1 /* Code for RTL transformations to satisfy insn constraints.
2 Copyright (C) 2010-2014 Free Software Foundation, Inc.
3 Contributed by Vladimir Makarov <vmakarov@redhat.com>.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 3, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
22 /* This file contains code for 3 passes: constraint pass,
23 inheritance/split pass, and pass for undoing failed inheritance and
26 The major goal of constraint pass is to transform RTL to satisfy
27 insn and address constraints by:
28 o choosing insn alternatives;
29 o generating *reload insns* (or reloads in brief) and *reload
30 pseudos* which will get necessary hard registers later;
31 o substituting pseudos with equivalent values and removing the
32 instructions that initialized those pseudos.
34 The constraint pass has biggest and most complicated code in LRA.
35 There are a lot of important details like:
36 o reuse of input reload pseudos to simplify reload pseudo
38 o some heuristics to choose insn alternative to improve the
42 The pass is mimicking former reload pass in alternative choosing
43 because the reload pass is oriented to current machine description
44 model. It might be changed if the machine description model is
47 There is special code for preventing all LRA and this pass cycling
50 On the first iteration of the pass we process every instruction and
51 choose an alternative for each one. On subsequent iterations we try
52 to avoid reprocessing instructions if we can be sure that the old
53 choice is still valid.
55 The inheritance/spilt pass is to transform code to achieve
56 ineheritance and live range splitting. It is done on backward
59 The inheritance optimization goal is to reuse values in hard
60 registers. There is analogous optimization in old reload pass. The
61 inheritance is achieved by following transformation:
63 reload_p1 <- p reload_p1 <- p
64 ... new_p <- reload_p1
66 reload_p2 <- p reload_p2 <- new_p
68 where p is spilled and not changed between the insns. Reload_p1 is
69 also called *original pseudo* and new_p is called *inheritance
72 The subsequent assignment pass will try to assign the same (or
73 another if it is not possible) hard register to new_p as to
74 reload_p1 or reload_p2.
76 If the assignment pass fails to assign a hard register to new_p,
77 this file will undo the inheritance and restore the original code.
78 This is because implementing the above sequence with a spilled
79 new_p would make the code much worse. The inheritance is done in
80 EBB scope. The above is just a simplified example to get an idea
81 of the inheritance as the inheritance is also done for non-reload
84 Splitting (transformation) is also done in EBB scope on the same
85 pass as the inheritance:
87 r <- ... or ... <- r r <- ... or ... <- r
88 ... s <- r (new insn -- save)
90 ... r <- s (new insn -- restore)
93 The *split pseudo* s is assigned to the hard register of the
94 original pseudo or hard register r.
97 o In EBBs with high register pressure for global pseudos (living
98 in at least 2 BBs) and assigned to hard registers when there
99 are more one reloads needing the hard registers;
100 o for pseudos needing save/restore code around calls.
102 If the split pseudo still has the same hard register as the
103 original pseudo after the subsequent assignment pass or the
104 original pseudo was split, the opposite transformation is done on
105 the same pass for undoing inheritance. */
111 #include "coretypes.h"
113 #include "hard-reg-set.h"
117 #include "insn-config.h"
118 #include "insn-codes.h"
121 #include "addresses.h"
123 #include "function.h"
125 #include "basic-block.h"
130 #include "rtl-error.h"
133 /* Value of LRA_CURR_RELOAD_NUM at the beginning of BB of the current
134 insn. Remember that LRA_CURR_RELOAD_NUM is the number of emitted
136 static int bb_reload_num
;
138 /* The current insn being processed and corresponding its single set
139 (NULL otherwise), its data (basic block, the insn data, the insn
140 static data, and the mode of each operand). */
141 static rtx curr_insn
;
142 static rtx curr_insn_set
;
143 static basic_block curr_bb
;
144 static lra_insn_recog_data_t curr_id
;
145 static struct lra_static_insn_data
*curr_static_id
;
146 static enum machine_mode curr_operand_mode
[MAX_RECOG_OPERANDS
];
150 /* Start numbers for new registers and insns at the current constraints
152 static int new_regno_start
;
153 static int new_insn_uid_start
;
155 /* If LOC is nonnull, strip any outer subreg from it. */
157 strip_subreg (rtx
*loc
)
159 return loc
&& GET_CODE (*loc
) == SUBREG
? &SUBREG_REG (*loc
) : loc
;
162 /* Return hard regno of REGNO or if it is was not assigned to a hard
163 register, use a hard register from its allocno class. */
165 get_try_hard_regno (int regno
)
168 enum reg_class rclass
;
170 if ((hard_regno
= regno
) >= FIRST_PSEUDO_REGISTER
)
171 hard_regno
= lra_get_regno_hard_regno (regno
);
174 rclass
= lra_get_allocno_class (regno
);
175 if (rclass
== NO_REGS
)
177 return ira_class_hard_regs
[rclass
][0];
180 /* Return final hard regno (plus offset) which will be after
181 elimination. We do this for matching constraints because the final
182 hard regno could have a different class. */
184 get_final_hard_regno (int hard_regno
, int offset
)
188 hard_regno
= lra_get_elimination_hard_regno (hard_regno
);
189 return hard_regno
+ offset
;
192 /* Return hard regno of X after removing subreg and making
193 elimination. If X is not a register or subreg of register, return
194 -1. For pseudo use its assignment. */
196 get_hard_regno (rtx x
)
199 int offset
, hard_regno
;
202 if (GET_CODE (x
) == SUBREG
)
203 reg
= SUBREG_REG (x
);
206 if ((hard_regno
= REGNO (reg
)) >= FIRST_PSEUDO_REGISTER
)
207 hard_regno
= lra_get_regno_hard_regno (hard_regno
);
211 if (GET_CODE (x
) == SUBREG
)
212 offset
+= subreg_regno_offset (hard_regno
, GET_MODE (reg
),
213 SUBREG_BYTE (x
), GET_MODE (x
));
214 return get_final_hard_regno (hard_regno
, offset
);
217 /* If REGNO is a hard register or has been allocated a hard register,
218 return the class of that register. If REGNO is a reload pseudo
219 created by the current constraints pass, return its allocno class.
220 Return NO_REGS otherwise. */
221 static enum reg_class
222 get_reg_class (int regno
)
226 if ((hard_regno
= regno
) >= FIRST_PSEUDO_REGISTER
)
227 hard_regno
= lra_get_regno_hard_regno (regno
);
230 hard_regno
= get_final_hard_regno (hard_regno
, 0);
231 return REGNO_REG_CLASS (hard_regno
);
233 if (regno
>= new_regno_start
)
234 return lra_get_allocno_class (regno
);
238 /* Return true if REG satisfies (or will satisfy) reg class constraint
239 CL. Use elimination first if REG is a hard register. If REG is a
240 reload pseudo created by this constraints pass, assume that it will
241 be allocated a hard register from its allocno class, but allow that
242 class to be narrowed to CL if it is currently a superset of CL.
244 If NEW_CLASS is nonnull, set *NEW_CLASS to the new allocno class of
245 REGNO (reg), or NO_REGS if no change in its class was needed. */
247 in_class_p (rtx reg
, enum reg_class cl
, enum reg_class
*new_class
)
249 enum reg_class rclass
, common_class
;
250 enum machine_mode reg_mode
;
251 int class_size
, hard_regno
, nregs
, i
, j
;
252 int regno
= REGNO (reg
);
254 if (new_class
!= NULL
)
255 *new_class
= NO_REGS
;
256 if (regno
< FIRST_PSEUDO_REGISTER
)
259 rtx
*final_loc
= &final_reg
;
261 lra_eliminate_reg_if_possible (final_loc
);
262 return TEST_HARD_REG_BIT (reg_class_contents
[cl
], REGNO (*final_loc
));
264 reg_mode
= GET_MODE (reg
);
265 rclass
= get_reg_class (regno
);
266 if (regno
< new_regno_start
267 /* Do not allow the constraints for reload instructions to
268 influence the classes of new pseudos. These reloads are
269 typically moves that have many alternatives, and restricting
270 reload pseudos for one alternative may lead to situations
271 where other reload pseudos are no longer allocatable. */
272 || (INSN_UID (curr_insn
) >= new_insn_uid_start
273 && curr_insn_set
!= NULL
274 && ((OBJECT_P (SET_SRC (curr_insn_set
))
275 && ! CONSTANT_P (SET_SRC (curr_insn_set
)))
276 || (GET_CODE (SET_SRC (curr_insn_set
)) == SUBREG
277 && OBJECT_P (SUBREG_REG (SET_SRC (curr_insn_set
)))
278 && ! CONSTANT_P (SUBREG_REG (SET_SRC (curr_insn_set
)))))))
279 /* When we don't know what class will be used finally for reload
280 pseudos, we use ALL_REGS. */
281 return ((regno
>= new_regno_start
&& rclass
== ALL_REGS
)
282 || (rclass
!= NO_REGS
&& ira_class_subset_p
[rclass
][cl
]
283 && ! hard_reg_set_subset_p (reg_class_contents
[cl
],
284 lra_no_alloc_regs
)));
287 common_class
= ira_reg_class_subset
[rclass
][cl
];
288 if (new_class
!= NULL
)
289 *new_class
= common_class
;
290 if (hard_reg_set_subset_p (reg_class_contents
[common_class
],
293 /* Check that there are enough allocatable regs. */
294 class_size
= ira_class_hard_regs_num
[common_class
];
295 for (i
= 0; i
< class_size
; i
++)
297 hard_regno
= ira_class_hard_regs
[common_class
][i
];
298 nregs
= hard_regno_nregs
[hard_regno
][reg_mode
];
301 for (j
= 0; j
< nregs
; j
++)
302 if (TEST_HARD_REG_BIT (lra_no_alloc_regs
, hard_regno
+ j
)
303 || ! TEST_HARD_REG_BIT (reg_class_contents
[common_class
],
313 /* Return true if REGNO satisfies a memory constraint. */
317 return get_reg_class (regno
) == NO_REGS
;
320 /* Initiate equivalences for LRA. As we keep original equivalences
321 before any elimination, we need to make copies otherwise any change
322 in insns might change the equivalences. */
324 lra_init_equiv (void)
326 ira_expand_reg_equiv ();
327 for (int i
= FIRST_PSEUDO_REGISTER
; i
< max_reg_num (); i
++)
331 if ((res
= ira_reg_equiv
[i
].memory
) != NULL_RTX
)
332 ira_reg_equiv
[i
].memory
= copy_rtx (res
);
333 if ((res
= ira_reg_equiv
[i
].invariant
) != NULL_RTX
)
334 ira_reg_equiv
[i
].invariant
= copy_rtx (res
);
338 static rtx
loc_equivalence_callback (rtx
, const_rtx
, void *);
340 /* Update equivalence for REGNO. We need to this as the equivalence
341 might contain other pseudos which are changed by their
344 update_equiv (int regno
)
348 if ((x
= ira_reg_equiv
[regno
].memory
) != NULL_RTX
)
349 ira_reg_equiv
[regno
].memory
350 = simplify_replace_fn_rtx (x
, NULL_RTX
, loc_equivalence_callback
,
352 if ((x
= ira_reg_equiv
[regno
].invariant
) != NULL_RTX
)
353 ira_reg_equiv
[regno
].invariant
354 = simplify_replace_fn_rtx (x
, NULL_RTX
, loc_equivalence_callback
,
358 /* If we have decided to substitute X with another value, return that
359 value, otherwise return X. */
366 if (! REG_P (x
) || (regno
= REGNO (x
)) < FIRST_PSEUDO_REGISTER
367 || ! ira_reg_equiv
[regno
].defined_p
368 || ! ira_reg_equiv
[regno
].profitable_p
369 || lra_get_regno_hard_regno (regno
) >= 0)
371 if ((res
= ira_reg_equiv
[regno
].memory
) != NULL_RTX
)
373 if ((res
= ira_reg_equiv
[regno
].constant
) != NULL_RTX
)
375 if ((res
= ira_reg_equiv
[regno
].invariant
) != NULL_RTX
)
380 /* If we have decided to substitute X with the equivalent value,
381 return that value after elimination for INSN, otherwise return
384 get_equiv_with_elimination (rtx x
, rtx insn
)
386 rtx res
= get_equiv (x
);
388 if (x
== res
|| CONSTANT_P (res
))
390 return lra_eliminate_regs_1 (insn
, res
, GET_MODE (res
), false, false, true);
393 /* Set up curr_operand_mode. */
395 init_curr_operand_mode (void)
397 int nop
= curr_static_id
->n_operands
;
398 for (int i
= 0; i
< nop
; i
++)
400 enum machine_mode mode
= GET_MODE (*curr_id
->operand_loc
[i
]);
401 if (mode
== VOIDmode
)
403 /* The .md mode for address operands is the mode of the
404 addressed value rather than the mode of the address itself. */
405 if (curr_id
->icode
>= 0 && curr_static_id
->operand
[i
].is_address
)
408 mode
= curr_static_id
->operand
[i
].mode
;
410 curr_operand_mode
[i
] = mode
;
416 /* The page contains code to reuse input reloads. */
418 /* Structure describes input reload of the current insns. */
421 /* Reloaded value. */
423 /* Reload pseudo used. */
427 /* The number of elements in the following array. */
428 static int curr_insn_input_reloads_num
;
429 /* Array containing info about input reloads. It is used to find the
430 same input reload and reuse the reload pseudo in this case. */
431 static struct input_reload curr_insn_input_reloads
[LRA_MAX_INSN_RELOADS
];
433 /* Initiate data concerning reuse of input reloads for the current
436 init_curr_insn_input_reloads (void)
438 curr_insn_input_reloads_num
= 0;
441 /* Create a new pseudo using MODE, RCLASS, ORIGINAL or reuse already
442 created input reload pseudo (only if TYPE is not OP_OUT). The
443 result pseudo is returned through RESULT_REG. Return TRUE if we
444 created a new pseudo, FALSE if we reused the already created input
445 reload pseudo. Use TITLE to describe new registers for debug
448 get_reload_reg (enum op_type type
, enum machine_mode mode
, rtx original
,
449 enum reg_class rclass
, const char *title
, rtx
*result_reg
)
452 enum reg_class new_class
;
457 = lra_create_new_reg_with_unique_value (mode
, original
, rclass
, title
);
460 /* Prevent reuse value of expression with side effects,
461 e.g. volatile memory. */
462 if (! side_effects_p (original
))
463 for (i
= 0; i
< curr_insn_input_reloads_num
; i
++)
464 if (rtx_equal_p (curr_insn_input_reloads
[i
].input
, original
)
465 && in_class_p (curr_insn_input_reloads
[i
].reg
, rclass
, &new_class
))
467 rtx reg
= curr_insn_input_reloads
[i
].reg
;
469 /* If input is equal to original and both are VOIDmode,
470 GET_MODE (reg) might be still different from mode.
471 Ensure we don't return *result_reg with wrong mode. */
472 if (GET_MODE (reg
) != mode
)
474 if (GET_MODE_SIZE (GET_MODE (reg
)) < GET_MODE_SIZE (mode
))
476 reg
= lowpart_subreg (mode
, reg
, GET_MODE (reg
));
477 if (reg
== NULL_RTX
|| GET_CODE (reg
) != SUBREG
)
481 if (lra_dump_file
!= NULL
)
483 fprintf (lra_dump_file
, " Reuse r%d for reload ", regno
);
484 dump_value_slim (lra_dump_file
, original
, 1);
486 if (new_class
!= lra_get_allocno_class (regno
))
487 lra_change_class (regno
, new_class
, ", change to", false);
488 if (lra_dump_file
!= NULL
)
489 fprintf (lra_dump_file
, "\n");
492 *result_reg
= lra_create_new_reg (mode
, original
, rclass
, title
);
493 lra_assert (curr_insn_input_reloads_num
< LRA_MAX_INSN_RELOADS
);
494 curr_insn_input_reloads
[curr_insn_input_reloads_num
].input
= original
;
495 curr_insn_input_reloads
[curr_insn_input_reloads_num
++].reg
= *result_reg
;
501 /* The page contains code to extract memory address parts. */
503 /* Wrapper around REGNO_OK_FOR_INDEX_P, to allow pseudos. */
505 ok_for_index_p_nonstrict (rtx reg
)
507 unsigned regno
= REGNO (reg
);
509 return regno
>= FIRST_PSEUDO_REGISTER
|| REGNO_OK_FOR_INDEX_P (regno
);
512 /* A version of regno_ok_for_base_p for use here, when all pseudos
513 should count as OK. Arguments as for regno_ok_for_base_p. */
515 ok_for_base_p_nonstrict (rtx reg
, enum machine_mode mode
, addr_space_t as
,
516 enum rtx_code outer_code
, enum rtx_code index_code
)
518 unsigned regno
= REGNO (reg
);
520 if (regno
>= FIRST_PSEUDO_REGISTER
)
522 return ok_for_base_p_1 (regno
, mode
, as
, outer_code
, index_code
);
527 /* The page contains major code to choose the current insn alternative
528 and generate reloads for it. */
530 /* Return the offset from REGNO of the least significant register
533 This function is used to tell whether two registers satisfy
534 a matching constraint. (reg:MODE1 REGNO1) matches (reg:MODE2 REGNO2) if:
536 REGNO1 + lra_constraint_offset (REGNO1, MODE1)
537 == REGNO2 + lra_constraint_offset (REGNO2, MODE2) */
539 lra_constraint_offset (int regno
, enum machine_mode mode
)
541 lra_assert (regno
< FIRST_PSEUDO_REGISTER
);
542 if (WORDS_BIG_ENDIAN
&& GET_MODE_SIZE (mode
) > UNITS_PER_WORD
543 && SCALAR_INT_MODE_P (mode
))
544 return hard_regno_nregs
[regno
][mode
] - 1;
548 /* Like rtx_equal_p except that it allows a REG and a SUBREG to match
549 if they are the same hard reg, and has special hacks for
550 auto-increment and auto-decrement. This is specifically intended for
551 process_alt_operands to use in determining whether two operands
552 match. X is the operand whose number is the lower of the two.
554 It is supposed that X is the output operand and Y is the input
555 operand. Y_HARD_REGNO is the final hard regno of register Y or
556 register in subreg Y as we know it now. Otherwise, it is a
559 operands_match_p (rtx x
, rtx y
, int y_hard_regno
)
562 RTX_CODE code
= GET_CODE (x
);
567 if ((code
== REG
|| (code
== SUBREG
&& REG_P (SUBREG_REG (x
))))
568 && (REG_P (y
) || (GET_CODE (y
) == SUBREG
&& REG_P (SUBREG_REG (y
)))))
572 i
= get_hard_regno (x
);
576 if ((j
= y_hard_regno
) < 0)
579 i
+= lra_constraint_offset (i
, GET_MODE (x
));
580 j
+= lra_constraint_offset (j
, GET_MODE (y
));
585 /* If two operands must match, because they are really a single
586 operand of an assembler insn, then two post-increments are invalid
587 because the assembler insn would increment only once. On the
588 other hand, a post-increment matches ordinary indexing if the
589 post-increment is the output operand. */
590 if (code
== POST_DEC
|| code
== POST_INC
|| code
== POST_MODIFY
)
591 return operands_match_p (XEXP (x
, 0), y
, y_hard_regno
);
593 /* Two pre-increments are invalid because the assembler insn would
594 increment only once. On the other hand, a pre-increment matches
595 ordinary indexing if the pre-increment is the input operand. */
596 if (GET_CODE (y
) == PRE_DEC
|| GET_CODE (y
) == PRE_INC
597 || GET_CODE (y
) == PRE_MODIFY
)
598 return operands_match_p (x
, XEXP (y
, 0), -1);
602 if (code
== REG
&& GET_CODE (y
) == SUBREG
&& REG_P (SUBREG_REG (y
))
603 && x
== SUBREG_REG (y
))
605 if (GET_CODE (y
) == REG
&& code
== SUBREG
&& REG_P (SUBREG_REG (x
))
606 && SUBREG_REG (x
) == y
)
609 /* Now we have disposed of all the cases in which different rtx
611 if (code
!= GET_CODE (y
))
614 /* (MULT:SI x y) and (MULT:HI x y) are NOT equivalent. */
615 if (GET_MODE (x
) != GET_MODE (y
))
624 return XEXP (x
, 0) == XEXP (y
, 0);
626 return XSTR (x
, 0) == XSTR (y
, 0);
632 /* Compare the elements. If any pair of corresponding elements fail
633 to match, return false for the whole things. */
635 fmt
= GET_RTX_FORMAT (code
);
636 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
642 if (XWINT (x
, i
) != XWINT (y
, i
))
647 if (XINT (x
, i
) != XINT (y
, i
))
652 val
= operands_match_p (XEXP (x
, i
), XEXP (y
, i
), -1);
661 if (XVECLEN (x
, i
) != XVECLEN (y
, i
))
663 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; --j
)
665 val
= operands_match_p (XVECEXP (x
, i
, j
), XVECEXP (y
, i
, j
), -1);
671 /* It is believed that rtx's at this level will never
672 contain anything but integers and other rtx's, except for
673 within LABEL_REFs and SYMBOL_REFs. */
681 /* True if X is a constant that can be forced into the constant pool.
682 MODE is the mode of the operand, or VOIDmode if not known. */
683 #define CONST_POOL_OK_P(MODE, X) \
684 ((MODE) != VOIDmode \
686 && GET_CODE (X) != HIGH \
687 && !targetm.cannot_force_const_mem (MODE, X))
689 /* True if C is a non-empty register class that has too few registers
690 to be safely used as a reload target class. */
691 #define SMALL_REGISTER_CLASS_P(C) \
692 (ira_class_hard_regs_num [(C)] == 1 \
693 || (ira_class_hard_regs_num [(C)] >= 1 \
694 && targetm.class_likely_spilled_p (C)))
696 /* If REG is a reload pseudo, try to make its class satisfying CL. */
698 narrow_reload_pseudo_class (rtx reg
, enum reg_class cl
)
700 enum reg_class rclass
;
702 /* Do not make more accurate class from reloads generated. They are
703 mostly moves with a lot of constraints. Making more accurate
704 class may results in very narrow class and impossibility of find
705 registers for several reloads of one insn. */
706 if (INSN_UID (curr_insn
) >= new_insn_uid_start
)
708 if (GET_CODE (reg
) == SUBREG
)
709 reg
= SUBREG_REG (reg
);
710 if (! REG_P (reg
) || (int) REGNO (reg
) < new_regno_start
)
712 if (in_class_p (reg
, cl
, &rclass
) && rclass
!= cl
)
713 lra_change_class (REGNO (reg
), rclass
, " Change to", true);
716 /* Generate reloads for matching OUT and INS (array of input operand
717 numbers with end marker -1) with reg class GOAL_CLASS. Add input
718 and output reloads correspondingly to the lists *BEFORE and *AFTER.
719 OUT might be negative. In this case we generate input reloads for
720 matched input operands INS. */
722 match_reload (signed char out
, signed char *ins
, enum reg_class goal_class
,
723 rtx
*before
, rtx
*after
)
726 rtx new_in_reg
, new_out_reg
, reg
, clobber
;
727 enum machine_mode inmode
, outmode
;
728 rtx in_rtx
= *curr_id
->operand_loc
[ins
[0]];
729 rtx out_rtx
= out
< 0 ? in_rtx
: *curr_id
->operand_loc
[out
];
731 inmode
= curr_operand_mode
[ins
[0]];
732 outmode
= out
< 0 ? inmode
: curr_operand_mode
[out
];
733 push_to_sequence (*before
);
734 if (inmode
!= outmode
)
736 if (GET_MODE_SIZE (inmode
) > GET_MODE_SIZE (outmode
))
739 = lra_create_new_reg_with_unique_value (inmode
, in_rtx
,
741 if (SCALAR_INT_MODE_P (inmode
))
742 new_out_reg
= gen_lowpart_SUBREG (outmode
, reg
);
744 new_out_reg
= gen_rtx_SUBREG (outmode
, reg
, 0);
745 LRA_SUBREG_P (new_out_reg
) = 1;
746 /* If the input reg is dying here, we can use the same hard
747 register for REG and IN_RTX. We do it only for original
748 pseudos as reload pseudos can die although original
749 pseudos still live where reload pseudos dies. */
750 if (REG_P (in_rtx
) && (int) REGNO (in_rtx
) < lra_new_regno_start
751 && find_regno_note (curr_insn
, REG_DEAD
, REGNO (in_rtx
)))
752 lra_assign_reg_val (REGNO (in_rtx
), REGNO (reg
));
757 = lra_create_new_reg_with_unique_value (outmode
, out_rtx
,
759 if (SCALAR_INT_MODE_P (outmode
))
760 new_in_reg
= gen_lowpart_SUBREG (inmode
, reg
);
762 new_in_reg
= gen_rtx_SUBREG (inmode
, reg
, 0);
763 /* NEW_IN_REG is non-paradoxical subreg. We don't want
764 NEW_OUT_REG living above. We add clobber clause for
765 this. This is just a temporary clobber. We can remove
766 it at the end of LRA work. */
767 clobber
= emit_clobber (new_out_reg
);
768 LRA_TEMP_CLOBBER_P (PATTERN (clobber
)) = 1;
769 LRA_SUBREG_P (new_in_reg
) = 1;
770 if (GET_CODE (in_rtx
) == SUBREG
)
772 rtx subreg_reg
= SUBREG_REG (in_rtx
);
774 /* If SUBREG_REG is dying here and sub-registers IN_RTX
775 and NEW_IN_REG are similar, we can use the same hard
776 register for REG and SUBREG_REG. */
777 if (REG_P (subreg_reg
)
778 && (int) REGNO (subreg_reg
) < lra_new_regno_start
779 && GET_MODE (subreg_reg
) == outmode
780 && SUBREG_BYTE (in_rtx
) == SUBREG_BYTE (new_in_reg
)
781 && find_regno_note (curr_insn
, REG_DEAD
, REGNO (subreg_reg
)))
782 lra_assign_reg_val (REGNO (subreg_reg
), REGNO (reg
));
788 /* Pseudos have values -- see comments for lra_reg_info.
789 Different pseudos with the same value do not conflict even if
790 they live in the same place. When we create a pseudo we
791 assign value of original pseudo (if any) from which we
792 created the new pseudo. If we create the pseudo from the
793 input pseudo, the new pseudo will no conflict with the input
794 pseudo which is wrong when the input pseudo lives after the
795 insn and as the new pseudo value is changed by the insn
796 output. Therefore we create the new pseudo from the output.
798 We cannot reuse the current output register because we might
799 have a situation like "a <- a op b", where the constraints
800 force the second input operand ("b") to match the output
801 operand ("a"). "b" must then be copied into a new register
802 so that it doesn't clobber the current value of "a". */
804 new_in_reg
= new_out_reg
805 = lra_create_new_reg_with_unique_value (outmode
, out_rtx
,
808 /* In operand can be got from transformations before processing insn
809 constraints. One example of such transformations is subreg
810 reloading (see function simplify_operand_subreg). The new
811 pseudos created by the transformations might have inaccurate
812 class (ALL_REGS) and we should make their classes more
814 narrow_reload_pseudo_class (in_rtx
, goal_class
);
815 lra_emit_move (copy_rtx (new_in_reg
), in_rtx
);
816 *before
= get_insns ();
818 for (i
= 0; (in
= ins
[i
]) >= 0; i
++)
821 (GET_MODE (*curr_id
->operand_loc
[in
]) == VOIDmode
822 || GET_MODE (new_in_reg
) == GET_MODE (*curr_id
->operand_loc
[in
]));
823 *curr_id
->operand_loc
[in
] = new_in_reg
;
825 lra_update_dups (curr_id
, ins
);
828 /* See a comment for the input operand above. */
829 narrow_reload_pseudo_class (out_rtx
, goal_class
);
830 if (find_reg_note (curr_insn
, REG_UNUSED
, out_rtx
) == NULL_RTX
)
833 lra_emit_move (out_rtx
, copy_rtx (new_out_reg
));
835 *after
= get_insns ();
838 *curr_id
->operand_loc
[out
] = new_out_reg
;
839 lra_update_dup (curr_id
, out
);
842 /* Return register class which is union of all reg classes in insn
843 constraint alternative string starting with P. */
844 static enum reg_class
845 reg_class_from_constraints (const char *p
)
848 enum reg_class op_class
= NO_REGS
;
851 switch ((c
= *p
, len
= CONSTRAINT_LEN (c
, p
)), c
)
858 op_class
= (reg_class_subunion
859 [op_class
][base_reg_class (VOIDmode
, ADDR_SPACE_GENERIC
,
865 op_class
= reg_class_subunion
[op_class
][GENERAL_REGS
];
869 if (REG_CLASS_FROM_CONSTRAINT (c
, p
) == NO_REGS
)
871 #ifdef EXTRA_CONSTRAINT_STR
872 if (EXTRA_ADDRESS_CONSTRAINT (c
, p
))
874 = (reg_class_subunion
875 [op_class
][base_reg_class (VOIDmode
, ADDR_SPACE_GENERIC
,
882 = reg_class_subunion
[op_class
][REG_CLASS_FROM_CONSTRAINT (c
, p
)];
885 while ((p
+= len
), c
);
889 /* If OP is a register, return the class of the register as per
890 get_reg_class, otherwise return NO_REGS. */
891 static inline enum reg_class
892 get_op_class (rtx op
)
894 return REG_P (op
) ? get_reg_class (REGNO (op
)) : NO_REGS
;
897 /* Return generated insn mem_pseudo:=val if TO_P or val:=mem_pseudo
898 otherwise. If modes of MEM_PSEUDO and VAL are different, use
899 SUBREG for VAL to make them equal. */
901 emit_spill_move (bool to_p
, rtx mem_pseudo
, rtx val
)
903 if (GET_MODE (mem_pseudo
) != GET_MODE (val
))
905 /* Usually size of mem_pseudo is greater than val size but in
906 rare cases it can be less as it can be defined by target
907 dependent macro HARD_REGNO_CALLER_SAVE_MODE. */
910 val
= gen_rtx_SUBREG (GET_MODE (mem_pseudo
),
911 GET_CODE (val
) == SUBREG
? SUBREG_REG (val
) : val
,
913 LRA_SUBREG_P (val
) = 1;
917 mem_pseudo
= gen_lowpart_SUBREG (GET_MODE (val
), mem_pseudo
);
918 LRA_SUBREG_P (mem_pseudo
) = 1;
922 ? gen_move_insn (mem_pseudo
, val
)
923 : gen_move_insn (val
, mem_pseudo
));
926 /* Process a special case insn (register move), return true if we
927 don't need to process it anymore. INSN should be a single set
928 insn. Set up that RTL was changed through CHANGE_P and macro
929 SECONDARY_MEMORY_NEEDED says to use secondary memory through
932 check_and_process_move (bool *change_p
, bool *sec_mem_p ATTRIBUTE_UNUSED
)
935 rtx dest
, src
, dreg
, sreg
, old_sreg
, new_reg
, before
, scratch_reg
;
936 enum reg_class dclass
, sclass
, secondary_class
;
937 enum machine_mode sreg_mode
;
938 secondary_reload_info sri
;
940 lra_assert (curr_insn_set
!= NULL_RTX
);
941 dreg
= dest
= SET_DEST (curr_insn_set
);
942 sreg
= src
= SET_SRC (curr_insn_set
);
943 if (GET_CODE (dest
) == SUBREG
)
944 dreg
= SUBREG_REG (dest
);
945 if (GET_CODE (src
) == SUBREG
)
946 sreg
= SUBREG_REG (src
);
947 if (! (REG_P (dreg
) || MEM_P (dreg
)) || ! (REG_P (sreg
) || MEM_P (sreg
)))
949 sclass
= dclass
= NO_REGS
;
951 dclass
= get_reg_class (REGNO (dreg
));
952 if (dclass
== ALL_REGS
)
953 /* ALL_REGS is used for new pseudos created by transformations
954 like reload of SUBREG_REG (see function
955 simplify_operand_subreg). We don't know their class yet. We
956 should figure out the class from processing the insn
957 constraints not in this fast path function. Even if ALL_REGS
958 were a right class for the pseudo, secondary_... hooks usually
959 are not define for ALL_REGS. */
961 sreg_mode
= GET_MODE (sreg
);
964 sclass
= get_reg_class (REGNO (sreg
));
965 if (sclass
== ALL_REGS
)
966 /* See comments above. */
968 if (sclass
== NO_REGS
&& dclass
== NO_REGS
)
970 #ifdef SECONDARY_MEMORY_NEEDED
971 if (SECONDARY_MEMORY_NEEDED (sclass
, dclass
, GET_MODE (src
))
972 #ifdef SECONDARY_MEMORY_NEEDED_MODE
973 && ((sclass
!= NO_REGS
&& dclass
!= NO_REGS
)
974 || GET_MODE (src
) != SECONDARY_MEMORY_NEEDED_MODE (GET_MODE (src
)))
982 if (! REG_P (dreg
) || ! REG_P (sreg
))
985 sri
.icode
= CODE_FOR_nothing
;
987 secondary_class
= NO_REGS
;
988 /* Set up hard register for a reload pseudo for hook
989 secondary_reload because some targets just ignore unassigned
990 pseudos in the hook. */
991 if (dclass
!= NO_REGS
&& lra_get_regno_hard_regno (REGNO (dreg
)) < 0)
993 dregno
= REGNO (dreg
);
994 reg_renumber
[dregno
] = ira_class_hard_regs
[dclass
][0];
998 if (sclass
!= NO_REGS
&& lra_get_regno_hard_regno (REGNO (sreg
)) < 0)
1000 sregno
= REGNO (sreg
);
1001 reg_renumber
[sregno
] = ira_class_hard_regs
[sclass
][0];
1005 if (sclass
!= NO_REGS
)
1007 = (enum reg_class
) targetm
.secondary_reload (false, dest
,
1008 (reg_class_t
) sclass
,
1009 GET_MODE (src
), &sri
);
1010 if (sclass
== NO_REGS
1011 || ((secondary_class
!= NO_REGS
|| sri
.icode
!= CODE_FOR_nothing
)
1012 && dclass
!= NO_REGS
))
1014 enum reg_class old_sclass
= secondary_class
;
1015 secondary_reload_info old_sri
= sri
;
1017 sri
.prev_sri
= NULL
;
1018 sri
.icode
= CODE_FOR_nothing
;
1021 = (enum reg_class
) targetm
.secondary_reload (true, sreg
,
1022 (reg_class_t
) dclass
,
1024 /* Check the target hook consistency. */
1026 ((secondary_class
== NO_REGS
&& sri
.icode
== CODE_FOR_nothing
)
1027 || (old_sclass
== NO_REGS
&& old_sri
.icode
== CODE_FOR_nothing
)
1028 || (secondary_class
== old_sclass
&& sri
.icode
== old_sri
.icode
));
1031 reg_renumber
[sregno
] = -1;
1033 reg_renumber
[dregno
] = -1;
1034 if (secondary_class
== NO_REGS
&& sri
.icode
== CODE_FOR_nothing
)
1038 if (secondary_class
!= NO_REGS
)
1039 new_reg
= lra_create_new_reg_with_unique_value (sreg_mode
, NULL_RTX
,
1043 if (old_sreg
!= sreg
)
1044 sreg
= copy_rtx (sreg
);
1045 if (sri
.icode
== CODE_FOR_nothing
)
1046 lra_emit_move (new_reg
, sreg
);
1049 enum reg_class scratch_class
;
1051 scratch_class
= (reg_class_from_constraints
1052 (insn_data
[sri
.icode
].operand
[2].constraint
));
1053 scratch_reg
= (lra_create_new_reg_with_unique_value
1054 (insn_data
[sri
.icode
].operand
[2].mode
, NULL_RTX
,
1055 scratch_class
, "scratch"));
1056 emit_insn (GEN_FCN (sri
.icode
) (new_reg
!= NULL_RTX
? new_reg
: dest
,
1057 sreg
, scratch_reg
));
1059 before
= get_insns ();
1061 lra_process_new_insns (curr_insn
, before
, NULL_RTX
, "Inserting the move");
1062 if (new_reg
!= NULL_RTX
)
1064 if (GET_CODE (src
) == SUBREG
)
1065 SUBREG_REG (src
) = new_reg
;
1067 SET_SRC (curr_insn_set
) = new_reg
;
1071 if (lra_dump_file
!= NULL
)
1073 fprintf (lra_dump_file
, "Deleting move %u\n", INSN_UID (curr_insn
));
1074 dump_insn_slim (lra_dump_file
, curr_insn
);
1076 lra_set_insn_deleted (curr_insn
);
1082 /* The following data describe the result of process_alt_operands.
1083 The data are used in curr_insn_transform to generate reloads. */
1085 /* The chosen reg classes which should be used for the corresponding
1087 static enum reg_class goal_alt
[MAX_RECOG_OPERANDS
];
1088 /* True if the operand should be the same as another operand and that
1089 other operand does not need a reload. */
1090 static bool goal_alt_match_win
[MAX_RECOG_OPERANDS
];
1091 /* True if the operand does not need a reload. */
1092 static bool goal_alt_win
[MAX_RECOG_OPERANDS
];
1093 /* True if the operand can be offsetable memory. */
1094 static bool goal_alt_offmemok
[MAX_RECOG_OPERANDS
];
1095 /* The number of an operand to which given operand can be matched to. */
1096 static int goal_alt_matches
[MAX_RECOG_OPERANDS
];
1097 /* The number of elements in the following array. */
1098 static int goal_alt_dont_inherit_ops_num
;
1099 /* Numbers of operands whose reload pseudos should not be inherited. */
1100 static int goal_alt_dont_inherit_ops
[MAX_RECOG_OPERANDS
];
1101 /* True if the insn commutative operands should be swapped. */
1102 static bool goal_alt_swapped
;
1103 /* The chosen insn alternative. */
1104 static int goal_alt_number
;
1106 /* The following five variables are used to choose the best insn
1107 alternative. They reflect final characteristics of the best
1110 /* Number of necessary reloads and overall cost reflecting the
1111 previous value and other unpleasantness of the best alternative. */
1112 static int best_losers
, best_overall
;
1113 /* Overall number hard registers used for reloads. For example, on
1114 some targets we need 2 general registers to reload DFmode and only
1115 one floating point register. */
1116 static int best_reload_nregs
;
1117 /* Overall number reflecting distances of previous reloading the same
1118 value. The distances are counted from the current BB start. It is
1119 used to improve inheritance chances. */
1120 static int best_reload_sum
;
1122 /* True if the current insn should have no correspondingly input or
1124 static bool no_input_reloads_p
, no_output_reloads_p
;
1126 /* True if we swapped the commutative operands in the current
1128 static int curr_swapped
;
1130 /* Arrange for address element *LOC to be a register of class CL.
1131 Add any input reloads to list BEFORE. AFTER is nonnull if *LOC is an
1132 automodified value; handle that case by adding the required output
1133 reloads to list AFTER. Return true if the RTL was changed. */
1135 process_addr_reg (rtx
*loc
, rtx
*before
, rtx
*after
, enum reg_class cl
)
1138 enum reg_class rclass
, new_class
;
1141 enum machine_mode mode
;
1142 bool before_p
= false;
1144 loc
= strip_subreg (loc
);
1146 mode
= GET_MODE (reg
);
1149 /* Always reload memory in an address even if the target supports
1151 new_reg
= lra_create_new_reg_with_unique_value (mode
, reg
, cl
, "address");
1156 regno
= REGNO (reg
);
1157 rclass
= get_reg_class (regno
);
1158 if ((*loc
= get_equiv_with_elimination (reg
, curr_insn
)) != reg
)
1160 if (lra_dump_file
!= NULL
)
1162 fprintf (lra_dump_file
,
1163 "Changing pseudo %d in address of insn %u on equiv ",
1164 REGNO (reg
), INSN_UID (curr_insn
));
1165 dump_value_slim (lra_dump_file
, *loc
, 1);
1166 fprintf (lra_dump_file
, "\n");
1168 *loc
= copy_rtx (*loc
);
1170 if (*loc
!= reg
|| ! in_class_p (reg
, cl
, &new_class
))
1173 if (get_reload_reg (after
== NULL
? OP_IN
: OP_INOUT
,
1174 mode
, reg
, cl
, "address", &new_reg
))
1177 else if (new_class
!= NO_REGS
&& rclass
!= new_class
)
1179 lra_change_class (regno
, new_class
, " Change to", true);
1187 push_to_sequence (*before
);
1188 lra_emit_move (new_reg
, reg
);
1189 *before
= get_insns ();
1196 lra_emit_move (reg
, new_reg
);
1198 *after
= get_insns ();
1204 /* Insert move insn in simplify_operand_subreg. BEFORE returns
1205 the insn to be inserted before curr insn. AFTER returns the
1206 the insn to be inserted after curr insn. ORIGREG and NEWREG
1207 are the original reg and new reg for reload. */
1209 insert_move_for_subreg (rtx
*before
, rtx
*after
, rtx origreg
, rtx newreg
)
1213 push_to_sequence (*before
);
1214 lra_emit_move (newreg
, origreg
);
1215 *before
= get_insns ();
1221 lra_emit_move (origreg
, newreg
);
1223 *after
= get_insns ();
1228 /* Make reloads for subreg in operand NOP with internal subreg mode
1229 REG_MODE, add new reloads for further processing. Return true if
1230 any reload was generated. */
1232 simplify_operand_subreg (int nop
, enum machine_mode reg_mode
)
1236 enum machine_mode mode
;
1238 rtx operand
= *curr_id
->operand_loc
[nop
];
1239 enum reg_class regclass
;
1242 before
= after
= NULL_RTX
;
1244 if (GET_CODE (operand
) != SUBREG
)
1247 mode
= GET_MODE (operand
);
1248 reg
= SUBREG_REG (operand
);
1249 type
= curr_static_id
->operand
[nop
].type
;
1250 /* If we change address for paradoxical subreg of memory, the
1251 address might violate the necessary alignment or the access might
1252 be slow. So take this into consideration. We should not worry
1253 about access beyond allocated memory for paradoxical memory
1254 subregs as we don't substitute such equiv memory (see processing
1255 equivalences in function lra_constraints) and because for spilled
1256 pseudos we allocate stack memory enough for the biggest
1257 corresponding paradoxical subreg. */
1259 && (! SLOW_UNALIGNED_ACCESS (mode
, MEM_ALIGN (reg
))
1260 || MEM_ALIGN (reg
) >= GET_MODE_ALIGNMENT (mode
)))
1261 || (REG_P (reg
) && REGNO (reg
) < FIRST_PSEUDO_REGISTER
))
1263 alter_subreg (curr_id
->operand_loc
[nop
], false);
1266 /* Put constant into memory when we have mixed modes. It generates
1267 a better code in most cases as it does not need a secondary
1268 reload memory. It also prevents LRA looping when LRA is using
1269 secondary reload memory again and again. */
1270 if (CONSTANT_P (reg
) && CONST_POOL_OK_P (reg_mode
, reg
)
1271 && SCALAR_INT_MODE_P (reg_mode
) != SCALAR_INT_MODE_P (mode
))
1273 SUBREG_REG (operand
) = force_const_mem (reg_mode
, reg
);
1274 alter_subreg (curr_id
->operand_loc
[nop
], false);
1277 /* Force a reload of the SUBREG_REG if this is a constant or PLUS or
1278 if there may be a problem accessing OPERAND in the outer
1281 && REGNO (reg
) >= FIRST_PSEUDO_REGISTER
1282 && (hard_regno
= lra_get_regno_hard_regno (REGNO (reg
))) >= 0
1283 /* Don't reload paradoxical subregs because we could be looping
1284 having repeatedly final regno out of hard regs range. */
1285 && (hard_regno_nregs
[hard_regno
][GET_MODE (reg
)]
1286 >= hard_regno_nregs
[hard_regno
][mode
])
1287 && simplify_subreg_regno (hard_regno
, GET_MODE (reg
),
1288 SUBREG_BYTE (operand
), mode
) < 0
1289 /* Don't reload subreg for matching reload. It is actually
1290 valid subreg in LRA. */
1291 && ! LRA_SUBREG_P (operand
))
1292 || CONSTANT_P (reg
) || GET_CODE (reg
) == PLUS
|| MEM_P (reg
))
1294 /* The class will be defined later in curr_insn_transform. */
1295 enum reg_class rclass
1296 = (enum reg_class
) targetm
.preferred_reload_class (reg
, ALL_REGS
);
1298 if (get_reload_reg (curr_static_id
->operand
[nop
].type
, reg_mode
, reg
,
1299 rclass
, "subreg reg", &new_reg
))
1301 bool insert_before
, insert_after
;
1302 bitmap_set_bit (&lra_subreg_reload_pseudos
, REGNO (new_reg
));
1304 insert_before
= (type
!= OP_OUT
1305 || GET_MODE_SIZE (GET_MODE (reg
)) > GET_MODE_SIZE (mode
));
1306 insert_after
= (type
!= OP_IN
);
1307 insert_move_for_subreg (insert_before
? &before
: NULL
,
1308 insert_after
? &after
: NULL
,
1311 SUBREG_REG (operand
) = new_reg
;
1312 lra_process_new_insns (curr_insn
, before
, after
,
1313 "Inserting subreg reload");
1316 /* Force a reload for a paradoxical subreg. For paradoxical subreg,
1317 IRA allocates hardreg to the inner pseudo reg according to its mode
1318 instead of the outermode, so the size of the hardreg may not be enough
1319 to contain the outermode operand, in that case we may need to insert
1320 reload for the reg. For the following two types of paradoxical subreg,
1321 we need to insert reload:
1322 1. If the op_type is OP_IN, and the hardreg could not be paired with
1323 other hardreg to contain the outermode operand
1324 (checked by in_hard_reg_set_p), we need to insert the reload.
1325 2. If the op_type is OP_OUT or OP_INOUT.
1327 Here is a paradoxical subreg example showing how the reload is generated:
1329 (insn 5 4 7 2 (set (reg:TI 106 [ __comp ])
1330 (subreg:TI (reg:DI 107 [ __comp ]) 0)) {*movti_internal_rex64}
1332 In IRA, reg107 is allocated to a DImode hardreg. We use x86-64 as example
1333 here, if reg107 is assigned to hardreg R15, because R15 is the last
1334 hardreg, compiler cannot find another hardreg to pair with R15 to
1335 contain TImode data. So we insert a TImode reload reg180 for it.
1336 After reload is inserted:
1338 (insn 283 0 0 (set (subreg:DI (reg:TI 180 [orig:107 __comp ] [107]) 0)
1339 (reg:DI 107 [ __comp ])) -1
1340 (insn 5 4 7 2 (set (reg:TI 106 [ __comp ])
1341 (subreg:TI (reg:TI 180 [orig:107 __comp ] [107]) 0)) {*movti_internal_rex64}
1343 Two reload hard registers will be allocated to reg180 to save TImode data
1345 else if (REG_P (reg
)
1346 && REGNO (reg
) >= FIRST_PSEUDO_REGISTER
1347 && (hard_regno
= lra_get_regno_hard_regno (REGNO (reg
))) >= 0
1348 && (hard_regno_nregs
[hard_regno
][GET_MODE (reg
)]
1349 < hard_regno_nregs
[hard_regno
][mode
])
1350 && (regclass
= lra_get_allocno_class (REGNO (reg
)))
1352 || !in_hard_reg_set_p (reg_class_contents
[regclass
],
1355 /* The class will be defined later in curr_insn_transform. */
1356 enum reg_class rclass
1357 = (enum reg_class
) targetm
.preferred_reload_class (reg
, ALL_REGS
);
1359 if (get_reload_reg (curr_static_id
->operand
[nop
].type
, mode
, reg
,
1360 rclass
, "paradoxical subreg", &new_reg
))
1363 bool insert_before
, insert_after
;
1365 PUT_MODE (new_reg
, mode
);
1366 subreg
= simplify_gen_subreg (GET_MODE (reg
), new_reg
, mode
, 0);
1367 bitmap_set_bit (&lra_subreg_reload_pseudos
, REGNO (new_reg
));
1369 insert_before
= (type
!= OP_OUT
);
1370 insert_after
= (type
!= OP_IN
);
1371 insert_move_for_subreg (insert_before
? &before
: NULL
,
1372 insert_after
? &after
: NULL
,
1375 SUBREG_REG (operand
) = new_reg
;
1376 lra_process_new_insns (curr_insn
, before
, after
,
1377 "Inserting paradoxical subreg reload");
1383 /* Return TRUE if X refers for a hard register from SET. */
1385 uses_hard_regs_p (rtx x
, HARD_REG_SET set
)
1387 int i
, j
, x_hard_regno
;
1388 enum machine_mode mode
;
1394 code
= GET_CODE (x
);
1395 mode
= GET_MODE (x
);
1399 code
= GET_CODE (x
);
1400 if (GET_MODE_SIZE (GET_MODE (x
)) > GET_MODE_SIZE (mode
))
1401 mode
= GET_MODE (x
);
1406 x_hard_regno
= get_hard_regno (x
);
1407 return (x_hard_regno
>= 0
1408 && overlaps_hard_reg_set_p (set
, mode
, x_hard_regno
));
1412 struct address_info ad
;
1414 decompose_mem_address (&ad
, x
);
1415 if (ad
.base_term
!= NULL
&& uses_hard_regs_p (*ad
.base_term
, set
))
1417 if (ad
.index_term
!= NULL
&& uses_hard_regs_p (*ad
.index_term
, set
))
1420 fmt
= GET_RTX_FORMAT (code
);
1421 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
1425 if (uses_hard_regs_p (XEXP (x
, i
), set
))
1428 else if (fmt
[i
] == 'E')
1430 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
1431 if (uses_hard_regs_p (XVECEXP (x
, i
, j
), set
))
1438 /* Return true if OP is a spilled pseudo. */
1440 spilled_pseudo_p (rtx op
)
1443 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
&& in_mem_p (REGNO (op
)));
1446 /* Return true if X is a general constant. */
1448 general_constant_p (rtx x
)
1450 return CONSTANT_P (x
) && (! flag_pic
|| LEGITIMATE_PIC_OPERAND_P (x
));
1454 reg_in_class_p (rtx reg
, enum reg_class cl
)
1457 return get_reg_class (REGNO (reg
)) == NO_REGS
;
1458 return in_class_p (reg
, cl
, NULL
);
1461 /* Major function to choose the current insn alternative and what
1462 operands should be reloaded and how. If ONLY_ALTERNATIVE is not
1463 negative we should consider only this alternative. Return false if
1464 we can not choose the alternative or find how to reload the
1467 process_alt_operands (int only_alternative
)
1470 int nop
, overall
, nalt
;
1471 int n_alternatives
= curr_static_id
->n_alternatives
;
1472 int n_operands
= curr_static_id
->n_operands
;
1473 /* LOSERS counts the operands that don't fit this alternative and
1474 would require loading. */
1476 /* REJECT is a count of how undesirable this alternative says it is
1477 if any reloading is required. If the alternative matches exactly
1478 then REJECT is ignored, but otherwise it gets this much counted
1479 against it in addition to the reloading needed. */
1481 /* The number of elements in the following array. */
1482 int early_clobbered_regs_num
;
1483 /* Numbers of operands which are early clobber registers. */
1484 int early_clobbered_nops
[MAX_RECOG_OPERANDS
];
1485 enum reg_class curr_alt
[MAX_RECOG_OPERANDS
];
1486 HARD_REG_SET curr_alt_set
[MAX_RECOG_OPERANDS
];
1487 bool curr_alt_match_win
[MAX_RECOG_OPERANDS
];
1488 bool curr_alt_win
[MAX_RECOG_OPERANDS
];
1489 bool curr_alt_offmemok
[MAX_RECOG_OPERANDS
];
1490 int curr_alt_matches
[MAX_RECOG_OPERANDS
];
1491 /* The number of elements in the following array. */
1492 int curr_alt_dont_inherit_ops_num
;
1493 /* Numbers of operands whose reload pseudos should not be inherited. */
1494 int curr_alt_dont_inherit_ops
[MAX_RECOG_OPERANDS
];
1496 /* The register when the operand is a subreg of register, otherwise the
1498 rtx no_subreg_reg_operand
[MAX_RECOG_OPERANDS
];
1499 /* The register if the operand is a register or subreg of register,
1501 rtx operand_reg
[MAX_RECOG_OPERANDS
];
1502 int hard_regno
[MAX_RECOG_OPERANDS
];
1503 enum machine_mode biggest_mode
[MAX_RECOG_OPERANDS
];
1504 int reload_nregs
, reload_sum
;
1508 /* Calculate some data common for all alternatives to speed up the
1510 for (nop
= 0; nop
< n_operands
; nop
++)
1514 op
= no_subreg_reg_operand
[nop
] = *curr_id
->operand_loc
[nop
];
1515 /* The real hard regno of the operand after the allocation. */
1516 hard_regno
[nop
] = get_hard_regno (op
);
1518 operand_reg
[nop
] = reg
= op
;
1519 biggest_mode
[nop
] = GET_MODE (op
);
1520 if (GET_CODE (op
) == SUBREG
)
1522 operand_reg
[nop
] = reg
= SUBREG_REG (op
);
1523 if (GET_MODE_SIZE (biggest_mode
[nop
])
1524 < GET_MODE_SIZE (GET_MODE (reg
)))
1525 biggest_mode
[nop
] = GET_MODE (reg
);
1528 operand_reg
[nop
] = NULL_RTX
;
1529 else if (REGNO (reg
) >= FIRST_PSEUDO_REGISTER
1530 || ((int) REGNO (reg
)
1531 == lra_get_elimination_hard_regno (REGNO (reg
))))
1532 no_subreg_reg_operand
[nop
] = reg
;
1534 operand_reg
[nop
] = no_subreg_reg_operand
[nop
]
1535 /* Just use natural mode for elimination result. It should
1536 be enough for extra constraints hooks. */
1537 = regno_reg_rtx
[hard_regno
[nop
]];
1540 /* The constraints are made of several alternatives. Each operand's
1541 constraint looks like foo,bar,... with commas separating the
1542 alternatives. The first alternatives for all operands go
1543 together, the second alternatives go together, etc.
1545 First loop over alternatives. */
1546 for (nalt
= 0; nalt
< n_alternatives
; nalt
++)
1548 /* Loop over operands for one constraint alternative. */
1549 #if HAVE_ATTR_enabled
1550 if (curr_id
->alternative_enabled_p
!= NULL
1551 && ! curr_id
->alternative_enabled_p
[nalt
])
1555 if (only_alternative
>= 0 && nalt
!= only_alternative
)
1559 overall
= losers
= reject
= reload_nregs
= reload_sum
= 0;
1560 for (nop
= 0; nop
< n_operands
; nop
++)
1562 int inc
= (curr_static_id
1563 ->operand_alternative
[nalt
* n_operands
+ nop
].reject
);
1564 if (lra_dump_file
!= NULL
&& inc
!= 0)
1565 fprintf (lra_dump_file
,
1566 " Staticly defined alt reject+=%d\n", inc
);
1569 early_clobbered_regs_num
= 0;
1571 for (nop
= 0; nop
< n_operands
; nop
++)
1575 int len
, c
, m
, i
, opalt_num
, this_alternative_matches
;
1576 bool win
, did_match
, offmemok
, early_clobber_p
;
1577 /* false => this operand can be reloaded somehow for this
1580 /* true => this operand can be reloaded if the alternative
1583 /* True if a constant forced into memory would be OK for
1586 enum reg_class this_alternative
, this_costly_alternative
;
1587 HARD_REG_SET this_alternative_set
, this_costly_alternative_set
;
1588 bool this_alternative_match_win
, this_alternative_win
;
1589 bool this_alternative_offmemok
;
1591 enum machine_mode mode
;
1593 opalt_num
= nalt
* n_operands
+ nop
;
1594 if (curr_static_id
->operand_alternative
[opalt_num
].anything_ok
)
1596 /* Fast track for no constraints at all. */
1597 curr_alt
[nop
] = NO_REGS
;
1598 CLEAR_HARD_REG_SET (curr_alt_set
[nop
]);
1599 curr_alt_win
[nop
] = true;
1600 curr_alt_match_win
[nop
] = false;
1601 curr_alt_offmemok
[nop
] = false;
1602 curr_alt_matches
[nop
] = -1;
1606 op
= no_subreg_reg_operand
[nop
];
1607 mode
= curr_operand_mode
[nop
];
1609 win
= did_match
= winreg
= offmemok
= constmemok
= false;
1612 early_clobber_p
= false;
1613 p
= curr_static_id
->operand_alternative
[opalt_num
].constraint
;
1615 this_costly_alternative
= this_alternative
= NO_REGS
;
1616 /* We update set of possible hard regs besides its class
1617 because reg class might be inaccurate. For example,
1618 union of LO_REGS (l), HI_REGS(h), and STACK_REG(k) in ARM
1619 is translated in HI_REGS because classes are merged by
1620 pairs and there is no accurate intermediate class. */
1621 CLEAR_HARD_REG_SET (this_alternative_set
);
1622 CLEAR_HARD_REG_SET (this_costly_alternative_set
);
1623 this_alternative_win
= false;
1624 this_alternative_match_win
= false;
1625 this_alternative_offmemok
= false;
1626 this_alternative_matches
= -1;
1628 /* An empty constraint should be excluded by the fast
1630 lra_assert (*p
!= 0 && *p
!= ',');
1632 /* Scan this alternative's specs for this operand; set WIN
1633 if the operand fits any letter in this alternative.
1634 Otherwise, clear BADOP if this operand could fit some
1635 letter after reloads, or set WINREG if this operand could
1636 fit after reloads provided the constraint allows some
1641 switch ((c
= *p
, len
= CONSTRAINT_LEN (c
, p
)), c
)
1650 case '=': case '+': case '?': case '*': case '!':
1651 case ' ': case '\t':
1655 /* We only support one commutative marker, the first
1656 one. We already set commutative above. */
1660 early_clobber_p
= true;
1664 /* Ignore rest of this alternative. */
1668 case '0': case '1': case '2': case '3': case '4':
1669 case '5': case '6': case '7': case '8': case '9':
1674 m
= strtoul (p
, &end
, 10);
1677 lra_assert (nop
> m
);
1679 this_alternative_matches
= m
;
1680 m_hregno
= get_hard_regno (*curr_id
->operand_loc
[m
]);
1681 /* We are supposed to match a previous operand.
1682 If we do, we win if that one did. If we do
1683 not, count both of the operands as losers.
1684 (This is too conservative, since most of the
1685 time only a single reload insn will be needed
1686 to make the two operands win. As a result,
1687 this alternative may be rejected when it is
1688 actually desirable.) */
1690 if (operands_match_p (*curr_id
->operand_loc
[nop
],
1691 *curr_id
->operand_loc
[m
], m_hregno
))
1693 /* We should reject matching of an early
1694 clobber operand if the matching operand is
1695 not dying in the insn. */
1696 if (! curr_static_id
->operand
[m
].early_clobber
1697 || operand_reg
[nop
] == NULL_RTX
1698 || (find_regno_note (curr_insn
, REG_DEAD
,
1700 || REGNO (op
) == REGNO (operand_reg
[m
])))
1705 /* If we are matching a non-offsettable
1706 address where an offsettable address was
1707 expected, then we must reject this
1708 combination, because we can't reload
1710 if (curr_alt_offmemok
[m
]
1711 && MEM_P (*curr_id
->operand_loc
[m
])
1712 && curr_alt
[m
] == NO_REGS
&& ! curr_alt_win
[m
])
1717 /* Operands don't match. Both operands must
1718 allow a reload register, otherwise we
1719 cannot make them match. */
1720 if (curr_alt
[m
] == NO_REGS
)
1722 /* Retroactively mark the operand we had to
1723 match as a loser, if it wasn't already and
1724 it wasn't matched to a register constraint
1725 (e.g it might be matched by memory). */
1727 && (operand_reg
[m
] == NULL_RTX
1728 || hard_regno
[m
] < 0))
1732 += (ira_reg_class_max_nregs
[curr_alt
[m
]]
1733 [GET_MODE (*curr_id
->operand_loc
[m
])]);
1736 /* We prefer no matching alternatives because
1737 it gives more freedom in RA. */
1738 if (operand_reg
[nop
] == NULL_RTX
1739 || (find_regno_note (curr_insn
, REG_DEAD
,
1740 REGNO (operand_reg
[nop
]))
1743 if (lra_dump_file
!= NULL
)
1746 " %d Matching alt: reject+=2\n",
1751 /* If we have to reload this operand and some
1752 previous operand also had to match the same
1753 thing as this operand, we don't know how to do
1755 if (!match_p
|| !curr_alt_win
[m
])
1757 for (i
= 0; i
< nop
; i
++)
1758 if (curr_alt_matches
[i
] == m
)
1766 /* This can be fixed with reloads if the operand
1767 we are supposed to match can be fixed with
1770 this_alternative
= curr_alt
[m
];
1771 COPY_HARD_REG_SET (this_alternative_set
, curr_alt_set
[m
]);
1772 winreg
= this_alternative
!= NO_REGS
;
1777 cl
= base_reg_class (VOIDmode
, ADDR_SPACE_GENERIC
,
1779 this_alternative
= reg_class_subunion
[this_alternative
][cl
];
1780 IOR_HARD_REG_SET (this_alternative_set
,
1781 reg_class_contents
[cl
]);
1784 this_costly_alternative
1785 = reg_class_subunion
[this_costly_alternative
][cl
];
1786 IOR_HARD_REG_SET (this_costly_alternative_set
,
1787 reg_class_contents
[cl
]);
1793 case TARGET_MEM_CONSTRAINT
:
1794 if (MEM_P (op
) || spilled_pseudo_p (op
))
1796 /* We can put constant or pseudo value into memory
1797 to satisfy the constraint. */
1798 if (CONST_POOL_OK_P (mode
, op
) || REG_P (op
))
1805 && (GET_CODE (XEXP (op
, 0)) == PRE_DEC
1806 || GET_CODE (XEXP (op
, 0)) == POST_DEC
))
1812 && (GET_CODE (XEXP (op
, 0)) == PRE_INC
1813 || GET_CODE (XEXP (op
, 0)) == POST_INC
))
1817 /* Memory op whose address is not offsettable. */
1820 && ! offsettable_nonstrict_memref_p (op
))
1824 /* Memory operand whose address is offsettable. */
1827 && offsettable_nonstrict_memref_p (op
))
1828 || spilled_pseudo_p (op
))
1830 /* We can put constant or pseudo value into memory
1831 or make memory address offsetable to satisfy the
1833 if (CONST_POOL_OK_P (mode
, op
) || MEM_P (op
) || REG_P (op
))
1841 if (GET_CODE (op
) == CONST_DOUBLE
1842 || (GET_CODE (op
) == CONST_VECTOR
1843 && (GET_MODE_CLASS (mode
) == MODE_VECTOR_FLOAT
)))
1849 if (CONST_DOUBLE_AS_FLOAT_P (op
)
1850 && CONST_DOUBLE_OK_FOR_CONSTRAINT_P (op
, c
, p
))
1855 if (CONST_SCALAR_INT_P (op
))
1859 if (general_constant_p (op
))
1864 if (CONST_SCALAR_INT_P (op
))
1876 if (CONST_INT_P (op
)
1877 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op
), c
, p
))
1882 /* This constraint should be excluded by the fast
1889 || general_constant_p (op
)
1890 || spilled_pseudo_p (op
))
1892 /* Drop through into 'r' case. */
1896 = reg_class_subunion
[this_alternative
][GENERAL_REGS
];
1897 IOR_HARD_REG_SET (this_alternative_set
,
1898 reg_class_contents
[GENERAL_REGS
]);
1901 this_costly_alternative
1902 = (reg_class_subunion
1903 [this_costly_alternative
][GENERAL_REGS
]);
1904 IOR_HARD_REG_SET (this_costly_alternative_set
,
1905 reg_class_contents
[GENERAL_REGS
]);
1910 if (REG_CLASS_FROM_CONSTRAINT (c
, p
) == NO_REGS
)
1912 #ifdef EXTRA_CONSTRAINT_STR
1913 if (EXTRA_MEMORY_CONSTRAINT (c
, p
))
1915 if (EXTRA_CONSTRAINT_STR (op
, c
, p
))
1917 else if (spilled_pseudo_p (op
))
1920 /* If we didn't already win, we can reload
1921 constants via force_const_mem or put the
1922 pseudo value into memory, or make other
1923 memory by reloading the address like for
1925 if (CONST_POOL_OK_P (mode
, op
)
1926 || MEM_P (op
) || REG_P (op
))
1932 if (EXTRA_ADDRESS_CONSTRAINT (c
, p
))
1934 if (EXTRA_CONSTRAINT_STR (op
, c
, p
))
1937 /* If we didn't already win, we can reload
1938 the address into a base register. */
1939 cl
= base_reg_class (VOIDmode
, ADDR_SPACE_GENERIC
,
1942 = reg_class_subunion
[this_alternative
][cl
];
1943 IOR_HARD_REG_SET (this_alternative_set
,
1944 reg_class_contents
[cl
]);
1947 this_costly_alternative
1948 = (reg_class_subunion
1949 [this_costly_alternative
][cl
]);
1950 IOR_HARD_REG_SET (this_costly_alternative_set
,
1951 reg_class_contents
[cl
]);
1957 if (EXTRA_CONSTRAINT_STR (op
, c
, p
))
1963 cl
= REG_CLASS_FROM_CONSTRAINT (c
, p
);
1964 this_alternative
= reg_class_subunion
[this_alternative
][cl
];
1965 IOR_HARD_REG_SET (this_alternative_set
,
1966 reg_class_contents
[cl
]);
1969 this_costly_alternative
1970 = reg_class_subunion
[this_costly_alternative
][cl
];
1971 IOR_HARD_REG_SET (this_costly_alternative_set
,
1972 reg_class_contents
[cl
]);
1975 if (mode
== BLKmode
)
1980 if (hard_regno
[nop
] >= 0
1981 && in_hard_reg_set_p (this_alternative_set
,
1982 mode
, hard_regno
[nop
]))
1984 else if (hard_regno
[nop
] < 0
1985 && in_class_p (op
, this_alternative
, NULL
))
1990 if (c
!= ' ' && c
!= '\t')
1991 costly_p
= c
== '*';
1993 while ((p
+= len
), c
);
1995 scratch_p
= (operand_reg
[nop
] != NULL_RTX
1996 && lra_former_scratch_p (REGNO (operand_reg
[nop
])));
1997 /* Record which operands fit this alternative. */
2000 this_alternative_win
= true;
2001 if (operand_reg
[nop
] != NULL_RTX
)
2003 if (hard_regno
[nop
] >= 0)
2005 if (in_hard_reg_set_p (this_costly_alternative_set
,
2006 mode
, hard_regno
[nop
]))
2008 if (lra_dump_file
!= NULL
)
2009 fprintf (lra_dump_file
,
2010 " %d Costly set: reject++\n",
2017 /* Prefer won reg to spilled pseudo under other
2018 equal conditions for possibe inheritance. */
2021 if (lra_dump_file
!= NULL
)
2024 " %d Non pseudo reload: reject++\n",
2028 if (in_class_p (operand_reg
[nop
],
2029 this_costly_alternative
, NULL
))
2031 if (lra_dump_file
!= NULL
)
2034 " %d Non pseudo costly reload:"
2040 /* We simulate the behaviour of old reload here.
2041 Although scratches need hard registers and it
2042 might result in spilling other pseudos, no reload
2043 insns are generated for the scratches. So it
2044 might cost something but probably less than old
2045 reload pass believes. */
2048 if (lra_dump_file
!= NULL
)
2049 fprintf (lra_dump_file
,
2050 " %d Scratch win: reject+=2\n",
2057 this_alternative_match_win
= true;
2060 int const_to_mem
= 0;
2063 /* Never do output reload of stack pointer. It makes
2064 impossible to do elimination when SP is changed in
2066 if (op
== stack_pointer_rtx
&& ! frame_pointer_needed
2067 && curr_static_id
->operand
[nop
].type
!= OP_IN
)
2070 /* If this alternative asks for a specific reg class, see if there
2071 is at least one allocatable register in that class. */
2073 = (this_alternative
== NO_REGS
2074 || (hard_reg_set_subset_p
2075 (reg_class_contents
[this_alternative
],
2076 lra_no_alloc_regs
)));
2078 /* For asms, verify that the class for this alternative is possible
2079 for the mode that is specified. */
2080 if (!no_regs_p
&& INSN_CODE (curr_insn
) < 0)
2083 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
2084 if (HARD_REGNO_MODE_OK (i
, mode
)
2085 && in_hard_reg_set_p (reg_class_contents
[this_alternative
],
2088 if (i
== FIRST_PSEUDO_REGISTER
)
2092 /* If this operand accepts a register, and if the
2093 register class has at least one allocatable register,
2094 then this operand can be reloaded. */
2095 if (winreg
&& !no_regs_p
)
2100 if (lra_dump_file
!= NULL
)
2101 fprintf (lra_dump_file
,
2102 " alt=%d: Bad operand -- refuse\n",
2107 this_alternative_offmemok
= offmemok
;
2108 if (this_costly_alternative
!= NO_REGS
)
2110 if (lra_dump_file
!= NULL
)
2111 fprintf (lra_dump_file
,
2112 " %d Costly loser: reject++\n", nop
);
2115 /* If the operand is dying, has a matching constraint,
2116 and satisfies constraints of the matched operand
2117 which failed to satisfy the own constraints, probably
2118 the reload for this operand will be gone. */
2119 if (this_alternative_matches
>= 0
2120 && !curr_alt_win
[this_alternative_matches
]
2122 && find_regno_note (curr_insn
, REG_DEAD
, REGNO (op
))
2123 && (hard_regno
[nop
] >= 0
2124 ? in_hard_reg_set_p (this_alternative_set
,
2125 mode
, hard_regno
[nop
])
2126 : in_class_p (op
, this_alternative
, NULL
)))
2128 if (lra_dump_file
!= NULL
)
2131 " %d Dying matched operand reload: reject++\n",
2137 /* Strict_low_part requires to reload the register
2138 not the sub-register. In this case we should
2139 check that a final reload hard reg can hold the
2141 if (curr_static_id
->operand
[nop
].strict_low
2143 && hard_regno
[nop
] < 0
2144 && GET_CODE (*curr_id
->operand_loc
[nop
]) == SUBREG
2145 && ira_class_hard_regs_num
[this_alternative
] > 0
2146 && ! HARD_REGNO_MODE_OK (ira_class_hard_regs
2147 [this_alternative
][0],
2149 (*curr_id
->operand_loc
[nop
])))
2151 if (lra_dump_file
!= NULL
)
2154 " alt=%d: Strict low subreg reload -- refuse\n",
2160 if (operand_reg
[nop
] != NULL_RTX
2161 /* Output operands and matched input operands are
2162 not inherited. The following conditions do not
2163 exactly describe the previous statement but they
2164 are pretty close. */
2165 && curr_static_id
->operand
[nop
].type
!= OP_OUT
2166 && (this_alternative_matches
< 0
2167 || curr_static_id
->operand
[nop
].type
!= OP_IN
))
2169 int last_reload
= (lra_reg_info
[ORIGINAL_REGNO
2173 if (last_reload
> bb_reload_num
)
2174 reload_sum
+= last_reload
- bb_reload_num
;
2176 /* If this is a constant that is reloaded into the
2177 desired class by copying it to memory first, count
2178 that as another reload. This is consistent with
2179 other code and is required to avoid choosing another
2180 alternative when the constant is moved into memory.
2181 Note that the test here is precisely the same as in
2182 the code below that calls force_const_mem. */
2183 if (CONST_POOL_OK_P (mode
, op
)
2184 && ((targetm
.preferred_reload_class
2185 (op
, this_alternative
) == NO_REGS
)
2186 || no_input_reloads_p
))
2193 /* Alternative loses if it requires a type of reload not
2194 permitted for this insn. We can always reload
2195 objects with a REG_UNUSED note. */
2196 if ((curr_static_id
->operand
[nop
].type
!= OP_IN
2197 && no_output_reloads_p
2198 && ! find_reg_note (curr_insn
, REG_UNUSED
, op
))
2199 || (curr_static_id
->operand
[nop
].type
!= OP_OUT
2200 && no_input_reloads_p
&& ! const_to_mem
)
2201 || (this_alternative_matches
>= 0
2202 && (no_input_reloads_p
2203 || (no_output_reloads_p
2204 && (curr_static_id
->operand
2205 [this_alternative_matches
].type
!= OP_IN
)
2206 && ! find_reg_note (curr_insn
, REG_UNUSED
,
2207 no_subreg_reg_operand
2208 [this_alternative_matches
])))))
2210 if (lra_dump_file
!= NULL
)
2213 " alt=%d: No input/otput reload -- refuse\n",
2218 /* Check strong discouragement of reload of non-constant
2219 into class THIS_ALTERNATIVE. */
2220 if (! CONSTANT_P (op
) && ! no_regs_p
2221 && (targetm
.preferred_reload_class
2222 (op
, this_alternative
) == NO_REGS
2223 || (curr_static_id
->operand
[nop
].type
== OP_OUT
2224 && (targetm
.preferred_output_reload_class
2225 (op
, this_alternative
) == NO_REGS
))))
2227 if (lra_dump_file
!= NULL
)
2228 fprintf (lra_dump_file
,
2229 " %d Non-prefered reload: reject+=%d\n",
2230 nop
, LRA_MAX_REJECT
);
2231 reject
+= LRA_MAX_REJECT
;
2234 if (! (MEM_P (op
) && offmemok
)
2235 && ! (const_to_mem
&& constmemok
))
2237 /* We prefer to reload pseudos over reloading other
2238 things, since such reloads may be able to be
2239 eliminated later. So bump REJECT in other cases.
2240 Don't do this in the case where we are forcing a
2241 constant into memory and it will then win since
2242 we don't want to have a different alternative
2244 if (! (REG_P (op
) && REGNO (op
) >= FIRST_PSEUDO_REGISTER
))
2246 if (lra_dump_file
!= NULL
)
2249 " %d Non-pseudo reload: reject+=2\n",
2256 += ira_reg_class_max_nregs
[this_alternative
][mode
];
2258 if (SMALL_REGISTER_CLASS_P (this_alternative
))
2260 if (lra_dump_file
!= NULL
)
2263 " %d Small class reload: reject+=%d\n",
2264 nop
, LRA_LOSER_COST_FACTOR
/ 2);
2265 reject
+= LRA_LOSER_COST_FACTOR
/ 2;
2269 /* We are trying to spill pseudo into memory. It is
2270 usually more costly than moving to a hard register
2271 although it might takes the same number of
2273 if (no_regs_p
&& REG_P (op
) && hard_regno
[nop
] >= 0)
2275 if (lra_dump_file
!= NULL
)
2278 " %d Spill pseudo in memory: reject+=3\n",
2283 #ifdef SECONDARY_MEMORY_NEEDED
2284 /* If reload requires moving value through secondary
2285 memory, it will need one more insn at least. */
2286 if (this_alternative
!= NO_REGS
2287 && REG_P (op
) && (cl
= get_reg_class (REGNO (op
))) != NO_REGS
2288 && ((curr_static_id
->operand
[nop
].type
!= OP_OUT
2289 && SECONDARY_MEMORY_NEEDED (cl
, this_alternative
,
2291 || (curr_static_id
->operand
[nop
].type
!= OP_IN
2292 && SECONDARY_MEMORY_NEEDED (this_alternative
, cl
,
2296 /* Input reloads can be inherited more often than output
2297 reloads can be removed, so penalize output
2299 if (!REG_P (op
) || curr_static_id
->operand
[nop
].type
!= OP_IN
)
2301 if (lra_dump_file
!= NULL
)
2304 " %d Non input pseudo reload: reject++\n",
2310 if (early_clobber_p
&& ! scratch_p
)
2312 if (lra_dump_file
!= NULL
)
2313 fprintf (lra_dump_file
,
2314 " %d Early clobber: reject++\n", nop
);
2317 /* ??? We check early clobbers after processing all operands
2318 (see loop below) and there we update the costs more.
2319 Should we update the cost (may be approximately) here
2320 because of early clobber register reloads or it is a rare
2321 or non-important thing to be worth to do it. */
2322 overall
= losers
* LRA_LOSER_COST_FACTOR
+ reject
;
2323 if ((best_losers
== 0 || losers
!= 0) && best_overall
< overall
)
2325 if (lra_dump_file
!= NULL
)
2326 fprintf (lra_dump_file
,
2327 " alt=%d,overall=%d,losers=%d -- refuse\n",
2328 nalt
, overall
, losers
);
2332 curr_alt
[nop
] = this_alternative
;
2333 COPY_HARD_REG_SET (curr_alt_set
[nop
], this_alternative_set
);
2334 curr_alt_win
[nop
] = this_alternative_win
;
2335 curr_alt_match_win
[nop
] = this_alternative_match_win
;
2336 curr_alt_offmemok
[nop
] = this_alternative_offmemok
;
2337 curr_alt_matches
[nop
] = this_alternative_matches
;
2339 if (this_alternative_matches
>= 0
2340 && !did_match
&& !this_alternative_win
)
2341 curr_alt_win
[this_alternative_matches
] = false;
2343 if (early_clobber_p
&& operand_reg
[nop
] != NULL_RTX
)
2344 early_clobbered_nops
[early_clobbered_regs_num
++] = nop
;
2346 if (curr_insn_set
!= NULL_RTX
&& n_operands
== 2
2347 /* Prevent processing non-move insns. */
2348 && (GET_CODE (SET_SRC (curr_insn_set
)) == SUBREG
2349 || SET_SRC (curr_insn_set
) == no_subreg_reg_operand
[1])
2350 && ((! curr_alt_win
[0] && ! curr_alt_win
[1]
2351 && REG_P (no_subreg_reg_operand
[0])
2352 && REG_P (no_subreg_reg_operand
[1])
2353 && (reg_in_class_p (no_subreg_reg_operand
[0], curr_alt
[1])
2354 || reg_in_class_p (no_subreg_reg_operand
[1], curr_alt
[0])))
2355 || (! curr_alt_win
[0] && curr_alt_win
[1]
2356 && REG_P (no_subreg_reg_operand
[1])
2357 && reg_in_class_p (no_subreg_reg_operand
[1], curr_alt
[0]))
2358 || (curr_alt_win
[0] && ! curr_alt_win
[1]
2359 && REG_P (no_subreg_reg_operand
[0])
2360 && reg_in_class_p (no_subreg_reg_operand
[0], curr_alt
[1])
2361 && (! CONST_POOL_OK_P (curr_operand_mode
[1],
2362 no_subreg_reg_operand
[1])
2363 || (targetm
.preferred_reload_class
2364 (no_subreg_reg_operand
[1],
2365 (enum reg_class
) curr_alt
[1]) != NO_REGS
))
2366 /* If it is a result of recent elimination in move
2367 insn we can transform it into an add still by
2368 using this alternative. */
2369 && GET_CODE (no_subreg_reg_operand
[1]) != PLUS
)))
2371 /* We have a move insn and a new reload insn will be similar
2372 to the current insn. We should avoid such situation as it
2373 results in LRA cycling. */
2374 overall
+= LRA_MAX_REJECT
;
2377 curr_alt_dont_inherit_ops_num
= 0;
2378 for (nop
= 0; nop
< early_clobbered_regs_num
; nop
++)
2380 int i
, j
, clobbered_hard_regno
, first_conflict_j
, last_conflict_j
;
2381 HARD_REG_SET temp_set
;
2383 i
= early_clobbered_nops
[nop
];
2384 if ((! curr_alt_win
[i
] && ! curr_alt_match_win
[i
])
2385 || hard_regno
[i
] < 0)
2387 lra_assert (operand_reg
[i
] != NULL_RTX
);
2388 clobbered_hard_regno
= hard_regno
[i
];
2389 CLEAR_HARD_REG_SET (temp_set
);
2390 add_to_hard_reg_set (&temp_set
, biggest_mode
[i
], clobbered_hard_regno
);
2391 first_conflict_j
= last_conflict_j
= -1;
2392 for (j
= 0; j
< n_operands
; j
++)
2394 /* We don't want process insides of match_operator and
2395 match_parallel because otherwise we would process
2396 their operands once again generating a wrong
2398 || curr_static_id
->operand
[j
].is_operator
)
2400 else if ((curr_alt_matches
[j
] == i
&& curr_alt_match_win
[j
])
2401 || (curr_alt_matches
[i
] == j
&& curr_alt_match_win
[i
]))
2403 /* If we don't reload j-th operand, check conflicts. */
2404 else if ((curr_alt_win
[j
] || curr_alt_match_win
[j
])
2405 && uses_hard_regs_p (*curr_id
->operand_loc
[j
], temp_set
))
2407 if (first_conflict_j
< 0)
2408 first_conflict_j
= j
;
2409 last_conflict_j
= j
;
2411 if (last_conflict_j
< 0)
2413 /* If earlyclobber operand conflicts with another
2414 non-matching operand which is actually the same register
2415 as the earlyclobber operand, it is better to reload the
2416 another operand as an operand matching the earlyclobber
2417 operand can be also the same. */
2418 if (first_conflict_j
== last_conflict_j
2419 && operand_reg
[last_conflict_j
]
2420 != NULL_RTX
&& ! curr_alt_match_win
[last_conflict_j
]
2421 && REGNO (operand_reg
[i
]) == REGNO (operand_reg
[last_conflict_j
]))
2423 curr_alt_win
[last_conflict_j
] = false;
2424 curr_alt_dont_inherit_ops
[curr_alt_dont_inherit_ops_num
++]
2427 /* Early clobber was already reflected in REJECT. */
2428 lra_assert (reject
> 0);
2429 if (lra_dump_file
!= NULL
)
2432 " %d Conflict early clobber reload: reject--\n",
2435 overall
+= LRA_LOSER_COST_FACTOR
- 1;
2439 /* We need to reload early clobbered register and the
2440 matched registers. */
2441 for (j
= 0; j
< n_operands
; j
++)
2442 if (curr_alt_matches
[j
] == i
)
2444 curr_alt_match_win
[j
] = false;
2446 overall
+= LRA_LOSER_COST_FACTOR
;
2448 if (! curr_alt_match_win
[i
])
2449 curr_alt_dont_inherit_ops
[curr_alt_dont_inherit_ops_num
++] = i
;
2452 /* Remember pseudos used for match reloads are never
2454 lra_assert (curr_alt_matches
[i
] >= 0);
2455 curr_alt_win
[curr_alt_matches
[i
]] = false;
2457 curr_alt_win
[i
] = curr_alt_match_win
[i
] = false;
2459 /* Early clobber was already reflected in REJECT. */
2460 lra_assert (reject
> 0);
2461 if (lra_dump_file
!= NULL
)
2464 " %d Matched conflict early clobber reloads:"
2468 overall
+= LRA_LOSER_COST_FACTOR
- 1;
2471 if (lra_dump_file
!= NULL
)
2472 fprintf (lra_dump_file
, " alt=%d,overall=%d,losers=%d,rld_nregs=%d\n",
2473 nalt
, overall
, losers
, reload_nregs
);
2475 /* If this alternative can be made to work by reloading, and it
2476 needs less reloading than the others checked so far, record
2477 it as the chosen goal for reloading. */
2478 if ((best_losers
!= 0 && losers
== 0)
2479 || (((best_losers
== 0 && losers
== 0)
2480 || (best_losers
!= 0 && losers
!= 0))
2481 && (best_overall
> overall
2482 || (best_overall
== overall
2483 /* If the cost of the reloads is the same,
2484 prefer alternative which requires minimal
2485 number of reload regs. */
2486 && (reload_nregs
< best_reload_nregs
2487 || (reload_nregs
== best_reload_nregs
2488 && (best_reload_sum
< reload_sum
2489 || (best_reload_sum
== reload_sum
2490 && nalt
< goal_alt_number
))))))))
2492 for (nop
= 0; nop
< n_operands
; nop
++)
2494 goal_alt_win
[nop
] = curr_alt_win
[nop
];
2495 goal_alt_match_win
[nop
] = curr_alt_match_win
[nop
];
2496 goal_alt_matches
[nop
] = curr_alt_matches
[nop
];
2497 goal_alt
[nop
] = curr_alt
[nop
];
2498 goal_alt_offmemok
[nop
] = curr_alt_offmemok
[nop
];
2500 goal_alt_dont_inherit_ops_num
= curr_alt_dont_inherit_ops_num
;
2501 for (nop
= 0; nop
< curr_alt_dont_inherit_ops_num
; nop
++)
2502 goal_alt_dont_inherit_ops
[nop
] = curr_alt_dont_inherit_ops
[nop
];
2503 goal_alt_swapped
= curr_swapped
;
2504 best_overall
= overall
;
2505 best_losers
= losers
;
2506 best_reload_nregs
= reload_nregs
;
2507 best_reload_sum
= reload_sum
;
2508 goal_alt_number
= nalt
;
2511 /* Everything is satisfied. Do not process alternatives
2520 /* Return 1 if ADDR is a valid memory address for mode MODE in address
2521 space AS, and check that each pseudo has the proper kind of hard
2524 valid_address_p (enum machine_mode mode ATTRIBUTE_UNUSED
,
2525 rtx addr
, addr_space_t as
)
2527 #ifdef GO_IF_LEGITIMATE_ADDRESS
2528 lra_assert (ADDR_SPACE_GENERIC_P (as
));
2529 GO_IF_LEGITIMATE_ADDRESS (mode
, addr
, win
);
2535 return targetm
.addr_space
.legitimate_address_p (mode
, addr
, 0, as
);
2539 /* Return whether address AD is valid. */
2542 valid_address_p (struct address_info
*ad
)
2544 /* Some ports do not check displacements for eliminable registers,
2545 so we replace them temporarily with the elimination target. */
2546 rtx saved_base_reg
= NULL_RTX
;
2547 rtx saved_index_reg
= NULL_RTX
;
2548 rtx
*base_term
= strip_subreg (ad
->base_term
);
2549 rtx
*index_term
= strip_subreg (ad
->index_term
);
2550 if (base_term
!= NULL
)
2552 saved_base_reg
= *base_term
;
2553 lra_eliminate_reg_if_possible (base_term
);
2554 if (ad
->base_term2
!= NULL
)
2555 *ad
->base_term2
= *ad
->base_term
;
2557 if (index_term
!= NULL
)
2559 saved_index_reg
= *index_term
;
2560 lra_eliminate_reg_if_possible (index_term
);
2562 bool ok_p
= valid_address_p (ad
->mode
, *ad
->outer
, ad
->as
);
2563 if (saved_base_reg
!= NULL_RTX
)
2565 *base_term
= saved_base_reg
;
2566 if (ad
->base_term2
!= NULL
)
2567 *ad
->base_term2
= *ad
->base_term
;
2569 if (saved_index_reg
!= NULL_RTX
)
2570 *index_term
= saved_index_reg
;
2574 /* Make reload base reg + disp from address AD. Return the new pseudo. */
2576 base_plus_disp_to_reg (struct address_info
*ad
)
2581 lra_assert (ad
->base
== ad
->base_term
&& ad
->disp
== ad
->disp_term
);
2582 cl
= base_reg_class (ad
->mode
, ad
->as
, ad
->base_outer_code
,
2583 get_index_code (ad
));
2584 new_reg
= lra_create_new_reg (GET_MODE (*ad
->base_term
), NULL_RTX
,
2586 lra_emit_add (new_reg
, *ad
->base_term
, *ad
->disp_term
);
2590 /* Return true if we can add a displacement to address AD, even if that
2591 makes the address invalid. The fix-up code requires any new address
2592 to be the sum of the BASE_TERM, INDEX and DISP_TERM fields. */
2594 can_add_disp_p (struct address_info
*ad
)
2596 return (!ad
->autoinc_p
2597 && ad
->segment
== NULL
2598 && ad
->base
== ad
->base_term
2599 && ad
->disp
== ad
->disp_term
);
2602 /* Make equiv substitution in address AD. Return true if a substitution
2605 equiv_address_substitution (struct address_info
*ad
)
2607 rtx base_reg
, new_base_reg
, index_reg
, new_index_reg
, *base_term
, *index_term
;
2608 HOST_WIDE_INT disp
, scale
;
2611 base_term
= strip_subreg (ad
->base_term
);
2612 if (base_term
== NULL
)
2613 base_reg
= new_base_reg
= NULL_RTX
;
2616 base_reg
= *base_term
;
2617 new_base_reg
= get_equiv_with_elimination (base_reg
, curr_insn
);
2619 index_term
= strip_subreg (ad
->index_term
);
2620 if (index_term
== NULL
)
2621 index_reg
= new_index_reg
= NULL_RTX
;
2624 index_reg
= *index_term
;
2625 new_index_reg
= get_equiv_with_elimination (index_reg
, curr_insn
);
2627 if (base_reg
== new_base_reg
&& index_reg
== new_index_reg
)
2631 if (lra_dump_file
!= NULL
)
2633 fprintf (lra_dump_file
, "Changing address in insn %d ",
2634 INSN_UID (curr_insn
));
2635 dump_value_slim (lra_dump_file
, *ad
->outer
, 1);
2637 if (base_reg
!= new_base_reg
)
2639 if (REG_P (new_base_reg
))
2641 *base_term
= new_base_reg
;
2644 else if (GET_CODE (new_base_reg
) == PLUS
2645 && REG_P (XEXP (new_base_reg
, 0))
2646 && CONST_INT_P (XEXP (new_base_reg
, 1))
2647 && can_add_disp_p (ad
))
2649 disp
+= INTVAL (XEXP (new_base_reg
, 1));
2650 *base_term
= XEXP (new_base_reg
, 0);
2653 if (ad
->base_term2
!= NULL
)
2654 *ad
->base_term2
= *ad
->base_term
;
2656 if (index_reg
!= new_index_reg
)
2658 if (REG_P (new_index_reg
))
2660 *index_term
= new_index_reg
;
2663 else if (GET_CODE (new_index_reg
) == PLUS
2664 && REG_P (XEXP (new_index_reg
, 0))
2665 && CONST_INT_P (XEXP (new_index_reg
, 1))
2666 && can_add_disp_p (ad
)
2667 && (scale
= get_index_scale (ad
)))
2669 disp
+= INTVAL (XEXP (new_index_reg
, 1)) * scale
;
2670 *index_term
= XEXP (new_index_reg
, 0);
2676 if (ad
->disp
!= NULL
)
2677 *ad
->disp
= plus_constant (GET_MODE (*ad
->inner
), *ad
->disp
, disp
);
2680 *ad
->inner
= plus_constant (GET_MODE (*ad
->inner
), *ad
->inner
, disp
);
2681 update_address (ad
);
2685 if (lra_dump_file
!= NULL
)
2688 fprintf (lra_dump_file
, " -- no change\n");
2691 fprintf (lra_dump_file
, " on equiv ");
2692 dump_value_slim (lra_dump_file
, *ad
->outer
, 1);
2693 fprintf (lra_dump_file
, "\n");
2699 /* Major function to make reloads for an address in operand NOP.
2700 The supported cases are:
2702 1) an address that existed before LRA started, at which point it
2703 must have been valid. These addresses are subject to elimination
2704 and may have become invalid due to the elimination offset being out
2707 2) an address created by forcing a constant to memory
2708 (force_const_to_mem). The initial form of these addresses might
2709 not be valid, and it is this function's job to make them valid.
2711 3) a frame address formed from a register and a (possibly zero)
2712 constant offset. As above, these addresses might not be valid and
2713 this function must make them so.
2715 Add reloads to the lists *BEFORE and *AFTER. We might need to add
2716 reloads to *AFTER because of inc/dec, {pre, post} modify in the
2717 address. Return true for any RTL change. */
2719 process_address (int nop
, rtx
*before
, rtx
*after
)
2721 struct address_info ad
;
2723 rtx op
= *curr_id
->operand_loc
[nop
];
2724 const char *constraint
= curr_static_id
->operand
[nop
].constraint
;
2727 if (constraint
[0] == 'p'
2728 || EXTRA_ADDRESS_CONSTRAINT (constraint
[0], constraint
))
2729 decompose_lea_address (&ad
, curr_id
->operand_loc
[nop
]);
2730 else if (MEM_P (op
))
2731 decompose_mem_address (&ad
, op
);
2732 else if (GET_CODE (op
) == SUBREG
2733 && MEM_P (SUBREG_REG (op
)))
2734 decompose_mem_address (&ad
, SUBREG_REG (op
));
2737 change_p
= equiv_address_substitution (&ad
);
2738 if (ad
.base_term
!= NULL
2739 && (process_addr_reg
2740 (ad
.base_term
, before
,
2742 && !(REG_P (*ad
.base_term
)
2743 && find_regno_note (curr_insn
, REG_DEAD
,
2744 REGNO (*ad
.base_term
)) != NULL_RTX
)
2746 base_reg_class (ad
.mode
, ad
.as
, ad
.base_outer_code
,
2747 get_index_code (&ad
)))))
2750 if (ad
.base_term2
!= NULL
)
2751 *ad
.base_term2
= *ad
.base_term
;
2753 if (ad
.index_term
!= NULL
2754 && process_addr_reg (ad
.index_term
, before
, NULL
, INDEX_REG_CLASS
))
2757 #ifdef EXTRA_CONSTRAINT_STR
2758 /* Target hooks sometimes reject extra constraint addresses -- use
2759 EXTRA_CONSTRAINT_STR for the validation. */
2760 if (constraint
[0] != 'p'
2761 && EXTRA_ADDRESS_CONSTRAINT (constraint
[0], constraint
)
2762 && EXTRA_CONSTRAINT_STR (op
, constraint
[0], constraint
))
2766 /* There are three cases where the shape of *AD.INNER may now be invalid:
2768 1) the original address was valid, but either elimination or
2769 equiv_address_substitution was applied and that made
2770 the address invalid.
2772 2) the address is an invalid symbolic address created by
2775 3) the address is a frame address with an invalid offset.
2777 All these cases involve a non-autoinc address, so there is no
2778 point revalidating other types. */
2779 if (ad
.autoinc_p
|| valid_address_p (&ad
))
2782 /* Any index existed before LRA started, so we can assume that the
2783 presence and shape of the index is valid. */
2784 push_to_sequence (*before
);
2785 lra_assert (ad
.disp
== ad
.disp_term
);
2786 if (ad
.base
== NULL
)
2788 if (ad
.index
== NULL
)
2791 enum reg_class cl
= base_reg_class (ad
.mode
, ad
.as
,
2793 rtx addr
= *ad
.inner
;
2795 new_reg
= lra_create_new_reg (Pmode
, NULL_RTX
, cl
, "addr");
2799 rtx last
= get_last_insn ();
2801 /* addr => lo_sum (new_base, addr), case (2) above. */
2802 insn
= emit_insn (gen_rtx_SET
2804 gen_rtx_HIGH (Pmode
, copy_rtx (addr
))));
2805 code
= recog_memoized (insn
);
2808 *ad
.inner
= gen_rtx_LO_SUM (Pmode
, new_reg
, addr
);
2809 if (! valid_address_p (ad
.mode
, *ad
.outer
, ad
.as
))
2811 /* Try to put lo_sum into register. */
2812 insn
= emit_insn (gen_rtx_SET
2814 gen_rtx_LO_SUM (Pmode
, new_reg
, addr
)));
2815 code
= recog_memoized (insn
);
2818 *ad
.inner
= new_reg
;
2819 if (! valid_address_p (ad
.mode
, *ad
.outer
, ad
.as
))
2829 delete_insns_since (last
);
2834 /* addr => new_base, case (2) above. */
2835 lra_emit_move (new_reg
, addr
);
2836 *ad
.inner
= new_reg
;
2841 /* index * scale + disp => new base + index * scale,
2843 enum reg_class cl
= base_reg_class (ad
.mode
, ad
.as
, PLUS
,
2844 GET_CODE (*ad
.index
));
2846 lra_assert (INDEX_REG_CLASS
!= NO_REGS
);
2847 new_reg
= lra_create_new_reg (Pmode
, NULL_RTX
, cl
, "disp");
2848 lra_emit_move (new_reg
, *ad
.disp
);
2849 *ad
.inner
= simplify_gen_binary (PLUS
, GET_MODE (new_reg
),
2850 new_reg
, *ad
.index
);
2853 else if (ad
.index
== NULL
)
2857 rtx set
, insns
, last_insn
;
2858 /* base + disp => new base, cases (1) and (3) above. */
2859 /* Another option would be to reload the displacement into an
2860 index register. However, postreload has code to optimize
2861 address reloads that have the same base and different
2862 displacements, so reloading into an index register would
2863 not necessarily be a win. */
2865 new_reg
= base_plus_disp_to_reg (&ad
);
2866 insns
= get_insns ();
2867 last_insn
= get_last_insn ();
2868 /* If we generated at least two insns, try last insn source as
2869 an address. If we succeed, we generate one less insn. */
2870 if (last_insn
!= insns
&& (set
= single_set (last_insn
)) != NULL_RTX
2871 && GET_CODE (SET_SRC (set
)) == PLUS
2872 && REG_P (XEXP (SET_SRC (set
), 0))
2873 && CONSTANT_P (XEXP (SET_SRC (set
), 1)))
2875 *ad
.inner
= SET_SRC (set
);
2876 if (valid_address_p (ad
.mode
, *ad
.outer
, ad
.as
))
2878 *ad
.base_term
= XEXP (SET_SRC (set
), 0);
2879 *ad
.disp_term
= XEXP (SET_SRC (set
), 1);
2880 cl
= base_reg_class (ad
.mode
, ad
.as
, ad
.base_outer_code
,
2881 get_index_code (&ad
));
2882 regno
= REGNO (*ad
.base_term
);
2883 if (regno
>= FIRST_PSEUDO_REGISTER
2884 && cl
!= lra_get_allocno_class (regno
))
2885 lra_change_class (regno
, cl
, " Change to", true);
2886 new_reg
= SET_SRC (set
);
2887 delete_insns_since (PREV_INSN (last_insn
));
2892 *ad
.inner
= new_reg
;
2896 /* base + scale * index + disp => new base + scale * index,
2898 new_reg
= base_plus_disp_to_reg (&ad
);
2899 *ad
.inner
= simplify_gen_binary (PLUS
, GET_MODE (new_reg
),
2900 new_reg
, *ad
.index
);
2902 *before
= get_insns ();
2907 /* Emit insns to reload VALUE into a new register. VALUE is an
2908 auto-increment or auto-decrement RTX whose operand is a register or
2909 memory location; so reloading involves incrementing that location.
2910 IN is either identical to VALUE, or some cheaper place to reload
2911 value being incremented/decremented from.
2913 INC_AMOUNT is the number to increment or decrement by (always
2914 positive and ignored for POST_MODIFY/PRE_MODIFY).
2916 Return pseudo containing the result. */
2918 emit_inc (enum reg_class new_rclass
, rtx in
, rtx value
, int inc_amount
)
2920 /* REG or MEM to be copied and incremented. */
2921 rtx incloc
= XEXP (value
, 0);
2922 /* Nonzero if increment after copying. */
2923 int post
= (GET_CODE (value
) == POST_DEC
|| GET_CODE (value
) == POST_INC
2924 || GET_CODE (value
) == POST_MODIFY
);
2929 rtx real_in
= in
== value
? incloc
: in
;
2933 if (GET_CODE (value
) == PRE_MODIFY
|| GET_CODE (value
) == POST_MODIFY
)
2935 lra_assert (GET_CODE (XEXP (value
, 1)) == PLUS
2936 || GET_CODE (XEXP (value
, 1)) == MINUS
);
2937 lra_assert (rtx_equal_p (XEXP (XEXP (value
, 1), 0), XEXP (value
, 0)));
2938 plus_p
= GET_CODE (XEXP (value
, 1)) == PLUS
;
2939 inc
= XEXP (XEXP (value
, 1), 1);
2943 if (GET_CODE (value
) == PRE_DEC
|| GET_CODE (value
) == POST_DEC
)
2944 inc_amount
= -inc_amount
;
2946 inc
= GEN_INT (inc_amount
);
2949 if (! post
&& REG_P (incloc
))
2952 result
= lra_create_new_reg (GET_MODE (value
), value
, new_rclass
,
2955 if (real_in
!= result
)
2957 /* First copy the location to the result register. */
2958 lra_assert (REG_P (result
));
2959 emit_insn (gen_move_insn (result
, real_in
));
2962 /* We suppose that there are insns to add/sub with the constant
2963 increment permitted in {PRE/POST)_{DEC/INC/MODIFY}. At least the
2964 old reload worked with this assumption. If the assumption
2965 becomes wrong, we should use approach in function
2966 base_plus_disp_to_reg. */
2969 /* See if we can directly increment INCLOC. */
2970 last
= get_last_insn ();
2971 add_insn
= emit_insn (plus_p
2972 ? gen_add2_insn (incloc
, inc
)
2973 : gen_sub2_insn (incloc
, inc
));
2975 code
= recog_memoized (add_insn
);
2978 if (! post
&& result
!= incloc
)
2979 emit_insn (gen_move_insn (result
, incloc
));
2982 delete_insns_since (last
);
2985 /* If couldn't do the increment directly, must increment in RESULT.
2986 The way we do this depends on whether this is pre- or
2987 post-increment. For pre-increment, copy INCLOC to the reload
2988 register, increment it there, then save back. */
2991 if (real_in
!= result
)
2992 emit_insn (gen_move_insn (result
, real_in
));
2994 emit_insn (gen_add2_insn (result
, inc
));
2996 emit_insn (gen_sub2_insn (result
, inc
));
2997 if (result
!= incloc
)
2998 emit_insn (gen_move_insn (incloc
, result
));
3004 Because this might be a jump insn or a compare, and because
3005 RESULT may not be available after the insn in an input
3006 reload, we must do the incrementing before the insn being
3009 We have already copied IN to RESULT. Increment the copy in
3010 RESULT, save that back, then decrement RESULT so it has
3011 the original value. */
3013 emit_insn (gen_add2_insn (result
, inc
));
3015 emit_insn (gen_sub2_insn (result
, inc
));
3016 emit_insn (gen_move_insn (incloc
, result
));
3017 /* Restore non-modified value for the result. We prefer this
3018 way because it does not require an additional hard
3022 if (CONST_INT_P (inc
))
3023 emit_insn (gen_add2_insn (result
,
3024 gen_int_mode (-INTVAL (inc
),
3025 GET_MODE (result
))));
3027 emit_insn (gen_sub2_insn (result
, inc
));
3030 emit_insn (gen_add2_insn (result
, inc
));
3035 /* Return true if the current move insn does not need processing as we
3036 already know that it satisfies its constraints. */
3038 simple_move_p (void)
3041 enum reg_class dclass
, sclass
;
3043 lra_assert (curr_insn_set
!= NULL_RTX
);
3044 dest
= SET_DEST (curr_insn_set
);
3045 src
= SET_SRC (curr_insn_set
);
3046 return ((dclass
= get_op_class (dest
)) != NO_REGS
3047 && (sclass
= get_op_class (src
)) != NO_REGS
3048 /* The backend guarantees that register moves of cost 2
3049 never need reloads. */
3050 && targetm
.register_move_cost (GET_MODE (src
), dclass
, sclass
) == 2);
3053 /* Swap operands NOP and NOP + 1. */
3055 swap_operands (int nop
)
3057 enum machine_mode mode
= curr_operand_mode
[nop
];
3058 curr_operand_mode
[nop
] = curr_operand_mode
[nop
+ 1];
3059 curr_operand_mode
[nop
+ 1] = mode
;
3060 rtx x
= *curr_id
->operand_loc
[nop
];
3061 *curr_id
->operand_loc
[nop
] = *curr_id
->operand_loc
[nop
+ 1];
3062 *curr_id
->operand_loc
[nop
+ 1] = x
;
3063 /* Swap the duplicates too. */
3064 lra_update_dup (curr_id
, nop
);
3065 lra_update_dup (curr_id
, nop
+ 1);
3068 /* Main entry point of the constraint code: search the body of the
3069 current insn to choose the best alternative. It is mimicking insn
3070 alternative cost calculation model of former reload pass. That is
3071 because machine descriptions were written to use this model. This
3072 model can be changed in future. Make commutative operand exchange
3075 Return true if some RTL changes happened during function call. */
3077 curr_insn_transform (void)
3083 signed char goal_alt_matched
[MAX_RECOG_OPERANDS
][MAX_RECOG_OPERANDS
];
3084 signed char match_inputs
[MAX_RECOG_OPERANDS
+ 1];
3087 /* Flag that the insn has been changed through a transformation. */
3090 #ifdef SECONDARY_MEMORY_NEEDED
3093 int max_regno_before
;
3094 int reused_alternative_num
;
3096 curr_insn_set
= single_set (curr_insn
);
3097 if (curr_insn_set
!= NULL_RTX
&& simple_move_p ())
3100 no_input_reloads_p
= no_output_reloads_p
= false;
3101 goal_alt_number
= -1;
3102 change_p
= sec_mem_p
= false;
3103 /* JUMP_INSNs and CALL_INSNs are not allowed to have any output
3104 reloads; neither are insns that SET cc0. Insns that use CC0 are
3105 not allowed to have any input reloads. */
3106 if (JUMP_P (curr_insn
) || CALL_P (curr_insn
))
3107 no_output_reloads_p
= true;
3110 if (reg_referenced_p (cc0_rtx
, PATTERN (curr_insn
)))
3111 no_input_reloads_p
= true;
3112 if (reg_set_p (cc0_rtx
, PATTERN (curr_insn
)))
3113 no_output_reloads_p
= true;
3116 n_operands
= curr_static_id
->n_operands
;
3117 n_alternatives
= curr_static_id
->n_alternatives
;
3119 /* Just return "no reloads" if insn has no operands with
3121 if (n_operands
== 0 || n_alternatives
== 0)
3124 max_regno_before
= max_reg_num ();
3126 for (i
= 0; i
< n_operands
; i
++)
3128 goal_alt_matched
[i
][0] = -1;
3129 goal_alt_matches
[i
] = -1;
3132 commutative
= curr_static_id
->commutative
;
3134 /* Now see what we need for pseudos that didn't get hard regs or got
3135 the wrong kind of hard reg. For this, we must consider all the
3136 operands together against the register constraints. */
3138 best_losers
= best_overall
= INT_MAX
;
3139 best_reload_sum
= 0;
3141 curr_swapped
= false;
3142 goal_alt_swapped
= false;
3144 /* Make equivalence substitution and memory subreg elimination
3145 before address processing because an address legitimacy can
3146 depend on memory mode. */
3147 for (i
= 0; i
< n_operands
; i
++)
3149 rtx op
= *curr_id
->operand_loc
[i
];
3150 rtx subst
, old
= op
;
3151 bool op_change_p
= false;
3153 if (GET_CODE (old
) == SUBREG
)
3154 old
= SUBREG_REG (old
);
3155 subst
= get_equiv_with_elimination (old
, curr_insn
);
3158 subst
= copy_rtx (subst
);
3159 lra_assert (REG_P (old
));
3160 if (GET_CODE (op
) == SUBREG
)
3161 SUBREG_REG (op
) = subst
;
3163 *curr_id
->operand_loc
[i
] = subst
;
3164 if (lra_dump_file
!= NULL
)
3166 fprintf (lra_dump_file
,
3167 "Changing pseudo %d in operand %i of insn %u on equiv ",
3168 REGNO (old
), i
, INSN_UID (curr_insn
));
3169 dump_value_slim (lra_dump_file
, subst
, 1);
3170 fprintf (lra_dump_file
, "\n");
3172 op_change_p
= change_p
= true;
3174 if (simplify_operand_subreg (i
, GET_MODE (old
)) || op_change_p
)
3177 lra_update_dup (curr_id
, i
);
3181 /* Reload address registers and displacements. We do it before
3182 finding an alternative because of memory constraints. */
3183 before
= after
= NULL_RTX
;
3184 for (i
= 0; i
< n_operands
; i
++)
3185 if (! curr_static_id
->operand
[i
].is_operator
3186 && process_address (i
, &before
, &after
))
3189 lra_update_dup (curr_id
, i
);
3193 /* If we've changed the instruction then any alternative that
3194 we chose previously may no longer be valid. */
3195 lra_set_used_insn_alternative (curr_insn
, -1);
3197 if (curr_insn_set
!= NULL_RTX
3198 && check_and_process_move (&change_p
, &sec_mem_p
))
3203 reused_alternative_num
= curr_id
->used_insn_alternative
;
3204 if (lra_dump_file
!= NULL
&& reused_alternative_num
>= 0)
3205 fprintf (lra_dump_file
, "Reusing alternative %d for insn #%u\n",
3206 reused_alternative_num
, INSN_UID (curr_insn
));
3208 if (process_alt_operands (reused_alternative_num
))
3211 /* If insn is commutative (it's safe to exchange a certain pair of
3212 operands) then we need to try each alternative twice, the second
3213 time matching those two operands as if we had exchanged them. To
3214 do this, really exchange them in operands.
3216 If we have just tried the alternatives the second time, return
3217 operands to normal and drop through. */
3219 if (reused_alternative_num
< 0 && commutative
>= 0)
3221 curr_swapped
= !curr_swapped
;
3224 swap_operands (commutative
);
3228 swap_operands (commutative
);
3231 if (! alt_p
&& ! sec_mem_p
)
3233 /* No alternative works with reloads?? */
3234 if (INSN_CODE (curr_insn
) >= 0)
3235 fatal_insn ("unable to generate reloads for:", curr_insn
);
3236 error_for_asm (curr_insn
,
3237 "inconsistent operand constraints in an %<asm%>");
3238 /* Avoid further trouble with this insn. */
3239 PATTERN (curr_insn
) = gen_rtx_USE (VOIDmode
, const0_rtx
);
3240 lra_invalidate_insn_data (curr_insn
);
3244 /* If the best alternative is with operands 1 and 2 swapped, swap
3245 them. Update the operand numbers of any reloads already
3248 if (goal_alt_swapped
)
3250 if (lra_dump_file
!= NULL
)
3251 fprintf (lra_dump_file
, " Commutative operand exchange in insn %u\n",
3252 INSN_UID (curr_insn
));
3254 /* Swap the duplicates too. */
3255 swap_operands (commutative
);
3259 #ifdef SECONDARY_MEMORY_NEEDED
3260 /* Some target macros SECONDARY_MEMORY_NEEDED (e.g. x86) are defined
3261 too conservatively. So we use the secondary memory only if there
3262 is no any alternative without reloads. */
3263 use_sec_mem_p
= false;
3265 use_sec_mem_p
= true;
3268 for (i
= 0; i
< n_operands
; i
++)
3269 if (! goal_alt_win
[i
] && ! goal_alt_match_win
[i
])
3271 use_sec_mem_p
= i
< n_operands
;
3276 rtx new_reg
, src
, dest
, rld
;
3277 enum machine_mode sec_mode
, rld_mode
;
3279 lra_assert (sec_mem_p
);
3280 lra_assert (curr_static_id
->operand
[0].type
== OP_OUT
3281 && curr_static_id
->operand
[1].type
== OP_IN
);
3282 dest
= *curr_id
->operand_loc
[0];
3283 src
= *curr_id
->operand_loc
[1];
3284 rld
= (GET_MODE_SIZE (GET_MODE (dest
)) <= GET_MODE_SIZE (GET_MODE (src
))
3286 rld_mode
= GET_MODE (rld
);
3287 #ifdef SECONDARY_MEMORY_NEEDED_MODE
3288 sec_mode
= SECONDARY_MEMORY_NEEDED_MODE (rld_mode
);
3290 sec_mode
= rld_mode
;
3292 new_reg
= lra_create_new_reg (sec_mode
, NULL_RTX
,
3293 NO_REGS
, "secondary");
3294 /* If the mode is changed, it should be wider. */
3295 lra_assert (GET_MODE_SIZE (sec_mode
) >= GET_MODE_SIZE (rld_mode
));
3296 if (sec_mode
!= rld_mode
)
3298 /* If the target says specifically to use another mode for
3299 secondary memory moves we can not reuse the original
3301 after
= emit_spill_move (false, new_reg
, dest
);
3302 lra_process_new_insns (curr_insn
, NULL_RTX
, after
,
3303 "Inserting the sec. move");
3304 /* We may have non null BEFORE here (e.g. after address
3306 push_to_sequence (before
);
3307 before
= emit_spill_move (true, new_reg
, src
);
3309 before
= get_insns ();
3311 lra_process_new_insns (curr_insn
, before
, NULL_RTX
, "Changing on");
3312 lra_set_insn_deleted (curr_insn
);
3314 else if (dest
== rld
)
3316 *curr_id
->operand_loc
[0] = new_reg
;
3317 after
= emit_spill_move (false, new_reg
, dest
);
3318 lra_process_new_insns (curr_insn
, NULL_RTX
, after
,
3319 "Inserting the sec. move");
3323 *curr_id
->operand_loc
[1] = new_reg
;
3324 /* See comments above. */
3325 push_to_sequence (before
);
3326 before
= emit_spill_move (true, new_reg
, src
);
3328 before
= get_insns ();
3330 lra_process_new_insns (curr_insn
, before
, NULL_RTX
,
3331 "Inserting the sec. move");
3333 lra_update_insn_regno_info (curr_insn
);
3338 lra_assert (goal_alt_number
>= 0);
3339 lra_set_used_insn_alternative (curr_insn
, goal_alt_number
);
3341 if (lra_dump_file
!= NULL
)
3345 fprintf (lra_dump_file
, " Choosing alt %d in insn %u:",
3346 goal_alt_number
, INSN_UID (curr_insn
));
3347 for (i
= 0; i
< n_operands
; i
++)
3349 p
= (curr_static_id
->operand_alternative
3350 [goal_alt_number
* n_operands
+ i
].constraint
);
3353 fprintf (lra_dump_file
, " (%d) ", i
);
3354 for (; *p
!= '\0' && *p
!= ',' && *p
!= '#'; p
++)
3355 fputc (*p
, lra_dump_file
);
3357 if (INSN_CODE (curr_insn
) >= 0
3358 && (p
= get_insn_name (INSN_CODE (curr_insn
))) != NULL
)
3359 fprintf (lra_dump_file
, " {%s}", p
);
3360 if (curr_id
->sp_offset
!= 0)
3361 fprintf (lra_dump_file
, " (sp_off=%" HOST_WIDE_INT_PRINT
"d)",
3362 curr_id
->sp_offset
);
3363 fprintf (lra_dump_file
, "\n");
3366 /* Right now, for any pair of operands I and J that are required to
3367 match, with J < I, goal_alt_matches[I] is J. Add I to
3368 goal_alt_matched[J]. */
3370 for (i
= 0; i
< n_operands
; i
++)
3371 if ((j
= goal_alt_matches
[i
]) >= 0)
3373 for (k
= 0; goal_alt_matched
[j
][k
] >= 0; k
++)
3375 /* We allow matching one output operand and several input
3378 || (curr_static_id
->operand
[j
].type
== OP_OUT
3379 && curr_static_id
->operand
[i
].type
== OP_IN
3380 && (curr_static_id
->operand
3381 [goal_alt_matched
[j
][0]].type
== OP_IN
)));
3382 goal_alt_matched
[j
][k
] = i
;
3383 goal_alt_matched
[j
][k
+ 1] = -1;
3386 for (i
= 0; i
< n_operands
; i
++)
3387 goal_alt_win
[i
] |= goal_alt_match_win
[i
];
3389 /* Any constants that aren't allowed and can't be reloaded into
3390 registers are here changed into memory references. */
3391 for (i
= 0; i
< n_operands
; i
++)
3392 if (goal_alt_win
[i
])
3395 enum reg_class new_class
;
3396 rtx reg
= *curr_id
->operand_loc
[i
];
3398 if (GET_CODE (reg
) == SUBREG
)
3399 reg
= SUBREG_REG (reg
);
3401 if (REG_P (reg
) && (regno
= REGNO (reg
)) >= FIRST_PSEUDO_REGISTER
)
3403 bool ok_p
= in_class_p (reg
, goal_alt
[i
], &new_class
);
3405 if (new_class
!= NO_REGS
&& get_reg_class (regno
) != new_class
)
3408 lra_change_class (regno
, new_class
, " Change to", true);
3414 const char *constraint
;
3416 rtx op
= *curr_id
->operand_loc
[i
];
3417 rtx subreg
= NULL_RTX
;
3418 enum machine_mode mode
= curr_operand_mode
[i
];
3420 if (GET_CODE (op
) == SUBREG
)
3423 op
= SUBREG_REG (op
);
3424 mode
= GET_MODE (op
);
3427 if (CONST_POOL_OK_P (mode
, op
)
3428 && ((targetm
.preferred_reload_class
3429 (op
, (enum reg_class
) goal_alt
[i
]) == NO_REGS
)
3430 || no_input_reloads_p
))
3432 rtx tem
= force_const_mem (mode
, op
);
3435 if (subreg
!= NULL_RTX
)
3436 tem
= gen_rtx_SUBREG (mode
, tem
, SUBREG_BYTE (subreg
));
3438 *curr_id
->operand_loc
[i
] = tem
;
3439 lra_update_dup (curr_id
, i
);
3440 process_address (i
, &before
, &after
);
3442 /* If the alternative accepts constant pool refs directly
3443 there will be no reload needed at all. */
3444 if (subreg
!= NULL_RTX
)
3446 /* Skip alternatives before the one requested. */
3447 constraint
= (curr_static_id
->operand_alternative
3448 [goal_alt_number
* n_operands
+ i
].constraint
);
3450 (c
= *constraint
) && c
!= ',' && c
!= '#';
3451 constraint
+= CONSTRAINT_LEN (c
, constraint
))
3453 if (c
== TARGET_MEM_CONSTRAINT
|| c
== 'o')
3455 #ifdef EXTRA_CONSTRAINT_STR
3456 if (EXTRA_MEMORY_CONSTRAINT (c
, constraint
)
3457 && EXTRA_CONSTRAINT_STR (tem
, c
, constraint
))
3461 if (c
== '\0' || c
== ',' || c
== '#')
3464 goal_alt_win
[i
] = true;
3468 for (i
= 0; i
< n_operands
; i
++)
3471 bool optional_p
= false;
3473 rtx op
= *curr_id
->operand_loc
[i
];
3475 if (goal_alt_win
[i
])
3477 if (goal_alt
[i
] == NO_REGS
3479 /* When we assign NO_REGS it means that we will not
3480 assign a hard register to the scratch pseudo by
3481 assigment pass and the scratch pseudo will be
3482 spilled. Spilled scratch pseudos are transformed
3483 back to scratches at the LRA end. */
3484 && lra_former_scratch_operand_p (curr_insn
, i
))
3486 int regno
= REGNO (op
);
3487 lra_change_class (regno
, NO_REGS
, " Change to", true);
3488 if (lra_get_regno_hard_regno (regno
) >= 0)
3489 /* We don't have to mark all insn affected by the
3490 spilled pseudo as there is only one such insn, the
3492 reg_renumber
[regno
] = -1;
3494 /* We can do an optional reload. If the pseudo got a hard
3495 reg, we might improve the code through inheritance. If
3496 it does not get a hard register we coalesce memory/memory
3497 moves later. Ignore move insns to avoid cycling. */
3499 && lra_undo_inheritance_iter
< LRA_MAX_INHERITANCE_PASSES
3500 && goal_alt
[i
] != NO_REGS
&& REG_P (op
)
3501 && (regno
= REGNO (op
)) >= FIRST_PSEUDO_REGISTER
3502 && regno
< new_regno_start
3503 && ! lra_former_scratch_p (regno
)
3504 && reg_renumber
[regno
] < 0
3505 && (curr_insn_set
== NULL_RTX
3506 || !((REG_P (SET_SRC (curr_insn_set
))
3507 || MEM_P (SET_SRC (curr_insn_set
))
3508 || GET_CODE (SET_SRC (curr_insn_set
)) == SUBREG
)
3509 && (REG_P (SET_DEST (curr_insn_set
))
3510 || MEM_P (SET_DEST (curr_insn_set
))
3511 || GET_CODE (SET_DEST (curr_insn_set
)) == SUBREG
))))
3517 /* Operands that match previous ones have already been handled. */
3518 if (goal_alt_matches
[i
] >= 0)
3521 /* We should not have an operand with a non-offsettable address
3522 appearing where an offsettable address will do. It also may
3523 be a case when the address should be special in other words
3524 not a general one (e.g. it needs no index reg). */
3525 if (goal_alt_matched
[i
][0] == -1 && goal_alt_offmemok
[i
] && MEM_P (op
))
3527 enum reg_class rclass
;
3528 rtx
*loc
= &XEXP (op
, 0);
3529 enum rtx_code code
= GET_CODE (*loc
);
3531 push_to_sequence (before
);
3532 rclass
= base_reg_class (GET_MODE (op
), MEM_ADDR_SPACE (op
),
3534 if (GET_RTX_CLASS (code
) == RTX_AUTOINC
)
3535 new_reg
= emit_inc (rclass
, *loc
, *loc
,
3536 /* This value does not matter for MODIFY. */
3537 GET_MODE_SIZE (GET_MODE (op
)));
3538 else if (get_reload_reg (OP_IN
, Pmode
, *loc
, rclass
,
3539 "offsetable address", &new_reg
))
3540 lra_emit_move (new_reg
, *loc
);
3541 before
= get_insns ();
3544 lra_update_dup (curr_id
, i
);
3546 else if (goal_alt_matched
[i
][0] == -1)
3548 enum machine_mode mode
;
3550 int hard_regno
, byte
;
3551 enum op_type type
= curr_static_id
->operand
[i
].type
;
3553 loc
= curr_id
->operand_loc
[i
];
3554 mode
= curr_operand_mode
[i
];
3555 if (GET_CODE (*loc
) == SUBREG
)
3557 reg
= SUBREG_REG (*loc
);
3558 byte
= SUBREG_BYTE (*loc
);
3560 /* Strict_low_part requires reload the register not
3561 the sub-register. */
3562 && (curr_static_id
->operand
[i
].strict_low
3563 || (GET_MODE_SIZE (mode
)
3564 <= GET_MODE_SIZE (GET_MODE (reg
))
3566 = get_try_hard_regno (REGNO (reg
))) >= 0
3567 && (simplify_subreg_regno
3569 GET_MODE (reg
), byte
, mode
) < 0)
3570 && (goal_alt
[i
] == NO_REGS
3571 || (simplify_subreg_regno
3572 (ira_class_hard_regs
[goal_alt
[i
]][0],
3573 GET_MODE (reg
), byte
, mode
) >= 0)))))
3575 loc
= &SUBREG_REG (*loc
);
3576 mode
= GET_MODE (*loc
);
3580 if (get_reload_reg (type
, mode
, old
, goal_alt
[i
], "", &new_reg
)
3583 push_to_sequence (before
);
3584 lra_emit_move (new_reg
, old
);
3585 before
= get_insns ();
3590 && find_reg_note (curr_insn
, REG_UNUSED
, old
) == NULL_RTX
)
3593 lra_emit_move (type
== OP_INOUT
? copy_rtx (old
) : old
, new_reg
);
3595 after
= get_insns ();
3599 for (j
= 0; j
< goal_alt_dont_inherit_ops_num
; j
++)
3600 if (goal_alt_dont_inherit_ops
[j
] == i
)
3602 lra_set_regno_unique_value (REGNO (new_reg
));
3605 lra_update_dup (curr_id
, i
);
3607 else if (curr_static_id
->operand
[i
].type
== OP_IN
3608 && (curr_static_id
->operand
[goal_alt_matched
[i
][0]].type
3611 /* generate reloads for input and matched outputs. */
3612 match_inputs
[0] = i
;
3613 match_inputs
[1] = -1;
3614 match_reload (goal_alt_matched
[i
][0], match_inputs
,
3615 goal_alt
[i
], &before
, &after
);
3617 else if (curr_static_id
->operand
[i
].type
== OP_OUT
3618 && (curr_static_id
->operand
[goal_alt_matched
[i
][0]].type
3620 /* Generate reloads for output and matched inputs. */
3621 match_reload (i
, goal_alt_matched
[i
], goal_alt
[i
], &before
, &after
);
3622 else if (curr_static_id
->operand
[i
].type
== OP_IN
3623 && (curr_static_id
->operand
[goal_alt_matched
[i
][0]].type
3626 /* Generate reloads for matched inputs. */
3627 match_inputs
[0] = i
;
3628 for (j
= 0; (k
= goal_alt_matched
[i
][j
]) >= 0; j
++)
3629 match_inputs
[j
+ 1] = k
;
3630 match_inputs
[j
+ 1] = -1;
3631 match_reload (-1, match_inputs
, goal_alt
[i
], &before
, &after
);
3634 /* We must generate code in any case when function
3635 process_alt_operands decides that it is possible. */
3639 lra_assert (REG_P (op
));
3641 op
= *curr_id
->operand_loc
[i
]; /* Substitution. */
3642 if (GET_CODE (op
) == SUBREG
)
3643 op
= SUBREG_REG (op
);
3644 gcc_assert (REG_P (op
) && (int) REGNO (op
) >= new_regno_start
);
3645 bitmap_set_bit (&lra_optional_reload_pseudos
, REGNO (op
));
3646 lra_reg_info
[REGNO (op
)].restore_regno
= regno
;
3647 if (lra_dump_file
!= NULL
)
3648 fprintf (lra_dump_file
,
3649 " Making reload reg %d for reg %d optional\n",
3653 if (before
!= NULL_RTX
|| after
!= NULL_RTX
3654 || max_regno_before
!= max_reg_num ())
3658 lra_update_operator_dups (curr_id
);
3659 /* Something changes -- process the insn. */
3660 lra_update_insn_regno_info (curr_insn
);
3662 lra_process_new_insns (curr_insn
, before
, after
, "Inserting insn reload");
3666 /* Return true if X is in LIST. */
3668 in_list_p (rtx x
, rtx list
)
3670 for (; list
!= NULL_RTX
; list
= XEXP (list
, 1))
3671 if (XEXP (list
, 0) == x
)
3676 /* Return true if X contains an allocatable hard register (if
3677 HARD_REG_P) or a (spilled if SPILLED_P) pseudo. */
3679 contains_reg_p (rtx x
, bool hard_reg_p
, bool spilled_p
)
3685 code
= GET_CODE (x
);
3688 int regno
= REGNO (x
);
3689 HARD_REG_SET alloc_regs
;
3693 if (regno
>= FIRST_PSEUDO_REGISTER
)
3694 regno
= lra_get_regno_hard_regno (regno
);
3697 COMPL_HARD_REG_SET (alloc_regs
, lra_no_alloc_regs
);
3698 return overlaps_hard_reg_set_p (alloc_regs
, GET_MODE (x
), regno
);
3702 if (regno
< FIRST_PSEUDO_REGISTER
)
3706 return lra_get_regno_hard_regno (regno
) < 0;
3709 fmt
= GET_RTX_FORMAT (code
);
3710 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
3714 if (contains_reg_p (XEXP (x
, i
), hard_reg_p
, spilled_p
))
3717 else if (fmt
[i
] == 'E')
3719 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3720 if (contains_reg_p (XVECEXP (x
, i
, j
), hard_reg_p
, spilled_p
))
3727 /* Process all regs in location *LOC and change them on equivalent
3728 substitution. Return true if any change was done. */
3730 loc_equivalence_change_p (rtx
*loc
)
3732 rtx subst
, reg
, x
= *loc
;
3733 bool result
= false;
3734 enum rtx_code code
= GET_CODE (x
);
3740 reg
= SUBREG_REG (x
);
3741 if ((subst
= get_equiv_with_elimination (reg
, curr_insn
)) != reg
3742 && GET_MODE (subst
) == VOIDmode
)
3744 /* We cannot reload debug location. Simplify subreg here
3745 while we know the inner mode. */
3746 *loc
= simplify_gen_subreg (GET_MODE (x
), subst
,
3747 GET_MODE (reg
), SUBREG_BYTE (x
));
3751 if (code
== REG
&& (subst
= get_equiv_with_elimination (x
, curr_insn
)) != x
)
3757 /* Scan all the operand sub-expressions. */
3758 fmt
= GET_RTX_FORMAT (code
);
3759 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
3762 result
= loc_equivalence_change_p (&XEXP (x
, i
)) || result
;
3763 else if (fmt
[i
] == 'E')
3764 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3766 = loc_equivalence_change_p (&XVECEXP (x
, i
, j
)) || result
;
3771 /* Similar to loc_equivalence_change_p, but for use as
3772 simplify_replace_fn_rtx callback. DATA is insn for which the
3773 elimination is done. If it null we don't do the elimination. */
3775 loc_equivalence_callback (rtx loc
, const_rtx
, void *data
)
3780 rtx subst
= (data
== NULL
3781 ? get_equiv (loc
) : get_equiv_with_elimination (loc
, (rtx
) data
));
3788 /* Maximum number of generated reload insns per an insn. It is for
3789 preventing this pass cycling in a bug case. */
3790 #define MAX_RELOAD_INSNS_NUMBER LRA_MAX_INSN_RELOADS
3792 /* The current iteration number of this LRA pass. */
3793 int lra_constraint_iter
;
3795 /* The current iteration number of this LRA pass after the last spill
3797 int lra_constraint_iter_after_spill
;
3799 /* True if we substituted equiv which needs checking register
3800 allocation correctness because the equivalent value contains
3801 allocatable hard registers or when we restore multi-register
3803 bool lra_risky_transformations_p
;
3805 /* Return true if REGNO is referenced in more than one block. */
3807 multi_block_pseudo_p (int regno
)
3809 basic_block bb
= NULL
;
3813 if (regno
< FIRST_PSEUDO_REGISTER
)
3816 EXECUTE_IF_SET_IN_BITMAP (&lra_reg_info
[regno
].insn_bitmap
, 0, uid
, bi
)
3818 bb
= BLOCK_FOR_INSN (lra_insn_recog_data
[uid
]->insn
);
3819 else if (BLOCK_FOR_INSN (lra_insn_recog_data
[uid
]->insn
) != bb
)
3824 /* Return true if LIST contains a deleted insn. */
3826 contains_deleted_insn_p (rtx list
)
3828 for (; list
!= NULL_RTX
; list
= XEXP (list
, 1))
3829 if (NOTE_P (XEXP (list
, 0))
3830 && NOTE_KIND (XEXP (list
, 0)) == NOTE_INSN_DELETED
)
3835 /* Return true if X contains a pseudo dying in INSN. */
3837 dead_pseudo_p (rtx x
, rtx insn
)
3844 return (insn
!= NULL_RTX
3845 && find_regno_note (insn
, REG_DEAD
, REGNO (x
)) != NULL_RTX
);
3846 code
= GET_CODE (x
);
3847 fmt
= GET_RTX_FORMAT (code
);
3848 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
3852 if (dead_pseudo_p (XEXP (x
, i
), insn
))
3855 else if (fmt
[i
] == 'E')
3857 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3858 if (dead_pseudo_p (XVECEXP (x
, i
, j
), insn
))
3865 /* Return true if INSN contains a dying pseudo in INSN right hand
3868 insn_rhs_dead_pseudo_p (rtx insn
)
3870 rtx set
= single_set (insn
);
3872 gcc_assert (set
!= NULL
);
3873 return dead_pseudo_p (SET_SRC (set
), insn
);
3876 /* Return true if any init insn of REGNO contains a dying pseudo in
3877 insn right hand side. */
3879 init_insn_rhs_dead_pseudo_p (int regno
)
3881 rtx insns
= ira_reg_equiv
[regno
].init_insns
;
3886 return insn_rhs_dead_pseudo_p (insns
);
3887 for (; insns
!= NULL_RTX
; insns
= XEXP (insns
, 1))
3888 if (insn_rhs_dead_pseudo_p (XEXP (insns
, 0)))
3893 /* Return TRUE if REGNO has a reverse equivalence. The equivalence is
3894 reverse only if we have one init insn with given REGNO as a
3897 reverse_equiv_p (int regno
)
3901 if ((insns
= ira_reg_equiv
[regno
].init_insns
) == NULL_RTX
)
3903 if (! INSN_P (XEXP (insns
, 0))
3904 || XEXP (insns
, 1) != NULL_RTX
)
3906 if ((set
= single_set (XEXP (insns
, 0))) == NULL_RTX
)
3908 return REG_P (SET_SRC (set
)) && (int) REGNO (SET_SRC (set
)) == regno
;
3911 /* Return TRUE if REGNO was reloaded in an equivalence init insn. We
3912 call this function only for non-reverse equivalence. */
3914 contains_reloaded_insn_p (int regno
)
3917 rtx list
= ira_reg_equiv
[regno
].init_insns
;
3919 for (; list
!= NULL_RTX
; list
= XEXP (list
, 1))
3920 if ((set
= single_set (XEXP (list
, 0))) == NULL_RTX
3921 || ! REG_P (SET_DEST (set
))
3922 || (int) REGNO (SET_DEST (set
)) != regno
)
3927 /* Entry function of LRA constraint pass. Return true if the
3928 constraint pass did change the code. */
3930 lra_constraints (bool first_p
)
3933 int i
, hard_regno
, new_insns_num
;
3934 unsigned int min_len
, new_min_len
, uid
;
3935 rtx set
, x
, reg
, dest_reg
;
3936 basic_block last_bb
;
3937 bitmap_head equiv_insn_bitmap
;
3940 lra_constraint_iter
++;
3941 if (lra_dump_file
!= NULL
)
3942 fprintf (lra_dump_file
, "\n********** Local #%d: **********\n\n",
3943 lra_constraint_iter
);
3944 lra_constraint_iter_after_spill
++;
3945 if (lra_constraint_iter_after_spill
> LRA_MAX_CONSTRAINT_ITERATION_NUMBER
)
3947 ("Maximum number of LRA constraint passes is achieved (%d)\n",
3948 LRA_MAX_CONSTRAINT_ITERATION_NUMBER
);
3950 lra_risky_transformations_p
= false;
3951 new_insn_uid_start
= get_max_uid ();
3952 new_regno_start
= first_p
? lra_constraint_new_regno_start
: max_reg_num ();
3953 /* Mark used hard regs for target stack size calulations. */
3954 for (i
= FIRST_PSEUDO_REGISTER
; i
< new_regno_start
; i
++)
3955 if (lra_reg_info
[i
].nrefs
!= 0
3956 && (hard_regno
= lra_get_regno_hard_regno (i
)) >= 0)
3960 nregs
= hard_regno_nregs
[hard_regno
][lra_reg_info
[i
].biggest_mode
];
3961 for (j
= 0; j
< nregs
; j
++)
3962 df_set_regs_ever_live (hard_regno
+ j
, true);
3964 /* Do elimination before the equivalence processing as we can spill
3965 some pseudos during elimination. */
3966 lra_eliminate (false, first_p
);
3967 bitmap_initialize (&equiv_insn_bitmap
, ®_obstack
);
3968 for (i
= FIRST_PSEUDO_REGISTER
; i
< new_regno_start
; i
++)
3969 if (lra_reg_info
[i
].nrefs
!= 0)
3971 ira_reg_equiv
[i
].profitable_p
= true;
3972 reg
= regno_reg_rtx
[i
];
3973 if (lra_get_regno_hard_regno (i
) < 0 && (x
= get_equiv (reg
)) != reg
)
3975 bool pseudo_p
= contains_reg_p (x
, false, false);
3977 /* After RTL transformation, we can not guarantee that
3978 pseudo in the substitution was not reloaded which might
3979 make equivalence invalid. For example, in reverse
3986 the memory address register was reloaded before the 2nd
3988 if ((! first_p
&& pseudo_p
)
3989 /* We don't use DF for compilation speed sake. So it
3990 is problematic to update live info when we use an
3991 equivalence containing pseudos in more than one
3993 || (pseudo_p
&& multi_block_pseudo_p (i
))
3994 /* If an init insn was deleted for some reason, cancel
3995 the equiv. We could update the equiv insns after
3996 transformations including an equiv insn deletion
3997 but it is not worthy as such cases are extremely
3999 || contains_deleted_insn_p (ira_reg_equiv
[i
].init_insns
)
4000 /* If it is not a reverse equivalence, we check that a
4001 pseudo in rhs of the init insn is not dying in the
4002 insn. Otherwise, the live info at the beginning of
4003 the corresponding BB might be wrong after we
4004 removed the insn. When the equiv can be a
4005 constant, the right hand side of the init insn can
4007 || (! reverse_equiv_p (i
)
4008 && (init_insn_rhs_dead_pseudo_p (i
)
4009 /* If we reloaded the pseudo in an equivalence
4010 init insn, we can not remove the equiv init
4011 insns and the init insns might write into
4012 const memory in this case. */
4013 || contains_reloaded_insn_p (i
)))
4014 /* Prevent access beyond equivalent memory for
4015 paradoxical subregs. */
4017 && (GET_MODE_SIZE (lra_reg_info
[i
].biggest_mode
)
4018 > GET_MODE_SIZE (GET_MODE (x
)))))
4019 ira_reg_equiv
[i
].defined_p
= false;
4020 if (contains_reg_p (x
, false, true))
4021 ira_reg_equiv
[i
].profitable_p
= false;
4022 if (get_equiv (reg
) != reg
)
4023 bitmap_ior_into (&equiv_insn_bitmap
, &lra_reg_info
[i
].insn_bitmap
);
4026 for (i
= FIRST_PSEUDO_REGISTER
; i
< new_regno_start
; i
++)
4028 /* We should add all insns containing pseudos which should be
4029 substituted by their equivalences. */
4030 EXECUTE_IF_SET_IN_BITMAP (&equiv_insn_bitmap
, 0, uid
, bi
)
4031 lra_push_insn_by_uid (uid
);
4032 min_len
= lra_insn_stack_length ();
4036 while ((new_min_len
= lra_insn_stack_length ()) != 0)
4038 curr_insn
= lra_pop_insn ();
4040 curr_bb
= BLOCK_FOR_INSN (curr_insn
);
4041 if (curr_bb
!= last_bb
)
4044 bb_reload_num
= lra_curr_reload_num
;
4046 if (min_len
> new_min_len
)
4048 min_len
= new_min_len
;
4051 if (new_insns_num
> MAX_RELOAD_INSNS_NUMBER
)
4053 ("Max. number of generated reload insns per insn is achieved (%d)\n",
4054 MAX_RELOAD_INSNS_NUMBER
);
4056 if (DEBUG_INSN_P (curr_insn
))
4058 /* We need to check equivalence in debug insn and change
4059 pseudo to the equivalent value if necessary. */
4060 curr_id
= lra_get_insn_recog_data (curr_insn
);
4061 if (bitmap_bit_p (&equiv_insn_bitmap
, INSN_UID (curr_insn
)))
4063 rtx old
= *curr_id
->operand_loc
[0];
4064 *curr_id
->operand_loc
[0]
4065 = simplify_replace_fn_rtx (old
, NULL_RTX
,
4066 loc_equivalence_callback
, curr_insn
);
4067 if (old
!= *curr_id
->operand_loc
[0])
4069 lra_update_insn_regno_info (curr_insn
);
4074 else if (INSN_P (curr_insn
))
4076 if ((set
= single_set (curr_insn
)) != NULL_RTX
)
4078 dest_reg
= SET_DEST (set
);
4079 /* The equivalence pseudo could be set up as SUBREG in a
4080 case when it is a call restore insn in a mode
4081 different from the pseudo mode. */
4082 if (GET_CODE (dest_reg
) == SUBREG
)
4083 dest_reg
= SUBREG_REG (dest_reg
);
4084 if ((REG_P (dest_reg
)
4085 && (x
= get_equiv (dest_reg
)) != dest_reg
4086 /* Remove insns which set up a pseudo whose value
4087 can not be changed. Such insns might be not in
4088 init_insns because we don't update equiv data
4089 during insn transformations.
4091 As an example, let suppose that a pseudo got
4092 hard register and on the 1st pass was not
4093 changed to equivalent constant. We generate an
4094 additional insn setting up the pseudo because of
4095 secondary memory movement. Then the pseudo is
4096 spilled and we use the equiv constant. In this
4097 case we should remove the additional insn and
4098 this insn is not init_insns list. */
4099 && (! MEM_P (x
) || MEM_READONLY_P (x
)
4100 /* Check that this is actually an insn setting
4101 up the equivalence. */
4102 || in_list_p (curr_insn
,
4104 [REGNO (dest_reg
)].init_insns
)))
4105 || (((x
= get_equiv (SET_SRC (set
))) != SET_SRC (set
))
4106 && in_list_p (curr_insn
,
4108 [REGNO (SET_SRC (set
))].init_insns
)))
4110 /* This is equiv init insn of pseudo which did not get a
4111 hard register -- remove the insn. */
4112 if (lra_dump_file
!= NULL
)
4114 fprintf (lra_dump_file
,
4115 " Removing equiv init insn %i (freq=%d)\n",
4116 INSN_UID (curr_insn
),
4117 REG_FREQ_FROM_BB (BLOCK_FOR_INSN (curr_insn
)));
4118 dump_insn_slim (lra_dump_file
, curr_insn
);
4120 if (contains_reg_p (x
, true, false))
4121 lra_risky_transformations_p
= true;
4122 lra_set_insn_deleted (curr_insn
);
4126 curr_id
= lra_get_insn_recog_data (curr_insn
);
4127 curr_static_id
= curr_id
->insn_static_data
;
4128 init_curr_insn_input_reloads ();
4129 init_curr_operand_mode ();
4130 if (curr_insn_transform ())
4132 /* Check non-transformed insns too for equiv change as USE
4133 or CLOBBER don't need reloads but can contain pseudos
4134 being changed on their equivalences. */
4135 else if (bitmap_bit_p (&equiv_insn_bitmap
, INSN_UID (curr_insn
))
4136 && loc_equivalence_change_p (&PATTERN (curr_insn
)))
4138 lra_update_insn_regno_info (curr_insn
);
4143 bitmap_clear (&equiv_insn_bitmap
);
4144 /* If we used a new hard regno, changed_p should be true because the
4145 hard reg is assigned to a new pseudo. */
4146 #ifdef ENABLE_CHECKING
4149 for (i
= FIRST_PSEUDO_REGISTER
; i
< new_regno_start
; i
++)
4150 if (lra_reg_info
[i
].nrefs
!= 0
4151 && (hard_regno
= lra_get_regno_hard_regno (i
)) >= 0)
4153 int j
, nregs
= hard_regno_nregs
[hard_regno
][PSEUDO_REGNO_MODE (i
)];
4155 for (j
= 0; j
< nregs
; j
++)
4156 lra_assert (df_regs_ever_live_p (hard_regno
+ j
));
4163 /* Initiate the LRA constraint pass. It is done once per
4166 lra_constraints_init (void)
4170 /* Finalize the LRA constraint pass. It is done once per
4173 lra_constraints_finish (void)
4179 /* This page contains code to do inheritance/split
4182 /* Number of reloads passed so far in current EBB. */
4183 static int reloads_num
;
4185 /* Number of calls passed so far in current EBB. */
4186 static int calls_num
;
4188 /* Current reload pseudo check for validity of elements in
4190 static int curr_usage_insns_check
;
4192 /* Info about last usage of registers in EBB to do inheritance/split
4193 transformation. Inheritance transformation is done from a spilled
4194 pseudo and split transformations from a hard register or a pseudo
4195 assigned to a hard register. */
4198 /* If the value is equal to CURR_USAGE_INSNS_CHECK, then the member
4199 value INSNS is valid. The insns is chain of optional debug insns
4200 and a finishing non-debug insn using the corresponding reg. The
4201 value is also used to mark the registers which are set up in the
4202 current insn. The negated insn uid is used for this. */
4204 /* Value of global reloads_num at the last insn in INSNS. */
4206 /* Value of global reloads_nums at the last insn in INSNS. */
4208 /* It can be true only for splitting. And it means that the restore
4209 insn should be put after insn given by the following member. */
4211 /* Next insns in the current EBB which use the original reg and the
4212 original reg value is not changed between the current insn and
4213 the next insns. In order words, e.g. for inheritance, if we need
4214 to use the original reg value again in the next insns we can try
4215 to use the value in a hard register from a reload insn of the
4220 /* Map: regno -> corresponding pseudo usage insns. */
4221 static struct usage_insns
*usage_insns
;
4224 setup_next_usage_insn (int regno
, rtx insn
, int reloads_num
, bool after_p
)
4226 usage_insns
[regno
].check
= curr_usage_insns_check
;
4227 usage_insns
[regno
].insns
= insn
;
4228 usage_insns
[regno
].reloads_num
= reloads_num
;
4229 usage_insns
[regno
].calls_num
= calls_num
;
4230 usage_insns
[regno
].after_p
= after_p
;
4233 /* The function is used to form list REGNO usages which consists of
4234 optional debug insns finished by a non-debug insn using REGNO.
4235 RELOADS_NUM is current number of reload insns processed so far. */
4237 add_next_usage_insn (int regno
, rtx insn
, int reloads_num
)
4239 rtx next_usage_insns
;
4241 if (usage_insns
[regno
].check
== curr_usage_insns_check
4242 && (next_usage_insns
= usage_insns
[regno
].insns
) != NULL_RTX
4243 && DEBUG_INSN_P (insn
))
4245 /* Check that we did not add the debug insn yet. */
4246 if (next_usage_insns
!= insn
4247 && (GET_CODE (next_usage_insns
) != INSN_LIST
4248 || XEXP (next_usage_insns
, 0) != insn
))
4249 usage_insns
[regno
].insns
= gen_rtx_INSN_LIST (VOIDmode
, insn
,
4252 else if (NONDEBUG_INSN_P (insn
))
4253 setup_next_usage_insn (regno
, insn
, reloads_num
, false);
4255 usage_insns
[regno
].check
= 0;
4258 /* Replace all references to register OLD_REGNO in *LOC with pseudo
4259 register NEW_REG. Return true if any change was made. */
4261 substitute_pseudo (rtx
*loc
, int old_regno
, rtx new_reg
)
4264 bool result
= false;
4272 code
= GET_CODE (x
);
4273 if (code
== REG
&& (int) REGNO (x
) == old_regno
)
4275 enum machine_mode mode
= GET_MODE (*loc
);
4276 enum machine_mode inner_mode
= GET_MODE (new_reg
);
4278 if (mode
!= inner_mode
)
4280 if (GET_MODE_SIZE (mode
) >= GET_MODE_SIZE (inner_mode
)
4281 || ! SCALAR_INT_MODE_P (inner_mode
))
4282 new_reg
= gen_rtx_SUBREG (mode
, new_reg
, 0);
4284 new_reg
= gen_lowpart_SUBREG (mode
, new_reg
);
4290 /* Scan all the operand sub-expressions. */
4291 fmt
= GET_RTX_FORMAT (code
);
4292 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
4296 if (substitute_pseudo (&XEXP (x
, i
), old_regno
, new_reg
))
4299 else if (fmt
[i
] == 'E')
4301 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
4302 if (substitute_pseudo (&XVECEXP (x
, i
, j
), old_regno
, new_reg
))
4309 /* Return first non-debug insn in list USAGE_INSNS. */
4311 skip_usage_debug_insns (rtx usage_insns
)
4315 /* Skip debug insns. */
4316 for (insn
= usage_insns
;
4317 insn
!= NULL_RTX
&& GET_CODE (insn
) == INSN_LIST
;
4318 insn
= XEXP (insn
, 1))
4323 /* Return true if we need secondary memory moves for insn in
4324 USAGE_INSNS after inserting inherited pseudo of class INHER_CL
4327 check_secondary_memory_needed_p (enum reg_class inher_cl ATTRIBUTE_UNUSED
,
4328 rtx usage_insns ATTRIBUTE_UNUSED
)
4330 #ifndef SECONDARY_MEMORY_NEEDED
4333 rtx insn
, set
, dest
;
4336 if (inher_cl
== ALL_REGS
4337 || (insn
= skip_usage_debug_insns (usage_insns
)) == NULL_RTX
)
4339 lra_assert (INSN_P (insn
));
4340 if ((set
= single_set (insn
)) == NULL_RTX
|| ! REG_P (SET_DEST (set
)))
4342 dest
= SET_DEST (set
);
4345 lra_assert (inher_cl
!= NO_REGS
);
4346 cl
= get_reg_class (REGNO (dest
));
4347 return (cl
!= NO_REGS
&& cl
!= ALL_REGS
4348 && SECONDARY_MEMORY_NEEDED (inher_cl
, cl
, GET_MODE (dest
)));
4352 /* Registers involved in inheritance/split in the current EBB
4353 (inheritance/split pseudos and original registers). */
4354 static bitmap_head check_only_regs
;
4356 /* Do inheritance transformations for insn INSN, which defines (if
4357 DEF_P) or uses ORIGINAL_REGNO. NEXT_USAGE_INSNS specifies which
4358 instruction in the EBB next uses ORIGINAL_REGNO; it has the same
4359 form as the "insns" field of usage_insns. Return true if we
4360 succeed in such transformation.
4362 The transformations look like:
4365 ... p <- i (new insn)
4367 <- ... p ... <- ... i ...
4369 ... i <- p (new insn)
4370 <- ... p ... <- ... i ...
4372 <- ... p ... <- ... i ...
4373 where p is a spilled original pseudo and i is a new inheritance pseudo.
4376 The inheritance pseudo has the smallest class of two classes CL and
4377 class of ORIGINAL REGNO. */
4379 inherit_reload_reg (bool def_p
, int original_regno
,
4380 enum reg_class cl
, rtx insn
, rtx next_usage_insns
)
4382 enum reg_class rclass
= lra_get_allocno_class (original_regno
);
4383 rtx original_reg
= regno_reg_rtx
[original_regno
];
4384 rtx new_reg
, new_insns
, usage_insn
;
4386 lra_assert (! usage_insns
[original_regno
].after_p
);
4387 if (lra_dump_file
!= NULL
)
4388 fprintf (lra_dump_file
,
4389 " <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<\n");
4390 if (! ira_reg_classes_intersect_p
[cl
][rclass
])
4392 if (lra_dump_file
!= NULL
)
4394 fprintf (lra_dump_file
,
4395 " Rejecting inheritance for %d "
4396 "because of disjoint classes %s and %s\n",
4397 original_regno
, reg_class_names
[cl
],
4398 reg_class_names
[rclass
]);
4399 fprintf (lra_dump_file
,
4400 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
4404 if ((ira_class_subset_p
[cl
][rclass
] && cl
!= rclass
)
4405 /* We don't use a subset of two classes because it can be
4406 NO_REGS. This transformation is still profitable in most
4407 cases even if the classes are not intersected as register
4408 move is probably cheaper than a memory load. */
4409 || ira_class_hard_regs_num
[cl
] < ira_class_hard_regs_num
[rclass
])
4411 if (lra_dump_file
!= NULL
)
4412 fprintf (lra_dump_file
, " Use smallest class of %s and %s\n",
4413 reg_class_names
[cl
], reg_class_names
[rclass
]);
4417 if (check_secondary_memory_needed_p (rclass
, next_usage_insns
))
4419 /* Reject inheritance resulting in secondary memory moves.
4420 Otherwise, there is a danger in LRA cycling. Also such
4421 transformation will be unprofitable. */
4422 if (lra_dump_file
!= NULL
)
4424 rtx insn
= skip_usage_debug_insns (next_usage_insns
);
4425 rtx set
= single_set (insn
);
4427 lra_assert (set
!= NULL_RTX
);
4429 rtx dest
= SET_DEST (set
);
4431 lra_assert (REG_P (dest
));
4432 fprintf (lra_dump_file
,
4433 " Rejecting inheritance for insn %d(%s)<-%d(%s) "
4434 "as secondary mem is needed\n",
4435 REGNO (dest
), reg_class_names
[get_reg_class (REGNO (dest
))],
4436 original_regno
, reg_class_names
[rclass
]);
4437 fprintf (lra_dump_file
,
4438 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
4442 new_reg
= lra_create_new_reg (GET_MODE (original_reg
), original_reg
,
4443 rclass
, "inheritance");
4446 emit_move_insn (original_reg
, new_reg
);
4448 emit_move_insn (new_reg
, original_reg
);
4449 new_insns
= get_insns ();
4451 if (NEXT_INSN (new_insns
) != NULL_RTX
)
4453 if (lra_dump_file
!= NULL
)
4455 fprintf (lra_dump_file
,
4456 " Rejecting inheritance %d->%d "
4457 "as it results in 2 or more insns:\n",
4458 original_regno
, REGNO (new_reg
));
4459 dump_rtl_slim (lra_dump_file
, new_insns
, NULL_RTX
, -1, 0);
4460 fprintf (lra_dump_file
,
4461 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
4465 substitute_pseudo (&insn
, original_regno
, new_reg
);
4466 lra_update_insn_regno_info (insn
);
4468 /* We now have a new usage insn for original regno. */
4469 setup_next_usage_insn (original_regno
, new_insns
, reloads_num
, false);
4470 if (lra_dump_file
!= NULL
)
4471 fprintf (lra_dump_file
, " Original reg change %d->%d (bb%d):\n",
4472 original_regno
, REGNO (new_reg
), BLOCK_FOR_INSN (insn
)->index
);
4473 lra_reg_info
[REGNO (new_reg
)].restore_regno
= original_regno
;
4474 bitmap_set_bit (&check_only_regs
, REGNO (new_reg
));
4475 bitmap_set_bit (&check_only_regs
, original_regno
);
4476 bitmap_set_bit (&lra_inheritance_pseudos
, REGNO (new_reg
));
4478 lra_process_new_insns (insn
, NULL_RTX
, new_insns
,
4479 "Add original<-inheritance");
4481 lra_process_new_insns (insn
, new_insns
, NULL_RTX
,
4482 "Add inheritance<-original");
4483 while (next_usage_insns
!= NULL_RTX
)
4485 if (GET_CODE (next_usage_insns
) != INSN_LIST
)
4487 usage_insn
= next_usage_insns
;
4488 lra_assert (NONDEBUG_INSN_P (usage_insn
));
4489 next_usage_insns
= NULL
;
4493 usage_insn
= XEXP (next_usage_insns
, 0);
4494 lra_assert (DEBUG_INSN_P (usage_insn
));
4495 next_usage_insns
= XEXP (next_usage_insns
, 1);
4497 substitute_pseudo (&usage_insn
, original_regno
, new_reg
);
4498 lra_update_insn_regno_info (usage_insn
);
4499 if (lra_dump_file
!= NULL
)
4501 fprintf (lra_dump_file
,
4502 " Inheritance reuse change %d->%d (bb%d):\n",
4503 original_regno
, REGNO (new_reg
),
4504 BLOCK_FOR_INSN (usage_insn
)->index
);
4505 dump_insn_slim (lra_dump_file
, usage_insn
);
4508 if (lra_dump_file
!= NULL
)
4509 fprintf (lra_dump_file
,
4510 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
4514 /* Return true if we need a caller save/restore for pseudo REGNO which
4515 was assigned to a hard register. */
4517 need_for_call_save_p (int regno
)
4519 lra_assert (regno
>= FIRST_PSEUDO_REGISTER
&& reg_renumber
[regno
] >= 0);
4520 return (usage_insns
[regno
].calls_num
< calls_num
4521 && (overlaps_hard_reg_set_p
4523 PSEUDO_REGNO_MODE (regno
), reg_renumber
[regno
])
4524 || HARD_REGNO_CALL_PART_CLOBBERED (reg_renumber
[regno
],
4525 PSEUDO_REGNO_MODE (regno
))));
4528 /* Global registers occurring in the current EBB. */
4529 static bitmap_head ebb_global_regs
;
4531 /* Return true if we need a split for hard register REGNO or pseudo
4532 REGNO which was assigned to a hard register.
4533 POTENTIAL_RELOAD_HARD_REGS contains hard registers which might be
4534 used for reloads since the EBB end. It is an approximation of the
4535 used hard registers in the split range. The exact value would
4536 require expensive calculations. If we were aggressive with
4537 splitting because of the approximation, the split pseudo will save
4538 the same hard register assignment and will be removed in the undo
4539 pass. We still need the approximation because too aggressive
4540 splitting would result in too inaccurate cost calculation in the
4541 assignment pass because of too many generated moves which will be
4542 probably removed in the undo pass. */
4544 need_for_split_p (HARD_REG_SET potential_reload_hard_regs
, int regno
)
4546 int hard_regno
= regno
< FIRST_PSEUDO_REGISTER
? regno
: reg_renumber
[regno
];
4548 lra_assert (hard_regno
>= 0);
4549 return ((TEST_HARD_REG_BIT (potential_reload_hard_regs
, hard_regno
)
4550 /* Don't split eliminable hard registers, otherwise we can
4551 split hard registers like hard frame pointer, which
4552 lives on BB start/end according to DF-infrastructure,
4553 when there is a pseudo assigned to the register and
4554 living in the same BB. */
4555 && (regno
>= FIRST_PSEUDO_REGISTER
4556 || ! TEST_HARD_REG_BIT (eliminable_regset
, hard_regno
))
4557 && ! TEST_HARD_REG_BIT (lra_no_alloc_regs
, hard_regno
)
4558 /* Don't split call clobbered hard regs living through
4559 calls, otherwise we might have a check problem in the
4560 assign sub-pass as in the most cases (exception is a
4561 situation when lra_risky_transformations_p value is
4562 true) the assign pass assumes that all pseudos living
4563 through calls are assigned to call saved hard regs. */
4564 && (regno
>= FIRST_PSEUDO_REGISTER
4565 || ! TEST_HARD_REG_BIT (call_used_reg_set
, regno
)
4566 || usage_insns
[regno
].calls_num
== calls_num
)
4567 /* We need at least 2 reloads to make pseudo splitting
4568 profitable. We should provide hard regno splitting in
4569 any case to solve 1st insn scheduling problem when
4570 moving hard register definition up might result in
4571 impossibility to find hard register for reload pseudo of
4572 small register class. */
4573 && (usage_insns
[regno
].reloads_num
4574 + (regno
< FIRST_PSEUDO_REGISTER
? 0 : 2) < reloads_num
)
4575 && (regno
< FIRST_PSEUDO_REGISTER
4576 /* For short living pseudos, spilling + inheritance can
4577 be considered a substitution for splitting.
4578 Therefore we do not splitting for local pseudos. It
4579 decreases also aggressiveness of splitting. The
4580 minimal number of references is chosen taking into
4581 account that for 2 references splitting has no sense
4582 as we can just spill the pseudo. */
4583 || (regno
>= FIRST_PSEUDO_REGISTER
4584 && lra_reg_info
[regno
].nrefs
> 3
4585 && bitmap_bit_p (&ebb_global_regs
, regno
))))
4586 || (regno
>= FIRST_PSEUDO_REGISTER
&& need_for_call_save_p (regno
)));
4589 /* Return class for the split pseudo created from original pseudo with
4590 ALLOCNO_CLASS and MODE which got a hard register HARD_REGNO. We
4591 choose subclass of ALLOCNO_CLASS which contains HARD_REGNO and
4592 results in no secondary memory movements. */
4593 static enum reg_class
4594 choose_split_class (enum reg_class allocno_class
,
4595 int hard_regno ATTRIBUTE_UNUSED
,
4596 enum machine_mode mode ATTRIBUTE_UNUSED
)
4598 #ifndef SECONDARY_MEMORY_NEEDED
4599 return allocno_class
;
4602 enum reg_class cl
, best_cl
= NO_REGS
;
4603 enum reg_class hard_reg_class ATTRIBUTE_UNUSED
4604 = REGNO_REG_CLASS (hard_regno
);
4606 if (! SECONDARY_MEMORY_NEEDED (allocno_class
, allocno_class
, mode
)
4607 && TEST_HARD_REG_BIT (reg_class_contents
[allocno_class
], hard_regno
))
4608 return allocno_class
;
4610 (cl
= reg_class_subclasses
[allocno_class
][i
]) != LIM_REG_CLASSES
;
4612 if (! SECONDARY_MEMORY_NEEDED (cl
, hard_reg_class
, mode
)
4613 && ! SECONDARY_MEMORY_NEEDED (hard_reg_class
, cl
, mode
)
4614 && TEST_HARD_REG_BIT (reg_class_contents
[cl
], hard_regno
)
4615 && (best_cl
== NO_REGS
4616 || ira_class_hard_regs_num
[best_cl
] < ira_class_hard_regs_num
[cl
]))
4622 /* Do split transformations for insn INSN, which defines or uses
4623 ORIGINAL_REGNO. NEXT_USAGE_INSNS specifies which instruction in
4624 the EBB next uses ORIGINAL_REGNO; it has the same form as the
4625 "insns" field of usage_insns.
4627 The transformations look like:
4630 ... s <- p (new insn -- save)
4632 ... p <- s (new insn -- restore)
4633 <- ... p ... <- ... p ...
4635 <- ... p ... <- ... p ...
4636 ... s <- p (new insn -- save)
4638 ... p <- s (new insn -- restore)
4639 <- ... p ... <- ... p ...
4641 where p is an original pseudo got a hard register or a hard
4642 register and s is a new split pseudo. The save is put before INSN
4643 if BEFORE_P is true. Return true if we succeed in such
4646 split_reg (bool before_p
, int original_regno
, rtx insn
, rtx next_usage_insns
)
4648 enum reg_class rclass
;
4650 int hard_regno
, nregs
;
4651 rtx new_reg
, save
, restore
, usage_insn
;
4655 if (original_regno
< FIRST_PSEUDO_REGISTER
)
4657 rclass
= ira_allocno_class_translate
[REGNO_REG_CLASS (original_regno
)];
4658 hard_regno
= original_regno
;
4659 call_save_p
= false;
4664 hard_regno
= reg_renumber
[original_regno
];
4665 nregs
= hard_regno_nregs
[hard_regno
][PSEUDO_REGNO_MODE (original_regno
)];
4666 rclass
= lra_get_allocno_class (original_regno
);
4667 original_reg
= regno_reg_rtx
[original_regno
];
4668 call_save_p
= need_for_call_save_p (original_regno
);
4670 original_reg
= regno_reg_rtx
[original_regno
];
4671 lra_assert (hard_regno
>= 0);
4672 if (lra_dump_file
!= NULL
)
4673 fprintf (lra_dump_file
,
4674 " ((((((((((((((((((((((((((((((((((((((((((((((((\n");
4677 enum machine_mode mode
= GET_MODE (original_reg
);
4679 mode
= HARD_REGNO_CALLER_SAVE_MODE (hard_regno
,
4680 hard_regno_nregs
[hard_regno
][mode
],
4682 new_reg
= lra_create_new_reg (mode
, NULL_RTX
, NO_REGS
, "save");
4686 rclass
= choose_split_class (rclass
, hard_regno
,
4687 GET_MODE (original_reg
));
4688 if (rclass
== NO_REGS
)
4690 if (lra_dump_file
!= NULL
)
4692 fprintf (lra_dump_file
,
4693 " Rejecting split of %d(%s): "
4694 "no good reg class for %d(%s)\n",
4696 reg_class_names
[lra_get_allocno_class (original_regno
)],
4698 reg_class_names
[REGNO_REG_CLASS (hard_regno
)]);
4701 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
4705 new_reg
= lra_create_new_reg (GET_MODE (original_reg
), original_reg
,
4707 reg_renumber
[REGNO (new_reg
)] = hard_regno
;
4709 save
= emit_spill_move (true, new_reg
, original_reg
);
4710 if (NEXT_INSN (save
) != NULL_RTX
)
4712 lra_assert (! call_save_p
);
4713 if (lra_dump_file
!= NULL
)
4717 " Rejecting split %d->%d resulting in > 2 %s save insns:\n",
4718 original_regno
, REGNO (new_reg
), call_save_p
? "call" : "");
4719 dump_rtl_slim (lra_dump_file
, save
, NULL_RTX
, -1, 0);
4720 fprintf (lra_dump_file
,
4721 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
4725 restore
= emit_spill_move (false, new_reg
, original_reg
);
4726 if (NEXT_INSN (restore
) != NULL_RTX
)
4728 lra_assert (! call_save_p
);
4729 if (lra_dump_file
!= NULL
)
4731 fprintf (lra_dump_file
,
4732 " Rejecting split %d->%d "
4733 "resulting in > 2 %s restore insns:\n",
4734 original_regno
, REGNO (new_reg
), call_save_p
? "call" : "");
4735 dump_rtl_slim (lra_dump_file
, restore
, NULL_RTX
, -1, 0);
4736 fprintf (lra_dump_file
,
4737 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
4741 after_p
= usage_insns
[original_regno
].after_p
;
4742 lra_reg_info
[REGNO (new_reg
)].restore_regno
= original_regno
;
4743 bitmap_set_bit (&check_only_regs
, REGNO (new_reg
));
4744 bitmap_set_bit (&check_only_regs
, original_regno
);
4745 bitmap_set_bit (&lra_split_regs
, REGNO (new_reg
));
4748 if (GET_CODE (next_usage_insns
) != INSN_LIST
)
4750 usage_insn
= next_usage_insns
;
4753 usage_insn
= XEXP (next_usage_insns
, 0);
4754 lra_assert (DEBUG_INSN_P (usage_insn
));
4755 next_usage_insns
= XEXP (next_usage_insns
, 1);
4756 substitute_pseudo (&usage_insn
, original_regno
, new_reg
);
4757 lra_update_insn_regno_info (usage_insn
);
4758 if (lra_dump_file
!= NULL
)
4760 fprintf (lra_dump_file
, " Split reuse change %d->%d:\n",
4761 original_regno
, REGNO (new_reg
));
4762 dump_insn_slim (lra_dump_file
, usage_insn
);
4765 lra_assert (NOTE_P (usage_insn
) || NONDEBUG_INSN_P (usage_insn
));
4766 lra_assert (usage_insn
!= insn
|| (after_p
&& before_p
));
4767 lra_process_new_insns (usage_insn
, after_p
? NULL_RTX
: restore
,
4768 after_p
? restore
: NULL_RTX
,
4770 ? "Add reg<-save" : "Add reg<-split");
4771 lra_process_new_insns (insn
, before_p
? save
: NULL_RTX
,
4772 before_p
? NULL_RTX
: save
,
4774 ? "Add save<-reg" : "Add split<-reg");
4776 /* If we are trying to split multi-register. We should check
4777 conflicts on the next assignment sub-pass. IRA can allocate on
4778 sub-register levels, LRA do this on pseudos level right now and
4779 this discrepancy may create allocation conflicts after
4781 lra_risky_transformations_p
= true;
4782 if (lra_dump_file
!= NULL
)
4783 fprintf (lra_dump_file
,
4784 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
4788 /* Recognize that we need a split transformation for insn INSN, which
4789 defines or uses REGNO in its insn biggest MODE (we use it only if
4790 REGNO is a hard register). POTENTIAL_RELOAD_HARD_REGS contains
4791 hard registers which might be used for reloads since the EBB end.
4792 Put the save before INSN if BEFORE_P is true. MAX_UID is maximla
4793 uid before starting INSN processing. Return true if we succeed in
4794 such transformation. */
4796 split_if_necessary (int regno
, enum machine_mode mode
,
4797 HARD_REG_SET potential_reload_hard_regs
,
4798 bool before_p
, rtx insn
, int max_uid
)
4802 rtx next_usage_insns
;
4804 if (regno
< FIRST_PSEUDO_REGISTER
)
4805 nregs
= hard_regno_nregs
[regno
][mode
];
4806 for (i
= 0; i
< nregs
; i
++)
4807 if (usage_insns
[regno
+ i
].check
== curr_usage_insns_check
4808 && (next_usage_insns
= usage_insns
[regno
+ i
].insns
) != NULL_RTX
4809 /* To avoid processing the register twice or more. */
4810 && ((GET_CODE (next_usage_insns
) != INSN_LIST
4811 && INSN_UID (next_usage_insns
) < max_uid
)
4812 || (GET_CODE (next_usage_insns
) == INSN_LIST
4813 && (INSN_UID (XEXP (next_usage_insns
, 0)) < max_uid
)))
4814 && need_for_split_p (potential_reload_hard_regs
, regno
+ i
)
4815 && split_reg (before_p
, regno
+ i
, insn
, next_usage_insns
))
4820 /* Check only registers living at the current program point in the
4822 static bitmap_head live_regs
;
4824 /* Update live info in EBB given by its HEAD and TAIL insns after
4825 inheritance/split transformation. The function removes dead moves
4828 update_ebb_live_info (rtx head
, rtx tail
)
4835 basic_block last_bb
, prev_bb
, curr_bb
;
4837 struct lra_insn_reg
*reg
;
4841 last_bb
= BLOCK_FOR_INSN (tail
);
4843 for (curr_insn
= tail
;
4844 curr_insn
!= PREV_INSN (head
);
4845 curr_insn
= prev_insn
)
4847 prev_insn
= PREV_INSN (curr_insn
);
4848 /* We need to process empty blocks too. They contain
4849 NOTE_INSN_BASIC_BLOCK referring for the basic block. */
4850 if (NOTE_P (curr_insn
) && NOTE_KIND (curr_insn
) != NOTE_INSN_BASIC_BLOCK
)
4852 curr_bb
= BLOCK_FOR_INSN (curr_insn
);
4853 if (curr_bb
!= prev_bb
)
4855 if (prev_bb
!= NULL
)
4857 /* Update df_get_live_in (prev_bb): */
4858 EXECUTE_IF_SET_IN_BITMAP (&check_only_regs
, 0, j
, bi
)
4859 if (bitmap_bit_p (&live_regs
, j
))
4860 bitmap_set_bit (df_get_live_in (prev_bb
), j
);
4862 bitmap_clear_bit (df_get_live_in (prev_bb
), j
);
4864 if (curr_bb
!= last_bb
)
4866 /* Update df_get_live_out (curr_bb): */
4867 EXECUTE_IF_SET_IN_BITMAP (&check_only_regs
, 0, j
, bi
)
4869 live_p
= bitmap_bit_p (&live_regs
, j
);
4871 FOR_EACH_EDGE (e
, ei
, curr_bb
->succs
)
4872 if (bitmap_bit_p (df_get_live_in (e
->dest
), j
))
4878 bitmap_set_bit (df_get_live_out (curr_bb
), j
);
4880 bitmap_clear_bit (df_get_live_out (curr_bb
), j
);
4884 bitmap_and (&live_regs
, &check_only_regs
, df_get_live_out (curr_bb
));
4886 if (! NONDEBUG_INSN_P (curr_insn
))
4888 curr_id
= lra_get_insn_recog_data (curr_insn
);
4890 if ((set
= single_set (curr_insn
)) != NULL_RTX
&& REG_P (SET_DEST (set
))
4891 && (regno
= REGNO (SET_DEST (set
))) >= FIRST_PSEUDO_REGISTER
4892 && bitmap_bit_p (&check_only_regs
, regno
)
4893 && ! bitmap_bit_p (&live_regs
, regno
))
4895 /* See which defined values die here. */
4896 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
4897 if (reg
->type
== OP_OUT
&& ! reg
->subreg_p
)
4898 bitmap_clear_bit (&live_regs
, reg
->regno
);
4899 /* Mark each used value as live. */
4900 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
4901 if (reg
->type
!= OP_OUT
4902 && bitmap_bit_p (&check_only_regs
, reg
->regno
))
4903 bitmap_set_bit (&live_regs
, reg
->regno
);
4904 /* It is quite important to remove dead move insns because it
4905 means removing dead store. We don't need to process them for
4909 if (lra_dump_file
!= NULL
)
4911 fprintf (lra_dump_file
, " Removing dead insn:\n ");
4912 dump_insn_slim (lra_dump_file
, curr_insn
);
4914 lra_set_insn_deleted (curr_insn
);
4919 /* The structure describes info to do an inheritance for the current
4920 insn. We need to collect such info first before doing the
4921 transformations because the transformations change the insn
4922 internal representation. */
4925 /* Original regno. */
4927 /* Subsequent insns which can inherit original reg value. */
4931 /* Array containing all info for doing inheritance from the current
4933 static struct to_inherit to_inherit
[LRA_MAX_INSN_RELOADS
];
4935 /* Number elements in the previous array. */
4936 static int to_inherit_num
;
4938 /* Add inheritance info REGNO and INSNS. Their meaning is described in
4939 structure to_inherit. */
4941 add_to_inherit (int regno
, rtx insns
)
4945 for (i
= 0; i
< to_inherit_num
; i
++)
4946 if (to_inherit
[i
].regno
== regno
)
4948 lra_assert (to_inherit_num
< LRA_MAX_INSN_RELOADS
);
4949 to_inherit
[to_inherit_num
].regno
= regno
;
4950 to_inherit
[to_inherit_num
++].insns
= insns
;
4953 /* Return the last non-debug insn in basic block BB, or the block begin
4956 get_last_insertion_point (basic_block bb
)
4960 FOR_BB_INSNS_REVERSE (bb
, insn
)
4961 if (NONDEBUG_INSN_P (insn
) || NOTE_INSN_BASIC_BLOCK_P (insn
))
4966 /* Set up RES by registers living on edges FROM except the edge (FROM,
4967 TO) or by registers set up in a jump insn in BB FROM. */
4969 get_live_on_other_edges (basic_block from
, basic_block to
, bitmap res
)
4972 struct lra_insn_reg
*reg
;
4976 lra_assert (to
!= NULL
);
4978 FOR_EACH_EDGE (e
, ei
, from
->succs
)
4980 bitmap_ior_into (res
, df_get_live_in (e
->dest
));
4981 last
= get_last_insertion_point (from
);
4982 if (! JUMP_P (last
))
4984 curr_id
= lra_get_insn_recog_data (last
);
4985 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
4986 if (reg
->type
!= OP_IN
)
4987 bitmap_set_bit (res
, reg
->regno
);
4990 /* Used as a temporary results of some bitmap calculations. */
4991 static bitmap_head temp_bitmap
;
4993 /* Do inheritance/split transformations in EBB starting with HEAD and
4994 finishing on TAIL. We process EBB insns in the reverse order.
4995 Return true if we did any inheritance/split transformation in the
4998 We should avoid excessive splitting which results in worse code
4999 because of inaccurate cost calculations for spilling new split
5000 pseudos in such case. To achieve this we do splitting only if
5001 register pressure is high in given basic block and there are reload
5002 pseudos requiring hard registers. We could do more register
5003 pressure calculations at any given program point to avoid necessary
5004 splitting even more but it is to expensive and the current approach
5005 works well enough. */
5007 inherit_in_ebb (rtx head
, rtx tail
)
5009 int i
, src_regno
, dst_regno
, nregs
;
5010 bool change_p
, succ_p
;
5011 rtx prev_insn
, next_usage_insns
, set
, last_insn
;
5013 struct lra_insn_reg
*reg
;
5014 basic_block last_processed_bb
, curr_bb
= NULL
;
5015 HARD_REG_SET potential_reload_hard_regs
, live_hard_regs
;
5019 bool head_p
, after_p
;
5022 curr_usage_insns_check
++;
5023 reloads_num
= calls_num
= 0;
5024 bitmap_clear (&check_only_regs
);
5025 last_processed_bb
= NULL
;
5026 CLEAR_HARD_REG_SET (potential_reload_hard_regs
);
5027 CLEAR_HARD_REG_SET (live_hard_regs
);
5028 /* We don't process new insns generated in the loop. */
5029 for (curr_insn
= tail
; curr_insn
!= PREV_INSN (head
); curr_insn
= prev_insn
)
5031 prev_insn
= PREV_INSN (curr_insn
);
5032 if (BLOCK_FOR_INSN (curr_insn
) != NULL
)
5033 curr_bb
= BLOCK_FOR_INSN (curr_insn
);
5034 if (last_processed_bb
!= curr_bb
)
5036 /* We are at the end of BB. Add qualified living
5037 pseudos for potential splitting. */
5038 to_process
= df_get_live_out (curr_bb
);
5039 if (last_processed_bb
!= NULL
)
5041 /* We are somewhere in the middle of EBB. */
5042 get_live_on_other_edges (curr_bb
, last_processed_bb
,
5044 to_process
= &temp_bitmap
;
5046 last_processed_bb
= curr_bb
;
5047 last_insn
= get_last_insertion_point (curr_bb
);
5048 after_p
= (! JUMP_P (last_insn
)
5049 && (! CALL_P (last_insn
)
5050 || (find_reg_note (last_insn
,
5051 REG_NORETURN
, NULL_RTX
) == NULL_RTX
5052 && ! SIBLING_CALL_P (last_insn
))));
5053 REG_SET_TO_HARD_REG_SET (live_hard_regs
, df_get_live_out (curr_bb
));
5054 IOR_HARD_REG_SET (live_hard_regs
, eliminable_regset
);
5055 IOR_HARD_REG_SET (live_hard_regs
, lra_no_alloc_regs
);
5056 CLEAR_HARD_REG_SET (potential_reload_hard_regs
);
5057 EXECUTE_IF_SET_IN_BITMAP (to_process
, 0, j
, bi
)
5059 if ((int) j
>= lra_constraint_new_regno_start
)
5061 if (j
< FIRST_PSEUDO_REGISTER
|| reg_renumber
[j
] >= 0)
5063 if (j
< FIRST_PSEUDO_REGISTER
)
5064 SET_HARD_REG_BIT (live_hard_regs
, j
);
5066 add_to_hard_reg_set (&live_hard_regs
,
5067 PSEUDO_REGNO_MODE (j
),
5069 setup_next_usage_insn (j
, last_insn
, reloads_num
, after_p
);
5073 src_regno
= dst_regno
= -1;
5074 if (NONDEBUG_INSN_P (curr_insn
)
5075 && (set
= single_set (curr_insn
)) != NULL_RTX
5076 && REG_P (SET_DEST (set
)) && REG_P (SET_SRC (set
)))
5078 src_regno
= REGNO (SET_SRC (set
));
5079 dst_regno
= REGNO (SET_DEST (set
));
5081 if (src_regno
< lra_constraint_new_regno_start
5082 && src_regno
>= FIRST_PSEUDO_REGISTER
5083 && reg_renumber
[src_regno
] < 0
5084 && dst_regno
>= lra_constraint_new_regno_start
5085 && (cl
= lra_get_allocno_class (dst_regno
)) != NO_REGS
)
5087 /* 'reload_pseudo <- original_pseudo'. */
5090 if (usage_insns
[src_regno
].check
== curr_usage_insns_check
5091 && (next_usage_insns
= usage_insns
[src_regno
].insns
) != NULL_RTX
)
5092 succ_p
= inherit_reload_reg (false, src_regno
, cl
,
5093 curr_insn
, next_usage_insns
);
5097 setup_next_usage_insn (src_regno
, curr_insn
, reloads_num
, false);
5098 if (hard_reg_set_subset_p (reg_class_contents
[cl
], live_hard_regs
))
5099 IOR_HARD_REG_SET (potential_reload_hard_regs
,
5100 reg_class_contents
[cl
]);
5102 else if (src_regno
>= lra_constraint_new_regno_start
5103 && dst_regno
< lra_constraint_new_regno_start
5104 && dst_regno
>= FIRST_PSEUDO_REGISTER
5105 && reg_renumber
[dst_regno
] < 0
5106 && (cl
= lra_get_allocno_class (src_regno
)) != NO_REGS
5107 && usage_insns
[dst_regno
].check
== curr_usage_insns_check
5108 && (next_usage_insns
5109 = usage_insns
[dst_regno
].insns
) != NULL_RTX
)
5112 /* 'original_pseudo <- reload_pseudo'. */
5113 if (! JUMP_P (curr_insn
)
5114 && inherit_reload_reg (true, dst_regno
, cl
,
5115 curr_insn
, next_usage_insns
))
5118 usage_insns
[dst_regno
].check
= 0;
5119 if (hard_reg_set_subset_p (reg_class_contents
[cl
], live_hard_regs
))
5120 IOR_HARD_REG_SET (potential_reload_hard_regs
,
5121 reg_class_contents
[cl
]);
5123 else if (INSN_P (curr_insn
))
5126 int max_uid
= get_max_uid ();
5128 curr_id
= lra_get_insn_recog_data (curr_insn
);
5129 curr_static_id
= curr_id
->insn_static_data
;
5131 /* Process insn definitions. */
5132 for (iter
= 0; iter
< 2; iter
++)
5133 for (reg
= iter
== 0 ? curr_id
->regs
: curr_static_id
->hard_regs
;
5136 if (reg
->type
!= OP_IN
5137 && (dst_regno
= reg
->regno
) < lra_constraint_new_regno_start
)
5139 if (dst_regno
>= FIRST_PSEUDO_REGISTER
&& reg
->type
== OP_OUT
5140 && reg_renumber
[dst_regno
] < 0 && ! reg
->subreg_p
5141 && usage_insns
[dst_regno
].check
== curr_usage_insns_check
5142 && (next_usage_insns
5143 = usage_insns
[dst_regno
].insns
) != NULL_RTX
)
5145 struct lra_insn_reg
*r
;
5147 for (r
= curr_id
->regs
; r
!= NULL
; r
= r
->next
)
5148 if (r
->type
!= OP_OUT
&& r
->regno
== dst_regno
)
5150 /* Don't do inheritance if the pseudo is also
5151 used in the insn. */
5153 /* We can not do inheritance right now
5154 because the current insn reg info (chain
5155 regs) can change after that. */
5156 add_to_inherit (dst_regno
, next_usage_insns
);
5158 /* We can not process one reg twice here because of
5159 usage_insns invalidation. */
5160 if ((dst_regno
< FIRST_PSEUDO_REGISTER
5161 || reg_renumber
[dst_regno
] >= 0)
5162 && ! reg
->subreg_p
&& reg
->type
!= OP_IN
)
5166 if (split_if_necessary (dst_regno
, reg
->biggest_mode
,
5167 potential_reload_hard_regs
,
5168 false, curr_insn
, max_uid
))
5170 CLEAR_HARD_REG_SET (s
);
5171 if (dst_regno
< FIRST_PSEUDO_REGISTER
)
5172 add_to_hard_reg_set (&s
, reg
->biggest_mode
, dst_regno
);
5174 add_to_hard_reg_set (&s
, PSEUDO_REGNO_MODE (dst_regno
),
5175 reg_renumber
[dst_regno
]);
5176 AND_COMPL_HARD_REG_SET (live_hard_regs
, s
);
5178 /* We should invalidate potential inheritance or
5179 splitting for the current insn usages to the next
5180 usage insns (see code below) as the output pseudo
5182 if ((dst_regno
>= FIRST_PSEUDO_REGISTER
5183 && reg_renumber
[dst_regno
] < 0)
5184 || (reg
->type
== OP_OUT
&& ! reg
->subreg_p
5185 && (dst_regno
< FIRST_PSEUDO_REGISTER
5186 || reg_renumber
[dst_regno
] >= 0)))
5188 /* Invalidate and mark definitions. */
5189 if (dst_regno
>= FIRST_PSEUDO_REGISTER
)
5190 usage_insns
[dst_regno
].check
= -(int) INSN_UID (curr_insn
);
5193 nregs
= hard_regno_nregs
[dst_regno
][reg
->biggest_mode
];
5194 for (i
= 0; i
< nregs
; i
++)
5195 usage_insns
[dst_regno
+ i
].check
5196 = -(int) INSN_UID (curr_insn
);
5200 if (! JUMP_P (curr_insn
))
5201 for (i
= 0; i
< to_inherit_num
; i
++)
5202 if (inherit_reload_reg (true, to_inherit
[i
].regno
,
5203 ALL_REGS
, curr_insn
,
5204 to_inherit
[i
].insns
))
5206 if (CALL_P (curr_insn
))
5208 rtx cheap
, pat
, dest
, restore
;
5209 int regno
, hard_regno
;
5212 if ((cheap
= find_reg_note (curr_insn
,
5213 REG_RETURNED
, NULL_RTX
)) != NULL_RTX
5214 && ((cheap
= XEXP (cheap
, 0)), true)
5215 && (regno
= REGNO (cheap
)) >= FIRST_PSEUDO_REGISTER
5216 && (hard_regno
= reg_renumber
[regno
]) >= 0
5217 /* If there are pending saves/restores, the
5218 optimization is not worth. */
5219 && usage_insns
[regno
].calls_num
== calls_num
- 1
5220 && TEST_HARD_REG_BIT (call_used_reg_set
, hard_regno
))
5222 /* Restore the pseudo from the call result as
5223 REG_RETURNED note says that the pseudo value is
5224 in the call result and the pseudo is an argument
5226 pat
= PATTERN (curr_insn
);
5227 if (GET_CODE (pat
) == PARALLEL
)
5228 pat
= XVECEXP (pat
, 0, 0);
5229 dest
= SET_DEST (pat
);
5231 emit_move_insn (cheap
, copy_rtx (dest
));
5232 restore
= get_insns ();
5234 lra_process_new_insns (curr_insn
, NULL
, restore
,
5235 "Inserting call parameter restore");
5236 /* We don't need to save/restore of the pseudo from
5238 usage_insns
[regno
].calls_num
= calls_num
;
5239 bitmap_set_bit (&check_only_regs
, regno
);
5243 /* Process insn usages. */
5244 for (iter
= 0; iter
< 2; iter
++)
5245 for (reg
= iter
== 0 ? curr_id
->regs
: curr_static_id
->hard_regs
;
5248 if ((reg
->type
!= OP_OUT
5249 || (reg
->type
== OP_OUT
&& reg
->subreg_p
))
5250 && (src_regno
= reg
->regno
) < lra_constraint_new_regno_start
)
5252 if (src_regno
>= FIRST_PSEUDO_REGISTER
5253 && reg_renumber
[src_regno
] < 0 && reg
->type
== OP_IN
)
5255 if (usage_insns
[src_regno
].check
== curr_usage_insns_check
5256 && (next_usage_insns
5257 = usage_insns
[src_regno
].insns
) != NULL_RTX
5258 && NONDEBUG_INSN_P (curr_insn
))
5259 add_to_inherit (src_regno
, next_usage_insns
);
5260 else if (usage_insns
[src_regno
].check
5261 != -(int) INSN_UID (curr_insn
))
5262 /* Add usages but only if the reg is not set up
5263 in the same insn. */
5264 add_next_usage_insn (src_regno
, curr_insn
, reloads_num
);
5266 else if (src_regno
< FIRST_PSEUDO_REGISTER
5267 || reg_renumber
[src_regno
] >= 0)
5270 rtx use_insn
= curr_insn
;
5272 before_p
= (JUMP_P (curr_insn
)
5273 || (CALL_P (curr_insn
) && reg
->type
== OP_IN
));
5274 if (NONDEBUG_INSN_P (curr_insn
)
5275 && split_if_necessary (src_regno
, reg
->biggest_mode
,
5276 potential_reload_hard_regs
,
5277 before_p
, curr_insn
, max_uid
))
5280 lra_risky_transformations_p
= true;
5283 usage_insns
[src_regno
].check
= 0;
5285 use_insn
= PREV_INSN (curr_insn
);
5287 if (NONDEBUG_INSN_P (curr_insn
))
5289 if (src_regno
< FIRST_PSEUDO_REGISTER
)
5290 add_to_hard_reg_set (&live_hard_regs
,
5291 reg
->biggest_mode
, src_regno
);
5293 add_to_hard_reg_set (&live_hard_regs
,
5294 PSEUDO_REGNO_MODE (src_regno
),
5295 reg_renumber
[src_regno
]);
5297 add_next_usage_insn (src_regno
, use_insn
, reloads_num
);
5300 for (i
= 0; i
< to_inherit_num
; i
++)
5302 src_regno
= to_inherit
[i
].regno
;
5303 if (inherit_reload_reg (false, src_regno
, ALL_REGS
,
5304 curr_insn
, to_inherit
[i
].insns
))
5307 setup_next_usage_insn (src_regno
, curr_insn
, reloads_num
, false);
5310 /* We reached the start of the current basic block. */
5311 if (prev_insn
== NULL_RTX
|| prev_insn
== PREV_INSN (head
)
5312 || BLOCK_FOR_INSN (prev_insn
) != curr_bb
)
5314 /* We reached the beginning of the current block -- do
5315 rest of spliting in the current BB. */
5316 to_process
= df_get_live_in (curr_bb
);
5317 if (BLOCK_FOR_INSN (head
) != curr_bb
)
5319 /* We are somewhere in the middle of EBB. */
5320 get_live_on_other_edges (EDGE_PRED (curr_bb
, 0)->src
,
5321 curr_bb
, &temp_bitmap
);
5322 to_process
= &temp_bitmap
;
5325 EXECUTE_IF_SET_IN_BITMAP (to_process
, 0, j
, bi
)
5327 if ((int) j
>= lra_constraint_new_regno_start
)
5329 if (((int) j
< FIRST_PSEUDO_REGISTER
|| reg_renumber
[j
] >= 0)
5330 && usage_insns
[j
].check
== curr_usage_insns_check
5331 && (next_usage_insns
= usage_insns
[j
].insns
) != NULL_RTX
)
5333 if (need_for_split_p (potential_reload_hard_regs
, j
))
5335 if (lra_dump_file
!= NULL
&& head_p
)
5337 fprintf (lra_dump_file
,
5338 " ----------------------------------\n");
5341 if (split_reg (false, j
, bb_note (curr_bb
),
5345 usage_insns
[j
].check
= 0;
5353 /* This value affects EBB forming. If probability of edge from EBB to
5354 a BB is not greater than the following value, we don't add the BB
5356 #define EBB_PROBABILITY_CUTOFF ((REG_BR_PROB_BASE * 50) / 100)
5358 /* Current number of inheritance/split iteration. */
5359 int lra_inheritance_iter
;
5361 /* Entry function for inheritance/split pass. */
5363 lra_inheritance (void)
5366 basic_block bb
, start_bb
;
5369 lra_inheritance_iter
++;
5370 if (lra_inheritance_iter
> LRA_MAX_INHERITANCE_PASSES
)
5372 timevar_push (TV_LRA_INHERITANCE
);
5373 if (lra_dump_file
!= NULL
)
5374 fprintf (lra_dump_file
, "\n********** Inheritance #%d: **********\n\n",
5375 lra_inheritance_iter
);
5376 curr_usage_insns_check
= 0;
5377 usage_insns
= XNEWVEC (struct usage_insns
, lra_constraint_new_regno_start
);
5378 for (i
= 0; i
< lra_constraint_new_regno_start
; i
++)
5379 usage_insns
[i
].check
= 0;
5380 bitmap_initialize (&check_only_regs
, ®_obstack
);
5381 bitmap_initialize (&live_regs
, ®_obstack
);
5382 bitmap_initialize (&temp_bitmap
, ®_obstack
);
5383 bitmap_initialize (&ebb_global_regs
, ®_obstack
);
5384 FOR_EACH_BB_FN (bb
, cfun
)
5387 if (lra_dump_file
!= NULL
)
5388 fprintf (lra_dump_file
, "EBB");
5389 /* Form a EBB starting with BB. */
5390 bitmap_clear (&ebb_global_regs
);
5391 bitmap_ior_into (&ebb_global_regs
, df_get_live_in (bb
));
5394 if (lra_dump_file
!= NULL
)
5395 fprintf (lra_dump_file
, " %d", bb
->index
);
5396 if (bb
->next_bb
== EXIT_BLOCK_PTR_FOR_FN (cfun
)
5397 || LABEL_P (BB_HEAD (bb
->next_bb
)))
5399 e
= find_fallthru_edge (bb
->succs
);
5402 if (e
->probability
<= EBB_PROBABILITY_CUTOFF
)
5406 bitmap_ior_into (&ebb_global_regs
, df_get_live_out (bb
));
5407 if (lra_dump_file
!= NULL
)
5408 fprintf (lra_dump_file
, "\n");
5409 if (inherit_in_ebb (BB_HEAD (start_bb
), BB_END (bb
)))
5410 /* Remember that the EBB head and tail can change in
5412 update_ebb_live_info (BB_HEAD (start_bb
), BB_END (bb
));
5414 bitmap_clear (&ebb_global_regs
);
5415 bitmap_clear (&temp_bitmap
);
5416 bitmap_clear (&live_regs
);
5417 bitmap_clear (&check_only_regs
);
5420 timevar_pop (TV_LRA_INHERITANCE
);
5425 /* This page contains code to undo failed inheritance/split
5428 /* Current number of iteration undoing inheritance/split. */
5429 int lra_undo_inheritance_iter
;
5431 /* Fix BB live info LIVE after removing pseudos created on pass doing
5432 inheritance/split which are REMOVED_PSEUDOS. */
5434 fix_bb_live_info (bitmap live
, bitmap removed_pseudos
)
5439 EXECUTE_IF_SET_IN_BITMAP (removed_pseudos
, 0, regno
, bi
)
5440 if (bitmap_clear_bit (live
, regno
))
5441 bitmap_set_bit (live
, lra_reg_info
[regno
].restore_regno
);
5444 /* Return regno of the (subreg of) REG. Otherwise, return a negative
5449 if (GET_CODE (reg
) == SUBREG
)
5450 reg
= SUBREG_REG (reg
);
5456 /* Remove inheritance/split pseudos which are in REMOVE_PSEUDOS and
5457 return true if we did any change. The undo transformations for
5458 inheritance looks like
5462 p <- i, i <- p, and i <- i3
5463 where p is original pseudo from which inheritance pseudo i was
5464 created, i and i3 are removed inheritance pseudos, i2 is another
5465 not removed inheritance pseudo. All split pseudos or other
5466 occurrences of removed inheritance pseudos are changed on the
5467 corresponding original pseudos.
5469 The function also schedules insns changed and created during
5470 inheritance/split pass for processing by the subsequent constraint
5473 remove_inheritance_pseudos (bitmap remove_pseudos
)
5476 int regno
, sregno
, prev_sregno
, dregno
, restore_regno
;
5477 rtx set
, prev_set
, prev_insn
;
5478 bool change_p
, done_p
;
5480 change_p
= ! bitmap_empty_p (remove_pseudos
);
5481 /* We can not finish the function right away if CHANGE_P is true
5482 because we need to marks insns affected by previous
5483 inheritance/split pass for processing by the subsequent
5485 FOR_EACH_BB_FN (bb
, cfun
)
5487 fix_bb_live_info (df_get_live_in (bb
), remove_pseudos
);
5488 fix_bb_live_info (df_get_live_out (bb
), remove_pseudos
);
5489 FOR_BB_INSNS_REVERSE (bb
, curr_insn
)
5491 if (! INSN_P (curr_insn
))
5494 sregno
= dregno
= -1;
5495 if (change_p
&& NONDEBUG_INSN_P (curr_insn
)
5496 && (set
= single_set (curr_insn
)) != NULL_RTX
)
5498 dregno
= get_regno (SET_DEST (set
));
5499 sregno
= get_regno (SET_SRC (set
));
5502 if (sregno
>= 0 && dregno
>= 0)
5504 if ((bitmap_bit_p (remove_pseudos
, sregno
)
5505 && (lra_reg_info
[sregno
].restore_regno
== dregno
5506 || (bitmap_bit_p (remove_pseudos
, dregno
)
5507 && (lra_reg_info
[sregno
].restore_regno
5508 == lra_reg_info
[dregno
].restore_regno
))))
5509 || (bitmap_bit_p (remove_pseudos
, dregno
)
5510 && lra_reg_info
[dregno
].restore_regno
== sregno
))
5511 /* One of the following cases:
5512 original <- removed inheritance pseudo
5513 removed inherit pseudo <- another removed inherit pseudo
5514 removed inherit pseudo <- original pseudo
5516 removed_split_pseudo <- original_reg
5517 original_reg <- removed_split_pseudo */
5519 if (lra_dump_file
!= NULL
)
5521 fprintf (lra_dump_file
, " Removing %s:\n",
5522 bitmap_bit_p (&lra_split_regs
, sregno
)
5523 || bitmap_bit_p (&lra_split_regs
, dregno
)
5524 ? "split" : "inheritance");
5525 dump_insn_slim (lra_dump_file
, curr_insn
);
5527 lra_set_insn_deleted (curr_insn
);
5530 else if (bitmap_bit_p (remove_pseudos
, sregno
)
5531 && bitmap_bit_p (&lra_inheritance_pseudos
, sregno
))
5533 /* Search the following pattern:
5534 inherit_or_split_pseudo1 <- inherit_or_split_pseudo2
5535 original_pseudo <- inherit_or_split_pseudo1
5536 where the 2nd insn is the current insn and
5537 inherit_or_split_pseudo2 is not removed. If it is found,
5538 change the current insn onto:
5539 original_pseudo <- inherit_or_split_pseudo2. */
5540 for (prev_insn
= PREV_INSN (curr_insn
);
5541 prev_insn
!= NULL_RTX
&& ! NONDEBUG_INSN_P (prev_insn
);
5542 prev_insn
= PREV_INSN (prev_insn
))
5544 if (prev_insn
!= NULL_RTX
&& BLOCK_FOR_INSN (prev_insn
) == bb
5545 && (prev_set
= single_set (prev_insn
)) != NULL_RTX
5546 /* There should be no subregs in insn we are
5547 searching because only the original reg might
5548 be in subreg when we changed the mode of
5549 load/store for splitting. */
5550 && REG_P (SET_DEST (prev_set
))
5551 && REG_P (SET_SRC (prev_set
))
5552 && (int) REGNO (SET_DEST (prev_set
)) == sregno
5553 && ((prev_sregno
= REGNO (SET_SRC (prev_set
)))
5554 >= FIRST_PSEUDO_REGISTER
)
5555 /* As we consider chain of inheritance or
5556 splitting described in above comment we should
5557 check that sregno and prev_sregno were
5558 inheritance/split pseudos created from the
5559 same original regno. */
5560 && (lra_reg_info
[sregno
].restore_regno
5561 == lra_reg_info
[prev_sregno
].restore_regno
)
5562 && ! bitmap_bit_p (remove_pseudos
, prev_sregno
))
5564 lra_assert (GET_MODE (SET_SRC (prev_set
))
5565 == GET_MODE (regno_reg_rtx
[sregno
]));
5566 if (GET_CODE (SET_SRC (set
)) == SUBREG
)
5567 SUBREG_REG (SET_SRC (set
)) = SET_SRC (prev_set
);
5569 SET_SRC (set
) = SET_SRC (prev_set
);
5570 lra_push_insn_and_update_insn_regno_info (curr_insn
);
5571 lra_set_used_insn_alternative_by_uid
5572 (INSN_UID (curr_insn
), -1);
5574 if (lra_dump_file
!= NULL
)
5576 fprintf (lra_dump_file
, " Change reload insn:\n");
5577 dump_insn_slim (lra_dump_file
, curr_insn
);
5584 struct lra_insn_reg
*reg
;
5585 bool restored_regs_p
= false;
5586 bool kept_regs_p
= false;
5588 curr_id
= lra_get_insn_recog_data (curr_insn
);
5589 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
5592 restore_regno
= lra_reg_info
[regno
].restore_regno
;
5593 if (restore_regno
>= 0)
5595 if (change_p
&& bitmap_bit_p (remove_pseudos
, regno
))
5597 substitute_pseudo (&curr_insn
, regno
,
5598 regno_reg_rtx
[restore_regno
]);
5599 restored_regs_p
= true;
5605 if (NONDEBUG_INSN_P (curr_insn
) && kept_regs_p
)
5607 /* The instruction has changed since the previous
5608 constraints pass. */
5609 lra_push_insn_and_update_insn_regno_info (curr_insn
);
5610 lra_set_used_insn_alternative_by_uid
5611 (INSN_UID (curr_insn
), -1);
5613 else if (restored_regs_p
)
5614 /* The instruction has been restored to the form that
5615 it had during the previous constraints pass. */
5616 lra_update_insn_regno_info (curr_insn
);
5617 if (restored_regs_p
&& lra_dump_file
!= NULL
)
5619 fprintf (lra_dump_file
, " Insn after restoring regs:\n");
5620 dump_insn_slim (lra_dump_file
, curr_insn
);
5628 /* If optional reload pseudos failed to get a hard register or was not
5629 inherited, it is better to remove optional reloads. We do this
5630 transformation after undoing inheritance to figure out necessity to
5631 remove optional reloads easier. Return true if we do any
5634 undo_optional_reloads (void)
5636 bool change_p
, keep_p
;
5637 unsigned int regno
, uid
;
5638 bitmap_iterator bi
, bi2
;
5639 rtx insn
, set
, src
, dest
;
5640 bitmap_head removed_optional_reload_pseudos
, insn_bitmap
;
5642 bitmap_initialize (&removed_optional_reload_pseudos
, ®_obstack
);
5643 bitmap_copy (&removed_optional_reload_pseudos
, &lra_optional_reload_pseudos
);
5644 EXECUTE_IF_SET_IN_BITMAP (&lra_optional_reload_pseudos
, 0, regno
, bi
)
5647 /* Keep optional reloads from previous subpasses. */
5648 if (lra_reg_info
[regno
].restore_regno
< 0
5649 /* If the original pseudo changed its allocation, just
5650 removing the optional pseudo is dangerous as the original
5651 pseudo will have longer live range. */
5652 || reg_renumber
[lra_reg_info
[regno
].restore_regno
] >= 0)
5654 else if (reg_renumber
[regno
] >= 0)
5655 EXECUTE_IF_SET_IN_BITMAP (&lra_reg_info
[regno
].insn_bitmap
, 0, uid
, bi2
)
5657 insn
= lra_insn_recog_data
[uid
]->insn
;
5658 if ((set
= single_set (insn
)) == NULL_RTX
)
5660 src
= SET_SRC (set
);
5661 dest
= SET_DEST (set
);
5662 if (! REG_P (src
) || ! REG_P (dest
))
5664 if (REGNO (dest
) == regno
5665 /* Ignore insn for optional reloads itself. */
5666 && lra_reg_info
[regno
].restore_regno
!= (int) REGNO (src
)
5667 /* Check only inheritance on last inheritance pass. */
5668 && (int) REGNO (src
) >= new_regno_start
5669 /* Check that the optional reload was inherited. */
5670 && bitmap_bit_p (&lra_inheritance_pseudos
, REGNO (src
)))
5678 bitmap_clear_bit (&removed_optional_reload_pseudos
, regno
);
5679 if (lra_dump_file
!= NULL
)
5680 fprintf (lra_dump_file
, "Keep optional reload reg %d\n", regno
);
5683 change_p
= ! bitmap_empty_p (&removed_optional_reload_pseudos
);
5684 bitmap_initialize (&insn_bitmap
, ®_obstack
);
5685 EXECUTE_IF_SET_IN_BITMAP (&removed_optional_reload_pseudos
, 0, regno
, bi
)
5687 if (lra_dump_file
!= NULL
)
5688 fprintf (lra_dump_file
, "Remove optional reload reg %d\n", regno
);
5689 bitmap_copy (&insn_bitmap
, &lra_reg_info
[regno
].insn_bitmap
);
5690 EXECUTE_IF_SET_IN_BITMAP (&insn_bitmap
, 0, uid
, bi2
)
5692 insn
= lra_insn_recog_data
[uid
]->insn
;
5693 if ((set
= single_set (insn
)) != NULL_RTX
)
5695 src
= SET_SRC (set
);
5696 dest
= SET_DEST (set
);
5697 if (REG_P (src
) && REG_P (dest
)
5698 && ((REGNO (src
) == regno
5699 && (lra_reg_info
[regno
].restore_regno
5700 == (int) REGNO (dest
)))
5701 || (REGNO (dest
) == regno
5702 && (lra_reg_info
[regno
].restore_regno
5703 == (int) REGNO (src
)))))
5705 if (lra_dump_file
!= NULL
)
5707 fprintf (lra_dump_file
, " Deleting move %u\n",
5709 dump_insn_slim (lra_dump_file
, insn
);
5711 lra_set_insn_deleted (insn
);
5714 /* We should not worry about generation memory-memory
5715 moves here as if the corresponding inheritance did
5716 not work (inheritance pseudo did not get a hard reg),
5717 we remove the inheritance pseudo and the optional
5720 substitute_pseudo (&insn
, regno
,
5721 regno_reg_rtx
[lra_reg_info
[regno
].restore_regno
]);
5722 lra_update_insn_regno_info (insn
);
5723 if (lra_dump_file
!= NULL
)
5725 fprintf (lra_dump_file
,
5726 " Restoring original insn:\n");
5727 dump_insn_slim (lra_dump_file
, insn
);
5731 /* Clear restore_regnos. */
5732 EXECUTE_IF_SET_IN_BITMAP (&lra_optional_reload_pseudos
, 0, regno
, bi
)
5733 lra_reg_info
[regno
].restore_regno
= -1;
5734 bitmap_clear (&insn_bitmap
);
5735 bitmap_clear (&removed_optional_reload_pseudos
);
5739 /* Entry function for undoing inheritance/split transformation. Return true
5740 if we did any RTL change in this pass. */
5742 lra_undo_inheritance (void)
5745 int restore_regno
, hard_regno
;
5746 int n_all_inherit
, n_inherit
, n_all_split
, n_split
;
5747 bitmap_head remove_pseudos
;
5751 lra_undo_inheritance_iter
++;
5752 if (lra_undo_inheritance_iter
> LRA_MAX_INHERITANCE_PASSES
)
5754 if (lra_dump_file
!= NULL
)
5755 fprintf (lra_dump_file
,
5756 "\n********** Undoing inheritance #%d: **********\n\n",
5757 lra_undo_inheritance_iter
);
5758 bitmap_initialize (&remove_pseudos
, ®_obstack
);
5759 n_inherit
= n_all_inherit
= 0;
5760 EXECUTE_IF_SET_IN_BITMAP (&lra_inheritance_pseudos
, 0, regno
, bi
)
5761 if (lra_reg_info
[regno
].restore_regno
>= 0)
5764 if (reg_renumber
[regno
] < 0
5765 /* If the original pseudo changed its allocation, just
5766 removing inheritance is dangerous as for changing
5767 allocation we used shorter live-ranges. */
5768 && reg_renumber
[lra_reg_info
[regno
].restore_regno
] < 0)
5769 bitmap_set_bit (&remove_pseudos
, regno
);
5773 if (lra_dump_file
!= NULL
&& n_all_inherit
!= 0)
5774 fprintf (lra_dump_file
, "Inherit %d out of %d (%.2f%%)\n",
5775 n_inherit
, n_all_inherit
,
5776 (double) n_inherit
/ n_all_inherit
* 100);
5777 n_split
= n_all_split
= 0;
5778 EXECUTE_IF_SET_IN_BITMAP (&lra_split_regs
, 0, regno
, bi
)
5779 if ((restore_regno
= lra_reg_info
[regno
].restore_regno
) >= 0)
5782 hard_regno
= (restore_regno
>= FIRST_PSEUDO_REGISTER
5783 ? reg_renumber
[restore_regno
] : restore_regno
);
5784 if (hard_regno
< 0 || reg_renumber
[regno
] == hard_regno
)
5785 bitmap_set_bit (&remove_pseudos
, regno
);
5789 if (lra_dump_file
!= NULL
)
5790 fprintf (lra_dump_file
, " Keep split r%d (orig=r%d)\n",
5791 regno
, restore_regno
);
5794 if (lra_dump_file
!= NULL
&& n_all_split
!= 0)
5795 fprintf (lra_dump_file
, "Split %d out of %d (%.2f%%)\n",
5796 n_split
, n_all_split
,
5797 (double) n_split
/ n_all_split
* 100);
5798 change_p
= remove_inheritance_pseudos (&remove_pseudos
);
5799 bitmap_clear (&remove_pseudos
);
5800 /* Clear restore_regnos. */
5801 EXECUTE_IF_SET_IN_BITMAP (&lra_inheritance_pseudos
, 0, regno
, bi
)
5802 lra_reg_info
[regno
].restore_regno
= -1;
5803 EXECUTE_IF_SET_IN_BITMAP (&lra_split_regs
, 0, regno
, bi
)
5804 lra_reg_info
[regno
].restore_regno
= -1;
5805 change_p
= undo_optional_reloads () || change_p
;