1 /* Code for RTL transformations to satisfy insn constraints.
2 Copyright (C) 2010-2014 Free Software Foundation, Inc.
3 Contributed by Vladimir Makarov <vmakarov@redhat.com>.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 3, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
22 /* This file contains code for 3 passes: constraint pass,
23 inheritance/split pass, and pass for undoing failed inheritance and
26 The major goal of constraint pass is to transform RTL to satisfy
27 insn and address constraints by:
28 o choosing insn alternatives;
29 o generating *reload insns* (or reloads in brief) and *reload
30 pseudos* which will get necessary hard registers later;
31 o substituting pseudos with equivalent values and removing the
32 instructions that initialized those pseudos.
34 The constraint pass has biggest and most complicated code in LRA.
35 There are a lot of important details like:
36 o reuse of input reload pseudos to simplify reload pseudo
38 o some heuristics to choose insn alternative to improve the
42 The pass is mimicking former reload pass in alternative choosing
43 because the reload pass is oriented to current machine description
44 model. It might be changed if the machine description model is
47 There is special code for preventing all LRA and this pass cycling
50 On the first iteration of the pass we process every instruction and
51 choose an alternative for each one. On subsequent iterations we try
52 to avoid reprocessing instructions if we can be sure that the old
53 choice is still valid.
55 The inheritance/spilt pass is to transform code to achieve
56 ineheritance and live range splitting. It is done on backward
59 The inheritance optimization goal is to reuse values in hard
60 registers. There is analogous optimization in old reload pass. The
61 inheritance is achieved by following transformation:
63 reload_p1 <- p reload_p1 <- p
64 ... new_p <- reload_p1
66 reload_p2 <- p reload_p2 <- new_p
68 where p is spilled and not changed between the insns. Reload_p1 is
69 also called *original pseudo* and new_p is called *inheritance
72 The subsequent assignment pass will try to assign the same (or
73 another if it is not possible) hard register to new_p as to
74 reload_p1 or reload_p2.
76 If the assignment pass fails to assign a hard register to new_p,
77 this file will undo the inheritance and restore the original code.
78 This is because implementing the above sequence with a spilled
79 new_p would make the code much worse. The inheritance is done in
80 EBB scope. The above is just a simplified example to get an idea
81 of the inheritance as the inheritance is also done for non-reload
84 Splitting (transformation) is also done in EBB scope on the same
85 pass as the inheritance:
87 r <- ... or ... <- r r <- ... or ... <- r
88 ... s <- r (new insn -- save)
90 ... r <- s (new insn -- restore)
93 The *split pseudo* s is assigned to the hard register of the
94 original pseudo or hard register r.
97 o In EBBs with high register pressure for global pseudos (living
98 in at least 2 BBs) and assigned to hard registers when there
99 are more one reloads needing the hard registers;
100 o for pseudos needing save/restore code around calls.
102 If the split pseudo still has the same hard register as the
103 original pseudo after the subsequent assignment pass or the
104 original pseudo was split, the opposite transformation is done on
105 the same pass for undoing inheritance. */
111 #include "coretypes.h"
113 #include "hard-reg-set.h"
117 #include "insn-config.h"
118 #include "insn-codes.h"
121 #include "addresses.h"
123 #include "function.h"
125 #include "basic-block.h"
130 #include "rtl-error.h"
133 /* Value of LRA_CURR_RELOAD_NUM at the beginning of BB of the current
134 insn. Remember that LRA_CURR_RELOAD_NUM is the number of emitted
136 static int bb_reload_num
;
138 /* The current insn being processed and corresponding its single set
139 (NULL otherwise), its data (basic block, the insn data, the insn
140 static data, and the mode of each operand). */
141 static rtx curr_insn
;
142 static rtx curr_insn_set
;
143 static basic_block curr_bb
;
144 static lra_insn_recog_data_t curr_id
;
145 static struct lra_static_insn_data
*curr_static_id
;
146 static enum machine_mode curr_operand_mode
[MAX_RECOG_OPERANDS
];
150 /* Start numbers for new registers and insns at the current constraints
152 static int new_regno_start
;
153 static int new_insn_uid_start
;
155 /* If LOC is nonnull, strip any outer subreg from it. */
157 strip_subreg (rtx
*loc
)
159 return loc
&& GET_CODE (*loc
) == SUBREG
? &SUBREG_REG (*loc
) : loc
;
162 /* Return hard regno of REGNO or if it is was not assigned to a hard
163 register, use a hard register from its allocno class. */
165 get_try_hard_regno (int regno
)
168 enum reg_class rclass
;
170 if ((hard_regno
= regno
) >= FIRST_PSEUDO_REGISTER
)
171 hard_regno
= lra_get_regno_hard_regno (regno
);
174 rclass
= lra_get_allocno_class (regno
);
175 if (rclass
== NO_REGS
)
177 return ira_class_hard_regs
[rclass
][0];
180 /* Return final hard regno (plus offset) which will be after
181 elimination. We do this for matching constraints because the final
182 hard regno could have a different class. */
184 get_final_hard_regno (int hard_regno
, int offset
)
188 hard_regno
= lra_get_elimination_hard_regno (hard_regno
);
189 return hard_regno
+ offset
;
192 /* Return hard regno of X after removing subreg and making
193 elimination. If X is not a register or subreg of register, return
194 -1. For pseudo use its assignment. */
196 get_hard_regno (rtx x
)
199 int offset
, hard_regno
;
202 if (GET_CODE (x
) == SUBREG
)
203 reg
= SUBREG_REG (x
);
206 if ((hard_regno
= REGNO (reg
)) >= FIRST_PSEUDO_REGISTER
)
207 hard_regno
= lra_get_regno_hard_regno (hard_regno
);
211 if (GET_CODE (x
) == SUBREG
)
212 offset
+= subreg_regno_offset (hard_regno
, GET_MODE (reg
),
213 SUBREG_BYTE (x
), GET_MODE (x
));
214 return get_final_hard_regno (hard_regno
, offset
);
217 /* If REGNO is a hard register or has been allocated a hard register,
218 return the class of that register. If REGNO is a reload pseudo
219 created by the current constraints pass, return its allocno class.
220 Return NO_REGS otherwise. */
221 static enum reg_class
222 get_reg_class (int regno
)
226 if ((hard_regno
= regno
) >= FIRST_PSEUDO_REGISTER
)
227 hard_regno
= lra_get_regno_hard_regno (regno
);
230 hard_regno
= get_final_hard_regno (hard_regno
, 0);
231 return REGNO_REG_CLASS (hard_regno
);
233 if (regno
>= new_regno_start
)
234 return lra_get_allocno_class (regno
);
238 /* Return true if REG satisfies (or will satisfy) reg class constraint
239 CL. Use elimination first if REG is a hard register. If REG is a
240 reload pseudo created by this constraints pass, assume that it will
241 be allocated a hard register from its allocno class, but allow that
242 class to be narrowed to CL if it is currently a superset of CL.
244 If NEW_CLASS is nonnull, set *NEW_CLASS to the new allocno class of
245 REGNO (reg), or NO_REGS if no change in its class was needed. */
247 in_class_p (rtx reg
, enum reg_class cl
, enum reg_class
*new_class
)
249 enum reg_class rclass
, common_class
;
250 enum machine_mode reg_mode
;
251 int class_size
, hard_regno
, nregs
, i
, j
;
252 int regno
= REGNO (reg
);
254 if (new_class
!= NULL
)
255 *new_class
= NO_REGS
;
256 if (regno
< FIRST_PSEUDO_REGISTER
)
259 rtx
*final_loc
= &final_reg
;
261 lra_eliminate_reg_if_possible (final_loc
);
262 return TEST_HARD_REG_BIT (reg_class_contents
[cl
], REGNO (*final_loc
));
264 reg_mode
= GET_MODE (reg
);
265 rclass
= get_reg_class (regno
);
266 if (regno
< new_regno_start
267 /* Do not allow the constraints for reload instructions to
268 influence the classes of new pseudos. These reloads are
269 typically moves that have many alternatives, and restricting
270 reload pseudos for one alternative may lead to situations
271 where other reload pseudos are no longer allocatable. */
272 || (INSN_UID (curr_insn
) >= new_insn_uid_start
273 && curr_insn_set
!= NULL
274 && ((OBJECT_P (SET_SRC (curr_insn_set
))
275 && ! CONSTANT_P (SET_SRC (curr_insn_set
)))
276 || (GET_CODE (SET_SRC (curr_insn_set
)) == SUBREG
277 && OBJECT_P (SUBREG_REG (SET_SRC (curr_insn_set
)))
278 && ! CONSTANT_P (SUBREG_REG (SET_SRC (curr_insn_set
)))))))
279 /* When we don't know what class will be used finally for reload
280 pseudos, we use ALL_REGS. */
281 return ((regno
>= new_regno_start
&& rclass
== ALL_REGS
)
282 || (rclass
!= NO_REGS
&& ira_class_subset_p
[rclass
][cl
]
283 && ! hard_reg_set_subset_p (reg_class_contents
[cl
],
284 lra_no_alloc_regs
)));
287 common_class
= ira_reg_class_subset
[rclass
][cl
];
288 if (new_class
!= NULL
)
289 *new_class
= common_class
;
290 if (hard_reg_set_subset_p (reg_class_contents
[common_class
],
293 /* Check that there are enough allocatable regs. */
294 class_size
= ira_class_hard_regs_num
[common_class
];
295 for (i
= 0; i
< class_size
; i
++)
297 hard_regno
= ira_class_hard_regs
[common_class
][i
];
298 nregs
= hard_regno_nregs
[hard_regno
][reg_mode
];
301 for (j
= 0; j
< nregs
; j
++)
302 if (TEST_HARD_REG_BIT (lra_no_alloc_regs
, hard_regno
+ j
)
303 || ! TEST_HARD_REG_BIT (reg_class_contents
[common_class
],
313 /* Return true if REGNO satisfies a memory constraint. */
317 return get_reg_class (regno
) == NO_REGS
;
320 /* Initiate equivalences for LRA. As we keep original equivalences
321 before any elimination, we need to make copies otherwise any change
322 in insns might change the equivalences. */
324 lra_init_equiv (void)
326 ira_expand_reg_equiv ();
327 for (int i
= FIRST_PSEUDO_REGISTER
; i
< max_reg_num (); i
++)
331 if ((res
= ira_reg_equiv
[i
].memory
) != NULL_RTX
)
332 ira_reg_equiv
[i
].memory
= copy_rtx (res
);
333 if ((res
= ira_reg_equiv
[i
].invariant
) != NULL_RTX
)
334 ira_reg_equiv
[i
].invariant
= copy_rtx (res
);
338 static rtx
loc_equivalence_callback (rtx
, const_rtx
, void *);
340 /* Update equivalence for REGNO. We need to this as the equivalence
341 might contain other pseudos which are changed by their
344 update_equiv (int regno
)
348 if ((x
= ira_reg_equiv
[regno
].memory
) != NULL_RTX
)
349 ira_reg_equiv
[regno
].memory
350 = simplify_replace_fn_rtx (x
, NULL_RTX
, loc_equivalence_callback
,
352 if ((x
= ira_reg_equiv
[regno
].invariant
) != NULL_RTX
)
353 ira_reg_equiv
[regno
].invariant
354 = simplify_replace_fn_rtx (x
, NULL_RTX
, loc_equivalence_callback
,
358 /* If we have decided to substitute X with another value, return that
359 value, otherwise return X. */
366 if (! REG_P (x
) || (regno
= REGNO (x
)) < FIRST_PSEUDO_REGISTER
367 || ! ira_reg_equiv
[regno
].defined_p
368 || ! ira_reg_equiv
[regno
].profitable_p
369 || lra_get_regno_hard_regno (regno
) >= 0)
371 if ((res
= ira_reg_equiv
[regno
].memory
) != NULL_RTX
)
373 if ((res
= ira_reg_equiv
[regno
].constant
) != NULL_RTX
)
375 if ((res
= ira_reg_equiv
[regno
].invariant
) != NULL_RTX
)
380 /* If we have decided to substitute X with the equivalent value,
381 return that value after elimination for INSN, otherwise return
384 get_equiv_with_elimination (rtx x
, rtx insn
)
386 rtx res
= get_equiv (x
);
388 if (x
== res
|| CONSTANT_P (res
))
390 return lra_eliminate_regs_1 (insn
, res
, GET_MODE (res
), false, false, true);
393 /* Set up curr_operand_mode. */
395 init_curr_operand_mode (void)
397 int nop
= curr_static_id
->n_operands
;
398 for (int i
= 0; i
< nop
; i
++)
400 enum machine_mode mode
= GET_MODE (*curr_id
->operand_loc
[i
]);
401 if (mode
== VOIDmode
)
403 /* The .md mode for address operands is the mode of the
404 addressed value rather than the mode of the address itself. */
405 if (curr_id
->icode
>= 0 && curr_static_id
->operand
[i
].is_address
)
408 mode
= curr_static_id
->operand
[i
].mode
;
410 curr_operand_mode
[i
] = mode
;
416 /* The page contains code to reuse input reloads. */
418 /* Structure describes input reload of the current insns. */
421 /* Reloaded value. */
423 /* Reload pseudo used. */
427 /* The number of elements in the following array. */
428 static int curr_insn_input_reloads_num
;
429 /* Array containing info about input reloads. It is used to find the
430 same input reload and reuse the reload pseudo in this case. */
431 static struct input_reload curr_insn_input_reloads
[LRA_MAX_INSN_RELOADS
];
433 /* Initiate data concerning reuse of input reloads for the current
436 init_curr_insn_input_reloads (void)
438 curr_insn_input_reloads_num
= 0;
441 /* Create a new pseudo using MODE, RCLASS, ORIGINAL or reuse already
442 created input reload pseudo (only if TYPE is not OP_OUT). The
443 result pseudo is returned through RESULT_REG. Return TRUE if we
444 created a new pseudo, FALSE if we reused the already created input
445 reload pseudo. Use TITLE to describe new registers for debug
448 get_reload_reg (enum op_type type
, enum machine_mode mode
, rtx original
,
449 enum reg_class rclass
, const char *title
, rtx
*result_reg
)
452 enum reg_class new_class
;
457 = lra_create_new_reg_with_unique_value (mode
, original
, rclass
, title
);
460 /* Prevent reuse value of expression with side effects,
461 e.g. volatile memory. */
462 if (! side_effects_p (original
))
463 for (i
= 0; i
< curr_insn_input_reloads_num
; i
++)
464 if (rtx_equal_p (curr_insn_input_reloads
[i
].input
, original
)
465 && in_class_p (curr_insn_input_reloads
[i
].reg
, rclass
, &new_class
))
467 rtx reg
= curr_insn_input_reloads
[i
].reg
;
469 /* If input is equal to original and both are VOIDmode,
470 GET_MODE (reg) might be still different from mode.
471 Ensure we don't return *result_reg with wrong mode. */
472 if (GET_MODE (reg
) != mode
)
474 if (GET_MODE_SIZE (GET_MODE (reg
)) < GET_MODE_SIZE (mode
))
476 reg
= lowpart_subreg (mode
, reg
, GET_MODE (reg
));
477 if (reg
== NULL_RTX
|| GET_CODE (reg
) != SUBREG
)
481 if (lra_dump_file
!= NULL
)
483 fprintf (lra_dump_file
, " Reuse r%d for reload ", regno
);
484 dump_value_slim (lra_dump_file
, original
, 1);
486 if (new_class
!= lra_get_allocno_class (regno
))
487 lra_change_class (regno
, new_class
, ", change to", false);
488 if (lra_dump_file
!= NULL
)
489 fprintf (lra_dump_file
, "\n");
492 *result_reg
= lra_create_new_reg (mode
, original
, rclass
, title
);
493 lra_assert (curr_insn_input_reloads_num
< LRA_MAX_INSN_RELOADS
);
494 curr_insn_input_reloads
[curr_insn_input_reloads_num
].input
= original
;
495 curr_insn_input_reloads
[curr_insn_input_reloads_num
++].reg
= *result_reg
;
501 /* The page contains code to extract memory address parts. */
503 /* Wrapper around REGNO_OK_FOR_INDEX_P, to allow pseudos. */
505 ok_for_index_p_nonstrict (rtx reg
)
507 unsigned regno
= REGNO (reg
);
509 return regno
>= FIRST_PSEUDO_REGISTER
|| REGNO_OK_FOR_INDEX_P (regno
);
512 /* A version of regno_ok_for_base_p for use here, when all pseudos
513 should count as OK. Arguments as for regno_ok_for_base_p. */
515 ok_for_base_p_nonstrict (rtx reg
, enum machine_mode mode
, addr_space_t as
,
516 enum rtx_code outer_code
, enum rtx_code index_code
)
518 unsigned regno
= REGNO (reg
);
520 if (regno
>= FIRST_PSEUDO_REGISTER
)
522 return ok_for_base_p_1 (regno
, mode
, as
, outer_code
, index_code
);
527 /* The page contains major code to choose the current insn alternative
528 and generate reloads for it. */
530 /* Return the offset from REGNO of the least significant register
533 This function is used to tell whether two registers satisfy
534 a matching constraint. (reg:MODE1 REGNO1) matches (reg:MODE2 REGNO2) if:
536 REGNO1 + lra_constraint_offset (REGNO1, MODE1)
537 == REGNO2 + lra_constraint_offset (REGNO2, MODE2) */
539 lra_constraint_offset (int regno
, enum machine_mode mode
)
541 lra_assert (regno
< FIRST_PSEUDO_REGISTER
);
542 if (WORDS_BIG_ENDIAN
&& GET_MODE_SIZE (mode
) > UNITS_PER_WORD
543 && SCALAR_INT_MODE_P (mode
))
544 return hard_regno_nregs
[regno
][mode
] - 1;
548 /* Like rtx_equal_p except that it allows a REG and a SUBREG to match
549 if they are the same hard reg, and has special hacks for
550 auto-increment and auto-decrement. This is specifically intended for
551 process_alt_operands to use in determining whether two operands
552 match. X is the operand whose number is the lower of the two.
554 It is supposed that X is the output operand and Y is the input
555 operand. Y_HARD_REGNO is the final hard regno of register Y or
556 register in subreg Y as we know it now. Otherwise, it is a
559 operands_match_p (rtx x
, rtx y
, int y_hard_regno
)
562 RTX_CODE code
= GET_CODE (x
);
567 if ((code
== REG
|| (code
== SUBREG
&& REG_P (SUBREG_REG (x
))))
568 && (REG_P (y
) || (GET_CODE (y
) == SUBREG
&& REG_P (SUBREG_REG (y
)))))
572 i
= get_hard_regno (x
);
576 if ((j
= y_hard_regno
) < 0)
579 i
+= lra_constraint_offset (i
, GET_MODE (x
));
580 j
+= lra_constraint_offset (j
, GET_MODE (y
));
585 /* If two operands must match, because they are really a single
586 operand of an assembler insn, then two post-increments are invalid
587 because the assembler insn would increment only once. On the
588 other hand, a post-increment matches ordinary indexing if the
589 post-increment is the output operand. */
590 if (code
== POST_DEC
|| code
== POST_INC
|| code
== POST_MODIFY
)
591 return operands_match_p (XEXP (x
, 0), y
, y_hard_regno
);
593 /* Two pre-increments are invalid because the assembler insn would
594 increment only once. On the other hand, a pre-increment matches
595 ordinary indexing if the pre-increment is the input operand. */
596 if (GET_CODE (y
) == PRE_DEC
|| GET_CODE (y
) == PRE_INC
597 || GET_CODE (y
) == PRE_MODIFY
)
598 return operands_match_p (x
, XEXP (y
, 0), -1);
602 if (code
== REG
&& GET_CODE (y
) == SUBREG
&& REG_P (SUBREG_REG (y
))
603 && x
== SUBREG_REG (y
))
605 if (GET_CODE (y
) == REG
&& code
== SUBREG
&& REG_P (SUBREG_REG (x
))
606 && SUBREG_REG (x
) == y
)
609 /* Now we have disposed of all the cases in which different rtx
611 if (code
!= GET_CODE (y
))
614 /* (MULT:SI x y) and (MULT:HI x y) are NOT equivalent. */
615 if (GET_MODE (x
) != GET_MODE (y
))
624 return XEXP (x
, 0) == XEXP (y
, 0);
626 return XSTR (x
, 0) == XSTR (y
, 0);
632 /* Compare the elements. If any pair of corresponding elements fail
633 to match, return false for the whole things. */
635 fmt
= GET_RTX_FORMAT (code
);
636 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
642 if (XWINT (x
, i
) != XWINT (y
, i
))
647 if (XINT (x
, i
) != XINT (y
, i
))
652 val
= operands_match_p (XEXP (x
, i
), XEXP (y
, i
), -1);
661 if (XVECLEN (x
, i
) != XVECLEN (y
, i
))
663 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; --j
)
665 val
= operands_match_p (XVECEXP (x
, i
, j
), XVECEXP (y
, i
, j
), -1);
671 /* It is believed that rtx's at this level will never
672 contain anything but integers and other rtx's, except for
673 within LABEL_REFs and SYMBOL_REFs. */
681 /* True if X is a constant that can be forced into the constant pool.
682 MODE is the mode of the operand, or VOIDmode if not known. */
683 #define CONST_POOL_OK_P(MODE, X) \
684 ((MODE) != VOIDmode \
686 && GET_CODE (X) != HIGH \
687 && !targetm.cannot_force_const_mem (MODE, X))
689 /* True if C is a non-empty register class that has too few registers
690 to be safely used as a reload target class. */
691 #define SMALL_REGISTER_CLASS_P(C) \
692 (ira_class_hard_regs_num [(C)] == 1 \
693 || (ira_class_hard_regs_num [(C)] >= 1 \
694 && targetm.class_likely_spilled_p (C)))
696 /* If REG is a reload pseudo, try to make its class satisfying CL. */
698 narrow_reload_pseudo_class (rtx reg
, enum reg_class cl
)
700 enum reg_class rclass
;
702 /* Do not make more accurate class from reloads generated. They are
703 mostly moves with a lot of constraints. Making more accurate
704 class may results in very narrow class and impossibility of find
705 registers for several reloads of one insn. */
706 if (INSN_UID (curr_insn
) >= new_insn_uid_start
)
708 if (GET_CODE (reg
) == SUBREG
)
709 reg
= SUBREG_REG (reg
);
710 if (! REG_P (reg
) || (int) REGNO (reg
) < new_regno_start
)
712 if (in_class_p (reg
, cl
, &rclass
) && rclass
!= cl
)
713 lra_change_class (REGNO (reg
), rclass
, " Change to", true);
716 /* Generate reloads for matching OUT and INS (array of input operand
717 numbers with end marker -1) with reg class GOAL_CLASS. Add input
718 and output reloads correspondingly to the lists *BEFORE and *AFTER.
719 OUT might be negative. In this case we generate input reloads for
720 matched input operands INS. */
722 match_reload (signed char out
, signed char *ins
, enum reg_class goal_class
,
723 rtx
*before
, rtx
*after
)
726 rtx new_in_reg
, new_out_reg
, reg
, clobber
;
727 enum machine_mode inmode
, outmode
;
728 rtx in_rtx
= *curr_id
->operand_loc
[ins
[0]];
729 rtx out_rtx
= out
< 0 ? in_rtx
: *curr_id
->operand_loc
[out
];
731 inmode
= curr_operand_mode
[ins
[0]];
732 outmode
= out
< 0 ? inmode
: curr_operand_mode
[out
];
733 push_to_sequence (*before
);
734 if (inmode
!= outmode
)
736 if (GET_MODE_SIZE (inmode
) > GET_MODE_SIZE (outmode
))
739 = lra_create_new_reg_with_unique_value (inmode
, in_rtx
,
741 if (SCALAR_INT_MODE_P (inmode
))
742 new_out_reg
= gen_lowpart_SUBREG (outmode
, reg
);
744 new_out_reg
= gen_rtx_SUBREG (outmode
, reg
, 0);
745 LRA_SUBREG_P (new_out_reg
) = 1;
746 /* If the input reg is dying here, we can use the same hard
747 register for REG and IN_RTX. We do it only for original
748 pseudos as reload pseudos can die although original
749 pseudos still live where reload pseudos dies. */
750 if (REG_P (in_rtx
) && (int) REGNO (in_rtx
) < lra_new_regno_start
751 && find_regno_note (curr_insn
, REG_DEAD
, REGNO (in_rtx
)))
752 lra_assign_reg_val (REGNO (in_rtx
), REGNO (reg
));
757 = lra_create_new_reg_with_unique_value (outmode
, out_rtx
,
759 if (SCALAR_INT_MODE_P (outmode
))
760 new_in_reg
= gen_lowpart_SUBREG (inmode
, reg
);
762 new_in_reg
= gen_rtx_SUBREG (inmode
, reg
, 0);
763 /* NEW_IN_REG is non-paradoxical subreg. We don't want
764 NEW_OUT_REG living above. We add clobber clause for
765 this. This is just a temporary clobber. We can remove
766 it at the end of LRA work. */
767 clobber
= emit_clobber (new_out_reg
);
768 LRA_TEMP_CLOBBER_P (PATTERN (clobber
)) = 1;
769 LRA_SUBREG_P (new_in_reg
) = 1;
770 if (GET_CODE (in_rtx
) == SUBREG
)
772 rtx subreg_reg
= SUBREG_REG (in_rtx
);
774 /* If SUBREG_REG is dying here and sub-registers IN_RTX
775 and NEW_IN_REG are similar, we can use the same hard
776 register for REG and SUBREG_REG. */
777 if (REG_P (subreg_reg
)
778 && (int) REGNO (subreg_reg
) < lra_new_regno_start
779 && GET_MODE (subreg_reg
) == outmode
780 && SUBREG_BYTE (in_rtx
) == SUBREG_BYTE (new_in_reg
)
781 && find_regno_note (curr_insn
, REG_DEAD
, REGNO (subreg_reg
)))
782 lra_assign_reg_val (REGNO (subreg_reg
), REGNO (reg
));
788 /* Pseudos have values -- see comments for lra_reg_info.
789 Different pseudos with the same value do not conflict even if
790 they live in the same place. When we create a pseudo we
791 assign value of original pseudo (if any) from which we
792 created the new pseudo. If we create the pseudo from the
793 input pseudo, the new pseudo will no conflict with the input
794 pseudo which is wrong when the input pseudo lives after the
795 insn and as the new pseudo value is changed by the insn
796 output. Therefore we create the new pseudo from the output.
798 We cannot reuse the current output register because we might
799 have a situation like "a <- a op b", where the constraints
800 force the second input operand ("b") to match the output
801 operand ("a"). "b" must then be copied into a new register
802 so that it doesn't clobber the current value of "a". */
804 new_in_reg
= new_out_reg
805 = lra_create_new_reg_with_unique_value (outmode
, out_rtx
,
808 /* In operand can be got from transformations before processing insn
809 constraints. One example of such transformations is subreg
810 reloading (see function simplify_operand_subreg). The new
811 pseudos created by the transformations might have inaccurate
812 class (ALL_REGS) and we should make their classes more
814 narrow_reload_pseudo_class (in_rtx
, goal_class
);
815 lra_emit_move (copy_rtx (new_in_reg
), in_rtx
);
816 *before
= get_insns ();
818 for (i
= 0; (in
= ins
[i
]) >= 0; i
++)
821 (GET_MODE (*curr_id
->operand_loc
[in
]) == VOIDmode
822 || GET_MODE (new_in_reg
) == GET_MODE (*curr_id
->operand_loc
[in
]));
823 *curr_id
->operand_loc
[in
] = new_in_reg
;
825 lra_update_dups (curr_id
, ins
);
828 /* See a comment for the input operand above. */
829 narrow_reload_pseudo_class (out_rtx
, goal_class
);
830 if (find_reg_note (curr_insn
, REG_UNUSED
, out_rtx
) == NULL_RTX
)
833 lra_emit_move (out_rtx
, copy_rtx (new_out_reg
));
835 *after
= get_insns ();
838 *curr_id
->operand_loc
[out
] = new_out_reg
;
839 lra_update_dup (curr_id
, out
);
842 /* Return register class which is union of all reg classes in insn
843 constraint alternative string starting with P. */
844 static enum reg_class
845 reg_class_from_constraints (const char *p
)
848 enum reg_class op_class
= NO_REGS
;
851 switch ((c
= *p
, len
= CONSTRAINT_LEN (c
, p
)), c
)
858 op_class
= (reg_class_subunion
859 [op_class
][base_reg_class (VOIDmode
, ADDR_SPACE_GENERIC
,
865 op_class
= reg_class_subunion
[op_class
][GENERAL_REGS
];
869 if (REG_CLASS_FROM_CONSTRAINT (c
, p
) == NO_REGS
)
871 #ifdef EXTRA_CONSTRAINT_STR
872 if (EXTRA_ADDRESS_CONSTRAINT (c
, p
))
874 = (reg_class_subunion
875 [op_class
][base_reg_class (VOIDmode
, ADDR_SPACE_GENERIC
,
882 = reg_class_subunion
[op_class
][REG_CLASS_FROM_CONSTRAINT (c
, p
)];
885 while ((p
+= len
), c
);
889 /* If OP is a register, return the class of the register as per
890 get_reg_class, otherwise return NO_REGS. */
891 static inline enum reg_class
892 get_op_class (rtx op
)
894 return REG_P (op
) ? get_reg_class (REGNO (op
)) : NO_REGS
;
897 /* Return generated insn mem_pseudo:=val if TO_P or val:=mem_pseudo
898 otherwise. If modes of MEM_PSEUDO and VAL are different, use
899 SUBREG for VAL to make them equal. */
901 emit_spill_move (bool to_p
, rtx mem_pseudo
, rtx val
)
903 if (GET_MODE (mem_pseudo
) != GET_MODE (val
))
905 /* Usually size of mem_pseudo is greater than val size but in
906 rare cases it can be less as it can be defined by target
907 dependent macro HARD_REGNO_CALLER_SAVE_MODE. */
910 val
= gen_rtx_SUBREG (GET_MODE (mem_pseudo
),
911 GET_CODE (val
) == SUBREG
? SUBREG_REG (val
) : val
,
913 LRA_SUBREG_P (val
) = 1;
917 mem_pseudo
= gen_lowpart_SUBREG (GET_MODE (val
), mem_pseudo
);
918 LRA_SUBREG_P (mem_pseudo
) = 1;
922 ? gen_move_insn (mem_pseudo
, val
)
923 : gen_move_insn (val
, mem_pseudo
));
926 /* Process a special case insn (register move), return true if we
927 don't need to process it anymore. INSN should be a single set
928 insn. Set up that RTL was changed through CHANGE_P and macro
929 SECONDARY_MEMORY_NEEDED says to use secondary memory through
932 check_and_process_move (bool *change_p
, bool *sec_mem_p ATTRIBUTE_UNUSED
)
935 rtx dest
, src
, dreg
, sreg
, old_sreg
, new_reg
, before
, scratch_reg
;
936 enum reg_class dclass
, sclass
, secondary_class
;
937 enum machine_mode sreg_mode
;
938 secondary_reload_info sri
;
940 lra_assert (curr_insn_set
!= NULL_RTX
);
941 dreg
= dest
= SET_DEST (curr_insn_set
);
942 sreg
= src
= SET_SRC (curr_insn_set
);
943 if (GET_CODE (dest
) == SUBREG
)
944 dreg
= SUBREG_REG (dest
);
945 if (GET_CODE (src
) == SUBREG
)
946 sreg
= SUBREG_REG (src
);
947 if (! (REG_P (dreg
) || MEM_P (dreg
)) || ! (REG_P (sreg
) || MEM_P (sreg
)))
949 sclass
= dclass
= NO_REGS
;
951 dclass
= get_reg_class (REGNO (dreg
));
952 if (dclass
== ALL_REGS
)
953 /* ALL_REGS is used for new pseudos created by transformations
954 like reload of SUBREG_REG (see function
955 simplify_operand_subreg). We don't know their class yet. We
956 should figure out the class from processing the insn
957 constraints not in this fast path function. Even if ALL_REGS
958 were a right class for the pseudo, secondary_... hooks usually
959 are not define for ALL_REGS. */
961 sreg_mode
= GET_MODE (sreg
);
964 sclass
= get_reg_class (REGNO (sreg
));
965 if (sclass
== ALL_REGS
)
966 /* See comments above. */
968 if (sclass
== NO_REGS
&& dclass
== NO_REGS
)
970 #ifdef SECONDARY_MEMORY_NEEDED
971 if (SECONDARY_MEMORY_NEEDED (sclass
, dclass
, GET_MODE (src
))
972 #ifdef SECONDARY_MEMORY_NEEDED_MODE
973 && ((sclass
!= NO_REGS
&& dclass
!= NO_REGS
)
974 || GET_MODE (src
) != SECONDARY_MEMORY_NEEDED_MODE (GET_MODE (src
)))
982 if (! REG_P (dreg
) || ! REG_P (sreg
))
985 sri
.icode
= CODE_FOR_nothing
;
987 secondary_class
= NO_REGS
;
988 /* Set up hard register for a reload pseudo for hook
989 secondary_reload because some targets just ignore unassigned
990 pseudos in the hook. */
991 if (dclass
!= NO_REGS
&& lra_get_regno_hard_regno (REGNO (dreg
)) < 0)
993 dregno
= REGNO (dreg
);
994 reg_renumber
[dregno
] = ira_class_hard_regs
[dclass
][0];
998 if (sclass
!= NO_REGS
&& lra_get_regno_hard_regno (REGNO (sreg
)) < 0)
1000 sregno
= REGNO (sreg
);
1001 reg_renumber
[sregno
] = ira_class_hard_regs
[sclass
][0];
1005 if (sclass
!= NO_REGS
)
1007 = (enum reg_class
) targetm
.secondary_reload (false, dest
,
1008 (reg_class_t
) sclass
,
1009 GET_MODE (src
), &sri
);
1010 if (sclass
== NO_REGS
1011 || ((secondary_class
!= NO_REGS
|| sri
.icode
!= CODE_FOR_nothing
)
1012 && dclass
!= NO_REGS
))
1014 enum reg_class old_sclass
= secondary_class
;
1015 secondary_reload_info old_sri
= sri
;
1017 sri
.prev_sri
= NULL
;
1018 sri
.icode
= CODE_FOR_nothing
;
1021 = (enum reg_class
) targetm
.secondary_reload (true, sreg
,
1022 (reg_class_t
) dclass
,
1024 /* Check the target hook consistency. */
1026 ((secondary_class
== NO_REGS
&& sri
.icode
== CODE_FOR_nothing
)
1027 || (old_sclass
== NO_REGS
&& old_sri
.icode
== CODE_FOR_nothing
)
1028 || (secondary_class
== old_sclass
&& sri
.icode
== old_sri
.icode
));
1031 reg_renumber
[sregno
] = -1;
1033 reg_renumber
[dregno
] = -1;
1034 if (secondary_class
== NO_REGS
&& sri
.icode
== CODE_FOR_nothing
)
1038 if (secondary_class
!= NO_REGS
)
1039 new_reg
= lra_create_new_reg_with_unique_value (sreg_mode
, NULL_RTX
,
1043 if (old_sreg
!= sreg
)
1044 sreg
= copy_rtx (sreg
);
1045 if (sri
.icode
== CODE_FOR_nothing
)
1046 lra_emit_move (new_reg
, sreg
);
1049 enum reg_class scratch_class
;
1051 scratch_class
= (reg_class_from_constraints
1052 (insn_data
[sri
.icode
].operand
[2].constraint
));
1053 scratch_reg
= (lra_create_new_reg_with_unique_value
1054 (insn_data
[sri
.icode
].operand
[2].mode
, NULL_RTX
,
1055 scratch_class
, "scratch"));
1056 emit_insn (GEN_FCN (sri
.icode
) (new_reg
!= NULL_RTX
? new_reg
: dest
,
1057 sreg
, scratch_reg
));
1059 before
= get_insns ();
1061 lra_process_new_insns (curr_insn
, before
, NULL_RTX
, "Inserting the move");
1062 if (new_reg
!= NULL_RTX
)
1064 if (GET_CODE (src
) == SUBREG
)
1065 SUBREG_REG (src
) = new_reg
;
1067 SET_SRC (curr_insn_set
) = new_reg
;
1071 if (lra_dump_file
!= NULL
)
1073 fprintf (lra_dump_file
, "Deleting move %u\n", INSN_UID (curr_insn
));
1074 dump_insn_slim (lra_dump_file
, curr_insn
);
1076 lra_set_insn_deleted (curr_insn
);
1082 /* The following data describe the result of process_alt_operands.
1083 The data are used in curr_insn_transform to generate reloads. */
1085 /* The chosen reg classes which should be used for the corresponding
1087 static enum reg_class goal_alt
[MAX_RECOG_OPERANDS
];
1088 /* True if the operand should be the same as another operand and that
1089 other operand does not need a reload. */
1090 static bool goal_alt_match_win
[MAX_RECOG_OPERANDS
];
1091 /* True if the operand does not need a reload. */
1092 static bool goal_alt_win
[MAX_RECOG_OPERANDS
];
1093 /* True if the operand can be offsetable memory. */
1094 static bool goal_alt_offmemok
[MAX_RECOG_OPERANDS
];
1095 /* The number of an operand to which given operand can be matched to. */
1096 static int goal_alt_matches
[MAX_RECOG_OPERANDS
];
1097 /* The number of elements in the following array. */
1098 static int goal_alt_dont_inherit_ops_num
;
1099 /* Numbers of operands whose reload pseudos should not be inherited. */
1100 static int goal_alt_dont_inherit_ops
[MAX_RECOG_OPERANDS
];
1101 /* True if the insn commutative operands should be swapped. */
1102 static bool goal_alt_swapped
;
1103 /* The chosen insn alternative. */
1104 static int goal_alt_number
;
1106 /* The following five variables are used to choose the best insn
1107 alternative. They reflect final characteristics of the best
1110 /* Number of necessary reloads and overall cost reflecting the
1111 previous value and other unpleasantness of the best alternative. */
1112 static int best_losers
, best_overall
;
1113 /* Overall number hard registers used for reloads. For example, on
1114 some targets we need 2 general registers to reload DFmode and only
1115 one floating point register. */
1116 static int best_reload_nregs
;
1117 /* Overall number reflecting distances of previous reloading the same
1118 value. The distances are counted from the current BB start. It is
1119 used to improve inheritance chances. */
1120 static int best_reload_sum
;
1122 /* True if the current insn should have no correspondingly input or
1124 static bool no_input_reloads_p
, no_output_reloads_p
;
1126 /* True if we swapped the commutative operands in the current
1128 static int curr_swapped
;
1130 /* Arrange for address element *LOC to be a register of class CL.
1131 Add any input reloads to list BEFORE. AFTER is nonnull if *LOC is an
1132 automodified value; handle that case by adding the required output
1133 reloads to list AFTER. Return true if the RTL was changed. */
1135 process_addr_reg (rtx
*loc
, rtx
*before
, rtx
*after
, enum reg_class cl
)
1138 enum reg_class rclass
, new_class
;
1141 enum machine_mode mode
;
1142 bool before_p
= false;
1144 loc
= strip_subreg (loc
);
1146 mode
= GET_MODE (reg
);
1149 /* Always reload memory in an address even if the target supports
1151 new_reg
= lra_create_new_reg_with_unique_value (mode
, reg
, cl
, "address");
1156 regno
= REGNO (reg
);
1157 rclass
= get_reg_class (regno
);
1158 if ((*loc
= get_equiv_with_elimination (reg
, curr_insn
)) != reg
)
1160 if (lra_dump_file
!= NULL
)
1162 fprintf (lra_dump_file
,
1163 "Changing pseudo %d in address of insn %u on equiv ",
1164 REGNO (reg
), INSN_UID (curr_insn
));
1165 dump_value_slim (lra_dump_file
, *loc
, 1);
1166 fprintf (lra_dump_file
, "\n");
1168 *loc
= copy_rtx (*loc
);
1170 if (*loc
!= reg
|| ! in_class_p (reg
, cl
, &new_class
))
1173 if (get_reload_reg (after
== NULL
? OP_IN
: OP_INOUT
,
1174 mode
, reg
, cl
, "address", &new_reg
))
1177 else if (new_class
!= NO_REGS
&& rclass
!= new_class
)
1179 lra_change_class (regno
, new_class
, " Change to", true);
1187 push_to_sequence (*before
);
1188 lra_emit_move (new_reg
, reg
);
1189 *before
= get_insns ();
1196 lra_emit_move (reg
, new_reg
);
1198 *after
= get_insns ();
1204 /* Insert move insn in simplify_operand_subreg. BEFORE returns
1205 the insn to be inserted before curr insn. AFTER returns the
1206 the insn to be inserted after curr insn. ORIGREG and NEWREG
1207 are the original reg and new reg for reload. */
1209 insert_move_for_subreg (rtx
*before
, rtx
*after
, rtx origreg
, rtx newreg
)
1213 push_to_sequence (*before
);
1214 lra_emit_move (newreg
, origreg
);
1215 *before
= get_insns ();
1221 lra_emit_move (origreg
, newreg
);
1223 *after
= get_insns ();
1228 /* Make reloads for subreg in operand NOP with internal subreg mode
1229 REG_MODE, add new reloads for further processing. Return true if
1230 any reload was generated. */
1232 simplify_operand_subreg (int nop
, enum machine_mode reg_mode
)
1236 enum machine_mode mode
;
1238 rtx operand
= *curr_id
->operand_loc
[nop
];
1239 enum reg_class regclass
;
1242 before
= after
= NULL_RTX
;
1244 if (GET_CODE (operand
) != SUBREG
)
1247 mode
= GET_MODE (operand
);
1248 reg
= SUBREG_REG (operand
);
1249 type
= curr_static_id
->operand
[nop
].type
;
1250 /* If we change address for paradoxical subreg of memory, the
1251 address might violate the necessary alignment or the access might
1252 be slow. So take this into consideration. We should not worry
1253 about access beyond allocated memory for paradoxical memory
1254 subregs as we don't substitute such equiv memory (see processing
1255 equivalences in function lra_constraints) and because for spilled
1256 pseudos we allocate stack memory enough for the biggest
1257 corresponding paradoxical subreg. */
1259 && (! SLOW_UNALIGNED_ACCESS (mode
, MEM_ALIGN (reg
))
1260 || MEM_ALIGN (reg
) >= GET_MODE_ALIGNMENT (mode
)))
1261 || (REG_P (reg
) && REGNO (reg
) < FIRST_PSEUDO_REGISTER
))
1263 alter_subreg (curr_id
->operand_loc
[nop
], false);
1266 /* Put constant into memory when we have mixed modes. It generates
1267 a better code in most cases as it does not need a secondary
1268 reload memory. It also prevents LRA looping when LRA is using
1269 secondary reload memory again and again. */
1270 if (CONSTANT_P (reg
) && CONST_POOL_OK_P (reg_mode
, reg
)
1271 && SCALAR_INT_MODE_P (reg_mode
) != SCALAR_INT_MODE_P (mode
))
1273 SUBREG_REG (operand
) = force_const_mem (reg_mode
, reg
);
1274 alter_subreg (curr_id
->operand_loc
[nop
], false);
1277 /* Force a reload of the SUBREG_REG if this is a constant or PLUS or
1278 if there may be a problem accessing OPERAND in the outer
1281 && REGNO (reg
) >= FIRST_PSEUDO_REGISTER
1282 && (hard_regno
= lra_get_regno_hard_regno (REGNO (reg
))) >= 0
1283 /* Don't reload paradoxical subregs because we could be looping
1284 having repeatedly final regno out of hard regs range. */
1285 && (hard_regno_nregs
[hard_regno
][GET_MODE (reg
)]
1286 >= hard_regno_nregs
[hard_regno
][mode
])
1287 && simplify_subreg_regno (hard_regno
, GET_MODE (reg
),
1288 SUBREG_BYTE (operand
), mode
) < 0
1289 /* Don't reload subreg for matching reload. It is actually
1290 valid subreg in LRA. */
1291 && ! LRA_SUBREG_P (operand
))
1292 || CONSTANT_P (reg
) || GET_CODE (reg
) == PLUS
|| MEM_P (reg
))
1294 /* The class will be defined later in curr_insn_transform. */
1295 enum reg_class rclass
1296 = (enum reg_class
) targetm
.preferred_reload_class (reg
, ALL_REGS
);
1298 if (get_reload_reg (curr_static_id
->operand
[nop
].type
, reg_mode
, reg
,
1299 rclass
, "subreg reg", &new_reg
))
1301 bool insert_before
, insert_after
;
1302 bitmap_set_bit (&lra_subreg_reload_pseudos
, REGNO (new_reg
));
1304 insert_before
= (type
!= OP_OUT
1305 || GET_MODE_SIZE (GET_MODE (reg
)) > GET_MODE_SIZE (mode
));
1306 insert_after
= (type
!= OP_IN
);
1307 insert_move_for_subreg (insert_before
? &before
: NULL
,
1308 insert_after
? &after
: NULL
,
1311 SUBREG_REG (operand
) = new_reg
;
1312 lra_process_new_insns (curr_insn
, before
, after
,
1313 "Inserting subreg reload");
1316 /* Force a reload for a paradoxical subreg. For paradoxical subreg,
1317 IRA allocates hardreg to the inner pseudo reg according to its mode
1318 instead of the outermode, so the size of the hardreg may not be enough
1319 to contain the outermode operand, in that case we may need to insert
1320 reload for the reg. For the following two types of paradoxical subreg,
1321 we need to insert reload:
1322 1. If the op_type is OP_IN, and the hardreg could not be paired with
1323 other hardreg to contain the outermode operand
1324 (checked by in_hard_reg_set_p), we need to insert the reload.
1325 2. If the op_type is OP_OUT or OP_INOUT.
1327 Here is a paradoxical subreg example showing how the reload is generated:
1329 (insn 5 4 7 2 (set (reg:TI 106 [ __comp ])
1330 (subreg:TI (reg:DI 107 [ __comp ]) 0)) {*movti_internal_rex64}
1332 In IRA, reg107 is allocated to a DImode hardreg. We use x86-64 as example
1333 here, if reg107 is assigned to hardreg R15, because R15 is the last
1334 hardreg, compiler cannot find another hardreg to pair with R15 to
1335 contain TImode data. So we insert a TImode reload reg180 for it.
1336 After reload is inserted:
1338 (insn 283 0 0 (set (subreg:DI (reg:TI 180 [orig:107 __comp ] [107]) 0)
1339 (reg:DI 107 [ __comp ])) -1
1340 (insn 5 4 7 2 (set (reg:TI 106 [ __comp ])
1341 (subreg:TI (reg:TI 180 [orig:107 __comp ] [107]) 0)) {*movti_internal_rex64}
1343 Two reload hard registers will be allocated to reg180 to save TImode data
1345 else if (REG_P (reg
)
1346 && REGNO (reg
) >= FIRST_PSEUDO_REGISTER
1347 && (hard_regno
= lra_get_regno_hard_regno (REGNO (reg
))) >= 0
1348 && (hard_regno_nregs
[hard_regno
][GET_MODE (reg
)]
1349 < hard_regno_nregs
[hard_regno
][mode
])
1350 && (regclass
= lra_get_allocno_class (REGNO (reg
)))
1352 || !in_hard_reg_set_p (reg_class_contents
[regclass
],
1355 /* The class will be defined later in curr_insn_transform. */
1356 enum reg_class rclass
1357 = (enum reg_class
) targetm
.preferred_reload_class (reg
, ALL_REGS
);
1359 if (get_reload_reg (curr_static_id
->operand
[nop
].type
, mode
, reg
,
1360 rclass
, "paradoxical subreg", &new_reg
))
1363 bool insert_before
, insert_after
;
1365 PUT_MODE (new_reg
, mode
);
1366 subreg
= simplify_gen_subreg (GET_MODE (reg
), new_reg
, mode
, 0);
1367 bitmap_set_bit (&lra_subreg_reload_pseudos
, REGNO (new_reg
));
1369 insert_before
= (type
!= OP_OUT
);
1370 insert_after
= (type
!= OP_IN
);
1371 insert_move_for_subreg (insert_before
? &before
: NULL
,
1372 insert_after
? &after
: NULL
,
1375 SUBREG_REG (operand
) = new_reg
;
1376 lra_process_new_insns (curr_insn
, before
, after
,
1377 "Inserting paradoxical subreg reload");
1383 /* Return TRUE if X refers for a hard register from SET. */
1385 uses_hard_regs_p (rtx x
, HARD_REG_SET set
)
1387 int i
, j
, x_hard_regno
;
1388 enum machine_mode mode
;
1394 code
= GET_CODE (x
);
1395 mode
= GET_MODE (x
);
1399 code
= GET_CODE (x
);
1400 if (GET_MODE_SIZE (GET_MODE (x
)) > GET_MODE_SIZE (mode
))
1401 mode
= GET_MODE (x
);
1406 x_hard_regno
= get_hard_regno (x
);
1407 return (x_hard_regno
>= 0
1408 && overlaps_hard_reg_set_p (set
, mode
, x_hard_regno
));
1412 struct address_info ad
;
1414 decompose_mem_address (&ad
, x
);
1415 if (ad
.base_term
!= NULL
&& uses_hard_regs_p (*ad
.base_term
, set
))
1417 if (ad
.index_term
!= NULL
&& uses_hard_regs_p (*ad
.index_term
, set
))
1420 fmt
= GET_RTX_FORMAT (code
);
1421 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
1425 if (uses_hard_regs_p (XEXP (x
, i
), set
))
1428 else if (fmt
[i
] == 'E')
1430 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
1431 if (uses_hard_regs_p (XVECEXP (x
, i
, j
), set
))
1438 /* Return true if OP is a spilled pseudo. */
1440 spilled_pseudo_p (rtx op
)
1443 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
&& in_mem_p (REGNO (op
)));
1446 /* Return true if X is a general constant. */
1448 general_constant_p (rtx x
)
1450 return CONSTANT_P (x
) && (! flag_pic
|| LEGITIMATE_PIC_OPERAND_P (x
));
1454 reg_in_class_p (rtx reg
, enum reg_class cl
)
1457 return get_reg_class (REGNO (reg
)) == NO_REGS
;
1458 return in_class_p (reg
, cl
, NULL
);
1461 /* Major function to choose the current insn alternative and what
1462 operands should be reloaded and how. If ONLY_ALTERNATIVE is not
1463 negative we should consider only this alternative. Return false if
1464 we can not choose the alternative or find how to reload the
1467 process_alt_operands (int only_alternative
)
1470 int nop
, overall
, nalt
;
1471 int n_alternatives
= curr_static_id
->n_alternatives
;
1472 int n_operands
= curr_static_id
->n_operands
;
1473 /* LOSERS counts the operands that don't fit this alternative and
1474 would require loading. */
1476 /* REJECT is a count of how undesirable this alternative says it is
1477 if any reloading is required. If the alternative matches exactly
1478 then REJECT is ignored, but otherwise it gets this much counted
1479 against it in addition to the reloading needed. */
1481 /* The number of elements in the following array. */
1482 int early_clobbered_regs_num
;
1483 /* Numbers of operands which are early clobber registers. */
1484 int early_clobbered_nops
[MAX_RECOG_OPERANDS
];
1485 enum reg_class curr_alt
[MAX_RECOG_OPERANDS
];
1486 HARD_REG_SET curr_alt_set
[MAX_RECOG_OPERANDS
];
1487 bool curr_alt_match_win
[MAX_RECOG_OPERANDS
];
1488 bool curr_alt_win
[MAX_RECOG_OPERANDS
];
1489 bool curr_alt_offmemok
[MAX_RECOG_OPERANDS
];
1490 int curr_alt_matches
[MAX_RECOG_OPERANDS
];
1491 /* The number of elements in the following array. */
1492 int curr_alt_dont_inherit_ops_num
;
1493 /* Numbers of operands whose reload pseudos should not be inherited. */
1494 int curr_alt_dont_inherit_ops
[MAX_RECOG_OPERANDS
];
1496 /* The register when the operand is a subreg of register, otherwise the
1498 rtx no_subreg_reg_operand
[MAX_RECOG_OPERANDS
];
1499 /* The register if the operand is a register or subreg of register,
1501 rtx operand_reg
[MAX_RECOG_OPERANDS
];
1502 int hard_regno
[MAX_RECOG_OPERANDS
];
1503 enum machine_mode biggest_mode
[MAX_RECOG_OPERANDS
];
1504 int reload_nregs
, reload_sum
;
1508 /* Calculate some data common for all alternatives to speed up the
1510 for (nop
= 0; nop
< n_operands
; nop
++)
1514 op
= no_subreg_reg_operand
[nop
] = *curr_id
->operand_loc
[nop
];
1515 /* The real hard regno of the operand after the allocation. */
1516 hard_regno
[nop
] = get_hard_regno (op
);
1518 operand_reg
[nop
] = reg
= op
;
1519 biggest_mode
[nop
] = GET_MODE (op
);
1520 if (GET_CODE (op
) == SUBREG
)
1522 operand_reg
[nop
] = reg
= SUBREG_REG (op
);
1523 if (GET_MODE_SIZE (biggest_mode
[nop
])
1524 < GET_MODE_SIZE (GET_MODE (reg
)))
1525 biggest_mode
[nop
] = GET_MODE (reg
);
1528 operand_reg
[nop
] = NULL_RTX
;
1529 else if (REGNO (reg
) >= FIRST_PSEUDO_REGISTER
1530 || ((int) REGNO (reg
)
1531 == lra_get_elimination_hard_regno (REGNO (reg
))))
1532 no_subreg_reg_operand
[nop
] = reg
;
1534 operand_reg
[nop
] = no_subreg_reg_operand
[nop
]
1535 /* Just use natural mode for elimination result. It should
1536 be enough for extra constraints hooks. */
1537 = regno_reg_rtx
[hard_regno
[nop
]];
1540 /* The constraints are made of several alternatives. Each operand's
1541 constraint looks like foo,bar,... with commas separating the
1542 alternatives. The first alternatives for all operands go
1543 together, the second alternatives go together, etc.
1545 First loop over alternatives. */
1546 for (nalt
= 0; nalt
< n_alternatives
; nalt
++)
1548 /* Loop over operands for one constraint alternative. */
1549 #if HAVE_ATTR_enabled
1550 if (curr_id
->alternative_enabled_p
!= NULL
1551 && ! curr_id
->alternative_enabled_p
[nalt
])
1555 if (only_alternative
>= 0 && nalt
!= only_alternative
)
1559 overall
= losers
= reject
= reload_nregs
= reload_sum
= 0;
1560 for (nop
= 0; nop
< n_operands
; nop
++)
1562 int inc
= (curr_static_id
1563 ->operand_alternative
[nalt
* n_operands
+ nop
].reject
);
1564 if (lra_dump_file
!= NULL
&& inc
!= 0)
1565 fprintf (lra_dump_file
,
1566 " Staticly defined alt reject+=%d\n", inc
);
1569 early_clobbered_regs_num
= 0;
1571 for (nop
= 0; nop
< n_operands
; nop
++)
1575 int len
, c
, m
, i
, opalt_num
, this_alternative_matches
;
1576 bool win
, did_match
, offmemok
, early_clobber_p
;
1577 /* false => this operand can be reloaded somehow for this
1580 /* true => this operand can be reloaded if the alternative
1583 /* True if a constant forced into memory would be OK for
1586 enum reg_class this_alternative
, this_costly_alternative
;
1587 HARD_REG_SET this_alternative_set
, this_costly_alternative_set
;
1588 bool this_alternative_match_win
, this_alternative_win
;
1589 bool this_alternative_offmemok
;
1591 enum machine_mode mode
;
1593 opalt_num
= nalt
* n_operands
+ nop
;
1594 if (curr_static_id
->operand_alternative
[opalt_num
].anything_ok
)
1596 /* Fast track for no constraints at all. */
1597 curr_alt
[nop
] = NO_REGS
;
1598 CLEAR_HARD_REG_SET (curr_alt_set
[nop
]);
1599 curr_alt_win
[nop
] = true;
1600 curr_alt_match_win
[nop
] = false;
1601 curr_alt_offmemok
[nop
] = false;
1602 curr_alt_matches
[nop
] = -1;
1606 op
= no_subreg_reg_operand
[nop
];
1607 mode
= curr_operand_mode
[nop
];
1609 win
= did_match
= winreg
= offmemok
= constmemok
= false;
1612 early_clobber_p
= false;
1613 p
= curr_static_id
->operand_alternative
[opalt_num
].constraint
;
1615 this_costly_alternative
= this_alternative
= NO_REGS
;
1616 /* We update set of possible hard regs besides its class
1617 because reg class might be inaccurate. For example,
1618 union of LO_REGS (l), HI_REGS(h), and STACK_REG(k) in ARM
1619 is translated in HI_REGS because classes are merged by
1620 pairs and there is no accurate intermediate class. */
1621 CLEAR_HARD_REG_SET (this_alternative_set
);
1622 CLEAR_HARD_REG_SET (this_costly_alternative_set
);
1623 this_alternative_win
= false;
1624 this_alternative_match_win
= false;
1625 this_alternative_offmemok
= false;
1626 this_alternative_matches
= -1;
1628 /* An empty constraint should be excluded by the fast
1630 lra_assert (*p
!= 0 && *p
!= ',');
1632 /* Scan this alternative's specs for this operand; set WIN
1633 if the operand fits any letter in this alternative.
1634 Otherwise, clear BADOP if this operand could fit some
1635 letter after reloads, or set WINREG if this operand could
1636 fit after reloads provided the constraint allows some
1641 switch ((c
= *p
, len
= CONSTRAINT_LEN (c
, p
)), c
)
1650 case '=': case '+': case '?': case '*': case '!':
1651 case ' ': case '\t':
1655 /* We only support one commutative marker, the first
1656 one. We already set commutative above. */
1660 early_clobber_p
= true;
1664 /* Ignore rest of this alternative. */
1668 case '0': case '1': case '2': case '3': case '4':
1669 case '5': case '6': case '7': case '8': case '9':
1674 m
= strtoul (p
, &end
, 10);
1677 lra_assert (nop
> m
);
1679 this_alternative_matches
= m
;
1680 m_hregno
= get_hard_regno (*curr_id
->operand_loc
[m
]);
1681 /* We are supposed to match a previous operand.
1682 If we do, we win if that one did. If we do
1683 not, count both of the operands as losers.
1684 (This is too conservative, since most of the
1685 time only a single reload insn will be needed
1686 to make the two operands win. As a result,
1687 this alternative may be rejected when it is
1688 actually desirable.) */
1690 if (operands_match_p (*curr_id
->operand_loc
[nop
],
1691 *curr_id
->operand_loc
[m
], m_hregno
))
1693 /* We should reject matching of an early
1694 clobber operand if the matching operand is
1695 not dying in the insn. */
1696 if (! curr_static_id
->operand
[m
].early_clobber
1697 || operand_reg
[nop
] == NULL_RTX
1698 || (find_regno_note (curr_insn
, REG_DEAD
,
1700 || REGNO (op
) == REGNO (operand_reg
[m
])))
1705 /* If we are matching a non-offsettable
1706 address where an offsettable address was
1707 expected, then we must reject this
1708 combination, because we can't reload
1710 if (curr_alt_offmemok
[m
]
1711 && MEM_P (*curr_id
->operand_loc
[m
])
1712 && curr_alt
[m
] == NO_REGS
&& ! curr_alt_win
[m
])
1717 /* Operands don't match. Both operands must
1718 allow a reload register, otherwise we
1719 cannot make them match. */
1720 if (curr_alt
[m
] == NO_REGS
)
1722 /* Retroactively mark the operand we had to
1723 match as a loser, if it wasn't already and
1724 it wasn't matched to a register constraint
1725 (e.g it might be matched by memory). */
1727 && (operand_reg
[m
] == NULL_RTX
1728 || hard_regno
[m
] < 0))
1732 += (ira_reg_class_max_nregs
[curr_alt
[m
]]
1733 [GET_MODE (*curr_id
->operand_loc
[m
])]);
1736 /* We prefer no matching alternatives because
1737 it gives more freedom in RA. */
1738 if (operand_reg
[nop
] == NULL_RTX
1739 || (find_regno_note (curr_insn
, REG_DEAD
,
1740 REGNO (operand_reg
[nop
]))
1743 if (lra_dump_file
!= NULL
)
1746 " %d Matching alt: reject+=2\n",
1751 /* If we have to reload this operand and some
1752 previous operand also had to match the same
1753 thing as this operand, we don't know how to do
1755 if (!match_p
|| !curr_alt_win
[m
])
1757 for (i
= 0; i
< nop
; i
++)
1758 if (curr_alt_matches
[i
] == m
)
1766 /* This can be fixed with reloads if the operand
1767 we are supposed to match can be fixed with
1770 this_alternative
= curr_alt
[m
];
1771 COPY_HARD_REG_SET (this_alternative_set
, curr_alt_set
[m
]);
1772 winreg
= this_alternative
!= NO_REGS
;
1777 cl
= base_reg_class (VOIDmode
, ADDR_SPACE_GENERIC
,
1779 this_alternative
= reg_class_subunion
[this_alternative
][cl
];
1780 IOR_HARD_REG_SET (this_alternative_set
,
1781 reg_class_contents
[cl
]);
1784 this_costly_alternative
1785 = reg_class_subunion
[this_costly_alternative
][cl
];
1786 IOR_HARD_REG_SET (this_costly_alternative_set
,
1787 reg_class_contents
[cl
]);
1793 case TARGET_MEM_CONSTRAINT
:
1794 if (MEM_P (op
) || spilled_pseudo_p (op
))
1796 /* We can put constant or pseudo value into memory
1797 to satisfy the constraint. */
1798 if (CONST_POOL_OK_P (mode
, op
) || REG_P (op
))
1805 && (GET_CODE (XEXP (op
, 0)) == PRE_DEC
1806 || GET_CODE (XEXP (op
, 0)) == POST_DEC
))
1812 && (GET_CODE (XEXP (op
, 0)) == PRE_INC
1813 || GET_CODE (XEXP (op
, 0)) == POST_INC
))
1817 /* Memory op whose address is not offsettable. */
1820 && ! offsettable_nonstrict_memref_p (op
))
1824 /* Memory operand whose address is offsettable. */
1827 && offsettable_nonstrict_memref_p (op
))
1828 || spilled_pseudo_p (op
))
1830 /* We can put constant or pseudo value into memory
1831 or make memory address offsetable to satisfy the
1833 if (CONST_POOL_OK_P (mode
, op
) || MEM_P (op
) || REG_P (op
))
1841 if (GET_CODE (op
) == CONST_DOUBLE
1842 || (GET_CODE (op
) == CONST_VECTOR
1843 && (GET_MODE_CLASS (mode
) == MODE_VECTOR_FLOAT
)))
1849 if (CONST_DOUBLE_AS_FLOAT_P (op
)
1850 && CONST_DOUBLE_OK_FOR_CONSTRAINT_P (op
, c
, p
))
1855 if (CONST_SCALAR_INT_P (op
))
1859 if (general_constant_p (op
))
1864 if (CONST_SCALAR_INT_P (op
))
1876 if (CONST_INT_P (op
)
1877 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op
), c
, p
))
1882 /* This constraint should be excluded by the fast
1889 || general_constant_p (op
)
1890 || spilled_pseudo_p (op
))
1892 /* Drop through into 'r' case. */
1896 = reg_class_subunion
[this_alternative
][GENERAL_REGS
];
1897 IOR_HARD_REG_SET (this_alternative_set
,
1898 reg_class_contents
[GENERAL_REGS
]);
1901 this_costly_alternative
1902 = (reg_class_subunion
1903 [this_costly_alternative
][GENERAL_REGS
]);
1904 IOR_HARD_REG_SET (this_costly_alternative_set
,
1905 reg_class_contents
[GENERAL_REGS
]);
1910 if (REG_CLASS_FROM_CONSTRAINT (c
, p
) == NO_REGS
)
1912 #ifdef EXTRA_CONSTRAINT_STR
1913 if (EXTRA_MEMORY_CONSTRAINT (c
, p
))
1915 if (EXTRA_CONSTRAINT_STR (op
, c
, p
))
1917 else if (spilled_pseudo_p (op
))
1920 /* If we didn't already win, we can reload
1921 constants via force_const_mem or put the
1922 pseudo value into memory, or make other
1923 memory by reloading the address like for
1925 if (CONST_POOL_OK_P (mode
, op
)
1926 || MEM_P (op
) || REG_P (op
))
1932 if (EXTRA_ADDRESS_CONSTRAINT (c
, p
))
1934 if (EXTRA_CONSTRAINT_STR (op
, c
, p
))
1937 /* If we didn't already win, we can reload
1938 the address into a base register. */
1939 cl
= base_reg_class (VOIDmode
, ADDR_SPACE_GENERIC
,
1942 = reg_class_subunion
[this_alternative
][cl
];
1943 IOR_HARD_REG_SET (this_alternative_set
,
1944 reg_class_contents
[cl
]);
1947 this_costly_alternative
1948 = (reg_class_subunion
1949 [this_costly_alternative
][cl
]);
1950 IOR_HARD_REG_SET (this_costly_alternative_set
,
1951 reg_class_contents
[cl
]);
1957 if (EXTRA_CONSTRAINT_STR (op
, c
, p
))
1963 cl
= REG_CLASS_FROM_CONSTRAINT (c
, p
);
1964 this_alternative
= reg_class_subunion
[this_alternative
][cl
];
1965 IOR_HARD_REG_SET (this_alternative_set
,
1966 reg_class_contents
[cl
]);
1969 this_costly_alternative
1970 = reg_class_subunion
[this_costly_alternative
][cl
];
1971 IOR_HARD_REG_SET (this_costly_alternative_set
,
1972 reg_class_contents
[cl
]);
1975 if (mode
== BLKmode
)
1980 if (hard_regno
[nop
] >= 0
1981 && in_hard_reg_set_p (this_alternative_set
,
1982 mode
, hard_regno
[nop
]))
1984 else if (hard_regno
[nop
] < 0
1985 && in_class_p (op
, this_alternative
, NULL
))
1990 if (c
!= ' ' && c
!= '\t')
1991 costly_p
= c
== '*';
1993 while ((p
+= len
), c
);
1995 scratch_p
= (operand_reg
[nop
] != NULL_RTX
1996 && lra_former_scratch_p (REGNO (operand_reg
[nop
])));
1997 /* Record which operands fit this alternative. */
2000 this_alternative_win
= true;
2001 if (operand_reg
[nop
] != NULL_RTX
)
2003 if (hard_regno
[nop
] >= 0)
2005 if (in_hard_reg_set_p (this_costly_alternative_set
,
2006 mode
, hard_regno
[nop
]))
2008 if (lra_dump_file
!= NULL
)
2009 fprintf (lra_dump_file
,
2010 " %d Costly set: reject++\n",
2017 /* Prefer won reg to spilled pseudo under other
2018 equal conditions for possibe inheritance. */
2021 if (lra_dump_file
!= NULL
)
2024 " %d Non pseudo reload: reject++\n",
2028 if (in_class_p (operand_reg
[nop
],
2029 this_costly_alternative
, NULL
))
2031 if (lra_dump_file
!= NULL
)
2034 " %d Non pseudo costly reload:"
2040 /* We simulate the behaviour of old reload here.
2041 Although scratches need hard registers and it
2042 might result in spilling other pseudos, no reload
2043 insns are generated for the scratches. So it
2044 might cost something but probably less than old
2045 reload pass believes. */
2048 if (lra_dump_file
!= NULL
)
2049 fprintf (lra_dump_file
,
2050 " %d Scratch win: reject+=2\n",
2057 this_alternative_match_win
= true;
2060 int const_to_mem
= 0;
2063 /* Never do output reload of stack pointer. It makes
2064 impossible to do elimination when SP is changed in
2066 if (op
== stack_pointer_rtx
&& ! frame_pointer_needed
2067 && curr_static_id
->operand
[nop
].type
!= OP_IN
)
2070 /* If this alternative asks for a specific reg class, see if there
2071 is at least one allocatable register in that class. */
2073 = (this_alternative
== NO_REGS
2074 || (hard_reg_set_subset_p
2075 (reg_class_contents
[this_alternative
],
2076 lra_no_alloc_regs
)));
2078 /* For asms, verify that the class for this alternative is possible
2079 for the mode that is specified. */
2080 if (!no_regs_p
&& INSN_CODE (curr_insn
) < 0)
2083 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
2084 if (HARD_REGNO_MODE_OK (i
, mode
)
2085 && in_hard_reg_set_p (reg_class_contents
[this_alternative
],
2088 if (i
== FIRST_PSEUDO_REGISTER
)
2092 /* If this operand accepts a register, and if the
2093 register class has at least one allocatable register,
2094 then this operand can be reloaded. */
2095 if (winreg
&& !no_regs_p
)
2100 if (lra_dump_file
!= NULL
)
2101 fprintf (lra_dump_file
,
2102 " alt=%d: Bad operand -- refuse\n",
2107 this_alternative_offmemok
= offmemok
;
2108 if (this_costly_alternative
!= NO_REGS
)
2110 if (lra_dump_file
!= NULL
)
2111 fprintf (lra_dump_file
,
2112 " %d Costly loser: reject++\n", nop
);
2115 /* If the operand is dying, has a matching constraint,
2116 and satisfies constraints of the matched operand
2117 which failed to satisfy the own constraints, probably
2118 the reload for this operand will be gone. */
2119 if (this_alternative_matches
>= 0
2120 && !curr_alt_win
[this_alternative_matches
]
2122 && find_regno_note (curr_insn
, REG_DEAD
, REGNO (op
))
2123 && (hard_regno
[nop
] >= 0
2124 ? in_hard_reg_set_p (this_alternative_set
,
2125 mode
, hard_regno
[nop
])
2126 : in_class_p (op
, this_alternative
, NULL
)))
2128 if (lra_dump_file
!= NULL
)
2131 " %d Dying matched operand reload: reject++\n",
2137 /* Strict_low_part requires to reload the register
2138 not the sub-register. In this case we should
2139 check that a final reload hard reg can hold the
2141 if (curr_static_id
->operand
[nop
].strict_low
2143 && hard_regno
[nop
] < 0
2144 && GET_CODE (*curr_id
->operand_loc
[nop
]) == SUBREG
2145 && ira_class_hard_regs_num
[this_alternative
] > 0
2146 && ! HARD_REGNO_MODE_OK (ira_class_hard_regs
2147 [this_alternative
][0],
2149 (*curr_id
->operand_loc
[nop
])))
2151 if (lra_dump_file
!= NULL
)
2154 " alt=%d: Strict low subreg reload -- refuse\n",
2160 if (operand_reg
[nop
] != NULL_RTX
2161 /* Output operands and matched input operands are
2162 not inherited. The following conditions do not
2163 exactly describe the previous statement but they
2164 are pretty close. */
2165 && curr_static_id
->operand
[nop
].type
!= OP_OUT
2166 && (this_alternative_matches
< 0
2167 || curr_static_id
->operand
[nop
].type
!= OP_IN
))
2169 int last_reload
= (lra_reg_info
[ORIGINAL_REGNO
2173 if (last_reload
> bb_reload_num
)
2174 reload_sum
+= last_reload
- bb_reload_num
;
2176 /* If this is a constant that is reloaded into the
2177 desired class by copying it to memory first, count
2178 that as another reload. This is consistent with
2179 other code and is required to avoid choosing another
2180 alternative when the constant is moved into memory.
2181 Note that the test here is precisely the same as in
2182 the code below that calls force_const_mem. */
2183 if (CONST_POOL_OK_P (mode
, op
)
2184 && ((targetm
.preferred_reload_class
2185 (op
, this_alternative
) == NO_REGS
)
2186 || no_input_reloads_p
))
2193 /* Alternative loses if it requires a type of reload not
2194 permitted for this insn. We can always reload
2195 objects with a REG_UNUSED note. */
2196 if ((curr_static_id
->operand
[nop
].type
!= OP_IN
2197 && no_output_reloads_p
2198 && ! find_reg_note (curr_insn
, REG_UNUSED
, op
))
2199 || (curr_static_id
->operand
[nop
].type
!= OP_OUT
2200 && no_input_reloads_p
&& ! const_to_mem
)
2201 || (this_alternative_matches
>= 0
2202 && (no_input_reloads_p
|| no_output_reloads_p
)))
2204 if (lra_dump_file
!= NULL
)
2207 " alt=%d: No input/otput reload -- refuse\n",
2212 /* Check strong discouragement of reload of non-constant
2213 into class THIS_ALTERNATIVE. */
2214 if (! CONSTANT_P (op
) && ! no_regs_p
2215 && (targetm
.preferred_reload_class
2216 (op
, this_alternative
) == NO_REGS
2217 || (curr_static_id
->operand
[nop
].type
== OP_OUT
2218 && (targetm
.preferred_output_reload_class
2219 (op
, this_alternative
) == NO_REGS
))))
2221 if (lra_dump_file
!= NULL
)
2222 fprintf (lra_dump_file
,
2223 " %d Non-prefered reload: reject+=%d\n",
2224 nop
, LRA_MAX_REJECT
);
2225 reject
+= LRA_MAX_REJECT
;
2228 if (! (MEM_P (op
) && offmemok
)
2229 && ! (const_to_mem
&& constmemok
))
2231 /* We prefer to reload pseudos over reloading other
2232 things, since such reloads may be able to be
2233 eliminated later. So bump REJECT in other cases.
2234 Don't do this in the case where we are forcing a
2235 constant into memory and it will then win since
2236 we don't want to have a different alternative
2238 if (! (REG_P (op
) && REGNO (op
) >= FIRST_PSEUDO_REGISTER
))
2240 if (lra_dump_file
!= NULL
)
2243 " %d Non-pseudo reload: reject+=2\n",
2250 += ira_reg_class_max_nregs
[this_alternative
][mode
];
2252 if (SMALL_REGISTER_CLASS_P (this_alternative
))
2254 if (lra_dump_file
!= NULL
)
2257 " %d Small class reload: reject+=%d\n",
2258 nop
, LRA_LOSER_COST_FACTOR
/ 2);
2259 reject
+= LRA_LOSER_COST_FACTOR
/ 2;
2263 /* We are trying to spill pseudo into memory. It is
2264 usually more costly than moving to a hard register
2265 although it might takes the same number of
2267 if (no_regs_p
&& REG_P (op
) && hard_regno
[nop
] >= 0)
2269 if (lra_dump_file
!= NULL
)
2272 " %d Spill pseudo in memory: reject+=3\n",
2277 #ifdef SECONDARY_MEMORY_NEEDED
2278 /* If reload requires moving value through secondary
2279 memory, it will need one more insn at least. */
2280 if (this_alternative
!= NO_REGS
2281 && REG_P (op
) && (cl
= get_reg_class (REGNO (op
))) != NO_REGS
2282 && ((curr_static_id
->operand
[nop
].type
!= OP_OUT
2283 && SECONDARY_MEMORY_NEEDED (cl
, this_alternative
,
2285 || (curr_static_id
->operand
[nop
].type
!= OP_IN
2286 && SECONDARY_MEMORY_NEEDED (this_alternative
, cl
,
2290 /* Input reloads can be inherited more often than output
2291 reloads can be removed, so penalize output
2293 if (!REG_P (op
) || curr_static_id
->operand
[nop
].type
!= OP_IN
)
2295 if (lra_dump_file
!= NULL
)
2298 " %d Non input pseudo reload: reject++\n",
2304 if (early_clobber_p
&& ! scratch_p
)
2306 if (lra_dump_file
!= NULL
)
2307 fprintf (lra_dump_file
,
2308 " %d Early clobber: reject++\n", nop
);
2311 /* ??? We check early clobbers after processing all operands
2312 (see loop below) and there we update the costs more.
2313 Should we update the cost (may be approximately) here
2314 because of early clobber register reloads or it is a rare
2315 or non-important thing to be worth to do it. */
2316 overall
= losers
* LRA_LOSER_COST_FACTOR
+ reject
;
2317 if ((best_losers
== 0 || losers
!= 0) && best_overall
< overall
)
2319 if (lra_dump_file
!= NULL
)
2320 fprintf (lra_dump_file
,
2321 " alt=%d,overall=%d,losers=%d -- refuse\n",
2322 nalt
, overall
, losers
);
2326 curr_alt
[nop
] = this_alternative
;
2327 COPY_HARD_REG_SET (curr_alt_set
[nop
], this_alternative_set
);
2328 curr_alt_win
[nop
] = this_alternative_win
;
2329 curr_alt_match_win
[nop
] = this_alternative_match_win
;
2330 curr_alt_offmemok
[nop
] = this_alternative_offmemok
;
2331 curr_alt_matches
[nop
] = this_alternative_matches
;
2333 if (this_alternative_matches
>= 0
2334 && !did_match
&& !this_alternative_win
)
2335 curr_alt_win
[this_alternative_matches
] = false;
2337 if (early_clobber_p
&& operand_reg
[nop
] != NULL_RTX
)
2338 early_clobbered_nops
[early_clobbered_regs_num
++] = nop
;
2340 if (curr_insn_set
!= NULL_RTX
&& n_operands
== 2
2341 /* Prevent processing non-move insns. */
2342 && (GET_CODE (SET_SRC (curr_insn_set
)) == SUBREG
2343 || SET_SRC (curr_insn_set
) == no_subreg_reg_operand
[1])
2344 && ((! curr_alt_win
[0] && ! curr_alt_win
[1]
2345 && REG_P (no_subreg_reg_operand
[0])
2346 && REG_P (no_subreg_reg_operand
[1])
2347 && (reg_in_class_p (no_subreg_reg_operand
[0], curr_alt
[1])
2348 || reg_in_class_p (no_subreg_reg_operand
[1], curr_alt
[0])))
2349 || (! curr_alt_win
[0] && curr_alt_win
[1]
2350 && REG_P (no_subreg_reg_operand
[1])
2351 && reg_in_class_p (no_subreg_reg_operand
[1], curr_alt
[0]))
2352 || (curr_alt_win
[0] && ! curr_alt_win
[1]
2353 && REG_P (no_subreg_reg_operand
[0])
2354 && reg_in_class_p (no_subreg_reg_operand
[0], curr_alt
[1])
2355 && (! CONST_POOL_OK_P (curr_operand_mode
[1],
2356 no_subreg_reg_operand
[1])
2357 || (targetm
.preferred_reload_class
2358 (no_subreg_reg_operand
[1],
2359 (enum reg_class
) curr_alt
[1]) != NO_REGS
))
2360 /* If it is a result of recent elimination in move
2361 insn we can transform it into an add still by
2362 using this alternative. */
2363 && GET_CODE (no_subreg_reg_operand
[1]) != PLUS
)))
2365 /* We have a move insn and a new reload insn will be similar
2366 to the current insn. We should avoid such situation as it
2367 results in LRA cycling. */
2368 overall
+= LRA_MAX_REJECT
;
2371 curr_alt_dont_inherit_ops_num
= 0;
2372 for (nop
= 0; nop
< early_clobbered_regs_num
; nop
++)
2374 int i
, j
, clobbered_hard_regno
, first_conflict_j
, last_conflict_j
;
2375 HARD_REG_SET temp_set
;
2377 i
= early_clobbered_nops
[nop
];
2378 if ((! curr_alt_win
[i
] && ! curr_alt_match_win
[i
])
2379 || hard_regno
[i
] < 0)
2381 lra_assert (operand_reg
[i
] != NULL_RTX
);
2382 clobbered_hard_regno
= hard_regno
[i
];
2383 CLEAR_HARD_REG_SET (temp_set
);
2384 add_to_hard_reg_set (&temp_set
, biggest_mode
[i
], clobbered_hard_regno
);
2385 first_conflict_j
= last_conflict_j
= -1;
2386 for (j
= 0; j
< n_operands
; j
++)
2388 /* We don't want process insides of match_operator and
2389 match_parallel because otherwise we would process
2390 their operands once again generating a wrong
2392 || curr_static_id
->operand
[j
].is_operator
)
2394 else if ((curr_alt_matches
[j
] == i
&& curr_alt_match_win
[j
])
2395 || (curr_alt_matches
[i
] == j
&& curr_alt_match_win
[i
]))
2397 /* If we don't reload j-th operand, check conflicts. */
2398 else if ((curr_alt_win
[j
] || curr_alt_match_win
[j
])
2399 && uses_hard_regs_p (*curr_id
->operand_loc
[j
], temp_set
))
2401 if (first_conflict_j
< 0)
2402 first_conflict_j
= j
;
2403 last_conflict_j
= j
;
2405 if (last_conflict_j
< 0)
2407 /* If earlyclobber operand conflicts with another
2408 non-matching operand which is actually the same register
2409 as the earlyclobber operand, it is better to reload the
2410 another operand as an operand matching the earlyclobber
2411 operand can be also the same. */
2412 if (first_conflict_j
== last_conflict_j
2413 && operand_reg
[last_conflict_j
]
2414 != NULL_RTX
&& ! curr_alt_match_win
[last_conflict_j
]
2415 && REGNO (operand_reg
[i
]) == REGNO (operand_reg
[last_conflict_j
]))
2417 curr_alt_win
[last_conflict_j
] = false;
2418 curr_alt_dont_inherit_ops
[curr_alt_dont_inherit_ops_num
++]
2421 /* Early clobber was already reflected in REJECT. */
2422 lra_assert (reject
> 0);
2423 if (lra_dump_file
!= NULL
)
2426 " %d Conflict early clobber reload: reject--\n",
2429 overall
+= LRA_LOSER_COST_FACTOR
- 1;
2433 /* We need to reload early clobbered register and the
2434 matched registers. */
2435 for (j
= 0; j
< n_operands
; j
++)
2436 if (curr_alt_matches
[j
] == i
)
2438 curr_alt_match_win
[j
] = false;
2440 overall
+= LRA_LOSER_COST_FACTOR
;
2442 if (! curr_alt_match_win
[i
])
2443 curr_alt_dont_inherit_ops
[curr_alt_dont_inherit_ops_num
++] = i
;
2446 /* Remember pseudos used for match reloads are never
2448 lra_assert (curr_alt_matches
[i
] >= 0);
2449 curr_alt_win
[curr_alt_matches
[i
]] = false;
2451 curr_alt_win
[i
] = curr_alt_match_win
[i
] = false;
2453 /* Early clobber was already reflected in REJECT. */
2454 lra_assert (reject
> 0);
2455 if (lra_dump_file
!= NULL
)
2458 " %d Matched conflict early clobber reloads:"
2462 overall
+= LRA_LOSER_COST_FACTOR
- 1;
2465 if (lra_dump_file
!= NULL
)
2466 fprintf (lra_dump_file
, " alt=%d,overall=%d,losers=%d,rld_nregs=%d\n",
2467 nalt
, overall
, losers
, reload_nregs
);
2469 /* If this alternative can be made to work by reloading, and it
2470 needs less reloading than the others checked so far, record
2471 it as the chosen goal for reloading. */
2472 if ((best_losers
!= 0 && losers
== 0)
2473 || (((best_losers
== 0 && losers
== 0)
2474 || (best_losers
!= 0 && losers
!= 0))
2475 && (best_overall
> overall
2476 || (best_overall
== overall
2477 /* If the cost of the reloads is the same,
2478 prefer alternative which requires minimal
2479 number of reload regs. */
2480 && (reload_nregs
< best_reload_nregs
2481 || (reload_nregs
== best_reload_nregs
2482 && (best_reload_sum
< reload_sum
2483 || (best_reload_sum
== reload_sum
2484 && nalt
< goal_alt_number
))))))))
2486 for (nop
= 0; nop
< n_operands
; nop
++)
2488 goal_alt_win
[nop
] = curr_alt_win
[nop
];
2489 goal_alt_match_win
[nop
] = curr_alt_match_win
[nop
];
2490 goal_alt_matches
[nop
] = curr_alt_matches
[nop
];
2491 goal_alt
[nop
] = curr_alt
[nop
];
2492 goal_alt_offmemok
[nop
] = curr_alt_offmemok
[nop
];
2494 goal_alt_dont_inherit_ops_num
= curr_alt_dont_inherit_ops_num
;
2495 for (nop
= 0; nop
< curr_alt_dont_inherit_ops_num
; nop
++)
2496 goal_alt_dont_inherit_ops
[nop
] = curr_alt_dont_inherit_ops
[nop
];
2497 goal_alt_swapped
= curr_swapped
;
2498 best_overall
= overall
;
2499 best_losers
= losers
;
2500 best_reload_nregs
= reload_nregs
;
2501 best_reload_sum
= reload_sum
;
2502 goal_alt_number
= nalt
;
2505 /* Everything is satisfied. Do not process alternatives
2514 /* Return 1 if ADDR is a valid memory address for mode MODE in address
2515 space AS, and check that each pseudo has the proper kind of hard
2518 valid_address_p (enum machine_mode mode ATTRIBUTE_UNUSED
,
2519 rtx addr
, addr_space_t as
)
2521 #ifdef GO_IF_LEGITIMATE_ADDRESS
2522 lra_assert (ADDR_SPACE_GENERIC_P (as
));
2523 GO_IF_LEGITIMATE_ADDRESS (mode
, addr
, win
);
2529 return targetm
.addr_space
.legitimate_address_p (mode
, addr
, 0, as
);
2533 /* Return whether address AD is valid. */
2536 valid_address_p (struct address_info
*ad
)
2538 /* Some ports do not check displacements for eliminable registers,
2539 so we replace them temporarily with the elimination target. */
2540 rtx saved_base_reg
= NULL_RTX
;
2541 rtx saved_index_reg
= NULL_RTX
;
2542 rtx
*base_term
= strip_subreg (ad
->base_term
);
2543 rtx
*index_term
= strip_subreg (ad
->index_term
);
2544 if (base_term
!= NULL
)
2546 saved_base_reg
= *base_term
;
2547 lra_eliminate_reg_if_possible (base_term
);
2548 if (ad
->base_term2
!= NULL
)
2549 *ad
->base_term2
= *ad
->base_term
;
2551 if (index_term
!= NULL
)
2553 saved_index_reg
= *index_term
;
2554 lra_eliminate_reg_if_possible (index_term
);
2556 bool ok_p
= valid_address_p (ad
->mode
, *ad
->outer
, ad
->as
);
2557 if (saved_base_reg
!= NULL_RTX
)
2559 *base_term
= saved_base_reg
;
2560 if (ad
->base_term2
!= NULL
)
2561 *ad
->base_term2
= *ad
->base_term
;
2563 if (saved_index_reg
!= NULL_RTX
)
2564 *index_term
= saved_index_reg
;
2568 /* Make reload base reg + disp from address AD. Return the new pseudo. */
2570 base_plus_disp_to_reg (struct address_info
*ad
)
2575 lra_assert (ad
->base
== ad
->base_term
&& ad
->disp
== ad
->disp_term
);
2576 cl
= base_reg_class (ad
->mode
, ad
->as
, ad
->base_outer_code
,
2577 get_index_code (ad
));
2578 new_reg
= lra_create_new_reg (GET_MODE (*ad
->base_term
), NULL_RTX
,
2580 lra_emit_add (new_reg
, *ad
->base_term
, *ad
->disp_term
);
2584 /* Return true if we can add a displacement to address AD, even if that
2585 makes the address invalid. The fix-up code requires any new address
2586 to be the sum of the BASE_TERM, INDEX and DISP_TERM fields. */
2588 can_add_disp_p (struct address_info
*ad
)
2590 return (!ad
->autoinc_p
2591 && ad
->segment
== NULL
2592 && ad
->base
== ad
->base_term
2593 && ad
->disp
== ad
->disp_term
);
2596 /* Make equiv substitution in address AD. Return true if a substitution
2599 equiv_address_substitution (struct address_info
*ad
)
2601 rtx base_reg
, new_base_reg
, index_reg
, new_index_reg
, *base_term
, *index_term
;
2602 HOST_WIDE_INT disp
, scale
;
2605 base_term
= strip_subreg (ad
->base_term
);
2606 if (base_term
== NULL
)
2607 base_reg
= new_base_reg
= NULL_RTX
;
2610 base_reg
= *base_term
;
2611 new_base_reg
= get_equiv_with_elimination (base_reg
, curr_insn
);
2613 index_term
= strip_subreg (ad
->index_term
);
2614 if (index_term
== NULL
)
2615 index_reg
= new_index_reg
= NULL_RTX
;
2618 index_reg
= *index_term
;
2619 new_index_reg
= get_equiv_with_elimination (index_reg
, curr_insn
);
2621 if (base_reg
== new_base_reg
&& index_reg
== new_index_reg
)
2625 if (lra_dump_file
!= NULL
)
2627 fprintf (lra_dump_file
, "Changing address in insn %d ",
2628 INSN_UID (curr_insn
));
2629 dump_value_slim (lra_dump_file
, *ad
->outer
, 1);
2631 if (base_reg
!= new_base_reg
)
2633 if (REG_P (new_base_reg
))
2635 *base_term
= new_base_reg
;
2638 else if (GET_CODE (new_base_reg
) == PLUS
2639 && REG_P (XEXP (new_base_reg
, 0))
2640 && CONST_INT_P (XEXP (new_base_reg
, 1))
2641 && can_add_disp_p (ad
))
2643 disp
+= INTVAL (XEXP (new_base_reg
, 1));
2644 *base_term
= XEXP (new_base_reg
, 0);
2647 if (ad
->base_term2
!= NULL
)
2648 *ad
->base_term2
= *ad
->base_term
;
2650 if (index_reg
!= new_index_reg
)
2652 if (REG_P (new_index_reg
))
2654 *index_term
= new_index_reg
;
2657 else if (GET_CODE (new_index_reg
) == PLUS
2658 && REG_P (XEXP (new_index_reg
, 0))
2659 && CONST_INT_P (XEXP (new_index_reg
, 1))
2660 && can_add_disp_p (ad
)
2661 && (scale
= get_index_scale (ad
)))
2663 disp
+= INTVAL (XEXP (new_index_reg
, 1)) * scale
;
2664 *index_term
= XEXP (new_index_reg
, 0);
2670 if (ad
->disp
!= NULL
)
2671 *ad
->disp
= plus_constant (GET_MODE (*ad
->inner
), *ad
->disp
, disp
);
2674 *ad
->inner
= plus_constant (GET_MODE (*ad
->inner
), *ad
->inner
, disp
);
2675 update_address (ad
);
2679 if (lra_dump_file
!= NULL
)
2682 fprintf (lra_dump_file
, " -- no change\n");
2685 fprintf (lra_dump_file
, " on equiv ");
2686 dump_value_slim (lra_dump_file
, *ad
->outer
, 1);
2687 fprintf (lra_dump_file
, "\n");
2693 /* Major function to make reloads for an address in operand NOP.
2694 The supported cases are:
2696 1) an address that existed before LRA started, at which point it
2697 must have been valid. These addresses are subject to elimination
2698 and may have become invalid due to the elimination offset being out
2701 2) an address created by forcing a constant to memory
2702 (force_const_to_mem). The initial form of these addresses might
2703 not be valid, and it is this function's job to make them valid.
2705 3) a frame address formed from a register and a (possibly zero)
2706 constant offset. As above, these addresses might not be valid and
2707 this function must make them so.
2709 Add reloads to the lists *BEFORE and *AFTER. We might need to add
2710 reloads to *AFTER because of inc/dec, {pre, post} modify in the
2711 address. Return true for any RTL change. */
2713 process_address (int nop
, rtx
*before
, rtx
*after
)
2715 struct address_info ad
;
2717 rtx op
= *curr_id
->operand_loc
[nop
];
2718 const char *constraint
= curr_static_id
->operand
[nop
].constraint
;
2721 if (constraint
[0] == 'p'
2722 || EXTRA_ADDRESS_CONSTRAINT (constraint
[0], constraint
))
2723 decompose_lea_address (&ad
, curr_id
->operand_loc
[nop
]);
2724 else if (MEM_P (op
))
2725 decompose_mem_address (&ad
, op
);
2726 else if (GET_CODE (op
) == SUBREG
2727 && MEM_P (SUBREG_REG (op
)))
2728 decompose_mem_address (&ad
, SUBREG_REG (op
));
2731 change_p
= equiv_address_substitution (&ad
);
2732 if (ad
.base_term
!= NULL
2733 && (process_addr_reg
2734 (ad
.base_term
, before
,
2736 && !(REG_P (*ad
.base_term
)
2737 && find_regno_note (curr_insn
, REG_DEAD
,
2738 REGNO (*ad
.base_term
)) != NULL_RTX
)
2740 base_reg_class (ad
.mode
, ad
.as
, ad
.base_outer_code
,
2741 get_index_code (&ad
)))))
2744 if (ad
.base_term2
!= NULL
)
2745 *ad
.base_term2
= *ad
.base_term
;
2747 if (ad
.index_term
!= NULL
2748 && process_addr_reg (ad
.index_term
, before
, NULL
, INDEX_REG_CLASS
))
2751 #ifdef EXTRA_CONSTRAINT_STR
2752 /* Target hooks sometimes reject extra constraint addresses -- use
2753 EXTRA_CONSTRAINT_STR for the validation. */
2754 if (constraint
[0] != 'p'
2755 && EXTRA_ADDRESS_CONSTRAINT (constraint
[0], constraint
)
2756 && EXTRA_CONSTRAINT_STR (op
, constraint
[0], constraint
))
2760 /* There are three cases where the shape of *AD.INNER may now be invalid:
2762 1) the original address was valid, but either elimination or
2763 equiv_address_substitution was applied and that made
2764 the address invalid.
2766 2) the address is an invalid symbolic address created by
2769 3) the address is a frame address with an invalid offset.
2771 All these cases involve a non-autoinc address, so there is no
2772 point revalidating other types. */
2773 if (ad
.autoinc_p
|| valid_address_p (&ad
))
2776 /* Any index existed before LRA started, so we can assume that the
2777 presence and shape of the index is valid. */
2778 push_to_sequence (*before
);
2779 lra_assert (ad
.disp
== ad
.disp_term
);
2780 if (ad
.base
== NULL
)
2782 if (ad
.index
== NULL
)
2785 enum reg_class cl
= base_reg_class (ad
.mode
, ad
.as
,
2787 rtx addr
= *ad
.inner
;
2789 new_reg
= lra_create_new_reg (Pmode
, NULL_RTX
, cl
, "addr");
2793 rtx last
= get_last_insn ();
2795 /* addr => lo_sum (new_base, addr), case (2) above. */
2796 insn
= emit_insn (gen_rtx_SET
2798 gen_rtx_HIGH (Pmode
, copy_rtx (addr
))));
2799 code
= recog_memoized (insn
);
2802 *ad
.inner
= gen_rtx_LO_SUM (Pmode
, new_reg
, addr
);
2803 if (! valid_address_p (ad
.mode
, *ad
.outer
, ad
.as
))
2805 /* Try to put lo_sum into register. */
2806 insn
= emit_insn (gen_rtx_SET
2808 gen_rtx_LO_SUM (Pmode
, new_reg
, addr
)));
2809 code
= recog_memoized (insn
);
2812 *ad
.inner
= new_reg
;
2813 if (! valid_address_p (ad
.mode
, *ad
.outer
, ad
.as
))
2823 delete_insns_since (last
);
2828 /* addr => new_base, case (2) above. */
2829 lra_emit_move (new_reg
, addr
);
2830 *ad
.inner
= new_reg
;
2835 /* index * scale + disp => new base + index * scale,
2837 enum reg_class cl
= base_reg_class (ad
.mode
, ad
.as
, PLUS
,
2838 GET_CODE (*ad
.index
));
2840 lra_assert (INDEX_REG_CLASS
!= NO_REGS
);
2841 new_reg
= lra_create_new_reg (Pmode
, NULL_RTX
, cl
, "disp");
2842 lra_emit_move (new_reg
, *ad
.disp
);
2843 *ad
.inner
= simplify_gen_binary (PLUS
, GET_MODE (new_reg
),
2844 new_reg
, *ad
.index
);
2847 else if (ad
.index
== NULL
)
2851 rtx set
, insns
, last_insn
;
2852 /* base + disp => new base, cases (1) and (3) above. */
2853 /* Another option would be to reload the displacement into an
2854 index register. However, postreload has code to optimize
2855 address reloads that have the same base and different
2856 displacements, so reloading into an index register would
2857 not necessarily be a win. */
2859 new_reg
= base_plus_disp_to_reg (&ad
);
2860 insns
= get_insns ();
2861 last_insn
= get_last_insn ();
2862 /* If we generated at least two insns, try last insn source as
2863 an address. If we succeed, we generate one less insn. */
2864 if (last_insn
!= insns
&& (set
= single_set (last_insn
)) != NULL_RTX
2865 && GET_CODE (SET_SRC (set
)) == PLUS
2866 && REG_P (XEXP (SET_SRC (set
), 0))
2867 && CONSTANT_P (XEXP (SET_SRC (set
), 1)))
2869 *ad
.inner
= SET_SRC (set
);
2870 if (valid_address_p (ad
.mode
, *ad
.outer
, ad
.as
))
2872 *ad
.base_term
= XEXP (SET_SRC (set
), 0);
2873 *ad
.disp_term
= XEXP (SET_SRC (set
), 1);
2874 cl
= base_reg_class (ad
.mode
, ad
.as
, ad
.base_outer_code
,
2875 get_index_code (&ad
));
2876 regno
= REGNO (*ad
.base_term
);
2877 if (regno
>= FIRST_PSEUDO_REGISTER
2878 && cl
!= lra_get_allocno_class (regno
))
2879 lra_change_class (regno
, cl
, " Change to", true);
2880 new_reg
= SET_SRC (set
);
2881 delete_insns_since (PREV_INSN (last_insn
));
2886 *ad
.inner
= new_reg
;
2890 /* base + scale * index + disp => new base + scale * index,
2892 new_reg
= base_plus_disp_to_reg (&ad
);
2893 *ad
.inner
= simplify_gen_binary (PLUS
, GET_MODE (new_reg
),
2894 new_reg
, *ad
.index
);
2896 *before
= get_insns ();
2901 /* Emit insns to reload VALUE into a new register. VALUE is an
2902 auto-increment or auto-decrement RTX whose operand is a register or
2903 memory location; so reloading involves incrementing that location.
2904 IN is either identical to VALUE, or some cheaper place to reload
2905 value being incremented/decremented from.
2907 INC_AMOUNT is the number to increment or decrement by (always
2908 positive and ignored for POST_MODIFY/PRE_MODIFY).
2910 Return pseudo containing the result. */
2912 emit_inc (enum reg_class new_rclass
, rtx in
, rtx value
, int inc_amount
)
2914 /* REG or MEM to be copied and incremented. */
2915 rtx incloc
= XEXP (value
, 0);
2916 /* Nonzero if increment after copying. */
2917 int post
= (GET_CODE (value
) == POST_DEC
|| GET_CODE (value
) == POST_INC
2918 || GET_CODE (value
) == POST_MODIFY
);
2923 rtx real_in
= in
== value
? incloc
: in
;
2927 if (GET_CODE (value
) == PRE_MODIFY
|| GET_CODE (value
) == POST_MODIFY
)
2929 lra_assert (GET_CODE (XEXP (value
, 1)) == PLUS
2930 || GET_CODE (XEXP (value
, 1)) == MINUS
);
2931 lra_assert (rtx_equal_p (XEXP (XEXP (value
, 1), 0), XEXP (value
, 0)));
2932 plus_p
= GET_CODE (XEXP (value
, 1)) == PLUS
;
2933 inc
= XEXP (XEXP (value
, 1), 1);
2937 if (GET_CODE (value
) == PRE_DEC
|| GET_CODE (value
) == POST_DEC
)
2938 inc_amount
= -inc_amount
;
2940 inc
= GEN_INT (inc_amount
);
2943 if (! post
&& REG_P (incloc
))
2946 result
= lra_create_new_reg (GET_MODE (value
), value
, new_rclass
,
2949 if (real_in
!= result
)
2951 /* First copy the location to the result register. */
2952 lra_assert (REG_P (result
));
2953 emit_insn (gen_move_insn (result
, real_in
));
2956 /* We suppose that there are insns to add/sub with the constant
2957 increment permitted in {PRE/POST)_{DEC/INC/MODIFY}. At least the
2958 old reload worked with this assumption. If the assumption
2959 becomes wrong, we should use approach in function
2960 base_plus_disp_to_reg. */
2963 /* See if we can directly increment INCLOC. */
2964 last
= get_last_insn ();
2965 add_insn
= emit_insn (plus_p
2966 ? gen_add2_insn (incloc
, inc
)
2967 : gen_sub2_insn (incloc
, inc
));
2969 code
= recog_memoized (add_insn
);
2972 if (! post
&& result
!= incloc
)
2973 emit_insn (gen_move_insn (result
, incloc
));
2976 delete_insns_since (last
);
2979 /* If couldn't do the increment directly, must increment in RESULT.
2980 The way we do this depends on whether this is pre- or
2981 post-increment. For pre-increment, copy INCLOC to the reload
2982 register, increment it there, then save back. */
2985 if (real_in
!= result
)
2986 emit_insn (gen_move_insn (result
, real_in
));
2988 emit_insn (gen_add2_insn (result
, inc
));
2990 emit_insn (gen_sub2_insn (result
, inc
));
2991 if (result
!= incloc
)
2992 emit_insn (gen_move_insn (incloc
, result
));
2998 Because this might be a jump insn or a compare, and because
2999 RESULT may not be available after the insn in an input
3000 reload, we must do the incrementing before the insn being
3003 We have already copied IN to RESULT. Increment the copy in
3004 RESULT, save that back, then decrement RESULT so it has
3005 the original value. */
3007 emit_insn (gen_add2_insn (result
, inc
));
3009 emit_insn (gen_sub2_insn (result
, inc
));
3010 emit_insn (gen_move_insn (incloc
, result
));
3011 /* Restore non-modified value for the result. We prefer this
3012 way because it does not require an additional hard
3016 if (CONST_INT_P (inc
))
3017 emit_insn (gen_add2_insn (result
,
3018 gen_int_mode (-INTVAL (inc
),
3019 GET_MODE (result
))));
3021 emit_insn (gen_sub2_insn (result
, inc
));
3024 emit_insn (gen_add2_insn (result
, inc
));
3029 /* Return true if the current move insn does not need processing as we
3030 already know that it satisfies its constraints. */
3032 simple_move_p (void)
3035 enum reg_class dclass
, sclass
;
3037 lra_assert (curr_insn_set
!= NULL_RTX
);
3038 dest
= SET_DEST (curr_insn_set
);
3039 src
= SET_SRC (curr_insn_set
);
3040 return ((dclass
= get_op_class (dest
)) != NO_REGS
3041 && (sclass
= get_op_class (src
)) != NO_REGS
3042 /* The backend guarantees that register moves of cost 2
3043 never need reloads. */
3044 && targetm
.register_move_cost (GET_MODE (src
), dclass
, sclass
) == 2);
3047 /* Swap operands NOP and NOP + 1. */
3049 swap_operands (int nop
)
3051 enum machine_mode mode
= curr_operand_mode
[nop
];
3052 curr_operand_mode
[nop
] = curr_operand_mode
[nop
+ 1];
3053 curr_operand_mode
[nop
+ 1] = mode
;
3054 rtx x
= *curr_id
->operand_loc
[nop
];
3055 *curr_id
->operand_loc
[nop
] = *curr_id
->operand_loc
[nop
+ 1];
3056 *curr_id
->operand_loc
[nop
+ 1] = x
;
3057 /* Swap the duplicates too. */
3058 lra_update_dup (curr_id
, nop
);
3059 lra_update_dup (curr_id
, nop
+ 1);
3062 /* Main entry point of the constraint code: search the body of the
3063 current insn to choose the best alternative. It is mimicking insn
3064 alternative cost calculation model of former reload pass. That is
3065 because machine descriptions were written to use this model. This
3066 model can be changed in future. Make commutative operand exchange
3069 Return true if some RTL changes happened during function call. */
3071 curr_insn_transform (void)
3077 signed char goal_alt_matched
[MAX_RECOG_OPERANDS
][MAX_RECOG_OPERANDS
];
3078 signed char match_inputs
[MAX_RECOG_OPERANDS
+ 1];
3081 /* Flag that the insn has been changed through a transformation. */
3084 #ifdef SECONDARY_MEMORY_NEEDED
3087 int max_regno_before
;
3088 int reused_alternative_num
;
3090 curr_insn_set
= single_set (curr_insn
);
3091 if (curr_insn_set
!= NULL_RTX
&& simple_move_p ())
3094 no_input_reloads_p
= no_output_reloads_p
= false;
3095 goal_alt_number
= -1;
3096 change_p
= sec_mem_p
= false;
3097 /* JUMP_INSNs and CALL_INSNs are not allowed to have any output
3098 reloads; neither are insns that SET cc0. Insns that use CC0 are
3099 not allowed to have any input reloads. */
3100 if (JUMP_P (curr_insn
) || CALL_P (curr_insn
))
3101 no_output_reloads_p
= true;
3104 if (reg_referenced_p (cc0_rtx
, PATTERN (curr_insn
)))
3105 no_input_reloads_p
= true;
3106 if (reg_set_p (cc0_rtx
, PATTERN (curr_insn
)))
3107 no_output_reloads_p
= true;
3110 n_operands
= curr_static_id
->n_operands
;
3111 n_alternatives
= curr_static_id
->n_alternatives
;
3113 /* Just return "no reloads" if insn has no operands with
3115 if (n_operands
== 0 || n_alternatives
== 0)
3118 max_regno_before
= max_reg_num ();
3120 for (i
= 0; i
< n_operands
; i
++)
3122 goal_alt_matched
[i
][0] = -1;
3123 goal_alt_matches
[i
] = -1;
3126 commutative
= curr_static_id
->commutative
;
3128 /* Now see what we need for pseudos that didn't get hard regs or got
3129 the wrong kind of hard reg. For this, we must consider all the
3130 operands together against the register constraints. */
3132 best_losers
= best_overall
= INT_MAX
;
3133 best_reload_sum
= 0;
3135 curr_swapped
= false;
3136 goal_alt_swapped
= false;
3138 /* Make equivalence substitution and memory subreg elimination
3139 before address processing because an address legitimacy can
3140 depend on memory mode. */
3141 for (i
= 0; i
< n_operands
; i
++)
3143 rtx op
= *curr_id
->operand_loc
[i
];
3144 rtx subst
, old
= op
;
3145 bool op_change_p
= false;
3147 if (GET_CODE (old
) == SUBREG
)
3148 old
= SUBREG_REG (old
);
3149 subst
= get_equiv_with_elimination (old
, curr_insn
);
3152 subst
= copy_rtx (subst
);
3153 lra_assert (REG_P (old
));
3154 if (GET_CODE (op
) == SUBREG
)
3155 SUBREG_REG (op
) = subst
;
3157 *curr_id
->operand_loc
[i
] = subst
;
3158 if (lra_dump_file
!= NULL
)
3160 fprintf (lra_dump_file
,
3161 "Changing pseudo %d in operand %i of insn %u on equiv ",
3162 REGNO (old
), i
, INSN_UID (curr_insn
));
3163 dump_value_slim (lra_dump_file
, subst
, 1);
3164 fprintf (lra_dump_file
, "\n");
3166 op_change_p
= change_p
= true;
3168 if (simplify_operand_subreg (i
, GET_MODE (old
)) || op_change_p
)
3171 lra_update_dup (curr_id
, i
);
3175 /* Reload address registers and displacements. We do it before
3176 finding an alternative because of memory constraints. */
3177 before
= after
= NULL_RTX
;
3178 for (i
= 0; i
< n_operands
; i
++)
3179 if (! curr_static_id
->operand
[i
].is_operator
3180 && process_address (i
, &before
, &after
))
3183 lra_update_dup (curr_id
, i
);
3187 /* If we've changed the instruction then any alternative that
3188 we chose previously may no longer be valid. */
3189 lra_set_used_insn_alternative (curr_insn
, -1);
3191 if (curr_insn_set
!= NULL_RTX
3192 && check_and_process_move (&change_p
, &sec_mem_p
))
3197 reused_alternative_num
= curr_id
->used_insn_alternative
;
3198 if (lra_dump_file
!= NULL
&& reused_alternative_num
>= 0)
3199 fprintf (lra_dump_file
, "Reusing alternative %d for insn #%u\n",
3200 reused_alternative_num
, INSN_UID (curr_insn
));
3202 if (process_alt_operands (reused_alternative_num
))
3205 /* If insn is commutative (it's safe to exchange a certain pair of
3206 operands) then we need to try each alternative twice, the second
3207 time matching those two operands as if we had exchanged them. To
3208 do this, really exchange them in operands.
3210 If we have just tried the alternatives the second time, return
3211 operands to normal and drop through. */
3213 if (reused_alternative_num
< 0 && commutative
>= 0)
3215 curr_swapped
= !curr_swapped
;
3218 swap_operands (commutative
);
3222 swap_operands (commutative
);
3225 if (! alt_p
&& ! sec_mem_p
)
3227 /* No alternative works with reloads?? */
3228 if (INSN_CODE (curr_insn
) >= 0)
3229 fatal_insn ("unable to generate reloads for:", curr_insn
);
3230 error_for_asm (curr_insn
,
3231 "inconsistent operand constraints in an %<asm%>");
3232 /* Avoid further trouble with this insn. */
3233 PATTERN (curr_insn
) = gen_rtx_USE (VOIDmode
, const0_rtx
);
3234 lra_invalidate_insn_data (curr_insn
);
3238 /* If the best alternative is with operands 1 and 2 swapped, swap
3239 them. Update the operand numbers of any reloads already
3242 if (goal_alt_swapped
)
3244 if (lra_dump_file
!= NULL
)
3245 fprintf (lra_dump_file
, " Commutative operand exchange in insn %u\n",
3246 INSN_UID (curr_insn
));
3248 /* Swap the duplicates too. */
3249 swap_operands (commutative
);
3253 #ifdef SECONDARY_MEMORY_NEEDED
3254 /* Some target macros SECONDARY_MEMORY_NEEDED (e.g. x86) are defined
3255 too conservatively. So we use the secondary memory only if there
3256 is no any alternative without reloads. */
3257 use_sec_mem_p
= false;
3259 use_sec_mem_p
= true;
3262 for (i
= 0; i
< n_operands
; i
++)
3263 if (! goal_alt_win
[i
] && ! goal_alt_match_win
[i
])
3265 use_sec_mem_p
= i
< n_operands
;
3270 rtx new_reg
, src
, dest
, rld
;
3271 enum machine_mode sec_mode
, rld_mode
;
3273 lra_assert (sec_mem_p
);
3274 lra_assert (curr_static_id
->operand
[0].type
== OP_OUT
3275 && curr_static_id
->operand
[1].type
== OP_IN
);
3276 dest
= *curr_id
->operand_loc
[0];
3277 src
= *curr_id
->operand_loc
[1];
3278 rld
= (GET_MODE_SIZE (GET_MODE (dest
)) <= GET_MODE_SIZE (GET_MODE (src
))
3280 rld_mode
= GET_MODE (rld
);
3281 #ifdef SECONDARY_MEMORY_NEEDED_MODE
3282 sec_mode
= SECONDARY_MEMORY_NEEDED_MODE (rld_mode
);
3284 sec_mode
= rld_mode
;
3286 new_reg
= lra_create_new_reg (sec_mode
, NULL_RTX
,
3287 NO_REGS
, "secondary");
3288 /* If the mode is changed, it should be wider. */
3289 lra_assert (GET_MODE_SIZE (sec_mode
) >= GET_MODE_SIZE (rld_mode
));
3290 if (sec_mode
!= rld_mode
)
3292 /* If the target says specifically to use another mode for
3293 secondary memory moves we can not reuse the original
3295 after
= emit_spill_move (false, new_reg
, dest
);
3296 lra_process_new_insns (curr_insn
, NULL_RTX
, after
,
3297 "Inserting the sec. move");
3298 /* We may have non null BEFORE here (e.g. after address
3300 push_to_sequence (before
);
3301 before
= emit_spill_move (true, new_reg
, src
);
3303 before
= get_insns ();
3305 lra_process_new_insns (curr_insn
, before
, NULL_RTX
, "Changing on");
3306 lra_set_insn_deleted (curr_insn
);
3308 else if (dest
== rld
)
3310 *curr_id
->operand_loc
[0] = new_reg
;
3311 after
= emit_spill_move (false, new_reg
, dest
);
3312 lra_process_new_insns (curr_insn
, NULL_RTX
, after
,
3313 "Inserting the sec. move");
3317 *curr_id
->operand_loc
[1] = new_reg
;
3318 /* See comments above. */
3319 push_to_sequence (before
);
3320 before
= emit_spill_move (true, new_reg
, src
);
3322 before
= get_insns ();
3324 lra_process_new_insns (curr_insn
, before
, NULL_RTX
,
3325 "Inserting the sec. move");
3327 lra_update_insn_regno_info (curr_insn
);
3332 lra_assert (goal_alt_number
>= 0);
3333 lra_set_used_insn_alternative (curr_insn
, goal_alt_number
);
3335 if (lra_dump_file
!= NULL
)
3339 fprintf (lra_dump_file
, " Choosing alt %d in insn %u:",
3340 goal_alt_number
, INSN_UID (curr_insn
));
3341 for (i
= 0; i
< n_operands
; i
++)
3343 p
= (curr_static_id
->operand_alternative
3344 [goal_alt_number
* n_operands
+ i
].constraint
);
3347 fprintf (lra_dump_file
, " (%d) ", i
);
3348 for (; *p
!= '\0' && *p
!= ',' && *p
!= '#'; p
++)
3349 fputc (*p
, lra_dump_file
);
3351 if (INSN_CODE (curr_insn
) >= 0
3352 && (p
= get_insn_name (INSN_CODE (curr_insn
))) != NULL
)
3353 fprintf (lra_dump_file
, " {%s}", p
);
3354 if (curr_id
->sp_offset
!= 0)
3355 fprintf (lra_dump_file
, " (sp_off=%" HOST_WIDE_INT_PRINT
"d)",
3356 curr_id
->sp_offset
);
3357 fprintf (lra_dump_file
, "\n");
3360 /* Right now, for any pair of operands I and J that are required to
3361 match, with J < I, goal_alt_matches[I] is J. Add I to
3362 goal_alt_matched[J]. */
3364 for (i
= 0; i
< n_operands
; i
++)
3365 if ((j
= goal_alt_matches
[i
]) >= 0)
3367 for (k
= 0; goal_alt_matched
[j
][k
] >= 0; k
++)
3369 /* We allow matching one output operand and several input
3372 || (curr_static_id
->operand
[j
].type
== OP_OUT
3373 && curr_static_id
->operand
[i
].type
== OP_IN
3374 && (curr_static_id
->operand
3375 [goal_alt_matched
[j
][0]].type
== OP_IN
)));
3376 goal_alt_matched
[j
][k
] = i
;
3377 goal_alt_matched
[j
][k
+ 1] = -1;
3380 for (i
= 0; i
< n_operands
; i
++)
3381 goal_alt_win
[i
] |= goal_alt_match_win
[i
];
3383 /* Any constants that aren't allowed and can't be reloaded into
3384 registers are here changed into memory references. */
3385 for (i
= 0; i
< n_operands
; i
++)
3386 if (goal_alt_win
[i
])
3389 enum reg_class new_class
;
3390 rtx reg
= *curr_id
->operand_loc
[i
];
3392 if (GET_CODE (reg
) == SUBREG
)
3393 reg
= SUBREG_REG (reg
);
3395 if (REG_P (reg
) && (regno
= REGNO (reg
)) >= FIRST_PSEUDO_REGISTER
)
3397 bool ok_p
= in_class_p (reg
, goal_alt
[i
], &new_class
);
3399 if (new_class
!= NO_REGS
&& get_reg_class (regno
) != new_class
)
3402 lra_change_class (regno
, new_class
, " Change to", true);
3408 const char *constraint
;
3410 rtx op
= *curr_id
->operand_loc
[i
];
3411 rtx subreg
= NULL_RTX
;
3412 enum machine_mode mode
= curr_operand_mode
[i
];
3414 if (GET_CODE (op
) == SUBREG
)
3417 op
= SUBREG_REG (op
);
3418 mode
= GET_MODE (op
);
3421 if (CONST_POOL_OK_P (mode
, op
)
3422 && ((targetm
.preferred_reload_class
3423 (op
, (enum reg_class
) goal_alt
[i
]) == NO_REGS
)
3424 || no_input_reloads_p
))
3426 rtx tem
= force_const_mem (mode
, op
);
3429 if (subreg
!= NULL_RTX
)
3430 tem
= gen_rtx_SUBREG (mode
, tem
, SUBREG_BYTE (subreg
));
3432 *curr_id
->operand_loc
[i
] = tem
;
3433 lra_update_dup (curr_id
, i
);
3434 process_address (i
, &before
, &after
);
3436 /* If the alternative accepts constant pool refs directly
3437 there will be no reload needed at all. */
3438 if (subreg
!= NULL_RTX
)
3440 /* Skip alternatives before the one requested. */
3441 constraint
= (curr_static_id
->operand_alternative
3442 [goal_alt_number
* n_operands
+ i
].constraint
);
3444 (c
= *constraint
) && c
!= ',' && c
!= '#';
3445 constraint
+= CONSTRAINT_LEN (c
, constraint
))
3447 if (c
== TARGET_MEM_CONSTRAINT
|| c
== 'o')
3449 #ifdef EXTRA_CONSTRAINT_STR
3450 if (EXTRA_MEMORY_CONSTRAINT (c
, constraint
)
3451 && EXTRA_CONSTRAINT_STR (tem
, c
, constraint
))
3455 if (c
== '\0' || c
== ',' || c
== '#')
3458 goal_alt_win
[i
] = true;
3462 for (i
= 0; i
< n_operands
; i
++)
3465 bool optional_p
= false;
3467 rtx op
= *curr_id
->operand_loc
[i
];
3469 if (goal_alt_win
[i
])
3471 if (goal_alt
[i
] == NO_REGS
3473 /* When we assign NO_REGS it means that we will not
3474 assign a hard register to the scratch pseudo by
3475 assigment pass and the scratch pseudo will be
3476 spilled. Spilled scratch pseudos are transformed
3477 back to scratches at the LRA end. */
3478 && lra_former_scratch_operand_p (curr_insn
, i
))
3480 int regno
= REGNO (op
);
3481 lra_change_class (regno
, NO_REGS
, " Change to", true);
3482 if (lra_get_regno_hard_regno (regno
) >= 0)
3483 /* We don't have to mark all insn affected by the
3484 spilled pseudo as there is only one such insn, the
3486 reg_renumber
[regno
] = -1;
3488 /* We can do an optional reload. If the pseudo got a hard
3489 reg, we might improve the code through inheritance. If
3490 it does not get a hard register we coalesce memory/memory
3491 moves later. Ignore move insns to avoid cycling. */
3493 && lra_undo_inheritance_iter
< LRA_MAX_INHERITANCE_PASSES
3494 && goal_alt
[i
] != NO_REGS
&& REG_P (op
)
3495 && (regno
= REGNO (op
)) >= FIRST_PSEUDO_REGISTER
3496 && regno
< new_regno_start
3497 && ! lra_former_scratch_p (regno
)
3498 && reg_renumber
[regno
] < 0
3499 && (curr_insn_set
== NULL_RTX
3500 || !((REG_P (SET_SRC (curr_insn_set
))
3501 || MEM_P (SET_SRC (curr_insn_set
))
3502 || GET_CODE (SET_SRC (curr_insn_set
)) == SUBREG
)
3503 && (REG_P (SET_DEST (curr_insn_set
))
3504 || MEM_P (SET_DEST (curr_insn_set
))
3505 || GET_CODE (SET_DEST (curr_insn_set
)) == SUBREG
))))
3511 /* Operands that match previous ones have already been handled. */
3512 if (goal_alt_matches
[i
] >= 0)
3515 /* We should not have an operand with a non-offsettable address
3516 appearing where an offsettable address will do. It also may
3517 be a case when the address should be special in other words
3518 not a general one (e.g. it needs no index reg). */
3519 if (goal_alt_matched
[i
][0] == -1 && goal_alt_offmemok
[i
] && MEM_P (op
))
3521 enum reg_class rclass
;
3522 rtx
*loc
= &XEXP (op
, 0);
3523 enum rtx_code code
= GET_CODE (*loc
);
3525 push_to_sequence (before
);
3526 rclass
= base_reg_class (GET_MODE (op
), MEM_ADDR_SPACE (op
),
3528 if (GET_RTX_CLASS (code
) == RTX_AUTOINC
)
3529 new_reg
= emit_inc (rclass
, *loc
, *loc
,
3530 /* This value does not matter for MODIFY. */
3531 GET_MODE_SIZE (GET_MODE (op
)));
3532 else if (get_reload_reg (OP_IN
, Pmode
, *loc
, rclass
,
3533 "offsetable address", &new_reg
))
3534 lra_emit_move (new_reg
, *loc
);
3535 before
= get_insns ();
3538 lra_update_dup (curr_id
, i
);
3540 else if (goal_alt_matched
[i
][0] == -1)
3542 enum machine_mode mode
;
3544 int hard_regno
, byte
;
3545 enum op_type type
= curr_static_id
->operand
[i
].type
;
3547 loc
= curr_id
->operand_loc
[i
];
3548 mode
= curr_operand_mode
[i
];
3549 if (GET_CODE (*loc
) == SUBREG
)
3551 reg
= SUBREG_REG (*loc
);
3552 byte
= SUBREG_BYTE (*loc
);
3554 /* Strict_low_part requires reload the register not
3555 the sub-register. */
3556 && (curr_static_id
->operand
[i
].strict_low
3557 || (GET_MODE_SIZE (mode
)
3558 <= GET_MODE_SIZE (GET_MODE (reg
))
3560 = get_try_hard_regno (REGNO (reg
))) >= 0
3561 && (simplify_subreg_regno
3563 GET_MODE (reg
), byte
, mode
) < 0)
3564 && (goal_alt
[i
] == NO_REGS
3565 || (simplify_subreg_regno
3566 (ira_class_hard_regs
[goal_alt
[i
]][0],
3567 GET_MODE (reg
), byte
, mode
) >= 0)))))
3569 loc
= &SUBREG_REG (*loc
);
3570 mode
= GET_MODE (*loc
);
3574 if (get_reload_reg (type
, mode
, old
, goal_alt
[i
], "", &new_reg
)
3577 push_to_sequence (before
);
3578 lra_emit_move (new_reg
, old
);
3579 before
= get_insns ();
3584 && find_reg_note (curr_insn
, REG_UNUSED
, old
) == NULL_RTX
)
3587 lra_emit_move (type
== OP_INOUT
? copy_rtx (old
) : old
, new_reg
);
3589 after
= get_insns ();
3593 for (j
= 0; j
< goal_alt_dont_inherit_ops_num
; j
++)
3594 if (goal_alt_dont_inherit_ops
[j
] == i
)
3596 lra_set_regno_unique_value (REGNO (new_reg
));
3599 lra_update_dup (curr_id
, i
);
3601 else if (curr_static_id
->operand
[i
].type
== OP_IN
3602 && (curr_static_id
->operand
[goal_alt_matched
[i
][0]].type
3605 /* generate reloads for input and matched outputs. */
3606 match_inputs
[0] = i
;
3607 match_inputs
[1] = -1;
3608 match_reload (goal_alt_matched
[i
][0], match_inputs
,
3609 goal_alt
[i
], &before
, &after
);
3611 else if (curr_static_id
->operand
[i
].type
== OP_OUT
3612 && (curr_static_id
->operand
[goal_alt_matched
[i
][0]].type
3614 /* Generate reloads for output and matched inputs. */
3615 match_reload (i
, goal_alt_matched
[i
], goal_alt
[i
], &before
, &after
);
3616 else if (curr_static_id
->operand
[i
].type
== OP_IN
3617 && (curr_static_id
->operand
[goal_alt_matched
[i
][0]].type
3620 /* Generate reloads for matched inputs. */
3621 match_inputs
[0] = i
;
3622 for (j
= 0; (k
= goal_alt_matched
[i
][j
]) >= 0; j
++)
3623 match_inputs
[j
+ 1] = k
;
3624 match_inputs
[j
+ 1] = -1;
3625 match_reload (-1, match_inputs
, goal_alt
[i
], &before
, &after
);
3628 /* We must generate code in any case when function
3629 process_alt_operands decides that it is possible. */
3633 lra_assert (REG_P (op
));
3635 op
= *curr_id
->operand_loc
[i
]; /* Substitution. */
3636 if (GET_CODE (op
) == SUBREG
)
3637 op
= SUBREG_REG (op
);
3638 gcc_assert (REG_P (op
) && (int) REGNO (op
) >= new_regno_start
);
3639 bitmap_set_bit (&lra_optional_reload_pseudos
, REGNO (op
));
3640 lra_reg_info
[REGNO (op
)].restore_regno
= regno
;
3641 if (lra_dump_file
!= NULL
)
3642 fprintf (lra_dump_file
,
3643 " Making reload reg %d for reg %d optional\n",
3647 if (before
!= NULL_RTX
|| after
!= NULL_RTX
3648 || max_regno_before
!= max_reg_num ())
3652 lra_update_operator_dups (curr_id
);
3653 /* Something changes -- process the insn. */
3654 lra_update_insn_regno_info (curr_insn
);
3656 lra_process_new_insns (curr_insn
, before
, after
, "Inserting insn reload");
3660 /* Return true if X is in LIST. */
3662 in_list_p (rtx x
, rtx list
)
3664 for (; list
!= NULL_RTX
; list
= XEXP (list
, 1))
3665 if (XEXP (list
, 0) == x
)
3670 /* Return true if X contains an allocatable hard register (if
3671 HARD_REG_P) or a (spilled if SPILLED_P) pseudo. */
3673 contains_reg_p (rtx x
, bool hard_reg_p
, bool spilled_p
)
3679 code
= GET_CODE (x
);
3682 int regno
= REGNO (x
);
3683 HARD_REG_SET alloc_regs
;
3687 if (regno
>= FIRST_PSEUDO_REGISTER
)
3688 regno
= lra_get_regno_hard_regno (regno
);
3691 COMPL_HARD_REG_SET (alloc_regs
, lra_no_alloc_regs
);
3692 return overlaps_hard_reg_set_p (alloc_regs
, GET_MODE (x
), regno
);
3696 if (regno
< FIRST_PSEUDO_REGISTER
)
3700 return lra_get_regno_hard_regno (regno
) < 0;
3703 fmt
= GET_RTX_FORMAT (code
);
3704 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
3708 if (contains_reg_p (XEXP (x
, i
), hard_reg_p
, spilled_p
))
3711 else if (fmt
[i
] == 'E')
3713 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3714 if (contains_reg_p (XVECEXP (x
, i
, j
), hard_reg_p
, spilled_p
))
3721 /* Process all regs in location *LOC and change them on equivalent
3722 substitution. Return true if any change was done. */
3724 loc_equivalence_change_p (rtx
*loc
)
3726 rtx subst
, reg
, x
= *loc
;
3727 bool result
= false;
3728 enum rtx_code code
= GET_CODE (x
);
3734 reg
= SUBREG_REG (x
);
3735 if ((subst
= get_equiv_with_elimination (reg
, curr_insn
)) != reg
3736 && GET_MODE (subst
) == VOIDmode
)
3738 /* We cannot reload debug location. Simplify subreg here
3739 while we know the inner mode. */
3740 *loc
= simplify_gen_subreg (GET_MODE (x
), subst
,
3741 GET_MODE (reg
), SUBREG_BYTE (x
));
3745 if (code
== REG
&& (subst
= get_equiv_with_elimination (x
, curr_insn
)) != x
)
3751 /* Scan all the operand sub-expressions. */
3752 fmt
= GET_RTX_FORMAT (code
);
3753 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
3756 result
= loc_equivalence_change_p (&XEXP (x
, i
)) || result
;
3757 else if (fmt
[i
] == 'E')
3758 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3760 = loc_equivalence_change_p (&XVECEXP (x
, i
, j
)) || result
;
3765 /* Similar to loc_equivalence_change_p, but for use as
3766 simplify_replace_fn_rtx callback. DATA is insn for which the
3767 elimination is done. If it null we don't do the elimination. */
3769 loc_equivalence_callback (rtx loc
, const_rtx
, void *data
)
3774 rtx subst
= (data
== NULL
3775 ? get_equiv (loc
) : get_equiv_with_elimination (loc
, (rtx
) data
));
3782 /* Maximum number of generated reload insns per an insn. It is for
3783 preventing this pass cycling in a bug case. */
3784 #define MAX_RELOAD_INSNS_NUMBER LRA_MAX_INSN_RELOADS
3786 /* The current iteration number of this LRA pass. */
3787 int lra_constraint_iter
;
3789 /* The current iteration number of this LRA pass after the last spill
3791 int lra_constraint_iter_after_spill
;
3793 /* True if we substituted equiv which needs checking register
3794 allocation correctness because the equivalent value contains
3795 allocatable hard registers or when we restore multi-register
3797 bool lra_risky_transformations_p
;
3799 /* Return true if REGNO is referenced in more than one block. */
3801 multi_block_pseudo_p (int regno
)
3803 basic_block bb
= NULL
;
3807 if (regno
< FIRST_PSEUDO_REGISTER
)
3810 EXECUTE_IF_SET_IN_BITMAP (&lra_reg_info
[regno
].insn_bitmap
, 0, uid
, bi
)
3812 bb
= BLOCK_FOR_INSN (lra_insn_recog_data
[uid
]->insn
);
3813 else if (BLOCK_FOR_INSN (lra_insn_recog_data
[uid
]->insn
) != bb
)
3818 /* Return true if LIST contains a deleted insn. */
3820 contains_deleted_insn_p (rtx list
)
3822 for (; list
!= NULL_RTX
; list
= XEXP (list
, 1))
3823 if (NOTE_P (XEXP (list
, 0))
3824 && NOTE_KIND (XEXP (list
, 0)) == NOTE_INSN_DELETED
)
3829 /* Return true if X contains a pseudo dying in INSN. */
3831 dead_pseudo_p (rtx x
, rtx insn
)
3838 return (insn
!= NULL_RTX
3839 && find_regno_note (insn
, REG_DEAD
, REGNO (x
)) != NULL_RTX
);
3840 code
= GET_CODE (x
);
3841 fmt
= GET_RTX_FORMAT (code
);
3842 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
3846 if (dead_pseudo_p (XEXP (x
, i
), insn
))
3849 else if (fmt
[i
] == 'E')
3851 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3852 if (dead_pseudo_p (XVECEXP (x
, i
, j
), insn
))
3859 /* Return true if INSN contains a dying pseudo in INSN right hand
3862 insn_rhs_dead_pseudo_p (rtx insn
)
3864 rtx set
= single_set (insn
);
3866 gcc_assert (set
!= NULL
);
3867 return dead_pseudo_p (SET_SRC (set
), insn
);
3870 /* Return true if any init insn of REGNO contains a dying pseudo in
3871 insn right hand side. */
3873 init_insn_rhs_dead_pseudo_p (int regno
)
3875 rtx insns
= ira_reg_equiv
[regno
].init_insns
;
3880 return insn_rhs_dead_pseudo_p (insns
);
3881 for (; insns
!= NULL_RTX
; insns
= XEXP (insns
, 1))
3882 if (insn_rhs_dead_pseudo_p (XEXP (insns
, 0)))
3887 /* Return TRUE if REGNO has a reverse equivalence. The equivalence is
3888 reverse only if we have one init insn with given REGNO as a
3891 reverse_equiv_p (int regno
)
3895 if ((insns
= ira_reg_equiv
[regno
].init_insns
) == NULL_RTX
)
3897 if (! INSN_P (XEXP (insns
, 0))
3898 || XEXP (insns
, 1) != NULL_RTX
)
3900 if ((set
= single_set (XEXP (insns
, 0))) == NULL_RTX
)
3902 return REG_P (SET_SRC (set
)) && (int) REGNO (SET_SRC (set
)) == regno
;
3905 /* Return TRUE if REGNO was reloaded in an equivalence init insn. We
3906 call this function only for non-reverse equivalence. */
3908 contains_reloaded_insn_p (int regno
)
3911 rtx list
= ira_reg_equiv
[regno
].init_insns
;
3913 for (; list
!= NULL_RTX
; list
= XEXP (list
, 1))
3914 if ((set
= single_set (XEXP (list
, 0))) == NULL_RTX
3915 || ! REG_P (SET_DEST (set
))
3916 || (int) REGNO (SET_DEST (set
)) != regno
)
3921 /* Entry function of LRA constraint pass. Return true if the
3922 constraint pass did change the code. */
3924 lra_constraints (bool first_p
)
3927 int i
, hard_regno
, new_insns_num
;
3928 unsigned int min_len
, new_min_len
, uid
;
3929 rtx set
, x
, reg
, dest_reg
;
3930 basic_block last_bb
;
3931 bitmap_head equiv_insn_bitmap
;
3934 lra_constraint_iter
++;
3935 if (lra_dump_file
!= NULL
)
3936 fprintf (lra_dump_file
, "\n********** Local #%d: **********\n\n",
3937 lra_constraint_iter
);
3938 lra_constraint_iter_after_spill
++;
3939 if (lra_constraint_iter_after_spill
> LRA_MAX_CONSTRAINT_ITERATION_NUMBER
)
3941 ("Maximum number of LRA constraint passes is achieved (%d)\n",
3942 LRA_MAX_CONSTRAINT_ITERATION_NUMBER
);
3944 lra_risky_transformations_p
= false;
3945 new_insn_uid_start
= get_max_uid ();
3946 new_regno_start
= first_p
? lra_constraint_new_regno_start
: max_reg_num ();
3947 /* Mark used hard regs for target stack size calulations. */
3948 for (i
= FIRST_PSEUDO_REGISTER
; i
< new_regno_start
; i
++)
3949 if (lra_reg_info
[i
].nrefs
!= 0
3950 && (hard_regno
= lra_get_regno_hard_regno (i
)) >= 0)
3954 nregs
= hard_regno_nregs
[hard_regno
][lra_reg_info
[i
].biggest_mode
];
3955 for (j
= 0; j
< nregs
; j
++)
3956 df_set_regs_ever_live (hard_regno
+ j
, true);
3958 /* Do elimination before the equivalence processing as we can spill
3959 some pseudos during elimination. */
3960 lra_eliminate (false, first_p
);
3961 bitmap_initialize (&equiv_insn_bitmap
, ®_obstack
);
3962 for (i
= FIRST_PSEUDO_REGISTER
; i
< new_regno_start
; i
++)
3963 if (lra_reg_info
[i
].nrefs
!= 0)
3965 ira_reg_equiv
[i
].profitable_p
= true;
3966 reg
= regno_reg_rtx
[i
];
3967 if (lra_get_regno_hard_regno (i
) < 0 && (x
= get_equiv (reg
)) != reg
)
3969 bool pseudo_p
= contains_reg_p (x
, false, false);
3971 /* After RTL transformation, we can not guarantee that
3972 pseudo in the substitution was not reloaded which might
3973 make equivalence invalid. For example, in reverse
3980 the memory address register was reloaded before the 2nd
3982 if ((! first_p
&& pseudo_p
)
3983 /* We don't use DF for compilation speed sake. So it
3984 is problematic to update live info when we use an
3985 equivalence containing pseudos in more than one
3987 || (pseudo_p
&& multi_block_pseudo_p (i
))
3988 /* If an init insn was deleted for some reason, cancel
3989 the equiv. We could update the equiv insns after
3990 transformations including an equiv insn deletion
3991 but it is not worthy as such cases are extremely
3993 || contains_deleted_insn_p (ira_reg_equiv
[i
].init_insns
)
3994 /* If it is not a reverse equivalence, we check that a
3995 pseudo in rhs of the init insn is not dying in the
3996 insn. Otherwise, the live info at the beginning of
3997 the corresponding BB might be wrong after we
3998 removed the insn. When the equiv can be a
3999 constant, the right hand side of the init insn can
4001 || (! reverse_equiv_p (i
)
4002 && (init_insn_rhs_dead_pseudo_p (i
)
4003 /* If we reloaded the pseudo in an equivalence
4004 init insn, we can not remove the equiv init
4005 insns and the init insns might write into
4006 const memory in this case. */
4007 || contains_reloaded_insn_p (i
)))
4008 /* Prevent access beyond equivalent memory for
4009 paradoxical subregs. */
4011 && (GET_MODE_SIZE (lra_reg_info
[i
].biggest_mode
)
4012 > GET_MODE_SIZE (GET_MODE (x
)))))
4013 ira_reg_equiv
[i
].defined_p
= false;
4014 if (contains_reg_p (x
, false, true))
4015 ira_reg_equiv
[i
].profitable_p
= false;
4016 if (get_equiv (reg
) != reg
)
4017 bitmap_ior_into (&equiv_insn_bitmap
, &lra_reg_info
[i
].insn_bitmap
);
4020 for (i
= FIRST_PSEUDO_REGISTER
; i
< new_regno_start
; i
++)
4022 /* We should add all insns containing pseudos which should be
4023 substituted by their equivalences. */
4024 EXECUTE_IF_SET_IN_BITMAP (&equiv_insn_bitmap
, 0, uid
, bi
)
4025 lra_push_insn_by_uid (uid
);
4026 min_len
= lra_insn_stack_length ();
4030 while ((new_min_len
= lra_insn_stack_length ()) != 0)
4032 curr_insn
= lra_pop_insn ();
4034 curr_bb
= BLOCK_FOR_INSN (curr_insn
);
4035 if (curr_bb
!= last_bb
)
4038 bb_reload_num
= lra_curr_reload_num
;
4040 if (min_len
> new_min_len
)
4042 min_len
= new_min_len
;
4045 if (new_insns_num
> MAX_RELOAD_INSNS_NUMBER
)
4047 ("Max. number of generated reload insns per insn is achieved (%d)\n",
4048 MAX_RELOAD_INSNS_NUMBER
);
4050 if (DEBUG_INSN_P (curr_insn
))
4052 /* We need to check equivalence in debug insn and change
4053 pseudo to the equivalent value if necessary. */
4054 curr_id
= lra_get_insn_recog_data (curr_insn
);
4055 if (bitmap_bit_p (&equiv_insn_bitmap
, INSN_UID (curr_insn
)))
4057 rtx old
= *curr_id
->operand_loc
[0];
4058 *curr_id
->operand_loc
[0]
4059 = simplify_replace_fn_rtx (old
, NULL_RTX
,
4060 loc_equivalence_callback
, curr_insn
);
4061 if (old
!= *curr_id
->operand_loc
[0])
4063 lra_update_insn_regno_info (curr_insn
);
4068 else if (INSN_P (curr_insn
))
4070 if ((set
= single_set (curr_insn
)) != NULL_RTX
)
4072 dest_reg
= SET_DEST (set
);
4073 /* The equivalence pseudo could be set up as SUBREG in a
4074 case when it is a call restore insn in a mode
4075 different from the pseudo mode. */
4076 if (GET_CODE (dest_reg
) == SUBREG
)
4077 dest_reg
= SUBREG_REG (dest_reg
);
4078 if ((REG_P (dest_reg
)
4079 && (x
= get_equiv (dest_reg
)) != dest_reg
4080 /* Remove insns which set up a pseudo whose value
4081 can not be changed. Such insns might be not in
4082 init_insns because we don't update equiv data
4083 during insn transformations.
4085 As an example, let suppose that a pseudo got
4086 hard register and on the 1st pass was not
4087 changed to equivalent constant. We generate an
4088 additional insn setting up the pseudo because of
4089 secondary memory movement. Then the pseudo is
4090 spilled and we use the equiv constant. In this
4091 case we should remove the additional insn and
4092 this insn is not init_insns list. */
4093 && (! MEM_P (x
) || MEM_READONLY_P (x
)
4094 /* Check that this is actually an insn setting
4095 up the equivalence. */
4096 || in_list_p (curr_insn
,
4098 [REGNO (dest_reg
)].init_insns
)))
4099 || (((x
= get_equiv (SET_SRC (set
))) != SET_SRC (set
))
4100 && in_list_p (curr_insn
,
4102 [REGNO (SET_SRC (set
))].init_insns
)))
4104 /* This is equiv init insn of pseudo which did not get a
4105 hard register -- remove the insn. */
4106 if (lra_dump_file
!= NULL
)
4108 fprintf (lra_dump_file
,
4109 " Removing equiv init insn %i (freq=%d)\n",
4110 INSN_UID (curr_insn
),
4111 REG_FREQ_FROM_BB (BLOCK_FOR_INSN (curr_insn
)));
4112 dump_insn_slim (lra_dump_file
, curr_insn
);
4114 if (contains_reg_p (x
, true, false))
4115 lra_risky_transformations_p
= true;
4116 lra_set_insn_deleted (curr_insn
);
4120 curr_id
= lra_get_insn_recog_data (curr_insn
);
4121 curr_static_id
= curr_id
->insn_static_data
;
4122 init_curr_insn_input_reloads ();
4123 init_curr_operand_mode ();
4124 if (curr_insn_transform ())
4126 /* Check non-transformed insns too for equiv change as USE
4127 or CLOBBER don't need reloads but can contain pseudos
4128 being changed on their equivalences. */
4129 else if (bitmap_bit_p (&equiv_insn_bitmap
, INSN_UID (curr_insn
))
4130 && loc_equivalence_change_p (&PATTERN (curr_insn
)))
4132 lra_update_insn_regno_info (curr_insn
);
4137 bitmap_clear (&equiv_insn_bitmap
);
4138 /* If we used a new hard regno, changed_p should be true because the
4139 hard reg is assigned to a new pseudo. */
4140 #ifdef ENABLE_CHECKING
4143 for (i
= FIRST_PSEUDO_REGISTER
; i
< new_regno_start
; i
++)
4144 if (lra_reg_info
[i
].nrefs
!= 0
4145 && (hard_regno
= lra_get_regno_hard_regno (i
)) >= 0)
4147 int j
, nregs
= hard_regno_nregs
[hard_regno
][PSEUDO_REGNO_MODE (i
)];
4149 for (j
= 0; j
< nregs
; j
++)
4150 lra_assert (df_regs_ever_live_p (hard_regno
+ j
));
4157 /* Initiate the LRA constraint pass. It is done once per
4160 lra_constraints_init (void)
4164 /* Finalize the LRA constraint pass. It is done once per
4167 lra_constraints_finish (void)
4173 /* This page contains code to do inheritance/split
4176 /* Number of reloads passed so far in current EBB. */
4177 static int reloads_num
;
4179 /* Number of calls passed so far in current EBB. */
4180 static int calls_num
;
4182 /* Current reload pseudo check for validity of elements in
4184 static int curr_usage_insns_check
;
4186 /* Info about last usage of registers in EBB to do inheritance/split
4187 transformation. Inheritance transformation is done from a spilled
4188 pseudo and split transformations from a hard register or a pseudo
4189 assigned to a hard register. */
4192 /* If the value is equal to CURR_USAGE_INSNS_CHECK, then the member
4193 value INSNS is valid. The insns is chain of optional debug insns
4194 and a finishing non-debug insn using the corresponding reg. The
4195 value is also used to mark the registers which are set up in the
4196 current insn. The negated insn uid is used for this. */
4198 /* Value of global reloads_num at the last insn in INSNS. */
4200 /* Value of global reloads_nums at the last insn in INSNS. */
4202 /* It can be true only for splitting. And it means that the restore
4203 insn should be put after insn given by the following member. */
4205 /* Next insns in the current EBB which use the original reg and the
4206 original reg value is not changed between the current insn and
4207 the next insns. In order words, e.g. for inheritance, if we need
4208 to use the original reg value again in the next insns we can try
4209 to use the value in a hard register from a reload insn of the
4214 /* Map: regno -> corresponding pseudo usage insns. */
4215 static struct usage_insns
*usage_insns
;
4218 setup_next_usage_insn (int regno
, rtx insn
, int reloads_num
, bool after_p
)
4220 usage_insns
[regno
].check
= curr_usage_insns_check
;
4221 usage_insns
[regno
].insns
= insn
;
4222 usage_insns
[regno
].reloads_num
= reloads_num
;
4223 usage_insns
[regno
].calls_num
= calls_num
;
4224 usage_insns
[regno
].after_p
= after_p
;
4227 /* The function is used to form list REGNO usages which consists of
4228 optional debug insns finished by a non-debug insn using REGNO.
4229 RELOADS_NUM is current number of reload insns processed so far. */
4231 add_next_usage_insn (int regno
, rtx insn
, int reloads_num
)
4233 rtx next_usage_insns
;
4235 if (usage_insns
[regno
].check
== curr_usage_insns_check
4236 && (next_usage_insns
= usage_insns
[regno
].insns
) != NULL_RTX
4237 && DEBUG_INSN_P (insn
))
4239 /* Check that we did not add the debug insn yet. */
4240 if (next_usage_insns
!= insn
4241 && (GET_CODE (next_usage_insns
) != INSN_LIST
4242 || XEXP (next_usage_insns
, 0) != insn
))
4243 usage_insns
[regno
].insns
= gen_rtx_INSN_LIST (VOIDmode
, insn
,
4246 else if (NONDEBUG_INSN_P (insn
))
4247 setup_next_usage_insn (regno
, insn
, reloads_num
, false);
4249 usage_insns
[regno
].check
= 0;
4252 /* Replace all references to register OLD_REGNO in *LOC with pseudo
4253 register NEW_REG. Return true if any change was made. */
4255 substitute_pseudo (rtx
*loc
, int old_regno
, rtx new_reg
)
4258 bool result
= false;
4266 code
= GET_CODE (x
);
4267 if (code
== REG
&& (int) REGNO (x
) == old_regno
)
4269 enum machine_mode mode
= GET_MODE (*loc
);
4270 enum machine_mode inner_mode
= GET_MODE (new_reg
);
4272 if (mode
!= inner_mode
)
4274 if (GET_MODE_SIZE (mode
) >= GET_MODE_SIZE (inner_mode
)
4275 || ! SCALAR_INT_MODE_P (inner_mode
))
4276 new_reg
= gen_rtx_SUBREG (mode
, new_reg
, 0);
4278 new_reg
= gen_lowpart_SUBREG (mode
, new_reg
);
4284 /* Scan all the operand sub-expressions. */
4285 fmt
= GET_RTX_FORMAT (code
);
4286 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
4290 if (substitute_pseudo (&XEXP (x
, i
), old_regno
, new_reg
))
4293 else if (fmt
[i
] == 'E')
4295 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
4296 if (substitute_pseudo (&XVECEXP (x
, i
, j
), old_regno
, new_reg
))
4303 /* Return first non-debug insn in list USAGE_INSNS. */
4305 skip_usage_debug_insns (rtx usage_insns
)
4309 /* Skip debug insns. */
4310 for (insn
= usage_insns
;
4311 insn
!= NULL_RTX
&& GET_CODE (insn
) == INSN_LIST
;
4312 insn
= XEXP (insn
, 1))
4317 /* Return true if we need secondary memory moves for insn in
4318 USAGE_INSNS after inserting inherited pseudo of class INHER_CL
4321 check_secondary_memory_needed_p (enum reg_class inher_cl ATTRIBUTE_UNUSED
,
4322 rtx usage_insns ATTRIBUTE_UNUSED
)
4324 #ifndef SECONDARY_MEMORY_NEEDED
4327 rtx insn
, set
, dest
;
4330 if (inher_cl
== ALL_REGS
4331 || (insn
= skip_usage_debug_insns (usage_insns
)) == NULL_RTX
)
4333 lra_assert (INSN_P (insn
));
4334 if ((set
= single_set (insn
)) == NULL_RTX
|| ! REG_P (SET_DEST (set
)))
4336 dest
= SET_DEST (set
);
4339 lra_assert (inher_cl
!= NO_REGS
);
4340 cl
= get_reg_class (REGNO (dest
));
4341 return (cl
!= NO_REGS
&& cl
!= ALL_REGS
4342 && SECONDARY_MEMORY_NEEDED (inher_cl
, cl
, GET_MODE (dest
)));
4346 /* Registers involved in inheritance/split in the current EBB
4347 (inheritance/split pseudos and original registers). */
4348 static bitmap_head check_only_regs
;
4350 /* Do inheritance transformations for insn INSN, which defines (if
4351 DEF_P) or uses ORIGINAL_REGNO. NEXT_USAGE_INSNS specifies which
4352 instruction in the EBB next uses ORIGINAL_REGNO; it has the same
4353 form as the "insns" field of usage_insns. Return true if we
4354 succeed in such transformation.
4356 The transformations look like:
4359 ... p <- i (new insn)
4361 <- ... p ... <- ... i ...
4363 ... i <- p (new insn)
4364 <- ... p ... <- ... i ...
4366 <- ... p ... <- ... i ...
4367 where p is a spilled original pseudo and i is a new inheritance pseudo.
4370 The inheritance pseudo has the smallest class of two classes CL and
4371 class of ORIGINAL REGNO. */
4373 inherit_reload_reg (bool def_p
, int original_regno
,
4374 enum reg_class cl
, rtx insn
, rtx next_usage_insns
)
4376 enum reg_class rclass
= lra_get_allocno_class (original_regno
);
4377 rtx original_reg
= regno_reg_rtx
[original_regno
];
4378 rtx new_reg
, new_insns
, usage_insn
;
4380 lra_assert (! usage_insns
[original_regno
].after_p
);
4381 if (lra_dump_file
!= NULL
)
4382 fprintf (lra_dump_file
,
4383 " <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<\n");
4384 if (! ira_reg_classes_intersect_p
[cl
][rclass
])
4386 if (lra_dump_file
!= NULL
)
4388 fprintf (lra_dump_file
,
4389 " Rejecting inheritance for %d "
4390 "because of disjoint classes %s and %s\n",
4391 original_regno
, reg_class_names
[cl
],
4392 reg_class_names
[rclass
]);
4393 fprintf (lra_dump_file
,
4394 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
4398 if ((ira_class_subset_p
[cl
][rclass
] && cl
!= rclass
)
4399 /* We don't use a subset of two classes because it can be
4400 NO_REGS. This transformation is still profitable in most
4401 cases even if the classes are not intersected as register
4402 move is probably cheaper than a memory load. */
4403 || ira_class_hard_regs_num
[cl
] < ira_class_hard_regs_num
[rclass
])
4405 if (lra_dump_file
!= NULL
)
4406 fprintf (lra_dump_file
, " Use smallest class of %s and %s\n",
4407 reg_class_names
[cl
], reg_class_names
[rclass
]);
4411 if (check_secondary_memory_needed_p (rclass
, next_usage_insns
))
4413 /* Reject inheritance resulting in secondary memory moves.
4414 Otherwise, there is a danger in LRA cycling. Also such
4415 transformation will be unprofitable. */
4416 if (lra_dump_file
!= NULL
)
4418 rtx insn
= skip_usage_debug_insns (next_usage_insns
);
4419 rtx set
= single_set (insn
);
4421 lra_assert (set
!= NULL_RTX
);
4423 rtx dest
= SET_DEST (set
);
4425 lra_assert (REG_P (dest
));
4426 fprintf (lra_dump_file
,
4427 " Rejecting inheritance for insn %d(%s)<-%d(%s) "
4428 "as secondary mem is needed\n",
4429 REGNO (dest
), reg_class_names
[get_reg_class (REGNO (dest
))],
4430 original_regno
, reg_class_names
[rclass
]);
4431 fprintf (lra_dump_file
,
4432 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
4436 new_reg
= lra_create_new_reg (GET_MODE (original_reg
), original_reg
,
4437 rclass
, "inheritance");
4440 emit_move_insn (original_reg
, new_reg
);
4442 emit_move_insn (new_reg
, original_reg
);
4443 new_insns
= get_insns ();
4445 if (NEXT_INSN (new_insns
) != NULL_RTX
)
4447 if (lra_dump_file
!= NULL
)
4449 fprintf (lra_dump_file
,
4450 " Rejecting inheritance %d->%d "
4451 "as it results in 2 or more insns:\n",
4452 original_regno
, REGNO (new_reg
));
4453 dump_rtl_slim (lra_dump_file
, new_insns
, NULL_RTX
, -1, 0);
4454 fprintf (lra_dump_file
,
4455 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
4459 substitute_pseudo (&insn
, original_regno
, new_reg
);
4460 lra_update_insn_regno_info (insn
);
4462 /* We now have a new usage insn for original regno. */
4463 setup_next_usage_insn (original_regno
, new_insns
, reloads_num
, false);
4464 if (lra_dump_file
!= NULL
)
4465 fprintf (lra_dump_file
, " Original reg change %d->%d (bb%d):\n",
4466 original_regno
, REGNO (new_reg
), BLOCK_FOR_INSN (insn
)->index
);
4467 lra_reg_info
[REGNO (new_reg
)].restore_regno
= original_regno
;
4468 bitmap_set_bit (&check_only_regs
, REGNO (new_reg
));
4469 bitmap_set_bit (&check_only_regs
, original_regno
);
4470 bitmap_set_bit (&lra_inheritance_pseudos
, REGNO (new_reg
));
4472 lra_process_new_insns (insn
, NULL_RTX
, new_insns
,
4473 "Add original<-inheritance");
4475 lra_process_new_insns (insn
, new_insns
, NULL_RTX
,
4476 "Add inheritance<-original");
4477 while (next_usage_insns
!= NULL_RTX
)
4479 if (GET_CODE (next_usage_insns
) != INSN_LIST
)
4481 usage_insn
= next_usage_insns
;
4482 lra_assert (NONDEBUG_INSN_P (usage_insn
));
4483 next_usage_insns
= NULL
;
4487 usage_insn
= XEXP (next_usage_insns
, 0);
4488 lra_assert (DEBUG_INSN_P (usage_insn
));
4489 next_usage_insns
= XEXP (next_usage_insns
, 1);
4491 substitute_pseudo (&usage_insn
, original_regno
, new_reg
);
4492 lra_update_insn_regno_info (usage_insn
);
4493 if (lra_dump_file
!= NULL
)
4495 fprintf (lra_dump_file
,
4496 " Inheritance reuse change %d->%d (bb%d):\n",
4497 original_regno
, REGNO (new_reg
),
4498 BLOCK_FOR_INSN (usage_insn
)->index
);
4499 dump_insn_slim (lra_dump_file
, usage_insn
);
4502 if (lra_dump_file
!= NULL
)
4503 fprintf (lra_dump_file
,
4504 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
4508 /* Return true if we need a caller save/restore for pseudo REGNO which
4509 was assigned to a hard register. */
4511 need_for_call_save_p (int regno
)
4513 lra_assert (regno
>= FIRST_PSEUDO_REGISTER
&& reg_renumber
[regno
] >= 0);
4514 return (usage_insns
[regno
].calls_num
< calls_num
4515 && (overlaps_hard_reg_set_p
4517 PSEUDO_REGNO_MODE (regno
), reg_renumber
[regno
])
4518 || HARD_REGNO_CALL_PART_CLOBBERED (reg_renumber
[regno
],
4519 PSEUDO_REGNO_MODE (regno
))));
4522 /* Global registers occurring in the current EBB. */
4523 static bitmap_head ebb_global_regs
;
4525 /* Return true if we need a split for hard register REGNO or pseudo
4526 REGNO which was assigned to a hard register.
4527 POTENTIAL_RELOAD_HARD_REGS contains hard registers which might be
4528 used for reloads since the EBB end. It is an approximation of the
4529 used hard registers in the split range. The exact value would
4530 require expensive calculations. If we were aggressive with
4531 splitting because of the approximation, the split pseudo will save
4532 the same hard register assignment and will be removed in the undo
4533 pass. We still need the approximation because too aggressive
4534 splitting would result in too inaccurate cost calculation in the
4535 assignment pass because of too many generated moves which will be
4536 probably removed in the undo pass. */
4538 need_for_split_p (HARD_REG_SET potential_reload_hard_regs
, int regno
)
4540 int hard_regno
= regno
< FIRST_PSEUDO_REGISTER
? regno
: reg_renumber
[regno
];
4542 lra_assert (hard_regno
>= 0);
4543 return ((TEST_HARD_REG_BIT (potential_reload_hard_regs
, hard_regno
)
4544 /* Don't split eliminable hard registers, otherwise we can
4545 split hard registers like hard frame pointer, which
4546 lives on BB start/end according to DF-infrastructure,
4547 when there is a pseudo assigned to the register and
4548 living in the same BB. */
4549 && (regno
>= FIRST_PSEUDO_REGISTER
4550 || ! TEST_HARD_REG_BIT (eliminable_regset
, hard_regno
))
4551 && ! TEST_HARD_REG_BIT (lra_no_alloc_regs
, hard_regno
)
4552 /* Don't split call clobbered hard regs living through
4553 calls, otherwise we might have a check problem in the
4554 assign sub-pass as in the most cases (exception is a
4555 situation when lra_risky_transformations_p value is
4556 true) the assign pass assumes that all pseudos living
4557 through calls are assigned to call saved hard regs. */
4558 && (regno
>= FIRST_PSEUDO_REGISTER
4559 || ! TEST_HARD_REG_BIT (call_used_reg_set
, regno
)
4560 || usage_insns
[regno
].calls_num
== calls_num
)
4561 /* We need at least 2 reloads to make pseudo splitting
4562 profitable. We should provide hard regno splitting in
4563 any case to solve 1st insn scheduling problem when
4564 moving hard register definition up might result in
4565 impossibility to find hard register for reload pseudo of
4566 small register class. */
4567 && (usage_insns
[regno
].reloads_num
4568 + (regno
< FIRST_PSEUDO_REGISTER
? 0 : 2) < reloads_num
)
4569 && (regno
< FIRST_PSEUDO_REGISTER
4570 /* For short living pseudos, spilling + inheritance can
4571 be considered a substitution for splitting.
4572 Therefore we do not splitting for local pseudos. It
4573 decreases also aggressiveness of splitting. The
4574 minimal number of references is chosen taking into
4575 account that for 2 references splitting has no sense
4576 as we can just spill the pseudo. */
4577 || (regno
>= FIRST_PSEUDO_REGISTER
4578 && lra_reg_info
[regno
].nrefs
> 3
4579 && bitmap_bit_p (&ebb_global_regs
, regno
))))
4580 || (regno
>= FIRST_PSEUDO_REGISTER
&& need_for_call_save_p (regno
)));
4583 /* Return class for the split pseudo created from original pseudo with
4584 ALLOCNO_CLASS and MODE which got a hard register HARD_REGNO. We
4585 choose subclass of ALLOCNO_CLASS which contains HARD_REGNO and
4586 results in no secondary memory movements. */
4587 static enum reg_class
4588 choose_split_class (enum reg_class allocno_class
,
4589 int hard_regno ATTRIBUTE_UNUSED
,
4590 enum machine_mode mode ATTRIBUTE_UNUSED
)
4592 #ifndef SECONDARY_MEMORY_NEEDED
4593 return allocno_class
;
4596 enum reg_class cl
, best_cl
= NO_REGS
;
4597 enum reg_class hard_reg_class ATTRIBUTE_UNUSED
4598 = REGNO_REG_CLASS (hard_regno
);
4600 if (! SECONDARY_MEMORY_NEEDED (allocno_class
, allocno_class
, mode
)
4601 && TEST_HARD_REG_BIT (reg_class_contents
[allocno_class
], hard_regno
))
4602 return allocno_class
;
4604 (cl
= reg_class_subclasses
[allocno_class
][i
]) != LIM_REG_CLASSES
;
4606 if (! SECONDARY_MEMORY_NEEDED (cl
, hard_reg_class
, mode
)
4607 && ! SECONDARY_MEMORY_NEEDED (hard_reg_class
, cl
, mode
)
4608 && TEST_HARD_REG_BIT (reg_class_contents
[cl
], hard_regno
)
4609 && (best_cl
== NO_REGS
4610 || ira_class_hard_regs_num
[best_cl
] < ira_class_hard_regs_num
[cl
]))
4616 /* Do split transformations for insn INSN, which defines or uses
4617 ORIGINAL_REGNO. NEXT_USAGE_INSNS specifies which instruction in
4618 the EBB next uses ORIGINAL_REGNO; it has the same form as the
4619 "insns" field of usage_insns.
4621 The transformations look like:
4624 ... s <- p (new insn -- save)
4626 ... p <- s (new insn -- restore)
4627 <- ... p ... <- ... p ...
4629 <- ... p ... <- ... p ...
4630 ... s <- p (new insn -- save)
4632 ... p <- s (new insn -- restore)
4633 <- ... p ... <- ... p ...
4635 where p is an original pseudo got a hard register or a hard
4636 register and s is a new split pseudo. The save is put before INSN
4637 if BEFORE_P is true. Return true if we succeed in such
4640 split_reg (bool before_p
, int original_regno
, rtx insn
, rtx next_usage_insns
)
4642 enum reg_class rclass
;
4644 int hard_regno
, nregs
;
4645 rtx new_reg
, save
, restore
, usage_insn
;
4649 if (original_regno
< FIRST_PSEUDO_REGISTER
)
4651 rclass
= ira_allocno_class_translate
[REGNO_REG_CLASS (original_regno
)];
4652 hard_regno
= original_regno
;
4653 call_save_p
= false;
4658 hard_regno
= reg_renumber
[original_regno
];
4659 nregs
= hard_regno_nregs
[hard_regno
][PSEUDO_REGNO_MODE (original_regno
)];
4660 rclass
= lra_get_allocno_class (original_regno
);
4661 original_reg
= regno_reg_rtx
[original_regno
];
4662 call_save_p
= need_for_call_save_p (original_regno
);
4664 original_reg
= regno_reg_rtx
[original_regno
];
4665 lra_assert (hard_regno
>= 0);
4666 if (lra_dump_file
!= NULL
)
4667 fprintf (lra_dump_file
,
4668 " ((((((((((((((((((((((((((((((((((((((((((((((((\n");
4671 enum machine_mode mode
= GET_MODE (original_reg
);
4673 mode
= HARD_REGNO_CALLER_SAVE_MODE (hard_regno
,
4674 hard_regno_nregs
[hard_regno
][mode
],
4676 new_reg
= lra_create_new_reg (mode
, NULL_RTX
, NO_REGS
, "save");
4680 rclass
= choose_split_class (rclass
, hard_regno
,
4681 GET_MODE (original_reg
));
4682 if (rclass
== NO_REGS
)
4684 if (lra_dump_file
!= NULL
)
4686 fprintf (lra_dump_file
,
4687 " Rejecting split of %d(%s): "
4688 "no good reg class for %d(%s)\n",
4690 reg_class_names
[lra_get_allocno_class (original_regno
)],
4692 reg_class_names
[REGNO_REG_CLASS (hard_regno
)]);
4695 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
4699 new_reg
= lra_create_new_reg (GET_MODE (original_reg
), original_reg
,
4701 reg_renumber
[REGNO (new_reg
)] = hard_regno
;
4703 save
= emit_spill_move (true, new_reg
, original_reg
);
4704 if (NEXT_INSN (save
) != NULL_RTX
)
4706 lra_assert (! call_save_p
);
4707 if (lra_dump_file
!= NULL
)
4711 " Rejecting split %d->%d resulting in > 2 %s save insns:\n",
4712 original_regno
, REGNO (new_reg
), call_save_p
? "call" : "");
4713 dump_rtl_slim (lra_dump_file
, save
, NULL_RTX
, -1, 0);
4714 fprintf (lra_dump_file
,
4715 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
4719 restore
= emit_spill_move (false, new_reg
, original_reg
);
4720 if (NEXT_INSN (restore
) != NULL_RTX
)
4722 lra_assert (! call_save_p
);
4723 if (lra_dump_file
!= NULL
)
4725 fprintf (lra_dump_file
,
4726 " Rejecting split %d->%d "
4727 "resulting in > 2 %s restore insns:\n",
4728 original_regno
, REGNO (new_reg
), call_save_p
? "call" : "");
4729 dump_rtl_slim (lra_dump_file
, restore
, NULL_RTX
, -1, 0);
4730 fprintf (lra_dump_file
,
4731 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
4735 after_p
= usage_insns
[original_regno
].after_p
;
4736 lra_reg_info
[REGNO (new_reg
)].restore_regno
= original_regno
;
4737 bitmap_set_bit (&check_only_regs
, REGNO (new_reg
));
4738 bitmap_set_bit (&check_only_regs
, original_regno
);
4739 bitmap_set_bit (&lra_split_regs
, REGNO (new_reg
));
4742 if (GET_CODE (next_usage_insns
) != INSN_LIST
)
4744 usage_insn
= next_usage_insns
;
4747 usage_insn
= XEXP (next_usage_insns
, 0);
4748 lra_assert (DEBUG_INSN_P (usage_insn
));
4749 next_usage_insns
= XEXP (next_usage_insns
, 1);
4750 substitute_pseudo (&usage_insn
, original_regno
, new_reg
);
4751 lra_update_insn_regno_info (usage_insn
);
4752 if (lra_dump_file
!= NULL
)
4754 fprintf (lra_dump_file
, " Split reuse change %d->%d:\n",
4755 original_regno
, REGNO (new_reg
));
4756 dump_insn_slim (lra_dump_file
, usage_insn
);
4759 lra_assert (NOTE_P (usage_insn
) || NONDEBUG_INSN_P (usage_insn
));
4760 lra_assert (usage_insn
!= insn
|| (after_p
&& before_p
));
4761 lra_process_new_insns (usage_insn
, after_p
? NULL_RTX
: restore
,
4762 after_p
? restore
: NULL_RTX
,
4764 ? "Add reg<-save" : "Add reg<-split");
4765 lra_process_new_insns (insn
, before_p
? save
: NULL_RTX
,
4766 before_p
? NULL_RTX
: save
,
4768 ? "Add save<-reg" : "Add split<-reg");
4770 /* If we are trying to split multi-register. We should check
4771 conflicts on the next assignment sub-pass. IRA can allocate on
4772 sub-register levels, LRA do this on pseudos level right now and
4773 this discrepancy may create allocation conflicts after
4775 lra_risky_transformations_p
= true;
4776 if (lra_dump_file
!= NULL
)
4777 fprintf (lra_dump_file
,
4778 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
4782 /* Recognize that we need a split transformation for insn INSN, which
4783 defines or uses REGNO in its insn biggest MODE (we use it only if
4784 REGNO is a hard register). POTENTIAL_RELOAD_HARD_REGS contains
4785 hard registers which might be used for reloads since the EBB end.
4786 Put the save before INSN if BEFORE_P is true. MAX_UID is maximla
4787 uid before starting INSN processing. Return true if we succeed in
4788 such transformation. */
4790 split_if_necessary (int regno
, enum machine_mode mode
,
4791 HARD_REG_SET potential_reload_hard_regs
,
4792 bool before_p
, rtx insn
, int max_uid
)
4796 rtx next_usage_insns
;
4798 if (regno
< FIRST_PSEUDO_REGISTER
)
4799 nregs
= hard_regno_nregs
[regno
][mode
];
4800 for (i
= 0; i
< nregs
; i
++)
4801 if (usage_insns
[regno
+ i
].check
== curr_usage_insns_check
4802 && (next_usage_insns
= usage_insns
[regno
+ i
].insns
) != NULL_RTX
4803 /* To avoid processing the register twice or more. */
4804 && ((GET_CODE (next_usage_insns
) != INSN_LIST
4805 && INSN_UID (next_usage_insns
) < max_uid
)
4806 || (GET_CODE (next_usage_insns
) == INSN_LIST
4807 && (INSN_UID (XEXP (next_usage_insns
, 0)) < max_uid
)))
4808 && need_for_split_p (potential_reload_hard_regs
, regno
+ i
)
4809 && split_reg (before_p
, regno
+ i
, insn
, next_usage_insns
))
4814 /* Check only registers living at the current program point in the
4816 static bitmap_head live_regs
;
4818 /* Update live info in EBB given by its HEAD and TAIL insns after
4819 inheritance/split transformation. The function removes dead moves
4822 update_ebb_live_info (rtx head
, rtx tail
)
4829 basic_block last_bb
, prev_bb
, curr_bb
;
4831 struct lra_insn_reg
*reg
;
4835 last_bb
= BLOCK_FOR_INSN (tail
);
4837 for (curr_insn
= tail
;
4838 curr_insn
!= PREV_INSN (head
);
4839 curr_insn
= prev_insn
)
4841 prev_insn
= PREV_INSN (curr_insn
);
4842 /* We need to process empty blocks too. They contain
4843 NOTE_INSN_BASIC_BLOCK referring for the basic block. */
4844 if (NOTE_P (curr_insn
) && NOTE_KIND (curr_insn
) != NOTE_INSN_BASIC_BLOCK
)
4846 curr_bb
= BLOCK_FOR_INSN (curr_insn
);
4847 if (curr_bb
!= prev_bb
)
4849 if (prev_bb
!= NULL
)
4851 /* Update df_get_live_in (prev_bb): */
4852 EXECUTE_IF_SET_IN_BITMAP (&check_only_regs
, 0, j
, bi
)
4853 if (bitmap_bit_p (&live_regs
, j
))
4854 bitmap_set_bit (df_get_live_in (prev_bb
), j
);
4856 bitmap_clear_bit (df_get_live_in (prev_bb
), j
);
4858 if (curr_bb
!= last_bb
)
4860 /* Update df_get_live_out (curr_bb): */
4861 EXECUTE_IF_SET_IN_BITMAP (&check_only_regs
, 0, j
, bi
)
4863 live_p
= bitmap_bit_p (&live_regs
, j
);
4865 FOR_EACH_EDGE (e
, ei
, curr_bb
->succs
)
4866 if (bitmap_bit_p (df_get_live_in (e
->dest
), j
))
4872 bitmap_set_bit (df_get_live_out (curr_bb
), j
);
4874 bitmap_clear_bit (df_get_live_out (curr_bb
), j
);
4878 bitmap_and (&live_regs
, &check_only_regs
, df_get_live_out (curr_bb
));
4880 if (! NONDEBUG_INSN_P (curr_insn
))
4882 curr_id
= lra_get_insn_recog_data (curr_insn
);
4884 if ((set
= single_set (curr_insn
)) != NULL_RTX
&& REG_P (SET_DEST (set
))
4885 && (regno
= REGNO (SET_DEST (set
))) >= FIRST_PSEUDO_REGISTER
4886 && bitmap_bit_p (&check_only_regs
, regno
)
4887 && ! bitmap_bit_p (&live_regs
, regno
))
4889 /* See which defined values die here. */
4890 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
4891 if (reg
->type
== OP_OUT
&& ! reg
->subreg_p
)
4892 bitmap_clear_bit (&live_regs
, reg
->regno
);
4893 /* Mark each used value as live. */
4894 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
4895 if (reg
->type
!= OP_OUT
4896 && bitmap_bit_p (&check_only_regs
, reg
->regno
))
4897 bitmap_set_bit (&live_regs
, reg
->regno
);
4898 /* It is quite important to remove dead move insns because it
4899 means removing dead store. We don't need to process them for
4903 if (lra_dump_file
!= NULL
)
4905 fprintf (lra_dump_file
, " Removing dead insn:\n ");
4906 dump_insn_slim (lra_dump_file
, curr_insn
);
4908 lra_set_insn_deleted (curr_insn
);
4913 /* The structure describes info to do an inheritance for the current
4914 insn. We need to collect such info first before doing the
4915 transformations because the transformations change the insn
4916 internal representation. */
4919 /* Original regno. */
4921 /* Subsequent insns which can inherit original reg value. */
4925 /* Array containing all info for doing inheritance from the current
4927 static struct to_inherit to_inherit
[LRA_MAX_INSN_RELOADS
];
4929 /* Number elements in the previous array. */
4930 static int to_inherit_num
;
4932 /* Add inheritance info REGNO and INSNS. Their meaning is described in
4933 structure to_inherit. */
4935 add_to_inherit (int regno
, rtx insns
)
4939 for (i
= 0; i
< to_inherit_num
; i
++)
4940 if (to_inherit
[i
].regno
== regno
)
4942 lra_assert (to_inherit_num
< LRA_MAX_INSN_RELOADS
);
4943 to_inherit
[to_inherit_num
].regno
= regno
;
4944 to_inherit
[to_inherit_num
++].insns
= insns
;
4947 /* Return the last non-debug insn in basic block BB, or the block begin
4950 get_last_insertion_point (basic_block bb
)
4954 FOR_BB_INSNS_REVERSE (bb
, insn
)
4955 if (NONDEBUG_INSN_P (insn
) || NOTE_INSN_BASIC_BLOCK_P (insn
))
4960 /* Set up RES by registers living on edges FROM except the edge (FROM,
4961 TO) or by registers set up in a jump insn in BB FROM. */
4963 get_live_on_other_edges (basic_block from
, basic_block to
, bitmap res
)
4966 struct lra_insn_reg
*reg
;
4970 lra_assert (to
!= NULL
);
4972 FOR_EACH_EDGE (e
, ei
, from
->succs
)
4974 bitmap_ior_into (res
, df_get_live_in (e
->dest
));
4975 last
= get_last_insertion_point (from
);
4976 if (! JUMP_P (last
))
4978 curr_id
= lra_get_insn_recog_data (last
);
4979 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
4980 if (reg
->type
!= OP_IN
)
4981 bitmap_set_bit (res
, reg
->regno
);
4984 /* Used as a temporary results of some bitmap calculations. */
4985 static bitmap_head temp_bitmap
;
4987 /* Do inheritance/split transformations in EBB starting with HEAD and
4988 finishing on TAIL. We process EBB insns in the reverse order.
4989 Return true if we did any inheritance/split transformation in the
4992 We should avoid excessive splitting which results in worse code
4993 because of inaccurate cost calculations for spilling new split
4994 pseudos in such case. To achieve this we do splitting only if
4995 register pressure is high in given basic block and there are reload
4996 pseudos requiring hard registers. We could do more register
4997 pressure calculations at any given program point to avoid necessary
4998 splitting even more but it is to expensive and the current approach
4999 works well enough. */
5001 inherit_in_ebb (rtx head
, rtx tail
)
5003 int i
, src_regno
, dst_regno
, nregs
;
5004 bool change_p
, succ_p
;
5005 rtx prev_insn
, next_usage_insns
, set
, last_insn
;
5007 struct lra_insn_reg
*reg
;
5008 basic_block last_processed_bb
, curr_bb
= NULL
;
5009 HARD_REG_SET potential_reload_hard_regs
, live_hard_regs
;
5013 bool head_p
, after_p
;
5016 curr_usage_insns_check
++;
5017 reloads_num
= calls_num
= 0;
5018 bitmap_clear (&check_only_regs
);
5019 last_processed_bb
= NULL
;
5020 CLEAR_HARD_REG_SET (potential_reload_hard_regs
);
5021 CLEAR_HARD_REG_SET (live_hard_regs
);
5022 /* We don't process new insns generated in the loop. */
5023 for (curr_insn
= tail
; curr_insn
!= PREV_INSN (head
); curr_insn
= prev_insn
)
5025 prev_insn
= PREV_INSN (curr_insn
);
5026 if (BLOCK_FOR_INSN (curr_insn
) != NULL
)
5027 curr_bb
= BLOCK_FOR_INSN (curr_insn
);
5028 if (last_processed_bb
!= curr_bb
)
5030 /* We are at the end of BB. Add qualified living
5031 pseudos for potential splitting. */
5032 to_process
= df_get_live_out (curr_bb
);
5033 if (last_processed_bb
!= NULL
)
5035 /* We are somewhere in the middle of EBB. */
5036 get_live_on_other_edges (curr_bb
, last_processed_bb
,
5038 to_process
= &temp_bitmap
;
5040 last_processed_bb
= curr_bb
;
5041 last_insn
= get_last_insertion_point (curr_bb
);
5042 after_p
= (! JUMP_P (last_insn
)
5043 && (! CALL_P (last_insn
)
5044 || (find_reg_note (last_insn
,
5045 REG_NORETURN
, NULL_RTX
) == NULL_RTX
5046 && ! SIBLING_CALL_P (last_insn
))));
5047 REG_SET_TO_HARD_REG_SET (live_hard_regs
, df_get_live_out (curr_bb
));
5048 IOR_HARD_REG_SET (live_hard_regs
, eliminable_regset
);
5049 IOR_HARD_REG_SET (live_hard_regs
, lra_no_alloc_regs
);
5050 CLEAR_HARD_REG_SET (potential_reload_hard_regs
);
5051 EXECUTE_IF_SET_IN_BITMAP (to_process
, 0, j
, bi
)
5053 if ((int) j
>= lra_constraint_new_regno_start
)
5055 if (j
< FIRST_PSEUDO_REGISTER
|| reg_renumber
[j
] >= 0)
5057 if (j
< FIRST_PSEUDO_REGISTER
)
5058 SET_HARD_REG_BIT (live_hard_regs
, j
);
5060 add_to_hard_reg_set (&live_hard_regs
,
5061 PSEUDO_REGNO_MODE (j
),
5063 setup_next_usage_insn (j
, last_insn
, reloads_num
, after_p
);
5067 src_regno
= dst_regno
= -1;
5068 if (NONDEBUG_INSN_P (curr_insn
)
5069 && (set
= single_set (curr_insn
)) != NULL_RTX
5070 && REG_P (SET_DEST (set
)) && REG_P (SET_SRC (set
)))
5072 src_regno
= REGNO (SET_SRC (set
));
5073 dst_regno
= REGNO (SET_DEST (set
));
5075 if (src_regno
< lra_constraint_new_regno_start
5076 && src_regno
>= FIRST_PSEUDO_REGISTER
5077 && reg_renumber
[src_regno
] < 0
5078 && dst_regno
>= lra_constraint_new_regno_start
5079 && (cl
= lra_get_allocno_class (dst_regno
)) != NO_REGS
)
5081 /* 'reload_pseudo <- original_pseudo'. */
5084 if (usage_insns
[src_regno
].check
== curr_usage_insns_check
5085 && (next_usage_insns
= usage_insns
[src_regno
].insns
) != NULL_RTX
)
5086 succ_p
= inherit_reload_reg (false, src_regno
, cl
,
5087 curr_insn
, next_usage_insns
);
5091 setup_next_usage_insn (src_regno
, curr_insn
, reloads_num
, false);
5092 if (hard_reg_set_subset_p (reg_class_contents
[cl
], live_hard_regs
))
5093 IOR_HARD_REG_SET (potential_reload_hard_regs
,
5094 reg_class_contents
[cl
]);
5096 else if (src_regno
>= lra_constraint_new_regno_start
5097 && dst_regno
< lra_constraint_new_regno_start
5098 && dst_regno
>= FIRST_PSEUDO_REGISTER
5099 && reg_renumber
[dst_regno
] < 0
5100 && (cl
= lra_get_allocno_class (src_regno
)) != NO_REGS
5101 && usage_insns
[dst_regno
].check
== curr_usage_insns_check
5102 && (next_usage_insns
5103 = usage_insns
[dst_regno
].insns
) != NULL_RTX
)
5106 /* 'original_pseudo <- reload_pseudo'. */
5107 if (! JUMP_P (curr_insn
)
5108 && inherit_reload_reg (true, dst_regno
, cl
,
5109 curr_insn
, next_usage_insns
))
5112 usage_insns
[dst_regno
].check
= 0;
5113 if (hard_reg_set_subset_p (reg_class_contents
[cl
], live_hard_regs
))
5114 IOR_HARD_REG_SET (potential_reload_hard_regs
,
5115 reg_class_contents
[cl
]);
5117 else if (INSN_P (curr_insn
))
5120 int max_uid
= get_max_uid ();
5122 curr_id
= lra_get_insn_recog_data (curr_insn
);
5123 curr_static_id
= curr_id
->insn_static_data
;
5125 /* Process insn definitions. */
5126 for (iter
= 0; iter
< 2; iter
++)
5127 for (reg
= iter
== 0 ? curr_id
->regs
: curr_static_id
->hard_regs
;
5130 if (reg
->type
!= OP_IN
5131 && (dst_regno
= reg
->regno
) < lra_constraint_new_regno_start
)
5133 if (dst_regno
>= FIRST_PSEUDO_REGISTER
&& reg
->type
== OP_OUT
5134 && reg_renumber
[dst_regno
] < 0 && ! reg
->subreg_p
5135 && usage_insns
[dst_regno
].check
== curr_usage_insns_check
5136 && (next_usage_insns
5137 = usage_insns
[dst_regno
].insns
) != NULL_RTX
)
5139 struct lra_insn_reg
*r
;
5141 for (r
= curr_id
->regs
; r
!= NULL
; r
= r
->next
)
5142 if (r
->type
!= OP_OUT
&& r
->regno
== dst_regno
)
5144 /* Don't do inheritance if the pseudo is also
5145 used in the insn. */
5147 /* We can not do inheritance right now
5148 because the current insn reg info (chain
5149 regs) can change after that. */
5150 add_to_inherit (dst_regno
, next_usage_insns
);
5152 /* We can not process one reg twice here because of
5153 usage_insns invalidation. */
5154 if ((dst_regno
< FIRST_PSEUDO_REGISTER
5155 || reg_renumber
[dst_regno
] >= 0)
5156 && ! reg
->subreg_p
&& reg
->type
!= OP_IN
)
5160 if (split_if_necessary (dst_regno
, reg
->biggest_mode
,
5161 potential_reload_hard_regs
,
5162 false, curr_insn
, max_uid
))
5164 CLEAR_HARD_REG_SET (s
);
5165 if (dst_regno
< FIRST_PSEUDO_REGISTER
)
5166 add_to_hard_reg_set (&s
, reg
->biggest_mode
, dst_regno
);
5168 add_to_hard_reg_set (&s
, PSEUDO_REGNO_MODE (dst_regno
),
5169 reg_renumber
[dst_regno
]);
5170 AND_COMPL_HARD_REG_SET (live_hard_regs
, s
);
5172 /* We should invalidate potential inheritance or
5173 splitting for the current insn usages to the next
5174 usage insns (see code below) as the output pseudo
5176 if ((dst_regno
>= FIRST_PSEUDO_REGISTER
5177 && reg_renumber
[dst_regno
] < 0)
5178 || (reg
->type
== OP_OUT
&& ! reg
->subreg_p
5179 && (dst_regno
< FIRST_PSEUDO_REGISTER
5180 || reg_renumber
[dst_regno
] >= 0)))
5182 /* Invalidate and mark definitions. */
5183 if (dst_regno
>= FIRST_PSEUDO_REGISTER
)
5184 usage_insns
[dst_regno
].check
= -(int) INSN_UID (curr_insn
);
5187 nregs
= hard_regno_nregs
[dst_regno
][reg
->biggest_mode
];
5188 for (i
= 0; i
< nregs
; i
++)
5189 usage_insns
[dst_regno
+ i
].check
5190 = -(int) INSN_UID (curr_insn
);
5194 if (! JUMP_P (curr_insn
))
5195 for (i
= 0; i
< to_inherit_num
; i
++)
5196 if (inherit_reload_reg (true, to_inherit
[i
].regno
,
5197 ALL_REGS
, curr_insn
,
5198 to_inherit
[i
].insns
))
5200 if (CALL_P (curr_insn
))
5202 rtx cheap
, pat
, dest
, restore
;
5203 int regno
, hard_regno
;
5206 if ((cheap
= find_reg_note (curr_insn
,
5207 REG_RETURNED
, NULL_RTX
)) != NULL_RTX
5208 && ((cheap
= XEXP (cheap
, 0)), true)
5209 && (regno
= REGNO (cheap
)) >= FIRST_PSEUDO_REGISTER
5210 && (hard_regno
= reg_renumber
[regno
]) >= 0
5211 /* If there are pending saves/restores, the
5212 optimization is not worth. */
5213 && usage_insns
[regno
].calls_num
== calls_num
- 1
5214 && TEST_HARD_REG_BIT (call_used_reg_set
, hard_regno
))
5216 /* Restore the pseudo from the call result as
5217 REG_RETURNED note says that the pseudo value is
5218 in the call result and the pseudo is an argument
5220 pat
= PATTERN (curr_insn
);
5221 if (GET_CODE (pat
) == PARALLEL
)
5222 pat
= XVECEXP (pat
, 0, 0);
5223 dest
= SET_DEST (pat
);
5225 emit_move_insn (cheap
, copy_rtx (dest
));
5226 restore
= get_insns ();
5228 lra_process_new_insns (curr_insn
, NULL
, restore
,
5229 "Inserting call parameter restore");
5230 /* We don't need to save/restore of the pseudo from
5232 usage_insns
[regno
].calls_num
= calls_num
;
5233 bitmap_set_bit (&check_only_regs
, regno
);
5237 /* Process insn usages. */
5238 for (iter
= 0; iter
< 2; iter
++)
5239 for (reg
= iter
== 0 ? curr_id
->regs
: curr_static_id
->hard_regs
;
5242 if ((reg
->type
!= OP_OUT
5243 || (reg
->type
== OP_OUT
&& reg
->subreg_p
))
5244 && (src_regno
= reg
->regno
) < lra_constraint_new_regno_start
)
5246 if (src_regno
>= FIRST_PSEUDO_REGISTER
5247 && reg_renumber
[src_regno
] < 0 && reg
->type
== OP_IN
)
5249 if (usage_insns
[src_regno
].check
== curr_usage_insns_check
5250 && (next_usage_insns
5251 = usage_insns
[src_regno
].insns
) != NULL_RTX
5252 && NONDEBUG_INSN_P (curr_insn
))
5253 add_to_inherit (src_regno
, next_usage_insns
);
5254 else if (usage_insns
[src_regno
].check
5255 != -(int) INSN_UID (curr_insn
))
5256 /* Add usages but only if the reg is not set up
5257 in the same insn. */
5258 add_next_usage_insn (src_regno
, curr_insn
, reloads_num
);
5260 else if (src_regno
< FIRST_PSEUDO_REGISTER
5261 || reg_renumber
[src_regno
] >= 0)
5264 rtx use_insn
= curr_insn
;
5266 before_p
= (JUMP_P (curr_insn
)
5267 || (CALL_P (curr_insn
) && reg
->type
== OP_IN
));
5268 if (NONDEBUG_INSN_P (curr_insn
)
5269 && split_if_necessary (src_regno
, reg
->biggest_mode
,
5270 potential_reload_hard_regs
,
5271 before_p
, curr_insn
, max_uid
))
5274 lra_risky_transformations_p
= true;
5277 usage_insns
[src_regno
].check
= 0;
5279 use_insn
= PREV_INSN (curr_insn
);
5281 if (NONDEBUG_INSN_P (curr_insn
))
5283 if (src_regno
< FIRST_PSEUDO_REGISTER
)
5284 add_to_hard_reg_set (&live_hard_regs
,
5285 reg
->biggest_mode
, src_regno
);
5287 add_to_hard_reg_set (&live_hard_regs
,
5288 PSEUDO_REGNO_MODE (src_regno
),
5289 reg_renumber
[src_regno
]);
5291 add_next_usage_insn (src_regno
, use_insn
, reloads_num
);
5294 for (i
= 0; i
< to_inherit_num
; i
++)
5296 src_regno
= to_inherit
[i
].regno
;
5297 if (inherit_reload_reg (false, src_regno
, ALL_REGS
,
5298 curr_insn
, to_inherit
[i
].insns
))
5301 setup_next_usage_insn (src_regno
, curr_insn
, reloads_num
, false);
5304 /* We reached the start of the current basic block. */
5305 if (prev_insn
== NULL_RTX
|| prev_insn
== PREV_INSN (head
)
5306 || BLOCK_FOR_INSN (prev_insn
) != curr_bb
)
5308 /* We reached the beginning of the current block -- do
5309 rest of spliting in the current BB. */
5310 to_process
= df_get_live_in (curr_bb
);
5311 if (BLOCK_FOR_INSN (head
) != curr_bb
)
5313 /* We are somewhere in the middle of EBB. */
5314 get_live_on_other_edges (EDGE_PRED (curr_bb
, 0)->src
,
5315 curr_bb
, &temp_bitmap
);
5316 to_process
= &temp_bitmap
;
5319 EXECUTE_IF_SET_IN_BITMAP (to_process
, 0, j
, bi
)
5321 if ((int) j
>= lra_constraint_new_regno_start
)
5323 if (((int) j
< FIRST_PSEUDO_REGISTER
|| reg_renumber
[j
] >= 0)
5324 && usage_insns
[j
].check
== curr_usage_insns_check
5325 && (next_usage_insns
= usage_insns
[j
].insns
) != NULL_RTX
)
5327 if (need_for_split_p (potential_reload_hard_regs
, j
))
5329 if (lra_dump_file
!= NULL
&& head_p
)
5331 fprintf (lra_dump_file
,
5332 " ----------------------------------\n");
5335 if (split_reg (false, j
, bb_note (curr_bb
),
5339 usage_insns
[j
].check
= 0;
5347 /* This value affects EBB forming. If probability of edge from EBB to
5348 a BB is not greater than the following value, we don't add the BB
5350 #define EBB_PROBABILITY_CUTOFF ((REG_BR_PROB_BASE * 50) / 100)
5352 /* Current number of inheritance/split iteration. */
5353 int lra_inheritance_iter
;
5355 /* Entry function for inheritance/split pass. */
5357 lra_inheritance (void)
5360 basic_block bb
, start_bb
;
5363 lra_inheritance_iter
++;
5364 if (lra_inheritance_iter
> LRA_MAX_INHERITANCE_PASSES
)
5366 timevar_push (TV_LRA_INHERITANCE
);
5367 if (lra_dump_file
!= NULL
)
5368 fprintf (lra_dump_file
, "\n********** Inheritance #%d: **********\n\n",
5369 lra_inheritance_iter
);
5370 curr_usage_insns_check
= 0;
5371 usage_insns
= XNEWVEC (struct usage_insns
, lra_constraint_new_regno_start
);
5372 for (i
= 0; i
< lra_constraint_new_regno_start
; i
++)
5373 usage_insns
[i
].check
= 0;
5374 bitmap_initialize (&check_only_regs
, ®_obstack
);
5375 bitmap_initialize (&live_regs
, ®_obstack
);
5376 bitmap_initialize (&temp_bitmap
, ®_obstack
);
5377 bitmap_initialize (&ebb_global_regs
, ®_obstack
);
5378 FOR_EACH_BB_FN (bb
, cfun
)
5381 if (lra_dump_file
!= NULL
)
5382 fprintf (lra_dump_file
, "EBB");
5383 /* Form a EBB starting with BB. */
5384 bitmap_clear (&ebb_global_regs
);
5385 bitmap_ior_into (&ebb_global_regs
, df_get_live_in (bb
));
5388 if (lra_dump_file
!= NULL
)
5389 fprintf (lra_dump_file
, " %d", bb
->index
);
5390 if (bb
->next_bb
== EXIT_BLOCK_PTR_FOR_FN (cfun
)
5391 || LABEL_P (BB_HEAD (bb
->next_bb
)))
5393 e
= find_fallthru_edge (bb
->succs
);
5396 if (e
->probability
<= EBB_PROBABILITY_CUTOFF
)
5400 bitmap_ior_into (&ebb_global_regs
, df_get_live_out (bb
));
5401 if (lra_dump_file
!= NULL
)
5402 fprintf (lra_dump_file
, "\n");
5403 if (inherit_in_ebb (BB_HEAD (start_bb
), BB_END (bb
)))
5404 /* Remember that the EBB head and tail can change in
5406 update_ebb_live_info (BB_HEAD (start_bb
), BB_END (bb
));
5408 bitmap_clear (&ebb_global_regs
);
5409 bitmap_clear (&temp_bitmap
);
5410 bitmap_clear (&live_regs
);
5411 bitmap_clear (&check_only_regs
);
5414 timevar_pop (TV_LRA_INHERITANCE
);
5419 /* This page contains code to undo failed inheritance/split
5422 /* Current number of iteration undoing inheritance/split. */
5423 int lra_undo_inheritance_iter
;
5425 /* Fix BB live info LIVE after removing pseudos created on pass doing
5426 inheritance/split which are REMOVED_PSEUDOS. */
5428 fix_bb_live_info (bitmap live
, bitmap removed_pseudos
)
5433 EXECUTE_IF_SET_IN_BITMAP (removed_pseudos
, 0, regno
, bi
)
5434 if (bitmap_clear_bit (live
, regno
))
5435 bitmap_set_bit (live
, lra_reg_info
[regno
].restore_regno
);
5438 /* Return regno of the (subreg of) REG. Otherwise, return a negative
5443 if (GET_CODE (reg
) == SUBREG
)
5444 reg
= SUBREG_REG (reg
);
5450 /* Remove inheritance/split pseudos which are in REMOVE_PSEUDOS and
5451 return true if we did any change. The undo transformations for
5452 inheritance looks like
5456 p <- i, i <- p, and i <- i3
5457 where p is original pseudo from which inheritance pseudo i was
5458 created, i and i3 are removed inheritance pseudos, i2 is another
5459 not removed inheritance pseudo. All split pseudos or other
5460 occurrences of removed inheritance pseudos are changed on the
5461 corresponding original pseudos.
5463 The function also schedules insns changed and created during
5464 inheritance/split pass for processing by the subsequent constraint
5467 remove_inheritance_pseudos (bitmap remove_pseudos
)
5470 int regno
, sregno
, prev_sregno
, dregno
, restore_regno
;
5471 rtx set
, prev_set
, prev_insn
;
5472 bool change_p
, done_p
;
5474 change_p
= ! bitmap_empty_p (remove_pseudos
);
5475 /* We can not finish the function right away if CHANGE_P is true
5476 because we need to marks insns affected by previous
5477 inheritance/split pass for processing by the subsequent
5479 FOR_EACH_BB_FN (bb
, cfun
)
5481 fix_bb_live_info (df_get_live_in (bb
), remove_pseudos
);
5482 fix_bb_live_info (df_get_live_out (bb
), remove_pseudos
);
5483 FOR_BB_INSNS_REVERSE (bb
, curr_insn
)
5485 if (! INSN_P (curr_insn
))
5488 sregno
= dregno
= -1;
5489 if (change_p
&& NONDEBUG_INSN_P (curr_insn
)
5490 && (set
= single_set (curr_insn
)) != NULL_RTX
)
5492 dregno
= get_regno (SET_DEST (set
));
5493 sregno
= get_regno (SET_SRC (set
));
5496 if (sregno
>= 0 && dregno
>= 0)
5498 if ((bitmap_bit_p (remove_pseudos
, sregno
)
5499 && (lra_reg_info
[sregno
].restore_regno
== dregno
5500 || (bitmap_bit_p (remove_pseudos
, dregno
)
5501 && (lra_reg_info
[sregno
].restore_regno
5502 == lra_reg_info
[dregno
].restore_regno
))))
5503 || (bitmap_bit_p (remove_pseudos
, dregno
)
5504 && lra_reg_info
[dregno
].restore_regno
== sregno
))
5505 /* One of the following cases:
5506 original <- removed inheritance pseudo
5507 removed inherit pseudo <- another removed inherit pseudo
5508 removed inherit pseudo <- original pseudo
5510 removed_split_pseudo <- original_reg
5511 original_reg <- removed_split_pseudo */
5513 if (lra_dump_file
!= NULL
)
5515 fprintf (lra_dump_file
, " Removing %s:\n",
5516 bitmap_bit_p (&lra_split_regs
, sregno
)
5517 || bitmap_bit_p (&lra_split_regs
, dregno
)
5518 ? "split" : "inheritance");
5519 dump_insn_slim (lra_dump_file
, curr_insn
);
5521 lra_set_insn_deleted (curr_insn
);
5524 else if (bitmap_bit_p (remove_pseudos
, sregno
)
5525 && bitmap_bit_p (&lra_inheritance_pseudos
, sregno
))
5527 /* Search the following pattern:
5528 inherit_or_split_pseudo1 <- inherit_or_split_pseudo2
5529 original_pseudo <- inherit_or_split_pseudo1
5530 where the 2nd insn is the current insn and
5531 inherit_or_split_pseudo2 is not removed. If it is found,
5532 change the current insn onto:
5533 original_pseudo <- inherit_or_split_pseudo2. */
5534 for (prev_insn
= PREV_INSN (curr_insn
);
5535 prev_insn
!= NULL_RTX
&& ! NONDEBUG_INSN_P (prev_insn
);
5536 prev_insn
= PREV_INSN (prev_insn
))
5538 if (prev_insn
!= NULL_RTX
&& BLOCK_FOR_INSN (prev_insn
) == bb
5539 && (prev_set
= single_set (prev_insn
)) != NULL_RTX
5540 /* There should be no subregs in insn we are
5541 searching because only the original reg might
5542 be in subreg when we changed the mode of
5543 load/store for splitting. */
5544 && REG_P (SET_DEST (prev_set
))
5545 && REG_P (SET_SRC (prev_set
))
5546 && (int) REGNO (SET_DEST (prev_set
)) == sregno
5547 && ((prev_sregno
= REGNO (SET_SRC (prev_set
)))
5548 >= FIRST_PSEUDO_REGISTER
)
5549 /* As we consider chain of inheritance or
5550 splitting described in above comment we should
5551 check that sregno and prev_sregno were
5552 inheritance/split pseudos created from the
5553 same original regno. */
5554 && (lra_reg_info
[sregno
].restore_regno
5555 == lra_reg_info
[prev_sregno
].restore_regno
)
5556 && ! bitmap_bit_p (remove_pseudos
, prev_sregno
))
5558 lra_assert (GET_MODE (SET_SRC (prev_set
))
5559 == GET_MODE (regno_reg_rtx
[sregno
]));
5560 if (GET_CODE (SET_SRC (set
)) == SUBREG
)
5561 SUBREG_REG (SET_SRC (set
)) = SET_SRC (prev_set
);
5563 SET_SRC (set
) = SET_SRC (prev_set
);
5564 lra_push_insn_and_update_insn_regno_info (curr_insn
);
5565 lra_set_used_insn_alternative_by_uid
5566 (INSN_UID (curr_insn
), -1);
5568 if (lra_dump_file
!= NULL
)
5570 fprintf (lra_dump_file
, " Change reload insn:\n");
5571 dump_insn_slim (lra_dump_file
, curr_insn
);
5578 struct lra_insn_reg
*reg
;
5579 bool restored_regs_p
= false;
5580 bool kept_regs_p
= false;
5582 curr_id
= lra_get_insn_recog_data (curr_insn
);
5583 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
5586 restore_regno
= lra_reg_info
[regno
].restore_regno
;
5587 if (restore_regno
>= 0)
5589 if (change_p
&& bitmap_bit_p (remove_pseudos
, regno
))
5591 substitute_pseudo (&curr_insn
, regno
,
5592 regno_reg_rtx
[restore_regno
]);
5593 restored_regs_p
= true;
5599 if (NONDEBUG_INSN_P (curr_insn
) && kept_regs_p
)
5601 /* The instruction has changed since the previous
5602 constraints pass. */
5603 lra_push_insn_and_update_insn_regno_info (curr_insn
);
5604 lra_set_used_insn_alternative_by_uid
5605 (INSN_UID (curr_insn
), -1);
5607 else if (restored_regs_p
)
5608 /* The instruction has been restored to the form that
5609 it had during the previous constraints pass. */
5610 lra_update_insn_regno_info (curr_insn
);
5611 if (restored_regs_p
&& lra_dump_file
!= NULL
)
5613 fprintf (lra_dump_file
, " Insn after restoring regs:\n");
5614 dump_insn_slim (lra_dump_file
, curr_insn
);
5622 /* If optional reload pseudos failed to get a hard register or was not
5623 inherited, it is better to remove optional reloads. We do this
5624 transformation after undoing inheritance to figure out necessity to
5625 remove optional reloads easier. Return true if we do any
5628 undo_optional_reloads (void)
5630 bool change_p
, keep_p
;
5631 unsigned int regno
, uid
;
5632 bitmap_iterator bi
, bi2
;
5633 rtx insn
, set
, src
, dest
;
5634 bitmap_head removed_optional_reload_pseudos
, insn_bitmap
;
5636 bitmap_initialize (&removed_optional_reload_pseudos
, ®_obstack
);
5637 bitmap_copy (&removed_optional_reload_pseudos
, &lra_optional_reload_pseudos
);
5638 EXECUTE_IF_SET_IN_BITMAP (&lra_optional_reload_pseudos
, 0, regno
, bi
)
5641 /* Keep optional reloads from previous subpasses. */
5642 if (lra_reg_info
[regno
].restore_regno
< 0
5643 /* If the original pseudo changed its allocation, just
5644 removing the optional pseudo is dangerous as the original
5645 pseudo will have longer live range. */
5646 || reg_renumber
[lra_reg_info
[regno
].restore_regno
] >= 0)
5648 else if (reg_renumber
[regno
] >= 0)
5649 EXECUTE_IF_SET_IN_BITMAP (&lra_reg_info
[regno
].insn_bitmap
, 0, uid
, bi2
)
5651 insn
= lra_insn_recog_data
[uid
]->insn
;
5652 if ((set
= single_set (insn
)) == NULL_RTX
)
5654 src
= SET_SRC (set
);
5655 dest
= SET_DEST (set
);
5656 if (! REG_P (src
) || ! REG_P (dest
))
5658 if (REGNO (dest
) == regno
5659 /* Ignore insn for optional reloads itself. */
5660 && lra_reg_info
[regno
].restore_regno
!= (int) REGNO (src
)
5661 /* Check only inheritance on last inheritance pass. */
5662 && (int) REGNO (src
) >= new_regno_start
5663 /* Check that the optional reload was inherited. */
5664 && bitmap_bit_p (&lra_inheritance_pseudos
, REGNO (src
)))
5672 bitmap_clear_bit (&removed_optional_reload_pseudos
, regno
);
5673 if (lra_dump_file
!= NULL
)
5674 fprintf (lra_dump_file
, "Keep optional reload reg %d\n", regno
);
5677 change_p
= ! bitmap_empty_p (&removed_optional_reload_pseudos
);
5678 bitmap_initialize (&insn_bitmap
, ®_obstack
);
5679 EXECUTE_IF_SET_IN_BITMAP (&removed_optional_reload_pseudos
, 0, regno
, bi
)
5681 if (lra_dump_file
!= NULL
)
5682 fprintf (lra_dump_file
, "Remove optional reload reg %d\n", regno
);
5683 bitmap_copy (&insn_bitmap
, &lra_reg_info
[regno
].insn_bitmap
);
5684 EXECUTE_IF_SET_IN_BITMAP (&insn_bitmap
, 0, uid
, bi2
)
5686 insn
= lra_insn_recog_data
[uid
]->insn
;
5687 if ((set
= single_set (insn
)) != NULL_RTX
)
5689 src
= SET_SRC (set
);
5690 dest
= SET_DEST (set
);
5691 if (REG_P (src
) && REG_P (dest
)
5692 && ((REGNO (src
) == regno
5693 && (lra_reg_info
[regno
].restore_regno
5694 == (int) REGNO (dest
)))
5695 || (REGNO (dest
) == regno
5696 && (lra_reg_info
[regno
].restore_regno
5697 == (int) REGNO (src
)))))
5699 if (lra_dump_file
!= NULL
)
5701 fprintf (lra_dump_file
, " Deleting move %u\n",
5703 dump_insn_slim (lra_dump_file
, insn
);
5705 lra_set_insn_deleted (insn
);
5708 /* We should not worry about generation memory-memory
5709 moves here as if the corresponding inheritance did
5710 not work (inheritance pseudo did not get a hard reg),
5711 we remove the inheritance pseudo and the optional
5714 substitute_pseudo (&insn
, regno
,
5715 regno_reg_rtx
[lra_reg_info
[regno
].restore_regno
]);
5716 lra_update_insn_regno_info (insn
);
5717 if (lra_dump_file
!= NULL
)
5719 fprintf (lra_dump_file
,
5720 " Restoring original insn:\n");
5721 dump_insn_slim (lra_dump_file
, insn
);
5725 /* Clear restore_regnos. */
5726 EXECUTE_IF_SET_IN_BITMAP (&lra_optional_reload_pseudos
, 0, regno
, bi
)
5727 lra_reg_info
[regno
].restore_regno
= -1;
5728 bitmap_clear (&insn_bitmap
);
5729 bitmap_clear (&removed_optional_reload_pseudos
);
5733 /* Entry function for undoing inheritance/split transformation. Return true
5734 if we did any RTL change in this pass. */
5736 lra_undo_inheritance (void)
5739 int restore_regno
, hard_regno
;
5740 int n_all_inherit
, n_inherit
, n_all_split
, n_split
;
5741 bitmap_head remove_pseudos
;
5745 lra_undo_inheritance_iter
++;
5746 if (lra_undo_inheritance_iter
> LRA_MAX_INHERITANCE_PASSES
)
5748 if (lra_dump_file
!= NULL
)
5749 fprintf (lra_dump_file
,
5750 "\n********** Undoing inheritance #%d: **********\n\n",
5751 lra_undo_inheritance_iter
);
5752 bitmap_initialize (&remove_pseudos
, ®_obstack
);
5753 n_inherit
= n_all_inherit
= 0;
5754 EXECUTE_IF_SET_IN_BITMAP (&lra_inheritance_pseudos
, 0, regno
, bi
)
5755 if (lra_reg_info
[regno
].restore_regno
>= 0)
5758 if (reg_renumber
[regno
] < 0
5759 /* If the original pseudo changed its allocation, just
5760 removing inheritance is dangerous as for changing
5761 allocation we used shorter live-ranges. */
5762 && reg_renumber
[lra_reg_info
[regno
].restore_regno
] < 0)
5763 bitmap_set_bit (&remove_pseudos
, regno
);
5767 if (lra_dump_file
!= NULL
&& n_all_inherit
!= 0)
5768 fprintf (lra_dump_file
, "Inherit %d out of %d (%.2f%%)\n",
5769 n_inherit
, n_all_inherit
,
5770 (double) n_inherit
/ n_all_inherit
* 100);
5771 n_split
= n_all_split
= 0;
5772 EXECUTE_IF_SET_IN_BITMAP (&lra_split_regs
, 0, regno
, bi
)
5773 if ((restore_regno
= lra_reg_info
[regno
].restore_regno
) >= 0)
5776 hard_regno
= (restore_regno
>= FIRST_PSEUDO_REGISTER
5777 ? reg_renumber
[restore_regno
] : restore_regno
);
5778 if (hard_regno
< 0 || reg_renumber
[regno
] == hard_regno
)
5779 bitmap_set_bit (&remove_pseudos
, regno
);
5783 if (lra_dump_file
!= NULL
)
5784 fprintf (lra_dump_file
, " Keep split r%d (orig=r%d)\n",
5785 regno
, restore_regno
);
5788 if (lra_dump_file
!= NULL
&& n_all_split
!= 0)
5789 fprintf (lra_dump_file
, "Split %d out of %d (%.2f%%)\n",
5790 n_split
, n_all_split
,
5791 (double) n_split
/ n_all_split
* 100);
5792 change_p
= remove_inheritance_pseudos (&remove_pseudos
);
5793 bitmap_clear (&remove_pseudos
);
5794 /* Clear restore_regnos. */
5795 EXECUTE_IF_SET_IN_BITMAP (&lra_inheritance_pseudos
, 0, regno
, bi
)
5796 lra_reg_info
[regno
].restore_regno
= -1;
5797 EXECUTE_IF_SET_IN_BITMAP (&lra_split_regs
, 0, regno
, bi
)
5798 lra_reg_info
[regno
].restore_regno
= -1;
5799 change_p
= undo_optional_reloads () || change_p
;