1 /* Code for RTL transformations to satisfy insn constraints.
2 Copyright (C) 2010-2013 Free Software Foundation, Inc.
3 Contributed by Vladimir Makarov <vmakarov@redhat.com>.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 3, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
22 /* This file contains code for 3 passes: constraint pass,
23 inheritance/split pass, and pass for undoing failed inheritance and
26 The major goal of constraint pass is to transform RTL to satisfy
27 insn and address constraints by:
28 o choosing insn alternatives;
29 o generating *reload insns* (or reloads in brief) and *reload
30 pseudos* which will get necessary hard registers later;
31 o substituting pseudos with equivalent values and removing the
32 instructions that initialized those pseudos.
34 The constraint pass has biggest and most complicated code in LRA.
35 There are a lot of important details like:
36 o reuse of input reload pseudos to simplify reload pseudo
38 o some heuristics to choose insn alternative to improve the
42 The pass is mimicking former reload pass in alternative choosing
43 because the reload pass is oriented to current machine description
44 model. It might be changed if the machine description model is
47 There is special code for preventing all LRA and this pass cycling
50 On the first iteration of the pass we process every instruction and
51 choose an alternative for each one. On subsequent iterations we try
52 to avoid reprocessing instructions if we can be sure that the old
53 choice is still valid.
55 The inheritance/spilt pass is to transform code to achieve
56 ineheritance and live range splitting. It is done on backward
59 The inheritance optimization goal is to reuse values in hard
60 registers. There is analogous optimization in old reload pass. The
61 inheritance is achieved by following transformation:
63 reload_p1 <- p reload_p1 <- p
64 ... new_p <- reload_p1
66 reload_p2 <- p reload_p2 <- new_p
68 where p is spilled and not changed between the insns. Reload_p1 is
69 also called *original pseudo* and new_p is called *inheritance
72 The subsequent assignment pass will try to assign the same (or
73 another if it is not possible) hard register to new_p as to
74 reload_p1 or reload_p2.
76 If the assignment pass fails to assign a hard register to new_p,
77 this file will undo the inheritance and restore the original code.
78 This is because implementing the above sequence with a spilled
79 new_p would make the code much worse. The inheritance is done in
80 EBB scope. The above is just a simplified example to get an idea
81 of the inheritance as the inheritance is also done for non-reload
84 Splitting (transformation) is also done in EBB scope on the same
85 pass as the inheritance:
87 r <- ... or ... <- r r <- ... or ... <- r
88 ... s <- r (new insn -- save)
90 ... r <- s (new insn -- restore)
93 The *split pseudo* s is assigned to the hard register of the
94 original pseudo or hard register r.
97 o In EBBs with high register pressure for global pseudos (living
98 in at least 2 BBs) and assigned to hard registers when there
99 are more one reloads needing the hard registers;
100 o for pseudos needing save/restore code around calls.
102 If the split pseudo still has the same hard register as the
103 original pseudo after the subsequent assignment pass or the
104 original pseudo was split, the opposite transformation is done on
105 the same pass for undoing inheritance. */
111 #include "coretypes.h"
113 #include "hard-reg-set.h"
117 #include "insn-config.h"
118 #include "insn-codes.h"
121 #include "addresses.h"
123 #include "function.h"
125 #include "basic-block.h"
130 #include "rtl-error.h"
133 /* Value of LRA_CURR_RELOAD_NUM at the beginning of BB of the current
134 insn. Remember that LRA_CURR_RELOAD_NUM is the number of emitted
136 static int bb_reload_num
;
138 /* The current insn being processed and corresponding its single set
139 (NULL otherwise), its data (basic block, the insn data, the insn
140 static data, and the mode of each operand). */
141 static rtx curr_insn
;
142 static rtx curr_insn_set
;
143 static basic_block curr_bb
;
144 static lra_insn_recog_data_t curr_id
;
145 static struct lra_static_insn_data
*curr_static_id
;
146 static enum machine_mode curr_operand_mode
[MAX_RECOG_OPERANDS
];
150 /* Start numbers for new registers and insns at the current constraints
152 static int new_regno_start
;
153 static int new_insn_uid_start
;
155 /* If LOC is nonnull, strip any outer subreg from it. */
157 strip_subreg (rtx
*loc
)
159 return loc
&& GET_CODE (*loc
) == SUBREG
? &SUBREG_REG (*loc
) : loc
;
162 /* Return hard regno of REGNO or if it is was not assigned to a hard
163 register, use a hard register from its allocno class. */
165 get_try_hard_regno (int regno
)
168 enum reg_class rclass
;
170 if ((hard_regno
= regno
) >= FIRST_PSEUDO_REGISTER
)
171 hard_regno
= lra_get_regno_hard_regno (regno
);
174 rclass
= lra_get_allocno_class (regno
);
175 if (rclass
== NO_REGS
)
177 return ira_class_hard_regs
[rclass
][0];
180 /* Return final hard regno (plus offset) which will be after
181 elimination. We do this for matching constraints because the final
182 hard regno could have a different class. */
184 get_final_hard_regno (int hard_regno
, int offset
)
188 hard_regno
= lra_get_elimination_hard_regno (hard_regno
);
189 return hard_regno
+ offset
;
192 /* Return hard regno of X after removing subreg and making
193 elimination. If X is not a register or subreg of register, return
194 -1. For pseudo use its assignment. */
196 get_hard_regno (rtx x
)
199 int offset
, hard_regno
;
202 if (GET_CODE (x
) == SUBREG
)
203 reg
= SUBREG_REG (x
);
206 if ((hard_regno
= REGNO (reg
)) >= FIRST_PSEUDO_REGISTER
)
207 hard_regno
= lra_get_regno_hard_regno (hard_regno
);
211 if (GET_CODE (x
) == SUBREG
)
212 offset
+= subreg_regno_offset (hard_regno
, GET_MODE (reg
),
213 SUBREG_BYTE (x
), GET_MODE (x
));
214 return get_final_hard_regno (hard_regno
, offset
);
217 /* If REGNO is a hard register or has been allocated a hard register,
218 return the class of that register. If REGNO is a reload pseudo
219 created by the current constraints pass, return its allocno class.
220 Return NO_REGS otherwise. */
221 static enum reg_class
222 get_reg_class (int regno
)
226 if ((hard_regno
= regno
) >= FIRST_PSEUDO_REGISTER
)
227 hard_regno
= lra_get_regno_hard_regno (regno
);
230 hard_regno
= get_final_hard_regno (hard_regno
, 0);
231 return REGNO_REG_CLASS (hard_regno
);
233 if (regno
>= new_regno_start
)
234 return lra_get_allocno_class (regno
);
238 /* Return true if REG satisfies (or will satisfy) reg class constraint
239 CL. Use elimination first if REG is a hard register. If REG is a
240 reload pseudo created by this constraints pass, assume that it will
241 be allocated a hard register from its allocno class, but allow that
242 class to be narrowed to CL if it is currently a superset of CL.
244 If NEW_CLASS is nonnull, set *NEW_CLASS to the new allocno class of
245 REGNO (reg), or NO_REGS if no change in its class was needed. */
247 in_class_p (rtx reg
, enum reg_class cl
, enum reg_class
*new_class
)
249 enum reg_class rclass
, common_class
;
250 enum machine_mode reg_mode
;
251 int class_size
, hard_regno
, nregs
, i
, j
;
252 int regno
= REGNO (reg
);
254 if (new_class
!= NULL
)
255 *new_class
= NO_REGS
;
256 if (regno
< FIRST_PSEUDO_REGISTER
)
259 rtx
*final_loc
= &final_reg
;
261 lra_eliminate_reg_if_possible (final_loc
);
262 return TEST_HARD_REG_BIT (reg_class_contents
[cl
], REGNO (*final_loc
));
264 reg_mode
= GET_MODE (reg
);
265 rclass
= get_reg_class (regno
);
266 if (regno
< new_regno_start
267 /* Do not allow the constraints for reload instructions to
268 influence the classes of new pseudos. These reloads are
269 typically moves that have many alternatives, and restricting
270 reload pseudos for one alternative may lead to situations
271 where other reload pseudos are no longer allocatable. */
272 || INSN_UID (curr_insn
) >= new_insn_uid_start
)
273 /* When we don't know what class will be used finally for reload
274 pseudos, we use ALL_REGS. */
275 return ((regno
>= new_regno_start
&& rclass
== ALL_REGS
)
276 || (rclass
!= NO_REGS
&& ira_class_subset_p
[rclass
][cl
]
277 && ! hard_reg_set_subset_p (reg_class_contents
[cl
],
278 lra_no_alloc_regs
)));
281 common_class
= ira_reg_class_subset
[rclass
][cl
];
282 if (new_class
!= NULL
)
283 *new_class
= common_class
;
284 if (hard_reg_set_subset_p (reg_class_contents
[common_class
],
287 /* Check that there are enough allocatable regs. */
288 class_size
= ira_class_hard_regs_num
[common_class
];
289 for (i
= 0; i
< class_size
; i
++)
291 hard_regno
= ira_class_hard_regs
[common_class
][i
];
292 nregs
= hard_regno_nregs
[hard_regno
][reg_mode
];
295 for (j
= 0; j
< nregs
; j
++)
296 if (TEST_HARD_REG_BIT (lra_no_alloc_regs
, hard_regno
+ j
)
297 || ! TEST_HARD_REG_BIT (reg_class_contents
[common_class
],
307 /* Return true if REGNO satisfies a memory constraint. */
311 return get_reg_class (regno
) == NO_REGS
;
314 /* If we have decided to substitute X with another value, return that
315 value, otherwise return X. */
317 get_equiv_substitution (rtx x
)
322 if (! REG_P (x
) || (regno
= REGNO (x
)) < FIRST_PSEUDO_REGISTER
323 || ! ira_reg_equiv
[regno
].defined_p
324 || ! ira_reg_equiv
[regno
].profitable_p
325 || lra_get_regno_hard_regno (regno
) >= 0)
327 if ((res
= ira_reg_equiv
[regno
].memory
) != NULL_RTX
)
329 if ((res
= ira_reg_equiv
[regno
].constant
) != NULL_RTX
)
331 if ((res
= ira_reg_equiv
[regno
].invariant
) != NULL_RTX
)
336 /* Set up curr_operand_mode. */
338 init_curr_operand_mode (void)
340 int nop
= curr_static_id
->n_operands
;
341 for (int i
= 0; i
< nop
; i
++)
343 enum machine_mode mode
= GET_MODE (*curr_id
->operand_loc
[i
]);
344 if (mode
== VOIDmode
)
346 /* The .md mode for address operands is the mode of the
347 addressed value rather than the mode of the address itself. */
348 if (curr_id
->icode
>= 0 && curr_static_id
->operand
[i
].is_address
)
351 mode
= curr_static_id
->operand
[i
].mode
;
353 curr_operand_mode
[i
] = mode
;
359 /* The page contains code to reuse input reloads. */
361 /* Structure describes input reload of the current insns. */
364 /* Reloaded value. */
366 /* Reload pseudo used. */
370 /* The number of elements in the following array. */
371 static int curr_insn_input_reloads_num
;
372 /* Array containing info about input reloads. It is used to find the
373 same input reload and reuse the reload pseudo in this case. */
374 static struct input_reload curr_insn_input_reloads
[LRA_MAX_INSN_RELOADS
];
376 /* Initiate data concerning reuse of input reloads for the current
379 init_curr_insn_input_reloads (void)
381 curr_insn_input_reloads_num
= 0;
384 /* Change class of pseudo REGNO to NEW_CLASS. Print info about it
385 using TITLE. Output a new line if NL_P. */
387 change_class (int regno
, enum reg_class new_class
,
388 const char *title
, bool nl_p
)
390 lra_assert (regno
>= FIRST_PSEUDO_REGISTER
);
391 if (lra_dump_file
!= NULL
)
392 fprintf (lra_dump_file
, "%s to class %s for r%d",
393 title
, reg_class_names
[new_class
], regno
);
394 setup_reg_classes (regno
, new_class
, NO_REGS
, new_class
);
395 if (lra_dump_file
!= NULL
&& nl_p
)
396 fprintf (lra_dump_file
, "\n");
399 /* Create a new pseudo using MODE, RCLASS, ORIGINAL or reuse already
400 created input reload pseudo (only if TYPE is not OP_OUT). The
401 result pseudo is returned through RESULT_REG. Return TRUE if we
402 created a new pseudo, FALSE if we reused the already created input
403 reload pseudo. Use TITLE to describe new registers for debug
406 get_reload_reg (enum op_type type
, enum machine_mode mode
, rtx original
,
407 enum reg_class rclass
, const char *title
, rtx
*result_reg
)
410 enum reg_class new_class
;
415 = lra_create_new_reg_with_unique_value (mode
, original
, rclass
, title
);
418 /* Prevent reuse value of expression with side effects,
419 e.g. volatile memory. */
420 if (! side_effects_p (original
))
421 for (i
= 0; i
< curr_insn_input_reloads_num
; i
++)
422 if (rtx_equal_p (curr_insn_input_reloads
[i
].input
, original
)
423 && in_class_p (curr_insn_input_reloads
[i
].reg
, rclass
, &new_class
))
425 rtx reg
= curr_insn_input_reloads
[i
].reg
;
427 /* If input is equal to original and both are VOIDmode,
428 GET_MODE (reg) might be still different from mode.
429 Ensure we don't return *result_reg with wrong mode. */
430 if (GET_MODE (reg
) != mode
)
432 if (GET_MODE_SIZE (GET_MODE (reg
)) < GET_MODE_SIZE (mode
))
434 reg
= lowpart_subreg (mode
, reg
, GET_MODE (reg
));
435 if (reg
== NULL_RTX
|| GET_CODE (reg
) != SUBREG
)
439 if (lra_dump_file
!= NULL
)
441 fprintf (lra_dump_file
, " Reuse r%d for reload ", regno
);
442 dump_value_slim (lra_dump_file
, original
, 1);
444 if (new_class
!= lra_get_allocno_class (regno
))
445 change_class (regno
, new_class
, ", change", false);
446 if (lra_dump_file
!= NULL
)
447 fprintf (lra_dump_file
, "\n");
450 *result_reg
= lra_create_new_reg (mode
, original
, rclass
, title
);
451 lra_assert (curr_insn_input_reloads_num
< LRA_MAX_INSN_RELOADS
);
452 curr_insn_input_reloads
[curr_insn_input_reloads_num
].input
= original
;
453 curr_insn_input_reloads
[curr_insn_input_reloads_num
++].reg
= *result_reg
;
459 /* The page contains code to extract memory address parts. */
461 /* Wrapper around REGNO_OK_FOR_INDEX_P, to allow pseudos. */
463 ok_for_index_p_nonstrict (rtx reg
)
465 unsigned regno
= REGNO (reg
);
467 return regno
>= FIRST_PSEUDO_REGISTER
|| REGNO_OK_FOR_INDEX_P (regno
);
470 /* A version of regno_ok_for_base_p for use here, when all pseudos
471 should count as OK. Arguments as for regno_ok_for_base_p. */
473 ok_for_base_p_nonstrict (rtx reg
, enum machine_mode mode
, addr_space_t as
,
474 enum rtx_code outer_code
, enum rtx_code index_code
)
476 unsigned regno
= REGNO (reg
);
478 if (regno
>= FIRST_PSEUDO_REGISTER
)
480 return ok_for_base_p_1 (regno
, mode
, as
, outer_code
, index_code
);
485 /* The page contains major code to choose the current insn alternative
486 and generate reloads for it. */
488 /* Return the offset from REGNO of the least significant register
491 This function is used to tell whether two registers satisfy
492 a matching constraint. (reg:MODE1 REGNO1) matches (reg:MODE2 REGNO2) if:
494 REGNO1 + lra_constraint_offset (REGNO1, MODE1)
495 == REGNO2 + lra_constraint_offset (REGNO2, MODE2) */
497 lra_constraint_offset (int regno
, enum machine_mode mode
)
499 lra_assert (regno
< FIRST_PSEUDO_REGISTER
);
500 if (WORDS_BIG_ENDIAN
&& GET_MODE_SIZE (mode
) > UNITS_PER_WORD
501 && SCALAR_INT_MODE_P (mode
))
502 return hard_regno_nregs
[regno
][mode
] - 1;
506 /* Like rtx_equal_p except that it allows a REG and a SUBREG to match
507 if they are the same hard reg, and has special hacks for
508 auto-increment and auto-decrement. This is specifically intended for
509 process_alt_operands to use in determining whether two operands
510 match. X is the operand whose number is the lower of the two.
512 It is supposed that X is the output operand and Y is the input
513 operand. Y_HARD_REGNO is the final hard regno of register Y or
514 register in subreg Y as we know it now. Otherwise, it is a
517 operands_match_p (rtx x
, rtx y
, int y_hard_regno
)
520 RTX_CODE code
= GET_CODE (x
);
525 if ((code
== REG
|| (code
== SUBREG
&& REG_P (SUBREG_REG (x
))))
526 && (REG_P (y
) || (GET_CODE (y
) == SUBREG
&& REG_P (SUBREG_REG (y
)))))
530 i
= get_hard_regno (x
);
534 if ((j
= y_hard_regno
) < 0)
537 i
+= lra_constraint_offset (i
, GET_MODE (x
));
538 j
+= lra_constraint_offset (j
, GET_MODE (y
));
543 /* If two operands must match, because they are really a single
544 operand of an assembler insn, then two post-increments are invalid
545 because the assembler insn would increment only once. On the
546 other hand, a post-increment matches ordinary indexing if the
547 post-increment is the output operand. */
548 if (code
== POST_DEC
|| code
== POST_INC
|| code
== POST_MODIFY
)
549 return operands_match_p (XEXP (x
, 0), y
, y_hard_regno
);
551 /* Two pre-increments are invalid because the assembler insn would
552 increment only once. On the other hand, a pre-increment matches
553 ordinary indexing if the pre-increment is the input operand. */
554 if (GET_CODE (y
) == PRE_DEC
|| GET_CODE (y
) == PRE_INC
555 || GET_CODE (y
) == PRE_MODIFY
)
556 return operands_match_p (x
, XEXP (y
, 0), -1);
560 if (code
== REG
&& GET_CODE (y
) == SUBREG
&& REG_P (SUBREG_REG (y
))
561 && x
== SUBREG_REG (y
))
563 if (GET_CODE (y
) == REG
&& code
== SUBREG
&& REG_P (SUBREG_REG (x
))
564 && SUBREG_REG (x
) == y
)
567 /* Now we have disposed of all the cases in which different rtx
569 if (code
!= GET_CODE (y
))
572 /* (MULT:SI x y) and (MULT:HI x y) are NOT equivalent. */
573 if (GET_MODE (x
) != GET_MODE (y
))
582 return XEXP (x
, 0) == XEXP (y
, 0);
584 return XSTR (x
, 0) == XSTR (y
, 0);
590 /* Compare the elements. If any pair of corresponding elements fail
591 to match, return false for the whole things. */
593 fmt
= GET_RTX_FORMAT (code
);
594 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
600 if (XWINT (x
, i
) != XWINT (y
, i
))
605 if (XINT (x
, i
) != XINT (y
, i
))
610 val
= operands_match_p (XEXP (x
, i
), XEXP (y
, i
), -1);
619 if (XVECLEN (x
, i
) != XVECLEN (y
, i
))
621 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; --j
)
623 val
= operands_match_p (XVECEXP (x
, i
, j
), XVECEXP (y
, i
, j
), -1);
629 /* It is believed that rtx's at this level will never
630 contain anything but integers and other rtx's, except for
631 within LABEL_REFs and SYMBOL_REFs. */
639 /* True if X is a constant that can be forced into the constant pool.
640 MODE is the mode of the operand, or VOIDmode if not known. */
641 #define CONST_POOL_OK_P(MODE, X) \
642 ((MODE) != VOIDmode \
644 && GET_CODE (X) != HIGH \
645 && !targetm.cannot_force_const_mem (MODE, X))
647 /* True if C is a non-empty register class that has too few registers
648 to be safely used as a reload target class. */
649 #define SMALL_REGISTER_CLASS_P(C) \
650 (reg_class_size [(C)] == 1 \
651 || (reg_class_size [(C)] >= 1 && targetm.class_likely_spilled_p (C)))
653 /* If REG is a reload pseudo, try to make its class satisfying CL. */
655 narrow_reload_pseudo_class (rtx reg
, enum reg_class cl
)
657 enum reg_class rclass
;
659 /* Do not make more accurate class from reloads generated. They are
660 mostly moves with a lot of constraints. Making more accurate
661 class may results in very narrow class and impossibility of find
662 registers for several reloads of one insn. */
663 if (INSN_UID (curr_insn
) >= new_insn_uid_start
)
665 if (GET_CODE (reg
) == SUBREG
)
666 reg
= SUBREG_REG (reg
);
667 if (! REG_P (reg
) || (int) REGNO (reg
) < new_regno_start
)
669 if (in_class_p (reg
, cl
, &rclass
) && rclass
!= cl
)
670 change_class (REGNO (reg
), rclass
, " Change", true);
673 /* Generate reloads for matching OUT and INS (array of input operand
674 numbers with end marker -1) with reg class GOAL_CLASS. Add input
675 and output reloads correspondingly to the lists *BEFORE and *AFTER.
676 OUT might be negative. In this case we generate input reloads for
677 matched input operands INS. */
679 match_reload (signed char out
, signed char *ins
, enum reg_class goal_class
,
680 rtx
*before
, rtx
*after
)
683 rtx new_in_reg
, new_out_reg
, reg
, clobber
;
684 enum machine_mode inmode
, outmode
;
685 rtx in_rtx
= *curr_id
->operand_loc
[ins
[0]];
686 rtx out_rtx
= out
< 0 ? in_rtx
: *curr_id
->operand_loc
[out
];
688 inmode
= curr_operand_mode
[ins
[0]];
689 outmode
= out
< 0 ? inmode
: curr_operand_mode
[out
];
690 push_to_sequence (*before
);
691 if (inmode
!= outmode
)
693 if (GET_MODE_SIZE (inmode
) > GET_MODE_SIZE (outmode
))
696 = lra_create_new_reg_with_unique_value (inmode
, in_rtx
,
698 if (SCALAR_INT_MODE_P (inmode
))
699 new_out_reg
= gen_lowpart_SUBREG (outmode
, reg
);
701 new_out_reg
= gen_rtx_SUBREG (outmode
, reg
, 0);
702 LRA_SUBREG_P (new_out_reg
) = 1;
703 /* If the input reg is dying here, we can use the same hard
704 register for REG and IN_RTX. We do it only for original
705 pseudos as reload pseudos can die although original
706 pseudos still live where reload pseudos dies. */
707 if (REG_P (in_rtx
) && (int) REGNO (in_rtx
) < lra_new_regno_start
708 && find_regno_note (curr_insn
, REG_DEAD
, REGNO (in_rtx
)))
709 lra_assign_reg_val (REGNO (in_rtx
), REGNO (reg
));
714 = lra_create_new_reg_with_unique_value (outmode
, out_rtx
,
716 if (SCALAR_INT_MODE_P (outmode
))
717 new_in_reg
= gen_lowpart_SUBREG (inmode
, reg
);
719 new_in_reg
= gen_rtx_SUBREG (inmode
, reg
, 0);
720 /* NEW_IN_REG is non-paradoxical subreg. We don't want
721 NEW_OUT_REG living above. We add clobber clause for
722 this. This is just a temporary clobber. We can remove
723 it at the end of LRA work. */
724 clobber
= emit_clobber (new_out_reg
);
725 LRA_TEMP_CLOBBER_P (PATTERN (clobber
)) = 1;
726 LRA_SUBREG_P (new_in_reg
) = 1;
727 if (GET_CODE (in_rtx
) == SUBREG
)
729 rtx subreg_reg
= SUBREG_REG (in_rtx
);
731 /* If SUBREG_REG is dying here and sub-registers IN_RTX
732 and NEW_IN_REG are similar, we can use the same hard
733 register for REG and SUBREG_REG. */
734 if (REG_P (subreg_reg
)
735 && (int) REGNO (subreg_reg
) < lra_new_regno_start
736 && GET_MODE (subreg_reg
) == outmode
737 && SUBREG_BYTE (in_rtx
) == SUBREG_BYTE (new_in_reg
)
738 && find_regno_note (curr_insn
, REG_DEAD
, REGNO (subreg_reg
)))
739 lra_assign_reg_val (REGNO (subreg_reg
), REGNO (reg
));
745 /* Pseudos have values -- see comments for lra_reg_info.
746 Different pseudos with the same value do not conflict even if
747 they live in the same place. When we create a pseudo we
748 assign value of original pseudo (if any) from which we
749 created the new pseudo. If we create the pseudo from the
750 input pseudo, the new pseudo will no conflict with the input
751 pseudo which is wrong when the input pseudo lives after the
752 insn and as the new pseudo value is changed by the insn
753 output. Therefore we create the new pseudo from the output.
755 We cannot reuse the current output register because we might
756 have a situation like "a <- a op b", where the constraints
757 force the second input operand ("b") to match the output
758 operand ("a"). "b" must then be copied into a new register
759 so that it doesn't clobber the current value of "a". */
761 new_in_reg
= new_out_reg
762 = lra_create_new_reg_with_unique_value (outmode
, out_rtx
,
765 /* In operand can be got from transformations before processing insn
766 constraints. One example of such transformations is subreg
767 reloading (see function simplify_operand_subreg). The new
768 pseudos created by the transformations might have inaccurate
769 class (ALL_REGS) and we should make their classes more
771 narrow_reload_pseudo_class (in_rtx
, goal_class
);
772 lra_emit_move (copy_rtx (new_in_reg
), in_rtx
);
773 *before
= get_insns ();
775 for (i
= 0; (in
= ins
[i
]) >= 0; i
++)
778 (GET_MODE (*curr_id
->operand_loc
[in
]) == VOIDmode
779 || GET_MODE (new_in_reg
) == GET_MODE (*curr_id
->operand_loc
[in
]));
780 *curr_id
->operand_loc
[in
] = new_in_reg
;
782 lra_update_dups (curr_id
, ins
);
785 /* See a comment for the input operand above. */
786 narrow_reload_pseudo_class (out_rtx
, goal_class
);
787 if (find_reg_note (curr_insn
, REG_UNUSED
, out_rtx
) == NULL_RTX
)
790 lra_emit_move (out_rtx
, copy_rtx (new_out_reg
));
792 *after
= get_insns ();
795 *curr_id
->operand_loc
[out
] = new_out_reg
;
796 lra_update_dup (curr_id
, out
);
799 /* Return register class which is union of all reg classes in insn
800 constraint alternative string starting with P. */
801 static enum reg_class
802 reg_class_from_constraints (const char *p
)
805 enum reg_class op_class
= NO_REGS
;
808 switch ((c
= *p
, len
= CONSTRAINT_LEN (c
, p
)), c
)
815 op_class
= (reg_class_subunion
816 [op_class
][base_reg_class (VOIDmode
, ADDR_SPACE_GENERIC
,
822 op_class
= reg_class_subunion
[op_class
][GENERAL_REGS
];
826 if (REG_CLASS_FROM_CONSTRAINT (c
, p
) == NO_REGS
)
828 #ifdef EXTRA_CONSTRAINT_STR
829 if (EXTRA_ADDRESS_CONSTRAINT (c
, p
))
831 = (reg_class_subunion
832 [op_class
][base_reg_class (VOIDmode
, ADDR_SPACE_GENERIC
,
839 = reg_class_subunion
[op_class
][REG_CLASS_FROM_CONSTRAINT (c
, p
)];
842 while ((p
+= len
), c
);
846 /* If OP is a register, return the class of the register as per
847 get_reg_class, otherwise return NO_REGS. */
848 static inline enum reg_class
849 get_op_class (rtx op
)
851 return REG_P (op
) ? get_reg_class (REGNO (op
)) : NO_REGS
;
854 /* Return generated insn mem_pseudo:=val if TO_P or val:=mem_pseudo
855 otherwise. If modes of MEM_PSEUDO and VAL are different, use
856 SUBREG for VAL to make them equal. */
858 emit_spill_move (bool to_p
, rtx mem_pseudo
, rtx val
)
860 if (GET_MODE (mem_pseudo
) != GET_MODE (val
))
862 /* Usually size of mem_pseudo is greater than val size but in
863 rare cases it can be less as it can be defined by target
864 dependent macro HARD_REGNO_CALLER_SAVE_MODE. */
867 val
= gen_rtx_SUBREG (GET_MODE (mem_pseudo
),
868 GET_CODE (val
) == SUBREG
? SUBREG_REG (val
) : val
,
870 LRA_SUBREG_P (val
) = 1;
874 mem_pseudo
= gen_lowpart_SUBREG (GET_MODE (val
), mem_pseudo
);
875 LRA_SUBREG_P (mem_pseudo
) = 1;
879 ? gen_move_insn (mem_pseudo
, val
)
880 : gen_move_insn (val
, mem_pseudo
));
883 /* Process a special case insn (register move), return true if we
884 don't need to process it anymore. INSN should be a single set
885 insn. Set up that RTL was changed through CHANGE_P and macro
886 SECONDARY_MEMORY_NEEDED says to use secondary memory through
889 check_and_process_move (bool *change_p
, bool *sec_mem_p ATTRIBUTE_UNUSED
)
892 rtx dest
, src
, dreg
, sreg
, old_sreg
, new_reg
, before
, scratch_reg
;
893 enum reg_class dclass
, sclass
, secondary_class
;
894 enum machine_mode sreg_mode
;
895 secondary_reload_info sri
;
897 lra_assert (curr_insn_set
!= NULL_RTX
);
898 dreg
= dest
= SET_DEST (curr_insn_set
);
899 sreg
= src
= SET_SRC (curr_insn_set
);
900 if (GET_CODE (dest
) == SUBREG
)
901 dreg
= SUBREG_REG (dest
);
902 if (GET_CODE (src
) == SUBREG
)
903 sreg
= SUBREG_REG (src
);
904 if (! (REG_P (dreg
) || MEM_P (dreg
)) || ! (REG_P (sreg
) || MEM_P (sreg
)))
906 sclass
= dclass
= NO_REGS
;
908 dclass
= get_reg_class (REGNO (dreg
));
909 if (dclass
== ALL_REGS
)
910 /* ALL_REGS is used for new pseudos created by transformations
911 like reload of SUBREG_REG (see function
912 simplify_operand_subreg). We don't know their class yet. We
913 should figure out the class from processing the insn
914 constraints not in this fast path function. Even if ALL_REGS
915 were a right class for the pseudo, secondary_... hooks usually
916 are not define for ALL_REGS. */
918 sreg_mode
= GET_MODE (sreg
);
921 sclass
= get_reg_class (REGNO (sreg
));
922 if (sclass
== ALL_REGS
)
923 /* See comments above. */
925 if (sclass
== NO_REGS
&& dclass
== NO_REGS
)
927 #ifdef SECONDARY_MEMORY_NEEDED
928 if (SECONDARY_MEMORY_NEEDED (sclass
, dclass
, GET_MODE (src
))
929 #ifdef SECONDARY_MEMORY_NEEDED_MODE
930 && ((sclass
!= NO_REGS
&& dclass
!= NO_REGS
)
931 || GET_MODE (src
) != SECONDARY_MEMORY_NEEDED_MODE (GET_MODE (src
)))
939 if (! REG_P (dreg
) || ! REG_P (sreg
))
942 sri
.icode
= CODE_FOR_nothing
;
944 secondary_class
= NO_REGS
;
945 /* Set up hard register for a reload pseudo for hook
946 secondary_reload because some targets just ignore unassigned
947 pseudos in the hook. */
948 if (dclass
!= NO_REGS
&& lra_get_regno_hard_regno (REGNO (dreg
)) < 0)
950 dregno
= REGNO (dreg
);
951 reg_renumber
[dregno
] = ira_class_hard_regs
[dclass
][0];
955 if (sclass
!= NO_REGS
&& lra_get_regno_hard_regno (REGNO (sreg
)) < 0)
957 sregno
= REGNO (sreg
);
958 reg_renumber
[sregno
] = ira_class_hard_regs
[sclass
][0];
962 if (sclass
!= NO_REGS
)
964 = (enum reg_class
) targetm
.secondary_reload (false, dest
,
965 (reg_class_t
) sclass
,
966 GET_MODE (src
), &sri
);
967 if (sclass
== NO_REGS
968 || ((secondary_class
!= NO_REGS
|| sri
.icode
!= CODE_FOR_nothing
)
969 && dclass
!= NO_REGS
))
971 enum reg_class old_sclass
= secondary_class
;
972 secondary_reload_info old_sri
= sri
;
975 sri
.icode
= CODE_FOR_nothing
;
978 = (enum reg_class
) targetm
.secondary_reload (true, sreg
,
979 (reg_class_t
) dclass
,
981 /* Check the target hook consistency. */
983 ((secondary_class
== NO_REGS
&& sri
.icode
== CODE_FOR_nothing
)
984 || (old_sclass
== NO_REGS
&& old_sri
.icode
== CODE_FOR_nothing
)
985 || (secondary_class
== old_sclass
&& sri
.icode
== old_sri
.icode
));
988 reg_renumber
[sregno
] = -1;
990 reg_renumber
[dregno
] = -1;
991 if (secondary_class
== NO_REGS
&& sri
.icode
== CODE_FOR_nothing
)
995 if (secondary_class
!= NO_REGS
)
996 new_reg
= lra_create_new_reg_with_unique_value (sreg_mode
, NULL_RTX
,
1000 if (old_sreg
!= sreg
)
1001 sreg
= copy_rtx (sreg
);
1002 if (sri
.icode
== CODE_FOR_nothing
)
1003 lra_emit_move (new_reg
, sreg
);
1006 enum reg_class scratch_class
;
1008 scratch_class
= (reg_class_from_constraints
1009 (insn_data
[sri
.icode
].operand
[2].constraint
));
1010 scratch_reg
= (lra_create_new_reg_with_unique_value
1011 (insn_data
[sri
.icode
].operand
[2].mode
, NULL_RTX
,
1012 scratch_class
, "scratch"));
1013 emit_insn (GEN_FCN (sri
.icode
) (new_reg
!= NULL_RTX
? new_reg
: dest
,
1014 sreg
, scratch_reg
));
1016 before
= get_insns ();
1018 lra_process_new_insns (curr_insn
, before
, NULL_RTX
, "Inserting the move");
1019 if (new_reg
!= NULL_RTX
)
1021 if (GET_CODE (src
) == SUBREG
)
1022 SUBREG_REG (src
) = new_reg
;
1024 SET_SRC (curr_insn_set
) = new_reg
;
1028 if (lra_dump_file
!= NULL
)
1030 fprintf (lra_dump_file
, "Deleting move %u\n", INSN_UID (curr_insn
));
1031 dump_insn_slim (lra_dump_file
, curr_insn
);
1033 lra_set_insn_deleted (curr_insn
);
1039 /* The following data describe the result of process_alt_operands.
1040 The data are used in curr_insn_transform to generate reloads. */
1042 /* The chosen reg classes which should be used for the corresponding
1044 static enum reg_class goal_alt
[MAX_RECOG_OPERANDS
];
1045 /* True if the operand should be the same as another operand and that
1046 other operand does not need a reload. */
1047 static bool goal_alt_match_win
[MAX_RECOG_OPERANDS
];
1048 /* True if the operand does not need a reload. */
1049 static bool goal_alt_win
[MAX_RECOG_OPERANDS
];
1050 /* True if the operand can be offsetable memory. */
1051 static bool goal_alt_offmemok
[MAX_RECOG_OPERANDS
];
1052 /* The number of an operand to which given operand can be matched to. */
1053 static int goal_alt_matches
[MAX_RECOG_OPERANDS
];
1054 /* The number of elements in the following array. */
1055 static int goal_alt_dont_inherit_ops_num
;
1056 /* Numbers of operands whose reload pseudos should not be inherited. */
1057 static int goal_alt_dont_inherit_ops
[MAX_RECOG_OPERANDS
];
1058 /* True if the insn commutative operands should be swapped. */
1059 static bool goal_alt_swapped
;
1060 /* The chosen insn alternative. */
1061 static int goal_alt_number
;
1063 /* The following five variables are used to choose the best insn
1064 alternative. They reflect final characteristics of the best
1067 /* Number of necessary reloads and overall cost reflecting the
1068 previous value and other unpleasantness of the best alternative. */
1069 static int best_losers
, best_overall
;
1070 /* Overall number hard registers used for reloads. For example, on
1071 some targets we need 2 general registers to reload DFmode and only
1072 one floating point register. */
1073 static int best_reload_nregs
;
1074 /* Overall number reflecting distances of previous reloading the same
1075 value. The distances are counted from the current BB start. It is
1076 used to improve inheritance chances. */
1077 static int best_reload_sum
;
1079 /* True if the current insn should have no correspondingly input or
1081 static bool no_input_reloads_p
, no_output_reloads_p
;
1083 /* True if we swapped the commutative operands in the current
1085 static int curr_swapped
;
1087 /* Arrange for address element *LOC to be a register of class CL.
1088 Add any input reloads to list BEFORE. AFTER is nonnull if *LOC is an
1089 automodified value; handle that case by adding the required output
1090 reloads to list AFTER. Return true if the RTL was changed. */
1092 process_addr_reg (rtx
*loc
, rtx
*before
, rtx
*after
, enum reg_class cl
)
1095 enum reg_class rclass
, new_class
;
1098 enum machine_mode mode
;
1099 bool before_p
= false;
1101 loc
= strip_subreg (loc
);
1103 mode
= GET_MODE (reg
);
1106 /* Always reload memory in an address even if the target supports
1108 new_reg
= lra_create_new_reg_with_unique_value (mode
, reg
, cl
, "address");
1113 regno
= REGNO (reg
);
1114 rclass
= get_reg_class (regno
);
1115 if ((*loc
= get_equiv_substitution (reg
)) != reg
)
1117 if (lra_dump_file
!= NULL
)
1119 fprintf (lra_dump_file
,
1120 "Changing pseudo %d in address of insn %u on equiv ",
1121 REGNO (reg
), INSN_UID (curr_insn
));
1122 dump_value_slim (lra_dump_file
, *loc
, 1);
1123 fprintf (lra_dump_file
, "\n");
1125 *loc
= copy_rtx (*loc
);
1127 if (*loc
!= reg
|| ! in_class_p (reg
, cl
, &new_class
))
1130 if (get_reload_reg (after
== NULL
? OP_IN
: OP_INOUT
,
1131 mode
, reg
, cl
, "address", &new_reg
))
1134 else if (new_class
!= NO_REGS
&& rclass
!= new_class
)
1136 change_class (regno
, new_class
, " Change", true);
1144 push_to_sequence (*before
);
1145 lra_emit_move (new_reg
, reg
);
1146 *before
= get_insns ();
1153 lra_emit_move (reg
, new_reg
);
1155 *after
= get_insns ();
1161 /* Make reloads for subreg in operand NOP with internal subreg mode
1162 REG_MODE, add new reloads for further processing. Return true if
1163 any reload was generated. */
1165 simplify_operand_subreg (int nop
, enum machine_mode reg_mode
)
1169 enum machine_mode mode
;
1171 rtx operand
= *curr_id
->operand_loc
[nop
];
1173 before
= after
= NULL_RTX
;
1175 if (GET_CODE (operand
) != SUBREG
)
1178 mode
= GET_MODE (operand
);
1179 reg
= SUBREG_REG (operand
);
1180 /* If we change address for paradoxical subreg of memory, the
1181 address might violate the necessary alignment or the access might
1182 be slow. So take this into consideration. We should not worry
1183 about access beyond allocated memory for paradoxical memory
1184 subregs as we don't substitute such equiv memory (see processing
1185 equivalences in function lra_constraints) and because for spilled
1186 pseudos we allocate stack memory enough for the biggest
1187 corresponding paradoxical subreg. */
1189 && (! SLOW_UNALIGNED_ACCESS (mode
, MEM_ALIGN (reg
))
1190 || MEM_ALIGN (reg
) >= GET_MODE_ALIGNMENT (mode
)))
1191 || (REG_P (reg
) && REGNO (reg
) < FIRST_PSEUDO_REGISTER
))
1193 alter_subreg (curr_id
->operand_loc
[nop
], false);
1196 /* Put constant into memory when we have mixed modes. It generates
1197 a better code in most cases as it does not need a secondary
1198 reload memory. It also prevents LRA looping when LRA is using
1199 secondary reload memory again and again. */
1200 if (CONSTANT_P (reg
) && CONST_POOL_OK_P (reg_mode
, reg
)
1201 && SCALAR_INT_MODE_P (reg_mode
) != SCALAR_INT_MODE_P (mode
))
1203 SUBREG_REG (operand
) = force_const_mem (reg_mode
, reg
);
1204 alter_subreg (curr_id
->operand_loc
[nop
], false);
1207 /* Force a reload of the SUBREG_REG if this is a constant or PLUS or
1208 if there may be a problem accessing OPERAND in the outer
1211 && REGNO (reg
) >= FIRST_PSEUDO_REGISTER
1212 && (hard_regno
= lra_get_regno_hard_regno (REGNO (reg
))) >= 0
1213 /* Don't reload paradoxical subregs because we could be looping
1214 having repeatedly final regno out of hard regs range. */
1215 && (hard_regno_nregs
[hard_regno
][GET_MODE (reg
)]
1216 >= hard_regno_nregs
[hard_regno
][mode
])
1217 && simplify_subreg_regno (hard_regno
, GET_MODE (reg
),
1218 SUBREG_BYTE (operand
), mode
) < 0
1219 /* Don't reload subreg for matching reload. It is actually
1220 valid subreg in LRA. */
1221 && ! LRA_SUBREG_P (operand
))
1222 || CONSTANT_P (reg
) || GET_CODE (reg
) == PLUS
|| MEM_P (reg
))
1224 enum op_type type
= curr_static_id
->operand
[nop
].type
;
1225 /* The class will be defined later in curr_insn_transform. */
1226 enum reg_class rclass
1227 = (enum reg_class
) targetm
.preferred_reload_class (reg
, ALL_REGS
);
1229 if (get_reload_reg (curr_static_id
->operand
[nop
].type
, reg_mode
, reg
,
1230 rclass
, "subreg reg", &new_reg
))
1232 bitmap_set_bit (&lra_subreg_reload_pseudos
, REGNO (new_reg
));
1234 || GET_MODE_SIZE (GET_MODE (reg
)) > GET_MODE_SIZE (mode
))
1236 push_to_sequence (before
);
1237 lra_emit_move (new_reg
, reg
);
1238 before
= get_insns ();
1244 lra_emit_move (reg
, new_reg
);
1246 after
= get_insns ();
1250 SUBREG_REG (operand
) = new_reg
;
1251 lra_process_new_insns (curr_insn
, before
, after
,
1252 "Inserting subreg reload");
1258 /* Return TRUE if X refers for a hard register from SET. */
1260 uses_hard_regs_p (rtx x
, HARD_REG_SET set
)
1262 int i
, j
, x_hard_regno
;
1263 enum machine_mode mode
;
1269 code
= GET_CODE (x
);
1270 mode
= GET_MODE (x
);
1274 code
= GET_CODE (x
);
1275 if (GET_MODE_SIZE (GET_MODE (x
)) > GET_MODE_SIZE (mode
))
1276 mode
= GET_MODE (x
);
1281 x_hard_regno
= get_hard_regno (x
);
1282 return (x_hard_regno
>= 0
1283 && overlaps_hard_reg_set_p (set
, mode
, x_hard_regno
));
1287 struct address_info ad
;
1289 decompose_mem_address (&ad
, x
);
1290 if (ad
.base_term
!= NULL
&& uses_hard_regs_p (*ad
.base_term
, set
))
1292 if (ad
.index_term
!= NULL
&& uses_hard_regs_p (*ad
.index_term
, set
))
1295 fmt
= GET_RTX_FORMAT (code
);
1296 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
1300 if (uses_hard_regs_p (XEXP (x
, i
), set
))
1303 else if (fmt
[i
] == 'E')
1305 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
1306 if (uses_hard_regs_p (XVECEXP (x
, i
, j
), set
))
1313 /* Return true if OP is a spilled pseudo. */
1315 spilled_pseudo_p (rtx op
)
1318 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
&& in_mem_p (REGNO (op
)));
1321 /* Return true if X is a general constant. */
1323 general_constant_p (rtx x
)
1325 return CONSTANT_P (x
) && (! flag_pic
|| LEGITIMATE_PIC_OPERAND_P (x
));
1329 reg_in_class_p (rtx reg
, enum reg_class cl
)
1332 return get_reg_class (REGNO (reg
)) == NO_REGS
;
1333 return in_class_p (reg
, cl
, NULL
);
1336 /* Major function to choose the current insn alternative and what
1337 operands should be reloaded and how. If ONLY_ALTERNATIVE is not
1338 negative we should consider only this alternative. Return false if
1339 we can not choose the alternative or find how to reload the
1342 process_alt_operands (int only_alternative
)
1345 int nop
, overall
, nalt
;
1346 int n_alternatives
= curr_static_id
->n_alternatives
;
1347 int n_operands
= curr_static_id
->n_operands
;
1348 /* LOSERS counts the operands that don't fit this alternative and
1349 would require loading. */
1351 /* REJECT is a count of how undesirable this alternative says it is
1352 if any reloading is required. If the alternative matches exactly
1353 then REJECT is ignored, but otherwise it gets this much counted
1354 against it in addition to the reloading needed. */
1356 /* The number of elements in the following array. */
1357 int early_clobbered_regs_num
;
1358 /* Numbers of operands which are early clobber registers. */
1359 int early_clobbered_nops
[MAX_RECOG_OPERANDS
];
1360 enum reg_class curr_alt
[MAX_RECOG_OPERANDS
];
1361 HARD_REG_SET curr_alt_set
[MAX_RECOG_OPERANDS
];
1362 bool curr_alt_match_win
[MAX_RECOG_OPERANDS
];
1363 bool curr_alt_win
[MAX_RECOG_OPERANDS
];
1364 bool curr_alt_offmemok
[MAX_RECOG_OPERANDS
];
1365 int curr_alt_matches
[MAX_RECOG_OPERANDS
];
1366 /* The number of elements in the following array. */
1367 int curr_alt_dont_inherit_ops_num
;
1368 /* Numbers of operands whose reload pseudos should not be inherited. */
1369 int curr_alt_dont_inherit_ops
[MAX_RECOG_OPERANDS
];
1371 /* The register when the operand is a subreg of register, otherwise the
1373 rtx no_subreg_reg_operand
[MAX_RECOG_OPERANDS
];
1374 /* The register if the operand is a register or subreg of register,
1376 rtx operand_reg
[MAX_RECOG_OPERANDS
];
1377 int hard_regno
[MAX_RECOG_OPERANDS
];
1378 enum machine_mode biggest_mode
[MAX_RECOG_OPERANDS
];
1379 int reload_nregs
, reload_sum
;
1383 /* Calculate some data common for all alternatives to speed up the
1385 for (nop
= 0; nop
< n_operands
; nop
++)
1387 op
= no_subreg_reg_operand
[nop
] = *curr_id
->operand_loc
[nop
];
1388 /* The real hard regno of the operand after the allocation. */
1389 hard_regno
[nop
] = get_hard_regno (op
);
1391 operand_reg
[nop
] = op
;
1392 biggest_mode
[nop
] = GET_MODE (operand_reg
[nop
]);
1393 if (GET_CODE (operand_reg
[nop
]) == SUBREG
)
1395 operand_reg
[nop
] = SUBREG_REG (operand_reg
[nop
]);
1396 if (GET_MODE_SIZE (biggest_mode
[nop
])
1397 < GET_MODE_SIZE (GET_MODE (operand_reg
[nop
])))
1398 biggest_mode
[nop
] = GET_MODE (operand_reg
[nop
]);
1400 if (REG_P (operand_reg
[nop
]))
1401 no_subreg_reg_operand
[nop
] = operand_reg
[nop
];
1403 operand_reg
[nop
] = NULL_RTX
;
1406 /* The constraints are made of several alternatives. Each operand's
1407 constraint looks like foo,bar,... with commas separating the
1408 alternatives. The first alternatives for all operands go
1409 together, the second alternatives go together, etc.
1411 First loop over alternatives. */
1412 for (nalt
= 0; nalt
< n_alternatives
; nalt
++)
1414 /* Loop over operands for one constraint alternative. */
1415 #if HAVE_ATTR_enabled
1416 if (curr_id
->alternative_enabled_p
!= NULL
1417 && ! curr_id
->alternative_enabled_p
[nalt
])
1421 if (only_alternative
>= 0 && nalt
!= only_alternative
)
1425 overall
= losers
= reject
= reload_nregs
= reload_sum
= 0;
1426 for (nop
= 0; nop
< n_operands
; nop
++)
1428 int inc
= (curr_static_id
1429 ->operand_alternative
[nalt
* n_operands
+ nop
].reject
);
1430 if (lra_dump_file
!= NULL
&& inc
!= 0)
1431 fprintf (lra_dump_file
,
1432 " Staticly defined alt reject+=%d\n", inc
);
1435 early_clobbered_regs_num
= 0;
1437 for (nop
= 0; nop
< n_operands
; nop
++)
1441 int len
, c
, m
, i
, opalt_num
, this_alternative_matches
;
1442 bool win
, did_match
, offmemok
, early_clobber_p
;
1443 /* false => this operand can be reloaded somehow for this
1446 /* true => this operand can be reloaded if the alternative
1449 /* True if a constant forced into memory would be OK for
1452 enum reg_class this_alternative
, this_costly_alternative
;
1453 HARD_REG_SET this_alternative_set
, this_costly_alternative_set
;
1454 bool this_alternative_match_win
, this_alternative_win
;
1455 bool this_alternative_offmemok
;
1456 enum machine_mode mode
;
1458 opalt_num
= nalt
* n_operands
+ nop
;
1459 if (curr_static_id
->operand_alternative
[opalt_num
].anything_ok
)
1461 /* Fast track for no constraints at all. */
1462 curr_alt
[nop
] = NO_REGS
;
1463 CLEAR_HARD_REG_SET (curr_alt_set
[nop
]);
1464 curr_alt_win
[nop
] = true;
1465 curr_alt_match_win
[nop
] = false;
1466 curr_alt_offmemok
[nop
] = false;
1467 curr_alt_matches
[nop
] = -1;
1471 op
= no_subreg_reg_operand
[nop
];
1472 mode
= curr_operand_mode
[nop
];
1474 win
= did_match
= winreg
= offmemok
= constmemok
= false;
1477 early_clobber_p
= false;
1478 p
= curr_static_id
->operand_alternative
[opalt_num
].constraint
;
1480 this_costly_alternative
= this_alternative
= NO_REGS
;
1481 /* We update set of possible hard regs besides its class
1482 because reg class might be inaccurate. For example,
1483 union of LO_REGS (l), HI_REGS(h), and STACK_REG(k) in ARM
1484 is translated in HI_REGS because classes are merged by
1485 pairs and there is no accurate intermediate class. */
1486 CLEAR_HARD_REG_SET (this_alternative_set
);
1487 CLEAR_HARD_REG_SET (this_costly_alternative_set
);
1488 this_alternative_win
= false;
1489 this_alternative_match_win
= false;
1490 this_alternative_offmemok
= false;
1491 this_alternative_matches
= -1;
1493 /* An empty constraint should be excluded by the fast
1495 lra_assert (*p
!= 0 && *p
!= ',');
1497 /* Scan this alternative's specs for this operand; set WIN
1498 if the operand fits any letter in this alternative.
1499 Otherwise, clear BADOP if this operand could fit some
1500 letter after reloads, or set WINREG if this operand could
1501 fit after reloads provided the constraint allows some
1506 switch ((c
= *p
, len
= CONSTRAINT_LEN (c
, p
)), c
)
1515 case '=': case '+': case '?': case '*': case '!':
1516 case ' ': case '\t':
1520 /* We only support one commutative marker, the first
1521 one. We already set commutative above. */
1525 early_clobber_p
= true;
1529 /* Ignore rest of this alternative. */
1533 case '0': case '1': case '2': case '3': case '4':
1534 case '5': case '6': case '7': case '8': case '9':
1539 m
= strtoul (p
, &end
, 10);
1542 lra_assert (nop
> m
);
1544 this_alternative_matches
= m
;
1545 m_hregno
= get_hard_regno (*curr_id
->operand_loc
[m
]);
1546 /* We are supposed to match a previous operand.
1547 If we do, we win if that one did. If we do
1548 not, count both of the operands as losers.
1549 (This is too conservative, since most of the
1550 time only a single reload insn will be needed
1551 to make the two operands win. As a result,
1552 this alternative may be rejected when it is
1553 actually desirable.) */
1555 if (operands_match_p (*curr_id
->operand_loc
[nop
],
1556 *curr_id
->operand_loc
[m
], m_hregno
))
1558 /* We should reject matching of an early
1559 clobber operand if the matching operand is
1560 not dying in the insn. */
1561 if (! curr_static_id
->operand
[m
].early_clobber
1562 || operand_reg
[nop
] == NULL_RTX
1563 || (find_regno_note (curr_insn
, REG_DEAD
,
1565 || REGNO (op
) == REGNO (operand_reg
[m
])))
1570 /* If we are matching a non-offsettable
1571 address where an offsettable address was
1572 expected, then we must reject this
1573 combination, because we can't reload
1575 if (curr_alt_offmemok
[m
]
1576 && MEM_P (*curr_id
->operand_loc
[m
])
1577 && curr_alt
[m
] == NO_REGS
&& ! curr_alt_win
[m
])
1583 /* Operands don't match. Both operands must
1584 allow a reload register, otherwise we
1585 cannot make them match. */
1586 if (curr_alt
[m
] == NO_REGS
)
1588 /* Retroactively mark the operand we had to
1589 match as a loser, if it wasn't already and
1590 it wasn't matched to a register constraint
1591 (e.g it might be matched by memory). */
1593 && (operand_reg
[m
] == NULL_RTX
1594 || hard_regno
[m
] < 0))
1598 += (ira_reg_class_max_nregs
[curr_alt
[m
]]
1599 [GET_MODE (*curr_id
->operand_loc
[m
])]);
1602 /* We prefer no matching alternatives because
1603 it gives more freedom in RA. */
1604 if (operand_reg
[nop
] == NULL_RTX
1605 || (find_regno_note (curr_insn
, REG_DEAD
,
1606 REGNO (operand_reg
[nop
]))
1609 if (lra_dump_file
!= NULL
)
1612 " %d Matching alt: reject+=2\n",
1617 /* If we have to reload this operand and some
1618 previous operand also had to match the same
1619 thing as this operand, we don't know how to do
1621 if (!match_p
|| !curr_alt_win
[m
])
1623 for (i
= 0; i
< nop
; i
++)
1624 if (curr_alt_matches
[i
] == m
)
1632 /* This can be fixed with reloads if the operand
1633 we are supposed to match can be fixed with
1636 this_alternative
= curr_alt
[m
];
1637 COPY_HARD_REG_SET (this_alternative_set
, curr_alt_set
[m
]);
1638 winreg
= this_alternative
!= NO_REGS
;
1643 cl
= base_reg_class (VOIDmode
, ADDR_SPACE_GENERIC
,
1645 this_alternative
= reg_class_subunion
[this_alternative
][cl
];
1646 IOR_HARD_REG_SET (this_alternative_set
,
1647 reg_class_contents
[cl
]);
1650 this_costly_alternative
1651 = reg_class_subunion
[this_costly_alternative
][cl
];
1652 IOR_HARD_REG_SET (this_costly_alternative_set
,
1653 reg_class_contents
[cl
]);
1659 case TARGET_MEM_CONSTRAINT
:
1660 if (MEM_P (op
) || spilled_pseudo_p (op
))
1662 /* We can put constant or pseudo value into memory
1663 to satisfy the constraint. */
1664 if (CONST_POOL_OK_P (mode
, op
) || REG_P (op
))
1671 && (GET_CODE (XEXP (op
, 0)) == PRE_DEC
1672 || GET_CODE (XEXP (op
, 0)) == POST_DEC
))
1678 && (GET_CODE (XEXP (op
, 0)) == PRE_INC
1679 || GET_CODE (XEXP (op
, 0)) == POST_INC
))
1683 /* Memory op whose address is not offsettable. */
1686 && ! offsettable_nonstrict_memref_p (op
))
1690 /* Memory operand whose address is offsettable. */
1693 && offsettable_nonstrict_memref_p (op
))
1694 || spilled_pseudo_p (op
))
1696 /* We can put constant or pseudo value into memory
1697 or make memory address offsetable to satisfy the
1699 if (CONST_POOL_OK_P (mode
, op
) || MEM_P (op
) || REG_P (op
))
1707 if (GET_CODE (op
) == CONST_DOUBLE
1708 || (GET_CODE (op
) == CONST_VECTOR
1709 && (GET_MODE_CLASS (mode
) == MODE_VECTOR_FLOAT
)))
1715 if (CONST_DOUBLE_AS_FLOAT_P (op
)
1716 && CONST_DOUBLE_OK_FOR_CONSTRAINT_P (op
, c
, p
))
1721 if (CONST_SCALAR_INT_P (op
))
1725 if (general_constant_p (op
))
1730 if (CONST_SCALAR_INT_P (op
))
1742 if (CONST_INT_P (op
)
1743 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op
), c
, p
))
1748 /* This constraint should be excluded by the fast
1755 || general_constant_p (op
)
1756 || spilled_pseudo_p (op
))
1758 /* Drop through into 'r' case. */
1762 = reg_class_subunion
[this_alternative
][GENERAL_REGS
];
1763 IOR_HARD_REG_SET (this_alternative_set
,
1764 reg_class_contents
[GENERAL_REGS
]);
1767 this_costly_alternative
1768 = (reg_class_subunion
1769 [this_costly_alternative
][GENERAL_REGS
]);
1770 IOR_HARD_REG_SET (this_costly_alternative_set
,
1771 reg_class_contents
[GENERAL_REGS
]);
1776 if (REG_CLASS_FROM_CONSTRAINT (c
, p
) == NO_REGS
)
1778 #ifdef EXTRA_CONSTRAINT_STR
1779 if (EXTRA_MEMORY_CONSTRAINT (c
, p
))
1781 if (EXTRA_CONSTRAINT_STR (op
, c
, p
))
1783 else if (spilled_pseudo_p (op
))
1786 /* If we didn't already win, we can reload
1787 constants via force_const_mem or put the
1788 pseudo value into memory, or make other
1789 memory by reloading the address like for
1791 if (CONST_POOL_OK_P (mode
, op
)
1792 || MEM_P (op
) || REG_P (op
))
1798 if (EXTRA_ADDRESS_CONSTRAINT (c
, p
))
1800 if (EXTRA_CONSTRAINT_STR (op
, c
, p
))
1803 /* If we didn't already win, we can reload
1804 the address into a base register. */
1805 cl
= base_reg_class (VOIDmode
, ADDR_SPACE_GENERIC
,
1808 = reg_class_subunion
[this_alternative
][cl
];
1809 IOR_HARD_REG_SET (this_alternative_set
,
1810 reg_class_contents
[cl
]);
1813 this_costly_alternative
1814 = (reg_class_subunion
1815 [this_costly_alternative
][cl
]);
1816 IOR_HARD_REG_SET (this_costly_alternative_set
,
1817 reg_class_contents
[cl
]);
1823 if (EXTRA_CONSTRAINT_STR (op
, c
, p
))
1829 cl
= REG_CLASS_FROM_CONSTRAINT (c
, p
);
1830 this_alternative
= reg_class_subunion
[this_alternative
][cl
];
1831 IOR_HARD_REG_SET (this_alternative_set
,
1832 reg_class_contents
[cl
]);
1835 this_costly_alternative
1836 = reg_class_subunion
[this_costly_alternative
][cl
];
1837 IOR_HARD_REG_SET (this_costly_alternative_set
,
1838 reg_class_contents
[cl
]);
1841 if (mode
== BLKmode
)
1846 if (hard_regno
[nop
] >= 0
1847 && in_hard_reg_set_p (this_alternative_set
,
1848 mode
, hard_regno
[nop
]))
1850 else if (hard_regno
[nop
] < 0
1851 && in_class_p (op
, this_alternative
, NULL
))
1856 if (c
!= ' ' && c
!= '\t')
1857 costly_p
= c
== '*';
1859 while ((p
+= len
), c
);
1861 /* Record which operands fit this alternative. */
1864 this_alternative_win
= true;
1865 if (operand_reg
[nop
] != NULL_RTX
)
1867 if (hard_regno
[nop
] >= 0)
1869 if (in_hard_reg_set_p (this_costly_alternative_set
,
1870 mode
, hard_regno
[nop
]))
1872 if (lra_dump_file
!= NULL
)
1873 fprintf (lra_dump_file
,
1874 " %d Costly set: reject++\n",
1881 /* Prefer won reg to spilled pseudo under other equal
1883 if (lra_dump_file
!= NULL
)
1886 " %d Non pseudo reload: reject++\n",
1889 if (in_class_p (operand_reg
[nop
],
1890 this_costly_alternative
, NULL
))
1892 if (lra_dump_file
!= NULL
)
1895 " %d Non pseudo costly reload:"
1901 /* We simulate the behaviour of old reload here.
1902 Although scratches need hard registers and it
1903 might result in spilling other pseudos, no reload
1904 insns are generated for the scratches. So it
1905 might cost something but probably less than old
1906 reload pass believes. */
1907 if (lra_former_scratch_p (REGNO (operand_reg
[nop
])))
1909 if (lra_dump_file
!= NULL
)
1910 fprintf (lra_dump_file
,
1911 " %d Scratch win: reject+=3\n",
1918 this_alternative_match_win
= true;
1921 int const_to_mem
= 0;
1924 /* If this alternative asks for a specific reg class, see if there
1925 is at least one allocatable register in that class. */
1927 = (this_alternative
== NO_REGS
1928 || (hard_reg_set_subset_p
1929 (reg_class_contents
[this_alternative
],
1930 lra_no_alloc_regs
)));
1932 /* For asms, verify that the class for this alternative is possible
1933 for the mode that is specified. */
1934 if (!no_regs_p
&& INSN_CODE (curr_insn
) < 0)
1937 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1938 if (HARD_REGNO_MODE_OK (i
, mode
)
1939 && in_hard_reg_set_p (reg_class_contents
[this_alternative
], mode
, i
))
1941 if (i
== FIRST_PSEUDO_REGISTER
)
1945 /* If this operand accepts a register, and if the
1946 register class has at least one allocatable register,
1947 then this operand can be reloaded. */
1948 if (winreg
&& !no_regs_p
)
1954 this_alternative_offmemok
= offmemok
;
1955 if (this_costly_alternative
!= NO_REGS
)
1957 if (lra_dump_file
!= NULL
)
1958 fprintf (lra_dump_file
,
1959 " %d Costly loser: reject++\n", nop
);
1962 /* If the operand is dying, has a matching constraint,
1963 and satisfies constraints of the matched operand
1964 which failed to satisfy the own constraints, we do
1965 not need to generate a reload insn for this
1967 if (!(this_alternative_matches
>= 0
1968 && !curr_alt_win
[this_alternative_matches
]
1970 && find_regno_note (curr_insn
, REG_DEAD
, REGNO (op
))
1971 && (hard_regno
[nop
] >= 0
1972 ? in_hard_reg_set_p (this_alternative_set
,
1973 mode
, hard_regno
[nop
])
1974 : in_class_p (op
, this_alternative
, NULL
))))
1976 /* Strict_low_part requires to reload the register
1977 not the sub-register. In this case we should
1978 check that a final reload hard reg can hold the
1980 if (curr_static_id
->operand
[nop
].strict_low
1982 && hard_regno
[nop
] < 0
1983 && GET_CODE (*curr_id
->operand_loc
[nop
]) == SUBREG
1984 && ira_class_hard_regs_num
[this_alternative
] > 0
1985 && ! HARD_REGNO_MODE_OK (ira_class_hard_regs
1986 [this_alternative
][0],
1988 (*curr_id
->operand_loc
[nop
])))
1992 if (operand_reg
[nop
] != NULL_RTX
1993 /* Output operands and matched input operands are
1994 not inherited. The following conditions do not
1995 exactly describe the previous statement but they
1996 are pretty close. */
1997 && curr_static_id
->operand
[nop
].type
!= OP_OUT
1998 && (this_alternative_matches
< 0
1999 || curr_static_id
->operand
[nop
].type
!= OP_IN
))
2001 int last_reload
= (lra_reg_info
[ORIGINAL_REGNO
2005 if (last_reload
> bb_reload_num
)
2006 reload_sum
+= last_reload
- bb_reload_num
;
2008 /* If this is a constant that is reloaded into the
2009 desired class by copying it to memory first, count
2010 that as another reload. This is consistent with
2011 other code and is required to avoid choosing another
2012 alternative when the constant is moved into memory.
2013 Note that the test here is precisely the same as in
2014 the code below that calls force_const_mem. */
2015 if (CONST_POOL_OK_P (mode
, op
)
2016 && ((targetm
.preferred_reload_class
2017 (op
, this_alternative
) == NO_REGS
)
2018 || no_input_reloads_p
))
2025 /* Alternative loses if it requires a type of reload not
2026 permitted for this insn. We can always reload
2027 objects with a REG_UNUSED note. */
2028 if ((curr_static_id
->operand
[nop
].type
!= OP_IN
2029 && no_output_reloads_p
2030 && ! find_reg_note (curr_insn
, REG_UNUSED
, op
))
2031 || (curr_static_id
->operand
[nop
].type
!= OP_OUT
2032 && no_input_reloads_p
&& ! const_to_mem
))
2035 /* Check strong discouragement of reload of non-constant
2036 into class THIS_ALTERNATIVE. */
2037 if (! CONSTANT_P (op
) && ! no_regs_p
2038 && (targetm
.preferred_reload_class
2039 (op
, this_alternative
) == NO_REGS
2040 || (curr_static_id
->operand
[nop
].type
== OP_OUT
2041 && (targetm
.preferred_output_reload_class
2042 (op
, this_alternative
) == NO_REGS
))))
2044 if (lra_dump_file
!= NULL
)
2045 fprintf (lra_dump_file
,
2046 " %d Non-prefered reload: reject+=%d\n",
2047 nop
, LRA_MAX_REJECT
);
2048 reject
+= LRA_MAX_REJECT
;
2051 if (! (MEM_P (op
) && offmemok
)
2052 && ! (const_to_mem
&& constmemok
))
2054 /* We prefer to reload pseudos over reloading other
2055 things, since such reloads may be able to be
2056 eliminated later. So bump REJECT in other cases.
2057 Don't do this in the case where we are forcing a
2058 constant into memory and it will then win since
2059 we don't want to have a different alternative
2061 if (! (REG_P (op
) && REGNO (op
) >= FIRST_PSEUDO_REGISTER
))
2063 if (lra_dump_file
!= NULL
)
2066 " %d Non-pseudo reload: reject+=2\n",
2073 += ira_reg_class_max_nregs
[this_alternative
][mode
];
2075 if (SMALL_REGISTER_CLASS_P (this_alternative
))
2077 if (lra_dump_file
!= NULL
)
2080 " %d Small class reload: reject+=%d\n",
2081 nop
, LRA_LOSER_COST_FACTOR
/ 2);
2082 reject
+= LRA_LOSER_COST_FACTOR
/ 2;
2086 /* We are trying to spill pseudo into memory. It is
2087 usually more costly than moving to a hard register
2088 although it might takes the same number of
2090 if (no_regs_p
&& REG_P (op
) && hard_regno
[nop
] >= 0)
2092 if (lra_dump_file
!= NULL
)
2095 " %d Spill pseudo in memory: reject+=3\n",
2100 #ifdef SECONDARY_MEMORY_NEEDED
2101 /* If reload requires moving value through secondary
2102 memory, it will need one more insn at least. */
2103 if (this_alternative
!= NO_REGS
2104 && REG_P (op
) && (cl
= get_reg_class (REGNO (op
))) != NO_REGS
2105 && ((curr_static_id
->operand
[nop
].type
!= OP_OUT
2106 && SECONDARY_MEMORY_NEEDED (cl
, this_alternative
,
2108 || (curr_static_id
->operand
[nop
].type
!= OP_IN
2109 && SECONDARY_MEMORY_NEEDED (this_alternative
, cl
,
2113 /* Input reloads can be inherited more often than output
2114 reloads can be removed, so penalize output
2116 if (!REG_P (op
) || curr_static_id
->operand
[nop
].type
!= OP_IN
)
2118 if (lra_dump_file
!= NULL
)
2121 " %d Non input pseudo reload: reject++\n",
2127 if (early_clobber_p
)
2129 if (lra_dump_file
!= NULL
)
2130 fprintf (lra_dump_file
,
2131 " %d Early clobber: reject++\n", nop
);
2134 /* ??? We check early clobbers after processing all operands
2135 (see loop below) and there we update the costs more.
2136 Should we update the cost (may be approximately) here
2137 because of early clobber register reloads or it is a rare
2138 or non-important thing to be worth to do it. */
2139 overall
= losers
* LRA_LOSER_COST_FACTOR
+ reject
;
2140 if ((best_losers
== 0 || losers
!= 0) && best_overall
< overall
)
2142 if (lra_dump_file
!= NULL
)
2143 fprintf (lra_dump_file
,
2144 " alt=%d,overall=%d,losers=%d -- refuse\n",
2145 nalt
, overall
, losers
);
2149 curr_alt
[nop
] = this_alternative
;
2150 COPY_HARD_REG_SET (curr_alt_set
[nop
], this_alternative_set
);
2151 curr_alt_win
[nop
] = this_alternative_win
;
2152 curr_alt_match_win
[nop
] = this_alternative_match_win
;
2153 curr_alt_offmemok
[nop
] = this_alternative_offmemok
;
2154 curr_alt_matches
[nop
] = this_alternative_matches
;
2156 if (this_alternative_matches
>= 0
2157 && !did_match
&& !this_alternative_win
)
2158 curr_alt_win
[this_alternative_matches
] = false;
2160 if (early_clobber_p
&& operand_reg
[nop
] != NULL_RTX
)
2161 early_clobbered_nops
[early_clobbered_regs_num
++] = nop
;
2163 if (curr_insn_set
!= NULL_RTX
&& n_operands
== 2
2164 /* Prevent processing non-move insns. */
2165 && (GET_CODE (SET_SRC (curr_insn_set
)) == SUBREG
2166 || SET_SRC (curr_insn_set
) == no_subreg_reg_operand
[1])
2167 && ((! curr_alt_win
[0] && ! curr_alt_win
[1]
2168 && REG_P (no_subreg_reg_operand
[0])
2169 && REG_P (no_subreg_reg_operand
[1])
2170 && (reg_in_class_p (no_subreg_reg_operand
[0], curr_alt
[1])
2171 || reg_in_class_p (no_subreg_reg_operand
[1], curr_alt
[0])))
2172 || (! curr_alt_win
[0] && curr_alt_win
[1]
2173 && REG_P (no_subreg_reg_operand
[1])
2174 && reg_in_class_p (no_subreg_reg_operand
[1], curr_alt
[0]))
2175 || (curr_alt_win
[0] && ! curr_alt_win
[1]
2176 && REG_P (no_subreg_reg_operand
[0])
2177 && reg_in_class_p (no_subreg_reg_operand
[0], curr_alt
[1])
2178 && (! CONST_POOL_OK_P (curr_operand_mode
[1],
2179 no_subreg_reg_operand
[1])
2180 || (targetm
.preferred_reload_class
2181 (no_subreg_reg_operand
[1],
2182 (enum reg_class
) curr_alt
[1]) != NO_REGS
))
2183 /* If it is a result of recent elimination in move
2184 insn we can transform it into an add still by
2185 using this alternative. */
2186 && GET_CODE (no_subreg_reg_operand
[1]) != PLUS
)))
2188 /* We have a move insn and a new reload insn will be similar
2189 to the current insn. We should avoid such situation as it
2190 results in LRA cycling. */
2191 overall
+= LRA_MAX_REJECT
;
2194 curr_alt_dont_inherit_ops_num
= 0;
2195 for (nop
= 0; nop
< early_clobbered_regs_num
; nop
++)
2197 int i
, j
, clobbered_hard_regno
, first_conflict_j
, last_conflict_j
;
2198 HARD_REG_SET temp_set
;
2200 i
= early_clobbered_nops
[nop
];
2201 if ((! curr_alt_win
[i
] && ! curr_alt_match_win
[i
])
2202 || hard_regno
[i
] < 0)
2204 lra_assert (operand_reg
[i
] != NULL_RTX
);
2205 clobbered_hard_regno
= hard_regno
[i
];
2206 CLEAR_HARD_REG_SET (temp_set
);
2207 add_to_hard_reg_set (&temp_set
, biggest_mode
[i
], clobbered_hard_regno
);
2208 first_conflict_j
= last_conflict_j
= -1;
2209 for (j
= 0; j
< n_operands
; j
++)
2211 /* We don't want process insides of match_operator and
2212 match_parallel because otherwise we would process
2213 their operands once again generating a wrong
2215 || curr_static_id
->operand
[j
].is_operator
)
2217 else if ((curr_alt_matches
[j
] == i
&& curr_alt_match_win
[j
])
2218 || (curr_alt_matches
[i
] == j
&& curr_alt_match_win
[i
]))
2220 /* If we don't reload j-th operand, check conflicts. */
2221 else if ((curr_alt_win
[j
] || curr_alt_match_win
[j
])
2222 && uses_hard_regs_p (*curr_id
->operand_loc
[j
], temp_set
))
2224 if (first_conflict_j
< 0)
2225 first_conflict_j
= j
;
2226 last_conflict_j
= j
;
2228 if (last_conflict_j
< 0)
2230 /* If earlyclobber operand conflicts with another
2231 non-matching operand which is actually the same register
2232 as the earlyclobber operand, it is better to reload the
2233 another operand as an operand matching the earlyclobber
2234 operand can be also the same. */
2235 if (first_conflict_j
== last_conflict_j
2236 && operand_reg
[last_conflict_j
]
2237 != NULL_RTX
&& ! curr_alt_match_win
[last_conflict_j
]
2238 && REGNO (operand_reg
[i
]) == REGNO (operand_reg
[last_conflict_j
]))
2240 curr_alt_win
[last_conflict_j
] = false;
2241 curr_alt_dont_inherit_ops
[curr_alt_dont_inherit_ops_num
++]
2244 /* Early clobber was already reflected in REJECT. */
2245 lra_assert (reject
> 0);
2246 if (lra_dump_file
!= NULL
)
2249 " %d Conflict early clobber reload: reject--\n",
2252 overall
+= LRA_LOSER_COST_FACTOR
- 1;
2256 /* We need to reload early clobbered register and the
2257 matched registers. */
2258 for (j
= 0; j
< n_operands
; j
++)
2259 if (curr_alt_matches
[j
] == i
)
2261 curr_alt_match_win
[j
] = false;
2263 overall
+= LRA_LOSER_COST_FACTOR
;
2265 if (! curr_alt_match_win
[i
])
2266 curr_alt_dont_inherit_ops
[curr_alt_dont_inherit_ops_num
++] = i
;
2269 /* Remember pseudos used for match reloads are never
2271 lra_assert (curr_alt_matches
[i
] >= 0);
2272 curr_alt_win
[curr_alt_matches
[i
]] = false;
2274 curr_alt_win
[i
] = curr_alt_match_win
[i
] = false;
2276 /* Early clobber was already reflected in REJECT. */
2277 lra_assert (reject
> 0);
2278 if (lra_dump_file
!= NULL
)
2281 " %d Matched conflict early clobber reloads:"
2285 overall
+= LRA_LOSER_COST_FACTOR
- 1;
2288 if (lra_dump_file
!= NULL
)
2289 fprintf (lra_dump_file
, " alt=%d,overall=%d,losers=%d,rld_nregs=%d\n",
2290 nalt
, overall
, losers
, reload_nregs
);
2292 /* If this alternative can be made to work by reloading, and it
2293 needs less reloading than the others checked so far, record
2294 it as the chosen goal for reloading. */
2295 if ((best_losers
!= 0 && losers
== 0)
2296 || (((best_losers
== 0 && losers
== 0)
2297 || (best_losers
!= 0 && losers
!= 0))
2298 && (best_overall
> overall
2299 || (best_overall
== overall
2300 /* If the cost of the reloads is the same,
2301 prefer alternative which requires minimal
2302 number of reload regs. */
2303 && (reload_nregs
< best_reload_nregs
2304 || (reload_nregs
== best_reload_nregs
2305 && (best_reload_sum
< reload_sum
2306 || (best_reload_sum
== reload_sum
2307 && nalt
< goal_alt_number
))))))))
2309 for (nop
= 0; nop
< n_operands
; nop
++)
2311 goal_alt_win
[nop
] = curr_alt_win
[nop
];
2312 goal_alt_match_win
[nop
] = curr_alt_match_win
[nop
];
2313 goal_alt_matches
[nop
] = curr_alt_matches
[nop
];
2314 goal_alt
[nop
] = curr_alt
[nop
];
2315 goal_alt_offmemok
[nop
] = curr_alt_offmemok
[nop
];
2317 goal_alt_dont_inherit_ops_num
= curr_alt_dont_inherit_ops_num
;
2318 for (nop
= 0; nop
< curr_alt_dont_inherit_ops_num
; nop
++)
2319 goal_alt_dont_inherit_ops
[nop
] = curr_alt_dont_inherit_ops
[nop
];
2320 goal_alt_swapped
= curr_swapped
;
2321 best_overall
= overall
;
2322 best_losers
= losers
;
2323 best_reload_nregs
= reload_nregs
;
2324 best_reload_sum
= reload_sum
;
2325 goal_alt_number
= nalt
;
2328 /* Everything is satisfied. Do not process alternatives
2337 /* Return 1 if ADDR is a valid memory address for mode MODE in address
2338 space AS, and check that each pseudo has the proper kind of hard
2341 valid_address_p (enum machine_mode mode ATTRIBUTE_UNUSED
,
2342 rtx addr
, addr_space_t as
)
2344 #ifdef GO_IF_LEGITIMATE_ADDRESS
2345 lra_assert (ADDR_SPACE_GENERIC_P (as
));
2346 GO_IF_LEGITIMATE_ADDRESS (mode
, addr
, win
);
2352 return targetm
.addr_space
.legitimate_address_p (mode
, addr
, 0, as
);
2356 /* Return whether address AD is valid. */
2359 valid_address_p (struct address_info
*ad
)
2361 /* Some ports do not check displacements for eliminable registers,
2362 so we replace them temporarily with the elimination target. */
2363 rtx saved_base_reg
= NULL_RTX
;
2364 rtx saved_index_reg
= NULL_RTX
;
2365 rtx
*base_term
= strip_subreg (ad
->base_term
);
2366 rtx
*index_term
= strip_subreg (ad
->index_term
);
2367 if (base_term
!= NULL
)
2369 saved_base_reg
= *base_term
;
2370 lra_eliminate_reg_if_possible (base_term
);
2371 if (ad
->base_term2
!= NULL
)
2372 *ad
->base_term2
= *ad
->base_term
;
2374 if (index_term
!= NULL
)
2376 saved_index_reg
= *index_term
;
2377 lra_eliminate_reg_if_possible (index_term
);
2379 bool ok_p
= valid_address_p (ad
->mode
, *ad
->outer
, ad
->as
);
2380 if (saved_base_reg
!= NULL_RTX
)
2382 *base_term
= saved_base_reg
;
2383 if (ad
->base_term2
!= NULL
)
2384 *ad
->base_term2
= *ad
->base_term
;
2386 if (saved_index_reg
!= NULL_RTX
)
2387 *index_term
= saved_index_reg
;
2391 /* Make reload base reg + disp from address AD. Return the new pseudo. */
2393 base_plus_disp_to_reg (struct address_info
*ad
)
2398 lra_assert (ad
->base
== ad
->base_term
&& ad
->disp
== ad
->disp_term
);
2399 cl
= base_reg_class (ad
->mode
, ad
->as
, ad
->base_outer_code
,
2400 get_index_code (ad
));
2401 new_reg
= lra_create_new_reg (GET_MODE (*ad
->base_term
), NULL_RTX
,
2403 lra_emit_add (new_reg
, *ad
->base_term
, *ad
->disp_term
);
2407 /* Return true if we can add a displacement to address AD, even if that
2408 makes the address invalid. The fix-up code requires any new address
2409 to be the sum of the BASE_TERM, INDEX and DISP_TERM fields. */
2411 can_add_disp_p (struct address_info
*ad
)
2413 return (!ad
->autoinc_p
2414 && ad
->segment
== NULL
2415 && ad
->base
== ad
->base_term
2416 && ad
->disp
== ad
->disp_term
);
2419 /* Make equiv substitution in address AD. Return true if a substitution
2422 equiv_address_substitution (struct address_info
*ad
)
2424 rtx base_reg
, new_base_reg
, index_reg
, new_index_reg
, *base_term
, *index_term
;
2425 HOST_WIDE_INT disp
, scale
;
2428 base_term
= strip_subreg (ad
->base_term
);
2429 if (base_term
== NULL
)
2430 base_reg
= new_base_reg
= NULL_RTX
;
2433 base_reg
= *base_term
;
2434 new_base_reg
= get_equiv_substitution (base_reg
);
2436 index_term
= strip_subreg (ad
->index_term
);
2437 if (index_term
== NULL
)
2438 index_reg
= new_index_reg
= NULL_RTX
;
2441 index_reg
= *index_term
;
2442 new_index_reg
= get_equiv_substitution (index_reg
);
2444 if (base_reg
== new_base_reg
&& index_reg
== new_index_reg
)
2448 if (lra_dump_file
!= NULL
)
2450 fprintf (lra_dump_file
, "Changing address in insn %d ",
2451 INSN_UID (curr_insn
));
2452 dump_value_slim (lra_dump_file
, *ad
->outer
, 1);
2454 if (base_reg
!= new_base_reg
)
2456 if (REG_P (new_base_reg
))
2458 *base_term
= new_base_reg
;
2461 else if (GET_CODE (new_base_reg
) == PLUS
2462 && REG_P (XEXP (new_base_reg
, 0))
2463 && CONST_INT_P (XEXP (new_base_reg
, 1))
2464 && can_add_disp_p (ad
))
2466 disp
+= INTVAL (XEXP (new_base_reg
, 1));
2467 *base_term
= XEXP (new_base_reg
, 0);
2470 if (ad
->base_term2
!= NULL
)
2471 *ad
->base_term2
= *ad
->base_term
;
2473 if (index_reg
!= new_index_reg
)
2475 if (REG_P (new_index_reg
))
2477 *index_term
= new_index_reg
;
2480 else if (GET_CODE (new_index_reg
) == PLUS
2481 && REG_P (XEXP (new_index_reg
, 0))
2482 && CONST_INT_P (XEXP (new_index_reg
, 1))
2483 && can_add_disp_p (ad
)
2484 && (scale
= get_index_scale (ad
)))
2486 disp
+= INTVAL (XEXP (new_index_reg
, 1)) * scale
;
2487 *index_term
= XEXP (new_index_reg
, 0);
2493 if (ad
->disp
!= NULL
)
2494 *ad
->disp
= plus_constant (GET_MODE (*ad
->inner
), *ad
->disp
, disp
);
2497 *ad
->inner
= plus_constant (GET_MODE (*ad
->inner
), *ad
->inner
, disp
);
2498 update_address (ad
);
2502 if (lra_dump_file
!= NULL
)
2505 fprintf (lra_dump_file
, " -- no change\n");
2508 fprintf (lra_dump_file
, " on equiv ");
2509 dump_value_slim (lra_dump_file
, *ad
->outer
, 1);
2510 fprintf (lra_dump_file
, "\n");
2516 /* Major function to make reloads for an address in operand NOP.
2517 The supported cases are:
2519 1) an address that existed before LRA started, at which point it
2520 must have been valid. These addresses are subject to elimination
2521 and may have become invalid due to the elimination offset being out
2524 2) an address created by forcing a constant to memory
2525 (force_const_to_mem). The initial form of these addresses might
2526 not be valid, and it is this function's job to make them valid.
2528 3) a frame address formed from a register and a (possibly zero)
2529 constant offset. As above, these addresses might not be valid and
2530 this function must make them so.
2532 Add reloads to the lists *BEFORE and *AFTER. We might need to add
2533 reloads to *AFTER because of inc/dec, {pre, post} modify in the
2534 address. Return true for any RTL change. */
2536 process_address (int nop
, rtx
*before
, rtx
*after
)
2538 struct address_info ad
;
2540 rtx op
= *curr_id
->operand_loc
[nop
];
2541 const char *constraint
= curr_static_id
->operand
[nop
].constraint
;
2544 if (constraint
[0] == 'p'
2545 || EXTRA_ADDRESS_CONSTRAINT (constraint
[0], constraint
))
2546 decompose_lea_address (&ad
, curr_id
->operand_loc
[nop
]);
2547 else if (MEM_P (op
))
2548 decompose_mem_address (&ad
, op
);
2549 else if (GET_CODE (op
) == SUBREG
2550 && MEM_P (SUBREG_REG (op
)))
2551 decompose_mem_address (&ad
, SUBREG_REG (op
));
2554 change_p
= equiv_address_substitution (&ad
);
2555 if (ad
.base_term
!= NULL
2556 && (process_addr_reg
2557 (ad
.base_term
, before
,
2559 && !(REG_P (*ad
.base_term
)
2560 && find_regno_note (curr_insn
, REG_DEAD
,
2561 REGNO (*ad
.base_term
)) != NULL_RTX
)
2563 base_reg_class (ad
.mode
, ad
.as
, ad
.base_outer_code
,
2564 get_index_code (&ad
)))))
2567 if (ad
.base_term2
!= NULL
)
2568 *ad
.base_term2
= *ad
.base_term
;
2570 if (ad
.index_term
!= NULL
2571 && process_addr_reg (ad
.index_term
, before
, NULL
, INDEX_REG_CLASS
))
2574 #ifdef EXTRA_CONSTRAINT_STR
2575 /* Target hooks sometimes reject extra constraint addresses -- use
2576 EXTRA_CONSTRAINT_STR for the validation. */
2577 if (constraint
[0] != 'p'
2578 && EXTRA_ADDRESS_CONSTRAINT (constraint
[0], constraint
)
2579 && EXTRA_CONSTRAINT_STR (op
, constraint
[0], constraint
))
2583 /* There are three cases where the shape of *AD.INNER may now be invalid:
2585 1) the original address was valid, but either elimination or
2586 equiv_address_substitution was applied and that made
2587 the address invalid.
2589 2) the address is an invalid symbolic address created by
2592 3) the address is a frame address with an invalid offset.
2594 All these cases involve a non-autoinc address, so there is no
2595 point revalidating other types. */
2596 if (ad
.autoinc_p
|| valid_address_p (&ad
))
2599 /* Any index existed before LRA started, so we can assume that the
2600 presence and shape of the index is valid. */
2601 push_to_sequence (*before
);
2602 lra_assert (ad
.disp
== ad
.disp_term
);
2603 if (ad
.base
== NULL
)
2605 if (ad
.index
== NULL
)
2608 enum reg_class cl
= base_reg_class (ad
.mode
, ad
.as
,
2610 rtx addr
= *ad
.inner
;
2612 new_reg
= lra_create_new_reg (Pmode
, NULL_RTX
, cl
, "addr");
2616 rtx last
= get_last_insn ();
2618 /* addr => lo_sum (new_base, addr), case (2) above. */
2619 insn
= emit_insn (gen_rtx_SET
2621 gen_rtx_HIGH (Pmode
, copy_rtx (addr
))));
2622 code
= recog_memoized (insn
);
2625 *ad
.inner
= gen_rtx_LO_SUM (Pmode
, new_reg
, addr
);
2626 if (! valid_address_p (ad
.mode
, *ad
.outer
, ad
.as
))
2628 /* Try to put lo_sum into register. */
2629 insn
= emit_insn (gen_rtx_SET
2631 gen_rtx_LO_SUM (Pmode
, new_reg
, addr
)));
2632 code
= recog_memoized (insn
);
2635 *ad
.inner
= new_reg
;
2636 if (! valid_address_p (ad
.mode
, *ad
.outer
, ad
.as
))
2646 delete_insns_since (last
);
2651 /* addr => new_base, case (2) above. */
2652 lra_emit_move (new_reg
, addr
);
2653 *ad
.inner
= new_reg
;
2658 /* index * scale + disp => new base + index * scale,
2660 enum reg_class cl
= base_reg_class (ad
.mode
, ad
.as
, PLUS
,
2661 GET_CODE (*ad
.index
));
2663 lra_assert (INDEX_REG_CLASS
!= NO_REGS
);
2664 new_reg
= lra_create_new_reg (Pmode
, NULL_RTX
, cl
, "disp");
2665 lra_emit_move (new_reg
, *ad
.disp
);
2666 *ad
.inner
= simplify_gen_binary (PLUS
, GET_MODE (new_reg
),
2667 new_reg
, *ad
.index
);
2670 else if (ad
.index
== NULL
)
2674 rtx set
, insns
, last_insn
;
2675 /* base + disp => new base, cases (1) and (3) above. */
2676 /* Another option would be to reload the displacement into an
2677 index register. However, postreload has code to optimize
2678 address reloads that have the same base and different
2679 displacements, so reloading into an index register would
2680 not necessarily be a win. */
2682 new_reg
= base_plus_disp_to_reg (&ad
);
2683 insns
= get_insns ();
2684 last_insn
= get_last_insn ();
2685 /* If we generated at least two insns, try last insn source as
2686 an address. If we succeed, we generate one less insn. */
2687 if (last_insn
!= insns
&& (set
= single_set (last_insn
)) != NULL_RTX
2688 && GET_CODE (SET_SRC (set
)) == PLUS
2689 && REG_P (XEXP (SET_SRC (set
), 0))
2690 && CONSTANT_P (XEXP (SET_SRC (set
), 1)))
2692 *ad
.inner
= SET_SRC (set
);
2693 if (valid_address_p (ad
.mode
, *ad
.outer
, ad
.as
))
2695 *ad
.base_term
= XEXP (SET_SRC (set
), 0);
2696 *ad
.disp_term
= XEXP (SET_SRC (set
), 1);
2697 cl
= base_reg_class (ad
.mode
, ad
.as
, ad
.base_outer_code
,
2698 get_index_code (&ad
));
2699 regno
= REGNO (*ad
.base_term
);
2700 if (regno
>= FIRST_PSEUDO_REGISTER
2701 && cl
!= lra_get_allocno_class (regno
))
2702 change_class (regno
, cl
, " Change", true);
2703 new_reg
= SET_SRC (set
);
2704 delete_insns_since (PREV_INSN (last_insn
));
2709 *ad
.inner
= new_reg
;
2713 /* base + scale * index + disp => new base + scale * index,
2715 new_reg
= base_plus_disp_to_reg (&ad
);
2716 *ad
.inner
= simplify_gen_binary (PLUS
, GET_MODE (new_reg
),
2717 new_reg
, *ad
.index
);
2719 *before
= get_insns ();
2724 /* Emit insns to reload VALUE into a new register. VALUE is an
2725 auto-increment or auto-decrement RTX whose operand is a register or
2726 memory location; so reloading involves incrementing that location.
2727 IN is either identical to VALUE, or some cheaper place to reload
2728 value being incremented/decremented from.
2730 INC_AMOUNT is the number to increment or decrement by (always
2731 positive and ignored for POST_MODIFY/PRE_MODIFY).
2733 Return pseudo containing the result. */
2735 emit_inc (enum reg_class new_rclass
, rtx in
, rtx value
, int inc_amount
)
2737 /* REG or MEM to be copied and incremented. */
2738 rtx incloc
= XEXP (value
, 0);
2739 /* Nonzero if increment after copying. */
2740 int post
= (GET_CODE (value
) == POST_DEC
|| GET_CODE (value
) == POST_INC
2741 || GET_CODE (value
) == POST_MODIFY
);
2746 rtx real_in
= in
== value
? incloc
: in
;
2750 if (GET_CODE (value
) == PRE_MODIFY
|| GET_CODE (value
) == POST_MODIFY
)
2752 lra_assert (GET_CODE (XEXP (value
, 1)) == PLUS
2753 || GET_CODE (XEXP (value
, 1)) == MINUS
);
2754 lra_assert (rtx_equal_p (XEXP (XEXP (value
, 1), 0), XEXP (value
, 0)));
2755 plus_p
= GET_CODE (XEXP (value
, 1)) == PLUS
;
2756 inc
= XEXP (XEXP (value
, 1), 1);
2760 if (GET_CODE (value
) == PRE_DEC
|| GET_CODE (value
) == POST_DEC
)
2761 inc_amount
= -inc_amount
;
2763 inc
= GEN_INT (inc_amount
);
2766 if (! post
&& REG_P (incloc
))
2769 result
= lra_create_new_reg (GET_MODE (value
), value
, new_rclass
,
2772 if (real_in
!= result
)
2774 /* First copy the location to the result register. */
2775 lra_assert (REG_P (result
));
2776 emit_insn (gen_move_insn (result
, real_in
));
2779 /* We suppose that there are insns to add/sub with the constant
2780 increment permitted in {PRE/POST)_{DEC/INC/MODIFY}. At least the
2781 old reload worked with this assumption. If the assumption
2782 becomes wrong, we should use approach in function
2783 base_plus_disp_to_reg. */
2786 /* See if we can directly increment INCLOC. */
2787 last
= get_last_insn ();
2788 add_insn
= emit_insn (plus_p
2789 ? gen_add2_insn (incloc
, inc
)
2790 : gen_sub2_insn (incloc
, inc
));
2792 code
= recog_memoized (add_insn
);
2795 if (! post
&& result
!= incloc
)
2796 emit_insn (gen_move_insn (result
, incloc
));
2799 delete_insns_since (last
);
2802 /* If couldn't do the increment directly, must increment in RESULT.
2803 The way we do this depends on whether this is pre- or
2804 post-increment. For pre-increment, copy INCLOC to the reload
2805 register, increment it there, then save back. */
2808 if (real_in
!= result
)
2809 emit_insn (gen_move_insn (result
, real_in
));
2811 emit_insn (gen_add2_insn (result
, inc
));
2813 emit_insn (gen_sub2_insn (result
, inc
));
2814 if (result
!= incloc
)
2815 emit_insn (gen_move_insn (incloc
, result
));
2821 Because this might be a jump insn or a compare, and because
2822 RESULT may not be available after the insn in an input
2823 reload, we must do the incrementing before the insn being
2826 We have already copied IN to RESULT. Increment the copy in
2827 RESULT, save that back, then decrement RESULT so it has
2828 the original value. */
2830 emit_insn (gen_add2_insn (result
, inc
));
2832 emit_insn (gen_sub2_insn (result
, inc
));
2833 emit_insn (gen_move_insn (incloc
, result
));
2834 /* Restore non-modified value for the result. We prefer this
2835 way because it does not require an additional hard
2839 if (CONST_INT_P (inc
))
2840 emit_insn (gen_add2_insn (result
,
2841 gen_int_mode (-INTVAL (inc
),
2842 GET_MODE (result
))));
2844 emit_insn (gen_sub2_insn (result
, inc
));
2847 emit_insn (gen_add2_insn (result
, inc
));
2852 /* Return true if the current move insn does not need processing as we
2853 already know that it satisfies its constraints. */
2855 simple_move_p (void)
2858 enum reg_class dclass
, sclass
;
2860 lra_assert (curr_insn_set
!= NULL_RTX
);
2861 dest
= SET_DEST (curr_insn_set
);
2862 src
= SET_SRC (curr_insn_set
);
2863 return ((dclass
= get_op_class (dest
)) != NO_REGS
2864 && (sclass
= get_op_class (src
)) != NO_REGS
2865 /* The backend guarantees that register moves of cost 2
2866 never need reloads. */
2867 && targetm
.register_move_cost (GET_MODE (src
), dclass
, sclass
) == 2);
2870 /* Swap operands NOP and NOP + 1. */
2872 swap_operands (int nop
)
2874 enum machine_mode mode
= curr_operand_mode
[nop
];
2875 curr_operand_mode
[nop
] = curr_operand_mode
[nop
+ 1];
2876 curr_operand_mode
[nop
+ 1] = mode
;
2877 rtx x
= *curr_id
->operand_loc
[nop
];
2878 *curr_id
->operand_loc
[nop
] = *curr_id
->operand_loc
[nop
+ 1];
2879 *curr_id
->operand_loc
[nop
+ 1] = x
;
2880 /* Swap the duplicates too. */
2881 lra_update_dup (curr_id
, nop
);
2882 lra_update_dup (curr_id
, nop
+ 1);
2885 /* Main entry point of the constraint code: search the body of the
2886 current insn to choose the best alternative. It is mimicking insn
2887 alternative cost calculation model of former reload pass. That is
2888 because machine descriptions were written to use this model. This
2889 model can be changed in future. Make commutative operand exchange
2892 Return true if some RTL changes happened during function call. */
2894 curr_insn_transform (void)
2900 signed char goal_alt_matched
[MAX_RECOG_OPERANDS
][MAX_RECOG_OPERANDS
];
2901 signed char match_inputs
[MAX_RECOG_OPERANDS
+ 1];
2904 /* Flag that the insn has been changed through a transformation. */
2907 #ifdef SECONDARY_MEMORY_NEEDED
2910 int max_regno_before
;
2911 int reused_alternative_num
;
2913 curr_insn_set
= single_set (curr_insn
);
2914 if (curr_insn_set
!= NULL_RTX
&& simple_move_p ())
2917 no_input_reloads_p
= no_output_reloads_p
= false;
2918 goal_alt_number
= -1;
2919 change_p
= sec_mem_p
= false;
2920 /* JUMP_INSNs and CALL_INSNs are not allowed to have any output
2921 reloads; neither are insns that SET cc0. Insns that use CC0 are
2922 not allowed to have any input reloads. */
2923 if (JUMP_P (curr_insn
) || CALL_P (curr_insn
))
2924 no_output_reloads_p
= true;
2927 if (reg_referenced_p (cc0_rtx
, PATTERN (curr_insn
)))
2928 no_input_reloads_p
= true;
2929 if (reg_set_p (cc0_rtx
, PATTERN (curr_insn
)))
2930 no_output_reloads_p
= true;
2933 n_operands
= curr_static_id
->n_operands
;
2934 n_alternatives
= curr_static_id
->n_alternatives
;
2936 /* Just return "no reloads" if insn has no operands with
2938 if (n_operands
== 0 || n_alternatives
== 0)
2941 max_regno_before
= max_reg_num ();
2943 for (i
= 0; i
< n_operands
; i
++)
2945 goal_alt_matched
[i
][0] = -1;
2946 goal_alt_matches
[i
] = -1;
2949 commutative
= curr_static_id
->commutative
;
2951 /* Now see what we need for pseudos that didn't get hard regs or got
2952 the wrong kind of hard reg. For this, we must consider all the
2953 operands together against the register constraints. */
2955 best_losers
= best_overall
= INT_MAX
;
2956 best_reload_sum
= 0;
2958 curr_swapped
= false;
2959 goal_alt_swapped
= false;
2961 /* Make equivalence substitution and memory subreg elimination
2962 before address processing because an address legitimacy can
2963 depend on memory mode. */
2964 for (i
= 0; i
< n_operands
; i
++)
2966 rtx op
= *curr_id
->operand_loc
[i
];
2967 rtx subst
, old
= op
;
2968 bool op_change_p
= false;
2970 if (GET_CODE (old
) == SUBREG
)
2971 old
= SUBREG_REG (old
);
2972 subst
= get_equiv_substitution (old
);
2975 subst
= copy_rtx (subst
);
2976 lra_assert (REG_P (old
));
2977 if (GET_CODE (op
) == SUBREG
)
2978 SUBREG_REG (op
) = subst
;
2980 *curr_id
->operand_loc
[i
] = subst
;
2981 if (lra_dump_file
!= NULL
)
2983 fprintf (lra_dump_file
,
2984 "Changing pseudo %d in operand %i of insn %u on equiv ",
2985 REGNO (old
), i
, INSN_UID (curr_insn
));
2986 dump_value_slim (lra_dump_file
, subst
, 1);
2987 fprintf (lra_dump_file
, "\n");
2989 op_change_p
= change_p
= true;
2991 if (simplify_operand_subreg (i
, GET_MODE (old
)) || op_change_p
)
2994 lra_update_dup (curr_id
, i
);
2998 /* Reload address registers and displacements. We do it before
2999 finding an alternative because of memory constraints. */
3000 before
= after
= NULL_RTX
;
3001 for (i
= 0; i
< n_operands
; i
++)
3002 if (! curr_static_id
->operand
[i
].is_operator
3003 && process_address (i
, &before
, &after
))
3006 lra_update_dup (curr_id
, i
);
3010 /* If we've changed the instruction then any alternative that
3011 we chose previously may no longer be valid. */
3012 lra_set_used_insn_alternative (curr_insn
, -1);
3014 if (curr_insn_set
!= NULL_RTX
3015 && check_and_process_move (&change_p
, &sec_mem_p
))
3020 reused_alternative_num
= curr_id
->used_insn_alternative
;
3021 if (lra_dump_file
!= NULL
&& reused_alternative_num
>= 0)
3022 fprintf (lra_dump_file
, "Reusing alternative %d for insn #%u\n",
3023 reused_alternative_num
, INSN_UID (curr_insn
));
3025 if (process_alt_operands (reused_alternative_num
))
3028 /* If insn is commutative (it's safe to exchange a certain pair of
3029 operands) then we need to try each alternative twice, the second
3030 time matching those two operands as if we had exchanged them. To
3031 do this, really exchange them in operands.
3033 If we have just tried the alternatives the second time, return
3034 operands to normal and drop through. */
3036 if (reused_alternative_num
< 0 && commutative
>= 0)
3038 curr_swapped
= !curr_swapped
;
3041 swap_operands (commutative
);
3045 swap_operands (commutative
);
3048 if (! alt_p
&& ! sec_mem_p
)
3050 /* No alternative works with reloads?? */
3051 if (INSN_CODE (curr_insn
) >= 0)
3052 fatal_insn ("unable to generate reloads for:", curr_insn
);
3053 error_for_asm (curr_insn
,
3054 "inconsistent operand constraints in an %<asm%>");
3055 /* Avoid further trouble with this insn. */
3056 PATTERN (curr_insn
) = gen_rtx_USE (VOIDmode
, const0_rtx
);
3057 lra_invalidate_insn_data (curr_insn
);
3061 /* If the best alternative is with operands 1 and 2 swapped, swap
3062 them. Update the operand numbers of any reloads already
3065 if (goal_alt_swapped
)
3067 if (lra_dump_file
!= NULL
)
3068 fprintf (lra_dump_file
, " Commutative operand exchange in insn %u\n",
3069 INSN_UID (curr_insn
));
3071 /* Swap the duplicates too. */
3072 swap_operands (commutative
);
3076 #ifdef SECONDARY_MEMORY_NEEDED
3077 /* Some target macros SECONDARY_MEMORY_NEEDED (e.g. x86) are defined
3078 too conservatively. So we use the secondary memory only if there
3079 is no any alternative without reloads. */
3080 use_sec_mem_p
= false;
3082 use_sec_mem_p
= true;
3085 for (i
= 0; i
< n_operands
; i
++)
3086 if (! goal_alt_win
[i
] && ! goal_alt_match_win
[i
])
3088 use_sec_mem_p
= i
< n_operands
;
3093 rtx new_reg
, src
, dest
, rld
;
3094 enum machine_mode sec_mode
, rld_mode
;
3096 lra_assert (sec_mem_p
);
3097 lra_assert (curr_static_id
->operand
[0].type
== OP_OUT
3098 && curr_static_id
->operand
[1].type
== OP_IN
);
3099 dest
= *curr_id
->operand_loc
[0];
3100 src
= *curr_id
->operand_loc
[1];
3101 rld
= (GET_MODE_SIZE (GET_MODE (dest
)) <= GET_MODE_SIZE (GET_MODE (src
))
3103 rld_mode
= GET_MODE (rld
);
3104 #ifdef SECONDARY_MEMORY_NEEDED_MODE
3105 sec_mode
= SECONDARY_MEMORY_NEEDED_MODE (rld_mode
);
3107 sec_mode
= rld_mode
;
3109 new_reg
= lra_create_new_reg (sec_mode
, NULL_RTX
,
3110 NO_REGS
, "secondary");
3111 /* If the mode is changed, it should be wider. */
3112 lra_assert (GET_MODE_SIZE (sec_mode
) >= GET_MODE_SIZE (rld_mode
));
3113 if (sec_mode
!= rld_mode
)
3115 /* If the target says specifically to use another mode for
3116 secondary memory moves we can not reuse the original
3118 after
= emit_spill_move (false, new_reg
, dest
);
3119 lra_process_new_insns (curr_insn
, NULL_RTX
, after
,
3120 "Inserting the sec. move");
3121 /* We may have non null BEFORE here (e.g. after address
3123 push_to_sequence (before
);
3124 before
= emit_spill_move (true, new_reg
, src
);
3126 before
= get_insns ();
3128 lra_process_new_insns (curr_insn
, before
, NULL_RTX
, "Changing on");
3129 lra_set_insn_deleted (curr_insn
);
3131 else if (dest
== rld
)
3133 *curr_id
->operand_loc
[0] = new_reg
;
3134 after
= emit_spill_move (false, new_reg
, dest
);
3135 lra_process_new_insns (curr_insn
, NULL_RTX
, after
,
3136 "Inserting the sec. move");
3140 *curr_id
->operand_loc
[1] = new_reg
;
3141 /* See comments above. */
3142 push_to_sequence (before
);
3143 before
= emit_spill_move (true, new_reg
, src
);
3145 before
= get_insns ();
3147 lra_process_new_insns (curr_insn
, before
, NULL_RTX
,
3148 "Inserting the sec. move");
3150 lra_update_insn_regno_info (curr_insn
);
3155 lra_assert (goal_alt_number
>= 0);
3156 lra_set_used_insn_alternative (curr_insn
, goal_alt_number
);
3158 if (lra_dump_file
!= NULL
)
3162 fprintf (lra_dump_file
, " Choosing alt %d in insn %u:",
3163 goal_alt_number
, INSN_UID (curr_insn
));
3164 for (i
= 0; i
< n_operands
; i
++)
3166 p
= (curr_static_id
->operand_alternative
3167 [goal_alt_number
* n_operands
+ i
].constraint
);
3170 fprintf (lra_dump_file
, " (%d) ", i
);
3171 for (; *p
!= '\0' && *p
!= ',' && *p
!= '#'; p
++)
3172 fputc (*p
, lra_dump_file
);
3174 if (INSN_CODE (curr_insn
) >= 0
3175 && (p
= get_insn_name (INSN_CODE (curr_insn
))) != NULL
)
3176 fprintf (lra_dump_file
, " {%s}", p
);
3177 fprintf (lra_dump_file
, "\n");
3180 /* Right now, for any pair of operands I and J that are required to
3181 match, with J < I, goal_alt_matches[I] is J. Add I to
3182 goal_alt_matched[J]. */
3184 for (i
= 0; i
< n_operands
; i
++)
3185 if ((j
= goal_alt_matches
[i
]) >= 0)
3187 for (k
= 0; goal_alt_matched
[j
][k
] >= 0; k
++)
3189 /* We allow matching one output operand and several input
3192 || (curr_static_id
->operand
[j
].type
== OP_OUT
3193 && curr_static_id
->operand
[i
].type
== OP_IN
3194 && (curr_static_id
->operand
3195 [goal_alt_matched
[j
][0]].type
== OP_IN
)));
3196 goal_alt_matched
[j
][k
] = i
;
3197 goal_alt_matched
[j
][k
+ 1] = -1;
3200 for (i
= 0; i
< n_operands
; i
++)
3201 goal_alt_win
[i
] |= goal_alt_match_win
[i
];
3203 /* Any constants that aren't allowed and can't be reloaded into
3204 registers are here changed into memory references. */
3205 for (i
= 0; i
< n_operands
; i
++)
3206 if (goal_alt_win
[i
])
3209 enum reg_class new_class
;
3210 rtx reg
= *curr_id
->operand_loc
[i
];
3212 if (GET_CODE (reg
) == SUBREG
)
3213 reg
= SUBREG_REG (reg
);
3215 if (REG_P (reg
) && (regno
= REGNO (reg
)) >= FIRST_PSEUDO_REGISTER
)
3217 bool ok_p
= in_class_p (reg
, goal_alt
[i
], &new_class
);
3219 if (new_class
!= NO_REGS
&& get_reg_class (regno
) != new_class
)
3222 change_class (regno
, new_class
, " Change", true);
3228 const char *constraint
;
3230 rtx op
= *curr_id
->operand_loc
[i
];
3231 rtx subreg
= NULL_RTX
;
3232 enum machine_mode mode
= curr_operand_mode
[i
];
3234 if (GET_CODE (op
) == SUBREG
)
3237 op
= SUBREG_REG (op
);
3238 mode
= GET_MODE (op
);
3241 if (CONST_POOL_OK_P (mode
, op
)
3242 && ((targetm
.preferred_reload_class
3243 (op
, (enum reg_class
) goal_alt
[i
]) == NO_REGS
)
3244 || no_input_reloads_p
))
3246 rtx tem
= force_const_mem (mode
, op
);
3249 if (subreg
!= NULL_RTX
)
3250 tem
= gen_rtx_SUBREG (mode
, tem
, SUBREG_BYTE (subreg
));
3252 *curr_id
->operand_loc
[i
] = tem
;
3253 lra_update_dup (curr_id
, i
);
3254 process_address (i
, &before
, &after
);
3256 /* If the alternative accepts constant pool refs directly
3257 there will be no reload needed at all. */
3258 if (subreg
!= NULL_RTX
)
3260 /* Skip alternatives before the one requested. */
3261 constraint
= (curr_static_id
->operand_alternative
3262 [goal_alt_number
* n_operands
+ i
].constraint
);
3264 (c
= *constraint
) && c
!= ',' && c
!= '#';
3265 constraint
+= CONSTRAINT_LEN (c
, constraint
))
3267 if (c
== TARGET_MEM_CONSTRAINT
|| c
== 'o')
3269 #ifdef EXTRA_CONSTRAINT_STR
3270 if (EXTRA_MEMORY_CONSTRAINT (c
, constraint
)
3271 && EXTRA_CONSTRAINT_STR (tem
, c
, constraint
))
3275 if (c
== '\0' || c
== ',' || c
== '#')
3278 goal_alt_win
[i
] = true;
3282 for (i
= 0; i
< n_operands
; i
++)
3285 bool optional_p
= false;
3287 rtx op
= *curr_id
->operand_loc
[i
];
3289 if (goal_alt_win
[i
])
3291 if (goal_alt
[i
] == NO_REGS
3293 /* When we assign NO_REGS it means that we will not
3294 assign a hard register to the scratch pseudo by
3295 assigment pass and the scratch pseudo will be
3296 spilled. Spilled scratch pseudos are transformed
3297 back to scratches at the LRA end. */
3298 && lra_former_scratch_operand_p (curr_insn
, i
))
3300 int regno
= REGNO (op
);
3301 change_class (regno
, NO_REGS
, " Change", true);
3302 if (lra_get_regno_hard_regno (regno
) >= 0)
3303 /* We don't have to mark all insn affected by the
3304 spilled pseudo as there is only one such insn, the
3306 reg_renumber
[regno
] = -1;
3308 /* We can do an optional reload. If the pseudo got a hard
3309 reg, we might improve the code through inheritance. If
3310 it does not get a hard register we coalesce memory/memory
3311 moves later. Ignore move insns to avoid cycling. */
3313 && lra_undo_inheritance_iter
< LRA_MAX_INHERITANCE_PASSES
3314 && goal_alt
[i
] != NO_REGS
&& REG_P (op
)
3315 && (regno
= REGNO (op
)) >= FIRST_PSEUDO_REGISTER
3316 && ! lra_former_scratch_p (regno
)
3317 && reg_renumber
[regno
] < 0
3318 && (curr_insn_set
== NULL_RTX
3319 || !((REG_P (SET_SRC (curr_insn_set
))
3320 || MEM_P (SET_SRC (curr_insn_set
))
3321 || GET_CODE (SET_SRC (curr_insn_set
)) == SUBREG
)
3322 && (REG_P (SET_DEST (curr_insn_set
))
3323 || MEM_P (SET_DEST (curr_insn_set
))
3324 || GET_CODE (SET_DEST (curr_insn_set
)) == SUBREG
))))
3330 /* Operands that match previous ones have already been handled. */
3331 if (goal_alt_matches
[i
] >= 0)
3334 /* We should not have an operand with a non-offsettable address
3335 appearing where an offsettable address will do. It also may
3336 be a case when the address should be special in other words
3337 not a general one (e.g. it needs no index reg). */
3338 if (goal_alt_matched
[i
][0] == -1 && goal_alt_offmemok
[i
] && MEM_P (op
))
3340 enum reg_class rclass
;
3341 rtx
*loc
= &XEXP (op
, 0);
3342 enum rtx_code code
= GET_CODE (*loc
);
3344 push_to_sequence (before
);
3345 rclass
= base_reg_class (GET_MODE (op
), MEM_ADDR_SPACE (op
),
3347 if (GET_RTX_CLASS (code
) == RTX_AUTOINC
)
3348 new_reg
= emit_inc (rclass
, *loc
, *loc
,
3349 /* This value does not matter for MODIFY. */
3350 GET_MODE_SIZE (GET_MODE (op
)));
3351 else if (get_reload_reg (OP_IN
, Pmode
, *loc
, rclass
,
3352 "offsetable address", &new_reg
))
3353 lra_emit_move (new_reg
, *loc
);
3354 before
= get_insns ();
3357 lra_update_dup (curr_id
, i
);
3359 else if (goal_alt_matched
[i
][0] == -1)
3361 enum machine_mode mode
;
3363 int hard_regno
, byte
;
3364 enum op_type type
= curr_static_id
->operand
[i
].type
;
3366 loc
= curr_id
->operand_loc
[i
];
3367 mode
= curr_operand_mode
[i
];
3368 if (GET_CODE (*loc
) == SUBREG
)
3370 reg
= SUBREG_REG (*loc
);
3371 byte
= SUBREG_BYTE (*loc
);
3373 /* Strict_low_part requires reload the register not
3374 the sub-register. */
3375 && (curr_static_id
->operand
[i
].strict_low
3376 || (GET_MODE_SIZE (mode
)
3377 <= GET_MODE_SIZE (GET_MODE (reg
))
3379 = get_try_hard_regno (REGNO (reg
))) >= 0
3380 && (simplify_subreg_regno
3382 GET_MODE (reg
), byte
, mode
) < 0)
3383 && (goal_alt
[i
] == NO_REGS
3384 || (simplify_subreg_regno
3385 (ira_class_hard_regs
[goal_alt
[i
]][0],
3386 GET_MODE (reg
), byte
, mode
) >= 0)))))
3388 loc
= &SUBREG_REG (*loc
);
3389 mode
= GET_MODE (*loc
);
3393 if (get_reload_reg (type
, mode
, old
, goal_alt
[i
], "", &new_reg
)
3396 push_to_sequence (before
);
3397 lra_emit_move (new_reg
, old
);
3398 before
= get_insns ();
3403 && find_reg_note (curr_insn
, REG_UNUSED
, old
) == NULL_RTX
)
3406 lra_emit_move (type
== OP_INOUT
? copy_rtx (old
) : old
, new_reg
);
3408 after
= get_insns ();
3412 for (j
= 0; j
< goal_alt_dont_inherit_ops_num
; j
++)
3413 if (goal_alt_dont_inherit_ops
[j
] == i
)
3415 lra_set_regno_unique_value (REGNO (new_reg
));
3418 lra_update_dup (curr_id
, i
);
3420 else if (curr_static_id
->operand
[i
].type
== OP_IN
3421 && (curr_static_id
->operand
[goal_alt_matched
[i
][0]].type
3424 /* generate reloads for input and matched outputs. */
3425 match_inputs
[0] = i
;
3426 match_inputs
[1] = -1;
3427 match_reload (goal_alt_matched
[i
][0], match_inputs
,
3428 goal_alt
[i
], &before
, &after
);
3430 else if (curr_static_id
->operand
[i
].type
== OP_OUT
3431 && (curr_static_id
->operand
[goal_alt_matched
[i
][0]].type
3433 /* Generate reloads for output and matched inputs. */
3434 match_reload (i
, goal_alt_matched
[i
], goal_alt
[i
], &before
, &after
);
3435 else if (curr_static_id
->operand
[i
].type
== OP_IN
3436 && (curr_static_id
->operand
[goal_alt_matched
[i
][0]].type
3439 /* Generate reloads for matched inputs. */
3440 match_inputs
[0] = i
;
3441 for (j
= 0; (k
= goal_alt_matched
[i
][j
]) >= 0; j
++)
3442 match_inputs
[j
+ 1] = k
;
3443 match_inputs
[j
+ 1] = -1;
3444 match_reload (-1, match_inputs
, goal_alt
[i
], &before
, &after
);
3447 /* We must generate code in any case when function
3448 process_alt_operands decides that it is possible. */
3452 lra_assert (REG_P (op
));
3454 op
= *curr_id
->operand_loc
[i
]; /* Substitution. */
3455 if (GET_CODE (op
) == SUBREG
)
3456 op
= SUBREG_REG (op
);
3457 gcc_assert (REG_P (op
) && (int) REGNO (op
) >= new_regno_start
);
3458 bitmap_set_bit (&lra_optional_reload_pseudos
, REGNO (op
));
3459 lra_reg_info
[REGNO (op
)].restore_regno
= regno
;
3460 if (lra_dump_file
!= NULL
)
3461 fprintf (lra_dump_file
,
3462 " Making reload reg %d for reg %d optional\n",
3466 if (before
!= NULL_RTX
|| after
!= NULL_RTX
3467 || max_regno_before
!= max_reg_num ())
3471 lra_update_operator_dups (curr_id
);
3472 /* Something changes -- process the insn. */
3473 lra_update_insn_regno_info (curr_insn
);
3475 lra_process_new_insns (curr_insn
, before
, after
, "Inserting insn reload");
3479 /* Return true if X is in LIST. */
3481 in_list_p (rtx x
, rtx list
)
3483 for (; list
!= NULL_RTX
; list
= XEXP (list
, 1))
3484 if (XEXP (list
, 0) == x
)
3489 /* Return true if X contains an allocatable hard register (if
3490 HARD_REG_P) or a (spilled if SPILLED_P) pseudo. */
3492 contains_reg_p (rtx x
, bool hard_reg_p
, bool spilled_p
)
3498 code
= GET_CODE (x
);
3501 int regno
= REGNO (x
);
3502 HARD_REG_SET alloc_regs
;
3506 if (regno
>= FIRST_PSEUDO_REGISTER
)
3507 regno
= lra_get_regno_hard_regno (regno
);
3510 COMPL_HARD_REG_SET (alloc_regs
, lra_no_alloc_regs
);
3511 return overlaps_hard_reg_set_p (alloc_regs
, GET_MODE (x
), regno
);
3515 if (regno
< FIRST_PSEUDO_REGISTER
)
3519 return lra_get_regno_hard_regno (regno
) < 0;
3522 fmt
= GET_RTX_FORMAT (code
);
3523 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
3527 if (contains_reg_p (XEXP (x
, i
), hard_reg_p
, spilled_p
))
3530 else if (fmt
[i
] == 'E')
3532 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3533 if (contains_reg_p (XVECEXP (x
, i
, j
), hard_reg_p
, spilled_p
))
3540 /* Process all regs in location *LOC and change them on equivalent
3541 substitution. Return true if any change was done. */
3543 loc_equivalence_change_p (rtx
*loc
)
3545 rtx subst
, reg
, x
= *loc
;
3546 bool result
= false;
3547 enum rtx_code code
= GET_CODE (x
);
3553 reg
= SUBREG_REG (x
);
3554 if ((subst
= get_equiv_substitution (reg
)) != reg
3555 && GET_MODE (subst
) == VOIDmode
)
3557 /* We cannot reload debug location. Simplify subreg here
3558 while we know the inner mode. */
3559 *loc
= simplify_gen_subreg (GET_MODE (x
), subst
,
3560 GET_MODE (reg
), SUBREG_BYTE (x
));
3564 if (code
== REG
&& (subst
= get_equiv_substitution (x
)) != x
)
3570 /* Scan all the operand sub-expressions. */
3571 fmt
= GET_RTX_FORMAT (code
);
3572 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
3575 result
= loc_equivalence_change_p (&XEXP (x
, i
)) || result
;
3576 else if (fmt
[i
] == 'E')
3577 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3579 = loc_equivalence_change_p (&XVECEXP (x
, i
, j
)) || result
;
3584 /* Similar to loc_equivalence_change_p, but for use as
3585 simplify_replace_fn_rtx callback. */
3587 loc_equivalence_callback (rtx loc
, const_rtx
, void *)
3592 rtx subst
= get_equiv_substitution (loc
);
3599 /* Maximum number of generated reload insns per an insn. It is for
3600 preventing this pass cycling in a bug case. */
3601 #define MAX_RELOAD_INSNS_NUMBER LRA_MAX_INSN_RELOADS
3603 /* The current iteration number of this LRA pass. */
3604 int lra_constraint_iter
;
3606 /* The current iteration number of this LRA pass after the last spill
3608 int lra_constraint_iter_after_spill
;
3610 /* True if we substituted equiv which needs checking register
3611 allocation correctness because the equivalent value contains
3612 allocatable hard registers or when we restore multi-register
3614 bool lra_risky_transformations_p
;
3616 /* Return true if REGNO is referenced in more than one block. */
3618 multi_block_pseudo_p (int regno
)
3620 basic_block bb
= NULL
;
3624 if (regno
< FIRST_PSEUDO_REGISTER
)
3627 EXECUTE_IF_SET_IN_BITMAP (&lra_reg_info
[regno
].insn_bitmap
, 0, uid
, bi
)
3629 bb
= BLOCK_FOR_INSN (lra_insn_recog_data
[uid
]->insn
);
3630 else if (BLOCK_FOR_INSN (lra_insn_recog_data
[uid
]->insn
) != bb
)
3635 /* Return true if LIST contains a deleted insn. */
3637 contains_deleted_insn_p (rtx list
)
3639 for (; list
!= NULL_RTX
; list
= XEXP (list
, 1))
3640 if (NOTE_P (XEXP (list
, 0))
3641 && NOTE_KIND (XEXP (list
, 0)) == NOTE_INSN_DELETED
)
3646 /* Return true if X contains a pseudo dying in INSN. */
3648 dead_pseudo_p (rtx x
, rtx insn
)
3655 return (insn
!= NULL_RTX
3656 && find_regno_note (insn
, REG_DEAD
, REGNO (x
)) != NULL_RTX
);
3657 code
= GET_CODE (x
);
3658 fmt
= GET_RTX_FORMAT (code
);
3659 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
3663 if (dead_pseudo_p (XEXP (x
, i
), insn
))
3666 else if (fmt
[i
] == 'E')
3668 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3669 if (dead_pseudo_p (XVECEXP (x
, i
, j
), insn
))
3676 /* Return true if INSN contains a dying pseudo in INSN right hand
3679 insn_rhs_dead_pseudo_p (rtx insn
)
3681 rtx set
= single_set (insn
);
3683 gcc_assert (set
!= NULL
);
3684 return dead_pseudo_p (SET_SRC (set
), insn
);
3687 /* Return true if any init insn of REGNO contains a dying pseudo in
3688 insn right hand side. */
3690 init_insn_rhs_dead_pseudo_p (int regno
)
3692 rtx insns
= ira_reg_equiv
[regno
].init_insns
;
3697 return insn_rhs_dead_pseudo_p (insns
);
3698 for (; insns
!= NULL_RTX
; insns
= XEXP (insns
, 1))
3699 if (insn_rhs_dead_pseudo_p (XEXP (insns
, 0)))
3704 /* Return TRUE if REGNO has a reverse equivalence. The equivalence is
3705 reverse only if we have one init insn with given REGNO as a
3708 reverse_equiv_p (int regno
)
3712 if ((insns
= ira_reg_equiv
[regno
].init_insns
) == NULL_RTX
)
3714 if (! INSN_P (XEXP (insns
, 0))
3715 || XEXP (insns
, 1) != NULL_RTX
)
3717 if ((set
= single_set (XEXP (insns
, 0))) == NULL_RTX
)
3719 return REG_P (SET_SRC (set
)) && (int) REGNO (SET_SRC (set
)) == regno
;
3722 /* Return TRUE if REGNO was reloaded in an equivalence init insn. We
3723 call this function only for non-reverse equivalence. */
3725 contains_reloaded_insn_p (int regno
)
3728 rtx list
= ira_reg_equiv
[regno
].init_insns
;
3730 for (; list
!= NULL_RTX
; list
= XEXP (list
, 1))
3731 if ((set
= single_set (XEXP (list
, 0))) == NULL_RTX
3732 || ! REG_P (SET_DEST (set
))
3733 || (int) REGNO (SET_DEST (set
)) != regno
)
3738 /* Entry function of LRA constraint pass. Return true if the
3739 constraint pass did change the code. */
3741 lra_constraints (bool first_p
)
3744 int i
, hard_regno
, new_insns_num
;
3745 unsigned int min_len
, new_min_len
, uid
;
3746 rtx set
, x
, reg
, dest_reg
;
3747 basic_block last_bb
;
3748 bitmap_head equiv_insn_bitmap
;
3751 lra_constraint_iter
++;
3752 if (lra_dump_file
!= NULL
)
3753 fprintf (lra_dump_file
, "\n********** Local #%d: **********\n\n",
3754 lra_constraint_iter
);
3755 lra_constraint_iter_after_spill
++;
3756 if (lra_constraint_iter_after_spill
> LRA_MAX_CONSTRAINT_ITERATION_NUMBER
)
3758 ("Maximum number of LRA constraint passes is achieved (%d)\n",
3759 LRA_MAX_CONSTRAINT_ITERATION_NUMBER
);
3761 lra_risky_transformations_p
= false;
3762 new_insn_uid_start
= get_max_uid ();
3763 new_regno_start
= first_p
? lra_constraint_new_regno_start
: max_reg_num ();
3764 bitmap_initialize (&equiv_insn_bitmap
, ®_obstack
);
3765 for (i
= FIRST_PSEUDO_REGISTER
; i
< new_regno_start
; i
++)
3766 if (lra_reg_info
[i
].nrefs
!= 0)
3768 ira_reg_equiv
[i
].profitable_p
= true;
3769 reg
= regno_reg_rtx
[i
];
3770 if ((hard_regno
= lra_get_regno_hard_regno (i
)) >= 0)
3774 nregs
= hard_regno_nregs
[hard_regno
][lra_reg_info
[i
].biggest_mode
];
3775 for (j
= 0; j
< nregs
; j
++)
3776 df_set_regs_ever_live (hard_regno
+ j
, true);
3778 else if ((x
= get_equiv_substitution (reg
)) != reg
)
3780 bool pseudo_p
= contains_reg_p (x
, false, false);
3782 /* After RTL transformation, we can not guarantee that
3783 pseudo in the substitution was not reloaded which might
3784 make equivalence invalid. For example, in reverse
3791 the memory address register was reloaded before the 2nd
3793 if ((! first_p
&& pseudo_p
)
3794 /* We don't use DF for compilation speed sake. So it
3795 is problematic to update live info when we use an
3796 equivalence containing pseudos in more than one
3798 || (pseudo_p
&& multi_block_pseudo_p (i
))
3799 /* If an init insn was deleted for some reason, cancel
3800 the equiv. We could update the equiv insns after
3801 transformations including an equiv insn deletion
3802 but it is not worthy as such cases are extremely
3804 || contains_deleted_insn_p (ira_reg_equiv
[i
].init_insns
)
3805 /* If it is not a reverse equivalence, we check that a
3806 pseudo in rhs of the init insn is not dying in the
3807 insn. Otherwise, the live info at the beginning of
3808 the corresponding BB might be wrong after we
3809 removed the insn. When the equiv can be a
3810 constant, the right hand side of the init insn can
3812 || (! reverse_equiv_p (i
)
3813 && (init_insn_rhs_dead_pseudo_p (i
)
3814 /* If we reloaded the pseudo in an equivalence
3815 init insn, we can not remove the equiv init
3816 insns and the init insns might write into
3817 const memory in this case. */
3818 || contains_reloaded_insn_p (i
)))
3819 /* Prevent access beyond equivalent memory for
3820 paradoxical subregs. */
3822 && (GET_MODE_SIZE (lra_reg_info
[i
].biggest_mode
)
3823 > GET_MODE_SIZE (GET_MODE (x
)))))
3824 ira_reg_equiv
[i
].defined_p
= false;
3825 if (contains_reg_p (x
, false, true))
3826 ira_reg_equiv
[i
].profitable_p
= false;
3827 if (get_equiv_substitution (reg
) != reg
)
3828 bitmap_ior_into (&equiv_insn_bitmap
, &lra_reg_info
[i
].insn_bitmap
);
3831 /* We should add all insns containing pseudos which should be
3832 substituted by their equivalences. */
3833 EXECUTE_IF_SET_IN_BITMAP (&equiv_insn_bitmap
, 0, uid
, bi
)
3834 lra_push_insn_by_uid (uid
);
3835 lra_eliminate (false);
3836 min_len
= lra_insn_stack_length ();
3840 while ((new_min_len
= lra_insn_stack_length ()) != 0)
3842 curr_insn
= lra_pop_insn ();
3844 curr_bb
= BLOCK_FOR_INSN (curr_insn
);
3845 if (curr_bb
!= last_bb
)
3848 bb_reload_num
= lra_curr_reload_num
;
3850 if (min_len
> new_min_len
)
3852 min_len
= new_min_len
;
3855 if (new_insns_num
> MAX_RELOAD_INSNS_NUMBER
)
3857 ("Max. number of generated reload insns per insn is achieved (%d)\n",
3858 MAX_RELOAD_INSNS_NUMBER
);
3860 if (DEBUG_INSN_P (curr_insn
))
3862 /* We need to check equivalence in debug insn and change
3863 pseudo to the equivalent value if necessary. */
3864 curr_id
= lra_get_insn_recog_data (curr_insn
);
3865 if (bitmap_bit_p (&equiv_insn_bitmap
, INSN_UID (curr_insn
)))
3867 rtx old
= *curr_id
->operand_loc
[0];
3868 *curr_id
->operand_loc
[0]
3869 = simplify_replace_fn_rtx (old
, NULL_RTX
,
3870 loc_equivalence_callback
, NULL
);
3871 if (old
!= *curr_id
->operand_loc
[0])
3873 lra_update_insn_regno_info (curr_insn
);
3878 else if (INSN_P (curr_insn
))
3880 if ((set
= single_set (curr_insn
)) != NULL_RTX
)
3882 dest_reg
= SET_DEST (set
);
3883 /* The equivalence pseudo could be set up as SUBREG in a
3884 case when it is a call restore insn in a mode
3885 different from the pseudo mode. */
3886 if (GET_CODE (dest_reg
) == SUBREG
)
3887 dest_reg
= SUBREG_REG (dest_reg
);
3888 if ((REG_P (dest_reg
)
3889 && (x
= get_equiv_substitution (dest_reg
)) != dest_reg
3890 /* Check that this is actually an insn setting up
3892 && (in_list_p (curr_insn
,
3894 [REGNO (dest_reg
)].init_insns
)
3895 /* Init insns may contain not all insns setting
3896 up equivalence as we have live range
3897 splitting. So here we use another condition
3898 to check insn setting up the equivalence
3899 which should be removed, e.g. in case when
3900 the equivalence is a constant. */
3902 /* Remove insns which set up a pseudo whose value
3903 can not be changed. Such insns might be not in
3904 init_insns because we don't update equiv data
3905 during insn transformations.
3907 As an example, let suppose that a pseudo got
3908 hard register and on the 1st pass was not
3909 changed to equivalent constant. We generate an
3910 additional insn setting up the pseudo because of
3911 secondary memory movement. Then the pseudo is
3912 spilled and we use the equiv constant. In this
3913 case we should remove the additional insn and
3914 this insn is not init_insns list. */
3915 && (! MEM_P (x
) || MEM_READONLY_P (x
)
3916 || in_list_p (curr_insn
,
3918 [REGNO (dest_reg
)].init_insns
)))
3919 || (((x
= get_equiv_substitution (SET_SRC (set
)))
3921 && in_list_p (curr_insn
,
3923 [REGNO (SET_SRC (set
))].init_insns
)))
3925 /* This is equiv init insn of pseudo which did not get a
3926 hard register -- remove the insn. */
3927 if (lra_dump_file
!= NULL
)
3929 fprintf (lra_dump_file
,
3930 " Removing equiv init insn %i (freq=%d)\n",
3931 INSN_UID (curr_insn
),
3932 BLOCK_FOR_INSN (curr_insn
)->frequency
);
3933 dump_insn_slim (lra_dump_file
, curr_insn
);
3935 if (contains_reg_p (x
, true, false))
3936 lra_risky_transformations_p
= true;
3937 lra_set_insn_deleted (curr_insn
);
3941 curr_id
= lra_get_insn_recog_data (curr_insn
);
3942 curr_static_id
= curr_id
->insn_static_data
;
3943 init_curr_insn_input_reloads ();
3944 init_curr_operand_mode ();
3945 if (curr_insn_transform ())
3947 /* Check non-transformed insns too for equiv change as USE
3948 or CLOBBER don't need reloads but can contain pseudos
3949 being changed on their equivalences. */
3950 else if (bitmap_bit_p (&equiv_insn_bitmap
, INSN_UID (curr_insn
))
3951 && loc_equivalence_change_p (&PATTERN (curr_insn
)))
3953 lra_update_insn_regno_info (curr_insn
);
3958 bitmap_clear (&equiv_insn_bitmap
);
3959 /* If we used a new hard regno, changed_p should be true because the
3960 hard reg is assigned to a new pseudo. */
3961 #ifdef ENABLE_CHECKING
3964 for (i
= FIRST_PSEUDO_REGISTER
; i
< new_regno_start
; i
++)
3965 if (lra_reg_info
[i
].nrefs
!= 0
3966 && (hard_regno
= lra_get_regno_hard_regno (i
)) >= 0)
3968 int j
, nregs
= hard_regno_nregs
[hard_regno
][PSEUDO_REGNO_MODE (i
)];
3970 for (j
= 0; j
< nregs
; j
++)
3971 lra_assert (df_regs_ever_live_p (hard_regno
+ j
));
3978 /* Initiate the LRA constraint pass. It is done once per
3981 lra_constraints_init (void)
3985 /* Finalize the LRA constraint pass. It is done once per
3988 lra_constraints_finish (void)
3994 /* This page contains code to do inheritance/split
3997 /* Number of reloads passed so far in current EBB. */
3998 static int reloads_num
;
4000 /* Number of calls passed so far in current EBB. */
4001 static int calls_num
;
4003 /* Current reload pseudo check for validity of elements in
4005 static int curr_usage_insns_check
;
4007 /* Info about last usage of registers in EBB to do inheritance/split
4008 transformation. Inheritance transformation is done from a spilled
4009 pseudo and split transformations from a hard register or a pseudo
4010 assigned to a hard register. */
4013 /* If the value is equal to CURR_USAGE_INSNS_CHECK, then the member
4014 value INSNS is valid. The insns is chain of optional debug insns
4015 and a finishing non-debug insn using the corresponding reg. The
4016 value is also used to mark the registers which are set up in the
4017 current insn. The negated insn uid is used for this. */
4019 /* Value of global reloads_num at the last insn in INSNS. */
4021 /* Value of global reloads_nums at the last insn in INSNS. */
4023 /* It can be true only for splitting. And it means that the restore
4024 insn should be put after insn given by the following member. */
4026 /* Next insns in the current EBB which use the original reg and the
4027 original reg value is not changed between the current insn and
4028 the next insns. In order words, e.g. for inheritance, if we need
4029 to use the original reg value again in the next insns we can try
4030 to use the value in a hard register from a reload insn of the
4035 /* Map: regno -> corresponding pseudo usage insns. */
4036 static struct usage_insns
*usage_insns
;
4039 setup_next_usage_insn (int regno
, rtx insn
, int reloads_num
, bool after_p
)
4041 usage_insns
[regno
].check
= curr_usage_insns_check
;
4042 usage_insns
[regno
].insns
= insn
;
4043 usage_insns
[regno
].reloads_num
= reloads_num
;
4044 usage_insns
[regno
].calls_num
= calls_num
;
4045 usage_insns
[regno
].after_p
= after_p
;
4048 /* The function is used to form list REGNO usages which consists of
4049 optional debug insns finished by a non-debug insn using REGNO.
4050 RELOADS_NUM is current number of reload insns processed so far. */
4052 add_next_usage_insn (int regno
, rtx insn
, int reloads_num
)
4054 rtx next_usage_insns
;
4056 if (usage_insns
[regno
].check
== curr_usage_insns_check
4057 && (next_usage_insns
= usage_insns
[regno
].insns
) != NULL_RTX
4058 && DEBUG_INSN_P (insn
))
4060 /* Check that we did not add the debug insn yet. */
4061 if (next_usage_insns
!= insn
4062 && (GET_CODE (next_usage_insns
) != INSN_LIST
4063 || XEXP (next_usage_insns
, 0) != insn
))
4064 usage_insns
[regno
].insns
= gen_rtx_INSN_LIST (VOIDmode
, insn
,
4067 else if (NONDEBUG_INSN_P (insn
))
4068 setup_next_usage_insn (regno
, insn
, reloads_num
, false);
4070 usage_insns
[regno
].check
= 0;
4073 /* Replace all references to register OLD_REGNO in *LOC with pseudo
4074 register NEW_REG. Return true if any change was made. */
4076 substitute_pseudo (rtx
*loc
, int old_regno
, rtx new_reg
)
4079 bool result
= false;
4087 code
= GET_CODE (x
);
4088 if (code
== REG
&& (int) REGNO (x
) == old_regno
)
4090 enum machine_mode mode
= GET_MODE (*loc
);
4091 enum machine_mode inner_mode
= GET_MODE (new_reg
);
4093 if (mode
!= inner_mode
)
4095 if (GET_MODE_SIZE (mode
) >= GET_MODE_SIZE (inner_mode
)
4096 || ! SCALAR_INT_MODE_P (inner_mode
))
4097 new_reg
= gen_rtx_SUBREG (mode
, new_reg
, 0);
4099 new_reg
= gen_lowpart_SUBREG (mode
, new_reg
);
4105 /* Scan all the operand sub-expressions. */
4106 fmt
= GET_RTX_FORMAT (code
);
4107 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
4111 if (substitute_pseudo (&XEXP (x
, i
), old_regno
, new_reg
))
4114 else if (fmt
[i
] == 'E')
4116 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
4117 if (substitute_pseudo (&XVECEXP (x
, i
, j
), old_regno
, new_reg
))
4124 /* Return first non-debug insn in list USAGE_INSNS. */
4126 skip_usage_debug_insns (rtx usage_insns
)
4130 /* Skip debug insns. */
4131 for (insn
= usage_insns
;
4132 insn
!= NULL_RTX
&& GET_CODE (insn
) == INSN_LIST
;
4133 insn
= XEXP (insn
, 1))
4138 /* Return true if we need secondary memory moves for insn in
4139 USAGE_INSNS after inserting inherited pseudo of class INHER_CL
4142 check_secondary_memory_needed_p (enum reg_class inher_cl ATTRIBUTE_UNUSED
,
4143 rtx usage_insns ATTRIBUTE_UNUSED
)
4145 #ifndef SECONDARY_MEMORY_NEEDED
4148 rtx insn
, set
, dest
;
4151 if (inher_cl
== ALL_REGS
4152 || (insn
= skip_usage_debug_insns (usage_insns
)) == NULL_RTX
)
4154 lra_assert (INSN_P (insn
));
4155 if ((set
= single_set (insn
)) == NULL_RTX
|| ! REG_P (SET_DEST (set
)))
4157 dest
= SET_DEST (set
);
4160 lra_assert (inher_cl
!= NO_REGS
);
4161 cl
= get_reg_class (REGNO (dest
));
4162 return (cl
!= NO_REGS
&& cl
!= ALL_REGS
4163 && SECONDARY_MEMORY_NEEDED (inher_cl
, cl
, GET_MODE (dest
)));
4167 /* Registers involved in inheritance/split in the current EBB
4168 (inheritance/split pseudos and original registers). */
4169 static bitmap_head check_only_regs
;
4171 /* Do inheritance transformations for insn INSN, which defines (if
4172 DEF_P) or uses ORIGINAL_REGNO. NEXT_USAGE_INSNS specifies which
4173 instruction in the EBB next uses ORIGINAL_REGNO; it has the same
4174 form as the "insns" field of usage_insns. Return true if we
4175 succeed in such transformation.
4177 The transformations look like:
4180 ... p <- i (new insn)
4182 <- ... p ... <- ... i ...
4184 ... i <- p (new insn)
4185 <- ... p ... <- ... i ...
4187 <- ... p ... <- ... i ...
4188 where p is a spilled original pseudo and i is a new inheritance pseudo.
4191 The inheritance pseudo has the smallest class of two classes CL and
4192 class of ORIGINAL REGNO. */
4194 inherit_reload_reg (bool def_p
, int original_regno
,
4195 enum reg_class cl
, rtx insn
, rtx next_usage_insns
)
4197 enum reg_class rclass
= lra_get_allocno_class (original_regno
);
4198 rtx original_reg
= regno_reg_rtx
[original_regno
];
4199 rtx new_reg
, new_insns
, usage_insn
;
4201 lra_assert (! usage_insns
[original_regno
].after_p
);
4202 if (lra_dump_file
!= NULL
)
4203 fprintf (lra_dump_file
,
4204 " <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<\n");
4205 if (! ira_reg_classes_intersect_p
[cl
][rclass
])
4207 if (lra_dump_file
!= NULL
)
4209 fprintf (lra_dump_file
,
4210 " Rejecting inheritance for %d "
4211 "because of disjoint classes %s and %s\n",
4212 original_regno
, reg_class_names
[cl
],
4213 reg_class_names
[rclass
]);
4214 fprintf (lra_dump_file
,
4215 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
4219 if ((ira_class_subset_p
[cl
][rclass
] && cl
!= rclass
)
4220 /* We don't use a subset of two classes because it can be
4221 NO_REGS. This transformation is still profitable in most
4222 cases even if the classes are not intersected as register
4223 move is probably cheaper than a memory load. */
4224 || ira_class_hard_regs_num
[cl
] < ira_class_hard_regs_num
[rclass
])
4226 if (lra_dump_file
!= NULL
)
4227 fprintf (lra_dump_file
, " Use smallest class of %s and %s\n",
4228 reg_class_names
[cl
], reg_class_names
[rclass
]);
4232 if (check_secondary_memory_needed_p (rclass
, next_usage_insns
))
4234 /* Reject inheritance resulting in secondary memory moves.
4235 Otherwise, there is a danger in LRA cycling. Also such
4236 transformation will be unprofitable. */
4237 if (lra_dump_file
!= NULL
)
4239 rtx insn
= skip_usage_debug_insns (next_usage_insns
);
4240 rtx set
= single_set (insn
);
4242 lra_assert (set
!= NULL_RTX
);
4244 rtx dest
= SET_DEST (set
);
4246 lra_assert (REG_P (dest
));
4247 fprintf (lra_dump_file
,
4248 " Rejecting inheritance for insn %d(%s)<-%d(%s) "
4249 "as secondary mem is needed\n",
4250 REGNO (dest
), reg_class_names
[get_reg_class (REGNO (dest
))],
4251 original_regno
, reg_class_names
[rclass
]);
4252 fprintf (lra_dump_file
,
4253 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
4257 new_reg
= lra_create_new_reg (GET_MODE (original_reg
), original_reg
,
4258 rclass
, "inheritance");
4261 emit_move_insn (original_reg
, new_reg
);
4263 emit_move_insn (new_reg
, original_reg
);
4264 new_insns
= get_insns ();
4266 if (NEXT_INSN (new_insns
) != NULL_RTX
)
4268 if (lra_dump_file
!= NULL
)
4270 fprintf (lra_dump_file
,
4271 " Rejecting inheritance %d->%d "
4272 "as it results in 2 or more insns:\n",
4273 original_regno
, REGNO (new_reg
));
4274 dump_rtl_slim (lra_dump_file
, new_insns
, NULL_RTX
, -1, 0);
4275 fprintf (lra_dump_file
,
4276 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
4280 substitute_pseudo (&insn
, original_regno
, new_reg
);
4281 lra_update_insn_regno_info (insn
);
4283 /* We now have a new usage insn for original regno. */
4284 setup_next_usage_insn (original_regno
, new_insns
, reloads_num
, false);
4285 if (lra_dump_file
!= NULL
)
4286 fprintf (lra_dump_file
, " Original reg change %d->%d (bb%d):\n",
4287 original_regno
, REGNO (new_reg
), BLOCK_FOR_INSN (insn
)->index
);
4288 lra_reg_info
[REGNO (new_reg
)].restore_regno
= original_regno
;
4289 bitmap_set_bit (&check_only_regs
, REGNO (new_reg
));
4290 bitmap_set_bit (&check_only_regs
, original_regno
);
4291 bitmap_set_bit (&lra_inheritance_pseudos
, REGNO (new_reg
));
4293 lra_process_new_insns (insn
, NULL_RTX
, new_insns
,
4294 "Add original<-inheritance");
4296 lra_process_new_insns (insn
, new_insns
, NULL_RTX
,
4297 "Add inheritance<-original");
4298 while (next_usage_insns
!= NULL_RTX
)
4300 if (GET_CODE (next_usage_insns
) != INSN_LIST
)
4302 usage_insn
= next_usage_insns
;
4303 lra_assert (NONDEBUG_INSN_P (usage_insn
));
4304 next_usage_insns
= NULL
;
4308 usage_insn
= XEXP (next_usage_insns
, 0);
4309 lra_assert (DEBUG_INSN_P (usage_insn
));
4310 next_usage_insns
= XEXP (next_usage_insns
, 1);
4312 substitute_pseudo (&usage_insn
, original_regno
, new_reg
);
4313 lra_update_insn_regno_info (usage_insn
);
4314 if (lra_dump_file
!= NULL
)
4316 fprintf (lra_dump_file
,
4317 " Inheritance reuse change %d->%d (bb%d):\n",
4318 original_regno
, REGNO (new_reg
),
4319 BLOCK_FOR_INSN (usage_insn
)->index
);
4320 dump_insn_slim (lra_dump_file
, usage_insn
);
4323 if (lra_dump_file
!= NULL
)
4324 fprintf (lra_dump_file
,
4325 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
4329 /* Return true if we need a caller save/restore for pseudo REGNO which
4330 was assigned to a hard register. */
4332 need_for_call_save_p (int regno
)
4334 lra_assert (regno
>= FIRST_PSEUDO_REGISTER
&& reg_renumber
[regno
] >= 0);
4335 return (usage_insns
[regno
].calls_num
< calls_num
4336 && (overlaps_hard_reg_set_p
4338 PSEUDO_REGNO_MODE (regno
), reg_renumber
[regno
])));
4341 /* Global registers occurring in the current EBB. */
4342 static bitmap_head ebb_global_regs
;
4344 /* Return true if we need a split for hard register REGNO or pseudo
4345 REGNO which was assigned to a hard register.
4346 POTENTIAL_RELOAD_HARD_REGS contains hard registers which might be
4347 used for reloads since the EBB end. It is an approximation of the
4348 used hard registers in the split range. The exact value would
4349 require expensive calculations. If we were aggressive with
4350 splitting because of the approximation, the split pseudo will save
4351 the same hard register assignment and will be removed in the undo
4352 pass. We still need the approximation because too aggressive
4353 splitting would result in too inaccurate cost calculation in the
4354 assignment pass because of too many generated moves which will be
4355 probably removed in the undo pass. */
4357 need_for_split_p (HARD_REG_SET potential_reload_hard_regs
, int regno
)
4359 int hard_regno
= regno
< FIRST_PSEUDO_REGISTER
? regno
: reg_renumber
[regno
];
4361 lra_assert (hard_regno
>= 0);
4362 return ((TEST_HARD_REG_BIT (potential_reload_hard_regs
, hard_regno
)
4363 /* Don't split eliminable hard registers, otherwise we can
4364 split hard registers like hard frame pointer, which
4365 lives on BB start/end according to DF-infrastructure,
4366 when there is a pseudo assigned to the register and
4367 living in the same BB. */
4368 && (regno
>= FIRST_PSEUDO_REGISTER
4369 || ! TEST_HARD_REG_BIT (eliminable_regset
, hard_regno
))
4370 && ! TEST_HARD_REG_BIT (lra_no_alloc_regs
, hard_regno
)
4371 /* Don't split call clobbered hard regs living through
4372 calls, otherwise we might have a check problem in the
4373 assign sub-pass as in the most cases (exception is a
4374 situation when lra_risky_transformations_p value is
4375 true) the assign pass assumes that all pseudos living
4376 through calls are assigned to call saved hard regs. */
4377 && (regno
>= FIRST_PSEUDO_REGISTER
4378 || ! TEST_HARD_REG_BIT (call_used_reg_set
, regno
)
4379 || usage_insns
[regno
].calls_num
== calls_num
)
4380 /* We need at least 2 reloads to make pseudo splitting
4381 profitable. We should provide hard regno splitting in
4382 any case to solve 1st insn scheduling problem when
4383 moving hard register definition up might result in
4384 impossibility to find hard register for reload pseudo of
4385 small register class. */
4386 && (usage_insns
[regno
].reloads_num
4387 + (regno
< FIRST_PSEUDO_REGISTER
? 0 : 2) < reloads_num
)
4388 && (regno
< FIRST_PSEUDO_REGISTER
4389 /* For short living pseudos, spilling + inheritance can
4390 be considered a substitution for splitting.
4391 Therefore we do not splitting for local pseudos. It
4392 decreases also aggressiveness of splitting. The
4393 minimal number of references is chosen taking into
4394 account that for 2 references splitting has no sense
4395 as we can just spill the pseudo. */
4396 || (regno
>= FIRST_PSEUDO_REGISTER
4397 && lra_reg_info
[regno
].nrefs
> 3
4398 && bitmap_bit_p (&ebb_global_regs
, regno
))))
4399 || (regno
>= FIRST_PSEUDO_REGISTER
&& need_for_call_save_p (regno
)));
4402 /* Return class for the split pseudo created from original pseudo with
4403 ALLOCNO_CLASS and MODE which got a hard register HARD_REGNO. We
4404 choose subclass of ALLOCNO_CLASS which contains HARD_REGNO and
4405 results in no secondary memory movements. */
4406 static enum reg_class
4407 choose_split_class (enum reg_class allocno_class
,
4408 int hard_regno ATTRIBUTE_UNUSED
,
4409 enum machine_mode mode ATTRIBUTE_UNUSED
)
4411 #ifndef SECONDARY_MEMORY_NEEDED
4412 return allocno_class
;
4415 enum reg_class cl
, best_cl
= NO_REGS
;
4416 enum reg_class hard_reg_class ATTRIBUTE_UNUSED
4417 = REGNO_REG_CLASS (hard_regno
);
4419 if (! SECONDARY_MEMORY_NEEDED (allocno_class
, allocno_class
, mode
)
4420 && TEST_HARD_REG_BIT (reg_class_contents
[allocno_class
], hard_regno
))
4421 return allocno_class
;
4423 (cl
= reg_class_subclasses
[allocno_class
][i
]) != LIM_REG_CLASSES
;
4425 if (! SECONDARY_MEMORY_NEEDED (cl
, hard_reg_class
, mode
)
4426 && ! SECONDARY_MEMORY_NEEDED (hard_reg_class
, cl
, mode
)
4427 && TEST_HARD_REG_BIT (reg_class_contents
[cl
], hard_regno
)
4428 && (best_cl
== NO_REGS
4429 || ira_class_hard_regs_num
[best_cl
] < ira_class_hard_regs_num
[cl
]))
4435 /* Do split transformations for insn INSN, which defines or uses
4436 ORIGINAL_REGNO. NEXT_USAGE_INSNS specifies which instruction in
4437 the EBB next uses ORIGINAL_REGNO; it has the same form as the
4438 "insns" field of usage_insns.
4440 The transformations look like:
4443 ... s <- p (new insn -- save)
4445 ... p <- s (new insn -- restore)
4446 <- ... p ... <- ... p ...
4448 <- ... p ... <- ... p ...
4449 ... s <- p (new insn -- save)
4451 ... p <- s (new insn -- restore)
4452 <- ... p ... <- ... p ...
4454 where p is an original pseudo got a hard register or a hard
4455 register and s is a new split pseudo. The save is put before INSN
4456 if BEFORE_P is true. Return true if we succeed in such
4459 split_reg (bool before_p
, int original_regno
, rtx insn
, rtx next_usage_insns
)
4461 enum reg_class rclass
;
4463 int hard_regno
, nregs
;
4464 rtx new_reg
, save
, restore
, usage_insn
;
4468 if (original_regno
< FIRST_PSEUDO_REGISTER
)
4470 rclass
= ira_allocno_class_translate
[REGNO_REG_CLASS (original_regno
)];
4471 hard_regno
= original_regno
;
4472 call_save_p
= false;
4477 hard_regno
= reg_renumber
[original_regno
];
4478 nregs
= hard_regno_nregs
[hard_regno
][PSEUDO_REGNO_MODE (original_regno
)];
4479 rclass
= lra_get_allocno_class (original_regno
);
4480 original_reg
= regno_reg_rtx
[original_regno
];
4481 call_save_p
= need_for_call_save_p (original_regno
);
4483 original_reg
= regno_reg_rtx
[original_regno
];
4484 lra_assert (hard_regno
>= 0);
4485 if (lra_dump_file
!= NULL
)
4486 fprintf (lra_dump_file
,
4487 " ((((((((((((((((((((((((((((((((((((((((((((((((\n");
4490 enum machine_mode mode
= GET_MODE (original_reg
);
4492 mode
= HARD_REGNO_CALLER_SAVE_MODE (hard_regno
,
4493 hard_regno_nregs
[hard_regno
][mode
],
4495 new_reg
= lra_create_new_reg (mode
, NULL_RTX
, NO_REGS
, "save");
4499 rclass
= choose_split_class (rclass
, hard_regno
,
4500 GET_MODE (original_reg
));
4501 if (rclass
== NO_REGS
)
4503 if (lra_dump_file
!= NULL
)
4505 fprintf (lra_dump_file
,
4506 " Rejecting split of %d(%s): "
4507 "no good reg class for %d(%s)\n",
4509 reg_class_names
[lra_get_allocno_class (original_regno
)],
4511 reg_class_names
[REGNO_REG_CLASS (hard_regno
)]);
4514 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
4518 new_reg
= lra_create_new_reg (GET_MODE (original_reg
), original_reg
,
4520 reg_renumber
[REGNO (new_reg
)] = hard_regno
;
4522 save
= emit_spill_move (true, new_reg
, original_reg
);
4523 if (NEXT_INSN (save
) != NULL_RTX
)
4525 lra_assert (! call_save_p
);
4526 if (lra_dump_file
!= NULL
)
4530 " Rejecting split %d->%d resulting in > 2 %s save insns:\n",
4531 original_regno
, REGNO (new_reg
), call_save_p
? "call" : "");
4532 dump_rtl_slim (lra_dump_file
, save
, NULL_RTX
, -1, 0);
4533 fprintf (lra_dump_file
,
4534 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
4538 restore
= emit_spill_move (false, new_reg
, original_reg
);
4539 if (NEXT_INSN (restore
) != NULL_RTX
)
4541 lra_assert (! call_save_p
);
4542 if (lra_dump_file
!= NULL
)
4544 fprintf (lra_dump_file
,
4545 " Rejecting split %d->%d "
4546 "resulting in > 2 %s restore insns:\n",
4547 original_regno
, REGNO (new_reg
), call_save_p
? "call" : "");
4548 dump_rtl_slim (lra_dump_file
, restore
, NULL_RTX
, -1, 0);
4549 fprintf (lra_dump_file
,
4550 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
4554 after_p
= usage_insns
[original_regno
].after_p
;
4555 lra_reg_info
[REGNO (new_reg
)].restore_regno
= original_regno
;
4556 bitmap_set_bit (&check_only_regs
, REGNO (new_reg
));
4557 bitmap_set_bit (&check_only_regs
, original_regno
);
4558 bitmap_set_bit (&lra_split_regs
, REGNO (new_reg
));
4561 if (GET_CODE (next_usage_insns
) != INSN_LIST
)
4563 usage_insn
= next_usage_insns
;
4566 usage_insn
= XEXP (next_usage_insns
, 0);
4567 lra_assert (DEBUG_INSN_P (usage_insn
));
4568 next_usage_insns
= XEXP (next_usage_insns
, 1);
4569 substitute_pseudo (&usage_insn
, original_regno
, new_reg
);
4570 lra_update_insn_regno_info (usage_insn
);
4571 if (lra_dump_file
!= NULL
)
4573 fprintf (lra_dump_file
, " Split reuse change %d->%d:\n",
4574 original_regno
, REGNO (new_reg
));
4575 dump_insn_slim (lra_dump_file
, usage_insn
);
4578 lra_assert (NOTE_P (usage_insn
) || NONDEBUG_INSN_P (usage_insn
));
4579 lra_assert (usage_insn
!= insn
|| (after_p
&& before_p
));
4580 lra_process_new_insns (usage_insn
, after_p
? NULL_RTX
: restore
,
4581 after_p
? restore
: NULL_RTX
,
4583 ? "Add reg<-save" : "Add reg<-split");
4584 lra_process_new_insns (insn
, before_p
? save
: NULL_RTX
,
4585 before_p
? NULL_RTX
: save
,
4587 ? "Add save<-reg" : "Add split<-reg");
4589 /* If we are trying to split multi-register. We should check
4590 conflicts on the next assignment sub-pass. IRA can allocate on
4591 sub-register levels, LRA do this on pseudos level right now and
4592 this discrepancy may create allocation conflicts after
4594 lra_risky_transformations_p
= true;
4595 if (lra_dump_file
!= NULL
)
4596 fprintf (lra_dump_file
,
4597 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
4601 /* Recognize that we need a split transformation for insn INSN, which
4602 defines or uses REGNO in its insn biggest MODE (we use it only if
4603 REGNO is a hard register). POTENTIAL_RELOAD_HARD_REGS contains
4604 hard registers which might be used for reloads since the EBB end.
4605 Put the save before INSN if BEFORE_P is true. MAX_UID is maximla
4606 uid before starting INSN processing. Return true if we succeed in
4607 such transformation. */
4609 split_if_necessary (int regno
, enum machine_mode mode
,
4610 HARD_REG_SET potential_reload_hard_regs
,
4611 bool before_p
, rtx insn
, int max_uid
)
4615 rtx next_usage_insns
;
4617 if (regno
< FIRST_PSEUDO_REGISTER
)
4618 nregs
= hard_regno_nregs
[regno
][mode
];
4619 for (i
= 0; i
< nregs
; i
++)
4620 if (usage_insns
[regno
+ i
].check
== curr_usage_insns_check
4621 && (next_usage_insns
= usage_insns
[regno
+ i
].insns
) != NULL_RTX
4622 /* To avoid processing the register twice or more. */
4623 && ((GET_CODE (next_usage_insns
) != INSN_LIST
4624 && INSN_UID (next_usage_insns
) < max_uid
)
4625 || (GET_CODE (next_usage_insns
) == INSN_LIST
4626 && (INSN_UID (XEXP (next_usage_insns
, 0)) < max_uid
)))
4627 && need_for_split_p (potential_reload_hard_regs
, regno
+ i
)
4628 && split_reg (before_p
, regno
+ i
, insn
, next_usage_insns
))
4633 /* Check only registers living at the current program point in the
4635 static bitmap_head live_regs
;
4637 /* Update live info in EBB given by its HEAD and TAIL insns after
4638 inheritance/split transformation. The function removes dead moves
4641 update_ebb_live_info (rtx head
, rtx tail
)
4648 basic_block last_bb
, prev_bb
, curr_bb
;
4650 struct lra_insn_reg
*reg
;
4654 last_bb
= BLOCK_FOR_INSN (tail
);
4656 for (curr_insn
= tail
;
4657 curr_insn
!= PREV_INSN (head
);
4658 curr_insn
= prev_insn
)
4660 prev_insn
= PREV_INSN (curr_insn
);
4661 /* We need to process empty blocks too. They contain
4662 NOTE_INSN_BASIC_BLOCK referring for the basic block. */
4663 if (NOTE_P (curr_insn
) && NOTE_KIND (curr_insn
) != NOTE_INSN_BASIC_BLOCK
)
4665 curr_bb
= BLOCK_FOR_INSN (curr_insn
);
4666 if (curr_bb
!= prev_bb
)
4668 if (prev_bb
!= NULL
)
4670 /* Update df_get_live_in (prev_bb): */
4671 EXECUTE_IF_SET_IN_BITMAP (&check_only_regs
, 0, j
, bi
)
4672 if (bitmap_bit_p (&live_regs
, j
))
4673 bitmap_set_bit (df_get_live_in (prev_bb
), j
);
4675 bitmap_clear_bit (df_get_live_in (prev_bb
), j
);
4677 if (curr_bb
!= last_bb
)
4679 /* Update df_get_live_out (curr_bb): */
4680 EXECUTE_IF_SET_IN_BITMAP (&check_only_regs
, 0, j
, bi
)
4682 live_p
= bitmap_bit_p (&live_regs
, j
);
4684 FOR_EACH_EDGE (e
, ei
, curr_bb
->succs
)
4685 if (bitmap_bit_p (df_get_live_in (e
->dest
), j
))
4691 bitmap_set_bit (df_get_live_out (curr_bb
), j
);
4693 bitmap_clear_bit (df_get_live_out (curr_bb
), j
);
4697 bitmap_and (&live_regs
, &check_only_regs
, df_get_live_out (curr_bb
));
4699 if (! NONDEBUG_INSN_P (curr_insn
))
4701 curr_id
= lra_get_insn_recog_data (curr_insn
);
4703 if ((set
= single_set (curr_insn
)) != NULL_RTX
&& REG_P (SET_DEST (set
))
4704 && (regno
= REGNO (SET_DEST (set
))) >= FIRST_PSEUDO_REGISTER
4705 && bitmap_bit_p (&check_only_regs
, regno
)
4706 && ! bitmap_bit_p (&live_regs
, regno
))
4708 /* See which defined values die here. */
4709 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
4710 if (reg
->type
== OP_OUT
&& ! reg
->subreg_p
)
4711 bitmap_clear_bit (&live_regs
, reg
->regno
);
4712 /* Mark each used value as live. */
4713 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
4714 if (reg
->type
!= OP_OUT
4715 && bitmap_bit_p (&check_only_regs
, reg
->regno
))
4716 bitmap_set_bit (&live_regs
, reg
->regno
);
4717 /* It is quite important to remove dead move insns because it
4718 means removing dead store. We don't need to process them for
4722 if (lra_dump_file
!= NULL
)
4724 fprintf (lra_dump_file
, " Removing dead insn:\n ");
4725 dump_insn_slim (lra_dump_file
, curr_insn
);
4727 lra_set_insn_deleted (curr_insn
);
4732 /* The structure describes info to do an inheritance for the current
4733 insn. We need to collect such info first before doing the
4734 transformations because the transformations change the insn
4735 internal representation. */
4738 /* Original regno. */
4740 /* Subsequent insns which can inherit original reg value. */
4744 /* Array containing all info for doing inheritance from the current
4746 static struct to_inherit to_inherit
[LRA_MAX_INSN_RELOADS
];
4748 /* Number elements in the previous array. */
4749 static int to_inherit_num
;
4751 /* Add inheritance info REGNO and INSNS. Their meaning is described in
4752 structure to_inherit. */
4754 add_to_inherit (int regno
, rtx insns
)
4758 for (i
= 0; i
< to_inherit_num
; i
++)
4759 if (to_inherit
[i
].regno
== regno
)
4761 lra_assert (to_inherit_num
< LRA_MAX_INSN_RELOADS
);
4762 to_inherit
[to_inherit_num
].regno
= regno
;
4763 to_inherit
[to_inherit_num
++].insns
= insns
;
4766 /* Return the last non-debug insn in basic block BB, or the block begin
4769 get_last_insertion_point (basic_block bb
)
4773 FOR_BB_INSNS_REVERSE (bb
, insn
)
4774 if (NONDEBUG_INSN_P (insn
) || NOTE_INSN_BASIC_BLOCK_P (insn
))
4779 /* Set up RES by registers living on edges FROM except the edge (FROM,
4780 TO) or by registers set up in a jump insn in BB FROM. */
4782 get_live_on_other_edges (basic_block from
, basic_block to
, bitmap res
)
4785 struct lra_insn_reg
*reg
;
4789 lra_assert (to
!= NULL
);
4791 FOR_EACH_EDGE (e
, ei
, from
->succs
)
4793 bitmap_ior_into (res
, df_get_live_in (e
->dest
));
4794 last
= get_last_insertion_point (from
);
4795 if (! JUMP_P (last
))
4797 curr_id
= lra_get_insn_recog_data (last
);
4798 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
4799 if (reg
->type
!= OP_IN
)
4800 bitmap_set_bit (res
, reg
->regno
);
4803 /* Used as a temporary results of some bitmap calculations. */
4804 static bitmap_head temp_bitmap
;
4806 /* Do inheritance/split transformations in EBB starting with HEAD and
4807 finishing on TAIL. We process EBB insns in the reverse order.
4808 Return true if we did any inheritance/split transformation in the
4811 We should avoid excessive splitting which results in worse code
4812 because of inaccurate cost calculations for spilling new split
4813 pseudos in such case. To achieve this we do splitting only if
4814 register pressure is high in given basic block and there are reload
4815 pseudos requiring hard registers. We could do more register
4816 pressure calculations at any given program point to avoid necessary
4817 splitting even more but it is to expensive and the current approach
4818 works well enough. */
4820 inherit_in_ebb (rtx head
, rtx tail
)
4822 int i
, src_regno
, dst_regno
, nregs
;
4823 bool change_p
, succ_p
;
4824 rtx prev_insn
, next_usage_insns
, set
, last_insn
;
4826 struct lra_insn_reg
*reg
;
4827 basic_block last_processed_bb
, curr_bb
= NULL
;
4828 HARD_REG_SET potential_reload_hard_regs
, live_hard_regs
;
4832 bool head_p
, after_p
;
4835 curr_usage_insns_check
++;
4836 reloads_num
= calls_num
= 0;
4837 bitmap_clear (&check_only_regs
);
4838 last_processed_bb
= NULL
;
4839 CLEAR_HARD_REG_SET (potential_reload_hard_regs
);
4840 CLEAR_HARD_REG_SET (live_hard_regs
);
4841 /* We don't process new insns generated in the loop. */
4842 for (curr_insn
= tail
; curr_insn
!= PREV_INSN (head
); curr_insn
= prev_insn
)
4844 prev_insn
= PREV_INSN (curr_insn
);
4845 if (BLOCK_FOR_INSN (curr_insn
) != NULL
)
4846 curr_bb
= BLOCK_FOR_INSN (curr_insn
);
4847 if (last_processed_bb
!= curr_bb
)
4849 /* We are at the end of BB. Add qualified living
4850 pseudos for potential splitting. */
4851 to_process
= df_get_live_out (curr_bb
);
4852 if (last_processed_bb
!= NULL
)
4854 /* We are somewhere in the middle of EBB. */
4855 get_live_on_other_edges (curr_bb
, last_processed_bb
,
4857 to_process
= &temp_bitmap
;
4859 last_processed_bb
= curr_bb
;
4860 last_insn
= get_last_insertion_point (curr_bb
);
4861 after_p
= (! JUMP_P (last_insn
)
4862 && (! CALL_P (last_insn
)
4863 || (find_reg_note (last_insn
,
4864 REG_NORETURN
, NULL_RTX
) == NULL_RTX
4865 && ! SIBLING_CALL_P (last_insn
))));
4866 REG_SET_TO_HARD_REG_SET (live_hard_regs
, df_get_live_out (curr_bb
));
4867 IOR_HARD_REG_SET (live_hard_regs
, eliminable_regset
);
4868 IOR_HARD_REG_SET (live_hard_regs
, lra_no_alloc_regs
);
4869 CLEAR_HARD_REG_SET (potential_reload_hard_regs
);
4870 EXECUTE_IF_SET_IN_BITMAP (to_process
, 0, j
, bi
)
4872 if ((int) j
>= lra_constraint_new_regno_start
)
4874 if (j
< FIRST_PSEUDO_REGISTER
|| reg_renumber
[j
] >= 0)
4876 if (j
< FIRST_PSEUDO_REGISTER
)
4877 SET_HARD_REG_BIT (live_hard_regs
, j
);
4879 add_to_hard_reg_set (&live_hard_regs
,
4880 PSEUDO_REGNO_MODE (j
),
4882 setup_next_usage_insn (j
, last_insn
, reloads_num
, after_p
);
4886 src_regno
= dst_regno
= -1;
4887 if (NONDEBUG_INSN_P (curr_insn
)
4888 && (set
= single_set (curr_insn
)) != NULL_RTX
4889 && REG_P (SET_DEST (set
)) && REG_P (SET_SRC (set
)))
4891 src_regno
= REGNO (SET_SRC (set
));
4892 dst_regno
= REGNO (SET_DEST (set
));
4894 if (src_regno
< lra_constraint_new_regno_start
4895 && src_regno
>= FIRST_PSEUDO_REGISTER
4896 && reg_renumber
[src_regno
] < 0
4897 && dst_regno
>= lra_constraint_new_regno_start
4898 && (cl
= lra_get_allocno_class (dst_regno
)) != NO_REGS
)
4900 /* 'reload_pseudo <- original_pseudo'. */
4903 if (usage_insns
[src_regno
].check
== curr_usage_insns_check
4904 && (next_usage_insns
= usage_insns
[src_regno
].insns
) != NULL_RTX
)
4905 succ_p
= inherit_reload_reg (false, src_regno
, cl
,
4906 curr_insn
, next_usage_insns
);
4910 setup_next_usage_insn (src_regno
, curr_insn
, reloads_num
, false);
4911 if (hard_reg_set_subset_p (reg_class_contents
[cl
], live_hard_regs
))
4912 IOR_HARD_REG_SET (potential_reload_hard_regs
,
4913 reg_class_contents
[cl
]);
4915 else if (src_regno
>= lra_constraint_new_regno_start
4916 && dst_regno
< lra_constraint_new_regno_start
4917 && dst_regno
>= FIRST_PSEUDO_REGISTER
4918 && reg_renumber
[dst_regno
] < 0
4919 && (cl
= lra_get_allocno_class (src_regno
)) != NO_REGS
4920 && usage_insns
[dst_regno
].check
== curr_usage_insns_check
4921 && (next_usage_insns
4922 = usage_insns
[dst_regno
].insns
) != NULL_RTX
)
4925 /* 'original_pseudo <- reload_pseudo'. */
4926 if (! JUMP_P (curr_insn
)
4927 && inherit_reload_reg (true, dst_regno
, cl
,
4928 curr_insn
, next_usage_insns
))
4931 usage_insns
[dst_regno
].check
= 0;
4932 if (hard_reg_set_subset_p (reg_class_contents
[cl
], live_hard_regs
))
4933 IOR_HARD_REG_SET (potential_reload_hard_regs
,
4934 reg_class_contents
[cl
]);
4936 else if (INSN_P (curr_insn
))
4939 int max_uid
= get_max_uid ();
4941 curr_id
= lra_get_insn_recog_data (curr_insn
);
4942 curr_static_id
= curr_id
->insn_static_data
;
4944 /* Process insn definitions. */
4945 for (iter
= 0; iter
< 2; iter
++)
4946 for (reg
= iter
== 0 ? curr_id
->regs
: curr_static_id
->hard_regs
;
4949 if (reg
->type
!= OP_IN
4950 && (dst_regno
= reg
->regno
) < lra_constraint_new_regno_start
)
4952 if (dst_regno
>= FIRST_PSEUDO_REGISTER
&& reg
->type
== OP_OUT
4953 && reg_renumber
[dst_regno
] < 0 && ! reg
->subreg_p
4954 && usage_insns
[dst_regno
].check
== curr_usage_insns_check
4955 && (next_usage_insns
4956 = usage_insns
[dst_regno
].insns
) != NULL_RTX
)
4958 struct lra_insn_reg
*r
;
4960 for (r
= curr_id
->regs
; r
!= NULL
; r
= r
->next
)
4961 if (r
->type
!= OP_OUT
&& r
->regno
== dst_regno
)
4963 /* Don't do inheritance if the pseudo is also
4964 used in the insn. */
4966 /* We can not do inheritance right now
4967 because the current insn reg info (chain
4968 regs) can change after that. */
4969 add_to_inherit (dst_regno
, next_usage_insns
);
4971 /* We can not process one reg twice here because of
4972 usage_insns invalidation. */
4973 if ((dst_regno
< FIRST_PSEUDO_REGISTER
4974 || reg_renumber
[dst_regno
] >= 0)
4975 && ! reg
->subreg_p
&& reg
->type
!= OP_IN
)
4979 if (split_if_necessary (dst_regno
, reg
->biggest_mode
,
4980 potential_reload_hard_regs
,
4981 false, curr_insn
, max_uid
))
4983 CLEAR_HARD_REG_SET (s
);
4984 if (dst_regno
< FIRST_PSEUDO_REGISTER
)
4985 add_to_hard_reg_set (&s
, reg
->biggest_mode
, dst_regno
);
4987 add_to_hard_reg_set (&s
, PSEUDO_REGNO_MODE (dst_regno
),
4988 reg_renumber
[dst_regno
]);
4989 AND_COMPL_HARD_REG_SET (live_hard_regs
, s
);
4991 /* We should invalidate potential inheritance or
4992 splitting for the current insn usages to the next
4993 usage insns (see code below) as the output pseudo
4995 if ((dst_regno
>= FIRST_PSEUDO_REGISTER
4996 && reg_renumber
[dst_regno
] < 0)
4997 || (reg
->type
== OP_OUT
&& ! reg
->subreg_p
4998 && (dst_regno
< FIRST_PSEUDO_REGISTER
4999 || reg_renumber
[dst_regno
] >= 0)))
5001 /* Invalidate and mark definitions. */
5002 if (dst_regno
>= FIRST_PSEUDO_REGISTER
)
5003 usage_insns
[dst_regno
].check
= -(int) INSN_UID (curr_insn
);
5006 nregs
= hard_regno_nregs
[dst_regno
][reg
->biggest_mode
];
5007 for (i
= 0; i
< nregs
; i
++)
5008 usage_insns
[dst_regno
+ i
].check
5009 = -(int) INSN_UID (curr_insn
);
5013 if (! JUMP_P (curr_insn
))
5014 for (i
= 0; i
< to_inherit_num
; i
++)
5015 if (inherit_reload_reg (true, to_inherit
[i
].regno
,
5016 ALL_REGS
, curr_insn
,
5017 to_inherit
[i
].insns
))
5019 if (CALL_P (curr_insn
))
5021 rtx cheap
, pat
, dest
, restore
;
5022 int regno
, hard_regno
;
5025 if ((cheap
= find_reg_note (curr_insn
,
5026 REG_RETURNED
, NULL_RTX
)) != NULL_RTX
5027 && ((cheap
= XEXP (cheap
, 0)), true)
5028 && (regno
= REGNO (cheap
)) >= FIRST_PSEUDO_REGISTER
5029 && (hard_regno
= reg_renumber
[regno
]) >= 0
5030 /* If there are pending saves/restores, the
5031 optimization is not worth. */
5032 && usage_insns
[regno
].calls_num
== calls_num
- 1
5033 && TEST_HARD_REG_BIT (call_used_reg_set
, hard_regno
))
5035 /* Restore the pseudo from the call result as
5036 REG_RETURNED note says that the pseudo value is
5037 in the call result and the pseudo is an argument
5039 pat
= PATTERN (curr_insn
);
5040 if (GET_CODE (pat
) == PARALLEL
)
5041 pat
= XVECEXP (pat
, 0, 0);
5042 dest
= SET_DEST (pat
);
5044 emit_move_insn (cheap
, copy_rtx (dest
));
5045 restore
= get_insns ();
5047 lra_process_new_insns (curr_insn
, NULL
, restore
,
5048 "Inserting call parameter restore");
5049 /* We don't need to save/restore of the pseudo from
5051 usage_insns
[regno
].calls_num
= calls_num
;
5052 bitmap_set_bit (&check_only_regs
, regno
);
5056 /* Process insn usages. */
5057 for (iter
= 0; iter
< 2; iter
++)
5058 for (reg
= iter
== 0 ? curr_id
->regs
: curr_static_id
->hard_regs
;
5061 if ((reg
->type
!= OP_OUT
5062 || (reg
->type
== OP_OUT
&& reg
->subreg_p
))
5063 && (src_regno
= reg
->regno
) < lra_constraint_new_regno_start
)
5065 if (src_regno
>= FIRST_PSEUDO_REGISTER
5066 && reg_renumber
[src_regno
] < 0 && reg
->type
== OP_IN
)
5068 if (usage_insns
[src_regno
].check
== curr_usage_insns_check
5069 && (next_usage_insns
5070 = usage_insns
[src_regno
].insns
) != NULL_RTX
5071 && NONDEBUG_INSN_P (curr_insn
))
5072 add_to_inherit (src_regno
, next_usage_insns
);
5073 else if (usage_insns
[src_regno
].check
5074 != -(int) INSN_UID (curr_insn
))
5075 /* Add usages but only if the reg is not set up
5076 in the same insn. */
5077 add_next_usage_insn (src_regno
, curr_insn
, reloads_num
);
5079 else if (src_regno
< FIRST_PSEUDO_REGISTER
5080 || reg_renumber
[src_regno
] >= 0)
5083 rtx use_insn
= curr_insn
;
5085 before_p
= (JUMP_P (curr_insn
)
5086 || (CALL_P (curr_insn
) && reg
->type
== OP_IN
));
5087 if (NONDEBUG_INSN_P (curr_insn
)
5088 && split_if_necessary (src_regno
, reg
->biggest_mode
,
5089 potential_reload_hard_regs
,
5090 before_p
, curr_insn
, max_uid
))
5093 lra_risky_transformations_p
= true;
5096 usage_insns
[src_regno
].check
= 0;
5098 use_insn
= PREV_INSN (curr_insn
);
5100 if (NONDEBUG_INSN_P (curr_insn
))
5102 if (src_regno
< FIRST_PSEUDO_REGISTER
)
5103 add_to_hard_reg_set (&live_hard_regs
,
5104 reg
->biggest_mode
, src_regno
);
5106 add_to_hard_reg_set (&live_hard_regs
,
5107 PSEUDO_REGNO_MODE (src_regno
),
5108 reg_renumber
[src_regno
]);
5110 add_next_usage_insn (src_regno
, use_insn
, reloads_num
);
5113 for (i
= 0; i
< to_inherit_num
; i
++)
5115 src_regno
= to_inherit
[i
].regno
;
5116 if (inherit_reload_reg (false, src_regno
, ALL_REGS
,
5117 curr_insn
, to_inherit
[i
].insns
))
5120 setup_next_usage_insn (src_regno
, curr_insn
, reloads_num
, false);
5123 /* We reached the start of the current basic block. */
5124 if (prev_insn
== NULL_RTX
|| prev_insn
== PREV_INSN (head
)
5125 || BLOCK_FOR_INSN (prev_insn
) != curr_bb
)
5127 /* We reached the beginning of the current block -- do
5128 rest of spliting in the current BB. */
5129 to_process
= df_get_live_in (curr_bb
);
5130 if (BLOCK_FOR_INSN (head
) != curr_bb
)
5132 /* We are somewhere in the middle of EBB. */
5133 get_live_on_other_edges (EDGE_PRED (curr_bb
, 0)->src
,
5134 curr_bb
, &temp_bitmap
);
5135 to_process
= &temp_bitmap
;
5138 EXECUTE_IF_SET_IN_BITMAP (to_process
, 0, j
, bi
)
5140 if ((int) j
>= lra_constraint_new_regno_start
)
5142 if (((int) j
< FIRST_PSEUDO_REGISTER
|| reg_renumber
[j
] >= 0)
5143 && usage_insns
[j
].check
== curr_usage_insns_check
5144 && (next_usage_insns
= usage_insns
[j
].insns
) != NULL_RTX
)
5146 if (need_for_split_p (potential_reload_hard_regs
, j
))
5148 if (lra_dump_file
!= NULL
&& head_p
)
5150 fprintf (lra_dump_file
,
5151 " ----------------------------------\n");
5154 if (split_reg (false, j
, bb_note (curr_bb
),
5158 usage_insns
[j
].check
= 0;
5166 /* This value affects EBB forming. If probability of edge from EBB to
5167 a BB is not greater than the following value, we don't add the BB
5169 #define EBB_PROBABILITY_CUTOFF ((REG_BR_PROB_BASE * 50) / 100)
5171 /* Current number of inheritance/split iteration. */
5172 int lra_inheritance_iter
;
5174 /* Entry function for inheritance/split pass. */
5176 lra_inheritance (void)
5179 basic_block bb
, start_bb
;
5182 lra_inheritance_iter
++;
5183 if (lra_inheritance_iter
> LRA_MAX_INHERITANCE_PASSES
)
5185 timevar_push (TV_LRA_INHERITANCE
);
5186 if (lra_dump_file
!= NULL
)
5187 fprintf (lra_dump_file
, "\n********** Inheritance #%d: **********\n\n",
5188 lra_inheritance_iter
);
5189 curr_usage_insns_check
= 0;
5190 usage_insns
= XNEWVEC (struct usage_insns
, lra_constraint_new_regno_start
);
5191 for (i
= 0; i
< lra_constraint_new_regno_start
; i
++)
5192 usage_insns
[i
].check
= 0;
5193 bitmap_initialize (&check_only_regs
, ®_obstack
);
5194 bitmap_initialize (&live_regs
, ®_obstack
);
5195 bitmap_initialize (&temp_bitmap
, ®_obstack
);
5196 bitmap_initialize (&ebb_global_regs
, ®_obstack
);
5200 if (lra_dump_file
!= NULL
)
5201 fprintf (lra_dump_file
, "EBB");
5202 /* Form a EBB starting with BB. */
5203 bitmap_clear (&ebb_global_regs
);
5204 bitmap_ior_into (&ebb_global_regs
, df_get_live_in (bb
));
5207 if (lra_dump_file
!= NULL
)
5208 fprintf (lra_dump_file
, " %d", bb
->index
);
5209 if (bb
->next_bb
== EXIT_BLOCK_PTR
|| LABEL_P (BB_HEAD (bb
->next_bb
)))
5211 e
= find_fallthru_edge (bb
->succs
);
5214 if (e
->probability
<= EBB_PROBABILITY_CUTOFF
)
5218 bitmap_ior_into (&ebb_global_regs
, df_get_live_out (bb
));
5219 if (lra_dump_file
!= NULL
)
5220 fprintf (lra_dump_file
, "\n");
5221 if (inherit_in_ebb (BB_HEAD (start_bb
), BB_END (bb
)))
5222 /* Remember that the EBB head and tail can change in
5224 update_ebb_live_info (BB_HEAD (start_bb
), BB_END (bb
));
5226 bitmap_clear (&ebb_global_regs
);
5227 bitmap_clear (&temp_bitmap
);
5228 bitmap_clear (&live_regs
);
5229 bitmap_clear (&check_only_regs
);
5232 timevar_pop (TV_LRA_INHERITANCE
);
5237 /* This page contains code to undo failed inheritance/split
5240 /* Current number of iteration undoing inheritance/split. */
5241 int lra_undo_inheritance_iter
;
5243 /* Fix BB live info LIVE after removing pseudos created on pass doing
5244 inheritance/split which are REMOVED_PSEUDOS. */
5246 fix_bb_live_info (bitmap live
, bitmap removed_pseudos
)
5251 EXECUTE_IF_SET_IN_BITMAP (removed_pseudos
, 0, regno
, bi
)
5252 if (bitmap_clear_bit (live
, regno
))
5253 bitmap_set_bit (live
, lra_reg_info
[regno
].restore_regno
);
5256 /* Return regno of the (subreg of) REG. Otherwise, return a negative
5261 if (GET_CODE (reg
) == SUBREG
)
5262 reg
= SUBREG_REG (reg
);
5268 /* Remove inheritance/split pseudos which are in REMOVE_PSEUDOS and
5269 return true if we did any change. The undo transformations for
5270 inheritance looks like
5274 p <- i, i <- p, and i <- i3
5275 where p is original pseudo from which inheritance pseudo i was
5276 created, i and i3 are removed inheritance pseudos, i2 is another
5277 not removed inheritance pseudo. All split pseudos or other
5278 occurrences of removed inheritance pseudos are changed on the
5279 corresponding original pseudos.
5281 The function also schedules insns changed and created during
5282 inheritance/split pass for processing by the subsequent constraint
5285 remove_inheritance_pseudos (bitmap remove_pseudos
)
5288 int regno
, sregno
, prev_sregno
, dregno
, restore_regno
;
5289 rtx set
, prev_set
, prev_insn
;
5290 bool change_p
, done_p
;
5292 change_p
= ! bitmap_empty_p (remove_pseudos
);
5293 /* We can not finish the function right away if CHANGE_P is true
5294 because we need to marks insns affected by previous
5295 inheritance/split pass for processing by the subsequent
5299 fix_bb_live_info (df_get_live_in (bb
), remove_pseudos
);
5300 fix_bb_live_info (df_get_live_out (bb
), remove_pseudos
);
5301 FOR_BB_INSNS_REVERSE (bb
, curr_insn
)
5303 if (! INSN_P (curr_insn
))
5306 sregno
= dregno
= -1;
5307 if (change_p
&& NONDEBUG_INSN_P (curr_insn
)
5308 && (set
= single_set (curr_insn
)) != NULL_RTX
)
5310 dregno
= get_regno (SET_DEST (set
));
5311 sregno
= get_regno (SET_SRC (set
));
5314 if (sregno
>= 0 && dregno
>= 0)
5316 if ((bitmap_bit_p (remove_pseudos
, sregno
)
5317 && (lra_reg_info
[sregno
].restore_regno
== dregno
5318 || (bitmap_bit_p (remove_pseudos
, dregno
)
5319 && (lra_reg_info
[sregno
].restore_regno
5320 == lra_reg_info
[dregno
].restore_regno
))))
5321 || (bitmap_bit_p (remove_pseudos
, dregno
)
5322 && lra_reg_info
[dregno
].restore_regno
== sregno
))
5323 /* One of the following cases:
5324 original <- removed inheritance pseudo
5325 removed inherit pseudo <- another removed inherit pseudo
5326 removed inherit pseudo <- original pseudo
5328 removed_split_pseudo <- original_reg
5329 original_reg <- removed_split_pseudo */
5331 if (lra_dump_file
!= NULL
)
5333 fprintf (lra_dump_file
, " Removing %s:\n",
5334 bitmap_bit_p (&lra_split_regs
, sregno
)
5335 || bitmap_bit_p (&lra_split_regs
, dregno
)
5336 ? "split" : "inheritance");
5337 dump_insn_slim (lra_dump_file
, curr_insn
);
5339 lra_set_insn_deleted (curr_insn
);
5342 else if (bitmap_bit_p (remove_pseudos
, sregno
)
5343 && bitmap_bit_p (&lra_inheritance_pseudos
, sregno
))
5345 /* Search the following pattern:
5346 inherit_or_split_pseudo1 <- inherit_or_split_pseudo2
5347 original_pseudo <- inherit_or_split_pseudo1
5348 where the 2nd insn is the current insn and
5349 inherit_or_split_pseudo2 is not removed. If it is found,
5350 change the current insn onto:
5351 original_pseudo <- inherit_or_split_pseudo2. */
5352 for (prev_insn
= PREV_INSN (curr_insn
);
5353 prev_insn
!= NULL_RTX
&& ! NONDEBUG_INSN_P (prev_insn
);
5354 prev_insn
= PREV_INSN (prev_insn
))
5356 if (prev_insn
!= NULL_RTX
&& BLOCK_FOR_INSN (prev_insn
) == bb
5357 && (prev_set
= single_set (prev_insn
)) != NULL_RTX
5358 /* There should be no subregs in insn we are
5359 searching because only the original reg might
5360 be in subreg when we changed the mode of
5361 load/store for splitting. */
5362 && REG_P (SET_DEST (prev_set
))
5363 && REG_P (SET_SRC (prev_set
))
5364 && (int) REGNO (SET_DEST (prev_set
)) == sregno
5365 && ((prev_sregno
= REGNO (SET_SRC (prev_set
)))
5366 >= FIRST_PSEUDO_REGISTER
)
5367 /* As we consider chain of inheritance or
5368 splitting described in above comment we should
5369 check that sregno and prev_sregno were
5370 inheritance/split pseudos created from the
5371 same original regno. */
5372 && (lra_reg_info
[sregno
].restore_regno
5373 == lra_reg_info
[prev_sregno
].restore_regno
)
5374 && ! bitmap_bit_p (remove_pseudos
, prev_sregno
))
5376 lra_assert (GET_MODE (SET_SRC (prev_set
))
5377 == GET_MODE (regno_reg_rtx
[sregno
]));
5378 if (GET_CODE (SET_SRC (set
)) == SUBREG
)
5379 SUBREG_REG (SET_SRC (set
)) = SET_SRC (prev_set
);
5381 SET_SRC (set
) = SET_SRC (prev_set
);
5382 lra_push_insn_and_update_insn_regno_info (curr_insn
);
5383 lra_set_used_insn_alternative_by_uid
5384 (INSN_UID (curr_insn
), -1);
5386 if (lra_dump_file
!= NULL
)
5388 fprintf (lra_dump_file
, " Change reload insn:\n");
5389 dump_insn_slim (lra_dump_file
, curr_insn
);
5396 struct lra_insn_reg
*reg
;
5397 bool restored_regs_p
= false;
5398 bool kept_regs_p
= false;
5400 curr_id
= lra_get_insn_recog_data (curr_insn
);
5401 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
5404 restore_regno
= lra_reg_info
[regno
].restore_regno
;
5405 if (restore_regno
>= 0)
5407 if (change_p
&& bitmap_bit_p (remove_pseudos
, regno
))
5409 substitute_pseudo (&curr_insn
, regno
,
5410 regno_reg_rtx
[restore_regno
]);
5411 restored_regs_p
= true;
5417 if (NONDEBUG_INSN_P (curr_insn
) && kept_regs_p
)
5419 /* The instruction has changed since the previous
5420 constraints pass. */
5421 lra_push_insn_and_update_insn_regno_info (curr_insn
);
5422 lra_set_used_insn_alternative_by_uid
5423 (INSN_UID (curr_insn
), -1);
5425 else if (restored_regs_p
)
5426 /* The instruction has been restored to the form that
5427 it had during the previous constraints pass. */
5428 lra_update_insn_regno_info (curr_insn
);
5429 if (restored_regs_p
&& lra_dump_file
!= NULL
)
5431 fprintf (lra_dump_file
, " Insn after restoring regs:\n");
5432 dump_insn_slim (lra_dump_file
, curr_insn
);
5440 /* If optional reload pseudos failed to get a hard register or was not
5441 inherited, it is better to remove optional reloads. We do this
5442 transformation after undoing inheritance to figure out necessity to
5443 remove optional reloads easier. Return true if we do any
5446 undo_optional_reloads (void)
5448 bool change_p
, keep_p
;
5449 unsigned int regno
, uid
;
5450 bitmap_iterator bi
, bi2
;
5451 rtx insn
, set
, src
, dest
;
5452 bitmap_head removed_optional_reload_pseudos
, insn_bitmap
;
5454 bitmap_initialize (&removed_optional_reload_pseudos
, ®_obstack
);
5455 bitmap_copy (&removed_optional_reload_pseudos
, &lra_optional_reload_pseudos
);
5456 EXECUTE_IF_SET_IN_BITMAP (&lra_optional_reload_pseudos
, 0, regno
, bi
)
5459 if (reg_renumber
[lra_reg_info
[regno
].restore_regno
] >= 0)
5460 /* If the original pseudo changed its allocation, just
5461 removing the optional pseudo is dangerous as the original
5462 pseudo will have longer live range. */
5464 else if (reg_renumber
[regno
] >= 0)
5465 EXECUTE_IF_SET_IN_BITMAP (&lra_reg_info
[regno
].insn_bitmap
, 0, uid
, bi2
)
5467 insn
= lra_insn_recog_data
[uid
]->insn
;
5468 if ((set
= single_set (insn
)) == NULL_RTX
)
5470 src
= SET_SRC (set
);
5471 dest
= SET_DEST (set
);
5472 if (! REG_P (src
) || ! REG_P (dest
))
5474 if (REGNO (dest
) == regno
5475 /* Ignore insn for optional reloads itself. */
5476 && lra_reg_info
[regno
].restore_regno
!= (int) REGNO (src
)
5477 /* Check only inheritance on last inheritance pass. */
5478 && (int) REGNO (src
) >= new_regno_start
5479 /* Check that the optional reload was inherited. */
5480 && bitmap_bit_p (&lra_inheritance_pseudos
, REGNO (src
)))
5488 bitmap_clear_bit (&removed_optional_reload_pseudos
, regno
);
5489 if (lra_dump_file
!= NULL
)
5490 fprintf (lra_dump_file
, "Keep optional reload reg %d\n", regno
);
5493 change_p
= ! bitmap_empty_p (&removed_optional_reload_pseudos
);
5494 bitmap_initialize (&insn_bitmap
, ®_obstack
);
5495 EXECUTE_IF_SET_IN_BITMAP (&removed_optional_reload_pseudos
, 0, regno
, bi
)
5497 if (lra_dump_file
!= NULL
)
5498 fprintf (lra_dump_file
, "Remove optional reload reg %d\n", regno
);
5499 bitmap_copy (&insn_bitmap
, &lra_reg_info
[regno
].insn_bitmap
);
5500 EXECUTE_IF_SET_IN_BITMAP (&insn_bitmap
, 0, uid
, bi2
)
5502 insn
= lra_insn_recog_data
[uid
]->insn
;
5503 if ((set
= single_set (insn
)) != NULL_RTX
)
5505 src
= SET_SRC (set
);
5506 dest
= SET_DEST (set
);
5507 if (REG_P (src
) && REG_P (dest
)
5508 && ((REGNO (src
) == regno
5509 && (lra_reg_info
[regno
].restore_regno
5510 == (int) REGNO (dest
)))
5511 || (REGNO (dest
) == regno
5512 && (lra_reg_info
[regno
].restore_regno
5513 == (int) REGNO (src
)))))
5515 if (lra_dump_file
!= NULL
)
5517 fprintf (lra_dump_file
, " Deleting move %u\n",
5519 dump_insn_slim (lra_dump_file
, insn
);
5521 lra_set_insn_deleted (insn
);
5524 /* We should not worry about generation memory-memory
5525 moves here as if the corresponding inheritance did
5526 not work (inheritance pseudo did not get a hard reg),
5527 we remove the inheritance pseudo and the optional
5530 substitute_pseudo (&insn
, regno
,
5531 regno_reg_rtx
[lra_reg_info
[regno
].restore_regno
]);
5532 lra_update_insn_regno_info (insn
);
5533 if (lra_dump_file
!= NULL
)
5535 fprintf (lra_dump_file
,
5536 " Restoring original insn:\n");
5537 dump_insn_slim (lra_dump_file
, insn
);
5541 /* Clear restore_regnos. */
5542 EXECUTE_IF_SET_IN_BITMAP (&lra_optional_reload_pseudos
, 0, regno
, bi
)
5543 lra_reg_info
[regno
].restore_regno
= -1;
5544 bitmap_clear (&insn_bitmap
);
5545 bitmap_clear (&removed_optional_reload_pseudos
);
5549 /* Entry function for undoing inheritance/split transformation. Return true
5550 if we did any RTL change in this pass. */
5552 lra_undo_inheritance (void)
5555 int restore_regno
, hard_regno
;
5556 int n_all_inherit
, n_inherit
, n_all_split
, n_split
;
5557 bitmap_head remove_pseudos
;
5561 lra_undo_inheritance_iter
++;
5562 if (lra_undo_inheritance_iter
> LRA_MAX_INHERITANCE_PASSES
)
5564 if (lra_dump_file
!= NULL
)
5565 fprintf (lra_dump_file
,
5566 "\n********** Undoing inheritance #%d: **********\n\n",
5567 lra_undo_inheritance_iter
);
5568 bitmap_initialize (&remove_pseudos
, ®_obstack
);
5569 n_inherit
= n_all_inherit
= 0;
5570 EXECUTE_IF_SET_IN_BITMAP (&lra_inheritance_pseudos
, 0, regno
, bi
)
5571 if (lra_reg_info
[regno
].restore_regno
>= 0)
5574 if (reg_renumber
[regno
] < 0
5575 /* If the original pseudo changed its allocation, just
5576 removing inheritance is dangerous as for changing
5577 allocation we used shorter live-ranges. */
5578 && reg_renumber
[lra_reg_info
[regno
].restore_regno
] < 0)
5579 bitmap_set_bit (&remove_pseudos
, regno
);
5583 if (lra_dump_file
!= NULL
&& n_all_inherit
!= 0)
5584 fprintf (lra_dump_file
, "Inherit %d out of %d (%.2f%%)\n",
5585 n_inherit
, n_all_inherit
,
5586 (double) n_inherit
/ n_all_inherit
* 100);
5587 n_split
= n_all_split
= 0;
5588 EXECUTE_IF_SET_IN_BITMAP (&lra_split_regs
, 0, regno
, bi
)
5589 if ((restore_regno
= lra_reg_info
[regno
].restore_regno
) >= 0)
5592 hard_regno
= (restore_regno
>= FIRST_PSEUDO_REGISTER
5593 ? reg_renumber
[restore_regno
] : restore_regno
);
5594 if (hard_regno
< 0 || reg_renumber
[regno
] == hard_regno
)
5595 bitmap_set_bit (&remove_pseudos
, regno
);
5599 if (lra_dump_file
!= NULL
)
5600 fprintf (lra_dump_file
, " Keep split r%d (orig=r%d)\n",
5601 regno
, restore_regno
);
5604 if (lra_dump_file
!= NULL
&& n_all_split
!= 0)
5605 fprintf (lra_dump_file
, "Split %d out of %d (%.2f%%)\n",
5606 n_split
, n_all_split
,
5607 (double) n_split
/ n_all_split
* 100);
5608 change_p
= remove_inheritance_pseudos (&remove_pseudos
);
5609 bitmap_clear (&remove_pseudos
);
5610 /* Clear restore_regnos. */
5611 EXECUTE_IF_SET_IN_BITMAP (&lra_inheritance_pseudos
, 0, regno
, bi
)
5612 lra_reg_info
[regno
].restore_regno
= -1;
5613 EXECUTE_IF_SET_IN_BITMAP (&lra_split_regs
, 0, regno
, bi
)
5614 lra_reg_info
[regno
].restore_regno
= -1;
5615 change_p
= undo_optional_reloads () || change_p
;