1 /* Code for RTL transformations to satisfy insn constraints.
2 Copyright (C) 2010-2014 Free Software Foundation, Inc.
3 Contributed by Vladimir Makarov <vmakarov@redhat.com>.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 3, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
22 /* This file contains code for 3 passes: constraint pass,
23 inheritance/split pass, and pass for undoing failed inheritance and
26 The major goal of constraint pass is to transform RTL to satisfy
27 insn and address constraints by:
28 o choosing insn alternatives;
29 o generating *reload insns* (or reloads in brief) and *reload
30 pseudos* which will get necessary hard registers later;
31 o substituting pseudos with equivalent values and removing the
32 instructions that initialized those pseudos.
34 The constraint pass has biggest and most complicated code in LRA.
35 There are a lot of important details like:
36 o reuse of input reload pseudos to simplify reload pseudo
38 o some heuristics to choose insn alternative to improve the
42 The pass is mimicking former reload pass in alternative choosing
43 because the reload pass is oriented to current machine description
44 model. It might be changed if the machine description model is
47 There is special code for preventing all LRA and this pass cycling
50 On the first iteration of the pass we process every instruction and
51 choose an alternative for each one. On subsequent iterations we try
52 to avoid reprocessing instructions if we can be sure that the old
53 choice is still valid.
55 The inheritance/spilt pass is to transform code to achieve
56 ineheritance and live range splitting. It is done on backward
59 The inheritance optimization goal is to reuse values in hard
60 registers. There is analogous optimization in old reload pass. The
61 inheritance is achieved by following transformation:
63 reload_p1 <- p reload_p1 <- p
64 ... new_p <- reload_p1
66 reload_p2 <- p reload_p2 <- new_p
68 where p is spilled and not changed between the insns. Reload_p1 is
69 also called *original pseudo* and new_p is called *inheritance
72 The subsequent assignment pass will try to assign the same (or
73 another if it is not possible) hard register to new_p as to
74 reload_p1 or reload_p2.
76 If the assignment pass fails to assign a hard register to new_p,
77 this file will undo the inheritance and restore the original code.
78 This is because implementing the above sequence with a spilled
79 new_p would make the code much worse. The inheritance is done in
80 EBB scope. The above is just a simplified example to get an idea
81 of the inheritance as the inheritance is also done for non-reload
84 Splitting (transformation) is also done in EBB scope on the same
85 pass as the inheritance:
87 r <- ... or ... <- r r <- ... or ... <- r
88 ... s <- r (new insn -- save)
90 ... r <- s (new insn -- restore)
93 The *split pseudo* s is assigned to the hard register of the
94 original pseudo or hard register r.
97 o In EBBs with high register pressure for global pseudos (living
98 in at least 2 BBs) and assigned to hard registers when there
99 are more one reloads needing the hard registers;
100 o for pseudos needing save/restore code around calls.
102 If the split pseudo still has the same hard register as the
103 original pseudo after the subsequent assignment pass or the
104 original pseudo was split, the opposite transformation is done on
105 the same pass for undoing inheritance. */
111 #include "coretypes.h"
113 #include "hard-reg-set.h"
117 #include "insn-config.h"
118 #include "insn-codes.h"
121 #include "addresses.h"
123 #include "function.h"
125 #include "basic-block.h"
130 #include "rtl-error.h"
133 /* Value of LRA_CURR_RELOAD_NUM at the beginning of BB of the current
134 insn. Remember that LRA_CURR_RELOAD_NUM is the number of emitted
136 static int bb_reload_num
;
138 /* The current insn being processed and corresponding its single set
139 (NULL otherwise), its data (basic block, the insn data, the insn
140 static data, and the mode of each operand). */
141 static rtx curr_insn
;
142 static rtx curr_insn_set
;
143 static basic_block curr_bb
;
144 static lra_insn_recog_data_t curr_id
;
145 static struct lra_static_insn_data
*curr_static_id
;
146 static enum machine_mode curr_operand_mode
[MAX_RECOG_OPERANDS
];
150 /* Start numbers for new registers and insns at the current constraints
152 static int new_regno_start
;
153 static int new_insn_uid_start
;
155 /* If LOC is nonnull, strip any outer subreg from it. */
157 strip_subreg (rtx
*loc
)
159 return loc
&& GET_CODE (*loc
) == SUBREG
? &SUBREG_REG (*loc
) : loc
;
162 /* Return hard regno of REGNO or if it is was not assigned to a hard
163 register, use a hard register from its allocno class. */
165 get_try_hard_regno (int regno
)
168 enum reg_class rclass
;
170 if ((hard_regno
= regno
) >= FIRST_PSEUDO_REGISTER
)
171 hard_regno
= lra_get_regno_hard_regno (regno
);
174 rclass
= lra_get_allocno_class (regno
);
175 if (rclass
== NO_REGS
)
177 return ira_class_hard_regs
[rclass
][0];
180 /* Return final hard regno (plus offset) which will be after
181 elimination. We do this for matching constraints because the final
182 hard regno could have a different class. */
184 get_final_hard_regno (int hard_regno
, int offset
)
188 hard_regno
= lra_get_elimination_hard_regno (hard_regno
);
189 return hard_regno
+ offset
;
192 /* Return hard regno of X after removing subreg and making
193 elimination. If X is not a register or subreg of register, return
194 -1. For pseudo use its assignment. */
196 get_hard_regno (rtx x
)
199 int offset
, hard_regno
;
202 if (GET_CODE (x
) == SUBREG
)
203 reg
= SUBREG_REG (x
);
206 if ((hard_regno
= REGNO (reg
)) >= FIRST_PSEUDO_REGISTER
)
207 hard_regno
= lra_get_regno_hard_regno (hard_regno
);
211 if (GET_CODE (x
) == SUBREG
)
212 offset
+= subreg_regno_offset (hard_regno
, GET_MODE (reg
),
213 SUBREG_BYTE (x
), GET_MODE (x
));
214 return get_final_hard_regno (hard_regno
, offset
);
217 /* If REGNO is a hard register or has been allocated a hard register,
218 return the class of that register. If REGNO is a reload pseudo
219 created by the current constraints pass, return its allocno class.
220 Return NO_REGS otherwise. */
221 static enum reg_class
222 get_reg_class (int regno
)
226 if ((hard_regno
= regno
) >= FIRST_PSEUDO_REGISTER
)
227 hard_regno
= lra_get_regno_hard_regno (regno
);
230 hard_regno
= get_final_hard_regno (hard_regno
, 0);
231 return REGNO_REG_CLASS (hard_regno
);
233 if (regno
>= new_regno_start
)
234 return lra_get_allocno_class (regno
);
238 /* Return true if REG satisfies (or will satisfy) reg class constraint
239 CL. Use elimination first if REG is a hard register. If REG is a
240 reload pseudo created by this constraints pass, assume that it will
241 be allocated a hard register from its allocno class, but allow that
242 class to be narrowed to CL if it is currently a superset of CL.
244 If NEW_CLASS is nonnull, set *NEW_CLASS to the new allocno class of
245 REGNO (reg), or NO_REGS if no change in its class was needed. */
247 in_class_p (rtx reg
, enum reg_class cl
, enum reg_class
*new_class
)
249 enum reg_class rclass
, common_class
;
250 enum machine_mode reg_mode
;
251 int class_size
, hard_regno
, nregs
, i
, j
;
252 int regno
= REGNO (reg
);
254 if (new_class
!= NULL
)
255 *new_class
= NO_REGS
;
256 if (regno
< FIRST_PSEUDO_REGISTER
)
259 rtx
*final_loc
= &final_reg
;
261 lra_eliminate_reg_if_possible (final_loc
);
262 return TEST_HARD_REG_BIT (reg_class_contents
[cl
], REGNO (*final_loc
));
264 reg_mode
= GET_MODE (reg
);
265 rclass
= get_reg_class (regno
);
266 if (regno
< new_regno_start
267 /* Do not allow the constraints for reload instructions to
268 influence the classes of new pseudos. These reloads are
269 typically moves that have many alternatives, and restricting
270 reload pseudos for one alternative may lead to situations
271 where other reload pseudos are no longer allocatable. */
272 || (INSN_UID (curr_insn
) >= new_insn_uid_start
273 && curr_insn_set
!= NULL
274 && ((OBJECT_P (SET_SRC (curr_insn_set
))
275 && ! CONSTANT_P (SET_SRC (curr_insn_set
)))
276 || (GET_CODE (SET_SRC (curr_insn_set
)) == SUBREG
277 && OBJECT_P (SUBREG_REG (SET_SRC (curr_insn_set
)))
278 && ! CONSTANT_P (SUBREG_REG (SET_SRC (curr_insn_set
)))))))
279 /* When we don't know what class will be used finally for reload
280 pseudos, we use ALL_REGS. */
281 return ((regno
>= new_regno_start
&& rclass
== ALL_REGS
)
282 || (rclass
!= NO_REGS
&& ira_class_subset_p
[rclass
][cl
]
283 && ! hard_reg_set_subset_p (reg_class_contents
[cl
],
284 lra_no_alloc_regs
)));
287 common_class
= ira_reg_class_subset
[rclass
][cl
];
288 if (new_class
!= NULL
)
289 *new_class
= common_class
;
290 if (hard_reg_set_subset_p (reg_class_contents
[common_class
],
293 /* Check that there are enough allocatable regs. */
294 class_size
= ira_class_hard_regs_num
[common_class
];
295 for (i
= 0; i
< class_size
; i
++)
297 hard_regno
= ira_class_hard_regs
[common_class
][i
];
298 nregs
= hard_regno_nregs
[hard_regno
][reg_mode
];
301 for (j
= 0; j
< nregs
; j
++)
302 if (TEST_HARD_REG_BIT (lra_no_alloc_regs
, hard_regno
+ j
)
303 || ! TEST_HARD_REG_BIT (reg_class_contents
[common_class
],
313 /* Return true if REGNO satisfies a memory constraint. */
317 return get_reg_class (regno
) == NO_REGS
;
320 /* Return 1 if ADDR is a valid memory address for mode MODE in address
321 space AS, and check that each pseudo has the proper kind of hard
324 valid_address_p (enum machine_mode mode ATTRIBUTE_UNUSED
,
325 rtx addr
, addr_space_t as
)
327 #ifdef GO_IF_LEGITIMATE_ADDRESS
328 lra_assert (ADDR_SPACE_GENERIC_P (as
));
329 GO_IF_LEGITIMATE_ADDRESS (mode
, addr
, win
);
335 return targetm
.addr_space
.legitimate_address_p (mode
, addr
, 0, as
);
340 /* Temporarily eliminates registers in an address (for the lifetime of
342 class address_eliminator
{
344 address_eliminator (struct address_info
*ad
);
345 ~address_eliminator ();
348 struct address_info
*m_ad
;
356 address_eliminator::address_eliminator (struct address_info
*ad
)
358 m_base_loc (strip_subreg (ad
->base_term
)),
359 m_base_reg (NULL_RTX
),
360 m_index_loc (strip_subreg (ad
->index_term
)),
361 m_index_reg (NULL_RTX
)
363 if (m_base_loc
!= NULL
)
365 m_base_reg
= *m_base_loc
;
366 lra_eliminate_reg_if_possible (m_base_loc
);
367 if (m_ad
->base_term2
!= NULL
)
368 *m_ad
->base_term2
= *m_ad
->base_term
;
370 if (m_index_loc
!= NULL
)
372 m_index_reg
= *m_index_loc
;
373 lra_eliminate_reg_if_possible (m_index_loc
);
377 address_eliminator::~address_eliminator ()
379 if (m_base_loc
&& *m_base_loc
!= m_base_reg
)
381 *m_base_loc
= m_base_reg
;
382 if (m_ad
->base_term2
!= NULL
)
383 *m_ad
->base_term2
= *m_ad
->base_term
;
385 if (m_index_loc
&& *m_index_loc
!= m_index_reg
)
386 *m_index_loc
= m_index_reg
;
389 /* Return true if the eliminated form of AD is a legitimate target address. */
391 valid_address_p (struct address_info
*ad
)
393 address_eliminator
eliminator (ad
);
394 return valid_address_p (ad
->mode
, *ad
->outer
, ad
->as
);
397 /* Return true if the eliminated form of memory reference OP satisfies
398 extra memory constraint CONSTRAINT. */
400 satisfies_memory_constraint_p (rtx op
, enum constraint_num constraint
)
402 struct address_info ad
;
404 decompose_mem_address (&ad
, op
);
405 address_eliminator
eliminator (&ad
);
406 return constraint_satisfied_p (op
, constraint
);
409 /* Return true if the eliminated form of address AD satisfies extra
410 address constraint CONSTRAINT. */
412 satisfies_address_constraint_p (struct address_info
*ad
,
413 enum constraint_num constraint
)
415 address_eliminator
eliminator (ad
);
416 return constraint_satisfied_p (*ad
->outer
, constraint
);
419 /* Return true if the eliminated form of address OP satisfies extra
420 address constraint CONSTRAINT. */
422 satisfies_address_constraint_p (rtx op
, enum constraint_num constraint
)
424 struct address_info ad
;
426 decompose_lea_address (&ad
, &op
);
427 return satisfies_address_constraint_p (&ad
, constraint
);
430 /* Initiate equivalences for LRA. As we keep original equivalences
431 before any elimination, we need to make copies otherwise any change
432 in insns might change the equivalences. */
434 lra_init_equiv (void)
436 ira_expand_reg_equiv ();
437 for (int i
= FIRST_PSEUDO_REGISTER
; i
< max_reg_num (); i
++)
441 if ((res
= ira_reg_equiv
[i
].memory
) != NULL_RTX
)
442 ira_reg_equiv
[i
].memory
= copy_rtx (res
);
443 if ((res
= ira_reg_equiv
[i
].invariant
) != NULL_RTX
)
444 ira_reg_equiv
[i
].invariant
= copy_rtx (res
);
448 static rtx
loc_equivalence_callback (rtx
, const_rtx
, void *);
450 /* Update equivalence for REGNO. We need to this as the equivalence
451 might contain other pseudos which are changed by their
454 update_equiv (int regno
)
458 if ((x
= ira_reg_equiv
[regno
].memory
) != NULL_RTX
)
459 ira_reg_equiv
[regno
].memory
460 = simplify_replace_fn_rtx (x
, NULL_RTX
, loc_equivalence_callback
,
462 if ((x
= ira_reg_equiv
[regno
].invariant
) != NULL_RTX
)
463 ira_reg_equiv
[regno
].invariant
464 = simplify_replace_fn_rtx (x
, NULL_RTX
, loc_equivalence_callback
,
468 /* If we have decided to substitute X with another value, return that
469 value, otherwise return X. */
476 if (! REG_P (x
) || (regno
= REGNO (x
)) < FIRST_PSEUDO_REGISTER
477 || ! ira_reg_equiv
[regno
].defined_p
478 || ! ira_reg_equiv
[regno
].profitable_p
479 || lra_get_regno_hard_regno (regno
) >= 0)
481 if ((res
= ira_reg_equiv
[regno
].memory
) != NULL_RTX
)
483 if ((res
= ira_reg_equiv
[regno
].constant
) != NULL_RTX
)
485 if ((res
= ira_reg_equiv
[regno
].invariant
) != NULL_RTX
)
490 /* If we have decided to substitute X with the equivalent value,
491 return that value after elimination for INSN, otherwise return
494 get_equiv_with_elimination (rtx x
, rtx insn
)
496 rtx res
= get_equiv (x
);
498 if (x
== res
|| CONSTANT_P (res
))
500 return lra_eliminate_regs_1 (insn
, res
, GET_MODE (res
), false, false, true);
503 /* Set up curr_operand_mode. */
505 init_curr_operand_mode (void)
507 int nop
= curr_static_id
->n_operands
;
508 for (int i
= 0; i
< nop
; i
++)
510 enum machine_mode mode
= GET_MODE (*curr_id
->operand_loc
[i
]);
511 if (mode
== VOIDmode
)
513 /* The .md mode for address operands is the mode of the
514 addressed value rather than the mode of the address itself. */
515 if (curr_id
->icode
>= 0 && curr_static_id
->operand
[i
].is_address
)
518 mode
= curr_static_id
->operand
[i
].mode
;
520 curr_operand_mode
[i
] = mode
;
526 /* The page contains code to reuse input reloads. */
528 /* Structure describes input reload of the current insns. */
531 /* Reloaded value. */
533 /* Reload pseudo used. */
537 /* The number of elements in the following array. */
538 static int curr_insn_input_reloads_num
;
539 /* Array containing info about input reloads. It is used to find the
540 same input reload and reuse the reload pseudo in this case. */
541 static struct input_reload curr_insn_input_reloads
[LRA_MAX_INSN_RELOADS
];
543 /* Initiate data concerning reuse of input reloads for the current
546 init_curr_insn_input_reloads (void)
548 curr_insn_input_reloads_num
= 0;
551 /* Create a new pseudo using MODE, RCLASS, ORIGINAL or reuse already
552 created input reload pseudo (only if TYPE is not OP_OUT). Don't
553 reuse pseudo if IN_SUBREG_P is true and the reused pseudo should be
554 wrapped up in SUBREG. The result pseudo is returned through
555 RESULT_REG. Return TRUE if we created a new pseudo, FALSE if we
556 reused the already created input reload pseudo. Use TITLE to
557 describe new registers for debug purposes. */
559 get_reload_reg (enum op_type type
, enum machine_mode mode
, rtx original
,
560 enum reg_class rclass
, bool in_subreg_p
,
561 const char *title
, rtx
*result_reg
)
564 enum reg_class new_class
;
569 = lra_create_new_reg_with_unique_value (mode
, original
, rclass
, title
);
572 /* Prevent reuse value of expression with side effects,
573 e.g. volatile memory. */
574 if (! side_effects_p (original
))
575 for (i
= 0; i
< curr_insn_input_reloads_num
; i
++)
576 if (rtx_equal_p (curr_insn_input_reloads
[i
].input
, original
)
577 && in_class_p (curr_insn_input_reloads
[i
].reg
, rclass
, &new_class
))
579 rtx reg
= curr_insn_input_reloads
[i
].reg
;
581 /* If input is equal to original and both are VOIDmode,
582 GET_MODE (reg) might be still different from mode.
583 Ensure we don't return *result_reg with wrong mode. */
584 if (GET_MODE (reg
) != mode
)
588 if (GET_MODE_SIZE (GET_MODE (reg
)) < GET_MODE_SIZE (mode
))
590 reg
= lowpart_subreg (mode
, reg
, GET_MODE (reg
));
591 if (reg
== NULL_RTX
|| GET_CODE (reg
) != SUBREG
)
595 if (lra_dump_file
!= NULL
)
597 fprintf (lra_dump_file
, " Reuse r%d for reload ", regno
);
598 dump_value_slim (lra_dump_file
, original
, 1);
600 if (new_class
!= lra_get_allocno_class (regno
))
601 lra_change_class (regno
, new_class
, ", change to", false);
602 if (lra_dump_file
!= NULL
)
603 fprintf (lra_dump_file
, "\n");
606 *result_reg
= lra_create_new_reg (mode
, original
, rclass
, title
);
607 lra_assert (curr_insn_input_reloads_num
< LRA_MAX_INSN_RELOADS
);
608 curr_insn_input_reloads
[curr_insn_input_reloads_num
].input
= original
;
609 curr_insn_input_reloads
[curr_insn_input_reloads_num
++].reg
= *result_reg
;
615 /* The page contains code to extract memory address parts. */
617 /* Wrapper around REGNO_OK_FOR_INDEX_P, to allow pseudos. */
619 ok_for_index_p_nonstrict (rtx reg
)
621 unsigned regno
= REGNO (reg
);
623 return regno
>= FIRST_PSEUDO_REGISTER
|| REGNO_OK_FOR_INDEX_P (regno
);
626 /* A version of regno_ok_for_base_p for use here, when all pseudos
627 should count as OK. Arguments as for regno_ok_for_base_p. */
629 ok_for_base_p_nonstrict (rtx reg
, enum machine_mode mode
, addr_space_t as
,
630 enum rtx_code outer_code
, enum rtx_code index_code
)
632 unsigned regno
= REGNO (reg
);
634 if (regno
>= FIRST_PSEUDO_REGISTER
)
636 return ok_for_base_p_1 (regno
, mode
, as
, outer_code
, index_code
);
641 /* The page contains major code to choose the current insn alternative
642 and generate reloads for it. */
644 /* Return the offset from REGNO of the least significant register
647 This function is used to tell whether two registers satisfy
648 a matching constraint. (reg:MODE1 REGNO1) matches (reg:MODE2 REGNO2) if:
650 REGNO1 + lra_constraint_offset (REGNO1, MODE1)
651 == REGNO2 + lra_constraint_offset (REGNO2, MODE2) */
653 lra_constraint_offset (int regno
, enum machine_mode mode
)
655 lra_assert (regno
< FIRST_PSEUDO_REGISTER
);
656 if (WORDS_BIG_ENDIAN
&& GET_MODE_SIZE (mode
) > UNITS_PER_WORD
657 && SCALAR_INT_MODE_P (mode
))
658 return hard_regno_nregs
[regno
][mode
] - 1;
662 /* Like rtx_equal_p except that it allows a REG and a SUBREG to match
663 if they are the same hard reg, and has special hacks for
664 auto-increment and auto-decrement. This is specifically intended for
665 process_alt_operands to use in determining whether two operands
666 match. X is the operand whose number is the lower of the two.
668 It is supposed that X is the output operand and Y is the input
669 operand. Y_HARD_REGNO is the final hard regno of register Y or
670 register in subreg Y as we know it now. Otherwise, it is a
673 operands_match_p (rtx x
, rtx y
, int y_hard_regno
)
676 RTX_CODE code
= GET_CODE (x
);
681 if ((code
== REG
|| (code
== SUBREG
&& REG_P (SUBREG_REG (x
))))
682 && (REG_P (y
) || (GET_CODE (y
) == SUBREG
&& REG_P (SUBREG_REG (y
)))))
686 i
= get_hard_regno (x
);
690 if ((j
= y_hard_regno
) < 0)
693 i
+= lra_constraint_offset (i
, GET_MODE (x
));
694 j
+= lra_constraint_offset (j
, GET_MODE (y
));
699 /* If two operands must match, because they are really a single
700 operand of an assembler insn, then two post-increments are invalid
701 because the assembler insn would increment only once. On the
702 other hand, a post-increment matches ordinary indexing if the
703 post-increment is the output operand. */
704 if (code
== POST_DEC
|| code
== POST_INC
|| code
== POST_MODIFY
)
705 return operands_match_p (XEXP (x
, 0), y
, y_hard_regno
);
707 /* Two pre-increments are invalid because the assembler insn would
708 increment only once. On the other hand, a pre-increment matches
709 ordinary indexing if the pre-increment is the input operand. */
710 if (GET_CODE (y
) == PRE_DEC
|| GET_CODE (y
) == PRE_INC
711 || GET_CODE (y
) == PRE_MODIFY
)
712 return operands_match_p (x
, XEXP (y
, 0), -1);
716 if (code
== REG
&& GET_CODE (y
) == SUBREG
&& REG_P (SUBREG_REG (y
))
717 && x
== SUBREG_REG (y
))
719 if (GET_CODE (y
) == REG
&& code
== SUBREG
&& REG_P (SUBREG_REG (x
))
720 && SUBREG_REG (x
) == y
)
723 /* Now we have disposed of all the cases in which different rtx
725 if (code
!= GET_CODE (y
))
728 /* (MULT:SI x y) and (MULT:HI x y) are NOT equivalent. */
729 if (GET_MODE (x
) != GET_MODE (y
))
738 return XEXP (x
, 0) == XEXP (y
, 0);
740 return XSTR (x
, 0) == XSTR (y
, 0);
746 /* Compare the elements. If any pair of corresponding elements fail
747 to match, return false for the whole things. */
749 fmt
= GET_RTX_FORMAT (code
);
750 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
756 if (XWINT (x
, i
) != XWINT (y
, i
))
761 if (XINT (x
, i
) != XINT (y
, i
))
766 val
= operands_match_p (XEXP (x
, i
), XEXP (y
, i
), -1);
775 if (XVECLEN (x
, i
) != XVECLEN (y
, i
))
777 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; --j
)
779 val
= operands_match_p (XVECEXP (x
, i
, j
), XVECEXP (y
, i
, j
), -1);
785 /* It is believed that rtx's at this level will never
786 contain anything but integers and other rtx's, except for
787 within LABEL_REFs and SYMBOL_REFs. */
795 /* True if X is a constant that can be forced into the constant pool.
796 MODE is the mode of the operand, or VOIDmode if not known. */
797 #define CONST_POOL_OK_P(MODE, X) \
798 ((MODE) != VOIDmode \
800 && GET_CODE (X) != HIGH \
801 && !targetm.cannot_force_const_mem (MODE, X))
803 /* True if C is a non-empty register class that has too few registers
804 to be safely used as a reload target class. */
805 #define SMALL_REGISTER_CLASS_P(C) \
806 (ira_class_hard_regs_num [(C)] == 1 \
807 || (ira_class_hard_regs_num [(C)] >= 1 \
808 && targetm.class_likely_spilled_p (C)))
810 /* If REG is a reload pseudo, try to make its class satisfying CL. */
812 narrow_reload_pseudo_class (rtx reg
, enum reg_class cl
)
814 enum reg_class rclass
;
816 /* Do not make more accurate class from reloads generated. They are
817 mostly moves with a lot of constraints. Making more accurate
818 class may results in very narrow class and impossibility of find
819 registers for several reloads of one insn. */
820 if (INSN_UID (curr_insn
) >= new_insn_uid_start
)
822 if (GET_CODE (reg
) == SUBREG
)
823 reg
= SUBREG_REG (reg
);
824 if (! REG_P (reg
) || (int) REGNO (reg
) < new_regno_start
)
826 if (in_class_p (reg
, cl
, &rclass
) && rclass
!= cl
)
827 lra_change_class (REGNO (reg
), rclass
, " Change to", true);
830 /* Generate reloads for matching OUT and INS (array of input operand
831 numbers with end marker -1) with reg class GOAL_CLASS. Add input
832 and output reloads correspondingly to the lists *BEFORE and *AFTER.
833 OUT might be negative. In this case we generate input reloads for
834 matched input operands INS. */
836 match_reload (signed char out
, signed char *ins
, enum reg_class goal_class
,
837 rtx
*before
, rtx
*after
)
840 rtx new_in_reg
, new_out_reg
, reg
, clobber
;
841 enum machine_mode inmode
, outmode
;
842 rtx in_rtx
= *curr_id
->operand_loc
[ins
[0]];
843 rtx out_rtx
= out
< 0 ? in_rtx
: *curr_id
->operand_loc
[out
];
845 inmode
= curr_operand_mode
[ins
[0]];
846 outmode
= out
< 0 ? inmode
: curr_operand_mode
[out
];
847 push_to_sequence (*before
);
848 if (inmode
!= outmode
)
850 if (GET_MODE_SIZE (inmode
) > GET_MODE_SIZE (outmode
))
853 = lra_create_new_reg_with_unique_value (inmode
, in_rtx
,
855 if (SCALAR_INT_MODE_P (inmode
))
856 new_out_reg
= gen_lowpart_SUBREG (outmode
, reg
);
858 new_out_reg
= gen_rtx_SUBREG (outmode
, reg
, 0);
859 LRA_SUBREG_P (new_out_reg
) = 1;
860 /* If the input reg is dying here, we can use the same hard
861 register for REG and IN_RTX. We do it only for original
862 pseudos as reload pseudos can die although original
863 pseudos still live where reload pseudos dies. */
864 if (REG_P (in_rtx
) && (int) REGNO (in_rtx
) < lra_new_regno_start
865 && find_regno_note (curr_insn
, REG_DEAD
, REGNO (in_rtx
)))
866 lra_assign_reg_val (REGNO (in_rtx
), REGNO (reg
));
871 = lra_create_new_reg_with_unique_value (outmode
, out_rtx
,
873 if (SCALAR_INT_MODE_P (outmode
))
874 new_in_reg
= gen_lowpart_SUBREG (inmode
, reg
);
876 new_in_reg
= gen_rtx_SUBREG (inmode
, reg
, 0);
877 /* NEW_IN_REG is non-paradoxical subreg. We don't want
878 NEW_OUT_REG living above. We add clobber clause for
879 this. This is just a temporary clobber. We can remove
880 it at the end of LRA work. */
881 clobber
= emit_clobber (new_out_reg
);
882 LRA_TEMP_CLOBBER_P (PATTERN (clobber
)) = 1;
883 LRA_SUBREG_P (new_in_reg
) = 1;
884 if (GET_CODE (in_rtx
) == SUBREG
)
886 rtx subreg_reg
= SUBREG_REG (in_rtx
);
888 /* If SUBREG_REG is dying here and sub-registers IN_RTX
889 and NEW_IN_REG are similar, we can use the same hard
890 register for REG and SUBREG_REG. */
891 if (REG_P (subreg_reg
)
892 && (int) REGNO (subreg_reg
) < lra_new_regno_start
893 && GET_MODE (subreg_reg
) == outmode
894 && SUBREG_BYTE (in_rtx
) == SUBREG_BYTE (new_in_reg
)
895 && find_regno_note (curr_insn
, REG_DEAD
, REGNO (subreg_reg
)))
896 lra_assign_reg_val (REGNO (subreg_reg
), REGNO (reg
));
902 /* Pseudos have values -- see comments for lra_reg_info.
903 Different pseudos with the same value do not conflict even if
904 they live in the same place. When we create a pseudo we
905 assign value of original pseudo (if any) from which we
906 created the new pseudo. If we create the pseudo from the
907 input pseudo, the new pseudo will no conflict with the input
908 pseudo which is wrong when the input pseudo lives after the
909 insn and as the new pseudo value is changed by the insn
910 output. Therefore we create the new pseudo from the output.
912 We cannot reuse the current output register because we might
913 have a situation like "a <- a op b", where the constraints
914 force the second input operand ("b") to match the output
915 operand ("a"). "b" must then be copied into a new register
916 so that it doesn't clobber the current value of "a". */
918 new_in_reg
= new_out_reg
919 = lra_create_new_reg_with_unique_value (outmode
, out_rtx
,
922 /* In operand can be got from transformations before processing insn
923 constraints. One example of such transformations is subreg
924 reloading (see function simplify_operand_subreg). The new
925 pseudos created by the transformations might have inaccurate
926 class (ALL_REGS) and we should make their classes more
928 narrow_reload_pseudo_class (in_rtx
, goal_class
);
929 lra_emit_move (copy_rtx (new_in_reg
), in_rtx
);
930 *before
= get_insns ();
932 for (i
= 0; (in
= ins
[i
]) >= 0; i
++)
935 (GET_MODE (*curr_id
->operand_loc
[in
]) == VOIDmode
936 || GET_MODE (new_in_reg
) == GET_MODE (*curr_id
->operand_loc
[in
]));
937 *curr_id
->operand_loc
[in
] = new_in_reg
;
939 lra_update_dups (curr_id
, ins
);
942 /* See a comment for the input operand above. */
943 narrow_reload_pseudo_class (out_rtx
, goal_class
);
944 if (find_reg_note (curr_insn
, REG_UNUSED
, out_rtx
) == NULL_RTX
)
947 lra_emit_move (out_rtx
, copy_rtx (new_out_reg
));
949 *after
= get_insns ();
952 *curr_id
->operand_loc
[out
] = new_out_reg
;
953 lra_update_dup (curr_id
, out
);
956 /* Return register class which is union of all reg classes in insn
957 constraint alternative string starting with P. */
958 static enum reg_class
959 reg_class_from_constraints (const char *p
)
962 enum reg_class op_class
= NO_REGS
;
965 switch ((c
= *p
, len
= CONSTRAINT_LEN (c
, p
)), c
)
972 op_class
= reg_class_subunion
[op_class
][GENERAL_REGS
];
976 enum constraint_num cn
= lookup_constraint (p
);
977 enum reg_class cl
= reg_class_for_constraint (cn
);
980 if (insn_extra_address_constraint (cn
))
982 = (reg_class_subunion
983 [op_class
][base_reg_class (VOIDmode
, ADDR_SPACE_GENERIC
,
988 op_class
= reg_class_subunion
[op_class
][cl
];
991 while ((p
+= len
), c
);
995 /* If OP is a register, return the class of the register as per
996 get_reg_class, otherwise return NO_REGS. */
997 static inline enum reg_class
998 get_op_class (rtx op
)
1000 return REG_P (op
) ? get_reg_class (REGNO (op
)) : NO_REGS
;
1003 /* Return generated insn mem_pseudo:=val if TO_P or val:=mem_pseudo
1004 otherwise. If modes of MEM_PSEUDO and VAL are different, use
1005 SUBREG for VAL to make them equal. */
1007 emit_spill_move (bool to_p
, rtx mem_pseudo
, rtx val
)
1009 if (GET_MODE (mem_pseudo
) != GET_MODE (val
))
1011 /* Usually size of mem_pseudo is greater than val size but in
1012 rare cases it can be less as it can be defined by target
1013 dependent macro HARD_REGNO_CALLER_SAVE_MODE. */
1016 val
= gen_rtx_SUBREG (GET_MODE (mem_pseudo
),
1017 GET_CODE (val
) == SUBREG
? SUBREG_REG (val
) : val
,
1019 LRA_SUBREG_P (val
) = 1;
1023 mem_pseudo
= gen_lowpart_SUBREG (GET_MODE (val
), mem_pseudo
);
1024 LRA_SUBREG_P (mem_pseudo
) = 1;
1028 ? gen_move_insn (mem_pseudo
, val
)
1029 : gen_move_insn (val
, mem_pseudo
));
1032 /* Process a special case insn (register move), return true if we
1033 don't need to process it anymore. INSN should be a single set
1034 insn. Set up that RTL was changed through CHANGE_P and macro
1035 SECONDARY_MEMORY_NEEDED says to use secondary memory through
1038 check_and_process_move (bool *change_p
, bool *sec_mem_p ATTRIBUTE_UNUSED
)
1041 rtx dest
, src
, dreg
, sreg
, old_sreg
, new_reg
, before
, scratch_reg
;
1042 enum reg_class dclass
, sclass
, secondary_class
;
1043 enum machine_mode sreg_mode
;
1044 secondary_reload_info sri
;
1046 lra_assert (curr_insn_set
!= NULL_RTX
);
1047 dreg
= dest
= SET_DEST (curr_insn_set
);
1048 sreg
= src
= SET_SRC (curr_insn_set
);
1049 if (GET_CODE (dest
) == SUBREG
)
1050 dreg
= SUBREG_REG (dest
);
1051 if (GET_CODE (src
) == SUBREG
)
1052 sreg
= SUBREG_REG (src
);
1053 if (! (REG_P (dreg
) || MEM_P (dreg
)) || ! (REG_P (sreg
) || MEM_P (sreg
)))
1055 sclass
= dclass
= NO_REGS
;
1057 dclass
= get_reg_class (REGNO (dreg
));
1058 if (dclass
== ALL_REGS
)
1059 /* ALL_REGS is used for new pseudos created by transformations
1060 like reload of SUBREG_REG (see function
1061 simplify_operand_subreg). We don't know their class yet. We
1062 should figure out the class from processing the insn
1063 constraints not in this fast path function. Even if ALL_REGS
1064 were a right class for the pseudo, secondary_... hooks usually
1065 are not define for ALL_REGS. */
1067 sreg_mode
= GET_MODE (sreg
);
1070 sclass
= get_reg_class (REGNO (sreg
));
1071 if (sclass
== ALL_REGS
)
1072 /* See comments above. */
1074 if (sclass
== NO_REGS
&& dclass
== NO_REGS
)
1076 #ifdef SECONDARY_MEMORY_NEEDED
1077 if (SECONDARY_MEMORY_NEEDED (sclass
, dclass
, GET_MODE (src
))
1078 #ifdef SECONDARY_MEMORY_NEEDED_MODE
1079 && ((sclass
!= NO_REGS
&& dclass
!= NO_REGS
)
1080 || GET_MODE (src
) != SECONDARY_MEMORY_NEEDED_MODE (GET_MODE (src
)))
1088 if (! REG_P (dreg
) || ! REG_P (sreg
))
1090 sri
.prev_sri
= NULL
;
1091 sri
.icode
= CODE_FOR_nothing
;
1093 secondary_class
= NO_REGS
;
1094 /* Set up hard register for a reload pseudo for hook
1095 secondary_reload because some targets just ignore unassigned
1096 pseudos in the hook. */
1097 if (dclass
!= NO_REGS
&& lra_get_regno_hard_regno (REGNO (dreg
)) < 0)
1099 dregno
= REGNO (dreg
);
1100 reg_renumber
[dregno
] = ira_class_hard_regs
[dclass
][0];
1104 if (sclass
!= NO_REGS
&& lra_get_regno_hard_regno (REGNO (sreg
)) < 0)
1106 sregno
= REGNO (sreg
);
1107 reg_renumber
[sregno
] = ira_class_hard_regs
[sclass
][0];
1111 if (sclass
!= NO_REGS
)
1113 = (enum reg_class
) targetm
.secondary_reload (false, dest
,
1114 (reg_class_t
) sclass
,
1115 GET_MODE (src
), &sri
);
1116 if (sclass
== NO_REGS
1117 || ((secondary_class
!= NO_REGS
|| sri
.icode
!= CODE_FOR_nothing
)
1118 && dclass
!= NO_REGS
))
1120 enum reg_class old_sclass
= secondary_class
;
1121 secondary_reload_info old_sri
= sri
;
1123 sri
.prev_sri
= NULL
;
1124 sri
.icode
= CODE_FOR_nothing
;
1127 = (enum reg_class
) targetm
.secondary_reload (true, sreg
,
1128 (reg_class_t
) dclass
,
1130 /* Check the target hook consistency. */
1132 ((secondary_class
== NO_REGS
&& sri
.icode
== CODE_FOR_nothing
)
1133 || (old_sclass
== NO_REGS
&& old_sri
.icode
== CODE_FOR_nothing
)
1134 || (secondary_class
== old_sclass
&& sri
.icode
== old_sri
.icode
));
1137 reg_renumber
[sregno
] = -1;
1139 reg_renumber
[dregno
] = -1;
1140 if (secondary_class
== NO_REGS
&& sri
.icode
== CODE_FOR_nothing
)
1144 if (secondary_class
!= NO_REGS
)
1145 new_reg
= lra_create_new_reg_with_unique_value (sreg_mode
, NULL_RTX
,
1149 if (old_sreg
!= sreg
)
1150 sreg
= copy_rtx (sreg
);
1151 if (sri
.icode
== CODE_FOR_nothing
)
1152 lra_emit_move (new_reg
, sreg
);
1155 enum reg_class scratch_class
;
1157 scratch_class
= (reg_class_from_constraints
1158 (insn_data
[sri
.icode
].operand
[2].constraint
));
1159 scratch_reg
= (lra_create_new_reg_with_unique_value
1160 (insn_data
[sri
.icode
].operand
[2].mode
, NULL_RTX
,
1161 scratch_class
, "scratch"));
1162 emit_insn (GEN_FCN (sri
.icode
) (new_reg
!= NULL_RTX
? new_reg
: dest
,
1163 sreg
, scratch_reg
));
1165 before
= get_insns ();
1167 lra_process_new_insns (curr_insn
, before
, NULL_RTX
, "Inserting the move");
1168 if (new_reg
!= NULL_RTX
)
1170 if (GET_CODE (src
) == SUBREG
)
1171 SUBREG_REG (src
) = new_reg
;
1173 SET_SRC (curr_insn_set
) = new_reg
;
1177 if (lra_dump_file
!= NULL
)
1179 fprintf (lra_dump_file
, "Deleting move %u\n", INSN_UID (curr_insn
));
1180 dump_insn_slim (lra_dump_file
, curr_insn
);
1182 lra_set_insn_deleted (curr_insn
);
1188 /* The following data describe the result of process_alt_operands.
1189 The data are used in curr_insn_transform to generate reloads. */
1191 /* The chosen reg classes which should be used for the corresponding
1193 static enum reg_class goal_alt
[MAX_RECOG_OPERANDS
];
1194 /* True if the operand should be the same as another operand and that
1195 other operand does not need a reload. */
1196 static bool goal_alt_match_win
[MAX_RECOG_OPERANDS
];
1197 /* True if the operand does not need a reload. */
1198 static bool goal_alt_win
[MAX_RECOG_OPERANDS
];
1199 /* True if the operand can be offsetable memory. */
1200 static bool goal_alt_offmemok
[MAX_RECOG_OPERANDS
];
1201 /* The number of an operand to which given operand can be matched to. */
1202 static int goal_alt_matches
[MAX_RECOG_OPERANDS
];
1203 /* The number of elements in the following array. */
1204 static int goal_alt_dont_inherit_ops_num
;
1205 /* Numbers of operands whose reload pseudos should not be inherited. */
1206 static int goal_alt_dont_inherit_ops
[MAX_RECOG_OPERANDS
];
1207 /* True if the insn commutative operands should be swapped. */
1208 static bool goal_alt_swapped
;
1209 /* The chosen insn alternative. */
1210 static int goal_alt_number
;
1212 /* The following five variables are used to choose the best insn
1213 alternative. They reflect final characteristics of the best
1216 /* Number of necessary reloads and overall cost reflecting the
1217 previous value and other unpleasantness of the best alternative. */
1218 static int best_losers
, best_overall
;
1219 /* Overall number hard registers used for reloads. For example, on
1220 some targets we need 2 general registers to reload DFmode and only
1221 one floating point register. */
1222 static int best_reload_nregs
;
1223 /* Overall number reflecting distances of previous reloading the same
1224 value. The distances are counted from the current BB start. It is
1225 used to improve inheritance chances. */
1226 static int best_reload_sum
;
1228 /* True if the current insn should have no correspondingly input or
1230 static bool no_input_reloads_p
, no_output_reloads_p
;
1232 /* True if we swapped the commutative operands in the current
1234 static int curr_swapped
;
1236 /* Arrange for address element *LOC to be a register of class CL.
1237 Add any input reloads to list BEFORE. AFTER is nonnull if *LOC is an
1238 automodified value; handle that case by adding the required output
1239 reloads to list AFTER. Return true if the RTL was changed. */
1241 process_addr_reg (rtx
*loc
, rtx
*before
, rtx
*after
, enum reg_class cl
)
1244 enum reg_class rclass
, new_class
;
1247 enum machine_mode mode
;
1248 bool subreg_p
, before_p
= false;
1250 subreg_p
= GET_CODE (*loc
) == SUBREG
;
1252 loc
= &SUBREG_REG (*loc
);
1254 mode
= GET_MODE (reg
);
1257 /* Always reload memory in an address even if the target supports
1259 new_reg
= lra_create_new_reg_with_unique_value (mode
, reg
, cl
, "address");
1264 regno
= REGNO (reg
);
1265 rclass
= get_reg_class (regno
);
1266 if ((*loc
= get_equiv_with_elimination (reg
, curr_insn
)) != reg
)
1268 if (lra_dump_file
!= NULL
)
1270 fprintf (lra_dump_file
,
1271 "Changing pseudo %d in address of insn %u on equiv ",
1272 REGNO (reg
), INSN_UID (curr_insn
));
1273 dump_value_slim (lra_dump_file
, *loc
, 1);
1274 fprintf (lra_dump_file
, "\n");
1276 *loc
= copy_rtx (*loc
);
1278 if (*loc
!= reg
|| ! in_class_p (reg
, cl
, &new_class
))
1281 if (get_reload_reg (after
== NULL
? OP_IN
: OP_INOUT
,
1282 mode
, reg
, cl
, subreg_p
, "address", &new_reg
))
1285 else if (new_class
!= NO_REGS
&& rclass
!= new_class
)
1287 lra_change_class (regno
, new_class
, " Change to", true);
1295 push_to_sequence (*before
);
1296 lra_emit_move (new_reg
, reg
);
1297 *before
= get_insns ();
1304 lra_emit_move (reg
, new_reg
);
1306 *after
= get_insns ();
1312 /* Insert move insn in simplify_operand_subreg. BEFORE returns
1313 the insn to be inserted before curr insn. AFTER returns the
1314 the insn to be inserted after curr insn. ORIGREG and NEWREG
1315 are the original reg and new reg for reload. */
1317 insert_move_for_subreg (rtx
*before
, rtx
*after
, rtx origreg
, rtx newreg
)
1321 push_to_sequence (*before
);
1322 lra_emit_move (newreg
, origreg
);
1323 *before
= get_insns ();
1329 lra_emit_move (origreg
, newreg
);
1331 *after
= get_insns ();
1336 static int valid_address_p (enum machine_mode mode
, rtx addr
, addr_space_t as
);
1338 /* Make reloads for subreg in operand NOP with internal subreg mode
1339 REG_MODE, add new reloads for further processing. Return true if
1340 any reload was generated. */
1342 simplify_operand_subreg (int nop
, enum machine_mode reg_mode
)
1346 enum machine_mode mode
;
1348 rtx operand
= *curr_id
->operand_loc
[nop
];
1349 enum reg_class regclass
;
1352 before
= after
= NULL_RTX
;
1354 if (GET_CODE (operand
) != SUBREG
)
1357 mode
= GET_MODE (operand
);
1358 reg
= SUBREG_REG (operand
);
1359 type
= curr_static_id
->operand
[nop
].type
;
1360 /* If we change address for paradoxical subreg of memory, the
1361 address might violate the necessary alignment or the access might
1362 be slow. So take this into consideration. We should not worry
1363 about access beyond allocated memory for paradoxical memory
1364 subregs as we don't substitute such equiv memory (see processing
1365 equivalences in function lra_constraints) and because for spilled
1366 pseudos we allocate stack memory enough for the biggest
1367 corresponding paradoxical subreg. */
1369 && (! SLOW_UNALIGNED_ACCESS (mode
, MEM_ALIGN (reg
))
1370 || MEM_ALIGN (reg
) >= GET_MODE_ALIGNMENT (mode
)))
1372 rtx subst
, old
= *curr_id
->operand_loc
[nop
];
1374 alter_subreg (curr_id
->operand_loc
[nop
], false);
1375 subst
= *curr_id
->operand_loc
[nop
];
1376 lra_assert (MEM_P (subst
));
1377 if (! valid_address_p (GET_MODE (reg
), XEXP (reg
, 0),
1378 MEM_ADDR_SPACE (reg
))
1379 || valid_address_p (GET_MODE (subst
), XEXP (subst
, 0),
1380 MEM_ADDR_SPACE (subst
)))
1382 /* If the address was valid and became invalid, prefer to reload
1383 the memory. Typical case is when the index scale should
1384 correspond the memory. */
1385 *curr_id
->operand_loc
[nop
] = old
;
1387 else if (REG_P (reg
) && REGNO (reg
) < FIRST_PSEUDO_REGISTER
)
1389 alter_subreg (curr_id
->operand_loc
[nop
], false);
1392 /* Put constant into memory when we have mixed modes. It generates
1393 a better code in most cases as it does not need a secondary
1394 reload memory. It also prevents LRA looping when LRA is using
1395 secondary reload memory again and again. */
1396 if (CONSTANT_P (reg
) && CONST_POOL_OK_P (reg_mode
, reg
)
1397 && SCALAR_INT_MODE_P (reg_mode
) != SCALAR_INT_MODE_P (mode
))
1399 SUBREG_REG (operand
) = force_const_mem (reg_mode
, reg
);
1400 alter_subreg (curr_id
->operand_loc
[nop
], false);
1403 /* Force a reload of the SUBREG_REG if this is a constant or PLUS or
1404 if there may be a problem accessing OPERAND in the outer
1407 && REGNO (reg
) >= FIRST_PSEUDO_REGISTER
1408 && (hard_regno
= lra_get_regno_hard_regno (REGNO (reg
))) >= 0
1409 /* Don't reload paradoxical subregs because we could be looping
1410 having repeatedly final regno out of hard regs range. */
1411 && (hard_regno_nregs
[hard_regno
][GET_MODE (reg
)]
1412 >= hard_regno_nregs
[hard_regno
][mode
])
1413 && simplify_subreg_regno (hard_regno
, GET_MODE (reg
),
1414 SUBREG_BYTE (operand
), mode
) < 0
1415 /* Don't reload subreg for matching reload. It is actually
1416 valid subreg in LRA. */
1417 && ! LRA_SUBREG_P (operand
))
1418 || CONSTANT_P (reg
) || GET_CODE (reg
) == PLUS
|| MEM_P (reg
))
1420 enum reg_class rclass
;
1423 /* There is a big probability that we will get the same class
1424 for the new pseudo and we will get the same insn which
1425 means infinite looping. So spill the new pseudo. */
1428 /* The class will be defined later in curr_insn_transform. */
1430 = (enum reg_class
) targetm
.preferred_reload_class (reg
, ALL_REGS
);
1432 if (get_reload_reg (curr_static_id
->operand
[nop
].type
, reg_mode
, reg
,
1433 rclass
, TRUE
, "subreg reg", &new_reg
))
1435 bool insert_before
, insert_after
;
1436 bitmap_set_bit (&lra_subreg_reload_pseudos
, REGNO (new_reg
));
1438 insert_before
= (type
!= OP_OUT
1439 || GET_MODE_SIZE (GET_MODE (reg
)) > GET_MODE_SIZE (mode
));
1440 insert_after
= (type
!= OP_IN
);
1441 insert_move_for_subreg (insert_before
? &before
: NULL
,
1442 insert_after
? &after
: NULL
,
1445 SUBREG_REG (operand
) = new_reg
;
1446 lra_process_new_insns (curr_insn
, before
, after
,
1447 "Inserting subreg reload");
1450 /* Force a reload for a paradoxical subreg. For paradoxical subreg,
1451 IRA allocates hardreg to the inner pseudo reg according to its mode
1452 instead of the outermode, so the size of the hardreg may not be enough
1453 to contain the outermode operand, in that case we may need to insert
1454 reload for the reg. For the following two types of paradoxical subreg,
1455 we need to insert reload:
1456 1. If the op_type is OP_IN, and the hardreg could not be paired with
1457 other hardreg to contain the outermode operand
1458 (checked by in_hard_reg_set_p), we need to insert the reload.
1459 2. If the op_type is OP_OUT or OP_INOUT.
1461 Here is a paradoxical subreg example showing how the reload is generated:
1463 (insn 5 4 7 2 (set (reg:TI 106 [ __comp ])
1464 (subreg:TI (reg:DI 107 [ __comp ]) 0)) {*movti_internal_rex64}
1466 In IRA, reg107 is allocated to a DImode hardreg. We use x86-64 as example
1467 here, if reg107 is assigned to hardreg R15, because R15 is the last
1468 hardreg, compiler cannot find another hardreg to pair with R15 to
1469 contain TImode data. So we insert a TImode reload reg180 for it.
1470 After reload is inserted:
1472 (insn 283 0 0 (set (subreg:DI (reg:TI 180 [orig:107 __comp ] [107]) 0)
1473 (reg:DI 107 [ __comp ])) -1
1474 (insn 5 4 7 2 (set (reg:TI 106 [ __comp ])
1475 (subreg:TI (reg:TI 180 [orig:107 __comp ] [107]) 0)) {*movti_internal_rex64}
1477 Two reload hard registers will be allocated to reg180 to save TImode data
1479 else if (REG_P (reg
)
1480 && REGNO (reg
) >= FIRST_PSEUDO_REGISTER
1481 && (hard_regno
= lra_get_regno_hard_regno (REGNO (reg
))) >= 0
1482 && (hard_regno_nregs
[hard_regno
][GET_MODE (reg
)]
1483 < hard_regno_nregs
[hard_regno
][mode
])
1484 && (regclass
= lra_get_allocno_class (REGNO (reg
)))
1486 || !in_hard_reg_set_p (reg_class_contents
[regclass
],
1489 /* The class will be defined later in curr_insn_transform. */
1490 enum reg_class rclass
1491 = (enum reg_class
) targetm
.preferred_reload_class (reg
, ALL_REGS
);
1493 if (get_reload_reg (curr_static_id
->operand
[nop
].type
, mode
, reg
,
1494 rclass
, TRUE
, "paradoxical subreg", &new_reg
))
1497 bool insert_before
, insert_after
;
1499 PUT_MODE (new_reg
, mode
);
1500 subreg
= simplify_gen_subreg (GET_MODE (reg
), new_reg
, mode
, 0);
1501 bitmap_set_bit (&lra_subreg_reload_pseudos
, REGNO (new_reg
));
1503 insert_before
= (type
!= OP_OUT
);
1504 insert_after
= (type
!= OP_IN
);
1505 insert_move_for_subreg (insert_before
? &before
: NULL
,
1506 insert_after
? &after
: NULL
,
1509 SUBREG_REG (operand
) = new_reg
;
1510 lra_process_new_insns (curr_insn
, before
, after
,
1511 "Inserting paradoxical subreg reload");
1517 /* Return TRUE if X refers for a hard register from SET. */
1519 uses_hard_regs_p (rtx x
, HARD_REG_SET set
)
1521 int i
, j
, x_hard_regno
;
1522 enum machine_mode mode
;
1528 code
= GET_CODE (x
);
1529 mode
= GET_MODE (x
);
1533 code
= GET_CODE (x
);
1534 if (GET_MODE_SIZE (GET_MODE (x
)) > GET_MODE_SIZE (mode
))
1535 mode
= GET_MODE (x
);
1540 x_hard_regno
= get_hard_regno (x
);
1541 return (x_hard_regno
>= 0
1542 && overlaps_hard_reg_set_p (set
, mode
, x_hard_regno
));
1546 struct address_info ad
;
1548 decompose_mem_address (&ad
, x
);
1549 if (ad
.base_term
!= NULL
&& uses_hard_regs_p (*ad
.base_term
, set
))
1551 if (ad
.index_term
!= NULL
&& uses_hard_regs_p (*ad
.index_term
, set
))
1554 fmt
= GET_RTX_FORMAT (code
);
1555 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
1559 if (uses_hard_regs_p (XEXP (x
, i
), set
))
1562 else if (fmt
[i
] == 'E')
1564 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
1565 if (uses_hard_regs_p (XVECEXP (x
, i
, j
), set
))
1572 /* Return true if OP is a spilled pseudo. */
1574 spilled_pseudo_p (rtx op
)
1577 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
&& in_mem_p (REGNO (op
)));
1580 /* Return true if X is a general constant. */
1582 general_constant_p (rtx x
)
1584 return CONSTANT_P (x
) && (! flag_pic
|| LEGITIMATE_PIC_OPERAND_P (x
));
1588 reg_in_class_p (rtx reg
, enum reg_class cl
)
1591 return get_reg_class (REGNO (reg
)) == NO_REGS
;
1592 return in_class_p (reg
, cl
, NULL
);
1595 /* Major function to choose the current insn alternative and what
1596 operands should be reloaded and how. If ONLY_ALTERNATIVE is not
1597 negative we should consider only this alternative. Return false if
1598 we can not choose the alternative or find how to reload the
1601 process_alt_operands (int only_alternative
)
1604 int nop
, overall
, nalt
;
1605 int n_alternatives
= curr_static_id
->n_alternatives
;
1606 int n_operands
= curr_static_id
->n_operands
;
1607 /* LOSERS counts the operands that don't fit this alternative and
1608 would require loading. */
1610 /* REJECT is a count of how undesirable this alternative says it is
1611 if any reloading is required. If the alternative matches exactly
1612 then REJECT is ignored, but otherwise it gets this much counted
1613 against it in addition to the reloading needed. */
1615 /* The number of elements in the following array. */
1616 int early_clobbered_regs_num
;
1617 /* Numbers of operands which are early clobber registers. */
1618 int early_clobbered_nops
[MAX_RECOG_OPERANDS
];
1619 enum reg_class curr_alt
[MAX_RECOG_OPERANDS
];
1620 HARD_REG_SET curr_alt_set
[MAX_RECOG_OPERANDS
];
1621 bool curr_alt_match_win
[MAX_RECOG_OPERANDS
];
1622 bool curr_alt_win
[MAX_RECOG_OPERANDS
];
1623 bool curr_alt_offmemok
[MAX_RECOG_OPERANDS
];
1624 int curr_alt_matches
[MAX_RECOG_OPERANDS
];
1625 /* The number of elements in the following array. */
1626 int curr_alt_dont_inherit_ops_num
;
1627 /* Numbers of operands whose reload pseudos should not be inherited. */
1628 int curr_alt_dont_inherit_ops
[MAX_RECOG_OPERANDS
];
1630 /* The register when the operand is a subreg of register, otherwise the
1632 rtx no_subreg_reg_operand
[MAX_RECOG_OPERANDS
];
1633 /* The register if the operand is a register or subreg of register,
1635 rtx operand_reg
[MAX_RECOG_OPERANDS
];
1636 int hard_regno
[MAX_RECOG_OPERANDS
];
1637 enum machine_mode biggest_mode
[MAX_RECOG_OPERANDS
];
1638 int reload_nregs
, reload_sum
;
1642 /* Calculate some data common for all alternatives to speed up the
1644 for (nop
= 0; nop
< n_operands
; nop
++)
1648 op
= no_subreg_reg_operand
[nop
] = *curr_id
->operand_loc
[nop
];
1649 /* The real hard regno of the operand after the allocation. */
1650 hard_regno
[nop
] = get_hard_regno (op
);
1652 operand_reg
[nop
] = reg
= op
;
1653 biggest_mode
[nop
] = GET_MODE (op
);
1654 if (GET_CODE (op
) == SUBREG
)
1656 operand_reg
[nop
] = reg
= SUBREG_REG (op
);
1657 if (GET_MODE_SIZE (biggest_mode
[nop
])
1658 < GET_MODE_SIZE (GET_MODE (reg
)))
1659 biggest_mode
[nop
] = GET_MODE (reg
);
1662 operand_reg
[nop
] = NULL_RTX
;
1663 else if (REGNO (reg
) >= FIRST_PSEUDO_REGISTER
1664 || ((int) REGNO (reg
)
1665 == lra_get_elimination_hard_regno (REGNO (reg
))))
1666 no_subreg_reg_operand
[nop
] = reg
;
1668 operand_reg
[nop
] = no_subreg_reg_operand
[nop
]
1669 /* Just use natural mode for elimination result. It should
1670 be enough for extra constraints hooks. */
1671 = regno_reg_rtx
[hard_regno
[nop
]];
1674 /* The constraints are made of several alternatives. Each operand's
1675 constraint looks like foo,bar,... with commas separating the
1676 alternatives. The first alternatives for all operands go
1677 together, the second alternatives go together, etc.
1679 First loop over alternatives. */
1680 alternative_mask enabled
= curr_id
->enabled_alternatives
;
1681 if (only_alternative
>= 0)
1682 enabled
&= ALTERNATIVE_BIT (only_alternative
);
1684 for (nalt
= 0; nalt
< n_alternatives
; nalt
++)
1686 /* Loop over operands for one constraint alternative. */
1687 if (!TEST_BIT (enabled
, nalt
))
1690 overall
= losers
= reject
= reload_nregs
= reload_sum
= 0;
1691 for (nop
= 0; nop
< n_operands
; nop
++)
1693 int inc
= (curr_static_id
1694 ->operand_alternative
[nalt
* n_operands
+ nop
].reject
);
1695 if (lra_dump_file
!= NULL
&& inc
!= 0)
1696 fprintf (lra_dump_file
,
1697 " Staticly defined alt reject+=%d\n", inc
);
1700 early_clobbered_regs_num
= 0;
1702 for (nop
= 0; nop
< n_operands
; nop
++)
1706 int len
, c
, m
, i
, opalt_num
, this_alternative_matches
;
1707 bool win
, did_match
, offmemok
, early_clobber_p
;
1708 /* false => this operand can be reloaded somehow for this
1711 /* true => this operand can be reloaded if the alternative
1714 /* True if a constant forced into memory would be OK for
1717 enum reg_class this_alternative
, this_costly_alternative
;
1718 HARD_REG_SET this_alternative_set
, this_costly_alternative_set
;
1719 bool this_alternative_match_win
, this_alternative_win
;
1720 bool this_alternative_offmemok
;
1722 enum machine_mode mode
;
1723 enum constraint_num cn
;
1725 opalt_num
= nalt
* n_operands
+ nop
;
1726 if (curr_static_id
->operand_alternative
[opalt_num
].anything_ok
)
1728 /* Fast track for no constraints at all. */
1729 curr_alt
[nop
] = NO_REGS
;
1730 CLEAR_HARD_REG_SET (curr_alt_set
[nop
]);
1731 curr_alt_win
[nop
] = true;
1732 curr_alt_match_win
[nop
] = false;
1733 curr_alt_offmemok
[nop
] = false;
1734 curr_alt_matches
[nop
] = -1;
1738 op
= no_subreg_reg_operand
[nop
];
1739 mode
= curr_operand_mode
[nop
];
1741 win
= did_match
= winreg
= offmemok
= constmemok
= false;
1744 early_clobber_p
= false;
1745 p
= curr_static_id
->operand_alternative
[opalt_num
].constraint
;
1747 this_costly_alternative
= this_alternative
= NO_REGS
;
1748 /* We update set of possible hard regs besides its class
1749 because reg class might be inaccurate. For example,
1750 union of LO_REGS (l), HI_REGS(h), and STACK_REG(k) in ARM
1751 is translated in HI_REGS because classes are merged by
1752 pairs and there is no accurate intermediate class. */
1753 CLEAR_HARD_REG_SET (this_alternative_set
);
1754 CLEAR_HARD_REG_SET (this_costly_alternative_set
);
1755 this_alternative_win
= false;
1756 this_alternative_match_win
= false;
1757 this_alternative_offmemok
= false;
1758 this_alternative_matches
= -1;
1760 /* An empty constraint should be excluded by the fast
1762 lra_assert (*p
!= 0 && *p
!= ',');
1764 /* Scan this alternative's specs for this operand; set WIN
1765 if the operand fits any letter in this alternative.
1766 Otherwise, clear BADOP if this operand could fit some
1767 letter after reloads, or set WINREG if this operand could
1768 fit after reloads provided the constraint allows some
1773 switch ((c
= *p
, len
= CONSTRAINT_LEN (c
, p
)), c
)
1783 early_clobber_p
= true;
1787 /* Ignore rest of this alternative. */
1791 case '0': case '1': case '2': case '3': case '4':
1792 case '5': case '6': case '7': case '8': case '9':
1797 m
= strtoul (p
, &end
, 10);
1800 lra_assert (nop
> m
);
1802 this_alternative_matches
= m
;
1803 m_hregno
= get_hard_regno (*curr_id
->operand_loc
[m
]);
1804 /* We are supposed to match a previous operand.
1805 If we do, we win if that one did. If we do
1806 not, count both of the operands as losers.
1807 (This is too conservative, since most of the
1808 time only a single reload insn will be needed
1809 to make the two operands win. As a result,
1810 this alternative may be rejected when it is
1811 actually desirable.) */
1813 if (operands_match_p (*curr_id
->operand_loc
[nop
],
1814 *curr_id
->operand_loc
[m
], m_hregno
))
1816 /* We should reject matching of an early
1817 clobber operand if the matching operand is
1818 not dying in the insn. */
1819 if (! curr_static_id
->operand
[m
].early_clobber
1820 || operand_reg
[nop
] == NULL_RTX
1821 || (find_regno_note (curr_insn
, REG_DEAD
,
1823 || REGNO (op
) == REGNO (operand_reg
[m
])))
1828 /* If we are matching a non-offsettable
1829 address where an offsettable address was
1830 expected, then we must reject this
1831 combination, because we can't reload
1833 if (curr_alt_offmemok
[m
]
1834 && MEM_P (*curr_id
->operand_loc
[m
])
1835 && curr_alt
[m
] == NO_REGS
&& ! curr_alt_win
[m
])
1840 /* Operands don't match. Both operands must
1841 allow a reload register, otherwise we
1842 cannot make them match. */
1843 if (curr_alt
[m
] == NO_REGS
)
1845 /* Retroactively mark the operand we had to
1846 match as a loser, if it wasn't already and
1847 it wasn't matched to a register constraint
1848 (e.g it might be matched by memory). */
1850 && (operand_reg
[m
] == NULL_RTX
1851 || hard_regno
[m
] < 0))
1855 += (ira_reg_class_max_nregs
[curr_alt
[m
]]
1856 [GET_MODE (*curr_id
->operand_loc
[m
])]);
1859 /* Prefer matching earlyclobber alternative as
1860 it results in less hard regs required for
1861 the insn than a non-matching earlyclobber
1863 if (curr_static_id
->operand
[m
].early_clobber
)
1865 if (lra_dump_file
!= NULL
)
1868 " %d Matching earlyclobber alt:"
1873 /* Otherwise we prefer no matching
1874 alternatives because it gives more freedom
1876 else if (operand_reg
[nop
] == NULL_RTX
1877 || (find_regno_note (curr_insn
, REG_DEAD
,
1878 REGNO (operand_reg
[nop
]))
1881 if (lra_dump_file
!= NULL
)
1884 " %d Matching alt: reject+=2\n",
1889 /* If we have to reload this operand and some
1890 previous operand also had to match the same
1891 thing as this operand, we don't know how to do
1893 if (!match_p
|| !curr_alt_win
[m
])
1895 for (i
= 0; i
< nop
; i
++)
1896 if (curr_alt_matches
[i
] == m
)
1904 /* This can be fixed with reloads if the operand
1905 we are supposed to match can be fixed with
1908 this_alternative
= curr_alt
[m
];
1909 COPY_HARD_REG_SET (this_alternative_set
, curr_alt_set
[m
]);
1910 winreg
= this_alternative
!= NO_REGS
;
1916 || general_constant_p (op
)
1917 || spilled_pseudo_p (op
))
1923 cn
= lookup_constraint (p
);
1924 switch (get_constraint_type (cn
))
1927 cl
= reg_class_for_constraint (cn
);
1933 if (CONST_INT_P (op
)
1934 && insn_const_int_ok_for_constraint (INTVAL (op
), cn
))
1940 && satisfies_memory_constraint_p (op
, cn
))
1942 else if (spilled_pseudo_p (op
))
1945 /* If we didn't already win, we can reload constants
1946 via force_const_mem or put the pseudo value into
1947 memory, or make other memory by reloading the
1948 address like for 'o'. */
1949 if (CONST_POOL_OK_P (mode
, op
)
1950 || MEM_P (op
) || REG_P (op
))
1957 /* If we didn't already win, we can reload the address
1958 into a base register. */
1959 if (satisfies_address_constraint_p (op
, cn
))
1961 cl
= base_reg_class (VOIDmode
, ADDR_SPACE_GENERIC
,
1967 if (constraint_satisfied_p (op
, cn
))
1974 this_alternative
= reg_class_subunion
[this_alternative
][cl
];
1975 IOR_HARD_REG_SET (this_alternative_set
,
1976 reg_class_contents
[cl
]);
1979 this_costly_alternative
1980 = reg_class_subunion
[this_costly_alternative
][cl
];
1981 IOR_HARD_REG_SET (this_costly_alternative_set
,
1982 reg_class_contents
[cl
]);
1984 if (mode
== BLKmode
)
1989 if (hard_regno
[nop
] >= 0
1990 && in_hard_reg_set_p (this_alternative_set
,
1991 mode
, hard_regno
[nop
]))
1993 else if (hard_regno
[nop
] < 0
1994 && in_class_p (op
, this_alternative
, NULL
))
1999 if (c
!= ' ' && c
!= '\t')
2000 costly_p
= c
== '*';
2002 while ((p
+= len
), c
);
2004 scratch_p
= (operand_reg
[nop
] != NULL_RTX
2005 && lra_former_scratch_p (REGNO (operand_reg
[nop
])));
2006 /* Record which operands fit this alternative. */
2009 this_alternative_win
= true;
2010 if (operand_reg
[nop
] != NULL_RTX
)
2012 if (hard_regno
[nop
] >= 0)
2014 if (in_hard_reg_set_p (this_costly_alternative_set
,
2015 mode
, hard_regno
[nop
]))
2017 if (lra_dump_file
!= NULL
)
2018 fprintf (lra_dump_file
,
2019 " %d Costly set: reject++\n",
2026 /* Prefer won reg to spilled pseudo under other
2027 equal conditions for possibe inheritance. */
2030 if (lra_dump_file
!= NULL
)
2033 " %d Non pseudo reload: reject++\n",
2037 if (in_class_p (operand_reg
[nop
],
2038 this_costly_alternative
, NULL
))
2040 if (lra_dump_file
!= NULL
)
2043 " %d Non pseudo costly reload:"
2049 /* We simulate the behaviour of old reload here.
2050 Although scratches need hard registers and it
2051 might result in spilling other pseudos, no reload
2052 insns are generated for the scratches. So it
2053 might cost something but probably less than old
2054 reload pass believes. */
2057 if (lra_dump_file
!= NULL
)
2058 fprintf (lra_dump_file
,
2059 " %d Scratch win: reject+=2\n",
2066 this_alternative_match_win
= true;
2069 int const_to_mem
= 0;
2072 /* Never do output reload of stack pointer. It makes
2073 impossible to do elimination when SP is changed in
2075 if (op
== stack_pointer_rtx
&& ! frame_pointer_needed
2076 && curr_static_id
->operand
[nop
].type
!= OP_IN
)
2079 /* If this alternative asks for a specific reg class, see if there
2080 is at least one allocatable register in that class. */
2082 = (this_alternative
== NO_REGS
2083 || (hard_reg_set_subset_p
2084 (reg_class_contents
[this_alternative
],
2085 lra_no_alloc_regs
)));
2087 /* For asms, verify that the class for this alternative is possible
2088 for the mode that is specified. */
2089 if (!no_regs_p
&& INSN_CODE (curr_insn
) < 0)
2092 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
2093 if (HARD_REGNO_MODE_OK (i
, mode
)
2094 && in_hard_reg_set_p (reg_class_contents
[this_alternative
],
2097 if (i
== FIRST_PSEUDO_REGISTER
)
2101 /* If this operand accepts a register, and if the
2102 register class has at least one allocatable register,
2103 then this operand can be reloaded. */
2104 if (winreg
&& !no_regs_p
)
2109 if (lra_dump_file
!= NULL
)
2110 fprintf (lra_dump_file
,
2111 " alt=%d: Bad operand -- refuse\n",
2116 /* If not assigned pseudo has a class which a subset of
2117 required reg class, it is a less costly alternative
2118 as the pseudo still can get a hard reg of necessary
2120 if (! no_regs_p
&& REG_P (op
) && hard_regno
[nop
] < 0
2121 && (cl
= get_reg_class (REGNO (op
))) != NO_REGS
2122 && ira_class_subset_p
[this_alternative
][cl
])
2124 if (lra_dump_file
!= NULL
)
2127 " %d Super set class reg: reject-=3\n", nop
);
2131 this_alternative_offmemok
= offmemok
;
2132 if (this_costly_alternative
!= NO_REGS
)
2134 if (lra_dump_file
!= NULL
)
2135 fprintf (lra_dump_file
,
2136 " %d Costly loser: reject++\n", nop
);
2139 /* If the operand is dying, has a matching constraint,
2140 and satisfies constraints of the matched operand
2141 which failed to satisfy the own constraints, most probably
2142 the reload for this operand will be gone. */
2143 if (this_alternative_matches
>= 0
2144 && !curr_alt_win
[this_alternative_matches
]
2146 && find_regno_note (curr_insn
, REG_DEAD
, REGNO (op
))
2147 && (hard_regno
[nop
] >= 0
2148 ? in_hard_reg_set_p (this_alternative_set
,
2149 mode
, hard_regno
[nop
])
2150 : in_class_p (op
, this_alternative
, NULL
)))
2152 if (lra_dump_file
!= NULL
)
2155 " %d Dying matched operand reload: reject++\n",
2161 /* Strict_low_part requires to reload the register
2162 not the sub-register. In this case we should
2163 check that a final reload hard reg can hold the
2165 if (curr_static_id
->operand
[nop
].strict_low
2167 && hard_regno
[nop
] < 0
2168 && GET_CODE (*curr_id
->operand_loc
[nop
]) == SUBREG
2169 && ira_class_hard_regs_num
[this_alternative
] > 0
2170 && ! HARD_REGNO_MODE_OK (ira_class_hard_regs
2171 [this_alternative
][0],
2173 (*curr_id
->operand_loc
[nop
])))
2175 if (lra_dump_file
!= NULL
)
2178 " alt=%d: Strict low subreg reload -- refuse\n",
2184 if (operand_reg
[nop
] != NULL_RTX
2185 /* Output operands and matched input operands are
2186 not inherited. The following conditions do not
2187 exactly describe the previous statement but they
2188 are pretty close. */
2189 && curr_static_id
->operand
[nop
].type
!= OP_OUT
2190 && (this_alternative_matches
< 0
2191 || curr_static_id
->operand
[nop
].type
!= OP_IN
))
2193 int last_reload
= (lra_reg_info
[ORIGINAL_REGNO
2197 /* The value of reload_sum has sense only if we
2198 process insns in their order. It happens only on
2199 the first constraints sub-pass when we do most of
2201 if (lra_constraint_iter
== 1 && last_reload
> bb_reload_num
)
2202 reload_sum
+= last_reload
- bb_reload_num
;
2204 /* If this is a constant that is reloaded into the
2205 desired class by copying it to memory first, count
2206 that as another reload. This is consistent with
2207 other code and is required to avoid choosing another
2208 alternative when the constant is moved into memory.
2209 Note that the test here is precisely the same as in
2210 the code below that calls force_const_mem. */
2211 if (CONST_POOL_OK_P (mode
, op
)
2212 && ((targetm
.preferred_reload_class
2213 (op
, this_alternative
) == NO_REGS
)
2214 || no_input_reloads_p
))
2221 /* Alternative loses if it requires a type of reload not
2222 permitted for this insn. We can always reload
2223 objects with a REG_UNUSED note. */
2224 if ((curr_static_id
->operand
[nop
].type
!= OP_IN
2225 && no_output_reloads_p
2226 && ! find_reg_note (curr_insn
, REG_UNUSED
, op
))
2227 || (curr_static_id
->operand
[nop
].type
!= OP_OUT
2228 && no_input_reloads_p
&& ! const_to_mem
)
2229 || (this_alternative_matches
>= 0
2230 && (no_input_reloads_p
2231 || (no_output_reloads_p
2232 && (curr_static_id
->operand
2233 [this_alternative_matches
].type
!= OP_IN
)
2234 && ! find_reg_note (curr_insn
, REG_UNUSED
,
2235 no_subreg_reg_operand
2236 [this_alternative_matches
])))))
2238 if (lra_dump_file
!= NULL
)
2241 " alt=%d: No input/otput reload -- refuse\n",
2246 /* Check strong discouragement of reload of non-constant
2247 into class THIS_ALTERNATIVE. */
2248 if (! CONSTANT_P (op
) && ! no_regs_p
2249 && (targetm
.preferred_reload_class
2250 (op
, this_alternative
) == NO_REGS
2251 || (curr_static_id
->operand
[nop
].type
== OP_OUT
2252 && (targetm
.preferred_output_reload_class
2253 (op
, this_alternative
) == NO_REGS
))))
2255 if (lra_dump_file
!= NULL
)
2256 fprintf (lra_dump_file
,
2257 " %d Non-prefered reload: reject+=%d\n",
2258 nop
, LRA_MAX_REJECT
);
2259 reject
+= LRA_MAX_REJECT
;
2262 if (! (MEM_P (op
) && offmemok
)
2263 && ! (const_to_mem
&& constmemok
))
2265 /* We prefer to reload pseudos over reloading other
2266 things, since such reloads may be able to be
2267 eliminated later. So bump REJECT in other cases.
2268 Don't do this in the case where we are forcing a
2269 constant into memory and it will then win since
2270 we don't want to have a different alternative
2272 if (! (REG_P (op
) && REGNO (op
) >= FIRST_PSEUDO_REGISTER
))
2274 if (lra_dump_file
!= NULL
)
2277 " %d Non-pseudo reload: reject+=2\n",
2284 += ira_reg_class_max_nregs
[this_alternative
][mode
];
2286 if (SMALL_REGISTER_CLASS_P (this_alternative
))
2288 if (lra_dump_file
!= NULL
)
2291 " %d Small class reload: reject+=%d\n",
2292 nop
, LRA_LOSER_COST_FACTOR
/ 2);
2293 reject
+= LRA_LOSER_COST_FACTOR
/ 2;
2297 /* We are trying to spill pseudo into memory. It is
2298 usually more costly than moving to a hard register
2299 although it might takes the same number of
2301 if (no_regs_p
&& REG_P (op
) && hard_regno
[nop
] >= 0)
2303 if (lra_dump_file
!= NULL
)
2306 " %d Spill pseudo into memory: reject+=3\n",
2309 if (VECTOR_MODE_P (mode
))
2311 /* Spilling vectors into memory is usually more
2312 costly as they contain big values. */
2313 if (lra_dump_file
!= NULL
)
2316 " %d Spill vector pseudo: reject+=2\n",
2322 #ifdef SECONDARY_MEMORY_NEEDED
2323 /* If reload requires moving value through secondary
2324 memory, it will need one more insn at least. */
2325 if (this_alternative
!= NO_REGS
2326 && REG_P (op
) && (cl
= get_reg_class (REGNO (op
))) != NO_REGS
2327 && ((curr_static_id
->operand
[nop
].type
!= OP_OUT
2328 && SECONDARY_MEMORY_NEEDED (cl
, this_alternative
,
2330 || (curr_static_id
->operand
[nop
].type
!= OP_IN
2331 && SECONDARY_MEMORY_NEEDED (this_alternative
, cl
,
2335 /* Input reloads can be inherited more often than output
2336 reloads can be removed, so penalize output
2338 if (!REG_P (op
) || curr_static_id
->operand
[nop
].type
!= OP_IN
)
2340 if (lra_dump_file
!= NULL
)
2343 " %d Non input pseudo reload: reject++\n",
2349 if (early_clobber_p
&& ! scratch_p
)
2351 if (lra_dump_file
!= NULL
)
2352 fprintf (lra_dump_file
,
2353 " %d Early clobber: reject++\n", nop
);
2356 /* ??? We check early clobbers after processing all operands
2357 (see loop below) and there we update the costs more.
2358 Should we update the cost (may be approximately) here
2359 because of early clobber register reloads or it is a rare
2360 or non-important thing to be worth to do it. */
2361 overall
= losers
* LRA_LOSER_COST_FACTOR
+ reject
;
2362 if ((best_losers
== 0 || losers
!= 0) && best_overall
< overall
)
2364 if (lra_dump_file
!= NULL
)
2365 fprintf (lra_dump_file
,
2366 " alt=%d,overall=%d,losers=%d -- refuse\n",
2367 nalt
, overall
, losers
);
2371 curr_alt
[nop
] = this_alternative
;
2372 COPY_HARD_REG_SET (curr_alt_set
[nop
], this_alternative_set
);
2373 curr_alt_win
[nop
] = this_alternative_win
;
2374 curr_alt_match_win
[nop
] = this_alternative_match_win
;
2375 curr_alt_offmemok
[nop
] = this_alternative_offmemok
;
2376 curr_alt_matches
[nop
] = this_alternative_matches
;
2378 if (this_alternative_matches
>= 0
2379 && !did_match
&& !this_alternative_win
)
2380 curr_alt_win
[this_alternative_matches
] = false;
2382 if (early_clobber_p
&& operand_reg
[nop
] != NULL_RTX
)
2383 early_clobbered_nops
[early_clobbered_regs_num
++] = nop
;
2385 if (curr_insn_set
!= NULL_RTX
&& n_operands
== 2
2386 /* Prevent processing non-move insns. */
2387 && (GET_CODE (SET_SRC (curr_insn_set
)) == SUBREG
2388 || SET_SRC (curr_insn_set
) == no_subreg_reg_operand
[1])
2389 && ((! curr_alt_win
[0] && ! curr_alt_win
[1]
2390 && REG_P (no_subreg_reg_operand
[0])
2391 && REG_P (no_subreg_reg_operand
[1])
2392 && (reg_in_class_p (no_subreg_reg_operand
[0], curr_alt
[1])
2393 || reg_in_class_p (no_subreg_reg_operand
[1], curr_alt
[0])))
2394 || (! curr_alt_win
[0] && curr_alt_win
[1]
2395 && REG_P (no_subreg_reg_operand
[1])
2396 && reg_in_class_p (no_subreg_reg_operand
[1], curr_alt
[0]))
2397 || (curr_alt_win
[0] && ! curr_alt_win
[1]
2398 && REG_P (no_subreg_reg_operand
[0])
2399 && reg_in_class_p (no_subreg_reg_operand
[0], curr_alt
[1])
2400 && (! CONST_POOL_OK_P (curr_operand_mode
[1],
2401 no_subreg_reg_operand
[1])
2402 || (targetm
.preferred_reload_class
2403 (no_subreg_reg_operand
[1],
2404 (enum reg_class
) curr_alt
[1]) != NO_REGS
))
2405 /* If it is a result of recent elimination in move
2406 insn we can transform it into an add still by
2407 using this alternative. */
2408 && GET_CODE (no_subreg_reg_operand
[1]) != PLUS
)))
2410 /* We have a move insn and a new reload insn will be similar
2411 to the current insn. We should avoid such situation as it
2412 results in LRA cycling. */
2413 overall
+= LRA_MAX_REJECT
;
2416 curr_alt_dont_inherit_ops_num
= 0;
2417 for (nop
= 0; nop
< early_clobbered_regs_num
; nop
++)
2419 int i
, j
, clobbered_hard_regno
, first_conflict_j
, last_conflict_j
;
2420 HARD_REG_SET temp_set
;
2422 i
= early_clobbered_nops
[nop
];
2423 if ((! curr_alt_win
[i
] && ! curr_alt_match_win
[i
])
2424 || hard_regno
[i
] < 0)
2426 lra_assert (operand_reg
[i
] != NULL_RTX
);
2427 clobbered_hard_regno
= hard_regno
[i
];
2428 CLEAR_HARD_REG_SET (temp_set
);
2429 add_to_hard_reg_set (&temp_set
, biggest_mode
[i
], clobbered_hard_regno
);
2430 first_conflict_j
= last_conflict_j
= -1;
2431 for (j
= 0; j
< n_operands
; j
++)
2433 /* We don't want process insides of match_operator and
2434 match_parallel because otherwise we would process
2435 their operands once again generating a wrong
2437 || curr_static_id
->operand
[j
].is_operator
)
2439 else if ((curr_alt_matches
[j
] == i
&& curr_alt_match_win
[j
])
2440 || (curr_alt_matches
[i
] == j
&& curr_alt_match_win
[i
]))
2442 /* If we don't reload j-th operand, check conflicts. */
2443 else if ((curr_alt_win
[j
] || curr_alt_match_win
[j
])
2444 && uses_hard_regs_p (*curr_id
->operand_loc
[j
], temp_set
))
2446 if (first_conflict_j
< 0)
2447 first_conflict_j
= j
;
2448 last_conflict_j
= j
;
2450 if (last_conflict_j
< 0)
2452 /* If earlyclobber operand conflicts with another
2453 non-matching operand which is actually the same register
2454 as the earlyclobber operand, it is better to reload the
2455 another operand as an operand matching the earlyclobber
2456 operand can be also the same. */
2457 if (first_conflict_j
== last_conflict_j
2458 && operand_reg
[last_conflict_j
]
2459 != NULL_RTX
&& ! curr_alt_match_win
[last_conflict_j
]
2460 && REGNO (operand_reg
[i
]) == REGNO (operand_reg
[last_conflict_j
]))
2462 curr_alt_win
[last_conflict_j
] = false;
2463 curr_alt_dont_inherit_ops
[curr_alt_dont_inherit_ops_num
++]
2466 /* Early clobber was already reflected in REJECT. */
2467 lra_assert (reject
> 0);
2468 if (lra_dump_file
!= NULL
)
2471 " %d Conflict early clobber reload: reject--\n",
2474 overall
+= LRA_LOSER_COST_FACTOR
- 1;
2478 /* We need to reload early clobbered register and the
2479 matched registers. */
2480 for (j
= 0; j
< n_operands
; j
++)
2481 if (curr_alt_matches
[j
] == i
)
2483 curr_alt_match_win
[j
] = false;
2485 overall
+= LRA_LOSER_COST_FACTOR
;
2487 if (! curr_alt_match_win
[i
])
2488 curr_alt_dont_inherit_ops
[curr_alt_dont_inherit_ops_num
++] = i
;
2491 /* Remember pseudos used for match reloads are never
2493 lra_assert (curr_alt_matches
[i
] >= 0);
2494 curr_alt_win
[curr_alt_matches
[i
]] = false;
2496 curr_alt_win
[i
] = curr_alt_match_win
[i
] = false;
2498 /* Early clobber was already reflected in REJECT. */
2499 lra_assert (reject
> 0);
2500 if (lra_dump_file
!= NULL
)
2503 " %d Matched conflict early clobber reloads:"
2507 overall
+= LRA_LOSER_COST_FACTOR
- 1;
2510 if (lra_dump_file
!= NULL
)
2511 fprintf (lra_dump_file
, " alt=%d,overall=%d,losers=%d,rld_nregs=%d\n",
2512 nalt
, overall
, losers
, reload_nregs
);
2514 /* If this alternative can be made to work by reloading, and it
2515 needs less reloading than the others checked so far, record
2516 it as the chosen goal for reloading. */
2517 if ((best_losers
!= 0 && losers
== 0)
2518 || (((best_losers
== 0 && losers
== 0)
2519 || (best_losers
!= 0 && losers
!= 0))
2520 && (best_overall
> overall
2521 || (best_overall
== overall
2522 /* If the cost of the reloads is the same,
2523 prefer alternative which requires minimal
2524 number of reload regs. */
2525 && (reload_nregs
< best_reload_nregs
2526 || (reload_nregs
== best_reload_nregs
2527 && (best_reload_sum
< reload_sum
2528 || (best_reload_sum
== reload_sum
2529 && nalt
< goal_alt_number
))))))))
2531 for (nop
= 0; nop
< n_operands
; nop
++)
2533 goal_alt_win
[nop
] = curr_alt_win
[nop
];
2534 goal_alt_match_win
[nop
] = curr_alt_match_win
[nop
];
2535 goal_alt_matches
[nop
] = curr_alt_matches
[nop
];
2536 goal_alt
[nop
] = curr_alt
[nop
];
2537 goal_alt_offmemok
[nop
] = curr_alt_offmemok
[nop
];
2539 goal_alt_dont_inherit_ops_num
= curr_alt_dont_inherit_ops_num
;
2540 for (nop
= 0; nop
< curr_alt_dont_inherit_ops_num
; nop
++)
2541 goal_alt_dont_inherit_ops
[nop
] = curr_alt_dont_inherit_ops
[nop
];
2542 goal_alt_swapped
= curr_swapped
;
2543 best_overall
= overall
;
2544 best_losers
= losers
;
2545 best_reload_nregs
= reload_nregs
;
2546 best_reload_sum
= reload_sum
;
2547 goal_alt_number
= nalt
;
2550 /* Everything is satisfied. Do not process alternatives
2559 /* Make reload base reg + disp from address AD. Return the new pseudo. */
2561 base_plus_disp_to_reg (struct address_info
*ad
)
2566 lra_assert (ad
->base
== ad
->base_term
&& ad
->disp
== ad
->disp_term
);
2567 cl
= base_reg_class (ad
->mode
, ad
->as
, ad
->base_outer_code
,
2568 get_index_code (ad
));
2569 new_reg
= lra_create_new_reg (GET_MODE (*ad
->base_term
), NULL_RTX
,
2571 lra_emit_add (new_reg
, *ad
->base_term
, *ad
->disp_term
);
2575 /* Make reload of index part of address AD. Return the new
2578 index_part_to_reg (struct address_info
*ad
)
2582 new_reg
= lra_create_new_reg (GET_MODE (*ad
->index
), NULL_RTX
,
2583 INDEX_REG_CLASS
, "index term");
2584 expand_mult (GET_MODE (*ad
->index
), *ad
->index_term
,
2585 GEN_INT (get_index_scale (ad
)), new_reg
, 1);
2589 /* Return true if we can add a displacement to address AD, even if that
2590 makes the address invalid. The fix-up code requires any new address
2591 to be the sum of the BASE_TERM, INDEX and DISP_TERM fields. */
2593 can_add_disp_p (struct address_info
*ad
)
2595 return (!ad
->autoinc_p
2596 && ad
->segment
== NULL
2597 && ad
->base
== ad
->base_term
2598 && ad
->disp
== ad
->disp_term
);
2601 /* Make equiv substitution in address AD. Return true if a substitution
2604 equiv_address_substitution (struct address_info
*ad
)
2606 rtx base_reg
, new_base_reg
, index_reg
, new_index_reg
, *base_term
, *index_term
;
2607 HOST_WIDE_INT disp
, scale
;
2610 base_term
= strip_subreg (ad
->base_term
);
2611 if (base_term
== NULL
)
2612 base_reg
= new_base_reg
= NULL_RTX
;
2615 base_reg
= *base_term
;
2616 new_base_reg
= get_equiv_with_elimination (base_reg
, curr_insn
);
2618 index_term
= strip_subreg (ad
->index_term
);
2619 if (index_term
== NULL
)
2620 index_reg
= new_index_reg
= NULL_RTX
;
2623 index_reg
= *index_term
;
2624 new_index_reg
= get_equiv_with_elimination (index_reg
, curr_insn
);
2626 if (base_reg
== new_base_reg
&& index_reg
== new_index_reg
)
2630 if (lra_dump_file
!= NULL
)
2632 fprintf (lra_dump_file
, "Changing address in insn %d ",
2633 INSN_UID (curr_insn
));
2634 dump_value_slim (lra_dump_file
, *ad
->outer
, 1);
2636 if (base_reg
!= new_base_reg
)
2638 if (REG_P (new_base_reg
))
2640 *base_term
= new_base_reg
;
2643 else if (GET_CODE (new_base_reg
) == PLUS
2644 && REG_P (XEXP (new_base_reg
, 0))
2645 && CONST_INT_P (XEXP (new_base_reg
, 1))
2646 && can_add_disp_p (ad
))
2648 disp
+= INTVAL (XEXP (new_base_reg
, 1));
2649 *base_term
= XEXP (new_base_reg
, 0);
2652 if (ad
->base_term2
!= NULL
)
2653 *ad
->base_term2
= *ad
->base_term
;
2655 if (index_reg
!= new_index_reg
)
2657 if (REG_P (new_index_reg
))
2659 *index_term
= new_index_reg
;
2662 else if (GET_CODE (new_index_reg
) == PLUS
2663 && REG_P (XEXP (new_index_reg
, 0))
2664 && CONST_INT_P (XEXP (new_index_reg
, 1))
2665 && can_add_disp_p (ad
)
2666 && (scale
= get_index_scale (ad
)))
2668 disp
+= INTVAL (XEXP (new_index_reg
, 1)) * scale
;
2669 *index_term
= XEXP (new_index_reg
, 0);
2675 if (ad
->disp
!= NULL
)
2676 *ad
->disp
= plus_constant (GET_MODE (*ad
->inner
), *ad
->disp
, disp
);
2679 *ad
->inner
= plus_constant (GET_MODE (*ad
->inner
), *ad
->inner
, disp
);
2680 update_address (ad
);
2684 if (lra_dump_file
!= NULL
)
2687 fprintf (lra_dump_file
, " -- no change\n");
2690 fprintf (lra_dump_file
, " on equiv ");
2691 dump_value_slim (lra_dump_file
, *ad
->outer
, 1);
2692 fprintf (lra_dump_file
, "\n");
2698 /* Major function to make reloads for an address in operand NOP.
2699 The supported cases are:
2701 1) an address that existed before LRA started, at which point it
2702 must have been valid. These addresses are subject to elimination
2703 and may have become invalid due to the elimination offset being out
2706 2) an address created by forcing a constant to memory
2707 (force_const_to_mem). The initial form of these addresses might
2708 not be valid, and it is this function's job to make them valid.
2710 3) a frame address formed from a register and a (possibly zero)
2711 constant offset. As above, these addresses might not be valid and
2712 this function must make them so.
2714 Add reloads to the lists *BEFORE and *AFTER. We might need to add
2715 reloads to *AFTER because of inc/dec, {pre, post} modify in the
2716 address. Return true for any RTL change.
2718 The function is a helper function which does not produce all
2719 transformations which can be necessary. It does just basic steps.
2720 To do all necessary transformations use function
2723 process_address_1 (int nop
, rtx
*before
, rtx
*after
)
2725 struct address_info ad
;
2727 rtx op
= *curr_id
->operand_loc
[nop
];
2728 const char *constraint
= curr_static_id
->operand
[nop
].constraint
;
2729 enum constraint_num cn
= lookup_constraint (constraint
);
2732 if (insn_extra_address_constraint (cn
))
2733 decompose_lea_address (&ad
, curr_id
->operand_loc
[nop
]);
2734 else if (MEM_P (op
))
2735 decompose_mem_address (&ad
, op
);
2736 else if (GET_CODE (op
) == SUBREG
2737 && MEM_P (SUBREG_REG (op
)))
2738 decompose_mem_address (&ad
, SUBREG_REG (op
));
2741 change_p
= equiv_address_substitution (&ad
);
2742 if (ad
.base_term
!= NULL
2743 && (process_addr_reg
2744 (ad
.base_term
, before
,
2746 && !(REG_P (*ad
.base_term
)
2747 && find_regno_note (curr_insn
, REG_DEAD
,
2748 REGNO (*ad
.base_term
)) != NULL_RTX
)
2750 base_reg_class (ad
.mode
, ad
.as
, ad
.base_outer_code
,
2751 get_index_code (&ad
)))))
2754 if (ad
.base_term2
!= NULL
)
2755 *ad
.base_term2
= *ad
.base_term
;
2757 if (ad
.index_term
!= NULL
2758 && process_addr_reg (ad
.index_term
, before
, NULL
, INDEX_REG_CLASS
))
2761 /* Target hooks sometimes don't treat extra-constraint addresses as
2762 legitimate address_operands, so handle them specially. */
2763 if (insn_extra_address_constraint (cn
)
2764 && satisfies_address_constraint_p (&ad
, cn
))
2767 /* There are three cases where the shape of *AD.INNER may now be invalid:
2769 1) the original address was valid, but either elimination or
2770 equiv_address_substitution was applied and that made
2771 the address invalid.
2773 2) the address is an invalid symbolic address created by
2776 3) the address is a frame address with an invalid offset.
2778 All these cases involve a non-autoinc address, so there is no
2779 point revalidating other types. */
2780 if (ad
.autoinc_p
|| valid_address_p (&ad
))
2783 /* Any index existed before LRA started, so we can assume that the
2784 presence and shape of the index is valid. */
2785 push_to_sequence (*before
);
2786 lra_assert (ad
.disp
== ad
.disp_term
);
2787 if (ad
.base
== NULL
)
2789 if (ad
.index
== NULL
)
2792 enum reg_class cl
= base_reg_class (ad
.mode
, ad
.as
,
2794 rtx addr
= *ad
.inner
;
2796 new_reg
= lra_create_new_reg (Pmode
, NULL_RTX
, cl
, "addr");
2800 rtx last
= get_last_insn ();
2802 /* addr => lo_sum (new_base, addr), case (2) above. */
2803 insn
= emit_insn (gen_rtx_SET
2805 gen_rtx_HIGH (Pmode
, copy_rtx (addr
))));
2806 code
= recog_memoized (insn
);
2809 *ad
.inner
= gen_rtx_LO_SUM (Pmode
, new_reg
, addr
);
2810 if (! valid_address_p (ad
.mode
, *ad
.outer
, ad
.as
))
2812 /* Try to put lo_sum into register. */
2813 insn
= emit_insn (gen_rtx_SET
2815 gen_rtx_LO_SUM (Pmode
, new_reg
, addr
)));
2816 code
= recog_memoized (insn
);
2819 *ad
.inner
= new_reg
;
2820 if (! valid_address_p (ad
.mode
, *ad
.outer
, ad
.as
))
2830 delete_insns_since (last
);
2835 /* addr => new_base, case (2) above. */
2836 lra_emit_move (new_reg
, addr
);
2837 *ad
.inner
= new_reg
;
2842 /* index * scale + disp => new base + index * scale,
2844 enum reg_class cl
= base_reg_class (ad
.mode
, ad
.as
, PLUS
,
2845 GET_CODE (*ad
.index
));
2847 lra_assert (INDEX_REG_CLASS
!= NO_REGS
);
2848 new_reg
= lra_create_new_reg (Pmode
, NULL_RTX
, cl
, "disp");
2849 lra_emit_move (new_reg
, *ad
.disp
);
2850 *ad
.inner
= simplify_gen_binary (PLUS
, GET_MODE (new_reg
),
2851 new_reg
, *ad
.index
);
2854 else if (ad
.index
== NULL
)
2858 rtx set
, insns
, last_insn
;
2859 /* base + disp => new base, cases (1) and (3) above. */
2860 /* Another option would be to reload the displacement into an
2861 index register. However, postreload has code to optimize
2862 address reloads that have the same base and different
2863 displacements, so reloading into an index register would
2864 not necessarily be a win. */
2866 new_reg
= base_plus_disp_to_reg (&ad
);
2867 insns
= get_insns ();
2868 last_insn
= get_last_insn ();
2869 /* If we generated at least two insns, try last insn source as
2870 an address. If we succeed, we generate one less insn. */
2871 if (last_insn
!= insns
&& (set
= single_set (last_insn
)) != NULL_RTX
2872 && GET_CODE (SET_SRC (set
)) == PLUS
2873 && REG_P (XEXP (SET_SRC (set
), 0))
2874 && CONSTANT_P (XEXP (SET_SRC (set
), 1)))
2876 *ad
.inner
= SET_SRC (set
);
2877 if (valid_address_p (ad
.mode
, *ad
.outer
, ad
.as
))
2879 *ad
.base_term
= XEXP (SET_SRC (set
), 0);
2880 *ad
.disp_term
= XEXP (SET_SRC (set
), 1);
2881 cl
= base_reg_class (ad
.mode
, ad
.as
, ad
.base_outer_code
,
2882 get_index_code (&ad
));
2883 regno
= REGNO (*ad
.base_term
);
2884 if (regno
>= FIRST_PSEUDO_REGISTER
2885 && cl
!= lra_get_allocno_class (regno
))
2886 lra_change_class (regno
, cl
, " Change to", true);
2887 new_reg
= SET_SRC (set
);
2888 delete_insns_since (PREV_INSN (last_insn
));
2893 *ad
.inner
= new_reg
;
2895 else if (ad
.disp_term
!= NULL
)
2897 /* base + scale * index + disp => new base + scale * index,
2899 new_reg
= base_plus_disp_to_reg (&ad
);
2900 *ad
.inner
= simplify_gen_binary (PLUS
, GET_MODE (new_reg
),
2901 new_reg
, *ad
.index
);
2903 else if (get_index_scale (&ad
) == 1)
2905 /* The last transformation to one reg will be made in
2906 curr_insn_transform function. */
2912 /* base + scale * index => base + new_reg,
2914 Index part of address may become invalid. For example, we
2915 changed pseudo on the equivalent memory and a subreg of the
2916 pseudo onto the memory of different mode for which the scale is
2918 new_reg
= index_part_to_reg (&ad
);
2919 *ad
.inner
= simplify_gen_binary (PLUS
, GET_MODE (new_reg
),
2920 *ad
.base_term
, new_reg
);
2922 *before
= get_insns ();
2927 /* Do address reloads until it is necessary. Use process_address_1 as
2928 a helper function. Return true for any RTL changes. */
2930 process_address (int nop
, rtx
*before
, rtx
*after
)
2934 while (process_address_1 (nop
, before
, after
))
2939 /* Emit insns to reload VALUE into a new register. VALUE is an
2940 auto-increment or auto-decrement RTX whose operand is a register or
2941 memory location; so reloading involves incrementing that location.
2942 IN is either identical to VALUE, or some cheaper place to reload
2943 value being incremented/decremented from.
2945 INC_AMOUNT is the number to increment or decrement by (always
2946 positive and ignored for POST_MODIFY/PRE_MODIFY).
2948 Return pseudo containing the result. */
2950 emit_inc (enum reg_class new_rclass
, rtx in
, rtx value
, int inc_amount
)
2952 /* REG or MEM to be copied and incremented. */
2953 rtx incloc
= XEXP (value
, 0);
2954 /* Nonzero if increment after copying. */
2955 int post
= (GET_CODE (value
) == POST_DEC
|| GET_CODE (value
) == POST_INC
2956 || GET_CODE (value
) == POST_MODIFY
);
2961 rtx real_in
= in
== value
? incloc
: in
;
2965 if (GET_CODE (value
) == PRE_MODIFY
|| GET_CODE (value
) == POST_MODIFY
)
2967 lra_assert (GET_CODE (XEXP (value
, 1)) == PLUS
2968 || GET_CODE (XEXP (value
, 1)) == MINUS
);
2969 lra_assert (rtx_equal_p (XEXP (XEXP (value
, 1), 0), XEXP (value
, 0)));
2970 plus_p
= GET_CODE (XEXP (value
, 1)) == PLUS
;
2971 inc
= XEXP (XEXP (value
, 1), 1);
2975 if (GET_CODE (value
) == PRE_DEC
|| GET_CODE (value
) == POST_DEC
)
2976 inc_amount
= -inc_amount
;
2978 inc
= GEN_INT (inc_amount
);
2981 if (! post
&& REG_P (incloc
))
2984 result
= lra_create_new_reg (GET_MODE (value
), value
, new_rclass
,
2987 if (real_in
!= result
)
2989 /* First copy the location to the result register. */
2990 lra_assert (REG_P (result
));
2991 emit_insn (gen_move_insn (result
, real_in
));
2994 /* We suppose that there are insns to add/sub with the constant
2995 increment permitted in {PRE/POST)_{DEC/INC/MODIFY}. At least the
2996 old reload worked with this assumption. If the assumption
2997 becomes wrong, we should use approach in function
2998 base_plus_disp_to_reg. */
3001 /* See if we can directly increment INCLOC. */
3002 last
= get_last_insn ();
3003 add_insn
= emit_insn (plus_p
3004 ? gen_add2_insn (incloc
, inc
)
3005 : gen_sub2_insn (incloc
, inc
));
3007 code
= recog_memoized (add_insn
);
3010 if (! post
&& result
!= incloc
)
3011 emit_insn (gen_move_insn (result
, incloc
));
3014 delete_insns_since (last
);
3017 /* If couldn't do the increment directly, must increment in RESULT.
3018 The way we do this depends on whether this is pre- or
3019 post-increment. For pre-increment, copy INCLOC to the reload
3020 register, increment it there, then save back. */
3023 if (real_in
!= result
)
3024 emit_insn (gen_move_insn (result
, real_in
));
3026 emit_insn (gen_add2_insn (result
, inc
));
3028 emit_insn (gen_sub2_insn (result
, inc
));
3029 if (result
!= incloc
)
3030 emit_insn (gen_move_insn (incloc
, result
));
3036 Because this might be a jump insn or a compare, and because
3037 RESULT may not be available after the insn in an input
3038 reload, we must do the incrementing before the insn being
3041 We have already copied IN to RESULT. Increment the copy in
3042 RESULT, save that back, then decrement RESULT so it has
3043 the original value. */
3045 emit_insn (gen_add2_insn (result
, inc
));
3047 emit_insn (gen_sub2_insn (result
, inc
));
3048 emit_insn (gen_move_insn (incloc
, result
));
3049 /* Restore non-modified value for the result. We prefer this
3050 way because it does not require an additional hard
3054 if (CONST_INT_P (inc
))
3055 emit_insn (gen_add2_insn (result
,
3056 gen_int_mode (-INTVAL (inc
),
3057 GET_MODE (result
))));
3059 emit_insn (gen_sub2_insn (result
, inc
));
3062 emit_insn (gen_add2_insn (result
, inc
));
3067 /* Return true if the current move insn does not need processing as we
3068 already know that it satisfies its constraints. */
3070 simple_move_p (void)
3073 enum reg_class dclass
, sclass
;
3075 lra_assert (curr_insn_set
!= NULL_RTX
);
3076 dest
= SET_DEST (curr_insn_set
);
3077 src
= SET_SRC (curr_insn_set
);
3078 return ((dclass
= get_op_class (dest
)) != NO_REGS
3079 && (sclass
= get_op_class (src
)) != NO_REGS
3080 /* The backend guarantees that register moves of cost 2
3081 never need reloads. */
3082 && targetm
.register_move_cost (GET_MODE (src
), dclass
, sclass
) == 2);
3085 /* Swap operands NOP and NOP + 1. */
3087 swap_operands (int nop
)
3089 enum machine_mode mode
= curr_operand_mode
[nop
];
3090 curr_operand_mode
[nop
] = curr_operand_mode
[nop
+ 1];
3091 curr_operand_mode
[nop
+ 1] = mode
;
3092 rtx x
= *curr_id
->operand_loc
[nop
];
3093 *curr_id
->operand_loc
[nop
] = *curr_id
->operand_loc
[nop
+ 1];
3094 *curr_id
->operand_loc
[nop
+ 1] = x
;
3095 /* Swap the duplicates too. */
3096 lra_update_dup (curr_id
, nop
);
3097 lra_update_dup (curr_id
, nop
+ 1);
3100 /* Main entry point of the constraint code: search the body of the
3101 current insn to choose the best alternative. It is mimicking insn
3102 alternative cost calculation model of former reload pass. That is
3103 because machine descriptions were written to use this model. This
3104 model can be changed in future. Make commutative operand exchange
3107 Return true if some RTL changes happened during function call. */
3109 curr_insn_transform (void)
3115 signed char goal_alt_matched
[MAX_RECOG_OPERANDS
][MAX_RECOG_OPERANDS
];
3116 signed char match_inputs
[MAX_RECOG_OPERANDS
+ 1];
3119 /* Flag that the insn has been changed through a transformation. */
3122 #ifdef SECONDARY_MEMORY_NEEDED
3125 int max_regno_before
;
3126 int reused_alternative_num
;
3128 curr_insn_set
= single_set (curr_insn
);
3129 if (curr_insn_set
!= NULL_RTX
&& simple_move_p ())
3132 no_input_reloads_p
= no_output_reloads_p
= false;
3133 goal_alt_number
= -1;
3134 change_p
= sec_mem_p
= false;
3135 /* JUMP_INSNs and CALL_INSNs are not allowed to have any output
3136 reloads; neither are insns that SET cc0. Insns that use CC0 are
3137 not allowed to have any input reloads. */
3138 if (JUMP_P (curr_insn
) || CALL_P (curr_insn
))
3139 no_output_reloads_p
= true;
3142 if (reg_referenced_p (cc0_rtx
, PATTERN (curr_insn
)))
3143 no_input_reloads_p
= true;
3144 if (reg_set_p (cc0_rtx
, PATTERN (curr_insn
)))
3145 no_output_reloads_p
= true;
3148 n_operands
= curr_static_id
->n_operands
;
3149 n_alternatives
= curr_static_id
->n_alternatives
;
3151 /* Just return "no reloads" if insn has no operands with
3153 if (n_operands
== 0 || n_alternatives
== 0)
3156 max_regno_before
= max_reg_num ();
3158 for (i
= 0; i
< n_operands
; i
++)
3160 goal_alt_matched
[i
][0] = -1;
3161 goal_alt_matches
[i
] = -1;
3164 commutative
= curr_static_id
->commutative
;
3166 /* Now see what we need for pseudos that didn't get hard regs or got
3167 the wrong kind of hard reg. For this, we must consider all the
3168 operands together against the register constraints. */
3170 best_losers
= best_overall
= INT_MAX
;
3171 best_reload_sum
= 0;
3173 curr_swapped
= false;
3174 goal_alt_swapped
= false;
3176 /* Make equivalence substitution and memory subreg elimination
3177 before address processing because an address legitimacy can
3178 depend on memory mode. */
3179 for (i
= 0; i
< n_operands
; i
++)
3181 rtx op
= *curr_id
->operand_loc
[i
];
3182 rtx subst
, old
= op
;
3183 bool op_change_p
= false;
3185 if (GET_CODE (old
) == SUBREG
)
3186 old
= SUBREG_REG (old
);
3187 subst
= get_equiv_with_elimination (old
, curr_insn
);
3190 subst
= copy_rtx (subst
);
3191 lra_assert (REG_P (old
));
3192 if (GET_CODE (op
) == SUBREG
)
3193 SUBREG_REG (op
) = subst
;
3195 *curr_id
->operand_loc
[i
] = subst
;
3196 if (lra_dump_file
!= NULL
)
3198 fprintf (lra_dump_file
,
3199 "Changing pseudo %d in operand %i of insn %u on equiv ",
3200 REGNO (old
), i
, INSN_UID (curr_insn
));
3201 dump_value_slim (lra_dump_file
, subst
, 1);
3202 fprintf (lra_dump_file
, "\n");
3204 op_change_p
= change_p
= true;
3206 if (simplify_operand_subreg (i
, GET_MODE (old
)) || op_change_p
)
3209 lra_update_dup (curr_id
, i
);
3213 /* Reload address registers and displacements. We do it before
3214 finding an alternative because of memory constraints. */
3215 before
= after
= NULL_RTX
;
3216 for (i
= 0; i
< n_operands
; i
++)
3217 if (! curr_static_id
->operand
[i
].is_operator
3218 && process_address (i
, &before
, &after
))
3221 lra_update_dup (curr_id
, i
);
3225 /* If we've changed the instruction then any alternative that
3226 we chose previously may no longer be valid. */
3227 lra_set_used_insn_alternative (curr_insn
, -1);
3229 if (curr_insn_set
!= NULL_RTX
3230 && check_and_process_move (&change_p
, &sec_mem_p
))
3235 reused_alternative_num
= curr_id
->used_insn_alternative
;
3236 if (lra_dump_file
!= NULL
&& reused_alternative_num
>= 0)
3237 fprintf (lra_dump_file
, "Reusing alternative %d for insn #%u\n",
3238 reused_alternative_num
, INSN_UID (curr_insn
));
3240 if (process_alt_operands (reused_alternative_num
))
3243 /* If insn is commutative (it's safe to exchange a certain pair of
3244 operands) then we need to try each alternative twice, the second
3245 time matching those two operands as if we had exchanged them. To
3246 do this, really exchange them in operands.
3248 If we have just tried the alternatives the second time, return
3249 operands to normal and drop through. */
3251 if (reused_alternative_num
< 0 && commutative
>= 0)
3253 curr_swapped
= !curr_swapped
;
3256 swap_operands (commutative
);
3260 swap_operands (commutative
);
3263 if (! alt_p
&& ! sec_mem_p
)
3265 /* No alternative works with reloads?? */
3266 if (INSN_CODE (curr_insn
) >= 0)
3267 fatal_insn ("unable to generate reloads for:", curr_insn
);
3268 error_for_asm (curr_insn
,
3269 "inconsistent operand constraints in an %<asm%>");
3270 /* Avoid further trouble with this insn. */
3271 PATTERN (curr_insn
) = gen_rtx_USE (VOIDmode
, const0_rtx
);
3272 lra_invalidate_insn_data (curr_insn
);
3276 /* If the best alternative is with operands 1 and 2 swapped, swap
3277 them. Update the operand numbers of any reloads already
3280 if (goal_alt_swapped
)
3282 if (lra_dump_file
!= NULL
)
3283 fprintf (lra_dump_file
, " Commutative operand exchange in insn %u\n",
3284 INSN_UID (curr_insn
));
3286 /* Swap the duplicates too. */
3287 swap_operands (commutative
);
3291 #ifdef SECONDARY_MEMORY_NEEDED
3292 /* Some target macros SECONDARY_MEMORY_NEEDED (e.g. x86) are defined
3293 too conservatively. So we use the secondary memory only if there
3294 is no any alternative without reloads. */
3295 use_sec_mem_p
= false;
3297 use_sec_mem_p
= true;
3300 for (i
= 0; i
< n_operands
; i
++)
3301 if (! goal_alt_win
[i
] && ! goal_alt_match_win
[i
])
3303 use_sec_mem_p
= i
< n_operands
;
3308 rtx new_reg
, src
, dest
, rld
;
3309 enum machine_mode sec_mode
, rld_mode
;
3311 lra_assert (sec_mem_p
);
3312 lra_assert (curr_static_id
->operand
[0].type
== OP_OUT
3313 && curr_static_id
->operand
[1].type
== OP_IN
);
3314 dest
= *curr_id
->operand_loc
[0];
3315 src
= *curr_id
->operand_loc
[1];
3316 rld
= (GET_MODE_SIZE (GET_MODE (dest
)) <= GET_MODE_SIZE (GET_MODE (src
))
3318 rld_mode
= GET_MODE (rld
);
3319 #ifdef SECONDARY_MEMORY_NEEDED_MODE
3320 sec_mode
= SECONDARY_MEMORY_NEEDED_MODE (rld_mode
);
3322 sec_mode
= rld_mode
;
3324 new_reg
= lra_create_new_reg (sec_mode
, NULL_RTX
,
3325 NO_REGS
, "secondary");
3326 /* If the mode is changed, it should be wider. */
3327 lra_assert (GET_MODE_SIZE (sec_mode
) >= GET_MODE_SIZE (rld_mode
));
3328 if (sec_mode
!= rld_mode
)
3330 /* If the target says specifically to use another mode for
3331 secondary memory moves we can not reuse the original
3333 after
= emit_spill_move (false, new_reg
, dest
);
3334 lra_process_new_insns (curr_insn
, NULL_RTX
, after
,
3335 "Inserting the sec. move");
3336 /* We may have non null BEFORE here (e.g. after address
3338 push_to_sequence (before
);
3339 before
= emit_spill_move (true, new_reg
, src
);
3341 before
= get_insns ();
3343 lra_process_new_insns (curr_insn
, before
, NULL_RTX
, "Changing on");
3344 lra_set_insn_deleted (curr_insn
);
3346 else if (dest
== rld
)
3348 *curr_id
->operand_loc
[0] = new_reg
;
3349 after
= emit_spill_move (false, new_reg
, dest
);
3350 lra_process_new_insns (curr_insn
, NULL_RTX
, after
,
3351 "Inserting the sec. move");
3355 *curr_id
->operand_loc
[1] = new_reg
;
3356 /* See comments above. */
3357 push_to_sequence (before
);
3358 before
= emit_spill_move (true, new_reg
, src
);
3360 before
= get_insns ();
3362 lra_process_new_insns (curr_insn
, before
, NULL_RTX
,
3363 "Inserting the sec. move");
3365 lra_update_insn_regno_info (curr_insn
);
3370 lra_assert (goal_alt_number
>= 0);
3371 lra_set_used_insn_alternative (curr_insn
, goal_alt_number
);
3373 if (lra_dump_file
!= NULL
)
3377 fprintf (lra_dump_file
, " Choosing alt %d in insn %u:",
3378 goal_alt_number
, INSN_UID (curr_insn
));
3379 for (i
= 0; i
< n_operands
; i
++)
3381 p
= (curr_static_id
->operand_alternative
3382 [goal_alt_number
* n_operands
+ i
].constraint
);
3385 fprintf (lra_dump_file
, " (%d) ", i
);
3386 for (; *p
!= '\0' && *p
!= ',' && *p
!= '#'; p
++)
3387 fputc (*p
, lra_dump_file
);
3389 if (INSN_CODE (curr_insn
) >= 0
3390 && (p
= get_insn_name (INSN_CODE (curr_insn
))) != NULL
)
3391 fprintf (lra_dump_file
, " {%s}", p
);
3392 if (curr_id
->sp_offset
!= 0)
3393 fprintf (lra_dump_file
, " (sp_off=%" HOST_WIDE_INT_PRINT
"d)",
3394 curr_id
->sp_offset
);
3395 fprintf (lra_dump_file
, "\n");
3398 /* Right now, for any pair of operands I and J that are required to
3399 match, with J < I, goal_alt_matches[I] is J. Add I to
3400 goal_alt_matched[J]. */
3402 for (i
= 0; i
< n_operands
; i
++)
3403 if ((j
= goal_alt_matches
[i
]) >= 0)
3405 for (k
= 0; goal_alt_matched
[j
][k
] >= 0; k
++)
3407 /* We allow matching one output operand and several input
3410 || (curr_static_id
->operand
[j
].type
== OP_OUT
3411 && curr_static_id
->operand
[i
].type
== OP_IN
3412 && (curr_static_id
->operand
3413 [goal_alt_matched
[j
][0]].type
== OP_IN
)));
3414 goal_alt_matched
[j
][k
] = i
;
3415 goal_alt_matched
[j
][k
+ 1] = -1;
3418 for (i
= 0; i
< n_operands
; i
++)
3419 goal_alt_win
[i
] |= goal_alt_match_win
[i
];
3421 /* Any constants that aren't allowed and can't be reloaded into
3422 registers are here changed into memory references. */
3423 for (i
= 0; i
< n_operands
; i
++)
3424 if (goal_alt_win
[i
])
3427 enum reg_class new_class
;
3428 rtx reg
= *curr_id
->operand_loc
[i
];
3430 if (GET_CODE (reg
) == SUBREG
)
3431 reg
= SUBREG_REG (reg
);
3433 if (REG_P (reg
) && (regno
= REGNO (reg
)) >= FIRST_PSEUDO_REGISTER
)
3435 bool ok_p
= in_class_p (reg
, goal_alt
[i
], &new_class
);
3437 if (new_class
!= NO_REGS
&& get_reg_class (regno
) != new_class
)
3440 lra_change_class (regno
, new_class
, " Change to", true);
3446 const char *constraint
;
3448 rtx op
= *curr_id
->operand_loc
[i
];
3449 rtx subreg
= NULL_RTX
;
3450 enum machine_mode mode
= curr_operand_mode
[i
];
3452 if (GET_CODE (op
) == SUBREG
)
3455 op
= SUBREG_REG (op
);
3456 mode
= GET_MODE (op
);
3459 if (CONST_POOL_OK_P (mode
, op
)
3460 && ((targetm
.preferred_reload_class
3461 (op
, (enum reg_class
) goal_alt
[i
]) == NO_REGS
)
3462 || no_input_reloads_p
))
3464 rtx tem
= force_const_mem (mode
, op
);
3467 if (subreg
!= NULL_RTX
)
3468 tem
= gen_rtx_SUBREG (mode
, tem
, SUBREG_BYTE (subreg
));
3470 *curr_id
->operand_loc
[i
] = tem
;
3471 lra_update_dup (curr_id
, i
);
3472 process_address (i
, &before
, &after
);
3474 /* If the alternative accepts constant pool refs directly
3475 there will be no reload needed at all. */
3476 if (subreg
!= NULL_RTX
)
3478 /* Skip alternatives before the one requested. */
3479 constraint
= (curr_static_id
->operand_alternative
3480 [goal_alt_number
* n_operands
+ i
].constraint
);
3482 (c
= *constraint
) && c
!= ',' && c
!= '#';
3483 constraint
+= CONSTRAINT_LEN (c
, constraint
))
3485 enum constraint_num cn
= lookup_constraint (constraint
);
3486 if (insn_extra_memory_constraint (cn
)
3487 && satisfies_memory_constraint_p (tem
, cn
))
3490 if (c
== '\0' || c
== ',' || c
== '#')
3493 goal_alt_win
[i
] = true;
3497 for (i
= 0; i
< n_operands
; i
++)
3500 bool optional_p
= false;
3502 rtx op
= *curr_id
->operand_loc
[i
];
3504 if (goal_alt_win
[i
])
3506 if (goal_alt
[i
] == NO_REGS
3508 /* When we assign NO_REGS it means that we will not
3509 assign a hard register to the scratch pseudo by
3510 assigment pass and the scratch pseudo will be
3511 spilled. Spilled scratch pseudos are transformed
3512 back to scratches at the LRA end. */
3513 && lra_former_scratch_operand_p (curr_insn
, i
))
3515 int regno
= REGNO (op
);
3516 lra_change_class (regno
, NO_REGS
, " Change to", true);
3517 if (lra_get_regno_hard_regno (regno
) >= 0)
3518 /* We don't have to mark all insn affected by the
3519 spilled pseudo as there is only one such insn, the
3521 reg_renumber
[regno
] = -1;
3523 /* We can do an optional reload. If the pseudo got a hard
3524 reg, we might improve the code through inheritance. If
3525 it does not get a hard register we coalesce memory/memory
3526 moves later. Ignore move insns to avoid cycling. */
3528 && lra_undo_inheritance_iter
< LRA_MAX_INHERITANCE_PASSES
3529 && goal_alt
[i
] != NO_REGS
&& REG_P (op
)
3530 && (regno
= REGNO (op
)) >= FIRST_PSEUDO_REGISTER
3531 && regno
< new_regno_start
3532 && ! lra_former_scratch_p (regno
)
3533 && reg_renumber
[regno
] < 0
3534 && (curr_insn_set
== NULL_RTX
3535 || !((REG_P (SET_SRC (curr_insn_set
))
3536 || MEM_P (SET_SRC (curr_insn_set
))
3537 || GET_CODE (SET_SRC (curr_insn_set
)) == SUBREG
)
3538 && (REG_P (SET_DEST (curr_insn_set
))
3539 || MEM_P (SET_DEST (curr_insn_set
))
3540 || GET_CODE (SET_DEST (curr_insn_set
)) == SUBREG
))))
3546 /* Operands that match previous ones have already been handled. */
3547 if (goal_alt_matches
[i
] >= 0)
3550 /* We should not have an operand with a non-offsettable address
3551 appearing where an offsettable address will do. It also may
3552 be a case when the address should be special in other words
3553 not a general one (e.g. it needs no index reg). */
3554 if (goal_alt_matched
[i
][0] == -1 && goal_alt_offmemok
[i
] && MEM_P (op
))
3556 enum reg_class rclass
;
3557 rtx
*loc
= &XEXP (op
, 0);
3558 enum rtx_code code
= GET_CODE (*loc
);
3560 push_to_sequence (before
);
3561 rclass
= base_reg_class (GET_MODE (op
), MEM_ADDR_SPACE (op
),
3563 if (GET_RTX_CLASS (code
) == RTX_AUTOINC
)
3564 new_reg
= emit_inc (rclass
, *loc
, *loc
,
3565 /* This value does not matter for MODIFY. */
3566 GET_MODE_SIZE (GET_MODE (op
)));
3567 else if (get_reload_reg (OP_IN
, Pmode
, *loc
, rclass
, FALSE
,
3568 "offsetable address", &new_reg
))
3569 lra_emit_move (new_reg
, *loc
);
3570 before
= get_insns ();
3573 lra_update_dup (curr_id
, i
);
3575 else if (goal_alt_matched
[i
][0] == -1)
3577 enum machine_mode mode
;
3579 int hard_regno
, byte
;
3580 enum op_type type
= curr_static_id
->operand
[i
].type
;
3582 loc
= curr_id
->operand_loc
[i
];
3583 mode
= curr_operand_mode
[i
];
3584 if (GET_CODE (*loc
) == SUBREG
)
3586 reg
= SUBREG_REG (*loc
);
3587 byte
= SUBREG_BYTE (*loc
);
3589 /* Strict_low_part requires reload the register not
3590 the sub-register. */
3591 && (curr_static_id
->operand
[i
].strict_low
3592 || (GET_MODE_SIZE (mode
)
3593 <= GET_MODE_SIZE (GET_MODE (reg
))
3595 = get_try_hard_regno (REGNO (reg
))) >= 0
3596 && (simplify_subreg_regno
3598 GET_MODE (reg
), byte
, mode
) < 0)
3599 && (goal_alt
[i
] == NO_REGS
3600 || (simplify_subreg_regno
3601 (ira_class_hard_regs
[goal_alt
[i
]][0],
3602 GET_MODE (reg
), byte
, mode
) >= 0)))))
3604 loc
= &SUBREG_REG (*loc
);
3605 mode
= GET_MODE (*loc
);
3609 if (get_reload_reg (type
, mode
, old
, goal_alt
[i
],
3610 loc
!= curr_id
->operand_loc
[i
], "", &new_reg
)
3613 push_to_sequence (before
);
3614 lra_emit_move (new_reg
, old
);
3615 before
= get_insns ();
3620 && find_reg_note (curr_insn
, REG_UNUSED
, old
) == NULL_RTX
)
3623 lra_emit_move (type
== OP_INOUT
? copy_rtx (old
) : old
, new_reg
);
3625 after
= get_insns ();
3629 for (j
= 0; j
< goal_alt_dont_inherit_ops_num
; j
++)
3630 if (goal_alt_dont_inherit_ops
[j
] == i
)
3632 lra_set_regno_unique_value (REGNO (new_reg
));
3635 lra_update_dup (curr_id
, i
);
3637 else if (curr_static_id
->operand
[i
].type
== OP_IN
3638 && (curr_static_id
->operand
[goal_alt_matched
[i
][0]].type
3641 /* generate reloads for input and matched outputs. */
3642 match_inputs
[0] = i
;
3643 match_inputs
[1] = -1;
3644 match_reload (goal_alt_matched
[i
][0], match_inputs
,
3645 goal_alt
[i
], &before
, &after
);
3647 else if (curr_static_id
->operand
[i
].type
== OP_OUT
3648 && (curr_static_id
->operand
[goal_alt_matched
[i
][0]].type
3650 /* Generate reloads for output and matched inputs. */
3651 match_reload (i
, goal_alt_matched
[i
], goal_alt
[i
], &before
, &after
);
3652 else if (curr_static_id
->operand
[i
].type
== OP_IN
3653 && (curr_static_id
->operand
[goal_alt_matched
[i
][0]].type
3656 /* Generate reloads for matched inputs. */
3657 match_inputs
[0] = i
;
3658 for (j
= 0; (k
= goal_alt_matched
[i
][j
]) >= 0; j
++)
3659 match_inputs
[j
+ 1] = k
;
3660 match_inputs
[j
+ 1] = -1;
3661 match_reload (-1, match_inputs
, goal_alt
[i
], &before
, &after
);
3664 /* We must generate code in any case when function
3665 process_alt_operands decides that it is possible. */
3669 lra_assert (REG_P (op
));
3671 op
= *curr_id
->operand_loc
[i
]; /* Substitution. */
3672 if (GET_CODE (op
) == SUBREG
)
3673 op
= SUBREG_REG (op
);
3674 gcc_assert (REG_P (op
) && (int) REGNO (op
) >= new_regno_start
);
3675 bitmap_set_bit (&lra_optional_reload_pseudos
, REGNO (op
));
3676 lra_reg_info
[REGNO (op
)].restore_regno
= regno
;
3677 if (lra_dump_file
!= NULL
)
3678 fprintf (lra_dump_file
,
3679 " Making reload reg %d for reg %d optional\n",
3683 if (before
!= NULL_RTX
|| after
!= NULL_RTX
3684 || max_regno_before
!= max_reg_num ())
3688 lra_update_operator_dups (curr_id
);
3689 /* Something changes -- process the insn. */
3690 lra_update_insn_regno_info (curr_insn
);
3692 lra_process_new_insns (curr_insn
, before
, after
, "Inserting insn reload");
3696 /* Return true if X is in LIST. */
3698 in_list_p (rtx x
, rtx list
)
3700 for (; list
!= NULL_RTX
; list
= XEXP (list
, 1))
3701 if (XEXP (list
, 0) == x
)
3706 /* Return true if X contains an allocatable hard register (if
3707 HARD_REG_P) or a (spilled if SPILLED_P) pseudo. */
3709 contains_reg_p (rtx x
, bool hard_reg_p
, bool spilled_p
)
3715 code
= GET_CODE (x
);
3718 int regno
= REGNO (x
);
3719 HARD_REG_SET alloc_regs
;
3723 if (regno
>= FIRST_PSEUDO_REGISTER
)
3724 regno
= lra_get_regno_hard_regno (regno
);
3727 COMPL_HARD_REG_SET (alloc_regs
, lra_no_alloc_regs
);
3728 return overlaps_hard_reg_set_p (alloc_regs
, GET_MODE (x
), regno
);
3732 if (regno
< FIRST_PSEUDO_REGISTER
)
3736 return lra_get_regno_hard_regno (regno
) < 0;
3739 fmt
= GET_RTX_FORMAT (code
);
3740 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
3744 if (contains_reg_p (XEXP (x
, i
), hard_reg_p
, spilled_p
))
3747 else if (fmt
[i
] == 'E')
3749 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3750 if (contains_reg_p (XVECEXP (x
, i
, j
), hard_reg_p
, spilled_p
))
3757 /* Process all regs in location *LOC and change them on equivalent
3758 substitution. Return true if any change was done. */
3760 loc_equivalence_change_p (rtx
*loc
)
3762 rtx subst
, reg
, x
= *loc
;
3763 bool result
= false;
3764 enum rtx_code code
= GET_CODE (x
);
3770 reg
= SUBREG_REG (x
);
3771 if ((subst
= get_equiv_with_elimination (reg
, curr_insn
)) != reg
3772 && GET_MODE (subst
) == VOIDmode
)
3774 /* We cannot reload debug location. Simplify subreg here
3775 while we know the inner mode. */
3776 *loc
= simplify_gen_subreg (GET_MODE (x
), subst
,
3777 GET_MODE (reg
), SUBREG_BYTE (x
));
3781 if (code
== REG
&& (subst
= get_equiv_with_elimination (x
, curr_insn
)) != x
)
3787 /* Scan all the operand sub-expressions. */
3788 fmt
= GET_RTX_FORMAT (code
);
3789 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
3792 result
= loc_equivalence_change_p (&XEXP (x
, i
)) || result
;
3793 else if (fmt
[i
] == 'E')
3794 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3796 = loc_equivalence_change_p (&XVECEXP (x
, i
, j
)) || result
;
3801 /* Similar to loc_equivalence_change_p, but for use as
3802 simplify_replace_fn_rtx callback. DATA is insn for which the
3803 elimination is done. If it null we don't do the elimination. */
3805 loc_equivalence_callback (rtx loc
, const_rtx
, void *data
)
3810 rtx subst
= (data
== NULL
3811 ? get_equiv (loc
) : get_equiv_with_elimination (loc
, (rtx
) data
));
3818 /* Maximum number of generated reload insns per an insn. It is for
3819 preventing this pass cycling in a bug case. */
3820 #define MAX_RELOAD_INSNS_NUMBER LRA_MAX_INSN_RELOADS
3822 /* The current iteration number of this LRA pass. */
3823 int lra_constraint_iter
;
3825 /* The current iteration number of this LRA pass after the last spill
3827 int lra_constraint_iter_after_spill
;
3829 /* True if we substituted equiv which needs checking register
3830 allocation correctness because the equivalent value contains
3831 allocatable hard registers or when we restore multi-register
3833 bool lra_risky_transformations_p
;
3835 /* Return true if REGNO is referenced in more than one block. */
3837 multi_block_pseudo_p (int regno
)
3839 basic_block bb
= NULL
;
3843 if (regno
< FIRST_PSEUDO_REGISTER
)
3846 EXECUTE_IF_SET_IN_BITMAP (&lra_reg_info
[regno
].insn_bitmap
, 0, uid
, bi
)
3848 bb
= BLOCK_FOR_INSN (lra_insn_recog_data
[uid
]->insn
);
3849 else if (BLOCK_FOR_INSN (lra_insn_recog_data
[uid
]->insn
) != bb
)
3854 /* Return true if LIST contains a deleted insn. */
3856 contains_deleted_insn_p (rtx list
)
3858 for (; list
!= NULL_RTX
; list
= XEXP (list
, 1))
3859 if (NOTE_P (XEXP (list
, 0))
3860 && NOTE_KIND (XEXP (list
, 0)) == NOTE_INSN_DELETED
)
3865 /* Return true if X contains a pseudo dying in INSN. */
3867 dead_pseudo_p (rtx x
, rtx insn
)
3874 return (insn
!= NULL_RTX
3875 && find_regno_note (insn
, REG_DEAD
, REGNO (x
)) != NULL_RTX
);
3876 code
= GET_CODE (x
);
3877 fmt
= GET_RTX_FORMAT (code
);
3878 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
3882 if (dead_pseudo_p (XEXP (x
, i
), insn
))
3885 else if (fmt
[i
] == 'E')
3887 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3888 if (dead_pseudo_p (XVECEXP (x
, i
, j
), insn
))
3895 /* Return true if INSN contains a dying pseudo in INSN right hand
3898 insn_rhs_dead_pseudo_p (rtx insn
)
3900 rtx set
= single_set (insn
);
3902 gcc_assert (set
!= NULL
);
3903 return dead_pseudo_p (SET_SRC (set
), insn
);
3906 /* Return true if any init insn of REGNO contains a dying pseudo in
3907 insn right hand side. */
3909 init_insn_rhs_dead_pseudo_p (int regno
)
3911 rtx insns
= ira_reg_equiv
[regno
].init_insns
;
3916 return insn_rhs_dead_pseudo_p (insns
);
3917 for (; insns
!= NULL_RTX
; insns
= XEXP (insns
, 1))
3918 if (insn_rhs_dead_pseudo_p (XEXP (insns
, 0)))
3923 /* Return TRUE if REGNO has a reverse equivalence. The equivalence is
3924 reverse only if we have one init insn with given REGNO as a
3927 reverse_equiv_p (int regno
)
3931 if ((insns
= ira_reg_equiv
[regno
].init_insns
) == NULL_RTX
)
3933 if (! INSN_P (XEXP (insns
, 0))
3934 || XEXP (insns
, 1) != NULL_RTX
)
3936 if ((set
= single_set (XEXP (insns
, 0))) == NULL_RTX
)
3938 return REG_P (SET_SRC (set
)) && (int) REGNO (SET_SRC (set
)) == regno
;
3941 /* Return TRUE if REGNO was reloaded in an equivalence init insn. We
3942 call this function only for non-reverse equivalence. */
3944 contains_reloaded_insn_p (int regno
)
3947 rtx list
= ira_reg_equiv
[regno
].init_insns
;
3949 for (; list
!= NULL_RTX
; list
= XEXP (list
, 1))
3950 if ((set
= single_set (XEXP (list
, 0))) == NULL_RTX
3951 || ! REG_P (SET_DEST (set
))
3952 || (int) REGNO (SET_DEST (set
)) != regno
)
3957 /* Entry function of LRA constraint pass. Return true if the
3958 constraint pass did change the code. */
3960 lra_constraints (bool first_p
)
3963 int i
, hard_regno
, new_insns_num
;
3964 unsigned int min_len
, new_min_len
, uid
;
3965 rtx set
, x
, reg
, dest_reg
;
3966 basic_block last_bb
;
3967 bitmap_head equiv_insn_bitmap
;
3970 lra_constraint_iter
++;
3971 if (lra_dump_file
!= NULL
)
3972 fprintf (lra_dump_file
, "\n********** Local #%d: **********\n\n",
3973 lra_constraint_iter
);
3974 lra_constraint_iter_after_spill
++;
3975 if (lra_constraint_iter_after_spill
> LRA_MAX_CONSTRAINT_ITERATION_NUMBER
)
3977 ("Maximum number of LRA constraint passes is achieved (%d)\n",
3978 LRA_MAX_CONSTRAINT_ITERATION_NUMBER
);
3980 lra_risky_transformations_p
= false;
3981 new_insn_uid_start
= get_max_uid ();
3982 new_regno_start
= first_p
? lra_constraint_new_regno_start
: max_reg_num ();
3983 /* Mark used hard regs for target stack size calulations. */
3984 for (i
= FIRST_PSEUDO_REGISTER
; i
< new_regno_start
; i
++)
3985 if (lra_reg_info
[i
].nrefs
!= 0
3986 && (hard_regno
= lra_get_regno_hard_regno (i
)) >= 0)
3990 nregs
= hard_regno_nregs
[hard_regno
][lra_reg_info
[i
].biggest_mode
];
3991 for (j
= 0; j
< nregs
; j
++)
3992 df_set_regs_ever_live (hard_regno
+ j
, true);
3994 /* Do elimination before the equivalence processing as we can spill
3995 some pseudos during elimination. */
3996 lra_eliminate (false, first_p
);
3997 bitmap_initialize (&equiv_insn_bitmap
, ®_obstack
);
3998 for (i
= FIRST_PSEUDO_REGISTER
; i
< new_regno_start
; i
++)
3999 if (lra_reg_info
[i
].nrefs
!= 0)
4001 ira_reg_equiv
[i
].profitable_p
= true;
4002 reg
= regno_reg_rtx
[i
];
4003 if (lra_get_regno_hard_regno (i
) < 0 && (x
= get_equiv (reg
)) != reg
)
4005 bool pseudo_p
= contains_reg_p (x
, false, false);
4007 /* After RTL transformation, we can not guarantee that
4008 pseudo in the substitution was not reloaded which might
4009 make equivalence invalid. For example, in reverse
4016 the memory address register was reloaded before the 2nd
4018 if ((! first_p
&& pseudo_p
)
4019 /* We don't use DF for compilation speed sake. So it
4020 is problematic to update live info when we use an
4021 equivalence containing pseudos in more than one
4023 || (pseudo_p
&& multi_block_pseudo_p (i
))
4024 /* If an init insn was deleted for some reason, cancel
4025 the equiv. We could update the equiv insns after
4026 transformations including an equiv insn deletion
4027 but it is not worthy as such cases are extremely
4029 || contains_deleted_insn_p (ira_reg_equiv
[i
].init_insns
)
4030 /* If it is not a reverse equivalence, we check that a
4031 pseudo in rhs of the init insn is not dying in the
4032 insn. Otherwise, the live info at the beginning of
4033 the corresponding BB might be wrong after we
4034 removed the insn. When the equiv can be a
4035 constant, the right hand side of the init insn can
4037 || (! reverse_equiv_p (i
)
4038 && (init_insn_rhs_dead_pseudo_p (i
)
4039 /* If we reloaded the pseudo in an equivalence
4040 init insn, we can not remove the equiv init
4041 insns and the init insns might write into
4042 const memory in this case. */
4043 || contains_reloaded_insn_p (i
)))
4044 /* Prevent access beyond equivalent memory for
4045 paradoxical subregs. */
4047 && (GET_MODE_SIZE (lra_reg_info
[i
].biggest_mode
)
4048 > GET_MODE_SIZE (GET_MODE (x
)))))
4049 ira_reg_equiv
[i
].defined_p
= false;
4050 if (contains_reg_p (x
, false, true))
4051 ira_reg_equiv
[i
].profitable_p
= false;
4052 if (get_equiv (reg
) != reg
)
4053 bitmap_ior_into (&equiv_insn_bitmap
, &lra_reg_info
[i
].insn_bitmap
);
4056 for (i
= FIRST_PSEUDO_REGISTER
; i
< new_regno_start
; i
++)
4058 /* We should add all insns containing pseudos which should be
4059 substituted by their equivalences. */
4060 EXECUTE_IF_SET_IN_BITMAP (&equiv_insn_bitmap
, 0, uid
, bi
)
4061 lra_push_insn_by_uid (uid
);
4062 min_len
= lra_insn_stack_length ();
4066 while ((new_min_len
= lra_insn_stack_length ()) != 0)
4068 curr_insn
= lra_pop_insn ();
4070 curr_bb
= BLOCK_FOR_INSN (curr_insn
);
4071 if (curr_bb
!= last_bb
)
4074 bb_reload_num
= lra_curr_reload_num
;
4076 if (min_len
> new_min_len
)
4078 min_len
= new_min_len
;
4081 if (new_insns_num
> MAX_RELOAD_INSNS_NUMBER
)
4083 ("Max. number of generated reload insns per insn is achieved (%d)\n",
4084 MAX_RELOAD_INSNS_NUMBER
);
4086 if (DEBUG_INSN_P (curr_insn
))
4088 /* We need to check equivalence in debug insn and change
4089 pseudo to the equivalent value if necessary. */
4090 curr_id
= lra_get_insn_recog_data (curr_insn
);
4091 if (bitmap_bit_p (&equiv_insn_bitmap
, INSN_UID (curr_insn
)))
4093 rtx old
= *curr_id
->operand_loc
[0];
4094 *curr_id
->operand_loc
[0]
4095 = simplify_replace_fn_rtx (old
, NULL_RTX
,
4096 loc_equivalence_callback
, curr_insn
);
4097 if (old
!= *curr_id
->operand_loc
[0])
4099 lra_update_insn_regno_info (curr_insn
);
4104 else if (INSN_P (curr_insn
))
4106 if ((set
= single_set (curr_insn
)) != NULL_RTX
)
4108 dest_reg
= SET_DEST (set
);
4109 /* The equivalence pseudo could be set up as SUBREG in a
4110 case when it is a call restore insn in a mode
4111 different from the pseudo mode. */
4112 if (GET_CODE (dest_reg
) == SUBREG
)
4113 dest_reg
= SUBREG_REG (dest_reg
);
4114 if ((REG_P (dest_reg
)
4115 && (x
= get_equiv (dest_reg
)) != dest_reg
4116 /* Remove insns which set up a pseudo whose value
4117 can not be changed. Such insns might be not in
4118 init_insns because we don't update equiv data
4119 during insn transformations.
4121 As an example, let suppose that a pseudo got
4122 hard register and on the 1st pass was not
4123 changed to equivalent constant. We generate an
4124 additional insn setting up the pseudo because of
4125 secondary memory movement. Then the pseudo is
4126 spilled and we use the equiv constant. In this
4127 case we should remove the additional insn and
4128 this insn is not init_insns list. */
4129 && (! MEM_P (x
) || MEM_READONLY_P (x
)
4130 /* Check that this is actually an insn setting
4131 up the equivalence. */
4132 || in_list_p (curr_insn
,
4134 [REGNO (dest_reg
)].init_insns
)))
4135 || (((x
= get_equiv (SET_SRC (set
))) != SET_SRC (set
))
4136 && in_list_p (curr_insn
,
4138 [REGNO (SET_SRC (set
))].init_insns
)))
4140 /* This is equiv init insn of pseudo which did not get a
4141 hard register -- remove the insn. */
4142 if (lra_dump_file
!= NULL
)
4144 fprintf (lra_dump_file
,
4145 " Removing equiv init insn %i (freq=%d)\n",
4146 INSN_UID (curr_insn
),
4147 REG_FREQ_FROM_BB (BLOCK_FOR_INSN (curr_insn
)));
4148 dump_insn_slim (lra_dump_file
, curr_insn
);
4150 if (contains_reg_p (x
, true, false))
4151 lra_risky_transformations_p
= true;
4152 lra_set_insn_deleted (curr_insn
);
4156 curr_id
= lra_get_insn_recog_data (curr_insn
);
4157 curr_static_id
= curr_id
->insn_static_data
;
4158 init_curr_insn_input_reloads ();
4159 init_curr_operand_mode ();
4160 if (curr_insn_transform ())
4162 /* Check non-transformed insns too for equiv change as USE
4163 or CLOBBER don't need reloads but can contain pseudos
4164 being changed on their equivalences. */
4165 else if (bitmap_bit_p (&equiv_insn_bitmap
, INSN_UID (curr_insn
))
4166 && loc_equivalence_change_p (&PATTERN (curr_insn
)))
4168 lra_update_insn_regno_info (curr_insn
);
4173 bitmap_clear (&equiv_insn_bitmap
);
4174 /* If we used a new hard regno, changed_p should be true because the
4175 hard reg is assigned to a new pseudo. */
4176 #ifdef ENABLE_CHECKING
4179 for (i
= FIRST_PSEUDO_REGISTER
; i
< new_regno_start
; i
++)
4180 if (lra_reg_info
[i
].nrefs
!= 0
4181 && (hard_regno
= lra_get_regno_hard_regno (i
)) >= 0)
4183 int j
, nregs
= hard_regno_nregs
[hard_regno
][PSEUDO_REGNO_MODE (i
)];
4185 for (j
= 0; j
< nregs
; j
++)
4186 lra_assert (df_regs_ever_live_p (hard_regno
+ j
));
4193 /* Initiate the LRA constraint pass. It is done once per
4196 lra_constraints_init (void)
4200 /* Finalize the LRA constraint pass. It is done once per
4203 lra_constraints_finish (void)
4209 /* This page contains code to do inheritance/split
4212 /* Number of reloads passed so far in current EBB. */
4213 static int reloads_num
;
4215 /* Number of calls passed so far in current EBB. */
4216 static int calls_num
;
4218 /* Current reload pseudo check for validity of elements in
4220 static int curr_usage_insns_check
;
4222 /* Info about last usage of registers in EBB to do inheritance/split
4223 transformation. Inheritance transformation is done from a spilled
4224 pseudo and split transformations from a hard register or a pseudo
4225 assigned to a hard register. */
4228 /* If the value is equal to CURR_USAGE_INSNS_CHECK, then the member
4229 value INSNS is valid. The insns is chain of optional debug insns
4230 and a finishing non-debug insn using the corresponding reg. The
4231 value is also used to mark the registers which are set up in the
4232 current insn. The negated insn uid is used for this. */
4234 /* Value of global reloads_num at the last insn in INSNS. */
4236 /* Value of global reloads_nums at the last insn in INSNS. */
4238 /* It can be true only for splitting. And it means that the restore
4239 insn should be put after insn given by the following member. */
4241 /* Next insns in the current EBB which use the original reg and the
4242 original reg value is not changed between the current insn and
4243 the next insns. In order words, e.g. for inheritance, if we need
4244 to use the original reg value again in the next insns we can try
4245 to use the value in a hard register from a reload insn of the
4250 /* Map: regno -> corresponding pseudo usage insns. */
4251 static struct usage_insns
*usage_insns
;
4254 setup_next_usage_insn (int regno
, rtx insn
, int reloads_num
, bool after_p
)
4256 usage_insns
[regno
].check
= curr_usage_insns_check
;
4257 usage_insns
[regno
].insns
= insn
;
4258 usage_insns
[regno
].reloads_num
= reloads_num
;
4259 usage_insns
[regno
].calls_num
= calls_num
;
4260 usage_insns
[regno
].after_p
= after_p
;
4263 /* The function is used to form list REGNO usages which consists of
4264 optional debug insns finished by a non-debug insn using REGNO.
4265 RELOADS_NUM is current number of reload insns processed so far. */
4267 add_next_usage_insn (int regno
, rtx insn
, int reloads_num
)
4269 rtx next_usage_insns
;
4271 if (usage_insns
[regno
].check
== curr_usage_insns_check
4272 && (next_usage_insns
= usage_insns
[regno
].insns
) != NULL_RTX
4273 && DEBUG_INSN_P (insn
))
4275 /* Check that we did not add the debug insn yet. */
4276 if (next_usage_insns
!= insn
4277 && (GET_CODE (next_usage_insns
) != INSN_LIST
4278 || XEXP (next_usage_insns
, 0) != insn
))
4279 usage_insns
[regno
].insns
= gen_rtx_INSN_LIST (VOIDmode
, insn
,
4282 else if (NONDEBUG_INSN_P (insn
))
4283 setup_next_usage_insn (regno
, insn
, reloads_num
, false);
4285 usage_insns
[regno
].check
= 0;
4288 /* Replace all references to register OLD_REGNO in *LOC with pseudo
4289 register NEW_REG. Return true if any change was made. */
4291 substitute_pseudo (rtx
*loc
, int old_regno
, rtx new_reg
)
4294 bool result
= false;
4302 code
= GET_CODE (x
);
4303 if (code
== REG
&& (int) REGNO (x
) == old_regno
)
4305 enum machine_mode mode
= GET_MODE (*loc
);
4306 enum machine_mode inner_mode
= GET_MODE (new_reg
);
4308 if (mode
!= inner_mode
)
4310 if (GET_MODE_SIZE (mode
) >= GET_MODE_SIZE (inner_mode
)
4311 || ! SCALAR_INT_MODE_P (inner_mode
))
4312 new_reg
= gen_rtx_SUBREG (mode
, new_reg
, 0);
4314 new_reg
= gen_lowpart_SUBREG (mode
, new_reg
);
4320 /* Scan all the operand sub-expressions. */
4321 fmt
= GET_RTX_FORMAT (code
);
4322 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
4326 if (substitute_pseudo (&XEXP (x
, i
), old_regno
, new_reg
))
4329 else if (fmt
[i
] == 'E')
4331 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
4332 if (substitute_pseudo (&XVECEXP (x
, i
, j
), old_regno
, new_reg
))
4339 /* Return first non-debug insn in list USAGE_INSNS. */
4341 skip_usage_debug_insns (rtx usage_insns
)
4345 /* Skip debug insns. */
4346 for (insn
= usage_insns
;
4347 insn
!= NULL_RTX
&& GET_CODE (insn
) == INSN_LIST
;
4348 insn
= XEXP (insn
, 1))
4353 /* Return true if we need secondary memory moves for insn in
4354 USAGE_INSNS after inserting inherited pseudo of class INHER_CL
4357 check_secondary_memory_needed_p (enum reg_class inher_cl ATTRIBUTE_UNUSED
,
4358 rtx usage_insns ATTRIBUTE_UNUSED
)
4360 #ifndef SECONDARY_MEMORY_NEEDED
4363 rtx insn
, set
, dest
;
4366 if (inher_cl
== ALL_REGS
4367 || (insn
= skip_usage_debug_insns (usage_insns
)) == NULL_RTX
)
4369 lra_assert (INSN_P (insn
));
4370 if ((set
= single_set (insn
)) == NULL_RTX
|| ! REG_P (SET_DEST (set
)))
4372 dest
= SET_DEST (set
);
4375 lra_assert (inher_cl
!= NO_REGS
);
4376 cl
= get_reg_class (REGNO (dest
));
4377 return (cl
!= NO_REGS
&& cl
!= ALL_REGS
4378 && SECONDARY_MEMORY_NEEDED (inher_cl
, cl
, GET_MODE (dest
)));
4382 /* Registers involved in inheritance/split in the current EBB
4383 (inheritance/split pseudos and original registers). */
4384 static bitmap_head check_only_regs
;
4386 /* Do inheritance transformations for insn INSN, which defines (if
4387 DEF_P) or uses ORIGINAL_REGNO. NEXT_USAGE_INSNS specifies which
4388 instruction in the EBB next uses ORIGINAL_REGNO; it has the same
4389 form as the "insns" field of usage_insns. Return true if we
4390 succeed in such transformation.
4392 The transformations look like:
4395 ... p <- i (new insn)
4397 <- ... p ... <- ... i ...
4399 ... i <- p (new insn)
4400 <- ... p ... <- ... i ...
4402 <- ... p ... <- ... i ...
4403 where p is a spilled original pseudo and i is a new inheritance pseudo.
4406 The inheritance pseudo has the smallest class of two classes CL and
4407 class of ORIGINAL REGNO. */
4409 inherit_reload_reg (bool def_p
, int original_regno
,
4410 enum reg_class cl
, rtx insn
, rtx next_usage_insns
)
4412 if (optimize_function_for_size_p (cfun
))
4415 enum reg_class rclass
= lra_get_allocno_class (original_regno
);
4416 rtx original_reg
= regno_reg_rtx
[original_regno
];
4417 rtx new_reg
, new_insns
, usage_insn
;
4419 lra_assert (! usage_insns
[original_regno
].after_p
);
4420 if (lra_dump_file
!= NULL
)
4421 fprintf (lra_dump_file
,
4422 " <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<\n");
4423 if (! ira_reg_classes_intersect_p
[cl
][rclass
])
4425 if (lra_dump_file
!= NULL
)
4427 fprintf (lra_dump_file
,
4428 " Rejecting inheritance for %d "
4429 "because of disjoint classes %s and %s\n",
4430 original_regno
, reg_class_names
[cl
],
4431 reg_class_names
[rclass
]);
4432 fprintf (lra_dump_file
,
4433 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
4437 if ((ira_class_subset_p
[cl
][rclass
] && cl
!= rclass
)
4438 /* We don't use a subset of two classes because it can be
4439 NO_REGS. This transformation is still profitable in most
4440 cases even if the classes are not intersected as register
4441 move is probably cheaper than a memory load. */
4442 || ira_class_hard_regs_num
[cl
] < ira_class_hard_regs_num
[rclass
])
4444 if (lra_dump_file
!= NULL
)
4445 fprintf (lra_dump_file
, " Use smallest class of %s and %s\n",
4446 reg_class_names
[cl
], reg_class_names
[rclass
]);
4450 if (check_secondary_memory_needed_p (rclass
, next_usage_insns
))
4452 /* Reject inheritance resulting in secondary memory moves.
4453 Otherwise, there is a danger in LRA cycling. Also such
4454 transformation will be unprofitable. */
4455 if (lra_dump_file
!= NULL
)
4457 rtx insn
= skip_usage_debug_insns (next_usage_insns
);
4458 rtx set
= single_set (insn
);
4460 lra_assert (set
!= NULL_RTX
);
4462 rtx dest
= SET_DEST (set
);
4464 lra_assert (REG_P (dest
));
4465 fprintf (lra_dump_file
,
4466 " Rejecting inheritance for insn %d(%s)<-%d(%s) "
4467 "as secondary mem is needed\n",
4468 REGNO (dest
), reg_class_names
[get_reg_class (REGNO (dest
))],
4469 original_regno
, reg_class_names
[rclass
]);
4470 fprintf (lra_dump_file
,
4471 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
4475 new_reg
= lra_create_new_reg (GET_MODE (original_reg
), original_reg
,
4476 rclass
, "inheritance");
4479 lra_emit_move (original_reg
, new_reg
);
4481 lra_emit_move (new_reg
, original_reg
);
4482 new_insns
= get_insns ();
4484 if (NEXT_INSN (new_insns
) != NULL_RTX
)
4486 if (lra_dump_file
!= NULL
)
4488 fprintf (lra_dump_file
,
4489 " Rejecting inheritance %d->%d "
4490 "as it results in 2 or more insns:\n",
4491 original_regno
, REGNO (new_reg
));
4492 dump_rtl_slim (lra_dump_file
, new_insns
, NULL_RTX
, -1, 0);
4493 fprintf (lra_dump_file
,
4494 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
4498 substitute_pseudo (&insn
, original_regno
, new_reg
);
4499 lra_update_insn_regno_info (insn
);
4501 /* We now have a new usage insn for original regno. */
4502 setup_next_usage_insn (original_regno
, new_insns
, reloads_num
, false);
4503 if (lra_dump_file
!= NULL
)
4504 fprintf (lra_dump_file
, " Original reg change %d->%d (bb%d):\n",
4505 original_regno
, REGNO (new_reg
), BLOCK_FOR_INSN (insn
)->index
);
4506 lra_reg_info
[REGNO (new_reg
)].restore_regno
= original_regno
;
4507 bitmap_set_bit (&check_only_regs
, REGNO (new_reg
));
4508 bitmap_set_bit (&check_only_regs
, original_regno
);
4509 bitmap_set_bit (&lra_inheritance_pseudos
, REGNO (new_reg
));
4511 lra_process_new_insns (insn
, NULL_RTX
, new_insns
,
4512 "Add original<-inheritance");
4514 lra_process_new_insns (insn
, new_insns
, NULL_RTX
,
4515 "Add inheritance<-original");
4516 while (next_usage_insns
!= NULL_RTX
)
4518 if (GET_CODE (next_usage_insns
) != INSN_LIST
)
4520 usage_insn
= next_usage_insns
;
4521 lra_assert (NONDEBUG_INSN_P (usage_insn
));
4522 next_usage_insns
= NULL
;
4526 usage_insn
= XEXP (next_usage_insns
, 0);
4527 lra_assert (DEBUG_INSN_P (usage_insn
));
4528 next_usage_insns
= XEXP (next_usage_insns
, 1);
4530 substitute_pseudo (&usage_insn
, original_regno
, new_reg
);
4531 lra_update_insn_regno_info (usage_insn
);
4532 if (lra_dump_file
!= NULL
)
4534 fprintf (lra_dump_file
,
4535 " Inheritance reuse change %d->%d (bb%d):\n",
4536 original_regno
, REGNO (new_reg
),
4537 BLOCK_FOR_INSN (usage_insn
)->index
);
4538 dump_insn_slim (lra_dump_file
, usage_insn
);
4541 if (lra_dump_file
!= NULL
)
4542 fprintf (lra_dump_file
,
4543 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
4547 /* Return true if we need a caller save/restore for pseudo REGNO which
4548 was assigned to a hard register. */
4550 need_for_call_save_p (int regno
)
4552 lra_assert (regno
>= FIRST_PSEUDO_REGISTER
&& reg_renumber
[regno
] >= 0);
4553 return (usage_insns
[regno
].calls_num
< calls_num
4554 && (overlaps_hard_reg_set_p
4555 ((flag_use_caller_save
&&
4556 ! hard_reg_set_empty_p (lra_reg_info
[regno
].actual_call_used_reg_set
))
4557 ? lra_reg_info
[regno
].actual_call_used_reg_set
4558 : call_used_reg_set
,
4559 PSEUDO_REGNO_MODE (regno
), reg_renumber
[regno
])
4560 || HARD_REGNO_CALL_PART_CLOBBERED (reg_renumber
[regno
],
4561 PSEUDO_REGNO_MODE (regno
))));
4564 /* Global registers occurring in the current EBB. */
4565 static bitmap_head ebb_global_regs
;
4567 /* Return true if we need a split for hard register REGNO or pseudo
4568 REGNO which was assigned to a hard register.
4569 POTENTIAL_RELOAD_HARD_REGS contains hard registers which might be
4570 used for reloads since the EBB end. It is an approximation of the
4571 used hard registers in the split range. The exact value would
4572 require expensive calculations. If we were aggressive with
4573 splitting because of the approximation, the split pseudo will save
4574 the same hard register assignment and will be removed in the undo
4575 pass. We still need the approximation because too aggressive
4576 splitting would result in too inaccurate cost calculation in the
4577 assignment pass because of too many generated moves which will be
4578 probably removed in the undo pass. */
4580 need_for_split_p (HARD_REG_SET potential_reload_hard_regs
, int regno
)
4582 int hard_regno
= regno
< FIRST_PSEUDO_REGISTER
? regno
: reg_renumber
[regno
];
4584 lra_assert (hard_regno
>= 0);
4585 return ((TEST_HARD_REG_BIT (potential_reload_hard_regs
, hard_regno
)
4586 /* Don't split eliminable hard registers, otherwise we can
4587 split hard registers like hard frame pointer, which
4588 lives on BB start/end according to DF-infrastructure,
4589 when there is a pseudo assigned to the register and
4590 living in the same BB. */
4591 && (regno
>= FIRST_PSEUDO_REGISTER
4592 || ! TEST_HARD_REG_BIT (eliminable_regset
, hard_regno
))
4593 && ! TEST_HARD_REG_BIT (lra_no_alloc_regs
, hard_regno
)
4594 /* Don't split call clobbered hard regs living through
4595 calls, otherwise we might have a check problem in the
4596 assign sub-pass as in the most cases (exception is a
4597 situation when lra_risky_transformations_p value is
4598 true) the assign pass assumes that all pseudos living
4599 through calls are assigned to call saved hard regs. */
4600 && (regno
>= FIRST_PSEUDO_REGISTER
4601 || ! TEST_HARD_REG_BIT (call_used_reg_set
, regno
)
4602 || usage_insns
[regno
].calls_num
== calls_num
)
4603 /* We need at least 2 reloads to make pseudo splitting
4604 profitable. We should provide hard regno splitting in
4605 any case to solve 1st insn scheduling problem when
4606 moving hard register definition up might result in
4607 impossibility to find hard register for reload pseudo of
4608 small register class. */
4609 && (usage_insns
[regno
].reloads_num
4610 + (regno
< FIRST_PSEUDO_REGISTER
? 0 : 3) < reloads_num
)
4611 && (regno
< FIRST_PSEUDO_REGISTER
4612 /* For short living pseudos, spilling + inheritance can
4613 be considered a substitution for splitting.
4614 Therefore we do not splitting for local pseudos. It
4615 decreases also aggressiveness of splitting. The
4616 minimal number of references is chosen taking into
4617 account that for 2 references splitting has no sense
4618 as we can just spill the pseudo. */
4619 || (regno
>= FIRST_PSEUDO_REGISTER
4620 && lra_reg_info
[regno
].nrefs
> 3
4621 && bitmap_bit_p (&ebb_global_regs
, regno
))))
4622 || (regno
>= FIRST_PSEUDO_REGISTER
&& need_for_call_save_p (regno
)));
4625 /* Return class for the split pseudo created from original pseudo with
4626 ALLOCNO_CLASS and MODE which got a hard register HARD_REGNO. We
4627 choose subclass of ALLOCNO_CLASS which contains HARD_REGNO and
4628 results in no secondary memory movements. */
4629 static enum reg_class
4630 choose_split_class (enum reg_class allocno_class
,
4631 int hard_regno ATTRIBUTE_UNUSED
,
4632 enum machine_mode mode ATTRIBUTE_UNUSED
)
4634 #ifndef SECONDARY_MEMORY_NEEDED
4635 return allocno_class
;
4638 enum reg_class cl
, best_cl
= NO_REGS
;
4639 enum reg_class hard_reg_class ATTRIBUTE_UNUSED
4640 = REGNO_REG_CLASS (hard_regno
);
4642 if (! SECONDARY_MEMORY_NEEDED (allocno_class
, allocno_class
, mode
)
4643 && TEST_HARD_REG_BIT (reg_class_contents
[allocno_class
], hard_regno
))
4644 return allocno_class
;
4646 (cl
= reg_class_subclasses
[allocno_class
][i
]) != LIM_REG_CLASSES
;
4648 if (! SECONDARY_MEMORY_NEEDED (cl
, hard_reg_class
, mode
)
4649 && ! SECONDARY_MEMORY_NEEDED (hard_reg_class
, cl
, mode
)
4650 && TEST_HARD_REG_BIT (reg_class_contents
[cl
], hard_regno
)
4651 && (best_cl
== NO_REGS
4652 || ira_class_hard_regs_num
[best_cl
] < ira_class_hard_regs_num
[cl
]))
4658 /* Do split transformations for insn INSN, which defines or uses
4659 ORIGINAL_REGNO. NEXT_USAGE_INSNS specifies which instruction in
4660 the EBB next uses ORIGINAL_REGNO; it has the same form as the
4661 "insns" field of usage_insns.
4663 The transformations look like:
4666 ... s <- p (new insn -- save)
4668 ... p <- s (new insn -- restore)
4669 <- ... p ... <- ... p ...
4671 <- ... p ... <- ... p ...
4672 ... s <- p (new insn -- save)
4674 ... p <- s (new insn -- restore)
4675 <- ... p ... <- ... p ...
4677 where p is an original pseudo got a hard register or a hard
4678 register and s is a new split pseudo. The save is put before INSN
4679 if BEFORE_P is true. Return true if we succeed in such
4682 split_reg (bool before_p
, int original_regno
, rtx insn
, rtx next_usage_insns
)
4684 enum reg_class rclass
;
4686 int hard_regno
, nregs
;
4687 rtx new_reg
, save
, restore
, usage_insn
;
4691 if (original_regno
< FIRST_PSEUDO_REGISTER
)
4693 rclass
= ira_allocno_class_translate
[REGNO_REG_CLASS (original_regno
)];
4694 hard_regno
= original_regno
;
4695 call_save_p
= false;
4700 hard_regno
= reg_renumber
[original_regno
];
4701 nregs
= hard_regno_nregs
[hard_regno
][PSEUDO_REGNO_MODE (original_regno
)];
4702 rclass
= lra_get_allocno_class (original_regno
);
4703 original_reg
= regno_reg_rtx
[original_regno
];
4704 call_save_p
= need_for_call_save_p (original_regno
);
4706 original_reg
= regno_reg_rtx
[original_regno
];
4707 lra_assert (hard_regno
>= 0);
4708 if (lra_dump_file
!= NULL
)
4709 fprintf (lra_dump_file
,
4710 " ((((((((((((((((((((((((((((((((((((((((((((((((\n");
4713 enum machine_mode mode
= GET_MODE (original_reg
);
4715 mode
= HARD_REGNO_CALLER_SAVE_MODE (hard_regno
,
4716 hard_regno_nregs
[hard_regno
][mode
],
4718 new_reg
= lra_create_new_reg (mode
, NULL_RTX
, NO_REGS
, "save");
4722 rclass
= choose_split_class (rclass
, hard_regno
,
4723 GET_MODE (original_reg
));
4724 if (rclass
== NO_REGS
)
4726 if (lra_dump_file
!= NULL
)
4728 fprintf (lra_dump_file
,
4729 " Rejecting split of %d(%s): "
4730 "no good reg class for %d(%s)\n",
4732 reg_class_names
[lra_get_allocno_class (original_regno
)],
4734 reg_class_names
[REGNO_REG_CLASS (hard_regno
)]);
4737 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
4741 new_reg
= lra_create_new_reg (GET_MODE (original_reg
), original_reg
,
4743 reg_renumber
[REGNO (new_reg
)] = hard_regno
;
4745 save
= emit_spill_move (true, new_reg
, original_reg
);
4746 if (NEXT_INSN (save
) != NULL_RTX
)
4748 lra_assert (! call_save_p
);
4749 if (lra_dump_file
!= NULL
)
4753 " Rejecting split %d->%d resulting in > 2 %s save insns:\n",
4754 original_regno
, REGNO (new_reg
), call_save_p
? "call" : "");
4755 dump_rtl_slim (lra_dump_file
, save
, NULL_RTX
, -1, 0);
4756 fprintf (lra_dump_file
,
4757 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
4761 restore
= emit_spill_move (false, new_reg
, original_reg
);
4762 if (NEXT_INSN (restore
) != NULL_RTX
)
4764 lra_assert (! call_save_p
);
4765 if (lra_dump_file
!= NULL
)
4767 fprintf (lra_dump_file
,
4768 " Rejecting split %d->%d "
4769 "resulting in > 2 %s restore insns:\n",
4770 original_regno
, REGNO (new_reg
), call_save_p
? "call" : "");
4771 dump_rtl_slim (lra_dump_file
, restore
, NULL_RTX
, -1, 0);
4772 fprintf (lra_dump_file
,
4773 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
4777 after_p
= usage_insns
[original_regno
].after_p
;
4778 lra_reg_info
[REGNO (new_reg
)].restore_regno
= original_regno
;
4779 bitmap_set_bit (&check_only_regs
, REGNO (new_reg
));
4780 bitmap_set_bit (&check_only_regs
, original_regno
);
4781 bitmap_set_bit (&lra_split_regs
, REGNO (new_reg
));
4784 if (GET_CODE (next_usage_insns
) != INSN_LIST
)
4786 usage_insn
= next_usage_insns
;
4789 usage_insn
= XEXP (next_usage_insns
, 0);
4790 lra_assert (DEBUG_INSN_P (usage_insn
));
4791 next_usage_insns
= XEXP (next_usage_insns
, 1);
4792 substitute_pseudo (&usage_insn
, original_regno
, new_reg
);
4793 lra_update_insn_regno_info (usage_insn
);
4794 if (lra_dump_file
!= NULL
)
4796 fprintf (lra_dump_file
, " Split reuse change %d->%d:\n",
4797 original_regno
, REGNO (new_reg
));
4798 dump_insn_slim (lra_dump_file
, usage_insn
);
4801 lra_assert (NOTE_P (usage_insn
) || NONDEBUG_INSN_P (usage_insn
));
4802 lra_assert (usage_insn
!= insn
|| (after_p
&& before_p
));
4803 lra_process_new_insns (usage_insn
, after_p
? NULL_RTX
: restore
,
4804 after_p
? restore
: NULL_RTX
,
4806 ? "Add reg<-save" : "Add reg<-split");
4807 lra_process_new_insns (insn
, before_p
? save
: NULL_RTX
,
4808 before_p
? NULL_RTX
: save
,
4810 ? "Add save<-reg" : "Add split<-reg");
4812 /* If we are trying to split multi-register. We should check
4813 conflicts on the next assignment sub-pass. IRA can allocate on
4814 sub-register levels, LRA do this on pseudos level right now and
4815 this discrepancy may create allocation conflicts after
4817 lra_risky_transformations_p
= true;
4818 if (lra_dump_file
!= NULL
)
4819 fprintf (lra_dump_file
,
4820 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
4824 /* Recognize that we need a split transformation for insn INSN, which
4825 defines or uses REGNO in its insn biggest MODE (we use it only if
4826 REGNO is a hard register). POTENTIAL_RELOAD_HARD_REGS contains
4827 hard registers which might be used for reloads since the EBB end.
4828 Put the save before INSN if BEFORE_P is true. MAX_UID is maximla
4829 uid before starting INSN processing. Return true if we succeed in
4830 such transformation. */
4832 split_if_necessary (int regno
, enum machine_mode mode
,
4833 HARD_REG_SET potential_reload_hard_regs
,
4834 bool before_p
, rtx insn
, int max_uid
)
4838 rtx next_usage_insns
;
4840 if (regno
< FIRST_PSEUDO_REGISTER
)
4841 nregs
= hard_regno_nregs
[regno
][mode
];
4842 for (i
= 0; i
< nregs
; i
++)
4843 if (usage_insns
[regno
+ i
].check
== curr_usage_insns_check
4844 && (next_usage_insns
= usage_insns
[regno
+ i
].insns
) != NULL_RTX
4845 /* To avoid processing the register twice or more. */
4846 && ((GET_CODE (next_usage_insns
) != INSN_LIST
4847 && INSN_UID (next_usage_insns
) < max_uid
)
4848 || (GET_CODE (next_usage_insns
) == INSN_LIST
4849 && (INSN_UID (XEXP (next_usage_insns
, 0)) < max_uid
)))
4850 && need_for_split_p (potential_reload_hard_regs
, regno
+ i
)
4851 && split_reg (before_p
, regno
+ i
, insn
, next_usage_insns
))
4856 /* Check only registers living at the current program point in the
4858 static bitmap_head live_regs
;
4860 /* Update live info in EBB given by its HEAD and TAIL insns after
4861 inheritance/split transformation. The function removes dead moves
4864 update_ebb_live_info (rtx head
, rtx tail
)
4871 basic_block last_bb
, prev_bb
, curr_bb
;
4873 struct lra_insn_reg
*reg
;
4877 last_bb
= BLOCK_FOR_INSN (tail
);
4879 for (curr_insn
= tail
;
4880 curr_insn
!= PREV_INSN (head
);
4881 curr_insn
= prev_insn
)
4883 prev_insn
= PREV_INSN (curr_insn
);
4884 /* We need to process empty blocks too. They contain
4885 NOTE_INSN_BASIC_BLOCK referring for the basic block. */
4886 if (NOTE_P (curr_insn
) && NOTE_KIND (curr_insn
) != NOTE_INSN_BASIC_BLOCK
)
4888 curr_bb
= BLOCK_FOR_INSN (curr_insn
);
4889 if (curr_bb
!= prev_bb
)
4891 if (prev_bb
!= NULL
)
4893 /* Update df_get_live_in (prev_bb): */
4894 EXECUTE_IF_SET_IN_BITMAP (&check_only_regs
, 0, j
, bi
)
4895 if (bitmap_bit_p (&live_regs
, j
))
4896 bitmap_set_bit (df_get_live_in (prev_bb
), j
);
4898 bitmap_clear_bit (df_get_live_in (prev_bb
), j
);
4900 if (curr_bb
!= last_bb
)
4902 /* Update df_get_live_out (curr_bb): */
4903 EXECUTE_IF_SET_IN_BITMAP (&check_only_regs
, 0, j
, bi
)
4905 live_p
= bitmap_bit_p (&live_regs
, j
);
4907 FOR_EACH_EDGE (e
, ei
, curr_bb
->succs
)
4908 if (bitmap_bit_p (df_get_live_in (e
->dest
), j
))
4914 bitmap_set_bit (df_get_live_out (curr_bb
), j
);
4916 bitmap_clear_bit (df_get_live_out (curr_bb
), j
);
4920 bitmap_and (&live_regs
, &check_only_regs
, df_get_live_out (curr_bb
));
4922 if (! NONDEBUG_INSN_P (curr_insn
))
4924 curr_id
= lra_get_insn_recog_data (curr_insn
);
4925 curr_static_id
= curr_id
->insn_static_data
;
4927 if ((set
= single_set (curr_insn
)) != NULL_RTX
&& REG_P (SET_DEST (set
))
4928 && (regno
= REGNO (SET_DEST (set
))) >= FIRST_PSEUDO_REGISTER
4929 && bitmap_bit_p (&check_only_regs
, regno
)
4930 && ! bitmap_bit_p (&live_regs
, regno
))
4932 /* See which defined values die here. */
4933 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
4934 if (reg
->type
== OP_OUT
&& ! reg
->subreg_p
)
4935 bitmap_clear_bit (&live_regs
, reg
->regno
);
4936 for (reg
= curr_static_id
->hard_regs
; reg
!= NULL
; reg
= reg
->next
)
4937 if (reg
->type
== OP_OUT
&& ! reg
->subreg_p
)
4938 bitmap_clear_bit (&live_regs
, reg
->regno
);
4939 /* Mark each used value as live. */
4940 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
4941 if (reg
->type
!= OP_OUT
4942 && bitmap_bit_p (&check_only_regs
, reg
->regno
))
4943 bitmap_set_bit (&live_regs
, reg
->regno
);
4944 for (reg
= curr_static_id
->hard_regs
; reg
!= NULL
; reg
= reg
->next
)
4945 if (reg
->type
!= OP_OUT
4946 && bitmap_bit_p (&check_only_regs
, reg
->regno
))
4947 bitmap_set_bit (&live_regs
, reg
->regno
);
4948 if (curr_id
->arg_hard_regs
!= NULL
)
4949 /* Make argument hard registers live. */
4950 for (i
= 0; (regno
= curr_id
->arg_hard_regs
[i
]) >= 0; i
++)
4951 if (bitmap_bit_p (&check_only_regs
, regno
))
4952 bitmap_set_bit (&live_regs
, regno
);
4953 /* It is quite important to remove dead move insns because it
4954 means removing dead store. We don't need to process them for
4958 if (lra_dump_file
!= NULL
)
4960 fprintf (lra_dump_file
, " Removing dead insn:\n ");
4961 dump_insn_slim (lra_dump_file
, curr_insn
);
4963 lra_set_insn_deleted (curr_insn
);
4968 /* The structure describes info to do an inheritance for the current
4969 insn. We need to collect such info first before doing the
4970 transformations because the transformations change the insn
4971 internal representation. */
4974 /* Original regno. */
4976 /* Subsequent insns which can inherit original reg value. */
4980 /* Array containing all info for doing inheritance from the current
4982 static struct to_inherit to_inherit
[LRA_MAX_INSN_RELOADS
];
4984 /* Number elements in the previous array. */
4985 static int to_inherit_num
;
4987 /* Add inheritance info REGNO and INSNS. Their meaning is described in
4988 structure to_inherit. */
4990 add_to_inherit (int regno
, rtx insns
)
4994 for (i
= 0; i
< to_inherit_num
; i
++)
4995 if (to_inherit
[i
].regno
== regno
)
4997 lra_assert (to_inherit_num
< LRA_MAX_INSN_RELOADS
);
4998 to_inherit
[to_inherit_num
].regno
= regno
;
4999 to_inherit
[to_inherit_num
++].insns
= insns
;
5002 /* Return the last non-debug insn in basic block BB, or the block begin
5005 get_last_insertion_point (basic_block bb
)
5009 FOR_BB_INSNS_REVERSE (bb
, insn
)
5010 if (NONDEBUG_INSN_P (insn
) || NOTE_INSN_BASIC_BLOCK_P (insn
))
5015 /* Set up RES by registers living on edges FROM except the edge (FROM,
5016 TO) or by registers set up in a jump insn in BB FROM. */
5018 get_live_on_other_edges (basic_block from
, basic_block to
, bitmap res
)
5021 struct lra_insn_reg
*reg
;
5025 lra_assert (to
!= NULL
);
5027 FOR_EACH_EDGE (e
, ei
, from
->succs
)
5029 bitmap_ior_into (res
, df_get_live_in (e
->dest
));
5030 last
= get_last_insertion_point (from
);
5031 if (! JUMP_P (last
))
5033 curr_id
= lra_get_insn_recog_data (last
);
5034 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
5035 if (reg
->type
!= OP_IN
)
5036 bitmap_set_bit (res
, reg
->regno
);
5039 /* Used as a temporary results of some bitmap calculations. */
5040 static bitmap_head temp_bitmap
;
5042 /* We split for reloads of small class of hard regs. The following
5043 defines how many hard regs the class should have to be qualified as
5044 small. The code is mostly oriented to x86/x86-64 architecture
5045 where some insns need to use only specific register or pair of
5046 registers and these register can live in RTL explicitly, e.g. for
5047 parameter passing. */
5048 static const int max_small_class_regs_num
= 2;
5050 /* Do inheritance/split transformations in EBB starting with HEAD and
5051 finishing on TAIL. We process EBB insns in the reverse order.
5052 Return true if we did any inheritance/split transformation in the
5055 We should avoid excessive splitting which results in worse code
5056 because of inaccurate cost calculations for spilling new split
5057 pseudos in such case. To achieve this we do splitting only if
5058 register pressure is high in given basic block and there are reload
5059 pseudos requiring hard registers. We could do more register
5060 pressure calculations at any given program point to avoid necessary
5061 splitting even more but it is to expensive and the current approach
5062 works well enough. */
5064 inherit_in_ebb (rtx head
, rtx tail
)
5066 int i
, src_regno
, dst_regno
, nregs
;
5067 bool change_p
, succ_p
, update_reloads_num_p
;
5068 rtx prev_insn
, next_usage_insns
, set
, last_insn
;
5070 struct lra_insn_reg
*reg
;
5071 basic_block last_processed_bb
, curr_bb
= NULL
;
5072 HARD_REG_SET potential_reload_hard_regs
, live_hard_regs
;
5076 bool head_p
, after_p
;
5079 curr_usage_insns_check
++;
5080 reloads_num
= calls_num
= 0;
5081 bitmap_clear (&check_only_regs
);
5082 last_processed_bb
= NULL
;
5083 CLEAR_HARD_REG_SET (potential_reload_hard_regs
);
5084 COPY_HARD_REG_SET (live_hard_regs
, eliminable_regset
);
5085 IOR_HARD_REG_SET (live_hard_regs
, lra_no_alloc_regs
);
5086 /* We don't process new insns generated in the loop. */
5087 for (curr_insn
= tail
; curr_insn
!= PREV_INSN (head
); curr_insn
= prev_insn
)
5089 prev_insn
= PREV_INSN (curr_insn
);
5090 if (BLOCK_FOR_INSN (curr_insn
) != NULL
)
5091 curr_bb
= BLOCK_FOR_INSN (curr_insn
);
5092 if (last_processed_bb
!= curr_bb
)
5094 /* We are at the end of BB. Add qualified living
5095 pseudos for potential splitting. */
5096 to_process
= df_get_live_out (curr_bb
);
5097 if (last_processed_bb
!= NULL
)
5099 /* We are somewhere in the middle of EBB. */
5100 get_live_on_other_edges (curr_bb
, last_processed_bb
,
5102 to_process
= &temp_bitmap
;
5104 last_processed_bb
= curr_bb
;
5105 last_insn
= get_last_insertion_point (curr_bb
);
5106 after_p
= (! JUMP_P (last_insn
)
5107 && (! CALL_P (last_insn
)
5108 || (find_reg_note (last_insn
,
5109 REG_NORETURN
, NULL_RTX
) == NULL_RTX
5110 && ! SIBLING_CALL_P (last_insn
))));
5111 CLEAR_HARD_REG_SET (potential_reload_hard_regs
);
5112 EXECUTE_IF_SET_IN_BITMAP (to_process
, 0, j
, bi
)
5114 if ((int) j
>= lra_constraint_new_regno_start
)
5116 if (j
< FIRST_PSEUDO_REGISTER
|| reg_renumber
[j
] >= 0)
5118 if (j
< FIRST_PSEUDO_REGISTER
)
5119 SET_HARD_REG_BIT (live_hard_regs
, j
);
5121 add_to_hard_reg_set (&live_hard_regs
,
5122 PSEUDO_REGNO_MODE (j
),
5124 setup_next_usage_insn (j
, last_insn
, reloads_num
, after_p
);
5128 src_regno
= dst_regno
= -1;
5129 if (NONDEBUG_INSN_P (curr_insn
)
5130 && (set
= single_set (curr_insn
)) != NULL_RTX
5131 && REG_P (SET_DEST (set
)) && REG_P (SET_SRC (set
)))
5133 src_regno
= REGNO (SET_SRC (set
));
5134 dst_regno
= REGNO (SET_DEST (set
));
5136 update_reloads_num_p
= true;
5137 if (src_regno
< lra_constraint_new_regno_start
5138 && src_regno
>= FIRST_PSEUDO_REGISTER
5139 && reg_renumber
[src_regno
] < 0
5140 && dst_regno
>= lra_constraint_new_regno_start
5141 && (cl
= lra_get_allocno_class (dst_regno
)) != NO_REGS
)
5143 /* 'reload_pseudo <- original_pseudo'. */
5144 if (ira_class_hard_regs_num
[cl
] <= max_small_class_regs_num
)
5146 update_reloads_num_p
= false;
5148 if (usage_insns
[src_regno
].check
== curr_usage_insns_check
5149 && (next_usage_insns
= usage_insns
[src_regno
].insns
) != NULL_RTX
)
5150 succ_p
= inherit_reload_reg (false, src_regno
, cl
,
5151 curr_insn
, next_usage_insns
);
5155 setup_next_usage_insn (src_regno
, curr_insn
, reloads_num
, false);
5156 if (hard_reg_set_subset_p (reg_class_contents
[cl
], live_hard_regs
))
5157 IOR_HARD_REG_SET (potential_reload_hard_regs
,
5158 reg_class_contents
[cl
]);
5160 else if (src_regno
>= lra_constraint_new_regno_start
5161 && dst_regno
< lra_constraint_new_regno_start
5162 && dst_regno
>= FIRST_PSEUDO_REGISTER
5163 && reg_renumber
[dst_regno
] < 0
5164 && (cl
= lra_get_allocno_class (src_regno
)) != NO_REGS
5165 && usage_insns
[dst_regno
].check
== curr_usage_insns_check
5166 && (next_usage_insns
5167 = usage_insns
[dst_regno
].insns
) != NULL_RTX
)
5169 if (ira_class_hard_regs_num
[cl
] <= max_small_class_regs_num
)
5171 update_reloads_num_p
= false;
5172 /* 'original_pseudo <- reload_pseudo'. */
5173 if (! JUMP_P (curr_insn
)
5174 && inherit_reload_reg (true, dst_regno
, cl
,
5175 curr_insn
, next_usage_insns
))
5178 usage_insns
[dst_regno
].check
= 0;
5179 if (hard_reg_set_subset_p (reg_class_contents
[cl
], live_hard_regs
))
5180 IOR_HARD_REG_SET (potential_reload_hard_regs
,
5181 reg_class_contents
[cl
]);
5183 else if (INSN_P (curr_insn
))
5186 int max_uid
= get_max_uid ();
5188 curr_id
= lra_get_insn_recog_data (curr_insn
);
5189 curr_static_id
= curr_id
->insn_static_data
;
5191 /* Process insn definitions. */
5192 for (iter
= 0; iter
< 2; iter
++)
5193 for (reg
= iter
== 0 ? curr_id
->regs
: curr_static_id
->hard_regs
;
5196 if (reg
->type
!= OP_IN
5197 && (dst_regno
= reg
->regno
) < lra_constraint_new_regno_start
)
5199 if (dst_regno
>= FIRST_PSEUDO_REGISTER
&& reg
->type
== OP_OUT
5200 && reg_renumber
[dst_regno
] < 0 && ! reg
->subreg_p
5201 && usage_insns
[dst_regno
].check
== curr_usage_insns_check
5202 && (next_usage_insns
5203 = usage_insns
[dst_regno
].insns
) != NULL_RTX
)
5205 struct lra_insn_reg
*r
;
5207 for (r
= curr_id
->regs
; r
!= NULL
; r
= r
->next
)
5208 if (r
->type
!= OP_OUT
&& r
->regno
== dst_regno
)
5210 /* Don't do inheritance if the pseudo is also
5211 used in the insn. */
5213 /* We can not do inheritance right now
5214 because the current insn reg info (chain
5215 regs) can change after that. */
5216 add_to_inherit (dst_regno
, next_usage_insns
);
5218 /* We can not process one reg twice here because of
5219 usage_insns invalidation. */
5220 if ((dst_regno
< FIRST_PSEUDO_REGISTER
5221 || reg_renumber
[dst_regno
] >= 0)
5222 && ! reg
->subreg_p
&& reg
->type
!= OP_IN
)
5226 if (split_if_necessary (dst_regno
, reg
->biggest_mode
,
5227 potential_reload_hard_regs
,
5228 false, curr_insn
, max_uid
))
5230 CLEAR_HARD_REG_SET (s
);
5231 if (dst_regno
< FIRST_PSEUDO_REGISTER
)
5232 add_to_hard_reg_set (&s
, reg
->biggest_mode
, dst_regno
);
5234 add_to_hard_reg_set (&s
, PSEUDO_REGNO_MODE (dst_regno
),
5235 reg_renumber
[dst_regno
]);
5236 AND_COMPL_HARD_REG_SET (live_hard_regs
, s
);
5238 /* We should invalidate potential inheritance or
5239 splitting for the current insn usages to the next
5240 usage insns (see code below) as the output pseudo
5242 if ((dst_regno
>= FIRST_PSEUDO_REGISTER
5243 && reg_renumber
[dst_regno
] < 0)
5244 || (reg
->type
== OP_OUT
&& ! reg
->subreg_p
5245 && (dst_regno
< FIRST_PSEUDO_REGISTER
5246 || reg_renumber
[dst_regno
] >= 0)))
5248 /* Invalidate and mark definitions. */
5249 if (dst_regno
>= FIRST_PSEUDO_REGISTER
)
5250 usage_insns
[dst_regno
].check
= -(int) INSN_UID (curr_insn
);
5253 nregs
= hard_regno_nregs
[dst_regno
][reg
->biggest_mode
];
5254 for (i
= 0; i
< nregs
; i
++)
5255 usage_insns
[dst_regno
+ i
].check
5256 = -(int) INSN_UID (curr_insn
);
5260 if (! JUMP_P (curr_insn
))
5261 for (i
= 0; i
< to_inherit_num
; i
++)
5262 if (inherit_reload_reg (true, to_inherit
[i
].regno
,
5263 ALL_REGS
, curr_insn
,
5264 to_inherit
[i
].insns
))
5266 if (CALL_P (curr_insn
))
5268 rtx cheap
, pat
, dest
, restore
;
5269 int regno
, hard_regno
;
5272 if ((cheap
= find_reg_note (curr_insn
,
5273 REG_RETURNED
, NULL_RTX
)) != NULL_RTX
5274 && ((cheap
= XEXP (cheap
, 0)), true)
5275 && (regno
= REGNO (cheap
)) >= FIRST_PSEUDO_REGISTER
5276 && (hard_regno
= reg_renumber
[regno
]) >= 0
5277 /* If there are pending saves/restores, the
5278 optimization is not worth. */
5279 && usage_insns
[regno
].calls_num
== calls_num
- 1
5280 && TEST_HARD_REG_BIT (call_used_reg_set
, hard_regno
))
5282 /* Restore the pseudo from the call result as
5283 REG_RETURNED note says that the pseudo value is
5284 in the call result and the pseudo is an argument
5286 pat
= PATTERN (curr_insn
);
5287 if (GET_CODE (pat
) == PARALLEL
)
5288 pat
= XVECEXP (pat
, 0, 0);
5289 dest
= SET_DEST (pat
);
5291 emit_move_insn (cheap
, copy_rtx (dest
));
5292 restore
= get_insns ();
5294 lra_process_new_insns (curr_insn
, NULL
, restore
,
5295 "Inserting call parameter restore");
5296 /* We don't need to save/restore of the pseudo from
5298 usage_insns
[regno
].calls_num
= calls_num
;
5299 bitmap_set_bit (&check_only_regs
, regno
);
5303 /* Process insn usages. */
5304 for (iter
= 0; iter
< 2; iter
++)
5305 for (reg
= iter
== 0 ? curr_id
->regs
: curr_static_id
->hard_regs
;
5308 if ((reg
->type
!= OP_OUT
5309 || (reg
->type
== OP_OUT
&& reg
->subreg_p
))
5310 && (src_regno
= reg
->regno
) < lra_constraint_new_regno_start
)
5312 if (src_regno
>= FIRST_PSEUDO_REGISTER
5313 && reg_renumber
[src_regno
] < 0 && reg
->type
== OP_IN
)
5315 if (usage_insns
[src_regno
].check
== curr_usage_insns_check
5316 && (next_usage_insns
5317 = usage_insns
[src_regno
].insns
) != NULL_RTX
5318 && NONDEBUG_INSN_P (curr_insn
))
5319 add_to_inherit (src_regno
, next_usage_insns
);
5320 else if (usage_insns
[src_regno
].check
5321 != -(int) INSN_UID (curr_insn
))
5322 /* Add usages but only if the reg is not set up
5323 in the same insn. */
5324 add_next_usage_insn (src_regno
, curr_insn
, reloads_num
);
5326 else if (src_regno
< FIRST_PSEUDO_REGISTER
5327 || reg_renumber
[src_regno
] >= 0)
5330 rtx use_insn
= curr_insn
;
5332 before_p
= (JUMP_P (curr_insn
)
5333 || (CALL_P (curr_insn
) && reg
->type
== OP_IN
));
5334 if (NONDEBUG_INSN_P (curr_insn
)
5335 && (! JUMP_P (curr_insn
) || reg
->type
== OP_IN
)
5336 && split_if_necessary (src_regno
, reg
->biggest_mode
,
5337 potential_reload_hard_regs
,
5338 before_p
, curr_insn
, max_uid
))
5341 lra_risky_transformations_p
= true;
5344 usage_insns
[src_regno
].check
= 0;
5346 use_insn
= PREV_INSN (curr_insn
);
5348 if (NONDEBUG_INSN_P (curr_insn
))
5350 if (src_regno
< FIRST_PSEUDO_REGISTER
)
5351 add_to_hard_reg_set (&live_hard_regs
,
5352 reg
->biggest_mode
, src_regno
);
5354 add_to_hard_reg_set (&live_hard_regs
,
5355 PSEUDO_REGNO_MODE (src_regno
),
5356 reg_renumber
[src_regno
]);
5358 add_next_usage_insn (src_regno
, use_insn
, reloads_num
);
5361 /* Process call args. */
5362 if (curr_id
->arg_hard_regs
!= NULL
)
5363 for (i
= 0; (src_regno
= curr_id
->arg_hard_regs
[i
]) >= 0; i
++)
5364 if (src_regno
< FIRST_PSEUDO_REGISTER
)
5366 SET_HARD_REG_BIT (live_hard_regs
, src_regno
);
5367 add_next_usage_insn (src_regno
, curr_insn
, reloads_num
);
5369 for (i
= 0; i
< to_inherit_num
; i
++)
5371 src_regno
= to_inherit
[i
].regno
;
5372 if (inherit_reload_reg (false, src_regno
, ALL_REGS
,
5373 curr_insn
, to_inherit
[i
].insns
))
5376 setup_next_usage_insn (src_regno
, curr_insn
, reloads_num
, false);
5379 if (update_reloads_num_p
5380 && NONDEBUG_INSN_P (curr_insn
)
5381 && (set
= single_set (curr_insn
)) != NULL_RTX
)
5384 if ((REG_P (SET_DEST (set
))
5385 && (regno
= REGNO (SET_DEST (set
))) >= lra_constraint_new_regno_start
5386 && reg_renumber
[regno
] < 0
5387 && (cl
= lra_get_allocno_class (regno
)) != NO_REGS
)
5388 || (REG_P (SET_SRC (set
))
5389 && (regno
= REGNO (SET_SRC (set
))) >= lra_constraint_new_regno_start
5390 && reg_renumber
[regno
] < 0
5391 && (cl
= lra_get_allocno_class (regno
)) != NO_REGS
))
5393 if (ira_class_hard_regs_num
[cl
] <= max_small_class_regs_num
)
5395 if (hard_reg_set_subset_p (reg_class_contents
[cl
], live_hard_regs
))
5396 IOR_HARD_REG_SET (potential_reload_hard_regs
,
5397 reg_class_contents
[cl
]);
5400 /* We reached the start of the current basic block. */
5401 if (prev_insn
== NULL_RTX
|| prev_insn
== PREV_INSN (head
)
5402 || BLOCK_FOR_INSN (prev_insn
) != curr_bb
)
5404 /* We reached the beginning of the current block -- do
5405 rest of spliting in the current BB. */
5406 to_process
= df_get_live_in (curr_bb
);
5407 if (BLOCK_FOR_INSN (head
) != curr_bb
)
5409 /* We are somewhere in the middle of EBB. */
5410 get_live_on_other_edges (EDGE_PRED (curr_bb
, 0)->src
,
5411 curr_bb
, &temp_bitmap
);
5412 to_process
= &temp_bitmap
;
5415 EXECUTE_IF_SET_IN_BITMAP (to_process
, 0, j
, bi
)
5417 if ((int) j
>= lra_constraint_new_regno_start
)
5419 if (((int) j
< FIRST_PSEUDO_REGISTER
|| reg_renumber
[j
] >= 0)
5420 && usage_insns
[j
].check
== curr_usage_insns_check
5421 && (next_usage_insns
= usage_insns
[j
].insns
) != NULL_RTX
)
5423 if (need_for_split_p (potential_reload_hard_regs
, j
))
5425 if (lra_dump_file
!= NULL
&& head_p
)
5427 fprintf (lra_dump_file
,
5428 " ----------------------------------\n");
5431 if (split_reg (false, j
, bb_note (curr_bb
),
5435 usage_insns
[j
].check
= 0;
5443 /* This value affects EBB forming. If probability of edge from EBB to
5444 a BB is not greater than the following value, we don't add the BB
5446 #define EBB_PROBABILITY_CUTOFF ((REG_BR_PROB_BASE * 50) / 100)
5448 /* Current number of inheritance/split iteration. */
5449 int lra_inheritance_iter
;
5451 /* Entry function for inheritance/split pass. */
5453 lra_inheritance (void)
5456 basic_block bb
, start_bb
;
5459 lra_inheritance_iter
++;
5460 if (lra_inheritance_iter
> LRA_MAX_INHERITANCE_PASSES
)
5462 timevar_push (TV_LRA_INHERITANCE
);
5463 if (lra_dump_file
!= NULL
)
5464 fprintf (lra_dump_file
, "\n********** Inheritance #%d: **********\n\n",
5465 lra_inheritance_iter
);
5466 curr_usage_insns_check
= 0;
5467 usage_insns
= XNEWVEC (struct usage_insns
, lra_constraint_new_regno_start
);
5468 for (i
= 0; i
< lra_constraint_new_regno_start
; i
++)
5469 usage_insns
[i
].check
= 0;
5470 bitmap_initialize (&check_only_regs
, ®_obstack
);
5471 bitmap_initialize (&live_regs
, ®_obstack
);
5472 bitmap_initialize (&temp_bitmap
, ®_obstack
);
5473 bitmap_initialize (&ebb_global_regs
, ®_obstack
);
5474 FOR_EACH_BB_FN (bb
, cfun
)
5477 if (lra_dump_file
!= NULL
)
5478 fprintf (lra_dump_file
, "EBB");
5479 /* Form a EBB starting with BB. */
5480 bitmap_clear (&ebb_global_regs
);
5481 bitmap_ior_into (&ebb_global_regs
, df_get_live_in (bb
));
5484 if (lra_dump_file
!= NULL
)
5485 fprintf (lra_dump_file
, " %d", bb
->index
);
5486 if (bb
->next_bb
== EXIT_BLOCK_PTR_FOR_FN (cfun
)
5487 || LABEL_P (BB_HEAD (bb
->next_bb
)))
5489 e
= find_fallthru_edge (bb
->succs
);
5492 if (e
->probability
<= EBB_PROBABILITY_CUTOFF
)
5496 bitmap_ior_into (&ebb_global_regs
, df_get_live_out (bb
));
5497 if (lra_dump_file
!= NULL
)
5498 fprintf (lra_dump_file
, "\n");
5499 if (inherit_in_ebb (BB_HEAD (start_bb
), BB_END (bb
)))
5500 /* Remember that the EBB head and tail can change in
5502 update_ebb_live_info (BB_HEAD (start_bb
), BB_END (bb
));
5504 bitmap_clear (&ebb_global_regs
);
5505 bitmap_clear (&temp_bitmap
);
5506 bitmap_clear (&live_regs
);
5507 bitmap_clear (&check_only_regs
);
5510 timevar_pop (TV_LRA_INHERITANCE
);
5515 /* This page contains code to undo failed inheritance/split
5518 /* Current number of iteration undoing inheritance/split. */
5519 int lra_undo_inheritance_iter
;
5521 /* Fix BB live info LIVE after removing pseudos created on pass doing
5522 inheritance/split which are REMOVED_PSEUDOS. */
5524 fix_bb_live_info (bitmap live
, bitmap removed_pseudos
)
5529 EXECUTE_IF_SET_IN_BITMAP (removed_pseudos
, 0, regno
, bi
)
5530 if (bitmap_clear_bit (live
, regno
))
5531 bitmap_set_bit (live
, lra_reg_info
[regno
].restore_regno
);
5534 /* Return regno of the (subreg of) REG. Otherwise, return a negative
5539 if (GET_CODE (reg
) == SUBREG
)
5540 reg
= SUBREG_REG (reg
);
5546 /* Remove inheritance/split pseudos which are in REMOVE_PSEUDOS and
5547 return true if we did any change. The undo transformations for
5548 inheritance looks like
5552 p <- i, i <- p, and i <- i3
5553 where p is original pseudo from which inheritance pseudo i was
5554 created, i and i3 are removed inheritance pseudos, i2 is another
5555 not removed inheritance pseudo. All split pseudos or other
5556 occurrences of removed inheritance pseudos are changed on the
5557 corresponding original pseudos.
5559 The function also schedules insns changed and created during
5560 inheritance/split pass for processing by the subsequent constraint
5563 remove_inheritance_pseudos (bitmap remove_pseudos
)
5566 int regno
, sregno
, prev_sregno
, dregno
, restore_regno
;
5567 rtx set
, prev_set
, prev_insn
;
5568 bool change_p
, done_p
;
5570 change_p
= ! bitmap_empty_p (remove_pseudos
);
5571 /* We can not finish the function right away if CHANGE_P is true
5572 because we need to marks insns affected by previous
5573 inheritance/split pass for processing by the subsequent
5575 FOR_EACH_BB_FN (bb
, cfun
)
5577 fix_bb_live_info (df_get_live_in (bb
), remove_pseudos
);
5578 fix_bb_live_info (df_get_live_out (bb
), remove_pseudos
);
5579 FOR_BB_INSNS_REVERSE (bb
, curr_insn
)
5581 if (! INSN_P (curr_insn
))
5584 sregno
= dregno
= -1;
5585 if (change_p
&& NONDEBUG_INSN_P (curr_insn
)
5586 && (set
= single_set (curr_insn
)) != NULL_RTX
)
5588 dregno
= get_regno (SET_DEST (set
));
5589 sregno
= get_regno (SET_SRC (set
));
5592 if (sregno
>= 0 && dregno
>= 0)
5594 if ((bitmap_bit_p (remove_pseudos
, sregno
)
5595 && (lra_reg_info
[sregno
].restore_regno
== dregno
5596 || (bitmap_bit_p (remove_pseudos
, dregno
)
5597 && (lra_reg_info
[sregno
].restore_regno
5598 == lra_reg_info
[dregno
].restore_regno
))))
5599 || (bitmap_bit_p (remove_pseudos
, dregno
)
5600 && lra_reg_info
[dregno
].restore_regno
== sregno
))
5601 /* One of the following cases:
5602 original <- removed inheritance pseudo
5603 removed inherit pseudo <- another removed inherit pseudo
5604 removed inherit pseudo <- original pseudo
5606 removed_split_pseudo <- original_reg
5607 original_reg <- removed_split_pseudo */
5609 if (lra_dump_file
!= NULL
)
5611 fprintf (lra_dump_file
, " Removing %s:\n",
5612 bitmap_bit_p (&lra_split_regs
, sregno
)
5613 || bitmap_bit_p (&lra_split_regs
, dregno
)
5614 ? "split" : "inheritance");
5615 dump_insn_slim (lra_dump_file
, curr_insn
);
5617 lra_set_insn_deleted (curr_insn
);
5620 else if (bitmap_bit_p (remove_pseudos
, sregno
)
5621 && bitmap_bit_p (&lra_inheritance_pseudos
, sregno
))
5623 /* Search the following pattern:
5624 inherit_or_split_pseudo1 <- inherit_or_split_pseudo2
5625 original_pseudo <- inherit_or_split_pseudo1
5626 where the 2nd insn is the current insn and
5627 inherit_or_split_pseudo2 is not removed. If it is found,
5628 change the current insn onto:
5629 original_pseudo <- inherit_or_split_pseudo2. */
5630 for (prev_insn
= PREV_INSN (curr_insn
);
5631 prev_insn
!= NULL_RTX
&& ! NONDEBUG_INSN_P (prev_insn
);
5632 prev_insn
= PREV_INSN (prev_insn
))
5634 if (prev_insn
!= NULL_RTX
&& BLOCK_FOR_INSN (prev_insn
) == bb
5635 && (prev_set
= single_set (prev_insn
)) != NULL_RTX
5636 /* There should be no subregs in insn we are
5637 searching because only the original reg might
5638 be in subreg when we changed the mode of
5639 load/store for splitting. */
5640 && REG_P (SET_DEST (prev_set
))
5641 && REG_P (SET_SRC (prev_set
))
5642 && (int) REGNO (SET_DEST (prev_set
)) == sregno
5643 && ((prev_sregno
= REGNO (SET_SRC (prev_set
)))
5644 >= FIRST_PSEUDO_REGISTER
)
5645 /* As we consider chain of inheritance or
5646 splitting described in above comment we should
5647 check that sregno and prev_sregno were
5648 inheritance/split pseudos created from the
5649 same original regno. */
5650 && (lra_reg_info
[sregno
].restore_regno
5651 == lra_reg_info
[prev_sregno
].restore_regno
)
5652 && ! bitmap_bit_p (remove_pseudos
, prev_sregno
))
5654 lra_assert (GET_MODE (SET_SRC (prev_set
))
5655 == GET_MODE (regno_reg_rtx
[sregno
]));
5656 if (GET_CODE (SET_SRC (set
)) == SUBREG
)
5657 SUBREG_REG (SET_SRC (set
)) = SET_SRC (prev_set
);
5659 SET_SRC (set
) = SET_SRC (prev_set
);
5660 lra_push_insn_and_update_insn_regno_info (curr_insn
);
5661 lra_set_used_insn_alternative_by_uid
5662 (INSN_UID (curr_insn
), -1);
5664 if (lra_dump_file
!= NULL
)
5666 fprintf (lra_dump_file
, " Change reload insn:\n");
5667 dump_insn_slim (lra_dump_file
, curr_insn
);
5674 struct lra_insn_reg
*reg
;
5675 bool restored_regs_p
= false;
5676 bool kept_regs_p
= false;
5678 curr_id
= lra_get_insn_recog_data (curr_insn
);
5679 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
5682 restore_regno
= lra_reg_info
[regno
].restore_regno
;
5683 if (restore_regno
>= 0)
5685 if (change_p
&& bitmap_bit_p (remove_pseudos
, regno
))
5687 substitute_pseudo (&curr_insn
, regno
,
5688 regno_reg_rtx
[restore_regno
]);
5689 restored_regs_p
= true;
5695 if (NONDEBUG_INSN_P (curr_insn
) && kept_regs_p
)
5697 /* The instruction has changed since the previous
5698 constraints pass. */
5699 lra_push_insn_and_update_insn_regno_info (curr_insn
);
5700 lra_set_used_insn_alternative_by_uid
5701 (INSN_UID (curr_insn
), -1);
5703 else if (restored_regs_p
)
5704 /* The instruction has been restored to the form that
5705 it had during the previous constraints pass. */
5706 lra_update_insn_regno_info (curr_insn
);
5707 if (restored_regs_p
&& lra_dump_file
!= NULL
)
5709 fprintf (lra_dump_file
, " Insn after restoring regs:\n");
5710 dump_insn_slim (lra_dump_file
, curr_insn
);
5718 /* If optional reload pseudos failed to get a hard register or was not
5719 inherited, it is better to remove optional reloads. We do this
5720 transformation after undoing inheritance to figure out necessity to
5721 remove optional reloads easier. Return true if we do any
5724 undo_optional_reloads (void)
5726 bool change_p
, keep_p
;
5727 unsigned int regno
, uid
;
5728 bitmap_iterator bi
, bi2
;
5729 rtx insn
, set
, src
, dest
;
5730 bitmap_head removed_optional_reload_pseudos
, insn_bitmap
;
5732 bitmap_initialize (&removed_optional_reload_pseudos
, ®_obstack
);
5733 bitmap_copy (&removed_optional_reload_pseudos
, &lra_optional_reload_pseudos
);
5734 EXECUTE_IF_SET_IN_BITMAP (&lra_optional_reload_pseudos
, 0, regno
, bi
)
5737 /* Keep optional reloads from previous subpasses. */
5738 if (lra_reg_info
[regno
].restore_regno
< 0
5739 /* If the original pseudo changed its allocation, just
5740 removing the optional pseudo is dangerous as the original
5741 pseudo will have longer live range. */
5742 || reg_renumber
[lra_reg_info
[regno
].restore_regno
] >= 0)
5744 else if (reg_renumber
[regno
] >= 0)
5745 EXECUTE_IF_SET_IN_BITMAP (&lra_reg_info
[regno
].insn_bitmap
, 0, uid
, bi2
)
5747 insn
= lra_insn_recog_data
[uid
]->insn
;
5748 if ((set
= single_set (insn
)) == NULL_RTX
)
5750 src
= SET_SRC (set
);
5751 dest
= SET_DEST (set
);
5752 if (! REG_P (src
) || ! REG_P (dest
))
5754 if (REGNO (dest
) == regno
5755 /* Ignore insn for optional reloads itself. */
5756 && lra_reg_info
[regno
].restore_regno
!= (int) REGNO (src
)
5757 /* Check only inheritance on last inheritance pass. */
5758 && (int) REGNO (src
) >= new_regno_start
5759 /* Check that the optional reload was inherited. */
5760 && bitmap_bit_p (&lra_inheritance_pseudos
, REGNO (src
)))
5768 bitmap_clear_bit (&removed_optional_reload_pseudos
, regno
);
5769 if (lra_dump_file
!= NULL
)
5770 fprintf (lra_dump_file
, "Keep optional reload reg %d\n", regno
);
5773 change_p
= ! bitmap_empty_p (&removed_optional_reload_pseudos
);
5774 bitmap_initialize (&insn_bitmap
, ®_obstack
);
5775 EXECUTE_IF_SET_IN_BITMAP (&removed_optional_reload_pseudos
, 0, regno
, bi
)
5777 if (lra_dump_file
!= NULL
)
5778 fprintf (lra_dump_file
, "Remove optional reload reg %d\n", regno
);
5779 bitmap_copy (&insn_bitmap
, &lra_reg_info
[regno
].insn_bitmap
);
5780 EXECUTE_IF_SET_IN_BITMAP (&insn_bitmap
, 0, uid
, bi2
)
5782 insn
= lra_insn_recog_data
[uid
]->insn
;
5783 if ((set
= single_set (insn
)) != NULL_RTX
)
5785 src
= SET_SRC (set
);
5786 dest
= SET_DEST (set
);
5787 if (REG_P (src
) && REG_P (dest
)
5788 && ((REGNO (src
) == regno
5789 && (lra_reg_info
[regno
].restore_regno
5790 == (int) REGNO (dest
)))
5791 || (REGNO (dest
) == regno
5792 && (lra_reg_info
[regno
].restore_regno
5793 == (int) REGNO (src
)))))
5795 if (lra_dump_file
!= NULL
)
5797 fprintf (lra_dump_file
, " Deleting move %u\n",
5799 dump_insn_slim (lra_dump_file
, insn
);
5801 lra_set_insn_deleted (insn
);
5804 /* We should not worry about generation memory-memory
5805 moves here as if the corresponding inheritance did
5806 not work (inheritance pseudo did not get a hard reg),
5807 we remove the inheritance pseudo and the optional
5810 substitute_pseudo (&insn
, regno
,
5811 regno_reg_rtx
[lra_reg_info
[regno
].restore_regno
]);
5812 lra_update_insn_regno_info (insn
);
5813 if (lra_dump_file
!= NULL
)
5815 fprintf (lra_dump_file
,
5816 " Restoring original insn:\n");
5817 dump_insn_slim (lra_dump_file
, insn
);
5821 /* Clear restore_regnos. */
5822 EXECUTE_IF_SET_IN_BITMAP (&lra_optional_reload_pseudos
, 0, regno
, bi
)
5823 lra_reg_info
[regno
].restore_regno
= -1;
5824 bitmap_clear (&insn_bitmap
);
5825 bitmap_clear (&removed_optional_reload_pseudos
);
5829 /* Entry function for undoing inheritance/split transformation. Return true
5830 if we did any RTL change in this pass. */
5832 lra_undo_inheritance (void)
5835 int restore_regno
, hard_regno
;
5836 int n_all_inherit
, n_inherit
, n_all_split
, n_split
;
5837 bitmap_head remove_pseudos
;
5841 lra_undo_inheritance_iter
++;
5842 if (lra_undo_inheritance_iter
> LRA_MAX_INHERITANCE_PASSES
)
5844 if (lra_dump_file
!= NULL
)
5845 fprintf (lra_dump_file
,
5846 "\n********** Undoing inheritance #%d: **********\n\n",
5847 lra_undo_inheritance_iter
);
5848 bitmap_initialize (&remove_pseudos
, ®_obstack
);
5849 n_inherit
= n_all_inherit
= 0;
5850 EXECUTE_IF_SET_IN_BITMAP (&lra_inheritance_pseudos
, 0, regno
, bi
)
5851 if (lra_reg_info
[regno
].restore_regno
>= 0)
5854 if (reg_renumber
[regno
] < 0
5855 /* If the original pseudo changed its allocation, just
5856 removing inheritance is dangerous as for changing
5857 allocation we used shorter live-ranges. */
5858 && reg_renumber
[lra_reg_info
[regno
].restore_regno
] < 0)
5859 bitmap_set_bit (&remove_pseudos
, regno
);
5863 if (lra_dump_file
!= NULL
&& n_all_inherit
!= 0)
5864 fprintf (lra_dump_file
, "Inherit %d out of %d (%.2f%%)\n",
5865 n_inherit
, n_all_inherit
,
5866 (double) n_inherit
/ n_all_inherit
* 100);
5867 n_split
= n_all_split
= 0;
5868 EXECUTE_IF_SET_IN_BITMAP (&lra_split_regs
, 0, regno
, bi
)
5869 if ((restore_regno
= lra_reg_info
[regno
].restore_regno
) >= 0)
5872 hard_regno
= (restore_regno
>= FIRST_PSEUDO_REGISTER
5873 ? reg_renumber
[restore_regno
] : restore_regno
);
5874 if (hard_regno
< 0 || reg_renumber
[regno
] == hard_regno
)
5875 bitmap_set_bit (&remove_pseudos
, regno
);
5879 if (lra_dump_file
!= NULL
)
5880 fprintf (lra_dump_file
, " Keep split r%d (orig=r%d)\n",
5881 regno
, restore_regno
);
5884 if (lra_dump_file
!= NULL
&& n_all_split
!= 0)
5885 fprintf (lra_dump_file
, "Split %d out of %d (%.2f%%)\n",
5886 n_split
, n_all_split
,
5887 (double) n_split
/ n_all_split
* 100);
5888 change_p
= remove_inheritance_pseudos (&remove_pseudos
);
5889 bitmap_clear (&remove_pseudos
);
5890 /* Clear restore_regnos. */
5891 EXECUTE_IF_SET_IN_BITMAP (&lra_inheritance_pseudos
, 0, regno
, bi
)
5892 lra_reg_info
[regno
].restore_regno
= -1;
5893 EXECUTE_IF_SET_IN_BITMAP (&lra_split_regs
, 0, regno
, bi
)
5894 lra_reg_info
[regno
].restore_regno
= -1;
5895 change_p
= undo_optional_reloads () || change_p
;