1 /* Code for RTL transformations to satisfy insn constraints.
2 Copyright (C) 2010-2014 Free Software Foundation, Inc.
3 Contributed by Vladimir Makarov <vmakarov@redhat.com>.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 3, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
22 /* This file contains code for 3 passes: constraint pass,
23 inheritance/split pass, and pass for undoing failed inheritance and
26 The major goal of constraint pass is to transform RTL to satisfy
27 insn and address constraints by:
28 o choosing insn alternatives;
29 o generating *reload insns* (or reloads in brief) and *reload
30 pseudos* which will get necessary hard registers later;
31 o substituting pseudos with equivalent values and removing the
32 instructions that initialized those pseudos.
34 The constraint pass has biggest and most complicated code in LRA.
35 There are a lot of important details like:
36 o reuse of input reload pseudos to simplify reload pseudo
38 o some heuristics to choose insn alternative to improve the
42 The pass is mimicking former reload pass in alternative choosing
43 because the reload pass is oriented to current machine description
44 model. It might be changed if the machine description model is
47 There is special code for preventing all LRA and this pass cycling
50 On the first iteration of the pass we process every instruction and
51 choose an alternative for each one. On subsequent iterations we try
52 to avoid reprocessing instructions if we can be sure that the old
53 choice is still valid.
55 The inheritance/spilt pass is to transform code to achieve
56 ineheritance and live range splitting. It is done on backward
59 The inheritance optimization goal is to reuse values in hard
60 registers. There is analogous optimization in old reload pass. The
61 inheritance is achieved by following transformation:
63 reload_p1 <- p reload_p1 <- p
64 ... new_p <- reload_p1
66 reload_p2 <- p reload_p2 <- new_p
68 where p is spilled and not changed between the insns. Reload_p1 is
69 also called *original pseudo* and new_p is called *inheritance
72 The subsequent assignment pass will try to assign the same (or
73 another if it is not possible) hard register to new_p as to
74 reload_p1 or reload_p2.
76 If the assignment pass fails to assign a hard register to new_p,
77 this file will undo the inheritance and restore the original code.
78 This is because implementing the above sequence with a spilled
79 new_p would make the code much worse. The inheritance is done in
80 EBB scope. The above is just a simplified example to get an idea
81 of the inheritance as the inheritance is also done for non-reload
84 Splitting (transformation) is also done in EBB scope on the same
85 pass as the inheritance:
87 r <- ... or ... <- r r <- ... or ... <- r
88 ... s <- r (new insn -- save)
90 ... r <- s (new insn -- restore)
93 The *split pseudo* s is assigned to the hard register of the
94 original pseudo or hard register r.
97 o In EBBs with high register pressure for global pseudos (living
98 in at least 2 BBs) and assigned to hard registers when there
99 are more one reloads needing the hard registers;
100 o for pseudos needing save/restore code around calls.
102 If the split pseudo still has the same hard register as the
103 original pseudo after the subsequent assignment pass or the
104 original pseudo was split, the opposite transformation is done on
105 the same pass for undoing inheritance. */
111 #include "coretypes.h"
113 #include "hard-reg-set.h"
117 #include "insn-config.h"
118 #include "insn-codes.h"
121 #include "addresses.h"
123 #include "function.h"
125 #include "basic-block.h"
130 #include "rtl-error.h"
133 /* Value of LRA_CURR_RELOAD_NUM at the beginning of BB of the current
134 insn. Remember that LRA_CURR_RELOAD_NUM is the number of emitted
136 static int bb_reload_num
;
138 /* The current insn being processed and corresponding its single set
139 (NULL otherwise), its data (basic block, the insn data, the insn
140 static data, and the mode of each operand). */
141 static rtx_insn
*curr_insn
;
142 static rtx curr_insn_set
;
143 static basic_block curr_bb
;
144 static lra_insn_recog_data_t curr_id
;
145 static struct lra_static_insn_data
*curr_static_id
;
146 static enum machine_mode curr_operand_mode
[MAX_RECOG_OPERANDS
];
150 /* Start numbers for new registers and insns at the current constraints
152 static int new_regno_start
;
153 static int new_insn_uid_start
;
155 /* If LOC is nonnull, strip any outer subreg from it. */
157 strip_subreg (rtx
*loc
)
159 return loc
&& GET_CODE (*loc
) == SUBREG
? &SUBREG_REG (*loc
) : loc
;
162 /* Return hard regno of REGNO or if it is was not assigned to a hard
163 register, use a hard register from its allocno class. */
165 get_try_hard_regno (int regno
)
168 enum reg_class rclass
;
170 if ((hard_regno
= regno
) >= FIRST_PSEUDO_REGISTER
)
171 hard_regno
= lra_get_regno_hard_regno (regno
);
174 rclass
= lra_get_allocno_class (regno
);
175 if (rclass
== NO_REGS
)
177 return ira_class_hard_regs
[rclass
][0];
180 /* Return final hard regno (plus offset) which will be after
181 elimination. We do this for matching constraints because the final
182 hard regno could have a different class. */
184 get_final_hard_regno (int hard_regno
, int offset
)
188 hard_regno
= lra_get_elimination_hard_regno (hard_regno
);
189 return hard_regno
+ offset
;
192 /* Return hard regno of X after removing subreg and making
193 elimination. If X is not a register or subreg of register, return
194 -1. For pseudo use its assignment. */
196 get_hard_regno (rtx x
)
199 int offset
, hard_regno
;
202 if (GET_CODE (x
) == SUBREG
)
203 reg
= SUBREG_REG (x
);
206 if ((hard_regno
= REGNO (reg
)) >= FIRST_PSEUDO_REGISTER
)
207 hard_regno
= lra_get_regno_hard_regno (hard_regno
);
211 if (GET_CODE (x
) == SUBREG
)
212 offset
+= subreg_regno_offset (hard_regno
, GET_MODE (reg
),
213 SUBREG_BYTE (x
), GET_MODE (x
));
214 return get_final_hard_regno (hard_regno
, offset
);
217 /* If REGNO is a hard register or has been allocated a hard register,
218 return the class of that register. If REGNO is a reload pseudo
219 created by the current constraints pass, return its allocno class.
220 Return NO_REGS otherwise. */
221 static enum reg_class
222 get_reg_class (int regno
)
226 if ((hard_regno
= regno
) >= FIRST_PSEUDO_REGISTER
)
227 hard_regno
= lra_get_regno_hard_regno (regno
);
230 hard_regno
= get_final_hard_regno (hard_regno
, 0);
231 return REGNO_REG_CLASS (hard_regno
);
233 if (regno
>= new_regno_start
)
234 return lra_get_allocno_class (regno
);
238 /* Return true if REG satisfies (or will satisfy) reg class constraint
239 CL. Use elimination first if REG is a hard register. If REG is a
240 reload pseudo created by this constraints pass, assume that it will
241 be allocated a hard register from its allocno class, but allow that
242 class to be narrowed to CL if it is currently a superset of CL.
244 If NEW_CLASS is nonnull, set *NEW_CLASS to the new allocno class of
245 REGNO (reg), or NO_REGS if no change in its class was needed. */
247 in_class_p (rtx reg
, enum reg_class cl
, enum reg_class
*new_class
)
249 enum reg_class rclass
, common_class
;
250 enum machine_mode reg_mode
;
251 int class_size
, hard_regno
, nregs
, i
, j
;
252 int regno
= REGNO (reg
);
254 if (new_class
!= NULL
)
255 *new_class
= NO_REGS
;
256 if (regno
< FIRST_PSEUDO_REGISTER
)
259 rtx
*final_loc
= &final_reg
;
261 lra_eliminate_reg_if_possible (final_loc
);
262 return TEST_HARD_REG_BIT (reg_class_contents
[cl
], REGNO (*final_loc
));
264 reg_mode
= GET_MODE (reg
);
265 rclass
= get_reg_class (regno
);
266 if (regno
< new_regno_start
267 /* Do not allow the constraints for reload instructions to
268 influence the classes of new pseudos. These reloads are
269 typically moves that have many alternatives, and restricting
270 reload pseudos for one alternative may lead to situations
271 where other reload pseudos are no longer allocatable. */
272 || (INSN_UID (curr_insn
) >= new_insn_uid_start
273 && curr_insn_set
!= NULL
274 && ((OBJECT_P (SET_SRC (curr_insn_set
))
275 && ! CONSTANT_P (SET_SRC (curr_insn_set
)))
276 || (GET_CODE (SET_SRC (curr_insn_set
)) == SUBREG
277 && OBJECT_P (SUBREG_REG (SET_SRC (curr_insn_set
)))
278 && ! CONSTANT_P (SUBREG_REG (SET_SRC (curr_insn_set
)))))))
279 /* When we don't know what class will be used finally for reload
280 pseudos, we use ALL_REGS. */
281 return ((regno
>= new_regno_start
&& rclass
== ALL_REGS
)
282 || (rclass
!= NO_REGS
&& ira_class_subset_p
[rclass
][cl
]
283 && ! hard_reg_set_subset_p (reg_class_contents
[cl
],
284 lra_no_alloc_regs
)));
287 common_class
= ira_reg_class_subset
[rclass
][cl
];
288 if (new_class
!= NULL
)
289 *new_class
= common_class
;
290 if (hard_reg_set_subset_p (reg_class_contents
[common_class
],
293 /* Check that there are enough allocatable regs. */
294 class_size
= ira_class_hard_regs_num
[common_class
];
295 for (i
= 0; i
< class_size
; i
++)
297 hard_regno
= ira_class_hard_regs
[common_class
][i
];
298 nregs
= hard_regno_nregs
[hard_regno
][reg_mode
];
301 for (j
= 0; j
< nregs
; j
++)
302 if (TEST_HARD_REG_BIT (lra_no_alloc_regs
, hard_regno
+ j
)
303 || ! TEST_HARD_REG_BIT (reg_class_contents
[common_class
],
313 /* Return true if REGNO satisfies a memory constraint. */
317 return get_reg_class (regno
) == NO_REGS
;
320 /* Return 1 if ADDR is a valid memory address for mode MODE in address
321 space AS, and check that each pseudo has the proper kind of hard
324 valid_address_p (enum machine_mode mode ATTRIBUTE_UNUSED
,
325 rtx addr
, addr_space_t as
)
327 #ifdef GO_IF_LEGITIMATE_ADDRESS
328 lra_assert (ADDR_SPACE_GENERIC_P (as
));
329 GO_IF_LEGITIMATE_ADDRESS (mode
, addr
, win
);
335 return targetm
.addr_space
.legitimate_address_p (mode
, addr
, 0, as
);
340 /* Temporarily eliminates registers in an address (for the lifetime of
342 class address_eliminator
{
344 address_eliminator (struct address_info
*ad
);
345 ~address_eliminator ();
348 struct address_info
*m_ad
;
356 address_eliminator::address_eliminator (struct address_info
*ad
)
358 m_base_loc (strip_subreg (ad
->base_term
)),
359 m_base_reg (NULL_RTX
),
360 m_index_loc (strip_subreg (ad
->index_term
)),
361 m_index_reg (NULL_RTX
)
363 if (m_base_loc
!= NULL
)
365 m_base_reg
= *m_base_loc
;
366 lra_eliminate_reg_if_possible (m_base_loc
);
367 if (m_ad
->base_term2
!= NULL
)
368 *m_ad
->base_term2
= *m_ad
->base_term
;
370 if (m_index_loc
!= NULL
)
372 m_index_reg
= *m_index_loc
;
373 lra_eliminate_reg_if_possible (m_index_loc
);
377 address_eliminator::~address_eliminator ()
379 if (m_base_loc
&& *m_base_loc
!= m_base_reg
)
381 *m_base_loc
= m_base_reg
;
382 if (m_ad
->base_term2
!= NULL
)
383 *m_ad
->base_term2
= *m_ad
->base_term
;
385 if (m_index_loc
&& *m_index_loc
!= m_index_reg
)
386 *m_index_loc
= m_index_reg
;
389 /* Return true if the eliminated form of AD is a legitimate target address. */
391 valid_address_p (struct address_info
*ad
)
393 address_eliminator
eliminator (ad
);
394 return valid_address_p (ad
->mode
, *ad
->outer
, ad
->as
);
397 /* Return true if the eliminated form of memory reference OP satisfies
398 extra memory constraint CONSTRAINT. */
400 satisfies_memory_constraint_p (rtx op
, enum constraint_num constraint
)
402 struct address_info ad
;
404 decompose_mem_address (&ad
, op
);
405 address_eliminator
eliminator (&ad
);
406 return constraint_satisfied_p (op
, constraint
);
409 /* Return true if the eliminated form of address AD satisfies extra
410 address constraint CONSTRAINT. */
412 satisfies_address_constraint_p (struct address_info
*ad
,
413 enum constraint_num constraint
)
415 address_eliminator
eliminator (ad
);
416 return constraint_satisfied_p (*ad
->outer
, constraint
);
419 /* Return true if the eliminated form of address OP satisfies extra
420 address constraint CONSTRAINT. */
422 satisfies_address_constraint_p (rtx op
, enum constraint_num constraint
)
424 struct address_info ad
;
426 decompose_lea_address (&ad
, &op
);
427 return satisfies_address_constraint_p (&ad
, constraint
);
430 /* Initiate equivalences for LRA. As we keep original equivalences
431 before any elimination, we need to make copies otherwise any change
432 in insns might change the equivalences. */
434 lra_init_equiv (void)
436 ira_expand_reg_equiv ();
437 for (int i
= FIRST_PSEUDO_REGISTER
; i
< max_reg_num (); i
++)
441 if ((res
= ira_reg_equiv
[i
].memory
) != NULL_RTX
)
442 ira_reg_equiv
[i
].memory
= copy_rtx (res
);
443 if ((res
= ira_reg_equiv
[i
].invariant
) != NULL_RTX
)
444 ira_reg_equiv
[i
].invariant
= copy_rtx (res
);
448 static rtx
loc_equivalence_callback (rtx
, const_rtx
, void *);
450 /* Update equivalence for REGNO. We need to this as the equivalence
451 might contain other pseudos which are changed by their
454 update_equiv (int regno
)
458 if ((x
= ira_reg_equiv
[regno
].memory
) != NULL_RTX
)
459 ira_reg_equiv
[regno
].memory
460 = simplify_replace_fn_rtx (x
, NULL_RTX
, loc_equivalence_callback
,
462 if ((x
= ira_reg_equiv
[regno
].invariant
) != NULL_RTX
)
463 ira_reg_equiv
[regno
].invariant
464 = simplify_replace_fn_rtx (x
, NULL_RTX
, loc_equivalence_callback
,
468 /* If we have decided to substitute X with another value, return that
469 value, otherwise return X. */
476 if (! REG_P (x
) || (regno
= REGNO (x
)) < FIRST_PSEUDO_REGISTER
477 || ! ira_reg_equiv
[regno
].defined_p
478 || ! ira_reg_equiv
[regno
].profitable_p
479 || lra_get_regno_hard_regno (regno
) >= 0)
481 if ((res
= ira_reg_equiv
[regno
].memory
) != NULL_RTX
)
483 if ((res
= ira_reg_equiv
[regno
].constant
) != NULL_RTX
)
485 if ((res
= ira_reg_equiv
[regno
].invariant
) != NULL_RTX
)
490 /* If we have decided to substitute X with the equivalent value,
491 return that value after elimination for INSN, otherwise return
494 get_equiv_with_elimination (rtx x
, rtx_insn
*insn
)
496 rtx res
= get_equiv (x
);
498 if (x
== res
|| CONSTANT_P (res
))
500 return lra_eliminate_regs_1 (insn
, res
, GET_MODE (res
), false, false, true);
503 /* Set up curr_operand_mode. */
505 init_curr_operand_mode (void)
507 int nop
= curr_static_id
->n_operands
;
508 for (int i
= 0; i
< nop
; i
++)
510 enum machine_mode mode
= GET_MODE (*curr_id
->operand_loc
[i
]);
511 if (mode
== VOIDmode
)
513 /* The .md mode for address operands is the mode of the
514 addressed value rather than the mode of the address itself. */
515 if (curr_id
->icode
>= 0 && curr_static_id
->operand
[i
].is_address
)
518 mode
= curr_static_id
->operand
[i
].mode
;
520 curr_operand_mode
[i
] = mode
;
526 /* The page contains code to reuse input reloads. */
528 /* Structure describes input reload of the current insns. */
531 /* Reloaded value. */
533 /* Reload pseudo used. */
537 /* The number of elements in the following array. */
538 static int curr_insn_input_reloads_num
;
539 /* Array containing info about input reloads. It is used to find the
540 same input reload and reuse the reload pseudo in this case. */
541 static struct input_reload curr_insn_input_reloads
[LRA_MAX_INSN_RELOADS
];
543 /* Initiate data concerning reuse of input reloads for the current
546 init_curr_insn_input_reloads (void)
548 curr_insn_input_reloads_num
= 0;
551 /* Create a new pseudo using MODE, RCLASS, ORIGINAL or reuse already
552 created input reload pseudo (only if TYPE is not OP_OUT). Don't
553 reuse pseudo if IN_SUBREG_P is true and the reused pseudo should be
554 wrapped up in SUBREG. The result pseudo is returned through
555 RESULT_REG. Return TRUE if we created a new pseudo, FALSE if we
556 reused the already created input reload pseudo. Use TITLE to
557 describe new registers for debug purposes. */
559 get_reload_reg (enum op_type type
, enum machine_mode mode
, rtx original
,
560 enum reg_class rclass
, bool in_subreg_p
,
561 const char *title
, rtx
*result_reg
)
564 enum reg_class new_class
;
569 = lra_create_new_reg_with_unique_value (mode
, original
, rclass
, title
);
572 /* Prevent reuse value of expression with side effects,
573 e.g. volatile memory. */
574 if (! side_effects_p (original
))
575 for (i
= 0; i
< curr_insn_input_reloads_num
; i
++)
576 if (rtx_equal_p (curr_insn_input_reloads
[i
].input
, original
)
577 && in_class_p (curr_insn_input_reloads
[i
].reg
, rclass
, &new_class
))
579 rtx reg
= curr_insn_input_reloads
[i
].reg
;
581 /* If input is equal to original and both are VOIDmode,
582 GET_MODE (reg) might be still different from mode.
583 Ensure we don't return *result_reg with wrong mode. */
584 if (GET_MODE (reg
) != mode
)
588 if (GET_MODE_SIZE (GET_MODE (reg
)) < GET_MODE_SIZE (mode
))
590 reg
= lowpart_subreg (mode
, reg
, GET_MODE (reg
));
591 if (reg
== NULL_RTX
|| GET_CODE (reg
) != SUBREG
)
595 if (lra_dump_file
!= NULL
)
597 fprintf (lra_dump_file
, " Reuse r%d for reload ", regno
);
598 dump_value_slim (lra_dump_file
, original
, 1);
600 if (new_class
!= lra_get_allocno_class (regno
))
601 lra_change_class (regno
, new_class
, ", change to", false);
602 if (lra_dump_file
!= NULL
)
603 fprintf (lra_dump_file
, "\n");
606 *result_reg
= lra_create_new_reg (mode
, original
, rclass
, title
);
607 lra_assert (curr_insn_input_reloads_num
< LRA_MAX_INSN_RELOADS
);
608 curr_insn_input_reloads
[curr_insn_input_reloads_num
].input
= original
;
609 curr_insn_input_reloads
[curr_insn_input_reloads_num
++].reg
= *result_reg
;
615 /* The page contains code to extract memory address parts. */
617 /* Wrapper around REGNO_OK_FOR_INDEX_P, to allow pseudos. */
619 ok_for_index_p_nonstrict (rtx reg
)
621 unsigned regno
= REGNO (reg
);
623 return regno
>= FIRST_PSEUDO_REGISTER
|| REGNO_OK_FOR_INDEX_P (regno
);
626 /* A version of regno_ok_for_base_p for use here, when all pseudos
627 should count as OK. Arguments as for regno_ok_for_base_p. */
629 ok_for_base_p_nonstrict (rtx reg
, enum machine_mode mode
, addr_space_t as
,
630 enum rtx_code outer_code
, enum rtx_code index_code
)
632 unsigned regno
= REGNO (reg
);
634 if (regno
>= FIRST_PSEUDO_REGISTER
)
636 return ok_for_base_p_1 (regno
, mode
, as
, outer_code
, index_code
);
641 /* The page contains major code to choose the current insn alternative
642 and generate reloads for it. */
644 /* Return the offset from REGNO of the least significant register
647 This function is used to tell whether two registers satisfy
648 a matching constraint. (reg:MODE1 REGNO1) matches (reg:MODE2 REGNO2) if:
650 REGNO1 + lra_constraint_offset (REGNO1, MODE1)
651 == REGNO2 + lra_constraint_offset (REGNO2, MODE2) */
653 lra_constraint_offset (int regno
, enum machine_mode mode
)
655 lra_assert (regno
< FIRST_PSEUDO_REGISTER
);
656 if (WORDS_BIG_ENDIAN
&& GET_MODE_SIZE (mode
) > UNITS_PER_WORD
657 && SCALAR_INT_MODE_P (mode
))
658 return hard_regno_nregs
[regno
][mode
] - 1;
662 /* Like rtx_equal_p except that it allows a REG and a SUBREG to match
663 if they are the same hard reg, and has special hacks for
664 auto-increment and auto-decrement. This is specifically intended for
665 process_alt_operands to use in determining whether two operands
666 match. X is the operand whose number is the lower of the two.
668 It is supposed that X is the output operand and Y is the input
669 operand. Y_HARD_REGNO is the final hard regno of register Y or
670 register in subreg Y as we know it now. Otherwise, it is a
673 operands_match_p (rtx x
, rtx y
, int y_hard_regno
)
676 RTX_CODE code
= GET_CODE (x
);
681 if ((code
== REG
|| (code
== SUBREG
&& REG_P (SUBREG_REG (x
))))
682 && (REG_P (y
) || (GET_CODE (y
) == SUBREG
&& REG_P (SUBREG_REG (y
)))))
686 i
= get_hard_regno (x
);
690 if ((j
= y_hard_regno
) < 0)
693 i
+= lra_constraint_offset (i
, GET_MODE (x
));
694 j
+= lra_constraint_offset (j
, GET_MODE (y
));
699 /* If two operands must match, because they are really a single
700 operand of an assembler insn, then two post-increments are invalid
701 because the assembler insn would increment only once. On the
702 other hand, a post-increment matches ordinary indexing if the
703 post-increment is the output operand. */
704 if (code
== POST_DEC
|| code
== POST_INC
|| code
== POST_MODIFY
)
705 return operands_match_p (XEXP (x
, 0), y
, y_hard_regno
);
707 /* Two pre-increments are invalid because the assembler insn would
708 increment only once. On the other hand, a pre-increment matches
709 ordinary indexing if the pre-increment is the input operand. */
710 if (GET_CODE (y
) == PRE_DEC
|| GET_CODE (y
) == PRE_INC
711 || GET_CODE (y
) == PRE_MODIFY
)
712 return operands_match_p (x
, XEXP (y
, 0), -1);
716 if (code
== REG
&& GET_CODE (y
) == SUBREG
&& REG_P (SUBREG_REG (y
))
717 && x
== SUBREG_REG (y
))
719 if (GET_CODE (y
) == REG
&& code
== SUBREG
&& REG_P (SUBREG_REG (x
))
720 && SUBREG_REG (x
) == y
)
723 /* Now we have disposed of all the cases in which different rtx
725 if (code
!= GET_CODE (y
))
728 /* (MULT:SI x y) and (MULT:HI x y) are NOT equivalent. */
729 if (GET_MODE (x
) != GET_MODE (y
))
738 return XEXP (x
, 0) == XEXP (y
, 0);
740 return XSTR (x
, 0) == XSTR (y
, 0);
746 /* Compare the elements. If any pair of corresponding elements fail
747 to match, return false for the whole things. */
749 fmt
= GET_RTX_FORMAT (code
);
750 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
756 if (XWINT (x
, i
) != XWINT (y
, i
))
761 if (XINT (x
, i
) != XINT (y
, i
))
766 val
= operands_match_p (XEXP (x
, i
), XEXP (y
, i
), -1);
775 if (XVECLEN (x
, i
) != XVECLEN (y
, i
))
777 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; --j
)
779 val
= operands_match_p (XVECEXP (x
, i
, j
), XVECEXP (y
, i
, j
), -1);
785 /* It is believed that rtx's at this level will never
786 contain anything but integers and other rtx's, except for
787 within LABEL_REFs and SYMBOL_REFs. */
795 /* True if X is a constant that can be forced into the constant pool.
796 MODE is the mode of the operand, or VOIDmode if not known. */
797 #define CONST_POOL_OK_P(MODE, X) \
798 ((MODE) != VOIDmode \
800 && GET_CODE (X) != HIGH \
801 && !targetm.cannot_force_const_mem (MODE, X))
803 /* True if C is a non-empty register class that has too few registers
804 to be safely used as a reload target class. */
805 #define SMALL_REGISTER_CLASS_P(C) \
806 (ira_class_hard_regs_num [(C)] == 1 \
807 || (ira_class_hard_regs_num [(C)] >= 1 \
808 && targetm.class_likely_spilled_p (C)))
810 /* If REG is a reload pseudo, try to make its class satisfying CL. */
812 narrow_reload_pseudo_class (rtx reg
, enum reg_class cl
)
814 enum reg_class rclass
;
816 /* Do not make more accurate class from reloads generated. They are
817 mostly moves with a lot of constraints. Making more accurate
818 class may results in very narrow class and impossibility of find
819 registers for several reloads of one insn. */
820 if (INSN_UID (curr_insn
) >= new_insn_uid_start
)
822 if (GET_CODE (reg
) == SUBREG
)
823 reg
= SUBREG_REG (reg
);
824 if (! REG_P (reg
) || (int) REGNO (reg
) < new_regno_start
)
826 if (in_class_p (reg
, cl
, &rclass
) && rclass
!= cl
)
827 lra_change_class (REGNO (reg
), rclass
, " Change to", true);
830 /* Generate reloads for matching OUT and INS (array of input operand
831 numbers with end marker -1) with reg class GOAL_CLASS. Add input
832 and output reloads correspondingly to the lists *BEFORE and *AFTER.
833 OUT might be negative. In this case we generate input reloads for
834 matched input operands INS. */
836 match_reload (signed char out
, signed char *ins
, enum reg_class goal_class
,
837 rtx_insn
**before
, rtx_insn
**after
)
840 rtx new_in_reg
, new_out_reg
, reg
, clobber
;
841 enum machine_mode inmode
, outmode
;
842 rtx in_rtx
= *curr_id
->operand_loc
[ins
[0]];
843 rtx out_rtx
= out
< 0 ? in_rtx
: *curr_id
->operand_loc
[out
];
845 inmode
= curr_operand_mode
[ins
[0]];
846 outmode
= out
< 0 ? inmode
: curr_operand_mode
[out
];
847 push_to_sequence (*before
);
848 if (inmode
!= outmode
)
850 if (GET_MODE_SIZE (inmode
) > GET_MODE_SIZE (outmode
))
853 = lra_create_new_reg_with_unique_value (inmode
, in_rtx
,
855 if (SCALAR_INT_MODE_P (inmode
))
856 new_out_reg
= gen_lowpart_SUBREG (outmode
, reg
);
858 new_out_reg
= gen_rtx_SUBREG (outmode
, reg
, 0);
859 LRA_SUBREG_P (new_out_reg
) = 1;
860 /* If the input reg is dying here, we can use the same hard
861 register for REG and IN_RTX. We do it only for original
862 pseudos as reload pseudos can die although original
863 pseudos still live where reload pseudos dies. */
864 if (REG_P (in_rtx
) && (int) REGNO (in_rtx
) < lra_new_regno_start
865 && find_regno_note (curr_insn
, REG_DEAD
, REGNO (in_rtx
)))
866 lra_assign_reg_val (REGNO (in_rtx
), REGNO (reg
));
871 = lra_create_new_reg_with_unique_value (outmode
, out_rtx
,
873 if (SCALAR_INT_MODE_P (outmode
))
874 new_in_reg
= gen_lowpart_SUBREG (inmode
, reg
);
876 new_in_reg
= gen_rtx_SUBREG (inmode
, reg
, 0);
877 /* NEW_IN_REG is non-paradoxical subreg. We don't want
878 NEW_OUT_REG living above. We add clobber clause for
879 this. This is just a temporary clobber. We can remove
880 it at the end of LRA work. */
881 clobber
= emit_clobber (new_out_reg
);
882 LRA_TEMP_CLOBBER_P (PATTERN (clobber
)) = 1;
883 LRA_SUBREG_P (new_in_reg
) = 1;
884 if (GET_CODE (in_rtx
) == SUBREG
)
886 rtx subreg_reg
= SUBREG_REG (in_rtx
);
888 /* If SUBREG_REG is dying here and sub-registers IN_RTX
889 and NEW_IN_REG are similar, we can use the same hard
890 register for REG and SUBREG_REG. */
891 if (REG_P (subreg_reg
)
892 && (int) REGNO (subreg_reg
) < lra_new_regno_start
893 && GET_MODE (subreg_reg
) == outmode
894 && SUBREG_BYTE (in_rtx
) == SUBREG_BYTE (new_in_reg
)
895 && find_regno_note (curr_insn
, REG_DEAD
, REGNO (subreg_reg
)))
896 lra_assign_reg_val (REGNO (subreg_reg
), REGNO (reg
));
902 /* Pseudos have values -- see comments for lra_reg_info.
903 Different pseudos with the same value do not conflict even if
904 they live in the same place. When we create a pseudo we
905 assign value of original pseudo (if any) from which we
906 created the new pseudo. If we create the pseudo from the
907 input pseudo, the new pseudo will no conflict with the input
908 pseudo which is wrong when the input pseudo lives after the
909 insn and as the new pseudo value is changed by the insn
910 output. Therefore we create the new pseudo from the output.
912 We cannot reuse the current output register because we might
913 have a situation like "a <- a op b", where the constraints
914 force the second input operand ("b") to match the output
915 operand ("a"). "b" must then be copied into a new register
916 so that it doesn't clobber the current value of "a". */
918 new_in_reg
= new_out_reg
919 = lra_create_new_reg_with_unique_value (outmode
, out_rtx
,
922 /* In operand can be got from transformations before processing insn
923 constraints. One example of such transformations is subreg
924 reloading (see function simplify_operand_subreg). The new
925 pseudos created by the transformations might have inaccurate
926 class (ALL_REGS) and we should make their classes more
928 narrow_reload_pseudo_class (in_rtx
, goal_class
);
929 lra_emit_move (copy_rtx (new_in_reg
), in_rtx
);
930 *before
= get_insns ();
932 for (i
= 0; (in
= ins
[i
]) >= 0; i
++)
935 (GET_MODE (*curr_id
->operand_loc
[in
]) == VOIDmode
936 || GET_MODE (new_in_reg
) == GET_MODE (*curr_id
->operand_loc
[in
]));
937 *curr_id
->operand_loc
[in
] = new_in_reg
;
939 lra_update_dups (curr_id
, ins
);
942 /* See a comment for the input operand above. */
943 narrow_reload_pseudo_class (out_rtx
, goal_class
);
944 if (find_reg_note (curr_insn
, REG_UNUSED
, out_rtx
) == NULL_RTX
)
947 lra_emit_move (out_rtx
, copy_rtx (new_out_reg
));
949 *after
= get_insns ();
952 *curr_id
->operand_loc
[out
] = new_out_reg
;
953 lra_update_dup (curr_id
, out
);
956 /* Return register class which is union of all reg classes in insn
957 constraint alternative string starting with P. */
958 static enum reg_class
959 reg_class_from_constraints (const char *p
)
962 enum reg_class op_class
= NO_REGS
;
965 switch ((c
= *p
, len
= CONSTRAINT_LEN (c
, p
)), c
)
972 op_class
= reg_class_subunion
[op_class
][GENERAL_REGS
];
976 enum constraint_num cn
= lookup_constraint (p
);
977 enum reg_class cl
= reg_class_for_constraint (cn
);
980 if (insn_extra_address_constraint (cn
))
982 = (reg_class_subunion
983 [op_class
][base_reg_class (VOIDmode
, ADDR_SPACE_GENERIC
,
988 op_class
= reg_class_subunion
[op_class
][cl
];
991 while ((p
+= len
), c
);
995 /* If OP is a register, return the class of the register as per
996 get_reg_class, otherwise return NO_REGS. */
997 static inline enum reg_class
998 get_op_class (rtx op
)
1000 return REG_P (op
) ? get_reg_class (REGNO (op
)) : NO_REGS
;
1003 /* Return generated insn mem_pseudo:=val if TO_P or val:=mem_pseudo
1004 otherwise. If modes of MEM_PSEUDO and VAL are different, use
1005 SUBREG for VAL to make them equal. */
1007 emit_spill_move (bool to_p
, rtx mem_pseudo
, rtx val
)
1009 if (GET_MODE (mem_pseudo
) != GET_MODE (val
))
1011 /* Usually size of mem_pseudo is greater than val size but in
1012 rare cases it can be less as it can be defined by target
1013 dependent macro HARD_REGNO_CALLER_SAVE_MODE. */
1016 val
= gen_rtx_SUBREG (GET_MODE (mem_pseudo
),
1017 GET_CODE (val
) == SUBREG
? SUBREG_REG (val
) : val
,
1019 LRA_SUBREG_P (val
) = 1;
1023 mem_pseudo
= gen_lowpart_SUBREG (GET_MODE (val
), mem_pseudo
);
1024 LRA_SUBREG_P (mem_pseudo
) = 1;
1027 return as_a
<rtx_insn
*> (to_p
1028 ? gen_move_insn (mem_pseudo
, val
)
1029 : gen_move_insn (val
, mem_pseudo
));
1032 /* Process a special case insn (register move), return true if we
1033 don't need to process it anymore. INSN should be a single set
1034 insn. Set up that RTL was changed through CHANGE_P and macro
1035 SECONDARY_MEMORY_NEEDED says to use secondary memory through
1038 check_and_process_move (bool *change_p
, bool *sec_mem_p ATTRIBUTE_UNUSED
)
1041 rtx dest
, src
, dreg
, sreg
, old_sreg
, new_reg
, scratch_reg
;
1043 enum reg_class dclass
, sclass
, secondary_class
;
1044 enum machine_mode sreg_mode
;
1045 secondary_reload_info sri
;
1047 lra_assert (curr_insn_set
!= NULL_RTX
);
1048 dreg
= dest
= SET_DEST (curr_insn_set
);
1049 sreg
= src
= SET_SRC (curr_insn_set
);
1050 if (GET_CODE (dest
) == SUBREG
)
1051 dreg
= SUBREG_REG (dest
);
1052 if (GET_CODE (src
) == SUBREG
)
1053 sreg
= SUBREG_REG (src
);
1054 if (! (REG_P (dreg
) || MEM_P (dreg
)) || ! (REG_P (sreg
) || MEM_P (sreg
)))
1056 sclass
= dclass
= NO_REGS
;
1058 dclass
= get_reg_class (REGNO (dreg
));
1059 if (dclass
== ALL_REGS
)
1060 /* ALL_REGS is used for new pseudos created by transformations
1061 like reload of SUBREG_REG (see function
1062 simplify_operand_subreg). We don't know their class yet. We
1063 should figure out the class from processing the insn
1064 constraints not in this fast path function. Even if ALL_REGS
1065 were a right class for the pseudo, secondary_... hooks usually
1066 are not define for ALL_REGS. */
1068 sreg_mode
= GET_MODE (sreg
);
1071 sclass
= get_reg_class (REGNO (sreg
));
1072 if (sclass
== ALL_REGS
)
1073 /* See comments above. */
1075 if (sclass
== NO_REGS
&& dclass
== NO_REGS
)
1077 #ifdef SECONDARY_MEMORY_NEEDED
1078 if (SECONDARY_MEMORY_NEEDED (sclass
, dclass
, GET_MODE (src
))
1079 #ifdef SECONDARY_MEMORY_NEEDED_MODE
1080 && ((sclass
!= NO_REGS
&& dclass
!= NO_REGS
)
1081 || GET_MODE (src
) != SECONDARY_MEMORY_NEEDED_MODE (GET_MODE (src
)))
1089 if (! REG_P (dreg
) || ! REG_P (sreg
))
1091 sri
.prev_sri
= NULL
;
1092 sri
.icode
= CODE_FOR_nothing
;
1094 secondary_class
= NO_REGS
;
1095 /* Set up hard register for a reload pseudo for hook
1096 secondary_reload because some targets just ignore unassigned
1097 pseudos in the hook. */
1098 if (dclass
!= NO_REGS
&& lra_get_regno_hard_regno (REGNO (dreg
)) < 0)
1100 dregno
= REGNO (dreg
);
1101 reg_renumber
[dregno
] = ira_class_hard_regs
[dclass
][0];
1105 if (sclass
!= NO_REGS
&& lra_get_regno_hard_regno (REGNO (sreg
)) < 0)
1107 sregno
= REGNO (sreg
);
1108 reg_renumber
[sregno
] = ira_class_hard_regs
[sclass
][0];
1112 if (sclass
!= NO_REGS
)
1114 = (enum reg_class
) targetm
.secondary_reload (false, dest
,
1115 (reg_class_t
) sclass
,
1116 GET_MODE (src
), &sri
);
1117 if (sclass
== NO_REGS
1118 || ((secondary_class
!= NO_REGS
|| sri
.icode
!= CODE_FOR_nothing
)
1119 && dclass
!= NO_REGS
))
1121 enum reg_class old_sclass
= secondary_class
;
1122 secondary_reload_info old_sri
= sri
;
1124 sri
.prev_sri
= NULL
;
1125 sri
.icode
= CODE_FOR_nothing
;
1128 = (enum reg_class
) targetm
.secondary_reload (true, sreg
,
1129 (reg_class_t
) dclass
,
1131 /* Check the target hook consistency. */
1133 ((secondary_class
== NO_REGS
&& sri
.icode
== CODE_FOR_nothing
)
1134 || (old_sclass
== NO_REGS
&& old_sri
.icode
== CODE_FOR_nothing
)
1135 || (secondary_class
== old_sclass
&& sri
.icode
== old_sri
.icode
));
1138 reg_renumber
[sregno
] = -1;
1140 reg_renumber
[dregno
] = -1;
1141 if (secondary_class
== NO_REGS
&& sri
.icode
== CODE_FOR_nothing
)
1145 if (secondary_class
!= NO_REGS
)
1146 new_reg
= lra_create_new_reg_with_unique_value (sreg_mode
, NULL_RTX
,
1150 if (old_sreg
!= sreg
)
1151 sreg
= copy_rtx (sreg
);
1152 if (sri
.icode
== CODE_FOR_nothing
)
1153 lra_emit_move (new_reg
, sreg
);
1156 enum reg_class scratch_class
;
1158 scratch_class
= (reg_class_from_constraints
1159 (insn_data
[sri
.icode
].operand
[2].constraint
));
1160 scratch_reg
= (lra_create_new_reg_with_unique_value
1161 (insn_data
[sri
.icode
].operand
[2].mode
, NULL_RTX
,
1162 scratch_class
, "scratch"));
1163 emit_insn (GEN_FCN (sri
.icode
) (new_reg
!= NULL_RTX
? new_reg
: dest
,
1164 sreg
, scratch_reg
));
1166 before
= get_insns ();
1168 lra_process_new_insns (curr_insn
, before
, NULL
, "Inserting the move");
1169 if (new_reg
!= NULL_RTX
)
1171 if (GET_CODE (src
) == SUBREG
)
1172 SUBREG_REG (src
) = new_reg
;
1174 SET_SRC (curr_insn_set
) = new_reg
;
1178 if (lra_dump_file
!= NULL
)
1180 fprintf (lra_dump_file
, "Deleting move %u\n", INSN_UID (curr_insn
));
1181 dump_insn_slim (lra_dump_file
, curr_insn
);
1183 lra_set_insn_deleted (curr_insn
);
1189 /* The following data describe the result of process_alt_operands.
1190 The data are used in curr_insn_transform to generate reloads. */
1192 /* The chosen reg classes which should be used for the corresponding
1194 static enum reg_class goal_alt
[MAX_RECOG_OPERANDS
];
1195 /* True if the operand should be the same as another operand and that
1196 other operand does not need a reload. */
1197 static bool goal_alt_match_win
[MAX_RECOG_OPERANDS
];
1198 /* True if the operand does not need a reload. */
1199 static bool goal_alt_win
[MAX_RECOG_OPERANDS
];
1200 /* True if the operand can be offsetable memory. */
1201 static bool goal_alt_offmemok
[MAX_RECOG_OPERANDS
];
1202 /* The number of an operand to which given operand can be matched to. */
1203 static int goal_alt_matches
[MAX_RECOG_OPERANDS
];
1204 /* The number of elements in the following array. */
1205 static int goal_alt_dont_inherit_ops_num
;
1206 /* Numbers of operands whose reload pseudos should not be inherited. */
1207 static int goal_alt_dont_inherit_ops
[MAX_RECOG_OPERANDS
];
1208 /* True if the insn commutative operands should be swapped. */
1209 static bool goal_alt_swapped
;
1210 /* The chosen insn alternative. */
1211 static int goal_alt_number
;
1213 /* The following five variables are used to choose the best insn
1214 alternative. They reflect final characteristics of the best
1217 /* Number of necessary reloads and overall cost reflecting the
1218 previous value and other unpleasantness of the best alternative. */
1219 static int best_losers
, best_overall
;
1220 /* Overall number hard registers used for reloads. For example, on
1221 some targets we need 2 general registers to reload DFmode and only
1222 one floating point register. */
1223 static int best_reload_nregs
;
1224 /* Overall number reflecting distances of previous reloading the same
1225 value. The distances are counted from the current BB start. It is
1226 used to improve inheritance chances. */
1227 static int best_reload_sum
;
1229 /* True if the current insn should have no correspondingly input or
1231 static bool no_input_reloads_p
, no_output_reloads_p
;
1233 /* True if we swapped the commutative operands in the current
1235 static int curr_swapped
;
1237 /* Arrange for address element *LOC to be a register of class CL.
1238 Add any input reloads to list BEFORE. AFTER is nonnull if *LOC is an
1239 automodified value; handle that case by adding the required output
1240 reloads to list AFTER. Return true if the RTL was changed. */
1242 process_addr_reg (rtx
*loc
, rtx_insn
**before
, rtx_insn
**after
,
1246 enum reg_class rclass
, new_class
;
1249 enum machine_mode mode
;
1250 bool subreg_p
, before_p
= false;
1252 subreg_p
= GET_CODE (*loc
) == SUBREG
;
1254 loc
= &SUBREG_REG (*loc
);
1256 mode
= GET_MODE (reg
);
1259 /* Always reload memory in an address even if the target supports
1261 new_reg
= lra_create_new_reg_with_unique_value (mode
, reg
, cl
, "address");
1266 regno
= REGNO (reg
);
1267 rclass
= get_reg_class (regno
);
1268 if ((*loc
= get_equiv_with_elimination (reg
, curr_insn
)) != reg
)
1270 if (lra_dump_file
!= NULL
)
1272 fprintf (lra_dump_file
,
1273 "Changing pseudo %d in address of insn %u on equiv ",
1274 REGNO (reg
), INSN_UID (curr_insn
));
1275 dump_value_slim (lra_dump_file
, *loc
, 1);
1276 fprintf (lra_dump_file
, "\n");
1278 *loc
= copy_rtx (*loc
);
1280 if (*loc
!= reg
|| ! in_class_p (reg
, cl
, &new_class
))
1283 if (get_reload_reg (after
== NULL
? OP_IN
: OP_INOUT
,
1284 mode
, reg
, cl
, subreg_p
, "address", &new_reg
))
1287 else if (new_class
!= NO_REGS
&& rclass
!= new_class
)
1289 lra_change_class (regno
, new_class
, " Change to", true);
1297 push_to_sequence (*before
);
1298 lra_emit_move (new_reg
, reg
);
1299 *before
= get_insns ();
1306 lra_emit_move (reg
, new_reg
);
1308 *after
= get_insns ();
1314 /* Insert move insn in simplify_operand_subreg. BEFORE returns
1315 the insn to be inserted before curr insn. AFTER returns the
1316 the insn to be inserted after curr insn. ORIGREG and NEWREG
1317 are the original reg and new reg for reload. */
1319 insert_move_for_subreg (rtx_insn
**before
, rtx_insn
**after
, rtx origreg
,
1324 push_to_sequence (*before
);
1325 lra_emit_move (newreg
, origreg
);
1326 *before
= get_insns ();
1332 lra_emit_move (origreg
, newreg
);
1334 *after
= get_insns ();
1339 static int valid_address_p (enum machine_mode mode
, rtx addr
, addr_space_t as
);
1341 /* Make reloads for subreg in operand NOP with internal subreg mode
1342 REG_MODE, add new reloads for further processing. Return true if
1343 any reload was generated. */
1345 simplify_operand_subreg (int nop
, enum machine_mode reg_mode
)
1348 rtx_insn
*before
, *after
;
1349 enum machine_mode mode
;
1351 rtx operand
= *curr_id
->operand_loc
[nop
];
1352 enum reg_class regclass
;
1355 before
= after
= NULL
;
1357 if (GET_CODE (operand
) != SUBREG
)
1360 mode
= GET_MODE (operand
);
1361 reg
= SUBREG_REG (operand
);
1362 type
= curr_static_id
->operand
[nop
].type
;
1363 /* If we change address for paradoxical subreg of memory, the
1364 address might violate the necessary alignment or the access might
1365 be slow. So take this into consideration. We should not worry
1366 about access beyond allocated memory for paradoxical memory
1367 subregs as we don't substitute such equiv memory (see processing
1368 equivalences in function lra_constraints) and because for spilled
1369 pseudos we allocate stack memory enough for the biggest
1370 corresponding paradoxical subreg. */
1372 && (! SLOW_UNALIGNED_ACCESS (mode
, MEM_ALIGN (reg
))
1373 || MEM_ALIGN (reg
) >= GET_MODE_ALIGNMENT (mode
)))
1375 rtx subst
, old
= *curr_id
->operand_loc
[nop
];
1377 alter_subreg (curr_id
->operand_loc
[nop
], false);
1378 subst
= *curr_id
->operand_loc
[nop
];
1379 lra_assert (MEM_P (subst
));
1380 if (! valid_address_p (GET_MODE (reg
), XEXP (reg
, 0),
1381 MEM_ADDR_SPACE (reg
))
1382 || valid_address_p (GET_MODE (subst
), XEXP (subst
, 0),
1383 MEM_ADDR_SPACE (subst
)))
1385 /* If the address was valid and became invalid, prefer to reload
1386 the memory. Typical case is when the index scale should
1387 correspond the memory. */
1388 *curr_id
->operand_loc
[nop
] = old
;
1390 else if (REG_P (reg
) && REGNO (reg
) < FIRST_PSEUDO_REGISTER
)
1392 alter_subreg (curr_id
->operand_loc
[nop
], false);
1395 /* Put constant into memory when we have mixed modes. It generates
1396 a better code in most cases as it does not need a secondary
1397 reload memory. It also prevents LRA looping when LRA is using
1398 secondary reload memory again and again. */
1399 if (CONSTANT_P (reg
) && CONST_POOL_OK_P (reg_mode
, reg
)
1400 && SCALAR_INT_MODE_P (reg_mode
) != SCALAR_INT_MODE_P (mode
))
1402 SUBREG_REG (operand
) = force_const_mem (reg_mode
, reg
);
1403 alter_subreg (curr_id
->operand_loc
[nop
], false);
1406 /* Force a reload of the SUBREG_REG if this is a constant or PLUS or
1407 if there may be a problem accessing OPERAND in the outer
1410 && REGNO (reg
) >= FIRST_PSEUDO_REGISTER
1411 && (hard_regno
= lra_get_regno_hard_regno (REGNO (reg
))) >= 0
1412 /* Don't reload paradoxical subregs because we could be looping
1413 having repeatedly final regno out of hard regs range. */
1414 && (hard_regno_nregs
[hard_regno
][GET_MODE (reg
)]
1415 >= hard_regno_nregs
[hard_regno
][mode
])
1416 && simplify_subreg_regno (hard_regno
, GET_MODE (reg
),
1417 SUBREG_BYTE (operand
), mode
) < 0
1418 /* Don't reload subreg for matching reload. It is actually
1419 valid subreg in LRA. */
1420 && ! LRA_SUBREG_P (operand
))
1421 || CONSTANT_P (reg
) || GET_CODE (reg
) == PLUS
|| MEM_P (reg
))
1423 enum reg_class rclass
;
1426 /* There is a big probability that we will get the same class
1427 for the new pseudo and we will get the same insn which
1428 means infinite looping. So spill the new pseudo. */
1431 /* The class will be defined later in curr_insn_transform. */
1433 = (enum reg_class
) targetm
.preferred_reload_class (reg
, ALL_REGS
);
1435 if (get_reload_reg (curr_static_id
->operand
[nop
].type
, reg_mode
, reg
,
1436 rclass
, TRUE
, "subreg reg", &new_reg
))
1438 bool insert_before
, insert_after
;
1439 bitmap_set_bit (&lra_subreg_reload_pseudos
, REGNO (new_reg
));
1441 insert_before
= (type
!= OP_OUT
1442 || GET_MODE_SIZE (GET_MODE (reg
)) > GET_MODE_SIZE (mode
));
1443 insert_after
= (type
!= OP_IN
);
1444 insert_move_for_subreg (insert_before
? &before
: NULL
,
1445 insert_after
? &after
: NULL
,
1448 SUBREG_REG (operand
) = new_reg
;
1449 lra_process_new_insns (curr_insn
, before
, after
,
1450 "Inserting subreg reload");
1453 /* Force a reload for a paradoxical subreg. For paradoxical subreg,
1454 IRA allocates hardreg to the inner pseudo reg according to its mode
1455 instead of the outermode, so the size of the hardreg may not be enough
1456 to contain the outermode operand, in that case we may need to insert
1457 reload for the reg. For the following two types of paradoxical subreg,
1458 we need to insert reload:
1459 1. If the op_type is OP_IN, and the hardreg could not be paired with
1460 other hardreg to contain the outermode operand
1461 (checked by in_hard_reg_set_p), we need to insert the reload.
1462 2. If the op_type is OP_OUT or OP_INOUT.
1464 Here is a paradoxical subreg example showing how the reload is generated:
1466 (insn 5 4 7 2 (set (reg:TI 106 [ __comp ])
1467 (subreg:TI (reg:DI 107 [ __comp ]) 0)) {*movti_internal_rex64}
1469 In IRA, reg107 is allocated to a DImode hardreg. We use x86-64 as example
1470 here, if reg107 is assigned to hardreg R15, because R15 is the last
1471 hardreg, compiler cannot find another hardreg to pair with R15 to
1472 contain TImode data. So we insert a TImode reload reg180 for it.
1473 After reload is inserted:
1475 (insn 283 0 0 (set (subreg:DI (reg:TI 180 [orig:107 __comp ] [107]) 0)
1476 (reg:DI 107 [ __comp ])) -1
1477 (insn 5 4 7 2 (set (reg:TI 106 [ __comp ])
1478 (subreg:TI (reg:TI 180 [orig:107 __comp ] [107]) 0)) {*movti_internal_rex64}
1480 Two reload hard registers will be allocated to reg180 to save TImode data
1482 else if (REG_P (reg
)
1483 && REGNO (reg
) >= FIRST_PSEUDO_REGISTER
1484 && (hard_regno
= lra_get_regno_hard_regno (REGNO (reg
))) >= 0
1485 && (hard_regno_nregs
[hard_regno
][GET_MODE (reg
)]
1486 < hard_regno_nregs
[hard_regno
][mode
])
1487 && (regclass
= lra_get_allocno_class (REGNO (reg
)))
1489 || !in_hard_reg_set_p (reg_class_contents
[regclass
],
1492 /* The class will be defined later in curr_insn_transform. */
1493 enum reg_class rclass
1494 = (enum reg_class
) targetm
.preferred_reload_class (reg
, ALL_REGS
);
1496 if (get_reload_reg (curr_static_id
->operand
[nop
].type
, mode
, reg
,
1497 rclass
, TRUE
, "paradoxical subreg", &new_reg
))
1500 bool insert_before
, insert_after
;
1502 PUT_MODE (new_reg
, mode
);
1503 subreg
= simplify_gen_subreg (GET_MODE (reg
), new_reg
, mode
, 0);
1504 bitmap_set_bit (&lra_subreg_reload_pseudos
, REGNO (new_reg
));
1506 insert_before
= (type
!= OP_OUT
);
1507 insert_after
= (type
!= OP_IN
);
1508 insert_move_for_subreg (insert_before
? &before
: NULL
,
1509 insert_after
? &after
: NULL
,
1512 SUBREG_REG (operand
) = new_reg
;
1513 lra_process_new_insns (curr_insn
, before
, after
,
1514 "Inserting paradoxical subreg reload");
1520 /* Return TRUE if X refers for a hard register from SET. */
1522 uses_hard_regs_p (rtx x
, HARD_REG_SET set
)
1524 int i
, j
, x_hard_regno
;
1525 enum machine_mode mode
;
1531 code
= GET_CODE (x
);
1532 mode
= GET_MODE (x
);
1536 code
= GET_CODE (x
);
1537 if (GET_MODE_SIZE (GET_MODE (x
)) > GET_MODE_SIZE (mode
))
1538 mode
= GET_MODE (x
);
1543 x_hard_regno
= get_hard_regno (x
);
1544 return (x_hard_regno
>= 0
1545 && overlaps_hard_reg_set_p (set
, mode
, x_hard_regno
));
1549 struct address_info ad
;
1551 decompose_mem_address (&ad
, x
);
1552 if (ad
.base_term
!= NULL
&& uses_hard_regs_p (*ad
.base_term
, set
))
1554 if (ad
.index_term
!= NULL
&& uses_hard_regs_p (*ad
.index_term
, set
))
1557 fmt
= GET_RTX_FORMAT (code
);
1558 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
1562 if (uses_hard_regs_p (XEXP (x
, i
), set
))
1565 else if (fmt
[i
] == 'E')
1567 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
1568 if (uses_hard_regs_p (XVECEXP (x
, i
, j
), set
))
1575 /* Return true if OP is a spilled pseudo. */
1577 spilled_pseudo_p (rtx op
)
1580 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
&& in_mem_p (REGNO (op
)));
1583 /* Return true if X is a general constant. */
1585 general_constant_p (rtx x
)
1587 return CONSTANT_P (x
) && (! flag_pic
|| LEGITIMATE_PIC_OPERAND_P (x
));
1591 reg_in_class_p (rtx reg
, enum reg_class cl
)
1594 return get_reg_class (REGNO (reg
)) == NO_REGS
;
1595 return in_class_p (reg
, cl
, NULL
);
1598 /* Major function to choose the current insn alternative and what
1599 operands should be reloaded and how. If ONLY_ALTERNATIVE is not
1600 negative we should consider only this alternative. Return false if
1601 we can not choose the alternative or find how to reload the
1604 process_alt_operands (int only_alternative
)
1607 int nop
, overall
, nalt
;
1608 int n_alternatives
= curr_static_id
->n_alternatives
;
1609 int n_operands
= curr_static_id
->n_operands
;
1610 /* LOSERS counts the operands that don't fit this alternative and
1611 would require loading. */
1613 /* REJECT is a count of how undesirable this alternative says it is
1614 if any reloading is required. If the alternative matches exactly
1615 then REJECT is ignored, but otherwise it gets this much counted
1616 against it in addition to the reloading needed. */
1618 /* The number of elements in the following array. */
1619 int early_clobbered_regs_num
;
1620 /* Numbers of operands which are early clobber registers. */
1621 int early_clobbered_nops
[MAX_RECOG_OPERANDS
];
1622 enum reg_class curr_alt
[MAX_RECOG_OPERANDS
];
1623 HARD_REG_SET curr_alt_set
[MAX_RECOG_OPERANDS
];
1624 bool curr_alt_match_win
[MAX_RECOG_OPERANDS
];
1625 bool curr_alt_win
[MAX_RECOG_OPERANDS
];
1626 bool curr_alt_offmemok
[MAX_RECOG_OPERANDS
];
1627 int curr_alt_matches
[MAX_RECOG_OPERANDS
];
1628 /* The number of elements in the following array. */
1629 int curr_alt_dont_inherit_ops_num
;
1630 /* Numbers of operands whose reload pseudos should not be inherited. */
1631 int curr_alt_dont_inherit_ops
[MAX_RECOG_OPERANDS
];
1633 /* The register when the operand is a subreg of register, otherwise the
1635 rtx no_subreg_reg_operand
[MAX_RECOG_OPERANDS
];
1636 /* The register if the operand is a register or subreg of register,
1638 rtx operand_reg
[MAX_RECOG_OPERANDS
];
1639 int hard_regno
[MAX_RECOG_OPERANDS
];
1640 enum machine_mode biggest_mode
[MAX_RECOG_OPERANDS
];
1641 int reload_nregs
, reload_sum
;
1645 /* Calculate some data common for all alternatives to speed up the
1647 for (nop
= 0; nop
< n_operands
; nop
++)
1651 op
= no_subreg_reg_operand
[nop
] = *curr_id
->operand_loc
[nop
];
1652 /* The real hard regno of the operand after the allocation. */
1653 hard_regno
[nop
] = get_hard_regno (op
);
1655 operand_reg
[nop
] = reg
= op
;
1656 biggest_mode
[nop
] = GET_MODE (op
);
1657 if (GET_CODE (op
) == SUBREG
)
1659 operand_reg
[nop
] = reg
= SUBREG_REG (op
);
1660 if (GET_MODE_SIZE (biggest_mode
[nop
])
1661 < GET_MODE_SIZE (GET_MODE (reg
)))
1662 biggest_mode
[nop
] = GET_MODE (reg
);
1665 operand_reg
[nop
] = NULL_RTX
;
1666 else if (REGNO (reg
) >= FIRST_PSEUDO_REGISTER
1667 || ((int) REGNO (reg
)
1668 == lra_get_elimination_hard_regno (REGNO (reg
))))
1669 no_subreg_reg_operand
[nop
] = reg
;
1671 operand_reg
[nop
] = no_subreg_reg_operand
[nop
]
1672 /* Just use natural mode for elimination result. It should
1673 be enough for extra constraints hooks. */
1674 = regno_reg_rtx
[hard_regno
[nop
]];
1677 /* The constraints are made of several alternatives. Each operand's
1678 constraint looks like foo,bar,... with commas separating the
1679 alternatives. The first alternatives for all operands go
1680 together, the second alternatives go together, etc.
1682 First loop over alternatives. */
1683 alternative_mask enabled
= curr_id
->enabled_alternatives
;
1684 if (only_alternative
>= 0)
1685 enabled
&= ALTERNATIVE_BIT (only_alternative
);
1687 for (nalt
= 0; nalt
< n_alternatives
; nalt
++)
1689 /* Loop over operands for one constraint alternative. */
1690 if (!TEST_BIT (enabled
, nalt
))
1693 overall
= losers
= reject
= reload_nregs
= reload_sum
= 0;
1694 for (nop
= 0; nop
< n_operands
; nop
++)
1696 int inc
= (curr_static_id
1697 ->operand_alternative
[nalt
* n_operands
+ nop
].reject
);
1698 if (lra_dump_file
!= NULL
&& inc
!= 0)
1699 fprintf (lra_dump_file
,
1700 " Staticly defined alt reject+=%d\n", inc
);
1703 early_clobbered_regs_num
= 0;
1705 for (nop
= 0; nop
< n_operands
; nop
++)
1709 int len
, c
, m
, i
, opalt_num
, this_alternative_matches
;
1710 bool win
, did_match
, offmemok
, early_clobber_p
;
1711 /* false => this operand can be reloaded somehow for this
1714 /* true => this operand can be reloaded if the alternative
1717 /* True if a constant forced into memory would be OK for
1720 enum reg_class this_alternative
, this_costly_alternative
;
1721 HARD_REG_SET this_alternative_set
, this_costly_alternative_set
;
1722 bool this_alternative_match_win
, this_alternative_win
;
1723 bool this_alternative_offmemok
;
1725 enum machine_mode mode
;
1726 enum constraint_num cn
;
1728 opalt_num
= nalt
* n_operands
+ nop
;
1729 if (curr_static_id
->operand_alternative
[opalt_num
].anything_ok
)
1731 /* Fast track for no constraints at all. */
1732 curr_alt
[nop
] = NO_REGS
;
1733 CLEAR_HARD_REG_SET (curr_alt_set
[nop
]);
1734 curr_alt_win
[nop
] = true;
1735 curr_alt_match_win
[nop
] = false;
1736 curr_alt_offmemok
[nop
] = false;
1737 curr_alt_matches
[nop
] = -1;
1741 op
= no_subreg_reg_operand
[nop
];
1742 mode
= curr_operand_mode
[nop
];
1744 win
= did_match
= winreg
= offmemok
= constmemok
= false;
1747 early_clobber_p
= false;
1748 p
= curr_static_id
->operand_alternative
[opalt_num
].constraint
;
1750 this_costly_alternative
= this_alternative
= NO_REGS
;
1751 /* We update set of possible hard regs besides its class
1752 because reg class might be inaccurate. For example,
1753 union of LO_REGS (l), HI_REGS(h), and STACK_REG(k) in ARM
1754 is translated in HI_REGS because classes are merged by
1755 pairs and there is no accurate intermediate class. */
1756 CLEAR_HARD_REG_SET (this_alternative_set
);
1757 CLEAR_HARD_REG_SET (this_costly_alternative_set
);
1758 this_alternative_win
= false;
1759 this_alternative_match_win
= false;
1760 this_alternative_offmemok
= false;
1761 this_alternative_matches
= -1;
1763 /* An empty constraint should be excluded by the fast
1765 lra_assert (*p
!= 0 && *p
!= ',');
1767 /* Scan this alternative's specs for this operand; set WIN
1768 if the operand fits any letter in this alternative.
1769 Otherwise, clear BADOP if this operand could fit some
1770 letter after reloads, or set WINREG if this operand could
1771 fit after reloads provided the constraint allows some
1776 switch ((c
= *p
, len
= CONSTRAINT_LEN (c
, p
)), c
)
1786 early_clobber_p
= true;
1790 /* Ignore rest of this alternative. */
1794 case '0': case '1': case '2': case '3': case '4':
1795 case '5': case '6': case '7': case '8': case '9':
1800 m
= strtoul (p
, &end
, 10);
1803 lra_assert (nop
> m
);
1805 this_alternative_matches
= m
;
1806 m_hregno
= get_hard_regno (*curr_id
->operand_loc
[m
]);
1807 /* We are supposed to match a previous operand.
1808 If we do, we win if that one did. If we do
1809 not, count both of the operands as losers.
1810 (This is too conservative, since most of the
1811 time only a single reload insn will be needed
1812 to make the two operands win. As a result,
1813 this alternative may be rejected when it is
1814 actually desirable.) */
1816 if (operands_match_p (*curr_id
->operand_loc
[nop
],
1817 *curr_id
->operand_loc
[m
], m_hregno
))
1819 /* We should reject matching of an early
1820 clobber operand if the matching operand is
1821 not dying in the insn. */
1822 if (! curr_static_id
->operand
[m
].early_clobber
1823 || operand_reg
[nop
] == NULL_RTX
1824 || (find_regno_note (curr_insn
, REG_DEAD
,
1826 || REGNO (op
) == REGNO (operand_reg
[m
])))
1831 /* If we are matching a non-offsettable
1832 address where an offsettable address was
1833 expected, then we must reject this
1834 combination, because we can't reload
1836 if (curr_alt_offmemok
[m
]
1837 && MEM_P (*curr_id
->operand_loc
[m
])
1838 && curr_alt
[m
] == NO_REGS
&& ! curr_alt_win
[m
])
1843 /* Operands don't match. Both operands must
1844 allow a reload register, otherwise we
1845 cannot make them match. */
1846 if (curr_alt
[m
] == NO_REGS
)
1848 /* Retroactively mark the operand we had to
1849 match as a loser, if it wasn't already and
1850 it wasn't matched to a register constraint
1851 (e.g it might be matched by memory). */
1853 && (operand_reg
[m
] == NULL_RTX
1854 || hard_regno
[m
] < 0))
1858 += (ira_reg_class_max_nregs
[curr_alt
[m
]]
1859 [GET_MODE (*curr_id
->operand_loc
[m
])]);
1862 /* Prefer matching earlyclobber alternative as
1863 it results in less hard regs required for
1864 the insn than a non-matching earlyclobber
1866 if (curr_static_id
->operand
[m
].early_clobber
)
1868 if (lra_dump_file
!= NULL
)
1871 " %d Matching earlyclobber alt:"
1876 /* Otherwise we prefer no matching
1877 alternatives because it gives more freedom
1879 else if (operand_reg
[nop
] == NULL_RTX
1880 || (find_regno_note (curr_insn
, REG_DEAD
,
1881 REGNO (operand_reg
[nop
]))
1884 if (lra_dump_file
!= NULL
)
1887 " %d Matching alt: reject+=2\n",
1892 /* If we have to reload this operand and some
1893 previous operand also had to match the same
1894 thing as this operand, we don't know how to do
1896 if (!match_p
|| !curr_alt_win
[m
])
1898 for (i
= 0; i
< nop
; i
++)
1899 if (curr_alt_matches
[i
] == m
)
1907 /* This can be fixed with reloads if the operand
1908 we are supposed to match can be fixed with
1911 this_alternative
= curr_alt
[m
];
1912 COPY_HARD_REG_SET (this_alternative_set
, curr_alt_set
[m
]);
1913 winreg
= this_alternative
!= NO_REGS
;
1919 || general_constant_p (op
)
1920 || spilled_pseudo_p (op
))
1926 cn
= lookup_constraint (p
);
1927 switch (get_constraint_type (cn
))
1930 cl
= reg_class_for_constraint (cn
);
1936 if (CONST_INT_P (op
)
1937 && insn_const_int_ok_for_constraint (INTVAL (op
), cn
))
1943 && satisfies_memory_constraint_p (op
, cn
))
1945 else if (spilled_pseudo_p (op
))
1948 /* If we didn't already win, we can reload constants
1949 via force_const_mem or put the pseudo value into
1950 memory, or make other memory by reloading the
1951 address like for 'o'. */
1952 if (CONST_POOL_OK_P (mode
, op
)
1953 || MEM_P (op
) || REG_P (op
))
1960 /* If we didn't already win, we can reload the address
1961 into a base register. */
1962 if (satisfies_address_constraint_p (op
, cn
))
1964 cl
= base_reg_class (VOIDmode
, ADDR_SPACE_GENERIC
,
1970 if (constraint_satisfied_p (op
, cn
))
1977 this_alternative
= reg_class_subunion
[this_alternative
][cl
];
1978 IOR_HARD_REG_SET (this_alternative_set
,
1979 reg_class_contents
[cl
]);
1982 this_costly_alternative
1983 = reg_class_subunion
[this_costly_alternative
][cl
];
1984 IOR_HARD_REG_SET (this_costly_alternative_set
,
1985 reg_class_contents
[cl
]);
1987 if (mode
== BLKmode
)
1992 if (hard_regno
[nop
] >= 0
1993 && in_hard_reg_set_p (this_alternative_set
,
1994 mode
, hard_regno
[nop
]))
1996 else if (hard_regno
[nop
] < 0
1997 && in_class_p (op
, this_alternative
, NULL
))
2002 if (c
!= ' ' && c
!= '\t')
2003 costly_p
= c
== '*';
2005 while ((p
+= len
), c
);
2007 scratch_p
= (operand_reg
[nop
] != NULL_RTX
2008 && lra_former_scratch_p (REGNO (operand_reg
[nop
])));
2009 /* Record which operands fit this alternative. */
2012 this_alternative_win
= true;
2013 if (operand_reg
[nop
] != NULL_RTX
)
2015 if (hard_regno
[nop
] >= 0)
2017 if (in_hard_reg_set_p (this_costly_alternative_set
,
2018 mode
, hard_regno
[nop
]))
2020 if (lra_dump_file
!= NULL
)
2021 fprintf (lra_dump_file
,
2022 " %d Costly set: reject++\n",
2029 /* Prefer won reg to spilled pseudo under other
2030 equal conditions for possibe inheritance. */
2033 if (lra_dump_file
!= NULL
)
2036 " %d Non pseudo reload: reject++\n",
2040 if (in_class_p (operand_reg
[nop
],
2041 this_costly_alternative
, NULL
))
2043 if (lra_dump_file
!= NULL
)
2046 " %d Non pseudo costly reload:"
2052 /* We simulate the behaviour of old reload here.
2053 Although scratches need hard registers and it
2054 might result in spilling other pseudos, no reload
2055 insns are generated for the scratches. So it
2056 might cost something but probably less than old
2057 reload pass believes. */
2060 if (lra_dump_file
!= NULL
)
2061 fprintf (lra_dump_file
,
2062 " %d Scratch win: reject+=2\n",
2069 this_alternative_match_win
= true;
2072 int const_to_mem
= 0;
2075 /* Never do output reload of stack pointer. It makes
2076 impossible to do elimination when SP is changed in
2078 if (op
== stack_pointer_rtx
&& ! frame_pointer_needed
2079 && curr_static_id
->operand
[nop
].type
!= OP_IN
)
2082 /* If this alternative asks for a specific reg class, see if there
2083 is at least one allocatable register in that class. */
2085 = (this_alternative
== NO_REGS
2086 || (hard_reg_set_subset_p
2087 (reg_class_contents
[this_alternative
],
2088 lra_no_alloc_regs
)));
2090 /* For asms, verify that the class for this alternative is possible
2091 for the mode that is specified. */
2092 if (!no_regs_p
&& INSN_CODE (curr_insn
) < 0)
2095 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
2096 if (HARD_REGNO_MODE_OK (i
, mode
)
2097 && in_hard_reg_set_p (reg_class_contents
[this_alternative
],
2100 if (i
== FIRST_PSEUDO_REGISTER
)
2104 /* If this operand accepts a register, and if the
2105 register class has at least one allocatable register,
2106 then this operand can be reloaded. */
2107 if (winreg
&& !no_regs_p
)
2112 if (lra_dump_file
!= NULL
)
2113 fprintf (lra_dump_file
,
2114 " alt=%d: Bad operand -- refuse\n",
2119 /* If not assigned pseudo has a class which a subset of
2120 required reg class, it is a less costly alternative
2121 as the pseudo still can get a hard reg of necessary
2123 if (! no_regs_p
&& REG_P (op
) && hard_regno
[nop
] < 0
2124 && (cl
= get_reg_class (REGNO (op
))) != NO_REGS
2125 && ira_class_subset_p
[this_alternative
][cl
])
2127 if (lra_dump_file
!= NULL
)
2130 " %d Super set class reg: reject-=3\n", nop
);
2134 this_alternative_offmemok
= offmemok
;
2135 if (this_costly_alternative
!= NO_REGS
)
2137 if (lra_dump_file
!= NULL
)
2138 fprintf (lra_dump_file
,
2139 " %d Costly loser: reject++\n", nop
);
2142 /* If the operand is dying, has a matching constraint,
2143 and satisfies constraints of the matched operand
2144 which failed to satisfy the own constraints, most probably
2145 the reload for this operand will be gone. */
2146 if (this_alternative_matches
>= 0
2147 && !curr_alt_win
[this_alternative_matches
]
2149 && find_regno_note (curr_insn
, REG_DEAD
, REGNO (op
))
2150 && (hard_regno
[nop
] >= 0
2151 ? in_hard_reg_set_p (this_alternative_set
,
2152 mode
, hard_regno
[nop
])
2153 : in_class_p (op
, this_alternative
, NULL
)))
2155 if (lra_dump_file
!= NULL
)
2158 " %d Dying matched operand reload: reject++\n",
2164 /* Strict_low_part requires to reload the register
2165 not the sub-register. In this case we should
2166 check that a final reload hard reg can hold the
2168 if (curr_static_id
->operand
[nop
].strict_low
2170 && hard_regno
[nop
] < 0
2171 && GET_CODE (*curr_id
->operand_loc
[nop
]) == SUBREG
2172 && ira_class_hard_regs_num
[this_alternative
] > 0
2173 && ! HARD_REGNO_MODE_OK (ira_class_hard_regs
2174 [this_alternative
][0],
2176 (*curr_id
->operand_loc
[nop
])))
2178 if (lra_dump_file
!= NULL
)
2181 " alt=%d: Strict low subreg reload -- refuse\n",
2187 if (operand_reg
[nop
] != NULL_RTX
2188 /* Output operands and matched input operands are
2189 not inherited. The following conditions do not
2190 exactly describe the previous statement but they
2191 are pretty close. */
2192 && curr_static_id
->operand
[nop
].type
!= OP_OUT
2193 && (this_alternative_matches
< 0
2194 || curr_static_id
->operand
[nop
].type
!= OP_IN
))
2196 int last_reload
= (lra_reg_info
[ORIGINAL_REGNO
2200 /* The value of reload_sum has sense only if we
2201 process insns in their order. It happens only on
2202 the first constraints sub-pass when we do most of
2204 if (lra_constraint_iter
== 1 && last_reload
> bb_reload_num
)
2205 reload_sum
+= last_reload
- bb_reload_num
;
2207 /* If this is a constant that is reloaded into the
2208 desired class by copying it to memory first, count
2209 that as another reload. This is consistent with
2210 other code and is required to avoid choosing another
2211 alternative when the constant is moved into memory.
2212 Note that the test here is precisely the same as in
2213 the code below that calls force_const_mem. */
2214 if (CONST_POOL_OK_P (mode
, op
)
2215 && ((targetm
.preferred_reload_class
2216 (op
, this_alternative
) == NO_REGS
)
2217 || no_input_reloads_p
))
2224 /* Alternative loses if it requires a type of reload not
2225 permitted for this insn. We can always reload
2226 objects with a REG_UNUSED note. */
2227 if ((curr_static_id
->operand
[nop
].type
!= OP_IN
2228 && no_output_reloads_p
2229 && ! find_reg_note (curr_insn
, REG_UNUSED
, op
))
2230 || (curr_static_id
->operand
[nop
].type
!= OP_OUT
2231 && no_input_reloads_p
&& ! const_to_mem
)
2232 || (this_alternative_matches
>= 0
2233 && (no_input_reloads_p
2234 || (no_output_reloads_p
2235 && (curr_static_id
->operand
2236 [this_alternative_matches
].type
!= OP_IN
)
2237 && ! find_reg_note (curr_insn
, REG_UNUSED
,
2238 no_subreg_reg_operand
2239 [this_alternative_matches
])))))
2241 if (lra_dump_file
!= NULL
)
2244 " alt=%d: No input/otput reload -- refuse\n",
2249 /* Check strong discouragement of reload of non-constant
2250 into class THIS_ALTERNATIVE. */
2251 if (! CONSTANT_P (op
) && ! no_regs_p
2252 && (targetm
.preferred_reload_class
2253 (op
, this_alternative
) == NO_REGS
2254 || (curr_static_id
->operand
[nop
].type
== OP_OUT
2255 && (targetm
.preferred_output_reload_class
2256 (op
, this_alternative
) == NO_REGS
))))
2258 if (lra_dump_file
!= NULL
)
2259 fprintf (lra_dump_file
,
2260 " %d Non-prefered reload: reject+=%d\n",
2261 nop
, LRA_MAX_REJECT
);
2262 reject
+= LRA_MAX_REJECT
;
2265 if (! (MEM_P (op
) && offmemok
)
2266 && ! (const_to_mem
&& constmemok
))
2268 /* We prefer to reload pseudos over reloading other
2269 things, since such reloads may be able to be
2270 eliminated later. So bump REJECT in other cases.
2271 Don't do this in the case where we are forcing a
2272 constant into memory and it will then win since
2273 we don't want to have a different alternative
2275 if (! (REG_P (op
) && REGNO (op
) >= FIRST_PSEUDO_REGISTER
))
2277 if (lra_dump_file
!= NULL
)
2280 " %d Non-pseudo reload: reject+=2\n",
2287 += ira_reg_class_max_nregs
[this_alternative
][mode
];
2289 if (SMALL_REGISTER_CLASS_P (this_alternative
))
2291 if (lra_dump_file
!= NULL
)
2294 " %d Small class reload: reject+=%d\n",
2295 nop
, LRA_LOSER_COST_FACTOR
/ 2);
2296 reject
+= LRA_LOSER_COST_FACTOR
/ 2;
2300 /* We are trying to spill pseudo into memory. It is
2301 usually more costly than moving to a hard register
2302 although it might takes the same number of
2304 if (no_regs_p
&& REG_P (op
) && hard_regno
[nop
] >= 0)
2306 if (lra_dump_file
!= NULL
)
2309 " %d Spill pseudo into memory: reject+=3\n",
2312 if (VECTOR_MODE_P (mode
))
2314 /* Spilling vectors into memory is usually more
2315 costly as they contain big values. */
2316 if (lra_dump_file
!= NULL
)
2319 " %d Spill vector pseudo: reject+=2\n",
2325 #ifdef SECONDARY_MEMORY_NEEDED
2326 /* If reload requires moving value through secondary
2327 memory, it will need one more insn at least. */
2328 if (this_alternative
!= NO_REGS
2329 && REG_P (op
) && (cl
= get_reg_class (REGNO (op
))) != NO_REGS
2330 && ((curr_static_id
->operand
[nop
].type
!= OP_OUT
2331 && SECONDARY_MEMORY_NEEDED (cl
, this_alternative
,
2333 || (curr_static_id
->operand
[nop
].type
!= OP_IN
2334 && SECONDARY_MEMORY_NEEDED (this_alternative
, cl
,
2338 /* Input reloads can be inherited more often than output
2339 reloads can be removed, so penalize output
2341 if (!REG_P (op
) || curr_static_id
->operand
[nop
].type
!= OP_IN
)
2343 if (lra_dump_file
!= NULL
)
2346 " %d Non input pseudo reload: reject++\n",
2352 if (early_clobber_p
&& ! scratch_p
)
2354 if (lra_dump_file
!= NULL
)
2355 fprintf (lra_dump_file
,
2356 " %d Early clobber: reject++\n", nop
);
2359 /* ??? We check early clobbers after processing all operands
2360 (see loop below) and there we update the costs more.
2361 Should we update the cost (may be approximately) here
2362 because of early clobber register reloads or it is a rare
2363 or non-important thing to be worth to do it. */
2364 overall
= losers
* LRA_LOSER_COST_FACTOR
+ reject
;
2365 if ((best_losers
== 0 || losers
!= 0) && best_overall
< overall
)
2367 if (lra_dump_file
!= NULL
)
2368 fprintf (lra_dump_file
,
2369 " alt=%d,overall=%d,losers=%d -- refuse\n",
2370 nalt
, overall
, losers
);
2374 curr_alt
[nop
] = this_alternative
;
2375 COPY_HARD_REG_SET (curr_alt_set
[nop
], this_alternative_set
);
2376 curr_alt_win
[nop
] = this_alternative_win
;
2377 curr_alt_match_win
[nop
] = this_alternative_match_win
;
2378 curr_alt_offmemok
[nop
] = this_alternative_offmemok
;
2379 curr_alt_matches
[nop
] = this_alternative_matches
;
2381 if (this_alternative_matches
>= 0
2382 && !did_match
&& !this_alternative_win
)
2383 curr_alt_win
[this_alternative_matches
] = false;
2385 if (early_clobber_p
&& operand_reg
[nop
] != NULL_RTX
)
2386 early_clobbered_nops
[early_clobbered_regs_num
++] = nop
;
2388 if (curr_insn_set
!= NULL_RTX
&& n_operands
== 2
2389 /* Prevent processing non-move insns. */
2390 && (GET_CODE (SET_SRC (curr_insn_set
)) == SUBREG
2391 || SET_SRC (curr_insn_set
) == no_subreg_reg_operand
[1])
2392 && ((! curr_alt_win
[0] && ! curr_alt_win
[1]
2393 && REG_P (no_subreg_reg_operand
[0])
2394 && REG_P (no_subreg_reg_operand
[1])
2395 && (reg_in_class_p (no_subreg_reg_operand
[0], curr_alt
[1])
2396 || reg_in_class_p (no_subreg_reg_operand
[1], curr_alt
[0])))
2397 || (! curr_alt_win
[0] && curr_alt_win
[1]
2398 && REG_P (no_subreg_reg_operand
[1])
2399 && reg_in_class_p (no_subreg_reg_operand
[1], curr_alt
[0]))
2400 || (curr_alt_win
[0] && ! curr_alt_win
[1]
2401 && REG_P (no_subreg_reg_operand
[0])
2402 && reg_in_class_p (no_subreg_reg_operand
[0], curr_alt
[1])
2403 && (! CONST_POOL_OK_P (curr_operand_mode
[1],
2404 no_subreg_reg_operand
[1])
2405 || (targetm
.preferred_reload_class
2406 (no_subreg_reg_operand
[1],
2407 (enum reg_class
) curr_alt
[1]) != NO_REGS
))
2408 /* If it is a result of recent elimination in move
2409 insn we can transform it into an add still by
2410 using this alternative. */
2411 && GET_CODE (no_subreg_reg_operand
[1]) != PLUS
)))
2413 /* We have a move insn and a new reload insn will be similar
2414 to the current insn. We should avoid such situation as it
2415 results in LRA cycling. */
2416 overall
+= LRA_MAX_REJECT
;
2419 curr_alt_dont_inherit_ops_num
= 0;
2420 for (nop
= 0; nop
< early_clobbered_regs_num
; nop
++)
2422 int i
, j
, clobbered_hard_regno
, first_conflict_j
, last_conflict_j
;
2423 HARD_REG_SET temp_set
;
2425 i
= early_clobbered_nops
[nop
];
2426 if ((! curr_alt_win
[i
] && ! curr_alt_match_win
[i
])
2427 || hard_regno
[i
] < 0)
2429 lra_assert (operand_reg
[i
] != NULL_RTX
);
2430 clobbered_hard_regno
= hard_regno
[i
];
2431 CLEAR_HARD_REG_SET (temp_set
);
2432 add_to_hard_reg_set (&temp_set
, biggest_mode
[i
], clobbered_hard_regno
);
2433 first_conflict_j
= last_conflict_j
= -1;
2434 for (j
= 0; j
< n_operands
; j
++)
2436 /* We don't want process insides of match_operator and
2437 match_parallel because otherwise we would process
2438 their operands once again generating a wrong
2440 || curr_static_id
->operand
[j
].is_operator
)
2442 else if ((curr_alt_matches
[j
] == i
&& curr_alt_match_win
[j
])
2443 || (curr_alt_matches
[i
] == j
&& curr_alt_match_win
[i
]))
2445 /* If we don't reload j-th operand, check conflicts. */
2446 else if ((curr_alt_win
[j
] || curr_alt_match_win
[j
])
2447 && uses_hard_regs_p (*curr_id
->operand_loc
[j
], temp_set
))
2449 if (first_conflict_j
< 0)
2450 first_conflict_j
= j
;
2451 last_conflict_j
= j
;
2453 if (last_conflict_j
< 0)
2455 /* If earlyclobber operand conflicts with another
2456 non-matching operand which is actually the same register
2457 as the earlyclobber operand, it is better to reload the
2458 another operand as an operand matching the earlyclobber
2459 operand can be also the same. */
2460 if (first_conflict_j
== last_conflict_j
2461 && operand_reg
[last_conflict_j
]
2462 != NULL_RTX
&& ! curr_alt_match_win
[last_conflict_j
]
2463 && REGNO (operand_reg
[i
]) == REGNO (operand_reg
[last_conflict_j
]))
2465 curr_alt_win
[last_conflict_j
] = false;
2466 curr_alt_dont_inherit_ops
[curr_alt_dont_inherit_ops_num
++]
2469 /* Early clobber was already reflected in REJECT. */
2470 lra_assert (reject
> 0);
2471 if (lra_dump_file
!= NULL
)
2474 " %d Conflict early clobber reload: reject--\n",
2477 overall
+= LRA_LOSER_COST_FACTOR
- 1;
2481 /* We need to reload early clobbered register and the
2482 matched registers. */
2483 for (j
= 0; j
< n_operands
; j
++)
2484 if (curr_alt_matches
[j
] == i
)
2486 curr_alt_match_win
[j
] = false;
2488 overall
+= LRA_LOSER_COST_FACTOR
;
2490 if (! curr_alt_match_win
[i
])
2491 curr_alt_dont_inherit_ops
[curr_alt_dont_inherit_ops_num
++] = i
;
2494 /* Remember pseudos used for match reloads are never
2496 lra_assert (curr_alt_matches
[i
] >= 0);
2497 curr_alt_win
[curr_alt_matches
[i
]] = false;
2499 curr_alt_win
[i
] = curr_alt_match_win
[i
] = false;
2501 /* Early clobber was already reflected in REJECT. */
2502 lra_assert (reject
> 0);
2503 if (lra_dump_file
!= NULL
)
2506 " %d Matched conflict early clobber reloads:"
2510 overall
+= LRA_LOSER_COST_FACTOR
- 1;
2513 if (lra_dump_file
!= NULL
)
2514 fprintf (lra_dump_file
, " alt=%d,overall=%d,losers=%d,rld_nregs=%d\n",
2515 nalt
, overall
, losers
, reload_nregs
);
2517 /* If this alternative can be made to work by reloading, and it
2518 needs less reloading than the others checked so far, record
2519 it as the chosen goal for reloading. */
2520 if ((best_losers
!= 0 && losers
== 0)
2521 || (((best_losers
== 0 && losers
== 0)
2522 || (best_losers
!= 0 && losers
!= 0))
2523 && (best_overall
> overall
2524 || (best_overall
== overall
2525 /* If the cost of the reloads is the same,
2526 prefer alternative which requires minimal
2527 number of reload regs. */
2528 && (reload_nregs
< best_reload_nregs
2529 || (reload_nregs
== best_reload_nregs
2530 && (best_reload_sum
< reload_sum
2531 || (best_reload_sum
== reload_sum
2532 && nalt
< goal_alt_number
))))))))
2534 for (nop
= 0; nop
< n_operands
; nop
++)
2536 goal_alt_win
[nop
] = curr_alt_win
[nop
];
2537 goal_alt_match_win
[nop
] = curr_alt_match_win
[nop
];
2538 goal_alt_matches
[nop
] = curr_alt_matches
[nop
];
2539 goal_alt
[nop
] = curr_alt
[nop
];
2540 goal_alt_offmemok
[nop
] = curr_alt_offmemok
[nop
];
2542 goal_alt_dont_inherit_ops_num
= curr_alt_dont_inherit_ops_num
;
2543 for (nop
= 0; nop
< curr_alt_dont_inherit_ops_num
; nop
++)
2544 goal_alt_dont_inherit_ops
[nop
] = curr_alt_dont_inherit_ops
[nop
];
2545 goal_alt_swapped
= curr_swapped
;
2546 best_overall
= overall
;
2547 best_losers
= losers
;
2548 best_reload_nregs
= reload_nregs
;
2549 best_reload_sum
= reload_sum
;
2550 goal_alt_number
= nalt
;
2553 /* Everything is satisfied. Do not process alternatives
2562 /* Make reload base reg from address AD. */
2564 base_to_reg (struct address_info
*ad
)
2568 rtx new_inner
= NULL_RTX
;
2569 rtx new_reg
= NULL_RTX
;
2571 rtx last_insn
= get_last_insn();
2573 lra_assert (ad
->base
== ad
->base_term
&& ad
->disp
== ad
->disp_term
);
2574 cl
= base_reg_class (ad
->mode
, ad
->as
, ad
->base_outer_code
,
2575 get_index_code (ad
));
2576 new_reg
= lra_create_new_reg (GET_MODE (*ad
->base_term
), NULL_RTX
,
2578 new_inner
= simplify_gen_binary (PLUS
, GET_MODE (new_reg
), new_reg
,
2579 ad
->disp_term
== NULL
2580 ? gen_int_mode (0, ad
->mode
)
2582 if (!valid_address_p (ad
->mode
, new_inner
, ad
->as
))
2584 insn
= emit_insn (gen_rtx_SET (ad
->mode
, new_reg
, *ad
->base_term
));
2585 code
= recog_memoized (insn
);
2588 delete_insns_since (last_insn
);
2595 /* Make reload base reg + disp from address AD. Return the new pseudo. */
2597 base_plus_disp_to_reg (struct address_info
*ad
)
2602 lra_assert (ad
->base
== ad
->base_term
&& ad
->disp
== ad
->disp_term
);
2603 cl
= base_reg_class (ad
->mode
, ad
->as
, ad
->base_outer_code
,
2604 get_index_code (ad
));
2605 new_reg
= lra_create_new_reg (GET_MODE (*ad
->base_term
), NULL_RTX
,
2607 lra_emit_add (new_reg
, *ad
->base_term
, *ad
->disp_term
);
2611 /* Make reload of index part of address AD. Return the new
2614 index_part_to_reg (struct address_info
*ad
)
2618 new_reg
= lra_create_new_reg (GET_MODE (*ad
->index
), NULL_RTX
,
2619 INDEX_REG_CLASS
, "index term");
2620 expand_mult (GET_MODE (*ad
->index
), *ad
->index_term
,
2621 GEN_INT (get_index_scale (ad
)), new_reg
, 1);
2625 /* Return true if we can add a displacement to address AD, even if that
2626 makes the address invalid. The fix-up code requires any new address
2627 to be the sum of the BASE_TERM, INDEX and DISP_TERM fields. */
2629 can_add_disp_p (struct address_info
*ad
)
2631 return (!ad
->autoinc_p
2632 && ad
->segment
== NULL
2633 && ad
->base
== ad
->base_term
2634 && ad
->disp
== ad
->disp_term
);
2637 /* Make equiv substitution in address AD. Return true if a substitution
2640 equiv_address_substitution (struct address_info
*ad
)
2642 rtx base_reg
, new_base_reg
, index_reg
, new_index_reg
, *base_term
, *index_term
;
2643 HOST_WIDE_INT disp
, scale
;
2646 base_term
= strip_subreg (ad
->base_term
);
2647 if (base_term
== NULL
)
2648 base_reg
= new_base_reg
= NULL_RTX
;
2651 base_reg
= *base_term
;
2652 new_base_reg
= get_equiv_with_elimination (base_reg
, curr_insn
);
2654 index_term
= strip_subreg (ad
->index_term
);
2655 if (index_term
== NULL
)
2656 index_reg
= new_index_reg
= NULL_RTX
;
2659 index_reg
= *index_term
;
2660 new_index_reg
= get_equiv_with_elimination (index_reg
, curr_insn
);
2662 if (base_reg
== new_base_reg
&& index_reg
== new_index_reg
)
2666 if (lra_dump_file
!= NULL
)
2668 fprintf (lra_dump_file
, "Changing address in insn %d ",
2669 INSN_UID (curr_insn
));
2670 dump_value_slim (lra_dump_file
, *ad
->outer
, 1);
2672 if (base_reg
!= new_base_reg
)
2674 if (REG_P (new_base_reg
))
2676 *base_term
= new_base_reg
;
2679 else if (GET_CODE (new_base_reg
) == PLUS
2680 && REG_P (XEXP (new_base_reg
, 0))
2681 && CONST_INT_P (XEXP (new_base_reg
, 1))
2682 && can_add_disp_p (ad
))
2684 disp
+= INTVAL (XEXP (new_base_reg
, 1));
2685 *base_term
= XEXP (new_base_reg
, 0);
2688 if (ad
->base_term2
!= NULL
)
2689 *ad
->base_term2
= *ad
->base_term
;
2691 if (index_reg
!= new_index_reg
)
2693 if (REG_P (new_index_reg
))
2695 *index_term
= new_index_reg
;
2698 else if (GET_CODE (new_index_reg
) == PLUS
2699 && REG_P (XEXP (new_index_reg
, 0))
2700 && CONST_INT_P (XEXP (new_index_reg
, 1))
2701 && can_add_disp_p (ad
)
2702 && (scale
= get_index_scale (ad
)))
2704 disp
+= INTVAL (XEXP (new_index_reg
, 1)) * scale
;
2705 *index_term
= XEXP (new_index_reg
, 0);
2711 if (ad
->disp
!= NULL
)
2712 *ad
->disp
= plus_constant (GET_MODE (*ad
->inner
), *ad
->disp
, disp
);
2715 *ad
->inner
= plus_constant (GET_MODE (*ad
->inner
), *ad
->inner
, disp
);
2716 update_address (ad
);
2720 if (lra_dump_file
!= NULL
)
2723 fprintf (lra_dump_file
, " -- no change\n");
2726 fprintf (lra_dump_file
, " on equiv ");
2727 dump_value_slim (lra_dump_file
, *ad
->outer
, 1);
2728 fprintf (lra_dump_file
, "\n");
2734 /* Major function to make reloads for an address in operand NOP.
2735 The supported cases are:
2737 1) an address that existed before LRA started, at which point it
2738 must have been valid. These addresses are subject to elimination
2739 and may have become invalid due to the elimination offset being out
2742 2) an address created by forcing a constant to memory
2743 (force_const_to_mem). The initial form of these addresses might
2744 not be valid, and it is this function's job to make them valid.
2746 3) a frame address formed from a register and a (possibly zero)
2747 constant offset. As above, these addresses might not be valid and
2748 this function must make them so.
2750 Add reloads to the lists *BEFORE and *AFTER. We might need to add
2751 reloads to *AFTER because of inc/dec, {pre, post} modify in the
2752 address. Return true for any RTL change.
2754 The function is a helper function which does not produce all
2755 transformations which can be necessary. It does just basic steps.
2756 To do all necessary transformations use function
2759 process_address_1 (int nop
, rtx_insn
**before
, rtx_insn
**after
)
2761 struct address_info ad
;
2763 rtx op
= *curr_id
->operand_loc
[nop
];
2764 const char *constraint
= curr_static_id
->operand
[nop
].constraint
;
2765 enum constraint_num cn
= lookup_constraint (constraint
);
2768 if (insn_extra_address_constraint (cn
))
2769 decompose_lea_address (&ad
, curr_id
->operand_loc
[nop
]);
2770 else if (MEM_P (op
))
2771 decompose_mem_address (&ad
, op
);
2772 else if (GET_CODE (op
) == SUBREG
2773 && MEM_P (SUBREG_REG (op
)))
2774 decompose_mem_address (&ad
, SUBREG_REG (op
));
2777 change_p
= equiv_address_substitution (&ad
);
2778 if (ad
.base_term
!= NULL
2779 && (process_addr_reg
2780 (ad
.base_term
, before
,
2782 && !(REG_P (*ad
.base_term
)
2783 && find_regno_note (curr_insn
, REG_DEAD
,
2784 REGNO (*ad
.base_term
)) != NULL_RTX
)
2786 base_reg_class (ad
.mode
, ad
.as
, ad
.base_outer_code
,
2787 get_index_code (&ad
)))))
2790 if (ad
.base_term2
!= NULL
)
2791 *ad
.base_term2
= *ad
.base_term
;
2793 if (ad
.index_term
!= NULL
2794 && process_addr_reg (ad
.index_term
, before
, NULL
, INDEX_REG_CLASS
))
2797 /* Target hooks sometimes don't treat extra-constraint addresses as
2798 legitimate address_operands, so handle them specially. */
2799 if (insn_extra_address_constraint (cn
)
2800 && satisfies_address_constraint_p (&ad
, cn
))
2803 /* There are three cases where the shape of *AD.INNER may now be invalid:
2805 1) the original address was valid, but either elimination or
2806 equiv_address_substitution was applied and that made
2807 the address invalid.
2809 2) the address is an invalid symbolic address created by
2812 3) the address is a frame address with an invalid offset.
2814 4) the address is a frame address with an invalid base.
2816 All these cases involve a non-autoinc address, so there is no
2817 point revalidating other types. */
2818 if (ad
.autoinc_p
|| valid_address_p (&ad
))
2821 /* Any index existed before LRA started, so we can assume that the
2822 presence and shape of the index is valid. */
2823 push_to_sequence (*before
);
2824 lra_assert (ad
.disp
== ad
.disp_term
);
2825 if (ad
.base
== NULL
)
2827 if (ad
.index
== NULL
)
2830 enum reg_class cl
= base_reg_class (ad
.mode
, ad
.as
,
2832 rtx addr
= *ad
.inner
;
2834 new_reg
= lra_create_new_reg (Pmode
, NULL_RTX
, cl
, "addr");
2838 rtx last
= get_last_insn ();
2840 /* addr => lo_sum (new_base, addr), case (2) above. */
2841 insn
= emit_insn (gen_rtx_SET
2843 gen_rtx_HIGH (Pmode
, copy_rtx (addr
))));
2844 code
= recog_memoized (insn
);
2847 *ad
.inner
= gen_rtx_LO_SUM (Pmode
, new_reg
, addr
);
2848 if (! valid_address_p (ad
.mode
, *ad
.outer
, ad
.as
))
2850 /* Try to put lo_sum into register. */
2851 insn
= emit_insn (gen_rtx_SET
2853 gen_rtx_LO_SUM (Pmode
, new_reg
, addr
)));
2854 code
= recog_memoized (insn
);
2857 *ad
.inner
= new_reg
;
2858 if (! valid_address_p (ad
.mode
, *ad
.outer
, ad
.as
))
2868 delete_insns_since (last
);
2873 /* addr => new_base, case (2) above. */
2874 lra_emit_move (new_reg
, addr
);
2875 *ad
.inner
= new_reg
;
2880 /* index * scale + disp => new base + index * scale,
2882 enum reg_class cl
= base_reg_class (ad
.mode
, ad
.as
, PLUS
,
2883 GET_CODE (*ad
.index
));
2885 lra_assert (INDEX_REG_CLASS
!= NO_REGS
);
2886 new_reg
= lra_create_new_reg (Pmode
, NULL_RTX
, cl
, "disp");
2887 lra_emit_move (new_reg
, *ad
.disp
);
2888 *ad
.inner
= simplify_gen_binary (PLUS
, GET_MODE (new_reg
),
2889 new_reg
, *ad
.index
);
2892 else if (ad
.index
== NULL
)
2897 rtx_insn
*insns
, *last_insn
;
2898 /* Try to reload base into register only if the base is invalid
2899 for the address but with valid offset, case (4) above. */
2901 new_reg
= base_to_reg (&ad
);
2903 /* base + disp => new base, cases (1) and (3) above. */
2904 /* Another option would be to reload the displacement into an
2905 index register. However, postreload has code to optimize
2906 address reloads that have the same base and different
2907 displacements, so reloading into an index register would
2908 not necessarily be a win. */
2909 if (new_reg
== NULL_RTX
)
2910 new_reg
= base_plus_disp_to_reg (&ad
);
2911 insns
= get_insns ();
2912 last_insn
= get_last_insn ();
2913 /* If we generated at least two insns, try last insn source as
2914 an address. If we succeed, we generate one less insn. */
2915 if (last_insn
!= insns
&& (set
= single_set (last_insn
)) != NULL_RTX
2916 && GET_CODE (SET_SRC (set
)) == PLUS
2917 && REG_P (XEXP (SET_SRC (set
), 0))
2918 && CONSTANT_P (XEXP (SET_SRC (set
), 1)))
2920 *ad
.inner
= SET_SRC (set
);
2921 if (valid_address_p (ad
.mode
, *ad
.outer
, ad
.as
))
2923 *ad
.base_term
= XEXP (SET_SRC (set
), 0);
2924 *ad
.disp_term
= XEXP (SET_SRC (set
), 1);
2925 cl
= base_reg_class (ad
.mode
, ad
.as
, ad
.base_outer_code
,
2926 get_index_code (&ad
));
2927 regno
= REGNO (*ad
.base_term
);
2928 if (regno
>= FIRST_PSEUDO_REGISTER
2929 && cl
!= lra_get_allocno_class (regno
))
2930 lra_change_class (regno
, cl
, " Change to", true);
2931 new_reg
= SET_SRC (set
);
2932 delete_insns_since (PREV_INSN (last_insn
));
2937 *ad
.inner
= new_reg
;
2939 else if (ad
.disp_term
!= NULL
)
2941 /* base + scale * index + disp => new base + scale * index,
2943 new_reg
= base_plus_disp_to_reg (&ad
);
2944 *ad
.inner
= simplify_gen_binary (PLUS
, GET_MODE (new_reg
),
2945 new_reg
, *ad
.index
);
2947 else if (get_index_scale (&ad
) == 1)
2949 /* The last transformation to one reg will be made in
2950 curr_insn_transform function. */
2956 /* base + scale * index => base + new_reg,
2958 Index part of address may become invalid. For example, we
2959 changed pseudo on the equivalent memory and a subreg of the
2960 pseudo onto the memory of different mode for which the scale is
2962 new_reg
= index_part_to_reg (&ad
);
2963 *ad
.inner
= simplify_gen_binary (PLUS
, GET_MODE (new_reg
),
2964 *ad
.base_term
, new_reg
);
2966 *before
= get_insns ();
2971 /* Do address reloads until it is necessary. Use process_address_1 as
2972 a helper function. Return true for any RTL changes. */
2974 process_address (int nop
, rtx_insn
**before
, rtx_insn
**after
)
2978 while (process_address_1 (nop
, before
, after
))
2983 /* Emit insns to reload VALUE into a new register. VALUE is an
2984 auto-increment or auto-decrement RTX whose operand is a register or
2985 memory location; so reloading involves incrementing that location.
2986 IN is either identical to VALUE, or some cheaper place to reload
2987 value being incremented/decremented from.
2989 INC_AMOUNT is the number to increment or decrement by (always
2990 positive and ignored for POST_MODIFY/PRE_MODIFY).
2992 Return pseudo containing the result. */
2994 emit_inc (enum reg_class new_rclass
, rtx in
, rtx value
, int inc_amount
)
2996 /* REG or MEM to be copied and incremented. */
2997 rtx incloc
= XEXP (value
, 0);
2998 /* Nonzero if increment after copying. */
2999 int post
= (GET_CODE (value
) == POST_DEC
|| GET_CODE (value
) == POST_INC
3000 || GET_CODE (value
) == POST_MODIFY
);
3005 rtx real_in
= in
== value
? incloc
: in
;
3009 if (GET_CODE (value
) == PRE_MODIFY
|| GET_CODE (value
) == POST_MODIFY
)
3011 lra_assert (GET_CODE (XEXP (value
, 1)) == PLUS
3012 || GET_CODE (XEXP (value
, 1)) == MINUS
);
3013 lra_assert (rtx_equal_p (XEXP (XEXP (value
, 1), 0), XEXP (value
, 0)));
3014 plus_p
= GET_CODE (XEXP (value
, 1)) == PLUS
;
3015 inc
= XEXP (XEXP (value
, 1), 1);
3019 if (GET_CODE (value
) == PRE_DEC
|| GET_CODE (value
) == POST_DEC
)
3020 inc_amount
= -inc_amount
;
3022 inc
= GEN_INT (inc_amount
);
3025 if (! post
&& REG_P (incloc
))
3028 result
= lra_create_new_reg (GET_MODE (value
), value
, new_rclass
,
3031 if (real_in
!= result
)
3033 /* First copy the location to the result register. */
3034 lra_assert (REG_P (result
));
3035 emit_insn (gen_move_insn (result
, real_in
));
3038 /* We suppose that there are insns to add/sub with the constant
3039 increment permitted in {PRE/POST)_{DEC/INC/MODIFY}. At least the
3040 old reload worked with this assumption. If the assumption
3041 becomes wrong, we should use approach in function
3042 base_plus_disp_to_reg. */
3045 /* See if we can directly increment INCLOC. */
3046 last
= get_last_insn ();
3047 add_insn
= emit_insn (plus_p
3048 ? gen_add2_insn (incloc
, inc
)
3049 : gen_sub2_insn (incloc
, inc
));
3051 code
= recog_memoized (add_insn
);
3054 if (! post
&& result
!= incloc
)
3055 emit_insn (gen_move_insn (result
, incloc
));
3058 delete_insns_since (last
);
3061 /* If couldn't do the increment directly, must increment in RESULT.
3062 The way we do this depends on whether this is pre- or
3063 post-increment. For pre-increment, copy INCLOC to the reload
3064 register, increment it there, then save back. */
3067 if (real_in
!= result
)
3068 emit_insn (gen_move_insn (result
, real_in
));
3070 emit_insn (gen_add2_insn (result
, inc
));
3072 emit_insn (gen_sub2_insn (result
, inc
));
3073 if (result
!= incloc
)
3074 emit_insn (gen_move_insn (incloc
, result
));
3080 Because this might be a jump insn or a compare, and because
3081 RESULT may not be available after the insn in an input
3082 reload, we must do the incrementing before the insn being
3085 We have already copied IN to RESULT. Increment the copy in
3086 RESULT, save that back, then decrement RESULT so it has
3087 the original value. */
3089 emit_insn (gen_add2_insn (result
, inc
));
3091 emit_insn (gen_sub2_insn (result
, inc
));
3092 emit_insn (gen_move_insn (incloc
, result
));
3093 /* Restore non-modified value for the result. We prefer this
3094 way because it does not require an additional hard
3098 if (CONST_INT_P (inc
))
3099 emit_insn (gen_add2_insn (result
,
3100 gen_int_mode (-INTVAL (inc
),
3101 GET_MODE (result
))));
3103 emit_insn (gen_sub2_insn (result
, inc
));
3106 emit_insn (gen_add2_insn (result
, inc
));
3111 /* Return true if the current move insn does not need processing as we
3112 already know that it satisfies its constraints. */
3114 simple_move_p (void)
3117 enum reg_class dclass
, sclass
;
3119 lra_assert (curr_insn_set
!= NULL_RTX
);
3120 dest
= SET_DEST (curr_insn_set
);
3121 src
= SET_SRC (curr_insn_set
);
3122 return ((dclass
= get_op_class (dest
)) != NO_REGS
3123 && (sclass
= get_op_class (src
)) != NO_REGS
3124 /* The backend guarantees that register moves of cost 2
3125 never need reloads. */
3126 && targetm
.register_move_cost (GET_MODE (src
), dclass
, sclass
) == 2);
3129 /* Swap operands NOP and NOP + 1. */
3131 swap_operands (int nop
)
3133 enum machine_mode mode
= curr_operand_mode
[nop
];
3134 curr_operand_mode
[nop
] = curr_operand_mode
[nop
+ 1];
3135 curr_operand_mode
[nop
+ 1] = mode
;
3136 rtx x
= *curr_id
->operand_loc
[nop
];
3137 *curr_id
->operand_loc
[nop
] = *curr_id
->operand_loc
[nop
+ 1];
3138 *curr_id
->operand_loc
[nop
+ 1] = x
;
3139 /* Swap the duplicates too. */
3140 lra_update_dup (curr_id
, nop
);
3141 lra_update_dup (curr_id
, nop
+ 1);
3144 /* Main entry point of the constraint code: search the body of the
3145 current insn to choose the best alternative. It is mimicking insn
3146 alternative cost calculation model of former reload pass. That is
3147 because machine descriptions were written to use this model. This
3148 model can be changed in future. Make commutative operand exchange
3151 Return true if some RTL changes happened during function call. */
3153 curr_insn_transform (void)
3159 signed char goal_alt_matched
[MAX_RECOG_OPERANDS
][MAX_RECOG_OPERANDS
];
3160 signed char match_inputs
[MAX_RECOG_OPERANDS
+ 1];
3161 rtx_insn
*before
, *after
;
3163 /* Flag that the insn has been changed through a transformation. */
3166 #ifdef SECONDARY_MEMORY_NEEDED
3169 int max_regno_before
;
3170 int reused_alternative_num
;
3172 curr_insn_set
= single_set (curr_insn
);
3173 if (curr_insn_set
!= NULL_RTX
&& simple_move_p ())
3176 no_input_reloads_p
= no_output_reloads_p
= false;
3177 goal_alt_number
= -1;
3178 change_p
= sec_mem_p
= false;
3179 /* JUMP_INSNs and CALL_INSNs are not allowed to have any output
3180 reloads; neither are insns that SET cc0. Insns that use CC0 are
3181 not allowed to have any input reloads. */
3182 if (JUMP_P (curr_insn
) || CALL_P (curr_insn
))
3183 no_output_reloads_p
= true;
3186 if (reg_referenced_p (cc0_rtx
, PATTERN (curr_insn
)))
3187 no_input_reloads_p
= true;
3188 if (reg_set_p (cc0_rtx
, PATTERN (curr_insn
)))
3189 no_output_reloads_p
= true;
3192 n_operands
= curr_static_id
->n_operands
;
3193 n_alternatives
= curr_static_id
->n_alternatives
;
3195 /* Just return "no reloads" if insn has no operands with
3197 if (n_operands
== 0 || n_alternatives
== 0)
3200 max_regno_before
= max_reg_num ();
3202 for (i
= 0; i
< n_operands
; i
++)
3204 goal_alt_matched
[i
][0] = -1;
3205 goal_alt_matches
[i
] = -1;
3208 commutative
= curr_static_id
->commutative
;
3210 /* Now see what we need for pseudos that didn't get hard regs or got
3211 the wrong kind of hard reg. For this, we must consider all the
3212 operands together against the register constraints. */
3214 best_losers
= best_overall
= INT_MAX
;
3215 best_reload_sum
= 0;
3217 curr_swapped
= false;
3218 goal_alt_swapped
= false;
3220 /* Make equivalence substitution and memory subreg elimination
3221 before address processing because an address legitimacy can
3222 depend on memory mode. */
3223 for (i
= 0; i
< n_operands
; i
++)
3225 rtx op
= *curr_id
->operand_loc
[i
];
3226 rtx subst
, old
= op
;
3227 bool op_change_p
= false;
3229 if (GET_CODE (old
) == SUBREG
)
3230 old
= SUBREG_REG (old
);
3231 subst
= get_equiv_with_elimination (old
, curr_insn
);
3234 subst
= copy_rtx (subst
);
3235 lra_assert (REG_P (old
));
3236 if (GET_CODE (op
) == SUBREG
)
3237 SUBREG_REG (op
) = subst
;
3239 *curr_id
->operand_loc
[i
] = subst
;
3240 if (lra_dump_file
!= NULL
)
3242 fprintf (lra_dump_file
,
3243 "Changing pseudo %d in operand %i of insn %u on equiv ",
3244 REGNO (old
), i
, INSN_UID (curr_insn
));
3245 dump_value_slim (lra_dump_file
, subst
, 1);
3246 fprintf (lra_dump_file
, "\n");
3248 op_change_p
= change_p
= true;
3250 if (simplify_operand_subreg (i
, GET_MODE (old
)) || op_change_p
)
3253 lra_update_dup (curr_id
, i
);
3257 /* Reload address registers and displacements. We do it before
3258 finding an alternative because of memory constraints. */
3259 before
= after
= NULL
;
3260 for (i
= 0; i
< n_operands
; i
++)
3261 if (! curr_static_id
->operand
[i
].is_operator
3262 && process_address (i
, &before
, &after
))
3265 lra_update_dup (curr_id
, i
);
3269 /* If we've changed the instruction then any alternative that
3270 we chose previously may no longer be valid. */
3271 lra_set_used_insn_alternative (curr_insn
, -1);
3273 if (curr_insn_set
!= NULL_RTX
3274 && check_and_process_move (&change_p
, &sec_mem_p
))
3279 reused_alternative_num
= curr_id
->used_insn_alternative
;
3280 if (lra_dump_file
!= NULL
&& reused_alternative_num
>= 0)
3281 fprintf (lra_dump_file
, "Reusing alternative %d for insn #%u\n",
3282 reused_alternative_num
, INSN_UID (curr_insn
));
3284 if (process_alt_operands (reused_alternative_num
))
3287 /* If insn is commutative (it's safe to exchange a certain pair of
3288 operands) then we need to try each alternative twice, the second
3289 time matching those two operands as if we had exchanged them. To
3290 do this, really exchange them in operands.
3292 If we have just tried the alternatives the second time, return
3293 operands to normal and drop through. */
3295 if (reused_alternative_num
< 0 && commutative
>= 0)
3297 curr_swapped
= !curr_swapped
;
3300 swap_operands (commutative
);
3304 swap_operands (commutative
);
3307 if (! alt_p
&& ! sec_mem_p
)
3309 /* No alternative works with reloads?? */
3310 if (INSN_CODE (curr_insn
) >= 0)
3311 fatal_insn ("unable to generate reloads for:", curr_insn
);
3312 error_for_asm (curr_insn
,
3313 "inconsistent operand constraints in an %<asm%>");
3314 /* Avoid further trouble with this insn. */
3315 PATTERN (curr_insn
) = gen_rtx_USE (VOIDmode
, const0_rtx
);
3316 lra_invalidate_insn_data (curr_insn
);
3320 /* If the best alternative is with operands 1 and 2 swapped, swap
3321 them. Update the operand numbers of any reloads already
3324 if (goal_alt_swapped
)
3326 if (lra_dump_file
!= NULL
)
3327 fprintf (lra_dump_file
, " Commutative operand exchange in insn %u\n",
3328 INSN_UID (curr_insn
));
3330 /* Swap the duplicates too. */
3331 swap_operands (commutative
);
3335 #ifdef SECONDARY_MEMORY_NEEDED
3336 /* Some target macros SECONDARY_MEMORY_NEEDED (e.g. x86) are defined
3337 too conservatively. So we use the secondary memory only if there
3338 is no any alternative without reloads. */
3339 use_sec_mem_p
= false;
3341 use_sec_mem_p
= true;
3344 for (i
= 0; i
< n_operands
; i
++)
3345 if (! goal_alt_win
[i
] && ! goal_alt_match_win
[i
])
3347 use_sec_mem_p
= i
< n_operands
;
3352 rtx new_reg
, src
, dest
, rld
;
3353 enum machine_mode sec_mode
, rld_mode
;
3355 lra_assert (sec_mem_p
);
3356 lra_assert (curr_static_id
->operand
[0].type
== OP_OUT
3357 && curr_static_id
->operand
[1].type
== OP_IN
);
3358 dest
= *curr_id
->operand_loc
[0];
3359 src
= *curr_id
->operand_loc
[1];
3360 rld
= (GET_MODE_SIZE (GET_MODE (dest
)) <= GET_MODE_SIZE (GET_MODE (src
))
3362 rld_mode
= GET_MODE (rld
);
3363 #ifdef SECONDARY_MEMORY_NEEDED_MODE
3364 sec_mode
= SECONDARY_MEMORY_NEEDED_MODE (rld_mode
);
3366 sec_mode
= rld_mode
;
3368 new_reg
= lra_create_new_reg (sec_mode
, NULL_RTX
,
3369 NO_REGS
, "secondary");
3370 /* If the mode is changed, it should be wider. */
3371 lra_assert (GET_MODE_SIZE (sec_mode
) >= GET_MODE_SIZE (rld_mode
));
3372 if (sec_mode
!= rld_mode
)
3374 /* If the target says specifically to use another mode for
3375 secondary memory moves we can not reuse the original
3377 after
= emit_spill_move (false, new_reg
, dest
);
3378 lra_process_new_insns (curr_insn
, NULL
, after
,
3379 "Inserting the sec. move");
3380 /* We may have non null BEFORE here (e.g. after address
3382 push_to_sequence (before
);
3383 before
= emit_spill_move (true, new_reg
, src
);
3385 before
= get_insns ();
3387 lra_process_new_insns (curr_insn
, before
, NULL
, "Changing on");
3388 lra_set_insn_deleted (curr_insn
);
3390 else if (dest
== rld
)
3392 *curr_id
->operand_loc
[0] = new_reg
;
3393 after
= emit_spill_move (false, new_reg
, dest
);
3394 lra_process_new_insns (curr_insn
, NULL
, after
,
3395 "Inserting the sec. move");
3399 *curr_id
->operand_loc
[1] = new_reg
;
3400 /* See comments above. */
3401 push_to_sequence (before
);
3402 before
= emit_spill_move (true, new_reg
, src
);
3404 before
= get_insns ();
3406 lra_process_new_insns (curr_insn
, before
, NULL
,
3407 "Inserting the sec. move");
3409 lra_update_insn_regno_info (curr_insn
);
3414 lra_assert (goal_alt_number
>= 0);
3415 lra_set_used_insn_alternative (curr_insn
, goal_alt_number
);
3417 if (lra_dump_file
!= NULL
)
3421 fprintf (lra_dump_file
, " Choosing alt %d in insn %u:",
3422 goal_alt_number
, INSN_UID (curr_insn
));
3423 for (i
= 0; i
< n_operands
; i
++)
3425 p
= (curr_static_id
->operand_alternative
3426 [goal_alt_number
* n_operands
+ i
].constraint
);
3429 fprintf (lra_dump_file
, " (%d) ", i
);
3430 for (; *p
!= '\0' && *p
!= ',' && *p
!= '#'; p
++)
3431 fputc (*p
, lra_dump_file
);
3433 if (INSN_CODE (curr_insn
) >= 0
3434 && (p
= get_insn_name (INSN_CODE (curr_insn
))) != NULL
)
3435 fprintf (lra_dump_file
, " {%s}", p
);
3436 if (curr_id
->sp_offset
!= 0)
3437 fprintf (lra_dump_file
, " (sp_off=%" HOST_WIDE_INT_PRINT
"d)",
3438 curr_id
->sp_offset
);
3439 fprintf (lra_dump_file
, "\n");
3442 /* Right now, for any pair of operands I and J that are required to
3443 match, with J < I, goal_alt_matches[I] is J. Add I to
3444 goal_alt_matched[J]. */
3446 for (i
= 0; i
< n_operands
; i
++)
3447 if ((j
= goal_alt_matches
[i
]) >= 0)
3449 for (k
= 0; goal_alt_matched
[j
][k
] >= 0; k
++)
3451 /* We allow matching one output operand and several input
3454 || (curr_static_id
->operand
[j
].type
== OP_OUT
3455 && curr_static_id
->operand
[i
].type
== OP_IN
3456 && (curr_static_id
->operand
3457 [goal_alt_matched
[j
][0]].type
== OP_IN
)));
3458 goal_alt_matched
[j
][k
] = i
;
3459 goal_alt_matched
[j
][k
+ 1] = -1;
3462 for (i
= 0; i
< n_operands
; i
++)
3463 goal_alt_win
[i
] |= goal_alt_match_win
[i
];
3465 /* Any constants that aren't allowed and can't be reloaded into
3466 registers are here changed into memory references. */
3467 for (i
= 0; i
< n_operands
; i
++)
3468 if (goal_alt_win
[i
])
3471 enum reg_class new_class
;
3472 rtx reg
= *curr_id
->operand_loc
[i
];
3474 if (GET_CODE (reg
) == SUBREG
)
3475 reg
= SUBREG_REG (reg
);
3477 if (REG_P (reg
) && (regno
= REGNO (reg
)) >= FIRST_PSEUDO_REGISTER
)
3479 bool ok_p
= in_class_p (reg
, goal_alt
[i
], &new_class
);
3481 if (new_class
!= NO_REGS
&& get_reg_class (regno
) != new_class
)
3484 lra_change_class (regno
, new_class
, " Change to", true);
3490 const char *constraint
;
3492 rtx op
= *curr_id
->operand_loc
[i
];
3493 rtx subreg
= NULL_RTX
;
3494 enum machine_mode mode
= curr_operand_mode
[i
];
3496 if (GET_CODE (op
) == SUBREG
)
3499 op
= SUBREG_REG (op
);
3500 mode
= GET_MODE (op
);
3503 if (CONST_POOL_OK_P (mode
, op
)
3504 && ((targetm
.preferred_reload_class
3505 (op
, (enum reg_class
) goal_alt
[i
]) == NO_REGS
)
3506 || no_input_reloads_p
))
3508 rtx tem
= force_const_mem (mode
, op
);
3511 if (subreg
!= NULL_RTX
)
3512 tem
= gen_rtx_SUBREG (mode
, tem
, SUBREG_BYTE (subreg
));
3514 *curr_id
->operand_loc
[i
] = tem
;
3515 lra_update_dup (curr_id
, i
);
3516 process_address (i
, &before
, &after
);
3518 /* If the alternative accepts constant pool refs directly
3519 there will be no reload needed at all. */
3520 if (subreg
!= NULL_RTX
)
3522 /* Skip alternatives before the one requested. */
3523 constraint
= (curr_static_id
->operand_alternative
3524 [goal_alt_number
* n_operands
+ i
].constraint
);
3526 (c
= *constraint
) && c
!= ',' && c
!= '#';
3527 constraint
+= CONSTRAINT_LEN (c
, constraint
))
3529 enum constraint_num cn
= lookup_constraint (constraint
);
3530 if (insn_extra_memory_constraint (cn
)
3531 && satisfies_memory_constraint_p (tem
, cn
))
3534 if (c
== '\0' || c
== ',' || c
== '#')
3537 goal_alt_win
[i
] = true;
3541 for (i
= 0; i
< n_operands
; i
++)
3544 bool optional_p
= false;
3546 rtx op
= *curr_id
->operand_loc
[i
];
3548 if (goal_alt_win
[i
])
3550 if (goal_alt
[i
] == NO_REGS
3552 /* When we assign NO_REGS it means that we will not
3553 assign a hard register to the scratch pseudo by
3554 assigment pass and the scratch pseudo will be
3555 spilled. Spilled scratch pseudos are transformed
3556 back to scratches at the LRA end. */
3557 && lra_former_scratch_operand_p (curr_insn
, i
))
3559 int regno
= REGNO (op
);
3560 lra_change_class (regno
, NO_REGS
, " Change to", true);
3561 if (lra_get_regno_hard_regno (regno
) >= 0)
3562 /* We don't have to mark all insn affected by the
3563 spilled pseudo as there is only one such insn, the
3565 reg_renumber
[regno
] = -1;
3567 /* We can do an optional reload. If the pseudo got a hard
3568 reg, we might improve the code through inheritance. If
3569 it does not get a hard register we coalesce memory/memory
3570 moves later. Ignore move insns to avoid cycling. */
3572 && lra_undo_inheritance_iter
< LRA_MAX_INHERITANCE_PASSES
3573 && goal_alt
[i
] != NO_REGS
&& REG_P (op
)
3574 && (regno
= REGNO (op
)) >= FIRST_PSEUDO_REGISTER
3575 && regno
< new_regno_start
3576 && ! lra_former_scratch_p (regno
)
3577 && reg_renumber
[regno
] < 0
3578 && (curr_insn_set
== NULL_RTX
3579 || !((REG_P (SET_SRC (curr_insn_set
))
3580 || MEM_P (SET_SRC (curr_insn_set
))
3581 || GET_CODE (SET_SRC (curr_insn_set
)) == SUBREG
)
3582 && (REG_P (SET_DEST (curr_insn_set
))
3583 || MEM_P (SET_DEST (curr_insn_set
))
3584 || GET_CODE (SET_DEST (curr_insn_set
)) == SUBREG
))))
3590 /* Operands that match previous ones have already been handled. */
3591 if (goal_alt_matches
[i
] >= 0)
3594 /* We should not have an operand with a non-offsettable address
3595 appearing where an offsettable address will do. It also may
3596 be a case when the address should be special in other words
3597 not a general one (e.g. it needs no index reg). */
3598 if (goal_alt_matched
[i
][0] == -1 && goal_alt_offmemok
[i
] && MEM_P (op
))
3600 enum reg_class rclass
;
3601 rtx
*loc
= &XEXP (op
, 0);
3602 enum rtx_code code
= GET_CODE (*loc
);
3604 push_to_sequence (before
);
3605 rclass
= base_reg_class (GET_MODE (op
), MEM_ADDR_SPACE (op
),
3607 if (GET_RTX_CLASS (code
) == RTX_AUTOINC
)
3608 new_reg
= emit_inc (rclass
, *loc
, *loc
,
3609 /* This value does not matter for MODIFY. */
3610 GET_MODE_SIZE (GET_MODE (op
)));
3611 else if (get_reload_reg (OP_IN
, Pmode
, *loc
, rclass
, FALSE
,
3612 "offsetable address", &new_reg
))
3613 lra_emit_move (new_reg
, *loc
);
3614 before
= get_insns ();
3617 lra_update_dup (curr_id
, i
);
3619 else if (goal_alt_matched
[i
][0] == -1)
3621 enum machine_mode mode
;
3623 int hard_regno
, byte
;
3624 enum op_type type
= curr_static_id
->operand
[i
].type
;
3626 loc
= curr_id
->operand_loc
[i
];
3627 mode
= curr_operand_mode
[i
];
3628 if (GET_CODE (*loc
) == SUBREG
)
3630 reg
= SUBREG_REG (*loc
);
3631 byte
= SUBREG_BYTE (*loc
);
3633 /* Strict_low_part requires reload the register not
3634 the sub-register. */
3635 && (curr_static_id
->operand
[i
].strict_low
3636 || (GET_MODE_SIZE (mode
)
3637 <= GET_MODE_SIZE (GET_MODE (reg
))
3639 = get_try_hard_regno (REGNO (reg
))) >= 0
3640 && (simplify_subreg_regno
3642 GET_MODE (reg
), byte
, mode
) < 0)
3643 && (goal_alt
[i
] == NO_REGS
3644 || (simplify_subreg_regno
3645 (ira_class_hard_regs
[goal_alt
[i
]][0],
3646 GET_MODE (reg
), byte
, mode
) >= 0)))))
3648 loc
= &SUBREG_REG (*loc
);
3649 mode
= GET_MODE (*loc
);
3653 if (get_reload_reg (type
, mode
, old
, goal_alt
[i
],
3654 loc
!= curr_id
->operand_loc
[i
], "", &new_reg
)
3657 push_to_sequence (before
);
3658 lra_emit_move (new_reg
, old
);
3659 before
= get_insns ();
3664 && find_reg_note (curr_insn
, REG_UNUSED
, old
) == NULL_RTX
)
3667 lra_emit_move (type
== OP_INOUT
? copy_rtx (old
) : old
, new_reg
);
3669 after
= get_insns ();
3673 for (j
= 0; j
< goal_alt_dont_inherit_ops_num
; j
++)
3674 if (goal_alt_dont_inherit_ops
[j
] == i
)
3676 lra_set_regno_unique_value (REGNO (new_reg
));
3679 lra_update_dup (curr_id
, i
);
3681 else if (curr_static_id
->operand
[i
].type
== OP_IN
3682 && (curr_static_id
->operand
[goal_alt_matched
[i
][0]].type
3685 /* generate reloads for input and matched outputs. */
3686 match_inputs
[0] = i
;
3687 match_inputs
[1] = -1;
3688 match_reload (goal_alt_matched
[i
][0], match_inputs
,
3689 goal_alt
[i
], &before
, &after
);
3691 else if (curr_static_id
->operand
[i
].type
== OP_OUT
3692 && (curr_static_id
->operand
[goal_alt_matched
[i
][0]].type
3694 /* Generate reloads for output and matched inputs. */
3695 match_reload (i
, goal_alt_matched
[i
], goal_alt
[i
], &before
, &after
);
3696 else if (curr_static_id
->operand
[i
].type
== OP_IN
3697 && (curr_static_id
->operand
[goal_alt_matched
[i
][0]].type
3700 /* Generate reloads for matched inputs. */
3701 match_inputs
[0] = i
;
3702 for (j
= 0; (k
= goal_alt_matched
[i
][j
]) >= 0; j
++)
3703 match_inputs
[j
+ 1] = k
;
3704 match_inputs
[j
+ 1] = -1;
3705 match_reload (-1, match_inputs
, goal_alt
[i
], &before
, &after
);
3708 /* We must generate code in any case when function
3709 process_alt_operands decides that it is possible. */
3713 lra_assert (REG_P (op
));
3715 op
= *curr_id
->operand_loc
[i
]; /* Substitution. */
3716 if (GET_CODE (op
) == SUBREG
)
3717 op
= SUBREG_REG (op
);
3718 gcc_assert (REG_P (op
) && (int) REGNO (op
) >= new_regno_start
);
3719 bitmap_set_bit (&lra_optional_reload_pseudos
, REGNO (op
));
3720 lra_reg_info
[REGNO (op
)].restore_regno
= regno
;
3721 if (lra_dump_file
!= NULL
)
3722 fprintf (lra_dump_file
,
3723 " Making reload reg %d for reg %d optional\n",
3727 if (before
!= NULL_RTX
|| after
!= NULL_RTX
3728 || max_regno_before
!= max_reg_num ())
3732 lra_update_operator_dups (curr_id
);
3733 /* Something changes -- process the insn. */
3734 lra_update_insn_regno_info (curr_insn
);
3736 lra_process_new_insns (curr_insn
, before
, after
, "Inserting insn reload");
3740 /* Return true if X is in LIST. */
3742 in_list_p (rtx x
, rtx list
)
3744 for (; list
!= NULL_RTX
; list
= XEXP (list
, 1))
3745 if (XEXP (list
, 0) == x
)
3750 /* Return true if X contains an allocatable hard register (if
3751 HARD_REG_P) or a (spilled if SPILLED_P) pseudo. */
3753 contains_reg_p (rtx x
, bool hard_reg_p
, bool spilled_p
)
3759 code
= GET_CODE (x
);
3762 int regno
= REGNO (x
);
3763 HARD_REG_SET alloc_regs
;
3767 if (regno
>= FIRST_PSEUDO_REGISTER
)
3768 regno
= lra_get_regno_hard_regno (regno
);
3771 COMPL_HARD_REG_SET (alloc_regs
, lra_no_alloc_regs
);
3772 return overlaps_hard_reg_set_p (alloc_regs
, GET_MODE (x
), regno
);
3776 if (regno
< FIRST_PSEUDO_REGISTER
)
3780 return lra_get_regno_hard_regno (regno
) < 0;
3783 fmt
= GET_RTX_FORMAT (code
);
3784 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
3788 if (contains_reg_p (XEXP (x
, i
), hard_reg_p
, spilled_p
))
3791 else if (fmt
[i
] == 'E')
3793 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3794 if (contains_reg_p (XVECEXP (x
, i
, j
), hard_reg_p
, spilled_p
))
3801 /* Process all regs in location *LOC and change them on equivalent
3802 substitution. Return true if any change was done. */
3804 loc_equivalence_change_p (rtx
*loc
)
3806 rtx subst
, reg
, x
= *loc
;
3807 bool result
= false;
3808 enum rtx_code code
= GET_CODE (x
);
3814 reg
= SUBREG_REG (x
);
3815 if ((subst
= get_equiv_with_elimination (reg
, curr_insn
)) != reg
3816 && GET_MODE (subst
) == VOIDmode
)
3818 /* We cannot reload debug location. Simplify subreg here
3819 while we know the inner mode. */
3820 *loc
= simplify_gen_subreg (GET_MODE (x
), subst
,
3821 GET_MODE (reg
), SUBREG_BYTE (x
));
3825 if (code
== REG
&& (subst
= get_equiv_with_elimination (x
, curr_insn
)) != x
)
3831 /* Scan all the operand sub-expressions. */
3832 fmt
= GET_RTX_FORMAT (code
);
3833 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
3836 result
= loc_equivalence_change_p (&XEXP (x
, i
)) || result
;
3837 else if (fmt
[i
] == 'E')
3838 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3840 = loc_equivalence_change_p (&XVECEXP (x
, i
, j
)) || result
;
3845 /* Similar to loc_equivalence_change_p, but for use as
3846 simplify_replace_fn_rtx callback. DATA is insn for which the
3847 elimination is done. If it null we don't do the elimination. */
3849 loc_equivalence_callback (rtx loc
, const_rtx
, void *data
)
3854 rtx subst
= (data
== NULL
3855 ? get_equiv (loc
) : get_equiv_with_elimination (loc
, (rtx_insn
*) data
));
3862 /* Maximum number of generated reload insns per an insn. It is for
3863 preventing this pass cycling in a bug case. */
3864 #define MAX_RELOAD_INSNS_NUMBER LRA_MAX_INSN_RELOADS
3866 /* The current iteration number of this LRA pass. */
3867 int lra_constraint_iter
;
3869 /* The current iteration number of this LRA pass after the last spill
3871 int lra_constraint_iter_after_spill
;
3873 /* True if we substituted equiv which needs checking register
3874 allocation correctness because the equivalent value contains
3875 allocatable hard registers or when we restore multi-register
3877 bool lra_risky_transformations_p
;
3879 /* Return true if REGNO is referenced in more than one block. */
3881 multi_block_pseudo_p (int regno
)
3883 basic_block bb
= NULL
;
3887 if (regno
< FIRST_PSEUDO_REGISTER
)
3890 EXECUTE_IF_SET_IN_BITMAP (&lra_reg_info
[regno
].insn_bitmap
, 0, uid
, bi
)
3892 bb
= BLOCK_FOR_INSN (lra_insn_recog_data
[uid
]->insn
);
3893 else if (BLOCK_FOR_INSN (lra_insn_recog_data
[uid
]->insn
) != bb
)
3898 /* Return true if LIST contains a deleted insn. */
3900 contains_deleted_insn_p (rtx list
)
3902 for (; list
!= NULL_RTX
; list
= XEXP (list
, 1))
3903 if (NOTE_P (XEXP (list
, 0))
3904 && NOTE_KIND (XEXP (list
, 0)) == NOTE_INSN_DELETED
)
3909 /* Return true if X contains a pseudo dying in INSN. */
3911 dead_pseudo_p (rtx x
, rtx insn
)
3918 return (insn
!= NULL_RTX
3919 && find_regno_note (insn
, REG_DEAD
, REGNO (x
)) != NULL_RTX
);
3920 code
= GET_CODE (x
);
3921 fmt
= GET_RTX_FORMAT (code
);
3922 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
3926 if (dead_pseudo_p (XEXP (x
, i
), insn
))
3929 else if (fmt
[i
] == 'E')
3931 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3932 if (dead_pseudo_p (XVECEXP (x
, i
, j
), insn
))
3939 /* Return true if INSN contains a dying pseudo in INSN right hand
3942 insn_rhs_dead_pseudo_p (rtx insn
)
3944 rtx set
= single_set (insn
);
3946 gcc_assert (set
!= NULL
);
3947 return dead_pseudo_p (SET_SRC (set
), insn
);
3950 /* Return true if any init insn of REGNO contains a dying pseudo in
3951 insn right hand side. */
3953 init_insn_rhs_dead_pseudo_p (int regno
)
3955 rtx insns
= ira_reg_equiv
[regno
].init_insns
;
3960 return insn_rhs_dead_pseudo_p (insns
);
3961 for (; insns
!= NULL_RTX
; insns
= XEXP (insns
, 1))
3962 if (insn_rhs_dead_pseudo_p (XEXP (insns
, 0)))
3967 /* Return TRUE if REGNO has a reverse equivalence. The equivalence is
3968 reverse only if we have one init insn with given REGNO as a
3971 reverse_equiv_p (int regno
)
3975 if ((insns
= ira_reg_equiv
[regno
].init_insns
) == NULL_RTX
)
3977 if (! INSN_P (XEXP (insns
, 0))
3978 || XEXP (insns
, 1) != NULL_RTX
)
3980 if ((set
= single_set (XEXP (insns
, 0))) == NULL_RTX
)
3982 return REG_P (SET_SRC (set
)) && (int) REGNO (SET_SRC (set
)) == regno
;
3985 /* Return TRUE if REGNO was reloaded in an equivalence init insn. We
3986 call this function only for non-reverse equivalence. */
3988 contains_reloaded_insn_p (int regno
)
3991 rtx list
= ira_reg_equiv
[regno
].init_insns
;
3993 for (; list
!= NULL_RTX
; list
= XEXP (list
, 1))
3994 if ((set
= single_set (XEXP (list
, 0))) == NULL_RTX
3995 || ! REG_P (SET_DEST (set
))
3996 || (int) REGNO (SET_DEST (set
)) != regno
)
4001 /* Entry function of LRA constraint pass. Return true if the
4002 constraint pass did change the code. */
4004 lra_constraints (bool first_p
)
4007 int i
, hard_regno
, new_insns_num
;
4008 unsigned int min_len
, new_min_len
, uid
;
4009 rtx set
, x
, reg
, dest_reg
;
4010 basic_block last_bb
;
4011 bitmap_head equiv_insn_bitmap
;
4014 lra_constraint_iter
++;
4015 if (lra_dump_file
!= NULL
)
4016 fprintf (lra_dump_file
, "\n********** Local #%d: **********\n\n",
4017 lra_constraint_iter
);
4018 lra_constraint_iter_after_spill
++;
4019 if (lra_constraint_iter_after_spill
> LRA_MAX_CONSTRAINT_ITERATION_NUMBER
)
4021 ("Maximum number of LRA constraint passes is achieved (%d)\n",
4022 LRA_MAX_CONSTRAINT_ITERATION_NUMBER
);
4024 lra_risky_transformations_p
= false;
4025 new_insn_uid_start
= get_max_uid ();
4026 new_regno_start
= first_p
? lra_constraint_new_regno_start
: max_reg_num ();
4027 /* Mark used hard regs for target stack size calulations. */
4028 for (i
= FIRST_PSEUDO_REGISTER
; i
< new_regno_start
; i
++)
4029 if (lra_reg_info
[i
].nrefs
!= 0
4030 && (hard_regno
= lra_get_regno_hard_regno (i
)) >= 0)
4034 nregs
= hard_regno_nregs
[hard_regno
][lra_reg_info
[i
].biggest_mode
];
4035 for (j
= 0; j
< nregs
; j
++)
4036 df_set_regs_ever_live (hard_regno
+ j
, true);
4038 /* Do elimination before the equivalence processing as we can spill
4039 some pseudos during elimination. */
4040 lra_eliminate (false, first_p
);
4041 bitmap_initialize (&equiv_insn_bitmap
, ®_obstack
);
4042 for (i
= FIRST_PSEUDO_REGISTER
; i
< new_regno_start
; i
++)
4043 if (lra_reg_info
[i
].nrefs
!= 0)
4045 ira_reg_equiv
[i
].profitable_p
= true;
4046 reg
= regno_reg_rtx
[i
];
4047 if (lra_get_regno_hard_regno (i
) < 0 && (x
= get_equiv (reg
)) != reg
)
4049 bool pseudo_p
= contains_reg_p (x
, false, false);
4051 /* After RTL transformation, we can not guarantee that
4052 pseudo in the substitution was not reloaded which might
4053 make equivalence invalid. For example, in reverse
4060 the memory address register was reloaded before the 2nd
4062 if ((! first_p
&& pseudo_p
)
4063 /* We don't use DF for compilation speed sake. So it
4064 is problematic to update live info when we use an
4065 equivalence containing pseudos in more than one
4067 || (pseudo_p
&& multi_block_pseudo_p (i
))
4068 /* If an init insn was deleted for some reason, cancel
4069 the equiv. We could update the equiv insns after
4070 transformations including an equiv insn deletion
4071 but it is not worthy as such cases are extremely
4073 || contains_deleted_insn_p (ira_reg_equiv
[i
].init_insns
)
4074 /* If it is not a reverse equivalence, we check that a
4075 pseudo in rhs of the init insn is not dying in the
4076 insn. Otherwise, the live info at the beginning of
4077 the corresponding BB might be wrong after we
4078 removed the insn. When the equiv can be a
4079 constant, the right hand side of the init insn can
4081 || (! reverse_equiv_p (i
)
4082 && (init_insn_rhs_dead_pseudo_p (i
)
4083 /* If we reloaded the pseudo in an equivalence
4084 init insn, we can not remove the equiv init
4085 insns and the init insns might write into
4086 const memory in this case. */
4087 || contains_reloaded_insn_p (i
)))
4088 /* Prevent access beyond equivalent memory for
4089 paradoxical subregs. */
4091 && (GET_MODE_SIZE (lra_reg_info
[i
].biggest_mode
)
4092 > GET_MODE_SIZE (GET_MODE (x
)))))
4093 ira_reg_equiv
[i
].defined_p
= false;
4094 if (contains_reg_p (x
, false, true))
4095 ira_reg_equiv
[i
].profitable_p
= false;
4096 if (get_equiv (reg
) != reg
)
4097 bitmap_ior_into (&equiv_insn_bitmap
, &lra_reg_info
[i
].insn_bitmap
);
4100 for (i
= FIRST_PSEUDO_REGISTER
; i
< new_regno_start
; i
++)
4102 /* We should add all insns containing pseudos which should be
4103 substituted by their equivalences. */
4104 EXECUTE_IF_SET_IN_BITMAP (&equiv_insn_bitmap
, 0, uid
, bi
)
4105 lra_push_insn_by_uid (uid
);
4106 min_len
= lra_insn_stack_length ();
4110 while ((new_min_len
= lra_insn_stack_length ()) != 0)
4112 curr_insn
= lra_pop_insn ();
4114 curr_bb
= BLOCK_FOR_INSN (curr_insn
);
4115 if (curr_bb
!= last_bb
)
4118 bb_reload_num
= lra_curr_reload_num
;
4120 if (min_len
> new_min_len
)
4122 min_len
= new_min_len
;
4125 if (new_insns_num
> MAX_RELOAD_INSNS_NUMBER
)
4127 ("Max. number of generated reload insns per insn is achieved (%d)\n",
4128 MAX_RELOAD_INSNS_NUMBER
);
4130 if (DEBUG_INSN_P (curr_insn
))
4132 /* We need to check equivalence in debug insn and change
4133 pseudo to the equivalent value if necessary. */
4134 curr_id
= lra_get_insn_recog_data (curr_insn
);
4135 if (bitmap_bit_p (&equiv_insn_bitmap
, INSN_UID (curr_insn
)))
4137 rtx old
= *curr_id
->operand_loc
[0];
4138 *curr_id
->operand_loc
[0]
4139 = simplify_replace_fn_rtx (old
, NULL_RTX
,
4140 loc_equivalence_callback
, curr_insn
);
4141 if (old
!= *curr_id
->operand_loc
[0])
4143 lra_update_insn_regno_info (curr_insn
);
4148 else if (INSN_P (curr_insn
))
4150 if ((set
= single_set (curr_insn
)) != NULL_RTX
)
4152 dest_reg
= SET_DEST (set
);
4153 /* The equivalence pseudo could be set up as SUBREG in a
4154 case when it is a call restore insn in a mode
4155 different from the pseudo mode. */
4156 if (GET_CODE (dest_reg
) == SUBREG
)
4157 dest_reg
= SUBREG_REG (dest_reg
);
4158 if ((REG_P (dest_reg
)
4159 && (x
= get_equiv (dest_reg
)) != dest_reg
4160 /* Remove insns which set up a pseudo whose value
4161 can not be changed. Such insns might be not in
4162 init_insns because we don't update equiv data
4163 during insn transformations.
4165 As an example, let suppose that a pseudo got
4166 hard register and on the 1st pass was not
4167 changed to equivalent constant. We generate an
4168 additional insn setting up the pseudo because of
4169 secondary memory movement. Then the pseudo is
4170 spilled and we use the equiv constant. In this
4171 case we should remove the additional insn and
4172 this insn is not init_insns list. */
4173 && (! MEM_P (x
) || MEM_READONLY_P (x
)
4174 /* Check that this is actually an insn setting
4175 up the equivalence. */
4176 || in_list_p (curr_insn
,
4178 [REGNO (dest_reg
)].init_insns
)))
4179 || (((x
= get_equiv (SET_SRC (set
))) != SET_SRC (set
))
4180 && in_list_p (curr_insn
,
4182 [REGNO (SET_SRC (set
))].init_insns
)))
4184 /* This is equiv init insn of pseudo which did not get a
4185 hard register -- remove the insn. */
4186 if (lra_dump_file
!= NULL
)
4188 fprintf (lra_dump_file
,
4189 " Removing equiv init insn %i (freq=%d)\n",
4190 INSN_UID (curr_insn
),
4191 REG_FREQ_FROM_BB (BLOCK_FOR_INSN (curr_insn
)));
4192 dump_insn_slim (lra_dump_file
, curr_insn
);
4194 if (contains_reg_p (x
, true, false))
4195 lra_risky_transformations_p
= true;
4196 lra_set_insn_deleted (curr_insn
);
4200 curr_id
= lra_get_insn_recog_data (curr_insn
);
4201 curr_static_id
= curr_id
->insn_static_data
;
4202 init_curr_insn_input_reloads ();
4203 init_curr_operand_mode ();
4204 if (curr_insn_transform ())
4206 /* Check non-transformed insns too for equiv change as USE
4207 or CLOBBER don't need reloads but can contain pseudos
4208 being changed on their equivalences. */
4209 else if (bitmap_bit_p (&equiv_insn_bitmap
, INSN_UID (curr_insn
))
4210 && loc_equivalence_change_p (&PATTERN (curr_insn
)))
4212 lra_update_insn_regno_info (curr_insn
);
4217 bitmap_clear (&equiv_insn_bitmap
);
4218 /* If we used a new hard regno, changed_p should be true because the
4219 hard reg is assigned to a new pseudo. */
4220 #ifdef ENABLE_CHECKING
4223 for (i
= FIRST_PSEUDO_REGISTER
; i
< new_regno_start
; i
++)
4224 if (lra_reg_info
[i
].nrefs
!= 0
4225 && (hard_regno
= lra_get_regno_hard_regno (i
)) >= 0)
4227 int j
, nregs
= hard_regno_nregs
[hard_regno
][PSEUDO_REGNO_MODE (i
)];
4229 for (j
= 0; j
< nregs
; j
++)
4230 lra_assert (df_regs_ever_live_p (hard_regno
+ j
));
4237 /* Initiate the LRA constraint pass. It is done once per
4240 lra_constraints_init (void)
4244 /* Finalize the LRA constraint pass. It is done once per
4247 lra_constraints_finish (void)
4253 /* This page contains code to do inheritance/split
4256 /* Number of reloads passed so far in current EBB. */
4257 static int reloads_num
;
4259 /* Number of calls passed so far in current EBB. */
4260 static int calls_num
;
4262 /* Current reload pseudo check for validity of elements in
4264 static int curr_usage_insns_check
;
4266 /* Info about last usage of registers in EBB to do inheritance/split
4267 transformation. Inheritance transformation is done from a spilled
4268 pseudo and split transformations from a hard register or a pseudo
4269 assigned to a hard register. */
4272 /* If the value is equal to CURR_USAGE_INSNS_CHECK, then the member
4273 value INSNS is valid. The insns is chain of optional debug insns
4274 and a finishing non-debug insn using the corresponding reg. The
4275 value is also used to mark the registers which are set up in the
4276 current insn. The negated insn uid is used for this. */
4278 /* Value of global reloads_num at the last insn in INSNS. */
4280 /* Value of global reloads_nums at the last insn in INSNS. */
4282 /* It can be true only for splitting. And it means that the restore
4283 insn should be put after insn given by the following member. */
4285 /* Next insns in the current EBB which use the original reg and the
4286 original reg value is not changed between the current insn and
4287 the next insns. In order words, e.g. for inheritance, if we need
4288 to use the original reg value again in the next insns we can try
4289 to use the value in a hard register from a reload insn of the
4294 /* Map: regno -> corresponding pseudo usage insns. */
4295 static struct usage_insns
*usage_insns
;
4298 setup_next_usage_insn (int regno
, rtx insn
, int reloads_num
, bool after_p
)
4300 usage_insns
[regno
].check
= curr_usage_insns_check
;
4301 usage_insns
[regno
].insns
= insn
;
4302 usage_insns
[regno
].reloads_num
= reloads_num
;
4303 usage_insns
[regno
].calls_num
= calls_num
;
4304 usage_insns
[regno
].after_p
= after_p
;
4307 /* The function is used to form list REGNO usages which consists of
4308 optional debug insns finished by a non-debug insn using REGNO.
4309 RELOADS_NUM is current number of reload insns processed so far. */
4311 add_next_usage_insn (int regno
, rtx insn
, int reloads_num
)
4313 rtx next_usage_insns
;
4315 if (usage_insns
[regno
].check
== curr_usage_insns_check
4316 && (next_usage_insns
= usage_insns
[regno
].insns
) != NULL_RTX
4317 && DEBUG_INSN_P (insn
))
4319 /* Check that we did not add the debug insn yet. */
4320 if (next_usage_insns
!= insn
4321 && (GET_CODE (next_usage_insns
) != INSN_LIST
4322 || XEXP (next_usage_insns
, 0) != insn
))
4323 usage_insns
[regno
].insns
= gen_rtx_INSN_LIST (VOIDmode
, insn
,
4326 else if (NONDEBUG_INSN_P (insn
))
4327 setup_next_usage_insn (regno
, insn
, reloads_num
, false);
4329 usage_insns
[regno
].check
= 0;
4332 /* Replace all references to register OLD_REGNO in *LOC with pseudo
4333 register NEW_REG. Return true if any change was made. */
4335 substitute_pseudo (rtx
*loc
, int old_regno
, rtx new_reg
)
4338 bool result
= false;
4346 code
= GET_CODE (x
);
4347 if (code
== REG
&& (int) REGNO (x
) == old_regno
)
4349 enum machine_mode mode
= GET_MODE (*loc
);
4350 enum machine_mode inner_mode
= GET_MODE (new_reg
);
4352 if (mode
!= inner_mode
)
4354 if (GET_MODE_SIZE (mode
) >= GET_MODE_SIZE (inner_mode
)
4355 || ! SCALAR_INT_MODE_P (inner_mode
))
4356 new_reg
= gen_rtx_SUBREG (mode
, new_reg
, 0);
4358 new_reg
= gen_lowpart_SUBREG (mode
, new_reg
);
4364 /* Scan all the operand sub-expressions. */
4365 fmt
= GET_RTX_FORMAT (code
);
4366 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
4370 if (substitute_pseudo (&XEXP (x
, i
), old_regno
, new_reg
))
4373 else if (fmt
[i
] == 'E')
4375 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
4376 if (substitute_pseudo (&XVECEXP (x
, i
, j
), old_regno
, new_reg
))
4383 /* Call substitute_pseudo within an insn. This won't update the insn ptr,
4384 just the contents of the insn. */
4387 substitute_pseudo_within_insn (rtx_insn
*insn
, int old_regno
, rtx new_reg
)
4390 return substitute_pseudo (&loc
, old_regno
, new_reg
);
4393 /* Return first non-debug insn in list USAGE_INSNS. */
4395 skip_usage_debug_insns (rtx usage_insns
)
4399 /* Skip debug insns. */
4400 for (insn
= usage_insns
;
4401 insn
!= NULL_RTX
&& GET_CODE (insn
) == INSN_LIST
;
4402 insn
= XEXP (insn
, 1))
4407 /* Return true if we need secondary memory moves for insn in
4408 USAGE_INSNS after inserting inherited pseudo of class INHER_CL
4411 check_secondary_memory_needed_p (enum reg_class inher_cl ATTRIBUTE_UNUSED
,
4412 rtx usage_insns ATTRIBUTE_UNUSED
)
4414 #ifndef SECONDARY_MEMORY_NEEDED
4417 rtx insn
, set
, dest
;
4420 if (inher_cl
== ALL_REGS
4421 || (insn
= skip_usage_debug_insns (usage_insns
)) == NULL_RTX
)
4423 lra_assert (INSN_P (insn
));
4424 if ((set
= single_set (insn
)) == NULL_RTX
|| ! REG_P (SET_DEST (set
)))
4426 dest
= SET_DEST (set
);
4429 lra_assert (inher_cl
!= NO_REGS
);
4430 cl
= get_reg_class (REGNO (dest
));
4431 return (cl
!= NO_REGS
&& cl
!= ALL_REGS
4432 && SECONDARY_MEMORY_NEEDED (inher_cl
, cl
, GET_MODE (dest
)));
4436 /* Registers involved in inheritance/split in the current EBB
4437 (inheritance/split pseudos and original registers). */
4438 static bitmap_head check_only_regs
;
4440 /* Do inheritance transformations for insn INSN, which defines (if
4441 DEF_P) or uses ORIGINAL_REGNO. NEXT_USAGE_INSNS specifies which
4442 instruction in the EBB next uses ORIGINAL_REGNO; it has the same
4443 form as the "insns" field of usage_insns. Return true if we
4444 succeed in such transformation.
4446 The transformations look like:
4449 ... p <- i (new insn)
4451 <- ... p ... <- ... i ...
4453 ... i <- p (new insn)
4454 <- ... p ... <- ... i ...
4456 <- ... p ... <- ... i ...
4457 where p is a spilled original pseudo and i is a new inheritance pseudo.
4460 The inheritance pseudo has the smallest class of two classes CL and
4461 class of ORIGINAL REGNO. */
4463 inherit_reload_reg (bool def_p
, int original_regno
,
4464 enum reg_class cl
, rtx_insn
*insn
, rtx next_usage_insns
)
4466 if (optimize_function_for_size_p (cfun
))
4469 enum reg_class rclass
= lra_get_allocno_class (original_regno
);
4470 rtx original_reg
= regno_reg_rtx
[original_regno
];
4471 rtx new_reg
, usage_insn
;
4472 rtx_insn
*new_insns
;
4474 lra_assert (! usage_insns
[original_regno
].after_p
);
4475 if (lra_dump_file
!= NULL
)
4476 fprintf (lra_dump_file
,
4477 " <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<\n");
4478 if (! ira_reg_classes_intersect_p
[cl
][rclass
])
4480 if (lra_dump_file
!= NULL
)
4482 fprintf (lra_dump_file
,
4483 " Rejecting inheritance for %d "
4484 "because of disjoint classes %s and %s\n",
4485 original_regno
, reg_class_names
[cl
],
4486 reg_class_names
[rclass
]);
4487 fprintf (lra_dump_file
,
4488 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
4492 if ((ira_class_subset_p
[cl
][rclass
] && cl
!= rclass
)
4493 /* We don't use a subset of two classes because it can be
4494 NO_REGS. This transformation is still profitable in most
4495 cases even if the classes are not intersected as register
4496 move is probably cheaper than a memory load. */
4497 || ira_class_hard_regs_num
[cl
] < ira_class_hard_regs_num
[rclass
])
4499 if (lra_dump_file
!= NULL
)
4500 fprintf (lra_dump_file
, " Use smallest class of %s and %s\n",
4501 reg_class_names
[cl
], reg_class_names
[rclass
]);
4505 if (check_secondary_memory_needed_p (rclass
, next_usage_insns
))
4507 /* Reject inheritance resulting in secondary memory moves.
4508 Otherwise, there is a danger in LRA cycling. Also such
4509 transformation will be unprofitable. */
4510 if (lra_dump_file
!= NULL
)
4512 rtx insn
= skip_usage_debug_insns (next_usage_insns
);
4513 rtx set
= single_set (insn
);
4515 lra_assert (set
!= NULL_RTX
);
4517 rtx dest
= SET_DEST (set
);
4519 lra_assert (REG_P (dest
));
4520 fprintf (lra_dump_file
,
4521 " Rejecting inheritance for insn %d(%s)<-%d(%s) "
4522 "as secondary mem is needed\n",
4523 REGNO (dest
), reg_class_names
[get_reg_class (REGNO (dest
))],
4524 original_regno
, reg_class_names
[rclass
]);
4525 fprintf (lra_dump_file
,
4526 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
4530 new_reg
= lra_create_new_reg (GET_MODE (original_reg
), original_reg
,
4531 rclass
, "inheritance");
4534 lra_emit_move (original_reg
, new_reg
);
4536 lra_emit_move (new_reg
, original_reg
);
4537 new_insns
= get_insns ();
4539 if (NEXT_INSN (new_insns
) != NULL_RTX
)
4541 if (lra_dump_file
!= NULL
)
4543 fprintf (lra_dump_file
,
4544 " Rejecting inheritance %d->%d "
4545 "as it results in 2 or more insns:\n",
4546 original_regno
, REGNO (new_reg
));
4547 dump_rtl_slim (lra_dump_file
, new_insns
, NULL_RTX
, -1, 0);
4548 fprintf (lra_dump_file
,
4549 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
4553 substitute_pseudo_within_insn (insn
, original_regno
, new_reg
);
4554 lra_update_insn_regno_info (insn
);
4556 /* We now have a new usage insn for original regno. */
4557 setup_next_usage_insn (original_regno
, new_insns
, reloads_num
, false);
4558 if (lra_dump_file
!= NULL
)
4559 fprintf (lra_dump_file
, " Original reg change %d->%d (bb%d):\n",
4560 original_regno
, REGNO (new_reg
), BLOCK_FOR_INSN (insn
)->index
);
4561 lra_reg_info
[REGNO (new_reg
)].restore_regno
= original_regno
;
4562 bitmap_set_bit (&check_only_regs
, REGNO (new_reg
));
4563 bitmap_set_bit (&check_only_regs
, original_regno
);
4564 bitmap_set_bit (&lra_inheritance_pseudos
, REGNO (new_reg
));
4566 lra_process_new_insns (insn
, NULL
, new_insns
,
4567 "Add original<-inheritance");
4569 lra_process_new_insns (insn
, new_insns
, NULL
,
4570 "Add inheritance<-original");
4571 while (next_usage_insns
!= NULL_RTX
)
4573 if (GET_CODE (next_usage_insns
) != INSN_LIST
)
4575 usage_insn
= next_usage_insns
;
4576 lra_assert (NONDEBUG_INSN_P (usage_insn
));
4577 next_usage_insns
= NULL
;
4581 usage_insn
= XEXP (next_usage_insns
, 0);
4582 lra_assert (DEBUG_INSN_P (usage_insn
));
4583 next_usage_insns
= XEXP (next_usage_insns
, 1);
4585 substitute_pseudo (&usage_insn
, original_regno
, new_reg
);
4586 lra_update_insn_regno_info (as_a
<rtx_insn
*> (usage_insn
));
4587 if (lra_dump_file
!= NULL
)
4589 fprintf (lra_dump_file
,
4590 " Inheritance reuse change %d->%d (bb%d):\n",
4591 original_regno
, REGNO (new_reg
),
4592 BLOCK_FOR_INSN (usage_insn
)->index
);
4593 dump_insn_slim (lra_dump_file
, usage_insn
);
4596 if (lra_dump_file
!= NULL
)
4597 fprintf (lra_dump_file
,
4598 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
4602 /* Return true if we need a caller save/restore for pseudo REGNO which
4603 was assigned to a hard register. */
4605 need_for_call_save_p (int regno
)
4607 lra_assert (regno
>= FIRST_PSEUDO_REGISTER
&& reg_renumber
[regno
] >= 0);
4608 return (usage_insns
[regno
].calls_num
< calls_num
4609 && (overlaps_hard_reg_set_p
4610 ((flag_use_caller_save
&&
4611 ! hard_reg_set_empty_p (lra_reg_info
[regno
].actual_call_used_reg_set
))
4612 ? lra_reg_info
[regno
].actual_call_used_reg_set
4613 : call_used_reg_set
,
4614 PSEUDO_REGNO_MODE (regno
), reg_renumber
[regno
])
4615 || HARD_REGNO_CALL_PART_CLOBBERED (reg_renumber
[regno
],
4616 PSEUDO_REGNO_MODE (regno
))));
4619 /* Global registers occurring in the current EBB. */
4620 static bitmap_head ebb_global_regs
;
4622 /* Return true if we need a split for hard register REGNO or pseudo
4623 REGNO which was assigned to a hard register.
4624 POTENTIAL_RELOAD_HARD_REGS contains hard registers which might be
4625 used for reloads since the EBB end. It is an approximation of the
4626 used hard registers in the split range. The exact value would
4627 require expensive calculations. If we were aggressive with
4628 splitting because of the approximation, the split pseudo will save
4629 the same hard register assignment and will be removed in the undo
4630 pass. We still need the approximation because too aggressive
4631 splitting would result in too inaccurate cost calculation in the
4632 assignment pass because of too many generated moves which will be
4633 probably removed in the undo pass. */
4635 need_for_split_p (HARD_REG_SET potential_reload_hard_regs
, int regno
)
4637 int hard_regno
= regno
< FIRST_PSEUDO_REGISTER
? regno
: reg_renumber
[regno
];
4639 lra_assert (hard_regno
>= 0);
4640 return ((TEST_HARD_REG_BIT (potential_reload_hard_regs
, hard_regno
)
4641 /* Don't split eliminable hard registers, otherwise we can
4642 split hard registers like hard frame pointer, which
4643 lives on BB start/end according to DF-infrastructure,
4644 when there is a pseudo assigned to the register and
4645 living in the same BB. */
4646 && (regno
>= FIRST_PSEUDO_REGISTER
4647 || ! TEST_HARD_REG_BIT (eliminable_regset
, hard_regno
))
4648 && ! TEST_HARD_REG_BIT (lra_no_alloc_regs
, hard_regno
)
4649 /* Don't split call clobbered hard regs living through
4650 calls, otherwise we might have a check problem in the
4651 assign sub-pass as in the most cases (exception is a
4652 situation when lra_risky_transformations_p value is
4653 true) the assign pass assumes that all pseudos living
4654 through calls are assigned to call saved hard regs. */
4655 && (regno
>= FIRST_PSEUDO_REGISTER
4656 || ! TEST_HARD_REG_BIT (call_used_reg_set
, regno
)
4657 || usage_insns
[regno
].calls_num
== calls_num
)
4658 /* We need at least 2 reloads to make pseudo splitting
4659 profitable. We should provide hard regno splitting in
4660 any case to solve 1st insn scheduling problem when
4661 moving hard register definition up might result in
4662 impossibility to find hard register for reload pseudo of
4663 small register class. */
4664 && (usage_insns
[regno
].reloads_num
4665 + (regno
< FIRST_PSEUDO_REGISTER
? 0 : 3) < reloads_num
)
4666 && (regno
< FIRST_PSEUDO_REGISTER
4667 /* For short living pseudos, spilling + inheritance can
4668 be considered a substitution for splitting.
4669 Therefore we do not splitting for local pseudos. It
4670 decreases also aggressiveness of splitting. The
4671 minimal number of references is chosen taking into
4672 account that for 2 references splitting has no sense
4673 as we can just spill the pseudo. */
4674 || (regno
>= FIRST_PSEUDO_REGISTER
4675 && lra_reg_info
[regno
].nrefs
> 3
4676 && bitmap_bit_p (&ebb_global_regs
, regno
))))
4677 || (regno
>= FIRST_PSEUDO_REGISTER
&& need_for_call_save_p (regno
)));
4680 /* Return class for the split pseudo created from original pseudo with
4681 ALLOCNO_CLASS and MODE which got a hard register HARD_REGNO. We
4682 choose subclass of ALLOCNO_CLASS which contains HARD_REGNO and
4683 results in no secondary memory movements. */
4684 static enum reg_class
4685 choose_split_class (enum reg_class allocno_class
,
4686 int hard_regno ATTRIBUTE_UNUSED
,
4687 enum machine_mode mode ATTRIBUTE_UNUSED
)
4689 #ifndef SECONDARY_MEMORY_NEEDED
4690 return allocno_class
;
4693 enum reg_class cl
, best_cl
= NO_REGS
;
4694 enum reg_class hard_reg_class ATTRIBUTE_UNUSED
4695 = REGNO_REG_CLASS (hard_regno
);
4697 if (! SECONDARY_MEMORY_NEEDED (allocno_class
, allocno_class
, mode
)
4698 && TEST_HARD_REG_BIT (reg_class_contents
[allocno_class
], hard_regno
))
4699 return allocno_class
;
4701 (cl
= reg_class_subclasses
[allocno_class
][i
]) != LIM_REG_CLASSES
;
4703 if (! SECONDARY_MEMORY_NEEDED (cl
, hard_reg_class
, mode
)
4704 && ! SECONDARY_MEMORY_NEEDED (hard_reg_class
, cl
, mode
)
4705 && TEST_HARD_REG_BIT (reg_class_contents
[cl
], hard_regno
)
4706 && (best_cl
== NO_REGS
4707 || ira_class_hard_regs_num
[best_cl
] < ira_class_hard_regs_num
[cl
]))
4713 /* Do split transformations for insn INSN, which defines or uses
4714 ORIGINAL_REGNO. NEXT_USAGE_INSNS specifies which instruction in
4715 the EBB next uses ORIGINAL_REGNO; it has the same form as the
4716 "insns" field of usage_insns.
4718 The transformations look like:
4721 ... s <- p (new insn -- save)
4723 ... p <- s (new insn -- restore)
4724 <- ... p ... <- ... p ...
4726 <- ... p ... <- ... p ...
4727 ... s <- p (new insn -- save)
4729 ... p <- s (new insn -- restore)
4730 <- ... p ... <- ... p ...
4732 where p is an original pseudo got a hard register or a hard
4733 register and s is a new split pseudo. The save is put before INSN
4734 if BEFORE_P is true. Return true if we succeed in such
4737 split_reg (bool before_p
, int original_regno
, rtx_insn
*insn
,
4738 rtx next_usage_insns
)
4740 enum reg_class rclass
;
4742 int hard_regno
, nregs
;
4743 rtx new_reg
, usage_insn
;
4744 rtx_insn
*restore
, *save
;
4748 if (original_regno
< FIRST_PSEUDO_REGISTER
)
4750 rclass
= ira_allocno_class_translate
[REGNO_REG_CLASS (original_regno
)];
4751 hard_regno
= original_regno
;
4752 call_save_p
= false;
4757 hard_regno
= reg_renumber
[original_regno
];
4758 nregs
= hard_regno_nregs
[hard_regno
][PSEUDO_REGNO_MODE (original_regno
)];
4759 rclass
= lra_get_allocno_class (original_regno
);
4760 original_reg
= regno_reg_rtx
[original_regno
];
4761 call_save_p
= need_for_call_save_p (original_regno
);
4763 original_reg
= regno_reg_rtx
[original_regno
];
4764 lra_assert (hard_regno
>= 0);
4765 if (lra_dump_file
!= NULL
)
4766 fprintf (lra_dump_file
,
4767 " ((((((((((((((((((((((((((((((((((((((((((((((((\n");
4770 enum machine_mode mode
= GET_MODE (original_reg
);
4772 mode
= HARD_REGNO_CALLER_SAVE_MODE (hard_regno
,
4773 hard_regno_nregs
[hard_regno
][mode
],
4775 new_reg
= lra_create_new_reg (mode
, NULL_RTX
, NO_REGS
, "save");
4779 rclass
= choose_split_class (rclass
, hard_regno
,
4780 GET_MODE (original_reg
));
4781 if (rclass
== NO_REGS
)
4783 if (lra_dump_file
!= NULL
)
4785 fprintf (lra_dump_file
,
4786 " Rejecting split of %d(%s): "
4787 "no good reg class for %d(%s)\n",
4789 reg_class_names
[lra_get_allocno_class (original_regno
)],
4791 reg_class_names
[REGNO_REG_CLASS (hard_regno
)]);
4794 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
4798 new_reg
= lra_create_new_reg (GET_MODE (original_reg
), original_reg
,
4800 reg_renumber
[REGNO (new_reg
)] = hard_regno
;
4802 save
= emit_spill_move (true, new_reg
, original_reg
);
4803 if (NEXT_INSN (save
) != NULL_RTX
)
4805 lra_assert (! call_save_p
);
4806 if (lra_dump_file
!= NULL
)
4810 " Rejecting split %d->%d resulting in > 2 %s save insns:\n",
4811 original_regno
, REGNO (new_reg
), call_save_p
? "call" : "");
4812 dump_rtl_slim (lra_dump_file
, save
, NULL_RTX
, -1, 0);
4813 fprintf (lra_dump_file
,
4814 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
4818 restore
= emit_spill_move (false, new_reg
, original_reg
);
4819 if (NEXT_INSN (restore
) != NULL_RTX
)
4821 lra_assert (! call_save_p
);
4822 if (lra_dump_file
!= NULL
)
4824 fprintf (lra_dump_file
,
4825 " Rejecting split %d->%d "
4826 "resulting in > 2 %s restore insns:\n",
4827 original_regno
, REGNO (new_reg
), call_save_p
? "call" : "");
4828 dump_rtl_slim (lra_dump_file
, restore
, NULL_RTX
, -1, 0);
4829 fprintf (lra_dump_file
,
4830 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
4834 after_p
= usage_insns
[original_regno
].after_p
;
4835 lra_reg_info
[REGNO (new_reg
)].restore_regno
= original_regno
;
4836 bitmap_set_bit (&check_only_regs
, REGNO (new_reg
));
4837 bitmap_set_bit (&check_only_regs
, original_regno
);
4838 bitmap_set_bit (&lra_split_regs
, REGNO (new_reg
));
4841 if (GET_CODE (next_usage_insns
) != INSN_LIST
)
4843 usage_insn
= next_usage_insns
;
4846 usage_insn
= XEXP (next_usage_insns
, 0);
4847 lra_assert (DEBUG_INSN_P (usage_insn
));
4848 next_usage_insns
= XEXP (next_usage_insns
, 1);
4849 substitute_pseudo (&usage_insn
, original_regno
, new_reg
);
4850 lra_update_insn_regno_info (as_a
<rtx_insn
*> (usage_insn
));
4851 if (lra_dump_file
!= NULL
)
4853 fprintf (lra_dump_file
, " Split reuse change %d->%d:\n",
4854 original_regno
, REGNO (new_reg
));
4855 dump_insn_slim (lra_dump_file
, usage_insn
);
4858 lra_assert (NOTE_P (usage_insn
) || NONDEBUG_INSN_P (usage_insn
));
4859 lra_assert (usage_insn
!= insn
|| (after_p
&& before_p
));
4860 lra_process_new_insns (as_a
<rtx_insn
*> (usage_insn
),
4861 after_p
? NULL
: restore
,
4862 after_p
? restore
: NULL
,
4864 ? "Add reg<-save" : "Add reg<-split");
4865 lra_process_new_insns (insn
, before_p
? save
: NULL
,
4866 before_p
? NULL
: save
,
4868 ? "Add save<-reg" : "Add split<-reg");
4870 /* If we are trying to split multi-register. We should check
4871 conflicts on the next assignment sub-pass. IRA can allocate on
4872 sub-register levels, LRA do this on pseudos level right now and
4873 this discrepancy may create allocation conflicts after
4875 lra_risky_transformations_p
= true;
4876 if (lra_dump_file
!= NULL
)
4877 fprintf (lra_dump_file
,
4878 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
4882 /* Recognize that we need a split transformation for insn INSN, which
4883 defines or uses REGNO in its insn biggest MODE (we use it only if
4884 REGNO is a hard register). POTENTIAL_RELOAD_HARD_REGS contains
4885 hard registers which might be used for reloads since the EBB end.
4886 Put the save before INSN if BEFORE_P is true. MAX_UID is maximla
4887 uid before starting INSN processing. Return true if we succeed in
4888 such transformation. */
4890 split_if_necessary (int regno
, enum machine_mode mode
,
4891 HARD_REG_SET potential_reload_hard_regs
,
4892 bool before_p
, rtx_insn
*insn
, int max_uid
)
4896 rtx next_usage_insns
;
4898 if (regno
< FIRST_PSEUDO_REGISTER
)
4899 nregs
= hard_regno_nregs
[regno
][mode
];
4900 for (i
= 0; i
< nregs
; i
++)
4901 if (usage_insns
[regno
+ i
].check
== curr_usage_insns_check
4902 && (next_usage_insns
= usage_insns
[regno
+ i
].insns
) != NULL_RTX
4903 /* To avoid processing the register twice or more. */
4904 && ((GET_CODE (next_usage_insns
) != INSN_LIST
4905 && INSN_UID (next_usage_insns
) < max_uid
)
4906 || (GET_CODE (next_usage_insns
) == INSN_LIST
4907 && (INSN_UID (XEXP (next_usage_insns
, 0)) < max_uid
)))
4908 && need_for_split_p (potential_reload_hard_regs
, regno
+ i
)
4909 && split_reg (before_p
, regno
+ i
, insn
, next_usage_insns
))
4914 /* Check only registers living at the current program point in the
4916 static bitmap_head live_regs
;
4918 /* Update live info in EBB given by its HEAD and TAIL insns after
4919 inheritance/split transformation. The function removes dead moves
4922 update_ebb_live_info (rtx_insn
*head
, rtx_insn
*tail
)
4927 rtx_insn
*prev_insn
;
4930 basic_block last_bb
, prev_bb
, curr_bb
;
4932 struct lra_insn_reg
*reg
;
4936 last_bb
= BLOCK_FOR_INSN (tail
);
4938 for (curr_insn
= tail
;
4939 curr_insn
!= PREV_INSN (head
);
4940 curr_insn
= prev_insn
)
4942 prev_insn
= PREV_INSN (curr_insn
);
4943 /* We need to process empty blocks too. They contain
4944 NOTE_INSN_BASIC_BLOCK referring for the basic block. */
4945 if (NOTE_P (curr_insn
) && NOTE_KIND (curr_insn
) != NOTE_INSN_BASIC_BLOCK
)
4947 curr_bb
= BLOCK_FOR_INSN (curr_insn
);
4948 if (curr_bb
!= prev_bb
)
4950 if (prev_bb
!= NULL
)
4952 /* Update df_get_live_in (prev_bb): */
4953 EXECUTE_IF_SET_IN_BITMAP (&check_only_regs
, 0, j
, bi
)
4954 if (bitmap_bit_p (&live_regs
, j
))
4955 bitmap_set_bit (df_get_live_in (prev_bb
), j
);
4957 bitmap_clear_bit (df_get_live_in (prev_bb
), j
);
4959 if (curr_bb
!= last_bb
)
4961 /* Update df_get_live_out (curr_bb): */
4962 EXECUTE_IF_SET_IN_BITMAP (&check_only_regs
, 0, j
, bi
)
4964 live_p
= bitmap_bit_p (&live_regs
, j
);
4966 FOR_EACH_EDGE (e
, ei
, curr_bb
->succs
)
4967 if (bitmap_bit_p (df_get_live_in (e
->dest
), j
))
4973 bitmap_set_bit (df_get_live_out (curr_bb
), j
);
4975 bitmap_clear_bit (df_get_live_out (curr_bb
), j
);
4979 bitmap_and (&live_regs
, &check_only_regs
, df_get_live_out (curr_bb
));
4981 if (! NONDEBUG_INSN_P (curr_insn
))
4983 curr_id
= lra_get_insn_recog_data (curr_insn
);
4984 curr_static_id
= curr_id
->insn_static_data
;
4986 if ((set
= single_set (curr_insn
)) != NULL_RTX
&& REG_P (SET_DEST (set
))
4987 && (regno
= REGNO (SET_DEST (set
))) >= FIRST_PSEUDO_REGISTER
4988 && bitmap_bit_p (&check_only_regs
, regno
)
4989 && ! bitmap_bit_p (&live_regs
, regno
))
4991 /* See which defined values die here. */
4992 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
4993 if (reg
->type
== OP_OUT
&& ! reg
->subreg_p
)
4994 bitmap_clear_bit (&live_regs
, reg
->regno
);
4995 for (reg
= curr_static_id
->hard_regs
; reg
!= NULL
; reg
= reg
->next
)
4996 if (reg
->type
== OP_OUT
&& ! reg
->subreg_p
)
4997 bitmap_clear_bit (&live_regs
, reg
->regno
);
4998 /* Mark each used value as live. */
4999 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
5000 if (reg
->type
!= OP_OUT
5001 && bitmap_bit_p (&check_only_regs
, reg
->regno
))
5002 bitmap_set_bit (&live_regs
, reg
->regno
);
5003 for (reg
= curr_static_id
->hard_regs
; reg
!= NULL
; reg
= reg
->next
)
5004 if (reg
->type
!= OP_OUT
5005 && bitmap_bit_p (&check_only_regs
, reg
->regno
))
5006 bitmap_set_bit (&live_regs
, reg
->regno
);
5007 if (curr_id
->arg_hard_regs
!= NULL
)
5008 /* Make argument hard registers live. */
5009 for (i
= 0; (regno
= curr_id
->arg_hard_regs
[i
]) >= 0; i
++)
5010 if (bitmap_bit_p (&check_only_regs
, regno
))
5011 bitmap_set_bit (&live_regs
, regno
);
5012 /* It is quite important to remove dead move insns because it
5013 means removing dead store. We don't need to process them for
5017 if (lra_dump_file
!= NULL
)
5019 fprintf (lra_dump_file
, " Removing dead insn:\n ");
5020 dump_insn_slim (lra_dump_file
, curr_insn
);
5022 lra_set_insn_deleted (curr_insn
);
5027 /* The structure describes info to do an inheritance for the current
5028 insn. We need to collect such info first before doing the
5029 transformations because the transformations change the insn
5030 internal representation. */
5033 /* Original regno. */
5035 /* Subsequent insns which can inherit original reg value. */
5039 /* Array containing all info for doing inheritance from the current
5041 static struct to_inherit to_inherit
[LRA_MAX_INSN_RELOADS
];
5043 /* Number elements in the previous array. */
5044 static int to_inherit_num
;
5046 /* Add inheritance info REGNO and INSNS. Their meaning is described in
5047 structure to_inherit. */
5049 add_to_inherit (int regno
, rtx insns
)
5053 for (i
= 0; i
< to_inherit_num
; i
++)
5054 if (to_inherit
[i
].regno
== regno
)
5056 lra_assert (to_inherit_num
< LRA_MAX_INSN_RELOADS
);
5057 to_inherit
[to_inherit_num
].regno
= regno
;
5058 to_inherit
[to_inherit_num
++].insns
= insns
;
5061 /* Return the last non-debug insn in basic block BB, or the block begin
5064 get_last_insertion_point (basic_block bb
)
5068 FOR_BB_INSNS_REVERSE (bb
, insn
)
5069 if (NONDEBUG_INSN_P (insn
) || NOTE_INSN_BASIC_BLOCK_P (insn
))
5074 /* Set up RES by registers living on edges FROM except the edge (FROM,
5075 TO) or by registers set up in a jump insn in BB FROM. */
5077 get_live_on_other_edges (basic_block from
, basic_block to
, bitmap res
)
5080 struct lra_insn_reg
*reg
;
5084 lra_assert (to
!= NULL
);
5086 FOR_EACH_EDGE (e
, ei
, from
->succs
)
5088 bitmap_ior_into (res
, df_get_live_in (e
->dest
));
5089 last
= get_last_insertion_point (from
);
5090 if (! JUMP_P (last
))
5092 curr_id
= lra_get_insn_recog_data (last
);
5093 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
5094 if (reg
->type
!= OP_IN
)
5095 bitmap_set_bit (res
, reg
->regno
);
5098 /* Used as a temporary results of some bitmap calculations. */
5099 static bitmap_head temp_bitmap
;
5101 /* We split for reloads of small class of hard regs. The following
5102 defines how many hard regs the class should have to be qualified as
5103 small. The code is mostly oriented to x86/x86-64 architecture
5104 where some insns need to use only specific register or pair of
5105 registers and these register can live in RTL explicitly, e.g. for
5106 parameter passing. */
5107 static const int max_small_class_regs_num
= 2;
5109 /* Do inheritance/split transformations in EBB starting with HEAD and
5110 finishing on TAIL. We process EBB insns in the reverse order.
5111 Return true if we did any inheritance/split transformation in the
5114 We should avoid excessive splitting which results in worse code
5115 because of inaccurate cost calculations for spilling new split
5116 pseudos in such case. To achieve this we do splitting only if
5117 register pressure is high in given basic block and there are reload
5118 pseudos requiring hard registers. We could do more register
5119 pressure calculations at any given program point to avoid necessary
5120 splitting even more but it is to expensive and the current approach
5121 works well enough. */
5123 inherit_in_ebb (rtx_insn
*head
, rtx_insn
*tail
)
5125 int i
, src_regno
, dst_regno
, nregs
;
5126 bool change_p
, succ_p
, update_reloads_num_p
;
5127 rtx_insn
*prev_insn
, *last_insn
;
5128 rtx next_usage_insns
, set
;
5130 struct lra_insn_reg
*reg
;
5131 basic_block last_processed_bb
, curr_bb
= NULL
;
5132 HARD_REG_SET potential_reload_hard_regs
, live_hard_regs
;
5136 bool head_p
, after_p
;
5139 curr_usage_insns_check
++;
5140 reloads_num
= calls_num
= 0;
5141 bitmap_clear (&check_only_regs
);
5142 last_processed_bb
= NULL
;
5143 CLEAR_HARD_REG_SET (potential_reload_hard_regs
);
5144 COPY_HARD_REG_SET (live_hard_regs
, eliminable_regset
);
5145 IOR_HARD_REG_SET (live_hard_regs
, lra_no_alloc_regs
);
5146 /* We don't process new insns generated in the loop. */
5147 for (curr_insn
= tail
; curr_insn
!= PREV_INSN (head
); curr_insn
= prev_insn
)
5149 prev_insn
= PREV_INSN (curr_insn
);
5150 if (BLOCK_FOR_INSN (curr_insn
) != NULL
)
5151 curr_bb
= BLOCK_FOR_INSN (curr_insn
);
5152 if (last_processed_bb
!= curr_bb
)
5154 /* We are at the end of BB. Add qualified living
5155 pseudos for potential splitting. */
5156 to_process
= df_get_live_out (curr_bb
);
5157 if (last_processed_bb
!= NULL
)
5159 /* We are somewhere in the middle of EBB. */
5160 get_live_on_other_edges (curr_bb
, last_processed_bb
,
5162 to_process
= &temp_bitmap
;
5164 last_processed_bb
= curr_bb
;
5165 last_insn
= get_last_insertion_point (curr_bb
);
5166 after_p
= (! JUMP_P (last_insn
)
5167 && (! CALL_P (last_insn
)
5168 || (find_reg_note (last_insn
,
5169 REG_NORETURN
, NULL_RTX
) == NULL_RTX
5170 && ! SIBLING_CALL_P (last_insn
))));
5171 CLEAR_HARD_REG_SET (potential_reload_hard_regs
);
5172 EXECUTE_IF_SET_IN_BITMAP (to_process
, 0, j
, bi
)
5174 if ((int) j
>= lra_constraint_new_regno_start
)
5176 if (j
< FIRST_PSEUDO_REGISTER
|| reg_renumber
[j
] >= 0)
5178 if (j
< FIRST_PSEUDO_REGISTER
)
5179 SET_HARD_REG_BIT (live_hard_regs
, j
);
5181 add_to_hard_reg_set (&live_hard_regs
,
5182 PSEUDO_REGNO_MODE (j
),
5184 setup_next_usage_insn (j
, last_insn
, reloads_num
, after_p
);
5188 src_regno
= dst_regno
= -1;
5189 if (NONDEBUG_INSN_P (curr_insn
)
5190 && (set
= single_set (curr_insn
)) != NULL_RTX
5191 && REG_P (SET_DEST (set
)) && REG_P (SET_SRC (set
)))
5193 src_regno
= REGNO (SET_SRC (set
));
5194 dst_regno
= REGNO (SET_DEST (set
));
5196 update_reloads_num_p
= true;
5197 if (src_regno
< lra_constraint_new_regno_start
5198 && src_regno
>= FIRST_PSEUDO_REGISTER
5199 && reg_renumber
[src_regno
] < 0
5200 && dst_regno
>= lra_constraint_new_regno_start
5201 && (cl
= lra_get_allocno_class (dst_regno
)) != NO_REGS
)
5203 /* 'reload_pseudo <- original_pseudo'. */
5204 if (ira_class_hard_regs_num
[cl
] <= max_small_class_regs_num
)
5206 update_reloads_num_p
= false;
5208 if (usage_insns
[src_regno
].check
== curr_usage_insns_check
5209 && (next_usage_insns
= usage_insns
[src_regno
].insns
) != NULL_RTX
)
5210 succ_p
= inherit_reload_reg (false, src_regno
, cl
,
5211 curr_insn
, next_usage_insns
);
5215 setup_next_usage_insn (src_regno
, curr_insn
, reloads_num
, false);
5216 if (hard_reg_set_subset_p (reg_class_contents
[cl
], live_hard_regs
))
5217 IOR_HARD_REG_SET (potential_reload_hard_regs
,
5218 reg_class_contents
[cl
]);
5220 else if (src_regno
>= lra_constraint_new_regno_start
5221 && dst_regno
< lra_constraint_new_regno_start
5222 && dst_regno
>= FIRST_PSEUDO_REGISTER
5223 && reg_renumber
[dst_regno
] < 0
5224 && (cl
= lra_get_allocno_class (src_regno
)) != NO_REGS
5225 && usage_insns
[dst_regno
].check
== curr_usage_insns_check
5226 && (next_usage_insns
5227 = usage_insns
[dst_regno
].insns
) != NULL_RTX
)
5229 if (ira_class_hard_regs_num
[cl
] <= max_small_class_regs_num
)
5231 update_reloads_num_p
= false;
5232 /* 'original_pseudo <- reload_pseudo'. */
5233 if (! JUMP_P (curr_insn
)
5234 && inherit_reload_reg (true, dst_regno
, cl
,
5235 curr_insn
, next_usage_insns
))
5238 usage_insns
[dst_regno
].check
= 0;
5239 if (hard_reg_set_subset_p (reg_class_contents
[cl
], live_hard_regs
))
5240 IOR_HARD_REG_SET (potential_reload_hard_regs
,
5241 reg_class_contents
[cl
]);
5243 else if (INSN_P (curr_insn
))
5246 int max_uid
= get_max_uid ();
5248 curr_id
= lra_get_insn_recog_data (curr_insn
);
5249 curr_static_id
= curr_id
->insn_static_data
;
5251 /* Process insn definitions. */
5252 for (iter
= 0; iter
< 2; iter
++)
5253 for (reg
= iter
== 0 ? curr_id
->regs
: curr_static_id
->hard_regs
;
5256 if (reg
->type
!= OP_IN
5257 && (dst_regno
= reg
->regno
) < lra_constraint_new_regno_start
)
5259 if (dst_regno
>= FIRST_PSEUDO_REGISTER
&& reg
->type
== OP_OUT
5260 && reg_renumber
[dst_regno
] < 0 && ! reg
->subreg_p
5261 && usage_insns
[dst_regno
].check
== curr_usage_insns_check
5262 && (next_usage_insns
5263 = usage_insns
[dst_regno
].insns
) != NULL_RTX
)
5265 struct lra_insn_reg
*r
;
5267 for (r
= curr_id
->regs
; r
!= NULL
; r
= r
->next
)
5268 if (r
->type
!= OP_OUT
&& r
->regno
== dst_regno
)
5270 /* Don't do inheritance if the pseudo is also
5271 used in the insn. */
5273 /* We can not do inheritance right now
5274 because the current insn reg info (chain
5275 regs) can change after that. */
5276 add_to_inherit (dst_regno
, next_usage_insns
);
5278 /* We can not process one reg twice here because of
5279 usage_insns invalidation. */
5280 if ((dst_regno
< FIRST_PSEUDO_REGISTER
5281 || reg_renumber
[dst_regno
] >= 0)
5282 && ! reg
->subreg_p
&& reg
->type
!= OP_IN
)
5286 if (split_if_necessary (dst_regno
, reg
->biggest_mode
,
5287 potential_reload_hard_regs
,
5288 false, curr_insn
, max_uid
))
5290 CLEAR_HARD_REG_SET (s
);
5291 if (dst_regno
< FIRST_PSEUDO_REGISTER
)
5292 add_to_hard_reg_set (&s
, reg
->biggest_mode
, dst_regno
);
5294 add_to_hard_reg_set (&s
, PSEUDO_REGNO_MODE (dst_regno
),
5295 reg_renumber
[dst_regno
]);
5296 AND_COMPL_HARD_REG_SET (live_hard_regs
, s
);
5298 /* We should invalidate potential inheritance or
5299 splitting for the current insn usages to the next
5300 usage insns (see code below) as the output pseudo
5302 if ((dst_regno
>= FIRST_PSEUDO_REGISTER
5303 && reg_renumber
[dst_regno
] < 0)
5304 || (reg
->type
== OP_OUT
&& ! reg
->subreg_p
5305 && (dst_regno
< FIRST_PSEUDO_REGISTER
5306 || reg_renumber
[dst_regno
] >= 0)))
5308 /* Invalidate and mark definitions. */
5309 if (dst_regno
>= FIRST_PSEUDO_REGISTER
)
5310 usage_insns
[dst_regno
].check
= -(int) INSN_UID (curr_insn
);
5313 nregs
= hard_regno_nregs
[dst_regno
][reg
->biggest_mode
];
5314 for (i
= 0; i
< nregs
; i
++)
5315 usage_insns
[dst_regno
+ i
].check
5316 = -(int) INSN_UID (curr_insn
);
5320 if (! JUMP_P (curr_insn
))
5321 for (i
= 0; i
< to_inherit_num
; i
++)
5322 if (inherit_reload_reg (true, to_inherit
[i
].regno
,
5323 ALL_REGS
, curr_insn
,
5324 to_inherit
[i
].insns
))
5326 if (CALL_P (curr_insn
))
5328 rtx cheap
, pat
, dest
;
5330 int regno
, hard_regno
;
5333 if ((cheap
= find_reg_note (curr_insn
,
5334 REG_RETURNED
, NULL_RTX
)) != NULL_RTX
5335 && ((cheap
= XEXP (cheap
, 0)), true)
5336 && (regno
= REGNO (cheap
)) >= FIRST_PSEUDO_REGISTER
5337 && (hard_regno
= reg_renumber
[regno
]) >= 0
5338 /* If there are pending saves/restores, the
5339 optimization is not worth. */
5340 && usage_insns
[regno
].calls_num
== calls_num
- 1
5341 && TEST_HARD_REG_BIT (call_used_reg_set
, hard_regno
))
5343 /* Restore the pseudo from the call result as
5344 REG_RETURNED note says that the pseudo value is
5345 in the call result and the pseudo is an argument
5347 pat
= PATTERN (curr_insn
);
5348 if (GET_CODE (pat
) == PARALLEL
)
5349 pat
= XVECEXP (pat
, 0, 0);
5350 dest
= SET_DEST (pat
);
5352 emit_move_insn (cheap
, copy_rtx (dest
));
5353 restore
= get_insns ();
5355 lra_process_new_insns (curr_insn
, NULL
, restore
,
5356 "Inserting call parameter restore");
5357 /* We don't need to save/restore of the pseudo from
5359 usage_insns
[regno
].calls_num
= calls_num
;
5360 bitmap_set_bit (&check_only_regs
, regno
);
5364 /* Process insn usages. */
5365 for (iter
= 0; iter
< 2; iter
++)
5366 for (reg
= iter
== 0 ? curr_id
->regs
: curr_static_id
->hard_regs
;
5369 if ((reg
->type
!= OP_OUT
5370 || (reg
->type
== OP_OUT
&& reg
->subreg_p
))
5371 && (src_regno
= reg
->regno
) < lra_constraint_new_regno_start
)
5373 if (src_regno
>= FIRST_PSEUDO_REGISTER
5374 && reg_renumber
[src_regno
] < 0 && reg
->type
== OP_IN
)
5376 if (usage_insns
[src_regno
].check
== curr_usage_insns_check
5377 && (next_usage_insns
5378 = usage_insns
[src_regno
].insns
) != NULL_RTX
5379 && NONDEBUG_INSN_P (curr_insn
))
5380 add_to_inherit (src_regno
, next_usage_insns
);
5381 else if (usage_insns
[src_regno
].check
5382 != -(int) INSN_UID (curr_insn
))
5383 /* Add usages but only if the reg is not set up
5384 in the same insn. */
5385 add_next_usage_insn (src_regno
, curr_insn
, reloads_num
);
5387 else if (src_regno
< FIRST_PSEUDO_REGISTER
5388 || reg_renumber
[src_regno
] >= 0)
5391 rtx use_insn
= curr_insn
;
5393 before_p
= (JUMP_P (curr_insn
)
5394 || (CALL_P (curr_insn
) && reg
->type
== OP_IN
));
5395 if (NONDEBUG_INSN_P (curr_insn
)
5396 && (! JUMP_P (curr_insn
) || reg
->type
== OP_IN
)
5397 && split_if_necessary (src_regno
, reg
->biggest_mode
,
5398 potential_reload_hard_regs
,
5399 before_p
, curr_insn
, max_uid
))
5402 lra_risky_transformations_p
= true;
5405 usage_insns
[src_regno
].check
= 0;
5407 use_insn
= PREV_INSN (curr_insn
);
5409 if (NONDEBUG_INSN_P (curr_insn
))
5411 if (src_regno
< FIRST_PSEUDO_REGISTER
)
5412 add_to_hard_reg_set (&live_hard_regs
,
5413 reg
->biggest_mode
, src_regno
);
5415 add_to_hard_reg_set (&live_hard_regs
,
5416 PSEUDO_REGNO_MODE (src_regno
),
5417 reg_renumber
[src_regno
]);
5419 add_next_usage_insn (src_regno
, use_insn
, reloads_num
);
5422 /* Process call args. */
5423 if (curr_id
->arg_hard_regs
!= NULL
)
5424 for (i
= 0; (src_regno
= curr_id
->arg_hard_regs
[i
]) >= 0; i
++)
5425 if (src_regno
< FIRST_PSEUDO_REGISTER
)
5427 SET_HARD_REG_BIT (live_hard_regs
, src_regno
);
5428 add_next_usage_insn (src_regno
, curr_insn
, reloads_num
);
5430 for (i
= 0; i
< to_inherit_num
; i
++)
5432 src_regno
= to_inherit
[i
].regno
;
5433 if (inherit_reload_reg (false, src_regno
, ALL_REGS
,
5434 curr_insn
, to_inherit
[i
].insns
))
5437 setup_next_usage_insn (src_regno
, curr_insn
, reloads_num
, false);
5440 if (update_reloads_num_p
5441 && NONDEBUG_INSN_P (curr_insn
)
5442 && (set
= single_set (curr_insn
)) != NULL_RTX
)
5445 if ((REG_P (SET_DEST (set
))
5446 && (regno
= REGNO (SET_DEST (set
))) >= lra_constraint_new_regno_start
5447 && reg_renumber
[regno
] < 0
5448 && (cl
= lra_get_allocno_class (regno
)) != NO_REGS
)
5449 || (REG_P (SET_SRC (set
))
5450 && (regno
= REGNO (SET_SRC (set
))) >= lra_constraint_new_regno_start
5451 && reg_renumber
[regno
] < 0
5452 && (cl
= lra_get_allocno_class (regno
)) != NO_REGS
))
5454 if (ira_class_hard_regs_num
[cl
] <= max_small_class_regs_num
)
5456 if (hard_reg_set_subset_p (reg_class_contents
[cl
], live_hard_regs
))
5457 IOR_HARD_REG_SET (potential_reload_hard_regs
,
5458 reg_class_contents
[cl
]);
5461 /* We reached the start of the current basic block. */
5462 if (prev_insn
== NULL_RTX
|| prev_insn
== PREV_INSN (head
)
5463 || BLOCK_FOR_INSN (prev_insn
) != curr_bb
)
5465 /* We reached the beginning of the current block -- do
5466 rest of spliting in the current BB. */
5467 to_process
= df_get_live_in (curr_bb
);
5468 if (BLOCK_FOR_INSN (head
) != curr_bb
)
5470 /* We are somewhere in the middle of EBB. */
5471 get_live_on_other_edges (EDGE_PRED (curr_bb
, 0)->src
,
5472 curr_bb
, &temp_bitmap
);
5473 to_process
= &temp_bitmap
;
5476 EXECUTE_IF_SET_IN_BITMAP (to_process
, 0, j
, bi
)
5478 if ((int) j
>= lra_constraint_new_regno_start
)
5480 if (((int) j
< FIRST_PSEUDO_REGISTER
|| reg_renumber
[j
] >= 0)
5481 && usage_insns
[j
].check
== curr_usage_insns_check
5482 && (next_usage_insns
= usage_insns
[j
].insns
) != NULL_RTX
)
5484 if (need_for_split_p (potential_reload_hard_regs
, j
))
5486 if (lra_dump_file
!= NULL
&& head_p
)
5488 fprintf (lra_dump_file
,
5489 " ----------------------------------\n");
5492 if (split_reg (false, j
, bb_note (curr_bb
),
5496 usage_insns
[j
].check
= 0;
5504 /* This value affects EBB forming. If probability of edge from EBB to
5505 a BB is not greater than the following value, we don't add the BB
5507 #define EBB_PROBABILITY_CUTOFF ((REG_BR_PROB_BASE * 50) / 100)
5509 /* Current number of inheritance/split iteration. */
5510 int lra_inheritance_iter
;
5512 /* Entry function for inheritance/split pass. */
5514 lra_inheritance (void)
5517 basic_block bb
, start_bb
;
5520 lra_inheritance_iter
++;
5521 if (lra_inheritance_iter
> LRA_MAX_INHERITANCE_PASSES
)
5523 timevar_push (TV_LRA_INHERITANCE
);
5524 if (lra_dump_file
!= NULL
)
5525 fprintf (lra_dump_file
, "\n********** Inheritance #%d: **********\n\n",
5526 lra_inheritance_iter
);
5527 curr_usage_insns_check
= 0;
5528 usage_insns
= XNEWVEC (struct usage_insns
, lra_constraint_new_regno_start
);
5529 for (i
= 0; i
< lra_constraint_new_regno_start
; i
++)
5530 usage_insns
[i
].check
= 0;
5531 bitmap_initialize (&check_only_regs
, ®_obstack
);
5532 bitmap_initialize (&live_regs
, ®_obstack
);
5533 bitmap_initialize (&temp_bitmap
, ®_obstack
);
5534 bitmap_initialize (&ebb_global_regs
, ®_obstack
);
5535 FOR_EACH_BB_FN (bb
, cfun
)
5538 if (lra_dump_file
!= NULL
)
5539 fprintf (lra_dump_file
, "EBB");
5540 /* Form a EBB starting with BB. */
5541 bitmap_clear (&ebb_global_regs
);
5542 bitmap_ior_into (&ebb_global_regs
, df_get_live_in (bb
));
5545 if (lra_dump_file
!= NULL
)
5546 fprintf (lra_dump_file
, " %d", bb
->index
);
5547 if (bb
->next_bb
== EXIT_BLOCK_PTR_FOR_FN (cfun
)
5548 || LABEL_P (BB_HEAD (bb
->next_bb
)))
5550 e
= find_fallthru_edge (bb
->succs
);
5553 if (e
->probability
<= EBB_PROBABILITY_CUTOFF
)
5557 bitmap_ior_into (&ebb_global_regs
, df_get_live_out (bb
));
5558 if (lra_dump_file
!= NULL
)
5559 fprintf (lra_dump_file
, "\n");
5560 if (inherit_in_ebb (BB_HEAD (start_bb
), BB_END (bb
)))
5561 /* Remember that the EBB head and tail can change in
5563 update_ebb_live_info (BB_HEAD (start_bb
), BB_END (bb
));
5565 bitmap_clear (&ebb_global_regs
);
5566 bitmap_clear (&temp_bitmap
);
5567 bitmap_clear (&live_regs
);
5568 bitmap_clear (&check_only_regs
);
5571 timevar_pop (TV_LRA_INHERITANCE
);
5576 /* This page contains code to undo failed inheritance/split
5579 /* Current number of iteration undoing inheritance/split. */
5580 int lra_undo_inheritance_iter
;
5582 /* Fix BB live info LIVE after removing pseudos created on pass doing
5583 inheritance/split which are REMOVED_PSEUDOS. */
5585 fix_bb_live_info (bitmap live
, bitmap removed_pseudos
)
5590 EXECUTE_IF_SET_IN_BITMAP (removed_pseudos
, 0, regno
, bi
)
5591 if (bitmap_clear_bit (live
, regno
))
5592 bitmap_set_bit (live
, lra_reg_info
[regno
].restore_regno
);
5595 /* Return regno of the (subreg of) REG. Otherwise, return a negative
5600 if (GET_CODE (reg
) == SUBREG
)
5601 reg
= SUBREG_REG (reg
);
5607 /* Remove inheritance/split pseudos which are in REMOVE_PSEUDOS and
5608 return true if we did any change. The undo transformations for
5609 inheritance looks like
5613 p <- i, i <- p, and i <- i3
5614 where p is original pseudo from which inheritance pseudo i was
5615 created, i and i3 are removed inheritance pseudos, i2 is another
5616 not removed inheritance pseudo. All split pseudos or other
5617 occurrences of removed inheritance pseudos are changed on the
5618 corresponding original pseudos.
5620 The function also schedules insns changed and created during
5621 inheritance/split pass for processing by the subsequent constraint
5624 remove_inheritance_pseudos (bitmap remove_pseudos
)
5627 int regno
, sregno
, prev_sregno
, dregno
, restore_regno
;
5629 rtx_insn
*prev_insn
;
5630 bool change_p
, done_p
;
5632 change_p
= ! bitmap_empty_p (remove_pseudos
);
5633 /* We can not finish the function right away if CHANGE_P is true
5634 because we need to marks insns affected by previous
5635 inheritance/split pass for processing by the subsequent
5637 FOR_EACH_BB_FN (bb
, cfun
)
5639 fix_bb_live_info (df_get_live_in (bb
), remove_pseudos
);
5640 fix_bb_live_info (df_get_live_out (bb
), remove_pseudos
);
5641 FOR_BB_INSNS_REVERSE (bb
, curr_insn
)
5643 if (! INSN_P (curr_insn
))
5646 sregno
= dregno
= -1;
5647 if (change_p
&& NONDEBUG_INSN_P (curr_insn
)
5648 && (set
= single_set (curr_insn
)) != NULL_RTX
)
5650 dregno
= get_regno (SET_DEST (set
));
5651 sregno
= get_regno (SET_SRC (set
));
5654 if (sregno
>= 0 && dregno
>= 0)
5656 if ((bitmap_bit_p (remove_pseudos
, sregno
)
5657 && (lra_reg_info
[sregno
].restore_regno
== dregno
5658 || (bitmap_bit_p (remove_pseudos
, dregno
)
5659 && (lra_reg_info
[sregno
].restore_regno
5660 == lra_reg_info
[dregno
].restore_regno
))))
5661 || (bitmap_bit_p (remove_pseudos
, dregno
)
5662 && lra_reg_info
[dregno
].restore_regno
== sregno
))
5663 /* One of the following cases:
5664 original <- removed inheritance pseudo
5665 removed inherit pseudo <- another removed inherit pseudo
5666 removed inherit pseudo <- original pseudo
5668 removed_split_pseudo <- original_reg
5669 original_reg <- removed_split_pseudo */
5671 if (lra_dump_file
!= NULL
)
5673 fprintf (lra_dump_file
, " Removing %s:\n",
5674 bitmap_bit_p (&lra_split_regs
, sregno
)
5675 || bitmap_bit_p (&lra_split_regs
, dregno
)
5676 ? "split" : "inheritance");
5677 dump_insn_slim (lra_dump_file
, curr_insn
);
5679 lra_set_insn_deleted (curr_insn
);
5682 else if (bitmap_bit_p (remove_pseudos
, sregno
)
5683 && bitmap_bit_p (&lra_inheritance_pseudos
, sregno
))
5685 /* Search the following pattern:
5686 inherit_or_split_pseudo1 <- inherit_or_split_pseudo2
5687 original_pseudo <- inherit_or_split_pseudo1
5688 where the 2nd insn is the current insn and
5689 inherit_or_split_pseudo2 is not removed. If it is found,
5690 change the current insn onto:
5691 original_pseudo <- inherit_or_split_pseudo2. */
5692 for (prev_insn
= PREV_INSN (curr_insn
);
5693 prev_insn
!= NULL_RTX
&& ! NONDEBUG_INSN_P (prev_insn
);
5694 prev_insn
= PREV_INSN (prev_insn
))
5696 if (prev_insn
!= NULL_RTX
&& BLOCK_FOR_INSN (prev_insn
) == bb
5697 && (prev_set
= single_set (prev_insn
)) != NULL_RTX
5698 /* There should be no subregs in insn we are
5699 searching because only the original reg might
5700 be in subreg when we changed the mode of
5701 load/store for splitting. */
5702 && REG_P (SET_DEST (prev_set
))
5703 && REG_P (SET_SRC (prev_set
))
5704 && (int) REGNO (SET_DEST (prev_set
)) == sregno
5705 && ((prev_sregno
= REGNO (SET_SRC (prev_set
)))
5706 >= FIRST_PSEUDO_REGISTER
)
5707 /* As we consider chain of inheritance or
5708 splitting described in above comment we should
5709 check that sregno and prev_sregno were
5710 inheritance/split pseudos created from the
5711 same original regno. */
5712 && (lra_reg_info
[sregno
].restore_regno
5713 == lra_reg_info
[prev_sregno
].restore_regno
)
5714 && ! bitmap_bit_p (remove_pseudos
, prev_sregno
))
5716 lra_assert (GET_MODE (SET_SRC (prev_set
))
5717 == GET_MODE (regno_reg_rtx
[sregno
]));
5718 if (GET_CODE (SET_SRC (set
)) == SUBREG
)
5719 SUBREG_REG (SET_SRC (set
)) = SET_SRC (prev_set
);
5721 SET_SRC (set
) = SET_SRC (prev_set
);
5722 /* As we are finishing with processing the insn
5723 here, check the destination too as it might
5724 inheritance pseudo for another pseudo. */
5725 if (bitmap_bit_p (remove_pseudos
, dregno
)
5726 && bitmap_bit_p (&lra_inheritance_pseudos
, dregno
)
5728 = lra_reg_info
[dregno
].restore_regno
) >= 0)
5730 if (GET_CODE (SET_DEST (set
)) == SUBREG
)
5731 SUBREG_REG (SET_DEST (set
))
5732 = regno_reg_rtx
[restore_regno
];
5734 SET_DEST (set
) = regno_reg_rtx
[restore_regno
];
5736 lra_push_insn_and_update_insn_regno_info (curr_insn
);
5737 lra_set_used_insn_alternative_by_uid
5738 (INSN_UID (curr_insn
), -1);
5740 if (lra_dump_file
!= NULL
)
5742 fprintf (lra_dump_file
, " Change reload insn:\n");
5743 dump_insn_slim (lra_dump_file
, curr_insn
);
5750 struct lra_insn_reg
*reg
;
5751 bool restored_regs_p
= false;
5752 bool kept_regs_p
= false;
5754 curr_id
= lra_get_insn_recog_data (curr_insn
);
5755 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
5758 restore_regno
= lra_reg_info
[regno
].restore_regno
;
5759 if (restore_regno
>= 0)
5761 if (change_p
&& bitmap_bit_p (remove_pseudos
, regno
))
5763 substitute_pseudo_within_insn (
5764 curr_insn
, regno
, regno_reg_rtx
[restore_regno
]);
5765 restored_regs_p
= true;
5771 if (NONDEBUG_INSN_P (curr_insn
) && kept_regs_p
)
5773 /* The instruction has changed since the previous
5774 constraints pass. */
5775 lra_push_insn_and_update_insn_regno_info (curr_insn
);
5776 lra_set_used_insn_alternative_by_uid
5777 (INSN_UID (curr_insn
), -1);
5779 else if (restored_regs_p
)
5780 /* The instruction has been restored to the form that
5781 it had during the previous constraints pass. */
5782 lra_update_insn_regno_info (curr_insn
);
5783 if (restored_regs_p
&& lra_dump_file
!= NULL
)
5785 fprintf (lra_dump_file
, " Insn after restoring regs:\n");
5786 dump_insn_slim (lra_dump_file
, curr_insn
);
5794 /* If optional reload pseudos failed to get a hard register or was not
5795 inherited, it is better to remove optional reloads. We do this
5796 transformation after undoing inheritance to figure out necessity to
5797 remove optional reloads easier. Return true if we do any
5800 undo_optional_reloads (void)
5802 bool change_p
, keep_p
;
5803 unsigned int regno
, uid
;
5804 bitmap_iterator bi
, bi2
;
5807 bitmap_head removed_optional_reload_pseudos
, insn_bitmap
;
5809 bitmap_initialize (&removed_optional_reload_pseudos
, ®_obstack
);
5810 bitmap_copy (&removed_optional_reload_pseudos
, &lra_optional_reload_pseudos
);
5811 EXECUTE_IF_SET_IN_BITMAP (&lra_optional_reload_pseudos
, 0, regno
, bi
)
5814 /* Keep optional reloads from previous subpasses. */
5815 if (lra_reg_info
[regno
].restore_regno
< 0
5816 /* If the original pseudo changed its allocation, just
5817 removing the optional pseudo is dangerous as the original
5818 pseudo will have longer live range. */
5819 || reg_renumber
[lra_reg_info
[regno
].restore_regno
] >= 0)
5821 else if (reg_renumber
[regno
] >= 0)
5822 EXECUTE_IF_SET_IN_BITMAP (&lra_reg_info
[regno
].insn_bitmap
, 0, uid
, bi2
)
5824 insn
= lra_insn_recog_data
[uid
]->insn
;
5825 if ((set
= single_set (insn
)) == NULL_RTX
)
5827 src
= SET_SRC (set
);
5828 dest
= SET_DEST (set
);
5829 if (! REG_P (src
) || ! REG_P (dest
))
5831 if (REGNO (dest
) == regno
5832 /* Ignore insn for optional reloads itself. */
5833 && lra_reg_info
[regno
].restore_regno
!= (int) REGNO (src
)
5834 /* Check only inheritance on last inheritance pass. */
5835 && (int) REGNO (src
) >= new_regno_start
5836 /* Check that the optional reload was inherited. */
5837 && bitmap_bit_p (&lra_inheritance_pseudos
, REGNO (src
)))
5845 bitmap_clear_bit (&removed_optional_reload_pseudos
, regno
);
5846 if (lra_dump_file
!= NULL
)
5847 fprintf (lra_dump_file
, "Keep optional reload reg %d\n", regno
);
5850 change_p
= ! bitmap_empty_p (&removed_optional_reload_pseudos
);
5851 bitmap_initialize (&insn_bitmap
, ®_obstack
);
5852 EXECUTE_IF_SET_IN_BITMAP (&removed_optional_reload_pseudos
, 0, regno
, bi
)
5854 if (lra_dump_file
!= NULL
)
5855 fprintf (lra_dump_file
, "Remove optional reload reg %d\n", regno
);
5856 bitmap_copy (&insn_bitmap
, &lra_reg_info
[regno
].insn_bitmap
);
5857 EXECUTE_IF_SET_IN_BITMAP (&insn_bitmap
, 0, uid
, bi2
)
5859 insn
= lra_insn_recog_data
[uid
]->insn
;
5860 if ((set
= single_set (insn
)) != NULL_RTX
)
5862 src
= SET_SRC (set
);
5863 dest
= SET_DEST (set
);
5864 if (REG_P (src
) && REG_P (dest
)
5865 && ((REGNO (src
) == regno
5866 && (lra_reg_info
[regno
].restore_regno
5867 == (int) REGNO (dest
)))
5868 || (REGNO (dest
) == regno
5869 && (lra_reg_info
[regno
].restore_regno
5870 == (int) REGNO (src
)))))
5872 if (lra_dump_file
!= NULL
)
5874 fprintf (lra_dump_file
, " Deleting move %u\n",
5876 dump_insn_slim (lra_dump_file
, insn
);
5878 lra_set_insn_deleted (insn
);
5881 /* We should not worry about generation memory-memory
5882 moves here as if the corresponding inheritance did
5883 not work (inheritance pseudo did not get a hard reg),
5884 we remove the inheritance pseudo and the optional
5887 substitute_pseudo_within_insn (
5889 regno_reg_rtx
[lra_reg_info
[regno
].restore_regno
]);
5890 lra_update_insn_regno_info (insn
);
5891 if (lra_dump_file
!= NULL
)
5893 fprintf (lra_dump_file
,
5894 " Restoring original insn:\n");
5895 dump_insn_slim (lra_dump_file
, insn
);
5899 /* Clear restore_regnos. */
5900 EXECUTE_IF_SET_IN_BITMAP (&lra_optional_reload_pseudos
, 0, regno
, bi
)
5901 lra_reg_info
[regno
].restore_regno
= -1;
5902 bitmap_clear (&insn_bitmap
);
5903 bitmap_clear (&removed_optional_reload_pseudos
);
5907 /* Entry function for undoing inheritance/split transformation. Return true
5908 if we did any RTL change in this pass. */
5910 lra_undo_inheritance (void)
5913 int restore_regno
, hard_regno
;
5914 int n_all_inherit
, n_inherit
, n_all_split
, n_split
;
5915 bitmap_head remove_pseudos
;
5919 lra_undo_inheritance_iter
++;
5920 if (lra_undo_inheritance_iter
> LRA_MAX_INHERITANCE_PASSES
)
5922 if (lra_dump_file
!= NULL
)
5923 fprintf (lra_dump_file
,
5924 "\n********** Undoing inheritance #%d: **********\n\n",
5925 lra_undo_inheritance_iter
);
5926 bitmap_initialize (&remove_pseudos
, ®_obstack
);
5927 n_inherit
= n_all_inherit
= 0;
5928 EXECUTE_IF_SET_IN_BITMAP (&lra_inheritance_pseudos
, 0, regno
, bi
)
5929 if (lra_reg_info
[regno
].restore_regno
>= 0)
5932 if (reg_renumber
[regno
] < 0
5933 /* If the original pseudo changed its allocation, just
5934 removing inheritance is dangerous as for changing
5935 allocation we used shorter live-ranges. */
5936 && reg_renumber
[lra_reg_info
[regno
].restore_regno
] < 0)
5937 bitmap_set_bit (&remove_pseudos
, regno
);
5941 if (lra_dump_file
!= NULL
&& n_all_inherit
!= 0)
5942 fprintf (lra_dump_file
, "Inherit %d out of %d (%.2f%%)\n",
5943 n_inherit
, n_all_inherit
,
5944 (double) n_inherit
/ n_all_inherit
* 100);
5945 n_split
= n_all_split
= 0;
5946 EXECUTE_IF_SET_IN_BITMAP (&lra_split_regs
, 0, regno
, bi
)
5947 if ((restore_regno
= lra_reg_info
[regno
].restore_regno
) >= 0)
5950 hard_regno
= (restore_regno
>= FIRST_PSEUDO_REGISTER
5951 ? reg_renumber
[restore_regno
] : restore_regno
);
5952 if (hard_regno
< 0 || reg_renumber
[regno
] == hard_regno
)
5953 bitmap_set_bit (&remove_pseudos
, regno
);
5957 if (lra_dump_file
!= NULL
)
5958 fprintf (lra_dump_file
, " Keep split r%d (orig=r%d)\n",
5959 regno
, restore_regno
);
5962 if (lra_dump_file
!= NULL
&& n_all_split
!= 0)
5963 fprintf (lra_dump_file
, "Split %d out of %d (%.2f%%)\n",
5964 n_split
, n_all_split
,
5965 (double) n_split
/ n_all_split
* 100);
5966 change_p
= remove_inheritance_pseudos (&remove_pseudos
);
5967 bitmap_clear (&remove_pseudos
);
5968 /* Clear restore_regnos. */
5969 EXECUTE_IF_SET_IN_BITMAP (&lra_inheritance_pseudos
, 0, regno
, bi
)
5970 lra_reg_info
[regno
].restore_regno
= -1;
5971 EXECUTE_IF_SET_IN_BITMAP (&lra_split_regs
, 0, regno
, bi
)
5972 lra_reg_info
[regno
].restore_regno
= -1;
5973 change_p
= undo_optional_reloads () || change_p
;