1 /* Code for RTL transformations to satisfy insn constraints.
2 Copyright (C) 2010-2015 Free Software Foundation, Inc.
3 Contributed by Vladimir Makarov <vmakarov@redhat.com>.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 3, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
22 /* This file contains code for 3 passes: constraint pass,
23 inheritance/split pass, and pass for undoing failed inheritance and
26 The major goal of constraint pass is to transform RTL to satisfy
27 insn and address constraints by:
28 o choosing insn alternatives;
29 o generating *reload insns* (or reloads in brief) and *reload
30 pseudos* which will get necessary hard registers later;
31 o substituting pseudos with equivalent values and removing the
32 instructions that initialized those pseudos.
34 The constraint pass has biggest and most complicated code in LRA.
35 There are a lot of important details like:
36 o reuse of input reload pseudos to simplify reload pseudo
38 o some heuristics to choose insn alternative to improve the
42 The pass is mimicking former reload pass in alternative choosing
43 because the reload pass is oriented to current machine description
44 model. It might be changed if the machine description model is
47 There is special code for preventing all LRA and this pass cycling
50 On the first iteration of the pass we process every instruction and
51 choose an alternative for each one. On subsequent iterations we try
52 to avoid reprocessing instructions if we can be sure that the old
53 choice is still valid.
55 The inheritance/spilt pass is to transform code to achieve
56 ineheritance and live range splitting. It is done on backward
59 The inheritance optimization goal is to reuse values in hard
60 registers. There is analogous optimization in old reload pass. The
61 inheritance is achieved by following transformation:
63 reload_p1 <- p reload_p1 <- p
64 ... new_p <- reload_p1
66 reload_p2 <- p reload_p2 <- new_p
68 where p is spilled and not changed between the insns. Reload_p1 is
69 also called *original pseudo* and new_p is called *inheritance
72 The subsequent assignment pass will try to assign the same (or
73 another if it is not possible) hard register to new_p as to
74 reload_p1 or reload_p2.
76 If the assignment pass fails to assign a hard register to new_p,
77 this file will undo the inheritance and restore the original code.
78 This is because implementing the above sequence with a spilled
79 new_p would make the code much worse. The inheritance is done in
80 EBB scope. The above is just a simplified example to get an idea
81 of the inheritance as the inheritance is also done for non-reload
84 Splitting (transformation) is also done in EBB scope on the same
85 pass as the inheritance:
87 r <- ... or ... <- r r <- ... or ... <- r
88 ... s <- r (new insn -- save)
90 ... r <- s (new insn -- restore)
93 The *split pseudo* s is assigned to the hard register of the
94 original pseudo or hard register r.
97 o In EBBs with high register pressure for global pseudos (living
98 in at least 2 BBs) and assigned to hard registers when there
99 are more one reloads needing the hard registers;
100 o for pseudos needing save/restore code around calls.
102 If the split pseudo still has the same hard register as the
103 original pseudo after the subsequent assignment pass or the
104 original pseudo was split, the opposite transformation is done on
105 the same pass for undoing inheritance. */
111 #include "coretypes.h"
113 #include "hard-reg-set.h"
117 #include "insn-config.h"
118 #include "insn-codes.h"
121 #include "addresses.h"
124 #include "hash-set.h"
126 #include "machmode.h"
128 #include "function.h"
131 #include "statistics.h"
132 #include "double-int.h"
134 #include "fixed-value.h"
136 #include "wide-int.h"
143 #include "emit-rtl.h"
148 #include "dominance.h"
151 #include "basic-block.h"
156 #include "rtl-error.h"
159 /* Value of LRA_CURR_RELOAD_NUM at the beginning of BB of the current
160 insn. Remember that LRA_CURR_RELOAD_NUM is the number of emitted
162 static int bb_reload_num
;
164 /* The current insn being processed and corresponding its single set
165 (NULL otherwise), its data (basic block, the insn data, the insn
166 static data, and the mode of each operand). */
167 static rtx_insn
*curr_insn
;
168 static rtx curr_insn_set
;
169 static basic_block curr_bb
;
170 static lra_insn_recog_data_t curr_id
;
171 static struct lra_static_insn_data
*curr_static_id
;
172 static machine_mode curr_operand_mode
[MAX_RECOG_OPERANDS
];
176 /* Start numbers for new registers and insns at the current constraints
178 static int new_regno_start
;
179 static int new_insn_uid_start
;
181 /* If LOC is nonnull, strip any outer subreg from it. */
183 strip_subreg (rtx
*loc
)
185 return loc
&& GET_CODE (*loc
) == SUBREG
? &SUBREG_REG (*loc
) : loc
;
188 /* Return hard regno of REGNO or if it is was not assigned to a hard
189 register, use a hard register from its allocno class. */
191 get_try_hard_regno (int regno
)
194 enum reg_class rclass
;
196 if ((hard_regno
= regno
) >= FIRST_PSEUDO_REGISTER
)
197 hard_regno
= lra_get_regno_hard_regno (regno
);
200 rclass
= lra_get_allocno_class (regno
);
201 if (rclass
== NO_REGS
)
203 return ira_class_hard_regs
[rclass
][0];
206 /* Return final hard regno (plus offset) which will be after
207 elimination. We do this for matching constraints because the final
208 hard regno could have a different class. */
210 get_final_hard_regno (int hard_regno
, int offset
)
214 hard_regno
= lra_get_elimination_hard_regno (hard_regno
);
215 return hard_regno
+ offset
;
218 /* Return hard regno of X after removing subreg and making
219 elimination. If X is not a register or subreg of register, return
220 -1. For pseudo use its assignment. */
222 get_hard_regno (rtx x
)
225 int offset
, hard_regno
;
228 if (GET_CODE (x
) == SUBREG
)
229 reg
= SUBREG_REG (x
);
232 if ((hard_regno
= REGNO (reg
)) >= FIRST_PSEUDO_REGISTER
)
233 hard_regno
= lra_get_regno_hard_regno (hard_regno
);
237 if (GET_CODE (x
) == SUBREG
)
238 offset
+= subreg_regno_offset (hard_regno
, GET_MODE (reg
),
239 SUBREG_BYTE (x
), GET_MODE (x
));
240 return get_final_hard_regno (hard_regno
, offset
);
243 /* If REGNO is a hard register or has been allocated a hard register,
244 return the class of that register. If REGNO is a reload pseudo
245 created by the current constraints pass, return its allocno class.
246 Return NO_REGS otherwise. */
247 static enum reg_class
248 get_reg_class (int regno
)
252 if ((hard_regno
= regno
) >= FIRST_PSEUDO_REGISTER
)
253 hard_regno
= lra_get_regno_hard_regno (regno
);
256 hard_regno
= get_final_hard_regno (hard_regno
, 0);
257 return REGNO_REG_CLASS (hard_regno
);
259 if (regno
>= new_regno_start
)
260 return lra_get_allocno_class (regno
);
264 /* Return true if REG satisfies (or will satisfy) reg class constraint
265 CL. Use elimination first if REG is a hard register. If REG is a
266 reload pseudo created by this constraints pass, assume that it will
267 be allocated a hard register from its allocno class, but allow that
268 class to be narrowed to CL if it is currently a superset of CL.
270 If NEW_CLASS is nonnull, set *NEW_CLASS to the new allocno class of
271 REGNO (reg), or NO_REGS if no change in its class was needed. */
273 in_class_p (rtx reg
, enum reg_class cl
, enum reg_class
*new_class
)
275 enum reg_class rclass
, common_class
;
276 machine_mode reg_mode
;
277 int class_size
, hard_regno
, nregs
, i
, j
;
278 int regno
= REGNO (reg
);
280 if (new_class
!= NULL
)
281 *new_class
= NO_REGS
;
282 if (regno
< FIRST_PSEUDO_REGISTER
)
285 rtx
*final_loc
= &final_reg
;
287 lra_eliminate_reg_if_possible (final_loc
);
288 return TEST_HARD_REG_BIT (reg_class_contents
[cl
], REGNO (*final_loc
));
290 reg_mode
= GET_MODE (reg
);
291 rclass
= get_reg_class (regno
);
292 if (regno
< new_regno_start
293 /* Do not allow the constraints for reload instructions to
294 influence the classes of new pseudos. These reloads are
295 typically moves that have many alternatives, and restricting
296 reload pseudos for one alternative may lead to situations
297 where other reload pseudos are no longer allocatable. */
298 || (INSN_UID (curr_insn
) >= new_insn_uid_start
299 && curr_insn_set
!= NULL
300 && ((OBJECT_P (SET_SRC (curr_insn_set
))
301 && ! CONSTANT_P (SET_SRC (curr_insn_set
)))
302 || (GET_CODE (SET_SRC (curr_insn_set
)) == SUBREG
303 && OBJECT_P (SUBREG_REG (SET_SRC (curr_insn_set
)))
304 && ! CONSTANT_P (SUBREG_REG (SET_SRC (curr_insn_set
)))))))
305 /* When we don't know what class will be used finally for reload
306 pseudos, we use ALL_REGS. */
307 return ((regno
>= new_regno_start
&& rclass
== ALL_REGS
)
308 || (rclass
!= NO_REGS
&& ira_class_subset_p
[rclass
][cl
]
309 && ! hard_reg_set_subset_p (reg_class_contents
[cl
],
310 lra_no_alloc_regs
)));
313 common_class
= ira_reg_class_subset
[rclass
][cl
];
314 if (new_class
!= NULL
)
315 *new_class
= common_class
;
316 if (hard_reg_set_subset_p (reg_class_contents
[common_class
],
319 /* Check that there are enough allocatable regs. */
320 class_size
= ira_class_hard_regs_num
[common_class
];
321 for (i
= 0; i
< class_size
; i
++)
323 hard_regno
= ira_class_hard_regs
[common_class
][i
];
324 nregs
= hard_regno_nregs
[hard_regno
][reg_mode
];
327 for (j
= 0; j
< nregs
; j
++)
328 if (TEST_HARD_REG_BIT (lra_no_alloc_regs
, hard_regno
+ j
)
329 || ! TEST_HARD_REG_BIT (reg_class_contents
[common_class
],
339 /* Return true if REGNO satisfies a memory constraint. */
343 return get_reg_class (regno
) == NO_REGS
;
346 /* Return 1 if ADDR is a valid memory address for mode MODE in address
347 space AS, and check that each pseudo has the proper kind of hard
350 valid_address_p (machine_mode mode ATTRIBUTE_UNUSED
,
351 rtx addr
, addr_space_t as
)
353 #ifdef GO_IF_LEGITIMATE_ADDRESS
354 lra_assert (ADDR_SPACE_GENERIC_P (as
));
355 GO_IF_LEGITIMATE_ADDRESS (mode
, addr
, win
);
361 return targetm
.addr_space
.legitimate_address_p (mode
, addr
, 0, as
);
366 /* Temporarily eliminates registers in an address (for the lifetime of
368 class address_eliminator
{
370 address_eliminator (struct address_info
*ad
);
371 ~address_eliminator ();
374 struct address_info
*m_ad
;
382 address_eliminator::address_eliminator (struct address_info
*ad
)
384 m_base_loc (strip_subreg (ad
->base_term
)),
385 m_base_reg (NULL_RTX
),
386 m_index_loc (strip_subreg (ad
->index_term
)),
387 m_index_reg (NULL_RTX
)
389 if (m_base_loc
!= NULL
)
391 m_base_reg
= *m_base_loc
;
392 lra_eliminate_reg_if_possible (m_base_loc
);
393 if (m_ad
->base_term2
!= NULL
)
394 *m_ad
->base_term2
= *m_ad
->base_term
;
396 if (m_index_loc
!= NULL
)
398 m_index_reg
= *m_index_loc
;
399 lra_eliminate_reg_if_possible (m_index_loc
);
403 address_eliminator::~address_eliminator ()
405 if (m_base_loc
&& *m_base_loc
!= m_base_reg
)
407 *m_base_loc
= m_base_reg
;
408 if (m_ad
->base_term2
!= NULL
)
409 *m_ad
->base_term2
= *m_ad
->base_term
;
411 if (m_index_loc
&& *m_index_loc
!= m_index_reg
)
412 *m_index_loc
= m_index_reg
;
415 /* Return true if the eliminated form of AD is a legitimate target address. */
417 valid_address_p (struct address_info
*ad
)
419 address_eliminator
eliminator (ad
);
420 return valid_address_p (ad
->mode
, *ad
->outer
, ad
->as
);
423 /* Return true if the eliminated form of memory reference OP satisfies
424 extra memory constraint CONSTRAINT. */
426 satisfies_memory_constraint_p (rtx op
, enum constraint_num constraint
)
428 struct address_info ad
;
430 decompose_mem_address (&ad
, op
);
431 address_eliminator
eliminator (&ad
);
432 return constraint_satisfied_p (op
, constraint
);
435 /* Return true if the eliminated form of address AD satisfies extra
436 address constraint CONSTRAINT. */
438 satisfies_address_constraint_p (struct address_info
*ad
,
439 enum constraint_num constraint
)
441 address_eliminator
eliminator (ad
);
442 return constraint_satisfied_p (*ad
->outer
, constraint
);
445 /* Return true if the eliminated form of address OP satisfies extra
446 address constraint CONSTRAINT. */
448 satisfies_address_constraint_p (rtx op
, enum constraint_num constraint
)
450 struct address_info ad
;
452 decompose_lea_address (&ad
, &op
);
453 return satisfies_address_constraint_p (&ad
, constraint
);
456 /* Initiate equivalences for LRA. As we keep original equivalences
457 before any elimination, we need to make copies otherwise any change
458 in insns might change the equivalences. */
460 lra_init_equiv (void)
462 ira_expand_reg_equiv ();
463 for (int i
= FIRST_PSEUDO_REGISTER
; i
< max_reg_num (); i
++)
467 if ((res
= ira_reg_equiv
[i
].memory
) != NULL_RTX
)
468 ira_reg_equiv
[i
].memory
= copy_rtx (res
);
469 if ((res
= ira_reg_equiv
[i
].invariant
) != NULL_RTX
)
470 ira_reg_equiv
[i
].invariant
= copy_rtx (res
);
474 static rtx
loc_equivalence_callback (rtx
, const_rtx
, void *);
476 /* Update equivalence for REGNO. We need to this as the equivalence
477 might contain other pseudos which are changed by their
480 update_equiv (int regno
)
484 if ((x
= ira_reg_equiv
[regno
].memory
) != NULL_RTX
)
485 ira_reg_equiv
[regno
].memory
486 = simplify_replace_fn_rtx (x
, NULL_RTX
, loc_equivalence_callback
,
488 if ((x
= ira_reg_equiv
[regno
].invariant
) != NULL_RTX
)
489 ira_reg_equiv
[regno
].invariant
490 = simplify_replace_fn_rtx (x
, NULL_RTX
, loc_equivalence_callback
,
494 /* If we have decided to substitute X with another value, return that
495 value, otherwise return X. */
502 if (! REG_P (x
) || (regno
= REGNO (x
)) < FIRST_PSEUDO_REGISTER
503 || ! ira_reg_equiv
[regno
].defined_p
504 || ! ira_reg_equiv
[regno
].profitable_p
505 || lra_get_regno_hard_regno (regno
) >= 0)
507 if ((res
= ira_reg_equiv
[regno
].memory
) != NULL_RTX
)
509 if (targetm
.cannot_substitute_mem_equiv_p (res
))
513 if ((res
= ira_reg_equiv
[regno
].constant
) != NULL_RTX
)
515 if ((res
= ira_reg_equiv
[regno
].invariant
) != NULL_RTX
)
520 /* If we have decided to substitute X with the equivalent value,
521 return that value after elimination for INSN, otherwise return
524 get_equiv_with_elimination (rtx x
, rtx_insn
*insn
)
526 rtx res
= get_equiv (x
);
528 if (x
== res
|| CONSTANT_P (res
))
530 return lra_eliminate_regs_1 (insn
, res
, GET_MODE (res
),
531 0, false, false, true);
534 /* Set up curr_operand_mode. */
536 init_curr_operand_mode (void)
538 int nop
= curr_static_id
->n_operands
;
539 for (int i
= 0; i
< nop
; i
++)
541 machine_mode mode
= GET_MODE (*curr_id
->operand_loc
[i
]);
542 if (mode
== VOIDmode
)
544 /* The .md mode for address operands is the mode of the
545 addressed value rather than the mode of the address itself. */
546 if (curr_id
->icode
>= 0 && curr_static_id
->operand
[i
].is_address
)
549 mode
= curr_static_id
->operand
[i
].mode
;
551 curr_operand_mode
[i
] = mode
;
557 /* The page contains code to reuse input reloads. */
559 /* Structure describes input reload of the current insns. */
562 /* Reloaded value. */
564 /* Reload pseudo used. */
568 /* The number of elements in the following array. */
569 static int curr_insn_input_reloads_num
;
570 /* Array containing info about input reloads. It is used to find the
571 same input reload and reuse the reload pseudo in this case. */
572 static struct input_reload curr_insn_input_reloads
[LRA_MAX_INSN_RELOADS
];
574 /* Initiate data concerning reuse of input reloads for the current
577 init_curr_insn_input_reloads (void)
579 curr_insn_input_reloads_num
= 0;
582 /* Create a new pseudo using MODE, RCLASS, ORIGINAL or reuse already
583 created input reload pseudo (only if TYPE is not OP_OUT). Don't
584 reuse pseudo if IN_SUBREG_P is true and the reused pseudo should be
585 wrapped up in SUBREG. The result pseudo is returned through
586 RESULT_REG. Return TRUE if we created a new pseudo, FALSE if we
587 reused the already created input reload pseudo. Use TITLE to
588 describe new registers for debug purposes. */
590 get_reload_reg (enum op_type type
, machine_mode mode
, rtx original
,
591 enum reg_class rclass
, bool in_subreg_p
,
592 const char *title
, rtx
*result_reg
)
595 enum reg_class new_class
;
600 = lra_create_new_reg_with_unique_value (mode
, original
, rclass
, title
);
603 /* Prevent reuse value of expression with side effects,
604 e.g. volatile memory. */
605 if (! side_effects_p (original
))
606 for (i
= 0; i
< curr_insn_input_reloads_num
; i
++)
607 if (rtx_equal_p (curr_insn_input_reloads
[i
].input
, original
)
608 && in_class_p (curr_insn_input_reloads
[i
].reg
, rclass
, &new_class
))
610 rtx reg
= curr_insn_input_reloads
[i
].reg
;
612 /* If input is equal to original and both are VOIDmode,
613 GET_MODE (reg) might be still different from mode.
614 Ensure we don't return *result_reg with wrong mode. */
615 if (GET_MODE (reg
) != mode
)
619 if (GET_MODE_SIZE (GET_MODE (reg
)) < GET_MODE_SIZE (mode
))
621 reg
= lowpart_subreg (mode
, reg
, GET_MODE (reg
));
622 if (reg
== NULL_RTX
|| GET_CODE (reg
) != SUBREG
)
626 if (lra_dump_file
!= NULL
)
628 fprintf (lra_dump_file
, " Reuse r%d for reload ", regno
);
629 dump_value_slim (lra_dump_file
, original
, 1);
631 if (new_class
!= lra_get_allocno_class (regno
))
632 lra_change_class (regno
, new_class
, ", change to", false);
633 if (lra_dump_file
!= NULL
)
634 fprintf (lra_dump_file
, "\n");
637 *result_reg
= lra_create_new_reg (mode
, original
, rclass
, title
);
638 lra_assert (curr_insn_input_reloads_num
< LRA_MAX_INSN_RELOADS
);
639 curr_insn_input_reloads
[curr_insn_input_reloads_num
].input
= original
;
640 curr_insn_input_reloads
[curr_insn_input_reloads_num
++].reg
= *result_reg
;
646 /* The page contains code to extract memory address parts. */
648 /* Wrapper around REGNO_OK_FOR_INDEX_P, to allow pseudos. */
650 ok_for_index_p_nonstrict (rtx reg
)
652 unsigned regno
= REGNO (reg
);
654 return regno
>= FIRST_PSEUDO_REGISTER
|| REGNO_OK_FOR_INDEX_P (regno
);
657 /* A version of regno_ok_for_base_p for use here, when all pseudos
658 should count as OK. Arguments as for regno_ok_for_base_p. */
660 ok_for_base_p_nonstrict (rtx reg
, machine_mode mode
, addr_space_t as
,
661 enum rtx_code outer_code
, enum rtx_code index_code
)
663 unsigned regno
= REGNO (reg
);
665 if (regno
>= FIRST_PSEUDO_REGISTER
)
667 return ok_for_base_p_1 (regno
, mode
, as
, outer_code
, index_code
);
672 /* The page contains major code to choose the current insn alternative
673 and generate reloads for it. */
675 /* Return the offset from REGNO of the least significant register
678 This function is used to tell whether two registers satisfy
679 a matching constraint. (reg:MODE1 REGNO1) matches (reg:MODE2 REGNO2) if:
681 REGNO1 + lra_constraint_offset (REGNO1, MODE1)
682 == REGNO2 + lra_constraint_offset (REGNO2, MODE2) */
684 lra_constraint_offset (int regno
, machine_mode mode
)
686 lra_assert (regno
< FIRST_PSEUDO_REGISTER
);
687 if (WORDS_BIG_ENDIAN
&& GET_MODE_SIZE (mode
) > UNITS_PER_WORD
688 && SCALAR_INT_MODE_P (mode
))
689 return hard_regno_nregs
[regno
][mode
] - 1;
693 /* Like rtx_equal_p except that it allows a REG and a SUBREG to match
694 if they are the same hard reg, and has special hacks for
695 auto-increment and auto-decrement. This is specifically intended for
696 process_alt_operands to use in determining whether two operands
697 match. X is the operand whose number is the lower of the two.
699 It is supposed that X is the output operand and Y is the input
700 operand. Y_HARD_REGNO is the final hard regno of register Y or
701 register in subreg Y as we know it now. Otherwise, it is a
704 operands_match_p (rtx x
, rtx y
, int y_hard_regno
)
707 RTX_CODE code
= GET_CODE (x
);
712 if ((code
== REG
|| (code
== SUBREG
&& REG_P (SUBREG_REG (x
))))
713 && (REG_P (y
) || (GET_CODE (y
) == SUBREG
&& REG_P (SUBREG_REG (y
)))))
717 i
= get_hard_regno (x
);
721 if ((j
= y_hard_regno
) < 0)
724 i
+= lra_constraint_offset (i
, GET_MODE (x
));
725 j
+= lra_constraint_offset (j
, GET_MODE (y
));
730 /* If two operands must match, because they are really a single
731 operand of an assembler insn, then two post-increments are invalid
732 because the assembler insn would increment only once. On the
733 other hand, a post-increment matches ordinary indexing if the
734 post-increment is the output operand. */
735 if (code
== POST_DEC
|| code
== POST_INC
|| code
== POST_MODIFY
)
736 return operands_match_p (XEXP (x
, 0), y
, y_hard_regno
);
738 /* Two pre-increments are invalid because the assembler insn would
739 increment only once. On the other hand, a pre-increment matches
740 ordinary indexing if the pre-increment is the input operand. */
741 if (GET_CODE (y
) == PRE_DEC
|| GET_CODE (y
) == PRE_INC
742 || GET_CODE (y
) == PRE_MODIFY
)
743 return operands_match_p (x
, XEXP (y
, 0), -1);
747 if (code
== REG
&& GET_CODE (y
) == SUBREG
&& REG_P (SUBREG_REG (y
))
748 && x
== SUBREG_REG (y
))
750 if (GET_CODE (y
) == REG
&& code
== SUBREG
&& REG_P (SUBREG_REG (x
))
751 && SUBREG_REG (x
) == y
)
754 /* Now we have disposed of all the cases in which different rtx
756 if (code
!= GET_CODE (y
))
759 /* (MULT:SI x y) and (MULT:HI x y) are NOT equivalent. */
760 if (GET_MODE (x
) != GET_MODE (y
))
769 return LABEL_REF_LABEL (x
) == LABEL_REF_LABEL (y
);
771 return XSTR (x
, 0) == XSTR (y
, 0);
777 /* Compare the elements. If any pair of corresponding elements fail
778 to match, return false for the whole things. */
780 fmt
= GET_RTX_FORMAT (code
);
781 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
787 if (XWINT (x
, i
) != XWINT (y
, i
))
792 if (XINT (x
, i
) != XINT (y
, i
))
797 val
= operands_match_p (XEXP (x
, i
), XEXP (y
, i
), -1);
806 if (XVECLEN (x
, i
) != XVECLEN (y
, i
))
808 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; --j
)
810 val
= operands_match_p (XVECEXP (x
, i
, j
), XVECEXP (y
, i
, j
), -1);
816 /* It is believed that rtx's at this level will never
817 contain anything but integers and other rtx's, except for
818 within LABEL_REFs and SYMBOL_REFs. */
826 /* True if X is a constant that can be forced into the constant pool.
827 MODE is the mode of the operand, or VOIDmode if not known. */
828 #define CONST_POOL_OK_P(MODE, X) \
829 ((MODE) != VOIDmode \
831 && GET_CODE (X) != HIGH \
832 && !targetm.cannot_force_const_mem (MODE, X))
834 /* True if C is a non-empty register class that has too few registers
835 to be safely used as a reload target class. */
836 #define SMALL_REGISTER_CLASS_P(C) \
837 (ira_class_hard_regs_num [(C)] == 1 \
838 || (ira_class_hard_regs_num [(C)] >= 1 \
839 && targetm.class_likely_spilled_p (C)))
841 /* If REG is a reload pseudo, try to make its class satisfying CL. */
843 narrow_reload_pseudo_class (rtx reg
, enum reg_class cl
)
845 enum reg_class rclass
;
847 /* Do not make more accurate class from reloads generated. They are
848 mostly moves with a lot of constraints. Making more accurate
849 class may results in very narrow class and impossibility of find
850 registers for several reloads of one insn. */
851 if (INSN_UID (curr_insn
) >= new_insn_uid_start
)
853 if (GET_CODE (reg
) == SUBREG
)
854 reg
= SUBREG_REG (reg
);
855 if (! REG_P (reg
) || (int) REGNO (reg
) < new_regno_start
)
857 if (in_class_p (reg
, cl
, &rclass
) && rclass
!= cl
)
858 lra_change_class (REGNO (reg
), rclass
, " Change to", true);
861 /* Generate reloads for matching OUT and INS (array of input operand
862 numbers with end marker -1) with reg class GOAL_CLASS. Add input
863 and output reloads correspondingly to the lists *BEFORE and *AFTER.
864 OUT might be negative. In this case we generate input reloads for
865 matched input operands INS. */
867 match_reload (signed char out
, signed char *ins
, enum reg_class goal_class
,
868 rtx_insn
**before
, rtx_insn
**after
)
871 rtx new_in_reg
, new_out_reg
, reg
, clobber
;
872 machine_mode inmode
, outmode
;
873 rtx in_rtx
= *curr_id
->operand_loc
[ins
[0]];
874 rtx out_rtx
= out
< 0 ? in_rtx
: *curr_id
->operand_loc
[out
];
876 inmode
= curr_operand_mode
[ins
[0]];
877 outmode
= out
< 0 ? inmode
: curr_operand_mode
[out
];
878 push_to_sequence (*before
);
879 if (inmode
!= outmode
)
881 if (GET_MODE_SIZE (inmode
) > GET_MODE_SIZE (outmode
))
884 = lra_create_new_reg_with_unique_value (inmode
, in_rtx
,
886 if (SCALAR_INT_MODE_P (inmode
))
887 new_out_reg
= gen_lowpart_SUBREG (outmode
, reg
);
889 new_out_reg
= gen_rtx_SUBREG (outmode
, reg
, 0);
890 LRA_SUBREG_P (new_out_reg
) = 1;
891 /* If the input reg is dying here, we can use the same hard
892 register for REG and IN_RTX. We do it only for original
893 pseudos as reload pseudos can die although original
894 pseudos still live where reload pseudos dies. */
895 if (REG_P (in_rtx
) && (int) REGNO (in_rtx
) < lra_new_regno_start
896 && find_regno_note (curr_insn
, REG_DEAD
, REGNO (in_rtx
)))
897 lra_assign_reg_val (REGNO (in_rtx
), REGNO (reg
));
902 = lra_create_new_reg_with_unique_value (outmode
, out_rtx
,
904 if (SCALAR_INT_MODE_P (outmode
))
905 new_in_reg
= gen_lowpart_SUBREG (inmode
, reg
);
907 new_in_reg
= gen_rtx_SUBREG (inmode
, reg
, 0);
908 /* NEW_IN_REG is non-paradoxical subreg. We don't want
909 NEW_OUT_REG living above. We add clobber clause for
910 this. This is just a temporary clobber. We can remove
911 it at the end of LRA work. */
912 clobber
= emit_clobber (new_out_reg
);
913 LRA_TEMP_CLOBBER_P (PATTERN (clobber
)) = 1;
914 LRA_SUBREG_P (new_in_reg
) = 1;
915 if (GET_CODE (in_rtx
) == SUBREG
)
917 rtx subreg_reg
= SUBREG_REG (in_rtx
);
919 /* If SUBREG_REG is dying here and sub-registers IN_RTX
920 and NEW_IN_REG are similar, we can use the same hard
921 register for REG and SUBREG_REG. */
922 if (REG_P (subreg_reg
)
923 && (int) REGNO (subreg_reg
) < lra_new_regno_start
924 && GET_MODE (subreg_reg
) == outmode
925 && SUBREG_BYTE (in_rtx
) == SUBREG_BYTE (new_in_reg
)
926 && find_regno_note (curr_insn
, REG_DEAD
, REGNO (subreg_reg
)))
927 lra_assign_reg_val (REGNO (subreg_reg
), REGNO (reg
));
933 /* Pseudos have values -- see comments for lra_reg_info.
934 Different pseudos with the same value do not conflict even if
935 they live in the same place. When we create a pseudo we
936 assign value of original pseudo (if any) from which we
937 created the new pseudo. If we create the pseudo from the
938 input pseudo, the new pseudo will no conflict with the input
939 pseudo which is wrong when the input pseudo lives after the
940 insn and as the new pseudo value is changed by the insn
941 output. Therefore we create the new pseudo from the output.
943 We cannot reuse the current output register because we might
944 have a situation like "a <- a op b", where the constraints
945 force the second input operand ("b") to match the output
946 operand ("a"). "b" must then be copied into a new register
947 so that it doesn't clobber the current value of "a". */
949 new_in_reg
= new_out_reg
950 = lra_create_new_reg_with_unique_value (outmode
, out_rtx
,
953 /* In operand can be got from transformations before processing insn
954 constraints. One example of such transformations is subreg
955 reloading (see function simplify_operand_subreg). The new
956 pseudos created by the transformations might have inaccurate
957 class (ALL_REGS) and we should make their classes more
959 narrow_reload_pseudo_class (in_rtx
, goal_class
);
960 lra_emit_move (copy_rtx (new_in_reg
), in_rtx
);
961 *before
= get_insns ();
963 for (i
= 0; (in
= ins
[i
]) >= 0; i
++)
966 (GET_MODE (*curr_id
->operand_loc
[in
]) == VOIDmode
967 || GET_MODE (new_in_reg
) == GET_MODE (*curr_id
->operand_loc
[in
]));
968 *curr_id
->operand_loc
[in
] = new_in_reg
;
970 lra_update_dups (curr_id
, ins
);
973 /* See a comment for the input operand above. */
974 narrow_reload_pseudo_class (out_rtx
, goal_class
);
975 if (find_reg_note (curr_insn
, REG_UNUSED
, out_rtx
) == NULL_RTX
)
978 lra_emit_move (out_rtx
, copy_rtx (new_out_reg
));
980 *after
= get_insns ();
983 *curr_id
->operand_loc
[out
] = new_out_reg
;
984 lra_update_dup (curr_id
, out
);
987 /* Return register class which is union of all reg classes in insn
988 constraint alternative string starting with P. */
989 static enum reg_class
990 reg_class_from_constraints (const char *p
)
993 enum reg_class op_class
= NO_REGS
;
996 switch ((c
= *p
, len
= CONSTRAINT_LEN (c
, p
)), c
)
1003 op_class
= reg_class_subunion
[op_class
][GENERAL_REGS
];
1007 enum constraint_num cn
= lookup_constraint (p
);
1008 enum reg_class cl
= reg_class_for_constraint (cn
);
1011 if (insn_extra_address_constraint (cn
))
1013 = (reg_class_subunion
1014 [op_class
][base_reg_class (VOIDmode
, ADDR_SPACE_GENERIC
,
1015 ADDRESS
, SCRATCH
)]);
1019 op_class
= reg_class_subunion
[op_class
][cl
];
1022 while ((p
+= len
), c
);
1026 /* If OP is a register, return the class of the register as per
1027 get_reg_class, otherwise return NO_REGS. */
1028 static inline enum reg_class
1029 get_op_class (rtx op
)
1031 return REG_P (op
) ? get_reg_class (REGNO (op
)) : NO_REGS
;
1034 /* Return generated insn mem_pseudo:=val if TO_P or val:=mem_pseudo
1035 otherwise. If modes of MEM_PSEUDO and VAL are different, use
1036 SUBREG for VAL to make them equal. */
1038 emit_spill_move (bool to_p
, rtx mem_pseudo
, rtx val
)
1040 if (GET_MODE (mem_pseudo
) != GET_MODE (val
))
1042 /* Usually size of mem_pseudo is greater than val size but in
1043 rare cases it can be less as it can be defined by target
1044 dependent macro HARD_REGNO_CALLER_SAVE_MODE. */
1047 val
= gen_rtx_SUBREG (GET_MODE (mem_pseudo
),
1048 GET_CODE (val
) == SUBREG
? SUBREG_REG (val
) : val
,
1050 LRA_SUBREG_P (val
) = 1;
1054 mem_pseudo
= gen_lowpart_SUBREG (GET_MODE (val
), mem_pseudo
);
1055 LRA_SUBREG_P (mem_pseudo
) = 1;
1058 return as_a
<rtx_insn
*> (to_p
1059 ? gen_move_insn (mem_pseudo
, val
)
1060 : gen_move_insn (val
, mem_pseudo
));
1063 /* Process a special case insn (register move), return true if we
1064 don't need to process it anymore. INSN should be a single set
1065 insn. Set up that RTL was changed through CHANGE_P and macro
1066 SECONDARY_MEMORY_NEEDED says to use secondary memory through
1069 check_and_process_move (bool *change_p
, bool *sec_mem_p ATTRIBUTE_UNUSED
)
1072 rtx dest
, src
, dreg
, sreg
, old_sreg
, new_reg
, scratch_reg
;
1074 enum reg_class dclass
, sclass
, secondary_class
;
1075 machine_mode sreg_mode
;
1076 secondary_reload_info sri
;
1078 lra_assert (curr_insn_set
!= NULL_RTX
);
1079 dreg
= dest
= SET_DEST (curr_insn_set
);
1080 sreg
= src
= SET_SRC (curr_insn_set
);
1081 if (GET_CODE (dest
) == SUBREG
)
1082 dreg
= SUBREG_REG (dest
);
1083 if (GET_CODE (src
) == SUBREG
)
1084 sreg
= SUBREG_REG (src
);
1085 if (! (REG_P (dreg
) || MEM_P (dreg
)) || ! (REG_P (sreg
) || MEM_P (sreg
)))
1087 sclass
= dclass
= NO_REGS
;
1089 dclass
= get_reg_class (REGNO (dreg
));
1090 if (dclass
== ALL_REGS
)
1091 /* ALL_REGS is used for new pseudos created by transformations
1092 like reload of SUBREG_REG (see function
1093 simplify_operand_subreg). We don't know their class yet. We
1094 should figure out the class from processing the insn
1095 constraints not in this fast path function. Even if ALL_REGS
1096 were a right class for the pseudo, secondary_... hooks usually
1097 are not define for ALL_REGS. */
1099 sreg_mode
= GET_MODE (sreg
);
1102 sclass
= get_reg_class (REGNO (sreg
));
1103 if (sclass
== ALL_REGS
)
1104 /* See comments above. */
1106 if (sclass
== NO_REGS
&& dclass
== NO_REGS
)
1108 #ifdef SECONDARY_MEMORY_NEEDED
1109 if (SECONDARY_MEMORY_NEEDED (sclass
, dclass
, GET_MODE (src
))
1110 #ifdef SECONDARY_MEMORY_NEEDED_MODE
1111 && ((sclass
!= NO_REGS
&& dclass
!= NO_REGS
)
1112 || GET_MODE (src
) != SECONDARY_MEMORY_NEEDED_MODE (GET_MODE (src
)))
1120 if (! REG_P (dreg
) || ! REG_P (sreg
))
1122 sri
.prev_sri
= NULL
;
1123 sri
.icode
= CODE_FOR_nothing
;
1125 secondary_class
= NO_REGS
;
1126 /* Set up hard register for a reload pseudo for hook
1127 secondary_reload because some targets just ignore unassigned
1128 pseudos in the hook. */
1129 if (dclass
!= NO_REGS
&& lra_get_regno_hard_regno (REGNO (dreg
)) < 0)
1131 dregno
= REGNO (dreg
);
1132 reg_renumber
[dregno
] = ira_class_hard_regs
[dclass
][0];
1136 if (sclass
!= NO_REGS
&& lra_get_regno_hard_regno (REGNO (sreg
)) < 0)
1138 sregno
= REGNO (sreg
);
1139 reg_renumber
[sregno
] = ira_class_hard_regs
[sclass
][0];
1143 if (sclass
!= NO_REGS
)
1145 = (enum reg_class
) targetm
.secondary_reload (false, dest
,
1146 (reg_class_t
) sclass
,
1147 GET_MODE (src
), &sri
);
1148 if (sclass
== NO_REGS
1149 || ((secondary_class
!= NO_REGS
|| sri
.icode
!= CODE_FOR_nothing
)
1150 && dclass
!= NO_REGS
))
1152 enum reg_class old_sclass
= secondary_class
;
1153 secondary_reload_info old_sri
= sri
;
1155 sri
.prev_sri
= NULL
;
1156 sri
.icode
= CODE_FOR_nothing
;
1159 = (enum reg_class
) targetm
.secondary_reload (true, sreg
,
1160 (reg_class_t
) dclass
,
1162 /* Check the target hook consistency. */
1164 ((secondary_class
== NO_REGS
&& sri
.icode
== CODE_FOR_nothing
)
1165 || (old_sclass
== NO_REGS
&& old_sri
.icode
== CODE_FOR_nothing
)
1166 || (secondary_class
== old_sclass
&& sri
.icode
== old_sri
.icode
));
1169 reg_renumber
[sregno
] = -1;
1171 reg_renumber
[dregno
] = -1;
1172 if (secondary_class
== NO_REGS
&& sri
.icode
== CODE_FOR_nothing
)
1176 if (secondary_class
!= NO_REGS
)
1177 new_reg
= lra_create_new_reg_with_unique_value (sreg_mode
, NULL_RTX
,
1181 if (old_sreg
!= sreg
)
1182 sreg
= copy_rtx (sreg
);
1183 if (sri
.icode
== CODE_FOR_nothing
)
1184 lra_emit_move (new_reg
, sreg
);
1187 enum reg_class scratch_class
;
1189 scratch_class
= (reg_class_from_constraints
1190 (insn_data
[sri
.icode
].operand
[2].constraint
));
1191 scratch_reg
= (lra_create_new_reg_with_unique_value
1192 (insn_data
[sri
.icode
].operand
[2].mode
, NULL_RTX
,
1193 scratch_class
, "scratch"));
1194 emit_insn (GEN_FCN (sri
.icode
) (new_reg
!= NULL_RTX
? new_reg
: dest
,
1195 sreg
, scratch_reg
));
1197 before
= get_insns ();
1199 lra_process_new_insns (curr_insn
, before
, NULL
, "Inserting the move");
1200 if (new_reg
!= NULL_RTX
)
1202 if (GET_CODE (src
) == SUBREG
)
1203 SUBREG_REG (src
) = new_reg
;
1205 SET_SRC (curr_insn_set
) = new_reg
;
1209 if (lra_dump_file
!= NULL
)
1211 fprintf (lra_dump_file
, "Deleting move %u\n", INSN_UID (curr_insn
));
1212 dump_insn_slim (lra_dump_file
, curr_insn
);
1214 lra_set_insn_deleted (curr_insn
);
1220 /* The following data describe the result of process_alt_operands.
1221 The data are used in curr_insn_transform to generate reloads. */
1223 /* The chosen reg classes which should be used for the corresponding
1225 static enum reg_class goal_alt
[MAX_RECOG_OPERANDS
];
1226 /* True if the operand should be the same as another operand and that
1227 other operand does not need a reload. */
1228 static bool goal_alt_match_win
[MAX_RECOG_OPERANDS
];
1229 /* True if the operand does not need a reload. */
1230 static bool goal_alt_win
[MAX_RECOG_OPERANDS
];
1231 /* True if the operand can be offsetable memory. */
1232 static bool goal_alt_offmemok
[MAX_RECOG_OPERANDS
];
1233 /* The number of an operand to which given operand can be matched to. */
1234 static int goal_alt_matches
[MAX_RECOG_OPERANDS
];
1235 /* The number of elements in the following array. */
1236 static int goal_alt_dont_inherit_ops_num
;
1237 /* Numbers of operands whose reload pseudos should not be inherited. */
1238 static int goal_alt_dont_inherit_ops
[MAX_RECOG_OPERANDS
];
1239 /* True if the insn commutative operands should be swapped. */
1240 static bool goal_alt_swapped
;
1241 /* The chosen insn alternative. */
1242 static int goal_alt_number
;
1244 /* The following five variables are used to choose the best insn
1245 alternative. They reflect final characteristics of the best
1248 /* Number of necessary reloads and overall cost reflecting the
1249 previous value and other unpleasantness of the best alternative. */
1250 static int best_losers
, best_overall
;
1251 /* Overall number hard registers used for reloads. For example, on
1252 some targets we need 2 general registers to reload DFmode and only
1253 one floating point register. */
1254 static int best_reload_nregs
;
1255 /* Overall number reflecting distances of previous reloading the same
1256 value. The distances are counted from the current BB start. It is
1257 used to improve inheritance chances. */
1258 static int best_reload_sum
;
1260 /* True if the current insn should have no correspondingly input or
1262 static bool no_input_reloads_p
, no_output_reloads_p
;
1264 /* True if we swapped the commutative operands in the current
1266 static int curr_swapped
;
1268 /* if CHECK_ONLY_P is false, arrange for address element *LOC to be a
1269 register of class CL. Add any input reloads to list BEFORE. AFTER
1270 is nonnull if *LOC is an automodified value; handle that case by
1271 adding the required output reloads to list AFTER. Return true if
1272 the RTL was changed.
1274 if CHECK_ONLY_P is true, check that the *LOC is a correct address
1275 register. Return false if the address register is correct. */
1277 process_addr_reg (rtx
*loc
, bool check_only_p
, rtx_insn
**before
, rtx_insn
**after
,
1281 enum reg_class rclass
, new_class
;
1285 bool subreg_p
, before_p
= false;
1287 subreg_p
= GET_CODE (*loc
) == SUBREG
;
1289 loc
= &SUBREG_REG (*loc
);
1291 mode
= GET_MODE (reg
);
1296 /* Always reload memory in an address even if the target supports
1298 new_reg
= lra_create_new_reg_with_unique_value (mode
, reg
, cl
, "address");
1303 regno
= REGNO (reg
);
1304 rclass
= get_reg_class (regno
);
1306 && (*loc
= get_equiv_with_elimination (reg
, curr_insn
)) != reg
)
1308 if (lra_dump_file
!= NULL
)
1310 fprintf (lra_dump_file
,
1311 "Changing pseudo %d in address of insn %u on equiv ",
1312 REGNO (reg
), INSN_UID (curr_insn
));
1313 dump_value_slim (lra_dump_file
, *loc
, 1);
1314 fprintf (lra_dump_file
, "\n");
1316 *loc
= copy_rtx (*loc
);
1318 if (*loc
!= reg
|| ! in_class_p (reg
, cl
, &new_class
))
1323 if (get_reload_reg (after
== NULL
? OP_IN
: OP_INOUT
,
1324 mode
, reg
, cl
, subreg_p
, "address", &new_reg
))
1327 else if (new_class
!= NO_REGS
&& rclass
!= new_class
)
1331 lra_change_class (regno
, new_class
, " Change to", true);
1339 push_to_sequence (*before
);
1340 lra_emit_move (new_reg
, reg
);
1341 *before
= get_insns ();
1348 lra_emit_move (reg
, new_reg
);
1350 *after
= get_insns ();
1356 /* Insert move insn in simplify_operand_subreg. BEFORE returns
1357 the insn to be inserted before curr insn. AFTER returns the
1358 the insn to be inserted after curr insn. ORIGREG and NEWREG
1359 are the original reg and new reg for reload. */
1361 insert_move_for_subreg (rtx_insn
**before
, rtx_insn
**after
, rtx origreg
,
1366 push_to_sequence (*before
);
1367 lra_emit_move (newreg
, origreg
);
1368 *before
= get_insns ();
1374 lra_emit_move (origreg
, newreg
);
1376 *after
= get_insns ();
1381 static int valid_address_p (machine_mode mode
, rtx addr
, addr_space_t as
);
1383 /* Make reloads for subreg in operand NOP with internal subreg mode
1384 REG_MODE, add new reloads for further processing. Return true if
1385 any reload was generated. */
1387 simplify_operand_subreg (int nop
, machine_mode reg_mode
)
1390 rtx_insn
*before
, *after
;
1393 rtx operand
= *curr_id
->operand_loc
[nop
];
1394 enum reg_class regclass
;
1397 before
= after
= NULL
;
1399 if (GET_CODE (operand
) != SUBREG
)
1402 mode
= GET_MODE (operand
);
1403 reg
= SUBREG_REG (operand
);
1404 type
= curr_static_id
->operand
[nop
].type
;
1405 /* If we change address for paradoxical subreg of memory, the
1406 address might violate the necessary alignment or the access might
1407 be slow. So take this into consideration. We should not worry
1408 about access beyond allocated memory for paradoxical memory
1409 subregs as we don't substitute such equiv memory (see processing
1410 equivalences in function lra_constraints) and because for spilled
1411 pseudos we allocate stack memory enough for the biggest
1412 corresponding paradoxical subreg. */
1414 && (! SLOW_UNALIGNED_ACCESS (mode
, MEM_ALIGN (reg
))
1415 || MEM_ALIGN (reg
) >= GET_MODE_ALIGNMENT (mode
)))
1417 rtx subst
, old
= *curr_id
->operand_loc
[nop
];
1419 alter_subreg (curr_id
->operand_loc
[nop
], false);
1420 subst
= *curr_id
->operand_loc
[nop
];
1421 lra_assert (MEM_P (subst
));
1422 if (! valid_address_p (GET_MODE (reg
), XEXP (reg
, 0),
1423 MEM_ADDR_SPACE (reg
))
1424 || valid_address_p (GET_MODE (subst
), XEXP (subst
, 0),
1425 MEM_ADDR_SPACE (subst
)))
1427 /* If the address was valid and became invalid, prefer to reload
1428 the memory. Typical case is when the index scale should
1429 correspond the memory. */
1430 *curr_id
->operand_loc
[nop
] = old
;
1432 else if (REG_P (reg
) && REGNO (reg
) < FIRST_PSEUDO_REGISTER
)
1434 alter_subreg (curr_id
->operand_loc
[nop
], false);
1437 /* Put constant into memory when we have mixed modes. It generates
1438 a better code in most cases as it does not need a secondary
1439 reload memory. It also prevents LRA looping when LRA is using
1440 secondary reload memory again and again. */
1441 if (CONSTANT_P (reg
) && CONST_POOL_OK_P (reg_mode
, reg
)
1442 && SCALAR_INT_MODE_P (reg_mode
) != SCALAR_INT_MODE_P (mode
))
1444 SUBREG_REG (operand
) = force_const_mem (reg_mode
, reg
);
1445 alter_subreg (curr_id
->operand_loc
[nop
], false);
1448 /* Force a reload of the SUBREG_REG if this is a constant or PLUS or
1449 if there may be a problem accessing OPERAND in the outer
1452 && REGNO (reg
) >= FIRST_PSEUDO_REGISTER
1453 && (hard_regno
= lra_get_regno_hard_regno (REGNO (reg
))) >= 0
1454 /* Don't reload paradoxical subregs because we could be looping
1455 having repeatedly final regno out of hard regs range. */
1456 && (hard_regno_nregs
[hard_regno
][GET_MODE (reg
)]
1457 >= hard_regno_nregs
[hard_regno
][mode
])
1458 && simplify_subreg_regno (hard_regno
, GET_MODE (reg
),
1459 SUBREG_BYTE (operand
), mode
) < 0
1460 /* Don't reload subreg for matching reload. It is actually
1461 valid subreg in LRA. */
1462 && ! LRA_SUBREG_P (operand
))
1463 || CONSTANT_P (reg
) || GET_CODE (reg
) == PLUS
|| MEM_P (reg
))
1465 enum reg_class rclass
;
1468 /* There is a big probability that we will get the same class
1469 for the new pseudo and we will get the same insn which
1470 means infinite looping. So spill the new pseudo. */
1473 /* The class will be defined later in curr_insn_transform. */
1475 = (enum reg_class
) targetm
.preferred_reload_class (reg
, ALL_REGS
);
1477 if (get_reload_reg (curr_static_id
->operand
[nop
].type
, reg_mode
, reg
,
1478 rclass
, TRUE
, "subreg reg", &new_reg
))
1480 bool insert_before
, insert_after
;
1481 bitmap_set_bit (&lra_subreg_reload_pseudos
, REGNO (new_reg
));
1483 insert_before
= (type
!= OP_OUT
1484 || GET_MODE_SIZE (GET_MODE (reg
)) > GET_MODE_SIZE (mode
));
1485 insert_after
= (type
!= OP_IN
);
1486 insert_move_for_subreg (insert_before
? &before
: NULL
,
1487 insert_after
? &after
: NULL
,
1490 SUBREG_REG (operand
) = new_reg
;
1491 lra_process_new_insns (curr_insn
, before
, after
,
1492 "Inserting subreg reload");
1495 /* Force a reload for a paradoxical subreg. For paradoxical subreg,
1496 IRA allocates hardreg to the inner pseudo reg according to its mode
1497 instead of the outermode, so the size of the hardreg may not be enough
1498 to contain the outermode operand, in that case we may need to insert
1499 reload for the reg. For the following two types of paradoxical subreg,
1500 we need to insert reload:
1501 1. If the op_type is OP_IN, and the hardreg could not be paired with
1502 other hardreg to contain the outermode operand
1503 (checked by in_hard_reg_set_p), we need to insert the reload.
1504 2. If the op_type is OP_OUT or OP_INOUT.
1506 Here is a paradoxical subreg example showing how the reload is generated:
1508 (insn 5 4 7 2 (set (reg:TI 106 [ __comp ])
1509 (subreg:TI (reg:DI 107 [ __comp ]) 0)) {*movti_internal_rex64}
1511 In IRA, reg107 is allocated to a DImode hardreg. We use x86-64 as example
1512 here, if reg107 is assigned to hardreg R15, because R15 is the last
1513 hardreg, compiler cannot find another hardreg to pair with R15 to
1514 contain TImode data. So we insert a TImode reload reg180 for it.
1515 After reload is inserted:
1517 (insn 283 0 0 (set (subreg:DI (reg:TI 180 [orig:107 __comp ] [107]) 0)
1518 (reg:DI 107 [ __comp ])) -1
1519 (insn 5 4 7 2 (set (reg:TI 106 [ __comp ])
1520 (subreg:TI (reg:TI 180 [orig:107 __comp ] [107]) 0)) {*movti_internal_rex64}
1522 Two reload hard registers will be allocated to reg180 to save TImode data
1524 else if (REG_P (reg
)
1525 && REGNO (reg
) >= FIRST_PSEUDO_REGISTER
1526 && (hard_regno
= lra_get_regno_hard_regno (REGNO (reg
))) >= 0
1527 && (hard_regno_nregs
[hard_regno
][GET_MODE (reg
)]
1528 < hard_regno_nregs
[hard_regno
][mode
])
1529 && (regclass
= lra_get_allocno_class (REGNO (reg
)))
1531 || !in_hard_reg_set_p (reg_class_contents
[regclass
],
1534 /* The class will be defined later in curr_insn_transform. */
1535 enum reg_class rclass
1536 = (enum reg_class
) targetm
.preferred_reload_class (reg
, ALL_REGS
);
1538 if (get_reload_reg (curr_static_id
->operand
[nop
].type
, mode
, reg
,
1539 rclass
, TRUE
, "paradoxical subreg", &new_reg
))
1542 bool insert_before
, insert_after
;
1544 PUT_MODE (new_reg
, mode
);
1545 subreg
= simplify_gen_subreg (GET_MODE (reg
), new_reg
, mode
, 0);
1546 bitmap_set_bit (&lra_subreg_reload_pseudos
, REGNO (new_reg
));
1548 insert_before
= (type
!= OP_OUT
);
1549 insert_after
= (type
!= OP_IN
);
1550 insert_move_for_subreg (insert_before
? &before
: NULL
,
1551 insert_after
? &after
: NULL
,
1554 SUBREG_REG (operand
) = new_reg
;
1555 lra_process_new_insns (curr_insn
, before
, after
,
1556 "Inserting paradoxical subreg reload");
1562 /* Return TRUE if X refers for a hard register from SET. */
1564 uses_hard_regs_p (rtx x
, HARD_REG_SET set
)
1566 int i
, j
, x_hard_regno
;
1573 code
= GET_CODE (x
);
1574 mode
= GET_MODE (x
);
1578 code
= GET_CODE (x
);
1579 if (GET_MODE_SIZE (GET_MODE (x
)) > GET_MODE_SIZE (mode
))
1580 mode
= GET_MODE (x
);
1585 x_hard_regno
= get_hard_regno (x
);
1586 return (x_hard_regno
>= 0
1587 && overlaps_hard_reg_set_p (set
, mode
, x_hard_regno
));
1591 struct address_info ad
;
1593 decompose_mem_address (&ad
, x
);
1594 if (ad
.base_term
!= NULL
&& uses_hard_regs_p (*ad
.base_term
, set
))
1596 if (ad
.index_term
!= NULL
&& uses_hard_regs_p (*ad
.index_term
, set
))
1599 fmt
= GET_RTX_FORMAT (code
);
1600 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
1604 if (uses_hard_regs_p (XEXP (x
, i
), set
))
1607 else if (fmt
[i
] == 'E')
1609 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
1610 if (uses_hard_regs_p (XVECEXP (x
, i
, j
), set
))
1617 /* Return true if OP is a spilled pseudo. */
1619 spilled_pseudo_p (rtx op
)
1622 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
&& in_mem_p (REGNO (op
)));
1625 /* Return true if X is a general constant. */
1627 general_constant_p (rtx x
)
1629 return CONSTANT_P (x
) && (! flag_pic
|| LEGITIMATE_PIC_OPERAND_P (x
));
1633 reg_in_class_p (rtx reg
, enum reg_class cl
)
1636 return get_reg_class (REGNO (reg
)) == NO_REGS
;
1637 return in_class_p (reg
, cl
, NULL
);
1640 /* Major function to choose the current insn alternative and what
1641 operands should be reloaded and how. If ONLY_ALTERNATIVE is not
1642 negative we should consider only this alternative. Return false if
1643 we can not choose the alternative or find how to reload the
1646 process_alt_operands (int only_alternative
)
1649 int nop
, overall
, nalt
;
1650 int n_alternatives
= curr_static_id
->n_alternatives
;
1651 int n_operands
= curr_static_id
->n_operands
;
1652 /* LOSERS counts the operands that don't fit this alternative and
1653 would require loading. */
1655 /* REJECT is a count of how undesirable this alternative says it is
1656 if any reloading is required. If the alternative matches exactly
1657 then REJECT is ignored, but otherwise it gets this much counted
1658 against it in addition to the reloading needed. */
1661 /* The number of elements in the following array. */
1662 int early_clobbered_regs_num
;
1663 /* Numbers of operands which are early clobber registers. */
1664 int early_clobbered_nops
[MAX_RECOG_OPERANDS
];
1665 enum reg_class curr_alt
[MAX_RECOG_OPERANDS
];
1666 HARD_REG_SET curr_alt_set
[MAX_RECOG_OPERANDS
];
1667 bool curr_alt_match_win
[MAX_RECOG_OPERANDS
];
1668 bool curr_alt_win
[MAX_RECOG_OPERANDS
];
1669 bool curr_alt_offmemok
[MAX_RECOG_OPERANDS
];
1670 int curr_alt_matches
[MAX_RECOG_OPERANDS
];
1671 /* The number of elements in the following array. */
1672 int curr_alt_dont_inherit_ops_num
;
1673 /* Numbers of operands whose reload pseudos should not be inherited. */
1674 int curr_alt_dont_inherit_ops
[MAX_RECOG_OPERANDS
];
1676 /* The register when the operand is a subreg of register, otherwise the
1678 rtx no_subreg_reg_operand
[MAX_RECOG_OPERANDS
];
1679 /* The register if the operand is a register or subreg of register,
1681 rtx operand_reg
[MAX_RECOG_OPERANDS
];
1682 int hard_regno
[MAX_RECOG_OPERANDS
];
1683 machine_mode biggest_mode
[MAX_RECOG_OPERANDS
];
1684 int reload_nregs
, reload_sum
;
1688 /* Calculate some data common for all alternatives to speed up the
1690 for (nop
= 0; nop
< n_operands
; nop
++)
1694 op
= no_subreg_reg_operand
[nop
] = *curr_id
->operand_loc
[nop
];
1695 /* The real hard regno of the operand after the allocation. */
1696 hard_regno
[nop
] = get_hard_regno (op
);
1698 operand_reg
[nop
] = reg
= op
;
1699 biggest_mode
[nop
] = GET_MODE (op
);
1700 if (GET_CODE (op
) == SUBREG
)
1702 operand_reg
[nop
] = reg
= SUBREG_REG (op
);
1703 if (GET_MODE_SIZE (biggest_mode
[nop
])
1704 < GET_MODE_SIZE (GET_MODE (reg
)))
1705 biggest_mode
[nop
] = GET_MODE (reg
);
1708 operand_reg
[nop
] = NULL_RTX
;
1709 else if (REGNO (reg
) >= FIRST_PSEUDO_REGISTER
1710 || ((int) REGNO (reg
)
1711 == lra_get_elimination_hard_regno (REGNO (reg
))))
1712 no_subreg_reg_operand
[nop
] = reg
;
1714 operand_reg
[nop
] = no_subreg_reg_operand
[nop
]
1715 /* Just use natural mode for elimination result. It should
1716 be enough for extra constraints hooks. */
1717 = regno_reg_rtx
[hard_regno
[nop
]];
1720 /* The constraints are made of several alternatives. Each operand's
1721 constraint looks like foo,bar,... with commas separating the
1722 alternatives. The first alternatives for all operands go
1723 together, the second alternatives go together, etc.
1725 First loop over alternatives. */
1726 alternative_mask preferred
= curr_id
->preferred_alternatives
;
1727 if (only_alternative
>= 0)
1728 preferred
&= ALTERNATIVE_BIT (only_alternative
);
1730 for (nalt
= 0; nalt
< n_alternatives
; nalt
++)
1732 /* Loop over operands for one constraint alternative. */
1733 if (!TEST_BIT (preferred
, nalt
))
1736 overall
= losers
= reject
= reload_nregs
= reload_sum
= 0;
1737 for (nop
= 0; nop
< n_operands
; nop
++)
1739 int inc
= (curr_static_id
1740 ->operand_alternative
[nalt
* n_operands
+ nop
].reject
);
1741 if (lra_dump_file
!= NULL
&& inc
!= 0)
1742 fprintf (lra_dump_file
,
1743 " Staticly defined alt reject+=%d\n", inc
);
1746 early_clobbered_regs_num
= 0;
1748 for (nop
= 0; nop
< n_operands
; nop
++)
1752 int len
, c
, m
, i
, opalt_num
, this_alternative_matches
;
1753 bool win
, did_match
, offmemok
, early_clobber_p
;
1754 /* false => this operand can be reloaded somehow for this
1757 /* true => this operand can be reloaded if the alternative
1760 /* True if a constant forced into memory would be OK for
1763 enum reg_class this_alternative
, this_costly_alternative
;
1764 HARD_REG_SET this_alternative_set
, this_costly_alternative_set
;
1765 bool this_alternative_match_win
, this_alternative_win
;
1766 bool this_alternative_offmemok
;
1769 enum constraint_num cn
;
1771 opalt_num
= nalt
* n_operands
+ nop
;
1772 if (curr_static_id
->operand_alternative
[opalt_num
].anything_ok
)
1774 /* Fast track for no constraints at all. */
1775 curr_alt
[nop
] = NO_REGS
;
1776 CLEAR_HARD_REG_SET (curr_alt_set
[nop
]);
1777 curr_alt_win
[nop
] = true;
1778 curr_alt_match_win
[nop
] = false;
1779 curr_alt_offmemok
[nop
] = false;
1780 curr_alt_matches
[nop
] = -1;
1784 op
= no_subreg_reg_operand
[nop
];
1785 mode
= curr_operand_mode
[nop
];
1787 win
= did_match
= winreg
= offmemok
= constmemok
= false;
1790 early_clobber_p
= false;
1791 p
= curr_static_id
->operand_alternative
[opalt_num
].constraint
;
1793 this_costly_alternative
= this_alternative
= NO_REGS
;
1794 /* We update set of possible hard regs besides its class
1795 because reg class might be inaccurate. For example,
1796 union of LO_REGS (l), HI_REGS(h), and STACK_REG(k) in ARM
1797 is translated in HI_REGS because classes are merged by
1798 pairs and there is no accurate intermediate class. */
1799 CLEAR_HARD_REG_SET (this_alternative_set
);
1800 CLEAR_HARD_REG_SET (this_costly_alternative_set
);
1801 this_alternative_win
= false;
1802 this_alternative_match_win
= false;
1803 this_alternative_offmemok
= false;
1804 this_alternative_matches
= -1;
1806 /* An empty constraint should be excluded by the fast
1808 lra_assert (*p
!= 0 && *p
!= ',');
1811 /* Scan this alternative's specs for this operand; set WIN
1812 if the operand fits any letter in this alternative.
1813 Otherwise, clear BADOP if this operand could fit some
1814 letter after reloads, or set WINREG if this operand could
1815 fit after reloads provided the constraint allows some
1820 switch ((c
= *p
, len
= CONSTRAINT_LEN (c
, p
)), c
)
1830 early_clobber_p
= true;
1834 op_reject
+= LRA_MAX_REJECT
;
1837 op_reject
+= LRA_LOSER_COST_FACTOR
;
1841 /* Ignore rest of this alternative. */
1845 case '0': case '1': case '2': case '3': case '4':
1846 case '5': case '6': case '7': case '8': case '9':
1851 m
= strtoul (p
, &end
, 10);
1854 lra_assert (nop
> m
);
1856 this_alternative_matches
= m
;
1857 m_hregno
= get_hard_regno (*curr_id
->operand_loc
[m
]);
1858 /* We are supposed to match a previous operand.
1859 If we do, we win if that one did. If we do
1860 not, count both of the operands as losers.
1861 (This is too conservative, since most of the
1862 time only a single reload insn will be needed
1863 to make the two operands win. As a result,
1864 this alternative may be rejected when it is
1865 actually desirable.) */
1867 if (operands_match_p (*curr_id
->operand_loc
[nop
],
1868 *curr_id
->operand_loc
[m
], m_hregno
))
1870 /* We should reject matching of an early
1871 clobber operand if the matching operand is
1872 not dying in the insn. */
1873 if (! curr_static_id
->operand
[m
].early_clobber
1874 || operand_reg
[nop
] == NULL_RTX
1875 || (find_regno_note (curr_insn
, REG_DEAD
,
1877 || REGNO (op
) == REGNO (operand_reg
[m
])))
1882 /* If we are matching a non-offsettable
1883 address where an offsettable address was
1884 expected, then we must reject this
1885 combination, because we can't reload
1887 if (curr_alt_offmemok
[m
]
1888 && MEM_P (*curr_id
->operand_loc
[m
])
1889 && curr_alt
[m
] == NO_REGS
&& ! curr_alt_win
[m
])
1894 /* Operands don't match. Both operands must
1895 allow a reload register, otherwise we
1896 cannot make them match. */
1897 if (curr_alt
[m
] == NO_REGS
)
1899 /* Retroactively mark the operand we had to
1900 match as a loser, if it wasn't already and
1901 it wasn't matched to a register constraint
1902 (e.g it might be matched by memory). */
1904 && (operand_reg
[m
] == NULL_RTX
1905 || hard_regno
[m
] < 0))
1909 += (ira_reg_class_max_nregs
[curr_alt
[m
]]
1910 [GET_MODE (*curr_id
->operand_loc
[m
])]);
1913 /* Prefer matching earlyclobber alternative as
1914 it results in less hard regs required for
1915 the insn than a non-matching earlyclobber
1917 if (curr_static_id
->operand
[m
].early_clobber
)
1919 if (lra_dump_file
!= NULL
)
1922 " %d Matching earlyclobber alt:"
1927 /* Otherwise we prefer no matching
1928 alternatives because it gives more freedom
1930 else if (operand_reg
[nop
] == NULL_RTX
1931 || (find_regno_note (curr_insn
, REG_DEAD
,
1932 REGNO (operand_reg
[nop
]))
1935 if (lra_dump_file
!= NULL
)
1938 " %d Matching alt: reject+=2\n",
1943 /* If we have to reload this operand and some
1944 previous operand also had to match the same
1945 thing as this operand, we don't know how to do
1947 if (!match_p
|| !curr_alt_win
[m
])
1949 for (i
= 0; i
< nop
; i
++)
1950 if (curr_alt_matches
[i
] == m
)
1958 /* This can be fixed with reloads if the operand
1959 we are supposed to match can be fixed with
1962 this_alternative
= curr_alt
[m
];
1963 COPY_HARD_REG_SET (this_alternative_set
, curr_alt_set
[m
]);
1964 winreg
= this_alternative
!= NO_REGS
;
1970 || general_constant_p (op
)
1971 || spilled_pseudo_p (op
))
1977 cn
= lookup_constraint (p
);
1978 switch (get_constraint_type (cn
))
1981 cl
= reg_class_for_constraint (cn
);
1987 if (CONST_INT_P (op
)
1988 && insn_const_int_ok_for_constraint (INTVAL (op
), cn
))
1994 && satisfies_memory_constraint_p (op
, cn
))
1996 else if (spilled_pseudo_p (op
))
1999 /* If we didn't already win, we can reload constants
2000 via force_const_mem or put the pseudo value into
2001 memory, or make other memory by reloading the
2002 address like for 'o'. */
2003 if (CONST_POOL_OK_P (mode
, op
)
2004 || MEM_P (op
) || REG_P (op
))
2011 /* If we didn't already win, we can reload the address
2012 into a base register. */
2013 if (satisfies_address_constraint_p (op
, cn
))
2015 cl
= base_reg_class (VOIDmode
, ADDR_SPACE_GENERIC
,
2021 if (constraint_satisfied_p (op
, cn
))
2028 this_alternative
= reg_class_subunion
[this_alternative
][cl
];
2029 IOR_HARD_REG_SET (this_alternative_set
,
2030 reg_class_contents
[cl
]);
2033 this_costly_alternative
2034 = reg_class_subunion
[this_costly_alternative
][cl
];
2035 IOR_HARD_REG_SET (this_costly_alternative_set
,
2036 reg_class_contents
[cl
]);
2038 if (mode
== BLKmode
)
2043 if (hard_regno
[nop
] >= 0
2044 && in_hard_reg_set_p (this_alternative_set
,
2045 mode
, hard_regno
[nop
]))
2047 else if (hard_regno
[nop
] < 0
2048 && in_class_p (op
, this_alternative
, NULL
))
2053 if (c
!= ' ' && c
!= '\t')
2054 costly_p
= c
== '*';
2056 while ((p
+= len
), c
);
2058 scratch_p
= (operand_reg
[nop
] != NULL_RTX
2059 && lra_former_scratch_p (REGNO (operand_reg
[nop
])));
2060 /* Record which operands fit this alternative. */
2063 this_alternative_win
= true;
2064 if (operand_reg
[nop
] != NULL_RTX
)
2066 if (hard_regno
[nop
] >= 0)
2068 if (in_hard_reg_set_p (this_costly_alternative_set
,
2069 mode
, hard_regno
[nop
]))
2071 if (lra_dump_file
!= NULL
)
2072 fprintf (lra_dump_file
,
2073 " %d Costly set: reject++\n",
2080 /* Prefer won reg to spilled pseudo under other
2081 equal conditions for possibe inheritance. */
2084 if (lra_dump_file
!= NULL
)
2087 " %d Non pseudo reload: reject++\n",
2091 if (in_class_p (operand_reg
[nop
],
2092 this_costly_alternative
, NULL
))
2094 if (lra_dump_file
!= NULL
)
2097 " %d Non pseudo costly reload:"
2103 /* We simulate the behaviour of old reload here.
2104 Although scratches need hard registers and it
2105 might result in spilling other pseudos, no reload
2106 insns are generated for the scratches. So it
2107 might cost something but probably less than old
2108 reload pass believes. */
2111 if (lra_dump_file
!= NULL
)
2112 fprintf (lra_dump_file
,
2113 " %d Scratch win: reject+=2\n",
2120 this_alternative_match_win
= true;
2123 int const_to_mem
= 0;
2126 reject
+= op_reject
;
2127 /* Never do output reload of stack pointer. It makes
2128 impossible to do elimination when SP is changed in
2130 if (op
== stack_pointer_rtx
&& ! frame_pointer_needed
2131 && curr_static_id
->operand
[nop
].type
!= OP_IN
)
2134 /* If this alternative asks for a specific reg class, see if there
2135 is at least one allocatable register in that class. */
2137 = (this_alternative
== NO_REGS
2138 || (hard_reg_set_subset_p
2139 (reg_class_contents
[this_alternative
],
2140 lra_no_alloc_regs
)));
2142 /* For asms, verify that the class for this alternative is possible
2143 for the mode that is specified. */
2144 if (!no_regs_p
&& INSN_CODE (curr_insn
) < 0)
2147 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
2148 if (HARD_REGNO_MODE_OK (i
, mode
)
2149 && in_hard_reg_set_p (reg_class_contents
[this_alternative
],
2152 if (i
== FIRST_PSEUDO_REGISTER
)
2156 /* If this operand accepts a register, and if the
2157 register class has at least one allocatable register,
2158 then this operand can be reloaded. */
2159 if (winreg
&& !no_regs_p
)
2164 if (lra_dump_file
!= NULL
)
2165 fprintf (lra_dump_file
,
2166 " alt=%d: Bad operand -- refuse\n",
2171 /* If not assigned pseudo has a class which a subset of
2172 required reg class, it is a less costly alternative
2173 as the pseudo still can get a hard reg of necessary
2175 if (! no_regs_p
&& REG_P (op
) && hard_regno
[nop
] < 0
2176 && (cl
= get_reg_class (REGNO (op
))) != NO_REGS
2177 && ira_class_subset_p
[this_alternative
][cl
])
2179 if (lra_dump_file
!= NULL
)
2182 " %d Super set class reg: reject-=3\n", nop
);
2186 this_alternative_offmemok
= offmemok
;
2187 if (this_costly_alternative
!= NO_REGS
)
2189 if (lra_dump_file
!= NULL
)
2190 fprintf (lra_dump_file
,
2191 " %d Costly loser: reject++\n", nop
);
2194 /* If the operand is dying, has a matching constraint,
2195 and satisfies constraints of the matched operand
2196 which failed to satisfy the own constraints, most probably
2197 the reload for this operand will be gone. */
2198 if (this_alternative_matches
>= 0
2199 && !curr_alt_win
[this_alternative_matches
]
2201 && find_regno_note (curr_insn
, REG_DEAD
, REGNO (op
))
2202 && (hard_regno
[nop
] >= 0
2203 ? in_hard_reg_set_p (this_alternative_set
,
2204 mode
, hard_regno
[nop
])
2205 : in_class_p (op
, this_alternative
, NULL
)))
2207 if (lra_dump_file
!= NULL
)
2210 " %d Dying matched operand reload: reject++\n",
2216 /* Strict_low_part requires to reload the register
2217 not the sub-register. In this case we should
2218 check that a final reload hard reg can hold the
2220 if (curr_static_id
->operand
[nop
].strict_low
2222 && hard_regno
[nop
] < 0
2223 && GET_CODE (*curr_id
->operand_loc
[nop
]) == SUBREG
2224 && ira_class_hard_regs_num
[this_alternative
] > 0
2225 && ! HARD_REGNO_MODE_OK (ira_class_hard_regs
2226 [this_alternative
][0],
2228 (*curr_id
->operand_loc
[nop
])))
2230 if (lra_dump_file
!= NULL
)
2233 " alt=%d: Strict low subreg reload -- refuse\n",
2239 if (operand_reg
[nop
] != NULL_RTX
2240 /* Output operands and matched input operands are
2241 not inherited. The following conditions do not
2242 exactly describe the previous statement but they
2243 are pretty close. */
2244 && curr_static_id
->operand
[nop
].type
!= OP_OUT
2245 && (this_alternative_matches
< 0
2246 || curr_static_id
->operand
[nop
].type
!= OP_IN
))
2248 int last_reload
= (lra_reg_info
[ORIGINAL_REGNO
2252 /* The value of reload_sum has sense only if we
2253 process insns in their order. It happens only on
2254 the first constraints sub-pass when we do most of
2256 if (lra_constraint_iter
== 1 && last_reload
> bb_reload_num
)
2257 reload_sum
+= last_reload
- bb_reload_num
;
2259 /* If this is a constant that is reloaded into the
2260 desired class by copying it to memory first, count
2261 that as another reload. This is consistent with
2262 other code and is required to avoid choosing another
2263 alternative when the constant is moved into memory.
2264 Note that the test here is precisely the same as in
2265 the code below that calls force_const_mem. */
2266 if (CONST_POOL_OK_P (mode
, op
)
2267 && ((targetm
.preferred_reload_class
2268 (op
, this_alternative
) == NO_REGS
)
2269 || no_input_reloads_p
))
2276 /* Alternative loses if it requires a type of reload not
2277 permitted for this insn. We can always reload
2278 objects with a REG_UNUSED note. */
2279 if ((curr_static_id
->operand
[nop
].type
!= OP_IN
2280 && no_output_reloads_p
2281 && ! find_reg_note (curr_insn
, REG_UNUSED
, op
))
2282 || (curr_static_id
->operand
[nop
].type
!= OP_OUT
2283 && no_input_reloads_p
&& ! const_to_mem
)
2284 || (this_alternative_matches
>= 0
2285 && (no_input_reloads_p
2286 || (no_output_reloads_p
2287 && (curr_static_id
->operand
2288 [this_alternative_matches
].type
!= OP_IN
)
2289 && ! find_reg_note (curr_insn
, REG_UNUSED
,
2290 no_subreg_reg_operand
2291 [this_alternative_matches
])))))
2293 if (lra_dump_file
!= NULL
)
2296 " alt=%d: No input/otput reload -- refuse\n",
2301 /* Alternative loses if it required class pseudo can not
2302 hold value of required mode. Such insns can be
2303 described by insn definitions with mode iterators. */
2304 if (GET_MODE (*curr_id
->operand_loc
[nop
]) != VOIDmode
2305 && ! hard_reg_set_empty_p (this_alternative_set
)
2306 /* It is common practice for constraints to use a
2307 class which does not have actually enough regs to
2308 hold the value (e.g. x86 AREG for mode requiring
2309 more one general reg). Therefore we have 2
2310 conditions to check that the reload pseudo can
2311 not hold the mode value. */
2312 && ! HARD_REGNO_MODE_OK (ira_class_hard_regs
2313 [this_alternative
][0],
2314 GET_MODE (*curr_id
->operand_loc
[nop
])))
2318 COPY_HARD_REG_SET (temp
, this_alternative_set
);
2319 AND_COMPL_HARD_REG_SET (temp
, lra_no_alloc_regs
);
2320 /* The above condition is not enough as the first
2321 reg in ira_class_hard_regs can be not aligned for
2322 multi-words mode values. */
2323 if (hard_reg_set_subset_p (temp
,
2324 ira_prohibited_class_mode_regs
2326 [GET_MODE (*curr_id
->operand_loc
[nop
])]))
2328 if (lra_dump_file
!= NULL
)
2331 " alt=%d: reload pseudo for op %d "
2332 " can not hold the mode value -- refuse\n",
2338 /* Check strong discouragement of reload of non-constant
2339 into class THIS_ALTERNATIVE. */
2340 if (! CONSTANT_P (op
) && ! no_regs_p
2341 && (targetm
.preferred_reload_class
2342 (op
, this_alternative
) == NO_REGS
2343 || (curr_static_id
->operand
[nop
].type
== OP_OUT
2344 && (targetm
.preferred_output_reload_class
2345 (op
, this_alternative
) == NO_REGS
))))
2347 if (lra_dump_file
!= NULL
)
2348 fprintf (lra_dump_file
,
2349 " %d Non-prefered reload: reject+=%d\n",
2350 nop
, LRA_MAX_REJECT
);
2351 reject
+= LRA_MAX_REJECT
;
2354 if (! (MEM_P (op
) && offmemok
)
2355 && ! (const_to_mem
&& constmemok
))
2357 /* We prefer to reload pseudos over reloading other
2358 things, since such reloads may be able to be
2359 eliminated later. So bump REJECT in other cases.
2360 Don't do this in the case where we are forcing a
2361 constant into memory and it will then win since
2362 we don't want to have a different alternative
2364 if (! (REG_P (op
) && REGNO (op
) >= FIRST_PSEUDO_REGISTER
))
2366 if (lra_dump_file
!= NULL
)
2369 " %d Non-pseudo reload: reject+=2\n",
2376 += ira_reg_class_max_nregs
[this_alternative
][mode
];
2378 if (SMALL_REGISTER_CLASS_P (this_alternative
))
2380 if (lra_dump_file
!= NULL
)
2383 " %d Small class reload: reject+=%d\n",
2384 nop
, LRA_LOSER_COST_FACTOR
/ 2);
2385 reject
+= LRA_LOSER_COST_FACTOR
/ 2;
2389 /* We are trying to spill pseudo into memory. It is
2390 usually more costly than moving to a hard register
2391 although it might takes the same number of
2393 if (no_regs_p
&& REG_P (op
) && hard_regno
[nop
] >= 0)
2395 if (lra_dump_file
!= NULL
)
2398 " %d Spill pseudo into memory: reject+=3\n",
2401 if (VECTOR_MODE_P (mode
))
2403 /* Spilling vectors into memory is usually more
2404 costly as they contain big values. */
2405 if (lra_dump_file
!= NULL
)
2408 " %d Spill vector pseudo: reject+=2\n",
2414 #ifdef SECONDARY_MEMORY_NEEDED
2415 /* If reload requires moving value through secondary
2416 memory, it will need one more insn at least. */
2417 if (this_alternative
!= NO_REGS
2418 && REG_P (op
) && (cl
= get_reg_class (REGNO (op
))) != NO_REGS
2419 && ((curr_static_id
->operand
[nop
].type
!= OP_OUT
2420 && SECONDARY_MEMORY_NEEDED (cl
, this_alternative
,
2422 || (curr_static_id
->operand
[nop
].type
!= OP_IN
2423 && SECONDARY_MEMORY_NEEDED (this_alternative
, cl
,
2427 /* Input reloads can be inherited more often than output
2428 reloads can be removed, so penalize output
2430 if (!REG_P (op
) || curr_static_id
->operand
[nop
].type
!= OP_IN
)
2432 if (lra_dump_file
!= NULL
)
2435 " %d Non input pseudo reload: reject++\n",
2441 if (early_clobber_p
&& ! scratch_p
)
2443 if (lra_dump_file
!= NULL
)
2444 fprintf (lra_dump_file
,
2445 " %d Early clobber: reject++\n", nop
);
2448 /* ??? We check early clobbers after processing all operands
2449 (see loop below) and there we update the costs more.
2450 Should we update the cost (may be approximately) here
2451 because of early clobber register reloads or it is a rare
2452 or non-important thing to be worth to do it. */
2453 overall
= losers
* LRA_LOSER_COST_FACTOR
+ reject
;
2454 if ((best_losers
== 0 || losers
!= 0) && best_overall
< overall
)
2456 if (lra_dump_file
!= NULL
)
2457 fprintf (lra_dump_file
,
2458 " alt=%d,overall=%d,losers=%d -- refuse\n",
2459 nalt
, overall
, losers
);
2463 curr_alt
[nop
] = this_alternative
;
2464 COPY_HARD_REG_SET (curr_alt_set
[nop
], this_alternative_set
);
2465 curr_alt_win
[nop
] = this_alternative_win
;
2466 curr_alt_match_win
[nop
] = this_alternative_match_win
;
2467 curr_alt_offmemok
[nop
] = this_alternative_offmemok
;
2468 curr_alt_matches
[nop
] = this_alternative_matches
;
2470 if (this_alternative_matches
>= 0
2471 && !did_match
&& !this_alternative_win
)
2472 curr_alt_win
[this_alternative_matches
] = false;
2474 if (early_clobber_p
&& operand_reg
[nop
] != NULL_RTX
)
2475 early_clobbered_nops
[early_clobbered_regs_num
++] = nop
;
2477 if (curr_insn_set
!= NULL_RTX
&& n_operands
== 2
2478 /* Prevent processing non-move insns. */
2479 && (GET_CODE (SET_SRC (curr_insn_set
)) == SUBREG
2480 || SET_SRC (curr_insn_set
) == no_subreg_reg_operand
[1])
2481 && ((! curr_alt_win
[0] && ! curr_alt_win
[1]
2482 && REG_P (no_subreg_reg_operand
[0])
2483 && REG_P (no_subreg_reg_operand
[1])
2484 && (reg_in_class_p (no_subreg_reg_operand
[0], curr_alt
[1])
2485 || reg_in_class_p (no_subreg_reg_operand
[1], curr_alt
[0])))
2486 || (! curr_alt_win
[0] && curr_alt_win
[1]
2487 && REG_P (no_subreg_reg_operand
[1])
2488 && reg_in_class_p (no_subreg_reg_operand
[1], curr_alt
[0]))
2489 || (curr_alt_win
[0] && ! curr_alt_win
[1]
2490 && REG_P (no_subreg_reg_operand
[0])
2491 && reg_in_class_p (no_subreg_reg_operand
[0], curr_alt
[1])
2492 && (! CONST_POOL_OK_P (curr_operand_mode
[1],
2493 no_subreg_reg_operand
[1])
2494 || (targetm
.preferred_reload_class
2495 (no_subreg_reg_operand
[1],
2496 (enum reg_class
) curr_alt
[1]) != NO_REGS
))
2497 /* If it is a result of recent elimination in move
2498 insn we can transform it into an add still by
2499 using this alternative. */
2500 && GET_CODE (no_subreg_reg_operand
[1]) != PLUS
)))
2502 /* We have a move insn and a new reload insn will be similar
2503 to the current insn. We should avoid such situation as it
2504 results in LRA cycling. */
2505 overall
+= LRA_MAX_REJECT
;
2508 curr_alt_dont_inherit_ops_num
= 0;
2509 for (nop
= 0; nop
< early_clobbered_regs_num
; nop
++)
2511 int i
, j
, clobbered_hard_regno
, first_conflict_j
, last_conflict_j
;
2512 HARD_REG_SET temp_set
;
2514 i
= early_clobbered_nops
[nop
];
2515 if ((! curr_alt_win
[i
] && ! curr_alt_match_win
[i
])
2516 || hard_regno
[i
] < 0)
2518 lra_assert (operand_reg
[i
] != NULL_RTX
);
2519 clobbered_hard_regno
= hard_regno
[i
];
2520 CLEAR_HARD_REG_SET (temp_set
);
2521 add_to_hard_reg_set (&temp_set
, biggest_mode
[i
], clobbered_hard_regno
);
2522 first_conflict_j
= last_conflict_j
= -1;
2523 for (j
= 0; j
< n_operands
; j
++)
2525 /* We don't want process insides of match_operator and
2526 match_parallel because otherwise we would process
2527 their operands once again generating a wrong
2529 || curr_static_id
->operand
[j
].is_operator
)
2531 else if ((curr_alt_matches
[j
] == i
&& curr_alt_match_win
[j
])
2532 || (curr_alt_matches
[i
] == j
&& curr_alt_match_win
[i
]))
2534 /* If we don't reload j-th operand, check conflicts. */
2535 else if ((curr_alt_win
[j
] || curr_alt_match_win
[j
])
2536 && uses_hard_regs_p (*curr_id
->operand_loc
[j
], temp_set
))
2538 if (first_conflict_j
< 0)
2539 first_conflict_j
= j
;
2540 last_conflict_j
= j
;
2542 if (last_conflict_j
< 0)
2544 /* If earlyclobber operand conflicts with another
2545 non-matching operand which is actually the same register
2546 as the earlyclobber operand, it is better to reload the
2547 another operand as an operand matching the earlyclobber
2548 operand can be also the same. */
2549 if (first_conflict_j
== last_conflict_j
2550 && operand_reg
[last_conflict_j
]
2551 != NULL_RTX
&& ! curr_alt_match_win
[last_conflict_j
]
2552 && REGNO (operand_reg
[i
]) == REGNO (operand_reg
[last_conflict_j
]))
2554 curr_alt_win
[last_conflict_j
] = false;
2555 curr_alt_dont_inherit_ops
[curr_alt_dont_inherit_ops_num
++]
2558 /* Early clobber was already reflected in REJECT. */
2559 lra_assert (reject
> 0);
2560 if (lra_dump_file
!= NULL
)
2563 " %d Conflict early clobber reload: reject--\n",
2566 overall
+= LRA_LOSER_COST_FACTOR
- 1;
2570 /* We need to reload early clobbered register and the
2571 matched registers. */
2572 for (j
= 0; j
< n_operands
; j
++)
2573 if (curr_alt_matches
[j
] == i
)
2575 curr_alt_match_win
[j
] = false;
2577 overall
+= LRA_LOSER_COST_FACTOR
;
2579 if (! curr_alt_match_win
[i
])
2580 curr_alt_dont_inherit_ops
[curr_alt_dont_inherit_ops_num
++] = i
;
2583 /* Remember pseudos used for match reloads are never
2585 lra_assert (curr_alt_matches
[i
] >= 0);
2586 curr_alt_win
[curr_alt_matches
[i
]] = false;
2588 curr_alt_win
[i
] = curr_alt_match_win
[i
] = false;
2590 /* Early clobber was already reflected in REJECT. */
2591 lra_assert (reject
> 0);
2592 if (lra_dump_file
!= NULL
)
2595 " %d Matched conflict early clobber reloads:"
2599 overall
+= LRA_LOSER_COST_FACTOR
- 1;
2602 if (lra_dump_file
!= NULL
)
2603 fprintf (lra_dump_file
, " alt=%d,overall=%d,losers=%d,rld_nregs=%d\n",
2604 nalt
, overall
, losers
, reload_nregs
);
2606 /* If this alternative can be made to work by reloading, and it
2607 needs less reloading than the others checked so far, record
2608 it as the chosen goal for reloading. */
2609 if ((best_losers
!= 0 && losers
== 0)
2610 || (((best_losers
== 0 && losers
== 0)
2611 || (best_losers
!= 0 && losers
!= 0))
2612 && (best_overall
> overall
2613 || (best_overall
== overall
2614 /* If the cost of the reloads is the same,
2615 prefer alternative which requires minimal
2616 number of reload regs. */
2617 && (reload_nregs
< best_reload_nregs
2618 || (reload_nregs
== best_reload_nregs
2619 && (best_reload_sum
< reload_sum
2620 || (best_reload_sum
== reload_sum
2621 && nalt
< goal_alt_number
))))))))
2623 for (nop
= 0; nop
< n_operands
; nop
++)
2625 goal_alt_win
[nop
] = curr_alt_win
[nop
];
2626 goal_alt_match_win
[nop
] = curr_alt_match_win
[nop
];
2627 goal_alt_matches
[nop
] = curr_alt_matches
[nop
];
2628 goal_alt
[nop
] = curr_alt
[nop
];
2629 goal_alt_offmemok
[nop
] = curr_alt_offmemok
[nop
];
2631 goal_alt_dont_inherit_ops_num
= curr_alt_dont_inherit_ops_num
;
2632 for (nop
= 0; nop
< curr_alt_dont_inherit_ops_num
; nop
++)
2633 goal_alt_dont_inherit_ops
[nop
] = curr_alt_dont_inherit_ops
[nop
];
2634 goal_alt_swapped
= curr_swapped
;
2635 best_overall
= overall
;
2636 best_losers
= losers
;
2637 best_reload_nregs
= reload_nregs
;
2638 best_reload_sum
= reload_sum
;
2639 goal_alt_number
= nalt
;
2642 /* Everything is satisfied. Do not process alternatives
2651 /* Make reload base reg from address AD. */
2653 base_to_reg (struct address_info
*ad
)
2657 rtx new_inner
= NULL_RTX
;
2658 rtx new_reg
= NULL_RTX
;
2660 rtx_insn
*last_insn
= get_last_insn();
2662 lra_assert (ad
->base
== ad
->base_term
&& ad
->disp
== ad
->disp_term
);
2663 cl
= base_reg_class (ad
->mode
, ad
->as
, ad
->base_outer_code
,
2664 get_index_code (ad
));
2665 new_reg
= lra_create_new_reg (GET_MODE (*ad
->base_term
), NULL_RTX
,
2667 new_inner
= simplify_gen_binary (PLUS
, GET_MODE (new_reg
), new_reg
,
2668 ad
->disp_term
== NULL
2669 ? gen_int_mode (0, ad
->mode
)
2671 if (!valid_address_p (ad
->mode
, new_inner
, ad
->as
))
2673 insn
= emit_insn (gen_rtx_SET (ad
->mode
, new_reg
, *ad
->base_term
));
2674 code
= recog_memoized (insn
);
2677 delete_insns_since (last_insn
);
2684 /* Make reload base reg + disp from address AD. Return the new pseudo. */
2686 base_plus_disp_to_reg (struct address_info
*ad
)
2691 lra_assert (ad
->base
== ad
->base_term
&& ad
->disp
== ad
->disp_term
);
2692 cl
= base_reg_class (ad
->mode
, ad
->as
, ad
->base_outer_code
,
2693 get_index_code (ad
));
2694 new_reg
= lra_create_new_reg (GET_MODE (*ad
->base_term
), NULL_RTX
,
2696 lra_emit_add (new_reg
, *ad
->base_term
, *ad
->disp_term
);
2700 /* Make reload of index part of address AD. Return the new
2703 index_part_to_reg (struct address_info
*ad
)
2707 new_reg
= lra_create_new_reg (GET_MODE (*ad
->index
), NULL_RTX
,
2708 INDEX_REG_CLASS
, "index term");
2709 expand_mult (GET_MODE (*ad
->index
), *ad
->index_term
,
2710 GEN_INT (get_index_scale (ad
)), new_reg
, 1);
2714 /* Return true if we can add a displacement to address AD, even if that
2715 makes the address invalid. The fix-up code requires any new address
2716 to be the sum of the BASE_TERM, INDEX and DISP_TERM fields. */
2718 can_add_disp_p (struct address_info
*ad
)
2720 return (!ad
->autoinc_p
2721 && ad
->segment
== NULL
2722 && ad
->base
== ad
->base_term
2723 && ad
->disp
== ad
->disp_term
);
2726 /* Make equiv substitution in address AD. Return true if a substitution
2729 equiv_address_substitution (struct address_info
*ad
)
2731 rtx base_reg
, new_base_reg
, index_reg
, new_index_reg
, *base_term
, *index_term
;
2732 HOST_WIDE_INT disp
, scale
;
2735 base_term
= strip_subreg (ad
->base_term
);
2736 if (base_term
== NULL
)
2737 base_reg
= new_base_reg
= NULL_RTX
;
2740 base_reg
= *base_term
;
2741 new_base_reg
= get_equiv_with_elimination (base_reg
, curr_insn
);
2743 index_term
= strip_subreg (ad
->index_term
);
2744 if (index_term
== NULL
)
2745 index_reg
= new_index_reg
= NULL_RTX
;
2748 index_reg
= *index_term
;
2749 new_index_reg
= get_equiv_with_elimination (index_reg
, curr_insn
);
2751 if (base_reg
== new_base_reg
&& index_reg
== new_index_reg
)
2755 if (lra_dump_file
!= NULL
)
2757 fprintf (lra_dump_file
, "Changing address in insn %d ",
2758 INSN_UID (curr_insn
));
2759 dump_value_slim (lra_dump_file
, *ad
->outer
, 1);
2761 if (base_reg
!= new_base_reg
)
2763 if (REG_P (new_base_reg
))
2765 *base_term
= new_base_reg
;
2768 else if (GET_CODE (new_base_reg
) == PLUS
2769 && REG_P (XEXP (new_base_reg
, 0))
2770 && CONST_INT_P (XEXP (new_base_reg
, 1))
2771 && can_add_disp_p (ad
))
2773 disp
+= INTVAL (XEXP (new_base_reg
, 1));
2774 *base_term
= XEXP (new_base_reg
, 0);
2777 if (ad
->base_term2
!= NULL
)
2778 *ad
->base_term2
= *ad
->base_term
;
2780 if (index_reg
!= new_index_reg
)
2782 if (REG_P (new_index_reg
))
2784 *index_term
= new_index_reg
;
2787 else if (GET_CODE (new_index_reg
) == PLUS
2788 && REG_P (XEXP (new_index_reg
, 0))
2789 && CONST_INT_P (XEXP (new_index_reg
, 1))
2790 && can_add_disp_p (ad
)
2791 && (scale
= get_index_scale (ad
)))
2793 disp
+= INTVAL (XEXP (new_index_reg
, 1)) * scale
;
2794 *index_term
= XEXP (new_index_reg
, 0);
2800 if (ad
->disp
!= NULL
)
2801 *ad
->disp
= plus_constant (GET_MODE (*ad
->inner
), *ad
->disp
, disp
);
2804 *ad
->inner
= plus_constant (GET_MODE (*ad
->inner
), *ad
->inner
, disp
);
2805 update_address (ad
);
2809 if (lra_dump_file
!= NULL
)
2812 fprintf (lra_dump_file
, " -- no change\n");
2815 fprintf (lra_dump_file
, " on equiv ");
2816 dump_value_slim (lra_dump_file
, *ad
->outer
, 1);
2817 fprintf (lra_dump_file
, "\n");
2823 /* Major function to make reloads for an address in operand NOP or
2824 check its correctness (If CHECK_ONLY_P is true). The supported
2827 1) an address that existed before LRA started, at which point it
2828 must have been valid. These addresses are subject to elimination
2829 and may have become invalid due to the elimination offset being out
2832 2) an address created by forcing a constant to memory
2833 (force_const_to_mem). The initial form of these addresses might
2834 not be valid, and it is this function's job to make them valid.
2836 3) a frame address formed from a register and a (possibly zero)
2837 constant offset. As above, these addresses might not be valid and
2838 this function must make them so.
2840 Add reloads to the lists *BEFORE and *AFTER. We might need to add
2841 reloads to *AFTER because of inc/dec, {pre, post} modify in the
2842 address. Return true for any RTL change.
2844 The function is a helper function which does not produce all
2845 transformations (when CHECK_ONLY_P is false) which can be
2846 necessary. It does just basic steps. To do all necessary
2847 transformations use function process_address. */
2849 process_address_1 (int nop
, bool check_only_p
,
2850 rtx_insn
**before
, rtx_insn
**after
)
2852 struct address_info ad
;
2854 rtx op
= *curr_id
->operand_loc
[nop
];
2855 const char *constraint
= curr_static_id
->operand
[nop
].constraint
;
2856 enum constraint_num cn
= lookup_constraint (constraint
);
2857 bool change_p
= false;
2859 if (insn_extra_address_constraint (cn
))
2860 decompose_lea_address (&ad
, curr_id
->operand_loc
[nop
]);
2861 else if (MEM_P (op
))
2862 decompose_mem_address (&ad
, op
);
2863 else if (GET_CODE (op
) == SUBREG
2864 && MEM_P (SUBREG_REG (op
)))
2865 decompose_mem_address (&ad
, SUBREG_REG (op
));
2868 /* If INDEX_REG_CLASS is assigned to base_term already and isn't to
2869 index_term, swap them so to avoid assigning INDEX_REG_CLASS to both
2870 when INDEX_REG_CLASS is a single register class. */
2871 if (ad
.base_term
!= NULL
2872 && ad
.index_term
!= NULL
2873 && ira_class_hard_regs_num
[INDEX_REG_CLASS
] == 1
2874 && REG_P (*ad
.base_term
)
2875 && REG_P (*ad
.index_term
)
2876 && in_class_p (*ad
.base_term
, INDEX_REG_CLASS
, NULL
)
2877 && ! in_class_p (*ad
.index_term
, INDEX_REG_CLASS
, NULL
))
2879 std::swap (ad
.base
, ad
.index
);
2880 std::swap (ad
.base_term
, ad
.index_term
);
2883 change_p
= equiv_address_substitution (&ad
);
2884 if (ad
.base_term
!= NULL
2885 && (process_addr_reg
2886 (ad
.base_term
, check_only_p
, before
,
2888 && !(REG_P (*ad
.base_term
)
2889 && find_regno_note (curr_insn
, REG_DEAD
,
2890 REGNO (*ad
.base_term
)) != NULL_RTX
)
2892 base_reg_class (ad
.mode
, ad
.as
, ad
.base_outer_code
,
2893 get_index_code (&ad
)))))
2896 if (ad
.base_term2
!= NULL
)
2897 *ad
.base_term2
= *ad
.base_term
;
2899 if (ad
.index_term
!= NULL
2900 && process_addr_reg (ad
.index_term
, check_only_p
,
2901 before
, NULL
, INDEX_REG_CLASS
))
2904 /* Target hooks sometimes don't treat extra-constraint addresses as
2905 legitimate address_operands, so handle them specially. */
2906 if (insn_extra_address_constraint (cn
)
2907 && satisfies_address_constraint_p (&ad
, cn
))
2913 /* There are three cases where the shape of *AD.INNER may now be invalid:
2915 1) the original address was valid, but either elimination or
2916 equiv_address_substitution was applied and that made
2917 the address invalid.
2919 2) the address is an invalid symbolic address created by
2922 3) the address is a frame address with an invalid offset.
2924 4) the address is a frame address with an invalid base.
2926 All these cases involve a non-autoinc address, so there is no
2927 point revalidating other types. */
2928 if (ad
.autoinc_p
|| valid_address_p (&ad
))
2931 /* Any index existed before LRA started, so we can assume that the
2932 presence and shape of the index is valid. */
2933 push_to_sequence (*before
);
2934 lra_assert (ad
.disp
== ad
.disp_term
);
2935 if (ad
.base
== NULL
)
2937 if (ad
.index
== NULL
)
2940 enum reg_class cl
= base_reg_class (ad
.mode
, ad
.as
,
2942 rtx addr
= *ad
.inner
;
2944 new_reg
= lra_create_new_reg (Pmode
, NULL_RTX
, cl
, "addr");
2948 rtx_insn
*last
= get_last_insn ();
2950 /* addr => lo_sum (new_base, addr), case (2) above. */
2951 insn
= emit_insn (gen_rtx_SET
2953 gen_rtx_HIGH (Pmode
, copy_rtx (addr
))));
2954 code
= recog_memoized (insn
);
2957 *ad
.inner
= gen_rtx_LO_SUM (Pmode
, new_reg
, addr
);
2958 if (! valid_address_p (ad
.mode
, *ad
.outer
, ad
.as
))
2960 /* Try to put lo_sum into register. */
2961 insn
= emit_insn (gen_rtx_SET
2963 gen_rtx_LO_SUM (Pmode
, new_reg
, addr
)));
2964 code
= recog_memoized (insn
);
2967 *ad
.inner
= new_reg
;
2968 if (! valid_address_p (ad
.mode
, *ad
.outer
, ad
.as
))
2978 delete_insns_since (last
);
2983 /* addr => new_base, case (2) above. */
2984 lra_emit_move (new_reg
, addr
);
2985 *ad
.inner
= new_reg
;
2990 /* index * scale + disp => new base + index * scale,
2992 enum reg_class cl
= base_reg_class (ad
.mode
, ad
.as
, PLUS
,
2993 GET_CODE (*ad
.index
));
2995 lra_assert (INDEX_REG_CLASS
!= NO_REGS
);
2996 new_reg
= lra_create_new_reg (Pmode
, NULL_RTX
, cl
, "disp");
2997 lra_emit_move (new_reg
, *ad
.disp
);
2998 *ad
.inner
= simplify_gen_binary (PLUS
, GET_MODE (new_reg
),
2999 new_reg
, *ad
.index
);
3002 else if (ad
.index
== NULL
)
3007 rtx_insn
*insns
, *last_insn
;
3008 /* Try to reload base into register only if the base is invalid
3009 for the address but with valid offset, case (4) above. */
3011 new_reg
= base_to_reg (&ad
);
3013 /* base + disp => new base, cases (1) and (3) above. */
3014 /* Another option would be to reload the displacement into an
3015 index register. However, postreload has code to optimize
3016 address reloads that have the same base and different
3017 displacements, so reloading into an index register would
3018 not necessarily be a win. */
3019 if (new_reg
== NULL_RTX
)
3020 new_reg
= base_plus_disp_to_reg (&ad
);
3021 insns
= get_insns ();
3022 last_insn
= get_last_insn ();
3023 /* If we generated at least two insns, try last insn source as
3024 an address. If we succeed, we generate one less insn. */
3025 if (last_insn
!= insns
&& (set
= single_set (last_insn
)) != NULL_RTX
3026 && GET_CODE (SET_SRC (set
)) == PLUS
3027 && REG_P (XEXP (SET_SRC (set
), 0))
3028 && CONSTANT_P (XEXP (SET_SRC (set
), 1)))
3030 *ad
.inner
= SET_SRC (set
);
3031 if (valid_address_p (ad
.mode
, *ad
.outer
, ad
.as
))
3033 *ad
.base_term
= XEXP (SET_SRC (set
), 0);
3034 *ad
.disp_term
= XEXP (SET_SRC (set
), 1);
3035 cl
= base_reg_class (ad
.mode
, ad
.as
, ad
.base_outer_code
,
3036 get_index_code (&ad
));
3037 regno
= REGNO (*ad
.base_term
);
3038 if (regno
>= FIRST_PSEUDO_REGISTER
3039 && cl
!= lra_get_allocno_class (regno
))
3040 lra_change_class (regno
, cl
, " Change to", true);
3041 new_reg
= SET_SRC (set
);
3042 delete_insns_since (PREV_INSN (last_insn
));
3045 /* Try if target can split displacement into legitimite new disp
3046 and offset. If it's the case, we replace the last insn with
3047 insns for base + offset => new_reg and set new_reg + new disp
3049 last_insn
= get_last_insn ();
3050 if ((set
= single_set (last_insn
)) != NULL_RTX
3051 && GET_CODE (SET_SRC (set
)) == PLUS
3052 && REG_P (XEXP (SET_SRC (set
), 0))
3053 && REGNO (XEXP (SET_SRC (set
), 0)) < FIRST_PSEUDO_REGISTER
3054 && CONST_INT_P (XEXP (SET_SRC (set
), 1)))
3056 rtx addend
, disp
= XEXP (SET_SRC (set
), 1);
3057 if (targetm
.legitimize_address_displacement (&disp
, &addend
,
3060 rtx_insn
*new_insns
;
3062 lra_emit_add (new_reg
, XEXP (SET_SRC (set
), 0), addend
);
3063 new_insns
= get_insns ();
3065 new_reg
= gen_rtx_PLUS (Pmode
, new_reg
, disp
);
3066 delete_insns_since (PREV_INSN (last_insn
));
3067 add_insn (new_insns
);
3068 insns
= get_insns ();
3073 *ad
.inner
= new_reg
;
3075 else if (ad
.disp_term
!= NULL
)
3077 /* base + scale * index + disp => new base + scale * index,
3079 new_reg
= base_plus_disp_to_reg (&ad
);
3080 *ad
.inner
= simplify_gen_binary (PLUS
, GET_MODE (new_reg
),
3081 new_reg
, *ad
.index
);
3083 else if (get_index_scale (&ad
) == 1)
3085 /* The last transformation to one reg will be made in
3086 curr_insn_transform function. */
3092 /* base + scale * index => base + new_reg,
3094 Index part of address may become invalid. For example, we
3095 changed pseudo on the equivalent memory and a subreg of the
3096 pseudo onto the memory of different mode for which the scale is
3098 new_reg
= index_part_to_reg (&ad
);
3099 *ad
.inner
= simplify_gen_binary (PLUS
, GET_MODE (new_reg
),
3100 *ad
.base_term
, new_reg
);
3102 *before
= get_insns ();
3107 /* If CHECK_ONLY_P is false, do address reloads until it is necessary.
3108 Use process_address_1 as a helper function. Return true for any
3111 If CHECK_ONLY_P is true, just check address correctness. Return
3112 false if the address correct. */
3114 process_address (int nop
, bool check_only_p
,
3115 rtx_insn
**before
, rtx_insn
**after
)
3119 while (process_address_1 (nop
, check_only_p
, before
, after
))
3128 /* Emit insns to reload VALUE into a new register. VALUE is an
3129 auto-increment or auto-decrement RTX whose operand is a register or
3130 memory location; so reloading involves incrementing that location.
3131 IN is either identical to VALUE, or some cheaper place to reload
3132 value being incremented/decremented from.
3134 INC_AMOUNT is the number to increment or decrement by (always
3135 positive and ignored for POST_MODIFY/PRE_MODIFY).
3137 Return pseudo containing the result. */
3139 emit_inc (enum reg_class new_rclass
, rtx in
, rtx value
, int inc_amount
)
3141 /* REG or MEM to be copied and incremented. */
3142 rtx incloc
= XEXP (value
, 0);
3143 /* Nonzero if increment after copying. */
3144 int post
= (GET_CODE (value
) == POST_DEC
|| GET_CODE (value
) == POST_INC
3145 || GET_CODE (value
) == POST_MODIFY
);
3150 rtx real_in
= in
== value
? incloc
: in
;
3154 if (GET_CODE (value
) == PRE_MODIFY
|| GET_CODE (value
) == POST_MODIFY
)
3156 lra_assert (GET_CODE (XEXP (value
, 1)) == PLUS
3157 || GET_CODE (XEXP (value
, 1)) == MINUS
);
3158 lra_assert (rtx_equal_p (XEXP (XEXP (value
, 1), 0), XEXP (value
, 0)));
3159 plus_p
= GET_CODE (XEXP (value
, 1)) == PLUS
;
3160 inc
= XEXP (XEXP (value
, 1), 1);
3164 if (GET_CODE (value
) == PRE_DEC
|| GET_CODE (value
) == POST_DEC
)
3165 inc_amount
= -inc_amount
;
3167 inc
= GEN_INT (inc_amount
);
3170 if (! post
&& REG_P (incloc
))
3173 result
= lra_create_new_reg (GET_MODE (value
), value
, new_rclass
,
3176 if (real_in
!= result
)
3178 /* First copy the location to the result register. */
3179 lra_assert (REG_P (result
));
3180 emit_insn (gen_move_insn (result
, real_in
));
3183 /* We suppose that there are insns to add/sub with the constant
3184 increment permitted in {PRE/POST)_{DEC/INC/MODIFY}. At least the
3185 old reload worked with this assumption. If the assumption
3186 becomes wrong, we should use approach in function
3187 base_plus_disp_to_reg. */
3190 /* See if we can directly increment INCLOC. */
3191 last
= get_last_insn ();
3192 add_insn
= emit_insn (plus_p
3193 ? gen_add2_insn (incloc
, inc
)
3194 : gen_sub2_insn (incloc
, inc
));
3196 code
= recog_memoized (add_insn
);
3199 if (! post
&& result
!= incloc
)
3200 emit_insn (gen_move_insn (result
, incloc
));
3203 delete_insns_since (last
);
3206 /* If couldn't do the increment directly, must increment in RESULT.
3207 The way we do this depends on whether this is pre- or
3208 post-increment. For pre-increment, copy INCLOC to the reload
3209 register, increment it there, then save back. */
3212 if (real_in
!= result
)
3213 emit_insn (gen_move_insn (result
, real_in
));
3215 emit_insn (gen_add2_insn (result
, inc
));
3217 emit_insn (gen_sub2_insn (result
, inc
));
3218 if (result
!= incloc
)
3219 emit_insn (gen_move_insn (incloc
, result
));
3225 Because this might be a jump insn or a compare, and because
3226 RESULT may not be available after the insn in an input
3227 reload, we must do the incrementing before the insn being
3230 We have already copied IN to RESULT. Increment the copy in
3231 RESULT, save that back, then decrement RESULT so it has
3232 the original value. */
3234 emit_insn (gen_add2_insn (result
, inc
));
3236 emit_insn (gen_sub2_insn (result
, inc
));
3237 emit_insn (gen_move_insn (incloc
, result
));
3238 /* Restore non-modified value for the result. We prefer this
3239 way because it does not require an additional hard
3243 if (CONST_INT_P (inc
))
3244 emit_insn (gen_add2_insn (result
,
3245 gen_int_mode (-INTVAL (inc
),
3246 GET_MODE (result
))));
3248 emit_insn (gen_sub2_insn (result
, inc
));
3251 emit_insn (gen_add2_insn (result
, inc
));
3256 /* Return true if the current move insn does not need processing as we
3257 already know that it satisfies its constraints. */
3259 simple_move_p (void)
3262 enum reg_class dclass
, sclass
;
3264 lra_assert (curr_insn_set
!= NULL_RTX
);
3265 dest
= SET_DEST (curr_insn_set
);
3266 src
= SET_SRC (curr_insn_set
);
3267 return ((dclass
= get_op_class (dest
)) != NO_REGS
3268 && (sclass
= get_op_class (src
)) != NO_REGS
3269 /* The backend guarantees that register moves of cost 2
3270 never need reloads. */
3271 && targetm
.register_move_cost (GET_MODE (src
), sclass
, dclass
) == 2);
3274 /* Swap operands NOP and NOP + 1. */
3276 swap_operands (int nop
)
3278 machine_mode mode
= curr_operand_mode
[nop
];
3279 curr_operand_mode
[nop
] = curr_operand_mode
[nop
+ 1];
3280 curr_operand_mode
[nop
+ 1] = mode
;
3281 rtx x
= *curr_id
->operand_loc
[nop
];
3282 *curr_id
->operand_loc
[nop
] = *curr_id
->operand_loc
[nop
+ 1];
3283 *curr_id
->operand_loc
[nop
+ 1] = x
;
3284 /* Swap the duplicates too. */
3285 lra_update_dup (curr_id
, nop
);
3286 lra_update_dup (curr_id
, nop
+ 1);
3289 /* Main entry point of the constraint code: search the body of the
3290 current insn to choose the best alternative. It is mimicking insn
3291 alternative cost calculation model of former reload pass. That is
3292 because machine descriptions were written to use this model. This
3293 model can be changed in future. Make commutative operand exchange
3296 if CHECK_ONLY_P is false, do RTL changes to satisfy the
3297 constraints. Return true if any change happened during function
3300 If CHECK_ONLY_P is true then don't do any transformation. Just
3301 check that the insn satisfies all constraints. If the insn does
3302 not satisfy any constraint, return true. */
3304 curr_insn_transform (bool check_only_p
)
3310 signed char goal_alt_matched
[MAX_RECOG_OPERANDS
][MAX_RECOG_OPERANDS
];
3311 signed char match_inputs
[MAX_RECOG_OPERANDS
+ 1];
3312 rtx_insn
*before
, *after
;
3314 /* Flag that the insn has been changed through a transformation. */
3317 #ifdef SECONDARY_MEMORY_NEEDED
3320 int max_regno_before
;
3321 int reused_alternative_num
;
3323 curr_insn_set
= single_set (curr_insn
);
3324 if (curr_insn_set
!= NULL_RTX
&& simple_move_p ())
3327 no_input_reloads_p
= no_output_reloads_p
= false;
3328 goal_alt_number
= -1;
3329 change_p
= sec_mem_p
= false;
3330 /* JUMP_INSNs and CALL_INSNs are not allowed to have any output
3331 reloads; neither are insns that SET cc0. Insns that use CC0 are
3332 not allowed to have any input reloads. */
3333 if (JUMP_P (curr_insn
) || CALL_P (curr_insn
))
3334 no_output_reloads_p
= true;
3337 if (reg_referenced_p (cc0_rtx
, PATTERN (curr_insn
)))
3338 no_input_reloads_p
= true;
3339 if (reg_set_p (cc0_rtx
, PATTERN (curr_insn
)))
3340 no_output_reloads_p
= true;
3343 n_operands
= curr_static_id
->n_operands
;
3344 n_alternatives
= curr_static_id
->n_alternatives
;
3346 /* Just return "no reloads" if insn has no operands with
3348 if (n_operands
== 0 || n_alternatives
== 0)
3351 max_regno_before
= max_reg_num ();
3353 for (i
= 0; i
< n_operands
; i
++)
3355 goal_alt_matched
[i
][0] = -1;
3356 goal_alt_matches
[i
] = -1;
3359 commutative
= curr_static_id
->commutative
;
3361 /* Now see what we need for pseudos that didn't get hard regs or got
3362 the wrong kind of hard reg. For this, we must consider all the
3363 operands together against the register constraints. */
3365 best_losers
= best_overall
= INT_MAX
;
3366 best_reload_sum
= 0;
3368 curr_swapped
= false;
3369 goal_alt_swapped
= false;
3372 /* Make equivalence substitution and memory subreg elimination
3373 before address processing because an address legitimacy can
3374 depend on memory mode. */
3375 for (i
= 0; i
< n_operands
; i
++)
3377 rtx op
= *curr_id
->operand_loc
[i
];
3378 rtx subst
, old
= op
;
3379 bool op_change_p
= false;
3381 if (GET_CODE (old
) == SUBREG
)
3382 old
= SUBREG_REG (old
);
3383 subst
= get_equiv_with_elimination (old
, curr_insn
);
3386 subst
= copy_rtx (subst
);
3387 lra_assert (REG_P (old
));
3388 if (GET_CODE (op
) == SUBREG
)
3389 SUBREG_REG (op
) = subst
;
3391 *curr_id
->operand_loc
[i
] = subst
;
3392 if (lra_dump_file
!= NULL
)
3394 fprintf (lra_dump_file
,
3395 "Changing pseudo %d in operand %i of insn %u on equiv ",
3396 REGNO (old
), i
, INSN_UID (curr_insn
));
3397 dump_value_slim (lra_dump_file
, subst
, 1);
3398 fprintf (lra_dump_file
, "\n");
3400 op_change_p
= change_p
= true;
3402 if (simplify_operand_subreg (i
, GET_MODE (old
)) || op_change_p
)
3405 lra_update_dup (curr_id
, i
);
3409 /* Reload address registers and displacements. We do it before
3410 finding an alternative because of memory constraints. */
3411 before
= after
= NULL
;
3412 for (i
= 0; i
< n_operands
; i
++)
3413 if (! curr_static_id
->operand
[i
].is_operator
3414 && process_address (i
, check_only_p
, &before
, &after
))
3419 lra_update_dup (curr_id
, i
);
3423 /* If we've changed the instruction then any alternative that
3424 we chose previously may no longer be valid. */
3425 lra_set_used_insn_alternative (curr_insn
, -1);
3427 if (! check_only_p
&& curr_insn_set
!= NULL_RTX
3428 && check_and_process_move (&change_p
, &sec_mem_p
))
3433 reused_alternative_num
= check_only_p
? -1 : curr_id
->used_insn_alternative
;
3434 if (lra_dump_file
!= NULL
&& reused_alternative_num
>= 0)
3435 fprintf (lra_dump_file
, "Reusing alternative %d for insn #%u\n",
3436 reused_alternative_num
, INSN_UID (curr_insn
));
3438 if (process_alt_operands (reused_alternative_num
))
3442 return ! alt_p
|| best_losers
!= 0;
3444 /* If insn is commutative (it's safe to exchange a certain pair of
3445 operands) then we need to try each alternative twice, the second
3446 time matching those two operands as if we had exchanged them. To
3447 do this, really exchange them in operands.
3449 If we have just tried the alternatives the second time, return
3450 operands to normal and drop through. */
3452 if (reused_alternative_num
< 0 && commutative
>= 0)
3454 curr_swapped
= !curr_swapped
;
3457 swap_operands (commutative
);
3461 swap_operands (commutative
);
3464 if (! alt_p
&& ! sec_mem_p
)
3466 /* No alternative works with reloads?? */
3467 if (INSN_CODE (curr_insn
) >= 0)
3468 fatal_insn ("unable to generate reloads for:", curr_insn
);
3469 error_for_asm (curr_insn
,
3470 "inconsistent operand constraints in an %<asm%>");
3471 /* Avoid further trouble with this insn. */
3472 PATTERN (curr_insn
) = gen_rtx_USE (VOIDmode
, const0_rtx
);
3473 lra_invalidate_insn_data (curr_insn
);
3477 /* If the best alternative is with operands 1 and 2 swapped, swap
3478 them. Update the operand numbers of any reloads already
3481 if (goal_alt_swapped
)
3483 if (lra_dump_file
!= NULL
)
3484 fprintf (lra_dump_file
, " Commutative operand exchange in insn %u\n",
3485 INSN_UID (curr_insn
));
3487 /* Swap the duplicates too. */
3488 swap_operands (commutative
);
3492 #ifdef SECONDARY_MEMORY_NEEDED
3493 /* Some target macros SECONDARY_MEMORY_NEEDED (e.g. x86) are defined
3494 too conservatively. So we use the secondary memory only if there
3495 is no any alternative without reloads. */
3496 use_sec_mem_p
= false;
3498 use_sec_mem_p
= true;
3501 for (i
= 0; i
< n_operands
; i
++)
3502 if (! goal_alt_win
[i
] && ! goal_alt_match_win
[i
])
3504 use_sec_mem_p
= i
< n_operands
;
3509 rtx new_reg
, src
, dest
, rld
;
3510 machine_mode sec_mode
, rld_mode
;
3512 lra_assert (sec_mem_p
);
3513 lra_assert (curr_static_id
->operand
[0].type
== OP_OUT
3514 && curr_static_id
->operand
[1].type
== OP_IN
);
3515 dest
= *curr_id
->operand_loc
[0];
3516 src
= *curr_id
->operand_loc
[1];
3517 rld
= (GET_MODE_SIZE (GET_MODE (dest
)) <= GET_MODE_SIZE (GET_MODE (src
))
3519 rld_mode
= GET_MODE (rld
);
3520 #ifdef SECONDARY_MEMORY_NEEDED_MODE
3521 sec_mode
= SECONDARY_MEMORY_NEEDED_MODE (rld_mode
);
3523 sec_mode
= rld_mode
;
3525 new_reg
= lra_create_new_reg (sec_mode
, NULL_RTX
,
3526 NO_REGS
, "secondary");
3527 /* If the mode is changed, it should be wider. */
3528 lra_assert (GET_MODE_SIZE (sec_mode
) >= GET_MODE_SIZE (rld_mode
));
3529 if (sec_mode
!= rld_mode
)
3531 /* If the target says specifically to use another mode for
3532 secondary memory moves we can not reuse the original
3534 after
= emit_spill_move (false, new_reg
, dest
);
3535 lra_process_new_insns (curr_insn
, NULL
, after
,
3536 "Inserting the sec. move");
3537 /* We may have non null BEFORE here (e.g. after address
3539 push_to_sequence (before
);
3540 before
= emit_spill_move (true, new_reg
, src
);
3542 before
= get_insns ();
3544 lra_process_new_insns (curr_insn
, before
, NULL
, "Changing on");
3545 lra_set_insn_deleted (curr_insn
);
3547 else if (dest
== rld
)
3549 *curr_id
->operand_loc
[0] = new_reg
;
3550 after
= emit_spill_move (false, new_reg
, dest
);
3551 lra_process_new_insns (curr_insn
, NULL
, after
,
3552 "Inserting the sec. move");
3556 *curr_id
->operand_loc
[1] = new_reg
;
3557 /* See comments above. */
3558 push_to_sequence (before
);
3559 before
= emit_spill_move (true, new_reg
, src
);
3561 before
= get_insns ();
3563 lra_process_new_insns (curr_insn
, before
, NULL
,
3564 "Inserting the sec. move");
3566 lra_update_insn_regno_info (curr_insn
);
3571 lra_assert (goal_alt_number
>= 0);
3572 lra_set_used_insn_alternative (curr_insn
, goal_alt_number
);
3574 if (lra_dump_file
!= NULL
)
3578 fprintf (lra_dump_file
, " Choosing alt %d in insn %u:",
3579 goal_alt_number
, INSN_UID (curr_insn
));
3580 for (i
= 0; i
< n_operands
; i
++)
3582 p
= (curr_static_id
->operand_alternative
3583 [goal_alt_number
* n_operands
+ i
].constraint
);
3586 fprintf (lra_dump_file
, " (%d) ", i
);
3587 for (; *p
!= '\0' && *p
!= ',' && *p
!= '#'; p
++)
3588 fputc (*p
, lra_dump_file
);
3590 if (INSN_CODE (curr_insn
) >= 0
3591 && (p
= get_insn_name (INSN_CODE (curr_insn
))) != NULL
)
3592 fprintf (lra_dump_file
, " {%s}", p
);
3593 if (curr_id
->sp_offset
!= 0)
3594 fprintf (lra_dump_file
, " (sp_off=%" HOST_WIDE_INT_PRINT
"d)",
3595 curr_id
->sp_offset
);
3596 fprintf (lra_dump_file
, "\n");
3599 /* Right now, for any pair of operands I and J that are required to
3600 match, with J < I, goal_alt_matches[I] is J. Add I to
3601 goal_alt_matched[J]. */
3603 for (i
= 0; i
< n_operands
; i
++)
3604 if ((j
= goal_alt_matches
[i
]) >= 0)
3606 for (k
= 0; goal_alt_matched
[j
][k
] >= 0; k
++)
3608 /* We allow matching one output operand and several input
3611 || (curr_static_id
->operand
[j
].type
== OP_OUT
3612 && curr_static_id
->operand
[i
].type
== OP_IN
3613 && (curr_static_id
->operand
3614 [goal_alt_matched
[j
][0]].type
== OP_IN
)));
3615 goal_alt_matched
[j
][k
] = i
;
3616 goal_alt_matched
[j
][k
+ 1] = -1;
3619 for (i
= 0; i
< n_operands
; i
++)
3620 goal_alt_win
[i
] |= goal_alt_match_win
[i
];
3622 /* Any constants that aren't allowed and can't be reloaded into
3623 registers are here changed into memory references. */
3624 for (i
= 0; i
< n_operands
; i
++)
3625 if (goal_alt_win
[i
])
3628 enum reg_class new_class
;
3629 rtx reg
= *curr_id
->operand_loc
[i
];
3631 if (GET_CODE (reg
) == SUBREG
)
3632 reg
= SUBREG_REG (reg
);
3634 if (REG_P (reg
) && (regno
= REGNO (reg
)) >= FIRST_PSEUDO_REGISTER
)
3636 bool ok_p
= in_class_p (reg
, goal_alt
[i
], &new_class
);
3638 if (new_class
!= NO_REGS
&& get_reg_class (regno
) != new_class
)
3641 lra_change_class (regno
, new_class
, " Change to", true);
3647 const char *constraint
;
3649 rtx op
= *curr_id
->operand_loc
[i
];
3650 rtx subreg
= NULL_RTX
;
3651 machine_mode mode
= curr_operand_mode
[i
];
3653 if (GET_CODE (op
) == SUBREG
)
3656 op
= SUBREG_REG (op
);
3657 mode
= GET_MODE (op
);
3660 if (CONST_POOL_OK_P (mode
, op
)
3661 && ((targetm
.preferred_reload_class
3662 (op
, (enum reg_class
) goal_alt
[i
]) == NO_REGS
)
3663 || no_input_reloads_p
))
3665 rtx tem
= force_const_mem (mode
, op
);
3668 if (subreg
!= NULL_RTX
)
3669 tem
= gen_rtx_SUBREG (mode
, tem
, SUBREG_BYTE (subreg
));
3671 *curr_id
->operand_loc
[i
] = tem
;
3672 lra_update_dup (curr_id
, i
);
3673 process_address (i
, false, &before
, &after
);
3675 /* If the alternative accepts constant pool refs directly
3676 there will be no reload needed at all. */
3677 if (subreg
!= NULL_RTX
)
3679 /* Skip alternatives before the one requested. */
3680 constraint
= (curr_static_id
->operand_alternative
3681 [goal_alt_number
* n_operands
+ i
].constraint
);
3683 (c
= *constraint
) && c
!= ',' && c
!= '#';
3684 constraint
+= CONSTRAINT_LEN (c
, constraint
))
3686 enum constraint_num cn
= lookup_constraint (constraint
);
3687 if (insn_extra_memory_constraint (cn
)
3688 && satisfies_memory_constraint_p (tem
, cn
))
3691 if (c
== '\0' || c
== ',' || c
== '#')
3694 goal_alt_win
[i
] = true;
3698 for (i
= 0; i
< n_operands
; i
++)
3701 bool optional_p
= false;
3703 rtx op
= *curr_id
->operand_loc
[i
];
3705 if (goal_alt_win
[i
])
3707 if (goal_alt
[i
] == NO_REGS
3709 /* When we assign NO_REGS it means that we will not
3710 assign a hard register to the scratch pseudo by
3711 assigment pass and the scratch pseudo will be
3712 spilled. Spilled scratch pseudos are transformed
3713 back to scratches at the LRA end. */
3714 && lra_former_scratch_operand_p (curr_insn
, i
))
3716 int regno
= REGNO (op
);
3717 lra_change_class (regno
, NO_REGS
, " Change to", true);
3718 if (lra_get_regno_hard_regno (regno
) >= 0)
3719 /* We don't have to mark all insn affected by the
3720 spilled pseudo as there is only one such insn, the
3722 reg_renumber
[regno
] = -1;
3724 /* We can do an optional reload. If the pseudo got a hard
3725 reg, we might improve the code through inheritance. If
3726 it does not get a hard register we coalesce memory/memory
3727 moves later. Ignore move insns to avoid cycling. */
3729 && lra_undo_inheritance_iter
< LRA_MAX_INHERITANCE_PASSES
3730 && goal_alt
[i
] != NO_REGS
&& REG_P (op
)
3731 && (regno
= REGNO (op
)) >= FIRST_PSEUDO_REGISTER
3732 && regno
< new_regno_start
3733 && ! lra_former_scratch_p (regno
)
3734 && reg_renumber
[regno
] < 0
3735 && (curr_insn_set
== NULL_RTX
3736 || !((REG_P (SET_SRC (curr_insn_set
))
3737 || MEM_P (SET_SRC (curr_insn_set
))
3738 || GET_CODE (SET_SRC (curr_insn_set
)) == SUBREG
)
3739 && (REG_P (SET_DEST (curr_insn_set
))
3740 || MEM_P (SET_DEST (curr_insn_set
))
3741 || GET_CODE (SET_DEST (curr_insn_set
)) == SUBREG
))))
3747 /* Operands that match previous ones have already been handled. */
3748 if (goal_alt_matches
[i
] >= 0)
3751 /* We should not have an operand with a non-offsettable address
3752 appearing where an offsettable address will do. It also may
3753 be a case when the address should be special in other words
3754 not a general one (e.g. it needs no index reg). */
3755 if (goal_alt_matched
[i
][0] == -1 && goal_alt_offmemok
[i
] && MEM_P (op
))
3757 enum reg_class rclass
;
3758 rtx
*loc
= &XEXP (op
, 0);
3759 enum rtx_code code
= GET_CODE (*loc
);
3761 push_to_sequence (before
);
3762 rclass
= base_reg_class (GET_MODE (op
), MEM_ADDR_SPACE (op
),
3764 if (GET_RTX_CLASS (code
) == RTX_AUTOINC
)
3765 new_reg
= emit_inc (rclass
, *loc
, *loc
,
3766 /* This value does not matter for MODIFY. */
3767 GET_MODE_SIZE (GET_MODE (op
)));
3768 else if (get_reload_reg (OP_IN
, Pmode
, *loc
, rclass
, FALSE
,
3769 "offsetable address", &new_reg
))
3770 lra_emit_move (new_reg
, *loc
);
3771 before
= get_insns ();
3774 lra_update_dup (curr_id
, i
);
3776 else if (goal_alt_matched
[i
][0] == -1)
3780 int hard_regno
, byte
;
3781 enum op_type type
= curr_static_id
->operand
[i
].type
;
3783 loc
= curr_id
->operand_loc
[i
];
3784 mode
= curr_operand_mode
[i
];
3785 if (GET_CODE (*loc
) == SUBREG
)
3787 reg
= SUBREG_REG (*loc
);
3788 byte
= SUBREG_BYTE (*loc
);
3790 /* Strict_low_part requires reload the register not
3791 the sub-register. */
3792 && (curr_static_id
->operand
[i
].strict_low
3793 || (GET_MODE_SIZE (mode
)
3794 <= GET_MODE_SIZE (GET_MODE (reg
))
3796 = get_try_hard_regno (REGNO (reg
))) >= 0
3797 && (simplify_subreg_regno
3799 GET_MODE (reg
), byte
, mode
) < 0)
3800 && (goal_alt
[i
] == NO_REGS
3801 || (simplify_subreg_regno
3802 (ira_class_hard_regs
[goal_alt
[i
]][0],
3803 GET_MODE (reg
), byte
, mode
) >= 0)))))
3805 loc
= &SUBREG_REG (*loc
);
3806 mode
= GET_MODE (*loc
);
3810 if (get_reload_reg (type
, mode
, old
, goal_alt
[i
],
3811 loc
!= curr_id
->operand_loc
[i
], "", &new_reg
)
3814 push_to_sequence (before
);
3815 lra_emit_move (new_reg
, old
);
3816 before
= get_insns ();
3821 && find_reg_note (curr_insn
, REG_UNUSED
, old
) == NULL_RTX
)
3824 lra_emit_move (type
== OP_INOUT
? copy_rtx (old
) : old
, new_reg
);
3826 after
= get_insns ();
3830 for (j
= 0; j
< goal_alt_dont_inherit_ops_num
; j
++)
3831 if (goal_alt_dont_inherit_ops
[j
] == i
)
3833 lra_set_regno_unique_value (REGNO (new_reg
));
3836 lra_update_dup (curr_id
, i
);
3838 else if (curr_static_id
->operand
[i
].type
== OP_IN
3839 && (curr_static_id
->operand
[goal_alt_matched
[i
][0]].type
3842 /* generate reloads for input and matched outputs. */
3843 match_inputs
[0] = i
;
3844 match_inputs
[1] = -1;
3845 match_reload (goal_alt_matched
[i
][0], match_inputs
,
3846 goal_alt
[i
], &before
, &after
);
3848 else if (curr_static_id
->operand
[i
].type
== OP_OUT
3849 && (curr_static_id
->operand
[goal_alt_matched
[i
][0]].type
3851 /* Generate reloads for output and matched inputs. */
3852 match_reload (i
, goal_alt_matched
[i
], goal_alt
[i
], &before
, &after
);
3853 else if (curr_static_id
->operand
[i
].type
== OP_IN
3854 && (curr_static_id
->operand
[goal_alt_matched
[i
][0]].type
3857 /* Generate reloads for matched inputs. */
3858 match_inputs
[0] = i
;
3859 for (j
= 0; (k
= goal_alt_matched
[i
][j
]) >= 0; j
++)
3860 match_inputs
[j
+ 1] = k
;
3861 match_inputs
[j
+ 1] = -1;
3862 match_reload (-1, match_inputs
, goal_alt
[i
], &before
, &after
);
3865 /* We must generate code in any case when function
3866 process_alt_operands decides that it is possible. */
3870 lra_assert (REG_P (op
));
3872 op
= *curr_id
->operand_loc
[i
]; /* Substitution. */
3873 if (GET_CODE (op
) == SUBREG
)
3874 op
= SUBREG_REG (op
);
3875 gcc_assert (REG_P (op
) && (int) REGNO (op
) >= new_regno_start
);
3876 bitmap_set_bit (&lra_optional_reload_pseudos
, REGNO (op
));
3877 lra_reg_info
[REGNO (op
)].restore_regno
= regno
;
3878 if (lra_dump_file
!= NULL
)
3879 fprintf (lra_dump_file
,
3880 " Making reload reg %d for reg %d optional\n",
3884 if (before
!= NULL_RTX
|| after
!= NULL_RTX
3885 || max_regno_before
!= max_reg_num ())
3889 lra_update_operator_dups (curr_id
);
3890 /* Something changes -- process the insn. */
3891 lra_update_insn_regno_info (curr_insn
);
3893 lra_process_new_insns (curr_insn
, before
, after
, "Inserting insn reload");
3897 /* Return true if INSN satisfies all constraints. In other words, no
3898 reload insns are needed. */
3900 lra_constrain_insn (rtx_insn
*insn
)
3902 int saved_new_regno_start
= new_regno_start
;
3903 int saved_new_insn_uid_start
= new_insn_uid_start
;
3907 curr_id
= lra_get_insn_recog_data (curr_insn
);
3908 curr_static_id
= curr_id
->insn_static_data
;
3909 new_insn_uid_start
= get_max_uid ();
3910 new_regno_start
= max_reg_num ();
3911 change_p
= curr_insn_transform (true);
3912 new_regno_start
= saved_new_regno_start
;
3913 new_insn_uid_start
= saved_new_insn_uid_start
;
3917 /* Return true if X is in LIST. */
3919 in_list_p (rtx x
, rtx list
)
3921 for (; list
!= NULL_RTX
; list
= XEXP (list
, 1))
3922 if (XEXP (list
, 0) == x
)
3927 /* Return true if X contains an allocatable hard register (if
3928 HARD_REG_P) or a (spilled if SPILLED_P) pseudo. */
3930 contains_reg_p (rtx x
, bool hard_reg_p
, bool spilled_p
)
3936 code
= GET_CODE (x
);
3939 int regno
= REGNO (x
);
3940 HARD_REG_SET alloc_regs
;
3944 if (regno
>= FIRST_PSEUDO_REGISTER
)
3945 regno
= lra_get_regno_hard_regno (regno
);
3948 COMPL_HARD_REG_SET (alloc_regs
, lra_no_alloc_regs
);
3949 return overlaps_hard_reg_set_p (alloc_regs
, GET_MODE (x
), regno
);
3953 if (regno
< FIRST_PSEUDO_REGISTER
)
3957 return lra_get_regno_hard_regno (regno
) < 0;
3960 fmt
= GET_RTX_FORMAT (code
);
3961 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
3965 if (contains_reg_p (XEXP (x
, i
), hard_reg_p
, spilled_p
))
3968 else if (fmt
[i
] == 'E')
3970 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3971 if (contains_reg_p (XVECEXP (x
, i
, j
), hard_reg_p
, spilled_p
))
3978 /* Return true if X contains a symbol reg. */
3980 contains_symbol_ref_p (rtx x
)
3986 code
= GET_CODE (x
);
3987 if (code
== SYMBOL_REF
)
3989 fmt
= GET_RTX_FORMAT (code
);
3990 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
3994 if (contains_symbol_ref_p (XEXP (x
, i
)))
3997 else if (fmt
[i
] == 'E')
3999 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
4000 if (contains_symbol_ref_p (XVECEXP (x
, i
, j
)))
4007 /* Process all regs in location *LOC and change them on equivalent
4008 substitution. Return true if any change was done. */
4010 loc_equivalence_change_p (rtx
*loc
)
4012 rtx subst
, reg
, x
= *loc
;
4013 bool result
= false;
4014 enum rtx_code code
= GET_CODE (x
);
4020 reg
= SUBREG_REG (x
);
4021 if ((subst
= get_equiv_with_elimination (reg
, curr_insn
)) != reg
4022 && GET_MODE (subst
) == VOIDmode
)
4024 /* We cannot reload debug location. Simplify subreg here
4025 while we know the inner mode. */
4026 *loc
= simplify_gen_subreg (GET_MODE (x
), subst
,
4027 GET_MODE (reg
), SUBREG_BYTE (x
));
4031 if (code
== REG
&& (subst
= get_equiv_with_elimination (x
, curr_insn
)) != x
)
4037 /* Scan all the operand sub-expressions. */
4038 fmt
= GET_RTX_FORMAT (code
);
4039 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
4042 result
= loc_equivalence_change_p (&XEXP (x
, i
)) || result
;
4043 else if (fmt
[i
] == 'E')
4044 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
4046 = loc_equivalence_change_p (&XVECEXP (x
, i
, j
)) || result
;
4051 /* Similar to loc_equivalence_change_p, but for use as
4052 simplify_replace_fn_rtx callback. DATA is insn for which the
4053 elimination is done. If it null we don't do the elimination. */
4055 loc_equivalence_callback (rtx loc
, const_rtx
, void *data
)
4060 rtx subst
= (data
== NULL
4061 ? get_equiv (loc
) : get_equiv_with_elimination (loc
, (rtx_insn
*) data
));
4068 /* Maximum number of generated reload insns per an insn. It is for
4069 preventing this pass cycling in a bug case. */
4070 #define MAX_RELOAD_INSNS_NUMBER LRA_MAX_INSN_RELOADS
4072 /* The current iteration number of this LRA pass. */
4073 int lra_constraint_iter
;
4075 /* True if we substituted equiv which needs checking register
4076 allocation correctness because the equivalent value contains
4077 allocatable hard registers or when we restore multi-register
4079 bool lra_risky_transformations_p
;
4081 /* Return true if REGNO is referenced in more than one block. */
4083 multi_block_pseudo_p (int regno
)
4085 basic_block bb
= NULL
;
4089 if (regno
< FIRST_PSEUDO_REGISTER
)
4092 EXECUTE_IF_SET_IN_BITMAP (&lra_reg_info
[regno
].insn_bitmap
, 0, uid
, bi
)
4094 bb
= BLOCK_FOR_INSN (lra_insn_recog_data
[uid
]->insn
);
4095 else if (BLOCK_FOR_INSN (lra_insn_recog_data
[uid
]->insn
) != bb
)
4100 /* Return true if LIST contains a deleted insn. */
4102 contains_deleted_insn_p (rtx_insn_list
*list
)
4104 for (; list
!= NULL_RTX
; list
= list
->next ())
4105 if (NOTE_P (list
->insn ())
4106 && NOTE_KIND (list
->insn ()) == NOTE_INSN_DELETED
)
4111 /* Return true if X contains a pseudo dying in INSN. */
4113 dead_pseudo_p (rtx x
, rtx insn
)
4120 return (insn
!= NULL_RTX
4121 && find_regno_note (insn
, REG_DEAD
, REGNO (x
)) != NULL_RTX
);
4122 code
= GET_CODE (x
);
4123 fmt
= GET_RTX_FORMAT (code
);
4124 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
4128 if (dead_pseudo_p (XEXP (x
, i
), insn
))
4131 else if (fmt
[i
] == 'E')
4133 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
4134 if (dead_pseudo_p (XVECEXP (x
, i
, j
), insn
))
4141 /* Return true if INSN contains a dying pseudo in INSN right hand
4144 insn_rhs_dead_pseudo_p (rtx_insn
*insn
)
4146 rtx set
= single_set (insn
);
4148 gcc_assert (set
!= NULL
);
4149 return dead_pseudo_p (SET_SRC (set
), insn
);
4152 /* Return true if any init insn of REGNO contains a dying pseudo in
4153 insn right hand side. */
4155 init_insn_rhs_dead_pseudo_p (int regno
)
4157 rtx_insn_list
*insns
= ira_reg_equiv
[regno
].init_insns
;
4161 for (; insns
!= NULL_RTX
; insns
= insns
->next ())
4162 if (insn_rhs_dead_pseudo_p (insns
->insn ()))
4167 /* Return TRUE if REGNO has a reverse equivalence. The equivalence is
4168 reverse only if we have one init insn with given REGNO as a
4171 reverse_equiv_p (int regno
)
4173 rtx_insn_list
*insns
= ira_reg_equiv
[regno
].init_insns
;
4178 if (! INSN_P (insns
->insn ())
4179 || insns
->next () != NULL
)
4181 if ((set
= single_set (insns
->insn ())) == NULL_RTX
)
4183 return REG_P (SET_SRC (set
)) && (int) REGNO (SET_SRC (set
)) == regno
;
4186 /* Return TRUE if REGNO was reloaded in an equivalence init insn. We
4187 call this function only for non-reverse equivalence. */
4189 contains_reloaded_insn_p (int regno
)
4192 rtx_insn_list
*list
= ira_reg_equiv
[regno
].init_insns
;
4194 for (; list
!= NULL
; list
= list
->next ())
4195 if ((set
= single_set (list
->insn ())) == NULL_RTX
4196 || ! REG_P (SET_DEST (set
))
4197 || (int) REGNO (SET_DEST (set
)) != regno
)
4202 /* Entry function of LRA constraint pass. Return true if the
4203 constraint pass did change the code. */
4205 lra_constraints (bool first_p
)
4208 int i
, hard_regno
, new_insns_num
;
4209 unsigned int min_len
, new_min_len
, uid
;
4210 rtx set
, x
, reg
, dest_reg
;
4211 basic_block last_bb
;
4212 bitmap_head equiv_insn_bitmap
;
4215 lra_constraint_iter
++;
4216 if (lra_dump_file
!= NULL
)
4217 fprintf (lra_dump_file
, "\n********** Local #%d: **********\n\n",
4218 lra_constraint_iter
);
4220 if (pic_offset_table_rtx
4221 && REGNO (pic_offset_table_rtx
) >= FIRST_PSEUDO_REGISTER
)
4222 lra_risky_transformations_p
= true;
4224 lra_risky_transformations_p
= false;
4225 new_insn_uid_start
= get_max_uid ();
4226 new_regno_start
= first_p
? lra_constraint_new_regno_start
: max_reg_num ();
4227 /* Mark used hard regs for target stack size calulations. */
4228 for (i
= FIRST_PSEUDO_REGISTER
; i
< new_regno_start
; i
++)
4229 if (lra_reg_info
[i
].nrefs
!= 0
4230 && (hard_regno
= lra_get_regno_hard_regno (i
)) >= 0)
4234 nregs
= hard_regno_nregs
[hard_regno
][lra_reg_info
[i
].biggest_mode
];
4235 for (j
= 0; j
< nregs
; j
++)
4236 df_set_regs_ever_live (hard_regno
+ j
, true);
4238 /* Do elimination before the equivalence processing as we can spill
4239 some pseudos during elimination. */
4240 lra_eliminate (false, first_p
);
4241 bitmap_initialize (&equiv_insn_bitmap
, ®_obstack
);
4242 for (i
= FIRST_PSEUDO_REGISTER
; i
< new_regno_start
; i
++)
4243 if (lra_reg_info
[i
].nrefs
!= 0)
4245 ira_reg_equiv
[i
].profitable_p
= true;
4246 reg
= regno_reg_rtx
[i
];
4247 if (lra_get_regno_hard_regno (i
) < 0 && (x
= get_equiv (reg
)) != reg
)
4249 bool pseudo_p
= contains_reg_p (x
, false, false);
4251 /* After RTL transformation, we can not guarantee that
4252 pseudo in the substitution was not reloaded which might
4253 make equivalence invalid. For example, in reverse
4260 the memory address register was reloaded before the 2nd
4262 if ((! first_p
&& pseudo_p
)
4263 /* We don't use DF for compilation speed sake. So it
4264 is problematic to update live info when we use an
4265 equivalence containing pseudos in more than one
4267 || (pseudo_p
&& multi_block_pseudo_p (i
))
4268 /* If an init insn was deleted for some reason, cancel
4269 the equiv. We could update the equiv insns after
4270 transformations including an equiv insn deletion
4271 but it is not worthy as such cases are extremely
4273 || contains_deleted_insn_p (ira_reg_equiv
[i
].init_insns
)
4274 /* If it is not a reverse equivalence, we check that a
4275 pseudo in rhs of the init insn is not dying in the
4276 insn. Otherwise, the live info at the beginning of
4277 the corresponding BB might be wrong after we
4278 removed the insn. When the equiv can be a
4279 constant, the right hand side of the init insn can
4281 || (! reverse_equiv_p (i
)
4282 && (init_insn_rhs_dead_pseudo_p (i
)
4283 /* If we reloaded the pseudo in an equivalence
4284 init insn, we can not remove the equiv init
4285 insns and the init insns might write into
4286 const memory in this case. */
4287 || contains_reloaded_insn_p (i
)))
4288 /* Prevent access beyond equivalent memory for
4289 paradoxical subregs. */
4291 && (GET_MODE_SIZE (lra_reg_info
[i
].biggest_mode
)
4292 > GET_MODE_SIZE (GET_MODE (x
))))
4293 || (pic_offset_table_rtx
4294 && ((CONST_POOL_OK_P (PSEUDO_REGNO_MODE (i
), x
)
4295 && (targetm
.preferred_reload_class
4296 (x
, lra_get_allocno_class (i
)) == NO_REGS
))
4297 || contains_symbol_ref_p (x
))))
4298 ira_reg_equiv
[i
].defined_p
= false;
4299 if (contains_reg_p (x
, false, true))
4300 ira_reg_equiv
[i
].profitable_p
= false;
4301 if (get_equiv (reg
) != reg
)
4302 bitmap_ior_into (&equiv_insn_bitmap
, &lra_reg_info
[i
].insn_bitmap
);
4305 for (i
= FIRST_PSEUDO_REGISTER
; i
< new_regno_start
; i
++)
4307 /* We should add all insns containing pseudos which should be
4308 substituted by their equivalences. */
4309 EXECUTE_IF_SET_IN_BITMAP (&equiv_insn_bitmap
, 0, uid
, bi
)
4310 lra_push_insn_by_uid (uid
);
4311 min_len
= lra_insn_stack_length ();
4315 while ((new_min_len
= lra_insn_stack_length ()) != 0)
4317 curr_insn
= lra_pop_insn ();
4319 curr_bb
= BLOCK_FOR_INSN (curr_insn
);
4320 if (curr_bb
!= last_bb
)
4323 bb_reload_num
= lra_curr_reload_num
;
4325 if (min_len
> new_min_len
)
4327 min_len
= new_min_len
;
4330 if (new_insns_num
> MAX_RELOAD_INSNS_NUMBER
)
4332 ("Max. number of generated reload insns per insn is achieved (%d)\n",
4333 MAX_RELOAD_INSNS_NUMBER
);
4335 if (DEBUG_INSN_P (curr_insn
))
4337 /* We need to check equivalence in debug insn and change
4338 pseudo to the equivalent value if necessary. */
4339 curr_id
= lra_get_insn_recog_data (curr_insn
);
4340 if (bitmap_bit_p (&equiv_insn_bitmap
, INSN_UID (curr_insn
)))
4342 rtx old
= *curr_id
->operand_loc
[0];
4343 *curr_id
->operand_loc
[0]
4344 = simplify_replace_fn_rtx (old
, NULL_RTX
,
4345 loc_equivalence_callback
, curr_insn
);
4346 if (old
!= *curr_id
->operand_loc
[0])
4348 lra_update_insn_regno_info (curr_insn
);
4353 else if (INSN_P (curr_insn
))
4355 if ((set
= single_set (curr_insn
)) != NULL_RTX
)
4357 dest_reg
= SET_DEST (set
);
4358 /* The equivalence pseudo could be set up as SUBREG in a
4359 case when it is a call restore insn in a mode
4360 different from the pseudo mode. */
4361 if (GET_CODE (dest_reg
) == SUBREG
)
4362 dest_reg
= SUBREG_REG (dest_reg
);
4363 if ((REG_P (dest_reg
)
4364 && (x
= get_equiv (dest_reg
)) != dest_reg
4365 /* Remove insns which set up a pseudo whose value
4366 can not be changed. Such insns might be not in
4367 init_insns because we don't update equiv data
4368 during insn transformations.
4370 As an example, let suppose that a pseudo got
4371 hard register and on the 1st pass was not
4372 changed to equivalent constant. We generate an
4373 additional insn setting up the pseudo because of
4374 secondary memory movement. Then the pseudo is
4375 spilled and we use the equiv constant. In this
4376 case we should remove the additional insn and
4377 this insn is not init_insns list. */
4378 && (! MEM_P (x
) || MEM_READONLY_P (x
)
4379 /* Check that this is actually an insn setting
4380 up the equivalence. */
4381 || in_list_p (curr_insn
,
4383 [REGNO (dest_reg
)].init_insns
)))
4384 || (((x
= get_equiv (SET_SRC (set
))) != SET_SRC (set
))
4385 && in_list_p (curr_insn
,
4387 [REGNO (SET_SRC (set
))].init_insns
)))
4389 /* This is equiv init insn of pseudo which did not get a
4390 hard register -- remove the insn. */
4391 if (lra_dump_file
!= NULL
)
4393 fprintf (lra_dump_file
,
4394 " Removing equiv init insn %i (freq=%d)\n",
4395 INSN_UID (curr_insn
),
4396 REG_FREQ_FROM_BB (BLOCK_FOR_INSN (curr_insn
)));
4397 dump_insn_slim (lra_dump_file
, curr_insn
);
4399 if (contains_reg_p (x
, true, false))
4400 lra_risky_transformations_p
= true;
4401 lra_set_insn_deleted (curr_insn
);
4405 curr_id
= lra_get_insn_recog_data (curr_insn
);
4406 curr_static_id
= curr_id
->insn_static_data
;
4407 init_curr_insn_input_reloads ();
4408 init_curr_operand_mode ();
4409 if (curr_insn_transform (false))
4411 /* Check non-transformed insns too for equiv change as USE
4412 or CLOBBER don't need reloads but can contain pseudos
4413 being changed on their equivalences. */
4414 else if (bitmap_bit_p (&equiv_insn_bitmap
, INSN_UID (curr_insn
))
4415 && loc_equivalence_change_p (&PATTERN (curr_insn
)))
4417 lra_update_insn_regno_info (curr_insn
);
4422 bitmap_clear (&equiv_insn_bitmap
);
4423 /* If we used a new hard regno, changed_p should be true because the
4424 hard reg is assigned to a new pseudo. */
4425 #ifdef ENABLE_CHECKING
4428 for (i
= FIRST_PSEUDO_REGISTER
; i
< new_regno_start
; i
++)
4429 if (lra_reg_info
[i
].nrefs
!= 0
4430 && (hard_regno
= lra_get_regno_hard_regno (i
)) >= 0)
4432 int j
, nregs
= hard_regno_nregs
[hard_regno
][PSEUDO_REGNO_MODE (i
)];
4434 for (j
= 0; j
< nregs
; j
++)
4435 lra_assert (df_regs_ever_live_p (hard_regno
+ j
));
4442 /* Initiate the LRA constraint pass. It is done once per
4445 lra_constraints_init (void)
4449 /* Finalize the LRA constraint pass. It is done once per
4452 lra_constraints_finish (void)
4458 /* This page contains code to do inheritance/split
4461 /* Number of reloads passed so far in current EBB. */
4462 static int reloads_num
;
4464 /* Number of calls passed so far in current EBB. */
4465 static int calls_num
;
4467 /* Current reload pseudo check for validity of elements in
4469 static int curr_usage_insns_check
;
4471 /* Info about last usage of registers in EBB to do inheritance/split
4472 transformation. Inheritance transformation is done from a spilled
4473 pseudo and split transformations from a hard register or a pseudo
4474 assigned to a hard register. */
4477 /* If the value is equal to CURR_USAGE_INSNS_CHECK, then the member
4478 value INSNS is valid. The insns is chain of optional debug insns
4479 and a finishing non-debug insn using the corresponding reg. The
4480 value is also used to mark the registers which are set up in the
4481 current insn. The negated insn uid is used for this. */
4483 /* Value of global reloads_num at the last insn in INSNS. */
4485 /* Value of global reloads_nums at the last insn in INSNS. */
4487 /* It can be true only for splitting. And it means that the restore
4488 insn should be put after insn given by the following member. */
4490 /* Next insns in the current EBB which use the original reg and the
4491 original reg value is not changed between the current insn and
4492 the next insns. In order words, e.g. for inheritance, if we need
4493 to use the original reg value again in the next insns we can try
4494 to use the value in a hard register from a reload insn of the
4499 /* Map: regno -> corresponding pseudo usage insns. */
4500 static struct usage_insns
*usage_insns
;
4503 setup_next_usage_insn (int regno
, rtx insn
, int reloads_num
, bool after_p
)
4505 usage_insns
[regno
].check
= curr_usage_insns_check
;
4506 usage_insns
[regno
].insns
= insn
;
4507 usage_insns
[regno
].reloads_num
= reloads_num
;
4508 usage_insns
[regno
].calls_num
= calls_num
;
4509 usage_insns
[regno
].after_p
= after_p
;
4512 /* The function is used to form list REGNO usages which consists of
4513 optional debug insns finished by a non-debug insn using REGNO.
4514 RELOADS_NUM is current number of reload insns processed so far. */
4516 add_next_usage_insn (int regno
, rtx insn
, int reloads_num
)
4518 rtx next_usage_insns
;
4520 if (usage_insns
[regno
].check
== curr_usage_insns_check
4521 && (next_usage_insns
= usage_insns
[regno
].insns
) != NULL_RTX
4522 && DEBUG_INSN_P (insn
))
4524 /* Check that we did not add the debug insn yet. */
4525 if (next_usage_insns
!= insn
4526 && (GET_CODE (next_usage_insns
) != INSN_LIST
4527 || XEXP (next_usage_insns
, 0) != insn
))
4528 usage_insns
[regno
].insns
= gen_rtx_INSN_LIST (VOIDmode
, insn
,
4531 else if (NONDEBUG_INSN_P (insn
))
4532 setup_next_usage_insn (regno
, insn
, reloads_num
, false);
4534 usage_insns
[regno
].check
= 0;
4537 /* Return first non-debug insn in list USAGE_INSNS. */
4539 skip_usage_debug_insns (rtx usage_insns
)
4543 /* Skip debug insns. */
4544 for (insn
= usage_insns
;
4545 insn
!= NULL_RTX
&& GET_CODE (insn
) == INSN_LIST
;
4546 insn
= XEXP (insn
, 1))
4548 return safe_as_a
<rtx_insn
*> (insn
);
4551 /* Return true if we need secondary memory moves for insn in
4552 USAGE_INSNS after inserting inherited pseudo of class INHER_CL
4555 check_secondary_memory_needed_p (enum reg_class inher_cl ATTRIBUTE_UNUSED
,
4556 rtx usage_insns ATTRIBUTE_UNUSED
)
4558 #ifndef SECONDARY_MEMORY_NEEDED
4565 if (inher_cl
== ALL_REGS
4566 || (insn
= skip_usage_debug_insns (usage_insns
)) == NULL_RTX
)
4568 lra_assert (INSN_P (insn
));
4569 if ((set
= single_set (insn
)) == NULL_RTX
|| ! REG_P (SET_DEST (set
)))
4571 dest
= SET_DEST (set
);
4574 lra_assert (inher_cl
!= NO_REGS
);
4575 cl
= get_reg_class (REGNO (dest
));
4576 return (cl
!= NO_REGS
&& cl
!= ALL_REGS
4577 && SECONDARY_MEMORY_NEEDED (inher_cl
, cl
, GET_MODE (dest
)));
4581 /* Registers involved in inheritance/split in the current EBB
4582 (inheritance/split pseudos and original registers). */
4583 static bitmap_head check_only_regs
;
4585 /* Do inheritance transformations for insn INSN, which defines (if
4586 DEF_P) or uses ORIGINAL_REGNO. NEXT_USAGE_INSNS specifies which
4587 instruction in the EBB next uses ORIGINAL_REGNO; it has the same
4588 form as the "insns" field of usage_insns. Return true if we
4589 succeed in such transformation.
4591 The transformations look like:
4594 ... p <- i (new insn)
4596 <- ... p ... <- ... i ...
4598 ... i <- p (new insn)
4599 <- ... p ... <- ... i ...
4601 <- ... p ... <- ... i ...
4602 where p is a spilled original pseudo and i is a new inheritance pseudo.
4605 The inheritance pseudo has the smallest class of two classes CL and
4606 class of ORIGINAL REGNO. */
4608 inherit_reload_reg (bool def_p
, int original_regno
,
4609 enum reg_class cl
, rtx_insn
*insn
, rtx next_usage_insns
)
4611 if (optimize_function_for_size_p (cfun
))
4614 enum reg_class rclass
= lra_get_allocno_class (original_regno
);
4615 rtx original_reg
= regno_reg_rtx
[original_regno
];
4616 rtx new_reg
, usage_insn
;
4617 rtx_insn
*new_insns
;
4619 lra_assert (! usage_insns
[original_regno
].after_p
);
4620 if (lra_dump_file
!= NULL
)
4621 fprintf (lra_dump_file
,
4622 " <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<\n");
4623 if (! ira_reg_classes_intersect_p
[cl
][rclass
])
4625 if (lra_dump_file
!= NULL
)
4627 fprintf (lra_dump_file
,
4628 " Rejecting inheritance for %d "
4629 "because of disjoint classes %s and %s\n",
4630 original_regno
, reg_class_names
[cl
],
4631 reg_class_names
[rclass
]);
4632 fprintf (lra_dump_file
,
4633 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
4637 if ((ira_class_subset_p
[cl
][rclass
] && cl
!= rclass
)
4638 /* We don't use a subset of two classes because it can be
4639 NO_REGS. This transformation is still profitable in most
4640 cases even if the classes are not intersected as register
4641 move is probably cheaper than a memory load. */
4642 || ira_class_hard_regs_num
[cl
] < ira_class_hard_regs_num
[rclass
])
4644 if (lra_dump_file
!= NULL
)
4645 fprintf (lra_dump_file
, " Use smallest class of %s and %s\n",
4646 reg_class_names
[cl
], reg_class_names
[rclass
]);
4650 if (check_secondary_memory_needed_p (rclass
, next_usage_insns
))
4652 /* Reject inheritance resulting in secondary memory moves.
4653 Otherwise, there is a danger in LRA cycling. Also such
4654 transformation will be unprofitable. */
4655 if (lra_dump_file
!= NULL
)
4657 rtx_insn
*insn
= skip_usage_debug_insns (next_usage_insns
);
4658 rtx set
= single_set (insn
);
4660 lra_assert (set
!= NULL_RTX
);
4662 rtx dest
= SET_DEST (set
);
4664 lra_assert (REG_P (dest
));
4665 fprintf (lra_dump_file
,
4666 " Rejecting inheritance for insn %d(%s)<-%d(%s) "
4667 "as secondary mem is needed\n",
4668 REGNO (dest
), reg_class_names
[get_reg_class (REGNO (dest
))],
4669 original_regno
, reg_class_names
[rclass
]);
4670 fprintf (lra_dump_file
,
4671 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
4675 new_reg
= lra_create_new_reg (GET_MODE (original_reg
), original_reg
,
4676 rclass
, "inheritance");
4679 lra_emit_move (original_reg
, new_reg
);
4681 lra_emit_move (new_reg
, original_reg
);
4682 new_insns
= get_insns ();
4684 if (NEXT_INSN (new_insns
) != NULL_RTX
)
4686 if (lra_dump_file
!= NULL
)
4688 fprintf (lra_dump_file
,
4689 " Rejecting inheritance %d->%d "
4690 "as it results in 2 or more insns:\n",
4691 original_regno
, REGNO (new_reg
));
4692 dump_rtl_slim (lra_dump_file
, new_insns
, NULL
, -1, 0);
4693 fprintf (lra_dump_file
,
4694 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
4698 lra_substitute_pseudo_within_insn (insn
, original_regno
, new_reg
);
4699 lra_update_insn_regno_info (insn
);
4701 /* We now have a new usage insn for original regno. */
4702 setup_next_usage_insn (original_regno
, new_insns
, reloads_num
, false);
4703 if (lra_dump_file
!= NULL
)
4704 fprintf (lra_dump_file
, " Original reg change %d->%d (bb%d):\n",
4705 original_regno
, REGNO (new_reg
), BLOCK_FOR_INSN (insn
)->index
);
4706 lra_reg_info
[REGNO (new_reg
)].restore_regno
= original_regno
;
4707 bitmap_set_bit (&check_only_regs
, REGNO (new_reg
));
4708 bitmap_set_bit (&check_only_regs
, original_regno
);
4709 bitmap_set_bit (&lra_inheritance_pseudos
, REGNO (new_reg
));
4711 lra_process_new_insns (insn
, NULL
, new_insns
,
4712 "Add original<-inheritance");
4714 lra_process_new_insns (insn
, new_insns
, NULL
,
4715 "Add inheritance<-original");
4716 while (next_usage_insns
!= NULL_RTX
)
4718 if (GET_CODE (next_usage_insns
) != INSN_LIST
)
4720 usage_insn
= next_usage_insns
;
4721 lra_assert (NONDEBUG_INSN_P (usage_insn
));
4722 next_usage_insns
= NULL
;
4726 usage_insn
= XEXP (next_usage_insns
, 0);
4727 lra_assert (DEBUG_INSN_P (usage_insn
));
4728 next_usage_insns
= XEXP (next_usage_insns
, 1);
4730 lra_substitute_pseudo (&usage_insn
, original_regno
, new_reg
);
4731 lra_update_insn_regno_info (as_a
<rtx_insn
*> (usage_insn
));
4732 if (lra_dump_file
!= NULL
)
4734 fprintf (lra_dump_file
,
4735 " Inheritance reuse change %d->%d (bb%d):\n",
4736 original_regno
, REGNO (new_reg
),
4737 BLOCK_FOR_INSN (usage_insn
)->index
);
4738 dump_insn_slim (lra_dump_file
, usage_insn
);
4741 if (lra_dump_file
!= NULL
)
4742 fprintf (lra_dump_file
,
4743 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
4747 /* Return true if we need a caller save/restore for pseudo REGNO which
4748 was assigned to a hard register. */
4750 need_for_call_save_p (int regno
)
4752 lra_assert (regno
>= FIRST_PSEUDO_REGISTER
&& reg_renumber
[regno
] >= 0);
4753 return (usage_insns
[regno
].calls_num
< calls_num
4754 && (overlaps_hard_reg_set_p
4756 ! hard_reg_set_empty_p (lra_reg_info
[regno
].actual_call_used_reg_set
))
4757 ? lra_reg_info
[regno
].actual_call_used_reg_set
4758 : call_used_reg_set
,
4759 PSEUDO_REGNO_MODE (regno
), reg_renumber
[regno
])
4760 || HARD_REGNO_CALL_PART_CLOBBERED (reg_renumber
[regno
],
4761 PSEUDO_REGNO_MODE (regno
))));
4764 /* Global registers occurring in the current EBB. */
4765 static bitmap_head ebb_global_regs
;
4767 /* Return true if we need a split for hard register REGNO or pseudo
4768 REGNO which was assigned to a hard register.
4769 POTENTIAL_RELOAD_HARD_REGS contains hard registers which might be
4770 used for reloads since the EBB end. It is an approximation of the
4771 used hard registers in the split range. The exact value would
4772 require expensive calculations. If we were aggressive with
4773 splitting because of the approximation, the split pseudo will save
4774 the same hard register assignment and will be removed in the undo
4775 pass. We still need the approximation because too aggressive
4776 splitting would result in too inaccurate cost calculation in the
4777 assignment pass because of too many generated moves which will be
4778 probably removed in the undo pass. */
4780 need_for_split_p (HARD_REG_SET potential_reload_hard_regs
, int regno
)
4782 int hard_regno
= regno
< FIRST_PSEUDO_REGISTER
? regno
: reg_renumber
[regno
];
4784 lra_assert (hard_regno
>= 0);
4785 return ((TEST_HARD_REG_BIT (potential_reload_hard_regs
, hard_regno
)
4786 /* Don't split eliminable hard registers, otherwise we can
4787 split hard registers like hard frame pointer, which
4788 lives on BB start/end according to DF-infrastructure,
4789 when there is a pseudo assigned to the register and
4790 living in the same BB. */
4791 && (regno
>= FIRST_PSEUDO_REGISTER
4792 || ! TEST_HARD_REG_BIT (eliminable_regset
, hard_regno
))
4793 && ! TEST_HARD_REG_BIT (lra_no_alloc_regs
, hard_regno
)
4794 /* Don't split call clobbered hard regs living through
4795 calls, otherwise we might have a check problem in the
4796 assign sub-pass as in the most cases (exception is a
4797 situation when lra_risky_transformations_p value is
4798 true) the assign pass assumes that all pseudos living
4799 through calls are assigned to call saved hard regs. */
4800 && (regno
>= FIRST_PSEUDO_REGISTER
4801 || ! TEST_HARD_REG_BIT (call_used_reg_set
, regno
)
4802 || usage_insns
[regno
].calls_num
== calls_num
)
4803 /* We need at least 2 reloads to make pseudo splitting
4804 profitable. We should provide hard regno splitting in
4805 any case to solve 1st insn scheduling problem when
4806 moving hard register definition up might result in
4807 impossibility to find hard register for reload pseudo of
4808 small register class. */
4809 && (usage_insns
[regno
].reloads_num
4810 + (regno
< FIRST_PSEUDO_REGISTER
? 0 : 3) < reloads_num
)
4811 && (regno
< FIRST_PSEUDO_REGISTER
4812 /* For short living pseudos, spilling + inheritance can
4813 be considered a substitution for splitting.
4814 Therefore we do not splitting for local pseudos. It
4815 decreases also aggressiveness of splitting. The
4816 minimal number of references is chosen taking into
4817 account that for 2 references splitting has no sense
4818 as we can just spill the pseudo. */
4819 || (regno
>= FIRST_PSEUDO_REGISTER
4820 && lra_reg_info
[regno
].nrefs
> 3
4821 && bitmap_bit_p (&ebb_global_regs
, regno
))))
4822 || (regno
>= FIRST_PSEUDO_REGISTER
&& need_for_call_save_p (regno
)));
4825 /* Return class for the split pseudo created from original pseudo with
4826 ALLOCNO_CLASS and MODE which got a hard register HARD_REGNO. We
4827 choose subclass of ALLOCNO_CLASS which contains HARD_REGNO and
4828 results in no secondary memory movements. */
4829 static enum reg_class
4830 choose_split_class (enum reg_class allocno_class
,
4831 int hard_regno ATTRIBUTE_UNUSED
,
4832 machine_mode mode ATTRIBUTE_UNUSED
)
4834 #ifndef SECONDARY_MEMORY_NEEDED
4835 return allocno_class
;
4838 enum reg_class cl
, best_cl
= NO_REGS
;
4839 enum reg_class hard_reg_class ATTRIBUTE_UNUSED
4840 = REGNO_REG_CLASS (hard_regno
);
4842 if (! SECONDARY_MEMORY_NEEDED (allocno_class
, allocno_class
, mode
)
4843 && TEST_HARD_REG_BIT (reg_class_contents
[allocno_class
], hard_regno
))
4844 return allocno_class
;
4846 (cl
= reg_class_subclasses
[allocno_class
][i
]) != LIM_REG_CLASSES
;
4848 if (! SECONDARY_MEMORY_NEEDED (cl
, hard_reg_class
, mode
)
4849 && ! SECONDARY_MEMORY_NEEDED (hard_reg_class
, cl
, mode
)
4850 && TEST_HARD_REG_BIT (reg_class_contents
[cl
], hard_regno
)
4851 && (best_cl
== NO_REGS
4852 || ira_class_hard_regs_num
[best_cl
] < ira_class_hard_regs_num
[cl
]))
4858 /* Do split transformations for insn INSN, which defines or uses
4859 ORIGINAL_REGNO. NEXT_USAGE_INSNS specifies which instruction in
4860 the EBB next uses ORIGINAL_REGNO; it has the same form as the
4861 "insns" field of usage_insns.
4863 The transformations look like:
4866 ... s <- p (new insn -- save)
4868 ... p <- s (new insn -- restore)
4869 <- ... p ... <- ... p ...
4871 <- ... p ... <- ... p ...
4872 ... s <- p (new insn -- save)
4874 ... p <- s (new insn -- restore)
4875 <- ... p ... <- ... p ...
4877 where p is an original pseudo got a hard register or a hard
4878 register and s is a new split pseudo. The save is put before INSN
4879 if BEFORE_P is true. Return true if we succeed in such
4882 split_reg (bool before_p
, int original_regno
, rtx_insn
*insn
,
4883 rtx next_usage_insns
)
4885 enum reg_class rclass
;
4887 int hard_regno
, nregs
;
4888 rtx new_reg
, usage_insn
;
4889 rtx_insn
*restore
, *save
;
4893 if (original_regno
< FIRST_PSEUDO_REGISTER
)
4895 rclass
= ira_allocno_class_translate
[REGNO_REG_CLASS (original_regno
)];
4896 hard_regno
= original_regno
;
4897 call_save_p
= false;
4902 hard_regno
= reg_renumber
[original_regno
];
4903 nregs
= hard_regno_nregs
[hard_regno
][PSEUDO_REGNO_MODE (original_regno
)];
4904 rclass
= lra_get_allocno_class (original_regno
);
4905 original_reg
= regno_reg_rtx
[original_regno
];
4906 call_save_p
= need_for_call_save_p (original_regno
);
4908 original_reg
= regno_reg_rtx
[original_regno
];
4909 lra_assert (hard_regno
>= 0);
4910 if (lra_dump_file
!= NULL
)
4911 fprintf (lra_dump_file
,
4912 " ((((((((((((((((((((((((((((((((((((((((((((((((\n");
4915 machine_mode mode
= GET_MODE (original_reg
);
4917 mode
= HARD_REGNO_CALLER_SAVE_MODE (hard_regno
,
4918 hard_regno_nregs
[hard_regno
][mode
],
4920 new_reg
= lra_create_new_reg (mode
, NULL_RTX
, NO_REGS
, "save");
4924 rclass
= choose_split_class (rclass
, hard_regno
,
4925 GET_MODE (original_reg
));
4926 if (rclass
== NO_REGS
)
4928 if (lra_dump_file
!= NULL
)
4930 fprintf (lra_dump_file
,
4931 " Rejecting split of %d(%s): "
4932 "no good reg class for %d(%s)\n",
4934 reg_class_names
[lra_get_allocno_class (original_regno
)],
4936 reg_class_names
[REGNO_REG_CLASS (hard_regno
)]);
4939 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
4943 new_reg
= lra_create_new_reg (GET_MODE (original_reg
), original_reg
,
4945 reg_renumber
[REGNO (new_reg
)] = hard_regno
;
4947 save
= emit_spill_move (true, new_reg
, original_reg
);
4948 if (NEXT_INSN (save
) != NULL_RTX
&& !call_save_p
)
4950 if (lra_dump_file
!= NULL
)
4954 " Rejecting split %d->%d resulting in > 2 save insns:\n",
4955 original_regno
, REGNO (new_reg
));
4956 dump_rtl_slim (lra_dump_file
, save
, NULL
, -1, 0);
4957 fprintf (lra_dump_file
,
4958 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
4962 restore
= emit_spill_move (false, new_reg
, original_reg
);
4963 if (NEXT_INSN (restore
) != NULL_RTX
&& !call_save_p
)
4965 if (lra_dump_file
!= NULL
)
4967 fprintf (lra_dump_file
,
4968 " Rejecting split %d->%d "
4969 "resulting in > 2 restore insns:\n",
4970 original_regno
, REGNO (new_reg
));
4971 dump_rtl_slim (lra_dump_file
, restore
, NULL
, -1, 0);
4972 fprintf (lra_dump_file
,
4973 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
4977 after_p
= usage_insns
[original_regno
].after_p
;
4978 lra_reg_info
[REGNO (new_reg
)].restore_regno
= original_regno
;
4979 bitmap_set_bit (&check_only_regs
, REGNO (new_reg
));
4980 bitmap_set_bit (&check_only_regs
, original_regno
);
4981 bitmap_set_bit (&lra_split_regs
, REGNO (new_reg
));
4984 if (GET_CODE (next_usage_insns
) != INSN_LIST
)
4986 usage_insn
= next_usage_insns
;
4989 usage_insn
= XEXP (next_usage_insns
, 0);
4990 lra_assert (DEBUG_INSN_P (usage_insn
));
4991 next_usage_insns
= XEXP (next_usage_insns
, 1);
4992 lra_substitute_pseudo (&usage_insn
, original_regno
, new_reg
);
4993 lra_update_insn_regno_info (as_a
<rtx_insn
*> (usage_insn
));
4994 if (lra_dump_file
!= NULL
)
4996 fprintf (lra_dump_file
, " Split reuse change %d->%d:\n",
4997 original_regno
, REGNO (new_reg
));
4998 dump_insn_slim (lra_dump_file
, usage_insn
);
5001 lra_assert (NOTE_P (usage_insn
) || NONDEBUG_INSN_P (usage_insn
));
5002 lra_assert (usage_insn
!= insn
|| (after_p
&& before_p
));
5003 lra_process_new_insns (as_a
<rtx_insn
*> (usage_insn
),
5004 after_p
? NULL
: restore
,
5005 after_p
? restore
: NULL
,
5007 ? "Add reg<-save" : "Add reg<-split");
5008 lra_process_new_insns (insn
, before_p
? save
: NULL
,
5009 before_p
? NULL
: save
,
5011 ? "Add save<-reg" : "Add split<-reg");
5013 /* If we are trying to split multi-register. We should check
5014 conflicts on the next assignment sub-pass. IRA can allocate on
5015 sub-register levels, LRA do this on pseudos level right now and
5016 this discrepancy may create allocation conflicts after
5018 lra_risky_transformations_p
= true;
5019 if (lra_dump_file
!= NULL
)
5020 fprintf (lra_dump_file
,
5021 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
5025 /* Recognize that we need a split transformation for insn INSN, which
5026 defines or uses REGNO in its insn biggest MODE (we use it only if
5027 REGNO is a hard register). POTENTIAL_RELOAD_HARD_REGS contains
5028 hard registers which might be used for reloads since the EBB end.
5029 Put the save before INSN if BEFORE_P is true. MAX_UID is maximla
5030 uid before starting INSN processing. Return true if we succeed in
5031 such transformation. */
5033 split_if_necessary (int regno
, machine_mode mode
,
5034 HARD_REG_SET potential_reload_hard_regs
,
5035 bool before_p
, rtx_insn
*insn
, int max_uid
)
5039 rtx next_usage_insns
;
5041 if (regno
< FIRST_PSEUDO_REGISTER
)
5042 nregs
= hard_regno_nregs
[regno
][mode
];
5043 for (i
= 0; i
< nregs
; i
++)
5044 if (usage_insns
[regno
+ i
].check
== curr_usage_insns_check
5045 && (next_usage_insns
= usage_insns
[regno
+ i
].insns
) != NULL_RTX
5046 /* To avoid processing the register twice or more. */
5047 && ((GET_CODE (next_usage_insns
) != INSN_LIST
5048 && INSN_UID (next_usage_insns
) < max_uid
)
5049 || (GET_CODE (next_usage_insns
) == INSN_LIST
5050 && (INSN_UID (XEXP (next_usage_insns
, 0)) < max_uid
)))
5051 && need_for_split_p (potential_reload_hard_regs
, regno
+ i
)
5052 && split_reg (before_p
, regno
+ i
, insn
, next_usage_insns
))
5057 /* Check only registers living at the current program point in the
5059 static bitmap_head live_regs
;
5061 /* Update live info in EBB given by its HEAD and TAIL insns after
5062 inheritance/split transformation. The function removes dead moves
5065 update_ebb_live_info (rtx_insn
*head
, rtx_insn
*tail
)
5070 rtx_insn
*prev_insn
;
5073 basic_block last_bb
, prev_bb
, curr_bb
;
5075 struct lra_insn_reg
*reg
;
5079 last_bb
= BLOCK_FOR_INSN (tail
);
5081 for (curr_insn
= tail
;
5082 curr_insn
!= PREV_INSN (head
);
5083 curr_insn
= prev_insn
)
5085 prev_insn
= PREV_INSN (curr_insn
);
5086 /* We need to process empty blocks too. They contain
5087 NOTE_INSN_BASIC_BLOCK referring for the basic block. */
5088 if (NOTE_P (curr_insn
) && NOTE_KIND (curr_insn
) != NOTE_INSN_BASIC_BLOCK
)
5090 curr_bb
= BLOCK_FOR_INSN (curr_insn
);
5091 if (curr_bb
!= prev_bb
)
5093 if (prev_bb
!= NULL
)
5095 /* Update df_get_live_in (prev_bb): */
5096 EXECUTE_IF_SET_IN_BITMAP (&check_only_regs
, 0, j
, bi
)
5097 if (bitmap_bit_p (&live_regs
, j
))
5098 bitmap_set_bit (df_get_live_in (prev_bb
), j
);
5100 bitmap_clear_bit (df_get_live_in (prev_bb
), j
);
5102 if (curr_bb
!= last_bb
)
5104 /* Update df_get_live_out (curr_bb): */
5105 EXECUTE_IF_SET_IN_BITMAP (&check_only_regs
, 0, j
, bi
)
5107 live_p
= bitmap_bit_p (&live_regs
, j
);
5109 FOR_EACH_EDGE (e
, ei
, curr_bb
->succs
)
5110 if (bitmap_bit_p (df_get_live_in (e
->dest
), j
))
5116 bitmap_set_bit (df_get_live_out (curr_bb
), j
);
5118 bitmap_clear_bit (df_get_live_out (curr_bb
), j
);
5122 bitmap_and (&live_regs
, &check_only_regs
, df_get_live_out (curr_bb
));
5124 if (! NONDEBUG_INSN_P (curr_insn
))
5126 curr_id
= lra_get_insn_recog_data (curr_insn
);
5127 curr_static_id
= curr_id
->insn_static_data
;
5129 if ((set
= single_set (curr_insn
)) != NULL_RTX
&& REG_P (SET_DEST (set
))
5130 && (regno
= REGNO (SET_DEST (set
))) >= FIRST_PSEUDO_REGISTER
5131 && bitmap_bit_p (&check_only_regs
, regno
)
5132 && ! bitmap_bit_p (&live_regs
, regno
))
5134 /* See which defined values die here. */
5135 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
5136 if (reg
->type
== OP_OUT
&& ! reg
->subreg_p
)
5137 bitmap_clear_bit (&live_regs
, reg
->regno
);
5138 for (reg
= curr_static_id
->hard_regs
; reg
!= NULL
; reg
= reg
->next
)
5139 if (reg
->type
== OP_OUT
&& ! reg
->subreg_p
)
5140 bitmap_clear_bit (&live_regs
, reg
->regno
);
5141 /* Mark each used value as live. */
5142 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
5143 if (reg
->type
!= OP_OUT
5144 && bitmap_bit_p (&check_only_regs
, reg
->regno
))
5145 bitmap_set_bit (&live_regs
, reg
->regno
);
5146 for (reg
= curr_static_id
->hard_regs
; reg
!= NULL
; reg
= reg
->next
)
5147 if (reg
->type
!= OP_OUT
5148 && bitmap_bit_p (&check_only_regs
, reg
->regno
))
5149 bitmap_set_bit (&live_regs
, reg
->regno
);
5150 if (curr_id
->arg_hard_regs
!= NULL
)
5151 /* Make argument hard registers live. */
5152 for (i
= 0; (regno
= curr_id
->arg_hard_regs
[i
]) >= 0; i
++)
5153 if (bitmap_bit_p (&check_only_regs
, regno
))
5154 bitmap_set_bit (&live_regs
, regno
);
5155 /* It is quite important to remove dead move insns because it
5156 means removing dead store. We don't need to process them for
5160 if (lra_dump_file
!= NULL
)
5162 fprintf (lra_dump_file
, " Removing dead insn:\n ");
5163 dump_insn_slim (lra_dump_file
, curr_insn
);
5165 lra_set_insn_deleted (curr_insn
);
5170 /* The structure describes info to do an inheritance for the current
5171 insn. We need to collect such info first before doing the
5172 transformations because the transformations change the insn
5173 internal representation. */
5176 /* Original regno. */
5178 /* Subsequent insns which can inherit original reg value. */
5182 /* Array containing all info for doing inheritance from the current
5184 static struct to_inherit to_inherit
[LRA_MAX_INSN_RELOADS
];
5186 /* Number elements in the previous array. */
5187 static int to_inherit_num
;
5189 /* Add inheritance info REGNO and INSNS. Their meaning is described in
5190 structure to_inherit. */
5192 add_to_inherit (int regno
, rtx insns
)
5196 for (i
= 0; i
< to_inherit_num
; i
++)
5197 if (to_inherit
[i
].regno
== regno
)
5199 lra_assert (to_inherit_num
< LRA_MAX_INSN_RELOADS
);
5200 to_inherit
[to_inherit_num
].regno
= regno
;
5201 to_inherit
[to_inherit_num
++].insns
= insns
;
5204 /* Return the last non-debug insn in basic block BB, or the block begin
5207 get_last_insertion_point (basic_block bb
)
5211 FOR_BB_INSNS_REVERSE (bb
, insn
)
5212 if (NONDEBUG_INSN_P (insn
) || NOTE_INSN_BASIC_BLOCK_P (insn
))
5217 /* Set up RES by registers living on edges FROM except the edge (FROM,
5218 TO) or by registers set up in a jump insn in BB FROM. */
5220 get_live_on_other_edges (basic_block from
, basic_block to
, bitmap res
)
5223 struct lra_insn_reg
*reg
;
5227 lra_assert (to
!= NULL
);
5229 FOR_EACH_EDGE (e
, ei
, from
->succs
)
5231 bitmap_ior_into (res
, df_get_live_in (e
->dest
));
5232 last
= get_last_insertion_point (from
);
5233 if (! JUMP_P (last
))
5235 curr_id
= lra_get_insn_recog_data (last
);
5236 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
5237 if (reg
->type
!= OP_IN
)
5238 bitmap_set_bit (res
, reg
->regno
);
5241 /* Used as a temporary results of some bitmap calculations. */
5242 static bitmap_head temp_bitmap
;
5244 /* We split for reloads of small class of hard regs. The following
5245 defines how many hard regs the class should have to be qualified as
5246 small. The code is mostly oriented to x86/x86-64 architecture
5247 where some insns need to use only specific register or pair of
5248 registers and these register can live in RTL explicitly, e.g. for
5249 parameter passing. */
5250 static const int max_small_class_regs_num
= 2;
5252 /* Do inheritance/split transformations in EBB starting with HEAD and
5253 finishing on TAIL. We process EBB insns in the reverse order.
5254 Return true if we did any inheritance/split transformation in the
5257 We should avoid excessive splitting which results in worse code
5258 because of inaccurate cost calculations for spilling new split
5259 pseudos in such case. To achieve this we do splitting only if
5260 register pressure is high in given basic block and there are reload
5261 pseudos requiring hard registers. We could do more register
5262 pressure calculations at any given program point to avoid necessary
5263 splitting even more but it is to expensive and the current approach
5264 works well enough. */
5266 inherit_in_ebb (rtx_insn
*head
, rtx_insn
*tail
)
5268 int i
, src_regno
, dst_regno
, nregs
;
5269 bool change_p
, succ_p
, update_reloads_num_p
;
5270 rtx_insn
*prev_insn
, *last_insn
;
5271 rtx next_usage_insns
, set
;
5273 struct lra_insn_reg
*reg
;
5274 basic_block last_processed_bb
, curr_bb
= NULL
;
5275 HARD_REG_SET potential_reload_hard_regs
, live_hard_regs
;
5279 bool head_p
, after_p
;
5282 curr_usage_insns_check
++;
5283 reloads_num
= calls_num
= 0;
5284 bitmap_clear (&check_only_regs
);
5285 last_processed_bb
= NULL
;
5286 CLEAR_HARD_REG_SET (potential_reload_hard_regs
);
5287 COPY_HARD_REG_SET (live_hard_regs
, eliminable_regset
);
5288 IOR_HARD_REG_SET (live_hard_regs
, lra_no_alloc_regs
);
5289 /* We don't process new insns generated in the loop. */
5290 for (curr_insn
= tail
; curr_insn
!= PREV_INSN (head
); curr_insn
= prev_insn
)
5292 prev_insn
= PREV_INSN (curr_insn
);
5293 if (BLOCK_FOR_INSN (curr_insn
) != NULL
)
5294 curr_bb
= BLOCK_FOR_INSN (curr_insn
);
5295 if (last_processed_bb
!= curr_bb
)
5297 /* We are at the end of BB. Add qualified living
5298 pseudos for potential splitting. */
5299 to_process
= df_get_live_out (curr_bb
);
5300 if (last_processed_bb
!= NULL
)
5302 /* We are somewhere in the middle of EBB. */
5303 get_live_on_other_edges (curr_bb
, last_processed_bb
,
5305 to_process
= &temp_bitmap
;
5307 last_processed_bb
= curr_bb
;
5308 last_insn
= get_last_insertion_point (curr_bb
);
5309 after_p
= (! JUMP_P (last_insn
)
5310 && (! CALL_P (last_insn
)
5311 || (find_reg_note (last_insn
,
5312 REG_NORETURN
, NULL_RTX
) == NULL_RTX
5313 && ! SIBLING_CALL_P (last_insn
))));
5314 CLEAR_HARD_REG_SET (potential_reload_hard_regs
);
5315 EXECUTE_IF_SET_IN_BITMAP (to_process
, 0, j
, bi
)
5317 if ((int) j
>= lra_constraint_new_regno_start
)
5319 if (j
< FIRST_PSEUDO_REGISTER
|| reg_renumber
[j
] >= 0)
5321 if (j
< FIRST_PSEUDO_REGISTER
)
5322 SET_HARD_REG_BIT (live_hard_regs
, j
);
5324 add_to_hard_reg_set (&live_hard_regs
,
5325 PSEUDO_REGNO_MODE (j
),
5327 setup_next_usage_insn (j
, last_insn
, reloads_num
, after_p
);
5331 src_regno
= dst_regno
= -1;
5332 if (NONDEBUG_INSN_P (curr_insn
)
5333 && (set
= single_set (curr_insn
)) != NULL_RTX
5334 && REG_P (SET_DEST (set
)) && REG_P (SET_SRC (set
)))
5336 src_regno
= REGNO (SET_SRC (set
));
5337 dst_regno
= REGNO (SET_DEST (set
));
5339 update_reloads_num_p
= true;
5340 if (src_regno
< lra_constraint_new_regno_start
5341 && src_regno
>= FIRST_PSEUDO_REGISTER
5342 && reg_renumber
[src_regno
] < 0
5343 && dst_regno
>= lra_constraint_new_regno_start
5344 && (cl
= lra_get_allocno_class (dst_regno
)) != NO_REGS
)
5346 /* 'reload_pseudo <- original_pseudo'. */
5347 if (ira_class_hard_regs_num
[cl
] <= max_small_class_regs_num
)
5349 update_reloads_num_p
= false;
5351 if (usage_insns
[src_regno
].check
== curr_usage_insns_check
5352 && (next_usage_insns
= usage_insns
[src_regno
].insns
) != NULL_RTX
)
5353 succ_p
= inherit_reload_reg (false, src_regno
, cl
,
5354 curr_insn
, next_usage_insns
);
5358 setup_next_usage_insn (src_regno
, curr_insn
, reloads_num
, false);
5359 if (hard_reg_set_subset_p (reg_class_contents
[cl
], live_hard_regs
))
5360 IOR_HARD_REG_SET (potential_reload_hard_regs
,
5361 reg_class_contents
[cl
]);
5363 else if (src_regno
>= lra_constraint_new_regno_start
5364 && dst_regno
< lra_constraint_new_regno_start
5365 && dst_regno
>= FIRST_PSEUDO_REGISTER
5366 && reg_renumber
[dst_regno
] < 0
5367 && (cl
= lra_get_allocno_class (src_regno
)) != NO_REGS
5368 && usage_insns
[dst_regno
].check
== curr_usage_insns_check
5369 && (next_usage_insns
5370 = usage_insns
[dst_regno
].insns
) != NULL_RTX
)
5372 if (ira_class_hard_regs_num
[cl
] <= max_small_class_regs_num
)
5374 update_reloads_num_p
= false;
5375 /* 'original_pseudo <- reload_pseudo'. */
5376 if (! JUMP_P (curr_insn
)
5377 && inherit_reload_reg (true, dst_regno
, cl
,
5378 curr_insn
, next_usage_insns
))
5381 usage_insns
[dst_regno
].check
= 0;
5382 if (hard_reg_set_subset_p (reg_class_contents
[cl
], live_hard_regs
))
5383 IOR_HARD_REG_SET (potential_reload_hard_regs
,
5384 reg_class_contents
[cl
]);
5386 else if (INSN_P (curr_insn
))
5389 int max_uid
= get_max_uid ();
5391 curr_id
= lra_get_insn_recog_data (curr_insn
);
5392 curr_static_id
= curr_id
->insn_static_data
;
5394 /* Process insn definitions. */
5395 for (iter
= 0; iter
< 2; iter
++)
5396 for (reg
= iter
== 0 ? curr_id
->regs
: curr_static_id
->hard_regs
;
5399 if (reg
->type
!= OP_IN
5400 && (dst_regno
= reg
->regno
) < lra_constraint_new_regno_start
)
5402 if (dst_regno
>= FIRST_PSEUDO_REGISTER
&& reg
->type
== OP_OUT
5403 && reg_renumber
[dst_regno
] < 0 && ! reg
->subreg_p
5404 && usage_insns
[dst_regno
].check
== curr_usage_insns_check
5405 && (next_usage_insns
5406 = usage_insns
[dst_regno
].insns
) != NULL_RTX
)
5408 struct lra_insn_reg
*r
;
5410 for (r
= curr_id
->regs
; r
!= NULL
; r
= r
->next
)
5411 if (r
->type
!= OP_OUT
&& r
->regno
== dst_regno
)
5413 /* Don't do inheritance if the pseudo is also
5414 used in the insn. */
5416 /* We can not do inheritance right now
5417 because the current insn reg info (chain
5418 regs) can change after that. */
5419 add_to_inherit (dst_regno
, next_usage_insns
);
5421 /* We can not process one reg twice here because of
5422 usage_insns invalidation. */
5423 if ((dst_regno
< FIRST_PSEUDO_REGISTER
5424 || reg_renumber
[dst_regno
] >= 0)
5425 && ! reg
->subreg_p
&& reg
->type
!= OP_IN
)
5429 if (split_if_necessary (dst_regno
, reg
->biggest_mode
,
5430 potential_reload_hard_regs
,
5431 false, curr_insn
, max_uid
))
5433 CLEAR_HARD_REG_SET (s
);
5434 if (dst_regno
< FIRST_PSEUDO_REGISTER
)
5435 add_to_hard_reg_set (&s
, reg
->biggest_mode
, dst_regno
);
5437 add_to_hard_reg_set (&s
, PSEUDO_REGNO_MODE (dst_regno
),
5438 reg_renumber
[dst_regno
]);
5439 AND_COMPL_HARD_REG_SET (live_hard_regs
, s
);
5441 /* We should invalidate potential inheritance or
5442 splitting for the current insn usages to the next
5443 usage insns (see code below) as the output pseudo
5445 if ((dst_regno
>= FIRST_PSEUDO_REGISTER
5446 && reg_renumber
[dst_regno
] < 0)
5447 || (reg
->type
== OP_OUT
&& ! reg
->subreg_p
5448 && (dst_regno
< FIRST_PSEUDO_REGISTER
5449 || reg_renumber
[dst_regno
] >= 0)))
5451 /* Invalidate and mark definitions. */
5452 if (dst_regno
>= FIRST_PSEUDO_REGISTER
)
5453 usage_insns
[dst_regno
].check
= -(int) INSN_UID (curr_insn
);
5456 nregs
= hard_regno_nregs
[dst_regno
][reg
->biggest_mode
];
5457 for (i
= 0; i
< nregs
; i
++)
5458 usage_insns
[dst_regno
+ i
].check
5459 = -(int) INSN_UID (curr_insn
);
5463 if (! JUMP_P (curr_insn
))
5464 for (i
= 0; i
< to_inherit_num
; i
++)
5465 if (inherit_reload_reg (true, to_inherit
[i
].regno
,
5466 ALL_REGS
, curr_insn
,
5467 to_inherit
[i
].insns
))
5469 if (CALL_P (curr_insn
))
5471 rtx cheap
, pat
, dest
;
5473 int regno
, hard_regno
;
5476 if ((cheap
= find_reg_note (curr_insn
,
5477 REG_RETURNED
, NULL_RTX
)) != NULL_RTX
5478 && ((cheap
= XEXP (cheap
, 0)), true)
5479 && (regno
= REGNO (cheap
)) >= FIRST_PSEUDO_REGISTER
5480 && (hard_regno
= reg_renumber
[regno
]) >= 0
5481 /* If there are pending saves/restores, the
5482 optimization is not worth. */
5483 && usage_insns
[regno
].calls_num
== calls_num
- 1
5484 && TEST_HARD_REG_BIT (call_used_reg_set
, hard_regno
))
5486 /* Restore the pseudo from the call result as
5487 REG_RETURNED note says that the pseudo value is
5488 in the call result and the pseudo is an argument
5490 pat
= PATTERN (curr_insn
);
5491 if (GET_CODE (pat
) == PARALLEL
)
5492 pat
= XVECEXP (pat
, 0, 0);
5493 dest
= SET_DEST (pat
);
5494 /* For multiple return values dest is PARALLEL.
5495 Currently we handle only single return value case. */
5499 emit_move_insn (cheap
, copy_rtx (dest
));
5500 restore
= get_insns ();
5502 lra_process_new_insns (curr_insn
, NULL
, restore
,
5503 "Inserting call parameter restore");
5504 /* We don't need to save/restore of the pseudo from
5506 usage_insns
[regno
].calls_num
= calls_num
;
5507 bitmap_set_bit (&check_only_regs
, regno
);
5512 /* Process insn usages. */
5513 for (iter
= 0; iter
< 2; iter
++)
5514 for (reg
= iter
== 0 ? curr_id
->regs
: curr_static_id
->hard_regs
;
5517 if ((reg
->type
!= OP_OUT
5518 || (reg
->type
== OP_OUT
&& reg
->subreg_p
))
5519 && (src_regno
= reg
->regno
) < lra_constraint_new_regno_start
)
5521 if (src_regno
>= FIRST_PSEUDO_REGISTER
5522 && reg_renumber
[src_regno
] < 0 && reg
->type
== OP_IN
)
5524 if (usage_insns
[src_regno
].check
== curr_usage_insns_check
5525 && (next_usage_insns
5526 = usage_insns
[src_regno
].insns
) != NULL_RTX
5527 && NONDEBUG_INSN_P (curr_insn
))
5528 add_to_inherit (src_regno
, next_usage_insns
);
5529 else if (usage_insns
[src_regno
].check
5530 != -(int) INSN_UID (curr_insn
))
5531 /* Add usages but only if the reg is not set up
5532 in the same insn. */
5533 add_next_usage_insn (src_regno
, curr_insn
, reloads_num
);
5535 else if (src_regno
< FIRST_PSEUDO_REGISTER
5536 || reg_renumber
[src_regno
] >= 0)
5539 rtx use_insn
= curr_insn
;
5541 before_p
= (JUMP_P (curr_insn
)
5542 || (CALL_P (curr_insn
) && reg
->type
== OP_IN
));
5543 if (NONDEBUG_INSN_P (curr_insn
)
5544 && (! JUMP_P (curr_insn
) || reg
->type
== OP_IN
)
5545 && split_if_necessary (src_regno
, reg
->biggest_mode
,
5546 potential_reload_hard_regs
,
5547 before_p
, curr_insn
, max_uid
))
5550 lra_risky_transformations_p
= true;
5553 usage_insns
[src_regno
].check
= 0;
5555 use_insn
= PREV_INSN (curr_insn
);
5557 if (NONDEBUG_INSN_P (curr_insn
))
5559 if (src_regno
< FIRST_PSEUDO_REGISTER
)
5560 add_to_hard_reg_set (&live_hard_regs
,
5561 reg
->biggest_mode
, src_regno
);
5563 add_to_hard_reg_set (&live_hard_regs
,
5564 PSEUDO_REGNO_MODE (src_regno
),
5565 reg_renumber
[src_regno
]);
5567 add_next_usage_insn (src_regno
, use_insn
, reloads_num
);
5570 /* Process call args. */
5571 if (curr_id
->arg_hard_regs
!= NULL
)
5572 for (i
= 0; (src_regno
= curr_id
->arg_hard_regs
[i
]) >= 0; i
++)
5573 if (src_regno
< FIRST_PSEUDO_REGISTER
)
5575 SET_HARD_REG_BIT (live_hard_regs
, src_regno
);
5576 add_next_usage_insn (src_regno
, curr_insn
, reloads_num
);
5578 for (i
= 0; i
< to_inherit_num
; i
++)
5580 src_regno
= to_inherit
[i
].regno
;
5581 if (inherit_reload_reg (false, src_regno
, ALL_REGS
,
5582 curr_insn
, to_inherit
[i
].insns
))
5585 setup_next_usage_insn (src_regno
, curr_insn
, reloads_num
, false);
5588 if (update_reloads_num_p
5589 && NONDEBUG_INSN_P (curr_insn
)
5590 && (set
= single_set (curr_insn
)) != NULL_RTX
)
5593 if ((REG_P (SET_DEST (set
))
5594 && (regno
= REGNO (SET_DEST (set
))) >= lra_constraint_new_regno_start
5595 && reg_renumber
[regno
] < 0
5596 && (cl
= lra_get_allocno_class (regno
)) != NO_REGS
)
5597 || (REG_P (SET_SRC (set
))
5598 && (regno
= REGNO (SET_SRC (set
))) >= lra_constraint_new_regno_start
5599 && reg_renumber
[regno
] < 0
5600 && (cl
= lra_get_allocno_class (regno
)) != NO_REGS
))
5602 if (ira_class_hard_regs_num
[cl
] <= max_small_class_regs_num
)
5604 if (hard_reg_set_subset_p (reg_class_contents
[cl
], live_hard_regs
))
5605 IOR_HARD_REG_SET (potential_reload_hard_regs
,
5606 reg_class_contents
[cl
]);
5609 /* We reached the start of the current basic block. */
5610 if (prev_insn
== NULL_RTX
|| prev_insn
== PREV_INSN (head
)
5611 || BLOCK_FOR_INSN (prev_insn
) != curr_bb
)
5613 /* We reached the beginning of the current block -- do
5614 rest of spliting in the current BB. */
5615 to_process
= df_get_live_in (curr_bb
);
5616 if (BLOCK_FOR_INSN (head
) != curr_bb
)
5618 /* We are somewhere in the middle of EBB. */
5619 get_live_on_other_edges (EDGE_PRED (curr_bb
, 0)->src
,
5620 curr_bb
, &temp_bitmap
);
5621 to_process
= &temp_bitmap
;
5624 EXECUTE_IF_SET_IN_BITMAP (to_process
, 0, j
, bi
)
5626 if ((int) j
>= lra_constraint_new_regno_start
)
5628 if (((int) j
< FIRST_PSEUDO_REGISTER
|| reg_renumber
[j
] >= 0)
5629 && usage_insns
[j
].check
== curr_usage_insns_check
5630 && (next_usage_insns
= usage_insns
[j
].insns
) != NULL_RTX
)
5632 if (need_for_split_p (potential_reload_hard_regs
, j
))
5634 if (lra_dump_file
!= NULL
&& head_p
)
5636 fprintf (lra_dump_file
,
5637 " ----------------------------------\n");
5640 if (split_reg (false, j
, bb_note (curr_bb
),
5644 usage_insns
[j
].check
= 0;
5652 /* This value affects EBB forming. If probability of edge from EBB to
5653 a BB is not greater than the following value, we don't add the BB
5655 #define EBB_PROBABILITY_CUTOFF ((REG_BR_PROB_BASE * 50) / 100)
5657 /* Current number of inheritance/split iteration. */
5658 int lra_inheritance_iter
;
5660 /* Entry function for inheritance/split pass. */
5662 lra_inheritance (void)
5665 basic_block bb
, start_bb
;
5668 lra_inheritance_iter
++;
5669 if (lra_inheritance_iter
> LRA_MAX_INHERITANCE_PASSES
)
5671 timevar_push (TV_LRA_INHERITANCE
);
5672 if (lra_dump_file
!= NULL
)
5673 fprintf (lra_dump_file
, "\n********** Inheritance #%d: **********\n\n",
5674 lra_inheritance_iter
);
5675 curr_usage_insns_check
= 0;
5676 usage_insns
= XNEWVEC (struct usage_insns
, lra_constraint_new_regno_start
);
5677 for (i
= 0; i
< lra_constraint_new_regno_start
; i
++)
5678 usage_insns
[i
].check
= 0;
5679 bitmap_initialize (&check_only_regs
, ®_obstack
);
5680 bitmap_initialize (&live_regs
, ®_obstack
);
5681 bitmap_initialize (&temp_bitmap
, ®_obstack
);
5682 bitmap_initialize (&ebb_global_regs
, ®_obstack
);
5683 FOR_EACH_BB_FN (bb
, cfun
)
5686 if (lra_dump_file
!= NULL
)
5687 fprintf (lra_dump_file
, "EBB");
5688 /* Form a EBB starting with BB. */
5689 bitmap_clear (&ebb_global_regs
);
5690 bitmap_ior_into (&ebb_global_regs
, df_get_live_in (bb
));
5693 if (lra_dump_file
!= NULL
)
5694 fprintf (lra_dump_file
, " %d", bb
->index
);
5695 if (bb
->next_bb
== EXIT_BLOCK_PTR_FOR_FN (cfun
)
5696 || LABEL_P (BB_HEAD (bb
->next_bb
)))
5698 e
= find_fallthru_edge (bb
->succs
);
5701 if (e
->probability
<= EBB_PROBABILITY_CUTOFF
)
5705 bitmap_ior_into (&ebb_global_regs
, df_get_live_out (bb
));
5706 if (lra_dump_file
!= NULL
)
5707 fprintf (lra_dump_file
, "\n");
5708 if (inherit_in_ebb (BB_HEAD (start_bb
), BB_END (bb
)))
5709 /* Remember that the EBB head and tail can change in
5711 update_ebb_live_info (BB_HEAD (start_bb
), BB_END (bb
));
5713 bitmap_clear (&ebb_global_regs
);
5714 bitmap_clear (&temp_bitmap
);
5715 bitmap_clear (&live_regs
);
5716 bitmap_clear (&check_only_regs
);
5719 timevar_pop (TV_LRA_INHERITANCE
);
5724 /* This page contains code to undo failed inheritance/split
5727 /* Current number of iteration undoing inheritance/split. */
5728 int lra_undo_inheritance_iter
;
5730 /* Fix BB live info LIVE after removing pseudos created on pass doing
5731 inheritance/split which are REMOVED_PSEUDOS. */
5733 fix_bb_live_info (bitmap live
, bitmap removed_pseudos
)
5738 EXECUTE_IF_SET_IN_BITMAP (removed_pseudos
, 0, regno
, bi
)
5739 if (bitmap_clear_bit (live
, regno
))
5740 bitmap_set_bit (live
, lra_reg_info
[regno
].restore_regno
);
5743 /* Return regno of the (subreg of) REG. Otherwise, return a negative
5748 if (GET_CODE (reg
) == SUBREG
)
5749 reg
= SUBREG_REG (reg
);
5755 /* Remove inheritance/split pseudos which are in REMOVE_PSEUDOS and
5756 return true if we did any change. The undo transformations for
5757 inheritance looks like
5761 p <- i, i <- p, and i <- i3
5762 where p is original pseudo from which inheritance pseudo i was
5763 created, i and i3 are removed inheritance pseudos, i2 is another
5764 not removed inheritance pseudo. All split pseudos or other
5765 occurrences of removed inheritance pseudos are changed on the
5766 corresponding original pseudos.
5768 The function also schedules insns changed and created during
5769 inheritance/split pass for processing by the subsequent constraint
5772 remove_inheritance_pseudos (bitmap remove_pseudos
)
5775 int regno
, sregno
, prev_sregno
, dregno
, restore_regno
;
5777 rtx_insn
*prev_insn
;
5778 bool change_p
, done_p
;
5780 change_p
= ! bitmap_empty_p (remove_pseudos
);
5781 /* We can not finish the function right away if CHANGE_P is true
5782 because we need to marks insns affected by previous
5783 inheritance/split pass for processing by the subsequent
5785 FOR_EACH_BB_FN (bb
, cfun
)
5787 fix_bb_live_info (df_get_live_in (bb
), remove_pseudos
);
5788 fix_bb_live_info (df_get_live_out (bb
), remove_pseudos
);
5789 FOR_BB_INSNS_REVERSE (bb
, curr_insn
)
5791 if (! INSN_P (curr_insn
))
5794 sregno
= dregno
= -1;
5795 if (change_p
&& NONDEBUG_INSN_P (curr_insn
)
5796 && (set
= single_set (curr_insn
)) != NULL_RTX
)
5798 dregno
= get_regno (SET_DEST (set
));
5799 sregno
= get_regno (SET_SRC (set
));
5802 if (sregno
>= 0 && dregno
>= 0)
5804 if ((bitmap_bit_p (remove_pseudos
, sregno
)
5805 && (lra_reg_info
[sregno
].restore_regno
== dregno
5806 || (bitmap_bit_p (remove_pseudos
, dregno
)
5807 && (lra_reg_info
[sregno
].restore_regno
5808 == lra_reg_info
[dregno
].restore_regno
))))
5809 || (bitmap_bit_p (remove_pseudos
, dregno
)
5810 && lra_reg_info
[dregno
].restore_regno
== sregno
))
5811 /* One of the following cases:
5812 original <- removed inheritance pseudo
5813 removed inherit pseudo <- another removed inherit pseudo
5814 removed inherit pseudo <- original pseudo
5816 removed_split_pseudo <- original_reg
5817 original_reg <- removed_split_pseudo */
5819 if (lra_dump_file
!= NULL
)
5821 fprintf (lra_dump_file
, " Removing %s:\n",
5822 bitmap_bit_p (&lra_split_regs
, sregno
)
5823 || bitmap_bit_p (&lra_split_regs
, dregno
)
5824 ? "split" : "inheritance");
5825 dump_insn_slim (lra_dump_file
, curr_insn
);
5827 lra_set_insn_deleted (curr_insn
);
5830 else if (bitmap_bit_p (remove_pseudos
, sregno
)
5831 && bitmap_bit_p (&lra_inheritance_pseudos
, sregno
))
5833 /* Search the following pattern:
5834 inherit_or_split_pseudo1 <- inherit_or_split_pseudo2
5835 original_pseudo <- inherit_or_split_pseudo1
5836 where the 2nd insn is the current insn and
5837 inherit_or_split_pseudo2 is not removed. If it is found,
5838 change the current insn onto:
5839 original_pseudo <- inherit_or_split_pseudo2. */
5840 for (prev_insn
= PREV_INSN (curr_insn
);
5841 prev_insn
!= NULL_RTX
&& ! NONDEBUG_INSN_P (prev_insn
);
5842 prev_insn
= PREV_INSN (prev_insn
))
5844 if (prev_insn
!= NULL_RTX
&& BLOCK_FOR_INSN (prev_insn
) == bb
5845 && (prev_set
= single_set (prev_insn
)) != NULL_RTX
5846 /* There should be no subregs in insn we are
5847 searching because only the original reg might
5848 be in subreg when we changed the mode of
5849 load/store for splitting. */
5850 && REG_P (SET_DEST (prev_set
))
5851 && REG_P (SET_SRC (prev_set
))
5852 && (int) REGNO (SET_DEST (prev_set
)) == sregno
5853 && ((prev_sregno
= REGNO (SET_SRC (prev_set
)))
5854 >= FIRST_PSEUDO_REGISTER
)
5855 /* As we consider chain of inheritance or
5856 splitting described in above comment we should
5857 check that sregno and prev_sregno were
5858 inheritance/split pseudos created from the
5859 same original regno. */
5860 && (lra_reg_info
[sregno
].restore_regno
5861 == lra_reg_info
[prev_sregno
].restore_regno
)
5862 && ! bitmap_bit_p (remove_pseudos
, prev_sregno
))
5864 lra_assert (GET_MODE (SET_SRC (prev_set
))
5865 == GET_MODE (regno_reg_rtx
[sregno
]));
5866 if (GET_CODE (SET_SRC (set
)) == SUBREG
)
5867 SUBREG_REG (SET_SRC (set
)) = SET_SRC (prev_set
);
5869 SET_SRC (set
) = SET_SRC (prev_set
);
5870 /* As we are finishing with processing the insn
5871 here, check the destination too as it might
5872 inheritance pseudo for another pseudo. */
5873 if (bitmap_bit_p (remove_pseudos
, dregno
)
5874 && bitmap_bit_p (&lra_inheritance_pseudos
, dregno
)
5876 = lra_reg_info
[dregno
].restore_regno
) >= 0)
5878 if (GET_CODE (SET_DEST (set
)) == SUBREG
)
5879 SUBREG_REG (SET_DEST (set
))
5880 = regno_reg_rtx
[restore_regno
];
5882 SET_DEST (set
) = regno_reg_rtx
[restore_regno
];
5884 lra_push_insn_and_update_insn_regno_info (curr_insn
);
5885 lra_set_used_insn_alternative_by_uid
5886 (INSN_UID (curr_insn
), -1);
5888 if (lra_dump_file
!= NULL
)
5890 fprintf (lra_dump_file
, " Change reload insn:\n");
5891 dump_insn_slim (lra_dump_file
, curr_insn
);
5898 struct lra_insn_reg
*reg
;
5899 bool restored_regs_p
= false;
5900 bool kept_regs_p
= false;
5902 curr_id
= lra_get_insn_recog_data (curr_insn
);
5903 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
5906 restore_regno
= lra_reg_info
[regno
].restore_regno
;
5907 if (restore_regno
>= 0)
5909 if (change_p
&& bitmap_bit_p (remove_pseudos
, regno
))
5911 lra_substitute_pseudo_within_insn (
5912 curr_insn
, regno
, regno_reg_rtx
[restore_regno
]);
5913 restored_regs_p
= true;
5919 if (NONDEBUG_INSN_P (curr_insn
) && kept_regs_p
)
5921 /* The instruction has changed since the previous
5922 constraints pass. */
5923 lra_push_insn_and_update_insn_regno_info (curr_insn
);
5924 lra_set_used_insn_alternative_by_uid
5925 (INSN_UID (curr_insn
), -1);
5927 else if (restored_regs_p
)
5928 /* The instruction has been restored to the form that
5929 it had during the previous constraints pass. */
5930 lra_update_insn_regno_info (curr_insn
);
5931 if (restored_regs_p
&& lra_dump_file
!= NULL
)
5933 fprintf (lra_dump_file
, " Insn after restoring regs:\n");
5934 dump_insn_slim (lra_dump_file
, curr_insn
);
5942 /* If optional reload pseudos failed to get a hard register or was not
5943 inherited, it is better to remove optional reloads. We do this
5944 transformation after undoing inheritance to figure out necessity to
5945 remove optional reloads easier. Return true if we do any
5948 undo_optional_reloads (void)
5950 bool change_p
, keep_p
;
5951 unsigned int regno
, uid
;
5952 bitmap_iterator bi
, bi2
;
5955 bitmap_head removed_optional_reload_pseudos
, insn_bitmap
;
5957 bitmap_initialize (&removed_optional_reload_pseudos
, ®_obstack
);
5958 bitmap_copy (&removed_optional_reload_pseudos
, &lra_optional_reload_pseudos
);
5959 EXECUTE_IF_SET_IN_BITMAP (&lra_optional_reload_pseudos
, 0, regno
, bi
)
5962 /* Keep optional reloads from previous subpasses. */
5963 if (lra_reg_info
[regno
].restore_regno
< 0
5964 /* If the original pseudo changed its allocation, just
5965 removing the optional pseudo is dangerous as the original
5966 pseudo will have longer live range. */
5967 || reg_renumber
[lra_reg_info
[regno
].restore_regno
] >= 0)
5969 else if (reg_renumber
[regno
] >= 0)
5970 EXECUTE_IF_SET_IN_BITMAP (&lra_reg_info
[regno
].insn_bitmap
, 0, uid
, bi2
)
5972 insn
= lra_insn_recog_data
[uid
]->insn
;
5973 if ((set
= single_set (insn
)) == NULL_RTX
)
5975 src
= SET_SRC (set
);
5976 dest
= SET_DEST (set
);
5977 if (! REG_P (src
) || ! REG_P (dest
))
5979 if (REGNO (dest
) == regno
5980 /* Ignore insn for optional reloads itself. */
5981 && lra_reg_info
[regno
].restore_regno
!= (int) REGNO (src
)
5982 /* Check only inheritance on last inheritance pass. */
5983 && (int) REGNO (src
) >= new_regno_start
5984 /* Check that the optional reload was inherited. */
5985 && bitmap_bit_p (&lra_inheritance_pseudos
, REGNO (src
)))
5993 bitmap_clear_bit (&removed_optional_reload_pseudos
, regno
);
5994 if (lra_dump_file
!= NULL
)
5995 fprintf (lra_dump_file
, "Keep optional reload reg %d\n", regno
);
5998 change_p
= ! bitmap_empty_p (&removed_optional_reload_pseudos
);
5999 bitmap_initialize (&insn_bitmap
, ®_obstack
);
6000 EXECUTE_IF_SET_IN_BITMAP (&removed_optional_reload_pseudos
, 0, regno
, bi
)
6002 if (lra_dump_file
!= NULL
)
6003 fprintf (lra_dump_file
, "Remove optional reload reg %d\n", regno
);
6004 bitmap_copy (&insn_bitmap
, &lra_reg_info
[regno
].insn_bitmap
);
6005 EXECUTE_IF_SET_IN_BITMAP (&insn_bitmap
, 0, uid
, bi2
)
6007 insn
= lra_insn_recog_data
[uid
]->insn
;
6008 if ((set
= single_set (insn
)) != NULL_RTX
)
6010 src
= SET_SRC (set
);
6011 dest
= SET_DEST (set
);
6012 if (REG_P (src
) && REG_P (dest
)
6013 && ((REGNO (src
) == regno
6014 && (lra_reg_info
[regno
].restore_regno
6015 == (int) REGNO (dest
)))
6016 || (REGNO (dest
) == regno
6017 && (lra_reg_info
[regno
].restore_regno
6018 == (int) REGNO (src
)))))
6020 if (lra_dump_file
!= NULL
)
6022 fprintf (lra_dump_file
, " Deleting move %u\n",
6024 dump_insn_slim (lra_dump_file
, insn
);
6026 lra_set_insn_deleted (insn
);
6029 /* We should not worry about generation memory-memory
6030 moves here as if the corresponding inheritance did
6031 not work (inheritance pseudo did not get a hard reg),
6032 we remove the inheritance pseudo and the optional
6035 lra_substitute_pseudo_within_insn (
6037 regno_reg_rtx
[lra_reg_info
[regno
].restore_regno
]);
6038 lra_update_insn_regno_info (insn
);
6039 if (lra_dump_file
!= NULL
)
6041 fprintf (lra_dump_file
,
6042 " Restoring original insn:\n");
6043 dump_insn_slim (lra_dump_file
, insn
);
6047 /* Clear restore_regnos. */
6048 EXECUTE_IF_SET_IN_BITMAP (&lra_optional_reload_pseudos
, 0, regno
, bi
)
6049 lra_reg_info
[regno
].restore_regno
= -1;
6050 bitmap_clear (&insn_bitmap
);
6051 bitmap_clear (&removed_optional_reload_pseudos
);
6055 /* Entry function for undoing inheritance/split transformation. Return true
6056 if we did any RTL change in this pass. */
6058 lra_undo_inheritance (void)
6061 int restore_regno
, hard_regno
;
6062 int n_all_inherit
, n_inherit
, n_all_split
, n_split
;
6063 bitmap_head remove_pseudos
;
6067 lra_undo_inheritance_iter
++;
6068 if (lra_undo_inheritance_iter
> LRA_MAX_INHERITANCE_PASSES
)
6070 if (lra_dump_file
!= NULL
)
6071 fprintf (lra_dump_file
,
6072 "\n********** Undoing inheritance #%d: **********\n\n",
6073 lra_undo_inheritance_iter
);
6074 bitmap_initialize (&remove_pseudos
, ®_obstack
);
6075 n_inherit
= n_all_inherit
= 0;
6076 EXECUTE_IF_SET_IN_BITMAP (&lra_inheritance_pseudos
, 0, regno
, bi
)
6077 if (lra_reg_info
[regno
].restore_regno
>= 0)
6080 if (reg_renumber
[regno
] < 0
6081 /* If the original pseudo changed its allocation, just
6082 removing inheritance is dangerous as for changing
6083 allocation we used shorter live-ranges. */
6084 && reg_renumber
[lra_reg_info
[regno
].restore_regno
] < 0)
6085 bitmap_set_bit (&remove_pseudos
, regno
);
6089 if (lra_dump_file
!= NULL
&& n_all_inherit
!= 0)
6090 fprintf (lra_dump_file
, "Inherit %d out of %d (%.2f%%)\n",
6091 n_inherit
, n_all_inherit
,
6092 (double) n_inherit
/ n_all_inherit
* 100);
6093 n_split
= n_all_split
= 0;
6094 EXECUTE_IF_SET_IN_BITMAP (&lra_split_regs
, 0, regno
, bi
)
6095 if ((restore_regno
= lra_reg_info
[regno
].restore_regno
) >= 0)
6098 hard_regno
= (restore_regno
>= FIRST_PSEUDO_REGISTER
6099 ? reg_renumber
[restore_regno
] : restore_regno
);
6100 if (hard_regno
< 0 || reg_renumber
[regno
] == hard_regno
)
6101 bitmap_set_bit (&remove_pseudos
, regno
);
6105 if (lra_dump_file
!= NULL
)
6106 fprintf (lra_dump_file
, " Keep split r%d (orig=r%d)\n",
6107 regno
, restore_regno
);
6110 if (lra_dump_file
!= NULL
&& n_all_split
!= 0)
6111 fprintf (lra_dump_file
, "Split %d out of %d (%.2f%%)\n",
6112 n_split
, n_all_split
,
6113 (double) n_split
/ n_all_split
* 100);
6114 change_p
= remove_inheritance_pseudos (&remove_pseudos
);
6115 bitmap_clear (&remove_pseudos
);
6116 /* Clear restore_regnos. */
6117 EXECUTE_IF_SET_IN_BITMAP (&lra_inheritance_pseudos
, 0, regno
, bi
)
6118 lra_reg_info
[regno
].restore_regno
= -1;
6119 EXECUTE_IF_SET_IN_BITMAP (&lra_split_regs
, 0, regno
, bi
)
6120 lra_reg_info
[regno
].restore_regno
= -1;
6121 change_p
= undo_optional_reloads () || change_p
;