1 /* Code for RTL transformations to satisfy insn constraints.
2 Copyright (C) 2010-2015 Free Software Foundation, Inc.
3 Contributed by Vladimir Makarov <vmakarov@redhat.com>.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 3, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
22 /* This file contains code for 3 passes: constraint pass,
23 inheritance/split pass, and pass for undoing failed inheritance and
26 The major goal of constraint pass is to transform RTL to satisfy
27 insn and address constraints by:
28 o choosing insn alternatives;
29 o generating *reload insns* (or reloads in brief) and *reload
30 pseudos* which will get necessary hard registers later;
31 o substituting pseudos with equivalent values and removing the
32 instructions that initialized those pseudos.
34 The constraint pass has biggest and most complicated code in LRA.
35 There are a lot of important details like:
36 o reuse of input reload pseudos to simplify reload pseudo
38 o some heuristics to choose insn alternative to improve the
42 The pass is mimicking former reload pass in alternative choosing
43 because the reload pass is oriented to current machine description
44 model. It might be changed if the machine description model is
47 There is special code for preventing all LRA and this pass cycling
50 On the first iteration of the pass we process every instruction and
51 choose an alternative for each one. On subsequent iterations we try
52 to avoid reprocessing instructions if we can be sure that the old
53 choice is still valid.
55 The inheritance/spilt pass is to transform code to achieve
56 ineheritance and live range splitting. It is done on backward
59 The inheritance optimization goal is to reuse values in hard
60 registers. There is analogous optimization in old reload pass. The
61 inheritance is achieved by following transformation:
63 reload_p1 <- p reload_p1 <- p
64 ... new_p <- reload_p1
66 reload_p2 <- p reload_p2 <- new_p
68 where p is spilled and not changed between the insns. Reload_p1 is
69 also called *original pseudo* and new_p is called *inheritance
72 The subsequent assignment pass will try to assign the same (or
73 another if it is not possible) hard register to new_p as to
74 reload_p1 or reload_p2.
76 If the assignment pass fails to assign a hard register to new_p,
77 this file will undo the inheritance and restore the original code.
78 This is because implementing the above sequence with a spilled
79 new_p would make the code much worse. The inheritance is done in
80 EBB scope. The above is just a simplified example to get an idea
81 of the inheritance as the inheritance is also done for non-reload
84 Splitting (transformation) is also done in EBB scope on the same
85 pass as the inheritance:
87 r <- ... or ... <- r r <- ... or ... <- r
88 ... s <- r (new insn -- save)
90 ... r <- s (new insn -- restore)
93 The *split pseudo* s is assigned to the hard register of the
94 original pseudo or hard register r.
97 o In EBBs with high register pressure for global pseudos (living
98 in at least 2 BBs) and assigned to hard registers when there
99 are more one reloads needing the hard registers;
100 o for pseudos needing save/restore code around calls.
102 If the split pseudo still has the same hard register as the
103 original pseudo after the subsequent assignment pass or the
104 original pseudo was split, the opposite transformation is done on
105 the same pass for undoing inheritance. */
111 #include "coretypes.h"
113 #include "hard-reg-set.h"
117 #include "insn-config.h"
118 #include "insn-codes.h"
121 #include "addresses.h"
124 #include "hash-set.h"
127 #include "function.h"
130 #include "statistics.h"
138 #include "emit-rtl.h"
143 #include "dominance.h"
146 #include "basic-block.h"
151 #include "rtl-error.h"
155 /* Value of LRA_CURR_RELOAD_NUM at the beginning of BB of the current
156 insn. Remember that LRA_CURR_RELOAD_NUM is the number of emitted
158 static int bb_reload_num
;
160 /* The current insn being processed and corresponding its single set
161 (NULL otherwise), its data (basic block, the insn data, the insn
162 static data, and the mode of each operand). */
163 static rtx_insn
*curr_insn
;
164 static rtx curr_insn_set
;
165 static basic_block curr_bb
;
166 static lra_insn_recog_data_t curr_id
;
167 static struct lra_static_insn_data
*curr_static_id
;
168 static machine_mode curr_operand_mode
[MAX_RECOG_OPERANDS
];
169 /* Mode of the register substituted by its equivalence with VOIDmode
170 (e.g. constant) and whose subreg is given operand of the current
171 insn. VOIDmode in all other cases. */
172 static machine_mode original_subreg_reg_mode
[MAX_RECOG_OPERANDS
];
176 /* Start numbers for new registers and insns at the current constraints
178 static int new_regno_start
;
179 static int new_insn_uid_start
;
181 /* If LOC is nonnull, strip any outer subreg from it. */
183 strip_subreg (rtx
*loc
)
185 return loc
&& GET_CODE (*loc
) == SUBREG
? &SUBREG_REG (*loc
) : loc
;
188 /* Return hard regno of REGNO or if it is was not assigned to a hard
189 register, use a hard register from its allocno class. */
191 get_try_hard_regno (int regno
)
194 enum reg_class rclass
;
196 if ((hard_regno
= regno
) >= FIRST_PSEUDO_REGISTER
)
197 hard_regno
= lra_get_regno_hard_regno (regno
);
200 rclass
= lra_get_allocno_class (regno
);
201 if (rclass
== NO_REGS
)
203 return ira_class_hard_regs
[rclass
][0];
206 /* Return final hard regno (plus offset) which will be after
207 elimination. We do this for matching constraints because the final
208 hard regno could have a different class. */
210 get_final_hard_regno (int hard_regno
, int offset
)
214 hard_regno
= lra_get_elimination_hard_regno (hard_regno
);
215 return hard_regno
+ offset
;
218 /* Return hard regno of X after removing subreg and making
219 elimination. If X is not a register or subreg of register, return
220 -1. For pseudo use its assignment. */
222 get_hard_regno (rtx x
)
225 int offset
, hard_regno
;
228 if (GET_CODE (x
) == SUBREG
)
229 reg
= SUBREG_REG (x
);
232 if ((hard_regno
= REGNO (reg
)) >= FIRST_PSEUDO_REGISTER
)
233 hard_regno
= lra_get_regno_hard_regno (hard_regno
);
237 if (GET_CODE (x
) == SUBREG
)
238 offset
+= subreg_regno_offset (hard_regno
, GET_MODE (reg
),
239 SUBREG_BYTE (x
), GET_MODE (x
));
240 return get_final_hard_regno (hard_regno
, offset
);
243 /* If REGNO is a hard register or has been allocated a hard register,
244 return the class of that register. If REGNO is a reload pseudo
245 created by the current constraints pass, return its allocno class.
246 Return NO_REGS otherwise. */
247 static enum reg_class
248 get_reg_class (int regno
)
252 if ((hard_regno
= regno
) >= FIRST_PSEUDO_REGISTER
)
253 hard_regno
= lra_get_regno_hard_regno (regno
);
256 hard_regno
= get_final_hard_regno (hard_regno
, 0);
257 return REGNO_REG_CLASS (hard_regno
);
259 if (regno
>= new_regno_start
)
260 return lra_get_allocno_class (regno
);
264 /* Return true if REG satisfies (or will satisfy) reg class constraint
265 CL. Use elimination first if REG is a hard register. If REG is a
266 reload pseudo created by this constraints pass, assume that it will
267 be allocated a hard register from its allocno class, but allow that
268 class to be narrowed to CL if it is currently a superset of CL.
270 If NEW_CLASS is nonnull, set *NEW_CLASS to the new allocno class of
271 REGNO (reg), or NO_REGS if no change in its class was needed. */
273 in_class_p (rtx reg
, enum reg_class cl
, enum reg_class
*new_class
)
275 enum reg_class rclass
, common_class
;
276 machine_mode reg_mode
;
277 int class_size
, hard_regno
, nregs
, i
, j
;
278 int regno
= REGNO (reg
);
280 if (new_class
!= NULL
)
281 *new_class
= NO_REGS
;
282 if (regno
< FIRST_PSEUDO_REGISTER
)
285 rtx
*final_loc
= &final_reg
;
287 lra_eliminate_reg_if_possible (final_loc
);
288 return TEST_HARD_REG_BIT (reg_class_contents
[cl
], REGNO (*final_loc
));
290 reg_mode
= GET_MODE (reg
);
291 rclass
= get_reg_class (regno
);
292 if (regno
< new_regno_start
293 /* Do not allow the constraints for reload instructions to
294 influence the classes of new pseudos. These reloads are
295 typically moves that have many alternatives, and restricting
296 reload pseudos for one alternative may lead to situations
297 where other reload pseudos are no longer allocatable. */
298 || (INSN_UID (curr_insn
) >= new_insn_uid_start
299 && curr_insn_set
!= NULL
300 && ((OBJECT_P (SET_SRC (curr_insn_set
))
301 && ! CONSTANT_P (SET_SRC (curr_insn_set
)))
302 || (GET_CODE (SET_SRC (curr_insn_set
)) == SUBREG
303 && OBJECT_P (SUBREG_REG (SET_SRC (curr_insn_set
)))
304 && ! CONSTANT_P (SUBREG_REG (SET_SRC (curr_insn_set
)))))))
305 /* When we don't know what class will be used finally for reload
306 pseudos, we use ALL_REGS. */
307 return ((regno
>= new_regno_start
&& rclass
== ALL_REGS
)
308 || (rclass
!= NO_REGS
&& ira_class_subset_p
[rclass
][cl
]
309 && ! hard_reg_set_subset_p (reg_class_contents
[cl
],
310 lra_no_alloc_regs
)));
313 common_class
= ira_reg_class_subset
[rclass
][cl
];
314 if (new_class
!= NULL
)
315 *new_class
= common_class
;
316 if (hard_reg_set_subset_p (reg_class_contents
[common_class
],
319 /* Check that there are enough allocatable regs. */
320 class_size
= ira_class_hard_regs_num
[common_class
];
321 for (i
= 0; i
< class_size
; i
++)
323 hard_regno
= ira_class_hard_regs
[common_class
][i
];
324 nregs
= hard_regno_nregs
[hard_regno
][reg_mode
];
327 for (j
= 0; j
< nregs
; j
++)
328 if (TEST_HARD_REG_BIT (lra_no_alloc_regs
, hard_regno
+ j
)
329 || ! TEST_HARD_REG_BIT (reg_class_contents
[common_class
],
339 /* Return true if REGNO satisfies a memory constraint. */
343 return get_reg_class (regno
) == NO_REGS
;
346 /* Return 1 if ADDR is a valid memory address for mode MODE in address
347 space AS, and check that each pseudo has the proper kind of hard
350 valid_address_p (machine_mode mode ATTRIBUTE_UNUSED
,
351 rtx addr
, addr_space_t as
)
353 #ifdef GO_IF_LEGITIMATE_ADDRESS
354 lra_assert (ADDR_SPACE_GENERIC_P (as
));
355 GO_IF_LEGITIMATE_ADDRESS (mode
, addr
, win
);
361 return targetm
.addr_space
.legitimate_address_p (mode
, addr
, 0, as
);
366 /* Temporarily eliminates registers in an address (for the lifetime of
368 class address_eliminator
{
370 address_eliminator (struct address_info
*ad
);
371 ~address_eliminator ();
374 struct address_info
*m_ad
;
382 address_eliminator::address_eliminator (struct address_info
*ad
)
384 m_base_loc (strip_subreg (ad
->base_term
)),
385 m_base_reg (NULL_RTX
),
386 m_index_loc (strip_subreg (ad
->index_term
)),
387 m_index_reg (NULL_RTX
)
389 if (m_base_loc
!= NULL
)
391 m_base_reg
= *m_base_loc
;
392 lra_eliminate_reg_if_possible (m_base_loc
);
393 if (m_ad
->base_term2
!= NULL
)
394 *m_ad
->base_term2
= *m_ad
->base_term
;
396 if (m_index_loc
!= NULL
)
398 m_index_reg
= *m_index_loc
;
399 lra_eliminate_reg_if_possible (m_index_loc
);
403 address_eliminator::~address_eliminator ()
405 if (m_base_loc
&& *m_base_loc
!= m_base_reg
)
407 *m_base_loc
= m_base_reg
;
408 if (m_ad
->base_term2
!= NULL
)
409 *m_ad
->base_term2
= *m_ad
->base_term
;
411 if (m_index_loc
&& *m_index_loc
!= m_index_reg
)
412 *m_index_loc
= m_index_reg
;
415 /* Return true if the eliminated form of AD is a legitimate target address. */
417 valid_address_p (struct address_info
*ad
)
419 address_eliminator
eliminator (ad
);
420 return valid_address_p (ad
->mode
, *ad
->outer
, ad
->as
);
423 /* Return true if the eliminated form of memory reference OP satisfies
424 extra memory constraint CONSTRAINT. */
426 satisfies_memory_constraint_p (rtx op
, enum constraint_num constraint
)
428 struct address_info ad
;
430 decompose_mem_address (&ad
, op
);
431 address_eliminator
eliminator (&ad
);
432 return constraint_satisfied_p (op
, constraint
);
435 /* Return true if the eliminated form of address AD satisfies extra
436 address constraint CONSTRAINT. */
438 satisfies_address_constraint_p (struct address_info
*ad
,
439 enum constraint_num constraint
)
441 address_eliminator
eliminator (ad
);
442 return constraint_satisfied_p (*ad
->outer
, constraint
);
445 /* Return true if the eliminated form of address OP satisfies extra
446 address constraint CONSTRAINT. */
448 satisfies_address_constraint_p (rtx op
, enum constraint_num constraint
)
450 struct address_info ad
;
452 decompose_lea_address (&ad
, &op
);
453 return satisfies_address_constraint_p (&ad
, constraint
);
456 /* Initiate equivalences for LRA. As we keep original equivalences
457 before any elimination, we need to make copies otherwise any change
458 in insns might change the equivalences. */
460 lra_init_equiv (void)
462 ira_expand_reg_equiv ();
463 for (int i
= FIRST_PSEUDO_REGISTER
; i
< max_reg_num (); i
++)
467 if ((res
= ira_reg_equiv
[i
].memory
) != NULL_RTX
)
468 ira_reg_equiv
[i
].memory
= copy_rtx (res
);
469 if ((res
= ira_reg_equiv
[i
].invariant
) != NULL_RTX
)
470 ira_reg_equiv
[i
].invariant
= copy_rtx (res
);
474 static rtx
loc_equivalence_callback (rtx
, const_rtx
, void *);
476 /* Update equivalence for REGNO. We need to this as the equivalence
477 might contain other pseudos which are changed by their
480 update_equiv (int regno
)
484 if ((x
= ira_reg_equiv
[regno
].memory
) != NULL_RTX
)
485 ira_reg_equiv
[regno
].memory
486 = simplify_replace_fn_rtx (x
, NULL_RTX
, loc_equivalence_callback
,
488 if ((x
= ira_reg_equiv
[regno
].invariant
) != NULL_RTX
)
489 ira_reg_equiv
[regno
].invariant
490 = simplify_replace_fn_rtx (x
, NULL_RTX
, loc_equivalence_callback
,
494 /* If we have decided to substitute X with another value, return that
495 value, otherwise return X. */
502 if (! REG_P (x
) || (regno
= REGNO (x
)) < FIRST_PSEUDO_REGISTER
503 || ! ira_reg_equiv
[regno
].defined_p
504 || ! ira_reg_equiv
[regno
].profitable_p
505 || lra_get_regno_hard_regno (regno
) >= 0)
507 if ((res
= ira_reg_equiv
[regno
].memory
) != NULL_RTX
)
509 if (targetm
.cannot_substitute_mem_equiv_p (res
))
513 if ((res
= ira_reg_equiv
[regno
].constant
) != NULL_RTX
)
515 if ((res
= ira_reg_equiv
[regno
].invariant
) != NULL_RTX
)
520 /* If we have decided to substitute X with the equivalent value,
521 return that value after elimination for INSN, otherwise return
524 get_equiv_with_elimination (rtx x
, rtx_insn
*insn
)
526 rtx res
= get_equiv (x
);
528 if (x
== res
|| CONSTANT_P (res
))
530 return lra_eliminate_regs_1 (insn
, res
, GET_MODE (res
),
531 false, false, 0, true);
534 /* Set up curr_operand_mode. */
536 init_curr_operand_mode (void)
538 int nop
= curr_static_id
->n_operands
;
539 for (int i
= 0; i
< nop
; i
++)
541 machine_mode mode
= GET_MODE (*curr_id
->operand_loc
[i
]);
542 if (mode
== VOIDmode
)
544 /* The .md mode for address operands is the mode of the
545 addressed value rather than the mode of the address itself. */
546 if (curr_id
->icode
>= 0 && curr_static_id
->operand
[i
].is_address
)
549 mode
= curr_static_id
->operand
[i
].mode
;
551 curr_operand_mode
[i
] = mode
;
557 /* The page contains code to reuse input reloads. */
559 /* Structure describes input reload of the current insns. */
562 /* Reloaded value. */
564 /* Reload pseudo used. */
568 /* The number of elements in the following array. */
569 static int curr_insn_input_reloads_num
;
570 /* Array containing info about input reloads. It is used to find the
571 same input reload and reuse the reload pseudo in this case. */
572 static struct input_reload curr_insn_input_reloads
[LRA_MAX_INSN_RELOADS
];
574 /* Initiate data concerning reuse of input reloads for the current
577 init_curr_insn_input_reloads (void)
579 curr_insn_input_reloads_num
= 0;
582 /* Create a new pseudo using MODE, RCLASS, ORIGINAL or reuse already
583 created input reload pseudo (only if TYPE is not OP_OUT). Don't
584 reuse pseudo if IN_SUBREG_P is true and the reused pseudo should be
585 wrapped up in SUBREG. The result pseudo is returned through
586 RESULT_REG. Return TRUE if we created a new pseudo, FALSE if we
587 reused the already created input reload pseudo. Use TITLE to
588 describe new registers for debug purposes. */
590 get_reload_reg (enum op_type type
, machine_mode mode
, rtx original
,
591 enum reg_class rclass
, bool in_subreg_p
,
592 const char *title
, rtx
*result_reg
)
595 enum reg_class new_class
;
600 = lra_create_new_reg_with_unique_value (mode
, original
, rclass
, title
);
603 /* Prevent reuse value of expression with side effects,
604 e.g. volatile memory. */
605 if (! side_effects_p (original
))
606 for (i
= 0; i
< curr_insn_input_reloads_num
; i
++)
607 if (rtx_equal_p (curr_insn_input_reloads
[i
].input
, original
)
608 && in_class_p (curr_insn_input_reloads
[i
].reg
, rclass
, &new_class
))
610 rtx reg
= curr_insn_input_reloads
[i
].reg
;
612 /* If input is equal to original and both are VOIDmode,
613 GET_MODE (reg) might be still different from mode.
614 Ensure we don't return *result_reg with wrong mode. */
615 if (GET_MODE (reg
) != mode
)
619 if (GET_MODE_SIZE (GET_MODE (reg
)) < GET_MODE_SIZE (mode
))
621 reg
= lowpart_subreg (mode
, reg
, GET_MODE (reg
));
622 if (reg
== NULL_RTX
|| GET_CODE (reg
) != SUBREG
)
626 if (lra_dump_file
!= NULL
)
628 fprintf (lra_dump_file
, " Reuse r%d for reload ", regno
);
629 dump_value_slim (lra_dump_file
, original
, 1);
631 if (new_class
!= lra_get_allocno_class (regno
))
632 lra_change_class (regno
, new_class
, ", change to", false);
633 if (lra_dump_file
!= NULL
)
634 fprintf (lra_dump_file
, "\n");
637 *result_reg
= lra_create_new_reg (mode
, original
, rclass
, title
);
638 lra_assert (curr_insn_input_reloads_num
< LRA_MAX_INSN_RELOADS
);
639 curr_insn_input_reloads
[curr_insn_input_reloads_num
].input
= original
;
640 curr_insn_input_reloads
[curr_insn_input_reloads_num
++].reg
= *result_reg
;
646 /* The page contains code to extract memory address parts. */
648 /* Wrapper around REGNO_OK_FOR_INDEX_P, to allow pseudos. */
650 ok_for_index_p_nonstrict (rtx reg
)
652 unsigned regno
= REGNO (reg
);
654 return regno
>= FIRST_PSEUDO_REGISTER
|| REGNO_OK_FOR_INDEX_P (regno
);
657 /* A version of regno_ok_for_base_p for use here, when all pseudos
658 should count as OK. Arguments as for regno_ok_for_base_p. */
660 ok_for_base_p_nonstrict (rtx reg
, machine_mode mode
, addr_space_t as
,
661 enum rtx_code outer_code
, enum rtx_code index_code
)
663 unsigned regno
= REGNO (reg
);
665 if (regno
>= FIRST_PSEUDO_REGISTER
)
667 return ok_for_base_p_1 (regno
, mode
, as
, outer_code
, index_code
);
672 /* The page contains major code to choose the current insn alternative
673 and generate reloads for it. */
675 /* Return the offset from REGNO of the least significant register
678 This function is used to tell whether two registers satisfy
679 a matching constraint. (reg:MODE1 REGNO1) matches (reg:MODE2 REGNO2) if:
681 REGNO1 + lra_constraint_offset (REGNO1, MODE1)
682 == REGNO2 + lra_constraint_offset (REGNO2, MODE2) */
684 lra_constraint_offset (int regno
, machine_mode mode
)
686 lra_assert (regno
< FIRST_PSEUDO_REGISTER
);
687 if (WORDS_BIG_ENDIAN
&& GET_MODE_SIZE (mode
) > UNITS_PER_WORD
688 && SCALAR_INT_MODE_P (mode
))
689 return hard_regno_nregs
[regno
][mode
] - 1;
693 /* Like rtx_equal_p except that it allows a REG and a SUBREG to match
694 if they are the same hard reg, and has special hacks for
695 auto-increment and auto-decrement. This is specifically intended for
696 process_alt_operands to use in determining whether two operands
697 match. X is the operand whose number is the lower of the two.
699 It is supposed that X is the output operand and Y is the input
700 operand. Y_HARD_REGNO is the final hard regno of register Y or
701 register in subreg Y as we know it now. Otherwise, it is a
704 operands_match_p (rtx x
, rtx y
, int y_hard_regno
)
707 RTX_CODE code
= GET_CODE (x
);
712 if ((code
== REG
|| (code
== SUBREG
&& REG_P (SUBREG_REG (x
))))
713 && (REG_P (y
) || (GET_CODE (y
) == SUBREG
&& REG_P (SUBREG_REG (y
)))))
717 i
= get_hard_regno (x
);
721 if ((j
= y_hard_regno
) < 0)
724 i
+= lra_constraint_offset (i
, GET_MODE (x
));
725 j
+= lra_constraint_offset (j
, GET_MODE (y
));
730 /* If two operands must match, because they are really a single
731 operand of an assembler insn, then two post-increments are invalid
732 because the assembler insn would increment only once. On the
733 other hand, a post-increment matches ordinary indexing if the
734 post-increment is the output operand. */
735 if (code
== POST_DEC
|| code
== POST_INC
|| code
== POST_MODIFY
)
736 return operands_match_p (XEXP (x
, 0), y
, y_hard_regno
);
738 /* Two pre-increments are invalid because the assembler insn would
739 increment only once. On the other hand, a pre-increment matches
740 ordinary indexing if the pre-increment is the input operand. */
741 if (GET_CODE (y
) == PRE_DEC
|| GET_CODE (y
) == PRE_INC
742 || GET_CODE (y
) == PRE_MODIFY
)
743 return operands_match_p (x
, XEXP (y
, 0), -1);
747 if (code
== REG
&& REG_P (y
))
748 return REGNO (x
) == REGNO (y
);
750 if (code
== REG
&& GET_CODE (y
) == SUBREG
&& REG_P (SUBREG_REG (y
))
751 && x
== SUBREG_REG (y
))
753 if (GET_CODE (y
) == REG
&& code
== SUBREG
&& REG_P (SUBREG_REG (x
))
754 && SUBREG_REG (x
) == y
)
757 /* Now we have disposed of all the cases in which different rtx
759 if (code
!= GET_CODE (y
))
762 /* (MULT:SI x y) and (MULT:HI x y) are NOT equivalent. */
763 if (GET_MODE (x
) != GET_MODE (y
))
772 return LABEL_REF_LABEL (x
) == LABEL_REF_LABEL (y
);
774 return XSTR (x
, 0) == XSTR (y
, 0);
780 /* Compare the elements. If any pair of corresponding elements fail
781 to match, return false for the whole things. */
783 fmt
= GET_RTX_FORMAT (code
);
784 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
790 if (XWINT (x
, i
) != XWINT (y
, i
))
795 if (XINT (x
, i
) != XINT (y
, i
))
800 val
= operands_match_p (XEXP (x
, i
), XEXP (y
, i
), -1);
809 if (XVECLEN (x
, i
) != XVECLEN (y
, i
))
811 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; --j
)
813 val
= operands_match_p (XVECEXP (x
, i
, j
), XVECEXP (y
, i
, j
), -1);
819 /* It is believed that rtx's at this level will never
820 contain anything but integers and other rtx's, except for
821 within LABEL_REFs and SYMBOL_REFs. */
829 /* True if X is a constant that can be forced into the constant pool.
830 MODE is the mode of the operand, or VOIDmode if not known. */
831 #define CONST_POOL_OK_P(MODE, X) \
832 ((MODE) != VOIDmode \
834 && GET_CODE (X) != HIGH \
835 && !targetm.cannot_force_const_mem (MODE, X))
837 /* True if C is a non-empty register class that has too few registers
838 to be safely used as a reload target class. */
839 #define SMALL_REGISTER_CLASS_P(C) \
840 (ira_class_hard_regs_num [(C)] == 1 \
841 || (ira_class_hard_regs_num [(C)] >= 1 \
842 && targetm.class_likely_spilled_p (C)))
844 /* If REG is a reload pseudo, try to make its class satisfying CL. */
846 narrow_reload_pseudo_class (rtx reg
, enum reg_class cl
)
848 enum reg_class rclass
;
850 /* Do not make more accurate class from reloads generated. They are
851 mostly moves with a lot of constraints. Making more accurate
852 class may results in very narrow class and impossibility of find
853 registers for several reloads of one insn. */
854 if (INSN_UID (curr_insn
) >= new_insn_uid_start
)
856 if (GET_CODE (reg
) == SUBREG
)
857 reg
= SUBREG_REG (reg
);
858 if (! REG_P (reg
) || (int) REGNO (reg
) < new_regno_start
)
860 if (in_class_p (reg
, cl
, &rclass
) && rclass
!= cl
)
861 lra_change_class (REGNO (reg
), rclass
, " Change to", true);
864 /* Generate reloads for matching OUT and INS (array of input operand
865 numbers with end marker -1) with reg class GOAL_CLASS. Add input
866 and output reloads correspondingly to the lists *BEFORE and *AFTER.
867 OUT might be negative. In this case we generate input reloads for
868 matched input operands INS. */
870 match_reload (signed char out
, signed char *ins
, enum reg_class goal_class
,
871 rtx_insn
**before
, rtx_insn
**after
)
874 rtx new_in_reg
, new_out_reg
, reg
, clobber
;
875 machine_mode inmode
, outmode
;
876 rtx in_rtx
= *curr_id
->operand_loc
[ins
[0]];
877 rtx out_rtx
= out
< 0 ? in_rtx
: *curr_id
->operand_loc
[out
];
879 inmode
= curr_operand_mode
[ins
[0]];
880 outmode
= out
< 0 ? inmode
: curr_operand_mode
[out
];
881 push_to_sequence (*before
);
882 if (inmode
!= outmode
)
884 if (GET_MODE_SIZE (inmode
) > GET_MODE_SIZE (outmode
))
887 = lra_create_new_reg_with_unique_value (inmode
, in_rtx
,
889 if (SCALAR_INT_MODE_P (inmode
))
890 new_out_reg
= gen_lowpart_SUBREG (outmode
, reg
);
892 new_out_reg
= gen_rtx_SUBREG (outmode
, reg
, 0);
893 LRA_SUBREG_P (new_out_reg
) = 1;
894 /* If the input reg is dying here, we can use the same hard
895 register for REG and IN_RTX. We do it only for original
896 pseudos as reload pseudos can die although original
897 pseudos still live where reload pseudos dies. */
898 if (REG_P (in_rtx
) && (int) REGNO (in_rtx
) < lra_new_regno_start
899 && find_regno_note (curr_insn
, REG_DEAD
, REGNO (in_rtx
)))
900 lra_assign_reg_val (REGNO (in_rtx
), REGNO (reg
));
905 = lra_create_new_reg_with_unique_value (outmode
, out_rtx
,
907 if (SCALAR_INT_MODE_P (outmode
))
908 new_in_reg
= gen_lowpart_SUBREG (inmode
, reg
);
910 new_in_reg
= gen_rtx_SUBREG (inmode
, reg
, 0);
911 /* NEW_IN_REG is non-paradoxical subreg. We don't want
912 NEW_OUT_REG living above. We add clobber clause for
913 this. This is just a temporary clobber. We can remove
914 it at the end of LRA work. */
915 clobber
= emit_clobber (new_out_reg
);
916 LRA_TEMP_CLOBBER_P (PATTERN (clobber
)) = 1;
917 LRA_SUBREG_P (new_in_reg
) = 1;
918 if (GET_CODE (in_rtx
) == SUBREG
)
920 rtx subreg_reg
= SUBREG_REG (in_rtx
);
922 /* If SUBREG_REG is dying here and sub-registers IN_RTX
923 and NEW_IN_REG are similar, we can use the same hard
924 register for REG and SUBREG_REG. */
925 if (REG_P (subreg_reg
)
926 && (int) REGNO (subreg_reg
) < lra_new_regno_start
927 && GET_MODE (subreg_reg
) == outmode
928 && SUBREG_BYTE (in_rtx
) == SUBREG_BYTE (new_in_reg
)
929 && find_regno_note (curr_insn
, REG_DEAD
, REGNO (subreg_reg
)))
930 lra_assign_reg_val (REGNO (subreg_reg
), REGNO (reg
));
936 /* Pseudos have values -- see comments for lra_reg_info.
937 Different pseudos with the same value do not conflict even if
938 they live in the same place. When we create a pseudo we
939 assign value of original pseudo (if any) from which we
940 created the new pseudo. If we create the pseudo from the
941 input pseudo, the new pseudo will no conflict with the input
942 pseudo which is wrong when the input pseudo lives after the
943 insn and as the new pseudo value is changed by the insn
944 output. Therefore we create the new pseudo from the output.
946 We cannot reuse the current output register because we might
947 have a situation like "a <- a op b", where the constraints
948 force the second input operand ("b") to match the output
949 operand ("a"). "b" must then be copied into a new register
950 so that it doesn't clobber the current value of "a". */
952 new_in_reg
= new_out_reg
953 = lra_create_new_reg_with_unique_value (outmode
, out_rtx
,
956 /* In operand can be got from transformations before processing insn
957 constraints. One example of such transformations is subreg
958 reloading (see function simplify_operand_subreg). The new
959 pseudos created by the transformations might have inaccurate
960 class (ALL_REGS) and we should make their classes more
962 narrow_reload_pseudo_class (in_rtx
, goal_class
);
963 lra_emit_move (copy_rtx (new_in_reg
), in_rtx
);
964 *before
= get_insns ();
966 for (i
= 0; (in
= ins
[i
]) >= 0; i
++)
969 (GET_MODE (*curr_id
->operand_loc
[in
]) == VOIDmode
970 || GET_MODE (new_in_reg
) == GET_MODE (*curr_id
->operand_loc
[in
]));
971 *curr_id
->operand_loc
[in
] = new_in_reg
;
973 lra_update_dups (curr_id
, ins
);
976 /* See a comment for the input operand above. */
977 narrow_reload_pseudo_class (out_rtx
, goal_class
);
978 if (find_reg_note (curr_insn
, REG_UNUSED
, out_rtx
) == NULL_RTX
)
981 lra_emit_move (out_rtx
, copy_rtx (new_out_reg
));
983 *after
= get_insns ();
986 *curr_id
->operand_loc
[out
] = new_out_reg
;
987 lra_update_dup (curr_id
, out
);
990 /* Return register class which is union of all reg classes in insn
991 constraint alternative string starting with P. */
992 static enum reg_class
993 reg_class_from_constraints (const char *p
)
996 enum reg_class op_class
= NO_REGS
;
999 switch ((c
= *p
, len
= CONSTRAINT_LEN (c
, p
)), c
)
1006 op_class
= reg_class_subunion
[op_class
][GENERAL_REGS
];
1010 enum constraint_num cn
= lookup_constraint (p
);
1011 enum reg_class cl
= reg_class_for_constraint (cn
);
1014 if (insn_extra_address_constraint (cn
))
1016 = (reg_class_subunion
1017 [op_class
][base_reg_class (VOIDmode
, ADDR_SPACE_GENERIC
,
1018 ADDRESS
, SCRATCH
)]);
1022 op_class
= reg_class_subunion
[op_class
][cl
];
1025 while ((p
+= len
), c
);
1029 /* If OP is a register, return the class of the register as per
1030 get_reg_class, otherwise return NO_REGS. */
1031 static inline enum reg_class
1032 get_op_class (rtx op
)
1034 return REG_P (op
) ? get_reg_class (REGNO (op
)) : NO_REGS
;
1037 /* Return generated insn mem_pseudo:=val if TO_P or val:=mem_pseudo
1038 otherwise. If modes of MEM_PSEUDO and VAL are different, use
1039 SUBREG for VAL to make them equal. */
1041 emit_spill_move (bool to_p
, rtx mem_pseudo
, rtx val
)
1043 if (GET_MODE (mem_pseudo
) != GET_MODE (val
))
1045 /* Usually size of mem_pseudo is greater than val size but in
1046 rare cases it can be less as it can be defined by target
1047 dependent macro HARD_REGNO_CALLER_SAVE_MODE. */
1050 val
= gen_rtx_SUBREG (GET_MODE (mem_pseudo
),
1051 GET_CODE (val
) == SUBREG
? SUBREG_REG (val
) : val
,
1053 LRA_SUBREG_P (val
) = 1;
1057 mem_pseudo
= gen_lowpart_SUBREG (GET_MODE (val
), mem_pseudo
);
1058 LRA_SUBREG_P (mem_pseudo
) = 1;
1061 return to_p
? gen_move_insn (mem_pseudo
, val
)
1062 : gen_move_insn (val
, mem_pseudo
);
1065 /* Process a special case insn (register move), return true if we
1066 don't need to process it anymore. INSN should be a single set
1067 insn. Set up that RTL was changed through CHANGE_P and macro
1068 SECONDARY_MEMORY_NEEDED says to use secondary memory through
1071 check_and_process_move (bool *change_p
, bool *sec_mem_p ATTRIBUTE_UNUSED
)
1074 rtx dest
, src
, dreg
, sreg
, new_reg
, scratch_reg
;
1076 enum reg_class dclass
, sclass
, secondary_class
;
1077 secondary_reload_info sri
;
1079 lra_assert (curr_insn_set
!= NULL_RTX
);
1080 dreg
= dest
= SET_DEST (curr_insn_set
);
1081 sreg
= src
= SET_SRC (curr_insn_set
);
1082 if (GET_CODE (dest
) == SUBREG
)
1083 dreg
= SUBREG_REG (dest
);
1084 if (GET_CODE (src
) == SUBREG
)
1085 sreg
= SUBREG_REG (src
);
1086 if (! (REG_P (dreg
) || MEM_P (dreg
)) || ! (REG_P (sreg
) || MEM_P (sreg
)))
1088 sclass
= dclass
= NO_REGS
;
1090 dclass
= get_reg_class (REGNO (dreg
));
1091 if (dclass
== ALL_REGS
)
1092 /* ALL_REGS is used for new pseudos created by transformations
1093 like reload of SUBREG_REG (see function
1094 simplify_operand_subreg). We don't know their class yet. We
1095 should figure out the class from processing the insn
1096 constraints not in this fast path function. Even if ALL_REGS
1097 were a right class for the pseudo, secondary_... hooks usually
1098 are not define for ALL_REGS. */
1101 sclass
= get_reg_class (REGNO (sreg
));
1102 if (sclass
== ALL_REGS
)
1103 /* See comments above. */
1105 if (sclass
== NO_REGS
&& dclass
== NO_REGS
)
1107 #ifdef SECONDARY_MEMORY_NEEDED
1108 if (SECONDARY_MEMORY_NEEDED (sclass
, dclass
, GET_MODE (src
))
1109 #ifdef SECONDARY_MEMORY_NEEDED_MODE
1110 && ((sclass
!= NO_REGS
&& dclass
!= NO_REGS
)
1111 || GET_MODE (src
) != SECONDARY_MEMORY_NEEDED_MODE (GET_MODE (src
)))
1119 if (! REG_P (dreg
) || ! REG_P (sreg
))
1121 sri
.prev_sri
= NULL
;
1122 sri
.icode
= CODE_FOR_nothing
;
1124 secondary_class
= NO_REGS
;
1125 /* Set up hard register for a reload pseudo for hook
1126 secondary_reload because some targets just ignore unassigned
1127 pseudos in the hook. */
1128 if (dclass
!= NO_REGS
&& lra_get_regno_hard_regno (REGNO (dreg
)) < 0)
1130 dregno
= REGNO (dreg
);
1131 reg_renumber
[dregno
] = ira_class_hard_regs
[dclass
][0];
1135 if (sclass
!= NO_REGS
&& lra_get_regno_hard_regno (REGNO (sreg
)) < 0)
1137 sregno
= REGNO (sreg
);
1138 reg_renumber
[sregno
] = ira_class_hard_regs
[sclass
][0];
1142 if (sclass
!= NO_REGS
)
1144 = (enum reg_class
) targetm
.secondary_reload (false, dest
,
1145 (reg_class_t
) sclass
,
1146 GET_MODE (src
), &sri
);
1147 if (sclass
== NO_REGS
1148 || ((secondary_class
!= NO_REGS
|| sri
.icode
!= CODE_FOR_nothing
)
1149 && dclass
!= NO_REGS
))
1151 enum reg_class old_sclass
= secondary_class
;
1152 secondary_reload_info old_sri
= sri
;
1154 sri
.prev_sri
= NULL
;
1155 sri
.icode
= CODE_FOR_nothing
;
1158 = (enum reg_class
) targetm
.secondary_reload (true, src
,
1159 (reg_class_t
) dclass
,
1160 GET_MODE (src
), &sri
);
1161 /* Check the target hook consistency. */
1163 ((secondary_class
== NO_REGS
&& sri
.icode
== CODE_FOR_nothing
)
1164 || (old_sclass
== NO_REGS
&& old_sri
.icode
== CODE_FOR_nothing
)
1165 || (secondary_class
== old_sclass
&& sri
.icode
== old_sri
.icode
));
1168 reg_renumber
[sregno
] = -1;
1170 reg_renumber
[dregno
] = -1;
1171 if (secondary_class
== NO_REGS
&& sri
.icode
== CODE_FOR_nothing
)
1175 if (secondary_class
!= NO_REGS
)
1176 new_reg
= lra_create_new_reg_with_unique_value (GET_MODE (src
), NULL_RTX
,
1180 if (sri
.icode
== CODE_FOR_nothing
)
1181 lra_emit_move (new_reg
, src
);
1184 enum reg_class scratch_class
;
1186 scratch_class
= (reg_class_from_constraints
1187 (insn_data
[sri
.icode
].operand
[2].constraint
));
1188 scratch_reg
= (lra_create_new_reg_with_unique_value
1189 (insn_data
[sri
.icode
].operand
[2].mode
, NULL_RTX
,
1190 scratch_class
, "scratch"));
1191 emit_insn (GEN_FCN (sri
.icode
) (new_reg
!= NULL_RTX
? new_reg
: dest
,
1194 before
= get_insns ();
1196 lra_process_new_insns (curr_insn
, before
, NULL
, "Inserting the move");
1197 if (new_reg
!= NULL_RTX
)
1198 SET_SRC (curr_insn_set
) = new_reg
;
1201 if (lra_dump_file
!= NULL
)
1203 fprintf (lra_dump_file
, "Deleting move %u\n", INSN_UID (curr_insn
));
1204 dump_insn_slim (lra_dump_file
, curr_insn
);
1206 lra_set_insn_deleted (curr_insn
);
1212 /* The following data describe the result of process_alt_operands.
1213 The data are used in curr_insn_transform to generate reloads. */
1215 /* The chosen reg classes which should be used for the corresponding
1217 static enum reg_class goal_alt
[MAX_RECOG_OPERANDS
];
1218 /* True if the operand should be the same as another operand and that
1219 other operand does not need a reload. */
1220 static bool goal_alt_match_win
[MAX_RECOG_OPERANDS
];
1221 /* True if the operand does not need a reload. */
1222 static bool goal_alt_win
[MAX_RECOG_OPERANDS
];
1223 /* True if the operand can be offsetable memory. */
1224 static bool goal_alt_offmemok
[MAX_RECOG_OPERANDS
];
1225 /* The number of an operand to which given operand can be matched to. */
1226 static int goal_alt_matches
[MAX_RECOG_OPERANDS
];
1227 /* The number of elements in the following array. */
1228 static int goal_alt_dont_inherit_ops_num
;
1229 /* Numbers of operands whose reload pseudos should not be inherited. */
1230 static int goal_alt_dont_inherit_ops
[MAX_RECOG_OPERANDS
];
1231 /* True if the insn commutative operands should be swapped. */
1232 static bool goal_alt_swapped
;
1233 /* The chosen insn alternative. */
1234 static int goal_alt_number
;
1236 /* The following five variables are used to choose the best insn
1237 alternative. They reflect final characteristics of the best
1240 /* Number of necessary reloads and overall cost reflecting the
1241 previous value and other unpleasantness of the best alternative. */
1242 static int best_losers
, best_overall
;
1243 /* Overall number hard registers used for reloads. For example, on
1244 some targets we need 2 general registers to reload DFmode and only
1245 one floating point register. */
1246 static int best_reload_nregs
;
1247 /* Overall number reflecting distances of previous reloading the same
1248 value. The distances are counted from the current BB start. It is
1249 used to improve inheritance chances. */
1250 static int best_reload_sum
;
1252 /* True if the current insn should have no correspondingly input or
1254 static bool no_input_reloads_p
, no_output_reloads_p
;
1256 /* True if we swapped the commutative operands in the current
1258 static int curr_swapped
;
1260 /* if CHECK_ONLY_P is false, arrange for address element *LOC to be a
1261 register of class CL. Add any input reloads to list BEFORE. AFTER
1262 is nonnull if *LOC is an automodified value; handle that case by
1263 adding the required output reloads to list AFTER. Return true if
1264 the RTL was changed.
1266 if CHECK_ONLY_P is true, check that the *LOC is a correct address
1267 register. Return false if the address register is correct. */
1269 process_addr_reg (rtx
*loc
, bool check_only_p
, rtx_insn
**before
, rtx_insn
**after
,
1273 enum reg_class rclass
, new_class
;
1277 bool subreg_p
, before_p
= false;
1279 subreg_p
= GET_CODE (*loc
) == SUBREG
;
1281 loc
= &SUBREG_REG (*loc
);
1283 mode
= GET_MODE (reg
);
1288 /* Always reload memory in an address even if the target supports
1290 new_reg
= lra_create_new_reg_with_unique_value (mode
, reg
, cl
, "address");
1295 regno
= REGNO (reg
);
1296 rclass
= get_reg_class (regno
);
1298 && (*loc
= get_equiv_with_elimination (reg
, curr_insn
)) != reg
)
1300 if (lra_dump_file
!= NULL
)
1302 fprintf (lra_dump_file
,
1303 "Changing pseudo %d in address of insn %u on equiv ",
1304 REGNO (reg
), INSN_UID (curr_insn
));
1305 dump_value_slim (lra_dump_file
, *loc
, 1);
1306 fprintf (lra_dump_file
, "\n");
1308 *loc
= copy_rtx (*loc
);
1310 if (*loc
!= reg
|| ! in_class_p (reg
, cl
, &new_class
))
1315 if (get_reload_reg (after
== NULL
? OP_IN
: OP_INOUT
,
1316 mode
, reg
, cl
, subreg_p
, "address", &new_reg
))
1319 else if (new_class
!= NO_REGS
&& rclass
!= new_class
)
1323 lra_change_class (regno
, new_class
, " Change to", true);
1331 push_to_sequence (*before
);
1332 lra_emit_move (new_reg
, reg
);
1333 *before
= get_insns ();
1340 lra_emit_move (reg
, new_reg
);
1342 *after
= get_insns ();
1348 /* Insert move insn in simplify_operand_subreg. BEFORE returns
1349 the insn to be inserted before curr insn. AFTER returns the
1350 the insn to be inserted after curr insn. ORIGREG and NEWREG
1351 are the original reg and new reg for reload. */
1353 insert_move_for_subreg (rtx_insn
**before
, rtx_insn
**after
, rtx origreg
,
1358 push_to_sequence (*before
);
1359 lra_emit_move (newreg
, origreg
);
1360 *before
= get_insns ();
1366 lra_emit_move (origreg
, newreg
);
1368 *after
= get_insns ();
1373 static int valid_address_p (machine_mode mode
, rtx addr
, addr_space_t as
);
1375 /* Make reloads for subreg in operand NOP with internal subreg mode
1376 REG_MODE, add new reloads for further processing. Return true if
1377 any change was done. */
1379 simplify_operand_subreg (int nop
, machine_mode reg_mode
)
1382 rtx_insn
*before
, *after
;
1383 machine_mode mode
, innermode
;
1385 rtx operand
= *curr_id
->operand_loc
[nop
];
1386 enum reg_class regclass
;
1389 before
= after
= NULL
;
1391 if (GET_CODE (operand
) != SUBREG
)
1394 mode
= GET_MODE (operand
);
1395 reg
= SUBREG_REG (operand
);
1396 innermode
= GET_MODE (reg
);
1397 type
= curr_static_id
->operand
[nop
].type
;
1398 /* If we change address for paradoxical subreg of memory, the
1399 address might violate the necessary alignment or the access might
1400 be slow. So take this into consideration. We should not worry
1401 about access beyond allocated memory for paradoxical memory
1402 subregs as we don't substitute such equiv memory (see processing
1403 equivalences in function lra_constraints) and because for spilled
1404 pseudos we allocate stack memory enough for the biggest
1405 corresponding paradoxical subreg. */
1407 && (! SLOW_UNALIGNED_ACCESS (mode
, MEM_ALIGN (reg
))
1408 || MEM_ALIGN (reg
) >= GET_MODE_ALIGNMENT (mode
)))
1410 rtx subst
, old
= *curr_id
->operand_loc
[nop
];
1412 alter_subreg (curr_id
->operand_loc
[nop
], false);
1413 subst
= *curr_id
->operand_loc
[nop
];
1414 lra_assert (MEM_P (subst
));
1415 if (! valid_address_p (innermode
, XEXP (reg
, 0),
1416 MEM_ADDR_SPACE (reg
))
1417 || valid_address_p (GET_MODE (subst
), XEXP (subst
, 0),
1418 MEM_ADDR_SPACE (subst
)))
1420 /* If the address was valid and became invalid, prefer to reload
1421 the memory. Typical case is when the index scale should
1422 correspond the memory. */
1423 *curr_id
->operand_loc
[nop
] = old
;
1425 else if (REG_P (reg
) && REGNO (reg
) < FIRST_PSEUDO_REGISTER
)
1427 alter_subreg (curr_id
->operand_loc
[nop
], false);
1430 else if (CONSTANT_P (reg
))
1432 /* Try to simplify subreg of constant. It is usually result of
1433 equivalence substitution. */
1434 if (innermode
== VOIDmode
1435 && (innermode
= original_subreg_reg_mode
[nop
]) == VOIDmode
)
1436 innermode
= curr_static_id
->operand
[nop
].mode
;
1437 if ((new_reg
= simplify_subreg (mode
, reg
, innermode
,
1438 SUBREG_BYTE (operand
))) != NULL_RTX
)
1440 *curr_id
->operand_loc
[nop
] = new_reg
;
1444 /* Put constant into memory when we have mixed modes. It generates
1445 a better code in most cases as it does not need a secondary
1446 reload memory. It also prevents LRA looping when LRA is using
1447 secondary reload memory again and again. */
1448 if (CONSTANT_P (reg
) && CONST_POOL_OK_P (reg_mode
, reg
)
1449 && SCALAR_INT_MODE_P (reg_mode
) != SCALAR_INT_MODE_P (mode
))
1451 SUBREG_REG (operand
) = force_const_mem (reg_mode
, reg
);
1452 alter_subreg (curr_id
->operand_loc
[nop
], false);
1455 /* Force a reload of the SUBREG_REG if this is a constant or PLUS or
1456 if there may be a problem accessing OPERAND in the outer
1459 && REGNO (reg
) >= FIRST_PSEUDO_REGISTER
1460 && (hard_regno
= lra_get_regno_hard_regno (REGNO (reg
))) >= 0
1461 /* Don't reload paradoxical subregs because we could be looping
1462 having repeatedly final regno out of hard regs range. */
1463 && (hard_regno_nregs
[hard_regno
][innermode
]
1464 >= hard_regno_nregs
[hard_regno
][mode
])
1465 && simplify_subreg_regno (hard_regno
, innermode
,
1466 SUBREG_BYTE (operand
), mode
) < 0
1467 /* Don't reload subreg for matching reload. It is actually
1468 valid subreg in LRA. */
1469 && ! LRA_SUBREG_P (operand
))
1470 || CONSTANT_P (reg
) || GET_CODE (reg
) == PLUS
|| MEM_P (reg
))
1472 enum reg_class rclass
;
1475 /* There is a big probability that we will get the same class
1476 for the new pseudo and we will get the same insn which
1477 means infinite looping. So spill the new pseudo. */
1480 /* The class will be defined later in curr_insn_transform. */
1482 = (enum reg_class
) targetm
.preferred_reload_class (reg
, ALL_REGS
);
1484 if (get_reload_reg (curr_static_id
->operand
[nop
].type
, reg_mode
, reg
,
1485 rclass
, TRUE
, "subreg reg", &new_reg
))
1487 bool insert_before
, insert_after
;
1488 bitmap_set_bit (&lra_subreg_reload_pseudos
, REGNO (new_reg
));
1490 insert_before
= (type
!= OP_OUT
1491 || GET_MODE_SIZE (innermode
) > GET_MODE_SIZE (mode
));
1492 insert_after
= (type
!= OP_IN
);
1493 insert_move_for_subreg (insert_before
? &before
: NULL
,
1494 insert_after
? &after
: NULL
,
1497 SUBREG_REG (operand
) = new_reg
;
1498 lra_process_new_insns (curr_insn
, before
, after
,
1499 "Inserting subreg reload");
1502 /* Force a reload for a paradoxical subreg. For paradoxical subreg,
1503 IRA allocates hardreg to the inner pseudo reg according to its mode
1504 instead of the outermode, so the size of the hardreg may not be enough
1505 to contain the outermode operand, in that case we may need to insert
1506 reload for the reg. For the following two types of paradoxical subreg,
1507 we need to insert reload:
1508 1. If the op_type is OP_IN, and the hardreg could not be paired with
1509 other hardreg to contain the outermode operand
1510 (checked by in_hard_reg_set_p), we need to insert the reload.
1511 2. If the op_type is OP_OUT or OP_INOUT.
1513 Here is a paradoxical subreg example showing how the reload is generated:
1515 (insn 5 4 7 2 (set (reg:TI 106 [ __comp ])
1516 (subreg:TI (reg:DI 107 [ __comp ]) 0)) {*movti_internal_rex64}
1518 In IRA, reg107 is allocated to a DImode hardreg. We use x86-64 as example
1519 here, if reg107 is assigned to hardreg R15, because R15 is the last
1520 hardreg, compiler cannot find another hardreg to pair with R15 to
1521 contain TImode data. So we insert a TImode reload reg180 for it.
1522 After reload is inserted:
1524 (insn 283 0 0 (set (subreg:DI (reg:TI 180 [orig:107 __comp ] [107]) 0)
1525 (reg:DI 107 [ __comp ])) -1
1526 (insn 5 4 7 2 (set (reg:TI 106 [ __comp ])
1527 (subreg:TI (reg:TI 180 [orig:107 __comp ] [107]) 0)) {*movti_internal_rex64}
1529 Two reload hard registers will be allocated to reg180 to save TImode data
1531 else if (REG_P (reg
)
1532 && REGNO (reg
) >= FIRST_PSEUDO_REGISTER
1533 && (hard_regno
= lra_get_regno_hard_regno (REGNO (reg
))) >= 0
1534 && (hard_regno_nregs
[hard_regno
][innermode
]
1535 < hard_regno_nregs
[hard_regno
][mode
])
1536 && (regclass
= lra_get_allocno_class (REGNO (reg
)))
1538 || !in_hard_reg_set_p (reg_class_contents
[regclass
],
1541 /* The class will be defined later in curr_insn_transform. */
1542 enum reg_class rclass
1543 = (enum reg_class
) targetm
.preferred_reload_class (reg
, ALL_REGS
);
1545 if (get_reload_reg (curr_static_id
->operand
[nop
].type
, mode
, reg
,
1546 rclass
, TRUE
, "paradoxical subreg", &new_reg
))
1549 bool insert_before
, insert_after
;
1551 PUT_MODE (new_reg
, mode
);
1552 subreg
= simplify_gen_subreg (innermode
, new_reg
, mode
, 0);
1553 bitmap_set_bit (&lra_subreg_reload_pseudos
, REGNO (new_reg
));
1555 insert_before
= (type
!= OP_OUT
);
1556 insert_after
= (type
!= OP_IN
);
1557 insert_move_for_subreg (insert_before
? &before
: NULL
,
1558 insert_after
? &after
: NULL
,
1561 SUBREG_REG (operand
) = new_reg
;
1562 lra_process_new_insns (curr_insn
, before
, after
,
1563 "Inserting paradoxical subreg reload");
1569 /* Return TRUE if X refers for a hard register from SET. */
1571 uses_hard_regs_p (rtx x
, HARD_REG_SET set
)
1573 int i
, j
, x_hard_regno
;
1580 code
= GET_CODE (x
);
1581 mode
= GET_MODE (x
);
1585 code
= GET_CODE (x
);
1586 if (GET_MODE_SIZE (GET_MODE (x
)) > GET_MODE_SIZE (mode
))
1587 mode
= GET_MODE (x
);
1592 x_hard_regno
= get_hard_regno (x
);
1593 return (x_hard_regno
>= 0
1594 && overlaps_hard_reg_set_p (set
, mode
, x_hard_regno
));
1598 struct address_info ad
;
1600 decompose_mem_address (&ad
, x
);
1601 if (ad
.base_term
!= NULL
&& uses_hard_regs_p (*ad
.base_term
, set
))
1603 if (ad
.index_term
!= NULL
&& uses_hard_regs_p (*ad
.index_term
, set
))
1606 fmt
= GET_RTX_FORMAT (code
);
1607 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
1611 if (uses_hard_regs_p (XEXP (x
, i
), set
))
1614 else if (fmt
[i
] == 'E')
1616 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
1617 if (uses_hard_regs_p (XVECEXP (x
, i
, j
), set
))
1624 /* Return true if OP is a spilled pseudo. */
1626 spilled_pseudo_p (rtx op
)
1629 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
&& in_mem_p (REGNO (op
)));
1632 /* Return true if X is a general constant. */
1634 general_constant_p (rtx x
)
1636 return CONSTANT_P (x
) && (! flag_pic
|| LEGITIMATE_PIC_OPERAND_P (x
));
1640 reg_in_class_p (rtx reg
, enum reg_class cl
)
1643 return get_reg_class (REGNO (reg
)) == NO_REGS
;
1644 return in_class_p (reg
, cl
, NULL
);
1647 /* Return true if SET of RCLASS contains no hard regs which can be
1650 prohibited_class_reg_set_mode_p (enum reg_class rclass
,
1652 enum machine_mode mode
)
1656 lra_assert (hard_reg_set_subset_p (reg_class_contents
[rclass
], set
));
1657 COPY_HARD_REG_SET (temp
, set
);
1658 AND_COMPL_HARD_REG_SET (temp
, lra_no_alloc_regs
);
1659 return (hard_reg_set_subset_p
1660 (temp
, ira_prohibited_class_mode_regs
[rclass
][mode
]));
1663 /* Major function to choose the current insn alternative and what
1664 operands should be reloaded and how. If ONLY_ALTERNATIVE is not
1665 negative we should consider only this alternative. Return false if
1666 we can not choose the alternative or find how to reload the
1669 process_alt_operands (int only_alternative
)
1672 int nop
, overall
, nalt
;
1673 int n_alternatives
= curr_static_id
->n_alternatives
;
1674 int n_operands
= curr_static_id
->n_operands
;
1675 /* LOSERS counts the operands that don't fit this alternative and
1676 would require loading. */
1678 /* REJECT is a count of how undesirable this alternative says it is
1679 if any reloading is required. If the alternative matches exactly
1680 then REJECT is ignored, but otherwise it gets this much counted
1681 against it in addition to the reloading needed. */
1684 /* The number of elements in the following array. */
1685 int early_clobbered_regs_num
;
1686 /* Numbers of operands which are early clobber registers. */
1687 int early_clobbered_nops
[MAX_RECOG_OPERANDS
];
1688 enum reg_class curr_alt
[MAX_RECOG_OPERANDS
];
1689 HARD_REG_SET curr_alt_set
[MAX_RECOG_OPERANDS
];
1690 bool curr_alt_match_win
[MAX_RECOG_OPERANDS
];
1691 bool curr_alt_win
[MAX_RECOG_OPERANDS
];
1692 bool curr_alt_offmemok
[MAX_RECOG_OPERANDS
];
1693 int curr_alt_matches
[MAX_RECOG_OPERANDS
];
1694 /* The number of elements in the following array. */
1695 int curr_alt_dont_inherit_ops_num
;
1696 /* Numbers of operands whose reload pseudos should not be inherited. */
1697 int curr_alt_dont_inherit_ops
[MAX_RECOG_OPERANDS
];
1699 /* The register when the operand is a subreg of register, otherwise the
1701 rtx no_subreg_reg_operand
[MAX_RECOG_OPERANDS
];
1702 /* The register if the operand is a register or subreg of register,
1704 rtx operand_reg
[MAX_RECOG_OPERANDS
];
1705 int hard_regno
[MAX_RECOG_OPERANDS
];
1706 machine_mode biggest_mode
[MAX_RECOG_OPERANDS
];
1707 int reload_nregs
, reload_sum
;
1711 /* Calculate some data common for all alternatives to speed up the
1713 for (nop
= 0; nop
< n_operands
; nop
++)
1717 op
= no_subreg_reg_operand
[nop
] = *curr_id
->operand_loc
[nop
];
1718 /* The real hard regno of the operand after the allocation. */
1719 hard_regno
[nop
] = get_hard_regno (op
);
1721 operand_reg
[nop
] = reg
= op
;
1722 biggest_mode
[nop
] = GET_MODE (op
);
1723 if (GET_CODE (op
) == SUBREG
)
1725 operand_reg
[nop
] = reg
= SUBREG_REG (op
);
1726 if (GET_MODE_SIZE (biggest_mode
[nop
])
1727 < GET_MODE_SIZE (GET_MODE (reg
)))
1728 biggest_mode
[nop
] = GET_MODE (reg
);
1731 operand_reg
[nop
] = NULL_RTX
;
1732 else if (REGNO (reg
) >= FIRST_PSEUDO_REGISTER
1733 || ((int) REGNO (reg
)
1734 == lra_get_elimination_hard_regno (REGNO (reg
))))
1735 no_subreg_reg_operand
[nop
] = reg
;
1737 operand_reg
[nop
] = no_subreg_reg_operand
[nop
]
1738 /* Just use natural mode for elimination result. It should
1739 be enough for extra constraints hooks. */
1740 = regno_reg_rtx
[hard_regno
[nop
]];
1743 /* The constraints are made of several alternatives. Each operand's
1744 constraint looks like foo,bar,... with commas separating the
1745 alternatives. The first alternatives for all operands go
1746 together, the second alternatives go together, etc.
1748 First loop over alternatives. */
1749 alternative_mask preferred
= curr_id
->preferred_alternatives
;
1750 if (only_alternative
>= 0)
1751 preferred
&= ALTERNATIVE_BIT (only_alternative
);
1753 for (nalt
= 0; nalt
< n_alternatives
; nalt
++)
1755 /* Loop over operands for one constraint alternative. */
1756 if (!TEST_BIT (preferred
, nalt
))
1759 overall
= losers
= reject
= reload_nregs
= reload_sum
= 0;
1760 for (nop
= 0; nop
< n_operands
; nop
++)
1762 int inc
= (curr_static_id
1763 ->operand_alternative
[nalt
* n_operands
+ nop
].reject
);
1764 if (lra_dump_file
!= NULL
&& inc
!= 0)
1765 fprintf (lra_dump_file
,
1766 " Staticly defined alt reject+=%d\n", inc
);
1769 early_clobbered_regs_num
= 0;
1771 for (nop
= 0; nop
< n_operands
; nop
++)
1775 int len
, c
, m
, i
, opalt_num
, this_alternative_matches
;
1776 bool win
, did_match
, offmemok
, early_clobber_p
;
1777 /* false => this operand can be reloaded somehow for this
1780 /* true => this operand can be reloaded if the alternative
1783 /* True if a constant forced into memory would be OK for
1786 enum reg_class this_alternative
, this_costly_alternative
;
1787 HARD_REG_SET this_alternative_set
, this_costly_alternative_set
;
1788 bool this_alternative_match_win
, this_alternative_win
;
1789 bool this_alternative_offmemok
;
1792 enum constraint_num cn
;
1794 opalt_num
= nalt
* n_operands
+ nop
;
1795 if (curr_static_id
->operand_alternative
[opalt_num
].anything_ok
)
1797 /* Fast track for no constraints at all. */
1798 curr_alt
[nop
] = NO_REGS
;
1799 CLEAR_HARD_REG_SET (curr_alt_set
[nop
]);
1800 curr_alt_win
[nop
] = true;
1801 curr_alt_match_win
[nop
] = false;
1802 curr_alt_offmemok
[nop
] = false;
1803 curr_alt_matches
[nop
] = -1;
1807 op
= no_subreg_reg_operand
[nop
];
1808 mode
= curr_operand_mode
[nop
];
1810 win
= did_match
= winreg
= offmemok
= constmemok
= false;
1813 early_clobber_p
= false;
1814 p
= curr_static_id
->operand_alternative
[opalt_num
].constraint
;
1816 this_costly_alternative
= this_alternative
= NO_REGS
;
1817 /* We update set of possible hard regs besides its class
1818 because reg class might be inaccurate. For example,
1819 union of LO_REGS (l), HI_REGS(h), and STACK_REG(k) in ARM
1820 is translated in HI_REGS because classes are merged by
1821 pairs and there is no accurate intermediate class. */
1822 CLEAR_HARD_REG_SET (this_alternative_set
);
1823 CLEAR_HARD_REG_SET (this_costly_alternative_set
);
1824 this_alternative_win
= false;
1825 this_alternative_match_win
= false;
1826 this_alternative_offmemok
= false;
1827 this_alternative_matches
= -1;
1829 /* An empty constraint should be excluded by the fast
1831 lra_assert (*p
!= 0 && *p
!= ',');
1834 /* Scan this alternative's specs for this operand; set WIN
1835 if the operand fits any letter in this alternative.
1836 Otherwise, clear BADOP if this operand could fit some
1837 letter after reloads, or set WINREG if this operand could
1838 fit after reloads provided the constraint allows some
1843 switch ((c
= *p
, len
= CONSTRAINT_LEN (c
, p
)), c
)
1853 early_clobber_p
= true;
1857 op_reject
+= LRA_MAX_REJECT
;
1860 op_reject
+= LRA_LOSER_COST_FACTOR
;
1864 /* Ignore rest of this alternative. */
1868 case '0': case '1': case '2': case '3': case '4':
1869 case '5': case '6': case '7': case '8': case '9':
1874 m
= strtoul (p
, &end
, 10);
1877 lra_assert (nop
> m
);
1879 this_alternative_matches
= m
;
1880 m_hregno
= get_hard_regno (*curr_id
->operand_loc
[m
]);
1881 /* We are supposed to match a previous operand.
1882 If we do, we win if that one did. If we do
1883 not, count both of the operands as losers.
1884 (This is too conservative, since most of the
1885 time only a single reload insn will be needed
1886 to make the two operands win. As a result,
1887 this alternative may be rejected when it is
1888 actually desirable.) */
1890 if (operands_match_p (*curr_id
->operand_loc
[nop
],
1891 *curr_id
->operand_loc
[m
], m_hregno
))
1893 /* We should reject matching of an early
1894 clobber operand if the matching operand is
1895 not dying in the insn. */
1896 if (! curr_static_id
->operand
[m
].early_clobber
1897 || operand_reg
[nop
] == NULL_RTX
1898 || (find_regno_note (curr_insn
, REG_DEAD
,
1900 || REGNO (op
) == REGNO (operand_reg
[m
])))
1905 /* If we are matching a non-offsettable
1906 address where an offsettable address was
1907 expected, then we must reject this
1908 combination, because we can't reload
1910 if (curr_alt_offmemok
[m
]
1911 && MEM_P (*curr_id
->operand_loc
[m
])
1912 && curr_alt
[m
] == NO_REGS
&& ! curr_alt_win
[m
])
1917 /* Operands don't match. Both operands must
1918 allow a reload register, otherwise we
1919 cannot make them match. */
1920 if (curr_alt
[m
] == NO_REGS
)
1922 /* Retroactively mark the operand we had to
1923 match as a loser, if it wasn't already and
1924 it wasn't matched to a register constraint
1925 (e.g it might be matched by memory). */
1927 && (operand_reg
[m
] == NULL_RTX
1928 || hard_regno
[m
] < 0))
1932 += (ira_reg_class_max_nregs
[curr_alt
[m
]]
1933 [GET_MODE (*curr_id
->operand_loc
[m
])]);
1936 /* Prefer matching earlyclobber alternative as
1937 it results in less hard regs required for
1938 the insn than a non-matching earlyclobber
1940 if (curr_static_id
->operand
[m
].early_clobber
)
1942 if (lra_dump_file
!= NULL
)
1945 " %d Matching earlyclobber alt:"
1950 /* Otherwise we prefer no matching
1951 alternatives because it gives more freedom
1953 else if (operand_reg
[nop
] == NULL_RTX
1954 || (find_regno_note (curr_insn
, REG_DEAD
,
1955 REGNO (operand_reg
[nop
]))
1958 if (lra_dump_file
!= NULL
)
1961 " %d Matching alt: reject+=2\n",
1966 /* If we have to reload this operand and some
1967 previous operand also had to match the same
1968 thing as this operand, we don't know how to do
1970 if (!match_p
|| !curr_alt_win
[m
])
1972 for (i
= 0; i
< nop
; i
++)
1973 if (curr_alt_matches
[i
] == m
)
1981 /* This can be fixed with reloads if the operand
1982 we are supposed to match can be fixed with
1985 this_alternative
= curr_alt
[m
];
1986 COPY_HARD_REG_SET (this_alternative_set
, curr_alt_set
[m
]);
1987 winreg
= this_alternative
!= NO_REGS
;
1993 || general_constant_p (op
)
1994 || spilled_pseudo_p (op
))
2000 cn
= lookup_constraint (p
);
2001 switch (get_constraint_type (cn
))
2004 cl
= reg_class_for_constraint (cn
);
2010 if (CONST_INT_P (op
)
2011 && insn_const_int_ok_for_constraint (INTVAL (op
), cn
))
2017 && satisfies_memory_constraint_p (op
, cn
))
2019 else if (spilled_pseudo_p (op
))
2022 /* If we didn't already win, we can reload constants
2023 via force_const_mem or put the pseudo value into
2024 memory, or make other memory by reloading the
2025 address like for 'o'. */
2026 if (CONST_POOL_OK_P (mode
, op
)
2027 || MEM_P (op
) || REG_P (op
))
2034 /* If we didn't already win, we can reload the address
2035 into a base register. */
2036 if (satisfies_address_constraint_p (op
, cn
))
2038 cl
= base_reg_class (VOIDmode
, ADDR_SPACE_GENERIC
,
2044 if (constraint_satisfied_p (op
, cn
))
2051 this_alternative
= reg_class_subunion
[this_alternative
][cl
];
2052 IOR_HARD_REG_SET (this_alternative_set
,
2053 reg_class_contents
[cl
]);
2056 this_costly_alternative
2057 = reg_class_subunion
[this_costly_alternative
][cl
];
2058 IOR_HARD_REG_SET (this_costly_alternative_set
,
2059 reg_class_contents
[cl
]);
2061 if (mode
== BLKmode
)
2066 if (hard_regno
[nop
] >= 0
2067 && in_hard_reg_set_p (this_alternative_set
,
2068 mode
, hard_regno
[nop
]))
2070 else if (hard_regno
[nop
] < 0
2071 && in_class_p (op
, this_alternative
, NULL
))
2076 if (c
!= ' ' && c
!= '\t')
2077 costly_p
= c
== '*';
2079 while ((p
+= len
), c
);
2081 scratch_p
= (operand_reg
[nop
] != NULL_RTX
2082 && lra_former_scratch_p (REGNO (operand_reg
[nop
])));
2083 /* Record which operands fit this alternative. */
2086 this_alternative_win
= true;
2087 if (operand_reg
[nop
] != NULL_RTX
)
2089 if (hard_regno
[nop
] >= 0)
2091 if (in_hard_reg_set_p (this_costly_alternative_set
,
2092 mode
, hard_regno
[nop
]))
2094 if (lra_dump_file
!= NULL
)
2095 fprintf (lra_dump_file
,
2096 " %d Costly set: reject++\n",
2103 /* Prefer won reg to spilled pseudo under other
2104 equal conditions for possibe inheritance. */
2107 if (lra_dump_file
!= NULL
)
2110 " %d Non pseudo reload: reject++\n",
2114 if (in_class_p (operand_reg
[nop
],
2115 this_costly_alternative
, NULL
))
2117 if (lra_dump_file
!= NULL
)
2120 " %d Non pseudo costly reload:"
2126 /* We simulate the behaviour of old reload here.
2127 Although scratches need hard registers and it
2128 might result in spilling other pseudos, no reload
2129 insns are generated for the scratches. So it
2130 might cost something but probably less than old
2131 reload pass believes. */
2134 if (lra_dump_file
!= NULL
)
2135 fprintf (lra_dump_file
,
2136 " %d Scratch win: reject+=2\n",
2143 this_alternative_match_win
= true;
2146 int const_to_mem
= 0;
2149 reject
+= op_reject
;
2150 /* Never do output reload of stack pointer. It makes
2151 impossible to do elimination when SP is changed in
2153 if (op
== stack_pointer_rtx
&& ! frame_pointer_needed
2154 && curr_static_id
->operand
[nop
].type
!= OP_IN
)
2157 /* If this alternative asks for a specific reg class, see if there
2158 is at least one allocatable register in that class. */
2160 = (this_alternative
== NO_REGS
2161 || (hard_reg_set_subset_p
2162 (reg_class_contents
[this_alternative
],
2163 lra_no_alloc_regs
)));
2165 /* For asms, verify that the class for this alternative is possible
2166 for the mode that is specified. */
2167 if (!no_regs_p
&& INSN_CODE (curr_insn
) < 0)
2170 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
2171 if (HARD_REGNO_MODE_OK (i
, mode
)
2172 && in_hard_reg_set_p (reg_class_contents
[this_alternative
],
2175 if (i
== FIRST_PSEUDO_REGISTER
)
2179 /* If this operand accepts a register, and if the
2180 register class has at least one allocatable register,
2181 then this operand can be reloaded. */
2182 if (winreg
&& !no_regs_p
)
2187 if (lra_dump_file
!= NULL
)
2188 fprintf (lra_dump_file
,
2189 " alt=%d: Bad operand -- refuse\n",
2194 /* If not assigned pseudo has a class which a subset of
2195 required reg class, it is a less costly alternative
2196 as the pseudo still can get a hard reg of necessary
2198 if (! no_regs_p
&& REG_P (op
) && hard_regno
[nop
] < 0
2199 && (cl
= get_reg_class (REGNO (op
))) != NO_REGS
2200 && ira_class_subset_p
[this_alternative
][cl
])
2202 if (lra_dump_file
!= NULL
)
2205 " %d Super set class reg: reject-=3\n", nop
);
2209 this_alternative_offmemok
= offmemok
;
2210 if (this_costly_alternative
!= NO_REGS
)
2212 if (lra_dump_file
!= NULL
)
2213 fprintf (lra_dump_file
,
2214 " %d Costly loser: reject++\n", nop
);
2217 /* If the operand is dying, has a matching constraint,
2218 and satisfies constraints of the matched operand
2219 which failed to satisfy the own constraints, most probably
2220 the reload for this operand will be gone. */
2221 if (this_alternative_matches
>= 0
2222 && !curr_alt_win
[this_alternative_matches
]
2224 && find_regno_note (curr_insn
, REG_DEAD
, REGNO (op
))
2225 && (hard_regno
[nop
] >= 0
2226 ? in_hard_reg_set_p (this_alternative_set
,
2227 mode
, hard_regno
[nop
])
2228 : in_class_p (op
, this_alternative
, NULL
)))
2230 if (lra_dump_file
!= NULL
)
2233 " %d Dying matched operand reload: reject++\n",
2239 /* Strict_low_part requires to reload the register
2240 not the sub-register. In this case we should
2241 check that a final reload hard reg can hold the
2243 if (curr_static_id
->operand
[nop
].strict_low
2245 && hard_regno
[nop
] < 0
2246 && GET_CODE (*curr_id
->operand_loc
[nop
]) == SUBREG
2247 && ira_class_hard_regs_num
[this_alternative
] > 0
2248 && ! HARD_REGNO_MODE_OK (ira_class_hard_regs
2249 [this_alternative
][0],
2251 (*curr_id
->operand_loc
[nop
])))
2253 if (lra_dump_file
!= NULL
)
2256 " alt=%d: Strict low subreg reload -- refuse\n",
2262 if (operand_reg
[nop
] != NULL_RTX
2263 /* Output operands and matched input operands are
2264 not inherited. The following conditions do not
2265 exactly describe the previous statement but they
2266 are pretty close. */
2267 && curr_static_id
->operand
[nop
].type
!= OP_OUT
2268 && (this_alternative_matches
< 0
2269 || curr_static_id
->operand
[nop
].type
!= OP_IN
))
2271 int last_reload
= (lra_reg_info
[ORIGINAL_REGNO
2275 /* The value of reload_sum has sense only if we
2276 process insns in their order. It happens only on
2277 the first constraints sub-pass when we do most of
2279 if (lra_constraint_iter
== 1 && last_reload
> bb_reload_num
)
2280 reload_sum
+= last_reload
- bb_reload_num
;
2282 /* If this is a constant that is reloaded into the
2283 desired class by copying it to memory first, count
2284 that as another reload. This is consistent with
2285 other code and is required to avoid choosing another
2286 alternative when the constant is moved into memory.
2287 Note that the test here is precisely the same as in
2288 the code below that calls force_const_mem. */
2289 if (CONST_POOL_OK_P (mode
, op
)
2290 && ((targetm
.preferred_reload_class
2291 (op
, this_alternative
) == NO_REGS
)
2292 || no_input_reloads_p
))
2299 /* Alternative loses if it requires a type of reload not
2300 permitted for this insn. We can always reload
2301 objects with a REG_UNUSED note. */
2302 if ((curr_static_id
->operand
[nop
].type
!= OP_IN
2303 && no_output_reloads_p
2304 && ! find_reg_note (curr_insn
, REG_UNUSED
, op
))
2305 || (curr_static_id
->operand
[nop
].type
!= OP_OUT
2306 && no_input_reloads_p
&& ! const_to_mem
)
2307 || (this_alternative_matches
>= 0
2308 && (no_input_reloads_p
2309 || (no_output_reloads_p
2310 && (curr_static_id
->operand
2311 [this_alternative_matches
].type
!= OP_IN
)
2312 && ! find_reg_note (curr_insn
, REG_UNUSED
,
2313 no_subreg_reg_operand
2314 [this_alternative_matches
])))))
2316 if (lra_dump_file
!= NULL
)
2319 " alt=%d: No input/otput reload -- refuse\n",
2324 /* Alternative loses if it required class pseudo can not
2325 hold value of required mode. Such insns can be
2326 described by insn definitions with mode iterators. */
2327 if (GET_MODE (*curr_id
->operand_loc
[nop
]) != VOIDmode
2328 && ! hard_reg_set_empty_p (this_alternative_set
)
2329 /* It is common practice for constraints to use a
2330 class which does not have actually enough regs to
2331 hold the value (e.g. x86 AREG for mode requiring
2332 more one general reg). Therefore we have 2
2333 conditions to check that the reload pseudo can
2334 not hold the mode value. */
2335 && ! HARD_REGNO_MODE_OK (ira_class_hard_regs
2336 [this_alternative
][0],
2337 GET_MODE (*curr_id
->operand_loc
[nop
]))
2338 /* The above condition is not enough as the first
2339 reg in ira_class_hard_regs can be not aligned for
2340 multi-words mode values. */
2341 && (prohibited_class_reg_set_mode_p
2342 (this_alternative
, this_alternative_set
,
2343 GET_MODE (*curr_id
->operand_loc
[nop
]))))
2345 if (lra_dump_file
!= NULL
)
2346 fprintf (lra_dump_file
,
2347 " alt=%d: reload pseudo for op %d "
2348 " can not hold the mode value -- refuse\n",
2353 /* Check strong discouragement of reload of non-constant
2354 into class THIS_ALTERNATIVE. */
2355 if (! CONSTANT_P (op
) && ! no_regs_p
2356 && (targetm
.preferred_reload_class
2357 (op
, this_alternative
) == NO_REGS
2358 || (curr_static_id
->operand
[nop
].type
== OP_OUT
2359 && (targetm
.preferred_output_reload_class
2360 (op
, this_alternative
) == NO_REGS
))))
2362 if (lra_dump_file
!= NULL
)
2363 fprintf (lra_dump_file
,
2364 " %d Non-prefered reload: reject+=%d\n",
2365 nop
, LRA_MAX_REJECT
);
2366 reject
+= LRA_MAX_REJECT
;
2369 if (! (MEM_P (op
) && offmemok
)
2370 && ! (const_to_mem
&& constmemok
))
2372 /* We prefer to reload pseudos over reloading other
2373 things, since such reloads may be able to be
2374 eliminated later. So bump REJECT in other cases.
2375 Don't do this in the case where we are forcing a
2376 constant into memory and it will then win since
2377 we don't want to have a different alternative
2379 if (! (REG_P (op
) && REGNO (op
) >= FIRST_PSEUDO_REGISTER
))
2381 if (lra_dump_file
!= NULL
)
2384 " %d Non-pseudo reload: reject+=2\n",
2391 += ira_reg_class_max_nregs
[this_alternative
][mode
];
2393 if (SMALL_REGISTER_CLASS_P (this_alternative
))
2395 if (lra_dump_file
!= NULL
)
2398 " %d Small class reload: reject+=%d\n",
2399 nop
, LRA_LOSER_COST_FACTOR
/ 2);
2400 reject
+= LRA_LOSER_COST_FACTOR
/ 2;
2404 /* We are trying to spill pseudo into memory. It is
2405 usually more costly than moving to a hard register
2406 although it might takes the same number of
2408 if (no_regs_p
&& REG_P (op
) && hard_regno
[nop
] >= 0)
2410 if (lra_dump_file
!= NULL
)
2413 " %d Spill pseudo into memory: reject+=3\n",
2416 if (VECTOR_MODE_P (mode
))
2418 /* Spilling vectors into memory is usually more
2419 costly as they contain big values. */
2420 if (lra_dump_file
!= NULL
)
2423 " %d Spill vector pseudo: reject+=2\n",
2429 #ifdef SECONDARY_MEMORY_NEEDED
2430 /* If reload requires moving value through secondary
2431 memory, it will need one more insn at least. */
2432 if (this_alternative
!= NO_REGS
2433 && REG_P (op
) && (cl
= get_reg_class (REGNO (op
))) != NO_REGS
2434 && ((curr_static_id
->operand
[nop
].type
!= OP_OUT
2435 && SECONDARY_MEMORY_NEEDED (cl
, this_alternative
,
2437 || (curr_static_id
->operand
[nop
].type
!= OP_IN
2438 && SECONDARY_MEMORY_NEEDED (this_alternative
, cl
,
2442 /* Input reloads can be inherited more often than output
2443 reloads can be removed, so penalize output
2445 if (!REG_P (op
) || curr_static_id
->operand
[nop
].type
!= OP_IN
)
2447 if (lra_dump_file
!= NULL
)
2450 " %d Non input pseudo reload: reject++\n",
2456 if (early_clobber_p
&& ! scratch_p
)
2458 if (lra_dump_file
!= NULL
)
2459 fprintf (lra_dump_file
,
2460 " %d Early clobber: reject++\n", nop
);
2463 /* ??? We check early clobbers after processing all operands
2464 (see loop below) and there we update the costs more.
2465 Should we update the cost (may be approximately) here
2466 because of early clobber register reloads or it is a rare
2467 or non-important thing to be worth to do it. */
2468 overall
= losers
* LRA_LOSER_COST_FACTOR
+ reject
;
2469 if ((best_losers
== 0 || losers
!= 0) && best_overall
< overall
)
2471 if (lra_dump_file
!= NULL
)
2472 fprintf (lra_dump_file
,
2473 " alt=%d,overall=%d,losers=%d -- refuse\n",
2474 nalt
, overall
, losers
);
2478 curr_alt
[nop
] = this_alternative
;
2479 COPY_HARD_REG_SET (curr_alt_set
[nop
], this_alternative_set
);
2480 curr_alt_win
[nop
] = this_alternative_win
;
2481 curr_alt_match_win
[nop
] = this_alternative_match_win
;
2482 curr_alt_offmemok
[nop
] = this_alternative_offmemok
;
2483 curr_alt_matches
[nop
] = this_alternative_matches
;
2485 if (this_alternative_matches
>= 0
2486 && !did_match
&& !this_alternative_win
)
2487 curr_alt_win
[this_alternative_matches
] = false;
2489 if (early_clobber_p
&& operand_reg
[nop
] != NULL_RTX
)
2490 early_clobbered_nops
[early_clobbered_regs_num
++] = nop
;
2492 if (curr_insn_set
!= NULL_RTX
&& n_operands
== 2
2493 /* Prevent processing non-move insns. */
2494 && (GET_CODE (SET_SRC (curr_insn_set
)) == SUBREG
2495 || SET_SRC (curr_insn_set
) == no_subreg_reg_operand
[1])
2496 && ((! curr_alt_win
[0] && ! curr_alt_win
[1]
2497 && REG_P (no_subreg_reg_operand
[0])
2498 && REG_P (no_subreg_reg_operand
[1])
2499 && (reg_in_class_p (no_subreg_reg_operand
[0], curr_alt
[1])
2500 || reg_in_class_p (no_subreg_reg_operand
[1], curr_alt
[0])))
2501 || (! curr_alt_win
[0] && curr_alt_win
[1]
2502 && REG_P (no_subreg_reg_operand
[1])
2503 && reg_in_class_p (no_subreg_reg_operand
[1], curr_alt
[0]))
2504 || (curr_alt_win
[0] && ! curr_alt_win
[1]
2505 && REG_P (no_subreg_reg_operand
[0])
2506 && reg_in_class_p (no_subreg_reg_operand
[0], curr_alt
[1])
2507 && (! CONST_POOL_OK_P (curr_operand_mode
[1],
2508 no_subreg_reg_operand
[1])
2509 || (targetm
.preferred_reload_class
2510 (no_subreg_reg_operand
[1],
2511 (enum reg_class
) curr_alt
[1]) != NO_REGS
))
2512 /* If it is a result of recent elimination in move
2513 insn we can transform it into an add still by
2514 using this alternative. */
2515 && GET_CODE (no_subreg_reg_operand
[1]) != PLUS
)))
2517 /* We have a move insn and a new reload insn will be similar
2518 to the current insn. We should avoid such situation as it
2519 results in LRA cycling. */
2520 overall
+= LRA_MAX_REJECT
;
2523 curr_alt_dont_inherit_ops_num
= 0;
2524 for (nop
= 0; nop
< early_clobbered_regs_num
; nop
++)
2526 int i
, j
, clobbered_hard_regno
, first_conflict_j
, last_conflict_j
;
2527 HARD_REG_SET temp_set
;
2529 i
= early_clobbered_nops
[nop
];
2530 if ((! curr_alt_win
[i
] && ! curr_alt_match_win
[i
])
2531 || hard_regno
[i
] < 0)
2533 lra_assert (operand_reg
[i
] != NULL_RTX
);
2534 clobbered_hard_regno
= hard_regno
[i
];
2535 CLEAR_HARD_REG_SET (temp_set
);
2536 add_to_hard_reg_set (&temp_set
, biggest_mode
[i
], clobbered_hard_regno
);
2537 first_conflict_j
= last_conflict_j
= -1;
2538 for (j
= 0; j
< n_operands
; j
++)
2540 /* We don't want process insides of match_operator and
2541 match_parallel because otherwise we would process
2542 their operands once again generating a wrong
2544 || curr_static_id
->operand
[j
].is_operator
)
2546 else if ((curr_alt_matches
[j
] == i
&& curr_alt_match_win
[j
])
2547 || (curr_alt_matches
[i
] == j
&& curr_alt_match_win
[i
]))
2549 /* If we don't reload j-th operand, check conflicts. */
2550 else if ((curr_alt_win
[j
] || curr_alt_match_win
[j
])
2551 && uses_hard_regs_p (*curr_id
->operand_loc
[j
], temp_set
))
2553 if (first_conflict_j
< 0)
2554 first_conflict_j
= j
;
2555 last_conflict_j
= j
;
2557 if (last_conflict_j
< 0)
2559 /* If earlyclobber operand conflicts with another
2560 non-matching operand which is actually the same register
2561 as the earlyclobber operand, it is better to reload the
2562 another operand as an operand matching the earlyclobber
2563 operand can be also the same. */
2564 if (first_conflict_j
== last_conflict_j
2565 && operand_reg
[last_conflict_j
]
2566 != NULL_RTX
&& ! curr_alt_match_win
[last_conflict_j
]
2567 && REGNO (operand_reg
[i
]) == REGNO (operand_reg
[last_conflict_j
]))
2569 curr_alt_win
[last_conflict_j
] = false;
2570 curr_alt_dont_inherit_ops
[curr_alt_dont_inherit_ops_num
++]
2573 /* Early clobber was already reflected in REJECT. */
2574 lra_assert (reject
> 0);
2575 if (lra_dump_file
!= NULL
)
2578 " %d Conflict early clobber reload: reject--\n",
2581 overall
+= LRA_LOSER_COST_FACTOR
- 1;
2585 /* We need to reload early clobbered register and the
2586 matched registers. */
2587 for (j
= 0; j
< n_operands
; j
++)
2588 if (curr_alt_matches
[j
] == i
)
2590 curr_alt_match_win
[j
] = false;
2592 overall
+= LRA_LOSER_COST_FACTOR
;
2594 if (! curr_alt_match_win
[i
])
2595 curr_alt_dont_inherit_ops
[curr_alt_dont_inherit_ops_num
++] = i
;
2598 /* Remember pseudos used for match reloads are never
2600 lra_assert (curr_alt_matches
[i
] >= 0);
2601 curr_alt_win
[curr_alt_matches
[i
]] = false;
2603 curr_alt_win
[i
] = curr_alt_match_win
[i
] = false;
2605 /* Early clobber was already reflected in REJECT. */
2606 lra_assert (reject
> 0);
2607 if (lra_dump_file
!= NULL
)
2610 " %d Matched conflict early clobber reloads:"
2614 overall
+= LRA_LOSER_COST_FACTOR
- 1;
2617 if (lra_dump_file
!= NULL
)
2618 fprintf (lra_dump_file
, " alt=%d,overall=%d,losers=%d,rld_nregs=%d\n",
2619 nalt
, overall
, losers
, reload_nregs
);
2621 /* If this alternative can be made to work by reloading, and it
2622 needs less reloading than the others checked so far, record
2623 it as the chosen goal for reloading. */
2624 if ((best_losers
!= 0 && losers
== 0)
2625 || (((best_losers
== 0 && losers
== 0)
2626 || (best_losers
!= 0 && losers
!= 0))
2627 && (best_overall
> overall
2628 || (best_overall
== overall
2629 /* If the cost of the reloads is the same,
2630 prefer alternative which requires minimal
2631 number of reload regs. */
2632 && (reload_nregs
< best_reload_nregs
2633 || (reload_nregs
== best_reload_nregs
2634 && (best_reload_sum
< reload_sum
2635 || (best_reload_sum
== reload_sum
2636 && nalt
< goal_alt_number
))))))))
2638 for (nop
= 0; nop
< n_operands
; nop
++)
2640 goal_alt_win
[nop
] = curr_alt_win
[nop
];
2641 goal_alt_match_win
[nop
] = curr_alt_match_win
[nop
];
2642 goal_alt_matches
[nop
] = curr_alt_matches
[nop
];
2643 goal_alt
[nop
] = curr_alt
[nop
];
2644 goal_alt_offmemok
[nop
] = curr_alt_offmemok
[nop
];
2646 goal_alt_dont_inherit_ops_num
= curr_alt_dont_inherit_ops_num
;
2647 for (nop
= 0; nop
< curr_alt_dont_inherit_ops_num
; nop
++)
2648 goal_alt_dont_inherit_ops
[nop
] = curr_alt_dont_inherit_ops
[nop
];
2649 goal_alt_swapped
= curr_swapped
;
2650 best_overall
= overall
;
2651 best_losers
= losers
;
2652 best_reload_nregs
= reload_nregs
;
2653 best_reload_sum
= reload_sum
;
2654 goal_alt_number
= nalt
;
2657 /* Everything is satisfied. Do not process alternatives
2666 /* Make reload base reg from address AD. */
2668 base_to_reg (struct address_info
*ad
)
2672 rtx new_inner
= NULL_RTX
;
2673 rtx new_reg
= NULL_RTX
;
2675 rtx_insn
*last_insn
= get_last_insn();
2677 lra_assert (ad
->base
== ad
->base_term
&& ad
->disp
== ad
->disp_term
);
2678 cl
= base_reg_class (ad
->mode
, ad
->as
, ad
->base_outer_code
,
2679 get_index_code (ad
));
2680 new_reg
= lra_create_new_reg (GET_MODE (*ad
->base_term
), NULL_RTX
,
2682 new_inner
= simplify_gen_binary (PLUS
, GET_MODE (new_reg
), new_reg
,
2683 ad
->disp_term
== NULL
2684 ? gen_int_mode (0, ad
->mode
)
2686 if (!valid_address_p (ad
->mode
, new_inner
, ad
->as
))
2688 insn
= emit_insn (gen_rtx_SET (new_reg
, *ad
->base_term
));
2689 code
= recog_memoized (insn
);
2692 delete_insns_since (last_insn
);
2699 /* Make reload base reg + disp from address AD. Return the new pseudo. */
2701 base_plus_disp_to_reg (struct address_info
*ad
)
2706 lra_assert (ad
->base
== ad
->base_term
&& ad
->disp
== ad
->disp_term
);
2707 cl
= base_reg_class (ad
->mode
, ad
->as
, ad
->base_outer_code
,
2708 get_index_code (ad
));
2709 new_reg
= lra_create_new_reg (GET_MODE (*ad
->base_term
), NULL_RTX
,
2711 lra_emit_add (new_reg
, *ad
->base_term
, *ad
->disp_term
);
2715 /* Make reload of index part of address AD. Return the new
2718 index_part_to_reg (struct address_info
*ad
)
2722 new_reg
= lra_create_new_reg (GET_MODE (*ad
->index
), NULL_RTX
,
2723 INDEX_REG_CLASS
, "index term");
2724 expand_mult (GET_MODE (*ad
->index
), *ad
->index_term
,
2725 GEN_INT (get_index_scale (ad
)), new_reg
, 1);
2729 /* Return true if we can add a displacement to address AD, even if that
2730 makes the address invalid. The fix-up code requires any new address
2731 to be the sum of the BASE_TERM, INDEX and DISP_TERM fields. */
2733 can_add_disp_p (struct address_info
*ad
)
2735 return (!ad
->autoinc_p
2736 && ad
->segment
== NULL
2737 && ad
->base
== ad
->base_term
2738 && ad
->disp
== ad
->disp_term
);
2741 /* Make equiv substitution in address AD. Return true if a substitution
2744 equiv_address_substitution (struct address_info
*ad
)
2746 rtx base_reg
, new_base_reg
, index_reg
, new_index_reg
, *base_term
, *index_term
;
2747 HOST_WIDE_INT disp
, scale
;
2750 base_term
= strip_subreg (ad
->base_term
);
2751 if (base_term
== NULL
)
2752 base_reg
= new_base_reg
= NULL_RTX
;
2755 base_reg
= *base_term
;
2756 new_base_reg
= get_equiv_with_elimination (base_reg
, curr_insn
);
2758 index_term
= strip_subreg (ad
->index_term
);
2759 if (index_term
== NULL
)
2760 index_reg
= new_index_reg
= NULL_RTX
;
2763 index_reg
= *index_term
;
2764 new_index_reg
= get_equiv_with_elimination (index_reg
, curr_insn
);
2766 if (base_reg
== new_base_reg
&& index_reg
== new_index_reg
)
2770 if (lra_dump_file
!= NULL
)
2772 fprintf (lra_dump_file
, "Changing address in insn %d ",
2773 INSN_UID (curr_insn
));
2774 dump_value_slim (lra_dump_file
, *ad
->outer
, 1);
2776 if (base_reg
!= new_base_reg
)
2778 if (REG_P (new_base_reg
))
2780 *base_term
= new_base_reg
;
2783 else if (GET_CODE (new_base_reg
) == PLUS
2784 && REG_P (XEXP (new_base_reg
, 0))
2785 && CONST_INT_P (XEXP (new_base_reg
, 1))
2786 && can_add_disp_p (ad
))
2788 disp
+= INTVAL (XEXP (new_base_reg
, 1));
2789 *base_term
= XEXP (new_base_reg
, 0);
2792 if (ad
->base_term2
!= NULL
)
2793 *ad
->base_term2
= *ad
->base_term
;
2795 if (index_reg
!= new_index_reg
)
2797 if (REG_P (new_index_reg
))
2799 *index_term
= new_index_reg
;
2802 else if (GET_CODE (new_index_reg
) == PLUS
2803 && REG_P (XEXP (new_index_reg
, 0))
2804 && CONST_INT_P (XEXP (new_index_reg
, 1))
2805 && can_add_disp_p (ad
)
2806 && (scale
= get_index_scale (ad
)))
2808 disp
+= INTVAL (XEXP (new_index_reg
, 1)) * scale
;
2809 *index_term
= XEXP (new_index_reg
, 0);
2815 if (ad
->disp
!= NULL
)
2816 *ad
->disp
= plus_constant (GET_MODE (*ad
->inner
), *ad
->disp
, disp
);
2819 *ad
->inner
= plus_constant (GET_MODE (*ad
->inner
), *ad
->inner
, disp
);
2820 update_address (ad
);
2824 if (lra_dump_file
!= NULL
)
2827 fprintf (lra_dump_file
, " -- no change\n");
2830 fprintf (lra_dump_file
, " on equiv ");
2831 dump_value_slim (lra_dump_file
, *ad
->outer
, 1);
2832 fprintf (lra_dump_file
, "\n");
2838 /* Major function to make reloads for an address in operand NOP or
2839 check its correctness (If CHECK_ONLY_P is true). The supported
2842 1) an address that existed before LRA started, at which point it
2843 must have been valid. These addresses are subject to elimination
2844 and may have become invalid due to the elimination offset being out
2847 2) an address created by forcing a constant to memory
2848 (force_const_to_mem). The initial form of these addresses might
2849 not be valid, and it is this function's job to make them valid.
2851 3) a frame address formed from a register and a (possibly zero)
2852 constant offset. As above, these addresses might not be valid and
2853 this function must make them so.
2855 Add reloads to the lists *BEFORE and *AFTER. We might need to add
2856 reloads to *AFTER because of inc/dec, {pre, post} modify in the
2857 address. Return true for any RTL change.
2859 The function is a helper function which does not produce all
2860 transformations (when CHECK_ONLY_P is false) which can be
2861 necessary. It does just basic steps. To do all necessary
2862 transformations use function process_address. */
2864 process_address_1 (int nop
, bool check_only_p
,
2865 rtx_insn
**before
, rtx_insn
**after
)
2867 struct address_info ad
;
2869 rtx op
= *curr_id
->operand_loc
[nop
];
2870 const char *constraint
= curr_static_id
->operand
[nop
].constraint
;
2871 enum constraint_num cn
= lookup_constraint (constraint
);
2872 bool change_p
= false;
2874 if (insn_extra_address_constraint (cn
))
2875 decompose_lea_address (&ad
, curr_id
->operand_loc
[nop
]);
2876 else if (MEM_P (op
))
2877 decompose_mem_address (&ad
, op
);
2878 else if (GET_CODE (op
) == SUBREG
2879 && MEM_P (SUBREG_REG (op
)))
2880 decompose_mem_address (&ad
, SUBREG_REG (op
));
2883 /* If INDEX_REG_CLASS is assigned to base_term already and isn't to
2884 index_term, swap them so to avoid assigning INDEX_REG_CLASS to both
2885 when INDEX_REG_CLASS is a single register class. */
2886 if (ad
.base_term
!= NULL
2887 && ad
.index_term
!= NULL
2888 && ira_class_hard_regs_num
[INDEX_REG_CLASS
] == 1
2889 && REG_P (*ad
.base_term
)
2890 && REG_P (*ad
.index_term
)
2891 && in_class_p (*ad
.base_term
, INDEX_REG_CLASS
, NULL
)
2892 && ! in_class_p (*ad
.index_term
, INDEX_REG_CLASS
, NULL
))
2894 std::swap (ad
.base
, ad
.index
);
2895 std::swap (ad
.base_term
, ad
.index_term
);
2898 change_p
= equiv_address_substitution (&ad
);
2899 if (ad
.base_term
!= NULL
2900 && (process_addr_reg
2901 (ad
.base_term
, check_only_p
, before
,
2903 && !(REG_P (*ad
.base_term
)
2904 && find_regno_note (curr_insn
, REG_DEAD
,
2905 REGNO (*ad
.base_term
)) != NULL_RTX
)
2907 base_reg_class (ad
.mode
, ad
.as
, ad
.base_outer_code
,
2908 get_index_code (&ad
)))))
2911 if (ad
.base_term2
!= NULL
)
2912 *ad
.base_term2
= *ad
.base_term
;
2914 if (ad
.index_term
!= NULL
2915 && process_addr_reg (ad
.index_term
, check_only_p
,
2916 before
, NULL
, INDEX_REG_CLASS
))
2919 /* Target hooks sometimes don't treat extra-constraint addresses as
2920 legitimate address_operands, so handle them specially. */
2921 if (insn_extra_address_constraint (cn
)
2922 && satisfies_address_constraint_p (&ad
, cn
))
2928 /* There are three cases where the shape of *AD.INNER may now be invalid:
2930 1) the original address was valid, but either elimination or
2931 equiv_address_substitution was applied and that made
2932 the address invalid.
2934 2) the address is an invalid symbolic address created by
2937 3) the address is a frame address with an invalid offset.
2939 4) the address is a frame address with an invalid base.
2941 All these cases involve a non-autoinc address, so there is no
2942 point revalidating other types. */
2943 if (ad
.autoinc_p
|| valid_address_p (&ad
))
2946 /* Any index existed before LRA started, so we can assume that the
2947 presence and shape of the index is valid. */
2948 push_to_sequence (*before
);
2949 lra_assert (ad
.disp
== ad
.disp_term
);
2950 if (ad
.base
== NULL
)
2952 if (ad
.index
== NULL
)
2955 enum reg_class cl
= base_reg_class (ad
.mode
, ad
.as
,
2957 rtx addr
= *ad
.inner
;
2959 new_reg
= lra_create_new_reg (Pmode
, NULL_RTX
, cl
, "addr");
2963 rtx_insn
*last
= get_last_insn ();
2965 /* addr => lo_sum (new_base, addr), case (2) above. */
2966 insn
= emit_insn (gen_rtx_SET
2968 gen_rtx_HIGH (Pmode
, copy_rtx (addr
))));
2969 code
= recog_memoized (insn
);
2972 *ad
.inner
= gen_rtx_LO_SUM (Pmode
, new_reg
, addr
);
2973 if (! valid_address_p (ad
.mode
, *ad
.outer
, ad
.as
))
2975 /* Try to put lo_sum into register. */
2976 insn
= emit_insn (gen_rtx_SET
2978 gen_rtx_LO_SUM (Pmode
, new_reg
, addr
)));
2979 code
= recog_memoized (insn
);
2982 *ad
.inner
= new_reg
;
2983 if (! valid_address_p (ad
.mode
, *ad
.outer
, ad
.as
))
2993 delete_insns_since (last
);
2998 /* addr => new_base, case (2) above. */
2999 lra_emit_move (new_reg
, addr
);
3000 *ad
.inner
= new_reg
;
3005 /* index * scale + disp => new base + index * scale,
3007 enum reg_class cl
= base_reg_class (ad
.mode
, ad
.as
, PLUS
,
3008 GET_CODE (*ad
.index
));
3010 lra_assert (INDEX_REG_CLASS
!= NO_REGS
);
3011 new_reg
= lra_create_new_reg (Pmode
, NULL_RTX
, cl
, "disp");
3012 lra_emit_move (new_reg
, *ad
.disp
);
3013 *ad
.inner
= simplify_gen_binary (PLUS
, GET_MODE (new_reg
),
3014 new_reg
, *ad
.index
);
3017 else if (ad
.index
== NULL
)
3022 rtx_insn
*insns
, *last_insn
;
3023 /* Try to reload base into register only if the base is invalid
3024 for the address but with valid offset, case (4) above. */
3026 new_reg
= base_to_reg (&ad
);
3028 /* base + disp => new base, cases (1) and (3) above. */
3029 /* Another option would be to reload the displacement into an
3030 index register. However, postreload has code to optimize
3031 address reloads that have the same base and different
3032 displacements, so reloading into an index register would
3033 not necessarily be a win. */
3034 if (new_reg
== NULL_RTX
)
3035 new_reg
= base_plus_disp_to_reg (&ad
);
3036 insns
= get_insns ();
3037 last_insn
= get_last_insn ();
3038 /* If we generated at least two insns, try last insn source as
3039 an address. If we succeed, we generate one less insn. */
3040 if (last_insn
!= insns
&& (set
= single_set (last_insn
)) != NULL_RTX
3041 && GET_CODE (SET_SRC (set
)) == PLUS
3042 && REG_P (XEXP (SET_SRC (set
), 0))
3043 && CONSTANT_P (XEXP (SET_SRC (set
), 1)))
3045 *ad
.inner
= SET_SRC (set
);
3046 if (valid_address_p (ad
.mode
, *ad
.outer
, ad
.as
))
3048 *ad
.base_term
= XEXP (SET_SRC (set
), 0);
3049 *ad
.disp_term
= XEXP (SET_SRC (set
), 1);
3050 cl
= base_reg_class (ad
.mode
, ad
.as
, ad
.base_outer_code
,
3051 get_index_code (&ad
));
3052 regno
= REGNO (*ad
.base_term
);
3053 if (regno
>= FIRST_PSEUDO_REGISTER
3054 && cl
!= lra_get_allocno_class (regno
))
3055 lra_change_class (regno
, cl
, " Change to", true);
3056 new_reg
= SET_SRC (set
);
3057 delete_insns_since (PREV_INSN (last_insn
));
3060 /* Try if target can split displacement into legitimite new disp
3061 and offset. If it's the case, we replace the last insn with
3062 insns for base + offset => new_reg and set new_reg + new disp
3064 last_insn
= get_last_insn ();
3065 if ((set
= single_set (last_insn
)) != NULL_RTX
3066 && GET_CODE (SET_SRC (set
)) == PLUS
3067 && REG_P (XEXP (SET_SRC (set
), 0))
3068 && REGNO (XEXP (SET_SRC (set
), 0)) < FIRST_PSEUDO_REGISTER
3069 && CONST_INT_P (XEXP (SET_SRC (set
), 1)))
3071 rtx addend
, disp
= XEXP (SET_SRC (set
), 1);
3072 if (targetm
.legitimize_address_displacement (&disp
, &addend
,
3075 rtx_insn
*new_insns
;
3077 lra_emit_add (new_reg
, XEXP (SET_SRC (set
), 0), addend
);
3078 new_insns
= get_insns ();
3080 new_reg
= gen_rtx_PLUS (Pmode
, new_reg
, disp
);
3081 delete_insns_since (PREV_INSN (last_insn
));
3082 add_insn (new_insns
);
3083 insns
= get_insns ();
3088 *ad
.inner
= new_reg
;
3090 else if (ad
.disp_term
!= NULL
)
3092 /* base + scale * index + disp => new base + scale * index,
3094 new_reg
= base_plus_disp_to_reg (&ad
);
3095 *ad
.inner
= simplify_gen_binary (PLUS
, GET_MODE (new_reg
),
3096 new_reg
, *ad
.index
);
3098 else if (get_index_scale (&ad
) == 1)
3100 /* The last transformation to one reg will be made in
3101 curr_insn_transform function. */
3107 /* base + scale * index => base + new_reg,
3109 Index part of address may become invalid. For example, we
3110 changed pseudo on the equivalent memory and a subreg of the
3111 pseudo onto the memory of different mode for which the scale is
3113 new_reg
= index_part_to_reg (&ad
);
3114 *ad
.inner
= simplify_gen_binary (PLUS
, GET_MODE (new_reg
),
3115 *ad
.base_term
, new_reg
);
3117 *before
= get_insns ();
3122 /* If CHECK_ONLY_P is false, do address reloads until it is necessary.
3123 Use process_address_1 as a helper function. Return true for any
3126 If CHECK_ONLY_P is true, just check address correctness. Return
3127 false if the address correct. */
3129 process_address (int nop
, bool check_only_p
,
3130 rtx_insn
**before
, rtx_insn
**after
)
3134 while (process_address_1 (nop
, check_only_p
, before
, after
))
3143 /* Emit insns to reload VALUE into a new register. VALUE is an
3144 auto-increment or auto-decrement RTX whose operand is a register or
3145 memory location; so reloading involves incrementing that location.
3146 IN is either identical to VALUE, or some cheaper place to reload
3147 value being incremented/decremented from.
3149 INC_AMOUNT is the number to increment or decrement by (always
3150 positive and ignored for POST_MODIFY/PRE_MODIFY).
3152 Return pseudo containing the result. */
3154 emit_inc (enum reg_class new_rclass
, rtx in
, rtx value
, int inc_amount
)
3156 /* REG or MEM to be copied and incremented. */
3157 rtx incloc
= XEXP (value
, 0);
3158 /* Nonzero if increment after copying. */
3159 int post
= (GET_CODE (value
) == POST_DEC
|| GET_CODE (value
) == POST_INC
3160 || GET_CODE (value
) == POST_MODIFY
);
3165 rtx real_in
= in
== value
? incloc
: in
;
3169 if (GET_CODE (value
) == PRE_MODIFY
|| GET_CODE (value
) == POST_MODIFY
)
3171 lra_assert (GET_CODE (XEXP (value
, 1)) == PLUS
3172 || GET_CODE (XEXP (value
, 1)) == MINUS
);
3173 lra_assert (rtx_equal_p (XEXP (XEXP (value
, 1), 0), XEXP (value
, 0)));
3174 plus_p
= GET_CODE (XEXP (value
, 1)) == PLUS
;
3175 inc
= XEXP (XEXP (value
, 1), 1);
3179 if (GET_CODE (value
) == PRE_DEC
|| GET_CODE (value
) == POST_DEC
)
3180 inc_amount
= -inc_amount
;
3182 inc
= GEN_INT (inc_amount
);
3185 if (! post
&& REG_P (incloc
))
3188 result
= lra_create_new_reg (GET_MODE (value
), value
, new_rclass
,
3191 if (real_in
!= result
)
3193 /* First copy the location to the result register. */
3194 lra_assert (REG_P (result
));
3195 emit_insn (gen_move_insn (result
, real_in
));
3198 /* We suppose that there are insns to add/sub with the constant
3199 increment permitted in {PRE/POST)_{DEC/INC/MODIFY}. At least the
3200 old reload worked with this assumption. If the assumption
3201 becomes wrong, we should use approach in function
3202 base_plus_disp_to_reg. */
3205 /* See if we can directly increment INCLOC. */
3206 last
= get_last_insn ();
3207 add_insn
= emit_insn (plus_p
3208 ? gen_add2_insn (incloc
, inc
)
3209 : gen_sub2_insn (incloc
, inc
));
3211 code
= recog_memoized (add_insn
);
3214 if (! post
&& result
!= incloc
)
3215 emit_insn (gen_move_insn (result
, incloc
));
3218 delete_insns_since (last
);
3221 /* If couldn't do the increment directly, must increment in RESULT.
3222 The way we do this depends on whether this is pre- or
3223 post-increment. For pre-increment, copy INCLOC to the reload
3224 register, increment it there, then save back. */
3227 if (real_in
!= result
)
3228 emit_insn (gen_move_insn (result
, real_in
));
3230 emit_insn (gen_add2_insn (result
, inc
));
3232 emit_insn (gen_sub2_insn (result
, inc
));
3233 if (result
!= incloc
)
3234 emit_insn (gen_move_insn (incloc
, result
));
3240 Because this might be a jump insn or a compare, and because
3241 RESULT may not be available after the insn in an input
3242 reload, we must do the incrementing before the insn being
3245 We have already copied IN to RESULT. Increment the copy in
3246 RESULT, save that back, then decrement RESULT so it has
3247 the original value. */
3249 emit_insn (gen_add2_insn (result
, inc
));
3251 emit_insn (gen_sub2_insn (result
, inc
));
3252 emit_insn (gen_move_insn (incloc
, result
));
3253 /* Restore non-modified value for the result. We prefer this
3254 way because it does not require an additional hard
3258 if (CONST_INT_P (inc
))
3259 emit_insn (gen_add2_insn (result
,
3260 gen_int_mode (-INTVAL (inc
),
3261 GET_MODE (result
))));
3263 emit_insn (gen_sub2_insn (result
, inc
));
3266 emit_insn (gen_add2_insn (result
, inc
));
3271 /* Return true if the current move insn does not need processing as we
3272 already know that it satisfies its constraints. */
3274 simple_move_p (void)
3277 enum reg_class dclass
, sclass
;
3279 lra_assert (curr_insn_set
!= NULL_RTX
);
3280 dest
= SET_DEST (curr_insn_set
);
3281 src
= SET_SRC (curr_insn_set
);
3282 return ((dclass
= get_op_class (dest
)) != NO_REGS
3283 && (sclass
= get_op_class (src
)) != NO_REGS
3284 /* The backend guarantees that register moves of cost 2
3285 never need reloads. */
3286 && targetm
.register_move_cost (GET_MODE (src
), sclass
, dclass
) == 2);
3289 /* Swap operands NOP and NOP + 1. */
3291 swap_operands (int nop
)
3293 std::swap (curr_operand_mode
[nop
], curr_operand_mode
[nop
+ 1]);
3294 std::swap (original_subreg_reg_mode
[nop
], original_subreg_reg_mode
[nop
+ 1]);
3295 std::swap (*curr_id
->operand_loc
[nop
], *curr_id
->operand_loc
[nop
+ 1]);
3296 /* Swap the duplicates too. */
3297 lra_update_dup (curr_id
, nop
);
3298 lra_update_dup (curr_id
, nop
+ 1);
3301 /* Main entry point of the constraint code: search the body of the
3302 current insn to choose the best alternative. It is mimicking insn
3303 alternative cost calculation model of former reload pass. That is
3304 because machine descriptions were written to use this model. This
3305 model can be changed in future. Make commutative operand exchange
3308 if CHECK_ONLY_P is false, do RTL changes to satisfy the
3309 constraints. Return true if any change happened during function
3312 If CHECK_ONLY_P is true then don't do any transformation. Just
3313 check that the insn satisfies all constraints. If the insn does
3314 not satisfy any constraint, return true. */
3316 curr_insn_transform (bool check_only_p
)
3322 signed char goal_alt_matched
[MAX_RECOG_OPERANDS
][MAX_RECOG_OPERANDS
];
3323 signed char match_inputs
[MAX_RECOG_OPERANDS
+ 1];
3324 rtx_insn
*before
, *after
;
3326 /* Flag that the insn has been changed through a transformation. */
3329 #ifdef SECONDARY_MEMORY_NEEDED
3332 int max_regno_before
;
3333 int reused_alternative_num
;
3335 curr_insn_set
= single_set (curr_insn
);
3336 if (curr_insn_set
!= NULL_RTX
&& simple_move_p ())
3339 no_input_reloads_p
= no_output_reloads_p
= false;
3340 goal_alt_number
= -1;
3341 change_p
= sec_mem_p
= false;
3342 /* JUMP_INSNs and CALL_INSNs are not allowed to have any output
3343 reloads; neither are insns that SET cc0. Insns that use CC0 are
3344 not allowed to have any input reloads. */
3345 if (JUMP_P (curr_insn
) || CALL_P (curr_insn
))
3346 no_output_reloads_p
= true;
3348 if (HAVE_cc0
&& reg_referenced_p (cc0_rtx
, PATTERN (curr_insn
)))
3349 no_input_reloads_p
= true;
3350 if (HAVE_cc0
&& reg_set_p (cc0_rtx
, PATTERN (curr_insn
)))
3351 no_output_reloads_p
= true;
3353 n_operands
= curr_static_id
->n_operands
;
3354 n_alternatives
= curr_static_id
->n_alternatives
;
3356 /* Just return "no reloads" if insn has no operands with
3358 if (n_operands
== 0 || n_alternatives
== 0)
3361 max_regno_before
= max_reg_num ();
3363 for (i
= 0; i
< n_operands
; i
++)
3365 goal_alt_matched
[i
][0] = -1;
3366 goal_alt_matches
[i
] = -1;
3369 commutative
= curr_static_id
->commutative
;
3371 /* Now see what we need for pseudos that didn't get hard regs or got
3372 the wrong kind of hard reg. For this, we must consider all the
3373 operands together against the register constraints. */
3375 best_losers
= best_overall
= INT_MAX
;
3376 best_reload_sum
= 0;
3378 curr_swapped
= false;
3379 goal_alt_swapped
= false;
3382 /* Make equivalence substitution and memory subreg elimination
3383 before address processing because an address legitimacy can
3384 depend on memory mode. */
3385 for (i
= 0; i
< n_operands
; i
++)
3387 rtx op
= *curr_id
->operand_loc
[i
];
3388 rtx subst
, old
= op
;
3389 bool op_change_p
= false;
3391 if (GET_CODE (old
) == SUBREG
)
3392 old
= SUBREG_REG (old
);
3393 subst
= get_equiv_with_elimination (old
, curr_insn
);
3394 original_subreg_reg_mode
[i
] = VOIDmode
;
3397 subst
= copy_rtx (subst
);
3398 lra_assert (REG_P (old
));
3399 if (GET_CODE (op
) != SUBREG
)
3400 *curr_id
->operand_loc
[i
] = subst
;
3403 SUBREG_REG (op
) = subst
;
3404 if (GET_MODE (subst
) == VOIDmode
)
3405 original_subreg_reg_mode
[i
] = GET_MODE (old
);
3407 if (lra_dump_file
!= NULL
)
3409 fprintf (lra_dump_file
,
3410 "Changing pseudo %d in operand %i of insn %u on equiv ",
3411 REGNO (old
), i
, INSN_UID (curr_insn
));
3412 dump_value_slim (lra_dump_file
, subst
, 1);
3413 fprintf (lra_dump_file
, "\n");
3415 op_change_p
= change_p
= true;
3417 if (simplify_operand_subreg (i
, GET_MODE (old
)) || op_change_p
)
3420 lra_update_dup (curr_id
, i
);
3424 /* Reload address registers and displacements. We do it before
3425 finding an alternative because of memory constraints. */
3426 before
= after
= NULL
;
3427 for (i
= 0; i
< n_operands
; i
++)
3428 if (! curr_static_id
->operand
[i
].is_operator
3429 && process_address (i
, check_only_p
, &before
, &after
))
3434 lra_update_dup (curr_id
, i
);
3438 /* If we've changed the instruction then any alternative that
3439 we chose previously may no longer be valid. */
3440 lra_set_used_insn_alternative (curr_insn
, -1);
3442 if (! check_only_p
&& curr_insn_set
!= NULL_RTX
3443 && check_and_process_move (&change_p
, &sec_mem_p
))
3448 reused_alternative_num
= check_only_p
? -1 : curr_id
->used_insn_alternative
;
3449 if (lra_dump_file
!= NULL
&& reused_alternative_num
>= 0)
3450 fprintf (lra_dump_file
, "Reusing alternative %d for insn #%u\n",
3451 reused_alternative_num
, INSN_UID (curr_insn
));
3453 if (process_alt_operands (reused_alternative_num
))
3457 return ! alt_p
|| best_losers
!= 0;
3459 /* If insn is commutative (it's safe to exchange a certain pair of
3460 operands) then we need to try each alternative twice, the second
3461 time matching those two operands as if we had exchanged them. To
3462 do this, really exchange them in operands.
3464 If we have just tried the alternatives the second time, return
3465 operands to normal and drop through. */
3467 if (reused_alternative_num
< 0 && commutative
>= 0)
3469 curr_swapped
= !curr_swapped
;
3472 swap_operands (commutative
);
3476 swap_operands (commutative
);
3479 if (! alt_p
&& ! sec_mem_p
)
3481 /* No alternative works with reloads?? */
3482 if (INSN_CODE (curr_insn
) >= 0)
3483 fatal_insn ("unable to generate reloads for:", curr_insn
);
3484 error_for_asm (curr_insn
,
3485 "inconsistent operand constraints in an %<asm%>");
3486 /* Avoid further trouble with this insn. */
3487 PATTERN (curr_insn
) = gen_rtx_USE (VOIDmode
, const0_rtx
);
3488 lra_invalidate_insn_data (curr_insn
);
3492 /* If the best alternative is with operands 1 and 2 swapped, swap
3493 them. Update the operand numbers of any reloads already
3496 if (goal_alt_swapped
)
3498 if (lra_dump_file
!= NULL
)
3499 fprintf (lra_dump_file
, " Commutative operand exchange in insn %u\n",
3500 INSN_UID (curr_insn
));
3502 /* Swap the duplicates too. */
3503 swap_operands (commutative
);
3507 #ifdef SECONDARY_MEMORY_NEEDED
3508 /* Some target macros SECONDARY_MEMORY_NEEDED (e.g. x86) are defined
3509 too conservatively. So we use the secondary memory only if there
3510 is no any alternative without reloads. */
3511 use_sec_mem_p
= false;
3513 use_sec_mem_p
= true;
3516 for (i
= 0; i
< n_operands
; i
++)
3517 if (! goal_alt_win
[i
] && ! goal_alt_match_win
[i
])
3519 use_sec_mem_p
= i
< n_operands
;
3524 rtx new_reg
, src
, dest
, rld
;
3525 machine_mode sec_mode
, rld_mode
;
3527 lra_assert (sec_mem_p
);
3528 lra_assert (curr_static_id
->operand
[0].type
== OP_OUT
3529 && curr_static_id
->operand
[1].type
== OP_IN
);
3530 dest
= *curr_id
->operand_loc
[0];
3531 src
= *curr_id
->operand_loc
[1];
3532 rld
= (GET_MODE_SIZE (GET_MODE (dest
)) <= GET_MODE_SIZE (GET_MODE (src
))
3534 rld_mode
= GET_MODE (rld
);
3535 #ifdef SECONDARY_MEMORY_NEEDED_MODE
3536 sec_mode
= SECONDARY_MEMORY_NEEDED_MODE (rld_mode
);
3538 sec_mode
= rld_mode
;
3540 new_reg
= lra_create_new_reg (sec_mode
, NULL_RTX
,
3541 NO_REGS
, "secondary");
3542 /* If the mode is changed, it should be wider. */
3543 lra_assert (GET_MODE_SIZE (sec_mode
) >= GET_MODE_SIZE (rld_mode
));
3544 if (sec_mode
!= rld_mode
)
3546 /* If the target says specifically to use another mode for
3547 secondary memory moves we can not reuse the original
3549 after
= emit_spill_move (false, new_reg
, dest
);
3550 lra_process_new_insns (curr_insn
, NULL
, after
,
3551 "Inserting the sec. move");
3552 /* We may have non null BEFORE here (e.g. after address
3554 push_to_sequence (before
);
3555 before
= emit_spill_move (true, new_reg
, src
);
3557 before
= get_insns ();
3559 lra_process_new_insns (curr_insn
, before
, NULL
, "Changing on");
3560 lra_set_insn_deleted (curr_insn
);
3562 else if (dest
== rld
)
3564 *curr_id
->operand_loc
[0] = new_reg
;
3565 after
= emit_spill_move (false, new_reg
, dest
);
3566 lra_process_new_insns (curr_insn
, NULL
, after
,
3567 "Inserting the sec. move");
3571 *curr_id
->operand_loc
[1] = new_reg
;
3572 /* See comments above. */
3573 push_to_sequence (before
);
3574 before
= emit_spill_move (true, new_reg
, src
);
3576 before
= get_insns ();
3578 lra_process_new_insns (curr_insn
, before
, NULL
,
3579 "Inserting the sec. move");
3581 lra_update_insn_regno_info (curr_insn
);
3586 lra_assert (goal_alt_number
>= 0);
3587 lra_set_used_insn_alternative (curr_insn
, goal_alt_number
);
3589 if (lra_dump_file
!= NULL
)
3593 fprintf (lra_dump_file
, " Choosing alt %d in insn %u:",
3594 goal_alt_number
, INSN_UID (curr_insn
));
3595 for (i
= 0; i
< n_operands
; i
++)
3597 p
= (curr_static_id
->operand_alternative
3598 [goal_alt_number
* n_operands
+ i
].constraint
);
3601 fprintf (lra_dump_file
, " (%d) ", i
);
3602 for (; *p
!= '\0' && *p
!= ',' && *p
!= '#'; p
++)
3603 fputc (*p
, lra_dump_file
);
3605 if (INSN_CODE (curr_insn
) >= 0
3606 && (p
= get_insn_name (INSN_CODE (curr_insn
))) != NULL
)
3607 fprintf (lra_dump_file
, " {%s}", p
);
3608 if (curr_id
->sp_offset
!= 0)
3609 fprintf (lra_dump_file
, " (sp_off=%" HOST_WIDE_INT_PRINT
"d)",
3610 curr_id
->sp_offset
);
3611 fprintf (lra_dump_file
, "\n");
3614 /* Right now, for any pair of operands I and J that are required to
3615 match, with J < I, goal_alt_matches[I] is J. Add I to
3616 goal_alt_matched[J]. */
3618 for (i
= 0; i
< n_operands
; i
++)
3619 if ((j
= goal_alt_matches
[i
]) >= 0)
3621 for (k
= 0; goal_alt_matched
[j
][k
] >= 0; k
++)
3623 /* We allow matching one output operand and several input
3626 || (curr_static_id
->operand
[j
].type
== OP_OUT
3627 && curr_static_id
->operand
[i
].type
== OP_IN
3628 && (curr_static_id
->operand
3629 [goal_alt_matched
[j
][0]].type
== OP_IN
)));
3630 goal_alt_matched
[j
][k
] = i
;
3631 goal_alt_matched
[j
][k
+ 1] = -1;
3634 for (i
= 0; i
< n_operands
; i
++)
3635 goal_alt_win
[i
] |= goal_alt_match_win
[i
];
3637 /* Any constants that aren't allowed and can't be reloaded into
3638 registers are here changed into memory references. */
3639 for (i
= 0; i
< n_operands
; i
++)
3640 if (goal_alt_win
[i
])
3643 enum reg_class new_class
;
3644 rtx reg
= *curr_id
->operand_loc
[i
];
3646 if (GET_CODE (reg
) == SUBREG
)
3647 reg
= SUBREG_REG (reg
);
3649 if (REG_P (reg
) && (regno
= REGNO (reg
)) >= FIRST_PSEUDO_REGISTER
)
3651 bool ok_p
= in_class_p (reg
, goal_alt
[i
], &new_class
);
3653 if (new_class
!= NO_REGS
&& get_reg_class (regno
) != new_class
)
3656 lra_change_class (regno
, new_class
, " Change to", true);
3662 const char *constraint
;
3664 rtx op
= *curr_id
->operand_loc
[i
];
3665 rtx subreg
= NULL_RTX
;
3666 machine_mode mode
= curr_operand_mode
[i
];
3668 if (GET_CODE (op
) == SUBREG
)
3671 op
= SUBREG_REG (op
);
3672 mode
= GET_MODE (op
);
3675 if (CONST_POOL_OK_P (mode
, op
)
3676 && ((targetm
.preferred_reload_class
3677 (op
, (enum reg_class
) goal_alt
[i
]) == NO_REGS
)
3678 || no_input_reloads_p
))
3680 rtx tem
= force_const_mem (mode
, op
);
3683 if (subreg
!= NULL_RTX
)
3684 tem
= gen_rtx_SUBREG (mode
, tem
, SUBREG_BYTE (subreg
));
3686 *curr_id
->operand_loc
[i
] = tem
;
3687 lra_update_dup (curr_id
, i
);
3688 process_address (i
, false, &before
, &after
);
3690 /* If the alternative accepts constant pool refs directly
3691 there will be no reload needed at all. */
3692 if (subreg
!= NULL_RTX
)
3694 /* Skip alternatives before the one requested. */
3695 constraint
= (curr_static_id
->operand_alternative
3696 [goal_alt_number
* n_operands
+ i
].constraint
);
3698 (c
= *constraint
) && c
!= ',' && c
!= '#';
3699 constraint
+= CONSTRAINT_LEN (c
, constraint
))
3701 enum constraint_num cn
= lookup_constraint (constraint
);
3702 if (insn_extra_memory_constraint (cn
)
3703 && satisfies_memory_constraint_p (tem
, cn
))
3706 if (c
== '\0' || c
== ',' || c
== '#')
3709 goal_alt_win
[i
] = true;
3713 for (i
= 0; i
< n_operands
; i
++)
3716 bool optional_p
= false;
3718 rtx op
= *curr_id
->operand_loc
[i
];
3720 if (goal_alt_win
[i
])
3722 if (goal_alt
[i
] == NO_REGS
3724 /* When we assign NO_REGS it means that we will not
3725 assign a hard register to the scratch pseudo by
3726 assigment pass and the scratch pseudo will be
3727 spilled. Spilled scratch pseudos are transformed
3728 back to scratches at the LRA end. */
3729 && lra_former_scratch_operand_p (curr_insn
, i
))
3731 int regno
= REGNO (op
);
3732 lra_change_class (regno
, NO_REGS
, " Change to", true);
3733 if (lra_get_regno_hard_regno (regno
) >= 0)
3734 /* We don't have to mark all insn affected by the
3735 spilled pseudo as there is only one such insn, the
3737 reg_renumber
[regno
] = -1;
3739 /* We can do an optional reload. If the pseudo got a hard
3740 reg, we might improve the code through inheritance. If
3741 it does not get a hard register we coalesce memory/memory
3742 moves later. Ignore move insns to avoid cycling. */
3744 && lra_undo_inheritance_iter
< LRA_MAX_INHERITANCE_PASSES
3745 && goal_alt
[i
] != NO_REGS
&& REG_P (op
)
3746 && (regno
= REGNO (op
)) >= FIRST_PSEUDO_REGISTER
3747 && regno
< new_regno_start
3748 && ! lra_former_scratch_p (regno
)
3749 && reg_renumber
[regno
] < 0
3750 /* Check that the optional reload pseudo will be able to
3751 hold given mode value. */
3752 && ! (prohibited_class_reg_set_mode_p
3753 (goal_alt
[i
], reg_class_contents
[goal_alt
[i
]],
3754 PSEUDO_REGNO_MODE (regno
)))
3755 && (curr_insn_set
== NULL_RTX
3756 || !((REG_P (SET_SRC (curr_insn_set
))
3757 || MEM_P (SET_SRC (curr_insn_set
))
3758 || GET_CODE (SET_SRC (curr_insn_set
)) == SUBREG
)
3759 && (REG_P (SET_DEST (curr_insn_set
))
3760 || MEM_P (SET_DEST (curr_insn_set
))
3761 || GET_CODE (SET_DEST (curr_insn_set
)) == SUBREG
))))
3767 /* Operands that match previous ones have already been handled. */
3768 if (goal_alt_matches
[i
] >= 0)
3771 /* We should not have an operand with a non-offsettable address
3772 appearing where an offsettable address will do. It also may
3773 be a case when the address should be special in other words
3774 not a general one (e.g. it needs no index reg). */
3775 if (goal_alt_matched
[i
][0] == -1 && goal_alt_offmemok
[i
] && MEM_P (op
))
3777 enum reg_class rclass
;
3778 rtx
*loc
= &XEXP (op
, 0);
3779 enum rtx_code code
= GET_CODE (*loc
);
3781 push_to_sequence (before
);
3782 rclass
= base_reg_class (GET_MODE (op
), MEM_ADDR_SPACE (op
),
3784 if (GET_RTX_CLASS (code
) == RTX_AUTOINC
)
3785 new_reg
= emit_inc (rclass
, *loc
, *loc
,
3786 /* This value does not matter for MODIFY. */
3787 GET_MODE_SIZE (GET_MODE (op
)));
3788 else if (get_reload_reg (OP_IN
, Pmode
, *loc
, rclass
, FALSE
,
3789 "offsetable address", &new_reg
))
3790 lra_emit_move (new_reg
, *loc
);
3791 before
= get_insns ();
3794 lra_update_dup (curr_id
, i
);
3796 else if (goal_alt_matched
[i
][0] == -1)
3800 int hard_regno
, byte
;
3801 enum op_type type
= curr_static_id
->operand
[i
].type
;
3803 loc
= curr_id
->operand_loc
[i
];
3804 mode
= curr_operand_mode
[i
];
3805 if (GET_CODE (*loc
) == SUBREG
)
3807 reg
= SUBREG_REG (*loc
);
3808 byte
= SUBREG_BYTE (*loc
);
3810 /* Strict_low_part requires reload the register not
3811 the sub-register. */
3812 && (curr_static_id
->operand
[i
].strict_low
3813 || (GET_MODE_SIZE (mode
)
3814 <= GET_MODE_SIZE (GET_MODE (reg
))
3816 = get_try_hard_regno (REGNO (reg
))) >= 0
3817 && (simplify_subreg_regno
3819 GET_MODE (reg
), byte
, mode
) < 0)
3820 && (goal_alt
[i
] == NO_REGS
3821 || (simplify_subreg_regno
3822 (ira_class_hard_regs
[goal_alt
[i
]][0],
3823 GET_MODE (reg
), byte
, mode
) >= 0)))))
3827 loc
= &SUBREG_REG (*loc
);
3828 mode
= GET_MODE (*loc
);
3832 if (get_reload_reg (type
, mode
, old
, goal_alt
[i
],
3833 loc
!= curr_id
->operand_loc
[i
], "", &new_reg
)
3836 push_to_sequence (before
);
3837 lra_emit_move (new_reg
, old
);
3838 before
= get_insns ();
3843 && find_reg_note (curr_insn
, REG_UNUSED
, old
) == NULL_RTX
)
3846 lra_emit_move (type
== OP_INOUT
? copy_rtx (old
) : old
, new_reg
);
3848 after
= get_insns ();
3852 for (j
= 0; j
< goal_alt_dont_inherit_ops_num
; j
++)
3853 if (goal_alt_dont_inherit_ops
[j
] == i
)
3855 lra_set_regno_unique_value (REGNO (new_reg
));
3858 lra_update_dup (curr_id
, i
);
3860 else if (curr_static_id
->operand
[i
].type
== OP_IN
3861 && (curr_static_id
->operand
[goal_alt_matched
[i
][0]].type
3864 /* generate reloads for input and matched outputs. */
3865 match_inputs
[0] = i
;
3866 match_inputs
[1] = -1;
3867 match_reload (goal_alt_matched
[i
][0], match_inputs
,
3868 goal_alt
[i
], &before
, &after
);
3870 else if (curr_static_id
->operand
[i
].type
== OP_OUT
3871 && (curr_static_id
->operand
[goal_alt_matched
[i
][0]].type
3873 /* Generate reloads for output and matched inputs. */
3874 match_reload (i
, goal_alt_matched
[i
], goal_alt
[i
], &before
, &after
);
3875 else if (curr_static_id
->operand
[i
].type
== OP_IN
3876 && (curr_static_id
->operand
[goal_alt_matched
[i
][0]].type
3879 /* Generate reloads for matched inputs. */
3880 match_inputs
[0] = i
;
3881 for (j
= 0; (k
= goal_alt_matched
[i
][j
]) >= 0; j
++)
3882 match_inputs
[j
+ 1] = k
;
3883 match_inputs
[j
+ 1] = -1;
3884 match_reload (-1, match_inputs
, goal_alt
[i
], &before
, &after
);
3887 /* We must generate code in any case when function
3888 process_alt_operands decides that it is possible. */
3892 lra_assert (REG_P (op
));
3894 op
= *curr_id
->operand_loc
[i
]; /* Substitution. */
3895 if (GET_CODE (op
) == SUBREG
)
3896 op
= SUBREG_REG (op
);
3897 gcc_assert (REG_P (op
) && (int) REGNO (op
) >= new_regno_start
);
3898 bitmap_set_bit (&lra_optional_reload_pseudos
, REGNO (op
));
3899 lra_reg_info
[REGNO (op
)].restore_regno
= regno
;
3900 if (lra_dump_file
!= NULL
)
3901 fprintf (lra_dump_file
,
3902 " Making reload reg %d for reg %d optional\n",
3906 if (before
!= NULL_RTX
|| after
!= NULL_RTX
3907 || max_regno_before
!= max_reg_num ())
3911 lra_update_operator_dups (curr_id
);
3912 /* Something changes -- process the insn. */
3913 lra_update_insn_regno_info (curr_insn
);
3915 lra_process_new_insns (curr_insn
, before
, after
, "Inserting insn reload");
3919 /* Return true if INSN satisfies all constraints. In other words, no
3920 reload insns are needed. */
3922 lra_constrain_insn (rtx_insn
*insn
)
3924 int saved_new_regno_start
= new_regno_start
;
3925 int saved_new_insn_uid_start
= new_insn_uid_start
;
3929 curr_id
= lra_get_insn_recog_data (curr_insn
);
3930 curr_static_id
= curr_id
->insn_static_data
;
3931 new_insn_uid_start
= get_max_uid ();
3932 new_regno_start
= max_reg_num ();
3933 change_p
= curr_insn_transform (true);
3934 new_regno_start
= saved_new_regno_start
;
3935 new_insn_uid_start
= saved_new_insn_uid_start
;
3939 /* Return true if X is in LIST. */
3941 in_list_p (rtx x
, rtx list
)
3943 for (; list
!= NULL_RTX
; list
= XEXP (list
, 1))
3944 if (XEXP (list
, 0) == x
)
3949 /* Return true if X contains an allocatable hard register (if
3950 HARD_REG_P) or a (spilled if SPILLED_P) pseudo. */
3952 contains_reg_p (rtx x
, bool hard_reg_p
, bool spilled_p
)
3958 code
= GET_CODE (x
);
3961 int regno
= REGNO (x
);
3962 HARD_REG_SET alloc_regs
;
3966 if (regno
>= FIRST_PSEUDO_REGISTER
)
3967 regno
= lra_get_regno_hard_regno (regno
);
3970 COMPL_HARD_REG_SET (alloc_regs
, lra_no_alloc_regs
);
3971 return overlaps_hard_reg_set_p (alloc_regs
, GET_MODE (x
), regno
);
3975 if (regno
< FIRST_PSEUDO_REGISTER
)
3979 return lra_get_regno_hard_regno (regno
) < 0;
3982 fmt
= GET_RTX_FORMAT (code
);
3983 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
3987 if (contains_reg_p (XEXP (x
, i
), hard_reg_p
, spilled_p
))
3990 else if (fmt
[i
] == 'E')
3992 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3993 if (contains_reg_p (XVECEXP (x
, i
, j
), hard_reg_p
, spilled_p
))
4000 /* Return true if X contains a symbol reg. */
4002 contains_symbol_ref_p (rtx x
)
4008 code
= GET_CODE (x
);
4009 if (code
== SYMBOL_REF
)
4011 fmt
= GET_RTX_FORMAT (code
);
4012 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
4016 if (contains_symbol_ref_p (XEXP (x
, i
)))
4019 else if (fmt
[i
] == 'E')
4021 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
4022 if (contains_symbol_ref_p (XVECEXP (x
, i
, j
)))
4029 /* Process all regs in location *LOC and change them on equivalent
4030 substitution. Return true if any change was done. */
4032 loc_equivalence_change_p (rtx
*loc
)
4034 rtx subst
, reg
, x
= *loc
;
4035 bool result
= false;
4036 enum rtx_code code
= GET_CODE (x
);
4042 reg
= SUBREG_REG (x
);
4043 if ((subst
= get_equiv_with_elimination (reg
, curr_insn
)) != reg
4044 && GET_MODE (subst
) == VOIDmode
)
4046 /* We cannot reload debug location. Simplify subreg here
4047 while we know the inner mode. */
4048 *loc
= simplify_gen_subreg (GET_MODE (x
), subst
,
4049 GET_MODE (reg
), SUBREG_BYTE (x
));
4053 if (code
== REG
&& (subst
= get_equiv_with_elimination (x
, curr_insn
)) != x
)
4059 /* Scan all the operand sub-expressions. */
4060 fmt
= GET_RTX_FORMAT (code
);
4061 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
4064 result
= loc_equivalence_change_p (&XEXP (x
, i
)) || result
;
4065 else if (fmt
[i
] == 'E')
4066 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
4068 = loc_equivalence_change_p (&XVECEXP (x
, i
, j
)) || result
;
4073 /* Similar to loc_equivalence_change_p, but for use as
4074 simplify_replace_fn_rtx callback. DATA is insn for which the
4075 elimination is done. If it null we don't do the elimination. */
4077 loc_equivalence_callback (rtx loc
, const_rtx
, void *data
)
4082 rtx subst
= (data
== NULL
4083 ? get_equiv (loc
) : get_equiv_with_elimination (loc
, (rtx_insn
*) data
));
4090 /* Maximum number of generated reload insns per an insn. It is for
4091 preventing this pass cycling in a bug case. */
4092 #define MAX_RELOAD_INSNS_NUMBER LRA_MAX_INSN_RELOADS
4094 /* The current iteration number of this LRA pass. */
4095 int lra_constraint_iter
;
4097 /* True if we substituted equiv which needs checking register
4098 allocation correctness because the equivalent value contains
4099 allocatable hard registers or when we restore multi-register
4101 bool lra_risky_transformations_p
;
4103 /* Return true if REGNO is referenced in more than one block. */
4105 multi_block_pseudo_p (int regno
)
4107 basic_block bb
= NULL
;
4111 if (regno
< FIRST_PSEUDO_REGISTER
)
4114 EXECUTE_IF_SET_IN_BITMAP (&lra_reg_info
[regno
].insn_bitmap
, 0, uid
, bi
)
4116 bb
= BLOCK_FOR_INSN (lra_insn_recog_data
[uid
]->insn
);
4117 else if (BLOCK_FOR_INSN (lra_insn_recog_data
[uid
]->insn
) != bb
)
4122 /* Return true if LIST contains a deleted insn. */
4124 contains_deleted_insn_p (rtx_insn_list
*list
)
4126 for (; list
!= NULL_RTX
; list
= list
->next ())
4127 if (NOTE_P (list
->insn ())
4128 && NOTE_KIND (list
->insn ()) == NOTE_INSN_DELETED
)
4133 /* Return true if X contains a pseudo dying in INSN. */
4135 dead_pseudo_p (rtx x
, rtx_insn
*insn
)
4142 return (insn
!= NULL_RTX
4143 && find_regno_note (insn
, REG_DEAD
, REGNO (x
)) != NULL_RTX
);
4144 code
= GET_CODE (x
);
4145 fmt
= GET_RTX_FORMAT (code
);
4146 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
4150 if (dead_pseudo_p (XEXP (x
, i
), insn
))
4153 else if (fmt
[i
] == 'E')
4155 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
4156 if (dead_pseudo_p (XVECEXP (x
, i
, j
), insn
))
4163 /* Return true if INSN contains a dying pseudo in INSN right hand
4166 insn_rhs_dead_pseudo_p (rtx_insn
*insn
)
4168 rtx set
= single_set (insn
);
4170 gcc_assert (set
!= NULL
);
4171 return dead_pseudo_p (SET_SRC (set
), insn
);
4174 /* Return true if any init insn of REGNO contains a dying pseudo in
4175 insn right hand side. */
4177 init_insn_rhs_dead_pseudo_p (int regno
)
4179 rtx_insn_list
*insns
= ira_reg_equiv
[regno
].init_insns
;
4183 for (; insns
!= NULL_RTX
; insns
= insns
->next ())
4184 if (insn_rhs_dead_pseudo_p (insns
->insn ()))
4189 /* Return TRUE if REGNO has a reverse equivalence. The equivalence is
4190 reverse only if we have one init insn with given REGNO as a
4193 reverse_equiv_p (int regno
)
4195 rtx_insn_list
*insns
= ira_reg_equiv
[regno
].init_insns
;
4200 if (! INSN_P (insns
->insn ())
4201 || insns
->next () != NULL
)
4203 if ((set
= single_set (insns
->insn ())) == NULL_RTX
)
4205 return REG_P (SET_SRC (set
)) && (int) REGNO (SET_SRC (set
)) == regno
;
4208 /* Return TRUE if REGNO was reloaded in an equivalence init insn. We
4209 call this function only for non-reverse equivalence. */
4211 contains_reloaded_insn_p (int regno
)
4214 rtx_insn_list
*list
= ira_reg_equiv
[regno
].init_insns
;
4216 for (; list
!= NULL
; list
= list
->next ())
4217 if ((set
= single_set (list
->insn ())) == NULL_RTX
4218 || ! REG_P (SET_DEST (set
))
4219 || (int) REGNO (SET_DEST (set
)) != regno
)
4224 /* Entry function of LRA constraint pass. Return true if the
4225 constraint pass did change the code. */
4227 lra_constraints (bool first_p
)
4230 int i
, hard_regno
, new_insns_num
;
4231 unsigned int min_len
, new_min_len
, uid
;
4232 rtx set
, x
, reg
, dest_reg
;
4233 basic_block last_bb
;
4234 bitmap_head equiv_insn_bitmap
;
4237 lra_constraint_iter
++;
4238 if (lra_dump_file
!= NULL
)
4239 fprintf (lra_dump_file
, "\n********** Local #%d: **********\n\n",
4240 lra_constraint_iter
);
4242 if (pic_offset_table_rtx
4243 && REGNO (pic_offset_table_rtx
) >= FIRST_PSEUDO_REGISTER
)
4244 lra_risky_transformations_p
= true;
4246 lra_risky_transformations_p
= false;
4247 new_insn_uid_start
= get_max_uid ();
4248 new_regno_start
= first_p
? lra_constraint_new_regno_start
: max_reg_num ();
4249 /* Mark used hard regs for target stack size calulations. */
4250 for (i
= FIRST_PSEUDO_REGISTER
; i
< new_regno_start
; i
++)
4251 if (lra_reg_info
[i
].nrefs
!= 0
4252 && (hard_regno
= lra_get_regno_hard_regno (i
)) >= 0)
4256 nregs
= hard_regno_nregs
[hard_regno
][lra_reg_info
[i
].biggest_mode
];
4257 for (j
= 0; j
< nregs
; j
++)
4258 df_set_regs_ever_live (hard_regno
+ j
, true);
4260 /* Do elimination before the equivalence processing as we can spill
4261 some pseudos during elimination. */
4262 lra_eliminate (false, first_p
);
4263 bitmap_initialize (&equiv_insn_bitmap
, ®_obstack
);
4264 for (i
= FIRST_PSEUDO_REGISTER
; i
< new_regno_start
; i
++)
4265 if (lra_reg_info
[i
].nrefs
!= 0)
4267 ira_reg_equiv
[i
].profitable_p
= true;
4268 reg
= regno_reg_rtx
[i
];
4269 if (lra_get_regno_hard_regno (i
) < 0 && (x
= get_equiv (reg
)) != reg
)
4271 bool pseudo_p
= contains_reg_p (x
, false, false);
4273 /* After RTL transformation, we can not guarantee that
4274 pseudo in the substitution was not reloaded which might
4275 make equivalence invalid. For example, in reverse
4282 the memory address register was reloaded before the 2nd
4284 if ((! first_p
&& pseudo_p
)
4285 /* We don't use DF for compilation speed sake. So it
4286 is problematic to update live info when we use an
4287 equivalence containing pseudos in more than one
4289 || (pseudo_p
&& multi_block_pseudo_p (i
))
4290 /* If an init insn was deleted for some reason, cancel
4291 the equiv. We could update the equiv insns after
4292 transformations including an equiv insn deletion
4293 but it is not worthy as such cases are extremely
4295 || contains_deleted_insn_p (ira_reg_equiv
[i
].init_insns
)
4296 /* If it is not a reverse equivalence, we check that a
4297 pseudo in rhs of the init insn is not dying in the
4298 insn. Otherwise, the live info at the beginning of
4299 the corresponding BB might be wrong after we
4300 removed the insn. When the equiv can be a
4301 constant, the right hand side of the init insn can
4303 || (! reverse_equiv_p (i
)
4304 && (init_insn_rhs_dead_pseudo_p (i
)
4305 /* If we reloaded the pseudo in an equivalence
4306 init insn, we can not remove the equiv init
4307 insns and the init insns might write into
4308 const memory in this case. */
4309 || contains_reloaded_insn_p (i
)))
4310 /* Prevent access beyond equivalent memory for
4311 paradoxical subregs. */
4313 && (GET_MODE_SIZE (lra_reg_info
[i
].biggest_mode
)
4314 > GET_MODE_SIZE (GET_MODE (x
))))
4315 || (pic_offset_table_rtx
4316 && ((CONST_POOL_OK_P (PSEUDO_REGNO_MODE (i
), x
)
4317 && (targetm
.preferred_reload_class
4318 (x
, lra_get_allocno_class (i
)) == NO_REGS
))
4319 || contains_symbol_ref_p (x
))))
4320 ira_reg_equiv
[i
].defined_p
= false;
4321 if (contains_reg_p (x
, false, true))
4322 ira_reg_equiv
[i
].profitable_p
= false;
4323 if (get_equiv (reg
) != reg
)
4324 bitmap_ior_into (&equiv_insn_bitmap
, &lra_reg_info
[i
].insn_bitmap
);
4327 for (i
= FIRST_PSEUDO_REGISTER
; i
< new_regno_start
; i
++)
4329 /* We should add all insns containing pseudos which should be
4330 substituted by their equivalences. */
4331 EXECUTE_IF_SET_IN_BITMAP (&equiv_insn_bitmap
, 0, uid
, bi
)
4332 lra_push_insn_by_uid (uid
);
4333 min_len
= lra_insn_stack_length ();
4337 while ((new_min_len
= lra_insn_stack_length ()) != 0)
4339 curr_insn
= lra_pop_insn ();
4341 curr_bb
= BLOCK_FOR_INSN (curr_insn
);
4342 if (curr_bb
!= last_bb
)
4345 bb_reload_num
= lra_curr_reload_num
;
4347 if (min_len
> new_min_len
)
4349 min_len
= new_min_len
;
4352 if (new_insns_num
> MAX_RELOAD_INSNS_NUMBER
)
4354 ("Max. number of generated reload insns per insn is achieved (%d)\n",
4355 MAX_RELOAD_INSNS_NUMBER
);
4357 if (DEBUG_INSN_P (curr_insn
))
4359 /* We need to check equivalence in debug insn and change
4360 pseudo to the equivalent value if necessary. */
4361 curr_id
= lra_get_insn_recog_data (curr_insn
);
4362 if (bitmap_bit_p (&equiv_insn_bitmap
, INSN_UID (curr_insn
)))
4364 rtx old
= *curr_id
->operand_loc
[0];
4365 *curr_id
->operand_loc
[0]
4366 = simplify_replace_fn_rtx (old
, NULL_RTX
,
4367 loc_equivalence_callback
, curr_insn
);
4368 if (old
!= *curr_id
->operand_loc
[0])
4370 lra_update_insn_regno_info (curr_insn
);
4375 else if (INSN_P (curr_insn
))
4377 if ((set
= single_set (curr_insn
)) != NULL_RTX
)
4379 dest_reg
= SET_DEST (set
);
4380 /* The equivalence pseudo could be set up as SUBREG in a
4381 case when it is a call restore insn in a mode
4382 different from the pseudo mode. */
4383 if (GET_CODE (dest_reg
) == SUBREG
)
4384 dest_reg
= SUBREG_REG (dest_reg
);
4385 if ((REG_P (dest_reg
)
4386 && (x
= get_equiv (dest_reg
)) != dest_reg
4387 /* Remove insns which set up a pseudo whose value
4388 can not be changed. Such insns might be not in
4389 init_insns because we don't update equiv data
4390 during insn transformations.
4392 As an example, let suppose that a pseudo got
4393 hard register and on the 1st pass was not
4394 changed to equivalent constant. We generate an
4395 additional insn setting up the pseudo because of
4396 secondary memory movement. Then the pseudo is
4397 spilled and we use the equiv constant. In this
4398 case we should remove the additional insn and
4399 this insn is not init_insns list. */
4400 && (! MEM_P (x
) || MEM_READONLY_P (x
)
4401 /* Check that this is actually an insn setting
4402 up the equivalence. */
4403 || in_list_p (curr_insn
,
4405 [REGNO (dest_reg
)].init_insns
)))
4406 || (((x
= get_equiv (SET_SRC (set
))) != SET_SRC (set
))
4407 && in_list_p (curr_insn
,
4409 [REGNO (SET_SRC (set
))].init_insns
)))
4411 /* This is equiv init insn of pseudo which did not get a
4412 hard register -- remove the insn. */
4413 if (lra_dump_file
!= NULL
)
4415 fprintf (lra_dump_file
,
4416 " Removing equiv init insn %i (freq=%d)\n",
4417 INSN_UID (curr_insn
),
4418 REG_FREQ_FROM_BB (BLOCK_FOR_INSN (curr_insn
)));
4419 dump_insn_slim (lra_dump_file
, curr_insn
);
4421 if (contains_reg_p (x
, true, false))
4422 lra_risky_transformations_p
= true;
4423 lra_set_insn_deleted (curr_insn
);
4427 curr_id
= lra_get_insn_recog_data (curr_insn
);
4428 curr_static_id
= curr_id
->insn_static_data
;
4429 init_curr_insn_input_reloads ();
4430 init_curr_operand_mode ();
4431 if (curr_insn_transform (false))
4433 /* Check non-transformed insns too for equiv change as USE
4434 or CLOBBER don't need reloads but can contain pseudos
4435 being changed on their equivalences. */
4436 else if (bitmap_bit_p (&equiv_insn_bitmap
, INSN_UID (curr_insn
))
4437 && loc_equivalence_change_p (&PATTERN (curr_insn
)))
4439 lra_update_insn_regno_info (curr_insn
);
4444 bitmap_clear (&equiv_insn_bitmap
);
4445 /* If we used a new hard regno, changed_p should be true because the
4446 hard reg is assigned to a new pseudo. */
4447 #ifdef ENABLE_CHECKING
4450 for (i
= FIRST_PSEUDO_REGISTER
; i
< new_regno_start
; i
++)
4451 if (lra_reg_info
[i
].nrefs
!= 0
4452 && (hard_regno
= lra_get_regno_hard_regno (i
)) >= 0)
4454 int j
, nregs
= hard_regno_nregs
[hard_regno
][PSEUDO_REGNO_MODE (i
)];
4456 for (j
= 0; j
< nregs
; j
++)
4457 lra_assert (df_regs_ever_live_p (hard_regno
+ j
));
4464 /* Initiate the LRA constraint pass. It is done once per
4467 lra_constraints_init (void)
4471 /* Finalize the LRA constraint pass. It is done once per
4474 lra_constraints_finish (void)
4480 /* This page contains code to do inheritance/split
4483 /* Number of reloads passed so far in current EBB. */
4484 static int reloads_num
;
4486 /* Number of calls passed so far in current EBB. */
4487 static int calls_num
;
4489 /* Current reload pseudo check for validity of elements in
4491 static int curr_usage_insns_check
;
4493 /* Info about last usage of registers in EBB to do inheritance/split
4494 transformation. Inheritance transformation is done from a spilled
4495 pseudo and split transformations from a hard register or a pseudo
4496 assigned to a hard register. */
4499 /* If the value is equal to CURR_USAGE_INSNS_CHECK, then the member
4500 value INSNS is valid. The insns is chain of optional debug insns
4501 and a finishing non-debug insn using the corresponding reg. The
4502 value is also used to mark the registers which are set up in the
4503 current insn. The negated insn uid is used for this. */
4505 /* Value of global reloads_num at the last insn in INSNS. */
4507 /* Value of global reloads_nums at the last insn in INSNS. */
4509 /* It can be true only for splitting. And it means that the restore
4510 insn should be put after insn given by the following member. */
4512 /* Next insns in the current EBB which use the original reg and the
4513 original reg value is not changed between the current insn and
4514 the next insns. In order words, e.g. for inheritance, if we need
4515 to use the original reg value again in the next insns we can try
4516 to use the value in a hard register from a reload insn of the
4521 /* Map: regno -> corresponding pseudo usage insns. */
4522 static struct usage_insns
*usage_insns
;
4525 setup_next_usage_insn (int regno
, rtx insn
, int reloads_num
, bool after_p
)
4527 usage_insns
[regno
].check
= curr_usage_insns_check
;
4528 usage_insns
[regno
].insns
= insn
;
4529 usage_insns
[regno
].reloads_num
= reloads_num
;
4530 usage_insns
[regno
].calls_num
= calls_num
;
4531 usage_insns
[regno
].after_p
= after_p
;
4534 /* The function is used to form list REGNO usages which consists of
4535 optional debug insns finished by a non-debug insn using REGNO.
4536 RELOADS_NUM is current number of reload insns processed so far. */
4538 add_next_usage_insn (int regno
, rtx insn
, int reloads_num
)
4540 rtx next_usage_insns
;
4542 if (usage_insns
[regno
].check
== curr_usage_insns_check
4543 && (next_usage_insns
= usage_insns
[regno
].insns
) != NULL_RTX
4544 && DEBUG_INSN_P (insn
))
4546 /* Check that we did not add the debug insn yet. */
4547 if (next_usage_insns
!= insn
4548 && (GET_CODE (next_usage_insns
) != INSN_LIST
4549 || XEXP (next_usage_insns
, 0) != insn
))
4550 usage_insns
[regno
].insns
= gen_rtx_INSN_LIST (VOIDmode
, insn
,
4553 else if (NONDEBUG_INSN_P (insn
))
4554 setup_next_usage_insn (regno
, insn
, reloads_num
, false);
4556 usage_insns
[regno
].check
= 0;
4559 /* Return first non-debug insn in list USAGE_INSNS. */
4561 skip_usage_debug_insns (rtx usage_insns
)
4565 /* Skip debug insns. */
4566 for (insn
= usage_insns
;
4567 insn
!= NULL_RTX
&& GET_CODE (insn
) == INSN_LIST
;
4568 insn
= XEXP (insn
, 1))
4570 return safe_as_a
<rtx_insn
*> (insn
);
4573 /* Return true if we need secondary memory moves for insn in
4574 USAGE_INSNS after inserting inherited pseudo of class INHER_CL
4577 check_secondary_memory_needed_p (enum reg_class inher_cl ATTRIBUTE_UNUSED
,
4578 rtx usage_insns ATTRIBUTE_UNUSED
)
4580 #ifndef SECONDARY_MEMORY_NEEDED
4587 if (inher_cl
== ALL_REGS
4588 || (insn
= skip_usage_debug_insns (usage_insns
)) == NULL_RTX
)
4590 lra_assert (INSN_P (insn
));
4591 if ((set
= single_set (insn
)) == NULL_RTX
|| ! REG_P (SET_DEST (set
)))
4593 dest
= SET_DEST (set
);
4596 lra_assert (inher_cl
!= NO_REGS
);
4597 cl
= get_reg_class (REGNO (dest
));
4598 return (cl
!= NO_REGS
&& cl
!= ALL_REGS
4599 && SECONDARY_MEMORY_NEEDED (inher_cl
, cl
, GET_MODE (dest
)));
4603 /* Registers involved in inheritance/split in the current EBB
4604 (inheritance/split pseudos and original registers). */
4605 static bitmap_head check_only_regs
;
4607 /* Do inheritance transformations for insn INSN, which defines (if
4608 DEF_P) or uses ORIGINAL_REGNO. NEXT_USAGE_INSNS specifies which
4609 instruction in the EBB next uses ORIGINAL_REGNO; it has the same
4610 form as the "insns" field of usage_insns. Return true if we
4611 succeed in such transformation.
4613 The transformations look like:
4616 ... p <- i (new insn)
4618 <- ... p ... <- ... i ...
4620 ... i <- p (new insn)
4621 <- ... p ... <- ... i ...
4623 <- ... p ... <- ... i ...
4624 where p is a spilled original pseudo and i is a new inheritance pseudo.
4627 The inheritance pseudo has the smallest class of two classes CL and
4628 class of ORIGINAL REGNO. */
4630 inherit_reload_reg (bool def_p
, int original_regno
,
4631 enum reg_class cl
, rtx_insn
*insn
, rtx next_usage_insns
)
4633 if (optimize_function_for_size_p (cfun
))
4636 enum reg_class rclass
= lra_get_allocno_class (original_regno
);
4637 rtx original_reg
= regno_reg_rtx
[original_regno
];
4638 rtx new_reg
, usage_insn
;
4639 rtx_insn
*new_insns
;
4641 lra_assert (! usage_insns
[original_regno
].after_p
);
4642 if (lra_dump_file
!= NULL
)
4643 fprintf (lra_dump_file
,
4644 " <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<\n");
4645 if (! ira_reg_classes_intersect_p
[cl
][rclass
])
4647 if (lra_dump_file
!= NULL
)
4649 fprintf (lra_dump_file
,
4650 " Rejecting inheritance for %d "
4651 "because of disjoint classes %s and %s\n",
4652 original_regno
, reg_class_names
[cl
],
4653 reg_class_names
[rclass
]);
4654 fprintf (lra_dump_file
,
4655 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
4659 if ((ira_class_subset_p
[cl
][rclass
] && cl
!= rclass
)
4660 /* We don't use a subset of two classes because it can be
4661 NO_REGS. This transformation is still profitable in most
4662 cases even if the classes are not intersected as register
4663 move is probably cheaper than a memory load. */
4664 || ira_class_hard_regs_num
[cl
] < ira_class_hard_regs_num
[rclass
])
4666 if (lra_dump_file
!= NULL
)
4667 fprintf (lra_dump_file
, " Use smallest class of %s and %s\n",
4668 reg_class_names
[cl
], reg_class_names
[rclass
]);
4672 if (check_secondary_memory_needed_p (rclass
, next_usage_insns
))
4674 /* Reject inheritance resulting in secondary memory moves.
4675 Otherwise, there is a danger in LRA cycling. Also such
4676 transformation will be unprofitable. */
4677 if (lra_dump_file
!= NULL
)
4679 rtx_insn
*insn
= skip_usage_debug_insns (next_usage_insns
);
4680 rtx set
= single_set (insn
);
4682 lra_assert (set
!= NULL_RTX
);
4684 rtx dest
= SET_DEST (set
);
4686 lra_assert (REG_P (dest
));
4687 fprintf (lra_dump_file
,
4688 " Rejecting inheritance for insn %d(%s)<-%d(%s) "
4689 "as secondary mem is needed\n",
4690 REGNO (dest
), reg_class_names
[get_reg_class (REGNO (dest
))],
4691 original_regno
, reg_class_names
[rclass
]);
4692 fprintf (lra_dump_file
,
4693 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
4697 new_reg
= lra_create_new_reg (GET_MODE (original_reg
), original_reg
,
4698 rclass
, "inheritance");
4701 lra_emit_move (original_reg
, new_reg
);
4703 lra_emit_move (new_reg
, original_reg
);
4704 new_insns
= get_insns ();
4706 if (NEXT_INSN (new_insns
) != NULL_RTX
)
4708 if (lra_dump_file
!= NULL
)
4710 fprintf (lra_dump_file
,
4711 " Rejecting inheritance %d->%d "
4712 "as it results in 2 or more insns:\n",
4713 original_regno
, REGNO (new_reg
));
4714 dump_rtl_slim (lra_dump_file
, new_insns
, NULL
, -1, 0);
4715 fprintf (lra_dump_file
,
4716 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
4720 lra_substitute_pseudo_within_insn (insn
, original_regno
, new_reg
);
4721 lra_update_insn_regno_info (insn
);
4723 /* We now have a new usage insn for original regno. */
4724 setup_next_usage_insn (original_regno
, new_insns
, reloads_num
, false);
4725 if (lra_dump_file
!= NULL
)
4726 fprintf (lra_dump_file
, " Original reg change %d->%d (bb%d):\n",
4727 original_regno
, REGNO (new_reg
), BLOCK_FOR_INSN (insn
)->index
);
4728 lra_reg_info
[REGNO (new_reg
)].restore_regno
= original_regno
;
4729 bitmap_set_bit (&check_only_regs
, REGNO (new_reg
));
4730 bitmap_set_bit (&check_only_regs
, original_regno
);
4731 bitmap_set_bit (&lra_inheritance_pseudos
, REGNO (new_reg
));
4733 lra_process_new_insns (insn
, NULL
, new_insns
,
4734 "Add original<-inheritance");
4736 lra_process_new_insns (insn
, new_insns
, NULL
,
4737 "Add inheritance<-original");
4738 while (next_usage_insns
!= NULL_RTX
)
4740 if (GET_CODE (next_usage_insns
) != INSN_LIST
)
4742 usage_insn
= next_usage_insns
;
4743 lra_assert (NONDEBUG_INSN_P (usage_insn
));
4744 next_usage_insns
= NULL
;
4748 usage_insn
= XEXP (next_usage_insns
, 0);
4749 lra_assert (DEBUG_INSN_P (usage_insn
));
4750 next_usage_insns
= XEXP (next_usage_insns
, 1);
4752 lra_substitute_pseudo (&usage_insn
, original_regno
, new_reg
);
4753 lra_update_insn_regno_info (as_a
<rtx_insn
*> (usage_insn
));
4754 if (lra_dump_file
!= NULL
)
4756 fprintf (lra_dump_file
,
4757 " Inheritance reuse change %d->%d (bb%d):\n",
4758 original_regno
, REGNO (new_reg
),
4759 BLOCK_FOR_INSN (usage_insn
)->index
);
4760 dump_insn_slim (lra_dump_file
, as_a
<rtx_insn
*> (usage_insn
));
4763 if (lra_dump_file
!= NULL
)
4764 fprintf (lra_dump_file
,
4765 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
4769 /* Return true if we need a caller save/restore for pseudo REGNO which
4770 was assigned to a hard register. */
4772 need_for_call_save_p (int regno
)
4774 lra_assert (regno
>= FIRST_PSEUDO_REGISTER
&& reg_renumber
[regno
] >= 0);
4775 return (usage_insns
[regno
].calls_num
< calls_num
4776 && (overlaps_hard_reg_set_p
4778 ! hard_reg_set_empty_p (lra_reg_info
[regno
].actual_call_used_reg_set
))
4779 ? lra_reg_info
[regno
].actual_call_used_reg_set
4780 : call_used_reg_set
,
4781 PSEUDO_REGNO_MODE (regno
), reg_renumber
[regno
])
4782 || HARD_REGNO_CALL_PART_CLOBBERED (reg_renumber
[regno
],
4783 PSEUDO_REGNO_MODE (regno
))));
4786 /* Global registers occurring in the current EBB. */
4787 static bitmap_head ebb_global_regs
;
4789 /* Return true if we need a split for hard register REGNO or pseudo
4790 REGNO which was assigned to a hard register.
4791 POTENTIAL_RELOAD_HARD_REGS contains hard registers which might be
4792 used for reloads since the EBB end. It is an approximation of the
4793 used hard registers in the split range. The exact value would
4794 require expensive calculations. If we were aggressive with
4795 splitting because of the approximation, the split pseudo will save
4796 the same hard register assignment and will be removed in the undo
4797 pass. We still need the approximation because too aggressive
4798 splitting would result in too inaccurate cost calculation in the
4799 assignment pass because of too many generated moves which will be
4800 probably removed in the undo pass. */
4802 need_for_split_p (HARD_REG_SET potential_reload_hard_regs
, int regno
)
4804 int hard_regno
= regno
< FIRST_PSEUDO_REGISTER
? regno
: reg_renumber
[regno
];
4806 lra_assert (hard_regno
>= 0);
4807 return ((TEST_HARD_REG_BIT (potential_reload_hard_regs
, hard_regno
)
4808 /* Don't split eliminable hard registers, otherwise we can
4809 split hard registers like hard frame pointer, which
4810 lives on BB start/end according to DF-infrastructure,
4811 when there is a pseudo assigned to the register and
4812 living in the same BB. */
4813 && (regno
>= FIRST_PSEUDO_REGISTER
4814 || ! TEST_HARD_REG_BIT (eliminable_regset
, hard_regno
))
4815 && ! TEST_HARD_REG_BIT (lra_no_alloc_regs
, hard_regno
)
4816 /* Don't split call clobbered hard regs living through
4817 calls, otherwise we might have a check problem in the
4818 assign sub-pass as in the most cases (exception is a
4819 situation when lra_risky_transformations_p value is
4820 true) the assign pass assumes that all pseudos living
4821 through calls are assigned to call saved hard regs. */
4822 && (regno
>= FIRST_PSEUDO_REGISTER
4823 || ! TEST_HARD_REG_BIT (call_used_reg_set
, regno
)
4824 || usage_insns
[regno
].calls_num
== calls_num
)
4825 /* We need at least 2 reloads to make pseudo splitting
4826 profitable. We should provide hard regno splitting in
4827 any case to solve 1st insn scheduling problem when
4828 moving hard register definition up might result in
4829 impossibility to find hard register for reload pseudo of
4830 small register class. */
4831 && (usage_insns
[regno
].reloads_num
4832 + (regno
< FIRST_PSEUDO_REGISTER
? 0 : 3) < reloads_num
)
4833 && (regno
< FIRST_PSEUDO_REGISTER
4834 /* For short living pseudos, spilling + inheritance can
4835 be considered a substitution for splitting.
4836 Therefore we do not splitting for local pseudos. It
4837 decreases also aggressiveness of splitting. The
4838 minimal number of references is chosen taking into
4839 account that for 2 references splitting has no sense
4840 as we can just spill the pseudo. */
4841 || (regno
>= FIRST_PSEUDO_REGISTER
4842 && lra_reg_info
[regno
].nrefs
> 3
4843 && bitmap_bit_p (&ebb_global_regs
, regno
))))
4844 || (regno
>= FIRST_PSEUDO_REGISTER
&& need_for_call_save_p (regno
)));
4847 /* Return class for the split pseudo created from original pseudo with
4848 ALLOCNO_CLASS and MODE which got a hard register HARD_REGNO. We
4849 choose subclass of ALLOCNO_CLASS which contains HARD_REGNO and
4850 results in no secondary memory movements. */
4851 static enum reg_class
4852 choose_split_class (enum reg_class allocno_class
,
4853 int hard_regno ATTRIBUTE_UNUSED
,
4854 machine_mode mode ATTRIBUTE_UNUSED
)
4856 #ifndef SECONDARY_MEMORY_NEEDED
4857 return allocno_class
;
4860 enum reg_class cl
, best_cl
= NO_REGS
;
4861 enum reg_class hard_reg_class ATTRIBUTE_UNUSED
4862 = REGNO_REG_CLASS (hard_regno
);
4864 if (! SECONDARY_MEMORY_NEEDED (allocno_class
, allocno_class
, mode
)
4865 && TEST_HARD_REG_BIT (reg_class_contents
[allocno_class
], hard_regno
))
4866 return allocno_class
;
4868 (cl
= reg_class_subclasses
[allocno_class
][i
]) != LIM_REG_CLASSES
;
4870 if (! SECONDARY_MEMORY_NEEDED (cl
, hard_reg_class
, mode
)
4871 && ! SECONDARY_MEMORY_NEEDED (hard_reg_class
, cl
, mode
)
4872 && TEST_HARD_REG_BIT (reg_class_contents
[cl
], hard_regno
)
4873 && (best_cl
== NO_REGS
4874 || ira_class_hard_regs_num
[best_cl
] < ira_class_hard_regs_num
[cl
]))
4880 /* Do split transformations for insn INSN, which defines or uses
4881 ORIGINAL_REGNO. NEXT_USAGE_INSNS specifies which instruction in
4882 the EBB next uses ORIGINAL_REGNO; it has the same form as the
4883 "insns" field of usage_insns.
4885 The transformations look like:
4888 ... s <- p (new insn -- save)
4890 ... p <- s (new insn -- restore)
4891 <- ... p ... <- ... p ...
4893 <- ... p ... <- ... p ...
4894 ... s <- p (new insn -- save)
4896 ... p <- s (new insn -- restore)
4897 <- ... p ... <- ... p ...
4899 where p is an original pseudo got a hard register or a hard
4900 register and s is a new split pseudo. The save is put before INSN
4901 if BEFORE_P is true. Return true if we succeed in such
4904 split_reg (bool before_p
, int original_regno
, rtx_insn
*insn
,
4905 rtx next_usage_insns
)
4907 enum reg_class rclass
;
4909 int hard_regno
, nregs
;
4910 rtx new_reg
, usage_insn
;
4911 rtx_insn
*restore
, *save
;
4915 if (original_regno
< FIRST_PSEUDO_REGISTER
)
4917 rclass
= ira_allocno_class_translate
[REGNO_REG_CLASS (original_regno
)];
4918 hard_regno
= original_regno
;
4919 call_save_p
= false;
4924 hard_regno
= reg_renumber
[original_regno
];
4925 nregs
= hard_regno_nregs
[hard_regno
][PSEUDO_REGNO_MODE (original_regno
)];
4926 rclass
= lra_get_allocno_class (original_regno
);
4927 original_reg
= regno_reg_rtx
[original_regno
];
4928 call_save_p
= need_for_call_save_p (original_regno
);
4930 original_reg
= regno_reg_rtx
[original_regno
];
4931 lra_assert (hard_regno
>= 0);
4932 if (lra_dump_file
!= NULL
)
4933 fprintf (lra_dump_file
,
4934 " ((((((((((((((((((((((((((((((((((((((((((((((((\n");
4937 machine_mode mode
= GET_MODE (original_reg
);
4939 mode
= HARD_REGNO_CALLER_SAVE_MODE (hard_regno
,
4940 hard_regno_nregs
[hard_regno
][mode
],
4942 new_reg
= lra_create_new_reg (mode
, NULL_RTX
, NO_REGS
, "save");
4946 rclass
= choose_split_class (rclass
, hard_regno
,
4947 GET_MODE (original_reg
));
4948 if (rclass
== NO_REGS
)
4950 if (lra_dump_file
!= NULL
)
4952 fprintf (lra_dump_file
,
4953 " Rejecting split of %d(%s): "
4954 "no good reg class for %d(%s)\n",
4956 reg_class_names
[lra_get_allocno_class (original_regno
)],
4958 reg_class_names
[REGNO_REG_CLASS (hard_regno
)]);
4961 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
4965 new_reg
= lra_create_new_reg (GET_MODE (original_reg
), original_reg
,
4967 reg_renumber
[REGNO (new_reg
)] = hard_regno
;
4969 save
= emit_spill_move (true, new_reg
, original_reg
);
4970 if (NEXT_INSN (save
) != NULL_RTX
&& !call_save_p
)
4972 if (lra_dump_file
!= NULL
)
4976 " Rejecting split %d->%d resulting in > 2 save insns:\n",
4977 original_regno
, REGNO (new_reg
));
4978 dump_rtl_slim (lra_dump_file
, save
, NULL
, -1, 0);
4979 fprintf (lra_dump_file
,
4980 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
4984 restore
= emit_spill_move (false, new_reg
, original_reg
);
4985 if (NEXT_INSN (restore
) != NULL_RTX
&& !call_save_p
)
4987 if (lra_dump_file
!= NULL
)
4989 fprintf (lra_dump_file
,
4990 " Rejecting split %d->%d "
4991 "resulting in > 2 restore insns:\n",
4992 original_regno
, REGNO (new_reg
));
4993 dump_rtl_slim (lra_dump_file
, restore
, NULL
, -1, 0);
4994 fprintf (lra_dump_file
,
4995 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
4999 after_p
= usage_insns
[original_regno
].after_p
;
5000 lra_reg_info
[REGNO (new_reg
)].restore_regno
= original_regno
;
5001 bitmap_set_bit (&check_only_regs
, REGNO (new_reg
));
5002 bitmap_set_bit (&check_only_regs
, original_regno
);
5003 bitmap_set_bit (&lra_split_regs
, REGNO (new_reg
));
5006 if (GET_CODE (next_usage_insns
) != INSN_LIST
)
5008 usage_insn
= next_usage_insns
;
5011 usage_insn
= XEXP (next_usage_insns
, 0);
5012 lra_assert (DEBUG_INSN_P (usage_insn
));
5013 next_usage_insns
= XEXP (next_usage_insns
, 1);
5014 lra_substitute_pseudo (&usage_insn
, original_regno
, new_reg
);
5015 lra_update_insn_regno_info (as_a
<rtx_insn
*> (usage_insn
));
5016 if (lra_dump_file
!= NULL
)
5018 fprintf (lra_dump_file
, " Split reuse change %d->%d:\n",
5019 original_regno
, REGNO (new_reg
));
5020 dump_insn_slim (lra_dump_file
, as_a
<rtx_insn
*> (usage_insn
));
5023 lra_assert (NOTE_P (usage_insn
) || NONDEBUG_INSN_P (usage_insn
));
5024 lra_assert (usage_insn
!= insn
|| (after_p
&& before_p
));
5025 lra_process_new_insns (as_a
<rtx_insn
*> (usage_insn
),
5026 after_p
? NULL
: restore
,
5027 after_p
? restore
: NULL
,
5029 ? "Add reg<-save" : "Add reg<-split");
5030 lra_process_new_insns (insn
, before_p
? save
: NULL
,
5031 before_p
? NULL
: save
,
5033 ? "Add save<-reg" : "Add split<-reg");
5035 /* If we are trying to split multi-register. We should check
5036 conflicts on the next assignment sub-pass. IRA can allocate on
5037 sub-register levels, LRA do this on pseudos level right now and
5038 this discrepancy may create allocation conflicts after
5040 lra_risky_transformations_p
= true;
5041 if (lra_dump_file
!= NULL
)
5042 fprintf (lra_dump_file
,
5043 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
5047 /* Recognize that we need a split transformation for insn INSN, which
5048 defines or uses REGNO in its insn biggest MODE (we use it only if
5049 REGNO is a hard register). POTENTIAL_RELOAD_HARD_REGS contains
5050 hard registers which might be used for reloads since the EBB end.
5051 Put the save before INSN if BEFORE_P is true. MAX_UID is maximla
5052 uid before starting INSN processing. Return true if we succeed in
5053 such transformation. */
5055 split_if_necessary (int regno
, machine_mode mode
,
5056 HARD_REG_SET potential_reload_hard_regs
,
5057 bool before_p
, rtx_insn
*insn
, int max_uid
)
5061 rtx next_usage_insns
;
5063 if (regno
< FIRST_PSEUDO_REGISTER
)
5064 nregs
= hard_regno_nregs
[regno
][mode
];
5065 for (i
= 0; i
< nregs
; i
++)
5066 if (usage_insns
[regno
+ i
].check
== curr_usage_insns_check
5067 && (next_usage_insns
= usage_insns
[regno
+ i
].insns
) != NULL_RTX
5068 /* To avoid processing the register twice or more. */
5069 && ((GET_CODE (next_usage_insns
) != INSN_LIST
5070 && INSN_UID (next_usage_insns
) < max_uid
)
5071 || (GET_CODE (next_usage_insns
) == INSN_LIST
5072 && (INSN_UID (XEXP (next_usage_insns
, 0)) < max_uid
)))
5073 && need_for_split_p (potential_reload_hard_regs
, regno
+ i
)
5074 && split_reg (before_p
, regno
+ i
, insn
, next_usage_insns
))
5079 /* Check only registers living at the current program point in the
5081 static bitmap_head live_regs
;
5083 /* Update live info in EBB given by its HEAD and TAIL insns after
5084 inheritance/split transformation. The function removes dead moves
5087 update_ebb_live_info (rtx_insn
*head
, rtx_insn
*tail
)
5092 rtx_insn
*prev_insn
;
5095 basic_block last_bb
, prev_bb
, curr_bb
;
5097 struct lra_insn_reg
*reg
;
5101 last_bb
= BLOCK_FOR_INSN (tail
);
5103 for (curr_insn
= tail
;
5104 curr_insn
!= PREV_INSN (head
);
5105 curr_insn
= prev_insn
)
5107 prev_insn
= PREV_INSN (curr_insn
);
5108 /* We need to process empty blocks too. They contain
5109 NOTE_INSN_BASIC_BLOCK referring for the basic block. */
5110 if (NOTE_P (curr_insn
) && NOTE_KIND (curr_insn
) != NOTE_INSN_BASIC_BLOCK
)
5112 curr_bb
= BLOCK_FOR_INSN (curr_insn
);
5113 if (curr_bb
!= prev_bb
)
5115 if (prev_bb
!= NULL
)
5117 /* Update df_get_live_in (prev_bb): */
5118 EXECUTE_IF_SET_IN_BITMAP (&check_only_regs
, 0, j
, bi
)
5119 if (bitmap_bit_p (&live_regs
, j
))
5120 bitmap_set_bit (df_get_live_in (prev_bb
), j
);
5122 bitmap_clear_bit (df_get_live_in (prev_bb
), j
);
5124 if (curr_bb
!= last_bb
)
5126 /* Update df_get_live_out (curr_bb): */
5127 EXECUTE_IF_SET_IN_BITMAP (&check_only_regs
, 0, j
, bi
)
5129 live_p
= bitmap_bit_p (&live_regs
, j
);
5131 FOR_EACH_EDGE (e
, ei
, curr_bb
->succs
)
5132 if (bitmap_bit_p (df_get_live_in (e
->dest
), j
))
5138 bitmap_set_bit (df_get_live_out (curr_bb
), j
);
5140 bitmap_clear_bit (df_get_live_out (curr_bb
), j
);
5144 bitmap_and (&live_regs
, &check_only_regs
, df_get_live_out (curr_bb
));
5146 if (! NONDEBUG_INSN_P (curr_insn
))
5148 curr_id
= lra_get_insn_recog_data (curr_insn
);
5149 curr_static_id
= curr_id
->insn_static_data
;
5151 if ((set
= single_set (curr_insn
)) != NULL_RTX
&& REG_P (SET_DEST (set
))
5152 && (regno
= REGNO (SET_DEST (set
))) >= FIRST_PSEUDO_REGISTER
5153 && bitmap_bit_p (&check_only_regs
, regno
)
5154 && ! bitmap_bit_p (&live_regs
, regno
))
5156 /* See which defined values die here. */
5157 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
5158 if (reg
->type
== OP_OUT
&& ! reg
->subreg_p
)
5159 bitmap_clear_bit (&live_regs
, reg
->regno
);
5160 for (reg
= curr_static_id
->hard_regs
; reg
!= NULL
; reg
= reg
->next
)
5161 if (reg
->type
== OP_OUT
&& ! reg
->subreg_p
)
5162 bitmap_clear_bit (&live_regs
, reg
->regno
);
5163 /* Mark each used value as live. */
5164 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
5165 if (reg
->type
!= OP_OUT
5166 && bitmap_bit_p (&check_only_regs
, reg
->regno
))
5167 bitmap_set_bit (&live_regs
, reg
->regno
);
5168 for (reg
= curr_static_id
->hard_regs
; reg
!= NULL
; reg
= reg
->next
)
5169 if (reg
->type
!= OP_OUT
5170 && bitmap_bit_p (&check_only_regs
, reg
->regno
))
5171 bitmap_set_bit (&live_regs
, reg
->regno
);
5172 if (curr_id
->arg_hard_regs
!= NULL
)
5173 /* Make argument hard registers live. */
5174 for (i
= 0; (regno
= curr_id
->arg_hard_regs
[i
]) >= 0; i
++)
5175 if (bitmap_bit_p (&check_only_regs
, regno
))
5176 bitmap_set_bit (&live_regs
, regno
);
5177 /* It is quite important to remove dead move insns because it
5178 means removing dead store. We don't need to process them for
5182 if (lra_dump_file
!= NULL
)
5184 fprintf (lra_dump_file
, " Removing dead insn:\n ");
5185 dump_insn_slim (lra_dump_file
, curr_insn
);
5187 lra_set_insn_deleted (curr_insn
);
5192 /* The structure describes info to do an inheritance for the current
5193 insn. We need to collect such info first before doing the
5194 transformations because the transformations change the insn
5195 internal representation. */
5198 /* Original regno. */
5200 /* Subsequent insns which can inherit original reg value. */
5204 /* Array containing all info for doing inheritance from the current
5206 static struct to_inherit to_inherit
[LRA_MAX_INSN_RELOADS
];
5208 /* Number elements in the previous array. */
5209 static int to_inherit_num
;
5211 /* Add inheritance info REGNO and INSNS. Their meaning is described in
5212 structure to_inherit. */
5214 add_to_inherit (int regno
, rtx insns
)
5218 for (i
= 0; i
< to_inherit_num
; i
++)
5219 if (to_inherit
[i
].regno
== regno
)
5221 lra_assert (to_inherit_num
< LRA_MAX_INSN_RELOADS
);
5222 to_inherit
[to_inherit_num
].regno
= regno
;
5223 to_inherit
[to_inherit_num
++].insns
= insns
;
5226 /* Return the last non-debug insn in basic block BB, or the block begin
5229 get_last_insertion_point (basic_block bb
)
5233 FOR_BB_INSNS_REVERSE (bb
, insn
)
5234 if (NONDEBUG_INSN_P (insn
) || NOTE_INSN_BASIC_BLOCK_P (insn
))
5239 /* Set up RES by registers living on edges FROM except the edge (FROM,
5240 TO) or by registers set up in a jump insn in BB FROM. */
5242 get_live_on_other_edges (basic_block from
, basic_block to
, bitmap res
)
5245 struct lra_insn_reg
*reg
;
5249 lra_assert (to
!= NULL
);
5251 FOR_EACH_EDGE (e
, ei
, from
->succs
)
5253 bitmap_ior_into (res
, df_get_live_in (e
->dest
));
5254 last
= get_last_insertion_point (from
);
5255 if (! JUMP_P (last
))
5257 curr_id
= lra_get_insn_recog_data (last
);
5258 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
5259 if (reg
->type
!= OP_IN
)
5260 bitmap_set_bit (res
, reg
->regno
);
5263 /* Used as a temporary results of some bitmap calculations. */
5264 static bitmap_head temp_bitmap
;
5266 /* We split for reloads of small class of hard regs. The following
5267 defines how many hard regs the class should have to be qualified as
5268 small. The code is mostly oriented to x86/x86-64 architecture
5269 where some insns need to use only specific register or pair of
5270 registers and these register can live in RTL explicitly, e.g. for
5271 parameter passing. */
5272 static const int max_small_class_regs_num
= 2;
5274 /* Do inheritance/split transformations in EBB starting with HEAD and
5275 finishing on TAIL. We process EBB insns in the reverse order.
5276 Return true if we did any inheritance/split transformation in the
5279 We should avoid excessive splitting which results in worse code
5280 because of inaccurate cost calculations for spilling new split
5281 pseudos in such case. To achieve this we do splitting only if
5282 register pressure is high in given basic block and there are reload
5283 pseudos requiring hard registers. We could do more register
5284 pressure calculations at any given program point to avoid necessary
5285 splitting even more but it is to expensive and the current approach
5286 works well enough. */
5288 inherit_in_ebb (rtx_insn
*head
, rtx_insn
*tail
)
5290 int i
, src_regno
, dst_regno
, nregs
;
5291 bool change_p
, succ_p
, update_reloads_num_p
;
5292 rtx_insn
*prev_insn
, *last_insn
;
5293 rtx next_usage_insns
, set
;
5295 struct lra_insn_reg
*reg
;
5296 basic_block last_processed_bb
, curr_bb
= NULL
;
5297 HARD_REG_SET potential_reload_hard_regs
, live_hard_regs
;
5301 bool head_p
, after_p
;
5304 curr_usage_insns_check
++;
5305 reloads_num
= calls_num
= 0;
5306 bitmap_clear (&check_only_regs
);
5307 last_processed_bb
= NULL
;
5308 CLEAR_HARD_REG_SET (potential_reload_hard_regs
);
5309 COPY_HARD_REG_SET (live_hard_regs
, eliminable_regset
);
5310 IOR_HARD_REG_SET (live_hard_regs
, lra_no_alloc_regs
);
5311 /* We don't process new insns generated in the loop. */
5312 for (curr_insn
= tail
; curr_insn
!= PREV_INSN (head
); curr_insn
= prev_insn
)
5314 prev_insn
= PREV_INSN (curr_insn
);
5315 if (BLOCK_FOR_INSN (curr_insn
) != NULL
)
5316 curr_bb
= BLOCK_FOR_INSN (curr_insn
);
5317 if (last_processed_bb
!= curr_bb
)
5319 /* We are at the end of BB. Add qualified living
5320 pseudos for potential splitting. */
5321 to_process
= df_get_live_out (curr_bb
);
5322 if (last_processed_bb
!= NULL
)
5324 /* We are somewhere in the middle of EBB. */
5325 get_live_on_other_edges (curr_bb
, last_processed_bb
,
5327 to_process
= &temp_bitmap
;
5329 last_processed_bb
= curr_bb
;
5330 last_insn
= get_last_insertion_point (curr_bb
);
5331 after_p
= (! JUMP_P (last_insn
)
5332 && (! CALL_P (last_insn
)
5333 || (find_reg_note (last_insn
,
5334 REG_NORETURN
, NULL_RTX
) == NULL_RTX
5335 && ! SIBLING_CALL_P (last_insn
))));
5336 CLEAR_HARD_REG_SET (potential_reload_hard_regs
);
5337 EXECUTE_IF_SET_IN_BITMAP (to_process
, 0, j
, bi
)
5339 if ((int) j
>= lra_constraint_new_regno_start
)
5341 if (j
< FIRST_PSEUDO_REGISTER
|| reg_renumber
[j
] >= 0)
5343 if (j
< FIRST_PSEUDO_REGISTER
)
5344 SET_HARD_REG_BIT (live_hard_regs
, j
);
5346 add_to_hard_reg_set (&live_hard_regs
,
5347 PSEUDO_REGNO_MODE (j
),
5349 setup_next_usage_insn (j
, last_insn
, reloads_num
, after_p
);
5353 src_regno
= dst_regno
= -1;
5354 if (NONDEBUG_INSN_P (curr_insn
)
5355 && (set
= single_set (curr_insn
)) != NULL_RTX
5356 && REG_P (SET_DEST (set
)) && REG_P (SET_SRC (set
)))
5358 src_regno
= REGNO (SET_SRC (set
));
5359 dst_regno
= REGNO (SET_DEST (set
));
5361 update_reloads_num_p
= true;
5362 if (src_regno
< lra_constraint_new_regno_start
5363 && src_regno
>= FIRST_PSEUDO_REGISTER
5364 && reg_renumber
[src_regno
] < 0
5365 && dst_regno
>= lra_constraint_new_regno_start
5366 && (cl
= lra_get_allocno_class (dst_regno
)) != NO_REGS
)
5368 /* 'reload_pseudo <- original_pseudo'. */
5369 if (ira_class_hard_regs_num
[cl
] <= max_small_class_regs_num
)
5371 update_reloads_num_p
= false;
5373 if (usage_insns
[src_regno
].check
== curr_usage_insns_check
5374 && (next_usage_insns
= usage_insns
[src_regno
].insns
) != NULL_RTX
)
5375 succ_p
= inherit_reload_reg (false, src_regno
, cl
,
5376 curr_insn
, next_usage_insns
);
5380 setup_next_usage_insn (src_regno
, curr_insn
, reloads_num
, false);
5381 if (hard_reg_set_subset_p (reg_class_contents
[cl
], live_hard_regs
))
5382 IOR_HARD_REG_SET (potential_reload_hard_regs
,
5383 reg_class_contents
[cl
]);
5385 else if (src_regno
>= lra_constraint_new_regno_start
5386 && dst_regno
< lra_constraint_new_regno_start
5387 && dst_regno
>= FIRST_PSEUDO_REGISTER
5388 && reg_renumber
[dst_regno
] < 0
5389 && (cl
= lra_get_allocno_class (src_regno
)) != NO_REGS
5390 && usage_insns
[dst_regno
].check
== curr_usage_insns_check
5391 && (next_usage_insns
5392 = usage_insns
[dst_regno
].insns
) != NULL_RTX
)
5394 if (ira_class_hard_regs_num
[cl
] <= max_small_class_regs_num
)
5396 update_reloads_num_p
= false;
5397 /* 'original_pseudo <- reload_pseudo'. */
5398 if (! JUMP_P (curr_insn
)
5399 && inherit_reload_reg (true, dst_regno
, cl
,
5400 curr_insn
, next_usage_insns
))
5403 usage_insns
[dst_regno
].check
= 0;
5404 if (hard_reg_set_subset_p (reg_class_contents
[cl
], live_hard_regs
))
5405 IOR_HARD_REG_SET (potential_reload_hard_regs
,
5406 reg_class_contents
[cl
]);
5408 else if (INSN_P (curr_insn
))
5411 int max_uid
= get_max_uid ();
5413 curr_id
= lra_get_insn_recog_data (curr_insn
);
5414 curr_static_id
= curr_id
->insn_static_data
;
5416 /* Process insn definitions. */
5417 for (iter
= 0; iter
< 2; iter
++)
5418 for (reg
= iter
== 0 ? curr_id
->regs
: curr_static_id
->hard_regs
;
5421 if (reg
->type
!= OP_IN
5422 && (dst_regno
= reg
->regno
) < lra_constraint_new_regno_start
)
5424 if (dst_regno
>= FIRST_PSEUDO_REGISTER
&& reg
->type
== OP_OUT
5425 && reg_renumber
[dst_regno
] < 0 && ! reg
->subreg_p
5426 && usage_insns
[dst_regno
].check
== curr_usage_insns_check
5427 && (next_usage_insns
5428 = usage_insns
[dst_regno
].insns
) != NULL_RTX
)
5430 struct lra_insn_reg
*r
;
5432 for (r
= curr_id
->regs
; r
!= NULL
; r
= r
->next
)
5433 if (r
->type
!= OP_OUT
&& r
->regno
== dst_regno
)
5435 /* Don't do inheritance if the pseudo is also
5436 used in the insn. */
5438 /* We can not do inheritance right now
5439 because the current insn reg info (chain
5440 regs) can change after that. */
5441 add_to_inherit (dst_regno
, next_usage_insns
);
5443 /* We can not process one reg twice here because of
5444 usage_insns invalidation. */
5445 if ((dst_regno
< FIRST_PSEUDO_REGISTER
5446 || reg_renumber
[dst_regno
] >= 0)
5447 && ! reg
->subreg_p
&& reg
->type
!= OP_IN
)
5451 if (split_if_necessary (dst_regno
, reg
->biggest_mode
,
5452 potential_reload_hard_regs
,
5453 false, curr_insn
, max_uid
))
5455 CLEAR_HARD_REG_SET (s
);
5456 if (dst_regno
< FIRST_PSEUDO_REGISTER
)
5457 add_to_hard_reg_set (&s
, reg
->biggest_mode
, dst_regno
);
5459 add_to_hard_reg_set (&s
, PSEUDO_REGNO_MODE (dst_regno
),
5460 reg_renumber
[dst_regno
]);
5461 AND_COMPL_HARD_REG_SET (live_hard_regs
, s
);
5463 /* We should invalidate potential inheritance or
5464 splitting for the current insn usages to the next
5465 usage insns (see code below) as the output pseudo
5467 if ((dst_regno
>= FIRST_PSEUDO_REGISTER
5468 && reg_renumber
[dst_regno
] < 0)
5469 || (reg
->type
== OP_OUT
&& ! reg
->subreg_p
5470 && (dst_regno
< FIRST_PSEUDO_REGISTER
5471 || reg_renumber
[dst_regno
] >= 0)))
5473 /* Invalidate and mark definitions. */
5474 if (dst_regno
>= FIRST_PSEUDO_REGISTER
)
5475 usage_insns
[dst_regno
].check
= -(int) INSN_UID (curr_insn
);
5478 nregs
= hard_regno_nregs
[dst_regno
][reg
->biggest_mode
];
5479 for (i
= 0; i
< nregs
; i
++)
5480 usage_insns
[dst_regno
+ i
].check
5481 = -(int) INSN_UID (curr_insn
);
5485 if (! JUMP_P (curr_insn
))
5486 for (i
= 0; i
< to_inherit_num
; i
++)
5487 if (inherit_reload_reg (true, to_inherit
[i
].regno
,
5488 ALL_REGS
, curr_insn
,
5489 to_inherit
[i
].insns
))
5491 if (CALL_P (curr_insn
))
5493 rtx cheap
, pat
, dest
;
5495 int regno
, hard_regno
;
5498 if ((cheap
= find_reg_note (curr_insn
,
5499 REG_RETURNED
, NULL_RTX
)) != NULL_RTX
5500 && ((cheap
= XEXP (cheap
, 0)), true)
5501 && (regno
= REGNO (cheap
)) >= FIRST_PSEUDO_REGISTER
5502 && (hard_regno
= reg_renumber
[regno
]) >= 0
5503 /* If there are pending saves/restores, the
5504 optimization is not worth. */
5505 && usage_insns
[regno
].calls_num
== calls_num
- 1
5506 && TEST_HARD_REG_BIT (call_used_reg_set
, hard_regno
))
5508 /* Restore the pseudo from the call result as
5509 REG_RETURNED note says that the pseudo value is
5510 in the call result and the pseudo is an argument
5512 pat
= PATTERN (curr_insn
);
5513 if (GET_CODE (pat
) == PARALLEL
)
5514 pat
= XVECEXP (pat
, 0, 0);
5515 dest
= SET_DEST (pat
);
5516 /* For multiple return values dest is PARALLEL.
5517 Currently we handle only single return value case. */
5521 emit_move_insn (cheap
, copy_rtx (dest
));
5522 restore
= get_insns ();
5524 lra_process_new_insns (curr_insn
, NULL
, restore
,
5525 "Inserting call parameter restore");
5526 /* We don't need to save/restore of the pseudo from
5528 usage_insns
[regno
].calls_num
= calls_num
;
5529 bitmap_set_bit (&check_only_regs
, regno
);
5534 /* Process insn usages. */
5535 for (iter
= 0; iter
< 2; iter
++)
5536 for (reg
= iter
== 0 ? curr_id
->regs
: curr_static_id
->hard_regs
;
5539 if ((reg
->type
!= OP_OUT
5540 || (reg
->type
== OP_OUT
&& reg
->subreg_p
))
5541 && (src_regno
= reg
->regno
) < lra_constraint_new_regno_start
)
5543 if (src_regno
>= FIRST_PSEUDO_REGISTER
5544 && reg_renumber
[src_regno
] < 0 && reg
->type
== OP_IN
)
5546 if (usage_insns
[src_regno
].check
== curr_usage_insns_check
5547 && (next_usage_insns
5548 = usage_insns
[src_regno
].insns
) != NULL_RTX
5549 && NONDEBUG_INSN_P (curr_insn
))
5550 add_to_inherit (src_regno
, next_usage_insns
);
5551 else if (usage_insns
[src_regno
].check
5552 != -(int) INSN_UID (curr_insn
))
5553 /* Add usages but only if the reg is not set up
5554 in the same insn. */
5555 add_next_usage_insn (src_regno
, curr_insn
, reloads_num
);
5557 else if (src_regno
< FIRST_PSEUDO_REGISTER
5558 || reg_renumber
[src_regno
] >= 0)
5561 rtx use_insn
= curr_insn
;
5563 before_p
= (JUMP_P (curr_insn
)
5564 || (CALL_P (curr_insn
) && reg
->type
== OP_IN
));
5565 if (NONDEBUG_INSN_P (curr_insn
)
5566 && (! JUMP_P (curr_insn
) || reg
->type
== OP_IN
)
5567 && split_if_necessary (src_regno
, reg
->biggest_mode
,
5568 potential_reload_hard_regs
,
5569 before_p
, curr_insn
, max_uid
))
5572 lra_risky_transformations_p
= true;
5575 usage_insns
[src_regno
].check
= 0;
5577 use_insn
= PREV_INSN (curr_insn
);
5579 if (NONDEBUG_INSN_P (curr_insn
))
5581 if (src_regno
< FIRST_PSEUDO_REGISTER
)
5582 add_to_hard_reg_set (&live_hard_regs
,
5583 reg
->biggest_mode
, src_regno
);
5585 add_to_hard_reg_set (&live_hard_regs
,
5586 PSEUDO_REGNO_MODE (src_regno
),
5587 reg_renumber
[src_regno
]);
5589 add_next_usage_insn (src_regno
, use_insn
, reloads_num
);
5592 /* Process call args. */
5593 if (curr_id
->arg_hard_regs
!= NULL
)
5594 for (i
= 0; (src_regno
= curr_id
->arg_hard_regs
[i
]) >= 0; i
++)
5595 if (src_regno
< FIRST_PSEUDO_REGISTER
)
5597 SET_HARD_REG_BIT (live_hard_regs
, src_regno
);
5598 add_next_usage_insn (src_regno
, curr_insn
, reloads_num
);
5600 for (i
= 0; i
< to_inherit_num
; i
++)
5602 src_regno
= to_inherit
[i
].regno
;
5603 if (inherit_reload_reg (false, src_regno
, ALL_REGS
,
5604 curr_insn
, to_inherit
[i
].insns
))
5607 setup_next_usage_insn (src_regno
, curr_insn
, reloads_num
, false);
5610 if (update_reloads_num_p
5611 && NONDEBUG_INSN_P (curr_insn
)
5612 && (set
= single_set (curr_insn
)) != NULL_RTX
)
5615 if ((REG_P (SET_DEST (set
))
5616 && (regno
= REGNO (SET_DEST (set
))) >= lra_constraint_new_regno_start
5617 && reg_renumber
[regno
] < 0
5618 && (cl
= lra_get_allocno_class (regno
)) != NO_REGS
)
5619 || (REG_P (SET_SRC (set
))
5620 && (regno
= REGNO (SET_SRC (set
))) >= lra_constraint_new_regno_start
5621 && reg_renumber
[regno
] < 0
5622 && (cl
= lra_get_allocno_class (regno
)) != NO_REGS
))
5624 if (ira_class_hard_regs_num
[cl
] <= max_small_class_regs_num
)
5626 if (hard_reg_set_subset_p (reg_class_contents
[cl
], live_hard_regs
))
5627 IOR_HARD_REG_SET (potential_reload_hard_regs
,
5628 reg_class_contents
[cl
]);
5631 /* We reached the start of the current basic block. */
5632 if (prev_insn
== NULL_RTX
|| prev_insn
== PREV_INSN (head
)
5633 || BLOCK_FOR_INSN (prev_insn
) != curr_bb
)
5635 /* We reached the beginning of the current block -- do
5636 rest of spliting in the current BB. */
5637 to_process
= df_get_live_in (curr_bb
);
5638 if (BLOCK_FOR_INSN (head
) != curr_bb
)
5640 /* We are somewhere in the middle of EBB. */
5641 get_live_on_other_edges (EDGE_PRED (curr_bb
, 0)->src
,
5642 curr_bb
, &temp_bitmap
);
5643 to_process
= &temp_bitmap
;
5646 EXECUTE_IF_SET_IN_BITMAP (to_process
, 0, j
, bi
)
5648 if ((int) j
>= lra_constraint_new_regno_start
)
5650 if (((int) j
< FIRST_PSEUDO_REGISTER
|| reg_renumber
[j
] >= 0)
5651 && usage_insns
[j
].check
== curr_usage_insns_check
5652 && (next_usage_insns
= usage_insns
[j
].insns
) != NULL_RTX
)
5654 if (need_for_split_p (potential_reload_hard_regs
, j
))
5656 if (lra_dump_file
!= NULL
&& head_p
)
5658 fprintf (lra_dump_file
,
5659 " ----------------------------------\n");
5662 if (split_reg (false, j
, bb_note (curr_bb
),
5666 usage_insns
[j
].check
= 0;
5674 /* This value affects EBB forming. If probability of edge from EBB to
5675 a BB is not greater than the following value, we don't add the BB
5677 #define EBB_PROBABILITY_CUTOFF \
5678 ((REG_BR_PROB_BASE * LRA_INHERITANCE_EBB_PROBABILITY_CUTOFF) / 100)
5680 /* Current number of inheritance/split iteration. */
5681 int lra_inheritance_iter
;
5683 /* Entry function for inheritance/split pass. */
5685 lra_inheritance (void)
5688 basic_block bb
, start_bb
;
5691 lra_inheritance_iter
++;
5692 if (lra_inheritance_iter
> LRA_MAX_INHERITANCE_PASSES
)
5694 timevar_push (TV_LRA_INHERITANCE
);
5695 if (lra_dump_file
!= NULL
)
5696 fprintf (lra_dump_file
, "\n********** Inheritance #%d: **********\n\n",
5697 lra_inheritance_iter
);
5698 curr_usage_insns_check
= 0;
5699 usage_insns
= XNEWVEC (struct usage_insns
, lra_constraint_new_regno_start
);
5700 for (i
= 0; i
< lra_constraint_new_regno_start
; i
++)
5701 usage_insns
[i
].check
= 0;
5702 bitmap_initialize (&check_only_regs
, ®_obstack
);
5703 bitmap_initialize (&live_regs
, ®_obstack
);
5704 bitmap_initialize (&temp_bitmap
, ®_obstack
);
5705 bitmap_initialize (&ebb_global_regs
, ®_obstack
);
5706 FOR_EACH_BB_FN (bb
, cfun
)
5709 if (lra_dump_file
!= NULL
)
5710 fprintf (lra_dump_file
, "EBB");
5711 /* Form a EBB starting with BB. */
5712 bitmap_clear (&ebb_global_regs
);
5713 bitmap_ior_into (&ebb_global_regs
, df_get_live_in (bb
));
5716 if (lra_dump_file
!= NULL
)
5717 fprintf (lra_dump_file
, " %d", bb
->index
);
5718 if (bb
->next_bb
== EXIT_BLOCK_PTR_FOR_FN (cfun
)
5719 || LABEL_P (BB_HEAD (bb
->next_bb
)))
5721 e
= find_fallthru_edge (bb
->succs
);
5724 if (e
->probability
< EBB_PROBABILITY_CUTOFF
)
5728 bitmap_ior_into (&ebb_global_regs
, df_get_live_out (bb
));
5729 if (lra_dump_file
!= NULL
)
5730 fprintf (lra_dump_file
, "\n");
5731 if (inherit_in_ebb (BB_HEAD (start_bb
), BB_END (bb
)))
5732 /* Remember that the EBB head and tail can change in
5734 update_ebb_live_info (BB_HEAD (start_bb
), BB_END (bb
));
5736 bitmap_clear (&ebb_global_regs
);
5737 bitmap_clear (&temp_bitmap
);
5738 bitmap_clear (&live_regs
);
5739 bitmap_clear (&check_only_regs
);
5742 timevar_pop (TV_LRA_INHERITANCE
);
5747 /* This page contains code to undo failed inheritance/split
5750 /* Current number of iteration undoing inheritance/split. */
5751 int lra_undo_inheritance_iter
;
5753 /* Fix BB live info LIVE after removing pseudos created on pass doing
5754 inheritance/split which are REMOVED_PSEUDOS. */
5756 fix_bb_live_info (bitmap live
, bitmap removed_pseudos
)
5761 EXECUTE_IF_SET_IN_BITMAP (removed_pseudos
, 0, regno
, bi
)
5762 if (bitmap_clear_bit (live
, regno
))
5763 bitmap_set_bit (live
, lra_reg_info
[regno
].restore_regno
);
5766 /* Return regno of the (subreg of) REG. Otherwise, return a negative
5771 if (GET_CODE (reg
) == SUBREG
)
5772 reg
= SUBREG_REG (reg
);
5778 /* Remove inheritance/split pseudos which are in REMOVE_PSEUDOS and
5779 return true if we did any change. The undo transformations for
5780 inheritance looks like
5784 p <- i, i <- p, and i <- i3
5785 where p is original pseudo from which inheritance pseudo i was
5786 created, i and i3 are removed inheritance pseudos, i2 is another
5787 not removed inheritance pseudo. All split pseudos or other
5788 occurrences of removed inheritance pseudos are changed on the
5789 corresponding original pseudos.
5791 The function also schedules insns changed and created during
5792 inheritance/split pass for processing by the subsequent constraint
5795 remove_inheritance_pseudos (bitmap remove_pseudos
)
5798 int regno
, sregno
, prev_sregno
, dregno
, restore_regno
;
5800 rtx_insn
*prev_insn
;
5801 bool change_p
, done_p
;
5803 change_p
= ! bitmap_empty_p (remove_pseudos
);
5804 /* We can not finish the function right away if CHANGE_P is true
5805 because we need to marks insns affected by previous
5806 inheritance/split pass for processing by the subsequent
5808 FOR_EACH_BB_FN (bb
, cfun
)
5810 fix_bb_live_info (df_get_live_in (bb
), remove_pseudos
);
5811 fix_bb_live_info (df_get_live_out (bb
), remove_pseudos
);
5812 FOR_BB_INSNS_REVERSE (bb
, curr_insn
)
5814 if (! INSN_P (curr_insn
))
5817 sregno
= dregno
= -1;
5818 if (change_p
&& NONDEBUG_INSN_P (curr_insn
)
5819 && (set
= single_set (curr_insn
)) != NULL_RTX
)
5821 dregno
= get_regno (SET_DEST (set
));
5822 sregno
= get_regno (SET_SRC (set
));
5825 if (sregno
>= 0 && dregno
>= 0)
5827 if ((bitmap_bit_p (remove_pseudos
, sregno
)
5828 && (lra_reg_info
[sregno
].restore_regno
== dregno
5829 || (bitmap_bit_p (remove_pseudos
, dregno
)
5830 && (lra_reg_info
[sregno
].restore_regno
5831 == lra_reg_info
[dregno
].restore_regno
))))
5832 || (bitmap_bit_p (remove_pseudos
, dregno
)
5833 && lra_reg_info
[dregno
].restore_regno
== sregno
))
5834 /* One of the following cases:
5835 original <- removed inheritance pseudo
5836 removed inherit pseudo <- another removed inherit pseudo
5837 removed inherit pseudo <- original pseudo
5839 removed_split_pseudo <- original_reg
5840 original_reg <- removed_split_pseudo */
5842 if (lra_dump_file
!= NULL
)
5844 fprintf (lra_dump_file
, " Removing %s:\n",
5845 bitmap_bit_p (&lra_split_regs
, sregno
)
5846 || bitmap_bit_p (&lra_split_regs
, dregno
)
5847 ? "split" : "inheritance");
5848 dump_insn_slim (lra_dump_file
, curr_insn
);
5850 lra_set_insn_deleted (curr_insn
);
5853 else if (bitmap_bit_p (remove_pseudos
, sregno
)
5854 && bitmap_bit_p (&lra_inheritance_pseudos
, sregno
))
5856 /* Search the following pattern:
5857 inherit_or_split_pseudo1 <- inherit_or_split_pseudo2
5858 original_pseudo <- inherit_or_split_pseudo1
5859 where the 2nd insn is the current insn and
5860 inherit_or_split_pseudo2 is not removed. If it is found,
5861 change the current insn onto:
5862 original_pseudo <- inherit_or_split_pseudo2. */
5863 for (prev_insn
= PREV_INSN (curr_insn
);
5864 prev_insn
!= NULL_RTX
&& ! NONDEBUG_INSN_P (prev_insn
);
5865 prev_insn
= PREV_INSN (prev_insn
))
5867 if (prev_insn
!= NULL_RTX
&& BLOCK_FOR_INSN (prev_insn
) == bb
5868 && (prev_set
= single_set (prev_insn
)) != NULL_RTX
5869 /* There should be no subregs in insn we are
5870 searching because only the original reg might
5871 be in subreg when we changed the mode of
5872 load/store for splitting. */
5873 && REG_P (SET_DEST (prev_set
))
5874 && REG_P (SET_SRC (prev_set
))
5875 && (int) REGNO (SET_DEST (prev_set
)) == sregno
5876 && ((prev_sregno
= REGNO (SET_SRC (prev_set
)))
5877 >= FIRST_PSEUDO_REGISTER
)
5878 /* As we consider chain of inheritance or
5879 splitting described in above comment we should
5880 check that sregno and prev_sregno were
5881 inheritance/split pseudos created from the
5882 same original regno. */
5883 && (lra_reg_info
[sregno
].restore_regno
5884 == lra_reg_info
[prev_sregno
].restore_regno
)
5885 && ! bitmap_bit_p (remove_pseudos
, prev_sregno
))
5887 lra_assert (GET_MODE (SET_SRC (prev_set
))
5888 == GET_MODE (regno_reg_rtx
[sregno
]));
5889 if (GET_CODE (SET_SRC (set
)) == SUBREG
)
5890 SUBREG_REG (SET_SRC (set
)) = SET_SRC (prev_set
);
5892 SET_SRC (set
) = SET_SRC (prev_set
);
5893 /* As we are finishing with processing the insn
5894 here, check the destination too as it might
5895 inheritance pseudo for another pseudo. */
5896 if (bitmap_bit_p (remove_pseudos
, dregno
)
5897 && bitmap_bit_p (&lra_inheritance_pseudos
, dregno
)
5899 = lra_reg_info
[dregno
].restore_regno
) >= 0)
5901 if (GET_CODE (SET_DEST (set
)) == SUBREG
)
5902 SUBREG_REG (SET_DEST (set
))
5903 = regno_reg_rtx
[restore_regno
];
5905 SET_DEST (set
) = regno_reg_rtx
[restore_regno
];
5907 lra_push_insn_and_update_insn_regno_info (curr_insn
);
5908 lra_set_used_insn_alternative_by_uid
5909 (INSN_UID (curr_insn
), -1);
5911 if (lra_dump_file
!= NULL
)
5913 fprintf (lra_dump_file
, " Change reload insn:\n");
5914 dump_insn_slim (lra_dump_file
, curr_insn
);
5921 struct lra_insn_reg
*reg
;
5922 bool restored_regs_p
= false;
5923 bool kept_regs_p
= false;
5925 curr_id
= lra_get_insn_recog_data (curr_insn
);
5926 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
5929 restore_regno
= lra_reg_info
[regno
].restore_regno
;
5930 if (restore_regno
>= 0)
5932 if (change_p
&& bitmap_bit_p (remove_pseudos
, regno
))
5934 lra_substitute_pseudo_within_insn (
5935 curr_insn
, regno
, regno_reg_rtx
[restore_regno
]);
5936 restored_regs_p
= true;
5942 if (NONDEBUG_INSN_P (curr_insn
) && kept_regs_p
)
5944 /* The instruction has changed since the previous
5945 constraints pass. */
5946 lra_push_insn_and_update_insn_regno_info (curr_insn
);
5947 lra_set_used_insn_alternative_by_uid
5948 (INSN_UID (curr_insn
), -1);
5950 else if (restored_regs_p
)
5951 /* The instruction has been restored to the form that
5952 it had during the previous constraints pass. */
5953 lra_update_insn_regno_info (curr_insn
);
5954 if (restored_regs_p
&& lra_dump_file
!= NULL
)
5956 fprintf (lra_dump_file
, " Insn after restoring regs:\n");
5957 dump_insn_slim (lra_dump_file
, curr_insn
);
5965 /* If optional reload pseudos failed to get a hard register or was not
5966 inherited, it is better to remove optional reloads. We do this
5967 transformation after undoing inheritance to figure out necessity to
5968 remove optional reloads easier. Return true if we do any
5971 undo_optional_reloads (void)
5973 bool change_p
, keep_p
;
5974 unsigned int regno
, uid
;
5975 bitmap_iterator bi
, bi2
;
5978 bitmap_head removed_optional_reload_pseudos
, insn_bitmap
;
5980 bitmap_initialize (&removed_optional_reload_pseudos
, ®_obstack
);
5981 bitmap_copy (&removed_optional_reload_pseudos
, &lra_optional_reload_pseudos
);
5982 EXECUTE_IF_SET_IN_BITMAP (&lra_optional_reload_pseudos
, 0, regno
, bi
)
5985 /* Keep optional reloads from previous subpasses. */
5986 if (lra_reg_info
[regno
].restore_regno
< 0
5987 /* If the original pseudo changed its allocation, just
5988 removing the optional pseudo is dangerous as the original
5989 pseudo will have longer live range. */
5990 || reg_renumber
[lra_reg_info
[regno
].restore_regno
] >= 0)
5992 else if (reg_renumber
[regno
] >= 0)
5993 EXECUTE_IF_SET_IN_BITMAP (&lra_reg_info
[regno
].insn_bitmap
, 0, uid
, bi2
)
5995 insn
= lra_insn_recog_data
[uid
]->insn
;
5996 if ((set
= single_set (insn
)) == NULL_RTX
)
5998 src
= SET_SRC (set
);
5999 dest
= SET_DEST (set
);
6000 if (! REG_P (src
) || ! REG_P (dest
))
6002 if (REGNO (dest
) == regno
6003 /* Ignore insn for optional reloads itself. */
6004 && lra_reg_info
[regno
].restore_regno
!= (int) REGNO (src
)
6005 /* Check only inheritance on last inheritance pass. */
6006 && (int) REGNO (src
) >= new_regno_start
6007 /* Check that the optional reload was inherited. */
6008 && bitmap_bit_p (&lra_inheritance_pseudos
, REGNO (src
)))
6016 bitmap_clear_bit (&removed_optional_reload_pseudos
, regno
);
6017 if (lra_dump_file
!= NULL
)
6018 fprintf (lra_dump_file
, "Keep optional reload reg %d\n", regno
);
6021 change_p
= ! bitmap_empty_p (&removed_optional_reload_pseudos
);
6022 bitmap_initialize (&insn_bitmap
, ®_obstack
);
6023 EXECUTE_IF_SET_IN_BITMAP (&removed_optional_reload_pseudos
, 0, regno
, bi
)
6025 if (lra_dump_file
!= NULL
)
6026 fprintf (lra_dump_file
, "Remove optional reload reg %d\n", regno
);
6027 bitmap_copy (&insn_bitmap
, &lra_reg_info
[regno
].insn_bitmap
);
6028 EXECUTE_IF_SET_IN_BITMAP (&insn_bitmap
, 0, uid
, bi2
)
6030 insn
= lra_insn_recog_data
[uid
]->insn
;
6031 if ((set
= single_set (insn
)) != NULL_RTX
)
6033 src
= SET_SRC (set
);
6034 dest
= SET_DEST (set
);
6035 if (REG_P (src
) && REG_P (dest
)
6036 && ((REGNO (src
) == regno
6037 && (lra_reg_info
[regno
].restore_regno
6038 == (int) REGNO (dest
)))
6039 || (REGNO (dest
) == regno
6040 && (lra_reg_info
[regno
].restore_regno
6041 == (int) REGNO (src
)))))
6043 if (lra_dump_file
!= NULL
)
6045 fprintf (lra_dump_file
, " Deleting move %u\n",
6047 dump_insn_slim (lra_dump_file
, insn
);
6049 lra_set_insn_deleted (insn
);
6052 /* We should not worry about generation memory-memory
6053 moves here as if the corresponding inheritance did
6054 not work (inheritance pseudo did not get a hard reg),
6055 we remove the inheritance pseudo and the optional
6058 lra_substitute_pseudo_within_insn (
6060 regno_reg_rtx
[lra_reg_info
[regno
].restore_regno
]);
6061 lra_update_insn_regno_info (insn
);
6062 if (lra_dump_file
!= NULL
)
6064 fprintf (lra_dump_file
,
6065 " Restoring original insn:\n");
6066 dump_insn_slim (lra_dump_file
, insn
);
6070 /* Clear restore_regnos. */
6071 EXECUTE_IF_SET_IN_BITMAP (&lra_optional_reload_pseudos
, 0, regno
, bi
)
6072 lra_reg_info
[regno
].restore_regno
= -1;
6073 bitmap_clear (&insn_bitmap
);
6074 bitmap_clear (&removed_optional_reload_pseudos
);
6078 /* Entry function for undoing inheritance/split transformation. Return true
6079 if we did any RTL change in this pass. */
6081 lra_undo_inheritance (void)
6084 int restore_regno
, hard_regno
;
6085 int n_all_inherit
, n_inherit
, n_all_split
, n_split
;
6086 bitmap_head remove_pseudos
;
6090 lra_undo_inheritance_iter
++;
6091 if (lra_undo_inheritance_iter
> LRA_MAX_INHERITANCE_PASSES
)
6093 if (lra_dump_file
!= NULL
)
6094 fprintf (lra_dump_file
,
6095 "\n********** Undoing inheritance #%d: **********\n\n",
6096 lra_undo_inheritance_iter
);
6097 bitmap_initialize (&remove_pseudos
, ®_obstack
);
6098 n_inherit
= n_all_inherit
= 0;
6099 EXECUTE_IF_SET_IN_BITMAP (&lra_inheritance_pseudos
, 0, regno
, bi
)
6100 if (lra_reg_info
[regno
].restore_regno
>= 0)
6103 if (reg_renumber
[regno
] < 0
6104 /* If the original pseudo changed its allocation, just
6105 removing inheritance is dangerous as for changing
6106 allocation we used shorter live-ranges. */
6107 && reg_renumber
[lra_reg_info
[regno
].restore_regno
] < 0)
6108 bitmap_set_bit (&remove_pseudos
, regno
);
6112 if (lra_dump_file
!= NULL
&& n_all_inherit
!= 0)
6113 fprintf (lra_dump_file
, "Inherit %d out of %d (%.2f%%)\n",
6114 n_inherit
, n_all_inherit
,
6115 (double) n_inherit
/ n_all_inherit
* 100);
6116 n_split
= n_all_split
= 0;
6117 EXECUTE_IF_SET_IN_BITMAP (&lra_split_regs
, 0, regno
, bi
)
6118 if ((restore_regno
= lra_reg_info
[regno
].restore_regno
) >= 0)
6121 hard_regno
= (restore_regno
>= FIRST_PSEUDO_REGISTER
6122 ? reg_renumber
[restore_regno
] : restore_regno
);
6123 if (hard_regno
< 0 || reg_renumber
[regno
] == hard_regno
)
6124 bitmap_set_bit (&remove_pseudos
, regno
);
6128 if (lra_dump_file
!= NULL
)
6129 fprintf (lra_dump_file
, " Keep split r%d (orig=r%d)\n",
6130 regno
, restore_regno
);
6133 if (lra_dump_file
!= NULL
&& n_all_split
!= 0)
6134 fprintf (lra_dump_file
, "Split %d out of %d (%.2f%%)\n",
6135 n_split
, n_all_split
,
6136 (double) n_split
/ n_all_split
* 100);
6137 change_p
= remove_inheritance_pseudos (&remove_pseudos
);
6138 bitmap_clear (&remove_pseudos
);
6139 /* Clear restore_regnos. */
6140 EXECUTE_IF_SET_IN_BITMAP (&lra_inheritance_pseudos
, 0, regno
, bi
)
6141 lra_reg_info
[regno
].restore_regno
= -1;
6142 EXECUTE_IF_SET_IN_BITMAP (&lra_split_regs
, 0, regno
, bi
)
6143 lra_reg_info
[regno
].restore_regno
= -1;
6144 change_p
= undo_optional_reloads () || change_p
;