1 /* Code for RTL transformations to satisfy insn constraints.
2 Copyright (C) 2010-2013 Free Software Foundation, Inc.
3 Contributed by Vladimir Makarov <vmakarov@redhat.com>.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 3, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
22 /* This file contains code for 3 passes: constraint pass,
23 inheritance/split pass, and pass for undoing failed inheritance and
26 The major goal of constraint pass is to transform RTL to satisfy
27 insn and address constraints by:
28 o choosing insn alternatives;
29 o generating *reload insns* (or reloads in brief) and *reload
30 pseudos* which will get necessary hard registers later;
31 o substituting pseudos with equivalent values and removing the
32 instructions that initialized those pseudos.
34 The constraint pass has biggest and most complicated code in LRA.
35 There are a lot of important details like:
36 o reuse of input reload pseudos to simplify reload pseudo
38 o some heuristics to choose insn alternative to improve the
42 The pass is mimicking former reload pass in alternative choosing
43 because the reload pass is oriented to current machine description
44 model. It might be changed if the machine description model is
47 There is special code for preventing all LRA and this pass cycling
50 On the first iteration of the pass we process every instruction and
51 choose an alternative for each one. On subsequent iterations we try
52 to avoid reprocessing instructions if we can be sure that the old
53 choice is still valid.
55 The inheritance/spilt pass is to transform code to achieve
56 ineheritance and live range splitting. It is done on backward
59 The inheritance optimization goal is to reuse values in hard
60 registers. There is analogous optimization in old reload pass. The
61 inheritance is achieved by following transformation:
63 reload_p1 <- p reload_p1 <- p
64 ... new_p <- reload_p1
66 reload_p2 <- p reload_p2 <- new_p
68 where p is spilled and not changed between the insns. Reload_p1 is
69 also called *original pseudo* and new_p is called *inheritance
72 The subsequent assignment pass will try to assign the same (or
73 another if it is not possible) hard register to new_p as to
74 reload_p1 or reload_p2.
76 If the assignment pass fails to assign a hard register to new_p,
77 this file will undo the inheritance and restore the original code.
78 This is because implementing the above sequence with a spilled
79 new_p would make the code much worse. The inheritance is done in
80 EBB scope. The above is just a simplified example to get an idea
81 of the inheritance as the inheritance is also done for non-reload
84 Splitting (transformation) is also done in EBB scope on the same
85 pass as the inheritance:
87 r <- ... or ... <- r r <- ... or ... <- r
88 ... s <- r (new insn -- save)
90 ... r <- s (new insn -- restore)
93 The *split pseudo* s is assigned to the hard register of the
94 original pseudo or hard register r.
97 o In EBBs with high register pressure for global pseudos (living
98 in at least 2 BBs) and assigned to hard registers when there
99 are more one reloads needing the hard registers;
100 o for pseudos needing save/restore code around calls.
102 If the split pseudo still has the same hard register as the
103 original pseudo after the subsequent assignment pass or the
104 original pseudo was split, the opposite transformation is done on
105 the same pass for undoing inheritance. */
111 #include "coretypes.h"
113 #include "hard-reg-set.h"
117 #include "insn-config.h"
118 #include "insn-codes.h"
121 #include "addresses.h"
123 #include "function.h"
125 #include "basic-block.h"
130 #include "rtl-error.h"
133 /* Value of LRA_CURR_RELOAD_NUM at the beginning of BB of the current
134 insn. Remember that LRA_CURR_RELOAD_NUM is the number of emitted
136 static int bb_reload_num
;
138 /* The current insn being processed and corresponding its single set
139 (NULL otherwise), its data (basic block, the insn data, the insn
140 static data, and the mode of each operand). */
141 static rtx curr_insn
;
142 static rtx curr_insn_set
;
143 static basic_block curr_bb
;
144 static lra_insn_recog_data_t curr_id
;
145 static struct lra_static_insn_data
*curr_static_id
;
146 static enum machine_mode curr_operand_mode
[MAX_RECOG_OPERANDS
];
150 /* Start numbers for new registers and insns at the current constraints
152 static int new_regno_start
;
153 static int new_insn_uid_start
;
155 /* If LOC is nonnull, strip any outer subreg from it. */
157 strip_subreg (rtx
*loc
)
159 return loc
&& GET_CODE (*loc
) == SUBREG
? &SUBREG_REG (*loc
) : loc
;
162 /* Return hard regno of REGNO or if it is was not assigned to a hard
163 register, use a hard register from its allocno class. */
165 get_try_hard_regno (int regno
)
168 enum reg_class rclass
;
170 if ((hard_regno
= regno
) >= FIRST_PSEUDO_REGISTER
)
171 hard_regno
= lra_get_regno_hard_regno (regno
);
174 rclass
= lra_get_allocno_class (regno
);
175 if (rclass
== NO_REGS
)
177 return ira_class_hard_regs
[rclass
][0];
180 /* Return final hard regno (plus offset) which will be after
181 elimination. We do this for matching constraints because the final
182 hard regno could have a different class. */
184 get_final_hard_regno (int hard_regno
, int offset
)
188 hard_regno
= lra_get_elimination_hard_regno (hard_regno
);
189 return hard_regno
+ offset
;
192 /* Return hard regno of X after removing subreg and making
193 elimination. If X is not a register or subreg of register, return
194 -1. For pseudo use its assignment. */
196 get_hard_regno (rtx x
)
199 int offset
, hard_regno
;
202 if (GET_CODE (x
) == SUBREG
)
203 reg
= SUBREG_REG (x
);
206 if ((hard_regno
= REGNO (reg
)) >= FIRST_PSEUDO_REGISTER
)
207 hard_regno
= lra_get_regno_hard_regno (hard_regno
);
211 if (GET_CODE (x
) == SUBREG
)
212 offset
+= subreg_regno_offset (hard_regno
, GET_MODE (reg
),
213 SUBREG_BYTE (x
), GET_MODE (x
));
214 return get_final_hard_regno (hard_regno
, offset
);
217 /* If REGNO is a hard register or has been allocated a hard register,
218 return the class of that register. If REGNO is a reload pseudo
219 created by the current constraints pass, return its allocno class.
220 Return NO_REGS otherwise. */
221 static enum reg_class
222 get_reg_class (int regno
)
226 if ((hard_regno
= regno
) >= FIRST_PSEUDO_REGISTER
)
227 hard_regno
= lra_get_regno_hard_regno (regno
);
230 hard_regno
= get_final_hard_regno (hard_regno
, 0);
231 return REGNO_REG_CLASS (hard_regno
);
233 if (regno
>= new_regno_start
)
234 return lra_get_allocno_class (regno
);
238 /* Return true if REG satisfies (or will satisfy) reg class constraint
239 CL. Use elimination first if REG is a hard register. If REG is a
240 reload pseudo created by this constraints pass, assume that it will
241 be allocated a hard register from its allocno class, but allow that
242 class to be narrowed to CL if it is currently a superset of CL.
244 If NEW_CLASS is nonnull, set *NEW_CLASS to the new allocno class of
245 REGNO (reg), or NO_REGS if no change in its class was needed. */
247 in_class_p (rtx reg
, enum reg_class cl
, enum reg_class
*new_class
)
249 enum reg_class rclass
, common_class
;
250 enum machine_mode reg_mode
;
251 int class_size
, hard_regno
, nregs
, i
, j
;
252 int regno
= REGNO (reg
);
254 if (new_class
!= NULL
)
255 *new_class
= NO_REGS
;
256 if (regno
< FIRST_PSEUDO_REGISTER
)
259 rtx
*final_loc
= &final_reg
;
261 lra_eliminate_reg_if_possible (final_loc
);
262 return TEST_HARD_REG_BIT (reg_class_contents
[cl
], REGNO (*final_loc
));
264 reg_mode
= GET_MODE (reg
);
265 rclass
= get_reg_class (regno
);
266 if (regno
< new_regno_start
267 /* Do not allow the constraints for reload instructions to
268 influence the classes of new pseudos. These reloads are
269 typically moves that have many alternatives, and restricting
270 reload pseudos for one alternative may lead to situations
271 where other reload pseudos are no longer allocatable. */
272 || INSN_UID (curr_insn
) >= new_insn_uid_start
)
273 /* When we don't know what class will be used finally for reload
274 pseudos, we use ALL_REGS. */
275 return ((regno
>= new_regno_start
&& rclass
== ALL_REGS
)
276 || (rclass
!= NO_REGS
&& ira_class_subset_p
[rclass
][cl
]
277 && ! hard_reg_set_subset_p (reg_class_contents
[cl
],
278 lra_no_alloc_regs
)));
281 common_class
= ira_reg_class_subset
[rclass
][cl
];
282 if (new_class
!= NULL
)
283 *new_class
= common_class
;
284 if (hard_reg_set_subset_p (reg_class_contents
[common_class
],
287 /* Check that there are enough allocatable regs. */
288 class_size
= ira_class_hard_regs_num
[common_class
];
289 for (i
= 0; i
< class_size
; i
++)
291 hard_regno
= ira_class_hard_regs
[common_class
][i
];
292 nregs
= hard_regno_nregs
[hard_regno
][reg_mode
];
295 for (j
= 0; j
< nregs
; j
++)
296 if (TEST_HARD_REG_BIT (lra_no_alloc_regs
, hard_regno
+ j
)
297 || ! TEST_HARD_REG_BIT (reg_class_contents
[common_class
],
307 /* Return true if REGNO satisfies a memory constraint. */
311 return get_reg_class (regno
) == NO_REGS
;
314 /* If we have decided to substitute X with another value, return that
315 value, otherwise return X. */
317 get_equiv_substitution (rtx x
)
322 if (! REG_P (x
) || (regno
= REGNO (x
)) < FIRST_PSEUDO_REGISTER
323 || ! ira_reg_equiv
[regno
].defined_p
324 || ! ira_reg_equiv
[regno
].profitable_p
325 || lra_get_regno_hard_regno (regno
) >= 0)
327 if ((res
= ira_reg_equiv
[regno
].memory
) != NULL_RTX
)
329 if ((res
= ira_reg_equiv
[regno
].constant
) != NULL_RTX
)
331 if ((res
= ira_reg_equiv
[regno
].invariant
) != NULL_RTX
)
336 /* Set up curr_operand_mode. */
338 init_curr_operand_mode (void)
340 int nop
= curr_static_id
->n_operands
;
341 for (int i
= 0; i
< nop
; i
++)
343 enum machine_mode mode
= GET_MODE (*curr_id
->operand_loc
[i
]);
344 if (mode
== VOIDmode
)
346 /* The .md mode for address operands is the mode of the
347 addressed value rather than the mode of the address itself. */
348 if (curr_id
->icode
>= 0 && curr_static_id
->operand
[i
].is_address
)
351 mode
= curr_static_id
->operand
[i
].mode
;
353 curr_operand_mode
[i
] = mode
;
359 /* The page contains code to reuse input reloads. */
361 /* Structure describes input reload of the current insns. */
364 /* Reloaded value. */
366 /* Reload pseudo used. */
370 /* The number of elements in the following array. */
371 static int curr_insn_input_reloads_num
;
372 /* Array containing info about input reloads. It is used to find the
373 same input reload and reuse the reload pseudo in this case. */
374 static struct input_reload curr_insn_input_reloads
[LRA_MAX_INSN_RELOADS
];
376 /* Initiate data concerning reuse of input reloads for the current
379 init_curr_insn_input_reloads (void)
381 curr_insn_input_reloads_num
= 0;
384 /* Change class of pseudo REGNO to NEW_CLASS. Print info about it
385 using TITLE. Output a new line if NL_P. */
387 change_class (int regno
, enum reg_class new_class
,
388 const char *title
, bool nl_p
)
390 lra_assert (regno
>= FIRST_PSEUDO_REGISTER
);
391 if (lra_dump_file
!= NULL
)
392 fprintf (lra_dump_file
, "%s to class %s for r%d",
393 title
, reg_class_names
[new_class
], regno
);
394 setup_reg_classes (regno
, new_class
, NO_REGS
, new_class
);
395 if (lra_dump_file
!= NULL
&& nl_p
)
396 fprintf (lra_dump_file
, "\n");
399 /* Create a new pseudo using MODE, RCLASS, ORIGINAL or reuse already
400 created input reload pseudo (only if TYPE is not OP_OUT). The
401 result pseudo is returned through RESULT_REG. Return TRUE if we
402 created a new pseudo, FALSE if we reused the already created input
403 reload pseudo. Use TITLE to describe new registers for debug
406 get_reload_reg (enum op_type type
, enum machine_mode mode
, rtx original
,
407 enum reg_class rclass
, const char *title
, rtx
*result_reg
)
410 enum reg_class new_class
;
415 = lra_create_new_reg_with_unique_value (mode
, original
, rclass
, title
);
418 /* Prevent reuse value of expression with side effects,
419 e.g. volatile memory. */
420 if (! side_effects_p (original
))
421 for (i
= 0; i
< curr_insn_input_reloads_num
; i
++)
422 if (rtx_equal_p (curr_insn_input_reloads
[i
].input
, original
)
423 && in_class_p (curr_insn_input_reloads
[i
].reg
, rclass
, &new_class
))
425 rtx reg
= curr_insn_input_reloads
[i
].reg
;
427 /* If input is equal to original and both are VOIDmode,
428 GET_MODE (reg) might be still different from mode.
429 Ensure we don't return *result_reg with wrong mode. */
430 if (GET_MODE (reg
) != mode
)
432 if (GET_MODE_SIZE (GET_MODE (reg
)) < GET_MODE_SIZE (mode
))
434 reg
= lowpart_subreg (mode
, reg
, GET_MODE (reg
));
435 if (reg
== NULL_RTX
|| GET_CODE (reg
) != SUBREG
)
439 if (lra_dump_file
!= NULL
)
441 fprintf (lra_dump_file
, " Reuse r%d for reload ", regno
);
442 dump_value_slim (lra_dump_file
, original
, 1);
444 if (new_class
!= lra_get_allocno_class (regno
))
445 change_class (regno
, new_class
, ", change", false);
446 if (lra_dump_file
!= NULL
)
447 fprintf (lra_dump_file
, "\n");
450 *result_reg
= lra_create_new_reg (mode
, original
, rclass
, title
);
451 lra_assert (curr_insn_input_reloads_num
< LRA_MAX_INSN_RELOADS
);
452 curr_insn_input_reloads
[curr_insn_input_reloads_num
].input
= original
;
453 curr_insn_input_reloads
[curr_insn_input_reloads_num
++].reg
= *result_reg
;
459 /* The page contains code to extract memory address parts. */
461 /* Wrapper around REGNO_OK_FOR_INDEX_P, to allow pseudos. */
463 ok_for_index_p_nonstrict (rtx reg
)
465 unsigned regno
= REGNO (reg
);
467 return regno
>= FIRST_PSEUDO_REGISTER
|| REGNO_OK_FOR_INDEX_P (regno
);
470 /* A version of regno_ok_for_base_p for use here, when all pseudos
471 should count as OK. Arguments as for regno_ok_for_base_p. */
473 ok_for_base_p_nonstrict (rtx reg
, enum machine_mode mode
, addr_space_t as
,
474 enum rtx_code outer_code
, enum rtx_code index_code
)
476 unsigned regno
= REGNO (reg
);
478 if (regno
>= FIRST_PSEUDO_REGISTER
)
480 return ok_for_base_p_1 (regno
, mode
, as
, outer_code
, index_code
);
485 /* The page contains major code to choose the current insn alternative
486 and generate reloads for it. */
488 /* Return the offset from REGNO of the least significant register
491 This function is used to tell whether two registers satisfy
492 a matching constraint. (reg:MODE1 REGNO1) matches (reg:MODE2 REGNO2) if:
494 REGNO1 + lra_constraint_offset (REGNO1, MODE1)
495 == REGNO2 + lra_constraint_offset (REGNO2, MODE2) */
497 lra_constraint_offset (int regno
, enum machine_mode mode
)
499 lra_assert (regno
< FIRST_PSEUDO_REGISTER
);
500 if (WORDS_BIG_ENDIAN
&& GET_MODE_SIZE (mode
) > UNITS_PER_WORD
501 && SCALAR_INT_MODE_P (mode
))
502 return hard_regno_nregs
[regno
][mode
] - 1;
506 /* Like rtx_equal_p except that it allows a REG and a SUBREG to match
507 if they are the same hard reg, and has special hacks for
508 auto-increment and auto-decrement. This is specifically intended for
509 process_alt_operands to use in determining whether two operands
510 match. X is the operand whose number is the lower of the two.
512 It is supposed that X is the output operand and Y is the input
513 operand. Y_HARD_REGNO is the final hard regno of register Y or
514 register in subreg Y as we know it now. Otherwise, it is a
517 operands_match_p (rtx x
, rtx y
, int y_hard_regno
)
520 RTX_CODE code
= GET_CODE (x
);
525 if ((code
== REG
|| (code
== SUBREG
&& REG_P (SUBREG_REG (x
))))
526 && (REG_P (y
) || (GET_CODE (y
) == SUBREG
&& REG_P (SUBREG_REG (y
)))))
530 i
= get_hard_regno (x
);
534 if ((j
= y_hard_regno
) < 0)
537 i
+= lra_constraint_offset (i
, GET_MODE (x
));
538 j
+= lra_constraint_offset (j
, GET_MODE (y
));
543 /* If two operands must match, because they are really a single
544 operand of an assembler insn, then two post-increments are invalid
545 because the assembler insn would increment only once. On the
546 other hand, a post-increment matches ordinary indexing if the
547 post-increment is the output operand. */
548 if (code
== POST_DEC
|| code
== POST_INC
|| code
== POST_MODIFY
)
549 return operands_match_p (XEXP (x
, 0), y
, y_hard_regno
);
551 /* Two pre-increments are invalid because the assembler insn would
552 increment only once. On the other hand, a pre-increment matches
553 ordinary indexing if the pre-increment is the input operand. */
554 if (GET_CODE (y
) == PRE_DEC
|| GET_CODE (y
) == PRE_INC
555 || GET_CODE (y
) == PRE_MODIFY
)
556 return operands_match_p (x
, XEXP (y
, 0), -1);
560 if (code
== REG
&& GET_CODE (y
) == SUBREG
&& REG_P (SUBREG_REG (y
))
561 && x
== SUBREG_REG (y
))
563 if (GET_CODE (y
) == REG
&& code
== SUBREG
&& REG_P (SUBREG_REG (x
))
564 && SUBREG_REG (x
) == y
)
567 /* Now we have disposed of all the cases in which different rtx
569 if (code
!= GET_CODE (y
))
572 /* (MULT:SI x y) and (MULT:HI x y) are NOT equivalent. */
573 if (GET_MODE (x
) != GET_MODE (y
))
582 return XEXP (x
, 0) == XEXP (y
, 0);
584 return XSTR (x
, 0) == XSTR (y
, 0);
590 /* Compare the elements. If any pair of corresponding elements fail
591 to match, return false for the whole things. */
593 fmt
= GET_RTX_FORMAT (code
);
594 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
600 if (XWINT (x
, i
) != XWINT (y
, i
))
605 if (XINT (x
, i
) != XINT (y
, i
))
610 val
= operands_match_p (XEXP (x
, i
), XEXP (y
, i
), -1);
619 if (XVECLEN (x
, i
) != XVECLEN (y
, i
))
621 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; --j
)
623 val
= operands_match_p (XVECEXP (x
, i
, j
), XVECEXP (y
, i
, j
), -1);
629 /* It is believed that rtx's at this level will never
630 contain anything but integers and other rtx's, except for
631 within LABEL_REFs and SYMBOL_REFs. */
639 /* True if X is a constant that can be forced into the constant pool.
640 MODE is the mode of the operand, or VOIDmode if not known. */
641 #define CONST_POOL_OK_P(MODE, X) \
642 ((MODE) != VOIDmode \
644 && GET_CODE (X) != HIGH \
645 && !targetm.cannot_force_const_mem (MODE, X))
647 /* True if C is a non-empty register class that has too few registers
648 to be safely used as a reload target class. */
649 #define SMALL_REGISTER_CLASS_P(C) \
650 (reg_class_size [(C)] == 1 \
651 || (reg_class_size [(C)] >= 1 && targetm.class_likely_spilled_p (C)))
653 /* If REG is a reload pseudo, try to make its class satisfying CL. */
655 narrow_reload_pseudo_class (rtx reg
, enum reg_class cl
)
657 enum reg_class rclass
;
659 /* Do not make more accurate class from reloads generated. They are
660 mostly moves with a lot of constraints. Making more accurate
661 class may results in very narrow class and impossibility of find
662 registers for several reloads of one insn. */
663 if (INSN_UID (curr_insn
) >= new_insn_uid_start
)
665 if (GET_CODE (reg
) == SUBREG
)
666 reg
= SUBREG_REG (reg
);
667 if (! REG_P (reg
) || (int) REGNO (reg
) < new_regno_start
)
669 if (in_class_p (reg
, cl
, &rclass
) && rclass
!= cl
)
670 change_class (REGNO (reg
), rclass
, " Change", true);
673 /* Generate reloads for matching OUT and INS (array of input operand
674 numbers with end marker -1) with reg class GOAL_CLASS. Add input
675 and output reloads correspondingly to the lists *BEFORE and *AFTER.
676 OUT might be negative. In this case we generate input reloads for
677 matched input operands INS. */
679 match_reload (signed char out
, signed char *ins
, enum reg_class goal_class
,
680 rtx
*before
, rtx
*after
)
683 rtx new_in_reg
, new_out_reg
, reg
, clobber
;
684 enum machine_mode inmode
, outmode
;
685 rtx in_rtx
= *curr_id
->operand_loc
[ins
[0]];
686 rtx out_rtx
= out
< 0 ? in_rtx
: *curr_id
->operand_loc
[out
];
688 inmode
= curr_operand_mode
[ins
[0]];
689 outmode
= out
< 0 ? inmode
: curr_operand_mode
[out
];
690 push_to_sequence (*before
);
691 if (inmode
!= outmode
)
693 if (GET_MODE_SIZE (inmode
) > GET_MODE_SIZE (outmode
))
696 = lra_create_new_reg_with_unique_value (inmode
, in_rtx
,
698 if (SCALAR_INT_MODE_P (inmode
))
699 new_out_reg
= gen_lowpart_SUBREG (outmode
, reg
);
701 new_out_reg
= gen_rtx_SUBREG (outmode
, reg
, 0);
702 LRA_SUBREG_P (new_out_reg
) = 1;
703 /* If the input reg is dying here, we can use the same hard
704 register for REG and IN_RTX. We do it only for original
705 pseudos as reload pseudos can die although original
706 pseudos still live where reload pseudos dies. */
707 if (REG_P (in_rtx
) && (int) REGNO (in_rtx
) < lra_new_regno_start
708 && find_regno_note (curr_insn
, REG_DEAD
, REGNO (in_rtx
)))
709 lra_assign_reg_val (REGNO (in_rtx
), REGNO (reg
));
714 = lra_create_new_reg_with_unique_value (outmode
, out_rtx
,
716 if (SCALAR_INT_MODE_P (outmode
))
717 new_in_reg
= gen_lowpart_SUBREG (inmode
, reg
);
719 new_in_reg
= gen_rtx_SUBREG (inmode
, reg
, 0);
720 /* NEW_IN_REG is non-paradoxical subreg. We don't want
721 NEW_OUT_REG living above. We add clobber clause for
722 this. This is just a temporary clobber. We can remove
723 it at the end of LRA work. */
724 clobber
= emit_clobber (new_out_reg
);
725 LRA_TEMP_CLOBBER_P (PATTERN (clobber
)) = 1;
726 LRA_SUBREG_P (new_in_reg
) = 1;
727 if (GET_CODE (in_rtx
) == SUBREG
)
729 rtx subreg_reg
= SUBREG_REG (in_rtx
);
731 /* If SUBREG_REG is dying here and sub-registers IN_RTX
732 and NEW_IN_REG are similar, we can use the same hard
733 register for REG and SUBREG_REG. */
734 if (REG_P (subreg_reg
)
735 && (int) REGNO (subreg_reg
) < lra_new_regno_start
736 && GET_MODE (subreg_reg
) == outmode
737 && SUBREG_BYTE (in_rtx
) == SUBREG_BYTE (new_in_reg
)
738 && find_regno_note (curr_insn
, REG_DEAD
, REGNO (subreg_reg
)))
739 lra_assign_reg_val (REGNO (subreg_reg
), REGNO (reg
));
745 /* Pseudos have values -- see comments for lra_reg_info.
746 Different pseudos with the same value do not conflict even if
747 they live in the same place. When we create a pseudo we
748 assign value of original pseudo (if any) from which we
749 created the new pseudo. If we create the pseudo from the
750 input pseudo, the new pseudo will no conflict with the input
751 pseudo which is wrong when the input pseudo lives after the
752 insn and as the new pseudo value is changed by the insn
753 output. Therefore we create the new pseudo from the output.
755 We cannot reuse the current output register because we might
756 have a situation like "a <- a op b", where the constraints
757 force the second input operand ("b") to match the output
758 operand ("a"). "b" must then be copied into a new register
759 so that it doesn't clobber the current value of "a". */
761 new_in_reg
= new_out_reg
762 = lra_create_new_reg_with_unique_value (outmode
, out_rtx
,
765 /* In operand can be got from transformations before processing insn
766 constraints. One example of such transformations is subreg
767 reloading (see function simplify_operand_subreg). The new
768 pseudos created by the transformations might have inaccurate
769 class (ALL_REGS) and we should make their classes more
771 narrow_reload_pseudo_class (in_rtx
, goal_class
);
772 lra_emit_move (copy_rtx (new_in_reg
), in_rtx
);
773 *before
= get_insns ();
775 for (i
= 0; (in
= ins
[i
]) >= 0; i
++)
778 (GET_MODE (*curr_id
->operand_loc
[in
]) == VOIDmode
779 || GET_MODE (new_in_reg
) == GET_MODE (*curr_id
->operand_loc
[in
]));
780 *curr_id
->operand_loc
[in
] = new_in_reg
;
782 lra_update_dups (curr_id
, ins
);
785 /* See a comment for the input operand above. */
786 narrow_reload_pseudo_class (out_rtx
, goal_class
);
787 if (find_reg_note (curr_insn
, REG_UNUSED
, out_rtx
) == NULL_RTX
)
790 lra_emit_move (out_rtx
, copy_rtx (new_out_reg
));
792 *after
= get_insns ();
795 *curr_id
->operand_loc
[out
] = new_out_reg
;
796 lra_update_dup (curr_id
, out
);
799 /* Return register class which is union of all reg classes in insn
800 constraint alternative string starting with P. */
801 static enum reg_class
802 reg_class_from_constraints (const char *p
)
805 enum reg_class op_class
= NO_REGS
;
808 switch ((c
= *p
, len
= CONSTRAINT_LEN (c
, p
)), c
)
815 op_class
= (reg_class_subunion
816 [op_class
][base_reg_class (VOIDmode
, ADDR_SPACE_GENERIC
,
822 op_class
= reg_class_subunion
[op_class
][GENERAL_REGS
];
826 if (REG_CLASS_FROM_CONSTRAINT (c
, p
) == NO_REGS
)
828 #ifdef EXTRA_CONSTRAINT_STR
829 if (EXTRA_ADDRESS_CONSTRAINT (c
, p
))
831 = (reg_class_subunion
832 [op_class
][base_reg_class (VOIDmode
, ADDR_SPACE_GENERIC
,
839 = reg_class_subunion
[op_class
][REG_CLASS_FROM_CONSTRAINT (c
, p
)];
842 while ((p
+= len
), c
);
846 /* If OP is a register, return the class of the register as per
847 get_reg_class, otherwise return NO_REGS. */
848 static inline enum reg_class
849 get_op_class (rtx op
)
851 return REG_P (op
) ? get_reg_class (REGNO (op
)) : NO_REGS
;
854 /* Return generated insn mem_pseudo:=val if TO_P or val:=mem_pseudo
855 otherwise. If modes of MEM_PSEUDO and VAL are different, use
856 SUBREG for VAL to make them equal. */
858 emit_spill_move (bool to_p
, rtx mem_pseudo
, rtx val
)
860 if (GET_MODE (mem_pseudo
) != GET_MODE (val
))
862 /* Usually size of mem_pseudo is greater than val size but in
863 rare cases it can be less as it can be defined by target
864 dependent macro HARD_REGNO_CALLER_SAVE_MODE. */
867 val
= gen_rtx_SUBREG (GET_MODE (mem_pseudo
),
868 GET_CODE (val
) == SUBREG
? SUBREG_REG (val
) : val
,
870 LRA_SUBREG_P (val
) = 1;
874 mem_pseudo
= gen_lowpart_SUBREG (GET_MODE (val
), mem_pseudo
);
875 LRA_SUBREG_P (mem_pseudo
) = 1;
879 ? gen_move_insn (mem_pseudo
, val
)
880 : gen_move_insn (val
, mem_pseudo
));
883 /* Process a special case insn (register move), return true if we
884 don't need to process it anymore. INSN should be a single set
885 insn. Set up that RTL was changed through CHANGE_P and macro
886 SECONDARY_MEMORY_NEEDED says to use secondary memory through
889 check_and_process_move (bool *change_p
, bool *sec_mem_p ATTRIBUTE_UNUSED
)
892 rtx dest
, src
, dreg
, sreg
, old_sreg
, new_reg
, before
, scratch_reg
;
893 enum reg_class dclass
, sclass
, secondary_class
;
894 enum machine_mode sreg_mode
;
895 secondary_reload_info sri
;
897 lra_assert (curr_insn_set
!= NULL_RTX
);
898 dreg
= dest
= SET_DEST (curr_insn_set
);
899 sreg
= src
= SET_SRC (curr_insn_set
);
900 if (GET_CODE (dest
) == SUBREG
)
901 dreg
= SUBREG_REG (dest
);
902 if (GET_CODE (src
) == SUBREG
)
903 sreg
= SUBREG_REG (src
);
904 if (! (REG_P (dreg
) || MEM_P (dreg
)) || ! (REG_P (sreg
) || MEM_P (sreg
)))
906 sclass
= dclass
= NO_REGS
;
908 dclass
= get_reg_class (REGNO (dreg
));
909 if (dclass
== ALL_REGS
)
910 /* ALL_REGS is used for new pseudos created by transformations
911 like reload of SUBREG_REG (see function
912 simplify_operand_subreg). We don't know their class yet. We
913 should figure out the class from processing the insn
914 constraints not in this fast path function. Even if ALL_REGS
915 were a right class for the pseudo, secondary_... hooks usually
916 are not define for ALL_REGS. */
918 sreg_mode
= GET_MODE (sreg
);
921 sclass
= get_reg_class (REGNO (sreg
));
922 if (sclass
== ALL_REGS
)
923 /* See comments above. */
925 if (sclass
== NO_REGS
&& dclass
== NO_REGS
)
927 #ifdef SECONDARY_MEMORY_NEEDED
928 if (SECONDARY_MEMORY_NEEDED (sclass
, dclass
, GET_MODE (src
))
929 #ifdef SECONDARY_MEMORY_NEEDED_MODE
930 && ((sclass
!= NO_REGS
&& dclass
!= NO_REGS
)
931 || GET_MODE (src
) != SECONDARY_MEMORY_NEEDED_MODE (GET_MODE (src
)))
939 if (! REG_P (dreg
) || ! REG_P (sreg
))
942 sri
.icode
= CODE_FOR_nothing
;
944 secondary_class
= NO_REGS
;
945 /* Set up hard register for a reload pseudo for hook
946 secondary_reload because some targets just ignore unassigned
947 pseudos in the hook. */
948 if (dclass
!= NO_REGS
&& lra_get_regno_hard_regno (REGNO (dreg
)) < 0)
950 dregno
= REGNO (dreg
);
951 reg_renumber
[dregno
] = ira_class_hard_regs
[dclass
][0];
955 if (sclass
!= NO_REGS
&& lra_get_regno_hard_regno (REGNO (sreg
)) < 0)
957 sregno
= REGNO (sreg
);
958 reg_renumber
[sregno
] = ira_class_hard_regs
[sclass
][0];
962 if (sclass
!= NO_REGS
)
964 = (enum reg_class
) targetm
.secondary_reload (false, dest
,
965 (reg_class_t
) sclass
,
966 GET_MODE (src
), &sri
);
967 if (sclass
== NO_REGS
968 || ((secondary_class
!= NO_REGS
|| sri
.icode
!= CODE_FOR_nothing
)
969 && dclass
!= NO_REGS
))
971 enum reg_class old_sclass
= secondary_class
;
972 secondary_reload_info old_sri
= sri
;
975 sri
.icode
= CODE_FOR_nothing
;
978 = (enum reg_class
) targetm
.secondary_reload (true, sreg
,
979 (reg_class_t
) dclass
,
981 /* Check the target hook consistency. */
983 ((secondary_class
== NO_REGS
&& sri
.icode
== CODE_FOR_nothing
)
984 || (old_sclass
== NO_REGS
&& old_sri
.icode
== CODE_FOR_nothing
)
985 || (secondary_class
== old_sclass
&& sri
.icode
== old_sri
.icode
));
988 reg_renumber
[sregno
] = -1;
990 reg_renumber
[dregno
] = -1;
991 if (secondary_class
== NO_REGS
&& sri
.icode
== CODE_FOR_nothing
)
995 if (secondary_class
!= NO_REGS
)
996 new_reg
= lra_create_new_reg_with_unique_value (sreg_mode
, NULL_RTX
,
1000 if (old_sreg
!= sreg
)
1001 sreg
= copy_rtx (sreg
);
1002 if (sri
.icode
== CODE_FOR_nothing
)
1003 lra_emit_move (new_reg
, sreg
);
1006 enum reg_class scratch_class
;
1008 scratch_class
= (reg_class_from_constraints
1009 (insn_data
[sri
.icode
].operand
[2].constraint
));
1010 scratch_reg
= (lra_create_new_reg_with_unique_value
1011 (insn_data
[sri
.icode
].operand
[2].mode
, NULL_RTX
,
1012 scratch_class
, "scratch"));
1013 emit_insn (GEN_FCN (sri
.icode
) (new_reg
!= NULL_RTX
? new_reg
: dest
,
1014 sreg
, scratch_reg
));
1016 before
= get_insns ();
1018 lra_process_new_insns (curr_insn
, before
, NULL_RTX
, "Inserting the move");
1019 if (new_reg
!= NULL_RTX
)
1021 if (GET_CODE (src
) == SUBREG
)
1022 SUBREG_REG (src
) = new_reg
;
1024 SET_SRC (curr_insn_set
) = new_reg
;
1028 if (lra_dump_file
!= NULL
)
1030 fprintf (lra_dump_file
, "Deleting move %u\n", INSN_UID (curr_insn
));
1031 dump_insn_slim (lra_dump_file
, curr_insn
);
1033 lra_set_insn_deleted (curr_insn
);
1039 /* The following data describe the result of process_alt_operands.
1040 The data are used in curr_insn_transform to generate reloads. */
1042 /* The chosen reg classes which should be used for the corresponding
1044 static enum reg_class goal_alt
[MAX_RECOG_OPERANDS
];
1045 /* True if the operand should be the same as another operand and that
1046 other operand does not need a reload. */
1047 static bool goal_alt_match_win
[MAX_RECOG_OPERANDS
];
1048 /* True if the operand does not need a reload. */
1049 static bool goal_alt_win
[MAX_RECOG_OPERANDS
];
1050 /* True if the operand can be offsetable memory. */
1051 static bool goal_alt_offmemok
[MAX_RECOG_OPERANDS
];
1052 /* The number of an operand to which given operand can be matched to. */
1053 static int goal_alt_matches
[MAX_RECOG_OPERANDS
];
1054 /* The number of elements in the following array. */
1055 static int goal_alt_dont_inherit_ops_num
;
1056 /* Numbers of operands whose reload pseudos should not be inherited. */
1057 static int goal_alt_dont_inherit_ops
[MAX_RECOG_OPERANDS
];
1058 /* True if the insn commutative operands should be swapped. */
1059 static bool goal_alt_swapped
;
1060 /* The chosen insn alternative. */
1061 static int goal_alt_number
;
1063 /* The following five variables are used to choose the best insn
1064 alternative. They reflect final characteristics of the best
1067 /* Number of necessary reloads and overall cost reflecting the
1068 previous value and other unpleasantness of the best alternative. */
1069 static int best_losers
, best_overall
;
1070 /* Overall number hard registers used for reloads. For example, on
1071 some targets we need 2 general registers to reload DFmode and only
1072 one floating point register. */
1073 static int best_reload_nregs
;
1074 /* Overall number reflecting distances of previous reloading the same
1075 value. The distances are counted from the current BB start. It is
1076 used to improve inheritance chances. */
1077 static int best_reload_sum
;
1079 /* True if the current insn should have no correspondingly input or
1081 static bool no_input_reloads_p
, no_output_reloads_p
;
1083 /* True if we swapped the commutative operands in the current
1085 static int curr_swapped
;
1087 /* Arrange for address element *LOC to be a register of class CL.
1088 Add any input reloads to list BEFORE. AFTER is nonnull if *LOC is an
1089 automodified value; handle that case by adding the required output
1090 reloads to list AFTER. Return true if the RTL was changed. */
1092 process_addr_reg (rtx
*loc
, rtx
*before
, rtx
*after
, enum reg_class cl
)
1095 enum reg_class rclass
, new_class
;
1098 enum machine_mode mode
;
1099 bool before_p
= false;
1101 loc
= strip_subreg (loc
);
1103 mode
= GET_MODE (reg
);
1106 /* Always reload memory in an address even if the target supports
1108 new_reg
= lra_create_new_reg_with_unique_value (mode
, reg
, cl
, "address");
1113 regno
= REGNO (reg
);
1114 rclass
= get_reg_class (regno
);
1115 if ((*loc
= get_equiv_substitution (reg
)) != reg
)
1117 if (lra_dump_file
!= NULL
)
1119 fprintf (lra_dump_file
,
1120 "Changing pseudo %d in address of insn %u on equiv ",
1121 REGNO (reg
), INSN_UID (curr_insn
));
1122 dump_value_slim (lra_dump_file
, *loc
, 1);
1123 fprintf (lra_dump_file
, "\n");
1125 *loc
= copy_rtx (*loc
);
1127 if (*loc
!= reg
|| ! in_class_p (reg
, cl
, &new_class
))
1130 if (get_reload_reg (after
== NULL
? OP_IN
: OP_INOUT
,
1131 mode
, reg
, cl
, "address", &new_reg
))
1134 else if (new_class
!= NO_REGS
&& rclass
!= new_class
)
1136 change_class (regno
, new_class
, " Change", true);
1144 push_to_sequence (*before
);
1145 lra_emit_move (new_reg
, reg
);
1146 *before
= get_insns ();
1153 lra_emit_move (reg
, new_reg
);
1155 *after
= get_insns ();
1161 /* Insert move insn in simplify_operand_subreg. BEFORE returns
1162 the insn to be inserted before curr insn. AFTER returns the
1163 the insn to be inserted after curr insn. ORIGREG and NEWREG
1164 are the original reg and new reg for reload. */
1166 insert_move_for_subreg (rtx
*before
, rtx
*after
, rtx origreg
, rtx newreg
)
1170 push_to_sequence (*before
);
1171 lra_emit_move (newreg
, origreg
);
1172 *before
= get_insns ();
1178 lra_emit_move (origreg
, newreg
);
1180 *after
= get_insns ();
1185 /* Make reloads for subreg in operand NOP with internal subreg mode
1186 REG_MODE, add new reloads for further processing. Return true if
1187 any reload was generated. */
1189 simplify_operand_subreg (int nop
, enum machine_mode reg_mode
)
1193 enum machine_mode mode
;
1195 rtx operand
= *curr_id
->operand_loc
[nop
];
1196 enum reg_class regclass
;
1199 before
= after
= NULL_RTX
;
1201 if (GET_CODE (operand
) != SUBREG
)
1204 mode
= GET_MODE (operand
);
1205 reg
= SUBREG_REG (operand
);
1206 type
= curr_static_id
->operand
[nop
].type
;
1207 /* If we change address for paradoxical subreg of memory, the
1208 address might violate the necessary alignment or the access might
1209 be slow. So take this into consideration. We should not worry
1210 about access beyond allocated memory for paradoxical memory
1211 subregs as we don't substitute such equiv memory (see processing
1212 equivalences in function lra_constraints) and because for spilled
1213 pseudos we allocate stack memory enough for the biggest
1214 corresponding paradoxical subreg. */
1216 && (! SLOW_UNALIGNED_ACCESS (mode
, MEM_ALIGN (reg
))
1217 || MEM_ALIGN (reg
) >= GET_MODE_ALIGNMENT (mode
)))
1218 || (REG_P (reg
) && REGNO (reg
) < FIRST_PSEUDO_REGISTER
))
1220 alter_subreg (curr_id
->operand_loc
[nop
], false);
1223 /* Put constant into memory when we have mixed modes. It generates
1224 a better code in most cases as it does not need a secondary
1225 reload memory. It also prevents LRA looping when LRA is using
1226 secondary reload memory again and again. */
1227 if (CONSTANT_P (reg
) && CONST_POOL_OK_P (reg_mode
, reg
)
1228 && SCALAR_INT_MODE_P (reg_mode
) != SCALAR_INT_MODE_P (mode
))
1230 SUBREG_REG (operand
) = force_const_mem (reg_mode
, reg
);
1231 alter_subreg (curr_id
->operand_loc
[nop
], false);
1234 /* Force a reload of the SUBREG_REG if this is a constant or PLUS or
1235 if there may be a problem accessing OPERAND in the outer
1238 && REGNO (reg
) >= FIRST_PSEUDO_REGISTER
1239 && (hard_regno
= lra_get_regno_hard_regno (REGNO (reg
))) >= 0
1240 /* Don't reload paradoxical subregs because we could be looping
1241 having repeatedly final regno out of hard regs range. */
1242 && (hard_regno_nregs
[hard_regno
][GET_MODE (reg
)]
1243 >= hard_regno_nregs
[hard_regno
][mode
])
1244 && simplify_subreg_regno (hard_regno
, GET_MODE (reg
),
1245 SUBREG_BYTE (operand
), mode
) < 0
1246 /* Don't reload subreg for matching reload. It is actually
1247 valid subreg in LRA. */
1248 && ! LRA_SUBREG_P (operand
))
1249 || CONSTANT_P (reg
) || GET_CODE (reg
) == PLUS
|| MEM_P (reg
))
1251 /* The class will be defined later in curr_insn_transform. */
1252 enum reg_class rclass
1253 = (enum reg_class
) targetm
.preferred_reload_class (reg
, ALL_REGS
);
1255 if (get_reload_reg (curr_static_id
->operand
[nop
].type
, reg_mode
, reg
,
1256 rclass
, "subreg reg", &new_reg
))
1258 bool insert_before
, insert_after
;
1259 bitmap_set_bit (&lra_subreg_reload_pseudos
, REGNO (new_reg
));
1261 insert_before
= (type
!= OP_OUT
1262 || GET_MODE_SIZE (GET_MODE (reg
)) > GET_MODE_SIZE (mode
));
1263 insert_after
= (type
!= OP_IN
);
1264 insert_move_for_subreg (insert_before
? &before
: NULL
,
1265 insert_after
? &after
: NULL
,
1268 SUBREG_REG (operand
) = new_reg
;
1269 lra_process_new_insns (curr_insn
, before
, after
,
1270 "Inserting subreg reload");
1273 /* Force a reload for a paradoxical subreg. For paradoxical subreg,
1274 IRA allocates hardreg to the inner pseudo reg according to its mode
1275 instead of the outermode, so the size of the hardreg may not be enough
1276 to contain the outermode operand, in that case we may need to insert
1277 reload for the reg. For the following two types of paradoxical subreg,
1278 we need to insert reload:
1279 1. If the op_type is OP_IN, and the hardreg could not be paired with
1280 other hardreg to contain the outermode operand
1281 (checked by in_hard_reg_set_p), we need to insert the reload.
1282 2. If the op_type is OP_OUT or OP_INOUT.
1284 Here is a paradoxical subreg example showing how the reload is generated:
1286 (insn 5 4 7 2 (set (reg:TI 106 [ __comp ])
1287 (subreg:TI (reg:DI 107 [ __comp ]) 0)) {*movti_internal_rex64}
1289 In IRA, reg107 is allocated to a DImode hardreg. We use x86-64 as example
1290 here, if reg107 is assigned to hardreg R15, because R15 is the last
1291 hardreg, compiler cannot find another hardreg to pair with R15 to
1292 contain TImode data. So we insert a TImode reload reg180 for it.
1293 After reload is inserted:
1295 (insn 283 0 0 (set (subreg:DI (reg:TI 180 [orig:107 __comp ] [107]) 0)
1296 (reg:DI 107 [ __comp ])) -1
1297 (insn 5 4 7 2 (set (reg:TI 106 [ __comp ])
1298 (subreg:TI (reg:TI 180 [orig:107 __comp ] [107]) 0)) {*movti_internal_rex64}
1300 Two reload hard registers will be allocated to reg180 to save TImode data
1302 else if (REG_P (reg
)
1303 && REGNO (reg
) >= FIRST_PSEUDO_REGISTER
1304 && (hard_regno
= lra_get_regno_hard_regno (REGNO (reg
))) >= 0
1305 && (hard_regno_nregs
[hard_regno
][GET_MODE (reg
)]
1306 < hard_regno_nregs
[hard_regno
][mode
])
1307 && (regclass
= lra_get_allocno_class (REGNO (reg
)))
1309 || !in_hard_reg_set_p (reg_class_contents
[regclass
],
1312 /* The class will be defined later in curr_insn_transform. */
1313 enum reg_class rclass
1314 = (enum reg_class
) targetm
.preferred_reload_class (reg
, ALL_REGS
);
1316 if (get_reload_reg (curr_static_id
->operand
[nop
].type
, mode
, reg
,
1317 rclass
, "paradoxical subreg", &new_reg
))
1320 bool insert_before
, insert_after
;
1322 PUT_MODE (new_reg
, mode
);
1323 subreg
= simplify_gen_subreg (GET_MODE (reg
), new_reg
, mode
, 0);
1324 bitmap_set_bit (&lra_subreg_reload_pseudos
, REGNO (new_reg
));
1326 insert_before
= (type
!= OP_OUT
);
1327 insert_after
= (type
!= OP_IN
);
1328 insert_move_for_subreg (insert_before
? &before
: NULL
,
1329 insert_after
? &after
: NULL
,
1332 SUBREG_REG (operand
) = new_reg
;
1333 lra_process_new_insns (curr_insn
, before
, after
,
1334 "Inserting paradoxical subreg reload");
1340 /* Return TRUE if X refers for a hard register from SET. */
1342 uses_hard_regs_p (rtx x
, HARD_REG_SET set
)
1344 int i
, j
, x_hard_regno
;
1345 enum machine_mode mode
;
1351 code
= GET_CODE (x
);
1352 mode
= GET_MODE (x
);
1356 code
= GET_CODE (x
);
1357 if (GET_MODE_SIZE (GET_MODE (x
)) > GET_MODE_SIZE (mode
))
1358 mode
= GET_MODE (x
);
1363 x_hard_regno
= get_hard_regno (x
);
1364 return (x_hard_regno
>= 0
1365 && overlaps_hard_reg_set_p (set
, mode
, x_hard_regno
));
1369 struct address_info ad
;
1371 decompose_mem_address (&ad
, x
);
1372 if (ad
.base_term
!= NULL
&& uses_hard_regs_p (*ad
.base_term
, set
))
1374 if (ad
.index_term
!= NULL
&& uses_hard_regs_p (*ad
.index_term
, set
))
1377 fmt
= GET_RTX_FORMAT (code
);
1378 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
1382 if (uses_hard_regs_p (XEXP (x
, i
), set
))
1385 else if (fmt
[i
] == 'E')
1387 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
1388 if (uses_hard_regs_p (XVECEXP (x
, i
, j
), set
))
1395 /* Return true if OP is a spilled pseudo. */
1397 spilled_pseudo_p (rtx op
)
1400 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
&& in_mem_p (REGNO (op
)));
1403 /* Return true if X is a general constant. */
1405 general_constant_p (rtx x
)
1407 return CONSTANT_P (x
) && (! flag_pic
|| LEGITIMATE_PIC_OPERAND_P (x
));
1411 reg_in_class_p (rtx reg
, enum reg_class cl
)
1414 return get_reg_class (REGNO (reg
)) == NO_REGS
;
1415 return in_class_p (reg
, cl
, NULL
);
1418 /* Major function to choose the current insn alternative and what
1419 operands should be reloaded and how. If ONLY_ALTERNATIVE is not
1420 negative we should consider only this alternative. Return false if
1421 we can not choose the alternative or find how to reload the
1424 process_alt_operands (int only_alternative
)
1427 int nop
, overall
, nalt
;
1428 int n_alternatives
= curr_static_id
->n_alternatives
;
1429 int n_operands
= curr_static_id
->n_operands
;
1430 /* LOSERS counts the operands that don't fit this alternative and
1431 would require loading. */
1433 /* REJECT is a count of how undesirable this alternative says it is
1434 if any reloading is required. If the alternative matches exactly
1435 then REJECT is ignored, but otherwise it gets this much counted
1436 against it in addition to the reloading needed. */
1438 /* The number of elements in the following array. */
1439 int early_clobbered_regs_num
;
1440 /* Numbers of operands which are early clobber registers. */
1441 int early_clobbered_nops
[MAX_RECOG_OPERANDS
];
1442 enum reg_class curr_alt
[MAX_RECOG_OPERANDS
];
1443 HARD_REG_SET curr_alt_set
[MAX_RECOG_OPERANDS
];
1444 bool curr_alt_match_win
[MAX_RECOG_OPERANDS
];
1445 bool curr_alt_win
[MAX_RECOG_OPERANDS
];
1446 bool curr_alt_offmemok
[MAX_RECOG_OPERANDS
];
1447 int curr_alt_matches
[MAX_RECOG_OPERANDS
];
1448 /* The number of elements in the following array. */
1449 int curr_alt_dont_inherit_ops_num
;
1450 /* Numbers of operands whose reload pseudos should not be inherited. */
1451 int curr_alt_dont_inherit_ops
[MAX_RECOG_OPERANDS
];
1453 /* The register when the operand is a subreg of register, otherwise the
1455 rtx no_subreg_reg_operand
[MAX_RECOG_OPERANDS
];
1456 /* The register if the operand is a register or subreg of register,
1458 rtx operand_reg
[MAX_RECOG_OPERANDS
];
1459 int hard_regno
[MAX_RECOG_OPERANDS
];
1460 enum machine_mode biggest_mode
[MAX_RECOG_OPERANDS
];
1461 int reload_nregs
, reload_sum
;
1465 /* Calculate some data common for all alternatives to speed up the
1467 for (nop
= 0; nop
< n_operands
; nop
++)
1471 op
= no_subreg_reg_operand
[nop
] = *curr_id
->operand_loc
[nop
];
1472 /* The real hard regno of the operand after the allocation. */
1473 hard_regno
[nop
] = get_hard_regno (op
);
1475 operand_reg
[nop
] = reg
= op
;
1476 biggest_mode
[nop
] = GET_MODE (op
);
1477 if (GET_CODE (op
) == SUBREG
)
1479 operand_reg
[nop
] = reg
= SUBREG_REG (op
);
1480 if (GET_MODE_SIZE (biggest_mode
[nop
])
1481 < GET_MODE_SIZE (GET_MODE (reg
)))
1482 biggest_mode
[nop
] = GET_MODE (reg
);
1485 operand_reg
[nop
] = NULL_RTX
;
1486 else if (REGNO (reg
) >= FIRST_PSEUDO_REGISTER
1487 || ((int) REGNO (reg
)
1488 == lra_get_elimination_hard_regno (REGNO (reg
))))
1489 no_subreg_reg_operand
[nop
] = reg
;
1491 operand_reg
[nop
] = no_subreg_reg_operand
[nop
]
1492 /* Just use natural mode for elimination result. It should
1493 be enough for extra constraints hooks. */
1494 = regno_reg_rtx
[hard_regno
[nop
]];
1497 /* The constraints are made of several alternatives. Each operand's
1498 constraint looks like foo,bar,... with commas separating the
1499 alternatives. The first alternatives for all operands go
1500 together, the second alternatives go together, etc.
1502 First loop over alternatives. */
1503 for (nalt
= 0; nalt
< n_alternatives
; nalt
++)
1505 /* Loop over operands for one constraint alternative. */
1506 #if HAVE_ATTR_enabled
1507 if (curr_id
->alternative_enabled_p
!= NULL
1508 && ! curr_id
->alternative_enabled_p
[nalt
])
1512 if (only_alternative
>= 0 && nalt
!= only_alternative
)
1516 overall
= losers
= reject
= reload_nregs
= reload_sum
= 0;
1517 for (nop
= 0; nop
< n_operands
; nop
++)
1519 int inc
= (curr_static_id
1520 ->operand_alternative
[nalt
* n_operands
+ nop
].reject
);
1521 if (lra_dump_file
!= NULL
&& inc
!= 0)
1522 fprintf (lra_dump_file
,
1523 " Staticly defined alt reject+=%d\n", inc
);
1526 early_clobbered_regs_num
= 0;
1528 for (nop
= 0; nop
< n_operands
; nop
++)
1532 int len
, c
, m
, i
, opalt_num
, this_alternative_matches
;
1533 bool win
, did_match
, offmemok
, early_clobber_p
;
1534 /* false => this operand can be reloaded somehow for this
1537 /* true => this operand can be reloaded if the alternative
1540 /* True if a constant forced into memory would be OK for
1543 enum reg_class this_alternative
, this_costly_alternative
;
1544 HARD_REG_SET this_alternative_set
, this_costly_alternative_set
;
1545 bool this_alternative_match_win
, this_alternative_win
;
1546 bool this_alternative_offmemok
;
1548 enum machine_mode mode
;
1550 opalt_num
= nalt
* n_operands
+ nop
;
1551 if (curr_static_id
->operand_alternative
[opalt_num
].anything_ok
)
1553 /* Fast track for no constraints at all. */
1554 curr_alt
[nop
] = NO_REGS
;
1555 CLEAR_HARD_REG_SET (curr_alt_set
[nop
]);
1556 curr_alt_win
[nop
] = true;
1557 curr_alt_match_win
[nop
] = false;
1558 curr_alt_offmemok
[nop
] = false;
1559 curr_alt_matches
[nop
] = -1;
1563 op
= no_subreg_reg_operand
[nop
];
1564 mode
= curr_operand_mode
[nop
];
1566 win
= did_match
= winreg
= offmemok
= constmemok
= false;
1569 early_clobber_p
= false;
1570 p
= curr_static_id
->operand_alternative
[opalt_num
].constraint
;
1572 this_costly_alternative
= this_alternative
= NO_REGS
;
1573 /* We update set of possible hard regs besides its class
1574 because reg class might be inaccurate. For example,
1575 union of LO_REGS (l), HI_REGS(h), and STACK_REG(k) in ARM
1576 is translated in HI_REGS because classes are merged by
1577 pairs and there is no accurate intermediate class. */
1578 CLEAR_HARD_REG_SET (this_alternative_set
);
1579 CLEAR_HARD_REG_SET (this_costly_alternative_set
);
1580 this_alternative_win
= false;
1581 this_alternative_match_win
= false;
1582 this_alternative_offmemok
= false;
1583 this_alternative_matches
= -1;
1585 /* An empty constraint should be excluded by the fast
1587 lra_assert (*p
!= 0 && *p
!= ',');
1589 /* Scan this alternative's specs for this operand; set WIN
1590 if the operand fits any letter in this alternative.
1591 Otherwise, clear BADOP if this operand could fit some
1592 letter after reloads, or set WINREG if this operand could
1593 fit after reloads provided the constraint allows some
1598 switch ((c
= *p
, len
= CONSTRAINT_LEN (c
, p
)), c
)
1607 case '=': case '+': case '?': case '*': case '!':
1608 case ' ': case '\t':
1612 /* We only support one commutative marker, the first
1613 one. We already set commutative above. */
1617 early_clobber_p
= true;
1621 /* Ignore rest of this alternative. */
1625 case '0': case '1': case '2': case '3': case '4':
1626 case '5': case '6': case '7': case '8': case '9':
1631 m
= strtoul (p
, &end
, 10);
1634 lra_assert (nop
> m
);
1636 this_alternative_matches
= m
;
1637 m_hregno
= get_hard_regno (*curr_id
->operand_loc
[m
]);
1638 /* We are supposed to match a previous operand.
1639 If we do, we win if that one did. If we do
1640 not, count both of the operands as losers.
1641 (This is too conservative, since most of the
1642 time only a single reload insn will be needed
1643 to make the two operands win. As a result,
1644 this alternative may be rejected when it is
1645 actually desirable.) */
1647 if (operands_match_p (*curr_id
->operand_loc
[nop
],
1648 *curr_id
->operand_loc
[m
], m_hregno
))
1650 /* We should reject matching of an early
1651 clobber operand if the matching operand is
1652 not dying in the insn. */
1653 if (! curr_static_id
->operand
[m
].early_clobber
1654 || operand_reg
[nop
] == NULL_RTX
1655 || (find_regno_note (curr_insn
, REG_DEAD
,
1657 || REGNO (op
) == REGNO (operand_reg
[m
])))
1662 /* If we are matching a non-offsettable
1663 address where an offsettable address was
1664 expected, then we must reject this
1665 combination, because we can't reload
1667 if (curr_alt_offmemok
[m
]
1668 && MEM_P (*curr_id
->operand_loc
[m
])
1669 && curr_alt
[m
] == NO_REGS
&& ! curr_alt_win
[m
])
1675 /* Operands don't match. Both operands must
1676 allow a reload register, otherwise we
1677 cannot make them match. */
1678 if (curr_alt
[m
] == NO_REGS
)
1680 /* Retroactively mark the operand we had to
1681 match as a loser, if it wasn't already and
1682 it wasn't matched to a register constraint
1683 (e.g it might be matched by memory). */
1685 && (operand_reg
[m
] == NULL_RTX
1686 || hard_regno
[m
] < 0))
1690 += (ira_reg_class_max_nregs
[curr_alt
[m
]]
1691 [GET_MODE (*curr_id
->operand_loc
[m
])]);
1694 /* We prefer no matching alternatives because
1695 it gives more freedom in RA. */
1696 if (operand_reg
[nop
] == NULL_RTX
1697 || (find_regno_note (curr_insn
, REG_DEAD
,
1698 REGNO (operand_reg
[nop
]))
1701 if (lra_dump_file
!= NULL
)
1704 " %d Matching alt: reject+=2\n",
1709 /* If we have to reload this operand and some
1710 previous operand also had to match the same
1711 thing as this operand, we don't know how to do
1713 if (!match_p
|| !curr_alt_win
[m
])
1715 for (i
= 0; i
< nop
; i
++)
1716 if (curr_alt_matches
[i
] == m
)
1724 /* This can be fixed with reloads if the operand
1725 we are supposed to match can be fixed with
1728 this_alternative
= curr_alt
[m
];
1729 COPY_HARD_REG_SET (this_alternative_set
, curr_alt_set
[m
]);
1730 winreg
= this_alternative
!= NO_REGS
;
1735 cl
= base_reg_class (VOIDmode
, ADDR_SPACE_GENERIC
,
1737 this_alternative
= reg_class_subunion
[this_alternative
][cl
];
1738 IOR_HARD_REG_SET (this_alternative_set
,
1739 reg_class_contents
[cl
]);
1742 this_costly_alternative
1743 = reg_class_subunion
[this_costly_alternative
][cl
];
1744 IOR_HARD_REG_SET (this_costly_alternative_set
,
1745 reg_class_contents
[cl
]);
1751 case TARGET_MEM_CONSTRAINT
:
1752 if (MEM_P (op
) || spilled_pseudo_p (op
))
1754 /* We can put constant or pseudo value into memory
1755 to satisfy the constraint. */
1756 if (CONST_POOL_OK_P (mode
, op
) || REG_P (op
))
1763 && (GET_CODE (XEXP (op
, 0)) == PRE_DEC
1764 || GET_CODE (XEXP (op
, 0)) == POST_DEC
))
1770 && (GET_CODE (XEXP (op
, 0)) == PRE_INC
1771 || GET_CODE (XEXP (op
, 0)) == POST_INC
))
1775 /* Memory op whose address is not offsettable. */
1778 && ! offsettable_nonstrict_memref_p (op
))
1782 /* Memory operand whose address is offsettable. */
1785 && offsettable_nonstrict_memref_p (op
))
1786 || spilled_pseudo_p (op
))
1788 /* We can put constant or pseudo value into memory
1789 or make memory address offsetable to satisfy the
1791 if (CONST_POOL_OK_P (mode
, op
) || MEM_P (op
) || REG_P (op
))
1799 if (GET_CODE (op
) == CONST_DOUBLE
1800 || (GET_CODE (op
) == CONST_VECTOR
1801 && (GET_MODE_CLASS (mode
) == MODE_VECTOR_FLOAT
)))
1807 if (CONST_DOUBLE_AS_FLOAT_P (op
)
1808 && CONST_DOUBLE_OK_FOR_CONSTRAINT_P (op
, c
, p
))
1813 if (CONST_SCALAR_INT_P (op
))
1817 if (general_constant_p (op
))
1822 if (CONST_SCALAR_INT_P (op
))
1834 if (CONST_INT_P (op
)
1835 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op
), c
, p
))
1840 /* This constraint should be excluded by the fast
1847 || general_constant_p (op
)
1848 || spilled_pseudo_p (op
))
1850 /* Drop through into 'r' case. */
1854 = reg_class_subunion
[this_alternative
][GENERAL_REGS
];
1855 IOR_HARD_REG_SET (this_alternative_set
,
1856 reg_class_contents
[GENERAL_REGS
]);
1859 this_costly_alternative
1860 = (reg_class_subunion
1861 [this_costly_alternative
][GENERAL_REGS
]);
1862 IOR_HARD_REG_SET (this_costly_alternative_set
,
1863 reg_class_contents
[GENERAL_REGS
]);
1868 if (REG_CLASS_FROM_CONSTRAINT (c
, p
) == NO_REGS
)
1870 #ifdef EXTRA_CONSTRAINT_STR
1871 if (EXTRA_MEMORY_CONSTRAINT (c
, p
))
1873 if (EXTRA_CONSTRAINT_STR (op
, c
, p
))
1875 else if (spilled_pseudo_p (op
))
1878 /* If we didn't already win, we can reload
1879 constants via force_const_mem or put the
1880 pseudo value into memory, or make other
1881 memory by reloading the address like for
1883 if (CONST_POOL_OK_P (mode
, op
)
1884 || MEM_P (op
) || REG_P (op
))
1890 if (EXTRA_ADDRESS_CONSTRAINT (c
, p
))
1892 if (EXTRA_CONSTRAINT_STR (op
, c
, p
))
1895 /* If we didn't already win, we can reload
1896 the address into a base register. */
1897 cl
= base_reg_class (VOIDmode
, ADDR_SPACE_GENERIC
,
1900 = reg_class_subunion
[this_alternative
][cl
];
1901 IOR_HARD_REG_SET (this_alternative_set
,
1902 reg_class_contents
[cl
]);
1905 this_costly_alternative
1906 = (reg_class_subunion
1907 [this_costly_alternative
][cl
]);
1908 IOR_HARD_REG_SET (this_costly_alternative_set
,
1909 reg_class_contents
[cl
]);
1915 if (EXTRA_CONSTRAINT_STR (op
, c
, p
))
1921 cl
= REG_CLASS_FROM_CONSTRAINT (c
, p
);
1922 this_alternative
= reg_class_subunion
[this_alternative
][cl
];
1923 IOR_HARD_REG_SET (this_alternative_set
,
1924 reg_class_contents
[cl
]);
1927 this_costly_alternative
1928 = reg_class_subunion
[this_costly_alternative
][cl
];
1929 IOR_HARD_REG_SET (this_costly_alternative_set
,
1930 reg_class_contents
[cl
]);
1933 if (mode
== BLKmode
)
1938 if (hard_regno
[nop
] >= 0
1939 && in_hard_reg_set_p (this_alternative_set
,
1940 mode
, hard_regno
[nop
]))
1942 else if (hard_regno
[nop
] < 0
1943 && in_class_p (op
, this_alternative
, NULL
))
1948 if (c
!= ' ' && c
!= '\t')
1949 costly_p
= c
== '*';
1951 while ((p
+= len
), c
);
1953 scratch_p
= (operand_reg
[nop
] != NULL_RTX
1954 && lra_former_scratch_p (REGNO (operand_reg
[nop
])));
1955 /* Record which operands fit this alternative. */
1958 this_alternative_win
= true;
1959 if (operand_reg
[nop
] != NULL_RTX
)
1961 if (hard_regno
[nop
] >= 0)
1963 if (in_hard_reg_set_p (this_costly_alternative_set
,
1964 mode
, hard_regno
[nop
]))
1966 if (lra_dump_file
!= NULL
)
1967 fprintf (lra_dump_file
,
1968 " %d Costly set: reject++\n",
1975 /* Prefer won reg to spilled pseudo under other
1976 equal conditions for possibe inheritance. */
1979 if (lra_dump_file
!= NULL
)
1982 " %d Non pseudo reload: reject++\n",
1986 if (in_class_p (operand_reg
[nop
],
1987 this_costly_alternative
, NULL
))
1989 if (lra_dump_file
!= NULL
)
1992 " %d Non pseudo costly reload:"
1998 /* We simulate the behaviour of old reload here.
1999 Although scratches need hard registers and it
2000 might result in spilling other pseudos, no reload
2001 insns are generated for the scratches. So it
2002 might cost something but probably less than old
2003 reload pass believes. */
2006 if (lra_dump_file
!= NULL
)
2007 fprintf (lra_dump_file
,
2008 " %d Scratch win: reject+=2\n",
2015 this_alternative_match_win
= true;
2018 int const_to_mem
= 0;
2021 /* If this alternative asks for a specific reg class, see if there
2022 is at least one allocatable register in that class. */
2024 = (this_alternative
== NO_REGS
2025 || (hard_reg_set_subset_p
2026 (reg_class_contents
[this_alternative
],
2027 lra_no_alloc_regs
)));
2029 /* For asms, verify that the class for this alternative is possible
2030 for the mode that is specified. */
2031 if (!no_regs_p
&& INSN_CODE (curr_insn
) < 0)
2034 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
2035 if (HARD_REGNO_MODE_OK (i
, mode
)
2036 && in_hard_reg_set_p (reg_class_contents
[this_alternative
], mode
, i
))
2038 if (i
== FIRST_PSEUDO_REGISTER
)
2042 /* If this operand accepts a register, and if the
2043 register class has at least one allocatable register,
2044 then this operand can be reloaded. */
2045 if (winreg
&& !no_regs_p
)
2051 this_alternative_offmemok
= offmemok
;
2052 if (this_costly_alternative
!= NO_REGS
)
2054 if (lra_dump_file
!= NULL
)
2055 fprintf (lra_dump_file
,
2056 " %d Costly loser: reject++\n", nop
);
2059 /* If the operand is dying, has a matching constraint,
2060 and satisfies constraints of the matched operand
2061 which failed to satisfy the own constraints, we do
2062 not need to generate a reload insn for this
2064 if (!(this_alternative_matches
>= 0
2065 && !curr_alt_win
[this_alternative_matches
]
2067 && find_regno_note (curr_insn
, REG_DEAD
, REGNO (op
))
2068 && (hard_regno
[nop
] >= 0
2069 ? in_hard_reg_set_p (this_alternative_set
,
2070 mode
, hard_regno
[nop
])
2071 : in_class_p (op
, this_alternative
, NULL
))))
2073 /* Strict_low_part requires to reload the register
2074 not the sub-register. In this case we should
2075 check that a final reload hard reg can hold the
2077 if (curr_static_id
->operand
[nop
].strict_low
2079 && hard_regno
[nop
] < 0
2080 && GET_CODE (*curr_id
->operand_loc
[nop
]) == SUBREG
2081 && ira_class_hard_regs_num
[this_alternative
] > 0
2082 && ! HARD_REGNO_MODE_OK (ira_class_hard_regs
2083 [this_alternative
][0],
2085 (*curr_id
->operand_loc
[nop
])))
2089 if (operand_reg
[nop
] != NULL_RTX
2090 /* Output operands and matched input operands are
2091 not inherited. The following conditions do not
2092 exactly describe the previous statement but they
2093 are pretty close. */
2094 && curr_static_id
->operand
[nop
].type
!= OP_OUT
2095 && (this_alternative_matches
< 0
2096 || curr_static_id
->operand
[nop
].type
!= OP_IN
))
2098 int last_reload
= (lra_reg_info
[ORIGINAL_REGNO
2102 if (last_reload
> bb_reload_num
)
2103 reload_sum
+= last_reload
- bb_reload_num
;
2105 /* If this is a constant that is reloaded into the
2106 desired class by copying it to memory first, count
2107 that as another reload. This is consistent with
2108 other code and is required to avoid choosing another
2109 alternative when the constant is moved into memory.
2110 Note that the test here is precisely the same as in
2111 the code below that calls force_const_mem. */
2112 if (CONST_POOL_OK_P (mode
, op
)
2113 && ((targetm
.preferred_reload_class
2114 (op
, this_alternative
) == NO_REGS
)
2115 || no_input_reloads_p
))
2122 /* Alternative loses if it requires a type of reload not
2123 permitted for this insn. We can always reload
2124 objects with a REG_UNUSED note. */
2125 if ((curr_static_id
->operand
[nop
].type
!= OP_IN
2126 && no_output_reloads_p
2127 && ! find_reg_note (curr_insn
, REG_UNUSED
, op
))
2128 || (curr_static_id
->operand
[nop
].type
!= OP_OUT
2129 && no_input_reloads_p
&& ! const_to_mem
))
2132 /* Check strong discouragement of reload of non-constant
2133 into class THIS_ALTERNATIVE. */
2134 if (! CONSTANT_P (op
) && ! no_regs_p
2135 && (targetm
.preferred_reload_class
2136 (op
, this_alternative
) == NO_REGS
2137 || (curr_static_id
->operand
[nop
].type
== OP_OUT
2138 && (targetm
.preferred_output_reload_class
2139 (op
, this_alternative
) == NO_REGS
))))
2141 if (lra_dump_file
!= NULL
)
2142 fprintf (lra_dump_file
,
2143 " %d Non-prefered reload: reject+=%d\n",
2144 nop
, LRA_MAX_REJECT
);
2145 reject
+= LRA_MAX_REJECT
;
2148 if (! (MEM_P (op
) && offmemok
)
2149 && ! (const_to_mem
&& constmemok
))
2151 /* We prefer to reload pseudos over reloading other
2152 things, since such reloads may be able to be
2153 eliminated later. So bump REJECT in other cases.
2154 Don't do this in the case where we are forcing a
2155 constant into memory and it will then win since
2156 we don't want to have a different alternative
2158 if (! (REG_P (op
) && REGNO (op
) >= FIRST_PSEUDO_REGISTER
))
2160 if (lra_dump_file
!= NULL
)
2163 " %d Non-pseudo reload: reject+=2\n",
2170 += ira_reg_class_max_nregs
[this_alternative
][mode
];
2172 if (SMALL_REGISTER_CLASS_P (this_alternative
))
2174 if (lra_dump_file
!= NULL
)
2177 " %d Small class reload: reject+=%d\n",
2178 nop
, LRA_LOSER_COST_FACTOR
/ 2);
2179 reject
+= LRA_LOSER_COST_FACTOR
/ 2;
2183 /* We are trying to spill pseudo into memory. It is
2184 usually more costly than moving to a hard register
2185 although it might takes the same number of
2187 if (no_regs_p
&& REG_P (op
) && hard_regno
[nop
] >= 0)
2189 if (lra_dump_file
!= NULL
)
2192 " %d Spill pseudo in memory: reject+=3\n",
2197 #ifdef SECONDARY_MEMORY_NEEDED
2198 /* If reload requires moving value through secondary
2199 memory, it will need one more insn at least. */
2200 if (this_alternative
!= NO_REGS
2201 && REG_P (op
) && (cl
= get_reg_class (REGNO (op
))) != NO_REGS
2202 && ((curr_static_id
->operand
[nop
].type
!= OP_OUT
2203 && SECONDARY_MEMORY_NEEDED (cl
, this_alternative
,
2205 || (curr_static_id
->operand
[nop
].type
!= OP_IN
2206 && SECONDARY_MEMORY_NEEDED (this_alternative
, cl
,
2210 /* Input reloads can be inherited more often than output
2211 reloads can be removed, so penalize output
2213 if (!REG_P (op
) || curr_static_id
->operand
[nop
].type
!= OP_IN
)
2215 if (lra_dump_file
!= NULL
)
2218 " %d Non input pseudo reload: reject++\n",
2224 if (early_clobber_p
&& ! scratch_p
)
2226 if (lra_dump_file
!= NULL
)
2227 fprintf (lra_dump_file
,
2228 " %d Early clobber: reject++\n", nop
);
2231 /* ??? We check early clobbers after processing all operands
2232 (see loop below) and there we update the costs more.
2233 Should we update the cost (may be approximately) here
2234 because of early clobber register reloads or it is a rare
2235 or non-important thing to be worth to do it. */
2236 overall
= losers
* LRA_LOSER_COST_FACTOR
+ reject
;
2237 if ((best_losers
== 0 || losers
!= 0) && best_overall
< overall
)
2239 if (lra_dump_file
!= NULL
)
2240 fprintf (lra_dump_file
,
2241 " alt=%d,overall=%d,losers=%d -- refuse\n",
2242 nalt
, overall
, losers
);
2246 curr_alt
[nop
] = this_alternative
;
2247 COPY_HARD_REG_SET (curr_alt_set
[nop
], this_alternative_set
);
2248 curr_alt_win
[nop
] = this_alternative_win
;
2249 curr_alt_match_win
[nop
] = this_alternative_match_win
;
2250 curr_alt_offmemok
[nop
] = this_alternative_offmemok
;
2251 curr_alt_matches
[nop
] = this_alternative_matches
;
2253 if (this_alternative_matches
>= 0
2254 && !did_match
&& !this_alternative_win
)
2255 curr_alt_win
[this_alternative_matches
] = false;
2257 if (early_clobber_p
&& operand_reg
[nop
] != NULL_RTX
)
2258 early_clobbered_nops
[early_clobbered_regs_num
++] = nop
;
2260 if (curr_insn_set
!= NULL_RTX
&& n_operands
== 2
2261 /* Prevent processing non-move insns. */
2262 && (GET_CODE (SET_SRC (curr_insn_set
)) == SUBREG
2263 || SET_SRC (curr_insn_set
) == no_subreg_reg_operand
[1])
2264 && ((! curr_alt_win
[0] && ! curr_alt_win
[1]
2265 && REG_P (no_subreg_reg_operand
[0])
2266 && REG_P (no_subreg_reg_operand
[1])
2267 && (reg_in_class_p (no_subreg_reg_operand
[0], curr_alt
[1])
2268 || reg_in_class_p (no_subreg_reg_operand
[1], curr_alt
[0])))
2269 || (! curr_alt_win
[0] && curr_alt_win
[1]
2270 && REG_P (no_subreg_reg_operand
[1])
2271 && reg_in_class_p (no_subreg_reg_operand
[1], curr_alt
[0]))
2272 || (curr_alt_win
[0] && ! curr_alt_win
[1]
2273 && REG_P (no_subreg_reg_operand
[0])
2274 && reg_in_class_p (no_subreg_reg_operand
[0], curr_alt
[1])
2275 && (! CONST_POOL_OK_P (curr_operand_mode
[1],
2276 no_subreg_reg_operand
[1])
2277 || (targetm
.preferred_reload_class
2278 (no_subreg_reg_operand
[1],
2279 (enum reg_class
) curr_alt
[1]) != NO_REGS
))
2280 /* If it is a result of recent elimination in move
2281 insn we can transform it into an add still by
2282 using this alternative. */
2283 && GET_CODE (no_subreg_reg_operand
[1]) != PLUS
)))
2285 /* We have a move insn and a new reload insn will be similar
2286 to the current insn. We should avoid such situation as it
2287 results in LRA cycling. */
2288 overall
+= LRA_MAX_REJECT
;
2291 curr_alt_dont_inherit_ops_num
= 0;
2292 for (nop
= 0; nop
< early_clobbered_regs_num
; nop
++)
2294 int i
, j
, clobbered_hard_regno
, first_conflict_j
, last_conflict_j
;
2295 HARD_REG_SET temp_set
;
2297 i
= early_clobbered_nops
[nop
];
2298 if ((! curr_alt_win
[i
] && ! curr_alt_match_win
[i
])
2299 || hard_regno
[i
] < 0)
2301 lra_assert (operand_reg
[i
] != NULL_RTX
);
2302 clobbered_hard_regno
= hard_regno
[i
];
2303 CLEAR_HARD_REG_SET (temp_set
);
2304 add_to_hard_reg_set (&temp_set
, biggest_mode
[i
], clobbered_hard_regno
);
2305 first_conflict_j
= last_conflict_j
= -1;
2306 for (j
= 0; j
< n_operands
; j
++)
2308 /* We don't want process insides of match_operator and
2309 match_parallel because otherwise we would process
2310 their operands once again generating a wrong
2312 || curr_static_id
->operand
[j
].is_operator
)
2314 else if ((curr_alt_matches
[j
] == i
&& curr_alt_match_win
[j
])
2315 || (curr_alt_matches
[i
] == j
&& curr_alt_match_win
[i
]))
2317 /* If we don't reload j-th operand, check conflicts. */
2318 else if ((curr_alt_win
[j
] || curr_alt_match_win
[j
])
2319 && uses_hard_regs_p (*curr_id
->operand_loc
[j
], temp_set
))
2321 if (first_conflict_j
< 0)
2322 first_conflict_j
= j
;
2323 last_conflict_j
= j
;
2325 if (last_conflict_j
< 0)
2327 /* If earlyclobber operand conflicts with another
2328 non-matching operand which is actually the same register
2329 as the earlyclobber operand, it is better to reload the
2330 another operand as an operand matching the earlyclobber
2331 operand can be also the same. */
2332 if (first_conflict_j
== last_conflict_j
2333 && operand_reg
[last_conflict_j
]
2334 != NULL_RTX
&& ! curr_alt_match_win
[last_conflict_j
]
2335 && REGNO (operand_reg
[i
]) == REGNO (operand_reg
[last_conflict_j
]))
2337 curr_alt_win
[last_conflict_j
] = false;
2338 curr_alt_dont_inherit_ops
[curr_alt_dont_inherit_ops_num
++]
2341 /* Early clobber was already reflected in REJECT. */
2342 lra_assert (reject
> 0);
2343 if (lra_dump_file
!= NULL
)
2346 " %d Conflict early clobber reload: reject--\n",
2349 overall
+= LRA_LOSER_COST_FACTOR
- 1;
2353 /* We need to reload early clobbered register and the
2354 matched registers. */
2355 for (j
= 0; j
< n_operands
; j
++)
2356 if (curr_alt_matches
[j
] == i
)
2358 curr_alt_match_win
[j
] = false;
2360 overall
+= LRA_LOSER_COST_FACTOR
;
2362 if (! curr_alt_match_win
[i
])
2363 curr_alt_dont_inherit_ops
[curr_alt_dont_inherit_ops_num
++] = i
;
2366 /* Remember pseudos used for match reloads are never
2368 lra_assert (curr_alt_matches
[i
] >= 0);
2369 curr_alt_win
[curr_alt_matches
[i
]] = false;
2371 curr_alt_win
[i
] = curr_alt_match_win
[i
] = false;
2373 /* Early clobber was already reflected in REJECT. */
2374 lra_assert (reject
> 0);
2375 if (lra_dump_file
!= NULL
)
2378 " %d Matched conflict early clobber reloads:"
2382 overall
+= LRA_LOSER_COST_FACTOR
- 1;
2385 if (lra_dump_file
!= NULL
)
2386 fprintf (lra_dump_file
, " alt=%d,overall=%d,losers=%d,rld_nregs=%d\n",
2387 nalt
, overall
, losers
, reload_nregs
);
2389 /* If this alternative can be made to work by reloading, and it
2390 needs less reloading than the others checked so far, record
2391 it as the chosen goal for reloading. */
2392 if ((best_losers
!= 0 && losers
== 0)
2393 || (((best_losers
== 0 && losers
== 0)
2394 || (best_losers
!= 0 && losers
!= 0))
2395 && (best_overall
> overall
2396 || (best_overall
== overall
2397 /* If the cost of the reloads is the same,
2398 prefer alternative which requires minimal
2399 number of reload regs. */
2400 && (reload_nregs
< best_reload_nregs
2401 || (reload_nregs
== best_reload_nregs
2402 && (best_reload_sum
< reload_sum
2403 || (best_reload_sum
== reload_sum
2404 && nalt
< goal_alt_number
))))))))
2406 for (nop
= 0; nop
< n_operands
; nop
++)
2408 goal_alt_win
[nop
] = curr_alt_win
[nop
];
2409 goal_alt_match_win
[nop
] = curr_alt_match_win
[nop
];
2410 goal_alt_matches
[nop
] = curr_alt_matches
[nop
];
2411 goal_alt
[nop
] = curr_alt
[nop
];
2412 goal_alt_offmemok
[nop
] = curr_alt_offmemok
[nop
];
2414 goal_alt_dont_inherit_ops_num
= curr_alt_dont_inherit_ops_num
;
2415 for (nop
= 0; nop
< curr_alt_dont_inherit_ops_num
; nop
++)
2416 goal_alt_dont_inherit_ops
[nop
] = curr_alt_dont_inherit_ops
[nop
];
2417 goal_alt_swapped
= curr_swapped
;
2418 best_overall
= overall
;
2419 best_losers
= losers
;
2420 best_reload_nregs
= reload_nregs
;
2421 best_reload_sum
= reload_sum
;
2422 goal_alt_number
= nalt
;
2425 /* Everything is satisfied. Do not process alternatives
2434 /* Return 1 if ADDR is a valid memory address for mode MODE in address
2435 space AS, and check that each pseudo has the proper kind of hard
2438 valid_address_p (enum machine_mode mode ATTRIBUTE_UNUSED
,
2439 rtx addr
, addr_space_t as
)
2441 #ifdef GO_IF_LEGITIMATE_ADDRESS
2442 lra_assert (ADDR_SPACE_GENERIC_P (as
));
2443 GO_IF_LEGITIMATE_ADDRESS (mode
, addr
, win
);
2449 return targetm
.addr_space
.legitimate_address_p (mode
, addr
, 0, as
);
2453 /* Return whether address AD is valid. */
2456 valid_address_p (struct address_info
*ad
)
2458 /* Some ports do not check displacements for eliminable registers,
2459 so we replace them temporarily with the elimination target. */
2460 rtx saved_base_reg
= NULL_RTX
;
2461 rtx saved_index_reg
= NULL_RTX
;
2462 rtx
*base_term
= strip_subreg (ad
->base_term
);
2463 rtx
*index_term
= strip_subreg (ad
->index_term
);
2464 if (base_term
!= NULL
)
2466 saved_base_reg
= *base_term
;
2467 lra_eliminate_reg_if_possible (base_term
);
2468 if (ad
->base_term2
!= NULL
)
2469 *ad
->base_term2
= *ad
->base_term
;
2471 if (index_term
!= NULL
)
2473 saved_index_reg
= *index_term
;
2474 lra_eliminate_reg_if_possible (index_term
);
2476 bool ok_p
= valid_address_p (ad
->mode
, *ad
->outer
, ad
->as
);
2477 if (saved_base_reg
!= NULL_RTX
)
2479 *base_term
= saved_base_reg
;
2480 if (ad
->base_term2
!= NULL
)
2481 *ad
->base_term2
= *ad
->base_term
;
2483 if (saved_index_reg
!= NULL_RTX
)
2484 *index_term
= saved_index_reg
;
2488 /* Make reload base reg + disp from address AD. Return the new pseudo. */
2490 base_plus_disp_to_reg (struct address_info
*ad
)
2495 lra_assert (ad
->base
== ad
->base_term
&& ad
->disp
== ad
->disp_term
);
2496 cl
= base_reg_class (ad
->mode
, ad
->as
, ad
->base_outer_code
,
2497 get_index_code (ad
));
2498 new_reg
= lra_create_new_reg (GET_MODE (*ad
->base_term
), NULL_RTX
,
2500 lra_emit_add (new_reg
, *ad
->base_term
, *ad
->disp_term
);
2504 /* Return true if we can add a displacement to address AD, even if that
2505 makes the address invalid. The fix-up code requires any new address
2506 to be the sum of the BASE_TERM, INDEX and DISP_TERM fields. */
2508 can_add_disp_p (struct address_info
*ad
)
2510 return (!ad
->autoinc_p
2511 && ad
->segment
== NULL
2512 && ad
->base
== ad
->base_term
2513 && ad
->disp
== ad
->disp_term
);
2516 /* Make equiv substitution in address AD. Return true if a substitution
2519 equiv_address_substitution (struct address_info
*ad
)
2521 rtx base_reg
, new_base_reg
, index_reg
, new_index_reg
, *base_term
, *index_term
;
2522 HOST_WIDE_INT disp
, scale
;
2525 base_term
= strip_subreg (ad
->base_term
);
2526 if (base_term
== NULL
)
2527 base_reg
= new_base_reg
= NULL_RTX
;
2530 base_reg
= *base_term
;
2531 new_base_reg
= get_equiv_substitution (base_reg
);
2533 index_term
= strip_subreg (ad
->index_term
);
2534 if (index_term
== NULL
)
2535 index_reg
= new_index_reg
= NULL_RTX
;
2538 index_reg
= *index_term
;
2539 new_index_reg
= get_equiv_substitution (index_reg
);
2541 if (base_reg
== new_base_reg
&& index_reg
== new_index_reg
)
2545 if (lra_dump_file
!= NULL
)
2547 fprintf (lra_dump_file
, "Changing address in insn %d ",
2548 INSN_UID (curr_insn
));
2549 dump_value_slim (lra_dump_file
, *ad
->outer
, 1);
2551 if (base_reg
!= new_base_reg
)
2553 if (REG_P (new_base_reg
))
2555 *base_term
= new_base_reg
;
2558 else if (GET_CODE (new_base_reg
) == PLUS
2559 && REG_P (XEXP (new_base_reg
, 0))
2560 && CONST_INT_P (XEXP (new_base_reg
, 1))
2561 && can_add_disp_p (ad
))
2563 disp
+= INTVAL (XEXP (new_base_reg
, 1));
2564 *base_term
= XEXP (new_base_reg
, 0);
2567 if (ad
->base_term2
!= NULL
)
2568 *ad
->base_term2
= *ad
->base_term
;
2570 if (index_reg
!= new_index_reg
)
2572 if (REG_P (new_index_reg
))
2574 *index_term
= new_index_reg
;
2577 else if (GET_CODE (new_index_reg
) == PLUS
2578 && REG_P (XEXP (new_index_reg
, 0))
2579 && CONST_INT_P (XEXP (new_index_reg
, 1))
2580 && can_add_disp_p (ad
)
2581 && (scale
= get_index_scale (ad
)))
2583 disp
+= INTVAL (XEXP (new_index_reg
, 1)) * scale
;
2584 *index_term
= XEXP (new_index_reg
, 0);
2590 if (ad
->disp
!= NULL
)
2591 *ad
->disp
= plus_constant (GET_MODE (*ad
->inner
), *ad
->disp
, disp
);
2594 *ad
->inner
= plus_constant (GET_MODE (*ad
->inner
), *ad
->inner
, disp
);
2595 update_address (ad
);
2599 if (lra_dump_file
!= NULL
)
2602 fprintf (lra_dump_file
, " -- no change\n");
2605 fprintf (lra_dump_file
, " on equiv ");
2606 dump_value_slim (lra_dump_file
, *ad
->outer
, 1);
2607 fprintf (lra_dump_file
, "\n");
2613 /* Major function to make reloads for an address in operand NOP.
2614 The supported cases are:
2616 1) an address that existed before LRA started, at which point it
2617 must have been valid. These addresses are subject to elimination
2618 and may have become invalid due to the elimination offset being out
2621 2) an address created by forcing a constant to memory
2622 (force_const_to_mem). The initial form of these addresses might
2623 not be valid, and it is this function's job to make them valid.
2625 3) a frame address formed from a register and a (possibly zero)
2626 constant offset. As above, these addresses might not be valid and
2627 this function must make them so.
2629 Add reloads to the lists *BEFORE and *AFTER. We might need to add
2630 reloads to *AFTER because of inc/dec, {pre, post} modify in the
2631 address. Return true for any RTL change. */
2633 process_address (int nop
, rtx
*before
, rtx
*after
)
2635 struct address_info ad
;
2637 rtx op
= *curr_id
->operand_loc
[nop
];
2638 const char *constraint
= curr_static_id
->operand
[nop
].constraint
;
2641 if (constraint
[0] == 'p'
2642 || EXTRA_ADDRESS_CONSTRAINT (constraint
[0], constraint
))
2643 decompose_lea_address (&ad
, curr_id
->operand_loc
[nop
]);
2644 else if (MEM_P (op
))
2645 decompose_mem_address (&ad
, op
);
2646 else if (GET_CODE (op
) == SUBREG
2647 && MEM_P (SUBREG_REG (op
)))
2648 decompose_mem_address (&ad
, SUBREG_REG (op
));
2651 change_p
= equiv_address_substitution (&ad
);
2652 if (ad
.base_term
!= NULL
2653 && (process_addr_reg
2654 (ad
.base_term
, before
,
2656 && !(REG_P (*ad
.base_term
)
2657 && find_regno_note (curr_insn
, REG_DEAD
,
2658 REGNO (*ad
.base_term
)) != NULL_RTX
)
2660 base_reg_class (ad
.mode
, ad
.as
, ad
.base_outer_code
,
2661 get_index_code (&ad
)))))
2664 if (ad
.base_term2
!= NULL
)
2665 *ad
.base_term2
= *ad
.base_term
;
2667 if (ad
.index_term
!= NULL
2668 && process_addr_reg (ad
.index_term
, before
, NULL
, INDEX_REG_CLASS
))
2671 #ifdef EXTRA_CONSTRAINT_STR
2672 /* Target hooks sometimes reject extra constraint addresses -- use
2673 EXTRA_CONSTRAINT_STR for the validation. */
2674 if (constraint
[0] != 'p'
2675 && EXTRA_ADDRESS_CONSTRAINT (constraint
[0], constraint
)
2676 && EXTRA_CONSTRAINT_STR (op
, constraint
[0], constraint
))
2680 /* There are three cases where the shape of *AD.INNER may now be invalid:
2682 1) the original address was valid, but either elimination or
2683 equiv_address_substitution was applied and that made
2684 the address invalid.
2686 2) the address is an invalid symbolic address created by
2689 3) the address is a frame address with an invalid offset.
2691 All these cases involve a non-autoinc address, so there is no
2692 point revalidating other types. */
2693 if (ad
.autoinc_p
|| valid_address_p (&ad
))
2696 /* Any index existed before LRA started, so we can assume that the
2697 presence and shape of the index is valid. */
2698 push_to_sequence (*before
);
2699 lra_assert (ad
.disp
== ad
.disp_term
);
2700 if (ad
.base
== NULL
)
2702 if (ad
.index
== NULL
)
2705 enum reg_class cl
= base_reg_class (ad
.mode
, ad
.as
,
2707 rtx addr
= *ad
.inner
;
2709 new_reg
= lra_create_new_reg (Pmode
, NULL_RTX
, cl
, "addr");
2713 rtx last
= get_last_insn ();
2715 /* addr => lo_sum (new_base, addr), case (2) above. */
2716 insn
= emit_insn (gen_rtx_SET
2718 gen_rtx_HIGH (Pmode
, copy_rtx (addr
))));
2719 code
= recog_memoized (insn
);
2722 *ad
.inner
= gen_rtx_LO_SUM (Pmode
, new_reg
, addr
);
2723 if (! valid_address_p (ad
.mode
, *ad
.outer
, ad
.as
))
2725 /* Try to put lo_sum into register. */
2726 insn
= emit_insn (gen_rtx_SET
2728 gen_rtx_LO_SUM (Pmode
, new_reg
, addr
)));
2729 code
= recog_memoized (insn
);
2732 *ad
.inner
= new_reg
;
2733 if (! valid_address_p (ad
.mode
, *ad
.outer
, ad
.as
))
2743 delete_insns_since (last
);
2748 /* addr => new_base, case (2) above. */
2749 lra_emit_move (new_reg
, addr
);
2750 *ad
.inner
= new_reg
;
2755 /* index * scale + disp => new base + index * scale,
2757 enum reg_class cl
= base_reg_class (ad
.mode
, ad
.as
, PLUS
,
2758 GET_CODE (*ad
.index
));
2760 lra_assert (INDEX_REG_CLASS
!= NO_REGS
);
2761 new_reg
= lra_create_new_reg (Pmode
, NULL_RTX
, cl
, "disp");
2762 lra_emit_move (new_reg
, *ad
.disp
);
2763 *ad
.inner
= simplify_gen_binary (PLUS
, GET_MODE (new_reg
),
2764 new_reg
, *ad
.index
);
2767 else if (ad
.index
== NULL
)
2771 rtx set
, insns
, last_insn
;
2772 /* base + disp => new base, cases (1) and (3) above. */
2773 /* Another option would be to reload the displacement into an
2774 index register. However, postreload has code to optimize
2775 address reloads that have the same base and different
2776 displacements, so reloading into an index register would
2777 not necessarily be a win. */
2779 new_reg
= base_plus_disp_to_reg (&ad
);
2780 insns
= get_insns ();
2781 last_insn
= get_last_insn ();
2782 /* If we generated at least two insns, try last insn source as
2783 an address. If we succeed, we generate one less insn. */
2784 if (last_insn
!= insns
&& (set
= single_set (last_insn
)) != NULL_RTX
2785 && GET_CODE (SET_SRC (set
)) == PLUS
2786 && REG_P (XEXP (SET_SRC (set
), 0))
2787 && CONSTANT_P (XEXP (SET_SRC (set
), 1)))
2789 *ad
.inner
= SET_SRC (set
);
2790 if (valid_address_p (ad
.mode
, *ad
.outer
, ad
.as
))
2792 *ad
.base_term
= XEXP (SET_SRC (set
), 0);
2793 *ad
.disp_term
= XEXP (SET_SRC (set
), 1);
2794 cl
= base_reg_class (ad
.mode
, ad
.as
, ad
.base_outer_code
,
2795 get_index_code (&ad
));
2796 regno
= REGNO (*ad
.base_term
);
2797 if (regno
>= FIRST_PSEUDO_REGISTER
2798 && cl
!= lra_get_allocno_class (regno
))
2799 change_class (regno
, cl
, " Change", true);
2800 new_reg
= SET_SRC (set
);
2801 delete_insns_since (PREV_INSN (last_insn
));
2806 *ad
.inner
= new_reg
;
2810 /* base + scale * index + disp => new base + scale * index,
2812 new_reg
= base_plus_disp_to_reg (&ad
);
2813 *ad
.inner
= simplify_gen_binary (PLUS
, GET_MODE (new_reg
),
2814 new_reg
, *ad
.index
);
2816 *before
= get_insns ();
2821 /* Emit insns to reload VALUE into a new register. VALUE is an
2822 auto-increment or auto-decrement RTX whose operand is a register or
2823 memory location; so reloading involves incrementing that location.
2824 IN is either identical to VALUE, or some cheaper place to reload
2825 value being incremented/decremented from.
2827 INC_AMOUNT is the number to increment or decrement by (always
2828 positive and ignored for POST_MODIFY/PRE_MODIFY).
2830 Return pseudo containing the result. */
2832 emit_inc (enum reg_class new_rclass
, rtx in
, rtx value
, int inc_amount
)
2834 /* REG or MEM to be copied and incremented. */
2835 rtx incloc
= XEXP (value
, 0);
2836 /* Nonzero if increment after copying. */
2837 int post
= (GET_CODE (value
) == POST_DEC
|| GET_CODE (value
) == POST_INC
2838 || GET_CODE (value
) == POST_MODIFY
);
2843 rtx real_in
= in
== value
? incloc
: in
;
2847 if (GET_CODE (value
) == PRE_MODIFY
|| GET_CODE (value
) == POST_MODIFY
)
2849 lra_assert (GET_CODE (XEXP (value
, 1)) == PLUS
2850 || GET_CODE (XEXP (value
, 1)) == MINUS
);
2851 lra_assert (rtx_equal_p (XEXP (XEXP (value
, 1), 0), XEXP (value
, 0)));
2852 plus_p
= GET_CODE (XEXP (value
, 1)) == PLUS
;
2853 inc
= XEXP (XEXP (value
, 1), 1);
2857 if (GET_CODE (value
) == PRE_DEC
|| GET_CODE (value
) == POST_DEC
)
2858 inc_amount
= -inc_amount
;
2860 inc
= GEN_INT (inc_amount
);
2863 if (! post
&& REG_P (incloc
))
2866 result
= lra_create_new_reg (GET_MODE (value
), value
, new_rclass
,
2869 if (real_in
!= result
)
2871 /* First copy the location to the result register. */
2872 lra_assert (REG_P (result
));
2873 emit_insn (gen_move_insn (result
, real_in
));
2876 /* We suppose that there are insns to add/sub with the constant
2877 increment permitted in {PRE/POST)_{DEC/INC/MODIFY}. At least the
2878 old reload worked with this assumption. If the assumption
2879 becomes wrong, we should use approach in function
2880 base_plus_disp_to_reg. */
2883 /* See if we can directly increment INCLOC. */
2884 last
= get_last_insn ();
2885 add_insn
= emit_insn (plus_p
2886 ? gen_add2_insn (incloc
, inc
)
2887 : gen_sub2_insn (incloc
, inc
));
2889 code
= recog_memoized (add_insn
);
2892 if (! post
&& result
!= incloc
)
2893 emit_insn (gen_move_insn (result
, incloc
));
2896 delete_insns_since (last
);
2899 /* If couldn't do the increment directly, must increment in RESULT.
2900 The way we do this depends on whether this is pre- or
2901 post-increment. For pre-increment, copy INCLOC to the reload
2902 register, increment it there, then save back. */
2905 if (real_in
!= result
)
2906 emit_insn (gen_move_insn (result
, real_in
));
2908 emit_insn (gen_add2_insn (result
, inc
));
2910 emit_insn (gen_sub2_insn (result
, inc
));
2911 if (result
!= incloc
)
2912 emit_insn (gen_move_insn (incloc
, result
));
2918 Because this might be a jump insn or a compare, and because
2919 RESULT may not be available after the insn in an input
2920 reload, we must do the incrementing before the insn being
2923 We have already copied IN to RESULT. Increment the copy in
2924 RESULT, save that back, then decrement RESULT so it has
2925 the original value. */
2927 emit_insn (gen_add2_insn (result
, inc
));
2929 emit_insn (gen_sub2_insn (result
, inc
));
2930 emit_insn (gen_move_insn (incloc
, result
));
2931 /* Restore non-modified value for the result. We prefer this
2932 way because it does not require an additional hard
2936 if (CONST_INT_P (inc
))
2937 emit_insn (gen_add2_insn (result
,
2938 gen_int_mode (-INTVAL (inc
),
2939 GET_MODE (result
))));
2941 emit_insn (gen_sub2_insn (result
, inc
));
2944 emit_insn (gen_add2_insn (result
, inc
));
2949 /* Return true if the current move insn does not need processing as we
2950 already know that it satisfies its constraints. */
2952 simple_move_p (void)
2955 enum reg_class dclass
, sclass
;
2957 lra_assert (curr_insn_set
!= NULL_RTX
);
2958 dest
= SET_DEST (curr_insn_set
);
2959 src
= SET_SRC (curr_insn_set
);
2960 return ((dclass
= get_op_class (dest
)) != NO_REGS
2961 && (sclass
= get_op_class (src
)) != NO_REGS
2962 /* The backend guarantees that register moves of cost 2
2963 never need reloads. */
2964 && targetm
.register_move_cost (GET_MODE (src
), dclass
, sclass
) == 2);
2967 /* Swap operands NOP and NOP + 1. */
2969 swap_operands (int nop
)
2971 enum machine_mode mode
= curr_operand_mode
[nop
];
2972 curr_operand_mode
[nop
] = curr_operand_mode
[nop
+ 1];
2973 curr_operand_mode
[nop
+ 1] = mode
;
2974 rtx x
= *curr_id
->operand_loc
[nop
];
2975 *curr_id
->operand_loc
[nop
] = *curr_id
->operand_loc
[nop
+ 1];
2976 *curr_id
->operand_loc
[nop
+ 1] = x
;
2977 /* Swap the duplicates too. */
2978 lra_update_dup (curr_id
, nop
);
2979 lra_update_dup (curr_id
, nop
+ 1);
2982 /* Main entry point of the constraint code: search the body of the
2983 current insn to choose the best alternative. It is mimicking insn
2984 alternative cost calculation model of former reload pass. That is
2985 because machine descriptions were written to use this model. This
2986 model can be changed in future. Make commutative operand exchange
2989 Return true if some RTL changes happened during function call. */
2991 curr_insn_transform (void)
2997 signed char goal_alt_matched
[MAX_RECOG_OPERANDS
][MAX_RECOG_OPERANDS
];
2998 signed char match_inputs
[MAX_RECOG_OPERANDS
+ 1];
3001 /* Flag that the insn has been changed through a transformation. */
3004 #ifdef SECONDARY_MEMORY_NEEDED
3007 int max_regno_before
;
3008 int reused_alternative_num
;
3010 curr_insn_set
= single_set (curr_insn
);
3011 if (curr_insn_set
!= NULL_RTX
&& simple_move_p ())
3014 no_input_reloads_p
= no_output_reloads_p
= false;
3015 goal_alt_number
= -1;
3016 change_p
= sec_mem_p
= false;
3017 /* JUMP_INSNs and CALL_INSNs are not allowed to have any output
3018 reloads; neither are insns that SET cc0. Insns that use CC0 are
3019 not allowed to have any input reloads. */
3020 if (JUMP_P (curr_insn
) || CALL_P (curr_insn
))
3021 no_output_reloads_p
= true;
3024 if (reg_referenced_p (cc0_rtx
, PATTERN (curr_insn
)))
3025 no_input_reloads_p
= true;
3026 if (reg_set_p (cc0_rtx
, PATTERN (curr_insn
)))
3027 no_output_reloads_p
= true;
3030 n_operands
= curr_static_id
->n_operands
;
3031 n_alternatives
= curr_static_id
->n_alternatives
;
3033 /* Just return "no reloads" if insn has no operands with
3035 if (n_operands
== 0 || n_alternatives
== 0)
3038 max_regno_before
= max_reg_num ();
3040 for (i
= 0; i
< n_operands
; i
++)
3042 goal_alt_matched
[i
][0] = -1;
3043 goal_alt_matches
[i
] = -1;
3046 commutative
= curr_static_id
->commutative
;
3048 /* Now see what we need for pseudos that didn't get hard regs or got
3049 the wrong kind of hard reg. For this, we must consider all the
3050 operands together against the register constraints. */
3052 best_losers
= best_overall
= INT_MAX
;
3053 best_reload_sum
= 0;
3055 curr_swapped
= false;
3056 goal_alt_swapped
= false;
3058 /* Make equivalence substitution and memory subreg elimination
3059 before address processing because an address legitimacy can
3060 depend on memory mode. */
3061 for (i
= 0; i
< n_operands
; i
++)
3063 rtx op
= *curr_id
->operand_loc
[i
];
3064 rtx subst
, old
= op
;
3065 bool op_change_p
= false;
3067 if (GET_CODE (old
) == SUBREG
)
3068 old
= SUBREG_REG (old
);
3069 subst
= get_equiv_substitution (old
);
3072 subst
= copy_rtx (subst
);
3073 lra_assert (REG_P (old
));
3074 if (GET_CODE (op
) == SUBREG
)
3075 SUBREG_REG (op
) = subst
;
3077 *curr_id
->operand_loc
[i
] = subst
;
3078 if (lra_dump_file
!= NULL
)
3080 fprintf (lra_dump_file
,
3081 "Changing pseudo %d in operand %i of insn %u on equiv ",
3082 REGNO (old
), i
, INSN_UID (curr_insn
));
3083 dump_value_slim (lra_dump_file
, subst
, 1);
3084 fprintf (lra_dump_file
, "\n");
3086 op_change_p
= change_p
= true;
3088 if (simplify_operand_subreg (i
, GET_MODE (old
)) || op_change_p
)
3091 lra_update_dup (curr_id
, i
);
3095 /* Reload address registers and displacements. We do it before
3096 finding an alternative because of memory constraints. */
3097 before
= after
= NULL_RTX
;
3098 for (i
= 0; i
< n_operands
; i
++)
3099 if (! curr_static_id
->operand
[i
].is_operator
3100 && process_address (i
, &before
, &after
))
3103 lra_update_dup (curr_id
, i
);
3107 /* If we've changed the instruction then any alternative that
3108 we chose previously may no longer be valid. */
3109 lra_set_used_insn_alternative (curr_insn
, -1);
3111 if (curr_insn_set
!= NULL_RTX
3112 && check_and_process_move (&change_p
, &sec_mem_p
))
3117 reused_alternative_num
= curr_id
->used_insn_alternative
;
3118 if (lra_dump_file
!= NULL
&& reused_alternative_num
>= 0)
3119 fprintf (lra_dump_file
, "Reusing alternative %d for insn #%u\n",
3120 reused_alternative_num
, INSN_UID (curr_insn
));
3122 if (process_alt_operands (reused_alternative_num
))
3125 /* If insn is commutative (it's safe to exchange a certain pair of
3126 operands) then we need to try each alternative twice, the second
3127 time matching those two operands as if we had exchanged them. To
3128 do this, really exchange them in operands.
3130 If we have just tried the alternatives the second time, return
3131 operands to normal and drop through. */
3133 if (reused_alternative_num
< 0 && commutative
>= 0)
3135 curr_swapped
= !curr_swapped
;
3138 swap_operands (commutative
);
3142 swap_operands (commutative
);
3145 if (! alt_p
&& ! sec_mem_p
)
3147 /* No alternative works with reloads?? */
3148 if (INSN_CODE (curr_insn
) >= 0)
3149 fatal_insn ("unable to generate reloads for:", curr_insn
);
3150 error_for_asm (curr_insn
,
3151 "inconsistent operand constraints in an %<asm%>");
3152 /* Avoid further trouble with this insn. */
3153 PATTERN (curr_insn
) = gen_rtx_USE (VOIDmode
, const0_rtx
);
3154 lra_invalidate_insn_data (curr_insn
);
3158 /* If the best alternative is with operands 1 and 2 swapped, swap
3159 them. Update the operand numbers of any reloads already
3162 if (goal_alt_swapped
)
3164 if (lra_dump_file
!= NULL
)
3165 fprintf (lra_dump_file
, " Commutative operand exchange in insn %u\n",
3166 INSN_UID (curr_insn
));
3168 /* Swap the duplicates too. */
3169 swap_operands (commutative
);
3173 #ifdef SECONDARY_MEMORY_NEEDED
3174 /* Some target macros SECONDARY_MEMORY_NEEDED (e.g. x86) are defined
3175 too conservatively. So we use the secondary memory only if there
3176 is no any alternative without reloads. */
3177 use_sec_mem_p
= false;
3179 use_sec_mem_p
= true;
3182 for (i
= 0; i
< n_operands
; i
++)
3183 if (! goal_alt_win
[i
] && ! goal_alt_match_win
[i
])
3185 use_sec_mem_p
= i
< n_operands
;
3190 rtx new_reg
, src
, dest
, rld
;
3191 enum machine_mode sec_mode
, rld_mode
;
3193 lra_assert (sec_mem_p
);
3194 lra_assert (curr_static_id
->operand
[0].type
== OP_OUT
3195 && curr_static_id
->operand
[1].type
== OP_IN
);
3196 dest
= *curr_id
->operand_loc
[0];
3197 src
= *curr_id
->operand_loc
[1];
3198 rld
= (GET_MODE_SIZE (GET_MODE (dest
)) <= GET_MODE_SIZE (GET_MODE (src
))
3200 rld_mode
= GET_MODE (rld
);
3201 #ifdef SECONDARY_MEMORY_NEEDED_MODE
3202 sec_mode
= SECONDARY_MEMORY_NEEDED_MODE (rld_mode
);
3204 sec_mode
= rld_mode
;
3206 new_reg
= lra_create_new_reg (sec_mode
, NULL_RTX
,
3207 NO_REGS
, "secondary");
3208 /* If the mode is changed, it should be wider. */
3209 lra_assert (GET_MODE_SIZE (sec_mode
) >= GET_MODE_SIZE (rld_mode
));
3210 if (sec_mode
!= rld_mode
)
3212 /* If the target says specifically to use another mode for
3213 secondary memory moves we can not reuse the original
3215 after
= emit_spill_move (false, new_reg
, dest
);
3216 lra_process_new_insns (curr_insn
, NULL_RTX
, after
,
3217 "Inserting the sec. move");
3218 /* We may have non null BEFORE here (e.g. after address
3220 push_to_sequence (before
);
3221 before
= emit_spill_move (true, new_reg
, src
);
3223 before
= get_insns ();
3225 lra_process_new_insns (curr_insn
, before
, NULL_RTX
, "Changing on");
3226 lra_set_insn_deleted (curr_insn
);
3228 else if (dest
== rld
)
3230 *curr_id
->operand_loc
[0] = new_reg
;
3231 after
= emit_spill_move (false, new_reg
, dest
);
3232 lra_process_new_insns (curr_insn
, NULL_RTX
, after
,
3233 "Inserting the sec. move");
3237 *curr_id
->operand_loc
[1] = new_reg
;
3238 /* See comments above. */
3239 push_to_sequence (before
);
3240 before
= emit_spill_move (true, new_reg
, src
);
3242 before
= get_insns ();
3244 lra_process_new_insns (curr_insn
, before
, NULL_RTX
,
3245 "Inserting the sec. move");
3247 lra_update_insn_regno_info (curr_insn
);
3252 lra_assert (goal_alt_number
>= 0);
3253 lra_set_used_insn_alternative (curr_insn
, goal_alt_number
);
3255 if (lra_dump_file
!= NULL
)
3259 fprintf (lra_dump_file
, " Choosing alt %d in insn %u:",
3260 goal_alt_number
, INSN_UID (curr_insn
));
3261 for (i
= 0; i
< n_operands
; i
++)
3263 p
= (curr_static_id
->operand_alternative
3264 [goal_alt_number
* n_operands
+ i
].constraint
);
3267 fprintf (lra_dump_file
, " (%d) ", i
);
3268 for (; *p
!= '\0' && *p
!= ',' && *p
!= '#'; p
++)
3269 fputc (*p
, lra_dump_file
);
3271 if (INSN_CODE (curr_insn
) >= 0
3272 && (p
= get_insn_name (INSN_CODE (curr_insn
))) != NULL
)
3273 fprintf (lra_dump_file
, " {%s}", p
);
3274 fprintf (lra_dump_file
, "\n");
3277 /* Right now, for any pair of operands I and J that are required to
3278 match, with J < I, goal_alt_matches[I] is J. Add I to
3279 goal_alt_matched[J]. */
3281 for (i
= 0; i
< n_operands
; i
++)
3282 if ((j
= goal_alt_matches
[i
]) >= 0)
3284 for (k
= 0; goal_alt_matched
[j
][k
] >= 0; k
++)
3286 /* We allow matching one output operand and several input
3289 || (curr_static_id
->operand
[j
].type
== OP_OUT
3290 && curr_static_id
->operand
[i
].type
== OP_IN
3291 && (curr_static_id
->operand
3292 [goal_alt_matched
[j
][0]].type
== OP_IN
)));
3293 goal_alt_matched
[j
][k
] = i
;
3294 goal_alt_matched
[j
][k
+ 1] = -1;
3297 for (i
= 0; i
< n_operands
; i
++)
3298 goal_alt_win
[i
] |= goal_alt_match_win
[i
];
3300 /* Any constants that aren't allowed and can't be reloaded into
3301 registers are here changed into memory references. */
3302 for (i
= 0; i
< n_operands
; i
++)
3303 if (goal_alt_win
[i
])
3306 enum reg_class new_class
;
3307 rtx reg
= *curr_id
->operand_loc
[i
];
3309 if (GET_CODE (reg
) == SUBREG
)
3310 reg
= SUBREG_REG (reg
);
3312 if (REG_P (reg
) && (regno
= REGNO (reg
)) >= FIRST_PSEUDO_REGISTER
)
3314 bool ok_p
= in_class_p (reg
, goal_alt
[i
], &new_class
);
3316 if (new_class
!= NO_REGS
&& get_reg_class (regno
) != new_class
)
3319 change_class (regno
, new_class
, " Change", true);
3325 const char *constraint
;
3327 rtx op
= *curr_id
->operand_loc
[i
];
3328 rtx subreg
= NULL_RTX
;
3329 enum machine_mode mode
= curr_operand_mode
[i
];
3331 if (GET_CODE (op
) == SUBREG
)
3334 op
= SUBREG_REG (op
);
3335 mode
= GET_MODE (op
);
3338 if (CONST_POOL_OK_P (mode
, op
)
3339 && ((targetm
.preferred_reload_class
3340 (op
, (enum reg_class
) goal_alt
[i
]) == NO_REGS
)
3341 || no_input_reloads_p
))
3343 rtx tem
= force_const_mem (mode
, op
);
3346 if (subreg
!= NULL_RTX
)
3347 tem
= gen_rtx_SUBREG (mode
, tem
, SUBREG_BYTE (subreg
));
3349 *curr_id
->operand_loc
[i
] = tem
;
3350 lra_update_dup (curr_id
, i
);
3351 process_address (i
, &before
, &after
);
3353 /* If the alternative accepts constant pool refs directly
3354 there will be no reload needed at all. */
3355 if (subreg
!= NULL_RTX
)
3357 /* Skip alternatives before the one requested. */
3358 constraint
= (curr_static_id
->operand_alternative
3359 [goal_alt_number
* n_operands
+ i
].constraint
);
3361 (c
= *constraint
) && c
!= ',' && c
!= '#';
3362 constraint
+= CONSTRAINT_LEN (c
, constraint
))
3364 if (c
== TARGET_MEM_CONSTRAINT
|| c
== 'o')
3366 #ifdef EXTRA_CONSTRAINT_STR
3367 if (EXTRA_MEMORY_CONSTRAINT (c
, constraint
)
3368 && EXTRA_CONSTRAINT_STR (tem
, c
, constraint
))
3372 if (c
== '\0' || c
== ',' || c
== '#')
3375 goal_alt_win
[i
] = true;
3379 for (i
= 0; i
< n_operands
; i
++)
3382 bool optional_p
= false;
3384 rtx op
= *curr_id
->operand_loc
[i
];
3386 if (goal_alt_win
[i
])
3388 if (goal_alt
[i
] == NO_REGS
3390 /* When we assign NO_REGS it means that we will not
3391 assign a hard register to the scratch pseudo by
3392 assigment pass and the scratch pseudo will be
3393 spilled. Spilled scratch pseudos are transformed
3394 back to scratches at the LRA end. */
3395 && lra_former_scratch_operand_p (curr_insn
, i
))
3397 int regno
= REGNO (op
);
3398 change_class (regno
, NO_REGS
, " Change", true);
3399 if (lra_get_regno_hard_regno (regno
) >= 0)
3400 /* We don't have to mark all insn affected by the
3401 spilled pseudo as there is only one such insn, the
3403 reg_renumber
[regno
] = -1;
3405 /* We can do an optional reload. If the pseudo got a hard
3406 reg, we might improve the code through inheritance. If
3407 it does not get a hard register we coalesce memory/memory
3408 moves later. Ignore move insns to avoid cycling. */
3410 && lra_undo_inheritance_iter
< LRA_MAX_INHERITANCE_PASSES
3411 && goal_alt
[i
] != NO_REGS
&& REG_P (op
)
3412 && (regno
= REGNO (op
)) >= FIRST_PSEUDO_REGISTER
3413 && ! lra_former_scratch_p (regno
)
3414 && reg_renumber
[regno
] < 0
3415 && (curr_insn_set
== NULL_RTX
3416 || !((REG_P (SET_SRC (curr_insn_set
))
3417 || MEM_P (SET_SRC (curr_insn_set
))
3418 || GET_CODE (SET_SRC (curr_insn_set
)) == SUBREG
)
3419 && (REG_P (SET_DEST (curr_insn_set
))
3420 || MEM_P (SET_DEST (curr_insn_set
))
3421 || GET_CODE (SET_DEST (curr_insn_set
)) == SUBREG
))))
3427 /* Operands that match previous ones have already been handled. */
3428 if (goal_alt_matches
[i
] >= 0)
3431 /* We should not have an operand with a non-offsettable address
3432 appearing where an offsettable address will do. It also may
3433 be a case when the address should be special in other words
3434 not a general one (e.g. it needs no index reg). */
3435 if (goal_alt_matched
[i
][0] == -1 && goal_alt_offmemok
[i
] && MEM_P (op
))
3437 enum reg_class rclass
;
3438 rtx
*loc
= &XEXP (op
, 0);
3439 enum rtx_code code
= GET_CODE (*loc
);
3441 push_to_sequence (before
);
3442 rclass
= base_reg_class (GET_MODE (op
), MEM_ADDR_SPACE (op
),
3444 if (GET_RTX_CLASS (code
) == RTX_AUTOINC
)
3445 new_reg
= emit_inc (rclass
, *loc
, *loc
,
3446 /* This value does not matter for MODIFY. */
3447 GET_MODE_SIZE (GET_MODE (op
)));
3448 else if (get_reload_reg (OP_IN
, Pmode
, *loc
, rclass
,
3449 "offsetable address", &new_reg
))
3450 lra_emit_move (new_reg
, *loc
);
3451 before
= get_insns ();
3454 lra_update_dup (curr_id
, i
);
3456 else if (goal_alt_matched
[i
][0] == -1)
3458 enum machine_mode mode
;
3460 int hard_regno
, byte
;
3461 enum op_type type
= curr_static_id
->operand
[i
].type
;
3463 loc
= curr_id
->operand_loc
[i
];
3464 mode
= curr_operand_mode
[i
];
3465 if (GET_CODE (*loc
) == SUBREG
)
3467 reg
= SUBREG_REG (*loc
);
3468 byte
= SUBREG_BYTE (*loc
);
3470 /* Strict_low_part requires reload the register not
3471 the sub-register. */
3472 && (curr_static_id
->operand
[i
].strict_low
3473 || (GET_MODE_SIZE (mode
)
3474 <= GET_MODE_SIZE (GET_MODE (reg
))
3476 = get_try_hard_regno (REGNO (reg
))) >= 0
3477 && (simplify_subreg_regno
3479 GET_MODE (reg
), byte
, mode
) < 0)
3480 && (goal_alt
[i
] == NO_REGS
3481 || (simplify_subreg_regno
3482 (ira_class_hard_regs
[goal_alt
[i
]][0],
3483 GET_MODE (reg
), byte
, mode
) >= 0)))))
3485 loc
= &SUBREG_REG (*loc
);
3486 mode
= GET_MODE (*loc
);
3490 if (get_reload_reg (type
, mode
, old
, goal_alt
[i
], "", &new_reg
)
3493 push_to_sequence (before
);
3494 lra_emit_move (new_reg
, old
);
3495 before
= get_insns ();
3500 && find_reg_note (curr_insn
, REG_UNUSED
, old
) == NULL_RTX
)
3503 lra_emit_move (type
== OP_INOUT
? copy_rtx (old
) : old
, new_reg
);
3505 after
= get_insns ();
3509 for (j
= 0; j
< goal_alt_dont_inherit_ops_num
; j
++)
3510 if (goal_alt_dont_inherit_ops
[j
] == i
)
3512 lra_set_regno_unique_value (REGNO (new_reg
));
3515 lra_update_dup (curr_id
, i
);
3517 else if (curr_static_id
->operand
[i
].type
== OP_IN
3518 && (curr_static_id
->operand
[goal_alt_matched
[i
][0]].type
3521 /* generate reloads for input and matched outputs. */
3522 match_inputs
[0] = i
;
3523 match_inputs
[1] = -1;
3524 match_reload (goal_alt_matched
[i
][0], match_inputs
,
3525 goal_alt
[i
], &before
, &after
);
3527 else if (curr_static_id
->operand
[i
].type
== OP_OUT
3528 && (curr_static_id
->operand
[goal_alt_matched
[i
][0]].type
3530 /* Generate reloads for output and matched inputs. */
3531 match_reload (i
, goal_alt_matched
[i
], goal_alt
[i
], &before
, &after
);
3532 else if (curr_static_id
->operand
[i
].type
== OP_IN
3533 && (curr_static_id
->operand
[goal_alt_matched
[i
][0]].type
3536 /* Generate reloads for matched inputs. */
3537 match_inputs
[0] = i
;
3538 for (j
= 0; (k
= goal_alt_matched
[i
][j
]) >= 0; j
++)
3539 match_inputs
[j
+ 1] = k
;
3540 match_inputs
[j
+ 1] = -1;
3541 match_reload (-1, match_inputs
, goal_alt
[i
], &before
, &after
);
3544 /* We must generate code in any case when function
3545 process_alt_operands decides that it is possible. */
3549 lra_assert (REG_P (op
));
3551 op
= *curr_id
->operand_loc
[i
]; /* Substitution. */
3552 if (GET_CODE (op
) == SUBREG
)
3553 op
= SUBREG_REG (op
);
3554 gcc_assert (REG_P (op
) && (int) REGNO (op
) >= new_regno_start
);
3555 bitmap_set_bit (&lra_optional_reload_pseudos
, REGNO (op
));
3556 lra_reg_info
[REGNO (op
)].restore_regno
= regno
;
3557 if (lra_dump_file
!= NULL
)
3558 fprintf (lra_dump_file
,
3559 " Making reload reg %d for reg %d optional\n",
3563 if (before
!= NULL_RTX
|| after
!= NULL_RTX
3564 || max_regno_before
!= max_reg_num ())
3568 lra_update_operator_dups (curr_id
);
3569 /* Something changes -- process the insn. */
3570 lra_update_insn_regno_info (curr_insn
);
3572 lra_process_new_insns (curr_insn
, before
, after
, "Inserting insn reload");
3576 /* Return true if X is in LIST. */
3578 in_list_p (rtx x
, rtx list
)
3580 for (; list
!= NULL_RTX
; list
= XEXP (list
, 1))
3581 if (XEXP (list
, 0) == x
)
3586 /* Return true if X contains an allocatable hard register (if
3587 HARD_REG_P) or a (spilled if SPILLED_P) pseudo. */
3589 contains_reg_p (rtx x
, bool hard_reg_p
, bool spilled_p
)
3595 code
= GET_CODE (x
);
3598 int regno
= REGNO (x
);
3599 HARD_REG_SET alloc_regs
;
3603 if (regno
>= FIRST_PSEUDO_REGISTER
)
3604 regno
= lra_get_regno_hard_regno (regno
);
3607 COMPL_HARD_REG_SET (alloc_regs
, lra_no_alloc_regs
);
3608 return overlaps_hard_reg_set_p (alloc_regs
, GET_MODE (x
), regno
);
3612 if (regno
< FIRST_PSEUDO_REGISTER
)
3616 return lra_get_regno_hard_regno (regno
) < 0;
3619 fmt
= GET_RTX_FORMAT (code
);
3620 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
3624 if (contains_reg_p (XEXP (x
, i
), hard_reg_p
, spilled_p
))
3627 else if (fmt
[i
] == 'E')
3629 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3630 if (contains_reg_p (XVECEXP (x
, i
, j
), hard_reg_p
, spilled_p
))
3637 /* Process all regs in location *LOC and change them on equivalent
3638 substitution. Return true if any change was done. */
3640 loc_equivalence_change_p (rtx
*loc
)
3642 rtx subst
, reg
, x
= *loc
;
3643 bool result
= false;
3644 enum rtx_code code
= GET_CODE (x
);
3650 reg
= SUBREG_REG (x
);
3651 if ((subst
= get_equiv_substitution (reg
)) != reg
3652 && GET_MODE (subst
) == VOIDmode
)
3654 /* We cannot reload debug location. Simplify subreg here
3655 while we know the inner mode. */
3656 *loc
= simplify_gen_subreg (GET_MODE (x
), subst
,
3657 GET_MODE (reg
), SUBREG_BYTE (x
));
3661 if (code
== REG
&& (subst
= get_equiv_substitution (x
)) != x
)
3667 /* Scan all the operand sub-expressions. */
3668 fmt
= GET_RTX_FORMAT (code
);
3669 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
3672 result
= loc_equivalence_change_p (&XEXP (x
, i
)) || result
;
3673 else if (fmt
[i
] == 'E')
3674 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3676 = loc_equivalence_change_p (&XVECEXP (x
, i
, j
)) || result
;
3681 /* Similar to loc_equivalence_change_p, but for use as
3682 simplify_replace_fn_rtx callback. */
3684 loc_equivalence_callback (rtx loc
, const_rtx
, void *)
3689 rtx subst
= get_equiv_substitution (loc
);
3696 /* Maximum number of generated reload insns per an insn. It is for
3697 preventing this pass cycling in a bug case. */
3698 #define MAX_RELOAD_INSNS_NUMBER LRA_MAX_INSN_RELOADS
3700 /* The current iteration number of this LRA pass. */
3701 int lra_constraint_iter
;
3703 /* The current iteration number of this LRA pass after the last spill
3705 int lra_constraint_iter_after_spill
;
3707 /* True if we substituted equiv which needs checking register
3708 allocation correctness because the equivalent value contains
3709 allocatable hard registers or when we restore multi-register
3711 bool lra_risky_transformations_p
;
3713 /* Return true if REGNO is referenced in more than one block. */
3715 multi_block_pseudo_p (int regno
)
3717 basic_block bb
= NULL
;
3721 if (regno
< FIRST_PSEUDO_REGISTER
)
3724 EXECUTE_IF_SET_IN_BITMAP (&lra_reg_info
[regno
].insn_bitmap
, 0, uid
, bi
)
3726 bb
= BLOCK_FOR_INSN (lra_insn_recog_data
[uid
]->insn
);
3727 else if (BLOCK_FOR_INSN (lra_insn_recog_data
[uid
]->insn
) != bb
)
3732 /* Return true if LIST contains a deleted insn. */
3734 contains_deleted_insn_p (rtx list
)
3736 for (; list
!= NULL_RTX
; list
= XEXP (list
, 1))
3737 if (NOTE_P (XEXP (list
, 0))
3738 && NOTE_KIND (XEXP (list
, 0)) == NOTE_INSN_DELETED
)
3743 /* Return true if X contains a pseudo dying in INSN. */
3745 dead_pseudo_p (rtx x
, rtx insn
)
3752 return (insn
!= NULL_RTX
3753 && find_regno_note (insn
, REG_DEAD
, REGNO (x
)) != NULL_RTX
);
3754 code
= GET_CODE (x
);
3755 fmt
= GET_RTX_FORMAT (code
);
3756 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
3760 if (dead_pseudo_p (XEXP (x
, i
), insn
))
3763 else if (fmt
[i
] == 'E')
3765 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3766 if (dead_pseudo_p (XVECEXP (x
, i
, j
), insn
))
3773 /* Return true if INSN contains a dying pseudo in INSN right hand
3776 insn_rhs_dead_pseudo_p (rtx insn
)
3778 rtx set
= single_set (insn
);
3780 gcc_assert (set
!= NULL
);
3781 return dead_pseudo_p (SET_SRC (set
), insn
);
3784 /* Return true if any init insn of REGNO contains a dying pseudo in
3785 insn right hand side. */
3787 init_insn_rhs_dead_pseudo_p (int regno
)
3789 rtx insns
= ira_reg_equiv
[regno
].init_insns
;
3794 return insn_rhs_dead_pseudo_p (insns
);
3795 for (; insns
!= NULL_RTX
; insns
= XEXP (insns
, 1))
3796 if (insn_rhs_dead_pseudo_p (XEXP (insns
, 0)))
3801 /* Return TRUE if REGNO has a reverse equivalence. The equivalence is
3802 reverse only if we have one init insn with given REGNO as a
3805 reverse_equiv_p (int regno
)
3809 if ((insns
= ira_reg_equiv
[regno
].init_insns
) == NULL_RTX
)
3811 if (! INSN_P (XEXP (insns
, 0))
3812 || XEXP (insns
, 1) != NULL_RTX
)
3814 if ((set
= single_set (XEXP (insns
, 0))) == NULL_RTX
)
3816 return REG_P (SET_SRC (set
)) && (int) REGNO (SET_SRC (set
)) == regno
;
3819 /* Return TRUE if REGNO was reloaded in an equivalence init insn. We
3820 call this function only for non-reverse equivalence. */
3822 contains_reloaded_insn_p (int regno
)
3825 rtx list
= ira_reg_equiv
[regno
].init_insns
;
3827 for (; list
!= NULL_RTX
; list
= XEXP (list
, 1))
3828 if ((set
= single_set (XEXP (list
, 0))) == NULL_RTX
3829 || ! REG_P (SET_DEST (set
))
3830 || (int) REGNO (SET_DEST (set
)) != regno
)
3835 /* Entry function of LRA constraint pass. Return true if the
3836 constraint pass did change the code. */
3838 lra_constraints (bool first_p
)
3841 int i
, hard_regno
, new_insns_num
;
3842 unsigned int min_len
, new_min_len
, uid
;
3843 rtx set
, x
, reg
, dest_reg
;
3844 basic_block last_bb
;
3845 bitmap_head equiv_insn_bitmap
;
3848 lra_constraint_iter
++;
3849 if (lra_dump_file
!= NULL
)
3850 fprintf (lra_dump_file
, "\n********** Local #%d: **********\n\n",
3851 lra_constraint_iter
);
3852 lra_constraint_iter_after_spill
++;
3853 if (lra_constraint_iter_after_spill
> LRA_MAX_CONSTRAINT_ITERATION_NUMBER
)
3855 ("Maximum number of LRA constraint passes is achieved (%d)\n",
3856 LRA_MAX_CONSTRAINT_ITERATION_NUMBER
);
3858 lra_risky_transformations_p
= false;
3859 new_insn_uid_start
= get_max_uid ();
3860 new_regno_start
= first_p
? lra_constraint_new_regno_start
: max_reg_num ();
3861 bitmap_initialize (&equiv_insn_bitmap
, ®_obstack
);
3862 for (i
= FIRST_PSEUDO_REGISTER
; i
< new_regno_start
; i
++)
3863 if (lra_reg_info
[i
].nrefs
!= 0)
3865 ira_reg_equiv
[i
].profitable_p
= true;
3866 reg
= regno_reg_rtx
[i
];
3867 if ((hard_regno
= lra_get_regno_hard_regno (i
)) >= 0)
3871 nregs
= hard_regno_nregs
[hard_regno
][lra_reg_info
[i
].biggest_mode
];
3872 for (j
= 0; j
< nregs
; j
++)
3873 df_set_regs_ever_live (hard_regno
+ j
, true);
3875 else if ((x
= get_equiv_substitution (reg
)) != reg
)
3877 bool pseudo_p
= contains_reg_p (x
, false, false);
3879 /* After RTL transformation, we can not guarantee that
3880 pseudo in the substitution was not reloaded which might
3881 make equivalence invalid. For example, in reverse
3888 the memory address register was reloaded before the 2nd
3890 if ((! first_p
&& pseudo_p
)
3891 /* We don't use DF for compilation speed sake. So it
3892 is problematic to update live info when we use an
3893 equivalence containing pseudos in more than one
3895 || (pseudo_p
&& multi_block_pseudo_p (i
))
3896 /* If an init insn was deleted for some reason, cancel
3897 the equiv. We could update the equiv insns after
3898 transformations including an equiv insn deletion
3899 but it is not worthy as such cases are extremely
3901 || contains_deleted_insn_p (ira_reg_equiv
[i
].init_insns
)
3902 /* If it is not a reverse equivalence, we check that a
3903 pseudo in rhs of the init insn is not dying in the
3904 insn. Otherwise, the live info at the beginning of
3905 the corresponding BB might be wrong after we
3906 removed the insn. When the equiv can be a
3907 constant, the right hand side of the init insn can
3909 || (! reverse_equiv_p (i
)
3910 && (init_insn_rhs_dead_pseudo_p (i
)
3911 /* If we reloaded the pseudo in an equivalence
3912 init insn, we can not remove the equiv init
3913 insns and the init insns might write into
3914 const memory in this case. */
3915 || contains_reloaded_insn_p (i
)))
3916 /* Prevent access beyond equivalent memory for
3917 paradoxical subregs. */
3919 && (GET_MODE_SIZE (lra_reg_info
[i
].biggest_mode
)
3920 > GET_MODE_SIZE (GET_MODE (x
)))))
3921 ira_reg_equiv
[i
].defined_p
= false;
3922 if (contains_reg_p (x
, false, true))
3923 ira_reg_equiv
[i
].profitable_p
= false;
3924 if (get_equiv_substitution (reg
) != reg
)
3925 bitmap_ior_into (&equiv_insn_bitmap
, &lra_reg_info
[i
].insn_bitmap
);
3928 /* We should add all insns containing pseudos which should be
3929 substituted by their equivalences. */
3930 EXECUTE_IF_SET_IN_BITMAP (&equiv_insn_bitmap
, 0, uid
, bi
)
3931 lra_push_insn_by_uid (uid
);
3932 lra_eliminate (false);
3933 min_len
= lra_insn_stack_length ();
3937 while ((new_min_len
= lra_insn_stack_length ()) != 0)
3939 curr_insn
= lra_pop_insn ();
3941 curr_bb
= BLOCK_FOR_INSN (curr_insn
);
3942 if (curr_bb
!= last_bb
)
3945 bb_reload_num
= lra_curr_reload_num
;
3947 if (min_len
> new_min_len
)
3949 min_len
= new_min_len
;
3952 if (new_insns_num
> MAX_RELOAD_INSNS_NUMBER
)
3954 ("Max. number of generated reload insns per insn is achieved (%d)\n",
3955 MAX_RELOAD_INSNS_NUMBER
);
3957 if (DEBUG_INSN_P (curr_insn
))
3959 /* We need to check equivalence in debug insn and change
3960 pseudo to the equivalent value if necessary. */
3961 curr_id
= lra_get_insn_recog_data (curr_insn
);
3962 if (bitmap_bit_p (&equiv_insn_bitmap
, INSN_UID (curr_insn
)))
3964 rtx old
= *curr_id
->operand_loc
[0];
3965 *curr_id
->operand_loc
[0]
3966 = simplify_replace_fn_rtx (old
, NULL_RTX
,
3967 loc_equivalence_callback
, NULL
);
3968 if (old
!= *curr_id
->operand_loc
[0])
3970 lra_update_insn_regno_info (curr_insn
);
3975 else if (INSN_P (curr_insn
))
3977 if ((set
= single_set (curr_insn
)) != NULL_RTX
)
3979 dest_reg
= SET_DEST (set
);
3980 /* The equivalence pseudo could be set up as SUBREG in a
3981 case when it is a call restore insn in a mode
3982 different from the pseudo mode. */
3983 if (GET_CODE (dest_reg
) == SUBREG
)
3984 dest_reg
= SUBREG_REG (dest_reg
);
3985 if ((REG_P (dest_reg
)
3986 && (x
= get_equiv_substitution (dest_reg
)) != dest_reg
3987 /* Remove insns which set up a pseudo whose value
3988 can not be changed. Such insns might be not in
3989 init_insns because we don't update equiv data
3990 during insn transformations.
3992 As an example, let suppose that a pseudo got
3993 hard register and on the 1st pass was not
3994 changed to equivalent constant. We generate an
3995 additional insn setting up the pseudo because of
3996 secondary memory movement. Then the pseudo is
3997 spilled and we use the equiv constant. In this
3998 case we should remove the additional insn and
3999 this insn is not init_insns list. */
4000 && (! MEM_P (x
) || MEM_READONLY_P (x
)
4001 /* Check that this is actually an insn setting
4002 up the equivalence. */
4003 || in_list_p (curr_insn
,
4005 [REGNO (dest_reg
)].init_insns
)))
4006 || (((x
= get_equiv_substitution (SET_SRC (set
)))
4008 && in_list_p (curr_insn
,
4010 [REGNO (SET_SRC (set
))].init_insns
)))
4012 /* This is equiv init insn of pseudo which did not get a
4013 hard register -- remove the insn. */
4014 if (lra_dump_file
!= NULL
)
4016 fprintf (lra_dump_file
,
4017 " Removing equiv init insn %i (freq=%d)\n",
4018 INSN_UID (curr_insn
),
4019 BLOCK_FOR_INSN (curr_insn
)->frequency
);
4020 dump_insn_slim (lra_dump_file
, curr_insn
);
4022 if (contains_reg_p (x
, true, false))
4023 lra_risky_transformations_p
= true;
4024 lra_set_insn_deleted (curr_insn
);
4028 curr_id
= lra_get_insn_recog_data (curr_insn
);
4029 curr_static_id
= curr_id
->insn_static_data
;
4030 init_curr_insn_input_reloads ();
4031 init_curr_operand_mode ();
4032 if (curr_insn_transform ())
4034 /* Check non-transformed insns too for equiv change as USE
4035 or CLOBBER don't need reloads but can contain pseudos
4036 being changed on their equivalences. */
4037 else if (bitmap_bit_p (&equiv_insn_bitmap
, INSN_UID (curr_insn
))
4038 && loc_equivalence_change_p (&PATTERN (curr_insn
)))
4040 lra_update_insn_regno_info (curr_insn
);
4045 bitmap_clear (&equiv_insn_bitmap
);
4046 /* If we used a new hard regno, changed_p should be true because the
4047 hard reg is assigned to a new pseudo. */
4048 #ifdef ENABLE_CHECKING
4051 for (i
= FIRST_PSEUDO_REGISTER
; i
< new_regno_start
; i
++)
4052 if (lra_reg_info
[i
].nrefs
!= 0
4053 && (hard_regno
= lra_get_regno_hard_regno (i
)) >= 0)
4055 int j
, nregs
= hard_regno_nregs
[hard_regno
][PSEUDO_REGNO_MODE (i
)];
4057 for (j
= 0; j
< nregs
; j
++)
4058 lra_assert (df_regs_ever_live_p (hard_regno
+ j
));
4065 /* Initiate the LRA constraint pass. It is done once per
4068 lra_constraints_init (void)
4072 /* Finalize the LRA constraint pass. It is done once per
4075 lra_constraints_finish (void)
4081 /* This page contains code to do inheritance/split
4084 /* Number of reloads passed so far in current EBB. */
4085 static int reloads_num
;
4087 /* Number of calls passed so far in current EBB. */
4088 static int calls_num
;
4090 /* Current reload pseudo check for validity of elements in
4092 static int curr_usage_insns_check
;
4094 /* Info about last usage of registers in EBB to do inheritance/split
4095 transformation. Inheritance transformation is done from a spilled
4096 pseudo and split transformations from a hard register or a pseudo
4097 assigned to a hard register. */
4100 /* If the value is equal to CURR_USAGE_INSNS_CHECK, then the member
4101 value INSNS is valid. The insns is chain of optional debug insns
4102 and a finishing non-debug insn using the corresponding reg. The
4103 value is also used to mark the registers which are set up in the
4104 current insn. The negated insn uid is used for this. */
4106 /* Value of global reloads_num at the last insn in INSNS. */
4108 /* Value of global reloads_nums at the last insn in INSNS. */
4110 /* It can be true only for splitting. And it means that the restore
4111 insn should be put after insn given by the following member. */
4113 /* Next insns in the current EBB which use the original reg and the
4114 original reg value is not changed between the current insn and
4115 the next insns. In order words, e.g. for inheritance, if we need
4116 to use the original reg value again in the next insns we can try
4117 to use the value in a hard register from a reload insn of the
4122 /* Map: regno -> corresponding pseudo usage insns. */
4123 static struct usage_insns
*usage_insns
;
4126 setup_next_usage_insn (int regno
, rtx insn
, int reloads_num
, bool after_p
)
4128 usage_insns
[regno
].check
= curr_usage_insns_check
;
4129 usage_insns
[regno
].insns
= insn
;
4130 usage_insns
[regno
].reloads_num
= reloads_num
;
4131 usage_insns
[regno
].calls_num
= calls_num
;
4132 usage_insns
[regno
].after_p
= after_p
;
4135 /* The function is used to form list REGNO usages which consists of
4136 optional debug insns finished by a non-debug insn using REGNO.
4137 RELOADS_NUM is current number of reload insns processed so far. */
4139 add_next_usage_insn (int regno
, rtx insn
, int reloads_num
)
4141 rtx next_usage_insns
;
4143 if (usage_insns
[regno
].check
== curr_usage_insns_check
4144 && (next_usage_insns
= usage_insns
[regno
].insns
) != NULL_RTX
4145 && DEBUG_INSN_P (insn
))
4147 /* Check that we did not add the debug insn yet. */
4148 if (next_usage_insns
!= insn
4149 && (GET_CODE (next_usage_insns
) != INSN_LIST
4150 || XEXP (next_usage_insns
, 0) != insn
))
4151 usage_insns
[regno
].insns
= gen_rtx_INSN_LIST (VOIDmode
, insn
,
4154 else if (NONDEBUG_INSN_P (insn
))
4155 setup_next_usage_insn (regno
, insn
, reloads_num
, false);
4157 usage_insns
[regno
].check
= 0;
4160 /* Replace all references to register OLD_REGNO in *LOC with pseudo
4161 register NEW_REG. Return true if any change was made. */
4163 substitute_pseudo (rtx
*loc
, int old_regno
, rtx new_reg
)
4166 bool result
= false;
4174 code
= GET_CODE (x
);
4175 if (code
== REG
&& (int) REGNO (x
) == old_regno
)
4177 enum machine_mode mode
= GET_MODE (*loc
);
4178 enum machine_mode inner_mode
= GET_MODE (new_reg
);
4180 if (mode
!= inner_mode
)
4182 if (GET_MODE_SIZE (mode
) >= GET_MODE_SIZE (inner_mode
)
4183 || ! SCALAR_INT_MODE_P (inner_mode
))
4184 new_reg
= gen_rtx_SUBREG (mode
, new_reg
, 0);
4186 new_reg
= gen_lowpart_SUBREG (mode
, new_reg
);
4192 /* Scan all the operand sub-expressions. */
4193 fmt
= GET_RTX_FORMAT (code
);
4194 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
4198 if (substitute_pseudo (&XEXP (x
, i
), old_regno
, new_reg
))
4201 else if (fmt
[i
] == 'E')
4203 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
4204 if (substitute_pseudo (&XVECEXP (x
, i
, j
), old_regno
, new_reg
))
4211 /* Return first non-debug insn in list USAGE_INSNS. */
4213 skip_usage_debug_insns (rtx usage_insns
)
4217 /* Skip debug insns. */
4218 for (insn
= usage_insns
;
4219 insn
!= NULL_RTX
&& GET_CODE (insn
) == INSN_LIST
;
4220 insn
= XEXP (insn
, 1))
4225 /* Return true if we need secondary memory moves for insn in
4226 USAGE_INSNS after inserting inherited pseudo of class INHER_CL
4229 check_secondary_memory_needed_p (enum reg_class inher_cl ATTRIBUTE_UNUSED
,
4230 rtx usage_insns ATTRIBUTE_UNUSED
)
4232 #ifndef SECONDARY_MEMORY_NEEDED
4235 rtx insn
, set
, dest
;
4238 if (inher_cl
== ALL_REGS
4239 || (insn
= skip_usage_debug_insns (usage_insns
)) == NULL_RTX
)
4241 lra_assert (INSN_P (insn
));
4242 if ((set
= single_set (insn
)) == NULL_RTX
|| ! REG_P (SET_DEST (set
)))
4244 dest
= SET_DEST (set
);
4247 lra_assert (inher_cl
!= NO_REGS
);
4248 cl
= get_reg_class (REGNO (dest
));
4249 return (cl
!= NO_REGS
&& cl
!= ALL_REGS
4250 && SECONDARY_MEMORY_NEEDED (inher_cl
, cl
, GET_MODE (dest
)));
4254 /* Registers involved in inheritance/split in the current EBB
4255 (inheritance/split pseudos and original registers). */
4256 static bitmap_head check_only_regs
;
4258 /* Do inheritance transformations for insn INSN, which defines (if
4259 DEF_P) or uses ORIGINAL_REGNO. NEXT_USAGE_INSNS specifies which
4260 instruction in the EBB next uses ORIGINAL_REGNO; it has the same
4261 form as the "insns" field of usage_insns. Return true if we
4262 succeed in such transformation.
4264 The transformations look like:
4267 ... p <- i (new insn)
4269 <- ... p ... <- ... i ...
4271 ... i <- p (new insn)
4272 <- ... p ... <- ... i ...
4274 <- ... p ... <- ... i ...
4275 where p is a spilled original pseudo and i is a new inheritance pseudo.
4278 The inheritance pseudo has the smallest class of two classes CL and
4279 class of ORIGINAL REGNO. */
4281 inherit_reload_reg (bool def_p
, int original_regno
,
4282 enum reg_class cl
, rtx insn
, rtx next_usage_insns
)
4284 enum reg_class rclass
= lra_get_allocno_class (original_regno
);
4285 rtx original_reg
= regno_reg_rtx
[original_regno
];
4286 rtx new_reg
, new_insns
, usage_insn
;
4288 lra_assert (! usage_insns
[original_regno
].after_p
);
4289 if (lra_dump_file
!= NULL
)
4290 fprintf (lra_dump_file
,
4291 " <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<\n");
4292 if (! ira_reg_classes_intersect_p
[cl
][rclass
])
4294 if (lra_dump_file
!= NULL
)
4296 fprintf (lra_dump_file
,
4297 " Rejecting inheritance for %d "
4298 "because of disjoint classes %s and %s\n",
4299 original_regno
, reg_class_names
[cl
],
4300 reg_class_names
[rclass
]);
4301 fprintf (lra_dump_file
,
4302 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
4306 if ((ira_class_subset_p
[cl
][rclass
] && cl
!= rclass
)
4307 /* We don't use a subset of two classes because it can be
4308 NO_REGS. This transformation is still profitable in most
4309 cases even if the classes are not intersected as register
4310 move is probably cheaper than a memory load. */
4311 || ira_class_hard_regs_num
[cl
] < ira_class_hard_regs_num
[rclass
])
4313 if (lra_dump_file
!= NULL
)
4314 fprintf (lra_dump_file
, " Use smallest class of %s and %s\n",
4315 reg_class_names
[cl
], reg_class_names
[rclass
]);
4319 if (check_secondary_memory_needed_p (rclass
, next_usage_insns
))
4321 /* Reject inheritance resulting in secondary memory moves.
4322 Otherwise, there is a danger in LRA cycling. Also such
4323 transformation will be unprofitable. */
4324 if (lra_dump_file
!= NULL
)
4326 rtx insn
= skip_usage_debug_insns (next_usage_insns
);
4327 rtx set
= single_set (insn
);
4329 lra_assert (set
!= NULL_RTX
);
4331 rtx dest
= SET_DEST (set
);
4333 lra_assert (REG_P (dest
));
4334 fprintf (lra_dump_file
,
4335 " Rejecting inheritance for insn %d(%s)<-%d(%s) "
4336 "as secondary mem is needed\n",
4337 REGNO (dest
), reg_class_names
[get_reg_class (REGNO (dest
))],
4338 original_regno
, reg_class_names
[rclass
]);
4339 fprintf (lra_dump_file
,
4340 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
4344 new_reg
= lra_create_new_reg (GET_MODE (original_reg
), original_reg
,
4345 rclass
, "inheritance");
4348 emit_move_insn (original_reg
, new_reg
);
4350 emit_move_insn (new_reg
, original_reg
);
4351 new_insns
= get_insns ();
4353 if (NEXT_INSN (new_insns
) != NULL_RTX
)
4355 if (lra_dump_file
!= NULL
)
4357 fprintf (lra_dump_file
,
4358 " Rejecting inheritance %d->%d "
4359 "as it results in 2 or more insns:\n",
4360 original_regno
, REGNO (new_reg
));
4361 dump_rtl_slim (lra_dump_file
, new_insns
, NULL_RTX
, -1, 0);
4362 fprintf (lra_dump_file
,
4363 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
4367 substitute_pseudo (&insn
, original_regno
, new_reg
);
4368 lra_update_insn_regno_info (insn
);
4370 /* We now have a new usage insn for original regno. */
4371 setup_next_usage_insn (original_regno
, new_insns
, reloads_num
, false);
4372 if (lra_dump_file
!= NULL
)
4373 fprintf (lra_dump_file
, " Original reg change %d->%d (bb%d):\n",
4374 original_regno
, REGNO (new_reg
), BLOCK_FOR_INSN (insn
)->index
);
4375 lra_reg_info
[REGNO (new_reg
)].restore_regno
= original_regno
;
4376 bitmap_set_bit (&check_only_regs
, REGNO (new_reg
));
4377 bitmap_set_bit (&check_only_regs
, original_regno
);
4378 bitmap_set_bit (&lra_inheritance_pseudos
, REGNO (new_reg
));
4380 lra_process_new_insns (insn
, NULL_RTX
, new_insns
,
4381 "Add original<-inheritance");
4383 lra_process_new_insns (insn
, new_insns
, NULL_RTX
,
4384 "Add inheritance<-original");
4385 while (next_usage_insns
!= NULL_RTX
)
4387 if (GET_CODE (next_usage_insns
) != INSN_LIST
)
4389 usage_insn
= next_usage_insns
;
4390 lra_assert (NONDEBUG_INSN_P (usage_insn
));
4391 next_usage_insns
= NULL
;
4395 usage_insn
= XEXP (next_usage_insns
, 0);
4396 lra_assert (DEBUG_INSN_P (usage_insn
));
4397 next_usage_insns
= XEXP (next_usage_insns
, 1);
4399 substitute_pseudo (&usage_insn
, original_regno
, new_reg
);
4400 lra_update_insn_regno_info (usage_insn
);
4401 if (lra_dump_file
!= NULL
)
4403 fprintf (lra_dump_file
,
4404 " Inheritance reuse change %d->%d (bb%d):\n",
4405 original_regno
, REGNO (new_reg
),
4406 BLOCK_FOR_INSN (usage_insn
)->index
);
4407 dump_insn_slim (lra_dump_file
, usage_insn
);
4410 if (lra_dump_file
!= NULL
)
4411 fprintf (lra_dump_file
,
4412 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
4416 /* Return true if we need a caller save/restore for pseudo REGNO which
4417 was assigned to a hard register. */
4419 need_for_call_save_p (int regno
)
4421 lra_assert (regno
>= FIRST_PSEUDO_REGISTER
&& reg_renumber
[regno
] >= 0);
4422 return (usage_insns
[regno
].calls_num
< calls_num
4423 && (overlaps_hard_reg_set_p
4425 PSEUDO_REGNO_MODE (regno
), reg_renumber
[regno
])
4426 || HARD_REGNO_CALL_PART_CLOBBERED (reg_renumber
[regno
],
4427 PSEUDO_REGNO_MODE (regno
))));
4430 /* Global registers occurring in the current EBB. */
4431 static bitmap_head ebb_global_regs
;
4433 /* Return true if we need a split for hard register REGNO or pseudo
4434 REGNO which was assigned to a hard register.
4435 POTENTIAL_RELOAD_HARD_REGS contains hard registers which might be
4436 used for reloads since the EBB end. It is an approximation of the
4437 used hard registers in the split range. The exact value would
4438 require expensive calculations. If we were aggressive with
4439 splitting because of the approximation, the split pseudo will save
4440 the same hard register assignment and will be removed in the undo
4441 pass. We still need the approximation because too aggressive
4442 splitting would result in too inaccurate cost calculation in the
4443 assignment pass because of too many generated moves which will be
4444 probably removed in the undo pass. */
4446 need_for_split_p (HARD_REG_SET potential_reload_hard_regs
, int regno
)
4448 int hard_regno
= regno
< FIRST_PSEUDO_REGISTER
? regno
: reg_renumber
[regno
];
4450 lra_assert (hard_regno
>= 0);
4451 return ((TEST_HARD_REG_BIT (potential_reload_hard_regs
, hard_regno
)
4452 /* Don't split eliminable hard registers, otherwise we can
4453 split hard registers like hard frame pointer, which
4454 lives on BB start/end according to DF-infrastructure,
4455 when there is a pseudo assigned to the register and
4456 living in the same BB. */
4457 && (regno
>= FIRST_PSEUDO_REGISTER
4458 || ! TEST_HARD_REG_BIT (eliminable_regset
, hard_regno
))
4459 && ! TEST_HARD_REG_BIT (lra_no_alloc_regs
, hard_regno
)
4460 /* Don't split call clobbered hard regs living through
4461 calls, otherwise we might have a check problem in the
4462 assign sub-pass as in the most cases (exception is a
4463 situation when lra_risky_transformations_p value is
4464 true) the assign pass assumes that all pseudos living
4465 through calls are assigned to call saved hard regs. */
4466 && (regno
>= FIRST_PSEUDO_REGISTER
4467 || ! TEST_HARD_REG_BIT (call_used_reg_set
, regno
)
4468 || usage_insns
[regno
].calls_num
== calls_num
)
4469 /* We need at least 2 reloads to make pseudo splitting
4470 profitable. We should provide hard regno splitting in
4471 any case to solve 1st insn scheduling problem when
4472 moving hard register definition up might result in
4473 impossibility to find hard register for reload pseudo of
4474 small register class. */
4475 && (usage_insns
[regno
].reloads_num
4476 + (regno
< FIRST_PSEUDO_REGISTER
? 0 : 2) < reloads_num
)
4477 && (regno
< FIRST_PSEUDO_REGISTER
4478 /* For short living pseudos, spilling + inheritance can
4479 be considered a substitution for splitting.
4480 Therefore we do not splitting for local pseudos. It
4481 decreases also aggressiveness of splitting. The
4482 minimal number of references is chosen taking into
4483 account that for 2 references splitting has no sense
4484 as we can just spill the pseudo. */
4485 || (regno
>= FIRST_PSEUDO_REGISTER
4486 && lra_reg_info
[regno
].nrefs
> 3
4487 && bitmap_bit_p (&ebb_global_regs
, regno
))))
4488 || (regno
>= FIRST_PSEUDO_REGISTER
&& need_for_call_save_p (regno
)));
4491 /* Return class for the split pseudo created from original pseudo with
4492 ALLOCNO_CLASS and MODE which got a hard register HARD_REGNO. We
4493 choose subclass of ALLOCNO_CLASS which contains HARD_REGNO and
4494 results in no secondary memory movements. */
4495 static enum reg_class
4496 choose_split_class (enum reg_class allocno_class
,
4497 int hard_regno ATTRIBUTE_UNUSED
,
4498 enum machine_mode mode ATTRIBUTE_UNUSED
)
4500 #ifndef SECONDARY_MEMORY_NEEDED
4501 return allocno_class
;
4504 enum reg_class cl
, best_cl
= NO_REGS
;
4505 enum reg_class hard_reg_class ATTRIBUTE_UNUSED
4506 = REGNO_REG_CLASS (hard_regno
);
4508 if (! SECONDARY_MEMORY_NEEDED (allocno_class
, allocno_class
, mode
)
4509 && TEST_HARD_REG_BIT (reg_class_contents
[allocno_class
], hard_regno
))
4510 return allocno_class
;
4512 (cl
= reg_class_subclasses
[allocno_class
][i
]) != LIM_REG_CLASSES
;
4514 if (! SECONDARY_MEMORY_NEEDED (cl
, hard_reg_class
, mode
)
4515 && ! SECONDARY_MEMORY_NEEDED (hard_reg_class
, cl
, mode
)
4516 && TEST_HARD_REG_BIT (reg_class_contents
[cl
], hard_regno
)
4517 && (best_cl
== NO_REGS
4518 || ira_class_hard_regs_num
[best_cl
] < ira_class_hard_regs_num
[cl
]))
4524 /* Do split transformations for insn INSN, which defines or uses
4525 ORIGINAL_REGNO. NEXT_USAGE_INSNS specifies which instruction in
4526 the EBB next uses ORIGINAL_REGNO; it has the same form as the
4527 "insns" field of usage_insns.
4529 The transformations look like:
4532 ... s <- p (new insn -- save)
4534 ... p <- s (new insn -- restore)
4535 <- ... p ... <- ... p ...
4537 <- ... p ... <- ... p ...
4538 ... s <- p (new insn -- save)
4540 ... p <- s (new insn -- restore)
4541 <- ... p ... <- ... p ...
4543 where p is an original pseudo got a hard register or a hard
4544 register and s is a new split pseudo. The save is put before INSN
4545 if BEFORE_P is true. Return true if we succeed in such
4548 split_reg (bool before_p
, int original_regno
, rtx insn
, rtx next_usage_insns
)
4550 enum reg_class rclass
;
4552 int hard_regno
, nregs
;
4553 rtx new_reg
, save
, restore
, usage_insn
;
4557 if (original_regno
< FIRST_PSEUDO_REGISTER
)
4559 rclass
= ira_allocno_class_translate
[REGNO_REG_CLASS (original_regno
)];
4560 hard_regno
= original_regno
;
4561 call_save_p
= false;
4566 hard_regno
= reg_renumber
[original_regno
];
4567 nregs
= hard_regno_nregs
[hard_regno
][PSEUDO_REGNO_MODE (original_regno
)];
4568 rclass
= lra_get_allocno_class (original_regno
);
4569 original_reg
= regno_reg_rtx
[original_regno
];
4570 call_save_p
= need_for_call_save_p (original_regno
);
4572 original_reg
= regno_reg_rtx
[original_regno
];
4573 lra_assert (hard_regno
>= 0);
4574 if (lra_dump_file
!= NULL
)
4575 fprintf (lra_dump_file
,
4576 " ((((((((((((((((((((((((((((((((((((((((((((((((\n");
4579 enum machine_mode mode
= GET_MODE (original_reg
);
4581 mode
= HARD_REGNO_CALLER_SAVE_MODE (hard_regno
,
4582 hard_regno_nregs
[hard_regno
][mode
],
4584 new_reg
= lra_create_new_reg (mode
, NULL_RTX
, NO_REGS
, "save");
4588 rclass
= choose_split_class (rclass
, hard_regno
,
4589 GET_MODE (original_reg
));
4590 if (rclass
== NO_REGS
)
4592 if (lra_dump_file
!= NULL
)
4594 fprintf (lra_dump_file
,
4595 " Rejecting split of %d(%s): "
4596 "no good reg class for %d(%s)\n",
4598 reg_class_names
[lra_get_allocno_class (original_regno
)],
4600 reg_class_names
[REGNO_REG_CLASS (hard_regno
)]);
4603 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
4607 new_reg
= lra_create_new_reg (GET_MODE (original_reg
), original_reg
,
4609 reg_renumber
[REGNO (new_reg
)] = hard_regno
;
4611 save
= emit_spill_move (true, new_reg
, original_reg
);
4612 if (NEXT_INSN (save
) != NULL_RTX
)
4614 lra_assert (! call_save_p
);
4615 if (lra_dump_file
!= NULL
)
4619 " Rejecting split %d->%d resulting in > 2 %s save insns:\n",
4620 original_regno
, REGNO (new_reg
), call_save_p
? "call" : "");
4621 dump_rtl_slim (lra_dump_file
, save
, NULL_RTX
, -1, 0);
4622 fprintf (lra_dump_file
,
4623 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
4627 restore
= emit_spill_move (false, new_reg
, original_reg
);
4628 if (NEXT_INSN (restore
) != NULL_RTX
)
4630 lra_assert (! call_save_p
);
4631 if (lra_dump_file
!= NULL
)
4633 fprintf (lra_dump_file
,
4634 " Rejecting split %d->%d "
4635 "resulting in > 2 %s restore insns:\n",
4636 original_regno
, REGNO (new_reg
), call_save_p
? "call" : "");
4637 dump_rtl_slim (lra_dump_file
, restore
, NULL_RTX
, -1, 0);
4638 fprintf (lra_dump_file
,
4639 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
4643 after_p
= usage_insns
[original_regno
].after_p
;
4644 lra_reg_info
[REGNO (new_reg
)].restore_regno
= original_regno
;
4645 bitmap_set_bit (&check_only_regs
, REGNO (new_reg
));
4646 bitmap_set_bit (&check_only_regs
, original_regno
);
4647 bitmap_set_bit (&lra_split_regs
, REGNO (new_reg
));
4650 if (GET_CODE (next_usage_insns
) != INSN_LIST
)
4652 usage_insn
= next_usage_insns
;
4655 usage_insn
= XEXP (next_usage_insns
, 0);
4656 lra_assert (DEBUG_INSN_P (usage_insn
));
4657 next_usage_insns
= XEXP (next_usage_insns
, 1);
4658 substitute_pseudo (&usage_insn
, original_regno
, new_reg
);
4659 lra_update_insn_regno_info (usage_insn
);
4660 if (lra_dump_file
!= NULL
)
4662 fprintf (lra_dump_file
, " Split reuse change %d->%d:\n",
4663 original_regno
, REGNO (new_reg
));
4664 dump_insn_slim (lra_dump_file
, usage_insn
);
4667 lra_assert (NOTE_P (usage_insn
) || NONDEBUG_INSN_P (usage_insn
));
4668 lra_assert (usage_insn
!= insn
|| (after_p
&& before_p
));
4669 lra_process_new_insns (usage_insn
, after_p
? NULL_RTX
: restore
,
4670 after_p
? restore
: NULL_RTX
,
4672 ? "Add reg<-save" : "Add reg<-split");
4673 lra_process_new_insns (insn
, before_p
? save
: NULL_RTX
,
4674 before_p
? NULL_RTX
: save
,
4676 ? "Add save<-reg" : "Add split<-reg");
4678 /* If we are trying to split multi-register. We should check
4679 conflicts on the next assignment sub-pass. IRA can allocate on
4680 sub-register levels, LRA do this on pseudos level right now and
4681 this discrepancy may create allocation conflicts after
4683 lra_risky_transformations_p
= true;
4684 if (lra_dump_file
!= NULL
)
4685 fprintf (lra_dump_file
,
4686 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
4690 /* Recognize that we need a split transformation for insn INSN, which
4691 defines or uses REGNO in its insn biggest MODE (we use it only if
4692 REGNO is a hard register). POTENTIAL_RELOAD_HARD_REGS contains
4693 hard registers which might be used for reloads since the EBB end.
4694 Put the save before INSN if BEFORE_P is true. MAX_UID is maximla
4695 uid before starting INSN processing. Return true if we succeed in
4696 such transformation. */
4698 split_if_necessary (int regno
, enum machine_mode mode
,
4699 HARD_REG_SET potential_reload_hard_regs
,
4700 bool before_p
, rtx insn
, int max_uid
)
4704 rtx next_usage_insns
;
4706 if (regno
< FIRST_PSEUDO_REGISTER
)
4707 nregs
= hard_regno_nregs
[regno
][mode
];
4708 for (i
= 0; i
< nregs
; i
++)
4709 if (usage_insns
[regno
+ i
].check
== curr_usage_insns_check
4710 && (next_usage_insns
= usage_insns
[regno
+ i
].insns
) != NULL_RTX
4711 /* To avoid processing the register twice or more. */
4712 && ((GET_CODE (next_usage_insns
) != INSN_LIST
4713 && INSN_UID (next_usage_insns
) < max_uid
)
4714 || (GET_CODE (next_usage_insns
) == INSN_LIST
4715 && (INSN_UID (XEXP (next_usage_insns
, 0)) < max_uid
)))
4716 && need_for_split_p (potential_reload_hard_regs
, regno
+ i
)
4717 && split_reg (before_p
, regno
+ i
, insn
, next_usage_insns
))
4722 /* Check only registers living at the current program point in the
4724 static bitmap_head live_regs
;
4726 /* Update live info in EBB given by its HEAD and TAIL insns after
4727 inheritance/split transformation. The function removes dead moves
4730 update_ebb_live_info (rtx head
, rtx tail
)
4737 basic_block last_bb
, prev_bb
, curr_bb
;
4739 struct lra_insn_reg
*reg
;
4743 last_bb
= BLOCK_FOR_INSN (tail
);
4745 for (curr_insn
= tail
;
4746 curr_insn
!= PREV_INSN (head
);
4747 curr_insn
= prev_insn
)
4749 prev_insn
= PREV_INSN (curr_insn
);
4750 /* We need to process empty blocks too. They contain
4751 NOTE_INSN_BASIC_BLOCK referring for the basic block. */
4752 if (NOTE_P (curr_insn
) && NOTE_KIND (curr_insn
) != NOTE_INSN_BASIC_BLOCK
)
4754 curr_bb
= BLOCK_FOR_INSN (curr_insn
);
4755 if (curr_bb
!= prev_bb
)
4757 if (prev_bb
!= NULL
)
4759 /* Update df_get_live_in (prev_bb): */
4760 EXECUTE_IF_SET_IN_BITMAP (&check_only_regs
, 0, j
, bi
)
4761 if (bitmap_bit_p (&live_regs
, j
))
4762 bitmap_set_bit (df_get_live_in (prev_bb
), j
);
4764 bitmap_clear_bit (df_get_live_in (prev_bb
), j
);
4766 if (curr_bb
!= last_bb
)
4768 /* Update df_get_live_out (curr_bb): */
4769 EXECUTE_IF_SET_IN_BITMAP (&check_only_regs
, 0, j
, bi
)
4771 live_p
= bitmap_bit_p (&live_regs
, j
);
4773 FOR_EACH_EDGE (e
, ei
, curr_bb
->succs
)
4774 if (bitmap_bit_p (df_get_live_in (e
->dest
), j
))
4780 bitmap_set_bit (df_get_live_out (curr_bb
), j
);
4782 bitmap_clear_bit (df_get_live_out (curr_bb
), j
);
4786 bitmap_and (&live_regs
, &check_only_regs
, df_get_live_out (curr_bb
));
4788 if (! NONDEBUG_INSN_P (curr_insn
))
4790 curr_id
= lra_get_insn_recog_data (curr_insn
);
4792 if ((set
= single_set (curr_insn
)) != NULL_RTX
&& REG_P (SET_DEST (set
))
4793 && (regno
= REGNO (SET_DEST (set
))) >= FIRST_PSEUDO_REGISTER
4794 && bitmap_bit_p (&check_only_regs
, regno
)
4795 && ! bitmap_bit_p (&live_regs
, regno
))
4797 /* See which defined values die here. */
4798 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
4799 if (reg
->type
== OP_OUT
&& ! reg
->subreg_p
)
4800 bitmap_clear_bit (&live_regs
, reg
->regno
);
4801 /* Mark each used value as live. */
4802 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
4803 if (reg
->type
!= OP_OUT
4804 && bitmap_bit_p (&check_only_regs
, reg
->regno
))
4805 bitmap_set_bit (&live_regs
, reg
->regno
);
4806 /* It is quite important to remove dead move insns because it
4807 means removing dead store. We don't need to process them for
4811 if (lra_dump_file
!= NULL
)
4813 fprintf (lra_dump_file
, " Removing dead insn:\n ");
4814 dump_insn_slim (lra_dump_file
, curr_insn
);
4816 lra_set_insn_deleted (curr_insn
);
4821 /* The structure describes info to do an inheritance for the current
4822 insn. We need to collect such info first before doing the
4823 transformations because the transformations change the insn
4824 internal representation. */
4827 /* Original regno. */
4829 /* Subsequent insns which can inherit original reg value. */
4833 /* Array containing all info for doing inheritance from the current
4835 static struct to_inherit to_inherit
[LRA_MAX_INSN_RELOADS
];
4837 /* Number elements in the previous array. */
4838 static int to_inherit_num
;
4840 /* Add inheritance info REGNO and INSNS. Their meaning is described in
4841 structure to_inherit. */
4843 add_to_inherit (int regno
, rtx insns
)
4847 for (i
= 0; i
< to_inherit_num
; i
++)
4848 if (to_inherit
[i
].regno
== regno
)
4850 lra_assert (to_inherit_num
< LRA_MAX_INSN_RELOADS
);
4851 to_inherit
[to_inherit_num
].regno
= regno
;
4852 to_inherit
[to_inherit_num
++].insns
= insns
;
4855 /* Return the last non-debug insn in basic block BB, or the block begin
4858 get_last_insertion_point (basic_block bb
)
4862 FOR_BB_INSNS_REVERSE (bb
, insn
)
4863 if (NONDEBUG_INSN_P (insn
) || NOTE_INSN_BASIC_BLOCK_P (insn
))
4868 /* Set up RES by registers living on edges FROM except the edge (FROM,
4869 TO) or by registers set up in a jump insn in BB FROM. */
4871 get_live_on_other_edges (basic_block from
, basic_block to
, bitmap res
)
4874 struct lra_insn_reg
*reg
;
4878 lra_assert (to
!= NULL
);
4880 FOR_EACH_EDGE (e
, ei
, from
->succs
)
4882 bitmap_ior_into (res
, df_get_live_in (e
->dest
));
4883 last
= get_last_insertion_point (from
);
4884 if (! JUMP_P (last
))
4886 curr_id
= lra_get_insn_recog_data (last
);
4887 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
4888 if (reg
->type
!= OP_IN
)
4889 bitmap_set_bit (res
, reg
->regno
);
4892 /* Used as a temporary results of some bitmap calculations. */
4893 static bitmap_head temp_bitmap
;
4895 /* Do inheritance/split transformations in EBB starting with HEAD and
4896 finishing on TAIL. We process EBB insns in the reverse order.
4897 Return true if we did any inheritance/split transformation in the
4900 We should avoid excessive splitting which results in worse code
4901 because of inaccurate cost calculations for spilling new split
4902 pseudos in such case. To achieve this we do splitting only if
4903 register pressure is high in given basic block and there are reload
4904 pseudos requiring hard registers. We could do more register
4905 pressure calculations at any given program point to avoid necessary
4906 splitting even more but it is to expensive and the current approach
4907 works well enough. */
4909 inherit_in_ebb (rtx head
, rtx tail
)
4911 int i
, src_regno
, dst_regno
, nregs
;
4912 bool change_p
, succ_p
;
4913 rtx prev_insn
, next_usage_insns
, set
, last_insn
;
4915 struct lra_insn_reg
*reg
;
4916 basic_block last_processed_bb
, curr_bb
= NULL
;
4917 HARD_REG_SET potential_reload_hard_regs
, live_hard_regs
;
4921 bool head_p
, after_p
;
4924 curr_usage_insns_check
++;
4925 reloads_num
= calls_num
= 0;
4926 bitmap_clear (&check_only_regs
);
4927 last_processed_bb
= NULL
;
4928 CLEAR_HARD_REG_SET (potential_reload_hard_regs
);
4929 CLEAR_HARD_REG_SET (live_hard_regs
);
4930 /* We don't process new insns generated in the loop. */
4931 for (curr_insn
= tail
; curr_insn
!= PREV_INSN (head
); curr_insn
= prev_insn
)
4933 prev_insn
= PREV_INSN (curr_insn
);
4934 if (BLOCK_FOR_INSN (curr_insn
) != NULL
)
4935 curr_bb
= BLOCK_FOR_INSN (curr_insn
);
4936 if (last_processed_bb
!= curr_bb
)
4938 /* We are at the end of BB. Add qualified living
4939 pseudos for potential splitting. */
4940 to_process
= df_get_live_out (curr_bb
);
4941 if (last_processed_bb
!= NULL
)
4943 /* We are somewhere in the middle of EBB. */
4944 get_live_on_other_edges (curr_bb
, last_processed_bb
,
4946 to_process
= &temp_bitmap
;
4948 last_processed_bb
= curr_bb
;
4949 last_insn
= get_last_insertion_point (curr_bb
);
4950 after_p
= (! JUMP_P (last_insn
)
4951 && (! CALL_P (last_insn
)
4952 || (find_reg_note (last_insn
,
4953 REG_NORETURN
, NULL_RTX
) == NULL_RTX
4954 && ! SIBLING_CALL_P (last_insn
))));
4955 REG_SET_TO_HARD_REG_SET (live_hard_regs
, df_get_live_out (curr_bb
));
4956 IOR_HARD_REG_SET (live_hard_regs
, eliminable_regset
);
4957 IOR_HARD_REG_SET (live_hard_regs
, lra_no_alloc_regs
);
4958 CLEAR_HARD_REG_SET (potential_reload_hard_regs
);
4959 EXECUTE_IF_SET_IN_BITMAP (to_process
, 0, j
, bi
)
4961 if ((int) j
>= lra_constraint_new_regno_start
)
4963 if (j
< FIRST_PSEUDO_REGISTER
|| reg_renumber
[j
] >= 0)
4965 if (j
< FIRST_PSEUDO_REGISTER
)
4966 SET_HARD_REG_BIT (live_hard_regs
, j
);
4968 add_to_hard_reg_set (&live_hard_regs
,
4969 PSEUDO_REGNO_MODE (j
),
4971 setup_next_usage_insn (j
, last_insn
, reloads_num
, after_p
);
4975 src_regno
= dst_regno
= -1;
4976 if (NONDEBUG_INSN_P (curr_insn
)
4977 && (set
= single_set (curr_insn
)) != NULL_RTX
4978 && REG_P (SET_DEST (set
)) && REG_P (SET_SRC (set
)))
4980 src_regno
= REGNO (SET_SRC (set
));
4981 dst_regno
= REGNO (SET_DEST (set
));
4983 if (src_regno
< lra_constraint_new_regno_start
4984 && src_regno
>= FIRST_PSEUDO_REGISTER
4985 && reg_renumber
[src_regno
] < 0
4986 && dst_regno
>= lra_constraint_new_regno_start
4987 && (cl
= lra_get_allocno_class (dst_regno
)) != NO_REGS
)
4989 /* 'reload_pseudo <- original_pseudo'. */
4992 if (usage_insns
[src_regno
].check
== curr_usage_insns_check
4993 && (next_usage_insns
= usage_insns
[src_regno
].insns
) != NULL_RTX
)
4994 succ_p
= inherit_reload_reg (false, src_regno
, cl
,
4995 curr_insn
, next_usage_insns
);
4999 setup_next_usage_insn (src_regno
, curr_insn
, reloads_num
, false);
5000 if (hard_reg_set_subset_p (reg_class_contents
[cl
], live_hard_regs
))
5001 IOR_HARD_REG_SET (potential_reload_hard_regs
,
5002 reg_class_contents
[cl
]);
5004 else if (src_regno
>= lra_constraint_new_regno_start
5005 && dst_regno
< lra_constraint_new_regno_start
5006 && dst_regno
>= FIRST_PSEUDO_REGISTER
5007 && reg_renumber
[dst_regno
] < 0
5008 && (cl
= lra_get_allocno_class (src_regno
)) != NO_REGS
5009 && usage_insns
[dst_regno
].check
== curr_usage_insns_check
5010 && (next_usage_insns
5011 = usage_insns
[dst_regno
].insns
) != NULL_RTX
)
5014 /* 'original_pseudo <- reload_pseudo'. */
5015 if (! JUMP_P (curr_insn
)
5016 && inherit_reload_reg (true, dst_regno
, cl
,
5017 curr_insn
, next_usage_insns
))
5020 usage_insns
[dst_regno
].check
= 0;
5021 if (hard_reg_set_subset_p (reg_class_contents
[cl
], live_hard_regs
))
5022 IOR_HARD_REG_SET (potential_reload_hard_regs
,
5023 reg_class_contents
[cl
]);
5025 else if (INSN_P (curr_insn
))
5028 int max_uid
= get_max_uid ();
5030 curr_id
= lra_get_insn_recog_data (curr_insn
);
5031 curr_static_id
= curr_id
->insn_static_data
;
5033 /* Process insn definitions. */
5034 for (iter
= 0; iter
< 2; iter
++)
5035 for (reg
= iter
== 0 ? curr_id
->regs
: curr_static_id
->hard_regs
;
5038 if (reg
->type
!= OP_IN
5039 && (dst_regno
= reg
->regno
) < lra_constraint_new_regno_start
)
5041 if (dst_regno
>= FIRST_PSEUDO_REGISTER
&& reg
->type
== OP_OUT
5042 && reg_renumber
[dst_regno
] < 0 && ! reg
->subreg_p
5043 && usage_insns
[dst_regno
].check
== curr_usage_insns_check
5044 && (next_usage_insns
5045 = usage_insns
[dst_regno
].insns
) != NULL_RTX
)
5047 struct lra_insn_reg
*r
;
5049 for (r
= curr_id
->regs
; r
!= NULL
; r
= r
->next
)
5050 if (r
->type
!= OP_OUT
&& r
->regno
== dst_regno
)
5052 /* Don't do inheritance if the pseudo is also
5053 used in the insn. */
5055 /* We can not do inheritance right now
5056 because the current insn reg info (chain
5057 regs) can change after that. */
5058 add_to_inherit (dst_regno
, next_usage_insns
);
5060 /* We can not process one reg twice here because of
5061 usage_insns invalidation. */
5062 if ((dst_regno
< FIRST_PSEUDO_REGISTER
5063 || reg_renumber
[dst_regno
] >= 0)
5064 && ! reg
->subreg_p
&& reg
->type
!= OP_IN
)
5068 if (split_if_necessary (dst_regno
, reg
->biggest_mode
,
5069 potential_reload_hard_regs
,
5070 false, curr_insn
, max_uid
))
5072 CLEAR_HARD_REG_SET (s
);
5073 if (dst_regno
< FIRST_PSEUDO_REGISTER
)
5074 add_to_hard_reg_set (&s
, reg
->biggest_mode
, dst_regno
);
5076 add_to_hard_reg_set (&s
, PSEUDO_REGNO_MODE (dst_regno
),
5077 reg_renumber
[dst_regno
]);
5078 AND_COMPL_HARD_REG_SET (live_hard_regs
, s
);
5080 /* We should invalidate potential inheritance or
5081 splitting for the current insn usages to the next
5082 usage insns (see code below) as the output pseudo
5084 if ((dst_regno
>= FIRST_PSEUDO_REGISTER
5085 && reg_renumber
[dst_regno
] < 0)
5086 || (reg
->type
== OP_OUT
&& ! reg
->subreg_p
5087 && (dst_regno
< FIRST_PSEUDO_REGISTER
5088 || reg_renumber
[dst_regno
] >= 0)))
5090 /* Invalidate and mark definitions. */
5091 if (dst_regno
>= FIRST_PSEUDO_REGISTER
)
5092 usage_insns
[dst_regno
].check
= -(int) INSN_UID (curr_insn
);
5095 nregs
= hard_regno_nregs
[dst_regno
][reg
->biggest_mode
];
5096 for (i
= 0; i
< nregs
; i
++)
5097 usage_insns
[dst_regno
+ i
].check
5098 = -(int) INSN_UID (curr_insn
);
5102 if (! JUMP_P (curr_insn
))
5103 for (i
= 0; i
< to_inherit_num
; i
++)
5104 if (inherit_reload_reg (true, to_inherit
[i
].regno
,
5105 ALL_REGS
, curr_insn
,
5106 to_inherit
[i
].insns
))
5108 if (CALL_P (curr_insn
))
5110 rtx cheap
, pat
, dest
, restore
;
5111 int regno
, hard_regno
;
5114 if ((cheap
= find_reg_note (curr_insn
,
5115 REG_RETURNED
, NULL_RTX
)) != NULL_RTX
5116 && ((cheap
= XEXP (cheap
, 0)), true)
5117 && (regno
= REGNO (cheap
)) >= FIRST_PSEUDO_REGISTER
5118 && (hard_regno
= reg_renumber
[regno
]) >= 0
5119 /* If there are pending saves/restores, the
5120 optimization is not worth. */
5121 && usage_insns
[regno
].calls_num
== calls_num
- 1
5122 && TEST_HARD_REG_BIT (call_used_reg_set
, hard_regno
))
5124 /* Restore the pseudo from the call result as
5125 REG_RETURNED note says that the pseudo value is
5126 in the call result and the pseudo is an argument
5128 pat
= PATTERN (curr_insn
);
5129 if (GET_CODE (pat
) == PARALLEL
)
5130 pat
= XVECEXP (pat
, 0, 0);
5131 dest
= SET_DEST (pat
);
5133 emit_move_insn (cheap
, copy_rtx (dest
));
5134 restore
= get_insns ();
5136 lra_process_new_insns (curr_insn
, NULL
, restore
,
5137 "Inserting call parameter restore");
5138 /* We don't need to save/restore of the pseudo from
5140 usage_insns
[regno
].calls_num
= calls_num
;
5141 bitmap_set_bit (&check_only_regs
, regno
);
5145 /* Process insn usages. */
5146 for (iter
= 0; iter
< 2; iter
++)
5147 for (reg
= iter
== 0 ? curr_id
->regs
: curr_static_id
->hard_regs
;
5150 if ((reg
->type
!= OP_OUT
5151 || (reg
->type
== OP_OUT
&& reg
->subreg_p
))
5152 && (src_regno
= reg
->regno
) < lra_constraint_new_regno_start
)
5154 if (src_regno
>= FIRST_PSEUDO_REGISTER
5155 && reg_renumber
[src_regno
] < 0 && reg
->type
== OP_IN
)
5157 if (usage_insns
[src_regno
].check
== curr_usage_insns_check
5158 && (next_usage_insns
5159 = usage_insns
[src_regno
].insns
) != NULL_RTX
5160 && NONDEBUG_INSN_P (curr_insn
))
5161 add_to_inherit (src_regno
, next_usage_insns
);
5162 else if (usage_insns
[src_regno
].check
5163 != -(int) INSN_UID (curr_insn
))
5164 /* Add usages but only if the reg is not set up
5165 in the same insn. */
5166 add_next_usage_insn (src_regno
, curr_insn
, reloads_num
);
5168 else if (src_regno
< FIRST_PSEUDO_REGISTER
5169 || reg_renumber
[src_regno
] >= 0)
5172 rtx use_insn
= curr_insn
;
5174 before_p
= (JUMP_P (curr_insn
)
5175 || (CALL_P (curr_insn
) && reg
->type
== OP_IN
));
5176 if (NONDEBUG_INSN_P (curr_insn
)
5177 && split_if_necessary (src_regno
, reg
->biggest_mode
,
5178 potential_reload_hard_regs
,
5179 before_p
, curr_insn
, max_uid
))
5182 lra_risky_transformations_p
= true;
5185 usage_insns
[src_regno
].check
= 0;
5187 use_insn
= PREV_INSN (curr_insn
);
5189 if (NONDEBUG_INSN_P (curr_insn
))
5191 if (src_regno
< FIRST_PSEUDO_REGISTER
)
5192 add_to_hard_reg_set (&live_hard_regs
,
5193 reg
->biggest_mode
, src_regno
);
5195 add_to_hard_reg_set (&live_hard_regs
,
5196 PSEUDO_REGNO_MODE (src_regno
),
5197 reg_renumber
[src_regno
]);
5199 add_next_usage_insn (src_regno
, use_insn
, reloads_num
);
5202 for (i
= 0; i
< to_inherit_num
; i
++)
5204 src_regno
= to_inherit
[i
].regno
;
5205 if (inherit_reload_reg (false, src_regno
, ALL_REGS
,
5206 curr_insn
, to_inherit
[i
].insns
))
5209 setup_next_usage_insn (src_regno
, curr_insn
, reloads_num
, false);
5212 /* We reached the start of the current basic block. */
5213 if (prev_insn
== NULL_RTX
|| prev_insn
== PREV_INSN (head
)
5214 || BLOCK_FOR_INSN (prev_insn
) != curr_bb
)
5216 /* We reached the beginning of the current block -- do
5217 rest of spliting in the current BB. */
5218 to_process
= df_get_live_in (curr_bb
);
5219 if (BLOCK_FOR_INSN (head
) != curr_bb
)
5221 /* We are somewhere in the middle of EBB. */
5222 get_live_on_other_edges (EDGE_PRED (curr_bb
, 0)->src
,
5223 curr_bb
, &temp_bitmap
);
5224 to_process
= &temp_bitmap
;
5227 EXECUTE_IF_SET_IN_BITMAP (to_process
, 0, j
, bi
)
5229 if ((int) j
>= lra_constraint_new_regno_start
)
5231 if (((int) j
< FIRST_PSEUDO_REGISTER
|| reg_renumber
[j
] >= 0)
5232 && usage_insns
[j
].check
== curr_usage_insns_check
5233 && (next_usage_insns
= usage_insns
[j
].insns
) != NULL_RTX
)
5235 if (need_for_split_p (potential_reload_hard_regs
, j
))
5237 if (lra_dump_file
!= NULL
&& head_p
)
5239 fprintf (lra_dump_file
,
5240 " ----------------------------------\n");
5243 if (split_reg (false, j
, bb_note (curr_bb
),
5247 usage_insns
[j
].check
= 0;
5255 /* This value affects EBB forming. If probability of edge from EBB to
5256 a BB is not greater than the following value, we don't add the BB
5258 #define EBB_PROBABILITY_CUTOFF ((REG_BR_PROB_BASE * 50) / 100)
5260 /* Current number of inheritance/split iteration. */
5261 int lra_inheritance_iter
;
5263 /* Entry function for inheritance/split pass. */
5265 lra_inheritance (void)
5268 basic_block bb
, start_bb
;
5271 lra_inheritance_iter
++;
5272 if (lra_inheritance_iter
> LRA_MAX_INHERITANCE_PASSES
)
5274 timevar_push (TV_LRA_INHERITANCE
);
5275 if (lra_dump_file
!= NULL
)
5276 fprintf (lra_dump_file
, "\n********** Inheritance #%d: **********\n\n",
5277 lra_inheritance_iter
);
5278 curr_usage_insns_check
= 0;
5279 usage_insns
= XNEWVEC (struct usage_insns
, lra_constraint_new_regno_start
);
5280 for (i
= 0; i
< lra_constraint_new_regno_start
; i
++)
5281 usage_insns
[i
].check
= 0;
5282 bitmap_initialize (&check_only_regs
, ®_obstack
);
5283 bitmap_initialize (&live_regs
, ®_obstack
);
5284 bitmap_initialize (&temp_bitmap
, ®_obstack
);
5285 bitmap_initialize (&ebb_global_regs
, ®_obstack
);
5289 if (lra_dump_file
!= NULL
)
5290 fprintf (lra_dump_file
, "EBB");
5291 /* Form a EBB starting with BB. */
5292 bitmap_clear (&ebb_global_regs
);
5293 bitmap_ior_into (&ebb_global_regs
, df_get_live_in (bb
));
5296 if (lra_dump_file
!= NULL
)
5297 fprintf (lra_dump_file
, " %d", bb
->index
);
5298 if (bb
->next_bb
== EXIT_BLOCK_PTR_FOR_FN (cfun
)
5299 || LABEL_P (BB_HEAD (bb
->next_bb
)))
5301 e
= find_fallthru_edge (bb
->succs
);
5304 if (e
->probability
<= EBB_PROBABILITY_CUTOFF
)
5308 bitmap_ior_into (&ebb_global_regs
, df_get_live_out (bb
));
5309 if (lra_dump_file
!= NULL
)
5310 fprintf (lra_dump_file
, "\n");
5311 if (inherit_in_ebb (BB_HEAD (start_bb
), BB_END (bb
)))
5312 /* Remember that the EBB head and tail can change in
5314 update_ebb_live_info (BB_HEAD (start_bb
), BB_END (bb
));
5316 bitmap_clear (&ebb_global_regs
);
5317 bitmap_clear (&temp_bitmap
);
5318 bitmap_clear (&live_regs
);
5319 bitmap_clear (&check_only_regs
);
5322 timevar_pop (TV_LRA_INHERITANCE
);
5327 /* This page contains code to undo failed inheritance/split
5330 /* Current number of iteration undoing inheritance/split. */
5331 int lra_undo_inheritance_iter
;
5333 /* Fix BB live info LIVE after removing pseudos created on pass doing
5334 inheritance/split which are REMOVED_PSEUDOS. */
5336 fix_bb_live_info (bitmap live
, bitmap removed_pseudos
)
5341 EXECUTE_IF_SET_IN_BITMAP (removed_pseudos
, 0, regno
, bi
)
5342 if (bitmap_clear_bit (live
, regno
))
5343 bitmap_set_bit (live
, lra_reg_info
[regno
].restore_regno
);
5346 /* Return regno of the (subreg of) REG. Otherwise, return a negative
5351 if (GET_CODE (reg
) == SUBREG
)
5352 reg
= SUBREG_REG (reg
);
5358 /* Remove inheritance/split pseudos which are in REMOVE_PSEUDOS and
5359 return true if we did any change. The undo transformations for
5360 inheritance looks like
5364 p <- i, i <- p, and i <- i3
5365 where p is original pseudo from which inheritance pseudo i was
5366 created, i and i3 are removed inheritance pseudos, i2 is another
5367 not removed inheritance pseudo. All split pseudos or other
5368 occurrences of removed inheritance pseudos are changed on the
5369 corresponding original pseudos.
5371 The function also schedules insns changed and created during
5372 inheritance/split pass for processing by the subsequent constraint
5375 remove_inheritance_pseudos (bitmap remove_pseudos
)
5378 int regno
, sregno
, prev_sregno
, dregno
, restore_regno
;
5379 rtx set
, prev_set
, prev_insn
;
5380 bool change_p
, done_p
;
5382 change_p
= ! bitmap_empty_p (remove_pseudos
);
5383 /* We can not finish the function right away if CHANGE_P is true
5384 because we need to marks insns affected by previous
5385 inheritance/split pass for processing by the subsequent
5389 fix_bb_live_info (df_get_live_in (bb
), remove_pseudos
);
5390 fix_bb_live_info (df_get_live_out (bb
), remove_pseudos
);
5391 FOR_BB_INSNS_REVERSE (bb
, curr_insn
)
5393 if (! INSN_P (curr_insn
))
5396 sregno
= dregno
= -1;
5397 if (change_p
&& NONDEBUG_INSN_P (curr_insn
)
5398 && (set
= single_set (curr_insn
)) != NULL_RTX
)
5400 dregno
= get_regno (SET_DEST (set
));
5401 sregno
= get_regno (SET_SRC (set
));
5404 if (sregno
>= 0 && dregno
>= 0)
5406 if ((bitmap_bit_p (remove_pseudos
, sregno
)
5407 && (lra_reg_info
[sregno
].restore_regno
== dregno
5408 || (bitmap_bit_p (remove_pseudos
, dregno
)
5409 && (lra_reg_info
[sregno
].restore_regno
5410 == lra_reg_info
[dregno
].restore_regno
))))
5411 || (bitmap_bit_p (remove_pseudos
, dregno
)
5412 && lra_reg_info
[dregno
].restore_regno
== sregno
))
5413 /* One of the following cases:
5414 original <- removed inheritance pseudo
5415 removed inherit pseudo <- another removed inherit pseudo
5416 removed inherit pseudo <- original pseudo
5418 removed_split_pseudo <- original_reg
5419 original_reg <- removed_split_pseudo */
5421 if (lra_dump_file
!= NULL
)
5423 fprintf (lra_dump_file
, " Removing %s:\n",
5424 bitmap_bit_p (&lra_split_regs
, sregno
)
5425 || bitmap_bit_p (&lra_split_regs
, dregno
)
5426 ? "split" : "inheritance");
5427 dump_insn_slim (lra_dump_file
, curr_insn
);
5429 lra_set_insn_deleted (curr_insn
);
5432 else if (bitmap_bit_p (remove_pseudos
, sregno
)
5433 && bitmap_bit_p (&lra_inheritance_pseudos
, sregno
))
5435 /* Search the following pattern:
5436 inherit_or_split_pseudo1 <- inherit_or_split_pseudo2
5437 original_pseudo <- inherit_or_split_pseudo1
5438 where the 2nd insn is the current insn and
5439 inherit_or_split_pseudo2 is not removed. If it is found,
5440 change the current insn onto:
5441 original_pseudo <- inherit_or_split_pseudo2. */
5442 for (prev_insn
= PREV_INSN (curr_insn
);
5443 prev_insn
!= NULL_RTX
&& ! NONDEBUG_INSN_P (prev_insn
);
5444 prev_insn
= PREV_INSN (prev_insn
))
5446 if (prev_insn
!= NULL_RTX
&& BLOCK_FOR_INSN (prev_insn
) == bb
5447 && (prev_set
= single_set (prev_insn
)) != NULL_RTX
5448 /* There should be no subregs in insn we are
5449 searching because only the original reg might
5450 be in subreg when we changed the mode of
5451 load/store for splitting. */
5452 && REG_P (SET_DEST (prev_set
))
5453 && REG_P (SET_SRC (prev_set
))
5454 && (int) REGNO (SET_DEST (prev_set
)) == sregno
5455 && ((prev_sregno
= REGNO (SET_SRC (prev_set
)))
5456 >= FIRST_PSEUDO_REGISTER
)
5457 /* As we consider chain of inheritance or
5458 splitting described in above comment we should
5459 check that sregno and prev_sregno were
5460 inheritance/split pseudos created from the
5461 same original regno. */
5462 && (lra_reg_info
[sregno
].restore_regno
5463 == lra_reg_info
[prev_sregno
].restore_regno
)
5464 && ! bitmap_bit_p (remove_pseudos
, prev_sregno
))
5466 lra_assert (GET_MODE (SET_SRC (prev_set
))
5467 == GET_MODE (regno_reg_rtx
[sregno
]));
5468 if (GET_CODE (SET_SRC (set
)) == SUBREG
)
5469 SUBREG_REG (SET_SRC (set
)) = SET_SRC (prev_set
);
5471 SET_SRC (set
) = SET_SRC (prev_set
);
5472 lra_push_insn_and_update_insn_regno_info (curr_insn
);
5473 lra_set_used_insn_alternative_by_uid
5474 (INSN_UID (curr_insn
), -1);
5476 if (lra_dump_file
!= NULL
)
5478 fprintf (lra_dump_file
, " Change reload insn:\n");
5479 dump_insn_slim (lra_dump_file
, curr_insn
);
5486 struct lra_insn_reg
*reg
;
5487 bool restored_regs_p
= false;
5488 bool kept_regs_p
= false;
5490 curr_id
= lra_get_insn_recog_data (curr_insn
);
5491 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
5494 restore_regno
= lra_reg_info
[regno
].restore_regno
;
5495 if (restore_regno
>= 0)
5497 if (change_p
&& bitmap_bit_p (remove_pseudos
, regno
))
5499 substitute_pseudo (&curr_insn
, regno
,
5500 regno_reg_rtx
[restore_regno
]);
5501 restored_regs_p
= true;
5507 if (NONDEBUG_INSN_P (curr_insn
) && kept_regs_p
)
5509 /* The instruction has changed since the previous
5510 constraints pass. */
5511 lra_push_insn_and_update_insn_regno_info (curr_insn
);
5512 lra_set_used_insn_alternative_by_uid
5513 (INSN_UID (curr_insn
), -1);
5515 else if (restored_regs_p
)
5516 /* The instruction has been restored to the form that
5517 it had during the previous constraints pass. */
5518 lra_update_insn_regno_info (curr_insn
);
5519 if (restored_regs_p
&& lra_dump_file
!= NULL
)
5521 fprintf (lra_dump_file
, " Insn after restoring regs:\n");
5522 dump_insn_slim (lra_dump_file
, curr_insn
);
5530 /* If optional reload pseudos failed to get a hard register or was not
5531 inherited, it is better to remove optional reloads. We do this
5532 transformation after undoing inheritance to figure out necessity to
5533 remove optional reloads easier. Return true if we do any
5536 undo_optional_reloads (void)
5538 bool change_p
, keep_p
;
5539 unsigned int regno
, uid
;
5540 bitmap_iterator bi
, bi2
;
5541 rtx insn
, set
, src
, dest
;
5542 bitmap_head removed_optional_reload_pseudos
, insn_bitmap
;
5544 bitmap_initialize (&removed_optional_reload_pseudos
, ®_obstack
);
5545 bitmap_copy (&removed_optional_reload_pseudos
, &lra_optional_reload_pseudos
);
5546 EXECUTE_IF_SET_IN_BITMAP (&lra_optional_reload_pseudos
, 0, regno
, bi
)
5549 /* Keep optional reloads from previous subpasses. */
5550 if (lra_reg_info
[regno
].restore_regno
< 0
5551 /* If the original pseudo changed its allocation, just
5552 removing the optional pseudo is dangerous as the original
5553 pseudo will have longer live range. */
5554 || reg_renumber
[lra_reg_info
[regno
].restore_regno
] >= 0)
5556 else if (reg_renumber
[regno
] >= 0)
5557 EXECUTE_IF_SET_IN_BITMAP (&lra_reg_info
[regno
].insn_bitmap
, 0, uid
, bi2
)
5559 insn
= lra_insn_recog_data
[uid
]->insn
;
5560 if ((set
= single_set (insn
)) == NULL_RTX
)
5562 src
= SET_SRC (set
);
5563 dest
= SET_DEST (set
);
5564 if (! REG_P (src
) || ! REG_P (dest
))
5566 if (REGNO (dest
) == regno
5567 /* Ignore insn for optional reloads itself. */
5568 && lra_reg_info
[regno
].restore_regno
!= (int) REGNO (src
)
5569 /* Check only inheritance on last inheritance pass. */
5570 && (int) REGNO (src
) >= new_regno_start
5571 /* Check that the optional reload was inherited. */
5572 && bitmap_bit_p (&lra_inheritance_pseudos
, REGNO (src
)))
5580 bitmap_clear_bit (&removed_optional_reload_pseudos
, regno
);
5581 if (lra_dump_file
!= NULL
)
5582 fprintf (lra_dump_file
, "Keep optional reload reg %d\n", regno
);
5585 change_p
= ! bitmap_empty_p (&removed_optional_reload_pseudos
);
5586 bitmap_initialize (&insn_bitmap
, ®_obstack
);
5587 EXECUTE_IF_SET_IN_BITMAP (&removed_optional_reload_pseudos
, 0, regno
, bi
)
5589 if (lra_dump_file
!= NULL
)
5590 fprintf (lra_dump_file
, "Remove optional reload reg %d\n", regno
);
5591 bitmap_copy (&insn_bitmap
, &lra_reg_info
[regno
].insn_bitmap
);
5592 EXECUTE_IF_SET_IN_BITMAP (&insn_bitmap
, 0, uid
, bi2
)
5594 insn
= lra_insn_recog_data
[uid
]->insn
;
5595 if ((set
= single_set (insn
)) != NULL_RTX
)
5597 src
= SET_SRC (set
);
5598 dest
= SET_DEST (set
);
5599 if (REG_P (src
) && REG_P (dest
)
5600 && ((REGNO (src
) == regno
5601 && (lra_reg_info
[regno
].restore_regno
5602 == (int) REGNO (dest
)))
5603 || (REGNO (dest
) == regno
5604 && (lra_reg_info
[regno
].restore_regno
5605 == (int) REGNO (src
)))))
5607 if (lra_dump_file
!= NULL
)
5609 fprintf (lra_dump_file
, " Deleting move %u\n",
5611 dump_insn_slim (lra_dump_file
, insn
);
5613 lra_set_insn_deleted (insn
);
5616 /* We should not worry about generation memory-memory
5617 moves here as if the corresponding inheritance did
5618 not work (inheritance pseudo did not get a hard reg),
5619 we remove the inheritance pseudo and the optional
5622 substitute_pseudo (&insn
, regno
,
5623 regno_reg_rtx
[lra_reg_info
[regno
].restore_regno
]);
5624 lra_update_insn_regno_info (insn
);
5625 if (lra_dump_file
!= NULL
)
5627 fprintf (lra_dump_file
,
5628 " Restoring original insn:\n");
5629 dump_insn_slim (lra_dump_file
, insn
);
5633 /* Clear restore_regnos. */
5634 EXECUTE_IF_SET_IN_BITMAP (&lra_optional_reload_pseudos
, 0, regno
, bi
)
5635 lra_reg_info
[regno
].restore_regno
= -1;
5636 bitmap_clear (&insn_bitmap
);
5637 bitmap_clear (&removed_optional_reload_pseudos
);
5641 /* Entry function for undoing inheritance/split transformation. Return true
5642 if we did any RTL change in this pass. */
5644 lra_undo_inheritance (void)
5647 int restore_regno
, hard_regno
;
5648 int n_all_inherit
, n_inherit
, n_all_split
, n_split
;
5649 bitmap_head remove_pseudos
;
5653 lra_undo_inheritance_iter
++;
5654 if (lra_undo_inheritance_iter
> LRA_MAX_INHERITANCE_PASSES
)
5656 if (lra_dump_file
!= NULL
)
5657 fprintf (lra_dump_file
,
5658 "\n********** Undoing inheritance #%d: **********\n\n",
5659 lra_undo_inheritance_iter
);
5660 bitmap_initialize (&remove_pseudos
, ®_obstack
);
5661 n_inherit
= n_all_inherit
= 0;
5662 EXECUTE_IF_SET_IN_BITMAP (&lra_inheritance_pseudos
, 0, regno
, bi
)
5663 if (lra_reg_info
[regno
].restore_regno
>= 0)
5666 if (reg_renumber
[regno
] < 0
5667 /* If the original pseudo changed its allocation, just
5668 removing inheritance is dangerous as for changing
5669 allocation we used shorter live-ranges. */
5670 && reg_renumber
[lra_reg_info
[regno
].restore_regno
] < 0)
5671 bitmap_set_bit (&remove_pseudos
, regno
);
5675 if (lra_dump_file
!= NULL
&& n_all_inherit
!= 0)
5676 fprintf (lra_dump_file
, "Inherit %d out of %d (%.2f%%)\n",
5677 n_inherit
, n_all_inherit
,
5678 (double) n_inherit
/ n_all_inherit
* 100);
5679 n_split
= n_all_split
= 0;
5680 EXECUTE_IF_SET_IN_BITMAP (&lra_split_regs
, 0, regno
, bi
)
5681 if ((restore_regno
= lra_reg_info
[regno
].restore_regno
) >= 0)
5684 hard_regno
= (restore_regno
>= FIRST_PSEUDO_REGISTER
5685 ? reg_renumber
[restore_regno
] : restore_regno
);
5686 if (hard_regno
< 0 || reg_renumber
[regno
] == hard_regno
)
5687 bitmap_set_bit (&remove_pseudos
, regno
);
5691 if (lra_dump_file
!= NULL
)
5692 fprintf (lra_dump_file
, " Keep split r%d (orig=r%d)\n",
5693 regno
, restore_regno
);
5696 if (lra_dump_file
!= NULL
&& n_all_split
!= 0)
5697 fprintf (lra_dump_file
, "Split %d out of %d (%.2f%%)\n",
5698 n_split
, n_all_split
,
5699 (double) n_split
/ n_all_split
* 100);
5700 change_p
= remove_inheritance_pseudos (&remove_pseudos
);
5701 bitmap_clear (&remove_pseudos
);
5702 /* Clear restore_regnos. */
5703 EXECUTE_IF_SET_IN_BITMAP (&lra_inheritance_pseudos
, 0, regno
, bi
)
5704 lra_reg_info
[regno
].restore_regno
= -1;
5705 EXECUTE_IF_SET_IN_BITMAP (&lra_split_regs
, 0, regno
, bi
)
5706 lra_reg_info
[regno
].restore_regno
= -1;
5707 change_p
= undo_optional_reloads () || change_p
;