1 /* Expand the basic unary and binary arithmetic operations, for GNU compiler.
2 Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010,
4 2011, 2012 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 3, or (at your option) any later
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
25 #include "coretypes.h"
27 #include "diagnostic-core.h"
29 /* Include insn-config.h before expr.h so that HAVE_conditional_move
30 is properly defined. */
31 #include "insn-config.h"
44 #include "basic-block.h"
47 struct target_optabs default_target_optabs
;
48 struct target_libfuncs default_target_libfuncs
;
50 struct target_optabs
*this_target_optabs
= &default_target_optabs
;
51 struct target_libfuncs
*this_target_libfuncs
= &default_target_libfuncs
;
54 #define libfunc_hash \
55 (this_target_libfuncs->x_libfunc_hash)
57 static void prepare_float_lib_cmp (rtx
, rtx
, enum rtx_code
, rtx
*,
59 static rtx
expand_unop_direct (enum machine_mode
, optab
, rtx
, rtx
, int);
60 static void emit_libcall_block_1 (rtx
, rtx
, rtx
, rtx
, bool);
62 /* Debug facility for use in GDB. */
63 void debug_optab_libfuncs (void);
65 /* Prefixes for the current version of decimal floating point (BID vs. DPD) */
66 #if ENABLE_DECIMAL_BID_FORMAT
67 #define DECIMAL_PREFIX "bid_"
69 #define DECIMAL_PREFIX "dpd_"
72 /* Used for libfunc_hash. */
75 hash_libfunc (const void *p
)
77 const struct libfunc_entry
*const e
= (const struct libfunc_entry
*) p
;
78 return ((e
->mode1
+ e
->mode2
* NUM_MACHINE_MODES
) ^ e
->op
);
81 /* Used for libfunc_hash. */
84 eq_libfunc (const void *p
, const void *q
)
86 const struct libfunc_entry
*const e1
= (const struct libfunc_entry
*) p
;
87 const struct libfunc_entry
*const e2
= (const struct libfunc_entry
*) q
;
88 return e1
->op
== e2
->op
&& e1
->mode1
== e2
->mode1
&& e1
->mode2
== e2
->mode2
;
91 /* Return libfunc corresponding operation defined by OPTAB converting
92 from MODE2 to MODE1. Trigger lazy initialization if needed, return NULL
93 if no libfunc is available. */
95 convert_optab_libfunc (convert_optab optab
, enum machine_mode mode1
,
96 enum machine_mode mode2
)
98 struct libfunc_entry e
;
99 struct libfunc_entry
**slot
;
101 /* ??? This ought to be an assert, but not all of the places
102 that we expand optabs know about the optabs that got moved
104 if (!(optab
>= FIRST_CONV_OPTAB
&& optab
<= LAST_CONVLIB_OPTAB
))
110 slot
= (struct libfunc_entry
**)
111 htab_find_slot (libfunc_hash
, &e
, NO_INSERT
);
114 const struct convert_optab_libcall_d
*d
115 = &convlib_def
[optab
- FIRST_CONV_OPTAB
];
117 if (d
->libcall_gen
== NULL
)
120 d
->libcall_gen (optab
, d
->libcall_basename
, mode1
, mode2
);
121 slot
= (struct libfunc_entry
**)
122 htab_find_slot (libfunc_hash
, &e
, NO_INSERT
);
126 return (*slot
)->libfunc
;
129 /* Return libfunc corresponding operation defined by OPTAB in MODE.
130 Trigger lazy initialization if needed, return NULL if no libfunc is
133 optab_libfunc (optab optab
, enum machine_mode mode
)
135 struct libfunc_entry e
;
136 struct libfunc_entry
**slot
;
138 /* ??? This ought to be an assert, but not all of the places
139 that we expand optabs know about the optabs that got moved
141 if (!(optab
>= FIRST_NORM_OPTAB
&& optab
<= LAST_NORMLIB_OPTAB
))
147 slot
= (struct libfunc_entry
**)
148 htab_find_slot (libfunc_hash
, &e
, NO_INSERT
);
151 const struct optab_libcall_d
*d
152 = &normlib_def
[optab
- FIRST_NORM_OPTAB
];
154 if (d
->libcall_gen
== NULL
)
157 d
->libcall_gen (optab
, d
->libcall_basename
, d
->libcall_suffix
, mode
);
158 slot
= (struct libfunc_entry
**)
159 htab_find_slot (libfunc_hash
, &e
, NO_INSERT
);
163 return (*slot
)->libfunc
;
167 /* Add a REG_EQUAL note to the last insn in INSNS. TARGET is being set to
168 the result of operation CODE applied to OP0 (and OP1 if it is a binary
171 If the last insn does not set TARGET, don't do anything, but return 1.
173 If the last insn or a previous insn sets TARGET and TARGET is one of OP0
174 or OP1, don't add the REG_EQUAL note but return 0. Our caller can then
175 try again, ensuring that TARGET is not one of the operands. */
178 add_equal_note (rtx insns
, rtx target
, enum rtx_code code
, rtx op0
, rtx op1
)
183 gcc_assert (insns
&& INSN_P (insns
) && NEXT_INSN (insns
));
185 if (GET_RTX_CLASS (code
) != RTX_COMM_ARITH
186 && GET_RTX_CLASS (code
) != RTX_BIN_ARITH
187 && GET_RTX_CLASS (code
) != RTX_COMM_COMPARE
188 && GET_RTX_CLASS (code
) != RTX_COMPARE
189 && GET_RTX_CLASS (code
) != RTX_UNARY
)
192 if (GET_CODE (target
) == ZERO_EXTRACT
)
195 /* If TARGET is in OP0 or OP1, punt. We'd end up with a note referencing
196 a value changing in the insn, so the note would be invalid for CSE. */
197 if (reg_overlap_mentioned_p (target
, op0
)
198 || (op1
&& reg_overlap_mentioned_p (target
, op1
)))
201 for (last_insn
= insns
;
202 NEXT_INSN (last_insn
) != NULL_RTX
;
203 last_insn
= NEXT_INSN (last_insn
))
206 set
= single_set (last_insn
);
210 if (! rtx_equal_p (SET_DEST (set
), target
)
211 /* For a STRICT_LOW_PART, the REG_NOTE applies to what is inside it. */
212 && (GET_CODE (SET_DEST (set
)) != STRICT_LOW_PART
213 || ! rtx_equal_p (XEXP (SET_DEST (set
), 0), target
)))
216 if (GET_RTX_CLASS (code
) == RTX_UNARY
)
226 if (GET_MODE (op0
) != VOIDmode
&& GET_MODE (target
) != GET_MODE (op0
))
228 note
= gen_rtx_fmt_e (code
, GET_MODE (op0
), copy_rtx (op0
));
229 if (GET_MODE_SIZE (GET_MODE (op0
))
230 > GET_MODE_SIZE (GET_MODE (target
)))
231 note
= simplify_gen_unary (TRUNCATE
, GET_MODE (target
),
232 note
, GET_MODE (op0
));
234 note
= simplify_gen_unary (ZERO_EXTEND
, GET_MODE (target
),
235 note
, GET_MODE (op0
));
240 note
= gen_rtx_fmt_e (code
, GET_MODE (target
), copy_rtx (op0
));
244 note
= gen_rtx_fmt_ee (code
, GET_MODE (target
), copy_rtx (op0
), copy_rtx (op1
));
246 set_unique_reg_note (last_insn
, REG_EQUAL
, note
);
251 /* Given two input operands, OP0 and OP1, determine what the correct from_mode
252 for a widening operation would be. In most cases this would be OP0, but if
253 that's a constant it'll be VOIDmode, which isn't useful. */
255 static enum machine_mode
256 widened_mode (enum machine_mode to_mode
, rtx op0
, rtx op1
)
258 enum machine_mode m0
= GET_MODE (op0
);
259 enum machine_mode m1
= GET_MODE (op1
);
260 enum machine_mode result
;
262 if (m0
== VOIDmode
&& m1
== VOIDmode
)
264 else if (m0
== VOIDmode
|| GET_MODE_SIZE (m0
) < GET_MODE_SIZE (m1
))
269 if (GET_MODE_SIZE (result
) > GET_MODE_SIZE (to_mode
))
275 /* Find a widening optab even if it doesn't widen as much as we want.
276 E.g. if from_mode is HImode, and to_mode is DImode, and there is no
277 direct HI->SI insn, then return SI->DI, if that exists.
278 If PERMIT_NON_WIDENING is non-zero then this can be used with
279 non-widening optabs also. */
282 find_widening_optab_handler_and_mode (optab op
, enum machine_mode to_mode
,
283 enum machine_mode from_mode
,
284 int permit_non_widening
,
285 enum machine_mode
*found_mode
)
287 for (; (permit_non_widening
|| from_mode
!= to_mode
)
288 && GET_MODE_SIZE (from_mode
) <= GET_MODE_SIZE (to_mode
)
289 && from_mode
!= VOIDmode
;
290 from_mode
= GET_MODE_WIDER_MODE (from_mode
))
292 enum insn_code handler
= widening_optab_handler (op
, to_mode
,
295 if (handler
!= CODE_FOR_nothing
)
298 *found_mode
= from_mode
;
303 return CODE_FOR_nothing
;
306 /* Widen OP to MODE and return the rtx for the widened operand. UNSIGNEDP
307 says whether OP is signed or unsigned. NO_EXTEND is nonzero if we need
308 not actually do a sign-extend or zero-extend, but can leave the
309 higher-order bits of the result rtx undefined, for example, in the case
310 of logical operations, but not right shifts. */
313 widen_operand (rtx op
, enum machine_mode mode
, enum machine_mode oldmode
,
314 int unsignedp
, int no_extend
)
318 /* If we don't have to extend and this is a constant, return it. */
319 if (no_extend
&& GET_MODE (op
) == VOIDmode
)
322 /* If we must extend do so. If OP is a SUBREG for a promoted object, also
323 extend since it will be more efficient to do so unless the signedness of
324 a promoted object differs from our extension. */
326 || (GET_CODE (op
) == SUBREG
&& SUBREG_PROMOTED_VAR_P (op
)
327 && SUBREG_PROMOTED_UNSIGNED_P (op
) == unsignedp
))
328 return convert_modes (mode
, oldmode
, op
, unsignedp
);
330 /* If MODE is no wider than a single word, we return a paradoxical
332 if (GET_MODE_SIZE (mode
) <= UNITS_PER_WORD
)
333 return gen_rtx_SUBREG (mode
, force_reg (GET_MODE (op
), op
), 0);
335 /* Otherwise, get an object of MODE, clobber it, and set the low-order
338 result
= gen_reg_rtx (mode
);
339 emit_clobber (result
);
340 emit_move_insn (gen_lowpart (GET_MODE (op
), result
), op
);
344 /* Return the optab used for computing the operation given by the tree code,
345 CODE and the tree EXP. This function is not always usable (for example, it
346 cannot give complete results for multiplication or division) but probably
347 ought to be relied on more widely throughout the expander. */
349 optab_for_tree_code (enum tree_code code
, const_tree type
,
350 enum optab_subtype subtype
)
362 return one_cmpl_optab
;
367 case MULT_HIGHPART_EXPR
:
368 return TYPE_UNSIGNED (type
) ? umul_highpart_optab
: smul_highpart_optab
;
374 return TYPE_UNSIGNED (type
) ? umod_optab
: smod_optab
;
382 if (TYPE_SATURATING(type
))
383 return TYPE_UNSIGNED(type
) ? usdiv_optab
: ssdiv_optab
;
384 return TYPE_UNSIGNED (type
) ? udiv_optab
: sdiv_optab
;
387 if (TREE_CODE (type
) == VECTOR_TYPE
)
389 if (subtype
== optab_vector
)
390 return TYPE_SATURATING (type
) ? unknown_optab
: vashl_optab
;
392 gcc_assert (subtype
== optab_scalar
);
394 if (TYPE_SATURATING(type
))
395 return TYPE_UNSIGNED(type
) ? usashl_optab
: ssashl_optab
;
399 if (TREE_CODE (type
) == VECTOR_TYPE
)
401 if (subtype
== optab_vector
)
402 return TYPE_UNSIGNED (type
) ? vlshr_optab
: vashr_optab
;
404 gcc_assert (subtype
== optab_scalar
);
406 return TYPE_UNSIGNED (type
) ? lshr_optab
: ashr_optab
;
409 if (TREE_CODE (type
) == VECTOR_TYPE
)
411 if (subtype
== optab_vector
)
414 gcc_assert (subtype
== optab_scalar
);
419 if (TREE_CODE (type
) == VECTOR_TYPE
)
421 if (subtype
== optab_vector
)
424 gcc_assert (subtype
== optab_scalar
);
429 return TYPE_UNSIGNED (type
) ? umax_optab
: smax_optab
;
432 return TYPE_UNSIGNED (type
) ? umin_optab
: smin_optab
;
434 case REALIGN_LOAD_EXPR
:
435 return vec_realign_load_optab
;
438 return TYPE_UNSIGNED (type
) ? usum_widen_optab
: ssum_widen_optab
;
441 return TYPE_UNSIGNED (type
) ? udot_prod_optab
: sdot_prod_optab
;
443 case WIDEN_MULT_PLUS_EXPR
:
444 return (TYPE_UNSIGNED (type
)
445 ? (TYPE_SATURATING (type
)
446 ? usmadd_widen_optab
: umadd_widen_optab
)
447 : (TYPE_SATURATING (type
)
448 ? ssmadd_widen_optab
: smadd_widen_optab
));
450 case WIDEN_MULT_MINUS_EXPR
:
451 return (TYPE_UNSIGNED (type
)
452 ? (TYPE_SATURATING (type
)
453 ? usmsub_widen_optab
: umsub_widen_optab
)
454 : (TYPE_SATURATING (type
)
455 ? ssmsub_widen_optab
: smsub_widen_optab
));
461 return TYPE_UNSIGNED (type
) ? reduc_umax_optab
: reduc_smax_optab
;
464 return TYPE_UNSIGNED (type
) ? reduc_umin_optab
: reduc_smin_optab
;
466 case REDUC_PLUS_EXPR
:
467 return TYPE_UNSIGNED (type
) ? reduc_uplus_optab
: reduc_splus_optab
;
469 case VEC_LSHIFT_EXPR
:
470 return vec_shl_optab
;
472 case VEC_RSHIFT_EXPR
:
473 return vec_shr_optab
;
475 case VEC_WIDEN_MULT_HI_EXPR
:
476 return TYPE_UNSIGNED (type
) ?
477 vec_widen_umult_hi_optab
: vec_widen_smult_hi_optab
;
479 case VEC_WIDEN_MULT_LO_EXPR
:
480 return TYPE_UNSIGNED (type
) ?
481 vec_widen_umult_lo_optab
: vec_widen_smult_lo_optab
;
483 case VEC_WIDEN_MULT_EVEN_EXPR
:
484 return TYPE_UNSIGNED (type
) ?
485 vec_widen_umult_even_optab
: vec_widen_smult_even_optab
;
487 case VEC_WIDEN_MULT_ODD_EXPR
:
488 return TYPE_UNSIGNED (type
) ?
489 vec_widen_umult_odd_optab
: vec_widen_smult_odd_optab
;
491 case VEC_WIDEN_LSHIFT_HI_EXPR
:
492 return TYPE_UNSIGNED (type
) ?
493 vec_widen_ushiftl_hi_optab
: vec_widen_sshiftl_hi_optab
;
495 case VEC_WIDEN_LSHIFT_LO_EXPR
:
496 return TYPE_UNSIGNED (type
) ?
497 vec_widen_ushiftl_lo_optab
: vec_widen_sshiftl_lo_optab
;
499 case VEC_UNPACK_HI_EXPR
:
500 return TYPE_UNSIGNED (type
) ?
501 vec_unpacku_hi_optab
: vec_unpacks_hi_optab
;
503 case VEC_UNPACK_LO_EXPR
:
504 return TYPE_UNSIGNED (type
) ?
505 vec_unpacku_lo_optab
: vec_unpacks_lo_optab
;
507 case VEC_UNPACK_FLOAT_HI_EXPR
:
508 /* The signedness is determined from input operand. */
509 return TYPE_UNSIGNED (type
) ?
510 vec_unpacku_float_hi_optab
: vec_unpacks_float_hi_optab
;
512 case VEC_UNPACK_FLOAT_LO_EXPR
:
513 /* The signedness is determined from input operand. */
514 return TYPE_UNSIGNED (type
) ?
515 vec_unpacku_float_lo_optab
: vec_unpacks_float_lo_optab
;
517 case VEC_PACK_TRUNC_EXPR
:
518 return vec_pack_trunc_optab
;
520 case VEC_PACK_SAT_EXPR
:
521 return TYPE_UNSIGNED (type
) ? vec_pack_usat_optab
: vec_pack_ssat_optab
;
523 case VEC_PACK_FIX_TRUNC_EXPR
:
524 /* The signedness is determined from output operand. */
525 return TYPE_UNSIGNED (type
) ?
526 vec_pack_ufix_trunc_optab
: vec_pack_sfix_trunc_optab
;
532 trapv
= INTEGRAL_TYPE_P (type
) && TYPE_OVERFLOW_TRAPS (type
);
535 case POINTER_PLUS_EXPR
:
537 if (TYPE_SATURATING(type
))
538 return TYPE_UNSIGNED(type
) ? usadd_optab
: ssadd_optab
;
539 return trapv
? addv_optab
: add_optab
;
542 if (TYPE_SATURATING(type
))
543 return TYPE_UNSIGNED(type
) ? ussub_optab
: sssub_optab
;
544 return trapv
? subv_optab
: sub_optab
;
547 if (TYPE_SATURATING(type
))
548 return TYPE_UNSIGNED(type
) ? usmul_optab
: ssmul_optab
;
549 return trapv
? smulv_optab
: smul_optab
;
552 if (TYPE_SATURATING(type
))
553 return TYPE_UNSIGNED(type
) ? usneg_optab
: ssneg_optab
;
554 return trapv
? negv_optab
: neg_optab
;
557 return trapv
? absv_optab
: abs_optab
;
560 return unknown_optab
;
565 /* Expand vector widening operations.
567 There are two different classes of operations handled here:
568 1) Operations whose result is wider than all the arguments to the operation.
569 Examples: VEC_UNPACK_HI/LO_EXPR, VEC_WIDEN_MULT_HI/LO_EXPR
570 In this case OP0 and optionally OP1 would be initialized,
571 but WIDE_OP wouldn't (not relevant for this case).
572 2) Operations whose result is of the same size as the last argument to the
573 operation, but wider than all the other arguments to the operation.
574 Examples: WIDEN_SUM_EXPR, VEC_DOT_PROD_EXPR.
575 In the case WIDE_OP, OP0 and optionally OP1 would be initialized.
577 E.g, when called to expand the following operations, this is how
578 the arguments will be initialized:
580 widening-sum 2 oprnd0 - oprnd1
581 widening-dot-product 3 oprnd0 oprnd1 oprnd2
582 widening-mult 2 oprnd0 oprnd1 -
583 type-promotion (vec-unpack) 1 oprnd0 - - */
586 expand_widen_pattern_expr (sepops ops
, rtx op0
, rtx op1
, rtx wide_op
,
587 rtx target
, int unsignedp
)
589 struct expand_operand eops
[4];
590 tree oprnd0
, oprnd1
, oprnd2
;
591 enum machine_mode wmode
= VOIDmode
, tmode0
, tmode1
= VOIDmode
;
592 optab widen_pattern_optab
;
593 enum insn_code icode
;
594 int nops
= TREE_CODE_LENGTH (ops
->code
);
598 tmode0
= TYPE_MODE (TREE_TYPE (oprnd0
));
599 widen_pattern_optab
=
600 optab_for_tree_code (ops
->code
, TREE_TYPE (oprnd0
), optab_default
);
601 if (ops
->code
== WIDEN_MULT_PLUS_EXPR
602 || ops
->code
== WIDEN_MULT_MINUS_EXPR
)
603 icode
= find_widening_optab_handler (widen_pattern_optab
,
604 TYPE_MODE (TREE_TYPE (ops
->op2
)),
607 icode
= optab_handler (widen_pattern_optab
, tmode0
);
608 gcc_assert (icode
!= CODE_FOR_nothing
);
613 tmode1
= TYPE_MODE (TREE_TYPE (oprnd1
));
616 /* The last operand is of a wider mode than the rest of the operands. */
621 gcc_assert (tmode1
== tmode0
);
624 wmode
= TYPE_MODE (TREE_TYPE (oprnd2
));
628 create_output_operand (&eops
[op
++], target
, TYPE_MODE (ops
->type
));
629 create_convert_operand_from (&eops
[op
++], op0
, tmode0
, unsignedp
);
631 create_convert_operand_from (&eops
[op
++], op1
, tmode1
, unsignedp
);
633 create_convert_operand_from (&eops
[op
++], wide_op
, wmode
, unsignedp
);
634 expand_insn (icode
, op
, eops
);
635 return eops
[0].value
;
638 /* Generate code to perform an operation specified by TERNARY_OPTAB
639 on operands OP0, OP1 and OP2, with result having machine-mode MODE.
641 UNSIGNEDP is for the case where we have to widen the operands
642 to perform the operation. It says to use zero-extension.
644 If TARGET is nonzero, the value
645 is generated there, if it is convenient to do so.
646 In all cases an rtx is returned for the locus of the value;
647 this may or may not be TARGET. */
650 expand_ternary_op (enum machine_mode mode
, optab ternary_optab
, rtx op0
,
651 rtx op1
, rtx op2
, rtx target
, int unsignedp
)
653 struct expand_operand ops
[4];
654 enum insn_code icode
= optab_handler (ternary_optab
, mode
);
656 gcc_assert (optab_handler (ternary_optab
, mode
) != CODE_FOR_nothing
);
658 create_output_operand (&ops
[0], target
, mode
);
659 create_convert_operand_from (&ops
[1], op0
, mode
, unsignedp
);
660 create_convert_operand_from (&ops
[2], op1
, mode
, unsignedp
);
661 create_convert_operand_from (&ops
[3], op2
, mode
, unsignedp
);
662 expand_insn (icode
, 4, ops
);
667 /* Like expand_binop, but return a constant rtx if the result can be
668 calculated at compile time. The arguments and return value are
669 otherwise the same as for expand_binop. */
672 simplify_expand_binop (enum machine_mode mode
, optab binoptab
,
673 rtx op0
, rtx op1
, rtx target
, int unsignedp
,
674 enum optab_methods methods
)
676 if (CONSTANT_P (op0
) && CONSTANT_P (op1
))
678 rtx x
= simplify_binary_operation (optab_to_code (binoptab
),
684 return expand_binop (mode
, binoptab
, op0
, op1
, target
, unsignedp
, methods
);
687 /* Like simplify_expand_binop, but always put the result in TARGET.
688 Return true if the expansion succeeded. */
691 force_expand_binop (enum machine_mode mode
, optab binoptab
,
692 rtx op0
, rtx op1
, rtx target
, int unsignedp
,
693 enum optab_methods methods
)
695 rtx x
= simplify_expand_binop (mode
, binoptab
, op0
, op1
,
696 target
, unsignedp
, methods
);
700 emit_move_insn (target
, x
);
704 /* Generate insns for VEC_LSHIFT_EXPR, VEC_RSHIFT_EXPR. */
707 expand_vec_shift_expr (sepops ops
, rtx target
)
709 struct expand_operand eops
[3];
710 enum insn_code icode
;
711 rtx rtx_op1
, rtx_op2
;
712 enum machine_mode mode
= TYPE_MODE (ops
->type
);
713 tree vec_oprnd
= ops
->op0
;
714 tree shift_oprnd
= ops
->op1
;
719 case VEC_RSHIFT_EXPR
:
720 shift_optab
= vec_shr_optab
;
722 case VEC_LSHIFT_EXPR
:
723 shift_optab
= vec_shl_optab
;
729 icode
= optab_handler (shift_optab
, mode
);
730 gcc_assert (icode
!= CODE_FOR_nothing
);
732 rtx_op1
= expand_normal (vec_oprnd
);
733 rtx_op2
= expand_normal (shift_oprnd
);
735 create_output_operand (&eops
[0], target
, mode
);
736 create_input_operand (&eops
[1], rtx_op1
, GET_MODE (rtx_op1
));
737 create_convert_operand_from_type (&eops
[2], rtx_op2
, TREE_TYPE (shift_oprnd
));
738 expand_insn (icode
, 3, eops
);
740 return eops
[0].value
;
743 /* Create a new vector value in VMODE with all elements set to OP. The
744 mode of OP must be the element mode of VMODE. If OP is a constant,
745 then the return value will be a constant. */
748 expand_vector_broadcast (enum machine_mode vmode
, rtx op
)
750 enum insn_code icode
;
755 gcc_checking_assert (VECTOR_MODE_P (vmode
));
757 n
= GET_MODE_NUNITS (vmode
);
758 vec
= rtvec_alloc (n
);
759 for (i
= 0; i
< n
; ++i
)
760 RTVEC_ELT (vec
, i
) = op
;
763 return gen_rtx_CONST_VECTOR (vmode
, vec
);
765 /* ??? If the target doesn't have a vec_init, then we have no easy way
766 of performing this operation. Most of this sort of generic support
767 is hidden away in the vector lowering support in gimple. */
768 icode
= optab_handler (vec_init_optab
, vmode
);
769 if (icode
== CODE_FOR_nothing
)
772 ret
= gen_reg_rtx (vmode
);
773 emit_insn (GEN_FCN (icode
) (ret
, gen_rtx_PARALLEL (vmode
, vec
)));
778 /* This subroutine of expand_doubleword_shift handles the cases in which
779 the effective shift value is >= BITS_PER_WORD. The arguments and return
780 value are the same as for the parent routine, except that SUPERWORD_OP1
781 is the shift count to use when shifting OUTOF_INPUT into INTO_TARGET.
782 INTO_TARGET may be null if the caller has decided to calculate it. */
785 expand_superword_shift (optab binoptab
, rtx outof_input
, rtx superword_op1
,
786 rtx outof_target
, rtx into_target
,
787 int unsignedp
, enum optab_methods methods
)
789 if (into_target
!= 0)
790 if (!force_expand_binop (word_mode
, binoptab
, outof_input
, superword_op1
,
791 into_target
, unsignedp
, methods
))
794 if (outof_target
!= 0)
796 /* For a signed right shift, we must fill OUTOF_TARGET with copies
797 of the sign bit, otherwise we must fill it with zeros. */
798 if (binoptab
!= ashr_optab
)
799 emit_move_insn (outof_target
, CONST0_RTX (word_mode
));
801 if (!force_expand_binop (word_mode
, binoptab
,
802 outof_input
, GEN_INT (BITS_PER_WORD
- 1),
803 outof_target
, unsignedp
, methods
))
809 /* This subroutine of expand_doubleword_shift handles the cases in which
810 the effective shift value is < BITS_PER_WORD. The arguments and return
811 value are the same as for the parent routine. */
814 expand_subword_shift (enum machine_mode op1_mode
, optab binoptab
,
815 rtx outof_input
, rtx into_input
, rtx op1
,
816 rtx outof_target
, rtx into_target
,
817 int unsignedp
, enum optab_methods methods
,
818 unsigned HOST_WIDE_INT shift_mask
)
820 optab reverse_unsigned_shift
, unsigned_shift
;
823 reverse_unsigned_shift
= (binoptab
== ashl_optab
? lshr_optab
: ashl_optab
);
824 unsigned_shift
= (binoptab
== ashl_optab
? ashl_optab
: lshr_optab
);
826 /* The low OP1 bits of INTO_TARGET come from the high bits of OUTOF_INPUT.
827 We therefore need to shift OUTOF_INPUT by (BITS_PER_WORD - OP1) bits in
828 the opposite direction to BINOPTAB. */
829 if (CONSTANT_P (op1
) || shift_mask
>= BITS_PER_WORD
)
831 carries
= outof_input
;
832 tmp
= immed_double_const (BITS_PER_WORD
, 0, op1_mode
);
833 tmp
= simplify_expand_binop (op1_mode
, sub_optab
, tmp
, op1
,
838 /* We must avoid shifting by BITS_PER_WORD bits since that is either
839 the same as a zero shift (if shift_mask == BITS_PER_WORD - 1) or
840 has unknown behavior. Do a single shift first, then shift by the
841 remainder. It's OK to use ~OP1 as the remainder if shift counts
842 are truncated to the mode size. */
843 carries
= expand_binop (word_mode
, reverse_unsigned_shift
,
844 outof_input
, const1_rtx
, 0, unsignedp
, methods
);
845 if (shift_mask
== BITS_PER_WORD
- 1)
847 tmp
= immed_double_const (-1, -1, op1_mode
);
848 tmp
= simplify_expand_binop (op1_mode
, xor_optab
, op1
, tmp
,
853 tmp
= immed_double_const (BITS_PER_WORD
- 1, 0, op1_mode
);
854 tmp
= simplify_expand_binop (op1_mode
, sub_optab
, tmp
, op1
,
858 if (tmp
== 0 || carries
== 0)
860 carries
= expand_binop (word_mode
, reverse_unsigned_shift
,
861 carries
, tmp
, 0, unsignedp
, methods
);
865 /* Shift INTO_INPUT logically by OP1. This is the last use of INTO_INPUT
866 so the result can go directly into INTO_TARGET if convenient. */
867 tmp
= expand_binop (word_mode
, unsigned_shift
, into_input
, op1
,
868 into_target
, unsignedp
, methods
);
872 /* Now OR in the bits carried over from OUTOF_INPUT. */
873 if (!force_expand_binop (word_mode
, ior_optab
, tmp
, carries
,
874 into_target
, unsignedp
, methods
))
877 /* Use a standard word_mode shift for the out-of half. */
878 if (outof_target
!= 0)
879 if (!force_expand_binop (word_mode
, binoptab
, outof_input
, op1
,
880 outof_target
, unsignedp
, methods
))
887 #ifdef HAVE_conditional_move
888 /* Try implementing expand_doubleword_shift using conditional moves.
889 The shift is by < BITS_PER_WORD if (CMP_CODE CMP1 CMP2) is true,
890 otherwise it is by >= BITS_PER_WORD. SUBWORD_OP1 and SUPERWORD_OP1
891 are the shift counts to use in the former and latter case. All other
892 arguments are the same as the parent routine. */
895 expand_doubleword_shift_condmove (enum machine_mode op1_mode
, optab binoptab
,
896 enum rtx_code cmp_code
, rtx cmp1
, rtx cmp2
,
897 rtx outof_input
, rtx into_input
,
898 rtx subword_op1
, rtx superword_op1
,
899 rtx outof_target
, rtx into_target
,
900 int unsignedp
, enum optab_methods methods
,
901 unsigned HOST_WIDE_INT shift_mask
)
903 rtx outof_superword
, into_superword
;
905 /* Put the superword version of the output into OUTOF_SUPERWORD and
907 outof_superword
= outof_target
!= 0 ? gen_reg_rtx (word_mode
) : 0;
908 if (outof_target
!= 0 && subword_op1
== superword_op1
)
910 /* The value INTO_TARGET >> SUBWORD_OP1, which we later store in
911 OUTOF_TARGET, is the same as the value of INTO_SUPERWORD. */
912 into_superword
= outof_target
;
913 if (!expand_superword_shift (binoptab
, outof_input
, superword_op1
,
914 outof_superword
, 0, unsignedp
, methods
))
919 into_superword
= gen_reg_rtx (word_mode
);
920 if (!expand_superword_shift (binoptab
, outof_input
, superword_op1
,
921 outof_superword
, into_superword
,
926 /* Put the subword version directly in OUTOF_TARGET and INTO_TARGET. */
927 if (!expand_subword_shift (op1_mode
, binoptab
,
928 outof_input
, into_input
, subword_op1
,
929 outof_target
, into_target
,
930 unsignedp
, methods
, shift_mask
))
933 /* Select between them. Do the INTO half first because INTO_SUPERWORD
934 might be the current value of OUTOF_TARGET. */
935 if (!emit_conditional_move (into_target
, cmp_code
, cmp1
, cmp2
, op1_mode
,
936 into_target
, into_superword
, word_mode
, false))
939 if (outof_target
!= 0)
940 if (!emit_conditional_move (outof_target
, cmp_code
, cmp1
, cmp2
, op1_mode
,
941 outof_target
, outof_superword
,
949 /* Expand a doubleword shift (ashl, ashr or lshr) using word-mode shifts.
950 OUTOF_INPUT and INTO_INPUT are the two word-sized halves of the first
951 input operand; the shift moves bits in the direction OUTOF_INPUT->
952 INTO_TARGET. OUTOF_TARGET and INTO_TARGET are the equivalent words
953 of the target. OP1 is the shift count and OP1_MODE is its mode.
954 If OP1 is constant, it will have been truncated as appropriate
955 and is known to be nonzero.
957 If SHIFT_MASK is zero, the result of word shifts is undefined when the
958 shift count is outside the range [0, BITS_PER_WORD). This routine must
959 avoid generating such shifts for OP1s in the range [0, BITS_PER_WORD * 2).
961 If SHIFT_MASK is nonzero, all word-mode shift counts are effectively
962 masked by it and shifts in the range [BITS_PER_WORD, SHIFT_MASK) will
963 fill with zeros or sign bits as appropriate.
965 If SHIFT_MASK is BITS_PER_WORD - 1, this routine will synthesize
966 a doubleword shift whose equivalent mask is BITS_PER_WORD * 2 - 1.
967 Doing this preserves semantics required by SHIFT_COUNT_TRUNCATED.
968 In all other cases, shifts by values outside [0, BITS_PER_UNIT * 2)
971 BINOPTAB, UNSIGNEDP and METHODS are as for expand_binop. This function
972 may not use INTO_INPUT after modifying INTO_TARGET, and similarly for
973 OUTOF_INPUT and OUTOF_TARGET. OUTOF_TARGET can be null if the parent
974 function wants to calculate it itself.
976 Return true if the shift could be successfully synthesized. */
979 expand_doubleword_shift (enum machine_mode op1_mode
, optab binoptab
,
980 rtx outof_input
, rtx into_input
, rtx op1
,
981 rtx outof_target
, rtx into_target
,
982 int unsignedp
, enum optab_methods methods
,
983 unsigned HOST_WIDE_INT shift_mask
)
985 rtx superword_op1
, tmp
, cmp1
, cmp2
;
986 rtx subword_label
, done_label
;
987 enum rtx_code cmp_code
;
989 /* See if word-mode shifts by BITS_PER_WORD...BITS_PER_WORD * 2 - 1 will
990 fill the result with sign or zero bits as appropriate. If so, the value
991 of OUTOF_TARGET will always be (SHIFT OUTOF_INPUT OP1). Recursively call
992 this routine to calculate INTO_TARGET (which depends on both OUTOF_INPUT
993 and INTO_INPUT), then emit code to set up OUTOF_TARGET.
995 This isn't worthwhile for constant shifts since the optimizers will
996 cope better with in-range shift counts. */
997 if (shift_mask
>= BITS_PER_WORD
999 && !CONSTANT_P (op1
))
1001 if (!expand_doubleword_shift (op1_mode
, binoptab
,
1002 outof_input
, into_input
, op1
,
1004 unsignedp
, methods
, shift_mask
))
1006 if (!force_expand_binop (word_mode
, binoptab
, outof_input
, op1
,
1007 outof_target
, unsignedp
, methods
))
1012 /* Set CMP_CODE, CMP1 and CMP2 so that the rtx (CMP_CODE CMP1 CMP2)
1013 is true when the effective shift value is less than BITS_PER_WORD.
1014 Set SUPERWORD_OP1 to the shift count that should be used to shift
1015 OUTOF_INPUT into INTO_TARGET when the condition is false. */
1016 tmp
= immed_double_const (BITS_PER_WORD
, 0, op1_mode
);
1017 if (!CONSTANT_P (op1
) && shift_mask
== BITS_PER_WORD
- 1)
1019 /* Set CMP1 to OP1 & BITS_PER_WORD. The result is zero iff OP1
1020 is a subword shift count. */
1021 cmp1
= simplify_expand_binop (op1_mode
, and_optab
, op1
, tmp
,
1023 cmp2
= CONST0_RTX (op1_mode
);
1025 superword_op1
= op1
;
1029 /* Set CMP1 to OP1 - BITS_PER_WORD. */
1030 cmp1
= simplify_expand_binop (op1_mode
, sub_optab
, op1
, tmp
,
1032 cmp2
= CONST0_RTX (op1_mode
);
1034 superword_op1
= cmp1
;
1039 /* If we can compute the condition at compile time, pick the
1040 appropriate subroutine. */
1041 tmp
= simplify_relational_operation (cmp_code
, SImode
, op1_mode
, cmp1
, cmp2
);
1042 if (tmp
!= 0 && CONST_INT_P (tmp
))
1044 if (tmp
== const0_rtx
)
1045 return expand_superword_shift (binoptab
, outof_input
, superword_op1
,
1046 outof_target
, into_target
,
1047 unsignedp
, methods
);
1049 return expand_subword_shift (op1_mode
, binoptab
,
1050 outof_input
, into_input
, op1
,
1051 outof_target
, into_target
,
1052 unsignedp
, methods
, shift_mask
);
1055 #ifdef HAVE_conditional_move
1056 /* Try using conditional moves to generate straight-line code. */
1058 rtx start
= get_last_insn ();
1059 if (expand_doubleword_shift_condmove (op1_mode
, binoptab
,
1060 cmp_code
, cmp1
, cmp2
,
1061 outof_input
, into_input
,
1063 outof_target
, into_target
,
1064 unsignedp
, methods
, shift_mask
))
1066 delete_insns_since (start
);
1070 /* As a last resort, use branches to select the correct alternative. */
1071 subword_label
= gen_label_rtx ();
1072 done_label
= gen_label_rtx ();
1075 do_compare_rtx_and_jump (cmp1
, cmp2
, cmp_code
, false, op1_mode
,
1076 0, 0, subword_label
, -1);
1079 if (!expand_superword_shift (binoptab
, outof_input
, superword_op1
,
1080 outof_target
, into_target
,
1081 unsignedp
, methods
))
1084 emit_jump_insn (gen_jump (done_label
));
1086 emit_label (subword_label
);
1088 if (!expand_subword_shift (op1_mode
, binoptab
,
1089 outof_input
, into_input
, op1
,
1090 outof_target
, into_target
,
1091 unsignedp
, methods
, shift_mask
))
1094 emit_label (done_label
);
1098 /* Subroutine of expand_binop. Perform a double word multiplication of
1099 operands OP0 and OP1 both of mode MODE, which is exactly twice as wide
1100 as the target's word_mode. This function return NULL_RTX if anything
1101 goes wrong, in which case it may have already emitted instructions
1102 which need to be deleted.
1104 If we want to multiply two two-word values and have normal and widening
1105 multiplies of single-word values, we can do this with three smaller
1108 The multiplication proceeds as follows:
1109 _______________________
1110 [__op0_high_|__op0_low__]
1111 _______________________
1112 * [__op1_high_|__op1_low__]
1113 _______________________________________________
1114 _______________________
1115 (1) [__op0_low__*__op1_low__]
1116 _______________________
1117 (2a) [__op0_low__*__op1_high_]
1118 _______________________
1119 (2b) [__op0_high_*__op1_low__]
1120 _______________________
1121 (3) [__op0_high_*__op1_high_]
1124 This gives a 4-word result. Since we are only interested in the
1125 lower 2 words, partial result (3) and the upper words of (2a) and
1126 (2b) don't need to be calculated. Hence (2a) and (2b) can be
1127 calculated using non-widening multiplication.
1129 (1), however, needs to be calculated with an unsigned widening
1130 multiplication. If this operation is not directly supported we
1131 try using a signed widening multiplication and adjust the result.
1132 This adjustment works as follows:
1134 If both operands are positive then no adjustment is needed.
1136 If the operands have different signs, for example op0_low < 0 and
1137 op1_low >= 0, the instruction treats the most significant bit of
1138 op0_low as a sign bit instead of a bit with significance
1139 2**(BITS_PER_WORD-1), i.e. the instruction multiplies op1_low
1140 with 2**BITS_PER_WORD - op0_low, and two's complements the
1141 result. Conclusion: We need to add op1_low * 2**BITS_PER_WORD to
1144 Similarly, if both operands are negative, we need to add
1145 (op0_low + op1_low) * 2**BITS_PER_WORD.
1147 We use a trick to adjust quickly. We logically shift op0_low right
1148 (op1_low) BITS_PER_WORD-1 steps to get 0 or 1, and add this to
1149 op0_high (op1_high) before it is used to calculate 2b (2a). If no
1150 logical shift exists, we do an arithmetic right shift and subtract
1154 expand_doubleword_mult (enum machine_mode mode
, rtx op0
, rtx op1
, rtx target
,
1155 bool umulp
, enum optab_methods methods
)
1157 int low
= (WORDS_BIG_ENDIAN
? 1 : 0);
1158 int high
= (WORDS_BIG_ENDIAN
? 0 : 1);
1159 rtx wordm1
= umulp
? NULL_RTX
: GEN_INT (BITS_PER_WORD
- 1);
1160 rtx product
, adjust
, product_high
, temp
;
1162 rtx op0_high
= operand_subword_force (op0
, high
, mode
);
1163 rtx op0_low
= operand_subword_force (op0
, low
, mode
);
1164 rtx op1_high
= operand_subword_force (op1
, high
, mode
);
1165 rtx op1_low
= operand_subword_force (op1
, low
, mode
);
1167 /* If we're using an unsigned multiply to directly compute the product
1168 of the low-order words of the operands and perform any required
1169 adjustments of the operands, we begin by trying two more multiplications
1170 and then computing the appropriate sum.
1172 We have checked above that the required addition is provided.
1173 Full-word addition will normally always succeed, especially if
1174 it is provided at all, so we don't worry about its failure. The
1175 multiplication may well fail, however, so we do handle that. */
1179 /* ??? This could be done with emit_store_flag where available. */
1180 temp
= expand_binop (word_mode
, lshr_optab
, op0_low
, wordm1
,
1181 NULL_RTX
, 1, methods
);
1183 op0_high
= expand_binop (word_mode
, add_optab
, op0_high
, temp
,
1184 NULL_RTX
, 0, OPTAB_DIRECT
);
1187 temp
= expand_binop (word_mode
, ashr_optab
, op0_low
, wordm1
,
1188 NULL_RTX
, 0, methods
);
1191 op0_high
= expand_binop (word_mode
, sub_optab
, op0_high
, temp
,
1192 NULL_RTX
, 0, OPTAB_DIRECT
);
1199 adjust
= expand_binop (word_mode
, smul_optab
, op0_high
, op1_low
,
1200 NULL_RTX
, 0, OPTAB_DIRECT
);
1204 /* OP0_HIGH should now be dead. */
1208 /* ??? This could be done with emit_store_flag where available. */
1209 temp
= expand_binop (word_mode
, lshr_optab
, op1_low
, wordm1
,
1210 NULL_RTX
, 1, methods
);
1212 op1_high
= expand_binop (word_mode
, add_optab
, op1_high
, temp
,
1213 NULL_RTX
, 0, OPTAB_DIRECT
);
1216 temp
= expand_binop (word_mode
, ashr_optab
, op1_low
, wordm1
,
1217 NULL_RTX
, 0, methods
);
1220 op1_high
= expand_binop (word_mode
, sub_optab
, op1_high
, temp
,
1221 NULL_RTX
, 0, OPTAB_DIRECT
);
1228 temp
= expand_binop (word_mode
, smul_optab
, op1_high
, op0_low
,
1229 NULL_RTX
, 0, OPTAB_DIRECT
);
1233 /* OP1_HIGH should now be dead. */
1235 adjust
= expand_binop (word_mode
, add_optab
, adjust
, temp
,
1236 NULL_RTX
, 0, OPTAB_DIRECT
);
1238 if (target
&& !REG_P (target
))
1242 product
= expand_binop (mode
, umul_widen_optab
, op0_low
, op1_low
,
1243 target
, 1, OPTAB_DIRECT
);
1245 product
= expand_binop (mode
, smul_widen_optab
, op0_low
, op1_low
,
1246 target
, 1, OPTAB_DIRECT
);
1251 product_high
= operand_subword (product
, high
, 1, mode
);
1252 adjust
= expand_binop (word_mode
, add_optab
, product_high
, adjust
,
1253 NULL_RTX
, 0, OPTAB_DIRECT
);
1254 emit_move_insn (product_high
, adjust
);
1258 /* Wrapper around expand_binop which takes an rtx code to specify
1259 the operation to perform, not an optab pointer. All other
1260 arguments are the same. */
1262 expand_simple_binop (enum machine_mode mode
, enum rtx_code code
, rtx op0
,
1263 rtx op1
, rtx target
, int unsignedp
,
1264 enum optab_methods methods
)
1266 optab binop
= code_to_optab (code
);
1269 return expand_binop (mode
, binop
, op0
, op1
, target
, unsignedp
, methods
);
1272 /* Return whether OP0 and OP1 should be swapped when expanding a commutative
1273 binop. Order them according to commutative_operand_precedence and, if
1274 possible, try to put TARGET or a pseudo first. */
1276 swap_commutative_operands_with_target (rtx target
, rtx op0
, rtx op1
)
1278 int op0_prec
= commutative_operand_precedence (op0
);
1279 int op1_prec
= commutative_operand_precedence (op1
);
1281 if (op0_prec
< op1_prec
)
1284 if (op0_prec
> op1_prec
)
1287 /* With equal precedence, both orders are ok, but it is better if the
1288 first operand is TARGET, or if both TARGET and OP0 are pseudos. */
1289 if (target
== 0 || REG_P (target
))
1290 return (REG_P (op1
) && !REG_P (op0
)) || target
== op1
;
1292 return rtx_equal_p (op1
, target
);
1295 /* Return true if BINOPTAB implements a shift operation. */
1298 shift_optab_p (optab binoptab
)
1300 switch (optab_to_code (binoptab
))
1316 /* Return true if BINOPTAB implements a commutative binary operation. */
1319 commutative_optab_p (optab binoptab
)
1321 return (GET_RTX_CLASS (optab_to_code (binoptab
)) == RTX_COMM_ARITH
1322 || binoptab
== smul_widen_optab
1323 || binoptab
== umul_widen_optab
1324 || binoptab
== smul_highpart_optab
1325 || binoptab
== umul_highpart_optab
);
1328 /* X is to be used in mode MODE as operand OPN to BINOPTAB. If we're
1329 optimizing, and if the operand is a constant that costs more than
1330 1 instruction, force the constant into a register and return that
1331 register. Return X otherwise. UNSIGNEDP says whether X is unsigned. */
1334 avoid_expensive_constant (enum machine_mode mode
, optab binoptab
,
1335 int opn
, rtx x
, bool unsignedp
)
1337 bool speed
= optimize_insn_for_speed_p ();
1339 if (mode
!= VOIDmode
1342 && (rtx_cost (x
, optab_to_code (binoptab
), opn
, speed
)
1343 > set_src_cost (x
, speed
)))
1345 if (CONST_INT_P (x
))
1347 HOST_WIDE_INT intval
= trunc_int_for_mode (INTVAL (x
), mode
);
1348 if (intval
!= INTVAL (x
))
1349 x
= GEN_INT (intval
);
1352 x
= convert_modes (mode
, VOIDmode
, x
, unsignedp
);
1353 x
= force_reg (mode
, x
);
1358 /* Helper function for expand_binop: handle the case where there
1359 is an insn that directly implements the indicated operation.
1360 Returns null if this is not possible. */
1362 expand_binop_directly (enum machine_mode mode
, optab binoptab
,
1364 rtx target
, int unsignedp
, enum optab_methods methods
,
1367 enum machine_mode from_mode
= widened_mode (mode
, op0
, op1
);
1368 enum insn_code icode
= find_widening_optab_handler (binoptab
, mode
,
1370 enum machine_mode xmode0
= insn_data
[(int) icode
].operand
[1].mode
;
1371 enum machine_mode xmode1
= insn_data
[(int) icode
].operand
[2].mode
;
1372 enum machine_mode mode0
, mode1
, tmp_mode
;
1373 struct expand_operand ops
[3];
1376 rtx xop0
= op0
, xop1
= op1
;
1379 /* If it is a commutative operator and the modes would match
1380 if we would swap the operands, we can save the conversions. */
1381 commutative_p
= commutative_optab_p (binoptab
);
1383 && GET_MODE (xop0
) != xmode0
&& GET_MODE (xop1
) != xmode1
1384 && GET_MODE (xop0
) == xmode1
&& GET_MODE (xop1
) == xmode1
)
1391 /* If we are optimizing, force expensive constants into a register. */
1392 xop0
= avoid_expensive_constant (xmode0
, binoptab
, 0, xop0
, unsignedp
);
1393 if (!shift_optab_p (binoptab
))
1394 xop1
= avoid_expensive_constant (xmode1
, binoptab
, 1, xop1
, unsignedp
);
1396 /* In case the insn wants input operands in modes different from
1397 those of the actual operands, convert the operands. It would
1398 seem that we don't need to convert CONST_INTs, but we do, so
1399 that they're properly zero-extended, sign-extended or truncated
1402 mode0
= GET_MODE (xop0
) != VOIDmode
? GET_MODE (xop0
) : mode
;
1403 if (xmode0
!= VOIDmode
&& xmode0
!= mode0
)
1405 xop0
= convert_modes (xmode0
, mode0
, xop0
, unsignedp
);
1409 mode1
= GET_MODE (xop1
) != VOIDmode
? GET_MODE (xop1
) : mode
;
1410 if (xmode1
!= VOIDmode
&& xmode1
!= mode1
)
1412 xop1
= convert_modes (xmode1
, mode1
, xop1
, unsignedp
);
1416 /* If operation is commutative,
1417 try to make the first operand a register.
1418 Even better, try to make it the same as the target.
1419 Also try to make the last operand a constant. */
1421 && swap_commutative_operands_with_target (target
, xop0
, xop1
))
1428 /* Now, if insn's predicates don't allow our operands, put them into
1431 if (binoptab
== vec_pack_trunc_optab
1432 || binoptab
== vec_pack_usat_optab
1433 || binoptab
== vec_pack_ssat_optab
1434 || binoptab
== vec_pack_ufix_trunc_optab
1435 || binoptab
== vec_pack_sfix_trunc_optab
)
1437 /* The mode of the result is different then the mode of the
1439 tmp_mode
= insn_data
[(int) icode
].operand
[0].mode
;
1440 if (GET_MODE_NUNITS (tmp_mode
) != 2 * GET_MODE_NUNITS (mode
))
1442 delete_insns_since (last
);
1449 create_output_operand (&ops
[0], target
, tmp_mode
);
1450 create_input_operand (&ops
[1], xop0
, mode0
);
1451 create_input_operand (&ops
[2], xop1
, mode1
);
1452 pat
= maybe_gen_insn (icode
, 3, ops
);
1455 /* If PAT is composed of more than one insn, try to add an appropriate
1456 REG_EQUAL note to it. If we can't because TEMP conflicts with an
1457 operand, call expand_binop again, this time without a target. */
1458 if (INSN_P (pat
) && NEXT_INSN (pat
) != NULL_RTX
1459 && ! add_equal_note (pat
, ops
[0].value
, optab_to_code (binoptab
),
1460 ops
[1].value
, ops
[2].value
))
1462 delete_insns_since (last
);
1463 return expand_binop (mode
, binoptab
, op0
, op1
, NULL_RTX
,
1464 unsignedp
, methods
);
1468 return ops
[0].value
;
1470 delete_insns_since (last
);
1474 /* Generate code to perform an operation specified by BINOPTAB
1475 on operands OP0 and OP1, with result having machine-mode MODE.
1477 UNSIGNEDP is for the case where we have to widen the operands
1478 to perform the operation. It says to use zero-extension.
1480 If TARGET is nonzero, the value
1481 is generated there, if it is convenient to do so.
1482 In all cases an rtx is returned for the locus of the value;
1483 this may or may not be TARGET. */
1486 expand_binop (enum machine_mode mode
, optab binoptab
, rtx op0
, rtx op1
,
1487 rtx target
, int unsignedp
, enum optab_methods methods
)
1489 enum optab_methods next_methods
1490 = (methods
== OPTAB_LIB
|| methods
== OPTAB_LIB_WIDEN
1491 ? OPTAB_WIDEN
: methods
);
1492 enum mode_class mclass
;
1493 enum machine_mode wider_mode
;
1496 rtx entry_last
= get_last_insn ();
1499 mclass
= GET_MODE_CLASS (mode
);
1501 /* If subtracting an integer constant, convert this into an addition of
1502 the negated constant. */
1504 if (binoptab
== sub_optab
&& CONST_INT_P (op1
))
1506 op1
= negate_rtx (mode
, op1
);
1507 binoptab
= add_optab
;
1510 /* Record where to delete back to if we backtrack. */
1511 last
= get_last_insn ();
1513 /* If we can do it with a three-operand insn, do so. */
1515 if (methods
!= OPTAB_MUST_WIDEN
1516 && find_widening_optab_handler (binoptab
, mode
,
1517 widened_mode (mode
, op0
, op1
), 1)
1518 != CODE_FOR_nothing
)
1520 temp
= expand_binop_directly (mode
, binoptab
, op0
, op1
, target
,
1521 unsignedp
, methods
, last
);
1526 /* If we were trying to rotate, and that didn't work, try rotating
1527 the other direction before falling back to shifts and bitwise-or. */
1528 if (((binoptab
== rotl_optab
1529 && optab_handler (rotr_optab
, mode
) != CODE_FOR_nothing
)
1530 || (binoptab
== rotr_optab
1531 && optab_handler (rotl_optab
, mode
) != CODE_FOR_nothing
))
1532 && mclass
== MODE_INT
)
1534 optab otheroptab
= (binoptab
== rotl_optab
? rotr_optab
: rotl_optab
);
1536 unsigned int bits
= GET_MODE_PRECISION (mode
);
1538 if (CONST_INT_P (op1
))
1539 newop1
= GEN_INT (bits
- INTVAL (op1
));
1540 else if (targetm
.shift_truncation_mask (mode
) == bits
- 1)
1541 newop1
= negate_rtx (GET_MODE (op1
), op1
);
1543 newop1
= expand_binop (GET_MODE (op1
), sub_optab
,
1544 GEN_INT (bits
), op1
,
1545 NULL_RTX
, unsignedp
, OPTAB_DIRECT
);
1547 temp
= expand_binop_directly (mode
, otheroptab
, op0
, newop1
,
1548 target
, unsignedp
, methods
, last
);
1553 /* If this is a multiply, see if we can do a widening operation that
1554 takes operands of this mode and makes a wider mode. */
1556 if (binoptab
== smul_optab
1557 && GET_MODE_2XWIDER_MODE (mode
) != VOIDmode
1558 && (widening_optab_handler ((unsignedp
? umul_widen_optab
1559 : smul_widen_optab
),
1560 GET_MODE_2XWIDER_MODE (mode
), mode
)
1561 != CODE_FOR_nothing
))
1563 temp
= expand_binop (GET_MODE_2XWIDER_MODE (mode
),
1564 unsignedp
? umul_widen_optab
: smul_widen_optab
,
1565 op0
, op1
, NULL_RTX
, unsignedp
, OPTAB_DIRECT
);
1569 if (GET_MODE_CLASS (mode
) == MODE_INT
1570 && TRULY_NOOP_TRUNCATION_MODES_P (mode
, GET_MODE (temp
)))
1571 return gen_lowpart (mode
, temp
);
1573 return convert_to_mode (mode
, temp
, unsignedp
);
1577 /* If this is a vector shift by a scalar, see if we can do a vector
1578 shift by a vector. If so, broadcast the scalar into a vector. */
1579 if (mclass
== MODE_VECTOR_INT
)
1581 optab otheroptab
= unknown_optab
;
1583 if (binoptab
== ashl_optab
)
1584 otheroptab
= vashl_optab
;
1585 else if (binoptab
== ashr_optab
)
1586 otheroptab
= vashr_optab
;
1587 else if (binoptab
== lshr_optab
)
1588 otheroptab
= vlshr_optab
;
1589 else if (binoptab
== rotl_optab
)
1590 otheroptab
= vrotl_optab
;
1591 else if (binoptab
== rotr_optab
)
1592 otheroptab
= vrotr_optab
;
1594 if (otheroptab
&& optab_handler (otheroptab
, mode
) != CODE_FOR_nothing
)
1596 rtx vop1
= expand_vector_broadcast (mode
, op1
);
1599 temp
= expand_binop_directly (mode
, otheroptab
, op0
, vop1
,
1600 target
, unsignedp
, methods
, last
);
1607 /* Look for a wider mode of the same class for which we think we
1608 can open-code the operation. Check for a widening multiply at the
1609 wider mode as well. */
1611 if (CLASS_HAS_WIDER_MODES_P (mclass
)
1612 && methods
!= OPTAB_DIRECT
&& methods
!= OPTAB_LIB
)
1613 for (wider_mode
= GET_MODE_WIDER_MODE (mode
);
1614 wider_mode
!= VOIDmode
;
1615 wider_mode
= GET_MODE_WIDER_MODE (wider_mode
))
1617 if (optab_handler (binoptab
, wider_mode
) != CODE_FOR_nothing
1618 || (binoptab
== smul_optab
1619 && GET_MODE_WIDER_MODE (wider_mode
) != VOIDmode
1620 && (find_widening_optab_handler ((unsignedp
1622 : smul_widen_optab
),
1623 GET_MODE_WIDER_MODE (wider_mode
),
1625 != CODE_FOR_nothing
)))
1627 rtx xop0
= op0
, xop1
= op1
;
1630 /* For certain integer operations, we need not actually extend
1631 the narrow operands, as long as we will truncate
1632 the results to the same narrowness. */
1634 if ((binoptab
== ior_optab
|| binoptab
== and_optab
1635 || binoptab
== xor_optab
1636 || binoptab
== add_optab
|| binoptab
== sub_optab
1637 || binoptab
== smul_optab
|| binoptab
== ashl_optab
)
1638 && mclass
== MODE_INT
)
1641 xop0
= avoid_expensive_constant (mode
, binoptab
, 0,
1643 if (binoptab
!= ashl_optab
)
1644 xop1
= avoid_expensive_constant (mode
, binoptab
, 1,
1648 xop0
= widen_operand (xop0
, wider_mode
, mode
, unsignedp
, no_extend
);
1650 /* The second operand of a shift must always be extended. */
1651 xop1
= widen_operand (xop1
, wider_mode
, mode
, unsignedp
,
1652 no_extend
&& binoptab
!= ashl_optab
);
1654 temp
= expand_binop (wider_mode
, binoptab
, xop0
, xop1
, NULL_RTX
,
1655 unsignedp
, OPTAB_DIRECT
);
1658 if (mclass
!= MODE_INT
1659 || !TRULY_NOOP_TRUNCATION_MODES_P (mode
, wider_mode
))
1662 target
= gen_reg_rtx (mode
);
1663 convert_move (target
, temp
, 0);
1667 return gen_lowpart (mode
, temp
);
1670 delete_insns_since (last
);
1674 /* If operation is commutative,
1675 try to make the first operand a register.
1676 Even better, try to make it the same as the target.
1677 Also try to make the last operand a constant. */
1678 if (commutative_optab_p (binoptab
)
1679 && swap_commutative_operands_with_target (target
, op0
, op1
))
1686 /* These can be done a word at a time. */
1687 if ((binoptab
== and_optab
|| binoptab
== ior_optab
|| binoptab
== xor_optab
)
1688 && mclass
== MODE_INT
1689 && GET_MODE_SIZE (mode
) > UNITS_PER_WORD
1690 && optab_handler (binoptab
, word_mode
) != CODE_FOR_nothing
)
1695 /* If TARGET is the same as one of the operands, the REG_EQUAL note
1696 won't be accurate, so use a new target. */
1700 || !valid_multiword_target_p (target
))
1701 target
= gen_reg_rtx (mode
);
1705 /* Do the actual arithmetic. */
1706 for (i
= 0; i
< GET_MODE_BITSIZE (mode
) / BITS_PER_WORD
; i
++)
1708 rtx target_piece
= operand_subword (target
, i
, 1, mode
);
1709 rtx x
= expand_binop (word_mode
, binoptab
,
1710 operand_subword_force (op0
, i
, mode
),
1711 operand_subword_force (op1
, i
, mode
),
1712 target_piece
, unsignedp
, next_methods
);
1717 if (target_piece
!= x
)
1718 emit_move_insn (target_piece
, x
);
1721 insns
= get_insns ();
1724 if (i
== GET_MODE_BITSIZE (mode
) / BITS_PER_WORD
)
1731 /* Synthesize double word shifts from single word shifts. */
1732 if ((binoptab
== lshr_optab
|| binoptab
== ashl_optab
1733 || binoptab
== ashr_optab
)
1734 && mclass
== MODE_INT
1735 && (CONST_INT_P (op1
) || optimize_insn_for_speed_p ())
1736 && GET_MODE_SIZE (mode
) == 2 * UNITS_PER_WORD
1737 && GET_MODE_PRECISION (mode
) == GET_MODE_BITSIZE (mode
)
1738 && optab_handler (binoptab
, word_mode
) != CODE_FOR_nothing
1739 && optab_handler (ashl_optab
, word_mode
) != CODE_FOR_nothing
1740 && optab_handler (lshr_optab
, word_mode
) != CODE_FOR_nothing
)
1742 unsigned HOST_WIDE_INT shift_mask
, double_shift_mask
;
1743 enum machine_mode op1_mode
;
1745 double_shift_mask
= targetm
.shift_truncation_mask (mode
);
1746 shift_mask
= targetm
.shift_truncation_mask (word_mode
);
1747 op1_mode
= GET_MODE (op1
) != VOIDmode
? GET_MODE (op1
) : word_mode
;
1749 /* Apply the truncation to constant shifts. */
1750 if (double_shift_mask
> 0 && CONST_INT_P (op1
))
1751 op1
= GEN_INT (INTVAL (op1
) & double_shift_mask
);
1753 if (op1
== CONST0_RTX (op1_mode
))
1756 /* Make sure that this is a combination that expand_doubleword_shift
1757 can handle. See the comments there for details. */
1758 if (double_shift_mask
== 0
1759 || (shift_mask
== BITS_PER_WORD
- 1
1760 && double_shift_mask
== BITS_PER_WORD
* 2 - 1))
1763 rtx into_target
, outof_target
;
1764 rtx into_input
, outof_input
;
1765 int left_shift
, outof_word
;
1767 /* If TARGET is the same as one of the operands, the REG_EQUAL note
1768 won't be accurate, so use a new target. */
1772 || !valid_multiword_target_p (target
))
1773 target
= gen_reg_rtx (mode
);
1777 /* OUTOF_* is the word we are shifting bits away from, and
1778 INTO_* is the word that we are shifting bits towards, thus
1779 they differ depending on the direction of the shift and
1780 WORDS_BIG_ENDIAN. */
1782 left_shift
= binoptab
== ashl_optab
;
1783 outof_word
= left_shift
^ ! WORDS_BIG_ENDIAN
;
1785 outof_target
= operand_subword (target
, outof_word
, 1, mode
);
1786 into_target
= operand_subword (target
, 1 - outof_word
, 1, mode
);
1788 outof_input
= operand_subword_force (op0
, outof_word
, mode
);
1789 into_input
= operand_subword_force (op0
, 1 - outof_word
, mode
);
1791 if (expand_doubleword_shift (op1_mode
, binoptab
,
1792 outof_input
, into_input
, op1
,
1793 outof_target
, into_target
,
1794 unsignedp
, next_methods
, shift_mask
))
1796 insns
= get_insns ();
1806 /* Synthesize double word rotates from single word shifts. */
1807 if ((binoptab
== rotl_optab
|| binoptab
== rotr_optab
)
1808 && mclass
== MODE_INT
1809 && CONST_INT_P (op1
)
1810 && GET_MODE_PRECISION (mode
) == 2 * BITS_PER_WORD
1811 && optab_handler (ashl_optab
, word_mode
) != CODE_FOR_nothing
1812 && optab_handler (lshr_optab
, word_mode
) != CODE_FOR_nothing
)
1815 rtx into_target
, outof_target
;
1816 rtx into_input
, outof_input
;
1818 int shift_count
, left_shift
, outof_word
;
1820 /* If TARGET is the same as one of the operands, the REG_EQUAL note
1821 won't be accurate, so use a new target. Do this also if target is not
1822 a REG, first because having a register instead may open optimization
1823 opportunities, and second because if target and op0 happen to be MEMs
1824 designating the same location, we would risk clobbering it too early
1825 in the code sequence we generate below. */
1830 || !valid_multiword_target_p (target
))
1831 target
= gen_reg_rtx (mode
);
1835 shift_count
= INTVAL (op1
);
1837 /* OUTOF_* is the word we are shifting bits away from, and
1838 INTO_* is the word that we are shifting bits towards, thus
1839 they differ depending on the direction of the shift and
1840 WORDS_BIG_ENDIAN. */
1842 left_shift
= (binoptab
== rotl_optab
);
1843 outof_word
= left_shift
^ ! WORDS_BIG_ENDIAN
;
1845 outof_target
= operand_subword (target
, outof_word
, 1, mode
);
1846 into_target
= operand_subword (target
, 1 - outof_word
, 1, mode
);
1848 outof_input
= operand_subword_force (op0
, outof_word
, mode
);
1849 into_input
= operand_subword_force (op0
, 1 - outof_word
, mode
);
1851 if (shift_count
== BITS_PER_WORD
)
1853 /* This is just a word swap. */
1854 emit_move_insn (outof_target
, into_input
);
1855 emit_move_insn (into_target
, outof_input
);
1860 rtx into_temp1
, into_temp2
, outof_temp1
, outof_temp2
;
1861 rtx first_shift_count
, second_shift_count
;
1862 optab reverse_unsigned_shift
, unsigned_shift
;
1864 reverse_unsigned_shift
= (left_shift
^ (shift_count
< BITS_PER_WORD
)
1865 ? lshr_optab
: ashl_optab
);
1867 unsigned_shift
= (left_shift
^ (shift_count
< BITS_PER_WORD
)
1868 ? ashl_optab
: lshr_optab
);
1870 if (shift_count
> BITS_PER_WORD
)
1872 first_shift_count
= GEN_INT (shift_count
- BITS_PER_WORD
);
1873 second_shift_count
= GEN_INT (2 * BITS_PER_WORD
- shift_count
);
1877 first_shift_count
= GEN_INT (BITS_PER_WORD
- shift_count
);
1878 second_shift_count
= GEN_INT (shift_count
);
1881 into_temp1
= expand_binop (word_mode
, unsigned_shift
,
1882 outof_input
, first_shift_count
,
1883 NULL_RTX
, unsignedp
, next_methods
);
1884 into_temp2
= expand_binop (word_mode
, reverse_unsigned_shift
,
1885 into_input
, second_shift_count
,
1886 NULL_RTX
, unsignedp
, next_methods
);
1888 if (into_temp1
!= 0 && into_temp2
!= 0)
1889 inter
= expand_binop (word_mode
, ior_optab
, into_temp1
, into_temp2
,
1890 into_target
, unsignedp
, next_methods
);
1894 if (inter
!= 0 && inter
!= into_target
)
1895 emit_move_insn (into_target
, inter
);
1897 outof_temp1
= expand_binop (word_mode
, unsigned_shift
,
1898 into_input
, first_shift_count
,
1899 NULL_RTX
, unsignedp
, next_methods
);
1900 outof_temp2
= expand_binop (word_mode
, reverse_unsigned_shift
,
1901 outof_input
, second_shift_count
,
1902 NULL_RTX
, unsignedp
, next_methods
);
1904 if (inter
!= 0 && outof_temp1
!= 0 && outof_temp2
!= 0)
1905 inter
= expand_binop (word_mode
, ior_optab
,
1906 outof_temp1
, outof_temp2
,
1907 outof_target
, unsignedp
, next_methods
);
1909 if (inter
!= 0 && inter
!= outof_target
)
1910 emit_move_insn (outof_target
, inter
);
1913 insns
= get_insns ();
1923 /* These can be done a word at a time by propagating carries. */
1924 if ((binoptab
== add_optab
|| binoptab
== sub_optab
)
1925 && mclass
== MODE_INT
1926 && GET_MODE_SIZE (mode
) >= 2 * UNITS_PER_WORD
1927 && optab_handler (binoptab
, word_mode
) != CODE_FOR_nothing
)
1930 optab otheroptab
= binoptab
== add_optab
? sub_optab
: add_optab
;
1931 const unsigned int nwords
= GET_MODE_BITSIZE (mode
) / BITS_PER_WORD
;
1932 rtx carry_in
= NULL_RTX
, carry_out
= NULL_RTX
;
1933 rtx xop0
, xop1
, xtarget
;
1935 /* We can handle either a 1 or -1 value for the carry. If STORE_FLAG
1936 value is one of those, use it. Otherwise, use 1 since it is the
1937 one easiest to get. */
1938 #if STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1
1939 int normalizep
= STORE_FLAG_VALUE
;
1944 /* Prepare the operands. */
1945 xop0
= force_reg (mode
, op0
);
1946 xop1
= force_reg (mode
, op1
);
1948 xtarget
= gen_reg_rtx (mode
);
1950 if (target
== 0 || !REG_P (target
) || !valid_multiword_target_p (target
))
1953 /* Indicate for flow that the entire target reg is being set. */
1955 emit_clobber (xtarget
);
1957 /* Do the actual arithmetic. */
1958 for (i
= 0; i
< nwords
; i
++)
1960 int index
= (WORDS_BIG_ENDIAN
? nwords
- i
- 1 : i
);
1961 rtx target_piece
= operand_subword (xtarget
, index
, 1, mode
);
1962 rtx op0_piece
= operand_subword_force (xop0
, index
, mode
);
1963 rtx op1_piece
= operand_subword_force (xop1
, index
, mode
);
1966 /* Main add/subtract of the input operands. */
1967 x
= expand_binop (word_mode
, binoptab
,
1968 op0_piece
, op1_piece
,
1969 target_piece
, unsignedp
, next_methods
);
1975 /* Store carry from main add/subtract. */
1976 carry_out
= gen_reg_rtx (word_mode
);
1977 carry_out
= emit_store_flag_force (carry_out
,
1978 (binoptab
== add_optab
1981 word_mode
, 1, normalizep
);
1988 /* Add/subtract previous carry to main result. */
1989 newx
= expand_binop (word_mode
,
1990 normalizep
== 1 ? binoptab
: otheroptab
,
1992 NULL_RTX
, 1, next_methods
);
1996 /* Get out carry from adding/subtracting carry in. */
1997 rtx carry_tmp
= gen_reg_rtx (word_mode
);
1998 carry_tmp
= emit_store_flag_force (carry_tmp
,
1999 (binoptab
== add_optab
2002 word_mode
, 1, normalizep
);
2004 /* Logical-ior the two poss. carry together. */
2005 carry_out
= expand_binop (word_mode
, ior_optab
,
2006 carry_out
, carry_tmp
,
2007 carry_out
, 0, next_methods
);
2011 emit_move_insn (target_piece
, newx
);
2015 if (x
!= target_piece
)
2016 emit_move_insn (target_piece
, x
);
2019 carry_in
= carry_out
;
2022 if (i
== GET_MODE_BITSIZE (mode
) / (unsigned) BITS_PER_WORD
)
2024 if (optab_handler (mov_optab
, mode
) != CODE_FOR_nothing
2025 || ! rtx_equal_p (target
, xtarget
))
2027 rtx temp
= emit_move_insn (target
, xtarget
);
2029 set_dst_reg_note (temp
, REG_EQUAL
,
2030 gen_rtx_fmt_ee (optab_to_code (binoptab
),
2031 mode
, copy_rtx (xop0
),
2042 delete_insns_since (last
);
2045 /* Attempt to synthesize double word multiplies using a sequence of word
2046 mode multiplications. We first attempt to generate a sequence using a
2047 more efficient unsigned widening multiply, and if that fails we then
2048 try using a signed widening multiply. */
2050 if (binoptab
== smul_optab
2051 && mclass
== MODE_INT
2052 && GET_MODE_SIZE (mode
) == 2 * UNITS_PER_WORD
2053 && optab_handler (smul_optab
, word_mode
) != CODE_FOR_nothing
2054 && optab_handler (add_optab
, word_mode
) != CODE_FOR_nothing
)
2056 rtx product
= NULL_RTX
;
2057 if (widening_optab_handler (umul_widen_optab
, mode
, word_mode
)
2058 != CODE_FOR_nothing
)
2060 product
= expand_doubleword_mult (mode
, op0
, op1
, target
,
2063 delete_insns_since (last
);
2066 if (product
== NULL_RTX
2067 && widening_optab_handler (smul_widen_optab
, mode
, word_mode
)
2068 != CODE_FOR_nothing
)
2070 product
= expand_doubleword_mult (mode
, op0
, op1
, target
,
2073 delete_insns_since (last
);
2076 if (product
!= NULL_RTX
)
2078 if (optab_handler (mov_optab
, mode
) != CODE_FOR_nothing
)
2080 temp
= emit_move_insn (target
? target
: product
, product
);
2081 set_dst_reg_note (temp
,
2083 gen_rtx_fmt_ee (MULT
, mode
,
2086 target
? target
: product
);
2092 /* It can't be open-coded in this mode.
2093 Use a library call if one is available and caller says that's ok. */
2095 libfunc
= optab_libfunc (binoptab
, mode
);
2097 && (methods
== OPTAB_LIB
|| methods
== OPTAB_LIB_WIDEN
))
2101 enum machine_mode op1_mode
= mode
;
2106 if (shift_optab_p (binoptab
))
2108 op1_mode
= targetm
.libgcc_shift_count_mode ();
2109 /* Specify unsigned here,
2110 since negative shift counts are meaningless. */
2111 op1x
= convert_to_mode (op1_mode
, op1
, 1);
2114 if (GET_MODE (op0
) != VOIDmode
2115 && GET_MODE (op0
) != mode
)
2116 op0
= convert_to_mode (mode
, op0
, unsignedp
);
2118 /* Pass 1 for NO_QUEUE so we don't lose any increments
2119 if the libcall is cse'd or moved. */
2120 value
= emit_library_call_value (libfunc
,
2121 NULL_RTX
, LCT_CONST
, mode
, 2,
2122 op0
, mode
, op1x
, op1_mode
);
2124 insns
= get_insns ();
2127 target
= gen_reg_rtx (mode
);
2128 emit_libcall_block_1 (insns
, target
, value
,
2129 gen_rtx_fmt_ee (optab_to_code (binoptab
),
2131 trapv_binoptab_p (binoptab
));
2136 delete_insns_since (last
);
2138 /* It can't be done in this mode. Can we do it in a wider mode? */
2140 if (! (methods
== OPTAB_WIDEN
|| methods
== OPTAB_LIB_WIDEN
2141 || methods
== OPTAB_MUST_WIDEN
))
2143 /* Caller says, don't even try. */
2144 delete_insns_since (entry_last
);
2148 /* Compute the value of METHODS to pass to recursive calls.
2149 Don't allow widening to be tried recursively. */
2151 methods
= (methods
== OPTAB_LIB_WIDEN
? OPTAB_LIB
: OPTAB_DIRECT
);
2153 /* Look for a wider mode of the same class for which it appears we can do
2156 if (CLASS_HAS_WIDER_MODES_P (mclass
))
2158 for (wider_mode
= GET_MODE_WIDER_MODE (mode
);
2159 wider_mode
!= VOIDmode
;
2160 wider_mode
= GET_MODE_WIDER_MODE (wider_mode
))
2162 if (find_widening_optab_handler (binoptab
, wider_mode
, mode
, 1)
2164 || (methods
== OPTAB_LIB
2165 && optab_libfunc (binoptab
, wider_mode
)))
2167 rtx xop0
= op0
, xop1
= op1
;
2170 /* For certain integer operations, we need not actually extend
2171 the narrow operands, as long as we will truncate
2172 the results to the same narrowness. */
2174 if ((binoptab
== ior_optab
|| binoptab
== and_optab
2175 || binoptab
== xor_optab
2176 || binoptab
== add_optab
|| binoptab
== sub_optab
2177 || binoptab
== smul_optab
|| binoptab
== ashl_optab
)
2178 && mclass
== MODE_INT
)
2181 xop0
= widen_operand (xop0
, wider_mode
, mode
,
2182 unsignedp
, no_extend
);
2184 /* The second operand of a shift must always be extended. */
2185 xop1
= widen_operand (xop1
, wider_mode
, mode
, unsignedp
,
2186 no_extend
&& binoptab
!= ashl_optab
);
2188 temp
= expand_binop (wider_mode
, binoptab
, xop0
, xop1
, NULL_RTX
,
2189 unsignedp
, methods
);
2192 if (mclass
!= MODE_INT
2193 || !TRULY_NOOP_TRUNCATION_MODES_P (mode
, wider_mode
))
2196 target
= gen_reg_rtx (mode
);
2197 convert_move (target
, temp
, 0);
2201 return gen_lowpart (mode
, temp
);
2204 delete_insns_since (last
);
2209 delete_insns_since (entry_last
);
2213 /* Expand a binary operator which has both signed and unsigned forms.
2214 UOPTAB is the optab for unsigned operations, and SOPTAB is for
2217 If we widen unsigned operands, we may use a signed wider operation instead
2218 of an unsigned wider operation, since the result would be the same. */
2221 sign_expand_binop (enum machine_mode mode
, optab uoptab
, optab soptab
,
2222 rtx op0
, rtx op1
, rtx target
, int unsignedp
,
2223 enum optab_methods methods
)
2226 optab direct_optab
= unsignedp
? uoptab
: soptab
;
2229 /* Do it without widening, if possible. */
2230 temp
= expand_binop (mode
, direct_optab
, op0
, op1
, target
,
2231 unsignedp
, OPTAB_DIRECT
);
2232 if (temp
|| methods
== OPTAB_DIRECT
)
2235 /* Try widening to a signed int. Disable any direct use of any
2236 signed insn in the current mode. */
2237 save_enable
= swap_optab_enable (soptab
, mode
, false);
2239 temp
= expand_binop (mode
, soptab
, op0
, op1
, target
,
2240 unsignedp
, OPTAB_WIDEN
);
2242 /* For unsigned operands, try widening to an unsigned int. */
2243 if (!temp
&& unsignedp
)
2244 temp
= expand_binop (mode
, uoptab
, op0
, op1
, target
,
2245 unsignedp
, OPTAB_WIDEN
);
2246 if (temp
|| methods
== OPTAB_WIDEN
)
2249 /* Use the right width libcall if that exists. */
2250 temp
= expand_binop (mode
, direct_optab
, op0
, op1
, target
,
2251 unsignedp
, OPTAB_LIB
);
2252 if (temp
|| methods
== OPTAB_LIB
)
2255 /* Must widen and use a libcall, use either signed or unsigned. */
2256 temp
= expand_binop (mode
, soptab
, op0
, op1
, target
,
2257 unsignedp
, methods
);
2258 if (!temp
&& unsignedp
)
2259 temp
= expand_binop (mode
, uoptab
, op0
, op1
, target
,
2260 unsignedp
, methods
);
2263 /* Undo the fiddling above. */
2265 swap_optab_enable (soptab
, mode
, true);
2269 /* Generate code to perform an operation specified by UNOPPTAB
2270 on operand OP0, with two results to TARG0 and TARG1.
2271 We assume that the order of the operands for the instruction
2272 is TARG0, TARG1, OP0.
2274 Either TARG0 or TARG1 may be zero, but what that means is that
2275 the result is not actually wanted. We will generate it into
2276 a dummy pseudo-reg and discard it. They may not both be zero.
2278 Returns 1 if this operation can be performed; 0 if not. */
2281 expand_twoval_unop (optab unoptab
, rtx op0
, rtx targ0
, rtx targ1
,
2284 enum machine_mode mode
= GET_MODE (targ0
? targ0
: targ1
);
2285 enum mode_class mclass
;
2286 enum machine_mode wider_mode
;
2287 rtx entry_last
= get_last_insn ();
2290 mclass
= GET_MODE_CLASS (mode
);
2293 targ0
= gen_reg_rtx (mode
);
2295 targ1
= gen_reg_rtx (mode
);
2297 /* Record where to go back to if we fail. */
2298 last
= get_last_insn ();
2300 if (optab_handler (unoptab
, mode
) != CODE_FOR_nothing
)
2302 struct expand_operand ops
[3];
2303 enum insn_code icode
= optab_handler (unoptab
, mode
);
2305 create_fixed_operand (&ops
[0], targ0
);
2306 create_fixed_operand (&ops
[1], targ1
);
2307 create_convert_operand_from (&ops
[2], op0
, mode
, unsignedp
);
2308 if (maybe_expand_insn (icode
, 3, ops
))
2312 /* It can't be done in this mode. Can we do it in a wider mode? */
2314 if (CLASS_HAS_WIDER_MODES_P (mclass
))
2316 for (wider_mode
= GET_MODE_WIDER_MODE (mode
);
2317 wider_mode
!= VOIDmode
;
2318 wider_mode
= GET_MODE_WIDER_MODE (wider_mode
))
2320 if (optab_handler (unoptab
, wider_mode
) != CODE_FOR_nothing
)
2322 rtx t0
= gen_reg_rtx (wider_mode
);
2323 rtx t1
= gen_reg_rtx (wider_mode
);
2324 rtx cop0
= convert_modes (wider_mode
, mode
, op0
, unsignedp
);
2326 if (expand_twoval_unop (unoptab
, cop0
, t0
, t1
, unsignedp
))
2328 convert_move (targ0
, t0
, unsignedp
);
2329 convert_move (targ1
, t1
, unsignedp
);
2333 delete_insns_since (last
);
2338 delete_insns_since (entry_last
);
2342 /* Generate code to perform an operation specified by BINOPTAB
2343 on operands OP0 and OP1, with two results to TARG1 and TARG2.
2344 We assume that the order of the operands for the instruction
2345 is TARG0, OP0, OP1, TARG1, which would fit a pattern like
2346 [(set TARG0 (operate OP0 OP1)) (set TARG1 (operate ...))].
2348 Either TARG0 or TARG1 may be zero, but what that means is that
2349 the result is not actually wanted. We will generate it into
2350 a dummy pseudo-reg and discard it. They may not both be zero.
2352 Returns 1 if this operation can be performed; 0 if not. */
2355 expand_twoval_binop (optab binoptab
, rtx op0
, rtx op1
, rtx targ0
, rtx targ1
,
2358 enum machine_mode mode
= GET_MODE (targ0
? targ0
: targ1
);
2359 enum mode_class mclass
;
2360 enum machine_mode wider_mode
;
2361 rtx entry_last
= get_last_insn ();
2364 mclass
= GET_MODE_CLASS (mode
);
2367 targ0
= gen_reg_rtx (mode
);
2369 targ1
= gen_reg_rtx (mode
);
2371 /* Record where to go back to if we fail. */
2372 last
= get_last_insn ();
2374 if (optab_handler (binoptab
, mode
) != CODE_FOR_nothing
)
2376 struct expand_operand ops
[4];
2377 enum insn_code icode
= optab_handler (binoptab
, mode
);
2378 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
2379 enum machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
2380 rtx xop0
= op0
, xop1
= op1
;
2382 /* If we are optimizing, force expensive constants into a register. */
2383 xop0
= avoid_expensive_constant (mode0
, binoptab
, 0, xop0
, unsignedp
);
2384 xop1
= avoid_expensive_constant (mode1
, binoptab
, 1, xop1
, unsignedp
);
2386 create_fixed_operand (&ops
[0], targ0
);
2387 create_convert_operand_from (&ops
[1], op0
, mode
, unsignedp
);
2388 create_convert_operand_from (&ops
[2], op1
, mode
, unsignedp
);
2389 create_fixed_operand (&ops
[3], targ1
);
2390 if (maybe_expand_insn (icode
, 4, ops
))
2392 delete_insns_since (last
);
2395 /* It can't be done in this mode. Can we do it in a wider mode? */
2397 if (CLASS_HAS_WIDER_MODES_P (mclass
))
2399 for (wider_mode
= GET_MODE_WIDER_MODE (mode
);
2400 wider_mode
!= VOIDmode
;
2401 wider_mode
= GET_MODE_WIDER_MODE (wider_mode
))
2403 if (optab_handler (binoptab
, wider_mode
) != CODE_FOR_nothing
)
2405 rtx t0
= gen_reg_rtx (wider_mode
);
2406 rtx t1
= gen_reg_rtx (wider_mode
);
2407 rtx cop0
= convert_modes (wider_mode
, mode
, op0
, unsignedp
);
2408 rtx cop1
= convert_modes (wider_mode
, mode
, op1
, unsignedp
);
2410 if (expand_twoval_binop (binoptab
, cop0
, cop1
,
2413 convert_move (targ0
, t0
, unsignedp
);
2414 convert_move (targ1
, t1
, unsignedp
);
2418 delete_insns_since (last
);
2423 delete_insns_since (entry_last
);
2427 /* Expand the two-valued library call indicated by BINOPTAB, but
2428 preserve only one of the values. If TARG0 is non-NULL, the first
2429 value is placed into TARG0; otherwise the second value is placed
2430 into TARG1. Exactly one of TARG0 and TARG1 must be non-NULL. The
2431 value stored into TARG0 or TARG1 is equivalent to (CODE OP0 OP1).
2432 This routine assumes that the value returned by the library call is
2433 as if the return value was of an integral mode twice as wide as the
2434 mode of OP0. Returns 1 if the call was successful. */
2437 expand_twoval_binop_libfunc (optab binoptab
, rtx op0
, rtx op1
,
2438 rtx targ0
, rtx targ1
, enum rtx_code code
)
2440 enum machine_mode mode
;
2441 enum machine_mode libval_mode
;
2446 /* Exactly one of TARG0 or TARG1 should be non-NULL. */
2447 gcc_assert (!targ0
!= !targ1
);
2449 mode
= GET_MODE (op0
);
2450 libfunc
= optab_libfunc (binoptab
, mode
);
2454 /* The value returned by the library function will have twice as
2455 many bits as the nominal MODE. */
2456 libval_mode
= smallest_mode_for_size (2 * GET_MODE_BITSIZE (mode
),
2459 libval
= emit_library_call_value (libfunc
, NULL_RTX
, LCT_CONST
,
2463 /* Get the part of VAL containing the value that we want. */
2464 libval
= simplify_gen_subreg (mode
, libval
, libval_mode
,
2465 targ0
? 0 : GET_MODE_SIZE (mode
));
2466 insns
= get_insns ();
2468 /* Move the into the desired location. */
2469 emit_libcall_block (insns
, targ0
? targ0
: targ1
, libval
,
2470 gen_rtx_fmt_ee (code
, mode
, op0
, op1
));
2476 /* Wrapper around expand_unop which takes an rtx code to specify
2477 the operation to perform, not an optab pointer. All other
2478 arguments are the same. */
2480 expand_simple_unop (enum machine_mode mode
, enum rtx_code code
, rtx op0
,
2481 rtx target
, int unsignedp
)
2483 optab unop
= code_to_optab (code
);
2486 return expand_unop (mode
, unop
, op0
, target
, unsignedp
);
2492 (clz:wide (zero_extend:wide x)) - ((width wide) - (width narrow)).
2494 A similar operation can be used for clrsb. UNOPTAB says which operation
2495 we are trying to expand. */
2497 widen_leading (enum machine_mode mode
, rtx op0
, rtx target
, optab unoptab
)
2499 enum mode_class mclass
= GET_MODE_CLASS (mode
);
2500 if (CLASS_HAS_WIDER_MODES_P (mclass
))
2502 enum machine_mode wider_mode
;
2503 for (wider_mode
= GET_MODE_WIDER_MODE (mode
);
2504 wider_mode
!= VOIDmode
;
2505 wider_mode
= GET_MODE_WIDER_MODE (wider_mode
))
2507 if (optab_handler (unoptab
, wider_mode
) != CODE_FOR_nothing
)
2509 rtx xop0
, temp
, last
;
2511 last
= get_last_insn ();
2514 target
= gen_reg_rtx (mode
);
2515 xop0
= widen_operand (op0
, wider_mode
, mode
,
2516 unoptab
!= clrsb_optab
, false);
2517 temp
= expand_unop (wider_mode
, unoptab
, xop0
, NULL_RTX
,
2518 unoptab
!= clrsb_optab
);
2520 temp
= expand_binop (wider_mode
, sub_optab
, temp
,
2521 GEN_INT (GET_MODE_PRECISION (wider_mode
)
2522 - GET_MODE_PRECISION (mode
)),
2523 target
, true, OPTAB_DIRECT
);
2525 delete_insns_since (last
);
2534 /* Try calculating clz of a double-word quantity as two clz's of word-sized
2535 quantities, choosing which based on whether the high word is nonzero. */
2537 expand_doubleword_clz (enum machine_mode mode
, rtx op0
, rtx target
)
2539 rtx xop0
= force_reg (mode
, op0
);
2540 rtx subhi
= gen_highpart (word_mode
, xop0
);
2541 rtx sublo
= gen_lowpart (word_mode
, xop0
);
2542 rtx hi0_label
= gen_label_rtx ();
2543 rtx after_label
= gen_label_rtx ();
2544 rtx seq
, temp
, result
;
2546 /* If we were not given a target, use a word_mode register, not a
2547 'mode' register. The result will fit, and nobody is expecting
2548 anything bigger (the return type of __builtin_clz* is int). */
2550 target
= gen_reg_rtx (word_mode
);
2552 /* In any case, write to a word_mode scratch in both branches of the
2553 conditional, so we can ensure there is a single move insn setting
2554 'target' to tag a REG_EQUAL note on. */
2555 result
= gen_reg_rtx (word_mode
);
2559 /* If the high word is not equal to zero,
2560 then clz of the full value is clz of the high word. */
2561 emit_cmp_and_jump_insns (subhi
, CONST0_RTX (word_mode
), EQ
, 0,
2562 word_mode
, true, hi0_label
);
2564 temp
= expand_unop_direct (word_mode
, clz_optab
, subhi
, result
, true);
2569 convert_move (result
, temp
, true);
2571 emit_jump_insn (gen_jump (after_label
));
2574 /* Else clz of the full value is clz of the low word plus the number
2575 of bits in the high word. */
2576 emit_label (hi0_label
);
2578 temp
= expand_unop_direct (word_mode
, clz_optab
, sublo
, 0, true);
2581 temp
= expand_binop (word_mode
, add_optab
, temp
,
2582 GEN_INT (GET_MODE_BITSIZE (word_mode
)),
2583 result
, true, OPTAB_DIRECT
);
2587 convert_move (result
, temp
, true);
2589 emit_label (after_label
);
2590 convert_move (target
, result
, true);
2595 add_equal_note (seq
, target
, CLZ
, xop0
, 0);
2607 (lshiftrt:wide (bswap:wide x) ((width wide) - (width narrow))). */
2609 widen_bswap (enum machine_mode mode
, rtx op0
, rtx target
)
2611 enum mode_class mclass
= GET_MODE_CLASS (mode
);
2612 enum machine_mode wider_mode
;
2615 if (!CLASS_HAS_WIDER_MODES_P (mclass
))
2618 for (wider_mode
= GET_MODE_WIDER_MODE (mode
);
2619 wider_mode
!= VOIDmode
;
2620 wider_mode
= GET_MODE_WIDER_MODE (wider_mode
))
2621 if (optab_handler (bswap_optab
, wider_mode
) != CODE_FOR_nothing
)
2626 last
= get_last_insn ();
2628 x
= widen_operand (op0
, wider_mode
, mode
, true, true);
2629 x
= expand_unop (wider_mode
, bswap_optab
, x
, NULL_RTX
, true);
2631 gcc_assert (GET_MODE_PRECISION (wider_mode
) == GET_MODE_BITSIZE (wider_mode
)
2632 && GET_MODE_PRECISION (mode
) == GET_MODE_BITSIZE (mode
));
2634 x
= expand_shift (RSHIFT_EXPR
, wider_mode
, x
,
2635 GET_MODE_BITSIZE (wider_mode
)
2636 - GET_MODE_BITSIZE (mode
),
2642 target
= gen_reg_rtx (mode
);
2643 emit_move_insn (target
, gen_lowpart (mode
, x
));
2646 delete_insns_since (last
);
2651 /* Try calculating bswap as two bswaps of two word-sized operands. */
2654 expand_doubleword_bswap (enum machine_mode mode
, rtx op
, rtx target
)
2658 t1
= expand_unop (word_mode
, bswap_optab
,
2659 operand_subword_force (op
, 0, mode
), NULL_RTX
, true);
2660 t0
= expand_unop (word_mode
, bswap_optab
,
2661 operand_subword_force (op
, 1, mode
), NULL_RTX
, true);
2663 if (target
== 0 || !valid_multiword_target_p (target
))
2664 target
= gen_reg_rtx (mode
);
2666 emit_clobber (target
);
2667 emit_move_insn (operand_subword (target
, 0, 1, mode
), t0
);
2668 emit_move_insn (operand_subword (target
, 1, 1, mode
), t1
);
2673 /* Try calculating (parity x) as (and (popcount x) 1), where
2674 popcount can also be done in a wider mode. */
2676 expand_parity (enum machine_mode mode
, rtx op0
, rtx target
)
2678 enum mode_class mclass
= GET_MODE_CLASS (mode
);
2679 if (CLASS_HAS_WIDER_MODES_P (mclass
))
2681 enum machine_mode wider_mode
;
2682 for (wider_mode
= mode
; wider_mode
!= VOIDmode
;
2683 wider_mode
= GET_MODE_WIDER_MODE (wider_mode
))
2685 if (optab_handler (popcount_optab
, wider_mode
) != CODE_FOR_nothing
)
2687 rtx xop0
, temp
, last
;
2689 last
= get_last_insn ();
2692 target
= gen_reg_rtx (mode
);
2693 xop0
= widen_operand (op0
, wider_mode
, mode
, true, false);
2694 temp
= expand_unop (wider_mode
, popcount_optab
, xop0
, NULL_RTX
,
2697 temp
= expand_binop (wider_mode
, and_optab
, temp
, const1_rtx
,
2698 target
, true, OPTAB_DIRECT
);
2700 delete_insns_since (last
);
2709 /* Try calculating ctz(x) as K - clz(x & -x) ,
2710 where K is GET_MODE_PRECISION(mode) - 1.
2712 Both __builtin_ctz and __builtin_clz are undefined at zero, so we
2713 don't have to worry about what the hardware does in that case. (If
2714 the clz instruction produces the usual value at 0, which is K, the
2715 result of this code sequence will be -1; expand_ffs, below, relies
2716 on this. It might be nice to have it be K instead, for consistency
2717 with the (very few) processors that provide a ctz with a defined
2718 value, but that would take one more instruction, and it would be
2719 less convenient for expand_ffs anyway. */
2722 expand_ctz (enum machine_mode mode
, rtx op0
, rtx target
)
2726 if (optab_handler (clz_optab
, mode
) == CODE_FOR_nothing
)
2731 temp
= expand_unop_direct (mode
, neg_optab
, op0
, NULL_RTX
, true);
2733 temp
= expand_binop (mode
, and_optab
, op0
, temp
, NULL_RTX
,
2734 true, OPTAB_DIRECT
);
2736 temp
= expand_unop_direct (mode
, clz_optab
, temp
, NULL_RTX
, true);
2738 temp
= expand_binop (mode
, sub_optab
, GEN_INT (GET_MODE_PRECISION (mode
) - 1),
2740 true, OPTAB_DIRECT
);
2750 add_equal_note (seq
, temp
, CTZ
, op0
, 0);
2756 /* Try calculating ffs(x) using ctz(x) if we have that instruction, or
2757 else with the sequence used by expand_clz.
2759 The ffs builtin promises to return zero for a zero value and ctz/clz
2760 may have an undefined value in that case. If they do not give us a
2761 convenient value, we have to generate a test and branch. */
2763 expand_ffs (enum machine_mode mode
, rtx op0
, rtx target
)
2765 HOST_WIDE_INT val
= 0;
2766 bool defined_at_zero
= false;
2769 if (optab_handler (ctz_optab
, mode
) != CODE_FOR_nothing
)
2773 temp
= expand_unop_direct (mode
, ctz_optab
, op0
, 0, true);
2777 defined_at_zero
= (CTZ_DEFINED_VALUE_AT_ZERO (mode
, val
) == 2);
2779 else if (optab_handler (clz_optab
, mode
) != CODE_FOR_nothing
)
2782 temp
= expand_ctz (mode
, op0
, 0);
2786 if (CLZ_DEFINED_VALUE_AT_ZERO (mode
, val
) == 2)
2788 defined_at_zero
= true;
2789 val
= (GET_MODE_PRECISION (mode
) - 1) - val
;
2795 if (defined_at_zero
&& val
== -1)
2796 /* No correction needed at zero. */;
2799 /* We don't try to do anything clever with the situation found
2800 on some processors (eg Alpha) where ctz(0:mode) ==
2801 bitsize(mode). If someone can think of a way to send N to -1
2802 and leave alone all values in the range 0..N-1 (where N is a
2803 power of two), cheaper than this test-and-branch, please add it.
2805 The test-and-branch is done after the operation itself, in case
2806 the operation sets condition codes that can be recycled for this.
2807 (This is true on i386, for instance.) */
2809 rtx nonzero_label
= gen_label_rtx ();
2810 emit_cmp_and_jump_insns (op0
, CONST0_RTX (mode
), NE
, 0,
2811 mode
, true, nonzero_label
);
2813 convert_move (temp
, GEN_INT (-1), false);
2814 emit_label (nonzero_label
);
2817 /* temp now has a value in the range -1..bitsize-1. ffs is supposed
2818 to produce a value in the range 0..bitsize. */
2819 temp
= expand_binop (mode
, add_optab
, temp
, GEN_INT (1),
2820 target
, false, OPTAB_DIRECT
);
2827 add_equal_note (seq
, temp
, FFS
, op0
, 0);
2836 /* Extract the OMODE lowpart from VAL, which has IMODE. Under certain
2837 conditions, VAL may already be a SUBREG against which we cannot generate
2838 a further SUBREG. In this case, we expect forcing the value into a
2839 register will work around the situation. */
2842 lowpart_subreg_maybe_copy (enum machine_mode omode
, rtx val
,
2843 enum machine_mode imode
)
2846 ret
= lowpart_subreg (omode
, val
, imode
);
2849 val
= force_reg (imode
, val
);
2850 ret
= lowpart_subreg (omode
, val
, imode
);
2851 gcc_assert (ret
!= NULL
);
2856 /* Expand a floating point absolute value or negation operation via a
2857 logical operation on the sign bit. */
2860 expand_absneg_bit (enum rtx_code code
, enum machine_mode mode
,
2861 rtx op0
, rtx target
)
2863 const struct real_format
*fmt
;
2864 int bitpos
, word
, nwords
, i
;
2865 enum machine_mode imode
;
2869 /* The format has to have a simple sign bit. */
2870 fmt
= REAL_MODE_FORMAT (mode
);
2874 bitpos
= fmt
->signbit_rw
;
2878 /* Don't create negative zeros if the format doesn't support them. */
2879 if (code
== NEG
&& !fmt
->has_signed_zero
)
2882 if (GET_MODE_SIZE (mode
) <= UNITS_PER_WORD
)
2884 imode
= int_mode_for_mode (mode
);
2885 if (imode
== BLKmode
)
2894 if (FLOAT_WORDS_BIG_ENDIAN
)
2895 word
= (GET_MODE_BITSIZE (mode
) - bitpos
) / BITS_PER_WORD
;
2897 word
= bitpos
/ BITS_PER_WORD
;
2898 bitpos
= bitpos
% BITS_PER_WORD
;
2899 nwords
= (GET_MODE_BITSIZE (mode
) + BITS_PER_WORD
- 1) / BITS_PER_WORD
;
2902 mask
= double_int_zero
.set_bit (bitpos
);
2908 || (nwords
> 1 && !valid_multiword_target_p (target
)))
2909 target
= gen_reg_rtx (mode
);
2915 for (i
= 0; i
< nwords
; ++i
)
2917 rtx targ_piece
= operand_subword (target
, i
, 1, mode
);
2918 rtx op0_piece
= operand_subword_force (op0
, i
, mode
);
2922 temp
= expand_binop (imode
, code
== ABS
? and_optab
: xor_optab
,
2924 immed_double_int_const (mask
, imode
),
2925 targ_piece
, 1, OPTAB_LIB_WIDEN
);
2926 if (temp
!= targ_piece
)
2927 emit_move_insn (targ_piece
, temp
);
2930 emit_move_insn (targ_piece
, op0_piece
);
2933 insns
= get_insns ();
2940 temp
= expand_binop (imode
, code
== ABS
? and_optab
: xor_optab
,
2941 gen_lowpart (imode
, op0
),
2942 immed_double_int_const (mask
, imode
),
2943 gen_lowpart (imode
, target
), 1, OPTAB_LIB_WIDEN
);
2944 target
= lowpart_subreg_maybe_copy (mode
, temp
, imode
);
2946 set_dst_reg_note (get_last_insn (), REG_EQUAL
,
2947 gen_rtx_fmt_e (code
, mode
, copy_rtx (op0
)),
2954 /* As expand_unop, but will fail rather than attempt the operation in a
2955 different mode or with a libcall. */
2957 expand_unop_direct (enum machine_mode mode
, optab unoptab
, rtx op0
, rtx target
,
2960 if (optab_handler (unoptab
, mode
) != CODE_FOR_nothing
)
2962 struct expand_operand ops
[2];
2963 enum insn_code icode
= optab_handler (unoptab
, mode
);
2964 rtx last
= get_last_insn ();
2967 create_output_operand (&ops
[0], target
, mode
);
2968 create_convert_operand_from (&ops
[1], op0
, mode
, unsignedp
);
2969 pat
= maybe_gen_insn (icode
, 2, ops
);
2972 if (INSN_P (pat
) && NEXT_INSN (pat
) != NULL_RTX
2973 && ! add_equal_note (pat
, ops
[0].value
, optab_to_code (unoptab
),
2974 ops
[1].value
, NULL_RTX
))
2976 delete_insns_since (last
);
2977 return expand_unop (mode
, unoptab
, op0
, NULL_RTX
, unsignedp
);
2982 return ops
[0].value
;
2988 /* Generate code to perform an operation specified by UNOPTAB
2989 on operand OP0, with result having machine-mode MODE.
2991 UNSIGNEDP is for the case where we have to widen the operands
2992 to perform the operation. It says to use zero-extension.
2994 If TARGET is nonzero, the value
2995 is generated there, if it is convenient to do so.
2996 In all cases an rtx is returned for the locus of the value;
2997 this may or may not be TARGET. */
3000 expand_unop (enum machine_mode mode
, optab unoptab
, rtx op0
, rtx target
,
3003 enum mode_class mclass
= GET_MODE_CLASS (mode
);
3004 enum machine_mode wider_mode
;
3008 temp
= expand_unop_direct (mode
, unoptab
, op0
, target
, unsignedp
);
3012 /* It can't be done in this mode. Can we open-code it in a wider mode? */
3014 /* Widening (or narrowing) clz needs special treatment. */
3015 if (unoptab
== clz_optab
)
3017 temp
= widen_leading (mode
, op0
, target
, unoptab
);
3021 if (GET_MODE_SIZE (mode
) == 2 * UNITS_PER_WORD
3022 && optab_handler (unoptab
, word_mode
) != CODE_FOR_nothing
)
3024 temp
= expand_doubleword_clz (mode
, op0
, target
);
3032 if (unoptab
== clrsb_optab
)
3034 temp
= widen_leading (mode
, op0
, target
, unoptab
);
3040 /* Widening (or narrowing) bswap needs special treatment. */
3041 if (unoptab
== bswap_optab
)
3043 /* HImode is special because in this mode BSWAP is equivalent to ROTATE
3044 or ROTATERT. First try these directly; if this fails, then try the
3045 obvious pair of shifts with allowed widening, as this will probably
3046 be always more efficient than the other fallback methods. */
3049 rtx last
, temp1
, temp2
;
3051 if (optab_handler (rotl_optab
, mode
) != CODE_FOR_nothing
)
3053 temp
= expand_binop (mode
, rotl_optab
, op0
, GEN_INT (8), target
,
3054 unsignedp
, OPTAB_DIRECT
);
3059 if (optab_handler (rotr_optab
, mode
) != CODE_FOR_nothing
)
3061 temp
= expand_binop (mode
, rotr_optab
, op0
, GEN_INT (8), target
,
3062 unsignedp
, OPTAB_DIRECT
);
3067 last
= get_last_insn ();
3069 temp1
= expand_binop (mode
, ashl_optab
, op0
, GEN_INT (8), NULL_RTX
,
3070 unsignedp
, OPTAB_WIDEN
);
3071 temp2
= expand_binop (mode
, lshr_optab
, op0
, GEN_INT (8), NULL_RTX
,
3072 unsignedp
, OPTAB_WIDEN
);
3075 temp
= expand_binop (mode
, ior_optab
, temp1
, temp2
, target
,
3076 unsignedp
, OPTAB_WIDEN
);
3081 delete_insns_since (last
);
3084 temp
= widen_bswap (mode
, op0
, target
);
3088 if (GET_MODE_SIZE (mode
) == 2 * UNITS_PER_WORD
3089 && optab_handler (unoptab
, word_mode
) != CODE_FOR_nothing
)
3091 temp
= expand_doubleword_bswap (mode
, op0
, target
);
3099 if (CLASS_HAS_WIDER_MODES_P (mclass
))
3100 for (wider_mode
= GET_MODE_WIDER_MODE (mode
);
3101 wider_mode
!= VOIDmode
;
3102 wider_mode
= GET_MODE_WIDER_MODE (wider_mode
))
3104 if (optab_handler (unoptab
, wider_mode
) != CODE_FOR_nothing
)
3107 rtx last
= get_last_insn ();
3109 /* For certain operations, we need not actually extend
3110 the narrow operand, as long as we will truncate the
3111 results to the same narrowness. */
3113 xop0
= widen_operand (xop0
, wider_mode
, mode
, unsignedp
,
3114 (unoptab
== neg_optab
3115 || unoptab
== one_cmpl_optab
)
3116 && mclass
== MODE_INT
);
3118 temp
= expand_unop (wider_mode
, unoptab
, xop0
, NULL_RTX
,
3123 if (mclass
!= MODE_INT
3124 || !TRULY_NOOP_TRUNCATION_MODES_P (mode
, wider_mode
))
3127 target
= gen_reg_rtx (mode
);
3128 convert_move (target
, temp
, 0);
3132 return gen_lowpart (mode
, temp
);
3135 delete_insns_since (last
);
3139 /* These can be done a word at a time. */
3140 if (unoptab
== one_cmpl_optab
3141 && mclass
== MODE_INT
3142 && GET_MODE_SIZE (mode
) > UNITS_PER_WORD
3143 && optab_handler (unoptab
, word_mode
) != CODE_FOR_nothing
)
3148 if (target
== 0 || target
== op0
|| !valid_multiword_target_p (target
))
3149 target
= gen_reg_rtx (mode
);
3153 /* Do the actual arithmetic. */
3154 for (i
= 0; i
< GET_MODE_BITSIZE (mode
) / BITS_PER_WORD
; i
++)
3156 rtx target_piece
= operand_subword (target
, i
, 1, mode
);
3157 rtx x
= expand_unop (word_mode
, unoptab
,
3158 operand_subword_force (op0
, i
, mode
),
3159 target_piece
, unsignedp
);
3161 if (target_piece
!= x
)
3162 emit_move_insn (target_piece
, x
);
3165 insns
= get_insns ();
3172 if (optab_to_code (unoptab
) == NEG
)
3174 /* Try negating floating point values by flipping the sign bit. */
3175 if (SCALAR_FLOAT_MODE_P (mode
))
3177 temp
= expand_absneg_bit (NEG
, mode
, op0
, target
);
3182 /* If there is no negation pattern, and we have no negative zero,
3183 try subtracting from zero. */
3184 if (!HONOR_SIGNED_ZEROS (mode
))
3186 temp
= expand_binop (mode
, (unoptab
== negv_optab
3187 ? subv_optab
: sub_optab
),
3188 CONST0_RTX (mode
), op0
, target
,
3189 unsignedp
, OPTAB_DIRECT
);
3195 /* Try calculating parity (x) as popcount (x) % 2. */
3196 if (unoptab
== parity_optab
)
3198 temp
= expand_parity (mode
, op0
, target
);
3203 /* Try implementing ffs (x) in terms of clz (x). */
3204 if (unoptab
== ffs_optab
)
3206 temp
= expand_ffs (mode
, op0
, target
);
3211 /* Try implementing ctz (x) in terms of clz (x). */
3212 if (unoptab
== ctz_optab
)
3214 temp
= expand_ctz (mode
, op0
, target
);
3220 /* Now try a library call in this mode. */
3221 libfunc
= optab_libfunc (unoptab
, mode
);
3227 enum machine_mode outmode
= mode
;
3229 /* All of these functions return small values. Thus we choose to
3230 have them return something that isn't a double-word. */
3231 if (unoptab
== ffs_optab
|| unoptab
== clz_optab
|| unoptab
== ctz_optab
3232 || unoptab
== clrsb_optab
|| unoptab
== popcount_optab
3233 || unoptab
== parity_optab
)
3235 = GET_MODE (hard_libcall_value (TYPE_MODE (integer_type_node
),
3236 optab_libfunc (unoptab
, mode
)));
3240 /* Pass 1 for NO_QUEUE so we don't lose any increments
3241 if the libcall is cse'd or moved. */
3242 value
= emit_library_call_value (libfunc
, NULL_RTX
, LCT_CONST
, outmode
,
3244 insns
= get_insns ();
3247 target
= gen_reg_rtx (outmode
);
3248 eq_value
= gen_rtx_fmt_e (optab_to_code (unoptab
), mode
, op0
);
3249 if (GET_MODE_SIZE (outmode
) < GET_MODE_SIZE (mode
))
3250 eq_value
= simplify_gen_unary (TRUNCATE
, outmode
, eq_value
, mode
);
3251 else if (GET_MODE_SIZE (outmode
) > GET_MODE_SIZE (mode
))
3252 eq_value
= simplify_gen_unary (ZERO_EXTEND
, outmode
, eq_value
, mode
);
3253 emit_libcall_block_1 (insns
, target
, value
, eq_value
,
3254 trapv_unoptab_p (unoptab
));
3259 /* It can't be done in this mode. Can we do it in a wider mode? */
3261 if (CLASS_HAS_WIDER_MODES_P (mclass
))
3263 for (wider_mode
= GET_MODE_WIDER_MODE (mode
);
3264 wider_mode
!= VOIDmode
;
3265 wider_mode
= GET_MODE_WIDER_MODE (wider_mode
))
3267 if (optab_handler (unoptab
, wider_mode
) != CODE_FOR_nothing
3268 || optab_libfunc (unoptab
, wider_mode
))
3271 rtx last
= get_last_insn ();
3273 /* For certain operations, we need not actually extend
3274 the narrow operand, as long as we will truncate the
3275 results to the same narrowness. */
3276 xop0
= widen_operand (xop0
, wider_mode
, mode
, unsignedp
,
3277 (unoptab
== neg_optab
3278 || unoptab
== one_cmpl_optab
3279 || unoptab
== bswap_optab
)
3280 && mclass
== MODE_INT
);
3282 temp
= expand_unop (wider_mode
, unoptab
, xop0
, NULL_RTX
,
3285 /* If we are generating clz using wider mode, adjust the
3286 result. Similarly for clrsb. */
3287 if ((unoptab
== clz_optab
|| unoptab
== clrsb_optab
)
3289 temp
= expand_binop (wider_mode
, sub_optab
, temp
,
3290 GEN_INT (GET_MODE_PRECISION (wider_mode
)
3291 - GET_MODE_PRECISION (mode
)),
3292 target
, true, OPTAB_DIRECT
);
3294 /* Likewise for bswap. */
3295 if (unoptab
== bswap_optab
&& temp
!= 0)
3297 gcc_assert (GET_MODE_PRECISION (wider_mode
)
3298 == GET_MODE_BITSIZE (wider_mode
)
3299 && GET_MODE_PRECISION (mode
)
3300 == GET_MODE_BITSIZE (mode
));
3302 temp
= expand_shift (RSHIFT_EXPR
, wider_mode
, temp
,
3303 GET_MODE_BITSIZE (wider_mode
)
3304 - GET_MODE_BITSIZE (mode
),
3310 if (mclass
!= MODE_INT
)
3313 target
= gen_reg_rtx (mode
);
3314 convert_move (target
, temp
, 0);
3318 return gen_lowpart (mode
, temp
);
3321 delete_insns_since (last
);
3326 /* One final attempt at implementing negation via subtraction,
3327 this time allowing widening of the operand. */
3328 if (optab_to_code (unoptab
) == NEG
&& !HONOR_SIGNED_ZEROS (mode
))
3331 temp
= expand_binop (mode
,
3332 unoptab
== negv_optab
? subv_optab
: sub_optab
,
3333 CONST0_RTX (mode
), op0
,
3334 target
, unsignedp
, OPTAB_LIB_WIDEN
);
3342 /* Emit code to compute the absolute value of OP0, with result to
3343 TARGET if convenient. (TARGET may be 0.) The return value says
3344 where the result actually is to be found.
3346 MODE is the mode of the operand; the mode of the result is
3347 different but can be deduced from MODE.
3352 expand_abs_nojump (enum machine_mode mode
, rtx op0
, rtx target
,
3353 int result_unsignedp
)
3358 result_unsignedp
= 1;
3360 /* First try to do it with a special abs instruction. */
3361 temp
= expand_unop (mode
, result_unsignedp
? abs_optab
: absv_optab
,
3366 /* For floating point modes, try clearing the sign bit. */
3367 if (SCALAR_FLOAT_MODE_P (mode
))
3369 temp
= expand_absneg_bit (ABS
, mode
, op0
, target
);
3374 /* If we have a MAX insn, we can do this as MAX (x, -x). */
3375 if (optab_handler (smax_optab
, mode
) != CODE_FOR_nothing
3376 && !HONOR_SIGNED_ZEROS (mode
))
3378 rtx last
= get_last_insn ();
3380 temp
= expand_unop (mode
, neg_optab
, op0
, NULL_RTX
, 0);
3382 temp
= expand_binop (mode
, smax_optab
, op0
, temp
, target
, 0,
3388 delete_insns_since (last
);
3391 /* If this machine has expensive jumps, we can do integer absolute
3392 value of X as (((signed) x >> (W-1)) ^ x) - ((signed) x >> (W-1)),
3393 where W is the width of MODE. */
3395 if (GET_MODE_CLASS (mode
) == MODE_INT
3396 && BRANCH_COST (optimize_insn_for_speed_p (),
3399 rtx extended
= expand_shift (RSHIFT_EXPR
, mode
, op0
,
3400 GET_MODE_PRECISION (mode
) - 1,
3403 temp
= expand_binop (mode
, xor_optab
, extended
, op0
, target
, 0,
3406 temp
= expand_binop (mode
, result_unsignedp
? sub_optab
: subv_optab
,
3407 temp
, extended
, target
, 0, OPTAB_LIB_WIDEN
);
3417 expand_abs (enum machine_mode mode
, rtx op0
, rtx target
,
3418 int result_unsignedp
, int safe
)
3423 result_unsignedp
= 1;
3425 temp
= expand_abs_nojump (mode
, op0
, target
, result_unsignedp
);
3429 /* If that does not win, use conditional jump and negate. */
3431 /* It is safe to use the target if it is the same
3432 as the source if this is also a pseudo register */
3433 if (op0
== target
&& REG_P (op0
)
3434 && REGNO (op0
) >= FIRST_PSEUDO_REGISTER
)
3437 op1
= gen_label_rtx ();
3438 if (target
== 0 || ! safe
3439 || GET_MODE (target
) != mode
3440 || (MEM_P (target
) && MEM_VOLATILE_P (target
))
3442 && REGNO (target
) < FIRST_PSEUDO_REGISTER
))
3443 target
= gen_reg_rtx (mode
);
3445 emit_move_insn (target
, op0
);
3448 do_compare_rtx_and_jump (target
, CONST0_RTX (mode
), GE
, 0, mode
,
3449 NULL_RTX
, NULL_RTX
, op1
, -1);
3451 op0
= expand_unop (mode
, result_unsignedp
? neg_optab
: negv_optab
,
3454 emit_move_insn (target
, op0
);
3460 /* Emit code to compute the one's complement absolute value of OP0
3461 (if (OP0 < 0) OP0 = ~OP0), with result to TARGET if convenient.
3462 (TARGET may be NULL_RTX.) The return value says where the result
3463 actually is to be found.
3465 MODE is the mode of the operand; the mode of the result is
3466 different but can be deduced from MODE. */
3469 expand_one_cmpl_abs_nojump (enum machine_mode mode
, rtx op0
, rtx target
)
3473 /* Not applicable for floating point modes. */
3474 if (FLOAT_MODE_P (mode
))
3477 /* If we have a MAX insn, we can do this as MAX (x, ~x). */
3478 if (optab_handler (smax_optab
, mode
) != CODE_FOR_nothing
)
3480 rtx last
= get_last_insn ();
3482 temp
= expand_unop (mode
, one_cmpl_optab
, op0
, NULL_RTX
, 0);
3484 temp
= expand_binop (mode
, smax_optab
, op0
, temp
, target
, 0,
3490 delete_insns_since (last
);
3493 /* If this machine has expensive jumps, we can do one's complement
3494 absolute value of X as (((signed) x >> (W-1)) ^ x). */
3496 if (GET_MODE_CLASS (mode
) == MODE_INT
3497 && BRANCH_COST (optimize_insn_for_speed_p (),
3500 rtx extended
= expand_shift (RSHIFT_EXPR
, mode
, op0
,
3501 GET_MODE_PRECISION (mode
) - 1,
3504 temp
= expand_binop (mode
, xor_optab
, extended
, op0
, target
, 0,
3514 /* A subroutine of expand_copysign, perform the copysign operation using the
3515 abs and neg primitives advertised to exist on the target. The assumption
3516 is that we have a split register file, and leaving op0 in fp registers,
3517 and not playing with subregs so much, will help the register allocator. */
3520 expand_copysign_absneg (enum machine_mode mode
, rtx op0
, rtx op1
, rtx target
,
3521 int bitpos
, bool op0_is_abs
)
3523 enum machine_mode imode
;
3524 enum insn_code icode
;
3530 /* Check if the back end provides an insn that handles signbit for the
3532 icode
= optab_handler (signbit_optab
, mode
);
3533 if (icode
!= CODE_FOR_nothing
)
3535 imode
= insn_data
[(int) icode
].operand
[0].mode
;
3536 sign
= gen_reg_rtx (imode
);
3537 emit_unop_insn (icode
, sign
, op1
, UNKNOWN
);
3543 if (GET_MODE_SIZE (mode
) <= UNITS_PER_WORD
)
3545 imode
= int_mode_for_mode (mode
);
3546 if (imode
== BLKmode
)
3548 op1
= gen_lowpart (imode
, op1
);
3555 if (FLOAT_WORDS_BIG_ENDIAN
)
3556 word
= (GET_MODE_BITSIZE (mode
) - bitpos
) / BITS_PER_WORD
;
3558 word
= bitpos
/ BITS_PER_WORD
;
3559 bitpos
= bitpos
% BITS_PER_WORD
;
3560 op1
= operand_subword_force (op1
, word
, mode
);
3563 mask
= double_int_zero
.set_bit (bitpos
);
3565 sign
= expand_binop (imode
, and_optab
, op1
,
3566 immed_double_int_const (mask
, imode
),
3567 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
3572 op0
= expand_unop (mode
, abs_optab
, op0
, target
, 0);
3579 if (target
== NULL_RTX
)
3580 target
= copy_to_reg (op0
);
3582 emit_move_insn (target
, op0
);
3585 label
= gen_label_rtx ();
3586 emit_cmp_and_jump_insns (sign
, const0_rtx
, EQ
, NULL_RTX
, imode
, 1, label
);
3588 if (CONST_DOUBLE_AS_FLOAT_P (op0
))
3589 op0
= simplify_unary_operation (NEG
, mode
, op0
, mode
);
3591 op0
= expand_unop (mode
, neg_optab
, op0
, target
, 0);
3593 emit_move_insn (target
, op0
);
3601 /* A subroutine of expand_copysign, perform the entire copysign operation
3602 with integer bitmasks. BITPOS is the position of the sign bit; OP0_IS_ABS
3603 is true if op0 is known to have its sign bit clear. */
3606 expand_copysign_bit (enum machine_mode mode
, rtx op0
, rtx op1
, rtx target
,
3607 int bitpos
, bool op0_is_abs
)
3609 enum machine_mode imode
;
3611 int word
, nwords
, i
;
3614 if (GET_MODE_SIZE (mode
) <= UNITS_PER_WORD
)
3616 imode
= int_mode_for_mode (mode
);
3617 if (imode
== BLKmode
)
3626 if (FLOAT_WORDS_BIG_ENDIAN
)
3627 word
= (GET_MODE_BITSIZE (mode
) - bitpos
) / BITS_PER_WORD
;
3629 word
= bitpos
/ BITS_PER_WORD
;
3630 bitpos
= bitpos
% BITS_PER_WORD
;
3631 nwords
= (GET_MODE_BITSIZE (mode
) + BITS_PER_WORD
- 1) / BITS_PER_WORD
;
3634 mask
= double_int_zero
.set_bit (bitpos
);
3639 || (nwords
> 1 && !valid_multiword_target_p (target
)))
3640 target
= gen_reg_rtx (mode
);
3646 for (i
= 0; i
< nwords
; ++i
)
3648 rtx targ_piece
= operand_subword (target
, i
, 1, mode
);
3649 rtx op0_piece
= operand_subword_force (op0
, i
, mode
);
3655 = expand_binop (imode
, and_optab
, op0_piece
,
3656 immed_double_int_const (~mask
, imode
),
3657 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
3659 op1
= expand_binop (imode
, and_optab
,
3660 operand_subword_force (op1
, i
, mode
),
3661 immed_double_int_const (mask
, imode
),
3662 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
3664 temp
= expand_binop (imode
, ior_optab
, op0_piece
, op1
,
3665 targ_piece
, 1, OPTAB_LIB_WIDEN
);
3666 if (temp
!= targ_piece
)
3667 emit_move_insn (targ_piece
, temp
);
3670 emit_move_insn (targ_piece
, op0_piece
);
3673 insns
= get_insns ();
3680 op1
= expand_binop (imode
, and_optab
, gen_lowpart (imode
, op1
),
3681 immed_double_int_const (mask
, imode
),
3682 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
3684 op0
= gen_lowpart (imode
, op0
);
3686 op0
= expand_binop (imode
, and_optab
, op0
,
3687 immed_double_int_const (~mask
, imode
),
3688 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
3690 temp
= expand_binop (imode
, ior_optab
, op0
, op1
,
3691 gen_lowpart (imode
, target
), 1, OPTAB_LIB_WIDEN
);
3692 target
= lowpart_subreg_maybe_copy (mode
, temp
, imode
);
3698 /* Expand the C99 copysign operation. OP0 and OP1 must be the same
3699 scalar floating point mode. Return NULL if we do not know how to
3700 expand the operation inline. */
3703 expand_copysign (rtx op0
, rtx op1
, rtx target
)
3705 enum machine_mode mode
= GET_MODE (op0
);
3706 const struct real_format
*fmt
;
3710 gcc_assert (SCALAR_FLOAT_MODE_P (mode
));
3711 gcc_assert (GET_MODE (op1
) == mode
);
3713 /* First try to do it with a special instruction. */
3714 temp
= expand_binop (mode
, copysign_optab
, op0
, op1
,
3715 target
, 0, OPTAB_DIRECT
);
3719 fmt
= REAL_MODE_FORMAT (mode
);
3720 if (fmt
== NULL
|| !fmt
->has_signed_zero
)
3724 if (CONST_DOUBLE_AS_FLOAT_P (op0
))
3726 if (real_isneg (CONST_DOUBLE_REAL_VALUE (op0
)))
3727 op0
= simplify_unary_operation (ABS
, mode
, op0
, mode
);
3731 if (fmt
->signbit_ro
>= 0
3732 && (CONST_DOUBLE_AS_FLOAT_P (op0
)
3733 || (optab_handler (neg_optab
, mode
) != CODE_FOR_nothing
3734 && optab_handler (abs_optab
, mode
) != CODE_FOR_nothing
)))
3736 temp
= expand_copysign_absneg (mode
, op0
, op1
, target
,
3737 fmt
->signbit_ro
, op0_is_abs
);
3742 if (fmt
->signbit_rw
< 0)
3744 return expand_copysign_bit (mode
, op0
, op1
, target
,
3745 fmt
->signbit_rw
, op0_is_abs
);
3748 /* Generate an instruction whose insn-code is INSN_CODE,
3749 with two operands: an output TARGET and an input OP0.
3750 TARGET *must* be nonzero, and the output is always stored there.
3751 CODE is an rtx code such that (CODE OP0) is an rtx that describes
3752 the value that is stored into TARGET.
3754 Return false if expansion failed. */
3757 maybe_emit_unop_insn (enum insn_code icode
, rtx target
, rtx op0
,
3760 struct expand_operand ops
[2];
3763 create_output_operand (&ops
[0], target
, GET_MODE (target
));
3764 create_input_operand (&ops
[1], op0
, GET_MODE (op0
));
3765 pat
= maybe_gen_insn (icode
, 2, ops
);
3769 if (INSN_P (pat
) && NEXT_INSN (pat
) != NULL_RTX
&& code
!= UNKNOWN
)
3770 add_equal_note (pat
, ops
[0].value
, code
, ops
[1].value
, NULL_RTX
);
3774 if (ops
[0].value
!= target
)
3775 emit_move_insn (target
, ops
[0].value
);
3778 /* Generate an instruction whose insn-code is INSN_CODE,
3779 with two operands: an output TARGET and an input OP0.
3780 TARGET *must* be nonzero, and the output is always stored there.
3781 CODE is an rtx code such that (CODE OP0) is an rtx that describes
3782 the value that is stored into TARGET. */
3785 emit_unop_insn (enum insn_code icode
, rtx target
, rtx op0
, enum rtx_code code
)
3787 bool ok
= maybe_emit_unop_insn (icode
, target
, op0
, code
);
3791 struct no_conflict_data
3793 rtx target
, first
, insn
;
3797 /* Called via note_stores by emit_libcall_block. Set P->must_stay if
3798 the currently examined clobber / store has to stay in the list of
3799 insns that constitute the actual libcall block. */
3801 no_conflict_move_test (rtx dest
, const_rtx set
, void *p0
)
3803 struct no_conflict_data
*p
= (struct no_conflict_data
*) p0
;
3805 /* If this inns directly contributes to setting the target, it must stay. */
3806 if (reg_overlap_mentioned_p (p
->target
, dest
))
3807 p
->must_stay
= true;
3808 /* If we haven't committed to keeping any other insns in the list yet,
3809 there is nothing more to check. */
3810 else if (p
->insn
== p
->first
)
3812 /* If this insn sets / clobbers a register that feeds one of the insns
3813 already in the list, this insn has to stay too. */
3814 else if (reg_overlap_mentioned_p (dest
, PATTERN (p
->first
))
3815 || (CALL_P (p
->first
) && (find_reg_fusage (p
->first
, USE
, dest
)))
3816 || reg_used_between_p (dest
, p
->first
, p
->insn
)
3817 /* Likewise if this insn depends on a register set by a previous
3818 insn in the list, or if it sets a result (presumably a hard
3819 register) that is set or clobbered by a previous insn.
3820 N.B. the modified_*_p (SET_DEST...) tests applied to a MEM
3821 SET_DEST perform the former check on the address, and the latter
3822 check on the MEM. */
3823 || (GET_CODE (set
) == SET
3824 && (modified_in_p (SET_SRC (set
), p
->first
)
3825 || modified_in_p (SET_DEST (set
), p
->first
)
3826 || modified_between_p (SET_SRC (set
), p
->first
, p
->insn
)
3827 || modified_between_p (SET_DEST (set
), p
->first
, p
->insn
))))
3828 p
->must_stay
= true;
3832 /* Emit code to make a call to a constant function or a library call.
3834 INSNS is a list containing all insns emitted in the call.
3835 These insns leave the result in RESULT. Our block is to copy RESULT
3836 to TARGET, which is logically equivalent to EQUIV.
3838 We first emit any insns that set a pseudo on the assumption that these are
3839 loading constants into registers; doing so allows them to be safely cse'ed
3840 between blocks. Then we emit all the other insns in the block, followed by
3841 an insn to move RESULT to TARGET. This last insn will have a REQ_EQUAL
3842 note with an operand of EQUIV. */
3845 emit_libcall_block_1 (rtx insns
, rtx target
, rtx result
, rtx equiv
,
3846 bool equiv_may_trap
)
3848 rtx final_dest
= target
;
3849 rtx next
, last
, insn
;
3851 /* If this is a reg with REG_USERVAR_P set, then it could possibly turn
3852 into a MEM later. Protect the libcall block from this change. */
3853 if (! REG_P (target
) || REG_USERVAR_P (target
))
3854 target
= gen_reg_rtx (GET_MODE (target
));
3856 /* If we're using non-call exceptions, a libcall corresponding to an
3857 operation that may trap may also trap. */
3858 /* ??? See the comment in front of make_reg_eh_region_note. */
3859 if (cfun
->can_throw_non_call_exceptions
3860 && (equiv_may_trap
|| may_trap_p (equiv
)))
3862 for (insn
= insns
; insn
; insn
= NEXT_INSN (insn
))
3865 rtx note
= find_reg_note (insn
, REG_EH_REGION
, NULL_RTX
);
3868 int lp_nr
= INTVAL (XEXP (note
, 0));
3869 if (lp_nr
== 0 || lp_nr
== INT_MIN
)
3870 remove_note (insn
, note
);
3876 /* Look for any CALL_INSNs in this sequence, and attach a REG_EH_REGION
3877 reg note to indicate that this call cannot throw or execute a nonlocal
3878 goto (unless there is already a REG_EH_REGION note, in which case
3880 for (insn
= insns
; insn
; insn
= NEXT_INSN (insn
))
3882 make_reg_eh_region_note_nothrow_nononlocal (insn
);
3885 /* First emit all insns that set pseudos. Remove them from the list as
3886 we go. Avoid insns that set pseudos which were referenced in previous
3887 insns. These can be generated by move_by_pieces, for example,
3888 to update an address. Similarly, avoid insns that reference things
3889 set in previous insns. */
3891 for (insn
= insns
; insn
; insn
= next
)
3893 rtx set
= single_set (insn
);
3895 next
= NEXT_INSN (insn
);
3897 if (set
!= 0 && REG_P (SET_DEST (set
))
3898 && REGNO (SET_DEST (set
)) >= FIRST_PSEUDO_REGISTER
)
3900 struct no_conflict_data data
;
3902 data
.target
= const0_rtx
;
3906 note_stores (PATTERN (insn
), no_conflict_move_test
, &data
);
3907 if (! data
.must_stay
)
3909 if (PREV_INSN (insn
))
3910 NEXT_INSN (PREV_INSN (insn
)) = next
;
3915 PREV_INSN (next
) = PREV_INSN (insn
);
3921 /* Some ports use a loop to copy large arguments onto the stack.
3922 Don't move anything outside such a loop. */
3927 /* Write the remaining insns followed by the final copy. */
3928 for (insn
= insns
; insn
; insn
= next
)
3930 next
= NEXT_INSN (insn
);
3935 last
= emit_move_insn (target
, result
);
3936 set_dst_reg_note (last
, REG_EQUAL
, copy_rtx (equiv
), target
);
3938 if (final_dest
!= target
)
3939 emit_move_insn (final_dest
, target
);
3943 emit_libcall_block (rtx insns
, rtx target
, rtx result
, rtx equiv
)
3945 emit_libcall_block_1 (insns
, target
, result
, equiv
, false);
3948 /* Nonzero if we can perform a comparison of mode MODE straightforwardly.
3949 PURPOSE describes how this comparison will be used. CODE is the rtx
3950 comparison code we will be using.
3952 ??? Actually, CODE is slightly weaker than that. A target is still
3953 required to implement all of the normal bcc operations, but not
3954 required to implement all (or any) of the unordered bcc operations. */
3957 can_compare_p (enum rtx_code code
, enum machine_mode mode
,
3958 enum can_compare_purpose purpose
)
3961 test
= gen_rtx_fmt_ee (code
, mode
, const0_rtx
, const0_rtx
);
3964 enum insn_code icode
;
3966 if (purpose
== ccp_jump
3967 && (icode
= optab_handler (cbranch_optab
, mode
)) != CODE_FOR_nothing
3968 && insn_operand_matches (icode
, 0, test
))
3970 if (purpose
== ccp_store_flag
3971 && (icode
= optab_handler (cstore_optab
, mode
)) != CODE_FOR_nothing
3972 && insn_operand_matches (icode
, 1, test
))
3974 if (purpose
== ccp_cmov
3975 && optab_handler (cmov_optab
, mode
) != CODE_FOR_nothing
)
3978 mode
= GET_MODE_WIDER_MODE (mode
);
3979 PUT_MODE (test
, mode
);
3981 while (mode
!= VOIDmode
);
3986 /* This function is called when we are going to emit a compare instruction that
3987 compares the values found in *PX and *PY, using the rtl operator COMPARISON.
3989 *PMODE is the mode of the inputs (in case they are const_int).
3990 *PUNSIGNEDP nonzero says that the operands are unsigned;
3991 this matters if they need to be widened (as given by METHODS).
3993 If they have mode BLKmode, then SIZE specifies the size of both operands.
3995 This function performs all the setup necessary so that the caller only has
3996 to emit a single comparison insn. This setup can involve doing a BLKmode
3997 comparison or emitting a library call to perform the comparison if no insn
3998 is available to handle it.
3999 The values which are passed in through pointers can be modified; the caller
4000 should perform the comparison on the modified values. Constant
4001 comparisons must have already been folded. */
4004 prepare_cmp_insn (rtx x
, rtx y
, enum rtx_code comparison
, rtx size
,
4005 int unsignedp
, enum optab_methods methods
,
4006 rtx
*ptest
, enum machine_mode
*pmode
)
4008 enum machine_mode mode
= *pmode
;
4010 enum machine_mode cmp_mode
;
4011 enum mode_class mclass
;
4013 /* The other methods are not needed. */
4014 gcc_assert (methods
== OPTAB_DIRECT
|| methods
== OPTAB_WIDEN
4015 || methods
== OPTAB_LIB_WIDEN
);
4017 /* If we are optimizing, force expensive constants into a register. */
4018 if (CONSTANT_P (x
) && optimize
4019 && (rtx_cost (x
, COMPARE
, 0, optimize_insn_for_speed_p ())
4020 > COSTS_N_INSNS (1)))
4021 x
= force_reg (mode
, x
);
4023 if (CONSTANT_P (y
) && optimize
4024 && (rtx_cost (y
, COMPARE
, 1, optimize_insn_for_speed_p ())
4025 > COSTS_N_INSNS (1)))
4026 y
= force_reg (mode
, y
);
4029 /* Make sure if we have a canonical comparison. The RTL
4030 documentation states that canonical comparisons are required only
4031 for targets which have cc0. */
4032 gcc_assert (!CONSTANT_P (x
) || CONSTANT_P (y
));
4035 /* Don't let both operands fail to indicate the mode. */
4036 if (GET_MODE (x
) == VOIDmode
&& GET_MODE (y
) == VOIDmode
)
4037 x
= force_reg (mode
, x
);
4038 if (mode
== VOIDmode
)
4039 mode
= GET_MODE (x
) != VOIDmode
? GET_MODE (x
) : GET_MODE (y
);
4041 /* Handle all BLKmode compares. */
4043 if (mode
== BLKmode
)
4045 enum machine_mode result_mode
;
4046 enum insn_code cmp_code
;
4051 = GEN_INT (MIN (MEM_ALIGN (x
), MEM_ALIGN (y
)) / BITS_PER_UNIT
);
4055 /* Try to use a memory block compare insn - either cmpstr
4056 or cmpmem will do. */
4057 for (cmp_mode
= GET_CLASS_NARROWEST_MODE (MODE_INT
);
4058 cmp_mode
!= VOIDmode
;
4059 cmp_mode
= GET_MODE_WIDER_MODE (cmp_mode
))
4061 cmp_code
= direct_optab_handler (cmpmem_optab
, cmp_mode
);
4062 if (cmp_code
== CODE_FOR_nothing
)
4063 cmp_code
= direct_optab_handler (cmpstr_optab
, cmp_mode
);
4064 if (cmp_code
== CODE_FOR_nothing
)
4065 cmp_code
= direct_optab_handler (cmpstrn_optab
, cmp_mode
);
4066 if (cmp_code
== CODE_FOR_nothing
)
4069 /* Must make sure the size fits the insn's mode. */
4070 if ((CONST_INT_P (size
)
4071 && INTVAL (size
) >= (1 << GET_MODE_BITSIZE (cmp_mode
)))
4072 || (GET_MODE_BITSIZE (GET_MODE (size
))
4073 > GET_MODE_BITSIZE (cmp_mode
)))
4076 result_mode
= insn_data
[cmp_code
].operand
[0].mode
;
4077 result
= gen_reg_rtx (result_mode
);
4078 size
= convert_to_mode (cmp_mode
, size
, 1);
4079 emit_insn (GEN_FCN (cmp_code
) (result
, x
, y
, size
, opalign
));
4081 *ptest
= gen_rtx_fmt_ee (comparison
, VOIDmode
, result
, const0_rtx
);
4082 *pmode
= result_mode
;
4086 if (methods
!= OPTAB_LIB
&& methods
!= OPTAB_LIB_WIDEN
)
4089 /* Otherwise call a library function, memcmp. */
4090 libfunc
= memcmp_libfunc
;
4091 length_type
= sizetype
;
4092 result_mode
= TYPE_MODE (integer_type_node
);
4093 cmp_mode
= TYPE_MODE (length_type
);
4094 size
= convert_to_mode (TYPE_MODE (length_type
), size
,
4095 TYPE_UNSIGNED (length_type
));
4097 result
= emit_library_call_value (libfunc
, 0, LCT_PURE
,
4105 methods
= OPTAB_LIB_WIDEN
;
4109 /* Don't allow operands to the compare to trap, as that can put the
4110 compare and branch in different basic blocks. */
4111 if (cfun
->can_throw_non_call_exceptions
)
4114 x
= force_reg (mode
, x
);
4116 y
= force_reg (mode
, y
);
4119 if (GET_MODE_CLASS (mode
) == MODE_CC
)
4121 gcc_assert (can_compare_p (comparison
, CCmode
, ccp_jump
));
4122 *ptest
= gen_rtx_fmt_ee (comparison
, VOIDmode
, x
, y
);
4126 mclass
= GET_MODE_CLASS (mode
);
4127 test
= gen_rtx_fmt_ee (comparison
, VOIDmode
, x
, y
);
4131 enum insn_code icode
;
4132 icode
= optab_handler (cbranch_optab
, cmp_mode
);
4133 if (icode
!= CODE_FOR_nothing
4134 && insn_operand_matches (icode
, 0, test
))
4136 rtx last
= get_last_insn ();
4137 rtx op0
= prepare_operand (icode
, x
, 1, mode
, cmp_mode
, unsignedp
);
4138 rtx op1
= prepare_operand (icode
, y
, 2, mode
, cmp_mode
, unsignedp
);
4140 && insn_operand_matches (icode
, 1, op0
)
4141 && insn_operand_matches (icode
, 2, op1
))
4143 XEXP (test
, 0) = op0
;
4144 XEXP (test
, 1) = op1
;
4149 delete_insns_since (last
);
4152 if (methods
== OPTAB_DIRECT
|| !CLASS_HAS_WIDER_MODES_P (mclass
))
4154 cmp_mode
= GET_MODE_WIDER_MODE (cmp_mode
);
4156 while (cmp_mode
!= VOIDmode
);
4158 if (methods
!= OPTAB_LIB_WIDEN
)
4161 if (!SCALAR_FLOAT_MODE_P (mode
))
4164 enum machine_mode ret_mode
;
4166 /* Handle a libcall just for the mode we are using. */
4167 libfunc
= optab_libfunc (cmp_optab
, mode
);
4168 gcc_assert (libfunc
);
4170 /* If we want unsigned, and this mode has a distinct unsigned
4171 comparison routine, use that. */
4174 rtx ulibfunc
= optab_libfunc (ucmp_optab
, mode
);
4179 ret_mode
= targetm
.libgcc_cmp_return_mode ();
4180 result
= emit_library_call_value (libfunc
, NULL_RTX
, LCT_CONST
,
4181 ret_mode
, 2, x
, mode
, y
, mode
);
4183 /* There are two kinds of comparison routines. Biased routines
4184 return 0/1/2, and unbiased routines return -1/0/1. Other parts
4185 of gcc expect that the comparison operation is equivalent
4186 to the modified comparison. For signed comparisons compare the
4187 result against 1 in the biased case, and zero in the unbiased
4188 case. For unsigned comparisons always compare against 1 after
4189 biasing the unbiased result by adding 1. This gives us a way to
4191 The comparisons in the fixed-point helper library are always
4196 if (!TARGET_LIB_INT_CMP_BIASED
&& !ALL_FIXED_POINT_MODE_P (mode
))
4199 x
= plus_constant (ret_mode
, result
, 1);
4205 prepare_cmp_insn (x
, y
, comparison
, NULL_RTX
, unsignedp
, methods
,
4209 prepare_float_lib_cmp (x
, y
, comparison
, ptest
, pmode
);
4217 /* Before emitting an insn with code ICODE, make sure that X, which is going
4218 to be used for operand OPNUM of the insn, is converted from mode MODE to
4219 WIDER_MODE (UNSIGNEDP determines whether it is an unsigned conversion), and
4220 that it is accepted by the operand predicate. Return the new value. */
4223 prepare_operand (enum insn_code icode
, rtx x
, int opnum
, enum machine_mode mode
,
4224 enum machine_mode wider_mode
, int unsignedp
)
4226 if (mode
!= wider_mode
)
4227 x
= convert_modes (wider_mode
, mode
, x
, unsignedp
);
4229 if (!insn_operand_matches (icode
, opnum
, x
))
4231 if (reload_completed
)
4233 x
= copy_to_mode_reg (insn_data
[(int) icode
].operand
[opnum
].mode
, x
);
4239 /* Subroutine of emit_cmp_and_jump_insns; this function is called when we know
4240 we can do the branch. */
4243 emit_cmp_and_jump_insn_1 (rtx test
, enum machine_mode mode
, rtx label
, int prob
)
4245 enum machine_mode optab_mode
;
4246 enum mode_class mclass
;
4247 enum insn_code icode
;
4250 mclass
= GET_MODE_CLASS (mode
);
4251 optab_mode
= (mclass
== MODE_CC
) ? CCmode
: mode
;
4252 icode
= optab_handler (cbranch_optab
, optab_mode
);
4254 gcc_assert (icode
!= CODE_FOR_nothing
);
4255 gcc_assert (insn_operand_matches (icode
, 0, test
));
4256 insn
= emit_jump_insn (GEN_FCN (icode
) (test
, XEXP (test
, 0),
4257 XEXP (test
, 1), label
));
4259 && profile_status
!= PROFILE_ABSENT
4262 && any_condjump_p (insn
)
4263 && !find_reg_note (insn
, REG_BR_PROB
, 0))
4264 add_reg_note (insn
, REG_BR_PROB
, GEN_INT (prob
));
4267 /* Generate code to compare X with Y so that the condition codes are
4268 set and to jump to LABEL if the condition is true. If X is a
4269 constant and Y is not a constant, then the comparison is swapped to
4270 ensure that the comparison RTL has the canonical form.
4272 UNSIGNEDP nonzero says that X and Y are unsigned; this matters if they
4273 need to be widened. UNSIGNEDP is also used to select the proper
4274 branch condition code.
4276 If X and Y have mode BLKmode, then SIZE specifies the size of both X and Y.
4278 MODE is the mode of the inputs (in case they are const_int).
4280 COMPARISON is the rtl operator to compare with (EQ, NE, GT, etc.).
4281 It will be potentially converted into an unsigned variant based on
4282 UNSIGNEDP to select a proper jump instruction.
4284 PROB is the probability of jumping to LABEL. */
4287 emit_cmp_and_jump_insns (rtx x
, rtx y
, enum rtx_code comparison
, rtx size
,
4288 enum machine_mode mode
, int unsignedp
, rtx label
,
4291 rtx op0
= x
, op1
= y
;
4294 /* Swap operands and condition to ensure canonical RTL. */
4295 if (swap_commutative_operands_p (x
, y
)
4296 && can_compare_p (swap_condition (comparison
), mode
, ccp_jump
))
4299 comparison
= swap_condition (comparison
);
4302 /* If OP0 is still a constant, then both X and Y must be constants
4303 or the opposite comparison is not supported. Force X into a register
4304 to create canonical RTL. */
4305 if (CONSTANT_P (op0
))
4306 op0
= force_reg (mode
, op0
);
4309 comparison
= unsigned_condition (comparison
);
4311 prepare_cmp_insn (op0
, op1
, comparison
, size
, unsignedp
, OPTAB_LIB_WIDEN
,
4313 emit_cmp_and_jump_insn_1 (test
, mode
, label
, prob
);
4317 /* Emit a library call comparison between floating point X and Y.
4318 COMPARISON is the rtl operator to compare with (EQ, NE, GT, etc.). */
4321 prepare_float_lib_cmp (rtx x
, rtx y
, enum rtx_code comparison
,
4322 rtx
*ptest
, enum machine_mode
*pmode
)
4324 enum rtx_code swapped
= swap_condition (comparison
);
4325 enum rtx_code reversed
= reverse_condition_maybe_unordered (comparison
);
4326 enum machine_mode orig_mode
= GET_MODE (x
);
4327 enum machine_mode mode
, cmp_mode
;
4328 rtx true_rtx
, false_rtx
;
4329 rtx value
, target
, insns
, equiv
;
4331 bool reversed_p
= false;
4332 cmp_mode
= targetm
.libgcc_cmp_return_mode ();
4334 for (mode
= orig_mode
;
4336 mode
= GET_MODE_WIDER_MODE (mode
))
4338 if (code_to_optab (comparison
)
4339 && (libfunc
= optab_libfunc (code_to_optab (comparison
), mode
)))
4342 if (code_to_optab (swapped
)
4343 && (libfunc
= optab_libfunc (code_to_optab (swapped
), mode
)))
4346 tmp
= x
; x
= y
; y
= tmp
;
4347 comparison
= swapped
;
4351 if (code_to_optab (reversed
)
4352 && (libfunc
= optab_libfunc (code_to_optab (reversed
), mode
)))
4354 comparison
= reversed
;
4360 gcc_assert (mode
!= VOIDmode
);
4362 if (mode
!= orig_mode
)
4364 x
= convert_to_mode (mode
, x
, 0);
4365 y
= convert_to_mode (mode
, y
, 0);
4368 /* Attach a REG_EQUAL note describing the semantics of the libcall to
4369 the RTL. The allows the RTL optimizers to delete the libcall if the
4370 condition can be determined at compile-time. */
4371 if (comparison
== UNORDERED
4372 || FLOAT_LIB_COMPARE_RETURNS_BOOL (mode
, comparison
))
4374 true_rtx
= const_true_rtx
;
4375 false_rtx
= const0_rtx
;
4382 true_rtx
= const0_rtx
;
4383 false_rtx
= const_true_rtx
;
4387 true_rtx
= const_true_rtx
;
4388 false_rtx
= const0_rtx
;
4392 true_rtx
= const1_rtx
;
4393 false_rtx
= const0_rtx
;
4397 true_rtx
= const0_rtx
;
4398 false_rtx
= constm1_rtx
;
4402 true_rtx
= constm1_rtx
;
4403 false_rtx
= const0_rtx
;
4407 true_rtx
= const0_rtx
;
4408 false_rtx
= const1_rtx
;
4416 if (comparison
== UNORDERED
)
4418 rtx temp
= simplify_gen_relational (NE
, cmp_mode
, mode
, x
, x
);
4419 equiv
= simplify_gen_relational (NE
, cmp_mode
, mode
, y
, y
);
4420 equiv
= simplify_gen_ternary (IF_THEN_ELSE
, cmp_mode
, cmp_mode
,
4421 temp
, const_true_rtx
, equiv
);
4425 equiv
= simplify_gen_relational (comparison
, cmp_mode
, mode
, x
, y
);
4426 if (! FLOAT_LIB_COMPARE_RETURNS_BOOL (mode
, comparison
))
4427 equiv
= simplify_gen_ternary (IF_THEN_ELSE
, cmp_mode
, cmp_mode
,
4428 equiv
, true_rtx
, false_rtx
);
4432 value
= emit_library_call_value (libfunc
, NULL_RTX
, LCT_CONST
,
4433 cmp_mode
, 2, x
, mode
, y
, mode
);
4434 insns
= get_insns ();
4437 target
= gen_reg_rtx (cmp_mode
);
4438 emit_libcall_block (insns
, target
, value
, equiv
);
4440 if (comparison
== UNORDERED
4441 || FLOAT_LIB_COMPARE_RETURNS_BOOL (mode
, comparison
)
4443 *ptest
= gen_rtx_fmt_ee (reversed_p
? EQ
: NE
, VOIDmode
, target
, false_rtx
);
4445 *ptest
= gen_rtx_fmt_ee (comparison
, VOIDmode
, target
, const0_rtx
);
4450 /* Generate code to indirectly jump to a location given in the rtx LOC. */
4453 emit_indirect_jump (rtx loc
)
4455 struct expand_operand ops
[1];
4457 create_address_operand (&ops
[0], loc
);
4458 expand_jump_insn (CODE_FOR_indirect_jump
, 1, ops
);
4462 #ifdef HAVE_conditional_move
4464 /* Emit a conditional move instruction if the machine supports one for that
4465 condition and machine mode.
4467 OP0 and OP1 are the operands that should be compared using CODE. CMODE is
4468 the mode to use should they be constants. If it is VOIDmode, they cannot
4471 OP2 should be stored in TARGET if the comparison is true, otherwise OP3
4472 should be stored there. MODE is the mode to use should they be constants.
4473 If it is VOIDmode, they cannot both be constants.
4475 The result is either TARGET (perhaps modified) or NULL_RTX if the operation
4476 is not supported. */
4479 emit_conditional_move (rtx target
, enum rtx_code code
, rtx op0
, rtx op1
,
4480 enum machine_mode cmode
, rtx op2
, rtx op3
,
4481 enum machine_mode mode
, int unsignedp
)
4483 rtx tem
, comparison
, last
;
4484 enum insn_code icode
;
4485 enum rtx_code reversed
;
4487 /* If one operand is constant, make it the second one. Only do this
4488 if the other operand is not constant as well. */
4490 if (swap_commutative_operands_p (op0
, op1
))
4495 code
= swap_condition (code
);
4498 /* get_condition will prefer to generate LT and GT even if the old
4499 comparison was against zero, so undo that canonicalization here since
4500 comparisons against zero are cheaper. */
4501 if (code
== LT
&& op1
== const1_rtx
)
4502 code
= LE
, op1
= const0_rtx
;
4503 else if (code
== GT
&& op1
== constm1_rtx
)
4504 code
= GE
, op1
= const0_rtx
;
4506 if (cmode
== VOIDmode
)
4507 cmode
= GET_MODE (op0
);
4509 if (swap_commutative_operands_p (op2
, op3
)
4510 && ((reversed
= reversed_comparison_code_parts (code
, op0
, op1
, NULL
))
4519 if (mode
== VOIDmode
)
4520 mode
= GET_MODE (op2
);
4522 icode
= direct_optab_handler (movcc_optab
, mode
);
4524 if (icode
== CODE_FOR_nothing
)
4528 target
= gen_reg_rtx (mode
);
4530 code
= unsignedp
? unsigned_condition (code
) : code
;
4531 comparison
= simplify_gen_relational (code
, VOIDmode
, cmode
, op0
, op1
);
4533 /* We can get const0_rtx or const_true_rtx in some circumstances. Just
4534 return NULL and let the caller figure out how best to deal with this
4536 if (!COMPARISON_P (comparison
))
4539 do_pending_stack_adjust ();
4540 last
= get_last_insn ();
4541 prepare_cmp_insn (XEXP (comparison
, 0), XEXP (comparison
, 1),
4542 GET_CODE (comparison
), NULL_RTX
, unsignedp
, OPTAB_WIDEN
,
4543 &comparison
, &cmode
);
4546 struct expand_operand ops
[4];
4548 create_output_operand (&ops
[0], target
, mode
);
4549 create_fixed_operand (&ops
[1], comparison
);
4550 create_input_operand (&ops
[2], op2
, mode
);
4551 create_input_operand (&ops
[3], op3
, mode
);
4552 if (maybe_expand_insn (icode
, 4, ops
))
4554 if (ops
[0].value
!= target
)
4555 convert_move (target
, ops
[0].value
, false);
4559 delete_insns_since (last
);
4563 /* Return nonzero if a conditional move of mode MODE is supported.
4565 This function is for combine so it can tell whether an insn that looks
4566 like a conditional move is actually supported by the hardware. If we
4567 guess wrong we lose a bit on optimization, but that's it. */
4568 /* ??? sparc64 supports conditionally moving integers values based on fp
4569 comparisons, and vice versa. How do we handle them? */
4572 can_conditionally_move_p (enum machine_mode mode
)
4574 if (direct_optab_handler (movcc_optab
, mode
) != CODE_FOR_nothing
)
4580 #endif /* HAVE_conditional_move */
4582 /* Emit a conditional addition instruction if the machine supports one for that
4583 condition and machine mode.
4585 OP0 and OP1 are the operands that should be compared using CODE. CMODE is
4586 the mode to use should they be constants. If it is VOIDmode, they cannot
4589 OP2 should be stored in TARGET if the comparison is false, otherwise OP2+OP3
4590 should be stored there. MODE is the mode to use should they be constants.
4591 If it is VOIDmode, they cannot both be constants.
4593 The result is either TARGET (perhaps modified) or NULL_RTX if the operation
4594 is not supported. */
4597 emit_conditional_add (rtx target
, enum rtx_code code
, rtx op0
, rtx op1
,
4598 enum machine_mode cmode
, rtx op2
, rtx op3
,
4599 enum machine_mode mode
, int unsignedp
)
4601 rtx tem
, comparison
, last
;
4602 enum insn_code icode
;
4604 /* If one operand is constant, make it the second one. Only do this
4605 if the other operand is not constant as well. */
4607 if (swap_commutative_operands_p (op0
, op1
))
4612 code
= swap_condition (code
);
4615 /* get_condition will prefer to generate LT and GT even if the old
4616 comparison was against zero, so undo that canonicalization here since
4617 comparisons against zero are cheaper. */
4618 if (code
== LT
&& op1
== const1_rtx
)
4619 code
= LE
, op1
= const0_rtx
;
4620 else if (code
== GT
&& op1
== constm1_rtx
)
4621 code
= GE
, op1
= const0_rtx
;
4623 if (cmode
== VOIDmode
)
4624 cmode
= GET_MODE (op0
);
4626 if (mode
== VOIDmode
)
4627 mode
= GET_MODE (op2
);
4629 icode
= optab_handler (addcc_optab
, mode
);
4631 if (icode
== CODE_FOR_nothing
)
4635 target
= gen_reg_rtx (mode
);
4637 code
= unsignedp
? unsigned_condition (code
) : code
;
4638 comparison
= simplify_gen_relational (code
, VOIDmode
, cmode
, op0
, op1
);
4640 /* We can get const0_rtx or const_true_rtx in some circumstances. Just
4641 return NULL and let the caller figure out how best to deal with this
4643 if (!COMPARISON_P (comparison
))
4646 do_pending_stack_adjust ();
4647 last
= get_last_insn ();
4648 prepare_cmp_insn (XEXP (comparison
, 0), XEXP (comparison
, 1),
4649 GET_CODE (comparison
), NULL_RTX
, unsignedp
, OPTAB_WIDEN
,
4650 &comparison
, &cmode
);
4653 struct expand_operand ops
[4];
4655 create_output_operand (&ops
[0], target
, mode
);
4656 create_fixed_operand (&ops
[1], comparison
);
4657 create_input_operand (&ops
[2], op2
, mode
);
4658 create_input_operand (&ops
[3], op3
, mode
);
4659 if (maybe_expand_insn (icode
, 4, ops
))
4661 if (ops
[0].value
!= target
)
4662 convert_move (target
, ops
[0].value
, false);
4666 delete_insns_since (last
);
4670 /* These functions attempt to generate an insn body, rather than
4671 emitting the insn, but if the gen function already emits them, we
4672 make no attempt to turn them back into naked patterns. */
4674 /* Generate and return an insn body to add Y to X. */
4677 gen_add2_insn (rtx x
, rtx y
)
4679 enum insn_code icode
= optab_handler (add_optab
, GET_MODE (x
));
4681 gcc_assert (insn_operand_matches (icode
, 0, x
));
4682 gcc_assert (insn_operand_matches (icode
, 1, x
));
4683 gcc_assert (insn_operand_matches (icode
, 2, y
));
4685 return GEN_FCN (icode
) (x
, x
, y
);
4688 /* Generate and return an insn body to add r1 and c,
4689 storing the result in r0. */
4692 gen_add3_insn (rtx r0
, rtx r1
, rtx c
)
4694 enum insn_code icode
= optab_handler (add_optab
, GET_MODE (r0
));
4696 if (icode
== CODE_FOR_nothing
4697 || !insn_operand_matches (icode
, 0, r0
)
4698 || !insn_operand_matches (icode
, 1, r1
)
4699 || !insn_operand_matches (icode
, 2, c
))
4702 return GEN_FCN (icode
) (r0
, r1
, c
);
4706 have_add2_insn (rtx x
, rtx y
)
4708 enum insn_code icode
;
4710 gcc_assert (GET_MODE (x
) != VOIDmode
);
4712 icode
= optab_handler (add_optab
, GET_MODE (x
));
4714 if (icode
== CODE_FOR_nothing
)
4717 if (!insn_operand_matches (icode
, 0, x
)
4718 || !insn_operand_matches (icode
, 1, x
)
4719 || !insn_operand_matches (icode
, 2, y
))
4725 /* Generate and return an insn body to subtract Y from X. */
4728 gen_sub2_insn (rtx x
, rtx y
)
4730 enum insn_code icode
= optab_handler (sub_optab
, GET_MODE (x
));
4732 gcc_assert (insn_operand_matches (icode
, 0, x
));
4733 gcc_assert (insn_operand_matches (icode
, 1, x
));
4734 gcc_assert (insn_operand_matches (icode
, 2, y
));
4736 return GEN_FCN (icode
) (x
, x
, y
);
4739 /* Generate and return an insn body to subtract r1 and c,
4740 storing the result in r0. */
4743 gen_sub3_insn (rtx r0
, rtx r1
, rtx c
)
4745 enum insn_code icode
= optab_handler (sub_optab
, GET_MODE (r0
));
4747 if (icode
== CODE_FOR_nothing
4748 || !insn_operand_matches (icode
, 0, r0
)
4749 || !insn_operand_matches (icode
, 1, r1
)
4750 || !insn_operand_matches (icode
, 2, c
))
4753 return GEN_FCN (icode
) (r0
, r1
, c
);
4757 have_sub2_insn (rtx x
, rtx y
)
4759 enum insn_code icode
;
4761 gcc_assert (GET_MODE (x
) != VOIDmode
);
4763 icode
= optab_handler (sub_optab
, GET_MODE (x
));
4765 if (icode
== CODE_FOR_nothing
)
4768 if (!insn_operand_matches (icode
, 0, x
)
4769 || !insn_operand_matches (icode
, 1, x
)
4770 || !insn_operand_matches (icode
, 2, y
))
4776 /* Generate the body of an instruction to copy Y into X.
4777 It may be a list of insns, if one insn isn't enough. */
4780 gen_move_insn (rtx x
, rtx y
)
4785 emit_move_insn_1 (x
, y
);
4791 /* Return the insn code used to extend FROM_MODE to TO_MODE.
4792 UNSIGNEDP specifies zero-extension instead of sign-extension. If
4793 no such operation exists, CODE_FOR_nothing will be returned. */
4796 can_extend_p (enum machine_mode to_mode
, enum machine_mode from_mode
,
4800 #ifdef HAVE_ptr_extend
4802 return CODE_FOR_ptr_extend
;
4805 tab
= unsignedp
? zext_optab
: sext_optab
;
4806 return convert_optab_handler (tab
, to_mode
, from_mode
);
4809 /* Generate the body of an insn to extend Y (with mode MFROM)
4810 into X (with mode MTO). Do zero-extension if UNSIGNEDP is nonzero. */
4813 gen_extend_insn (rtx x
, rtx y
, enum machine_mode mto
,
4814 enum machine_mode mfrom
, int unsignedp
)
4816 enum insn_code icode
= can_extend_p (mto
, mfrom
, unsignedp
);
4817 return GEN_FCN (icode
) (x
, y
);
4820 /* can_fix_p and can_float_p say whether the target machine
4821 can directly convert a given fixed point type to
4822 a given floating point type, or vice versa.
4823 The returned value is the CODE_FOR_... value to use,
4824 or CODE_FOR_nothing if these modes cannot be directly converted.
4826 *TRUNCP_PTR is set to 1 if it is necessary to output
4827 an explicit FTRUNC insn before the fix insn; otherwise 0. */
4829 static enum insn_code
4830 can_fix_p (enum machine_mode fixmode
, enum machine_mode fltmode
,
4831 int unsignedp
, int *truncp_ptr
)
4834 enum insn_code icode
;
4836 tab
= unsignedp
? ufixtrunc_optab
: sfixtrunc_optab
;
4837 icode
= convert_optab_handler (tab
, fixmode
, fltmode
);
4838 if (icode
!= CODE_FOR_nothing
)
4844 /* FIXME: This requires a port to define both FIX and FTRUNC pattern
4845 for this to work. We need to rework the fix* and ftrunc* patterns
4846 and documentation. */
4847 tab
= unsignedp
? ufix_optab
: sfix_optab
;
4848 icode
= convert_optab_handler (tab
, fixmode
, fltmode
);
4849 if (icode
!= CODE_FOR_nothing
4850 && optab_handler (ftrunc_optab
, fltmode
) != CODE_FOR_nothing
)
4857 return CODE_FOR_nothing
;
4861 can_float_p (enum machine_mode fltmode
, enum machine_mode fixmode
,
4866 tab
= unsignedp
? ufloat_optab
: sfloat_optab
;
4867 return convert_optab_handler (tab
, fltmode
, fixmode
);
4870 /* Function supportable_convert_operation
4872 Check whether an operation represented by the code CODE is a
4873 convert operation that is supported by the target platform in
4874 vector form (i.e., when operating on arguments of type VECTYPE_IN
4875 producing a result of type VECTYPE_OUT).
4877 Convert operations we currently support directly are FIX_TRUNC and FLOAT.
4878 This function checks if these operations are supported
4879 by the target platform either directly (via vector tree-codes), or via
4883 - CODE1 is code of vector operation to be used when
4884 vectorizing the operation, if available.
4885 - DECL is decl of target builtin functions to be used
4886 when vectorizing the operation, if available. In this case,
4887 CODE1 is CALL_EXPR. */
4890 supportable_convert_operation (enum tree_code code
,
4891 tree vectype_out
, tree vectype_in
,
4892 tree
*decl
, enum tree_code
*code1
)
4894 enum machine_mode m1
,m2
;
4897 m1
= TYPE_MODE (vectype_out
);
4898 m2
= TYPE_MODE (vectype_in
);
4900 /* First check if we can done conversion directly. */
4901 if ((code
== FIX_TRUNC_EXPR
4902 && can_fix_p (m1
,m2
,TYPE_UNSIGNED (vectype_out
), &truncp
)
4903 != CODE_FOR_nothing
)
4904 || (code
== FLOAT_EXPR
4905 && can_float_p (m1
,m2
,TYPE_UNSIGNED (vectype_in
))
4906 != CODE_FOR_nothing
))
4912 /* Now check for builtin. */
4913 if (targetm
.vectorize
.builtin_conversion
4914 && targetm
.vectorize
.builtin_conversion (code
, vectype_out
, vectype_in
))
4917 *decl
= targetm
.vectorize
.builtin_conversion (code
, vectype_out
, vectype_in
);
4924 /* Generate code to convert FROM to floating point
4925 and store in TO. FROM must be fixed point and not VOIDmode.
4926 UNSIGNEDP nonzero means regard FROM as unsigned.
4927 Normally this is done by correcting the final value
4928 if it is negative. */
4931 expand_float (rtx to
, rtx from
, int unsignedp
)
4933 enum insn_code icode
;
4935 enum machine_mode fmode
, imode
;
4936 bool can_do_signed
= false;
4938 /* Crash now, because we won't be able to decide which mode to use. */
4939 gcc_assert (GET_MODE (from
) != VOIDmode
);
4941 /* Look for an insn to do the conversion. Do it in the specified
4942 modes if possible; otherwise convert either input, output or both to
4943 wider mode. If the integer mode is wider than the mode of FROM,
4944 we can do the conversion signed even if the input is unsigned. */
4946 for (fmode
= GET_MODE (to
); fmode
!= VOIDmode
;
4947 fmode
= GET_MODE_WIDER_MODE (fmode
))
4948 for (imode
= GET_MODE (from
); imode
!= VOIDmode
;
4949 imode
= GET_MODE_WIDER_MODE (imode
))
4951 int doing_unsigned
= unsignedp
;
4953 if (fmode
!= GET_MODE (to
)
4954 && significand_size (fmode
) < GET_MODE_PRECISION (GET_MODE (from
)))
4957 icode
= can_float_p (fmode
, imode
, unsignedp
);
4958 if (icode
== CODE_FOR_nothing
&& unsignedp
)
4960 enum insn_code scode
= can_float_p (fmode
, imode
, 0);
4961 if (scode
!= CODE_FOR_nothing
)
4962 can_do_signed
= true;
4963 if (imode
!= GET_MODE (from
))
4964 icode
= scode
, doing_unsigned
= 0;
4967 if (icode
!= CODE_FOR_nothing
)
4969 if (imode
!= GET_MODE (from
))
4970 from
= convert_to_mode (imode
, from
, unsignedp
);
4972 if (fmode
!= GET_MODE (to
))
4973 target
= gen_reg_rtx (fmode
);
4975 emit_unop_insn (icode
, target
, from
,
4976 doing_unsigned
? UNSIGNED_FLOAT
: FLOAT
);
4979 convert_move (to
, target
, 0);
4984 /* Unsigned integer, and no way to convert directly. Convert as signed,
4985 then unconditionally adjust the result. */
4986 if (unsignedp
&& can_do_signed
)
4988 rtx label
= gen_label_rtx ();
4990 REAL_VALUE_TYPE offset
;
4992 /* Look for a usable floating mode FMODE wider than the source and at
4993 least as wide as the target. Using FMODE will avoid rounding woes
4994 with unsigned values greater than the signed maximum value. */
4996 for (fmode
= GET_MODE (to
); fmode
!= VOIDmode
;
4997 fmode
= GET_MODE_WIDER_MODE (fmode
))
4998 if (GET_MODE_PRECISION (GET_MODE (from
)) < GET_MODE_BITSIZE (fmode
)
4999 && can_float_p (fmode
, GET_MODE (from
), 0) != CODE_FOR_nothing
)
5002 if (fmode
== VOIDmode
)
5004 /* There is no such mode. Pretend the target is wide enough. */
5005 fmode
= GET_MODE (to
);
5007 /* Avoid double-rounding when TO is narrower than FROM. */
5008 if ((significand_size (fmode
) + 1)
5009 < GET_MODE_PRECISION (GET_MODE (from
)))
5012 rtx neglabel
= gen_label_rtx ();
5014 /* Don't use TARGET if it isn't a register, is a hard register,
5015 or is the wrong mode. */
5017 || REGNO (target
) < FIRST_PSEUDO_REGISTER
5018 || GET_MODE (target
) != fmode
)
5019 target
= gen_reg_rtx (fmode
);
5021 imode
= GET_MODE (from
);
5022 do_pending_stack_adjust ();
5024 /* Test whether the sign bit is set. */
5025 emit_cmp_and_jump_insns (from
, const0_rtx
, LT
, NULL_RTX
, imode
,
5028 /* The sign bit is not set. Convert as signed. */
5029 expand_float (target
, from
, 0);
5030 emit_jump_insn (gen_jump (label
));
5033 /* The sign bit is set.
5034 Convert to a usable (positive signed) value by shifting right
5035 one bit, while remembering if a nonzero bit was shifted
5036 out; i.e., compute (from & 1) | (from >> 1). */
5038 emit_label (neglabel
);
5039 temp
= expand_binop (imode
, and_optab
, from
, const1_rtx
,
5040 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
5041 temp1
= expand_shift (RSHIFT_EXPR
, imode
, from
, 1, NULL_RTX
, 1);
5042 temp
= expand_binop (imode
, ior_optab
, temp
, temp1
, temp
, 1,
5044 expand_float (target
, temp
, 0);
5046 /* Multiply by 2 to undo the shift above. */
5047 temp
= expand_binop (fmode
, add_optab
, target
, target
,
5048 target
, 0, OPTAB_LIB_WIDEN
);
5050 emit_move_insn (target
, temp
);
5052 do_pending_stack_adjust ();
5058 /* If we are about to do some arithmetic to correct for an
5059 unsigned operand, do it in a pseudo-register. */
5061 if (GET_MODE (to
) != fmode
5062 || !REG_P (to
) || REGNO (to
) < FIRST_PSEUDO_REGISTER
)
5063 target
= gen_reg_rtx (fmode
);
5065 /* Convert as signed integer to floating. */
5066 expand_float (target
, from
, 0);
5068 /* If FROM is negative (and therefore TO is negative),
5069 correct its value by 2**bitwidth. */
5071 do_pending_stack_adjust ();
5072 emit_cmp_and_jump_insns (from
, const0_rtx
, GE
, NULL_RTX
, GET_MODE (from
),
5076 real_2expN (&offset
, GET_MODE_PRECISION (GET_MODE (from
)), fmode
);
5077 temp
= expand_binop (fmode
, add_optab
, target
,
5078 CONST_DOUBLE_FROM_REAL_VALUE (offset
, fmode
),
5079 target
, 0, OPTAB_LIB_WIDEN
);
5081 emit_move_insn (target
, temp
);
5083 do_pending_stack_adjust ();
5088 /* No hardware instruction available; call a library routine. */
5093 convert_optab tab
= unsignedp
? ufloat_optab
: sfloat_optab
;
5095 if (GET_MODE_SIZE (GET_MODE (from
)) < GET_MODE_SIZE (SImode
))
5096 from
= convert_to_mode (SImode
, from
, unsignedp
);
5098 libfunc
= convert_optab_libfunc (tab
, GET_MODE (to
), GET_MODE (from
));
5099 gcc_assert (libfunc
);
5103 value
= emit_library_call_value (libfunc
, NULL_RTX
, LCT_CONST
,
5104 GET_MODE (to
), 1, from
,
5106 insns
= get_insns ();
5109 emit_libcall_block (insns
, target
, value
,
5110 gen_rtx_fmt_e (unsignedp
? UNSIGNED_FLOAT
: FLOAT
,
5111 GET_MODE (to
), from
));
5116 /* Copy result to requested destination
5117 if we have been computing in a temp location. */
5121 if (GET_MODE (target
) == GET_MODE (to
))
5122 emit_move_insn (to
, target
);
5124 convert_move (to
, target
, 0);
5128 /* Generate code to convert FROM to fixed point and store in TO. FROM
5129 must be floating point. */
5132 expand_fix (rtx to
, rtx from
, int unsignedp
)
5134 enum insn_code icode
;
5136 enum machine_mode fmode
, imode
;
5139 /* We first try to find a pair of modes, one real and one integer, at
5140 least as wide as FROM and TO, respectively, in which we can open-code
5141 this conversion. If the integer mode is wider than the mode of TO,
5142 we can do the conversion either signed or unsigned. */
5144 for (fmode
= GET_MODE (from
); fmode
!= VOIDmode
;
5145 fmode
= GET_MODE_WIDER_MODE (fmode
))
5146 for (imode
= GET_MODE (to
); imode
!= VOIDmode
;
5147 imode
= GET_MODE_WIDER_MODE (imode
))
5149 int doing_unsigned
= unsignedp
;
5151 icode
= can_fix_p (imode
, fmode
, unsignedp
, &must_trunc
);
5152 if (icode
== CODE_FOR_nothing
&& imode
!= GET_MODE (to
) && unsignedp
)
5153 icode
= can_fix_p (imode
, fmode
, 0, &must_trunc
), doing_unsigned
= 0;
5155 if (icode
!= CODE_FOR_nothing
)
5157 rtx last
= get_last_insn ();
5158 if (fmode
!= GET_MODE (from
))
5159 from
= convert_to_mode (fmode
, from
, 0);
5163 rtx temp
= gen_reg_rtx (GET_MODE (from
));
5164 from
= expand_unop (GET_MODE (from
), ftrunc_optab
, from
,
5168 if (imode
!= GET_MODE (to
))
5169 target
= gen_reg_rtx (imode
);
5171 if (maybe_emit_unop_insn (icode
, target
, from
,
5172 doing_unsigned
? UNSIGNED_FIX
: FIX
))
5175 convert_move (to
, target
, unsignedp
);
5178 delete_insns_since (last
);
5182 /* For an unsigned conversion, there is one more way to do it.
5183 If we have a signed conversion, we generate code that compares
5184 the real value to the largest representable positive number. If if
5185 is smaller, the conversion is done normally. Otherwise, subtract
5186 one plus the highest signed number, convert, and add it back.
5188 We only need to check all real modes, since we know we didn't find
5189 anything with a wider integer mode.
5191 This code used to extend FP value into mode wider than the destination.
5192 This is needed for decimal float modes which cannot accurately
5193 represent one plus the highest signed number of the same size, but
5194 not for binary modes. Consider, for instance conversion from SFmode
5197 The hot path through the code is dealing with inputs smaller than 2^63
5198 and doing just the conversion, so there is no bits to lose.
5200 In the other path we know the value is positive in the range 2^63..2^64-1
5201 inclusive. (as for other input overflow happens and result is undefined)
5202 So we know that the most important bit set in mantissa corresponds to
5203 2^63. The subtraction of 2^63 should not generate any rounding as it
5204 simply clears out that bit. The rest is trivial. */
5206 if (unsignedp
&& GET_MODE_PRECISION (GET_MODE (to
)) <= HOST_BITS_PER_WIDE_INT
)
5207 for (fmode
= GET_MODE (from
); fmode
!= VOIDmode
;
5208 fmode
= GET_MODE_WIDER_MODE (fmode
))
5209 if (CODE_FOR_nothing
!= can_fix_p (GET_MODE (to
), fmode
, 0, &must_trunc
)
5210 && (!DECIMAL_FLOAT_MODE_P (fmode
)
5211 || GET_MODE_BITSIZE (fmode
) > GET_MODE_PRECISION (GET_MODE (to
))))
5214 REAL_VALUE_TYPE offset
;
5215 rtx limit
, lab1
, lab2
, insn
;
5217 bitsize
= GET_MODE_PRECISION (GET_MODE (to
));
5218 real_2expN (&offset
, bitsize
- 1, fmode
);
5219 limit
= CONST_DOUBLE_FROM_REAL_VALUE (offset
, fmode
);
5220 lab1
= gen_label_rtx ();
5221 lab2
= gen_label_rtx ();
5223 if (fmode
!= GET_MODE (from
))
5224 from
= convert_to_mode (fmode
, from
, 0);
5226 /* See if we need to do the subtraction. */
5227 do_pending_stack_adjust ();
5228 emit_cmp_and_jump_insns (from
, limit
, GE
, NULL_RTX
, GET_MODE (from
),
5231 /* If not, do the signed "fix" and branch around fixup code. */
5232 expand_fix (to
, from
, 0);
5233 emit_jump_insn (gen_jump (lab2
));
5236 /* Otherwise, subtract 2**(N-1), convert to signed number,
5237 then add 2**(N-1). Do the addition using XOR since this
5238 will often generate better code. */
5240 target
= expand_binop (GET_MODE (from
), sub_optab
, from
, limit
,
5241 NULL_RTX
, 0, OPTAB_LIB_WIDEN
);
5242 expand_fix (to
, target
, 0);
5243 target
= expand_binop (GET_MODE (to
), xor_optab
, to
,
5245 ((HOST_WIDE_INT
) 1 << (bitsize
- 1),
5247 to
, 1, OPTAB_LIB_WIDEN
);
5250 emit_move_insn (to
, target
);
5254 if (optab_handler (mov_optab
, GET_MODE (to
)) != CODE_FOR_nothing
)
5256 /* Make a place for a REG_NOTE and add it. */
5257 insn
= emit_move_insn (to
, to
);
5258 set_dst_reg_note (insn
, REG_EQUAL
,
5259 gen_rtx_fmt_e (UNSIGNED_FIX
, GET_MODE (to
),
5267 /* We can't do it with an insn, so use a library call. But first ensure
5268 that the mode of TO is at least as wide as SImode, since those are the
5269 only library calls we know about. */
5271 if (GET_MODE_SIZE (GET_MODE (to
)) < GET_MODE_SIZE (SImode
))
5273 target
= gen_reg_rtx (SImode
);
5275 expand_fix (target
, from
, unsignedp
);
5283 convert_optab tab
= unsignedp
? ufix_optab
: sfix_optab
;
5284 libfunc
= convert_optab_libfunc (tab
, GET_MODE (to
), GET_MODE (from
));
5285 gcc_assert (libfunc
);
5289 value
= emit_library_call_value (libfunc
, NULL_RTX
, LCT_CONST
,
5290 GET_MODE (to
), 1, from
,
5292 insns
= get_insns ();
5295 emit_libcall_block (insns
, target
, value
,
5296 gen_rtx_fmt_e (unsignedp
? UNSIGNED_FIX
: FIX
,
5297 GET_MODE (to
), from
));
5302 if (GET_MODE (to
) == GET_MODE (target
))
5303 emit_move_insn (to
, target
);
5305 convert_move (to
, target
, 0);
5309 /* Generate code to convert FROM or TO a fixed-point.
5310 If UINTP is true, either TO or FROM is an unsigned integer.
5311 If SATP is true, we need to saturate the result. */
5314 expand_fixed_convert (rtx to
, rtx from
, int uintp
, int satp
)
5316 enum machine_mode to_mode
= GET_MODE (to
);
5317 enum machine_mode from_mode
= GET_MODE (from
);
5319 enum rtx_code this_code
;
5320 enum insn_code code
;
5324 if (to_mode
== from_mode
)
5326 emit_move_insn (to
, from
);
5332 tab
= satp
? satfractuns_optab
: fractuns_optab
;
5333 this_code
= satp
? UNSIGNED_SAT_FRACT
: UNSIGNED_FRACT_CONVERT
;
5337 tab
= satp
? satfract_optab
: fract_optab
;
5338 this_code
= satp
? SAT_FRACT
: FRACT_CONVERT
;
5340 code
= convert_optab_handler (tab
, to_mode
, from_mode
);
5341 if (code
!= CODE_FOR_nothing
)
5343 emit_unop_insn (code
, to
, from
, this_code
);
5347 libfunc
= convert_optab_libfunc (tab
, to_mode
, from_mode
);
5348 gcc_assert (libfunc
);
5351 value
= emit_library_call_value (libfunc
, NULL_RTX
, LCT_CONST
, to_mode
,
5352 1, from
, from_mode
);
5353 insns
= get_insns ();
5356 emit_libcall_block (insns
, to
, value
,
5357 gen_rtx_fmt_e (optab_to_code (tab
), to_mode
, from
));
5360 /* Generate code to convert FROM to fixed point and store in TO. FROM
5361 must be floating point, TO must be signed. Use the conversion optab
5362 TAB to do the conversion. */
5365 expand_sfix_optab (rtx to
, rtx from
, convert_optab tab
)
5367 enum insn_code icode
;
5369 enum machine_mode fmode
, imode
;
5371 /* We first try to find a pair of modes, one real and one integer, at
5372 least as wide as FROM and TO, respectively, in which we can open-code
5373 this conversion. If the integer mode is wider than the mode of TO,
5374 we can do the conversion either signed or unsigned. */
5376 for (fmode
= GET_MODE (from
); fmode
!= VOIDmode
;
5377 fmode
= GET_MODE_WIDER_MODE (fmode
))
5378 for (imode
= GET_MODE (to
); imode
!= VOIDmode
;
5379 imode
= GET_MODE_WIDER_MODE (imode
))
5381 icode
= convert_optab_handler (tab
, imode
, fmode
);
5382 if (icode
!= CODE_FOR_nothing
)
5384 rtx last
= get_last_insn ();
5385 if (fmode
!= GET_MODE (from
))
5386 from
= convert_to_mode (fmode
, from
, 0);
5388 if (imode
!= GET_MODE (to
))
5389 target
= gen_reg_rtx (imode
);
5391 if (!maybe_emit_unop_insn (icode
, target
, from
, UNKNOWN
))
5393 delete_insns_since (last
);
5397 convert_move (to
, target
, 0);
5405 /* Report whether we have an instruction to perform the operation
5406 specified by CODE on operands of mode MODE. */
5408 have_insn_for (enum rtx_code code
, enum machine_mode mode
)
5410 return (code_to_optab (code
)
5411 && (optab_handler (code_to_optab (code
), mode
)
5412 != CODE_FOR_nothing
));
5415 /* Initialize the libfunc fields of an entire group of entries in some
5416 optab. Each entry is set equal to a string consisting of a leading
5417 pair of underscores followed by a generic operation name followed by
5418 a mode name (downshifted to lowercase) followed by a single character
5419 representing the number of operands for the given operation (which is
5420 usually one of the characters '2', '3', or '4').
5422 OPTABLE is the table in which libfunc fields are to be initialized.
5423 OPNAME is the generic (string) name of the operation.
5424 SUFFIX is the character which specifies the number of operands for
5425 the given generic operation.
5426 MODE is the mode to generate for.
5430 gen_libfunc (optab optable
, const char *opname
, int suffix
,
5431 enum machine_mode mode
)
5433 unsigned opname_len
= strlen (opname
);
5434 const char *mname
= GET_MODE_NAME (mode
);
5435 unsigned mname_len
= strlen (mname
);
5436 int prefix_len
= targetm
.libfunc_gnu_prefix
? 6 : 2;
5437 int len
= prefix_len
+ opname_len
+ mname_len
+ 1 + 1;
5438 char *libfunc_name
= XALLOCAVEC (char, len
);
5445 if (targetm
.libfunc_gnu_prefix
)
5452 for (q
= opname
; *q
; )
5454 for (q
= mname
; *q
; q
++)
5455 *p
++ = TOLOWER (*q
);
5459 set_optab_libfunc (optable
, mode
,
5460 ggc_alloc_string (libfunc_name
, p
- libfunc_name
));
5463 /* Like gen_libfunc, but verify that integer operation is involved. */
5466 gen_int_libfunc (optab optable
, const char *opname
, char suffix
,
5467 enum machine_mode mode
)
5469 int maxsize
= 2 * BITS_PER_WORD
;
5471 if (GET_MODE_CLASS (mode
) != MODE_INT
)
5473 if (maxsize
< LONG_LONG_TYPE_SIZE
)
5474 maxsize
= LONG_LONG_TYPE_SIZE
;
5475 if (GET_MODE_CLASS (mode
) != MODE_INT
5476 || mode
< word_mode
|| GET_MODE_BITSIZE (mode
) > maxsize
)
5478 gen_libfunc (optable
, opname
, suffix
, mode
);
5481 /* Like gen_libfunc, but verify that FP and set decimal prefix if needed. */
5484 gen_fp_libfunc (optab optable
, const char *opname
, char suffix
,
5485 enum machine_mode mode
)
5489 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
)
5490 gen_libfunc (optable
, opname
, suffix
, mode
);
5491 if (DECIMAL_FLOAT_MODE_P (mode
))
5493 dec_opname
= XALLOCAVEC (char, sizeof (DECIMAL_PREFIX
) + strlen (opname
));
5494 /* For BID support, change the name to have either a bid_ or dpd_ prefix
5495 depending on the low level floating format used. */
5496 memcpy (dec_opname
, DECIMAL_PREFIX
, sizeof (DECIMAL_PREFIX
) - 1);
5497 strcpy (dec_opname
+ sizeof (DECIMAL_PREFIX
) - 1, opname
);
5498 gen_libfunc (optable
, dec_opname
, suffix
, mode
);
5502 /* Like gen_libfunc, but verify that fixed-point operation is involved. */
5505 gen_fixed_libfunc (optab optable
, const char *opname
, char suffix
,
5506 enum machine_mode mode
)
5508 if (!ALL_FIXED_POINT_MODE_P (mode
))
5510 gen_libfunc (optable
, opname
, suffix
, mode
);
5513 /* Like gen_libfunc, but verify that signed fixed-point operation is
5517 gen_signed_fixed_libfunc (optab optable
, const char *opname
, char suffix
,
5518 enum machine_mode mode
)
5520 if (!SIGNED_FIXED_POINT_MODE_P (mode
))
5522 gen_libfunc (optable
, opname
, suffix
, mode
);
5525 /* Like gen_libfunc, but verify that unsigned fixed-point operation is
5529 gen_unsigned_fixed_libfunc (optab optable
, const char *opname
, char suffix
,
5530 enum machine_mode mode
)
5532 if (!UNSIGNED_FIXED_POINT_MODE_P (mode
))
5534 gen_libfunc (optable
, opname
, suffix
, mode
);
5537 /* Like gen_libfunc, but verify that FP or INT operation is involved. */
5540 gen_int_fp_libfunc (optab optable
, const char *name
, char suffix
,
5541 enum machine_mode mode
)
5543 if (DECIMAL_FLOAT_MODE_P (mode
) || GET_MODE_CLASS (mode
) == MODE_FLOAT
)
5544 gen_fp_libfunc (optable
, name
, suffix
, mode
);
5545 if (INTEGRAL_MODE_P (mode
))
5546 gen_int_libfunc (optable
, name
, suffix
, mode
);
5549 /* Like gen_libfunc, but verify that FP or INT operation is involved
5550 and add 'v' suffix for integer operation. */
5553 gen_intv_fp_libfunc (optab optable
, const char *name
, char suffix
,
5554 enum machine_mode mode
)
5556 if (DECIMAL_FLOAT_MODE_P (mode
) || GET_MODE_CLASS (mode
) == MODE_FLOAT
)
5557 gen_fp_libfunc (optable
, name
, suffix
, mode
);
5558 if (GET_MODE_CLASS (mode
) == MODE_INT
)
5560 int len
= strlen (name
);
5561 char *v_name
= XALLOCAVEC (char, len
+ 2);
5562 strcpy (v_name
, name
);
5564 v_name
[len
+ 1] = 0;
5565 gen_int_libfunc (optable
, v_name
, suffix
, mode
);
5569 /* Like gen_libfunc, but verify that FP or INT or FIXED operation is
5573 gen_int_fp_fixed_libfunc (optab optable
, const char *name
, char suffix
,
5574 enum machine_mode mode
)
5576 if (DECIMAL_FLOAT_MODE_P (mode
) || GET_MODE_CLASS (mode
) == MODE_FLOAT
)
5577 gen_fp_libfunc (optable
, name
, suffix
, mode
);
5578 if (INTEGRAL_MODE_P (mode
))
5579 gen_int_libfunc (optable
, name
, suffix
, mode
);
5580 if (ALL_FIXED_POINT_MODE_P (mode
))
5581 gen_fixed_libfunc (optable
, name
, suffix
, mode
);
5584 /* Like gen_libfunc, but verify that FP or INT or signed FIXED operation is
5588 gen_int_fp_signed_fixed_libfunc (optab optable
, const char *name
, char suffix
,
5589 enum machine_mode mode
)
5591 if (DECIMAL_FLOAT_MODE_P (mode
) || GET_MODE_CLASS (mode
) == MODE_FLOAT
)
5592 gen_fp_libfunc (optable
, name
, suffix
, mode
);
5593 if (INTEGRAL_MODE_P (mode
))
5594 gen_int_libfunc (optable
, name
, suffix
, mode
);
5595 if (SIGNED_FIXED_POINT_MODE_P (mode
))
5596 gen_signed_fixed_libfunc (optable
, name
, suffix
, mode
);
5599 /* Like gen_libfunc, but verify that INT or FIXED operation is
5603 gen_int_fixed_libfunc (optab optable
, const char *name
, char suffix
,
5604 enum machine_mode mode
)
5606 if (INTEGRAL_MODE_P (mode
))
5607 gen_int_libfunc (optable
, name
, suffix
, mode
);
5608 if (ALL_FIXED_POINT_MODE_P (mode
))
5609 gen_fixed_libfunc (optable
, name
, suffix
, mode
);
5612 /* Like gen_libfunc, but verify that INT or signed FIXED operation is
5616 gen_int_signed_fixed_libfunc (optab optable
, const char *name
, char suffix
,
5617 enum machine_mode mode
)
5619 if (INTEGRAL_MODE_P (mode
))
5620 gen_int_libfunc (optable
, name
, suffix
, mode
);
5621 if (SIGNED_FIXED_POINT_MODE_P (mode
))
5622 gen_signed_fixed_libfunc (optable
, name
, suffix
, mode
);
5625 /* Like gen_libfunc, but verify that INT or unsigned FIXED operation is
5629 gen_int_unsigned_fixed_libfunc (optab optable
, const char *name
, char suffix
,
5630 enum machine_mode mode
)
5632 if (INTEGRAL_MODE_P (mode
))
5633 gen_int_libfunc (optable
, name
, suffix
, mode
);
5634 if (UNSIGNED_FIXED_POINT_MODE_P (mode
))
5635 gen_unsigned_fixed_libfunc (optable
, name
, suffix
, mode
);
5638 /* Initialize the libfunc fields of an entire group of entries of an
5639 inter-mode-class conversion optab. The string formation rules are
5640 similar to the ones for init_libfuncs, above, but instead of having
5641 a mode name and an operand count these functions have two mode names
5642 and no operand count. */
5645 gen_interclass_conv_libfunc (convert_optab tab
,
5647 enum machine_mode tmode
,
5648 enum machine_mode fmode
)
5650 size_t opname_len
= strlen (opname
);
5651 size_t mname_len
= 0;
5653 const char *fname
, *tname
;
5655 int prefix_len
= targetm
.libfunc_gnu_prefix
? 6 : 2;
5656 char *libfunc_name
, *suffix
;
5657 char *nondec_name
, *dec_name
, *nondec_suffix
, *dec_suffix
;
5660 /* If this is a decimal conversion, add the current BID vs. DPD prefix that
5661 depends on which underlying decimal floating point format is used. */
5662 const size_t dec_len
= sizeof (DECIMAL_PREFIX
) - 1;
5664 mname_len
= strlen (GET_MODE_NAME (tmode
)) + strlen (GET_MODE_NAME (fmode
));
5666 nondec_name
= XALLOCAVEC (char, prefix_len
+ opname_len
+ mname_len
+ 1 + 1);
5667 nondec_name
[0] = '_';
5668 nondec_name
[1] = '_';
5669 if (targetm
.libfunc_gnu_prefix
)
5671 nondec_name
[2] = 'g';
5672 nondec_name
[3] = 'n';
5673 nondec_name
[4] = 'u';
5674 nondec_name
[5] = '_';
5677 memcpy (&nondec_name
[prefix_len
], opname
, opname_len
);
5678 nondec_suffix
= nondec_name
+ opname_len
+ prefix_len
;
5680 dec_name
= XALLOCAVEC (char, 2 + dec_len
+ opname_len
+ mname_len
+ 1 + 1);
5683 memcpy (&dec_name
[2], DECIMAL_PREFIX
, dec_len
);
5684 memcpy (&dec_name
[2+dec_len
], opname
, opname_len
);
5685 dec_suffix
= dec_name
+ dec_len
+ opname_len
+ 2;
5687 fname
= GET_MODE_NAME (fmode
);
5688 tname
= GET_MODE_NAME (tmode
);
5690 if (DECIMAL_FLOAT_MODE_P(fmode
) || DECIMAL_FLOAT_MODE_P(tmode
))
5692 libfunc_name
= dec_name
;
5693 suffix
= dec_suffix
;
5697 libfunc_name
= nondec_name
;
5698 suffix
= nondec_suffix
;
5702 for (q
= fname
; *q
; p
++, q
++)
5704 for (q
= tname
; *q
; p
++, q
++)
5709 set_conv_libfunc (tab
, tmode
, fmode
,
5710 ggc_alloc_string (libfunc_name
, p
- libfunc_name
));
5713 /* Same as gen_interclass_conv_libfunc but verify that we are producing
5714 int->fp conversion. */
5717 gen_int_to_fp_conv_libfunc (convert_optab tab
,
5719 enum machine_mode tmode
,
5720 enum machine_mode fmode
)
5722 if (GET_MODE_CLASS (fmode
) != MODE_INT
)
5724 if (GET_MODE_CLASS (tmode
) != MODE_FLOAT
&& !DECIMAL_FLOAT_MODE_P (tmode
))
5726 gen_interclass_conv_libfunc (tab
, opname
, tmode
, fmode
);
5729 /* ufloat_optab is special by using floatun for FP and floatuns decimal fp
5733 gen_ufloat_conv_libfunc (convert_optab tab
,
5734 const char *opname ATTRIBUTE_UNUSED
,
5735 enum machine_mode tmode
,
5736 enum machine_mode fmode
)
5738 if (DECIMAL_FLOAT_MODE_P (tmode
))
5739 gen_int_to_fp_conv_libfunc (tab
, "floatuns", tmode
, fmode
);
5741 gen_int_to_fp_conv_libfunc (tab
, "floatun", tmode
, fmode
);
5744 /* Same as gen_interclass_conv_libfunc but verify that we are producing
5745 fp->int conversion. */
5748 gen_int_to_fp_nondecimal_conv_libfunc (convert_optab tab
,
5750 enum machine_mode tmode
,
5751 enum machine_mode fmode
)
5753 if (GET_MODE_CLASS (fmode
) != MODE_INT
)
5755 if (GET_MODE_CLASS (tmode
) != MODE_FLOAT
)
5757 gen_interclass_conv_libfunc (tab
, opname
, tmode
, fmode
);
5760 /* Same as gen_interclass_conv_libfunc but verify that we are producing
5761 fp->int conversion with no decimal floating point involved. */
5764 gen_fp_to_int_conv_libfunc (convert_optab tab
,
5766 enum machine_mode tmode
,
5767 enum machine_mode fmode
)
5769 if (GET_MODE_CLASS (fmode
) != MODE_FLOAT
&& !DECIMAL_FLOAT_MODE_P (fmode
))
5771 if (GET_MODE_CLASS (tmode
) != MODE_INT
)
5773 gen_interclass_conv_libfunc (tab
, opname
, tmode
, fmode
);
5776 /* Initialize the libfunc fields of an of an intra-mode-class conversion optab.
5777 The string formation rules are
5778 similar to the ones for init_libfunc, above. */
5781 gen_intraclass_conv_libfunc (convert_optab tab
, const char *opname
,
5782 enum machine_mode tmode
, enum machine_mode fmode
)
5784 size_t opname_len
= strlen (opname
);
5785 size_t mname_len
= 0;
5787 const char *fname
, *tname
;
5789 int prefix_len
= targetm
.libfunc_gnu_prefix
? 6 : 2;
5790 char *nondec_name
, *dec_name
, *nondec_suffix
, *dec_suffix
;
5791 char *libfunc_name
, *suffix
;
5794 /* If this is a decimal conversion, add the current BID vs. DPD prefix that
5795 depends on which underlying decimal floating point format is used. */
5796 const size_t dec_len
= sizeof (DECIMAL_PREFIX
) - 1;
5798 mname_len
= strlen (GET_MODE_NAME (tmode
)) + strlen (GET_MODE_NAME (fmode
));
5800 nondec_name
= XALLOCAVEC (char, 2 + opname_len
+ mname_len
+ 1 + 1);
5801 nondec_name
[0] = '_';
5802 nondec_name
[1] = '_';
5803 if (targetm
.libfunc_gnu_prefix
)
5805 nondec_name
[2] = 'g';
5806 nondec_name
[3] = 'n';
5807 nondec_name
[4] = 'u';
5808 nondec_name
[5] = '_';
5810 memcpy (&nondec_name
[prefix_len
], opname
, opname_len
);
5811 nondec_suffix
= nondec_name
+ opname_len
+ prefix_len
;
5813 dec_name
= XALLOCAVEC (char, 2 + dec_len
+ opname_len
+ mname_len
+ 1 + 1);
5816 memcpy (&dec_name
[2], DECIMAL_PREFIX
, dec_len
);
5817 memcpy (&dec_name
[2 + dec_len
], opname
, opname_len
);
5818 dec_suffix
= dec_name
+ dec_len
+ opname_len
+ 2;
5820 fname
= GET_MODE_NAME (fmode
);
5821 tname
= GET_MODE_NAME (tmode
);
5823 if (DECIMAL_FLOAT_MODE_P(fmode
) || DECIMAL_FLOAT_MODE_P(tmode
))
5825 libfunc_name
= dec_name
;
5826 suffix
= dec_suffix
;
5830 libfunc_name
= nondec_name
;
5831 suffix
= nondec_suffix
;
5835 for (q
= fname
; *q
; p
++, q
++)
5837 for (q
= tname
; *q
; p
++, q
++)
5843 set_conv_libfunc (tab
, tmode
, fmode
,
5844 ggc_alloc_string (libfunc_name
, p
- libfunc_name
));
5847 /* Pick proper libcall for trunc_optab. We need to chose if we do
5848 truncation or extension and interclass or intraclass. */
5851 gen_trunc_conv_libfunc (convert_optab tab
,
5853 enum machine_mode tmode
,
5854 enum machine_mode fmode
)
5856 if (GET_MODE_CLASS (tmode
) != MODE_FLOAT
&& !DECIMAL_FLOAT_MODE_P (tmode
))
5858 if (GET_MODE_CLASS (fmode
) != MODE_FLOAT
&& !DECIMAL_FLOAT_MODE_P (fmode
))
5863 if ((GET_MODE_CLASS (tmode
) == MODE_FLOAT
&& DECIMAL_FLOAT_MODE_P (fmode
))
5864 || (GET_MODE_CLASS (fmode
) == MODE_FLOAT
&& DECIMAL_FLOAT_MODE_P (tmode
)))
5865 gen_interclass_conv_libfunc (tab
, opname
, tmode
, fmode
);
5867 if (GET_MODE_PRECISION (fmode
) <= GET_MODE_PRECISION (tmode
))
5870 if ((GET_MODE_CLASS (tmode
) == MODE_FLOAT
5871 && GET_MODE_CLASS (fmode
) == MODE_FLOAT
)
5872 || (DECIMAL_FLOAT_MODE_P (fmode
) && DECIMAL_FLOAT_MODE_P (tmode
)))
5873 gen_intraclass_conv_libfunc (tab
, opname
, tmode
, fmode
);
5876 /* Pick proper libcall for extend_optab. We need to chose if we do
5877 truncation or extension and interclass or intraclass. */
5880 gen_extend_conv_libfunc (convert_optab tab
,
5881 const char *opname ATTRIBUTE_UNUSED
,
5882 enum machine_mode tmode
,
5883 enum machine_mode fmode
)
5885 if (GET_MODE_CLASS (tmode
) != MODE_FLOAT
&& !DECIMAL_FLOAT_MODE_P (tmode
))
5887 if (GET_MODE_CLASS (fmode
) != MODE_FLOAT
&& !DECIMAL_FLOAT_MODE_P (fmode
))
5892 if ((GET_MODE_CLASS (tmode
) == MODE_FLOAT
&& DECIMAL_FLOAT_MODE_P (fmode
))
5893 || (GET_MODE_CLASS (fmode
) == MODE_FLOAT
&& DECIMAL_FLOAT_MODE_P (tmode
)))
5894 gen_interclass_conv_libfunc (tab
, opname
, tmode
, fmode
);
5896 if (GET_MODE_PRECISION (fmode
) > GET_MODE_PRECISION (tmode
))
5899 if ((GET_MODE_CLASS (tmode
) == MODE_FLOAT
5900 && GET_MODE_CLASS (fmode
) == MODE_FLOAT
)
5901 || (DECIMAL_FLOAT_MODE_P (fmode
) && DECIMAL_FLOAT_MODE_P (tmode
)))
5902 gen_intraclass_conv_libfunc (tab
, opname
, tmode
, fmode
);
5905 /* Pick proper libcall for fract_optab. We need to chose if we do
5906 interclass or intraclass. */
5909 gen_fract_conv_libfunc (convert_optab tab
,
5911 enum machine_mode tmode
,
5912 enum machine_mode fmode
)
5916 if (!(ALL_FIXED_POINT_MODE_P (tmode
) || ALL_FIXED_POINT_MODE_P (fmode
)))
5919 if (GET_MODE_CLASS (tmode
) == GET_MODE_CLASS (fmode
))
5920 gen_intraclass_conv_libfunc (tab
, opname
, tmode
, fmode
);
5922 gen_interclass_conv_libfunc (tab
, opname
, tmode
, fmode
);
5925 /* Pick proper libcall for fractuns_optab. */
5928 gen_fractuns_conv_libfunc (convert_optab tab
,
5930 enum machine_mode tmode
,
5931 enum machine_mode fmode
)
5935 /* One mode must be a fixed-point mode, and the other must be an integer
5937 if (!((ALL_FIXED_POINT_MODE_P (tmode
) && GET_MODE_CLASS (fmode
) == MODE_INT
)
5938 || (ALL_FIXED_POINT_MODE_P (fmode
)
5939 && GET_MODE_CLASS (tmode
) == MODE_INT
)))
5942 gen_interclass_conv_libfunc (tab
, opname
, tmode
, fmode
);
5945 /* Pick proper libcall for satfract_optab. We need to chose if we do
5946 interclass or intraclass. */
5949 gen_satfract_conv_libfunc (convert_optab tab
,
5951 enum machine_mode tmode
,
5952 enum machine_mode fmode
)
5956 /* TMODE must be a fixed-point mode. */
5957 if (!ALL_FIXED_POINT_MODE_P (tmode
))
5960 if (GET_MODE_CLASS (tmode
) == GET_MODE_CLASS (fmode
))
5961 gen_intraclass_conv_libfunc (tab
, opname
, tmode
, fmode
);
5963 gen_interclass_conv_libfunc (tab
, opname
, tmode
, fmode
);
5966 /* Pick proper libcall for satfractuns_optab. */
5969 gen_satfractuns_conv_libfunc (convert_optab tab
,
5971 enum machine_mode tmode
,
5972 enum machine_mode fmode
)
5976 /* TMODE must be a fixed-point mode, and FMODE must be an integer mode. */
5977 if (!(ALL_FIXED_POINT_MODE_P (tmode
) && GET_MODE_CLASS (fmode
) == MODE_INT
))
5980 gen_interclass_conv_libfunc (tab
, opname
, tmode
, fmode
);
5983 /* A table of previously-created libfuncs, hashed by name. */
5984 static GTY ((param_is (union tree_node
))) htab_t libfunc_decls
;
5986 /* Hashtable callbacks for libfunc_decls. */
5989 libfunc_decl_hash (const void *entry
)
5991 return IDENTIFIER_HASH_VALUE (DECL_NAME ((const_tree
) entry
));
5995 libfunc_decl_eq (const void *entry1
, const void *entry2
)
5997 return DECL_NAME ((const_tree
) entry1
) == (const_tree
) entry2
;
6000 /* Build a decl for a libfunc named NAME. */
6003 build_libfunc_function (const char *name
)
6005 tree decl
= build_decl (UNKNOWN_LOCATION
, FUNCTION_DECL
,
6006 get_identifier (name
),
6007 build_function_type (integer_type_node
, NULL_TREE
));
6008 /* ??? We don't have any type information except for this is
6009 a function. Pretend this is "int foo()". */
6010 DECL_ARTIFICIAL (decl
) = 1;
6011 DECL_EXTERNAL (decl
) = 1;
6012 TREE_PUBLIC (decl
) = 1;
6013 gcc_assert (DECL_ASSEMBLER_NAME (decl
));
6015 /* Zap the nonsensical SYMBOL_REF_DECL for this. What we're left with
6016 are the flags assigned by targetm.encode_section_info. */
6017 SET_SYMBOL_REF_DECL (XEXP (DECL_RTL (decl
), 0), NULL
);
6023 init_one_libfunc (const char *name
)
6029 if (libfunc_decls
== NULL
)
6030 libfunc_decls
= htab_create_ggc (37, libfunc_decl_hash
,
6031 libfunc_decl_eq
, NULL
);
6033 /* See if we have already created a libfunc decl for this function. */
6034 id
= get_identifier (name
);
6035 hash
= IDENTIFIER_HASH_VALUE (id
);
6036 slot
= htab_find_slot_with_hash (libfunc_decls
, id
, hash
, INSERT
);
6037 decl
= (tree
) *slot
;
6040 /* Create a new decl, so that it can be passed to
6041 targetm.encode_section_info. */
6042 decl
= build_libfunc_function (name
);
6045 return XEXP (DECL_RTL (decl
), 0);
6048 /* Adjust the assembler name of libfunc NAME to ASMSPEC. */
6051 set_user_assembler_libfunc (const char *name
, const char *asmspec
)
6057 id
= get_identifier (name
);
6058 hash
= IDENTIFIER_HASH_VALUE (id
);
6059 slot
= htab_find_slot_with_hash (libfunc_decls
, id
, hash
, NO_INSERT
);
6061 decl
= (tree
) *slot
;
6062 set_user_assembler_name (decl
, asmspec
);
6063 return XEXP (DECL_RTL (decl
), 0);
6066 /* Call this to reset the function entry for one optab (OPTABLE) in mode
6067 MODE to NAME, which should be either 0 or a string constant. */
6069 set_optab_libfunc (optab op
, enum machine_mode mode
, const char *name
)
6072 struct libfunc_entry e
;
6073 struct libfunc_entry
**slot
;
6080 val
= init_one_libfunc (name
);
6083 slot
= (struct libfunc_entry
**) htab_find_slot (libfunc_hash
, &e
, INSERT
);
6085 *slot
= ggc_alloc_libfunc_entry ();
6087 (*slot
)->mode1
= mode
;
6088 (*slot
)->mode2
= VOIDmode
;
6089 (*slot
)->libfunc
= val
;
6092 /* Call this to reset the function entry for one conversion optab
6093 (OPTABLE) from mode FMODE to mode TMODE to NAME, which should be
6094 either 0 or a string constant. */
6096 set_conv_libfunc (convert_optab optab
, enum machine_mode tmode
,
6097 enum machine_mode fmode
, const char *name
)
6100 struct libfunc_entry e
;
6101 struct libfunc_entry
**slot
;
6108 val
= init_one_libfunc (name
);
6111 slot
= (struct libfunc_entry
**) htab_find_slot (libfunc_hash
, &e
, INSERT
);
6113 *slot
= ggc_alloc_libfunc_entry ();
6114 (*slot
)->op
= optab
;
6115 (*slot
)->mode1
= tmode
;
6116 (*slot
)->mode2
= fmode
;
6117 (*slot
)->libfunc
= val
;
6120 /* Call this to initialize the contents of the optabs
6121 appropriately for the current target machine. */
6127 htab_empty (libfunc_hash
);
6129 libfunc_hash
= htab_create_ggc (10, hash_libfunc
, eq_libfunc
, NULL
);
6131 /* Fill in the optabs with the insns we support. */
6134 /* The ffs function operates on `int'. Fall back on it if we do not
6135 have a libgcc2 function for that width. */
6136 if (INT_TYPE_SIZE
< BITS_PER_WORD
)
6137 set_optab_libfunc (ffs_optab
, mode_for_size (INT_TYPE_SIZE
, MODE_INT
, 0),
6140 /* Explicitly initialize the bswap libfuncs since we need them to be
6141 valid for things other than word_mode. */
6142 if (targetm
.libfunc_gnu_prefix
)
6144 set_optab_libfunc (bswap_optab
, SImode
, "__gnu_bswapsi2");
6145 set_optab_libfunc (bswap_optab
, DImode
, "__gnu_bswapdi2");
6149 set_optab_libfunc (bswap_optab
, SImode
, "__bswapsi2");
6150 set_optab_libfunc (bswap_optab
, DImode
, "__bswapdi2");
6153 /* Use cabs for double complex abs, since systems generally have cabs.
6154 Don't define any libcall for float complex, so that cabs will be used. */
6155 if (complex_double_type_node
)
6156 set_optab_libfunc (abs_optab
, TYPE_MODE (complex_double_type_node
),
6159 abort_libfunc
= init_one_libfunc ("abort");
6160 memcpy_libfunc
= init_one_libfunc ("memcpy");
6161 memmove_libfunc
= init_one_libfunc ("memmove");
6162 memcmp_libfunc
= init_one_libfunc ("memcmp");
6163 memset_libfunc
= init_one_libfunc ("memset");
6164 setbits_libfunc
= init_one_libfunc ("__setbits");
6166 #ifndef DONT_USE_BUILTIN_SETJMP
6167 setjmp_libfunc
= init_one_libfunc ("__builtin_setjmp");
6168 longjmp_libfunc
= init_one_libfunc ("__builtin_longjmp");
6170 setjmp_libfunc
= init_one_libfunc ("setjmp");
6171 longjmp_libfunc
= init_one_libfunc ("longjmp");
6173 unwind_sjlj_register_libfunc
= init_one_libfunc ("_Unwind_SjLj_Register");
6174 unwind_sjlj_unregister_libfunc
6175 = init_one_libfunc ("_Unwind_SjLj_Unregister");
6177 /* For function entry/exit instrumentation. */
6178 profile_function_entry_libfunc
6179 = init_one_libfunc ("__cyg_profile_func_enter");
6180 profile_function_exit_libfunc
6181 = init_one_libfunc ("__cyg_profile_func_exit");
6183 gcov_flush_libfunc
= init_one_libfunc ("__gcov_flush");
6185 /* Allow the target to add more libcalls or rename some, etc. */
6186 targetm
.init_libfuncs ();
6189 /* A helper function for init_sync_libfuncs. Using the basename BASE,
6190 install libfuncs into TAB for BASE_N for 1 <= N <= MAX. */
6193 init_sync_libfuncs_1 (optab tab
, const char *base
, int max
)
6195 enum machine_mode mode
;
6197 size_t len
= strlen (base
);
6200 gcc_assert (max
<= 8);
6201 gcc_assert (len
+ 3 < sizeof (buf
));
6203 memcpy (buf
, base
, len
);
6206 buf
[len
+ 2] = '\0';
6209 for (i
= 1; i
<= max
; i
*= 2)
6211 buf
[len
+ 1] = '0' + i
;
6212 set_optab_libfunc (tab
, mode
, buf
);
6213 mode
= GET_MODE_2XWIDER_MODE (mode
);
6218 init_sync_libfuncs (int max
)
6220 if (!flag_sync_libcalls
)
6223 init_sync_libfuncs_1 (sync_compare_and_swap_optab
,
6224 "__sync_val_compare_and_swap", max
);
6225 init_sync_libfuncs_1 (sync_lock_test_and_set_optab
,
6226 "__sync_lock_test_and_set", max
);
6228 init_sync_libfuncs_1 (sync_old_add_optab
, "__sync_fetch_and_add", max
);
6229 init_sync_libfuncs_1 (sync_old_sub_optab
, "__sync_fetch_and_sub", max
);
6230 init_sync_libfuncs_1 (sync_old_ior_optab
, "__sync_fetch_and_or", max
);
6231 init_sync_libfuncs_1 (sync_old_and_optab
, "__sync_fetch_and_and", max
);
6232 init_sync_libfuncs_1 (sync_old_xor_optab
, "__sync_fetch_and_xor", max
);
6233 init_sync_libfuncs_1 (sync_old_nand_optab
, "__sync_fetch_and_nand", max
);
6235 init_sync_libfuncs_1 (sync_new_add_optab
, "__sync_add_and_fetch", max
);
6236 init_sync_libfuncs_1 (sync_new_sub_optab
, "__sync_sub_and_fetch", max
);
6237 init_sync_libfuncs_1 (sync_new_ior_optab
, "__sync_or_and_fetch", max
);
6238 init_sync_libfuncs_1 (sync_new_and_optab
, "__sync_and_and_fetch", max
);
6239 init_sync_libfuncs_1 (sync_new_xor_optab
, "__sync_xor_and_fetch", max
);
6240 init_sync_libfuncs_1 (sync_new_nand_optab
, "__sync_nand_and_fetch", max
);
6243 /* Print information about the current contents of the optabs on
6247 debug_optab_libfuncs (void)
6251 /* Dump the arithmetic optabs. */
6252 for (i
= FIRST_NORM_OPTAB
; i
<= LAST_NORMLIB_OPTAB
; ++i
)
6253 for (j
= 0; j
< NUM_MACHINE_MODES
; ++j
)
6255 rtx l
= optab_libfunc ((optab
) i
, (enum machine_mode
) j
);
6258 gcc_assert (GET_CODE (l
) == SYMBOL_REF
);
6259 fprintf (stderr
, "%s\t%s:\t%s\n",
6260 GET_RTX_NAME (optab_to_code ((optab
) i
)),
6266 /* Dump the conversion optabs. */
6267 for (i
= FIRST_CONV_OPTAB
; i
<= LAST_CONVLIB_OPTAB
; ++i
)
6268 for (j
= 0; j
< NUM_MACHINE_MODES
; ++j
)
6269 for (k
= 0; k
< NUM_MACHINE_MODES
; ++k
)
6271 rtx l
= convert_optab_libfunc ((optab
) i
, (enum machine_mode
) j
,
6272 (enum machine_mode
) k
);
6275 gcc_assert (GET_CODE (l
) == SYMBOL_REF
);
6276 fprintf (stderr
, "%s\t%s\t%s:\t%s\n",
6277 GET_RTX_NAME (optab_to_code ((optab
) i
)),
6286 /* Generate insns to trap with code TCODE if OP1 and OP2 satisfy condition
6287 CODE. Return 0 on failure. */
6290 gen_cond_trap (enum rtx_code code
, rtx op1
, rtx op2
, rtx tcode
)
6292 enum machine_mode mode
= GET_MODE (op1
);
6293 enum insn_code icode
;
6297 if (mode
== VOIDmode
)
6300 icode
= optab_handler (ctrap_optab
, mode
);
6301 if (icode
== CODE_FOR_nothing
)
6304 /* Some targets only accept a zero trap code. */
6305 if (!insn_operand_matches (icode
, 3, tcode
))
6308 do_pending_stack_adjust ();
6310 prepare_cmp_insn (op1
, op2
, code
, NULL_RTX
, false, OPTAB_DIRECT
,
6315 insn
= GEN_FCN (icode
) (trap_rtx
, XEXP (trap_rtx
, 0), XEXP (trap_rtx
, 1),
6318 /* If that failed, then give up. */
6326 insn
= get_insns ();
6331 /* Return rtx code for TCODE. Use UNSIGNEDP to select signed
6332 or unsigned operation code. */
6334 static enum rtx_code
6335 get_rtx_code (enum tree_code tcode
, bool unsignedp
)
6347 code
= unsignedp
? LTU
: LT
;
6350 code
= unsignedp
? LEU
: LE
;
6353 code
= unsignedp
? GTU
: GT
;
6356 code
= unsignedp
? GEU
: GE
;
6359 case UNORDERED_EXPR
:
6390 /* Return comparison rtx for COND. Use UNSIGNEDP to select signed or
6391 unsigned operators. Do not generate compare instruction. */
6394 vector_compare_rtx (enum tree_code tcode
, tree t_op0
, tree t_op1
,
6395 bool unsignedp
, enum insn_code icode
)
6397 struct expand_operand ops
[2];
6398 rtx rtx_op0
, rtx_op1
;
6399 enum rtx_code rcode
= get_rtx_code (tcode
, unsignedp
);
6401 gcc_assert (TREE_CODE_CLASS (tcode
) == tcc_comparison
);
6403 /* Expand operands. */
6404 rtx_op0
= expand_expr (t_op0
, NULL_RTX
, TYPE_MODE (TREE_TYPE (t_op0
)),
6406 rtx_op1
= expand_expr (t_op1
, NULL_RTX
, TYPE_MODE (TREE_TYPE (t_op1
)),
6409 create_input_operand (&ops
[0], rtx_op0
, GET_MODE (rtx_op0
));
6410 create_input_operand (&ops
[1], rtx_op1
, GET_MODE (rtx_op1
));
6411 if (!maybe_legitimize_operands (icode
, 4, 2, ops
))
6413 return gen_rtx_fmt_ee (rcode
, VOIDmode
, ops
[0].value
, ops
[1].value
);
6416 /* Return true if VEC_PERM_EXPR can be expanded using SIMD extensions
6417 of the CPU. SEL may be NULL, which stands for an unknown constant. */
6420 can_vec_perm_p (enum machine_mode mode
, bool variable
,
6421 const unsigned char *sel
)
6423 enum machine_mode qimode
;
6425 /* If the target doesn't implement a vector mode for the vector type,
6426 then no operations are supported. */
6427 if (!VECTOR_MODE_P (mode
))
6432 if (direct_optab_handler (vec_perm_const_optab
, mode
) != CODE_FOR_nothing
6434 || targetm
.vectorize
.vec_perm_const_ok
== NULL
6435 || targetm
.vectorize
.vec_perm_const_ok (mode
, sel
)))
6439 if (direct_optab_handler (vec_perm_optab
, mode
) != CODE_FOR_nothing
)
6442 /* We allow fallback to a QI vector mode, and adjust the mask. */
6443 if (GET_MODE_INNER (mode
) == QImode
)
6445 qimode
= mode_for_vector (QImode
, GET_MODE_SIZE (mode
));
6446 if (!VECTOR_MODE_P (qimode
))
6449 /* ??? For completeness, we ought to check the QImode version of
6450 vec_perm_const_optab. But all users of this implicit lowering
6451 feature implement the variable vec_perm_optab. */
6452 if (direct_optab_handler (vec_perm_optab
, qimode
) == CODE_FOR_nothing
)
6455 /* In order to support the lowering of variable permutations,
6456 we need to support shifts and adds. */
6459 if (GET_MODE_UNIT_SIZE (mode
) > 2
6460 && optab_handler (ashl_optab
, mode
) == CODE_FOR_nothing
6461 && optab_handler (vashl_optab
, mode
) == CODE_FOR_nothing
)
6463 if (optab_handler (add_optab
, qimode
) == CODE_FOR_nothing
)
6470 /* A subroutine of expand_vec_perm for expanding one vec_perm insn. */
6473 expand_vec_perm_1 (enum insn_code icode
, rtx target
,
6474 rtx v0
, rtx v1
, rtx sel
)
6476 enum machine_mode tmode
= GET_MODE (target
);
6477 enum machine_mode smode
= GET_MODE (sel
);
6478 struct expand_operand ops
[4];
6480 create_output_operand (&ops
[0], target
, tmode
);
6481 create_input_operand (&ops
[3], sel
, smode
);
6483 /* Make an effort to preserve v0 == v1. The target expander is able to
6484 rely on this to determine if we're permuting a single input operand. */
6485 if (rtx_equal_p (v0
, v1
))
6487 if (!insn_operand_matches (icode
, 1, v0
))
6488 v0
= force_reg (tmode
, v0
);
6489 gcc_checking_assert (insn_operand_matches (icode
, 1, v0
));
6490 gcc_checking_assert (insn_operand_matches (icode
, 2, v0
));
6492 create_fixed_operand (&ops
[1], v0
);
6493 create_fixed_operand (&ops
[2], v0
);
6497 create_input_operand (&ops
[1], v0
, tmode
);
6498 create_input_operand (&ops
[2], v1
, tmode
);
6501 if (maybe_expand_insn (icode
, 4, ops
))
6502 return ops
[0].value
;
6506 /* Generate instructions for vec_perm optab given its mode
6507 and three operands. */
6510 expand_vec_perm (enum machine_mode mode
, rtx v0
, rtx v1
, rtx sel
, rtx target
)
6512 enum insn_code icode
;
6513 enum machine_mode qimode
;
6514 unsigned int i
, w
, e
, u
;
6515 rtx tmp
, sel_qi
= NULL
;
6518 if (!target
|| GET_MODE (target
) != mode
)
6519 target
= gen_reg_rtx (mode
);
6521 w
= GET_MODE_SIZE (mode
);
6522 e
= GET_MODE_NUNITS (mode
);
6523 u
= GET_MODE_UNIT_SIZE (mode
);
6525 /* Set QIMODE to a different vector mode with byte elements.
6526 If no such mode, or if MODE already has byte elements, use VOIDmode. */
6528 if (GET_MODE_INNER (mode
) != QImode
)
6530 qimode
= mode_for_vector (QImode
, w
);
6531 if (!VECTOR_MODE_P (qimode
))
6535 /* If the input is a constant, expand it specially. */
6536 gcc_assert (GET_MODE_CLASS (GET_MODE (sel
)) == MODE_VECTOR_INT
);
6537 if (GET_CODE (sel
) == CONST_VECTOR
)
6539 icode
= direct_optab_handler (vec_perm_const_optab
, mode
);
6540 if (icode
!= CODE_FOR_nothing
)
6542 tmp
= expand_vec_perm_1 (icode
, target
, v0
, v1
, sel
);
6547 /* Fall back to a constant byte-based permutation. */
6548 if (qimode
!= VOIDmode
)
6550 vec
= rtvec_alloc (w
);
6551 for (i
= 0; i
< e
; ++i
)
6553 unsigned int j
, this_e
;
6555 this_e
= INTVAL (CONST_VECTOR_ELT (sel
, i
));
6556 this_e
&= 2 * e
- 1;
6559 for (j
= 0; j
< u
; ++j
)
6560 RTVEC_ELT (vec
, i
* u
+ j
) = GEN_INT (this_e
+ j
);
6562 sel_qi
= gen_rtx_CONST_VECTOR (qimode
, vec
);
6564 icode
= direct_optab_handler (vec_perm_const_optab
, qimode
);
6565 if (icode
!= CODE_FOR_nothing
)
6567 tmp
= expand_vec_perm_1 (icode
, gen_lowpart (qimode
, target
),
6568 gen_lowpart (qimode
, v0
),
6569 gen_lowpart (qimode
, v1
), sel_qi
);
6571 return gen_lowpart (mode
, tmp
);
6576 /* Otherwise expand as a fully variable permuation. */
6577 icode
= direct_optab_handler (vec_perm_optab
, mode
);
6578 if (icode
!= CODE_FOR_nothing
)
6580 tmp
= expand_vec_perm_1 (icode
, target
, v0
, v1
, sel
);
6585 /* As a special case to aid several targets, lower the element-based
6586 permutation to a byte-based permutation and try again. */
6587 if (qimode
== VOIDmode
)
6589 icode
= direct_optab_handler (vec_perm_optab
, qimode
);
6590 if (icode
== CODE_FOR_nothing
)
6595 /* Multiply each element by its byte size. */
6596 enum machine_mode selmode
= GET_MODE (sel
);
6598 sel
= expand_simple_binop (selmode
, PLUS
, sel
, sel
,
6599 sel
, 0, OPTAB_DIRECT
);
6601 sel
= expand_simple_binop (selmode
, ASHIFT
, sel
,
6602 GEN_INT (exact_log2 (u
)),
6603 sel
, 0, OPTAB_DIRECT
);
6604 gcc_assert (sel
!= NULL
);
6606 /* Broadcast the low byte each element into each of its bytes. */
6607 vec
= rtvec_alloc (w
);
6608 for (i
= 0; i
< w
; ++i
)
6610 int this_e
= i
/ u
* u
;
6611 if (BYTES_BIG_ENDIAN
)
6613 RTVEC_ELT (vec
, i
) = GEN_INT (this_e
);
6615 tmp
= gen_rtx_CONST_VECTOR (qimode
, vec
);
6616 sel
= gen_lowpart (qimode
, sel
);
6617 sel
= expand_vec_perm (qimode
, sel
, sel
, tmp
, NULL
);
6618 gcc_assert (sel
!= NULL
);
6620 /* Add the byte offset to each byte element. */
6621 /* Note that the definition of the indicies here is memory ordering,
6622 so there should be no difference between big and little endian. */
6623 vec
= rtvec_alloc (w
);
6624 for (i
= 0; i
< w
; ++i
)
6625 RTVEC_ELT (vec
, i
) = GEN_INT (i
% u
);
6626 tmp
= gen_rtx_CONST_VECTOR (qimode
, vec
);
6627 sel_qi
= expand_simple_binop (qimode
, PLUS
, sel
, tmp
,
6628 sel
, 0, OPTAB_DIRECT
);
6629 gcc_assert (sel_qi
!= NULL
);
6632 tmp
= expand_vec_perm_1 (icode
, gen_lowpart (qimode
, target
),
6633 gen_lowpart (qimode
, v0
),
6634 gen_lowpart (qimode
, v1
), sel_qi
);
6636 tmp
= gen_lowpart (mode
, tmp
);
6640 /* Return insn code for a conditional operator with a comparison in
6641 mode CMODE, unsigned if UNS is true, resulting in a value of mode VMODE. */
6643 static inline enum insn_code
6644 get_vcond_icode (enum machine_mode vmode
, enum machine_mode cmode
, bool uns
)
6646 enum insn_code icode
= CODE_FOR_nothing
;
6648 icode
= convert_optab_handler (vcondu_optab
, vmode
, cmode
);
6650 icode
= convert_optab_handler (vcond_optab
, vmode
, cmode
);
6654 /* Return TRUE iff, appropriate vector insns are available
6655 for vector cond expr with vector type VALUE_TYPE and a comparison
6656 with operand vector types in CMP_OP_TYPE. */
6659 expand_vec_cond_expr_p (tree value_type
, tree cmp_op_type
)
6661 enum machine_mode value_mode
= TYPE_MODE (value_type
);
6662 enum machine_mode cmp_op_mode
= TYPE_MODE (cmp_op_type
);
6663 if (GET_MODE_SIZE (value_mode
) != GET_MODE_SIZE (cmp_op_mode
)
6664 || GET_MODE_NUNITS (value_mode
) != GET_MODE_NUNITS (cmp_op_mode
)
6665 || get_vcond_icode (TYPE_MODE (value_type
), TYPE_MODE (cmp_op_type
),
6666 TYPE_UNSIGNED (cmp_op_type
)) == CODE_FOR_nothing
)
6671 /* Generate insns for a VEC_COND_EXPR, given its TYPE and its
6675 expand_vec_cond_expr (tree vec_cond_type
, tree op0
, tree op1
, tree op2
,
6678 struct expand_operand ops
[6];
6679 enum insn_code icode
;
6680 rtx comparison
, rtx_op1
, rtx_op2
;
6681 enum machine_mode mode
= TYPE_MODE (vec_cond_type
);
6682 enum machine_mode cmp_op_mode
;
6685 enum tree_code tcode
;
6687 if (COMPARISON_CLASS_P (op0
))
6689 op0a
= TREE_OPERAND (op0
, 0);
6690 op0b
= TREE_OPERAND (op0
, 1);
6691 tcode
= TREE_CODE (op0
);
6696 gcc_assert (!TYPE_UNSIGNED (TREE_TYPE (op0
)));
6698 op0b
= build_zero_cst (TREE_TYPE (op0
));
6701 unsignedp
= TYPE_UNSIGNED (TREE_TYPE (op0a
));
6702 cmp_op_mode
= TYPE_MODE (TREE_TYPE (op0a
));
6705 gcc_assert (GET_MODE_SIZE (mode
) == GET_MODE_SIZE (cmp_op_mode
)
6706 && GET_MODE_NUNITS (mode
) == GET_MODE_NUNITS (cmp_op_mode
));
6708 icode
= get_vcond_icode (mode
, cmp_op_mode
, unsignedp
);
6709 if (icode
== CODE_FOR_nothing
)
6712 comparison
= vector_compare_rtx (tcode
, op0a
, op0b
, unsignedp
, icode
);
6713 rtx_op1
= expand_normal (op1
);
6714 rtx_op2
= expand_normal (op2
);
6716 create_output_operand (&ops
[0], target
, mode
);
6717 create_input_operand (&ops
[1], rtx_op1
, mode
);
6718 create_input_operand (&ops
[2], rtx_op2
, mode
);
6719 create_fixed_operand (&ops
[3], comparison
);
6720 create_fixed_operand (&ops
[4], XEXP (comparison
, 0));
6721 create_fixed_operand (&ops
[5], XEXP (comparison
, 1));
6722 expand_insn (icode
, 6, ops
);
6723 return ops
[0].value
;
6726 /* Return non-zero if a highpart multiply is supported of can be synthisized.
6727 For the benefit of expand_mult_highpart, the return value is 1 for direct,
6728 2 for even/odd widening, and 3 for hi/lo widening. */
6731 can_mult_highpart_p (enum machine_mode mode
, bool uns_p
)
6737 op
= uns_p
? umul_highpart_optab
: smul_highpart_optab
;
6738 if (optab_handler (op
, mode
) != CODE_FOR_nothing
)
6741 /* If the mode is an integral vector, synth from widening operations. */
6742 if (GET_MODE_CLASS (mode
) != MODE_VECTOR_INT
)
6745 nunits
= GET_MODE_NUNITS (mode
);
6746 sel
= XALLOCAVEC (unsigned char, nunits
);
6748 op
= uns_p
? vec_widen_umult_even_optab
: vec_widen_smult_even_optab
;
6749 if (optab_handler (op
, mode
) != CODE_FOR_nothing
)
6751 op
= uns_p
? vec_widen_umult_odd_optab
: vec_widen_smult_odd_optab
;
6752 if (optab_handler (op
, mode
) != CODE_FOR_nothing
)
6754 for (i
= 0; i
< nunits
; ++i
)
6755 sel
[i
] = !BYTES_BIG_ENDIAN
+ (i
& ~1) + ((i
& 1) ? nunits
: 0);
6756 if (can_vec_perm_p (mode
, false, sel
))
6761 op
= uns_p
? vec_widen_umult_hi_optab
: vec_widen_smult_hi_optab
;
6762 if (optab_handler (op
, mode
) != CODE_FOR_nothing
)
6764 op
= uns_p
? vec_widen_umult_lo_optab
: vec_widen_smult_lo_optab
;
6765 if (optab_handler (op
, mode
) != CODE_FOR_nothing
)
6767 for (i
= 0; i
< nunits
; ++i
)
6768 sel
[i
] = 2 * i
+ (BYTES_BIG_ENDIAN
? 0 : 1);
6769 if (can_vec_perm_p (mode
, false, sel
))
6777 /* Expand a highpart multiply. */
6780 expand_mult_highpart (enum machine_mode mode
, rtx op0
, rtx op1
,
6781 rtx target
, bool uns_p
)
6783 struct expand_operand eops
[3];
6784 enum insn_code icode
;
6785 int method
, i
, nunits
;
6786 enum machine_mode wmode
;
6791 method
= can_mult_highpart_p (mode
, uns_p
);
6797 tab1
= uns_p
? umul_highpart_optab
: smul_highpart_optab
;
6798 return expand_binop (mode
, tab1
, op0
, op1
, target
, uns_p
,
6801 tab1
= uns_p
? vec_widen_umult_even_optab
: vec_widen_smult_even_optab
;
6802 tab2
= uns_p
? vec_widen_umult_odd_optab
: vec_widen_smult_odd_optab
;
6805 tab1
= uns_p
? vec_widen_umult_lo_optab
: vec_widen_smult_lo_optab
;
6806 tab2
= uns_p
? vec_widen_umult_hi_optab
: vec_widen_smult_hi_optab
;
6807 if (BYTES_BIG_ENDIAN
)
6818 icode
= optab_handler (tab1
, mode
);
6819 nunits
= GET_MODE_NUNITS (mode
);
6820 wmode
= insn_data
[icode
].operand
[0].mode
;
6821 gcc_checking_assert (2 * GET_MODE_NUNITS (wmode
) == nunits
);
6822 gcc_checking_assert (GET_MODE_SIZE (wmode
) == GET_MODE_SIZE (mode
));
6824 create_output_operand (&eops
[0], gen_reg_rtx (wmode
), wmode
);
6825 create_input_operand (&eops
[1], op0
, mode
);
6826 create_input_operand (&eops
[2], op1
, mode
);
6827 expand_insn (icode
, 3, eops
);
6828 m1
= gen_lowpart (mode
, eops
[0].value
);
6830 create_output_operand (&eops
[0], gen_reg_rtx (wmode
), wmode
);
6831 create_input_operand (&eops
[1], op0
, mode
);
6832 create_input_operand (&eops
[2], op1
, mode
);
6833 expand_insn (optab_handler (tab2
, mode
), 3, eops
);
6834 m2
= gen_lowpart (mode
, eops
[0].value
);
6836 v
= rtvec_alloc (nunits
);
6839 for (i
= 0; i
< nunits
; ++i
)
6840 RTVEC_ELT (v
, i
) = GEN_INT (!BYTES_BIG_ENDIAN
+ (i
& ~1)
6841 + ((i
& 1) ? nunits
: 0));
6845 for (i
= 0; i
< nunits
; ++i
)
6846 RTVEC_ELT (v
, i
) = GEN_INT (2 * i
+ (BYTES_BIG_ENDIAN
? 0 : 1));
6848 perm
= gen_rtx_CONST_VECTOR (mode
, v
);
6850 return expand_vec_perm (mode
, m1
, m2
, perm
, target
);
6853 /* Return true if there is a compare_and_swap pattern. */
6856 can_compare_and_swap_p (enum machine_mode mode
, bool allow_libcall
)
6858 enum insn_code icode
;
6860 /* Check for __atomic_compare_and_swap. */
6861 icode
= direct_optab_handler (atomic_compare_and_swap_optab
, mode
);
6862 if (icode
!= CODE_FOR_nothing
)
6865 /* Check for __sync_compare_and_swap. */
6866 icode
= optab_handler (sync_compare_and_swap_optab
, mode
);
6867 if (icode
!= CODE_FOR_nothing
)
6869 if (allow_libcall
&& optab_libfunc (sync_compare_and_swap_optab
, mode
))
6872 /* No inline compare and swap. */
6876 /* Return true if an atomic exchange can be performed. */
6879 can_atomic_exchange_p (enum machine_mode mode
, bool allow_libcall
)
6881 enum insn_code icode
;
6883 /* Check for __atomic_exchange. */
6884 icode
= direct_optab_handler (atomic_exchange_optab
, mode
);
6885 if (icode
!= CODE_FOR_nothing
)
6888 /* Don't check __sync_test_and_set, as on some platforms that
6889 has reduced functionality. Targets that really do support
6890 a proper exchange should simply be updated to the __atomics. */
6892 return can_compare_and_swap_p (mode
, allow_libcall
);
6896 /* Helper function to find the MODE_CC set in a sync_compare_and_swap
6900 find_cc_set (rtx x
, const_rtx pat
, void *data
)
6902 if (REG_P (x
) && GET_MODE_CLASS (GET_MODE (x
)) == MODE_CC
6903 && GET_CODE (pat
) == SET
)
6905 rtx
*p_cc_reg
= (rtx
*) data
;
6906 gcc_assert (!*p_cc_reg
);
6911 /* This is a helper function for the other atomic operations. This function
6912 emits a loop that contains SEQ that iterates until a compare-and-swap
6913 operation at the end succeeds. MEM is the memory to be modified. SEQ is
6914 a set of instructions that takes a value from OLD_REG as an input and
6915 produces a value in NEW_REG as an output. Before SEQ, OLD_REG will be
6916 set to the current contents of MEM. After SEQ, a compare-and-swap will
6917 attempt to update MEM with NEW_REG. The function returns true when the
6918 loop was generated successfully. */
6921 expand_compare_and_swap_loop (rtx mem
, rtx old_reg
, rtx new_reg
, rtx seq
)
6923 enum machine_mode mode
= GET_MODE (mem
);
6924 rtx label
, cmp_reg
, success
, oldval
;
6926 /* The loop we want to generate looks like
6932 (success, cmp_reg) = compare-and-swap(mem, old_reg, new_reg)
6936 Note that we only do the plain load from memory once. Subsequent
6937 iterations use the value loaded by the compare-and-swap pattern. */
6939 label
= gen_label_rtx ();
6940 cmp_reg
= gen_reg_rtx (mode
);
6942 emit_move_insn (cmp_reg
, mem
);
6944 emit_move_insn (old_reg
, cmp_reg
);
6950 if (!expand_atomic_compare_and_swap (&success
, &oldval
, mem
, old_reg
,
6951 new_reg
, false, MEMMODEL_SEQ_CST
,
6955 if (oldval
!= cmp_reg
)
6956 emit_move_insn (cmp_reg
, oldval
);
6958 /* Mark this jump predicted not taken. */
6959 emit_cmp_and_jump_insns (success
, const0_rtx
, EQ
, const0_rtx
,
6960 GET_MODE (success
), 1, label
, 0);
6965 /* This function tries to emit an atomic_exchange intruction. VAL is written
6966 to *MEM using memory model MODEL. The previous contents of *MEM are returned,
6967 using TARGET if possible. */
6970 maybe_emit_atomic_exchange (rtx target
, rtx mem
, rtx val
, enum memmodel model
)
6972 enum machine_mode mode
= GET_MODE (mem
);
6973 enum insn_code icode
;
6975 /* If the target supports the exchange directly, great. */
6976 icode
= direct_optab_handler (atomic_exchange_optab
, mode
);
6977 if (icode
!= CODE_FOR_nothing
)
6979 struct expand_operand ops
[4];
6981 create_output_operand (&ops
[0], target
, mode
);
6982 create_fixed_operand (&ops
[1], mem
);
6983 /* VAL may have been promoted to a wider mode. Shrink it if so. */
6984 create_convert_operand_to (&ops
[2], val
, mode
, true);
6985 create_integer_operand (&ops
[3], model
);
6986 if (maybe_expand_insn (icode
, 4, ops
))
6987 return ops
[0].value
;
6993 /* This function tries to implement an atomic exchange operation using
6994 __sync_lock_test_and_set. VAL is written to *MEM using memory model MODEL.
6995 The previous contents of *MEM are returned, using TARGET if possible.
6996 Since this instructionn is an acquire barrier only, stronger memory
6997 models may require additional barriers to be emitted. */
7000 maybe_emit_sync_lock_test_and_set (rtx target
, rtx mem
, rtx val
,
7001 enum memmodel model
)
7003 enum machine_mode mode
= GET_MODE (mem
);
7004 enum insn_code icode
;
7005 rtx last_insn
= get_last_insn ();
7007 icode
= optab_handler (sync_lock_test_and_set_optab
, mode
);
7009 /* Legacy sync_lock_test_and_set is an acquire barrier. If the pattern
7010 exists, and the memory model is stronger than acquire, add a release
7011 barrier before the instruction. */
7013 if (model
== MEMMODEL_SEQ_CST
7014 || model
== MEMMODEL_RELEASE
7015 || model
== MEMMODEL_ACQ_REL
)
7016 expand_mem_thread_fence (model
);
7018 if (icode
!= CODE_FOR_nothing
)
7020 struct expand_operand ops
[3];
7021 create_output_operand (&ops
[0], target
, mode
);
7022 create_fixed_operand (&ops
[1], mem
);
7023 /* VAL may have been promoted to a wider mode. Shrink it if so. */
7024 create_convert_operand_to (&ops
[2], val
, mode
, true);
7025 if (maybe_expand_insn (icode
, 3, ops
))
7026 return ops
[0].value
;
7029 /* If an external test-and-set libcall is provided, use that instead of
7030 any external compare-and-swap that we might get from the compare-and-
7031 swap-loop expansion later. */
7032 if (!can_compare_and_swap_p (mode
, false))
7034 rtx libfunc
= optab_libfunc (sync_lock_test_and_set_optab
, mode
);
7035 if (libfunc
!= NULL
)
7039 addr
= convert_memory_address (ptr_mode
, XEXP (mem
, 0));
7040 return emit_library_call_value (libfunc
, NULL_RTX
, LCT_NORMAL
,
7041 mode
, 2, addr
, ptr_mode
,
7046 /* If the test_and_set can't be emitted, eliminate any barrier that might
7047 have been emitted. */
7048 delete_insns_since (last_insn
);
7052 /* This function tries to implement an atomic exchange operation using a
7053 compare_and_swap loop. VAL is written to *MEM. The previous contents of
7054 *MEM are returned, using TARGET if possible. No memory model is required
7055 since a compare_and_swap loop is seq-cst. */
7058 maybe_emit_compare_and_swap_exchange_loop (rtx target
, rtx mem
, rtx val
)
7060 enum machine_mode mode
= GET_MODE (mem
);
7062 if (can_compare_and_swap_p (mode
, true))
7064 if (!target
|| !register_operand (target
, mode
))
7065 target
= gen_reg_rtx (mode
);
7066 if (GET_MODE (val
) != VOIDmode
&& GET_MODE (val
) != mode
)
7067 val
= convert_modes (mode
, GET_MODE (val
), val
, 1);
7068 if (expand_compare_and_swap_loop (mem
, target
, val
, NULL_RTX
))
7075 /* This function tries to implement an atomic test-and-set operation
7076 using the atomic_test_and_set instruction pattern. A boolean value
7077 is returned from the operation, using TARGET if possible. */
7079 #ifndef HAVE_atomic_test_and_set
7080 #define HAVE_atomic_test_and_set 0
7081 #define CODE_FOR_atomic_test_and_set CODE_FOR_nothing
7085 maybe_emit_atomic_test_and_set (rtx target
, rtx mem
, enum memmodel model
)
7087 enum machine_mode pat_bool_mode
;
7088 struct expand_operand ops
[3];
7090 if (!HAVE_atomic_test_and_set
)
7093 /* While we always get QImode from __atomic_test_and_set, we get
7094 other memory modes from __sync_lock_test_and_set. Note that we
7095 use no endian adjustment here. This matches the 4.6 behavior
7096 in the Sparc backend. */
7098 (insn_data
[CODE_FOR_atomic_test_and_set
].operand
[1].mode
== QImode
);
7099 if (GET_MODE (mem
) != QImode
)
7100 mem
= adjust_address_nv (mem
, QImode
, 0);
7102 pat_bool_mode
= insn_data
[CODE_FOR_atomic_test_and_set
].operand
[0].mode
;
7103 create_output_operand (&ops
[0], target
, pat_bool_mode
);
7104 create_fixed_operand (&ops
[1], mem
);
7105 create_integer_operand (&ops
[2], model
);
7107 if (maybe_expand_insn (CODE_FOR_atomic_test_and_set
, 3, ops
))
7108 return ops
[0].value
;
7112 /* This function expands the legacy _sync_lock test_and_set operation which is
7113 generally an atomic exchange. Some limited targets only allow the
7114 constant 1 to be stored. This is an ACQUIRE operation.
7116 TARGET is an optional place to stick the return value.
7117 MEM is where VAL is stored. */
7120 expand_sync_lock_test_and_set (rtx target
, rtx mem
, rtx val
)
7124 /* Try an atomic_exchange first. */
7125 ret
= maybe_emit_atomic_exchange (target
, mem
, val
, MEMMODEL_ACQUIRE
);
7129 ret
= maybe_emit_sync_lock_test_and_set (target
, mem
, val
, MEMMODEL_ACQUIRE
);
7133 ret
= maybe_emit_compare_and_swap_exchange_loop (target
, mem
, val
);
7137 /* If there are no other options, try atomic_test_and_set if the value
7138 being stored is 1. */
7139 if (val
== const1_rtx
)
7140 ret
= maybe_emit_atomic_test_and_set (target
, mem
, MEMMODEL_ACQUIRE
);
7145 /* This function expands the atomic test_and_set operation:
7146 atomically store a boolean TRUE into MEM and return the previous value.
7148 MEMMODEL is the memory model variant to use.
7149 TARGET is an optional place to stick the return value. */
7152 expand_atomic_test_and_set (rtx target
, rtx mem
, enum memmodel model
)
7154 enum machine_mode mode
= GET_MODE (mem
);
7155 rtx ret
, trueval
, subtarget
;
7157 ret
= maybe_emit_atomic_test_and_set (target
, mem
, model
);
7161 /* Be binary compatible with non-default settings of trueval, and different
7162 cpu revisions. E.g. one revision may have atomic-test-and-set, but
7163 another only has atomic-exchange. */
7164 if (targetm
.atomic_test_and_set_trueval
== 1)
7166 trueval
= const1_rtx
;
7167 subtarget
= target
? target
: gen_reg_rtx (mode
);
7171 trueval
= gen_int_mode (targetm
.atomic_test_and_set_trueval
, mode
);
7172 subtarget
= gen_reg_rtx (mode
);
7175 /* Try the atomic-exchange optab... */
7176 ret
= maybe_emit_atomic_exchange (subtarget
, mem
, trueval
, model
);
7178 /* ... then an atomic-compare-and-swap loop ... */
7180 ret
= maybe_emit_compare_and_swap_exchange_loop (subtarget
, mem
, trueval
);
7182 /* ... before trying the vaguely defined legacy lock_test_and_set. */
7184 ret
= maybe_emit_sync_lock_test_and_set (subtarget
, mem
, trueval
, model
);
7186 /* Recall that the legacy lock_test_and_set optab was allowed to do magic
7187 things with the value 1. Thus we try again without trueval. */
7188 if (!ret
&& targetm
.atomic_test_and_set_trueval
!= 1)
7189 ret
= maybe_emit_sync_lock_test_and_set (subtarget
, mem
, const1_rtx
, model
);
7191 /* Failing all else, assume a single threaded environment and simply
7192 perform the operation. */
7195 emit_move_insn (subtarget
, mem
);
7196 emit_move_insn (mem
, trueval
);
7200 /* Recall that have to return a boolean value; rectify if trueval
7201 is not exactly one. */
7202 if (targetm
.atomic_test_and_set_trueval
!= 1)
7203 ret
= emit_store_flag_force (target
, NE
, ret
, const0_rtx
, mode
, 0, 1);
7208 /* This function expands the atomic exchange operation:
7209 atomically store VAL in MEM and return the previous value in MEM.
7211 MEMMODEL is the memory model variant to use.
7212 TARGET is an optional place to stick the return value. */
7215 expand_atomic_exchange (rtx target
, rtx mem
, rtx val
, enum memmodel model
)
7219 ret
= maybe_emit_atomic_exchange (target
, mem
, val
, model
);
7221 /* Next try a compare-and-swap loop for the exchange. */
7223 ret
= maybe_emit_compare_and_swap_exchange_loop (target
, mem
, val
);
7228 /* This function expands the atomic compare exchange operation:
7230 *PTARGET_BOOL is an optional place to store the boolean success/failure.
7231 *PTARGET_OVAL is an optional place to store the old value from memory.
7232 Both target parameters may be NULL to indicate that we do not care about
7233 that return value. Both target parameters are updated on success to
7234 the actual location of the corresponding result.
7236 MEMMODEL is the memory model variant to use.
7238 The return value of the function is true for success. */
7241 expand_atomic_compare_and_swap (rtx
*ptarget_bool
, rtx
*ptarget_oval
,
7242 rtx mem
, rtx expected
, rtx desired
,
7243 bool is_weak
, enum memmodel succ_model
,
7244 enum memmodel fail_model
)
7246 enum machine_mode mode
= GET_MODE (mem
);
7247 struct expand_operand ops
[8];
7248 enum insn_code icode
;
7249 rtx target_oval
, target_bool
= NULL_RTX
;
7252 /* Load expected into a register for the compare and swap. */
7253 if (MEM_P (expected
))
7254 expected
= copy_to_reg (expected
);
7256 /* Make sure we always have some place to put the return oldval.
7257 Further, make sure that place is distinct from the input expected,
7258 just in case we need that path down below. */
7259 if (ptarget_oval
== NULL
7260 || (target_oval
= *ptarget_oval
) == NULL
7261 || reg_overlap_mentioned_p (expected
, target_oval
))
7262 target_oval
= gen_reg_rtx (mode
);
7264 icode
= direct_optab_handler (atomic_compare_and_swap_optab
, mode
);
7265 if (icode
!= CODE_FOR_nothing
)
7267 enum machine_mode bool_mode
= insn_data
[icode
].operand
[0].mode
;
7269 /* Make sure we always have a place for the bool operand. */
7270 if (ptarget_bool
== NULL
7271 || (target_bool
= *ptarget_bool
) == NULL
7272 || GET_MODE (target_bool
) != bool_mode
)
7273 target_bool
= gen_reg_rtx (bool_mode
);
7275 /* Emit the compare_and_swap. */
7276 create_output_operand (&ops
[0], target_bool
, bool_mode
);
7277 create_output_operand (&ops
[1], target_oval
, mode
);
7278 create_fixed_operand (&ops
[2], mem
);
7279 create_convert_operand_to (&ops
[3], expected
, mode
, true);
7280 create_convert_operand_to (&ops
[4], desired
, mode
, true);
7281 create_integer_operand (&ops
[5], is_weak
);
7282 create_integer_operand (&ops
[6], succ_model
);
7283 create_integer_operand (&ops
[7], fail_model
);
7284 expand_insn (icode
, 8, ops
);
7286 /* Return success/failure. */
7287 target_bool
= ops
[0].value
;
7288 target_oval
= ops
[1].value
;
7292 /* Otherwise fall back to the original __sync_val_compare_and_swap
7293 which is always seq-cst. */
7294 icode
= optab_handler (sync_compare_and_swap_optab
, mode
);
7295 if (icode
!= CODE_FOR_nothing
)
7299 create_output_operand (&ops
[0], target_oval
, mode
);
7300 create_fixed_operand (&ops
[1], mem
);
7301 create_convert_operand_to (&ops
[2], expected
, mode
, true);
7302 create_convert_operand_to (&ops
[3], desired
, mode
, true);
7303 if (!maybe_expand_insn (icode
, 4, ops
))
7306 target_oval
= ops
[0].value
;
7308 /* If the caller isn't interested in the boolean return value,
7309 skip the computation of it. */
7310 if (ptarget_bool
== NULL
)
7313 /* Otherwise, work out if the compare-and-swap succeeded. */
7315 if (have_insn_for (COMPARE
, CCmode
))
7316 note_stores (PATTERN (get_last_insn ()), find_cc_set
, &cc_reg
);
7319 target_bool
= emit_store_flag_force (target_bool
, EQ
, cc_reg
,
7320 const0_rtx
, VOIDmode
, 0, 1);
7323 goto success_bool_from_val
;
7326 /* Also check for library support for __sync_val_compare_and_swap. */
7327 libfunc
= optab_libfunc (sync_compare_and_swap_optab
, mode
);
7328 if (libfunc
!= NULL
)
7330 rtx addr
= convert_memory_address (ptr_mode
, XEXP (mem
, 0));
7331 target_oval
= emit_library_call_value (libfunc
, NULL_RTX
, LCT_NORMAL
,
7332 mode
, 3, addr
, ptr_mode
,
7333 expected
, mode
, desired
, mode
);
7335 /* Compute the boolean return value only if requested. */
7337 goto success_bool_from_val
;
7345 success_bool_from_val
:
7346 target_bool
= emit_store_flag_force (target_bool
, EQ
, target_oval
,
7347 expected
, VOIDmode
, 1, 1);
7349 /* Make sure that the oval output winds up where the caller asked. */
7351 *ptarget_oval
= target_oval
;
7353 *ptarget_bool
= target_bool
;
7357 /* Generate asm volatile("" : : : "memory") as the memory barrier. */
7360 expand_asm_memory_barrier (void)
7364 asm_op
= gen_rtx_ASM_OPERANDS (VOIDmode
, empty_string
, empty_string
, 0,
7365 rtvec_alloc (0), rtvec_alloc (0),
7366 rtvec_alloc (0), UNKNOWN_LOCATION
);
7367 MEM_VOLATILE_P (asm_op
) = 1;
7369 clob
= gen_rtx_SCRATCH (VOIDmode
);
7370 clob
= gen_rtx_MEM (BLKmode
, clob
);
7371 clob
= gen_rtx_CLOBBER (VOIDmode
, clob
);
7373 emit_insn (gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, asm_op
, clob
)));
7376 /* This routine will either emit the mem_thread_fence pattern or issue a
7377 sync_synchronize to generate a fence for memory model MEMMODEL. */
7379 #ifndef HAVE_mem_thread_fence
7380 # define HAVE_mem_thread_fence 0
7381 # define gen_mem_thread_fence(x) (gcc_unreachable (), NULL_RTX)
7383 #ifndef HAVE_memory_barrier
7384 # define HAVE_memory_barrier 0
7385 # define gen_memory_barrier() (gcc_unreachable (), NULL_RTX)
7389 expand_mem_thread_fence (enum memmodel model
)
7391 if (HAVE_mem_thread_fence
)
7392 emit_insn (gen_mem_thread_fence (GEN_INT (model
)));
7393 else if (model
!= MEMMODEL_RELAXED
)
7395 if (HAVE_memory_barrier
)
7396 emit_insn (gen_memory_barrier ());
7397 else if (synchronize_libfunc
!= NULL_RTX
)
7398 emit_library_call (synchronize_libfunc
, LCT_NORMAL
, VOIDmode
, 0);
7400 expand_asm_memory_barrier ();
7404 /* This routine will either emit the mem_signal_fence pattern or issue a
7405 sync_synchronize to generate a fence for memory model MEMMODEL. */
7407 #ifndef HAVE_mem_signal_fence
7408 # define HAVE_mem_signal_fence 0
7409 # define gen_mem_signal_fence(x) (gcc_unreachable (), NULL_RTX)
7413 expand_mem_signal_fence (enum memmodel model
)
7415 if (HAVE_mem_signal_fence
)
7416 emit_insn (gen_mem_signal_fence (GEN_INT (model
)));
7417 else if (model
!= MEMMODEL_RELAXED
)
7419 /* By default targets are coherent between a thread and the signal
7420 handler running on the same thread. Thus this really becomes a
7421 compiler barrier, in that stores must not be sunk past
7422 (or raised above) a given point. */
7423 expand_asm_memory_barrier ();
7427 /* This function expands the atomic load operation:
7428 return the atomically loaded value in MEM.
7430 MEMMODEL is the memory model variant to use.
7431 TARGET is an option place to stick the return value. */
7434 expand_atomic_load (rtx target
, rtx mem
, enum memmodel model
)
7436 enum machine_mode mode
= GET_MODE (mem
);
7437 enum insn_code icode
;
7439 /* If the target supports the load directly, great. */
7440 icode
= direct_optab_handler (atomic_load_optab
, mode
);
7441 if (icode
!= CODE_FOR_nothing
)
7443 struct expand_operand ops
[3];
7445 create_output_operand (&ops
[0], target
, mode
);
7446 create_fixed_operand (&ops
[1], mem
);
7447 create_integer_operand (&ops
[2], model
);
7448 if (maybe_expand_insn (icode
, 3, ops
))
7449 return ops
[0].value
;
7452 /* If the size of the object is greater than word size on this target,
7453 then we assume that a load will not be atomic. */
7454 if (GET_MODE_PRECISION (mode
) > BITS_PER_WORD
)
7456 /* Issue val = compare_and_swap (mem, 0, 0).
7457 This may cause the occasional harmless store of 0 when the value is
7458 already 0, but it seems to be OK according to the standards guys. */
7459 if (expand_atomic_compare_and_swap (NULL
, &target
, mem
, const0_rtx
,
7460 const0_rtx
, false, model
, model
))
7463 /* Otherwise there is no atomic load, leave the library call. */
7467 /* Otherwise assume loads are atomic, and emit the proper barriers. */
7468 if (!target
|| target
== const0_rtx
)
7469 target
= gen_reg_rtx (mode
);
7471 /* For SEQ_CST, emit a barrier before the load. */
7472 if (model
== MEMMODEL_SEQ_CST
)
7473 expand_mem_thread_fence (model
);
7475 emit_move_insn (target
, mem
);
7477 /* Emit the appropriate barrier after the load. */
7478 expand_mem_thread_fence (model
);
7483 /* This function expands the atomic store operation:
7484 Atomically store VAL in MEM.
7485 MEMMODEL is the memory model variant to use.
7486 USE_RELEASE is true if __sync_lock_release can be used as a fall back.
7487 function returns const0_rtx if a pattern was emitted. */
7490 expand_atomic_store (rtx mem
, rtx val
, enum memmodel model
, bool use_release
)
7492 enum machine_mode mode
= GET_MODE (mem
);
7493 enum insn_code icode
;
7494 struct expand_operand ops
[3];
7496 /* If the target supports the store directly, great. */
7497 icode
= direct_optab_handler (atomic_store_optab
, mode
);
7498 if (icode
!= CODE_FOR_nothing
)
7500 create_fixed_operand (&ops
[0], mem
);
7501 create_input_operand (&ops
[1], val
, mode
);
7502 create_integer_operand (&ops
[2], model
);
7503 if (maybe_expand_insn (icode
, 3, ops
))
7507 /* If using __sync_lock_release is a viable alternative, try it. */
7510 icode
= direct_optab_handler (sync_lock_release_optab
, mode
);
7511 if (icode
!= CODE_FOR_nothing
)
7513 create_fixed_operand (&ops
[0], mem
);
7514 create_input_operand (&ops
[1], const0_rtx
, mode
);
7515 if (maybe_expand_insn (icode
, 2, ops
))
7517 /* lock_release is only a release barrier. */
7518 if (model
== MEMMODEL_SEQ_CST
)
7519 expand_mem_thread_fence (model
);
7525 /* If the size of the object is greater than word size on this target,
7526 a default store will not be atomic, Try a mem_exchange and throw away
7527 the result. If that doesn't work, don't do anything. */
7528 if (GET_MODE_PRECISION(mode
) > BITS_PER_WORD
)
7530 rtx target
= maybe_emit_atomic_exchange (NULL_RTX
, mem
, val
, model
);
7532 target
= maybe_emit_compare_and_swap_exchange_loop (NULL_RTX
, mem
, val
);
7539 /* Otherwise assume stores are atomic, and emit the proper barriers. */
7540 expand_mem_thread_fence (model
);
7542 emit_move_insn (mem
, val
);
7544 /* For SEQ_CST, also emit a barrier after the store. */
7545 if (model
== MEMMODEL_SEQ_CST
)
7546 expand_mem_thread_fence (model
);
7552 /* Structure containing the pointers and values required to process the
7553 various forms of the atomic_fetch_op and atomic_op_fetch builtins. */
7555 struct atomic_op_functions
7557 direct_optab mem_fetch_before
;
7558 direct_optab mem_fetch_after
;
7559 direct_optab mem_no_result
;
7562 direct_optab no_result
;
7563 enum rtx_code reverse_code
;
7567 /* Fill in structure pointed to by OP with the various optab entries for an
7568 operation of type CODE. */
7571 get_atomic_op_for_code (struct atomic_op_functions
*op
, enum rtx_code code
)
7573 gcc_assert (op
!= NULL
);
7575 /* If SWITCHABLE_TARGET is defined, then subtargets can be switched
7576 in the source code during compilation, and the optab entries are not
7577 computable until runtime. Fill in the values at runtime. */
7581 op
->mem_fetch_before
= atomic_fetch_add_optab
;
7582 op
->mem_fetch_after
= atomic_add_fetch_optab
;
7583 op
->mem_no_result
= atomic_add_optab
;
7584 op
->fetch_before
= sync_old_add_optab
;
7585 op
->fetch_after
= sync_new_add_optab
;
7586 op
->no_result
= sync_add_optab
;
7587 op
->reverse_code
= MINUS
;
7590 op
->mem_fetch_before
= atomic_fetch_sub_optab
;
7591 op
->mem_fetch_after
= atomic_sub_fetch_optab
;
7592 op
->mem_no_result
= atomic_sub_optab
;
7593 op
->fetch_before
= sync_old_sub_optab
;
7594 op
->fetch_after
= sync_new_sub_optab
;
7595 op
->no_result
= sync_sub_optab
;
7596 op
->reverse_code
= PLUS
;
7599 op
->mem_fetch_before
= atomic_fetch_xor_optab
;
7600 op
->mem_fetch_after
= atomic_xor_fetch_optab
;
7601 op
->mem_no_result
= atomic_xor_optab
;
7602 op
->fetch_before
= sync_old_xor_optab
;
7603 op
->fetch_after
= sync_new_xor_optab
;
7604 op
->no_result
= sync_xor_optab
;
7605 op
->reverse_code
= XOR
;
7608 op
->mem_fetch_before
= atomic_fetch_and_optab
;
7609 op
->mem_fetch_after
= atomic_and_fetch_optab
;
7610 op
->mem_no_result
= atomic_and_optab
;
7611 op
->fetch_before
= sync_old_and_optab
;
7612 op
->fetch_after
= sync_new_and_optab
;
7613 op
->no_result
= sync_and_optab
;
7614 op
->reverse_code
= UNKNOWN
;
7617 op
->mem_fetch_before
= atomic_fetch_or_optab
;
7618 op
->mem_fetch_after
= atomic_or_fetch_optab
;
7619 op
->mem_no_result
= atomic_or_optab
;
7620 op
->fetch_before
= sync_old_ior_optab
;
7621 op
->fetch_after
= sync_new_ior_optab
;
7622 op
->no_result
= sync_ior_optab
;
7623 op
->reverse_code
= UNKNOWN
;
7626 op
->mem_fetch_before
= atomic_fetch_nand_optab
;
7627 op
->mem_fetch_after
= atomic_nand_fetch_optab
;
7628 op
->mem_no_result
= atomic_nand_optab
;
7629 op
->fetch_before
= sync_old_nand_optab
;
7630 op
->fetch_after
= sync_new_nand_optab
;
7631 op
->no_result
= sync_nand_optab
;
7632 op
->reverse_code
= UNKNOWN
;
7639 /* See if there is a more optimal way to implement the operation "*MEM CODE VAL"
7640 using memory order MODEL. If AFTER is true the operation needs to return
7641 the value of *MEM after the operation, otherwise the previous value.
7642 TARGET is an optional place to place the result. The result is unused if
7644 Return the result if there is a better sequence, otherwise NULL_RTX. */
7647 maybe_optimize_fetch_op (rtx target
, rtx mem
, rtx val
, enum rtx_code code
,
7648 enum memmodel model
, bool after
)
7650 /* If the value is prefetched, or not used, it may be possible to replace
7651 the sequence with a native exchange operation. */
7652 if (!after
|| target
== const0_rtx
)
7654 /* fetch_and (&x, 0, m) can be replaced with exchange (&x, 0, m). */
7655 if (code
== AND
&& val
== const0_rtx
)
7657 if (target
== const0_rtx
)
7658 target
= gen_reg_rtx (GET_MODE (mem
));
7659 return maybe_emit_atomic_exchange (target
, mem
, val
, model
);
7662 /* fetch_or (&x, -1, m) can be replaced with exchange (&x, -1, m). */
7663 if (code
== IOR
&& val
== constm1_rtx
)
7665 if (target
== const0_rtx
)
7666 target
= gen_reg_rtx (GET_MODE (mem
));
7667 return maybe_emit_atomic_exchange (target
, mem
, val
, model
);
7674 /* Try to emit an instruction for a specific operation varaition.
7675 OPTAB contains the OP functions.
7676 TARGET is an optional place to return the result. const0_rtx means unused.
7677 MEM is the memory location to operate on.
7678 VAL is the value to use in the operation.
7679 USE_MEMMODEL is TRUE if the variation with a memory model should be tried.
7680 MODEL is the memory model, if used.
7681 AFTER is true if the returned result is the value after the operation. */
7684 maybe_emit_op (const struct atomic_op_functions
*optab
, rtx target
, rtx mem
,
7685 rtx val
, bool use_memmodel
, enum memmodel model
, bool after
)
7687 enum machine_mode mode
= GET_MODE (mem
);
7688 struct expand_operand ops
[4];
7689 enum insn_code icode
;
7693 /* Check to see if there is a result returned. */
7694 if (target
== const0_rtx
)
7698 icode
= direct_optab_handler (optab
->mem_no_result
, mode
);
7699 create_integer_operand (&ops
[2], model
);
7704 icode
= direct_optab_handler (optab
->no_result
, mode
);
7708 /* Otherwise, we need to generate a result. */
7713 icode
= direct_optab_handler (after
? optab
->mem_fetch_after
7714 : optab
->mem_fetch_before
, mode
);
7715 create_integer_operand (&ops
[3], model
);
7720 icode
= optab_handler (after
? optab
->fetch_after
7721 : optab
->fetch_before
, mode
);
7724 create_output_operand (&ops
[op_counter
++], target
, mode
);
7726 if (icode
== CODE_FOR_nothing
)
7729 create_fixed_operand (&ops
[op_counter
++], mem
);
7730 /* VAL may have been promoted to a wider mode. Shrink it if so. */
7731 create_convert_operand_to (&ops
[op_counter
++], val
, mode
, true);
7733 if (maybe_expand_insn (icode
, num_ops
, ops
))
7734 return (target
== const0_rtx
? const0_rtx
: ops
[0].value
);
7740 /* This function expands an atomic fetch_OP or OP_fetch operation:
7741 TARGET is an option place to stick the return value. const0_rtx indicates
7742 the result is unused.
7743 atomically fetch MEM, perform the operation with VAL and return it to MEM.
7744 CODE is the operation being performed (OP)
7745 MEMMODEL is the memory model variant to use.
7746 AFTER is true to return the result of the operation (OP_fetch).
7747 AFTER is false to return the value before the operation (fetch_OP).
7749 This function will *only* generate instructions if there is a direct
7750 optab. No compare and swap loops or libcalls will be generated. */
7753 expand_atomic_fetch_op_no_fallback (rtx target
, rtx mem
, rtx val
,
7754 enum rtx_code code
, enum memmodel model
,
7757 enum machine_mode mode
= GET_MODE (mem
);
7758 struct atomic_op_functions optab
;
7760 bool unused_result
= (target
== const0_rtx
);
7762 get_atomic_op_for_code (&optab
, code
);
7764 /* Check to see if there are any better instructions. */
7765 result
= maybe_optimize_fetch_op (target
, mem
, val
, code
, model
, after
);
7769 /* Check for the case where the result isn't used and try those patterns. */
7772 /* Try the memory model variant first. */
7773 result
= maybe_emit_op (&optab
, target
, mem
, val
, true, model
, true);
7777 /* Next try the old style withuot a memory model. */
7778 result
= maybe_emit_op (&optab
, target
, mem
, val
, false, model
, true);
7782 /* There is no no-result pattern, so try patterns with a result. */
7786 /* Try the __atomic version. */
7787 result
= maybe_emit_op (&optab
, target
, mem
, val
, true, model
, after
);
7791 /* Try the older __sync version. */
7792 result
= maybe_emit_op (&optab
, target
, mem
, val
, false, model
, after
);
7796 /* If the fetch value can be calculated from the other variation of fetch,
7797 try that operation. */
7798 if (after
|| unused_result
|| optab
.reverse_code
!= UNKNOWN
)
7800 /* Try the __atomic version, then the older __sync version. */
7801 result
= maybe_emit_op (&optab
, target
, mem
, val
, true, model
, !after
);
7803 result
= maybe_emit_op (&optab
, target
, mem
, val
, false, model
, !after
);
7807 /* If the result isn't used, no need to do compensation code. */
7811 /* Issue compensation code. Fetch_after == fetch_before OP val.
7812 Fetch_before == after REVERSE_OP val. */
7814 code
= optab
.reverse_code
;
7817 result
= expand_simple_binop (mode
, AND
, result
, val
, NULL_RTX
,
7818 true, OPTAB_LIB_WIDEN
);
7819 result
= expand_simple_unop (mode
, NOT
, result
, target
, true);
7822 result
= expand_simple_binop (mode
, code
, result
, val
, target
,
7823 true, OPTAB_LIB_WIDEN
);
7828 /* No direct opcode can be generated. */
7834 /* This function expands an atomic fetch_OP or OP_fetch operation:
7835 TARGET is an option place to stick the return value. const0_rtx indicates
7836 the result is unused.
7837 atomically fetch MEM, perform the operation with VAL and return it to MEM.
7838 CODE is the operation being performed (OP)
7839 MEMMODEL is the memory model variant to use.
7840 AFTER is true to return the result of the operation (OP_fetch).
7841 AFTER is false to return the value before the operation (fetch_OP). */
7843 expand_atomic_fetch_op (rtx target
, rtx mem
, rtx val
, enum rtx_code code
,
7844 enum memmodel model
, bool after
)
7846 enum machine_mode mode
= GET_MODE (mem
);
7848 bool unused_result
= (target
== const0_rtx
);
7850 result
= expand_atomic_fetch_op_no_fallback (target
, mem
, val
, code
, model
,
7856 /* Add/sub can be implemented by doing the reverse operation with -(val). */
7857 if (code
== PLUS
|| code
== MINUS
)
7860 enum rtx_code reverse
= (code
== PLUS
? MINUS
: PLUS
);
7863 tmp
= expand_simple_unop (mode
, NEG
, val
, NULL_RTX
, true);
7864 result
= expand_atomic_fetch_op_no_fallback (target
, mem
, tmp
, reverse
,
7868 /* PLUS worked so emit the insns and return. */
7875 /* PLUS did not work, so throw away the negation code and continue. */
7879 /* Try the __sync libcalls only if we can't do compare-and-swap inline. */
7880 if (!can_compare_and_swap_p (mode
, false))
7884 enum rtx_code orig_code
= code
;
7885 struct atomic_op_functions optab
;
7887 get_atomic_op_for_code (&optab
, code
);
7888 libfunc
= optab_libfunc (after
? optab
.fetch_after
7889 : optab
.fetch_before
, mode
);
7891 && (after
|| unused_result
|| optab
.reverse_code
!= UNKNOWN
))
7895 code
= optab
.reverse_code
;
7896 libfunc
= optab_libfunc (after
? optab
.fetch_before
7897 : optab
.fetch_after
, mode
);
7899 if (libfunc
!= NULL
)
7901 rtx addr
= convert_memory_address (ptr_mode
, XEXP (mem
, 0));
7902 result
= emit_library_call_value (libfunc
, NULL
, LCT_NORMAL
, mode
,
7903 2, addr
, ptr_mode
, val
, mode
);
7905 if (!unused_result
&& fixup
)
7906 result
= expand_simple_binop (mode
, code
, result
, val
, target
,
7907 true, OPTAB_LIB_WIDEN
);
7911 /* We need the original code for any further attempts. */
7915 /* If nothing else has succeeded, default to a compare and swap loop. */
7916 if (can_compare_and_swap_p (mode
, true))
7919 rtx t0
= gen_reg_rtx (mode
), t1
;
7923 /* If the result is used, get a register for it. */
7926 if (!target
|| !register_operand (target
, mode
))
7927 target
= gen_reg_rtx (mode
);
7928 /* If fetch_before, copy the value now. */
7930 emit_move_insn (target
, t0
);
7933 target
= const0_rtx
;
7938 t1
= expand_simple_binop (mode
, AND
, t1
, val
, NULL_RTX
,
7939 true, OPTAB_LIB_WIDEN
);
7940 t1
= expand_simple_unop (mode
, code
, t1
, NULL_RTX
, true);
7943 t1
= expand_simple_binop (mode
, code
, t1
, val
, NULL_RTX
, true,
7946 /* For after, copy the value now. */
7947 if (!unused_result
&& after
)
7948 emit_move_insn (target
, t1
);
7949 insn
= get_insns ();
7952 if (t1
!= NULL
&& expand_compare_and_swap_loop (mem
, t0
, t1
, insn
))
7959 /* Return true if OPERAND is suitable for operand number OPNO of
7960 instruction ICODE. */
7963 insn_operand_matches (enum insn_code icode
, unsigned int opno
, rtx operand
)
7965 return (!insn_data
[(int) icode
].operand
[opno
].predicate
7966 || (insn_data
[(int) icode
].operand
[opno
].predicate
7967 (operand
, insn_data
[(int) icode
].operand
[opno
].mode
)));
7970 /* TARGET is a target of a multiword operation that we are going to
7971 implement as a series of word-mode operations. Return true if
7972 TARGET is suitable for this purpose. */
7975 valid_multiword_target_p (rtx target
)
7977 enum machine_mode mode
;
7980 mode
= GET_MODE (target
);
7981 for (i
= 0; i
< GET_MODE_SIZE (mode
); i
+= UNITS_PER_WORD
)
7982 if (!validate_subreg (word_mode
, mode
, target
, i
))
7987 /* Like maybe_legitimize_operand, but do not change the code of the
7988 current rtx value. */
7991 maybe_legitimize_operand_same_code (enum insn_code icode
, unsigned int opno
,
7992 struct expand_operand
*op
)
7994 /* See if the operand matches in its current form. */
7995 if (insn_operand_matches (icode
, opno
, op
->value
))
7998 /* If the operand is a memory whose address has no side effects,
7999 try forcing the address into a non-virtual pseudo register.
8000 The check for side effects is important because copy_to_mode_reg
8001 cannot handle things like auto-modified addresses. */
8002 if (insn_data
[(int) icode
].operand
[opno
].allows_mem
&& MEM_P (op
->value
))
8007 addr
= XEXP (mem
, 0);
8008 if (!(REG_P (addr
) && REGNO (addr
) > LAST_VIRTUAL_REGISTER
)
8009 && !side_effects_p (addr
))
8012 enum machine_mode mode
;
8014 last
= get_last_insn ();
8015 mode
= get_address_mode (mem
);
8016 mem
= replace_equiv_address (mem
, copy_to_mode_reg (mode
, addr
));
8017 if (insn_operand_matches (icode
, opno
, mem
))
8022 delete_insns_since (last
);
8029 /* Try to make OP match operand OPNO of instruction ICODE. Return true
8030 on success, storing the new operand value back in OP. */
8033 maybe_legitimize_operand (enum insn_code icode
, unsigned int opno
,
8034 struct expand_operand
*op
)
8036 enum machine_mode mode
, imode
;
8037 bool old_volatile_ok
, result
;
8043 old_volatile_ok
= volatile_ok
;
8045 result
= maybe_legitimize_operand_same_code (icode
, opno
, op
);
8046 volatile_ok
= old_volatile_ok
;
8050 gcc_assert (mode
!= VOIDmode
);
8052 && op
->value
!= const0_rtx
8053 && GET_MODE (op
->value
) == mode
8054 && maybe_legitimize_operand_same_code (icode
, opno
, op
))
8057 op
->value
= gen_reg_rtx (mode
);
8062 gcc_assert (mode
!= VOIDmode
);
8063 gcc_assert (GET_MODE (op
->value
) == VOIDmode
8064 || GET_MODE (op
->value
) == mode
);
8065 if (maybe_legitimize_operand_same_code (icode
, opno
, op
))
8068 op
->value
= copy_to_mode_reg (mode
, op
->value
);
8071 case EXPAND_CONVERT_TO
:
8072 gcc_assert (mode
!= VOIDmode
);
8073 op
->value
= convert_to_mode (mode
, op
->value
, op
->unsigned_p
);
8076 case EXPAND_CONVERT_FROM
:
8077 if (GET_MODE (op
->value
) != VOIDmode
)
8078 mode
= GET_MODE (op
->value
);
8080 /* The caller must tell us what mode this value has. */
8081 gcc_assert (mode
!= VOIDmode
);
8083 imode
= insn_data
[(int) icode
].operand
[opno
].mode
;
8084 if (imode
!= VOIDmode
&& imode
!= mode
)
8086 op
->value
= convert_modes (imode
, mode
, op
->value
, op
->unsigned_p
);
8091 case EXPAND_ADDRESS
:
8092 gcc_assert (mode
!= VOIDmode
);
8093 op
->value
= convert_memory_address (mode
, op
->value
);
8096 case EXPAND_INTEGER
:
8097 mode
= insn_data
[(int) icode
].operand
[opno
].mode
;
8098 if (mode
!= VOIDmode
&& const_int_operand (op
->value
, mode
))
8102 return insn_operand_matches (icode
, opno
, op
->value
);
8105 /* Make OP describe an input operand that should have the same value
8106 as VALUE, after any mode conversion that the target might request.
8107 TYPE is the type of VALUE. */
8110 create_convert_operand_from_type (struct expand_operand
*op
,
8111 rtx value
, tree type
)
8113 create_convert_operand_from (op
, value
, TYPE_MODE (type
),
8114 TYPE_UNSIGNED (type
));
8117 /* Try to make operands [OPS, OPS + NOPS) match operands [OPNO, OPNO + NOPS)
8118 of instruction ICODE. Return true on success, leaving the new operand
8119 values in the OPS themselves. Emit no code on failure. */
8122 maybe_legitimize_operands (enum insn_code icode
, unsigned int opno
,
8123 unsigned int nops
, struct expand_operand
*ops
)
8128 last
= get_last_insn ();
8129 for (i
= 0; i
< nops
; i
++)
8130 if (!maybe_legitimize_operand (icode
, opno
+ i
, &ops
[i
]))
8132 delete_insns_since (last
);
8138 /* Try to generate instruction ICODE, using operands [OPS, OPS + NOPS)
8139 as its operands. Return the instruction pattern on success,
8140 and emit any necessary set-up code. Return null and emit no
8144 maybe_gen_insn (enum insn_code icode
, unsigned int nops
,
8145 struct expand_operand
*ops
)
8147 gcc_assert (nops
== (unsigned int) insn_data
[(int) icode
].n_generator_args
);
8148 if (!maybe_legitimize_operands (icode
, 0, nops
, ops
))
8154 return GEN_FCN (icode
) (ops
[0].value
);
8156 return GEN_FCN (icode
) (ops
[0].value
, ops
[1].value
);
8158 return GEN_FCN (icode
) (ops
[0].value
, ops
[1].value
, ops
[2].value
);
8160 return GEN_FCN (icode
) (ops
[0].value
, ops
[1].value
, ops
[2].value
,
8163 return GEN_FCN (icode
) (ops
[0].value
, ops
[1].value
, ops
[2].value
,
8164 ops
[3].value
, ops
[4].value
);
8166 return GEN_FCN (icode
) (ops
[0].value
, ops
[1].value
, ops
[2].value
,
8167 ops
[3].value
, ops
[4].value
, ops
[5].value
);
8169 return GEN_FCN (icode
) (ops
[0].value
, ops
[1].value
, ops
[2].value
,
8170 ops
[3].value
, ops
[4].value
, ops
[5].value
,
8173 return GEN_FCN (icode
) (ops
[0].value
, ops
[1].value
, ops
[2].value
,
8174 ops
[3].value
, ops
[4].value
, ops
[5].value
,
8175 ops
[6].value
, ops
[7].value
);
8180 /* Try to emit instruction ICODE, using operands [OPS, OPS + NOPS)
8181 as its operands. Return true on success and emit no code on failure. */
8184 maybe_expand_insn (enum insn_code icode
, unsigned int nops
,
8185 struct expand_operand
*ops
)
8187 rtx pat
= maybe_gen_insn (icode
, nops
, ops
);
8196 /* Like maybe_expand_insn, but for jumps. */
8199 maybe_expand_jump_insn (enum insn_code icode
, unsigned int nops
,
8200 struct expand_operand
*ops
)
8202 rtx pat
= maybe_gen_insn (icode
, nops
, ops
);
8205 emit_jump_insn (pat
);
8211 /* Emit instruction ICODE, using operands [OPS, OPS + NOPS)
8215 expand_insn (enum insn_code icode
, unsigned int nops
,
8216 struct expand_operand
*ops
)
8218 if (!maybe_expand_insn (icode
, nops
, ops
))
8222 /* Like expand_insn, but for jumps. */
8225 expand_jump_insn (enum insn_code icode
, unsigned int nops
,
8226 struct expand_operand
*ops
)
8228 if (!maybe_expand_jump_insn (icode
, nops
, ops
))
8232 /* Reduce conditional compilation elsewhere. */
8235 #define CODE_FOR_insv CODE_FOR_nothing
8239 #define CODE_FOR_extv CODE_FOR_nothing
8242 #define HAVE_extzv 0
8243 #define CODE_FOR_extzv CODE_FOR_nothing
8246 /* Enumerates the possible types of structure operand to an
8248 enum extraction_type
{ ET_unaligned_mem
, ET_reg
};
8250 /* Check whether insv, extv or extzv pattern ICODE can be used for an
8251 insertion or extraction of type TYPE on a structure of mode MODE.
8252 Return true if so and fill in *INSN accordingly. STRUCT_OP is the
8253 operand number of the structure (the first sign_extract or zero_extract
8254 operand) and FIELD_OP is the operand number of the field (the other
8255 side of the set from the sign_extract or zero_extract). */
8258 get_traditional_extraction_insn (extraction_insn
*insn
,
8259 enum extraction_type type
,
8260 enum machine_mode mode
,
8261 enum insn_code icode
,
8262 int struct_op
, int field_op
)
8264 const struct insn_data_d
*data
= &insn_data
[icode
];
8266 enum machine_mode struct_mode
= data
->operand
[struct_op
].mode
;
8267 if (struct_mode
== VOIDmode
)
8268 struct_mode
= word_mode
;
8269 if (mode
!= struct_mode
)
8272 enum machine_mode field_mode
= data
->operand
[field_op
].mode
;
8273 if (field_mode
== VOIDmode
)
8274 field_mode
= word_mode
;
8276 enum machine_mode pos_mode
= data
->operand
[struct_op
+ 2].mode
;
8277 if (pos_mode
== VOIDmode
)
8278 pos_mode
= word_mode
;
8280 insn
->icode
= icode
;
8281 insn
->field_mode
= field_mode
;
8282 insn
->struct_mode
= (type
== ET_unaligned_mem
? byte_mode
: struct_mode
);
8283 insn
->pos_mode
= pos_mode
;
8287 /* Return true if an optab exists to perform an insertion or extraction
8288 of type TYPE in mode MODE. Describe the instruction in *INSN if so.
8290 REG_OPTAB is the optab to use for register structures and
8291 MISALIGN_OPTAB is the optab to use for misaligned memory structures.
8292 POS_OP is the operand number of the bit position. */
8295 get_optab_extraction_insn (struct extraction_insn
*insn
,
8296 enum extraction_type type
,
8297 enum machine_mode mode
, direct_optab reg_optab
,
8298 direct_optab misalign_optab
, int pos_op
)
8300 direct_optab optab
= (type
== ET_unaligned_mem
? misalign_optab
: reg_optab
);
8301 enum insn_code icode
= direct_optab_handler (optab
, mode
);
8302 if (icode
== CODE_FOR_nothing
)
8305 const struct insn_data_d
*data
= &insn_data
[icode
];
8307 insn
->icode
= icode
;
8308 insn
->field_mode
= mode
;
8309 insn
->struct_mode
= (type
== ET_unaligned_mem
? BLKmode
: mode
);
8310 insn
->pos_mode
= data
->operand
[pos_op
].mode
;
8311 if (insn
->pos_mode
== VOIDmode
)
8312 insn
->pos_mode
= word_mode
;
8316 /* Return true if an instruction exists to perform an insertion or
8317 extraction (PATTERN says which) of type TYPE in mode MODE.
8318 Describe the instruction in *INSN if so. */
8321 get_extraction_insn (extraction_insn
*insn
,
8322 enum extraction_pattern pattern
,
8323 enum extraction_type type
,
8324 enum machine_mode mode
)
8330 && get_traditional_extraction_insn (insn
, type
, mode
,
8331 CODE_FOR_insv
, 0, 3))
8333 return get_optab_extraction_insn (insn
, type
, mode
, insv_optab
,
8334 insvmisalign_optab
, 2);
8338 && get_traditional_extraction_insn (insn
, type
, mode
,
8339 CODE_FOR_extv
, 1, 0))
8341 return get_optab_extraction_insn (insn
, type
, mode
, extv_optab
,
8342 extvmisalign_optab
, 3);
8346 && get_traditional_extraction_insn (insn
, type
, mode
,
8347 CODE_FOR_extzv
, 1, 0))
8349 return get_optab_extraction_insn (insn
, type
, mode
, extzv_optab
,
8350 extzvmisalign_optab
, 3);
8357 /* Return true if an instruction exists to access a field of mode
8358 FIELDMODE in a structure that has STRUCT_BITS significant bits.
8359 Describe the "best" such instruction in *INSN if so. PATTERN and
8360 TYPE describe the type of insertion or extraction we want to perform.
8362 For an insertion, the number of significant structure bits includes
8363 all bits of the target. For an extraction, it need only include the
8364 most significant bit of the field. Larger widths are acceptable
8368 get_best_extraction_insn (extraction_insn
*insn
,
8369 enum extraction_pattern pattern
,
8370 enum extraction_type type
,
8371 unsigned HOST_WIDE_INT struct_bits
,
8372 enum machine_mode field_mode
)
8374 enum machine_mode mode
= smallest_mode_for_size (struct_bits
, MODE_INT
);
8375 while (mode
!= VOIDmode
)
8377 if (get_extraction_insn (insn
, pattern
, type
, mode
))
8379 while (mode
!= VOIDmode
8380 && GET_MODE_SIZE (mode
) <= GET_MODE_SIZE (field_mode
)
8381 && !TRULY_NOOP_TRUNCATION_MODES_P (insn
->field_mode
,
8384 get_extraction_insn (insn
, pattern
, type
, mode
);
8385 mode
= GET_MODE_WIDER_MODE (mode
);
8389 mode
= GET_MODE_WIDER_MODE (mode
);
8394 /* Return true if an instruction exists to access a field of mode
8395 FIELDMODE in a register structure that has STRUCT_BITS significant bits.
8396 Describe the "best" such instruction in *INSN if so. PATTERN describes
8397 the type of insertion or extraction we want to perform.
8399 For an insertion, the number of significant structure bits includes
8400 all bits of the target. For an extraction, it need only include the
8401 most significant bit of the field. Larger widths are acceptable
8405 get_best_reg_extraction_insn (extraction_insn
*insn
,
8406 enum extraction_pattern pattern
,
8407 unsigned HOST_WIDE_INT struct_bits
,
8408 enum machine_mode field_mode
)
8410 return get_best_extraction_insn (insn
, pattern
, ET_reg
, struct_bits
,
8414 /* Return true if an instruction exists to access a field of BITSIZE
8415 bits starting BITNUM bits into a memory structure. Describe the
8416 "best" such instruction in *INSN if so. PATTERN describes the type
8417 of insertion or extraction we want to perform and FIELDMODE is the
8418 natural mode of the extracted field.
8420 The instructions considered here only access bytes that overlap
8421 the bitfield; they do not touch any surrounding bytes. */
8424 get_best_mem_extraction_insn (extraction_insn
*insn
,
8425 enum extraction_pattern pattern
,
8426 HOST_WIDE_INT bitsize
, HOST_WIDE_INT bitnum
,
8427 enum machine_mode field_mode
)
8429 unsigned HOST_WIDE_INT struct_bits
= (bitnum
% BITS_PER_UNIT
8431 + BITS_PER_UNIT
- 1);
8432 struct_bits
-= struct_bits
% BITS_PER_UNIT
;
8433 return get_best_extraction_insn (insn
, pattern
, ET_unaligned_mem
,
8434 struct_bits
, field_mode
);
8437 #include "gt-optabs.h"