1 /* Expand the basic unary and binary arithmetic operations, for GNU compiler.
2 Copyright (C) 1987, 88, 92-98, 1999 Free Software Foundation, Inc.
4 This file is part of GNU CC.
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
27 #include "insn-flags.h"
28 #include "insn-codes.h"
30 #include "insn-config.h"
34 /* Each optab contains info on how this target machine
35 can perform a particular operation
36 for all sizes and kinds of operands.
38 The operation to be performed is often specified
39 by passing one of these optabs as an argument.
41 See expr.h for documentation of these optabs. */
46 optab smul_highpart_optab
;
47 optab umul_highpart_optab
;
48 optab smul_widen_optab
;
49 optab umul_widen_optab
;
72 optab movstrict_optab
;
83 optab ucmp_optab
; /* Used only for libcalls for unsigned comparisons. */
88 /* Tables of patterns for extending one integer mode to another. */
89 enum insn_code extendtab
[MAX_MACHINE_MODE
][MAX_MACHINE_MODE
][2];
91 /* Tables of patterns for converting between fixed and floating point. */
92 enum insn_code fixtab
[NUM_MACHINE_MODES
][NUM_MACHINE_MODES
][2];
93 enum insn_code fixtrunctab
[NUM_MACHINE_MODES
][NUM_MACHINE_MODES
][2];
94 enum insn_code floattab
[NUM_MACHINE_MODES
][NUM_MACHINE_MODES
][2];
96 /* Contains the optab used for each rtx code. */
97 optab code_to_optab
[NUM_RTX_CODE
+ 1];
99 /* SYMBOL_REF rtx's for the library functions that are called
100 implicitly and not via optabs. */
102 rtx extendsfdf2_libfunc
;
103 rtx extendsfxf2_libfunc
;
104 rtx extendsftf2_libfunc
;
105 rtx extenddfxf2_libfunc
;
106 rtx extenddftf2_libfunc
;
108 rtx truncdfsf2_libfunc
;
109 rtx truncxfsf2_libfunc
;
110 rtx trunctfsf2_libfunc
;
111 rtx truncxfdf2_libfunc
;
112 rtx trunctfdf2_libfunc
;
124 rtx sjpopnthrow_libfunc
;
125 rtx terminate_libfunc
;
128 rtx eh_rtime_match_libfunc
;
165 rtx floatsisf_libfunc
;
166 rtx floatdisf_libfunc
;
167 rtx floattisf_libfunc
;
169 rtx floatsidf_libfunc
;
170 rtx floatdidf_libfunc
;
171 rtx floattidf_libfunc
;
173 rtx floatsixf_libfunc
;
174 rtx floatdixf_libfunc
;
175 rtx floattixf_libfunc
;
177 rtx floatsitf_libfunc
;
178 rtx floatditf_libfunc
;
179 rtx floattitf_libfunc
;
197 rtx fixunssfsi_libfunc
;
198 rtx fixunssfdi_libfunc
;
199 rtx fixunssfti_libfunc
;
201 rtx fixunsdfsi_libfunc
;
202 rtx fixunsdfdi_libfunc
;
203 rtx fixunsdfti_libfunc
;
205 rtx fixunsxfsi_libfunc
;
206 rtx fixunsxfdi_libfunc
;
207 rtx fixunsxfti_libfunc
;
209 rtx fixunstfsi_libfunc
;
210 rtx fixunstfdi_libfunc
;
211 rtx fixunstfti_libfunc
;
213 rtx chkr_check_addr_libfunc
;
214 rtx chkr_set_right_libfunc
;
215 rtx chkr_copy_bitmap_libfunc
;
216 rtx chkr_check_exec_libfunc
;
217 rtx chkr_check_str_libfunc
;
219 rtx profile_function_entry_libfunc
;
220 rtx profile_function_exit_libfunc
;
222 /* Indexed by the rtx-code for a conditional (eg. EQ, LT,...)
223 gives the gen_function to make a branch to test that condition. */
225 rtxfun bcc_gen_fctn
[NUM_RTX_CODE
];
227 /* Indexed by the rtx-code for a conditional (eg. EQ, LT,...)
228 gives the insn code to make a store-condition insn
229 to test that condition. */
231 enum insn_code setcc_gen_code
[NUM_RTX_CODE
];
233 #ifdef HAVE_conditional_move
234 /* Indexed by the machine mode, gives the insn code to make a conditional
235 move insn. This is not indexed by the rtx-code like bcc_gen_fctn and
236 setcc_gen_code to cut down on the number of named patterns. Consider a day
237 when a lot more rtx codes are conditional (eg: for the ARM). */
239 enum insn_code movcc_gen_code
[NUM_MACHINE_MODES
];
242 static int add_equal_note
PROTO((rtx
, rtx
, enum rtx_code
, rtx
, rtx
));
243 static rtx widen_operand
PROTO((rtx
, enum machine_mode
,
244 enum machine_mode
, int, int));
245 static enum insn_code can_fix_p
PROTO((enum machine_mode
, enum machine_mode
,
247 static enum insn_code can_float_p
PROTO((enum machine_mode
, enum machine_mode
,
249 static rtx ftruncify
PROTO((rtx
));
250 static optab init_optab
PROTO((enum rtx_code
));
251 static void init_libfuncs
PROTO((optab
, int, int, char *, int));
252 static void init_integral_libfuncs
PROTO((optab
, char *, int));
253 static void init_floating_libfuncs
PROTO((optab
, char *, int));
254 #ifdef HAVE_conditional_trap
255 static void init_traps
PROTO((void));
258 /* Add a REG_EQUAL note to the last insn in SEQ. TARGET is being set to
259 the result of operation CODE applied to OP0 (and OP1 if it is a binary
262 If the last insn does not set TARGET, don't do anything, but return 1.
264 If a previous insn sets TARGET and TARGET is one of OP0 or OP1,
265 don't add the REG_EQUAL note but return 0. Our caller can then try
266 again, ensuring that TARGET is not one of the operands. */
269 add_equal_note (seq
, target
, code
, op0
, op1
)
279 if ((GET_RTX_CLASS (code
) != '1' && GET_RTX_CLASS (code
) != '2'
280 && GET_RTX_CLASS (code
) != 'c' && GET_RTX_CLASS (code
) != '<')
281 || GET_CODE (seq
) != SEQUENCE
282 || (set
= single_set (XVECEXP (seq
, 0, XVECLEN (seq
, 0) - 1))) == 0
283 || GET_CODE (target
) == ZERO_EXTRACT
284 || (! rtx_equal_p (SET_DEST (set
), target
)
285 /* For a STRICT_LOW_PART, the REG_NOTE applies to what is inside the
287 && (GET_CODE (SET_DEST (set
)) != STRICT_LOW_PART
288 || ! rtx_equal_p (SUBREG_REG (XEXP (SET_DEST (set
), 0)),
292 /* If TARGET is in OP0 or OP1, check if anything in SEQ sets TARGET
293 besides the last insn. */
294 if (reg_overlap_mentioned_p (target
, op0
)
295 || (op1
&& reg_overlap_mentioned_p (target
, op1
)))
296 for (i
= XVECLEN (seq
, 0) - 2; i
>= 0; i
--)
297 if (reg_set_p (target
, XVECEXP (seq
, 0, i
)))
300 if (GET_RTX_CLASS (code
) == '1')
301 note
= gen_rtx_fmt_e (code
, GET_MODE (target
), copy_rtx (op0
));
303 note
= gen_rtx_fmt_ee (code
, GET_MODE (target
), copy_rtx (op0
), copy_rtx (op1
));
305 REG_NOTES (XVECEXP (seq
, 0, XVECLEN (seq
, 0) - 1))
306 = gen_rtx_EXPR_LIST (REG_EQUAL
, note
,
307 REG_NOTES (XVECEXP (seq
, 0, XVECLEN (seq
, 0) - 1)));
312 /* Widen OP to MODE and return the rtx for the widened operand. UNSIGNEDP
313 says whether OP is signed or unsigned. NO_EXTEND is nonzero if we need
314 not actually do a sign-extend or zero-extend, but can leave the
315 higher-order bits of the result rtx undefined, for example, in the case
316 of logical operations, but not right shifts. */
319 widen_operand (op
, mode
, oldmode
, unsignedp
, no_extend
)
321 enum machine_mode mode
, oldmode
;
327 /* If we must extend do so. If OP is either a constant or a SUBREG
328 for a promoted object, also extend since it will be more efficient to
331 || GET_MODE (op
) == VOIDmode
332 || (GET_CODE (op
) == SUBREG
&& SUBREG_PROMOTED_VAR_P (op
)))
333 return convert_modes (mode
, oldmode
, op
, unsignedp
);
335 /* If MODE is no wider than a single word, we return a paradoxical
337 if (GET_MODE_SIZE (mode
) <= UNITS_PER_WORD
)
338 return gen_rtx_SUBREG (mode
, force_reg (GET_MODE (op
), op
), 0);
340 /* Otherwise, get an object of MODE, clobber it, and set the low-order
343 result
= gen_reg_rtx (mode
);
344 emit_insn (gen_rtx_CLOBBER (VOIDmode
, result
));
345 emit_move_insn (gen_lowpart (GET_MODE (op
), result
), op
);
349 /* Generate code to perform an operation specified by BINOPTAB
350 on operands OP0 and OP1, with result having machine-mode MODE.
352 UNSIGNEDP is for the case where we have to widen the operands
353 to perform the operation. It says to use zero-extension.
355 If TARGET is nonzero, the value
356 is generated there, if it is convenient to do so.
357 In all cases an rtx is returned for the locus of the value;
358 this may or may not be TARGET. */
361 expand_binop (mode
, binoptab
, op0
, op1
, target
, unsignedp
, methods
)
362 enum machine_mode mode
;
367 enum optab_methods methods
;
369 enum optab_methods next_methods
370 = (methods
== OPTAB_LIB
|| methods
== OPTAB_LIB_WIDEN
371 ? OPTAB_WIDEN
: methods
);
372 enum mode_class
class;
373 enum machine_mode wider_mode
;
375 int commutative_op
= 0;
376 int shift_op
= (binoptab
->code
== ASHIFT
377 || binoptab
->code
== ASHIFTRT
378 || binoptab
->code
== LSHIFTRT
379 || binoptab
->code
== ROTATE
380 || binoptab
->code
== ROTATERT
);
381 rtx entry_last
= get_last_insn ();
384 class = GET_MODE_CLASS (mode
);
386 op0
= protect_from_queue (op0
, 0);
387 op1
= protect_from_queue (op1
, 0);
389 target
= protect_from_queue (target
, 1);
393 op0
= force_not_mem (op0
);
394 op1
= force_not_mem (op1
);
397 /* If subtracting an integer constant, convert this into an addition of
398 the negated constant. */
400 if (binoptab
== sub_optab
&& GET_CODE (op1
) == CONST_INT
)
402 op1
= negate_rtx (mode
, op1
);
403 binoptab
= add_optab
;
406 /* If we are inside an appropriately-short loop and one operand is an
407 expensive constant, force it into a register. */
408 if (CONSTANT_P (op0
) && preserve_subexpressions_p ()
409 && rtx_cost (op0
, binoptab
->code
) > 2)
410 op0
= force_reg (mode
, op0
);
412 if (CONSTANT_P (op1
) && preserve_subexpressions_p ()
413 && ! shift_op
&& rtx_cost (op1
, binoptab
->code
) > 2)
414 op1
= force_reg (mode
, op1
);
416 /* Record where to delete back to if we backtrack. */
417 last
= get_last_insn ();
419 /* If operation is commutative,
420 try to make the first operand a register.
421 Even better, try to make it the same as the target.
422 Also try to make the last operand a constant. */
423 if (GET_RTX_CLASS (binoptab
->code
) == 'c'
424 || binoptab
== smul_widen_optab
425 || binoptab
== umul_widen_optab
426 || binoptab
== smul_highpart_optab
427 || binoptab
== umul_highpart_optab
)
431 if (((target
== 0 || GET_CODE (target
) == REG
)
432 ? ((GET_CODE (op1
) == REG
433 && GET_CODE (op0
) != REG
)
435 : rtx_equal_p (op1
, target
))
436 || GET_CODE (op0
) == CONST_INT
)
444 /* If we can do it with a three-operand insn, do so. */
446 if (methods
!= OPTAB_MUST_WIDEN
447 && binoptab
->handlers
[(int) mode
].insn_code
!= CODE_FOR_nothing
)
449 int icode
= (int) binoptab
->handlers
[(int) mode
].insn_code
;
450 enum machine_mode mode0
= insn_operand_mode
[icode
][1];
451 enum machine_mode mode1
= insn_operand_mode
[icode
][2];
453 rtx xop0
= op0
, xop1
= op1
;
458 temp
= gen_reg_rtx (mode
);
460 /* If it is a commutative operator and the modes would match
461 if we would swap the operands, we can save the conversions. */
464 if (GET_MODE (op0
) != mode0
&& GET_MODE (op1
) != mode1
465 && GET_MODE (op0
) == mode1
&& GET_MODE (op1
) == mode0
)
469 tmp
= op0
; op0
= op1
; op1
= tmp
;
470 tmp
= xop0
; xop0
= xop1
; xop1
= tmp
;
474 /* In case the insn wants input operands in modes different from
475 the result, convert the operands. */
477 if (GET_MODE (op0
) != VOIDmode
478 && GET_MODE (op0
) != mode0
479 && mode0
!= VOIDmode
)
480 xop0
= convert_to_mode (mode0
, xop0
, unsignedp
);
482 if (GET_MODE (xop1
) != VOIDmode
483 && GET_MODE (xop1
) != mode1
484 && mode1
!= VOIDmode
)
485 xop1
= convert_to_mode (mode1
, xop1
, unsignedp
);
487 /* Now, if insn's predicates don't allow our operands, put them into
490 if (! (*insn_operand_predicate
[icode
][1]) (xop0
, mode0
)
491 && mode0
!= VOIDmode
)
492 xop0
= copy_to_mode_reg (mode0
, xop0
);
494 if (! (*insn_operand_predicate
[icode
][2]) (xop1
, mode1
)
495 && mode1
!= VOIDmode
)
496 xop1
= copy_to_mode_reg (mode1
, xop1
);
498 if (! (*insn_operand_predicate
[icode
][0]) (temp
, mode
))
499 temp
= gen_reg_rtx (mode
);
501 pat
= GEN_FCN (icode
) (temp
, xop0
, xop1
);
504 /* If PAT is a multi-insn sequence, try to add an appropriate
505 REG_EQUAL note to it. If we can't because TEMP conflicts with an
506 operand, call ourselves again, this time without a target. */
507 if (GET_CODE (pat
) == SEQUENCE
508 && ! add_equal_note (pat
, temp
, binoptab
->code
, xop0
, xop1
))
510 delete_insns_since (last
);
511 return expand_binop (mode
, binoptab
, op0
, op1
, NULL_RTX
,
519 delete_insns_since (last
);
522 /* If this is a multiply, see if we can do a widening operation that
523 takes operands of this mode and makes a wider mode. */
525 if (binoptab
== smul_optab
&& GET_MODE_WIDER_MODE (mode
) != VOIDmode
526 && (((unsignedp
? umul_widen_optab
: smul_widen_optab
)
527 ->handlers
[(int) GET_MODE_WIDER_MODE (mode
)].insn_code
)
528 != CODE_FOR_nothing
))
530 temp
= expand_binop (GET_MODE_WIDER_MODE (mode
),
531 unsignedp
? umul_widen_optab
: smul_widen_optab
,
532 op0
, op1
, NULL_RTX
, unsignedp
, OPTAB_DIRECT
);
536 if (GET_MODE_CLASS (mode
) == MODE_INT
)
537 return gen_lowpart (mode
, temp
);
539 return convert_to_mode (mode
, temp
, unsignedp
);
543 /* Look for a wider mode of the same class for which we think we
544 can open-code the operation. Check for a widening multiply at the
545 wider mode as well. */
547 if ((class == MODE_INT
|| class == MODE_FLOAT
|| class == MODE_COMPLEX_FLOAT
)
548 && methods
!= OPTAB_DIRECT
&& methods
!= OPTAB_LIB
)
549 for (wider_mode
= GET_MODE_WIDER_MODE (mode
); wider_mode
!= VOIDmode
;
550 wider_mode
= GET_MODE_WIDER_MODE (wider_mode
))
552 if (binoptab
->handlers
[(int) wider_mode
].insn_code
!= CODE_FOR_nothing
553 || (binoptab
== smul_optab
554 && GET_MODE_WIDER_MODE (wider_mode
) != VOIDmode
555 && (((unsignedp
? umul_widen_optab
: smul_widen_optab
)
556 ->handlers
[(int) GET_MODE_WIDER_MODE (wider_mode
)].insn_code
)
557 != CODE_FOR_nothing
)))
559 rtx xop0
= op0
, xop1
= op1
;
562 /* For certain integer operations, we need not actually extend
563 the narrow operands, as long as we will truncate
564 the results to the same narrowness. */
566 if ((binoptab
== ior_optab
|| binoptab
== and_optab
567 || binoptab
== xor_optab
568 || binoptab
== add_optab
|| binoptab
== sub_optab
569 || binoptab
== smul_optab
|| binoptab
== ashl_optab
)
570 && class == MODE_INT
)
573 xop0
= widen_operand (xop0
, wider_mode
, mode
, unsignedp
, no_extend
);
575 /* The second operand of a shift must always be extended. */
576 xop1
= widen_operand (xop1
, wider_mode
, mode
, unsignedp
,
577 no_extend
&& binoptab
!= ashl_optab
);
579 temp
= expand_binop (wider_mode
, binoptab
, xop0
, xop1
, NULL_RTX
,
580 unsignedp
, OPTAB_DIRECT
);
583 if (class != MODE_INT
)
586 target
= gen_reg_rtx (mode
);
587 convert_move (target
, temp
, 0);
591 return gen_lowpart (mode
, temp
);
594 delete_insns_since (last
);
598 /* These can be done a word at a time. */
599 if ((binoptab
== and_optab
|| binoptab
== ior_optab
|| binoptab
== xor_optab
)
601 && GET_MODE_SIZE (mode
) > UNITS_PER_WORD
602 && binoptab
->handlers
[(int) word_mode
].insn_code
!= CODE_FOR_nothing
)
608 /* If TARGET is the same as one of the operands, the REG_EQUAL note
609 won't be accurate, so use a new target. */
610 if (target
== 0 || target
== op0
|| target
== op1
)
611 target
= gen_reg_rtx (mode
);
615 /* Do the actual arithmetic. */
616 for (i
= 0; i
< GET_MODE_BITSIZE (mode
) / BITS_PER_WORD
; i
++)
618 rtx target_piece
= operand_subword (target
, i
, 1, mode
);
619 rtx x
= expand_binop (word_mode
, binoptab
,
620 operand_subword_force (op0
, i
, mode
),
621 operand_subword_force (op1
, i
, mode
),
622 target_piece
, unsignedp
, next_methods
);
627 if (target_piece
!= x
)
628 emit_move_insn (target_piece
, x
);
631 insns
= get_insns ();
634 if (i
== GET_MODE_BITSIZE (mode
) / BITS_PER_WORD
)
636 if (binoptab
->code
!= UNKNOWN
)
638 = gen_rtx_fmt_ee (binoptab
->code
, mode
,
639 copy_rtx (op0
), copy_rtx (op1
));
643 emit_no_conflict_block (insns
, target
, op0
, op1
, equiv_value
);
648 /* Synthesize double word shifts from single word shifts. */
649 if ((binoptab
== lshr_optab
|| binoptab
== ashl_optab
650 || binoptab
== ashr_optab
)
652 && GET_CODE (op1
) == CONST_INT
653 && GET_MODE_SIZE (mode
) == 2 * UNITS_PER_WORD
654 && binoptab
->handlers
[(int) word_mode
].insn_code
!= CODE_FOR_nothing
655 && ashl_optab
->handlers
[(int) word_mode
].insn_code
!= CODE_FOR_nothing
656 && lshr_optab
->handlers
[(int) word_mode
].insn_code
!= CODE_FOR_nothing
)
658 rtx insns
, inter
, equiv_value
;
659 rtx into_target
, outof_target
;
660 rtx into_input
, outof_input
;
661 int shift_count
, left_shift
, outof_word
;
663 /* If TARGET is the same as one of the operands, the REG_EQUAL note
664 won't be accurate, so use a new target. */
665 if (target
== 0 || target
== op0
|| target
== op1
)
666 target
= gen_reg_rtx (mode
);
670 shift_count
= INTVAL (op1
);
672 /* OUTOF_* is the word we are shifting bits away from, and
673 INTO_* is the word that we are shifting bits towards, thus
674 they differ depending on the direction of the shift and
677 left_shift
= binoptab
== ashl_optab
;
678 outof_word
= left_shift
^ ! WORDS_BIG_ENDIAN
;
680 outof_target
= operand_subword (target
, outof_word
, 1, mode
);
681 into_target
= operand_subword (target
, 1 - outof_word
, 1, mode
);
683 outof_input
= operand_subword_force (op0
, outof_word
, mode
);
684 into_input
= operand_subword_force (op0
, 1 - outof_word
, mode
);
686 if (shift_count
>= BITS_PER_WORD
)
688 inter
= expand_binop (word_mode
, binoptab
,
690 GEN_INT (shift_count
- BITS_PER_WORD
),
691 into_target
, unsignedp
, next_methods
);
693 if (inter
!= 0 && inter
!= into_target
)
694 emit_move_insn (into_target
, inter
);
696 /* For a signed right shift, we must fill the word we are shifting
697 out of with copies of the sign bit. Otherwise it is zeroed. */
698 if (inter
!= 0 && binoptab
!= ashr_optab
)
699 inter
= CONST0_RTX (word_mode
);
701 inter
= expand_binop (word_mode
, binoptab
,
703 GEN_INT (BITS_PER_WORD
- 1),
704 outof_target
, unsignedp
, next_methods
);
706 if (inter
!= 0 && inter
!= outof_target
)
707 emit_move_insn (outof_target
, inter
);
712 optab reverse_unsigned_shift
, unsigned_shift
;
714 /* For a shift of less then BITS_PER_WORD, to compute the carry,
715 we must do a logical shift in the opposite direction of the
718 reverse_unsigned_shift
= (left_shift
? lshr_optab
: ashl_optab
);
720 /* For a shift of less than BITS_PER_WORD, to compute the word
721 shifted towards, we need to unsigned shift the orig value of
724 unsigned_shift
= (left_shift
? ashl_optab
: lshr_optab
);
726 carries
= expand_binop (word_mode
, reverse_unsigned_shift
,
728 GEN_INT (BITS_PER_WORD
- shift_count
),
729 0, unsignedp
, next_methods
);
734 inter
= expand_binop (word_mode
, unsigned_shift
, into_input
,
735 op1
, 0, unsignedp
, next_methods
);
738 inter
= expand_binop (word_mode
, ior_optab
, carries
, inter
,
739 into_target
, unsignedp
, next_methods
);
741 if (inter
!= 0 && inter
!= into_target
)
742 emit_move_insn (into_target
, inter
);
745 inter
= expand_binop (word_mode
, binoptab
, outof_input
,
746 op1
, outof_target
, unsignedp
, next_methods
);
748 if (inter
!= 0 && inter
!= outof_target
)
749 emit_move_insn (outof_target
, inter
);
752 insns
= get_insns ();
757 if (binoptab
->code
!= UNKNOWN
)
758 equiv_value
= gen_rtx_fmt_ee (binoptab
->code
, mode
, op0
, op1
);
762 emit_no_conflict_block (insns
, target
, op0
, op1
, equiv_value
);
767 /* Synthesize double word rotates from single word shifts. */
768 if ((binoptab
== rotl_optab
|| binoptab
== rotr_optab
)
770 && GET_CODE (op1
) == CONST_INT
771 && GET_MODE_SIZE (mode
) == 2 * UNITS_PER_WORD
772 && ashl_optab
->handlers
[(int) word_mode
].insn_code
!= CODE_FOR_nothing
773 && lshr_optab
->handlers
[(int) word_mode
].insn_code
!= CODE_FOR_nothing
)
775 rtx insns
, equiv_value
;
776 rtx into_target
, outof_target
;
777 rtx into_input
, outof_input
;
779 int shift_count
, left_shift
, outof_word
;
781 /* If TARGET is the same as one of the operands, the REG_EQUAL note
782 won't be accurate, so use a new target. */
783 if (target
== 0 || target
== op0
|| target
== op1
)
784 target
= gen_reg_rtx (mode
);
788 shift_count
= INTVAL (op1
);
790 /* OUTOF_* is the word we are shifting bits away from, and
791 INTO_* is the word that we are shifting bits towards, thus
792 they differ depending on the direction of the shift and
795 left_shift
= (binoptab
== rotl_optab
);
796 outof_word
= left_shift
^ ! WORDS_BIG_ENDIAN
;
798 outof_target
= operand_subword (target
, outof_word
, 1, mode
);
799 into_target
= operand_subword (target
, 1 - outof_word
, 1, mode
);
801 outof_input
= operand_subword_force (op0
, outof_word
, mode
);
802 into_input
= operand_subword_force (op0
, 1 - outof_word
, mode
);
804 if (shift_count
== BITS_PER_WORD
)
806 /* This is just a word swap. */
807 emit_move_insn (outof_target
, into_input
);
808 emit_move_insn (into_target
, outof_input
);
813 rtx into_temp1
, into_temp2
, outof_temp1
, outof_temp2
;
814 rtx first_shift_count
, second_shift_count
;
815 optab reverse_unsigned_shift
, unsigned_shift
;
817 reverse_unsigned_shift
= (left_shift
^ (shift_count
< BITS_PER_WORD
)
818 ? lshr_optab
: ashl_optab
);
820 unsigned_shift
= (left_shift
^ (shift_count
< BITS_PER_WORD
)
821 ? ashl_optab
: lshr_optab
);
823 if (shift_count
> BITS_PER_WORD
)
825 first_shift_count
= GEN_INT (shift_count
- BITS_PER_WORD
);
826 second_shift_count
= GEN_INT (2*BITS_PER_WORD
- shift_count
);
830 first_shift_count
= GEN_INT (BITS_PER_WORD
- shift_count
);
831 second_shift_count
= GEN_INT (shift_count
);
834 into_temp1
= expand_binop (word_mode
, unsigned_shift
,
835 outof_input
, first_shift_count
,
836 NULL_RTX
, unsignedp
, next_methods
);
837 into_temp2
= expand_binop (word_mode
, reverse_unsigned_shift
,
838 into_input
, second_shift_count
,
839 into_target
, unsignedp
, next_methods
);
841 if (into_temp1
!= 0 && into_temp2
!= 0)
842 inter
= expand_binop (word_mode
, ior_optab
, into_temp1
, into_temp2
,
843 into_target
, unsignedp
, next_methods
);
847 if (inter
!= 0 && inter
!= into_target
)
848 emit_move_insn (into_target
, inter
);
850 outof_temp1
= expand_binop (word_mode
, unsigned_shift
,
851 into_input
, first_shift_count
,
852 NULL_RTX
, unsignedp
, next_methods
);
853 outof_temp2
= expand_binop (word_mode
, reverse_unsigned_shift
,
854 outof_input
, second_shift_count
,
855 outof_target
, unsignedp
, next_methods
);
857 if (inter
!= 0 && outof_temp1
!= 0 && outof_temp2
!= 0)
858 inter
= expand_binop (word_mode
, ior_optab
,
859 outof_temp1
, outof_temp2
,
860 outof_target
, unsignedp
, next_methods
);
862 if (inter
!= 0 && inter
!= outof_target
)
863 emit_move_insn (outof_target
, inter
);
866 insns
= get_insns ();
871 if (binoptab
->code
!= UNKNOWN
)
872 equiv_value
= gen_rtx_fmt_ee (binoptab
->code
, mode
, op0
, op1
);
876 /* We can't make this a no conflict block if this is a word swap,
877 because the word swap case fails if the input and output values
878 are in the same register. */
879 if (shift_count
!= BITS_PER_WORD
)
880 emit_no_conflict_block (insns
, target
, op0
, op1
, equiv_value
);
889 /* These can be done a word at a time by propagating carries. */
890 if ((binoptab
== add_optab
|| binoptab
== sub_optab
)
892 && GET_MODE_SIZE (mode
) >= 2 * UNITS_PER_WORD
893 && binoptab
->handlers
[(int) word_mode
].insn_code
!= CODE_FOR_nothing
)
896 rtx carry_tmp
= gen_reg_rtx (word_mode
);
897 optab otheroptab
= binoptab
== add_optab
? sub_optab
: add_optab
;
898 int nwords
= GET_MODE_BITSIZE (mode
) / BITS_PER_WORD
;
899 rtx carry_in
, carry_out
;
902 /* We can handle either a 1 or -1 value for the carry. If STORE_FLAG
903 value is one of those, use it. Otherwise, use 1 since it is the
904 one easiest to get. */
905 #if STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1
906 int normalizep
= STORE_FLAG_VALUE
;
911 /* Prepare the operands. */
912 xop0
= force_reg (mode
, op0
);
913 xop1
= force_reg (mode
, op1
);
915 if (target
== 0 || GET_CODE (target
) != REG
916 || target
== xop0
|| target
== xop1
)
917 target
= gen_reg_rtx (mode
);
919 /* Indicate for flow that the entire target reg is being set. */
920 if (GET_CODE (target
) == REG
)
921 emit_insn (gen_rtx_CLOBBER (VOIDmode
, target
));
923 /* Do the actual arithmetic. */
924 for (i
= 0; i
< nwords
; i
++)
926 int index
= (WORDS_BIG_ENDIAN
? nwords
- i
- 1 : i
);
927 rtx target_piece
= operand_subword (target
, index
, 1, mode
);
928 rtx op0_piece
= operand_subword_force (xop0
, index
, mode
);
929 rtx op1_piece
= operand_subword_force (xop1
, index
, mode
);
932 /* Main add/subtract of the input operands. */
933 x
= expand_binop (word_mode
, binoptab
,
934 op0_piece
, op1_piece
,
935 target_piece
, unsignedp
, next_methods
);
941 /* Store carry from main add/subtract. */
942 carry_out
= gen_reg_rtx (word_mode
);
943 carry_out
= emit_store_flag_force (carry_out
,
944 (binoptab
== add_optab
947 word_mode
, 1, normalizep
);
952 /* Add/subtract previous carry to main result. */
953 x
= expand_binop (word_mode
,
954 normalizep
== 1 ? binoptab
: otheroptab
,
956 target_piece
, 1, next_methods
);
959 else if (target_piece
!= x
)
960 emit_move_insn (target_piece
, x
);
964 /* THIS CODE HAS NOT BEEN TESTED. */
965 /* Get out carry from adding/subtracting carry in. */
966 carry_tmp
= emit_store_flag_force (carry_tmp
,
967 binoptab
== add_optab
970 word_mode
, 1, normalizep
);
972 /* Logical-ior the two poss. carry together. */
973 carry_out
= expand_binop (word_mode
, ior_optab
,
974 carry_out
, carry_tmp
,
975 carry_out
, 0, next_methods
);
981 carry_in
= carry_out
;
984 if (i
== GET_MODE_BITSIZE (mode
) / BITS_PER_WORD
)
986 if (mov_optab
->handlers
[(int) mode
].insn_code
!= CODE_FOR_nothing
)
988 rtx temp
= emit_move_insn (target
, target
);
991 = gen_rtx_EXPR_LIST (REG_EQUAL
,
992 gen_rtx_fmt_ee (binoptab
->code
, mode
,
1000 delete_insns_since (last
);
1003 /* If we want to multiply two two-word values and have normal and widening
1004 multiplies of single-word values, we can do this with three smaller
1005 multiplications. Note that we do not make a REG_NO_CONFLICT block here
1006 because we are not operating on one word at a time.
1008 The multiplication proceeds as follows:
1009 _______________________
1010 [__op0_high_|__op0_low__]
1011 _______________________
1012 * [__op1_high_|__op1_low__]
1013 _______________________________________________
1014 _______________________
1015 (1) [__op0_low__*__op1_low__]
1016 _______________________
1017 (2a) [__op0_low__*__op1_high_]
1018 _______________________
1019 (2b) [__op0_high_*__op1_low__]
1020 _______________________
1021 (3) [__op0_high_*__op1_high_]
1024 This gives a 4-word result. Since we are only interested in the
1025 lower 2 words, partial result (3) and the upper words of (2a) and
1026 (2b) don't need to be calculated. Hence (2a) and (2b) can be
1027 calculated using non-widening multiplication.
1029 (1), however, needs to be calculated with an unsigned widening
1030 multiplication. If this operation is not directly supported we
1031 try using a signed widening multiplication and adjust the result.
1032 This adjustment works as follows:
1034 If both operands are positive then no adjustment is needed.
1036 If the operands have different signs, for example op0_low < 0 and
1037 op1_low >= 0, the instruction treats the most significant bit of
1038 op0_low as a sign bit instead of a bit with significance
1039 2**(BITS_PER_WORD-1), i.e. the instruction multiplies op1_low
1040 with 2**BITS_PER_WORD - op0_low, and two's complements the
1041 result. Conclusion: We need to add op1_low * 2**BITS_PER_WORD to
1044 Similarly, if both operands are negative, we need to add
1045 (op0_low + op1_low) * 2**BITS_PER_WORD.
1047 We use a trick to adjust quickly. We logically shift op0_low right
1048 (op1_low) BITS_PER_WORD-1 steps to get 0 or 1, and add this to
1049 op0_high (op1_high) before it is used to calculate 2b (2a). If no
1050 logical shift exists, we do an arithmetic right shift and subtract
1053 if (binoptab
== smul_optab
1054 && class == MODE_INT
1055 && GET_MODE_SIZE (mode
) == 2 * UNITS_PER_WORD
1056 && smul_optab
->handlers
[(int) word_mode
].insn_code
!= CODE_FOR_nothing
1057 && add_optab
->handlers
[(int) word_mode
].insn_code
!= CODE_FOR_nothing
1058 && ((umul_widen_optab
->handlers
[(int) mode
].insn_code
1059 != CODE_FOR_nothing
)
1060 || (smul_widen_optab
->handlers
[(int) mode
].insn_code
1061 != CODE_FOR_nothing
)))
1063 int low
= (WORDS_BIG_ENDIAN
? 1 : 0);
1064 int high
= (WORDS_BIG_ENDIAN
? 0 : 1);
1065 rtx op0_high
= operand_subword_force (op0
, high
, mode
);
1066 rtx op0_low
= operand_subword_force (op0
, low
, mode
);
1067 rtx op1_high
= operand_subword_force (op1
, high
, mode
);
1068 rtx op1_low
= operand_subword_force (op1
, low
, mode
);
1073 /* If the target is the same as one of the inputs, don't use it. This
1074 prevents problems with the REG_EQUAL note. */
1075 if (target
== op0
|| target
== op1
1076 || (target
!= 0 && GET_CODE (target
) != REG
))
1079 /* Multiply the two lower words to get a double-word product.
1080 If unsigned widening multiplication is available, use that;
1081 otherwise use the signed form and compensate. */
1083 if (umul_widen_optab
->handlers
[(int) mode
].insn_code
!= CODE_FOR_nothing
)
1085 product
= expand_binop (mode
, umul_widen_optab
, op0_low
, op1_low
,
1086 target
, 1, OPTAB_DIRECT
);
1088 /* If we didn't succeed, delete everything we did so far. */
1090 delete_insns_since (last
);
1092 op0_xhigh
= op0_high
, op1_xhigh
= op1_high
;
1096 && smul_widen_optab
->handlers
[(int) mode
].insn_code
1097 != CODE_FOR_nothing
)
1099 rtx wordm1
= GEN_INT (BITS_PER_WORD
- 1);
1100 product
= expand_binop (mode
, smul_widen_optab
, op0_low
, op1_low
,
1101 target
, 1, OPTAB_DIRECT
);
1102 op0_xhigh
= expand_binop (word_mode
, lshr_optab
, op0_low
, wordm1
,
1103 NULL_RTX
, 1, next_methods
);
1105 op0_xhigh
= expand_binop (word_mode
, add_optab
, op0_high
,
1106 op0_xhigh
, op0_xhigh
, 0, next_methods
);
1109 op0_xhigh
= expand_binop (word_mode
, ashr_optab
, op0_low
, wordm1
,
1110 NULL_RTX
, 0, next_methods
);
1112 op0_xhigh
= expand_binop (word_mode
, sub_optab
, op0_high
,
1113 op0_xhigh
, op0_xhigh
, 0,
1117 op1_xhigh
= expand_binop (word_mode
, lshr_optab
, op1_low
, wordm1
,
1118 NULL_RTX
, 1, next_methods
);
1120 op1_xhigh
= expand_binop (word_mode
, add_optab
, op1_high
,
1121 op1_xhigh
, op1_xhigh
, 0, next_methods
);
1124 op1_xhigh
= expand_binop (word_mode
, ashr_optab
, op1_low
, wordm1
,
1125 NULL_RTX
, 0, next_methods
);
1127 op1_xhigh
= expand_binop (word_mode
, sub_optab
, op1_high
,
1128 op1_xhigh
, op1_xhigh
, 0,
1133 /* If we have been able to directly compute the product of the
1134 low-order words of the operands and perform any required adjustments
1135 of the operands, we proceed by trying two more multiplications
1136 and then computing the appropriate sum.
1138 We have checked above that the required addition is provided.
1139 Full-word addition will normally always succeed, especially if
1140 it is provided at all, so we don't worry about its failure. The
1141 multiplication may well fail, however, so we do handle that. */
1143 if (product
&& op0_xhigh
&& op1_xhigh
)
1145 rtx product_high
= operand_subword (product
, high
, 1, mode
);
1146 rtx temp
= expand_binop (word_mode
, binoptab
, op0_low
, op1_xhigh
,
1147 NULL_RTX
, 0, OPTAB_DIRECT
);
1150 temp
= expand_binop (word_mode
, add_optab
, temp
, product_high
,
1151 product_high
, 0, next_methods
);
1153 if (temp
!= 0 && temp
!= product_high
)
1154 emit_move_insn (product_high
, temp
);
1157 temp
= expand_binop (word_mode
, binoptab
, op1_low
, op0_xhigh
,
1158 NULL_RTX
, 0, OPTAB_DIRECT
);
1161 temp
= expand_binop (word_mode
, add_optab
, temp
,
1162 product_high
, product_high
,
1165 if (temp
!= 0 && temp
!= product_high
)
1166 emit_move_insn (product_high
, temp
);
1170 if (mov_optab
->handlers
[(int) mode
].insn_code
!= CODE_FOR_nothing
)
1172 temp
= emit_move_insn (product
, product
);
1174 = gen_rtx_EXPR_LIST (REG_EQUAL
,
1175 gen_rtx_fmt_ee (MULT
, mode
,
1184 /* If we get here, we couldn't do it for some reason even though we
1185 originally thought we could. Delete anything we've emitted in
1188 delete_insns_since (last
);
1191 /* We need to open-code the complex type operations: '+, -, * and /' */
1193 /* At this point we allow operations between two similar complex
1194 numbers, and also if one of the operands is not a complex number
1195 but rather of MODE_FLOAT or MODE_INT. However, the caller
1196 must make sure that the MODE of the non-complex operand matches
1197 the SUBMODE of the complex operand. */
1199 if (class == MODE_COMPLEX_FLOAT
|| class == MODE_COMPLEX_INT
)
1201 rtx real0
= 0, imag0
= 0;
1202 rtx real1
= 0, imag1
= 0;
1203 rtx realr
, imagr
, res
;
1208 /* Find the correct mode for the real and imaginary parts */
1209 enum machine_mode submode
1210 = mode_for_size (GET_MODE_UNIT_SIZE (mode
) * BITS_PER_UNIT
,
1211 class == MODE_COMPLEX_INT
? MODE_INT
: MODE_FLOAT
,
1214 if (submode
== BLKmode
)
1218 target
= gen_reg_rtx (mode
);
1222 realr
= gen_realpart (submode
, target
);
1223 imagr
= gen_imagpart (submode
, target
);
1225 if (GET_MODE (op0
) == mode
)
1227 real0
= gen_realpart (submode
, op0
);
1228 imag0
= gen_imagpart (submode
, op0
);
1233 if (GET_MODE (op1
) == mode
)
1235 real1
= gen_realpart (submode
, op1
);
1236 imag1
= gen_imagpart (submode
, op1
);
1241 if (real0
== 0 || real1
== 0 || ! (imag0
!= 0|| imag1
!= 0))
1244 switch (binoptab
->code
)
1247 /* (a+ib) + (c+id) = (a+c) + i(b+d) */
1249 /* (a+ib) - (c+id) = (a-c) + i(b-d) */
1250 res
= expand_binop (submode
, binoptab
, real0
, real1
,
1251 realr
, unsignedp
, methods
);
1255 else if (res
!= realr
)
1256 emit_move_insn (realr
, res
);
1259 res
= expand_binop (submode
, binoptab
, imag0
, imag1
,
1260 imagr
, unsignedp
, methods
);
1263 else if (binoptab
->code
== MINUS
)
1264 res
= expand_unop (submode
, neg_optab
, imag1
, imagr
, unsignedp
);
1270 else if (res
!= imagr
)
1271 emit_move_insn (imagr
, res
);
1277 /* (a+ib) * (c+id) = (ac-bd) + i(ad+cb) */
1283 /* Don't fetch these from memory more than once. */
1284 real0
= force_reg (submode
, real0
);
1285 real1
= force_reg (submode
, real1
);
1286 imag0
= force_reg (submode
, imag0
);
1287 imag1
= force_reg (submode
, imag1
);
1289 temp1
= expand_binop (submode
, binoptab
, real0
, real1
, NULL_RTX
,
1290 unsignedp
, methods
);
1292 temp2
= expand_binop (submode
, binoptab
, imag0
, imag1
, NULL_RTX
,
1293 unsignedp
, methods
);
1295 if (temp1
== 0 || temp2
== 0)
1298 res
= expand_binop (submode
, sub_optab
, temp1
, temp2
,
1299 realr
, unsignedp
, methods
);
1303 else if (res
!= realr
)
1304 emit_move_insn (realr
, res
);
1306 temp1
= expand_binop (submode
, binoptab
, real0
, imag1
,
1307 NULL_RTX
, unsignedp
, methods
);
1309 temp2
= expand_binop (submode
, binoptab
, real1
, imag0
,
1310 NULL_RTX
, unsignedp
, methods
);
1312 if (temp1
== 0 || temp2
== 0)
1315 res
= expand_binop (submode
, add_optab
, temp1
, temp2
,
1316 imagr
, unsignedp
, methods
);
1320 else if (res
!= imagr
)
1321 emit_move_insn (imagr
, res
);
1327 /* Don't fetch these from memory more than once. */
1328 real0
= force_reg (submode
, real0
);
1329 real1
= force_reg (submode
, real1
);
1331 res
= expand_binop (submode
, binoptab
, real0
, real1
,
1332 realr
, unsignedp
, methods
);
1335 else if (res
!= realr
)
1336 emit_move_insn (realr
, res
);
1339 res
= expand_binop (submode
, binoptab
,
1340 real1
, imag0
, imagr
, unsignedp
, methods
);
1342 res
= expand_binop (submode
, binoptab
,
1343 real0
, imag1
, imagr
, unsignedp
, methods
);
1347 else if (res
!= imagr
)
1348 emit_move_insn (imagr
, res
);
1355 /* (a+ib) / (c+id) = ((ac+bd)/(cc+dd)) + i((bc-ad)/(cc+dd)) */
1359 /* (a+ib) / (c+i0) = (a/c) + i(b/c) */
1361 /* Don't fetch these from memory more than once. */
1362 real1
= force_reg (submode
, real1
);
1364 /* Simply divide the real and imaginary parts by `c' */
1365 if (class == MODE_COMPLEX_FLOAT
)
1366 res
= expand_binop (submode
, binoptab
, real0
, real1
,
1367 realr
, unsignedp
, methods
);
1369 res
= expand_divmod (0, TRUNC_DIV_EXPR
, submode
,
1370 real0
, real1
, realr
, unsignedp
);
1374 else if (res
!= realr
)
1375 emit_move_insn (realr
, res
);
1377 if (class == MODE_COMPLEX_FLOAT
)
1378 res
= expand_binop (submode
, binoptab
, imag0
, real1
,
1379 imagr
, unsignedp
, methods
);
1381 res
= expand_divmod (0, TRUNC_DIV_EXPR
, submode
,
1382 imag0
, real1
, imagr
, unsignedp
);
1386 else if (res
!= imagr
)
1387 emit_move_insn (imagr
, res
);
1393 /* Divisor is of complex type:
1399 /* Don't fetch these from memory more than once. */
1400 real0
= force_reg (submode
, real0
);
1401 real1
= force_reg (submode
, real1
);
1404 imag0
= force_reg (submode
, imag0
);
1406 imag1
= force_reg (submode
, imag1
);
1408 /* Divisor: c*c + d*d */
1409 temp1
= expand_binop (submode
, smul_optab
, real1
, real1
,
1410 NULL_RTX
, unsignedp
, methods
);
1412 temp2
= expand_binop (submode
, smul_optab
, imag1
, imag1
,
1413 NULL_RTX
, unsignedp
, methods
);
1415 if (temp1
== 0 || temp2
== 0)
1418 divisor
= expand_binop (submode
, add_optab
, temp1
, temp2
,
1419 NULL_RTX
, unsignedp
, methods
);
1425 /* ((a)(c-id))/divisor */
1426 /* (a+i0) / (c+id) = (ac/(cc+dd)) + i(-ad/(cc+dd)) */
1428 /* Calculate the dividend */
1429 real_t
= expand_binop (submode
, smul_optab
, real0
, real1
,
1430 NULL_RTX
, unsignedp
, methods
);
1432 imag_t
= expand_binop (submode
, smul_optab
, real0
, imag1
,
1433 NULL_RTX
, unsignedp
, methods
);
1435 if (real_t
== 0 || imag_t
== 0)
1438 imag_t
= expand_unop (submode
, neg_optab
, imag_t
,
1439 NULL_RTX
, unsignedp
);
1443 /* ((a+ib)(c-id))/divider */
1444 /* Calculate the dividend */
1445 temp1
= expand_binop (submode
, smul_optab
, real0
, real1
,
1446 NULL_RTX
, unsignedp
, methods
);
1448 temp2
= expand_binop (submode
, smul_optab
, imag0
, imag1
,
1449 NULL_RTX
, unsignedp
, methods
);
1451 if (temp1
== 0 || temp2
== 0)
1454 real_t
= expand_binop (submode
, add_optab
, temp1
, temp2
,
1455 NULL_RTX
, unsignedp
, methods
);
1457 temp1
= expand_binop (submode
, smul_optab
, imag0
, real1
,
1458 NULL_RTX
, unsignedp
, methods
);
1460 temp2
= expand_binop (submode
, smul_optab
, real0
, imag1
,
1461 NULL_RTX
, unsignedp
, methods
);
1463 if (temp1
== 0 || temp2
== 0)
1466 imag_t
= expand_binop (submode
, sub_optab
, temp1
, temp2
,
1467 NULL_RTX
, unsignedp
, methods
);
1469 if (real_t
== 0 || imag_t
== 0)
1473 if (class == MODE_COMPLEX_FLOAT
)
1474 res
= expand_binop (submode
, binoptab
, real_t
, divisor
,
1475 realr
, unsignedp
, methods
);
1477 res
= expand_divmod (0, TRUNC_DIV_EXPR
, submode
,
1478 real_t
, divisor
, realr
, unsignedp
);
1482 else if (res
!= realr
)
1483 emit_move_insn (realr
, res
);
1485 if (class == MODE_COMPLEX_FLOAT
)
1486 res
= expand_binop (submode
, binoptab
, imag_t
, divisor
,
1487 imagr
, unsignedp
, methods
);
1489 res
= expand_divmod (0, TRUNC_DIV_EXPR
, submode
,
1490 imag_t
, divisor
, imagr
, unsignedp
);
1494 else if (res
!= imagr
)
1495 emit_move_insn (imagr
, res
);
1510 if (binoptab
->code
!= UNKNOWN
)
1512 = gen_rtx_fmt_ee (binoptab
->code
, mode
,
1513 copy_rtx (op0
), copy_rtx (op1
));
1517 emit_no_conflict_block (seq
, target
, op0
, op1
, equiv_value
);
1523 /* It can't be open-coded in this mode.
1524 Use a library call if one is available and caller says that's ok. */
1526 if (binoptab
->handlers
[(int) mode
].libfunc
1527 && (methods
== OPTAB_LIB
|| methods
== OPTAB_LIB_WIDEN
))
1531 enum machine_mode op1_mode
= mode
;
1538 op1_mode
= word_mode
;
1539 /* Specify unsigned here,
1540 since negative shift counts are meaningless. */
1541 op1x
= convert_to_mode (word_mode
, op1
, 1);
1544 if (GET_MODE (op0
) != VOIDmode
1545 && GET_MODE (op0
) != mode
)
1546 op0
= convert_to_mode (mode
, op0
, unsignedp
);
1548 /* Pass 1 for NO_QUEUE so we don't lose any increments
1549 if the libcall is cse'd or moved. */
1550 value
= emit_library_call_value (binoptab
->handlers
[(int) mode
].libfunc
,
1551 NULL_RTX
, 1, mode
, 2,
1552 op0
, mode
, op1x
, op1_mode
);
1554 insns
= get_insns ();
1557 target
= gen_reg_rtx (mode
);
1558 emit_libcall_block (insns
, target
, value
,
1559 gen_rtx_fmt_ee (binoptab
->code
, mode
, op0
, op1
));
1564 delete_insns_since (last
);
1566 /* It can't be done in this mode. Can we do it in a wider mode? */
1568 if (! (methods
== OPTAB_WIDEN
|| methods
== OPTAB_LIB_WIDEN
1569 || methods
== OPTAB_MUST_WIDEN
))
1571 /* Caller says, don't even try. */
1572 delete_insns_since (entry_last
);
1576 /* Compute the value of METHODS to pass to recursive calls.
1577 Don't allow widening to be tried recursively. */
1579 methods
= (methods
== OPTAB_LIB_WIDEN
? OPTAB_LIB
: OPTAB_DIRECT
);
1581 /* Look for a wider mode of the same class for which it appears we can do
1584 if (class == MODE_INT
|| class == MODE_FLOAT
|| class == MODE_COMPLEX_FLOAT
)
1586 for (wider_mode
= GET_MODE_WIDER_MODE (mode
); wider_mode
!= VOIDmode
;
1587 wider_mode
= GET_MODE_WIDER_MODE (wider_mode
))
1589 if ((binoptab
->handlers
[(int) wider_mode
].insn_code
1590 != CODE_FOR_nothing
)
1591 || (methods
== OPTAB_LIB
1592 && binoptab
->handlers
[(int) wider_mode
].libfunc
))
1594 rtx xop0
= op0
, xop1
= op1
;
1597 /* For certain integer operations, we need not actually extend
1598 the narrow operands, as long as we will truncate
1599 the results to the same narrowness. */
1601 if ((binoptab
== ior_optab
|| binoptab
== and_optab
1602 || binoptab
== xor_optab
1603 || binoptab
== add_optab
|| binoptab
== sub_optab
1604 || binoptab
== smul_optab
|| binoptab
== ashl_optab
)
1605 && class == MODE_INT
)
1608 xop0
= widen_operand (xop0
, wider_mode
, mode
,
1609 unsignedp
, no_extend
);
1611 /* The second operand of a shift must always be extended. */
1612 xop1
= widen_operand (xop1
, wider_mode
, mode
, unsignedp
,
1613 no_extend
&& binoptab
!= ashl_optab
);
1615 temp
= expand_binop (wider_mode
, binoptab
, xop0
, xop1
, NULL_RTX
,
1616 unsignedp
, methods
);
1619 if (class != MODE_INT
)
1622 target
= gen_reg_rtx (mode
);
1623 convert_move (target
, temp
, 0);
1627 return gen_lowpart (mode
, temp
);
1630 delete_insns_since (last
);
1635 delete_insns_since (entry_last
);
1639 /* Expand a binary operator which has both signed and unsigned forms.
1640 UOPTAB is the optab for unsigned operations, and SOPTAB is for
1643 If we widen unsigned operands, we may use a signed wider operation instead
1644 of an unsigned wider operation, since the result would be the same. */
1647 sign_expand_binop (mode
, uoptab
, soptab
, op0
, op1
, target
, unsignedp
, methods
)
1648 enum machine_mode mode
;
1649 optab uoptab
, soptab
;
1650 rtx op0
, op1
, target
;
1652 enum optab_methods methods
;
1655 optab direct_optab
= unsignedp
? uoptab
: soptab
;
1656 struct optab wide_soptab
;
1658 /* Do it without widening, if possible. */
1659 temp
= expand_binop (mode
, direct_optab
, op0
, op1
, target
,
1660 unsignedp
, OPTAB_DIRECT
);
1661 if (temp
|| methods
== OPTAB_DIRECT
)
1664 /* Try widening to a signed int. Make a fake signed optab that
1665 hides any signed insn for direct use. */
1666 wide_soptab
= *soptab
;
1667 wide_soptab
.handlers
[(int) mode
].insn_code
= CODE_FOR_nothing
;
1668 wide_soptab
.handlers
[(int) mode
].libfunc
= 0;
1670 temp
= expand_binop (mode
, &wide_soptab
, op0
, op1
, target
,
1671 unsignedp
, OPTAB_WIDEN
);
1673 /* For unsigned operands, try widening to an unsigned int. */
1674 if (temp
== 0 && unsignedp
)
1675 temp
= expand_binop (mode
, uoptab
, op0
, op1
, target
,
1676 unsignedp
, OPTAB_WIDEN
);
1677 if (temp
|| methods
== OPTAB_WIDEN
)
1680 /* Use the right width lib call if that exists. */
1681 temp
= expand_binop (mode
, direct_optab
, op0
, op1
, target
, unsignedp
, OPTAB_LIB
);
1682 if (temp
|| methods
== OPTAB_LIB
)
1685 /* Must widen and use a lib call, use either signed or unsigned. */
1686 temp
= expand_binop (mode
, &wide_soptab
, op0
, op1
, target
,
1687 unsignedp
, methods
);
1691 return expand_binop (mode
, uoptab
, op0
, op1
, target
,
1692 unsignedp
, methods
);
1696 /* Generate code to perform an operation specified by BINOPTAB
1697 on operands OP0 and OP1, with two results to TARG1 and TARG2.
1698 We assume that the order of the operands for the instruction
1699 is TARG0, OP0, OP1, TARG1, which would fit a pattern like
1700 [(set TARG0 (operate OP0 OP1)) (set TARG1 (operate ...))].
1702 Either TARG0 or TARG1 may be zero, but what that means is that
1703 the result is not actually wanted. We will generate it into
1704 a dummy pseudo-reg and discard it. They may not both be zero.
1706 Returns 1 if this operation can be performed; 0 if not. */
1709 expand_twoval_binop (binoptab
, op0
, op1
, targ0
, targ1
, unsignedp
)
1715 enum machine_mode mode
= GET_MODE (targ0
? targ0
: targ1
);
1716 enum mode_class
class;
1717 enum machine_mode wider_mode
;
1718 rtx entry_last
= get_last_insn ();
1721 class = GET_MODE_CLASS (mode
);
1723 op0
= protect_from_queue (op0
, 0);
1724 op1
= protect_from_queue (op1
, 0);
1728 op0
= force_not_mem (op0
);
1729 op1
= force_not_mem (op1
);
1732 /* If we are inside an appropriately-short loop and one operand is an
1733 expensive constant, force it into a register. */
1734 if (CONSTANT_P (op0
) && preserve_subexpressions_p ()
1735 && rtx_cost (op0
, binoptab
->code
) > 2)
1736 op0
= force_reg (mode
, op0
);
1738 if (CONSTANT_P (op1
) && preserve_subexpressions_p ()
1739 && rtx_cost (op1
, binoptab
->code
) > 2)
1740 op1
= force_reg (mode
, op1
);
1743 targ0
= protect_from_queue (targ0
, 1);
1745 targ0
= gen_reg_rtx (mode
);
1747 targ1
= protect_from_queue (targ1
, 1);
1749 targ1
= gen_reg_rtx (mode
);
1751 /* Record where to go back to if we fail. */
1752 last
= get_last_insn ();
1754 if (binoptab
->handlers
[(int) mode
].insn_code
!= CODE_FOR_nothing
)
1756 int icode
= (int) binoptab
->handlers
[(int) mode
].insn_code
;
1757 enum machine_mode mode0
= insn_operand_mode
[icode
][1];
1758 enum machine_mode mode1
= insn_operand_mode
[icode
][2];
1760 rtx xop0
= op0
, xop1
= op1
;
1762 /* In case this insn wants input operands in modes different from the
1763 result, convert the operands. */
1764 if (GET_MODE (op0
) != VOIDmode
&& GET_MODE (op0
) != mode0
)
1765 xop0
= convert_to_mode (mode0
, xop0
, unsignedp
);
1767 if (GET_MODE (op1
) != VOIDmode
&& GET_MODE (op1
) != mode1
)
1768 xop1
= convert_to_mode (mode1
, xop1
, unsignedp
);
1770 /* Now, if insn doesn't accept these operands, put them into pseudos. */
1771 if (! (*insn_operand_predicate
[icode
][1]) (xop0
, mode0
))
1772 xop0
= copy_to_mode_reg (mode0
, xop0
);
1774 if (! (*insn_operand_predicate
[icode
][2]) (xop1
, mode1
))
1775 xop1
= copy_to_mode_reg (mode1
, xop1
);
1777 /* We could handle this, but we should always be called with a pseudo
1778 for our targets and all insns should take them as outputs. */
1779 if (! (*insn_operand_predicate
[icode
][0]) (targ0
, mode
)
1780 || ! (*insn_operand_predicate
[icode
][3]) (targ1
, mode
))
1783 pat
= GEN_FCN (icode
) (targ0
, xop0
, xop1
, targ1
);
1790 delete_insns_since (last
);
1793 /* It can't be done in this mode. Can we do it in a wider mode? */
1795 if (class == MODE_INT
|| class == MODE_FLOAT
|| class == MODE_COMPLEX_FLOAT
)
1797 for (wider_mode
= GET_MODE_WIDER_MODE (mode
); wider_mode
!= VOIDmode
;
1798 wider_mode
= GET_MODE_WIDER_MODE (wider_mode
))
1800 if (binoptab
->handlers
[(int) wider_mode
].insn_code
1801 != CODE_FOR_nothing
)
1803 register rtx t0
= gen_reg_rtx (wider_mode
);
1804 register rtx t1
= gen_reg_rtx (wider_mode
);
1806 if (expand_twoval_binop (binoptab
,
1807 convert_modes (wider_mode
, mode
, op0
,
1809 convert_modes (wider_mode
, mode
, op1
,
1813 convert_move (targ0
, t0
, unsignedp
);
1814 convert_move (targ1
, t1
, unsignedp
);
1818 delete_insns_since (last
);
1823 delete_insns_since (entry_last
);
1827 /* Generate code to perform an operation specified by UNOPTAB
1828 on operand OP0, with result having machine-mode MODE.
1830 UNSIGNEDP is for the case where we have to widen the operands
1831 to perform the operation. It says to use zero-extension.
1833 If TARGET is nonzero, the value
1834 is generated there, if it is convenient to do so.
1835 In all cases an rtx is returned for the locus of the value;
1836 this may or may not be TARGET. */
1839 expand_unop (mode
, unoptab
, op0
, target
, unsignedp
)
1840 enum machine_mode mode
;
1846 enum mode_class
class;
1847 enum machine_mode wider_mode
;
1849 rtx last
= get_last_insn ();
1852 class = GET_MODE_CLASS (mode
);
1854 op0
= protect_from_queue (op0
, 0);
1858 op0
= force_not_mem (op0
);
1862 target
= protect_from_queue (target
, 1);
1864 if (unoptab
->handlers
[(int) mode
].insn_code
!= CODE_FOR_nothing
)
1866 int icode
= (int) unoptab
->handlers
[(int) mode
].insn_code
;
1867 enum machine_mode mode0
= insn_operand_mode
[icode
][1];
1873 temp
= gen_reg_rtx (mode
);
1875 if (GET_MODE (xop0
) != VOIDmode
1876 && GET_MODE (xop0
) != mode0
)
1877 xop0
= convert_to_mode (mode0
, xop0
, unsignedp
);
1879 /* Now, if insn doesn't accept our operand, put it into a pseudo. */
1881 if (! (*insn_operand_predicate
[icode
][1]) (xop0
, mode0
))
1882 xop0
= copy_to_mode_reg (mode0
, xop0
);
1884 if (! (*insn_operand_predicate
[icode
][0]) (temp
, mode
))
1885 temp
= gen_reg_rtx (mode
);
1887 pat
= GEN_FCN (icode
) (temp
, xop0
);
1890 if (GET_CODE (pat
) == SEQUENCE
1891 && ! add_equal_note (pat
, temp
, unoptab
->code
, xop0
, NULL_RTX
))
1893 delete_insns_since (last
);
1894 return expand_unop (mode
, unoptab
, op0
, NULL_RTX
, unsignedp
);
1902 delete_insns_since (last
);
1905 /* It can't be done in this mode. Can we open-code it in a wider mode? */
1907 if (class == MODE_INT
|| class == MODE_FLOAT
|| class == MODE_COMPLEX_FLOAT
)
1908 for (wider_mode
= GET_MODE_WIDER_MODE (mode
); wider_mode
!= VOIDmode
;
1909 wider_mode
= GET_MODE_WIDER_MODE (wider_mode
))
1911 if (unoptab
->handlers
[(int) wider_mode
].insn_code
!= CODE_FOR_nothing
)
1915 /* For certain operations, we need not actually extend
1916 the narrow operand, as long as we will truncate the
1917 results to the same narrowness. */
1919 xop0
= widen_operand (xop0
, wider_mode
, mode
, unsignedp
,
1920 (unoptab
== neg_optab
1921 || unoptab
== one_cmpl_optab
)
1922 && class == MODE_INT
);
1924 temp
= expand_unop (wider_mode
, unoptab
, xop0
, NULL_RTX
,
1929 if (class != MODE_INT
)
1932 target
= gen_reg_rtx (mode
);
1933 convert_move (target
, temp
, 0);
1937 return gen_lowpart (mode
, temp
);
1940 delete_insns_since (last
);
1944 /* These can be done a word at a time. */
1945 if (unoptab
== one_cmpl_optab
1946 && class == MODE_INT
1947 && GET_MODE_SIZE (mode
) > UNITS_PER_WORD
1948 && unoptab
->handlers
[(int) word_mode
].insn_code
!= CODE_FOR_nothing
)
1953 if (target
== 0 || target
== op0
)
1954 target
= gen_reg_rtx (mode
);
1958 /* Do the actual arithmetic. */
1959 for (i
= 0; i
< GET_MODE_BITSIZE (mode
) / BITS_PER_WORD
; i
++)
1961 rtx target_piece
= operand_subword (target
, i
, 1, mode
);
1962 rtx x
= expand_unop (word_mode
, unoptab
,
1963 operand_subword_force (op0
, i
, mode
),
1964 target_piece
, unsignedp
);
1965 if (target_piece
!= x
)
1966 emit_move_insn (target_piece
, x
);
1969 insns
= get_insns ();
1972 emit_no_conflict_block (insns
, target
, op0
, NULL_RTX
,
1973 gen_rtx_fmt_e (unoptab
->code
, mode
,
1978 /* Open-code the complex negation operation. */
1979 else if (unoptab
== neg_optab
1980 && (class == MODE_COMPLEX_FLOAT
|| class == MODE_COMPLEX_INT
))
1986 /* Find the correct mode for the real and imaginary parts */
1987 enum machine_mode submode
1988 = mode_for_size (GET_MODE_UNIT_SIZE (mode
) * BITS_PER_UNIT
,
1989 class == MODE_COMPLEX_INT
? MODE_INT
: MODE_FLOAT
,
1992 if (submode
== BLKmode
)
1996 target
= gen_reg_rtx (mode
);
2000 target_piece
= gen_imagpart (submode
, target
);
2001 x
= expand_unop (submode
, unoptab
,
2002 gen_imagpart (submode
, op0
),
2003 target_piece
, unsignedp
);
2004 if (target_piece
!= x
)
2005 emit_move_insn (target_piece
, x
);
2007 target_piece
= gen_realpart (submode
, target
);
2008 x
= expand_unop (submode
, unoptab
,
2009 gen_realpart (submode
, op0
),
2010 target_piece
, unsignedp
);
2011 if (target_piece
!= x
)
2012 emit_move_insn (target_piece
, x
);
2017 emit_no_conflict_block (seq
, target
, op0
, 0,
2018 gen_rtx_fmt_e (unoptab
->code
, mode
,
2023 /* Now try a library call in this mode. */
2024 if (unoptab
->handlers
[(int) mode
].libfunc
)
2031 /* Pass 1 for NO_QUEUE so we don't lose any increments
2032 if the libcall is cse'd or moved. */
2033 value
= emit_library_call_value (unoptab
->handlers
[(int) mode
].libfunc
,
2034 NULL_RTX
, 1, mode
, 1, op0
, mode
);
2035 insns
= get_insns ();
2038 target
= gen_reg_rtx (mode
);
2039 emit_libcall_block (insns
, target
, value
,
2040 gen_rtx_fmt_e (unoptab
->code
, mode
, op0
));
2045 /* It can't be done in this mode. Can we do it in a wider mode? */
2047 if (class == MODE_INT
|| class == MODE_FLOAT
|| class == MODE_COMPLEX_FLOAT
)
2049 for (wider_mode
= GET_MODE_WIDER_MODE (mode
); wider_mode
!= VOIDmode
;
2050 wider_mode
= GET_MODE_WIDER_MODE (wider_mode
))
2052 if ((unoptab
->handlers
[(int) wider_mode
].insn_code
2053 != CODE_FOR_nothing
)
2054 || unoptab
->handlers
[(int) wider_mode
].libfunc
)
2058 /* For certain operations, we need not actually extend
2059 the narrow operand, as long as we will truncate the
2060 results to the same narrowness. */
2062 xop0
= widen_operand (xop0
, wider_mode
, mode
, unsignedp
,
2063 (unoptab
== neg_optab
2064 || unoptab
== one_cmpl_optab
)
2065 && class == MODE_INT
);
2067 temp
= expand_unop (wider_mode
, unoptab
, xop0
, NULL_RTX
,
2072 if (class != MODE_INT
)
2075 target
= gen_reg_rtx (mode
);
2076 convert_move (target
, temp
, 0);
2080 return gen_lowpart (mode
, temp
);
2083 delete_insns_since (last
);
2088 /* If there is no negate operation, try doing a subtract from zero.
2089 The US Software GOFAST library needs this. */
2090 if (unoptab
== neg_optab
)
2093 temp
= expand_binop (mode
, sub_optab
, CONST0_RTX (mode
), op0
,
2094 target
, unsignedp
, OPTAB_LIB_WIDEN
);
2102 /* Emit code to compute the absolute value of OP0, with result to
2103 TARGET if convenient. (TARGET may be 0.) The return value says
2104 where the result actually is to be found.
2106 MODE is the mode of the operand; the mode of the result is
2107 different but can be deduced from MODE.
2109 UNSIGNEDP is relevant if extension is needed. */
2112 expand_abs (mode
, op0
, target
, unsignedp
, safe
)
2113 enum machine_mode mode
;
2121 /* First try to do it with a special abs instruction. */
2122 temp
= expand_unop (mode
, abs_optab
, op0
, target
, 0);
2126 /* If this machine has expensive jumps, we can do integer absolute
2127 value of X as (((signed) x >> (W-1)) ^ x) - ((signed) x >> (W-1)),
2128 where W is the width of MODE. */
2130 if (GET_MODE_CLASS (mode
) == MODE_INT
&& BRANCH_COST
>= 2)
2132 rtx extended
= expand_shift (RSHIFT_EXPR
, mode
, op0
,
2133 size_int (GET_MODE_BITSIZE (mode
) - 1),
2136 temp
= expand_binop (mode
, xor_optab
, extended
, op0
, target
, 0,
2139 temp
= expand_binop (mode
, sub_optab
, temp
, extended
, target
, 0,
2146 /* If that does not win, use conditional jump and negate. */
2148 /* It is safe to use the target if it is the same
2149 as the source if this is also a pseudo register */
2150 if (op0
== target
&& GET_CODE (op0
) == REG
2151 && REGNO (op0
) >= FIRST_PSEUDO_REGISTER
)
2154 op1
= gen_label_rtx ();
2155 if (target
== 0 || ! safe
2156 || GET_MODE (target
) != mode
2157 || (GET_CODE (target
) == MEM
&& MEM_VOLATILE_P (target
))
2158 || (GET_CODE (target
) == REG
2159 && REGNO (target
) < FIRST_PSEUDO_REGISTER
))
2160 target
= gen_reg_rtx (mode
);
2162 emit_move_insn (target
, op0
);
2165 /* If this mode is an integer too wide to compare properly,
2166 compare word by word. Rely on CSE to optimize constant cases. */
2167 if (GET_MODE_CLASS (mode
) == MODE_INT
&& ! can_compare_p (mode
))
2168 do_jump_by_parts_greater_rtx (mode
, 0, target
, const0_rtx
,
2172 temp
= compare_from_rtx (target
, CONST0_RTX (mode
), GE
, 0, mode
,
2174 if (temp
== const1_rtx
)
2176 else if (temp
!= const0_rtx
)
2178 if (bcc_gen_fctn
[(int) GET_CODE (temp
)] != 0)
2179 emit_jump_insn ((*bcc_gen_fctn
[(int) GET_CODE (temp
)]) (op1
));
2185 op0
= expand_unop (mode
, neg_optab
, target
, target
, 0);
2187 emit_move_insn (target
, op0
);
2193 /* Emit code to compute the absolute value of OP0, with result to
2194 TARGET if convenient. (TARGET may be 0.) The return value says
2195 where the result actually is to be found.
2197 MODE is the mode of the operand; the mode of the result is
2198 different but can be deduced from MODE.
2200 UNSIGNEDP is relevant for complex integer modes. */
2203 expand_complex_abs (mode
, op0
, target
, unsignedp
)
2204 enum machine_mode mode
;
2209 enum mode_class
class = GET_MODE_CLASS (mode
);
2210 enum machine_mode wider_mode
;
2212 rtx entry_last
= get_last_insn ();
2216 /* Find the correct mode for the real and imaginary parts. */
2217 enum machine_mode submode
2218 = mode_for_size (GET_MODE_UNIT_SIZE (mode
) * BITS_PER_UNIT
,
2219 class == MODE_COMPLEX_INT
? MODE_INT
: MODE_FLOAT
,
2222 if (submode
== BLKmode
)
2225 op0
= protect_from_queue (op0
, 0);
2229 op0
= force_not_mem (op0
);
2232 last
= get_last_insn ();
2235 target
= protect_from_queue (target
, 1);
2237 if (abs_optab
->handlers
[(int) mode
].insn_code
!= CODE_FOR_nothing
)
2239 int icode
= (int) abs_optab
->handlers
[(int) mode
].insn_code
;
2240 enum machine_mode mode0
= insn_operand_mode
[icode
][1];
2246 temp
= gen_reg_rtx (submode
);
2248 if (GET_MODE (xop0
) != VOIDmode
2249 && GET_MODE (xop0
) != mode0
)
2250 xop0
= convert_to_mode (mode0
, xop0
, unsignedp
);
2252 /* Now, if insn doesn't accept our operand, put it into a pseudo. */
2254 if (! (*insn_operand_predicate
[icode
][1]) (xop0
, mode0
))
2255 xop0
= copy_to_mode_reg (mode0
, xop0
);
2257 if (! (*insn_operand_predicate
[icode
][0]) (temp
, submode
))
2258 temp
= gen_reg_rtx (submode
);
2260 pat
= GEN_FCN (icode
) (temp
, xop0
);
2263 if (GET_CODE (pat
) == SEQUENCE
2264 && ! add_equal_note (pat
, temp
, abs_optab
->code
, xop0
, NULL_RTX
))
2266 delete_insns_since (last
);
2267 return expand_unop (mode
, abs_optab
, op0
, NULL_RTX
, unsignedp
);
2275 delete_insns_since (last
);
2278 /* It can't be done in this mode. Can we open-code it in a wider mode? */
2280 for (wider_mode
= GET_MODE_WIDER_MODE (mode
); wider_mode
!= VOIDmode
;
2281 wider_mode
= GET_MODE_WIDER_MODE (wider_mode
))
2283 if (abs_optab
->handlers
[(int) wider_mode
].insn_code
!= CODE_FOR_nothing
)
2287 xop0
= convert_modes (wider_mode
, mode
, xop0
, unsignedp
);
2288 temp
= expand_complex_abs (wider_mode
, xop0
, NULL_RTX
, unsignedp
);
2292 if (class != MODE_COMPLEX_INT
)
2295 target
= gen_reg_rtx (submode
);
2296 convert_move (target
, temp
, 0);
2300 return gen_lowpart (submode
, temp
);
2303 delete_insns_since (last
);
2307 /* Open-code the complex absolute-value operation
2308 if we can open-code sqrt. Otherwise it's not worth while. */
2309 if (sqrt_optab
->handlers
[(int) submode
].insn_code
!= CODE_FOR_nothing
)
2311 rtx real
, imag
, total
;
2313 real
= gen_realpart (submode
, op0
);
2314 imag
= gen_imagpart (submode
, op0
);
2316 /* Square both parts. */
2317 real
= expand_mult (submode
, real
, real
, NULL_RTX
, 0);
2318 imag
= expand_mult (submode
, imag
, imag
, NULL_RTX
, 0);
2320 /* Sum the parts. */
2321 total
= expand_binop (submode
, add_optab
, real
, imag
, NULL_RTX
,
2322 0, OPTAB_LIB_WIDEN
);
2324 /* Get sqrt in TARGET. Set TARGET to where the result is. */
2325 target
= expand_unop (submode
, sqrt_optab
, total
, target
, 0);
2327 delete_insns_since (last
);
2332 /* Now try a library call in this mode. */
2333 if (abs_optab
->handlers
[(int) mode
].libfunc
)
2340 /* Pass 1 for NO_QUEUE so we don't lose any increments
2341 if the libcall is cse'd or moved. */
2342 value
= emit_library_call_value (abs_optab
->handlers
[(int) mode
].libfunc
,
2343 NULL_RTX
, 1, submode
, 1, op0
, mode
);
2344 insns
= get_insns ();
2347 target
= gen_reg_rtx (submode
);
2348 emit_libcall_block (insns
, target
, value
,
2349 gen_rtx_fmt_e (abs_optab
->code
, mode
, op0
));
2354 /* It can't be done in this mode. Can we do it in a wider mode? */
2356 for (wider_mode
= GET_MODE_WIDER_MODE (mode
); wider_mode
!= VOIDmode
;
2357 wider_mode
= GET_MODE_WIDER_MODE (wider_mode
))
2359 if ((abs_optab
->handlers
[(int) wider_mode
].insn_code
2360 != CODE_FOR_nothing
)
2361 || abs_optab
->handlers
[(int) wider_mode
].libfunc
)
2365 xop0
= convert_modes (wider_mode
, mode
, xop0
, unsignedp
);
2367 temp
= expand_complex_abs (wider_mode
, xop0
, NULL_RTX
, unsignedp
);
2371 if (class != MODE_COMPLEX_INT
)
2374 target
= gen_reg_rtx (submode
);
2375 convert_move (target
, temp
, 0);
2379 return gen_lowpart (submode
, temp
);
2382 delete_insns_since (last
);
2386 delete_insns_since (entry_last
);
2390 /* Generate an instruction whose insn-code is INSN_CODE,
2391 with two operands: an output TARGET and an input OP0.
2392 TARGET *must* be nonzero, and the output is always stored there.
2393 CODE is an rtx code such that (CODE OP0) is an rtx that describes
2394 the value that is stored into TARGET. */
2397 emit_unop_insn (icode
, target
, op0
, code
)
2404 enum machine_mode mode0
= insn_operand_mode
[icode
][1];
2407 temp
= target
= protect_from_queue (target
, 1);
2409 op0
= protect_from_queue (op0
, 0);
2411 /* Sign and zero extension from memory is often done specially on
2412 RISC machines, so forcing into a register here can pessimize
2414 if (flag_force_mem
&& code
!= SIGN_EXTEND
&& code
!= ZERO_EXTEND
)
2415 op0
= force_not_mem (op0
);
2417 /* Now, if insn does not accept our operands, put them into pseudos. */
2419 if (! (*insn_operand_predicate
[icode
][1]) (op0
, mode0
))
2420 op0
= copy_to_mode_reg (mode0
, op0
);
2422 if (! (*insn_operand_predicate
[icode
][0]) (temp
, GET_MODE (temp
))
2423 || (flag_force_mem
&& GET_CODE (temp
) == MEM
))
2424 temp
= gen_reg_rtx (GET_MODE (temp
));
2426 pat
= GEN_FCN (icode
) (temp
, op0
);
2428 if (GET_CODE (pat
) == SEQUENCE
&& code
!= UNKNOWN
)
2429 add_equal_note (pat
, temp
, code
, op0
, NULL_RTX
);
2434 emit_move_insn (target
, temp
);
2437 /* Emit code to perform a series of operations on a multi-word quantity, one
2440 Such a block is preceded by a CLOBBER of the output, consists of multiple
2441 insns, each setting one word of the output, and followed by a SET copying
2442 the output to itself.
2444 Each of the insns setting words of the output receives a REG_NO_CONFLICT
2445 note indicating that it doesn't conflict with the (also multi-word)
2446 inputs. The entire block is surrounded by REG_LIBCALL and REG_RETVAL
2449 INSNS is a block of code generated to perform the operation, not including
2450 the CLOBBER and final copy. All insns that compute intermediate values
2451 are first emitted, followed by the block as described above.
2453 TARGET, OP0, and OP1 are the output and inputs of the operations,
2454 respectively. OP1 may be zero for a unary operation.
2456 EQUIV, if non-zero, is an expression to be placed into a REG_EQUAL note
2459 If TARGET is not a register, INSNS is simply emitted with no special
2460 processing. Likewise if anything in INSNS is not an INSN or if
2461 there is a libcall block inside INSNS.
2463 The final insn emitted is returned. */
2466 emit_no_conflict_block (insns
, target
, op0
, op1
, equiv
)
2472 rtx prev
, next
, first
, last
, insn
;
2474 if (GET_CODE (target
) != REG
|| reload_in_progress
)
2475 return emit_insns (insns
);
2477 for (insn
= insns
; insn
; insn
= NEXT_INSN (insn
))
2478 if (GET_CODE (insn
) != INSN
2479 || find_reg_note (insn
, REG_LIBCALL
, NULL_RTX
))
2480 return emit_insns (insns
);
2482 /* First emit all insns that do not store into words of the output and remove
2483 these from the list. */
2484 for (insn
= insns
; insn
; insn
= next
)
2489 next
= NEXT_INSN (insn
);
2491 if (GET_CODE (PATTERN (insn
)) == SET
)
2492 set
= PATTERN (insn
);
2493 else if (GET_CODE (PATTERN (insn
)) == PARALLEL
)
2495 for (i
= 0; i
< XVECLEN (PATTERN (insn
), 0); i
++)
2496 if (GET_CODE (XVECEXP (PATTERN (insn
), 0, i
)) == SET
)
2498 set
= XVECEXP (PATTERN (insn
), 0, i
);
2506 if (! reg_overlap_mentioned_p (target
, SET_DEST (set
)))
2508 if (PREV_INSN (insn
))
2509 NEXT_INSN (PREV_INSN (insn
)) = next
;
2514 PREV_INSN (next
) = PREV_INSN (insn
);
2520 prev
= get_last_insn ();
2522 /* Now write the CLOBBER of the output, followed by the setting of each
2523 of the words, followed by the final copy. */
2524 if (target
!= op0
&& target
!= op1
)
2525 emit_insn (gen_rtx_CLOBBER (VOIDmode
, target
));
2527 for (insn
= insns
; insn
; insn
= next
)
2529 next
= NEXT_INSN (insn
);
2532 if (op1
&& GET_CODE (op1
) == REG
)
2533 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_NO_CONFLICT
, op1
,
2536 if (op0
&& GET_CODE (op0
) == REG
)
2537 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_NO_CONFLICT
, op0
,
2541 if (mov_optab
->handlers
[(int) GET_MODE (target
)].insn_code
2542 != CODE_FOR_nothing
)
2544 last
= emit_move_insn (target
, target
);
2547 = gen_rtx_EXPR_LIST (REG_EQUAL
, equiv
, REG_NOTES (last
));
2550 last
= get_last_insn ();
2553 first
= get_insns ();
2555 first
= NEXT_INSN (prev
);
2557 /* Encapsulate the block so it gets manipulated as a unit. */
2558 REG_NOTES (first
) = gen_rtx_INSN_LIST (REG_LIBCALL
, last
,
2560 REG_NOTES (last
) = gen_rtx_INSN_LIST (REG_RETVAL
, first
, REG_NOTES (last
));
2565 /* Emit code to make a call to a constant function or a library call.
2567 INSNS is a list containing all insns emitted in the call.
2568 These insns leave the result in RESULT. Our block is to copy RESULT
2569 to TARGET, which is logically equivalent to EQUIV.
2571 We first emit any insns that set a pseudo on the assumption that these are
2572 loading constants into registers; doing so allows them to be safely cse'ed
2573 between blocks. Then we emit all the other insns in the block, followed by
2574 an insn to move RESULT to TARGET. This last insn will have a REQ_EQUAL
2575 note with an operand of EQUIV.
2577 Moving assignments to pseudos outside of the block is done to improve
2578 the generated code, but is not required to generate correct code,
2579 hence being unable to move an assignment is not grounds for not making
2580 a libcall block. There are two reasons why it is safe to leave these
2581 insns inside the block: First, we know that these pseudos cannot be
2582 used in generated RTL outside the block since they are created for
2583 temporary purposes within the block. Second, CSE will not record the
2584 values of anything set inside a libcall block, so we know they must
2585 be dead at the end of the block.
2587 Except for the first group of insns (the ones setting pseudos), the
2588 block is delimited by REG_RETVAL and REG_LIBCALL notes. */
2591 emit_libcall_block (insns
, target
, result
, equiv
)
2597 rtx prev
, next
, first
, last
, insn
;
2599 /* First emit all insns that set pseudos. Remove them from the list as
2600 we go. Avoid insns that set pseudos which were referenced in previous
2601 insns. These can be generated by move_by_pieces, for example,
2602 to update an address. Similarly, avoid insns that reference things
2603 set in previous insns. */
2605 for (insn
= insns
; insn
; insn
= next
)
2607 rtx set
= single_set (insn
);
2609 next
= NEXT_INSN (insn
);
2611 if (set
!= 0 && GET_CODE (SET_DEST (set
)) == REG
2612 && REGNO (SET_DEST (set
)) >= FIRST_PSEUDO_REGISTER
2614 || (! reg_mentioned_p (SET_DEST (set
), PATTERN (insns
))
2615 && ! reg_used_between_p (SET_DEST (set
), insns
, insn
)
2616 && ! modified_in_p (SET_SRC (set
), insns
)
2617 && ! modified_between_p (SET_SRC (set
), insns
, insn
))))
2619 if (PREV_INSN (insn
))
2620 NEXT_INSN (PREV_INSN (insn
)) = next
;
2625 PREV_INSN (next
) = PREV_INSN (insn
);
2631 prev
= get_last_insn ();
2633 /* Write the remaining insns followed by the final copy. */
2635 for (insn
= insns
; insn
; insn
= next
)
2637 next
= NEXT_INSN (insn
);
2642 last
= emit_move_insn (target
, result
);
2643 if (mov_optab
->handlers
[(int) GET_MODE (target
)].insn_code
2644 != CODE_FOR_nothing
)
2645 REG_NOTES (last
) = gen_rtx_EXPR_LIST (REG_EQUAL
, copy_rtx (equiv
),
2649 first
= get_insns ();
2651 first
= NEXT_INSN (prev
);
2653 /* Encapsulate the block so it gets manipulated as a unit. */
2654 REG_NOTES (first
) = gen_rtx_INSN_LIST (REG_LIBCALL
, last
,
2656 REG_NOTES (last
) = gen_rtx_INSN_LIST (REG_RETVAL
, first
, REG_NOTES (last
));
2659 /* Generate code to store zero in X. */
2665 emit_move_insn (x
, const0_rtx
);
2668 /* Generate code to store 1 in X
2669 assuming it contains zero beforehand. */
2672 emit_0_to_1_insn (x
)
2675 emit_move_insn (x
, const1_rtx
);
2678 /* Generate code to compare X with Y
2679 so that the condition codes are set.
2681 MODE is the mode of the inputs (in case they are const_int).
2682 UNSIGNEDP nonzero says that X and Y are unsigned;
2683 this matters if they need to be widened.
2685 If they have mode BLKmode, then SIZE specifies the size of both X and Y,
2686 and ALIGN specifies the known shared alignment of X and Y.
2688 COMPARISON is the rtl operator to compare with (EQ, NE, GT, etc.).
2689 It is ignored for fixed-point and block comparisons;
2690 it is used only for floating-point comparisons. */
2693 emit_cmp_insn (x
, y
, comparison
, size
, mode
, unsignedp
, align
)
2695 enum rtx_code comparison
;
2697 enum machine_mode mode
;
2701 enum mode_class
class;
2702 enum machine_mode wider_mode
;
2704 class = GET_MODE_CLASS (mode
);
2706 /* They could both be VOIDmode if both args are immediate constants,
2707 but we should fold that at an earlier stage.
2708 With no special code here, this will call abort,
2709 reminding the programmer to implement such folding. */
2711 if (mode
!= BLKmode
&& flag_force_mem
)
2713 x
= force_not_mem (x
);
2714 y
= force_not_mem (y
);
2717 /* If we are inside an appropriately-short loop and one operand is an
2718 expensive constant, force it into a register. */
2719 if (CONSTANT_P (x
) && preserve_subexpressions_p () && rtx_cost (x
, COMPARE
) > 2)
2720 x
= force_reg (mode
, x
);
2722 if (CONSTANT_P (y
) && preserve_subexpressions_p () && rtx_cost (y
, COMPARE
) > 2)
2723 y
= force_reg (mode
, y
);
2726 /* Abort if we have a non-canonical comparison. The RTL documentation
2727 states that canonical comparisons are required only for targets which
2729 if (CONSTANT_P (x
) && ! CONSTANT_P (y
))
2733 /* Don't let both operands fail to indicate the mode. */
2734 if (GET_MODE (x
) == VOIDmode
&& GET_MODE (y
) == VOIDmode
)
2735 x
= force_reg (mode
, x
);
2737 /* Handle all BLKmode compares. */
2739 if (mode
== BLKmode
)
2742 x
= protect_from_queue (x
, 0);
2743 y
= protect_from_queue (y
, 0);
2747 #ifdef HAVE_cmpstrqi
2749 && GET_CODE (size
) == CONST_INT
2750 && INTVAL (size
) < (1 << GET_MODE_BITSIZE (QImode
)))
2752 enum machine_mode result_mode
2753 = insn_operand_mode
[(int) CODE_FOR_cmpstrqi
][0];
2754 rtx result
= gen_reg_rtx (result_mode
);
2755 emit_insn (gen_cmpstrqi (result
, x
, y
, size
, GEN_INT (align
)));
2756 emit_cmp_insn (result
, const0_rtx
, comparison
, NULL_RTX
,
2761 #ifdef HAVE_cmpstrhi
2763 && GET_CODE (size
) == CONST_INT
2764 && INTVAL (size
) < (1 << GET_MODE_BITSIZE (HImode
)))
2766 enum machine_mode result_mode
2767 = insn_operand_mode
[(int) CODE_FOR_cmpstrhi
][0];
2768 rtx result
= gen_reg_rtx (result_mode
);
2769 emit_insn (gen_cmpstrhi (result
, x
, y
, size
, GEN_INT (align
)));
2770 emit_cmp_insn (result
, const0_rtx
, comparison
, NULL_RTX
,
2775 #ifdef HAVE_cmpstrsi
2778 enum machine_mode result_mode
2779 = insn_operand_mode
[(int) CODE_FOR_cmpstrsi
][0];
2780 rtx result
= gen_reg_rtx (result_mode
);
2781 size
= protect_from_queue (size
, 0);
2782 emit_insn (gen_cmpstrsi (result
, x
, y
,
2783 convert_to_mode (SImode
, size
, 1),
2785 emit_cmp_insn (result
, const0_rtx
, comparison
, NULL_RTX
,
2793 #ifdef TARGET_MEM_FUNCTIONS
2794 emit_library_call (memcmp_libfunc
, 0,
2795 TYPE_MODE (integer_type_node
), 3,
2796 XEXP (x
, 0), Pmode
, XEXP (y
, 0), Pmode
,
2797 convert_to_mode (TYPE_MODE (sizetype
), size
,
2798 TREE_UNSIGNED (sizetype
)),
2799 TYPE_MODE (sizetype
));
2801 emit_library_call (bcmp_libfunc
, 0,
2802 TYPE_MODE (integer_type_node
), 3,
2803 XEXP (x
, 0), Pmode
, XEXP (y
, 0), Pmode
,
2804 convert_to_mode (TYPE_MODE (integer_type_node
),
2806 TREE_UNSIGNED (integer_type_node
)),
2807 TYPE_MODE (integer_type_node
));
2810 /* Immediately move the result of the libcall into a pseudo
2811 register so reload doesn't clobber the value if it needs
2812 the return register for a spill reg. */
2813 result
= gen_reg_rtx (TYPE_MODE (integer_type_node
));
2814 emit_move_insn (result
,
2815 hard_libcall_value (TYPE_MODE (integer_type_node
)));
2816 emit_cmp_insn (result
,
2817 const0_rtx
, comparison
, NULL_RTX
,
2818 TYPE_MODE (integer_type_node
), 0, 0);
2823 /* Handle some compares against zero. */
2825 if (y
== CONST0_RTX (mode
)
2826 && tst_optab
->handlers
[(int) mode
].insn_code
!= CODE_FOR_nothing
)
2828 int icode
= (int) tst_optab
->handlers
[(int) mode
].insn_code
;
2831 x
= protect_from_queue (x
, 0);
2832 y
= protect_from_queue (y
, 0);
2834 /* Now, if insn does accept these operands, put them into pseudos. */
2835 if (! (*insn_operand_predicate
[icode
][0])
2836 (x
, insn_operand_mode
[icode
][0]))
2837 x
= copy_to_mode_reg (insn_operand_mode
[icode
][0], x
);
2839 emit_insn (GEN_FCN (icode
) (x
));
2843 /* Handle compares for which there is a directly suitable insn. */
2845 if (cmp_optab
->handlers
[(int) mode
].insn_code
!= CODE_FOR_nothing
)
2847 int icode
= (int) cmp_optab
->handlers
[(int) mode
].insn_code
;
2850 x
= protect_from_queue (x
, 0);
2851 y
= protect_from_queue (y
, 0);
2853 /* Now, if insn doesn't accept these operands, put them into pseudos. */
2854 if (! (*insn_operand_predicate
[icode
][0])
2855 (x
, insn_operand_mode
[icode
][0]))
2856 x
= copy_to_mode_reg (insn_operand_mode
[icode
][0], x
);
2858 if (! (*insn_operand_predicate
[icode
][1])
2859 (y
, insn_operand_mode
[icode
][1]))
2860 y
= copy_to_mode_reg (insn_operand_mode
[icode
][1], y
);
2862 emit_insn (GEN_FCN (icode
) (x
, y
));
2866 /* Try widening if we can find a direct insn that way. */
2868 if (class == MODE_INT
|| class == MODE_FLOAT
|| class == MODE_COMPLEX_FLOAT
)
2870 for (wider_mode
= GET_MODE_WIDER_MODE (mode
); wider_mode
!= VOIDmode
;
2871 wider_mode
= GET_MODE_WIDER_MODE (wider_mode
))
2873 if (cmp_optab
->handlers
[(int) wider_mode
].insn_code
2874 != CODE_FOR_nothing
)
2876 x
= protect_from_queue (x
, 0);
2877 y
= protect_from_queue (y
, 0);
2878 x
= convert_modes (wider_mode
, mode
, x
, unsignedp
);
2879 y
= convert_modes (wider_mode
, mode
, y
, unsignedp
);
2880 emit_cmp_insn (x
, y
, comparison
, NULL_RTX
,
2881 wider_mode
, unsignedp
, align
);
2887 /* Handle a lib call just for the mode we are using. */
2889 if (cmp_optab
->handlers
[(int) mode
].libfunc
2890 && class != MODE_FLOAT
)
2892 rtx libfunc
= cmp_optab
->handlers
[(int) mode
].libfunc
;
2895 /* If we want unsigned, and this mode has a distinct unsigned
2896 comparison routine, use that. */
2897 if (unsignedp
&& ucmp_optab
->handlers
[(int) mode
].libfunc
)
2898 libfunc
= ucmp_optab
->handlers
[(int) mode
].libfunc
;
2900 emit_library_call (libfunc
, 1,
2901 word_mode
, 2, x
, mode
, y
, mode
);
2903 /* Immediately move the result of the libcall into a pseudo
2904 register so reload doesn't clobber the value if it needs
2905 the return register for a spill reg. */
2906 result
= gen_reg_rtx (word_mode
);
2907 emit_move_insn (result
, hard_libcall_value (word_mode
));
2909 /* Integer comparison returns a result that must be compared against 1,
2910 so that even if we do an unsigned compare afterward,
2911 there is still a value that can represent the result "less than". */
2912 emit_cmp_insn (result
, const1_rtx
,
2913 comparison
, NULL_RTX
, word_mode
, unsignedp
, 0);
2917 if (class == MODE_FLOAT
)
2918 emit_float_lib_cmp (x
, y
, comparison
);
2924 /* Generate code to compare X with Y so that the condition codes are
2925 set and to jump to LABEL if the condition is true. If X is a
2926 constant and Y is not a constant, then the comparison is swapped to
2927 ensure that the comparison RTL has the canonical form.
2929 MODE is the mode of the inputs (in case they are const_int).
2930 UNSIGNEDP nonzero says that X and Y are unsigned;
2931 this matters if they need to be widened.
2933 If they have mode BLKmode, then SIZE specifies the size of both X and Y,
2934 and ALIGN specifies the known shared alignment of X and Y.
2936 COMPARISON is the rtl operator to compare with (EQ, NE, GT, etc.).
2937 It is ignored for fixed-point and block comparisons;
2938 it is used only for floating-point comparisons. */
2941 emit_cmp_and_jump_insns (x
, y
, comparison
, size
, mode
, unsignedp
, align
, label
)
2943 enum rtx_code comparison
;
2945 enum machine_mode mode
;
2955 /* Swap operands and condition to ensure canonical RTL. */
2958 comparison
= swap_condition (comparison
);
2965 emit_cmp_insn (op0
, op1
, comparison
, size
, mode
, unsignedp
, align
);
2966 emit_jump_insn ((*bcc_gen_fctn
[(int) comparison
]) (label
));
2970 /* Nonzero if a compare of mode MODE can be done straightforwardly
2971 (without splitting it into pieces). */
2974 can_compare_p (mode
)
2975 enum machine_mode mode
;
2979 if (cmp_optab
->handlers
[(int)mode
].insn_code
!= CODE_FOR_nothing
)
2981 mode
= GET_MODE_WIDER_MODE (mode
);
2982 } while (mode
!= VOIDmode
);
2987 /* Emit a library call comparison between floating point X and Y.
2988 COMPARISON is the rtl operator to compare with (EQ, NE, GT, etc.). */
2991 emit_float_lib_cmp (x
, y
, comparison
)
2993 enum rtx_code comparison
;
2995 enum machine_mode mode
= GET_MODE (x
);
3003 libfunc
= eqhf2_libfunc
;
3007 libfunc
= nehf2_libfunc
;
3011 libfunc
= gthf2_libfunc
;
3015 libfunc
= gehf2_libfunc
;
3019 libfunc
= lthf2_libfunc
;
3023 libfunc
= lehf2_libfunc
;
3029 else if (mode
== SFmode
)
3033 libfunc
= eqsf2_libfunc
;
3037 libfunc
= nesf2_libfunc
;
3041 libfunc
= gtsf2_libfunc
;
3045 libfunc
= gesf2_libfunc
;
3049 libfunc
= ltsf2_libfunc
;
3053 libfunc
= lesf2_libfunc
;
3059 else if (mode
== DFmode
)
3063 libfunc
= eqdf2_libfunc
;
3067 libfunc
= nedf2_libfunc
;
3071 libfunc
= gtdf2_libfunc
;
3075 libfunc
= gedf2_libfunc
;
3079 libfunc
= ltdf2_libfunc
;
3083 libfunc
= ledf2_libfunc
;
3089 else if (mode
== XFmode
)
3093 libfunc
= eqxf2_libfunc
;
3097 libfunc
= nexf2_libfunc
;
3101 libfunc
= gtxf2_libfunc
;
3105 libfunc
= gexf2_libfunc
;
3109 libfunc
= ltxf2_libfunc
;
3113 libfunc
= lexf2_libfunc
;
3119 else if (mode
== TFmode
)
3123 libfunc
= eqtf2_libfunc
;
3127 libfunc
= netf2_libfunc
;
3131 libfunc
= gttf2_libfunc
;
3135 libfunc
= getf2_libfunc
;
3139 libfunc
= lttf2_libfunc
;
3143 libfunc
= letf2_libfunc
;
3151 enum machine_mode wider_mode
;
3153 for (wider_mode
= GET_MODE_WIDER_MODE (mode
); wider_mode
!= VOIDmode
;
3154 wider_mode
= GET_MODE_WIDER_MODE (wider_mode
))
3156 if ((cmp_optab
->handlers
[(int) wider_mode
].insn_code
3157 != CODE_FOR_nothing
)
3158 || (cmp_optab
->handlers
[(int) wider_mode
].libfunc
!= 0))
3160 x
= protect_from_queue (x
, 0);
3161 y
= protect_from_queue (y
, 0);
3162 x
= convert_to_mode (wider_mode
, x
, 0);
3163 y
= convert_to_mode (wider_mode
, y
, 0);
3164 emit_float_lib_cmp (x
, y
, comparison
);
3174 emit_library_call (libfunc
, 1,
3175 word_mode
, 2, x
, mode
, y
, mode
);
3177 /* Immediately move the result of the libcall into a pseudo
3178 register so reload doesn't clobber the value if it needs
3179 the return register for a spill reg. */
3180 result
= gen_reg_rtx (word_mode
);
3181 emit_move_insn (result
, hard_libcall_value (word_mode
));
3183 emit_cmp_insn (result
, const0_rtx
, comparison
,
3184 NULL_RTX
, word_mode
, 0, 0);
3187 /* Generate code to indirectly jump to a location given in the rtx LOC. */
3190 emit_indirect_jump (loc
)
3193 if (! ((*insn_operand_predicate
[(int)CODE_FOR_indirect_jump
][0])
3195 loc
= copy_to_mode_reg (Pmode
, loc
);
3197 emit_jump_insn (gen_indirect_jump (loc
));
3201 #ifdef HAVE_conditional_move
3203 /* Emit a conditional move instruction if the machine supports one for that
3204 condition and machine mode.
3206 OP0 and OP1 are the operands that should be compared using CODE. CMODE is
3207 the mode to use should they be constants. If it is VOIDmode, they cannot
3210 OP2 should be stored in TARGET if the comparison is true, otherwise OP3
3211 should be stored there. MODE is the mode to use should they be constants.
3212 If it is VOIDmode, they cannot both be constants.
3214 The result is either TARGET (perhaps modified) or NULL_RTX if the operation
3215 is not supported. */
3218 emit_conditional_move (target
, code
, op0
, op1
, cmode
, op2
, op3
, mode
,
3223 enum machine_mode cmode
;
3225 enum machine_mode mode
;
3228 rtx tem
, subtarget
, comparison
, insn
;
3229 enum insn_code icode
;
3231 /* If one operand is constant, make it the second one. Only do this
3232 if the other operand is not constant as well. */
3234 if ((CONSTANT_P (op0
) && ! CONSTANT_P (op1
))
3235 || (GET_CODE (op0
) == CONST_INT
&& GET_CODE (op1
) != CONST_INT
))
3240 code
= swap_condition (code
);
3243 if (cmode
== VOIDmode
)
3244 cmode
= GET_MODE (op0
);
3246 if (((CONSTANT_P (op2
) && ! CONSTANT_P (op3
))
3247 || (GET_CODE (op2
) == CONST_INT
&& GET_CODE (op3
) != CONST_INT
))
3248 && (GET_MODE_CLASS (GET_MODE (op1
)) != MODE_FLOAT
3249 || TARGET_FLOAT_FORMAT
!= IEEE_FLOAT_FORMAT
|| flag_fast_math
))
3254 code
= reverse_condition (code
);
3257 if (mode
== VOIDmode
)
3258 mode
= GET_MODE (op2
);
3260 icode
= movcc_gen_code
[mode
];
3262 if (icode
== CODE_FOR_nothing
)
3267 op2
= force_not_mem (op2
);
3268 op3
= force_not_mem (op3
);
3272 target
= protect_from_queue (target
, 1);
3274 target
= gen_reg_rtx (mode
);
3280 op2
= protect_from_queue (op2
, 0);
3281 op3
= protect_from_queue (op3
, 0);
3283 /* If the insn doesn't accept these operands, put them in pseudos. */
3285 if (! (*insn_operand_predicate
[icode
][0])
3286 (subtarget
, insn_operand_mode
[icode
][0]))
3287 subtarget
= gen_reg_rtx (insn_operand_mode
[icode
][0]);
3289 if (! (*insn_operand_predicate
[icode
][2])
3290 (op2
, insn_operand_mode
[icode
][2]))
3291 op2
= copy_to_mode_reg (insn_operand_mode
[icode
][2], op2
);
3293 if (! (*insn_operand_predicate
[icode
][3])
3294 (op3
, insn_operand_mode
[icode
][3]))
3295 op3
= copy_to_mode_reg (insn_operand_mode
[icode
][3], op3
);
3297 /* Everything should now be in the suitable form, so emit the compare insn
3298 and then the conditional move. */
3301 = compare_from_rtx (op0
, op1
, code
, unsignedp
, cmode
, NULL_RTX
, 0);
3303 /* ??? Watch for const0_rtx (nop) and const_true_rtx (unconditional)? */
3304 if (GET_CODE (comparison
) != code
)
3305 /* This shouldn't happen. */
3308 insn
= GEN_FCN (icode
) (subtarget
, comparison
, op2
, op3
);
3310 /* If that failed, then give up. */
3316 if (subtarget
!= target
)
3317 convert_move (target
, subtarget
, 0);
3322 /* Return non-zero if a conditional move of mode MODE is supported.
3324 This function is for combine so it can tell whether an insn that looks
3325 like a conditional move is actually supported by the hardware. If we
3326 guess wrong we lose a bit on optimization, but that's it. */
3327 /* ??? sparc64 supports conditionally moving integers values based on fp
3328 comparisons, and vice versa. How do we handle them? */
3331 can_conditionally_move_p (mode
)
3332 enum machine_mode mode
;
3334 if (movcc_gen_code
[mode
] != CODE_FOR_nothing
)
3340 #endif /* HAVE_conditional_move */
3342 /* These three functions generate an insn body and return it
3343 rather than emitting the insn.
3345 They do not protect from queued increments,
3346 because they may be used 1) in protect_from_queue itself
3347 and 2) in other passes where there is no queue. */
3349 /* Generate and return an insn body to add Y to X. */
3352 gen_add2_insn (x
, y
)
3355 int icode
= (int) add_optab
->handlers
[(int) GET_MODE (x
)].insn_code
;
3357 if (! (*insn_operand_predicate
[icode
][0]) (x
, insn_operand_mode
[icode
][0])
3358 || ! (*insn_operand_predicate
[icode
][1]) (x
, insn_operand_mode
[icode
][1])
3359 || ! (*insn_operand_predicate
[icode
][2]) (y
, insn_operand_mode
[icode
][2]))
3362 return (GEN_FCN (icode
) (x
, x
, y
));
3366 have_add2_insn (mode
)
3367 enum machine_mode mode
;
3369 return add_optab
->handlers
[(int) mode
].insn_code
!= CODE_FOR_nothing
;
3372 /* Generate and return an insn body to subtract Y from X. */
3375 gen_sub2_insn (x
, y
)
3378 int icode
= (int) sub_optab
->handlers
[(int) GET_MODE (x
)].insn_code
;
3380 if (! (*insn_operand_predicate
[icode
][0]) (x
, insn_operand_mode
[icode
][0])
3381 || ! (*insn_operand_predicate
[icode
][1]) (x
, insn_operand_mode
[icode
][1])
3382 || ! (*insn_operand_predicate
[icode
][2]) (y
, insn_operand_mode
[icode
][2]))
3385 return (GEN_FCN (icode
) (x
, x
, y
));
3389 have_sub2_insn (mode
)
3390 enum machine_mode mode
;
3392 return sub_optab
->handlers
[(int) mode
].insn_code
!= CODE_FOR_nothing
;
3395 /* Generate the body of an instruction to copy Y into X.
3396 It may be a SEQUENCE, if one insn isn't enough. */
3399 gen_move_insn (x
, y
)
3402 register enum machine_mode mode
= GET_MODE (x
);
3403 enum insn_code insn_code
;
3406 if (mode
== VOIDmode
)
3407 mode
= GET_MODE (y
);
3409 insn_code
= mov_optab
->handlers
[(int) mode
].insn_code
;
3411 /* Handle MODE_CC modes: If we don't have a special move insn for this mode,
3412 find a mode to do it in. If we have a movcc, use it. Otherwise,
3413 find the MODE_INT mode of the same width. */
3415 if (GET_MODE_CLASS (mode
) == MODE_CC
&& insn_code
== CODE_FOR_nothing
)
3417 enum machine_mode tmode
= VOIDmode
;
3421 && mov_optab
->handlers
[(int) CCmode
].insn_code
!= CODE_FOR_nothing
)
3424 for (tmode
= QImode
; tmode
!= VOIDmode
;
3425 tmode
= GET_MODE_WIDER_MODE (tmode
))
3426 if (GET_MODE_SIZE (tmode
) == GET_MODE_SIZE (mode
))
3429 if (tmode
== VOIDmode
)
3432 /* Get X and Y in TMODE. We can't use gen_lowpart here because it
3433 may call change_address which is not appropriate if we were
3434 called when a reload was in progress. We don't have to worry
3435 about changing the address since the size in bytes is supposed to
3436 be the same. Copy the MEM to change the mode and move any
3437 substitutions from the old MEM to the new one. */
3439 if (reload_in_progress
)
3441 x
= gen_lowpart_common (tmode
, x1
);
3442 if (x
== 0 && GET_CODE (x1
) == MEM
)
3444 x
= gen_rtx_MEM (tmode
, XEXP (x1
, 0));
3445 RTX_UNCHANGING_P (x
) = RTX_UNCHANGING_P (x1
);
3446 MEM_IN_STRUCT_P (x
) = MEM_IN_STRUCT_P (x1
);
3447 MEM_VOLATILE_P (x
) = MEM_VOLATILE_P (x1
);
3448 copy_replacements (x1
, x
);
3451 y
= gen_lowpart_common (tmode
, y1
);
3452 if (y
== 0 && GET_CODE (y1
) == MEM
)
3454 y
= gen_rtx_MEM (tmode
, XEXP (y1
, 0));
3455 RTX_UNCHANGING_P (y
) = RTX_UNCHANGING_P (y1
);
3456 MEM_IN_STRUCT_P (y
) = MEM_IN_STRUCT_P (y1
);
3457 MEM_VOLATILE_P (y
) = MEM_VOLATILE_P (y1
);
3458 copy_replacements (y1
, y
);
3463 x
= gen_lowpart (tmode
, x
);
3464 y
= gen_lowpart (tmode
, y
);
3467 insn_code
= mov_optab
->handlers
[(int) tmode
].insn_code
;
3468 return (GEN_FCN (insn_code
) (x
, y
));
3472 emit_move_insn_1 (x
, y
);
3473 seq
= gen_sequence ();
3478 /* Return the insn code used to extend FROM_MODE to TO_MODE.
3479 UNSIGNEDP specifies zero-extension instead of sign-extension. If
3480 no such operation exists, CODE_FOR_nothing will be returned. */
3483 can_extend_p (to_mode
, from_mode
, unsignedp
)
3484 enum machine_mode to_mode
, from_mode
;
3487 return extendtab
[(int) to_mode
][(int) from_mode
][unsignedp
];
3490 /* Generate the body of an insn to extend Y (with mode MFROM)
3491 into X (with mode MTO). Do zero-extension if UNSIGNEDP is nonzero. */
3494 gen_extend_insn (x
, y
, mto
, mfrom
, unsignedp
)
3496 enum machine_mode mto
, mfrom
;
3499 return (GEN_FCN (extendtab
[(int) mto
][(int) mfrom
][unsignedp
]) (x
, y
));
3502 /* can_fix_p and can_float_p say whether the target machine
3503 can directly convert a given fixed point type to
3504 a given floating point type, or vice versa.
3505 The returned value is the CODE_FOR_... value to use,
3506 or CODE_FOR_nothing if these modes cannot be directly converted.
3508 *TRUNCP_PTR is set to 1 if it is necessary to output
3509 an explicit FTRUNC insn before the fix insn; otherwise 0. */
3511 static enum insn_code
3512 can_fix_p (fixmode
, fltmode
, unsignedp
, truncp_ptr
)
3513 enum machine_mode fltmode
, fixmode
;
3518 if (fixtrunctab
[(int) fltmode
][(int) fixmode
][unsignedp
] != CODE_FOR_nothing
)
3519 return fixtrunctab
[(int) fltmode
][(int) fixmode
][unsignedp
];
3521 if (ftrunc_optab
->handlers
[(int) fltmode
].insn_code
!= CODE_FOR_nothing
)
3524 return fixtab
[(int) fltmode
][(int) fixmode
][unsignedp
];
3526 return CODE_FOR_nothing
;
3529 static enum insn_code
3530 can_float_p (fltmode
, fixmode
, unsignedp
)
3531 enum machine_mode fixmode
, fltmode
;
3534 return floattab
[(int) fltmode
][(int) fixmode
][unsignedp
];
3537 /* Generate code to convert FROM to floating point
3538 and store in TO. FROM must be fixed point and not VOIDmode.
3539 UNSIGNEDP nonzero means regard FROM as unsigned.
3540 Normally this is done by correcting the final value
3541 if it is negative. */
3544 expand_float (to
, from
, unsignedp
)
3548 enum insn_code icode
;
3549 register rtx target
= to
;
3550 enum machine_mode fmode
, imode
;
3552 /* Crash now, because we won't be able to decide which mode to use. */
3553 if (GET_MODE (from
) == VOIDmode
)
3556 /* Look for an insn to do the conversion. Do it in the specified
3557 modes if possible; otherwise convert either input, output or both to
3558 wider mode. If the integer mode is wider than the mode of FROM,
3559 we can do the conversion signed even if the input is unsigned. */
3561 for (imode
= GET_MODE (from
); imode
!= VOIDmode
;
3562 imode
= GET_MODE_WIDER_MODE (imode
))
3563 for (fmode
= GET_MODE (to
); fmode
!= VOIDmode
;
3564 fmode
= GET_MODE_WIDER_MODE (fmode
))
3566 int doing_unsigned
= unsignedp
;
3568 icode
= can_float_p (fmode
, imode
, unsignedp
);
3569 if (icode
== CODE_FOR_nothing
&& imode
!= GET_MODE (from
) && unsignedp
)
3570 icode
= can_float_p (fmode
, imode
, 0), doing_unsigned
= 0;
3572 if (icode
!= CODE_FOR_nothing
)
3574 to
= protect_from_queue (to
, 1);
3575 from
= protect_from_queue (from
, 0);
3577 if (imode
!= GET_MODE (from
))
3578 from
= convert_to_mode (imode
, from
, unsignedp
);
3580 if (fmode
!= GET_MODE (to
))
3581 target
= gen_reg_rtx (fmode
);
3583 emit_unop_insn (icode
, target
, from
,
3584 doing_unsigned
? UNSIGNED_FLOAT
: FLOAT
);
3587 convert_move (to
, target
, 0);
3592 #if !defined (REAL_IS_NOT_DOUBLE) || defined (REAL_ARITHMETIC)
3594 /* Unsigned integer, and no way to convert directly.
3595 Convert as signed, then conditionally adjust the result. */
3598 rtx label
= gen_label_rtx ();
3600 REAL_VALUE_TYPE offset
;
3604 to
= protect_from_queue (to
, 1);
3605 from
= protect_from_queue (from
, 0);
3608 from
= force_not_mem (from
);
3610 /* Look for a usable floating mode FMODE wider than the source and at
3611 least as wide as the target. Using FMODE will avoid rounding woes
3612 with unsigned values greater than the signed maximum value. */
3614 for (fmode
= GET_MODE (to
); fmode
!= VOIDmode
;
3615 fmode
= GET_MODE_WIDER_MODE (fmode
))
3616 if (GET_MODE_BITSIZE (GET_MODE (from
)) < GET_MODE_BITSIZE (fmode
)
3617 && can_float_p (fmode
, GET_MODE (from
), 0) != CODE_FOR_nothing
)
3620 if (fmode
== VOIDmode
)
3622 /* There is no such mode. Pretend the target is wide enough. */
3623 fmode
= GET_MODE (to
);
3625 /* Avoid double-rounding when TO is narrower than FROM. */
3626 if ((significand_size (fmode
) + 1)
3627 < GET_MODE_BITSIZE (GET_MODE (from
)))
3630 rtx neglabel
= gen_label_rtx ();
3632 /* Don't use TARGET if it isn't a register, is a hard register,
3633 or is the wrong mode. */
3634 if (GET_CODE (target
) != REG
3635 || REGNO (target
) < FIRST_PSEUDO_REGISTER
3636 || GET_MODE (target
) != fmode
)
3637 target
= gen_reg_rtx (fmode
);
3639 imode
= GET_MODE (from
);
3640 do_pending_stack_adjust ();
3642 /* Test whether the sign bit is set. */
3643 emit_cmp_insn (from
, const0_rtx
, GE
, NULL_RTX
, imode
, 0, 0);
3644 emit_jump_insn (gen_blt (neglabel
));
3646 /* The sign bit is not set. Convert as signed. */
3647 expand_float (target
, from
, 0);
3648 emit_jump_insn (gen_jump (label
));
3651 /* The sign bit is set.
3652 Convert to a usable (positive signed) value by shifting right
3653 one bit, while remembering if a nonzero bit was shifted
3654 out; i.e., compute (from & 1) | (from >> 1). */
3656 emit_label (neglabel
);
3657 temp
= expand_binop (imode
, and_optab
, from
, const1_rtx
,
3658 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
3659 temp1
= expand_shift (RSHIFT_EXPR
, imode
, from
, integer_one_node
,
3661 temp
= expand_binop (imode
, ior_optab
, temp
, temp1
, temp
, 1,
3663 expand_float (target
, temp
, 0);
3665 /* Multiply by 2 to undo the shift above. */
3666 temp
= expand_binop (fmode
, add_optab
, target
, target
,
3667 target
, 0, OPTAB_LIB_WIDEN
);
3669 emit_move_insn (target
, temp
);
3671 do_pending_stack_adjust ();
3677 /* If we are about to do some arithmetic to correct for an
3678 unsigned operand, do it in a pseudo-register. */
3680 if (GET_MODE (to
) != fmode
3681 || GET_CODE (to
) != REG
|| REGNO (to
) < FIRST_PSEUDO_REGISTER
)
3682 target
= gen_reg_rtx (fmode
);
3684 /* Convert as signed integer to floating. */
3685 expand_float (target
, from
, 0);
3687 /* If FROM is negative (and therefore TO is negative),
3688 correct its value by 2**bitwidth. */
3690 do_pending_stack_adjust ();
3691 emit_cmp_insn (from
, const0_rtx
, GE
, NULL_RTX
, GET_MODE (from
), 0, 0);
3692 emit_jump_insn (gen_bge (label
));
3694 /* On SCO 3.2.1, ldexp rejects values outside [0.5, 1).
3695 Rather than setting up a dconst_dot_5, let's hope SCO
3697 offset
= REAL_VALUE_LDEXP (dconst1
, GET_MODE_BITSIZE (GET_MODE (from
)));
3698 temp
= expand_binop (fmode
, add_optab
, target
,
3699 CONST_DOUBLE_FROM_REAL_VALUE (offset
, fmode
),
3700 target
, 0, OPTAB_LIB_WIDEN
);
3702 emit_move_insn (target
, temp
);
3704 do_pending_stack_adjust ();
3710 /* No hardware instruction available; call a library routine to convert from
3711 SImode, DImode, or TImode into SFmode, DFmode, XFmode, or TFmode. */
3717 to
= protect_from_queue (to
, 1);
3718 from
= protect_from_queue (from
, 0);
3720 if (GET_MODE_SIZE (GET_MODE (from
)) < GET_MODE_SIZE (SImode
))
3721 from
= convert_to_mode (SImode
, from
, unsignedp
);
3724 from
= force_not_mem (from
);
3726 if (GET_MODE (to
) == SFmode
)
3728 if (GET_MODE (from
) == SImode
)
3729 libfcn
= floatsisf_libfunc
;
3730 else if (GET_MODE (from
) == DImode
)
3731 libfcn
= floatdisf_libfunc
;
3732 else if (GET_MODE (from
) == TImode
)
3733 libfcn
= floattisf_libfunc
;
3737 else if (GET_MODE (to
) == DFmode
)
3739 if (GET_MODE (from
) == SImode
)
3740 libfcn
= floatsidf_libfunc
;
3741 else if (GET_MODE (from
) == DImode
)
3742 libfcn
= floatdidf_libfunc
;
3743 else if (GET_MODE (from
) == TImode
)
3744 libfcn
= floattidf_libfunc
;
3748 else if (GET_MODE (to
) == XFmode
)
3750 if (GET_MODE (from
) == SImode
)
3751 libfcn
= floatsixf_libfunc
;
3752 else if (GET_MODE (from
) == DImode
)
3753 libfcn
= floatdixf_libfunc
;
3754 else if (GET_MODE (from
) == TImode
)
3755 libfcn
= floattixf_libfunc
;
3759 else if (GET_MODE (to
) == TFmode
)
3761 if (GET_MODE (from
) == SImode
)
3762 libfcn
= floatsitf_libfunc
;
3763 else if (GET_MODE (from
) == DImode
)
3764 libfcn
= floatditf_libfunc
;
3765 else if (GET_MODE (from
) == TImode
)
3766 libfcn
= floattitf_libfunc
;
3775 value
= emit_library_call_value (libfcn
, NULL_RTX
, 1,
3777 1, from
, GET_MODE (from
));
3778 insns
= get_insns ();
3781 emit_libcall_block (insns
, target
, value
,
3782 gen_rtx_FLOAT (GET_MODE (to
), from
));
3787 /* Copy result to requested destination
3788 if we have been computing in a temp location. */
3792 if (GET_MODE (target
) == GET_MODE (to
))
3793 emit_move_insn (to
, target
);
3795 convert_move (to
, target
, 0);
3799 /* expand_fix: generate code to convert FROM to fixed point
3800 and store in TO. FROM must be floating point. */
3806 rtx temp
= gen_reg_rtx (GET_MODE (x
));
3807 return expand_unop (GET_MODE (x
), ftrunc_optab
, x
, temp
, 0);
3811 expand_fix (to
, from
, unsignedp
)
3812 register rtx to
, from
;
3815 enum insn_code icode
;
3816 register rtx target
= to
;
3817 enum machine_mode fmode
, imode
;
3821 /* We first try to find a pair of modes, one real and one integer, at
3822 least as wide as FROM and TO, respectively, in which we can open-code
3823 this conversion. If the integer mode is wider than the mode of TO,
3824 we can do the conversion either signed or unsigned. */
3826 for (imode
= GET_MODE (to
); imode
!= VOIDmode
;
3827 imode
= GET_MODE_WIDER_MODE (imode
))
3828 for (fmode
= GET_MODE (from
); fmode
!= VOIDmode
;
3829 fmode
= GET_MODE_WIDER_MODE (fmode
))
3831 int doing_unsigned
= unsignedp
;
3833 icode
= can_fix_p (imode
, fmode
, unsignedp
, &must_trunc
);
3834 if (icode
== CODE_FOR_nothing
&& imode
!= GET_MODE (to
) && unsignedp
)
3835 icode
= can_fix_p (imode
, fmode
, 0, &must_trunc
), doing_unsigned
= 0;
3837 if (icode
!= CODE_FOR_nothing
)
3839 to
= protect_from_queue (to
, 1);
3840 from
= protect_from_queue (from
, 0);
3842 if (fmode
!= GET_MODE (from
))
3843 from
= convert_to_mode (fmode
, from
, 0);
3846 from
= ftruncify (from
);
3848 if (imode
!= GET_MODE (to
))
3849 target
= gen_reg_rtx (imode
);
3851 emit_unop_insn (icode
, target
, from
,
3852 doing_unsigned
? UNSIGNED_FIX
: FIX
);
3854 convert_move (to
, target
, unsignedp
);
3859 #if !defined (REAL_IS_NOT_DOUBLE) || defined (REAL_ARITHMETIC)
3860 /* For an unsigned conversion, there is one more way to do it.
3861 If we have a signed conversion, we generate code that compares
3862 the real value to the largest representable positive number. If if
3863 is smaller, the conversion is done normally. Otherwise, subtract
3864 one plus the highest signed number, convert, and add it back.
3866 We only need to check all real modes, since we know we didn't find
3867 anything with a wider integer mode. */
3869 if (unsignedp
&& GET_MODE_BITSIZE (GET_MODE (to
)) <= HOST_BITS_PER_WIDE_INT
)
3870 for (fmode
= GET_MODE (from
); fmode
!= VOIDmode
;
3871 fmode
= GET_MODE_WIDER_MODE (fmode
))
3872 /* Make sure we won't lose significant bits doing this. */
3873 if (GET_MODE_BITSIZE (fmode
) > GET_MODE_BITSIZE (GET_MODE (to
))
3874 && CODE_FOR_nothing
!= can_fix_p (GET_MODE (to
), fmode
, 0,
3878 REAL_VALUE_TYPE offset
;
3879 rtx limit
, lab1
, lab2
, insn
;
3881 bitsize
= GET_MODE_BITSIZE (GET_MODE (to
));
3882 offset
= REAL_VALUE_LDEXP (dconst1
, bitsize
- 1);
3883 limit
= CONST_DOUBLE_FROM_REAL_VALUE (offset
, fmode
);
3884 lab1
= gen_label_rtx ();
3885 lab2
= gen_label_rtx ();
3888 to
= protect_from_queue (to
, 1);
3889 from
= protect_from_queue (from
, 0);
3892 from
= force_not_mem (from
);
3894 if (fmode
!= GET_MODE (from
))
3895 from
= convert_to_mode (fmode
, from
, 0);
3897 /* See if we need to do the subtraction. */
3898 do_pending_stack_adjust ();
3899 emit_cmp_insn (from
, limit
, GE
, NULL_RTX
, GET_MODE (from
), 0, 0);
3900 emit_jump_insn (gen_bge (lab1
));
3902 /* If not, do the signed "fix" and branch around fixup code. */
3903 expand_fix (to
, from
, 0);
3904 emit_jump_insn (gen_jump (lab2
));
3907 /* Otherwise, subtract 2**(N-1), convert to signed number,
3908 then add 2**(N-1). Do the addition using XOR since this
3909 will often generate better code. */
3911 target
= expand_binop (GET_MODE (from
), sub_optab
, from
, limit
,
3912 NULL_RTX
, 0, OPTAB_LIB_WIDEN
);
3913 expand_fix (to
, target
, 0);
3914 target
= expand_binop (GET_MODE (to
), xor_optab
, to
,
3915 GEN_INT ((HOST_WIDE_INT
) 1 << (bitsize
- 1)),
3916 to
, 1, OPTAB_LIB_WIDEN
);
3919 emit_move_insn (to
, target
);
3923 if (mov_optab
->handlers
[(int) GET_MODE (to
)].insn_code
3924 != CODE_FOR_nothing
)
3926 /* Make a place for a REG_NOTE and add it. */
3927 insn
= emit_move_insn (to
, to
);
3929 = gen_rtx_EXPR_LIST (REG_EQUAL
,
3930 gen_rtx_fmt_e (UNSIGNED_FIX
,
3939 /* We can't do it with an insn, so use a library call. But first ensure
3940 that the mode of TO is at least as wide as SImode, since those are the
3941 only library calls we know about. */
3943 if (GET_MODE_SIZE (GET_MODE (to
)) < GET_MODE_SIZE (SImode
))
3945 target
= gen_reg_rtx (SImode
);
3947 expand_fix (target
, from
, unsignedp
);
3949 else if (GET_MODE (from
) == SFmode
)
3951 if (GET_MODE (to
) == SImode
)
3952 libfcn
= unsignedp
? fixunssfsi_libfunc
: fixsfsi_libfunc
;
3953 else if (GET_MODE (to
) == DImode
)
3954 libfcn
= unsignedp
? fixunssfdi_libfunc
: fixsfdi_libfunc
;
3955 else if (GET_MODE (to
) == TImode
)
3956 libfcn
= unsignedp
? fixunssfti_libfunc
: fixsfti_libfunc
;
3960 else if (GET_MODE (from
) == DFmode
)
3962 if (GET_MODE (to
) == SImode
)
3963 libfcn
= unsignedp
? fixunsdfsi_libfunc
: fixdfsi_libfunc
;
3964 else if (GET_MODE (to
) == DImode
)
3965 libfcn
= unsignedp
? fixunsdfdi_libfunc
: fixdfdi_libfunc
;
3966 else if (GET_MODE (to
) == TImode
)
3967 libfcn
= unsignedp
? fixunsdfti_libfunc
: fixdfti_libfunc
;
3971 else if (GET_MODE (from
) == XFmode
)
3973 if (GET_MODE (to
) == SImode
)
3974 libfcn
= unsignedp
? fixunsxfsi_libfunc
: fixxfsi_libfunc
;
3975 else if (GET_MODE (to
) == DImode
)
3976 libfcn
= unsignedp
? fixunsxfdi_libfunc
: fixxfdi_libfunc
;
3977 else if (GET_MODE (to
) == TImode
)
3978 libfcn
= unsignedp
? fixunsxfti_libfunc
: fixxfti_libfunc
;
3982 else if (GET_MODE (from
) == TFmode
)
3984 if (GET_MODE (to
) == SImode
)
3985 libfcn
= unsignedp
? fixunstfsi_libfunc
: fixtfsi_libfunc
;
3986 else if (GET_MODE (to
) == DImode
)
3987 libfcn
= unsignedp
? fixunstfdi_libfunc
: fixtfdi_libfunc
;
3988 else if (GET_MODE (to
) == TImode
)
3989 libfcn
= unsignedp
? fixunstfti_libfunc
: fixtfti_libfunc
;
4001 to
= protect_from_queue (to
, 1);
4002 from
= protect_from_queue (from
, 0);
4005 from
= force_not_mem (from
);
4009 value
= emit_library_call_value (libfcn
, NULL_RTX
, 1, GET_MODE (to
),
4011 1, from
, GET_MODE (from
));
4012 insns
= get_insns ();
4015 emit_libcall_block (insns
, target
, value
,
4016 gen_rtx_fmt_e (unsignedp
? UNSIGNED_FIX
: FIX
,
4017 GET_MODE (to
), from
));
4022 if (GET_MODE (to
) == GET_MODE (target
))
4023 emit_move_insn (to
, target
);
4025 convert_move (to
, target
, 0);
4034 optab op
= (optab
) xmalloc (sizeof (struct optab
));
4036 for (i
= 0; i
< NUM_MACHINE_MODES
; i
++)
4038 op
->handlers
[i
].insn_code
= CODE_FOR_nothing
;
4039 op
->handlers
[i
].libfunc
= 0;
4042 if (code
!= UNKNOWN
)
4043 code_to_optab
[(int) code
] = op
;
4048 /* Initialize the libfunc fields of an entire group of entries in some
4049 optab. Each entry is set equal to a string consisting of a leading
4050 pair of underscores followed by a generic operation name followed by
4051 a mode name (downshifted to lower case) followed by a single character
4052 representing the number of operands for the given operation (which is
4053 usually one of the characters '2', '3', or '4').
4055 OPTABLE is the table in which libfunc fields are to be initialized.
4056 FIRST_MODE is the first machine mode index in the given optab to
4058 LAST_MODE is the last machine mode index in the given optab to
4060 OPNAME is the generic (string) name of the operation.
4061 SUFFIX is the character which specifies the number of operands for
4062 the given generic operation.
4066 init_libfuncs (optable
, first_mode
, last_mode
, opname
, suffix
)
4067 register optab optable
;
4068 register int first_mode
;
4069 register int last_mode
;
4070 register char *opname
;
4071 register int suffix
;
4074 register unsigned opname_len
= strlen (opname
);
4076 for (mode
= first_mode
; (int) mode
<= (int) last_mode
;
4077 mode
= (enum machine_mode
) ((int) mode
+ 1))
4079 register char *mname
= mode_name
[(int) mode
];
4080 register unsigned mname_len
= strlen (mname
);
4081 register char *libfunc_name
4082 = (char *) xmalloc (2 + opname_len
+ mname_len
+ 1 + 1);
4089 for (q
= opname
; *q
; )
4091 for (q
= mname
; *q
; q
++)
4092 *p
++ = tolower ((unsigned char)*q
);
4095 optable
->handlers
[(int) mode
].libfunc
4096 = gen_rtx_SYMBOL_REF (Pmode
, libfunc_name
);
4100 /* Initialize the libfunc fields of an entire group of entries in some
4101 optab which correspond to all integer mode operations. The parameters
4102 have the same meaning as similarly named ones for the `init_libfuncs'
4103 routine. (See above). */
4106 init_integral_libfuncs (optable
, opname
, suffix
)
4107 register optab optable
;
4108 register char *opname
;
4109 register int suffix
;
4111 init_libfuncs (optable
, SImode
, TImode
, opname
, suffix
);
4114 /* Initialize the libfunc fields of an entire group of entries in some
4115 optab which correspond to all real mode operations. The parameters
4116 have the same meaning as similarly named ones for the `init_libfuncs'
4117 routine. (See above). */
4120 init_floating_libfuncs (optable
, opname
, suffix
)
4121 register optab optable
;
4122 register char *opname
;
4123 register int suffix
;
4125 init_libfuncs (optable
, SFmode
, TFmode
, opname
, suffix
);
4129 /* Call this once to initialize the contents of the optabs
4130 appropriately for the current target machine. */
4136 #ifdef FIXUNS_TRUNC_LIKE_FIX_TRUNC
4142 /* Start by initializing all tables to contain CODE_FOR_nothing. */
4144 for (p
= fixtab
[0][0];
4145 p
< fixtab
[0][0] + sizeof fixtab
/ sizeof (fixtab
[0][0][0]);
4147 *p
= CODE_FOR_nothing
;
4149 for (p
= fixtrunctab
[0][0];
4150 p
< fixtrunctab
[0][0] + sizeof fixtrunctab
/ sizeof (fixtrunctab
[0][0][0]);
4152 *p
= CODE_FOR_nothing
;
4154 for (p
= floattab
[0][0];
4155 p
< floattab
[0][0] + sizeof floattab
/ sizeof (floattab
[0][0][0]);
4157 *p
= CODE_FOR_nothing
;
4159 for (p
= extendtab
[0][0];
4160 p
< extendtab
[0][0] + sizeof extendtab
/ sizeof extendtab
[0][0][0];
4162 *p
= CODE_FOR_nothing
;
4164 for (i
= 0; i
< NUM_RTX_CODE
; i
++)
4165 setcc_gen_code
[i
] = CODE_FOR_nothing
;
4167 #ifdef HAVE_conditional_move
4168 for (i
= 0; i
< NUM_MACHINE_MODES
; i
++)
4169 movcc_gen_code
[i
] = CODE_FOR_nothing
;
4172 add_optab
= init_optab (PLUS
);
4173 sub_optab
= init_optab (MINUS
);
4174 smul_optab
= init_optab (MULT
);
4175 smul_highpart_optab
= init_optab (UNKNOWN
);
4176 umul_highpart_optab
= init_optab (UNKNOWN
);
4177 smul_widen_optab
= init_optab (UNKNOWN
);
4178 umul_widen_optab
= init_optab (UNKNOWN
);
4179 sdiv_optab
= init_optab (DIV
);
4180 sdivmod_optab
= init_optab (UNKNOWN
);
4181 udiv_optab
= init_optab (UDIV
);
4182 udivmod_optab
= init_optab (UNKNOWN
);
4183 smod_optab
= init_optab (MOD
);
4184 umod_optab
= init_optab (UMOD
);
4185 flodiv_optab
= init_optab (DIV
);
4186 ftrunc_optab
= init_optab (UNKNOWN
);
4187 and_optab
= init_optab (AND
);
4188 ior_optab
= init_optab (IOR
);
4189 xor_optab
= init_optab (XOR
);
4190 ashl_optab
= init_optab (ASHIFT
);
4191 ashr_optab
= init_optab (ASHIFTRT
);
4192 lshr_optab
= init_optab (LSHIFTRT
);
4193 rotl_optab
= init_optab (ROTATE
);
4194 rotr_optab
= init_optab (ROTATERT
);
4195 smin_optab
= init_optab (SMIN
);
4196 smax_optab
= init_optab (SMAX
);
4197 umin_optab
= init_optab (UMIN
);
4198 umax_optab
= init_optab (UMAX
);
4199 mov_optab
= init_optab (UNKNOWN
);
4200 movstrict_optab
= init_optab (UNKNOWN
);
4201 cmp_optab
= init_optab (UNKNOWN
);
4202 ucmp_optab
= init_optab (UNKNOWN
);
4203 tst_optab
= init_optab (UNKNOWN
);
4204 neg_optab
= init_optab (NEG
);
4205 abs_optab
= init_optab (ABS
);
4206 one_cmpl_optab
= init_optab (NOT
);
4207 ffs_optab
= init_optab (FFS
);
4208 sqrt_optab
= init_optab (SQRT
);
4209 sin_optab
= init_optab (UNKNOWN
);
4210 cos_optab
= init_optab (UNKNOWN
);
4211 strlen_optab
= init_optab (UNKNOWN
);
4213 for (i
= 0; i
< NUM_MACHINE_MODES
; i
++)
4215 movstr_optab
[i
] = CODE_FOR_nothing
;
4216 clrstr_optab
[i
] = CODE_FOR_nothing
;
4218 #ifdef HAVE_SECONDARY_RELOADS
4219 reload_in_optab
[i
] = reload_out_optab
[i
] = CODE_FOR_nothing
;
4223 /* Fill in the optabs with the insns we support. */
4226 #ifdef FIXUNS_TRUNC_LIKE_FIX_TRUNC
4227 /* This flag says the same insns that convert to a signed fixnum
4228 also convert validly to an unsigned one. */
4229 for (i
= 0; i
< NUM_MACHINE_MODES
; i
++)
4230 for (j
= 0; j
< NUM_MACHINE_MODES
; j
++)
4231 fixtrunctab
[i
][j
][1] = fixtrunctab
[i
][j
][0];
4234 #ifdef EXTRA_CC_MODES
4238 /* Initialize the optabs with the names of the library functions. */
4239 init_integral_libfuncs (add_optab
, "add", '3');
4240 init_floating_libfuncs (add_optab
, "add", '3');
4241 init_integral_libfuncs (sub_optab
, "sub", '3');
4242 init_floating_libfuncs (sub_optab
, "sub", '3');
4243 init_integral_libfuncs (smul_optab
, "mul", '3');
4244 init_floating_libfuncs (smul_optab
, "mul", '3');
4245 init_integral_libfuncs (sdiv_optab
, "div", '3');
4246 init_integral_libfuncs (udiv_optab
, "udiv", '3');
4247 init_integral_libfuncs (sdivmod_optab
, "divmod", '4');
4248 init_integral_libfuncs (udivmod_optab
, "udivmod", '4');
4249 init_integral_libfuncs (smod_optab
, "mod", '3');
4250 init_integral_libfuncs (umod_optab
, "umod", '3');
4251 init_floating_libfuncs (flodiv_optab
, "div", '3');
4252 init_floating_libfuncs (ftrunc_optab
, "ftrunc", '2');
4253 init_integral_libfuncs (and_optab
, "and", '3');
4254 init_integral_libfuncs (ior_optab
, "ior", '3');
4255 init_integral_libfuncs (xor_optab
, "xor", '3');
4256 init_integral_libfuncs (ashl_optab
, "ashl", '3');
4257 init_integral_libfuncs (ashr_optab
, "ashr", '3');
4258 init_integral_libfuncs (lshr_optab
, "lshr", '3');
4259 init_integral_libfuncs (smin_optab
, "min", '3');
4260 init_floating_libfuncs (smin_optab
, "min", '3');
4261 init_integral_libfuncs (smax_optab
, "max", '3');
4262 init_floating_libfuncs (smax_optab
, "max", '3');
4263 init_integral_libfuncs (umin_optab
, "umin", '3');
4264 init_integral_libfuncs (umax_optab
, "umax", '3');
4265 init_integral_libfuncs (neg_optab
, "neg", '2');
4266 init_floating_libfuncs (neg_optab
, "neg", '2');
4267 init_integral_libfuncs (one_cmpl_optab
, "one_cmpl", '2');
4268 init_integral_libfuncs (ffs_optab
, "ffs", '2');
4270 /* Comparison libcalls for integers MUST come in pairs, signed/unsigned. */
4271 init_integral_libfuncs (cmp_optab
, "cmp", '2');
4272 init_integral_libfuncs (ucmp_optab
, "ucmp", '2');
4273 init_floating_libfuncs (cmp_optab
, "cmp", '2');
4275 #ifdef MULSI3_LIBCALL
4276 smul_optab
->handlers
[(int) SImode
].libfunc
4277 = gen_rtx_SYMBOL_REF (Pmode
, MULSI3_LIBCALL
);
4279 #ifdef MULDI3_LIBCALL
4280 smul_optab
->handlers
[(int) DImode
].libfunc
4281 = gen_rtx_SYMBOL_REF (Pmode
, MULDI3_LIBCALL
);
4284 #ifdef DIVSI3_LIBCALL
4285 sdiv_optab
->handlers
[(int) SImode
].libfunc
4286 = gen_rtx_SYMBOL_REF (Pmode
, DIVSI3_LIBCALL
);
4288 #ifdef DIVDI3_LIBCALL
4289 sdiv_optab
->handlers
[(int) DImode
].libfunc
4290 = gen_rtx_SYMBOL_REF (Pmode
, DIVDI3_LIBCALL
);
4293 #ifdef UDIVSI3_LIBCALL
4294 udiv_optab
->handlers
[(int) SImode
].libfunc
4295 = gen_rtx_SYMBOL_REF (Pmode
, UDIVSI3_LIBCALL
);
4297 #ifdef UDIVDI3_LIBCALL
4298 udiv_optab
->handlers
[(int) DImode
].libfunc
4299 = gen_rtx_SYMBOL_REF (Pmode
, UDIVDI3_LIBCALL
);
4302 #ifdef MODSI3_LIBCALL
4303 smod_optab
->handlers
[(int) SImode
].libfunc
4304 = gen_rtx_SYMBOL_REF (Pmode
, MODSI3_LIBCALL
);
4306 #ifdef MODDI3_LIBCALL
4307 smod_optab
->handlers
[(int) DImode
].libfunc
4308 = gen_rtx_SYMBOL_REF (Pmode
, MODDI3_LIBCALL
);
4311 #ifdef UMODSI3_LIBCALL
4312 umod_optab
->handlers
[(int) SImode
].libfunc
4313 = gen_rtx_SYMBOL_REF (Pmode
, UMODSI3_LIBCALL
);
4315 #ifdef UMODDI3_LIBCALL
4316 umod_optab
->handlers
[(int) DImode
].libfunc
4317 = gen_rtx_SYMBOL_REF (Pmode
, UMODDI3_LIBCALL
);
4320 /* Use cabs for DC complex abs, since systems generally have cabs.
4321 Don't define any libcall for SCmode, so that cabs will be used. */
4322 abs_optab
->handlers
[(int) DCmode
].libfunc
4323 = gen_rtx_SYMBOL_REF (Pmode
, "cabs");
4325 /* The ffs function operates on `int'. */
4326 #ifndef INT_TYPE_SIZE
4327 #define INT_TYPE_SIZE BITS_PER_WORD
4329 ffs_optab
->handlers
[(int) mode_for_size (INT_TYPE_SIZE
, MODE_INT
, 0)] .libfunc
4330 = gen_rtx_SYMBOL_REF (Pmode
, "ffs");
4332 extendsfdf2_libfunc
= gen_rtx_SYMBOL_REF (Pmode
, "__extendsfdf2");
4333 extendsfxf2_libfunc
= gen_rtx_SYMBOL_REF (Pmode
, "__extendsfxf2");
4334 extendsftf2_libfunc
= gen_rtx_SYMBOL_REF (Pmode
, "__extendsftf2");
4335 extenddfxf2_libfunc
= gen_rtx_SYMBOL_REF (Pmode
, "__extenddfxf2");
4336 extenddftf2_libfunc
= gen_rtx_SYMBOL_REF (Pmode
, "__extenddftf2");
4338 truncdfsf2_libfunc
= gen_rtx_SYMBOL_REF (Pmode
, "__truncdfsf2");
4339 truncxfsf2_libfunc
= gen_rtx_SYMBOL_REF (Pmode
, "__truncxfsf2");
4340 trunctfsf2_libfunc
= gen_rtx_SYMBOL_REF (Pmode
, "__trunctfsf2");
4341 truncxfdf2_libfunc
= gen_rtx_SYMBOL_REF (Pmode
, "__truncxfdf2");
4342 trunctfdf2_libfunc
= gen_rtx_SYMBOL_REF (Pmode
, "__trunctfdf2");
4344 memcpy_libfunc
= gen_rtx_SYMBOL_REF (Pmode
, "memcpy");
4345 bcopy_libfunc
= gen_rtx_SYMBOL_REF (Pmode
, "bcopy");
4346 memcmp_libfunc
= gen_rtx_SYMBOL_REF (Pmode
, "memcmp");
4347 bcmp_libfunc
= gen_rtx_SYMBOL_REF (Pmode
, "__gcc_bcmp");
4348 memset_libfunc
= gen_rtx_SYMBOL_REF (Pmode
, "memset");
4349 bzero_libfunc
= gen_rtx_SYMBOL_REF (Pmode
, "bzero");
4351 throw_libfunc
= gen_rtx_SYMBOL_REF (Pmode
, "__throw");
4352 rethrow_libfunc
= gen_rtx_SYMBOL_REF (Pmode
, "__rethrow");
4353 sjthrow_libfunc
= gen_rtx_SYMBOL_REF (Pmode
, "__sjthrow");
4354 sjpopnthrow_libfunc
= gen_rtx_SYMBOL_REF (Pmode
, "__sjpopnthrow");
4355 terminate_libfunc
= gen_rtx_SYMBOL_REF (Pmode
, "__terminate");
4356 eh_rtime_match_libfunc
= gen_rtx_SYMBOL_REF (Pmode
, "__eh_rtime_match");
4357 #ifndef DONT_USE_BUILTIN_SETJMP
4358 setjmp_libfunc
= gen_rtx_SYMBOL_REF (Pmode
, "__builtin_setjmp");
4359 longjmp_libfunc
= gen_rtx_SYMBOL_REF (Pmode
, "__builtin_longjmp");
4361 setjmp_libfunc
= gen_rtx_SYMBOL_REF (Pmode
, "setjmp");
4362 longjmp_libfunc
= gen_rtx_SYMBOL_REF (Pmode
, "longjmp");
4365 eqhf2_libfunc
= gen_rtx_SYMBOL_REF (Pmode
, "__eqhf2");
4366 nehf2_libfunc
= gen_rtx_SYMBOL_REF (Pmode
, "__nehf2");
4367 gthf2_libfunc
= gen_rtx_SYMBOL_REF (Pmode
, "__gthf2");
4368 gehf2_libfunc
= gen_rtx_SYMBOL_REF (Pmode
, "__gehf2");
4369 lthf2_libfunc
= gen_rtx_SYMBOL_REF (Pmode
, "__lthf2");
4370 lehf2_libfunc
= gen_rtx_SYMBOL_REF (Pmode
, "__lehf2");
4372 eqsf2_libfunc
= gen_rtx_SYMBOL_REF (Pmode
, "__eqsf2");
4373 nesf2_libfunc
= gen_rtx_SYMBOL_REF (Pmode
, "__nesf2");
4374 gtsf2_libfunc
= gen_rtx_SYMBOL_REF (Pmode
, "__gtsf2");
4375 gesf2_libfunc
= gen_rtx_SYMBOL_REF (Pmode
, "__gesf2");
4376 ltsf2_libfunc
= gen_rtx_SYMBOL_REF (Pmode
, "__ltsf2");
4377 lesf2_libfunc
= gen_rtx_SYMBOL_REF (Pmode
, "__lesf2");
4379 eqdf2_libfunc
= gen_rtx_SYMBOL_REF (Pmode
, "__eqdf2");
4380 nedf2_libfunc
= gen_rtx_SYMBOL_REF (Pmode
, "__nedf2");
4381 gtdf2_libfunc
= gen_rtx_SYMBOL_REF (Pmode
, "__gtdf2");
4382 gedf2_libfunc
= gen_rtx_SYMBOL_REF (Pmode
, "__gedf2");
4383 ltdf2_libfunc
= gen_rtx_SYMBOL_REF (Pmode
, "__ltdf2");
4384 ledf2_libfunc
= gen_rtx_SYMBOL_REF (Pmode
, "__ledf2");
4386 eqxf2_libfunc
= gen_rtx_SYMBOL_REF (Pmode
, "__eqxf2");
4387 nexf2_libfunc
= gen_rtx_SYMBOL_REF (Pmode
, "__nexf2");
4388 gtxf2_libfunc
= gen_rtx_SYMBOL_REF (Pmode
, "__gtxf2");
4389 gexf2_libfunc
= gen_rtx_SYMBOL_REF (Pmode
, "__gexf2");
4390 ltxf2_libfunc
= gen_rtx_SYMBOL_REF (Pmode
, "__ltxf2");
4391 lexf2_libfunc
= gen_rtx_SYMBOL_REF (Pmode
, "__lexf2");
4393 eqtf2_libfunc
= gen_rtx_SYMBOL_REF (Pmode
, "__eqtf2");
4394 netf2_libfunc
= gen_rtx_SYMBOL_REF (Pmode
, "__netf2");
4395 gttf2_libfunc
= gen_rtx_SYMBOL_REF (Pmode
, "__gttf2");
4396 getf2_libfunc
= gen_rtx_SYMBOL_REF (Pmode
, "__getf2");
4397 lttf2_libfunc
= gen_rtx_SYMBOL_REF (Pmode
, "__lttf2");
4398 letf2_libfunc
= gen_rtx_SYMBOL_REF (Pmode
, "__letf2");
4400 floatsisf_libfunc
= gen_rtx_SYMBOL_REF (Pmode
, "__floatsisf");
4401 floatdisf_libfunc
= gen_rtx_SYMBOL_REF (Pmode
, "__floatdisf");
4402 floattisf_libfunc
= gen_rtx_SYMBOL_REF (Pmode
, "__floattisf");
4404 floatsidf_libfunc
= gen_rtx_SYMBOL_REF (Pmode
, "__floatsidf");
4405 floatdidf_libfunc
= gen_rtx_SYMBOL_REF (Pmode
, "__floatdidf");
4406 floattidf_libfunc
= gen_rtx_SYMBOL_REF (Pmode
, "__floattidf");
4408 floatsixf_libfunc
= gen_rtx_SYMBOL_REF (Pmode
, "__floatsixf");
4409 floatdixf_libfunc
= gen_rtx_SYMBOL_REF (Pmode
, "__floatdixf");
4410 floattixf_libfunc
= gen_rtx_SYMBOL_REF (Pmode
, "__floattixf");
4412 floatsitf_libfunc
= gen_rtx_SYMBOL_REF (Pmode
, "__floatsitf");
4413 floatditf_libfunc
= gen_rtx_SYMBOL_REF (Pmode
, "__floatditf");
4414 floattitf_libfunc
= gen_rtx_SYMBOL_REF (Pmode
, "__floattitf");
4416 fixsfsi_libfunc
= gen_rtx_SYMBOL_REF (Pmode
, "__fixsfsi");
4417 fixsfdi_libfunc
= gen_rtx_SYMBOL_REF (Pmode
, "__fixsfdi");
4418 fixsfti_libfunc
= gen_rtx_SYMBOL_REF (Pmode
, "__fixsfti");
4420 fixdfsi_libfunc
= gen_rtx_SYMBOL_REF (Pmode
, "__fixdfsi");
4421 fixdfdi_libfunc
= gen_rtx_SYMBOL_REF (Pmode
, "__fixdfdi");
4422 fixdfti_libfunc
= gen_rtx_SYMBOL_REF (Pmode
, "__fixdfti");
4424 fixxfsi_libfunc
= gen_rtx_SYMBOL_REF (Pmode
, "__fixxfsi");
4425 fixxfdi_libfunc
= gen_rtx_SYMBOL_REF (Pmode
, "__fixxfdi");
4426 fixxfti_libfunc
= gen_rtx_SYMBOL_REF (Pmode
, "__fixxfti");
4428 fixtfsi_libfunc
= gen_rtx_SYMBOL_REF (Pmode
, "__fixtfsi");
4429 fixtfdi_libfunc
= gen_rtx_SYMBOL_REF (Pmode
, "__fixtfdi");
4430 fixtfti_libfunc
= gen_rtx_SYMBOL_REF (Pmode
, "__fixtfti");
4432 fixunssfsi_libfunc
= gen_rtx_SYMBOL_REF (Pmode
, "__fixunssfsi");
4433 fixunssfdi_libfunc
= gen_rtx_SYMBOL_REF (Pmode
, "__fixunssfdi");
4434 fixunssfti_libfunc
= gen_rtx_SYMBOL_REF (Pmode
, "__fixunssfti");
4436 fixunsdfsi_libfunc
= gen_rtx_SYMBOL_REF (Pmode
, "__fixunsdfsi");
4437 fixunsdfdi_libfunc
= gen_rtx_SYMBOL_REF (Pmode
, "__fixunsdfdi");
4438 fixunsdfti_libfunc
= gen_rtx_SYMBOL_REF (Pmode
, "__fixunsdfti");
4440 fixunsxfsi_libfunc
= gen_rtx_SYMBOL_REF (Pmode
, "__fixunsxfsi");
4441 fixunsxfdi_libfunc
= gen_rtx_SYMBOL_REF (Pmode
, "__fixunsxfdi");
4442 fixunsxfti_libfunc
= gen_rtx_SYMBOL_REF (Pmode
, "__fixunsxfti");
4444 fixunstfsi_libfunc
= gen_rtx_SYMBOL_REF (Pmode
, "__fixunstfsi");
4445 fixunstfdi_libfunc
= gen_rtx_SYMBOL_REF (Pmode
, "__fixunstfdi");
4446 fixunstfti_libfunc
= gen_rtx_SYMBOL_REF (Pmode
, "__fixunstfti");
4448 /* For check-memory-usage. */
4449 chkr_check_addr_libfunc
= gen_rtx_SYMBOL_REF (Pmode
, "chkr_check_addr");
4450 chkr_set_right_libfunc
= gen_rtx_SYMBOL_REF (Pmode
, "chkr_set_right");
4451 chkr_copy_bitmap_libfunc
= gen_rtx_SYMBOL_REF (Pmode
, "chkr_copy_bitmap");
4452 chkr_check_exec_libfunc
= gen_rtx_SYMBOL_REF (Pmode
, "chkr_check_exec");
4453 chkr_check_str_libfunc
= gen_rtx_SYMBOL_REF (Pmode
, "chkr_check_str");
4455 /* For function entry/exit instrumentation. */
4456 profile_function_entry_libfunc
4457 = gen_rtx_SYMBOL_REF (Pmode
, "__cyg_profile_func_enter");
4458 profile_function_exit_libfunc
4459 = gen_rtx_SYMBOL_REF (Pmode
, "__cyg_profile_func_exit");
4461 #ifdef HAVE_conditional_trap
4465 #ifdef INIT_TARGET_OPTABS
4466 /* Allow the target to add more libcalls or rename some, etc. */
4473 /* SCO 3.2 apparently has a broken ldexp. */
4486 #endif /* BROKEN_LDEXP */
4488 #ifdef HAVE_conditional_trap
4489 /* The insn generating function can not take an rtx_code argument.
4490 TRAP_RTX is used as an rtx argument. Its code is replaced with
4491 the code to be used in the trap insn and all other fields are
4494 ??? Will need to change to support garbage collection. */
4495 static rtx trap_rtx
;
4500 if (HAVE_conditional_trap
)
4501 trap_rtx
= gen_rtx_fmt_ee (EQ
, VOIDmode
, NULL_RTX
, NULL_RTX
);
4505 /* Generate insns to trap with code TCODE if OP1 and OP2 satisfy condition
4506 CODE. Return 0 on failure. */
4509 gen_cond_trap (code
, op1
, op2
, tcode
)
4510 enum rtx_code code ATTRIBUTE_UNUSED
;
4511 rtx op1
, op2 ATTRIBUTE_UNUSED
, tcode ATTRIBUTE_UNUSED
;
4513 enum machine_mode mode
= GET_MODE (op1
);
4515 if (mode
== VOIDmode
)
4518 #ifdef HAVE_conditional_trap
4519 if (HAVE_conditional_trap
4520 && cmp_optab
->handlers
[(int) mode
].insn_code
!= CODE_FOR_nothing
)
4523 emit_insn (GEN_FCN (cmp_optab
->handlers
[(int) mode
].insn_code
) (op1
, op2
));
4524 PUT_CODE (trap_rtx
, code
);
4525 insn
= gen_conditional_trap (trap_rtx
, tcode
);