1 /* Expand the basic unary and binary arithmetic operations, for GNU compiler.
2 Copyright (C) 1987-2015 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify it under
7 the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 3, or (at your option) any later
11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
23 #include "coretypes.h"
26 #include "diagnostic-core.h"
28 /* Include insn-config.h before expr.h so that HAVE_conditional_move
29 is properly defined. */
30 #include "insn-config.h"
34 #include "tree-hasher.h"
35 #include "stor-layout.h"
36 #include "stringpool.h"
48 #include "insn-codes.h"
55 struct target_optabs default_target_optabs
;
56 struct target_libfuncs default_target_libfuncs
;
57 struct target_optabs
*this_fn_optabs
= &default_target_optabs
;
59 struct target_optabs
*this_target_optabs
= &default_target_optabs
;
60 struct target_libfuncs
*this_target_libfuncs
= &default_target_libfuncs
;
63 #define libfunc_hash \
64 (this_target_libfuncs->x_libfunc_hash)
66 static void prepare_float_lib_cmp (rtx
, rtx
, enum rtx_code
, rtx
*,
68 static rtx
expand_unop_direct (machine_mode
, optab
, rtx
, rtx
, int);
69 static void emit_libcall_block_1 (rtx_insn
*, rtx
, rtx
, rtx
, bool);
71 /* Debug facility for use in GDB. */
72 void debug_optab_libfuncs (void);
74 /* Prefixes for the current version of decimal floating point (BID vs. DPD) */
75 #if ENABLE_DECIMAL_BID_FORMAT
76 #define DECIMAL_PREFIX "bid_"
78 #define DECIMAL_PREFIX "dpd_"
81 /* Used for libfunc_hash. */
84 libfunc_hasher::hash (libfunc_entry
*e
)
86 return ((e
->mode1
+ e
->mode2
* NUM_MACHINE_MODES
) ^ e
->op
);
89 /* Used for libfunc_hash. */
92 libfunc_hasher::equal (libfunc_entry
*e1
, libfunc_entry
*e2
)
94 return e1
->op
== e2
->op
&& e1
->mode1
== e2
->mode1
&& e1
->mode2
== e2
->mode2
;
97 /* Return libfunc corresponding operation defined by OPTAB converting
98 from MODE2 to MODE1. Trigger lazy initialization if needed, return NULL
99 if no libfunc is available. */
101 convert_optab_libfunc (convert_optab optab
, machine_mode mode1
,
104 struct libfunc_entry e
;
105 struct libfunc_entry
**slot
;
107 /* ??? This ought to be an assert, but not all of the places
108 that we expand optabs know about the optabs that got moved
110 if (!(optab
>= FIRST_CONV_OPTAB
&& optab
<= LAST_CONVLIB_OPTAB
))
116 slot
= libfunc_hash
->find_slot (&e
, NO_INSERT
);
119 const struct convert_optab_libcall_d
*d
120 = &convlib_def
[optab
- FIRST_CONV_OPTAB
];
122 if (d
->libcall_gen
== NULL
)
125 d
->libcall_gen (optab
, d
->libcall_basename
, mode1
, mode2
);
126 slot
= libfunc_hash
->find_slot (&e
, NO_INSERT
);
130 return (*slot
)->libfunc
;
133 /* Return libfunc corresponding operation defined by OPTAB in MODE.
134 Trigger lazy initialization if needed, return NULL if no libfunc is
137 optab_libfunc (optab optab
, machine_mode mode
)
139 struct libfunc_entry e
;
140 struct libfunc_entry
**slot
;
142 /* ??? This ought to be an assert, but not all of the places
143 that we expand optabs know about the optabs that got moved
145 if (!(optab
>= FIRST_NORM_OPTAB
&& optab
<= LAST_NORMLIB_OPTAB
))
151 slot
= libfunc_hash
->find_slot (&e
, NO_INSERT
);
154 const struct optab_libcall_d
*d
155 = &normlib_def
[optab
- FIRST_NORM_OPTAB
];
157 if (d
->libcall_gen
== NULL
)
160 d
->libcall_gen (optab
, d
->libcall_basename
, d
->libcall_suffix
, mode
);
161 slot
= libfunc_hash
->find_slot (&e
, NO_INSERT
);
165 return (*slot
)->libfunc
;
169 /* Add a REG_EQUAL note to the last insn in INSNS. TARGET is being set to
170 the result of operation CODE applied to OP0 (and OP1 if it is a binary
173 If the last insn does not set TARGET, don't do anything, but return 1.
175 If the last insn or a previous insn sets TARGET and TARGET is one of OP0
176 or OP1, don't add the REG_EQUAL note but return 0. Our caller can then
177 try again, ensuring that TARGET is not one of the operands. */
180 add_equal_note (rtx_insn
*insns
, rtx target
, enum rtx_code code
, rtx op0
, rtx op1
)
186 gcc_assert (insns
&& INSN_P (insns
) && NEXT_INSN (insns
));
188 if (GET_RTX_CLASS (code
) != RTX_COMM_ARITH
189 && GET_RTX_CLASS (code
) != RTX_BIN_ARITH
190 && GET_RTX_CLASS (code
) != RTX_COMM_COMPARE
191 && GET_RTX_CLASS (code
) != RTX_COMPARE
192 && GET_RTX_CLASS (code
) != RTX_UNARY
)
195 if (GET_CODE (target
) == ZERO_EXTRACT
)
198 for (last_insn
= insns
;
199 NEXT_INSN (last_insn
) != NULL_RTX
;
200 last_insn
= NEXT_INSN (last_insn
))
203 /* If TARGET is in OP0 or OP1, punt. We'd end up with a note referencing
204 a value changing in the insn, so the note would be invalid for CSE. */
205 if (reg_overlap_mentioned_p (target
, op0
)
206 || (op1
&& reg_overlap_mentioned_p (target
, op1
)))
209 && (rtx_equal_p (target
, op0
)
210 || (op1
&& rtx_equal_p (target
, op1
))))
212 /* For MEM target, with MEM = MEM op X, prefer no REG_EQUAL note
213 over expanding it as temp = MEM op X, MEM = temp. If the target
214 supports MEM = MEM op X instructions, it is sometimes too hard
215 to reconstruct that form later, especially if X is also a memory,
216 and due to multiple occurrences of addresses the address might
217 be forced into register unnecessarily.
218 Note that not emitting the REG_EQUIV note might inhibit
219 CSE in some cases. */
220 set
= single_set (last_insn
);
222 && GET_CODE (SET_SRC (set
)) == code
223 && MEM_P (SET_DEST (set
))
224 && (rtx_equal_p (SET_DEST (set
), XEXP (SET_SRC (set
), 0))
225 || (op1
&& rtx_equal_p (SET_DEST (set
),
226 XEXP (SET_SRC (set
), 1)))))
232 set
= set_for_reg_notes (last_insn
);
236 if (! rtx_equal_p (SET_DEST (set
), target
)
237 /* For a STRICT_LOW_PART, the REG_NOTE applies to what is inside it. */
238 && (GET_CODE (SET_DEST (set
)) != STRICT_LOW_PART
239 || ! rtx_equal_p (XEXP (SET_DEST (set
), 0), target
)))
242 if (GET_RTX_CLASS (code
) == RTX_UNARY
)
252 if (GET_MODE (op0
) != VOIDmode
&& GET_MODE (target
) != GET_MODE (op0
))
254 note
= gen_rtx_fmt_e (code
, GET_MODE (op0
), copy_rtx (op0
));
255 if (GET_MODE_SIZE (GET_MODE (op0
))
256 > GET_MODE_SIZE (GET_MODE (target
)))
257 note
= simplify_gen_unary (TRUNCATE
, GET_MODE (target
),
258 note
, GET_MODE (op0
));
260 note
= simplify_gen_unary (ZERO_EXTEND
, GET_MODE (target
),
261 note
, GET_MODE (op0
));
266 note
= gen_rtx_fmt_e (code
, GET_MODE (target
), copy_rtx (op0
));
270 note
= gen_rtx_fmt_ee (code
, GET_MODE (target
), copy_rtx (op0
), copy_rtx (op1
));
272 set_unique_reg_note (last_insn
, REG_EQUAL
, note
);
277 /* Given two input operands, OP0 and OP1, determine what the correct from_mode
278 for a widening operation would be. In most cases this would be OP0, but if
279 that's a constant it'll be VOIDmode, which isn't useful. */
282 widened_mode (machine_mode to_mode
, rtx op0
, rtx op1
)
284 machine_mode m0
= GET_MODE (op0
);
285 machine_mode m1
= GET_MODE (op1
);
288 if (m0
== VOIDmode
&& m1
== VOIDmode
)
290 else if (m0
== VOIDmode
|| GET_MODE_SIZE (m0
) < GET_MODE_SIZE (m1
))
295 if (GET_MODE_SIZE (result
) > GET_MODE_SIZE (to_mode
))
301 /* Like optab_handler, but for widening_operations that have a
302 TO_MODE and a FROM_MODE. */
305 widening_optab_handler (optab op
, machine_mode to_mode
,
306 machine_mode from_mode
)
308 unsigned scode
= (op
<< 16) | to_mode
;
309 if (to_mode
!= from_mode
&& from_mode
!= VOIDmode
)
311 /* ??? Why does find_widening_optab_handler_and_mode attempt to
312 widen things that can't be widened? E.g. add_optab... */
313 if (op
> LAST_CONV_OPTAB
)
314 return CODE_FOR_nothing
;
315 scode
|= from_mode
<< 8;
317 return raw_optab_handler (scode
);
320 /* Find a widening optab even if it doesn't widen as much as we want.
321 E.g. if from_mode is HImode, and to_mode is DImode, and there is no
322 direct HI->SI insn, then return SI->DI, if that exists.
323 If PERMIT_NON_WIDENING is non-zero then this can be used with
324 non-widening optabs also. */
327 find_widening_optab_handler_and_mode (optab op
, machine_mode to_mode
,
328 machine_mode from_mode
,
329 int permit_non_widening
,
330 machine_mode
*found_mode
)
332 for (; (permit_non_widening
|| from_mode
!= to_mode
)
333 && GET_MODE_SIZE (from_mode
) <= GET_MODE_SIZE (to_mode
)
334 && from_mode
!= VOIDmode
;
335 from_mode
= GET_MODE_WIDER_MODE (from_mode
))
337 enum insn_code handler
= widening_optab_handler (op
, to_mode
,
340 if (handler
!= CODE_FOR_nothing
)
343 *found_mode
= from_mode
;
348 return CODE_FOR_nothing
;
351 /* Widen OP to MODE and return the rtx for the widened operand. UNSIGNEDP
352 says whether OP is signed or unsigned. NO_EXTEND is nonzero if we need
353 not actually do a sign-extend or zero-extend, but can leave the
354 higher-order bits of the result rtx undefined, for example, in the case
355 of logical operations, but not right shifts. */
358 widen_operand (rtx op
, machine_mode mode
, machine_mode oldmode
,
359 int unsignedp
, int no_extend
)
363 /* If we don't have to extend and this is a constant, return it. */
364 if (no_extend
&& GET_MODE (op
) == VOIDmode
)
367 /* If we must extend do so. If OP is a SUBREG for a promoted object, also
368 extend since it will be more efficient to do so unless the signedness of
369 a promoted object differs from our extension. */
371 || (GET_CODE (op
) == SUBREG
&& SUBREG_PROMOTED_VAR_P (op
)
372 && SUBREG_CHECK_PROMOTED_SIGN (op
, unsignedp
)))
373 return convert_modes (mode
, oldmode
, op
, unsignedp
);
375 /* If MODE is no wider than a single word, we return a lowpart or paradoxical
377 if (GET_MODE_SIZE (mode
) <= UNITS_PER_WORD
)
378 return gen_lowpart (mode
, force_reg (GET_MODE (op
), op
));
380 /* Otherwise, get an object of MODE, clobber it, and set the low-order
383 result
= gen_reg_rtx (mode
);
384 emit_clobber (result
);
385 emit_move_insn (gen_lowpart (GET_MODE (op
), result
), op
);
389 /* Return the optab used for computing the operation given by the tree code,
390 CODE and the tree EXP. This function is not always usable (for example, it
391 cannot give complete results for multiplication or division) but probably
392 ought to be relied on more widely throughout the expander. */
394 optab_for_tree_code (enum tree_code code
, const_tree type
,
395 enum optab_subtype subtype
)
407 return one_cmpl_optab
;
412 case MULT_HIGHPART_EXPR
:
413 return TYPE_UNSIGNED (type
) ? umul_highpart_optab
: smul_highpart_optab
;
419 return TYPE_UNSIGNED (type
) ? umod_optab
: smod_optab
;
427 if (TYPE_SATURATING (type
))
428 return TYPE_UNSIGNED (type
) ? usdiv_optab
: ssdiv_optab
;
429 return TYPE_UNSIGNED (type
) ? udiv_optab
: sdiv_optab
;
432 if (TREE_CODE (type
) == VECTOR_TYPE
)
434 if (subtype
== optab_vector
)
435 return TYPE_SATURATING (type
) ? unknown_optab
: vashl_optab
;
437 gcc_assert (subtype
== optab_scalar
);
439 if (TYPE_SATURATING (type
))
440 return TYPE_UNSIGNED (type
) ? usashl_optab
: ssashl_optab
;
444 if (TREE_CODE (type
) == VECTOR_TYPE
)
446 if (subtype
== optab_vector
)
447 return TYPE_UNSIGNED (type
) ? vlshr_optab
: vashr_optab
;
449 gcc_assert (subtype
== optab_scalar
);
451 return TYPE_UNSIGNED (type
) ? lshr_optab
: ashr_optab
;
454 if (TREE_CODE (type
) == VECTOR_TYPE
)
456 if (subtype
== optab_vector
)
459 gcc_assert (subtype
== optab_scalar
);
464 if (TREE_CODE (type
) == VECTOR_TYPE
)
466 if (subtype
== optab_vector
)
469 gcc_assert (subtype
== optab_scalar
);
474 return TYPE_UNSIGNED (type
) ? umax_optab
: smax_optab
;
477 return TYPE_UNSIGNED (type
) ? umin_optab
: smin_optab
;
479 case REALIGN_LOAD_EXPR
:
480 return vec_realign_load_optab
;
483 return TYPE_UNSIGNED (type
) ? usum_widen_optab
: ssum_widen_optab
;
486 return TYPE_UNSIGNED (type
) ? udot_prod_optab
: sdot_prod_optab
;
489 return TYPE_UNSIGNED (type
) ? usad_optab
: ssad_optab
;
491 case WIDEN_MULT_PLUS_EXPR
:
492 return (TYPE_UNSIGNED (type
)
493 ? (TYPE_SATURATING (type
)
494 ? usmadd_widen_optab
: umadd_widen_optab
)
495 : (TYPE_SATURATING (type
)
496 ? ssmadd_widen_optab
: smadd_widen_optab
));
498 case WIDEN_MULT_MINUS_EXPR
:
499 return (TYPE_UNSIGNED (type
)
500 ? (TYPE_SATURATING (type
)
501 ? usmsub_widen_optab
: umsub_widen_optab
)
502 : (TYPE_SATURATING (type
)
503 ? ssmsub_widen_optab
: smsub_widen_optab
));
509 return TYPE_UNSIGNED (type
)
510 ? reduc_umax_scal_optab
: reduc_smax_scal_optab
;
513 return TYPE_UNSIGNED (type
)
514 ? reduc_umin_scal_optab
: reduc_smin_scal_optab
;
516 case REDUC_PLUS_EXPR
:
517 return reduc_plus_scal_optab
;
519 case VEC_WIDEN_MULT_HI_EXPR
:
520 return TYPE_UNSIGNED (type
) ?
521 vec_widen_umult_hi_optab
: vec_widen_smult_hi_optab
;
523 case VEC_WIDEN_MULT_LO_EXPR
:
524 return TYPE_UNSIGNED (type
) ?
525 vec_widen_umult_lo_optab
: vec_widen_smult_lo_optab
;
527 case VEC_WIDEN_MULT_EVEN_EXPR
:
528 return TYPE_UNSIGNED (type
) ?
529 vec_widen_umult_even_optab
: vec_widen_smult_even_optab
;
531 case VEC_WIDEN_MULT_ODD_EXPR
:
532 return TYPE_UNSIGNED (type
) ?
533 vec_widen_umult_odd_optab
: vec_widen_smult_odd_optab
;
535 case VEC_WIDEN_LSHIFT_HI_EXPR
:
536 return TYPE_UNSIGNED (type
) ?
537 vec_widen_ushiftl_hi_optab
: vec_widen_sshiftl_hi_optab
;
539 case VEC_WIDEN_LSHIFT_LO_EXPR
:
540 return TYPE_UNSIGNED (type
) ?
541 vec_widen_ushiftl_lo_optab
: vec_widen_sshiftl_lo_optab
;
543 case VEC_UNPACK_HI_EXPR
:
544 return TYPE_UNSIGNED (type
) ?
545 vec_unpacku_hi_optab
: vec_unpacks_hi_optab
;
547 case VEC_UNPACK_LO_EXPR
:
548 return TYPE_UNSIGNED (type
) ?
549 vec_unpacku_lo_optab
: vec_unpacks_lo_optab
;
551 case VEC_UNPACK_FLOAT_HI_EXPR
:
552 /* The signedness is determined from input operand. */
553 return TYPE_UNSIGNED (type
) ?
554 vec_unpacku_float_hi_optab
: vec_unpacks_float_hi_optab
;
556 case VEC_UNPACK_FLOAT_LO_EXPR
:
557 /* The signedness is determined from input operand. */
558 return TYPE_UNSIGNED (type
) ?
559 vec_unpacku_float_lo_optab
: vec_unpacks_float_lo_optab
;
561 case VEC_PACK_TRUNC_EXPR
:
562 return vec_pack_trunc_optab
;
564 case VEC_PACK_SAT_EXPR
:
565 return TYPE_UNSIGNED (type
) ? vec_pack_usat_optab
: vec_pack_ssat_optab
;
567 case VEC_PACK_FIX_TRUNC_EXPR
:
568 /* The signedness is determined from output operand. */
569 return TYPE_UNSIGNED (type
) ?
570 vec_pack_ufix_trunc_optab
: vec_pack_sfix_trunc_optab
;
576 trapv
= INTEGRAL_TYPE_P (type
) && TYPE_OVERFLOW_TRAPS (type
);
579 case POINTER_PLUS_EXPR
:
581 if (TYPE_SATURATING (type
))
582 return TYPE_UNSIGNED (type
) ? usadd_optab
: ssadd_optab
;
583 return trapv
? addv_optab
: add_optab
;
586 if (TYPE_SATURATING (type
))
587 return TYPE_UNSIGNED (type
) ? ussub_optab
: sssub_optab
;
588 return trapv
? subv_optab
: sub_optab
;
591 if (TYPE_SATURATING (type
))
592 return TYPE_UNSIGNED (type
) ? usmul_optab
: ssmul_optab
;
593 return trapv
? smulv_optab
: smul_optab
;
596 if (TYPE_SATURATING (type
))
597 return TYPE_UNSIGNED (type
) ? usneg_optab
: ssneg_optab
;
598 return trapv
? negv_optab
: neg_optab
;
601 return trapv
? absv_optab
: abs_optab
;
604 return unknown_optab
;
608 /* Given optab UNOPTAB that reduces a vector to a scalar, find instead the old
609 optab that produces a vector with the reduction result in one element,
610 for a tree with type TYPE. */
613 scalar_reduc_to_vector (optab unoptab
, const_tree type
)
617 case reduc_plus_scal_optab
:
618 return TYPE_UNSIGNED (type
) ? reduc_uplus_optab
: reduc_splus_optab
;
620 case reduc_smin_scal_optab
: return reduc_smin_optab
;
621 case reduc_umin_scal_optab
: return reduc_umin_optab
;
622 case reduc_smax_scal_optab
: return reduc_smax_optab
;
623 case reduc_umax_scal_optab
: return reduc_umax_optab
;
624 default: return unknown_optab
;
628 /* Expand vector widening operations.
630 There are two different classes of operations handled here:
631 1) Operations whose result is wider than all the arguments to the operation.
632 Examples: VEC_UNPACK_HI/LO_EXPR, VEC_WIDEN_MULT_HI/LO_EXPR
633 In this case OP0 and optionally OP1 would be initialized,
634 but WIDE_OP wouldn't (not relevant for this case).
635 2) Operations whose result is of the same size as the last argument to the
636 operation, but wider than all the other arguments to the operation.
637 Examples: WIDEN_SUM_EXPR, VEC_DOT_PROD_EXPR.
638 In the case WIDE_OP, OP0 and optionally OP1 would be initialized.
640 E.g, when called to expand the following operations, this is how
641 the arguments will be initialized:
643 widening-sum 2 oprnd0 - oprnd1
644 widening-dot-product 3 oprnd0 oprnd1 oprnd2
645 widening-mult 2 oprnd0 oprnd1 -
646 type-promotion (vec-unpack) 1 oprnd0 - - */
649 expand_widen_pattern_expr (sepops ops
, rtx op0
, rtx op1
, rtx wide_op
,
650 rtx target
, int unsignedp
)
652 struct expand_operand eops
[4];
653 tree oprnd0
, oprnd1
, oprnd2
;
654 machine_mode wmode
= VOIDmode
, tmode0
, tmode1
= VOIDmode
;
655 optab widen_pattern_optab
;
656 enum insn_code icode
;
657 int nops
= TREE_CODE_LENGTH (ops
->code
);
661 tmode0
= TYPE_MODE (TREE_TYPE (oprnd0
));
662 widen_pattern_optab
=
663 optab_for_tree_code (ops
->code
, TREE_TYPE (oprnd0
), optab_default
);
664 if (ops
->code
== WIDEN_MULT_PLUS_EXPR
665 || ops
->code
== WIDEN_MULT_MINUS_EXPR
)
666 icode
= find_widening_optab_handler (widen_pattern_optab
,
667 TYPE_MODE (TREE_TYPE (ops
->op2
)),
670 icode
= optab_handler (widen_pattern_optab
, tmode0
);
671 gcc_assert (icode
!= CODE_FOR_nothing
);
676 tmode1
= TYPE_MODE (TREE_TYPE (oprnd1
));
679 /* The last operand is of a wider mode than the rest of the operands. */
684 gcc_assert (tmode1
== tmode0
);
687 wmode
= TYPE_MODE (TREE_TYPE (oprnd2
));
691 create_output_operand (&eops
[op
++], target
, TYPE_MODE (ops
->type
));
692 create_convert_operand_from (&eops
[op
++], op0
, tmode0
, unsignedp
);
694 create_convert_operand_from (&eops
[op
++], op1
, tmode1
, unsignedp
);
696 create_convert_operand_from (&eops
[op
++], wide_op
, wmode
, unsignedp
);
697 expand_insn (icode
, op
, eops
);
698 return eops
[0].value
;
701 /* Generate code to perform an operation specified by TERNARY_OPTAB
702 on operands OP0, OP1 and OP2, with result having machine-mode MODE.
704 UNSIGNEDP is for the case where we have to widen the operands
705 to perform the operation. It says to use zero-extension.
707 If TARGET is nonzero, the value
708 is generated there, if it is convenient to do so.
709 In all cases an rtx is returned for the locus of the value;
710 this may or may not be TARGET. */
713 expand_ternary_op (machine_mode mode
, optab ternary_optab
, rtx op0
,
714 rtx op1
, rtx op2
, rtx target
, int unsignedp
)
716 struct expand_operand ops
[4];
717 enum insn_code icode
= optab_handler (ternary_optab
, mode
);
719 gcc_assert (optab_handler (ternary_optab
, mode
) != CODE_FOR_nothing
);
721 create_output_operand (&ops
[0], target
, mode
);
722 create_convert_operand_from (&ops
[1], op0
, mode
, unsignedp
);
723 create_convert_operand_from (&ops
[2], op1
, mode
, unsignedp
);
724 create_convert_operand_from (&ops
[3], op2
, mode
, unsignedp
);
725 expand_insn (icode
, 4, ops
);
730 /* Like expand_binop, but return a constant rtx if the result can be
731 calculated at compile time. The arguments and return value are
732 otherwise the same as for expand_binop. */
735 simplify_expand_binop (machine_mode mode
, optab binoptab
,
736 rtx op0
, rtx op1
, rtx target
, int unsignedp
,
737 enum optab_methods methods
)
739 if (CONSTANT_P (op0
) && CONSTANT_P (op1
))
741 rtx x
= simplify_binary_operation (optab_to_code (binoptab
),
747 return expand_binop (mode
, binoptab
, op0
, op1
, target
, unsignedp
, methods
);
750 /* Like simplify_expand_binop, but always put the result in TARGET.
751 Return true if the expansion succeeded. */
754 force_expand_binop (machine_mode mode
, optab binoptab
,
755 rtx op0
, rtx op1
, rtx target
, int unsignedp
,
756 enum optab_methods methods
)
758 rtx x
= simplify_expand_binop (mode
, binoptab
, op0
, op1
,
759 target
, unsignedp
, methods
);
763 emit_move_insn (target
, x
);
767 /* Create a new vector value in VMODE with all elements set to OP. The
768 mode of OP must be the element mode of VMODE. If OP is a constant,
769 then the return value will be a constant. */
772 expand_vector_broadcast (machine_mode vmode
, rtx op
)
774 enum insn_code icode
;
779 gcc_checking_assert (VECTOR_MODE_P (vmode
));
781 n
= GET_MODE_NUNITS (vmode
);
782 vec
= rtvec_alloc (n
);
783 for (i
= 0; i
< n
; ++i
)
784 RTVEC_ELT (vec
, i
) = op
;
787 return gen_rtx_CONST_VECTOR (vmode
, vec
);
789 /* ??? If the target doesn't have a vec_init, then we have no easy way
790 of performing this operation. Most of this sort of generic support
791 is hidden away in the vector lowering support in gimple. */
792 icode
= optab_handler (vec_init_optab
, vmode
);
793 if (icode
== CODE_FOR_nothing
)
796 ret
= gen_reg_rtx (vmode
);
797 emit_insn (GEN_FCN (icode
) (ret
, gen_rtx_PARALLEL (vmode
, vec
)));
802 /* This subroutine of expand_doubleword_shift handles the cases in which
803 the effective shift value is >= BITS_PER_WORD. The arguments and return
804 value are the same as for the parent routine, except that SUPERWORD_OP1
805 is the shift count to use when shifting OUTOF_INPUT into INTO_TARGET.
806 INTO_TARGET may be null if the caller has decided to calculate it. */
809 expand_superword_shift (optab binoptab
, rtx outof_input
, rtx superword_op1
,
810 rtx outof_target
, rtx into_target
,
811 int unsignedp
, enum optab_methods methods
)
813 if (into_target
!= 0)
814 if (!force_expand_binop (word_mode
, binoptab
, outof_input
, superword_op1
,
815 into_target
, unsignedp
, methods
))
818 if (outof_target
!= 0)
820 /* For a signed right shift, we must fill OUTOF_TARGET with copies
821 of the sign bit, otherwise we must fill it with zeros. */
822 if (binoptab
!= ashr_optab
)
823 emit_move_insn (outof_target
, CONST0_RTX (word_mode
));
825 if (!force_expand_binop (word_mode
, binoptab
,
826 outof_input
, GEN_INT (BITS_PER_WORD
- 1),
827 outof_target
, unsignedp
, methods
))
833 /* This subroutine of expand_doubleword_shift handles the cases in which
834 the effective shift value is < BITS_PER_WORD. The arguments and return
835 value are the same as for the parent routine. */
838 expand_subword_shift (machine_mode op1_mode
, optab binoptab
,
839 rtx outof_input
, rtx into_input
, rtx op1
,
840 rtx outof_target
, rtx into_target
,
841 int unsignedp
, enum optab_methods methods
,
842 unsigned HOST_WIDE_INT shift_mask
)
844 optab reverse_unsigned_shift
, unsigned_shift
;
847 reverse_unsigned_shift
= (binoptab
== ashl_optab
? lshr_optab
: ashl_optab
);
848 unsigned_shift
= (binoptab
== ashl_optab
? ashl_optab
: lshr_optab
);
850 /* The low OP1 bits of INTO_TARGET come from the high bits of OUTOF_INPUT.
851 We therefore need to shift OUTOF_INPUT by (BITS_PER_WORD - OP1) bits in
852 the opposite direction to BINOPTAB. */
853 if (CONSTANT_P (op1
) || shift_mask
>= BITS_PER_WORD
)
855 carries
= outof_input
;
856 tmp
= immed_wide_int_const (wi::shwi (BITS_PER_WORD
,
857 op1_mode
), op1_mode
);
858 tmp
= simplify_expand_binop (op1_mode
, sub_optab
, tmp
, op1
,
863 /* We must avoid shifting by BITS_PER_WORD bits since that is either
864 the same as a zero shift (if shift_mask == BITS_PER_WORD - 1) or
865 has unknown behavior. Do a single shift first, then shift by the
866 remainder. It's OK to use ~OP1 as the remainder if shift counts
867 are truncated to the mode size. */
868 carries
= expand_binop (word_mode
, reverse_unsigned_shift
,
869 outof_input
, const1_rtx
, 0, unsignedp
, methods
);
870 if (shift_mask
== BITS_PER_WORD
- 1)
872 tmp
= immed_wide_int_const
873 (wi::minus_one (GET_MODE_PRECISION (op1_mode
)), op1_mode
);
874 tmp
= simplify_expand_binop (op1_mode
, xor_optab
, op1
, tmp
,
879 tmp
= immed_wide_int_const (wi::shwi (BITS_PER_WORD
- 1,
880 op1_mode
), op1_mode
);
881 tmp
= simplify_expand_binop (op1_mode
, sub_optab
, tmp
, op1
,
885 if (tmp
== 0 || carries
== 0)
887 carries
= expand_binop (word_mode
, reverse_unsigned_shift
,
888 carries
, tmp
, 0, unsignedp
, methods
);
892 /* Shift INTO_INPUT logically by OP1. This is the last use of INTO_INPUT
893 so the result can go directly into INTO_TARGET if convenient. */
894 tmp
= expand_binop (word_mode
, unsigned_shift
, into_input
, op1
,
895 into_target
, unsignedp
, methods
);
899 /* Now OR in the bits carried over from OUTOF_INPUT. */
900 if (!force_expand_binop (word_mode
, ior_optab
, tmp
, carries
,
901 into_target
, unsignedp
, methods
))
904 /* Use a standard word_mode shift for the out-of half. */
905 if (outof_target
!= 0)
906 if (!force_expand_binop (word_mode
, binoptab
, outof_input
, op1
,
907 outof_target
, unsignedp
, methods
))
914 /* Try implementing expand_doubleword_shift using conditional moves.
915 The shift is by < BITS_PER_WORD if (CMP_CODE CMP1 CMP2) is true,
916 otherwise it is by >= BITS_PER_WORD. SUBWORD_OP1 and SUPERWORD_OP1
917 are the shift counts to use in the former and latter case. All other
918 arguments are the same as the parent routine. */
921 expand_doubleword_shift_condmove (machine_mode op1_mode
, optab binoptab
,
922 enum rtx_code cmp_code
, rtx cmp1
, rtx cmp2
,
923 rtx outof_input
, rtx into_input
,
924 rtx subword_op1
, rtx superword_op1
,
925 rtx outof_target
, rtx into_target
,
926 int unsignedp
, enum optab_methods methods
,
927 unsigned HOST_WIDE_INT shift_mask
)
929 rtx outof_superword
, into_superword
;
931 /* Put the superword version of the output into OUTOF_SUPERWORD and
933 outof_superword
= outof_target
!= 0 ? gen_reg_rtx (word_mode
) : 0;
934 if (outof_target
!= 0 && subword_op1
== superword_op1
)
936 /* The value INTO_TARGET >> SUBWORD_OP1, which we later store in
937 OUTOF_TARGET, is the same as the value of INTO_SUPERWORD. */
938 into_superword
= outof_target
;
939 if (!expand_superword_shift (binoptab
, outof_input
, superword_op1
,
940 outof_superword
, 0, unsignedp
, methods
))
945 into_superword
= gen_reg_rtx (word_mode
);
946 if (!expand_superword_shift (binoptab
, outof_input
, superword_op1
,
947 outof_superword
, into_superword
,
952 /* Put the subword version directly in OUTOF_TARGET and INTO_TARGET. */
953 if (!expand_subword_shift (op1_mode
, binoptab
,
954 outof_input
, into_input
, subword_op1
,
955 outof_target
, into_target
,
956 unsignedp
, methods
, shift_mask
))
959 /* Select between them. Do the INTO half first because INTO_SUPERWORD
960 might be the current value of OUTOF_TARGET. */
961 if (!emit_conditional_move (into_target
, cmp_code
, cmp1
, cmp2
, op1_mode
,
962 into_target
, into_superword
, word_mode
, false))
965 if (outof_target
!= 0)
966 if (!emit_conditional_move (outof_target
, cmp_code
, cmp1
, cmp2
, op1_mode
,
967 outof_target
, outof_superword
,
974 /* Expand a doubleword shift (ashl, ashr or lshr) using word-mode shifts.
975 OUTOF_INPUT and INTO_INPUT are the two word-sized halves of the first
976 input operand; the shift moves bits in the direction OUTOF_INPUT->
977 INTO_TARGET. OUTOF_TARGET and INTO_TARGET are the equivalent words
978 of the target. OP1 is the shift count and OP1_MODE is its mode.
979 If OP1 is constant, it will have been truncated as appropriate
980 and is known to be nonzero.
982 If SHIFT_MASK is zero, the result of word shifts is undefined when the
983 shift count is outside the range [0, BITS_PER_WORD). This routine must
984 avoid generating such shifts for OP1s in the range [0, BITS_PER_WORD * 2).
986 If SHIFT_MASK is nonzero, all word-mode shift counts are effectively
987 masked by it and shifts in the range [BITS_PER_WORD, SHIFT_MASK) will
988 fill with zeros or sign bits as appropriate.
990 If SHIFT_MASK is BITS_PER_WORD - 1, this routine will synthesize
991 a doubleword shift whose equivalent mask is BITS_PER_WORD * 2 - 1.
992 Doing this preserves semantics required by SHIFT_COUNT_TRUNCATED.
993 In all other cases, shifts by values outside [0, BITS_PER_UNIT * 2)
996 BINOPTAB, UNSIGNEDP and METHODS are as for expand_binop. This function
997 may not use INTO_INPUT after modifying INTO_TARGET, and similarly for
998 OUTOF_INPUT and OUTOF_TARGET. OUTOF_TARGET can be null if the parent
999 function wants to calculate it itself.
1001 Return true if the shift could be successfully synthesized. */
1004 expand_doubleword_shift (machine_mode op1_mode
, optab binoptab
,
1005 rtx outof_input
, rtx into_input
, rtx op1
,
1006 rtx outof_target
, rtx into_target
,
1007 int unsignedp
, enum optab_methods methods
,
1008 unsigned HOST_WIDE_INT shift_mask
)
1010 rtx superword_op1
, tmp
, cmp1
, cmp2
;
1011 enum rtx_code cmp_code
;
1013 /* See if word-mode shifts by BITS_PER_WORD...BITS_PER_WORD * 2 - 1 will
1014 fill the result with sign or zero bits as appropriate. If so, the value
1015 of OUTOF_TARGET will always be (SHIFT OUTOF_INPUT OP1). Recursively call
1016 this routine to calculate INTO_TARGET (which depends on both OUTOF_INPUT
1017 and INTO_INPUT), then emit code to set up OUTOF_TARGET.
1019 This isn't worthwhile for constant shifts since the optimizers will
1020 cope better with in-range shift counts. */
1021 if (shift_mask
>= BITS_PER_WORD
1022 && outof_target
!= 0
1023 && !CONSTANT_P (op1
))
1025 if (!expand_doubleword_shift (op1_mode
, binoptab
,
1026 outof_input
, into_input
, op1
,
1028 unsignedp
, methods
, shift_mask
))
1030 if (!force_expand_binop (word_mode
, binoptab
, outof_input
, op1
,
1031 outof_target
, unsignedp
, methods
))
1036 /* Set CMP_CODE, CMP1 and CMP2 so that the rtx (CMP_CODE CMP1 CMP2)
1037 is true when the effective shift value is less than BITS_PER_WORD.
1038 Set SUPERWORD_OP1 to the shift count that should be used to shift
1039 OUTOF_INPUT into INTO_TARGET when the condition is false. */
1040 tmp
= immed_wide_int_const (wi::shwi (BITS_PER_WORD
, op1_mode
), op1_mode
);
1041 if (!CONSTANT_P (op1
) && shift_mask
== BITS_PER_WORD
- 1)
1043 /* Set CMP1 to OP1 & BITS_PER_WORD. The result is zero iff OP1
1044 is a subword shift count. */
1045 cmp1
= simplify_expand_binop (op1_mode
, and_optab
, op1
, tmp
,
1047 cmp2
= CONST0_RTX (op1_mode
);
1049 superword_op1
= op1
;
1053 /* Set CMP1 to OP1 - BITS_PER_WORD. */
1054 cmp1
= simplify_expand_binop (op1_mode
, sub_optab
, op1
, tmp
,
1056 cmp2
= CONST0_RTX (op1_mode
);
1058 superword_op1
= cmp1
;
1063 /* If we can compute the condition at compile time, pick the
1064 appropriate subroutine. */
1065 tmp
= simplify_relational_operation (cmp_code
, SImode
, op1_mode
, cmp1
, cmp2
);
1066 if (tmp
!= 0 && CONST_INT_P (tmp
))
1068 if (tmp
== const0_rtx
)
1069 return expand_superword_shift (binoptab
, outof_input
, superword_op1
,
1070 outof_target
, into_target
,
1071 unsignedp
, methods
);
1073 return expand_subword_shift (op1_mode
, binoptab
,
1074 outof_input
, into_input
, op1
,
1075 outof_target
, into_target
,
1076 unsignedp
, methods
, shift_mask
);
1079 /* Try using conditional moves to generate straight-line code. */
1080 if (HAVE_conditional_move
)
1082 rtx_insn
*start
= get_last_insn ();
1083 if (expand_doubleword_shift_condmove (op1_mode
, binoptab
,
1084 cmp_code
, cmp1
, cmp2
,
1085 outof_input
, into_input
,
1087 outof_target
, into_target
,
1088 unsignedp
, methods
, shift_mask
))
1090 delete_insns_since (start
);
1093 /* As a last resort, use branches to select the correct alternative. */
1094 rtx_code_label
*subword_label
= gen_label_rtx ();
1095 rtx_code_label
*done_label
= gen_label_rtx ();
1098 do_compare_rtx_and_jump (cmp1
, cmp2
, cmp_code
, false, op1_mode
,
1099 0, 0, subword_label
, -1);
1102 if (!expand_superword_shift (binoptab
, outof_input
, superword_op1
,
1103 outof_target
, into_target
,
1104 unsignedp
, methods
))
1107 emit_jump_insn (targetm
.gen_jump (done_label
));
1109 emit_label (subword_label
);
1111 if (!expand_subword_shift (op1_mode
, binoptab
,
1112 outof_input
, into_input
, op1
,
1113 outof_target
, into_target
,
1114 unsignedp
, methods
, shift_mask
))
1117 emit_label (done_label
);
1121 /* Subroutine of expand_binop. Perform a double word multiplication of
1122 operands OP0 and OP1 both of mode MODE, which is exactly twice as wide
1123 as the target's word_mode. This function return NULL_RTX if anything
1124 goes wrong, in which case it may have already emitted instructions
1125 which need to be deleted.
1127 If we want to multiply two two-word values and have normal and widening
1128 multiplies of single-word values, we can do this with three smaller
1131 The multiplication proceeds as follows:
1132 _______________________
1133 [__op0_high_|__op0_low__]
1134 _______________________
1135 * [__op1_high_|__op1_low__]
1136 _______________________________________________
1137 _______________________
1138 (1) [__op0_low__*__op1_low__]
1139 _______________________
1140 (2a) [__op0_low__*__op1_high_]
1141 _______________________
1142 (2b) [__op0_high_*__op1_low__]
1143 _______________________
1144 (3) [__op0_high_*__op1_high_]
1147 This gives a 4-word result. Since we are only interested in the
1148 lower 2 words, partial result (3) and the upper words of (2a) and
1149 (2b) don't need to be calculated. Hence (2a) and (2b) can be
1150 calculated using non-widening multiplication.
1152 (1), however, needs to be calculated with an unsigned widening
1153 multiplication. If this operation is not directly supported we
1154 try using a signed widening multiplication and adjust the result.
1155 This adjustment works as follows:
1157 If both operands are positive then no adjustment is needed.
1159 If the operands have different signs, for example op0_low < 0 and
1160 op1_low >= 0, the instruction treats the most significant bit of
1161 op0_low as a sign bit instead of a bit with significance
1162 2**(BITS_PER_WORD-1), i.e. the instruction multiplies op1_low
1163 with 2**BITS_PER_WORD - op0_low, and two's complements the
1164 result. Conclusion: We need to add op1_low * 2**BITS_PER_WORD to
1167 Similarly, if both operands are negative, we need to add
1168 (op0_low + op1_low) * 2**BITS_PER_WORD.
1170 We use a trick to adjust quickly. We logically shift op0_low right
1171 (op1_low) BITS_PER_WORD-1 steps to get 0 or 1, and add this to
1172 op0_high (op1_high) before it is used to calculate 2b (2a). If no
1173 logical shift exists, we do an arithmetic right shift and subtract
1177 expand_doubleword_mult (machine_mode mode
, rtx op0
, rtx op1
, rtx target
,
1178 bool umulp
, enum optab_methods methods
)
1180 int low
= (WORDS_BIG_ENDIAN
? 1 : 0);
1181 int high
= (WORDS_BIG_ENDIAN
? 0 : 1);
1182 rtx wordm1
= umulp
? NULL_RTX
: GEN_INT (BITS_PER_WORD
- 1);
1183 rtx product
, adjust
, product_high
, temp
;
1185 rtx op0_high
= operand_subword_force (op0
, high
, mode
);
1186 rtx op0_low
= operand_subword_force (op0
, low
, mode
);
1187 rtx op1_high
= operand_subword_force (op1
, high
, mode
);
1188 rtx op1_low
= operand_subword_force (op1
, low
, mode
);
1190 /* If we're using an unsigned multiply to directly compute the product
1191 of the low-order words of the operands and perform any required
1192 adjustments of the operands, we begin by trying two more multiplications
1193 and then computing the appropriate sum.
1195 We have checked above that the required addition is provided.
1196 Full-word addition will normally always succeed, especially if
1197 it is provided at all, so we don't worry about its failure. The
1198 multiplication may well fail, however, so we do handle that. */
1202 /* ??? This could be done with emit_store_flag where available. */
1203 temp
= expand_binop (word_mode
, lshr_optab
, op0_low
, wordm1
,
1204 NULL_RTX
, 1, methods
);
1206 op0_high
= expand_binop (word_mode
, add_optab
, op0_high
, temp
,
1207 NULL_RTX
, 0, OPTAB_DIRECT
);
1210 temp
= expand_binop (word_mode
, ashr_optab
, op0_low
, wordm1
,
1211 NULL_RTX
, 0, methods
);
1214 op0_high
= expand_binop (word_mode
, sub_optab
, op0_high
, temp
,
1215 NULL_RTX
, 0, OPTAB_DIRECT
);
1222 adjust
= expand_binop (word_mode
, smul_optab
, op0_high
, op1_low
,
1223 NULL_RTX
, 0, OPTAB_DIRECT
);
1227 /* OP0_HIGH should now be dead. */
1231 /* ??? This could be done with emit_store_flag where available. */
1232 temp
= expand_binop (word_mode
, lshr_optab
, op1_low
, wordm1
,
1233 NULL_RTX
, 1, methods
);
1235 op1_high
= expand_binop (word_mode
, add_optab
, op1_high
, temp
,
1236 NULL_RTX
, 0, OPTAB_DIRECT
);
1239 temp
= expand_binop (word_mode
, ashr_optab
, op1_low
, wordm1
,
1240 NULL_RTX
, 0, methods
);
1243 op1_high
= expand_binop (word_mode
, sub_optab
, op1_high
, temp
,
1244 NULL_RTX
, 0, OPTAB_DIRECT
);
1251 temp
= expand_binop (word_mode
, smul_optab
, op1_high
, op0_low
,
1252 NULL_RTX
, 0, OPTAB_DIRECT
);
1256 /* OP1_HIGH should now be dead. */
1258 adjust
= expand_binop (word_mode
, add_optab
, adjust
, temp
,
1259 NULL_RTX
, 0, OPTAB_DIRECT
);
1261 if (target
&& !REG_P (target
))
1265 product
= expand_binop (mode
, umul_widen_optab
, op0_low
, op1_low
,
1266 target
, 1, OPTAB_DIRECT
);
1268 product
= expand_binop (mode
, smul_widen_optab
, op0_low
, op1_low
,
1269 target
, 1, OPTAB_DIRECT
);
1274 product_high
= operand_subword (product
, high
, 1, mode
);
1275 adjust
= expand_binop (word_mode
, add_optab
, product_high
, adjust
,
1276 NULL_RTX
, 0, OPTAB_DIRECT
);
1277 emit_move_insn (product_high
, adjust
);
1281 /* Wrapper around expand_binop which takes an rtx code to specify
1282 the operation to perform, not an optab pointer. All other
1283 arguments are the same. */
1285 expand_simple_binop (machine_mode mode
, enum rtx_code code
, rtx op0
,
1286 rtx op1
, rtx target
, int unsignedp
,
1287 enum optab_methods methods
)
1289 optab binop
= code_to_optab (code
);
1292 return expand_binop (mode
, binop
, op0
, op1
, target
, unsignedp
, methods
);
1295 /* Return whether OP0 and OP1 should be swapped when expanding a commutative
1296 binop. Order them according to commutative_operand_precedence and, if
1297 possible, try to put TARGET or a pseudo first. */
1299 swap_commutative_operands_with_target (rtx target
, rtx op0
, rtx op1
)
1301 int op0_prec
= commutative_operand_precedence (op0
);
1302 int op1_prec
= commutative_operand_precedence (op1
);
1304 if (op0_prec
< op1_prec
)
1307 if (op0_prec
> op1_prec
)
1310 /* With equal precedence, both orders are ok, but it is better if the
1311 first operand is TARGET, or if both TARGET and OP0 are pseudos. */
1312 if (target
== 0 || REG_P (target
))
1313 return (REG_P (op1
) && !REG_P (op0
)) || target
== op1
;
1315 return rtx_equal_p (op1
, target
);
1318 /* Return true if BINOPTAB implements a shift operation. */
1321 shift_optab_p (optab binoptab
)
1323 switch (optab_to_code (binoptab
))
1339 /* Return true if BINOPTAB implements a commutative binary operation. */
1342 commutative_optab_p (optab binoptab
)
1344 return (GET_RTX_CLASS (optab_to_code (binoptab
)) == RTX_COMM_ARITH
1345 || binoptab
== smul_widen_optab
1346 || binoptab
== umul_widen_optab
1347 || binoptab
== smul_highpart_optab
1348 || binoptab
== umul_highpart_optab
);
1351 /* X is to be used in mode MODE as operand OPN to BINOPTAB. If we're
1352 optimizing, and if the operand is a constant that costs more than
1353 1 instruction, force the constant into a register and return that
1354 register. Return X otherwise. UNSIGNEDP says whether X is unsigned. */
1357 avoid_expensive_constant (machine_mode mode
, optab binoptab
,
1358 int opn
, rtx x
, bool unsignedp
)
1360 bool speed
= optimize_insn_for_speed_p ();
1362 if (mode
!= VOIDmode
1365 && (rtx_cost (x
, mode
, optab_to_code (binoptab
), opn
, speed
)
1366 > set_src_cost (x
, mode
, speed
)))
1368 if (CONST_INT_P (x
))
1370 HOST_WIDE_INT intval
= trunc_int_for_mode (INTVAL (x
), mode
);
1371 if (intval
!= INTVAL (x
))
1372 x
= GEN_INT (intval
);
1375 x
= convert_modes (mode
, VOIDmode
, x
, unsignedp
);
1376 x
= force_reg (mode
, x
);
1381 /* Helper function for expand_binop: handle the case where there
1382 is an insn that directly implements the indicated operation.
1383 Returns null if this is not possible. */
1385 expand_binop_directly (machine_mode mode
, optab binoptab
,
1387 rtx target
, int unsignedp
, enum optab_methods methods
,
1390 machine_mode from_mode
= widened_mode (mode
, op0
, op1
);
1391 enum insn_code icode
= find_widening_optab_handler (binoptab
, mode
,
1393 machine_mode xmode0
= insn_data
[(int) icode
].operand
[1].mode
;
1394 machine_mode xmode1
= insn_data
[(int) icode
].operand
[2].mode
;
1395 machine_mode mode0
, mode1
, tmp_mode
;
1396 struct expand_operand ops
[3];
1399 rtx xop0
= op0
, xop1
= op1
;
1401 /* If it is a commutative operator and the modes would match
1402 if we would swap the operands, we can save the conversions. */
1403 commutative_p
= commutative_optab_p (binoptab
);
1405 && GET_MODE (xop0
) != xmode0
&& GET_MODE (xop1
) != xmode1
1406 && GET_MODE (xop0
) == xmode1
&& GET_MODE (xop1
) == xmode1
)
1407 std::swap (xop0
, xop1
);
1409 /* If we are optimizing, force expensive constants into a register. */
1410 xop0
= avoid_expensive_constant (xmode0
, binoptab
, 0, xop0
, unsignedp
);
1411 if (!shift_optab_p (binoptab
))
1412 xop1
= avoid_expensive_constant (xmode1
, binoptab
, 1, xop1
, unsignedp
);
1414 /* In case the insn wants input operands in modes different from
1415 those of the actual operands, convert the operands. It would
1416 seem that we don't need to convert CONST_INTs, but we do, so
1417 that they're properly zero-extended, sign-extended or truncated
1420 mode0
= GET_MODE (xop0
) != VOIDmode
? GET_MODE (xop0
) : mode
;
1421 if (xmode0
!= VOIDmode
&& xmode0
!= mode0
)
1423 xop0
= convert_modes (xmode0
, mode0
, xop0
, unsignedp
);
1427 mode1
= GET_MODE (xop1
) != VOIDmode
? GET_MODE (xop1
) : mode
;
1428 if (xmode1
!= VOIDmode
&& xmode1
!= mode1
)
1430 xop1
= convert_modes (xmode1
, mode1
, xop1
, unsignedp
);
1434 /* If operation is commutative,
1435 try to make the first operand a register.
1436 Even better, try to make it the same as the target.
1437 Also try to make the last operand a constant. */
1439 && swap_commutative_operands_with_target (target
, xop0
, xop1
))
1440 std::swap (xop0
, xop1
);
1442 /* Now, if insn's predicates don't allow our operands, put them into
1445 if (binoptab
== vec_pack_trunc_optab
1446 || binoptab
== vec_pack_usat_optab
1447 || binoptab
== vec_pack_ssat_optab
1448 || binoptab
== vec_pack_ufix_trunc_optab
1449 || binoptab
== vec_pack_sfix_trunc_optab
)
1451 /* The mode of the result is different then the mode of the
1453 tmp_mode
= insn_data
[(int) icode
].operand
[0].mode
;
1454 if (GET_MODE_NUNITS (tmp_mode
) != 2 * GET_MODE_NUNITS (mode
))
1456 delete_insns_since (last
);
1463 create_output_operand (&ops
[0], target
, tmp_mode
);
1464 create_input_operand (&ops
[1], xop0
, mode0
);
1465 create_input_operand (&ops
[2], xop1
, mode1
);
1466 pat
= maybe_gen_insn (icode
, 3, ops
);
1469 /* If PAT is composed of more than one insn, try to add an appropriate
1470 REG_EQUAL note to it. If we can't because TEMP conflicts with an
1471 operand, call expand_binop again, this time without a target. */
1472 if (INSN_P (pat
) && NEXT_INSN (pat
) != NULL_RTX
1473 && ! add_equal_note (pat
, ops
[0].value
,
1474 optab_to_code (binoptab
),
1475 ops
[1].value
, ops
[2].value
))
1477 delete_insns_since (last
);
1478 return expand_binop (mode
, binoptab
, op0
, op1
, NULL_RTX
,
1479 unsignedp
, methods
);
1483 return ops
[0].value
;
1485 delete_insns_since (last
);
1489 /* Generate code to perform an operation specified by BINOPTAB
1490 on operands OP0 and OP1, with result having machine-mode MODE.
1492 UNSIGNEDP is for the case where we have to widen the operands
1493 to perform the operation. It says to use zero-extension.
1495 If TARGET is nonzero, the value
1496 is generated there, if it is convenient to do so.
1497 In all cases an rtx is returned for the locus of the value;
1498 this may or may not be TARGET. */
1501 expand_binop (machine_mode mode
, optab binoptab
, rtx op0
, rtx op1
,
1502 rtx target
, int unsignedp
, enum optab_methods methods
)
1504 enum optab_methods next_methods
1505 = (methods
== OPTAB_LIB
|| methods
== OPTAB_LIB_WIDEN
1506 ? OPTAB_WIDEN
: methods
);
1507 enum mode_class mclass
;
1508 machine_mode wider_mode
;
1511 rtx_insn
*entry_last
= get_last_insn ();
1514 mclass
= GET_MODE_CLASS (mode
);
1516 /* If subtracting an integer constant, convert this into an addition of
1517 the negated constant. */
1519 if (binoptab
== sub_optab
&& CONST_INT_P (op1
))
1521 op1
= negate_rtx (mode
, op1
);
1522 binoptab
= add_optab
;
1525 /* Record where to delete back to if we backtrack. */
1526 last
= get_last_insn ();
1528 /* If we can do it with a three-operand insn, do so. */
1530 if (methods
!= OPTAB_MUST_WIDEN
1531 && find_widening_optab_handler (binoptab
, mode
,
1532 widened_mode (mode
, op0
, op1
), 1)
1533 != CODE_FOR_nothing
)
1535 temp
= expand_binop_directly (mode
, binoptab
, op0
, op1
, target
,
1536 unsignedp
, methods
, last
);
1541 /* If we were trying to rotate, and that didn't work, try rotating
1542 the other direction before falling back to shifts and bitwise-or. */
1543 if (((binoptab
== rotl_optab
1544 && optab_handler (rotr_optab
, mode
) != CODE_FOR_nothing
)
1545 || (binoptab
== rotr_optab
1546 && optab_handler (rotl_optab
, mode
) != CODE_FOR_nothing
))
1547 && mclass
== MODE_INT
)
1549 optab otheroptab
= (binoptab
== rotl_optab
? rotr_optab
: rotl_optab
);
1551 unsigned int bits
= GET_MODE_PRECISION (mode
);
1553 if (CONST_INT_P (op1
))
1554 newop1
= GEN_INT (bits
- INTVAL (op1
));
1555 else if (targetm
.shift_truncation_mask (mode
) == bits
- 1)
1556 newop1
= negate_rtx (GET_MODE (op1
), op1
);
1558 newop1
= expand_binop (GET_MODE (op1
), sub_optab
,
1559 gen_int_mode (bits
, GET_MODE (op1
)), op1
,
1560 NULL_RTX
, unsignedp
, OPTAB_DIRECT
);
1562 temp
= expand_binop_directly (mode
, otheroptab
, op0
, newop1
,
1563 target
, unsignedp
, methods
, last
);
1568 /* If this is a multiply, see if we can do a widening operation that
1569 takes operands of this mode and makes a wider mode. */
1571 if (binoptab
== smul_optab
1572 && GET_MODE_2XWIDER_MODE (mode
) != VOIDmode
1573 && (widening_optab_handler ((unsignedp
? umul_widen_optab
1574 : smul_widen_optab
),
1575 GET_MODE_2XWIDER_MODE (mode
), mode
)
1576 != CODE_FOR_nothing
))
1578 temp
= expand_binop (GET_MODE_2XWIDER_MODE (mode
),
1579 unsignedp
? umul_widen_optab
: smul_widen_optab
,
1580 op0
, op1
, NULL_RTX
, unsignedp
, OPTAB_DIRECT
);
1584 if (GET_MODE_CLASS (mode
) == MODE_INT
1585 && TRULY_NOOP_TRUNCATION_MODES_P (mode
, GET_MODE (temp
)))
1586 return gen_lowpart (mode
, temp
);
1588 return convert_to_mode (mode
, temp
, unsignedp
);
1592 /* If this is a vector shift by a scalar, see if we can do a vector
1593 shift by a vector. If so, broadcast the scalar into a vector. */
1594 if (mclass
== MODE_VECTOR_INT
)
1596 optab otheroptab
= unknown_optab
;
1598 if (binoptab
== ashl_optab
)
1599 otheroptab
= vashl_optab
;
1600 else if (binoptab
== ashr_optab
)
1601 otheroptab
= vashr_optab
;
1602 else if (binoptab
== lshr_optab
)
1603 otheroptab
= vlshr_optab
;
1604 else if (binoptab
== rotl_optab
)
1605 otheroptab
= vrotl_optab
;
1606 else if (binoptab
== rotr_optab
)
1607 otheroptab
= vrotr_optab
;
1609 if (otheroptab
&& optab_handler (otheroptab
, mode
) != CODE_FOR_nothing
)
1611 rtx vop1
= expand_vector_broadcast (mode
, op1
);
1614 temp
= expand_binop_directly (mode
, otheroptab
, op0
, vop1
,
1615 target
, unsignedp
, methods
, last
);
1622 /* Look for a wider mode of the same class for which we think we
1623 can open-code the operation. Check for a widening multiply at the
1624 wider mode as well. */
1626 if (CLASS_HAS_WIDER_MODES_P (mclass
)
1627 && methods
!= OPTAB_DIRECT
&& methods
!= OPTAB_LIB
)
1628 for (wider_mode
= GET_MODE_WIDER_MODE (mode
);
1629 wider_mode
!= VOIDmode
;
1630 wider_mode
= GET_MODE_WIDER_MODE (wider_mode
))
1632 if (optab_handler (binoptab
, wider_mode
) != CODE_FOR_nothing
1633 || (binoptab
== smul_optab
1634 && GET_MODE_WIDER_MODE (wider_mode
) != VOIDmode
1635 && (find_widening_optab_handler ((unsignedp
1637 : smul_widen_optab
),
1638 GET_MODE_WIDER_MODE (wider_mode
),
1640 != CODE_FOR_nothing
)))
1642 rtx xop0
= op0
, xop1
= op1
;
1645 /* For certain integer operations, we need not actually extend
1646 the narrow operands, as long as we will truncate
1647 the results to the same narrowness. */
1649 if ((binoptab
== ior_optab
|| binoptab
== and_optab
1650 || binoptab
== xor_optab
1651 || binoptab
== add_optab
|| binoptab
== sub_optab
1652 || binoptab
== smul_optab
|| binoptab
== ashl_optab
)
1653 && mclass
== MODE_INT
)
1656 xop0
= avoid_expensive_constant (mode
, binoptab
, 0,
1658 if (binoptab
!= ashl_optab
)
1659 xop1
= avoid_expensive_constant (mode
, binoptab
, 1,
1663 xop0
= widen_operand (xop0
, wider_mode
, mode
, unsignedp
, no_extend
);
1665 /* The second operand of a shift must always be extended. */
1666 xop1
= widen_operand (xop1
, wider_mode
, mode
, unsignedp
,
1667 no_extend
&& binoptab
!= ashl_optab
);
1669 temp
= expand_binop (wider_mode
, binoptab
, xop0
, xop1
, NULL_RTX
,
1670 unsignedp
, OPTAB_DIRECT
);
1673 if (mclass
!= MODE_INT
1674 || !TRULY_NOOP_TRUNCATION_MODES_P (mode
, wider_mode
))
1677 target
= gen_reg_rtx (mode
);
1678 convert_move (target
, temp
, 0);
1682 return gen_lowpart (mode
, temp
);
1685 delete_insns_since (last
);
1689 /* If operation is commutative,
1690 try to make the first operand a register.
1691 Even better, try to make it the same as the target.
1692 Also try to make the last operand a constant. */
1693 if (commutative_optab_p (binoptab
)
1694 && swap_commutative_operands_with_target (target
, op0
, op1
))
1695 std::swap (op0
, op1
);
1697 /* These can be done a word at a time. */
1698 if ((binoptab
== and_optab
|| binoptab
== ior_optab
|| binoptab
== xor_optab
)
1699 && mclass
== MODE_INT
1700 && GET_MODE_SIZE (mode
) > UNITS_PER_WORD
1701 && optab_handler (binoptab
, word_mode
) != CODE_FOR_nothing
)
1706 /* If TARGET is the same as one of the operands, the REG_EQUAL note
1707 won't be accurate, so use a new target. */
1711 || !valid_multiword_target_p (target
))
1712 target
= gen_reg_rtx (mode
);
1716 /* Do the actual arithmetic. */
1717 for (i
= 0; i
< GET_MODE_BITSIZE (mode
) / BITS_PER_WORD
; i
++)
1719 rtx target_piece
= operand_subword (target
, i
, 1, mode
);
1720 rtx x
= expand_binop (word_mode
, binoptab
,
1721 operand_subword_force (op0
, i
, mode
),
1722 operand_subword_force (op1
, i
, mode
),
1723 target_piece
, unsignedp
, next_methods
);
1728 if (target_piece
!= x
)
1729 emit_move_insn (target_piece
, x
);
1732 insns
= get_insns ();
1735 if (i
== GET_MODE_BITSIZE (mode
) / BITS_PER_WORD
)
1742 /* Synthesize double word shifts from single word shifts. */
1743 if ((binoptab
== lshr_optab
|| binoptab
== ashl_optab
1744 || binoptab
== ashr_optab
)
1745 && mclass
== MODE_INT
1746 && (CONST_INT_P (op1
) || optimize_insn_for_speed_p ())
1747 && GET_MODE_SIZE (mode
) == 2 * UNITS_PER_WORD
1748 && GET_MODE_PRECISION (mode
) == GET_MODE_BITSIZE (mode
)
1749 && optab_handler (binoptab
, word_mode
) != CODE_FOR_nothing
1750 && optab_handler (ashl_optab
, word_mode
) != CODE_FOR_nothing
1751 && optab_handler (lshr_optab
, word_mode
) != CODE_FOR_nothing
)
1753 unsigned HOST_WIDE_INT shift_mask
, double_shift_mask
;
1754 machine_mode op1_mode
;
1756 double_shift_mask
= targetm
.shift_truncation_mask (mode
);
1757 shift_mask
= targetm
.shift_truncation_mask (word_mode
);
1758 op1_mode
= GET_MODE (op1
) != VOIDmode
? GET_MODE (op1
) : word_mode
;
1760 /* Apply the truncation to constant shifts. */
1761 if (double_shift_mask
> 0 && CONST_INT_P (op1
))
1762 op1
= GEN_INT (INTVAL (op1
) & double_shift_mask
);
1764 if (op1
== CONST0_RTX (op1_mode
))
1767 /* Make sure that this is a combination that expand_doubleword_shift
1768 can handle. See the comments there for details. */
1769 if (double_shift_mask
== 0
1770 || (shift_mask
== BITS_PER_WORD
- 1
1771 && double_shift_mask
== BITS_PER_WORD
* 2 - 1))
1774 rtx into_target
, outof_target
;
1775 rtx into_input
, outof_input
;
1776 int left_shift
, outof_word
;
1778 /* If TARGET is the same as one of the operands, the REG_EQUAL note
1779 won't be accurate, so use a new target. */
1783 || !valid_multiword_target_p (target
))
1784 target
= gen_reg_rtx (mode
);
1788 /* OUTOF_* is the word we are shifting bits away from, and
1789 INTO_* is the word that we are shifting bits towards, thus
1790 they differ depending on the direction of the shift and
1791 WORDS_BIG_ENDIAN. */
1793 left_shift
= binoptab
== ashl_optab
;
1794 outof_word
= left_shift
^ ! WORDS_BIG_ENDIAN
;
1796 outof_target
= operand_subword (target
, outof_word
, 1, mode
);
1797 into_target
= operand_subword (target
, 1 - outof_word
, 1, mode
);
1799 outof_input
= operand_subword_force (op0
, outof_word
, mode
);
1800 into_input
= operand_subword_force (op0
, 1 - outof_word
, mode
);
1802 if (expand_doubleword_shift (op1_mode
, binoptab
,
1803 outof_input
, into_input
, op1
,
1804 outof_target
, into_target
,
1805 unsignedp
, next_methods
, shift_mask
))
1807 insns
= get_insns ();
1817 /* Synthesize double word rotates from single word shifts. */
1818 if ((binoptab
== rotl_optab
|| binoptab
== rotr_optab
)
1819 && mclass
== MODE_INT
1820 && CONST_INT_P (op1
)
1821 && GET_MODE_PRECISION (mode
) == 2 * BITS_PER_WORD
1822 && optab_handler (ashl_optab
, word_mode
) != CODE_FOR_nothing
1823 && optab_handler (lshr_optab
, word_mode
) != CODE_FOR_nothing
)
1826 rtx into_target
, outof_target
;
1827 rtx into_input
, outof_input
;
1829 int shift_count
, left_shift
, outof_word
;
1831 /* If TARGET is the same as one of the operands, the REG_EQUAL note
1832 won't be accurate, so use a new target. Do this also if target is not
1833 a REG, first because having a register instead may open optimization
1834 opportunities, and second because if target and op0 happen to be MEMs
1835 designating the same location, we would risk clobbering it too early
1836 in the code sequence we generate below. */
1841 || !valid_multiword_target_p (target
))
1842 target
= gen_reg_rtx (mode
);
1846 shift_count
= INTVAL (op1
);
1848 /* OUTOF_* is the word we are shifting bits away from, and
1849 INTO_* is the word that we are shifting bits towards, thus
1850 they differ depending on the direction of the shift and
1851 WORDS_BIG_ENDIAN. */
1853 left_shift
= (binoptab
== rotl_optab
);
1854 outof_word
= left_shift
^ ! WORDS_BIG_ENDIAN
;
1856 outof_target
= operand_subword (target
, outof_word
, 1, mode
);
1857 into_target
= operand_subword (target
, 1 - outof_word
, 1, mode
);
1859 outof_input
= operand_subword_force (op0
, outof_word
, mode
);
1860 into_input
= operand_subword_force (op0
, 1 - outof_word
, mode
);
1862 if (shift_count
== BITS_PER_WORD
)
1864 /* This is just a word swap. */
1865 emit_move_insn (outof_target
, into_input
);
1866 emit_move_insn (into_target
, outof_input
);
1871 rtx into_temp1
, into_temp2
, outof_temp1
, outof_temp2
;
1872 rtx first_shift_count
, second_shift_count
;
1873 optab reverse_unsigned_shift
, unsigned_shift
;
1875 reverse_unsigned_shift
= (left_shift
^ (shift_count
< BITS_PER_WORD
)
1876 ? lshr_optab
: ashl_optab
);
1878 unsigned_shift
= (left_shift
^ (shift_count
< BITS_PER_WORD
)
1879 ? ashl_optab
: lshr_optab
);
1881 if (shift_count
> BITS_PER_WORD
)
1883 first_shift_count
= GEN_INT (shift_count
- BITS_PER_WORD
);
1884 second_shift_count
= GEN_INT (2 * BITS_PER_WORD
- shift_count
);
1888 first_shift_count
= GEN_INT (BITS_PER_WORD
- shift_count
);
1889 second_shift_count
= GEN_INT (shift_count
);
1892 into_temp1
= expand_binop (word_mode
, unsigned_shift
,
1893 outof_input
, first_shift_count
,
1894 NULL_RTX
, unsignedp
, next_methods
);
1895 into_temp2
= expand_binop (word_mode
, reverse_unsigned_shift
,
1896 into_input
, second_shift_count
,
1897 NULL_RTX
, unsignedp
, next_methods
);
1899 if (into_temp1
!= 0 && into_temp2
!= 0)
1900 inter
= expand_binop (word_mode
, ior_optab
, into_temp1
, into_temp2
,
1901 into_target
, unsignedp
, next_methods
);
1905 if (inter
!= 0 && inter
!= into_target
)
1906 emit_move_insn (into_target
, inter
);
1908 outof_temp1
= expand_binop (word_mode
, unsigned_shift
,
1909 into_input
, first_shift_count
,
1910 NULL_RTX
, unsignedp
, next_methods
);
1911 outof_temp2
= expand_binop (word_mode
, reverse_unsigned_shift
,
1912 outof_input
, second_shift_count
,
1913 NULL_RTX
, unsignedp
, next_methods
);
1915 if (inter
!= 0 && outof_temp1
!= 0 && outof_temp2
!= 0)
1916 inter
= expand_binop (word_mode
, ior_optab
,
1917 outof_temp1
, outof_temp2
,
1918 outof_target
, unsignedp
, next_methods
);
1920 if (inter
!= 0 && inter
!= outof_target
)
1921 emit_move_insn (outof_target
, inter
);
1924 insns
= get_insns ();
1934 /* These can be done a word at a time by propagating carries. */
1935 if ((binoptab
== add_optab
|| binoptab
== sub_optab
)
1936 && mclass
== MODE_INT
1937 && GET_MODE_SIZE (mode
) >= 2 * UNITS_PER_WORD
1938 && optab_handler (binoptab
, word_mode
) != CODE_FOR_nothing
)
1941 optab otheroptab
= binoptab
== add_optab
? sub_optab
: add_optab
;
1942 const unsigned int nwords
= GET_MODE_BITSIZE (mode
) / BITS_PER_WORD
;
1943 rtx carry_in
= NULL_RTX
, carry_out
= NULL_RTX
;
1944 rtx xop0
, xop1
, xtarget
;
1946 /* We can handle either a 1 or -1 value for the carry. If STORE_FLAG
1947 value is one of those, use it. Otherwise, use 1 since it is the
1948 one easiest to get. */
1949 #if STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1
1950 int normalizep
= STORE_FLAG_VALUE
;
1955 /* Prepare the operands. */
1956 xop0
= force_reg (mode
, op0
);
1957 xop1
= force_reg (mode
, op1
);
1959 xtarget
= gen_reg_rtx (mode
);
1961 if (target
== 0 || !REG_P (target
) || !valid_multiword_target_p (target
))
1964 /* Indicate for flow that the entire target reg is being set. */
1966 emit_clobber (xtarget
);
1968 /* Do the actual arithmetic. */
1969 for (i
= 0; i
< nwords
; i
++)
1971 int index
= (WORDS_BIG_ENDIAN
? nwords
- i
- 1 : i
);
1972 rtx target_piece
= operand_subword (xtarget
, index
, 1, mode
);
1973 rtx op0_piece
= operand_subword_force (xop0
, index
, mode
);
1974 rtx op1_piece
= operand_subword_force (xop1
, index
, mode
);
1977 /* Main add/subtract of the input operands. */
1978 x
= expand_binop (word_mode
, binoptab
,
1979 op0_piece
, op1_piece
,
1980 target_piece
, unsignedp
, next_methods
);
1986 /* Store carry from main add/subtract. */
1987 carry_out
= gen_reg_rtx (word_mode
);
1988 carry_out
= emit_store_flag_force (carry_out
,
1989 (binoptab
== add_optab
1992 word_mode
, 1, normalizep
);
1999 /* Add/subtract previous carry to main result. */
2000 newx
= expand_binop (word_mode
,
2001 normalizep
== 1 ? binoptab
: otheroptab
,
2003 NULL_RTX
, 1, next_methods
);
2007 /* Get out carry from adding/subtracting carry in. */
2008 rtx carry_tmp
= gen_reg_rtx (word_mode
);
2009 carry_tmp
= emit_store_flag_force (carry_tmp
,
2010 (binoptab
== add_optab
2013 word_mode
, 1, normalizep
);
2015 /* Logical-ior the two poss. carry together. */
2016 carry_out
= expand_binop (word_mode
, ior_optab
,
2017 carry_out
, carry_tmp
,
2018 carry_out
, 0, next_methods
);
2022 emit_move_insn (target_piece
, newx
);
2026 if (x
!= target_piece
)
2027 emit_move_insn (target_piece
, x
);
2030 carry_in
= carry_out
;
2033 if (i
== GET_MODE_BITSIZE (mode
) / (unsigned) BITS_PER_WORD
)
2035 if (optab_handler (mov_optab
, mode
) != CODE_FOR_nothing
2036 || ! rtx_equal_p (target
, xtarget
))
2038 rtx_insn
*temp
= emit_move_insn (target
, xtarget
);
2040 set_dst_reg_note (temp
, REG_EQUAL
,
2041 gen_rtx_fmt_ee (optab_to_code (binoptab
),
2042 mode
, copy_rtx (xop0
),
2053 delete_insns_since (last
);
2056 /* Attempt to synthesize double word multiplies using a sequence of word
2057 mode multiplications. We first attempt to generate a sequence using a
2058 more efficient unsigned widening multiply, and if that fails we then
2059 try using a signed widening multiply. */
2061 if (binoptab
== smul_optab
2062 && mclass
== MODE_INT
2063 && GET_MODE_SIZE (mode
) == 2 * UNITS_PER_WORD
2064 && optab_handler (smul_optab
, word_mode
) != CODE_FOR_nothing
2065 && optab_handler (add_optab
, word_mode
) != CODE_FOR_nothing
)
2067 rtx product
= NULL_RTX
;
2068 if (widening_optab_handler (umul_widen_optab
, mode
, word_mode
)
2069 != CODE_FOR_nothing
)
2071 product
= expand_doubleword_mult (mode
, op0
, op1
, target
,
2074 delete_insns_since (last
);
2077 if (product
== NULL_RTX
2078 && widening_optab_handler (smul_widen_optab
, mode
, word_mode
)
2079 != CODE_FOR_nothing
)
2081 product
= expand_doubleword_mult (mode
, op0
, op1
, target
,
2084 delete_insns_since (last
);
2087 if (product
!= NULL_RTX
)
2089 if (optab_handler (mov_optab
, mode
) != CODE_FOR_nothing
)
2091 temp
= emit_move_insn (target
? target
: product
, product
);
2092 set_dst_reg_note (temp
,
2094 gen_rtx_fmt_ee (MULT
, mode
,
2097 target
? target
: product
);
2103 /* It can't be open-coded in this mode.
2104 Use a library call if one is available and caller says that's ok. */
2106 libfunc
= optab_libfunc (binoptab
, mode
);
2108 && (methods
== OPTAB_LIB
|| methods
== OPTAB_LIB_WIDEN
))
2112 machine_mode op1_mode
= mode
;
2117 if (shift_optab_p (binoptab
))
2119 op1_mode
= targetm
.libgcc_shift_count_mode ();
2120 /* Specify unsigned here,
2121 since negative shift counts are meaningless. */
2122 op1x
= convert_to_mode (op1_mode
, op1
, 1);
2125 if (GET_MODE (op0
) != VOIDmode
2126 && GET_MODE (op0
) != mode
)
2127 op0
= convert_to_mode (mode
, op0
, unsignedp
);
2129 /* Pass 1 for NO_QUEUE so we don't lose any increments
2130 if the libcall is cse'd or moved. */
2131 value
= emit_library_call_value (libfunc
,
2132 NULL_RTX
, LCT_CONST
, mode
, 2,
2133 op0
, mode
, op1x
, op1_mode
);
2135 insns
= get_insns ();
2138 target
= gen_reg_rtx (mode
);
2139 emit_libcall_block_1 (insns
, target
, value
,
2140 gen_rtx_fmt_ee (optab_to_code (binoptab
),
2142 trapv_binoptab_p (binoptab
));
2147 delete_insns_since (last
);
2149 /* It can't be done in this mode. Can we do it in a wider mode? */
2151 if (! (methods
== OPTAB_WIDEN
|| methods
== OPTAB_LIB_WIDEN
2152 || methods
== OPTAB_MUST_WIDEN
))
2154 /* Caller says, don't even try. */
2155 delete_insns_since (entry_last
);
2159 /* Compute the value of METHODS to pass to recursive calls.
2160 Don't allow widening to be tried recursively. */
2162 methods
= (methods
== OPTAB_LIB_WIDEN
? OPTAB_LIB
: OPTAB_DIRECT
);
2164 /* Look for a wider mode of the same class for which it appears we can do
2167 if (CLASS_HAS_WIDER_MODES_P (mclass
))
2169 for (wider_mode
= GET_MODE_WIDER_MODE (mode
);
2170 wider_mode
!= VOIDmode
;
2171 wider_mode
= GET_MODE_WIDER_MODE (wider_mode
))
2173 if (find_widening_optab_handler (binoptab
, wider_mode
, mode
, 1)
2175 || (methods
== OPTAB_LIB
2176 && optab_libfunc (binoptab
, wider_mode
)))
2178 rtx xop0
= op0
, xop1
= op1
;
2181 /* For certain integer operations, we need not actually extend
2182 the narrow operands, as long as we will truncate
2183 the results to the same narrowness. */
2185 if ((binoptab
== ior_optab
|| binoptab
== and_optab
2186 || binoptab
== xor_optab
2187 || binoptab
== add_optab
|| binoptab
== sub_optab
2188 || binoptab
== smul_optab
|| binoptab
== ashl_optab
)
2189 && mclass
== MODE_INT
)
2192 xop0
= widen_operand (xop0
, wider_mode
, mode
,
2193 unsignedp
, no_extend
);
2195 /* The second operand of a shift must always be extended. */
2196 xop1
= widen_operand (xop1
, wider_mode
, mode
, unsignedp
,
2197 no_extend
&& binoptab
!= ashl_optab
);
2199 temp
= expand_binop (wider_mode
, binoptab
, xop0
, xop1
, NULL_RTX
,
2200 unsignedp
, methods
);
2203 if (mclass
!= MODE_INT
2204 || !TRULY_NOOP_TRUNCATION_MODES_P (mode
, wider_mode
))
2207 target
= gen_reg_rtx (mode
);
2208 convert_move (target
, temp
, 0);
2212 return gen_lowpart (mode
, temp
);
2215 delete_insns_since (last
);
2220 delete_insns_since (entry_last
);
2224 /* Expand a binary operator which has both signed and unsigned forms.
2225 UOPTAB is the optab for unsigned operations, and SOPTAB is for
2228 If we widen unsigned operands, we may use a signed wider operation instead
2229 of an unsigned wider operation, since the result would be the same. */
2232 sign_expand_binop (machine_mode mode
, optab uoptab
, optab soptab
,
2233 rtx op0
, rtx op1
, rtx target
, int unsignedp
,
2234 enum optab_methods methods
)
2237 optab direct_optab
= unsignedp
? uoptab
: soptab
;
2240 /* Do it without widening, if possible. */
2241 temp
= expand_binop (mode
, direct_optab
, op0
, op1
, target
,
2242 unsignedp
, OPTAB_DIRECT
);
2243 if (temp
|| methods
== OPTAB_DIRECT
)
2246 /* Try widening to a signed int. Disable any direct use of any
2247 signed insn in the current mode. */
2248 save_enable
= swap_optab_enable (soptab
, mode
, false);
2250 temp
= expand_binop (mode
, soptab
, op0
, op1
, target
,
2251 unsignedp
, OPTAB_WIDEN
);
2253 /* For unsigned operands, try widening to an unsigned int. */
2254 if (!temp
&& unsignedp
)
2255 temp
= expand_binop (mode
, uoptab
, op0
, op1
, target
,
2256 unsignedp
, OPTAB_WIDEN
);
2257 if (temp
|| methods
== OPTAB_WIDEN
)
2260 /* Use the right width libcall if that exists. */
2261 temp
= expand_binop (mode
, direct_optab
, op0
, op1
, target
,
2262 unsignedp
, OPTAB_LIB
);
2263 if (temp
|| methods
== OPTAB_LIB
)
2266 /* Must widen and use a libcall, use either signed or unsigned. */
2267 temp
= expand_binop (mode
, soptab
, op0
, op1
, target
,
2268 unsignedp
, methods
);
2269 if (!temp
&& unsignedp
)
2270 temp
= expand_binop (mode
, uoptab
, op0
, op1
, target
,
2271 unsignedp
, methods
);
2274 /* Undo the fiddling above. */
2276 swap_optab_enable (soptab
, mode
, true);
2280 /* Generate code to perform an operation specified by UNOPPTAB
2281 on operand OP0, with two results to TARG0 and TARG1.
2282 We assume that the order of the operands for the instruction
2283 is TARG0, TARG1, OP0.
2285 Either TARG0 or TARG1 may be zero, but what that means is that
2286 the result is not actually wanted. We will generate it into
2287 a dummy pseudo-reg and discard it. They may not both be zero.
2289 Returns 1 if this operation can be performed; 0 if not. */
2292 expand_twoval_unop (optab unoptab
, rtx op0
, rtx targ0
, rtx targ1
,
2295 machine_mode mode
= GET_MODE (targ0
? targ0
: targ1
);
2296 enum mode_class mclass
;
2297 machine_mode wider_mode
;
2298 rtx_insn
*entry_last
= get_last_insn ();
2301 mclass
= GET_MODE_CLASS (mode
);
2304 targ0
= gen_reg_rtx (mode
);
2306 targ1
= gen_reg_rtx (mode
);
2308 /* Record where to go back to if we fail. */
2309 last
= get_last_insn ();
2311 if (optab_handler (unoptab
, mode
) != CODE_FOR_nothing
)
2313 struct expand_operand ops
[3];
2314 enum insn_code icode
= optab_handler (unoptab
, mode
);
2316 create_fixed_operand (&ops
[0], targ0
);
2317 create_fixed_operand (&ops
[1], targ1
);
2318 create_convert_operand_from (&ops
[2], op0
, mode
, unsignedp
);
2319 if (maybe_expand_insn (icode
, 3, ops
))
2323 /* It can't be done in this mode. Can we do it in a wider mode? */
2325 if (CLASS_HAS_WIDER_MODES_P (mclass
))
2327 for (wider_mode
= GET_MODE_WIDER_MODE (mode
);
2328 wider_mode
!= VOIDmode
;
2329 wider_mode
= GET_MODE_WIDER_MODE (wider_mode
))
2331 if (optab_handler (unoptab
, wider_mode
) != CODE_FOR_nothing
)
2333 rtx t0
= gen_reg_rtx (wider_mode
);
2334 rtx t1
= gen_reg_rtx (wider_mode
);
2335 rtx cop0
= convert_modes (wider_mode
, mode
, op0
, unsignedp
);
2337 if (expand_twoval_unop (unoptab
, cop0
, t0
, t1
, unsignedp
))
2339 convert_move (targ0
, t0
, unsignedp
);
2340 convert_move (targ1
, t1
, unsignedp
);
2344 delete_insns_since (last
);
2349 delete_insns_since (entry_last
);
2353 /* Generate code to perform an operation specified by BINOPTAB
2354 on operands OP0 and OP1, with two results to TARG1 and TARG2.
2355 We assume that the order of the operands for the instruction
2356 is TARG0, OP0, OP1, TARG1, which would fit a pattern like
2357 [(set TARG0 (operate OP0 OP1)) (set TARG1 (operate ...))].
2359 Either TARG0 or TARG1 may be zero, but what that means is that
2360 the result is not actually wanted. We will generate it into
2361 a dummy pseudo-reg and discard it. They may not both be zero.
2363 Returns 1 if this operation can be performed; 0 if not. */
2366 expand_twoval_binop (optab binoptab
, rtx op0
, rtx op1
, rtx targ0
, rtx targ1
,
2369 machine_mode mode
= GET_MODE (targ0
? targ0
: targ1
);
2370 enum mode_class mclass
;
2371 machine_mode wider_mode
;
2372 rtx_insn
*entry_last
= get_last_insn ();
2375 mclass
= GET_MODE_CLASS (mode
);
2378 targ0
= gen_reg_rtx (mode
);
2380 targ1
= gen_reg_rtx (mode
);
2382 /* Record where to go back to if we fail. */
2383 last
= get_last_insn ();
2385 if (optab_handler (binoptab
, mode
) != CODE_FOR_nothing
)
2387 struct expand_operand ops
[4];
2388 enum insn_code icode
= optab_handler (binoptab
, mode
);
2389 machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
2390 machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
2391 rtx xop0
= op0
, xop1
= op1
;
2393 /* If we are optimizing, force expensive constants into a register. */
2394 xop0
= avoid_expensive_constant (mode0
, binoptab
, 0, xop0
, unsignedp
);
2395 xop1
= avoid_expensive_constant (mode1
, binoptab
, 1, xop1
, unsignedp
);
2397 create_fixed_operand (&ops
[0], targ0
);
2398 create_convert_operand_from (&ops
[1], op0
, mode
, unsignedp
);
2399 create_convert_operand_from (&ops
[2], op1
, mode
, unsignedp
);
2400 create_fixed_operand (&ops
[3], targ1
);
2401 if (maybe_expand_insn (icode
, 4, ops
))
2403 delete_insns_since (last
);
2406 /* It can't be done in this mode. Can we do it in a wider mode? */
2408 if (CLASS_HAS_WIDER_MODES_P (mclass
))
2410 for (wider_mode
= GET_MODE_WIDER_MODE (mode
);
2411 wider_mode
!= VOIDmode
;
2412 wider_mode
= GET_MODE_WIDER_MODE (wider_mode
))
2414 if (optab_handler (binoptab
, wider_mode
) != CODE_FOR_nothing
)
2416 rtx t0
= gen_reg_rtx (wider_mode
);
2417 rtx t1
= gen_reg_rtx (wider_mode
);
2418 rtx cop0
= convert_modes (wider_mode
, mode
, op0
, unsignedp
);
2419 rtx cop1
= convert_modes (wider_mode
, mode
, op1
, unsignedp
);
2421 if (expand_twoval_binop (binoptab
, cop0
, cop1
,
2424 convert_move (targ0
, t0
, unsignedp
);
2425 convert_move (targ1
, t1
, unsignedp
);
2429 delete_insns_since (last
);
2434 delete_insns_since (entry_last
);
2438 /* Expand the two-valued library call indicated by BINOPTAB, but
2439 preserve only one of the values. If TARG0 is non-NULL, the first
2440 value is placed into TARG0; otherwise the second value is placed
2441 into TARG1. Exactly one of TARG0 and TARG1 must be non-NULL. The
2442 value stored into TARG0 or TARG1 is equivalent to (CODE OP0 OP1).
2443 This routine assumes that the value returned by the library call is
2444 as if the return value was of an integral mode twice as wide as the
2445 mode of OP0. Returns 1 if the call was successful. */
2448 expand_twoval_binop_libfunc (optab binoptab
, rtx op0
, rtx op1
,
2449 rtx targ0
, rtx targ1
, enum rtx_code code
)
2452 machine_mode libval_mode
;
2457 /* Exactly one of TARG0 or TARG1 should be non-NULL. */
2458 gcc_assert (!targ0
!= !targ1
);
2460 mode
= GET_MODE (op0
);
2461 libfunc
= optab_libfunc (binoptab
, mode
);
2465 /* The value returned by the library function will have twice as
2466 many bits as the nominal MODE. */
2467 libval_mode
= smallest_mode_for_size (2 * GET_MODE_BITSIZE (mode
),
2470 libval
= emit_library_call_value (libfunc
, NULL_RTX
, LCT_CONST
,
2474 /* Get the part of VAL containing the value that we want. */
2475 libval
= simplify_gen_subreg (mode
, libval
, libval_mode
,
2476 targ0
? 0 : GET_MODE_SIZE (mode
));
2477 insns
= get_insns ();
2479 /* Move the into the desired location. */
2480 emit_libcall_block (insns
, targ0
? targ0
: targ1
, libval
,
2481 gen_rtx_fmt_ee (code
, mode
, op0
, op1
));
2487 /* Wrapper around expand_unop which takes an rtx code to specify
2488 the operation to perform, not an optab pointer. All other
2489 arguments are the same. */
2491 expand_simple_unop (machine_mode mode
, enum rtx_code code
, rtx op0
,
2492 rtx target
, int unsignedp
)
2494 optab unop
= code_to_optab (code
);
2497 return expand_unop (mode
, unop
, op0
, target
, unsignedp
);
2503 (clz:wide (zero_extend:wide x)) - ((width wide) - (width narrow)).
2505 A similar operation can be used for clrsb. UNOPTAB says which operation
2506 we are trying to expand. */
2508 widen_leading (machine_mode mode
, rtx op0
, rtx target
, optab unoptab
)
2510 enum mode_class mclass
= GET_MODE_CLASS (mode
);
2511 if (CLASS_HAS_WIDER_MODES_P (mclass
))
2513 machine_mode wider_mode
;
2514 for (wider_mode
= GET_MODE_WIDER_MODE (mode
);
2515 wider_mode
!= VOIDmode
;
2516 wider_mode
= GET_MODE_WIDER_MODE (wider_mode
))
2518 if (optab_handler (unoptab
, wider_mode
) != CODE_FOR_nothing
)
2523 last
= get_last_insn ();
2526 target
= gen_reg_rtx (mode
);
2527 xop0
= widen_operand (op0
, wider_mode
, mode
,
2528 unoptab
!= clrsb_optab
, false);
2529 temp
= expand_unop (wider_mode
, unoptab
, xop0
, NULL_RTX
,
2530 unoptab
!= clrsb_optab
);
2533 (wider_mode
, sub_optab
, temp
,
2534 gen_int_mode (GET_MODE_PRECISION (wider_mode
)
2535 - GET_MODE_PRECISION (mode
),
2537 target
, true, OPTAB_DIRECT
);
2539 delete_insns_since (last
);
2548 /* Try calculating clz of a double-word quantity as two clz's of word-sized
2549 quantities, choosing which based on whether the high word is nonzero. */
2551 expand_doubleword_clz (machine_mode mode
, rtx op0
, rtx target
)
2553 rtx xop0
= force_reg (mode
, op0
);
2554 rtx subhi
= gen_highpart (word_mode
, xop0
);
2555 rtx sublo
= gen_lowpart (word_mode
, xop0
);
2556 rtx_code_label
*hi0_label
= gen_label_rtx ();
2557 rtx_code_label
*after_label
= gen_label_rtx ();
2561 /* If we were not given a target, use a word_mode register, not a
2562 'mode' register. The result will fit, and nobody is expecting
2563 anything bigger (the return type of __builtin_clz* is int). */
2565 target
= gen_reg_rtx (word_mode
);
2567 /* In any case, write to a word_mode scratch in both branches of the
2568 conditional, so we can ensure there is a single move insn setting
2569 'target' to tag a REG_EQUAL note on. */
2570 result
= gen_reg_rtx (word_mode
);
2574 /* If the high word is not equal to zero,
2575 then clz of the full value is clz of the high word. */
2576 emit_cmp_and_jump_insns (subhi
, CONST0_RTX (word_mode
), EQ
, 0,
2577 word_mode
, true, hi0_label
);
2579 temp
= expand_unop_direct (word_mode
, clz_optab
, subhi
, result
, true);
2584 convert_move (result
, temp
, true);
2586 emit_jump_insn (targetm
.gen_jump (after_label
));
2589 /* Else clz of the full value is clz of the low word plus the number
2590 of bits in the high word. */
2591 emit_label (hi0_label
);
2593 temp
= expand_unop_direct (word_mode
, clz_optab
, sublo
, 0, true);
2596 temp
= expand_binop (word_mode
, add_optab
, temp
,
2597 gen_int_mode (GET_MODE_BITSIZE (word_mode
), word_mode
),
2598 result
, true, OPTAB_DIRECT
);
2602 convert_move (result
, temp
, true);
2604 emit_label (after_label
);
2605 convert_move (target
, result
, true);
2610 add_equal_note (seq
, target
, CLZ
, xop0
, 0);
2622 (lshiftrt:wide (bswap:wide x) ((width wide) - (width narrow))). */
2624 widen_bswap (machine_mode mode
, rtx op0
, rtx target
)
2626 enum mode_class mclass
= GET_MODE_CLASS (mode
);
2627 machine_mode wider_mode
;
2631 if (!CLASS_HAS_WIDER_MODES_P (mclass
))
2634 for (wider_mode
= GET_MODE_WIDER_MODE (mode
);
2635 wider_mode
!= VOIDmode
;
2636 wider_mode
= GET_MODE_WIDER_MODE (wider_mode
))
2637 if (optab_handler (bswap_optab
, wider_mode
) != CODE_FOR_nothing
)
2642 last
= get_last_insn ();
2644 x
= widen_operand (op0
, wider_mode
, mode
, true, true);
2645 x
= expand_unop (wider_mode
, bswap_optab
, x
, NULL_RTX
, true);
2647 gcc_assert (GET_MODE_PRECISION (wider_mode
) == GET_MODE_BITSIZE (wider_mode
)
2648 && GET_MODE_PRECISION (mode
) == GET_MODE_BITSIZE (mode
));
2650 x
= expand_shift (RSHIFT_EXPR
, wider_mode
, x
,
2651 GET_MODE_BITSIZE (wider_mode
)
2652 - GET_MODE_BITSIZE (mode
),
2658 target
= gen_reg_rtx (mode
);
2659 emit_move_insn (target
, gen_lowpart (mode
, x
));
2662 delete_insns_since (last
);
2667 /* Try calculating bswap as two bswaps of two word-sized operands. */
2670 expand_doubleword_bswap (machine_mode mode
, rtx op
, rtx target
)
2674 t1
= expand_unop (word_mode
, bswap_optab
,
2675 operand_subword_force (op
, 0, mode
), NULL_RTX
, true);
2676 t0
= expand_unop (word_mode
, bswap_optab
,
2677 operand_subword_force (op
, 1, mode
), NULL_RTX
, true);
2679 if (target
== 0 || !valid_multiword_target_p (target
))
2680 target
= gen_reg_rtx (mode
);
2682 emit_clobber (target
);
2683 emit_move_insn (operand_subword (target
, 0, 1, mode
), t0
);
2684 emit_move_insn (operand_subword (target
, 1, 1, mode
), t1
);
2689 /* Try calculating (parity x) as (and (popcount x) 1), where
2690 popcount can also be done in a wider mode. */
2692 expand_parity (machine_mode mode
, rtx op0
, rtx target
)
2694 enum mode_class mclass
= GET_MODE_CLASS (mode
);
2695 if (CLASS_HAS_WIDER_MODES_P (mclass
))
2697 machine_mode wider_mode
;
2698 for (wider_mode
= mode
; wider_mode
!= VOIDmode
;
2699 wider_mode
= GET_MODE_WIDER_MODE (wider_mode
))
2701 if (optab_handler (popcount_optab
, wider_mode
) != CODE_FOR_nothing
)
2706 last
= get_last_insn ();
2709 target
= gen_reg_rtx (mode
);
2710 xop0
= widen_operand (op0
, wider_mode
, mode
, true, false);
2711 temp
= expand_unop (wider_mode
, popcount_optab
, xop0
, NULL_RTX
,
2714 temp
= expand_binop (wider_mode
, and_optab
, temp
, const1_rtx
,
2715 target
, true, OPTAB_DIRECT
);
2717 delete_insns_since (last
);
2726 /* Try calculating ctz(x) as K - clz(x & -x) ,
2727 where K is GET_MODE_PRECISION(mode) - 1.
2729 Both __builtin_ctz and __builtin_clz are undefined at zero, so we
2730 don't have to worry about what the hardware does in that case. (If
2731 the clz instruction produces the usual value at 0, which is K, the
2732 result of this code sequence will be -1; expand_ffs, below, relies
2733 on this. It might be nice to have it be K instead, for consistency
2734 with the (very few) processors that provide a ctz with a defined
2735 value, but that would take one more instruction, and it would be
2736 less convenient for expand_ffs anyway. */
2739 expand_ctz (machine_mode mode
, rtx op0
, rtx target
)
2744 if (optab_handler (clz_optab
, mode
) == CODE_FOR_nothing
)
2749 temp
= expand_unop_direct (mode
, neg_optab
, op0
, NULL_RTX
, true);
2751 temp
= expand_binop (mode
, and_optab
, op0
, temp
, NULL_RTX
,
2752 true, OPTAB_DIRECT
);
2754 temp
= expand_unop_direct (mode
, clz_optab
, temp
, NULL_RTX
, true);
2756 temp
= expand_binop (mode
, sub_optab
,
2757 gen_int_mode (GET_MODE_PRECISION (mode
) - 1, mode
),
2759 true, OPTAB_DIRECT
);
2769 add_equal_note (seq
, temp
, CTZ
, op0
, 0);
2775 /* Try calculating ffs(x) using ctz(x) if we have that instruction, or
2776 else with the sequence used by expand_clz.
2778 The ffs builtin promises to return zero for a zero value and ctz/clz
2779 may have an undefined value in that case. If they do not give us a
2780 convenient value, we have to generate a test and branch. */
2782 expand_ffs (machine_mode mode
, rtx op0
, rtx target
)
2784 HOST_WIDE_INT val
= 0;
2785 bool defined_at_zero
= false;
2789 if (optab_handler (ctz_optab
, mode
) != CODE_FOR_nothing
)
2793 temp
= expand_unop_direct (mode
, ctz_optab
, op0
, 0, true);
2797 defined_at_zero
= (CTZ_DEFINED_VALUE_AT_ZERO (mode
, val
) == 2);
2799 else if (optab_handler (clz_optab
, mode
) != CODE_FOR_nothing
)
2802 temp
= expand_ctz (mode
, op0
, 0);
2806 if (CLZ_DEFINED_VALUE_AT_ZERO (mode
, val
) == 2)
2808 defined_at_zero
= true;
2809 val
= (GET_MODE_PRECISION (mode
) - 1) - val
;
2815 if (defined_at_zero
&& val
== -1)
2816 /* No correction needed at zero. */;
2819 /* We don't try to do anything clever with the situation found
2820 on some processors (eg Alpha) where ctz(0:mode) ==
2821 bitsize(mode). If someone can think of a way to send N to -1
2822 and leave alone all values in the range 0..N-1 (where N is a
2823 power of two), cheaper than this test-and-branch, please add it.
2825 The test-and-branch is done after the operation itself, in case
2826 the operation sets condition codes that can be recycled for this.
2827 (This is true on i386, for instance.) */
2829 rtx_code_label
*nonzero_label
= gen_label_rtx ();
2830 emit_cmp_and_jump_insns (op0
, CONST0_RTX (mode
), NE
, 0,
2831 mode
, true, nonzero_label
);
2833 convert_move (temp
, GEN_INT (-1), false);
2834 emit_label (nonzero_label
);
2837 /* temp now has a value in the range -1..bitsize-1. ffs is supposed
2838 to produce a value in the range 0..bitsize. */
2839 temp
= expand_binop (mode
, add_optab
, temp
, gen_int_mode (1, mode
),
2840 target
, false, OPTAB_DIRECT
);
2847 add_equal_note (seq
, temp
, FFS
, op0
, 0);
2856 /* Extract the OMODE lowpart from VAL, which has IMODE. Under certain
2857 conditions, VAL may already be a SUBREG against which we cannot generate
2858 a further SUBREG. In this case, we expect forcing the value into a
2859 register will work around the situation. */
2862 lowpart_subreg_maybe_copy (machine_mode omode
, rtx val
,
2866 ret
= lowpart_subreg (omode
, val
, imode
);
2869 val
= force_reg (imode
, val
);
2870 ret
= lowpart_subreg (omode
, val
, imode
);
2871 gcc_assert (ret
!= NULL
);
2876 /* Expand a floating point absolute value or negation operation via a
2877 logical operation on the sign bit. */
2880 expand_absneg_bit (enum rtx_code code
, machine_mode mode
,
2881 rtx op0
, rtx target
)
2883 const struct real_format
*fmt
;
2884 int bitpos
, word
, nwords
, i
;
2889 /* The format has to have a simple sign bit. */
2890 fmt
= REAL_MODE_FORMAT (mode
);
2894 bitpos
= fmt
->signbit_rw
;
2898 /* Don't create negative zeros if the format doesn't support them. */
2899 if (code
== NEG
&& !fmt
->has_signed_zero
)
2902 if (GET_MODE_SIZE (mode
) <= UNITS_PER_WORD
)
2904 imode
= int_mode_for_mode (mode
);
2905 if (imode
== BLKmode
)
2914 if (FLOAT_WORDS_BIG_ENDIAN
)
2915 word
= (GET_MODE_BITSIZE (mode
) - bitpos
) / BITS_PER_WORD
;
2917 word
= bitpos
/ BITS_PER_WORD
;
2918 bitpos
= bitpos
% BITS_PER_WORD
;
2919 nwords
= (GET_MODE_BITSIZE (mode
) + BITS_PER_WORD
- 1) / BITS_PER_WORD
;
2922 wide_int mask
= wi::set_bit_in_zero (bitpos
, GET_MODE_PRECISION (imode
));
2928 || (nwords
> 1 && !valid_multiword_target_p (target
)))
2929 target
= gen_reg_rtx (mode
);
2935 for (i
= 0; i
< nwords
; ++i
)
2937 rtx targ_piece
= operand_subword (target
, i
, 1, mode
);
2938 rtx op0_piece
= operand_subword_force (op0
, i
, mode
);
2942 temp
= expand_binop (imode
, code
== ABS
? and_optab
: xor_optab
,
2944 immed_wide_int_const (mask
, imode
),
2945 targ_piece
, 1, OPTAB_LIB_WIDEN
);
2946 if (temp
!= targ_piece
)
2947 emit_move_insn (targ_piece
, temp
);
2950 emit_move_insn (targ_piece
, op0_piece
);
2953 insns
= get_insns ();
2960 temp
= expand_binop (imode
, code
== ABS
? and_optab
: xor_optab
,
2961 gen_lowpart (imode
, op0
),
2962 immed_wide_int_const (mask
, imode
),
2963 gen_lowpart (imode
, target
), 1, OPTAB_LIB_WIDEN
);
2964 target
= lowpart_subreg_maybe_copy (mode
, temp
, imode
);
2966 set_dst_reg_note (get_last_insn (), REG_EQUAL
,
2967 gen_rtx_fmt_e (code
, mode
, copy_rtx (op0
)),
2974 /* As expand_unop, but will fail rather than attempt the operation in a
2975 different mode or with a libcall. */
2977 expand_unop_direct (machine_mode mode
, optab unoptab
, rtx op0
, rtx target
,
2980 if (optab_handler (unoptab
, mode
) != CODE_FOR_nothing
)
2982 struct expand_operand ops
[2];
2983 enum insn_code icode
= optab_handler (unoptab
, mode
);
2984 rtx_insn
*last
= get_last_insn ();
2987 create_output_operand (&ops
[0], target
, mode
);
2988 create_convert_operand_from (&ops
[1], op0
, mode
, unsignedp
);
2989 pat
= maybe_gen_insn (icode
, 2, ops
);
2992 if (INSN_P (pat
) && NEXT_INSN (pat
) != NULL_RTX
2993 && ! add_equal_note (pat
, ops
[0].value
,
2994 optab_to_code (unoptab
),
2995 ops
[1].value
, NULL_RTX
))
2997 delete_insns_since (last
);
2998 return expand_unop (mode
, unoptab
, op0
, NULL_RTX
, unsignedp
);
3003 return ops
[0].value
;
3009 /* Generate code to perform an operation specified by UNOPTAB
3010 on operand OP0, with result having machine-mode MODE.
3012 UNSIGNEDP is for the case where we have to widen the operands
3013 to perform the operation. It says to use zero-extension.
3015 If TARGET is nonzero, the value
3016 is generated there, if it is convenient to do so.
3017 In all cases an rtx is returned for the locus of the value;
3018 this may or may not be TARGET. */
3021 expand_unop (machine_mode mode
, optab unoptab
, rtx op0
, rtx target
,
3024 enum mode_class mclass
= GET_MODE_CLASS (mode
);
3025 machine_mode wider_mode
;
3029 temp
= expand_unop_direct (mode
, unoptab
, op0
, target
, unsignedp
);
3033 /* It can't be done in this mode. Can we open-code it in a wider mode? */
3035 /* Widening (or narrowing) clz needs special treatment. */
3036 if (unoptab
== clz_optab
)
3038 temp
= widen_leading (mode
, op0
, target
, unoptab
);
3042 if (GET_MODE_SIZE (mode
) == 2 * UNITS_PER_WORD
3043 && optab_handler (unoptab
, word_mode
) != CODE_FOR_nothing
)
3045 temp
= expand_doubleword_clz (mode
, op0
, target
);
3053 if (unoptab
== clrsb_optab
)
3055 temp
= widen_leading (mode
, op0
, target
, unoptab
);
3061 /* Widening (or narrowing) bswap needs special treatment. */
3062 if (unoptab
== bswap_optab
)
3064 /* HImode is special because in this mode BSWAP is equivalent to ROTATE
3065 or ROTATERT. First try these directly; if this fails, then try the
3066 obvious pair of shifts with allowed widening, as this will probably
3067 be always more efficient than the other fallback methods. */
3073 if (optab_handler (rotl_optab
, mode
) != CODE_FOR_nothing
)
3075 temp
= expand_binop (mode
, rotl_optab
, op0
, GEN_INT (8), target
,
3076 unsignedp
, OPTAB_DIRECT
);
3081 if (optab_handler (rotr_optab
, mode
) != CODE_FOR_nothing
)
3083 temp
= expand_binop (mode
, rotr_optab
, op0
, GEN_INT (8), target
,
3084 unsignedp
, OPTAB_DIRECT
);
3089 last
= get_last_insn ();
3091 temp1
= expand_binop (mode
, ashl_optab
, op0
, GEN_INT (8), NULL_RTX
,
3092 unsignedp
, OPTAB_WIDEN
);
3093 temp2
= expand_binop (mode
, lshr_optab
, op0
, GEN_INT (8), NULL_RTX
,
3094 unsignedp
, OPTAB_WIDEN
);
3097 temp
= expand_binop (mode
, ior_optab
, temp1
, temp2
, target
,
3098 unsignedp
, OPTAB_WIDEN
);
3103 delete_insns_since (last
);
3106 temp
= widen_bswap (mode
, op0
, target
);
3110 if (GET_MODE_SIZE (mode
) == 2 * UNITS_PER_WORD
3111 && optab_handler (unoptab
, word_mode
) != CODE_FOR_nothing
)
3113 temp
= expand_doubleword_bswap (mode
, op0
, target
);
3121 if (CLASS_HAS_WIDER_MODES_P (mclass
))
3122 for (wider_mode
= GET_MODE_WIDER_MODE (mode
);
3123 wider_mode
!= VOIDmode
;
3124 wider_mode
= GET_MODE_WIDER_MODE (wider_mode
))
3126 if (optab_handler (unoptab
, wider_mode
) != CODE_FOR_nothing
)
3129 rtx_insn
*last
= get_last_insn ();
3131 /* For certain operations, we need not actually extend
3132 the narrow operand, as long as we will truncate the
3133 results to the same narrowness. */
3135 xop0
= widen_operand (xop0
, wider_mode
, mode
, unsignedp
,
3136 (unoptab
== neg_optab
3137 || unoptab
== one_cmpl_optab
)
3138 && mclass
== MODE_INT
);
3140 temp
= expand_unop (wider_mode
, unoptab
, xop0
, NULL_RTX
,
3145 if (mclass
!= MODE_INT
3146 || !TRULY_NOOP_TRUNCATION_MODES_P (mode
, wider_mode
))
3149 target
= gen_reg_rtx (mode
);
3150 convert_move (target
, temp
, 0);
3154 return gen_lowpart (mode
, temp
);
3157 delete_insns_since (last
);
3161 /* These can be done a word at a time. */
3162 if (unoptab
== one_cmpl_optab
3163 && mclass
== MODE_INT
3164 && GET_MODE_SIZE (mode
) > UNITS_PER_WORD
3165 && optab_handler (unoptab
, word_mode
) != CODE_FOR_nothing
)
3170 if (target
== 0 || target
== op0
|| !valid_multiword_target_p (target
))
3171 target
= gen_reg_rtx (mode
);
3175 /* Do the actual arithmetic. */
3176 for (i
= 0; i
< GET_MODE_BITSIZE (mode
) / BITS_PER_WORD
; i
++)
3178 rtx target_piece
= operand_subword (target
, i
, 1, mode
);
3179 rtx x
= expand_unop (word_mode
, unoptab
,
3180 operand_subword_force (op0
, i
, mode
),
3181 target_piece
, unsignedp
);
3183 if (target_piece
!= x
)
3184 emit_move_insn (target_piece
, x
);
3187 insns
= get_insns ();
3194 if (optab_to_code (unoptab
) == NEG
)
3196 /* Try negating floating point values by flipping the sign bit. */
3197 if (SCALAR_FLOAT_MODE_P (mode
))
3199 temp
= expand_absneg_bit (NEG
, mode
, op0
, target
);
3204 /* If there is no negation pattern, and we have no negative zero,
3205 try subtracting from zero. */
3206 if (!HONOR_SIGNED_ZEROS (mode
))
3208 temp
= expand_binop (mode
, (unoptab
== negv_optab
3209 ? subv_optab
: sub_optab
),
3210 CONST0_RTX (mode
), op0
, target
,
3211 unsignedp
, OPTAB_DIRECT
);
3217 /* Try calculating parity (x) as popcount (x) % 2. */
3218 if (unoptab
== parity_optab
)
3220 temp
= expand_parity (mode
, op0
, target
);
3225 /* Try implementing ffs (x) in terms of clz (x). */
3226 if (unoptab
== ffs_optab
)
3228 temp
= expand_ffs (mode
, op0
, target
);
3233 /* Try implementing ctz (x) in terms of clz (x). */
3234 if (unoptab
== ctz_optab
)
3236 temp
= expand_ctz (mode
, op0
, target
);
3242 /* Now try a library call in this mode. */
3243 libfunc
= optab_libfunc (unoptab
, mode
);
3249 machine_mode outmode
= mode
;
3251 /* All of these functions return small values. Thus we choose to
3252 have them return something that isn't a double-word. */
3253 if (unoptab
== ffs_optab
|| unoptab
== clz_optab
|| unoptab
== ctz_optab
3254 || unoptab
== clrsb_optab
|| unoptab
== popcount_optab
3255 || unoptab
== parity_optab
)
3257 = GET_MODE (hard_libcall_value (TYPE_MODE (integer_type_node
),
3258 optab_libfunc (unoptab
, mode
)));
3262 /* Pass 1 for NO_QUEUE so we don't lose any increments
3263 if the libcall is cse'd or moved. */
3264 value
= emit_library_call_value (libfunc
, NULL_RTX
, LCT_CONST
, outmode
,
3266 insns
= get_insns ();
3269 target
= gen_reg_rtx (outmode
);
3270 eq_value
= gen_rtx_fmt_e (optab_to_code (unoptab
), mode
, op0
);
3271 if (GET_MODE_SIZE (outmode
) < GET_MODE_SIZE (mode
))
3272 eq_value
= simplify_gen_unary (TRUNCATE
, outmode
, eq_value
, mode
);
3273 else if (GET_MODE_SIZE (outmode
) > GET_MODE_SIZE (mode
))
3274 eq_value
= simplify_gen_unary (ZERO_EXTEND
, outmode
, eq_value
, mode
);
3275 emit_libcall_block_1 (insns
, target
, value
, eq_value
,
3276 trapv_unoptab_p (unoptab
));
3281 /* It can't be done in this mode. Can we do it in a wider mode? */
3283 if (CLASS_HAS_WIDER_MODES_P (mclass
))
3285 for (wider_mode
= GET_MODE_WIDER_MODE (mode
);
3286 wider_mode
!= VOIDmode
;
3287 wider_mode
= GET_MODE_WIDER_MODE (wider_mode
))
3289 if (optab_handler (unoptab
, wider_mode
) != CODE_FOR_nothing
3290 || optab_libfunc (unoptab
, wider_mode
))
3293 rtx_insn
*last
= get_last_insn ();
3295 /* For certain operations, we need not actually extend
3296 the narrow operand, as long as we will truncate the
3297 results to the same narrowness. */
3298 xop0
= widen_operand (xop0
, wider_mode
, mode
, unsignedp
,
3299 (unoptab
== neg_optab
3300 || unoptab
== one_cmpl_optab
3301 || unoptab
== bswap_optab
)
3302 && mclass
== MODE_INT
);
3304 temp
= expand_unop (wider_mode
, unoptab
, xop0
, NULL_RTX
,
3307 /* If we are generating clz using wider mode, adjust the
3308 result. Similarly for clrsb. */
3309 if ((unoptab
== clz_optab
|| unoptab
== clrsb_optab
)
3312 (wider_mode
, sub_optab
, temp
,
3313 gen_int_mode (GET_MODE_PRECISION (wider_mode
)
3314 - GET_MODE_PRECISION (mode
),
3316 target
, true, OPTAB_DIRECT
);
3318 /* Likewise for bswap. */
3319 if (unoptab
== bswap_optab
&& temp
!= 0)
3321 gcc_assert (GET_MODE_PRECISION (wider_mode
)
3322 == GET_MODE_BITSIZE (wider_mode
)
3323 && GET_MODE_PRECISION (mode
)
3324 == GET_MODE_BITSIZE (mode
));
3326 temp
= expand_shift (RSHIFT_EXPR
, wider_mode
, temp
,
3327 GET_MODE_BITSIZE (wider_mode
)
3328 - GET_MODE_BITSIZE (mode
),
3334 if (mclass
!= MODE_INT
)
3337 target
= gen_reg_rtx (mode
);
3338 convert_move (target
, temp
, 0);
3342 return gen_lowpart (mode
, temp
);
3345 delete_insns_since (last
);
3350 /* One final attempt at implementing negation via subtraction,
3351 this time allowing widening of the operand. */
3352 if (optab_to_code (unoptab
) == NEG
&& !HONOR_SIGNED_ZEROS (mode
))
3355 temp
= expand_binop (mode
,
3356 unoptab
== negv_optab
? subv_optab
: sub_optab
,
3357 CONST0_RTX (mode
), op0
,
3358 target
, unsignedp
, OPTAB_LIB_WIDEN
);
3366 /* Emit code to compute the absolute value of OP0, with result to
3367 TARGET if convenient. (TARGET may be 0.) The return value says
3368 where the result actually is to be found.
3370 MODE is the mode of the operand; the mode of the result is
3371 different but can be deduced from MODE.
3376 expand_abs_nojump (machine_mode mode
, rtx op0
, rtx target
,
3377 int result_unsignedp
)
3381 if (GET_MODE_CLASS (mode
) != MODE_INT
3383 result_unsignedp
= 1;
3385 /* First try to do it with a special abs instruction. */
3386 temp
= expand_unop (mode
, result_unsignedp
? abs_optab
: absv_optab
,
3391 /* For floating point modes, try clearing the sign bit. */
3392 if (SCALAR_FLOAT_MODE_P (mode
))
3394 temp
= expand_absneg_bit (ABS
, mode
, op0
, target
);
3399 /* If we have a MAX insn, we can do this as MAX (x, -x). */
3400 if (optab_handler (smax_optab
, mode
) != CODE_FOR_nothing
3401 && !HONOR_SIGNED_ZEROS (mode
))
3403 rtx_insn
*last
= get_last_insn ();
3405 temp
= expand_unop (mode
, result_unsignedp
? neg_optab
: negv_optab
,
3408 temp
= expand_binop (mode
, smax_optab
, op0
, temp
, target
, 0,
3414 delete_insns_since (last
);
3417 /* If this machine has expensive jumps, we can do integer absolute
3418 value of X as (((signed) x >> (W-1)) ^ x) - ((signed) x >> (W-1)),
3419 where W is the width of MODE. */
3421 if (GET_MODE_CLASS (mode
) == MODE_INT
3422 && BRANCH_COST (optimize_insn_for_speed_p (),
3425 rtx extended
= expand_shift (RSHIFT_EXPR
, mode
, op0
,
3426 GET_MODE_PRECISION (mode
) - 1,
3429 temp
= expand_binop (mode
, xor_optab
, extended
, op0
, target
, 0,
3432 temp
= expand_binop (mode
, result_unsignedp
? sub_optab
: subv_optab
,
3433 temp
, extended
, target
, 0, OPTAB_LIB_WIDEN
);
3443 expand_abs (machine_mode mode
, rtx op0
, rtx target
,
3444 int result_unsignedp
, int safe
)
3447 rtx_code_label
*op1
;
3449 if (GET_MODE_CLASS (mode
) != MODE_INT
3451 result_unsignedp
= 1;
3453 temp
= expand_abs_nojump (mode
, op0
, target
, result_unsignedp
);
3457 /* If that does not win, use conditional jump and negate. */
3459 /* It is safe to use the target if it is the same
3460 as the source if this is also a pseudo register */
3461 if (op0
== target
&& REG_P (op0
)
3462 && REGNO (op0
) >= FIRST_PSEUDO_REGISTER
)
3465 op1
= gen_label_rtx ();
3466 if (target
== 0 || ! safe
3467 || GET_MODE (target
) != mode
3468 || (MEM_P (target
) && MEM_VOLATILE_P (target
))
3470 && REGNO (target
) < FIRST_PSEUDO_REGISTER
))
3471 target
= gen_reg_rtx (mode
);
3473 emit_move_insn (target
, op0
);
3476 do_compare_rtx_and_jump (target
, CONST0_RTX (mode
), GE
, 0, mode
,
3477 NULL_RTX
, NULL
, op1
, -1);
3479 op0
= expand_unop (mode
, result_unsignedp
? neg_optab
: negv_optab
,
3482 emit_move_insn (target
, op0
);
3488 /* Emit code to compute the one's complement absolute value of OP0
3489 (if (OP0 < 0) OP0 = ~OP0), with result to TARGET if convenient.
3490 (TARGET may be NULL_RTX.) The return value says where the result
3491 actually is to be found.
3493 MODE is the mode of the operand; the mode of the result is
3494 different but can be deduced from MODE. */
3497 expand_one_cmpl_abs_nojump (machine_mode mode
, rtx op0
, rtx target
)
3501 /* Not applicable for floating point modes. */
3502 if (FLOAT_MODE_P (mode
))
3505 /* If we have a MAX insn, we can do this as MAX (x, ~x). */
3506 if (optab_handler (smax_optab
, mode
) != CODE_FOR_nothing
)
3508 rtx_insn
*last
= get_last_insn ();
3510 temp
= expand_unop (mode
, one_cmpl_optab
, op0
, NULL_RTX
, 0);
3512 temp
= expand_binop (mode
, smax_optab
, op0
, temp
, target
, 0,
3518 delete_insns_since (last
);
3521 /* If this machine has expensive jumps, we can do one's complement
3522 absolute value of X as (((signed) x >> (W-1)) ^ x). */
3524 if (GET_MODE_CLASS (mode
) == MODE_INT
3525 && BRANCH_COST (optimize_insn_for_speed_p (),
3528 rtx extended
= expand_shift (RSHIFT_EXPR
, mode
, op0
,
3529 GET_MODE_PRECISION (mode
) - 1,
3532 temp
= expand_binop (mode
, xor_optab
, extended
, op0
, target
, 0,
3542 /* A subroutine of expand_copysign, perform the copysign operation using the
3543 abs and neg primitives advertised to exist on the target. The assumption
3544 is that we have a split register file, and leaving op0 in fp registers,
3545 and not playing with subregs so much, will help the register allocator. */
3548 expand_copysign_absneg (machine_mode mode
, rtx op0
, rtx op1
, rtx target
,
3549 int bitpos
, bool op0_is_abs
)
3552 enum insn_code icode
;
3554 rtx_code_label
*label
;
3559 /* Check if the back end provides an insn that handles signbit for the
3561 icode
= optab_handler (signbit_optab
, mode
);
3562 if (icode
!= CODE_FOR_nothing
)
3564 imode
= insn_data
[(int) icode
].operand
[0].mode
;
3565 sign
= gen_reg_rtx (imode
);
3566 emit_unop_insn (icode
, sign
, op1
, UNKNOWN
);
3570 if (GET_MODE_SIZE (mode
) <= UNITS_PER_WORD
)
3572 imode
= int_mode_for_mode (mode
);
3573 if (imode
== BLKmode
)
3575 op1
= gen_lowpart (imode
, op1
);
3582 if (FLOAT_WORDS_BIG_ENDIAN
)
3583 word
= (GET_MODE_BITSIZE (mode
) - bitpos
) / BITS_PER_WORD
;
3585 word
= bitpos
/ BITS_PER_WORD
;
3586 bitpos
= bitpos
% BITS_PER_WORD
;
3587 op1
= operand_subword_force (op1
, word
, mode
);
3590 wide_int mask
= wi::set_bit_in_zero (bitpos
, GET_MODE_PRECISION (imode
));
3591 sign
= expand_binop (imode
, and_optab
, op1
,
3592 immed_wide_int_const (mask
, imode
),
3593 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
3598 op0
= expand_unop (mode
, abs_optab
, op0
, target
, 0);
3605 if (target
== NULL_RTX
)
3606 target
= copy_to_reg (op0
);
3608 emit_move_insn (target
, op0
);
3611 label
= gen_label_rtx ();
3612 emit_cmp_and_jump_insns (sign
, const0_rtx
, EQ
, NULL_RTX
, imode
, 1, label
);
3614 if (CONST_DOUBLE_AS_FLOAT_P (op0
))
3615 op0
= simplify_unary_operation (NEG
, mode
, op0
, mode
);
3617 op0
= expand_unop (mode
, neg_optab
, op0
, target
, 0);
3619 emit_move_insn (target
, op0
);
3627 /* A subroutine of expand_copysign, perform the entire copysign operation
3628 with integer bitmasks. BITPOS is the position of the sign bit; OP0_IS_ABS
3629 is true if op0 is known to have its sign bit clear. */
3632 expand_copysign_bit (machine_mode mode
, rtx op0
, rtx op1
, rtx target
,
3633 int bitpos
, bool op0_is_abs
)
3636 int word
, nwords
, i
;
3640 if (GET_MODE_SIZE (mode
) <= UNITS_PER_WORD
)
3642 imode
= int_mode_for_mode (mode
);
3643 if (imode
== BLKmode
)
3652 if (FLOAT_WORDS_BIG_ENDIAN
)
3653 word
= (GET_MODE_BITSIZE (mode
) - bitpos
) / BITS_PER_WORD
;
3655 word
= bitpos
/ BITS_PER_WORD
;
3656 bitpos
= bitpos
% BITS_PER_WORD
;
3657 nwords
= (GET_MODE_BITSIZE (mode
) + BITS_PER_WORD
- 1) / BITS_PER_WORD
;
3660 wide_int mask
= wi::set_bit_in_zero (bitpos
, GET_MODE_PRECISION (imode
));
3665 || (nwords
> 1 && !valid_multiword_target_p (target
)))
3666 target
= gen_reg_rtx (mode
);
3672 for (i
= 0; i
< nwords
; ++i
)
3674 rtx targ_piece
= operand_subword (target
, i
, 1, mode
);
3675 rtx op0_piece
= operand_subword_force (op0
, i
, mode
);
3681 = expand_binop (imode
, and_optab
, op0_piece
,
3682 immed_wide_int_const (~mask
, imode
),
3683 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
3684 op1
= expand_binop (imode
, and_optab
,
3685 operand_subword_force (op1
, i
, mode
),
3686 immed_wide_int_const (mask
, imode
),
3687 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
3689 temp
= expand_binop (imode
, ior_optab
, op0_piece
, op1
,
3690 targ_piece
, 1, OPTAB_LIB_WIDEN
);
3691 if (temp
!= targ_piece
)
3692 emit_move_insn (targ_piece
, temp
);
3695 emit_move_insn (targ_piece
, op0_piece
);
3698 insns
= get_insns ();
3705 op1
= expand_binop (imode
, and_optab
, gen_lowpart (imode
, op1
),
3706 immed_wide_int_const (mask
, imode
),
3707 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
3709 op0
= gen_lowpart (imode
, op0
);
3711 op0
= expand_binop (imode
, and_optab
, op0
,
3712 immed_wide_int_const (~mask
, imode
),
3713 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
3715 temp
= expand_binop (imode
, ior_optab
, op0
, op1
,
3716 gen_lowpart (imode
, target
), 1, OPTAB_LIB_WIDEN
);
3717 target
= lowpart_subreg_maybe_copy (mode
, temp
, imode
);
3723 /* Expand the C99 copysign operation. OP0 and OP1 must be the same
3724 scalar floating point mode. Return NULL if we do not know how to
3725 expand the operation inline. */
3728 expand_copysign (rtx op0
, rtx op1
, rtx target
)
3730 machine_mode mode
= GET_MODE (op0
);
3731 const struct real_format
*fmt
;
3735 gcc_assert (SCALAR_FLOAT_MODE_P (mode
));
3736 gcc_assert (GET_MODE (op1
) == mode
);
3738 /* First try to do it with a special instruction. */
3739 temp
= expand_binop (mode
, copysign_optab
, op0
, op1
,
3740 target
, 0, OPTAB_DIRECT
);
3744 fmt
= REAL_MODE_FORMAT (mode
);
3745 if (fmt
== NULL
|| !fmt
->has_signed_zero
)
3749 if (CONST_DOUBLE_AS_FLOAT_P (op0
))
3751 if (real_isneg (CONST_DOUBLE_REAL_VALUE (op0
)))
3752 op0
= simplify_unary_operation (ABS
, mode
, op0
, mode
);
3756 if (fmt
->signbit_ro
>= 0
3757 && (CONST_DOUBLE_AS_FLOAT_P (op0
)
3758 || (optab_handler (neg_optab
, mode
) != CODE_FOR_nothing
3759 && optab_handler (abs_optab
, mode
) != CODE_FOR_nothing
)))
3761 temp
= expand_copysign_absneg (mode
, op0
, op1
, target
,
3762 fmt
->signbit_ro
, op0_is_abs
);
3767 if (fmt
->signbit_rw
< 0)
3769 return expand_copysign_bit (mode
, op0
, op1
, target
,
3770 fmt
->signbit_rw
, op0_is_abs
);
3773 /* Generate an instruction whose insn-code is INSN_CODE,
3774 with two operands: an output TARGET and an input OP0.
3775 TARGET *must* be nonzero, and the output is always stored there.
3776 CODE is an rtx code such that (CODE OP0) is an rtx that describes
3777 the value that is stored into TARGET.
3779 Return false if expansion failed. */
3782 maybe_emit_unop_insn (enum insn_code icode
, rtx target
, rtx op0
,
3785 struct expand_operand ops
[2];
3788 create_output_operand (&ops
[0], target
, GET_MODE (target
));
3789 create_input_operand (&ops
[1], op0
, GET_MODE (op0
));
3790 pat
= maybe_gen_insn (icode
, 2, ops
);
3794 if (INSN_P (pat
) && NEXT_INSN (pat
) != NULL_RTX
3796 add_equal_note (pat
, ops
[0].value
, code
, ops
[1].value
, NULL_RTX
);
3800 if (ops
[0].value
!= target
)
3801 emit_move_insn (target
, ops
[0].value
);
3804 /* Generate an instruction whose insn-code is INSN_CODE,
3805 with two operands: an output TARGET and an input OP0.
3806 TARGET *must* be nonzero, and the output is always stored there.
3807 CODE is an rtx code such that (CODE OP0) is an rtx that describes
3808 the value that is stored into TARGET. */
3811 emit_unop_insn (enum insn_code icode
, rtx target
, rtx op0
, enum rtx_code code
)
3813 bool ok
= maybe_emit_unop_insn (icode
, target
, op0
, code
);
3817 struct no_conflict_data
3820 rtx_insn
*first
, *insn
;
3824 /* Called via note_stores by emit_libcall_block. Set P->must_stay if
3825 the currently examined clobber / store has to stay in the list of
3826 insns that constitute the actual libcall block. */
3828 no_conflict_move_test (rtx dest
, const_rtx set
, void *p0
)
3830 struct no_conflict_data
*p
= (struct no_conflict_data
*) p0
;
3832 /* If this inns directly contributes to setting the target, it must stay. */
3833 if (reg_overlap_mentioned_p (p
->target
, dest
))
3834 p
->must_stay
= true;
3835 /* If we haven't committed to keeping any other insns in the list yet,
3836 there is nothing more to check. */
3837 else if (p
->insn
== p
->first
)
3839 /* If this insn sets / clobbers a register that feeds one of the insns
3840 already in the list, this insn has to stay too. */
3841 else if (reg_overlap_mentioned_p (dest
, PATTERN (p
->first
))
3842 || (CALL_P (p
->first
) && (find_reg_fusage (p
->first
, USE
, dest
)))
3843 || reg_used_between_p (dest
, p
->first
, p
->insn
)
3844 /* Likewise if this insn depends on a register set by a previous
3845 insn in the list, or if it sets a result (presumably a hard
3846 register) that is set or clobbered by a previous insn.
3847 N.B. the modified_*_p (SET_DEST...) tests applied to a MEM
3848 SET_DEST perform the former check on the address, and the latter
3849 check on the MEM. */
3850 || (GET_CODE (set
) == SET
3851 && (modified_in_p (SET_SRC (set
), p
->first
)
3852 || modified_in_p (SET_DEST (set
), p
->first
)
3853 || modified_between_p (SET_SRC (set
), p
->first
, p
->insn
)
3854 || modified_between_p (SET_DEST (set
), p
->first
, p
->insn
))))
3855 p
->must_stay
= true;
3859 /* Emit code to make a call to a constant function or a library call.
3861 INSNS is a list containing all insns emitted in the call.
3862 These insns leave the result in RESULT. Our block is to copy RESULT
3863 to TARGET, which is logically equivalent to EQUIV.
3865 We first emit any insns that set a pseudo on the assumption that these are
3866 loading constants into registers; doing so allows them to be safely cse'ed
3867 between blocks. Then we emit all the other insns in the block, followed by
3868 an insn to move RESULT to TARGET. This last insn will have a REQ_EQUAL
3869 note with an operand of EQUIV. */
3872 emit_libcall_block_1 (rtx_insn
*insns
, rtx target
, rtx result
, rtx equiv
,
3873 bool equiv_may_trap
)
3875 rtx final_dest
= target
;
3876 rtx_insn
*next
, *last
, *insn
;
3878 /* If this is a reg with REG_USERVAR_P set, then it could possibly turn
3879 into a MEM later. Protect the libcall block from this change. */
3880 if (! REG_P (target
) || REG_USERVAR_P (target
))
3881 target
= gen_reg_rtx (GET_MODE (target
));
3883 /* If we're using non-call exceptions, a libcall corresponding to an
3884 operation that may trap may also trap. */
3885 /* ??? See the comment in front of make_reg_eh_region_note. */
3886 if (cfun
->can_throw_non_call_exceptions
3887 && (equiv_may_trap
|| may_trap_p (equiv
)))
3889 for (insn
= insns
; insn
; insn
= NEXT_INSN (insn
))
3892 rtx note
= find_reg_note (insn
, REG_EH_REGION
, NULL_RTX
);
3895 int lp_nr
= INTVAL (XEXP (note
, 0));
3896 if (lp_nr
== 0 || lp_nr
== INT_MIN
)
3897 remove_note (insn
, note
);
3903 /* Look for any CALL_INSNs in this sequence, and attach a REG_EH_REGION
3904 reg note to indicate that this call cannot throw or execute a nonlocal
3905 goto (unless there is already a REG_EH_REGION note, in which case
3907 for (insn
= insns
; insn
; insn
= NEXT_INSN (insn
))
3909 make_reg_eh_region_note_nothrow_nononlocal (insn
);
3912 /* First emit all insns that set pseudos. Remove them from the list as
3913 we go. Avoid insns that set pseudos which were referenced in previous
3914 insns. These can be generated by move_by_pieces, for example,
3915 to update an address. Similarly, avoid insns that reference things
3916 set in previous insns. */
3918 for (insn
= insns
; insn
; insn
= next
)
3920 rtx set
= single_set (insn
);
3922 next
= NEXT_INSN (insn
);
3924 if (set
!= 0 && REG_P (SET_DEST (set
))
3925 && REGNO (SET_DEST (set
)) >= FIRST_PSEUDO_REGISTER
)
3927 struct no_conflict_data data
;
3929 data
.target
= const0_rtx
;
3933 note_stores (PATTERN (insn
), no_conflict_move_test
, &data
);
3934 if (! data
.must_stay
)
3936 if (PREV_INSN (insn
))
3937 SET_NEXT_INSN (PREV_INSN (insn
)) = next
;
3942 SET_PREV_INSN (next
) = PREV_INSN (insn
);
3948 /* Some ports use a loop to copy large arguments onto the stack.
3949 Don't move anything outside such a loop. */
3954 /* Write the remaining insns followed by the final copy. */
3955 for (insn
= insns
; insn
; insn
= next
)
3957 next
= NEXT_INSN (insn
);
3962 last
= emit_move_insn (target
, result
);
3963 set_dst_reg_note (last
, REG_EQUAL
, copy_rtx (equiv
), target
);
3965 if (final_dest
!= target
)
3966 emit_move_insn (final_dest
, target
);
3970 emit_libcall_block (rtx insns
, rtx target
, rtx result
, rtx equiv
)
3972 emit_libcall_block_1 (safe_as_a
<rtx_insn
*> (insns
),
3973 target
, result
, equiv
, false);
3976 /* Nonzero if we can perform a comparison of mode MODE straightforwardly.
3977 PURPOSE describes how this comparison will be used. CODE is the rtx
3978 comparison code we will be using.
3980 ??? Actually, CODE is slightly weaker than that. A target is still
3981 required to implement all of the normal bcc operations, but not
3982 required to implement all (or any) of the unordered bcc operations. */
3985 can_compare_p (enum rtx_code code
, machine_mode mode
,
3986 enum can_compare_purpose purpose
)
3989 test
= gen_rtx_fmt_ee (code
, mode
, const0_rtx
, const0_rtx
);
3992 enum insn_code icode
;
3994 if (purpose
== ccp_jump
3995 && (icode
= optab_handler (cbranch_optab
, mode
)) != CODE_FOR_nothing
3996 && insn_operand_matches (icode
, 0, test
))
3998 if (purpose
== ccp_store_flag
3999 && (icode
= optab_handler (cstore_optab
, mode
)) != CODE_FOR_nothing
4000 && insn_operand_matches (icode
, 1, test
))
4002 if (purpose
== ccp_cmov
4003 && optab_handler (cmov_optab
, mode
) != CODE_FOR_nothing
)
4006 mode
= GET_MODE_WIDER_MODE (mode
);
4007 PUT_MODE (test
, mode
);
4009 while (mode
!= VOIDmode
);
4014 /* This function is called when we are going to emit a compare instruction that
4015 compares the values found in *PX and *PY, using the rtl operator COMPARISON.
4017 *PMODE is the mode of the inputs (in case they are const_int).
4018 *PUNSIGNEDP nonzero says that the operands are unsigned;
4019 this matters if they need to be widened (as given by METHODS).
4021 If they have mode BLKmode, then SIZE specifies the size of both operands.
4023 This function performs all the setup necessary so that the caller only has
4024 to emit a single comparison insn. This setup can involve doing a BLKmode
4025 comparison or emitting a library call to perform the comparison if no insn
4026 is available to handle it.
4027 The values which are passed in through pointers can be modified; the caller
4028 should perform the comparison on the modified values. Constant
4029 comparisons must have already been folded. */
4032 prepare_cmp_insn (rtx x
, rtx y
, enum rtx_code comparison
, rtx size
,
4033 int unsignedp
, enum optab_methods methods
,
4034 rtx
*ptest
, machine_mode
*pmode
)
4036 machine_mode mode
= *pmode
;
4038 machine_mode cmp_mode
;
4039 enum mode_class mclass
;
4041 /* The other methods are not needed. */
4042 gcc_assert (methods
== OPTAB_DIRECT
|| methods
== OPTAB_WIDEN
4043 || methods
== OPTAB_LIB_WIDEN
);
4045 /* If we are optimizing, force expensive constants into a register. */
4046 if (CONSTANT_P (x
) && optimize
4047 && (rtx_cost (x
, mode
, COMPARE
, 0, optimize_insn_for_speed_p ())
4048 > COSTS_N_INSNS (1)))
4049 x
= force_reg (mode
, x
);
4051 if (CONSTANT_P (y
) && optimize
4052 && (rtx_cost (y
, mode
, COMPARE
, 1, optimize_insn_for_speed_p ())
4053 > COSTS_N_INSNS (1)))
4054 y
= force_reg (mode
, y
);
4057 /* Make sure if we have a canonical comparison. The RTL
4058 documentation states that canonical comparisons are required only
4059 for targets which have cc0. */
4060 gcc_assert (!CONSTANT_P (x
) || CONSTANT_P (y
));
4063 /* Don't let both operands fail to indicate the mode. */
4064 if (GET_MODE (x
) == VOIDmode
&& GET_MODE (y
) == VOIDmode
)
4065 x
= force_reg (mode
, x
);
4066 if (mode
== VOIDmode
)
4067 mode
= GET_MODE (x
) != VOIDmode
? GET_MODE (x
) : GET_MODE (y
);
4069 /* Handle all BLKmode compares. */
4071 if (mode
== BLKmode
)
4073 machine_mode result_mode
;
4074 enum insn_code cmp_code
;
4079 = GEN_INT (MIN (MEM_ALIGN (x
), MEM_ALIGN (y
)) / BITS_PER_UNIT
);
4083 /* Try to use a memory block compare insn - either cmpstr
4084 or cmpmem will do. */
4085 for (cmp_mode
= GET_CLASS_NARROWEST_MODE (MODE_INT
);
4086 cmp_mode
!= VOIDmode
;
4087 cmp_mode
= GET_MODE_WIDER_MODE (cmp_mode
))
4089 cmp_code
= direct_optab_handler (cmpmem_optab
, cmp_mode
);
4090 if (cmp_code
== CODE_FOR_nothing
)
4091 cmp_code
= direct_optab_handler (cmpstr_optab
, cmp_mode
);
4092 if (cmp_code
== CODE_FOR_nothing
)
4093 cmp_code
= direct_optab_handler (cmpstrn_optab
, cmp_mode
);
4094 if (cmp_code
== CODE_FOR_nothing
)
4097 /* Must make sure the size fits the insn's mode. */
4098 if ((CONST_INT_P (size
)
4099 && INTVAL (size
) >= (1 << GET_MODE_BITSIZE (cmp_mode
)))
4100 || (GET_MODE_BITSIZE (GET_MODE (size
))
4101 > GET_MODE_BITSIZE (cmp_mode
)))
4104 result_mode
= insn_data
[cmp_code
].operand
[0].mode
;
4105 result
= gen_reg_rtx (result_mode
);
4106 size
= convert_to_mode (cmp_mode
, size
, 1);
4107 emit_insn (GEN_FCN (cmp_code
) (result
, x
, y
, size
, opalign
));
4109 *ptest
= gen_rtx_fmt_ee (comparison
, VOIDmode
, result
, const0_rtx
);
4110 *pmode
= result_mode
;
4114 if (methods
!= OPTAB_LIB
&& methods
!= OPTAB_LIB_WIDEN
)
4117 /* Otherwise call a library function, memcmp. */
4118 libfunc
= memcmp_libfunc
;
4119 length_type
= sizetype
;
4120 result_mode
= TYPE_MODE (integer_type_node
);
4121 cmp_mode
= TYPE_MODE (length_type
);
4122 size
= convert_to_mode (TYPE_MODE (length_type
), size
,
4123 TYPE_UNSIGNED (length_type
));
4125 result
= emit_library_call_value (libfunc
, 0, LCT_PURE
,
4133 methods
= OPTAB_LIB_WIDEN
;
4137 /* Don't allow operands to the compare to trap, as that can put the
4138 compare and branch in different basic blocks. */
4139 if (cfun
->can_throw_non_call_exceptions
)
4142 x
= force_reg (mode
, x
);
4144 y
= force_reg (mode
, y
);
4147 if (GET_MODE_CLASS (mode
) == MODE_CC
)
4149 enum insn_code icode
= optab_handler (cbranch_optab
, CCmode
);
4150 test
= gen_rtx_fmt_ee (comparison
, VOIDmode
, x
, y
);
4151 gcc_assert (icode
!= CODE_FOR_nothing
4152 && insn_operand_matches (icode
, 0, test
));
4157 mclass
= GET_MODE_CLASS (mode
);
4158 test
= gen_rtx_fmt_ee (comparison
, VOIDmode
, x
, y
);
4162 enum insn_code icode
;
4163 icode
= optab_handler (cbranch_optab
, cmp_mode
);
4164 if (icode
!= CODE_FOR_nothing
4165 && insn_operand_matches (icode
, 0, test
))
4167 rtx_insn
*last
= get_last_insn ();
4168 rtx op0
= prepare_operand (icode
, x
, 1, mode
, cmp_mode
, unsignedp
);
4169 rtx op1
= prepare_operand (icode
, y
, 2, mode
, cmp_mode
, unsignedp
);
4171 && insn_operand_matches (icode
, 1, op0
)
4172 && insn_operand_matches (icode
, 2, op1
))
4174 XEXP (test
, 0) = op0
;
4175 XEXP (test
, 1) = op1
;
4180 delete_insns_since (last
);
4183 if (methods
== OPTAB_DIRECT
|| !CLASS_HAS_WIDER_MODES_P (mclass
))
4185 cmp_mode
= GET_MODE_WIDER_MODE (cmp_mode
);
4187 while (cmp_mode
!= VOIDmode
);
4189 if (methods
!= OPTAB_LIB_WIDEN
)
4192 if (!SCALAR_FLOAT_MODE_P (mode
))
4195 machine_mode ret_mode
;
4197 /* Handle a libcall just for the mode we are using. */
4198 libfunc
= optab_libfunc (cmp_optab
, mode
);
4199 gcc_assert (libfunc
);
4201 /* If we want unsigned, and this mode has a distinct unsigned
4202 comparison routine, use that. */
4205 rtx ulibfunc
= optab_libfunc (ucmp_optab
, mode
);
4210 ret_mode
= targetm
.libgcc_cmp_return_mode ();
4211 result
= emit_library_call_value (libfunc
, NULL_RTX
, LCT_CONST
,
4212 ret_mode
, 2, x
, mode
, y
, mode
);
4214 /* There are two kinds of comparison routines. Biased routines
4215 return 0/1/2, and unbiased routines return -1/0/1. Other parts
4216 of gcc expect that the comparison operation is equivalent
4217 to the modified comparison. For signed comparisons compare the
4218 result against 1 in the biased case, and zero in the unbiased
4219 case. For unsigned comparisons always compare against 1 after
4220 biasing the unbiased result by adding 1. This gives us a way to
4222 The comparisons in the fixed-point helper library are always
4227 if (!TARGET_LIB_INT_CMP_BIASED
&& !ALL_FIXED_POINT_MODE_P (mode
))
4230 x
= plus_constant (ret_mode
, result
, 1);
4236 prepare_cmp_insn (x
, y
, comparison
, NULL_RTX
, unsignedp
, methods
,
4240 prepare_float_lib_cmp (x
, y
, comparison
, ptest
, pmode
);
4248 /* Before emitting an insn with code ICODE, make sure that X, which is going
4249 to be used for operand OPNUM of the insn, is converted from mode MODE to
4250 WIDER_MODE (UNSIGNEDP determines whether it is an unsigned conversion), and
4251 that it is accepted by the operand predicate. Return the new value. */
4254 prepare_operand (enum insn_code icode
, rtx x
, int opnum
, machine_mode mode
,
4255 machine_mode wider_mode
, int unsignedp
)
4257 if (mode
!= wider_mode
)
4258 x
= convert_modes (wider_mode
, mode
, x
, unsignedp
);
4260 if (!insn_operand_matches (icode
, opnum
, x
))
4262 machine_mode op_mode
= insn_data
[(int) icode
].operand
[opnum
].mode
;
4263 if (reload_completed
)
4265 if (GET_MODE (x
) != op_mode
&& GET_MODE (x
) != VOIDmode
)
4267 x
= copy_to_mode_reg (op_mode
, x
);
4273 /* Subroutine of emit_cmp_and_jump_insns; this function is called when we know
4274 we can do the branch. */
4277 emit_cmp_and_jump_insn_1 (rtx test
, machine_mode mode
, rtx label
, int prob
)
4279 machine_mode optab_mode
;
4280 enum mode_class mclass
;
4281 enum insn_code icode
;
4284 mclass
= GET_MODE_CLASS (mode
);
4285 optab_mode
= (mclass
== MODE_CC
) ? CCmode
: mode
;
4286 icode
= optab_handler (cbranch_optab
, optab_mode
);
4288 gcc_assert (icode
!= CODE_FOR_nothing
);
4289 gcc_assert (insn_operand_matches (icode
, 0, test
));
4290 insn
= emit_jump_insn (GEN_FCN (icode
) (test
, XEXP (test
, 0),
4291 XEXP (test
, 1), label
));
4293 && profile_status_for_fn (cfun
) != PROFILE_ABSENT
4296 && any_condjump_p (insn
)
4297 && !find_reg_note (insn
, REG_BR_PROB
, 0))
4298 add_int_reg_note (insn
, REG_BR_PROB
, prob
);
4301 /* Generate code to compare X with Y so that the condition codes are
4302 set and to jump to LABEL if the condition is true. If X is a
4303 constant and Y is not a constant, then the comparison is swapped to
4304 ensure that the comparison RTL has the canonical form.
4306 UNSIGNEDP nonzero says that X and Y are unsigned; this matters if they
4307 need to be widened. UNSIGNEDP is also used to select the proper
4308 branch condition code.
4310 If X and Y have mode BLKmode, then SIZE specifies the size of both X and Y.
4312 MODE is the mode of the inputs (in case they are const_int).
4314 COMPARISON is the rtl operator to compare with (EQ, NE, GT, etc.).
4315 It will be potentially converted into an unsigned variant based on
4316 UNSIGNEDP to select a proper jump instruction.
4318 PROB is the probability of jumping to LABEL. */
4321 emit_cmp_and_jump_insns (rtx x
, rtx y
, enum rtx_code comparison
, rtx size
,
4322 machine_mode mode
, int unsignedp
, rtx label
,
4325 rtx op0
= x
, op1
= y
;
4328 /* Swap operands and condition to ensure canonical RTL. */
4329 if (swap_commutative_operands_p (x
, y
)
4330 && can_compare_p (swap_condition (comparison
), mode
, ccp_jump
))
4333 comparison
= swap_condition (comparison
);
4336 /* If OP0 is still a constant, then both X and Y must be constants
4337 or the opposite comparison is not supported. Force X into a register
4338 to create canonical RTL. */
4339 if (CONSTANT_P (op0
))
4340 op0
= force_reg (mode
, op0
);
4343 comparison
= unsigned_condition (comparison
);
4345 prepare_cmp_insn (op0
, op1
, comparison
, size
, unsignedp
, OPTAB_LIB_WIDEN
,
4347 emit_cmp_and_jump_insn_1 (test
, mode
, label
, prob
);
4351 /* Emit a library call comparison between floating point X and Y.
4352 COMPARISON is the rtl operator to compare with (EQ, NE, GT, etc.). */
4355 prepare_float_lib_cmp (rtx x
, rtx y
, enum rtx_code comparison
,
4356 rtx
*ptest
, machine_mode
*pmode
)
4358 enum rtx_code swapped
= swap_condition (comparison
);
4359 enum rtx_code reversed
= reverse_condition_maybe_unordered (comparison
);
4360 machine_mode orig_mode
= GET_MODE (x
);
4361 machine_mode mode
, cmp_mode
;
4362 rtx true_rtx
, false_rtx
;
4363 rtx value
, target
, equiv
;
4366 bool reversed_p
= false;
4367 cmp_mode
= targetm
.libgcc_cmp_return_mode ();
4369 for (mode
= orig_mode
;
4371 mode
= GET_MODE_WIDER_MODE (mode
))
4373 if (code_to_optab (comparison
)
4374 && (libfunc
= optab_libfunc (code_to_optab (comparison
), mode
)))
4377 if (code_to_optab (swapped
)
4378 && (libfunc
= optab_libfunc (code_to_optab (swapped
), mode
)))
4381 comparison
= swapped
;
4385 if (code_to_optab (reversed
)
4386 && (libfunc
= optab_libfunc (code_to_optab (reversed
), mode
)))
4388 comparison
= reversed
;
4394 gcc_assert (mode
!= VOIDmode
);
4396 if (mode
!= orig_mode
)
4398 x
= convert_to_mode (mode
, x
, 0);
4399 y
= convert_to_mode (mode
, y
, 0);
4402 /* Attach a REG_EQUAL note describing the semantics of the libcall to
4403 the RTL. The allows the RTL optimizers to delete the libcall if the
4404 condition can be determined at compile-time. */
4405 if (comparison
== UNORDERED
4406 || FLOAT_LIB_COMPARE_RETURNS_BOOL (mode
, comparison
))
4408 true_rtx
= const_true_rtx
;
4409 false_rtx
= const0_rtx
;
4416 true_rtx
= const0_rtx
;
4417 false_rtx
= const_true_rtx
;
4421 true_rtx
= const_true_rtx
;
4422 false_rtx
= const0_rtx
;
4426 true_rtx
= const1_rtx
;
4427 false_rtx
= const0_rtx
;
4431 true_rtx
= const0_rtx
;
4432 false_rtx
= constm1_rtx
;
4436 true_rtx
= constm1_rtx
;
4437 false_rtx
= const0_rtx
;
4441 true_rtx
= const0_rtx
;
4442 false_rtx
= const1_rtx
;
4450 if (comparison
== UNORDERED
)
4452 rtx temp
= simplify_gen_relational (NE
, cmp_mode
, mode
, x
, x
);
4453 equiv
= simplify_gen_relational (NE
, cmp_mode
, mode
, y
, y
);
4454 equiv
= simplify_gen_ternary (IF_THEN_ELSE
, cmp_mode
, cmp_mode
,
4455 temp
, const_true_rtx
, equiv
);
4459 equiv
= simplify_gen_relational (comparison
, cmp_mode
, mode
, x
, y
);
4460 if (! FLOAT_LIB_COMPARE_RETURNS_BOOL (mode
, comparison
))
4461 equiv
= simplify_gen_ternary (IF_THEN_ELSE
, cmp_mode
, cmp_mode
,
4462 equiv
, true_rtx
, false_rtx
);
4466 value
= emit_library_call_value (libfunc
, NULL_RTX
, LCT_CONST
,
4467 cmp_mode
, 2, x
, mode
, y
, mode
);
4468 insns
= get_insns ();
4471 target
= gen_reg_rtx (cmp_mode
);
4472 emit_libcall_block (insns
, target
, value
, equiv
);
4474 if (comparison
== UNORDERED
4475 || FLOAT_LIB_COMPARE_RETURNS_BOOL (mode
, comparison
)
4477 *ptest
= gen_rtx_fmt_ee (reversed_p
? EQ
: NE
, VOIDmode
, target
, false_rtx
);
4479 *ptest
= gen_rtx_fmt_ee (comparison
, VOIDmode
, target
, const0_rtx
);
4484 /* Generate code to indirectly jump to a location given in the rtx LOC. */
4487 emit_indirect_jump (rtx loc
)
4489 if (!targetm
.have_indirect_jump ())
4490 sorry ("indirect jumps are not available on this target");
4492 struct expand_operand ops
[1];
4493 create_address_operand (&ops
[0], loc
);
4494 expand_jump_insn (targetm
.code_for_indirect_jump
, 1, ops
);
4499 /* Emit a conditional move instruction if the machine supports one for that
4500 condition and machine mode.
4502 OP0 and OP1 are the operands that should be compared using CODE. CMODE is
4503 the mode to use should they be constants. If it is VOIDmode, they cannot
4506 OP2 should be stored in TARGET if the comparison is true, otherwise OP3
4507 should be stored there. MODE is the mode to use should they be constants.
4508 If it is VOIDmode, they cannot both be constants.
4510 The result is either TARGET (perhaps modified) or NULL_RTX if the operation
4511 is not supported. */
4514 emit_conditional_move (rtx target
, enum rtx_code code
, rtx op0
, rtx op1
,
4515 machine_mode cmode
, rtx op2
, rtx op3
,
4516 machine_mode mode
, int unsignedp
)
4520 enum insn_code icode
;
4521 enum rtx_code reversed
;
4523 /* If one operand is constant, make it the second one. Only do this
4524 if the other operand is not constant as well. */
4526 if (swap_commutative_operands_p (op0
, op1
))
4528 std::swap (op0
, op1
);
4529 code
= swap_condition (code
);
4532 /* get_condition will prefer to generate LT and GT even if the old
4533 comparison was against zero, so undo that canonicalization here since
4534 comparisons against zero are cheaper. */
4535 if (code
== LT
&& op1
== const1_rtx
)
4536 code
= LE
, op1
= const0_rtx
;
4537 else if (code
== GT
&& op1
== constm1_rtx
)
4538 code
= GE
, op1
= const0_rtx
;
4540 if (cmode
== VOIDmode
)
4541 cmode
= GET_MODE (op0
);
4543 if (swap_commutative_operands_p (op2
, op3
)
4544 && ((reversed
= reversed_comparison_code_parts (code
, op0
, op1
, NULL
))
4547 std::swap (op2
, op3
);
4551 if (mode
== VOIDmode
)
4552 mode
= GET_MODE (op2
);
4554 icode
= direct_optab_handler (movcc_optab
, mode
);
4556 if (icode
== CODE_FOR_nothing
)
4560 target
= gen_reg_rtx (mode
);
4562 code
= unsignedp
? unsigned_condition (code
) : code
;
4563 comparison
= simplify_gen_relational (code
, VOIDmode
, cmode
, op0
, op1
);
4565 /* We can get const0_rtx or const_true_rtx in some circumstances. Just
4566 return NULL and let the caller figure out how best to deal with this
4568 if (!COMPARISON_P (comparison
))
4571 saved_pending_stack_adjust save
;
4572 save_pending_stack_adjust (&save
);
4573 last
= get_last_insn ();
4574 do_pending_stack_adjust ();
4575 prepare_cmp_insn (XEXP (comparison
, 0), XEXP (comparison
, 1),
4576 GET_CODE (comparison
), NULL_RTX
, unsignedp
, OPTAB_WIDEN
,
4577 &comparison
, &cmode
);
4580 struct expand_operand ops
[4];
4582 create_output_operand (&ops
[0], target
, mode
);
4583 create_fixed_operand (&ops
[1], comparison
);
4584 create_input_operand (&ops
[2], op2
, mode
);
4585 create_input_operand (&ops
[3], op3
, mode
);
4586 if (maybe_expand_insn (icode
, 4, ops
))
4588 if (ops
[0].value
!= target
)
4589 convert_move (target
, ops
[0].value
, false);
4593 delete_insns_since (last
);
4594 restore_pending_stack_adjust (&save
);
4598 /* Return nonzero if a conditional move of mode MODE is supported.
4600 This function is for combine so it can tell whether an insn that looks
4601 like a conditional move is actually supported by the hardware. If we
4602 guess wrong we lose a bit on optimization, but that's it. */
4603 /* ??? sparc64 supports conditionally moving integers values based on fp
4604 comparisons, and vice versa. How do we handle them? */
4607 can_conditionally_move_p (machine_mode mode
)
4609 if (direct_optab_handler (movcc_optab
, mode
) != CODE_FOR_nothing
)
4615 /* Emit a conditional addition instruction if the machine supports one for that
4616 condition and machine mode.
4618 OP0 and OP1 are the operands that should be compared using CODE. CMODE is
4619 the mode to use should they be constants. If it is VOIDmode, they cannot
4622 OP2 should be stored in TARGET if the comparison is false, otherwise OP2+OP3
4623 should be stored there. MODE is the mode to use should they be constants.
4624 If it is VOIDmode, they cannot both be constants.
4626 The result is either TARGET (perhaps modified) or NULL_RTX if the operation
4627 is not supported. */
4630 emit_conditional_add (rtx target
, enum rtx_code code
, rtx op0
, rtx op1
,
4631 machine_mode cmode
, rtx op2
, rtx op3
,
4632 machine_mode mode
, int unsignedp
)
4636 enum insn_code icode
;
4638 /* If one operand is constant, make it the second one. Only do this
4639 if the other operand is not constant as well. */
4641 if (swap_commutative_operands_p (op0
, op1
))
4643 std::swap (op0
, op1
);
4644 code
= swap_condition (code
);
4647 /* get_condition will prefer to generate LT and GT even if the old
4648 comparison was against zero, so undo that canonicalization here since
4649 comparisons against zero are cheaper. */
4650 if (code
== LT
&& op1
== const1_rtx
)
4651 code
= LE
, op1
= const0_rtx
;
4652 else if (code
== GT
&& op1
== constm1_rtx
)
4653 code
= GE
, op1
= const0_rtx
;
4655 if (cmode
== VOIDmode
)
4656 cmode
= GET_MODE (op0
);
4658 if (mode
== VOIDmode
)
4659 mode
= GET_MODE (op2
);
4661 icode
= optab_handler (addcc_optab
, mode
);
4663 if (icode
== CODE_FOR_nothing
)
4667 target
= gen_reg_rtx (mode
);
4669 code
= unsignedp
? unsigned_condition (code
) : code
;
4670 comparison
= simplify_gen_relational (code
, VOIDmode
, cmode
, op0
, op1
);
4672 /* We can get const0_rtx or const_true_rtx in some circumstances. Just
4673 return NULL and let the caller figure out how best to deal with this
4675 if (!COMPARISON_P (comparison
))
4678 do_pending_stack_adjust ();
4679 last
= get_last_insn ();
4680 prepare_cmp_insn (XEXP (comparison
, 0), XEXP (comparison
, 1),
4681 GET_CODE (comparison
), NULL_RTX
, unsignedp
, OPTAB_WIDEN
,
4682 &comparison
, &cmode
);
4685 struct expand_operand ops
[4];
4687 create_output_operand (&ops
[0], target
, mode
);
4688 create_fixed_operand (&ops
[1], comparison
);
4689 create_input_operand (&ops
[2], op2
, mode
);
4690 create_input_operand (&ops
[3], op3
, mode
);
4691 if (maybe_expand_insn (icode
, 4, ops
))
4693 if (ops
[0].value
!= target
)
4694 convert_move (target
, ops
[0].value
, false);
4698 delete_insns_since (last
);
4702 /* These functions attempt to generate an insn body, rather than
4703 emitting the insn, but if the gen function already emits them, we
4704 make no attempt to turn them back into naked patterns. */
4706 /* Generate and return an insn body to add Y to X. */
4709 gen_add2_insn (rtx x
, rtx y
)
4711 enum insn_code icode
= optab_handler (add_optab
, GET_MODE (x
));
4713 gcc_assert (insn_operand_matches (icode
, 0, x
));
4714 gcc_assert (insn_operand_matches (icode
, 1, x
));
4715 gcc_assert (insn_operand_matches (icode
, 2, y
));
4717 return GEN_FCN (icode
) (x
, x
, y
);
4720 /* Generate and return an insn body to add r1 and c,
4721 storing the result in r0. */
4724 gen_add3_insn (rtx r0
, rtx r1
, rtx c
)
4726 enum insn_code icode
= optab_handler (add_optab
, GET_MODE (r0
));
4728 if (icode
== CODE_FOR_nothing
4729 || !insn_operand_matches (icode
, 0, r0
)
4730 || !insn_operand_matches (icode
, 1, r1
)
4731 || !insn_operand_matches (icode
, 2, c
))
4734 return GEN_FCN (icode
) (r0
, r1
, c
);
4738 have_add2_insn (rtx x
, rtx y
)
4740 enum insn_code icode
;
4742 gcc_assert (GET_MODE (x
) != VOIDmode
);
4744 icode
= optab_handler (add_optab
, GET_MODE (x
));
4746 if (icode
== CODE_FOR_nothing
)
4749 if (!insn_operand_matches (icode
, 0, x
)
4750 || !insn_operand_matches (icode
, 1, x
)
4751 || !insn_operand_matches (icode
, 2, y
))
4757 /* Generate and return an insn body to add Y to X. */
4760 gen_addptr3_insn (rtx x
, rtx y
, rtx z
)
4762 enum insn_code icode
= optab_handler (addptr3_optab
, GET_MODE (x
));
4764 gcc_assert (insn_operand_matches (icode
, 0, x
));
4765 gcc_assert (insn_operand_matches (icode
, 1, y
));
4766 gcc_assert (insn_operand_matches (icode
, 2, z
));
4768 return GEN_FCN (icode
) (x
, y
, z
);
4771 /* Return true if the target implements an addptr pattern and X, Y,
4772 and Z are valid for the pattern predicates. */
4775 have_addptr3_insn (rtx x
, rtx y
, rtx z
)
4777 enum insn_code icode
;
4779 gcc_assert (GET_MODE (x
) != VOIDmode
);
4781 icode
= optab_handler (addptr3_optab
, GET_MODE (x
));
4783 if (icode
== CODE_FOR_nothing
)
4786 if (!insn_operand_matches (icode
, 0, x
)
4787 || !insn_operand_matches (icode
, 1, y
)
4788 || !insn_operand_matches (icode
, 2, z
))
4794 /* Generate and return an insn body to subtract Y from X. */
4797 gen_sub2_insn (rtx x
, rtx y
)
4799 enum insn_code icode
= optab_handler (sub_optab
, GET_MODE (x
));
4801 gcc_assert (insn_operand_matches (icode
, 0, x
));
4802 gcc_assert (insn_operand_matches (icode
, 1, x
));
4803 gcc_assert (insn_operand_matches (icode
, 2, y
));
4805 return GEN_FCN (icode
) (x
, x
, y
);
4808 /* Generate and return an insn body to subtract r1 and c,
4809 storing the result in r0. */
4812 gen_sub3_insn (rtx r0
, rtx r1
, rtx c
)
4814 enum insn_code icode
= optab_handler (sub_optab
, GET_MODE (r0
));
4816 if (icode
== CODE_FOR_nothing
4817 || !insn_operand_matches (icode
, 0, r0
)
4818 || !insn_operand_matches (icode
, 1, r1
)
4819 || !insn_operand_matches (icode
, 2, c
))
4822 return GEN_FCN (icode
) (r0
, r1
, c
);
4826 have_sub2_insn (rtx x
, rtx y
)
4828 enum insn_code icode
;
4830 gcc_assert (GET_MODE (x
) != VOIDmode
);
4832 icode
= optab_handler (sub_optab
, GET_MODE (x
));
4834 if (icode
== CODE_FOR_nothing
)
4837 if (!insn_operand_matches (icode
, 0, x
)
4838 || !insn_operand_matches (icode
, 1, x
)
4839 || !insn_operand_matches (icode
, 2, y
))
4845 /* Return the insn code used to extend FROM_MODE to TO_MODE.
4846 UNSIGNEDP specifies zero-extension instead of sign-extension. If
4847 no such operation exists, CODE_FOR_nothing will be returned. */
4850 can_extend_p (machine_mode to_mode
, machine_mode from_mode
,
4854 #ifdef HAVE_ptr_extend
4856 return CODE_FOR_ptr_extend
;
4859 tab
= unsignedp
? zext_optab
: sext_optab
;
4860 return convert_optab_handler (tab
, to_mode
, from_mode
);
4863 /* Generate the body of an insn to extend Y (with mode MFROM)
4864 into X (with mode MTO). Do zero-extension if UNSIGNEDP is nonzero. */
4867 gen_extend_insn (rtx x
, rtx y
, machine_mode mto
,
4868 machine_mode mfrom
, int unsignedp
)
4870 enum insn_code icode
= can_extend_p (mto
, mfrom
, unsignedp
);
4871 return GEN_FCN (icode
) (x
, y
);
4874 /* can_fix_p and can_float_p say whether the target machine
4875 can directly convert a given fixed point type to
4876 a given floating point type, or vice versa.
4877 The returned value is the CODE_FOR_... value to use,
4878 or CODE_FOR_nothing if these modes cannot be directly converted.
4880 *TRUNCP_PTR is set to 1 if it is necessary to output
4881 an explicit FTRUNC insn before the fix insn; otherwise 0. */
4883 static enum insn_code
4884 can_fix_p (machine_mode fixmode
, machine_mode fltmode
,
4885 int unsignedp
, int *truncp_ptr
)
4888 enum insn_code icode
;
4890 tab
= unsignedp
? ufixtrunc_optab
: sfixtrunc_optab
;
4891 icode
= convert_optab_handler (tab
, fixmode
, fltmode
);
4892 if (icode
!= CODE_FOR_nothing
)
4898 /* FIXME: This requires a port to define both FIX and FTRUNC pattern
4899 for this to work. We need to rework the fix* and ftrunc* patterns
4900 and documentation. */
4901 tab
= unsignedp
? ufix_optab
: sfix_optab
;
4902 icode
= convert_optab_handler (tab
, fixmode
, fltmode
);
4903 if (icode
!= CODE_FOR_nothing
4904 && optab_handler (ftrunc_optab
, fltmode
) != CODE_FOR_nothing
)
4911 return CODE_FOR_nothing
;
4915 can_float_p (machine_mode fltmode
, machine_mode fixmode
,
4920 tab
= unsignedp
? ufloat_optab
: sfloat_optab
;
4921 return convert_optab_handler (tab
, fltmode
, fixmode
);
4924 /* Function supportable_convert_operation
4926 Check whether an operation represented by the code CODE is a
4927 convert operation that is supported by the target platform in
4928 vector form (i.e., when operating on arguments of type VECTYPE_IN
4929 producing a result of type VECTYPE_OUT).
4931 Convert operations we currently support directly are FIX_TRUNC and FLOAT.
4932 This function checks if these operations are supported
4933 by the target platform either directly (via vector tree-codes), or via
4937 - CODE1 is code of vector operation to be used when
4938 vectorizing the operation, if available.
4939 - DECL is decl of target builtin functions to be used
4940 when vectorizing the operation, if available. In this case,
4941 CODE1 is CALL_EXPR. */
4944 supportable_convert_operation (enum tree_code code
,
4945 tree vectype_out
, tree vectype_in
,
4946 tree
*decl
, enum tree_code
*code1
)
4951 m1
= TYPE_MODE (vectype_out
);
4952 m2
= TYPE_MODE (vectype_in
);
4954 /* First check if we can done conversion directly. */
4955 if ((code
== FIX_TRUNC_EXPR
4956 && can_fix_p (m1
,m2
,TYPE_UNSIGNED (vectype_out
), &truncp
)
4957 != CODE_FOR_nothing
)
4958 || (code
== FLOAT_EXPR
4959 && can_float_p (m1
,m2
,TYPE_UNSIGNED (vectype_in
))
4960 != CODE_FOR_nothing
))
4966 /* Now check for builtin. */
4967 if (targetm
.vectorize
.builtin_conversion
4968 && targetm
.vectorize
.builtin_conversion (code
, vectype_out
, vectype_in
))
4971 *decl
= targetm
.vectorize
.builtin_conversion (code
, vectype_out
, vectype_in
);
4978 /* Generate code to convert FROM to floating point
4979 and store in TO. FROM must be fixed point and not VOIDmode.
4980 UNSIGNEDP nonzero means regard FROM as unsigned.
4981 Normally this is done by correcting the final value
4982 if it is negative. */
4985 expand_float (rtx to
, rtx from
, int unsignedp
)
4987 enum insn_code icode
;
4989 machine_mode fmode
, imode
;
4990 bool can_do_signed
= false;
4992 /* Crash now, because we won't be able to decide which mode to use. */
4993 gcc_assert (GET_MODE (from
) != VOIDmode
);
4995 /* Look for an insn to do the conversion. Do it in the specified
4996 modes if possible; otherwise convert either input, output or both to
4997 wider mode. If the integer mode is wider than the mode of FROM,
4998 we can do the conversion signed even if the input is unsigned. */
5000 for (fmode
= GET_MODE (to
); fmode
!= VOIDmode
;
5001 fmode
= GET_MODE_WIDER_MODE (fmode
))
5002 for (imode
= GET_MODE (from
); imode
!= VOIDmode
;
5003 imode
= GET_MODE_WIDER_MODE (imode
))
5005 int doing_unsigned
= unsignedp
;
5007 if (fmode
!= GET_MODE (to
)
5008 && significand_size (fmode
) < GET_MODE_PRECISION (GET_MODE (from
)))
5011 icode
= can_float_p (fmode
, imode
, unsignedp
);
5012 if (icode
== CODE_FOR_nothing
&& unsignedp
)
5014 enum insn_code scode
= can_float_p (fmode
, imode
, 0);
5015 if (scode
!= CODE_FOR_nothing
)
5016 can_do_signed
= true;
5017 if (imode
!= GET_MODE (from
))
5018 icode
= scode
, doing_unsigned
= 0;
5021 if (icode
!= CODE_FOR_nothing
)
5023 if (imode
!= GET_MODE (from
))
5024 from
= convert_to_mode (imode
, from
, unsignedp
);
5026 if (fmode
!= GET_MODE (to
))
5027 target
= gen_reg_rtx (fmode
);
5029 emit_unop_insn (icode
, target
, from
,
5030 doing_unsigned
? UNSIGNED_FLOAT
: FLOAT
);
5033 convert_move (to
, target
, 0);
5038 /* Unsigned integer, and no way to convert directly. Convert as signed,
5039 then unconditionally adjust the result. */
5040 if (unsignedp
&& can_do_signed
)
5042 rtx_code_label
*label
= gen_label_rtx ();
5044 REAL_VALUE_TYPE offset
;
5046 /* Look for a usable floating mode FMODE wider than the source and at
5047 least as wide as the target. Using FMODE will avoid rounding woes
5048 with unsigned values greater than the signed maximum value. */
5050 for (fmode
= GET_MODE (to
); fmode
!= VOIDmode
;
5051 fmode
= GET_MODE_WIDER_MODE (fmode
))
5052 if (GET_MODE_PRECISION (GET_MODE (from
)) < GET_MODE_BITSIZE (fmode
)
5053 && can_float_p (fmode
, GET_MODE (from
), 0) != CODE_FOR_nothing
)
5056 if (fmode
== VOIDmode
)
5058 /* There is no such mode. Pretend the target is wide enough. */
5059 fmode
= GET_MODE (to
);
5061 /* Avoid double-rounding when TO is narrower than FROM. */
5062 if ((significand_size (fmode
) + 1)
5063 < GET_MODE_PRECISION (GET_MODE (from
)))
5066 rtx_code_label
*neglabel
= gen_label_rtx ();
5068 /* Don't use TARGET if it isn't a register, is a hard register,
5069 or is the wrong mode. */
5071 || REGNO (target
) < FIRST_PSEUDO_REGISTER
5072 || GET_MODE (target
) != fmode
)
5073 target
= gen_reg_rtx (fmode
);
5075 imode
= GET_MODE (from
);
5076 do_pending_stack_adjust ();
5078 /* Test whether the sign bit is set. */
5079 emit_cmp_and_jump_insns (from
, const0_rtx
, LT
, NULL_RTX
, imode
,
5082 /* The sign bit is not set. Convert as signed. */
5083 expand_float (target
, from
, 0);
5084 emit_jump_insn (targetm
.gen_jump (label
));
5087 /* The sign bit is set.
5088 Convert to a usable (positive signed) value by shifting right
5089 one bit, while remembering if a nonzero bit was shifted
5090 out; i.e., compute (from & 1) | (from >> 1). */
5092 emit_label (neglabel
);
5093 temp
= expand_binop (imode
, and_optab
, from
, const1_rtx
,
5094 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
5095 temp1
= expand_shift (RSHIFT_EXPR
, imode
, from
, 1, NULL_RTX
, 1);
5096 temp
= expand_binop (imode
, ior_optab
, temp
, temp1
, temp
, 1,
5098 expand_float (target
, temp
, 0);
5100 /* Multiply by 2 to undo the shift above. */
5101 temp
= expand_binop (fmode
, add_optab
, target
, target
,
5102 target
, 0, OPTAB_LIB_WIDEN
);
5104 emit_move_insn (target
, temp
);
5106 do_pending_stack_adjust ();
5112 /* If we are about to do some arithmetic to correct for an
5113 unsigned operand, do it in a pseudo-register. */
5115 if (GET_MODE (to
) != fmode
5116 || !REG_P (to
) || REGNO (to
) < FIRST_PSEUDO_REGISTER
)
5117 target
= gen_reg_rtx (fmode
);
5119 /* Convert as signed integer to floating. */
5120 expand_float (target
, from
, 0);
5122 /* If FROM is negative (and therefore TO is negative),
5123 correct its value by 2**bitwidth. */
5125 do_pending_stack_adjust ();
5126 emit_cmp_and_jump_insns (from
, const0_rtx
, GE
, NULL_RTX
, GET_MODE (from
),
5130 real_2expN (&offset
, GET_MODE_PRECISION (GET_MODE (from
)), fmode
);
5131 temp
= expand_binop (fmode
, add_optab
, target
,
5132 CONST_DOUBLE_FROM_REAL_VALUE (offset
, fmode
),
5133 target
, 0, OPTAB_LIB_WIDEN
);
5135 emit_move_insn (target
, temp
);
5137 do_pending_stack_adjust ();
5142 /* No hardware instruction available; call a library routine. */
5147 convert_optab tab
= unsignedp
? ufloat_optab
: sfloat_optab
;
5149 if (GET_MODE_PRECISION (GET_MODE (from
)) < GET_MODE_PRECISION (SImode
))
5150 from
= convert_to_mode (SImode
, from
, unsignedp
);
5152 libfunc
= convert_optab_libfunc (tab
, GET_MODE (to
), GET_MODE (from
));
5153 gcc_assert (libfunc
);
5157 value
= emit_library_call_value (libfunc
, NULL_RTX
, LCT_CONST
,
5158 GET_MODE (to
), 1, from
,
5160 insns
= get_insns ();
5163 emit_libcall_block (insns
, target
, value
,
5164 gen_rtx_fmt_e (unsignedp
? UNSIGNED_FLOAT
: FLOAT
,
5165 GET_MODE (to
), from
));
5170 /* Copy result to requested destination
5171 if we have been computing in a temp location. */
5175 if (GET_MODE (target
) == GET_MODE (to
))
5176 emit_move_insn (to
, target
);
5178 convert_move (to
, target
, 0);
5182 /* Generate code to convert FROM to fixed point and store in TO. FROM
5183 must be floating point. */
5186 expand_fix (rtx to
, rtx from
, int unsignedp
)
5188 enum insn_code icode
;
5190 machine_mode fmode
, imode
;
5193 /* We first try to find a pair of modes, one real and one integer, at
5194 least as wide as FROM and TO, respectively, in which we can open-code
5195 this conversion. If the integer mode is wider than the mode of TO,
5196 we can do the conversion either signed or unsigned. */
5198 for (fmode
= GET_MODE (from
); fmode
!= VOIDmode
;
5199 fmode
= GET_MODE_WIDER_MODE (fmode
))
5200 for (imode
= GET_MODE (to
); imode
!= VOIDmode
;
5201 imode
= GET_MODE_WIDER_MODE (imode
))
5203 int doing_unsigned
= unsignedp
;
5205 icode
= can_fix_p (imode
, fmode
, unsignedp
, &must_trunc
);
5206 if (icode
== CODE_FOR_nothing
&& imode
!= GET_MODE (to
) && unsignedp
)
5207 icode
= can_fix_p (imode
, fmode
, 0, &must_trunc
), doing_unsigned
= 0;
5209 if (icode
!= CODE_FOR_nothing
)
5211 rtx_insn
*last
= get_last_insn ();
5212 if (fmode
!= GET_MODE (from
))
5213 from
= convert_to_mode (fmode
, from
, 0);
5217 rtx temp
= gen_reg_rtx (GET_MODE (from
));
5218 from
= expand_unop (GET_MODE (from
), ftrunc_optab
, from
,
5222 if (imode
!= GET_MODE (to
))
5223 target
= gen_reg_rtx (imode
);
5225 if (maybe_emit_unop_insn (icode
, target
, from
,
5226 doing_unsigned
? UNSIGNED_FIX
: FIX
))
5229 convert_move (to
, target
, unsignedp
);
5232 delete_insns_since (last
);
5236 /* For an unsigned conversion, there is one more way to do it.
5237 If we have a signed conversion, we generate code that compares
5238 the real value to the largest representable positive number. If if
5239 is smaller, the conversion is done normally. Otherwise, subtract
5240 one plus the highest signed number, convert, and add it back.
5242 We only need to check all real modes, since we know we didn't find
5243 anything with a wider integer mode.
5245 This code used to extend FP value into mode wider than the destination.
5246 This is needed for decimal float modes which cannot accurately
5247 represent one plus the highest signed number of the same size, but
5248 not for binary modes. Consider, for instance conversion from SFmode
5251 The hot path through the code is dealing with inputs smaller than 2^63
5252 and doing just the conversion, so there is no bits to lose.
5254 In the other path we know the value is positive in the range 2^63..2^64-1
5255 inclusive. (as for other input overflow happens and result is undefined)
5256 So we know that the most important bit set in mantissa corresponds to
5257 2^63. The subtraction of 2^63 should not generate any rounding as it
5258 simply clears out that bit. The rest is trivial. */
5260 if (unsignedp
&& GET_MODE_PRECISION (GET_MODE (to
)) <= HOST_BITS_PER_WIDE_INT
)
5261 for (fmode
= GET_MODE (from
); fmode
!= VOIDmode
;
5262 fmode
= GET_MODE_WIDER_MODE (fmode
))
5263 if (CODE_FOR_nothing
!= can_fix_p (GET_MODE (to
), fmode
, 0, &must_trunc
)
5264 && (!DECIMAL_FLOAT_MODE_P (fmode
)
5265 || GET_MODE_BITSIZE (fmode
) > GET_MODE_PRECISION (GET_MODE (to
))))
5268 REAL_VALUE_TYPE offset
;
5270 rtx_code_label
*lab1
, *lab2
;
5273 bitsize
= GET_MODE_PRECISION (GET_MODE (to
));
5274 real_2expN (&offset
, bitsize
- 1, fmode
);
5275 limit
= CONST_DOUBLE_FROM_REAL_VALUE (offset
, fmode
);
5276 lab1
= gen_label_rtx ();
5277 lab2
= gen_label_rtx ();
5279 if (fmode
!= GET_MODE (from
))
5280 from
= convert_to_mode (fmode
, from
, 0);
5282 /* See if we need to do the subtraction. */
5283 do_pending_stack_adjust ();
5284 emit_cmp_and_jump_insns (from
, limit
, GE
, NULL_RTX
, GET_MODE (from
),
5287 /* If not, do the signed "fix" and branch around fixup code. */
5288 expand_fix (to
, from
, 0);
5289 emit_jump_insn (targetm
.gen_jump (lab2
));
5292 /* Otherwise, subtract 2**(N-1), convert to signed number,
5293 then add 2**(N-1). Do the addition using XOR since this
5294 will often generate better code. */
5296 target
= expand_binop (GET_MODE (from
), sub_optab
, from
, limit
,
5297 NULL_RTX
, 0, OPTAB_LIB_WIDEN
);
5298 expand_fix (to
, target
, 0);
5299 target
= expand_binop (GET_MODE (to
), xor_optab
, to
,
5301 ((HOST_WIDE_INT
) 1 << (bitsize
- 1),
5303 to
, 1, OPTAB_LIB_WIDEN
);
5306 emit_move_insn (to
, target
);
5310 if (optab_handler (mov_optab
, GET_MODE (to
)) != CODE_FOR_nothing
)
5312 /* Make a place for a REG_NOTE and add it. */
5313 insn
= emit_move_insn (to
, to
);
5314 set_dst_reg_note (insn
, REG_EQUAL
,
5315 gen_rtx_fmt_e (UNSIGNED_FIX
, GET_MODE (to
),
5323 /* We can't do it with an insn, so use a library call. But first ensure
5324 that the mode of TO is at least as wide as SImode, since those are the
5325 only library calls we know about. */
5327 if (GET_MODE_PRECISION (GET_MODE (to
)) < GET_MODE_PRECISION (SImode
))
5329 target
= gen_reg_rtx (SImode
);
5331 expand_fix (target
, from
, unsignedp
);
5339 convert_optab tab
= unsignedp
? ufix_optab
: sfix_optab
;
5340 libfunc
= convert_optab_libfunc (tab
, GET_MODE (to
), GET_MODE (from
));
5341 gcc_assert (libfunc
);
5345 value
= emit_library_call_value (libfunc
, NULL_RTX
, LCT_CONST
,
5346 GET_MODE (to
), 1, from
,
5348 insns
= get_insns ();
5351 emit_libcall_block (insns
, target
, value
,
5352 gen_rtx_fmt_e (unsignedp
? UNSIGNED_FIX
: FIX
,
5353 GET_MODE (to
), from
));
5358 if (GET_MODE (to
) == GET_MODE (target
))
5359 emit_move_insn (to
, target
);
5361 convert_move (to
, target
, 0);
5365 /* Generate code to convert FROM or TO a fixed-point.
5366 If UINTP is true, either TO or FROM is an unsigned integer.
5367 If SATP is true, we need to saturate the result. */
5370 expand_fixed_convert (rtx to
, rtx from
, int uintp
, int satp
)
5372 machine_mode to_mode
= GET_MODE (to
);
5373 machine_mode from_mode
= GET_MODE (from
);
5375 enum rtx_code this_code
;
5376 enum insn_code code
;
5381 if (to_mode
== from_mode
)
5383 emit_move_insn (to
, from
);
5389 tab
= satp
? satfractuns_optab
: fractuns_optab
;
5390 this_code
= satp
? UNSIGNED_SAT_FRACT
: UNSIGNED_FRACT_CONVERT
;
5394 tab
= satp
? satfract_optab
: fract_optab
;
5395 this_code
= satp
? SAT_FRACT
: FRACT_CONVERT
;
5397 code
= convert_optab_handler (tab
, to_mode
, from_mode
);
5398 if (code
!= CODE_FOR_nothing
)
5400 emit_unop_insn (code
, to
, from
, this_code
);
5404 libfunc
= convert_optab_libfunc (tab
, to_mode
, from_mode
);
5405 gcc_assert (libfunc
);
5408 value
= emit_library_call_value (libfunc
, NULL_RTX
, LCT_CONST
, to_mode
,
5409 1, from
, from_mode
);
5410 insns
= get_insns ();
5413 emit_libcall_block (insns
, to
, value
,
5414 gen_rtx_fmt_e (optab_to_code (tab
), to_mode
, from
));
5417 /* Generate code to convert FROM to fixed point and store in TO. FROM
5418 must be floating point, TO must be signed. Use the conversion optab
5419 TAB to do the conversion. */
5422 expand_sfix_optab (rtx to
, rtx from
, convert_optab tab
)
5424 enum insn_code icode
;
5426 machine_mode fmode
, imode
;
5428 /* We first try to find a pair of modes, one real and one integer, at
5429 least as wide as FROM and TO, respectively, in which we can open-code
5430 this conversion. If the integer mode is wider than the mode of TO,
5431 we can do the conversion either signed or unsigned. */
5433 for (fmode
= GET_MODE (from
); fmode
!= VOIDmode
;
5434 fmode
= GET_MODE_WIDER_MODE (fmode
))
5435 for (imode
= GET_MODE (to
); imode
!= VOIDmode
;
5436 imode
= GET_MODE_WIDER_MODE (imode
))
5438 icode
= convert_optab_handler (tab
, imode
, fmode
);
5439 if (icode
!= CODE_FOR_nothing
)
5441 rtx_insn
*last
= get_last_insn ();
5442 if (fmode
!= GET_MODE (from
))
5443 from
= convert_to_mode (fmode
, from
, 0);
5445 if (imode
!= GET_MODE (to
))
5446 target
= gen_reg_rtx (imode
);
5448 if (!maybe_emit_unop_insn (icode
, target
, from
, UNKNOWN
))
5450 delete_insns_since (last
);
5454 convert_move (to
, target
, 0);
5462 /* Report whether we have an instruction to perform the operation
5463 specified by CODE on operands of mode MODE. */
5465 have_insn_for (enum rtx_code code
, machine_mode mode
)
5467 return (code_to_optab (code
)
5468 && (optab_handler (code_to_optab (code
), mode
)
5469 != CODE_FOR_nothing
));
5472 /* Initialize the libfunc fields of an entire group of entries in some
5473 optab. Each entry is set equal to a string consisting of a leading
5474 pair of underscores followed by a generic operation name followed by
5475 a mode name (downshifted to lowercase) followed by a single character
5476 representing the number of operands for the given operation (which is
5477 usually one of the characters '2', '3', or '4').
5479 OPTABLE is the table in which libfunc fields are to be initialized.
5480 OPNAME is the generic (string) name of the operation.
5481 SUFFIX is the character which specifies the number of operands for
5482 the given generic operation.
5483 MODE is the mode to generate for.
5487 gen_libfunc (optab optable
, const char *opname
, int suffix
,
5490 unsigned opname_len
= strlen (opname
);
5491 const char *mname
= GET_MODE_NAME (mode
);
5492 unsigned mname_len
= strlen (mname
);
5493 int prefix_len
= targetm
.libfunc_gnu_prefix
? 6 : 2;
5494 int len
= prefix_len
+ opname_len
+ mname_len
+ 1 + 1;
5495 char *libfunc_name
= XALLOCAVEC (char, len
);
5502 if (targetm
.libfunc_gnu_prefix
)
5509 for (q
= opname
; *q
; )
5511 for (q
= mname
; *q
; q
++)
5512 *p
++ = TOLOWER (*q
);
5516 set_optab_libfunc (optable
, mode
,
5517 ggc_alloc_string (libfunc_name
, p
- libfunc_name
));
5520 /* Like gen_libfunc, but verify that integer operation is involved. */
5523 gen_int_libfunc (optab optable
, const char *opname
, char suffix
,
5526 int maxsize
= 2 * BITS_PER_WORD
;
5527 int minsize
= BITS_PER_WORD
;
5529 if (GET_MODE_CLASS (mode
) != MODE_INT
)
5531 if (maxsize
< LONG_LONG_TYPE_SIZE
)
5532 maxsize
= LONG_LONG_TYPE_SIZE
;
5533 if (minsize
> INT_TYPE_SIZE
5534 && (trapv_binoptab_p (optable
)
5535 || trapv_unoptab_p (optable
)))
5536 minsize
= INT_TYPE_SIZE
;
5537 if (GET_MODE_BITSIZE (mode
) < minsize
5538 || GET_MODE_BITSIZE (mode
) > maxsize
)
5540 gen_libfunc (optable
, opname
, suffix
, mode
);
5543 /* Like gen_libfunc, but verify that FP and set decimal prefix if needed. */
5546 gen_fp_libfunc (optab optable
, const char *opname
, char suffix
,
5551 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
)
5552 gen_libfunc (optable
, opname
, suffix
, mode
);
5553 if (DECIMAL_FLOAT_MODE_P (mode
))
5555 dec_opname
= XALLOCAVEC (char, sizeof (DECIMAL_PREFIX
) + strlen (opname
));
5556 /* For BID support, change the name to have either a bid_ or dpd_ prefix
5557 depending on the low level floating format used. */
5558 memcpy (dec_opname
, DECIMAL_PREFIX
, sizeof (DECIMAL_PREFIX
) - 1);
5559 strcpy (dec_opname
+ sizeof (DECIMAL_PREFIX
) - 1, opname
);
5560 gen_libfunc (optable
, dec_opname
, suffix
, mode
);
5564 /* Like gen_libfunc, but verify that fixed-point operation is involved. */
5567 gen_fixed_libfunc (optab optable
, const char *opname
, char suffix
,
5570 if (!ALL_FIXED_POINT_MODE_P (mode
))
5572 gen_libfunc (optable
, opname
, suffix
, mode
);
5575 /* Like gen_libfunc, but verify that signed fixed-point operation is
5579 gen_signed_fixed_libfunc (optab optable
, const char *opname
, char suffix
,
5582 if (!SIGNED_FIXED_POINT_MODE_P (mode
))
5584 gen_libfunc (optable
, opname
, suffix
, mode
);
5587 /* Like gen_libfunc, but verify that unsigned fixed-point operation is
5591 gen_unsigned_fixed_libfunc (optab optable
, const char *opname
, char suffix
,
5594 if (!UNSIGNED_FIXED_POINT_MODE_P (mode
))
5596 gen_libfunc (optable
, opname
, suffix
, mode
);
5599 /* Like gen_libfunc, but verify that FP or INT operation is involved. */
5602 gen_int_fp_libfunc (optab optable
, const char *name
, char suffix
,
5605 if (DECIMAL_FLOAT_MODE_P (mode
) || GET_MODE_CLASS (mode
) == MODE_FLOAT
)
5606 gen_fp_libfunc (optable
, name
, suffix
, mode
);
5607 if (INTEGRAL_MODE_P (mode
))
5608 gen_int_libfunc (optable
, name
, suffix
, mode
);
5611 /* Like gen_libfunc, but verify that FP or INT operation is involved
5612 and add 'v' suffix for integer operation. */
5615 gen_intv_fp_libfunc (optab optable
, const char *name
, char suffix
,
5618 if (DECIMAL_FLOAT_MODE_P (mode
) || GET_MODE_CLASS (mode
) == MODE_FLOAT
)
5619 gen_fp_libfunc (optable
, name
, suffix
, mode
);
5620 if (GET_MODE_CLASS (mode
) == MODE_INT
)
5622 int len
= strlen (name
);
5623 char *v_name
= XALLOCAVEC (char, len
+ 2);
5624 strcpy (v_name
, name
);
5626 v_name
[len
+ 1] = 0;
5627 gen_int_libfunc (optable
, v_name
, suffix
, mode
);
5631 /* Like gen_libfunc, but verify that FP or INT or FIXED operation is
5635 gen_int_fp_fixed_libfunc (optab optable
, const char *name
, char suffix
,
5638 if (DECIMAL_FLOAT_MODE_P (mode
) || GET_MODE_CLASS (mode
) == MODE_FLOAT
)
5639 gen_fp_libfunc (optable
, name
, suffix
, mode
);
5640 if (INTEGRAL_MODE_P (mode
))
5641 gen_int_libfunc (optable
, name
, suffix
, mode
);
5642 if (ALL_FIXED_POINT_MODE_P (mode
))
5643 gen_fixed_libfunc (optable
, name
, suffix
, mode
);
5646 /* Like gen_libfunc, but verify that FP or INT or signed FIXED operation is
5650 gen_int_fp_signed_fixed_libfunc (optab optable
, const char *name
, char suffix
,
5653 if (DECIMAL_FLOAT_MODE_P (mode
) || GET_MODE_CLASS (mode
) == MODE_FLOAT
)
5654 gen_fp_libfunc (optable
, name
, suffix
, mode
);
5655 if (INTEGRAL_MODE_P (mode
))
5656 gen_int_libfunc (optable
, name
, suffix
, mode
);
5657 if (SIGNED_FIXED_POINT_MODE_P (mode
))
5658 gen_signed_fixed_libfunc (optable
, name
, suffix
, mode
);
5661 /* Like gen_libfunc, but verify that INT or FIXED operation is
5665 gen_int_fixed_libfunc (optab optable
, const char *name
, char suffix
,
5668 if (INTEGRAL_MODE_P (mode
))
5669 gen_int_libfunc (optable
, name
, suffix
, mode
);
5670 if (ALL_FIXED_POINT_MODE_P (mode
))
5671 gen_fixed_libfunc (optable
, name
, suffix
, mode
);
5674 /* Like gen_libfunc, but verify that INT or signed FIXED operation is
5678 gen_int_signed_fixed_libfunc (optab optable
, const char *name
, char suffix
,
5681 if (INTEGRAL_MODE_P (mode
))
5682 gen_int_libfunc (optable
, name
, suffix
, mode
);
5683 if (SIGNED_FIXED_POINT_MODE_P (mode
))
5684 gen_signed_fixed_libfunc (optable
, name
, suffix
, mode
);
5687 /* Like gen_libfunc, but verify that INT or unsigned FIXED operation is
5691 gen_int_unsigned_fixed_libfunc (optab optable
, const char *name
, char suffix
,
5694 if (INTEGRAL_MODE_P (mode
))
5695 gen_int_libfunc (optable
, name
, suffix
, mode
);
5696 if (UNSIGNED_FIXED_POINT_MODE_P (mode
))
5697 gen_unsigned_fixed_libfunc (optable
, name
, suffix
, mode
);
5700 /* Initialize the libfunc fields of an entire group of entries of an
5701 inter-mode-class conversion optab. The string formation rules are
5702 similar to the ones for init_libfuncs, above, but instead of having
5703 a mode name and an operand count these functions have two mode names
5704 and no operand count. */
5707 gen_interclass_conv_libfunc (convert_optab tab
,
5712 size_t opname_len
= strlen (opname
);
5713 size_t mname_len
= 0;
5715 const char *fname
, *tname
;
5717 int prefix_len
= targetm
.libfunc_gnu_prefix
? 6 : 2;
5718 char *libfunc_name
, *suffix
;
5719 char *nondec_name
, *dec_name
, *nondec_suffix
, *dec_suffix
;
5722 /* If this is a decimal conversion, add the current BID vs. DPD prefix that
5723 depends on which underlying decimal floating point format is used. */
5724 const size_t dec_len
= sizeof (DECIMAL_PREFIX
) - 1;
5726 mname_len
= strlen (GET_MODE_NAME (tmode
)) + strlen (GET_MODE_NAME (fmode
));
5728 nondec_name
= XALLOCAVEC (char, prefix_len
+ opname_len
+ mname_len
+ 1 + 1);
5729 nondec_name
[0] = '_';
5730 nondec_name
[1] = '_';
5731 if (targetm
.libfunc_gnu_prefix
)
5733 nondec_name
[2] = 'g';
5734 nondec_name
[3] = 'n';
5735 nondec_name
[4] = 'u';
5736 nondec_name
[5] = '_';
5739 memcpy (&nondec_name
[prefix_len
], opname
, opname_len
);
5740 nondec_suffix
= nondec_name
+ opname_len
+ prefix_len
;
5742 dec_name
= XALLOCAVEC (char, 2 + dec_len
+ opname_len
+ mname_len
+ 1 + 1);
5745 memcpy (&dec_name
[2], DECIMAL_PREFIX
, dec_len
);
5746 memcpy (&dec_name
[2+dec_len
], opname
, opname_len
);
5747 dec_suffix
= dec_name
+ dec_len
+ opname_len
+ 2;
5749 fname
= GET_MODE_NAME (fmode
);
5750 tname
= GET_MODE_NAME (tmode
);
5752 if (DECIMAL_FLOAT_MODE_P (fmode
) || DECIMAL_FLOAT_MODE_P (tmode
))
5754 libfunc_name
= dec_name
;
5755 suffix
= dec_suffix
;
5759 libfunc_name
= nondec_name
;
5760 suffix
= nondec_suffix
;
5764 for (q
= fname
; *q
; p
++, q
++)
5766 for (q
= tname
; *q
; p
++, q
++)
5771 set_conv_libfunc (tab
, tmode
, fmode
,
5772 ggc_alloc_string (libfunc_name
, p
- libfunc_name
));
5775 /* Same as gen_interclass_conv_libfunc but verify that we are producing
5776 int->fp conversion. */
5779 gen_int_to_fp_conv_libfunc (convert_optab tab
,
5784 if (GET_MODE_CLASS (fmode
) != MODE_INT
)
5786 if (GET_MODE_CLASS (tmode
) != MODE_FLOAT
&& !DECIMAL_FLOAT_MODE_P (tmode
))
5788 gen_interclass_conv_libfunc (tab
, opname
, tmode
, fmode
);
5791 /* ufloat_optab is special by using floatun for FP and floatuns decimal fp
5795 gen_ufloat_conv_libfunc (convert_optab tab
,
5796 const char *opname ATTRIBUTE_UNUSED
,
5800 if (DECIMAL_FLOAT_MODE_P (tmode
))
5801 gen_int_to_fp_conv_libfunc (tab
, "floatuns", tmode
, fmode
);
5803 gen_int_to_fp_conv_libfunc (tab
, "floatun", tmode
, fmode
);
5806 /* Same as gen_interclass_conv_libfunc but verify that we are producing
5807 fp->int conversion. */
5810 gen_int_to_fp_nondecimal_conv_libfunc (convert_optab tab
,
5815 if (GET_MODE_CLASS (fmode
) != MODE_INT
)
5817 if (GET_MODE_CLASS (tmode
) != MODE_FLOAT
)
5819 gen_interclass_conv_libfunc (tab
, opname
, tmode
, fmode
);
5822 /* Same as gen_interclass_conv_libfunc but verify that we are producing
5823 fp->int conversion with no decimal floating point involved. */
5826 gen_fp_to_int_conv_libfunc (convert_optab tab
,
5831 if (GET_MODE_CLASS (fmode
) != MODE_FLOAT
&& !DECIMAL_FLOAT_MODE_P (fmode
))
5833 if (GET_MODE_CLASS (tmode
) != MODE_INT
)
5835 gen_interclass_conv_libfunc (tab
, opname
, tmode
, fmode
);
5838 /* Initialize the libfunc fields of an of an intra-mode-class conversion optab.
5839 The string formation rules are
5840 similar to the ones for init_libfunc, above. */
5843 gen_intraclass_conv_libfunc (convert_optab tab
, const char *opname
,
5844 machine_mode tmode
, machine_mode fmode
)
5846 size_t opname_len
= strlen (opname
);
5847 size_t mname_len
= 0;
5849 const char *fname
, *tname
;
5851 int prefix_len
= targetm
.libfunc_gnu_prefix
? 6 : 2;
5852 char *nondec_name
, *dec_name
, *nondec_suffix
, *dec_suffix
;
5853 char *libfunc_name
, *suffix
;
5856 /* If this is a decimal conversion, add the current BID vs. DPD prefix that
5857 depends on which underlying decimal floating point format is used. */
5858 const size_t dec_len
= sizeof (DECIMAL_PREFIX
) - 1;
5860 mname_len
= strlen (GET_MODE_NAME (tmode
)) + strlen (GET_MODE_NAME (fmode
));
5862 nondec_name
= XALLOCAVEC (char, 2 + opname_len
+ mname_len
+ 1 + 1);
5863 nondec_name
[0] = '_';
5864 nondec_name
[1] = '_';
5865 if (targetm
.libfunc_gnu_prefix
)
5867 nondec_name
[2] = 'g';
5868 nondec_name
[3] = 'n';
5869 nondec_name
[4] = 'u';
5870 nondec_name
[5] = '_';
5872 memcpy (&nondec_name
[prefix_len
], opname
, opname_len
);
5873 nondec_suffix
= nondec_name
+ opname_len
+ prefix_len
;
5875 dec_name
= XALLOCAVEC (char, 2 + dec_len
+ opname_len
+ mname_len
+ 1 + 1);
5878 memcpy (&dec_name
[2], DECIMAL_PREFIX
, dec_len
);
5879 memcpy (&dec_name
[2 + dec_len
], opname
, opname_len
);
5880 dec_suffix
= dec_name
+ dec_len
+ opname_len
+ 2;
5882 fname
= GET_MODE_NAME (fmode
);
5883 tname
= GET_MODE_NAME (tmode
);
5885 if (DECIMAL_FLOAT_MODE_P (fmode
) || DECIMAL_FLOAT_MODE_P (tmode
))
5887 libfunc_name
= dec_name
;
5888 suffix
= dec_suffix
;
5892 libfunc_name
= nondec_name
;
5893 suffix
= nondec_suffix
;
5897 for (q
= fname
; *q
; p
++, q
++)
5899 for (q
= tname
; *q
; p
++, q
++)
5905 set_conv_libfunc (tab
, tmode
, fmode
,
5906 ggc_alloc_string (libfunc_name
, p
- libfunc_name
));
5909 /* Pick proper libcall for trunc_optab. We need to chose if we do
5910 truncation or extension and interclass or intraclass. */
5913 gen_trunc_conv_libfunc (convert_optab tab
,
5918 if (GET_MODE_CLASS (tmode
) != MODE_FLOAT
&& !DECIMAL_FLOAT_MODE_P (tmode
))
5920 if (GET_MODE_CLASS (fmode
) != MODE_FLOAT
&& !DECIMAL_FLOAT_MODE_P (fmode
))
5925 if ((GET_MODE_CLASS (tmode
) == MODE_FLOAT
&& DECIMAL_FLOAT_MODE_P (fmode
))
5926 || (GET_MODE_CLASS (fmode
) == MODE_FLOAT
&& DECIMAL_FLOAT_MODE_P (tmode
)))
5927 gen_interclass_conv_libfunc (tab
, opname
, tmode
, fmode
);
5929 if (GET_MODE_PRECISION (fmode
) <= GET_MODE_PRECISION (tmode
))
5932 if ((GET_MODE_CLASS (tmode
) == MODE_FLOAT
5933 && GET_MODE_CLASS (fmode
) == MODE_FLOAT
)
5934 || (DECIMAL_FLOAT_MODE_P (fmode
) && DECIMAL_FLOAT_MODE_P (tmode
)))
5935 gen_intraclass_conv_libfunc (tab
, opname
, tmode
, fmode
);
5938 /* Pick proper libcall for extend_optab. We need to chose if we do
5939 truncation or extension and interclass or intraclass. */
5942 gen_extend_conv_libfunc (convert_optab tab
,
5943 const char *opname ATTRIBUTE_UNUSED
,
5947 if (GET_MODE_CLASS (tmode
) != MODE_FLOAT
&& !DECIMAL_FLOAT_MODE_P (tmode
))
5949 if (GET_MODE_CLASS (fmode
) != MODE_FLOAT
&& !DECIMAL_FLOAT_MODE_P (fmode
))
5954 if ((GET_MODE_CLASS (tmode
) == MODE_FLOAT
&& DECIMAL_FLOAT_MODE_P (fmode
))
5955 || (GET_MODE_CLASS (fmode
) == MODE_FLOAT
&& DECIMAL_FLOAT_MODE_P (tmode
)))
5956 gen_interclass_conv_libfunc (tab
, opname
, tmode
, fmode
);
5958 if (GET_MODE_PRECISION (fmode
) > GET_MODE_PRECISION (tmode
))
5961 if ((GET_MODE_CLASS (tmode
) == MODE_FLOAT
5962 && GET_MODE_CLASS (fmode
) == MODE_FLOAT
)
5963 || (DECIMAL_FLOAT_MODE_P (fmode
) && DECIMAL_FLOAT_MODE_P (tmode
)))
5964 gen_intraclass_conv_libfunc (tab
, opname
, tmode
, fmode
);
5967 /* Pick proper libcall for fract_optab. We need to chose if we do
5968 interclass or intraclass. */
5971 gen_fract_conv_libfunc (convert_optab tab
,
5978 if (!(ALL_FIXED_POINT_MODE_P (tmode
) || ALL_FIXED_POINT_MODE_P (fmode
)))
5981 if (GET_MODE_CLASS (tmode
) == GET_MODE_CLASS (fmode
))
5982 gen_intraclass_conv_libfunc (tab
, opname
, tmode
, fmode
);
5984 gen_interclass_conv_libfunc (tab
, opname
, tmode
, fmode
);
5987 /* Pick proper libcall for fractuns_optab. */
5990 gen_fractuns_conv_libfunc (convert_optab tab
,
5997 /* One mode must be a fixed-point mode, and the other must be an integer
5999 if (!((ALL_FIXED_POINT_MODE_P (tmode
) && GET_MODE_CLASS (fmode
) == MODE_INT
)
6000 || (ALL_FIXED_POINT_MODE_P (fmode
)
6001 && GET_MODE_CLASS (tmode
) == MODE_INT
)))
6004 gen_interclass_conv_libfunc (tab
, opname
, tmode
, fmode
);
6007 /* Pick proper libcall for satfract_optab. We need to chose if we do
6008 interclass or intraclass. */
6011 gen_satfract_conv_libfunc (convert_optab tab
,
6018 /* TMODE must be a fixed-point mode. */
6019 if (!ALL_FIXED_POINT_MODE_P (tmode
))
6022 if (GET_MODE_CLASS (tmode
) == GET_MODE_CLASS (fmode
))
6023 gen_intraclass_conv_libfunc (tab
, opname
, tmode
, fmode
);
6025 gen_interclass_conv_libfunc (tab
, opname
, tmode
, fmode
);
6028 /* Pick proper libcall for satfractuns_optab. */
6031 gen_satfractuns_conv_libfunc (convert_optab tab
,
6038 /* TMODE must be a fixed-point mode, and FMODE must be an integer mode. */
6039 if (!(ALL_FIXED_POINT_MODE_P (tmode
) && GET_MODE_CLASS (fmode
) == MODE_INT
))
6042 gen_interclass_conv_libfunc (tab
, opname
, tmode
, fmode
);
6045 /* Hashtable callbacks for libfunc_decls. */
6047 struct libfunc_decl_hasher
: ggc_ptr_hash
<tree_node
>
6052 return IDENTIFIER_HASH_VALUE (DECL_NAME (entry
));
6056 equal (tree decl
, tree name
)
6058 return DECL_NAME (decl
) == name
;
6062 /* A table of previously-created libfuncs, hashed by name. */
6063 static GTY (()) hash_table
<libfunc_decl_hasher
> *libfunc_decls
;
6065 /* Build a decl for a libfunc named NAME. */
6068 build_libfunc_function (const char *name
)
6070 tree decl
= build_decl (UNKNOWN_LOCATION
, FUNCTION_DECL
,
6071 get_identifier (name
),
6072 build_function_type (integer_type_node
, NULL_TREE
));
6073 /* ??? We don't have any type information except for this is
6074 a function. Pretend this is "int foo()". */
6075 DECL_ARTIFICIAL (decl
) = 1;
6076 DECL_EXTERNAL (decl
) = 1;
6077 TREE_PUBLIC (decl
) = 1;
6078 gcc_assert (DECL_ASSEMBLER_NAME (decl
));
6080 /* Zap the nonsensical SYMBOL_REF_DECL for this. What we're left with
6081 are the flags assigned by targetm.encode_section_info. */
6082 SET_SYMBOL_REF_DECL (XEXP (DECL_RTL (decl
), 0), NULL
);
6088 init_one_libfunc (const char *name
)
6093 if (libfunc_decls
== NULL
)
6094 libfunc_decls
= hash_table
<libfunc_decl_hasher
>::create_ggc (37);
6096 /* See if we have already created a libfunc decl for this function. */
6097 id
= get_identifier (name
);
6098 hash
= IDENTIFIER_HASH_VALUE (id
);
6099 tree
*slot
= libfunc_decls
->find_slot_with_hash (id
, hash
, INSERT
);
6103 /* Create a new decl, so that it can be passed to
6104 targetm.encode_section_info. */
6105 decl
= build_libfunc_function (name
);
6108 return XEXP (DECL_RTL (decl
), 0);
6111 /* Adjust the assembler name of libfunc NAME to ASMSPEC. */
6114 set_user_assembler_libfunc (const char *name
, const char *asmspec
)
6119 id
= get_identifier (name
);
6120 hash
= IDENTIFIER_HASH_VALUE (id
);
6121 tree
*slot
= libfunc_decls
->find_slot_with_hash (id
, hash
, NO_INSERT
);
6123 decl
= (tree
) *slot
;
6124 set_user_assembler_name (decl
, asmspec
);
6125 return XEXP (DECL_RTL (decl
), 0);
6128 /* Call this to reset the function entry for one optab (OPTABLE) in mode
6129 MODE to NAME, which should be either 0 or a string constant. */
6131 set_optab_libfunc (optab op
, machine_mode mode
, const char *name
)
6134 struct libfunc_entry e
;
6135 struct libfunc_entry
**slot
;
6142 val
= init_one_libfunc (name
);
6145 slot
= libfunc_hash
->find_slot (&e
, INSERT
);
6147 *slot
= ggc_alloc
<libfunc_entry
> ();
6149 (*slot
)->mode1
= mode
;
6150 (*slot
)->mode2
= VOIDmode
;
6151 (*slot
)->libfunc
= val
;
6154 /* Call this to reset the function entry for one conversion optab
6155 (OPTABLE) from mode FMODE to mode TMODE to NAME, which should be
6156 either 0 or a string constant. */
6158 set_conv_libfunc (convert_optab optab
, machine_mode tmode
,
6159 machine_mode fmode
, const char *name
)
6162 struct libfunc_entry e
;
6163 struct libfunc_entry
**slot
;
6170 val
= init_one_libfunc (name
);
6173 slot
= libfunc_hash
->find_slot (&e
, INSERT
);
6175 *slot
= ggc_alloc
<libfunc_entry
> ();
6176 (*slot
)->op
= optab
;
6177 (*slot
)->mode1
= tmode
;
6178 (*slot
)->mode2
= fmode
;
6179 (*slot
)->libfunc
= val
;
6182 /* Call this to initialize the contents of the optabs
6183 appropriately for the current target machine. */
6189 libfunc_hash
->empty ();
6191 libfunc_hash
= hash_table
<libfunc_hasher
>::create_ggc (10);
6193 /* Fill in the optabs with the insns we support. */
6194 init_all_optabs (this_fn_optabs
);
6196 /* The ffs function operates on `int'. Fall back on it if we do not
6197 have a libgcc2 function for that width. */
6198 if (INT_TYPE_SIZE
< BITS_PER_WORD
)
6199 set_optab_libfunc (ffs_optab
, mode_for_size (INT_TYPE_SIZE
, MODE_INT
, 0),
6202 /* Explicitly initialize the bswap libfuncs since we need them to be
6203 valid for things other than word_mode. */
6204 if (targetm
.libfunc_gnu_prefix
)
6206 set_optab_libfunc (bswap_optab
, SImode
, "__gnu_bswapsi2");
6207 set_optab_libfunc (bswap_optab
, DImode
, "__gnu_bswapdi2");
6211 set_optab_libfunc (bswap_optab
, SImode
, "__bswapsi2");
6212 set_optab_libfunc (bswap_optab
, DImode
, "__bswapdi2");
6215 /* Use cabs for double complex abs, since systems generally have cabs.
6216 Don't define any libcall for float complex, so that cabs will be used. */
6217 if (complex_double_type_node
)
6218 set_optab_libfunc (abs_optab
, TYPE_MODE (complex_double_type_node
),
6221 abort_libfunc
= init_one_libfunc ("abort");
6222 memcpy_libfunc
= init_one_libfunc ("memcpy");
6223 memmove_libfunc
= init_one_libfunc ("memmove");
6224 memcmp_libfunc
= init_one_libfunc ("memcmp");
6225 memset_libfunc
= init_one_libfunc ("memset");
6226 setbits_libfunc
= init_one_libfunc ("__setbits");
6228 #ifndef DONT_USE_BUILTIN_SETJMP
6229 setjmp_libfunc
= init_one_libfunc ("__builtin_setjmp");
6230 longjmp_libfunc
= init_one_libfunc ("__builtin_longjmp");
6232 setjmp_libfunc
= init_one_libfunc ("setjmp");
6233 longjmp_libfunc
= init_one_libfunc ("longjmp");
6235 unwind_sjlj_register_libfunc
= init_one_libfunc ("_Unwind_SjLj_Register");
6236 unwind_sjlj_unregister_libfunc
6237 = init_one_libfunc ("_Unwind_SjLj_Unregister");
6239 /* For function entry/exit instrumentation. */
6240 profile_function_entry_libfunc
6241 = init_one_libfunc ("__cyg_profile_func_enter");
6242 profile_function_exit_libfunc
6243 = init_one_libfunc ("__cyg_profile_func_exit");
6245 gcov_flush_libfunc
= init_one_libfunc ("__gcov_flush");
6247 /* Allow the target to add more libcalls or rename some, etc. */
6248 targetm
.init_libfuncs ();
6251 /* Use the current target and options to initialize
6252 TREE_OPTIMIZATION_OPTABS (OPTNODE). */
6255 init_tree_optimization_optabs (tree optnode
)
6257 /* Quick exit if we have already computed optabs for this target. */
6258 if (TREE_OPTIMIZATION_BASE_OPTABS (optnode
) == this_target_optabs
)
6261 /* Forget any previous information and set up for the current target. */
6262 TREE_OPTIMIZATION_BASE_OPTABS (optnode
) = this_target_optabs
;
6263 struct target_optabs
*tmp_optabs
= (struct target_optabs
*)
6264 TREE_OPTIMIZATION_OPTABS (optnode
);
6266 memset (tmp_optabs
, 0, sizeof (struct target_optabs
));
6268 tmp_optabs
= ggc_alloc
<target_optabs
> ();
6270 /* Generate a new set of optabs into tmp_optabs. */
6271 init_all_optabs (tmp_optabs
);
6273 /* If the optabs changed, record it. */
6274 if (memcmp (tmp_optabs
, this_target_optabs
, sizeof (struct target_optabs
)))
6275 TREE_OPTIMIZATION_OPTABS (optnode
) = tmp_optabs
;
6278 TREE_OPTIMIZATION_OPTABS (optnode
) = NULL
;
6279 ggc_free (tmp_optabs
);
6283 /* A helper function for init_sync_libfuncs. Using the basename BASE,
6284 install libfuncs into TAB for BASE_N for 1 <= N <= MAX. */
6287 init_sync_libfuncs_1 (optab tab
, const char *base
, int max
)
6291 size_t len
= strlen (base
);
6294 gcc_assert (max
<= 8);
6295 gcc_assert (len
+ 3 < sizeof (buf
));
6297 memcpy (buf
, base
, len
);
6300 buf
[len
+ 2] = '\0';
6303 for (i
= 1; i
<= max
; i
*= 2)
6305 buf
[len
+ 1] = '0' + i
;
6306 set_optab_libfunc (tab
, mode
, buf
);
6307 mode
= GET_MODE_2XWIDER_MODE (mode
);
6312 init_sync_libfuncs (int max
)
6314 if (!flag_sync_libcalls
)
6317 init_sync_libfuncs_1 (sync_compare_and_swap_optab
,
6318 "__sync_val_compare_and_swap", max
);
6319 init_sync_libfuncs_1 (sync_lock_test_and_set_optab
,
6320 "__sync_lock_test_and_set", max
);
6322 init_sync_libfuncs_1 (sync_old_add_optab
, "__sync_fetch_and_add", max
);
6323 init_sync_libfuncs_1 (sync_old_sub_optab
, "__sync_fetch_and_sub", max
);
6324 init_sync_libfuncs_1 (sync_old_ior_optab
, "__sync_fetch_and_or", max
);
6325 init_sync_libfuncs_1 (sync_old_and_optab
, "__sync_fetch_and_and", max
);
6326 init_sync_libfuncs_1 (sync_old_xor_optab
, "__sync_fetch_and_xor", max
);
6327 init_sync_libfuncs_1 (sync_old_nand_optab
, "__sync_fetch_and_nand", max
);
6329 init_sync_libfuncs_1 (sync_new_add_optab
, "__sync_add_and_fetch", max
);
6330 init_sync_libfuncs_1 (sync_new_sub_optab
, "__sync_sub_and_fetch", max
);
6331 init_sync_libfuncs_1 (sync_new_ior_optab
, "__sync_or_and_fetch", max
);
6332 init_sync_libfuncs_1 (sync_new_and_optab
, "__sync_and_and_fetch", max
);
6333 init_sync_libfuncs_1 (sync_new_xor_optab
, "__sync_xor_and_fetch", max
);
6334 init_sync_libfuncs_1 (sync_new_nand_optab
, "__sync_nand_and_fetch", max
);
6337 /* Print information about the current contents of the optabs on
6341 debug_optab_libfuncs (void)
6345 /* Dump the arithmetic optabs. */
6346 for (i
= FIRST_NORM_OPTAB
; i
<= LAST_NORMLIB_OPTAB
; ++i
)
6347 for (j
= 0; j
< NUM_MACHINE_MODES
; ++j
)
6349 rtx l
= optab_libfunc ((optab
) i
, (machine_mode
) j
);
6352 gcc_assert (GET_CODE (l
) == SYMBOL_REF
);
6353 fprintf (stderr
, "%s\t%s:\t%s\n",
6354 GET_RTX_NAME (optab_to_code ((optab
) i
)),
6360 /* Dump the conversion optabs. */
6361 for (i
= FIRST_CONV_OPTAB
; i
<= LAST_CONVLIB_OPTAB
; ++i
)
6362 for (j
= 0; j
< NUM_MACHINE_MODES
; ++j
)
6363 for (k
= 0; k
< NUM_MACHINE_MODES
; ++k
)
6365 rtx l
= convert_optab_libfunc ((optab
) i
, (machine_mode
) j
,
6369 gcc_assert (GET_CODE (l
) == SYMBOL_REF
);
6370 fprintf (stderr
, "%s\t%s\t%s:\t%s\n",
6371 GET_RTX_NAME (optab_to_code ((optab
) i
)),
6380 /* Generate insns to trap with code TCODE if OP1 and OP2 satisfy condition
6381 CODE. Return 0 on failure. */
6384 gen_cond_trap (enum rtx_code code
, rtx op1
, rtx op2
, rtx tcode
)
6386 machine_mode mode
= GET_MODE (op1
);
6387 enum insn_code icode
;
6391 if (mode
== VOIDmode
)
6394 icode
= optab_handler (ctrap_optab
, mode
);
6395 if (icode
== CODE_FOR_nothing
)
6398 /* Some targets only accept a zero trap code. */
6399 if (!insn_operand_matches (icode
, 3, tcode
))
6402 do_pending_stack_adjust ();
6404 prepare_cmp_insn (op1
, op2
, code
, NULL_RTX
, false, OPTAB_DIRECT
,
6409 insn
= GEN_FCN (icode
) (trap_rtx
, XEXP (trap_rtx
, 0), XEXP (trap_rtx
, 1),
6412 /* If that failed, then give up. */
6420 insn
= get_insns ();
6425 /* Return rtx code for TCODE. Use UNSIGNEDP to select signed
6426 or unsigned operation code. */
6429 get_rtx_code (enum tree_code tcode
, bool unsignedp
)
6441 code
= unsignedp
? LTU
: LT
;
6444 code
= unsignedp
? LEU
: LE
;
6447 code
= unsignedp
? GTU
: GT
;
6450 code
= unsignedp
? GEU
: GE
;
6453 case UNORDERED_EXPR
:
6492 /* Return comparison rtx for COND. Use UNSIGNEDP to select signed or
6493 unsigned operators. Do not generate compare instruction. */
6496 vector_compare_rtx (enum tree_code tcode
, tree t_op0
, tree t_op1
,
6497 bool unsignedp
, enum insn_code icode
)
6499 struct expand_operand ops
[2];
6500 rtx rtx_op0
, rtx_op1
;
6501 machine_mode m0
, m1
;
6502 enum rtx_code rcode
= get_rtx_code (tcode
, unsignedp
);
6504 gcc_assert (TREE_CODE_CLASS (tcode
) == tcc_comparison
);
6506 /* Expand operands. For vector types with scalar modes, e.g. where int64x1_t
6507 has mode DImode, this can produce a constant RTX of mode VOIDmode; in such
6508 cases, use the original mode. */
6509 rtx_op0
= expand_expr (t_op0
, NULL_RTX
, TYPE_MODE (TREE_TYPE (t_op0
)),
6511 m0
= GET_MODE (rtx_op0
);
6513 m0
= TYPE_MODE (TREE_TYPE (t_op0
));
6515 rtx_op1
= expand_expr (t_op1
, NULL_RTX
, TYPE_MODE (TREE_TYPE (t_op1
)),
6517 m1
= GET_MODE (rtx_op1
);
6519 m1
= TYPE_MODE (TREE_TYPE (t_op1
));
6521 create_input_operand (&ops
[0], rtx_op0
, m0
);
6522 create_input_operand (&ops
[1], rtx_op1
, m1
);
6523 if (!maybe_legitimize_operands (icode
, 4, 2, ops
))
6525 return gen_rtx_fmt_ee (rcode
, VOIDmode
, ops
[0].value
, ops
[1].value
);
6528 /* Return true if VEC_PERM_EXPR of arbitrary input vectors can be expanded using
6529 SIMD extensions of the CPU. SEL may be NULL, which stands for an unknown
6530 constant. Note that additional permutations representing whole-vector shifts
6531 may also be handled via the vec_shr optab, but only where the second input
6532 vector is entirely constant zeroes; this case is not dealt with here. */
6535 can_vec_perm_p (machine_mode mode
, bool variable
,
6536 const unsigned char *sel
)
6538 machine_mode qimode
;
6540 /* If the target doesn't implement a vector mode for the vector type,
6541 then no operations are supported. */
6542 if (!VECTOR_MODE_P (mode
))
6547 if (direct_optab_handler (vec_perm_const_optab
, mode
) != CODE_FOR_nothing
6549 || targetm
.vectorize
.vec_perm_const_ok
== NULL
6550 || targetm
.vectorize
.vec_perm_const_ok (mode
, sel
)))
6554 if (direct_optab_handler (vec_perm_optab
, mode
) != CODE_FOR_nothing
)
6557 /* We allow fallback to a QI vector mode, and adjust the mask. */
6558 if (GET_MODE_INNER (mode
) == QImode
)
6560 qimode
= mode_for_vector (QImode
, GET_MODE_SIZE (mode
));
6561 if (!VECTOR_MODE_P (qimode
))
6564 /* ??? For completeness, we ought to check the QImode version of
6565 vec_perm_const_optab. But all users of this implicit lowering
6566 feature implement the variable vec_perm_optab. */
6567 if (direct_optab_handler (vec_perm_optab
, qimode
) == CODE_FOR_nothing
)
6570 /* In order to support the lowering of variable permutations,
6571 we need to support shifts and adds. */
6574 if (GET_MODE_UNIT_SIZE (mode
) > 2
6575 && optab_handler (ashl_optab
, mode
) == CODE_FOR_nothing
6576 && optab_handler (vashl_optab
, mode
) == CODE_FOR_nothing
)
6578 if (optab_handler (add_optab
, qimode
) == CODE_FOR_nothing
)
6585 /* Checks if vec_perm mask SEL is a constant equivalent to a shift of the first
6586 vec_perm operand, assuming the second operand is a constant vector of zeroes.
6587 Return the shift distance in bits if so, or NULL_RTX if the vec_perm is not a
6590 shift_amt_for_vec_perm_mask (rtx sel
)
6592 unsigned int i
, first
, nelt
= GET_MODE_NUNITS (GET_MODE (sel
));
6593 unsigned int bitsize
= GET_MODE_BITSIZE (GET_MODE_INNER (GET_MODE (sel
)));
6595 if (GET_CODE (sel
) != CONST_VECTOR
)
6598 first
= INTVAL (CONST_VECTOR_ELT (sel
, 0));
6599 if (first
>= 2*nelt
)
6601 for (i
= 1; i
< nelt
; i
++)
6603 int idx
= INTVAL (CONST_VECTOR_ELT (sel
, i
));
6604 unsigned int expected
= (i
+ first
) & (2 * nelt
- 1);
6605 /* Indices into the second vector are all equivalent. */
6606 if (idx
< 0 || (MIN (nelt
, (unsigned) idx
) != MIN (nelt
, expected
)))
6610 return GEN_INT (first
* bitsize
);
6613 /* A subroutine of expand_vec_perm for expanding one vec_perm insn. */
6616 expand_vec_perm_1 (enum insn_code icode
, rtx target
,
6617 rtx v0
, rtx v1
, rtx sel
)
6619 machine_mode tmode
= GET_MODE (target
);
6620 machine_mode smode
= GET_MODE (sel
);
6621 struct expand_operand ops
[4];
6623 create_output_operand (&ops
[0], target
, tmode
);
6624 create_input_operand (&ops
[3], sel
, smode
);
6626 /* Make an effort to preserve v0 == v1. The target expander is able to
6627 rely on this to determine if we're permuting a single input operand. */
6628 if (rtx_equal_p (v0
, v1
))
6630 if (!insn_operand_matches (icode
, 1, v0
))
6631 v0
= force_reg (tmode
, v0
);
6632 gcc_checking_assert (insn_operand_matches (icode
, 1, v0
));
6633 gcc_checking_assert (insn_operand_matches (icode
, 2, v0
));
6635 create_fixed_operand (&ops
[1], v0
);
6636 create_fixed_operand (&ops
[2], v0
);
6640 create_input_operand (&ops
[1], v0
, tmode
);
6641 /* See if this can be handled with a vec_shr. We only do this if the
6642 second vector is all zeroes. */
6643 enum insn_code shift_code
= optab_handler (vec_shr_optab
, GET_MODE (v0
));
6644 if (v1
== CONST0_RTX (GET_MODE (v1
)) && shift_code
)
6645 if (rtx shift_amt
= shift_amt_for_vec_perm_mask (sel
))
6647 create_convert_operand_from_type (&ops
[2], shift_amt
,
6648 sizetype_tab
[(int) stk_sizetype
]);
6649 if (maybe_expand_insn (shift_code
, 3, ops
))
6650 return ops
[0].value
;
6652 create_input_operand (&ops
[2], v1
, tmode
);
6655 if (maybe_expand_insn (icode
, 4, ops
))
6656 return ops
[0].value
;
6660 /* Generate instructions for vec_perm optab given its mode
6661 and three operands. */
6664 expand_vec_perm (machine_mode mode
, rtx v0
, rtx v1
, rtx sel
, rtx target
)
6666 enum insn_code icode
;
6667 machine_mode qimode
;
6668 unsigned int i
, w
, e
, u
;
6669 rtx tmp
, sel_qi
= NULL
;
6672 if (!target
|| GET_MODE (target
) != mode
)
6673 target
= gen_reg_rtx (mode
);
6675 w
= GET_MODE_SIZE (mode
);
6676 e
= GET_MODE_NUNITS (mode
);
6677 u
= GET_MODE_UNIT_SIZE (mode
);
6679 /* Set QIMODE to a different vector mode with byte elements.
6680 If no such mode, or if MODE already has byte elements, use VOIDmode. */
6682 if (GET_MODE_INNER (mode
) != QImode
)
6684 qimode
= mode_for_vector (QImode
, w
);
6685 if (!VECTOR_MODE_P (qimode
))
6689 /* If the input is a constant, expand it specially. */
6690 gcc_assert (GET_MODE_CLASS (GET_MODE (sel
)) == MODE_VECTOR_INT
);
6691 if (GET_CODE (sel
) == CONST_VECTOR
)
6693 icode
= direct_optab_handler (vec_perm_const_optab
, mode
);
6694 if (icode
!= CODE_FOR_nothing
)
6696 tmp
= expand_vec_perm_1 (icode
, target
, v0
, v1
, sel
);
6701 /* Fall back to a constant byte-based permutation. */
6702 if (qimode
!= VOIDmode
)
6704 vec
= rtvec_alloc (w
);
6705 for (i
= 0; i
< e
; ++i
)
6707 unsigned int j
, this_e
;
6709 this_e
= INTVAL (CONST_VECTOR_ELT (sel
, i
));
6710 this_e
&= 2 * e
- 1;
6713 for (j
= 0; j
< u
; ++j
)
6714 RTVEC_ELT (vec
, i
* u
+ j
) = GEN_INT (this_e
+ j
);
6716 sel_qi
= gen_rtx_CONST_VECTOR (qimode
, vec
);
6718 icode
= direct_optab_handler (vec_perm_const_optab
, qimode
);
6719 if (icode
!= CODE_FOR_nothing
)
6721 tmp
= mode
!= qimode
? gen_reg_rtx (qimode
) : target
;
6722 tmp
= expand_vec_perm_1 (icode
, tmp
, gen_lowpart (qimode
, v0
),
6723 gen_lowpart (qimode
, v1
), sel_qi
);
6725 return gen_lowpart (mode
, tmp
);
6730 /* Otherwise expand as a fully variable permuation. */
6731 icode
= direct_optab_handler (vec_perm_optab
, mode
);
6732 if (icode
!= CODE_FOR_nothing
)
6734 tmp
= expand_vec_perm_1 (icode
, target
, v0
, v1
, sel
);
6739 /* As a special case to aid several targets, lower the element-based
6740 permutation to a byte-based permutation and try again. */
6741 if (qimode
== VOIDmode
)
6743 icode
= direct_optab_handler (vec_perm_optab
, qimode
);
6744 if (icode
== CODE_FOR_nothing
)
6749 /* Multiply each element by its byte size. */
6750 machine_mode selmode
= GET_MODE (sel
);
6752 sel
= expand_simple_binop (selmode
, PLUS
, sel
, sel
,
6753 NULL
, 0, OPTAB_DIRECT
);
6755 sel
= expand_simple_binop (selmode
, ASHIFT
, sel
,
6756 GEN_INT (exact_log2 (u
)),
6757 NULL
, 0, OPTAB_DIRECT
);
6758 gcc_assert (sel
!= NULL
);
6760 /* Broadcast the low byte each element into each of its bytes. */
6761 vec
= rtvec_alloc (w
);
6762 for (i
= 0; i
< w
; ++i
)
6764 int this_e
= i
/ u
* u
;
6765 if (BYTES_BIG_ENDIAN
)
6767 RTVEC_ELT (vec
, i
) = GEN_INT (this_e
);
6769 tmp
= gen_rtx_CONST_VECTOR (qimode
, vec
);
6770 sel
= gen_lowpart (qimode
, sel
);
6771 sel
= expand_vec_perm (qimode
, sel
, sel
, tmp
, NULL
);
6772 gcc_assert (sel
!= NULL
);
6774 /* Add the byte offset to each byte element. */
6775 /* Note that the definition of the indicies here is memory ordering,
6776 so there should be no difference between big and little endian. */
6777 vec
= rtvec_alloc (w
);
6778 for (i
= 0; i
< w
; ++i
)
6779 RTVEC_ELT (vec
, i
) = GEN_INT (i
% u
);
6780 tmp
= gen_rtx_CONST_VECTOR (qimode
, vec
);
6781 sel_qi
= expand_simple_binop (qimode
, PLUS
, sel
, tmp
,
6782 sel
, 0, OPTAB_DIRECT
);
6783 gcc_assert (sel_qi
!= NULL
);
6786 tmp
= mode
!= qimode
? gen_reg_rtx (qimode
) : target
;
6787 tmp
= expand_vec_perm_1 (icode
, tmp
, gen_lowpart (qimode
, v0
),
6788 gen_lowpart (qimode
, v1
), sel_qi
);
6790 tmp
= gen_lowpart (mode
, tmp
);
6794 /* Return insn code for a conditional operator with a comparison in
6795 mode CMODE, unsigned if UNS is true, resulting in a value of mode VMODE. */
6797 static inline enum insn_code
6798 get_vcond_icode (machine_mode vmode
, machine_mode cmode
, bool uns
)
6800 enum insn_code icode
= CODE_FOR_nothing
;
6802 icode
= convert_optab_handler (vcondu_optab
, vmode
, cmode
);
6804 icode
= convert_optab_handler (vcond_optab
, vmode
, cmode
);
6808 /* Return TRUE iff, appropriate vector insns are available
6809 for vector cond expr with vector type VALUE_TYPE and a comparison
6810 with operand vector types in CMP_OP_TYPE. */
6813 expand_vec_cond_expr_p (tree value_type
, tree cmp_op_type
)
6815 machine_mode value_mode
= TYPE_MODE (value_type
);
6816 machine_mode cmp_op_mode
= TYPE_MODE (cmp_op_type
);
6817 if (GET_MODE_SIZE (value_mode
) != GET_MODE_SIZE (cmp_op_mode
)
6818 || GET_MODE_NUNITS (value_mode
) != GET_MODE_NUNITS (cmp_op_mode
)
6819 || get_vcond_icode (TYPE_MODE (value_type
), TYPE_MODE (cmp_op_type
),
6820 TYPE_UNSIGNED (cmp_op_type
)) == CODE_FOR_nothing
)
6825 /* Generate insns for a VEC_COND_EXPR, given its TYPE and its
6829 expand_vec_cond_expr (tree vec_cond_type
, tree op0
, tree op1
, tree op2
,
6832 struct expand_operand ops
[6];
6833 enum insn_code icode
;
6834 rtx comparison
, rtx_op1
, rtx_op2
;
6835 machine_mode mode
= TYPE_MODE (vec_cond_type
);
6836 machine_mode cmp_op_mode
;
6839 enum tree_code tcode
;
6841 if (COMPARISON_CLASS_P (op0
))
6843 op0a
= TREE_OPERAND (op0
, 0);
6844 op0b
= TREE_OPERAND (op0
, 1);
6845 tcode
= TREE_CODE (op0
);
6850 gcc_assert (!TYPE_UNSIGNED (TREE_TYPE (op0
)));
6852 op0b
= build_zero_cst (TREE_TYPE (op0
));
6855 unsignedp
= TYPE_UNSIGNED (TREE_TYPE (op0a
));
6856 cmp_op_mode
= TYPE_MODE (TREE_TYPE (op0a
));
6859 gcc_assert (GET_MODE_SIZE (mode
) == GET_MODE_SIZE (cmp_op_mode
)
6860 && GET_MODE_NUNITS (mode
) == GET_MODE_NUNITS (cmp_op_mode
));
6862 icode
= get_vcond_icode (mode
, cmp_op_mode
, unsignedp
);
6863 if (icode
== CODE_FOR_nothing
)
6866 comparison
= vector_compare_rtx (tcode
, op0a
, op0b
, unsignedp
, icode
);
6867 rtx_op1
= expand_normal (op1
);
6868 rtx_op2
= expand_normal (op2
);
6870 create_output_operand (&ops
[0], target
, mode
);
6871 create_input_operand (&ops
[1], rtx_op1
, mode
);
6872 create_input_operand (&ops
[2], rtx_op2
, mode
);
6873 create_fixed_operand (&ops
[3], comparison
);
6874 create_fixed_operand (&ops
[4], XEXP (comparison
, 0));
6875 create_fixed_operand (&ops
[5], XEXP (comparison
, 1));
6876 expand_insn (icode
, 6, ops
);
6877 return ops
[0].value
;
6880 /* Return non-zero if a highpart multiply is supported of can be synthisized.
6881 For the benefit of expand_mult_highpart, the return value is 1 for direct,
6882 2 for even/odd widening, and 3 for hi/lo widening. */
6885 can_mult_highpart_p (machine_mode mode
, bool uns_p
)
6891 op
= uns_p
? umul_highpart_optab
: smul_highpart_optab
;
6892 if (optab_handler (op
, mode
) != CODE_FOR_nothing
)
6895 /* If the mode is an integral vector, synth from widening operations. */
6896 if (GET_MODE_CLASS (mode
) != MODE_VECTOR_INT
)
6899 nunits
= GET_MODE_NUNITS (mode
);
6900 sel
= XALLOCAVEC (unsigned char, nunits
);
6902 op
= uns_p
? vec_widen_umult_even_optab
: vec_widen_smult_even_optab
;
6903 if (optab_handler (op
, mode
) != CODE_FOR_nothing
)
6905 op
= uns_p
? vec_widen_umult_odd_optab
: vec_widen_smult_odd_optab
;
6906 if (optab_handler (op
, mode
) != CODE_FOR_nothing
)
6908 for (i
= 0; i
< nunits
; ++i
)
6909 sel
[i
] = !BYTES_BIG_ENDIAN
+ (i
& ~1) + ((i
& 1) ? nunits
: 0);
6910 if (can_vec_perm_p (mode
, false, sel
))
6915 op
= uns_p
? vec_widen_umult_hi_optab
: vec_widen_smult_hi_optab
;
6916 if (optab_handler (op
, mode
) != CODE_FOR_nothing
)
6918 op
= uns_p
? vec_widen_umult_lo_optab
: vec_widen_smult_lo_optab
;
6919 if (optab_handler (op
, mode
) != CODE_FOR_nothing
)
6921 for (i
= 0; i
< nunits
; ++i
)
6922 sel
[i
] = 2 * i
+ (BYTES_BIG_ENDIAN
? 0 : 1);
6923 if (can_vec_perm_p (mode
, false, sel
))
6931 /* Expand a highpart multiply. */
6934 expand_mult_highpart (machine_mode mode
, rtx op0
, rtx op1
,
6935 rtx target
, bool uns_p
)
6937 struct expand_operand eops
[3];
6938 enum insn_code icode
;
6939 int method
, i
, nunits
;
6945 method
= can_mult_highpart_p (mode
, uns_p
);
6951 tab1
= uns_p
? umul_highpart_optab
: smul_highpart_optab
;
6952 return expand_binop (mode
, tab1
, op0
, op1
, target
, uns_p
,
6955 tab1
= uns_p
? vec_widen_umult_even_optab
: vec_widen_smult_even_optab
;
6956 tab2
= uns_p
? vec_widen_umult_odd_optab
: vec_widen_smult_odd_optab
;
6959 tab1
= uns_p
? vec_widen_umult_lo_optab
: vec_widen_smult_lo_optab
;
6960 tab2
= uns_p
? vec_widen_umult_hi_optab
: vec_widen_smult_hi_optab
;
6961 if (BYTES_BIG_ENDIAN
)
6962 std::swap (tab1
, tab2
);
6968 icode
= optab_handler (tab1
, mode
);
6969 nunits
= GET_MODE_NUNITS (mode
);
6970 wmode
= insn_data
[icode
].operand
[0].mode
;
6971 gcc_checking_assert (2 * GET_MODE_NUNITS (wmode
) == nunits
);
6972 gcc_checking_assert (GET_MODE_SIZE (wmode
) == GET_MODE_SIZE (mode
));
6974 create_output_operand (&eops
[0], gen_reg_rtx (wmode
), wmode
);
6975 create_input_operand (&eops
[1], op0
, mode
);
6976 create_input_operand (&eops
[2], op1
, mode
);
6977 expand_insn (icode
, 3, eops
);
6978 m1
= gen_lowpart (mode
, eops
[0].value
);
6980 create_output_operand (&eops
[0], gen_reg_rtx (wmode
), wmode
);
6981 create_input_operand (&eops
[1], op0
, mode
);
6982 create_input_operand (&eops
[2], op1
, mode
);
6983 expand_insn (optab_handler (tab2
, mode
), 3, eops
);
6984 m2
= gen_lowpart (mode
, eops
[0].value
);
6986 v
= rtvec_alloc (nunits
);
6989 for (i
= 0; i
< nunits
; ++i
)
6990 RTVEC_ELT (v
, i
) = GEN_INT (!BYTES_BIG_ENDIAN
+ (i
& ~1)
6991 + ((i
& 1) ? nunits
: 0));
6995 for (i
= 0; i
< nunits
; ++i
)
6996 RTVEC_ELT (v
, i
) = GEN_INT (2 * i
+ (BYTES_BIG_ENDIAN
? 0 : 1));
6998 perm
= gen_rtx_CONST_VECTOR (mode
, v
);
7000 return expand_vec_perm (mode
, m1
, m2
, perm
, target
);
7003 /* Return true if target supports vector masked load/store for mode. */
7005 can_vec_mask_load_store_p (machine_mode mode
, bool is_load
)
7007 optab op
= is_load
? maskload_optab
: maskstore_optab
;
7009 unsigned int vector_sizes
;
7011 /* If mode is vector mode, check it directly. */
7012 if (VECTOR_MODE_P (mode
))
7013 return optab_handler (op
, mode
) != CODE_FOR_nothing
;
7015 /* Otherwise, return true if there is some vector mode with
7016 the mask load/store supported. */
7018 /* See if there is any chance the mask load or store might be
7019 vectorized. If not, punt. */
7020 vmode
= targetm
.vectorize
.preferred_simd_mode (mode
);
7021 if (!VECTOR_MODE_P (vmode
))
7024 if (optab_handler (op
, vmode
) != CODE_FOR_nothing
)
7027 vector_sizes
= targetm
.vectorize
.autovectorize_vector_sizes ();
7028 while (vector_sizes
!= 0)
7030 unsigned int cur
= 1 << floor_log2 (vector_sizes
);
7031 vector_sizes
&= ~cur
;
7032 if (cur
<= GET_MODE_SIZE (mode
))
7034 vmode
= mode_for_vector (mode
, cur
/ GET_MODE_SIZE (mode
));
7035 if (VECTOR_MODE_P (vmode
)
7036 && optab_handler (op
, vmode
) != CODE_FOR_nothing
)
7042 /* Return true if there is a compare_and_swap pattern. */
7045 can_compare_and_swap_p (machine_mode mode
, bool allow_libcall
)
7047 enum insn_code icode
;
7049 /* Check for __atomic_compare_and_swap. */
7050 icode
= direct_optab_handler (atomic_compare_and_swap_optab
, mode
);
7051 if (icode
!= CODE_FOR_nothing
)
7054 /* Check for __sync_compare_and_swap. */
7055 icode
= optab_handler (sync_compare_and_swap_optab
, mode
);
7056 if (icode
!= CODE_FOR_nothing
)
7058 if (allow_libcall
&& optab_libfunc (sync_compare_and_swap_optab
, mode
))
7061 /* No inline compare and swap. */
7065 /* Return true if an atomic exchange can be performed. */
7068 can_atomic_exchange_p (machine_mode mode
, bool allow_libcall
)
7070 enum insn_code icode
;
7072 /* Check for __atomic_exchange. */
7073 icode
= direct_optab_handler (atomic_exchange_optab
, mode
);
7074 if (icode
!= CODE_FOR_nothing
)
7077 /* Don't check __sync_test_and_set, as on some platforms that
7078 has reduced functionality. Targets that really do support
7079 a proper exchange should simply be updated to the __atomics. */
7081 return can_compare_and_swap_p (mode
, allow_libcall
);
7085 /* Helper function to find the MODE_CC set in a sync_compare_and_swap
7089 find_cc_set (rtx x
, const_rtx pat
, void *data
)
7091 if (REG_P (x
) && GET_MODE_CLASS (GET_MODE (x
)) == MODE_CC
7092 && GET_CODE (pat
) == SET
)
7094 rtx
*p_cc_reg
= (rtx
*) data
;
7095 gcc_assert (!*p_cc_reg
);
7100 /* This is a helper function for the other atomic operations. This function
7101 emits a loop that contains SEQ that iterates until a compare-and-swap
7102 operation at the end succeeds. MEM is the memory to be modified. SEQ is
7103 a set of instructions that takes a value from OLD_REG as an input and
7104 produces a value in NEW_REG as an output. Before SEQ, OLD_REG will be
7105 set to the current contents of MEM. After SEQ, a compare-and-swap will
7106 attempt to update MEM with NEW_REG. The function returns true when the
7107 loop was generated successfully. */
7110 expand_compare_and_swap_loop (rtx mem
, rtx old_reg
, rtx new_reg
, rtx seq
)
7112 machine_mode mode
= GET_MODE (mem
);
7113 rtx_code_label
*label
;
7114 rtx cmp_reg
, success
, oldval
;
7116 /* The loop we want to generate looks like
7122 (success, cmp_reg) = compare-and-swap(mem, old_reg, new_reg)
7126 Note that we only do the plain load from memory once. Subsequent
7127 iterations use the value loaded by the compare-and-swap pattern. */
7129 label
= gen_label_rtx ();
7130 cmp_reg
= gen_reg_rtx (mode
);
7132 emit_move_insn (cmp_reg
, mem
);
7134 emit_move_insn (old_reg
, cmp_reg
);
7140 if (!expand_atomic_compare_and_swap (&success
, &oldval
, mem
, old_reg
,
7141 new_reg
, false, MEMMODEL_SYNC_SEQ_CST
,
7145 if (oldval
!= cmp_reg
)
7146 emit_move_insn (cmp_reg
, oldval
);
7148 /* Mark this jump predicted not taken. */
7149 emit_cmp_and_jump_insns (success
, const0_rtx
, EQ
, const0_rtx
,
7150 GET_MODE (success
), 1, label
, 0);
7155 /* This function tries to emit an atomic_exchange intruction. VAL is written
7156 to *MEM using memory model MODEL. The previous contents of *MEM are returned,
7157 using TARGET if possible. */
7160 maybe_emit_atomic_exchange (rtx target
, rtx mem
, rtx val
, enum memmodel model
)
7162 machine_mode mode
= GET_MODE (mem
);
7163 enum insn_code icode
;
7165 /* If the target supports the exchange directly, great. */
7166 icode
= direct_optab_handler (atomic_exchange_optab
, mode
);
7167 if (icode
!= CODE_FOR_nothing
)
7169 struct expand_operand ops
[4];
7171 create_output_operand (&ops
[0], target
, mode
);
7172 create_fixed_operand (&ops
[1], mem
);
7173 create_input_operand (&ops
[2], val
, mode
);
7174 create_integer_operand (&ops
[3], model
);
7175 if (maybe_expand_insn (icode
, 4, ops
))
7176 return ops
[0].value
;
7182 /* This function tries to implement an atomic exchange operation using
7183 __sync_lock_test_and_set. VAL is written to *MEM using memory model MODEL.
7184 The previous contents of *MEM are returned, using TARGET if possible.
7185 Since this instructionn is an acquire barrier only, stronger memory
7186 models may require additional barriers to be emitted. */
7189 maybe_emit_sync_lock_test_and_set (rtx target
, rtx mem
, rtx val
,
7190 enum memmodel model
)
7192 machine_mode mode
= GET_MODE (mem
);
7193 enum insn_code icode
;
7194 rtx_insn
*last_insn
= get_last_insn ();
7196 icode
= optab_handler (sync_lock_test_and_set_optab
, mode
);
7198 /* Legacy sync_lock_test_and_set is an acquire barrier. If the pattern
7199 exists, and the memory model is stronger than acquire, add a release
7200 barrier before the instruction. */
7202 if (is_mm_seq_cst (model
) || is_mm_release (model
) || is_mm_acq_rel (model
))
7203 expand_mem_thread_fence (model
);
7205 if (icode
!= CODE_FOR_nothing
)
7207 struct expand_operand ops
[3];
7208 create_output_operand (&ops
[0], target
, mode
);
7209 create_fixed_operand (&ops
[1], mem
);
7210 create_input_operand (&ops
[2], val
, mode
);
7211 if (maybe_expand_insn (icode
, 3, ops
))
7212 return ops
[0].value
;
7215 /* If an external test-and-set libcall is provided, use that instead of
7216 any external compare-and-swap that we might get from the compare-and-
7217 swap-loop expansion later. */
7218 if (!can_compare_and_swap_p (mode
, false))
7220 rtx libfunc
= optab_libfunc (sync_lock_test_and_set_optab
, mode
);
7221 if (libfunc
!= NULL
)
7225 addr
= convert_memory_address (ptr_mode
, XEXP (mem
, 0));
7226 return emit_library_call_value (libfunc
, NULL_RTX
, LCT_NORMAL
,
7227 mode
, 2, addr
, ptr_mode
,
7232 /* If the test_and_set can't be emitted, eliminate any barrier that might
7233 have been emitted. */
7234 delete_insns_since (last_insn
);
7238 /* This function tries to implement an atomic exchange operation using a
7239 compare_and_swap loop. VAL is written to *MEM. The previous contents of
7240 *MEM are returned, using TARGET if possible. No memory model is required
7241 since a compare_and_swap loop is seq-cst. */
7244 maybe_emit_compare_and_swap_exchange_loop (rtx target
, rtx mem
, rtx val
)
7246 machine_mode mode
= GET_MODE (mem
);
7248 if (can_compare_and_swap_p (mode
, true))
7250 if (!target
|| !register_operand (target
, mode
))
7251 target
= gen_reg_rtx (mode
);
7252 if (expand_compare_and_swap_loop (mem
, target
, val
, NULL_RTX
))
7259 /* This function tries to implement an atomic test-and-set operation
7260 using the atomic_test_and_set instruction pattern. A boolean value
7261 is returned from the operation, using TARGET if possible. */
7263 #ifndef HAVE_atomic_test_and_set
7264 #define HAVE_atomic_test_and_set 0
7265 #define CODE_FOR_atomic_test_and_set CODE_FOR_nothing
7269 maybe_emit_atomic_test_and_set (rtx target
, rtx mem
, enum memmodel model
)
7271 machine_mode pat_bool_mode
;
7272 struct expand_operand ops
[3];
7274 if (!HAVE_atomic_test_and_set
)
7277 /* While we always get QImode from __atomic_test_and_set, we get
7278 other memory modes from __sync_lock_test_and_set. Note that we
7279 use no endian adjustment here. This matches the 4.6 behavior
7280 in the Sparc backend. */
7282 (insn_data
[CODE_FOR_atomic_test_and_set
].operand
[1].mode
== QImode
);
7283 if (GET_MODE (mem
) != QImode
)
7284 mem
= adjust_address_nv (mem
, QImode
, 0);
7286 pat_bool_mode
= insn_data
[CODE_FOR_atomic_test_and_set
].operand
[0].mode
;
7287 create_output_operand (&ops
[0], target
, pat_bool_mode
);
7288 create_fixed_operand (&ops
[1], mem
);
7289 create_integer_operand (&ops
[2], model
);
7291 if (maybe_expand_insn (CODE_FOR_atomic_test_and_set
, 3, ops
))
7292 return ops
[0].value
;
7296 /* This function expands the legacy _sync_lock test_and_set operation which is
7297 generally an atomic exchange. Some limited targets only allow the
7298 constant 1 to be stored. This is an ACQUIRE operation.
7300 TARGET is an optional place to stick the return value.
7301 MEM is where VAL is stored. */
7304 expand_sync_lock_test_and_set (rtx target
, rtx mem
, rtx val
)
7308 /* Try an atomic_exchange first. */
7309 ret
= maybe_emit_atomic_exchange (target
, mem
, val
, MEMMODEL_SYNC_ACQUIRE
);
7313 ret
= maybe_emit_sync_lock_test_and_set (target
, mem
, val
,
7314 MEMMODEL_SYNC_ACQUIRE
);
7318 ret
= maybe_emit_compare_and_swap_exchange_loop (target
, mem
, val
);
7322 /* If there are no other options, try atomic_test_and_set if the value
7323 being stored is 1. */
7324 if (val
== const1_rtx
)
7325 ret
= maybe_emit_atomic_test_and_set (target
, mem
, MEMMODEL_SYNC_ACQUIRE
);
7330 /* This function expands the atomic test_and_set operation:
7331 atomically store a boolean TRUE into MEM and return the previous value.
7333 MEMMODEL is the memory model variant to use.
7334 TARGET is an optional place to stick the return value. */
7337 expand_atomic_test_and_set (rtx target
, rtx mem
, enum memmodel model
)
7339 machine_mode mode
= GET_MODE (mem
);
7340 rtx ret
, trueval
, subtarget
;
7342 ret
= maybe_emit_atomic_test_and_set (target
, mem
, model
);
7346 /* Be binary compatible with non-default settings of trueval, and different
7347 cpu revisions. E.g. one revision may have atomic-test-and-set, but
7348 another only has atomic-exchange. */
7349 if (targetm
.atomic_test_and_set_trueval
== 1)
7351 trueval
= const1_rtx
;
7352 subtarget
= target
? target
: gen_reg_rtx (mode
);
7356 trueval
= gen_int_mode (targetm
.atomic_test_and_set_trueval
, mode
);
7357 subtarget
= gen_reg_rtx (mode
);
7360 /* Try the atomic-exchange optab... */
7361 ret
= maybe_emit_atomic_exchange (subtarget
, mem
, trueval
, model
);
7363 /* ... then an atomic-compare-and-swap loop ... */
7365 ret
= maybe_emit_compare_and_swap_exchange_loop (subtarget
, mem
, trueval
);
7367 /* ... before trying the vaguely defined legacy lock_test_and_set. */
7369 ret
= maybe_emit_sync_lock_test_and_set (subtarget
, mem
, trueval
, model
);
7371 /* Recall that the legacy lock_test_and_set optab was allowed to do magic
7372 things with the value 1. Thus we try again without trueval. */
7373 if (!ret
&& targetm
.atomic_test_and_set_trueval
!= 1)
7374 ret
= maybe_emit_sync_lock_test_and_set (subtarget
, mem
, const1_rtx
, model
);
7376 /* Failing all else, assume a single threaded environment and simply
7377 perform the operation. */
7380 /* If the result is ignored skip the move to target. */
7381 if (subtarget
!= const0_rtx
)
7382 emit_move_insn (subtarget
, mem
);
7384 emit_move_insn (mem
, trueval
);
7388 /* Recall that have to return a boolean value; rectify if trueval
7389 is not exactly one. */
7390 if (targetm
.atomic_test_and_set_trueval
!= 1)
7391 ret
= emit_store_flag_force (target
, NE
, ret
, const0_rtx
, mode
, 0, 1);
7396 /* This function expands the atomic exchange operation:
7397 atomically store VAL in MEM and return the previous value in MEM.
7399 MEMMODEL is the memory model variant to use.
7400 TARGET is an optional place to stick the return value. */
7403 expand_atomic_exchange (rtx target
, rtx mem
, rtx val
, enum memmodel model
)
7407 ret
= maybe_emit_atomic_exchange (target
, mem
, val
, model
);
7409 /* Next try a compare-and-swap loop for the exchange. */
7411 ret
= maybe_emit_compare_and_swap_exchange_loop (target
, mem
, val
);
7416 /* This function expands the atomic compare exchange operation:
7418 *PTARGET_BOOL is an optional place to store the boolean success/failure.
7419 *PTARGET_OVAL is an optional place to store the old value from memory.
7420 Both target parameters may be NULL to indicate that we do not care about
7421 that return value. Both target parameters are updated on success to
7422 the actual location of the corresponding result.
7424 MEMMODEL is the memory model variant to use.
7426 The return value of the function is true for success. */
7429 expand_atomic_compare_and_swap (rtx
*ptarget_bool
, rtx
*ptarget_oval
,
7430 rtx mem
, rtx expected
, rtx desired
,
7431 bool is_weak
, enum memmodel succ_model
,
7432 enum memmodel fail_model
)
7434 machine_mode mode
= GET_MODE (mem
);
7435 struct expand_operand ops
[8];
7436 enum insn_code icode
;
7437 rtx target_oval
, target_bool
= NULL_RTX
;
7440 /* Load expected into a register for the compare and swap. */
7441 if (MEM_P (expected
))
7442 expected
= copy_to_reg (expected
);
7444 /* Make sure we always have some place to put the return oldval.
7445 Further, make sure that place is distinct from the input expected,
7446 just in case we need that path down below. */
7447 if (ptarget_oval
== NULL
7448 || (target_oval
= *ptarget_oval
) == NULL
7449 || reg_overlap_mentioned_p (expected
, target_oval
))
7450 target_oval
= gen_reg_rtx (mode
);
7452 icode
= direct_optab_handler (atomic_compare_and_swap_optab
, mode
);
7453 if (icode
!= CODE_FOR_nothing
)
7455 machine_mode bool_mode
= insn_data
[icode
].operand
[0].mode
;
7457 /* Make sure we always have a place for the bool operand. */
7458 if (ptarget_bool
== NULL
7459 || (target_bool
= *ptarget_bool
) == NULL
7460 || GET_MODE (target_bool
) != bool_mode
)
7461 target_bool
= gen_reg_rtx (bool_mode
);
7463 /* Emit the compare_and_swap. */
7464 create_output_operand (&ops
[0], target_bool
, bool_mode
);
7465 create_output_operand (&ops
[1], target_oval
, mode
);
7466 create_fixed_operand (&ops
[2], mem
);
7467 create_input_operand (&ops
[3], expected
, mode
);
7468 create_input_operand (&ops
[4], desired
, mode
);
7469 create_integer_operand (&ops
[5], is_weak
);
7470 create_integer_operand (&ops
[6], succ_model
);
7471 create_integer_operand (&ops
[7], fail_model
);
7472 if (maybe_expand_insn (icode
, 8, ops
))
7474 /* Return success/failure. */
7475 target_bool
= ops
[0].value
;
7476 target_oval
= ops
[1].value
;
7481 /* Otherwise fall back to the original __sync_val_compare_and_swap
7482 which is always seq-cst. */
7483 icode
= optab_handler (sync_compare_and_swap_optab
, mode
);
7484 if (icode
!= CODE_FOR_nothing
)
7488 create_output_operand (&ops
[0], target_oval
, mode
);
7489 create_fixed_operand (&ops
[1], mem
);
7490 create_input_operand (&ops
[2], expected
, mode
);
7491 create_input_operand (&ops
[3], desired
, mode
);
7492 if (!maybe_expand_insn (icode
, 4, ops
))
7495 target_oval
= ops
[0].value
;
7497 /* If the caller isn't interested in the boolean return value,
7498 skip the computation of it. */
7499 if (ptarget_bool
== NULL
)
7502 /* Otherwise, work out if the compare-and-swap succeeded. */
7504 if (have_insn_for (COMPARE
, CCmode
))
7505 note_stores (PATTERN (get_last_insn ()), find_cc_set
, &cc_reg
);
7508 target_bool
= emit_store_flag_force (target_bool
, EQ
, cc_reg
,
7509 const0_rtx
, VOIDmode
, 0, 1);
7512 goto success_bool_from_val
;
7515 /* Also check for library support for __sync_val_compare_and_swap. */
7516 libfunc
= optab_libfunc (sync_compare_and_swap_optab
, mode
);
7517 if (libfunc
!= NULL
)
7519 rtx addr
= convert_memory_address (ptr_mode
, XEXP (mem
, 0));
7520 target_oval
= emit_library_call_value (libfunc
, NULL_RTX
, LCT_NORMAL
,
7521 mode
, 3, addr
, ptr_mode
,
7522 expected
, mode
, desired
, mode
);
7524 /* Compute the boolean return value only if requested. */
7526 goto success_bool_from_val
;
7534 success_bool_from_val
:
7535 target_bool
= emit_store_flag_force (target_bool
, EQ
, target_oval
,
7536 expected
, VOIDmode
, 1, 1);
7538 /* Make sure that the oval output winds up where the caller asked. */
7540 *ptarget_oval
= target_oval
;
7542 *ptarget_bool
= target_bool
;
7546 /* Generate asm volatile("" : : : "memory") as the memory barrier. */
7549 expand_asm_memory_barrier (void)
7553 asm_op
= gen_rtx_ASM_OPERANDS (VOIDmode
, empty_string
, empty_string
, 0,
7554 rtvec_alloc (0), rtvec_alloc (0),
7555 rtvec_alloc (0), UNKNOWN_LOCATION
);
7556 MEM_VOLATILE_P (asm_op
) = 1;
7558 clob
= gen_rtx_SCRATCH (VOIDmode
);
7559 clob
= gen_rtx_MEM (BLKmode
, clob
);
7560 clob
= gen_rtx_CLOBBER (VOIDmode
, clob
);
7562 emit_insn (gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, asm_op
, clob
)));
7565 /* This routine will either emit the mem_thread_fence pattern or issue a
7566 sync_synchronize to generate a fence for memory model MEMMODEL. */
7569 expand_mem_thread_fence (enum memmodel model
)
7571 if (targetm
.have_mem_thread_fence ())
7572 emit_insn (targetm
.gen_mem_thread_fence (GEN_INT (model
)));
7573 else if (!is_mm_relaxed (model
))
7575 if (targetm
.have_memory_barrier ())
7576 emit_insn (targetm
.gen_memory_barrier ());
7577 else if (synchronize_libfunc
!= NULL_RTX
)
7578 emit_library_call (synchronize_libfunc
, LCT_NORMAL
, VOIDmode
, 0);
7580 expand_asm_memory_barrier ();
7584 /* This routine will either emit the mem_signal_fence pattern or issue a
7585 sync_synchronize to generate a fence for memory model MEMMODEL. */
7588 expand_mem_signal_fence (enum memmodel model
)
7590 if (targetm
.have_mem_signal_fence ())
7591 emit_insn (targetm
.gen_mem_signal_fence (GEN_INT (model
)));
7592 else if (!is_mm_relaxed (model
))
7594 /* By default targets are coherent between a thread and the signal
7595 handler running on the same thread. Thus this really becomes a
7596 compiler barrier, in that stores must not be sunk past
7597 (or raised above) a given point. */
7598 expand_asm_memory_barrier ();
7602 /* This function expands the atomic load operation:
7603 return the atomically loaded value in MEM.
7605 MEMMODEL is the memory model variant to use.
7606 TARGET is an option place to stick the return value. */
7609 expand_atomic_load (rtx target
, rtx mem
, enum memmodel model
)
7611 machine_mode mode
= GET_MODE (mem
);
7612 enum insn_code icode
;
7614 /* If the target supports the load directly, great. */
7615 icode
= direct_optab_handler (atomic_load_optab
, mode
);
7616 if (icode
!= CODE_FOR_nothing
)
7618 struct expand_operand ops
[3];
7620 create_output_operand (&ops
[0], target
, mode
);
7621 create_fixed_operand (&ops
[1], mem
);
7622 create_integer_operand (&ops
[2], model
);
7623 if (maybe_expand_insn (icode
, 3, ops
))
7624 return ops
[0].value
;
7627 /* If the size of the object is greater than word size on this target,
7628 then we assume that a load will not be atomic. */
7629 if (GET_MODE_PRECISION (mode
) > BITS_PER_WORD
)
7631 /* Issue val = compare_and_swap (mem, 0, 0).
7632 This may cause the occasional harmless store of 0 when the value is
7633 already 0, but it seems to be OK according to the standards guys. */
7634 if (expand_atomic_compare_and_swap (NULL
, &target
, mem
, const0_rtx
,
7635 const0_rtx
, false, model
, model
))
7638 /* Otherwise there is no atomic load, leave the library call. */
7642 /* Otherwise assume loads are atomic, and emit the proper barriers. */
7643 if (!target
|| target
== const0_rtx
)
7644 target
= gen_reg_rtx (mode
);
7646 /* For SEQ_CST, emit a barrier before the load. */
7647 if (is_mm_seq_cst (model
))
7648 expand_mem_thread_fence (model
);
7650 emit_move_insn (target
, mem
);
7652 /* Emit the appropriate barrier after the load. */
7653 expand_mem_thread_fence (model
);
7658 /* This function expands the atomic store operation:
7659 Atomically store VAL in MEM.
7660 MEMMODEL is the memory model variant to use.
7661 USE_RELEASE is true if __sync_lock_release can be used as a fall back.
7662 function returns const0_rtx if a pattern was emitted. */
7665 expand_atomic_store (rtx mem
, rtx val
, enum memmodel model
, bool use_release
)
7667 machine_mode mode
= GET_MODE (mem
);
7668 enum insn_code icode
;
7669 struct expand_operand ops
[3];
7671 /* If the target supports the store directly, great. */
7672 icode
= direct_optab_handler (atomic_store_optab
, mode
);
7673 if (icode
!= CODE_FOR_nothing
)
7675 create_fixed_operand (&ops
[0], mem
);
7676 create_input_operand (&ops
[1], val
, mode
);
7677 create_integer_operand (&ops
[2], model
);
7678 if (maybe_expand_insn (icode
, 3, ops
))
7682 /* If using __sync_lock_release is a viable alternative, try it. */
7685 icode
= direct_optab_handler (sync_lock_release_optab
, mode
);
7686 if (icode
!= CODE_FOR_nothing
)
7688 create_fixed_operand (&ops
[0], mem
);
7689 create_input_operand (&ops
[1], const0_rtx
, mode
);
7690 if (maybe_expand_insn (icode
, 2, ops
))
7692 /* lock_release is only a release barrier. */
7693 if (is_mm_seq_cst (model
))
7694 expand_mem_thread_fence (model
);
7700 /* If the size of the object is greater than word size on this target,
7701 a default store will not be atomic, Try a mem_exchange and throw away
7702 the result. If that doesn't work, don't do anything. */
7703 if (GET_MODE_PRECISION (mode
) > BITS_PER_WORD
)
7705 rtx target
= maybe_emit_atomic_exchange (NULL_RTX
, mem
, val
, model
);
7707 target
= maybe_emit_compare_and_swap_exchange_loop (NULL_RTX
, mem
, val
);
7714 /* Otherwise assume stores are atomic, and emit the proper barriers. */
7715 expand_mem_thread_fence (model
);
7717 emit_move_insn (mem
, val
);
7719 /* For SEQ_CST, also emit a barrier after the store. */
7720 if (is_mm_seq_cst (model
))
7721 expand_mem_thread_fence (model
);
7727 /* Structure containing the pointers and values required to process the
7728 various forms of the atomic_fetch_op and atomic_op_fetch builtins. */
7730 struct atomic_op_functions
7732 direct_optab mem_fetch_before
;
7733 direct_optab mem_fetch_after
;
7734 direct_optab mem_no_result
;
7737 direct_optab no_result
;
7738 enum rtx_code reverse_code
;
7742 /* Fill in structure pointed to by OP with the various optab entries for an
7743 operation of type CODE. */
7746 get_atomic_op_for_code (struct atomic_op_functions
*op
, enum rtx_code code
)
7748 gcc_assert (op
!= NULL
);
7750 /* If SWITCHABLE_TARGET is defined, then subtargets can be switched
7751 in the source code during compilation, and the optab entries are not
7752 computable until runtime. Fill in the values at runtime. */
7756 op
->mem_fetch_before
= atomic_fetch_add_optab
;
7757 op
->mem_fetch_after
= atomic_add_fetch_optab
;
7758 op
->mem_no_result
= atomic_add_optab
;
7759 op
->fetch_before
= sync_old_add_optab
;
7760 op
->fetch_after
= sync_new_add_optab
;
7761 op
->no_result
= sync_add_optab
;
7762 op
->reverse_code
= MINUS
;
7765 op
->mem_fetch_before
= atomic_fetch_sub_optab
;
7766 op
->mem_fetch_after
= atomic_sub_fetch_optab
;
7767 op
->mem_no_result
= atomic_sub_optab
;
7768 op
->fetch_before
= sync_old_sub_optab
;
7769 op
->fetch_after
= sync_new_sub_optab
;
7770 op
->no_result
= sync_sub_optab
;
7771 op
->reverse_code
= PLUS
;
7774 op
->mem_fetch_before
= atomic_fetch_xor_optab
;
7775 op
->mem_fetch_after
= atomic_xor_fetch_optab
;
7776 op
->mem_no_result
= atomic_xor_optab
;
7777 op
->fetch_before
= sync_old_xor_optab
;
7778 op
->fetch_after
= sync_new_xor_optab
;
7779 op
->no_result
= sync_xor_optab
;
7780 op
->reverse_code
= XOR
;
7783 op
->mem_fetch_before
= atomic_fetch_and_optab
;
7784 op
->mem_fetch_after
= atomic_and_fetch_optab
;
7785 op
->mem_no_result
= atomic_and_optab
;
7786 op
->fetch_before
= sync_old_and_optab
;
7787 op
->fetch_after
= sync_new_and_optab
;
7788 op
->no_result
= sync_and_optab
;
7789 op
->reverse_code
= UNKNOWN
;
7792 op
->mem_fetch_before
= atomic_fetch_or_optab
;
7793 op
->mem_fetch_after
= atomic_or_fetch_optab
;
7794 op
->mem_no_result
= atomic_or_optab
;
7795 op
->fetch_before
= sync_old_ior_optab
;
7796 op
->fetch_after
= sync_new_ior_optab
;
7797 op
->no_result
= sync_ior_optab
;
7798 op
->reverse_code
= UNKNOWN
;
7801 op
->mem_fetch_before
= atomic_fetch_nand_optab
;
7802 op
->mem_fetch_after
= atomic_nand_fetch_optab
;
7803 op
->mem_no_result
= atomic_nand_optab
;
7804 op
->fetch_before
= sync_old_nand_optab
;
7805 op
->fetch_after
= sync_new_nand_optab
;
7806 op
->no_result
= sync_nand_optab
;
7807 op
->reverse_code
= UNKNOWN
;
7814 /* See if there is a more optimal way to implement the operation "*MEM CODE VAL"
7815 using memory order MODEL. If AFTER is true the operation needs to return
7816 the value of *MEM after the operation, otherwise the previous value.
7817 TARGET is an optional place to place the result. The result is unused if
7819 Return the result if there is a better sequence, otherwise NULL_RTX. */
7822 maybe_optimize_fetch_op (rtx target
, rtx mem
, rtx val
, enum rtx_code code
,
7823 enum memmodel model
, bool after
)
7825 /* If the value is prefetched, or not used, it may be possible to replace
7826 the sequence with a native exchange operation. */
7827 if (!after
|| target
== const0_rtx
)
7829 /* fetch_and (&x, 0, m) can be replaced with exchange (&x, 0, m). */
7830 if (code
== AND
&& val
== const0_rtx
)
7832 if (target
== const0_rtx
)
7833 target
= gen_reg_rtx (GET_MODE (mem
));
7834 return maybe_emit_atomic_exchange (target
, mem
, val
, model
);
7837 /* fetch_or (&x, -1, m) can be replaced with exchange (&x, -1, m). */
7838 if (code
== IOR
&& val
== constm1_rtx
)
7840 if (target
== const0_rtx
)
7841 target
= gen_reg_rtx (GET_MODE (mem
));
7842 return maybe_emit_atomic_exchange (target
, mem
, val
, model
);
7849 /* Try to emit an instruction for a specific operation varaition.
7850 OPTAB contains the OP functions.
7851 TARGET is an optional place to return the result. const0_rtx means unused.
7852 MEM is the memory location to operate on.
7853 VAL is the value to use in the operation.
7854 USE_MEMMODEL is TRUE if the variation with a memory model should be tried.
7855 MODEL is the memory model, if used.
7856 AFTER is true if the returned result is the value after the operation. */
7859 maybe_emit_op (const struct atomic_op_functions
*optab
, rtx target
, rtx mem
,
7860 rtx val
, bool use_memmodel
, enum memmodel model
, bool after
)
7862 machine_mode mode
= GET_MODE (mem
);
7863 struct expand_operand ops
[4];
7864 enum insn_code icode
;
7868 /* Check to see if there is a result returned. */
7869 if (target
== const0_rtx
)
7873 icode
= direct_optab_handler (optab
->mem_no_result
, mode
);
7874 create_integer_operand (&ops
[2], model
);
7879 icode
= direct_optab_handler (optab
->no_result
, mode
);
7883 /* Otherwise, we need to generate a result. */
7888 icode
= direct_optab_handler (after
? optab
->mem_fetch_after
7889 : optab
->mem_fetch_before
, mode
);
7890 create_integer_operand (&ops
[3], model
);
7895 icode
= optab_handler (after
? optab
->fetch_after
7896 : optab
->fetch_before
, mode
);
7899 create_output_operand (&ops
[op_counter
++], target
, mode
);
7901 if (icode
== CODE_FOR_nothing
)
7904 create_fixed_operand (&ops
[op_counter
++], mem
);
7905 /* VAL may have been promoted to a wider mode. Shrink it if so. */
7906 create_convert_operand_to (&ops
[op_counter
++], val
, mode
, true);
7908 if (maybe_expand_insn (icode
, num_ops
, ops
))
7909 return (target
== const0_rtx
? const0_rtx
: ops
[0].value
);
7915 /* This function expands an atomic fetch_OP or OP_fetch operation:
7916 TARGET is an option place to stick the return value. const0_rtx indicates
7917 the result is unused.
7918 atomically fetch MEM, perform the operation with VAL and return it to MEM.
7919 CODE is the operation being performed (OP)
7920 MEMMODEL is the memory model variant to use.
7921 AFTER is true to return the result of the operation (OP_fetch).
7922 AFTER is false to return the value before the operation (fetch_OP).
7924 This function will *only* generate instructions if there is a direct
7925 optab. No compare and swap loops or libcalls will be generated. */
7928 expand_atomic_fetch_op_no_fallback (rtx target
, rtx mem
, rtx val
,
7929 enum rtx_code code
, enum memmodel model
,
7932 machine_mode mode
= GET_MODE (mem
);
7933 struct atomic_op_functions optab
;
7935 bool unused_result
= (target
== const0_rtx
);
7937 get_atomic_op_for_code (&optab
, code
);
7939 /* Check to see if there are any better instructions. */
7940 result
= maybe_optimize_fetch_op (target
, mem
, val
, code
, model
, after
);
7944 /* Check for the case where the result isn't used and try those patterns. */
7947 /* Try the memory model variant first. */
7948 result
= maybe_emit_op (&optab
, target
, mem
, val
, true, model
, true);
7952 /* Next try the old style withuot a memory model. */
7953 result
= maybe_emit_op (&optab
, target
, mem
, val
, false, model
, true);
7957 /* There is no no-result pattern, so try patterns with a result. */
7961 /* Try the __atomic version. */
7962 result
= maybe_emit_op (&optab
, target
, mem
, val
, true, model
, after
);
7966 /* Try the older __sync version. */
7967 result
= maybe_emit_op (&optab
, target
, mem
, val
, false, model
, after
);
7971 /* If the fetch value can be calculated from the other variation of fetch,
7972 try that operation. */
7973 if (after
|| unused_result
|| optab
.reverse_code
!= UNKNOWN
)
7975 /* Try the __atomic version, then the older __sync version. */
7976 result
= maybe_emit_op (&optab
, target
, mem
, val
, true, model
, !after
);
7978 result
= maybe_emit_op (&optab
, target
, mem
, val
, false, model
, !after
);
7982 /* If the result isn't used, no need to do compensation code. */
7986 /* Issue compensation code. Fetch_after == fetch_before OP val.
7987 Fetch_before == after REVERSE_OP val. */
7989 code
= optab
.reverse_code
;
7992 result
= expand_simple_binop (mode
, AND
, result
, val
, NULL_RTX
,
7993 true, OPTAB_LIB_WIDEN
);
7994 result
= expand_simple_unop (mode
, NOT
, result
, target
, true);
7997 result
= expand_simple_binop (mode
, code
, result
, val
, target
,
7998 true, OPTAB_LIB_WIDEN
);
8003 /* No direct opcode can be generated. */
8009 /* This function expands an atomic fetch_OP or OP_fetch operation:
8010 TARGET is an option place to stick the return value. const0_rtx indicates
8011 the result is unused.
8012 atomically fetch MEM, perform the operation with VAL and return it to MEM.
8013 CODE is the operation being performed (OP)
8014 MEMMODEL is the memory model variant to use.
8015 AFTER is true to return the result of the operation (OP_fetch).
8016 AFTER is false to return the value before the operation (fetch_OP). */
8018 expand_atomic_fetch_op (rtx target
, rtx mem
, rtx val
, enum rtx_code code
,
8019 enum memmodel model
, bool after
)
8021 machine_mode mode
= GET_MODE (mem
);
8023 bool unused_result
= (target
== const0_rtx
);
8025 result
= expand_atomic_fetch_op_no_fallback (target
, mem
, val
, code
, model
,
8031 /* Add/sub can be implemented by doing the reverse operation with -(val). */
8032 if (code
== PLUS
|| code
== MINUS
)
8035 enum rtx_code reverse
= (code
== PLUS
? MINUS
: PLUS
);
8038 tmp
= expand_simple_unop (mode
, NEG
, val
, NULL_RTX
, true);
8039 result
= expand_atomic_fetch_op_no_fallback (target
, mem
, tmp
, reverse
,
8043 /* PLUS worked so emit the insns and return. */
8050 /* PLUS did not work, so throw away the negation code and continue. */
8054 /* Try the __sync libcalls only if we can't do compare-and-swap inline. */
8055 if (!can_compare_and_swap_p (mode
, false))
8059 enum rtx_code orig_code
= code
;
8060 struct atomic_op_functions optab
;
8062 get_atomic_op_for_code (&optab
, code
);
8063 libfunc
= optab_libfunc (after
? optab
.fetch_after
8064 : optab
.fetch_before
, mode
);
8066 && (after
|| unused_result
|| optab
.reverse_code
!= UNKNOWN
))
8070 code
= optab
.reverse_code
;
8071 libfunc
= optab_libfunc (after
? optab
.fetch_before
8072 : optab
.fetch_after
, mode
);
8074 if (libfunc
!= NULL
)
8076 rtx addr
= convert_memory_address (ptr_mode
, XEXP (mem
, 0));
8077 result
= emit_library_call_value (libfunc
, NULL
, LCT_NORMAL
, mode
,
8078 2, addr
, ptr_mode
, val
, mode
);
8080 if (!unused_result
&& fixup
)
8081 result
= expand_simple_binop (mode
, code
, result
, val
, target
,
8082 true, OPTAB_LIB_WIDEN
);
8086 /* We need the original code for any further attempts. */
8090 /* If nothing else has succeeded, default to a compare and swap loop. */
8091 if (can_compare_and_swap_p (mode
, true))
8094 rtx t0
= gen_reg_rtx (mode
), t1
;
8098 /* If the result is used, get a register for it. */
8101 if (!target
|| !register_operand (target
, mode
))
8102 target
= gen_reg_rtx (mode
);
8103 /* If fetch_before, copy the value now. */
8105 emit_move_insn (target
, t0
);
8108 target
= const0_rtx
;
8113 t1
= expand_simple_binop (mode
, AND
, t1
, val
, NULL_RTX
,
8114 true, OPTAB_LIB_WIDEN
);
8115 t1
= expand_simple_unop (mode
, code
, t1
, NULL_RTX
, true);
8118 t1
= expand_simple_binop (mode
, code
, t1
, val
, NULL_RTX
, true,
8121 /* For after, copy the value now. */
8122 if (!unused_result
&& after
)
8123 emit_move_insn (target
, t1
);
8124 insn
= get_insns ();
8127 if (t1
!= NULL
&& expand_compare_and_swap_loop (mem
, t0
, t1
, insn
))
8134 /* Return true if OPERAND is suitable for operand number OPNO of
8135 instruction ICODE. */
8138 insn_operand_matches (enum insn_code icode
, unsigned int opno
, rtx operand
)
8140 return (!insn_data
[(int) icode
].operand
[opno
].predicate
8141 || (insn_data
[(int) icode
].operand
[opno
].predicate
8142 (operand
, insn_data
[(int) icode
].operand
[opno
].mode
)));
8145 /* TARGET is a target of a multiword operation that we are going to
8146 implement as a series of word-mode operations. Return true if
8147 TARGET is suitable for this purpose. */
8150 valid_multiword_target_p (rtx target
)
8155 mode
= GET_MODE (target
);
8156 for (i
= 0; i
< GET_MODE_SIZE (mode
); i
+= UNITS_PER_WORD
)
8157 if (!validate_subreg (word_mode
, mode
, target
, i
))
8162 /* Like maybe_legitimize_operand, but do not change the code of the
8163 current rtx value. */
8166 maybe_legitimize_operand_same_code (enum insn_code icode
, unsigned int opno
,
8167 struct expand_operand
*op
)
8169 /* See if the operand matches in its current form. */
8170 if (insn_operand_matches (icode
, opno
, op
->value
))
8173 /* If the operand is a memory whose address has no side effects,
8174 try forcing the address into a non-virtual pseudo register.
8175 The check for side effects is important because copy_to_mode_reg
8176 cannot handle things like auto-modified addresses. */
8177 if (insn_data
[(int) icode
].operand
[opno
].allows_mem
&& MEM_P (op
->value
))
8182 addr
= XEXP (mem
, 0);
8183 if (!(REG_P (addr
) && REGNO (addr
) > LAST_VIRTUAL_REGISTER
)
8184 && !side_effects_p (addr
))
8189 last
= get_last_insn ();
8190 mode
= get_address_mode (mem
);
8191 mem
= replace_equiv_address (mem
, copy_to_mode_reg (mode
, addr
));
8192 if (insn_operand_matches (icode
, opno
, mem
))
8197 delete_insns_since (last
);
8204 /* Try to make OP match operand OPNO of instruction ICODE. Return true
8205 on success, storing the new operand value back in OP. */
8208 maybe_legitimize_operand (enum insn_code icode
, unsigned int opno
,
8209 struct expand_operand
*op
)
8211 machine_mode mode
, imode
;
8212 bool old_volatile_ok
, result
;
8218 old_volatile_ok
= volatile_ok
;
8220 result
= maybe_legitimize_operand_same_code (icode
, opno
, op
);
8221 volatile_ok
= old_volatile_ok
;
8225 gcc_assert (mode
!= VOIDmode
);
8227 && op
->value
!= const0_rtx
8228 && GET_MODE (op
->value
) == mode
8229 && maybe_legitimize_operand_same_code (icode
, opno
, op
))
8232 op
->value
= gen_reg_rtx (mode
);
8237 gcc_assert (mode
!= VOIDmode
);
8238 gcc_assert (GET_MODE (op
->value
) == VOIDmode
8239 || GET_MODE (op
->value
) == mode
);
8240 if (maybe_legitimize_operand_same_code (icode
, opno
, op
))
8243 op
->value
= copy_to_mode_reg (mode
, op
->value
);
8246 case EXPAND_CONVERT_TO
:
8247 gcc_assert (mode
!= VOIDmode
);
8248 op
->value
= convert_to_mode (mode
, op
->value
, op
->unsigned_p
);
8251 case EXPAND_CONVERT_FROM
:
8252 if (GET_MODE (op
->value
) != VOIDmode
)
8253 mode
= GET_MODE (op
->value
);
8255 /* The caller must tell us what mode this value has. */
8256 gcc_assert (mode
!= VOIDmode
);
8258 imode
= insn_data
[(int) icode
].operand
[opno
].mode
;
8259 if (imode
!= VOIDmode
&& imode
!= mode
)
8261 op
->value
= convert_modes (imode
, mode
, op
->value
, op
->unsigned_p
);
8266 case EXPAND_ADDRESS
:
8267 gcc_assert (mode
!= VOIDmode
);
8268 op
->value
= convert_memory_address (mode
, op
->value
);
8271 case EXPAND_INTEGER
:
8272 mode
= insn_data
[(int) icode
].operand
[opno
].mode
;
8273 if (mode
!= VOIDmode
&& const_int_operand (op
->value
, mode
))
8277 return insn_operand_matches (icode
, opno
, op
->value
);
8280 /* Make OP describe an input operand that should have the same value
8281 as VALUE, after any mode conversion that the target might request.
8282 TYPE is the type of VALUE. */
8285 create_convert_operand_from_type (struct expand_operand
*op
,
8286 rtx value
, tree type
)
8288 create_convert_operand_from (op
, value
, TYPE_MODE (type
),
8289 TYPE_UNSIGNED (type
));
8292 /* Try to make operands [OPS, OPS + NOPS) match operands [OPNO, OPNO + NOPS)
8293 of instruction ICODE. Return true on success, leaving the new operand
8294 values in the OPS themselves. Emit no code on failure. */
8297 maybe_legitimize_operands (enum insn_code icode
, unsigned int opno
,
8298 unsigned int nops
, struct expand_operand
*ops
)
8303 last
= get_last_insn ();
8304 for (i
= 0; i
< nops
; i
++)
8305 if (!maybe_legitimize_operand (icode
, opno
+ i
, &ops
[i
]))
8307 delete_insns_since (last
);
8313 /* Try to generate instruction ICODE, using operands [OPS, OPS + NOPS)
8314 as its operands. Return the instruction pattern on success,
8315 and emit any necessary set-up code. Return null and emit no
8319 maybe_gen_insn (enum insn_code icode
, unsigned int nops
,
8320 struct expand_operand
*ops
)
8322 gcc_assert (nops
== (unsigned int) insn_data
[(int) icode
].n_generator_args
);
8323 if (!maybe_legitimize_operands (icode
, 0, nops
, ops
))
8329 return GEN_FCN (icode
) (ops
[0].value
);
8331 return GEN_FCN (icode
) (ops
[0].value
, ops
[1].value
);
8333 return GEN_FCN (icode
) (ops
[0].value
, ops
[1].value
, ops
[2].value
);
8335 return GEN_FCN (icode
) (ops
[0].value
, ops
[1].value
, ops
[2].value
,
8338 return GEN_FCN (icode
) (ops
[0].value
, ops
[1].value
, ops
[2].value
,
8339 ops
[3].value
, ops
[4].value
);
8341 return GEN_FCN (icode
) (ops
[0].value
, ops
[1].value
, ops
[2].value
,
8342 ops
[3].value
, ops
[4].value
, ops
[5].value
);
8344 return GEN_FCN (icode
) (ops
[0].value
, ops
[1].value
, ops
[2].value
,
8345 ops
[3].value
, ops
[4].value
, ops
[5].value
,
8348 return GEN_FCN (icode
) (ops
[0].value
, ops
[1].value
, ops
[2].value
,
8349 ops
[3].value
, ops
[4].value
, ops
[5].value
,
8350 ops
[6].value
, ops
[7].value
);
8352 return GEN_FCN (icode
) (ops
[0].value
, ops
[1].value
, ops
[2].value
,
8353 ops
[3].value
, ops
[4].value
, ops
[5].value
,
8354 ops
[6].value
, ops
[7].value
, ops
[8].value
);
8359 /* Try to emit instruction ICODE, using operands [OPS, OPS + NOPS)
8360 as its operands. Return true on success and emit no code on failure. */
8363 maybe_expand_insn (enum insn_code icode
, unsigned int nops
,
8364 struct expand_operand
*ops
)
8366 rtx_insn
*pat
= maybe_gen_insn (icode
, nops
, ops
);
8375 /* Like maybe_expand_insn, but for jumps. */
8378 maybe_expand_jump_insn (enum insn_code icode
, unsigned int nops
,
8379 struct expand_operand
*ops
)
8381 rtx_insn
*pat
= maybe_gen_insn (icode
, nops
, ops
);
8384 emit_jump_insn (pat
);
8390 /* Emit instruction ICODE, using operands [OPS, OPS + NOPS)
8394 expand_insn (enum insn_code icode
, unsigned int nops
,
8395 struct expand_operand
*ops
)
8397 if (!maybe_expand_insn (icode
, nops
, ops
))
8401 /* Like expand_insn, but for jumps. */
8404 expand_jump_insn (enum insn_code icode
, unsigned int nops
,
8405 struct expand_operand
*ops
)
8407 if (!maybe_expand_jump_insn (icode
, nops
, ops
))
8411 /* Reduce conditional compilation elsewhere. */
8413 /* Enumerates the possible types of structure operand to an
8415 enum extraction_type
{ ET_unaligned_mem
, ET_reg
};
8417 /* Check whether insv, extv or extzv pattern ICODE can be used for an
8418 insertion or extraction of type TYPE on a structure of mode MODE.
8419 Return true if so and fill in *INSN accordingly. STRUCT_OP is the
8420 operand number of the structure (the first sign_extract or zero_extract
8421 operand) and FIELD_OP is the operand number of the field (the other
8422 side of the set from the sign_extract or zero_extract). */
8425 get_traditional_extraction_insn (extraction_insn
*insn
,
8426 enum extraction_type type
,
8428 enum insn_code icode
,
8429 int struct_op
, int field_op
)
8431 const struct insn_data_d
*data
= &insn_data
[icode
];
8433 machine_mode struct_mode
= data
->operand
[struct_op
].mode
;
8434 if (struct_mode
== VOIDmode
)
8435 struct_mode
= word_mode
;
8436 if (mode
!= struct_mode
)
8439 machine_mode field_mode
= data
->operand
[field_op
].mode
;
8440 if (field_mode
== VOIDmode
)
8441 field_mode
= word_mode
;
8443 machine_mode pos_mode
= data
->operand
[struct_op
+ 2].mode
;
8444 if (pos_mode
== VOIDmode
)
8445 pos_mode
= word_mode
;
8447 insn
->icode
= icode
;
8448 insn
->field_mode
= field_mode
;
8449 insn
->struct_mode
= (type
== ET_unaligned_mem
? byte_mode
: struct_mode
);
8450 insn
->pos_mode
= pos_mode
;
8454 /* Return true if an optab exists to perform an insertion or extraction
8455 of type TYPE in mode MODE. Describe the instruction in *INSN if so.
8457 REG_OPTAB is the optab to use for register structures and
8458 MISALIGN_OPTAB is the optab to use for misaligned memory structures.
8459 POS_OP is the operand number of the bit position. */
8462 get_optab_extraction_insn (struct extraction_insn
*insn
,
8463 enum extraction_type type
,
8464 machine_mode mode
, direct_optab reg_optab
,
8465 direct_optab misalign_optab
, int pos_op
)
8467 direct_optab optab
= (type
== ET_unaligned_mem
? misalign_optab
: reg_optab
);
8468 enum insn_code icode
= direct_optab_handler (optab
, mode
);
8469 if (icode
== CODE_FOR_nothing
)
8472 const struct insn_data_d
*data
= &insn_data
[icode
];
8474 insn
->icode
= icode
;
8475 insn
->field_mode
= mode
;
8476 insn
->struct_mode
= (type
== ET_unaligned_mem
? BLKmode
: mode
);
8477 insn
->pos_mode
= data
->operand
[pos_op
].mode
;
8478 if (insn
->pos_mode
== VOIDmode
)
8479 insn
->pos_mode
= word_mode
;
8483 /* Return true if an instruction exists to perform an insertion or
8484 extraction (PATTERN says which) of type TYPE in mode MODE.
8485 Describe the instruction in *INSN if so. */
8488 get_extraction_insn (extraction_insn
*insn
,
8489 enum extraction_pattern pattern
,
8490 enum extraction_type type
,
8496 if (targetm
.have_insv ()
8497 && get_traditional_extraction_insn (insn
, type
, mode
,
8498 targetm
.code_for_insv
, 0, 3))
8500 return get_optab_extraction_insn (insn
, type
, mode
, insv_optab
,
8501 insvmisalign_optab
, 2);
8504 if (targetm
.have_extv ()
8505 && get_traditional_extraction_insn (insn
, type
, mode
,
8506 targetm
.code_for_extv
, 1, 0))
8508 return get_optab_extraction_insn (insn
, type
, mode
, extv_optab
,
8509 extvmisalign_optab
, 3);
8512 if (targetm
.have_extzv ()
8513 && get_traditional_extraction_insn (insn
, type
, mode
,
8514 targetm
.code_for_extzv
, 1, 0))
8516 return get_optab_extraction_insn (insn
, type
, mode
, extzv_optab
,
8517 extzvmisalign_optab
, 3);
8524 /* Return true if an instruction exists to access a field of mode
8525 FIELDMODE in a structure that has STRUCT_BITS significant bits.
8526 Describe the "best" such instruction in *INSN if so. PATTERN and
8527 TYPE describe the type of insertion or extraction we want to perform.
8529 For an insertion, the number of significant structure bits includes
8530 all bits of the target. For an extraction, it need only include the
8531 most significant bit of the field. Larger widths are acceptable
8535 get_best_extraction_insn (extraction_insn
*insn
,
8536 enum extraction_pattern pattern
,
8537 enum extraction_type type
,
8538 unsigned HOST_WIDE_INT struct_bits
,
8539 machine_mode field_mode
)
8541 machine_mode mode
= smallest_mode_for_size (struct_bits
, MODE_INT
);
8542 while (mode
!= VOIDmode
)
8544 if (get_extraction_insn (insn
, pattern
, type
, mode
))
8546 while (mode
!= VOIDmode
8547 && GET_MODE_SIZE (mode
) <= GET_MODE_SIZE (field_mode
)
8548 && !TRULY_NOOP_TRUNCATION_MODES_P (insn
->field_mode
,
8551 get_extraction_insn (insn
, pattern
, type
, mode
);
8552 mode
= GET_MODE_WIDER_MODE (mode
);
8556 mode
= GET_MODE_WIDER_MODE (mode
);
8561 /* Return true if an instruction exists to access a field of mode
8562 FIELDMODE in a register structure that has STRUCT_BITS significant bits.
8563 Describe the "best" such instruction in *INSN if so. PATTERN describes
8564 the type of insertion or extraction we want to perform.
8566 For an insertion, the number of significant structure bits includes
8567 all bits of the target. For an extraction, it need only include the
8568 most significant bit of the field. Larger widths are acceptable
8572 get_best_reg_extraction_insn (extraction_insn
*insn
,
8573 enum extraction_pattern pattern
,
8574 unsigned HOST_WIDE_INT struct_bits
,
8575 machine_mode field_mode
)
8577 return get_best_extraction_insn (insn
, pattern
, ET_reg
, struct_bits
,
8581 /* Return true if an instruction exists to access a field of BITSIZE
8582 bits starting BITNUM bits into a memory structure. Describe the
8583 "best" such instruction in *INSN if so. PATTERN describes the type
8584 of insertion or extraction we want to perform and FIELDMODE is the
8585 natural mode of the extracted field.
8587 The instructions considered here only access bytes that overlap
8588 the bitfield; they do not touch any surrounding bytes. */
8591 get_best_mem_extraction_insn (extraction_insn
*insn
,
8592 enum extraction_pattern pattern
,
8593 HOST_WIDE_INT bitsize
, HOST_WIDE_INT bitnum
,
8594 machine_mode field_mode
)
8596 unsigned HOST_WIDE_INT struct_bits
= (bitnum
% BITS_PER_UNIT
8598 + BITS_PER_UNIT
- 1);
8599 struct_bits
-= struct_bits
% BITS_PER_UNIT
;
8600 return get_best_extraction_insn (insn
, pattern
, ET_unaligned_mem
,
8601 struct_bits
, field_mode
);
8604 /* Determine whether "1 << x" is relatively cheap in word_mode. */
8607 lshift_cheap_p (bool speed_p
)
8609 /* FIXME: This should be made target dependent via this "this_target"
8610 mechanism, similar to e.g. can_copy_init_p in gcse.c. */
8611 static bool init
[2] = { false, false };
8612 static bool cheap
[2] = { true, true };
8614 /* If the targer has no lshift in word_mode, the operation will most
8615 probably not be cheap. ??? Does GCC even work for such targets? */
8616 if (optab_handler (ashl_optab
, word_mode
) == CODE_FOR_nothing
)
8621 rtx reg
= gen_raw_REG (word_mode
, 10000);
8622 int cost
= set_src_cost (gen_rtx_ASHIFT (word_mode
, const1_rtx
, reg
),
8623 word_mode
, speed_p
);
8624 cheap
[speed_p
] = cost
< COSTS_N_INSNS (3);
8625 init
[speed_p
] = true;
8628 return cheap
[speed_p
];
8631 #include "gt-optabs.h"