1 /* Expand the basic unary and binary arithmetic operations, for GNU compiler.
2 Copyright (C) 1987-2014 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify it under
7 the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 3, or (at your option) any later
11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
23 #include "coretypes.h"
25 #include "diagnostic-core.h"
27 /* Include insn-config.h before expr.h so that HAVE_conditional_move
28 is properly defined. */
29 #include "insn-config.h"
32 #include "stor-layout.h"
33 #include "stringpool.h"
45 #include "basic-block.h"
48 struct target_optabs default_target_optabs
;
49 struct target_libfuncs default_target_libfuncs
;
50 struct target_optabs
*this_fn_optabs
= &default_target_optabs
;
52 struct target_optabs
*this_target_optabs
= &default_target_optabs
;
53 struct target_libfuncs
*this_target_libfuncs
= &default_target_libfuncs
;
56 #define libfunc_hash \
57 (this_target_libfuncs->x_libfunc_hash)
59 static void prepare_float_lib_cmp (rtx
, rtx
, enum rtx_code
, rtx
*,
61 static rtx
expand_unop_direct (enum machine_mode
, optab
, rtx
, rtx
, int);
62 static void emit_libcall_block_1 (rtx_insn
*, rtx
, rtx
, rtx
, bool);
64 /* Debug facility for use in GDB. */
65 void debug_optab_libfuncs (void);
67 /* Prefixes for the current version of decimal floating point (BID vs. DPD) */
68 #if ENABLE_DECIMAL_BID_FORMAT
69 #define DECIMAL_PREFIX "bid_"
71 #define DECIMAL_PREFIX "dpd_"
74 /* Used for libfunc_hash. */
77 hash_libfunc (const void *p
)
79 const struct libfunc_entry
*const e
= (const struct libfunc_entry
*) p
;
80 return ((e
->mode1
+ e
->mode2
* NUM_MACHINE_MODES
) ^ e
->op
);
83 /* Used for libfunc_hash. */
86 eq_libfunc (const void *p
, const void *q
)
88 const struct libfunc_entry
*const e1
= (const struct libfunc_entry
*) p
;
89 const struct libfunc_entry
*const e2
= (const struct libfunc_entry
*) q
;
90 return e1
->op
== e2
->op
&& e1
->mode1
== e2
->mode1
&& e1
->mode2
== e2
->mode2
;
93 /* Return libfunc corresponding operation defined by OPTAB converting
94 from MODE2 to MODE1. Trigger lazy initialization if needed, return NULL
95 if no libfunc is available. */
97 convert_optab_libfunc (convert_optab optab
, enum machine_mode mode1
,
98 enum machine_mode mode2
)
100 struct libfunc_entry e
;
101 struct libfunc_entry
**slot
;
103 /* ??? This ought to be an assert, but not all of the places
104 that we expand optabs know about the optabs that got moved
106 if (!(optab
>= FIRST_CONV_OPTAB
&& optab
<= LAST_CONVLIB_OPTAB
))
112 slot
= (struct libfunc_entry
**)
113 htab_find_slot (libfunc_hash
, &e
, NO_INSERT
);
116 const struct convert_optab_libcall_d
*d
117 = &convlib_def
[optab
- FIRST_CONV_OPTAB
];
119 if (d
->libcall_gen
== NULL
)
122 d
->libcall_gen (optab
, d
->libcall_basename
, mode1
, mode2
);
123 slot
= (struct libfunc_entry
**)
124 htab_find_slot (libfunc_hash
, &e
, NO_INSERT
);
128 return (*slot
)->libfunc
;
131 /* Return libfunc corresponding operation defined by OPTAB in MODE.
132 Trigger lazy initialization if needed, return NULL if no libfunc is
135 optab_libfunc (optab optab
, enum machine_mode mode
)
137 struct libfunc_entry e
;
138 struct libfunc_entry
**slot
;
140 /* ??? This ought to be an assert, but not all of the places
141 that we expand optabs know about the optabs that got moved
143 if (!(optab
>= FIRST_NORM_OPTAB
&& optab
<= LAST_NORMLIB_OPTAB
))
149 slot
= (struct libfunc_entry
**)
150 htab_find_slot (libfunc_hash
, &e
, NO_INSERT
);
153 const struct optab_libcall_d
*d
154 = &normlib_def
[optab
- FIRST_NORM_OPTAB
];
156 if (d
->libcall_gen
== NULL
)
159 d
->libcall_gen (optab
, d
->libcall_basename
, d
->libcall_suffix
, mode
);
160 slot
= (struct libfunc_entry
**)
161 htab_find_slot (libfunc_hash
, &e
, NO_INSERT
);
165 return (*slot
)->libfunc
;
169 /* Add a REG_EQUAL note to the last insn in INSNS. TARGET is being set to
170 the result of operation CODE applied to OP0 (and OP1 if it is a binary
173 If the last insn does not set TARGET, don't do anything, but return 1.
175 If the last insn or a previous insn sets TARGET and TARGET is one of OP0
176 or OP1, don't add the REG_EQUAL note but return 0. Our caller can then
177 try again, ensuring that TARGET is not one of the operands. */
180 add_equal_note (rtx_insn
*insns
, rtx target
, enum rtx_code code
, rtx op0
, rtx op1
)
186 gcc_assert (insns
&& INSN_P (insns
) && NEXT_INSN (insns
));
188 if (GET_RTX_CLASS (code
) != RTX_COMM_ARITH
189 && GET_RTX_CLASS (code
) != RTX_BIN_ARITH
190 && GET_RTX_CLASS (code
) != RTX_COMM_COMPARE
191 && GET_RTX_CLASS (code
) != RTX_COMPARE
192 && GET_RTX_CLASS (code
) != RTX_UNARY
)
195 if (GET_CODE (target
) == ZERO_EXTRACT
)
198 for (last_insn
= insns
;
199 NEXT_INSN (last_insn
) != NULL_RTX
;
200 last_insn
= NEXT_INSN (last_insn
))
203 /* If TARGET is in OP0 or OP1, punt. We'd end up with a note referencing
204 a value changing in the insn, so the note would be invalid for CSE. */
205 if (reg_overlap_mentioned_p (target
, op0
)
206 || (op1
&& reg_overlap_mentioned_p (target
, op1
)))
209 && (rtx_equal_p (target
, op0
)
210 || (op1
&& rtx_equal_p (target
, op1
))))
212 /* For MEM target, with MEM = MEM op X, prefer no REG_EQUAL note
213 over expanding it as temp = MEM op X, MEM = temp. If the target
214 supports MEM = MEM op X instructions, it is sometimes too hard
215 to reconstruct that form later, especially if X is also a memory,
216 and due to multiple occurrences of addresses the address might
217 be forced into register unnecessarily.
218 Note that not emitting the REG_EQUIV note might inhibit
219 CSE in some cases. */
220 set
= single_set (last_insn
);
222 && GET_CODE (SET_SRC (set
)) == code
223 && MEM_P (SET_DEST (set
))
224 && (rtx_equal_p (SET_DEST (set
), XEXP (SET_SRC (set
), 0))
225 || (op1
&& rtx_equal_p (SET_DEST (set
),
226 XEXP (SET_SRC (set
), 1)))))
232 set
= set_for_reg_notes (last_insn
);
236 if (! rtx_equal_p (SET_DEST (set
), target
)
237 /* For a STRICT_LOW_PART, the REG_NOTE applies to what is inside it. */
238 && (GET_CODE (SET_DEST (set
)) != STRICT_LOW_PART
239 || ! rtx_equal_p (XEXP (SET_DEST (set
), 0), target
)))
242 if (GET_RTX_CLASS (code
) == RTX_UNARY
)
252 if (GET_MODE (op0
) != VOIDmode
&& GET_MODE (target
) != GET_MODE (op0
))
254 note
= gen_rtx_fmt_e (code
, GET_MODE (op0
), copy_rtx (op0
));
255 if (GET_MODE_SIZE (GET_MODE (op0
))
256 > GET_MODE_SIZE (GET_MODE (target
)))
257 note
= simplify_gen_unary (TRUNCATE
, GET_MODE (target
),
258 note
, GET_MODE (op0
));
260 note
= simplify_gen_unary (ZERO_EXTEND
, GET_MODE (target
),
261 note
, GET_MODE (op0
));
266 note
= gen_rtx_fmt_e (code
, GET_MODE (target
), copy_rtx (op0
));
270 note
= gen_rtx_fmt_ee (code
, GET_MODE (target
), copy_rtx (op0
), copy_rtx (op1
));
272 set_unique_reg_note (last_insn
, REG_EQUAL
, note
);
277 /* Given two input operands, OP0 and OP1, determine what the correct from_mode
278 for a widening operation would be. In most cases this would be OP0, but if
279 that's a constant it'll be VOIDmode, which isn't useful. */
281 static enum machine_mode
282 widened_mode (enum machine_mode to_mode
, rtx op0
, rtx op1
)
284 enum machine_mode m0
= GET_MODE (op0
);
285 enum machine_mode m1
= GET_MODE (op1
);
286 enum machine_mode result
;
288 if (m0
== VOIDmode
&& m1
== VOIDmode
)
290 else if (m0
== VOIDmode
|| GET_MODE_SIZE (m0
) < GET_MODE_SIZE (m1
))
295 if (GET_MODE_SIZE (result
) > GET_MODE_SIZE (to_mode
))
301 /* Like optab_handler, but for widening_operations that have a
302 TO_MODE and a FROM_MODE. */
305 widening_optab_handler (optab op
, enum machine_mode to_mode
,
306 enum machine_mode from_mode
)
308 unsigned scode
= (op
<< 16) | to_mode
;
309 if (to_mode
!= from_mode
&& from_mode
!= VOIDmode
)
311 /* ??? Why does find_widening_optab_handler_and_mode attempt to
312 widen things that can't be widened? E.g. add_optab... */
313 if (op
> LAST_CONV_OPTAB
)
314 return CODE_FOR_nothing
;
315 scode
|= from_mode
<< 8;
317 return raw_optab_handler (scode
);
320 /* Find a widening optab even if it doesn't widen as much as we want.
321 E.g. if from_mode is HImode, and to_mode is DImode, and there is no
322 direct HI->SI insn, then return SI->DI, if that exists.
323 If PERMIT_NON_WIDENING is non-zero then this can be used with
324 non-widening optabs also. */
327 find_widening_optab_handler_and_mode (optab op
, enum machine_mode to_mode
,
328 enum machine_mode from_mode
,
329 int permit_non_widening
,
330 enum machine_mode
*found_mode
)
332 for (; (permit_non_widening
|| from_mode
!= to_mode
)
333 && GET_MODE_SIZE (from_mode
) <= GET_MODE_SIZE (to_mode
)
334 && from_mode
!= VOIDmode
;
335 from_mode
= GET_MODE_WIDER_MODE (from_mode
))
337 enum insn_code handler
= widening_optab_handler (op
, to_mode
,
340 if (handler
!= CODE_FOR_nothing
)
343 *found_mode
= from_mode
;
348 return CODE_FOR_nothing
;
351 /* Widen OP to MODE and return the rtx for the widened operand. UNSIGNEDP
352 says whether OP is signed or unsigned. NO_EXTEND is nonzero if we need
353 not actually do a sign-extend or zero-extend, but can leave the
354 higher-order bits of the result rtx undefined, for example, in the case
355 of logical operations, but not right shifts. */
358 widen_operand (rtx op
, enum machine_mode mode
, enum machine_mode oldmode
,
359 int unsignedp
, int no_extend
)
363 /* If we don't have to extend and this is a constant, return it. */
364 if (no_extend
&& GET_MODE (op
) == VOIDmode
)
367 /* If we must extend do so. If OP is a SUBREG for a promoted object, also
368 extend since it will be more efficient to do so unless the signedness of
369 a promoted object differs from our extension. */
371 || (GET_CODE (op
) == SUBREG
&& SUBREG_PROMOTED_VAR_P (op
)
372 && SUBREG_CHECK_PROMOTED_SIGN (op
, unsignedp
)))
373 return convert_modes (mode
, oldmode
, op
, unsignedp
);
375 /* If MODE is no wider than a single word, we return a lowpart or paradoxical
377 if (GET_MODE_SIZE (mode
) <= UNITS_PER_WORD
)
378 return gen_lowpart (mode
, force_reg (GET_MODE (op
), op
));
380 /* Otherwise, get an object of MODE, clobber it, and set the low-order
383 result
= gen_reg_rtx (mode
);
384 emit_clobber (result
);
385 emit_move_insn (gen_lowpart (GET_MODE (op
), result
), op
);
389 /* Return the optab used for computing the operation given by the tree code,
390 CODE and the tree EXP. This function is not always usable (for example, it
391 cannot give complete results for multiplication or division) but probably
392 ought to be relied on more widely throughout the expander. */
394 optab_for_tree_code (enum tree_code code
, const_tree type
,
395 enum optab_subtype subtype
)
407 return one_cmpl_optab
;
412 case MULT_HIGHPART_EXPR
:
413 return TYPE_UNSIGNED (type
) ? umul_highpart_optab
: smul_highpart_optab
;
419 return TYPE_UNSIGNED (type
) ? umod_optab
: smod_optab
;
427 if (TYPE_SATURATING (type
))
428 return TYPE_UNSIGNED (type
) ? usdiv_optab
: ssdiv_optab
;
429 return TYPE_UNSIGNED (type
) ? udiv_optab
: sdiv_optab
;
432 if (TREE_CODE (type
) == VECTOR_TYPE
)
434 if (subtype
== optab_vector
)
435 return TYPE_SATURATING (type
) ? unknown_optab
: vashl_optab
;
437 gcc_assert (subtype
== optab_scalar
);
439 if (TYPE_SATURATING (type
))
440 return TYPE_UNSIGNED (type
) ? usashl_optab
: ssashl_optab
;
444 if (TREE_CODE (type
) == VECTOR_TYPE
)
446 if (subtype
== optab_vector
)
447 return TYPE_UNSIGNED (type
) ? vlshr_optab
: vashr_optab
;
449 gcc_assert (subtype
== optab_scalar
);
451 return TYPE_UNSIGNED (type
) ? lshr_optab
: ashr_optab
;
454 if (TREE_CODE (type
) == VECTOR_TYPE
)
456 if (subtype
== optab_vector
)
459 gcc_assert (subtype
== optab_scalar
);
464 if (TREE_CODE (type
) == VECTOR_TYPE
)
466 if (subtype
== optab_vector
)
469 gcc_assert (subtype
== optab_scalar
);
474 return TYPE_UNSIGNED (type
) ? umax_optab
: smax_optab
;
477 return TYPE_UNSIGNED (type
) ? umin_optab
: smin_optab
;
479 case REALIGN_LOAD_EXPR
:
480 return vec_realign_load_optab
;
483 return TYPE_UNSIGNED (type
) ? usum_widen_optab
: ssum_widen_optab
;
486 return TYPE_UNSIGNED (type
) ? udot_prod_optab
: sdot_prod_optab
;
489 return TYPE_UNSIGNED (type
) ? usad_optab
: ssad_optab
;
491 case WIDEN_MULT_PLUS_EXPR
:
492 return (TYPE_UNSIGNED (type
)
493 ? (TYPE_SATURATING (type
)
494 ? usmadd_widen_optab
: umadd_widen_optab
)
495 : (TYPE_SATURATING (type
)
496 ? ssmadd_widen_optab
: smadd_widen_optab
));
498 case WIDEN_MULT_MINUS_EXPR
:
499 return (TYPE_UNSIGNED (type
)
500 ? (TYPE_SATURATING (type
)
501 ? usmsub_widen_optab
: umsub_widen_optab
)
502 : (TYPE_SATURATING (type
)
503 ? ssmsub_widen_optab
: smsub_widen_optab
));
509 return TYPE_UNSIGNED (type
) ? reduc_umax_optab
: reduc_smax_optab
;
512 return TYPE_UNSIGNED (type
) ? reduc_umin_optab
: reduc_smin_optab
;
514 case REDUC_PLUS_EXPR
:
515 return TYPE_UNSIGNED (type
) ? reduc_uplus_optab
: reduc_splus_optab
;
517 case VEC_LSHIFT_EXPR
:
518 return vec_shl_optab
;
520 case VEC_RSHIFT_EXPR
:
521 return vec_shr_optab
;
523 case VEC_WIDEN_MULT_HI_EXPR
:
524 return TYPE_UNSIGNED (type
) ?
525 vec_widen_umult_hi_optab
: vec_widen_smult_hi_optab
;
527 case VEC_WIDEN_MULT_LO_EXPR
:
528 return TYPE_UNSIGNED (type
) ?
529 vec_widen_umult_lo_optab
: vec_widen_smult_lo_optab
;
531 case VEC_WIDEN_MULT_EVEN_EXPR
:
532 return TYPE_UNSIGNED (type
) ?
533 vec_widen_umult_even_optab
: vec_widen_smult_even_optab
;
535 case VEC_WIDEN_MULT_ODD_EXPR
:
536 return TYPE_UNSIGNED (type
) ?
537 vec_widen_umult_odd_optab
: vec_widen_smult_odd_optab
;
539 case VEC_WIDEN_LSHIFT_HI_EXPR
:
540 return TYPE_UNSIGNED (type
) ?
541 vec_widen_ushiftl_hi_optab
: vec_widen_sshiftl_hi_optab
;
543 case VEC_WIDEN_LSHIFT_LO_EXPR
:
544 return TYPE_UNSIGNED (type
) ?
545 vec_widen_ushiftl_lo_optab
: vec_widen_sshiftl_lo_optab
;
547 case VEC_UNPACK_HI_EXPR
:
548 return TYPE_UNSIGNED (type
) ?
549 vec_unpacku_hi_optab
: vec_unpacks_hi_optab
;
551 case VEC_UNPACK_LO_EXPR
:
552 return TYPE_UNSIGNED (type
) ?
553 vec_unpacku_lo_optab
: vec_unpacks_lo_optab
;
555 case VEC_UNPACK_FLOAT_HI_EXPR
:
556 /* The signedness is determined from input operand. */
557 return TYPE_UNSIGNED (type
) ?
558 vec_unpacku_float_hi_optab
: vec_unpacks_float_hi_optab
;
560 case VEC_UNPACK_FLOAT_LO_EXPR
:
561 /* The signedness is determined from input operand. */
562 return TYPE_UNSIGNED (type
) ?
563 vec_unpacku_float_lo_optab
: vec_unpacks_float_lo_optab
;
565 case VEC_PACK_TRUNC_EXPR
:
566 return vec_pack_trunc_optab
;
568 case VEC_PACK_SAT_EXPR
:
569 return TYPE_UNSIGNED (type
) ? vec_pack_usat_optab
: vec_pack_ssat_optab
;
571 case VEC_PACK_FIX_TRUNC_EXPR
:
572 /* The signedness is determined from output operand. */
573 return TYPE_UNSIGNED (type
) ?
574 vec_pack_ufix_trunc_optab
: vec_pack_sfix_trunc_optab
;
580 trapv
= INTEGRAL_TYPE_P (type
) && TYPE_OVERFLOW_TRAPS (type
);
583 case POINTER_PLUS_EXPR
:
585 if (TYPE_SATURATING (type
))
586 return TYPE_UNSIGNED (type
) ? usadd_optab
: ssadd_optab
;
587 return trapv
? addv_optab
: add_optab
;
590 if (TYPE_SATURATING (type
))
591 return TYPE_UNSIGNED (type
) ? ussub_optab
: sssub_optab
;
592 return trapv
? subv_optab
: sub_optab
;
595 if (TYPE_SATURATING (type
))
596 return TYPE_UNSIGNED (type
) ? usmul_optab
: ssmul_optab
;
597 return trapv
? smulv_optab
: smul_optab
;
600 if (TYPE_SATURATING (type
))
601 return TYPE_UNSIGNED (type
) ? usneg_optab
: ssneg_optab
;
602 return trapv
? negv_optab
: neg_optab
;
605 return trapv
? absv_optab
: abs_optab
;
608 return unknown_optab
;
613 /* Expand vector widening operations.
615 There are two different classes of operations handled here:
616 1) Operations whose result is wider than all the arguments to the operation.
617 Examples: VEC_UNPACK_HI/LO_EXPR, VEC_WIDEN_MULT_HI/LO_EXPR
618 In this case OP0 and optionally OP1 would be initialized,
619 but WIDE_OP wouldn't (not relevant for this case).
620 2) Operations whose result is of the same size as the last argument to the
621 operation, but wider than all the other arguments to the operation.
622 Examples: WIDEN_SUM_EXPR, VEC_DOT_PROD_EXPR.
623 In the case WIDE_OP, OP0 and optionally OP1 would be initialized.
625 E.g, when called to expand the following operations, this is how
626 the arguments will be initialized:
628 widening-sum 2 oprnd0 - oprnd1
629 widening-dot-product 3 oprnd0 oprnd1 oprnd2
630 widening-mult 2 oprnd0 oprnd1 -
631 type-promotion (vec-unpack) 1 oprnd0 - - */
634 expand_widen_pattern_expr (sepops ops
, rtx op0
, rtx op1
, rtx wide_op
,
635 rtx target
, int unsignedp
)
637 struct expand_operand eops
[4];
638 tree oprnd0
, oprnd1
, oprnd2
;
639 enum machine_mode wmode
= VOIDmode
, tmode0
, tmode1
= VOIDmode
;
640 optab widen_pattern_optab
;
641 enum insn_code icode
;
642 int nops
= TREE_CODE_LENGTH (ops
->code
);
646 tmode0
= TYPE_MODE (TREE_TYPE (oprnd0
));
647 widen_pattern_optab
=
648 optab_for_tree_code (ops
->code
, TREE_TYPE (oprnd0
), optab_default
);
649 if (ops
->code
== WIDEN_MULT_PLUS_EXPR
650 || ops
->code
== WIDEN_MULT_MINUS_EXPR
)
651 icode
= find_widening_optab_handler (widen_pattern_optab
,
652 TYPE_MODE (TREE_TYPE (ops
->op2
)),
655 icode
= optab_handler (widen_pattern_optab
, tmode0
);
656 gcc_assert (icode
!= CODE_FOR_nothing
);
661 tmode1
= TYPE_MODE (TREE_TYPE (oprnd1
));
664 /* The last operand is of a wider mode than the rest of the operands. */
669 gcc_assert (tmode1
== tmode0
);
672 wmode
= TYPE_MODE (TREE_TYPE (oprnd2
));
676 create_output_operand (&eops
[op
++], target
, TYPE_MODE (ops
->type
));
677 create_convert_operand_from (&eops
[op
++], op0
, tmode0
, unsignedp
);
679 create_convert_operand_from (&eops
[op
++], op1
, tmode1
, unsignedp
);
681 create_convert_operand_from (&eops
[op
++], wide_op
, wmode
, unsignedp
);
682 expand_insn (icode
, op
, eops
);
683 return eops
[0].value
;
686 /* Generate code to perform an operation specified by TERNARY_OPTAB
687 on operands OP0, OP1 and OP2, with result having machine-mode MODE.
689 UNSIGNEDP is for the case where we have to widen the operands
690 to perform the operation. It says to use zero-extension.
692 If TARGET is nonzero, the value
693 is generated there, if it is convenient to do so.
694 In all cases an rtx is returned for the locus of the value;
695 this may or may not be TARGET. */
698 expand_ternary_op (enum machine_mode mode
, optab ternary_optab
, rtx op0
,
699 rtx op1
, rtx op2
, rtx target
, int unsignedp
)
701 struct expand_operand ops
[4];
702 enum insn_code icode
= optab_handler (ternary_optab
, mode
);
704 gcc_assert (optab_handler (ternary_optab
, mode
) != CODE_FOR_nothing
);
706 create_output_operand (&ops
[0], target
, mode
);
707 create_convert_operand_from (&ops
[1], op0
, mode
, unsignedp
);
708 create_convert_operand_from (&ops
[2], op1
, mode
, unsignedp
);
709 create_convert_operand_from (&ops
[3], op2
, mode
, unsignedp
);
710 expand_insn (icode
, 4, ops
);
715 /* Like expand_binop, but return a constant rtx if the result can be
716 calculated at compile time. The arguments and return value are
717 otherwise the same as for expand_binop. */
720 simplify_expand_binop (enum machine_mode mode
, optab binoptab
,
721 rtx op0
, rtx op1
, rtx target
, int unsignedp
,
722 enum optab_methods methods
)
724 if (CONSTANT_P (op0
) && CONSTANT_P (op1
))
726 rtx x
= simplify_binary_operation (optab_to_code (binoptab
),
732 return expand_binop (mode
, binoptab
, op0
, op1
, target
, unsignedp
, methods
);
735 /* Like simplify_expand_binop, but always put the result in TARGET.
736 Return true if the expansion succeeded. */
739 force_expand_binop (enum machine_mode mode
, optab binoptab
,
740 rtx op0
, rtx op1
, rtx target
, int unsignedp
,
741 enum optab_methods methods
)
743 rtx x
= simplify_expand_binop (mode
, binoptab
, op0
, op1
,
744 target
, unsignedp
, methods
);
748 emit_move_insn (target
, x
);
752 /* Generate insns for VEC_LSHIFT_EXPR, VEC_RSHIFT_EXPR. */
755 expand_vec_shift_expr (sepops ops
, rtx target
)
757 struct expand_operand eops
[3];
758 enum insn_code icode
;
759 rtx rtx_op1
, rtx_op2
;
760 enum machine_mode mode
= TYPE_MODE (ops
->type
);
761 tree vec_oprnd
= ops
->op0
;
762 tree shift_oprnd
= ops
->op1
;
767 case VEC_RSHIFT_EXPR
:
768 shift_optab
= vec_shr_optab
;
770 case VEC_LSHIFT_EXPR
:
771 shift_optab
= vec_shl_optab
;
777 icode
= optab_handler (shift_optab
, mode
);
778 gcc_assert (icode
!= CODE_FOR_nothing
);
780 rtx_op1
= expand_normal (vec_oprnd
);
781 rtx_op2
= expand_normal (shift_oprnd
);
783 create_output_operand (&eops
[0], target
, mode
);
784 create_input_operand (&eops
[1], rtx_op1
, GET_MODE (rtx_op1
));
785 create_convert_operand_from_type (&eops
[2], rtx_op2
, TREE_TYPE (shift_oprnd
));
786 expand_insn (icode
, 3, eops
);
788 return eops
[0].value
;
791 /* Create a new vector value in VMODE with all elements set to OP. The
792 mode of OP must be the element mode of VMODE. If OP is a constant,
793 then the return value will be a constant. */
796 expand_vector_broadcast (enum machine_mode vmode
, rtx op
)
798 enum insn_code icode
;
803 gcc_checking_assert (VECTOR_MODE_P (vmode
));
805 n
= GET_MODE_NUNITS (vmode
);
806 vec
= rtvec_alloc (n
);
807 for (i
= 0; i
< n
; ++i
)
808 RTVEC_ELT (vec
, i
) = op
;
811 return gen_rtx_CONST_VECTOR (vmode
, vec
);
813 /* ??? If the target doesn't have a vec_init, then we have no easy way
814 of performing this operation. Most of this sort of generic support
815 is hidden away in the vector lowering support in gimple. */
816 icode
= optab_handler (vec_init_optab
, vmode
);
817 if (icode
== CODE_FOR_nothing
)
820 ret
= gen_reg_rtx (vmode
);
821 emit_insn (GEN_FCN (icode
) (ret
, gen_rtx_PARALLEL (vmode
, vec
)));
826 /* This subroutine of expand_doubleword_shift handles the cases in which
827 the effective shift value is >= BITS_PER_WORD. The arguments and return
828 value are the same as for the parent routine, except that SUPERWORD_OP1
829 is the shift count to use when shifting OUTOF_INPUT into INTO_TARGET.
830 INTO_TARGET may be null if the caller has decided to calculate it. */
833 expand_superword_shift (optab binoptab
, rtx outof_input
, rtx superword_op1
,
834 rtx outof_target
, rtx into_target
,
835 int unsignedp
, enum optab_methods methods
)
837 if (into_target
!= 0)
838 if (!force_expand_binop (word_mode
, binoptab
, outof_input
, superword_op1
,
839 into_target
, unsignedp
, methods
))
842 if (outof_target
!= 0)
844 /* For a signed right shift, we must fill OUTOF_TARGET with copies
845 of the sign bit, otherwise we must fill it with zeros. */
846 if (binoptab
!= ashr_optab
)
847 emit_move_insn (outof_target
, CONST0_RTX (word_mode
));
849 if (!force_expand_binop (word_mode
, binoptab
,
850 outof_input
, GEN_INT (BITS_PER_WORD
- 1),
851 outof_target
, unsignedp
, methods
))
857 /* This subroutine of expand_doubleword_shift handles the cases in which
858 the effective shift value is < BITS_PER_WORD. The arguments and return
859 value are the same as for the parent routine. */
862 expand_subword_shift (enum machine_mode op1_mode
, optab binoptab
,
863 rtx outof_input
, rtx into_input
, rtx op1
,
864 rtx outof_target
, rtx into_target
,
865 int unsignedp
, enum optab_methods methods
,
866 unsigned HOST_WIDE_INT shift_mask
)
868 optab reverse_unsigned_shift
, unsigned_shift
;
871 reverse_unsigned_shift
= (binoptab
== ashl_optab
? lshr_optab
: ashl_optab
);
872 unsigned_shift
= (binoptab
== ashl_optab
? ashl_optab
: lshr_optab
);
874 /* The low OP1 bits of INTO_TARGET come from the high bits of OUTOF_INPUT.
875 We therefore need to shift OUTOF_INPUT by (BITS_PER_WORD - OP1) bits in
876 the opposite direction to BINOPTAB. */
877 if (CONSTANT_P (op1
) || shift_mask
>= BITS_PER_WORD
)
879 carries
= outof_input
;
880 tmp
= immed_wide_int_const (wi::shwi (BITS_PER_WORD
,
881 op1_mode
), op1_mode
);
882 tmp
= simplify_expand_binop (op1_mode
, sub_optab
, tmp
, op1
,
887 /* We must avoid shifting by BITS_PER_WORD bits since that is either
888 the same as a zero shift (if shift_mask == BITS_PER_WORD - 1) or
889 has unknown behavior. Do a single shift first, then shift by the
890 remainder. It's OK to use ~OP1 as the remainder if shift counts
891 are truncated to the mode size. */
892 carries
= expand_binop (word_mode
, reverse_unsigned_shift
,
893 outof_input
, const1_rtx
, 0, unsignedp
, methods
);
894 if (shift_mask
== BITS_PER_WORD
- 1)
896 tmp
= immed_wide_int_const
897 (wi::minus_one (GET_MODE_PRECISION (op1_mode
)), op1_mode
);
898 tmp
= simplify_expand_binop (op1_mode
, xor_optab
, op1
, tmp
,
903 tmp
= immed_wide_int_const (wi::shwi (BITS_PER_WORD
- 1,
904 op1_mode
), op1_mode
);
905 tmp
= simplify_expand_binop (op1_mode
, sub_optab
, tmp
, op1
,
909 if (tmp
== 0 || carries
== 0)
911 carries
= expand_binop (word_mode
, reverse_unsigned_shift
,
912 carries
, tmp
, 0, unsignedp
, methods
);
916 /* Shift INTO_INPUT logically by OP1. This is the last use of INTO_INPUT
917 so the result can go directly into INTO_TARGET if convenient. */
918 tmp
= expand_binop (word_mode
, unsigned_shift
, into_input
, op1
,
919 into_target
, unsignedp
, methods
);
923 /* Now OR in the bits carried over from OUTOF_INPUT. */
924 if (!force_expand_binop (word_mode
, ior_optab
, tmp
, carries
,
925 into_target
, unsignedp
, methods
))
928 /* Use a standard word_mode shift for the out-of half. */
929 if (outof_target
!= 0)
930 if (!force_expand_binop (word_mode
, binoptab
, outof_input
, op1
,
931 outof_target
, unsignedp
, methods
))
938 #ifdef HAVE_conditional_move
939 /* Try implementing expand_doubleword_shift using conditional moves.
940 The shift is by < BITS_PER_WORD if (CMP_CODE CMP1 CMP2) is true,
941 otherwise it is by >= BITS_PER_WORD. SUBWORD_OP1 and SUPERWORD_OP1
942 are the shift counts to use in the former and latter case. All other
943 arguments are the same as the parent routine. */
946 expand_doubleword_shift_condmove (enum machine_mode op1_mode
, optab binoptab
,
947 enum rtx_code cmp_code
, rtx cmp1
, rtx cmp2
,
948 rtx outof_input
, rtx into_input
,
949 rtx subword_op1
, rtx superword_op1
,
950 rtx outof_target
, rtx into_target
,
951 int unsignedp
, enum optab_methods methods
,
952 unsigned HOST_WIDE_INT shift_mask
)
954 rtx outof_superword
, into_superword
;
956 /* Put the superword version of the output into OUTOF_SUPERWORD and
958 outof_superword
= outof_target
!= 0 ? gen_reg_rtx (word_mode
) : 0;
959 if (outof_target
!= 0 && subword_op1
== superword_op1
)
961 /* The value INTO_TARGET >> SUBWORD_OP1, which we later store in
962 OUTOF_TARGET, is the same as the value of INTO_SUPERWORD. */
963 into_superword
= outof_target
;
964 if (!expand_superword_shift (binoptab
, outof_input
, superword_op1
,
965 outof_superword
, 0, unsignedp
, methods
))
970 into_superword
= gen_reg_rtx (word_mode
);
971 if (!expand_superword_shift (binoptab
, outof_input
, superword_op1
,
972 outof_superword
, into_superword
,
977 /* Put the subword version directly in OUTOF_TARGET and INTO_TARGET. */
978 if (!expand_subword_shift (op1_mode
, binoptab
,
979 outof_input
, into_input
, subword_op1
,
980 outof_target
, into_target
,
981 unsignedp
, methods
, shift_mask
))
984 /* Select between them. Do the INTO half first because INTO_SUPERWORD
985 might be the current value of OUTOF_TARGET. */
986 if (!emit_conditional_move (into_target
, cmp_code
, cmp1
, cmp2
, op1_mode
,
987 into_target
, into_superword
, word_mode
, false))
990 if (outof_target
!= 0)
991 if (!emit_conditional_move (outof_target
, cmp_code
, cmp1
, cmp2
, op1_mode
,
992 outof_target
, outof_superword
,
1000 /* Expand a doubleword shift (ashl, ashr or lshr) using word-mode shifts.
1001 OUTOF_INPUT and INTO_INPUT are the two word-sized halves of the first
1002 input operand; the shift moves bits in the direction OUTOF_INPUT->
1003 INTO_TARGET. OUTOF_TARGET and INTO_TARGET are the equivalent words
1004 of the target. OP1 is the shift count and OP1_MODE is its mode.
1005 If OP1 is constant, it will have been truncated as appropriate
1006 and is known to be nonzero.
1008 If SHIFT_MASK is zero, the result of word shifts is undefined when the
1009 shift count is outside the range [0, BITS_PER_WORD). This routine must
1010 avoid generating such shifts for OP1s in the range [0, BITS_PER_WORD * 2).
1012 If SHIFT_MASK is nonzero, all word-mode shift counts are effectively
1013 masked by it and shifts in the range [BITS_PER_WORD, SHIFT_MASK) will
1014 fill with zeros or sign bits as appropriate.
1016 If SHIFT_MASK is BITS_PER_WORD - 1, this routine will synthesize
1017 a doubleword shift whose equivalent mask is BITS_PER_WORD * 2 - 1.
1018 Doing this preserves semantics required by SHIFT_COUNT_TRUNCATED.
1019 In all other cases, shifts by values outside [0, BITS_PER_UNIT * 2)
1022 BINOPTAB, UNSIGNEDP and METHODS are as for expand_binop. This function
1023 may not use INTO_INPUT after modifying INTO_TARGET, and similarly for
1024 OUTOF_INPUT and OUTOF_TARGET. OUTOF_TARGET can be null if the parent
1025 function wants to calculate it itself.
1027 Return true if the shift could be successfully synthesized. */
1030 expand_doubleword_shift (enum machine_mode op1_mode
, optab binoptab
,
1031 rtx outof_input
, rtx into_input
, rtx op1
,
1032 rtx outof_target
, rtx into_target
,
1033 int unsignedp
, enum optab_methods methods
,
1034 unsigned HOST_WIDE_INT shift_mask
)
1036 rtx superword_op1
, tmp
, cmp1
, cmp2
;
1037 rtx subword_label
, done_label
;
1038 enum rtx_code cmp_code
;
1040 /* See if word-mode shifts by BITS_PER_WORD...BITS_PER_WORD * 2 - 1 will
1041 fill the result with sign or zero bits as appropriate. If so, the value
1042 of OUTOF_TARGET will always be (SHIFT OUTOF_INPUT OP1). Recursively call
1043 this routine to calculate INTO_TARGET (which depends on both OUTOF_INPUT
1044 and INTO_INPUT), then emit code to set up OUTOF_TARGET.
1046 This isn't worthwhile for constant shifts since the optimizers will
1047 cope better with in-range shift counts. */
1048 if (shift_mask
>= BITS_PER_WORD
1049 && outof_target
!= 0
1050 && !CONSTANT_P (op1
))
1052 if (!expand_doubleword_shift (op1_mode
, binoptab
,
1053 outof_input
, into_input
, op1
,
1055 unsignedp
, methods
, shift_mask
))
1057 if (!force_expand_binop (word_mode
, binoptab
, outof_input
, op1
,
1058 outof_target
, unsignedp
, methods
))
1063 /* Set CMP_CODE, CMP1 and CMP2 so that the rtx (CMP_CODE CMP1 CMP2)
1064 is true when the effective shift value is less than BITS_PER_WORD.
1065 Set SUPERWORD_OP1 to the shift count that should be used to shift
1066 OUTOF_INPUT into INTO_TARGET when the condition is false. */
1067 tmp
= immed_wide_int_const (wi::shwi (BITS_PER_WORD
, op1_mode
), op1_mode
);
1068 if (!CONSTANT_P (op1
) && shift_mask
== BITS_PER_WORD
- 1)
1070 /* Set CMP1 to OP1 & BITS_PER_WORD. The result is zero iff OP1
1071 is a subword shift count. */
1072 cmp1
= simplify_expand_binop (op1_mode
, and_optab
, op1
, tmp
,
1074 cmp2
= CONST0_RTX (op1_mode
);
1076 superword_op1
= op1
;
1080 /* Set CMP1 to OP1 - BITS_PER_WORD. */
1081 cmp1
= simplify_expand_binop (op1_mode
, sub_optab
, op1
, tmp
,
1083 cmp2
= CONST0_RTX (op1_mode
);
1085 superword_op1
= cmp1
;
1090 /* If we can compute the condition at compile time, pick the
1091 appropriate subroutine. */
1092 tmp
= simplify_relational_operation (cmp_code
, SImode
, op1_mode
, cmp1
, cmp2
);
1093 if (tmp
!= 0 && CONST_INT_P (tmp
))
1095 if (tmp
== const0_rtx
)
1096 return expand_superword_shift (binoptab
, outof_input
, superword_op1
,
1097 outof_target
, into_target
,
1098 unsignedp
, methods
);
1100 return expand_subword_shift (op1_mode
, binoptab
,
1101 outof_input
, into_input
, op1
,
1102 outof_target
, into_target
,
1103 unsignedp
, methods
, shift_mask
);
1106 #ifdef HAVE_conditional_move
1107 /* Try using conditional moves to generate straight-line code. */
1109 rtx_insn
*start
= get_last_insn ();
1110 if (expand_doubleword_shift_condmove (op1_mode
, binoptab
,
1111 cmp_code
, cmp1
, cmp2
,
1112 outof_input
, into_input
,
1114 outof_target
, into_target
,
1115 unsignedp
, methods
, shift_mask
))
1117 delete_insns_since (start
);
1121 /* As a last resort, use branches to select the correct alternative. */
1122 subword_label
= gen_label_rtx ();
1123 done_label
= gen_label_rtx ();
1126 do_compare_rtx_and_jump (cmp1
, cmp2
, cmp_code
, false, op1_mode
,
1127 0, 0, subword_label
, -1);
1130 if (!expand_superword_shift (binoptab
, outof_input
, superword_op1
,
1131 outof_target
, into_target
,
1132 unsignedp
, methods
))
1135 emit_jump_insn (gen_jump (done_label
));
1137 emit_label (subword_label
);
1139 if (!expand_subword_shift (op1_mode
, binoptab
,
1140 outof_input
, into_input
, op1
,
1141 outof_target
, into_target
,
1142 unsignedp
, methods
, shift_mask
))
1145 emit_label (done_label
);
1149 /* Subroutine of expand_binop. Perform a double word multiplication of
1150 operands OP0 and OP1 both of mode MODE, which is exactly twice as wide
1151 as the target's word_mode. This function return NULL_RTX if anything
1152 goes wrong, in which case it may have already emitted instructions
1153 which need to be deleted.
1155 If we want to multiply two two-word values and have normal and widening
1156 multiplies of single-word values, we can do this with three smaller
1159 The multiplication proceeds as follows:
1160 _______________________
1161 [__op0_high_|__op0_low__]
1162 _______________________
1163 * [__op1_high_|__op1_low__]
1164 _______________________________________________
1165 _______________________
1166 (1) [__op0_low__*__op1_low__]
1167 _______________________
1168 (2a) [__op0_low__*__op1_high_]
1169 _______________________
1170 (2b) [__op0_high_*__op1_low__]
1171 _______________________
1172 (3) [__op0_high_*__op1_high_]
1175 This gives a 4-word result. Since we are only interested in the
1176 lower 2 words, partial result (3) and the upper words of (2a) and
1177 (2b) don't need to be calculated. Hence (2a) and (2b) can be
1178 calculated using non-widening multiplication.
1180 (1), however, needs to be calculated with an unsigned widening
1181 multiplication. If this operation is not directly supported we
1182 try using a signed widening multiplication and adjust the result.
1183 This adjustment works as follows:
1185 If both operands are positive then no adjustment is needed.
1187 If the operands have different signs, for example op0_low < 0 and
1188 op1_low >= 0, the instruction treats the most significant bit of
1189 op0_low as a sign bit instead of a bit with significance
1190 2**(BITS_PER_WORD-1), i.e. the instruction multiplies op1_low
1191 with 2**BITS_PER_WORD - op0_low, and two's complements the
1192 result. Conclusion: We need to add op1_low * 2**BITS_PER_WORD to
1195 Similarly, if both operands are negative, we need to add
1196 (op0_low + op1_low) * 2**BITS_PER_WORD.
1198 We use a trick to adjust quickly. We logically shift op0_low right
1199 (op1_low) BITS_PER_WORD-1 steps to get 0 or 1, and add this to
1200 op0_high (op1_high) before it is used to calculate 2b (2a). If no
1201 logical shift exists, we do an arithmetic right shift and subtract
1205 expand_doubleword_mult (enum machine_mode mode
, rtx op0
, rtx op1
, rtx target
,
1206 bool umulp
, enum optab_methods methods
)
1208 int low
= (WORDS_BIG_ENDIAN
? 1 : 0);
1209 int high
= (WORDS_BIG_ENDIAN
? 0 : 1);
1210 rtx wordm1
= umulp
? NULL_RTX
: GEN_INT (BITS_PER_WORD
- 1);
1211 rtx product
, adjust
, product_high
, temp
;
1213 rtx op0_high
= operand_subword_force (op0
, high
, mode
);
1214 rtx op0_low
= operand_subword_force (op0
, low
, mode
);
1215 rtx op1_high
= operand_subword_force (op1
, high
, mode
);
1216 rtx op1_low
= operand_subword_force (op1
, low
, mode
);
1218 /* If we're using an unsigned multiply to directly compute the product
1219 of the low-order words of the operands and perform any required
1220 adjustments of the operands, we begin by trying two more multiplications
1221 and then computing the appropriate sum.
1223 We have checked above that the required addition is provided.
1224 Full-word addition will normally always succeed, especially if
1225 it is provided at all, so we don't worry about its failure. The
1226 multiplication may well fail, however, so we do handle that. */
1230 /* ??? This could be done with emit_store_flag where available. */
1231 temp
= expand_binop (word_mode
, lshr_optab
, op0_low
, wordm1
,
1232 NULL_RTX
, 1, methods
);
1234 op0_high
= expand_binop (word_mode
, add_optab
, op0_high
, temp
,
1235 NULL_RTX
, 0, OPTAB_DIRECT
);
1238 temp
= expand_binop (word_mode
, ashr_optab
, op0_low
, wordm1
,
1239 NULL_RTX
, 0, methods
);
1242 op0_high
= expand_binop (word_mode
, sub_optab
, op0_high
, temp
,
1243 NULL_RTX
, 0, OPTAB_DIRECT
);
1250 adjust
= expand_binop (word_mode
, smul_optab
, op0_high
, op1_low
,
1251 NULL_RTX
, 0, OPTAB_DIRECT
);
1255 /* OP0_HIGH should now be dead. */
1259 /* ??? This could be done with emit_store_flag where available. */
1260 temp
= expand_binop (word_mode
, lshr_optab
, op1_low
, wordm1
,
1261 NULL_RTX
, 1, methods
);
1263 op1_high
= expand_binop (word_mode
, add_optab
, op1_high
, temp
,
1264 NULL_RTX
, 0, OPTAB_DIRECT
);
1267 temp
= expand_binop (word_mode
, ashr_optab
, op1_low
, wordm1
,
1268 NULL_RTX
, 0, methods
);
1271 op1_high
= expand_binop (word_mode
, sub_optab
, op1_high
, temp
,
1272 NULL_RTX
, 0, OPTAB_DIRECT
);
1279 temp
= expand_binop (word_mode
, smul_optab
, op1_high
, op0_low
,
1280 NULL_RTX
, 0, OPTAB_DIRECT
);
1284 /* OP1_HIGH should now be dead. */
1286 adjust
= expand_binop (word_mode
, add_optab
, adjust
, temp
,
1287 NULL_RTX
, 0, OPTAB_DIRECT
);
1289 if (target
&& !REG_P (target
))
1293 product
= expand_binop (mode
, umul_widen_optab
, op0_low
, op1_low
,
1294 target
, 1, OPTAB_DIRECT
);
1296 product
= expand_binop (mode
, smul_widen_optab
, op0_low
, op1_low
,
1297 target
, 1, OPTAB_DIRECT
);
1302 product_high
= operand_subword (product
, high
, 1, mode
);
1303 adjust
= expand_binop (word_mode
, add_optab
, product_high
, adjust
,
1304 NULL_RTX
, 0, OPTAB_DIRECT
);
1305 emit_move_insn (product_high
, adjust
);
1309 /* Wrapper around expand_binop which takes an rtx code to specify
1310 the operation to perform, not an optab pointer. All other
1311 arguments are the same. */
1313 expand_simple_binop (enum machine_mode mode
, enum rtx_code code
, rtx op0
,
1314 rtx op1
, rtx target
, int unsignedp
,
1315 enum optab_methods methods
)
1317 optab binop
= code_to_optab (code
);
1320 return expand_binop (mode
, binop
, op0
, op1
, target
, unsignedp
, methods
);
1323 /* Return whether OP0 and OP1 should be swapped when expanding a commutative
1324 binop. Order them according to commutative_operand_precedence and, if
1325 possible, try to put TARGET or a pseudo first. */
1327 swap_commutative_operands_with_target (rtx target
, rtx op0
, rtx op1
)
1329 int op0_prec
= commutative_operand_precedence (op0
);
1330 int op1_prec
= commutative_operand_precedence (op1
);
1332 if (op0_prec
< op1_prec
)
1335 if (op0_prec
> op1_prec
)
1338 /* With equal precedence, both orders are ok, but it is better if the
1339 first operand is TARGET, or if both TARGET and OP0 are pseudos. */
1340 if (target
== 0 || REG_P (target
))
1341 return (REG_P (op1
) && !REG_P (op0
)) || target
== op1
;
1343 return rtx_equal_p (op1
, target
);
1346 /* Return true if BINOPTAB implements a shift operation. */
1349 shift_optab_p (optab binoptab
)
1351 switch (optab_to_code (binoptab
))
1367 /* Return true if BINOPTAB implements a commutative binary operation. */
1370 commutative_optab_p (optab binoptab
)
1372 return (GET_RTX_CLASS (optab_to_code (binoptab
)) == RTX_COMM_ARITH
1373 || binoptab
== smul_widen_optab
1374 || binoptab
== umul_widen_optab
1375 || binoptab
== smul_highpart_optab
1376 || binoptab
== umul_highpart_optab
);
1379 /* X is to be used in mode MODE as operand OPN to BINOPTAB. If we're
1380 optimizing, and if the operand is a constant that costs more than
1381 1 instruction, force the constant into a register and return that
1382 register. Return X otherwise. UNSIGNEDP says whether X is unsigned. */
1385 avoid_expensive_constant (enum machine_mode mode
, optab binoptab
,
1386 int opn
, rtx x
, bool unsignedp
)
1388 bool speed
= optimize_insn_for_speed_p ();
1390 if (mode
!= VOIDmode
1393 && (rtx_cost (x
, optab_to_code (binoptab
), opn
, speed
)
1394 > set_src_cost (x
, speed
)))
1396 if (CONST_INT_P (x
))
1398 HOST_WIDE_INT intval
= trunc_int_for_mode (INTVAL (x
), mode
);
1399 if (intval
!= INTVAL (x
))
1400 x
= GEN_INT (intval
);
1403 x
= convert_modes (mode
, VOIDmode
, x
, unsignedp
);
1404 x
= force_reg (mode
, x
);
1409 /* Helper function for expand_binop: handle the case where there
1410 is an insn that directly implements the indicated operation.
1411 Returns null if this is not possible. */
1413 expand_binop_directly (enum machine_mode mode
, optab binoptab
,
1415 rtx target
, int unsignedp
, enum optab_methods methods
,
1418 enum machine_mode from_mode
= widened_mode (mode
, op0
, op1
);
1419 enum insn_code icode
= find_widening_optab_handler (binoptab
, mode
,
1421 enum machine_mode xmode0
= insn_data
[(int) icode
].operand
[1].mode
;
1422 enum machine_mode xmode1
= insn_data
[(int) icode
].operand
[2].mode
;
1423 enum machine_mode mode0
, mode1
, tmp_mode
;
1424 struct expand_operand ops
[3];
1427 rtx xop0
= op0
, xop1
= op1
;
1430 /* If it is a commutative operator and the modes would match
1431 if we would swap the operands, we can save the conversions. */
1432 commutative_p
= commutative_optab_p (binoptab
);
1434 && GET_MODE (xop0
) != xmode0
&& GET_MODE (xop1
) != xmode1
1435 && GET_MODE (xop0
) == xmode1
&& GET_MODE (xop1
) == xmode1
)
1442 /* If we are optimizing, force expensive constants into a register. */
1443 xop0
= avoid_expensive_constant (xmode0
, binoptab
, 0, xop0
, unsignedp
);
1444 if (!shift_optab_p (binoptab
))
1445 xop1
= avoid_expensive_constant (xmode1
, binoptab
, 1, xop1
, unsignedp
);
1447 /* In case the insn wants input operands in modes different from
1448 those of the actual operands, convert the operands. It would
1449 seem that we don't need to convert CONST_INTs, but we do, so
1450 that they're properly zero-extended, sign-extended or truncated
1453 mode0
= GET_MODE (xop0
) != VOIDmode
? GET_MODE (xop0
) : mode
;
1454 if (xmode0
!= VOIDmode
&& xmode0
!= mode0
)
1456 xop0
= convert_modes (xmode0
, mode0
, xop0
, unsignedp
);
1460 mode1
= GET_MODE (xop1
) != VOIDmode
? GET_MODE (xop1
) : mode
;
1461 if (xmode1
!= VOIDmode
&& xmode1
!= mode1
)
1463 xop1
= convert_modes (xmode1
, mode1
, xop1
, unsignedp
);
1467 /* If operation is commutative,
1468 try to make the first operand a register.
1469 Even better, try to make it the same as the target.
1470 Also try to make the last operand a constant. */
1472 && swap_commutative_operands_with_target (target
, xop0
, xop1
))
1479 /* Now, if insn's predicates don't allow our operands, put them into
1482 if (binoptab
== vec_pack_trunc_optab
1483 || binoptab
== vec_pack_usat_optab
1484 || binoptab
== vec_pack_ssat_optab
1485 || binoptab
== vec_pack_ufix_trunc_optab
1486 || binoptab
== vec_pack_sfix_trunc_optab
)
1488 /* The mode of the result is different then the mode of the
1490 tmp_mode
= insn_data
[(int) icode
].operand
[0].mode
;
1491 if (GET_MODE_NUNITS (tmp_mode
) != 2 * GET_MODE_NUNITS (mode
))
1493 delete_insns_since (last
);
1500 create_output_operand (&ops
[0], target
, tmp_mode
);
1501 create_input_operand (&ops
[1], xop0
, mode0
);
1502 create_input_operand (&ops
[2], xop1
, mode1
);
1503 pat
= maybe_gen_insn (icode
, 3, ops
);
1506 /* If PAT is composed of more than one insn, try to add an appropriate
1507 REG_EQUAL note to it. If we can't because TEMP conflicts with an
1508 operand, call expand_binop again, this time without a target. */
1509 if (INSN_P (pat
) && NEXT_INSN (as_a
<rtx_insn
*> (pat
)) != NULL_RTX
1510 && ! add_equal_note (as_a
<rtx_insn
*> (pat
), ops
[0].value
,
1511 optab_to_code (binoptab
),
1512 ops
[1].value
, ops
[2].value
))
1514 delete_insns_since (last
);
1515 return expand_binop (mode
, binoptab
, op0
, op1
, NULL_RTX
,
1516 unsignedp
, methods
);
1520 return ops
[0].value
;
1522 delete_insns_since (last
);
1526 /* Generate code to perform an operation specified by BINOPTAB
1527 on operands OP0 and OP1, with result having machine-mode MODE.
1529 UNSIGNEDP is for the case where we have to widen the operands
1530 to perform the operation. It says to use zero-extension.
1532 If TARGET is nonzero, the value
1533 is generated there, if it is convenient to do so.
1534 In all cases an rtx is returned for the locus of the value;
1535 this may or may not be TARGET. */
1538 expand_binop (enum machine_mode mode
, optab binoptab
, rtx op0
, rtx op1
,
1539 rtx target
, int unsignedp
, enum optab_methods methods
)
1541 enum optab_methods next_methods
1542 = (methods
== OPTAB_LIB
|| methods
== OPTAB_LIB_WIDEN
1543 ? OPTAB_WIDEN
: methods
);
1544 enum mode_class mclass
;
1545 enum machine_mode wider_mode
;
1548 rtx_insn
*entry_last
= get_last_insn ();
1551 mclass
= GET_MODE_CLASS (mode
);
1553 /* If subtracting an integer constant, convert this into an addition of
1554 the negated constant. */
1556 if (binoptab
== sub_optab
&& CONST_INT_P (op1
))
1558 op1
= negate_rtx (mode
, op1
);
1559 binoptab
= add_optab
;
1562 /* Record where to delete back to if we backtrack. */
1563 last
= get_last_insn ();
1565 /* If we can do it with a three-operand insn, do so. */
1567 if (methods
!= OPTAB_MUST_WIDEN
1568 && find_widening_optab_handler (binoptab
, mode
,
1569 widened_mode (mode
, op0
, op1
), 1)
1570 != CODE_FOR_nothing
)
1572 temp
= expand_binop_directly (mode
, binoptab
, op0
, op1
, target
,
1573 unsignedp
, methods
, last
);
1578 /* If we were trying to rotate, and that didn't work, try rotating
1579 the other direction before falling back to shifts and bitwise-or. */
1580 if (((binoptab
== rotl_optab
1581 && optab_handler (rotr_optab
, mode
) != CODE_FOR_nothing
)
1582 || (binoptab
== rotr_optab
1583 && optab_handler (rotl_optab
, mode
) != CODE_FOR_nothing
))
1584 && mclass
== MODE_INT
)
1586 optab otheroptab
= (binoptab
== rotl_optab
? rotr_optab
: rotl_optab
);
1588 unsigned int bits
= GET_MODE_PRECISION (mode
);
1590 if (CONST_INT_P (op1
))
1591 newop1
= GEN_INT (bits
- INTVAL (op1
));
1592 else if (targetm
.shift_truncation_mask (mode
) == bits
- 1)
1593 newop1
= negate_rtx (GET_MODE (op1
), op1
);
1595 newop1
= expand_binop (GET_MODE (op1
), sub_optab
,
1596 gen_int_mode (bits
, GET_MODE (op1
)), op1
,
1597 NULL_RTX
, unsignedp
, OPTAB_DIRECT
);
1599 temp
= expand_binop_directly (mode
, otheroptab
, op0
, newop1
,
1600 target
, unsignedp
, methods
, last
);
1605 /* If this is a multiply, see if we can do a widening operation that
1606 takes operands of this mode and makes a wider mode. */
1608 if (binoptab
== smul_optab
1609 && GET_MODE_2XWIDER_MODE (mode
) != VOIDmode
1610 && (widening_optab_handler ((unsignedp
? umul_widen_optab
1611 : smul_widen_optab
),
1612 GET_MODE_2XWIDER_MODE (mode
), mode
)
1613 != CODE_FOR_nothing
))
1615 temp
= expand_binop (GET_MODE_2XWIDER_MODE (mode
),
1616 unsignedp
? umul_widen_optab
: smul_widen_optab
,
1617 op0
, op1
, NULL_RTX
, unsignedp
, OPTAB_DIRECT
);
1621 if (GET_MODE_CLASS (mode
) == MODE_INT
1622 && TRULY_NOOP_TRUNCATION_MODES_P (mode
, GET_MODE (temp
)))
1623 return gen_lowpart (mode
, temp
);
1625 return convert_to_mode (mode
, temp
, unsignedp
);
1629 /* If this is a vector shift by a scalar, see if we can do a vector
1630 shift by a vector. If so, broadcast the scalar into a vector. */
1631 if (mclass
== MODE_VECTOR_INT
)
1633 optab otheroptab
= unknown_optab
;
1635 if (binoptab
== ashl_optab
)
1636 otheroptab
= vashl_optab
;
1637 else if (binoptab
== ashr_optab
)
1638 otheroptab
= vashr_optab
;
1639 else if (binoptab
== lshr_optab
)
1640 otheroptab
= vlshr_optab
;
1641 else if (binoptab
== rotl_optab
)
1642 otheroptab
= vrotl_optab
;
1643 else if (binoptab
== rotr_optab
)
1644 otheroptab
= vrotr_optab
;
1646 if (otheroptab
&& optab_handler (otheroptab
, mode
) != CODE_FOR_nothing
)
1648 rtx vop1
= expand_vector_broadcast (mode
, op1
);
1651 temp
= expand_binop_directly (mode
, otheroptab
, op0
, vop1
,
1652 target
, unsignedp
, methods
, last
);
1659 /* Look for a wider mode of the same class for which we think we
1660 can open-code the operation. Check for a widening multiply at the
1661 wider mode as well. */
1663 if (CLASS_HAS_WIDER_MODES_P (mclass
)
1664 && methods
!= OPTAB_DIRECT
&& methods
!= OPTAB_LIB
)
1665 for (wider_mode
= GET_MODE_WIDER_MODE (mode
);
1666 wider_mode
!= VOIDmode
;
1667 wider_mode
= GET_MODE_WIDER_MODE (wider_mode
))
1669 if (optab_handler (binoptab
, wider_mode
) != CODE_FOR_nothing
1670 || (binoptab
== smul_optab
1671 && GET_MODE_WIDER_MODE (wider_mode
) != VOIDmode
1672 && (find_widening_optab_handler ((unsignedp
1674 : smul_widen_optab
),
1675 GET_MODE_WIDER_MODE (wider_mode
),
1677 != CODE_FOR_nothing
)))
1679 rtx xop0
= op0
, xop1
= op1
;
1682 /* For certain integer operations, we need not actually extend
1683 the narrow operands, as long as we will truncate
1684 the results to the same narrowness. */
1686 if ((binoptab
== ior_optab
|| binoptab
== and_optab
1687 || binoptab
== xor_optab
1688 || binoptab
== add_optab
|| binoptab
== sub_optab
1689 || binoptab
== smul_optab
|| binoptab
== ashl_optab
)
1690 && mclass
== MODE_INT
)
1693 xop0
= avoid_expensive_constant (mode
, binoptab
, 0,
1695 if (binoptab
!= ashl_optab
)
1696 xop1
= avoid_expensive_constant (mode
, binoptab
, 1,
1700 xop0
= widen_operand (xop0
, wider_mode
, mode
, unsignedp
, no_extend
);
1702 /* The second operand of a shift must always be extended. */
1703 xop1
= widen_operand (xop1
, wider_mode
, mode
, unsignedp
,
1704 no_extend
&& binoptab
!= ashl_optab
);
1706 temp
= expand_binop (wider_mode
, binoptab
, xop0
, xop1
, NULL_RTX
,
1707 unsignedp
, OPTAB_DIRECT
);
1710 if (mclass
!= MODE_INT
1711 || !TRULY_NOOP_TRUNCATION_MODES_P (mode
, wider_mode
))
1714 target
= gen_reg_rtx (mode
);
1715 convert_move (target
, temp
, 0);
1719 return gen_lowpart (mode
, temp
);
1722 delete_insns_since (last
);
1726 /* If operation is commutative,
1727 try to make the first operand a register.
1728 Even better, try to make it the same as the target.
1729 Also try to make the last operand a constant. */
1730 if (commutative_optab_p (binoptab
)
1731 && swap_commutative_operands_with_target (target
, op0
, op1
))
1738 /* These can be done a word at a time. */
1739 if ((binoptab
== and_optab
|| binoptab
== ior_optab
|| binoptab
== xor_optab
)
1740 && mclass
== MODE_INT
1741 && GET_MODE_SIZE (mode
) > UNITS_PER_WORD
1742 && optab_handler (binoptab
, word_mode
) != CODE_FOR_nothing
)
1747 /* If TARGET is the same as one of the operands, the REG_EQUAL note
1748 won't be accurate, so use a new target. */
1752 || !valid_multiword_target_p (target
))
1753 target
= gen_reg_rtx (mode
);
1757 /* Do the actual arithmetic. */
1758 for (i
= 0; i
< GET_MODE_BITSIZE (mode
) / BITS_PER_WORD
; i
++)
1760 rtx target_piece
= operand_subword (target
, i
, 1, mode
);
1761 rtx x
= expand_binop (word_mode
, binoptab
,
1762 operand_subword_force (op0
, i
, mode
),
1763 operand_subword_force (op1
, i
, mode
),
1764 target_piece
, unsignedp
, next_methods
);
1769 if (target_piece
!= x
)
1770 emit_move_insn (target_piece
, x
);
1773 insns
= get_insns ();
1776 if (i
== GET_MODE_BITSIZE (mode
) / BITS_PER_WORD
)
1783 /* Synthesize double word shifts from single word shifts. */
1784 if ((binoptab
== lshr_optab
|| binoptab
== ashl_optab
1785 || binoptab
== ashr_optab
)
1786 && mclass
== MODE_INT
1787 && (CONST_INT_P (op1
) || optimize_insn_for_speed_p ())
1788 && GET_MODE_SIZE (mode
) == 2 * UNITS_PER_WORD
1789 && GET_MODE_PRECISION (mode
) == GET_MODE_BITSIZE (mode
)
1790 && optab_handler (binoptab
, word_mode
) != CODE_FOR_nothing
1791 && optab_handler (ashl_optab
, word_mode
) != CODE_FOR_nothing
1792 && optab_handler (lshr_optab
, word_mode
) != CODE_FOR_nothing
)
1794 unsigned HOST_WIDE_INT shift_mask
, double_shift_mask
;
1795 enum machine_mode op1_mode
;
1797 double_shift_mask
= targetm
.shift_truncation_mask (mode
);
1798 shift_mask
= targetm
.shift_truncation_mask (word_mode
);
1799 op1_mode
= GET_MODE (op1
) != VOIDmode
? GET_MODE (op1
) : word_mode
;
1801 /* Apply the truncation to constant shifts. */
1802 if (double_shift_mask
> 0 && CONST_INT_P (op1
))
1803 op1
= GEN_INT (INTVAL (op1
) & double_shift_mask
);
1805 if (op1
== CONST0_RTX (op1_mode
))
1808 /* Make sure that this is a combination that expand_doubleword_shift
1809 can handle. See the comments there for details. */
1810 if (double_shift_mask
== 0
1811 || (shift_mask
== BITS_PER_WORD
- 1
1812 && double_shift_mask
== BITS_PER_WORD
* 2 - 1))
1815 rtx into_target
, outof_target
;
1816 rtx into_input
, outof_input
;
1817 int left_shift
, outof_word
;
1819 /* If TARGET is the same as one of the operands, the REG_EQUAL note
1820 won't be accurate, so use a new target. */
1824 || !valid_multiword_target_p (target
))
1825 target
= gen_reg_rtx (mode
);
1829 /* OUTOF_* is the word we are shifting bits away from, and
1830 INTO_* is the word that we are shifting bits towards, thus
1831 they differ depending on the direction of the shift and
1832 WORDS_BIG_ENDIAN. */
1834 left_shift
= binoptab
== ashl_optab
;
1835 outof_word
= left_shift
^ ! WORDS_BIG_ENDIAN
;
1837 outof_target
= operand_subword (target
, outof_word
, 1, mode
);
1838 into_target
= operand_subword (target
, 1 - outof_word
, 1, mode
);
1840 outof_input
= operand_subword_force (op0
, outof_word
, mode
);
1841 into_input
= operand_subword_force (op0
, 1 - outof_word
, mode
);
1843 if (expand_doubleword_shift (op1_mode
, binoptab
,
1844 outof_input
, into_input
, op1
,
1845 outof_target
, into_target
,
1846 unsignedp
, next_methods
, shift_mask
))
1848 insns
= get_insns ();
1858 /* Synthesize double word rotates from single word shifts. */
1859 if ((binoptab
== rotl_optab
|| binoptab
== rotr_optab
)
1860 && mclass
== MODE_INT
1861 && CONST_INT_P (op1
)
1862 && GET_MODE_PRECISION (mode
) == 2 * BITS_PER_WORD
1863 && optab_handler (ashl_optab
, word_mode
) != CODE_FOR_nothing
1864 && optab_handler (lshr_optab
, word_mode
) != CODE_FOR_nothing
)
1867 rtx into_target
, outof_target
;
1868 rtx into_input
, outof_input
;
1870 int shift_count
, left_shift
, outof_word
;
1872 /* If TARGET is the same as one of the operands, the REG_EQUAL note
1873 won't be accurate, so use a new target. Do this also if target is not
1874 a REG, first because having a register instead may open optimization
1875 opportunities, and second because if target and op0 happen to be MEMs
1876 designating the same location, we would risk clobbering it too early
1877 in the code sequence we generate below. */
1882 || !valid_multiword_target_p (target
))
1883 target
= gen_reg_rtx (mode
);
1887 shift_count
= INTVAL (op1
);
1889 /* OUTOF_* is the word we are shifting bits away from, and
1890 INTO_* is the word that we are shifting bits towards, thus
1891 they differ depending on the direction of the shift and
1892 WORDS_BIG_ENDIAN. */
1894 left_shift
= (binoptab
== rotl_optab
);
1895 outof_word
= left_shift
^ ! WORDS_BIG_ENDIAN
;
1897 outof_target
= operand_subword (target
, outof_word
, 1, mode
);
1898 into_target
= operand_subword (target
, 1 - outof_word
, 1, mode
);
1900 outof_input
= operand_subword_force (op0
, outof_word
, mode
);
1901 into_input
= operand_subword_force (op0
, 1 - outof_word
, mode
);
1903 if (shift_count
== BITS_PER_WORD
)
1905 /* This is just a word swap. */
1906 emit_move_insn (outof_target
, into_input
);
1907 emit_move_insn (into_target
, outof_input
);
1912 rtx into_temp1
, into_temp2
, outof_temp1
, outof_temp2
;
1913 rtx first_shift_count
, second_shift_count
;
1914 optab reverse_unsigned_shift
, unsigned_shift
;
1916 reverse_unsigned_shift
= (left_shift
^ (shift_count
< BITS_PER_WORD
)
1917 ? lshr_optab
: ashl_optab
);
1919 unsigned_shift
= (left_shift
^ (shift_count
< BITS_PER_WORD
)
1920 ? ashl_optab
: lshr_optab
);
1922 if (shift_count
> BITS_PER_WORD
)
1924 first_shift_count
= GEN_INT (shift_count
- BITS_PER_WORD
);
1925 second_shift_count
= GEN_INT (2 * BITS_PER_WORD
- shift_count
);
1929 first_shift_count
= GEN_INT (BITS_PER_WORD
- shift_count
);
1930 second_shift_count
= GEN_INT (shift_count
);
1933 into_temp1
= expand_binop (word_mode
, unsigned_shift
,
1934 outof_input
, first_shift_count
,
1935 NULL_RTX
, unsignedp
, next_methods
);
1936 into_temp2
= expand_binop (word_mode
, reverse_unsigned_shift
,
1937 into_input
, second_shift_count
,
1938 NULL_RTX
, unsignedp
, next_methods
);
1940 if (into_temp1
!= 0 && into_temp2
!= 0)
1941 inter
= expand_binop (word_mode
, ior_optab
, into_temp1
, into_temp2
,
1942 into_target
, unsignedp
, next_methods
);
1946 if (inter
!= 0 && inter
!= into_target
)
1947 emit_move_insn (into_target
, inter
);
1949 outof_temp1
= expand_binop (word_mode
, unsigned_shift
,
1950 into_input
, first_shift_count
,
1951 NULL_RTX
, unsignedp
, next_methods
);
1952 outof_temp2
= expand_binop (word_mode
, reverse_unsigned_shift
,
1953 outof_input
, second_shift_count
,
1954 NULL_RTX
, unsignedp
, next_methods
);
1956 if (inter
!= 0 && outof_temp1
!= 0 && outof_temp2
!= 0)
1957 inter
= expand_binop (word_mode
, ior_optab
,
1958 outof_temp1
, outof_temp2
,
1959 outof_target
, unsignedp
, next_methods
);
1961 if (inter
!= 0 && inter
!= outof_target
)
1962 emit_move_insn (outof_target
, inter
);
1965 insns
= get_insns ();
1975 /* These can be done a word at a time by propagating carries. */
1976 if ((binoptab
== add_optab
|| binoptab
== sub_optab
)
1977 && mclass
== MODE_INT
1978 && GET_MODE_SIZE (mode
) >= 2 * UNITS_PER_WORD
1979 && optab_handler (binoptab
, word_mode
) != CODE_FOR_nothing
)
1982 optab otheroptab
= binoptab
== add_optab
? sub_optab
: add_optab
;
1983 const unsigned int nwords
= GET_MODE_BITSIZE (mode
) / BITS_PER_WORD
;
1984 rtx carry_in
= NULL_RTX
, carry_out
= NULL_RTX
;
1985 rtx xop0
, xop1
, xtarget
;
1987 /* We can handle either a 1 or -1 value for the carry. If STORE_FLAG
1988 value is one of those, use it. Otherwise, use 1 since it is the
1989 one easiest to get. */
1990 #if STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1
1991 int normalizep
= STORE_FLAG_VALUE
;
1996 /* Prepare the operands. */
1997 xop0
= force_reg (mode
, op0
);
1998 xop1
= force_reg (mode
, op1
);
2000 xtarget
= gen_reg_rtx (mode
);
2002 if (target
== 0 || !REG_P (target
) || !valid_multiword_target_p (target
))
2005 /* Indicate for flow that the entire target reg is being set. */
2007 emit_clobber (xtarget
);
2009 /* Do the actual arithmetic. */
2010 for (i
= 0; i
< nwords
; i
++)
2012 int index
= (WORDS_BIG_ENDIAN
? nwords
- i
- 1 : i
);
2013 rtx target_piece
= operand_subword (xtarget
, index
, 1, mode
);
2014 rtx op0_piece
= operand_subword_force (xop0
, index
, mode
);
2015 rtx op1_piece
= operand_subword_force (xop1
, index
, mode
);
2018 /* Main add/subtract of the input operands. */
2019 x
= expand_binop (word_mode
, binoptab
,
2020 op0_piece
, op1_piece
,
2021 target_piece
, unsignedp
, next_methods
);
2027 /* Store carry from main add/subtract. */
2028 carry_out
= gen_reg_rtx (word_mode
);
2029 carry_out
= emit_store_flag_force (carry_out
,
2030 (binoptab
== add_optab
2033 word_mode
, 1, normalizep
);
2040 /* Add/subtract previous carry to main result. */
2041 newx
= expand_binop (word_mode
,
2042 normalizep
== 1 ? binoptab
: otheroptab
,
2044 NULL_RTX
, 1, next_methods
);
2048 /* Get out carry from adding/subtracting carry in. */
2049 rtx carry_tmp
= gen_reg_rtx (word_mode
);
2050 carry_tmp
= emit_store_flag_force (carry_tmp
,
2051 (binoptab
== add_optab
2054 word_mode
, 1, normalizep
);
2056 /* Logical-ior the two poss. carry together. */
2057 carry_out
= expand_binop (word_mode
, ior_optab
,
2058 carry_out
, carry_tmp
,
2059 carry_out
, 0, next_methods
);
2063 emit_move_insn (target_piece
, newx
);
2067 if (x
!= target_piece
)
2068 emit_move_insn (target_piece
, x
);
2071 carry_in
= carry_out
;
2074 if (i
== GET_MODE_BITSIZE (mode
) / (unsigned) BITS_PER_WORD
)
2076 if (optab_handler (mov_optab
, mode
) != CODE_FOR_nothing
2077 || ! rtx_equal_p (target
, xtarget
))
2079 rtx temp
= emit_move_insn (target
, xtarget
);
2081 set_dst_reg_note (temp
, REG_EQUAL
,
2082 gen_rtx_fmt_ee (optab_to_code (binoptab
),
2083 mode
, copy_rtx (xop0
),
2094 delete_insns_since (last
);
2097 /* Attempt to synthesize double word multiplies using a sequence of word
2098 mode multiplications. We first attempt to generate a sequence using a
2099 more efficient unsigned widening multiply, and if that fails we then
2100 try using a signed widening multiply. */
2102 if (binoptab
== smul_optab
2103 && mclass
== MODE_INT
2104 && GET_MODE_SIZE (mode
) == 2 * UNITS_PER_WORD
2105 && optab_handler (smul_optab
, word_mode
) != CODE_FOR_nothing
2106 && optab_handler (add_optab
, word_mode
) != CODE_FOR_nothing
)
2108 rtx product
= NULL_RTX
;
2109 if (widening_optab_handler (umul_widen_optab
, mode
, word_mode
)
2110 != CODE_FOR_nothing
)
2112 product
= expand_doubleword_mult (mode
, op0
, op1
, target
,
2115 delete_insns_since (last
);
2118 if (product
== NULL_RTX
2119 && widening_optab_handler (smul_widen_optab
, mode
, word_mode
)
2120 != CODE_FOR_nothing
)
2122 product
= expand_doubleword_mult (mode
, op0
, op1
, target
,
2125 delete_insns_since (last
);
2128 if (product
!= NULL_RTX
)
2130 if (optab_handler (mov_optab
, mode
) != CODE_FOR_nothing
)
2132 temp
= emit_move_insn (target
? target
: product
, product
);
2133 set_dst_reg_note (temp
,
2135 gen_rtx_fmt_ee (MULT
, mode
,
2138 target
? target
: product
);
2144 /* It can't be open-coded in this mode.
2145 Use a library call if one is available and caller says that's ok. */
2147 libfunc
= optab_libfunc (binoptab
, mode
);
2149 && (methods
== OPTAB_LIB
|| methods
== OPTAB_LIB_WIDEN
))
2153 enum machine_mode op1_mode
= mode
;
2158 if (shift_optab_p (binoptab
))
2160 op1_mode
= targetm
.libgcc_shift_count_mode ();
2161 /* Specify unsigned here,
2162 since negative shift counts are meaningless. */
2163 op1x
= convert_to_mode (op1_mode
, op1
, 1);
2166 if (GET_MODE (op0
) != VOIDmode
2167 && GET_MODE (op0
) != mode
)
2168 op0
= convert_to_mode (mode
, op0
, unsignedp
);
2170 /* Pass 1 for NO_QUEUE so we don't lose any increments
2171 if the libcall is cse'd or moved. */
2172 value
= emit_library_call_value (libfunc
,
2173 NULL_RTX
, LCT_CONST
, mode
, 2,
2174 op0
, mode
, op1x
, op1_mode
);
2176 insns
= get_insns ();
2179 target
= gen_reg_rtx (mode
);
2180 emit_libcall_block_1 (insns
, target
, value
,
2181 gen_rtx_fmt_ee (optab_to_code (binoptab
),
2183 trapv_binoptab_p (binoptab
));
2188 delete_insns_since (last
);
2190 /* It can't be done in this mode. Can we do it in a wider mode? */
2192 if (! (methods
== OPTAB_WIDEN
|| methods
== OPTAB_LIB_WIDEN
2193 || methods
== OPTAB_MUST_WIDEN
))
2195 /* Caller says, don't even try. */
2196 delete_insns_since (entry_last
);
2200 /* Compute the value of METHODS to pass to recursive calls.
2201 Don't allow widening to be tried recursively. */
2203 methods
= (methods
== OPTAB_LIB_WIDEN
? OPTAB_LIB
: OPTAB_DIRECT
);
2205 /* Look for a wider mode of the same class for which it appears we can do
2208 if (CLASS_HAS_WIDER_MODES_P (mclass
))
2210 for (wider_mode
= GET_MODE_WIDER_MODE (mode
);
2211 wider_mode
!= VOIDmode
;
2212 wider_mode
= GET_MODE_WIDER_MODE (wider_mode
))
2214 if (find_widening_optab_handler (binoptab
, wider_mode
, mode
, 1)
2216 || (methods
== OPTAB_LIB
2217 && optab_libfunc (binoptab
, wider_mode
)))
2219 rtx xop0
= op0
, xop1
= op1
;
2222 /* For certain integer operations, we need not actually extend
2223 the narrow operands, as long as we will truncate
2224 the results to the same narrowness. */
2226 if ((binoptab
== ior_optab
|| binoptab
== and_optab
2227 || binoptab
== xor_optab
2228 || binoptab
== add_optab
|| binoptab
== sub_optab
2229 || binoptab
== smul_optab
|| binoptab
== ashl_optab
)
2230 && mclass
== MODE_INT
)
2233 xop0
= widen_operand (xop0
, wider_mode
, mode
,
2234 unsignedp
, no_extend
);
2236 /* The second operand of a shift must always be extended. */
2237 xop1
= widen_operand (xop1
, wider_mode
, mode
, unsignedp
,
2238 no_extend
&& binoptab
!= ashl_optab
);
2240 temp
= expand_binop (wider_mode
, binoptab
, xop0
, xop1
, NULL_RTX
,
2241 unsignedp
, methods
);
2244 if (mclass
!= MODE_INT
2245 || !TRULY_NOOP_TRUNCATION_MODES_P (mode
, wider_mode
))
2248 target
= gen_reg_rtx (mode
);
2249 convert_move (target
, temp
, 0);
2253 return gen_lowpart (mode
, temp
);
2256 delete_insns_since (last
);
2261 delete_insns_since (entry_last
);
2265 /* Expand a binary operator which has both signed and unsigned forms.
2266 UOPTAB is the optab for unsigned operations, and SOPTAB is for
2269 If we widen unsigned operands, we may use a signed wider operation instead
2270 of an unsigned wider operation, since the result would be the same. */
2273 sign_expand_binop (enum machine_mode mode
, optab uoptab
, optab soptab
,
2274 rtx op0
, rtx op1
, rtx target
, int unsignedp
,
2275 enum optab_methods methods
)
2278 optab direct_optab
= unsignedp
? uoptab
: soptab
;
2281 /* Do it without widening, if possible. */
2282 temp
= expand_binop (mode
, direct_optab
, op0
, op1
, target
,
2283 unsignedp
, OPTAB_DIRECT
);
2284 if (temp
|| methods
== OPTAB_DIRECT
)
2287 /* Try widening to a signed int. Disable any direct use of any
2288 signed insn in the current mode. */
2289 save_enable
= swap_optab_enable (soptab
, mode
, false);
2291 temp
= expand_binop (mode
, soptab
, op0
, op1
, target
,
2292 unsignedp
, OPTAB_WIDEN
);
2294 /* For unsigned operands, try widening to an unsigned int. */
2295 if (!temp
&& unsignedp
)
2296 temp
= expand_binop (mode
, uoptab
, op0
, op1
, target
,
2297 unsignedp
, OPTAB_WIDEN
);
2298 if (temp
|| methods
== OPTAB_WIDEN
)
2301 /* Use the right width libcall if that exists. */
2302 temp
= expand_binop (mode
, direct_optab
, op0
, op1
, target
,
2303 unsignedp
, OPTAB_LIB
);
2304 if (temp
|| methods
== OPTAB_LIB
)
2307 /* Must widen and use a libcall, use either signed or unsigned. */
2308 temp
= expand_binop (mode
, soptab
, op0
, op1
, target
,
2309 unsignedp
, methods
);
2310 if (!temp
&& unsignedp
)
2311 temp
= expand_binop (mode
, uoptab
, op0
, op1
, target
,
2312 unsignedp
, methods
);
2315 /* Undo the fiddling above. */
2317 swap_optab_enable (soptab
, mode
, true);
2321 /* Generate code to perform an operation specified by UNOPPTAB
2322 on operand OP0, with two results to TARG0 and TARG1.
2323 We assume that the order of the operands for the instruction
2324 is TARG0, TARG1, OP0.
2326 Either TARG0 or TARG1 may be zero, but what that means is that
2327 the result is not actually wanted. We will generate it into
2328 a dummy pseudo-reg and discard it. They may not both be zero.
2330 Returns 1 if this operation can be performed; 0 if not. */
2333 expand_twoval_unop (optab unoptab
, rtx op0
, rtx targ0
, rtx targ1
,
2336 enum machine_mode mode
= GET_MODE (targ0
? targ0
: targ1
);
2337 enum mode_class mclass
;
2338 enum machine_mode wider_mode
;
2339 rtx_insn
*entry_last
= get_last_insn ();
2342 mclass
= GET_MODE_CLASS (mode
);
2345 targ0
= gen_reg_rtx (mode
);
2347 targ1
= gen_reg_rtx (mode
);
2349 /* Record where to go back to if we fail. */
2350 last
= get_last_insn ();
2352 if (optab_handler (unoptab
, mode
) != CODE_FOR_nothing
)
2354 struct expand_operand ops
[3];
2355 enum insn_code icode
= optab_handler (unoptab
, mode
);
2357 create_fixed_operand (&ops
[0], targ0
);
2358 create_fixed_operand (&ops
[1], targ1
);
2359 create_convert_operand_from (&ops
[2], op0
, mode
, unsignedp
);
2360 if (maybe_expand_insn (icode
, 3, ops
))
2364 /* It can't be done in this mode. Can we do it in a wider mode? */
2366 if (CLASS_HAS_WIDER_MODES_P (mclass
))
2368 for (wider_mode
= GET_MODE_WIDER_MODE (mode
);
2369 wider_mode
!= VOIDmode
;
2370 wider_mode
= GET_MODE_WIDER_MODE (wider_mode
))
2372 if (optab_handler (unoptab
, wider_mode
) != CODE_FOR_nothing
)
2374 rtx t0
= gen_reg_rtx (wider_mode
);
2375 rtx t1
= gen_reg_rtx (wider_mode
);
2376 rtx cop0
= convert_modes (wider_mode
, mode
, op0
, unsignedp
);
2378 if (expand_twoval_unop (unoptab
, cop0
, t0
, t1
, unsignedp
))
2380 convert_move (targ0
, t0
, unsignedp
);
2381 convert_move (targ1
, t1
, unsignedp
);
2385 delete_insns_since (last
);
2390 delete_insns_since (entry_last
);
2394 /* Generate code to perform an operation specified by BINOPTAB
2395 on operands OP0 and OP1, with two results to TARG1 and TARG2.
2396 We assume that the order of the operands for the instruction
2397 is TARG0, OP0, OP1, TARG1, which would fit a pattern like
2398 [(set TARG0 (operate OP0 OP1)) (set TARG1 (operate ...))].
2400 Either TARG0 or TARG1 may be zero, but what that means is that
2401 the result is not actually wanted. We will generate it into
2402 a dummy pseudo-reg and discard it. They may not both be zero.
2404 Returns 1 if this operation can be performed; 0 if not. */
2407 expand_twoval_binop (optab binoptab
, rtx op0
, rtx op1
, rtx targ0
, rtx targ1
,
2410 enum machine_mode mode
= GET_MODE (targ0
? targ0
: targ1
);
2411 enum mode_class mclass
;
2412 enum machine_mode wider_mode
;
2413 rtx_insn
*entry_last
= get_last_insn ();
2416 mclass
= GET_MODE_CLASS (mode
);
2419 targ0
= gen_reg_rtx (mode
);
2421 targ1
= gen_reg_rtx (mode
);
2423 /* Record where to go back to if we fail. */
2424 last
= get_last_insn ();
2426 if (optab_handler (binoptab
, mode
) != CODE_FOR_nothing
)
2428 struct expand_operand ops
[4];
2429 enum insn_code icode
= optab_handler (binoptab
, mode
);
2430 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
2431 enum machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
2432 rtx xop0
= op0
, xop1
= op1
;
2434 /* If we are optimizing, force expensive constants into a register. */
2435 xop0
= avoid_expensive_constant (mode0
, binoptab
, 0, xop0
, unsignedp
);
2436 xop1
= avoid_expensive_constant (mode1
, binoptab
, 1, xop1
, unsignedp
);
2438 create_fixed_operand (&ops
[0], targ0
);
2439 create_convert_operand_from (&ops
[1], op0
, mode
, unsignedp
);
2440 create_convert_operand_from (&ops
[2], op1
, mode
, unsignedp
);
2441 create_fixed_operand (&ops
[3], targ1
);
2442 if (maybe_expand_insn (icode
, 4, ops
))
2444 delete_insns_since (last
);
2447 /* It can't be done in this mode. Can we do it in a wider mode? */
2449 if (CLASS_HAS_WIDER_MODES_P (mclass
))
2451 for (wider_mode
= GET_MODE_WIDER_MODE (mode
);
2452 wider_mode
!= VOIDmode
;
2453 wider_mode
= GET_MODE_WIDER_MODE (wider_mode
))
2455 if (optab_handler (binoptab
, wider_mode
) != CODE_FOR_nothing
)
2457 rtx t0
= gen_reg_rtx (wider_mode
);
2458 rtx t1
= gen_reg_rtx (wider_mode
);
2459 rtx cop0
= convert_modes (wider_mode
, mode
, op0
, unsignedp
);
2460 rtx cop1
= convert_modes (wider_mode
, mode
, op1
, unsignedp
);
2462 if (expand_twoval_binop (binoptab
, cop0
, cop1
,
2465 convert_move (targ0
, t0
, unsignedp
);
2466 convert_move (targ1
, t1
, unsignedp
);
2470 delete_insns_since (last
);
2475 delete_insns_since (entry_last
);
2479 /* Expand the two-valued library call indicated by BINOPTAB, but
2480 preserve only one of the values. If TARG0 is non-NULL, the first
2481 value is placed into TARG0; otherwise the second value is placed
2482 into TARG1. Exactly one of TARG0 and TARG1 must be non-NULL. The
2483 value stored into TARG0 or TARG1 is equivalent to (CODE OP0 OP1).
2484 This routine assumes that the value returned by the library call is
2485 as if the return value was of an integral mode twice as wide as the
2486 mode of OP0. Returns 1 if the call was successful. */
2489 expand_twoval_binop_libfunc (optab binoptab
, rtx op0
, rtx op1
,
2490 rtx targ0
, rtx targ1
, enum rtx_code code
)
2492 enum machine_mode mode
;
2493 enum machine_mode libval_mode
;
2498 /* Exactly one of TARG0 or TARG1 should be non-NULL. */
2499 gcc_assert (!targ0
!= !targ1
);
2501 mode
= GET_MODE (op0
);
2502 libfunc
= optab_libfunc (binoptab
, mode
);
2506 /* The value returned by the library function will have twice as
2507 many bits as the nominal MODE. */
2508 libval_mode
= smallest_mode_for_size (2 * GET_MODE_BITSIZE (mode
),
2511 libval
= emit_library_call_value (libfunc
, NULL_RTX
, LCT_CONST
,
2515 /* Get the part of VAL containing the value that we want. */
2516 libval
= simplify_gen_subreg (mode
, libval
, libval_mode
,
2517 targ0
? 0 : GET_MODE_SIZE (mode
));
2518 insns
= get_insns ();
2520 /* Move the into the desired location. */
2521 emit_libcall_block (insns
, targ0
? targ0
: targ1
, libval
,
2522 gen_rtx_fmt_ee (code
, mode
, op0
, op1
));
2528 /* Wrapper around expand_unop which takes an rtx code to specify
2529 the operation to perform, not an optab pointer. All other
2530 arguments are the same. */
2532 expand_simple_unop (enum machine_mode mode
, enum rtx_code code
, rtx op0
,
2533 rtx target
, int unsignedp
)
2535 optab unop
= code_to_optab (code
);
2538 return expand_unop (mode
, unop
, op0
, target
, unsignedp
);
2544 (clz:wide (zero_extend:wide x)) - ((width wide) - (width narrow)).
2546 A similar operation can be used for clrsb. UNOPTAB says which operation
2547 we are trying to expand. */
2549 widen_leading (enum machine_mode mode
, rtx op0
, rtx target
, optab unoptab
)
2551 enum mode_class mclass
= GET_MODE_CLASS (mode
);
2552 if (CLASS_HAS_WIDER_MODES_P (mclass
))
2554 enum machine_mode wider_mode
;
2555 for (wider_mode
= GET_MODE_WIDER_MODE (mode
);
2556 wider_mode
!= VOIDmode
;
2557 wider_mode
= GET_MODE_WIDER_MODE (wider_mode
))
2559 if (optab_handler (unoptab
, wider_mode
) != CODE_FOR_nothing
)
2564 last
= get_last_insn ();
2567 target
= gen_reg_rtx (mode
);
2568 xop0
= widen_operand (op0
, wider_mode
, mode
,
2569 unoptab
!= clrsb_optab
, false);
2570 temp
= expand_unop (wider_mode
, unoptab
, xop0
, NULL_RTX
,
2571 unoptab
!= clrsb_optab
);
2574 (wider_mode
, sub_optab
, temp
,
2575 gen_int_mode (GET_MODE_PRECISION (wider_mode
)
2576 - GET_MODE_PRECISION (mode
),
2578 target
, true, OPTAB_DIRECT
);
2580 delete_insns_since (last
);
2589 /* Try calculating clz of a double-word quantity as two clz's of word-sized
2590 quantities, choosing which based on whether the high word is nonzero. */
2592 expand_doubleword_clz (enum machine_mode mode
, rtx op0
, rtx target
)
2594 rtx xop0
= force_reg (mode
, op0
);
2595 rtx subhi
= gen_highpart (word_mode
, xop0
);
2596 rtx sublo
= gen_lowpart (word_mode
, xop0
);
2597 rtx_code_label
*hi0_label
= gen_label_rtx ();
2598 rtx_code_label
*after_label
= gen_label_rtx ();
2602 /* If we were not given a target, use a word_mode register, not a
2603 'mode' register. The result will fit, and nobody is expecting
2604 anything bigger (the return type of __builtin_clz* is int). */
2606 target
= gen_reg_rtx (word_mode
);
2608 /* In any case, write to a word_mode scratch in both branches of the
2609 conditional, so we can ensure there is a single move insn setting
2610 'target' to tag a REG_EQUAL note on. */
2611 result
= gen_reg_rtx (word_mode
);
2615 /* If the high word is not equal to zero,
2616 then clz of the full value is clz of the high word. */
2617 emit_cmp_and_jump_insns (subhi
, CONST0_RTX (word_mode
), EQ
, 0,
2618 word_mode
, true, hi0_label
);
2620 temp
= expand_unop_direct (word_mode
, clz_optab
, subhi
, result
, true);
2625 convert_move (result
, temp
, true);
2627 emit_jump_insn (gen_jump (after_label
));
2630 /* Else clz of the full value is clz of the low word plus the number
2631 of bits in the high word. */
2632 emit_label (hi0_label
);
2634 temp
= expand_unop_direct (word_mode
, clz_optab
, sublo
, 0, true);
2637 temp
= expand_binop (word_mode
, add_optab
, temp
,
2638 gen_int_mode (GET_MODE_BITSIZE (word_mode
), word_mode
),
2639 result
, true, OPTAB_DIRECT
);
2643 convert_move (result
, temp
, true);
2645 emit_label (after_label
);
2646 convert_move (target
, result
, true);
2651 add_equal_note (seq
, target
, CLZ
, xop0
, 0);
2663 (lshiftrt:wide (bswap:wide x) ((width wide) - (width narrow))). */
2665 widen_bswap (enum machine_mode mode
, rtx op0
, rtx target
)
2667 enum mode_class mclass
= GET_MODE_CLASS (mode
);
2668 enum machine_mode wider_mode
;
2672 if (!CLASS_HAS_WIDER_MODES_P (mclass
))
2675 for (wider_mode
= GET_MODE_WIDER_MODE (mode
);
2676 wider_mode
!= VOIDmode
;
2677 wider_mode
= GET_MODE_WIDER_MODE (wider_mode
))
2678 if (optab_handler (bswap_optab
, wider_mode
) != CODE_FOR_nothing
)
2683 last
= get_last_insn ();
2685 x
= widen_operand (op0
, wider_mode
, mode
, true, true);
2686 x
= expand_unop (wider_mode
, bswap_optab
, x
, NULL_RTX
, true);
2688 gcc_assert (GET_MODE_PRECISION (wider_mode
) == GET_MODE_BITSIZE (wider_mode
)
2689 && GET_MODE_PRECISION (mode
) == GET_MODE_BITSIZE (mode
));
2691 x
= expand_shift (RSHIFT_EXPR
, wider_mode
, x
,
2692 GET_MODE_BITSIZE (wider_mode
)
2693 - GET_MODE_BITSIZE (mode
),
2699 target
= gen_reg_rtx (mode
);
2700 emit_move_insn (target
, gen_lowpart (mode
, x
));
2703 delete_insns_since (last
);
2708 /* Try calculating bswap as two bswaps of two word-sized operands. */
2711 expand_doubleword_bswap (enum machine_mode mode
, rtx op
, rtx target
)
2715 t1
= expand_unop (word_mode
, bswap_optab
,
2716 operand_subword_force (op
, 0, mode
), NULL_RTX
, true);
2717 t0
= expand_unop (word_mode
, bswap_optab
,
2718 operand_subword_force (op
, 1, mode
), NULL_RTX
, true);
2720 if (target
== 0 || !valid_multiword_target_p (target
))
2721 target
= gen_reg_rtx (mode
);
2723 emit_clobber (target
);
2724 emit_move_insn (operand_subword (target
, 0, 1, mode
), t0
);
2725 emit_move_insn (operand_subword (target
, 1, 1, mode
), t1
);
2730 /* Try calculating (parity x) as (and (popcount x) 1), where
2731 popcount can also be done in a wider mode. */
2733 expand_parity (enum machine_mode mode
, rtx op0
, rtx target
)
2735 enum mode_class mclass
= GET_MODE_CLASS (mode
);
2736 if (CLASS_HAS_WIDER_MODES_P (mclass
))
2738 enum machine_mode wider_mode
;
2739 for (wider_mode
= mode
; wider_mode
!= VOIDmode
;
2740 wider_mode
= GET_MODE_WIDER_MODE (wider_mode
))
2742 if (optab_handler (popcount_optab
, wider_mode
) != CODE_FOR_nothing
)
2747 last
= get_last_insn ();
2750 target
= gen_reg_rtx (mode
);
2751 xop0
= widen_operand (op0
, wider_mode
, mode
, true, false);
2752 temp
= expand_unop (wider_mode
, popcount_optab
, xop0
, NULL_RTX
,
2755 temp
= expand_binop (wider_mode
, and_optab
, temp
, const1_rtx
,
2756 target
, true, OPTAB_DIRECT
);
2758 delete_insns_since (last
);
2767 /* Try calculating ctz(x) as K - clz(x & -x) ,
2768 where K is GET_MODE_PRECISION(mode) - 1.
2770 Both __builtin_ctz and __builtin_clz are undefined at zero, so we
2771 don't have to worry about what the hardware does in that case. (If
2772 the clz instruction produces the usual value at 0, which is K, the
2773 result of this code sequence will be -1; expand_ffs, below, relies
2774 on this. It might be nice to have it be K instead, for consistency
2775 with the (very few) processors that provide a ctz with a defined
2776 value, but that would take one more instruction, and it would be
2777 less convenient for expand_ffs anyway. */
2780 expand_ctz (enum machine_mode mode
, rtx op0
, rtx target
)
2785 if (optab_handler (clz_optab
, mode
) == CODE_FOR_nothing
)
2790 temp
= expand_unop_direct (mode
, neg_optab
, op0
, NULL_RTX
, true);
2792 temp
= expand_binop (mode
, and_optab
, op0
, temp
, NULL_RTX
,
2793 true, OPTAB_DIRECT
);
2795 temp
= expand_unop_direct (mode
, clz_optab
, temp
, NULL_RTX
, true);
2797 temp
= expand_binop (mode
, sub_optab
,
2798 gen_int_mode (GET_MODE_PRECISION (mode
) - 1, mode
),
2800 true, OPTAB_DIRECT
);
2810 add_equal_note (seq
, temp
, CTZ
, op0
, 0);
2816 /* Try calculating ffs(x) using ctz(x) if we have that instruction, or
2817 else with the sequence used by expand_clz.
2819 The ffs builtin promises to return zero for a zero value and ctz/clz
2820 may have an undefined value in that case. If they do not give us a
2821 convenient value, we have to generate a test and branch. */
2823 expand_ffs (enum machine_mode mode
, rtx op0
, rtx target
)
2825 HOST_WIDE_INT val
= 0;
2826 bool defined_at_zero
= false;
2830 if (optab_handler (ctz_optab
, mode
) != CODE_FOR_nothing
)
2834 temp
= expand_unop_direct (mode
, ctz_optab
, op0
, 0, true);
2838 defined_at_zero
= (CTZ_DEFINED_VALUE_AT_ZERO (mode
, val
) == 2);
2840 else if (optab_handler (clz_optab
, mode
) != CODE_FOR_nothing
)
2843 temp
= expand_ctz (mode
, op0
, 0);
2847 if (CLZ_DEFINED_VALUE_AT_ZERO (mode
, val
) == 2)
2849 defined_at_zero
= true;
2850 val
= (GET_MODE_PRECISION (mode
) - 1) - val
;
2856 if (defined_at_zero
&& val
== -1)
2857 /* No correction needed at zero. */;
2860 /* We don't try to do anything clever with the situation found
2861 on some processors (eg Alpha) where ctz(0:mode) ==
2862 bitsize(mode). If someone can think of a way to send N to -1
2863 and leave alone all values in the range 0..N-1 (where N is a
2864 power of two), cheaper than this test-and-branch, please add it.
2866 The test-and-branch is done after the operation itself, in case
2867 the operation sets condition codes that can be recycled for this.
2868 (This is true on i386, for instance.) */
2870 rtx_code_label
*nonzero_label
= gen_label_rtx ();
2871 emit_cmp_and_jump_insns (op0
, CONST0_RTX (mode
), NE
, 0,
2872 mode
, true, nonzero_label
);
2874 convert_move (temp
, GEN_INT (-1), false);
2875 emit_label (nonzero_label
);
2878 /* temp now has a value in the range -1..bitsize-1. ffs is supposed
2879 to produce a value in the range 0..bitsize. */
2880 temp
= expand_binop (mode
, add_optab
, temp
, gen_int_mode (1, mode
),
2881 target
, false, OPTAB_DIRECT
);
2888 add_equal_note (seq
, temp
, FFS
, op0
, 0);
2897 /* Extract the OMODE lowpart from VAL, which has IMODE. Under certain
2898 conditions, VAL may already be a SUBREG against which we cannot generate
2899 a further SUBREG. In this case, we expect forcing the value into a
2900 register will work around the situation. */
2903 lowpart_subreg_maybe_copy (enum machine_mode omode
, rtx val
,
2904 enum machine_mode imode
)
2907 ret
= lowpart_subreg (omode
, val
, imode
);
2910 val
= force_reg (imode
, val
);
2911 ret
= lowpart_subreg (omode
, val
, imode
);
2912 gcc_assert (ret
!= NULL
);
2917 /* Expand a floating point absolute value or negation operation via a
2918 logical operation on the sign bit. */
2921 expand_absneg_bit (enum rtx_code code
, enum machine_mode mode
,
2922 rtx op0
, rtx target
)
2924 const struct real_format
*fmt
;
2925 int bitpos
, word
, nwords
, i
;
2926 enum machine_mode imode
;
2930 /* The format has to have a simple sign bit. */
2931 fmt
= REAL_MODE_FORMAT (mode
);
2935 bitpos
= fmt
->signbit_rw
;
2939 /* Don't create negative zeros if the format doesn't support them. */
2940 if (code
== NEG
&& !fmt
->has_signed_zero
)
2943 if (GET_MODE_SIZE (mode
) <= UNITS_PER_WORD
)
2945 imode
= int_mode_for_mode (mode
);
2946 if (imode
== BLKmode
)
2955 if (FLOAT_WORDS_BIG_ENDIAN
)
2956 word
= (GET_MODE_BITSIZE (mode
) - bitpos
) / BITS_PER_WORD
;
2958 word
= bitpos
/ BITS_PER_WORD
;
2959 bitpos
= bitpos
% BITS_PER_WORD
;
2960 nwords
= (GET_MODE_BITSIZE (mode
) + BITS_PER_WORD
- 1) / BITS_PER_WORD
;
2963 wide_int mask
= wi::set_bit_in_zero (bitpos
, GET_MODE_PRECISION (imode
));
2969 || (nwords
> 1 && !valid_multiword_target_p (target
)))
2970 target
= gen_reg_rtx (mode
);
2976 for (i
= 0; i
< nwords
; ++i
)
2978 rtx targ_piece
= operand_subword (target
, i
, 1, mode
);
2979 rtx op0_piece
= operand_subword_force (op0
, i
, mode
);
2983 temp
= expand_binop (imode
, code
== ABS
? and_optab
: xor_optab
,
2985 immed_wide_int_const (mask
, imode
),
2986 targ_piece
, 1, OPTAB_LIB_WIDEN
);
2987 if (temp
!= targ_piece
)
2988 emit_move_insn (targ_piece
, temp
);
2991 emit_move_insn (targ_piece
, op0_piece
);
2994 insns
= get_insns ();
3001 temp
= expand_binop (imode
, code
== ABS
? and_optab
: xor_optab
,
3002 gen_lowpart (imode
, op0
),
3003 immed_wide_int_const (mask
, imode
),
3004 gen_lowpart (imode
, target
), 1, OPTAB_LIB_WIDEN
);
3005 target
= lowpart_subreg_maybe_copy (mode
, temp
, imode
);
3007 set_dst_reg_note (get_last_insn (), REG_EQUAL
,
3008 gen_rtx_fmt_e (code
, mode
, copy_rtx (op0
)),
3015 /* As expand_unop, but will fail rather than attempt the operation in a
3016 different mode or with a libcall. */
3018 expand_unop_direct (enum machine_mode mode
, optab unoptab
, rtx op0
, rtx target
,
3021 if (optab_handler (unoptab
, mode
) != CODE_FOR_nothing
)
3023 struct expand_operand ops
[2];
3024 enum insn_code icode
= optab_handler (unoptab
, mode
);
3025 rtx_insn
*last
= get_last_insn ();
3028 create_output_operand (&ops
[0], target
, mode
);
3029 create_convert_operand_from (&ops
[1], op0
, mode
, unsignedp
);
3030 pat
= maybe_gen_insn (icode
, 2, ops
);
3033 if (INSN_P (pat
) && NEXT_INSN (as_a
<rtx_insn
*> (pat
)) != NULL_RTX
3034 && ! add_equal_note (as_a
<rtx_insn
*> (pat
), ops
[0].value
,
3035 optab_to_code (unoptab
),
3036 ops
[1].value
, NULL_RTX
))
3038 delete_insns_since (last
);
3039 return expand_unop (mode
, unoptab
, op0
, NULL_RTX
, unsignedp
);
3044 return ops
[0].value
;
3050 /* Generate code to perform an operation specified by UNOPTAB
3051 on operand OP0, with result having machine-mode MODE.
3053 UNSIGNEDP is for the case where we have to widen the operands
3054 to perform the operation. It says to use zero-extension.
3056 If TARGET is nonzero, the value
3057 is generated there, if it is convenient to do so.
3058 In all cases an rtx is returned for the locus of the value;
3059 this may or may not be TARGET. */
3062 expand_unop (enum machine_mode mode
, optab unoptab
, rtx op0
, rtx target
,
3065 enum mode_class mclass
= GET_MODE_CLASS (mode
);
3066 enum machine_mode wider_mode
;
3070 temp
= expand_unop_direct (mode
, unoptab
, op0
, target
, unsignedp
);
3074 /* It can't be done in this mode. Can we open-code it in a wider mode? */
3076 /* Widening (or narrowing) clz needs special treatment. */
3077 if (unoptab
== clz_optab
)
3079 temp
= widen_leading (mode
, op0
, target
, unoptab
);
3083 if (GET_MODE_SIZE (mode
) == 2 * UNITS_PER_WORD
3084 && optab_handler (unoptab
, word_mode
) != CODE_FOR_nothing
)
3086 temp
= expand_doubleword_clz (mode
, op0
, target
);
3094 if (unoptab
== clrsb_optab
)
3096 temp
= widen_leading (mode
, op0
, target
, unoptab
);
3102 /* Widening (or narrowing) bswap needs special treatment. */
3103 if (unoptab
== bswap_optab
)
3105 /* HImode is special because in this mode BSWAP is equivalent to ROTATE
3106 or ROTATERT. First try these directly; if this fails, then try the
3107 obvious pair of shifts with allowed widening, as this will probably
3108 be always more efficient than the other fallback methods. */
3114 if (optab_handler (rotl_optab
, mode
) != CODE_FOR_nothing
)
3116 temp
= expand_binop (mode
, rotl_optab
, op0
, GEN_INT (8), target
,
3117 unsignedp
, OPTAB_DIRECT
);
3122 if (optab_handler (rotr_optab
, mode
) != CODE_FOR_nothing
)
3124 temp
= expand_binop (mode
, rotr_optab
, op0
, GEN_INT (8), target
,
3125 unsignedp
, OPTAB_DIRECT
);
3130 last
= get_last_insn ();
3132 temp1
= expand_binop (mode
, ashl_optab
, op0
, GEN_INT (8), NULL_RTX
,
3133 unsignedp
, OPTAB_WIDEN
);
3134 temp2
= expand_binop (mode
, lshr_optab
, op0
, GEN_INT (8), NULL_RTX
,
3135 unsignedp
, OPTAB_WIDEN
);
3138 temp
= expand_binop (mode
, ior_optab
, temp1
, temp2
, target
,
3139 unsignedp
, OPTAB_WIDEN
);
3144 delete_insns_since (last
);
3147 temp
= widen_bswap (mode
, op0
, target
);
3151 if (GET_MODE_SIZE (mode
) == 2 * UNITS_PER_WORD
3152 && optab_handler (unoptab
, word_mode
) != CODE_FOR_nothing
)
3154 temp
= expand_doubleword_bswap (mode
, op0
, target
);
3162 if (CLASS_HAS_WIDER_MODES_P (mclass
))
3163 for (wider_mode
= GET_MODE_WIDER_MODE (mode
);
3164 wider_mode
!= VOIDmode
;
3165 wider_mode
= GET_MODE_WIDER_MODE (wider_mode
))
3167 if (optab_handler (unoptab
, wider_mode
) != CODE_FOR_nothing
)
3170 rtx_insn
*last
= get_last_insn ();
3172 /* For certain operations, we need not actually extend
3173 the narrow operand, as long as we will truncate the
3174 results to the same narrowness. */
3176 xop0
= widen_operand (xop0
, wider_mode
, mode
, unsignedp
,
3177 (unoptab
== neg_optab
3178 || unoptab
== one_cmpl_optab
)
3179 && mclass
== MODE_INT
);
3181 temp
= expand_unop (wider_mode
, unoptab
, xop0
, NULL_RTX
,
3186 if (mclass
!= MODE_INT
3187 || !TRULY_NOOP_TRUNCATION_MODES_P (mode
, wider_mode
))
3190 target
= gen_reg_rtx (mode
);
3191 convert_move (target
, temp
, 0);
3195 return gen_lowpart (mode
, temp
);
3198 delete_insns_since (last
);
3202 /* These can be done a word at a time. */
3203 if (unoptab
== one_cmpl_optab
3204 && mclass
== MODE_INT
3205 && GET_MODE_SIZE (mode
) > UNITS_PER_WORD
3206 && optab_handler (unoptab
, word_mode
) != CODE_FOR_nothing
)
3211 if (target
== 0 || target
== op0
|| !valid_multiword_target_p (target
))
3212 target
= gen_reg_rtx (mode
);
3216 /* Do the actual arithmetic. */
3217 for (i
= 0; i
< GET_MODE_BITSIZE (mode
) / BITS_PER_WORD
; i
++)
3219 rtx target_piece
= operand_subword (target
, i
, 1, mode
);
3220 rtx x
= expand_unop (word_mode
, unoptab
,
3221 operand_subword_force (op0
, i
, mode
),
3222 target_piece
, unsignedp
);
3224 if (target_piece
!= x
)
3225 emit_move_insn (target_piece
, x
);
3228 insns
= get_insns ();
3235 if (optab_to_code (unoptab
) == NEG
)
3237 /* Try negating floating point values by flipping the sign bit. */
3238 if (SCALAR_FLOAT_MODE_P (mode
))
3240 temp
= expand_absneg_bit (NEG
, mode
, op0
, target
);
3245 /* If there is no negation pattern, and we have no negative zero,
3246 try subtracting from zero. */
3247 if (!HONOR_SIGNED_ZEROS (mode
))
3249 temp
= expand_binop (mode
, (unoptab
== negv_optab
3250 ? subv_optab
: sub_optab
),
3251 CONST0_RTX (mode
), op0
, target
,
3252 unsignedp
, OPTAB_DIRECT
);
3258 /* Try calculating parity (x) as popcount (x) % 2. */
3259 if (unoptab
== parity_optab
)
3261 temp
= expand_parity (mode
, op0
, target
);
3266 /* Try implementing ffs (x) in terms of clz (x). */
3267 if (unoptab
== ffs_optab
)
3269 temp
= expand_ffs (mode
, op0
, target
);
3274 /* Try implementing ctz (x) in terms of clz (x). */
3275 if (unoptab
== ctz_optab
)
3277 temp
= expand_ctz (mode
, op0
, target
);
3283 /* Now try a library call in this mode. */
3284 libfunc
= optab_libfunc (unoptab
, mode
);
3290 enum machine_mode outmode
= mode
;
3292 /* All of these functions return small values. Thus we choose to
3293 have them return something that isn't a double-word. */
3294 if (unoptab
== ffs_optab
|| unoptab
== clz_optab
|| unoptab
== ctz_optab
3295 || unoptab
== clrsb_optab
|| unoptab
== popcount_optab
3296 || unoptab
== parity_optab
)
3298 = GET_MODE (hard_libcall_value (TYPE_MODE (integer_type_node
),
3299 optab_libfunc (unoptab
, mode
)));
3303 /* Pass 1 for NO_QUEUE so we don't lose any increments
3304 if the libcall is cse'd or moved. */
3305 value
= emit_library_call_value (libfunc
, NULL_RTX
, LCT_CONST
, outmode
,
3307 insns
= get_insns ();
3310 target
= gen_reg_rtx (outmode
);
3311 eq_value
= gen_rtx_fmt_e (optab_to_code (unoptab
), mode
, op0
);
3312 if (GET_MODE_SIZE (outmode
) < GET_MODE_SIZE (mode
))
3313 eq_value
= simplify_gen_unary (TRUNCATE
, outmode
, eq_value
, mode
);
3314 else if (GET_MODE_SIZE (outmode
) > GET_MODE_SIZE (mode
))
3315 eq_value
= simplify_gen_unary (ZERO_EXTEND
, outmode
, eq_value
, mode
);
3316 emit_libcall_block_1 (insns
, target
, value
, eq_value
,
3317 trapv_unoptab_p (unoptab
));
3322 /* It can't be done in this mode. Can we do it in a wider mode? */
3324 if (CLASS_HAS_WIDER_MODES_P (mclass
))
3326 for (wider_mode
= GET_MODE_WIDER_MODE (mode
);
3327 wider_mode
!= VOIDmode
;
3328 wider_mode
= GET_MODE_WIDER_MODE (wider_mode
))
3330 if (optab_handler (unoptab
, wider_mode
) != CODE_FOR_nothing
3331 || optab_libfunc (unoptab
, wider_mode
))
3334 rtx_insn
*last
= get_last_insn ();
3336 /* For certain operations, we need not actually extend
3337 the narrow operand, as long as we will truncate the
3338 results to the same narrowness. */
3339 xop0
= widen_operand (xop0
, wider_mode
, mode
, unsignedp
,
3340 (unoptab
== neg_optab
3341 || unoptab
== one_cmpl_optab
3342 || unoptab
== bswap_optab
)
3343 && mclass
== MODE_INT
);
3345 temp
= expand_unop (wider_mode
, unoptab
, xop0
, NULL_RTX
,
3348 /* If we are generating clz using wider mode, adjust the
3349 result. Similarly for clrsb. */
3350 if ((unoptab
== clz_optab
|| unoptab
== clrsb_optab
)
3353 (wider_mode
, sub_optab
, temp
,
3354 gen_int_mode (GET_MODE_PRECISION (wider_mode
)
3355 - GET_MODE_PRECISION (mode
),
3357 target
, true, OPTAB_DIRECT
);
3359 /* Likewise for bswap. */
3360 if (unoptab
== bswap_optab
&& temp
!= 0)
3362 gcc_assert (GET_MODE_PRECISION (wider_mode
)
3363 == GET_MODE_BITSIZE (wider_mode
)
3364 && GET_MODE_PRECISION (mode
)
3365 == GET_MODE_BITSIZE (mode
));
3367 temp
= expand_shift (RSHIFT_EXPR
, wider_mode
, temp
,
3368 GET_MODE_BITSIZE (wider_mode
)
3369 - GET_MODE_BITSIZE (mode
),
3375 if (mclass
!= MODE_INT
)
3378 target
= gen_reg_rtx (mode
);
3379 convert_move (target
, temp
, 0);
3383 return gen_lowpart (mode
, temp
);
3386 delete_insns_since (last
);
3391 /* One final attempt at implementing negation via subtraction,
3392 this time allowing widening of the operand. */
3393 if (optab_to_code (unoptab
) == NEG
&& !HONOR_SIGNED_ZEROS (mode
))
3396 temp
= expand_binop (mode
,
3397 unoptab
== negv_optab
? subv_optab
: sub_optab
,
3398 CONST0_RTX (mode
), op0
,
3399 target
, unsignedp
, OPTAB_LIB_WIDEN
);
3407 /* Emit code to compute the absolute value of OP0, with result to
3408 TARGET if convenient. (TARGET may be 0.) The return value says
3409 where the result actually is to be found.
3411 MODE is the mode of the operand; the mode of the result is
3412 different but can be deduced from MODE.
3417 expand_abs_nojump (enum machine_mode mode
, rtx op0
, rtx target
,
3418 int result_unsignedp
)
3422 if (GET_MODE_CLASS (mode
) != MODE_INT
3424 result_unsignedp
= 1;
3426 /* First try to do it with a special abs instruction. */
3427 temp
= expand_unop (mode
, result_unsignedp
? abs_optab
: absv_optab
,
3432 /* For floating point modes, try clearing the sign bit. */
3433 if (SCALAR_FLOAT_MODE_P (mode
))
3435 temp
= expand_absneg_bit (ABS
, mode
, op0
, target
);
3440 /* If we have a MAX insn, we can do this as MAX (x, -x). */
3441 if (optab_handler (smax_optab
, mode
) != CODE_FOR_nothing
3442 && !HONOR_SIGNED_ZEROS (mode
))
3444 rtx_insn
*last
= get_last_insn ();
3446 temp
= expand_unop (mode
, result_unsignedp
? neg_optab
: negv_optab
,
3449 temp
= expand_binop (mode
, smax_optab
, op0
, temp
, target
, 0,
3455 delete_insns_since (last
);
3458 /* If this machine has expensive jumps, we can do integer absolute
3459 value of X as (((signed) x >> (W-1)) ^ x) - ((signed) x >> (W-1)),
3460 where W is the width of MODE. */
3462 if (GET_MODE_CLASS (mode
) == MODE_INT
3463 && BRANCH_COST (optimize_insn_for_speed_p (),
3466 rtx extended
= expand_shift (RSHIFT_EXPR
, mode
, op0
,
3467 GET_MODE_PRECISION (mode
) - 1,
3470 temp
= expand_binop (mode
, xor_optab
, extended
, op0
, target
, 0,
3473 temp
= expand_binop (mode
, result_unsignedp
? sub_optab
: subv_optab
,
3474 temp
, extended
, target
, 0, OPTAB_LIB_WIDEN
);
3484 expand_abs (enum machine_mode mode
, rtx op0
, rtx target
,
3485 int result_unsignedp
, int safe
)
3488 rtx_code_label
*op1
;
3490 if (GET_MODE_CLASS (mode
) != MODE_INT
3492 result_unsignedp
= 1;
3494 temp
= expand_abs_nojump (mode
, op0
, target
, result_unsignedp
);
3498 /* If that does not win, use conditional jump and negate. */
3500 /* It is safe to use the target if it is the same
3501 as the source if this is also a pseudo register */
3502 if (op0
== target
&& REG_P (op0
)
3503 && REGNO (op0
) >= FIRST_PSEUDO_REGISTER
)
3506 op1
= gen_label_rtx ();
3507 if (target
== 0 || ! safe
3508 || GET_MODE (target
) != mode
3509 || (MEM_P (target
) && MEM_VOLATILE_P (target
))
3511 && REGNO (target
) < FIRST_PSEUDO_REGISTER
))
3512 target
= gen_reg_rtx (mode
);
3514 emit_move_insn (target
, op0
);
3517 do_compare_rtx_and_jump (target
, CONST0_RTX (mode
), GE
, 0, mode
,
3518 NULL_RTX
, NULL_RTX
, op1
, -1);
3520 op0
= expand_unop (mode
, result_unsignedp
? neg_optab
: negv_optab
,
3523 emit_move_insn (target
, op0
);
3529 /* Emit code to compute the one's complement absolute value of OP0
3530 (if (OP0 < 0) OP0 = ~OP0), with result to TARGET if convenient.
3531 (TARGET may be NULL_RTX.) The return value says where the result
3532 actually is to be found.
3534 MODE is the mode of the operand; the mode of the result is
3535 different but can be deduced from MODE. */
3538 expand_one_cmpl_abs_nojump (enum machine_mode mode
, rtx op0
, rtx target
)
3542 /* Not applicable for floating point modes. */
3543 if (FLOAT_MODE_P (mode
))
3546 /* If we have a MAX insn, we can do this as MAX (x, ~x). */
3547 if (optab_handler (smax_optab
, mode
) != CODE_FOR_nothing
)
3549 rtx_insn
*last
= get_last_insn ();
3551 temp
= expand_unop (mode
, one_cmpl_optab
, op0
, NULL_RTX
, 0);
3553 temp
= expand_binop (mode
, smax_optab
, op0
, temp
, target
, 0,
3559 delete_insns_since (last
);
3562 /* If this machine has expensive jumps, we can do one's complement
3563 absolute value of X as (((signed) x >> (W-1)) ^ x). */
3565 if (GET_MODE_CLASS (mode
) == MODE_INT
3566 && BRANCH_COST (optimize_insn_for_speed_p (),
3569 rtx extended
= expand_shift (RSHIFT_EXPR
, mode
, op0
,
3570 GET_MODE_PRECISION (mode
) - 1,
3573 temp
= expand_binop (mode
, xor_optab
, extended
, op0
, target
, 0,
3583 /* A subroutine of expand_copysign, perform the copysign operation using the
3584 abs and neg primitives advertised to exist on the target. The assumption
3585 is that we have a split register file, and leaving op0 in fp registers,
3586 and not playing with subregs so much, will help the register allocator. */
3589 expand_copysign_absneg (enum machine_mode mode
, rtx op0
, rtx op1
, rtx target
,
3590 int bitpos
, bool op0_is_abs
)
3592 enum machine_mode imode
;
3593 enum insn_code icode
;
3595 rtx_code_label
*label
;
3600 /* Check if the back end provides an insn that handles signbit for the
3602 icode
= optab_handler (signbit_optab
, mode
);
3603 if (icode
!= CODE_FOR_nothing
)
3605 imode
= insn_data
[(int) icode
].operand
[0].mode
;
3606 sign
= gen_reg_rtx (imode
);
3607 emit_unop_insn (icode
, sign
, op1
, UNKNOWN
);
3611 if (GET_MODE_SIZE (mode
) <= UNITS_PER_WORD
)
3613 imode
= int_mode_for_mode (mode
);
3614 if (imode
== BLKmode
)
3616 op1
= gen_lowpart (imode
, op1
);
3623 if (FLOAT_WORDS_BIG_ENDIAN
)
3624 word
= (GET_MODE_BITSIZE (mode
) - bitpos
) / BITS_PER_WORD
;
3626 word
= bitpos
/ BITS_PER_WORD
;
3627 bitpos
= bitpos
% BITS_PER_WORD
;
3628 op1
= operand_subword_force (op1
, word
, mode
);
3631 wide_int mask
= wi::set_bit_in_zero (bitpos
, GET_MODE_PRECISION (imode
));
3632 sign
= expand_binop (imode
, and_optab
, op1
,
3633 immed_wide_int_const (mask
, imode
),
3634 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
3639 op0
= expand_unop (mode
, abs_optab
, op0
, target
, 0);
3646 if (target
== NULL_RTX
)
3647 target
= copy_to_reg (op0
);
3649 emit_move_insn (target
, op0
);
3652 label
= gen_label_rtx ();
3653 emit_cmp_and_jump_insns (sign
, const0_rtx
, EQ
, NULL_RTX
, imode
, 1, label
);
3655 if (CONST_DOUBLE_AS_FLOAT_P (op0
))
3656 op0
= simplify_unary_operation (NEG
, mode
, op0
, mode
);
3658 op0
= expand_unop (mode
, neg_optab
, op0
, target
, 0);
3660 emit_move_insn (target
, op0
);
3668 /* A subroutine of expand_copysign, perform the entire copysign operation
3669 with integer bitmasks. BITPOS is the position of the sign bit; OP0_IS_ABS
3670 is true if op0 is known to have its sign bit clear. */
3673 expand_copysign_bit (enum machine_mode mode
, rtx op0
, rtx op1
, rtx target
,
3674 int bitpos
, bool op0_is_abs
)
3676 enum machine_mode imode
;
3677 int word
, nwords
, i
;
3681 if (GET_MODE_SIZE (mode
) <= UNITS_PER_WORD
)
3683 imode
= int_mode_for_mode (mode
);
3684 if (imode
== BLKmode
)
3693 if (FLOAT_WORDS_BIG_ENDIAN
)
3694 word
= (GET_MODE_BITSIZE (mode
) - bitpos
) / BITS_PER_WORD
;
3696 word
= bitpos
/ BITS_PER_WORD
;
3697 bitpos
= bitpos
% BITS_PER_WORD
;
3698 nwords
= (GET_MODE_BITSIZE (mode
) + BITS_PER_WORD
- 1) / BITS_PER_WORD
;
3701 wide_int mask
= wi::set_bit_in_zero (bitpos
, GET_MODE_PRECISION (imode
));
3706 || (nwords
> 1 && !valid_multiword_target_p (target
)))
3707 target
= gen_reg_rtx (mode
);
3713 for (i
= 0; i
< nwords
; ++i
)
3715 rtx targ_piece
= operand_subword (target
, i
, 1, mode
);
3716 rtx op0_piece
= operand_subword_force (op0
, i
, mode
);
3722 = expand_binop (imode
, and_optab
, op0_piece
,
3723 immed_wide_int_const (~mask
, imode
),
3724 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
3725 op1
= expand_binop (imode
, and_optab
,
3726 operand_subword_force (op1
, i
, mode
),
3727 immed_wide_int_const (mask
, imode
),
3728 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
3730 temp
= expand_binop (imode
, ior_optab
, op0_piece
, op1
,
3731 targ_piece
, 1, OPTAB_LIB_WIDEN
);
3732 if (temp
!= targ_piece
)
3733 emit_move_insn (targ_piece
, temp
);
3736 emit_move_insn (targ_piece
, op0_piece
);
3739 insns
= get_insns ();
3746 op1
= expand_binop (imode
, and_optab
, gen_lowpart (imode
, op1
),
3747 immed_wide_int_const (mask
, imode
),
3748 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
3750 op0
= gen_lowpart (imode
, op0
);
3752 op0
= expand_binop (imode
, and_optab
, op0
,
3753 immed_wide_int_const (~mask
, imode
),
3754 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
3756 temp
= expand_binop (imode
, ior_optab
, op0
, op1
,
3757 gen_lowpart (imode
, target
), 1, OPTAB_LIB_WIDEN
);
3758 target
= lowpart_subreg_maybe_copy (mode
, temp
, imode
);
3764 /* Expand the C99 copysign operation. OP0 and OP1 must be the same
3765 scalar floating point mode. Return NULL if we do not know how to
3766 expand the operation inline. */
3769 expand_copysign (rtx op0
, rtx op1
, rtx target
)
3771 enum machine_mode mode
= GET_MODE (op0
);
3772 const struct real_format
*fmt
;
3776 gcc_assert (SCALAR_FLOAT_MODE_P (mode
));
3777 gcc_assert (GET_MODE (op1
) == mode
);
3779 /* First try to do it with a special instruction. */
3780 temp
= expand_binop (mode
, copysign_optab
, op0
, op1
,
3781 target
, 0, OPTAB_DIRECT
);
3785 fmt
= REAL_MODE_FORMAT (mode
);
3786 if (fmt
== NULL
|| !fmt
->has_signed_zero
)
3790 if (CONST_DOUBLE_AS_FLOAT_P (op0
))
3792 if (real_isneg (CONST_DOUBLE_REAL_VALUE (op0
)))
3793 op0
= simplify_unary_operation (ABS
, mode
, op0
, mode
);
3797 if (fmt
->signbit_ro
>= 0
3798 && (CONST_DOUBLE_AS_FLOAT_P (op0
)
3799 || (optab_handler (neg_optab
, mode
) != CODE_FOR_nothing
3800 && optab_handler (abs_optab
, mode
) != CODE_FOR_nothing
)))
3802 temp
= expand_copysign_absneg (mode
, op0
, op1
, target
,
3803 fmt
->signbit_ro
, op0_is_abs
);
3808 if (fmt
->signbit_rw
< 0)
3810 return expand_copysign_bit (mode
, op0
, op1
, target
,
3811 fmt
->signbit_rw
, op0_is_abs
);
3814 /* Generate an instruction whose insn-code is INSN_CODE,
3815 with two operands: an output TARGET and an input OP0.
3816 TARGET *must* be nonzero, and the output is always stored there.
3817 CODE is an rtx code such that (CODE OP0) is an rtx that describes
3818 the value that is stored into TARGET.
3820 Return false if expansion failed. */
3823 maybe_emit_unop_insn (enum insn_code icode
, rtx target
, rtx op0
,
3826 struct expand_operand ops
[2];
3829 create_output_operand (&ops
[0], target
, GET_MODE (target
));
3830 create_input_operand (&ops
[1], op0
, GET_MODE (op0
));
3831 pat
= maybe_gen_insn (icode
, 2, ops
);
3835 if (INSN_P (pat
) && NEXT_INSN (as_a
<rtx_insn
*> (pat
)) != NULL_RTX
3837 add_equal_note (as_a
<rtx_insn
*> (pat
), ops
[0].value
, code
, ops
[1].value
,
3842 if (ops
[0].value
!= target
)
3843 emit_move_insn (target
, ops
[0].value
);
3846 /* Generate an instruction whose insn-code is INSN_CODE,
3847 with two operands: an output TARGET and an input OP0.
3848 TARGET *must* be nonzero, and the output is always stored there.
3849 CODE is an rtx code such that (CODE OP0) is an rtx that describes
3850 the value that is stored into TARGET. */
3853 emit_unop_insn (enum insn_code icode
, rtx target
, rtx op0
, enum rtx_code code
)
3855 bool ok
= maybe_emit_unop_insn (icode
, target
, op0
, code
);
3859 struct no_conflict_data
3862 rtx_insn
*first
, *insn
;
3866 /* Called via note_stores by emit_libcall_block. Set P->must_stay if
3867 the currently examined clobber / store has to stay in the list of
3868 insns that constitute the actual libcall block. */
3870 no_conflict_move_test (rtx dest
, const_rtx set
, void *p0
)
3872 struct no_conflict_data
*p
= (struct no_conflict_data
*) p0
;
3874 /* If this inns directly contributes to setting the target, it must stay. */
3875 if (reg_overlap_mentioned_p (p
->target
, dest
))
3876 p
->must_stay
= true;
3877 /* If we haven't committed to keeping any other insns in the list yet,
3878 there is nothing more to check. */
3879 else if (p
->insn
== p
->first
)
3881 /* If this insn sets / clobbers a register that feeds one of the insns
3882 already in the list, this insn has to stay too. */
3883 else if (reg_overlap_mentioned_p (dest
, PATTERN (p
->first
))
3884 || (CALL_P (p
->first
) && (find_reg_fusage (p
->first
, USE
, dest
)))
3885 || reg_used_between_p (dest
, p
->first
, p
->insn
)
3886 /* Likewise if this insn depends on a register set by a previous
3887 insn in the list, or if it sets a result (presumably a hard
3888 register) that is set or clobbered by a previous insn.
3889 N.B. the modified_*_p (SET_DEST...) tests applied to a MEM
3890 SET_DEST perform the former check on the address, and the latter
3891 check on the MEM. */
3892 || (GET_CODE (set
) == SET
3893 && (modified_in_p (SET_SRC (set
), p
->first
)
3894 || modified_in_p (SET_DEST (set
), p
->first
)
3895 || modified_between_p (SET_SRC (set
), p
->first
, p
->insn
)
3896 || modified_between_p (SET_DEST (set
), p
->first
, p
->insn
))))
3897 p
->must_stay
= true;
3901 /* Emit code to make a call to a constant function or a library call.
3903 INSNS is a list containing all insns emitted in the call.
3904 These insns leave the result in RESULT. Our block is to copy RESULT
3905 to TARGET, which is logically equivalent to EQUIV.
3907 We first emit any insns that set a pseudo on the assumption that these are
3908 loading constants into registers; doing so allows them to be safely cse'ed
3909 between blocks. Then we emit all the other insns in the block, followed by
3910 an insn to move RESULT to TARGET. This last insn will have a REQ_EQUAL
3911 note with an operand of EQUIV. */
3914 emit_libcall_block_1 (rtx_insn
*insns
, rtx target
, rtx result
, rtx equiv
,
3915 bool equiv_may_trap
)
3917 rtx final_dest
= target
;
3918 rtx_insn
*next
, *last
, *insn
;
3920 /* If this is a reg with REG_USERVAR_P set, then it could possibly turn
3921 into a MEM later. Protect the libcall block from this change. */
3922 if (! REG_P (target
) || REG_USERVAR_P (target
))
3923 target
= gen_reg_rtx (GET_MODE (target
));
3925 /* If we're using non-call exceptions, a libcall corresponding to an
3926 operation that may trap may also trap. */
3927 /* ??? See the comment in front of make_reg_eh_region_note. */
3928 if (cfun
->can_throw_non_call_exceptions
3929 && (equiv_may_trap
|| may_trap_p (equiv
)))
3931 for (insn
= insns
; insn
; insn
= NEXT_INSN (insn
))
3934 rtx note
= find_reg_note (insn
, REG_EH_REGION
, NULL_RTX
);
3937 int lp_nr
= INTVAL (XEXP (note
, 0));
3938 if (lp_nr
== 0 || lp_nr
== INT_MIN
)
3939 remove_note (insn
, note
);
3945 /* Look for any CALL_INSNs in this sequence, and attach a REG_EH_REGION
3946 reg note to indicate that this call cannot throw or execute a nonlocal
3947 goto (unless there is already a REG_EH_REGION note, in which case
3949 for (insn
= insns
; insn
; insn
= NEXT_INSN (insn
))
3951 make_reg_eh_region_note_nothrow_nononlocal (insn
);
3954 /* First emit all insns that set pseudos. Remove them from the list as
3955 we go. Avoid insns that set pseudos which were referenced in previous
3956 insns. These can be generated by move_by_pieces, for example,
3957 to update an address. Similarly, avoid insns that reference things
3958 set in previous insns. */
3960 for (insn
= insns
; insn
; insn
= next
)
3962 rtx set
= single_set (insn
);
3964 next
= NEXT_INSN (insn
);
3966 if (set
!= 0 && REG_P (SET_DEST (set
))
3967 && REGNO (SET_DEST (set
)) >= FIRST_PSEUDO_REGISTER
)
3969 struct no_conflict_data data
;
3971 data
.target
= const0_rtx
;
3975 note_stores (PATTERN (insn
), no_conflict_move_test
, &data
);
3976 if (! data
.must_stay
)
3978 if (PREV_INSN (insn
))
3979 SET_NEXT_INSN (PREV_INSN (insn
)) = next
;
3984 SET_PREV_INSN (next
) = PREV_INSN (insn
);
3990 /* Some ports use a loop to copy large arguments onto the stack.
3991 Don't move anything outside such a loop. */
3996 /* Write the remaining insns followed by the final copy. */
3997 for (insn
= insns
; insn
; insn
= next
)
3999 next
= NEXT_INSN (insn
);
4004 last
= emit_move_insn (target
, result
);
4005 set_dst_reg_note (last
, REG_EQUAL
, copy_rtx (equiv
), target
);
4007 if (final_dest
!= target
)
4008 emit_move_insn (final_dest
, target
);
4012 emit_libcall_block (rtx insns
, rtx target
, rtx result
, rtx equiv
)
4014 emit_libcall_block_1 (safe_as_a
<rtx_insn
*> (insns
),
4015 target
, result
, equiv
, false);
4018 /* Nonzero if we can perform a comparison of mode MODE straightforwardly.
4019 PURPOSE describes how this comparison will be used. CODE is the rtx
4020 comparison code we will be using.
4022 ??? Actually, CODE is slightly weaker than that. A target is still
4023 required to implement all of the normal bcc operations, but not
4024 required to implement all (or any) of the unordered bcc operations. */
4027 can_compare_p (enum rtx_code code
, enum machine_mode mode
,
4028 enum can_compare_purpose purpose
)
4031 test
= gen_rtx_fmt_ee (code
, mode
, const0_rtx
, const0_rtx
);
4034 enum insn_code icode
;
4036 if (purpose
== ccp_jump
4037 && (icode
= optab_handler (cbranch_optab
, mode
)) != CODE_FOR_nothing
4038 && insn_operand_matches (icode
, 0, test
))
4040 if (purpose
== ccp_store_flag
4041 && (icode
= optab_handler (cstore_optab
, mode
)) != CODE_FOR_nothing
4042 && insn_operand_matches (icode
, 1, test
))
4044 if (purpose
== ccp_cmov
4045 && optab_handler (cmov_optab
, mode
) != CODE_FOR_nothing
)
4048 mode
= GET_MODE_WIDER_MODE (mode
);
4049 PUT_MODE (test
, mode
);
4051 while (mode
!= VOIDmode
);
4056 /* This function is called when we are going to emit a compare instruction that
4057 compares the values found in *PX and *PY, using the rtl operator COMPARISON.
4059 *PMODE is the mode of the inputs (in case they are const_int).
4060 *PUNSIGNEDP nonzero says that the operands are unsigned;
4061 this matters if they need to be widened (as given by METHODS).
4063 If they have mode BLKmode, then SIZE specifies the size of both operands.
4065 This function performs all the setup necessary so that the caller only has
4066 to emit a single comparison insn. This setup can involve doing a BLKmode
4067 comparison or emitting a library call to perform the comparison if no insn
4068 is available to handle it.
4069 The values which are passed in through pointers can be modified; the caller
4070 should perform the comparison on the modified values. Constant
4071 comparisons must have already been folded. */
4074 prepare_cmp_insn (rtx x
, rtx y
, enum rtx_code comparison
, rtx size
,
4075 int unsignedp
, enum optab_methods methods
,
4076 rtx
*ptest
, enum machine_mode
*pmode
)
4078 enum machine_mode mode
= *pmode
;
4080 enum machine_mode cmp_mode
;
4081 enum mode_class mclass
;
4083 /* The other methods are not needed. */
4084 gcc_assert (methods
== OPTAB_DIRECT
|| methods
== OPTAB_WIDEN
4085 || methods
== OPTAB_LIB_WIDEN
);
4087 /* If we are optimizing, force expensive constants into a register. */
4088 if (CONSTANT_P (x
) && optimize
4089 && (rtx_cost (x
, COMPARE
, 0, optimize_insn_for_speed_p ())
4090 > COSTS_N_INSNS (1)))
4091 x
= force_reg (mode
, x
);
4093 if (CONSTANT_P (y
) && optimize
4094 && (rtx_cost (y
, COMPARE
, 1, optimize_insn_for_speed_p ())
4095 > COSTS_N_INSNS (1)))
4096 y
= force_reg (mode
, y
);
4099 /* Make sure if we have a canonical comparison. The RTL
4100 documentation states that canonical comparisons are required only
4101 for targets which have cc0. */
4102 gcc_assert (!CONSTANT_P (x
) || CONSTANT_P (y
));
4105 /* Don't let both operands fail to indicate the mode. */
4106 if (GET_MODE (x
) == VOIDmode
&& GET_MODE (y
) == VOIDmode
)
4107 x
= force_reg (mode
, x
);
4108 if (mode
== VOIDmode
)
4109 mode
= GET_MODE (x
) != VOIDmode
? GET_MODE (x
) : GET_MODE (y
);
4111 /* Handle all BLKmode compares. */
4113 if (mode
== BLKmode
)
4115 enum machine_mode result_mode
;
4116 enum insn_code cmp_code
;
4121 = GEN_INT (MIN (MEM_ALIGN (x
), MEM_ALIGN (y
)) / BITS_PER_UNIT
);
4125 /* Try to use a memory block compare insn - either cmpstr
4126 or cmpmem will do. */
4127 for (cmp_mode
= GET_CLASS_NARROWEST_MODE (MODE_INT
);
4128 cmp_mode
!= VOIDmode
;
4129 cmp_mode
= GET_MODE_WIDER_MODE (cmp_mode
))
4131 cmp_code
= direct_optab_handler (cmpmem_optab
, cmp_mode
);
4132 if (cmp_code
== CODE_FOR_nothing
)
4133 cmp_code
= direct_optab_handler (cmpstr_optab
, cmp_mode
);
4134 if (cmp_code
== CODE_FOR_nothing
)
4135 cmp_code
= direct_optab_handler (cmpstrn_optab
, cmp_mode
);
4136 if (cmp_code
== CODE_FOR_nothing
)
4139 /* Must make sure the size fits the insn's mode. */
4140 if ((CONST_INT_P (size
)
4141 && INTVAL (size
) >= (1 << GET_MODE_BITSIZE (cmp_mode
)))
4142 || (GET_MODE_BITSIZE (GET_MODE (size
))
4143 > GET_MODE_BITSIZE (cmp_mode
)))
4146 result_mode
= insn_data
[cmp_code
].operand
[0].mode
;
4147 result
= gen_reg_rtx (result_mode
);
4148 size
= convert_to_mode (cmp_mode
, size
, 1);
4149 emit_insn (GEN_FCN (cmp_code
) (result
, x
, y
, size
, opalign
));
4151 *ptest
= gen_rtx_fmt_ee (comparison
, VOIDmode
, result
, const0_rtx
);
4152 *pmode
= result_mode
;
4156 if (methods
!= OPTAB_LIB
&& methods
!= OPTAB_LIB_WIDEN
)
4159 /* Otherwise call a library function, memcmp. */
4160 libfunc
= memcmp_libfunc
;
4161 length_type
= sizetype
;
4162 result_mode
= TYPE_MODE (integer_type_node
);
4163 cmp_mode
= TYPE_MODE (length_type
);
4164 size
= convert_to_mode (TYPE_MODE (length_type
), size
,
4165 TYPE_UNSIGNED (length_type
));
4167 result
= emit_library_call_value (libfunc
, 0, LCT_PURE
,
4175 methods
= OPTAB_LIB_WIDEN
;
4179 /* Don't allow operands to the compare to trap, as that can put the
4180 compare and branch in different basic blocks. */
4181 if (cfun
->can_throw_non_call_exceptions
)
4184 x
= force_reg (mode
, x
);
4186 y
= force_reg (mode
, y
);
4189 if (GET_MODE_CLASS (mode
) == MODE_CC
)
4191 gcc_assert (can_compare_p (comparison
, CCmode
, ccp_jump
));
4192 *ptest
= gen_rtx_fmt_ee (comparison
, VOIDmode
, x
, y
);
4196 mclass
= GET_MODE_CLASS (mode
);
4197 test
= gen_rtx_fmt_ee (comparison
, VOIDmode
, x
, y
);
4201 enum insn_code icode
;
4202 icode
= optab_handler (cbranch_optab
, cmp_mode
);
4203 if (icode
!= CODE_FOR_nothing
4204 && insn_operand_matches (icode
, 0, test
))
4206 rtx_insn
*last
= get_last_insn ();
4207 rtx op0
= prepare_operand (icode
, x
, 1, mode
, cmp_mode
, unsignedp
);
4208 rtx op1
= prepare_operand (icode
, y
, 2, mode
, cmp_mode
, unsignedp
);
4210 && insn_operand_matches (icode
, 1, op0
)
4211 && insn_operand_matches (icode
, 2, op1
))
4213 XEXP (test
, 0) = op0
;
4214 XEXP (test
, 1) = op1
;
4219 delete_insns_since (last
);
4222 if (methods
== OPTAB_DIRECT
|| !CLASS_HAS_WIDER_MODES_P (mclass
))
4224 cmp_mode
= GET_MODE_WIDER_MODE (cmp_mode
);
4226 while (cmp_mode
!= VOIDmode
);
4228 if (methods
!= OPTAB_LIB_WIDEN
)
4231 if (!SCALAR_FLOAT_MODE_P (mode
))
4234 enum machine_mode ret_mode
;
4236 /* Handle a libcall just for the mode we are using. */
4237 libfunc
= optab_libfunc (cmp_optab
, mode
);
4238 gcc_assert (libfunc
);
4240 /* If we want unsigned, and this mode has a distinct unsigned
4241 comparison routine, use that. */
4244 rtx ulibfunc
= optab_libfunc (ucmp_optab
, mode
);
4249 ret_mode
= targetm
.libgcc_cmp_return_mode ();
4250 result
= emit_library_call_value (libfunc
, NULL_RTX
, LCT_CONST
,
4251 ret_mode
, 2, x
, mode
, y
, mode
);
4253 /* There are two kinds of comparison routines. Biased routines
4254 return 0/1/2, and unbiased routines return -1/0/1. Other parts
4255 of gcc expect that the comparison operation is equivalent
4256 to the modified comparison. For signed comparisons compare the
4257 result against 1 in the biased case, and zero in the unbiased
4258 case. For unsigned comparisons always compare against 1 after
4259 biasing the unbiased result by adding 1. This gives us a way to
4261 The comparisons in the fixed-point helper library are always
4266 if (!TARGET_LIB_INT_CMP_BIASED
&& !ALL_FIXED_POINT_MODE_P (mode
))
4269 x
= plus_constant (ret_mode
, result
, 1);
4275 prepare_cmp_insn (x
, y
, comparison
, NULL_RTX
, unsignedp
, methods
,
4279 prepare_float_lib_cmp (x
, y
, comparison
, ptest
, pmode
);
4287 /* Before emitting an insn with code ICODE, make sure that X, which is going
4288 to be used for operand OPNUM of the insn, is converted from mode MODE to
4289 WIDER_MODE (UNSIGNEDP determines whether it is an unsigned conversion), and
4290 that it is accepted by the operand predicate. Return the new value. */
4293 prepare_operand (enum insn_code icode
, rtx x
, int opnum
, enum machine_mode mode
,
4294 enum machine_mode wider_mode
, int unsignedp
)
4296 if (mode
!= wider_mode
)
4297 x
= convert_modes (wider_mode
, mode
, x
, unsignedp
);
4299 if (!insn_operand_matches (icode
, opnum
, x
))
4301 if (reload_completed
)
4303 x
= copy_to_mode_reg (insn_data
[(int) icode
].operand
[opnum
].mode
, x
);
4309 /* Subroutine of emit_cmp_and_jump_insns; this function is called when we know
4310 we can do the branch. */
4313 emit_cmp_and_jump_insn_1 (rtx test
, enum machine_mode mode
, rtx label
, int prob
)
4315 enum machine_mode optab_mode
;
4316 enum mode_class mclass
;
4317 enum insn_code icode
;
4320 mclass
= GET_MODE_CLASS (mode
);
4321 optab_mode
= (mclass
== MODE_CC
) ? CCmode
: mode
;
4322 icode
= optab_handler (cbranch_optab
, optab_mode
);
4324 gcc_assert (icode
!= CODE_FOR_nothing
);
4325 gcc_assert (insn_operand_matches (icode
, 0, test
));
4326 insn
= emit_jump_insn (GEN_FCN (icode
) (test
, XEXP (test
, 0),
4327 XEXP (test
, 1), label
));
4329 && profile_status_for_fn (cfun
) != PROFILE_ABSENT
4332 && any_condjump_p (insn
)
4333 && !find_reg_note (insn
, REG_BR_PROB
, 0))
4334 add_int_reg_note (insn
, REG_BR_PROB
, prob
);
4337 /* Generate code to compare X with Y so that the condition codes are
4338 set and to jump to LABEL if the condition is true. If X is a
4339 constant and Y is not a constant, then the comparison is swapped to
4340 ensure that the comparison RTL has the canonical form.
4342 UNSIGNEDP nonzero says that X and Y are unsigned; this matters if they
4343 need to be widened. UNSIGNEDP is also used to select the proper
4344 branch condition code.
4346 If X and Y have mode BLKmode, then SIZE specifies the size of both X and Y.
4348 MODE is the mode of the inputs (in case they are const_int).
4350 COMPARISON is the rtl operator to compare with (EQ, NE, GT, etc.).
4351 It will be potentially converted into an unsigned variant based on
4352 UNSIGNEDP to select a proper jump instruction.
4354 PROB is the probability of jumping to LABEL. */
4357 emit_cmp_and_jump_insns (rtx x
, rtx y
, enum rtx_code comparison
, rtx size
,
4358 enum machine_mode mode
, int unsignedp
, rtx label
,
4361 rtx op0
= x
, op1
= y
;
4364 /* Swap operands and condition to ensure canonical RTL. */
4365 if (swap_commutative_operands_p (x
, y
)
4366 && can_compare_p (swap_condition (comparison
), mode
, ccp_jump
))
4369 comparison
= swap_condition (comparison
);
4372 /* If OP0 is still a constant, then both X and Y must be constants
4373 or the opposite comparison is not supported. Force X into a register
4374 to create canonical RTL. */
4375 if (CONSTANT_P (op0
))
4376 op0
= force_reg (mode
, op0
);
4379 comparison
= unsigned_condition (comparison
);
4381 prepare_cmp_insn (op0
, op1
, comparison
, size
, unsignedp
, OPTAB_LIB_WIDEN
,
4383 emit_cmp_and_jump_insn_1 (test
, mode
, label
, prob
);
4387 /* Emit a library call comparison between floating point X and Y.
4388 COMPARISON is the rtl operator to compare with (EQ, NE, GT, etc.). */
4391 prepare_float_lib_cmp (rtx x
, rtx y
, enum rtx_code comparison
,
4392 rtx
*ptest
, enum machine_mode
*pmode
)
4394 enum rtx_code swapped
= swap_condition (comparison
);
4395 enum rtx_code reversed
= reverse_condition_maybe_unordered (comparison
);
4396 enum machine_mode orig_mode
= GET_MODE (x
);
4397 enum machine_mode mode
, cmp_mode
;
4398 rtx true_rtx
, false_rtx
;
4399 rtx value
, target
, equiv
;
4402 bool reversed_p
= false;
4403 cmp_mode
= targetm
.libgcc_cmp_return_mode ();
4405 for (mode
= orig_mode
;
4407 mode
= GET_MODE_WIDER_MODE (mode
))
4409 if (code_to_optab (comparison
)
4410 && (libfunc
= optab_libfunc (code_to_optab (comparison
), mode
)))
4413 if (code_to_optab (swapped
)
4414 && (libfunc
= optab_libfunc (code_to_optab (swapped
), mode
)))
4417 tmp
= x
; x
= y
; y
= tmp
;
4418 comparison
= swapped
;
4422 if (code_to_optab (reversed
)
4423 && (libfunc
= optab_libfunc (code_to_optab (reversed
), mode
)))
4425 comparison
= reversed
;
4431 gcc_assert (mode
!= VOIDmode
);
4433 if (mode
!= orig_mode
)
4435 x
= convert_to_mode (mode
, x
, 0);
4436 y
= convert_to_mode (mode
, y
, 0);
4439 /* Attach a REG_EQUAL note describing the semantics of the libcall to
4440 the RTL. The allows the RTL optimizers to delete the libcall if the
4441 condition can be determined at compile-time. */
4442 if (comparison
== UNORDERED
4443 || FLOAT_LIB_COMPARE_RETURNS_BOOL (mode
, comparison
))
4445 true_rtx
= const_true_rtx
;
4446 false_rtx
= const0_rtx
;
4453 true_rtx
= const0_rtx
;
4454 false_rtx
= const_true_rtx
;
4458 true_rtx
= const_true_rtx
;
4459 false_rtx
= const0_rtx
;
4463 true_rtx
= const1_rtx
;
4464 false_rtx
= const0_rtx
;
4468 true_rtx
= const0_rtx
;
4469 false_rtx
= constm1_rtx
;
4473 true_rtx
= constm1_rtx
;
4474 false_rtx
= const0_rtx
;
4478 true_rtx
= const0_rtx
;
4479 false_rtx
= const1_rtx
;
4487 if (comparison
== UNORDERED
)
4489 rtx temp
= simplify_gen_relational (NE
, cmp_mode
, mode
, x
, x
);
4490 equiv
= simplify_gen_relational (NE
, cmp_mode
, mode
, y
, y
);
4491 equiv
= simplify_gen_ternary (IF_THEN_ELSE
, cmp_mode
, cmp_mode
,
4492 temp
, const_true_rtx
, equiv
);
4496 equiv
= simplify_gen_relational (comparison
, cmp_mode
, mode
, x
, y
);
4497 if (! FLOAT_LIB_COMPARE_RETURNS_BOOL (mode
, comparison
))
4498 equiv
= simplify_gen_ternary (IF_THEN_ELSE
, cmp_mode
, cmp_mode
,
4499 equiv
, true_rtx
, false_rtx
);
4503 value
= emit_library_call_value (libfunc
, NULL_RTX
, LCT_CONST
,
4504 cmp_mode
, 2, x
, mode
, y
, mode
);
4505 insns
= get_insns ();
4508 target
= gen_reg_rtx (cmp_mode
);
4509 emit_libcall_block (insns
, target
, value
, equiv
);
4511 if (comparison
== UNORDERED
4512 || FLOAT_LIB_COMPARE_RETURNS_BOOL (mode
, comparison
)
4514 *ptest
= gen_rtx_fmt_ee (reversed_p
? EQ
: NE
, VOIDmode
, target
, false_rtx
);
4516 *ptest
= gen_rtx_fmt_ee (comparison
, VOIDmode
, target
, const0_rtx
);
4521 /* Generate code to indirectly jump to a location given in the rtx LOC. */
4524 emit_indirect_jump (rtx loc
)
4526 struct expand_operand ops
[1];
4528 create_address_operand (&ops
[0], loc
);
4529 expand_jump_insn (CODE_FOR_indirect_jump
, 1, ops
);
4533 #ifdef HAVE_conditional_move
4535 /* Emit a conditional move instruction if the machine supports one for that
4536 condition and machine mode.
4538 OP0 and OP1 are the operands that should be compared using CODE. CMODE is
4539 the mode to use should they be constants. If it is VOIDmode, they cannot
4542 OP2 should be stored in TARGET if the comparison is true, otherwise OP3
4543 should be stored there. MODE is the mode to use should they be constants.
4544 If it is VOIDmode, they cannot both be constants.
4546 The result is either TARGET (perhaps modified) or NULL_RTX if the operation
4547 is not supported. */
4550 emit_conditional_move (rtx target
, enum rtx_code code
, rtx op0
, rtx op1
,
4551 enum machine_mode cmode
, rtx op2
, rtx op3
,
4552 enum machine_mode mode
, int unsignedp
)
4554 rtx tem
, comparison
;
4556 enum insn_code icode
;
4557 enum rtx_code reversed
;
4559 /* If one operand is constant, make it the second one. Only do this
4560 if the other operand is not constant as well. */
4562 if (swap_commutative_operands_p (op0
, op1
))
4567 code
= swap_condition (code
);
4570 /* get_condition will prefer to generate LT and GT even if the old
4571 comparison was against zero, so undo that canonicalization here since
4572 comparisons against zero are cheaper. */
4573 if (code
== LT
&& op1
== const1_rtx
)
4574 code
= LE
, op1
= const0_rtx
;
4575 else if (code
== GT
&& op1
== constm1_rtx
)
4576 code
= GE
, op1
= const0_rtx
;
4578 if (cmode
== VOIDmode
)
4579 cmode
= GET_MODE (op0
);
4581 if (swap_commutative_operands_p (op2
, op3
)
4582 && ((reversed
= reversed_comparison_code_parts (code
, op0
, op1
, NULL
))
4591 if (mode
== VOIDmode
)
4592 mode
= GET_MODE (op2
);
4594 icode
= direct_optab_handler (movcc_optab
, mode
);
4596 if (icode
== CODE_FOR_nothing
)
4600 target
= gen_reg_rtx (mode
);
4602 code
= unsignedp
? unsigned_condition (code
) : code
;
4603 comparison
= simplify_gen_relational (code
, VOIDmode
, cmode
, op0
, op1
);
4605 /* We can get const0_rtx or const_true_rtx in some circumstances. Just
4606 return NULL and let the caller figure out how best to deal with this
4608 if (!COMPARISON_P (comparison
))
4611 saved_pending_stack_adjust save
;
4612 save_pending_stack_adjust (&save
);
4613 last
= get_last_insn ();
4614 do_pending_stack_adjust ();
4615 prepare_cmp_insn (XEXP (comparison
, 0), XEXP (comparison
, 1),
4616 GET_CODE (comparison
), NULL_RTX
, unsignedp
, OPTAB_WIDEN
,
4617 &comparison
, &cmode
);
4620 struct expand_operand ops
[4];
4622 create_output_operand (&ops
[0], target
, mode
);
4623 create_fixed_operand (&ops
[1], comparison
);
4624 create_input_operand (&ops
[2], op2
, mode
);
4625 create_input_operand (&ops
[3], op3
, mode
);
4626 if (maybe_expand_insn (icode
, 4, ops
))
4628 if (ops
[0].value
!= target
)
4629 convert_move (target
, ops
[0].value
, false);
4633 delete_insns_since (last
);
4634 restore_pending_stack_adjust (&save
);
4638 /* Return nonzero if a conditional move of mode MODE is supported.
4640 This function is for combine so it can tell whether an insn that looks
4641 like a conditional move is actually supported by the hardware. If we
4642 guess wrong we lose a bit on optimization, but that's it. */
4643 /* ??? sparc64 supports conditionally moving integers values based on fp
4644 comparisons, and vice versa. How do we handle them? */
4647 can_conditionally_move_p (enum machine_mode mode
)
4649 if (direct_optab_handler (movcc_optab
, mode
) != CODE_FOR_nothing
)
4655 #endif /* HAVE_conditional_move */
4657 /* Emit a conditional addition instruction if the machine supports one for that
4658 condition and machine mode.
4660 OP0 and OP1 are the operands that should be compared using CODE. CMODE is
4661 the mode to use should they be constants. If it is VOIDmode, they cannot
4664 OP2 should be stored in TARGET if the comparison is false, otherwise OP2+OP3
4665 should be stored there. MODE is the mode to use should they be constants.
4666 If it is VOIDmode, they cannot both be constants.
4668 The result is either TARGET (perhaps modified) or NULL_RTX if the operation
4669 is not supported. */
4672 emit_conditional_add (rtx target
, enum rtx_code code
, rtx op0
, rtx op1
,
4673 enum machine_mode cmode
, rtx op2
, rtx op3
,
4674 enum machine_mode mode
, int unsignedp
)
4676 rtx tem
, comparison
;
4678 enum insn_code icode
;
4680 /* If one operand is constant, make it the second one. Only do this
4681 if the other operand is not constant as well. */
4683 if (swap_commutative_operands_p (op0
, op1
))
4688 code
= swap_condition (code
);
4691 /* get_condition will prefer to generate LT and GT even if the old
4692 comparison was against zero, so undo that canonicalization here since
4693 comparisons against zero are cheaper. */
4694 if (code
== LT
&& op1
== const1_rtx
)
4695 code
= LE
, op1
= const0_rtx
;
4696 else if (code
== GT
&& op1
== constm1_rtx
)
4697 code
= GE
, op1
= const0_rtx
;
4699 if (cmode
== VOIDmode
)
4700 cmode
= GET_MODE (op0
);
4702 if (mode
== VOIDmode
)
4703 mode
= GET_MODE (op2
);
4705 icode
= optab_handler (addcc_optab
, mode
);
4707 if (icode
== CODE_FOR_nothing
)
4711 target
= gen_reg_rtx (mode
);
4713 code
= unsignedp
? unsigned_condition (code
) : code
;
4714 comparison
= simplify_gen_relational (code
, VOIDmode
, cmode
, op0
, op1
);
4716 /* We can get const0_rtx or const_true_rtx in some circumstances. Just
4717 return NULL and let the caller figure out how best to deal with this
4719 if (!COMPARISON_P (comparison
))
4722 do_pending_stack_adjust ();
4723 last
= get_last_insn ();
4724 prepare_cmp_insn (XEXP (comparison
, 0), XEXP (comparison
, 1),
4725 GET_CODE (comparison
), NULL_RTX
, unsignedp
, OPTAB_WIDEN
,
4726 &comparison
, &cmode
);
4729 struct expand_operand ops
[4];
4731 create_output_operand (&ops
[0], target
, mode
);
4732 create_fixed_operand (&ops
[1], comparison
);
4733 create_input_operand (&ops
[2], op2
, mode
);
4734 create_input_operand (&ops
[3], op3
, mode
);
4735 if (maybe_expand_insn (icode
, 4, ops
))
4737 if (ops
[0].value
!= target
)
4738 convert_move (target
, ops
[0].value
, false);
4742 delete_insns_since (last
);
4746 /* These functions attempt to generate an insn body, rather than
4747 emitting the insn, but if the gen function already emits them, we
4748 make no attempt to turn them back into naked patterns. */
4750 /* Generate and return an insn body to add Y to X. */
4753 gen_add2_insn (rtx x
, rtx y
)
4755 enum insn_code icode
= optab_handler (add_optab
, GET_MODE (x
));
4757 gcc_assert (insn_operand_matches (icode
, 0, x
));
4758 gcc_assert (insn_operand_matches (icode
, 1, x
));
4759 gcc_assert (insn_operand_matches (icode
, 2, y
));
4761 return GEN_FCN (icode
) (x
, x
, y
);
4764 /* Generate and return an insn body to add r1 and c,
4765 storing the result in r0. */
4768 gen_add3_insn (rtx r0
, rtx r1
, rtx c
)
4770 enum insn_code icode
= optab_handler (add_optab
, GET_MODE (r0
));
4772 if (icode
== CODE_FOR_nothing
4773 || !insn_operand_matches (icode
, 0, r0
)
4774 || !insn_operand_matches (icode
, 1, r1
)
4775 || !insn_operand_matches (icode
, 2, c
))
4778 return GEN_FCN (icode
) (r0
, r1
, c
);
4782 have_add2_insn (rtx x
, rtx y
)
4784 enum insn_code icode
;
4786 gcc_assert (GET_MODE (x
) != VOIDmode
);
4788 icode
= optab_handler (add_optab
, GET_MODE (x
));
4790 if (icode
== CODE_FOR_nothing
)
4793 if (!insn_operand_matches (icode
, 0, x
)
4794 || !insn_operand_matches (icode
, 1, x
)
4795 || !insn_operand_matches (icode
, 2, y
))
4801 /* Generate and return an insn body to add Y to X. */
4804 gen_addptr3_insn (rtx x
, rtx y
, rtx z
)
4806 enum insn_code icode
= optab_handler (addptr3_optab
, GET_MODE (x
));
4808 gcc_assert (insn_operand_matches (icode
, 0, x
));
4809 gcc_assert (insn_operand_matches (icode
, 1, y
));
4810 gcc_assert (insn_operand_matches (icode
, 2, z
));
4812 return GEN_FCN (icode
) (x
, y
, z
);
4815 /* Return true if the target implements an addptr pattern and X, Y,
4816 and Z are valid for the pattern predicates. */
4819 have_addptr3_insn (rtx x
, rtx y
, rtx z
)
4821 enum insn_code icode
;
4823 gcc_assert (GET_MODE (x
) != VOIDmode
);
4825 icode
= optab_handler (addptr3_optab
, GET_MODE (x
));
4827 if (icode
== CODE_FOR_nothing
)
4830 if (!insn_operand_matches (icode
, 0, x
)
4831 || !insn_operand_matches (icode
, 1, y
)
4832 || !insn_operand_matches (icode
, 2, z
))
4838 /* Generate and return an insn body to subtract Y from X. */
4841 gen_sub2_insn (rtx x
, rtx y
)
4843 enum insn_code icode
= optab_handler (sub_optab
, GET_MODE (x
));
4845 gcc_assert (insn_operand_matches (icode
, 0, x
));
4846 gcc_assert (insn_operand_matches (icode
, 1, x
));
4847 gcc_assert (insn_operand_matches (icode
, 2, y
));
4849 return GEN_FCN (icode
) (x
, x
, y
);
4852 /* Generate and return an insn body to subtract r1 and c,
4853 storing the result in r0. */
4856 gen_sub3_insn (rtx r0
, rtx r1
, rtx c
)
4858 enum insn_code icode
= optab_handler (sub_optab
, GET_MODE (r0
));
4860 if (icode
== CODE_FOR_nothing
4861 || !insn_operand_matches (icode
, 0, r0
)
4862 || !insn_operand_matches (icode
, 1, r1
)
4863 || !insn_operand_matches (icode
, 2, c
))
4866 return GEN_FCN (icode
) (r0
, r1
, c
);
4870 have_sub2_insn (rtx x
, rtx y
)
4872 enum insn_code icode
;
4874 gcc_assert (GET_MODE (x
) != VOIDmode
);
4876 icode
= optab_handler (sub_optab
, GET_MODE (x
));
4878 if (icode
== CODE_FOR_nothing
)
4881 if (!insn_operand_matches (icode
, 0, x
)
4882 || !insn_operand_matches (icode
, 1, x
)
4883 || !insn_operand_matches (icode
, 2, y
))
4889 /* Generate the body of an instruction to copy Y into X.
4890 It may be a list of insns, if one insn isn't enough. */
4893 gen_move_insn (rtx x
, rtx y
)
4898 emit_move_insn_1 (x
, y
);
4904 /* Return the insn code used to extend FROM_MODE to TO_MODE.
4905 UNSIGNEDP specifies zero-extension instead of sign-extension. If
4906 no such operation exists, CODE_FOR_nothing will be returned. */
4909 can_extend_p (enum machine_mode to_mode
, enum machine_mode from_mode
,
4913 #ifdef HAVE_ptr_extend
4915 return CODE_FOR_ptr_extend
;
4918 tab
= unsignedp
? zext_optab
: sext_optab
;
4919 return convert_optab_handler (tab
, to_mode
, from_mode
);
4922 /* Generate the body of an insn to extend Y (with mode MFROM)
4923 into X (with mode MTO). Do zero-extension if UNSIGNEDP is nonzero. */
4926 gen_extend_insn (rtx x
, rtx y
, enum machine_mode mto
,
4927 enum machine_mode mfrom
, int unsignedp
)
4929 enum insn_code icode
= can_extend_p (mto
, mfrom
, unsignedp
);
4930 return GEN_FCN (icode
) (x
, y
);
4933 /* can_fix_p and can_float_p say whether the target machine
4934 can directly convert a given fixed point type to
4935 a given floating point type, or vice versa.
4936 The returned value is the CODE_FOR_... value to use,
4937 or CODE_FOR_nothing if these modes cannot be directly converted.
4939 *TRUNCP_PTR is set to 1 if it is necessary to output
4940 an explicit FTRUNC insn before the fix insn; otherwise 0. */
4942 static enum insn_code
4943 can_fix_p (enum machine_mode fixmode
, enum machine_mode fltmode
,
4944 int unsignedp
, int *truncp_ptr
)
4947 enum insn_code icode
;
4949 tab
= unsignedp
? ufixtrunc_optab
: sfixtrunc_optab
;
4950 icode
= convert_optab_handler (tab
, fixmode
, fltmode
);
4951 if (icode
!= CODE_FOR_nothing
)
4957 /* FIXME: This requires a port to define both FIX and FTRUNC pattern
4958 for this to work. We need to rework the fix* and ftrunc* patterns
4959 and documentation. */
4960 tab
= unsignedp
? ufix_optab
: sfix_optab
;
4961 icode
= convert_optab_handler (tab
, fixmode
, fltmode
);
4962 if (icode
!= CODE_FOR_nothing
4963 && optab_handler (ftrunc_optab
, fltmode
) != CODE_FOR_nothing
)
4970 return CODE_FOR_nothing
;
4974 can_float_p (enum machine_mode fltmode
, enum machine_mode fixmode
,
4979 tab
= unsignedp
? ufloat_optab
: sfloat_optab
;
4980 return convert_optab_handler (tab
, fltmode
, fixmode
);
4983 /* Function supportable_convert_operation
4985 Check whether an operation represented by the code CODE is a
4986 convert operation that is supported by the target platform in
4987 vector form (i.e., when operating on arguments of type VECTYPE_IN
4988 producing a result of type VECTYPE_OUT).
4990 Convert operations we currently support directly are FIX_TRUNC and FLOAT.
4991 This function checks if these operations are supported
4992 by the target platform either directly (via vector tree-codes), or via
4996 - CODE1 is code of vector operation to be used when
4997 vectorizing the operation, if available.
4998 - DECL is decl of target builtin functions to be used
4999 when vectorizing the operation, if available. In this case,
5000 CODE1 is CALL_EXPR. */
5003 supportable_convert_operation (enum tree_code code
,
5004 tree vectype_out
, tree vectype_in
,
5005 tree
*decl
, enum tree_code
*code1
)
5007 enum machine_mode m1
,m2
;
5010 m1
= TYPE_MODE (vectype_out
);
5011 m2
= TYPE_MODE (vectype_in
);
5013 /* First check if we can done conversion directly. */
5014 if ((code
== FIX_TRUNC_EXPR
5015 && can_fix_p (m1
,m2
,TYPE_UNSIGNED (vectype_out
), &truncp
)
5016 != CODE_FOR_nothing
)
5017 || (code
== FLOAT_EXPR
5018 && can_float_p (m1
,m2
,TYPE_UNSIGNED (vectype_in
))
5019 != CODE_FOR_nothing
))
5025 /* Now check for builtin. */
5026 if (targetm
.vectorize
.builtin_conversion
5027 && targetm
.vectorize
.builtin_conversion (code
, vectype_out
, vectype_in
))
5030 *decl
= targetm
.vectorize
.builtin_conversion (code
, vectype_out
, vectype_in
);
5037 /* Generate code to convert FROM to floating point
5038 and store in TO. FROM must be fixed point and not VOIDmode.
5039 UNSIGNEDP nonzero means regard FROM as unsigned.
5040 Normally this is done by correcting the final value
5041 if it is negative. */
5044 expand_float (rtx to
, rtx from
, int unsignedp
)
5046 enum insn_code icode
;
5048 enum machine_mode fmode
, imode
;
5049 bool can_do_signed
= false;
5051 /* Crash now, because we won't be able to decide which mode to use. */
5052 gcc_assert (GET_MODE (from
) != VOIDmode
);
5054 /* Look for an insn to do the conversion. Do it in the specified
5055 modes if possible; otherwise convert either input, output or both to
5056 wider mode. If the integer mode is wider than the mode of FROM,
5057 we can do the conversion signed even if the input is unsigned. */
5059 for (fmode
= GET_MODE (to
); fmode
!= VOIDmode
;
5060 fmode
= GET_MODE_WIDER_MODE (fmode
))
5061 for (imode
= GET_MODE (from
); imode
!= VOIDmode
;
5062 imode
= GET_MODE_WIDER_MODE (imode
))
5064 int doing_unsigned
= unsignedp
;
5066 if (fmode
!= GET_MODE (to
)
5067 && significand_size (fmode
) < GET_MODE_PRECISION (GET_MODE (from
)))
5070 icode
= can_float_p (fmode
, imode
, unsignedp
);
5071 if (icode
== CODE_FOR_nothing
&& unsignedp
)
5073 enum insn_code scode
= can_float_p (fmode
, imode
, 0);
5074 if (scode
!= CODE_FOR_nothing
)
5075 can_do_signed
= true;
5076 if (imode
!= GET_MODE (from
))
5077 icode
= scode
, doing_unsigned
= 0;
5080 if (icode
!= CODE_FOR_nothing
)
5082 if (imode
!= GET_MODE (from
))
5083 from
= convert_to_mode (imode
, from
, unsignedp
);
5085 if (fmode
!= GET_MODE (to
))
5086 target
= gen_reg_rtx (fmode
);
5088 emit_unop_insn (icode
, target
, from
,
5089 doing_unsigned
? UNSIGNED_FLOAT
: FLOAT
);
5092 convert_move (to
, target
, 0);
5097 /* Unsigned integer, and no way to convert directly. Convert as signed,
5098 then unconditionally adjust the result. */
5099 if (unsignedp
&& can_do_signed
)
5101 rtx_code_label
*label
= gen_label_rtx ();
5103 REAL_VALUE_TYPE offset
;
5105 /* Look for a usable floating mode FMODE wider than the source and at
5106 least as wide as the target. Using FMODE will avoid rounding woes
5107 with unsigned values greater than the signed maximum value. */
5109 for (fmode
= GET_MODE (to
); fmode
!= VOIDmode
;
5110 fmode
= GET_MODE_WIDER_MODE (fmode
))
5111 if (GET_MODE_PRECISION (GET_MODE (from
)) < GET_MODE_BITSIZE (fmode
)
5112 && can_float_p (fmode
, GET_MODE (from
), 0) != CODE_FOR_nothing
)
5115 if (fmode
== VOIDmode
)
5117 /* There is no such mode. Pretend the target is wide enough. */
5118 fmode
= GET_MODE (to
);
5120 /* Avoid double-rounding when TO is narrower than FROM. */
5121 if ((significand_size (fmode
) + 1)
5122 < GET_MODE_PRECISION (GET_MODE (from
)))
5125 rtx_code_label
*neglabel
= gen_label_rtx ();
5127 /* Don't use TARGET if it isn't a register, is a hard register,
5128 or is the wrong mode. */
5130 || REGNO (target
) < FIRST_PSEUDO_REGISTER
5131 || GET_MODE (target
) != fmode
)
5132 target
= gen_reg_rtx (fmode
);
5134 imode
= GET_MODE (from
);
5135 do_pending_stack_adjust ();
5137 /* Test whether the sign bit is set. */
5138 emit_cmp_and_jump_insns (from
, const0_rtx
, LT
, NULL_RTX
, imode
,
5141 /* The sign bit is not set. Convert as signed. */
5142 expand_float (target
, from
, 0);
5143 emit_jump_insn (gen_jump (label
));
5146 /* The sign bit is set.
5147 Convert to a usable (positive signed) value by shifting right
5148 one bit, while remembering if a nonzero bit was shifted
5149 out; i.e., compute (from & 1) | (from >> 1). */
5151 emit_label (neglabel
);
5152 temp
= expand_binop (imode
, and_optab
, from
, const1_rtx
,
5153 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
5154 temp1
= expand_shift (RSHIFT_EXPR
, imode
, from
, 1, NULL_RTX
, 1);
5155 temp
= expand_binop (imode
, ior_optab
, temp
, temp1
, temp
, 1,
5157 expand_float (target
, temp
, 0);
5159 /* Multiply by 2 to undo the shift above. */
5160 temp
= expand_binop (fmode
, add_optab
, target
, target
,
5161 target
, 0, OPTAB_LIB_WIDEN
);
5163 emit_move_insn (target
, temp
);
5165 do_pending_stack_adjust ();
5171 /* If we are about to do some arithmetic to correct for an
5172 unsigned operand, do it in a pseudo-register. */
5174 if (GET_MODE (to
) != fmode
5175 || !REG_P (to
) || REGNO (to
) < FIRST_PSEUDO_REGISTER
)
5176 target
= gen_reg_rtx (fmode
);
5178 /* Convert as signed integer to floating. */
5179 expand_float (target
, from
, 0);
5181 /* If FROM is negative (and therefore TO is negative),
5182 correct its value by 2**bitwidth. */
5184 do_pending_stack_adjust ();
5185 emit_cmp_and_jump_insns (from
, const0_rtx
, GE
, NULL_RTX
, GET_MODE (from
),
5189 real_2expN (&offset
, GET_MODE_PRECISION (GET_MODE (from
)), fmode
);
5190 temp
= expand_binop (fmode
, add_optab
, target
,
5191 CONST_DOUBLE_FROM_REAL_VALUE (offset
, fmode
),
5192 target
, 0, OPTAB_LIB_WIDEN
);
5194 emit_move_insn (target
, temp
);
5196 do_pending_stack_adjust ();
5201 /* No hardware instruction available; call a library routine. */
5206 convert_optab tab
= unsignedp
? ufloat_optab
: sfloat_optab
;
5208 if (GET_MODE_SIZE (GET_MODE (from
)) < GET_MODE_SIZE (SImode
))
5209 from
= convert_to_mode (SImode
, from
, unsignedp
);
5211 libfunc
= convert_optab_libfunc (tab
, GET_MODE (to
), GET_MODE (from
));
5212 gcc_assert (libfunc
);
5216 value
= emit_library_call_value (libfunc
, NULL_RTX
, LCT_CONST
,
5217 GET_MODE (to
), 1, from
,
5219 insns
= get_insns ();
5222 emit_libcall_block (insns
, target
, value
,
5223 gen_rtx_fmt_e (unsignedp
? UNSIGNED_FLOAT
: FLOAT
,
5224 GET_MODE (to
), from
));
5229 /* Copy result to requested destination
5230 if we have been computing in a temp location. */
5234 if (GET_MODE (target
) == GET_MODE (to
))
5235 emit_move_insn (to
, target
);
5237 convert_move (to
, target
, 0);
5241 /* Generate code to convert FROM to fixed point and store in TO. FROM
5242 must be floating point. */
5245 expand_fix (rtx to
, rtx from
, int unsignedp
)
5247 enum insn_code icode
;
5249 enum machine_mode fmode
, imode
;
5252 /* We first try to find a pair of modes, one real and one integer, at
5253 least as wide as FROM and TO, respectively, in which we can open-code
5254 this conversion. If the integer mode is wider than the mode of TO,
5255 we can do the conversion either signed or unsigned. */
5257 for (fmode
= GET_MODE (from
); fmode
!= VOIDmode
;
5258 fmode
= GET_MODE_WIDER_MODE (fmode
))
5259 for (imode
= GET_MODE (to
); imode
!= VOIDmode
;
5260 imode
= GET_MODE_WIDER_MODE (imode
))
5262 int doing_unsigned
= unsignedp
;
5264 icode
= can_fix_p (imode
, fmode
, unsignedp
, &must_trunc
);
5265 if (icode
== CODE_FOR_nothing
&& imode
!= GET_MODE (to
) && unsignedp
)
5266 icode
= can_fix_p (imode
, fmode
, 0, &must_trunc
), doing_unsigned
= 0;
5268 if (icode
!= CODE_FOR_nothing
)
5270 rtx_insn
*last
= get_last_insn ();
5271 if (fmode
!= GET_MODE (from
))
5272 from
= convert_to_mode (fmode
, from
, 0);
5276 rtx temp
= gen_reg_rtx (GET_MODE (from
));
5277 from
= expand_unop (GET_MODE (from
), ftrunc_optab
, from
,
5281 if (imode
!= GET_MODE (to
))
5282 target
= gen_reg_rtx (imode
);
5284 if (maybe_emit_unop_insn (icode
, target
, from
,
5285 doing_unsigned
? UNSIGNED_FIX
: FIX
))
5288 convert_move (to
, target
, unsignedp
);
5291 delete_insns_since (last
);
5295 /* For an unsigned conversion, there is one more way to do it.
5296 If we have a signed conversion, we generate code that compares
5297 the real value to the largest representable positive number. If if
5298 is smaller, the conversion is done normally. Otherwise, subtract
5299 one plus the highest signed number, convert, and add it back.
5301 We only need to check all real modes, since we know we didn't find
5302 anything with a wider integer mode.
5304 This code used to extend FP value into mode wider than the destination.
5305 This is needed for decimal float modes which cannot accurately
5306 represent one plus the highest signed number of the same size, but
5307 not for binary modes. Consider, for instance conversion from SFmode
5310 The hot path through the code is dealing with inputs smaller than 2^63
5311 and doing just the conversion, so there is no bits to lose.
5313 In the other path we know the value is positive in the range 2^63..2^64-1
5314 inclusive. (as for other input overflow happens and result is undefined)
5315 So we know that the most important bit set in mantissa corresponds to
5316 2^63. The subtraction of 2^63 should not generate any rounding as it
5317 simply clears out that bit. The rest is trivial. */
5319 if (unsignedp
&& GET_MODE_PRECISION (GET_MODE (to
)) <= HOST_BITS_PER_WIDE_INT
)
5320 for (fmode
= GET_MODE (from
); fmode
!= VOIDmode
;
5321 fmode
= GET_MODE_WIDER_MODE (fmode
))
5322 if (CODE_FOR_nothing
!= can_fix_p (GET_MODE (to
), fmode
, 0, &must_trunc
)
5323 && (!DECIMAL_FLOAT_MODE_P (fmode
)
5324 || GET_MODE_BITSIZE (fmode
) > GET_MODE_PRECISION (GET_MODE (to
))))
5327 REAL_VALUE_TYPE offset
;
5329 rtx_code_label
*lab1
, *lab2
;
5332 bitsize
= GET_MODE_PRECISION (GET_MODE (to
));
5333 real_2expN (&offset
, bitsize
- 1, fmode
);
5334 limit
= CONST_DOUBLE_FROM_REAL_VALUE (offset
, fmode
);
5335 lab1
= gen_label_rtx ();
5336 lab2
= gen_label_rtx ();
5338 if (fmode
!= GET_MODE (from
))
5339 from
= convert_to_mode (fmode
, from
, 0);
5341 /* See if we need to do the subtraction. */
5342 do_pending_stack_adjust ();
5343 emit_cmp_and_jump_insns (from
, limit
, GE
, NULL_RTX
, GET_MODE (from
),
5346 /* If not, do the signed "fix" and branch around fixup code. */
5347 expand_fix (to
, from
, 0);
5348 emit_jump_insn (gen_jump (lab2
));
5351 /* Otherwise, subtract 2**(N-1), convert to signed number,
5352 then add 2**(N-1). Do the addition using XOR since this
5353 will often generate better code. */
5355 target
= expand_binop (GET_MODE (from
), sub_optab
, from
, limit
,
5356 NULL_RTX
, 0, OPTAB_LIB_WIDEN
);
5357 expand_fix (to
, target
, 0);
5358 target
= expand_binop (GET_MODE (to
), xor_optab
, to
,
5360 ((HOST_WIDE_INT
) 1 << (bitsize
- 1),
5362 to
, 1, OPTAB_LIB_WIDEN
);
5365 emit_move_insn (to
, target
);
5369 if (optab_handler (mov_optab
, GET_MODE (to
)) != CODE_FOR_nothing
)
5371 /* Make a place for a REG_NOTE and add it. */
5372 insn
= emit_move_insn (to
, to
);
5373 set_dst_reg_note (insn
, REG_EQUAL
,
5374 gen_rtx_fmt_e (UNSIGNED_FIX
, GET_MODE (to
),
5382 /* We can't do it with an insn, so use a library call. But first ensure
5383 that the mode of TO is at least as wide as SImode, since those are the
5384 only library calls we know about. */
5386 if (GET_MODE_SIZE (GET_MODE (to
)) < GET_MODE_SIZE (SImode
))
5388 target
= gen_reg_rtx (SImode
);
5390 expand_fix (target
, from
, unsignedp
);
5398 convert_optab tab
= unsignedp
? ufix_optab
: sfix_optab
;
5399 libfunc
= convert_optab_libfunc (tab
, GET_MODE (to
), GET_MODE (from
));
5400 gcc_assert (libfunc
);
5404 value
= emit_library_call_value (libfunc
, NULL_RTX
, LCT_CONST
,
5405 GET_MODE (to
), 1, from
,
5407 insns
= get_insns ();
5410 emit_libcall_block (insns
, target
, value
,
5411 gen_rtx_fmt_e (unsignedp
? UNSIGNED_FIX
: FIX
,
5412 GET_MODE (to
), from
));
5417 if (GET_MODE (to
) == GET_MODE (target
))
5418 emit_move_insn (to
, target
);
5420 convert_move (to
, target
, 0);
5424 /* Generate code to convert FROM or TO a fixed-point.
5425 If UINTP is true, either TO or FROM is an unsigned integer.
5426 If SATP is true, we need to saturate the result. */
5429 expand_fixed_convert (rtx to
, rtx from
, int uintp
, int satp
)
5431 enum machine_mode to_mode
= GET_MODE (to
);
5432 enum machine_mode from_mode
= GET_MODE (from
);
5434 enum rtx_code this_code
;
5435 enum insn_code code
;
5440 if (to_mode
== from_mode
)
5442 emit_move_insn (to
, from
);
5448 tab
= satp
? satfractuns_optab
: fractuns_optab
;
5449 this_code
= satp
? UNSIGNED_SAT_FRACT
: UNSIGNED_FRACT_CONVERT
;
5453 tab
= satp
? satfract_optab
: fract_optab
;
5454 this_code
= satp
? SAT_FRACT
: FRACT_CONVERT
;
5456 code
= convert_optab_handler (tab
, to_mode
, from_mode
);
5457 if (code
!= CODE_FOR_nothing
)
5459 emit_unop_insn (code
, to
, from
, this_code
);
5463 libfunc
= convert_optab_libfunc (tab
, to_mode
, from_mode
);
5464 gcc_assert (libfunc
);
5467 value
= emit_library_call_value (libfunc
, NULL_RTX
, LCT_CONST
, to_mode
,
5468 1, from
, from_mode
);
5469 insns
= get_insns ();
5472 emit_libcall_block (insns
, to
, value
,
5473 gen_rtx_fmt_e (optab_to_code (tab
), to_mode
, from
));
5476 /* Generate code to convert FROM to fixed point and store in TO. FROM
5477 must be floating point, TO must be signed. Use the conversion optab
5478 TAB to do the conversion. */
5481 expand_sfix_optab (rtx to
, rtx from
, convert_optab tab
)
5483 enum insn_code icode
;
5485 enum machine_mode fmode
, imode
;
5487 /* We first try to find a pair of modes, one real and one integer, at
5488 least as wide as FROM and TO, respectively, in which we can open-code
5489 this conversion. If the integer mode is wider than the mode of TO,
5490 we can do the conversion either signed or unsigned. */
5492 for (fmode
= GET_MODE (from
); fmode
!= VOIDmode
;
5493 fmode
= GET_MODE_WIDER_MODE (fmode
))
5494 for (imode
= GET_MODE (to
); imode
!= VOIDmode
;
5495 imode
= GET_MODE_WIDER_MODE (imode
))
5497 icode
= convert_optab_handler (tab
, imode
, fmode
);
5498 if (icode
!= CODE_FOR_nothing
)
5500 rtx_insn
*last
= get_last_insn ();
5501 if (fmode
!= GET_MODE (from
))
5502 from
= convert_to_mode (fmode
, from
, 0);
5504 if (imode
!= GET_MODE (to
))
5505 target
= gen_reg_rtx (imode
);
5507 if (!maybe_emit_unop_insn (icode
, target
, from
, UNKNOWN
))
5509 delete_insns_since (last
);
5513 convert_move (to
, target
, 0);
5521 /* Report whether we have an instruction to perform the operation
5522 specified by CODE on operands of mode MODE. */
5524 have_insn_for (enum rtx_code code
, enum machine_mode mode
)
5526 return (code_to_optab (code
)
5527 && (optab_handler (code_to_optab (code
), mode
)
5528 != CODE_FOR_nothing
));
5531 /* Initialize the libfunc fields of an entire group of entries in some
5532 optab. Each entry is set equal to a string consisting of a leading
5533 pair of underscores followed by a generic operation name followed by
5534 a mode name (downshifted to lowercase) followed by a single character
5535 representing the number of operands for the given operation (which is
5536 usually one of the characters '2', '3', or '4').
5538 OPTABLE is the table in which libfunc fields are to be initialized.
5539 OPNAME is the generic (string) name of the operation.
5540 SUFFIX is the character which specifies the number of operands for
5541 the given generic operation.
5542 MODE is the mode to generate for.
5546 gen_libfunc (optab optable
, const char *opname
, int suffix
,
5547 enum machine_mode mode
)
5549 unsigned opname_len
= strlen (opname
);
5550 const char *mname
= GET_MODE_NAME (mode
);
5551 unsigned mname_len
= strlen (mname
);
5552 int prefix_len
= targetm
.libfunc_gnu_prefix
? 6 : 2;
5553 int len
= prefix_len
+ opname_len
+ mname_len
+ 1 + 1;
5554 char *libfunc_name
= XALLOCAVEC (char, len
);
5561 if (targetm
.libfunc_gnu_prefix
)
5568 for (q
= opname
; *q
; )
5570 for (q
= mname
; *q
; q
++)
5571 *p
++ = TOLOWER (*q
);
5575 set_optab_libfunc (optable
, mode
,
5576 ggc_alloc_string (libfunc_name
, p
- libfunc_name
));
5579 /* Like gen_libfunc, but verify that integer operation is involved. */
5582 gen_int_libfunc (optab optable
, const char *opname
, char suffix
,
5583 enum machine_mode mode
)
5585 int maxsize
= 2 * BITS_PER_WORD
;
5586 int minsize
= BITS_PER_WORD
;
5588 if (GET_MODE_CLASS (mode
) != MODE_INT
)
5590 if (maxsize
< LONG_LONG_TYPE_SIZE
)
5591 maxsize
= LONG_LONG_TYPE_SIZE
;
5592 if (minsize
> INT_TYPE_SIZE
5593 && (trapv_binoptab_p (optable
)
5594 || trapv_unoptab_p (optable
)))
5595 minsize
= INT_TYPE_SIZE
;
5596 if (GET_MODE_BITSIZE (mode
) < minsize
5597 || GET_MODE_BITSIZE (mode
) > maxsize
)
5599 gen_libfunc (optable
, opname
, suffix
, mode
);
5602 /* Like gen_libfunc, but verify that FP and set decimal prefix if needed. */
5605 gen_fp_libfunc (optab optable
, const char *opname
, char suffix
,
5606 enum machine_mode mode
)
5610 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
)
5611 gen_libfunc (optable
, opname
, suffix
, mode
);
5612 if (DECIMAL_FLOAT_MODE_P (mode
))
5614 dec_opname
= XALLOCAVEC (char, sizeof (DECIMAL_PREFIX
) + strlen (opname
));
5615 /* For BID support, change the name to have either a bid_ or dpd_ prefix
5616 depending on the low level floating format used. */
5617 memcpy (dec_opname
, DECIMAL_PREFIX
, sizeof (DECIMAL_PREFIX
) - 1);
5618 strcpy (dec_opname
+ sizeof (DECIMAL_PREFIX
) - 1, opname
);
5619 gen_libfunc (optable
, dec_opname
, suffix
, mode
);
5623 /* Like gen_libfunc, but verify that fixed-point operation is involved. */
5626 gen_fixed_libfunc (optab optable
, const char *opname
, char suffix
,
5627 enum machine_mode mode
)
5629 if (!ALL_FIXED_POINT_MODE_P (mode
))
5631 gen_libfunc (optable
, opname
, suffix
, mode
);
5634 /* Like gen_libfunc, but verify that signed fixed-point operation is
5638 gen_signed_fixed_libfunc (optab optable
, const char *opname
, char suffix
,
5639 enum machine_mode mode
)
5641 if (!SIGNED_FIXED_POINT_MODE_P (mode
))
5643 gen_libfunc (optable
, opname
, suffix
, mode
);
5646 /* Like gen_libfunc, but verify that unsigned fixed-point operation is
5650 gen_unsigned_fixed_libfunc (optab optable
, const char *opname
, char suffix
,
5651 enum machine_mode mode
)
5653 if (!UNSIGNED_FIXED_POINT_MODE_P (mode
))
5655 gen_libfunc (optable
, opname
, suffix
, mode
);
5658 /* Like gen_libfunc, but verify that FP or INT operation is involved. */
5661 gen_int_fp_libfunc (optab optable
, const char *name
, char suffix
,
5662 enum machine_mode mode
)
5664 if (DECIMAL_FLOAT_MODE_P (mode
) || GET_MODE_CLASS (mode
) == MODE_FLOAT
)
5665 gen_fp_libfunc (optable
, name
, suffix
, mode
);
5666 if (INTEGRAL_MODE_P (mode
))
5667 gen_int_libfunc (optable
, name
, suffix
, mode
);
5670 /* Like gen_libfunc, but verify that FP or INT operation is involved
5671 and add 'v' suffix for integer operation. */
5674 gen_intv_fp_libfunc (optab optable
, const char *name
, char suffix
,
5675 enum machine_mode mode
)
5677 if (DECIMAL_FLOAT_MODE_P (mode
) || GET_MODE_CLASS (mode
) == MODE_FLOAT
)
5678 gen_fp_libfunc (optable
, name
, suffix
, mode
);
5679 if (GET_MODE_CLASS (mode
) == MODE_INT
)
5681 int len
= strlen (name
);
5682 char *v_name
= XALLOCAVEC (char, len
+ 2);
5683 strcpy (v_name
, name
);
5685 v_name
[len
+ 1] = 0;
5686 gen_int_libfunc (optable
, v_name
, suffix
, mode
);
5690 /* Like gen_libfunc, but verify that FP or INT or FIXED operation is
5694 gen_int_fp_fixed_libfunc (optab optable
, const char *name
, char suffix
,
5695 enum machine_mode mode
)
5697 if (DECIMAL_FLOAT_MODE_P (mode
) || GET_MODE_CLASS (mode
) == MODE_FLOAT
)
5698 gen_fp_libfunc (optable
, name
, suffix
, mode
);
5699 if (INTEGRAL_MODE_P (mode
))
5700 gen_int_libfunc (optable
, name
, suffix
, mode
);
5701 if (ALL_FIXED_POINT_MODE_P (mode
))
5702 gen_fixed_libfunc (optable
, name
, suffix
, mode
);
5705 /* Like gen_libfunc, but verify that FP or INT or signed FIXED operation is
5709 gen_int_fp_signed_fixed_libfunc (optab optable
, const char *name
, char suffix
,
5710 enum machine_mode mode
)
5712 if (DECIMAL_FLOAT_MODE_P (mode
) || GET_MODE_CLASS (mode
) == MODE_FLOAT
)
5713 gen_fp_libfunc (optable
, name
, suffix
, mode
);
5714 if (INTEGRAL_MODE_P (mode
))
5715 gen_int_libfunc (optable
, name
, suffix
, mode
);
5716 if (SIGNED_FIXED_POINT_MODE_P (mode
))
5717 gen_signed_fixed_libfunc (optable
, name
, suffix
, mode
);
5720 /* Like gen_libfunc, but verify that INT or FIXED operation is
5724 gen_int_fixed_libfunc (optab optable
, const char *name
, char suffix
,
5725 enum machine_mode mode
)
5727 if (INTEGRAL_MODE_P (mode
))
5728 gen_int_libfunc (optable
, name
, suffix
, mode
);
5729 if (ALL_FIXED_POINT_MODE_P (mode
))
5730 gen_fixed_libfunc (optable
, name
, suffix
, mode
);
5733 /* Like gen_libfunc, but verify that INT or signed FIXED operation is
5737 gen_int_signed_fixed_libfunc (optab optable
, const char *name
, char suffix
,
5738 enum machine_mode mode
)
5740 if (INTEGRAL_MODE_P (mode
))
5741 gen_int_libfunc (optable
, name
, suffix
, mode
);
5742 if (SIGNED_FIXED_POINT_MODE_P (mode
))
5743 gen_signed_fixed_libfunc (optable
, name
, suffix
, mode
);
5746 /* Like gen_libfunc, but verify that INT or unsigned FIXED operation is
5750 gen_int_unsigned_fixed_libfunc (optab optable
, const char *name
, char suffix
,
5751 enum machine_mode mode
)
5753 if (INTEGRAL_MODE_P (mode
))
5754 gen_int_libfunc (optable
, name
, suffix
, mode
);
5755 if (UNSIGNED_FIXED_POINT_MODE_P (mode
))
5756 gen_unsigned_fixed_libfunc (optable
, name
, suffix
, mode
);
5759 /* Initialize the libfunc fields of an entire group of entries of an
5760 inter-mode-class conversion optab. The string formation rules are
5761 similar to the ones for init_libfuncs, above, but instead of having
5762 a mode name and an operand count these functions have two mode names
5763 and no operand count. */
5766 gen_interclass_conv_libfunc (convert_optab tab
,
5768 enum machine_mode tmode
,
5769 enum machine_mode fmode
)
5771 size_t opname_len
= strlen (opname
);
5772 size_t mname_len
= 0;
5774 const char *fname
, *tname
;
5776 int prefix_len
= targetm
.libfunc_gnu_prefix
? 6 : 2;
5777 char *libfunc_name
, *suffix
;
5778 char *nondec_name
, *dec_name
, *nondec_suffix
, *dec_suffix
;
5781 /* If this is a decimal conversion, add the current BID vs. DPD prefix that
5782 depends on which underlying decimal floating point format is used. */
5783 const size_t dec_len
= sizeof (DECIMAL_PREFIX
) - 1;
5785 mname_len
= strlen (GET_MODE_NAME (tmode
)) + strlen (GET_MODE_NAME (fmode
));
5787 nondec_name
= XALLOCAVEC (char, prefix_len
+ opname_len
+ mname_len
+ 1 + 1);
5788 nondec_name
[0] = '_';
5789 nondec_name
[1] = '_';
5790 if (targetm
.libfunc_gnu_prefix
)
5792 nondec_name
[2] = 'g';
5793 nondec_name
[3] = 'n';
5794 nondec_name
[4] = 'u';
5795 nondec_name
[5] = '_';
5798 memcpy (&nondec_name
[prefix_len
], opname
, opname_len
);
5799 nondec_suffix
= nondec_name
+ opname_len
+ prefix_len
;
5801 dec_name
= XALLOCAVEC (char, 2 + dec_len
+ opname_len
+ mname_len
+ 1 + 1);
5804 memcpy (&dec_name
[2], DECIMAL_PREFIX
, dec_len
);
5805 memcpy (&dec_name
[2+dec_len
], opname
, opname_len
);
5806 dec_suffix
= dec_name
+ dec_len
+ opname_len
+ 2;
5808 fname
= GET_MODE_NAME (fmode
);
5809 tname
= GET_MODE_NAME (tmode
);
5811 if (DECIMAL_FLOAT_MODE_P (fmode
) || DECIMAL_FLOAT_MODE_P (tmode
))
5813 libfunc_name
= dec_name
;
5814 suffix
= dec_suffix
;
5818 libfunc_name
= nondec_name
;
5819 suffix
= nondec_suffix
;
5823 for (q
= fname
; *q
; p
++, q
++)
5825 for (q
= tname
; *q
; p
++, q
++)
5830 set_conv_libfunc (tab
, tmode
, fmode
,
5831 ggc_alloc_string (libfunc_name
, p
- libfunc_name
));
5834 /* Same as gen_interclass_conv_libfunc but verify that we are producing
5835 int->fp conversion. */
5838 gen_int_to_fp_conv_libfunc (convert_optab tab
,
5840 enum machine_mode tmode
,
5841 enum machine_mode fmode
)
5843 if (GET_MODE_CLASS (fmode
) != MODE_INT
)
5845 if (GET_MODE_CLASS (tmode
) != MODE_FLOAT
&& !DECIMAL_FLOAT_MODE_P (tmode
))
5847 gen_interclass_conv_libfunc (tab
, opname
, tmode
, fmode
);
5850 /* ufloat_optab is special by using floatun for FP and floatuns decimal fp
5854 gen_ufloat_conv_libfunc (convert_optab tab
,
5855 const char *opname ATTRIBUTE_UNUSED
,
5856 enum machine_mode tmode
,
5857 enum machine_mode fmode
)
5859 if (DECIMAL_FLOAT_MODE_P (tmode
))
5860 gen_int_to_fp_conv_libfunc (tab
, "floatuns", tmode
, fmode
);
5862 gen_int_to_fp_conv_libfunc (tab
, "floatun", tmode
, fmode
);
5865 /* Same as gen_interclass_conv_libfunc but verify that we are producing
5866 fp->int conversion. */
5869 gen_int_to_fp_nondecimal_conv_libfunc (convert_optab tab
,
5871 enum machine_mode tmode
,
5872 enum machine_mode fmode
)
5874 if (GET_MODE_CLASS (fmode
) != MODE_INT
)
5876 if (GET_MODE_CLASS (tmode
) != MODE_FLOAT
)
5878 gen_interclass_conv_libfunc (tab
, opname
, tmode
, fmode
);
5881 /* Same as gen_interclass_conv_libfunc but verify that we are producing
5882 fp->int conversion with no decimal floating point involved. */
5885 gen_fp_to_int_conv_libfunc (convert_optab tab
,
5887 enum machine_mode tmode
,
5888 enum machine_mode fmode
)
5890 if (GET_MODE_CLASS (fmode
) != MODE_FLOAT
&& !DECIMAL_FLOAT_MODE_P (fmode
))
5892 if (GET_MODE_CLASS (tmode
) != MODE_INT
)
5894 gen_interclass_conv_libfunc (tab
, opname
, tmode
, fmode
);
5897 /* Initialize the libfunc fields of an of an intra-mode-class conversion optab.
5898 The string formation rules are
5899 similar to the ones for init_libfunc, above. */
5902 gen_intraclass_conv_libfunc (convert_optab tab
, const char *opname
,
5903 enum machine_mode tmode
, enum machine_mode fmode
)
5905 size_t opname_len
= strlen (opname
);
5906 size_t mname_len
= 0;
5908 const char *fname
, *tname
;
5910 int prefix_len
= targetm
.libfunc_gnu_prefix
? 6 : 2;
5911 char *nondec_name
, *dec_name
, *nondec_suffix
, *dec_suffix
;
5912 char *libfunc_name
, *suffix
;
5915 /* If this is a decimal conversion, add the current BID vs. DPD prefix that
5916 depends on which underlying decimal floating point format is used. */
5917 const size_t dec_len
= sizeof (DECIMAL_PREFIX
) - 1;
5919 mname_len
= strlen (GET_MODE_NAME (tmode
)) + strlen (GET_MODE_NAME (fmode
));
5921 nondec_name
= XALLOCAVEC (char, 2 + opname_len
+ mname_len
+ 1 + 1);
5922 nondec_name
[0] = '_';
5923 nondec_name
[1] = '_';
5924 if (targetm
.libfunc_gnu_prefix
)
5926 nondec_name
[2] = 'g';
5927 nondec_name
[3] = 'n';
5928 nondec_name
[4] = 'u';
5929 nondec_name
[5] = '_';
5931 memcpy (&nondec_name
[prefix_len
], opname
, opname_len
);
5932 nondec_suffix
= nondec_name
+ opname_len
+ prefix_len
;
5934 dec_name
= XALLOCAVEC (char, 2 + dec_len
+ opname_len
+ mname_len
+ 1 + 1);
5937 memcpy (&dec_name
[2], DECIMAL_PREFIX
, dec_len
);
5938 memcpy (&dec_name
[2 + dec_len
], opname
, opname_len
);
5939 dec_suffix
= dec_name
+ dec_len
+ opname_len
+ 2;
5941 fname
= GET_MODE_NAME (fmode
);
5942 tname
= GET_MODE_NAME (tmode
);
5944 if (DECIMAL_FLOAT_MODE_P (fmode
) || DECIMAL_FLOAT_MODE_P (tmode
))
5946 libfunc_name
= dec_name
;
5947 suffix
= dec_suffix
;
5951 libfunc_name
= nondec_name
;
5952 suffix
= nondec_suffix
;
5956 for (q
= fname
; *q
; p
++, q
++)
5958 for (q
= tname
; *q
; p
++, q
++)
5964 set_conv_libfunc (tab
, tmode
, fmode
,
5965 ggc_alloc_string (libfunc_name
, p
- libfunc_name
));
5968 /* Pick proper libcall for trunc_optab. We need to chose if we do
5969 truncation or extension and interclass or intraclass. */
5972 gen_trunc_conv_libfunc (convert_optab tab
,
5974 enum machine_mode tmode
,
5975 enum machine_mode fmode
)
5977 if (GET_MODE_CLASS (tmode
) != MODE_FLOAT
&& !DECIMAL_FLOAT_MODE_P (tmode
))
5979 if (GET_MODE_CLASS (fmode
) != MODE_FLOAT
&& !DECIMAL_FLOAT_MODE_P (fmode
))
5984 if ((GET_MODE_CLASS (tmode
) == MODE_FLOAT
&& DECIMAL_FLOAT_MODE_P (fmode
))
5985 || (GET_MODE_CLASS (fmode
) == MODE_FLOAT
&& DECIMAL_FLOAT_MODE_P (tmode
)))
5986 gen_interclass_conv_libfunc (tab
, opname
, tmode
, fmode
);
5988 if (GET_MODE_PRECISION (fmode
) <= GET_MODE_PRECISION (tmode
))
5991 if ((GET_MODE_CLASS (tmode
) == MODE_FLOAT
5992 && GET_MODE_CLASS (fmode
) == MODE_FLOAT
)
5993 || (DECIMAL_FLOAT_MODE_P (fmode
) && DECIMAL_FLOAT_MODE_P (tmode
)))
5994 gen_intraclass_conv_libfunc (tab
, opname
, tmode
, fmode
);
5997 /* Pick proper libcall for extend_optab. We need to chose if we do
5998 truncation or extension and interclass or intraclass. */
6001 gen_extend_conv_libfunc (convert_optab tab
,
6002 const char *opname ATTRIBUTE_UNUSED
,
6003 enum machine_mode tmode
,
6004 enum machine_mode fmode
)
6006 if (GET_MODE_CLASS (tmode
) != MODE_FLOAT
&& !DECIMAL_FLOAT_MODE_P (tmode
))
6008 if (GET_MODE_CLASS (fmode
) != MODE_FLOAT
&& !DECIMAL_FLOAT_MODE_P (fmode
))
6013 if ((GET_MODE_CLASS (tmode
) == MODE_FLOAT
&& DECIMAL_FLOAT_MODE_P (fmode
))
6014 || (GET_MODE_CLASS (fmode
) == MODE_FLOAT
&& DECIMAL_FLOAT_MODE_P (tmode
)))
6015 gen_interclass_conv_libfunc (tab
, opname
, tmode
, fmode
);
6017 if (GET_MODE_PRECISION (fmode
) > GET_MODE_PRECISION (tmode
))
6020 if ((GET_MODE_CLASS (tmode
) == MODE_FLOAT
6021 && GET_MODE_CLASS (fmode
) == MODE_FLOAT
)
6022 || (DECIMAL_FLOAT_MODE_P (fmode
) && DECIMAL_FLOAT_MODE_P (tmode
)))
6023 gen_intraclass_conv_libfunc (tab
, opname
, tmode
, fmode
);
6026 /* Pick proper libcall for fract_optab. We need to chose if we do
6027 interclass or intraclass. */
6030 gen_fract_conv_libfunc (convert_optab tab
,
6032 enum machine_mode tmode
,
6033 enum machine_mode fmode
)
6037 if (!(ALL_FIXED_POINT_MODE_P (tmode
) || ALL_FIXED_POINT_MODE_P (fmode
)))
6040 if (GET_MODE_CLASS (tmode
) == GET_MODE_CLASS (fmode
))
6041 gen_intraclass_conv_libfunc (tab
, opname
, tmode
, fmode
);
6043 gen_interclass_conv_libfunc (tab
, opname
, tmode
, fmode
);
6046 /* Pick proper libcall for fractuns_optab. */
6049 gen_fractuns_conv_libfunc (convert_optab tab
,
6051 enum machine_mode tmode
,
6052 enum machine_mode fmode
)
6056 /* One mode must be a fixed-point mode, and the other must be an integer
6058 if (!((ALL_FIXED_POINT_MODE_P (tmode
) && GET_MODE_CLASS (fmode
) == MODE_INT
)
6059 || (ALL_FIXED_POINT_MODE_P (fmode
)
6060 && GET_MODE_CLASS (tmode
) == MODE_INT
)))
6063 gen_interclass_conv_libfunc (tab
, opname
, tmode
, fmode
);
6066 /* Pick proper libcall for satfract_optab. We need to chose if we do
6067 interclass or intraclass. */
6070 gen_satfract_conv_libfunc (convert_optab tab
,
6072 enum machine_mode tmode
,
6073 enum machine_mode fmode
)
6077 /* TMODE must be a fixed-point mode. */
6078 if (!ALL_FIXED_POINT_MODE_P (tmode
))
6081 if (GET_MODE_CLASS (tmode
) == GET_MODE_CLASS (fmode
))
6082 gen_intraclass_conv_libfunc (tab
, opname
, tmode
, fmode
);
6084 gen_interclass_conv_libfunc (tab
, opname
, tmode
, fmode
);
6087 /* Pick proper libcall for satfractuns_optab. */
6090 gen_satfractuns_conv_libfunc (convert_optab tab
,
6092 enum machine_mode tmode
,
6093 enum machine_mode fmode
)
6097 /* TMODE must be a fixed-point mode, and FMODE must be an integer mode. */
6098 if (!(ALL_FIXED_POINT_MODE_P (tmode
) && GET_MODE_CLASS (fmode
) == MODE_INT
))
6101 gen_interclass_conv_libfunc (tab
, opname
, tmode
, fmode
);
6104 /* A table of previously-created libfuncs, hashed by name. */
6105 static GTY ((param_is (union tree_node
))) htab_t libfunc_decls
;
6107 /* Hashtable callbacks for libfunc_decls. */
6110 libfunc_decl_hash (const void *entry
)
6112 return IDENTIFIER_HASH_VALUE (DECL_NAME ((const_tree
) entry
));
6116 libfunc_decl_eq (const void *entry1
, const void *entry2
)
6118 return DECL_NAME ((const_tree
) entry1
) == (const_tree
) entry2
;
6121 /* Build a decl for a libfunc named NAME. */
6124 build_libfunc_function (const char *name
)
6126 tree decl
= build_decl (UNKNOWN_LOCATION
, FUNCTION_DECL
,
6127 get_identifier (name
),
6128 build_function_type (integer_type_node
, NULL_TREE
));
6129 /* ??? We don't have any type information except for this is
6130 a function. Pretend this is "int foo()". */
6131 DECL_ARTIFICIAL (decl
) = 1;
6132 DECL_EXTERNAL (decl
) = 1;
6133 TREE_PUBLIC (decl
) = 1;
6134 gcc_assert (DECL_ASSEMBLER_NAME (decl
));
6136 /* Zap the nonsensical SYMBOL_REF_DECL for this. What we're left with
6137 are the flags assigned by targetm.encode_section_info. */
6138 SET_SYMBOL_REF_DECL (XEXP (DECL_RTL (decl
), 0), NULL
);
6144 init_one_libfunc (const char *name
)
6150 if (libfunc_decls
== NULL
)
6151 libfunc_decls
= htab_create_ggc (37, libfunc_decl_hash
,
6152 libfunc_decl_eq
, NULL
);
6154 /* See if we have already created a libfunc decl for this function. */
6155 id
= get_identifier (name
);
6156 hash
= IDENTIFIER_HASH_VALUE (id
);
6157 slot
= htab_find_slot_with_hash (libfunc_decls
, id
, hash
, INSERT
);
6158 decl
= (tree
) *slot
;
6161 /* Create a new decl, so that it can be passed to
6162 targetm.encode_section_info. */
6163 decl
= build_libfunc_function (name
);
6166 return XEXP (DECL_RTL (decl
), 0);
6169 /* Adjust the assembler name of libfunc NAME to ASMSPEC. */
6172 set_user_assembler_libfunc (const char *name
, const char *asmspec
)
6178 id
= get_identifier (name
);
6179 hash
= IDENTIFIER_HASH_VALUE (id
);
6180 slot
= htab_find_slot_with_hash (libfunc_decls
, id
, hash
, NO_INSERT
);
6182 decl
= (tree
) *slot
;
6183 set_user_assembler_name (decl
, asmspec
);
6184 return XEXP (DECL_RTL (decl
), 0);
6187 /* Call this to reset the function entry for one optab (OPTABLE) in mode
6188 MODE to NAME, which should be either 0 or a string constant. */
6190 set_optab_libfunc (optab op
, enum machine_mode mode
, const char *name
)
6193 struct libfunc_entry e
;
6194 struct libfunc_entry
**slot
;
6201 val
= init_one_libfunc (name
);
6204 slot
= (struct libfunc_entry
**) htab_find_slot (libfunc_hash
, &e
, INSERT
);
6206 *slot
= ggc_alloc
<libfunc_entry
> ();
6208 (*slot
)->mode1
= mode
;
6209 (*slot
)->mode2
= VOIDmode
;
6210 (*slot
)->libfunc
= val
;
6213 /* Call this to reset the function entry for one conversion optab
6214 (OPTABLE) from mode FMODE to mode TMODE to NAME, which should be
6215 either 0 or a string constant. */
6217 set_conv_libfunc (convert_optab optab
, enum machine_mode tmode
,
6218 enum machine_mode fmode
, const char *name
)
6221 struct libfunc_entry e
;
6222 struct libfunc_entry
**slot
;
6229 val
= init_one_libfunc (name
);
6232 slot
= (struct libfunc_entry
**) htab_find_slot (libfunc_hash
, &e
, INSERT
);
6234 *slot
= ggc_alloc
<libfunc_entry
> ();
6235 (*slot
)->op
= optab
;
6236 (*slot
)->mode1
= tmode
;
6237 (*slot
)->mode2
= fmode
;
6238 (*slot
)->libfunc
= val
;
6241 /* Call this to initialize the contents of the optabs
6242 appropriately for the current target machine. */
6248 htab_empty (libfunc_hash
);
6250 libfunc_hash
= htab_create_ggc (10, hash_libfunc
, eq_libfunc
, NULL
);
6252 /* Fill in the optabs with the insns we support. */
6253 init_all_optabs (this_fn_optabs
);
6255 /* The ffs function operates on `int'. Fall back on it if we do not
6256 have a libgcc2 function for that width. */
6257 if (INT_TYPE_SIZE
< BITS_PER_WORD
)
6258 set_optab_libfunc (ffs_optab
, mode_for_size (INT_TYPE_SIZE
, MODE_INT
, 0),
6261 /* Explicitly initialize the bswap libfuncs since we need them to be
6262 valid for things other than word_mode. */
6263 if (targetm
.libfunc_gnu_prefix
)
6265 set_optab_libfunc (bswap_optab
, SImode
, "__gnu_bswapsi2");
6266 set_optab_libfunc (bswap_optab
, DImode
, "__gnu_bswapdi2");
6270 set_optab_libfunc (bswap_optab
, SImode
, "__bswapsi2");
6271 set_optab_libfunc (bswap_optab
, DImode
, "__bswapdi2");
6274 /* Use cabs for double complex abs, since systems generally have cabs.
6275 Don't define any libcall for float complex, so that cabs will be used. */
6276 if (complex_double_type_node
)
6277 set_optab_libfunc (abs_optab
, TYPE_MODE (complex_double_type_node
),
6280 abort_libfunc
= init_one_libfunc ("abort");
6281 memcpy_libfunc
= init_one_libfunc ("memcpy");
6282 memmove_libfunc
= init_one_libfunc ("memmove");
6283 memcmp_libfunc
= init_one_libfunc ("memcmp");
6284 memset_libfunc
= init_one_libfunc ("memset");
6285 setbits_libfunc
= init_one_libfunc ("__setbits");
6287 #ifndef DONT_USE_BUILTIN_SETJMP
6288 setjmp_libfunc
= init_one_libfunc ("__builtin_setjmp");
6289 longjmp_libfunc
= init_one_libfunc ("__builtin_longjmp");
6291 setjmp_libfunc
= init_one_libfunc ("setjmp");
6292 longjmp_libfunc
= init_one_libfunc ("longjmp");
6294 unwind_sjlj_register_libfunc
= init_one_libfunc ("_Unwind_SjLj_Register");
6295 unwind_sjlj_unregister_libfunc
6296 = init_one_libfunc ("_Unwind_SjLj_Unregister");
6298 /* For function entry/exit instrumentation. */
6299 profile_function_entry_libfunc
6300 = init_one_libfunc ("__cyg_profile_func_enter");
6301 profile_function_exit_libfunc
6302 = init_one_libfunc ("__cyg_profile_func_exit");
6304 gcov_flush_libfunc
= init_one_libfunc ("__gcov_flush");
6306 /* Allow the target to add more libcalls or rename some, etc. */
6307 targetm
.init_libfuncs ();
6310 /* Use the current target and options to initialize
6311 TREE_OPTIMIZATION_OPTABS (OPTNODE). */
6314 init_tree_optimization_optabs (tree optnode
)
6316 /* Quick exit if we have already computed optabs for this target. */
6317 if (TREE_OPTIMIZATION_BASE_OPTABS (optnode
) == this_target_optabs
)
6320 /* Forget any previous information and set up for the current target. */
6321 TREE_OPTIMIZATION_BASE_OPTABS (optnode
) = this_target_optabs
;
6322 struct target_optabs
*tmp_optabs
= (struct target_optabs
*)
6323 TREE_OPTIMIZATION_OPTABS (optnode
);
6325 memset (tmp_optabs
, 0, sizeof (struct target_optabs
));
6327 tmp_optabs
= ggc_alloc
<target_optabs
> ();
6329 /* Generate a new set of optabs into tmp_optabs. */
6330 init_all_optabs (tmp_optabs
);
6332 /* If the optabs changed, record it. */
6333 if (memcmp (tmp_optabs
, this_target_optabs
, sizeof (struct target_optabs
)))
6334 TREE_OPTIMIZATION_OPTABS (optnode
) = tmp_optabs
;
6337 TREE_OPTIMIZATION_OPTABS (optnode
) = NULL
;
6338 ggc_free (tmp_optabs
);
6342 /* A helper function for init_sync_libfuncs. Using the basename BASE,
6343 install libfuncs into TAB for BASE_N for 1 <= N <= MAX. */
6346 init_sync_libfuncs_1 (optab tab
, const char *base
, int max
)
6348 enum machine_mode mode
;
6350 size_t len
= strlen (base
);
6353 gcc_assert (max
<= 8);
6354 gcc_assert (len
+ 3 < sizeof (buf
));
6356 memcpy (buf
, base
, len
);
6359 buf
[len
+ 2] = '\0';
6362 for (i
= 1; i
<= max
; i
*= 2)
6364 buf
[len
+ 1] = '0' + i
;
6365 set_optab_libfunc (tab
, mode
, buf
);
6366 mode
= GET_MODE_2XWIDER_MODE (mode
);
6371 init_sync_libfuncs (int max
)
6373 if (!flag_sync_libcalls
)
6376 init_sync_libfuncs_1 (sync_compare_and_swap_optab
,
6377 "__sync_val_compare_and_swap", max
);
6378 init_sync_libfuncs_1 (sync_lock_test_and_set_optab
,
6379 "__sync_lock_test_and_set", max
);
6381 init_sync_libfuncs_1 (sync_old_add_optab
, "__sync_fetch_and_add", max
);
6382 init_sync_libfuncs_1 (sync_old_sub_optab
, "__sync_fetch_and_sub", max
);
6383 init_sync_libfuncs_1 (sync_old_ior_optab
, "__sync_fetch_and_or", max
);
6384 init_sync_libfuncs_1 (sync_old_and_optab
, "__sync_fetch_and_and", max
);
6385 init_sync_libfuncs_1 (sync_old_xor_optab
, "__sync_fetch_and_xor", max
);
6386 init_sync_libfuncs_1 (sync_old_nand_optab
, "__sync_fetch_and_nand", max
);
6388 init_sync_libfuncs_1 (sync_new_add_optab
, "__sync_add_and_fetch", max
);
6389 init_sync_libfuncs_1 (sync_new_sub_optab
, "__sync_sub_and_fetch", max
);
6390 init_sync_libfuncs_1 (sync_new_ior_optab
, "__sync_or_and_fetch", max
);
6391 init_sync_libfuncs_1 (sync_new_and_optab
, "__sync_and_and_fetch", max
);
6392 init_sync_libfuncs_1 (sync_new_xor_optab
, "__sync_xor_and_fetch", max
);
6393 init_sync_libfuncs_1 (sync_new_nand_optab
, "__sync_nand_and_fetch", max
);
6396 /* Print information about the current contents of the optabs on
6400 debug_optab_libfuncs (void)
6404 /* Dump the arithmetic optabs. */
6405 for (i
= FIRST_NORM_OPTAB
; i
<= LAST_NORMLIB_OPTAB
; ++i
)
6406 for (j
= 0; j
< NUM_MACHINE_MODES
; ++j
)
6408 rtx l
= optab_libfunc ((optab
) i
, (enum machine_mode
) j
);
6411 gcc_assert (GET_CODE (l
) == SYMBOL_REF
);
6412 fprintf (stderr
, "%s\t%s:\t%s\n",
6413 GET_RTX_NAME (optab_to_code ((optab
) i
)),
6419 /* Dump the conversion optabs. */
6420 for (i
= FIRST_CONV_OPTAB
; i
<= LAST_CONVLIB_OPTAB
; ++i
)
6421 for (j
= 0; j
< NUM_MACHINE_MODES
; ++j
)
6422 for (k
= 0; k
< NUM_MACHINE_MODES
; ++k
)
6424 rtx l
= convert_optab_libfunc ((optab
) i
, (enum machine_mode
) j
,
6425 (enum machine_mode
) k
);
6428 gcc_assert (GET_CODE (l
) == SYMBOL_REF
);
6429 fprintf (stderr
, "%s\t%s\t%s:\t%s\n",
6430 GET_RTX_NAME (optab_to_code ((optab
) i
)),
6439 /* Generate insns to trap with code TCODE if OP1 and OP2 satisfy condition
6440 CODE. Return 0 on failure. */
6443 gen_cond_trap (enum rtx_code code
, rtx op1
, rtx op2
, rtx tcode
)
6445 enum machine_mode mode
= GET_MODE (op1
);
6446 enum insn_code icode
;
6450 if (mode
== VOIDmode
)
6453 icode
= optab_handler (ctrap_optab
, mode
);
6454 if (icode
== CODE_FOR_nothing
)
6457 /* Some targets only accept a zero trap code. */
6458 if (!insn_operand_matches (icode
, 3, tcode
))
6461 do_pending_stack_adjust ();
6463 prepare_cmp_insn (op1
, op2
, code
, NULL_RTX
, false, OPTAB_DIRECT
,
6468 insn
= GEN_FCN (icode
) (trap_rtx
, XEXP (trap_rtx
, 0), XEXP (trap_rtx
, 1),
6471 /* If that failed, then give up. */
6479 insn
= get_insns ();
6484 /* Return rtx code for TCODE. Use UNSIGNEDP to select signed
6485 or unsigned operation code. */
6487 static enum rtx_code
6488 get_rtx_code (enum tree_code tcode
, bool unsignedp
)
6500 code
= unsignedp
? LTU
: LT
;
6503 code
= unsignedp
? LEU
: LE
;
6506 code
= unsignedp
? GTU
: GT
;
6509 code
= unsignedp
? GEU
: GE
;
6512 case UNORDERED_EXPR
:
6543 /* Return comparison rtx for COND. Use UNSIGNEDP to select signed or
6544 unsigned operators. Do not generate compare instruction. */
6547 vector_compare_rtx (enum tree_code tcode
, tree t_op0
, tree t_op1
,
6548 bool unsignedp
, enum insn_code icode
)
6550 struct expand_operand ops
[2];
6551 rtx rtx_op0
, rtx_op1
;
6552 enum rtx_code rcode
= get_rtx_code (tcode
, unsignedp
);
6554 gcc_assert (TREE_CODE_CLASS (tcode
) == tcc_comparison
);
6556 /* Expand operands. */
6557 rtx_op0
= expand_expr (t_op0
, NULL_RTX
, TYPE_MODE (TREE_TYPE (t_op0
)),
6559 rtx_op1
= expand_expr (t_op1
, NULL_RTX
, TYPE_MODE (TREE_TYPE (t_op1
)),
6562 create_input_operand (&ops
[0], rtx_op0
, GET_MODE (rtx_op0
));
6563 create_input_operand (&ops
[1], rtx_op1
, GET_MODE (rtx_op1
));
6564 if (!maybe_legitimize_operands (icode
, 4, 2, ops
))
6566 return gen_rtx_fmt_ee (rcode
, VOIDmode
, ops
[0].value
, ops
[1].value
);
6569 /* Return true if VEC_PERM_EXPR can be expanded using SIMD extensions
6570 of the CPU. SEL may be NULL, which stands for an unknown constant. */
6573 can_vec_perm_p (enum machine_mode mode
, bool variable
,
6574 const unsigned char *sel
)
6576 enum machine_mode qimode
;
6578 /* If the target doesn't implement a vector mode for the vector type,
6579 then no operations are supported. */
6580 if (!VECTOR_MODE_P (mode
))
6585 if (direct_optab_handler (vec_perm_const_optab
, mode
) != CODE_FOR_nothing
6587 || targetm
.vectorize
.vec_perm_const_ok
== NULL
6588 || targetm
.vectorize
.vec_perm_const_ok (mode
, sel
)))
6592 if (direct_optab_handler (vec_perm_optab
, mode
) != CODE_FOR_nothing
)
6595 /* We allow fallback to a QI vector mode, and adjust the mask. */
6596 if (GET_MODE_INNER (mode
) == QImode
)
6598 qimode
= mode_for_vector (QImode
, GET_MODE_SIZE (mode
));
6599 if (!VECTOR_MODE_P (qimode
))
6602 /* ??? For completeness, we ought to check the QImode version of
6603 vec_perm_const_optab. But all users of this implicit lowering
6604 feature implement the variable vec_perm_optab. */
6605 if (direct_optab_handler (vec_perm_optab
, qimode
) == CODE_FOR_nothing
)
6608 /* In order to support the lowering of variable permutations,
6609 we need to support shifts and adds. */
6612 if (GET_MODE_UNIT_SIZE (mode
) > 2
6613 && optab_handler (ashl_optab
, mode
) == CODE_FOR_nothing
6614 && optab_handler (vashl_optab
, mode
) == CODE_FOR_nothing
)
6616 if (optab_handler (add_optab
, qimode
) == CODE_FOR_nothing
)
6623 /* A subroutine of expand_vec_perm for expanding one vec_perm insn. */
6626 expand_vec_perm_1 (enum insn_code icode
, rtx target
,
6627 rtx v0
, rtx v1
, rtx sel
)
6629 enum machine_mode tmode
= GET_MODE (target
);
6630 enum machine_mode smode
= GET_MODE (sel
);
6631 struct expand_operand ops
[4];
6633 create_output_operand (&ops
[0], target
, tmode
);
6634 create_input_operand (&ops
[3], sel
, smode
);
6636 /* Make an effort to preserve v0 == v1. The target expander is able to
6637 rely on this to determine if we're permuting a single input operand. */
6638 if (rtx_equal_p (v0
, v1
))
6640 if (!insn_operand_matches (icode
, 1, v0
))
6641 v0
= force_reg (tmode
, v0
);
6642 gcc_checking_assert (insn_operand_matches (icode
, 1, v0
));
6643 gcc_checking_assert (insn_operand_matches (icode
, 2, v0
));
6645 create_fixed_operand (&ops
[1], v0
);
6646 create_fixed_operand (&ops
[2], v0
);
6650 create_input_operand (&ops
[1], v0
, tmode
);
6651 create_input_operand (&ops
[2], v1
, tmode
);
6654 if (maybe_expand_insn (icode
, 4, ops
))
6655 return ops
[0].value
;
6659 /* Generate instructions for vec_perm optab given its mode
6660 and three operands. */
6663 expand_vec_perm (enum machine_mode mode
, rtx v0
, rtx v1
, rtx sel
, rtx target
)
6665 enum insn_code icode
;
6666 enum machine_mode qimode
;
6667 unsigned int i
, w
, e
, u
;
6668 rtx tmp
, sel_qi
= NULL
;
6671 if (!target
|| GET_MODE (target
) != mode
)
6672 target
= gen_reg_rtx (mode
);
6674 w
= GET_MODE_SIZE (mode
);
6675 e
= GET_MODE_NUNITS (mode
);
6676 u
= GET_MODE_UNIT_SIZE (mode
);
6678 /* Set QIMODE to a different vector mode with byte elements.
6679 If no such mode, or if MODE already has byte elements, use VOIDmode. */
6681 if (GET_MODE_INNER (mode
) != QImode
)
6683 qimode
= mode_for_vector (QImode
, w
);
6684 if (!VECTOR_MODE_P (qimode
))
6688 /* If the input is a constant, expand it specially. */
6689 gcc_assert (GET_MODE_CLASS (GET_MODE (sel
)) == MODE_VECTOR_INT
);
6690 if (GET_CODE (sel
) == CONST_VECTOR
)
6692 icode
= direct_optab_handler (vec_perm_const_optab
, mode
);
6693 if (icode
!= CODE_FOR_nothing
)
6695 tmp
= expand_vec_perm_1 (icode
, target
, v0
, v1
, sel
);
6700 /* Fall back to a constant byte-based permutation. */
6701 if (qimode
!= VOIDmode
)
6703 vec
= rtvec_alloc (w
);
6704 for (i
= 0; i
< e
; ++i
)
6706 unsigned int j
, this_e
;
6708 this_e
= INTVAL (CONST_VECTOR_ELT (sel
, i
));
6709 this_e
&= 2 * e
- 1;
6712 for (j
= 0; j
< u
; ++j
)
6713 RTVEC_ELT (vec
, i
* u
+ j
) = GEN_INT (this_e
+ j
);
6715 sel_qi
= gen_rtx_CONST_VECTOR (qimode
, vec
);
6717 icode
= direct_optab_handler (vec_perm_const_optab
, qimode
);
6718 if (icode
!= CODE_FOR_nothing
)
6720 tmp
= mode
!= qimode
? gen_reg_rtx (qimode
) : target
;
6721 tmp
= expand_vec_perm_1 (icode
, tmp
, gen_lowpart (qimode
, v0
),
6722 gen_lowpart (qimode
, v1
), sel_qi
);
6724 return gen_lowpart (mode
, tmp
);
6729 /* Otherwise expand as a fully variable permuation. */
6730 icode
= direct_optab_handler (vec_perm_optab
, mode
);
6731 if (icode
!= CODE_FOR_nothing
)
6733 tmp
= expand_vec_perm_1 (icode
, target
, v0
, v1
, sel
);
6738 /* As a special case to aid several targets, lower the element-based
6739 permutation to a byte-based permutation and try again. */
6740 if (qimode
== VOIDmode
)
6742 icode
= direct_optab_handler (vec_perm_optab
, qimode
);
6743 if (icode
== CODE_FOR_nothing
)
6748 /* Multiply each element by its byte size. */
6749 enum machine_mode selmode
= GET_MODE (sel
);
6751 sel
= expand_simple_binop (selmode
, PLUS
, sel
, sel
,
6752 sel
, 0, OPTAB_DIRECT
);
6754 sel
= expand_simple_binop (selmode
, ASHIFT
, sel
,
6755 GEN_INT (exact_log2 (u
)),
6756 sel
, 0, OPTAB_DIRECT
);
6757 gcc_assert (sel
!= NULL
);
6759 /* Broadcast the low byte each element into each of its bytes. */
6760 vec
= rtvec_alloc (w
);
6761 for (i
= 0; i
< w
; ++i
)
6763 int this_e
= i
/ u
* u
;
6764 if (BYTES_BIG_ENDIAN
)
6766 RTVEC_ELT (vec
, i
) = GEN_INT (this_e
);
6768 tmp
= gen_rtx_CONST_VECTOR (qimode
, vec
);
6769 sel
= gen_lowpart (qimode
, sel
);
6770 sel
= expand_vec_perm (qimode
, sel
, sel
, tmp
, NULL
);
6771 gcc_assert (sel
!= NULL
);
6773 /* Add the byte offset to each byte element. */
6774 /* Note that the definition of the indicies here is memory ordering,
6775 so there should be no difference between big and little endian. */
6776 vec
= rtvec_alloc (w
);
6777 for (i
= 0; i
< w
; ++i
)
6778 RTVEC_ELT (vec
, i
) = GEN_INT (i
% u
);
6779 tmp
= gen_rtx_CONST_VECTOR (qimode
, vec
);
6780 sel_qi
= expand_simple_binop (qimode
, PLUS
, sel
, tmp
,
6781 sel
, 0, OPTAB_DIRECT
);
6782 gcc_assert (sel_qi
!= NULL
);
6785 tmp
= mode
!= qimode
? gen_reg_rtx (qimode
) : target
;
6786 tmp
= expand_vec_perm_1 (icode
, tmp
, gen_lowpart (qimode
, v0
),
6787 gen_lowpart (qimode
, v1
), sel_qi
);
6789 tmp
= gen_lowpart (mode
, tmp
);
6793 /* Return insn code for a conditional operator with a comparison in
6794 mode CMODE, unsigned if UNS is true, resulting in a value of mode VMODE. */
6796 static inline enum insn_code
6797 get_vcond_icode (enum machine_mode vmode
, enum machine_mode cmode
, bool uns
)
6799 enum insn_code icode
= CODE_FOR_nothing
;
6801 icode
= convert_optab_handler (vcondu_optab
, vmode
, cmode
);
6803 icode
= convert_optab_handler (vcond_optab
, vmode
, cmode
);
6807 /* Return TRUE iff, appropriate vector insns are available
6808 for vector cond expr with vector type VALUE_TYPE and a comparison
6809 with operand vector types in CMP_OP_TYPE. */
6812 expand_vec_cond_expr_p (tree value_type
, tree cmp_op_type
)
6814 enum machine_mode value_mode
= TYPE_MODE (value_type
);
6815 enum machine_mode cmp_op_mode
= TYPE_MODE (cmp_op_type
);
6816 if (GET_MODE_SIZE (value_mode
) != GET_MODE_SIZE (cmp_op_mode
)
6817 || GET_MODE_NUNITS (value_mode
) != GET_MODE_NUNITS (cmp_op_mode
)
6818 || get_vcond_icode (TYPE_MODE (value_type
), TYPE_MODE (cmp_op_type
),
6819 TYPE_UNSIGNED (cmp_op_type
)) == CODE_FOR_nothing
)
6824 /* Generate insns for a VEC_COND_EXPR, given its TYPE and its
6828 expand_vec_cond_expr (tree vec_cond_type
, tree op0
, tree op1
, tree op2
,
6831 struct expand_operand ops
[6];
6832 enum insn_code icode
;
6833 rtx comparison
, rtx_op1
, rtx_op2
;
6834 enum machine_mode mode
= TYPE_MODE (vec_cond_type
);
6835 enum machine_mode cmp_op_mode
;
6838 enum tree_code tcode
;
6840 if (COMPARISON_CLASS_P (op0
))
6842 op0a
= TREE_OPERAND (op0
, 0);
6843 op0b
= TREE_OPERAND (op0
, 1);
6844 tcode
= TREE_CODE (op0
);
6849 gcc_assert (!TYPE_UNSIGNED (TREE_TYPE (op0
)));
6851 op0b
= build_zero_cst (TREE_TYPE (op0
));
6854 unsignedp
= TYPE_UNSIGNED (TREE_TYPE (op0a
));
6855 cmp_op_mode
= TYPE_MODE (TREE_TYPE (op0a
));
6858 gcc_assert (GET_MODE_SIZE (mode
) == GET_MODE_SIZE (cmp_op_mode
)
6859 && GET_MODE_NUNITS (mode
) == GET_MODE_NUNITS (cmp_op_mode
));
6861 icode
= get_vcond_icode (mode
, cmp_op_mode
, unsignedp
);
6862 if (icode
== CODE_FOR_nothing
)
6865 comparison
= vector_compare_rtx (tcode
, op0a
, op0b
, unsignedp
, icode
);
6866 rtx_op1
= expand_normal (op1
);
6867 rtx_op2
= expand_normal (op2
);
6869 create_output_operand (&ops
[0], target
, mode
);
6870 create_input_operand (&ops
[1], rtx_op1
, mode
);
6871 create_input_operand (&ops
[2], rtx_op2
, mode
);
6872 create_fixed_operand (&ops
[3], comparison
);
6873 create_fixed_operand (&ops
[4], XEXP (comparison
, 0));
6874 create_fixed_operand (&ops
[5], XEXP (comparison
, 1));
6875 expand_insn (icode
, 6, ops
);
6876 return ops
[0].value
;
6879 /* Return non-zero if a highpart multiply is supported of can be synthisized.
6880 For the benefit of expand_mult_highpart, the return value is 1 for direct,
6881 2 for even/odd widening, and 3 for hi/lo widening. */
6884 can_mult_highpart_p (enum machine_mode mode
, bool uns_p
)
6890 op
= uns_p
? umul_highpart_optab
: smul_highpart_optab
;
6891 if (optab_handler (op
, mode
) != CODE_FOR_nothing
)
6894 /* If the mode is an integral vector, synth from widening operations. */
6895 if (GET_MODE_CLASS (mode
) != MODE_VECTOR_INT
)
6898 nunits
= GET_MODE_NUNITS (mode
);
6899 sel
= XALLOCAVEC (unsigned char, nunits
);
6901 op
= uns_p
? vec_widen_umult_even_optab
: vec_widen_smult_even_optab
;
6902 if (optab_handler (op
, mode
) != CODE_FOR_nothing
)
6904 op
= uns_p
? vec_widen_umult_odd_optab
: vec_widen_smult_odd_optab
;
6905 if (optab_handler (op
, mode
) != CODE_FOR_nothing
)
6907 for (i
= 0; i
< nunits
; ++i
)
6908 sel
[i
] = !BYTES_BIG_ENDIAN
+ (i
& ~1) + ((i
& 1) ? nunits
: 0);
6909 if (can_vec_perm_p (mode
, false, sel
))
6914 op
= uns_p
? vec_widen_umult_hi_optab
: vec_widen_smult_hi_optab
;
6915 if (optab_handler (op
, mode
) != CODE_FOR_nothing
)
6917 op
= uns_p
? vec_widen_umult_lo_optab
: vec_widen_smult_lo_optab
;
6918 if (optab_handler (op
, mode
) != CODE_FOR_nothing
)
6920 for (i
= 0; i
< nunits
; ++i
)
6921 sel
[i
] = 2 * i
+ (BYTES_BIG_ENDIAN
? 0 : 1);
6922 if (can_vec_perm_p (mode
, false, sel
))
6930 /* Expand a highpart multiply. */
6933 expand_mult_highpart (enum machine_mode mode
, rtx op0
, rtx op1
,
6934 rtx target
, bool uns_p
)
6936 struct expand_operand eops
[3];
6937 enum insn_code icode
;
6938 int method
, i
, nunits
;
6939 enum machine_mode wmode
;
6944 method
= can_mult_highpart_p (mode
, uns_p
);
6950 tab1
= uns_p
? umul_highpart_optab
: smul_highpart_optab
;
6951 return expand_binop (mode
, tab1
, op0
, op1
, target
, uns_p
,
6954 tab1
= uns_p
? vec_widen_umult_even_optab
: vec_widen_smult_even_optab
;
6955 tab2
= uns_p
? vec_widen_umult_odd_optab
: vec_widen_smult_odd_optab
;
6958 tab1
= uns_p
? vec_widen_umult_lo_optab
: vec_widen_smult_lo_optab
;
6959 tab2
= uns_p
? vec_widen_umult_hi_optab
: vec_widen_smult_hi_optab
;
6960 if (BYTES_BIG_ENDIAN
)
6971 icode
= optab_handler (tab1
, mode
);
6972 nunits
= GET_MODE_NUNITS (mode
);
6973 wmode
= insn_data
[icode
].operand
[0].mode
;
6974 gcc_checking_assert (2 * GET_MODE_NUNITS (wmode
) == nunits
);
6975 gcc_checking_assert (GET_MODE_SIZE (wmode
) == GET_MODE_SIZE (mode
));
6977 create_output_operand (&eops
[0], gen_reg_rtx (wmode
), wmode
);
6978 create_input_operand (&eops
[1], op0
, mode
);
6979 create_input_operand (&eops
[2], op1
, mode
);
6980 expand_insn (icode
, 3, eops
);
6981 m1
= gen_lowpart (mode
, eops
[0].value
);
6983 create_output_operand (&eops
[0], gen_reg_rtx (wmode
), wmode
);
6984 create_input_operand (&eops
[1], op0
, mode
);
6985 create_input_operand (&eops
[2], op1
, mode
);
6986 expand_insn (optab_handler (tab2
, mode
), 3, eops
);
6987 m2
= gen_lowpart (mode
, eops
[0].value
);
6989 v
= rtvec_alloc (nunits
);
6992 for (i
= 0; i
< nunits
; ++i
)
6993 RTVEC_ELT (v
, i
) = GEN_INT (!BYTES_BIG_ENDIAN
+ (i
& ~1)
6994 + ((i
& 1) ? nunits
: 0));
6998 for (i
= 0; i
< nunits
; ++i
)
6999 RTVEC_ELT (v
, i
) = GEN_INT (2 * i
+ (BYTES_BIG_ENDIAN
? 0 : 1));
7001 perm
= gen_rtx_CONST_VECTOR (mode
, v
);
7003 return expand_vec_perm (mode
, m1
, m2
, perm
, target
);
7006 /* Return true if target supports vector masked load/store for mode. */
7008 can_vec_mask_load_store_p (enum machine_mode mode
, bool is_load
)
7010 optab op
= is_load
? maskload_optab
: maskstore_optab
;
7011 enum machine_mode vmode
;
7012 unsigned int vector_sizes
;
7014 /* If mode is vector mode, check it directly. */
7015 if (VECTOR_MODE_P (mode
))
7016 return optab_handler (op
, mode
) != CODE_FOR_nothing
;
7018 /* Otherwise, return true if there is some vector mode with
7019 the mask load/store supported. */
7021 /* See if there is any chance the mask load or store might be
7022 vectorized. If not, punt. */
7023 vmode
= targetm
.vectorize
.preferred_simd_mode (mode
);
7024 if (!VECTOR_MODE_P (vmode
))
7027 if (optab_handler (op
, vmode
) != CODE_FOR_nothing
)
7030 vector_sizes
= targetm
.vectorize
.autovectorize_vector_sizes ();
7031 while (vector_sizes
!= 0)
7033 unsigned int cur
= 1 << floor_log2 (vector_sizes
);
7034 vector_sizes
&= ~cur
;
7035 if (cur
<= GET_MODE_SIZE (mode
))
7037 vmode
= mode_for_vector (mode
, cur
/ GET_MODE_SIZE (mode
));
7038 if (VECTOR_MODE_P (vmode
)
7039 && optab_handler (op
, vmode
) != CODE_FOR_nothing
)
7045 /* Return true if there is a compare_and_swap pattern. */
7048 can_compare_and_swap_p (enum machine_mode mode
, bool allow_libcall
)
7050 enum insn_code icode
;
7052 /* Check for __atomic_compare_and_swap. */
7053 icode
= direct_optab_handler (atomic_compare_and_swap_optab
, mode
);
7054 if (icode
!= CODE_FOR_nothing
)
7057 /* Check for __sync_compare_and_swap. */
7058 icode
= optab_handler (sync_compare_and_swap_optab
, mode
);
7059 if (icode
!= CODE_FOR_nothing
)
7061 if (allow_libcall
&& optab_libfunc (sync_compare_and_swap_optab
, mode
))
7064 /* No inline compare and swap. */
7068 /* Return true if an atomic exchange can be performed. */
7071 can_atomic_exchange_p (enum machine_mode mode
, bool allow_libcall
)
7073 enum insn_code icode
;
7075 /* Check for __atomic_exchange. */
7076 icode
= direct_optab_handler (atomic_exchange_optab
, mode
);
7077 if (icode
!= CODE_FOR_nothing
)
7080 /* Don't check __sync_test_and_set, as on some platforms that
7081 has reduced functionality. Targets that really do support
7082 a proper exchange should simply be updated to the __atomics. */
7084 return can_compare_and_swap_p (mode
, allow_libcall
);
7088 /* Helper function to find the MODE_CC set in a sync_compare_and_swap
7092 find_cc_set (rtx x
, const_rtx pat
, void *data
)
7094 if (REG_P (x
) && GET_MODE_CLASS (GET_MODE (x
)) == MODE_CC
7095 && GET_CODE (pat
) == SET
)
7097 rtx
*p_cc_reg
= (rtx
*) data
;
7098 gcc_assert (!*p_cc_reg
);
7103 /* This is a helper function for the other atomic operations. This function
7104 emits a loop that contains SEQ that iterates until a compare-and-swap
7105 operation at the end succeeds. MEM is the memory to be modified. SEQ is
7106 a set of instructions that takes a value from OLD_REG as an input and
7107 produces a value in NEW_REG as an output. Before SEQ, OLD_REG will be
7108 set to the current contents of MEM. After SEQ, a compare-and-swap will
7109 attempt to update MEM with NEW_REG. The function returns true when the
7110 loop was generated successfully. */
7113 expand_compare_and_swap_loop (rtx mem
, rtx old_reg
, rtx new_reg
, rtx seq
)
7115 enum machine_mode mode
= GET_MODE (mem
);
7116 rtx_code_label
*label
;
7117 rtx cmp_reg
, success
, oldval
;
7119 /* The loop we want to generate looks like
7125 (success, cmp_reg) = compare-and-swap(mem, old_reg, new_reg)
7129 Note that we only do the plain load from memory once. Subsequent
7130 iterations use the value loaded by the compare-and-swap pattern. */
7132 label
= gen_label_rtx ();
7133 cmp_reg
= gen_reg_rtx (mode
);
7135 emit_move_insn (cmp_reg
, mem
);
7137 emit_move_insn (old_reg
, cmp_reg
);
7143 if (!expand_atomic_compare_and_swap (&success
, &oldval
, mem
, old_reg
,
7144 new_reg
, false, MEMMODEL_SEQ_CST
,
7148 if (oldval
!= cmp_reg
)
7149 emit_move_insn (cmp_reg
, oldval
);
7151 /* Mark this jump predicted not taken. */
7152 emit_cmp_and_jump_insns (success
, const0_rtx
, EQ
, const0_rtx
,
7153 GET_MODE (success
), 1, label
, 0);
7158 /* This function tries to emit an atomic_exchange intruction. VAL is written
7159 to *MEM using memory model MODEL. The previous contents of *MEM are returned,
7160 using TARGET if possible. */
7163 maybe_emit_atomic_exchange (rtx target
, rtx mem
, rtx val
, enum memmodel model
)
7165 enum machine_mode mode
= GET_MODE (mem
);
7166 enum insn_code icode
;
7168 /* If the target supports the exchange directly, great. */
7169 icode
= direct_optab_handler (atomic_exchange_optab
, mode
);
7170 if (icode
!= CODE_FOR_nothing
)
7172 struct expand_operand ops
[4];
7174 create_output_operand (&ops
[0], target
, mode
);
7175 create_fixed_operand (&ops
[1], mem
);
7176 create_input_operand (&ops
[2], val
, mode
);
7177 create_integer_operand (&ops
[3], model
);
7178 if (maybe_expand_insn (icode
, 4, ops
))
7179 return ops
[0].value
;
7185 /* This function tries to implement an atomic exchange operation using
7186 __sync_lock_test_and_set. VAL is written to *MEM using memory model MODEL.
7187 The previous contents of *MEM are returned, using TARGET if possible.
7188 Since this instructionn is an acquire barrier only, stronger memory
7189 models may require additional barriers to be emitted. */
7192 maybe_emit_sync_lock_test_and_set (rtx target
, rtx mem
, rtx val
,
7193 enum memmodel model
)
7195 enum machine_mode mode
= GET_MODE (mem
);
7196 enum insn_code icode
;
7197 rtx_insn
*last_insn
= get_last_insn ();
7199 icode
= optab_handler (sync_lock_test_and_set_optab
, mode
);
7201 /* Legacy sync_lock_test_and_set is an acquire barrier. If the pattern
7202 exists, and the memory model is stronger than acquire, add a release
7203 barrier before the instruction. */
7205 if ((model
& MEMMODEL_MASK
) == MEMMODEL_SEQ_CST
7206 || (model
& MEMMODEL_MASK
) == MEMMODEL_RELEASE
7207 || (model
& MEMMODEL_MASK
) == MEMMODEL_ACQ_REL
)
7208 expand_mem_thread_fence (model
);
7210 if (icode
!= CODE_FOR_nothing
)
7212 struct expand_operand ops
[3];
7213 create_output_operand (&ops
[0], target
, mode
);
7214 create_fixed_operand (&ops
[1], mem
);
7215 create_input_operand (&ops
[2], val
, mode
);
7216 if (maybe_expand_insn (icode
, 3, ops
))
7217 return ops
[0].value
;
7220 /* If an external test-and-set libcall is provided, use that instead of
7221 any external compare-and-swap that we might get from the compare-and-
7222 swap-loop expansion later. */
7223 if (!can_compare_and_swap_p (mode
, false))
7225 rtx libfunc
= optab_libfunc (sync_lock_test_and_set_optab
, mode
);
7226 if (libfunc
!= NULL
)
7230 addr
= convert_memory_address (ptr_mode
, XEXP (mem
, 0));
7231 return emit_library_call_value (libfunc
, NULL_RTX
, LCT_NORMAL
,
7232 mode
, 2, addr
, ptr_mode
,
7237 /* If the test_and_set can't be emitted, eliminate any barrier that might
7238 have been emitted. */
7239 delete_insns_since (last_insn
);
7243 /* This function tries to implement an atomic exchange operation using a
7244 compare_and_swap loop. VAL is written to *MEM. The previous contents of
7245 *MEM are returned, using TARGET if possible. No memory model is required
7246 since a compare_and_swap loop is seq-cst. */
7249 maybe_emit_compare_and_swap_exchange_loop (rtx target
, rtx mem
, rtx val
)
7251 enum machine_mode mode
= GET_MODE (mem
);
7253 if (can_compare_and_swap_p (mode
, true))
7255 if (!target
|| !register_operand (target
, mode
))
7256 target
= gen_reg_rtx (mode
);
7257 if (expand_compare_and_swap_loop (mem
, target
, val
, NULL_RTX
))
7264 /* This function tries to implement an atomic test-and-set operation
7265 using the atomic_test_and_set instruction pattern. A boolean value
7266 is returned from the operation, using TARGET if possible. */
7268 #ifndef HAVE_atomic_test_and_set
7269 #define HAVE_atomic_test_and_set 0
7270 #define CODE_FOR_atomic_test_and_set CODE_FOR_nothing
7274 maybe_emit_atomic_test_and_set (rtx target
, rtx mem
, enum memmodel model
)
7276 enum machine_mode pat_bool_mode
;
7277 struct expand_operand ops
[3];
7279 if (!HAVE_atomic_test_and_set
)
7282 /* While we always get QImode from __atomic_test_and_set, we get
7283 other memory modes from __sync_lock_test_and_set. Note that we
7284 use no endian adjustment here. This matches the 4.6 behavior
7285 in the Sparc backend. */
7287 (insn_data
[CODE_FOR_atomic_test_and_set
].operand
[1].mode
== QImode
);
7288 if (GET_MODE (mem
) != QImode
)
7289 mem
= adjust_address_nv (mem
, QImode
, 0);
7291 pat_bool_mode
= insn_data
[CODE_FOR_atomic_test_and_set
].operand
[0].mode
;
7292 create_output_operand (&ops
[0], target
, pat_bool_mode
);
7293 create_fixed_operand (&ops
[1], mem
);
7294 create_integer_operand (&ops
[2], model
);
7296 if (maybe_expand_insn (CODE_FOR_atomic_test_and_set
, 3, ops
))
7297 return ops
[0].value
;
7301 /* This function expands the legacy _sync_lock test_and_set operation which is
7302 generally an atomic exchange. Some limited targets only allow the
7303 constant 1 to be stored. This is an ACQUIRE operation.
7305 TARGET is an optional place to stick the return value.
7306 MEM is where VAL is stored. */
7309 expand_sync_lock_test_and_set (rtx target
, rtx mem
, rtx val
)
7313 /* Try an atomic_exchange first. */
7314 ret
= maybe_emit_atomic_exchange (target
, mem
, val
, MEMMODEL_ACQUIRE
);
7318 ret
= maybe_emit_sync_lock_test_and_set (target
, mem
, val
, MEMMODEL_ACQUIRE
);
7322 ret
= maybe_emit_compare_and_swap_exchange_loop (target
, mem
, val
);
7326 /* If there are no other options, try atomic_test_and_set if the value
7327 being stored is 1. */
7328 if (val
== const1_rtx
)
7329 ret
= maybe_emit_atomic_test_and_set (target
, mem
, MEMMODEL_ACQUIRE
);
7334 /* This function expands the atomic test_and_set operation:
7335 atomically store a boolean TRUE into MEM and return the previous value.
7337 MEMMODEL is the memory model variant to use.
7338 TARGET is an optional place to stick the return value. */
7341 expand_atomic_test_and_set (rtx target
, rtx mem
, enum memmodel model
)
7343 enum machine_mode mode
= GET_MODE (mem
);
7344 rtx ret
, trueval
, subtarget
;
7346 ret
= maybe_emit_atomic_test_and_set (target
, mem
, model
);
7350 /* Be binary compatible with non-default settings of trueval, and different
7351 cpu revisions. E.g. one revision may have atomic-test-and-set, but
7352 another only has atomic-exchange. */
7353 if (targetm
.atomic_test_and_set_trueval
== 1)
7355 trueval
= const1_rtx
;
7356 subtarget
= target
? target
: gen_reg_rtx (mode
);
7360 trueval
= gen_int_mode (targetm
.atomic_test_and_set_trueval
, mode
);
7361 subtarget
= gen_reg_rtx (mode
);
7364 /* Try the atomic-exchange optab... */
7365 ret
= maybe_emit_atomic_exchange (subtarget
, mem
, trueval
, model
);
7367 /* ... then an atomic-compare-and-swap loop ... */
7369 ret
= maybe_emit_compare_and_swap_exchange_loop (subtarget
, mem
, trueval
);
7371 /* ... before trying the vaguely defined legacy lock_test_and_set. */
7373 ret
= maybe_emit_sync_lock_test_and_set (subtarget
, mem
, trueval
, model
);
7375 /* Recall that the legacy lock_test_and_set optab was allowed to do magic
7376 things with the value 1. Thus we try again without trueval. */
7377 if (!ret
&& targetm
.atomic_test_and_set_trueval
!= 1)
7378 ret
= maybe_emit_sync_lock_test_and_set (subtarget
, mem
, const1_rtx
, model
);
7380 /* Failing all else, assume a single threaded environment and simply
7381 perform the operation. */
7384 /* If the result is ignored skip the move to target. */
7385 if (subtarget
!= const0_rtx
)
7386 emit_move_insn (subtarget
, mem
);
7388 emit_move_insn (mem
, trueval
);
7392 /* Recall that have to return a boolean value; rectify if trueval
7393 is not exactly one. */
7394 if (targetm
.atomic_test_and_set_trueval
!= 1)
7395 ret
= emit_store_flag_force (target
, NE
, ret
, const0_rtx
, mode
, 0, 1);
7400 /* This function expands the atomic exchange operation:
7401 atomically store VAL in MEM and return the previous value in MEM.
7403 MEMMODEL is the memory model variant to use.
7404 TARGET is an optional place to stick the return value. */
7407 expand_atomic_exchange (rtx target
, rtx mem
, rtx val
, enum memmodel model
)
7411 ret
= maybe_emit_atomic_exchange (target
, mem
, val
, model
);
7413 /* Next try a compare-and-swap loop for the exchange. */
7415 ret
= maybe_emit_compare_and_swap_exchange_loop (target
, mem
, val
);
7420 /* This function expands the atomic compare exchange operation:
7422 *PTARGET_BOOL is an optional place to store the boolean success/failure.
7423 *PTARGET_OVAL is an optional place to store the old value from memory.
7424 Both target parameters may be NULL to indicate that we do not care about
7425 that return value. Both target parameters are updated on success to
7426 the actual location of the corresponding result.
7428 MEMMODEL is the memory model variant to use.
7430 The return value of the function is true for success. */
7433 expand_atomic_compare_and_swap (rtx
*ptarget_bool
, rtx
*ptarget_oval
,
7434 rtx mem
, rtx expected
, rtx desired
,
7435 bool is_weak
, enum memmodel succ_model
,
7436 enum memmodel fail_model
)
7438 enum machine_mode mode
= GET_MODE (mem
);
7439 struct expand_operand ops
[8];
7440 enum insn_code icode
;
7441 rtx target_oval
, target_bool
= NULL_RTX
;
7444 /* Load expected into a register for the compare and swap. */
7445 if (MEM_P (expected
))
7446 expected
= copy_to_reg (expected
);
7448 /* Make sure we always have some place to put the return oldval.
7449 Further, make sure that place is distinct from the input expected,
7450 just in case we need that path down below. */
7451 if (ptarget_oval
== NULL
7452 || (target_oval
= *ptarget_oval
) == NULL
7453 || reg_overlap_mentioned_p (expected
, target_oval
))
7454 target_oval
= gen_reg_rtx (mode
);
7456 icode
= direct_optab_handler (atomic_compare_and_swap_optab
, mode
);
7457 if (icode
!= CODE_FOR_nothing
)
7459 enum machine_mode bool_mode
= insn_data
[icode
].operand
[0].mode
;
7461 /* Make sure we always have a place for the bool operand. */
7462 if (ptarget_bool
== NULL
7463 || (target_bool
= *ptarget_bool
) == NULL
7464 || GET_MODE (target_bool
) != bool_mode
)
7465 target_bool
= gen_reg_rtx (bool_mode
);
7467 /* Emit the compare_and_swap. */
7468 create_output_operand (&ops
[0], target_bool
, bool_mode
);
7469 create_output_operand (&ops
[1], target_oval
, mode
);
7470 create_fixed_operand (&ops
[2], mem
);
7471 create_input_operand (&ops
[3], expected
, mode
);
7472 create_input_operand (&ops
[4], desired
, mode
);
7473 create_integer_operand (&ops
[5], is_weak
);
7474 create_integer_operand (&ops
[6], succ_model
);
7475 create_integer_operand (&ops
[7], fail_model
);
7476 if (maybe_expand_insn (icode
, 8, ops
))
7478 /* Return success/failure. */
7479 target_bool
= ops
[0].value
;
7480 target_oval
= ops
[1].value
;
7485 /* Otherwise fall back to the original __sync_val_compare_and_swap
7486 which is always seq-cst. */
7487 icode
= optab_handler (sync_compare_and_swap_optab
, mode
);
7488 if (icode
!= CODE_FOR_nothing
)
7492 create_output_operand (&ops
[0], target_oval
, mode
);
7493 create_fixed_operand (&ops
[1], mem
);
7494 create_input_operand (&ops
[2], expected
, mode
);
7495 create_input_operand (&ops
[3], desired
, mode
);
7496 if (!maybe_expand_insn (icode
, 4, ops
))
7499 target_oval
= ops
[0].value
;
7501 /* If the caller isn't interested in the boolean return value,
7502 skip the computation of it. */
7503 if (ptarget_bool
== NULL
)
7506 /* Otherwise, work out if the compare-and-swap succeeded. */
7508 if (have_insn_for (COMPARE
, CCmode
))
7509 note_stores (PATTERN (get_last_insn ()), find_cc_set
, &cc_reg
);
7512 target_bool
= emit_store_flag_force (target_bool
, EQ
, cc_reg
,
7513 const0_rtx
, VOIDmode
, 0, 1);
7516 goto success_bool_from_val
;
7519 /* Also check for library support for __sync_val_compare_and_swap. */
7520 libfunc
= optab_libfunc (sync_compare_and_swap_optab
, mode
);
7521 if (libfunc
!= NULL
)
7523 rtx addr
= convert_memory_address (ptr_mode
, XEXP (mem
, 0));
7524 target_oval
= emit_library_call_value (libfunc
, NULL_RTX
, LCT_NORMAL
,
7525 mode
, 3, addr
, ptr_mode
,
7526 expected
, mode
, desired
, mode
);
7528 /* Compute the boolean return value only if requested. */
7530 goto success_bool_from_val
;
7538 success_bool_from_val
:
7539 target_bool
= emit_store_flag_force (target_bool
, EQ
, target_oval
,
7540 expected
, VOIDmode
, 1, 1);
7542 /* Make sure that the oval output winds up where the caller asked. */
7544 *ptarget_oval
= target_oval
;
7546 *ptarget_bool
= target_bool
;
7550 /* Generate asm volatile("" : : : "memory") as the memory barrier. */
7553 expand_asm_memory_barrier (void)
7557 asm_op
= gen_rtx_ASM_OPERANDS (VOIDmode
, empty_string
, empty_string
, 0,
7558 rtvec_alloc (0), rtvec_alloc (0),
7559 rtvec_alloc (0), UNKNOWN_LOCATION
);
7560 MEM_VOLATILE_P (asm_op
) = 1;
7562 clob
= gen_rtx_SCRATCH (VOIDmode
);
7563 clob
= gen_rtx_MEM (BLKmode
, clob
);
7564 clob
= gen_rtx_CLOBBER (VOIDmode
, clob
);
7566 emit_insn (gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, asm_op
, clob
)));
7569 /* This routine will either emit the mem_thread_fence pattern or issue a
7570 sync_synchronize to generate a fence for memory model MEMMODEL. */
7572 #ifndef HAVE_mem_thread_fence
7573 # define HAVE_mem_thread_fence 0
7574 # define gen_mem_thread_fence(x) (gcc_unreachable (), NULL_RTX)
7576 #ifndef HAVE_memory_barrier
7577 # define HAVE_memory_barrier 0
7578 # define gen_memory_barrier() (gcc_unreachable (), NULL_RTX)
7582 expand_mem_thread_fence (enum memmodel model
)
7584 if (HAVE_mem_thread_fence
)
7585 emit_insn (gen_mem_thread_fence (GEN_INT (model
)));
7586 else if ((model
& MEMMODEL_MASK
) != MEMMODEL_RELAXED
)
7588 if (HAVE_memory_barrier
)
7589 emit_insn (gen_memory_barrier ());
7590 else if (synchronize_libfunc
!= NULL_RTX
)
7591 emit_library_call (synchronize_libfunc
, LCT_NORMAL
, VOIDmode
, 0);
7593 expand_asm_memory_barrier ();
7597 /* This routine will either emit the mem_signal_fence pattern or issue a
7598 sync_synchronize to generate a fence for memory model MEMMODEL. */
7600 #ifndef HAVE_mem_signal_fence
7601 # define HAVE_mem_signal_fence 0
7602 # define gen_mem_signal_fence(x) (gcc_unreachable (), NULL_RTX)
7606 expand_mem_signal_fence (enum memmodel model
)
7608 if (HAVE_mem_signal_fence
)
7609 emit_insn (gen_mem_signal_fence (GEN_INT (model
)));
7610 else if ((model
& MEMMODEL_MASK
) != MEMMODEL_RELAXED
)
7612 /* By default targets are coherent between a thread and the signal
7613 handler running on the same thread. Thus this really becomes a
7614 compiler barrier, in that stores must not be sunk past
7615 (or raised above) a given point. */
7616 expand_asm_memory_barrier ();
7620 /* This function expands the atomic load operation:
7621 return the atomically loaded value in MEM.
7623 MEMMODEL is the memory model variant to use.
7624 TARGET is an option place to stick the return value. */
7627 expand_atomic_load (rtx target
, rtx mem
, enum memmodel model
)
7629 enum machine_mode mode
= GET_MODE (mem
);
7630 enum insn_code icode
;
7632 /* If the target supports the load directly, great. */
7633 icode
= direct_optab_handler (atomic_load_optab
, mode
);
7634 if (icode
!= CODE_FOR_nothing
)
7636 struct expand_operand ops
[3];
7638 create_output_operand (&ops
[0], target
, mode
);
7639 create_fixed_operand (&ops
[1], mem
);
7640 create_integer_operand (&ops
[2], model
);
7641 if (maybe_expand_insn (icode
, 3, ops
))
7642 return ops
[0].value
;
7645 /* If the size of the object is greater than word size on this target,
7646 then we assume that a load will not be atomic. */
7647 if (GET_MODE_PRECISION (mode
) > BITS_PER_WORD
)
7649 /* Issue val = compare_and_swap (mem, 0, 0).
7650 This may cause the occasional harmless store of 0 when the value is
7651 already 0, but it seems to be OK according to the standards guys. */
7652 if (expand_atomic_compare_and_swap (NULL
, &target
, mem
, const0_rtx
,
7653 const0_rtx
, false, model
, model
))
7656 /* Otherwise there is no atomic load, leave the library call. */
7660 /* Otherwise assume loads are atomic, and emit the proper barriers. */
7661 if (!target
|| target
== const0_rtx
)
7662 target
= gen_reg_rtx (mode
);
7664 /* For SEQ_CST, emit a barrier before the load. */
7665 if ((model
& MEMMODEL_MASK
) == MEMMODEL_SEQ_CST
)
7666 expand_mem_thread_fence (model
);
7668 emit_move_insn (target
, mem
);
7670 /* Emit the appropriate barrier after the load. */
7671 expand_mem_thread_fence (model
);
7676 /* This function expands the atomic store operation:
7677 Atomically store VAL in MEM.
7678 MEMMODEL is the memory model variant to use.
7679 USE_RELEASE is true if __sync_lock_release can be used as a fall back.
7680 function returns const0_rtx if a pattern was emitted. */
7683 expand_atomic_store (rtx mem
, rtx val
, enum memmodel model
, bool use_release
)
7685 enum machine_mode mode
= GET_MODE (mem
);
7686 enum insn_code icode
;
7687 struct expand_operand ops
[3];
7689 /* If the target supports the store directly, great. */
7690 icode
= direct_optab_handler (atomic_store_optab
, mode
);
7691 if (icode
!= CODE_FOR_nothing
)
7693 create_fixed_operand (&ops
[0], mem
);
7694 create_input_operand (&ops
[1], val
, mode
);
7695 create_integer_operand (&ops
[2], model
);
7696 if (maybe_expand_insn (icode
, 3, ops
))
7700 /* If using __sync_lock_release is a viable alternative, try it. */
7703 icode
= direct_optab_handler (sync_lock_release_optab
, mode
);
7704 if (icode
!= CODE_FOR_nothing
)
7706 create_fixed_operand (&ops
[0], mem
);
7707 create_input_operand (&ops
[1], const0_rtx
, mode
);
7708 if (maybe_expand_insn (icode
, 2, ops
))
7710 /* lock_release is only a release barrier. */
7711 if ((model
& MEMMODEL_MASK
) == MEMMODEL_SEQ_CST
)
7712 expand_mem_thread_fence (model
);
7718 /* If the size of the object is greater than word size on this target,
7719 a default store will not be atomic, Try a mem_exchange and throw away
7720 the result. If that doesn't work, don't do anything. */
7721 if (GET_MODE_PRECISION (mode
) > BITS_PER_WORD
)
7723 rtx target
= maybe_emit_atomic_exchange (NULL_RTX
, mem
, val
, model
);
7725 target
= maybe_emit_compare_and_swap_exchange_loop (NULL_RTX
, mem
, val
);
7732 /* Otherwise assume stores are atomic, and emit the proper barriers. */
7733 expand_mem_thread_fence (model
);
7735 emit_move_insn (mem
, val
);
7737 /* For SEQ_CST, also emit a barrier after the store. */
7738 if ((model
& MEMMODEL_MASK
) == MEMMODEL_SEQ_CST
)
7739 expand_mem_thread_fence (model
);
7745 /* Structure containing the pointers and values required to process the
7746 various forms of the atomic_fetch_op and atomic_op_fetch builtins. */
7748 struct atomic_op_functions
7750 direct_optab mem_fetch_before
;
7751 direct_optab mem_fetch_after
;
7752 direct_optab mem_no_result
;
7755 direct_optab no_result
;
7756 enum rtx_code reverse_code
;
7760 /* Fill in structure pointed to by OP with the various optab entries for an
7761 operation of type CODE. */
7764 get_atomic_op_for_code (struct atomic_op_functions
*op
, enum rtx_code code
)
7766 gcc_assert (op
!= NULL
);
7768 /* If SWITCHABLE_TARGET is defined, then subtargets can be switched
7769 in the source code during compilation, and the optab entries are not
7770 computable until runtime. Fill in the values at runtime. */
7774 op
->mem_fetch_before
= atomic_fetch_add_optab
;
7775 op
->mem_fetch_after
= atomic_add_fetch_optab
;
7776 op
->mem_no_result
= atomic_add_optab
;
7777 op
->fetch_before
= sync_old_add_optab
;
7778 op
->fetch_after
= sync_new_add_optab
;
7779 op
->no_result
= sync_add_optab
;
7780 op
->reverse_code
= MINUS
;
7783 op
->mem_fetch_before
= atomic_fetch_sub_optab
;
7784 op
->mem_fetch_after
= atomic_sub_fetch_optab
;
7785 op
->mem_no_result
= atomic_sub_optab
;
7786 op
->fetch_before
= sync_old_sub_optab
;
7787 op
->fetch_after
= sync_new_sub_optab
;
7788 op
->no_result
= sync_sub_optab
;
7789 op
->reverse_code
= PLUS
;
7792 op
->mem_fetch_before
= atomic_fetch_xor_optab
;
7793 op
->mem_fetch_after
= atomic_xor_fetch_optab
;
7794 op
->mem_no_result
= atomic_xor_optab
;
7795 op
->fetch_before
= sync_old_xor_optab
;
7796 op
->fetch_after
= sync_new_xor_optab
;
7797 op
->no_result
= sync_xor_optab
;
7798 op
->reverse_code
= XOR
;
7801 op
->mem_fetch_before
= atomic_fetch_and_optab
;
7802 op
->mem_fetch_after
= atomic_and_fetch_optab
;
7803 op
->mem_no_result
= atomic_and_optab
;
7804 op
->fetch_before
= sync_old_and_optab
;
7805 op
->fetch_after
= sync_new_and_optab
;
7806 op
->no_result
= sync_and_optab
;
7807 op
->reverse_code
= UNKNOWN
;
7810 op
->mem_fetch_before
= atomic_fetch_or_optab
;
7811 op
->mem_fetch_after
= atomic_or_fetch_optab
;
7812 op
->mem_no_result
= atomic_or_optab
;
7813 op
->fetch_before
= sync_old_ior_optab
;
7814 op
->fetch_after
= sync_new_ior_optab
;
7815 op
->no_result
= sync_ior_optab
;
7816 op
->reverse_code
= UNKNOWN
;
7819 op
->mem_fetch_before
= atomic_fetch_nand_optab
;
7820 op
->mem_fetch_after
= atomic_nand_fetch_optab
;
7821 op
->mem_no_result
= atomic_nand_optab
;
7822 op
->fetch_before
= sync_old_nand_optab
;
7823 op
->fetch_after
= sync_new_nand_optab
;
7824 op
->no_result
= sync_nand_optab
;
7825 op
->reverse_code
= UNKNOWN
;
7832 /* See if there is a more optimal way to implement the operation "*MEM CODE VAL"
7833 using memory order MODEL. If AFTER is true the operation needs to return
7834 the value of *MEM after the operation, otherwise the previous value.
7835 TARGET is an optional place to place the result. The result is unused if
7837 Return the result if there is a better sequence, otherwise NULL_RTX. */
7840 maybe_optimize_fetch_op (rtx target
, rtx mem
, rtx val
, enum rtx_code code
,
7841 enum memmodel model
, bool after
)
7843 /* If the value is prefetched, or not used, it may be possible to replace
7844 the sequence with a native exchange operation. */
7845 if (!after
|| target
== const0_rtx
)
7847 /* fetch_and (&x, 0, m) can be replaced with exchange (&x, 0, m). */
7848 if (code
== AND
&& val
== const0_rtx
)
7850 if (target
== const0_rtx
)
7851 target
= gen_reg_rtx (GET_MODE (mem
));
7852 return maybe_emit_atomic_exchange (target
, mem
, val
, model
);
7855 /* fetch_or (&x, -1, m) can be replaced with exchange (&x, -1, m). */
7856 if (code
== IOR
&& val
== constm1_rtx
)
7858 if (target
== const0_rtx
)
7859 target
= gen_reg_rtx (GET_MODE (mem
));
7860 return maybe_emit_atomic_exchange (target
, mem
, val
, model
);
7867 /* Try to emit an instruction for a specific operation varaition.
7868 OPTAB contains the OP functions.
7869 TARGET is an optional place to return the result. const0_rtx means unused.
7870 MEM is the memory location to operate on.
7871 VAL is the value to use in the operation.
7872 USE_MEMMODEL is TRUE if the variation with a memory model should be tried.
7873 MODEL is the memory model, if used.
7874 AFTER is true if the returned result is the value after the operation. */
7877 maybe_emit_op (const struct atomic_op_functions
*optab
, rtx target
, rtx mem
,
7878 rtx val
, bool use_memmodel
, enum memmodel model
, bool after
)
7880 enum machine_mode mode
= GET_MODE (mem
);
7881 struct expand_operand ops
[4];
7882 enum insn_code icode
;
7886 /* Check to see if there is a result returned. */
7887 if (target
== const0_rtx
)
7891 icode
= direct_optab_handler (optab
->mem_no_result
, mode
);
7892 create_integer_operand (&ops
[2], model
);
7897 icode
= direct_optab_handler (optab
->no_result
, mode
);
7901 /* Otherwise, we need to generate a result. */
7906 icode
= direct_optab_handler (after
? optab
->mem_fetch_after
7907 : optab
->mem_fetch_before
, mode
);
7908 create_integer_operand (&ops
[3], model
);
7913 icode
= optab_handler (after
? optab
->fetch_after
7914 : optab
->fetch_before
, mode
);
7917 create_output_operand (&ops
[op_counter
++], target
, mode
);
7919 if (icode
== CODE_FOR_nothing
)
7922 create_fixed_operand (&ops
[op_counter
++], mem
);
7923 /* VAL may have been promoted to a wider mode. Shrink it if so. */
7924 create_convert_operand_to (&ops
[op_counter
++], val
, mode
, true);
7926 if (maybe_expand_insn (icode
, num_ops
, ops
))
7927 return (target
== const0_rtx
? const0_rtx
: ops
[0].value
);
7933 /* This function expands an atomic fetch_OP or OP_fetch operation:
7934 TARGET is an option place to stick the return value. const0_rtx indicates
7935 the result is unused.
7936 atomically fetch MEM, perform the operation with VAL and return it to MEM.
7937 CODE is the operation being performed (OP)
7938 MEMMODEL is the memory model variant to use.
7939 AFTER is true to return the result of the operation (OP_fetch).
7940 AFTER is false to return the value before the operation (fetch_OP).
7942 This function will *only* generate instructions if there is a direct
7943 optab. No compare and swap loops or libcalls will be generated. */
7946 expand_atomic_fetch_op_no_fallback (rtx target
, rtx mem
, rtx val
,
7947 enum rtx_code code
, enum memmodel model
,
7950 enum machine_mode mode
= GET_MODE (mem
);
7951 struct atomic_op_functions optab
;
7953 bool unused_result
= (target
== const0_rtx
);
7955 get_atomic_op_for_code (&optab
, code
);
7957 /* Check to see if there are any better instructions. */
7958 result
= maybe_optimize_fetch_op (target
, mem
, val
, code
, model
, after
);
7962 /* Check for the case where the result isn't used and try those patterns. */
7965 /* Try the memory model variant first. */
7966 result
= maybe_emit_op (&optab
, target
, mem
, val
, true, model
, true);
7970 /* Next try the old style withuot a memory model. */
7971 result
= maybe_emit_op (&optab
, target
, mem
, val
, false, model
, true);
7975 /* There is no no-result pattern, so try patterns with a result. */
7979 /* Try the __atomic version. */
7980 result
= maybe_emit_op (&optab
, target
, mem
, val
, true, model
, after
);
7984 /* Try the older __sync version. */
7985 result
= maybe_emit_op (&optab
, target
, mem
, val
, false, model
, after
);
7989 /* If the fetch value can be calculated from the other variation of fetch,
7990 try that operation. */
7991 if (after
|| unused_result
|| optab
.reverse_code
!= UNKNOWN
)
7993 /* Try the __atomic version, then the older __sync version. */
7994 result
= maybe_emit_op (&optab
, target
, mem
, val
, true, model
, !after
);
7996 result
= maybe_emit_op (&optab
, target
, mem
, val
, false, model
, !after
);
8000 /* If the result isn't used, no need to do compensation code. */
8004 /* Issue compensation code. Fetch_after == fetch_before OP val.
8005 Fetch_before == after REVERSE_OP val. */
8007 code
= optab
.reverse_code
;
8010 result
= expand_simple_binop (mode
, AND
, result
, val
, NULL_RTX
,
8011 true, OPTAB_LIB_WIDEN
);
8012 result
= expand_simple_unop (mode
, NOT
, result
, target
, true);
8015 result
= expand_simple_binop (mode
, code
, result
, val
, target
,
8016 true, OPTAB_LIB_WIDEN
);
8021 /* No direct opcode can be generated. */
8027 /* This function expands an atomic fetch_OP or OP_fetch operation:
8028 TARGET is an option place to stick the return value. const0_rtx indicates
8029 the result is unused.
8030 atomically fetch MEM, perform the operation with VAL and return it to MEM.
8031 CODE is the operation being performed (OP)
8032 MEMMODEL is the memory model variant to use.
8033 AFTER is true to return the result of the operation (OP_fetch).
8034 AFTER is false to return the value before the operation (fetch_OP). */
8036 expand_atomic_fetch_op (rtx target
, rtx mem
, rtx val
, enum rtx_code code
,
8037 enum memmodel model
, bool after
)
8039 enum machine_mode mode
= GET_MODE (mem
);
8041 bool unused_result
= (target
== const0_rtx
);
8043 result
= expand_atomic_fetch_op_no_fallback (target
, mem
, val
, code
, model
,
8049 /* Add/sub can be implemented by doing the reverse operation with -(val). */
8050 if (code
== PLUS
|| code
== MINUS
)
8053 enum rtx_code reverse
= (code
== PLUS
? MINUS
: PLUS
);
8056 tmp
= expand_simple_unop (mode
, NEG
, val
, NULL_RTX
, true);
8057 result
= expand_atomic_fetch_op_no_fallback (target
, mem
, tmp
, reverse
,
8061 /* PLUS worked so emit the insns and return. */
8068 /* PLUS did not work, so throw away the negation code and continue. */
8072 /* Try the __sync libcalls only if we can't do compare-and-swap inline. */
8073 if (!can_compare_and_swap_p (mode
, false))
8077 enum rtx_code orig_code
= code
;
8078 struct atomic_op_functions optab
;
8080 get_atomic_op_for_code (&optab
, code
);
8081 libfunc
= optab_libfunc (after
? optab
.fetch_after
8082 : optab
.fetch_before
, mode
);
8084 && (after
|| unused_result
|| optab
.reverse_code
!= UNKNOWN
))
8088 code
= optab
.reverse_code
;
8089 libfunc
= optab_libfunc (after
? optab
.fetch_before
8090 : optab
.fetch_after
, mode
);
8092 if (libfunc
!= NULL
)
8094 rtx addr
= convert_memory_address (ptr_mode
, XEXP (mem
, 0));
8095 result
= emit_library_call_value (libfunc
, NULL
, LCT_NORMAL
, mode
,
8096 2, addr
, ptr_mode
, val
, mode
);
8098 if (!unused_result
&& fixup
)
8099 result
= expand_simple_binop (mode
, code
, result
, val
, target
,
8100 true, OPTAB_LIB_WIDEN
);
8104 /* We need the original code for any further attempts. */
8108 /* If nothing else has succeeded, default to a compare and swap loop. */
8109 if (can_compare_and_swap_p (mode
, true))
8112 rtx t0
= gen_reg_rtx (mode
), t1
;
8116 /* If the result is used, get a register for it. */
8119 if (!target
|| !register_operand (target
, mode
))
8120 target
= gen_reg_rtx (mode
);
8121 /* If fetch_before, copy the value now. */
8123 emit_move_insn (target
, t0
);
8126 target
= const0_rtx
;
8131 t1
= expand_simple_binop (mode
, AND
, t1
, val
, NULL_RTX
,
8132 true, OPTAB_LIB_WIDEN
);
8133 t1
= expand_simple_unop (mode
, code
, t1
, NULL_RTX
, true);
8136 t1
= expand_simple_binop (mode
, code
, t1
, val
, NULL_RTX
, true,
8139 /* For after, copy the value now. */
8140 if (!unused_result
&& after
)
8141 emit_move_insn (target
, t1
);
8142 insn
= get_insns ();
8145 if (t1
!= NULL
&& expand_compare_and_swap_loop (mem
, t0
, t1
, insn
))
8152 /* Return true if OPERAND is suitable for operand number OPNO of
8153 instruction ICODE. */
8156 insn_operand_matches (enum insn_code icode
, unsigned int opno
, rtx operand
)
8158 return (!insn_data
[(int) icode
].operand
[opno
].predicate
8159 || (insn_data
[(int) icode
].operand
[opno
].predicate
8160 (operand
, insn_data
[(int) icode
].operand
[opno
].mode
)));
8163 /* TARGET is a target of a multiword operation that we are going to
8164 implement as a series of word-mode operations. Return true if
8165 TARGET is suitable for this purpose. */
8168 valid_multiword_target_p (rtx target
)
8170 enum machine_mode mode
;
8173 mode
= GET_MODE (target
);
8174 for (i
= 0; i
< GET_MODE_SIZE (mode
); i
+= UNITS_PER_WORD
)
8175 if (!validate_subreg (word_mode
, mode
, target
, i
))
8180 /* Like maybe_legitimize_operand, but do not change the code of the
8181 current rtx value. */
8184 maybe_legitimize_operand_same_code (enum insn_code icode
, unsigned int opno
,
8185 struct expand_operand
*op
)
8187 /* See if the operand matches in its current form. */
8188 if (insn_operand_matches (icode
, opno
, op
->value
))
8191 /* If the operand is a memory whose address has no side effects,
8192 try forcing the address into a non-virtual pseudo register.
8193 The check for side effects is important because copy_to_mode_reg
8194 cannot handle things like auto-modified addresses. */
8195 if (insn_data
[(int) icode
].operand
[opno
].allows_mem
&& MEM_P (op
->value
))
8200 addr
= XEXP (mem
, 0);
8201 if (!(REG_P (addr
) && REGNO (addr
) > LAST_VIRTUAL_REGISTER
)
8202 && !side_effects_p (addr
))
8205 enum machine_mode mode
;
8207 last
= get_last_insn ();
8208 mode
= get_address_mode (mem
);
8209 mem
= replace_equiv_address (mem
, copy_to_mode_reg (mode
, addr
));
8210 if (insn_operand_matches (icode
, opno
, mem
))
8215 delete_insns_since (last
);
8222 /* Try to make OP match operand OPNO of instruction ICODE. Return true
8223 on success, storing the new operand value back in OP. */
8226 maybe_legitimize_operand (enum insn_code icode
, unsigned int opno
,
8227 struct expand_operand
*op
)
8229 enum machine_mode mode
, imode
;
8230 bool old_volatile_ok
, result
;
8236 old_volatile_ok
= volatile_ok
;
8238 result
= maybe_legitimize_operand_same_code (icode
, opno
, op
);
8239 volatile_ok
= old_volatile_ok
;
8243 gcc_assert (mode
!= VOIDmode
);
8245 && op
->value
!= const0_rtx
8246 && GET_MODE (op
->value
) == mode
8247 && maybe_legitimize_operand_same_code (icode
, opno
, op
))
8250 op
->value
= gen_reg_rtx (mode
);
8255 gcc_assert (mode
!= VOIDmode
);
8256 gcc_assert (GET_MODE (op
->value
) == VOIDmode
8257 || GET_MODE (op
->value
) == mode
);
8258 if (maybe_legitimize_operand_same_code (icode
, opno
, op
))
8261 op
->value
= copy_to_mode_reg (mode
, op
->value
);
8264 case EXPAND_CONVERT_TO
:
8265 gcc_assert (mode
!= VOIDmode
);
8266 op
->value
= convert_to_mode (mode
, op
->value
, op
->unsigned_p
);
8269 case EXPAND_CONVERT_FROM
:
8270 if (GET_MODE (op
->value
) != VOIDmode
)
8271 mode
= GET_MODE (op
->value
);
8273 /* The caller must tell us what mode this value has. */
8274 gcc_assert (mode
!= VOIDmode
);
8276 imode
= insn_data
[(int) icode
].operand
[opno
].mode
;
8277 if (imode
!= VOIDmode
&& imode
!= mode
)
8279 op
->value
= convert_modes (imode
, mode
, op
->value
, op
->unsigned_p
);
8284 case EXPAND_ADDRESS
:
8285 gcc_assert (mode
!= VOIDmode
);
8286 op
->value
= convert_memory_address (mode
, op
->value
);
8289 case EXPAND_INTEGER
:
8290 mode
= insn_data
[(int) icode
].operand
[opno
].mode
;
8291 if (mode
!= VOIDmode
&& const_int_operand (op
->value
, mode
))
8295 return insn_operand_matches (icode
, opno
, op
->value
);
8298 /* Make OP describe an input operand that should have the same value
8299 as VALUE, after any mode conversion that the target might request.
8300 TYPE is the type of VALUE. */
8303 create_convert_operand_from_type (struct expand_operand
*op
,
8304 rtx value
, tree type
)
8306 create_convert_operand_from (op
, value
, TYPE_MODE (type
),
8307 TYPE_UNSIGNED (type
));
8310 /* Try to make operands [OPS, OPS + NOPS) match operands [OPNO, OPNO + NOPS)
8311 of instruction ICODE. Return true on success, leaving the new operand
8312 values in the OPS themselves. Emit no code on failure. */
8315 maybe_legitimize_operands (enum insn_code icode
, unsigned int opno
,
8316 unsigned int nops
, struct expand_operand
*ops
)
8321 last
= get_last_insn ();
8322 for (i
= 0; i
< nops
; i
++)
8323 if (!maybe_legitimize_operand (icode
, opno
+ i
, &ops
[i
]))
8325 delete_insns_since (last
);
8331 /* Try to generate instruction ICODE, using operands [OPS, OPS + NOPS)
8332 as its operands. Return the instruction pattern on success,
8333 and emit any necessary set-up code. Return null and emit no
8337 maybe_gen_insn (enum insn_code icode
, unsigned int nops
,
8338 struct expand_operand
*ops
)
8340 gcc_assert (nops
== (unsigned int) insn_data
[(int) icode
].n_generator_args
);
8341 if (!maybe_legitimize_operands (icode
, 0, nops
, ops
))
8347 return GEN_FCN (icode
) (ops
[0].value
);
8349 return GEN_FCN (icode
) (ops
[0].value
, ops
[1].value
);
8351 return GEN_FCN (icode
) (ops
[0].value
, ops
[1].value
, ops
[2].value
);
8353 return GEN_FCN (icode
) (ops
[0].value
, ops
[1].value
, ops
[2].value
,
8356 return GEN_FCN (icode
) (ops
[0].value
, ops
[1].value
, ops
[2].value
,
8357 ops
[3].value
, ops
[4].value
);
8359 return GEN_FCN (icode
) (ops
[0].value
, ops
[1].value
, ops
[2].value
,
8360 ops
[3].value
, ops
[4].value
, ops
[5].value
);
8362 return GEN_FCN (icode
) (ops
[0].value
, ops
[1].value
, ops
[2].value
,
8363 ops
[3].value
, ops
[4].value
, ops
[5].value
,
8366 return GEN_FCN (icode
) (ops
[0].value
, ops
[1].value
, ops
[2].value
,
8367 ops
[3].value
, ops
[4].value
, ops
[5].value
,
8368 ops
[6].value
, ops
[7].value
);
8370 return GEN_FCN (icode
) (ops
[0].value
, ops
[1].value
, ops
[2].value
,
8371 ops
[3].value
, ops
[4].value
, ops
[5].value
,
8372 ops
[6].value
, ops
[7].value
, ops
[8].value
);
8377 /* Try to emit instruction ICODE, using operands [OPS, OPS + NOPS)
8378 as its operands. Return true on success and emit no code on failure. */
8381 maybe_expand_insn (enum insn_code icode
, unsigned int nops
,
8382 struct expand_operand
*ops
)
8384 rtx pat
= maybe_gen_insn (icode
, nops
, ops
);
8393 /* Like maybe_expand_insn, but for jumps. */
8396 maybe_expand_jump_insn (enum insn_code icode
, unsigned int nops
,
8397 struct expand_operand
*ops
)
8399 rtx pat
= maybe_gen_insn (icode
, nops
, ops
);
8402 emit_jump_insn (pat
);
8408 /* Emit instruction ICODE, using operands [OPS, OPS + NOPS)
8412 expand_insn (enum insn_code icode
, unsigned int nops
,
8413 struct expand_operand
*ops
)
8415 if (!maybe_expand_insn (icode
, nops
, ops
))
8419 /* Like expand_insn, but for jumps. */
8422 expand_jump_insn (enum insn_code icode
, unsigned int nops
,
8423 struct expand_operand
*ops
)
8425 if (!maybe_expand_jump_insn (icode
, nops
, ops
))
8429 /* Reduce conditional compilation elsewhere. */
8432 #define CODE_FOR_insv CODE_FOR_nothing
8436 #define CODE_FOR_extv CODE_FOR_nothing
8439 #define HAVE_extzv 0
8440 #define CODE_FOR_extzv CODE_FOR_nothing
8443 /* Enumerates the possible types of structure operand to an
8445 enum extraction_type
{ ET_unaligned_mem
, ET_reg
};
8447 /* Check whether insv, extv or extzv pattern ICODE can be used for an
8448 insertion or extraction of type TYPE on a structure of mode MODE.
8449 Return true if so and fill in *INSN accordingly. STRUCT_OP is the
8450 operand number of the structure (the first sign_extract or zero_extract
8451 operand) and FIELD_OP is the operand number of the field (the other
8452 side of the set from the sign_extract or zero_extract). */
8455 get_traditional_extraction_insn (extraction_insn
*insn
,
8456 enum extraction_type type
,
8457 enum machine_mode mode
,
8458 enum insn_code icode
,
8459 int struct_op
, int field_op
)
8461 const struct insn_data_d
*data
= &insn_data
[icode
];
8463 enum machine_mode struct_mode
= data
->operand
[struct_op
].mode
;
8464 if (struct_mode
== VOIDmode
)
8465 struct_mode
= word_mode
;
8466 if (mode
!= struct_mode
)
8469 enum machine_mode field_mode
= data
->operand
[field_op
].mode
;
8470 if (field_mode
== VOIDmode
)
8471 field_mode
= word_mode
;
8473 enum machine_mode pos_mode
= data
->operand
[struct_op
+ 2].mode
;
8474 if (pos_mode
== VOIDmode
)
8475 pos_mode
= word_mode
;
8477 insn
->icode
= icode
;
8478 insn
->field_mode
= field_mode
;
8479 insn
->struct_mode
= (type
== ET_unaligned_mem
? byte_mode
: struct_mode
);
8480 insn
->pos_mode
= pos_mode
;
8484 /* Return true if an optab exists to perform an insertion or extraction
8485 of type TYPE in mode MODE. Describe the instruction in *INSN if so.
8487 REG_OPTAB is the optab to use for register structures and
8488 MISALIGN_OPTAB is the optab to use for misaligned memory structures.
8489 POS_OP is the operand number of the bit position. */
8492 get_optab_extraction_insn (struct extraction_insn
*insn
,
8493 enum extraction_type type
,
8494 enum machine_mode mode
, direct_optab reg_optab
,
8495 direct_optab misalign_optab
, int pos_op
)
8497 direct_optab optab
= (type
== ET_unaligned_mem
? misalign_optab
: reg_optab
);
8498 enum insn_code icode
= direct_optab_handler (optab
, mode
);
8499 if (icode
== CODE_FOR_nothing
)
8502 const struct insn_data_d
*data
= &insn_data
[icode
];
8504 insn
->icode
= icode
;
8505 insn
->field_mode
= mode
;
8506 insn
->struct_mode
= (type
== ET_unaligned_mem
? BLKmode
: mode
);
8507 insn
->pos_mode
= data
->operand
[pos_op
].mode
;
8508 if (insn
->pos_mode
== VOIDmode
)
8509 insn
->pos_mode
= word_mode
;
8513 /* Return true if an instruction exists to perform an insertion or
8514 extraction (PATTERN says which) of type TYPE in mode MODE.
8515 Describe the instruction in *INSN if so. */
8518 get_extraction_insn (extraction_insn
*insn
,
8519 enum extraction_pattern pattern
,
8520 enum extraction_type type
,
8521 enum machine_mode mode
)
8527 && get_traditional_extraction_insn (insn
, type
, mode
,
8528 CODE_FOR_insv
, 0, 3))
8530 return get_optab_extraction_insn (insn
, type
, mode
, insv_optab
,
8531 insvmisalign_optab
, 2);
8535 && get_traditional_extraction_insn (insn
, type
, mode
,
8536 CODE_FOR_extv
, 1, 0))
8538 return get_optab_extraction_insn (insn
, type
, mode
, extv_optab
,
8539 extvmisalign_optab
, 3);
8543 && get_traditional_extraction_insn (insn
, type
, mode
,
8544 CODE_FOR_extzv
, 1, 0))
8546 return get_optab_extraction_insn (insn
, type
, mode
, extzv_optab
,
8547 extzvmisalign_optab
, 3);
8554 /* Return true if an instruction exists to access a field of mode
8555 FIELDMODE in a structure that has STRUCT_BITS significant bits.
8556 Describe the "best" such instruction in *INSN if so. PATTERN and
8557 TYPE describe the type of insertion or extraction we want to perform.
8559 For an insertion, the number of significant structure bits includes
8560 all bits of the target. For an extraction, it need only include the
8561 most significant bit of the field. Larger widths are acceptable
8565 get_best_extraction_insn (extraction_insn
*insn
,
8566 enum extraction_pattern pattern
,
8567 enum extraction_type type
,
8568 unsigned HOST_WIDE_INT struct_bits
,
8569 enum machine_mode field_mode
)
8571 enum machine_mode mode
= smallest_mode_for_size (struct_bits
, MODE_INT
);
8572 while (mode
!= VOIDmode
)
8574 if (get_extraction_insn (insn
, pattern
, type
, mode
))
8576 while (mode
!= VOIDmode
8577 && GET_MODE_SIZE (mode
) <= GET_MODE_SIZE (field_mode
)
8578 && !TRULY_NOOP_TRUNCATION_MODES_P (insn
->field_mode
,
8581 get_extraction_insn (insn
, pattern
, type
, mode
);
8582 mode
= GET_MODE_WIDER_MODE (mode
);
8586 mode
= GET_MODE_WIDER_MODE (mode
);
8591 /* Return true if an instruction exists to access a field of mode
8592 FIELDMODE in a register structure that has STRUCT_BITS significant bits.
8593 Describe the "best" such instruction in *INSN if so. PATTERN describes
8594 the type of insertion or extraction we want to perform.
8596 For an insertion, the number of significant structure bits includes
8597 all bits of the target. For an extraction, it need only include the
8598 most significant bit of the field. Larger widths are acceptable
8602 get_best_reg_extraction_insn (extraction_insn
*insn
,
8603 enum extraction_pattern pattern
,
8604 unsigned HOST_WIDE_INT struct_bits
,
8605 enum machine_mode field_mode
)
8607 return get_best_extraction_insn (insn
, pattern
, ET_reg
, struct_bits
,
8611 /* Return true if an instruction exists to access a field of BITSIZE
8612 bits starting BITNUM bits into a memory structure. Describe the
8613 "best" such instruction in *INSN if so. PATTERN describes the type
8614 of insertion or extraction we want to perform and FIELDMODE is the
8615 natural mode of the extracted field.
8617 The instructions considered here only access bytes that overlap
8618 the bitfield; they do not touch any surrounding bytes. */
8621 get_best_mem_extraction_insn (extraction_insn
*insn
,
8622 enum extraction_pattern pattern
,
8623 HOST_WIDE_INT bitsize
, HOST_WIDE_INT bitnum
,
8624 enum machine_mode field_mode
)
8626 unsigned HOST_WIDE_INT struct_bits
= (bitnum
% BITS_PER_UNIT
8628 + BITS_PER_UNIT
- 1);
8629 struct_bits
-= struct_bits
% BITS_PER_UNIT
;
8630 return get_best_extraction_insn (insn
, pattern
, ET_unaligned_mem
,
8631 struct_bits
, field_mode
);
8634 #include "gt-optabs.h"