1 /* Perform simple optimizations to clean up the result of reload.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
24 #include "coretypes.h"
28 #include "hard-reg-set.h"
32 #include "insn-config.h"
38 #include "basic-block.h"
48 static int reload_cse_noop_set_p
PARAMS ((rtx
));
49 static void reload_cse_simplify
PARAMS ((rtx
, rtx
));
50 static void reload_cse_regs_1
PARAMS ((rtx
));
51 static int reload_cse_simplify_set
PARAMS ((rtx
, rtx
));
52 static int reload_cse_simplify_operands
PARAMS ((rtx
, rtx
));
54 static void reload_combine
PARAMS ((void));
55 static void reload_combine_note_use
PARAMS ((rtx
*, rtx
));
56 static void reload_combine_note_store
PARAMS ((rtx
, rtx
, void *));
58 static void reload_cse_move2add
PARAMS ((rtx
));
59 static void move2add_note_store
PARAMS ((rtx
, rtx
, void *));
61 /* Call cse / combine like post-reload optimization phases.
62 FIRST is the first instruction. */
64 reload_cse_regs (first
)
65 rtx first ATTRIBUTE_UNUSED
;
67 reload_cse_regs_1 (first
);
69 reload_cse_move2add (first
);
70 if (flag_expensive_optimizations
)
71 reload_cse_regs_1 (first
);
74 /* See whether a single set SET is a noop. */
76 reload_cse_noop_set_p (set
)
79 if (cselib_reg_set_mode (SET_DEST (set
)) != GET_MODE (SET_DEST (set
)))
82 return rtx_equal_for_cselib_p (SET_DEST (set
), SET_SRC (set
));
85 /* Try to simplify INSN. */
87 reload_cse_simplify (insn
, testreg
)
91 rtx body
= PATTERN (insn
);
93 if (GET_CODE (body
) == SET
)
97 /* Simplify even if we may think it is a no-op.
98 We may think a memory load of a value smaller than WORD_SIZE
99 is redundant because we haven't taken into account possible
100 implicit extension. reload_cse_simplify_set() will bring
101 this out, so it's safer to simplify before we delete. */
102 count
+= reload_cse_simplify_set (body
, insn
);
104 if (!count
&& reload_cse_noop_set_p (body
))
106 rtx value
= SET_DEST (body
);
108 && ! REG_FUNCTION_VALUE_P (value
))
110 delete_insn_and_edges (insn
);
115 apply_change_group ();
117 reload_cse_simplify_operands (insn
, testreg
);
119 else if (GET_CODE (body
) == PARALLEL
)
123 rtx value
= NULL_RTX
;
125 /* If every action in a PARALLEL is a noop, we can delete
126 the entire PARALLEL. */
127 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; --i
)
129 rtx part
= XVECEXP (body
, 0, i
);
130 if (GET_CODE (part
) == SET
)
132 if (! reload_cse_noop_set_p (part
))
134 if (REG_P (SET_DEST (part
))
135 && REG_FUNCTION_VALUE_P (SET_DEST (part
)))
139 value
= SET_DEST (part
);
142 else if (GET_CODE (part
) != CLOBBER
)
148 delete_insn_and_edges (insn
);
149 /* We're done with this insn. */
153 /* It's not a no-op, but we can try to simplify it. */
154 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; --i
)
155 if (GET_CODE (XVECEXP (body
, 0, i
)) == SET
)
156 count
+= reload_cse_simplify_set (XVECEXP (body
, 0, i
), insn
);
159 apply_change_group ();
161 reload_cse_simplify_operands (insn
, testreg
);
165 /* Do a very simple CSE pass over the hard registers.
167 This function detects no-op moves where we happened to assign two
168 different pseudo-registers to the same hard register, and then
169 copied one to the other. Reload will generate a useless
170 instruction copying a register to itself.
172 This function also detects cases where we load a value from memory
173 into two different registers, and (if memory is more expensive than
174 registers) changes it to simply copy the first register into the
177 Another optimization is performed that scans the operands of each
178 instruction to see whether the value is already available in a
179 hard register. It then replaces the operand with the hard register
180 if possible, much like an optional reload would. */
183 reload_cse_regs_1 (first
)
187 rtx testreg
= gen_rtx_REG (VOIDmode
, -1);
190 init_alias_analysis ();
192 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
195 reload_cse_simplify (insn
, testreg
);
197 cselib_process_insn (insn
);
201 end_alias_analysis ();
205 /* Try to simplify a single SET instruction. SET is the set pattern.
206 INSN is the instruction it came from.
207 This function only handles one case: if we set a register to a value
208 which is not a register, we try to find that value in some other register
209 and change the set into a register copy. */
212 reload_cse_simplify_set (set
, insn
)
219 enum reg_class dclass
;
222 struct elt_loc_list
*l
;
223 #ifdef LOAD_EXTEND_OP
224 enum rtx_code extend_op
= NIL
;
227 dreg
= true_regnum (SET_DEST (set
));
232 if (side_effects_p (src
) || true_regnum (src
) >= 0)
235 dclass
= REGNO_REG_CLASS (dreg
);
237 #ifdef LOAD_EXTEND_OP
238 /* When replacing a memory with a register, we need to honor assumptions
239 that combine made wrt the contents of sign bits. We'll do this by
240 generating an extend instruction instead of a reg->reg copy. Thus
241 the destination must be a register that we can widen. */
242 if (GET_CODE (src
) == MEM
243 && GET_MODE_BITSIZE (GET_MODE (src
)) < BITS_PER_WORD
244 && (extend_op
= LOAD_EXTEND_OP (GET_MODE (src
))) != NIL
245 && GET_CODE (SET_DEST (set
)) != REG
)
249 /* If memory loads are cheaper than register copies, don't change them. */
250 if (GET_CODE (src
) == MEM
)
251 old_cost
= MEMORY_MOVE_COST (GET_MODE (src
), dclass
, 1);
252 else if (CONSTANT_P (src
))
253 old_cost
= rtx_cost (src
, SET
);
254 else if (GET_CODE (src
) == REG
)
255 old_cost
= REGISTER_MOVE_COST (GET_MODE (src
),
256 REGNO_REG_CLASS (REGNO (src
)), dclass
);
259 old_cost
= rtx_cost (src
, SET
);
261 val
= cselib_lookup (src
, GET_MODE (SET_DEST (set
)), 0);
264 for (l
= val
->locs
; l
; l
= l
->next
)
266 rtx this_rtx
= l
->loc
;
269 if (CONSTANT_P (this_rtx
) && ! references_value_p (this_rtx
, 0))
271 #ifdef LOAD_EXTEND_OP
272 if (extend_op
!= NIL
)
274 HOST_WIDE_INT this_val
;
276 /* ??? I'm lazy and don't wish to handle CONST_DOUBLE. Other
277 constants, such as SYMBOL_REF, cannot be extended. */
278 if (GET_CODE (this_rtx
) != CONST_INT
)
281 this_val
= INTVAL (this_rtx
);
285 this_val
&= GET_MODE_MASK (GET_MODE (src
));
288 /* ??? In theory we're already extended. */
289 if (this_val
== trunc_int_for_mode (this_val
, GET_MODE (src
)))
294 this_rtx
= GEN_INT (this_val
);
297 this_cost
= rtx_cost (this_rtx
, SET
);
299 else if (GET_CODE (this_rtx
) == REG
)
301 #ifdef LOAD_EXTEND_OP
302 if (extend_op
!= NIL
)
304 this_rtx
= gen_rtx_fmt_e (extend_op
, word_mode
, this_rtx
);
305 this_cost
= rtx_cost (this_rtx
, SET
);
309 this_cost
= REGISTER_MOVE_COST (GET_MODE (this_rtx
),
310 REGNO_REG_CLASS (REGNO (this_rtx
)),
316 /* If equal costs, prefer registers over anything else. That
317 tends to lead to smaller instructions on some machines. */
318 if (this_cost
< old_cost
319 || (this_cost
== old_cost
320 && GET_CODE (this_rtx
) == REG
321 && GET_CODE (SET_SRC (set
)) != REG
))
323 #ifdef LOAD_EXTEND_OP
324 if (GET_MODE_BITSIZE (GET_MODE (SET_DEST (set
))) < BITS_PER_WORD
326 #ifdef CANNOT_CHANGE_MODE_CLASS
327 && !CANNOT_CHANGE_MODE_CLASS (GET_MODE (SET_DEST (set
)),
329 REGNO_REG_CLASS (REGNO (SET_DEST (set
))))
333 rtx wide_dest
= gen_rtx_REG (word_mode
, REGNO (SET_DEST (set
)));
334 ORIGINAL_REGNO (wide_dest
) = ORIGINAL_REGNO (SET_DEST (set
));
335 validate_change (insn
, &SET_DEST (set
), wide_dest
, 1);
339 validate_change (insn
, &SET_SRC (set
), copy_rtx (this_rtx
), 1);
340 old_cost
= this_cost
, did_change
= 1;
347 /* Try to replace operands in INSN with equivalent values that are already
348 in registers. This can be viewed as optional reloading.
350 For each non-register operand in the insn, see if any hard regs are
351 known to be equivalent to that operand. Record the alternatives which
352 can accept these hard registers. Among all alternatives, select the
353 ones which are better or equal to the one currently matching, where
354 "better" is in terms of '?' and '!' constraints. Among the remaining
355 alternatives, select the one which replaces most operands with
359 reload_cse_simplify_operands (insn
, testreg
)
365 /* For each operand, all registers that are equivalent to it. */
366 HARD_REG_SET equiv_regs
[MAX_RECOG_OPERANDS
];
368 const char *constraints
[MAX_RECOG_OPERANDS
];
370 /* Vector recording how bad an alternative is. */
371 int *alternative_reject
;
372 /* Vector recording how many registers can be introduced by choosing
374 int *alternative_nregs
;
375 /* Array of vectors recording, for each operand and each alternative,
376 which hard register to substitute, or -1 if the operand should be
378 int *op_alt_regno
[MAX_RECOG_OPERANDS
];
379 /* Array of alternatives, sorted in order of decreasing desirability. */
380 int *alternative_order
;
384 if (recog_data
.n_alternatives
== 0 || recog_data
.n_operands
== 0)
387 /* Figure out which alternative currently matches. */
388 if (! constrain_operands (1))
389 fatal_insn_not_found (insn
);
391 alternative_reject
= (int *) alloca (recog_data
.n_alternatives
* sizeof (int));
392 alternative_nregs
= (int *) alloca (recog_data
.n_alternatives
* sizeof (int));
393 alternative_order
= (int *) alloca (recog_data
.n_alternatives
* sizeof (int));
394 memset ((char *) alternative_reject
, 0, recog_data
.n_alternatives
* sizeof (int));
395 memset ((char *) alternative_nregs
, 0, recog_data
.n_alternatives
* sizeof (int));
397 /* For each operand, find out which regs are equivalent. */
398 for (i
= 0; i
< recog_data
.n_operands
; i
++)
401 struct elt_loc_list
*l
;
403 CLEAR_HARD_REG_SET (equiv_regs
[i
]);
405 /* cselib blows up on CODE_LABELs. Trying to fix that doesn't seem
406 right, so avoid the problem here. Likewise if we have a constant
407 and the insn pattern doesn't tell us the mode we need. */
408 if (GET_CODE (recog_data
.operand
[i
]) == CODE_LABEL
409 || (CONSTANT_P (recog_data
.operand
[i
])
410 && recog_data
.operand_mode
[i
] == VOIDmode
))
413 v
= cselib_lookup (recog_data
.operand
[i
], recog_data
.operand_mode
[i
], 0);
417 for (l
= v
->locs
; l
; l
= l
->next
)
418 if (GET_CODE (l
->loc
) == REG
)
419 SET_HARD_REG_BIT (equiv_regs
[i
], REGNO (l
->loc
));
422 for (i
= 0; i
< recog_data
.n_operands
; i
++)
424 enum machine_mode mode
;
428 op_alt_regno
[i
] = (int *) alloca (recog_data
.n_alternatives
* sizeof (int));
429 for (j
= 0; j
< recog_data
.n_alternatives
; j
++)
430 op_alt_regno
[i
][j
] = -1;
432 p
= constraints
[i
] = recog_data
.constraints
[i
];
433 mode
= recog_data
.operand_mode
[i
];
435 /* Add the reject values for each alternative given by the constraints
444 alternative_reject
[j
] += 3;
446 alternative_reject
[j
] += 300;
449 /* We won't change operands which are already registers. We
450 also don't want to modify output operands. */
451 regno
= true_regnum (recog_data
.operand
[i
]);
453 || constraints
[i
][0] == '='
454 || constraints
[i
][0] == '+')
457 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
459 int class = (int) NO_REGS
;
461 if (! TEST_HARD_REG_BIT (equiv_regs
[i
], regno
))
464 REGNO (testreg
) = regno
;
465 PUT_MODE (testreg
, mode
);
467 /* We found a register equal to this operand. Now look for all
468 alternatives that can accept this register and have not been
469 assigned a register they can use yet. */
478 case '=': case '+': case '?':
479 case '#': case '&': case '!':
481 case '0': case '1': case '2': case '3': case '4':
482 case '5': case '6': case '7': case '8': case '9':
483 case 'm': case '<': case '>': case 'V': case 'o':
484 case 'E': case 'F': case 'G': case 'H':
485 case 's': case 'i': case 'n':
486 case 'I': case 'J': case 'K': case 'L':
487 case 'M': case 'N': case 'O': case 'P':
489 /* These don't say anything we care about. */
493 class = reg_class_subunion
[(int) class][(int) GENERAL_REGS
];
498 = (reg_class_subunion
500 [(int) REG_CLASS_FROM_CONSTRAINT ((unsigned char) c
, p
)]);
504 /* See if REGNO fits this alternative, and set it up as the
505 replacement register if we don't have one for this
506 alternative yet and the operand being replaced is not
507 a cheap CONST_INT. */
508 if (op_alt_regno
[i
][j
] == -1
509 && reg_fits_class_p (testreg
, class, 0, mode
)
510 && (GET_CODE (recog_data
.operand
[i
]) != CONST_INT
511 || (rtx_cost (recog_data
.operand
[i
], SET
)
512 > rtx_cost (testreg
, SET
))))
514 alternative_nregs
[j
]++;
515 op_alt_regno
[i
][j
] = regno
;
520 p
+= CONSTRAINT_LEN (c
, p
);
528 /* Record all alternatives which are better or equal to the currently
529 matching one in the alternative_order array. */
530 for (i
= j
= 0; i
< recog_data
.n_alternatives
; i
++)
531 if (alternative_reject
[i
] <= alternative_reject
[which_alternative
])
532 alternative_order
[j
++] = i
;
533 recog_data
.n_alternatives
= j
;
535 /* Sort it. Given a small number of alternatives, a dumb algorithm
536 won't hurt too much. */
537 for (i
= 0; i
< recog_data
.n_alternatives
- 1; i
++)
540 int best_reject
= alternative_reject
[alternative_order
[i
]];
541 int best_nregs
= alternative_nregs
[alternative_order
[i
]];
544 for (j
= i
+ 1; j
< recog_data
.n_alternatives
; j
++)
546 int this_reject
= alternative_reject
[alternative_order
[j
]];
547 int this_nregs
= alternative_nregs
[alternative_order
[j
]];
549 if (this_reject
< best_reject
550 || (this_reject
== best_reject
&& this_nregs
< best_nregs
))
553 best_reject
= this_reject
;
554 best_nregs
= this_nregs
;
558 tmp
= alternative_order
[best
];
559 alternative_order
[best
] = alternative_order
[i
];
560 alternative_order
[i
] = tmp
;
563 /* Substitute the operands as determined by op_alt_regno for the best
565 j
= alternative_order
[0];
567 for (i
= 0; i
< recog_data
.n_operands
; i
++)
569 enum machine_mode mode
= recog_data
.operand_mode
[i
];
570 if (op_alt_regno
[i
][j
] == -1)
573 validate_change (insn
, recog_data
.operand_loc
[i
],
574 gen_rtx_REG (mode
, op_alt_regno
[i
][j
]), 1);
577 for (i
= recog_data
.n_dups
- 1; i
>= 0; i
--)
579 int op
= recog_data
.dup_num
[i
];
580 enum machine_mode mode
= recog_data
.operand_mode
[op
];
582 if (op_alt_regno
[op
][j
] == -1)
585 validate_change (insn
, recog_data
.dup_loc
[i
],
586 gen_rtx_REG (mode
, op_alt_regno
[op
][j
]), 1);
589 return apply_change_group ();
592 /* If reload couldn't use reg+reg+offset addressing, try to use reg+reg
594 This code might also be useful when reload gave up on reg+reg addressing
595 because of clashes between the return register and INDEX_REG_CLASS. */
597 /* The maximum number of uses of a register we can keep track of to
598 replace them with reg+reg addressing. */
599 #define RELOAD_COMBINE_MAX_USES 6
601 /* INSN is the insn where a register has ben used, and USEP points to the
602 location of the register within the rtl. */
603 struct reg_use
{ rtx insn
, *usep
; };
605 /* If the register is used in some unknown fashion, USE_INDEX is negative.
606 If it is dead, USE_INDEX is RELOAD_COMBINE_MAX_USES, and STORE_RUID
607 indicates where it becomes live again.
608 Otherwise, USE_INDEX is the index of the last encountered use of the
609 register (which is first among these we have seen since we scan backwards),
610 OFFSET contains the constant offset that is added to the register in
611 all encountered uses, and USE_RUID indicates the first encountered, i.e.
613 STORE_RUID is always meaningful if we only want to use a value in a
614 register in a different place: it denotes the next insn in the insn
615 stream (i.e. the last encountered) that sets or clobbers the register. */
618 struct reg_use reg_use
[RELOAD_COMBINE_MAX_USES
];
623 } reg_state
[FIRST_PSEUDO_REGISTER
];
625 /* Reverse linear uid. This is increased in reload_combine while scanning
626 the instructions from last to first. It is used to set last_label_ruid
627 and the store_ruid / use_ruid fields in reg_state. */
628 static int reload_combine_ruid
;
630 #define LABEL_LIVE(LABEL) \
631 (label_live[CODE_LABEL_NUMBER (LABEL) - min_labelno])
637 int first_index_reg
= -1;
638 int last_index_reg
= 0;
643 int min_labelno
, n_labels
;
644 HARD_REG_SET ever_live_at_start
, *label_live
;
646 /* If reg+reg can be used in offsetable memory addresses, the main chunk of
647 reload has already used it where appropriate, so there is no use in
648 trying to generate it now. */
649 if (double_reg_address_ok
&& INDEX_REG_CLASS
!= NO_REGS
)
652 /* To avoid wasting too much time later searching for an index register,
653 determine the minimum and maximum index register numbers. */
654 for (r
= 0; r
< FIRST_PSEUDO_REGISTER
; r
++)
655 if (TEST_HARD_REG_BIT (reg_class_contents
[INDEX_REG_CLASS
], r
))
657 if (first_index_reg
== -1)
663 /* If no index register is available, we can quit now. */
664 if (first_index_reg
== -1)
667 /* Set up LABEL_LIVE and EVER_LIVE_AT_START. The register lifetime
668 information is a bit fuzzy immediately after reload, but it's
669 still good enough to determine which registers are live at a jump
671 min_labelno
= get_first_label_num ();
672 n_labels
= max_label_num () - min_labelno
;
673 label_live
= (HARD_REG_SET
*) xmalloc (n_labels
* sizeof (HARD_REG_SET
));
674 CLEAR_HARD_REG_SET (ever_live_at_start
);
676 FOR_EACH_BB_REVERSE (bb
)
679 if (GET_CODE (insn
) == CODE_LABEL
)
683 REG_SET_TO_HARD_REG_SET (live
,
684 bb
->global_live_at_start
);
685 compute_use_by_pseudos (&live
,
686 bb
->global_live_at_start
);
687 COPY_HARD_REG_SET (LABEL_LIVE (insn
), live
);
688 IOR_HARD_REG_SET (ever_live_at_start
, live
);
692 /* Initialize last_label_ruid, reload_combine_ruid and reg_state. */
693 last_label_ruid
= reload_combine_ruid
= 0;
694 for (r
= 0; r
< FIRST_PSEUDO_REGISTER
; r
++)
696 reg_state
[r
].store_ruid
= reload_combine_ruid
;
698 reg_state
[r
].use_index
= -1;
700 reg_state
[r
].use_index
= RELOAD_COMBINE_MAX_USES
;
703 for (insn
= get_last_insn (); insn
; insn
= PREV_INSN (insn
))
707 /* We cannot do our optimization across labels. Invalidating all the use
708 information we have would be costly, so we just note where the label
709 is and then later disable any optimization that would cross it. */
710 if (GET_CODE (insn
) == CODE_LABEL
)
711 last_label_ruid
= reload_combine_ruid
;
712 else if (GET_CODE (insn
) == BARRIER
)
713 for (r
= 0; r
< FIRST_PSEUDO_REGISTER
; r
++)
715 reg_state
[r
].use_index
= RELOAD_COMBINE_MAX_USES
;
720 reload_combine_ruid
++;
722 /* Look for (set (REGX) (CONST_INT))
723 (set (REGX) (PLUS (REGX) (REGY)))
727 (set (REGZ) (CONST_INT))
729 ... (MEM (PLUS (REGZ) (REGY)))... .
731 First, check that we have (set (REGX) (PLUS (REGX) (REGY)))
732 and that we know all uses of REGX before it dies. */
733 set
= single_set (insn
);
735 && GET_CODE (SET_DEST (set
)) == REG
736 && (HARD_REGNO_NREGS (REGNO (SET_DEST (set
)),
737 GET_MODE (SET_DEST (set
)))
739 && GET_CODE (SET_SRC (set
)) == PLUS
740 && GET_CODE (XEXP (SET_SRC (set
), 1)) == REG
741 && rtx_equal_p (XEXP (SET_SRC (set
), 0), SET_DEST (set
))
742 && last_label_ruid
< reg_state
[REGNO (SET_DEST (set
))].use_ruid
)
744 rtx reg
= SET_DEST (set
);
745 rtx plus
= SET_SRC (set
);
746 rtx base
= XEXP (plus
, 1);
747 rtx prev
= prev_nonnote_insn (insn
);
748 rtx prev_set
= prev
? single_set (prev
) : NULL_RTX
;
749 unsigned int regno
= REGNO (reg
);
750 rtx const_reg
= NULL_RTX
;
751 rtx reg_sum
= NULL_RTX
;
753 /* Now, we need an index register.
754 We'll set index_reg to this index register, const_reg to the
755 register that is to be loaded with the constant
756 (denoted as REGZ in the substitution illustration above),
757 and reg_sum to the register-register that we want to use to
758 substitute uses of REG (typically in MEMs) with.
759 First check REG and BASE for being index registers;
760 we can use them even if they are not dead. */
761 if (TEST_HARD_REG_BIT (reg_class_contents
[INDEX_REG_CLASS
], regno
)
762 || TEST_HARD_REG_BIT (reg_class_contents
[INDEX_REG_CLASS
],
770 /* Otherwise, look for a free index register. Since we have
771 checked above that neiter REG nor BASE are index registers,
772 if we find anything at all, it will be different from these
774 for (i
= first_index_reg
; i
<= last_index_reg
; i
++)
776 if (TEST_HARD_REG_BIT (reg_class_contents
[INDEX_REG_CLASS
],
778 && reg_state
[i
].use_index
== RELOAD_COMBINE_MAX_USES
779 && reg_state
[i
].store_ruid
<= reg_state
[regno
].use_ruid
780 && HARD_REGNO_NREGS (i
, GET_MODE (reg
)) == 1)
782 rtx index_reg
= gen_rtx_REG (GET_MODE (reg
), i
);
784 const_reg
= index_reg
;
785 reg_sum
= gen_rtx_PLUS (GET_MODE (reg
), index_reg
, base
);
791 /* Check that PREV_SET is indeed (set (REGX) (CONST_INT)) and that
792 (REGY), i.e. BASE, is not clobbered before the last use we'll
795 && GET_CODE (SET_SRC (prev_set
)) == CONST_INT
796 && rtx_equal_p (SET_DEST (prev_set
), reg
)
797 && reg_state
[regno
].use_index
>= 0
798 && (reg_state
[REGNO (base
)].store_ruid
799 <= reg_state
[regno
].use_ruid
)
804 /* Change destination register and, if necessary, the
805 constant value in PREV, the constant loading instruction. */
806 validate_change (prev
, &SET_DEST (prev_set
), const_reg
, 1);
807 if (reg_state
[regno
].offset
!= const0_rtx
)
808 validate_change (prev
,
810 GEN_INT (INTVAL (SET_SRC (prev_set
))
811 + INTVAL (reg_state
[regno
].offset
)),
814 /* Now for every use of REG that we have recorded, replace REG
816 for (i
= reg_state
[regno
].use_index
;
817 i
< RELOAD_COMBINE_MAX_USES
; i
++)
818 validate_change (reg_state
[regno
].reg_use
[i
].insn
,
819 reg_state
[regno
].reg_use
[i
].usep
,
820 /* Each change must have its own
822 copy_rtx (reg_sum
), 1);
824 if (apply_change_group ())
828 /* Delete the reg-reg addition. */
831 if (reg_state
[regno
].offset
!= const0_rtx
)
832 /* Previous REG_EQUIV / REG_EQUAL notes for PREV
834 for (np
= ®_NOTES (prev
); *np
;)
836 if (REG_NOTE_KIND (*np
) == REG_EQUAL
837 || REG_NOTE_KIND (*np
) == REG_EQUIV
)
843 reg_state
[regno
].use_index
= RELOAD_COMBINE_MAX_USES
;
844 reg_state
[REGNO (const_reg
)].store_ruid
845 = reload_combine_ruid
;
851 note_stores (PATTERN (insn
), reload_combine_note_store
, NULL
);
853 if (GET_CODE (insn
) == CALL_INSN
)
857 for (r
= 0; r
< FIRST_PSEUDO_REGISTER
; r
++)
858 if (call_used_regs
[r
])
860 reg_state
[r
].use_index
= RELOAD_COMBINE_MAX_USES
;
861 reg_state
[r
].store_ruid
= reload_combine_ruid
;
864 for (link
= CALL_INSN_FUNCTION_USAGE (insn
); link
;
865 link
= XEXP (link
, 1))
867 rtx usage_rtx
= XEXP (XEXP (link
, 0), 0);
868 if (GET_CODE (usage_rtx
) == REG
)
871 unsigned int start_reg
= REGNO (usage_rtx
);
872 unsigned int num_regs
=
873 HARD_REGNO_NREGS (start_reg
, GET_MODE (usage_rtx
));
874 unsigned int end_reg
= start_reg
+ num_regs
- 1;
875 for (i
= start_reg
; i
<= end_reg
; i
++)
876 if (GET_CODE (XEXP (link
, 0)) == CLOBBER
)
878 reg_state
[i
].use_index
= RELOAD_COMBINE_MAX_USES
;
879 reg_state
[i
].store_ruid
= reload_combine_ruid
;
882 reg_state
[i
].use_index
= -1;
887 else if (GET_CODE (insn
) == JUMP_INSN
888 && GET_CODE (PATTERN (insn
)) != RETURN
)
890 /* Non-spill registers might be used at the call destination in
891 some unknown fashion, so we have to mark the unknown use. */
894 if ((condjump_p (insn
) || condjump_in_parallel_p (insn
))
895 && JUMP_LABEL (insn
))
896 live
= &LABEL_LIVE (JUMP_LABEL (insn
));
898 live
= &ever_live_at_start
;
900 for (i
= FIRST_PSEUDO_REGISTER
- 1; i
>= 0; --i
)
901 if (TEST_HARD_REG_BIT (*live
, i
))
902 reg_state
[i
].use_index
= -1;
905 reload_combine_note_use (&PATTERN (insn
), insn
);
906 for (note
= REG_NOTES (insn
); note
; note
= XEXP (note
, 1))
908 if (REG_NOTE_KIND (note
) == REG_INC
909 && GET_CODE (XEXP (note
, 0)) == REG
)
911 int regno
= REGNO (XEXP (note
, 0));
913 reg_state
[regno
].store_ruid
= reload_combine_ruid
;
914 reg_state
[regno
].use_index
= -1;
922 /* Check if DST is a register or a subreg of a register; if it is,
923 update reg_state[regno].store_ruid and reg_state[regno].use_index
924 accordingly. Called via note_stores from reload_combine. */
927 reload_combine_note_store (dst
, set
, data
)
929 void *data ATTRIBUTE_UNUSED
;
933 enum machine_mode mode
= GET_MODE (dst
);
935 if (GET_CODE (dst
) == SUBREG
)
937 regno
= subreg_regno_offset (REGNO (SUBREG_REG (dst
)),
938 GET_MODE (SUBREG_REG (dst
)),
941 dst
= SUBREG_REG (dst
);
943 if (GET_CODE (dst
) != REG
)
945 regno
+= REGNO (dst
);
947 /* note_stores might have stripped a STRICT_LOW_PART, so we have to be
948 careful with registers / register parts that are not full words.
950 Similarly for ZERO_EXTRACT and SIGN_EXTRACT. */
951 if (GET_CODE (set
) != SET
952 || GET_CODE (SET_DEST (set
)) == ZERO_EXTRACT
953 || GET_CODE (SET_DEST (set
)) == SIGN_EXTRACT
954 || GET_CODE (SET_DEST (set
)) == STRICT_LOW_PART
)
956 for (i
= HARD_REGNO_NREGS (regno
, mode
) - 1 + regno
; i
>= regno
; i
--)
958 reg_state
[i
].use_index
= -1;
959 reg_state
[i
].store_ruid
= reload_combine_ruid
;
964 for (i
= HARD_REGNO_NREGS (regno
, mode
) - 1 + regno
; i
>= regno
; i
--)
966 reg_state
[i
].store_ruid
= reload_combine_ruid
;
967 reg_state
[i
].use_index
= RELOAD_COMBINE_MAX_USES
;
972 /* XP points to a piece of rtl that has to be checked for any uses of
974 *XP is the pattern of INSN, or a part of it.
975 Called from reload_combine, and recursively by itself. */
977 reload_combine_note_use (xp
, insn
)
981 enum rtx_code code
= x
->code
;
984 rtx offset
= const0_rtx
; /* For the REG case below. */
989 if (GET_CODE (SET_DEST (x
)) == REG
)
991 reload_combine_note_use (&SET_SRC (x
), insn
);
997 /* If this is the USE of a return value, we can't change it. */
998 if (GET_CODE (XEXP (x
, 0)) == REG
&& REG_FUNCTION_VALUE_P (XEXP (x
, 0)))
1000 /* Mark the return register as used in an unknown fashion. */
1001 rtx reg
= XEXP (x
, 0);
1002 int regno
= REGNO (reg
);
1003 int nregs
= HARD_REGNO_NREGS (regno
, GET_MODE (reg
));
1005 while (--nregs
>= 0)
1006 reg_state
[regno
+ nregs
].use_index
= -1;
1012 if (GET_CODE (SET_DEST (x
)) == REG
)
1014 /* No spurious CLOBBERs of pseudo registers may remain. */
1015 if (REGNO (SET_DEST (x
)) >= FIRST_PSEUDO_REGISTER
)
1022 /* We are interested in (plus (reg) (const_int)) . */
1023 if (GET_CODE (XEXP (x
, 0)) != REG
1024 || GET_CODE (XEXP (x
, 1)) != CONST_INT
)
1026 offset
= XEXP (x
, 1);
1031 int regno
= REGNO (x
);
1035 /* No spurious USEs of pseudo registers may remain. */
1036 if (regno
>= FIRST_PSEUDO_REGISTER
)
1039 nregs
= HARD_REGNO_NREGS (regno
, GET_MODE (x
));
1041 /* We can't substitute into multi-hard-reg uses. */
1044 while (--nregs
>= 0)
1045 reg_state
[regno
+ nregs
].use_index
= -1;
1049 /* If this register is already used in some unknown fashion, we
1051 If we decrement the index from zero to -1, we can't store more
1052 uses, so this register becomes used in an unknown fashion. */
1053 use_index
= --reg_state
[regno
].use_index
;
1057 if (use_index
!= RELOAD_COMBINE_MAX_USES
- 1)
1059 /* We have found another use for a register that is already
1060 used later. Check if the offsets match; if not, mark the
1061 register as used in an unknown fashion. */
1062 if (! rtx_equal_p (offset
, reg_state
[regno
].offset
))
1064 reg_state
[regno
].use_index
= -1;
1070 /* This is the first use of this register we have seen since we
1071 marked it as dead. */
1072 reg_state
[regno
].offset
= offset
;
1073 reg_state
[regno
].use_ruid
= reload_combine_ruid
;
1075 reg_state
[regno
].reg_use
[use_index
].insn
= insn
;
1076 reg_state
[regno
].reg_use
[use_index
].usep
= xp
;
1084 /* Recursively process the components of X. */
1085 fmt
= GET_RTX_FORMAT (code
);
1086 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
1089 reload_combine_note_use (&XEXP (x
, i
), insn
);
1090 else if (fmt
[i
] == 'E')
1092 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
1093 reload_combine_note_use (&XVECEXP (x
, i
, j
), insn
);
1098 /* See if we can reduce the cost of a constant by replacing a move
1099 with an add. We track situations in which a register is set to a
1100 constant or to a register plus a constant. */
1101 /* We cannot do our optimization across labels. Invalidating all the
1102 information about register contents we have would be costly, so we
1103 use move2add_last_label_luid to note where the label is and then
1104 later disable any optimization that would cross it.
1105 reg_offset[n] / reg_base_reg[n] / reg_mode[n] are only valid if
1106 reg_set_luid[n] is greater than move2add_last_label_luid. */
1107 static int reg_set_luid
[FIRST_PSEUDO_REGISTER
];
1109 /* If reg_base_reg[n] is negative, register n has been set to
1110 reg_offset[n] in mode reg_mode[n] .
1111 If reg_base_reg[n] is non-negative, register n has been set to the
1112 sum of reg_offset[n] and the value of register reg_base_reg[n]
1113 before reg_set_luid[n], calculated in mode reg_mode[n] . */
1114 static HOST_WIDE_INT reg_offset
[FIRST_PSEUDO_REGISTER
];
1115 static int reg_base_reg
[FIRST_PSEUDO_REGISTER
];
1116 static enum machine_mode reg_mode
[FIRST_PSEUDO_REGISTER
];
1118 /* move2add_luid is linearly increased while scanning the instructions
1119 from first to last. It is used to set reg_set_luid in
1120 reload_cse_move2add and move2add_note_store. */
1121 static int move2add_luid
;
1123 /* move2add_last_label_luid is set whenever a label is found. Labels
1124 invalidate all previously collected reg_offset data. */
1125 static int move2add_last_label_luid
;
1127 /* ??? We don't know how zero / sign extension is handled, hence we
1128 can't go from a narrower to a wider mode. */
1129 #define MODES_OK_FOR_MOVE2ADD(OUTMODE, INMODE) \
1130 (GET_MODE_SIZE (OUTMODE) == GET_MODE_SIZE (INMODE) \
1131 || (GET_MODE_SIZE (OUTMODE) <= GET_MODE_SIZE (INMODE) \
1132 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (OUTMODE), \
1133 GET_MODE_BITSIZE (INMODE))))
1136 reload_cse_move2add (first
)
1142 for (i
= FIRST_PSEUDO_REGISTER
- 1; i
>= 0; i
--)
1143 reg_set_luid
[i
] = 0;
1145 move2add_last_label_luid
= 0;
1147 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
), move2add_luid
++)
1151 if (GET_CODE (insn
) == CODE_LABEL
)
1153 move2add_last_label_luid
= move2add_luid
;
1154 /* We're going to increment move2add_luid twice after a
1155 label, so that we can use move2add_last_label_luid + 1 as
1156 the luid for constants. */
1160 if (! INSN_P (insn
))
1162 pat
= PATTERN (insn
);
1163 /* For simplicity, we only perform this optimization on
1164 straightforward SETs. */
1165 if (GET_CODE (pat
) == SET
1166 && GET_CODE (SET_DEST (pat
)) == REG
)
1168 rtx reg
= SET_DEST (pat
);
1169 int regno
= REGNO (reg
);
1170 rtx src
= SET_SRC (pat
);
1172 /* Check if we have valid information on the contents of this
1173 register in the mode of REG. */
1174 if (reg_set_luid
[regno
] > move2add_last_label_luid
1175 && MODES_OK_FOR_MOVE2ADD (GET_MODE (reg
), reg_mode
[regno
]))
1177 /* Try to transform (set (REGX) (CONST_INT A))
1179 (set (REGX) (CONST_INT B))
1181 (set (REGX) (CONST_INT A))
1183 (set (REGX) (plus (REGX) (CONST_INT B-A)))
1185 (set (REGX) (CONST_INT A))
1187 (set (STRICT_LOW_PART (REGX)) (CONST_INT B))
1190 if (GET_CODE (src
) == CONST_INT
&& reg_base_reg
[regno
] < 0)
1193 GEN_INT (trunc_int_for_mode (INTVAL (src
)
1194 - reg_offset
[regno
],
1196 /* (set (reg) (plus (reg) (const_int 0))) is not canonical;
1197 use (set (reg) (reg)) instead.
1198 We don't delete this insn, nor do we convert it into a
1199 note, to avoid losing register notes or the return
1200 value flag. jump2 already knows how to get rid of
1202 if (new_src
== const0_rtx
)
1204 /* If the constants are different, this is a
1205 truncation, that, if turned into (set (reg)
1206 (reg)), would be discarded. Maybe we should
1207 try a truncMN pattern? */
1208 if (INTVAL (src
) == reg_offset
[regno
])
1209 validate_change (insn
, &SET_SRC (pat
), reg
, 0);
1211 else if (rtx_cost (new_src
, PLUS
) < rtx_cost (src
, SET
)
1212 && have_add2_insn (reg
, new_src
))
1214 rtx newpat
= gen_add2_insn (reg
, new_src
);
1215 if (INSN_P (newpat
) && NEXT_INSN (newpat
) == NULL_RTX
)
1216 newpat
= PATTERN (newpat
);
1217 /* If it was the first insn of a sequence or
1218 some other emitted insn, validate_change will
1220 validate_change (insn
, &PATTERN (insn
),
1225 enum machine_mode narrow_mode
;
1226 for (narrow_mode
= GET_CLASS_NARROWEST_MODE (MODE_INT
);
1227 narrow_mode
!= GET_MODE (reg
);
1228 narrow_mode
= GET_MODE_WIDER_MODE (narrow_mode
))
1230 if (have_insn_for (STRICT_LOW_PART
, narrow_mode
)
1231 && ((reg_offset
[regno
]
1232 & ~GET_MODE_MASK (narrow_mode
))
1234 & ~GET_MODE_MASK (narrow_mode
))))
1236 rtx narrow_reg
= gen_rtx_REG (narrow_mode
,
1239 GEN_INT (trunc_int_for_mode (INTVAL (src
),
1242 gen_rtx_SET (VOIDmode
,
1243 gen_rtx_STRICT_LOW_PART (VOIDmode
,
1246 if (validate_change (insn
, &PATTERN (insn
),
1252 reg_set_luid
[regno
] = move2add_luid
;
1253 reg_mode
[regno
] = GET_MODE (reg
);
1254 reg_offset
[regno
] = INTVAL (src
);
1258 /* Try to transform (set (REGX) (REGY))
1259 (set (REGX) (PLUS (REGX) (CONST_INT A)))
1262 (set (REGX) (PLUS (REGX) (CONST_INT B)))
1265 (set (REGX) (PLUS (REGX) (CONST_INT A)))
1267 (set (REGX) (plus (REGX) (CONST_INT B-A))) */
1268 else if (GET_CODE (src
) == REG
1269 && reg_set_luid
[regno
] == reg_set_luid
[REGNO (src
)]
1270 && reg_base_reg
[regno
] == reg_base_reg
[REGNO (src
)]
1271 && MODES_OK_FOR_MOVE2ADD (GET_MODE (reg
),
1272 reg_mode
[REGNO (src
)]))
1274 rtx next
= next_nonnote_insn (insn
);
1277 set
= single_set (next
);
1279 && SET_DEST (set
) == reg
1280 && GET_CODE (SET_SRC (set
)) == PLUS
1281 && XEXP (SET_SRC (set
), 0) == reg
1282 && GET_CODE (XEXP (SET_SRC (set
), 1)) == CONST_INT
)
1284 rtx src3
= XEXP (SET_SRC (set
), 1);
1285 HOST_WIDE_INT added_offset
= INTVAL (src3
);
1286 HOST_WIDE_INT base_offset
= reg_offset
[REGNO (src
)];
1287 HOST_WIDE_INT regno_offset
= reg_offset
[regno
];
1289 GEN_INT (trunc_int_for_mode (added_offset
1295 if (new_src
== const0_rtx
)
1296 /* See above why we create (set (reg) (reg)) here. */
1298 = validate_change (next
, &SET_SRC (set
), reg
, 0);
1299 else if ((rtx_cost (new_src
, PLUS
)
1300 < COSTS_N_INSNS (1) + rtx_cost (src3
, SET
))
1301 && have_add2_insn (reg
, new_src
))
1303 rtx newpat
= gen_add2_insn (reg
, new_src
);
1305 && NEXT_INSN (newpat
) == NULL_RTX
)
1306 newpat
= PATTERN (newpat
);
1308 = validate_change (next
, &PATTERN (next
),
1314 reg_mode
[regno
] = GET_MODE (reg
);
1316 trunc_int_for_mode (added_offset
+ base_offset
,
1324 for (note
= REG_NOTES (insn
); note
; note
= XEXP (note
, 1))
1326 if (REG_NOTE_KIND (note
) == REG_INC
1327 && GET_CODE (XEXP (note
, 0)) == REG
)
1329 /* Reset the information about this register. */
1330 int regno
= REGNO (XEXP (note
, 0));
1331 if (regno
< FIRST_PSEUDO_REGISTER
)
1332 reg_set_luid
[regno
] = 0;
1335 note_stores (PATTERN (insn
), move2add_note_store
, NULL
);
1337 /* If INSN is a conditional branch, we try to extract an
1338 implicit set out of it. */
1339 if (any_condjump_p (insn
) && onlyjump_p (insn
))
1341 rtx cnd
= fis_get_condition (insn
);
1344 && GET_CODE (cnd
) == NE
1345 && GET_CODE (XEXP (cnd
, 0)) == REG
1346 /* The following two checks, which are also in
1347 move2add_note_store, are intended to reduce the
1348 number of calls to gen_rtx_SET to avoid memory
1349 allocation if possible. */
1350 && SCALAR_INT_MODE_P (GET_MODE (XEXP (cnd
, 0)))
1351 && HARD_REGNO_NREGS (REGNO (XEXP (cnd
, 0)), GET_MODE (XEXP (cnd
, 0))) == 1
1352 && GET_CODE (XEXP (cnd
, 1)) == CONST_INT
)
1355 gen_rtx_SET (VOIDmode
, XEXP (cnd
, 0), XEXP (cnd
, 1));
1356 move2add_note_store (SET_DEST (implicit_set
), implicit_set
, 0);
1360 /* If this is a CALL_INSN, all call used registers are stored with
1362 if (GET_CODE (insn
) == CALL_INSN
)
1364 for (i
= FIRST_PSEUDO_REGISTER
- 1; i
>= 0; i
--)
1366 if (call_used_regs
[i
])
1367 /* Reset the information about this register. */
1368 reg_set_luid
[i
] = 0;
1374 /* SET is a SET or CLOBBER that sets DST.
1375 Update reg_set_luid, reg_offset and reg_base_reg accordingly.
1376 Called from reload_cse_move2add via note_stores. */
1379 move2add_note_store (dst
, set
, data
)
1381 void *data ATTRIBUTE_UNUSED
;
1383 unsigned int regno
= 0;
1385 enum machine_mode mode
= GET_MODE (dst
);
1387 if (GET_CODE (dst
) == SUBREG
)
1389 regno
= subreg_regno_offset (REGNO (SUBREG_REG (dst
)),
1390 GET_MODE (SUBREG_REG (dst
)),
1393 dst
= SUBREG_REG (dst
);
1396 /* Some targets do argument pushes without adding REG_INC notes. */
1398 if (GET_CODE (dst
) == MEM
)
1400 dst
= XEXP (dst
, 0);
1401 if (GET_CODE (dst
) == PRE_INC
|| GET_CODE (dst
) == POST_INC
1402 || GET_CODE (dst
) == PRE_DEC
|| GET_CODE (dst
) == POST_DEC
)
1403 reg_set_luid
[REGNO (XEXP (dst
, 0))] = 0;
1406 if (GET_CODE (dst
) != REG
)
1409 regno
+= REGNO (dst
);
1411 if (SCALAR_INT_MODE_P (mode
)
1412 && HARD_REGNO_NREGS (regno
, mode
) == 1 && GET_CODE (set
) == SET
1413 && GET_CODE (SET_DEST (set
)) != ZERO_EXTRACT
1414 && GET_CODE (SET_DEST (set
)) != SIGN_EXTRACT
1415 && GET_CODE (SET_DEST (set
)) != STRICT_LOW_PART
)
1417 rtx src
= SET_SRC (set
);
1419 HOST_WIDE_INT offset
;
1421 /* This may be different from mode, if SET_DEST (set) is a
1423 enum machine_mode dst_mode
= GET_MODE (dst
);
1425 switch (GET_CODE (src
))
1428 if (GET_CODE (XEXP (src
, 0)) == REG
)
1430 base_reg
= XEXP (src
, 0);
1432 if (GET_CODE (XEXP (src
, 1)) == CONST_INT
)
1433 offset
= INTVAL (XEXP (src
, 1));
1434 else if (GET_CODE (XEXP (src
, 1)) == REG
1435 && (reg_set_luid
[REGNO (XEXP (src
, 1))]
1436 > move2add_last_label_luid
)
1437 && (MODES_OK_FOR_MOVE2ADD
1438 (dst_mode
, reg_mode
[REGNO (XEXP (src
, 1))])))
1440 if (reg_base_reg
[REGNO (XEXP (src
, 1))] < 0)
1441 offset
= reg_offset
[REGNO (XEXP (src
, 1))];
1442 /* Maybe the first register is known to be a
1444 else if (reg_set_luid
[REGNO (base_reg
)]
1445 > move2add_last_label_luid
1446 && (MODES_OK_FOR_MOVE2ADD
1447 (dst_mode
, reg_mode
[REGNO (XEXP (src
, 1))]))
1448 && reg_base_reg
[REGNO (base_reg
)] < 0)
1450 offset
= reg_offset
[REGNO (base_reg
)];
1451 base_reg
= XEXP (src
, 1);
1470 /* Start tracking the register as a constant. */
1471 reg_base_reg
[regno
] = -1;
1472 reg_offset
[regno
] = INTVAL (SET_SRC (set
));
1473 /* We assign the same luid to all registers set to constants. */
1474 reg_set_luid
[regno
] = move2add_last_label_luid
+ 1;
1475 reg_mode
[regno
] = mode
;
1480 /* Invalidate the contents of the register. */
1481 reg_set_luid
[regno
] = 0;
1485 base_regno
= REGNO (base_reg
);
1486 /* If information about the base register is not valid, set it
1487 up as a new base register, pretending its value is known
1488 starting from the current insn. */
1489 if (reg_set_luid
[base_regno
] <= move2add_last_label_luid
)
1491 reg_base_reg
[base_regno
] = base_regno
;
1492 reg_offset
[base_regno
] = 0;
1493 reg_set_luid
[base_regno
] = move2add_luid
;
1494 reg_mode
[base_regno
] = mode
;
1496 else if (! MODES_OK_FOR_MOVE2ADD (dst_mode
,
1497 reg_mode
[base_regno
]))
1500 reg_mode
[regno
] = mode
;
1502 /* Copy base information from our base register. */
1503 reg_set_luid
[regno
] = reg_set_luid
[base_regno
];
1504 reg_base_reg
[regno
] = reg_base_reg
[base_regno
];
1506 /* Compute the sum of the offsets or constants. */
1507 reg_offset
[regno
] = trunc_int_for_mode (offset
1508 + reg_offset
[base_regno
],
1513 unsigned int endregno
= regno
+ HARD_REGNO_NREGS (regno
, mode
);
1515 for (i
= regno
; i
< endregno
; i
++)
1516 /* Reset the information about this register. */
1517 reg_set_luid
[i
] = 0;