1 /* Subroutines used by or related to instruction recognition.
2 Copyright (C) 1987-2020 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify it under
7 the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 3, or (at your option) any later
11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
23 #include "coretypes.h"
32 #include "insn-config.h"
36 #include "insn-attr.h"
37 #include "addresses.h"
40 #include "cfgcleanup.h"
42 #include "tree-pass.h"
43 #include "function-abi.h"
45 #ifndef STACK_POP_CODE
46 #if STACK_GROWS_DOWNWARD
47 #define STACK_POP_CODE POST_INC
49 #define STACK_POP_CODE POST_DEC
53 static void validate_replace_rtx_1 (rtx
*, rtx
, rtx
, rtx_insn
*, bool);
54 static void validate_replace_src_1 (rtx
*, void *);
55 static rtx_insn
*split_insn (rtx_insn
*);
57 struct target_recog default_target_recog
;
59 struct target_recog
*this_target_recog
= &default_target_recog
;
62 /* Nonzero means allow operands to be volatile.
63 This should be 0 if you are generating rtl, such as if you are calling
64 the functions in optabs.c and expmed.c (most of the time).
65 This should be 1 if all valid insns need to be recognized,
66 such as in reginfo.c and final.c and reload.c.
68 init_recog and init_recog_no_volatile are responsible for setting this. */
72 struct recog_data_d recog_data
;
74 /* Contains a vector of operand_alternative structures, such that
75 operand OP of alternative A is at index A * n_operands + OP.
76 Set up by preprocess_constraints. */
77 const operand_alternative
*recog_op_alt
;
79 /* Used to provide recog_op_alt for asms. */
80 static operand_alternative asm_op_alt
[MAX_RECOG_OPERANDS
81 * MAX_RECOG_ALTERNATIVES
];
83 /* On return from `constrain_operands', indicate which alternative
86 int which_alternative
;
88 /* Nonzero after end of reload pass.
89 Set to 1 or 0 by toplev.c.
90 Controls the significance of (SUBREG (MEM)). */
94 /* Nonzero after thread_prologue_and_epilogue_insns has run. */
95 int epilogue_completed
;
97 /* Initialize data used by the function `recog'.
98 This must be called once in the compilation of a function
99 before any insn recognition may be done in the function. */
102 init_recog_no_volatile (void)
114 /* Return true if labels in asm operands BODY are LABEL_REFs. */
117 asm_labels_ok (rtx body
)
122 asmop
= extract_asm_operands (body
);
123 if (asmop
== NULL_RTX
)
126 for (i
= 0; i
< ASM_OPERANDS_LABEL_LENGTH (asmop
); i
++)
127 if (GET_CODE (ASM_OPERANDS_LABEL (asmop
, i
)) != LABEL_REF
)
133 /* Check that X is an insn-body for an `asm' with operands
134 and that the operands mentioned in it are legitimate. */
137 check_asm_operands (rtx x
)
141 const char **constraints
;
144 if (!asm_labels_ok (x
))
147 /* Post-reload, be more strict with things. */
148 if (reload_completed
)
150 /* ??? Doh! We've not got the wrapping insn. Cook one up. */
151 rtx_insn
*insn
= make_insn_raw (x
);
153 constrain_operands (1, get_enabled_alternatives (insn
));
154 return which_alternative
>= 0;
157 noperands
= asm_noperands (x
);
163 operands
= XALLOCAVEC (rtx
, noperands
);
164 constraints
= XALLOCAVEC (const char *, noperands
);
166 decode_asm_operands (x
, operands
, NULL
, constraints
, NULL
, NULL
);
168 for (i
= 0; i
< noperands
; i
++)
170 const char *c
= constraints
[i
];
173 if (! asm_operand_ok (operands
[i
], c
, constraints
))
180 /* Static data for the next two routines. */
191 static change_t
*changes
;
192 static int changes_allocated
;
194 static int num_changes
= 0;
196 /* Validate a proposed change to OBJECT. LOC is the location in the rtl
197 at which NEW_RTX will be placed. If OBJECT is zero, no validation is done,
198 the change is simply made.
200 Two types of objects are supported: If OBJECT is a MEM, memory_address_p
201 will be called with the address and mode as parameters. If OBJECT is
202 an INSN, CALL_INSN, or JUMP_INSN, the insn will be re-recognized with
205 IN_GROUP is nonzero if this is part of a group of changes that must be
206 performed as a group. In that case, the changes will be stored. The
207 function `apply_change_group' will validate and apply the changes.
209 If IN_GROUP is zero, this is a single change. Try to recognize the insn
210 or validate the memory reference with the change applied. If the result
211 is not valid for the machine, suppress the change and return zero.
212 Otherwise, perform the change and return 1. */
215 validate_change_1 (rtx object
, rtx
*loc
, rtx new_rtx
, bool in_group
, bool unshare
)
219 if (old
== new_rtx
|| rtx_equal_p (old
, new_rtx
))
222 gcc_assert (in_group
!= 0 || num_changes
== 0);
226 /* Save the information describing this change. */
227 if (num_changes
>= changes_allocated
)
229 if (changes_allocated
== 0)
230 /* This value allows for repeated substitutions inside complex
231 indexed addresses, or changes in up to 5 insns. */
232 changes_allocated
= MAX_RECOG_OPERANDS
* 5;
234 changes_allocated
*= 2;
236 changes
= XRESIZEVEC (change_t
, changes
, changes_allocated
);
239 changes
[num_changes
].object
= object
;
240 changes
[num_changes
].loc
= loc
;
241 changes
[num_changes
].old
= old
;
242 changes
[num_changes
].unshare
= unshare
;
244 if (object
&& !MEM_P (object
))
246 /* Set INSN_CODE to force rerecognition of insn. Save old code in
248 changes
[num_changes
].old_code
= INSN_CODE (object
);
249 INSN_CODE (object
) = -1;
254 /* If we are making a group of changes, return 1. Otherwise, validate the
255 change group we made. */
260 return apply_change_group ();
263 /* Wrapper for validate_change_1 without the UNSHARE argument defaulting
267 validate_change (rtx object
, rtx
*loc
, rtx new_rtx
, bool in_group
)
269 return validate_change_1 (object
, loc
, new_rtx
, in_group
, false);
272 /* Wrapper for validate_change_1 without the UNSHARE argument defaulting
276 validate_unshare_change (rtx object
, rtx
*loc
, rtx new_rtx
, bool in_group
)
278 return validate_change_1 (object
, loc
, new_rtx
, in_group
, true);
282 /* Keep X canonicalized if some changes have made it non-canonical; only
283 modifies the operands of X, not (for example) its code. Simplifications
284 are not the job of this routine.
286 Return true if anything was changed. */
288 canonicalize_change_group (rtx_insn
*insn
, rtx x
)
290 if (COMMUTATIVE_P (x
)
291 && swap_commutative_operands_p (XEXP (x
, 0), XEXP (x
, 1)))
293 /* Oops, the caller has made X no longer canonical.
294 Let's redo the changes in the correct order. */
295 rtx tem
= XEXP (x
, 0);
296 validate_unshare_change (insn
, &XEXP (x
, 0), XEXP (x
, 1), 1);
297 validate_unshare_change (insn
, &XEXP (x
, 1), tem
, 1);
305 /* This subroutine of apply_change_group verifies whether the changes to INSN
306 were valid; i.e. whether INSN can still be recognized.
308 If IN_GROUP is true clobbers which have to be added in order to
309 match the instructions will be added to the current change group.
310 Otherwise the changes will take effect immediately. */
313 insn_invalid_p (rtx_insn
*insn
, bool in_group
)
315 rtx pat
= PATTERN (insn
);
316 int num_clobbers
= 0;
317 /* If we are before reload and the pattern is a SET, see if we can add
319 int icode
= recog (pat
, insn
,
320 (GET_CODE (pat
) == SET
321 && ! reload_completed
322 && ! reload_in_progress
)
323 ? &num_clobbers
: 0);
324 int is_asm
= icode
< 0 && asm_noperands (PATTERN (insn
)) >= 0;
327 /* If this is an asm and the operand aren't legal, then fail. Likewise if
328 this is not an asm and the insn wasn't recognized. */
329 if ((is_asm
&& ! check_asm_operands (PATTERN (insn
)))
330 || (!is_asm
&& icode
< 0))
333 /* If we have to add CLOBBERs, fail if we have to add ones that reference
334 hard registers since our callers can't know if they are live or not.
335 Otherwise, add them. */
336 if (num_clobbers
> 0)
340 if (added_clobbers_hard_reg_p (icode
))
343 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (num_clobbers
+ 1));
344 XVECEXP (newpat
, 0, 0) = pat
;
345 add_clobbers (newpat
, icode
);
347 validate_change (insn
, &PATTERN (insn
), newpat
, 1);
349 PATTERN (insn
) = pat
= newpat
;
352 /* After reload, verify that all constraints are satisfied. */
353 if (reload_completed
)
357 if (! constrain_operands (1, get_preferred_alternatives (insn
)))
361 INSN_CODE (insn
) = icode
;
365 /* Return number of changes made and not validated yet. */
367 num_changes_pending (void)
372 /* Tentatively apply the changes numbered NUM and up.
373 Return 1 if all changes are valid, zero otherwise. */
376 verify_changes (int num
)
379 rtx last_validated
= NULL_RTX
;
381 /* The changes have been applied and all INSN_CODEs have been reset to force
384 The changes are valid if we aren't given an object, or if we are
385 given a MEM and it still is a valid address, or if this is in insn
386 and it is recognized. In the latter case, if reload has completed,
387 we also require that the operands meet the constraints for
390 for (i
= num
; i
< num_changes
; i
++)
392 rtx object
= changes
[i
].object
;
394 /* If there is no object to test or if it is the same as the one we
395 already tested, ignore it. */
396 if (object
== 0 || object
== last_validated
)
401 if (! memory_address_addr_space_p (GET_MODE (object
),
403 MEM_ADDR_SPACE (object
)))
406 else if (/* changes[i].old might be zero, e.g. when putting a
407 REG_FRAME_RELATED_EXPR into a previously empty list. */
409 && REG_P (changes
[i
].old
)
410 && asm_noperands (PATTERN (object
)) > 0
411 && REG_EXPR (changes
[i
].old
) != NULL_TREE
412 && HAS_DECL_ASSEMBLER_NAME_P (REG_EXPR (changes
[i
].old
))
413 && DECL_ASSEMBLER_NAME_SET_P (REG_EXPR (changes
[i
].old
))
414 && DECL_REGISTER (REG_EXPR (changes
[i
].old
)))
416 /* Don't allow changes of hard register operands to inline
417 assemblies if they have been defined as register asm ("x"). */
420 else if (DEBUG_INSN_P (object
))
422 else if (insn_invalid_p (as_a
<rtx_insn
*> (object
), true))
424 rtx pat
= PATTERN (object
);
426 /* Perhaps we couldn't recognize the insn because there were
427 extra CLOBBERs at the end. If so, try to re-recognize
428 without the last CLOBBER (later iterations will cause each of
429 them to be eliminated, in turn). But don't do this if we
430 have an ASM_OPERAND. */
431 if (GET_CODE (pat
) == PARALLEL
432 && GET_CODE (XVECEXP (pat
, 0, XVECLEN (pat
, 0) - 1)) == CLOBBER
433 && asm_noperands (PATTERN (object
)) < 0)
437 if (XVECLEN (pat
, 0) == 2)
438 newpat
= XVECEXP (pat
, 0, 0);
444 = gen_rtx_PARALLEL (VOIDmode
,
445 rtvec_alloc (XVECLEN (pat
, 0) - 1));
446 for (j
= 0; j
< XVECLEN (newpat
, 0); j
++)
447 XVECEXP (newpat
, 0, j
) = XVECEXP (pat
, 0, j
);
450 /* Add a new change to this group to replace the pattern
451 with this new pattern. Then consider this change
452 as having succeeded. The change we added will
453 cause the entire call to fail if things remain invalid.
455 Note that this can lose if a later change than the one
456 we are processing specified &XVECEXP (PATTERN (object), 0, X)
457 but this shouldn't occur. */
459 validate_change (object
, &PATTERN (object
), newpat
, 1);
462 else if (GET_CODE (pat
) == USE
|| GET_CODE (pat
) == CLOBBER
463 || GET_CODE (pat
) == VAR_LOCATION
)
464 /* If this insn is a CLOBBER or USE, it is always valid, but is
470 last_validated
= object
;
473 return (i
== num_changes
);
476 /* A group of changes has previously been issued with validate_change
477 and verified with verify_changes. Call df_insn_rescan for each of
478 the insn changed and clear num_changes. */
481 confirm_change_group (void)
484 rtx last_object
= NULL
;
486 for (i
= 0; i
< num_changes
; i
++)
488 rtx object
= changes
[i
].object
;
490 if (changes
[i
].unshare
)
491 *changes
[i
].loc
= copy_rtx (*changes
[i
].loc
);
493 /* Avoid unnecessary rescanning when multiple changes to same instruction
497 if (object
!= last_object
&& last_object
&& INSN_P (last_object
))
498 df_insn_rescan (as_a
<rtx_insn
*> (last_object
));
499 last_object
= object
;
503 if (last_object
&& INSN_P (last_object
))
504 df_insn_rescan (as_a
<rtx_insn
*> (last_object
));
508 /* Apply a group of changes previously issued with `validate_change'.
509 If all changes are valid, call confirm_change_group and return 1,
510 otherwise, call cancel_changes and return 0. */
513 apply_change_group (void)
515 if (verify_changes (0))
517 confirm_change_group ();
528 /* Return the number of changes so far in the current group. */
531 num_validated_changes (void)
536 /* Retract the changes numbered NUM and up. */
539 cancel_changes (int num
)
543 /* Back out all the changes. Do this in the opposite order in which
545 for (i
= num_changes
- 1; i
>= num
; i
--)
547 *changes
[i
].loc
= changes
[i
].old
;
548 if (changes
[i
].object
&& !MEM_P (changes
[i
].object
))
549 INSN_CODE (changes
[i
].object
) = changes
[i
].old_code
;
554 /* Reduce conditional compilation elsewhere. */
555 /* A subroutine of validate_replace_rtx_1 that tries to simplify the resulting
559 simplify_while_replacing (rtx
*loc
, rtx to
, rtx_insn
*object
,
560 machine_mode op0_mode
)
563 enum rtx_code code
= GET_CODE (x
);
564 rtx new_rtx
= NULL_RTX
;
565 scalar_int_mode is_mode
;
567 if (SWAPPABLE_OPERANDS_P (x
)
568 && swap_commutative_operands_p (XEXP (x
, 0), XEXP (x
, 1)))
570 validate_unshare_change (object
, loc
,
571 gen_rtx_fmt_ee (COMMUTATIVE_ARITH_P (x
) ? code
572 : swap_condition (code
),
573 GET_MODE (x
), XEXP (x
, 1),
579 /* Canonicalize arithmetics with all constant operands. */
580 switch (GET_RTX_CLASS (code
))
583 if (CONSTANT_P (XEXP (x
, 0)))
584 new_rtx
= simplify_unary_operation (code
, GET_MODE (x
), XEXP (x
, 0),
589 if (CONSTANT_P (XEXP (x
, 0)) && CONSTANT_P (XEXP (x
, 1)))
590 new_rtx
= simplify_binary_operation (code
, GET_MODE (x
), XEXP (x
, 0),
594 case RTX_COMM_COMPARE
:
595 if (CONSTANT_P (XEXP (x
, 0)) && CONSTANT_P (XEXP (x
, 1)))
596 new_rtx
= simplify_relational_operation (code
, GET_MODE (x
), op0_mode
,
597 XEXP (x
, 0), XEXP (x
, 1));
604 validate_change (object
, loc
, new_rtx
, 1);
611 /* If we have a PLUS whose second operand is now a CONST_INT, use
612 simplify_gen_binary to try to simplify it.
613 ??? We may want later to remove this, once simplification is
614 separated from this function. */
615 if (CONST_INT_P (XEXP (x
, 1)) && XEXP (x
, 1) == to
)
616 validate_change (object
, loc
,
618 (PLUS
, GET_MODE (x
), XEXP (x
, 0), XEXP (x
, 1)), 1);
621 if (CONST_SCALAR_INT_P (XEXP (x
, 1)))
622 validate_change (object
, loc
,
624 (PLUS
, GET_MODE (x
), XEXP (x
, 0),
625 simplify_gen_unary (NEG
,
626 GET_MODE (x
), XEXP (x
, 1),
631 if (GET_MODE (XEXP (x
, 0)) == VOIDmode
)
633 new_rtx
= simplify_gen_unary (code
, GET_MODE (x
), XEXP (x
, 0),
635 /* If any of the above failed, substitute in something that
636 we know won't be recognized. */
638 new_rtx
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
639 validate_change (object
, loc
, new_rtx
, 1);
643 /* All subregs possible to simplify should be simplified. */
644 new_rtx
= simplify_subreg (GET_MODE (x
), SUBREG_REG (x
), op0_mode
,
647 /* Subregs of VOIDmode operands are incorrect. */
648 if (!new_rtx
&& GET_MODE (SUBREG_REG (x
)) == VOIDmode
)
649 new_rtx
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
651 validate_change (object
, loc
, new_rtx
, 1);
655 /* If we are replacing a register with memory, try to change the memory
656 to be the mode required for memory in extract operations (this isn't
657 likely to be an insertion operation; if it was, nothing bad will
658 happen, we might just fail in some cases). */
660 if (MEM_P (XEXP (x
, 0))
661 && is_a
<scalar_int_mode
> (GET_MODE (XEXP (x
, 0)), &is_mode
)
662 && CONST_INT_P (XEXP (x
, 1))
663 && CONST_INT_P (XEXP (x
, 2))
664 && !mode_dependent_address_p (XEXP (XEXP (x
, 0), 0),
665 MEM_ADDR_SPACE (XEXP (x
, 0)))
666 && !MEM_VOLATILE_P (XEXP (x
, 0)))
668 int pos
= INTVAL (XEXP (x
, 2));
669 machine_mode new_mode
= is_mode
;
670 if (GET_CODE (x
) == ZERO_EXTRACT
&& targetm
.have_extzv ())
671 new_mode
= insn_data
[targetm
.code_for_extzv
].operand
[1].mode
;
672 else if (GET_CODE (x
) == SIGN_EXTRACT
&& targetm
.have_extv ())
673 new_mode
= insn_data
[targetm
.code_for_extv
].operand
[1].mode
;
674 scalar_int_mode wanted_mode
= (new_mode
== VOIDmode
676 : as_a
<scalar_int_mode
> (new_mode
));
678 /* If we have a narrower mode, we can do something. */
679 if (GET_MODE_SIZE (wanted_mode
) < GET_MODE_SIZE (is_mode
))
681 int offset
= pos
/ BITS_PER_UNIT
;
684 /* If the bytes and bits are counted differently, we
685 must adjust the offset. */
686 if (BYTES_BIG_ENDIAN
!= BITS_BIG_ENDIAN
)
688 (GET_MODE_SIZE (is_mode
) - GET_MODE_SIZE (wanted_mode
) -
691 gcc_assert (GET_MODE_PRECISION (wanted_mode
)
692 == GET_MODE_BITSIZE (wanted_mode
));
693 pos
%= GET_MODE_BITSIZE (wanted_mode
);
695 newmem
= adjust_address_nv (XEXP (x
, 0), wanted_mode
, offset
);
697 validate_change (object
, &XEXP (x
, 2), GEN_INT (pos
), 1);
698 validate_change (object
, &XEXP (x
, 0), newmem
, 1);
709 /* Replace every occurrence of FROM in X with TO. Mark each change with
710 validate_change passing OBJECT. */
713 validate_replace_rtx_1 (rtx
*loc
, rtx from
, rtx to
, rtx_insn
*object
,
720 machine_mode op0_mode
= VOIDmode
;
721 int prev_changes
= num_changes
;
727 fmt
= GET_RTX_FORMAT (code
);
729 op0_mode
= GET_MODE (XEXP (x
, 0));
731 /* X matches FROM if it is the same rtx or they are both referring to the
732 same register in the same mode. Avoid calling rtx_equal_p unless the
733 operands look similar. */
736 || (REG_P (x
) && REG_P (from
)
737 && GET_MODE (x
) == GET_MODE (from
)
738 && REGNO (x
) == REGNO (from
))
739 || (GET_CODE (x
) == GET_CODE (from
) && GET_MODE (x
) == GET_MODE (from
)
740 && rtx_equal_p (x
, from
)))
742 validate_unshare_change (object
, loc
, to
, 1);
746 /* Call ourself recursively to perform the replacements.
747 We must not replace inside already replaced expression, otherwise we
748 get infinite recursion for replacements like (reg X)->(subreg (reg X))
749 so we must special case shared ASM_OPERANDS. */
751 if (GET_CODE (x
) == PARALLEL
)
753 for (j
= XVECLEN (x
, 0) - 1; j
>= 0; j
--)
755 if (j
&& GET_CODE (XVECEXP (x
, 0, j
)) == SET
756 && GET_CODE (SET_SRC (XVECEXP (x
, 0, j
))) == ASM_OPERANDS
)
758 /* Verify that operands are really shared. */
759 gcc_assert (ASM_OPERANDS_INPUT_VEC (SET_SRC (XVECEXP (x
, 0, 0)))
760 == ASM_OPERANDS_INPUT_VEC (SET_SRC (XVECEXP
762 validate_replace_rtx_1 (&SET_DEST (XVECEXP (x
, 0, j
)),
763 from
, to
, object
, simplify
);
766 validate_replace_rtx_1 (&XVECEXP (x
, 0, j
), from
, to
, object
,
771 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
774 validate_replace_rtx_1 (&XEXP (x
, i
), from
, to
, object
, simplify
);
775 else if (fmt
[i
] == 'E')
776 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
777 validate_replace_rtx_1 (&XVECEXP (x
, i
, j
), from
, to
, object
,
781 /* If we didn't substitute, there is nothing more to do. */
782 if (num_changes
== prev_changes
)
785 /* ??? The regmove is no more, so is this aberration still necessary? */
786 /* Allow substituted expression to have different mode. This is used by
787 regmove to change mode of pseudo register. */
788 if (fmt
[0] == 'e' && GET_MODE (XEXP (x
, 0)) != VOIDmode
)
789 op0_mode
= GET_MODE (XEXP (x
, 0));
791 /* Do changes needed to keep rtx consistent. Don't do any other
792 simplifications, as it is not our job. */
794 simplify_while_replacing (loc
, to
, object
, op0_mode
);
797 /* Try replacing every occurrence of FROM in subexpression LOC of INSN
798 with TO. After all changes have been made, validate by seeing
799 if INSN is still valid. */
802 validate_replace_rtx_subexp (rtx from
, rtx to
, rtx_insn
*insn
, rtx
*loc
)
804 validate_replace_rtx_1 (loc
, from
, to
, insn
, true);
805 return apply_change_group ();
808 /* Try replacing every occurrence of FROM in INSN with TO. After all
809 changes have been made, validate by seeing if INSN is still valid. */
812 validate_replace_rtx (rtx from
, rtx to
, rtx_insn
*insn
)
814 validate_replace_rtx_1 (&PATTERN (insn
), from
, to
, insn
, true);
815 return apply_change_group ();
818 /* Try replacing every occurrence of FROM in WHERE with TO. Assume that WHERE
819 is a part of INSN. After all changes have been made, validate by seeing if
821 validate_replace_rtx (from, to, insn) is equivalent to
822 validate_replace_rtx_part (from, to, &PATTERN (insn), insn). */
825 validate_replace_rtx_part (rtx from
, rtx to
, rtx
*where
, rtx_insn
*insn
)
827 validate_replace_rtx_1 (where
, from
, to
, insn
, true);
828 return apply_change_group ();
831 /* Same as above, but do not simplify rtx afterwards. */
833 validate_replace_rtx_part_nosimplify (rtx from
, rtx to
, rtx
*where
,
836 validate_replace_rtx_1 (where
, from
, to
, insn
, false);
837 return apply_change_group ();
841 /* Try replacing every occurrence of FROM in INSN with TO. This also
842 will replace in REG_EQUAL and REG_EQUIV notes. */
845 validate_replace_rtx_group (rtx from
, rtx to
, rtx_insn
*insn
)
848 validate_replace_rtx_1 (&PATTERN (insn
), from
, to
, insn
, true);
849 for (note
= REG_NOTES (insn
); note
; note
= XEXP (note
, 1))
850 if (REG_NOTE_KIND (note
) == REG_EQUAL
851 || REG_NOTE_KIND (note
) == REG_EQUIV
)
852 validate_replace_rtx_1 (&XEXP (note
, 0), from
, to
, insn
, true);
855 /* Function called by note_uses to replace used subexpressions. */
856 struct validate_replace_src_data
858 rtx from
; /* Old RTX */
859 rtx to
; /* New RTX */
860 rtx_insn
*insn
; /* Insn in which substitution is occurring. */
864 validate_replace_src_1 (rtx
*x
, void *data
)
866 struct validate_replace_src_data
*d
867 = (struct validate_replace_src_data
*) data
;
869 validate_replace_rtx_1 (x
, d
->from
, d
->to
, d
->insn
, true);
872 /* Try replacing every occurrence of FROM in INSN with TO, avoiding
876 validate_replace_src_group (rtx from
, rtx to
, rtx_insn
*insn
)
878 struct validate_replace_src_data d
;
883 note_uses (&PATTERN (insn
), validate_replace_src_1
, &d
);
886 /* Try simplify INSN.
887 Invoke simplify_rtx () on every SET_SRC and SET_DEST inside the INSN's
888 pattern and return true if something was simplified. */
891 validate_simplify_insn (rtx_insn
*insn
)
897 pat
= PATTERN (insn
);
899 if (GET_CODE (pat
) == SET
)
901 newpat
= simplify_rtx (SET_SRC (pat
));
902 if (newpat
&& !rtx_equal_p (SET_SRC (pat
), newpat
))
903 validate_change (insn
, &SET_SRC (pat
), newpat
, 1);
904 newpat
= simplify_rtx (SET_DEST (pat
));
905 if (newpat
&& !rtx_equal_p (SET_DEST (pat
), newpat
))
906 validate_change (insn
, &SET_DEST (pat
), newpat
, 1);
908 else if (GET_CODE (pat
) == PARALLEL
)
909 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
911 rtx s
= XVECEXP (pat
, 0, i
);
913 if (GET_CODE (XVECEXP (pat
, 0, i
)) == SET
)
915 newpat
= simplify_rtx (SET_SRC (s
));
916 if (newpat
&& !rtx_equal_p (SET_SRC (s
), newpat
))
917 validate_change (insn
, &SET_SRC (s
), newpat
, 1);
918 newpat
= simplify_rtx (SET_DEST (s
));
919 if (newpat
&& !rtx_equal_p (SET_DEST (s
), newpat
))
920 validate_change (insn
, &SET_DEST (s
), newpat
, 1);
923 return ((num_changes_pending () > 0) && (apply_change_group () > 0));
926 /* Return 1 if OP is a valid general operand for machine mode MODE.
927 This is either a register reference, a memory reference,
928 or a constant. In the case of a memory reference, the address
929 is checked for general validity for the target machine.
931 Register and memory references must have mode MODE in order to be valid,
932 but some constants have no machine mode and are valid for any mode.
934 If MODE is VOIDmode, OP is checked for validity for whatever mode
937 The main use of this function is as a predicate in match_operand
938 expressions in the machine description. */
941 general_operand (rtx op
, machine_mode mode
)
943 enum rtx_code code
= GET_CODE (op
);
945 if (mode
== VOIDmode
)
946 mode
= GET_MODE (op
);
948 /* Don't accept CONST_INT or anything similar
949 if the caller wants something floating. */
950 if (GET_MODE (op
) == VOIDmode
&& mode
!= VOIDmode
951 && GET_MODE_CLASS (mode
) != MODE_INT
952 && GET_MODE_CLASS (mode
) != MODE_PARTIAL_INT
)
957 && trunc_int_for_mode (INTVAL (op
), mode
) != INTVAL (op
))
961 return ((GET_MODE (op
) == VOIDmode
|| GET_MODE (op
) == mode
963 && (! flag_pic
|| LEGITIMATE_PIC_OPERAND_P (op
))
964 && targetm
.legitimate_constant_p (mode
== VOIDmode
968 /* Except for certain constants with VOIDmode, already checked for,
969 OP's mode must match MODE if MODE specifies a mode. */
971 if (GET_MODE (op
) != mode
)
976 rtx sub
= SUBREG_REG (op
);
978 #ifdef INSN_SCHEDULING
979 /* On machines that have insn scheduling, we want all memory
980 reference to be explicit, so outlaw paradoxical SUBREGs.
981 However, we must allow them after reload so that they can
982 get cleaned up by cleanup_subreg_operands. */
983 if (!reload_completed
&& MEM_P (sub
)
984 && paradoxical_subreg_p (op
))
987 /* Avoid memories with nonzero SUBREG_BYTE, as offsetting the memory
988 may result in incorrect reference. We should simplify all valid
989 subregs of MEM anyway. But allow this after reload because we
990 might be called from cleanup_subreg_operands.
992 ??? This is a kludge. */
993 if (!reload_completed
994 && maybe_ne (SUBREG_BYTE (op
), 0)
999 && REGNO (sub
) < FIRST_PSEUDO_REGISTER
1000 && !REG_CAN_CHANGE_MODE_P (REGNO (sub
), GET_MODE (sub
), mode
)
1001 && GET_MODE_CLASS (GET_MODE (sub
)) != MODE_COMPLEX_INT
1002 && GET_MODE_CLASS (GET_MODE (sub
)) != MODE_COMPLEX_FLOAT
1003 /* LRA can generate some invalid SUBREGS just for matched
1004 operand reload presentation. LRA needs to treat them as
1006 && ! LRA_SUBREG_P (op
))
1009 /* FLOAT_MODE subregs can't be paradoxical. Combine will occasionally
1010 create such rtl, and we must reject it. */
1011 if (SCALAR_FLOAT_MODE_P (GET_MODE (op
))
1012 /* LRA can use subreg to store a floating point value in an
1013 integer mode. Although the floating point and the
1014 integer modes need the same number of hard registers, the
1015 size of floating point mode can be less than the integer
1017 && ! lra_in_progress
1018 && paradoxical_subreg_p (op
))
1022 code
= GET_CODE (op
);
1026 return (REGNO (op
) >= FIRST_PSEUDO_REGISTER
1027 || in_hard_reg_set_p (operand_reg_set
, GET_MODE (op
), REGNO (op
)));
1031 rtx y
= XEXP (op
, 0);
1033 if (! volatile_ok
&& MEM_VOLATILE_P (op
))
1036 /* Use the mem's mode, since it will be reloaded thus. LRA can
1037 generate move insn with invalid addresses which is made valid
1038 and efficiently calculated by LRA through further numerous
1041 || memory_address_addr_space_p (GET_MODE (op
), y
, MEM_ADDR_SPACE (op
)))
1048 /* Return 1 if OP is a valid memory address for a memory reference
1051 The main use of this function is as a predicate in match_operand
1052 expressions in the machine description. */
1055 address_operand (rtx op
, machine_mode mode
)
1057 /* Wrong mode for an address expr. */
1058 if (GET_MODE (op
) != VOIDmode
1059 && ! SCALAR_INT_MODE_P (GET_MODE (op
)))
1062 return memory_address_p (mode
, op
);
1065 /* Return 1 if OP is a register reference of mode MODE.
1066 If MODE is VOIDmode, accept a register in any mode.
1068 The main use of this function is as a predicate in match_operand
1069 expressions in the machine description. */
1072 register_operand (rtx op
, machine_mode mode
)
1074 if (GET_CODE (op
) == SUBREG
)
1076 rtx sub
= SUBREG_REG (op
);
1078 /* Before reload, we can allow (SUBREG (MEM...)) as a register operand
1079 because it is guaranteed to be reloaded into one.
1080 Just make sure the MEM is valid in itself.
1081 (Ideally, (SUBREG (MEM)...) should not exist after reload,
1082 but currently it does result from (SUBREG (REG)...) where the
1083 reg went on the stack.) */
1084 if (!REG_P (sub
) && (reload_completed
|| !MEM_P (sub
)))
1087 else if (!REG_P (op
))
1089 return general_operand (op
, mode
);
1092 /* Return 1 for a register in Pmode; ignore the tested mode. */
1095 pmode_register_operand (rtx op
, machine_mode mode ATTRIBUTE_UNUSED
)
1097 return register_operand (op
, Pmode
);
1100 /* Return 1 if OP should match a MATCH_SCRATCH, i.e., if it is a SCRATCH
1101 or a hard register. */
1104 scratch_operand (rtx op
, machine_mode mode
)
1106 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
1109 return (GET_CODE (op
) == SCRATCH
1112 || (REGNO (op
) < FIRST_PSEUDO_REGISTER
1113 && REGNO_REG_CLASS (REGNO (op
)) != NO_REGS
))));
1116 /* Return 1 if OP is a valid immediate operand for mode MODE.
1118 The main use of this function is as a predicate in match_operand
1119 expressions in the machine description. */
1122 immediate_operand (rtx op
, machine_mode mode
)
1124 /* Don't accept CONST_INT or anything similar
1125 if the caller wants something floating. */
1126 if (GET_MODE (op
) == VOIDmode
&& mode
!= VOIDmode
1127 && GET_MODE_CLASS (mode
) != MODE_INT
1128 && GET_MODE_CLASS (mode
) != MODE_PARTIAL_INT
)
1131 if (CONST_INT_P (op
)
1133 && trunc_int_for_mode (INTVAL (op
), mode
) != INTVAL (op
))
1136 return (CONSTANT_P (op
)
1137 && (GET_MODE (op
) == mode
|| mode
== VOIDmode
1138 || GET_MODE (op
) == VOIDmode
)
1139 && (! flag_pic
|| LEGITIMATE_PIC_OPERAND_P (op
))
1140 && targetm
.legitimate_constant_p (mode
== VOIDmode
1145 /* Returns 1 if OP is an operand that is a CONST_INT of mode MODE. */
1148 const_int_operand (rtx op
, machine_mode mode
)
1150 if (!CONST_INT_P (op
))
1153 if (mode
!= VOIDmode
1154 && trunc_int_for_mode (INTVAL (op
), mode
) != INTVAL (op
))
1160 #if TARGET_SUPPORTS_WIDE_INT
1161 /* Returns 1 if OP is an operand that is a CONST_INT or CONST_WIDE_INT
1164 const_scalar_int_operand (rtx op
, machine_mode mode
)
1166 if (!CONST_SCALAR_INT_P (op
))
1169 if (CONST_INT_P (op
))
1170 return const_int_operand (op
, mode
);
1172 if (mode
!= VOIDmode
)
1174 scalar_int_mode int_mode
= as_a
<scalar_int_mode
> (mode
);
1175 int prec
= GET_MODE_PRECISION (int_mode
);
1176 int bitsize
= GET_MODE_BITSIZE (int_mode
);
1178 if (CONST_WIDE_INT_NUNITS (op
) * HOST_BITS_PER_WIDE_INT
> bitsize
)
1181 if (prec
== bitsize
)
1185 /* Multiword partial int. */
1187 = CONST_WIDE_INT_ELT (op
, CONST_WIDE_INT_NUNITS (op
) - 1);
1188 return (sext_hwi (x
, prec
& (HOST_BITS_PER_WIDE_INT
- 1)) == x
);
1194 /* Returns 1 if OP is an operand that is a constant integer or constant
1195 floating-point number of MODE. */
1198 const_double_operand (rtx op
, machine_mode mode
)
1200 return (GET_CODE (op
) == CONST_DOUBLE
)
1201 && (GET_MODE (op
) == mode
|| mode
== VOIDmode
);
1204 /* Returns 1 if OP is an operand that is a constant integer or constant
1205 floating-point number of MODE. */
1208 const_double_operand (rtx op
, machine_mode mode
)
1210 /* Don't accept CONST_INT or anything similar
1211 if the caller wants something floating. */
1212 if (GET_MODE (op
) == VOIDmode
&& mode
!= VOIDmode
1213 && GET_MODE_CLASS (mode
) != MODE_INT
1214 && GET_MODE_CLASS (mode
) != MODE_PARTIAL_INT
)
1217 return ((CONST_DOUBLE_P (op
) || CONST_INT_P (op
))
1218 && (mode
== VOIDmode
|| GET_MODE (op
) == mode
1219 || GET_MODE (op
) == VOIDmode
));
1222 /* Return 1 if OP is a general operand that is not an immediate
1223 operand of mode MODE. */
1226 nonimmediate_operand (rtx op
, machine_mode mode
)
1228 return (general_operand (op
, mode
) && ! CONSTANT_P (op
));
1231 /* Return 1 if OP is a register reference or immediate value of mode MODE. */
1234 nonmemory_operand (rtx op
, machine_mode mode
)
1236 if (CONSTANT_P (op
))
1237 return immediate_operand (op
, mode
);
1238 return register_operand (op
, mode
);
1241 /* Return 1 if OP is a valid operand that stands for pushing a
1242 value of mode MODE onto the stack.
1244 The main use of this function is as a predicate in match_operand
1245 expressions in the machine description. */
1248 push_operand (rtx op
, machine_mode mode
)
1253 if (mode
!= VOIDmode
&& GET_MODE (op
) != mode
)
1256 poly_int64 rounded_size
= GET_MODE_SIZE (mode
);
1258 #ifdef PUSH_ROUNDING
1259 rounded_size
= PUSH_ROUNDING (MACRO_INT (rounded_size
));
1264 if (known_eq (rounded_size
, GET_MODE_SIZE (mode
)))
1266 if (GET_CODE (op
) != STACK_PUSH_CODE
)
1272 if (GET_CODE (op
) != PRE_MODIFY
1273 || GET_CODE (XEXP (op
, 1)) != PLUS
1274 || XEXP (XEXP (op
, 1), 0) != XEXP (op
, 0)
1275 || !poly_int_rtx_p (XEXP (XEXP (op
, 1), 1), &offset
)
1276 || (STACK_GROWS_DOWNWARD
1277 ? maybe_ne (offset
, -rounded_size
)
1278 : maybe_ne (offset
, rounded_size
)))
1282 return XEXP (op
, 0) == stack_pointer_rtx
;
1285 /* Return 1 if OP is a valid operand that stands for popping a
1286 value of mode MODE off the stack.
1288 The main use of this function is as a predicate in match_operand
1289 expressions in the machine description. */
1292 pop_operand (rtx op
, machine_mode mode
)
1297 if (mode
!= VOIDmode
&& GET_MODE (op
) != mode
)
1302 if (GET_CODE (op
) != STACK_POP_CODE
)
1305 return XEXP (op
, 0) == stack_pointer_rtx
;
1308 /* Return 1 if ADDR is a valid memory address
1309 for mode MODE in address space AS. */
1312 memory_address_addr_space_p (machine_mode mode ATTRIBUTE_UNUSED
,
1313 rtx addr
, addr_space_t as
)
1315 #ifdef GO_IF_LEGITIMATE_ADDRESS
1316 gcc_assert (ADDR_SPACE_GENERIC_P (as
));
1317 GO_IF_LEGITIMATE_ADDRESS (mode
, addr
, win
);
1323 return targetm
.addr_space
.legitimate_address_p (mode
, addr
, 0, as
);
1327 /* Return 1 if OP is a valid memory reference with mode MODE,
1328 including a valid address.
1330 The main use of this function is as a predicate in match_operand
1331 expressions in the machine description. */
1334 memory_operand (rtx op
, machine_mode mode
)
1338 if (! reload_completed
)
1339 /* Note that no SUBREG is a memory operand before end of reload pass,
1340 because (SUBREG (MEM...)) forces reloading into a register. */
1341 return MEM_P (op
) && general_operand (op
, mode
);
1343 if (mode
!= VOIDmode
&& GET_MODE (op
) != mode
)
1347 if (GET_CODE (inner
) == SUBREG
)
1348 inner
= SUBREG_REG (inner
);
1350 return (MEM_P (inner
) && general_operand (op
, mode
));
1353 /* Return 1 if OP is a valid indirect memory reference with mode MODE;
1354 that is, a memory reference whose address is a general_operand. */
1357 indirect_operand (rtx op
, machine_mode mode
)
1359 /* Before reload, a SUBREG isn't in memory (see memory_operand, above). */
1360 if (! reload_completed
1361 && GET_CODE (op
) == SUBREG
&& MEM_P (SUBREG_REG (op
)))
1363 if (mode
!= VOIDmode
&& GET_MODE (op
) != mode
)
1366 /* The only way that we can have a general_operand as the resulting
1367 address is if OFFSET is zero and the address already is an operand
1368 or if the address is (plus Y (const_int -OFFSET)) and Y is an
1371 rtx addr
= strip_offset (XEXP (SUBREG_REG (op
), 0), &offset
);
1372 return (known_eq (offset
+ SUBREG_BYTE (op
), 0)
1373 && general_operand (addr
, Pmode
));
1377 && memory_operand (op
, mode
)
1378 && general_operand (XEXP (op
, 0), Pmode
));
1381 /* Return 1 if this is an ordered comparison operator (not including
1382 ORDERED and UNORDERED). */
1385 ordered_comparison_operator (rtx op
, machine_mode mode
)
1387 if (mode
!= VOIDmode
&& GET_MODE (op
) != mode
)
1389 switch (GET_CODE (op
))
1407 /* Return 1 if this is a comparison operator. This allows the use of
1408 MATCH_OPERATOR to recognize all the branch insns. */
1411 comparison_operator (rtx op
, machine_mode mode
)
1413 return ((mode
== VOIDmode
|| GET_MODE (op
) == mode
)
1414 && COMPARISON_P (op
));
1417 /* If BODY is an insn body that uses ASM_OPERANDS, return it. */
1420 extract_asm_operands (rtx body
)
1423 switch (GET_CODE (body
))
1429 /* Single output operand: BODY is (set OUTPUT (asm_operands ...)). */
1430 tmp
= SET_SRC (body
);
1431 if (GET_CODE (tmp
) == ASM_OPERANDS
)
1436 tmp
= XVECEXP (body
, 0, 0);
1437 if (GET_CODE (tmp
) == ASM_OPERANDS
)
1439 if (GET_CODE (tmp
) == SET
)
1441 tmp
= SET_SRC (tmp
);
1442 if (GET_CODE (tmp
) == ASM_OPERANDS
)
1453 /* If BODY is an insn body that uses ASM_OPERANDS,
1454 return the number of operands (both input and output) in the insn.
1455 If BODY is an insn body that uses ASM_INPUT with CLOBBERS in PARALLEL,
1457 Otherwise return -1. */
1460 asm_noperands (const_rtx body
)
1462 rtx asm_op
= extract_asm_operands (CONST_CAST_RTX (body
));
1467 if (GET_CODE (body
) == PARALLEL
&& XVECLEN (body
, 0) >= 2
1468 && GET_CODE (XVECEXP (body
, 0, 0)) == ASM_INPUT
)
1470 /* body is [(asm_input ...) (clobber (reg ...))...]. */
1471 for (i
= XVECLEN (body
, 0) - 1; i
> 0; i
--)
1472 if (GET_CODE (XVECEXP (body
, 0, i
)) != CLOBBER
)
1479 if (GET_CODE (body
) == SET
)
1481 else if (GET_CODE (body
) == PARALLEL
)
1483 if (GET_CODE (XVECEXP (body
, 0, 0)) == SET
)
1485 /* Multiple output operands, or 1 output plus some clobbers:
1487 [(set OUTPUT (asm_operands ...))... (clobber (reg ...))...]. */
1488 /* Count backwards through CLOBBERs to determine number of SETs. */
1489 for (i
= XVECLEN (body
, 0); i
> 0; i
--)
1491 if (GET_CODE (XVECEXP (body
, 0, i
- 1)) == SET
)
1493 if (GET_CODE (XVECEXP (body
, 0, i
- 1)) != CLOBBER
)
1497 /* N_SETS is now number of output operands. */
1500 /* Verify that all the SETs we have
1501 came from a single original asm_operands insn
1502 (so that invalid combinations are blocked). */
1503 for (i
= 0; i
< n_sets
; i
++)
1505 rtx elt
= XVECEXP (body
, 0, i
);
1506 if (GET_CODE (elt
) != SET
)
1508 if (GET_CODE (SET_SRC (elt
)) != ASM_OPERANDS
)
1510 /* If these ASM_OPERANDS rtx's came from different original insns
1511 then they aren't allowed together. */
1512 if (ASM_OPERANDS_INPUT_VEC (SET_SRC (elt
))
1513 != ASM_OPERANDS_INPUT_VEC (asm_op
))
1519 /* 0 outputs, but some clobbers:
1520 body is [(asm_operands ...) (clobber (reg ...))...]. */
1521 /* Make sure all the other parallel things really are clobbers. */
1522 for (i
= XVECLEN (body
, 0) - 1; i
> 0; i
--)
1523 if (GET_CODE (XVECEXP (body
, 0, i
)) != CLOBBER
)
1528 return (ASM_OPERANDS_INPUT_LENGTH (asm_op
)
1529 + ASM_OPERANDS_LABEL_LENGTH (asm_op
) + n_sets
);
1532 /* Assuming BODY is an insn body that uses ASM_OPERANDS,
1533 copy its operands (both input and output) into the vector OPERANDS,
1534 the locations of the operands within the insn into the vector OPERAND_LOCS,
1535 and the constraints for the operands into CONSTRAINTS.
1536 Write the modes of the operands into MODES.
1537 Write the location info into LOC.
1538 Return the assembler-template.
1539 If BODY is an insn body that uses ASM_INPUT with CLOBBERS in PARALLEL,
1540 return the basic assembly string.
1542 If LOC, MODES, OPERAND_LOCS, CONSTRAINTS or OPERANDS is 0,
1543 we don't store that info. */
1546 decode_asm_operands (rtx body
, rtx
*operands
, rtx
**operand_locs
,
1547 const char **constraints
, machine_mode
*modes
,
1550 int nbase
= 0, n
, i
;
1553 switch (GET_CODE (body
))
1556 /* Zero output asm: BODY is (asm_operands ...). */
1561 /* Single output asm: BODY is (set OUTPUT (asm_operands ...)). */
1562 asmop
= SET_SRC (body
);
1564 /* The output is in the SET.
1565 Its constraint is in the ASM_OPERANDS itself. */
1567 operands
[0] = SET_DEST (body
);
1569 operand_locs
[0] = &SET_DEST (body
);
1571 constraints
[0] = ASM_OPERANDS_OUTPUT_CONSTRAINT (asmop
);
1573 modes
[0] = GET_MODE (SET_DEST (body
));
1579 int nparallel
= XVECLEN (body
, 0); /* Includes CLOBBERs. */
1581 asmop
= XVECEXP (body
, 0, 0);
1582 if (GET_CODE (asmop
) == SET
)
1584 asmop
= SET_SRC (asmop
);
1586 /* At least one output, plus some CLOBBERs. The outputs are in
1587 the SETs. Their constraints are in the ASM_OPERANDS itself. */
1588 for (i
= 0; i
< nparallel
; i
++)
1590 if (GET_CODE (XVECEXP (body
, 0, i
)) == CLOBBER
)
1591 break; /* Past last SET */
1592 gcc_assert (GET_CODE (XVECEXP (body
, 0, i
)) == SET
);
1594 operands
[i
] = SET_DEST (XVECEXP (body
, 0, i
));
1596 operand_locs
[i
] = &SET_DEST (XVECEXP (body
, 0, i
));
1598 constraints
[i
] = XSTR (SET_SRC (XVECEXP (body
, 0, i
)), 1);
1600 modes
[i
] = GET_MODE (SET_DEST (XVECEXP (body
, 0, i
)));
1604 else if (GET_CODE (asmop
) == ASM_INPUT
)
1607 *loc
= ASM_INPUT_SOURCE_LOCATION (asmop
);
1608 return XSTR (asmop
, 0);
1617 n
= ASM_OPERANDS_INPUT_LENGTH (asmop
);
1618 for (i
= 0; i
< n
; i
++)
1621 operand_locs
[nbase
+ i
] = &ASM_OPERANDS_INPUT (asmop
, i
);
1623 operands
[nbase
+ i
] = ASM_OPERANDS_INPUT (asmop
, i
);
1625 constraints
[nbase
+ i
] = ASM_OPERANDS_INPUT_CONSTRAINT (asmop
, i
);
1627 modes
[nbase
+ i
] = ASM_OPERANDS_INPUT_MODE (asmop
, i
);
1631 n
= ASM_OPERANDS_LABEL_LENGTH (asmop
);
1632 for (i
= 0; i
< n
; i
++)
1635 operand_locs
[nbase
+ i
] = &ASM_OPERANDS_LABEL (asmop
, i
);
1637 operands
[nbase
+ i
] = ASM_OPERANDS_LABEL (asmop
, i
);
1639 constraints
[nbase
+ i
] = "";
1641 modes
[nbase
+ i
] = Pmode
;
1645 *loc
= ASM_OPERANDS_SOURCE_LOCATION (asmop
);
1647 return ASM_OPERANDS_TEMPLATE (asmop
);
1650 /* Parse inline assembly string STRING and determine which operands are
1651 referenced by % markers. For the first NOPERANDS operands, set USED[I]
1652 to true if operand I is referenced.
1654 This is intended to distinguish barrier-like asms such as:
1656 asm ("" : "=m" (...));
1658 from real references such as:
1660 asm ("sw\t$0, %0" : "=m" (...)); */
1663 get_referenced_operands (const char *string
, bool *used
,
1664 unsigned int noperands
)
1666 memset (used
, 0, sizeof (bool) * noperands
);
1667 const char *p
= string
;
1673 /* A letter followed by a digit indicates an operand number. */
1674 if (ISALPHA (p
[0]) && ISDIGIT (p
[1]))
1679 unsigned long opnum
= strtoul (p
, &endptr
, 10);
1680 if (endptr
!= p
&& opnum
< noperands
)
1694 /* Check if an asm_operand matches its constraints.
1695 Return > 0 if ok, = 0 if bad, < 0 if inconclusive. */
1698 asm_operand_ok (rtx op
, const char *constraint
, const char **constraints
)
1701 bool incdec_ok
= false;
1703 /* Use constrain_operands after reload. */
1704 gcc_assert (!reload_completed
);
1706 /* Empty constraint string is the same as "X,...,X", i.e. X for as
1707 many alternatives as required to match the other operands. */
1708 if (*constraint
== '\0')
1713 enum constraint_num cn
;
1714 char c
= *constraint
;
1722 case '0': case '1': case '2': case '3': case '4':
1723 case '5': case '6': case '7': case '8': case '9':
1724 /* If caller provided constraints pointer, look up
1725 the matching constraint. Otherwise, our caller should have
1726 given us the proper matching constraint, but we can't
1727 actually fail the check if they didn't. Indicate that
1728 results are inconclusive. */
1732 unsigned long match
;
1734 match
= strtoul (constraint
, &end
, 10);
1736 result
= asm_operand_ok (op
, constraints
[match
], NULL
);
1737 constraint
= (const char *) end
;
1743 while (ISDIGIT (*constraint
));
1749 /* The rest of the compiler assumes that reloading the address
1750 of a MEM into a register will make it fit an 'o' constraint.
1751 That is, if it sees a MEM operand for an 'o' constraint,
1752 it assumes that (mem (base-reg)) will fit.
1754 That assumption fails on targets that don't have offsettable
1755 addresses at all. We therefore need to treat 'o' asm
1756 constraints as a special case and only accept operands that
1757 are already offsettable, thus proving that at least one
1758 offsettable address exists. */
1759 case 'o': /* offsettable */
1760 if (offsettable_nonstrict_memref_p (op
))
1765 if (general_operand (op
, VOIDmode
))
1771 /* ??? Before auto-inc-dec, auto inc/dec insns are not supposed
1772 to exist, excepting those that expand_call created. Further,
1773 on some machines which do not have generalized auto inc/dec,
1774 an inc/dec is not a memory_operand.
1776 Match any memory and hope things are resolved after reload. */
1780 cn
= lookup_constraint (constraint
);
1781 switch (get_constraint_type (cn
))
1785 && reg_class_for_constraint (cn
) != NO_REGS
1786 && GET_MODE (op
) != BLKmode
1787 && register_operand (op
, VOIDmode
))
1794 && insn_const_int_ok_for_constraint (INTVAL (op
), cn
))
1799 case CT_SPECIAL_MEMORY
:
1800 /* Every memory operand can be reloaded to fit. */
1801 result
= result
|| memory_operand (op
, VOIDmode
);
1805 /* Every address operand can be reloaded to fit. */
1806 result
= result
|| address_operand (op
, VOIDmode
);
1810 result
= result
|| constraint_satisfied_p (op
, cn
);
1815 len
= CONSTRAINT_LEN (c
, constraint
);
1818 while (--len
&& *constraint
&& *constraint
!= ',');
1823 /* For operands without < or > constraints reject side-effects. */
1824 if (AUTO_INC_DEC
&& !incdec_ok
&& result
&& MEM_P (op
))
1825 switch (GET_CODE (XEXP (op
, 0)))
1841 /* Given an rtx *P, if it is a sum containing an integer constant term,
1842 return the location (type rtx *) of the pointer to that constant term.
1843 Otherwise, return a null pointer. */
1846 find_constant_term_loc (rtx
*p
)
1849 enum rtx_code code
= GET_CODE (*p
);
1851 /* If *P IS such a constant term, P is its location. */
1853 if (code
== CONST_INT
|| code
== SYMBOL_REF
|| code
== LABEL_REF
1857 /* Otherwise, if not a sum, it has no constant term. */
1859 if (GET_CODE (*p
) != PLUS
)
1862 /* If one of the summands is constant, return its location. */
1864 if (XEXP (*p
, 0) && CONSTANT_P (XEXP (*p
, 0))
1865 && XEXP (*p
, 1) && CONSTANT_P (XEXP (*p
, 1)))
1868 /* Otherwise, check each summand for containing a constant term. */
1870 if (XEXP (*p
, 0) != 0)
1872 tem
= find_constant_term_loc (&XEXP (*p
, 0));
1877 if (XEXP (*p
, 1) != 0)
1879 tem
= find_constant_term_loc (&XEXP (*p
, 1));
1887 /* Return 1 if OP is a memory reference
1888 whose address contains no side effects
1889 and remains valid after the addition
1890 of a positive integer less than the
1891 size of the object being referenced.
1893 We assume that the original address is valid and do not check it.
1895 This uses strict_memory_address_p as a subroutine, so
1896 don't use it before reload. */
1899 offsettable_memref_p (rtx op
)
1901 return ((MEM_P (op
))
1902 && offsettable_address_addr_space_p (1, GET_MODE (op
), XEXP (op
, 0),
1903 MEM_ADDR_SPACE (op
)));
1906 /* Similar, but don't require a strictly valid mem ref:
1907 consider pseudo-regs valid as index or base regs. */
1910 offsettable_nonstrict_memref_p (rtx op
)
1912 return ((MEM_P (op
))
1913 && offsettable_address_addr_space_p (0, GET_MODE (op
), XEXP (op
, 0),
1914 MEM_ADDR_SPACE (op
)));
1917 /* Return 1 if Y is a memory address which contains no side effects
1918 and would remain valid for address space AS after the addition of
1919 a positive integer less than the size of that mode.
1921 We assume that the original address is valid and do not check it.
1922 We do check that it is valid for narrower modes.
1924 If STRICTP is nonzero, we require a strictly valid address,
1925 for the sake of use in reload.c. */
1928 offsettable_address_addr_space_p (int strictp
, machine_mode mode
, rtx y
,
1931 enum rtx_code ycode
= GET_CODE (y
);
1935 int (*addressp
) (machine_mode
, rtx
, addr_space_t
) =
1936 (strictp
? strict_memory_address_addr_space_p
1937 : memory_address_addr_space_p
);
1938 poly_int64 mode_sz
= GET_MODE_SIZE (mode
);
1940 if (CONSTANT_ADDRESS_P (y
))
1943 /* Adjusting an offsettable address involves changing to a narrower mode.
1944 Make sure that's OK. */
1946 if (mode_dependent_address_p (y
, as
))
1949 machine_mode address_mode
= GET_MODE (y
);
1950 if (address_mode
== VOIDmode
)
1951 address_mode
= targetm
.addr_space
.address_mode (as
);
1952 #ifdef POINTERS_EXTEND_UNSIGNED
1953 machine_mode pointer_mode
= targetm
.addr_space
.pointer_mode (as
);
1956 /* ??? How much offset does an offsettable BLKmode reference need?
1957 Clearly that depends on the situation in which it's being used.
1958 However, the current situation in which we test 0xffffffff is
1959 less than ideal. Caveat user. */
1960 if (known_eq (mode_sz
, 0))
1961 mode_sz
= BIGGEST_ALIGNMENT
/ BITS_PER_UNIT
;
1963 /* If the expression contains a constant term,
1964 see if it remains valid when max possible offset is added. */
1966 if ((ycode
== PLUS
) && (y2
= find_constant_term_loc (&y1
)))
1971 *y2
= plus_constant (address_mode
, *y2
, mode_sz
- 1);
1972 /* Use QImode because an odd displacement may be automatically invalid
1973 for any wider mode. But it should be valid for a single byte. */
1974 good
= (*addressp
) (QImode
, y
, as
);
1976 /* In any case, restore old contents of memory. */
1981 if (GET_RTX_CLASS (ycode
) == RTX_AUTOINC
)
1984 /* The offset added here is chosen as the maximum offset that
1985 any instruction could need to add when operating on something
1986 of the specified mode. We assume that if Y and Y+c are
1987 valid addresses then so is Y+d for all 0<d<c. adjust_address will
1988 go inside a LO_SUM here, so we do so as well. */
1989 if (GET_CODE (y
) == LO_SUM
1991 && known_le (mode_sz
, GET_MODE_ALIGNMENT (mode
) / BITS_PER_UNIT
))
1992 z
= gen_rtx_LO_SUM (address_mode
, XEXP (y
, 0),
1993 plus_constant (address_mode
, XEXP (y
, 1),
1995 #ifdef POINTERS_EXTEND_UNSIGNED
1996 /* Likewise for a ZERO_EXTEND from pointer_mode. */
1997 else if (POINTERS_EXTEND_UNSIGNED
> 0
1998 && GET_CODE (y
) == ZERO_EXTEND
1999 && GET_MODE (XEXP (y
, 0)) == pointer_mode
)
2000 z
= gen_rtx_ZERO_EXTEND (address_mode
,
2001 plus_constant (pointer_mode
, XEXP (y
, 0),
2005 z
= plus_constant (address_mode
, y
, mode_sz
- 1);
2007 /* Use QImode because an odd displacement may be automatically invalid
2008 for any wider mode. But it should be valid for a single byte. */
2009 return (*addressp
) (QImode
, z
, as
);
2012 /* Return 1 if ADDR is an address-expression whose effect depends
2013 on the mode of the memory reference it is used in.
2015 ADDRSPACE is the address space associated with the address.
2017 Autoincrement addressing is a typical example of mode-dependence
2018 because the amount of the increment depends on the mode. */
2021 mode_dependent_address_p (rtx addr
, addr_space_t addrspace
)
2023 /* Auto-increment addressing with anything other than post_modify
2024 or pre_modify always introduces a mode dependency. Catch such
2025 cases now instead of deferring to the target. */
2026 if (GET_CODE (addr
) == PRE_INC
2027 || GET_CODE (addr
) == POST_INC
2028 || GET_CODE (addr
) == PRE_DEC
2029 || GET_CODE (addr
) == POST_DEC
)
2032 return targetm
.mode_dependent_address_p (addr
, addrspace
);
2035 /* Return true if boolean attribute ATTR is supported. */
2038 have_bool_attr (bool_attr attr
)
2043 return HAVE_ATTR_enabled
;
2044 case BA_PREFERRED_FOR_SIZE
:
2045 return HAVE_ATTR_enabled
|| HAVE_ATTR_preferred_for_size
;
2046 case BA_PREFERRED_FOR_SPEED
:
2047 return HAVE_ATTR_enabled
|| HAVE_ATTR_preferred_for_speed
;
2052 /* Return the value of ATTR for instruction INSN. */
2055 get_bool_attr (rtx_insn
*insn
, bool_attr attr
)
2060 return get_attr_enabled (insn
);
2061 case BA_PREFERRED_FOR_SIZE
:
2062 return get_attr_enabled (insn
) && get_attr_preferred_for_size (insn
);
2063 case BA_PREFERRED_FOR_SPEED
:
2064 return get_attr_enabled (insn
) && get_attr_preferred_for_speed (insn
);
2069 /* Like get_bool_attr_mask, but don't use the cache. */
2071 static alternative_mask
2072 get_bool_attr_mask_uncached (rtx_insn
*insn
, bool_attr attr
)
2074 /* Temporarily install enough information for get_attr_<foo> to assume
2075 that the insn operands are already cached. As above, the attribute
2076 mustn't depend on the values of operands, so we don't provide their
2077 real values here. */
2078 rtx_insn
*old_insn
= recog_data
.insn
;
2079 int old_alternative
= which_alternative
;
2081 recog_data
.insn
= insn
;
2082 alternative_mask mask
= ALL_ALTERNATIVES
;
2083 int n_alternatives
= insn_data
[INSN_CODE (insn
)].n_alternatives
;
2084 for (int i
= 0; i
< n_alternatives
; i
++)
2086 which_alternative
= i
;
2087 if (!get_bool_attr (insn
, attr
))
2088 mask
&= ~ALTERNATIVE_BIT (i
);
2091 recog_data
.insn
= old_insn
;
2092 which_alternative
= old_alternative
;
2096 /* Return the mask of operand alternatives that are allowed for INSN
2097 by boolean attribute ATTR. This mask depends only on INSN and on
2098 the current target; it does not depend on things like the values of
2101 static alternative_mask
2102 get_bool_attr_mask (rtx_insn
*insn
, bool_attr attr
)
2104 /* Quick exit for asms and for targets that don't use these attributes. */
2105 int code
= INSN_CODE (insn
);
2106 if (code
< 0 || !have_bool_attr (attr
))
2107 return ALL_ALTERNATIVES
;
2109 /* Calling get_attr_<foo> can be expensive, so cache the mask
2111 if (!this_target_recog
->x_bool_attr_masks
[code
][attr
])
2112 this_target_recog
->x_bool_attr_masks
[code
][attr
]
2113 = get_bool_attr_mask_uncached (insn
, attr
);
2114 return this_target_recog
->x_bool_attr_masks
[code
][attr
];
2117 /* Return the set of alternatives of INSN that are allowed by the current
2121 get_enabled_alternatives (rtx_insn
*insn
)
2123 return get_bool_attr_mask (insn
, BA_ENABLED
);
2126 /* Return the set of alternatives of INSN that are allowed by the current
2127 target and are preferred for the current size/speed optimization
2131 get_preferred_alternatives (rtx_insn
*insn
)
2133 if (optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn
)))
2134 return get_bool_attr_mask (insn
, BA_PREFERRED_FOR_SPEED
);
2136 return get_bool_attr_mask (insn
, BA_PREFERRED_FOR_SIZE
);
2139 /* Return the set of alternatives of INSN that are allowed by the current
2140 target and are preferred for the size/speed optimization choice
2141 associated with BB. Passing a separate BB is useful if INSN has not
2142 been emitted yet or if we are considering moving it to a different
2146 get_preferred_alternatives (rtx_insn
*insn
, basic_block bb
)
2148 if (optimize_bb_for_speed_p (bb
))
2149 return get_bool_attr_mask (insn
, BA_PREFERRED_FOR_SPEED
);
2151 return get_bool_attr_mask (insn
, BA_PREFERRED_FOR_SIZE
);
2154 /* Assert that the cached boolean attributes for INSN are still accurate.
2155 The backend is required to define these attributes in a way that only
2156 depends on the current target (rather than operands, compiler phase,
2160 check_bool_attrs (rtx_insn
*insn
)
2162 int code
= INSN_CODE (insn
);
2164 for (int i
= 0; i
<= BA_LAST
; ++i
)
2166 enum bool_attr attr
= (enum bool_attr
) i
;
2167 if (this_target_recog
->x_bool_attr_masks
[code
][attr
])
2168 gcc_assert (this_target_recog
->x_bool_attr_masks
[code
][attr
]
2169 == get_bool_attr_mask_uncached (insn
, attr
));
2174 /* Like extract_insn, but save insn extracted and don't extract again, when
2175 called again for the same insn expecting that recog_data still contain the
2176 valid information. This is used primary by gen_attr infrastructure that
2177 often does extract insn again and again. */
2179 extract_insn_cached (rtx_insn
*insn
)
2181 if (recog_data
.insn
== insn
&& INSN_CODE (insn
) >= 0)
2183 extract_insn (insn
);
2184 recog_data
.insn
= insn
;
2187 /* Do uncached extract_insn, constrain_operands and complain about failures.
2188 This should be used when extracting a pre-existing constrained instruction
2189 if the caller wants to know which alternative was chosen. */
2191 extract_constrain_insn (rtx_insn
*insn
)
2193 extract_insn (insn
);
2194 if (!constrain_operands (reload_completed
, get_enabled_alternatives (insn
)))
2195 fatal_insn_not_found (insn
);
2198 /* Do cached extract_insn, constrain_operands and complain about failures.
2199 Used by insn_attrtab. */
2201 extract_constrain_insn_cached (rtx_insn
*insn
)
2203 extract_insn_cached (insn
);
2204 if (which_alternative
== -1
2205 && !constrain_operands (reload_completed
,
2206 get_enabled_alternatives (insn
)))
2207 fatal_insn_not_found (insn
);
2210 /* Do cached constrain_operands on INSN and complain about failures. */
2212 constrain_operands_cached (rtx_insn
*insn
, int strict
)
2214 if (which_alternative
== -1)
2215 return constrain_operands (strict
, get_enabled_alternatives (insn
));
2220 /* Analyze INSN and fill in recog_data. */
2223 extract_insn (rtx_insn
*insn
)
2228 rtx body
= PATTERN (insn
);
2230 recog_data
.n_operands
= 0;
2231 recog_data
.n_alternatives
= 0;
2232 recog_data
.n_dups
= 0;
2233 recog_data
.is_asm
= false;
2235 switch (GET_CODE (body
))
2247 if (GET_CODE (SET_SRC (body
)) == ASM_OPERANDS
)
2252 if ((GET_CODE (XVECEXP (body
, 0, 0)) == SET
2253 && GET_CODE (SET_SRC (XVECEXP (body
, 0, 0))) == ASM_OPERANDS
)
2254 || GET_CODE (XVECEXP (body
, 0, 0)) == ASM_OPERANDS
2255 || GET_CODE (XVECEXP (body
, 0, 0)) == ASM_INPUT
)
2261 recog_data
.n_operands
= noperands
= asm_noperands (body
);
2264 /* This insn is an `asm' with operands. */
2266 /* expand_asm_operands makes sure there aren't too many operands. */
2267 gcc_assert (noperands
<= MAX_RECOG_OPERANDS
);
2269 /* Now get the operand values and constraints out of the insn. */
2270 decode_asm_operands (body
, recog_data
.operand
,
2271 recog_data
.operand_loc
,
2272 recog_data
.constraints
,
2273 recog_data
.operand_mode
, NULL
);
2274 memset (recog_data
.is_operator
, 0, sizeof recog_data
.is_operator
);
2277 const char *p
= recog_data
.constraints
[0];
2278 recog_data
.n_alternatives
= 1;
2280 recog_data
.n_alternatives
+= (*p
++ == ',');
2282 recog_data
.is_asm
= true;
2285 fatal_insn_not_found (insn
);
2289 /* Ordinary insn: recognize it, get the operands via insn_extract
2290 and get the constraints. */
2292 icode
= recog_memoized (insn
);
2294 fatal_insn_not_found (insn
);
2296 recog_data
.n_operands
= noperands
= insn_data
[icode
].n_operands
;
2297 recog_data
.n_alternatives
= insn_data
[icode
].n_alternatives
;
2298 recog_data
.n_dups
= insn_data
[icode
].n_dups
;
2300 insn_extract (insn
);
2302 for (i
= 0; i
< noperands
; i
++)
2304 recog_data
.constraints
[i
] = insn_data
[icode
].operand
[i
].constraint
;
2305 recog_data
.is_operator
[i
] = insn_data
[icode
].operand
[i
].is_operator
;
2306 recog_data
.operand_mode
[i
] = insn_data
[icode
].operand
[i
].mode
;
2307 /* VOIDmode match_operands gets mode from their real operand. */
2308 if (recog_data
.operand_mode
[i
] == VOIDmode
)
2309 recog_data
.operand_mode
[i
] = GET_MODE (recog_data
.operand
[i
]);
2312 for (i
= 0; i
< noperands
; i
++)
2313 recog_data
.operand_type
[i
]
2314 = (recog_data
.constraints
[i
][0] == '=' ? OP_OUT
2315 : recog_data
.constraints
[i
][0] == '+' ? OP_INOUT
2318 gcc_assert (recog_data
.n_alternatives
<= MAX_RECOG_ALTERNATIVES
);
2320 recog_data
.insn
= NULL
;
2321 which_alternative
= -1;
2324 /* Fill in OP_ALT_BASE for an instruction that has N_OPERANDS
2325 operands, N_ALTERNATIVES alternatives and constraint strings
2326 CONSTRAINTS. OP_ALT_BASE has N_ALTERNATIVES * N_OPERANDS entries
2327 and CONSTRAINTS has N_OPERANDS entries. OPLOC should be passed in
2328 if the insn is an asm statement and preprocessing should take the
2329 asm operands into account, e.g. to determine whether they could be
2330 addresses in constraints that require addresses; it should then
2331 point to an array of pointers to each operand. */
2334 preprocess_constraints (int n_operands
, int n_alternatives
,
2335 const char **constraints
,
2336 operand_alternative
*op_alt_base
,
2339 for (int i
= 0; i
< n_operands
; i
++)
2342 struct operand_alternative
*op_alt
;
2343 const char *p
= constraints
[i
];
2345 op_alt
= op_alt_base
;
2347 for (j
= 0; j
< n_alternatives
; j
++, op_alt
+= n_operands
)
2349 op_alt
[i
].cl
= NO_REGS
;
2350 op_alt
[i
].constraint
= p
;
2351 op_alt
[i
].matches
= -1;
2352 op_alt
[i
].matched
= -1;
2354 if (*p
== '\0' || *p
== ',')
2356 op_alt
[i
].anything_ok
= 1;
2366 while (c
!= ',' && c
!= '\0');
2367 if (c
== ',' || c
== '\0')
2376 op_alt
[i
].reject
+= 6;
2379 op_alt
[i
].reject
+= 600;
2382 op_alt
[i
].earlyclobber
= 1;
2385 case '0': case '1': case '2': case '3': case '4':
2386 case '5': case '6': case '7': case '8': case '9':
2389 op_alt
[i
].matches
= strtoul (p
, &end
, 10);
2390 op_alt
[op_alt
[i
].matches
].matched
= i
;
2396 op_alt
[i
].anything_ok
= 1;
2401 reg_class_subunion
[(int) op_alt
[i
].cl
][(int) GENERAL_REGS
];
2405 enum constraint_num cn
= lookup_constraint (p
);
2407 switch (get_constraint_type (cn
))
2410 cl
= reg_class_for_constraint (cn
);
2412 op_alt
[i
].cl
= reg_class_subunion
[op_alt
[i
].cl
][cl
];
2419 case CT_SPECIAL_MEMORY
:
2420 op_alt
[i
].memory_ok
= 1;
2424 if (oploc
&& !address_operand (*oploc
[i
], VOIDmode
))
2427 op_alt
[i
].is_address
= 1;
2429 = (reg_class_subunion
2430 [(int) op_alt
[i
].cl
]
2431 [(int) base_reg_class (VOIDmode
, ADDR_SPACE_GENERIC
,
2432 ADDRESS
, SCRATCH
)]);
2440 p
+= CONSTRAINT_LEN (c
, p
);
2446 /* Return an array of operand_alternative instructions for
2447 instruction ICODE. */
2449 const operand_alternative
*
2450 preprocess_insn_constraints (unsigned int icode
)
2452 gcc_checking_assert (IN_RANGE (icode
, 0, NUM_INSN_CODES
- 1));
2453 if (this_target_recog
->x_op_alt
[icode
])
2454 return this_target_recog
->x_op_alt
[icode
];
2456 int n_operands
= insn_data
[icode
].n_operands
;
2457 if (n_operands
== 0)
2459 /* Always provide at least one alternative so that which_op_alt ()
2460 works correctly. If the instruction has 0 alternatives (i.e. all
2461 constraint strings are empty) then each operand in this alternative
2462 will have anything_ok set. */
2463 int n_alternatives
= MAX (insn_data
[icode
].n_alternatives
, 1);
2464 int n_entries
= n_operands
* n_alternatives
;
2466 operand_alternative
*op_alt
= XCNEWVEC (operand_alternative
, n_entries
);
2467 const char **constraints
= XALLOCAVEC (const char *, n_operands
);
2469 for (int i
= 0; i
< n_operands
; ++i
)
2470 constraints
[i
] = insn_data
[icode
].operand
[i
].constraint
;
2471 preprocess_constraints (n_operands
, n_alternatives
, constraints
, op_alt
,
2474 this_target_recog
->x_op_alt
[icode
] = op_alt
;
2478 /* After calling extract_insn, you can use this function to extract some
2479 information from the constraint strings into a more usable form.
2480 The collected data is stored in recog_op_alt. */
2483 preprocess_constraints (rtx_insn
*insn
)
2485 int icode
= INSN_CODE (insn
);
2487 recog_op_alt
= preprocess_insn_constraints (icode
);
2490 int n_operands
= recog_data
.n_operands
;
2491 int n_alternatives
= recog_data
.n_alternatives
;
2492 int n_entries
= n_operands
* n_alternatives
;
2493 memset (asm_op_alt
, 0, n_entries
* sizeof (operand_alternative
));
2494 preprocess_constraints (n_operands
, n_alternatives
,
2495 recog_data
.constraints
, asm_op_alt
,
2497 recog_op_alt
= asm_op_alt
;
2501 /* Check the operands of an insn against the insn's operand constraints
2502 and return 1 if they match any of the alternatives in ALTERNATIVES.
2504 The information about the insn's operands, constraints, operand modes
2505 etc. is obtained from the global variables set up by extract_insn.
2507 WHICH_ALTERNATIVE is set to a number which indicates which
2508 alternative of constraints was matched: 0 for the first alternative,
2509 1 for the next, etc.
2511 In addition, when two operands are required to match
2512 and it happens that the output operand is (reg) while the
2513 input operand is --(reg) or ++(reg) (a pre-inc or pre-dec),
2514 make the output operand look like the input.
2515 This is because the output operand is the one the template will print.
2517 This is used in final, just before printing the assembler code and by
2518 the routines that determine an insn's attribute.
2520 If STRICT is a positive nonzero value, it means that we have been
2521 called after reload has been completed. In that case, we must
2522 do all checks strictly. If it is zero, it means that we have been called
2523 before reload has completed. In that case, we first try to see if we can
2524 find an alternative that matches strictly. If not, we try again, this
2525 time assuming that reload will fix up the insn. This provides a "best
2526 guess" for the alternative and is used to compute attributes of insns prior
2527 to reload. A negative value of STRICT is used for this internal call. */
2535 constrain_operands (int strict
, alternative_mask alternatives
)
2537 const char *constraints
[MAX_RECOG_OPERANDS
];
2538 int matching_operands
[MAX_RECOG_OPERANDS
];
2539 int earlyclobber
[MAX_RECOG_OPERANDS
];
2542 struct funny_match funny_match
[MAX_RECOG_OPERANDS
];
2543 int funny_match_index
;
2545 which_alternative
= 0;
2546 if (recog_data
.n_operands
== 0 || recog_data
.n_alternatives
== 0)
2549 for (c
= 0; c
< recog_data
.n_operands
; c
++)
2551 constraints
[c
] = recog_data
.constraints
[c
];
2552 matching_operands
[c
] = -1;
2557 int seen_earlyclobber_at
= -1;
2560 funny_match_index
= 0;
2562 if (!TEST_BIT (alternatives
, which_alternative
))
2566 for (i
= 0; i
< recog_data
.n_operands
; i
++)
2567 constraints
[i
] = skip_alternative (constraints
[i
]);
2569 which_alternative
++;
2573 for (opno
= 0; opno
< recog_data
.n_operands
; opno
++)
2575 rtx op
= recog_data
.operand
[opno
];
2576 machine_mode mode
= GET_MODE (op
);
2577 const char *p
= constraints
[opno
];
2583 earlyclobber
[opno
] = 0;
2585 /* A unary operator may be accepted by the predicate, but it
2586 is irrelevant for matching constraints. */
2590 if (GET_CODE (op
) == SUBREG
)
2592 if (REG_P (SUBREG_REG (op
))
2593 && REGNO (SUBREG_REG (op
)) < FIRST_PSEUDO_REGISTER
)
2594 offset
= subreg_regno_offset (REGNO (SUBREG_REG (op
)),
2595 GET_MODE (SUBREG_REG (op
)),
2598 op
= SUBREG_REG (op
);
2601 /* An empty constraint or empty alternative
2602 allows anything which matched the pattern. */
2603 if (*p
== 0 || *p
== ',')
2607 switch (c
= *p
, len
= CONSTRAINT_LEN (c
, p
), c
)
2617 /* Ignore rest of this alternative as far as
2618 constraint checking is concerned. */
2621 while (*p
&& *p
!= ',');
2626 earlyclobber
[opno
] = 1;
2627 if (seen_earlyclobber_at
< 0)
2628 seen_earlyclobber_at
= opno
;
2631 case '0': case '1': case '2': case '3': case '4':
2632 case '5': case '6': case '7': case '8': case '9':
2634 /* This operand must be the same as a previous one.
2635 This kind of constraint is used for instructions such
2636 as add when they take only two operands.
2638 Note that the lower-numbered operand is passed first.
2640 If we are not testing strictly, assume that this
2641 constraint will be satisfied. */
2646 match
= strtoul (p
, &end
, 10);
2653 rtx op1
= recog_data
.operand
[match
];
2654 rtx op2
= recog_data
.operand
[opno
];
2656 /* A unary operator may be accepted by the predicate,
2657 but it is irrelevant for matching constraints. */
2659 op1
= XEXP (op1
, 0);
2661 op2
= XEXP (op2
, 0);
2663 val
= operands_match_p (op1
, op2
);
2666 matching_operands
[opno
] = match
;
2667 matching_operands
[match
] = opno
;
2672 /* If output is *x and input is *--x, arrange later
2673 to change the output to *--x as well, since the
2674 output op is the one that will be printed. */
2675 if (val
== 2 && strict
> 0)
2677 funny_match
[funny_match_index
].this_op
= opno
;
2678 funny_match
[funny_match_index
++].other
= match
;
2685 /* p is used for address_operands. When we are called by
2686 gen_reload, no one will have checked that the address is
2687 strictly valid, i.e., that all pseudos requiring hard regs
2688 have gotten them. We also want to make sure we have a
2690 if ((GET_MODE (op
) == VOIDmode
2691 || SCALAR_INT_MODE_P (GET_MODE (op
)))
2693 || (strict_memory_address_p
2694 (recog_data
.operand_mode
[opno
], op
))))
2698 /* No need to check general_operand again;
2699 it was done in insn-recog.c. Well, except that reload
2700 doesn't check the validity of its replacements, but
2701 that should only matter when there's a bug. */
2703 /* Anything goes unless it is a REG and really has a hard reg
2704 but the hard reg is not in the class GENERAL_REGS. */
2708 || GENERAL_REGS
== ALL_REGS
2709 || (reload_in_progress
2710 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
)
2711 || reg_fits_class_p (op
, GENERAL_REGS
, offset
, mode
))
2714 else if (strict
< 0 || general_operand (op
, mode
))
2720 enum constraint_num cn
= lookup_constraint (p
);
2721 enum reg_class cl
= reg_class_for_constraint (cn
);
2727 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
)
2728 || (strict
== 0 && GET_CODE (op
) == SCRATCH
)
2730 && reg_fits_class_p (op
, cl
, offset
, mode
)))
2734 else if (constraint_satisfied_p (op
, cn
))
2737 else if (insn_extra_memory_constraint (cn
)
2738 /* Every memory operand can be reloaded to fit. */
2739 && ((strict
< 0 && MEM_P (op
))
2740 /* Before reload, accept what reload can turn
2742 || (strict
< 0 && CONSTANT_P (op
))
2743 /* Before reload, accept a pseudo or hard register,
2744 since LRA can turn it into a mem. */
2745 || (strict
< 0 && targetm
.lra_p () && REG_P (op
))
2746 /* During reload, accept a pseudo */
2747 || (reload_in_progress
&& REG_P (op
)
2748 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
)))
2750 else if (insn_extra_address_constraint (cn
)
2751 /* Every address operand can be reloaded to fit. */
2754 /* Cater to architectures like IA-64 that define extra memory
2755 constraints without using define_memory_constraint. */
2756 else if (reload_in_progress
2758 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
2759 && reg_renumber
[REGNO (op
)] < 0
2760 && reg_equiv_mem (REGNO (op
)) != 0
2761 && constraint_satisfied_p
2762 (reg_equiv_mem (REGNO (op
)), cn
))
2767 while (p
+= len
, c
);
2769 constraints
[opno
] = p
;
2770 /* If this operand did not win somehow,
2771 this alternative loses. */
2775 /* This alternative won; the operands are ok.
2776 Change whichever operands this alternative says to change. */
2781 /* See if any earlyclobber operand conflicts with some other
2784 if (strict
> 0 && seen_earlyclobber_at
>= 0)
2785 for (eopno
= seen_earlyclobber_at
;
2786 eopno
< recog_data
.n_operands
;
2788 /* Ignore earlyclobber operands now in memory,
2789 because we would often report failure when we have
2790 two memory operands, one of which was formerly a REG. */
2791 if (earlyclobber
[eopno
]
2792 && REG_P (recog_data
.operand
[eopno
]))
2793 for (opno
= 0; opno
< recog_data
.n_operands
; opno
++)
2794 if ((MEM_P (recog_data
.operand
[opno
])
2795 || recog_data
.operand_type
[opno
] != OP_OUT
)
2797 /* Ignore things like match_operator operands. */
2798 && *recog_data
.constraints
[opno
] != 0
2799 && ! (matching_operands
[opno
] == eopno
2800 && operands_match_p (recog_data
.operand
[opno
],
2801 recog_data
.operand
[eopno
]))
2802 && ! safe_from_earlyclobber (recog_data
.operand
[opno
],
2803 recog_data
.operand
[eopno
]))
2808 while (--funny_match_index
>= 0)
2810 recog_data
.operand
[funny_match
[funny_match_index
].other
]
2811 = recog_data
.operand
[funny_match
[funny_match_index
].this_op
];
2814 /* For operands without < or > constraints reject side-effects. */
2815 if (AUTO_INC_DEC
&& recog_data
.is_asm
)
2817 for (opno
= 0; opno
< recog_data
.n_operands
; opno
++)
2818 if (MEM_P (recog_data
.operand
[opno
]))
2819 switch (GET_CODE (XEXP (recog_data
.operand
[opno
], 0)))
2827 if (strchr (recog_data
.constraints
[opno
], '<') == NULL
2828 && strchr (recog_data
.constraints
[opno
], '>')
2841 which_alternative
++;
2843 while (which_alternative
< recog_data
.n_alternatives
);
2845 which_alternative
= -1;
2846 /* If we are about to reject this, but we are not to test strictly,
2847 try a very loose test. Only return failure if it fails also. */
2849 return constrain_operands (-1, alternatives
);
2854 /* Return true iff OPERAND (assumed to be a REG rtx)
2855 is a hard reg in class CLASS when its regno is offset by OFFSET
2856 and changed to mode MODE.
2857 If REG occupies multiple hard regs, all of them must be in CLASS. */
2860 reg_fits_class_p (const_rtx operand
, reg_class_t cl
, int offset
,
2863 unsigned int regno
= REGNO (operand
);
2868 /* Regno must not be a pseudo register. Offset may be negative. */
2869 return (HARD_REGISTER_NUM_P (regno
)
2870 && HARD_REGISTER_NUM_P (regno
+ offset
)
2871 && in_hard_reg_set_p (reg_class_contents
[(int) cl
], mode
,
2875 /* Split single instruction. Helper function for split_all_insns and
2876 split_all_insns_noflow. Return last insn in the sequence if successful,
2877 or NULL if unsuccessful. */
2880 split_insn (rtx_insn
*insn
)
2882 /* Split insns here to get max fine-grain parallelism. */
2883 rtx_insn
*first
= PREV_INSN (insn
);
2884 rtx_insn
*last
= try_split (PATTERN (insn
), insn
, 1);
2885 rtx insn_set
, last_set
, note
;
2890 /* If the original instruction was a single set that was known to be
2891 equivalent to a constant, see if we can say the same about the last
2892 instruction in the split sequence. The two instructions must set
2893 the same destination. */
2894 insn_set
= single_set (insn
);
2897 last_set
= single_set (last
);
2898 if (last_set
&& rtx_equal_p (SET_DEST (last_set
), SET_DEST (insn_set
)))
2900 note
= find_reg_equal_equiv_note (insn
);
2901 if (note
&& CONSTANT_P (XEXP (note
, 0)))
2902 set_unique_reg_note (last
, REG_EQUAL
, XEXP (note
, 0));
2903 else if (CONSTANT_P (SET_SRC (insn_set
)))
2904 set_unique_reg_note (last
, REG_EQUAL
,
2905 copy_rtx (SET_SRC (insn_set
)));
2909 /* try_split returns the NOTE that INSN became. */
2910 SET_INSN_DELETED (insn
);
2912 /* ??? Coddle to md files that generate subregs in post-reload
2913 splitters instead of computing the proper hard register. */
2914 if (reload_completed
&& first
!= last
)
2916 first
= NEXT_INSN (first
);
2920 cleanup_subreg_operands (first
);
2923 first
= NEXT_INSN (first
);
2930 /* Split all insns in the function. If UPD_LIFE, update life info after. */
2933 split_all_insns (void)
2936 bool need_cfg_cleanup
= false;
2939 auto_sbitmap
blocks (last_basic_block_for_fn (cfun
));
2940 bitmap_clear (blocks
);
2943 FOR_EACH_BB_REVERSE_FN (bb
, cfun
)
2945 rtx_insn
*insn
, *next
;
2946 bool finish
= false;
2948 rtl_profile_for_bb (bb
);
2949 for (insn
= BB_HEAD (bb
); !finish
; insn
= next
)
2951 /* Can't use `next_real_insn' because that might go across
2952 CODE_LABELS and short-out basic blocks. */
2953 next
= NEXT_INSN (insn
);
2954 finish
= (insn
== BB_END (bb
));
2956 /* If INSN has a REG_EH_REGION note and we split INSN, the
2957 resulting split may not have/need REG_EH_REGION notes.
2959 If that happens and INSN was the last reference to the
2960 given EH region, then the EH region will become unreachable.
2961 We cannot leave the unreachable blocks in the CFG as that
2962 will trigger a checking failure.
2964 So track if INSN has a REG_EH_REGION note. If so and we
2965 split INSN, then trigger a CFG cleanup. */
2966 rtx note
= find_reg_note (insn
, REG_EH_REGION
, NULL_RTX
);
2969 rtx set
= single_set (insn
);
2971 /* Don't split no-op move insns. These should silently
2972 disappear later in final. Splitting such insns would
2973 break the code that handles LIBCALL blocks. */
2974 if (set
&& set_noop_p (set
))
2976 /* Nops get in the way while scheduling, so delete them
2977 now if register allocation has already been done. It
2978 is too risky to try to do this before register
2979 allocation, and there are unlikely to be very many
2980 nops then anyways. */
2981 if (reload_completed
)
2982 delete_insn_and_edges (insn
);
2984 need_cfg_cleanup
= true;
2988 if (split_insn (insn
))
2990 bitmap_set_bit (blocks
, bb
->index
);
2993 need_cfg_cleanup
= true;
3000 default_rtl_profile ();
3003 find_many_sub_basic_blocks (blocks
);
3005 /* Splitting could drop an REG_EH_REGION if it potentially
3006 trapped in its original form, but does not in its split
3007 form. Consider a FLOAT_TRUNCATE which splits into a memory
3008 store/load pair and -fnon-call-exceptions. */
3009 if (need_cfg_cleanup
)
3013 checking_verify_flow_info ();
3016 /* Same as split_all_insns, but do not expect CFG to be available.
3017 Used by machine dependent reorg passes. */
3020 split_all_insns_noflow (void)
3022 rtx_insn
*next
, *insn
;
3024 for (insn
= get_insns (); insn
; insn
= next
)
3026 next
= NEXT_INSN (insn
);
3029 /* Don't split no-op move insns. These should silently
3030 disappear later in final. Splitting such insns would
3031 break the code that handles LIBCALL blocks. */
3032 rtx set
= single_set (insn
);
3033 if (set
&& set_noop_p (set
))
3035 /* Nops get in the way while scheduling, so delete them
3036 now if register allocation has already been done. It
3037 is too risky to try to do this before register
3038 allocation, and there are unlikely to be very many
3041 ??? Should we use delete_insn when the CFG isn't valid? */
3042 if (reload_completed
)
3043 delete_insn_and_edges (insn
);
3052 struct peep2_insn_data
3058 static struct peep2_insn_data peep2_insn_data
[MAX_INSNS_PER_PEEP2
+ 1];
3059 static int peep2_current
;
3061 static bool peep2_do_rebuild_jump_labels
;
3062 static bool peep2_do_cleanup_cfg
;
3064 /* The number of instructions available to match a peep2. */
3065 int peep2_current_count
;
3067 /* A marker indicating the last insn of the block. The live_before regset
3068 for this element is correct, indicating DF_LIVE_OUT for the block. */
3069 #define PEEP2_EOB invalid_insn_rtx
3071 /* Wrap N to fit into the peep2_insn_data buffer. */
3074 peep2_buf_position (int n
)
3076 if (n
>= MAX_INSNS_PER_PEEP2
+ 1)
3077 n
-= MAX_INSNS_PER_PEEP2
+ 1;
3081 /* Return the Nth non-note insn after `current', or return NULL_RTX if it
3082 does not exist. Used by the recognizer to find the next insn to match
3083 in a multi-insn pattern. */
3086 peep2_next_insn (int n
)
3088 gcc_assert (n
<= peep2_current_count
);
3090 n
= peep2_buf_position (peep2_current
+ n
);
3092 return peep2_insn_data
[n
].insn
;
3095 /* Return true if REGNO is dead before the Nth non-note insn
3099 peep2_regno_dead_p (int ofs
, int regno
)
3101 gcc_assert (ofs
< MAX_INSNS_PER_PEEP2
+ 1);
3103 ofs
= peep2_buf_position (peep2_current
+ ofs
);
3105 gcc_assert (peep2_insn_data
[ofs
].insn
!= NULL_RTX
);
3107 return ! REGNO_REG_SET_P (peep2_insn_data
[ofs
].live_before
, regno
);
3110 /* Similarly for a REG. */
3113 peep2_reg_dead_p (int ofs
, rtx reg
)
3115 gcc_assert (ofs
< MAX_INSNS_PER_PEEP2
+ 1);
3117 ofs
= peep2_buf_position (peep2_current
+ ofs
);
3119 gcc_assert (peep2_insn_data
[ofs
].insn
!= NULL_RTX
);
3121 unsigned int end_regno
= END_REGNO (reg
);
3122 for (unsigned int regno
= REGNO (reg
); regno
< end_regno
; ++regno
)
3123 if (REGNO_REG_SET_P (peep2_insn_data
[ofs
].live_before
, regno
))
3128 /* Regno offset to be used in the register search. */
3129 static int search_ofs
;
3131 /* Try to find a hard register of mode MODE, matching the register class in
3132 CLASS_STR, which is available at the beginning of insn CURRENT_INSN and
3133 remains available until the end of LAST_INSN. LAST_INSN may be NULL_RTX,
3134 in which case the only condition is that the register must be available
3135 before CURRENT_INSN.
3136 Registers that already have bits set in REG_SET will not be considered.
3138 If an appropriate register is available, it will be returned and the
3139 corresponding bit(s) in REG_SET will be set; otherwise, NULL_RTX is
3143 peep2_find_free_register (int from
, int to
, const char *class_str
,
3144 machine_mode mode
, HARD_REG_SET
*reg_set
)
3151 gcc_assert (from
< MAX_INSNS_PER_PEEP2
+ 1);
3152 gcc_assert (to
< MAX_INSNS_PER_PEEP2
+ 1);
3154 from
= peep2_buf_position (peep2_current
+ from
);
3155 to
= peep2_buf_position (peep2_current
+ to
);
3157 gcc_assert (peep2_insn_data
[from
].insn
!= NULL_RTX
);
3158 REG_SET_TO_HARD_REG_SET (live
, peep2_insn_data
[from
].live_before
);
3162 gcc_assert (peep2_insn_data
[from
].insn
!= NULL_RTX
);
3164 /* Don't use registers set or clobbered by the insn. */
3165 FOR_EACH_INSN_DEF (def
, peep2_insn_data
[from
].insn
)
3166 SET_HARD_REG_BIT (live
, DF_REF_REGNO (def
));
3168 from
= peep2_buf_position (from
+ 1);
3171 cl
= reg_class_for_constraint (lookup_constraint (class_str
));
3173 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
3175 int raw_regno
, regno
, success
, j
;
3177 /* Distribute the free registers as much as possible. */
3178 raw_regno
= search_ofs
+ i
;
3179 if (raw_regno
>= FIRST_PSEUDO_REGISTER
)
3180 raw_regno
-= FIRST_PSEUDO_REGISTER
;
3181 #ifdef REG_ALLOC_ORDER
3182 regno
= reg_alloc_order
[raw_regno
];
3187 /* Can it support the mode we need? */
3188 if (!targetm
.hard_regno_mode_ok (regno
, mode
))
3192 for (j
= 0; success
&& j
< hard_regno_nregs (regno
, mode
); j
++)
3194 /* Don't allocate fixed registers. */
3195 if (fixed_regs
[regno
+ j
])
3200 /* Don't allocate global registers. */
3201 if (global_regs
[regno
+ j
])
3206 /* Make sure the register is of the right class. */
3207 if (! TEST_HARD_REG_BIT (reg_class_contents
[cl
], regno
+ j
))
3212 /* And that we don't create an extra save/restore. */
3213 if (! crtl
->abi
->clobbers_full_reg_p (regno
+ j
)
3214 && ! df_regs_ever_live_p (regno
+ j
))
3220 if (! targetm
.hard_regno_scratch_ok (regno
+ j
))
3226 /* And we don't clobber traceback for noreturn functions. */
3227 if ((regno
+ j
== FRAME_POINTER_REGNUM
3228 || regno
+ j
== HARD_FRAME_POINTER_REGNUM
)
3229 && (! reload_completed
|| frame_pointer_needed
))
3235 if (TEST_HARD_REG_BIT (*reg_set
, regno
+ j
)
3236 || TEST_HARD_REG_BIT (live
, regno
+ j
))
3245 add_to_hard_reg_set (reg_set
, mode
, regno
);
3247 /* Start the next search with the next register. */
3248 if (++raw_regno
>= FIRST_PSEUDO_REGISTER
)
3250 search_ofs
= raw_regno
;
3252 return gen_rtx_REG (mode
, regno
);
3260 /* Forget all currently tracked instructions, only remember current
3264 peep2_reinit_state (regset live
)
3268 /* Indicate that all slots except the last holds invalid data. */
3269 for (i
= 0; i
< MAX_INSNS_PER_PEEP2
; ++i
)
3270 peep2_insn_data
[i
].insn
= NULL
;
3271 peep2_current_count
= 0;
3273 /* Indicate that the last slot contains live_after data. */
3274 peep2_insn_data
[MAX_INSNS_PER_PEEP2
].insn
= PEEP2_EOB
;
3275 peep2_current
= MAX_INSNS_PER_PEEP2
;
3277 COPY_REG_SET (peep2_insn_data
[MAX_INSNS_PER_PEEP2
].live_before
, live
);
3280 /* While scanning basic block BB, we found a match of length MATCH_LEN,
3281 starting at INSN. Perform the replacement, removing the old insns and
3282 replacing them with ATTEMPT. Returns the last insn emitted, or NULL
3283 if the replacement is rejected. */
3286 peep2_attempt (basic_block bb
, rtx_insn
*insn
, int match_len
, rtx_insn
*attempt
)
3289 rtx_insn
*last
, *before_try
, *x
;
3290 rtx eh_note
, as_note
;
3293 bool was_call
= false;
3295 /* If we are splitting an RTX_FRAME_RELATED_P insn, do not allow it to
3296 match more than one insn, or to be split into more than one insn. */
3297 old_insn
= peep2_insn_data
[peep2_current
].insn
;
3298 if (RTX_FRAME_RELATED_P (old_insn
))
3300 bool any_note
= false;
3306 /* Look for one "active" insn. I.e. ignore any "clobber" insns that
3307 may be in the stream for the purpose of register allocation. */
3308 if (active_insn_p (attempt
))
3311 new_insn
= next_active_insn (attempt
);
3312 if (next_active_insn (new_insn
))
3315 /* We have a 1-1 replacement. Copy over any frame-related info. */
3316 RTX_FRAME_RELATED_P (new_insn
) = 1;
3318 /* Allow the backend to fill in a note during the split. */
3319 for (note
= REG_NOTES (new_insn
); note
; note
= XEXP (note
, 1))
3320 switch (REG_NOTE_KIND (note
))
3322 case REG_FRAME_RELATED_EXPR
:
3323 case REG_CFA_DEF_CFA
:
3324 case REG_CFA_ADJUST_CFA
:
3325 case REG_CFA_OFFSET
:
3326 case REG_CFA_REGISTER
:
3327 case REG_CFA_EXPRESSION
:
3328 case REG_CFA_RESTORE
:
3329 case REG_CFA_SET_VDRAP
:
3336 /* If the backend didn't supply a note, copy one over. */
3338 for (note
= REG_NOTES (old_insn
); note
; note
= XEXP (note
, 1))
3339 switch (REG_NOTE_KIND (note
))
3341 case REG_FRAME_RELATED_EXPR
:
3342 case REG_CFA_DEF_CFA
:
3343 case REG_CFA_ADJUST_CFA
:
3344 case REG_CFA_OFFSET
:
3345 case REG_CFA_REGISTER
:
3346 case REG_CFA_EXPRESSION
:
3347 case REG_CFA_RESTORE
:
3348 case REG_CFA_SET_VDRAP
:
3349 add_reg_note (new_insn
, REG_NOTE_KIND (note
), XEXP (note
, 0));
3356 /* If there still isn't a note, make sure the unwind info sees the
3357 same expression as before the split. */
3360 rtx old_set
, new_set
;
3362 /* The old insn had better have been simple, or annotated. */
3363 old_set
= single_set (old_insn
);
3364 gcc_assert (old_set
!= NULL
);
3366 new_set
= single_set (new_insn
);
3367 if (!new_set
|| !rtx_equal_p (new_set
, old_set
))
3368 add_reg_note (new_insn
, REG_FRAME_RELATED_EXPR
, old_set
);
3371 /* Copy prologue/epilogue status. This is required in order to keep
3372 proper placement of EPILOGUE_BEG and the DW_CFA_remember_state. */
3373 maybe_copy_prologue_epilogue_insn (old_insn
, new_insn
);
3376 /* If we are splitting a CALL_INSN, look for the CALL_INSN
3377 in SEQ and copy our CALL_INSN_FUNCTION_USAGE and other
3378 cfg-related call notes. */
3379 for (i
= 0; i
<= match_len
; ++i
)
3384 j
= peep2_buf_position (peep2_current
+ i
);
3385 old_insn
= peep2_insn_data
[j
].insn
;
3386 if (!CALL_P (old_insn
))
3391 while (new_insn
!= NULL_RTX
)
3393 if (CALL_P (new_insn
))
3395 new_insn
= NEXT_INSN (new_insn
);
3398 gcc_assert (new_insn
!= NULL_RTX
);
3400 CALL_INSN_FUNCTION_USAGE (new_insn
)
3401 = CALL_INSN_FUNCTION_USAGE (old_insn
);
3402 SIBLING_CALL_P (new_insn
) = SIBLING_CALL_P (old_insn
);
3404 for (note
= REG_NOTES (old_insn
);
3406 note
= XEXP (note
, 1))
3407 switch (REG_NOTE_KIND (note
))
3412 case REG_CALL_NOCF_CHECK
:
3413 add_reg_note (new_insn
, REG_NOTE_KIND (note
),
3417 /* Discard all other reg notes. */
3421 /* Croak if there is another call in the sequence. */
3422 while (++i
<= match_len
)
3424 j
= peep2_buf_position (peep2_current
+ i
);
3425 old_insn
= peep2_insn_data
[j
].insn
;
3426 gcc_assert (!CALL_P (old_insn
));
3431 /* If we matched any instruction that had a REG_ARGS_SIZE, then
3432 move those notes over to the new sequence. */
3434 for (i
= match_len
; i
>= 0; --i
)
3436 int j
= peep2_buf_position (peep2_current
+ i
);
3437 old_insn
= peep2_insn_data
[j
].insn
;
3439 as_note
= find_reg_note (old_insn
, REG_ARGS_SIZE
, NULL
);
3444 i
= peep2_buf_position (peep2_current
+ match_len
);
3445 eh_note
= find_reg_note (peep2_insn_data
[i
].insn
, REG_EH_REGION
, NULL_RTX
);
3447 /* Replace the old sequence with the new. */
3448 rtx_insn
*peepinsn
= peep2_insn_data
[i
].insn
;
3449 last
= emit_insn_after_setloc (attempt
,
3450 peep2_insn_data
[i
].insn
,
3451 INSN_LOCATION (peepinsn
));
3452 if (JUMP_P (peepinsn
) && JUMP_P (last
))
3453 CROSSING_JUMP_P (last
) = CROSSING_JUMP_P (peepinsn
);
3454 before_try
= PREV_INSN (insn
);
3455 delete_insn_chain (insn
, peep2_insn_data
[i
].insn
, false);
3457 /* Re-insert the EH_REGION notes. */
3458 if (eh_note
|| (was_call
&& nonlocal_goto_handler_labels
))
3463 FOR_EACH_EDGE (eh_edge
, ei
, bb
->succs
)
3464 if (eh_edge
->flags
& (EDGE_EH
| EDGE_ABNORMAL_CALL
))
3468 copy_reg_eh_region_note_backward (eh_note
, last
, before_try
);
3471 for (x
= last
; x
!= before_try
; x
= PREV_INSN (x
))
3472 if (x
!= BB_END (bb
)
3473 && (can_throw_internal (x
)
3474 || can_nonlocal_goto (x
)))
3479 nfte
= split_block (bb
, x
);
3480 flags
= (eh_edge
->flags
3481 & (EDGE_EH
| EDGE_ABNORMAL
));
3483 flags
|= EDGE_ABNORMAL_CALL
;
3484 nehe
= make_edge (nfte
->src
, eh_edge
->dest
,
3487 nehe
->probability
= eh_edge
->probability
;
3488 nfte
->probability
= nehe
->probability
.invert ();
3490 peep2_do_cleanup_cfg
|= purge_dead_edges (nfte
->dest
);
3495 /* Converting possibly trapping insn to non-trapping is
3496 possible. Zap dummy outgoing edges. */
3497 peep2_do_cleanup_cfg
|= purge_dead_edges (bb
);
3500 /* Re-insert the ARGS_SIZE notes. */
3502 fixup_args_size_notes (before_try
, last
, get_args_size (as_note
));
3504 /* If we generated a jump instruction, it won't have
3505 JUMP_LABEL set. Recompute after we're done. */
3506 for (x
= last
; x
!= before_try
; x
= PREV_INSN (x
))
3509 peep2_do_rebuild_jump_labels
= true;
3516 /* After performing a replacement in basic block BB, fix up the life
3517 information in our buffer. LAST is the last of the insns that we
3518 emitted as a replacement. PREV is the insn before the start of
3519 the replacement. MATCH_LEN is the number of instructions that were
3520 matched, and which now need to be replaced in the buffer. */
3523 peep2_update_life (basic_block bb
, int match_len
, rtx_insn
*last
,
3526 int i
= peep2_buf_position (peep2_current
+ match_len
+ 1);
3530 INIT_REG_SET (&live
);
3531 COPY_REG_SET (&live
, peep2_insn_data
[i
].live_before
);
3533 gcc_assert (peep2_current_count
>= match_len
+ 1);
3534 peep2_current_count
-= match_len
+ 1;
3542 if (peep2_current_count
< MAX_INSNS_PER_PEEP2
)
3544 peep2_current_count
++;
3546 i
= MAX_INSNS_PER_PEEP2
;
3547 peep2_insn_data
[i
].insn
= x
;
3548 df_simulate_one_insn_backwards (bb
, x
, &live
);
3549 COPY_REG_SET (peep2_insn_data
[i
].live_before
, &live
);
3555 CLEAR_REG_SET (&live
);
3560 /* Add INSN, which is in BB, at the end of the peep2 insn buffer if possible.
3561 Return true if we added it, false otherwise. The caller will try to match
3562 peepholes against the buffer if we return false; otherwise it will try to
3563 add more instructions to the buffer. */
3566 peep2_fill_buffer (basic_block bb
, rtx_insn
*insn
, regset live
)
3570 /* Once we have filled the maximum number of insns the buffer can hold,
3571 allow the caller to match the insns against peepholes. We wait until
3572 the buffer is full in case the target has similar peepholes of different
3573 length; we always want to match the longest if possible. */
3574 if (peep2_current_count
== MAX_INSNS_PER_PEEP2
)
3577 /* If an insn has RTX_FRAME_RELATED_P set, do not allow it to be matched with
3578 any other pattern, lest it change the semantics of the frame info. */
3579 if (RTX_FRAME_RELATED_P (insn
))
3581 /* Let the buffer drain first. */
3582 if (peep2_current_count
> 0)
3584 /* Now the insn will be the only thing in the buffer. */
3587 pos
= peep2_buf_position (peep2_current
+ peep2_current_count
);
3588 peep2_insn_data
[pos
].insn
= insn
;
3589 COPY_REG_SET (peep2_insn_data
[pos
].live_before
, live
);
3590 peep2_current_count
++;
3592 df_simulate_one_insn_forwards (bb
, insn
, live
);
3596 /* Perform the peephole2 optimization pass. */
3599 peephole2_optimize (void)
3606 peep2_do_cleanup_cfg
= false;
3607 peep2_do_rebuild_jump_labels
= false;
3609 df_set_flags (DF_LR_RUN_DCE
);
3610 df_note_add_problem ();
3613 /* Initialize the regsets we're going to use. */
3614 for (i
= 0; i
< MAX_INSNS_PER_PEEP2
+ 1; ++i
)
3615 peep2_insn_data
[i
].live_before
= BITMAP_ALLOC (®_obstack
);
3617 live
= BITMAP_ALLOC (®_obstack
);
3619 FOR_EACH_BB_REVERSE_FN (bb
, cfun
)
3621 bool past_end
= false;
3624 rtl_profile_for_bb (bb
);
3626 /* Start up propagation. */
3627 bitmap_copy (live
, DF_LR_IN (bb
));
3628 df_simulate_initialize_forwards (bb
, live
);
3629 peep2_reinit_state (live
);
3631 insn
= BB_HEAD (bb
);
3634 rtx_insn
*attempt
, *head
;
3637 if (!past_end
&& !NONDEBUG_INSN_P (insn
))
3640 insn
= NEXT_INSN (insn
);
3641 if (insn
== NEXT_INSN (BB_END (bb
)))
3645 if (!past_end
&& peep2_fill_buffer (bb
, insn
, live
))
3648 /* If we did not fill an empty buffer, it signals the end of the
3650 if (peep2_current_count
== 0)
3653 /* The buffer filled to the current maximum, so try to match. */
3655 pos
= peep2_buf_position (peep2_current
+ peep2_current_count
);
3656 peep2_insn_data
[pos
].insn
= PEEP2_EOB
;
3657 COPY_REG_SET (peep2_insn_data
[pos
].live_before
, live
);
3659 /* Match the peephole. */
3660 head
= peep2_insn_data
[peep2_current
].insn
;
3661 attempt
= peephole2_insns (PATTERN (head
), head
, &match_len
);
3662 if (attempt
!= NULL
)
3664 rtx_insn
*last
= peep2_attempt (bb
, head
, match_len
, attempt
);
3667 peep2_update_life (bb
, match_len
, last
, PREV_INSN (attempt
));
3672 /* No match: advance the buffer by one insn. */
3673 peep2_current
= peep2_buf_position (peep2_current
+ 1);
3674 peep2_current_count
--;
3678 default_rtl_profile ();
3679 for (i
= 0; i
< MAX_INSNS_PER_PEEP2
+ 1; ++i
)
3680 BITMAP_FREE (peep2_insn_data
[i
].live_before
);
3682 if (peep2_do_rebuild_jump_labels
)
3683 rebuild_jump_labels (get_insns ());
3684 if (peep2_do_cleanup_cfg
)
3685 cleanup_cfg (CLEANUP_CFG_CHANGED
);
3688 /* Common predicates for use with define_bypass. */
3690 /* Helper function for store_data_bypass_p, handle just a single SET
3694 store_data_bypass_p_1 (rtx_insn
*out_insn
, rtx in_set
)
3696 if (!MEM_P (SET_DEST (in_set
)))
3699 rtx out_set
= single_set (out_insn
);
3701 return !reg_mentioned_p (SET_DEST (out_set
), SET_DEST (in_set
));
3703 rtx out_pat
= PATTERN (out_insn
);
3704 if (GET_CODE (out_pat
) != PARALLEL
)
3707 for (int i
= 0; i
< XVECLEN (out_pat
, 0); i
++)
3709 rtx out_exp
= XVECEXP (out_pat
, 0, i
);
3711 if (GET_CODE (out_exp
) == CLOBBER
|| GET_CODE (out_exp
) == USE
)
3714 gcc_assert (GET_CODE (out_exp
) == SET
);
3716 if (reg_mentioned_p (SET_DEST (out_exp
), SET_DEST (in_set
)))
3723 /* True if the dependency between OUT_INSN and IN_INSN is on the store
3724 data not the address operand(s) of the store. IN_INSN and OUT_INSN
3725 must be either a single_set or a PARALLEL with SETs inside. */
3728 store_data_bypass_p (rtx_insn
*out_insn
, rtx_insn
*in_insn
)
3730 rtx in_set
= single_set (in_insn
);
3732 return store_data_bypass_p_1 (out_insn
, in_set
);
3734 rtx in_pat
= PATTERN (in_insn
);
3735 if (GET_CODE (in_pat
) != PARALLEL
)
3738 for (int i
= 0; i
< XVECLEN (in_pat
, 0); i
++)
3740 rtx in_exp
= XVECEXP (in_pat
, 0, i
);
3742 if (GET_CODE (in_exp
) == CLOBBER
|| GET_CODE (in_exp
) == USE
)
3745 gcc_assert (GET_CODE (in_exp
) == SET
);
3747 if (!store_data_bypass_p_1 (out_insn
, in_exp
))
3754 /* True if the dependency between OUT_INSN and IN_INSN is in the IF_THEN_ELSE
3755 condition, and not the THEN or ELSE branch. OUT_INSN may be either a single
3756 or multiple set; IN_INSN should be single_set for truth, but for convenience
3757 of insn categorization may be any JUMP or CALL insn. */
3760 if_test_bypass_p (rtx_insn
*out_insn
, rtx_insn
*in_insn
)
3762 rtx out_set
, in_set
;
3764 in_set
= single_set (in_insn
);
3767 gcc_assert (JUMP_P (in_insn
) || CALL_P (in_insn
));
3771 if (GET_CODE (SET_SRC (in_set
)) != IF_THEN_ELSE
)
3773 in_set
= SET_SRC (in_set
);
3775 out_set
= single_set (out_insn
);
3778 if (reg_mentioned_p (SET_DEST (out_set
), XEXP (in_set
, 1))
3779 || reg_mentioned_p (SET_DEST (out_set
), XEXP (in_set
, 2)))
3787 out_pat
= PATTERN (out_insn
);
3788 gcc_assert (GET_CODE (out_pat
) == PARALLEL
);
3790 for (i
= 0; i
< XVECLEN (out_pat
, 0); i
++)
3792 rtx exp
= XVECEXP (out_pat
, 0, i
);
3794 if (GET_CODE (exp
) == CLOBBER
)
3797 gcc_assert (GET_CODE (exp
) == SET
);
3799 if (reg_mentioned_p (SET_DEST (out_set
), XEXP (in_set
, 1))
3800 || reg_mentioned_p (SET_DEST (out_set
), XEXP (in_set
, 2)))
3809 rest_of_handle_peephole2 (void)
3812 peephole2_optimize ();
3819 const pass_data pass_data_peephole2
=
3821 RTL_PASS
, /* type */
3822 "peephole2", /* name */
3823 OPTGROUP_NONE
, /* optinfo_flags */
3824 TV_PEEPHOLE2
, /* tv_id */
3825 0, /* properties_required */
3826 0, /* properties_provided */
3827 0, /* properties_destroyed */
3828 0, /* todo_flags_start */
3829 TODO_df_finish
, /* todo_flags_finish */
3832 class pass_peephole2
: public rtl_opt_pass
3835 pass_peephole2 (gcc::context
*ctxt
)
3836 : rtl_opt_pass (pass_data_peephole2
, ctxt
)
3839 /* opt_pass methods: */
3840 /* The epiphany backend creates a second instance of this pass, so we need
3842 opt_pass
* clone () { return new pass_peephole2 (m_ctxt
); }
3843 virtual bool gate (function
*) { return (optimize
> 0 && flag_peephole2
); }
3844 virtual unsigned int execute (function
*)
3846 return rest_of_handle_peephole2 ();
3849 }; // class pass_peephole2
3854 make_pass_peephole2 (gcc::context
*ctxt
)
3856 return new pass_peephole2 (ctxt
);
3861 const pass_data pass_data_split_all_insns
=
3863 RTL_PASS
, /* type */
3864 "split1", /* name */
3865 OPTGROUP_NONE
, /* optinfo_flags */
3866 TV_NONE
, /* tv_id */
3867 0, /* properties_required */
3868 PROP_rtl_split_insns
, /* properties_provided */
3869 0, /* properties_destroyed */
3870 0, /* todo_flags_start */
3871 0, /* todo_flags_finish */
3874 class pass_split_all_insns
: public rtl_opt_pass
3877 pass_split_all_insns (gcc::context
*ctxt
)
3878 : rtl_opt_pass (pass_data_split_all_insns
, ctxt
)
3881 /* opt_pass methods: */
3882 /* The epiphany backend creates a second instance of this pass, so
3883 we need a clone method. */
3884 opt_pass
* clone () { return new pass_split_all_insns (m_ctxt
); }
3885 virtual unsigned int execute (function
*)
3891 }; // class pass_split_all_insns
3896 make_pass_split_all_insns (gcc::context
*ctxt
)
3898 return new pass_split_all_insns (ctxt
);
3903 const pass_data pass_data_split_after_reload
=
3905 RTL_PASS
, /* type */
3906 "split2", /* name */
3907 OPTGROUP_NONE
, /* optinfo_flags */
3908 TV_NONE
, /* tv_id */
3909 0, /* properties_required */
3910 0, /* properties_provided */
3911 0, /* properties_destroyed */
3912 0, /* todo_flags_start */
3913 0, /* todo_flags_finish */
3916 class pass_split_after_reload
: public rtl_opt_pass
3919 pass_split_after_reload (gcc::context
*ctxt
)
3920 : rtl_opt_pass (pass_data_split_after_reload
, ctxt
)
3923 /* opt_pass methods: */
3924 virtual bool gate (function
*)
3926 /* If optimizing, then go ahead and split insns now. */
3937 virtual unsigned int execute (function
*)
3943 }; // class pass_split_after_reload
3948 make_pass_split_after_reload (gcc::context
*ctxt
)
3950 return new pass_split_after_reload (ctxt
);
3955 const pass_data pass_data_split_before_regstack
=
3957 RTL_PASS
, /* type */
3958 "split3", /* name */
3959 OPTGROUP_NONE
, /* optinfo_flags */
3960 TV_NONE
, /* tv_id */
3961 0, /* properties_required */
3962 0, /* properties_provided */
3963 0, /* properties_destroyed */
3964 0, /* todo_flags_start */
3965 0, /* todo_flags_finish */
3968 class pass_split_before_regstack
: public rtl_opt_pass
3971 pass_split_before_regstack (gcc::context
*ctxt
)
3972 : rtl_opt_pass (pass_data_split_before_regstack
, ctxt
)
3975 /* opt_pass methods: */
3976 virtual bool gate (function
*);
3977 virtual unsigned int execute (function
*)
3983 }; // class pass_split_before_regstack
3986 pass_split_before_regstack::gate (function
*)
3988 #if HAVE_ATTR_length && defined (STACK_REGS)
3989 /* If flow2 creates new instructions which need splitting
3990 and scheduling after reload is not done, they might not be
3991 split until final which doesn't allow splitting
3992 if HAVE_ATTR_length. */
3993 # ifdef INSN_SCHEDULING
3994 return (optimize
&& !flag_schedule_insns_after_reload
);
4006 make_pass_split_before_regstack (gcc::context
*ctxt
)
4008 return new pass_split_before_regstack (ctxt
);
4012 rest_of_handle_split_before_sched2 (void)
4014 #ifdef INSN_SCHEDULING
4022 const pass_data pass_data_split_before_sched2
=
4024 RTL_PASS
, /* type */
4025 "split4", /* name */
4026 OPTGROUP_NONE
, /* optinfo_flags */
4027 TV_NONE
, /* tv_id */
4028 0, /* properties_required */
4029 0, /* properties_provided */
4030 0, /* properties_destroyed */
4031 0, /* todo_flags_start */
4032 0, /* todo_flags_finish */
4035 class pass_split_before_sched2
: public rtl_opt_pass
4038 pass_split_before_sched2 (gcc::context
*ctxt
)
4039 : rtl_opt_pass (pass_data_split_before_sched2
, ctxt
)
4042 /* opt_pass methods: */
4043 virtual bool gate (function
*)
4045 #ifdef INSN_SCHEDULING
4046 return optimize
> 0 && flag_schedule_insns_after_reload
;
4052 virtual unsigned int execute (function
*)
4054 return rest_of_handle_split_before_sched2 ();
4057 }; // class pass_split_before_sched2
4062 make_pass_split_before_sched2 (gcc::context
*ctxt
)
4064 return new pass_split_before_sched2 (ctxt
);
4069 const pass_data pass_data_split_for_shorten_branches
=
4071 RTL_PASS
, /* type */
4072 "split5", /* name */
4073 OPTGROUP_NONE
, /* optinfo_flags */
4074 TV_NONE
, /* tv_id */
4075 0, /* properties_required */
4076 0, /* properties_provided */
4077 0, /* properties_destroyed */
4078 0, /* todo_flags_start */
4079 0, /* todo_flags_finish */
4082 class pass_split_for_shorten_branches
: public rtl_opt_pass
4085 pass_split_for_shorten_branches (gcc::context
*ctxt
)
4086 : rtl_opt_pass (pass_data_split_for_shorten_branches
, ctxt
)
4089 /* opt_pass methods: */
4090 virtual bool gate (function
*)
4092 /* The placement of the splitting that we do for shorten_branches
4093 depends on whether regstack is used by the target or not. */
4094 #if HAVE_ATTR_length && !defined (STACK_REGS)
4101 virtual unsigned int execute (function
*)
4103 return split_all_insns_noflow ();
4106 }; // class pass_split_for_shorten_branches
4111 make_pass_split_for_shorten_branches (gcc::context
*ctxt
)
4113 return new pass_split_for_shorten_branches (ctxt
);
4116 /* (Re)initialize the target information after a change in target. */
4121 /* The information is zero-initialized, so we don't need to do anything
4122 first time round. */
4123 if (!this_target_recog
->x_initialized
)
4125 this_target_recog
->x_initialized
= true;
4128 memset (this_target_recog
->x_bool_attr_masks
, 0,
4129 sizeof (this_target_recog
->x_bool_attr_masks
));
4130 for (unsigned int i
= 0; i
< NUM_INSN_CODES
; ++i
)
4131 if (this_target_recog
->x_op_alt
[i
])
4133 free (this_target_recog
->x_op_alt
[i
]);
4134 this_target_recog
->x_op_alt
[i
] = 0;