1 /* Subroutines used by or related to instruction recognition.
2 Copyright (C) 1987, 1988, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 3, or (at your option) any later
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
25 #include "coretypes.h"
27 #include "rtl-error.h"
29 #include "insn-config.h"
30 #include "insn-attr.h"
31 #include "hard-reg-set.h"
34 #include "addresses.h"
38 #include "basic-block.h"
43 #include "tree-pass.h"
46 #ifndef STACK_PUSH_CODE
47 #ifdef STACK_GROWS_DOWNWARD
48 #define STACK_PUSH_CODE PRE_DEC
50 #define STACK_PUSH_CODE PRE_INC
54 #ifndef STACK_POP_CODE
55 #ifdef STACK_GROWS_DOWNWARD
56 #define STACK_POP_CODE POST_INC
58 #define STACK_POP_CODE POST_DEC
62 #ifndef HAVE_ATTR_enabled
64 get_attr_enabled (rtx insn ATTRIBUTE_UNUSED
)
70 static void validate_replace_rtx_1 (rtx
*, rtx
, rtx
, rtx
, bool);
71 static void validate_replace_src_1 (rtx
*, void *);
72 static rtx
split_insn (rtx
);
74 /* Nonzero means allow operands to be volatile.
75 This should be 0 if you are generating rtl, such as if you are calling
76 the functions in optabs.c and expmed.c (most of the time).
77 This should be 1 if all valid insns need to be recognized,
78 such as in reginfo.c and final.c and reload.c.
80 init_recog and init_recog_no_volatile are responsible for setting this. */
84 struct recog_data recog_data
;
86 /* Contains a vector of operand_alternative structures for every operand.
87 Set up by preprocess_constraints. */
88 struct operand_alternative recog_op_alt
[MAX_RECOG_OPERANDS
][MAX_RECOG_ALTERNATIVES
];
90 /* On return from `constrain_operands', indicate which alternative
93 int which_alternative
;
95 /* Nonzero after end of reload pass.
96 Set to 1 or 0 by toplev.c.
97 Controls the significance of (SUBREG (MEM)). */
101 /* Nonzero after thread_prologue_and_epilogue_insns has run. */
102 int epilogue_completed
;
104 /* Initialize data used by the function `recog'.
105 This must be called once in the compilation of a function
106 before any insn recognition may be done in the function. */
109 init_recog_no_volatile (void)
121 /* Return true if labels in asm operands BODY are LABEL_REFs. */
124 asm_labels_ok (rtx body
)
129 asmop
= extract_asm_operands (body
);
130 if (asmop
== NULL_RTX
)
133 for (i
= 0; i
< ASM_OPERANDS_LABEL_LENGTH (asmop
); i
++)
134 if (GET_CODE (ASM_OPERANDS_LABEL (asmop
, i
)) != LABEL_REF
)
140 /* Check that X is an insn-body for an `asm' with operands
141 and that the operands mentioned in it are legitimate. */
144 check_asm_operands (rtx x
)
148 const char **constraints
;
151 if (!asm_labels_ok (x
))
154 /* Post-reload, be more strict with things. */
155 if (reload_completed
)
157 /* ??? Doh! We've not got the wrapping insn. Cook one up. */
158 extract_insn (make_insn_raw (x
));
159 constrain_operands (1);
160 return which_alternative
>= 0;
163 noperands
= asm_noperands (x
);
169 operands
= XALLOCAVEC (rtx
, noperands
);
170 constraints
= XALLOCAVEC (const char *, noperands
);
172 decode_asm_operands (x
, operands
, NULL
, constraints
, NULL
, NULL
);
174 for (i
= 0; i
< noperands
; i
++)
176 const char *c
= constraints
[i
];
179 if (! asm_operand_ok (operands
[i
], c
, constraints
))
186 /* Static data for the next two routines. */
188 typedef struct change_t
197 static change_t
*changes
;
198 static int changes_allocated
;
200 static int num_changes
= 0;
202 /* Validate a proposed change to OBJECT. LOC is the location in the rtl
203 at which NEW_RTX will be placed. If OBJECT is zero, no validation is done,
204 the change is simply made.
206 Two types of objects are supported: If OBJECT is a MEM, memory_address_p
207 will be called with the address and mode as parameters. If OBJECT is
208 an INSN, CALL_INSN, or JUMP_INSN, the insn will be re-recognized with
211 IN_GROUP is nonzero if this is part of a group of changes that must be
212 performed as a group. In that case, the changes will be stored. The
213 function `apply_change_group' will validate and apply the changes.
215 If IN_GROUP is zero, this is a single change. Try to recognize the insn
216 or validate the memory reference with the change applied. If the result
217 is not valid for the machine, suppress the change and return zero.
218 Otherwise, perform the change and return 1. */
221 validate_change_1 (rtx object
, rtx
*loc
, rtx new_rtx
, bool in_group
, bool unshare
)
225 if (old
== new_rtx
|| rtx_equal_p (old
, new_rtx
))
228 gcc_assert (in_group
!= 0 || num_changes
== 0);
232 /* Save the information describing this change. */
233 if (num_changes
>= changes_allocated
)
235 if (changes_allocated
== 0)
236 /* This value allows for repeated substitutions inside complex
237 indexed addresses, or changes in up to 5 insns. */
238 changes_allocated
= MAX_RECOG_OPERANDS
* 5;
240 changes_allocated
*= 2;
242 changes
= XRESIZEVEC (change_t
, changes
, changes_allocated
);
245 changes
[num_changes
].object
= object
;
246 changes
[num_changes
].loc
= loc
;
247 changes
[num_changes
].old
= old
;
248 changes
[num_changes
].unshare
= unshare
;
250 if (object
&& !MEM_P (object
))
252 /* Set INSN_CODE to force rerecognition of insn. Save old code in
254 changes
[num_changes
].old_code
= INSN_CODE (object
);
255 INSN_CODE (object
) = -1;
260 /* If we are making a group of changes, return 1. Otherwise, validate the
261 change group we made. */
266 return apply_change_group ();
269 /* Wrapper for validate_change_1 without the UNSHARE argument defaulting
273 validate_change (rtx object
, rtx
*loc
, rtx new_rtx
, bool in_group
)
275 return validate_change_1 (object
, loc
, new_rtx
, in_group
, false);
278 /* Wrapper for validate_change_1 without the UNSHARE argument defaulting
282 validate_unshare_change (rtx object
, rtx
*loc
, rtx new_rtx
, bool in_group
)
284 return validate_change_1 (object
, loc
, new_rtx
, in_group
, true);
288 /* Keep X canonicalized if some changes have made it non-canonical; only
289 modifies the operands of X, not (for example) its code. Simplifications
290 are not the job of this routine.
292 Return true if anything was changed. */
294 canonicalize_change_group (rtx insn
, rtx x
)
296 if (COMMUTATIVE_P (x
)
297 && swap_commutative_operands_p (XEXP (x
, 0), XEXP (x
, 1)))
299 /* Oops, the caller has made X no longer canonical.
300 Let's redo the changes in the correct order. */
301 rtx tem
= XEXP (x
, 0);
302 validate_unshare_change (insn
, &XEXP (x
, 0), XEXP (x
, 1), 1);
303 validate_unshare_change (insn
, &XEXP (x
, 1), tem
, 1);
311 /* This subroutine of apply_change_group verifies whether the changes to INSN
312 were valid; i.e. whether INSN can still be recognized.
314 If IN_GROUP is true clobbers which have to be added in order to
315 match the instructions will be added to the current change group.
316 Otherwise the changes will take effect immediately. */
319 insn_invalid_p (rtx insn
, bool in_group
)
321 rtx pat
= PATTERN (insn
);
322 int num_clobbers
= 0;
323 /* If we are before reload and the pattern is a SET, see if we can add
325 int icode
= recog (pat
, insn
,
326 (GET_CODE (pat
) == SET
327 && ! reload_completed
&& ! reload_in_progress
)
328 ? &num_clobbers
: 0);
329 int is_asm
= icode
< 0 && asm_noperands (PATTERN (insn
)) >= 0;
332 /* If this is an asm and the operand aren't legal, then fail. Likewise if
333 this is not an asm and the insn wasn't recognized. */
334 if ((is_asm
&& ! check_asm_operands (PATTERN (insn
)))
335 || (!is_asm
&& icode
< 0))
338 /* If we have to add CLOBBERs, fail if we have to add ones that reference
339 hard registers since our callers can't know if they are live or not.
340 Otherwise, add them. */
341 if (num_clobbers
> 0)
345 if (added_clobbers_hard_reg_p (icode
))
348 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (num_clobbers
+ 1));
349 XVECEXP (newpat
, 0, 0) = pat
;
350 add_clobbers (newpat
, icode
);
352 validate_change (insn
, &PATTERN (insn
), newpat
, 1);
354 PATTERN (insn
) = pat
= newpat
;
357 /* After reload, verify that all constraints are satisfied. */
358 if (reload_completed
)
362 if (! constrain_operands (1))
366 INSN_CODE (insn
) = icode
;
370 /* Return number of changes made and not validated yet. */
372 num_changes_pending (void)
377 /* Tentatively apply the changes numbered NUM and up.
378 Return 1 if all changes are valid, zero otherwise. */
381 verify_changes (int num
)
384 rtx last_validated
= NULL_RTX
;
386 /* The changes have been applied and all INSN_CODEs have been reset to force
389 The changes are valid if we aren't given an object, or if we are
390 given a MEM and it still is a valid address, or if this is in insn
391 and it is recognized. In the latter case, if reload has completed,
392 we also require that the operands meet the constraints for
395 for (i
= num
; i
< num_changes
; i
++)
397 rtx object
= changes
[i
].object
;
399 /* If there is no object to test or if it is the same as the one we
400 already tested, ignore it. */
401 if (object
== 0 || object
== last_validated
)
406 if (! memory_address_addr_space_p (GET_MODE (object
),
408 MEM_ADDR_SPACE (object
)))
411 else if (REG_P (changes
[i
].old
)
412 && asm_noperands (PATTERN (object
)) > 0
413 && REG_EXPR (changes
[i
].old
) != NULL_TREE
414 && DECL_ASSEMBLER_NAME_SET_P (REG_EXPR (changes
[i
].old
))
415 && DECL_REGISTER (REG_EXPR (changes
[i
].old
)))
417 /* Don't allow changes of hard register operands to inline
418 assemblies if they have been defined as register asm ("x"). */
421 else if (DEBUG_INSN_P (object
))
423 else if (insn_invalid_p (object
, true))
425 rtx pat
= PATTERN (object
);
427 /* Perhaps we couldn't recognize the insn because there were
428 extra CLOBBERs at the end. If so, try to re-recognize
429 without the last CLOBBER (later iterations will cause each of
430 them to be eliminated, in turn). But don't do this if we
431 have an ASM_OPERAND. */
432 if (GET_CODE (pat
) == PARALLEL
433 && GET_CODE (XVECEXP (pat
, 0, XVECLEN (pat
, 0) - 1)) == CLOBBER
434 && asm_noperands (PATTERN (object
)) < 0)
438 if (XVECLEN (pat
, 0) == 2)
439 newpat
= XVECEXP (pat
, 0, 0);
445 = gen_rtx_PARALLEL (VOIDmode
,
446 rtvec_alloc (XVECLEN (pat
, 0) - 1));
447 for (j
= 0; j
< XVECLEN (newpat
, 0); j
++)
448 XVECEXP (newpat
, 0, j
) = XVECEXP (pat
, 0, j
);
451 /* Add a new change to this group to replace the pattern
452 with this new pattern. Then consider this change
453 as having succeeded. The change we added will
454 cause the entire call to fail if things remain invalid.
456 Note that this can lose if a later change than the one
457 we are processing specified &XVECEXP (PATTERN (object), 0, X)
458 but this shouldn't occur. */
460 validate_change (object
, &PATTERN (object
), newpat
, 1);
463 else if (GET_CODE (pat
) == USE
|| GET_CODE (pat
) == CLOBBER
464 || GET_CODE (pat
) == VAR_LOCATION
)
465 /* If this insn is a CLOBBER or USE, it is always valid, but is
471 last_validated
= object
;
474 return (i
== num_changes
);
477 /* A group of changes has previously been issued with validate_change
478 and verified with verify_changes. Call df_insn_rescan for each of
479 the insn changed and clear num_changes. */
482 confirm_change_group (void)
485 rtx last_object
= NULL
;
487 for (i
= 0; i
< num_changes
; i
++)
489 rtx object
= changes
[i
].object
;
491 if (changes
[i
].unshare
)
492 *changes
[i
].loc
= copy_rtx (*changes
[i
].loc
);
494 /* Avoid unnecessary rescanning when multiple changes to same instruction
498 if (object
!= last_object
&& last_object
&& INSN_P (last_object
))
499 df_insn_rescan (last_object
);
500 last_object
= object
;
504 if (last_object
&& INSN_P (last_object
))
505 df_insn_rescan (last_object
);
509 /* Apply a group of changes previously issued with `validate_change'.
510 If all changes are valid, call confirm_change_group and return 1,
511 otherwise, call cancel_changes and return 0. */
514 apply_change_group (void)
516 if (verify_changes (0))
518 confirm_change_group ();
529 /* Return the number of changes so far in the current group. */
532 num_validated_changes (void)
537 /* Retract the changes numbered NUM and up. */
540 cancel_changes (int num
)
544 /* Back out all the changes. Do this in the opposite order in which
546 for (i
= num_changes
- 1; i
>= num
; i
--)
548 *changes
[i
].loc
= changes
[i
].old
;
549 if (changes
[i
].object
&& !MEM_P (changes
[i
].object
))
550 INSN_CODE (changes
[i
].object
) = changes
[i
].old_code
;
555 /* A subroutine of validate_replace_rtx_1 that tries to simplify the resulting
559 simplify_while_replacing (rtx
*loc
, rtx to
, rtx object
,
560 enum machine_mode op0_mode
)
563 enum rtx_code code
= GET_CODE (x
);
566 if (SWAPPABLE_OPERANDS_P (x
)
567 && swap_commutative_operands_p (XEXP (x
, 0), XEXP (x
, 1)))
569 validate_unshare_change (object
, loc
,
570 gen_rtx_fmt_ee (COMMUTATIVE_ARITH_P (x
) ? code
571 : swap_condition (code
),
572 GET_MODE (x
), XEXP (x
, 1),
581 /* If we have a PLUS whose second operand is now a CONST_INT, use
582 simplify_gen_binary to try to simplify it.
583 ??? We may want later to remove this, once simplification is
584 separated from this function. */
585 if (CONST_INT_P (XEXP (x
, 1)) && XEXP (x
, 1) == to
)
586 validate_change (object
, loc
,
588 (PLUS
, GET_MODE (x
), XEXP (x
, 0), XEXP (x
, 1)), 1);
591 if (CONST_INT_P (XEXP (x
, 1))
592 || GET_CODE (XEXP (x
, 1)) == CONST_DOUBLE
)
593 validate_change (object
, loc
,
595 (PLUS
, GET_MODE (x
), XEXP (x
, 0),
596 simplify_gen_unary (NEG
,
597 GET_MODE (x
), XEXP (x
, 1),
602 if (GET_MODE (XEXP (x
, 0)) == VOIDmode
)
604 new_rtx
= simplify_gen_unary (code
, GET_MODE (x
), XEXP (x
, 0),
606 /* If any of the above failed, substitute in something that
607 we know won't be recognized. */
609 new_rtx
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
610 validate_change (object
, loc
, new_rtx
, 1);
614 /* All subregs possible to simplify should be simplified. */
615 new_rtx
= simplify_subreg (GET_MODE (x
), SUBREG_REG (x
), op0_mode
,
618 /* Subregs of VOIDmode operands are incorrect. */
619 if (!new_rtx
&& GET_MODE (SUBREG_REG (x
)) == VOIDmode
)
620 new_rtx
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
622 validate_change (object
, loc
, new_rtx
, 1);
626 /* If we are replacing a register with memory, try to change the memory
627 to be the mode required for memory in extract operations (this isn't
628 likely to be an insertion operation; if it was, nothing bad will
629 happen, we might just fail in some cases). */
631 if (MEM_P (XEXP (x
, 0))
632 && CONST_INT_P (XEXP (x
, 1))
633 && CONST_INT_P (XEXP (x
, 2))
634 && !mode_dependent_address_p (XEXP (XEXP (x
, 0), 0))
635 && !MEM_VOLATILE_P (XEXP (x
, 0)))
637 enum machine_mode wanted_mode
= VOIDmode
;
638 enum machine_mode is_mode
= GET_MODE (XEXP (x
, 0));
639 int pos
= INTVAL (XEXP (x
, 2));
641 if (GET_CODE (x
) == ZERO_EXTRACT
)
643 enum machine_mode new_mode
644 = mode_for_extraction (EP_extzv
, 1);
645 if (new_mode
!= MAX_MACHINE_MODE
)
646 wanted_mode
= new_mode
;
648 else if (GET_CODE (x
) == SIGN_EXTRACT
)
650 enum machine_mode new_mode
651 = mode_for_extraction (EP_extv
, 1);
652 if (new_mode
!= MAX_MACHINE_MODE
)
653 wanted_mode
= new_mode
;
656 /* If we have a narrower mode, we can do something. */
657 if (wanted_mode
!= VOIDmode
658 && GET_MODE_SIZE (wanted_mode
) < GET_MODE_SIZE (is_mode
))
660 int offset
= pos
/ BITS_PER_UNIT
;
663 /* If the bytes and bits are counted differently, we
664 must adjust the offset. */
665 if (BYTES_BIG_ENDIAN
!= BITS_BIG_ENDIAN
)
667 (GET_MODE_SIZE (is_mode
) - GET_MODE_SIZE (wanted_mode
) -
670 gcc_assert (GET_MODE_PRECISION (wanted_mode
)
671 == GET_MODE_BITSIZE (wanted_mode
));
672 pos
%= GET_MODE_BITSIZE (wanted_mode
);
674 newmem
= adjust_address_nv (XEXP (x
, 0), wanted_mode
, offset
);
676 validate_change (object
, &XEXP (x
, 2), GEN_INT (pos
), 1);
677 validate_change (object
, &XEXP (x
, 0), newmem
, 1);
688 /* Replace every occurrence of FROM in X with TO. Mark each change with
689 validate_change passing OBJECT. */
692 validate_replace_rtx_1 (rtx
*loc
, rtx from
, rtx to
, rtx object
,
699 enum machine_mode op0_mode
= VOIDmode
;
700 int prev_changes
= num_changes
;
706 fmt
= GET_RTX_FORMAT (code
);
708 op0_mode
= GET_MODE (XEXP (x
, 0));
710 /* X matches FROM if it is the same rtx or they are both referring to the
711 same register in the same mode. Avoid calling rtx_equal_p unless the
712 operands look similar. */
715 || (REG_P (x
) && REG_P (from
)
716 && GET_MODE (x
) == GET_MODE (from
)
717 && REGNO (x
) == REGNO (from
))
718 || (GET_CODE (x
) == GET_CODE (from
) && GET_MODE (x
) == GET_MODE (from
)
719 && rtx_equal_p (x
, from
)))
721 validate_unshare_change (object
, loc
, to
, 1);
725 /* Call ourself recursively to perform the replacements.
726 We must not replace inside already replaced expression, otherwise we
727 get infinite recursion for replacements like (reg X)->(subreg (reg X))
728 done by regmove, so we must special case shared ASM_OPERANDS. */
730 if (GET_CODE (x
) == PARALLEL
)
732 for (j
= XVECLEN (x
, 0) - 1; j
>= 0; j
--)
734 if (j
&& GET_CODE (XVECEXP (x
, 0, j
)) == SET
735 && GET_CODE (SET_SRC (XVECEXP (x
, 0, j
))) == ASM_OPERANDS
)
737 /* Verify that operands are really shared. */
738 gcc_assert (ASM_OPERANDS_INPUT_VEC (SET_SRC (XVECEXP (x
, 0, 0)))
739 == ASM_OPERANDS_INPUT_VEC (SET_SRC (XVECEXP
741 validate_replace_rtx_1 (&SET_DEST (XVECEXP (x
, 0, j
)),
742 from
, to
, object
, simplify
);
745 validate_replace_rtx_1 (&XVECEXP (x
, 0, j
), from
, to
, object
,
750 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
753 validate_replace_rtx_1 (&XEXP (x
, i
), from
, to
, object
, simplify
);
754 else if (fmt
[i
] == 'E')
755 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
756 validate_replace_rtx_1 (&XVECEXP (x
, i
, j
), from
, to
, object
,
760 /* If we didn't substitute, there is nothing more to do. */
761 if (num_changes
== prev_changes
)
764 /* Allow substituted expression to have different mode. This is used by
765 regmove to change mode of pseudo register. */
766 if (fmt
[0] == 'e' && GET_MODE (XEXP (x
, 0)) != VOIDmode
)
767 op0_mode
= GET_MODE (XEXP (x
, 0));
769 /* Do changes needed to keep rtx consistent. Don't do any other
770 simplifications, as it is not our job. */
772 simplify_while_replacing (loc
, to
, object
, op0_mode
);
775 /* Try replacing every occurrence of FROM in subexpression LOC of INSN
776 with TO. After all changes have been made, validate by seeing
777 if INSN is still valid. */
780 validate_replace_rtx_subexp (rtx from
, rtx to
, rtx insn
, rtx
*loc
)
782 validate_replace_rtx_1 (loc
, from
, to
, insn
, true);
783 return apply_change_group ();
786 /* Try replacing every occurrence of FROM in INSN with TO. After all
787 changes have been made, validate by seeing if INSN is still valid. */
790 validate_replace_rtx (rtx from
, rtx to
, rtx insn
)
792 validate_replace_rtx_1 (&PATTERN (insn
), from
, to
, insn
, true);
793 return apply_change_group ();
796 /* Try replacing every occurrence of FROM in WHERE with TO. Assume that WHERE
797 is a part of INSN. After all changes have been made, validate by seeing if
799 validate_replace_rtx (from, to, insn) is equivalent to
800 validate_replace_rtx_part (from, to, &PATTERN (insn), insn). */
803 validate_replace_rtx_part (rtx from
, rtx to
, rtx
*where
, rtx insn
)
805 validate_replace_rtx_1 (where
, from
, to
, insn
, true);
806 return apply_change_group ();
809 /* Same as above, but do not simplify rtx afterwards. */
811 validate_replace_rtx_part_nosimplify (rtx from
, rtx to
, rtx
*where
,
814 validate_replace_rtx_1 (where
, from
, to
, insn
, false);
815 return apply_change_group ();
819 /* Try replacing every occurrence of FROM in INSN with TO. This also
820 will replace in REG_EQUAL and REG_EQUIV notes. */
823 validate_replace_rtx_group (rtx from
, rtx to
, rtx insn
)
826 validate_replace_rtx_1 (&PATTERN (insn
), from
, to
, insn
, true);
827 for (note
= REG_NOTES (insn
); note
; note
= XEXP (note
, 1))
828 if (REG_NOTE_KIND (note
) == REG_EQUAL
829 || REG_NOTE_KIND (note
) == REG_EQUIV
)
830 validate_replace_rtx_1 (&XEXP (note
, 0), from
, to
, insn
, true);
833 /* Function called by note_uses to replace used subexpressions. */
834 struct validate_replace_src_data
836 rtx from
; /* Old RTX */
837 rtx to
; /* New RTX */
838 rtx insn
; /* Insn in which substitution is occurring. */
842 validate_replace_src_1 (rtx
*x
, void *data
)
844 struct validate_replace_src_data
*d
845 = (struct validate_replace_src_data
*) data
;
847 validate_replace_rtx_1 (x
, d
->from
, d
->to
, d
->insn
, true);
850 /* Try replacing every occurrence of FROM in INSN with TO, avoiding
854 validate_replace_src_group (rtx from
, rtx to
, rtx insn
)
856 struct validate_replace_src_data d
;
861 note_uses (&PATTERN (insn
), validate_replace_src_1
, &d
);
864 /* Try simplify INSN.
865 Invoke simplify_rtx () on every SET_SRC and SET_DEST inside the INSN's
866 pattern and return true if something was simplified. */
869 validate_simplify_insn (rtx insn
)
875 pat
= PATTERN (insn
);
877 if (GET_CODE (pat
) == SET
)
879 newpat
= simplify_rtx (SET_SRC (pat
));
880 if (newpat
&& !rtx_equal_p (SET_SRC (pat
), newpat
))
881 validate_change (insn
, &SET_SRC (pat
), newpat
, 1);
882 newpat
= simplify_rtx (SET_DEST (pat
));
883 if (newpat
&& !rtx_equal_p (SET_DEST (pat
), newpat
))
884 validate_change (insn
, &SET_DEST (pat
), newpat
, 1);
886 else if (GET_CODE (pat
) == PARALLEL
)
887 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
889 rtx s
= XVECEXP (pat
, 0, i
);
891 if (GET_CODE (XVECEXP (pat
, 0, i
)) == SET
)
893 newpat
= simplify_rtx (SET_SRC (s
));
894 if (newpat
&& !rtx_equal_p (SET_SRC (s
), newpat
))
895 validate_change (insn
, &SET_SRC (s
), newpat
, 1);
896 newpat
= simplify_rtx (SET_DEST (s
));
897 if (newpat
&& !rtx_equal_p (SET_DEST (s
), newpat
))
898 validate_change (insn
, &SET_DEST (s
), newpat
, 1);
901 return ((num_changes_pending () > 0) && (apply_change_group () > 0));
905 /* Return 1 if the insn using CC0 set by INSN does not contain
906 any ordered tests applied to the condition codes.
907 EQ and NE tests do not count. */
910 next_insn_tests_no_inequality (rtx insn
)
912 rtx next
= next_cc0_user (insn
);
914 /* If there is no next insn, we have to take the conservative choice. */
918 return (INSN_P (next
)
919 && ! inequality_comparisons_p (PATTERN (next
)));
923 /* Return 1 if OP is a valid general operand for machine mode MODE.
924 This is either a register reference, a memory reference,
925 or a constant. In the case of a memory reference, the address
926 is checked for general validity for the target machine.
928 Register and memory references must have mode MODE in order to be valid,
929 but some constants have no machine mode and are valid for any mode.
931 If MODE is VOIDmode, OP is checked for validity for whatever mode
934 The main use of this function is as a predicate in match_operand
935 expressions in the machine description. */
938 general_operand (rtx op
, enum machine_mode mode
)
940 enum rtx_code code
= GET_CODE (op
);
942 if (mode
== VOIDmode
)
943 mode
= GET_MODE (op
);
945 /* Don't accept CONST_INT or anything similar
946 if the caller wants something floating. */
947 if (GET_MODE (op
) == VOIDmode
&& mode
!= VOIDmode
948 && GET_MODE_CLASS (mode
) != MODE_INT
949 && GET_MODE_CLASS (mode
) != MODE_PARTIAL_INT
)
954 && trunc_int_for_mode (INTVAL (op
), mode
) != INTVAL (op
))
958 return ((GET_MODE (op
) == VOIDmode
|| GET_MODE (op
) == mode
960 && (! flag_pic
|| LEGITIMATE_PIC_OPERAND_P (op
))
961 && targetm
.legitimate_constant_p (mode
== VOIDmode
965 /* Except for certain constants with VOIDmode, already checked for,
966 OP's mode must match MODE if MODE specifies a mode. */
968 if (GET_MODE (op
) != mode
)
973 rtx sub
= SUBREG_REG (op
);
975 #ifdef INSN_SCHEDULING
976 /* On machines that have insn scheduling, we want all memory
977 reference to be explicit, so outlaw paradoxical SUBREGs.
978 However, we must allow them after reload so that they can
979 get cleaned up by cleanup_subreg_operands. */
980 if (!reload_completed
&& MEM_P (sub
)
981 && GET_MODE_SIZE (mode
) > GET_MODE_SIZE (GET_MODE (sub
)))
984 /* Avoid memories with nonzero SUBREG_BYTE, as offsetting the memory
985 may result in incorrect reference. We should simplify all valid
986 subregs of MEM anyway. But allow this after reload because we
987 might be called from cleanup_subreg_operands.
989 ??? This is a kludge. */
990 if (!reload_completed
&& SUBREG_BYTE (op
) != 0
994 /* FLOAT_MODE subregs can't be paradoxical. Combine will occasionally
995 create such rtl, and we must reject it. */
996 if (SCALAR_FLOAT_MODE_P (GET_MODE (op
))
997 && GET_MODE_SIZE (GET_MODE (op
)) > GET_MODE_SIZE (GET_MODE (sub
)))
1001 code
= GET_CODE (op
);
1005 return (REGNO (op
) >= FIRST_PSEUDO_REGISTER
1006 || in_hard_reg_set_p (operand_reg_set
, GET_MODE (op
), REGNO (op
)));
1010 rtx y
= XEXP (op
, 0);
1012 if (! volatile_ok
&& MEM_VOLATILE_P (op
))
1015 /* Use the mem's mode, since it will be reloaded thus. */
1016 if (memory_address_addr_space_p (GET_MODE (op
), y
, MEM_ADDR_SPACE (op
)))
1023 /* Return 1 if OP is a valid memory address for a memory reference
1026 The main use of this function is as a predicate in match_operand
1027 expressions in the machine description. */
1030 address_operand (rtx op
, enum machine_mode mode
)
1032 return memory_address_p (mode
, op
);
1035 /* Return 1 if OP is a register reference of mode MODE.
1036 If MODE is VOIDmode, accept a register in any mode.
1038 The main use of this function is as a predicate in match_operand
1039 expressions in the machine description. */
1042 register_operand (rtx op
, enum machine_mode mode
)
1044 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
1047 if (GET_CODE (op
) == SUBREG
)
1049 rtx sub
= SUBREG_REG (op
);
1051 /* Before reload, we can allow (SUBREG (MEM...)) as a register operand
1052 because it is guaranteed to be reloaded into one.
1053 Just make sure the MEM is valid in itself.
1054 (Ideally, (SUBREG (MEM)...) should not exist after reload,
1055 but currently it does result from (SUBREG (REG)...) where the
1056 reg went on the stack.) */
1057 if (! reload_completed
&& MEM_P (sub
))
1058 return general_operand (op
, mode
);
1060 #ifdef CANNOT_CHANGE_MODE_CLASS
1062 && REGNO (sub
) < FIRST_PSEUDO_REGISTER
1063 && REG_CANNOT_CHANGE_MODE_P (REGNO (sub
), GET_MODE (sub
), mode
)
1064 && GET_MODE_CLASS (GET_MODE (sub
)) != MODE_COMPLEX_INT
1065 && GET_MODE_CLASS (GET_MODE (sub
)) != MODE_COMPLEX_FLOAT
)
1069 /* FLOAT_MODE subregs can't be paradoxical. Combine will occasionally
1070 create such rtl, and we must reject it. */
1071 if (SCALAR_FLOAT_MODE_P (GET_MODE (op
))
1072 && GET_MODE_SIZE (GET_MODE (op
)) > GET_MODE_SIZE (GET_MODE (sub
)))
1079 && (REGNO (op
) >= FIRST_PSEUDO_REGISTER
1080 || in_hard_reg_set_p (operand_reg_set
,
1081 GET_MODE (op
), REGNO (op
))));
1084 /* Return 1 for a register in Pmode; ignore the tested mode. */
1087 pmode_register_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1089 return register_operand (op
, Pmode
);
1092 /* Return 1 if OP should match a MATCH_SCRATCH, i.e., if it is a SCRATCH
1093 or a hard register. */
1096 scratch_operand (rtx op
, enum machine_mode mode
)
1098 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
1101 return (GET_CODE (op
) == SCRATCH
1103 && REGNO (op
) < FIRST_PSEUDO_REGISTER
));
1106 /* Return 1 if OP is a valid immediate operand for mode MODE.
1108 The main use of this function is as a predicate in match_operand
1109 expressions in the machine description. */
1112 immediate_operand (rtx op
, enum machine_mode mode
)
1114 /* Don't accept CONST_INT or anything similar
1115 if the caller wants something floating. */
1116 if (GET_MODE (op
) == VOIDmode
&& mode
!= VOIDmode
1117 && GET_MODE_CLASS (mode
) != MODE_INT
1118 && GET_MODE_CLASS (mode
) != MODE_PARTIAL_INT
)
1121 if (CONST_INT_P (op
)
1123 && trunc_int_for_mode (INTVAL (op
), mode
) != INTVAL (op
))
1126 return (CONSTANT_P (op
)
1127 && (GET_MODE (op
) == mode
|| mode
== VOIDmode
1128 || GET_MODE (op
) == VOIDmode
)
1129 && (! flag_pic
|| LEGITIMATE_PIC_OPERAND_P (op
))
1130 && targetm
.legitimate_constant_p (mode
== VOIDmode
1135 /* Returns 1 if OP is an operand that is a CONST_INT. */
1138 const_int_operand (rtx op
, enum machine_mode mode
)
1140 if (!CONST_INT_P (op
))
1143 if (mode
!= VOIDmode
1144 && trunc_int_for_mode (INTVAL (op
), mode
) != INTVAL (op
))
1150 /* Returns 1 if OP is an operand that is a constant integer or constant
1151 floating-point number. */
1154 const_double_operand (rtx op
, enum machine_mode mode
)
1156 /* Don't accept CONST_INT or anything similar
1157 if the caller wants something floating. */
1158 if (GET_MODE (op
) == VOIDmode
&& mode
!= VOIDmode
1159 && GET_MODE_CLASS (mode
) != MODE_INT
1160 && GET_MODE_CLASS (mode
) != MODE_PARTIAL_INT
)
1163 return ((GET_CODE (op
) == CONST_DOUBLE
|| CONST_INT_P (op
))
1164 && (mode
== VOIDmode
|| GET_MODE (op
) == mode
1165 || GET_MODE (op
) == VOIDmode
));
1168 /* Return 1 if OP is a general operand that is not an immediate operand. */
1171 nonimmediate_operand (rtx op
, enum machine_mode mode
)
1173 return (general_operand (op
, mode
) && ! CONSTANT_P (op
));
1176 /* Return 1 if OP is a register reference or immediate value of mode MODE. */
1179 nonmemory_operand (rtx op
, enum machine_mode mode
)
1181 if (CONSTANT_P (op
))
1182 return immediate_operand (op
, mode
);
1184 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
1187 if (GET_CODE (op
) == SUBREG
)
1189 /* Before reload, we can allow (SUBREG (MEM...)) as a register operand
1190 because it is guaranteed to be reloaded into one.
1191 Just make sure the MEM is valid in itself.
1192 (Ideally, (SUBREG (MEM)...) should not exist after reload,
1193 but currently it does result from (SUBREG (REG)...) where the
1194 reg went on the stack.) */
1195 if (! reload_completed
&& MEM_P (SUBREG_REG (op
)))
1196 return general_operand (op
, mode
);
1197 op
= SUBREG_REG (op
);
1201 && (REGNO (op
) >= FIRST_PSEUDO_REGISTER
1202 || in_hard_reg_set_p (operand_reg_set
,
1203 GET_MODE (op
), REGNO (op
))));
1206 /* Return 1 if OP is a valid operand that stands for pushing a
1207 value of mode MODE onto the stack.
1209 The main use of this function is as a predicate in match_operand
1210 expressions in the machine description. */
1213 push_operand (rtx op
, enum machine_mode mode
)
1215 unsigned int rounded_size
= GET_MODE_SIZE (mode
);
1217 #ifdef PUSH_ROUNDING
1218 rounded_size
= PUSH_ROUNDING (rounded_size
);
1224 if (mode
!= VOIDmode
&& GET_MODE (op
) != mode
)
1229 if (rounded_size
== GET_MODE_SIZE (mode
))
1231 if (GET_CODE (op
) != STACK_PUSH_CODE
)
1236 if (GET_CODE (op
) != PRE_MODIFY
1237 || GET_CODE (XEXP (op
, 1)) != PLUS
1238 || XEXP (XEXP (op
, 1), 0) != XEXP (op
, 0)
1239 || !CONST_INT_P (XEXP (XEXP (op
, 1), 1))
1240 #ifdef STACK_GROWS_DOWNWARD
1241 || INTVAL (XEXP (XEXP (op
, 1), 1)) != - (int) rounded_size
1243 || INTVAL (XEXP (XEXP (op
, 1), 1)) != (int) rounded_size
1249 return XEXP (op
, 0) == stack_pointer_rtx
;
1252 /* Return 1 if OP is a valid operand that stands for popping a
1253 value of mode MODE off the stack.
1255 The main use of this function is as a predicate in match_operand
1256 expressions in the machine description. */
1259 pop_operand (rtx op
, enum machine_mode mode
)
1264 if (mode
!= VOIDmode
&& GET_MODE (op
) != mode
)
1269 if (GET_CODE (op
) != STACK_POP_CODE
)
1272 return XEXP (op
, 0) == stack_pointer_rtx
;
1275 /* Return 1 if ADDR is a valid memory address
1276 for mode MODE in address space AS. */
1279 memory_address_addr_space_p (enum machine_mode mode ATTRIBUTE_UNUSED
,
1280 rtx addr
, addr_space_t as
)
1282 #ifdef GO_IF_LEGITIMATE_ADDRESS
1283 gcc_assert (ADDR_SPACE_GENERIC_P (as
));
1284 GO_IF_LEGITIMATE_ADDRESS (mode
, addr
, win
);
1290 return targetm
.addr_space
.legitimate_address_p (mode
, addr
, 0, as
);
1294 /* Return 1 if OP is a valid memory reference with mode MODE,
1295 including a valid address.
1297 The main use of this function is as a predicate in match_operand
1298 expressions in the machine description. */
1301 memory_operand (rtx op
, enum machine_mode mode
)
1305 if (! reload_completed
)
1306 /* Note that no SUBREG is a memory operand before end of reload pass,
1307 because (SUBREG (MEM...)) forces reloading into a register. */
1308 return MEM_P (op
) && general_operand (op
, mode
);
1310 if (mode
!= VOIDmode
&& GET_MODE (op
) != mode
)
1314 if (GET_CODE (inner
) == SUBREG
)
1315 inner
= SUBREG_REG (inner
);
1317 return (MEM_P (inner
) && general_operand (op
, mode
));
1320 /* Return 1 if OP is a valid indirect memory reference with mode MODE;
1321 that is, a memory reference whose address is a general_operand. */
1324 indirect_operand (rtx op
, enum machine_mode mode
)
1326 /* Before reload, a SUBREG isn't in memory (see memory_operand, above). */
1327 if (! reload_completed
1328 && GET_CODE (op
) == SUBREG
&& MEM_P (SUBREG_REG (op
)))
1330 int offset
= SUBREG_BYTE (op
);
1331 rtx inner
= SUBREG_REG (op
);
1333 if (mode
!= VOIDmode
&& GET_MODE (op
) != mode
)
1336 /* The only way that we can have a general_operand as the resulting
1337 address is if OFFSET is zero and the address already is an operand
1338 or if the address is (plus Y (const_int -OFFSET)) and Y is an
1341 return ((offset
== 0 && general_operand (XEXP (inner
, 0), Pmode
))
1342 || (GET_CODE (XEXP (inner
, 0)) == PLUS
1343 && CONST_INT_P (XEXP (XEXP (inner
, 0), 1))
1344 && INTVAL (XEXP (XEXP (inner
, 0), 1)) == -offset
1345 && general_operand (XEXP (XEXP (inner
, 0), 0), Pmode
)));
1349 && memory_operand (op
, mode
)
1350 && general_operand (XEXP (op
, 0), Pmode
));
1353 /* Return 1 if this is an ordered comparison operator (not including
1354 ORDERED and UNORDERED). */
1357 ordered_comparison_operator (rtx op
, enum machine_mode mode
)
1359 if (mode
!= VOIDmode
&& GET_MODE (op
) != mode
)
1361 switch (GET_CODE (op
))
1379 /* Return 1 if this is a comparison operator. This allows the use of
1380 MATCH_OPERATOR to recognize all the branch insns. */
1383 comparison_operator (rtx op
, enum machine_mode mode
)
1385 return ((mode
== VOIDmode
|| GET_MODE (op
) == mode
)
1386 && COMPARISON_P (op
));
1389 /* If BODY is an insn body that uses ASM_OPERANDS, return it. */
1392 extract_asm_operands (rtx body
)
1395 switch (GET_CODE (body
))
1401 /* Single output operand: BODY is (set OUTPUT (asm_operands ...)). */
1402 tmp
= SET_SRC (body
);
1403 if (GET_CODE (tmp
) == ASM_OPERANDS
)
1408 tmp
= XVECEXP (body
, 0, 0);
1409 if (GET_CODE (tmp
) == ASM_OPERANDS
)
1411 if (GET_CODE (tmp
) == SET
)
1413 tmp
= SET_SRC (tmp
);
1414 if (GET_CODE (tmp
) == ASM_OPERANDS
)
1425 /* If BODY is an insn body that uses ASM_OPERANDS,
1426 return the number of operands (both input and output) in the insn.
1427 Otherwise return -1. */
1430 asm_noperands (const_rtx body
)
1432 rtx asm_op
= extract_asm_operands (CONST_CAST_RTX (body
));
1438 if (GET_CODE (body
) == SET
)
1440 else if (GET_CODE (body
) == PARALLEL
)
1443 if (GET_CODE (XVECEXP (body
, 0, 0)) == SET
)
1445 /* Multiple output operands, or 1 output plus some clobbers:
1447 [(set OUTPUT (asm_operands ...))... (clobber (reg ...))...]. */
1448 /* Count backwards through CLOBBERs to determine number of SETs. */
1449 for (i
= XVECLEN (body
, 0); i
> 0; i
--)
1451 if (GET_CODE (XVECEXP (body
, 0, i
- 1)) == SET
)
1453 if (GET_CODE (XVECEXP (body
, 0, i
- 1)) != CLOBBER
)
1457 /* N_SETS is now number of output operands. */
1460 /* Verify that all the SETs we have
1461 came from a single original asm_operands insn
1462 (so that invalid combinations are blocked). */
1463 for (i
= 0; i
< n_sets
; i
++)
1465 rtx elt
= XVECEXP (body
, 0, i
);
1466 if (GET_CODE (elt
) != SET
)
1468 if (GET_CODE (SET_SRC (elt
)) != ASM_OPERANDS
)
1470 /* If these ASM_OPERANDS rtx's came from different original insns
1471 then they aren't allowed together. */
1472 if (ASM_OPERANDS_INPUT_VEC (SET_SRC (elt
))
1473 != ASM_OPERANDS_INPUT_VEC (asm_op
))
1479 /* 0 outputs, but some clobbers:
1480 body is [(asm_operands ...) (clobber (reg ...))...]. */
1481 /* Make sure all the other parallel things really are clobbers. */
1482 for (i
= XVECLEN (body
, 0) - 1; i
> 0; i
--)
1483 if (GET_CODE (XVECEXP (body
, 0, i
)) != CLOBBER
)
1488 return (ASM_OPERANDS_INPUT_LENGTH (asm_op
)
1489 + ASM_OPERANDS_LABEL_LENGTH (asm_op
) + n_sets
);
1492 /* Assuming BODY is an insn body that uses ASM_OPERANDS,
1493 copy its operands (both input and output) into the vector OPERANDS,
1494 the locations of the operands within the insn into the vector OPERAND_LOCS,
1495 and the constraints for the operands into CONSTRAINTS.
1496 Write the modes of the operands into MODES.
1497 Return the assembler-template.
1499 If MODES, OPERAND_LOCS, CONSTRAINTS or OPERANDS is 0,
1500 we don't store that info. */
1503 decode_asm_operands (rtx body
, rtx
*operands
, rtx
**operand_locs
,
1504 const char **constraints
, enum machine_mode
*modes
,
1507 int nbase
= 0, n
, i
;
1510 switch (GET_CODE (body
))
1513 /* Zero output asm: BODY is (asm_operands ...). */
1518 /* Single output asm: BODY is (set OUTPUT (asm_operands ...)). */
1519 asmop
= SET_SRC (body
);
1521 /* The output is in the SET.
1522 Its constraint is in the ASM_OPERANDS itself. */
1524 operands
[0] = SET_DEST (body
);
1526 operand_locs
[0] = &SET_DEST (body
);
1528 constraints
[0] = ASM_OPERANDS_OUTPUT_CONSTRAINT (asmop
);
1530 modes
[0] = GET_MODE (SET_DEST (body
));
1536 int nparallel
= XVECLEN (body
, 0); /* Includes CLOBBERs. */
1538 asmop
= XVECEXP (body
, 0, 0);
1539 if (GET_CODE (asmop
) == SET
)
1541 asmop
= SET_SRC (asmop
);
1543 /* At least one output, plus some CLOBBERs. The outputs are in
1544 the SETs. Their constraints are in the ASM_OPERANDS itself. */
1545 for (i
= 0; i
< nparallel
; i
++)
1547 if (GET_CODE (XVECEXP (body
, 0, i
)) == CLOBBER
)
1548 break; /* Past last SET */
1550 operands
[i
] = SET_DEST (XVECEXP (body
, 0, i
));
1552 operand_locs
[i
] = &SET_DEST (XVECEXP (body
, 0, i
));
1554 constraints
[i
] = XSTR (SET_SRC (XVECEXP (body
, 0, i
)), 1);
1556 modes
[i
] = GET_MODE (SET_DEST (XVECEXP (body
, 0, i
)));
1567 n
= ASM_OPERANDS_INPUT_LENGTH (asmop
);
1568 for (i
= 0; i
< n
; i
++)
1571 operand_locs
[nbase
+ i
] = &ASM_OPERANDS_INPUT (asmop
, i
);
1573 operands
[nbase
+ i
] = ASM_OPERANDS_INPUT (asmop
, i
);
1575 constraints
[nbase
+ i
] = ASM_OPERANDS_INPUT_CONSTRAINT (asmop
, i
);
1577 modes
[nbase
+ i
] = ASM_OPERANDS_INPUT_MODE (asmop
, i
);
1581 n
= ASM_OPERANDS_LABEL_LENGTH (asmop
);
1582 for (i
= 0; i
< n
; i
++)
1585 operand_locs
[nbase
+ i
] = &ASM_OPERANDS_LABEL (asmop
, i
);
1587 operands
[nbase
+ i
] = ASM_OPERANDS_LABEL (asmop
, i
);
1589 constraints
[nbase
+ i
] = "";
1591 modes
[nbase
+ i
] = Pmode
;
1595 *loc
= ASM_OPERANDS_SOURCE_LOCATION (asmop
);
1597 return ASM_OPERANDS_TEMPLATE (asmop
);
1600 /* Check if an asm_operand matches its constraints.
1601 Return > 0 if ok, = 0 if bad, < 0 if inconclusive. */
1604 asm_operand_ok (rtx op
, const char *constraint
, const char **constraints
)
1608 bool incdec_ok
= false;
1611 /* Use constrain_operands after reload. */
1612 gcc_assert (!reload_completed
);
1614 /* Empty constraint string is the same as "X,...,X", i.e. X for as
1615 many alternatives as required to match the other operands. */
1616 if (*constraint
== '\0')
1621 char c
= *constraint
;
1638 case '0': case '1': case '2': case '3': case '4':
1639 case '5': case '6': case '7': case '8': case '9':
1640 /* If caller provided constraints pointer, look up
1641 the maching constraint. Otherwise, our caller should have
1642 given us the proper matching constraint, but we can't
1643 actually fail the check if they didn't. Indicate that
1644 results are inconclusive. */
1648 unsigned long match
;
1650 match
= strtoul (constraint
, &end
, 10);
1652 result
= asm_operand_ok (op
, constraints
[match
], NULL
);
1653 constraint
= (const char *) end
;
1659 while (ISDIGIT (*constraint
));
1666 if (address_operand (op
, VOIDmode
))
1670 case TARGET_MEM_CONSTRAINT
:
1671 case 'V': /* non-offsettable */
1672 if (memory_operand (op
, VOIDmode
))
1676 case 'o': /* offsettable */
1677 if (offsettable_nonstrict_memref_p (op
))
1682 /* ??? Before auto-inc-dec, auto inc/dec insns are not supposed to exist,
1683 excepting those that expand_call created. Further, on some
1684 machines which do not have generalized auto inc/dec, an inc/dec
1685 is not a memory_operand.
1687 Match any memory and hope things are resolved after reload. */
1691 || GET_CODE (XEXP (op
, 0)) == PRE_DEC
1692 || GET_CODE (XEXP (op
, 0)) == POST_DEC
))
1702 || GET_CODE (XEXP (op
, 0)) == PRE_INC
1703 || GET_CODE (XEXP (op
, 0)) == POST_INC
))
1712 if (GET_CODE (op
) == CONST_DOUBLE
1713 || (GET_CODE (op
) == CONST_VECTOR
1714 && GET_MODE_CLASS (GET_MODE (op
)) == MODE_VECTOR_FLOAT
))
1719 if (GET_CODE (op
) == CONST_DOUBLE
1720 && CONST_DOUBLE_OK_FOR_CONSTRAINT_P (op
, 'G', constraint
))
1724 if (GET_CODE (op
) == CONST_DOUBLE
1725 && CONST_DOUBLE_OK_FOR_CONSTRAINT_P (op
, 'H', constraint
))
1730 if (CONST_INT_P (op
)
1731 || (GET_CODE (op
) == CONST_DOUBLE
1732 && GET_MODE (op
) == VOIDmode
))
1737 if (CONSTANT_P (op
) && (! flag_pic
|| LEGITIMATE_PIC_OPERAND_P (op
)))
1742 if (CONST_INT_P (op
)
1743 || (GET_CODE (op
) == CONST_DOUBLE
1744 && GET_MODE (op
) == VOIDmode
))
1749 if (CONST_INT_P (op
)
1750 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op
), 'I', constraint
))
1754 if (CONST_INT_P (op
)
1755 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op
), 'J', constraint
))
1759 if (CONST_INT_P (op
)
1760 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op
), 'K', constraint
))
1764 if (CONST_INT_P (op
)
1765 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op
), 'L', constraint
))
1769 if (CONST_INT_P (op
)
1770 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op
), 'M', constraint
))
1774 if (CONST_INT_P (op
)
1775 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op
), 'N', constraint
))
1779 if (CONST_INT_P (op
)
1780 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op
), 'O', constraint
))
1784 if (CONST_INT_P (op
)
1785 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op
), 'P', constraint
))
1794 if (general_operand (op
, VOIDmode
))
1799 /* For all other letters, we first check for a register class,
1800 otherwise it is an EXTRA_CONSTRAINT. */
1801 if (REG_CLASS_FROM_CONSTRAINT (c
, constraint
) != NO_REGS
)
1804 if (GET_MODE (op
) == BLKmode
)
1806 if (register_operand (op
, VOIDmode
))
1809 #ifdef EXTRA_CONSTRAINT_STR
1810 else if (EXTRA_MEMORY_CONSTRAINT (c
, constraint
))
1811 /* Every memory operand can be reloaded to fit. */
1812 result
= result
|| memory_operand (op
, VOIDmode
);
1813 else if (EXTRA_ADDRESS_CONSTRAINT (c
, constraint
))
1814 /* Every address operand can be reloaded to fit. */
1815 result
= result
|| address_operand (op
, VOIDmode
);
1816 else if (EXTRA_CONSTRAINT_STR (op
, c
, constraint
))
1821 len
= CONSTRAINT_LEN (c
, constraint
);
1824 while (--len
&& *constraint
);
1830 /* For operands without < or > constraints reject side-effects. */
1831 if (!incdec_ok
&& result
&& MEM_P (op
))
1832 switch (GET_CODE (XEXP (op
, 0)))
1849 /* Given an rtx *P, if it is a sum containing an integer constant term,
1850 return the location (type rtx *) of the pointer to that constant term.
1851 Otherwise, return a null pointer. */
1854 find_constant_term_loc (rtx
*p
)
1857 enum rtx_code code
= GET_CODE (*p
);
1859 /* If *P IS such a constant term, P is its location. */
1861 if (code
== CONST_INT
|| code
== SYMBOL_REF
|| code
== LABEL_REF
1865 /* Otherwise, if not a sum, it has no constant term. */
1867 if (GET_CODE (*p
) != PLUS
)
1870 /* If one of the summands is constant, return its location. */
1872 if (XEXP (*p
, 0) && CONSTANT_P (XEXP (*p
, 0))
1873 && XEXP (*p
, 1) && CONSTANT_P (XEXP (*p
, 1)))
1876 /* Otherwise, check each summand for containing a constant term. */
1878 if (XEXP (*p
, 0) != 0)
1880 tem
= find_constant_term_loc (&XEXP (*p
, 0));
1885 if (XEXP (*p
, 1) != 0)
1887 tem
= find_constant_term_loc (&XEXP (*p
, 1));
1895 /* Return 1 if OP is a memory reference
1896 whose address contains no side effects
1897 and remains valid after the addition
1898 of a positive integer less than the
1899 size of the object being referenced.
1901 We assume that the original address is valid and do not check it.
1903 This uses strict_memory_address_p as a subroutine, so
1904 don't use it before reload. */
1907 offsettable_memref_p (rtx op
)
1909 return ((MEM_P (op
))
1910 && offsettable_address_addr_space_p (1, GET_MODE (op
), XEXP (op
, 0),
1911 MEM_ADDR_SPACE (op
)));
1914 /* Similar, but don't require a strictly valid mem ref:
1915 consider pseudo-regs valid as index or base regs. */
1918 offsettable_nonstrict_memref_p (rtx op
)
1920 return ((MEM_P (op
))
1921 && offsettable_address_addr_space_p (0, GET_MODE (op
), XEXP (op
, 0),
1922 MEM_ADDR_SPACE (op
)));
1925 /* Return 1 if Y is a memory address which contains no side effects
1926 and would remain valid for address space AS after the addition of
1927 a positive integer less than the size of that mode.
1929 We assume that the original address is valid and do not check it.
1930 We do check that it is valid for narrower modes.
1932 If STRICTP is nonzero, we require a strictly valid address,
1933 for the sake of use in reload.c. */
1936 offsettable_address_addr_space_p (int strictp
, enum machine_mode mode
, rtx y
,
1939 enum rtx_code ycode
= GET_CODE (y
);
1943 int (*addressp
) (enum machine_mode
, rtx
, addr_space_t
) =
1944 (strictp
? strict_memory_address_addr_space_p
1945 : memory_address_addr_space_p
);
1946 unsigned int mode_sz
= GET_MODE_SIZE (mode
);
1948 if (CONSTANT_ADDRESS_P (y
))
1951 /* Adjusting an offsettable address involves changing to a narrower mode.
1952 Make sure that's OK. */
1954 if (mode_dependent_address_p (y
))
1957 /* ??? How much offset does an offsettable BLKmode reference need?
1958 Clearly that depends on the situation in which it's being used.
1959 However, the current situation in which we test 0xffffffff is
1960 less than ideal. Caveat user. */
1962 mode_sz
= BIGGEST_ALIGNMENT
/ BITS_PER_UNIT
;
1964 /* If the expression contains a constant term,
1965 see if it remains valid when max possible offset is added. */
1967 if ((ycode
== PLUS
) && (y2
= find_constant_term_loc (&y1
)))
1972 *y2
= plus_constant (GET_MODE (y
), *y2
, mode_sz
- 1);
1973 /* Use QImode because an odd displacement may be automatically invalid
1974 for any wider mode. But it should be valid for a single byte. */
1975 good
= (*addressp
) (QImode
, y
, as
);
1977 /* In any case, restore old contents of memory. */
1982 if (GET_RTX_CLASS (ycode
) == RTX_AUTOINC
)
1985 /* The offset added here is chosen as the maximum offset that
1986 any instruction could need to add when operating on something
1987 of the specified mode. We assume that if Y and Y+c are
1988 valid addresses then so is Y+d for all 0<d<c. adjust_address will
1989 go inside a LO_SUM here, so we do so as well. */
1990 if (GET_CODE (y
) == LO_SUM
1992 && mode_sz
<= GET_MODE_ALIGNMENT (mode
) / BITS_PER_UNIT
)
1993 z
= gen_rtx_LO_SUM (GET_MODE (y
), XEXP (y
, 0),
1994 plus_constant (GET_MODE (y
), XEXP (y
, 1),
1997 z
= plus_constant (GET_MODE (y
), y
, mode_sz
- 1);
1999 /* Use QImode because an odd displacement may be automatically invalid
2000 for any wider mode. But it should be valid for a single byte. */
2001 return (*addressp
) (QImode
, z
, as
);
2004 /* Return 1 if ADDR is an address-expression whose effect depends
2005 on the mode of the memory reference it is used in.
2007 Autoincrement addressing is a typical example of mode-dependence
2008 because the amount of the increment depends on the mode. */
2011 mode_dependent_address_p (rtx addr
)
2013 /* Auto-increment addressing with anything other than post_modify
2014 or pre_modify always introduces a mode dependency. Catch such
2015 cases now instead of deferring to the target. */
2016 if (GET_CODE (addr
) == PRE_INC
2017 || GET_CODE (addr
) == POST_INC
2018 || GET_CODE (addr
) == PRE_DEC
2019 || GET_CODE (addr
) == POST_DEC
)
2022 return targetm
.mode_dependent_address_p (addr
);
2025 /* Like extract_insn, but save insn extracted and don't extract again, when
2026 called again for the same insn expecting that recog_data still contain the
2027 valid information. This is used primary by gen_attr infrastructure that
2028 often does extract insn again and again. */
2030 extract_insn_cached (rtx insn
)
2032 if (recog_data
.insn
== insn
&& INSN_CODE (insn
) >= 0)
2034 extract_insn (insn
);
2035 recog_data
.insn
= insn
;
2038 /* Do cached extract_insn, constrain_operands and complain about failures.
2039 Used by insn_attrtab. */
2041 extract_constrain_insn_cached (rtx insn
)
2043 extract_insn_cached (insn
);
2044 if (which_alternative
== -1
2045 && !constrain_operands (reload_completed
))
2046 fatal_insn_not_found (insn
);
2049 /* Do cached constrain_operands and complain about failures. */
2051 constrain_operands_cached (int strict
)
2053 if (which_alternative
== -1)
2054 return constrain_operands (strict
);
2059 /* Analyze INSN and fill in recog_data. */
2062 extract_insn (rtx insn
)
2067 rtx body
= PATTERN (insn
);
2069 recog_data
.n_operands
= 0;
2070 recog_data
.n_alternatives
= 0;
2071 recog_data
.n_dups
= 0;
2072 recog_data
.is_asm
= false;
2074 switch (GET_CODE (body
))
2085 if (GET_CODE (SET_SRC (body
)) == ASM_OPERANDS
)
2090 if ((GET_CODE (XVECEXP (body
, 0, 0)) == SET
2091 && GET_CODE (SET_SRC (XVECEXP (body
, 0, 0))) == ASM_OPERANDS
)
2092 || GET_CODE (XVECEXP (body
, 0, 0)) == ASM_OPERANDS
)
2098 recog_data
.n_operands
= noperands
= asm_noperands (body
);
2101 /* This insn is an `asm' with operands. */
2103 /* expand_asm_operands makes sure there aren't too many operands. */
2104 gcc_assert (noperands
<= MAX_RECOG_OPERANDS
);
2106 /* Now get the operand values and constraints out of the insn. */
2107 decode_asm_operands (body
, recog_data
.operand
,
2108 recog_data
.operand_loc
,
2109 recog_data
.constraints
,
2110 recog_data
.operand_mode
, NULL
);
2111 memset (recog_data
.is_operator
, 0, sizeof recog_data
.is_operator
);
2114 const char *p
= recog_data
.constraints
[0];
2115 recog_data
.n_alternatives
= 1;
2117 recog_data
.n_alternatives
+= (*p
++ == ',');
2119 recog_data
.is_asm
= true;
2122 fatal_insn_not_found (insn
);
2126 /* Ordinary insn: recognize it, get the operands via insn_extract
2127 and get the constraints. */
2129 icode
= recog_memoized (insn
);
2131 fatal_insn_not_found (insn
);
2133 recog_data
.n_operands
= noperands
= insn_data
[icode
].n_operands
;
2134 recog_data
.n_alternatives
= insn_data
[icode
].n_alternatives
;
2135 recog_data
.n_dups
= insn_data
[icode
].n_dups
;
2137 insn_extract (insn
);
2139 for (i
= 0; i
< noperands
; i
++)
2141 recog_data
.constraints
[i
] = insn_data
[icode
].operand
[i
].constraint
;
2142 recog_data
.is_operator
[i
] = insn_data
[icode
].operand
[i
].is_operator
;
2143 recog_data
.operand_mode
[i
] = insn_data
[icode
].operand
[i
].mode
;
2144 /* VOIDmode match_operands gets mode from their real operand. */
2145 if (recog_data
.operand_mode
[i
] == VOIDmode
)
2146 recog_data
.operand_mode
[i
] = GET_MODE (recog_data
.operand
[i
]);
2149 for (i
= 0; i
< noperands
; i
++)
2150 recog_data
.operand_type
[i
]
2151 = (recog_data
.constraints
[i
][0] == '=' ? OP_OUT
2152 : recog_data
.constraints
[i
][0] == '+' ? OP_INOUT
2155 gcc_assert (recog_data
.n_alternatives
<= MAX_RECOG_ALTERNATIVES
);
2157 if (INSN_CODE (insn
) < 0)
2158 for (i
= 0; i
< recog_data
.n_alternatives
; i
++)
2159 recog_data
.alternative_enabled_p
[i
] = true;
2162 recog_data
.insn
= insn
;
2163 for (i
= 0; i
< recog_data
.n_alternatives
; i
++)
2165 which_alternative
= i
;
2166 recog_data
.alternative_enabled_p
[i
] = get_attr_enabled (insn
);
2170 recog_data
.insn
= NULL
;
2171 which_alternative
= -1;
2174 /* After calling extract_insn, you can use this function to extract some
2175 information from the constraint strings into a more usable form.
2176 The collected data is stored in recog_op_alt. */
2178 preprocess_constraints (void)
2182 for (i
= 0; i
< recog_data
.n_operands
; i
++)
2183 memset (recog_op_alt
[i
], 0, (recog_data
.n_alternatives
2184 * sizeof (struct operand_alternative
)));
2186 for (i
= 0; i
< recog_data
.n_operands
; i
++)
2189 struct operand_alternative
*op_alt
;
2190 const char *p
= recog_data
.constraints
[i
];
2192 op_alt
= recog_op_alt
[i
];
2194 for (j
= 0; j
< recog_data
.n_alternatives
; j
++)
2196 op_alt
[j
].cl
= NO_REGS
;
2197 op_alt
[j
].constraint
= p
;
2198 op_alt
[j
].matches
= -1;
2199 op_alt
[j
].matched
= -1;
2201 if (!recog_data
.alternative_enabled_p
[j
])
2203 p
= skip_alternative (p
);
2207 if (*p
== '\0' || *p
== ',')
2209 op_alt
[j
].anything_ok
= 1;
2219 while (c
!= ',' && c
!= '\0');
2220 if (c
== ',' || c
== '\0')
2228 case '=': case '+': case '*': case '%':
2229 case 'E': case 'F': case 'G': case 'H':
2230 case 's': case 'i': case 'n':
2231 case 'I': case 'J': case 'K': case 'L':
2232 case 'M': case 'N': case 'O': case 'P':
2233 /* These don't say anything we care about. */
2237 op_alt
[j
].reject
+= 6;
2240 op_alt
[j
].reject
+= 600;
2243 op_alt
[j
].earlyclobber
= 1;
2246 case '0': case '1': case '2': case '3': case '4':
2247 case '5': case '6': case '7': case '8': case '9':
2250 op_alt
[j
].matches
= strtoul (p
, &end
, 10);
2251 recog_op_alt
[op_alt
[j
].matches
][j
].matched
= i
;
2256 case TARGET_MEM_CONSTRAINT
:
2257 op_alt
[j
].memory_ok
= 1;
2260 op_alt
[j
].decmem_ok
= 1;
2263 op_alt
[j
].incmem_ok
= 1;
2266 op_alt
[j
].nonoffmem_ok
= 1;
2269 op_alt
[j
].offmem_ok
= 1;
2272 op_alt
[j
].anything_ok
= 1;
2276 op_alt
[j
].is_address
= 1;
2277 op_alt
[j
].cl
= reg_class_subunion
[(int) op_alt
[j
].cl
]
2278 [(int) base_reg_class (VOIDmode
, ADDR_SPACE_GENERIC
,
2285 reg_class_subunion
[(int) op_alt
[j
].cl
][(int) GENERAL_REGS
];
2289 if (EXTRA_MEMORY_CONSTRAINT (c
, p
))
2291 op_alt
[j
].memory_ok
= 1;
2294 if (EXTRA_ADDRESS_CONSTRAINT (c
, p
))
2296 op_alt
[j
].is_address
= 1;
2298 = (reg_class_subunion
2299 [(int) op_alt
[j
].cl
]
2300 [(int) base_reg_class (VOIDmode
, ADDR_SPACE_GENERIC
,
2301 ADDRESS
, SCRATCH
)]);
2306 = (reg_class_subunion
2307 [(int) op_alt
[j
].cl
]
2308 [(int) REG_CLASS_FROM_CONSTRAINT ((unsigned char) c
, p
)]);
2311 p
+= CONSTRAINT_LEN (c
, p
);
2317 /* Check the operands of an insn against the insn's operand constraints
2318 and return 1 if they are valid.
2319 The information about the insn's operands, constraints, operand modes
2320 etc. is obtained from the global variables set up by extract_insn.
2322 WHICH_ALTERNATIVE is set to a number which indicates which
2323 alternative of constraints was matched: 0 for the first alternative,
2324 1 for the next, etc.
2326 In addition, when two operands are required to match
2327 and it happens that the output operand is (reg) while the
2328 input operand is --(reg) or ++(reg) (a pre-inc or pre-dec),
2329 make the output operand look like the input.
2330 This is because the output operand is the one the template will print.
2332 This is used in final, just before printing the assembler code and by
2333 the routines that determine an insn's attribute.
2335 If STRICT is a positive nonzero value, it means that we have been
2336 called after reload has been completed. In that case, we must
2337 do all checks strictly. If it is zero, it means that we have been called
2338 before reload has completed. In that case, we first try to see if we can
2339 find an alternative that matches strictly. If not, we try again, this
2340 time assuming that reload will fix up the insn. This provides a "best
2341 guess" for the alternative and is used to compute attributes of insns prior
2342 to reload. A negative value of STRICT is used for this internal call. */
2350 constrain_operands (int strict
)
2352 const char *constraints
[MAX_RECOG_OPERANDS
];
2353 int matching_operands
[MAX_RECOG_OPERANDS
];
2354 int earlyclobber
[MAX_RECOG_OPERANDS
];
2357 struct funny_match funny_match
[MAX_RECOG_OPERANDS
];
2358 int funny_match_index
;
2360 which_alternative
= 0;
2361 if (recog_data
.n_operands
== 0 || recog_data
.n_alternatives
== 0)
2364 for (c
= 0; c
< recog_data
.n_operands
; c
++)
2366 constraints
[c
] = recog_data
.constraints
[c
];
2367 matching_operands
[c
] = -1;
2372 int seen_earlyclobber_at
= -1;
2375 funny_match_index
= 0;
2377 if (!recog_data
.alternative_enabled_p
[which_alternative
])
2381 for (i
= 0; i
< recog_data
.n_operands
; i
++)
2382 constraints
[i
] = skip_alternative (constraints
[i
]);
2384 which_alternative
++;
2388 for (opno
= 0; opno
< recog_data
.n_operands
; opno
++)
2390 rtx op
= recog_data
.operand
[opno
];
2391 enum machine_mode mode
= GET_MODE (op
);
2392 const char *p
= constraints
[opno
];
2398 earlyclobber
[opno
] = 0;
2400 /* A unary operator may be accepted by the predicate, but it
2401 is irrelevant for matching constraints. */
2405 if (GET_CODE (op
) == SUBREG
)
2407 if (REG_P (SUBREG_REG (op
))
2408 && REGNO (SUBREG_REG (op
)) < FIRST_PSEUDO_REGISTER
)
2409 offset
= subreg_regno_offset (REGNO (SUBREG_REG (op
)),
2410 GET_MODE (SUBREG_REG (op
)),
2413 op
= SUBREG_REG (op
);
2416 /* An empty constraint or empty alternative
2417 allows anything which matched the pattern. */
2418 if (*p
== 0 || *p
== ',')
2422 switch (c
= *p
, len
= CONSTRAINT_LEN (c
, p
), c
)
2431 case '?': case '!': case '*': case '%':
2436 /* Ignore rest of this alternative as far as
2437 constraint checking is concerned. */
2440 while (*p
&& *p
!= ',');
2445 earlyclobber
[opno
] = 1;
2446 if (seen_earlyclobber_at
< 0)
2447 seen_earlyclobber_at
= opno
;
2450 case '0': case '1': case '2': case '3': case '4':
2451 case '5': case '6': case '7': case '8': case '9':
2453 /* This operand must be the same as a previous one.
2454 This kind of constraint is used for instructions such
2455 as add when they take only two operands.
2457 Note that the lower-numbered operand is passed first.
2459 If we are not testing strictly, assume that this
2460 constraint will be satisfied. */
2465 match
= strtoul (p
, &end
, 10);
2472 rtx op1
= recog_data
.operand
[match
];
2473 rtx op2
= recog_data
.operand
[opno
];
2475 /* A unary operator may be accepted by the predicate,
2476 but it is irrelevant for matching constraints. */
2478 op1
= XEXP (op1
, 0);
2480 op2
= XEXP (op2
, 0);
2482 val
= operands_match_p (op1
, op2
);
2485 matching_operands
[opno
] = match
;
2486 matching_operands
[match
] = opno
;
2491 /* If output is *x and input is *--x, arrange later
2492 to change the output to *--x as well, since the
2493 output op is the one that will be printed. */
2494 if (val
== 2 && strict
> 0)
2496 funny_match
[funny_match_index
].this_op
= opno
;
2497 funny_match
[funny_match_index
++].other
= match
;
2504 /* p is used for address_operands. When we are called by
2505 gen_reload, no one will have checked that the address is
2506 strictly valid, i.e., that all pseudos requiring hard regs
2507 have gotten them. */
2509 || (strict_memory_address_p (recog_data
.operand_mode
[opno
],
2514 /* No need to check general_operand again;
2515 it was done in insn-recog.c. Well, except that reload
2516 doesn't check the validity of its replacements, but
2517 that should only matter when there's a bug. */
2519 /* Anything goes unless it is a REG and really has a hard reg
2520 but the hard reg is not in the class GENERAL_REGS. */
2524 || GENERAL_REGS
== ALL_REGS
2525 || (reload_in_progress
2526 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
)
2527 || reg_fits_class_p (op
, GENERAL_REGS
, offset
, mode
))
2530 else if (strict
< 0 || general_operand (op
, mode
))
2535 /* This is used for a MATCH_SCRATCH in the cases when
2536 we don't actually need anything. So anything goes
2541 case TARGET_MEM_CONSTRAINT
:
2542 /* Memory operands must be valid, to the extent
2543 required by STRICT. */
2547 && !strict_memory_address_addr_space_p
2548 (GET_MODE (op
), XEXP (op
, 0),
2549 MEM_ADDR_SPACE (op
)))
2552 && !memory_address_addr_space_p
2553 (GET_MODE (op
), XEXP (op
, 0),
2554 MEM_ADDR_SPACE (op
)))
2558 /* Before reload, accept what reload can turn into mem. */
2559 else if (strict
< 0 && CONSTANT_P (op
))
2561 /* During reload, accept a pseudo */
2562 else if (reload_in_progress
&& REG_P (op
)
2563 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
)
2569 && (GET_CODE (XEXP (op
, 0)) == PRE_DEC
2570 || GET_CODE (XEXP (op
, 0)) == POST_DEC
))
2576 && (GET_CODE (XEXP (op
, 0)) == PRE_INC
2577 || GET_CODE (XEXP (op
, 0)) == POST_INC
))
2583 if (GET_CODE (op
) == CONST_DOUBLE
2584 || (GET_CODE (op
) == CONST_VECTOR
2585 && GET_MODE_CLASS (GET_MODE (op
)) == MODE_VECTOR_FLOAT
))
2591 if (GET_CODE (op
) == CONST_DOUBLE
2592 && CONST_DOUBLE_OK_FOR_CONSTRAINT_P (op
, c
, p
))
2597 if (CONST_INT_P (op
)
2598 || (GET_CODE (op
) == CONST_DOUBLE
2599 && GET_MODE (op
) == VOIDmode
))
2602 if (CONSTANT_P (op
))
2607 if (CONST_INT_P (op
)
2608 || (GET_CODE (op
) == CONST_DOUBLE
2609 && GET_MODE (op
) == VOIDmode
))
2621 if (CONST_INT_P (op
)
2622 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op
), c
, p
))
2628 && ((strict
> 0 && ! offsettable_memref_p (op
))
2630 && !(CONSTANT_P (op
) || MEM_P (op
)))
2631 || (reload_in_progress
2633 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
))))
2638 if ((strict
> 0 && offsettable_memref_p (op
))
2639 || (strict
== 0 && offsettable_nonstrict_memref_p (op
))
2640 /* Before reload, accept what reload can handle. */
2642 && (CONSTANT_P (op
) || MEM_P (op
)))
2643 /* During reload, accept a pseudo */
2644 || (reload_in_progress
&& REG_P (op
)
2645 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
))
2654 ? GENERAL_REGS
: REG_CLASS_FROM_CONSTRAINT (c
, p
));
2660 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
)
2661 || (strict
== 0 && GET_CODE (op
) == SCRATCH
)
2663 && reg_fits_class_p (op
, cl
, offset
, mode
)))
2666 #ifdef EXTRA_CONSTRAINT_STR
2667 else if (EXTRA_CONSTRAINT_STR (op
, c
, p
))
2670 else if (EXTRA_MEMORY_CONSTRAINT (c
, p
)
2671 /* Every memory operand can be reloaded to fit. */
2672 && ((strict
< 0 && MEM_P (op
))
2673 /* Before reload, accept what reload can turn
2675 || (strict
< 0 && CONSTANT_P (op
))
2676 /* During reload, accept a pseudo */
2677 || (reload_in_progress
&& REG_P (op
)
2678 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
)))
2680 else if (EXTRA_ADDRESS_CONSTRAINT (c
, p
)
2681 /* Every address operand can be reloaded to fit. */
2684 /* Cater to architectures like IA-64 that define extra memory
2685 constraints without using define_memory_constraint. */
2686 else if (reload_in_progress
2688 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
2689 && reg_renumber
[REGNO (op
)] < 0
2690 && reg_equiv_mem (REGNO (op
)) != 0
2691 && EXTRA_CONSTRAINT_STR
2692 (reg_equiv_mem (REGNO (op
)), c
, p
))
2698 while (p
+= len
, c
);
2700 constraints
[opno
] = p
;
2701 /* If this operand did not win somehow,
2702 this alternative loses. */
2706 /* This alternative won; the operands are ok.
2707 Change whichever operands this alternative says to change. */
2712 /* See if any earlyclobber operand conflicts with some other
2715 if (strict
> 0 && seen_earlyclobber_at
>= 0)
2716 for (eopno
= seen_earlyclobber_at
;
2717 eopno
< recog_data
.n_operands
;
2719 /* Ignore earlyclobber operands now in memory,
2720 because we would often report failure when we have
2721 two memory operands, one of which was formerly a REG. */
2722 if (earlyclobber
[eopno
]
2723 && REG_P (recog_data
.operand
[eopno
]))
2724 for (opno
= 0; opno
< recog_data
.n_operands
; opno
++)
2725 if ((MEM_P (recog_data
.operand
[opno
])
2726 || recog_data
.operand_type
[opno
] != OP_OUT
)
2728 /* Ignore things like match_operator operands. */
2729 && *recog_data
.constraints
[opno
] != 0
2730 && ! (matching_operands
[opno
] == eopno
2731 && operands_match_p (recog_data
.operand
[opno
],
2732 recog_data
.operand
[eopno
]))
2733 && ! safe_from_earlyclobber (recog_data
.operand
[opno
],
2734 recog_data
.operand
[eopno
]))
2739 while (--funny_match_index
>= 0)
2741 recog_data
.operand
[funny_match
[funny_match_index
].other
]
2742 = recog_data
.operand
[funny_match
[funny_match_index
].this_op
];
2746 /* For operands without < or > constraints reject side-effects. */
2747 if (recog_data
.is_asm
)
2749 for (opno
= 0; opno
< recog_data
.n_operands
; opno
++)
2750 if (MEM_P (recog_data
.operand
[opno
]))
2751 switch (GET_CODE (XEXP (recog_data
.operand
[opno
], 0)))
2759 if (strchr (recog_data
.constraints
[opno
], '<') == NULL
2760 && strchr (recog_data
.constraints
[opno
], '>')
2773 which_alternative
++;
2775 while (which_alternative
< recog_data
.n_alternatives
);
2777 which_alternative
= -1;
2778 /* If we are about to reject this, but we are not to test strictly,
2779 try a very loose test. Only return failure if it fails also. */
2781 return constrain_operands (-1);
2786 /* Return true iff OPERAND (assumed to be a REG rtx)
2787 is a hard reg in class CLASS when its regno is offset by OFFSET
2788 and changed to mode MODE.
2789 If REG occupies multiple hard regs, all of them must be in CLASS. */
2792 reg_fits_class_p (const_rtx operand
, reg_class_t cl
, int offset
,
2793 enum machine_mode mode
)
2795 unsigned int regno
= REGNO (operand
);
2800 /* Regno must not be a pseudo register. Offset may be negative. */
2801 return (HARD_REGISTER_NUM_P (regno
)
2802 && HARD_REGISTER_NUM_P (regno
+ offset
)
2803 && in_hard_reg_set_p (reg_class_contents
[(int) cl
], mode
,
2807 /* Split single instruction. Helper function for split_all_insns and
2808 split_all_insns_noflow. Return last insn in the sequence if successful,
2809 or NULL if unsuccessful. */
2812 split_insn (rtx insn
)
2814 /* Split insns here to get max fine-grain parallelism. */
2815 rtx first
= PREV_INSN (insn
);
2816 rtx last
= try_split (PATTERN (insn
), insn
, 1);
2817 rtx insn_set
, last_set
, note
;
2822 /* If the original instruction was a single set that was known to be
2823 equivalent to a constant, see if we can say the same about the last
2824 instruction in the split sequence. The two instructions must set
2825 the same destination. */
2826 insn_set
= single_set (insn
);
2829 last_set
= single_set (last
);
2830 if (last_set
&& rtx_equal_p (SET_DEST (last_set
), SET_DEST (insn_set
)))
2832 note
= find_reg_equal_equiv_note (insn
);
2833 if (note
&& CONSTANT_P (XEXP (note
, 0)))
2834 set_unique_reg_note (last
, REG_EQUAL
, XEXP (note
, 0));
2835 else if (CONSTANT_P (SET_SRC (insn_set
)))
2836 set_unique_reg_note (last
, REG_EQUAL
, SET_SRC (insn_set
));
2840 /* try_split returns the NOTE that INSN became. */
2841 SET_INSN_DELETED (insn
);
2843 /* ??? Coddle to md files that generate subregs in post-reload
2844 splitters instead of computing the proper hard register. */
2845 if (reload_completed
&& first
!= last
)
2847 first
= NEXT_INSN (first
);
2851 cleanup_subreg_operands (first
);
2854 first
= NEXT_INSN (first
);
2861 /* Split all insns in the function. If UPD_LIFE, update life info after. */
2864 split_all_insns (void)
2870 blocks
= sbitmap_alloc (last_basic_block
);
2871 sbitmap_zero (blocks
);
2874 FOR_EACH_BB_REVERSE (bb
)
2877 bool finish
= false;
2879 rtl_profile_for_bb (bb
);
2880 for (insn
= BB_HEAD (bb
); !finish
; insn
= next
)
2882 /* Can't use `next_real_insn' because that might go across
2883 CODE_LABELS and short-out basic blocks. */
2884 next
= NEXT_INSN (insn
);
2885 finish
= (insn
== BB_END (bb
));
2888 rtx set
= single_set (insn
);
2890 /* Don't split no-op move insns. These should silently
2891 disappear later in final. Splitting such insns would
2892 break the code that handles LIBCALL blocks. */
2893 if (set
&& set_noop_p (set
))
2895 /* Nops get in the way while scheduling, so delete them
2896 now if register allocation has already been done. It
2897 is too risky to try to do this before register
2898 allocation, and there are unlikely to be very many
2899 nops then anyways. */
2900 if (reload_completed
)
2901 delete_insn_and_edges (insn
);
2905 if (split_insn (insn
))
2907 SET_BIT (blocks
, bb
->index
);
2915 default_rtl_profile ();
2917 find_many_sub_basic_blocks (blocks
);
2919 #ifdef ENABLE_CHECKING
2920 verify_flow_info ();
2923 sbitmap_free (blocks
);
2926 /* Same as split_all_insns, but do not expect CFG to be available.
2927 Used by machine dependent reorg passes. */
2930 split_all_insns_noflow (void)
2934 for (insn
= get_insns (); insn
; insn
= next
)
2936 next
= NEXT_INSN (insn
);
2939 /* Don't split no-op move insns. These should silently
2940 disappear later in final. Splitting such insns would
2941 break the code that handles LIBCALL blocks. */
2942 rtx set
= single_set (insn
);
2943 if (set
&& set_noop_p (set
))
2945 /* Nops get in the way while scheduling, so delete them
2946 now if register allocation has already been done. It
2947 is too risky to try to do this before register
2948 allocation, and there are unlikely to be very many
2951 ??? Should we use delete_insn when the CFG isn't valid? */
2952 if (reload_completed
)
2953 delete_insn_and_edges (insn
);
2962 #ifdef HAVE_peephole2
2963 struct peep2_insn_data
2969 static struct peep2_insn_data peep2_insn_data
[MAX_INSNS_PER_PEEP2
+ 1];
2970 static int peep2_current
;
2972 static bool peep2_do_rebuild_jump_labels
;
2973 static bool peep2_do_cleanup_cfg
;
2975 /* The number of instructions available to match a peep2. */
2976 int peep2_current_count
;
2978 /* A non-insn marker indicating the last insn of the block.
2979 The live_before regset for this element is correct, indicating
2980 DF_LIVE_OUT for the block. */
2981 #define PEEP2_EOB pc_rtx
2983 /* Wrap N to fit into the peep2_insn_data buffer. */
2986 peep2_buf_position (int n
)
2988 if (n
>= MAX_INSNS_PER_PEEP2
+ 1)
2989 n
-= MAX_INSNS_PER_PEEP2
+ 1;
2993 /* Return the Nth non-note insn after `current', or return NULL_RTX if it
2994 does not exist. Used by the recognizer to find the next insn to match
2995 in a multi-insn pattern. */
2998 peep2_next_insn (int n
)
3000 gcc_assert (n
<= peep2_current_count
);
3002 n
= peep2_buf_position (peep2_current
+ n
);
3004 return peep2_insn_data
[n
].insn
;
3007 /* Return true if REGNO is dead before the Nth non-note insn
3011 peep2_regno_dead_p (int ofs
, int regno
)
3013 gcc_assert (ofs
< MAX_INSNS_PER_PEEP2
+ 1);
3015 ofs
= peep2_buf_position (peep2_current
+ ofs
);
3017 gcc_assert (peep2_insn_data
[ofs
].insn
!= NULL_RTX
);
3019 return ! REGNO_REG_SET_P (peep2_insn_data
[ofs
].live_before
, regno
);
3022 /* Similarly for a REG. */
3025 peep2_reg_dead_p (int ofs
, rtx reg
)
3029 gcc_assert (ofs
< MAX_INSNS_PER_PEEP2
+ 1);
3031 ofs
= peep2_buf_position (peep2_current
+ ofs
);
3033 gcc_assert (peep2_insn_data
[ofs
].insn
!= NULL_RTX
);
3035 regno
= REGNO (reg
);
3036 n
= hard_regno_nregs
[regno
][GET_MODE (reg
)];
3038 if (REGNO_REG_SET_P (peep2_insn_data
[ofs
].live_before
, regno
+ n
))
3043 /* Try to find a hard register of mode MODE, matching the register class in
3044 CLASS_STR, which is available at the beginning of insn CURRENT_INSN and
3045 remains available until the end of LAST_INSN. LAST_INSN may be NULL_RTX,
3046 in which case the only condition is that the register must be available
3047 before CURRENT_INSN.
3048 Registers that already have bits set in REG_SET will not be considered.
3050 If an appropriate register is available, it will be returned and the
3051 corresponding bit(s) in REG_SET will be set; otherwise, NULL_RTX is
3055 peep2_find_free_register (int from
, int to
, const char *class_str
,
3056 enum machine_mode mode
, HARD_REG_SET
*reg_set
)
3058 static int search_ofs
;
3064 gcc_assert (from
< MAX_INSNS_PER_PEEP2
+ 1);
3065 gcc_assert (to
< MAX_INSNS_PER_PEEP2
+ 1);
3067 from
= peep2_buf_position (peep2_current
+ from
);
3068 to
= peep2_buf_position (peep2_current
+ to
);
3070 gcc_assert (peep2_insn_data
[from
].insn
!= NULL_RTX
);
3071 REG_SET_TO_HARD_REG_SET (live
, peep2_insn_data
[from
].live_before
);
3075 gcc_assert (peep2_insn_data
[from
].insn
!= NULL_RTX
);
3077 /* Don't use registers set or clobbered by the insn. */
3078 for (def_rec
= DF_INSN_DEFS (peep2_insn_data
[from
].insn
);
3079 *def_rec
; def_rec
++)
3080 SET_HARD_REG_BIT (live
, DF_REF_REGNO (*def_rec
));
3082 from
= peep2_buf_position (from
+ 1);
3085 cl
= (class_str
[0] == 'r' ? GENERAL_REGS
3086 : REG_CLASS_FROM_CONSTRAINT (class_str
[0], class_str
));
3088 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
3090 int raw_regno
, regno
, success
, j
;
3092 /* Distribute the free registers as much as possible. */
3093 raw_regno
= search_ofs
+ i
;
3094 if (raw_regno
>= FIRST_PSEUDO_REGISTER
)
3095 raw_regno
-= FIRST_PSEUDO_REGISTER
;
3096 #ifdef REG_ALLOC_ORDER
3097 regno
= reg_alloc_order
[raw_regno
];
3102 /* Don't allocate fixed registers. */
3103 if (fixed_regs
[regno
])
3105 /* Don't allocate global registers. */
3106 if (global_regs
[regno
])
3108 /* Make sure the register is of the right class. */
3109 if (! TEST_HARD_REG_BIT (reg_class_contents
[cl
], regno
))
3111 /* And can support the mode we need. */
3112 if (! HARD_REGNO_MODE_OK (regno
, mode
))
3114 /* And that we don't create an extra save/restore. */
3115 if (! call_used_regs
[regno
] && ! df_regs_ever_live_p (regno
))
3117 if (! targetm
.hard_regno_scratch_ok (regno
))
3120 /* And we don't clobber traceback for noreturn functions. */
3121 if ((regno
== FRAME_POINTER_REGNUM
|| regno
== HARD_FRAME_POINTER_REGNUM
)
3122 && (! reload_completed
|| frame_pointer_needed
))
3126 for (j
= hard_regno_nregs
[regno
][mode
] - 1; j
>= 0; j
--)
3128 if (TEST_HARD_REG_BIT (*reg_set
, regno
+ j
)
3129 || TEST_HARD_REG_BIT (live
, regno
+ j
))
3137 add_to_hard_reg_set (reg_set
, mode
, regno
);
3139 /* Start the next search with the next register. */
3140 if (++raw_regno
>= FIRST_PSEUDO_REGISTER
)
3142 search_ofs
= raw_regno
;
3144 return gen_rtx_REG (mode
, regno
);
3152 /* Forget all currently tracked instructions, only remember current
3156 peep2_reinit_state (regset live
)
3160 /* Indicate that all slots except the last holds invalid data. */
3161 for (i
= 0; i
< MAX_INSNS_PER_PEEP2
; ++i
)
3162 peep2_insn_data
[i
].insn
= NULL_RTX
;
3163 peep2_current_count
= 0;
3165 /* Indicate that the last slot contains live_after data. */
3166 peep2_insn_data
[MAX_INSNS_PER_PEEP2
].insn
= PEEP2_EOB
;
3167 peep2_current
= MAX_INSNS_PER_PEEP2
;
3169 COPY_REG_SET (peep2_insn_data
[MAX_INSNS_PER_PEEP2
].live_before
, live
);
3172 /* While scanning basic block BB, we found a match of length MATCH_LEN,
3173 starting at INSN. Perform the replacement, removing the old insns and
3174 replacing them with ATTEMPT. Returns the last insn emitted, or NULL
3175 if the replacement is rejected. */
3178 peep2_attempt (basic_block bb
, rtx insn
, int match_len
, rtx attempt
)
3181 rtx last
, eh_note
, as_note
, before_try
, x
;
3182 rtx old_insn
, new_insn
;
3183 bool was_call
= false;
3185 /* If we are splitting an RTX_FRAME_RELATED_P insn, do not allow it to
3186 match more than one insn, or to be split into more than one insn. */
3187 old_insn
= peep2_insn_data
[peep2_current
].insn
;
3188 if (RTX_FRAME_RELATED_P (old_insn
))
3190 bool any_note
= false;
3196 /* Look for one "active" insn. I.e. ignore any "clobber" insns that
3197 may be in the stream for the purpose of register allocation. */
3198 if (active_insn_p (attempt
))
3201 new_insn
= next_active_insn (attempt
);
3202 if (next_active_insn (new_insn
))
3205 /* We have a 1-1 replacement. Copy over any frame-related info. */
3206 RTX_FRAME_RELATED_P (new_insn
) = 1;
3208 /* Allow the backend to fill in a note during the split. */
3209 for (note
= REG_NOTES (new_insn
); note
; note
= XEXP (note
, 1))
3210 switch (REG_NOTE_KIND (note
))
3212 case REG_FRAME_RELATED_EXPR
:
3213 case REG_CFA_DEF_CFA
:
3214 case REG_CFA_ADJUST_CFA
:
3215 case REG_CFA_OFFSET
:
3216 case REG_CFA_REGISTER
:
3217 case REG_CFA_EXPRESSION
:
3218 case REG_CFA_RESTORE
:
3219 case REG_CFA_SET_VDRAP
:
3226 /* If the backend didn't supply a note, copy one over. */
3228 for (note
= REG_NOTES (old_insn
); note
; note
= XEXP (note
, 1))
3229 switch (REG_NOTE_KIND (note
))
3231 case REG_FRAME_RELATED_EXPR
:
3232 case REG_CFA_DEF_CFA
:
3233 case REG_CFA_ADJUST_CFA
:
3234 case REG_CFA_OFFSET
:
3235 case REG_CFA_REGISTER
:
3236 case REG_CFA_EXPRESSION
:
3237 case REG_CFA_RESTORE
:
3238 case REG_CFA_SET_VDRAP
:
3239 add_reg_note (new_insn
, REG_NOTE_KIND (note
), XEXP (note
, 0));
3246 /* If there still isn't a note, make sure the unwind info sees the
3247 same expression as before the split. */
3250 rtx old_set
, new_set
;
3252 /* The old insn had better have been simple, or annotated. */
3253 old_set
= single_set (old_insn
);
3254 gcc_assert (old_set
!= NULL
);
3256 new_set
= single_set (new_insn
);
3257 if (!new_set
|| !rtx_equal_p (new_set
, old_set
))
3258 add_reg_note (new_insn
, REG_FRAME_RELATED_EXPR
, old_set
);
3261 /* Copy prologue/epilogue status. This is required in order to keep
3262 proper placement of EPILOGUE_BEG and the DW_CFA_remember_state. */
3263 maybe_copy_prologue_epilogue_insn (old_insn
, new_insn
);
3266 /* If we are splitting a CALL_INSN, look for the CALL_INSN
3267 in SEQ and copy our CALL_INSN_FUNCTION_USAGE and other
3268 cfg-related call notes. */
3269 for (i
= 0; i
<= match_len
; ++i
)
3274 j
= peep2_buf_position (peep2_current
+ i
);
3275 old_insn
= peep2_insn_data
[j
].insn
;
3276 if (!CALL_P (old_insn
))
3281 while (new_insn
!= NULL_RTX
)
3283 if (CALL_P (new_insn
))
3285 new_insn
= NEXT_INSN (new_insn
);
3288 gcc_assert (new_insn
!= NULL_RTX
);
3290 CALL_INSN_FUNCTION_USAGE (new_insn
)
3291 = CALL_INSN_FUNCTION_USAGE (old_insn
);
3293 for (note
= REG_NOTES (old_insn
);
3295 note
= XEXP (note
, 1))
3296 switch (REG_NOTE_KIND (note
))
3301 add_reg_note (new_insn
, REG_NOTE_KIND (note
),
3305 /* Discard all other reg notes. */
3309 /* Croak if there is another call in the sequence. */
3310 while (++i
<= match_len
)
3312 j
= peep2_buf_position (peep2_current
+ i
);
3313 old_insn
= peep2_insn_data
[j
].insn
;
3314 gcc_assert (!CALL_P (old_insn
));
3319 /* If we matched any instruction that had a REG_ARGS_SIZE, then
3320 move those notes over to the new sequence. */
3322 for (i
= match_len
; i
>= 0; --i
)
3324 int j
= peep2_buf_position (peep2_current
+ i
);
3325 old_insn
= peep2_insn_data
[j
].insn
;
3327 as_note
= find_reg_note (old_insn
, REG_ARGS_SIZE
, NULL
);
3332 i
= peep2_buf_position (peep2_current
+ match_len
);
3333 eh_note
= find_reg_note (peep2_insn_data
[i
].insn
, REG_EH_REGION
, NULL_RTX
);
3335 /* Replace the old sequence with the new. */
3336 last
= emit_insn_after_setloc (attempt
,
3337 peep2_insn_data
[i
].insn
,
3338 INSN_LOCATOR (peep2_insn_data
[i
].insn
));
3339 before_try
= PREV_INSN (insn
);
3340 delete_insn_chain (insn
, peep2_insn_data
[i
].insn
, false);
3342 /* Re-insert the EH_REGION notes. */
3343 if (eh_note
|| (was_call
&& nonlocal_goto_handler_labels
))
3348 FOR_EACH_EDGE (eh_edge
, ei
, bb
->succs
)
3349 if (eh_edge
->flags
& (EDGE_EH
| EDGE_ABNORMAL_CALL
))
3353 copy_reg_eh_region_note_backward (eh_note
, last
, before_try
);
3356 for (x
= last
; x
!= before_try
; x
= PREV_INSN (x
))
3357 if (x
!= BB_END (bb
)
3358 && (can_throw_internal (x
)
3359 || can_nonlocal_goto (x
)))
3364 nfte
= split_block (bb
, x
);
3365 flags
= (eh_edge
->flags
3366 & (EDGE_EH
| EDGE_ABNORMAL
));
3368 flags
|= EDGE_ABNORMAL_CALL
;
3369 nehe
= make_edge (nfte
->src
, eh_edge
->dest
,
3372 nehe
->probability
= eh_edge
->probability
;
3374 = REG_BR_PROB_BASE
- nehe
->probability
;
3376 peep2_do_cleanup_cfg
|= purge_dead_edges (nfte
->dest
);
3381 /* Converting possibly trapping insn to non-trapping is
3382 possible. Zap dummy outgoing edges. */
3383 peep2_do_cleanup_cfg
|= purge_dead_edges (bb
);
3386 /* Re-insert the ARGS_SIZE notes. */
3388 fixup_args_size_notes (before_try
, last
, INTVAL (XEXP (as_note
, 0)));
3390 /* If we generated a jump instruction, it won't have
3391 JUMP_LABEL set. Recompute after we're done. */
3392 for (x
= last
; x
!= before_try
; x
= PREV_INSN (x
))
3395 peep2_do_rebuild_jump_labels
= true;
3402 /* After performing a replacement in basic block BB, fix up the life
3403 information in our buffer. LAST is the last of the insns that we
3404 emitted as a replacement. PREV is the insn before the start of
3405 the replacement. MATCH_LEN is the number of instructions that were
3406 matched, and which now need to be replaced in the buffer. */
3409 peep2_update_life (basic_block bb
, int match_len
, rtx last
, rtx prev
)
3411 int i
= peep2_buf_position (peep2_current
+ match_len
+ 1);
3415 INIT_REG_SET (&live
);
3416 COPY_REG_SET (&live
, peep2_insn_data
[i
].live_before
);
3418 gcc_assert (peep2_current_count
>= match_len
+ 1);
3419 peep2_current_count
-= match_len
+ 1;
3427 if (peep2_current_count
< MAX_INSNS_PER_PEEP2
)
3429 peep2_current_count
++;
3431 i
= MAX_INSNS_PER_PEEP2
;
3432 peep2_insn_data
[i
].insn
= x
;
3433 df_simulate_one_insn_backwards (bb
, x
, &live
);
3434 COPY_REG_SET (peep2_insn_data
[i
].live_before
, &live
);
3440 CLEAR_REG_SET (&live
);
3445 /* Add INSN, which is in BB, at the end of the peep2 insn buffer if possible.
3446 Return true if we added it, false otherwise. The caller will try to match
3447 peepholes against the buffer if we return false; otherwise it will try to
3448 add more instructions to the buffer. */
3451 peep2_fill_buffer (basic_block bb
, rtx insn
, regset live
)
3455 /* Once we have filled the maximum number of insns the buffer can hold,
3456 allow the caller to match the insns against peepholes. We wait until
3457 the buffer is full in case the target has similar peepholes of different
3458 length; we always want to match the longest if possible. */
3459 if (peep2_current_count
== MAX_INSNS_PER_PEEP2
)
3462 /* If an insn has RTX_FRAME_RELATED_P set, do not allow it to be matched with
3463 any other pattern, lest it change the semantics of the frame info. */
3464 if (RTX_FRAME_RELATED_P (insn
))
3466 /* Let the buffer drain first. */
3467 if (peep2_current_count
> 0)
3469 /* Now the insn will be the only thing in the buffer. */
3472 pos
= peep2_buf_position (peep2_current
+ peep2_current_count
);
3473 peep2_insn_data
[pos
].insn
= insn
;
3474 COPY_REG_SET (peep2_insn_data
[pos
].live_before
, live
);
3475 peep2_current_count
++;
3477 df_simulate_one_insn_forwards (bb
, insn
, live
);
3481 /* Perform the peephole2 optimization pass. */
3484 peephole2_optimize (void)
3491 peep2_do_cleanup_cfg
= false;
3492 peep2_do_rebuild_jump_labels
= false;
3494 df_set_flags (DF_LR_RUN_DCE
);
3495 df_note_add_problem ();
3498 /* Initialize the regsets we're going to use. */
3499 for (i
= 0; i
< MAX_INSNS_PER_PEEP2
+ 1; ++i
)
3500 peep2_insn_data
[i
].live_before
= BITMAP_ALLOC (®_obstack
);
3501 live
= BITMAP_ALLOC (®_obstack
);
3503 FOR_EACH_BB_REVERSE (bb
)
3505 bool past_end
= false;
3508 rtl_profile_for_bb (bb
);
3510 /* Start up propagation. */
3511 bitmap_copy (live
, DF_LR_IN (bb
));
3512 df_simulate_initialize_forwards (bb
, live
);
3513 peep2_reinit_state (live
);
3515 insn
= BB_HEAD (bb
);
3521 if (!past_end
&& !NONDEBUG_INSN_P (insn
))
3524 insn
= NEXT_INSN (insn
);
3525 if (insn
== NEXT_INSN (BB_END (bb
)))
3529 if (!past_end
&& peep2_fill_buffer (bb
, insn
, live
))
3532 /* If we did not fill an empty buffer, it signals the end of the
3534 if (peep2_current_count
== 0)
3537 /* The buffer filled to the current maximum, so try to match. */
3539 pos
= peep2_buf_position (peep2_current
+ peep2_current_count
);
3540 peep2_insn_data
[pos
].insn
= PEEP2_EOB
;
3541 COPY_REG_SET (peep2_insn_data
[pos
].live_before
, live
);
3543 /* Match the peephole. */
3544 head
= peep2_insn_data
[peep2_current
].insn
;
3545 attempt
= peephole2_insns (PATTERN (head
), head
, &match_len
);
3546 if (attempt
!= NULL
)
3548 rtx last
= peep2_attempt (bb
, head
, match_len
, attempt
);
3551 peep2_update_life (bb
, match_len
, last
, PREV_INSN (attempt
));
3556 /* No match: advance the buffer by one insn. */
3557 peep2_current
= peep2_buf_position (peep2_current
+ 1);
3558 peep2_current_count
--;
3562 default_rtl_profile ();
3563 for (i
= 0; i
< MAX_INSNS_PER_PEEP2
+ 1; ++i
)
3564 BITMAP_FREE (peep2_insn_data
[i
].live_before
);
3566 if (peep2_do_rebuild_jump_labels
)
3567 rebuild_jump_labels (get_insns ());
3569 #endif /* HAVE_peephole2 */
3571 /* Common predicates for use with define_bypass. */
3573 /* True if the dependency between OUT_INSN and IN_INSN is on the store
3574 data not the address operand(s) of the store. IN_INSN and OUT_INSN
3575 must be either a single_set or a PARALLEL with SETs inside. */
3578 store_data_bypass_p (rtx out_insn
, rtx in_insn
)
3580 rtx out_set
, in_set
;
3581 rtx out_pat
, in_pat
;
3582 rtx out_exp
, in_exp
;
3585 in_set
= single_set (in_insn
);
3588 if (!MEM_P (SET_DEST (in_set
)))
3591 out_set
= single_set (out_insn
);
3594 if (reg_mentioned_p (SET_DEST (out_set
), SET_DEST (in_set
)))
3599 out_pat
= PATTERN (out_insn
);
3601 if (GET_CODE (out_pat
) != PARALLEL
)
3604 for (i
= 0; i
< XVECLEN (out_pat
, 0); i
++)
3606 out_exp
= XVECEXP (out_pat
, 0, i
);
3608 if (GET_CODE (out_exp
) == CLOBBER
)
3611 gcc_assert (GET_CODE (out_exp
) == SET
);
3613 if (reg_mentioned_p (SET_DEST (out_exp
), SET_DEST (in_set
)))
3620 in_pat
= PATTERN (in_insn
);
3621 gcc_assert (GET_CODE (in_pat
) == PARALLEL
);
3623 for (i
= 0; i
< XVECLEN (in_pat
, 0); i
++)
3625 in_exp
= XVECEXP (in_pat
, 0, i
);
3627 if (GET_CODE (in_exp
) == CLOBBER
)
3630 gcc_assert (GET_CODE (in_exp
) == SET
);
3632 if (!MEM_P (SET_DEST (in_exp
)))
3635 out_set
= single_set (out_insn
);
3638 if (reg_mentioned_p (SET_DEST (out_set
), SET_DEST (in_exp
)))
3643 out_pat
= PATTERN (out_insn
);
3644 gcc_assert (GET_CODE (out_pat
) == PARALLEL
);
3646 for (j
= 0; j
< XVECLEN (out_pat
, 0); j
++)
3648 out_exp
= XVECEXP (out_pat
, 0, j
);
3650 if (GET_CODE (out_exp
) == CLOBBER
)
3653 gcc_assert (GET_CODE (out_exp
) == SET
);
3655 if (reg_mentioned_p (SET_DEST (out_exp
), SET_DEST (in_exp
)))
3665 /* True if the dependency between OUT_INSN and IN_INSN is in the IF_THEN_ELSE
3666 condition, and not the THEN or ELSE branch. OUT_INSN may be either a single
3667 or multiple set; IN_INSN should be single_set for truth, but for convenience
3668 of insn categorization may be any JUMP or CALL insn. */
3671 if_test_bypass_p (rtx out_insn
, rtx in_insn
)
3673 rtx out_set
, in_set
;
3675 in_set
= single_set (in_insn
);
3678 gcc_assert (JUMP_P (in_insn
) || CALL_P (in_insn
));
3682 if (GET_CODE (SET_SRC (in_set
)) != IF_THEN_ELSE
)
3684 in_set
= SET_SRC (in_set
);
3686 out_set
= single_set (out_insn
);
3689 if (reg_mentioned_p (SET_DEST (out_set
), XEXP (in_set
, 1))
3690 || reg_mentioned_p (SET_DEST (out_set
), XEXP (in_set
, 2)))
3698 out_pat
= PATTERN (out_insn
);
3699 gcc_assert (GET_CODE (out_pat
) == PARALLEL
);
3701 for (i
= 0; i
< XVECLEN (out_pat
, 0); i
++)
3703 rtx exp
= XVECEXP (out_pat
, 0, i
);
3705 if (GET_CODE (exp
) == CLOBBER
)
3708 gcc_assert (GET_CODE (exp
) == SET
);
3710 if (reg_mentioned_p (SET_DEST (out_set
), XEXP (in_set
, 1))
3711 || reg_mentioned_p (SET_DEST (out_set
), XEXP (in_set
, 2)))
3720 gate_handle_peephole2 (void)
3722 return (optimize
> 0 && flag_peephole2
);
3726 rest_of_handle_peephole2 (void)
3728 #ifdef HAVE_peephole2
3729 peephole2_optimize ();
3734 struct rtl_opt_pass pass_peephole2
=
3738 "peephole2", /* name */
3739 gate_handle_peephole2
, /* gate */
3740 rest_of_handle_peephole2
, /* execute */
3743 0, /* static_pass_number */
3744 TV_PEEPHOLE2
, /* tv_id */
3745 0, /* properties_required */
3746 0, /* properties_provided */
3747 0, /* properties_destroyed */
3748 0, /* todo_flags_start */
3749 TODO_df_finish
| TODO_verify_rtl_sharing
|
3750 0 /* todo_flags_finish */
3755 rest_of_handle_split_all_insns (void)
3761 struct rtl_opt_pass pass_split_all_insns
=
3765 "split1", /* name */
3767 rest_of_handle_split_all_insns
, /* execute */
3770 0, /* static_pass_number */
3771 TV_NONE
, /* tv_id */
3772 0, /* properties_required */
3773 0, /* properties_provided */
3774 0, /* properties_destroyed */
3775 0, /* todo_flags_start */
3776 0 /* todo_flags_finish */
3781 rest_of_handle_split_after_reload (void)
3783 /* If optimizing, then go ahead and split insns now. */
3791 struct rtl_opt_pass pass_split_after_reload
=
3795 "split2", /* name */
3797 rest_of_handle_split_after_reload
, /* execute */
3800 0, /* static_pass_number */
3801 TV_NONE
, /* tv_id */
3802 0, /* properties_required */
3803 0, /* properties_provided */
3804 0, /* properties_destroyed */
3805 0, /* todo_flags_start */
3806 0 /* todo_flags_finish */
3811 gate_handle_split_before_regstack (void)
3813 #if defined (HAVE_ATTR_length) && defined (STACK_REGS)
3814 /* If flow2 creates new instructions which need splitting
3815 and scheduling after reload is not done, they might not be
3816 split until final which doesn't allow splitting
3817 if HAVE_ATTR_length. */
3818 # ifdef INSN_SCHEDULING
3819 return (optimize
&& !flag_schedule_insns_after_reload
);
3829 rest_of_handle_split_before_regstack (void)
3835 struct rtl_opt_pass pass_split_before_regstack
=
3839 "split3", /* name */
3840 gate_handle_split_before_regstack
, /* gate */
3841 rest_of_handle_split_before_regstack
, /* execute */
3844 0, /* static_pass_number */
3845 TV_NONE
, /* tv_id */
3846 0, /* properties_required */
3847 0, /* properties_provided */
3848 0, /* properties_destroyed */
3849 0, /* todo_flags_start */
3850 0 /* todo_flags_finish */
3855 gate_handle_split_before_sched2 (void)
3857 #ifdef INSN_SCHEDULING
3858 return optimize
> 0 && flag_schedule_insns_after_reload
;
3865 rest_of_handle_split_before_sched2 (void)
3867 #ifdef INSN_SCHEDULING
3873 struct rtl_opt_pass pass_split_before_sched2
=
3877 "split4", /* name */
3878 gate_handle_split_before_sched2
, /* gate */
3879 rest_of_handle_split_before_sched2
, /* execute */
3882 0, /* static_pass_number */
3883 TV_NONE
, /* tv_id */
3884 0, /* properties_required */
3885 0, /* properties_provided */
3886 0, /* properties_destroyed */
3887 0, /* todo_flags_start */
3888 TODO_verify_flow
/* todo_flags_finish */
3892 /* The placement of the splitting that we do for shorten_branches
3893 depends on whether regstack is used by the target or not. */
3895 gate_do_final_split (void)
3897 #if defined (HAVE_ATTR_length) && !defined (STACK_REGS)
3904 struct rtl_opt_pass pass_split_for_shorten_branches
=
3908 "split5", /* name */
3909 gate_do_final_split
, /* gate */
3910 split_all_insns_noflow
, /* execute */
3913 0, /* static_pass_number */
3914 TV_NONE
, /* tv_id */
3915 0, /* properties_required */
3916 0, /* properties_provided */
3917 0, /* properties_destroyed */
3918 0, /* todo_flags_start */
3919 TODO_verify_rtl_sharing
/* todo_flags_finish */