re PR c/7652 (-Wswitch-break : Warn if a switch case falls through)
[gcc.git] / gcc / recog.c
1 /* Subroutines used by or related to instruction recognition.
2 Copyright (C) 1987-2016 Free Software Foundation, Inc.
3
4 This file is part of GCC.
5
6 GCC is free software; you can redistribute it and/or modify it under
7 the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 3, or (at your option) any later
9 version.
10
11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
19
20
21 #include "config.h"
22 #include "system.h"
23 #include "coretypes.h"
24 #include "backend.h"
25 #include "target.h"
26 #include "rtl.h"
27 #include "tree.h"
28 #include "cfghooks.h"
29 #include "df.h"
30 #include "tm_p.h"
31 #include "insn-config.h"
32 #include "regs.h"
33 #include "emit-rtl.h"
34 #include "recog.h"
35 #include "insn-attr.h"
36 #include "addresses.h"
37 #include "cfgrtl.h"
38 #include "cfgbuild.h"
39 #include "cfgcleanup.h"
40 #include "reload.h"
41 #include "tree-pass.h"
42
43 #ifndef STACK_POP_CODE
44 #if STACK_GROWS_DOWNWARD
45 #define STACK_POP_CODE POST_INC
46 #else
47 #define STACK_POP_CODE POST_DEC
48 #endif
49 #endif
50
51 static void validate_replace_rtx_1 (rtx *, rtx, rtx, rtx_insn *, bool);
52 static void validate_replace_src_1 (rtx *, void *);
53 static rtx_insn *split_insn (rtx_insn *);
54
55 struct target_recog default_target_recog;
56 #if SWITCHABLE_TARGET
57 struct target_recog *this_target_recog = &default_target_recog;
58 #endif
59
60 /* Nonzero means allow operands to be volatile.
61 This should be 0 if you are generating rtl, such as if you are calling
62 the functions in optabs.c and expmed.c (most of the time).
63 This should be 1 if all valid insns need to be recognized,
64 such as in reginfo.c and final.c and reload.c.
65
66 init_recog and init_recog_no_volatile are responsible for setting this. */
67
68 int volatile_ok;
69
70 struct recog_data_d recog_data;
71
72 /* Contains a vector of operand_alternative structures, such that
73 operand OP of alternative A is at index A * n_operands + OP.
74 Set up by preprocess_constraints. */
75 const operand_alternative *recog_op_alt;
76
77 /* Used to provide recog_op_alt for asms. */
78 static operand_alternative asm_op_alt[MAX_RECOG_OPERANDS
79 * MAX_RECOG_ALTERNATIVES];
80
81 /* On return from `constrain_operands', indicate which alternative
82 was satisfied. */
83
84 int which_alternative;
85
86 /* Nonzero after end of reload pass.
87 Set to 1 or 0 by toplev.c.
88 Controls the significance of (SUBREG (MEM)). */
89
90 int reload_completed;
91
92 /* Nonzero after thread_prologue_and_epilogue_insns has run. */
93 int epilogue_completed;
94
95 /* Initialize data used by the function `recog'.
96 This must be called once in the compilation of a function
97 before any insn recognition may be done in the function. */
98
99 void
100 init_recog_no_volatile (void)
101 {
102 volatile_ok = 0;
103 }
104
105 void
106 init_recog (void)
107 {
108 volatile_ok = 1;
109 }
110
111 \f
112 /* Return true if labels in asm operands BODY are LABEL_REFs. */
113
114 static bool
115 asm_labels_ok (rtx body)
116 {
117 rtx asmop;
118 int i;
119
120 asmop = extract_asm_operands (body);
121 if (asmop == NULL_RTX)
122 return true;
123
124 for (i = 0; i < ASM_OPERANDS_LABEL_LENGTH (asmop); i++)
125 if (GET_CODE (ASM_OPERANDS_LABEL (asmop, i)) != LABEL_REF)
126 return false;
127
128 return true;
129 }
130
131 /* Check that X is an insn-body for an `asm' with operands
132 and that the operands mentioned in it are legitimate. */
133
134 int
135 check_asm_operands (rtx x)
136 {
137 int noperands;
138 rtx *operands;
139 const char **constraints;
140 int i;
141
142 if (!asm_labels_ok (x))
143 return 0;
144
145 /* Post-reload, be more strict with things. */
146 if (reload_completed)
147 {
148 /* ??? Doh! We've not got the wrapping insn. Cook one up. */
149 rtx_insn *insn = make_insn_raw (x);
150 extract_insn (insn);
151 constrain_operands (1, get_enabled_alternatives (insn));
152 return which_alternative >= 0;
153 }
154
155 noperands = asm_noperands (x);
156 if (noperands < 0)
157 return 0;
158 if (noperands == 0)
159 return 1;
160
161 operands = XALLOCAVEC (rtx, noperands);
162 constraints = XALLOCAVEC (const char *, noperands);
163
164 decode_asm_operands (x, operands, NULL, constraints, NULL, NULL);
165
166 for (i = 0; i < noperands; i++)
167 {
168 const char *c = constraints[i];
169 if (c[0] == '%')
170 c++;
171 if (! asm_operand_ok (operands[i], c, constraints))
172 return 0;
173 }
174
175 return 1;
176 }
177 \f
178 /* Static data for the next two routines. */
179
180 struct change_t
181 {
182 rtx object;
183 int old_code;
184 rtx *loc;
185 rtx old;
186 bool unshare;
187 };
188
189 static change_t *changes;
190 static int changes_allocated;
191
192 static int num_changes = 0;
193
194 /* Validate a proposed change to OBJECT. LOC is the location in the rtl
195 at which NEW_RTX will be placed. If OBJECT is zero, no validation is done,
196 the change is simply made.
197
198 Two types of objects are supported: If OBJECT is a MEM, memory_address_p
199 will be called with the address and mode as parameters. If OBJECT is
200 an INSN, CALL_INSN, or JUMP_INSN, the insn will be re-recognized with
201 the change in place.
202
203 IN_GROUP is nonzero if this is part of a group of changes that must be
204 performed as a group. In that case, the changes will be stored. The
205 function `apply_change_group' will validate and apply the changes.
206
207 If IN_GROUP is zero, this is a single change. Try to recognize the insn
208 or validate the memory reference with the change applied. If the result
209 is not valid for the machine, suppress the change and return zero.
210 Otherwise, perform the change and return 1. */
211
212 static bool
213 validate_change_1 (rtx object, rtx *loc, rtx new_rtx, bool in_group, bool unshare)
214 {
215 rtx old = *loc;
216
217 if (old == new_rtx || rtx_equal_p (old, new_rtx))
218 return 1;
219
220 gcc_assert (in_group != 0 || num_changes == 0);
221
222 *loc = new_rtx;
223
224 /* Save the information describing this change. */
225 if (num_changes >= changes_allocated)
226 {
227 if (changes_allocated == 0)
228 /* This value allows for repeated substitutions inside complex
229 indexed addresses, or changes in up to 5 insns. */
230 changes_allocated = MAX_RECOG_OPERANDS * 5;
231 else
232 changes_allocated *= 2;
233
234 changes = XRESIZEVEC (change_t, changes, changes_allocated);
235 }
236
237 changes[num_changes].object = object;
238 changes[num_changes].loc = loc;
239 changes[num_changes].old = old;
240 changes[num_changes].unshare = unshare;
241
242 if (object && !MEM_P (object))
243 {
244 /* Set INSN_CODE to force rerecognition of insn. Save old code in
245 case invalid. */
246 changes[num_changes].old_code = INSN_CODE (object);
247 INSN_CODE (object) = -1;
248 }
249
250 num_changes++;
251
252 /* If we are making a group of changes, return 1. Otherwise, validate the
253 change group we made. */
254
255 if (in_group)
256 return 1;
257 else
258 return apply_change_group ();
259 }
260
261 /* Wrapper for validate_change_1 without the UNSHARE argument defaulting
262 UNSHARE to false. */
263
264 bool
265 validate_change (rtx object, rtx *loc, rtx new_rtx, bool in_group)
266 {
267 return validate_change_1 (object, loc, new_rtx, in_group, false);
268 }
269
270 /* Wrapper for validate_change_1 without the UNSHARE argument defaulting
271 UNSHARE to true. */
272
273 bool
274 validate_unshare_change (rtx object, rtx *loc, rtx new_rtx, bool in_group)
275 {
276 return validate_change_1 (object, loc, new_rtx, in_group, true);
277 }
278
279
280 /* Keep X canonicalized if some changes have made it non-canonical; only
281 modifies the operands of X, not (for example) its code. Simplifications
282 are not the job of this routine.
283
284 Return true if anything was changed. */
285 bool
286 canonicalize_change_group (rtx_insn *insn, rtx x)
287 {
288 if (COMMUTATIVE_P (x)
289 && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
290 {
291 /* Oops, the caller has made X no longer canonical.
292 Let's redo the changes in the correct order. */
293 rtx tem = XEXP (x, 0);
294 validate_unshare_change (insn, &XEXP (x, 0), XEXP (x, 1), 1);
295 validate_unshare_change (insn, &XEXP (x, 1), tem, 1);
296 return true;
297 }
298 else
299 return false;
300 }
301
302
303 /* This subroutine of apply_change_group verifies whether the changes to INSN
304 were valid; i.e. whether INSN can still be recognized.
305
306 If IN_GROUP is true clobbers which have to be added in order to
307 match the instructions will be added to the current change group.
308 Otherwise the changes will take effect immediately. */
309
310 int
311 insn_invalid_p (rtx_insn *insn, bool in_group)
312 {
313 rtx pat = PATTERN (insn);
314 int num_clobbers = 0;
315 /* If we are before reload and the pattern is a SET, see if we can add
316 clobbers. */
317 int icode = recog (pat, insn,
318 (GET_CODE (pat) == SET
319 && ! reload_completed
320 && ! reload_in_progress)
321 ? &num_clobbers : 0);
322 int is_asm = icode < 0 && asm_noperands (PATTERN (insn)) >= 0;
323
324
325 /* If this is an asm and the operand aren't legal, then fail. Likewise if
326 this is not an asm and the insn wasn't recognized. */
327 if ((is_asm && ! check_asm_operands (PATTERN (insn)))
328 || (!is_asm && icode < 0))
329 return 1;
330
331 /* If we have to add CLOBBERs, fail if we have to add ones that reference
332 hard registers since our callers can't know if they are live or not.
333 Otherwise, add them. */
334 if (num_clobbers > 0)
335 {
336 rtx newpat;
337
338 if (added_clobbers_hard_reg_p (icode))
339 return 1;
340
341 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (num_clobbers + 1));
342 XVECEXP (newpat, 0, 0) = pat;
343 add_clobbers (newpat, icode);
344 if (in_group)
345 validate_change (insn, &PATTERN (insn), newpat, 1);
346 else
347 PATTERN (insn) = pat = newpat;
348 }
349
350 /* After reload, verify that all constraints are satisfied. */
351 if (reload_completed)
352 {
353 extract_insn (insn);
354
355 if (! constrain_operands (1, get_preferred_alternatives (insn)))
356 return 1;
357 }
358
359 INSN_CODE (insn) = icode;
360 return 0;
361 }
362
363 /* Return number of changes made and not validated yet. */
364 int
365 num_changes_pending (void)
366 {
367 return num_changes;
368 }
369
370 /* Tentatively apply the changes numbered NUM and up.
371 Return 1 if all changes are valid, zero otherwise. */
372
373 int
374 verify_changes (int num)
375 {
376 int i;
377 rtx last_validated = NULL_RTX;
378
379 /* The changes have been applied and all INSN_CODEs have been reset to force
380 rerecognition.
381
382 The changes are valid if we aren't given an object, or if we are
383 given a MEM and it still is a valid address, or if this is in insn
384 and it is recognized. In the latter case, if reload has completed,
385 we also require that the operands meet the constraints for
386 the insn. */
387
388 for (i = num; i < num_changes; i++)
389 {
390 rtx object = changes[i].object;
391
392 /* If there is no object to test or if it is the same as the one we
393 already tested, ignore it. */
394 if (object == 0 || object == last_validated)
395 continue;
396
397 if (MEM_P (object))
398 {
399 if (! memory_address_addr_space_p (GET_MODE (object),
400 XEXP (object, 0),
401 MEM_ADDR_SPACE (object)))
402 break;
403 }
404 else if (/* changes[i].old might be zero, e.g. when putting a
405 REG_FRAME_RELATED_EXPR into a previously empty list. */
406 changes[i].old
407 && REG_P (changes[i].old)
408 && asm_noperands (PATTERN (object)) > 0
409 && REG_EXPR (changes[i].old) != NULL_TREE
410 && DECL_ASSEMBLER_NAME_SET_P (REG_EXPR (changes[i].old))
411 && DECL_REGISTER (REG_EXPR (changes[i].old)))
412 {
413 /* Don't allow changes of hard register operands to inline
414 assemblies if they have been defined as register asm ("x"). */
415 break;
416 }
417 else if (DEBUG_INSN_P (object))
418 continue;
419 else if (insn_invalid_p (as_a <rtx_insn *> (object), true))
420 {
421 rtx pat = PATTERN (object);
422
423 /* Perhaps we couldn't recognize the insn because there were
424 extra CLOBBERs at the end. If so, try to re-recognize
425 without the last CLOBBER (later iterations will cause each of
426 them to be eliminated, in turn). But don't do this if we
427 have an ASM_OPERAND. */
428 if (GET_CODE (pat) == PARALLEL
429 && GET_CODE (XVECEXP (pat, 0, XVECLEN (pat, 0) - 1)) == CLOBBER
430 && asm_noperands (PATTERN (object)) < 0)
431 {
432 rtx newpat;
433
434 if (XVECLEN (pat, 0) == 2)
435 newpat = XVECEXP (pat, 0, 0);
436 else
437 {
438 int j;
439
440 newpat
441 = gen_rtx_PARALLEL (VOIDmode,
442 rtvec_alloc (XVECLEN (pat, 0) - 1));
443 for (j = 0; j < XVECLEN (newpat, 0); j++)
444 XVECEXP (newpat, 0, j) = XVECEXP (pat, 0, j);
445 }
446
447 /* Add a new change to this group to replace the pattern
448 with this new pattern. Then consider this change
449 as having succeeded. The change we added will
450 cause the entire call to fail if things remain invalid.
451
452 Note that this can lose if a later change than the one
453 we are processing specified &XVECEXP (PATTERN (object), 0, X)
454 but this shouldn't occur. */
455
456 validate_change (object, &PATTERN (object), newpat, 1);
457 continue;
458 }
459 else if (GET_CODE (pat) == USE || GET_CODE (pat) == CLOBBER
460 || GET_CODE (pat) == VAR_LOCATION)
461 /* If this insn is a CLOBBER or USE, it is always valid, but is
462 never recognized. */
463 continue;
464 else
465 break;
466 }
467 last_validated = object;
468 }
469
470 return (i == num_changes);
471 }
472
473 /* A group of changes has previously been issued with validate_change
474 and verified with verify_changes. Call df_insn_rescan for each of
475 the insn changed and clear num_changes. */
476
477 void
478 confirm_change_group (void)
479 {
480 int i;
481 rtx last_object = NULL;
482
483 for (i = 0; i < num_changes; i++)
484 {
485 rtx object = changes[i].object;
486
487 if (changes[i].unshare)
488 *changes[i].loc = copy_rtx (*changes[i].loc);
489
490 /* Avoid unnecessary rescanning when multiple changes to same instruction
491 are made. */
492 if (object)
493 {
494 if (object != last_object && last_object && INSN_P (last_object))
495 df_insn_rescan (as_a <rtx_insn *> (last_object));
496 last_object = object;
497 }
498 }
499
500 if (last_object && INSN_P (last_object))
501 df_insn_rescan (as_a <rtx_insn *> (last_object));
502 num_changes = 0;
503 }
504
505 /* Apply a group of changes previously issued with `validate_change'.
506 If all changes are valid, call confirm_change_group and return 1,
507 otherwise, call cancel_changes and return 0. */
508
509 int
510 apply_change_group (void)
511 {
512 if (verify_changes (0))
513 {
514 confirm_change_group ();
515 return 1;
516 }
517 else
518 {
519 cancel_changes (0);
520 return 0;
521 }
522 }
523
524
525 /* Return the number of changes so far in the current group. */
526
527 int
528 num_validated_changes (void)
529 {
530 return num_changes;
531 }
532
533 /* Retract the changes numbered NUM and up. */
534
535 void
536 cancel_changes (int num)
537 {
538 int i;
539
540 /* Back out all the changes. Do this in the opposite order in which
541 they were made. */
542 for (i = num_changes - 1; i >= num; i--)
543 {
544 *changes[i].loc = changes[i].old;
545 if (changes[i].object && !MEM_P (changes[i].object))
546 INSN_CODE (changes[i].object) = changes[i].old_code;
547 }
548 num_changes = num;
549 }
550
551 /* Reduce conditional compilation elsewhere. */
552 /* A subroutine of validate_replace_rtx_1 that tries to simplify the resulting
553 rtx. */
554
555 static void
556 simplify_while_replacing (rtx *loc, rtx to, rtx_insn *object,
557 machine_mode op0_mode)
558 {
559 rtx x = *loc;
560 enum rtx_code code = GET_CODE (x);
561 rtx new_rtx = NULL_RTX;
562
563 if (SWAPPABLE_OPERANDS_P (x)
564 && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
565 {
566 validate_unshare_change (object, loc,
567 gen_rtx_fmt_ee (COMMUTATIVE_ARITH_P (x) ? code
568 : swap_condition (code),
569 GET_MODE (x), XEXP (x, 1),
570 XEXP (x, 0)), 1);
571 x = *loc;
572 code = GET_CODE (x);
573 }
574
575 /* Canonicalize arithmetics with all constant operands. */
576 switch (GET_RTX_CLASS (code))
577 {
578 case RTX_UNARY:
579 if (CONSTANT_P (XEXP (x, 0)))
580 new_rtx = simplify_unary_operation (code, GET_MODE (x), XEXP (x, 0),
581 op0_mode);
582 break;
583 case RTX_COMM_ARITH:
584 case RTX_BIN_ARITH:
585 if (CONSTANT_P (XEXP (x, 0)) && CONSTANT_P (XEXP (x, 1)))
586 new_rtx = simplify_binary_operation (code, GET_MODE (x), XEXP (x, 0),
587 XEXP (x, 1));
588 break;
589 case RTX_COMPARE:
590 case RTX_COMM_COMPARE:
591 if (CONSTANT_P (XEXP (x, 0)) && CONSTANT_P (XEXP (x, 1)))
592 new_rtx = simplify_relational_operation (code, GET_MODE (x), op0_mode,
593 XEXP (x, 0), XEXP (x, 1));
594 break;
595 default:
596 break;
597 }
598 if (new_rtx)
599 {
600 validate_change (object, loc, new_rtx, 1);
601 return;
602 }
603
604 switch (code)
605 {
606 case PLUS:
607 /* If we have a PLUS whose second operand is now a CONST_INT, use
608 simplify_gen_binary to try to simplify it.
609 ??? We may want later to remove this, once simplification is
610 separated from this function. */
611 if (CONST_INT_P (XEXP (x, 1)) && XEXP (x, 1) == to)
612 validate_change (object, loc,
613 simplify_gen_binary
614 (PLUS, GET_MODE (x), XEXP (x, 0), XEXP (x, 1)), 1);
615 break;
616 case MINUS:
617 if (CONST_SCALAR_INT_P (XEXP (x, 1)))
618 validate_change (object, loc,
619 simplify_gen_binary
620 (PLUS, GET_MODE (x), XEXP (x, 0),
621 simplify_gen_unary (NEG,
622 GET_MODE (x), XEXP (x, 1),
623 GET_MODE (x))), 1);
624 break;
625 case ZERO_EXTEND:
626 case SIGN_EXTEND:
627 if (GET_MODE (XEXP (x, 0)) == VOIDmode)
628 {
629 new_rtx = simplify_gen_unary (code, GET_MODE (x), XEXP (x, 0),
630 op0_mode);
631 /* If any of the above failed, substitute in something that
632 we know won't be recognized. */
633 if (!new_rtx)
634 new_rtx = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
635 validate_change (object, loc, new_rtx, 1);
636 }
637 break;
638 case SUBREG:
639 /* All subregs possible to simplify should be simplified. */
640 new_rtx = simplify_subreg (GET_MODE (x), SUBREG_REG (x), op0_mode,
641 SUBREG_BYTE (x));
642
643 /* Subregs of VOIDmode operands are incorrect. */
644 if (!new_rtx && GET_MODE (SUBREG_REG (x)) == VOIDmode)
645 new_rtx = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
646 if (new_rtx)
647 validate_change (object, loc, new_rtx, 1);
648 break;
649 case ZERO_EXTRACT:
650 case SIGN_EXTRACT:
651 /* If we are replacing a register with memory, try to change the memory
652 to be the mode required for memory in extract operations (this isn't
653 likely to be an insertion operation; if it was, nothing bad will
654 happen, we might just fail in some cases). */
655
656 if (MEM_P (XEXP (x, 0))
657 && CONST_INT_P (XEXP (x, 1))
658 && CONST_INT_P (XEXP (x, 2))
659 && !mode_dependent_address_p (XEXP (XEXP (x, 0), 0),
660 MEM_ADDR_SPACE (XEXP (x, 0)))
661 && !MEM_VOLATILE_P (XEXP (x, 0)))
662 {
663 machine_mode wanted_mode = VOIDmode;
664 machine_mode is_mode = GET_MODE (XEXP (x, 0));
665 int pos = INTVAL (XEXP (x, 2));
666
667 if (GET_CODE (x) == ZERO_EXTRACT && targetm.have_extzv ())
668 {
669 wanted_mode = insn_data[targetm.code_for_extzv].operand[1].mode;
670 if (wanted_mode == VOIDmode)
671 wanted_mode = word_mode;
672 }
673 else if (GET_CODE (x) == SIGN_EXTRACT && targetm.have_extv ())
674 {
675 wanted_mode = insn_data[targetm.code_for_extv].operand[1].mode;
676 if (wanted_mode == VOIDmode)
677 wanted_mode = word_mode;
678 }
679
680 /* If we have a narrower mode, we can do something. */
681 if (wanted_mode != VOIDmode
682 && GET_MODE_SIZE (wanted_mode) < GET_MODE_SIZE (is_mode))
683 {
684 int offset = pos / BITS_PER_UNIT;
685 rtx newmem;
686
687 /* If the bytes and bits are counted differently, we
688 must adjust the offset. */
689 if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN)
690 offset =
691 (GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (wanted_mode) -
692 offset);
693
694 gcc_assert (GET_MODE_PRECISION (wanted_mode)
695 == GET_MODE_BITSIZE (wanted_mode));
696 pos %= GET_MODE_BITSIZE (wanted_mode);
697
698 newmem = adjust_address_nv (XEXP (x, 0), wanted_mode, offset);
699
700 validate_change (object, &XEXP (x, 2), GEN_INT (pos), 1);
701 validate_change (object, &XEXP (x, 0), newmem, 1);
702 }
703 }
704
705 break;
706
707 default:
708 break;
709 }
710 }
711
712 /* Replace every occurrence of FROM in X with TO. Mark each change with
713 validate_change passing OBJECT. */
714
715 static void
716 validate_replace_rtx_1 (rtx *loc, rtx from, rtx to, rtx_insn *object,
717 bool simplify)
718 {
719 int i, j;
720 const char *fmt;
721 rtx x = *loc;
722 enum rtx_code code;
723 machine_mode op0_mode = VOIDmode;
724 int prev_changes = num_changes;
725
726 if (!x)
727 return;
728
729 code = GET_CODE (x);
730 fmt = GET_RTX_FORMAT (code);
731 if (fmt[0] == 'e')
732 op0_mode = GET_MODE (XEXP (x, 0));
733
734 /* X matches FROM if it is the same rtx or they are both referring to the
735 same register in the same mode. Avoid calling rtx_equal_p unless the
736 operands look similar. */
737
738 if (x == from
739 || (REG_P (x) && REG_P (from)
740 && GET_MODE (x) == GET_MODE (from)
741 && REGNO (x) == REGNO (from))
742 || (GET_CODE (x) == GET_CODE (from) && GET_MODE (x) == GET_MODE (from)
743 && rtx_equal_p (x, from)))
744 {
745 validate_unshare_change (object, loc, to, 1);
746 return;
747 }
748
749 /* Call ourself recursively to perform the replacements.
750 We must not replace inside already replaced expression, otherwise we
751 get infinite recursion for replacements like (reg X)->(subreg (reg X))
752 so we must special case shared ASM_OPERANDS. */
753
754 if (GET_CODE (x) == PARALLEL)
755 {
756 for (j = XVECLEN (x, 0) - 1; j >= 0; j--)
757 {
758 if (j && GET_CODE (XVECEXP (x, 0, j)) == SET
759 && GET_CODE (SET_SRC (XVECEXP (x, 0, j))) == ASM_OPERANDS)
760 {
761 /* Verify that operands are really shared. */
762 gcc_assert (ASM_OPERANDS_INPUT_VEC (SET_SRC (XVECEXP (x, 0, 0)))
763 == ASM_OPERANDS_INPUT_VEC (SET_SRC (XVECEXP
764 (x, 0, j))));
765 validate_replace_rtx_1 (&SET_DEST (XVECEXP (x, 0, j)),
766 from, to, object, simplify);
767 }
768 else
769 validate_replace_rtx_1 (&XVECEXP (x, 0, j), from, to, object,
770 simplify);
771 }
772 }
773 else
774 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
775 {
776 if (fmt[i] == 'e')
777 validate_replace_rtx_1 (&XEXP (x, i), from, to, object, simplify);
778 else if (fmt[i] == 'E')
779 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
780 validate_replace_rtx_1 (&XVECEXP (x, i, j), from, to, object,
781 simplify);
782 }
783
784 /* If we didn't substitute, there is nothing more to do. */
785 if (num_changes == prev_changes)
786 return;
787
788 /* ??? The regmove is no more, so is this aberration still necessary? */
789 /* Allow substituted expression to have different mode. This is used by
790 regmove to change mode of pseudo register. */
791 if (fmt[0] == 'e' && GET_MODE (XEXP (x, 0)) != VOIDmode)
792 op0_mode = GET_MODE (XEXP (x, 0));
793
794 /* Do changes needed to keep rtx consistent. Don't do any other
795 simplifications, as it is not our job. */
796 if (simplify)
797 simplify_while_replacing (loc, to, object, op0_mode);
798 }
799
800 /* Try replacing every occurrence of FROM in subexpression LOC of INSN
801 with TO. After all changes have been made, validate by seeing
802 if INSN is still valid. */
803
804 int
805 validate_replace_rtx_subexp (rtx from, rtx to, rtx_insn *insn, rtx *loc)
806 {
807 validate_replace_rtx_1 (loc, from, to, insn, true);
808 return apply_change_group ();
809 }
810
811 /* Try replacing every occurrence of FROM in INSN with TO. After all
812 changes have been made, validate by seeing if INSN is still valid. */
813
814 int
815 validate_replace_rtx (rtx from, rtx to, rtx_insn *insn)
816 {
817 validate_replace_rtx_1 (&PATTERN (insn), from, to, insn, true);
818 return apply_change_group ();
819 }
820
821 /* Try replacing every occurrence of FROM in WHERE with TO. Assume that WHERE
822 is a part of INSN. After all changes have been made, validate by seeing if
823 INSN is still valid.
824 validate_replace_rtx (from, to, insn) is equivalent to
825 validate_replace_rtx_part (from, to, &PATTERN (insn), insn). */
826
827 int
828 validate_replace_rtx_part (rtx from, rtx to, rtx *where, rtx_insn *insn)
829 {
830 validate_replace_rtx_1 (where, from, to, insn, true);
831 return apply_change_group ();
832 }
833
834 /* Same as above, but do not simplify rtx afterwards. */
835 int
836 validate_replace_rtx_part_nosimplify (rtx from, rtx to, rtx *where,
837 rtx_insn *insn)
838 {
839 validate_replace_rtx_1 (where, from, to, insn, false);
840 return apply_change_group ();
841
842 }
843
844 /* Try replacing every occurrence of FROM in INSN with TO. This also
845 will replace in REG_EQUAL and REG_EQUIV notes. */
846
847 void
848 validate_replace_rtx_group (rtx from, rtx to, rtx_insn *insn)
849 {
850 rtx note;
851 validate_replace_rtx_1 (&PATTERN (insn), from, to, insn, true);
852 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
853 if (REG_NOTE_KIND (note) == REG_EQUAL
854 || REG_NOTE_KIND (note) == REG_EQUIV)
855 validate_replace_rtx_1 (&XEXP (note, 0), from, to, insn, true);
856 }
857
858 /* Function called by note_uses to replace used subexpressions. */
859 struct validate_replace_src_data
860 {
861 rtx from; /* Old RTX */
862 rtx to; /* New RTX */
863 rtx_insn *insn; /* Insn in which substitution is occurring. */
864 };
865
866 static void
867 validate_replace_src_1 (rtx *x, void *data)
868 {
869 struct validate_replace_src_data *d
870 = (struct validate_replace_src_data *) data;
871
872 validate_replace_rtx_1 (x, d->from, d->to, d->insn, true);
873 }
874
875 /* Try replacing every occurrence of FROM in INSN with TO, avoiding
876 SET_DESTs. */
877
878 void
879 validate_replace_src_group (rtx from, rtx to, rtx_insn *insn)
880 {
881 struct validate_replace_src_data d;
882
883 d.from = from;
884 d.to = to;
885 d.insn = insn;
886 note_uses (&PATTERN (insn), validate_replace_src_1, &d);
887 }
888
889 /* Try simplify INSN.
890 Invoke simplify_rtx () on every SET_SRC and SET_DEST inside the INSN's
891 pattern and return true if something was simplified. */
892
893 bool
894 validate_simplify_insn (rtx_insn *insn)
895 {
896 int i;
897 rtx pat = NULL;
898 rtx newpat = NULL;
899
900 pat = PATTERN (insn);
901
902 if (GET_CODE (pat) == SET)
903 {
904 newpat = simplify_rtx (SET_SRC (pat));
905 if (newpat && !rtx_equal_p (SET_SRC (pat), newpat))
906 validate_change (insn, &SET_SRC (pat), newpat, 1);
907 newpat = simplify_rtx (SET_DEST (pat));
908 if (newpat && !rtx_equal_p (SET_DEST (pat), newpat))
909 validate_change (insn, &SET_DEST (pat), newpat, 1);
910 }
911 else if (GET_CODE (pat) == PARALLEL)
912 for (i = 0; i < XVECLEN (pat, 0); i++)
913 {
914 rtx s = XVECEXP (pat, 0, i);
915
916 if (GET_CODE (XVECEXP (pat, 0, i)) == SET)
917 {
918 newpat = simplify_rtx (SET_SRC (s));
919 if (newpat && !rtx_equal_p (SET_SRC (s), newpat))
920 validate_change (insn, &SET_SRC (s), newpat, 1);
921 newpat = simplify_rtx (SET_DEST (s));
922 if (newpat && !rtx_equal_p (SET_DEST (s), newpat))
923 validate_change (insn, &SET_DEST (s), newpat, 1);
924 }
925 }
926 return ((num_changes_pending () > 0) && (apply_change_group () > 0));
927 }
928 \f
929 /* Return 1 if the insn using CC0 set by INSN does not contain
930 any ordered tests applied to the condition codes.
931 EQ and NE tests do not count. */
932
933 int
934 next_insn_tests_no_inequality (rtx_insn *insn)
935 {
936 rtx_insn *next = next_cc0_user (insn);
937
938 /* If there is no next insn, we have to take the conservative choice. */
939 if (next == 0)
940 return 0;
941
942 return (INSN_P (next)
943 && ! inequality_comparisons_p (PATTERN (next)));
944 }
945 \f
946 /* Return 1 if OP is a valid general operand for machine mode MODE.
947 This is either a register reference, a memory reference,
948 or a constant. In the case of a memory reference, the address
949 is checked for general validity for the target machine.
950
951 Register and memory references must have mode MODE in order to be valid,
952 but some constants have no machine mode and are valid for any mode.
953
954 If MODE is VOIDmode, OP is checked for validity for whatever mode
955 it has.
956
957 The main use of this function is as a predicate in match_operand
958 expressions in the machine description. */
959
960 int
961 general_operand (rtx op, machine_mode mode)
962 {
963 enum rtx_code code = GET_CODE (op);
964
965 if (mode == VOIDmode)
966 mode = GET_MODE (op);
967
968 /* Don't accept CONST_INT or anything similar
969 if the caller wants something floating. */
970 if (GET_MODE (op) == VOIDmode && mode != VOIDmode
971 && GET_MODE_CLASS (mode) != MODE_INT
972 && GET_MODE_CLASS (mode) != MODE_PARTIAL_INT)
973 return 0;
974
975 if (CONST_INT_P (op)
976 && mode != VOIDmode
977 && trunc_int_for_mode (INTVAL (op), mode) != INTVAL (op))
978 return 0;
979
980 if (CONSTANT_P (op))
981 return ((GET_MODE (op) == VOIDmode || GET_MODE (op) == mode
982 || mode == VOIDmode)
983 && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op))
984 && targetm.legitimate_constant_p (mode == VOIDmode
985 ? GET_MODE (op)
986 : mode, op));
987
988 /* Except for certain constants with VOIDmode, already checked for,
989 OP's mode must match MODE if MODE specifies a mode. */
990
991 if (GET_MODE (op) != mode)
992 return 0;
993
994 if (code == SUBREG)
995 {
996 rtx sub = SUBREG_REG (op);
997
998 #ifdef INSN_SCHEDULING
999 /* On machines that have insn scheduling, we want all memory
1000 reference to be explicit, so outlaw paradoxical SUBREGs.
1001 However, we must allow them after reload so that they can
1002 get cleaned up by cleanup_subreg_operands. */
1003 if (!reload_completed && MEM_P (sub)
1004 && GET_MODE_SIZE (mode) > GET_MODE_SIZE (GET_MODE (sub)))
1005 return 0;
1006 #endif
1007 /* Avoid memories with nonzero SUBREG_BYTE, as offsetting the memory
1008 may result in incorrect reference. We should simplify all valid
1009 subregs of MEM anyway. But allow this after reload because we
1010 might be called from cleanup_subreg_operands.
1011
1012 ??? This is a kludge. */
1013 if (!reload_completed && SUBREG_BYTE (op) != 0
1014 && MEM_P (sub))
1015 return 0;
1016
1017 #ifdef CANNOT_CHANGE_MODE_CLASS
1018 if (REG_P (sub)
1019 && REGNO (sub) < FIRST_PSEUDO_REGISTER
1020 && REG_CANNOT_CHANGE_MODE_P (REGNO (sub), GET_MODE (sub), mode)
1021 && GET_MODE_CLASS (GET_MODE (sub)) != MODE_COMPLEX_INT
1022 && GET_MODE_CLASS (GET_MODE (sub)) != MODE_COMPLEX_FLOAT
1023 /* LRA can generate some invalid SUBREGS just for matched
1024 operand reload presentation. LRA needs to treat them as
1025 valid. */
1026 && ! LRA_SUBREG_P (op))
1027 return 0;
1028 #endif
1029
1030 /* FLOAT_MODE subregs can't be paradoxical. Combine will occasionally
1031 create such rtl, and we must reject it. */
1032 if (SCALAR_FLOAT_MODE_P (GET_MODE (op))
1033 /* LRA can use subreg to store a floating point value in an
1034 integer mode. Although the floating point and the
1035 integer modes need the same number of hard registers, the
1036 size of floating point mode can be less than the integer
1037 mode. */
1038 && ! lra_in_progress
1039 && GET_MODE_SIZE (GET_MODE (op)) > GET_MODE_SIZE (GET_MODE (sub)))
1040 return 0;
1041
1042 op = sub;
1043 code = GET_CODE (op);
1044 }
1045
1046 if (code == REG)
1047 return (REGNO (op) >= FIRST_PSEUDO_REGISTER
1048 || in_hard_reg_set_p (operand_reg_set, GET_MODE (op), REGNO (op)));
1049
1050 if (code == MEM)
1051 {
1052 rtx y = XEXP (op, 0);
1053
1054 if (! volatile_ok && MEM_VOLATILE_P (op))
1055 return 0;
1056
1057 /* Use the mem's mode, since it will be reloaded thus. LRA can
1058 generate move insn with invalid addresses which is made valid
1059 and efficiently calculated by LRA through further numerous
1060 transformations. */
1061 if (lra_in_progress
1062 || memory_address_addr_space_p (GET_MODE (op), y, MEM_ADDR_SPACE (op)))
1063 return 1;
1064 }
1065
1066 return 0;
1067 }
1068 \f
1069 /* Return 1 if OP is a valid memory address for a memory reference
1070 of mode MODE.
1071
1072 The main use of this function is as a predicate in match_operand
1073 expressions in the machine description. */
1074
1075 int
1076 address_operand (rtx op, machine_mode mode)
1077 {
1078 return memory_address_p (mode, op);
1079 }
1080
1081 /* Return 1 if OP is a register reference of mode MODE.
1082 If MODE is VOIDmode, accept a register in any mode.
1083
1084 The main use of this function is as a predicate in match_operand
1085 expressions in the machine description. */
1086
1087 int
1088 register_operand (rtx op, machine_mode mode)
1089 {
1090 if (GET_CODE (op) == SUBREG)
1091 {
1092 rtx sub = SUBREG_REG (op);
1093
1094 /* Before reload, we can allow (SUBREG (MEM...)) as a register operand
1095 because it is guaranteed to be reloaded into one.
1096 Just make sure the MEM is valid in itself.
1097 (Ideally, (SUBREG (MEM)...) should not exist after reload,
1098 but currently it does result from (SUBREG (REG)...) where the
1099 reg went on the stack.) */
1100 if (!REG_P (sub) && (reload_completed || !MEM_P (sub)))
1101 return 0;
1102 }
1103 else if (!REG_P (op))
1104 return 0;
1105 return general_operand (op, mode);
1106 }
1107
1108 /* Return 1 for a register in Pmode; ignore the tested mode. */
1109
1110 int
1111 pmode_register_operand (rtx op, machine_mode mode ATTRIBUTE_UNUSED)
1112 {
1113 return register_operand (op, Pmode);
1114 }
1115
1116 /* Return 1 if OP should match a MATCH_SCRATCH, i.e., if it is a SCRATCH
1117 or a hard register. */
1118
1119 int
1120 scratch_operand (rtx op, machine_mode mode)
1121 {
1122 if (GET_MODE (op) != mode && mode != VOIDmode)
1123 return 0;
1124
1125 return (GET_CODE (op) == SCRATCH
1126 || (REG_P (op)
1127 && (lra_in_progress
1128 || (REGNO (op) < FIRST_PSEUDO_REGISTER
1129 && REGNO_REG_CLASS (REGNO (op)) != NO_REGS))));
1130 }
1131
1132 /* Return 1 if OP is a valid immediate operand for mode MODE.
1133
1134 The main use of this function is as a predicate in match_operand
1135 expressions in the machine description. */
1136
1137 int
1138 immediate_operand (rtx op, machine_mode mode)
1139 {
1140 /* Don't accept CONST_INT or anything similar
1141 if the caller wants something floating. */
1142 if (GET_MODE (op) == VOIDmode && mode != VOIDmode
1143 && GET_MODE_CLASS (mode) != MODE_INT
1144 && GET_MODE_CLASS (mode) != MODE_PARTIAL_INT)
1145 return 0;
1146
1147 if (CONST_INT_P (op)
1148 && mode != VOIDmode
1149 && trunc_int_for_mode (INTVAL (op), mode) != INTVAL (op))
1150 return 0;
1151
1152 return (CONSTANT_P (op)
1153 && (GET_MODE (op) == mode || mode == VOIDmode
1154 || GET_MODE (op) == VOIDmode)
1155 && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op))
1156 && targetm.legitimate_constant_p (mode == VOIDmode
1157 ? GET_MODE (op)
1158 : mode, op));
1159 }
1160
1161 /* Returns 1 if OP is an operand that is a CONST_INT of mode MODE. */
1162
1163 int
1164 const_int_operand (rtx op, machine_mode mode)
1165 {
1166 if (!CONST_INT_P (op))
1167 return 0;
1168
1169 if (mode != VOIDmode
1170 && trunc_int_for_mode (INTVAL (op), mode) != INTVAL (op))
1171 return 0;
1172
1173 return 1;
1174 }
1175
1176 #if TARGET_SUPPORTS_WIDE_INT
1177 /* Returns 1 if OP is an operand that is a CONST_INT or CONST_WIDE_INT
1178 of mode MODE. */
1179 int
1180 const_scalar_int_operand (rtx op, machine_mode mode)
1181 {
1182 if (!CONST_SCALAR_INT_P (op))
1183 return 0;
1184
1185 if (CONST_INT_P (op))
1186 return const_int_operand (op, mode);
1187
1188 if (mode != VOIDmode)
1189 {
1190 int prec = GET_MODE_PRECISION (mode);
1191 int bitsize = GET_MODE_BITSIZE (mode);
1192
1193 if (CONST_WIDE_INT_NUNITS (op) * HOST_BITS_PER_WIDE_INT > bitsize)
1194 return 0;
1195
1196 if (prec == bitsize)
1197 return 1;
1198 else
1199 {
1200 /* Multiword partial int. */
1201 HOST_WIDE_INT x
1202 = CONST_WIDE_INT_ELT (op, CONST_WIDE_INT_NUNITS (op) - 1);
1203 return (sext_hwi (x, prec & (HOST_BITS_PER_WIDE_INT - 1)) == x);
1204 }
1205 }
1206 return 1;
1207 }
1208
1209 /* Returns 1 if OP is an operand that is a constant integer or constant
1210 floating-point number of MODE. */
1211
1212 int
1213 const_double_operand (rtx op, machine_mode mode)
1214 {
1215 return (GET_CODE (op) == CONST_DOUBLE)
1216 && (GET_MODE (op) == mode || mode == VOIDmode);
1217 }
1218 #else
1219 /* Returns 1 if OP is an operand that is a constant integer or constant
1220 floating-point number of MODE. */
1221
1222 int
1223 const_double_operand (rtx op, machine_mode mode)
1224 {
1225 /* Don't accept CONST_INT or anything similar
1226 if the caller wants something floating. */
1227 if (GET_MODE (op) == VOIDmode && mode != VOIDmode
1228 && GET_MODE_CLASS (mode) != MODE_INT
1229 && GET_MODE_CLASS (mode) != MODE_PARTIAL_INT)
1230 return 0;
1231
1232 return ((CONST_DOUBLE_P (op) || CONST_INT_P (op))
1233 && (mode == VOIDmode || GET_MODE (op) == mode
1234 || GET_MODE (op) == VOIDmode));
1235 }
1236 #endif
1237 /* Return 1 if OP is a general operand that is not an immediate
1238 operand of mode MODE. */
1239
1240 int
1241 nonimmediate_operand (rtx op, machine_mode mode)
1242 {
1243 return (general_operand (op, mode) && ! CONSTANT_P (op));
1244 }
1245
1246 /* Return 1 if OP is a register reference or immediate value of mode MODE. */
1247
1248 int
1249 nonmemory_operand (rtx op, machine_mode mode)
1250 {
1251 if (CONSTANT_P (op))
1252 return immediate_operand (op, mode);
1253 return register_operand (op, mode);
1254 }
1255
1256 /* Return 1 if OP is a valid operand that stands for pushing a
1257 value of mode MODE onto the stack.
1258
1259 The main use of this function is as a predicate in match_operand
1260 expressions in the machine description. */
1261
1262 int
1263 push_operand (rtx op, machine_mode mode)
1264 {
1265 unsigned int rounded_size = GET_MODE_SIZE (mode);
1266
1267 #ifdef PUSH_ROUNDING
1268 rounded_size = PUSH_ROUNDING (rounded_size);
1269 #endif
1270
1271 if (!MEM_P (op))
1272 return 0;
1273
1274 if (mode != VOIDmode && GET_MODE (op) != mode)
1275 return 0;
1276
1277 op = XEXP (op, 0);
1278
1279 if (rounded_size == GET_MODE_SIZE (mode))
1280 {
1281 if (GET_CODE (op) != STACK_PUSH_CODE)
1282 return 0;
1283 }
1284 else
1285 {
1286 if (GET_CODE (op) != PRE_MODIFY
1287 || GET_CODE (XEXP (op, 1)) != PLUS
1288 || XEXP (XEXP (op, 1), 0) != XEXP (op, 0)
1289 || !CONST_INT_P (XEXP (XEXP (op, 1), 1))
1290 || INTVAL (XEXP (XEXP (op, 1), 1))
1291 != ((STACK_GROWS_DOWNWARD ? -1 : 1) * (int) rounded_size))
1292 return 0;
1293 }
1294
1295 return XEXP (op, 0) == stack_pointer_rtx;
1296 }
1297
1298 /* Return 1 if OP is a valid operand that stands for popping a
1299 value of mode MODE off the stack.
1300
1301 The main use of this function is as a predicate in match_operand
1302 expressions in the machine description. */
1303
1304 int
1305 pop_operand (rtx op, machine_mode mode)
1306 {
1307 if (!MEM_P (op))
1308 return 0;
1309
1310 if (mode != VOIDmode && GET_MODE (op) != mode)
1311 return 0;
1312
1313 op = XEXP (op, 0);
1314
1315 if (GET_CODE (op) != STACK_POP_CODE)
1316 return 0;
1317
1318 return XEXP (op, 0) == stack_pointer_rtx;
1319 }
1320
1321 /* Return 1 if ADDR is a valid memory address
1322 for mode MODE in address space AS. */
1323
1324 int
1325 memory_address_addr_space_p (machine_mode mode ATTRIBUTE_UNUSED,
1326 rtx addr, addr_space_t as)
1327 {
1328 #ifdef GO_IF_LEGITIMATE_ADDRESS
1329 gcc_assert (ADDR_SPACE_GENERIC_P (as));
1330 GO_IF_LEGITIMATE_ADDRESS (mode, addr, win);
1331 return 0;
1332
1333 win:
1334 return 1;
1335 #else
1336 return targetm.addr_space.legitimate_address_p (mode, addr, 0, as);
1337 #endif
1338 }
1339
1340 /* Return 1 if OP is a valid memory reference with mode MODE,
1341 including a valid address.
1342
1343 The main use of this function is as a predicate in match_operand
1344 expressions in the machine description. */
1345
1346 int
1347 memory_operand (rtx op, machine_mode mode)
1348 {
1349 rtx inner;
1350
1351 if (! reload_completed)
1352 /* Note that no SUBREG is a memory operand before end of reload pass,
1353 because (SUBREG (MEM...)) forces reloading into a register. */
1354 return MEM_P (op) && general_operand (op, mode);
1355
1356 if (mode != VOIDmode && GET_MODE (op) != mode)
1357 return 0;
1358
1359 inner = op;
1360 if (GET_CODE (inner) == SUBREG)
1361 inner = SUBREG_REG (inner);
1362
1363 return (MEM_P (inner) && general_operand (op, mode));
1364 }
1365
1366 /* Return 1 if OP is a valid indirect memory reference with mode MODE;
1367 that is, a memory reference whose address is a general_operand. */
1368
1369 int
1370 indirect_operand (rtx op, machine_mode mode)
1371 {
1372 /* Before reload, a SUBREG isn't in memory (see memory_operand, above). */
1373 if (! reload_completed
1374 && GET_CODE (op) == SUBREG && MEM_P (SUBREG_REG (op)))
1375 {
1376 int offset = SUBREG_BYTE (op);
1377 rtx inner = SUBREG_REG (op);
1378
1379 if (mode != VOIDmode && GET_MODE (op) != mode)
1380 return 0;
1381
1382 /* The only way that we can have a general_operand as the resulting
1383 address is if OFFSET is zero and the address already is an operand
1384 or if the address is (plus Y (const_int -OFFSET)) and Y is an
1385 operand. */
1386
1387 return ((offset == 0 && general_operand (XEXP (inner, 0), Pmode))
1388 || (GET_CODE (XEXP (inner, 0)) == PLUS
1389 && CONST_INT_P (XEXP (XEXP (inner, 0), 1))
1390 && INTVAL (XEXP (XEXP (inner, 0), 1)) == -offset
1391 && general_operand (XEXP (XEXP (inner, 0), 0), Pmode)));
1392 }
1393
1394 return (MEM_P (op)
1395 && memory_operand (op, mode)
1396 && general_operand (XEXP (op, 0), Pmode));
1397 }
1398
1399 /* Return 1 if this is an ordered comparison operator (not including
1400 ORDERED and UNORDERED). */
1401
1402 int
1403 ordered_comparison_operator (rtx op, machine_mode mode)
1404 {
1405 if (mode != VOIDmode && GET_MODE (op) != mode)
1406 return false;
1407 switch (GET_CODE (op))
1408 {
1409 case EQ:
1410 case NE:
1411 case LT:
1412 case LTU:
1413 case LE:
1414 case LEU:
1415 case GT:
1416 case GTU:
1417 case GE:
1418 case GEU:
1419 return true;
1420 default:
1421 return false;
1422 }
1423 }
1424
1425 /* Return 1 if this is a comparison operator. This allows the use of
1426 MATCH_OPERATOR to recognize all the branch insns. */
1427
1428 int
1429 comparison_operator (rtx op, machine_mode mode)
1430 {
1431 return ((mode == VOIDmode || GET_MODE (op) == mode)
1432 && COMPARISON_P (op));
1433 }
1434 \f
1435 /* If BODY is an insn body that uses ASM_OPERANDS, return it. */
1436
1437 rtx
1438 extract_asm_operands (rtx body)
1439 {
1440 rtx tmp;
1441 switch (GET_CODE (body))
1442 {
1443 case ASM_OPERANDS:
1444 return body;
1445
1446 case SET:
1447 /* Single output operand: BODY is (set OUTPUT (asm_operands ...)). */
1448 tmp = SET_SRC (body);
1449 if (GET_CODE (tmp) == ASM_OPERANDS)
1450 return tmp;
1451 break;
1452
1453 case PARALLEL:
1454 tmp = XVECEXP (body, 0, 0);
1455 if (GET_CODE (tmp) == ASM_OPERANDS)
1456 return tmp;
1457 if (GET_CODE (tmp) == SET)
1458 {
1459 tmp = SET_SRC (tmp);
1460 if (GET_CODE (tmp) == ASM_OPERANDS)
1461 return tmp;
1462 }
1463 break;
1464
1465 default:
1466 break;
1467 }
1468 return NULL;
1469 }
1470
1471 /* If BODY is an insn body that uses ASM_OPERANDS,
1472 return the number of operands (both input and output) in the insn.
1473 If BODY is an insn body that uses ASM_INPUT with CLOBBERS in PARALLEL,
1474 return 0.
1475 Otherwise return -1. */
1476
1477 int
1478 asm_noperands (const_rtx body)
1479 {
1480 rtx asm_op = extract_asm_operands (CONST_CAST_RTX (body));
1481 int i, n_sets = 0;
1482
1483 if (asm_op == NULL)
1484 {
1485 if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0) >= 2
1486 && GET_CODE (XVECEXP (body, 0, 0)) == ASM_INPUT)
1487 {
1488 /* body is [(asm_input ...) (clobber (reg ...))...]. */
1489 for (i = XVECLEN (body, 0) - 1; i > 0; i--)
1490 if (GET_CODE (XVECEXP (body, 0, i)) != CLOBBER)
1491 return -1;
1492 return 0;
1493 }
1494 return -1;
1495 }
1496
1497 if (GET_CODE (body) == SET)
1498 n_sets = 1;
1499 else if (GET_CODE (body) == PARALLEL)
1500 {
1501 if (GET_CODE (XVECEXP (body, 0, 0)) == SET)
1502 {
1503 /* Multiple output operands, or 1 output plus some clobbers:
1504 body is
1505 [(set OUTPUT (asm_operands ...))... (clobber (reg ...))...]. */
1506 /* Count backwards through CLOBBERs to determine number of SETs. */
1507 for (i = XVECLEN (body, 0); i > 0; i--)
1508 {
1509 if (GET_CODE (XVECEXP (body, 0, i - 1)) == SET)
1510 break;
1511 if (GET_CODE (XVECEXP (body, 0, i - 1)) != CLOBBER)
1512 return -1;
1513 }
1514
1515 /* N_SETS is now number of output operands. */
1516 n_sets = i;
1517
1518 /* Verify that all the SETs we have
1519 came from a single original asm_operands insn
1520 (so that invalid combinations are blocked). */
1521 for (i = 0; i < n_sets; i++)
1522 {
1523 rtx elt = XVECEXP (body, 0, i);
1524 if (GET_CODE (elt) != SET)
1525 return -1;
1526 if (GET_CODE (SET_SRC (elt)) != ASM_OPERANDS)
1527 return -1;
1528 /* If these ASM_OPERANDS rtx's came from different original insns
1529 then they aren't allowed together. */
1530 if (ASM_OPERANDS_INPUT_VEC (SET_SRC (elt))
1531 != ASM_OPERANDS_INPUT_VEC (asm_op))
1532 return -1;
1533 }
1534 }
1535 else
1536 {
1537 /* 0 outputs, but some clobbers:
1538 body is [(asm_operands ...) (clobber (reg ...))...]. */
1539 /* Make sure all the other parallel things really are clobbers. */
1540 for (i = XVECLEN (body, 0) - 1; i > 0; i--)
1541 if (GET_CODE (XVECEXP (body, 0, i)) != CLOBBER)
1542 return -1;
1543 }
1544 }
1545
1546 return (ASM_OPERANDS_INPUT_LENGTH (asm_op)
1547 + ASM_OPERANDS_LABEL_LENGTH (asm_op) + n_sets);
1548 }
1549
1550 /* Assuming BODY is an insn body that uses ASM_OPERANDS,
1551 copy its operands (both input and output) into the vector OPERANDS,
1552 the locations of the operands within the insn into the vector OPERAND_LOCS,
1553 and the constraints for the operands into CONSTRAINTS.
1554 Write the modes of the operands into MODES.
1555 Write the location info into LOC.
1556 Return the assembler-template.
1557 If BODY is an insn body that uses ASM_INPUT with CLOBBERS in PARALLEL,
1558 return the basic assembly string.
1559
1560 If LOC, MODES, OPERAND_LOCS, CONSTRAINTS or OPERANDS is 0,
1561 we don't store that info. */
1562
1563 const char *
1564 decode_asm_operands (rtx body, rtx *operands, rtx **operand_locs,
1565 const char **constraints, machine_mode *modes,
1566 location_t *loc)
1567 {
1568 int nbase = 0, n, i;
1569 rtx asmop;
1570
1571 switch (GET_CODE (body))
1572 {
1573 case ASM_OPERANDS:
1574 /* Zero output asm: BODY is (asm_operands ...). */
1575 asmop = body;
1576 break;
1577
1578 case SET:
1579 /* Single output asm: BODY is (set OUTPUT (asm_operands ...)). */
1580 asmop = SET_SRC (body);
1581
1582 /* The output is in the SET.
1583 Its constraint is in the ASM_OPERANDS itself. */
1584 if (operands)
1585 operands[0] = SET_DEST (body);
1586 if (operand_locs)
1587 operand_locs[0] = &SET_DEST (body);
1588 if (constraints)
1589 constraints[0] = ASM_OPERANDS_OUTPUT_CONSTRAINT (asmop);
1590 if (modes)
1591 modes[0] = GET_MODE (SET_DEST (body));
1592 nbase = 1;
1593 break;
1594
1595 case PARALLEL:
1596 {
1597 int nparallel = XVECLEN (body, 0); /* Includes CLOBBERs. */
1598
1599 asmop = XVECEXP (body, 0, 0);
1600 if (GET_CODE (asmop) == SET)
1601 {
1602 asmop = SET_SRC (asmop);
1603
1604 /* At least one output, plus some CLOBBERs. The outputs are in
1605 the SETs. Their constraints are in the ASM_OPERANDS itself. */
1606 for (i = 0; i < nparallel; i++)
1607 {
1608 if (GET_CODE (XVECEXP (body, 0, i)) == CLOBBER)
1609 break; /* Past last SET */
1610 if (operands)
1611 operands[i] = SET_DEST (XVECEXP (body, 0, i));
1612 if (operand_locs)
1613 operand_locs[i] = &SET_DEST (XVECEXP (body, 0, i));
1614 if (constraints)
1615 constraints[i] = XSTR (SET_SRC (XVECEXP (body, 0, i)), 1);
1616 if (modes)
1617 modes[i] = GET_MODE (SET_DEST (XVECEXP (body, 0, i)));
1618 }
1619 nbase = i;
1620 }
1621 else if (GET_CODE (asmop) == ASM_INPUT)
1622 {
1623 if (loc)
1624 *loc = ASM_INPUT_SOURCE_LOCATION (asmop);
1625 return XSTR (asmop, 0);
1626 }
1627 break;
1628 }
1629
1630 default:
1631 gcc_unreachable ();
1632 }
1633
1634 n = ASM_OPERANDS_INPUT_LENGTH (asmop);
1635 for (i = 0; i < n; i++)
1636 {
1637 if (operand_locs)
1638 operand_locs[nbase + i] = &ASM_OPERANDS_INPUT (asmop, i);
1639 if (operands)
1640 operands[nbase + i] = ASM_OPERANDS_INPUT (asmop, i);
1641 if (constraints)
1642 constraints[nbase + i] = ASM_OPERANDS_INPUT_CONSTRAINT (asmop, i);
1643 if (modes)
1644 modes[nbase + i] = ASM_OPERANDS_INPUT_MODE (asmop, i);
1645 }
1646 nbase += n;
1647
1648 n = ASM_OPERANDS_LABEL_LENGTH (asmop);
1649 for (i = 0; i < n; i++)
1650 {
1651 if (operand_locs)
1652 operand_locs[nbase + i] = &ASM_OPERANDS_LABEL (asmop, i);
1653 if (operands)
1654 operands[nbase + i] = ASM_OPERANDS_LABEL (asmop, i);
1655 if (constraints)
1656 constraints[nbase + i] = "";
1657 if (modes)
1658 modes[nbase + i] = Pmode;
1659 }
1660
1661 if (loc)
1662 *loc = ASM_OPERANDS_SOURCE_LOCATION (asmop);
1663
1664 return ASM_OPERANDS_TEMPLATE (asmop);
1665 }
1666
1667 /* Parse inline assembly string STRING and determine which operands are
1668 referenced by % markers. For the first NOPERANDS operands, set USED[I]
1669 to true if operand I is referenced.
1670
1671 This is intended to distinguish barrier-like asms such as:
1672
1673 asm ("" : "=m" (...));
1674
1675 from real references such as:
1676
1677 asm ("sw\t$0, %0" : "=m" (...)); */
1678
1679 void
1680 get_referenced_operands (const char *string, bool *used,
1681 unsigned int noperands)
1682 {
1683 memset (used, 0, sizeof (bool) * noperands);
1684 const char *p = string;
1685 while (*p)
1686 switch (*p)
1687 {
1688 case '%':
1689 p += 1;
1690 /* A letter followed by a digit indicates an operand number. */
1691 if (ISALPHA (p[0]) && ISDIGIT (p[1]))
1692 p += 1;
1693 if (ISDIGIT (*p))
1694 {
1695 char *endptr;
1696 unsigned long opnum = strtoul (p, &endptr, 10);
1697 if (endptr != p && opnum < noperands)
1698 used[opnum] = true;
1699 p = endptr;
1700 }
1701 else
1702 p += 1;
1703 break;
1704
1705 default:
1706 p++;
1707 break;
1708 }
1709 }
1710
1711 /* Check if an asm_operand matches its constraints.
1712 Return > 0 if ok, = 0 if bad, < 0 if inconclusive. */
1713
1714 int
1715 asm_operand_ok (rtx op, const char *constraint, const char **constraints)
1716 {
1717 int result = 0;
1718 bool incdec_ok = false;
1719
1720 /* Use constrain_operands after reload. */
1721 gcc_assert (!reload_completed);
1722
1723 /* Empty constraint string is the same as "X,...,X", i.e. X for as
1724 many alternatives as required to match the other operands. */
1725 if (*constraint == '\0')
1726 result = 1;
1727
1728 while (*constraint)
1729 {
1730 enum constraint_num cn;
1731 char c = *constraint;
1732 int len;
1733 switch (c)
1734 {
1735 case ',':
1736 constraint++;
1737 continue;
1738
1739 case '0': case '1': case '2': case '3': case '4':
1740 case '5': case '6': case '7': case '8': case '9':
1741 /* If caller provided constraints pointer, look up
1742 the matching constraint. Otherwise, our caller should have
1743 given us the proper matching constraint, but we can't
1744 actually fail the check if they didn't. Indicate that
1745 results are inconclusive. */
1746 if (constraints)
1747 {
1748 char *end;
1749 unsigned long match;
1750
1751 match = strtoul (constraint, &end, 10);
1752 if (!result)
1753 result = asm_operand_ok (op, constraints[match], NULL);
1754 constraint = (const char *) end;
1755 }
1756 else
1757 {
1758 do
1759 constraint++;
1760 while (ISDIGIT (*constraint));
1761 if (! result)
1762 result = -1;
1763 }
1764 continue;
1765
1766 /* The rest of the compiler assumes that reloading the address
1767 of a MEM into a register will make it fit an 'o' constraint.
1768 That is, if it sees a MEM operand for an 'o' constraint,
1769 it assumes that (mem (base-reg)) will fit.
1770
1771 That assumption fails on targets that don't have offsettable
1772 addresses at all. We therefore need to treat 'o' asm
1773 constraints as a special case and only accept operands that
1774 are already offsettable, thus proving that at least one
1775 offsettable address exists. */
1776 case 'o': /* offsettable */
1777 if (offsettable_nonstrict_memref_p (op))
1778 result = 1;
1779 break;
1780
1781 case 'g':
1782 if (general_operand (op, VOIDmode))
1783 result = 1;
1784 break;
1785
1786 case '<':
1787 case '>':
1788 /* ??? Before auto-inc-dec, auto inc/dec insns are not supposed
1789 to exist, excepting those that expand_call created. Further,
1790 on some machines which do not have generalized auto inc/dec,
1791 an inc/dec is not a memory_operand.
1792
1793 Match any memory and hope things are resolved after reload. */
1794 incdec_ok = true;
1795 /* FALLTHRU */
1796 default:
1797 cn = lookup_constraint (constraint);
1798 switch (get_constraint_type (cn))
1799 {
1800 case CT_REGISTER:
1801 if (!result
1802 && reg_class_for_constraint (cn) != NO_REGS
1803 && GET_MODE (op) != BLKmode
1804 && register_operand (op, VOIDmode))
1805 result = 1;
1806 break;
1807
1808 case CT_CONST_INT:
1809 if (!result
1810 && CONST_INT_P (op)
1811 && insn_const_int_ok_for_constraint (INTVAL (op), cn))
1812 result = 1;
1813 break;
1814
1815 case CT_MEMORY:
1816 case CT_SPECIAL_MEMORY:
1817 /* Every memory operand can be reloaded to fit. */
1818 result = result || memory_operand (op, VOIDmode);
1819 break;
1820
1821 case CT_ADDRESS:
1822 /* Every address operand can be reloaded to fit. */
1823 result = result || address_operand (op, VOIDmode);
1824 break;
1825
1826 case CT_FIXED_FORM:
1827 result = result || constraint_satisfied_p (op, cn);
1828 break;
1829 }
1830 break;
1831 }
1832 len = CONSTRAINT_LEN (c, constraint);
1833 do
1834 constraint++;
1835 while (--len && *constraint);
1836 if (len)
1837 return 0;
1838 }
1839
1840 /* For operands without < or > constraints reject side-effects. */
1841 if (AUTO_INC_DEC && !incdec_ok && result && MEM_P (op))
1842 switch (GET_CODE (XEXP (op, 0)))
1843 {
1844 case PRE_INC:
1845 case POST_INC:
1846 case PRE_DEC:
1847 case POST_DEC:
1848 case PRE_MODIFY:
1849 case POST_MODIFY:
1850 return 0;
1851 default:
1852 break;
1853 }
1854
1855 return result;
1856 }
1857 \f
1858 /* Given an rtx *P, if it is a sum containing an integer constant term,
1859 return the location (type rtx *) of the pointer to that constant term.
1860 Otherwise, return a null pointer. */
1861
1862 rtx *
1863 find_constant_term_loc (rtx *p)
1864 {
1865 rtx *tem;
1866 enum rtx_code code = GET_CODE (*p);
1867
1868 /* If *P IS such a constant term, P is its location. */
1869
1870 if (code == CONST_INT || code == SYMBOL_REF || code == LABEL_REF
1871 || code == CONST)
1872 return p;
1873
1874 /* Otherwise, if not a sum, it has no constant term. */
1875
1876 if (GET_CODE (*p) != PLUS)
1877 return 0;
1878
1879 /* If one of the summands is constant, return its location. */
1880
1881 if (XEXP (*p, 0) && CONSTANT_P (XEXP (*p, 0))
1882 && XEXP (*p, 1) && CONSTANT_P (XEXP (*p, 1)))
1883 return p;
1884
1885 /* Otherwise, check each summand for containing a constant term. */
1886
1887 if (XEXP (*p, 0) != 0)
1888 {
1889 tem = find_constant_term_loc (&XEXP (*p, 0));
1890 if (tem != 0)
1891 return tem;
1892 }
1893
1894 if (XEXP (*p, 1) != 0)
1895 {
1896 tem = find_constant_term_loc (&XEXP (*p, 1));
1897 if (tem != 0)
1898 return tem;
1899 }
1900
1901 return 0;
1902 }
1903 \f
1904 /* Return 1 if OP is a memory reference
1905 whose address contains no side effects
1906 and remains valid after the addition
1907 of a positive integer less than the
1908 size of the object being referenced.
1909
1910 We assume that the original address is valid and do not check it.
1911
1912 This uses strict_memory_address_p as a subroutine, so
1913 don't use it before reload. */
1914
1915 int
1916 offsettable_memref_p (rtx op)
1917 {
1918 return ((MEM_P (op))
1919 && offsettable_address_addr_space_p (1, GET_MODE (op), XEXP (op, 0),
1920 MEM_ADDR_SPACE (op)));
1921 }
1922
1923 /* Similar, but don't require a strictly valid mem ref:
1924 consider pseudo-regs valid as index or base regs. */
1925
1926 int
1927 offsettable_nonstrict_memref_p (rtx op)
1928 {
1929 return ((MEM_P (op))
1930 && offsettable_address_addr_space_p (0, GET_MODE (op), XEXP (op, 0),
1931 MEM_ADDR_SPACE (op)));
1932 }
1933
1934 /* Return 1 if Y is a memory address which contains no side effects
1935 and would remain valid for address space AS after the addition of
1936 a positive integer less than the size of that mode.
1937
1938 We assume that the original address is valid and do not check it.
1939 We do check that it is valid for narrower modes.
1940
1941 If STRICTP is nonzero, we require a strictly valid address,
1942 for the sake of use in reload.c. */
1943
1944 int
1945 offsettable_address_addr_space_p (int strictp, machine_mode mode, rtx y,
1946 addr_space_t as)
1947 {
1948 enum rtx_code ycode = GET_CODE (y);
1949 rtx z;
1950 rtx y1 = y;
1951 rtx *y2;
1952 int (*addressp) (machine_mode, rtx, addr_space_t) =
1953 (strictp ? strict_memory_address_addr_space_p
1954 : memory_address_addr_space_p);
1955 unsigned int mode_sz = GET_MODE_SIZE (mode);
1956
1957 if (CONSTANT_ADDRESS_P (y))
1958 return 1;
1959
1960 /* Adjusting an offsettable address involves changing to a narrower mode.
1961 Make sure that's OK. */
1962
1963 if (mode_dependent_address_p (y, as))
1964 return 0;
1965
1966 machine_mode address_mode = GET_MODE (y);
1967 if (address_mode == VOIDmode)
1968 address_mode = targetm.addr_space.address_mode (as);
1969 #ifdef POINTERS_EXTEND_UNSIGNED
1970 machine_mode pointer_mode = targetm.addr_space.pointer_mode (as);
1971 #endif
1972
1973 /* ??? How much offset does an offsettable BLKmode reference need?
1974 Clearly that depends on the situation in which it's being used.
1975 However, the current situation in which we test 0xffffffff is
1976 less than ideal. Caveat user. */
1977 if (mode_sz == 0)
1978 mode_sz = BIGGEST_ALIGNMENT / BITS_PER_UNIT;
1979
1980 /* If the expression contains a constant term,
1981 see if it remains valid when max possible offset is added. */
1982
1983 if ((ycode == PLUS) && (y2 = find_constant_term_loc (&y1)))
1984 {
1985 int good;
1986
1987 y1 = *y2;
1988 *y2 = plus_constant (address_mode, *y2, mode_sz - 1);
1989 /* Use QImode because an odd displacement may be automatically invalid
1990 for any wider mode. But it should be valid for a single byte. */
1991 good = (*addressp) (QImode, y, as);
1992
1993 /* In any case, restore old contents of memory. */
1994 *y2 = y1;
1995 return good;
1996 }
1997
1998 if (GET_RTX_CLASS (ycode) == RTX_AUTOINC)
1999 return 0;
2000
2001 /* The offset added here is chosen as the maximum offset that
2002 any instruction could need to add when operating on something
2003 of the specified mode. We assume that if Y and Y+c are
2004 valid addresses then so is Y+d for all 0<d<c. adjust_address will
2005 go inside a LO_SUM here, so we do so as well. */
2006 if (GET_CODE (y) == LO_SUM
2007 && mode != BLKmode
2008 && mode_sz <= GET_MODE_ALIGNMENT (mode) / BITS_PER_UNIT)
2009 z = gen_rtx_LO_SUM (address_mode, XEXP (y, 0),
2010 plus_constant (address_mode, XEXP (y, 1),
2011 mode_sz - 1));
2012 #ifdef POINTERS_EXTEND_UNSIGNED
2013 /* Likewise for a ZERO_EXTEND from pointer_mode. */
2014 else if (POINTERS_EXTEND_UNSIGNED > 0
2015 && GET_CODE (y) == ZERO_EXTEND
2016 && GET_MODE (XEXP (y, 0)) == pointer_mode)
2017 z = gen_rtx_ZERO_EXTEND (address_mode,
2018 plus_constant (pointer_mode, XEXP (y, 0),
2019 mode_sz - 1));
2020 #endif
2021 else
2022 z = plus_constant (address_mode, y, mode_sz - 1);
2023
2024 /* Use QImode because an odd displacement may be automatically invalid
2025 for any wider mode. But it should be valid for a single byte. */
2026 return (*addressp) (QImode, z, as);
2027 }
2028
2029 /* Return 1 if ADDR is an address-expression whose effect depends
2030 on the mode of the memory reference it is used in.
2031
2032 ADDRSPACE is the address space associated with the address.
2033
2034 Autoincrement addressing is a typical example of mode-dependence
2035 because the amount of the increment depends on the mode. */
2036
2037 bool
2038 mode_dependent_address_p (rtx addr, addr_space_t addrspace)
2039 {
2040 /* Auto-increment addressing with anything other than post_modify
2041 or pre_modify always introduces a mode dependency. Catch such
2042 cases now instead of deferring to the target. */
2043 if (GET_CODE (addr) == PRE_INC
2044 || GET_CODE (addr) == POST_INC
2045 || GET_CODE (addr) == PRE_DEC
2046 || GET_CODE (addr) == POST_DEC)
2047 return true;
2048
2049 return targetm.mode_dependent_address_p (addr, addrspace);
2050 }
2051 \f
2052 /* Return true if boolean attribute ATTR is supported. */
2053
2054 static bool
2055 have_bool_attr (bool_attr attr)
2056 {
2057 switch (attr)
2058 {
2059 case BA_ENABLED:
2060 return HAVE_ATTR_enabled;
2061 case BA_PREFERRED_FOR_SIZE:
2062 return HAVE_ATTR_enabled || HAVE_ATTR_preferred_for_size;
2063 case BA_PREFERRED_FOR_SPEED:
2064 return HAVE_ATTR_enabled || HAVE_ATTR_preferred_for_speed;
2065 }
2066 gcc_unreachable ();
2067 }
2068
2069 /* Return the value of ATTR for instruction INSN. */
2070
2071 static bool
2072 get_bool_attr (rtx_insn *insn, bool_attr attr)
2073 {
2074 switch (attr)
2075 {
2076 case BA_ENABLED:
2077 return get_attr_enabled (insn);
2078 case BA_PREFERRED_FOR_SIZE:
2079 return get_attr_enabled (insn) && get_attr_preferred_for_size (insn);
2080 case BA_PREFERRED_FOR_SPEED:
2081 return get_attr_enabled (insn) && get_attr_preferred_for_speed (insn);
2082 }
2083 gcc_unreachable ();
2084 }
2085
2086 /* Like get_bool_attr_mask, but don't use the cache. */
2087
2088 static alternative_mask
2089 get_bool_attr_mask_uncached (rtx_insn *insn, bool_attr attr)
2090 {
2091 /* Temporarily install enough information for get_attr_<foo> to assume
2092 that the insn operands are already cached. As above, the attribute
2093 mustn't depend on the values of operands, so we don't provide their
2094 real values here. */
2095 rtx_insn *old_insn = recog_data.insn;
2096 int old_alternative = which_alternative;
2097
2098 recog_data.insn = insn;
2099 alternative_mask mask = ALL_ALTERNATIVES;
2100 int n_alternatives = insn_data[INSN_CODE (insn)].n_alternatives;
2101 for (int i = 0; i < n_alternatives; i++)
2102 {
2103 which_alternative = i;
2104 if (!get_bool_attr (insn, attr))
2105 mask &= ~ALTERNATIVE_BIT (i);
2106 }
2107
2108 recog_data.insn = old_insn;
2109 which_alternative = old_alternative;
2110 return mask;
2111 }
2112
2113 /* Return the mask of operand alternatives that are allowed for INSN
2114 by boolean attribute ATTR. This mask depends only on INSN and on
2115 the current target; it does not depend on things like the values of
2116 operands. */
2117
2118 static alternative_mask
2119 get_bool_attr_mask (rtx_insn *insn, bool_attr attr)
2120 {
2121 /* Quick exit for asms and for targets that don't use these attributes. */
2122 int code = INSN_CODE (insn);
2123 if (code < 0 || !have_bool_attr (attr))
2124 return ALL_ALTERNATIVES;
2125
2126 /* Calling get_attr_<foo> can be expensive, so cache the mask
2127 for speed. */
2128 if (!this_target_recog->x_bool_attr_masks[code][attr])
2129 this_target_recog->x_bool_attr_masks[code][attr]
2130 = get_bool_attr_mask_uncached (insn, attr);
2131 return this_target_recog->x_bool_attr_masks[code][attr];
2132 }
2133
2134 /* Return the set of alternatives of INSN that are allowed by the current
2135 target. */
2136
2137 alternative_mask
2138 get_enabled_alternatives (rtx_insn *insn)
2139 {
2140 return get_bool_attr_mask (insn, BA_ENABLED);
2141 }
2142
2143 /* Return the set of alternatives of INSN that are allowed by the current
2144 target and are preferred for the current size/speed optimization
2145 choice. */
2146
2147 alternative_mask
2148 get_preferred_alternatives (rtx_insn *insn)
2149 {
2150 if (optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn)))
2151 return get_bool_attr_mask (insn, BA_PREFERRED_FOR_SPEED);
2152 else
2153 return get_bool_attr_mask (insn, BA_PREFERRED_FOR_SIZE);
2154 }
2155
2156 /* Return the set of alternatives of INSN that are allowed by the current
2157 target and are preferred for the size/speed optimization choice
2158 associated with BB. Passing a separate BB is useful if INSN has not
2159 been emitted yet or if we are considering moving it to a different
2160 block. */
2161
2162 alternative_mask
2163 get_preferred_alternatives (rtx_insn *insn, basic_block bb)
2164 {
2165 if (optimize_bb_for_speed_p (bb))
2166 return get_bool_attr_mask (insn, BA_PREFERRED_FOR_SPEED);
2167 else
2168 return get_bool_attr_mask (insn, BA_PREFERRED_FOR_SIZE);
2169 }
2170
2171 /* Assert that the cached boolean attributes for INSN are still accurate.
2172 The backend is required to define these attributes in a way that only
2173 depends on the current target (rather than operands, compiler phase,
2174 etc.). */
2175
2176 bool
2177 check_bool_attrs (rtx_insn *insn)
2178 {
2179 int code = INSN_CODE (insn);
2180 if (code >= 0)
2181 for (int i = 0; i <= BA_LAST; ++i)
2182 {
2183 enum bool_attr attr = (enum bool_attr) i;
2184 if (this_target_recog->x_bool_attr_masks[code][attr])
2185 gcc_assert (this_target_recog->x_bool_attr_masks[code][attr]
2186 == get_bool_attr_mask_uncached (insn, attr));
2187 }
2188 return true;
2189 }
2190
2191 /* Like extract_insn, but save insn extracted and don't extract again, when
2192 called again for the same insn expecting that recog_data still contain the
2193 valid information. This is used primary by gen_attr infrastructure that
2194 often does extract insn again and again. */
2195 void
2196 extract_insn_cached (rtx_insn *insn)
2197 {
2198 if (recog_data.insn == insn && INSN_CODE (insn) >= 0)
2199 return;
2200 extract_insn (insn);
2201 recog_data.insn = insn;
2202 }
2203
2204 /* Do uncached extract_insn, constrain_operands and complain about failures.
2205 This should be used when extracting a pre-existing constrained instruction
2206 if the caller wants to know which alternative was chosen. */
2207 void
2208 extract_constrain_insn (rtx_insn *insn)
2209 {
2210 extract_insn (insn);
2211 if (!constrain_operands (reload_completed, get_enabled_alternatives (insn)))
2212 fatal_insn_not_found (insn);
2213 }
2214
2215 /* Do cached extract_insn, constrain_operands and complain about failures.
2216 Used by insn_attrtab. */
2217 void
2218 extract_constrain_insn_cached (rtx_insn *insn)
2219 {
2220 extract_insn_cached (insn);
2221 if (which_alternative == -1
2222 && !constrain_operands (reload_completed,
2223 get_enabled_alternatives (insn)))
2224 fatal_insn_not_found (insn);
2225 }
2226
2227 /* Do cached constrain_operands on INSN and complain about failures. */
2228 int
2229 constrain_operands_cached (rtx_insn *insn, int strict)
2230 {
2231 if (which_alternative == -1)
2232 return constrain_operands (strict, get_enabled_alternatives (insn));
2233 else
2234 return 1;
2235 }
2236 \f
2237 /* Analyze INSN and fill in recog_data. */
2238
2239 void
2240 extract_insn (rtx_insn *insn)
2241 {
2242 int i;
2243 int icode;
2244 int noperands;
2245 rtx body = PATTERN (insn);
2246
2247 recog_data.n_operands = 0;
2248 recog_data.n_alternatives = 0;
2249 recog_data.n_dups = 0;
2250 recog_data.is_asm = false;
2251
2252 switch (GET_CODE (body))
2253 {
2254 case USE:
2255 case CLOBBER:
2256 case ASM_INPUT:
2257 case ADDR_VEC:
2258 case ADDR_DIFF_VEC:
2259 case VAR_LOCATION:
2260 return;
2261
2262 case SET:
2263 if (GET_CODE (SET_SRC (body)) == ASM_OPERANDS)
2264 goto asm_insn;
2265 else
2266 goto normal_insn;
2267 case PARALLEL:
2268 if ((GET_CODE (XVECEXP (body, 0, 0)) == SET
2269 && GET_CODE (SET_SRC (XVECEXP (body, 0, 0))) == ASM_OPERANDS)
2270 || GET_CODE (XVECEXP (body, 0, 0)) == ASM_OPERANDS
2271 || GET_CODE (XVECEXP (body, 0, 0)) == ASM_INPUT)
2272 goto asm_insn;
2273 else
2274 goto normal_insn;
2275 case ASM_OPERANDS:
2276 asm_insn:
2277 recog_data.n_operands = noperands = asm_noperands (body);
2278 if (noperands >= 0)
2279 {
2280 /* This insn is an `asm' with operands. */
2281
2282 /* expand_asm_operands makes sure there aren't too many operands. */
2283 gcc_assert (noperands <= MAX_RECOG_OPERANDS);
2284
2285 /* Now get the operand values and constraints out of the insn. */
2286 decode_asm_operands (body, recog_data.operand,
2287 recog_data.operand_loc,
2288 recog_data.constraints,
2289 recog_data.operand_mode, NULL);
2290 memset (recog_data.is_operator, 0, sizeof recog_data.is_operator);
2291 if (noperands > 0)
2292 {
2293 const char *p = recog_data.constraints[0];
2294 recog_data.n_alternatives = 1;
2295 while (*p)
2296 recog_data.n_alternatives += (*p++ == ',');
2297 }
2298 recog_data.is_asm = true;
2299 break;
2300 }
2301 fatal_insn_not_found (insn);
2302
2303 default:
2304 normal_insn:
2305 /* Ordinary insn: recognize it, get the operands via insn_extract
2306 and get the constraints. */
2307
2308 icode = recog_memoized (insn);
2309 if (icode < 0)
2310 fatal_insn_not_found (insn);
2311
2312 recog_data.n_operands = noperands = insn_data[icode].n_operands;
2313 recog_data.n_alternatives = insn_data[icode].n_alternatives;
2314 recog_data.n_dups = insn_data[icode].n_dups;
2315
2316 insn_extract (insn);
2317
2318 for (i = 0; i < noperands; i++)
2319 {
2320 recog_data.constraints[i] = insn_data[icode].operand[i].constraint;
2321 recog_data.is_operator[i] = insn_data[icode].operand[i].is_operator;
2322 recog_data.operand_mode[i] = insn_data[icode].operand[i].mode;
2323 /* VOIDmode match_operands gets mode from their real operand. */
2324 if (recog_data.operand_mode[i] == VOIDmode)
2325 recog_data.operand_mode[i] = GET_MODE (recog_data.operand[i]);
2326 }
2327 }
2328 for (i = 0; i < noperands; i++)
2329 recog_data.operand_type[i]
2330 = (recog_data.constraints[i][0] == '=' ? OP_OUT
2331 : recog_data.constraints[i][0] == '+' ? OP_INOUT
2332 : OP_IN);
2333
2334 gcc_assert (recog_data.n_alternatives <= MAX_RECOG_ALTERNATIVES);
2335
2336 recog_data.insn = NULL;
2337 which_alternative = -1;
2338 }
2339
2340 /* Fill in OP_ALT_BASE for an instruction that has N_OPERANDS operands,
2341 N_ALTERNATIVES alternatives and constraint strings CONSTRAINTS.
2342 OP_ALT_BASE has N_ALTERNATIVES * N_OPERANDS entries and CONSTRAINTS
2343 has N_OPERANDS entries. */
2344
2345 void
2346 preprocess_constraints (int n_operands, int n_alternatives,
2347 const char **constraints,
2348 operand_alternative *op_alt_base)
2349 {
2350 for (int i = 0; i < n_operands; i++)
2351 {
2352 int j;
2353 struct operand_alternative *op_alt;
2354 const char *p = constraints[i];
2355
2356 op_alt = op_alt_base;
2357
2358 for (j = 0; j < n_alternatives; j++, op_alt += n_operands)
2359 {
2360 op_alt[i].cl = NO_REGS;
2361 op_alt[i].constraint = p;
2362 op_alt[i].matches = -1;
2363 op_alt[i].matched = -1;
2364
2365 if (*p == '\0' || *p == ',')
2366 {
2367 op_alt[i].anything_ok = 1;
2368 continue;
2369 }
2370
2371 for (;;)
2372 {
2373 char c = *p;
2374 if (c == '#')
2375 do
2376 c = *++p;
2377 while (c != ',' && c != '\0');
2378 if (c == ',' || c == '\0')
2379 {
2380 p++;
2381 break;
2382 }
2383
2384 switch (c)
2385 {
2386 case '?':
2387 op_alt[i].reject += 6;
2388 break;
2389 case '!':
2390 op_alt[i].reject += 600;
2391 break;
2392 case '&':
2393 op_alt[i].earlyclobber = 1;
2394 break;
2395
2396 case '0': case '1': case '2': case '3': case '4':
2397 case '5': case '6': case '7': case '8': case '9':
2398 {
2399 char *end;
2400 op_alt[i].matches = strtoul (p, &end, 10);
2401 op_alt[op_alt[i].matches].matched = i;
2402 p = end;
2403 }
2404 continue;
2405
2406 case 'X':
2407 op_alt[i].anything_ok = 1;
2408 break;
2409
2410 case 'g':
2411 op_alt[i].cl =
2412 reg_class_subunion[(int) op_alt[i].cl][(int) GENERAL_REGS];
2413 break;
2414
2415 default:
2416 enum constraint_num cn = lookup_constraint (p);
2417 enum reg_class cl;
2418 switch (get_constraint_type (cn))
2419 {
2420 case CT_REGISTER:
2421 cl = reg_class_for_constraint (cn);
2422 if (cl != NO_REGS)
2423 op_alt[i].cl = reg_class_subunion[op_alt[i].cl][cl];
2424 break;
2425
2426 case CT_CONST_INT:
2427 break;
2428
2429 case CT_MEMORY:
2430 case CT_SPECIAL_MEMORY:
2431 op_alt[i].memory_ok = 1;
2432 break;
2433
2434 case CT_ADDRESS:
2435 op_alt[i].is_address = 1;
2436 op_alt[i].cl
2437 = (reg_class_subunion
2438 [(int) op_alt[i].cl]
2439 [(int) base_reg_class (VOIDmode, ADDR_SPACE_GENERIC,
2440 ADDRESS, SCRATCH)]);
2441 break;
2442
2443 case CT_FIXED_FORM:
2444 break;
2445 }
2446 break;
2447 }
2448 p += CONSTRAINT_LEN (c, p);
2449 }
2450 }
2451 }
2452 }
2453
2454 /* Return an array of operand_alternative instructions for
2455 instruction ICODE. */
2456
2457 const operand_alternative *
2458 preprocess_insn_constraints (unsigned int icode)
2459 {
2460 gcc_checking_assert (IN_RANGE (icode, 0, NUM_INSN_CODES - 1));
2461 if (this_target_recog->x_op_alt[icode])
2462 return this_target_recog->x_op_alt[icode];
2463
2464 int n_operands = insn_data[icode].n_operands;
2465 if (n_operands == 0)
2466 return 0;
2467 /* Always provide at least one alternative so that which_op_alt ()
2468 works correctly. If the instruction has 0 alternatives (i.e. all
2469 constraint strings are empty) then each operand in this alternative
2470 will have anything_ok set. */
2471 int n_alternatives = MAX (insn_data[icode].n_alternatives, 1);
2472 int n_entries = n_operands * n_alternatives;
2473
2474 operand_alternative *op_alt = XCNEWVEC (operand_alternative, n_entries);
2475 const char **constraints = XALLOCAVEC (const char *, n_operands);
2476
2477 for (int i = 0; i < n_operands; ++i)
2478 constraints[i] = insn_data[icode].operand[i].constraint;
2479 preprocess_constraints (n_operands, n_alternatives, constraints, op_alt);
2480
2481 this_target_recog->x_op_alt[icode] = op_alt;
2482 return op_alt;
2483 }
2484
2485 /* After calling extract_insn, you can use this function to extract some
2486 information from the constraint strings into a more usable form.
2487 The collected data is stored in recog_op_alt. */
2488
2489 void
2490 preprocess_constraints (rtx_insn *insn)
2491 {
2492 int icode = INSN_CODE (insn);
2493 if (icode >= 0)
2494 recog_op_alt = preprocess_insn_constraints (icode);
2495 else
2496 {
2497 int n_operands = recog_data.n_operands;
2498 int n_alternatives = recog_data.n_alternatives;
2499 int n_entries = n_operands * n_alternatives;
2500 memset (asm_op_alt, 0, n_entries * sizeof (operand_alternative));
2501 preprocess_constraints (n_operands, n_alternatives,
2502 recog_data.constraints, asm_op_alt);
2503 recog_op_alt = asm_op_alt;
2504 }
2505 }
2506
2507 /* Check the operands of an insn against the insn's operand constraints
2508 and return 1 if they match any of the alternatives in ALTERNATIVES.
2509
2510 The information about the insn's operands, constraints, operand modes
2511 etc. is obtained from the global variables set up by extract_insn.
2512
2513 WHICH_ALTERNATIVE is set to a number which indicates which
2514 alternative of constraints was matched: 0 for the first alternative,
2515 1 for the next, etc.
2516
2517 In addition, when two operands are required to match
2518 and it happens that the output operand is (reg) while the
2519 input operand is --(reg) or ++(reg) (a pre-inc or pre-dec),
2520 make the output operand look like the input.
2521 This is because the output operand is the one the template will print.
2522
2523 This is used in final, just before printing the assembler code and by
2524 the routines that determine an insn's attribute.
2525
2526 If STRICT is a positive nonzero value, it means that we have been
2527 called after reload has been completed. In that case, we must
2528 do all checks strictly. If it is zero, it means that we have been called
2529 before reload has completed. In that case, we first try to see if we can
2530 find an alternative that matches strictly. If not, we try again, this
2531 time assuming that reload will fix up the insn. This provides a "best
2532 guess" for the alternative and is used to compute attributes of insns prior
2533 to reload. A negative value of STRICT is used for this internal call. */
2534
2535 struct funny_match
2536 {
2537 int this_op, other;
2538 };
2539
2540 int
2541 constrain_operands (int strict, alternative_mask alternatives)
2542 {
2543 const char *constraints[MAX_RECOG_OPERANDS];
2544 int matching_operands[MAX_RECOG_OPERANDS];
2545 int earlyclobber[MAX_RECOG_OPERANDS];
2546 int c;
2547
2548 struct funny_match funny_match[MAX_RECOG_OPERANDS];
2549 int funny_match_index;
2550
2551 which_alternative = 0;
2552 if (recog_data.n_operands == 0 || recog_data.n_alternatives == 0)
2553 return 1;
2554
2555 for (c = 0; c < recog_data.n_operands; c++)
2556 {
2557 constraints[c] = recog_data.constraints[c];
2558 matching_operands[c] = -1;
2559 }
2560
2561 do
2562 {
2563 int seen_earlyclobber_at = -1;
2564 int opno;
2565 int lose = 0;
2566 funny_match_index = 0;
2567
2568 if (!TEST_BIT (alternatives, which_alternative))
2569 {
2570 int i;
2571
2572 for (i = 0; i < recog_data.n_operands; i++)
2573 constraints[i] = skip_alternative (constraints[i]);
2574
2575 which_alternative++;
2576 continue;
2577 }
2578
2579 for (opno = 0; opno < recog_data.n_operands; opno++)
2580 {
2581 rtx op = recog_data.operand[opno];
2582 machine_mode mode = GET_MODE (op);
2583 const char *p = constraints[opno];
2584 int offset = 0;
2585 int win = 0;
2586 int val;
2587 int len;
2588
2589 earlyclobber[opno] = 0;
2590
2591 /* A unary operator may be accepted by the predicate, but it
2592 is irrelevant for matching constraints. */
2593 if (UNARY_P (op))
2594 op = XEXP (op, 0);
2595
2596 if (GET_CODE (op) == SUBREG)
2597 {
2598 if (REG_P (SUBREG_REG (op))
2599 && REGNO (SUBREG_REG (op)) < FIRST_PSEUDO_REGISTER)
2600 offset = subreg_regno_offset (REGNO (SUBREG_REG (op)),
2601 GET_MODE (SUBREG_REG (op)),
2602 SUBREG_BYTE (op),
2603 GET_MODE (op));
2604 op = SUBREG_REG (op);
2605 }
2606
2607 /* An empty constraint or empty alternative
2608 allows anything which matched the pattern. */
2609 if (*p == 0 || *p == ',')
2610 win = 1;
2611
2612 do
2613 switch (c = *p, len = CONSTRAINT_LEN (c, p), c)
2614 {
2615 case '\0':
2616 len = 0;
2617 break;
2618 case ',':
2619 c = '\0';
2620 break;
2621
2622 case '#':
2623 /* Ignore rest of this alternative as far as
2624 constraint checking is concerned. */
2625 do
2626 p++;
2627 while (*p && *p != ',');
2628 len = 0;
2629 break;
2630
2631 case '&':
2632 earlyclobber[opno] = 1;
2633 if (seen_earlyclobber_at < 0)
2634 seen_earlyclobber_at = opno;
2635 break;
2636
2637 case '0': case '1': case '2': case '3': case '4':
2638 case '5': case '6': case '7': case '8': case '9':
2639 {
2640 /* This operand must be the same as a previous one.
2641 This kind of constraint is used for instructions such
2642 as add when they take only two operands.
2643
2644 Note that the lower-numbered operand is passed first.
2645
2646 If we are not testing strictly, assume that this
2647 constraint will be satisfied. */
2648
2649 char *end;
2650 int match;
2651
2652 match = strtoul (p, &end, 10);
2653 p = end;
2654
2655 if (strict < 0)
2656 val = 1;
2657 else
2658 {
2659 rtx op1 = recog_data.operand[match];
2660 rtx op2 = recog_data.operand[opno];
2661
2662 /* A unary operator may be accepted by the predicate,
2663 but it is irrelevant for matching constraints. */
2664 if (UNARY_P (op1))
2665 op1 = XEXP (op1, 0);
2666 if (UNARY_P (op2))
2667 op2 = XEXP (op2, 0);
2668
2669 val = operands_match_p (op1, op2);
2670 }
2671
2672 matching_operands[opno] = match;
2673 matching_operands[match] = opno;
2674
2675 if (val != 0)
2676 win = 1;
2677
2678 /* If output is *x and input is *--x, arrange later
2679 to change the output to *--x as well, since the
2680 output op is the one that will be printed. */
2681 if (val == 2 && strict > 0)
2682 {
2683 funny_match[funny_match_index].this_op = opno;
2684 funny_match[funny_match_index++].other = match;
2685 }
2686 }
2687 len = 0;
2688 break;
2689
2690 case 'p':
2691 /* p is used for address_operands. When we are called by
2692 gen_reload, no one will have checked that the address is
2693 strictly valid, i.e., that all pseudos requiring hard regs
2694 have gotten them. */
2695 if (strict <= 0
2696 || (strict_memory_address_p (recog_data.operand_mode[opno],
2697 op)))
2698 win = 1;
2699 break;
2700
2701 /* No need to check general_operand again;
2702 it was done in insn-recog.c. Well, except that reload
2703 doesn't check the validity of its replacements, but
2704 that should only matter when there's a bug. */
2705 case 'g':
2706 /* Anything goes unless it is a REG and really has a hard reg
2707 but the hard reg is not in the class GENERAL_REGS. */
2708 if (REG_P (op))
2709 {
2710 if (strict < 0
2711 || GENERAL_REGS == ALL_REGS
2712 || (reload_in_progress
2713 && REGNO (op) >= FIRST_PSEUDO_REGISTER)
2714 || reg_fits_class_p (op, GENERAL_REGS, offset, mode))
2715 win = 1;
2716 }
2717 else if (strict < 0 || general_operand (op, mode))
2718 win = 1;
2719 break;
2720
2721 default:
2722 {
2723 enum constraint_num cn = lookup_constraint (p);
2724 enum reg_class cl = reg_class_for_constraint (cn);
2725 if (cl != NO_REGS)
2726 {
2727 if (strict < 0
2728 || (strict == 0
2729 && REG_P (op)
2730 && REGNO (op) >= FIRST_PSEUDO_REGISTER)
2731 || (strict == 0 && GET_CODE (op) == SCRATCH)
2732 || (REG_P (op)
2733 && reg_fits_class_p (op, cl, offset, mode)))
2734 win = 1;
2735 }
2736
2737 else if (constraint_satisfied_p (op, cn))
2738 win = 1;
2739
2740 else if (insn_extra_memory_constraint (cn)
2741 /* Every memory operand can be reloaded to fit. */
2742 && ((strict < 0 && MEM_P (op))
2743 /* Before reload, accept what reload can turn
2744 into a mem. */
2745 || (strict < 0 && CONSTANT_P (op))
2746 /* Before reload, accept a pseudo,
2747 since LRA can turn it into a mem. */
2748 || (strict < 0 && targetm.lra_p () && REG_P (op)
2749 && REGNO (op) >= FIRST_PSEUDO_REGISTER)
2750 /* During reload, accept a pseudo */
2751 || (reload_in_progress && REG_P (op)
2752 && REGNO (op) >= FIRST_PSEUDO_REGISTER)))
2753 win = 1;
2754 else if (insn_extra_address_constraint (cn)
2755 /* Every address operand can be reloaded to fit. */
2756 && strict < 0)
2757 win = 1;
2758 /* Cater to architectures like IA-64 that define extra memory
2759 constraints without using define_memory_constraint. */
2760 else if (reload_in_progress
2761 && REG_P (op)
2762 && REGNO (op) >= FIRST_PSEUDO_REGISTER
2763 && reg_renumber[REGNO (op)] < 0
2764 && reg_equiv_mem (REGNO (op)) != 0
2765 && constraint_satisfied_p
2766 (reg_equiv_mem (REGNO (op)), cn))
2767 win = 1;
2768 break;
2769 }
2770 }
2771 while (p += len, c);
2772
2773 constraints[opno] = p;
2774 /* If this operand did not win somehow,
2775 this alternative loses. */
2776 if (! win)
2777 lose = 1;
2778 }
2779 /* This alternative won; the operands are ok.
2780 Change whichever operands this alternative says to change. */
2781 if (! lose)
2782 {
2783 int opno, eopno;
2784
2785 /* See if any earlyclobber operand conflicts with some other
2786 operand. */
2787
2788 if (strict > 0 && seen_earlyclobber_at >= 0)
2789 for (eopno = seen_earlyclobber_at;
2790 eopno < recog_data.n_operands;
2791 eopno++)
2792 /* Ignore earlyclobber operands now in memory,
2793 because we would often report failure when we have
2794 two memory operands, one of which was formerly a REG. */
2795 if (earlyclobber[eopno]
2796 && REG_P (recog_data.operand[eopno]))
2797 for (opno = 0; opno < recog_data.n_operands; opno++)
2798 if ((MEM_P (recog_data.operand[opno])
2799 || recog_data.operand_type[opno] != OP_OUT)
2800 && opno != eopno
2801 /* Ignore things like match_operator operands. */
2802 && *recog_data.constraints[opno] != 0
2803 && ! (matching_operands[opno] == eopno
2804 && operands_match_p (recog_data.operand[opno],
2805 recog_data.operand[eopno]))
2806 && ! safe_from_earlyclobber (recog_data.operand[opno],
2807 recog_data.operand[eopno]))
2808 lose = 1;
2809
2810 if (! lose)
2811 {
2812 while (--funny_match_index >= 0)
2813 {
2814 recog_data.operand[funny_match[funny_match_index].other]
2815 = recog_data.operand[funny_match[funny_match_index].this_op];
2816 }
2817
2818 /* For operands without < or > constraints reject side-effects. */
2819 if (AUTO_INC_DEC && recog_data.is_asm)
2820 {
2821 for (opno = 0; opno < recog_data.n_operands; opno++)
2822 if (MEM_P (recog_data.operand[opno]))
2823 switch (GET_CODE (XEXP (recog_data.operand[opno], 0)))
2824 {
2825 case PRE_INC:
2826 case POST_INC:
2827 case PRE_DEC:
2828 case POST_DEC:
2829 case PRE_MODIFY:
2830 case POST_MODIFY:
2831 if (strchr (recog_data.constraints[opno], '<') == NULL
2832 && strchr (recog_data.constraints[opno], '>')
2833 == NULL)
2834 return 0;
2835 break;
2836 default:
2837 break;
2838 }
2839 }
2840
2841 return 1;
2842 }
2843 }
2844
2845 which_alternative++;
2846 }
2847 while (which_alternative < recog_data.n_alternatives);
2848
2849 which_alternative = -1;
2850 /* If we are about to reject this, but we are not to test strictly,
2851 try a very loose test. Only return failure if it fails also. */
2852 if (strict == 0)
2853 return constrain_operands (-1, alternatives);
2854 else
2855 return 0;
2856 }
2857
2858 /* Return true iff OPERAND (assumed to be a REG rtx)
2859 is a hard reg in class CLASS when its regno is offset by OFFSET
2860 and changed to mode MODE.
2861 If REG occupies multiple hard regs, all of them must be in CLASS. */
2862
2863 bool
2864 reg_fits_class_p (const_rtx operand, reg_class_t cl, int offset,
2865 machine_mode mode)
2866 {
2867 unsigned int regno = REGNO (operand);
2868
2869 if (cl == NO_REGS)
2870 return false;
2871
2872 /* Regno must not be a pseudo register. Offset may be negative. */
2873 return (HARD_REGISTER_NUM_P (regno)
2874 && HARD_REGISTER_NUM_P (regno + offset)
2875 && in_hard_reg_set_p (reg_class_contents[(int) cl], mode,
2876 regno + offset));
2877 }
2878 \f
2879 /* Split single instruction. Helper function for split_all_insns and
2880 split_all_insns_noflow. Return last insn in the sequence if successful,
2881 or NULL if unsuccessful. */
2882
2883 static rtx_insn *
2884 split_insn (rtx_insn *insn)
2885 {
2886 /* Split insns here to get max fine-grain parallelism. */
2887 rtx_insn *first = PREV_INSN (insn);
2888 rtx_insn *last = try_split (PATTERN (insn), insn, 1);
2889 rtx insn_set, last_set, note;
2890
2891 if (last == insn)
2892 return NULL;
2893
2894 /* If the original instruction was a single set that was known to be
2895 equivalent to a constant, see if we can say the same about the last
2896 instruction in the split sequence. The two instructions must set
2897 the same destination. */
2898 insn_set = single_set (insn);
2899 if (insn_set)
2900 {
2901 last_set = single_set (last);
2902 if (last_set && rtx_equal_p (SET_DEST (last_set), SET_DEST (insn_set)))
2903 {
2904 note = find_reg_equal_equiv_note (insn);
2905 if (note && CONSTANT_P (XEXP (note, 0)))
2906 set_unique_reg_note (last, REG_EQUAL, XEXP (note, 0));
2907 else if (CONSTANT_P (SET_SRC (insn_set)))
2908 set_unique_reg_note (last, REG_EQUAL,
2909 copy_rtx (SET_SRC (insn_set)));
2910 }
2911 }
2912
2913 /* try_split returns the NOTE that INSN became. */
2914 SET_INSN_DELETED (insn);
2915
2916 /* ??? Coddle to md files that generate subregs in post-reload
2917 splitters instead of computing the proper hard register. */
2918 if (reload_completed && first != last)
2919 {
2920 first = NEXT_INSN (first);
2921 for (;;)
2922 {
2923 if (INSN_P (first))
2924 cleanup_subreg_operands (first);
2925 if (first == last)
2926 break;
2927 first = NEXT_INSN (first);
2928 }
2929 }
2930
2931 return last;
2932 }
2933
2934 /* Split all insns in the function. If UPD_LIFE, update life info after. */
2935
2936 void
2937 split_all_insns (void)
2938 {
2939 bool changed;
2940 basic_block bb;
2941
2942 auto_sbitmap blocks (last_basic_block_for_fn (cfun));
2943 bitmap_clear (blocks);
2944 changed = false;
2945
2946 FOR_EACH_BB_REVERSE_FN (bb, cfun)
2947 {
2948 rtx_insn *insn, *next;
2949 bool finish = false;
2950
2951 rtl_profile_for_bb (bb);
2952 for (insn = BB_HEAD (bb); !finish ; insn = next)
2953 {
2954 /* Can't use `next_real_insn' because that might go across
2955 CODE_LABELS and short-out basic blocks. */
2956 next = NEXT_INSN (insn);
2957 finish = (insn == BB_END (bb));
2958 if (INSN_P (insn))
2959 {
2960 rtx set = single_set (insn);
2961
2962 /* Don't split no-op move insns. These should silently
2963 disappear later in final. Splitting such insns would
2964 break the code that handles LIBCALL blocks. */
2965 if (set && set_noop_p (set))
2966 {
2967 /* Nops get in the way while scheduling, so delete them
2968 now if register allocation has already been done. It
2969 is too risky to try to do this before register
2970 allocation, and there are unlikely to be very many
2971 nops then anyways. */
2972 if (reload_completed)
2973 delete_insn_and_edges (insn);
2974 }
2975 else
2976 {
2977 if (split_insn (insn))
2978 {
2979 bitmap_set_bit (blocks, bb->index);
2980 changed = true;
2981 }
2982 }
2983 }
2984 }
2985 }
2986
2987 default_rtl_profile ();
2988 if (changed)
2989 find_many_sub_basic_blocks (blocks);
2990
2991 checking_verify_flow_info ();
2992 }
2993
2994 /* Same as split_all_insns, but do not expect CFG to be available.
2995 Used by machine dependent reorg passes. */
2996
2997 unsigned int
2998 split_all_insns_noflow (void)
2999 {
3000 rtx_insn *next, *insn;
3001
3002 for (insn = get_insns (); insn; insn = next)
3003 {
3004 next = NEXT_INSN (insn);
3005 if (INSN_P (insn))
3006 {
3007 /* Don't split no-op move insns. These should silently
3008 disappear later in final. Splitting such insns would
3009 break the code that handles LIBCALL blocks. */
3010 rtx set = single_set (insn);
3011 if (set && set_noop_p (set))
3012 {
3013 /* Nops get in the way while scheduling, so delete them
3014 now if register allocation has already been done. It
3015 is too risky to try to do this before register
3016 allocation, and there are unlikely to be very many
3017 nops then anyways.
3018
3019 ??? Should we use delete_insn when the CFG isn't valid? */
3020 if (reload_completed)
3021 delete_insn_and_edges (insn);
3022 }
3023 else
3024 split_insn (insn);
3025 }
3026 }
3027 return 0;
3028 }
3029 \f
3030 struct peep2_insn_data
3031 {
3032 rtx_insn *insn;
3033 regset live_before;
3034 };
3035
3036 static struct peep2_insn_data peep2_insn_data[MAX_INSNS_PER_PEEP2 + 1];
3037 static int peep2_current;
3038
3039 static bool peep2_do_rebuild_jump_labels;
3040 static bool peep2_do_cleanup_cfg;
3041
3042 /* The number of instructions available to match a peep2. */
3043 int peep2_current_count;
3044
3045 /* A marker indicating the last insn of the block. The live_before regset
3046 for this element is correct, indicating DF_LIVE_OUT for the block. */
3047 #define PEEP2_EOB invalid_insn_rtx
3048
3049 /* Wrap N to fit into the peep2_insn_data buffer. */
3050
3051 static int
3052 peep2_buf_position (int n)
3053 {
3054 if (n >= MAX_INSNS_PER_PEEP2 + 1)
3055 n -= MAX_INSNS_PER_PEEP2 + 1;
3056 return n;
3057 }
3058
3059 /* Return the Nth non-note insn after `current', or return NULL_RTX if it
3060 does not exist. Used by the recognizer to find the next insn to match
3061 in a multi-insn pattern. */
3062
3063 rtx_insn *
3064 peep2_next_insn (int n)
3065 {
3066 gcc_assert (n <= peep2_current_count);
3067
3068 n = peep2_buf_position (peep2_current + n);
3069
3070 return peep2_insn_data[n].insn;
3071 }
3072
3073 /* Return true if REGNO is dead before the Nth non-note insn
3074 after `current'. */
3075
3076 int
3077 peep2_regno_dead_p (int ofs, int regno)
3078 {
3079 gcc_assert (ofs < MAX_INSNS_PER_PEEP2 + 1);
3080
3081 ofs = peep2_buf_position (peep2_current + ofs);
3082
3083 gcc_assert (peep2_insn_data[ofs].insn != NULL_RTX);
3084
3085 return ! REGNO_REG_SET_P (peep2_insn_data[ofs].live_before, regno);
3086 }
3087
3088 /* Similarly for a REG. */
3089
3090 int
3091 peep2_reg_dead_p (int ofs, rtx reg)
3092 {
3093 gcc_assert (ofs < MAX_INSNS_PER_PEEP2 + 1);
3094
3095 ofs = peep2_buf_position (peep2_current + ofs);
3096
3097 gcc_assert (peep2_insn_data[ofs].insn != NULL_RTX);
3098
3099 unsigned int end_regno = END_REGNO (reg);
3100 for (unsigned int regno = REGNO (reg); regno < end_regno; ++regno)
3101 if (REGNO_REG_SET_P (peep2_insn_data[ofs].live_before, regno))
3102 return 0;
3103 return 1;
3104 }
3105
3106 /* Regno offset to be used in the register search. */
3107 static int search_ofs;
3108
3109 /* Try to find a hard register of mode MODE, matching the register class in
3110 CLASS_STR, which is available at the beginning of insn CURRENT_INSN and
3111 remains available until the end of LAST_INSN. LAST_INSN may be NULL_RTX,
3112 in which case the only condition is that the register must be available
3113 before CURRENT_INSN.
3114 Registers that already have bits set in REG_SET will not be considered.
3115
3116 If an appropriate register is available, it will be returned and the
3117 corresponding bit(s) in REG_SET will be set; otherwise, NULL_RTX is
3118 returned. */
3119
3120 rtx
3121 peep2_find_free_register (int from, int to, const char *class_str,
3122 machine_mode mode, HARD_REG_SET *reg_set)
3123 {
3124 enum reg_class cl;
3125 HARD_REG_SET live;
3126 df_ref def;
3127 int i;
3128
3129 gcc_assert (from < MAX_INSNS_PER_PEEP2 + 1);
3130 gcc_assert (to < MAX_INSNS_PER_PEEP2 + 1);
3131
3132 from = peep2_buf_position (peep2_current + from);
3133 to = peep2_buf_position (peep2_current + to);
3134
3135 gcc_assert (peep2_insn_data[from].insn != NULL_RTX);
3136 REG_SET_TO_HARD_REG_SET (live, peep2_insn_data[from].live_before);
3137
3138 while (from != to)
3139 {
3140 gcc_assert (peep2_insn_data[from].insn != NULL_RTX);
3141
3142 /* Don't use registers set or clobbered by the insn. */
3143 FOR_EACH_INSN_DEF (def, peep2_insn_data[from].insn)
3144 SET_HARD_REG_BIT (live, DF_REF_REGNO (def));
3145
3146 from = peep2_buf_position (from + 1);
3147 }
3148
3149 cl = reg_class_for_constraint (lookup_constraint (class_str));
3150
3151 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3152 {
3153 int raw_regno, regno, success, j;
3154
3155 /* Distribute the free registers as much as possible. */
3156 raw_regno = search_ofs + i;
3157 if (raw_regno >= FIRST_PSEUDO_REGISTER)
3158 raw_regno -= FIRST_PSEUDO_REGISTER;
3159 #ifdef REG_ALLOC_ORDER
3160 regno = reg_alloc_order[raw_regno];
3161 #else
3162 regno = raw_regno;
3163 #endif
3164
3165 /* Can it support the mode we need? */
3166 if (! HARD_REGNO_MODE_OK (regno, mode))
3167 continue;
3168
3169 success = 1;
3170 for (j = 0; success && j < hard_regno_nregs[regno][mode]; j++)
3171 {
3172 /* Don't allocate fixed registers. */
3173 if (fixed_regs[regno + j])
3174 {
3175 success = 0;
3176 break;
3177 }
3178 /* Don't allocate global registers. */
3179 if (global_regs[regno + j])
3180 {
3181 success = 0;
3182 break;
3183 }
3184 /* Make sure the register is of the right class. */
3185 if (! TEST_HARD_REG_BIT (reg_class_contents[cl], regno + j))
3186 {
3187 success = 0;
3188 break;
3189 }
3190 /* And that we don't create an extra save/restore. */
3191 if (! call_used_regs[regno + j] && ! df_regs_ever_live_p (regno + j))
3192 {
3193 success = 0;
3194 break;
3195 }
3196
3197 if (! targetm.hard_regno_scratch_ok (regno + j))
3198 {
3199 success = 0;
3200 break;
3201 }
3202
3203 /* And we don't clobber traceback for noreturn functions. */
3204 if ((regno + j == FRAME_POINTER_REGNUM
3205 || regno + j == HARD_FRAME_POINTER_REGNUM)
3206 && (! reload_completed || frame_pointer_needed))
3207 {
3208 success = 0;
3209 break;
3210 }
3211
3212 if (TEST_HARD_REG_BIT (*reg_set, regno + j)
3213 || TEST_HARD_REG_BIT (live, regno + j))
3214 {
3215 success = 0;
3216 break;
3217 }
3218 }
3219
3220 if (success)
3221 {
3222 add_to_hard_reg_set (reg_set, mode, regno);
3223
3224 /* Start the next search with the next register. */
3225 if (++raw_regno >= FIRST_PSEUDO_REGISTER)
3226 raw_regno = 0;
3227 search_ofs = raw_regno;
3228
3229 return gen_rtx_REG (mode, regno);
3230 }
3231 }
3232
3233 search_ofs = 0;
3234 return NULL_RTX;
3235 }
3236
3237 /* Forget all currently tracked instructions, only remember current
3238 LIVE regset. */
3239
3240 static void
3241 peep2_reinit_state (regset live)
3242 {
3243 int i;
3244
3245 /* Indicate that all slots except the last holds invalid data. */
3246 for (i = 0; i < MAX_INSNS_PER_PEEP2; ++i)
3247 peep2_insn_data[i].insn = NULL;
3248 peep2_current_count = 0;
3249
3250 /* Indicate that the last slot contains live_after data. */
3251 peep2_insn_data[MAX_INSNS_PER_PEEP2].insn = PEEP2_EOB;
3252 peep2_current = MAX_INSNS_PER_PEEP2;
3253
3254 COPY_REG_SET (peep2_insn_data[MAX_INSNS_PER_PEEP2].live_before, live);
3255 }
3256
3257 /* While scanning basic block BB, we found a match of length MATCH_LEN,
3258 starting at INSN. Perform the replacement, removing the old insns and
3259 replacing them with ATTEMPT. Returns the last insn emitted, or NULL
3260 if the replacement is rejected. */
3261
3262 static rtx_insn *
3263 peep2_attempt (basic_block bb, rtx_insn *insn, int match_len, rtx_insn *attempt)
3264 {
3265 int i;
3266 rtx_insn *last, *before_try, *x;
3267 rtx eh_note, as_note;
3268 rtx_insn *old_insn;
3269 rtx_insn *new_insn;
3270 bool was_call = false;
3271
3272 /* If we are splitting an RTX_FRAME_RELATED_P insn, do not allow it to
3273 match more than one insn, or to be split into more than one insn. */
3274 old_insn = peep2_insn_data[peep2_current].insn;
3275 if (RTX_FRAME_RELATED_P (old_insn))
3276 {
3277 bool any_note = false;
3278 rtx note;
3279
3280 if (match_len != 0)
3281 return NULL;
3282
3283 /* Look for one "active" insn. I.e. ignore any "clobber" insns that
3284 may be in the stream for the purpose of register allocation. */
3285 if (active_insn_p (attempt))
3286 new_insn = attempt;
3287 else
3288 new_insn = next_active_insn (attempt);
3289 if (next_active_insn (new_insn))
3290 return NULL;
3291
3292 /* We have a 1-1 replacement. Copy over any frame-related info. */
3293 RTX_FRAME_RELATED_P (new_insn) = 1;
3294
3295 /* Allow the backend to fill in a note during the split. */
3296 for (note = REG_NOTES (new_insn); note ; note = XEXP (note, 1))
3297 switch (REG_NOTE_KIND (note))
3298 {
3299 case REG_FRAME_RELATED_EXPR:
3300 case REG_CFA_DEF_CFA:
3301 case REG_CFA_ADJUST_CFA:
3302 case REG_CFA_OFFSET:
3303 case REG_CFA_REGISTER:
3304 case REG_CFA_EXPRESSION:
3305 case REG_CFA_RESTORE:
3306 case REG_CFA_SET_VDRAP:
3307 any_note = true;
3308 break;
3309 default:
3310 break;
3311 }
3312
3313 /* If the backend didn't supply a note, copy one over. */
3314 if (!any_note)
3315 for (note = REG_NOTES (old_insn); note ; note = XEXP (note, 1))
3316 switch (REG_NOTE_KIND (note))
3317 {
3318 case REG_FRAME_RELATED_EXPR:
3319 case REG_CFA_DEF_CFA:
3320 case REG_CFA_ADJUST_CFA:
3321 case REG_CFA_OFFSET:
3322 case REG_CFA_REGISTER:
3323 case REG_CFA_EXPRESSION:
3324 case REG_CFA_RESTORE:
3325 case REG_CFA_SET_VDRAP:
3326 add_reg_note (new_insn, REG_NOTE_KIND (note), XEXP (note, 0));
3327 any_note = true;
3328 break;
3329 default:
3330 break;
3331 }
3332
3333 /* If there still isn't a note, make sure the unwind info sees the
3334 same expression as before the split. */
3335 if (!any_note)
3336 {
3337 rtx old_set, new_set;
3338
3339 /* The old insn had better have been simple, or annotated. */
3340 old_set = single_set (old_insn);
3341 gcc_assert (old_set != NULL);
3342
3343 new_set = single_set (new_insn);
3344 if (!new_set || !rtx_equal_p (new_set, old_set))
3345 add_reg_note (new_insn, REG_FRAME_RELATED_EXPR, old_set);
3346 }
3347
3348 /* Copy prologue/epilogue status. This is required in order to keep
3349 proper placement of EPILOGUE_BEG and the DW_CFA_remember_state. */
3350 maybe_copy_prologue_epilogue_insn (old_insn, new_insn);
3351 }
3352
3353 /* If we are splitting a CALL_INSN, look for the CALL_INSN
3354 in SEQ and copy our CALL_INSN_FUNCTION_USAGE and other
3355 cfg-related call notes. */
3356 for (i = 0; i <= match_len; ++i)
3357 {
3358 int j;
3359 rtx note;
3360
3361 j = peep2_buf_position (peep2_current + i);
3362 old_insn = peep2_insn_data[j].insn;
3363 if (!CALL_P (old_insn))
3364 continue;
3365 was_call = true;
3366
3367 new_insn = attempt;
3368 while (new_insn != NULL_RTX)
3369 {
3370 if (CALL_P (new_insn))
3371 break;
3372 new_insn = NEXT_INSN (new_insn);
3373 }
3374
3375 gcc_assert (new_insn != NULL_RTX);
3376
3377 CALL_INSN_FUNCTION_USAGE (new_insn)
3378 = CALL_INSN_FUNCTION_USAGE (old_insn);
3379 SIBLING_CALL_P (new_insn) = SIBLING_CALL_P (old_insn);
3380
3381 for (note = REG_NOTES (old_insn);
3382 note;
3383 note = XEXP (note, 1))
3384 switch (REG_NOTE_KIND (note))
3385 {
3386 case REG_NORETURN:
3387 case REG_SETJMP:
3388 case REG_TM:
3389 add_reg_note (new_insn, REG_NOTE_KIND (note),
3390 XEXP (note, 0));
3391 break;
3392 default:
3393 /* Discard all other reg notes. */
3394 break;
3395 }
3396
3397 /* Croak if there is another call in the sequence. */
3398 while (++i <= match_len)
3399 {
3400 j = peep2_buf_position (peep2_current + i);
3401 old_insn = peep2_insn_data[j].insn;
3402 gcc_assert (!CALL_P (old_insn));
3403 }
3404 break;
3405 }
3406
3407 /* If we matched any instruction that had a REG_ARGS_SIZE, then
3408 move those notes over to the new sequence. */
3409 as_note = NULL;
3410 for (i = match_len; i >= 0; --i)
3411 {
3412 int j = peep2_buf_position (peep2_current + i);
3413 old_insn = peep2_insn_data[j].insn;
3414
3415 as_note = find_reg_note (old_insn, REG_ARGS_SIZE, NULL);
3416 if (as_note)
3417 break;
3418 }
3419
3420 i = peep2_buf_position (peep2_current + match_len);
3421 eh_note = find_reg_note (peep2_insn_data[i].insn, REG_EH_REGION, NULL_RTX);
3422
3423 /* Replace the old sequence with the new. */
3424 rtx_insn *peepinsn = peep2_insn_data[i].insn;
3425 last = emit_insn_after_setloc (attempt,
3426 peep2_insn_data[i].insn,
3427 INSN_LOCATION (peepinsn));
3428 before_try = PREV_INSN (insn);
3429 delete_insn_chain (insn, peep2_insn_data[i].insn, false);
3430
3431 /* Re-insert the EH_REGION notes. */
3432 if (eh_note || (was_call && nonlocal_goto_handler_labels))
3433 {
3434 edge eh_edge;
3435 edge_iterator ei;
3436
3437 FOR_EACH_EDGE (eh_edge, ei, bb->succs)
3438 if (eh_edge->flags & (EDGE_EH | EDGE_ABNORMAL_CALL))
3439 break;
3440
3441 if (eh_note)
3442 copy_reg_eh_region_note_backward (eh_note, last, before_try);
3443
3444 if (eh_edge)
3445 for (x = last; x != before_try; x = PREV_INSN (x))
3446 if (x != BB_END (bb)
3447 && (can_throw_internal (x)
3448 || can_nonlocal_goto (x)))
3449 {
3450 edge nfte, nehe;
3451 int flags;
3452
3453 nfte = split_block (bb, x);
3454 flags = (eh_edge->flags
3455 & (EDGE_EH | EDGE_ABNORMAL));
3456 if (CALL_P (x))
3457 flags |= EDGE_ABNORMAL_CALL;
3458 nehe = make_edge (nfte->src, eh_edge->dest,
3459 flags);
3460
3461 nehe->probability = eh_edge->probability;
3462 nfte->probability
3463 = REG_BR_PROB_BASE - nehe->probability;
3464
3465 peep2_do_cleanup_cfg |= purge_dead_edges (nfte->dest);
3466 bb = nfte->src;
3467 eh_edge = nehe;
3468 }
3469
3470 /* Converting possibly trapping insn to non-trapping is
3471 possible. Zap dummy outgoing edges. */
3472 peep2_do_cleanup_cfg |= purge_dead_edges (bb);
3473 }
3474
3475 /* Re-insert the ARGS_SIZE notes. */
3476 if (as_note)
3477 fixup_args_size_notes (before_try, last, INTVAL (XEXP (as_note, 0)));
3478
3479 /* If we generated a jump instruction, it won't have
3480 JUMP_LABEL set. Recompute after we're done. */
3481 for (x = last; x != before_try; x = PREV_INSN (x))
3482 if (JUMP_P (x))
3483 {
3484 peep2_do_rebuild_jump_labels = true;
3485 break;
3486 }
3487
3488 return last;
3489 }
3490
3491 /* After performing a replacement in basic block BB, fix up the life
3492 information in our buffer. LAST is the last of the insns that we
3493 emitted as a replacement. PREV is the insn before the start of
3494 the replacement. MATCH_LEN is the number of instructions that were
3495 matched, and which now need to be replaced in the buffer. */
3496
3497 static void
3498 peep2_update_life (basic_block bb, int match_len, rtx_insn *last,
3499 rtx_insn *prev)
3500 {
3501 int i = peep2_buf_position (peep2_current + match_len + 1);
3502 rtx_insn *x;
3503 regset_head live;
3504
3505 INIT_REG_SET (&live);
3506 COPY_REG_SET (&live, peep2_insn_data[i].live_before);
3507
3508 gcc_assert (peep2_current_count >= match_len + 1);
3509 peep2_current_count -= match_len + 1;
3510
3511 x = last;
3512 do
3513 {
3514 if (INSN_P (x))
3515 {
3516 df_insn_rescan (x);
3517 if (peep2_current_count < MAX_INSNS_PER_PEEP2)
3518 {
3519 peep2_current_count++;
3520 if (--i < 0)
3521 i = MAX_INSNS_PER_PEEP2;
3522 peep2_insn_data[i].insn = x;
3523 df_simulate_one_insn_backwards (bb, x, &live);
3524 COPY_REG_SET (peep2_insn_data[i].live_before, &live);
3525 }
3526 }
3527 x = PREV_INSN (x);
3528 }
3529 while (x != prev);
3530 CLEAR_REG_SET (&live);
3531
3532 peep2_current = i;
3533 }
3534
3535 /* Add INSN, which is in BB, at the end of the peep2 insn buffer if possible.
3536 Return true if we added it, false otherwise. The caller will try to match
3537 peepholes against the buffer if we return false; otherwise it will try to
3538 add more instructions to the buffer. */
3539
3540 static bool
3541 peep2_fill_buffer (basic_block bb, rtx_insn *insn, regset live)
3542 {
3543 int pos;
3544
3545 /* Once we have filled the maximum number of insns the buffer can hold,
3546 allow the caller to match the insns against peepholes. We wait until
3547 the buffer is full in case the target has similar peepholes of different
3548 length; we always want to match the longest if possible. */
3549 if (peep2_current_count == MAX_INSNS_PER_PEEP2)
3550 return false;
3551
3552 /* If an insn has RTX_FRAME_RELATED_P set, do not allow it to be matched with
3553 any other pattern, lest it change the semantics of the frame info. */
3554 if (RTX_FRAME_RELATED_P (insn))
3555 {
3556 /* Let the buffer drain first. */
3557 if (peep2_current_count > 0)
3558 return false;
3559 /* Now the insn will be the only thing in the buffer. */
3560 }
3561
3562 pos = peep2_buf_position (peep2_current + peep2_current_count);
3563 peep2_insn_data[pos].insn = insn;
3564 COPY_REG_SET (peep2_insn_data[pos].live_before, live);
3565 peep2_current_count++;
3566
3567 df_simulate_one_insn_forwards (bb, insn, live);
3568 return true;
3569 }
3570
3571 /* Perform the peephole2 optimization pass. */
3572
3573 static void
3574 peephole2_optimize (void)
3575 {
3576 rtx_insn *insn;
3577 bitmap live;
3578 int i;
3579 basic_block bb;
3580
3581 peep2_do_cleanup_cfg = false;
3582 peep2_do_rebuild_jump_labels = false;
3583
3584 df_set_flags (DF_LR_RUN_DCE);
3585 df_note_add_problem ();
3586 df_analyze ();
3587
3588 /* Initialize the regsets we're going to use. */
3589 for (i = 0; i < MAX_INSNS_PER_PEEP2 + 1; ++i)
3590 peep2_insn_data[i].live_before = BITMAP_ALLOC (&reg_obstack);
3591 search_ofs = 0;
3592 live = BITMAP_ALLOC (&reg_obstack);
3593
3594 FOR_EACH_BB_REVERSE_FN (bb, cfun)
3595 {
3596 bool past_end = false;
3597 int pos;
3598
3599 rtl_profile_for_bb (bb);
3600
3601 /* Start up propagation. */
3602 bitmap_copy (live, DF_LR_IN (bb));
3603 df_simulate_initialize_forwards (bb, live);
3604 peep2_reinit_state (live);
3605
3606 insn = BB_HEAD (bb);
3607 for (;;)
3608 {
3609 rtx_insn *attempt, *head;
3610 int match_len;
3611
3612 if (!past_end && !NONDEBUG_INSN_P (insn))
3613 {
3614 next_insn:
3615 insn = NEXT_INSN (insn);
3616 if (insn == NEXT_INSN (BB_END (bb)))
3617 past_end = true;
3618 continue;
3619 }
3620 if (!past_end && peep2_fill_buffer (bb, insn, live))
3621 goto next_insn;
3622
3623 /* If we did not fill an empty buffer, it signals the end of the
3624 block. */
3625 if (peep2_current_count == 0)
3626 break;
3627
3628 /* The buffer filled to the current maximum, so try to match. */
3629
3630 pos = peep2_buf_position (peep2_current + peep2_current_count);
3631 peep2_insn_data[pos].insn = PEEP2_EOB;
3632 COPY_REG_SET (peep2_insn_data[pos].live_before, live);
3633
3634 /* Match the peephole. */
3635 head = peep2_insn_data[peep2_current].insn;
3636 attempt = peephole2_insns (PATTERN (head), head, &match_len);
3637 if (attempt != NULL)
3638 {
3639 rtx_insn *last = peep2_attempt (bb, head, match_len, attempt);
3640 if (last)
3641 {
3642 peep2_update_life (bb, match_len, last, PREV_INSN (attempt));
3643 continue;
3644 }
3645 }
3646
3647 /* No match: advance the buffer by one insn. */
3648 peep2_current = peep2_buf_position (peep2_current + 1);
3649 peep2_current_count--;
3650 }
3651 }
3652
3653 default_rtl_profile ();
3654 for (i = 0; i < MAX_INSNS_PER_PEEP2 + 1; ++i)
3655 BITMAP_FREE (peep2_insn_data[i].live_before);
3656 BITMAP_FREE (live);
3657 if (peep2_do_rebuild_jump_labels)
3658 rebuild_jump_labels (get_insns ());
3659 if (peep2_do_cleanup_cfg)
3660 cleanup_cfg (CLEANUP_CFG_CHANGED);
3661 }
3662
3663 /* Common predicates for use with define_bypass. */
3664
3665 /* True if the dependency between OUT_INSN and IN_INSN is on the store
3666 data not the address operand(s) of the store. IN_INSN and OUT_INSN
3667 must be either a single_set or a PARALLEL with SETs inside. */
3668
3669 int
3670 store_data_bypass_p (rtx_insn *out_insn, rtx_insn *in_insn)
3671 {
3672 rtx out_set, in_set;
3673 rtx out_pat, in_pat;
3674 rtx out_exp, in_exp;
3675 int i, j;
3676
3677 in_set = single_set (in_insn);
3678 if (in_set)
3679 {
3680 if (!MEM_P (SET_DEST (in_set)))
3681 return false;
3682
3683 out_set = single_set (out_insn);
3684 if (out_set)
3685 {
3686 if (reg_mentioned_p (SET_DEST (out_set), SET_DEST (in_set)))
3687 return false;
3688 }
3689 else
3690 {
3691 out_pat = PATTERN (out_insn);
3692
3693 if (GET_CODE (out_pat) != PARALLEL)
3694 return false;
3695
3696 for (i = 0; i < XVECLEN (out_pat, 0); i++)
3697 {
3698 out_exp = XVECEXP (out_pat, 0, i);
3699
3700 if (GET_CODE (out_exp) == CLOBBER)
3701 continue;
3702
3703 gcc_assert (GET_CODE (out_exp) == SET);
3704
3705 if (reg_mentioned_p (SET_DEST (out_exp), SET_DEST (in_set)))
3706 return false;
3707 }
3708 }
3709 }
3710 else
3711 {
3712 in_pat = PATTERN (in_insn);
3713 gcc_assert (GET_CODE (in_pat) == PARALLEL);
3714
3715 for (i = 0; i < XVECLEN (in_pat, 0); i++)
3716 {
3717 in_exp = XVECEXP (in_pat, 0, i);
3718
3719 if (GET_CODE (in_exp) == CLOBBER)
3720 continue;
3721
3722 gcc_assert (GET_CODE (in_exp) == SET);
3723
3724 if (!MEM_P (SET_DEST (in_exp)))
3725 return false;
3726
3727 out_set = single_set (out_insn);
3728 if (out_set)
3729 {
3730 if (reg_mentioned_p (SET_DEST (out_set), SET_DEST (in_exp)))
3731 return false;
3732 }
3733 else
3734 {
3735 out_pat = PATTERN (out_insn);
3736 gcc_assert (GET_CODE (out_pat) == PARALLEL);
3737
3738 for (j = 0; j < XVECLEN (out_pat, 0); j++)
3739 {
3740 out_exp = XVECEXP (out_pat, 0, j);
3741
3742 if (GET_CODE (out_exp) == CLOBBER)
3743 continue;
3744
3745 gcc_assert (GET_CODE (out_exp) == SET);
3746
3747 if (reg_mentioned_p (SET_DEST (out_exp), SET_DEST (in_exp)))
3748 return false;
3749 }
3750 }
3751 }
3752 }
3753
3754 return true;
3755 }
3756
3757 /* True if the dependency between OUT_INSN and IN_INSN is in the IF_THEN_ELSE
3758 condition, and not the THEN or ELSE branch. OUT_INSN may be either a single
3759 or multiple set; IN_INSN should be single_set for truth, but for convenience
3760 of insn categorization may be any JUMP or CALL insn. */
3761
3762 int
3763 if_test_bypass_p (rtx_insn *out_insn, rtx_insn *in_insn)
3764 {
3765 rtx out_set, in_set;
3766
3767 in_set = single_set (in_insn);
3768 if (! in_set)
3769 {
3770 gcc_assert (JUMP_P (in_insn) || CALL_P (in_insn));
3771 return false;
3772 }
3773
3774 if (GET_CODE (SET_SRC (in_set)) != IF_THEN_ELSE)
3775 return false;
3776 in_set = SET_SRC (in_set);
3777
3778 out_set = single_set (out_insn);
3779 if (out_set)
3780 {
3781 if (reg_mentioned_p (SET_DEST (out_set), XEXP (in_set, 1))
3782 || reg_mentioned_p (SET_DEST (out_set), XEXP (in_set, 2)))
3783 return false;
3784 }
3785 else
3786 {
3787 rtx out_pat;
3788 int i;
3789
3790 out_pat = PATTERN (out_insn);
3791 gcc_assert (GET_CODE (out_pat) == PARALLEL);
3792
3793 for (i = 0; i < XVECLEN (out_pat, 0); i++)
3794 {
3795 rtx exp = XVECEXP (out_pat, 0, i);
3796
3797 if (GET_CODE (exp) == CLOBBER)
3798 continue;
3799
3800 gcc_assert (GET_CODE (exp) == SET);
3801
3802 if (reg_mentioned_p (SET_DEST (out_set), XEXP (in_set, 1))
3803 || reg_mentioned_p (SET_DEST (out_set), XEXP (in_set, 2)))
3804 return false;
3805 }
3806 }
3807
3808 return true;
3809 }
3810 \f
3811 static unsigned int
3812 rest_of_handle_peephole2 (void)
3813 {
3814 if (HAVE_peephole2)
3815 peephole2_optimize ();
3816
3817 return 0;
3818 }
3819
3820 namespace {
3821
3822 const pass_data pass_data_peephole2 =
3823 {
3824 RTL_PASS, /* type */
3825 "peephole2", /* name */
3826 OPTGROUP_NONE, /* optinfo_flags */
3827 TV_PEEPHOLE2, /* tv_id */
3828 0, /* properties_required */
3829 0, /* properties_provided */
3830 0, /* properties_destroyed */
3831 0, /* todo_flags_start */
3832 TODO_df_finish, /* todo_flags_finish */
3833 };
3834
3835 class pass_peephole2 : public rtl_opt_pass
3836 {
3837 public:
3838 pass_peephole2 (gcc::context *ctxt)
3839 : rtl_opt_pass (pass_data_peephole2, ctxt)
3840 {}
3841
3842 /* opt_pass methods: */
3843 /* The epiphany backend creates a second instance of this pass, so we need
3844 a clone method. */
3845 opt_pass * clone () { return new pass_peephole2 (m_ctxt); }
3846 virtual bool gate (function *) { return (optimize > 0 && flag_peephole2); }
3847 virtual unsigned int execute (function *)
3848 {
3849 return rest_of_handle_peephole2 ();
3850 }
3851
3852 }; // class pass_peephole2
3853
3854 } // anon namespace
3855
3856 rtl_opt_pass *
3857 make_pass_peephole2 (gcc::context *ctxt)
3858 {
3859 return new pass_peephole2 (ctxt);
3860 }
3861
3862 namespace {
3863
3864 const pass_data pass_data_split_all_insns =
3865 {
3866 RTL_PASS, /* type */
3867 "split1", /* name */
3868 OPTGROUP_NONE, /* optinfo_flags */
3869 TV_NONE, /* tv_id */
3870 0, /* properties_required */
3871 0, /* properties_provided */
3872 0, /* properties_destroyed */
3873 0, /* todo_flags_start */
3874 0, /* todo_flags_finish */
3875 };
3876
3877 class pass_split_all_insns : public rtl_opt_pass
3878 {
3879 public:
3880 pass_split_all_insns (gcc::context *ctxt)
3881 : rtl_opt_pass (pass_data_split_all_insns, ctxt)
3882 {}
3883
3884 /* opt_pass methods: */
3885 /* The epiphany backend creates a second instance of this pass, so
3886 we need a clone method. */
3887 opt_pass * clone () { return new pass_split_all_insns (m_ctxt); }
3888 virtual unsigned int execute (function *)
3889 {
3890 split_all_insns ();
3891 return 0;
3892 }
3893
3894 }; // class pass_split_all_insns
3895
3896 } // anon namespace
3897
3898 rtl_opt_pass *
3899 make_pass_split_all_insns (gcc::context *ctxt)
3900 {
3901 return new pass_split_all_insns (ctxt);
3902 }
3903
3904 static unsigned int
3905 rest_of_handle_split_after_reload (void)
3906 {
3907 /* If optimizing, then go ahead and split insns now. */
3908 #ifndef STACK_REGS
3909 if (optimize > 0)
3910 #endif
3911 split_all_insns ();
3912 return 0;
3913 }
3914
3915 namespace {
3916
3917 const pass_data pass_data_split_after_reload =
3918 {
3919 RTL_PASS, /* type */
3920 "split2", /* name */
3921 OPTGROUP_NONE, /* optinfo_flags */
3922 TV_NONE, /* tv_id */
3923 0, /* properties_required */
3924 0, /* properties_provided */
3925 0, /* properties_destroyed */
3926 0, /* todo_flags_start */
3927 0, /* todo_flags_finish */
3928 };
3929
3930 class pass_split_after_reload : public rtl_opt_pass
3931 {
3932 public:
3933 pass_split_after_reload (gcc::context *ctxt)
3934 : rtl_opt_pass (pass_data_split_after_reload, ctxt)
3935 {}
3936
3937 /* opt_pass methods: */
3938 virtual unsigned int execute (function *)
3939 {
3940 return rest_of_handle_split_after_reload ();
3941 }
3942
3943 }; // class pass_split_after_reload
3944
3945 } // anon namespace
3946
3947 rtl_opt_pass *
3948 make_pass_split_after_reload (gcc::context *ctxt)
3949 {
3950 return new pass_split_after_reload (ctxt);
3951 }
3952
3953 namespace {
3954
3955 const pass_data pass_data_split_before_regstack =
3956 {
3957 RTL_PASS, /* type */
3958 "split3", /* name */
3959 OPTGROUP_NONE, /* optinfo_flags */
3960 TV_NONE, /* tv_id */
3961 0, /* properties_required */
3962 0, /* properties_provided */
3963 0, /* properties_destroyed */
3964 0, /* todo_flags_start */
3965 0, /* todo_flags_finish */
3966 };
3967
3968 class pass_split_before_regstack : public rtl_opt_pass
3969 {
3970 public:
3971 pass_split_before_regstack (gcc::context *ctxt)
3972 : rtl_opt_pass (pass_data_split_before_regstack, ctxt)
3973 {}
3974
3975 /* opt_pass methods: */
3976 virtual bool gate (function *);
3977 virtual unsigned int execute (function *)
3978 {
3979 split_all_insns ();
3980 return 0;
3981 }
3982
3983 }; // class pass_split_before_regstack
3984
3985 bool
3986 pass_split_before_regstack::gate (function *)
3987 {
3988 #if HAVE_ATTR_length && defined (STACK_REGS)
3989 /* If flow2 creates new instructions which need splitting
3990 and scheduling after reload is not done, they might not be
3991 split until final which doesn't allow splitting
3992 if HAVE_ATTR_length. */
3993 # ifdef INSN_SCHEDULING
3994 return (optimize && !flag_schedule_insns_after_reload);
3995 # else
3996 return (optimize);
3997 # endif
3998 #else
3999 return 0;
4000 #endif
4001 }
4002
4003 } // anon namespace
4004
4005 rtl_opt_pass *
4006 make_pass_split_before_regstack (gcc::context *ctxt)
4007 {
4008 return new pass_split_before_regstack (ctxt);
4009 }
4010
4011 static unsigned int
4012 rest_of_handle_split_before_sched2 (void)
4013 {
4014 #ifdef INSN_SCHEDULING
4015 split_all_insns ();
4016 #endif
4017 return 0;
4018 }
4019
4020 namespace {
4021
4022 const pass_data pass_data_split_before_sched2 =
4023 {
4024 RTL_PASS, /* type */
4025 "split4", /* name */
4026 OPTGROUP_NONE, /* optinfo_flags */
4027 TV_NONE, /* tv_id */
4028 0, /* properties_required */
4029 0, /* properties_provided */
4030 0, /* properties_destroyed */
4031 0, /* todo_flags_start */
4032 0, /* todo_flags_finish */
4033 };
4034
4035 class pass_split_before_sched2 : public rtl_opt_pass
4036 {
4037 public:
4038 pass_split_before_sched2 (gcc::context *ctxt)
4039 : rtl_opt_pass (pass_data_split_before_sched2, ctxt)
4040 {}
4041
4042 /* opt_pass methods: */
4043 virtual bool gate (function *)
4044 {
4045 #ifdef INSN_SCHEDULING
4046 return optimize > 0 && flag_schedule_insns_after_reload;
4047 #else
4048 return false;
4049 #endif
4050 }
4051
4052 virtual unsigned int execute (function *)
4053 {
4054 return rest_of_handle_split_before_sched2 ();
4055 }
4056
4057 }; // class pass_split_before_sched2
4058
4059 } // anon namespace
4060
4061 rtl_opt_pass *
4062 make_pass_split_before_sched2 (gcc::context *ctxt)
4063 {
4064 return new pass_split_before_sched2 (ctxt);
4065 }
4066
4067 namespace {
4068
4069 const pass_data pass_data_split_for_shorten_branches =
4070 {
4071 RTL_PASS, /* type */
4072 "split5", /* name */
4073 OPTGROUP_NONE, /* optinfo_flags */
4074 TV_NONE, /* tv_id */
4075 0, /* properties_required */
4076 0, /* properties_provided */
4077 0, /* properties_destroyed */
4078 0, /* todo_flags_start */
4079 0, /* todo_flags_finish */
4080 };
4081
4082 class pass_split_for_shorten_branches : public rtl_opt_pass
4083 {
4084 public:
4085 pass_split_for_shorten_branches (gcc::context *ctxt)
4086 : rtl_opt_pass (pass_data_split_for_shorten_branches, ctxt)
4087 {}
4088
4089 /* opt_pass methods: */
4090 virtual bool gate (function *)
4091 {
4092 /* The placement of the splitting that we do for shorten_branches
4093 depends on whether regstack is used by the target or not. */
4094 #if HAVE_ATTR_length && !defined (STACK_REGS)
4095 return true;
4096 #else
4097 return false;
4098 #endif
4099 }
4100
4101 virtual unsigned int execute (function *)
4102 {
4103 return split_all_insns_noflow ();
4104 }
4105
4106 }; // class pass_split_for_shorten_branches
4107
4108 } // anon namespace
4109
4110 rtl_opt_pass *
4111 make_pass_split_for_shorten_branches (gcc::context *ctxt)
4112 {
4113 return new pass_split_for_shorten_branches (ctxt);
4114 }
4115
4116 /* (Re)initialize the target information after a change in target. */
4117
4118 void
4119 recog_init ()
4120 {
4121 /* The information is zero-initialized, so we don't need to do anything
4122 first time round. */
4123 if (!this_target_recog->x_initialized)
4124 {
4125 this_target_recog->x_initialized = true;
4126 return;
4127 }
4128 memset (this_target_recog->x_bool_attr_masks, 0,
4129 sizeof (this_target_recog->x_bool_attr_masks));
4130 for (unsigned int i = 0; i < NUM_INSN_CODES; ++i)
4131 if (this_target_recog->x_op_alt[i])
4132 {
4133 free (this_target_recog->x_op_alt[i]);
4134 this_target_recog->x_op_alt[i] = 0;
4135 }
4136 }