1 /* Subroutines used by or related to instruction recognition.
2 Copyright (C) 1987-2015 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify it under
7 the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 3, or (at your option) any later
11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
23 #include "coretypes.h"
28 #include "double-int.h"
35 #include "rtl-error.h"
37 #include "insn-config.h"
38 #include "insn-attr.h"
39 #include "hard-reg-set.h"
42 #include "addresses.h"
47 #include "statistics.h"
49 #include "fixed-value.h"
59 #include "dominance.h"
63 #include "cfgcleanup.h"
64 #include "basic-block.h"
67 #include "tree-pass.h"
69 #include "insn-codes.h"
71 #ifndef STACK_PUSH_CODE
72 #ifdef STACK_GROWS_DOWNWARD
73 #define STACK_PUSH_CODE PRE_DEC
75 #define STACK_PUSH_CODE PRE_INC
79 #ifndef STACK_POP_CODE
80 #ifdef STACK_GROWS_DOWNWARD
81 #define STACK_POP_CODE POST_INC
83 #define STACK_POP_CODE POST_DEC
87 static void validate_replace_rtx_1 (rtx
*, rtx
, rtx
, rtx
, bool);
88 static void validate_replace_src_1 (rtx
*, void *);
89 static rtx
split_insn (rtx_insn
*);
91 struct target_recog default_target_recog
;
93 struct target_recog
*this_target_recog
= &default_target_recog
;
96 /* Nonzero means allow operands to be volatile.
97 This should be 0 if you are generating rtl, such as if you are calling
98 the functions in optabs.c and expmed.c (most of the time).
99 This should be 1 if all valid insns need to be recognized,
100 such as in reginfo.c and final.c and reload.c.
102 init_recog and init_recog_no_volatile are responsible for setting this. */
106 struct recog_data_d recog_data
;
108 /* Contains a vector of operand_alternative structures, such that
109 operand OP of alternative A is at index A * n_operands + OP.
110 Set up by preprocess_constraints. */
111 const operand_alternative
*recog_op_alt
;
113 /* Used to provide recog_op_alt for asms. */
114 static operand_alternative asm_op_alt
[MAX_RECOG_OPERANDS
115 * MAX_RECOG_ALTERNATIVES
];
117 /* On return from `constrain_operands', indicate which alternative
120 int which_alternative
;
122 /* Nonzero after end of reload pass.
123 Set to 1 or 0 by toplev.c.
124 Controls the significance of (SUBREG (MEM)). */
126 int reload_completed
;
128 /* Nonzero after thread_prologue_and_epilogue_insns has run. */
129 int epilogue_completed
;
131 /* Initialize data used by the function `recog'.
132 This must be called once in the compilation of a function
133 before any insn recognition may be done in the function. */
136 init_recog_no_volatile (void)
148 /* Return true if labels in asm operands BODY are LABEL_REFs. */
151 asm_labels_ok (rtx body
)
156 asmop
= extract_asm_operands (body
);
157 if (asmop
== NULL_RTX
)
160 for (i
= 0; i
< ASM_OPERANDS_LABEL_LENGTH (asmop
); i
++)
161 if (GET_CODE (ASM_OPERANDS_LABEL (asmop
, i
)) != LABEL_REF
)
167 /* Check that X is an insn-body for an `asm' with operands
168 and that the operands mentioned in it are legitimate. */
171 check_asm_operands (rtx x
)
175 const char **constraints
;
178 if (!asm_labels_ok (x
))
181 /* Post-reload, be more strict with things. */
182 if (reload_completed
)
184 /* ??? Doh! We've not got the wrapping insn. Cook one up. */
185 rtx_insn
*insn
= make_insn_raw (x
);
187 constrain_operands (1, get_enabled_alternatives (insn
));
188 return which_alternative
>= 0;
191 noperands
= asm_noperands (x
);
197 operands
= XALLOCAVEC (rtx
, noperands
);
198 constraints
= XALLOCAVEC (const char *, noperands
);
200 decode_asm_operands (x
, operands
, NULL
, constraints
, NULL
, NULL
);
202 for (i
= 0; i
< noperands
; i
++)
204 const char *c
= constraints
[i
];
207 if (! asm_operand_ok (operands
[i
], c
, constraints
))
214 /* Static data for the next two routines. */
216 typedef struct change_t
225 static change_t
*changes
;
226 static int changes_allocated
;
228 static int num_changes
= 0;
230 /* Validate a proposed change to OBJECT. LOC is the location in the rtl
231 at which NEW_RTX will be placed. If OBJECT is zero, no validation is done,
232 the change is simply made.
234 Two types of objects are supported: If OBJECT is a MEM, memory_address_p
235 will be called with the address and mode as parameters. If OBJECT is
236 an INSN, CALL_INSN, or JUMP_INSN, the insn will be re-recognized with
239 IN_GROUP is nonzero if this is part of a group of changes that must be
240 performed as a group. In that case, the changes will be stored. The
241 function `apply_change_group' will validate and apply the changes.
243 If IN_GROUP is zero, this is a single change. Try to recognize the insn
244 or validate the memory reference with the change applied. If the result
245 is not valid for the machine, suppress the change and return zero.
246 Otherwise, perform the change and return 1. */
249 validate_change_1 (rtx object
, rtx
*loc
, rtx new_rtx
, bool in_group
, bool unshare
)
253 if (old
== new_rtx
|| rtx_equal_p (old
, new_rtx
))
256 gcc_assert (in_group
!= 0 || num_changes
== 0);
260 /* Save the information describing this change. */
261 if (num_changes
>= changes_allocated
)
263 if (changes_allocated
== 0)
264 /* This value allows for repeated substitutions inside complex
265 indexed addresses, or changes in up to 5 insns. */
266 changes_allocated
= MAX_RECOG_OPERANDS
* 5;
268 changes_allocated
*= 2;
270 changes
= XRESIZEVEC (change_t
, changes
, changes_allocated
);
273 changes
[num_changes
].object
= object
;
274 changes
[num_changes
].loc
= loc
;
275 changes
[num_changes
].old
= old
;
276 changes
[num_changes
].unshare
= unshare
;
278 if (object
&& !MEM_P (object
))
280 /* Set INSN_CODE to force rerecognition of insn. Save old code in
282 changes
[num_changes
].old_code
= INSN_CODE (object
);
283 INSN_CODE (object
) = -1;
288 /* If we are making a group of changes, return 1. Otherwise, validate the
289 change group we made. */
294 return apply_change_group ();
297 /* Wrapper for validate_change_1 without the UNSHARE argument defaulting
301 validate_change (rtx object
, rtx
*loc
, rtx new_rtx
, bool in_group
)
303 return validate_change_1 (object
, loc
, new_rtx
, in_group
, false);
306 /* Wrapper for validate_change_1 without the UNSHARE argument defaulting
310 validate_unshare_change (rtx object
, rtx
*loc
, rtx new_rtx
, bool in_group
)
312 return validate_change_1 (object
, loc
, new_rtx
, in_group
, true);
316 /* Keep X canonicalized if some changes have made it non-canonical; only
317 modifies the operands of X, not (for example) its code. Simplifications
318 are not the job of this routine.
320 Return true if anything was changed. */
322 canonicalize_change_group (rtx insn
, rtx x
)
324 if (COMMUTATIVE_P (x
)
325 && swap_commutative_operands_p (XEXP (x
, 0), XEXP (x
, 1)))
327 /* Oops, the caller has made X no longer canonical.
328 Let's redo the changes in the correct order. */
329 rtx tem
= XEXP (x
, 0);
330 validate_unshare_change (insn
, &XEXP (x
, 0), XEXP (x
, 1), 1);
331 validate_unshare_change (insn
, &XEXP (x
, 1), tem
, 1);
339 /* This subroutine of apply_change_group verifies whether the changes to INSN
340 were valid; i.e. whether INSN can still be recognized.
342 If IN_GROUP is true clobbers which have to be added in order to
343 match the instructions will be added to the current change group.
344 Otherwise the changes will take effect immediately. */
347 insn_invalid_p (rtx_insn
*insn
, bool in_group
)
349 rtx pat
= PATTERN (insn
);
350 int num_clobbers
= 0;
351 /* If we are before reload and the pattern is a SET, see if we can add
353 int icode
= recog (pat
, insn
,
354 (GET_CODE (pat
) == SET
355 && ! reload_completed
356 && ! reload_in_progress
)
357 ? &num_clobbers
: 0);
358 int is_asm
= icode
< 0 && asm_noperands (PATTERN (insn
)) >= 0;
361 /* If this is an asm and the operand aren't legal, then fail. Likewise if
362 this is not an asm and the insn wasn't recognized. */
363 if ((is_asm
&& ! check_asm_operands (PATTERN (insn
)))
364 || (!is_asm
&& icode
< 0))
367 /* If we have to add CLOBBERs, fail if we have to add ones that reference
368 hard registers since our callers can't know if they are live or not.
369 Otherwise, add them. */
370 if (num_clobbers
> 0)
374 if (added_clobbers_hard_reg_p (icode
))
377 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (num_clobbers
+ 1));
378 XVECEXP (newpat
, 0, 0) = pat
;
379 add_clobbers (newpat
, icode
);
381 validate_change (insn
, &PATTERN (insn
), newpat
, 1);
383 PATTERN (insn
) = pat
= newpat
;
386 /* After reload, verify that all constraints are satisfied. */
387 if (reload_completed
)
391 if (! constrain_operands (1, get_preferred_alternatives (insn
)))
395 INSN_CODE (insn
) = icode
;
399 /* Return number of changes made and not validated yet. */
401 num_changes_pending (void)
406 /* Tentatively apply the changes numbered NUM and up.
407 Return 1 if all changes are valid, zero otherwise. */
410 verify_changes (int num
)
413 rtx last_validated
= NULL_RTX
;
415 /* The changes have been applied and all INSN_CODEs have been reset to force
418 The changes are valid if we aren't given an object, or if we are
419 given a MEM and it still is a valid address, or if this is in insn
420 and it is recognized. In the latter case, if reload has completed,
421 we also require that the operands meet the constraints for
424 for (i
= num
; i
< num_changes
; i
++)
426 rtx object
= changes
[i
].object
;
428 /* If there is no object to test or if it is the same as the one we
429 already tested, ignore it. */
430 if (object
== 0 || object
== last_validated
)
435 if (! memory_address_addr_space_p (GET_MODE (object
),
437 MEM_ADDR_SPACE (object
)))
440 else if (/* changes[i].old might be zero, e.g. when putting a
441 REG_FRAME_RELATED_EXPR into a previously empty list. */
443 && REG_P (changes
[i
].old
)
444 && asm_noperands (PATTERN (object
)) > 0
445 && REG_EXPR (changes
[i
].old
) != NULL_TREE
446 && DECL_ASSEMBLER_NAME_SET_P (REG_EXPR (changes
[i
].old
))
447 && DECL_REGISTER (REG_EXPR (changes
[i
].old
)))
449 /* Don't allow changes of hard register operands to inline
450 assemblies if they have been defined as register asm ("x"). */
453 else if (DEBUG_INSN_P (object
))
455 else if (insn_invalid_p (as_a
<rtx_insn
*> (object
), true))
457 rtx pat
= PATTERN (object
);
459 /* Perhaps we couldn't recognize the insn because there were
460 extra CLOBBERs at the end. If so, try to re-recognize
461 without the last CLOBBER (later iterations will cause each of
462 them to be eliminated, in turn). But don't do this if we
463 have an ASM_OPERAND. */
464 if (GET_CODE (pat
) == PARALLEL
465 && GET_CODE (XVECEXP (pat
, 0, XVECLEN (pat
, 0) - 1)) == CLOBBER
466 && asm_noperands (PATTERN (object
)) < 0)
470 if (XVECLEN (pat
, 0) == 2)
471 newpat
= XVECEXP (pat
, 0, 0);
477 = gen_rtx_PARALLEL (VOIDmode
,
478 rtvec_alloc (XVECLEN (pat
, 0) - 1));
479 for (j
= 0; j
< XVECLEN (newpat
, 0); j
++)
480 XVECEXP (newpat
, 0, j
) = XVECEXP (pat
, 0, j
);
483 /* Add a new change to this group to replace the pattern
484 with this new pattern. Then consider this change
485 as having succeeded. The change we added will
486 cause the entire call to fail if things remain invalid.
488 Note that this can lose if a later change than the one
489 we are processing specified &XVECEXP (PATTERN (object), 0, X)
490 but this shouldn't occur. */
492 validate_change (object
, &PATTERN (object
), newpat
, 1);
495 else if (GET_CODE (pat
) == USE
|| GET_CODE (pat
) == CLOBBER
496 || GET_CODE (pat
) == VAR_LOCATION
)
497 /* If this insn is a CLOBBER or USE, it is always valid, but is
503 last_validated
= object
;
506 return (i
== num_changes
);
509 /* A group of changes has previously been issued with validate_change
510 and verified with verify_changes. Call df_insn_rescan for each of
511 the insn changed and clear num_changes. */
514 confirm_change_group (void)
517 rtx last_object
= NULL
;
519 for (i
= 0; i
< num_changes
; i
++)
521 rtx object
= changes
[i
].object
;
523 if (changes
[i
].unshare
)
524 *changes
[i
].loc
= copy_rtx (*changes
[i
].loc
);
526 /* Avoid unnecessary rescanning when multiple changes to same instruction
530 if (object
!= last_object
&& last_object
&& INSN_P (last_object
))
531 df_insn_rescan (as_a
<rtx_insn
*> (last_object
));
532 last_object
= object
;
536 if (last_object
&& INSN_P (last_object
))
537 df_insn_rescan (as_a
<rtx_insn
*> (last_object
));
541 /* Apply a group of changes previously issued with `validate_change'.
542 If all changes are valid, call confirm_change_group and return 1,
543 otherwise, call cancel_changes and return 0. */
546 apply_change_group (void)
548 if (verify_changes (0))
550 confirm_change_group ();
561 /* Return the number of changes so far in the current group. */
564 num_validated_changes (void)
569 /* Retract the changes numbered NUM and up. */
572 cancel_changes (int num
)
576 /* Back out all the changes. Do this in the opposite order in which
578 for (i
= num_changes
- 1; i
>= num
; i
--)
580 *changes
[i
].loc
= changes
[i
].old
;
581 if (changes
[i
].object
&& !MEM_P (changes
[i
].object
))
582 INSN_CODE (changes
[i
].object
) = changes
[i
].old_code
;
587 /* Reduce conditional compilation elsewhere. */
590 #define CODE_FOR_extv CODE_FOR_nothing
594 #define CODE_FOR_extzv CODE_FOR_nothing
597 /* A subroutine of validate_replace_rtx_1 that tries to simplify the resulting
601 simplify_while_replacing (rtx
*loc
, rtx to
, rtx object
,
602 machine_mode op0_mode
)
605 enum rtx_code code
= GET_CODE (x
);
606 rtx new_rtx
= NULL_RTX
;
608 if (SWAPPABLE_OPERANDS_P (x
)
609 && swap_commutative_operands_p (XEXP (x
, 0), XEXP (x
, 1)))
611 validate_unshare_change (object
, loc
,
612 gen_rtx_fmt_ee (COMMUTATIVE_ARITH_P (x
) ? code
613 : swap_condition (code
),
614 GET_MODE (x
), XEXP (x
, 1),
620 /* Canonicalize arithmetics with all constant operands. */
621 switch (GET_RTX_CLASS (code
))
624 if (CONSTANT_P (XEXP (x
, 0)))
625 new_rtx
= simplify_unary_operation (code
, GET_MODE (x
), XEXP (x
, 0),
630 if (CONSTANT_P (XEXP (x
, 0)) && CONSTANT_P (XEXP (x
, 1)))
631 new_rtx
= simplify_binary_operation (code
, GET_MODE (x
), XEXP (x
, 0),
635 case RTX_COMM_COMPARE
:
636 if (CONSTANT_P (XEXP (x
, 0)) && CONSTANT_P (XEXP (x
, 1)))
637 new_rtx
= simplify_relational_operation (code
, GET_MODE (x
), op0_mode
,
638 XEXP (x
, 0), XEXP (x
, 1));
645 validate_change (object
, loc
, new_rtx
, 1);
652 /* If we have a PLUS whose second operand is now a CONST_INT, use
653 simplify_gen_binary to try to simplify it.
654 ??? We may want later to remove this, once simplification is
655 separated from this function. */
656 if (CONST_INT_P (XEXP (x
, 1)) && XEXP (x
, 1) == to
)
657 validate_change (object
, loc
,
659 (PLUS
, GET_MODE (x
), XEXP (x
, 0), XEXP (x
, 1)), 1);
662 if (CONST_SCALAR_INT_P (XEXP (x
, 1)))
663 validate_change (object
, loc
,
665 (PLUS
, GET_MODE (x
), XEXP (x
, 0),
666 simplify_gen_unary (NEG
,
667 GET_MODE (x
), XEXP (x
, 1),
672 if (GET_MODE (XEXP (x
, 0)) == VOIDmode
)
674 new_rtx
= simplify_gen_unary (code
, GET_MODE (x
), XEXP (x
, 0),
676 /* If any of the above failed, substitute in something that
677 we know won't be recognized. */
679 new_rtx
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
680 validate_change (object
, loc
, new_rtx
, 1);
684 /* All subregs possible to simplify should be simplified. */
685 new_rtx
= simplify_subreg (GET_MODE (x
), SUBREG_REG (x
), op0_mode
,
688 /* Subregs of VOIDmode operands are incorrect. */
689 if (!new_rtx
&& GET_MODE (SUBREG_REG (x
)) == VOIDmode
)
690 new_rtx
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
692 validate_change (object
, loc
, new_rtx
, 1);
696 /* If we are replacing a register with memory, try to change the memory
697 to be the mode required for memory in extract operations (this isn't
698 likely to be an insertion operation; if it was, nothing bad will
699 happen, we might just fail in some cases). */
701 if (MEM_P (XEXP (x
, 0))
702 && CONST_INT_P (XEXP (x
, 1))
703 && CONST_INT_P (XEXP (x
, 2))
704 && !mode_dependent_address_p (XEXP (XEXP (x
, 0), 0),
705 MEM_ADDR_SPACE (XEXP (x
, 0)))
706 && !MEM_VOLATILE_P (XEXP (x
, 0)))
708 machine_mode wanted_mode
= VOIDmode
;
709 machine_mode is_mode
= GET_MODE (XEXP (x
, 0));
710 int pos
= INTVAL (XEXP (x
, 2));
712 if (GET_CODE (x
) == ZERO_EXTRACT
&& HAVE_extzv
)
714 wanted_mode
= insn_data
[CODE_FOR_extzv
].operand
[1].mode
;
715 if (wanted_mode
== VOIDmode
)
716 wanted_mode
= word_mode
;
718 else if (GET_CODE (x
) == SIGN_EXTRACT
&& HAVE_extv
)
720 wanted_mode
= insn_data
[CODE_FOR_extv
].operand
[1].mode
;
721 if (wanted_mode
== VOIDmode
)
722 wanted_mode
= word_mode
;
725 /* If we have a narrower mode, we can do something. */
726 if (wanted_mode
!= VOIDmode
727 && GET_MODE_SIZE (wanted_mode
) < GET_MODE_SIZE (is_mode
))
729 int offset
= pos
/ BITS_PER_UNIT
;
732 /* If the bytes and bits are counted differently, we
733 must adjust the offset. */
734 if (BYTES_BIG_ENDIAN
!= BITS_BIG_ENDIAN
)
736 (GET_MODE_SIZE (is_mode
) - GET_MODE_SIZE (wanted_mode
) -
739 gcc_assert (GET_MODE_PRECISION (wanted_mode
)
740 == GET_MODE_BITSIZE (wanted_mode
));
741 pos
%= GET_MODE_BITSIZE (wanted_mode
);
743 newmem
= adjust_address_nv (XEXP (x
, 0), wanted_mode
, offset
);
745 validate_change (object
, &XEXP (x
, 2), GEN_INT (pos
), 1);
746 validate_change (object
, &XEXP (x
, 0), newmem
, 1);
757 /* Replace every occurrence of FROM in X with TO. Mark each change with
758 validate_change passing OBJECT. */
761 validate_replace_rtx_1 (rtx
*loc
, rtx from
, rtx to
, rtx object
,
768 machine_mode op0_mode
= VOIDmode
;
769 int prev_changes
= num_changes
;
775 fmt
= GET_RTX_FORMAT (code
);
777 op0_mode
= GET_MODE (XEXP (x
, 0));
779 /* X matches FROM if it is the same rtx or they are both referring to the
780 same register in the same mode. Avoid calling rtx_equal_p unless the
781 operands look similar. */
784 || (REG_P (x
) && REG_P (from
)
785 && GET_MODE (x
) == GET_MODE (from
)
786 && REGNO (x
) == REGNO (from
))
787 || (GET_CODE (x
) == GET_CODE (from
) && GET_MODE (x
) == GET_MODE (from
)
788 && rtx_equal_p (x
, from
)))
790 validate_unshare_change (object
, loc
, to
, 1);
794 /* Call ourself recursively to perform the replacements.
795 We must not replace inside already replaced expression, otherwise we
796 get infinite recursion for replacements like (reg X)->(subreg (reg X))
797 so we must special case shared ASM_OPERANDS. */
799 if (GET_CODE (x
) == PARALLEL
)
801 for (j
= XVECLEN (x
, 0) - 1; j
>= 0; j
--)
803 if (j
&& GET_CODE (XVECEXP (x
, 0, j
)) == SET
804 && GET_CODE (SET_SRC (XVECEXP (x
, 0, j
))) == ASM_OPERANDS
)
806 /* Verify that operands are really shared. */
807 gcc_assert (ASM_OPERANDS_INPUT_VEC (SET_SRC (XVECEXP (x
, 0, 0)))
808 == ASM_OPERANDS_INPUT_VEC (SET_SRC (XVECEXP
810 validate_replace_rtx_1 (&SET_DEST (XVECEXP (x
, 0, j
)),
811 from
, to
, object
, simplify
);
814 validate_replace_rtx_1 (&XVECEXP (x
, 0, j
), from
, to
, object
,
819 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
822 validate_replace_rtx_1 (&XEXP (x
, i
), from
, to
, object
, simplify
);
823 else if (fmt
[i
] == 'E')
824 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
825 validate_replace_rtx_1 (&XVECEXP (x
, i
, j
), from
, to
, object
,
829 /* If we didn't substitute, there is nothing more to do. */
830 if (num_changes
== prev_changes
)
833 /* ??? The regmove is no more, so is this aberration still necessary? */
834 /* Allow substituted expression to have different mode. This is used by
835 regmove to change mode of pseudo register. */
836 if (fmt
[0] == 'e' && GET_MODE (XEXP (x
, 0)) != VOIDmode
)
837 op0_mode
= GET_MODE (XEXP (x
, 0));
839 /* Do changes needed to keep rtx consistent. Don't do any other
840 simplifications, as it is not our job. */
842 simplify_while_replacing (loc
, to
, object
, op0_mode
);
845 /* Try replacing every occurrence of FROM in subexpression LOC of INSN
846 with TO. After all changes have been made, validate by seeing
847 if INSN is still valid. */
850 validate_replace_rtx_subexp (rtx from
, rtx to
, rtx insn
, rtx
*loc
)
852 validate_replace_rtx_1 (loc
, from
, to
, insn
, true);
853 return apply_change_group ();
856 /* Try replacing every occurrence of FROM in INSN with TO. After all
857 changes have been made, validate by seeing if INSN is still valid. */
860 validate_replace_rtx (rtx from
, rtx to
, rtx insn
)
862 validate_replace_rtx_1 (&PATTERN (insn
), from
, to
, insn
, true);
863 return apply_change_group ();
866 /* Try replacing every occurrence of FROM in WHERE with TO. Assume that WHERE
867 is a part of INSN. After all changes have been made, validate by seeing if
869 validate_replace_rtx (from, to, insn) is equivalent to
870 validate_replace_rtx_part (from, to, &PATTERN (insn), insn). */
873 validate_replace_rtx_part (rtx from
, rtx to
, rtx
*where
, rtx insn
)
875 validate_replace_rtx_1 (where
, from
, to
, insn
, true);
876 return apply_change_group ();
879 /* Same as above, but do not simplify rtx afterwards. */
881 validate_replace_rtx_part_nosimplify (rtx from
, rtx to
, rtx
*where
,
884 validate_replace_rtx_1 (where
, from
, to
, insn
, false);
885 return apply_change_group ();
889 /* Try replacing every occurrence of FROM in INSN with TO. This also
890 will replace in REG_EQUAL and REG_EQUIV notes. */
893 validate_replace_rtx_group (rtx from
, rtx to
, rtx insn
)
896 validate_replace_rtx_1 (&PATTERN (insn
), from
, to
, insn
, true);
897 for (note
= REG_NOTES (insn
); note
; note
= XEXP (note
, 1))
898 if (REG_NOTE_KIND (note
) == REG_EQUAL
899 || REG_NOTE_KIND (note
) == REG_EQUIV
)
900 validate_replace_rtx_1 (&XEXP (note
, 0), from
, to
, insn
, true);
903 /* Function called by note_uses to replace used subexpressions. */
904 struct validate_replace_src_data
906 rtx from
; /* Old RTX */
907 rtx to
; /* New RTX */
908 rtx insn
; /* Insn in which substitution is occurring. */
912 validate_replace_src_1 (rtx
*x
, void *data
)
914 struct validate_replace_src_data
*d
915 = (struct validate_replace_src_data
*) data
;
917 validate_replace_rtx_1 (x
, d
->from
, d
->to
, d
->insn
, true);
920 /* Try replacing every occurrence of FROM in INSN with TO, avoiding
924 validate_replace_src_group (rtx from
, rtx to
, rtx insn
)
926 struct validate_replace_src_data d
;
931 note_uses (&PATTERN (insn
), validate_replace_src_1
, &d
);
934 /* Try simplify INSN.
935 Invoke simplify_rtx () on every SET_SRC and SET_DEST inside the INSN's
936 pattern and return true if something was simplified. */
939 validate_simplify_insn (rtx insn
)
945 pat
= PATTERN (insn
);
947 if (GET_CODE (pat
) == SET
)
949 newpat
= simplify_rtx (SET_SRC (pat
));
950 if (newpat
&& !rtx_equal_p (SET_SRC (pat
), newpat
))
951 validate_change (insn
, &SET_SRC (pat
), newpat
, 1);
952 newpat
= simplify_rtx (SET_DEST (pat
));
953 if (newpat
&& !rtx_equal_p (SET_DEST (pat
), newpat
))
954 validate_change (insn
, &SET_DEST (pat
), newpat
, 1);
956 else if (GET_CODE (pat
) == PARALLEL
)
957 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
959 rtx s
= XVECEXP (pat
, 0, i
);
961 if (GET_CODE (XVECEXP (pat
, 0, i
)) == SET
)
963 newpat
= simplify_rtx (SET_SRC (s
));
964 if (newpat
&& !rtx_equal_p (SET_SRC (s
), newpat
))
965 validate_change (insn
, &SET_SRC (s
), newpat
, 1);
966 newpat
= simplify_rtx (SET_DEST (s
));
967 if (newpat
&& !rtx_equal_p (SET_DEST (s
), newpat
))
968 validate_change (insn
, &SET_DEST (s
), newpat
, 1);
971 return ((num_changes_pending () > 0) && (apply_change_group () > 0));
974 /* Return 1 if the insn using CC0 set by INSN does not contain
975 any ordered tests applied to the condition codes.
976 EQ and NE tests do not count. */
979 next_insn_tests_no_inequality (rtx insn
)
981 rtx_insn
*next
= next_cc0_user (insn
);
983 /* If there is no next insn, we have to take the conservative choice. */
987 return (INSN_P (next
)
988 && ! inequality_comparisons_p (PATTERN (next
)));
991 /* Return 1 if OP is a valid general operand for machine mode MODE.
992 This is either a register reference, a memory reference,
993 or a constant. In the case of a memory reference, the address
994 is checked for general validity for the target machine.
996 Register and memory references must have mode MODE in order to be valid,
997 but some constants have no machine mode and are valid for any mode.
999 If MODE is VOIDmode, OP is checked for validity for whatever mode
1002 The main use of this function is as a predicate in match_operand
1003 expressions in the machine description. */
1006 general_operand (rtx op
, machine_mode mode
)
1008 enum rtx_code code
= GET_CODE (op
);
1010 if (mode
== VOIDmode
)
1011 mode
= GET_MODE (op
);
1013 /* Don't accept CONST_INT or anything similar
1014 if the caller wants something floating. */
1015 if (GET_MODE (op
) == VOIDmode
&& mode
!= VOIDmode
1016 && GET_MODE_CLASS (mode
) != MODE_INT
1017 && GET_MODE_CLASS (mode
) != MODE_PARTIAL_INT
)
1020 if (CONST_INT_P (op
)
1022 && trunc_int_for_mode (INTVAL (op
), mode
) != INTVAL (op
))
1025 if (CONSTANT_P (op
))
1026 return ((GET_MODE (op
) == VOIDmode
|| GET_MODE (op
) == mode
1027 || mode
== VOIDmode
)
1028 && (! flag_pic
|| LEGITIMATE_PIC_OPERAND_P (op
))
1029 && targetm
.legitimate_constant_p (mode
== VOIDmode
1033 /* Except for certain constants with VOIDmode, already checked for,
1034 OP's mode must match MODE if MODE specifies a mode. */
1036 if (GET_MODE (op
) != mode
)
1041 rtx sub
= SUBREG_REG (op
);
1043 #ifdef INSN_SCHEDULING
1044 /* On machines that have insn scheduling, we want all memory
1045 reference to be explicit, so outlaw paradoxical SUBREGs.
1046 However, we must allow them after reload so that they can
1047 get cleaned up by cleanup_subreg_operands. */
1048 if (!reload_completed
&& MEM_P (sub
)
1049 && GET_MODE_SIZE (mode
) > GET_MODE_SIZE (GET_MODE (sub
)))
1052 /* Avoid memories with nonzero SUBREG_BYTE, as offsetting the memory
1053 may result in incorrect reference. We should simplify all valid
1054 subregs of MEM anyway. But allow this after reload because we
1055 might be called from cleanup_subreg_operands.
1057 ??? This is a kludge. */
1058 if (!reload_completed
&& SUBREG_BYTE (op
) != 0
1062 #ifdef CANNOT_CHANGE_MODE_CLASS
1064 && REGNO (sub
) < FIRST_PSEUDO_REGISTER
1065 && REG_CANNOT_CHANGE_MODE_P (REGNO (sub
), GET_MODE (sub
), mode
)
1066 && GET_MODE_CLASS (GET_MODE (sub
)) != MODE_COMPLEX_INT
1067 && GET_MODE_CLASS (GET_MODE (sub
)) != MODE_COMPLEX_FLOAT
1068 /* LRA can generate some invalid SUBREGS just for matched
1069 operand reload presentation. LRA needs to treat them as
1071 && ! LRA_SUBREG_P (op
))
1075 /* FLOAT_MODE subregs can't be paradoxical. Combine will occasionally
1076 create such rtl, and we must reject it. */
1077 if (SCALAR_FLOAT_MODE_P (GET_MODE (op
))
1078 /* LRA can use subreg to store a floating point value in an
1079 integer mode. Although the floating point and the
1080 integer modes need the same number of hard registers, the
1081 size of floating point mode can be less than the integer
1083 && ! lra_in_progress
1084 && GET_MODE_SIZE (GET_MODE (op
)) > GET_MODE_SIZE (GET_MODE (sub
)))
1088 code
= GET_CODE (op
);
1092 return (REGNO (op
) >= FIRST_PSEUDO_REGISTER
1093 || in_hard_reg_set_p (operand_reg_set
, GET_MODE (op
), REGNO (op
)));
1097 rtx y
= XEXP (op
, 0);
1099 if (! volatile_ok
&& MEM_VOLATILE_P (op
))
1102 /* Use the mem's mode, since it will be reloaded thus. LRA can
1103 generate move insn with invalid addresses which is made valid
1104 and efficiently calculated by LRA through further numerous
1107 || memory_address_addr_space_p (GET_MODE (op
), y
, MEM_ADDR_SPACE (op
)))
1114 /* Return 1 if OP is a valid memory address for a memory reference
1117 The main use of this function is as a predicate in match_operand
1118 expressions in the machine description. */
1121 address_operand (rtx op
, machine_mode mode
)
1123 return memory_address_p (mode
, op
);
1126 /* Return 1 if OP is a register reference of mode MODE.
1127 If MODE is VOIDmode, accept a register in any mode.
1129 The main use of this function is as a predicate in match_operand
1130 expressions in the machine description. */
1133 register_operand (rtx op
, machine_mode mode
)
1135 if (GET_CODE (op
) == SUBREG
)
1137 rtx sub
= SUBREG_REG (op
);
1139 /* Before reload, we can allow (SUBREG (MEM...)) as a register operand
1140 because it is guaranteed to be reloaded into one.
1141 Just make sure the MEM is valid in itself.
1142 (Ideally, (SUBREG (MEM)...) should not exist after reload,
1143 but currently it does result from (SUBREG (REG)...) where the
1144 reg went on the stack.) */
1145 if (!REG_P (sub
) && (reload_completed
|| !MEM_P (sub
)))
1148 else if (!REG_P (op
))
1150 return general_operand (op
, mode
);
1153 /* Return 1 for a register in Pmode; ignore the tested mode. */
1156 pmode_register_operand (rtx op
, machine_mode mode ATTRIBUTE_UNUSED
)
1158 return register_operand (op
, Pmode
);
1161 /* Return 1 if OP should match a MATCH_SCRATCH, i.e., if it is a SCRATCH
1162 or a hard register. */
1165 scratch_operand (rtx op
, machine_mode mode
)
1167 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
1170 return (GET_CODE (op
) == SCRATCH
1173 || (REGNO (op
) < FIRST_PSEUDO_REGISTER
1174 && REGNO_REG_CLASS (REGNO (op
)) != NO_REGS
))));
1177 /* Return 1 if OP is a valid immediate operand for mode MODE.
1179 The main use of this function is as a predicate in match_operand
1180 expressions in the machine description. */
1183 immediate_operand (rtx op
, machine_mode mode
)
1185 /* Don't accept CONST_INT or anything similar
1186 if the caller wants something floating. */
1187 if (GET_MODE (op
) == VOIDmode
&& mode
!= VOIDmode
1188 && GET_MODE_CLASS (mode
) != MODE_INT
1189 && GET_MODE_CLASS (mode
) != MODE_PARTIAL_INT
)
1192 if (CONST_INT_P (op
)
1194 && trunc_int_for_mode (INTVAL (op
), mode
) != INTVAL (op
))
1197 return (CONSTANT_P (op
)
1198 && (GET_MODE (op
) == mode
|| mode
== VOIDmode
1199 || GET_MODE (op
) == VOIDmode
)
1200 && (! flag_pic
|| LEGITIMATE_PIC_OPERAND_P (op
))
1201 && targetm
.legitimate_constant_p (mode
== VOIDmode
1206 /* Returns 1 if OP is an operand that is a CONST_INT of mode MODE. */
1209 const_int_operand (rtx op
, machine_mode mode
)
1211 if (!CONST_INT_P (op
))
1214 if (mode
!= VOIDmode
1215 && trunc_int_for_mode (INTVAL (op
), mode
) != INTVAL (op
))
1221 #if TARGET_SUPPORTS_WIDE_INT
1222 /* Returns 1 if OP is an operand that is a CONST_INT or CONST_WIDE_INT
1225 const_scalar_int_operand (rtx op
, machine_mode mode
)
1227 if (!CONST_SCALAR_INT_P (op
))
1230 if (CONST_INT_P (op
))
1231 return const_int_operand (op
, mode
);
1233 if (mode
!= VOIDmode
)
1235 int prec
= GET_MODE_PRECISION (mode
);
1236 int bitsize
= GET_MODE_BITSIZE (mode
);
1238 if (CONST_WIDE_INT_NUNITS (op
) * HOST_BITS_PER_WIDE_INT
> bitsize
)
1241 if (prec
== bitsize
)
1245 /* Multiword partial int. */
1247 = CONST_WIDE_INT_ELT (op
, CONST_WIDE_INT_NUNITS (op
) - 1);
1248 return (sext_hwi (x
, prec
& (HOST_BITS_PER_WIDE_INT
- 1)) == x
);
1254 /* Returns 1 if OP is an operand that is a constant integer or constant
1255 floating-point number of MODE. */
1258 const_double_operand (rtx op
, machine_mode mode
)
1260 return (GET_CODE (op
) == CONST_DOUBLE
)
1261 && (GET_MODE (op
) == mode
|| mode
== VOIDmode
);
1264 /* Returns 1 if OP is an operand that is a constant integer or constant
1265 floating-point number of MODE. */
1268 const_double_operand (rtx op
, machine_mode mode
)
1270 /* Don't accept CONST_INT or anything similar
1271 if the caller wants something floating. */
1272 if (GET_MODE (op
) == VOIDmode
&& mode
!= VOIDmode
1273 && GET_MODE_CLASS (mode
) != MODE_INT
1274 && GET_MODE_CLASS (mode
) != MODE_PARTIAL_INT
)
1277 return ((CONST_DOUBLE_P (op
) || CONST_INT_P (op
))
1278 && (mode
== VOIDmode
|| GET_MODE (op
) == mode
1279 || GET_MODE (op
) == VOIDmode
));
1282 /* Return 1 if OP is a general operand that is not an immediate
1283 operand of mode MODE. */
1286 nonimmediate_operand (rtx op
, machine_mode mode
)
1288 return (general_operand (op
, mode
) && ! CONSTANT_P (op
));
1291 /* Return 1 if OP is a register reference or immediate value of mode MODE. */
1294 nonmemory_operand (rtx op
, machine_mode mode
)
1296 if (CONSTANT_P (op
))
1297 return immediate_operand (op
, mode
);
1298 return register_operand (op
, mode
);
1301 /* Return 1 if OP is a valid operand that stands for pushing a
1302 value of mode MODE onto the stack.
1304 The main use of this function is as a predicate in match_operand
1305 expressions in the machine description. */
1308 push_operand (rtx op
, machine_mode mode
)
1310 unsigned int rounded_size
= GET_MODE_SIZE (mode
);
1312 #ifdef PUSH_ROUNDING
1313 rounded_size
= PUSH_ROUNDING (rounded_size
);
1319 if (mode
!= VOIDmode
&& GET_MODE (op
) != mode
)
1324 if (rounded_size
== GET_MODE_SIZE (mode
))
1326 if (GET_CODE (op
) != STACK_PUSH_CODE
)
1331 if (GET_CODE (op
) != PRE_MODIFY
1332 || GET_CODE (XEXP (op
, 1)) != PLUS
1333 || XEXP (XEXP (op
, 1), 0) != XEXP (op
, 0)
1334 || !CONST_INT_P (XEXP (XEXP (op
, 1), 1))
1335 #ifdef STACK_GROWS_DOWNWARD
1336 || INTVAL (XEXP (XEXP (op
, 1), 1)) != - (int) rounded_size
1338 || INTVAL (XEXP (XEXP (op
, 1), 1)) != (int) rounded_size
1344 return XEXP (op
, 0) == stack_pointer_rtx
;
1347 /* Return 1 if OP is a valid operand that stands for popping a
1348 value of mode MODE off the stack.
1350 The main use of this function is as a predicate in match_operand
1351 expressions in the machine description. */
1354 pop_operand (rtx op
, machine_mode mode
)
1359 if (mode
!= VOIDmode
&& GET_MODE (op
) != mode
)
1364 if (GET_CODE (op
) != STACK_POP_CODE
)
1367 return XEXP (op
, 0) == stack_pointer_rtx
;
1370 /* Return 1 if ADDR is a valid memory address
1371 for mode MODE in address space AS. */
1374 memory_address_addr_space_p (machine_mode mode ATTRIBUTE_UNUSED
,
1375 rtx addr
, addr_space_t as
)
1377 #ifdef GO_IF_LEGITIMATE_ADDRESS
1378 gcc_assert (ADDR_SPACE_GENERIC_P (as
));
1379 GO_IF_LEGITIMATE_ADDRESS (mode
, addr
, win
);
1385 return targetm
.addr_space
.legitimate_address_p (mode
, addr
, 0, as
);
1389 /* Return 1 if OP is a valid memory reference with mode MODE,
1390 including a valid address.
1392 The main use of this function is as a predicate in match_operand
1393 expressions in the machine description. */
1396 memory_operand (rtx op
, machine_mode mode
)
1400 if (! reload_completed
)
1401 /* Note that no SUBREG is a memory operand before end of reload pass,
1402 because (SUBREG (MEM...)) forces reloading into a register. */
1403 return MEM_P (op
) && general_operand (op
, mode
);
1405 if (mode
!= VOIDmode
&& GET_MODE (op
) != mode
)
1409 if (GET_CODE (inner
) == SUBREG
)
1410 inner
= SUBREG_REG (inner
);
1412 return (MEM_P (inner
) && general_operand (op
, mode
));
1415 /* Return 1 if OP is a valid indirect memory reference with mode MODE;
1416 that is, a memory reference whose address is a general_operand. */
1419 indirect_operand (rtx op
, machine_mode mode
)
1421 /* Before reload, a SUBREG isn't in memory (see memory_operand, above). */
1422 if (! reload_completed
1423 && GET_CODE (op
) == SUBREG
&& MEM_P (SUBREG_REG (op
)))
1425 int offset
= SUBREG_BYTE (op
);
1426 rtx inner
= SUBREG_REG (op
);
1428 if (mode
!= VOIDmode
&& GET_MODE (op
) != mode
)
1431 /* The only way that we can have a general_operand as the resulting
1432 address is if OFFSET is zero and the address already is an operand
1433 or if the address is (plus Y (const_int -OFFSET)) and Y is an
1436 return ((offset
== 0 && general_operand (XEXP (inner
, 0), Pmode
))
1437 || (GET_CODE (XEXP (inner
, 0)) == PLUS
1438 && CONST_INT_P (XEXP (XEXP (inner
, 0), 1))
1439 && INTVAL (XEXP (XEXP (inner
, 0), 1)) == -offset
1440 && general_operand (XEXP (XEXP (inner
, 0), 0), Pmode
)));
1444 && memory_operand (op
, mode
)
1445 && general_operand (XEXP (op
, 0), Pmode
));
1448 /* Return 1 if this is an ordered comparison operator (not including
1449 ORDERED and UNORDERED). */
1452 ordered_comparison_operator (rtx op
, machine_mode mode
)
1454 if (mode
!= VOIDmode
&& GET_MODE (op
) != mode
)
1456 switch (GET_CODE (op
))
1474 /* Return 1 if this is a comparison operator. This allows the use of
1475 MATCH_OPERATOR to recognize all the branch insns. */
1478 comparison_operator (rtx op
, machine_mode mode
)
1480 return ((mode
== VOIDmode
|| GET_MODE (op
) == mode
)
1481 && COMPARISON_P (op
));
1484 /* If BODY is an insn body that uses ASM_OPERANDS, return it. */
1487 extract_asm_operands (rtx body
)
1490 switch (GET_CODE (body
))
1496 /* Single output operand: BODY is (set OUTPUT (asm_operands ...)). */
1497 tmp
= SET_SRC (body
);
1498 if (GET_CODE (tmp
) == ASM_OPERANDS
)
1503 tmp
= XVECEXP (body
, 0, 0);
1504 if (GET_CODE (tmp
) == ASM_OPERANDS
)
1506 if (GET_CODE (tmp
) == SET
)
1508 tmp
= SET_SRC (tmp
);
1509 if (GET_CODE (tmp
) == ASM_OPERANDS
)
1520 /* If BODY is an insn body that uses ASM_OPERANDS,
1521 return the number of operands (both input and output) in the insn.
1522 Otherwise return -1. */
1525 asm_noperands (const_rtx body
)
1527 rtx asm_op
= extract_asm_operands (CONST_CAST_RTX (body
));
1533 if (GET_CODE (body
) == SET
)
1535 else if (GET_CODE (body
) == PARALLEL
)
1538 if (GET_CODE (XVECEXP (body
, 0, 0)) == SET
)
1540 /* Multiple output operands, or 1 output plus some clobbers:
1542 [(set OUTPUT (asm_operands ...))... (clobber (reg ...))...]. */
1543 /* Count backwards through CLOBBERs to determine number of SETs. */
1544 for (i
= XVECLEN (body
, 0); i
> 0; i
--)
1546 if (GET_CODE (XVECEXP (body
, 0, i
- 1)) == SET
)
1548 if (GET_CODE (XVECEXP (body
, 0, i
- 1)) != CLOBBER
)
1552 /* N_SETS is now number of output operands. */
1555 /* Verify that all the SETs we have
1556 came from a single original asm_operands insn
1557 (so that invalid combinations are blocked). */
1558 for (i
= 0; i
< n_sets
; i
++)
1560 rtx elt
= XVECEXP (body
, 0, i
);
1561 if (GET_CODE (elt
) != SET
)
1563 if (GET_CODE (SET_SRC (elt
)) != ASM_OPERANDS
)
1565 /* If these ASM_OPERANDS rtx's came from different original insns
1566 then they aren't allowed together. */
1567 if (ASM_OPERANDS_INPUT_VEC (SET_SRC (elt
))
1568 != ASM_OPERANDS_INPUT_VEC (asm_op
))
1574 /* 0 outputs, but some clobbers:
1575 body is [(asm_operands ...) (clobber (reg ...))...]. */
1576 /* Make sure all the other parallel things really are clobbers. */
1577 for (i
= XVECLEN (body
, 0) - 1; i
> 0; i
--)
1578 if (GET_CODE (XVECEXP (body
, 0, i
)) != CLOBBER
)
1583 return (ASM_OPERANDS_INPUT_LENGTH (asm_op
)
1584 + ASM_OPERANDS_LABEL_LENGTH (asm_op
) + n_sets
);
1587 /* Assuming BODY is an insn body that uses ASM_OPERANDS,
1588 copy its operands (both input and output) into the vector OPERANDS,
1589 the locations of the operands within the insn into the vector OPERAND_LOCS,
1590 and the constraints for the operands into CONSTRAINTS.
1591 Write the modes of the operands into MODES.
1592 Return the assembler-template.
1594 If MODES, OPERAND_LOCS, CONSTRAINTS or OPERANDS is 0,
1595 we don't store that info. */
1598 decode_asm_operands (rtx body
, rtx
*operands
, rtx
**operand_locs
,
1599 const char **constraints
, machine_mode
*modes
,
1602 int nbase
= 0, n
, i
;
1605 switch (GET_CODE (body
))
1608 /* Zero output asm: BODY is (asm_operands ...). */
1613 /* Single output asm: BODY is (set OUTPUT (asm_operands ...)). */
1614 asmop
= SET_SRC (body
);
1616 /* The output is in the SET.
1617 Its constraint is in the ASM_OPERANDS itself. */
1619 operands
[0] = SET_DEST (body
);
1621 operand_locs
[0] = &SET_DEST (body
);
1623 constraints
[0] = ASM_OPERANDS_OUTPUT_CONSTRAINT (asmop
);
1625 modes
[0] = GET_MODE (SET_DEST (body
));
1631 int nparallel
= XVECLEN (body
, 0); /* Includes CLOBBERs. */
1633 asmop
= XVECEXP (body
, 0, 0);
1634 if (GET_CODE (asmop
) == SET
)
1636 asmop
= SET_SRC (asmop
);
1638 /* At least one output, plus some CLOBBERs. The outputs are in
1639 the SETs. Their constraints are in the ASM_OPERANDS itself. */
1640 for (i
= 0; i
< nparallel
; i
++)
1642 if (GET_CODE (XVECEXP (body
, 0, i
)) == CLOBBER
)
1643 break; /* Past last SET */
1645 operands
[i
] = SET_DEST (XVECEXP (body
, 0, i
));
1647 operand_locs
[i
] = &SET_DEST (XVECEXP (body
, 0, i
));
1649 constraints
[i
] = XSTR (SET_SRC (XVECEXP (body
, 0, i
)), 1);
1651 modes
[i
] = GET_MODE (SET_DEST (XVECEXP (body
, 0, i
)));
1662 n
= ASM_OPERANDS_INPUT_LENGTH (asmop
);
1663 for (i
= 0; i
< n
; i
++)
1666 operand_locs
[nbase
+ i
] = &ASM_OPERANDS_INPUT (asmop
, i
);
1668 operands
[nbase
+ i
] = ASM_OPERANDS_INPUT (asmop
, i
);
1670 constraints
[nbase
+ i
] = ASM_OPERANDS_INPUT_CONSTRAINT (asmop
, i
);
1672 modes
[nbase
+ i
] = ASM_OPERANDS_INPUT_MODE (asmop
, i
);
1676 n
= ASM_OPERANDS_LABEL_LENGTH (asmop
);
1677 for (i
= 0; i
< n
; i
++)
1680 operand_locs
[nbase
+ i
] = &ASM_OPERANDS_LABEL (asmop
, i
);
1682 operands
[nbase
+ i
] = ASM_OPERANDS_LABEL (asmop
, i
);
1684 constraints
[nbase
+ i
] = "";
1686 modes
[nbase
+ i
] = Pmode
;
1690 *loc
= ASM_OPERANDS_SOURCE_LOCATION (asmop
);
1692 return ASM_OPERANDS_TEMPLATE (asmop
);
1695 /* Parse inline assembly string STRING and determine which operands are
1696 referenced by % markers. For the first NOPERANDS operands, set USED[I]
1697 to true if operand I is referenced.
1699 This is intended to distinguish barrier-like asms such as:
1701 asm ("" : "=m" (...));
1703 from real references such as:
1705 asm ("sw\t$0, %0" : "=m" (...)); */
1708 get_referenced_operands (const char *string
, bool *used
,
1709 unsigned int noperands
)
1711 memset (used
, 0, sizeof (bool) * noperands
);
1712 const char *p
= string
;
1718 /* A letter followed by a digit indicates an operand number. */
1719 if (ISALPHA (p
[0]) && ISDIGIT (p
[1]))
1724 unsigned long opnum
= strtoul (p
, &endptr
, 10);
1725 if (endptr
!= p
&& opnum
< noperands
)
1739 /* Check if an asm_operand matches its constraints.
1740 Return > 0 if ok, = 0 if bad, < 0 if inconclusive. */
1743 asm_operand_ok (rtx op
, const char *constraint
, const char **constraints
)
1747 bool incdec_ok
= false;
1750 /* Use constrain_operands after reload. */
1751 gcc_assert (!reload_completed
);
1753 /* Empty constraint string is the same as "X,...,X", i.e. X for as
1754 many alternatives as required to match the other operands. */
1755 if (*constraint
== '\0')
1760 enum constraint_num cn
;
1761 char c
= *constraint
;
1769 case '0': case '1': case '2': case '3': case '4':
1770 case '5': case '6': case '7': case '8': case '9':
1771 /* If caller provided constraints pointer, look up
1772 the matching constraint. Otherwise, our caller should have
1773 given us the proper matching constraint, but we can't
1774 actually fail the check if they didn't. Indicate that
1775 results are inconclusive. */
1779 unsigned long match
;
1781 match
= strtoul (constraint
, &end
, 10);
1783 result
= asm_operand_ok (op
, constraints
[match
], NULL
);
1784 constraint
= (const char *) end
;
1790 while (ISDIGIT (*constraint
));
1796 /* The rest of the compiler assumes that reloading the address
1797 of a MEM into a register will make it fit an 'o' constraint.
1798 That is, if it sees a MEM operand for an 'o' constraint,
1799 it assumes that (mem (base-reg)) will fit.
1801 That assumption fails on targets that don't have offsettable
1802 addresses at all. We therefore need to treat 'o' asm
1803 constraints as a special case and only accept operands that
1804 are already offsettable, thus proving that at least one
1805 offsettable address exists. */
1806 case 'o': /* offsettable */
1807 if (offsettable_nonstrict_memref_p (op
))
1812 if (general_operand (op
, VOIDmode
))
1819 /* ??? Before auto-inc-dec, auto inc/dec insns are not supposed
1820 to exist, excepting those that expand_call created. Further,
1821 on some machines which do not have generalized auto inc/dec,
1822 an inc/dec is not a memory_operand.
1824 Match any memory and hope things are resolved after reload. */
1828 cn
= lookup_constraint (constraint
);
1829 switch (get_constraint_type (cn
))
1833 && reg_class_for_constraint (cn
) != NO_REGS
1834 && GET_MODE (op
) != BLKmode
1835 && register_operand (op
, VOIDmode
))
1842 && insn_const_int_ok_for_constraint (INTVAL (op
), cn
))
1847 /* Every memory operand can be reloaded to fit. */
1848 result
= result
|| memory_operand (op
, VOIDmode
);
1852 /* Every address operand can be reloaded to fit. */
1853 result
= result
|| address_operand (op
, VOIDmode
);
1857 result
= result
|| constraint_satisfied_p (op
, cn
);
1862 len
= CONSTRAINT_LEN (c
, constraint
);
1865 while (--len
&& *constraint
);
1871 /* For operands without < or > constraints reject side-effects. */
1872 if (!incdec_ok
&& result
&& MEM_P (op
))
1873 switch (GET_CODE (XEXP (op
, 0)))
1890 /* Given an rtx *P, if it is a sum containing an integer constant term,
1891 return the location (type rtx *) of the pointer to that constant term.
1892 Otherwise, return a null pointer. */
1895 find_constant_term_loc (rtx
*p
)
1898 enum rtx_code code
= GET_CODE (*p
);
1900 /* If *P IS such a constant term, P is its location. */
1902 if (code
== CONST_INT
|| code
== SYMBOL_REF
|| code
== LABEL_REF
1906 /* Otherwise, if not a sum, it has no constant term. */
1908 if (GET_CODE (*p
) != PLUS
)
1911 /* If one of the summands is constant, return its location. */
1913 if (XEXP (*p
, 0) && CONSTANT_P (XEXP (*p
, 0))
1914 && XEXP (*p
, 1) && CONSTANT_P (XEXP (*p
, 1)))
1917 /* Otherwise, check each summand for containing a constant term. */
1919 if (XEXP (*p
, 0) != 0)
1921 tem
= find_constant_term_loc (&XEXP (*p
, 0));
1926 if (XEXP (*p
, 1) != 0)
1928 tem
= find_constant_term_loc (&XEXP (*p
, 1));
1936 /* Return 1 if OP is a memory reference
1937 whose address contains no side effects
1938 and remains valid after the addition
1939 of a positive integer less than the
1940 size of the object being referenced.
1942 We assume that the original address is valid and do not check it.
1944 This uses strict_memory_address_p as a subroutine, so
1945 don't use it before reload. */
1948 offsettable_memref_p (rtx op
)
1950 return ((MEM_P (op
))
1951 && offsettable_address_addr_space_p (1, GET_MODE (op
), XEXP (op
, 0),
1952 MEM_ADDR_SPACE (op
)));
1955 /* Similar, but don't require a strictly valid mem ref:
1956 consider pseudo-regs valid as index or base regs. */
1959 offsettable_nonstrict_memref_p (rtx op
)
1961 return ((MEM_P (op
))
1962 && offsettable_address_addr_space_p (0, GET_MODE (op
), XEXP (op
, 0),
1963 MEM_ADDR_SPACE (op
)));
1966 /* Return 1 if Y is a memory address which contains no side effects
1967 and would remain valid for address space AS after the addition of
1968 a positive integer less than the size of that mode.
1970 We assume that the original address is valid and do not check it.
1971 We do check that it is valid for narrower modes.
1973 If STRICTP is nonzero, we require a strictly valid address,
1974 for the sake of use in reload.c. */
1977 offsettable_address_addr_space_p (int strictp
, machine_mode mode
, rtx y
,
1980 enum rtx_code ycode
= GET_CODE (y
);
1984 int (*addressp
) (machine_mode
, rtx
, addr_space_t
) =
1985 (strictp
? strict_memory_address_addr_space_p
1986 : memory_address_addr_space_p
);
1987 unsigned int mode_sz
= GET_MODE_SIZE (mode
);
1989 if (CONSTANT_ADDRESS_P (y
))
1992 /* Adjusting an offsettable address involves changing to a narrower mode.
1993 Make sure that's OK. */
1995 if (mode_dependent_address_p (y
, as
))
1998 machine_mode address_mode
= GET_MODE (y
);
1999 if (address_mode
== VOIDmode
)
2000 address_mode
= targetm
.addr_space
.address_mode (as
);
2001 #ifdef POINTERS_EXTEND_UNSIGNED
2002 machine_mode pointer_mode
= targetm
.addr_space
.pointer_mode (as
);
2005 /* ??? How much offset does an offsettable BLKmode reference need?
2006 Clearly that depends on the situation in which it's being used.
2007 However, the current situation in which we test 0xffffffff is
2008 less than ideal. Caveat user. */
2010 mode_sz
= BIGGEST_ALIGNMENT
/ BITS_PER_UNIT
;
2012 /* If the expression contains a constant term,
2013 see if it remains valid when max possible offset is added. */
2015 if ((ycode
== PLUS
) && (y2
= find_constant_term_loc (&y1
)))
2020 *y2
= plus_constant (address_mode
, *y2
, mode_sz
- 1);
2021 /* Use QImode because an odd displacement may be automatically invalid
2022 for any wider mode. But it should be valid for a single byte. */
2023 good
= (*addressp
) (QImode
, y
, as
);
2025 /* In any case, restore old contents of memory. */
2030 if (GET_RTX_CLASS (ycode
) == RTX_AUTOINC
)
2033 /* The offset added here is chosen as the maximum offset that
2034 any instruction could need to add when operating on something
2035 of the specified mode. We assume that if Y and Y+c are
2036 valid addresses then so is Y+d for all 0<d<c. adjust_address will
2037 go inside a LO_SUM here, so we do so as well. */
2038 if (GET_CODE (y
) == LO_SUM
2040 && mode_sz
<= GET_MODE_ALIGNMENT (mode
) / BITS_PER_UNIT
)
2041 z
= gen_rtx_LO_SUM (address_mode
, XEXP (y
, 0),
2042 plus_constant (address_mode
, XEXP (y
, 1),
2044 #ifdef POINTERS_EXTEND_UNSIGNED
2045 /* Likewise for a ZERO_EXTEND from pointer_mode. */
2046 else if (POINTERS_EXTEND_UNSIGNED
> 0
2047 && GET_CODE (y
) == ZERO_EXTEND
2048 && GET_MODE (XEXP (y
, 0)) == pointer_mode
)
2049 z
= gen_rtx_ZERO_EXTEND (address_mode
,
2050 plus_constant (pointer_mode
, XEXP (y
, 0),
2054 z
= plus_constant (address_mode
, y
, mode_sz
- 1);
2056 /* Use QImode because an odd displacement may be automatically invalid
2057 for any wider mode. But it should be valid for a single byte. */
2058 return (*addressp
) (QImode
, z
, as
);
2061 /* Return 1 if ADDR is an address-expression whose effect depends
2062 on the mode of the memory reference it is used in.
2064 ADDRSPACE is the address space associated with the address.
2066 Autoincrement addressing is a typical example of mode-dependence
2067 because the amount of the increment depends on the mode. */
2070 mode_dependent_address_p (rtx addr
, addr_space_t addrspace
)
2072 /* Auto-increment addressing with anything other than post_modify
2073 or pre_modify always introduces a mode dependency. Catch such
2074 cases now instead of deferring to the target. */
2075 if (GET_CODE (addr
) == PRE_INC
2076 || GET_CODE (addr
) == POST_INC
2077 || GET_CODE (addr
) == PRE_DEC
2078 || GET_CODE (addr
) == POST_DEC
)
2081 return targetm
.mode_dependent_address_p (addr
, addrspace
);
2084 /* Return true if boolean attribute ATTR is supported. */
2087 have_bool_attr (bool_attr attr
)
2092 return HAVE_ATTR_enabled
;
2093 case BA_PREFERRED_FOR_SIZE
:
2094 return HAVE_ATTR_enabled
|| HAVE_ATTR_preferred_for_size
;
2095 case BA_PREFERRED_FOR_SPEED
:
2096 return HAVE_ATTR_enabled
|| HAVE_ATTR_preferred_for_speed
;
2101 /* Return the value of ATTR for instruction INSN. */
2104 get_bool_attr (rtx_insn
*insn
, bool_attr attr
)
2109 return get_attr_enabled (insn
);
2110 case BA_PREFERRED_FOR_SIZE
:
2111 return get_attr_enabled (insn
) && get_attr_preferred_for_size (insn
);
2112 case BA_PREFERRED_FOR_SPEED
:
2113 return get_attr_enabled (insn
) && get_attr_preferred_for_speed (insn
);
2118 /* Like get_bool_attr_mask, but don't use the cache. */
2120 static alternative_mask
2121 get_bool_attr_mask_uncached (rtx_insn
*insn
, bool_attr attr
)
2123 /* Temporarily install enough information for get_attr_<foo> to assume
2124 that the insn operands are already cached. As above, the attribute
2125 mustn't depend on the values of operands, so we don't provide their
2126 real values here. */
2127 rtx old_insn
= recog_data
.insn
;
2128 int old_alternative
= which_alternative
;
2130 recog_data
.insn
= insn
;
2131 alternative_mask mask
= ALL_ALTERNATIVES
;
2132 int n_alternatives
= insn_data
[INSN_CODE (insn
)].n_alternatives
;
2133 for (int i
= 0; i
< n_alternatives
; i
++)
2135 which_alternative
= i
;
2136 if (!get_bool_attr (insn
, attr
))
2137 mask
&= ~ALTERNATIVE_BIT (i
);
2140 recog_data
.insn
= old_insn
;
2141 which_alternative
= old_alternative
;
2145 /* Return the mask of operand alternatives that are allowed for INSN
2146 by boolean attribute ATTR. This mask depends only on INSN and on
2147 the current target; it does not depend on things like the values of
2150 static alternative_mask
2151 get_bool_attr_mask (rtx_insn
*insn
, bool_attr attr
)
2153 /* Quick exit for asms and for targets that don't use these attributes. */
2154 int code
= INSN_CODE (insn
);
2155 if (code
< 0 || !have_bool_attr (attr
))
2156 return ALL_ALTERNATIVES
;
2158 /* Calling get_attr_<foo> can be expensive, so cache the mask
2160 if (!this_target_recog
->x_bool_attr_masks
[code
][attr
])
2161 this_target_recog
->x_bool_attr_masks
[code
][attr
]
2162 = get_bool_attr_mask_uncached (insn
, attr
);
2163 return this_target_recog
->x_bool_attr_masks
[code
][attr
];
2166 /* Return the set of alternatives of INSN that are allowed by the current
2170 get_enabled_alternatives (rtx_insn
*insn
)
2172 return get_bool_attr_mask (insn
, BA_ENABLED
);
2175 /* Return the set of alternatives of INSN that are allowed by the current
2176 target and are preferred for the current size/speed optimization
2180 get_preferred_alternatives (rtx_insn
*insn
)
2182 if (optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn
)))
2183 return get_bool_attr_mask (insn
, BA_PREFERRED_FOR_SPEED
);
2185 return get_bool_attr_mask (insn
, BA_PREFERRED_FOR_SIZE
);
2188 /* Return the set of alternatives of INSN that are allowed by the current
2189 target and are preferred for the size/speed optimization choice
2190 associated with BB. Passing a separate BB is useful if INSN has not
2191 been emitted yet or if we are considering moving it to a different
2195 get_preferred_alternatives (rtx_insn
*insn
, basic_block bb
)
2197 if (optimize_bb_for_speed_p (bb
))
2198 return get_bool_attr_mask (insn
, BA_PREFERRED_FOR_SPEED
);
2200 return get_bool_attr_mask (insn
, BA_PREFERRED_FOR_SIZE
);
2203 /* Assert that the cached boolean attributes for INSN are still accurate.
2204 The backend is required to define these attributes in a way that only
2205 depends on the current target (rather than operands, compiler phase,
2209 check_bool_attrs (rtx_insn
*insn
)
2211 int code
= INSN_CODE (insn
);
2213 for (int i
= 0; i
<= BA_LAST
; ++i
)
2215 enum bool_attr attr
= (enum bool_attr
) i
;
2216 if (this_target_recog
->x_bool_attr_masks
[code
][attr
])
2217 gcc_assert (this_target_recog
->x_bool_attr_masks
[code
][attr
]
2218 == get_bool_attr_mask_uncached (insn
, attr
));
2223 /* Like extract_insn, but save insn extracted and don't extract again, when
2224 called again for the same insn expecting that recog_data still contain the
2225 valid information. This is used primary by gen_attr infrastructure that
2226 often does extract insn again and again. */
2228 extract_insn_cached (rtx_insn
*insn
)
2230 if (recog_data
.insn
== insn
&& INSN_CODE (insn
) >= 0)
2232 extract_insn (insn
);
2233 recog_data
.insn
= insn
;
2236 /* Do uncached extract_insn, constrain_operands and complain about failures.
2237 This should be used when extracting a pre-existing constrained instruction
2238 if the caller wants to know which alternative was chosen. */
2240 extract_constrain_insn (rtx_insn
*insn
)
2242 extract_insn (insn
);
2243 if (!constrain_operands (reload_completed
, get_enabled_alternatives (insn
)))
2244 fatal_insn_not_found (insn
);
2247 /* Do cached extract_insn, constrain_operands and complain about failures.
2248 Used by insn_attrtab. */
2250 extract_constrain_insn_cached (rtx_insn
*insn
)
2252 extract_insn_cached (insn
);
2253 if (which_alternative
== -1
2254 && !constrain_operands (reload_completed
,
2255 get_enabled_alternatives (insn
)))
2256 fatal_insn_not_found (insn
);
2259 /* Do cached constrain_operands on INSN and complain about failures. */
2261 constrain_operands_cached (rtx_insn
*insn
, int strict
)
2263 if (which_alternative
== -1)
2264 return constrain_operands (strict
, get_enabled_alternatives (insn
));
2269 /* Analyze INSN and fill in recog_data. */
2272 extract_insn (rtx_insn
*insn
)
2277 rtx body
= PATTERN (insn
);
2279 recog_data
.n_operands
= 0;
2280 recog_data
.n_alternatives
= 0;
2281 recog_data
.n_dups
= 0;
2282 recog_data
.is_asm
= false;
2284 switch (GET_CODE (body
))
2295 if (GET_CODE (SET_SRC (body
)) == ASM_OPERANDS
)
2300 if ((GET_CODE (XVECEXP (body
, 0, 0)) == SET
2301 && GET_CODE (SET_SRC (XVECEXP (body
, 0, 0))) == ASM_OPERANDS
)
2302 || GET_CODE (XVECEXP (body
, 0, 0)) == ASM_OPERANDS
)
2308 recog_data
.n_operands
= noperands
= asm_noperands (body
);
2311 /* This insn is an `asm' with operands. */
2313 /* expand_asm_operands makes sure there aren't too many operands. */
2314 gcc_assert (noperands
<= MAX_RECOG_OPERANDS
);
2316 /* Now get the operand values and constraints out of the insn. */
2317 decode_asm_operands (body
, recog_data
.operand
,
2318 recog_data
.operand_loc
,
2319 recog_data
.constraints
,
2320 recog_data
.operand_mode
, NULL
);
2321 memset (recog_data
.is_operator
, 0, sizeof recog_data
.is_operator
);
2324 const char *p
= recog_data
.constraints
[0];
2325 recog_data
.n_alternatives
= 1;
2327 recog_data
.n_alternatives
+= (*p
++ == ',');
2329 recog_data
.is_asm
= true;
2332 fatal_insn_not_found (insn
);
2336 /* Ordinary insn: recognize it, get the operands via insn_extract
2337 and get the constraints. */
2339 icode
= recog_memoized (insn
);
2341 fatal_insn_not_found (insn
);
2343 recog_data
.n_operands
= noperands
= insn_data
[icode
].n_operands
;
2344 recog_data
.n_alternatives
= insn_data
[icode
].n_alternatives
;
2345 recog_data
.n_dups
= insn_data
[icode
].n_dups
;
2347 insn_extract (insn
);
2349 for (i
= 0; i
< noperands
; i
++)
2351 recog_data
.constraints
[i
] = insn_data
[icode
].operand
[i
].constraint
;
2352 recog_data
.is_operator
[i
] = insn_data
[icode
].operand
[i
].is_operator
;
2353 recog_data
.operand_mode
[i
] = insn_data
[icode
].operand
[i
].mode
;
2354 /* VOIDmode match_operands gets mode from their real operand. */
2355 if (recog_data
.operand_mode
[i
] == VOIDmode
)
2356 recog_data
.operand_mode
[i
] = GET_MODE (recog_data
.operand
[i
]);
2359 for (i
= 0; i
< noperands
; i
++)
2360 recog_data
.operand_type
[i
]
2361 = (recog_data
.constraints
[i
][0] == '=' ? OP_OUT
2362 : recog_data
.constraints
[i
][0] == '+' ? OP_INOUT
2365 gcc_assert (recog_data
.n_alternatives
<= MAX_RECOG_ALTERNATIVES
);
2367 recog_data
.insn
= NULL
;
2368 which_alternative
= -1;
2371 /* Fill in OP_ALT_BASE for an instruction that has N_OPERANDS operands,
2372 N_ALTERNATIVES alternatives and constraint strings CONSTRAINTS.
2373 OP_ALT_BASE has N_ALTERNATIVES * N_OPERANDS entries and CONSTRAINTS
2374 has N_OPERANDS entries. */
2377 preprocess_constraints (int n_operands
, int n_alternatives
,
2378 const char **constraints
,
2379 operand_alternative
*op_alt_base
)
2381 for (int i
= 0; i
< n_operands
; i
++)
2384 struct operand_alternative
*op_alt
;
2385 const char *p
= constraints
[i
];
2387 op_alt
= op_alt_base
;
2389 for (j
= 0; j
< n_alternatives
; j
++, op_alt
+= n_operands
)
2391 op_alt
[i
].cl
= NO_REGS
;
2392 op_alt
[i
].constraint
= p
;
2393 op_alt
[i
].matches
= -1;
2394 op_alt
[i
].matched
= -1;
2396 if (*p
== '\0' || *p
== ',')
2398 op_alt
[i
].anything_ok
= 1;
2408 while (c
!= ',' && c
!= '\0');
2409 if (c
== ',' || c
== '\0')
2418 op_alt
[i
].reject
+= 6;
2421 op_alt
[i
].reject
+= 600;
2424 op_alt
[i
].earlyclobber
= 1;
2427 case '0': case '1': case '2': case '3': case '4':
2428 case '5': case '6': case '7': case '8': case '9':
2431 op_alt
[i
].matches
= strtoul (p
, &end
, 10);
2432 op_alt
[op_alt
[i
].matches
].matched
= i
;
2438 op_alt
[i
].anything_ok
= 1;
2443 reg_class_subunion
[(int) op_alt
[i
].cl
][(int) GENERAL_REGS
];
2447 enum constraint_num cn
= lookup_constraint (p
);
2449 switch (get_constraint_type (cn
))
2452 cl
= reg_class_for_constraint (cn
);
2454 op_alt
[i
].cl
= reg_class_subunion
[op_alt
[i
].cl
][cl
];
2461 op_alt
[i
].memory_ok
= 1;
2465 op_alt
[i
].is_address
= 1;
2467 = (reg_class_subunion
2468 [(int) op_alt
[i
].cl
]
2469 [(int) base_reg_class (VOIDmode
, ADDR_SPACE_GENERIC
,
2470 ADDRESS
, SCRATCH
)]);
2478 p
+= CONSTRAINT_LEN (c
, p
);
2484 /* Return an array of operand_alternative instructions for
2485 instruction ICODE. */
2487 const operand_alternative
*
2488 preprocess_insn_constraints (int icode
)
2490 gcc_checking_assert (IN_RANGE (icode
, 0, LAST_INSN_CODE
));
2491 if (this_target_recog
->x_op_alt
[icode
])
2492 return this_target_recog
->x_op_alt
[icode
];
2494 int n_operands
= insn_data
[icode
].n_operands
;
2495 if (n_operands
== 0)
2497 /* Always provide at least one alternative so that which_op_alt ()
2498 works correctly. If the instruction has 0 alternatives (i.e. all
2499 constraint strings are empty) then each operand in this alternative
2500 will have anything_ok set. */
2501 int n_alternatives
= MAX (insn_data
[icode
].n_alternatives
, 1);
2502 int n_entries
= n_operands
* n_alternatives
;
2504 operand_alternative
*op_alt
= XCNEWVEC (operand_alternative
, n_entries
);
2505 const char **constraints
= XALLOCAVEC (const char *, n_operands
);
2507 for (int i
= 0; i
< n_operands
; ++i
)
2508 constraints
[i
] = insn_data
[icode
].operand
[i
].constraint
;
2509 preprocess_constraints (n_operands
, n_alternatives
, constraints
, op_alt
);
2511 this_target_recog
->x_op_alt
[icode
] = op_alt
;
2515 /* After calling extract_insn, you can use this function to extract some
2516 information from the constraint strings into a more usable form.
2517 The collected data is stored in recog_op_alt. */
2520 preprocess_constraints (rtx insn
)
2522 int icode
= INSN_CODE (insn
);
2524 recog_op_alt
= preprocess_insn_constraints (icode
);
2527 int n_operands
= recog_data
.n_operands
;
2528 int n_alternatives
= recog_data
.n_alternatives
;
2529 int n_entries
= n_operands
* n_alternatives
;
2530 memset (asm_op_alt
, 0, n_entries
* sizeof (operand_alternative
));
2531 preprocess_constraints (n_operands
, n_alternatives
,
2532 recog_data
.constraints
, asm_op_alt
);
2533 recog_op_alt
= asm_op_alt
;
2537 /* Check the operands of an insn against the insn's operand constraints
2538 and return 1 if they match any of the alternatives in ALTERNATIVES.
2540 The information about the insn's operands, constraints, operand modes
2541 etc. is obtained from the global variables set up by extract_insn.
2543 WHICH_ALTERNATIVE is set to a number which indicates which
2544 alternative of constraints was matched: 0 for the first alternative,
2545 1 for the next, etc.
2547 In addition, when two operands are required to match
2548 and it happens that the output operand is (reg) while the
2549 input operand is --(reg) or ++(reg) (a pre-inc or pre-dec),
2550 make the output operand look like the input.
2551 This is because the output operand is the one the template will print.
2553 This is used in final, just before printing the assembler code and by
2554 the routines that determine an insn's attribute.
2556 If STRICT is a positive nonzero value, it means that we have been
2557 called after reload has been completed. In that case, we must
2558 do all checks strictly. If it is zero, it means that we have been called
2559 before reload has completed. In that case, we first try to see if we can
2560 find an alternative that matches strictly. If not, we try again, this
2561 time assuming that reload will fix up the insn. This provides a "best
2562 guess" for the alternative and is used to compute attributes of insns prior
2563 to reload. A negative value of STRICT is used for this internal call. */
2571 constrain_operands (int strict
, alternative_mask alternatives
)
2573 const char *constraints
[MAX_RECOG_OPERANDS
];
2574 int matching_operands
[MAX_RECOG_OPERANDS
];
2575 int earlyclobber
[MAX_RECOG_OPERANDS
];
2578 struct funny_match funny_match
[MAX_RECOG_OPERANDS
];
2579 int funny_match_index
;
2581 which_alternative
= 0;
2582 if (recog_data
.n_operands
== 0 || recog_data
.n_alternatives
== 0)
2585 for (c
= 0; c
< recog_data
.n_operands
; c
++)
2587 constraints
[c
] = recog_data
.constraints
[c
];
2588 matching_operands
[c
] = -1;
2593 int seen_earlyclobber_at
= -1;
2596 funny_match_index
= 0;
2598 if (!TEST_BIT (alternatives
, which_alternative
))
2602 for (i
= 0; i
< recog_data
.n_operands
; i
++)
2603 constraints
[i
] = skip_alternative (constraints
[i
]);
2605 which_alternative
++;
2609 for (opno
= 0; opno
< recog_data
.n_operands
; opno
++)
2611 rtx op
= recog_data
.operand
[opno
];
2612 machine_mode mode
= GET_MODE (op
);
2613 const char *p
= constraints
[opno
];
2619 earlyclobber
[opno
] = 0;
2621 /* A unary operator may be accepted by the predicate, but it
2622 is irrelevant for matching constraints. */
2626 if (GET_CODE (op
) == SUBREG
)
2628 if (REG_P (SUBREG_REG (op
))
2629 && REGNO (SUBREG_REG (op
)) < FIRST_PSEUDO_REGISTER
)
2630 offset
= subreg_regno_offset (REGNO (SUBREG_REG (op
)),
2631 GET_MODE (SUBREG_REG (op
)),
2634 op
= SUBREG_REG (op
);
2637 /* An empty constraint or empty alternative
2638 allows anything which matched the pattern. */
2639 if (*p
== 0 || *p
== ',')
2643 switch (c
= *p
, len
= CONSTRAINT_LEN (c
, p
), c
)
2653 /* Ignore rest of this alternative as far as
2654 constraint checking is concerned. */
2657 while (*p
&& *p
!= ',');
2662 earlyclobber
[opno
] = 1;
2663 if (seen_earlyclobber_at
< 0)
2664 seen_earlyclobber_at
= opno
;
2667 case '0': case '1': case '2': case '3': case '4':
2668 case '5': case '6': case '7': case '8': case '9':
2670 /* This operand must be the same as a previous one.
2671 This kind of constraint is used for instructions such
2672 as add when they take only two operands.
2674 Note that the lower-numbered operand is passed first.
2676 If we are not testing strictly, assume that this
2677 constraint will be satisfied. */
2682 match
= strtoul (p
, &end
, 10);
2689 rtx op1
= recog_data
.operand
[match
];
2690 rtx op2
= recog_data
.operand
[opno
];
2692 /* A unary operator may be accepted by the predicate,
2693 but it is irrelevant for matching constraints. */
2695 op1
= XEXP (op1
, 0);
2697 op2
= XEXP (op2
, 0);
2699 val
= operands_match_p (op1
, op2
);
2702 matching_operands
[opno
] = match
;
2703 matching_operands
[match
] = opno
;
2708 /* If output is *x and input is *--x, arrange later
2709 to change the output to *--x as well, since the
2710 output op is the one that will be printed. */
2711 if (val
== 2 && strict
> 0)
2713 funny_match
[funny_match_index
].this_op
= opno
;
2714 funny_match
[funny_match_index
++].other
= match
;
2721 /* p is used for address_operands. When we are called by
2722 gen_reload, no one will have checked that the address is
2723 strictly valid, i.e., that all pseudos requiring hard regs
2724 have gotten them. */
2726 || (strict_memory_address_p (recog_data
.operand_mode
[opno
],
2731 /* No need to check general_operand again;
2732 it was done in insn-recog.c. Well, except that reload
2733 doesn't check the validity of its replacements, but
2734 that should only matter when there's a bug. */
2736 /* Anything goes unless it is a REG and really has a hard reg
2737 but the hard reg is not in the class GENERAL_REGS. */
2741 || GENERAL_REGS
== ALL_REGS
2742 || (reload_in_progress
2743 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
)
2744 || reg_fits_class_p (op
, GENERAL_REGS
, offset
, mode
))
2747 else if (strict
< 0 || general_operand (op
, mode
))
2753 enum constraint_num cn
= lookup_constraint (p
);
2754 enum reg_class cl
= reg_class_for_constraint (cn
);
2760 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
)
2761 || (strict
== 0 && GET_CODE (op
) == SCRATCH
)
2763 && reg_fits_class_p (op
, cl
, offset
, mode
)))
2767 else if (constraint_satisfied_p (op
, cn
))
2770 else if (insn_extra_memory_constraint (cn
)
2771 /* Every memory operand can be reloaded to fit. */
2772 && ((strict
< 0 && MEM_P (op
))
2773 /* Before reload, accept what reload can turn
2775 || (strict
< 0 && CONSTANT_P (op
))
2776 /* Before reload, accept a pseudo,
2777 since LRA can turn it into a mem. */
2778 || (strict
< 0 && targetm
.lra_p () && REG_P (op
)
2779 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
)
2780 /* During reload, accept a pseudo */
2781 || (reload_in_progress
&& REG_P (op
)
2782 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
)))
2784 else if (insn_extra_address_constraint (cn
)
2785 /* Every address operand can be reloaded to fit. */
2788 /* Cater to architectures like IA-64 that define extra memory
2789 constraints without using define_memory_constraint. */
2790 else if (reload_in_progress
2792 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
2793 && reg_renumber
[REGNO (op
)] < 0
2794 && reg_equiv_mem (REGNO (op
)) != 0
2795 && constraint_satisfied_p
2796 (reg_equiv_mem (REGNO (op
)), cn
))
2801 while (p
+= len
, c
);
2803 constraints
[opno
] = p
;
2804 /* If this operand did not win somehow,
2805 this alternative loses. */
2809 /* This alternative won; the operands are ok.
2810 Change whichever operands this alternative says to change. */
2815 /* See if any earlyclobber operand conflicts with some other
2818 if (strict
> 0 && seen_earlyclobber_at
>= 0)
2819 for (eopno
= seen_earlyclobber_at
;
2820 eopno
< recog_data
.n_operands
;
2822 /* Ignore earlyclobber operands now in memory,
2823 because we would often report failure when we have
2824 two memory operands, one of which was formerly a REG. */
2825 if (earlyclobber
[eopno
]
2826 && REG_P (recog_data
.operand
[eopno
]))
2827 for (opno
= 0; opno
< recog_data
.n_operands
; opno
++)
2828 if ((MEM_P (recog_data
.operand
[opno
])
2829 || recog_data
.operand_type
[opno
] != OP_OUT
)
2831 /* Ignore things like match_operator operands. */
2832 && *recog_data
.constraints
[opno
] != 0
2833 && ! (matching_operands
[opno
] == eopno
2834 && operands_match_p (recog_data
.operand
[opno
],
2835 recog_data
.operand
[eopno
]))
2836 && ! safe_from_earlyclobber (recog_data
.operand
[opno
],
2837 recog_data
.operand
[eopno
]))
2842 while (--funny_match_index
>= 0)
2844 recog_data
.operand
[funny_match
[funny_match_index
].other
]
2845 = recog_data
.operand
[funny_match
[funny_match_index
].this_op
];
2849 /* For operands without < or > constraints reject side-effects. */
2850 if (recog_data
.is_asm
)
2852 for (opno
= 0; opno
< recog_data
.n_operands
; opno
++)
2853 if (MEM_P (recog_data
.operand
[opno
]))
2854 switch (GET_CODE (XEXP (recog_data
.operand
[opno
], 0)))
2862 if (strchr (recog_data
.constraints
[opno
], '<') == NULL
2863 && strchr (recog_data
.constraints
[opno
], '>')
2876 which_alternative
++;
2878 while (which_alternative
< recog_data
.n_alternatives
);
2880 which_alternative
= -1;
2881 /* If we are about to reject this, but we are not to test strictly,
2882 try a very loose test. Only return failure if it fails also. */
2884 return constrain_operands (-1, alternatives
);
2889 /* Return true iff OPERAND (assumed to be a REG rtx)
2890 is a hard reg in class CLASS when its regno is offset by OFFSET
2891 and changed to mode MODE.
2892 If REG occupies multiple hard regs, all of them must be in CLASS. */
2895 reg_fits_class_p (const_rtx operand
, reg_class_t cl
, int offset
,
2898 unsigned int regno
= REGNO (operand
);
2903 /* Regno must not be a pseudo register. Offset may be negative. */
2904 return (HARD_REGISTER_NUM_P (regno
)
2905 && HARD_REGISTER_NUM_P (regno
+ offset
)
2906 && in_hard_reg_set_p (reg_class_contents
[(int) cl
], mode
,
2910 /* Split single instruction. Helper function for split_all_insns and
2911 split_all_insns_noflow. Return last insn in the sequence if successful,
2912 or NULL if unsuccessful. */
2915 split_insn (rtx_insn
*insn
)
2917 /* Split insns here to get max fine-grain parallelism. */
2918 rtx_insn
*first
= PREV_INSN (insn
);
2919 rtx_insn
*last
= try_split (PATTERN (insn
), insn
, 1);
2920 rtx insn_set
, last_set
, note
;
2925 /* If the original instruction was a single set that was known to be
2926 equivalent to a constant, see if we can say the same about the last
2927 instruction in the split sequence. The two instructions must set
2928 the same destination. */
2929 insn_set
= single_set (insn
);
2932 last_set
= single_set (last
);
2933 if (last_set
&& rtx_equal_p (SET_DEST (last_set
), SET_DEST (insn_set
)))
2935 note
= find_reg_equal_equiv_note (insn
);
2936 if (note
&& CONSTANT_P (XEXP (note
, 0)))
2937 set_unique_reg_note (last
, REG_EQUAL
, XEXP (note
, 0));
2938 else if (CONSTANT_P (SET_SRC (insn_set
)))
2939 set_unique_reg_note (last
, REG_EQUAL
,
2940 copy_rtx (SET_SRC (insn_set
)));
2944 /* try_split returns the NOTE that INSN became. */
2945 SET_INSN_DELETED (insn
);
2947 /* ??? Coddle to md files that generate subregs in post-reload
2948 splitters instead of computing the proper hard register. */
2949 if (reload_completed
&& first
!= last
)
2951 first
= NEXT_INSN (first
);
2955 cleanup_subreg_operands (first
);
2958 first
= NEXT_INSN (first
);
2965 /* Split all insns in the function. If UPD_LIFE, update life info after. */
2968 split_all_insns (void)
2974 blocks
= sbitmap_alloc (last_basic_block_for_fn (cfun
));
2975 bitmap_clear (blocks
);
2978 FOR_EACH_BB_REVERSE_FN (bb
, cfun
)
2980 rtx_insn
*insn
, *next
;
2981 bool finish
= false;
2983 rtl_profile_for_bb (bb
);
2984 for (insn
= BB_HEAD (bb
); !finish
; insn
= next
)
2986 /* Can't use `next_real_insn' because that might go across
2987 CODE_LABELS and short-out basic blocks. */
2988 next
= NEXT_INSN (insn
);
2989 finish
= (insn
== BB_END (bb
));
2992 rtx set
= single_set (insn
);
2994 /* Don't split no-op move insns. These should silently
2995 disappear later in final. Splitting such insns would
2996 break the code that handles LIBCALL blocks. */
2997 if (set
&& set_noop_p (set
))
2999 /* Nops get in the way while scheduling, so delete them
3000 now if register allocation has already been done. It
3001 is too risky to try to do this before register
3002 allocation, and there are unlikely to be very many
3003 nops then anyways. */
3004 if (reload_completed
)
3005 delete_insn_and_edges (insn
);
3009 if (split_insn (insn
))
3011 bitmap_set_bit (blocks
, bb
->index
);
3019 default_rtl_profile ();
3021 find_many_sub_basic_blocks (blocks
);
3023 #ifdef ENABLE_CHECKING
3024 verify_flow_info ();
3027 sbitmap_free (blocks
);
3030 /* Same as split_all_insns, but do not expect CFG to be available.
3031 Used by machine dependent reorg passes. */
3034 split_all_insns_noflow (void)
3036 rtx_insn
*next
, *insn
;
3038 for (insn
= get_insns (); insn
; insn
= next
)
3040 next
= NEXT_INSN (insn
);
3043 /* Don't split no-op move insns. These should silently
3044 disappear later in final. Splitting such insns would
3045 break the code that handles LIBCALL blocks. */
3046 rtx set
= single_set (insn
);
3047 if (set
&& set_noop_p (set
))
3049 /* Nops get in the way while scheduling, so delete them
3050 now if register allocation has already been done. It
3051 is too risky to try to do this before register
3052 allocation, and there are unlikely to be very many
3055 ??? Should we use delete_insn when the CFG isn't valid? */
3056 if (reload_completed
)
3057 delete_insn_and_edges (insn
);
3066 #ifdef HAVE_peephole2
3067 struct peep2_insn_data
3073 static struct peep2_insn_data peep2_insn_data
[MAX_INSNS_PER_PEEP2
+ 1];
3074 static int peep2_current
;
3076 static bool peep2_do_rebuild_jump_labels
;
3077 static bool peep2_do_cleanup_cfg
;
3079 /* The number of instructions available to match a peep2. */
3080 int peep2_current_count
;
3082 /* A non-insn marker indicating the last insn of the block.
3083 The live_before regset for this element is correct, indicating
3084 DF_LIVE_OUT for the block. */
3085 #define PEEP2_EOB pc_rtx
3087 /* Wrap N to fit into the peep2_insn_data buffer. */
3090 peep2_buf_position (int n
)
3092 if (n
>= MAX_INSNS_PER_PEEP2
+ 1)
3093 n
-= MAX_INSNS_PER_PEEP2
+ 1;
3097 /* Return the Nth non-note insn after `current', or return NULL_RTX if it
3098 does not exist. Used by the recognizer to find the next insn to match
3099 in a multi-insn pattern. */
3102 peep2_next_insn (int n
)
3104 gcc_assert (n
<= peep2_current_count
);
3106 n
= peep2_buf_position (peep2_current
+ n
);
3108 return peep2_insn_data
[n
].insn
;
3111 /* Return true if REGNO is dead before the Nth non-note insn
3115 peep2_regno_dead_p (int ofs
, int regno
)
3117 gcc_assert (ofs
< MAX_INSNS_PER_PEEP2
+ 1);
3119 ofs
= peep2_buf_position (peep2_current
+ ofs
);
3121 gcc_assert (peep2_insn_data
[ofs
].insn
!= NULL_RTX
);
3123 return ! REGNO_REG_SET_P (peep2_insn_data
[ofs
].live_before
, regno
);
3126 /* Similarly for a REG. */
3129 peep2_reg_dead_p (int ofs
, rtx reg
)
3133 gcc_assert (ofs
< MAX_INSNS_PER_PEEP2
+ 1);
3135 ofs
= peep2_buf_position (peep2_current
+ ofs
);
3137 gcc_assert (peep2_insn_data
[ofs
].insn
!= NULL_RTX
);
3139 regno
= REGNO (reg
);
3140 n
= hard_regno_nregs
[regno
][GET_MODE (reg
)];
3142 if (REGNO_REG_SET_P (peep2_insn_data
[ofs
].live_before
, regno
+ n
))
3147 /* Regno offset to be used in the register search. */
3148 static int search_ofs
;
3150 /* Try to find a hard register of mode MODE, matching the register class in
3151 CLASS_STR, which is available at the beginning of insn CURRENT_INSN and
3152 remains available until the end of LAST_INSN. LAST_INSN may be NULL_RTX,
3153 in which case the only condition is that the register must be available
3154 before CURRENT_INSN.
3155 Registers that already have bits set in REG_SET will not be considered.
3157 If an appropriate register is available, it will be returned and the
3158 corresponding bit(s) in REG_SET will be set; otherwise, NULL_RTX is
3162 peep2_find_free_register (int from
, int to
, const char *class_str
,
3163 machine_mode mode
, HARD_REG_SET
*reg_set
)
3170 gcc_assert (from
< MAX_INSNS_PER_PEEP2
+ 1);
3171 gcc_assert (to
< MAX_INSNS_PER_PEEP2
+ 1);
3173 from
= peep2_buf_position (peep2_current
+ from
);
3174 to
= peep2_buf_position (peep2_current
+ to
);
3176 gcc_assert (peep2_insn_data
[from
].insn
!= NULL_RTX
);
3177 REG_SET_TO_HARD_REG_SET (live
, peep2_insn_data
[from
].live_before
);
3181 gcc_assert (peep2_insn_data
[from
].insn
!= NULL_RTX
);
3183 /* Don't use registers set or clobbered by the insn. */
3184 FOR_EACH_INSN_DEF (def
, peep2_insn_data
[from
].insn
)
3185 SET_HARD_REG_BIT (live
, DF_REF_REGNO (def
));
3187 from
= peep2_buf_position (from
+ 1);
3190 cl
= reg_class_for_constraint (lookup_constraint (class_str
));
3192 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
3194 int raw_regno
, regno
, success
, j
;
3196 /* Distribute the free registers as much as possible. */
3197 raw_regno
= search_ofs
+ i
;
3198 if (raw_regno
>= FIRST_PSEUDO_REGISTER
)
3199 raw_regno
-= FIRST_PSEUDO_REGISTER
;
3200 #ifdef REG_ALLOC_ORDER
3201 regno
= reg_alloc_order
[raw_regno
];
3206 /* Can it support the mode we need? */
3207 if (! HARD_REGNO_MODE_OK (regno
, mode
))
3211 for (j
= 0; success
&& j
< hard_regno_nregs
[regno
][mode
]; j
++)
3213 /* Don't allocate fixed registers. */
3214 if (fixed_regs
[regno
+ j
])
3219 /* Don't allocate global registers. */
3220 if (global_regs
[regno
+ j
])
3225 /* Make sure the register is of the right class. */
3226 if (! TEST_HARD_REG_BIT (reg_class_contents
[cl
], regno
+ j
))
3231 /* And that we don't create an extra save/restore. */
3232 if (! call_used_regs
[regno
+ j
] && ! df_regs_ever_live_p (regno
+ j
))
3238 if (! targetm
.hard_regno_scratch_ok (regno
+ j
))
3244 /* And we don't clobber traceback for noreturn functions. */
3245 if ((regno
+ j
== FRAME_POINTER_REGNUM
3246 || regno
+ j
== HARD_FRAME_POINTER_REGNUM
)
3247 && (! reload_completed
|| frame_pointer_needed
))
3253 if (TEST_HARD_REG_BIT (*reg_set
, regno
+ j
)
3254 || TEST_HARD_REG_BIT (live
, regno
+ j
))
3263 add_to_hard_reg_set (reg_set
, mode
, regno
);
3265 /* Start the next search with the next register. */
3266 if (++raw_regno
>= FIRST_PSEUDO_REGISTER
)
3268 search_ofs
= raw_regno
;
3270 return gen_rtx_REG (mode
, regno
);
3278 /* Forget all currently tracked instructions, only remember current
3282 peep2_reinit_state (regset live
)
3286 /* Indicate that all slots except the last holds invalid data. */
3287 for (i
= 0; i
< MAX_INSNS_PER_PEEP2
; ++i
)
3288 peep2_insn_data
[i
].insn
= NULL_RTX
;
3289 peep2_current_count
= 0;
3291 /* Indicate that the last slot contains live_after data. */
3292 peep2_insn_data
[MAX_INSNS_PER_PEEP2
].insn
= PEEP2_EOB
;
3293 peep2_current
= MAX_INSNS_PER_PEEP2
;
3295 COPY_REG_SET (peep2_insn_data
[MAX_INSNS_PER_PEEP2
].live_before
, live
);
3298 /* While scanning basic block BB, we found a match of length MATCH_LEN,
3299 starting at INSN. Perform the replacement, removing the old insns and
3300 replacing them with ATTEMPT. Returns the last insn emitted, or NULL
3301 if the replacement is rejected. */
3304 peep2_attempt (basic_block bb
, rtx uncast_insn
, int match_len
, rtx_insn
*attempt
)
3306 rtx_insn
*insn
= safe_as_a
<rtx_insn
*> (uncast_insn
);
3308 rtx_insn
*last
, *before_try
, *x
;
3309 rtx eh_note
, as_note
;
3312 bool was_call
= false;
3314 /* If we are splitting an RTX_FRAME_RELATED_P insn, do not allow it to
3315 match more than one insn, or to be split into more than one insn. */
3316 old_insn
= as_a
<rtx_insn
*> (peep2_insn_data
[peep2_current
].insn
);
3317 if (RTX_FRAME_RELATED_P (old_insn
))
3319 bool any_note
= false;
3325 /* Look for one "active" insn. I.e. ignore any "clobber" insns that
3326 may be in the stream for the purpose of register allocation. */
3327 if (active_insn_p (attempt
))
3330 new_insn
= next_active_insn (attempt
);
3331 if (next_active_insn (new_insn
))
3334 /* We have a 1-1 replacement. Copy over any frame-related info. */
3335 RTX_FRAME_RELATED_P (new_insn
) = 1;
3337 /* Allow the backend to fill in a note during the split. */
3338 for (note
= REG_NOTES (new_insn
); note
; note
= XEXP (note
, 1))
3339 switch (REG_NOTE_KIND (note
))
3341 case REG_FRAME_RELATED_EXPR
:
3342 case REG_CFA_DEF_CFA
:
3343 case REG_CFA_ADJUST_CFA
:
3344 case REG_CFA_OFFSET
:
3345 case REG_CFA_REGISTER
:
3346 case REG_CFA_EXPRESSION
:
3347 case REG_CFA_RESTORE
:
3348 case REG_CFA_SET_VDRAP
:
3355 /* If the backend didn't supply a note, copy one over. */
3357 for (note
= REG_NOTES (old_insn
); note
; note
= XEXP (note
, 1))
3358 switch (REG_NOTE_KIND (note
))
3360 case REG_FRAME_RELATED_EXPR
:
3361 case REG_CFA_DEF_CFA
:
3362 case REG_CFA_ADJUST_CFA
:
3363 case REG_CFA_OFFSET
:
3364 case REG_CFA_REGISTER
:
3365 case REG_CFA_EXPRESSION
:
3366 case REG_CFA_RESTORE
:
3367 case REG_CFA_SET_VDRAP
:
3368 add_reg_note (new_insn
, REG_NOTE_KIND (note
), XEXP (note
, 0));
3375 /* If there still isn't a note, make sure the unwind info sees the
3376 same expression as before the split. */
3379 rtx old_set
, new_set
;
3381 /* The old insn had better have been simple, or annotated. */
3382 old_set
= single_set (old_insn
);
3383 gcc_assert (old_set
!= NULL
);
3385 new_set
= single_set (new_insn
);
3386 if (!new_set
|| !rtx_equal_p (new_set
, old_set
))
3387 add_reg_note (new_insn
, REG_FRAME_RELATED_EXPR
, old_set
);
3390 /* Copy prologue/epilogue status. This is required in order to keep
3391 proper placement of EPILOGUE_BEG and the DW_CFA_remember_state. */
3392 maybe_copy_prologue_epilogue_insn (old_insn
, new_insn
);
3395 /* If we are splitting a CALL_INSN, look for the CALL_INSN
3396 in SEQ and copy our CALL_INSN_FUNCTION_USAGE and other
3397 cfg-related call notes. */
3398 for (i
= 0; i
<= match_len
; ++i
)
3403 j
= peep2_buf_position (peep2_current
+ i
);
3404 old_insn
= as_a
<rtx_insn
*> (peep2_insn_data
[j
].insn
);
3405 if (!CALL_P (old_insn
))
3410 while (new_insn
!= NULL_RTX
)
3412 if (CALL_P (new_insn
))
3414 new_insn
= NEXT_INSN (new_insn
);
3417 gcc_assert (new_insn
!= NULL_RTX
);
3419 CALL_INSN_FUNCTION_USAGE (new_insn
)
3420 = CALL_INSN_FUNCTION_USAGE (old_insn
);
3421 SIBLING_CALL_P (new_insn
) = SIBLING_CALL_P (old_insn
);
3423 for (note
= REG_NOTES (old_insn
);
3425 note
= XEXP (note
, 1))
3426 switch (REG_NOTE_KIND (note
))
3431 add_reg_note (new_insn
, REG_NOTE_KIND (note
),
3435 /* Discard all other reg notes. */
3439 /* Croak if there is another call in the sequence. */
3440 while (++i
<= match_len
)
3442 j
= peep2_buf_position (peep2_current
+ i
);
3443 old_insn
= as_a
<rtx_insn
*> (peep2_insn_data
[j
].insn
);
3444 gcc_assert (!CALL_P (old_insn
));
3449 /* If we matched any instruction that had a REG_ARGS_SIZE, then
3450 move those notes over to the new sequence. */
3452 for (i
= match_len
; i
>= 0; --i
)
3454 int j
= peep2_buf_position (peep2_current
+ i
);
3455 old_insn
= as_a
<rtx_insn
*> (peep2_insn_data
[j
].insn
);
3457 as_note
= find_reg_note (old_insn
, REG_ARGS_SIZE
, NULL
);
3462 i
= peep2_buf_position (peep2_current
+ match_len
);
3463 eh_note
= find_reg_note (peep2_insn_data
[i
].insn
, REG_EH_REGION
, NULL_RTX
);
3465 /* Replace the old sequence with the new. */
3466 rtx_insn
*peepinsn
= as_a
<rtx_insn
*> (peep2_insn_data
[i
].insn
);
3467 last
= emit_insn_after_setloc (attempt
,
3468 peep2_insn_data
[i
].insn
,
3469 INSN_LOCATION (peepinsn
));
3470 before_try
= PREV_INSN (insn
);
3471 delete_insn_chain (insn
, peep2_insn_data
[i
].insn
, false);
3473 /* Re-insert the EH_REGION notes. */
3474 if (eh_note
|| (was_call
&& nonlocal_goto_handler_labels
))
3479 FOR_EACH_EDGE (eh_edge
, ei
, bb
->succs
)
3480 if (eh_edge
->flags
& (EDGE_EH
| EDGE_ABNORMAL_CALL
))
3484 copy_reg_eh_region_note_backward (eh_note
, last
, before_try
);
3487 for (x
= last
; x
!= before_try
; x
= PREV_INSN (x
))
3488 if (x
!= BB_END (bb
)
3489 && (can_throw_internal (x
)
3490 || can_nonlocal_goto (x
)))
3495 nfte
= split_block (bb
, x
);
3496 flags
= (eh_edge
->flags
3497 & (EDGE_EH
| EDGE_ABNORMAL
));
3499 flags
|= EDGE_ABNORMAL_CALL
;
3500 nehe
= make_edge (nfte
->src
, eh_edge
->dest
,
3503 nehe
->probability
= eh_edge
->probability
;
3505 = REG_BR_PROB_BASE
- nehe
->probability
;
3507 peep2_do_cleanup_cfg
|= purge_dead_edges (nfte
->dest
);
3512 /* Converting possibly trapping insn to non-trapping is
3513 possible. Zap dummy outgoing edges. */
3514 peep2_do_cleanup_cfg
|= purge_dead_edges (bb
);
3517 /* Re-insert the ARGS_SIZE notes. */
3519 fixup_args_size_notes (before_try
, last
, INTVAL (XEXP (as_note
, 0)));
3521 /* If we generated a jump instruction, it won't have
3522 JUMP_LABEL set. Recompute after we're done. */
3523 for (x
= last
; x
!= before_try
; x
= PREV_INSN (x
))
3526 peep2_do_rebuild_jump_labels
= true;
3533 /* After performing a replacement in basic block BB, fix up the life
3534 information in our buffer. LAST is the last of the insns that we
3535 emitted as a replacement. PREV is the insn before the start of
3536 the replacement. MATCH_LEN is the number of instructions that were
3537 matched, and which now need to be replaced in the buffer. */
3540 peep2_update_life (basic_block bb
, int match_len
, rtx_insn
*last
,
3543 int i
= peep2_buf_position (peep2_current
+ match_len
+ 1);
3547 INIT_REG_SET (&live
);
3548 COPY_REG_SET (&live
, peep2_insn_data
[i
].live_before
);
3550 gcc_assert (peep2_current_count
>= match_len
+ 1);
3551 peep2_current_count
-= match_len
+ 1;
3559 if (peep2_current_count
< MAX_INSNS_PER_PEEP2
)
3561 peep2_current_count
++;
3563 i
= MAX_INSNS_PER_PEEP2
;
3564 peep2_insn_data
[i
].insn
= x
;
3565 df_simulate_one_insn_backwards (bb
, x
, &live
);
3566 COPY_REG_SET (peep2_insn_data
[i
].live_before
, &live
);
3572 CLEAR_REG_SET (&live
);
3577 /* Add INSN, which is in BB, at the end of the peep2 insn buffer if possible.
3578 Return true if we added it, false otherwise. The caller will try to match
3579 peepholes against the buffer if we return false; otherwise it will try to
3580 add more instructions to the buffer. */
3583 peep2_fill_buffer (basic_block bb
, rtx insn
, regset live
)
3587 /* Once we have filled the maximum number of insns the buffer can hold,
3588 allow the caller to match the insns against peepholes. We wait until
3589 the buffer is full in case the target has similar peepholes of different
3590 length; we always want to match the longest if possible. */
3591 if (peep2_current_count
== MAX_INSNS_PER_PEEP2
)
3594 /* If an insn has RTX_FRAME_RELATED_P set, do not allow it to be matched with
3595 any other pattern, lest it change the semantics of the frame info. */
3596 if (RTX_FRAME_RELATED_P (insn
))
3598 /* Let the buffer drain first. */
3599 if (peep2_current_count
> 0)
3601 /* Now the insn will be the only thing in the buffer. */
3604 pos
= peep2_buf_position (peep2_current
+ peep2_current_count
);
3605 peep2_insn_data
[pos
].insn
= insn
;
3606 COPY_REG_SET (peep2_insn_data
[pos
].live_before
, live
);
3607 peep2_current_count
++;
3609 df_simulate_one_insn_forwards (bb
, as_a
<rtx_insn
*> (insn
), live
);
3613 /* Perform the peephole2 optimization pass. */
3616 peephole2_optimize (void)
3623 peep2_do_cleanup_cfg
= false;
3624 peep2_do_rebuild_jump_labels
= false;
3626 df_set_flags (DF_LR_RUN_DCE
);
3627 df_note_add_problem ();
3630 /* Initialize the regsets we're going to use. */
3631 for (i
= 0; i
< MAX_INSNS_PER_PEEP2
+ 1; ++i
)
3632 peep2_insn_data
[i
].live_before
= BITMAP_ALLOC (®_obstack
);
3634 live
= BITMAP_ALLOC (®_obstack
);
3636 FOR_EACH_BB_REVERSE_FN (bb
, cfun
)
3638 bool past_end
= false;
3641 rtl_profile_for_bb (bb
);
3643 /* Start up propagation. */
3644 bitmap_copy (live
, DF_LR_IN (bb
));
3645 df_simulate_initialize_forwards (bb
, live
);
3646 peep2_reinit_state (live
);
3648 insn
= BB_HEAD (bb
);
3655 if (!past_end
&& !NONDEBUG_INSN_P (insn
))
3658 insn
= NEXT_INSN (insn
);
3659 if (insn
== NEXT_INSN (BB_END (bb
)))
3663 if (!past_end
&& peep2_fill_buffer (bb
, insn
, live
))
3666 /* If we did not fill an empty buffer, it signals the end of the
3668 if (peep2_current_count
== 0)
3671 /* The buffer filled to the current maximum, so try to match. */
3673 pos
= peep2_buf_position (peep2_current
+ peep2_current_count
);
3674 peep2_insn_data
[pos
].insn
= PEEP2_EOB
;
3675 COPY_REG_SET (peep2_insn_data
[pos
].live_before
, live
);
3677 /* Match the peephole. */
3678 head
= peep2_insn_data
[peep2_current
].insn
;
3679 attempt
= safe_as_a
<rtx_insn
*> (
3680 peephole2_insns (PATTERN (head
), head
, &match_len
));
3681 if (attempt
!= NULL
)
3683 rtx_insn
*last
= peep2_attempt (bb
, head
, match_len
, attempt
);
3686 peep2_update_life (bb
, match_len
, last
, PREV_INSN (attempt
));
3691 /* No match: advance the buffer by one insn. */
3692 peep2_current
= peep2_buf_position (peep2_current
+ 1);
3693 peep2_current_count
--;
3697 default_rtl_profile ();
3698 for (i
= 0; i
< MAX_INSNS_PER_PEEP2
+ 1; ++i
)
3699 BITMAP_FREE (peep2_insn_data
[i
].live_before
);
3701 if (peep2_do_rebuild_jump_labels
)
3702 rebuild_jump_labels (get_insns ());
3703 if (peep2_do_cleanup_cfg
)
3704 cleanup_cfg (CLEANUP_CFG_CHANGED
);
3706 #endif /* HAVE_peephole2 */
3708 /* Common predicates for use with define_bypass. */
3710 /* True if the dependency between OUT_INSN and IN_INSN is on the store
3711 data not the address operand(s) of the store. IN_INSN and OUT_INSN
3712 must be either a single_set or a PARALLEL with SETs inside. */
3715 store_data_bypass_p (rtx_insn
*out_insn
, rtx_insn
*in_insn
)
3717 rtx out_set
, in_set
;
3718 rtx out_pat
, in_pat
;
3719 rtx out_exp
, in_exp
;
3722 in_set
= single_set (in_insn
);
3725 if (!MEM_P (SET_DEST (in_set
)))
3728 out_set
= single_set (out_insn
);
3731 if (reg_mentioned_p (SET_DEST (out_set
), SET_DEST (in_set
)))
3736 out_pat
= PATTERN (out_insn
);
3738 if (GET_CODE (out_pat
) != PARALLEL
)
3741 for (i
= 0; i
< XVECLEN (out_pat
, 0); i
++)
3743 out_exp
= XVECEXP (out_pat
, 0, i
);
3745 if (GET_CODE (out_exp
) == CLOBBER
)
3748 gcc_assert (GET_CODE (out_exp
) == SET
);
3750 if (reg_mentioned_p (SET_DEST (out_exp
), SET_DEST (in_set
)))
3757 in_pat
= PATTERN (in_insn
);
3758 gcc_assert (GET_CODE (in_pat
) == PARALLEL
);
3760 for (i
= 0; i
< XVECLEN (in_pat
, 0); i
++)
3762 in_exp
= XVECEXP (in_pat
, 0, i
);
3764 if (GET_CODE (in_exp
) == CLOBBER
)
3767 gcc_assert (GET_CODE (in_exp
) == SET
);
3769 if (!MEM_P (SET_DEST (in_exp
)))
3772 out_set
= single_set (out_insn
);
3775 if (reg_mentioned_p (SET_DEST (out_set
), SET_DEST (in_exp
)))
3780 out_pat
= PATTERN (out_insn
);
3781 gcc_assert (GET_CODE (out_pat
) == PARALLEL
);
3783 for (j
= 0; j
< XVECLEN (out_pat
, 0); j
++)
3785 out_exp
= XVECEXP (out_pat
, 0, j
);
3787 if (GET_CODE (out_exp
) == CLOBBER
)
3790 gcc_assert (GET_CODE (out_exp
) == SET
);
3792 if (reg_mentioned_p (SET_DEST (out_exp
), SET_DEST (in_exp
)))
3802 /* True if the dependency between OUT_INSN and IN_INSN is in the IF_THEN_ELSE
3803 condition, and not the THEN or ELSE branch. OUT_INSN may be either a single
3804 or multiple set; IN_INSN should be single_set for truth, but for convenience
3805 of insn categorization may be any JUMP or CALL insn. */
3808 if_test_bypass_p (rtx_insn
*out_insn
, rtx_insn
*in_insn
)
3810 rtx out_set
, in_set
;
3812 in_set
= single_set (in_insn
);
3815 gcc_assert (JUMP_P (in_insn
) || CALL_P (in_insn
));
3819 if (GET_CODE (SET_SRC (in_set
)) != IF_THEN_ELSE
)
3821 in_set
= SET_SRC (in_set
);
3823 out_set
= single_set (out_insn
);
3826 if (reg_mentioned_p (SET_DEST (out_set
), XEXP (in_set
, 1))
3827 || reg_mentioned_p (SET_DEST (out_set
), XEXP (in_set
, 2)))
3835 out_pat
= PATTERN (out_insn
);
3836 gcc_assert (GET_CODE (out_pat
) == PARALLEL
);
3838 for (i
= 0; i
< XVECLEN (out_pat
, 0); i
++)
3840 rtx exp
= XVECEXP (out_pat
, 0, i
);
3842 if (GET_CODE (exp
) == CLOBBER
)
3845 gcc_assert (GET_CODE (exp
) == SET
);
3847 if (reg_mentioned_p (SET_DEST (out_set
), XEXP (in_set
, 1))
3848 || reg_mentioned_p (SET_DEST (out_set
), XEXP (in_set
, 2)))
3857 rest_of_handle_peephole2 (void)
3859 #ifdef HAVE_peephole2
3860 peephole2_optimize ();
3867 const pass_data pass_data_peephole2
=
3869 RTL_PASS
, /* type */
3870 "peephole2", /* name */
3871 OPTGROUP_NONE
, /* optinfo_flags */
3872 TV_PEEPHOLE2
, /* tv_id */
3873 0, /* properties_required */
3874 0, /* properties_provided */
3875 0, /* properties_destroyed */
3876 0, /* todo_flags_start */
3877 TODO_df_finish
, /* todo_flags_finish */
3880 class pass_peephole2
: public rtl_opt_pass
3883 pass_peephole2 (gcc::context
*ctxt
)
3884 : rtl_opt_pass (pass_data_peephole2
, ctxt
)
3887 /* opt_pass methods: */
3888 /* The epiphany backend creates a second instance of this pass, so we need
3890 opt_pass
* clone () { return new pass_peephole2 (m_ctxt
); }
3891 virtual bool gate (function
*) { return (optimize
> 0 && flag_peephole2
); }
3892 virtual unsigned int execute (function
*)
3894 return rest_of_handle_peephole2 ();
3897 }; // class pass_peephole2
3902 make_pass_peephole2 (gcc::context
*ctxt
)
3904 return new pass_peephole2 (ctxt
);
3909 const pass_data pass_data_split_all_insns
=
3911 RTL_PASS
, /* type */
3912 "split1", /* name */
3913 OPTGROUP_NONE
, /* optinfo_flags */
3914 TV_NONE
, /* tv_id */
3915 0, /* properties_required */
3916 0, /* properties_provided */
3917 0, /* properties_destroyed */
3918 0, /* todo_flags_start */
3919 0, /* todo_flags_finish */
3922 class pass_split_all_insns
: public rtl_opt_pass
3925 pass_split_all_insns (gcc::context
*ctxt
)
3926 : rtl_opt_pass (pass_data_split_all_insns
, ctxt
)
3929 /* opt_pass methods: */
3930 /* The epiphany backend creates a second instance of this pass, so
3931 we need a clone method. */
3932 opt_pass
* clone () { return new pass_split_all_insns (m_ctxt
); }
3933 virtual unsigned int execute (function
*)
3939 }; // class pass_split_all_insns
3944 make_pass_split_all_insns (gcc::context
*ctxt
)
3946 return new pass_split_all_insns (ctxt
);
3950 rest_of_handle_split_after_reload (void)
3952 /* If optimizing, then go ahead and split insns now. */
3962 const pass_data pass_data_split_after_reload
=
3964 RTL_PASS
, /* type */
3965 "split2", /* name */
3966 OPTGROUP_NONE
, /* optinfo_flags */
3967 TV_NONE
, /* tv_id */
3968 0, /* properties_required */
3969 0, /* properties_provided */
3970 0, /* properties_destroyed */
3971 0, /* todo_flags_start */
3972 0, /* todo_flags_finish */
3975 class pass_split_after_reload
: public rtl_opt_pass
3978 pass_split_after_reload (gcc::context
*ctxt
)
3979 : rtl_opt_pass (pass_data_split_after_reload
, ctxt
)
3982 /* opt_pass methods: */
3983 virtual unsigned int execute (function
*)
3985 return rest_of_handle_split_after_reload ();
3988 }; // class pass_split_after_reload
3993 make_pass_split_after_reload (gcc::context
*ctxt
)
3995 return new pass_split_after_reload (ctxt
);
4000 const pass_data pass_data_split_before_regstack
=
4002 RTL_PASS
, /* type */
4003 "split3", /* name */
4004 OPTGROUP_NONE
, /* optinfo_flags */
4005 TV_NONE
, /* tv_id */
4006 0, /* properties_required */
4007 0, /* properties_provided */
4008 0, /* properties_destroyed */
4009 0, /* todo_flags_start */
4010 0, /* todo_flags_finish */
4013 class pass_split_before_regstack
: public rtl_opt_pass
4016 pass_split_before_regstack (gcc::context
*ctxt
)
4017 : rtl_opt_pass (pass_data_split_before_regstack
, ctxt
)
4020 /* opt_pass methods: */
4021 virtual bool gate (function
*);
4022 virtual unsigned int execute (function
*)
4028 }; // class pass_split_before_regstack
4031 pass_split_before_regstack::gate (function
*)
4033 #if HAVE_ATTR_length && defined (STACK_REGS)
4034 /* If flow2 creates new instructions which need splitting
4035 and scheduling after reload is not done, they might not be
4036 split until final which doesn't allow splitting
4037 if HAVE_ATTR_length. */
4038 # ifdef INSN_SCHEDULING
4039 return (optimize
&& !flag_schedule_insns_after_reload
);
4051 make_pass_split_before_regstack (gcc::context
*ctxt
)
4053 return new pass_split_before_regstack (ctxt
);
4057 rest_of_handle_split_before_sched2 (void)
4059 #ifdef INSN_SCHEDULING
4067 const pass_data pass_data_split_before_sched2
=
4069 RTL_PASS
, /* type */
4070 "split4", /* name */
4071 OPTGROUP_NONE
, /* optinfo_flags */
4072 TV_NONE
, /* tv_id */
4073 0, /* properties_required */
4074 0, /* properties_provided */
4075 0, /* properties_destroyed */
4076 0, /* todo_flags_start */
4077 0, /* todo_flags_finish */
4080 class pass_split_before_sched2
: public rtl_opt_pass
4083 pass_split_before_sched2 (gcc::context
*ctxt
)
4084 : rtl_opt_pass (pass_data_split_before_sched2
, ctxt
)
4087 /* opt_pass methods: */
4088 virtual bool gate (function
*)
4090 #ifdef INSN_SCHEDULING
4091 return optimize
> 0 && flag_schedule_insns_after_reload
;
4097 virtual unsigned int execute (function
*)
4099 return rest_of_handle_split_before_sched2 ();
4102 }; // class pass_split_before_sched2
4107 make_pass_split_before_sched2 (gcc::context
*ctxt
)
4109 return new pass_split_before_sched2 (ctxt
);
4114 const pass_data pass_data_split_for_shorten_branches
=
4116 RTL_PASS
, /* type */
4117 "split5", /* name */
4118 OPTGROUP_NONE
, /* optinfo_flags */
4119 TV_NONE
, /* tv_id */
4120 0, /* properties_required */
4121 0, /* properties_provided */
4122 0, /* properties_destroyed */
4123 0, /* todo_flags_start */
4124 0, /* todo_flags_finish */
4127 class pass_split_for_shorten_branches
: public rtl_opt_pass
4130 pass_split_for_shorten_branches (gcc::context
*ctxt
)
4131 : rtl_opt_pass (pass_data_split_for_shorten_branches
, ctxt
)
4134 /* opt_pass methods: */
4135 virtual bool gate (function
*)
4137 /* The placement of the splitting that we do for shorten_branches
4138 depends on whether regstack is used by the target or not. */
4139 #if HAVE_ATTR_length && !defined (STACK_REGS)
4146 virtual unsigned int execute (function
*)
4148 return split_all_insns_noflow ();
4151 }; // class pass_split_for_shorten_branches
4156 make_pass_split_for_shorten_branches (gcc::context
*ctxt
)
4158 return new pass_split_for_shorten_branches (ctxt
);
4161 /* (Re)initialize the target information after a change in target. */
4166 /* The information is zero-initialized, so we don't need to do anything
4167 first time round. */
4168 if (!this_target_recog
->x_initialized
)
4170 this_target_recog
->x_initialized
= true;
4173 memset (this_target_recog
->x_bool_attr_masks
, 0,
4174 sizeof (this_target_recog
->x_bool_attr_masks
));
4175 for (int i
= 0; i
< LAST_INSN_CODE
; ++i
)
4176 if (this_target_recog
->x_op_alt
[i
])
4178 free (this_target_recog
->x_op_alt
[i
]);
4179 this_target_recog
->x_op_alt
[i
] = 0;