1 /* Subroutines used by or related to instruction recognition.
2 Copyright (C) 1987-2015 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify it under
7 the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 3, or (at your option) any later
11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
23 #include "coretypes.h"
28 #include "double-int.h"
35 #include "rtl-error.h"
37 #include "insn-config.h"
38 #include "insn-attr.h"
39 #include "hard-reg-set.h"
42 #include "addresses.h"
47 #include "statistics.h"
49 #include "fixed-value.h"
59 #include "dominance.h"
63 #include "cfgcleanup.h"
64 #include "basic-block.h"
67 #include "tree-pass.h"
69 #include "insn-codes.h"
71 #ifndef STACK_PUSH_CODE
72 #if STACK_GROWS_DOWNWARD
73 #define STACK_PUSH_CODE PRE_DEC
75 #define STACK_PUSH_CODE PRE_INC
79 #ifndef STACK_POP_CODE
80 #if STACK_GROWS_DOWNWARD
81 #define STACK_POP_CODE POST_INC
83 #define STACK_POP_CODE POST_DEC
87 static void validate_replace_rtx_1 (rtx
*, rtx
, rtx
, rtx_insn
*, bool);
88 static void validate_replace_src_1 (rtx
*, void *);
89 static rtx_insn
*split_insn (rtx_insn
*);
91 struct target_recog default_target_recog
;
93 struct target_recog
*this_target_recog
= &default_target_recog
;
96 /* Nonzero means allow operands to be volatile.
97 This should be 0 if you are generating rtl, such as if you are calling
98 the functions in optabs.c and expmed.c (most of the time).
99 This should be 1 if all valid insns need to be recognized,
100 such as in reginfo.c and final.c and reload.c.
102 init_recog and init_recog_no_volatile are responsible for setting this. */
106 struct recog_data_d recog_data
;
108 /* Contains a vector of operand_alternative structures, such that
109 operand OP of alternative A is at index A * n_operands + OP.
110 Set up by preprocess_constraints. */
111 const operand_alternative
*recog_op_alt
;
113 /* Used to provide recog_op_alt for asms. */
114 static operand_alternative asm_op_alt
[MAX_RECOG_OPERANDS
115 * MAX_RECOG_ALTERNATIVES
];
117 /* On return from `constrain_operands', indicate which alternative
120 int which_alternative
;
122 /* Nonzero after end of reload pass.
123 Set to 1 or 0 by toplev.c.
124 Controls the significance of (SUBREG (MEM)). */
126 int reload_completed
;
128 /* Nonzero after thread_prologue_and_epilogue_insns has run. */
129 int epilogue_completed
;
131 /* Initialize data used by the function `recog'.
132 This must be called once in the compilation of a function
133 before any insn recognition may be done in the function. */
136 init_recog_no_volatile (void)
148 /* Return true if labels in asm operands BODY are LABEL_REFs. */
151 asm_labels_ok (rtx body
)
156 asmop
= extract_asm_operands (body
);
157 if (asmop
== NULL_RTX
)
160 for (i
= 0; i
< ASM_OPERANDS_LABEL_LENGTH (asmop
); i
++)
161 if (GET_CODE (ASM_OPERANDS_LABEL (asmop
, i
)) != LABEL_REF
)
167 /* Check that X is an insn-body for an `asm' with operands
168 and that the operands mentioned in it are legitimate. */
171 check_asm_operands (rtx x
)
175 const char **constraints
;
178 if (!asm_labels_ok (x
))
181 /* Post-reload, be more strict with things. */
182 if (reload_completed
)
184 /* ??? Doh! We've not got the wrapping insn. Cook one up. */
185 rtx_insn
*insn
= make_insn_raw (x
);
187 constrain_operands (1, get_enabled_alternatives (insn
));
188 return which_alternative
>= 0;
191 noperands
= asm_noperands (x
);
197 operands
= XALLOCAVEC (rtx
, noperands
);
198 constraints
= XALLOCAVEC (const char *, noperands
);
200 decode_asm_operands (x
, operands
, NULL
, constraints
, NULL
, NULL
);
202 for (i
= 0; i
< noperands
; i
++)
204 const char *c
= constraints
[i
];
207 if (! asm_operand_ok (operands
[i
], c
, constraints
))
214 /* Static data for the next two routines. */
216 typedef struct change_t
225 static change_t
*changes
;
226 static int changes_allocated
;
228 static int num_changes
= 0;
230 /* Validate a proposed change to OBJECT. LOC is the location in the rtl
231 at which NEW_RTX will be placed. If OBJECT is zero, no validation is done,
232 the change is simply made.
234 Two types of objects are supported: If OBJECT is a MEM, memory_address_p
235 will be called with the address and mode as parameters. If OBJECT is
236 an INSN, CALL_INSN, or JUMP_INSN, the insn will be re-recognized with
239 IN_GROUP is nonzero if this is part of a group of changes that must be
240 performed as a group. In that case, the changes will be stored. The
241 function `apply_change_group' will validate and apply the changes.
243 If IN_GROUP is zero, this is a single change. Try to recognize the insn
244 or validate the memory reference with the change applied. If the result
245 is not valid for the machine, suppress the change and return zero.
246 Otherwise, perform the change and return 1. */
249 validate_change_1 (rtx object
, rtx
*loc
, rtx new_rtx
, bool in_group
, bool unshare
)
253 if (old
== new_rtx
|| rtx_equal_p (old
, new_rtx
))
256 gcc_assert (in_group
!= 0 || num_changes
== 0);
260 /* Save the information describing this change. */
261 if (num_changes
>= changes_allocated
)
263 if (changes_allocated
== 0)
264 /* This value allows for repeated substitutions inside complex
265 indexed addresses, or changes in up to 5 insns. */
266 changes_allocated
= MAX_RECOG_OPERANDS
* 5;
268 changes_allocated
*= 2;
270 changes
= XRESIZEVEC (change_t
, changes
, changes_allocated
);
273 changes
[num_changes
].object
= object
;
274 changes
[num_changes
].loc
= loc
;
275 changes
[num_changes
].old
= old
;
276 changes
[num_changes
].unshare
= unshare
;
278 if (object
&& !MEM_P (object
))
280 /* Set INSN_CODE to force rerecognition of insn. Save old code in
282 changes
[num_changes
].old_code
= INSN_CODE (object
);
283 INSN_CODE (object
) = -1;
288 /* If we are making a group of changes, return 1. Otherwise, validate the
289 change group we made. */
294 return apply_change_group ();
297 /* Wrapper for validate_change_1 without the UNSHARE argument defaulting
301 validate_change (rtx object
, rtx
*loc
, rtx new_rtx
, bool in_group
)
303 return validate_change_1 (object
, loc
, new_rtx
, in_group
, false);
306 /* Wrapper for validate_change_1 without the UNSHARE argument defaulting
310 validate_unshare_change (rtx object
, rtx
*loc
, rtx new_rtx
, bool in_group
)
312 return validate_change_1 (object
, loc
, new_rtx
, in_group
, true);
316 /* Keep X canonicalized if some changes have made it non-canonical; only
317 modifies the operands of X, not (for example) its code. Simplifications
318 are not the job of this routine.
320 Return true if anything was changed. */
322 canonicalize_change_group (rtx_insn
*insn
, rtx x
)
324 if (COMMUTATIVE_P (x
)
325 && swap_commutative_operands_p (XEXP (x
, 0), XEXP (x
, 1)))
327 /* Oops, the caller has made X no longer canonical.
328 Let's redo the changes in the correct order. */
329 rtx tem
= XEXP (x
, 0);
330 validate_unshare_change (insn
, &XEXP (x
, 0), XEXP (x
, 1), 1);
331 validate_unshare_change (insn
, &XEXP (x
, 1), tem
, 1);
339 /* This subroutine of apply_change_group verifies whether the changes to INSN
340 were valid; i.e. whether INSN can still be recognized.
342 If IN_GROUP is true clobbers which have to be added in order to
343 match the instructions will be added to the current change group.
344 Otherwise the changes will take effect immediately. */
347 insn_invalid_p (rtx_insn
*insn
, bool in_group
)
349 rtx pat
= PATTERN (insn
);
350 int num_clobbers
= 0;
351 /* If we are before reload and the pattern is a SET, see if we can add
353 int icode
= recog (pat
, insn
,
354 (GET_CODE (pat
) == SET
355 && ! reload_completed
356 && ! reload_in_progress
)
357 ? &num_clobbers
: 0);
358 int is_asm
= icode
< 0 && asm_noperands (PATTERN (insn
)) >= 0;
361 /* If this is an asm and the operand aren't legal, then fail. Likewise if
362 this is not an asm and the insn wasn't recognized. */
363 if ((is_asm
&& ! check_asm_operands (PATTERN (insn
)))
364 || (!is_asm
&& icode
< 0))
367 /* If we have to add CLOBBERs, fail if we have to add ones that reference
368 hard registers since our callers can't know if they are live or not.
369 Otherwise, add them. */
370 if (num_clobbers
> 0)
374 if (added_clobbers_hard_reg_p (icode
))
377 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (num_clobbers
+ 1));
378 XVECEXP (newpat
, 0, 0) = pat
;
379 add_clobbers (newpat
, icode
);
381 validate_change (insn
, &PATTERN (insn
), newpat
, 1);
383 PATTERN (insn
) = pat
= newpat
;
386 /* After reload, verify that all constraints are satisfied. */
387 if (reload_completed
)
391 if (! constrain_operands (1, get_preferred_alternatives (insn
)))
395 INSN_CODE (insn
) = icode
;
399 /* Return number of changes made and not validated yet. */
401 num_changes_pending (void)
406 /* Tentatively apply the changes numbered NUM and up.
407 Return 1 if all changes are valid, zero otherwise. */
410 verify_changes (int num
)
413 rtx last_validated
= NULL_RTX
;
415 /* The changes have been applied and all INSN_CODEs have been reset to force
418 The changes are valid if we aren't given an object, or if we are
419 given a MEM and it still is a valid address, or if this is in insn
420 and it is recognized. In the latter case, if reload has completed,
421 we also require that the operands meet the constraints for
424 for (i
= num
; i
< num_changes
; i
++)
426 rtx object
= changes
[i
].object
;
428 /* If there is no object to test or if it is the same as the one we
429 already tested, ignore it. */
430 if (object
== 0 || object
== last_validated
)
435 if (! memory_address_addr_space_p (GET_MODE (object
),
437 MEM_ADDR_SPACE (object
)))
440 else if (/* changes[i].old might be zero, e.g. when putting a
441 REG_FRAME_RELATED_EXPR into a previously empty list. */
443 && REG_P (changes
[i
].old
)
444 && asm_noperands (PATTERN (object
)) > 0
445 && REG_EXPR (changes
[i
].old
) != NULL_TREE
446 && DECL_ASSEMBLER_NAME_SET_P (REG_EXPR (changes
[i
].old
))
447 && DECL_REGISTER (REG_EXPR (changes
[i
].old
)))
449 /* Don't allow changes of hard register operands to inline
450 assemblies if they have been defined as register asm ("x"). */
453 else if (DEBUG_INSN_P (object
))
455 else if (insn_invalid_p (as_a
<rtx_insn
*> (object
), true))
457 rtx pat
= PATTERN (object
);
459 /* Perhaps we couldn't recognize the insn because there were
460 extra CLOBBERs at the end. If so, try to re-recognize
461 without the last CLOBBER (later iterations will cause each of
462 them to be eliminated, in turn). But don't do this if we
463 have an ASM_OPERAND. */
464 if (GET_CODE (pat
) == PARALLEL
465 && GET_CODE (XVECEXP (pat
, 0, XVECLEN (pat
, 0) - 1)) == CLOBBER
466 && asm_noperands (PATTERN (object
)) < 0)
470 if (XVECLEN (pat
, 0) == 2)
471 newpat
= XVECEXP (pat
, 0, 0);
477 = gen_rtx_PARALLEL (VOIDmode
,
478 rtvec_alloc (XVECLEN (pat
, 0) - 1));
479 for (j
= 0; j
< XVECLEN (newpat
, 0); j
++)
480 XVECEXP (newpat
, 0, j
) = XVECEXP (pat
, 0, j
);
483 /* Add a new change to this group to replace the pattern
484 with this new pattern. Then consider this change
485 as having succeeded. The change we added will
486 cause the entire call to fail if things remain invalid.
488 Note that this can lose if a later change than the one
489 we are processing specified &XVECEXP (PATTERN (object), 0, X)
490 but this shouldn't occur. */
492 validate_change (object
, &PATTERN (object
), newpat
, 1);
495 else if (GET_CODE (pat
) == USE
|| GET_CODE (pat
) == CLOBBER
496 || GET_CODE (pat
) == VAR_LOCATION
)
497 /* If this insn is a CLOBBER or USE, it is always valid, but is
503 last_validated
= object
;
506 return (i
== num_changes
);
509 /* A group of changes has previously been issued with validate_change
510 and verified with verify_changes. Call df_insn_rescan for each of
511 the insn changed and clear num_changes. */
514 confirm_change_group (void)
517 rtx last_object
= NULL
;
519 for (i
= 0; i
< num_changes
; i
++)
521 rtx object
= changes
[i
].object
;
523 if (changes
[i
].unshare
)
524 *changes
[i
].loc
= copy_rtx (*changes
[i
].loc
);
526 /* Avoid unnecessary rescanning when multiple changes to same instruction
530 if (object
!= last_object
&& last_object
&& INSN_P (last_object
))
531 df_insn_rescan (as_a
<rtx_insn
*> (last_object
));
532 last_object
= object
;
536 if (last_object
&& INSN_P (last_object
))
537 df_insn_rescan (as_a
<rtx_insn
*> (last_object
));
541 /* Apply a group of changes previously issued with `validate_change'.
542 If all changes are valid, call confirm_change_group and return 1,
543 otherwise, call cancel_changes and return 0. */
546 apply_change_group (void)
548 if (verify_changes (0))
550 confirm_change_group ();
561 /* Return the number of changes so far in the current group. */
564 num_validated_changes (void)
569 /* Retract the changes numbered NUM and up. */
572 cancel_changes (int num
)
576 /* Back out all the changes. Do this in the opposite order in which
578 for (i
= num_changes
- 1; i
>= num
; i
--)
580 *changes
[i
].loc
= changes
[i
].old
;
581 if (changes
[i
].object
&& !MEM_P (changes
[i
].object
))
582 INSN_CODE (changes
[i
].object
) = changes
[i
].old_code
;
587 /* Reduce conditional compilation elsewhere. */
590 #define CODE_FOR_extv CODE_FOR_nothing
594 #define CODE_FOR_extzv CODE_FOR_nothing
597 /* A subroutine of validate_replace_rtx_1 that tries to simplify the resulting
601 simplify_while_replacing (rtx
*loc
, rtx to
, rtx_insn
*object
,
602 machine_mode op0_mode
)
605 enum rtx_code code
= GET_CODE (x
);
606 rtx new_rtx
= NULL_RTX
;
608 if (SWAPPABLE_OPERANDS_P (x
)
609 && swap_commutative_operands_p (XEXP (x
, 0), XEXP (x
, 1)))
611 validate_unshare_change (object
, loc
,
612 gen_rtx_fmt_ee (COMMUTATIVE_ARITH_P (x
) ? code
613 : swap_condition (code
),
614 GET_MODE (x
), XEXP (x
, 1),
620 /* Canonicalize arithmetics with all constant operands. */
621 switch (GET_RTX_CLASS (code
))
624 if (CONSTANT_P (XEXP (x
, 0)))
625 new_rtx
= simplify_unary_operation (code
, GET_MODE (x
), XEXP (x
, 0),
630 if (CONSTANT_P (XEXP (x
, 0)) && CONSTANT_P (XEXP (x
, 1)))
631 new_rtx
= simplify_binary_operation (code
, GET_MODE (x
), XEXP (x
, 0),
635 case RTX_COMM_COMPARE
:
636 if (CONSTANT_P (XEXP (x
, 0)) && CONSTANT_P (XEXP (x
, 1)))
637 new_rtx
= simplify_relational_operation (code
, GET_MODE (x
), op0_mode
,
638 XEXP (x
, 0), XEXP (x
, 1));
645 validate_change (object
, loc
, new_rtx
, 1);
652 /* If we have a PLUS whose second operand is now a CONST_INT, use
653 simplify_gen_binary to try to simplify it.
654 ??? We may want later to remove this, once simplification is
655 separated from this function. */
656 if (CONST_INT_P (XEXP (x
, 1)) && XEXP (x
, 1) == to
)
657 validate_change (object
, loc
,
659 (PLUS
, GET_MODE (x
), XEXP (x
, 0), XEXP (x
, 1)), 1);
662 if (CONST_SCALAR_INT_P (XEXP (x
, 1)))
663 validate_change (object
, loc
,
665 (PLUS
, GET_MODE (x
), XEXP (x
, 0),
666 simplify_gen_unary (NEG
,
667 GET_MODE (x
), XEXP (x
, 1),
672 if (GET_MODE (XEXP (x
, 0)) == VOIDmode
)
674 new_rtx
= simplify_gen_unary (code
, GET_MODE (x
), XEXP (x
, 0),
676 /* If any of the above failed, substitute in something that
677 we know won't be recognized. */
679 new_rtx
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
680 validate_change (object
, loc
, new_rtx
, 1);
684 /* All subregs possible to simplify should be simplified. */
685 new_rtx
= simplify_subreg (GET_MODE (x
), SUBREG_REG (x
), op0_mode
,
688 /* Subregs of VOIDmode operands are incorrect. */
689 if (!new_rtx
&& GET_MODE (SUBREG_REG (x
)) == VOIDmode
)
690 new_rtx
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
692 validate_change (object
, loc
, new_rtx
, 1);
696 /* If we are replacing a register with memory, try to change the memory
697 to be the mode required for memory in extract operations (this isn't
698 likely to be an insertion operation; if it was, nothing bad will
699 happen, we might just fail in some cases). */
701 if (MEM_P (XEXP (x
, 0))
702 && CONST_INT_P (XEXP (x
, 1))
703 && CONST_INT_P (XEXP (x
, 2))
704 && !mode_dependent_address_p (XEXP (XEXP (x
, 0), 0),
705 MEM_ADDR_SPACE (XEXP (x
, 0)))
706 && !MEM_VOLATILE_P (XEXP (x
, 0)))
708 machine_mode wanted_mode
= VOIDmode
;
709 machine_mode is_mode
= GET_MODE (XEXP (x
, 0));
710 int pos
= INTVAL (XEXP (x
, 2));
712 if (GET_CODE (x
) == ZERO_EXTRACT
&& HAVE_extzv
)
714 wanted_mode
= insn_data
[CODE_FOR_extzv
].operand
[1].mode
;
715 if (wanted_mode
== VOIDmode
)
716 wanted_mode
= word_mode
;
718 else if (GET_CODE (x
) == SIGN_EXTRACT
&& HAVE_extv
)
720 wanted_mode
= insn_data
[CODE_FOR_extv
].operand
[1].mode
;
721 if (wanted_mode
== VOIDmode
)
722 wanted_mode
= word_mode
;
725 /* If we have a narrower mode, we can do something. */
726 if (wanted_mode
!= VOIDmode
727 && GET_MODE_SIZE (wanted_mode
) < GET_MODE_SIZE (is_mode
))
729 int offset
= pos
/ BITS_PER_UNIT
;
732 /* If the bytes and bits are counted differently, we
733 must adjust the offset. */
734 if (BYTES_BIG_ENDIAN
!= BITS_BIG_ENDIAN
)
736 (GET_MODE_SIZE (is_mode
) - GET_MODE_SIZE (wanted_mode
) -
739 gcc_assert (GET_MODE_PRECISION (wanted_mode
)
740 == GET_MODE_BITSIZE (wanted_mode
));
741 pos
%= GET_MODE_BITSIZE (wanted_mode
);
743 newmem
= adjust_address_nv (XEXP (x
, 0), wanted_mode
, offset
);
745 validate_change (object
, &XEXP (x
, 2), GEN_INT (pos
), 1);
746 validate_change (object
, &XEXP (x
, 0), newmem
, 1);
757 /* Replace every occurrence of FROM in X with TO. Mark each change with
758 validate_change passing OBJECT. */
761 validate_replace_rtx_1 (rtx
*loc
, rtx from
, rtx to
, rtx_insn
*object
,
768 machine_mode op0_mode
= VOIDmode
;
769 int prev_changes
= num_changes
;
775 fmt
= GET_RTX_FORMAT (code
);
777 op0_mode
= GET_MODE (XEXP (x
, 0));
779 /* X matches FROM if it is the same rtx or they are both referring to the
780 same register in the same mode. Avoid calling rtx_equal_p unless the
781 operands look similar. */
784 || (REG_P (x
) && REG_P (from
)
785 && GET_MODE (x
) == GET_MODE (from
)
786 && REGNO (x
) == REGNO (from
))
787 || (GET_CODE (x
) == GET_CODE (from
) && GET_MODE (x
) == GET_MODE (from
)
788 && rtx_equal_p (x
, from
)))
790 validate_unshare_change (object
, loc
, to
, 1);
794 /* Call ourself recursively to perform the replacements.
795 We must not replace inside already replaced expression, otherwise we
796 get infinite recursion for replacements like (reg X)->(subreg (reg X))
797 so we must special case shared ASM_OPERANDS. */
799 if (GET_CODE (x
) == PARALLEL
)
801 for (j
= XVECLEN (x
, 0) - 1; j
>= 0; j
--)
803 if (j
&& GET_CODE (XVECEXP (x
, 0, j
)) == SET
804 && GET_CODE (SET_SRC (XVECEXP (x
, 0, j
))) == ASM_OPERANDS
)
806 /* Verify that operands are really shared. */
807 gcc_assert (ASM_OPERANDS_INPUT_VEC (SET_SRC (XVECEXP (x
, 0, 0)))
808 == ASM_OPERANDS_INPUT_VEC (SET_SRC (XVECEXP
810 validate_replace_rtx_1 (&SET_DEST (XVECEXP (x
, 0, j
)),
811 from
, to
, object
, simplify
);
814 validate_replace_rtx_1 (&XVECEXP (x
, 0, j
), from
, to
, object
,
819 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
822 validate_replace_rtx_1 (&XEXP (x
, i
), from
, to
, object
, simplify
);
823 else if (fmt
[i
] == 'E')
824 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
825 validate_replace_rtx_1 (&XVECEXP (x
, i
, j
), from
, to
, object
,
829 /* If we didn't substitute, there is nothing more to do. */
830 if (num_changes
== prev_changes
)
833 /* ??? The regmove is no more, so is this aberration still necessary? */
834 /* Allow substituted expression to have different mode. This is used by
835 regmove to change mode of pseudo register. */
836 if (fmt
[0] == 'e' && GET_MODE (XEXP (x
, 0)) != VOIDmode
)
837 op0_mode
= GET_MODE (XEXP (x
, 0));
839 /* Do changes needed to keep rtx consistent. Don't do any other
840 simplifications, as it is not our job. */
842 simplify_while_replacing (loc
, to
, object
, op0_mode
);
845 /* Try replacing every occurrence of FROM in subexpression LOC of INSN
846 with TO. After all changes have been made, validate by seeing
847 if INSN is still valid. */
850 validate_replace_rtx_subexp (rtx from
, rtx to
, rtx_insn
*insn
, rtx
*loc
)
852 validate_replace_rtx_1 (loc
, from
, to
, insn
, true);
853 return apply_change_group ();
856 /* Try replacing every occurrence of FROM in INSN with TO. After all
857 changes have been made, validate by seeing if INSN is still valid. */
860 validate_replace_rtx (rtx from
, rtx to
, rtx_insn
*insn
)
862 validate_replace_rtx_1 (&PATTERN (insn
), from
, to
, insn
, true);
863 return apply_change_group ();
866 /* Try replacing every occurrence of FROM in WHERE with TO. Assume that WHERE
867 is a part of INSN. After all changes have been made, validate by seeing if
869 validate_replace_rtx (from, to, insn) is equivalent to
870 validate_replace_rtx_part (from, to, &PATTERN (insn), insn). */
873 validate_replace_rtx_part (rtx from
, rtx to
, rtx
*where
, rtx_insn
*insn
)
875 validate_replace_rtx_1 (where
, from
, to
, insn
, true);
876 return apply_change_group ();
879 /* Same as above, but do not simplify rtx afterwards. */
881 validate_replace_rtx_part_nosimplify (rtx from
, rtx to
, rtx
*where
,
884 validate_replace_rtx_1 (where
, from
, to
, insn
, false);
885 return apply_change_group ();
889 /* Try replacing every occurrence of FROM in INSN with TO. This also
890 will replace in REG_EQUAL and REG_EQUIV notes. */
893 validate_replace_rtx_group (rtx from
, rtx to
, rtx_insn
*insn
)
896 validate_replace_rtx_1 (&PATTERN (insn
), from
, to
, insn
, true);
897 for (note
= REG_NOTES (insn
); note
; note
= XEXP (note
, 1))
898 if (REG_NOTE_KIND (note
) == REG_EQUAL
899 || REG_NOTE_KIND (note
) == REG_EQUIV
)
900 validate_replace_rtx_1 (&XEXP (note
, 0), from
, to
, insn
, true);
903 /* Function called by note_uses to replace used subexpressions. */
904 struct validate_replace_src_data
906 rtx from
; /* Old RTX */
907 rtx to
; /* New RTX */
908 rtx_insn
*insn
; /* Insn in which substitution is occurring. */
912 validate_replace_src_1 (rtx
*x
, void *data
)
914 struct validate_replace_src_data
*d
915 = (struct validate_replace_src_data
*) data
;
917 validate_replace_rtx_1 (x
, d
->from
, d
->to
, d
->insn
, true);
920 /* Try replacing every occurrence of FROM in INSN with TO, avoiding
924 validate_replace_src_group (rtx from
, rtx to
, rtx_insn
*insn
)
926 struct validate_replace_src_data d
;
931 note_uses (&PATTERN (insn
), validate_replace_src_1
, &d
);
934 /* Try simplify INSN.
935 Invoke simplify_rtx () on every SET_SRC and SET_DEST inside the INSN's
936 pattern and return true if something was simplified. */
939 validate_simplify_insn (rtx_insn
*insn
)
945 pat
= PATTERN (insn
);
947 if (GET_CODE (pat
) == SET
)
949 newpat
= simplify_rtx (SET_SRC (pat
));
950 if (newpat
&& !rtx_equal_p (SET_SRC (pat
), newpat
))
951 validate_change (insn
, &SET_SRC (pat
), newpat
, 1);
952 newpat
= simplify_rtx (SET_DEST (pat
));
953 if (newpat
&& !rtx_equal_p (SET_DEST (pat
), newpat
))
954 validate_change (insn
, &SET_DEST (pat
), newpat
, 1);
956 else if (GET_CODE (pat
) == PARALLEL
)
957 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
959 rtx s
= XVECEXP (pat
, 0, i
);
961 if (GET_CODE (XVECEXP (pat
, 0, i
)) == SET
)
963 newpat
= simplify_rtx (SET_SRC (s
));
964 if (newpat
&& !rtx_equal_p (SET_SRC (s
), newpat
))
965 validate_change (insn
, &SET_SRC (s
), newpat
, 1);
966 newpat
= simplify_rtx (SET_DEST (s
));
967 if (newpat
&& !rtx_equal_p (SET_DEST (s
), newpat
))
968 validate_change (insn
, &SET_DEST (s
), newpat
, 1);
971 return ((num_changes_pending () > 0) && (apply_change_group () > 0));
974 /* Return 1 if the insn using CC0 set by INSN does not contain
975 any ordered tests applied to the condition codes.
976 EQ and NE tests do not count. */
979 next_insn_tests_no_inequality (rtx_insn
*insn
)
981 rtx_insn
*next
= next_cc0_user (insn
);
983 /* If there is no next insn, we have to take the conservative choice. */
987 return (INSN_P (next
)
988 && ! inequality_comparisons_p (PATTERN (next
)));
991 /* Return 1 if OP is a valid general operand for machine mode MODE.
992 This is either a register reference, a memory reference,
993 or a constant. In the case of a memory reference, the address
994 is checked for general validity for the target machine.
996 Register and memory references must have mode MODE in order to be valid,
997 but some constants have no machine mode and are valid for any mode.
999 If MODE is VOIDmode, OP is checked for validity for whatever mode
1002 The main use of this function is as a predicate in match_operand
1003 expressions in the machine description. */
1006 general_operand (rtx op
, machine_mode mode
)
1008 enum rtx_code code
= GET_CODE (op
);
1010 if (mode
== VOIDmode
)
1011 mode
= GET_MODE (op
);
1013 /* Don't accept CONST_INT or anything similar
1014 if the caller wants something floating. */
1015 if (GET_MODE (op
) == VOIDmode
&& mode
!= VOIDmode
1016 && GET_MODE_CLASS (mode
) != MODE_INT
1017 && GET_MODE_CLASS (mode
) != MODE_PARTIAL_INT
)
1020 if (CONST_INT_P (op
)
1022 && trunc_int_for_mode (INTVAL (op
), mode
) != INTVAL (op
))
1025 if (CONSTANT_P (op
))
1026 return ((GET_MODE (op
) == VOIDmode
|| GET_MODE (op
) == mode
1027 || mode
== VOIDmode
)
1028 && (! flag_pic
|| LEGITIMATE_PIC_OPERAND_P (op
))
1029 && targetm
.legitimate_constant_p (mode
== VOIDmode
1033 /* Except for certain constants with VOIDmode, already checked for,
1034 OP's mode must match MODE if MODE specifies a mode. */
1036 if (GET_MODE (op
) != mode
)
1041 rtx sub
= SUBREG_REG (op
);
1043 #ifdef INSN_SCHEDULING
1044 /* On machines that have insn scheduling, we want all memory
1045 reference to be explicit, so outlaw paradoxical SUBREGs.
1046 However, we must allow them after reload so that they can
1047 get cleaned up by cleanup_subreg_operands. */
1048 if (!reload_completed
&& MEM_P (sub
)
1049 && GET_MODE_SIZE (mode
) > GET_MODE_SIZE (GET_MODE (sub
)))
1052 /* Avoid memories with nonzero SUBREG_BYTE, as offsetting the memory
1053 may result in incorrect reference. We should simplify all valid
1054 subregs of MEM anyway. But allow this after reload because we
1055 might be called from cleanup_subreg_operands.
1057 ??? This is a kludge. */
1058 if (!reload_completed
&& SUBREG_BYTE (op
) != 0
1062 #ifdef CANNOT_CHANGE_MODE_CLASS
1064 && REGNO (sub
) < FIRST_PSEUDO_REGISTER
1065 && REG_CANNOT_CHANGE_MODE_P (REGNO (sub
), GET_MODE (sub
), mode
)
1066 && GET_MODE_CLASS (GET_MODE (sub
)) != MODE_COMPLEX_INT
1067 && GET_MODE_CLASS (GET_MODE (sub
)) != MODE_COMPLEX_FLOAT
1068 /* LRA can generate some invalid SUBREGS just for matched
1069 operand reload presentation. LRA needs to treat them as
1071 && ! LRA_SUBREG_P (op
))
1075 /* FLOAT_MODE subregs can't be paradoxical. Combine will occasionally
1076 create such rtl, and we must reject it. */
1077 if (SCALAR_FLOAT_MODE_P (GET_MODE (op
))
1078 /* LRA can use subreg to store a floating point value in an
1079 integer mode. Although the floating point and the
1080 integer modes need the same number of hard registers, the
1081 size of floating point mode can be less than the integer
1083 && ! lra_in_progress
1084 && GET_MODE_SIZE (GET_MODE (op
)) > GET_MODE_SIZE (GET_MODE (sub
)))
1088 code
= GET_CODE (op
);
1092 return (REGNO (op
) >= FIRST_PSEUDO_REGISTER
1093 || in_hard_reg_set_p (operand_reg_set
, GET_MODE (op
), REGNO (op
)));
1097 rtx y
= XEXP (op
, 0);
1099 if (! volatile_ok
&& MEM_VOLATILE_P (op
))
1102 /* Use the mem's mode, since it will be reloaded thus. LRA can
1103 generate move insn with invalid addresses which is made valid
1104 and efficiently calculated by LRA through further numerous
1107 || memory_address_addr_space_p (GET_MODE (op
), y
, MEM_ADDR_SPACE (op
)))
1114 /* Return 1 if OP is a valid memory address for a memory reference
1117 The main use of this function is as a predicate in match_operand
1118 expressions in the machine description. */
1121 address_operand (rtx op
, machine_mode mode
)
1123 return memory_address_p (mode
, op
);
1126 /* Return 1 if OP is a register reference of mode MODE.
1127 If MODE is VOIDmode, accept a register in any mode.
1129 The main use of this function is as a predicate in match_operand
1130 expressions in the machine description. */
1133 register_operand (rtx op
, machine_mode mode
)
1135 if (GET_CODE (op
) == SUBREG
)
1137 rtx sub
= SUBREG_REG (op
);
1139 /* Before reload, we can allow (SUBREG (MEM...)) as a register operand
1140 because it is guaranteed to be reloaded into one.
1141 Just make sure the MEM is valid in itself.
1142 (Ideally, (SUBREG (MEM)...) should not exist after reload,
1143 but currently it does result from (SUBREG (REG)...) where the
1144 reg went on the stack.) */
1145 if (!REG_P (sub
) && (reload_completed
|| !MEM_P (sub
)))
1148 else if (!REG_P (op
))
1150 return general_operand (op
, mode
);
1153 /* Return 1 for a register in Pmode; ignore the tested mode. */
1156 pmode_register_operand (rtx op
, machine_mode mode ATTRIBUTE_UNUSED
)
1158 return register_operand (op
, Pmode
);
1161 /* Return 1 if OP should match a MATCH_SCRATCH, i.e., if it is a SCRATCH
1162 or a hard register. */
1165 scratch_operand (rtx op
, machine_mode mode
)
1167 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
1170 return (GET_CODE (op
) == SCRATCH
1173 || (REGNO (op
) < FIRST_PSEUDO_REGISTER
1174 && REGNO_REG_CLASS (REGNO (op
)) != NO_REGS
))));
1177 /* Return 1 if OP is a valid immediate operand for mode MODE.
1179 The main use of this function is as a predicate in match_operand
1180 expressions in the machine description. */
1183 immediate_operand (rtx op
, machine_mode mode
)
1185 /* Don't accept CONST_INT or anything similar
1186 if the caller wants something floating. */
1187 if (GET_MODE (op
) == VOIDmode
&& mode
!= VOIDmode
1188 && GET_MODE_CLASS (mode
) != MODE_INT
1189 && GET_MODE_CLASS (mode
) != MODE_PARTIAL_INT
)
1192 if (CONST_INT_P (op
)
1194 && trunc_int_for_mode (INTVAL (op
), mode
) != INTVAL (op
))
1197 return (CONSTANT_P (op
)
1198 && (GET_MODE (op
) == mode
|| mode
== VOIDmode
1199 || GET_MODE (op
) == VOIDmode
)
1200 && (! flag_pic
|| LEGITIMATE_PIC_OPERAND_P (op
))
1201 && targetm
.legitimate_constant_p (mode
== VOIDmode
1206 /* Returns 1 if OP is an operand that is a CONST_INT of mode MODE. */
1209 const_int_operand (rtx op
, machine_mode mode
)
1211 if (!CONST_INT_P (op
))
1214 if (mode
!= VOIDmode
1215 && trunc_int_for_mode (INTVAL (op
), mode
) != INTVAL (op
))
1221 #if TARGET_SUPPORTS_WIDE_INT
1222 /* Returns 1 if OP is an operand that is a CONST_INT or CONST_WIDE_INT
1225 const_scalar_int_operand (rtx op
, machine_mode mode
)
1227 if (!CONST_SCALAR_INT_P (op
))
1230 if (CONST_INT_P (op
))
1231 return const_int_operand (op
, mode
);
1233 if (mode
!= VOIDmode
)
1235 int prec
= GET_MODE_PRECISION (mode
);
1236 int bitsize
= GET_MODE_BITSIZE (mode
);
1238 if (CONST_WIDE_INT_NUNITS (op
) * HOST_BITS_PER_WIDE_INT
> bitsize
)
1241 if (prec
== bitsize
)
1245 /* Multiword partial int. */
1247 = CONST_WIDE_INT_ELT (op
, CONST_WIDE_INT_NUNITS (op
) - 1);
1248 return (sext_hwi (x
, prec
& (HOST_BITS_PER_WIDE_INT
- 1)) == x
);
1254 /* Returns 1 if OP is an operand that is a constant integer or constant
1255 floating-point number of MODE. */
1258 const_double_operand (rtx op
, machine_mode mode
)
1260 return (GET_CODE (op
) == CONST_DOUBLE
)
1261 && (GET_MODE (op
) == mode
|| mode
== VOIDmode
);
1264 /* Returns 1 if OP is an operand that is a constant integer or constant
1265 floating-point number of MODE. */
1268 const_double_operand (rtx op
, machine_mode mode
)
1270 /* Don't accept CONST_INT or anything similar
1271 if the caller wants something floating. */
1272 if (GET_MODE (op
) == VOIDmode
&& mode
!= VOIDmode
1273 && GET_MODE_CLASS (mode
) != MODE_INT
1274 && GET_MODE_CLASS (mode
) != MODE_PARTIAL_INT
)
1277 return ((CONST_DOUBLE_P (op
) || CONST_INT_P (op
))
1278 && (mode
== VOIDmode
|| GET_MODE (op
) == mode
1279 || GET_MODE (op
) == VOIDmode
));
1282 /* Return 1 if OP is a general operand that is not an immediate
1283 operand of mode MODE. */
1286 nonimmediate_operand (rtx op
, machine_mode mode
)
1288 return (general_operand (op
, mode
) && ! CONSTANT_P (op
));
1291 /* Return 1 if OP is a register reference or immediate value of mode MODE. */
1294 nonmemory_operand (rtx op
, machine_mode mode
)
1296 if (CONSTANT_P (op
))
1297 return immediate_operand (op
, mode
);
1298 return register_operand (op
, mode
);
1301 /* Return 1 if OP is a valid operand that stands for pushing a
1302 value of mode MODE onto the stack.
1304 The main use of this function is as a predicate in match_operand
1305 expressions in the machine description. */
1308 push_operand (rtx op
, machine_mode mode
)
1310 unsigned int rounded_size
= GET_MODE_SIZE (mode
);
1312 #ifdef PUSH_ROUNDING
1313 rounded_size
= PUSH_ROUNDING (rounded_size
);
1319 if (mode
!= VOIDmode
&& GET_MODE (op
) != mode
)
1324 if (rounded_size
== GET_MODE_SIZE (mode
))
1326 if (GET_CODE (op
) != STACK_PUSH_CODE
)
1331 if (GET_CODE (op
) != PRE_MODIFY
1332 || GET_CODE (XEXP (op
, 1)) != PLUS
1333 || XEXP (XEXP (op
, 1), 0) != XEXP (op
, 0)
1334 || !CONST_INT_P (XEXP (XEXP (op
, 1), 1))
1335 || INTVAL (XEXP (XEXP (op
, 1), 1))
1336 != ((STACK_GROWS_DOWNWARD
? -1 : 1) * (int) rounded_size
))
1340 return XEXP (op
, 0) == stack_pointer_rtx
;
1343 /* Return 1 if OP is a valid operand that stands for popping a
1344 value of mode MODE off the stack.
1346 The main use of this function is as a predicate in match_operand
1347 expressions in the machine description. */
1350 pop_operand (rtx op
, machine_mode mode
)
1355 if (mode
!= VOIDmode
&& GET_MODE (op
) != mode
)
1360 if (GET_CODE (op
) != STACK_POP_CODE
)
1363 return XEXP (op
, 0) == stack_pointer_rtx
;
1366 /* Return 1 if ADDR is a valid memory address
1367 for mode MODE in address space AS. */
1370 memory_address_addr_space_p (machine_mode mode ATTRIBUTE_UNUSED
,
1371 rtx addr
, addr_space_t as
)
1373 #ifdef GO_IF_LEGITIMATE_ADDRESS
1374 gcc_assert (ADDR_SPACE_GENERIC_P (as
));
1375 GO_IF_LEGITIMATE_ADDRESS (mode
, addr
, win
);
1381 return targetm
.addr_space
.legitimate_address_p (mode
, addr
, 0, as
);
1385 /* Return 1 if OP is a valid memory reference with mode MODE,
1386 including a valid address.
1388 The main use of this function is as a predicate in match_operand
1389 expressions in the machine description. */
1392 memory_operand (rtx op
, machine_mode mode
)
1396 if (! reload_completed
)
1397 /* Note that no SUBREG is a memory operand before end of reload pass,
1398 because (SUBREG (MEM...)) forces reloading into a register. */
1399 return MEM_P (op
) && general_operand (op
, mode
);
1401 if (mode
!= VOIDmode
&& GET_MODE (op
) != mode
)
1405 if (GET_CODE (inner
) == SUBREG
)
1406 inner
= SUBREG_REG (inner
);
1408 return (MEM_P (inner
) && general_operand (op
, mode
));
1411 /* Return 1 if OP is a valid indirect memory reference with mode MODE;
1412 that is, a memory reference whose address is a general_operand. */
1415 indirect_operand (rtx op
, machine_mode mode
)
1417 /* Before reload, a SUBREG isn't in memory (see memory_operand, above). */
1418 if (! reload_completed
1419 && GET_CODE (op
) == SUBREG
&& MEM_P (SUBREG_REG (op
)))
1421 int offset
= SUBREG_BYTE (op
);
1422 rtx inner
= SUBREG_REG (op
);
1424 if (mode
!= VOIDmode
&& GET_MODE (op
) != mode
)
1427 /* The only way that we can have a general_operand as the resulting
1428 address is if OFFSET is zero and the address already is an operand
1429 or if the address is (plus Y (const_int -OFFSET)) and Y is an
1432 return ((offset
== 0 && general_operand (XEXP (inner
, 0), Pmode
))
1433 || (GET_CODE (XEXP (inner
, 0)) == PLUS
1434 && CONST_INT_P (XEXP (XEXP (inner
, 0), 1))
1435 && INTVAL (XEXP (XEXP (inner
, 0), 1)) == -offset
1436 && general_operand (XEXP (XEXP (inner
, 0), 0), Pmode
)));
1440 && memory_operand (op
, mode
)
1441 && general_operand (XEXP (op
, 0), Pmode
));
1444 /* Return 1 if this is an ordered comparison operator (not including
1445 ORDERED and UNORDERED). */
1448 ordered_comparison_operator (rtx op
, machine_mode mode
)
1450 if (mode
!= VOIDmode
&& GET_MODE (op
) != mode
)
1452 switch (GET_CODE (op
))
1470 /* Return 1 if this is a comparison operator. This allows the use of
1471 MATCH_OPERATOR to recognize all the branch insns. */
1474 comparison_operator (rtx op
, machine_mode mode
)
1476 return ((mode
== VOIDmode
|| GET_MODE (op
) == mode
)
1477 && COMPARISON_P (op
));
1480 /* If BODY is an insn body that uses ASM_OPERANDS, return it. */
1483 extract_asm_operands (rtx body
)
1486 switch (GET_CODE (body
))
1492 /* Single output operand: BODY is (set OUTPUT (asm_operands ...)). */
1493 tmp
= SET_SRC (body
);
1494 if (GET_CODE (tmp
) == ASM_OPERANDS
)
1499 tmp
= XVECEXP (body
, 0, 0);
1500 if (GET_CODE (tmp
) == ASM_OPERANDS
)
1502 if (GET_CODE (tmp
) == SET
)
1504 tmp
= SET_SRC (tmp
);
1505 if (GET_CODE (tmp
) == ASM_OPERANDS
)
1516 /* If BODY is an insn body that uses ASM_OPERANDS,
1517 return the number of operands (both input and output) in the insn.
1518 Otherwise return -1. */
1521 asm_noperands (const_rtx body
)
1523 rtx asm_op
= extract_asm_operands (CONST_CAST_RTX (body
));
1529 if (GET_CODE (body
) == SET
)
1531 else if (GET_CODE (body
) == PARALLEL
)
1534 if (GET_CODE (XVECEXP (body
, 0, 0)) == SET
)
1536 /* Multiple output operands, or 1 output plus some clobbers:
1538 [(set OUTPUT (asm_operands ...))... (clobber (reg ...))...]. */
1539 /* Count backwards through CLOBBERs to determine number of SETs. */
1540 for (i
= XVECLEN (body
, 0); i
> 0; i
--)
1542 if (GET_CODE (XVECEXP (body
, 0, i
- 1)) == SET
)
1544 if (GET_CODE (XVECEXP (body
, 0, i
- 1)) != CLOBBER
)
1548 /* N_SETS is now number of output operands. */
1551 /* Verify that all the SETs we have
1552 came from a single original asm_operands insn
1553 (so that invalid combinations are blocked). */
1554 for (i
= 0; i
< n_sets
; i
++)
1556 rtx elt
= XVECEXP (body
, 0, i
);
1557 if (GET_CODE (elt
) != SET
)
1559 if (GET_CODE (SET_SRC (elt
)) != ASM_OPERANDS
)
1561 /* If these ASM_OPERANDS rtx's came from different original insns
1562 then they aren't allowed together. */
1563 if (ASM_OPERANDS_INPUT_VEC (SET_SRC (elt
))
1564 != ASM_OPERANDS_INPUT_VEC (asm_op
))
1570 /* 0 outputs, but some clobbers:
1571 body is [(asm_operands ...) (clobber (reg ...))...]. */
1572 /* Make sure all the other parallel things really are clobbers. */
1573 for (i
= XVECLEN (body
, 0) - 1; i
> 0; i
--)
1574 if (GET_CODE (XVECEXP (body
, 0, i
)) != CLOBBER
)
1579 return (ASM_OPERANDS_INPUT_LENGTH (asm_op
)
1580 + ASM_OPERANDS_LABEL_LENGTH (asm_op
) + n_sets
);
1583 /* Assuming BODY is an insn body that uses ASM_OPERANDS,
1584 copy its operands (both input and output) into the vector OPERANDS,
1585 the locations of the operands within the insn into the vector OPERAND_LOCS,
1586 and the constraints for the operands into CONSTRAINTS.
1587 Write the modes of the operands into MODES.
1588 Return the assembler-template.
1590 If MODES, OPERAND_LOCS, CONSTRAINTS or OPERANDS is 0,
1591 we don't store that info. */
1594 decode_asm_operands (rtx body
, rtx
*operands
, rtx
**operand_locs
,
1595 const char **constraints
, machine_mode
*modes
,
1598 int nbase
= 0, n
, i
;
1601 switch (GET_CODE (body
))
1604 /* Zero output asm: BODY is (asm_operands ...). */
1609 /* Single output asm: BODY is (set OUTPUT (asm_operands ...)). */
1610 asmop
= SET_SRC (body
);
1612 /* The output is in the SET.
1613 Its constraint is in the ASM_OPERANDS itself. */
1615 operands
[0] = SET_DEST (body
);
1617 operand_locs
[0] = &SET_DEST (body
);
1619 constraints
[0] = ASM_OPERANDS_OUTPUT_CONSTRAINT (asmop
);
1621 modes
[0] = GET_MODE (SET_DEST (body
));
1627 int nparallel
= XVECLEN (body
, 0); /* Includes CLOBBERs. */
1629 asmop
= XVECEXP (body
, 0, 0);
1630 if (GET_CODE (asmop
) == SET
)
1632 asmop
= SET_SRC (asmop
);
1634 /* At least one output, plus some CLOBBERs. The outputs are in
1635 the SETs. Their constraints are in the ASM_OPERANDS itself. */
1636 for (i
= 0; i
< nparallel
; i
++)
1638 if (GET_CODE (XVECEXP (body
, 0, i
)) == CLOBBER
)
1639 break; /* Past last SET */
1641 operands
[i
] = SET_DEST (XVECEXP (body
, 0, i
));
1643 operand_locs
[i
] = &SET_DEST (XVECEXP (body
, 0, i
));
1645 constraints
[i
] = XSTR (SET_SRC (XVECEXP (body
, 0, i
)), 1);
1647 modes
[i
] = GET_MODE (SET_DEST (XVECEXP (body
, 0, i
)));
1658 n
= ASM_OPERANDS_INPUT_LENGTH (asmop
);
1659 for (i
= 0; i
< n
; i
++)
1662 operand_locs
[nbase
+ i
] = &ASM_OPERANDS_INPUT (asmop
, i
);
1664 operands
[nbase
+ i
] = ASM_OPERANDS_INPUT (asmop
, i
);
1666 constraints
[nbase
+ i
] = ASM_OPERANDS_INPUT_CONSTRAINT (asmop
, i
);
1668 modes
[nbase
+ i
] = ASM_OPERANDS_INPUT_MODE (asmop
, i
);
1672 n
= ASM_OPERANDS_LABEL_LENGTH (asmop
);
1673 for (i
= 0; i
< n
; i
++)
1676 operand_locs
[nbase
+ i
] = &ASM_OPERANDS_LABEL (asmop
, i
);
1678 operands
[nbase
+ i
] = ASM_OPERANDS_LABEL (asmop
, i
);
1680 constraints
[nbase
+ i
] = "";
1682 modes
[nbase
+ i
] = Pmode
;
1686 *loc
= ASM_OPERANDS_SOURCE_LOCATION (asmop
);
1688 return ASM_OPERANDS_TEMPLATE (asmop
);
1691 /* Parse inline assembly string STRING and determine which operands are
1692 referenced by % markers. For the first NOPERANDS operands, set USED[I]
1693 to true if operand I is referenced.
1695 This is intended to distinguish barrier-like asms such as:
1697 asm ("" : "=m" (...));
1699 from real references such as:
1701 asm ("sw\t$0, %0" : "=m" (...)); */
1704 get_referenced_operands (const char *string
, bool *used
,
1705 unsigned int noperands
)
1707 memset (used
, 0, sizeof (bool) * noperands
);
1708 const char *p
= string
;
1714 /* A letter followed by a digit indicates an operand number. */
1715 if (ISALPHA (p
[0]) && ISDIGIT (p
[1]))
1720 unsigned long opnum
= strtoul (p
, &endptr
, 10);
1721 if (endptr
!= p
&& opnum
< noperands
)
1735 /* Check if an asm_operand matches its constraints.
1736 Return > 0 if ok, = 0 if bad, < 0 if inconclusive. */
1739 asm_operand_ok (rtx op
, const char *constraint
, const char **constraints
)
1743 bool incdec_ok
= false;
1746 /* Use constrain_operands after reload. */
1747 gcc_assert (!reload_completed
);
1749 /* Empty constraint string is the same as "X,...,X", i.e. X for as
1750 many alternatives as required to match the other operands. */
1751 if (*constraint
== '\0')
1756 enum constraint_num cn
;
1757 char c
= *constraint
;
1765 case '0': case '1': case '2': case '3': case '4':
1766 case '5': case '6': case '7': case '8': case '9':
1767 /* If caller provided constraints pointer, look up
1768 the matching constraint. Otherwise, our caller should have
1769 given us the proper matching constraint, but we can't
1770 actually fail the check if they didn't. Indicate that
1771 results are inconclusive. */
1775 unsigned long match
;
1777 match
= strtoul (constraint
, &end
, 10);
1779 result
= asm_operand_ok (op
, constraints
[match
], NULL
);
1780 constraint
= (const char *) end
;
1786 while (ISDIGIT (*constraint
));
1792 /* The rest of the compiler assumes that reloading the address
1793 of a MEM into a register will make it fit an 'o' constraint.
1794 That is, if it sees a MEM operand for an 'o' constraint,
1795 it assumes that (mem (base-reg)) will fit.
1797 That assumption fails on targets that don't have offsettable
1798 addresses at all. We therefore need to treat 'o' asm
1799 constraints as a special case and only accept operands that
1800 are already offsettable, thus proving that at least one
1801 offsettable address exists. */
1802 case 'o': /* offsettable */
1803 if (offsettable_nonstrict_memref_p (op
))
1808 if (general_operand (op
, VOIDmode
))
1815 /* ??? Before auto-inc-dec, auto inc/dec insns are not supposed
1816 to exist, excepting those that expand_call created. Further,
1817 on some machines which do not have generalized auto inc/dec,
1818 an inc/dec is not a memory_operand.
1820 Match any memory and hope things are resolved after reload. */
1824 cn
= lookup_constraint (constraint
);
1825 switch (get_constraint_type (cn
))
1829 && reg_class_for_constraint (cn
) != NO_REGS
1830 && GET_MODE (op
) != BLKmode
1831 && register_operand (op
, VOIDmode
))
1838 && insn_const_int_ok_for_constraint (INTVAL (op
), cn
))
1843 /* Every memory operand can be reloaded to fit. */
1844 result
= result
|| memory_operand (op
, VOIDmode
);
1848 /* Every address operand can be reloaded to fit. */
1849 result
= result
|| address_operand (op
, VOIDmode
);
1853 result
= result
|| constraint_satisfied_p (op
, cn
);
1858 len
= CONSTRAINT_LEN (c
, constraint
);
1861 while (--len
&& *constraint
);
1867 /* For operands without < or > constraints reject side-effects. */
1868 if (!incdec_ok
&& result
&& MEM_P (op
))
1869 switch (GET_CODE (XEXP (op
, 0)))
1886 /* Given an rtx *P, if it is a sum containing an integer constant term,
1887 return the location (type rtx *) of the pointer to that constant term.
1888 Otherwise, return a null pointer. */
1891 find_constant_term_loc (rtx
*p
)
1894 enum rtx_code code
= GET_CODE (*p
);
1896 /* If *P IS such a constant term, P is its location. */
1898 if (code
== CONST_INT
|| code
== SYMBOL_REF
|| code
== LABEL_REF
1902 /* Otherwise, if not a sum, it has no constant term. */
1904 if (GET_CODE (*p
) != PLUS
)
1907 /* If one of the summands is constant, return its location. */
1909 if (XEXP (*p
, 0) && CONSTANT_P (XEXP (*p
, 0))
1910 && XEXP (*p
, 1) && CONSTANT_P (XEXP (*p
, 1)))
1913 /* Otherwise, check each summand for containing a constant term. */
1915 if (XEXP (*p
, 0) != 0)
1917 tem
= find_constant_term_loc (&XEXP (*p
, 0));
1922 if (XEXP (*p
, 1) != 0)
1924 tem
= find_constant_term_loc (&XEXP (*p
, 1));
1932 /* Return 1 if OP is a memory reference
1933 whose address contains no side effects
1934 and remains valid after the addition
1935 of a positive integer less than the
1936 size of the object being referenced.
1938 We assume that the original address is valid and do not check it.
1940 This uses strict_memory_address_p as a subroutine, so
1941 don't use it before reload. */
1944 offsettable_memref_p (rtx op
)
1946 return ((MEM_P (op
))
1947 && offsettable_address_addr_space_p (1, GET_MODE (op
), XEXP (op
, 0),
1948 MEM_ADDR_SPACE (op
)));
1951 /* Similar, but don't require a strictly valid mem ref:
1952 consider pseudo-regs valid as index or base regs. */
1955 offsettable_nonstrict_memref_p (rtx op
)
1957 return ((MEM_P (op
))
1958 && offsettable_address_addr_space_p (0, GET_MODE (op
), XEXP (op
, 0),
1959 MEM_ADDR_SPACE (op
)));
1962 /* Return 1 if Y is a memory address which contains no side effects
1963 and would remain valid for address space AS after the addition of
1964 a positive integer less than the size of that mode.
1966 We assume that the original address is valid and do not check it.
1967 We do check that it is valid for narrower modes.
1969 If STRICTP is nonzero, we require a strictly valid address,
1970 for the sake of use in reload.c. */
1973 offsettable_address_addr_space_p (int strictp
, machine_mode mode
, rtx y
,
1976 enum rtx_code ycode
= GET_CODE (y
);
1980 int (*addressp
) (machine_mode
, rtx
, addr_space_t
) =
1981 (strictp
? strict_memory_address_addr_space_p
1982 : memory_address_addr_space_p
);
1983 unsigned int mode_sz
= GET_MODE_SIZE (mode
);
1985 if (CONSTANT_ADDRESS_P (y
))
1988 /* Adjusting an offsettable address involves changing to a narrower mode.
1989 Make sure that's OK. */
1991 if (mode_dependent_address_p (y
, as
))
1994 machine_mode address_mode
= GET_MODE (y
);
1995 if (address_mode
== VOIDmode
)
1996 address_mode
= targetm
.addr_space
.address_mode (as
);
1997 #ifdef POINTERS_EXTEND_UNSIGNED
1998 machine_mode pointer_mode
= targetm
.addr_space
.pointer_mode (as
);
2001 /* ??? How much offset does an offsettable BLKmode reference need?
2002 Clearly that depends on the situation in which it's being used.
2003 However, the current situation in which we test 0xffffffff is
2004 less than ideal. Caveat user. */
2006 mode_sz
= BIGGEST_ALIGNMENT
/ BITS_PER_UNIT
;
2008 /* If the expression contains a constant term,
2009 see if it remains valid when max possible offset is added. */
2011 if ((ycode
== PLUS
) && (y2
= find_constant_term_loc (&y1
)))
2016 *y2
= plus_constant (address_mode
, *y2
, mode_sz
- 1);
2017 /* Use QImode because an odd displacement may be automatically invalid
2018 for any wider mode. But it should be valid for a single byte. */
2019 good
= (*addressp
) (QImode
, y
, as
);
2021 /* In any case, restore old contents of memory. */
2026 if (GET_RTX_CLASS (ycode
) == RTX_AUTOINC
)
2029 /* The offset added here is chosen as the maximum offset that
2030 any instruction could need to add when operating on something
2031 of the specified mode. We assume that if Y and Y+c are
2032 valid addresses then so is Y+d for all 0<d<c. adjust_address will
2033 go inside a LO_SUM here, so we do so as well. */
2034 if (GET_CODE (y
) == LO_SUM
2036 && mode_sz
<= GET_MODE_ALIGNMENT (mode
) / BITS_PER_UNIT
)
2037 z
= gen_rtx_LO_SUM (address_mode
, XEXP (y
, 0),
2038 plus_constant (address_mode
, XEXP (y
, 1),
2040 #ifdef POINTERS_EXTEND_UNSIGNED
2041 /* Likewise for a ZERO_EXTEND from pointer_mode. */
2042 else if (POINTERS_EXTEND_UNSIGNED
> 0
2043 && GET_CODE (y
) == ZERO_EXTEND
2044 && GET_MODE (XEXP (y
, 0)) == pointer_mode
)
2045 z
= gen_rtx_ZERO_EXTEND (address_mode
,
2046 plus_constant (pointer_mode
, XEXP (y
, 0),
2050 z
= plus_constant (address_mode
, y
, mode_sz
- 1);
2052 /* Use QImode because an odd displacement may be automatically invalid
2053 for any wider mode. But it should be valid for a single byte. */
2054 return (*addressp
) (QImode
, z
, as
);
2057 /* Return 1 if ADDR is an address-expression whose effect depends
2058 on the mode of the memory reference it is used in.
2060 ADDRSPACE is the address space associated with the address.
2062 Autoincrement addressing is a typical example of mode-dependence
2063 because the amount of the increment depends on the mode. */
2066 mode_dependent_address_p (rtx addr
, addr_space_t addrspace
)
2068 /* Auto-increment addressing with anything other than post_modify
2069 or pre_modify always introduces a mode dependency. Catch such
2070 cases now instead of deferring to the target. */
2071 if (GET_CODE (addr
) == PRE_INC
2072 || GET_CODE (addr
) == POST_INC
2073 || GET_CODE (addr
) == PRE_DEC
2074 || GET_CODE (addr
) == POST_DEC
)
2077 return targetm
.mode_dependent_address_p (addr
, addrspace
);
2080 /* Return true if boolean attribute ATTR is supported. */
2083 have_bool_attr (bool_attr attr
)
2088 return HAVE_ATTR_enabled
;
2089 case BA_PREFERRED_FOR_SIZE
:
2090 return HAVE_ATTR_enabled
|| HAVE_ATTR_preferred_for_size
;
2091 case BA_PREFERRED_FOR_SPEED
:
2092 return HAVE_ATTR_enabled
|| HAVE_ATTR_preferred_for_speed
;
2097 /* Return the value of ATTR for instruction INSN. */
2100 get_bool_attr (rtx_insn
*insn
, bool_attr attr
)
2105 return get_attr_enabled (insn
);
2106 case BA_PREFERRED_FOR_SIZE
:
2107 return get_attr_enabled (insn
) && get_attr_preferred_for_size (insn
);
2108 case BA_PREFERRED_FOR_SPEED
:
2109 return get_attr_enabled (insn
) && get_attr_preferred_for_speed (insn
);
2114 /* Like get_bool_attr_mask, but don't use the cache. */
2116 static alternative_mask
2117 get_bool_attr_mask_uncached (rtx_insn
*insn
, bool_attr attr
)
2119 /* Temporarily install enough information for get_attr_<foo> to assume
2120 that the insn operands are already cached. As above, the attribute
2121 mustn't depend on the values of operands, so we don't provide their
2122 real values here. */
2123 rtx_insn
*old_insn
= recog_data
.insn
;
2124 int old_alternative
= which_alternative
;
2126 recog_data
.insn
= insn
;
2127 alternative_mask mask
= ALL_ALTERNATIVES
;
2128 int n_alternatives
= insn_data
[INSN_CODE (insn
)].n_alternatives
;
2129 for (int i
= 0; i
< n_alternatives
; i
++)
2131 which_alternative
= i
;
2132 if (!get_bool_attr (insn
, attr
))
2133 mask
&= ~ALTERNATIVE_BIT (i
);
2136 recog_data
.insn
= old_insn
;
2137 which_alternative
= old_alternative
;
2141 /* Return the mask of operand alternatives that are allowed for INSN
2142 by boolean attribute ATTR. This mask depends only on INSN and on
2143 the current target; it does not depend on things like the values of
2146 static alternative_mask
2147 get_bool_attr_mask (rtx_insn
*insn
, bool_attr attr
)
2149 /* Quick exit for asms and for targets that don't use these attributes. */
2150 int code
= INSN_CODE (insn
);
2151 if (code
< 0 || !have_bool_attr (attr
))
2152 return ALL_ALTERNATIVES
;
2154 /* Calling get_attr_<foo> can be expensive, so cache the mask
2156 if (!this_target_recog
->x_bool_attr_masks
[code
][attr
])
2157 this_target_recog
->x_bool_attr_masks
[code
][attr
]
2158 = get_bool_attr_mask_uncached (insn
, attr
);
2159 return this_target_recog
->x_bool_attr_masks
[code
][attr
];
2162 /* Return the set of alternatives of INSN that are allowed by the current
2166 get_enabled_alternatives (rtx_insn
*insn
)
2168 return get_bool_attr_mask (insn
, BA_ENABLED
);
2171 /* Return the set of alternatives of INSN that are allowed by the current
2172 target and are preferred for the current size/speed optimization
2176 get_preferred_alternatives (rtx_insn
*insn
)
2178 if (optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn
)))
2179 return get_bool_attr_mask (insn
, BA_PREFERRED_FOR_SPEED
);
2181 return get_bool_attr_mask (insn
, BA_PREFERRED_FOR_SIZE
);
2184 /* Return the set of alternatives of INSN that are allowed by the current
2185 target and are preferred for the size/speed optimization choice
2186 associated with BB. Passing a separate BB is useful if INSN has not
2187 been emitted yet or if we are considering moving it to a different
2191 get_preferred_alternatives (rtx_insn
*insn
, basic_block bb
)
2193 if (optimize_bb_for_speed_p (bb
))
2194 return get_bool_attr_mask (insn
, BA_PREFERRED_FOR_SPEED
);
2196 return get_bool_attr_mask (insn
, BA_PREFERRED_FOR_SIZE
);
2199 /* Assert that the cached boolean attributes for INSN are still accurate.
2200 The backend is required to define these attributes in a way that only
2201 depends on the current target (rather than operands, compiler phase,
2205 check_bool_attrs (rtx_insn
*insn
)
2207 int code
= INSN_CODE (insn
);
2209 for (int i
= 0; i
<= BA_LAST
; ++i
)
2211 enum bool_attr attr
= (enum bool_attr
) i
;
2212 if (this_target_recog
->x_bool_attr_masks
[code
][attr
])
2213 gcc_assert (this_target_recog
->x_bool_attr_masks
[code
][attr
]
2214 == get_bool_attr_mask_uncached (insn
, attr
));
2219 /* Like extract_insn, but save insn extracted and don't extract again, when
2220 called again for the same insn expecting that recog_data still contain the
2221 valid information. This is used primary by gen_attr infrastructure that
2222 often does extract insn again and again. */
2224 extract_insn_cached (rtx_insn
*insn
)
2226 if (recog_data
.insn
== insn
&& INSN_CODE (insn
) >= 0)
2228 extract_insn (insn
);
2229 recog_data
.insn
= insn
;
2232 /* Do uncached extract_insn, constrain_operands and complain about failures.
2233 This should be used when extracting a pre-existing constrained instruction
2234 if the caller wants to know which alternative was chosen. */
2236 extract_constrain_insn (rtx_insn
*insn
)
2238 extract_insn (insn
);
2239 if (!constrain_operands (reload_completed
, get_enabled_alternatives (insn
)))
2240 fatal_insn_not_found (insn
);
2243 /* Do cached extract_insn, constrain_operands and complain about failures.
2244 Used by insn_attrtab. */
2246 extract_constrain_insn_cached (rtx_insn
*insn
)
2248 extract_insn_cached (insn
);
2249 if (which_alternative
== -1
2250 && !constrain_operands (reload_completed
,
2251 get_enabled_alternatives (insn
)))
2252 fatal_insn_not_found (insn
);
2255 /* Do cached constrain_operands on INSN and complain about failures. */
2257 constrain_operands_cached (rtx_insn
*insn
, int strict
)
2259 if (which_alternative
== -1)
2260 return constrain_operands (strict
, get_enabled_alternatives (insn
));
2265 /* Analyze INSN and fill in recog_data. */
2268 extract_insn (rtx_insn
*insn
)
2273 rtx body
= PATTERN (insn
);
2275 recog_data
.n_operands
= 0;
2276 recog_data
.n_alternatives
= 0;
2277 recog_data
.n_dups
= 0;
2278 recog_data
.is_asm
= false;
2280 switch (GET_CODE (body
))
2291 if (GET_CODE (SET_SRC (body
)) == ASM_OPERANDS
)
2296 if ((GET_CODE (XVECEXP (body
, 0, 0)) == SET
2297 && GET_CODE (SET_SRC (XVECEXP (body
, 0, 0))) == ASM_OPERANDS
)
2298 || GET_CODE (XVECEXP (body
, 0, 0)) == ASM_OPERANDS
)
2304 recog_data
.n_operands
= noperands
= asm_noperands (body
);
2307 /* This insn is an `asm' with operands. */
2309 /* expand_asm_operands makes sure there aren't too many operands. */
2310 gcc_assert (noperands
<= MAX_RECOG_OPERANDS
);
2312 /* Now get the operand values and constraints out of the insn. */
2313 decode_asm_operands (body
, recog_data
.operand
,
2314 recog_data
.operand_loc
,
2315 recog_data
.constraints
,
2316 recog_data
.operand_mode
, NULL
);
2317 memset (recog_data
.is_operator
, 0, sizeof recog_data
.is_operator
);
2320 const char *p
= recog_data
.constraints
[0];
2321 recog_data
.n_alternatives
= 1;
2323 recog_data
.n_alternatives
+= (*p
++ == ',');
2325 recog_data
.is_asm
= true;
2328 fatal_insn_not_found (insn
);
2332 /* Ordinary insn: recognize it, get the operands via insn_extract
2333 and get the constraints. */
2335 icode
= recog_memoized (insn
);
2337 fatal_insn_not_found (insn
);
2339 recog_data
.n_operands
= noperands
= insn_data
[icode
].n_operands
;
2340 recog_data
.n_alternatives
= insn_data
[icode
].n_alternatives
;
2341 recog_data
.n_dups
= insn_data
[icode
].n_dups
;
2343 insn_extract (insn
);
2345 for (i
= 0; i
< noperands
; i
++)
2347 recog_data
.constraints
[i
] = insn_data
[icode
].operand
[i
].constraint
;
2348 recog_data
.is_operator
[i
] = insn_data
[icode
].operand
[i
].is_operator
;
2349 recog_data
.operand_mode
[i
] = insn_data
[icode
].operand
[i
].mode
;
2350 /* VOIDmode match_operands gets mode from their real operand. */
2351 if (recog_data
.operand_mode
[i
] == VOIDmode
)
2352 recog_data
.operand_mode
[i
] = GET_MODE (recog_data
.operand
[i
]);
2355 for (i
= 0; i
< noperands
; i
++)
2356 recog_data
.operand_type
[i
]
2357 = (recog_data
.constraints
[i
][0] == '=' ? OP_OUT
2358 : recog_data
.constraints
[i
][0] == '+' ? OP_INOUT
2361 gcc_assert (recog_data
.n_alternatives
<= MAX_RECOG_ALTERNATIVES
);
2363 recog_data
.insn
= NULL
;
2364 which_alternative
= -1;
2367 /* Fill in OP_ALT_BASE for an instruction that has N_OPERANDS operands,
2368 N_ALTERNATIVES alternatives and constraint strings CONSTRAINTS.
2369 OP_ALT_BASE has N_ALTERNATIVES * N_OPERANDS entries and CONSTRAINTS
2370 has N_OPERANDS entries. */
2373 preprocess_constraints (int n_operands
, int n_alternatives
,
2374 const char **constraints
,
2375 operand_alternative
*op_alt_base
)
2377 for (int i
= 0; i
< n_operands
; i
++)
2380 struct operand_alternative
*op_alt
;
2381 const char *p
= constraints
[i
];
2383 op_alt
= op_alt_base
;
2385 for (j
= 0; j
< n_alternatives
; j
++, op_alt
+= n_operands
)
2387 op_alt
[i
].cl
= NO_REGS
;
2388 op_alt
[i
].constraint
= p
;
2389 op_alt
[i
].matches
= -1;
2390 op_alt
[i
].matched
= -1;
2392 if (*p
== '\0' || *p
== ',')
2394 op_alt
[i
].anything_ok
= 1;
2404 while (c
!= ',' && c
!= '\0');
2405 if (c
== ',' || c
== '\0')
2414 op_alt
[i
].reject
+= 6;
2417 op_alt
[i
].reject
+= 600;
2420 op_alt
[i
].earlyclobber
= 1;
2423 case '0': case '1': case '2': case '3': case '4':
2424 case '5': case '6': case '7': case '8': case '9':
2427 op_alt
[i
].matches
= strtoul (p
, &end
, 10);
2428 op_alt
[op_alt
[i
].matches
].matched
= i
;
2434 op_alt
[i
].anything_ok
= 1;
2439 reg_class_subunion
[(int) op_alt
[i
].cl
][(int) GENERAL_REGS
];
2443 enum constraint_num cn
= lookup_constraint (p
);
2445 switch (get_constraint_type (cn
))
2448 cl
= reg_class_for_constraint (cn
);
2450 op_alt
[i
].cl
= reg_class_subunion
[op_alt
[i
].cl
][cl
];
2457 op_alt
[i
].memory_ok
= 1;
2461 op_alt
[i
].is_address
= 1;
2463 = (reg_class_subunion
2464 [(int) op_alt
[i
].cl
]
2465 [(int) base_reg_class (VOIDmode
, ADDR_SPACE_GENERIC
,
2466 ADDRESS
, SCRATCH
)]);
2474 p
+= CONSTRAINT_LEN (c
, p
);
2480 /* Return an array of operand_alternative instructions for
2481 instruction ICODE. */
2483 const operand_alternative
*
2484 preprocess_insn_constraints (int icode
)
2486 gcc_checking_assert (IN_RANGE (icode
, 0, LAST_INSN_CODE
));
2487 if (this_target_recog
->x_op_alt
[icode
])
2488 return this_target_recog
->x_op_alt
[icode
];
2490 int n_operands
= insn_data
[icode
].n_operands
;
2491 if (n_operands
== 0)
2493 /* Always provide at least one alternative so that which_op_alt ()
2494 works correctly. If the instruction has 0 alternatives (i.e. all
2495 constraint strings are empty) then each operand in this alternative
2496 will have anything_ok set. */
2497 int n_alternatives
= MAX (insn_data
[icode
].n_alternatives
, 1);
2498 int n_entries
= n_operands
* n_alternatives
;
2500 operand_alternative
*op_alt
= XCNEWVEC (operand_alternative
, n_entries
);
2501 const char **constraints
= XALLOCAVEC (const char *, n_operands
);
2503 for (int i
= 0; i
< n_operands
; ++i
)
2504 constraints
[i
] = insn_data
[icode
].operand
[i
].constraint
;
2505 preprocess_constraints (n_operands
, n_alternatives
, constraints
, op_alt
);
2507 this_target_recog
->x_op_alt
[icode
] = op_alt
;
2511 /* After calling extract_insn, you can use this function to extract some
2512 information from the constraint strings into a more usable form.
2513 The collected data is stored in recog_op_alt. */
2516 preprocess_constraints (rtx_insn
*insn
)
2518 int icode
= INSN_CODE (insn
);
2520 recog_op_alt
= preprocess_insn_constraints (icode
);
2523 int n_operands
= recog_data
.n_operands
;
2524 int n_alternatives
= recog_data
.n_alternatives
;
2525 int n_entries
= n_operands
* n_alternatives
;
2526 memset (asm_op_alt
, 0, n_entries
* sizeof (operand_alternative
));
2527 preprocess_constraints (n_operands
, n_alternatives
,
2528 recog_data
.constraints
, asm_op_alt
);
2529 recog_op_alt
= asm_op_alt
;
2533 /* Check the operands of an insn against the insn's operand constraints
2534 and return 1 if they match any of the alternatives in ALTERNATIVES.
2536 The information about the insn's operands, constraints, operand modes
2537 etc. is obtained from the global variables set up by extract_insn.
2539 WHICH_ALTERNATIVE is set to a number which indicates which
2540 alternative of constraints was matched: 0 for the first alternative,
2541 1 for the next, etc.
2543 In addition, when two operands are required to match
2544 and it happens that the output operand is (reg) while the
2545 input operand is --(reg) or ++(reg) (a pre-inc or pre-dec),
2546 make the output operand look like the input.
2547 This is because the output operand is the one the template will print.
2549 This is used in final, just before printing the assembler code and by
2550 the routines that determine an insn's attribute.
2552 If STRICT is a positive nonzero value, it means that we have been
2553 called after reload has been completed. In that case, we must
2554 do all checks strictly. If it is zero, it means that we have been called
2555 before reload has completed. In that case, we first try to see if we can
2556 find an alternative that matches strictly. If not, we try again, this
2557 time assuming that reload will fix up the insn. This provides a "best
2558 guess" for the alternative and is used to compute attributes of insns prior
2559 to reload. A negative value of STRICT is used for this internal call. */
2567 constrain_operands (int strict
, alternative_mask alternatives
)
2569 const char *constraints
[MAX_RECOG_OPERANDS
];
2570 int matching_operands
[MAX_RECOG_OPERANDS
];
2571 int earlyclobber
[MAX_RECOG_OPERANDS
];
2574 struct funny_match funny_match
[MAX_RECOG_OPERANDS
];
2575 int funny_match_index
;
2577 which_alternative
= 0;
2578 if (recog_data
.n_operands
== 0 || recog_data
.n_alternatives
== 0)
2581 for (c
= 0; c
< recog_data
.n_operands
; c
++)
2583 constraints
[c
] = recog_data
.constraints
[c
];
2584 matching_operands
[c
] = -1;
2589 int seen_earlyclobber_at
= -1;
2592 funny_match_index
= 0;
2594 if (!TEST_BIT (alternatives
, which_alternative
))
2598 for (i
= 0; i
< recog_data
.n_operands
; i
++)
2599 constraints
[i
] = skip_alternative (constraints
[i
]);
2601 which_alternative
++;
2605 for (opno
= 0; opno
< recog_data
.n_operands
; opno
++)
2607 rtx op
= recog_data
.operand
[opno
];
2608 machine_mode mode
= GET_MODE (op
);
2609 const char *p
= constraints
[opno
];
2615 earlyclobber
[opno
] = 0;
2617 /* A unary operator may be accepted by the predicate, but it
2618 is irrelevant for matching constraints. */
2622 if (GET_CODE (op
) == SUBREG
)
2624 if (REG_P (SUBREG_REG (op
))
2625 && REGNO (SUBREG_REG (op
)) < FIRST_PSEUDO_REGISTER
)
2626 offset
= subreg_regno_offset (REGNO (SUBREG_REG (op
)),
2627 GET_MODE (SUBREG_REG (op
)),
2630 op
= SUBREG_REG (op
);
2633 /* An empty constraint or empty alternative
2634 allows anything which matched the pattern. */
2635 if (*p
== 0 || *p
== ',')
2639 switch (c
= *p
, len
= CONSTRAINT_LEN (c
, p
), c
)
2649 /* Ignore rest of this alternative as far as
2650 constraint checking is concerned. */
2653 while (*p
&& *p
!= ',');
2658 earlyclobber
[opno
] = 1;
2659 if (seen_earlyclobber_at
< 0)
2660 seen_earlyclobber_at
= opno
;
2663 case '0': case '1': case '2': case '3': case '4':
2664 case '5': case '6': case '7': case '8': case '9':
2666 /* This operand must be the same as a previous one.
2667 This kind of constraint is used for instructions such
2668 as add when they take only two operands.
2670 Note that the lower-numbered operand is passed first.
2672 If we are not testing strictly, assume that this
2673 constraint will be satisfied. */
2678 match
= strtoul (p
, &end
, 10);
2685 rtx op1
= recog_data
.operand
[match
];
2686 rtx op2
= recog_data
.operand
[opno
];
2688 /* A unary operator may be accepted by the predicate,
2689 but it is irrelevant for matching constraints. */
2691 op1
= XEXP (op1
, 0);
2693 op2
= XEXP (op2
, 0);
2695 val
= operands_match_p (op1
, op2
);
2698 matching_operands
[opno
] = match
;
2699 matching_operands
[match
] = opno
;
2704 /* If output is *x and input is *--x, arrange later
2705 to change the output to *--x as well, since the
2706 output op is the one that will be printed. */
2707 if (val
== 2 && strict
> 0)
2709 funny_match
[funny_match_index
].this_op
= opno
;
2710 funny_match
[funny_match_index
++].other
= match
;
2717 /* p is used for address_operands. When we are called by
2718 gen_reload, no one will have checked that the address is
2719 strictly valid, i.e., that all pseudos requiring hard regs
2720 have gotten them. */
2722 || (strict_memory_address_p (recog_data
.operand_mode
[opno
],
2727 /* No need to check general_operand again;
2728 it was done in insn-recog.c. Well, except that reload
2729 doesn't check the validity of its replacements, but
2730 that should only matter when there's a bug. */
2732 /* Anything goes unless it is a REG and really has a hard reg
2733 but the hard reg is not in the class GENERAL_REGS. */
2737 || GENERAL_REGS
== ALL_REGS
2738 || (reload_in_progress
2739 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
)
2740 || reg_fits_class_p (op
, GENERAL_REGS
, offset
, mode
))
2743 else if (strict
< 0 || general_operand (op
, mode
))
2749 enum constraint_num cn
= lookup_constraint (p
);
2750 enum reg_class cl
= reg_class_for_constraint (cn
);
2756 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
)
2757 || (strict
== 0 && GET_CODE (op
) == SCRATCH
)
2759 && reg_fits_class_p (op
, cl
, offset
, mode
)))
2763 else if (constraint_satisfied_p (op
, cn
))
2766 else if (insn_extra_memory_constraint (cn
)
2767 /* Every memory operand can be reloaded to fit. */
2768 && ((strict
< 0 && MEM_P (op
))
2769 /* Before reload, accept what reload can turn
2771 || (strict
< 0 && CONSTANT_P (op
))
2772 /* Before reload, accept a pseudo,
2773 since LRA can turn it into a mem. */
2774 || (strict
< 0 && targetm
.lra_p () && REG_P (op
)
2775 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
)
2776 /* During reload, accept a pseudo */
2777 || (reload_in_progress
&& REG_P (op
)
2778 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
)))
2780 else if (insn_extra_address_constraint (cn
)
2781 /* Every address operand can be reloaded to fit. */
2784 /* Cater to architectures like IA-64 that define extra memory
2785 constraints without using define_memory_constraint. */
2786 else if (reload_in_progress
2788 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
2789 && reg_renumber
[REGNO (op
)] < 0
2790 && reg_equiv_mem (REGNO (op
)) != 0
2791 && constraint_satisfied_p
2792 (reg_equiv_mem (REGNO (op
)), cn
))
2797 while (p
+= len
, c
);
2799 constraints
[opno
] = p
;
2800 /* If this operand did not win somehow,
2801 this alternative loses. */
2805 /* This alternative won; the operands are ok.
2806 Change whichever operands this alternative says to change. */
2811 /* See if any earlyclobber operand conflicts with some other
2814 if (strict
> 0 && seen_earlyclobber_at
>= 0)
2815 for (eopno
= seen_earlyclobber_at
;
2816 eopno
< recog_data
.n_operands
;
2818 /* Ignore earlyclobber operands now in memory,
2819 because we would often report failure when we have
2820 two memory operands, one of which was formerly a REG. */
2821 if (earlyclobber
[eopno
]
2822 && REG_P (recog_data
.operand
[eopno
]))
2823 for (opno
= 0; opno
< recog_data
.n_operands
; opno
++)
2824 if ((MEM_P (recog_data
.operand
[opno
])
2825 || recog_data
.operand_type
[opno
] != OP_OUT
)
2827 /* Ignore things like match_operator operands. */
2828 && *recog_data
.constraints
[opno
] != 0
2829 && ! (matching_operands
[opno
] == eopno
2830 && operands_match_p (recog_data
.operand
[opno
],
2831 recog_data
.operand
[eopno
]))
2832 && ! safe_from_earlyclobber (recog_data
.operand
[opno
],
2833 recog_data
.operand
[eopno
]))
2838 while (--funny_match_index
>= 0)
2840 recog_data
.operand
[funny_match
[funny_match_index
].other
]
2841 = recog_data
.operand
[funny_match
[funny_match_index
].this_op
];
2845 /* For operands without < or > constraints reject side-effects. */
2846 if (recog_data
.is_asm
)
2848 for (opno
= 0; opno
< recog_data
.n_operands
; opno
++)
2849 if (MEM_P (recog_data
.operand
[opno
]))
2850 switch (GET_CODE (XEXP (recog_data
.operand
[opno
], 0)))
2858 if (strchr (recog_data
.constraints
[opno
], '<') == NULL
2859 && strchr (recog_data
.constraints
[opno
], '>')
2872 which_alternative
++;
2874 while (which_alternative
< recog_data
.n_alternatives
);
2876 which_alternative
= -1;
2877 /* If we are about to reject this, but we are not to test strictly,
2878 try a very loose test. Only return failure if it fails also. */
2880 return constrain_operands (-1, alternatives
);
2885 /* Return true iff OPERAND (assumed to be a REG rtx)
2886 is a hard reg in class CLASS when its regno is offset by OFFSET
2887 and changed to mode MODE.
2888 If REG occupies multiple hard regs, all of them must be in CLASS. */
2891 reg_fits_class_p (const_rtx operand
, reg_class_t cl
, int offset
,
2894 unsigned int regno
= REGNO (operand
);
2899 /* Regno must not be a pseudo register. Offset may be negative. */
2900 return (HARD_REGISTER_NUM_P (regno
)
2901 && HARD_REGISTER_NUM_P (regno
+ offset
)
2902 && in_hard_reg_set_p (reg_class_contents
[(int) cl
], mode
,
2906 /* Split single instruction. Helper function for split_all_insns and
2907 split_all_insns_noflow. Return last insn in the sequence if successful,
2908 or NULL if unsuccessful. */
2911 split_insn (rtx_insn
*insn
)
2913 /* Split insns here to get max fine-grain parallelism. */
2914 rtx_insn
*first
= PREV_INSN (insn
);
2915 rtx_insn
*last
= try_split (PATTERN (insn
), insn
, 1);
2916 rtx insn_set
, last_set
, note
;
2921 /* If the original instruction was a single set that was known to be
2922 equivalent to a constant, see if we can say the same about the last
2923 instruction in the split sequence. The two instructions must set
2924 the same destination. */
2925 insn_set
= single_set (insn
);
2928 last_set
= single_set (last
);
2929 if (last_set
&& rtx_equal_p (SET_DEST (last_set
), SET_DEST (insn_set
)))
2931 note
= find_reg_equal_equiv_note (insn
);
2932 if (note
&& CONSTANT_P (XEXP (note
, 0)))
2933 set_unique_reg_note (last
, REG_EQUAL
, XEXP (note
, 0));
2934 else if (CONSTANT_P (SET_SRC (insn_set
)))
2935 set_unique_reg_note (last
, REG_EQUAL
,
2936 copy_rtx (SET_SRC (insn_set
)));
2940 /* try_split returns the NOTE that INSN became. */
2941 SET_INSN_DELETED (insn
);
2943 /* ??? Coddle to md files that generate subregs in post-reload
2944 splitters instead of computing the proper hard register. */
2945 if (reload_completed
&& first
!= last
)
2947 first
= NEXT_INSN (first
);
2951 cleanup_subreg_operands (first
);
2954 first
= NEXT_INSN (first
);
2961 /* Split all insns in the function. If UPD_LIFE, update life info after. */
2964 split_all_insns (void)
2970 blocks
= sbitmap_alloc (last_basic_block_for_fn (cfun
));
2971 bitmap_clear (blocks
);
2974 FOR_EACH_BB_REVERSE_FN (bb
, cfun
)
2976 rtx_insn
*insn
, *next
;
2977 bool finish
= false;
2979 rtl_profile_for_bb (bb
);
2980 for (insn
= BB_HEAD (bb
); !finish
; insn
= next
)
2982 /* Can't use `next_real_insn' because that might go across
2983 CODE_LABELS and short-out basic blocks. */
2984 next
= NEXT_INSN (insn
);
2985 finish
= (insn
== BB_END (bb
));
2988 rtx set
= single_set (insn
);
2990 /* Don't split no-op move insns. These should silently
2991 disappear later in final. Splitting such insns would
2992 break the code that handles LIBCALL blocks. */
2993 if (set
&& set_noop_p (set
))
2995 /* Nops get in the way while scheduling, so delete them
2996 now if register allocation has already been done. It
2997 is too risky to try to do this before register
2998 allocation, and there are unlikely to be very many
2999 nops then anyways. */
3000 if (reload_completed
)
3001 delete_insn_and_edges (insn
);
3005 if (split_insn (insn
))
3007 bitmap_set_bit (blocks
, bb
->index
);
3015 default_rtl_profile ();
3017 find_many_sub_basic_blocks (blocks
);
3019 #ifdef ENABLE_CHECKING
3020 verify_flow_info ();
3023 sbitmap_free (blocks
);
3026 /* Same as split_all_insns, but do not expect CFG to be available.
3027 Used by machine dependent reorg passes. */
3030 split_all_insns_noflow (void)
3032 rtx_insn
*next
, *insn
;
3034 for (insn
= get_insns (); insn
; insn
= next
)
3036 next
= NEXT_INSN (insn
);
3039 /* Don't split no-op move insns. These should silently
3040 disappear later in final. Splitting such insns would
3041 break the code that handles LIBCALL blocks. */
3042 rtx set
= single_set (insn
);
3043 if (set
&& set_noop_p (set
))
3045 /* Nops get in the way while scheduling, so delete them
3046 now if register allocation has already been done. It
3047 is too risky to try to do this before register
3048 allocation, and there are unlikely to be very many
3051 ??? Should we use delete_insn when the CFG isn't valid? */
3052 if (reload_completed
)
3053 delete_insn_and_edges (insn
);
3062 #ifdef HAVE_peephole2
3063 struct peep2_insn_data
3069 static struct peep2_insn_data peep2_insn_data
[MAX_INSNS_PER_PEEP2
+ 1];
3070 static int peep2_current
;
3072 static bool peep2_do_rebuild_jump_labels
;
3073 static bool peep2_do_cleanup_cfg
;
3075 /* The number of instructions available to match a peep2. */
3076 int peep2_current_count
;
3078 /* A marker indicating the last insn of the block. The live_before regset
3079 for this element is correct, indicating DF_LIVE_OUT for the block. */
3080 #define PEEP2_EOB invalid_insn_rtx
3082 /* Wrap N to fit into the peep2_insn_data buffer. */
3085 peep2_buf_position (int n
)
3087 if (n
>= MAX_INSNS_PER_PEEP2
+ 1)
3088 n
-= MAX_INSNS_PER_PEEP2
+ 1;
3092 /* Return the Nth non-note insn after `current', or return NULL_RTX if it
3093 does not exist. Used by the recognizer to find the next insn to match
3094 in a multi-insn pattern. */
3097 peep2_next_insn (int n
)
3099 gcc_assert (n
<= peep2_current_count
);
3101 n
= peep2_buf_position (peep2_current
+ n
);
3103 return peep2_insn_data
[n
].insn
;
3106 /* Return true if REGNO is dead before the Nth non-note insn
3110 peep2_regno_dead_p (int ofs
, int regno
)
3112 gcc_assert (ofs
< MAX_INSNS_PER_PEEP2
+ 1);
3114 ofs
= peep2_buf_position (peep2_current
+ ofs
);
3116 gcc_assert (peep2_insn_data
[ofs
].insn
!= NULL_RTX
);
3118 return ! REGNO_REG_SET_P (peep2_insn_data
[ofs
].live_before
, regno
);
3121 /* Similarly for a REG. */
3124 peep2_reg_dead_p (int ofs
, rtx reg
)
3126 gcc_assert (ofs
< MAX_INSNS_PER_PEEP2
+ 1);
3128 ofs
= peep2_buf_position (peep2_current
+ ofs
);
3130 gcc_assert (peep2_insn_data
[ofs
].insn
!= NULL_RTX
);
3132 unsigned int end_regno
= END_REGNO (reg
);
3133 for (unsigned int regno
= REGNO (reg
); regno
< end_regno
; ++regno
)
3134 if (REGNO_REG_SET_P (peep2_insn_data
[ofs
].live_before
, regno
))
3139 /* Regno offset to be used in the register search. */
3140 static int search_ofs
;
3142 /* Try to find a hard register of mode MODE, matching the register class in
3143 CLASS_STR, which is available at the beginning of insn CURRENT_INSN and
3144 remains available until the end of LAST_INSN. LAST_INSN may be NULL_RTX,
3145 in which case the only condition is that the register must be available
3146 before CURRENT_INSN.
3147 Registers that already have bits set in REG_SET will not be considered.
3149 If an appropriate register is available, it will be returned and the
3150 corresponding bit(s) in REG_SET will be set; otherwise, NULL_RTX is
3154 peep2_find_free_register (int from
, int to
, const char *class_str
,
3155 machine_mode mode
, HARD_REG_SET
*reg_set
)
3162 gcc_assert (from
< MAX_INSNS_PER_PEEP2
+ 1);
3163 gcc_assert (to
< MAX_INSNS_PER_PEEP2
+ 1);
3165 from
= peep2_buf_position (peep2_current
+ from
);
3166 to
= peep2_buf_position (peep2_current
+ to
);
3168 gcc_assert (peep2_insn_data
[from
].insn
!= NULL_RTX
);
3169 REG_SET_TO_HARD_REG_SET (live
, peep2_insn_data
[from
].live_before
);
3173 gcc_assert (peep2_insn_data
[from
].insn
!= NULL_RTX
);
3175 /* Don't use registers set or clobbered by the insn. */
3176 FOR_EACH_INSN_DEF (def
, peep2_insn_data
[from
].insn
)
3177 SET_HARD_REG_BIT (live
, DF_REF_REGNO (def
));
3179 from
= peep2_buf_position (from
+ 1);
3182 cl
= reg_class_for_constraint (lookup_constraint (class_str
));
3184 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
3186 int raw_regno
, regno
, success
, j
;
3188 /* Distribute the free registers as much as possible. */
3189 raw_regno
= search_ofs
+ i
;
3190 if (raw_regno
>= FIRST_PSEUDO_REGISTER
)
3191 raw_regno
-= FIRST_PSEUDO_REGISTER
;
3192 #ifdef REG_ALLOC_ORDER
3193 regno
= reg_alloc_order
[raw_regno
];
3198 /* Can it support the mode we need? */
3199 if (! HARD_REGNO_MODE_OK (regno
, mode
))
3203 for (j
= 0; success
&& j
< hard_regno_nregs
[regno
][mode
]; j
++)
3205 /* Don't allocate fixed registers. */
3206 if (fixed_regs
[regno
+ j
])
3211 /* Don't allocate global registers. */
3212 if (global_regs
[regno
+ j
])
3217 /* Make sure the register is of the right class. */
3218 if (! TEST_HARD_REG_BIT (reg_class_contents
[cl
], regno
+ j
))
3223 /* And that we don't create an extra save/restore. */
3224 if (! call_used_regs
[regno
+ j
] && ! df_regs_ever_live_p (regno
+ j
))
3230 if (! targetm
.hard_regno_scratch_ok (regno
+ j
))
3236 /* And we don't clobber traceback for noreturn functions. */
3237 if ((regno
+ j
== FRAME_POINTER_REGNUM
3238 || regno
+ j
== HARD_FRAME_POINTER_REGNUM
)
3239 && (! reload_completed
|| frame_pointer_needed
))
3245 if (TEST_HARD_REG_BIT (*reg_set
, regno
+ j
)
3246 || TEST_HARD_REG_BIT (live
, regno
+ j
))
3255 add_to_hard_reg_set (reg_set
, mode
, regno
);
3257 /* Start the next search with the next register. */
3258 if (++raw_regno
>= FIRST_PSEUDO_REGISTER
)
3260 search_ofs
= raw_regno
;
3262 return gen_rtx_REG (mode
, regno
);
3270 /* Forget all currently tracked instructions, only remember current
3274 peep2_reinit_state (regset live
)
3278 /* Indicate that all slots except the last holds invalid data. */
3279 for (i
= 0; i
< MAX_INSNS_PER_PEEP2
; ++i
)
3280 peep2_insn_data
[i
].insn
= NULL
;
3281 peep2_current_count
= 0;
3283 /* Indicate that the last slot contains live_after data. */
3284 peep2_insn_data
[MAX_INSNS_PER_PEEP2
].insn
= PEEP2_EOB
;
3285 peep2_current
= MAX_INSNS_PER_PEEP2
;
3287 COPY_REG_SET (peep2_insn_data
[MAX_INSNS_PER_PEEP2
].live_before
, live
);
3290 /* While scanning basic block BB, we found a match of length MATCH_LEN,
3291 starting at INSN. Perform the replacement, removing the old insns and
3292 replacing them with ATTEMPT. Returns the last insn emitted, or NULL
3293 if the replacement is rejected. */
3296 peep2_attempt (basic_block bb
, rtx_insn
*insn
, int match_len
, rtx_insn
*attempt
)
3299 rtx_insn
*last
, *before_try
, *x
;
3300 rtx eh_note
, as_note
;
3303 bool was_call
= false;
3305 /* If we are splitting an RTX_FRAME_RELATED_P insn, do not allow it to
3306 match more than one insn, or to be split into more than one insn. */
3307 old_insn
= peep2_insn_data
[peep2_current
].insn
;
3308 if (RTX_FRAME_RELATED_P (old_insn
))
3310 bool any_note
= false;
3316 /* Look for one "active" insn. I.e. ignore any "clobber" insns that
3317 may be in the stream for the purpose of register allocation. */
3318 if (active_insn_p (attempt
))
3321 new_insn
= next_active_insn (attempt
);
3322 if (next_active_insn (new_insn
))
3325 /* We have a 1-1 replacement. Copy over any frame-related info. */
3326 RTX_FRAME_RELATED_P (new_insn
) = 1;
3328 /* Allow the backend to fill in a note during the split. */
3329 for (note
= REG_NOTES (new_insn
); note
; note
= XEXP (note
, 1))
3330 switch (REG_NOTE_KIND (note
))
3332 case REG_FRAME_RELATED_EXPR
:
3333 case REG_CFA_DEF_CFA
:
3334 case REG_CFA_ADJUST_CFA
:
3335 case REG_CFA_OFFSET
:
3336 case REG_CFA_REGISTER
:
3337 case REG_CFA_EXPRESSION
:
3338 case REG_CFA_RESTORE
:
3339 case REG_CFA_SET_VDRAP
:
3346 /* If the backend didn't supply a note, copy one over. */
3348 for (note
= REG_NOTES (old_insn
); note
; note
= XEXP (note
, 1))
3349 switch (REG_NOTE_KIND (note
))
3351 case REG_FRAME_RELATED_EXPR
:
3352 case REG_CFA_DEF_CFA
:
3353 case REG_CFA_ADJUST_CFA
:
3354 case REG_CFA_OFFSET
:
3355 case REG_CFA_REGISTER
:
3356 case REG_CFA_EXPRESSION
:
3357 case REG_CFA_RESTORE
:
3358 case REG_CFA_SET_VDRAP
:
3359 add_reg_note (new_insn
, REG_NOTE_KIND (note
), XEXP (note
, 0));
3366 /* If there still isn't a note, make sure the unwind info sees the
3367 same expression as before the split. */
3370 rtx old_set
, new_set
;
3372 /* The old insn had better have been simple, or annotated. */
3373 old_set
= single_set (old_insn
);
3374 gcc_assert (old_set
!= NULL
);
3376 new_set
= single_set (new_insn
);
3377 if (!new_set
|| !rtx_equal_p (new_set
, old_set
))
3378 add_reg_note (new_insn
, REG_FRAME_RELATED_EXPR
, old_set
);
3381 /* Copy prologue/epilogue status. This is required in order to keep
3382 proper placement of EPILOGUE_BEG and the DW_CFA_remember_state. */
3383 maybe_copy_prologue_epilogue_insn (old_insn
, new_insn
);
3386 /* If we are splitting a CALL_INSN, look for the CALL_INSN
3387 in SEQ and copy our CALL_INSN_FUNCTION_USAGE and other
3388 cfg-related call notes. */
3389 for (i
= 0; i
<= match_len
; ++i
)
3394 j
= peep2_buf_position (peep2_current
+ i
);
3395 old_insn
= peep2_insn_data
[j
].insn
;
3396 if (!CALL_P (old_insn
))
3401 while (new_insn
!= NULL_RTX
)
3403 if (CALL_P (new_insn
))
3405 new_insn
= NEXT_INSN (new_insn
);
3408 gcc_assert (new_insn
!= NULL_RTX
);
3410 CALL_INSN_FUNCTION_USAGE (new_insn
)
3411 = CALL_INSN_FUNCTION_USAGE (old_insn
);
3412 SIBLING_CALL_P (new_insn
) = SIBLING_CALL_P (old_insn
);
3414 for (note
= REG_NOTES (old_insn
);
3416 note
= XEXP (note
, 1))
3417 switch (REG_NOTE_KIND (note
))
3422 add_reg_note (new_insn
, REG_NOTE_KIND (note
),
3426 /* Discard all other reg notes. */
3430 /* Croak if there is another call in the sequence. */
3431 while (++i
<= match_len
)
3433 j
= peep2_buf_position (peep2_current
+ i
);
3434 old_insn
= peep2_insn_data
[j
].insn
;
3435 gcc_assert (!CALL_P (old_insn
));
3440 /* If we matched any instruction that had a REG_ARGS_SIZE, then
3441 move those notes over to the new sequence. */
3443 for (i
= match_len
; i
>= 0; --i
)
3445 int j
= peep2_buf_position (peep2_current
+ i
);
3446 old_insn
= peep2_insn_data
[j
].insn
;
3448 as_note
= find_reg_note (old_insn
, REG_ARGS_SIZE
, NULL
);
3453 i
= peep2_buf_position (peep2_current
+ match_len
);
3454 eh_note
= find_reg_note (peep2_insn_data
[i
].insn
, REG_EH_REGION
, NULL_RTX
);
3456 /* Replace the old sequence with the new. */
3457 rtx_insn
*peepinsn
= peep2_insn_data
[i
].insn
;
3458 last
= emit_insn_after_setloc (attempt
,
3459 peep2_insn_data
[i
].insn
,
3460 INSN_LOCATION (peepinsn
));
3461 before_try
= PREV_INSN (insn
);
3462 delete_insn_chain (insn
, peep2_insn_data
[i
].insn
, false);
3464 /* Re-insert the EH_REGION notes. */
3465 if (eh_note
|| (was_call
&& nonlocal_goto_handler_labels
))
3470 FOR_EACH_EDGE (eh_edge
, ei
, bb
->succs
)
3471 if (eh_edge
->flags
& (EDGE_EH
| EDGE_ABNORMAL_CALL
))
3475 copy_reg_eh_region_note_backward (eh_note
, last
, before_try
);
3478 for (x
= last
; x
!= before_try
; x
= PREV_INSN (x
))
3479 if (x
!= BB_END (bb
)
3480 && (can_throw_internal (x
)
3481 || can_nonlocal_goto (x
)))
3486 nfte
= split_block (bb
, x
);
3487 flags
= (eh_edge
->flags
3488 & (EDGE_EH
| EDGE_ABNORMAL
));
3490 flags
|= EDGE_ABNORMAL_CALL
;
3491 nehe
= make_edge (nfte
->src
, eh_edge
->dest
,
3494 nehe
->probability
= eh_edge
->probability
;
3496 = REG_BR_PROB_BASE
- nehe
->probability
;
3498 peep2_do_cleanup_cfg
|= purge_dead_edges (nfte
->dest
);
3503 /* Converting possibly trapping insn to non-trapping is
3504 possible. Zap dummy outgoing edges. */
3505 peep2_do_cleanup_cfg
|= purge_dead_edges (bb
);
3508 /* Re-insert the ARGS_SIZE notes. */
3510 fixup_args_size_notes (before_try
, last
, INTVAL (XEXP (as_note
, 0)));
3512 /* If we generated a jump instruction, it won't have
3513 JUMP_LABEL set. Recompute after we're done. */
3514 for (x
= last
; x
!= before_try
; x
= PREV_INSN (x
))
3517 peep2_do_rebuild_jump_labels
= true;
3524 /* After performing a replacement in basic block BB, fix up the life
3525 information in our buffer. LAST is the last of the insns that we
3526 emitted as a replacement. PREV is the insn before the start of
3527 the replacement. MATCH_LEN is the number of instructions that were
3528 matched, and which now need to be replaced in the buffer. */
3531 peep2_update_life (basic_block bb
, int match_len
, rtx_insn
*last
,
3534 int i
= peep2_buf_position (peep2_current
+ match_len
+ 1);
3538 INIT_REG_SET (&live
);
3539 COPY_REG_SET (&live
, peep2_insn_data
[i
].live_before
);
3541 gcc_assert (peep2_current_count
>= match_len
+ 1);
3542 peep2_current_count
-= match_len
+ 1;
3550 if (peep2_current_count
< MAX_INSNS_PER_PEEP2
)
3552 peep2_current_count
++;
3554 i
= MAX_INSNS_PER_PEEP2
;
3555 peep2_insn_data
[i
].insn
= x
;
3556 df_simulate_one_insn_backwards (bb
, x
, &live
);
3557 COPY_REG_SET (peep2_insn_data
[i
].live_before
, &live
);
3563 CLEAR_REG_SET (&live
);
3568 /* Add INSN, which is in BB, at the end of the peep2 insn buffer if possible.
3569 Return true if we added it, false otherwise. The caller will try to match
3570 peepholes against the buffer if we return false; otherwise it will try to
3571 add more instructions to the buffer. */
3574 peep2_fill_buffer (basic_block bb
, rtx_insn
*insn
, regset live
)
3578 /* Once we have filled the maximum number of insns the buffer can hold,
3579 allow the caller to match the insns against peepholes. We wait until
3580 the buffer is full in case the target has similar peepholes of different
3581 length; we always want to match the longest if possible. */
3582 if (peep2_current_count
== MAX_INSNS_PER_PEEP2
)
3585 /* If an insn has RTX_FRAME_RELATED_P set, do not allow it to be matched with
3586 any other pattern, lest it change the semantics of the frame info. */
3587 if (RTX_FRAME_RELATED_P (insn
))
3589 /* Let the buffer drain first. */
3590 if (peep2_current_count
> 0)
3592 /* Now the insn will be the only thing in the buffer. */
3595 pos
= peep2_buf_position (peep2_current
+ peep2_current_count
);
3596 peep2_insn_data
[pos
].insn
= insn
;
3597 COPY_REG_SET (peep2_insn_data
[pos
].live_before
, live
);
3598 peep2_current_count
++;
3600 df_simulate_one_insn_forwards (bb
, insn
, live
);
3604 /* Perform the peephole2 optimization pass. */
3607 peephole2_optimize (void)
3614 peep2_do_cleanup_cfg
= false;
3615 peep2_do_rebuild_jump_labels
= false;
3617 df_set_flags (DF_LR_RUN_DCE
);
3618 df_note_add_problem ();
3621 /* Initialize the regsets we're going to use. */
3622 for (i
= 0; i
< MAX_INSNS_PER_PEEP2
+ 1; ++i
)
3623 peep2_insn_data
[i
].live_before
= BITMAP_ALLOC (®_obstack
);
3625 live
= BITMAP_ALLOC (®_obstack
);
3627 FOR_EACH_BB_REVERSE_FN (bb
, cfun
)
3629 bool past_end
= false;
3632 rtl_profile_for_bb (bb
);
3634 /* Start up propagation. */
3635 bitmap_copy (live
, DF_LR_IN (bb
));
3636 df_simulate_initialize_forwards (bb
, live
);
3637 peep2_reinit_state (live
);
3639 insn
= BB_HEAD (bb
);
3642 rtx_insn
*attempt
, *head
;
3645 if (!past_end
&& !NONDEBUG_INSN_P (insn
))
3648 insn
= NEXT_INSN (insn
);
3649 if (insn
== NEXT_INSN (BB_END (bb
)))
3653 if (!past_end
&& peep2_fill_buffer (bb
, insn
, live
))
3656 /* If we did not fill an empty buffer, it signals the end of the
3658 if (peep2_current_count
== 0)
3661 /* The buffer filled to the current maximum, so try to match. */
3663 pos
= peep2_buf_position (peep2_current
+ peep2_current_count
);
3664 peep2_insn_data
[pos
].insn
= PEEP2_EOB
;
3665 COPY_REG_SET (peep2_insn_data
[pos
].live_before
, live
);
3667 /* Match the peephole. */
3668 head
= peep2_insn_data
[peep2_current
].insn
;
3669 attempt
= safe_as_a
<rtx_insn
*> (
3670 peephole2_insns (PATTERN (head
), head
, &match_len
));
3671 if (attempt
!= NULL
)
3673 rtx_insn
*last
= peep2_attempt (bb
, head
, match_len
, attempt
);
3676 peep2_update_life (bb
, match_len
, last
, PREV_INSN (attempt
));
3681 /* No match: advance the buffer by one insn. */
3682 peep2_current
= peep2_buf_position (peep2_current
+ 1);
3683 peep2_current_count
--;
3687 default_rtl_profile ();
3688 for (i
= 0; i
< MAX_INSNS_PER_PEEP2
+ 1; ++i
)
3689 BITMAP_FREE (peep2_insn_data
[i
].live_before
);
3691 if (peep2_do_rebuild_jump_labels
)
3692 rebuild_jump_labels (get_insns ());
3693 if (peep2_do_cleanup_cfg
)
3694 cleanup_cfg (CLEANUP_CFG_CHANGED
);
3696 #endif /* HAVE_peephole2 */
3698 /* Common predicates for use with define_bypass. */
3700 /* True if the dependency between OUT_INSN and IN_INSN is on the store
3701 data not the address operand(s) of the store. IN_INSN and OUT_INSN
3702 must be either a single_set or a PARALLEL with SETs inside. */
3705 store_data_bypass_p (rtx_insn
*out_insn
, rtx_insn
*in_insn
)
3707 rtx out_set
, in_set
;
3708 rtx out_pat
, in_pat
;
3709 rtx out_exp
, in_exp
;
3712 in_set
= single_set (in_insn
);
3715 if (!MEM_P (SET_DEST (in_set
)))
3718 out_set
= single_set (out_insn
);
3721 if (reg_mentioned_p (SET_DEST (out_set
), SET_DEST (in_set
)))
3726 out_pat
= PATTERN (out_insn
);
3728 if (GET_CODE (out_pat
) != PARALLEL
)
3731 for (i
= 0; i
< XVECLEN (out_pat
, 0); i
++)
3733 out_exp
= XVECEXP (out_pat
, 0, i
);
3735 if (GET_CODE (out_exp
) == CLOBBER
)
3738 gcc_assert (GET_CODE (out_exp
) == SET
);
3740 if (reg_mentioned_p (SET_DEST (out_exp
), SET_DEST (in_set
)))
3747 in_pat
= PATTERN (in_insn
);
3748 gcc_assert (GET_CODE (in_pat
) == PARALLEL
);
3750 for (i
= 0; i
< XVECLEN (in_pat
, 0); i
++)
3752 in_exp
= XVECEXP (in_pat
, 0, i
);
3754 if (GET_CODE (in_exp
) == CLOBBER
)
3757 gcc_assert (GET_CODE (in_exp
) == SET
);
3759 if (!MEM_P (SET_DEST (in_exp
)))
3762 out_set
= single_set (out_insn
);
3765 if (reg_mentioned_p (SET_DEST (out_set
), SET_DEST (in_exp
)))
3770 out_pat
= PATTERN (out_insn
);
3771 gcc_assert (GET_CODE (out_pat
) == PARALLEL
);
3773 for (j
= 0; j
< XVECLEN (out_pat
, 0); j
++)
3775 out_exp
= XVECEXP (out_pat
, 0, j
);
3777 if (GET_CODE (out_exp
) == CLOBBER
)
3780 gcc_assert (GET_CODE (out_exp
) == SET
);
3782 if (reg_mentioned_p (SET_DEST (out_exp
), SET_DEST (in_exp
)))
3792 /* True if the dependency between OUT_INSN and IN_INSN is in the IF_THEN_ELSE
3793 condition, and not the THEN or ELSE branch. OUT_INSN may be either a single
3794 or multiple set; IN_INSN should be single_set for truth, but for convenience
3795 of insn categorization may be any JUMP or CALL insn. */
3798 if_test_bypass_p (rtx_insn
*out_insn
, rtx_insn
*in_insn
)
3800 rtx out_set
, in_set
;
3802 in_set
= single_set (in_insn
);
3805 gcc_assert (JUMP_P (in_insn
) || CALL_P (in_insn
));
3809 if (GET_CODE (SET_SRC (in_set
)) != IF_THEN_ELSE
)
3811 in_set
= SET_SRC (in_set
);
3813 out_set
= single_set (out_insn
);
3816 if (reg_mentioned_p (SET_DEST (out_set
), XEXP (in_set
, 1))
3817 || reg_mentioned_p (SET_DEST (out_set
), XEXP (in_set
, 2)))
3825 out_pat
= PATTERN (out_insn
);
3826 gcc_assert (GET_CODE (out_pat
) == PARALLEL
);
3828 for (i
= 0; i
< XVECLEN (out_pat
, 0); i
++)
3830 rtx exp
= XVECEXP (out_pat
, 0, i
);
3832 if (GET_CODE (exp
) == CLOBBER
)
3835 gcc_assert (GET_CODE (exp
) == SET
);
3837 if (reg_mentioned_p (SET_DEST (out_set
), XEXP (in_set
, 1))
3838 || reg_mentioned_p (SET_DEST (out_set
), XEXP (in_set
, 2)))
3847 rest_of_handle_peephole2 (void)
3849 #ifdef HAVE_peephole2
3850 peephole2_optimize ();
3857 const pass_data pass_data_peephole2
=
3859 RTL_PASS
, /* type */
3860 "peephole2", /* name */
3861 OPTGROUP_NONE
, /* optinfo_flags */
3862 TV_PEEPHOLE2
, /* tv_id */
3863 0, /* properties_required */
3864 0, /* properties_provided */
3865 0, /* properties_destroyed */
3866 0, /* todo_flags_start */
3867 TODO_df_finish
, /* todo_flags_finish */
3870 class pass_peephole2
: public rtl_opt_pass
3873 pass_peephole2 (gcc::context
*ctxt
)
3874 : rtl_opt_pass (pass_data_peephole2
, ctxt
)
3877 /* opt_pass methods: */
3878 /* The epiphany backend creates a second instance of this pass, so we need
3880 opt_pass
* clone () { return new pass_peephole2 (m_ctxt
); }
3881 virtual bool gate (function
*) { return (optimize
> 0 && flag_peephole2
); }
3882 virtual unsigned int execute (function
*)
3884 return rest_of_handle_peephole2 ();
3887 }; // class pass_peephole2
3892 make_pass_peephole2 (gcc::context
*ctxt
)
3894 return new pass_peephole2 (ctxt
);
3899 const pass_data pass_data_split_all_insns
=
3901 RTL_PASS
, /* type */
3902 "split1", /* name */
3903 OPTGROUP_NONE
, /* optinfo_flags */
3904 TV_NONE
, /* tv_id */
3905 0, /* properties_required */
3906 0, /* properties_provided */
3907 0, /* properties_destroyed */
3908 0, /* todo_flags_start */
3909 0, /* todo_flags_finish */
3912 class pass_split_all_insns
: public rtl_opt_pass
3915 pass_split_all_insns (gcc::context
*ctxt
)
3916 : rtl_opt_pass (pass_data_split_all_insns
, ctxt
)
3919 /* opt_pass methods: */
3920 /* The epiphany backend creates a second instance of this pass, so
3921 we need a clone method. */
3922 opt_pass
* clone () { return new pass_split_all_insns (m_ctxt
); }
3923 virtual unsigned int execute (function
*)
3929 }; // class pass_split_all_insns
3934 make_pass_split_all_insns (gcc::context
*ctxt
)
3936 return new pass_split_all_insns (ctxt
);
3940 rest_of_handle_split_after_reload (void)
3942 /* If optimizing, then go ahead and split insns now. */
3952 const pass_data pass_data_split_after_reload
=
3954 RTL_PASS
, /* type */
3955 "split2", /* name */
3956 OPTGROUP_NONE
, /* optinfo_flags */
3957 TV_NONE
, /* tv_id */
3958 0, /* properties_required */
3959 0, /* properties_provided */
3960 0, /* properties_destroyed */
3961 0, /* todo_flags_start */
3962 0, /* todo_flags_finish */
3965 class pass_split_after_reload
: public rtl_opt_pass
3968 pass_split_after_reload (gcc::context
*ctxt
)
3969 : rtl_opt_pass (pass_data_split_after_reload
, ctxt
)
3972 /* opt_pass methods: */
3973 virtual unsigned int execute (function
*)
3975 return rest_of_handle_split_after_reload ();
3978 }; // class pass_split_after_reload
3983 make_pass_split_after_reload (gcc::context
*ctxt
)
3985 return new pass_split_after_reload (ctxt
);
3990 const pass_data pass_data_split_before_regstack
=
3992 RTL_PASS
, /* type */
3993 "split3", /* name */
3994 OPTGROUP_NONE
, /* optinfo_flags */
3995 TV_NONE
, /* tv_id */
3996 0, /* properties_required */
3997 0, /* properties_provided */
3998 0, /* properties_destroyed */
3999 0, /* todo_flags_start */
4000 0, /* todo_flags_finish */
4003 class pass_split_before_regstack
: public rtl_opt_pass
4006 pass_split_before_regstack (gcc::context
*ctxt
)
4007 : rtl_opt_pass (pass_data_split_before_regstack
, ctxt
)
4010 /* opt_pass methods: */
4011 virtual bool gate (function
*);
4012 virtual unsigned int execute (function
*)
4018 }; // class pass_split_before_regstack
4021 pass_split_before_regstack::gate (function
*)
4023 #if HAVE_ATTR_length && defined (STACK_REGS)
4024 /* If flow2 creates new instructions which need splitting
4025 and scheduling after reload is not done, they might not be
4026 split until final which doesn't allow splitting
4027 if HAVE_ATTR_length. */
4028 # ifdef INSN_SCHEDULING
4029 return (optimize
&& !flag_schedule_insns_after_reload
);
4041 make_pass_split_before_regstack (gcc::context
*ctxt
)
4043 return new pass_split_before_regstack (ctxt
);
4047 rest_of_handle_split_before_sched2 (void)
4049 #ifdef INSN_SCHEDULING
4057 const pass_data pass_data_split_before_sched2
=
4059 RTL_PASS
, /* type */
4060 "split4", /* name */
4061 OPTGROUP_NONE
, /* optinfo_flags */
4062 TV_NONE
, /* tv_id */
4063 0, /* properties_required */
4064 0, /* properties_provided */
4065 0, /* properties_destroyed */
4066 0, /* todo_flags_start */
4067 0, /* todo_flags_finish */
4070 class pass_split_before_sched2
: public rtl_opt_pass
4073 pass_split_before_sched2 (gcc::context
*ctxt
)
4074 : rtl_opt_pass (pass_data_split_before_sched2
, ctxt
)
4077 /* opt_pass methods: */
4078 virtual bool gate (function
*)
4080 #ifdef INSN_SCHEDULING
4081 return optimize
> 0 && flag_schedule_insns_after_reload
;
4087 virtual unsigned int execute (function
*)
4089 return rest_of_handle_split_before_sched2 ();
4092 }; // class pass_split_before_sched2
4097 make_pass_split_before_sched2 (gcc::context
*ctxt
)
4099 return new pass_split_before_sched2 (ctxt
);
4104 const pass_data pass_data_split_for_shorten_branches
=
4106 RTL_PASS
, /* type */
4107 "split5", /* name */
4108 OPTGROUP_NONE
, /* optinfo_flags */
4109 TV_NONE
, /* tv_id */
4110 0, /* properties_required */
4111 0, /* properties_provided */
4112 0, /* properties_destroyed */
4113 0, /* todo_flags_start */
4114 0, /* todo_flags_finish */
4117 class pass_split_for_shorten_branches
: public rtl_opt_pass
4120 pass_split_for_shorten_branches (gcc::context
*ctxt
)
4121 : rtl_opt_pass (pass_data_split_for_shorten_branches
, ctxt
)
4124 /* opt_pass methods: */
4125 virtual bool gate (function
*)
4127 /* The placement of the splitting that we do for shorten_branches
4128 depends on whether regstack is used by the target or not. */
4129 #if HAVE_ATTR_length && !defined (STACK_REGS)
4136 virtual unsigned int execute (function
*)
4138 return split_all_insns_noflow ();
4141 }; // class pass_split_for_shorten_branches
4146 make_pass_split_for_shorten_branches (gcc::context
*ctxt
)
4148 return new pass_split_for_shorten_branches (ctxt
);
4151 /* (Re)initialize the target information after a change in target. */
4156 /* The information is zero-initialized, so we don't need to do anything
4157 first time round. */
4158 if (!this_target_recog
->x_initialized
)
4160 this_target_recog
->x_initialized
= true;
4163 memset (this_target_recog
->x_bool_attr_masks
, 0,
4164 sizeof (this_target_recog
->x_bool_attr_masks
));
4165 for (int i
= 0; i
< LAST_INSN_CODE
; ++i
)
4166 if (this_target_recog
->x_op_alt
[i
])
4168 free (this_target_recog
->x_op_alt
[i
]);
4169 this_target_recog
->x_op_alt
[i
] = 0;