1 /* Subroutines used by or related to instruction recognition.
2 Copyright (C) 1987-2015 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify it under
7 the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 3, or (at your option) any later
11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
23 #include "coretypes.h"
32 #include "rtl-error.h"
34 #include "insn-config.h"
35 #include "insn-attr.h"
36 #include "hard-reg-set.h"
39 #include "addresses.h"
44 #include "statistics.h"
54 #include "dominance.h"
58 #include "cfgcleanup.h"
59 #include "basic-block.h"
62 #include "tree-pass.h"
64 #include "insn-codes.h"
66 #ifndef STACK_POP_CODE
67 #if STACK_GROWS_DOWNWARD
68 #define STACK_POP_CODE POST_INC
70 #define STACK_POP_CODE POST_DEC
74 static void validate_replace_rtx_1 (rtx
*, rtx
, rtx
, rtx_insn
*, bool);
75 static void validate_replace_src_1 (rtx
*, void *);
76 static rtx_insn
*split_insn (rtx_insn
*);
78 struct target_recog default_target_recog
;
80 struct target_recog
*this_target_recog
= &default_target_recog
;
83 /* Nonzero means allow operands to be volatile.
84 This should be 0 if you are generating rtl, such as if you are calling
85 the functions in optabs.c and expmed.c (most of the time).
86 This should be 1 if all valid insns need to be recognized,
87 such as in reginfo.c and final.c and reload.c.
89 init_recog and init_recog_no_volatile are responsible for setting this. */
93 struct recog_data_d recog_data
;
95 /* Contains a vector of operand_alternative structures, such that
96 operand OP of alternative A is at index A * n_operands + OP.
97 Set up by preprocess_constraints. */
98 const operand_alternative
*recog_op_alt
;
100 /* Used to provide recog_op_alt for asms. */
101 static operand_alternative asm_op_alt
[MAX_RECOG_OPERANDS
102 * MAX_RECOG_ALTERNATIVES
];
104 /* On return from `constrain_operands', indicate which alternative
107 int which_alternative
;
109 /* Nonzero after end of reload pass.
110 Set to 1 or 0 by toplev.c.
111 Controls the significance of (SUBREG (MEM)). */
113 int reload_completed
;
115 /* Nonzero after thread_prologue_and_epilogue_insns has run. */
116 int epilogue_completed
;
118 /* Initialize data used by the function `recog'.
119 This must be called once in the compilation of a function
120 before any insn recognition may be done in the function. */
123 init_recog_no_volatile (void)
135 /* Return true if labels in asm operands BODY are LABEL_REFs. */
138 asm_labels_ok (rtx body
)
143 asmop
= extract_asm_operands (body
);
144 if (asmop
== NULL_RTX
)
147 for (i
= 0; i
< ASM_OPERANDS_LABEL_LENGTH (asmop
); i
++)
148 if (GET_CODE (ASM_OPERANDS_LABEL (asmop
, i
)) != LABEL_REF
)
154 /* Check that X is an insn-body for an `asm' with operands
155 and that the operands mentioned in it are legitimate. */
158 check_asm_operands (rtx x
)
162 const char **constraints
;
165 if (!asm_labels_ok (x
))
168 /* Post-reload, be more strict with things. */
169 if (reload_completed
)
171 /* ??? Doh! We've not got the wrapping insn. Cook one up. */
172 rtx_insn
*insn
= make_insn_raw (x
);
174 constrain_operands (1, get_enabled_alternatives (insn
));
175 return which_alternative
>= 0;
178 noperands
= asm_noperands (x
);
184 operands
= XALLOCAVEC (rtx
, noperands
);
185 constraints
= XALLOCAVEC (const char *, noperands
);
187 decode_asm_operands (x
, operands
, NULL
, constraints
, NULL
, NULL
);
189 for (i
= 0; i
< noperands
; i
++)
191 const char *c
= constraints
[i
];
194 if (! asm_operand_ok (operands
[i
], c
, constraints
))
201 /* Static data for the next two routines. */
203 typedef struct change_t
212 static change_t
*changes
;
213 static int changes_allocated
;
215 static int num_changes
= 0;
217 /* Validate a proposed change to OBJECT. LOC is the location in the rtl
218 at which NEW_RTX will be placed. If OBJECT is zero, no validation is done,
219 the change is simply made.
221 Two types of objects are supported: If OBJECT is a MEM, memory_address_p
222 will be called with the address and mode as parameters. If OBJECT is
223 an INSN, CALL_INSN, or JUMP_INSN, the insn will be re-recognized with
226 IN_GROUP is nonzero if this is part of a group of changes that must be
227 performed as a group. In that case, the changes will be stored. The
228 function `apply_change_group' will validate and apply the changes.
230 If IN_GROUP is zero, this is a single change. Try to recognize the insn
231 or validate the memory reference with the change applied. If the result
232 is not valid for the machine, suppress the change and return zero.
233 Otherwise, perform the change and return 1. */
236 validate_change_1 (rtx object
, rtx
*loc
, rtx new_rtx
, bool in_group
, bool unshare
)
240 if (old
== new_rtx
|| rtx_equal_p (old
, new_rtx
))
243 gcc_assert (in_group
!= 0 || num_changes
== 0);
247 /* Save the information describing this change. */
248 if (num_changes
>= changes_allocated
)
250 if (changes_allocated
== 0)
251 /* This value allows for repeated substitutions inside complex
252 indexed addresses, or changes in up to 5 insns. */
253 changes_allocated
= MAX_RECOG_OPERANDS
* 5;
255 changes_allocated
*= 2;
257 changes
= XRESIZEVEC (change_t
, changes
, changes_allocated
);
260 changes
[num_changes
].object
= object
;
261 changes
[num_changes
].loc
= loc
;
262 changes
[num_changes
].old
= old
;
263 changes
[num_changes
].unshare
= unshare
;
265 if (object
&& !MEM_P (object
))
267 /* Set INSN_CODE to force rerecognition of insn. Save old code in
269 changes
[num_changes
].old_code
= INSN_CODE (object
);
270 INSN_CODE (object
) = -1;
275 /* If we are making a group of changes, return 1. Otherwise, validate the
276 change group we made. */
281 return apply_change_group ();
284 /* Wrapper for validate_change_1 without the UNSHARE argument defaulting
288 validate_change (rtx object
, rtx
*loc
, rtx new_rtx
, bool in_group
)
290 return validate_change_1 (object
, loc
, new_rtx
, in_group
, false);
293 /* Wrapper for validate_change_1 without the UNSHARE argument defaulting
297 validate_unshare_change (rtx object
, rtx
*loc
, rtx new_rtx
, bool in_group
)
299 return validate_change_1 (object
, loc
, new_rtx
, in_group
, true);
303 /* Keep X canonicalized if some changes have made it non-canonical; only
304 modifies the operands of X, not (for example) its code. Simplifications
305 are not the job of this routine.
307 Return true if anything was changed. */
309 canonicalize_change_group (rtx_insn
*insn
, rtx x
)
311 if (COMMUTATIVE_P (x
)
312 && swap_commutative_operands_p (XEXP (x
, 0), XEXP (x
, 1)))
314 /* Oops, the caller has made X no longer canonical.
315 Let's redo the changes in the correct order. */
316 rtx tem
= XEXP (x
, 0);
317 validate_unshare_change (insn
, &XEXP (x
, 0), XEXP (x
, 1), 1);
318 validate_unshare_change (insn
, &XEXP (x
, 1), tem
, 1);
326 /* This subroutine of apply_change_group verifies whether the changes to INSN
327 were valid; i.e. whether INSN can still be recognized.
329 If IN_GROUP is true clobbers which have to be added in order to
330 match the instructions will be added to the current change group.
331 Otherwise the changes will take effect immediately. */
334 insn_invalid_p (rtx_insn
*insn
, bool in_group
)
336 rtx pat
= PATTERN (insn
);
337 int num_clobbers
= 0;
338 /* If we are before reload and the pattern is a SET, see if we can add
340 int icode
= recog (pat
, insn
,
341 (GET_CODE (pat
) == SET
342 && ! reload_completed
343 && ! reload_in_progress
)
344 ? &num_clobbers
: 0);
345 int is_asm
= icode
< 0 && asm_noperands (PATTERN (insn
)) >= 0;
348 /* If this is an asm and the operand aren't legal, then fail. Likewise if
349 this is not an asm and the insn wasn't recognized. */
350 if ((is_asm
&& ! check_asm_operands (PATTERN (insn
)))
351 || (!is_asm
&& icode
< 0))
354 /* If we have to add CLOBBERs, fail if we have to add ones that reference
355 hard registers since our callers can't know if they are live or not.
356 Otherwise, add them. */
357 if (num_clobbers
> 0)
361 if (added_clobbers_hard_reg_p (icode
))
364 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (num_clobbers
+ 1));
365 XVECEXP (newpat
, 0, 0) = pat
;
366 add_clobbers (newpat
, icode
);
368 validate_change (insn
, &PATTERN (insn
), newpat
, 1);
370 PATTERN (insn
) = pat
= newpat
;
373 /* After reload, verify that all constraints are satisfied. */
374 if (reload_completed
)
378 if (! constrain_operands (1, get_preferred_alternatives (insn
)))
382 INSN_CODE (insn
) = icode
;
386 /* Return number of changes made and not validated yet. */
388 num_changes_pending (void)
393 /* Tentatively apply the changes numbered NUM and up.
394 Return 1 if all changes are valid, zero otherwise. */
397 verify_changes (int num
)
400 rtx last_validated
= NULL_RTX
;
402 /* The changes have been applied and all INSN_CODEs have been reset to force
405 The changes are valid if we aren't given an object, or if we are
406 given a MEM and it still is a valid address, or if this is in insn
407 and it is recognized. In the latter case, if reload has completed,
408 we also require that the operands meet the constraints for
411 for (i
= num
; i
< num_changes
; i
++)
413 rtx object
= changes
[i
].object
;
415 /* If there is no object to test or if it is the same as the one we
416 already tested, ignore it. */
417 if (object
== 0 || object
== last_validated
)
422 if (! memory_address_addr_space_p (GET_MODE (object
),
424 MEM_ADDR_SPACE (object
)))
427 else if (/* changes[i].old might be zero, e.g. when putting a
428 REG_FRAME_RELATED_EXPR into a previously empty list. */
430 && REG_P (changes
[i
].old
)
431 && asm_noperands (PATTERN (object
)) > 0
432 && REG_EXPR (changes
[i
].old
) != NULL_TREE
433 && DECL_ASSEMBLER_NAME_SET_P (REG_EXPR (changes
[i
].old
))
434 && DECL_REGISTER (REG_EXPR (changes
[i
].old
)))
436 /* Don't allow changes of hard register operands to inline
437 assemblies if they have been defined as register asm ("x"). */
440 else if (DEBUG_INSN_P (object
))
442 else if (insn_invalid_p (as_a
<rtx_insn
*> (object
), true))
444 rtx pat
= PATTERN (object
);
446 /* Perhaps we couldn't recognize the insn because there were
447 extra CLOBBERs at the end. If so, try to re-recognize
448 without the last CLOBBER (later iterations will cause each of
449 them to be eliminated, in turn). But don't do this if we
450 have an ASM_OPERAND. */
451 if (GET_CODE (pat
) == PARALLEL
452 && GET_CODE (XVECEXP (pat
, 0, XVECLEN (pat
, 0) - 1)) == CLOBBER
453 && asm_noperands (PATTERN (object
)) < 0)
457 if (XVECLEN (pat
, 0) == 2)
458 newpat
= XVECEXP (pat
, 0, 0);
464 = gen_rtx_PARALLEL (VOIDmode
,
465 rtvec_alloc (XVECLEN (pat
, 0) - 1));
466 for (j
= 0; j
< XVECLEN (newpat
, 0); j
++)
467 XVECEXP (newpat
, 0, j
) = XVECEXP (pat
, 0, j
);
470 /* Add a new change to this group to replace the pattern
471 with this new pattern. Then consider this change
472 as having succeeded. The change we added will
473 cause the entire call to fail if things remain invalid.
475 Note that this can lose if a later change than the one
476 we are processing specified &XVECEXP (PATTERN (object), 0, X)
477 but this shouldn't occur. */
479 validate_change (object
, &PATTERN (object
), newpat
, 1);
482 else if (GET_CODE (pat
) == USE
|| GET_CODE (pat
) == CLOBBER
483 || GET_CODE (pat
) == VAR_LOCATION
)
484 /* If this insn is a CLOBBER or USE, it is always valid, but is
490 last_validated
= object
;
493 return (i
== num_changes
);
496 /* A group of changes has previously been issued with validate_change
497 and verified with verify_changes. Call df_insn_rescan for each of
498 the insn changed and clear num_changes. */
501 confirm_change_group (void)
504 rtx last_object
= NULL
;
506 for (i
= 0; i
< num_changes
; i
++)
508 rtx object
= changes
[i
].object
;
510 if (changes
[i
].unshare
)
511 *changes
[i
].loc
= copy_rtx (*changes
[i
].loc
);
513 /* Avoid unnecessary rescanning when multiple changes to same instruction
517 if (object
!= last_object
&& last_object
&& INSN_P (last_object
))
518 df_insn_rescan (as_a
<rtx_insn
*> (last_object
));
519 last_object
= object
;
523 if (last_object
&& INSN_P (last_object
))
524 df_insn_rescan (as_a
<rtx_insn
*> (last_object
));
528 /* Apply a group of changes previously issued with `validate_change'.
529 If all changes are valid, call confirm_change_group and return 1,
530 otherwise, call cancel_changes and return 0. */
533 apply_change_group (void)
535 if (verify_changes (0))
537 confirm_change_group ();
548 /* Return the number of changes so far in the current group. */
551 num_validated_changes (void)
556 /* Retract the changes numbered NUM and up. */
559 cancel_changes (int num
)
563 /* Back out all the changes. Do this in the opposite order in which
565 for (i
= num_changes
- 1; i
>= num
; i
--)
567 *changes
[i
].loc
= changes
[i
].old
;
568 if (changes
[i
].object
&& !MEM_P (changes
[i
].object
))
569 INSN_CODE (changes
[i
].object
) = changes
[i
].old_code
;
574 /* Reduce conditional compilation elsewhere. */
577 #define CODE_FOR_extv CODE_FOR_nothing
581 #define CODE_FOR_extzv CODE_FOR_nothing
584 /* A subroutine of validate_replace_rtx_1 that tries to simplify the resulting
588 simplify_while_replacing (rtx
*loc
, rtx to
, rtx_insn
*object
,
589 machine_mode op0_mode
)
592 enum rtx_code code
= GET_CODE (x
);
593 rtx new_rtx
= NULL_RTX
;
595 if (SWAPPABLE_OPERANDS_P (x
)
596 && swap_commutative_operands_p (XEXP (x
, 0), XEXP (x
, 1)))
598 validate_unshare_change (object
, loc
,
599 gen_rtx_fmt_ee (COMMUTATIVE_ARITH_P (x
) ? code
600 : swap_condition (code
),
601 GET_MODE (x
), XEXP (x
, 1),
607 /* Canonicalize arithmetics with all constant operands. */
608 switch (GET_RTX_CLASS (code
))
611 if (CONSTANT_P (XEXP (x
, 0)))
612 new_rtx
= simplify_unary_operation (code
, GET_MODE (x
), XEXP (x
, 0),
617 if (CONSTANT_P (XEXP (x
, 0)) && CONSTANT_P (XEXP (x
, 1)))
618 new_rtx
= simplify_binary_operation (code
, GET_MODE (x
), XEXP (x
, 0),
622 case RTX_COMM_COMPARE
:
623 if (CONSTANT_P (XEXP (x
, 0)) && CONSTANT_P (XEXP (x
, 1)))
624 new_rtx
= simplify_relational_operation (code
, GET_MODE (x
), op0_mode
,
625 XEXP (x
, 0), XEXP (x
, 1));
632 validate_change (object
, loc
, new_rtx
, 1);
639 /* If we have a PLUS whose second operand is now a CONST_INT, use
640 simplify_gen_binary to try to simplify it.
641 ??? We may want later to remove this, once simplification is
642 separated from this function. */
643 if (CONST_INT_P (XEXP (x
, 1)) && XEXP (x
, 1) == to
)
644 validate_change (object
, loc
,
646 (PLUS
, GET_MODE (x
), XEXP (x
, 0), XEXP (x
, 1)), 1);
649 if (CONST_SCALAR_INT_P (XEXP (x
, 1)))
650 validate_change (object
, loc
,
652 (PLUS
, GET_MODE (x
), XEXP (x
, 0),
653 simplify_gen_unary (NEG
,
654 GET_MODE (x
), XEXP (x
, 1),
659 if (GET_MODE (XEXP (x
, 0)) == VOIDmode
)
661 new_rtx
= simplify_gen_unary (code
, GET_MODE (x
), XEXP (x
, 0),
663 /* If any of the above failed, substitute in something that
664 we know won't be recognized. */
666 new_rtx
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
667 validate_change (object
, loc
, new_rtx
, 1);
671 /* All subregs possible to simplify should be simplified. */
672 new_rtx
= simplify_subreg (GET_MODE (x
), SUBREG_REG (x
), op0_mode
,
675 /* Subregs of VOIDmode operands are incorrect. */
676 if (!new_rtx
&& GET_MODE (SUBREG_REG (x
)) == VOIDmode
)
677 new_rtx
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
679 validate_change (object
, loc
, new_rtx
, 1);
683 /* If we are replacing a register with memory, try to change the memory
684 to be the mode required for memory in extract operations (this isn't
685 likely to be an insertion operation; if it was, nothing bad will
686 happen, we might just fail in some cases). */
688 if (MEM_P (XEXP (x
, 0))
689 && CONST_INT_P (XEXP (x
, 1))
690 && CONST_INT_P (XEXP (x
, 2))
691 && !mode_dependent_address_p (XEXP (XEXP (x
, 0), 0),
692 MEM_ADDR_SPACE (XEXP (x
, 0)))
693 && !MEM_VOLATILE_P (XEXP (x
, 0)))
695 machine_mode wanted_mode
= VOIDmode
;
696 machine_mode is_mode
= GET_MODE (XEXP (x
, 0));
697 int pos
= INTVAL (XEXP (x
, 2));
699 if (GET_CODE (x
) == ZERO_EXTRACT
&& HAVE_extzv
)
701 wanted_mode
= insn_data
[CODE_FOR_extzv
].operand
[1].mode
;
702 if (wanted_mode
== VOIDmode
)
703 wanted_mode
= word_mode
;
705 else if (GET_CODE (x
) == SIGN_EXTRACT
&& HAVE_extv
)
707 wanted_mode
= insn_data
[CODE_FOR_extv
].operand
[1].mode
;
708 if (wanted_mode
== VOIDmode
)
709 wanted_mode
= word_mode
;
712 /* If we have a narrower mode, we can do something. */
713 if (wanted_mode
!= VOIDmode
714 && GET_MODE_SIZE (wanted_mode
) < GET_MODE_SIZE (is_mode
))
716 int offset
= pos
/ BITS_PER_UNIT
;
719 /* If the bytes and bits are counted differently, we
720 must adjust the offset. */
721 if (BYTES_BIG_ENDIAN
!= BITS_BIG_ENDIAN
)
723 (GET_MODE_SIZE (is_mode
) - GET_MODE_SIZE (wanted_mode
) -
726 gcc_assert (GET_MODE_PRECISION (wanted_mode
)
727 == GET_MODE_BITSIZE (wanted_mode
));
728 pos
%= GET_MODE_BITSIZE (wanted_mode
);
730 newmem
= adjust_address_nv (XEXP (x
, 0), wanted_mode
, offset
);
732 validate_change (object
, &XEXP (x
, 2), GEN_INT (pos
), 1);
733 validate_change (object
, &XEXP (x
, 0), newmem
, 1);
744 /* Replace every occurrence of FROM in X with TO. Mark each change with
745 validate_change passing OBJECT. */
748 validate_replace_rtx_1 (rtx
*loc
, rtx from
, rtx to
, rtx_insn
*object
,
755 machine_mode op0_mode
= VOIDmode
;
756 int prev_changes
= num_changes
;
762 fmt
= GET_RTX_FORMAT (code
);
764 op0_mode
= GET_MODE (XEXP (x
, 0));
766 /* X matches FROM if it is the same rtx or they are both referring to the
767 same register in the same mode. Avoid calling rtx_equal_p unless the
768 operands look similar. */
771 || (REG_P (x
) && REG_P (from
)
772 && GET_MODE (x
) == GET_MODE (from
)
773 && REGNO (x
) == REGNO (from
))
774 || (GET_CODE (x
) == GET_CODE (from
) && GET_MODE (x
) == GET_MODE (from
)
775 && rtx_equal_p (x
, from
)))
777 validate_unshare_change (object
, loc
, to
, 1);
781 /* Call ourself recursively to perform the replacements.
782 We must not replace inside already replaced expression, otherwise we
783 get infinite recursion for replacements like (reg X)->(subreg (reg X))
784 so we must special case shared ASM_OPERANDS. */
786 if (GET_CODE (x
) == PARALLEL
)
788 for (j
= XVECLEN (x
, 0) - 1; j
>= 0; j
--)
790 if (j
&& GET_CODE (XVECEXP (x
, 0, j
)) == SET
791 && GET_CODE (SET_SRC (XVECEXP (x
, 0, j
))) == ASM_OPERANDS
)
793 /* Verify that operands are really shared. */
794 gcc_assert (ASM_OPERANDS_INPUT_VEC (SET_SRC (XVECEXP (x
, 0, 0)))
795 == ASM_OPERANDS_INPUT_VEC (SET_SRC (XVECEXP
797 validate_replace_rtx_1 (&SET_DEST (XVECEXP (x
, 0, j
)),
798 from
, to
, object
, simplify
);
801 validate_replace_rtx_1 (&XVECEXP (x
, 0, j
), from
, to
, object
,
806 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
809 validate_replace_rtx_1 (&XEXP (x
, i
), from
, to
, object
, simplify
);
810 else if (fmt
[i
] == 'E')
811 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
812 validate_replace_rtx_1 (&XVECEXP (x
, i
, j
), from
, to
, object
,
816 /* If we didn't substitute, there is nothing more to do. */
817 if (num_changes
== prev_changes
)
820 /* ??? The regmove is no more, so is this aberration still necessary? */
821 /* Allow substituted expression to have different mode. This is used by
822 regmove to change mode of pseudo register. */
823 if (fmt
[0] == 'e' && GET_MODE (XEXP (x
, 0)) != VOIDmode
)
824 op0_mode
= GET_MODE (XEXP (x
, 0));
826 /* Do changes needed to keep rtx consistent. Don't do any other
827 simplifications, as it is not our job. */
829 simplify_while_replacing (loc
, to
, object
, op0_mode
);
832 /* Try replacing every occurrence of FROM in subexpression LOC of INSN
833 with TO. After all changes have been made, validate by seeing
834 if INSN is still valid. */
837 validate_replace_rtx_subexp (rtx from
, rtx to
, rtx_insn
*insn
, rtx
*loc
)
839 validate_replace_rtx_1 (loc
, from
, to
, insn
, true);
840 return apply_change_group ();
843 /* Try replacing every occurrence of FROM in INSN with TO. After all
844 changes have been made, validate by seeing if INSN is still valid. */
847 validate_replace_rtx (rtx from
, rtx to
, rtx_insn
*insn
)
849 validate_replace_rtx_1 (&PATTERN (insn
), from
, to
, insn
, true);
850 return apply_change_group ();
853 /* Try replacing every occurrence of FROM in WHERE with TO. Assume that WHERE
854 is a part of INSN. After all changes have been made, validate by seeing if
856 validate_replace_rtx (from, to, insn) is equivalent to
857 validate_replace_rtx_part (from, to, &PATTERN (insn), insn). */
860 validate_replace_rtx_part (rtx from
, rtx to
, rtx
*where
, rtx_insn
*insn
)
862 validate_replace_rtx_1 (where
, from
, to
, insn
, true);
863 return apply_change_group ();
866 /* Same as above, but do not simplify rtx afterwards. */
868 validate_replace_rtx_part_nosimplify (rtx from
, rtx to
, rtx
*where
,
871 validate_replace_rtx_1 (where
, from
, to
, insn
, false);
872 return apply_change_group ();
876 /* Try replacing every occurrence of FROM in INSN with TO. This also
877 will replace in REG_EQUAL and REG_EQUIV notes. */
880 validate_replace_rtx_group (rtx from
, rtx to
, rtx_insn
*insn
)
883 validate_replace_rtx_1 (&PATTERN (insn
), from
, to
, insn
, true);
884 for (note
= REG_NOTES (insn
); note
; note
= XEXP (note
, 1))
885 if (REG_NOTE_KIND (note
) == REG_EQUAL
886 || REG_NOTE_KIND (note
) == REG_EQUIV
)
887 validate_replace_rtx_1 (&XEXP (note
, 0), from
, to
, insn
, true);
890 /* Function called by note_uses to replace used subexpressions. */
891 struct validate_replace_src_data
893 rtx from
; /* Old RTX */
894 rtx to
; /* New RTX */
895 rtx_insn
*insn
; /* Insn in which substitution is occurring. */
899 validate_replace_src_1 (rtx
*x
, void *data
)
901 struct validate_replace_src_data
*d
902 = (struct validate_replace_src_data
*) data
;
904 validate_replace_rtx_1 (x
, d
->from
, d
->to
, d
->insn
, true);
907 /* Try replacing every occurrence of FROM in INSN with TO, avoiding
911 validate_replace_src_group (rtx from
, rtx to
, rtx_insn
*insn
)
913 struct validate_replace_src_data d
;
918 note_uses (&PATTERN (insn
), validate_replace_src_1
, &d
);
921 /* Try simplify INSN.
922 Invoke simplify_rtx () on every SET_SRC and SET_DEST inside the INSN's
923 pattern and return true if something was simplified. */
926 validate_simplify_insn (rtx_insn
*insn
)
932 pat
= PATTERN (insn
);
934 if (GET_CODE (pat
) == SET
)
936 newpat
= simplify_rtx (SET_SRC (pat
));
937 if (newpat
&& !rtx_equal_p (SET_SRC (pat
), newpat
))
938 validate_change (insn
, &SET_SRC (pat
), newpat
, 1);
939 newpat
= simplify_rtx (SET_DEST (pat
));
940 if (newpat
&& !rtx_equal_p (SET_DEST (pat
), newpat
))
941 validate_change (insn
, &SET_DEST (pat
), newpat
, 1);
943 else if (GET_CODE (pat
) == PARALLEL
)
944 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
946 rtx s
= XVECEXP (pat
, 0, i
);
948 if (GET_CODE (XVECEXP (pat
, 0, i
)) == SET
)
950 newpat
= simplify_rtx (SET_SRC (s
));
951 if (newpat
&& !rtx_equal_p (SET_SRC (s
), newpat
))
952 validate_change (insn
, &SET_SRC (s
), newpat
, 1);
953 newpat
= simplify_rtx (SET_DEST (s
));
954 if (newpat
&& !rtx_equal_p (SET_DEST (s
), newpat
))
955 validate_change (insn
, &SET_DEST (s
), newpat
, 1);
958 return ((num_changes_pending () > 0) && (apply_change_group () > 0));
961 /* Return 1 if the insn using CC0 set by INSN does not contain
962 any ordered tests applied to the condition codes.
963 EQ and NE tests do not count. */
966 next_insn_tests_no_inequality (rtx_insn
*insn
)
968 rtx_insn
*next
= next_cc0_user (insn
);
970 /* If there is no next insn, we have to take the conservative choice. */
974 return (INSN_P (next
)
975 && ! inequality_comparisons_p (PATTERN (next
)));
978 /* Return 1 if OP is a valid general operand for machine mode MODE.
979 This is either a register reference, a memory reference,
980 or a constant. In the case of a memory reference, the address
981 is checked for general validity for the target machine.
983 Register and memory references must have mode MODE in order to be valid,
984 but some constants have no machine mode and are valid for any mode.
986 If MODE is VOIDmode, OP is checked for validity for whatever mode
989 The main use of this function is as a predicate in match_operand
990 expressions in the machine description. */
993 general_operand (rtx op
, machine_mode mode
)
995 enum rtx_code code
= GET_CODE (op
);
997 if (mode
== VOIDmode
)
998 mode
= GET_MODE (op
);
1000 /* Don't accept CONST_INT or anything similar
1001 if the caller wants something floating. */
1002 if (GET_MODE (op
) == VOIDmode
&& mode
!= VOIDmode
1003 && GET_MODE_CLASS (mode
) != MODE_INT
1004 && GET_MODE_CLASS (mode
) != MODE_PARTIAL_INT
)
1007 if (CONST_INT_P (op
)
1009 && trunc_int_for_mode (INTVAL (op
), mode
) != INTVAL (op
))
1012 if (CONSTANT_P (op
))
1013 return ((GET_MODE (op
) == VOIDmode
|| GET_MODE (op
) == mode
1014 || mode
== VOIDmode
)
1015 && (! flag_pic
|| LEGITIMATE_PIC_OPERAND_P (op
))
1016 && targetm
.legitimate_constant_p (mode
== VOIDmode
1020 /* Except for certain constants with VOIDmode, already checked for,
1021 OP's mode must match MODE if MODE specifies a mode. */
1023 if (GET_MODE (op
) != mode
)
1028 rtx sub
= SUBREG_REG (op
);
1030 #ifdef INSN_SCHEDULING
1031 /* On machines that have insn scheduling, we want all memory
1032 reference to be explicit, so outlaw paradoxical SUBREGs.
1033 However, we must allow them after reload so that they can
1034 get cleaned up by cleanup_subreg_operands. */
1035 if (!reload_completed
&& MEM_P (sub
)
1036 && GET_MODE_SIZE (mode
) > GET_MODE_SIZE (GET_MODE (sub
)))
1039 /* Avoid memories with nonzero SUBREG_BYTE, as offsetting the memory
1040 may result in incorrect reference. We should simplify all valid
1041 subregs of MEM anyway. But allow this after reload because we
1042 might be called from cleanup_subreg_operands.
1044 ??? This is a kludge. */
1045 if (!reload_completed
&& SUBREG_BYTE (op
) != 0
1049 #ifdef CANNOT_CHANGE_MODE_CLASS
1051 && REGNO (sub
) < FIRST_PSEUDO_REGISTER
1052 && REG_CANNOT_CHANGE_MODE_P (REGNO (sub
), GET_MODE (sub
), mode
)
1053 && GET_MODE_CLASS (GET_MODE (sub
)) != MODE_COMPLEX_INT
1054 && GET_MODE_CLASS (GET_MODE (sub
)) != MODE_COMPLEX_FLOAT
1055 /* LRA can generate some invalid SUBREGS just for matched
1056 operand reload presentation. LRA needs to treat them as
1058 && ! LRA_SUBREG_P (op
))
1062 /* FLOAT_MODE subregs can't be paradoxical. Combine will occasionally
1063 create such rtl, and we must reject it. */
1064 if (SCALAR_FLOAT_MODE_P (GET_MODE (op
))
1065 /* LRA can use subreg to store a floating point value in an
1066 integer mode. Although the floating point and the
1067 integer modes need the same number of hard registers, the
1068 size of floating point mode can be less than the integer
1070 && ! lra_in_progress
1071 && GET_MODE_SIZE (GET_MODE (op
)) > GET_MODE_SIZE (GET_MODE (sub
)))
1075 code
= GET_CODE (op
);
1079 return (REGNO (op
) >= FIRST_PSEUDO_REGISTER
1080 || in_hard_reg_set_p (operand_reg_set
, GET_MODE (op
), REGNO (op
)));
1084 rtx y
= XEXP (op
, 0);
1086 if (! volatile_ok
&& MEM_VOLATILE_P (op
))
1089 /* Use the mem's mode, since it will be reloaded thus. LRA can
1090 generate move insn with invalid addresses which is made valid
1091 and efficiently calculated by LRA through further numerous
1094 || memory_address_addr_space_p (GET_MODE (op
), y
, MEM_ADDR_SPACE (op
)))
1101 /* Return 1 if OP is a valid memory address for a memory reference
1104 The main use of this function is as a predicate in match_operand
1105 expressions in the machine description. */
1108 address_operand (rtx op
, machine_mode mode
)
1110 return memory_address_p (mode
, op
);
1113 /* Return 1 if OP is a register reference of mode MODE.
1114 If MODE is VOIDmode, accept a register in any mode.
1116 The main use of this function is as a predicate in match_operand
1117 expressions in the machine description. */
1120 register_operand (rtx op
, machine_mode mode
)
1122 if (GET_CODE (op
) == SUBREG
)
1124 rtx sub
= SUBREG_REG (op
);
1126 /* Before reload, we can allow (SUBREG (MEM...)) as a register operand
1127 because it is guaranteed to be reloaded into one.
1128 Just make sure the MEM is valid in itself.
1129 (Ideally, (SUBREG (MEM)...) should not exist after reload,
1130 but currently it does result from (SUBREG (REG)...) where the
1131 reg went on the stack.) */
1132 if (!REG_P (sub
) && (reload_completed
|| !MEM_P (sub
)))
1135 else if (!REG_P (op
))
1137 return general_operand (op
, mode
);
1140 /* Return 1 for a register in Pmode; ignore the tested mode. */
1143 pmode_register_operand (rtx op
, machine_mode mode ATTRIBUTE_UNUSED
)
1145 return register_operand (op
, Pmode
);
1148 /* Return 1 if OP should match a MATCH_SCRATCH, i.e., if it is a SCRATCH
1149 or a hard register. */
1152 scratch_operand (rtx op
, machine_mode mode
)
1154 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
1157 return (GET_CODE (op
) == SCRATCH
1160 || (REGNO (op
) < FIRST_PSEUDO_REGISTER
1161 && REGNO_REG_CLASS (REGNO (op
)) != NO_REGS
))));
1164 /* Return 1 if OP is a valid immediate operand for mode MODE.
1166 The main use of this function is as a predicate in match_operand
1167 expressions in the machine description. */
1170 immediate_operand (rtx op
, machine_mode mode
)
1172 /* Don't accept CONST_INT or anything similar
1173 if the caller wants something floating. */
1174 if (GET_MODE (op
) == VOIDmode
&& mode
!= VOIDmode
1175 && GET_MODE_CLASS (mode
) != MODE_INT
1176 && GET_MODE_CLASS (mode
) != MODE_PARTIAL_INT
)
1179 if (CONST_INT_P (op
)
1181 && trunc_int_for_mode (INTVAL (op
), mode
) != INTVAL (op
))
1184 return (CONSTANT_P (op
)
1185 && (GET_MODE (op
) == mode
|| mode
== VOIDmode
1186 || GET_MODE (op
) == VOIDmode
)
1187 && (! flag_pic
|| LEGITIMATE_PIC_OPERAND_P (op
))
1188 && targetm
.legitimate_constant_p (mode
== VOIDmode
1193 /* Returns 1 if OP is an operand that is a CONST_INT of mode MODE. */
1196 const_int_operand (rtx op
, machine_mode mode
)
1198 if (!CONST_INT_P (op
))
1201 if (mode
!= VOIDmode
1202 && trunc_int_for_mode (INTVAL (op
), mode
) != INTVAL (op
))
1208 #if TARGET_SUPPORTS_WIDE_INT
1209 /* Returns 1 if OP is an operand that is a CONST_INT or CONST_WIDE_INT
1212 const_scalar_int_operand (rtx op
, machine_mode mode
)
1214 if (!CONST_SCALAR_INT_P (op
))
1217 if (CONST_INT_P (op
))
1218 return const_int_operand (op
, mode
);
1220 if (mode
!= VOIDmode
)
1222 int prec
= GET_MODE_PRECISION (mode
);
1223 int bitsize
= GET_MODE_BITSIZE (mode
);
1225 if (CONST_WIDE_INT_NUNITS (op
) * HOST_BITS_PER_WIDE_INT
> bitsize
)
1228 if (prec
== bitsize
)
1232 /* Multiword partial int. */
1234 = CONST_WIDE_INT_ELT (op
, CONST_WIDE_INT_NUNITS (op
) - 1);
1235 return (sext_hwi (x
, prec
& (HOST_BITS_PER_WIDE_INT
- 1)) == x
);
1241 /* Returns 1 if OP is an operand that is a constant integer or constant
1242 floating-point number of MODE. */
1245 const_double_operand (rtx op
, machine_mode mode
)
1247 return (GET_CODE (op
) == CONST_DOUBLE
)
1248 && (GET_MODE (op
) == mode
|| mode
== VOIDmode
);
1251 /* Returns 1 if OP is an operand that is a constant integer or constant
1252 floating-point number of MODE. */
1255 const_double_operand (rtx op
, machine_mode mode
)
1257 /* Don't accept CONST_INT or anything similar
1258 if the caller wants something floating. */
1259 if (GET_MODE (op
) == VOIDmode
&& mode
!= VOIDmode
1260 && GET_MODE_CLASS (mode
) != MODE_INT
1261 && GET_MODE_CLASS (mode
) != MODE_PARTIAL_INT
)
1264 return ((CONST_DOUBLE_P (op
) || CONST_INT_P (op
))
1265 && (mode
== VOIDmode
|| GET_MODE (op
) == mode
1266 || GET_MODE (op
) == VOIDmode
));
1269 /* Return 1 if OP is a general operand that is not an immediate
1270 operand of mode MODE. */
1273 nonimmediate_operand (rtx op
, machine_mode mode
)
1275 return (general_operand (op
, mode
) && ! CONSTANT_P (op
));
1278 /* Return 1 if OP is a register reference or immediate value of mode MODE. */
1281 nonmemory_operand (rtx op
, machine_mode mode
)
1283 if (CONSTANT_P (op
))
1284 return immediate_operand (op
, mode
);
1285 return register_operand (op
, mode
);
1288 /* Return 1 if OP is a valid operand that stands for pushing a
1289 value of mode MODE onto the stack.
1291 The main use of this function is as a predicate in match_operand
1292 expressions in the machine description. */
1295 push_operand (rtx op
, machine_mode mode
)
1297 unsigned int rounded_size
= GET_MODE_SIZE (mode
);
1299 #ifdef PUSH_ROUNDING
1300 rounded_size
= PUSH_ROUNDING (rounded_size
);
1306 if (mode
!= VOIDmode
&& GET_MODE (op
) != mode
)
1311 if (rounded_size
== GET_MODE_SIZE (mode
))
1313 if (GET_CODE (op
) != STACK_PUSH_CODE
)
1318 if (GET_CODE (op
) != PRE_MODIFY
1319 || GET_CODE (XEXP (op
, 1)) != PLUS
1320 || XEXP (XEXP (op
, 1), 0) != XEXP (op
, 0)
1321 || !CONST_INT_P (XEXP (XEXP (op
, 1), 1))
1322 || INTVAL (XEXP (XEXP (op
, 1), 1))
1323 != ((STACK_GROWS_DOWNWARD
? -1 : 1) * (int) rounded_size
))
1327 return XEXP (op
, 0) == stack_pointer_rtx
;
1330 /* Return 1 if OP is a valid operand that stands for popping a
1331 value of mode MODE off the stack.
1333 The main use of this function is as a predicate in match_operand
1334 expressions in the machine description. */
1337 pop_operand (rtx op
, machine_mode mode
)
1342 if (mode
!= VOIDmode
&& GET_MODE (op
) != mode
)
1347 if (GET_CODE (op
) != STACK_POP_CODE
)
1350 return XEXP (op
, 0) == stack_pointer_rtx
;
1353 /* Return 1 if ADDR is a valid memory address
1354 for mode MODE in address space AS. */
1357 memory_address_addr_space_p (machine_mode mode ATTRIBUTE_UNUSED
,
1358 rtx addr
, addr_space_t as
)
1360 #ifdef GO_IF_LEGITIMATE_ADDRESS
1361 gcc_assert (ADDR_SPACE_GENERIC_P (as
));
1362 GO_IF_LEGITIMATE_ADDRESS (mode
, addr
, win
);
1368 return targetm
.addr_space
.legitimate_address_p (mode
, addr
, 0, as
);
1372 /* Return 1 if OP is a valid memory reference with mode MODE,
1373 including a valid address.
1375 The main use of this function is as a predicate in match_operand
1376 expressions in the machine description. */
1379 memory_operand (rtx op
, machine_mode mode
)
1383 if (! reload_completed
)
1384 /* Note that no SUBREG is a memory operand before end of reload pass,
1385 because (SUBREG (MEM...)) forces reloading into a register. */
1386 return MEM_P (op
) && general_operand (op
, mode
);
1388 if (mode
!= VOIDmode
&& GET_MODE (op
) != mode
)
1392 if (GET_CODE (inner
) == SUBREG
)
1393 inner
= SUBREG_REG (inner
);
1395 return (MEM_P (inner
) && general_operand (op
, mode
));
1398 /* Return 1 if OP is a valid indirect memory reference with mode MODE;
1399 that is, a memory reference whose address is a general_operand. */
1402 indirect_operand (rtx op
, machine_mode mode
)
1404 /* Before reload, a SUBREG isn't in memory (see memory_operand, above). */
1405 if (! reload_completed
1406 && GET_CODE (op
) == SUBREG
&& MEM_P (SUBREG_REG (op
)))
1408 int offset
= SUBREG_BYTE (op
);
1409 rtx inner
= SUBREG_REG (op
);
1411 if (mode
!= VOIDmode
&& GET_MODE (op
) != mode
)
1414 /* The only way that we can have a general_operand as the resulting
1415 address is if OFFSET is zero and the address already is an operand
1416 or if the address is (plus Y (const_int -OFFSET)) and Y is an
1419 return ((offset
== 0 && general_operand (XEXP (inner
, 0), Pmode
))
1420 || (GET_CODE (XEXP (inner
, 0)) == PLUS
1421 && CONST_INT_P (XEXP (XEXP (inner
, 0), 1))
1422 && INTVAL (XEXP (XEXP (inner
, 0), 1)) == -offset
1423 && general_operand (XEXP (XEXP (inner
, 0), 0), Pmode
)));
1427 && memory_operand (op
, mode
)
1428 && general_operand (XEXP (op
, 0), Pmode
));
1431 /* Return 1 if this is an ordered comparison operator (not including
1432 ORDERED and UNORDERED). */
1435 ordered_comparison_operator (rtx op
, machine_mode mode
)
1437 if (mode
!= VOIDmode
&& GET_MODE (op
) != mode
)
1439 switch (GET_CODE (op
))
1457 /* Return 1 if this is a comparison operator. This allows the use of
1458 MATCH_OPERATOR to recognize all the branch insns. */
1461 comparison_operator (rtx op
, machine_mode mode
)
1463 return ((mode
== VOIDmode
|| GET_MODE (op
) == mode
)
1464 && COMPARISON_P (op
));
1467 /* If BODY is an insn body that uses ASM_OPERANDS, return it. */
1470 extract_asm_operands (rtx body
)
1473 switch (GET_CODE (body
))
1479 /* Single output operand: BODY is (set OUTPUT (asm_operands ...)). */
1480 tmp
= SET_SRC (body
);
1481 if (GET_CODE (tmp
) == ASM_OPERANDS
)
1486 tmp
= XVECEXP (body
, 0, 0);
1487 if (GET_CODE (tmp
) == ASM_OPERANDS
)
1489 if (GET_CODE (tmp
) == SET
)
1491 tmp
= SET_SRC (tmp
);
1492 if (GET_CODE (tmp
) == ASM_OPERANDS
)
1503 /* If BODY is an insn body that uses ASM_OPERANDS,
1504 return the number of operands (both input and output) in the insn.
1505 Otherwise return -1. */
1508 asm_noperands (const_rtx body
)
1510 rtx asm_op
= extract_asm_operands (CONST_CAST_RTX (body
));
1516 if (GET_CODE (body
) == SET
)
1518 else if (GET_CODE (body
) == PARALLEL
)
1521 if (GET_CODE (XVECEXP (body
, 0, 0)) == SET
)
1523 /* Multiple output operands, or 1 output plus some clobbers:
1525 [(set OUTPUT (asm_operands ...))... (clobber (reg ...))...]. */
1526 /* Count backwards through CLOBBERs to determine number of SETs. */
1527 for (i
= XVECLEN (body
, 0); i
> 0; i
--)
1529 if (GET_CODE (XVECEXP (body
, 0, i
- 1)) == SET
)
1531 if (GET_CODE (XVECEXP (body
, 0, i
- 1)) != CLOBBER
)
1535 /* N_SETS is now number of output operands. */
1538 /* Verify that all the SETs we have
1539 came from a single original asm_operands insn
1540 (so that invalid combinations are blocked). */
1541 for (i
= 0; i
< n_sets
; i
++)
1543 rtx elt
= XVECEXP (body
, 0, i
);
1544 if (GET_CODE (elt
) != SET
)
1546 if (GET_CODE (SET_SRC (elt
)) != ASM_OPERANDS
)
1548 /* If these ASM_OPERANDS rtx's came from different original insns
1549 then they aren't allowed together. */
1550 if (ASM_OPERANDS_INPUT_VEC (SET_SRC (elt
))
1551 != ASM_OPERANDS_INPUT_VEC (asm_op
))
1557 /* 0 outputs, but some clobbers:
1558 body is [(asm_operands ...) (clobber (reg ...))...]. */
1559 /* Make sure all the other parallel things really are clobbers. */
1560 for (i
= XVECLEN (body
, 0) - 1; i
> 0; i
--)
1561 if (GET_CODE (XVECEXP (body
, 0, i
)) != CLOBBER
)
1566 return (ASM_OPERANDS_INPUT_LENGTH (asm_op
)
1567 + ASM_OPERANDS_LABEL_LENGTH (asm_op
) + n_sets
);
1570 /* Assuming BODY is an insn body that uses ASM_OPERANDS,
1571 copy its operands (both input and output) into the vector OPERANDS,
1572 the locations of the operands within the insn into the vector OPERAND_LOCS,
1573 and the constraints for the operands into CONSTRAINTS.
1574 Write the modes of the operands into MODES.
1575 Return the assembler-template.
1577 If MODES, OPERAND_LOCS, CONSTRAINTS or OPERANDS is 0,
1578 we don't store that info. */
1581 decode_asm_operands (rtx body
, rtx
*operands
, rtx
**operand_locs
,
1582 const char **constraints
, machine_mode
*modes
,
1585 int nbase
= 0, n
, i
;
1588 switch (GET_CODE (body
))
1591 /* Zero output asm: BODY is (asm_operands ...). */
1596 /* Single output asm: BODY is (set OUTPUT (asm_operands ...)). */
1597 asmop
= SET_SRC (body
);
1599 /* The output is in the SET.
1600 Its constraint is in the ASM_OPERANDS itself. */
1602 operands
[0] = SET_DEST (body
);
1604 operand_locs
[0] = &SET_DEST (body
);
1606 constraints
[0] = ASM_OPERANDS_OUTPUT_CONSTRAINT (asmop
);
1608 modes
[0] = GET_MODE (SET_DEST (body
));
1614 int nparallel
= XVECLEN (body
, 0); /* Includes CLOBBERs. */
1616 asmop
= XVECEXP (body
, 0, 0);
1617 if (GET_CODE (asmop
) == SET
)
1619 asmop
= SET_SRC (asmop
);
1621 /* At least one output, plus some CLOBBERs. The outputs are in
1622 the SETs. Their constraints are in the ASM_OPERANDS itself. */
1623 for (i
= 0; i
< nparallel
; i
++)
1625 if (GET_CODE (XVECEXP (body
, 0, i
)) == CLOBBER
)
1626 break; /* Past last SET */
1628 operands
[i
] = SET_DEST (XVECEXP (body
, 0, i
));
1630 operand_locs
[i
] = &SET_DEST (XVECEXP (body
, 0, i
));
1632 constraints
[i
] = XSTR (SET_SRC (XVECEXP (body
, 0, i
)), 1);
1634 modes
[i
] = GET_MODE (SET_DEST (XVECEXP (body
, 0, i
)));
1645 n
= ASM_OPERANDS_INPUT_LENGTH (asmop
);
1646 for (i
= 0; i
< n
; i
++)
1649 operand_locs
[nbase
+ i
] = &ASM_OPERANDS_INPUT (asmop
, i
);
1651 operands
[nbase
+ i
] = ASM_OPERANDS_INPUT (asmop
, i
);
1653 constraints
[nbase
+ i
] = ASM_OPERANDS_INPUT_CONSTRAINT (asmop
, i
);
1655 modes
[nbase
+ i
] = ASM_OPERANDS_INPUT_MODE (asmop
, i
);
1659 n
= ASM_OPERANDS_LABEL_LENGTH (asmop
);
1660 for (i
= 0; i
< n
; i
++)
1663 operand_locs
[nbase
+ i
] = &ASM_OPERANDS_LABEL (asmop
, i
);
1665 operands
[nbase
+ i
] = ASM_OPERANDS_LABEL (asmop
, i
);
1667 constraints
[nbase
+ i
] = "";
1669 modes
[nbase
+ i
] = Pmode
;
1673 *loc
= ASM_OPERANDS_SOURCE_LOCATION (asmop
);
1675 return ASM_OPERANDS_TEMPLATE (asmop
);
1678 /* Parse inline assembly string STRING and determine which operands are
1679 referenced by % markers. For the first NOPERANDS operands, set USED[I]
1680 to true if operand I is referenced.
1682 This is intended to distinguish barrier-like asms such as:
1684 asm ("" : "=m" (...));
1686 from real references such as:
1688 asm ("sw\t$0, %0" : "=m" (...)); */
1691 get_referenced_operands (const char *string
, bool *used
,
1692 unsigned int noperands
)
1694 memset (used
, 0, sizeof (bool) * noperands
);
1695 const char *p
= string
;
1701 /* A letter followed by a digit indicates an operand number. */
1702 if (ISALPHA (p
[0]) && ISDIGIT (p
[1]))
1707 unsigned long opnum
= strtoul (p
, &endptr
, 10);
1708 if (endptr
!= p
&& opnum
< noperands
)
1722 /* Check if an asm_operand matches its constraints.
1723 Return > 0 if ok, = 0 if bad, < 0 if inconclusive. */
1726 asm_operand_ok (rtx op
, const char *constraint
, const char **constraints
)
1730 bool incdec_ok
= false;
1733 /* Use constrain_operands after reload. */
1734 gcc_assert (!reload_completed
);
1736 /* Empty constraint string is the same as "X,...,X", i.e. X for as
1737 many alternatives as required to match the other operands. */
1738 if (*constraint
== '\0')
1743 enum constraint_num cn
;
1744 char c
= *constraint
;
1752 case '0': case '1': case '2': case '3': case '4':
1753 case '5': case '6': case '7': case '8': case '9':
1754 /* If caller provided constraints pointer, look up
1755 the matching constraint. Otherwise, our caller should have
1756 given us the proper matching constraint, but we can't
1757 actually fail the check if they didn't. Indicate that
1758 results are inconclusive. */
1762 unsigned long match
;
1764 match
= strtoul (constraint
, &end
, 10);
1766 result
= asm_operand_ok (op
, constraints
[match
], NULL
);
1767 constraint
= (const char *) end
;
1773 while (ISDIGIT (*constraint
));
1779 /* The rest of the compiler assumes that reloading the address
1780 of a MEM into a register will make it fit an 'o' constraint.
1781 That is, if it sees a MEM operand for an 'o' constraint,
1782 it assumes that (mem (base-reg)) will fit.
1784 That assumption fails on targets that don't have offsettable
1785 addresses at all. We therefore need to treat 'o' asm
1786 constraints as a special case and only accept operands that
1787 are already offsettable, thus proving that at least one
1788 offsettable address exists. */
1789 case 'o': /* offsettable */
1790 if (offsettable_nonstrict_memref_p (op
))
1795 if (general_operand (op
, VOIDmode
))
1802 /* ??? Before auto-inc-dec, auto inc/dec insns are not supposed
1803 to exist, excepting those that expand_call created. Further,
1804 on some machines which do not have generalized auto inc/dec,
1805 an inc/dec is not a memory_operand.
1807 Match any memory and hope things are resolved after reload. */
1811 cn
= lookup_constraint (constraint
);
1812 switch (get_constraint_type (cn
))
1816 && reg_class_for_constraint (cn
) != NO_REGS
1817 && GET_MODE (op
) != BLKmode
1818 && register_operand (op
, VOIDmode
))
1825 && insn_const_int_ok_for_constraint (INTVAL (op
), cn
))
1830 /* Every memory operand can be reloaded to fit. */
1831 result
= result
|| memory_operand (op
, VOIDmode
);
1835 /* Every address operand can be reloaded to fit. */
1836 result
= result
|| address_operand (op
, VOIDmode
);
1840 result
= result
|| constraint_satisfied_p (op
, cn
);
1845 len
= CONSTRAINT_LEN (c
, constraint
);
1848 while (--len
&& *constraint
);
1854 /* For operands without < or > constraints reject side-effects. */
1855 if (!incdec_ok
&& result
&& MEM_P (op
))
1856 switch (GET_CODE (XEXP (op
, 0)))
1873 /* Given an rtx *P, if it is a sum containing an integer constant term,
1874 return the location (type rtx *) of the pointer to that constant term.
1875 Otherwise, return a null pointer. */
1878 find_constant_term_loc (rtx
*p
)
1881 enum rtx_code code
= GET_CODE (*p
);
1883 /* If *P IS such a constant term, P is its location. */
1885 if (code
== CONST_INT
|| code
== SYMBOL_REF
|| code
== LABEL_REF
1889 /* Otherwise, if not a sum, it has no constant term. */
1891 if (GET_CODE (*p
) != PLUS
)
1894 /* If one of the summands is constant, return its location. */
1896 if (XEXP (*p
, 0) && CONSTANT_P (XEXP (*p
, 0))
1897 && XEXP (*p
, 1) && CONSTANT_P (XEXP (*p
, 1)))
1900 /* Otherwise, check each summand for containing a constant term. */
1902 if (XEXP (*p
, 0) != 0)
1904 tem
= find_constant_term_loc (&XEXP (*p
, 0));
1909 if (XEXP (*p
, 1) != 0)
1911 tem
= find_constant_term_loc (&XEXP (*p
, 1));
1919 /* Return 1 if OP is a memory reference
1920 whose address contains no side effects
1921 and remains valid after the addition
1922 of a positive integer less than the
1923 size of the object being referenced.
1925 We assume that the original address is valid and do not check it.
1927 This uses strict_memory_address_p as a subroutine, so
1928 don't use it before reload. */
1931 offsettable_memref_p (rtx op
)
1933 return ((MEM_P (op
))
1934 && offsettable_address_addr_space_p (1, GET_MODE (op
), XEXP (op
, 0),
1935 MEM_ADDR_SPACE (op
)));
1938 /* Similar, but don't require a strictly valid mem ref:
1939 consider pseudo-regs valid as index or base regs. */
1942 offsettable_nonstrict_memref_p (rtx op
)
1944 return ((MEM_P (op
))
1945 && offsettable_address_addr_space_p (0, GET_MODE (op
), XEXP (op
, 0),
1946 MEM_ADDR_SPACE (op
)));
1949 /* Return 1 if Y is a memory address which contains no side effects
1950 and would remain valid for address space AS after the addition of
1951 a positive integer less than the size of that mode.
1953 We assume that the original address is valid and do not check it.
1954 We do check that it is valid for narrower modes.
1956 If STRICTP is nonzero, we require a strictly valid address,
1957 for the sake of use in reload.c. */
1960 offsettable_address_addr_space_p (int strictp
, machine_mode mode
, rtx y
,
1963 enum rtx_code ycode
= GET_CODE (y
);
1967 int (*addressp
) (machine_mode
, rtx
, addr_space_t
) =
1968 (strictp
? strict_memory_address_addr_space_p
1969 : memory_address_addr_space_p
);
1970 unsigned int mode_sz
= GET_MODE_SIZE (mode
);
1972 if (CONSTANT_ADDRESS_P (y
))
1975 /* Adjusting an offsettable address involves changing to a narrower mode.
1976 Make sure that's OK. */
1978 if (mode_dependent_address_p (y
, as
))
1981 machine_mode address_mode
= GET_MODE (y
);
1982 if (address_mode
== VOIDmode
)
1983 address_mode
= targetm
.addr_space
.address_mode (as
);
1984 #ifdef POINTERS_EXTEND_UNSIGNED
1985 machine_mode pointer_mode
= targetm
.addr_space
.pointer_mode (as
);
1988 /* ??? How much offset does an offsettable BLKmode reference need?
1989 Clearly that depends on the situation in which it's being used.
1990 However, the current situation in which we test 0xffffffff is
1991 less than ideal. Caveat user. */
1993 mode_sz
= BIGGEST_ALIGNMENT
/ BITS_PER_UNIT
;
1995 /* If the expression contains a constant term,
1996 see if it remains valid when max possible offset is added. */
1998 if ((ycode
== PLUS
) && (y2
= find_constant_term_loc (&y1
)))
2003 *y2
= plus_constant (address_mode
, *y2
, mode_sz
- 1);
2004 /* Use QImode because an odd displacement may be automatically invalid
2005 for any wider mode. But it should be valid for a single byte. */
2006 good
= (*addressp
) (QImode
, y
, as
);
2008 /* In any case, restore old contents of memory. */
2013 if (GET_RTX_CLASS (ycode
) == RTX_AUTOINC
)
2016 /* The offset added here is chosen as the maximum offset that
2017 any instruction could need to add when operating on something
2018 of the specified mode. We assume that if Y and Y+c are
2019 valid addresses then so is Y+d for all 0<d<c. adjust_address will
2020 go inside a LO_SUM here, so we do so as well. */
2021 if (GET_CODE (y
) == LO_SUM
2023 && mode_sz
<= GET_MODE_ALIGNMENT (mode
) / BITS_PER_UNIT
)
2024 z
= gen_rtx_LO_SUM (address_mode
, XEXP (y
, 0),
2025 plus_constant (address_mode
, XEXP (y
, 1),
2027 #ifdef POINTERS_EXTEND_UNSIGNED
2028 /* Likewise for a ZERO_EXTEND from pointer_mode. */
2029 else if (POINTERS_EXTEND_UNSIGNED
> 0
2030 && GET_CODE (y
) == ZERO_EXTEND
2031 && GET_MODE (XEXP (y
, 0)) == pointer_mode
)
2032 z
= gen_rtx_ZERO_EXTEND (address_mode
,
2033 plus_constant (pointer_mode
, XEXP (y
, 0),
2037 z
= plus_constant (address_mode
, y
, mode_sz
- 1);
2039 /* Use QImode because an odd displacement may be automatically invalid
2040 for any wider mode. But it should be valid for a single byte. */
2041 return (*addressp
) (QImode
, z
, as
);
2044 /* Return 1 if ADDR is an address-expression whose effect depends
2045 on the mode of the memory reference it is used in.
2047 ADDRSPACE is the address space associated with the address.
2049 Autoincrement addressing is a typical example of mode-dependence
2050 because the amount of the increment depends on the mode. */
2053 mode_dependent_address_p (rtx addr
, addr_space_t addrspace
)
2055 /* Auto-increment addressing with anything other than post_modify
2056 or pre_modify always introduces a mode dependency. Catch such
2057 cases now instead of deferring to the target. */
2058 if (GET_CODE (addr
) == PRE_INC
2059 || GET_CODE (addr
) == POST_INC
2060 || GET_CODE (addr
) == PRE_DEC
2061 || GET_CODE (addr
) == POST_DEC
)
2064 return targetm
.mode_dependent_address_p (addr
, addrspace
);
2067 /* Return true if boolean attribute ATTR is supported. */
2070 have_bool_attr (bool_attr attr
)
2075 return HAVE_ATTR_enabled
;
2076 case BA_PREFERRED_FOR_SIZE
:
2077 return HAVE_ATTR_enabled
|| HAVE_ATTR_preferred_for_size
;
2078 case BA_PREFERRED_FOR_SPEED
:
2079 return HAVE_ATTR_enabled
|| HAVE_ATTR_preferred_for_speed
;
2084 /* Return the value of ATTR for instruction INSN. */
2087 get_bool_attr (rtx_insn
*insn
, bool_attr attr
)
2092 return get_attr_enabled (insn
);
2093 case BA_PREFERRED_FOR_SIZE
:
2094 return get_attr_enabled (insn
) && get_attr_preferred_for_size (insn
);
2095 case BA_PREFERRED_FOR_SPEED
:
2096 return get_attr_enabled (insn
) && get_attr_preferred_for_speed (insn
);
2101 /* Like get_bool_attr_mask, but don't use the cache. */
2103 static alternative_mask
2104 get_bool_attr_mask_uncached (rtx_insn
*insn
, bool_attr attr
)
2106 /* Temporarily install enough information for get_attr_<foo> to assume
2107 that the insn operands are already cached. As above, the attribute
2108 mustn't depend on the values of operands, so we don't provide their
2109 real values here. */
2110 rtx_insn
*old_insn
= recog_data
.insn
;
2111 int old_alternative
= which_alternative
;
2113 recog_data
.insn
= insn
;
2114 alternative_mask mask
= ALL_ALTERNATIVES
;
2115 int n_alternatives
= insn_data
[INSN_CODE (insn
)].n_alternatives
;
2116 for (int i
= 0; i
< n_alternatives
; i
++)
2118 which_alternative
= i
;
2119 if (!get_bool_attr (insn
, attr
))
2120 mask
&= ~ALTERNATIVE_BIT (i
);
2123 recog_data
.insn
= old_insn
;
2124 which_alternative
= old_alternative
;
2128 /* Return the mask of operand alternatives that are allowed for INSN
2129 by boolean attribute ATTR. This mask depends only on INSN and on
2130 the current target; it does not depend on things like the values of
2133 static alternative_mask
2134 get_bool_attr_mask (rtx_insn
*insn
, bool_attr attr
)
2136 /* Quick exit for asms and for targets that don't use these attributes. */
2137 int code
= INSN_CODE (insn
);
2138 if (code
< 0 || !have_bool_attr (attr
))
2139 return ALL_ALTERNATIVES
;
2141 /* Calling get_attr_<foo> can be expensive, so cache the mask
2143 if (!this_target_recog
->x_bool_attr_masks
[code
][attr
])
2144 this_target_recog
->x_bool_attr_masks
[code
][attr
]
2145 = get_bool_attr_mask_uncached (insn
, attr
);
2146 return this_target_recog
->x_bool_attr_masks
[code
][attr
];
2149 /* Return the set of alternatives of INSN that are allowed by the current
2153 get_enabled_alternatives (rtx_insn
*insn
)
2155 return get_bool_attr_mask (insn
, BA_ENABLED
);
2158 /* Return the set of alternatives of INSN that are allowed by the current
2159 target and are preferred for the current size/speed optimization
2163 get_preferred_alternatives (rtx_insn
*insn
)
2165 if (optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn
)))
2166 return get_bool_attr_mask (insn
, BA_PREFERRED_FOR_SPEED
);
2168 return get_bool_attr_mask (insn
, BA_PREFERRED_FOR_SIZE
);
2171 /* Return the set of alternatives of INSN that are allowed by the current
2172 target and are preferred for the size/speed optimization choice
2173 associated with BB. Passing a separate BB is useful if INSN has not
2174 been emitted yet or if we are considering moving it to a different
2178 get_preferred_alternatives (rtx_insn
*insn
, basic_block bb
)
2180 if (optimize_bb_for_speed_p (bb
))
2181 return get_bool_attr_mask (insn
, BA_PREFERRED_FOR_SPEED
);
2183 return get_bool_attr_mask (insn
, BA_PREFERRED_FOR_SIZE
);
2186 /* Assert that the cached boolean attributes for INSN are still accurate.
2187 The backend is required to define these attributes in a way that only
2188 depends on the current target (rather than operands, compiler phase,
2192 check_bool_attrs (rtx_insn
*insn
)
2194 int code
= INSN_CODE (insn
);
2196 for (int i
= 0; i
<= BA_LAST
; ++i
)
2198 enum bool_attr attr
= (enum bool_attr
) i
;
2199 if (this_target_recog
->x_bool_attr_masks
[code
][attr
])
2200 gcc_assert (this_target_recog
->x_bool_attr_masks
[code
][attr
]
2201 == get_bool_attr_mask_uncached (insn
, attr
));
2206 /* Like extract_insn, but save insn extracted and don't extract again, when
2207 called again for the same insn expecting that recog_data still contain the
2208 valid information. This is used primary by gen_attr infrastructure that
2209 often does extract insn again and again. */
2211 extract_insn_cached (rtx_insn
*insn
)
2213 if (recog_data
.insn
== insn
&& INSN_CODE (insn
) >= 0)
2215 extract_insn (insn
);
2216 recog_data
.insn
= insn
;
2219 /* Do uncached extract_insn, constrain_operands and complain about failures.
2220 This should be used when extracting a pre-existing constrained instruction
2221 if the caller wants to know which alternative was chosen. */
2223 extract_constrain_insn (rtx_insn
*insn
)
2225 extract_insn (insn
);
2226 if (!constrain_operands (reload_completed
, get_enabled_alternatives (insn
)))
2227 fatal_insn_not_found (insn
);
2230 /* Do cached extract_insn, constrain_operands and complain about failures.
2231 Used by insn_attrtab. */
2233 extract_constrain_insn_cached (rtx_insn
*insn
)
2235 extract_insn_cached (insn
);
2236 if (which_alternative
== -1
2237 && !constrain_operands (reload_completed
,
2238 get_enabled_alternatives (insn
)))
2239 fatal_insn_not_found (insn
);
2242 /* Do cached constrain_operands on INSN and complain about failures. */
2244 constrain_operands_cached (rtx_insn
*insn
, int strict
)
2246 if (which_alternative
== -1)
2247 return constrain_operands (strict
, get_enabled_alternatives (insn
));
2252 /* Analyze INSN and fill in recog_data. */
2255 extract_insn (rtx_insn
*insn
)
2260 rtx body
= PATTERN (insn
);
2262 recog_data
.n_operands
= 0;
2263 recog_data
.n_alternatives
= 0;
2264 recog_data
.n_dups
= 0;
2265 recog_data
.is_asm
= false;
2267 switch (GET_CODE (body
))
2278 if (GET_CODE (SET_SRC (body
)) == ASM_OPERANDS
)
2283 if ((GET_CODE (XVECEXP (body
, 0, 0)) == SET
2284 && GET_CODE (SET_SRC (XVECEXP (body
, 0, 0))) == ASM_OPERANDS
)
2285 || GET_CODE (XVECEXP (body
, 0, 0)) == ASM_OPERANDS
)
2291 recog_data
.n_operands
= noperands
= asm_noperands (body
);
2294 /* This insn is an `asm' with operands. */
2296 /* expand_asm_operands makes sure there aren't too many operands. */
2297 gcc_assert (noperands
<= MAX_RECOG_OPERANDS
);
2299 /* Now get the operand values and constraints out of the insn. */
2300 decode_asm_operands (body
, recog_data
.operand
,
2301 recog_data
.operand_loc
,
2302 recog_data
.constraints
,
2303 recog_data
.operand_mode
, NULL
);
2304 memset (recog_data
.is_operator
, 0, sizeof recog_data
.is_operator
);
2307 const char *p
= recog_data
.constraints
[0];
2308 recog_data
.n_alternatives
= 1;
2310 recog_data
.n_alternatives
+= (*p
++ == ',');
2312 recog_data
.is_asm
= true;
2315 fatal_insn_not_found (insn
);
2319 /* Ordinary insn: recognize it, get the operands via insn_extract
2320 and get the constraints. */
2322 icode
= recog_memoized (insn
);
2324 fatal_insn_not_found (insn
);
2326 recog_data
.n_operands
= noperands
= insn_data
[icode
].n_operands
;
2327 recog_data
.n_alternatives
= insn_data
[icode
].n_alternatives
;
2328 recog_data
.n_dups
= insn_data
[icode
].n_dups
;
2330 insn_extract (insn
);
2332 for (i
= 0; i
< noperands
; i
++)
2334 recog_data
.constraints
[i
] = insn_data
[icode
].operand
[i
].constraint
;
2335 recog_data
.is_operator
[i
] = insn_data
[icode
].operand
[i
].is_operator
;
2336 recog_data
.operand_mode
[i
] = insn_data
[icode
].operand
[i
].mode
;
2337 /* VOIDmode match_operands gets mode from their real operand. */
2338 if (recog_data
.operand_mode
[i
] == VOIDmode
)
2339 recog_data
.operand_mode
[i
] = GET_MODE (recog_data
.operand
[i
]);
2342 for (i
= 0; i
< noperands
; i
++)
2343 recog_data
.operand_type
[i
]
2344 = (recog_data
.constraints
[i
][0] == '=' ? OP_OUT
2345 : recog_data
.constraints
[i
][0] == '+' ? OP_INOUT
2348 gcc_assert (recog_data
.n_alternatives
<= MAX_RECOG_ALTERNATIVES
);
2350 recog_data
.insn
= NULL
;
2351 which_alternative
= -1;
2354 /* Fill in OP_ALT_BASE for an instruction that has N_OPERANDS operands,
2355 N_ALTERNATIVES alternatives and constraint strings CONSTRAINTS.
2356 OP_ALT_BASE has N_ALTERNATIVES * N_OPERANDS entries and CONSTRAINTS
2357 has N_OPERANDS entries. */
2360 preprocess_constraints (int n_operands
, int n_alternatives
,
2361 const char **constraints
,
2362 operand_alternative
*op_alt_base
)
2364 for (int i
= 0; i
< n_operands
; i
++)
2367 struct operand_alternative
*op_alt
;
2368 const char *p
= constraints
[i
];
2370 op_alt
= op_alt_base
;
2372 for (j
= 0; j
< n_alternatives
; j
++, op_alt
+= n_operands
)
2374 op_alt
[i
].cl
= NO_REGS
;
2375 op_alt
[i
].constraint
= p
;
2376 op_alt
[i
].matches
= -1;
2377 op_alt
[i
].matched
= -1;
2379 if (*p
== '\0' || *p
== ',')
2381 op_alt
[i
].anything_ok
= 1;
2391 while (c
!= ',' && c
!= '\0');
2392 if (c
== ',' || c
== '\0')
2401 op_alt
[i
].reject
+= 6;
2404 op_alt
[i
].reject
+= 600;
2407 op_alt
[i
].earlyclobber
= 1;
2410 case '0': case '1': case '2': case '3': case '4':
2411 case '5': case '6': case '7': case '8': case '9':
2414 op_alt
[i
].matches
= strtoul (p
, &end
, 10);
2415 op_alt
[op_alt
[i
].matches
].matched
= i
;
2421 op_alt
[i
].anything_ok
= 1;
2426 reg_class_subunion
[(int) op_alt
[i
].cl
][(int) GENERAL_REGS
];
2430 enum constraint_num cn
= lookup_constraint (p
);
2432 switch (get_constraint_type (cn
))
2435 cl
= reg_class_for_constraint (cn
);
2437 op_alt
[i
].cl
= reg_class_subunion
[op_alt
[i
].cl
][cl
];
2444 op_alt
[i
].memory_ok
= 1;
2448 op_alt
[i
].is_address
= 1;
2450 = (reg_class_subunion
2451 [(int) op_alt
[i
].cl
]
2452 [(int) base_reg_class (VOIDmode
, ADDR_SPACE_GENERIC
,
2453 ADDRESS
, SCRATCH
)]);
2461 p
+= CONSTRAINT_LEN (c
, p
);
2467 /* Return an array of operand_alternative instructions for
2468 instruction ICODE. */
2470 const operand_alternative
*
2471 preprocess_insn_constraints (int icode
)
2473 gcc_checking_assert (IN_RANGE (icode
, 0, LAST_INSN_CODE
));
2474 if (this_target_recog
->x_op_alt
[icode
])
2475 return this_target_recog
->x_op_alt
[icode
];
2477 int n_operands
= insn_data
[icode
].n_operands
;
2478 if (n_operands
== 0)
2480 /* Always provide at least one alternative so that which_op_alt ()
2481 works correctly. If the instruction has 0 alternatives (i.e. all
2482 constraint strings are empty) then each operand in this alternative
2483 will have anything_ok set. */
2484 int n_alternatives
= MAX (insn_data
[icode
].n_alternatives
, 1);
2485 int n_entries
= n_operands
* n_alternatives
;
2487 operand_alternative
*op_alt
= XCNEWVEC (operand_alternative
, n_entries
);
2488 const char **constraints
= XALLOCAVEC (const char *, n_operands
);
2490 for (int i
= 0; i
< n_operands
; ++i
)
2491 constraints
[i
] = insn_data
[icode
].operand
[i
].constraint
;
2492 preprocess_constraints (n_operands
, n_alternatives
, constraints
, op_alt
);
2494 this_target_recog
->x_op_alt
[icode
] = op_alt
;
2498 /* After calling extract_insn, you can use this function to extract some
2499 information from the constraint strings into a more usable form.
2500 The collected data is stored in recog_op_alt. */
2503 preprocess_constraints (rtx_insn
*insn
)
2505 int icode
= INSN_CODE (insn
);
2507 recog_op_alt
= preprocess_insn_constraints (icode
);
2510 int n_operands
= recog_data
.n_operands
;
2511 int n_alternatives
= recog_data
.n_alternatives
;
2512 int n_entries
= n_operands
* n_alternatives
;
2513 memset (asm_op_alt
, 0, n_entries
* sizeof (operand_alternative
));
2514 preprocess_constraints (n_operands
, n_alternatives
,
2515 recog_data
.constraints
, asm_op_alt
);
2516 recog_op_alt
= asm_op_alt
;
2520 /* Check the operands of an insn against the insn's operand constraints
2521 and return 1 if they match any of the alternatives in ALTERNATIVES.
2523 The information about the insn's operands, constraints, operand modes
2524 etc. is obtained from the global variables set up by extract_insn.
2526 WHICH_ALTERNATIVE is set to a number which indicates which
2527 alternative of constraints was matched: 0 for the first alternative,
2528 1 for the next, etc.
2530 In addition, when two operands are required to match
2531 and it happens that the output operand is (reg) while the
2532 input operand is --(reg) or ++(reg) (a pre-inc or pre-dec),
2533 make the output operand look like the input.
2534 This is because the output operand is the one the template will print.
2536 This is used in final, just before printing the assembler code and by
2537 the routines that determine an insn's attribute.
2539 If STRICT is a positive nonzero value, it means that we have been
2540 called after reload has been completed. In that case, we must
2541 do all checks strictly. If it is zero, it means that we have been called
2542 before reload has completed. In that case, we first try to see if we can
2543 find an alternative that matches strictly. If not, we try again, this
2544 time assuming that reload will fix up the insn. This provides a "best
2545 guess" for the alternative and is used to compute attributes of insns prior
2546 to reload. A negative value of STRICT is used for this internal call. */
2554 constrain_operands (int strict
, alternative_mask alternatives
)
2556 const char *constraints
[MAX_RECOG_OPERANDS
];
2557 int matching_operands
[MAX_RECOG_OPERANDS
];
2558 int earlyclobber
[MAX_RECOG_OPERANDS
];
2561 struct funny_match funny_match
[MAX_RECOG_OPERANDS
];
2562 int funny_match_index
;
2564 which_alternative
= 0;
2565 if (recog_data
.n_operands
== 0 || recog_data
.n_alternatives
== 0)
2568 for (c
= 0; c
< recog_data
.n_operands
; c
++)
2570 constraints
[c
] = recog_data
.constraints
[c
];
2571 matching_operands
[c
] = -1;
2576 int seen_earlyclobber_at
= -1;
2579 funny_match_index
= 0;
2581 if (!TEST_BIT (alternatives
, which_alternative
))
2585 for (i
= 0; i
< recog_data
.n_operands
; i
++)
2586 constraints
[i
] = skip_alternative (constraints
[i
]);
2588 which_alternative
++;
2592 for (opno
= 0; opno
< recog_data
.n_operands
; opno
++)
2594 rtx op
= recog_data
.operand
[opno
];
2595 machine_mode mode
= GET_MODE (op
);
2596 const char *p
= constraints
[opno
];
2602 earlyclobber
[opno
] = 0;
2604 /* A unary operator may be accepted by the predicate, but it
2605 is irrelevant for matching constraints. */
2609 if (GET_CODE (op
) == SUBREG
)
2611 if (REG_P (SUBREG_REG (op
))
2612 && REGNO (SUBREG_REG (op
)) < FIRST_PSEUDO_REGISTER
)
2613 offset
= subreg_regno_offset (REGNO (SUBREG_REG (op
)),
2614 GET_MODE (SUBREG_REG (op
)),
2617 op
= SUBREG_REG (op
);
2620 /* An empty constraint or empty alternative
2621 allows anything which matched the pattern. */
2622 if (*p
== 0 || *p
== ',')
2626 switch (c
= *p
, len
= CONSTRAINT_LEN (c
, p
), c
)
2636 /* Ignore rest of this alternative as far as
2637 constraint checking is concerned. */
2640 while (*p
&& *p
!= ',');
2645 earlyclobber
[opno
] = 1;
2646 if (seen_earlyclobber_at
< 0)
2647 seen_earlyclobber_at
= opno
;
2650 case '0': case '1': case '2': case '3': case '4':
2651 case '5': case '6': case '7': case '8': case '9':
2653 /* This operand must be the same as a previous one.
2654 This kind of constraint is used for instructions such
2655 as add when they take only two operands.
2657 Note that the lower-numbered operand is passed first.
2659 If we are not testing strictly, assume that this
2660 constraint will be satisfied. */
2665 match
= strtoul (p
, &end
, 10);
2672 rtx op1
= recog_data
.operand
[match
];
2673 rtx op2
= recog_data
.operand
[opno
];
2675 /* A unary operator may be accepted by the predicate,
2676 but it is irrelevant for matching constraints. */
2678 op1
= XEXP (op1
, 0);
2680 op2
= XEXP (op2
, 0);
2682 val
= operands_match_p (op1
, op2
);
2685 matching_operands
[opno
] = match
;
2686 matching_operands
[match
] = opno
;
2691 /* If output is *x and input is *--x, arrange later
2692 to change the output to *--x as well, since the
2693 output op is the one that will be printed. */
2694 if (val
== 2 && strict
> 0)
2696 funny_match
[funny_match_index
].this_op
= opno
;
2697 funny_match
[funny_match_index
++].other
= match
;
2704 /* p is used for address_operands. When we are called by
2705 gen_reload, no one will have checked that the address is
2706 strictly valid, i.e., that all pseudos requiring hard regs
2707 have gotten them. */
2709 || (strict_memory_address_p (recog_data
.operand_mode
[opno
],
2714 /* No need to check general_operand again;
2715 it was done in insn-recog.c. Well, except that reload
2716 doesn't check the validity of its replacements, but
2717 that should only matter when there's a bug. */
2719 /* Anything goes unless it is a REG and really has a hard reg
2720 but the hard reg is not in the class GENERAL_REGS. */
2724 || GENERAL_REGS
== ALL_REGS
2725 || (reload_in_progress
2726 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
)
2727 || reg_fits_class_p (op
, GENERAL_REGS
, offset
, mode
))
2730 else if (strict
< 0 || general_operand (op
, mode
))
2736 enum constraint_num cn
= lookup_constraint (p
);
2737 enum reg_class cl
= reg_class_for_constraint (cn
);
2743 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
)
2744 || (strict
== 0 && GET_CODE (op
) == SCRATCH
)
2746 && reg_fits_class_p (op
, cl
, offset
, mode
)))
2750 else if (constraint_satisfied_p (op
, cn
))
2753 else if (insn_extra_memory_constraint (cn
)
2754 /* Every memory operand can be reloaded to fit. */
2755 && ((strict
< 0 && MEM_P (op
))
2756 /* Before reload, accept what reload can turn
2758 || (strict
< 0 && CONSTANT_P (op
))
2759 /* Before reload, accept a pseudo,
2760 since LRA can turn it into a mem. */
2761 || (strict
< 0 && targetm
.lra_p () && REG_P (op
)
2762 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
)
2763 /* During reload, accept a pseudo */
2764 || (reload_in_progress
&& REG_P (op
)
2765 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
)))
2767 else if (insn_extra_address_constraint (cn
)
2768 /* Every address operand can be reloaded to fit. */
2771 /* Cater to architectures like IA-64 that define extra memory
2772 constraints without using define_memory_constraint. */
2773 else if (reload_in_progress
2775 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
2776 && reg_renumber
[REGNO (op
)] < 0
2777 && reg_equiv_mem (REGNO (op
)) != 0
2778 && constraint_satisfied_p
2779 (reg_equiv_mem (REGNO (op
)), cn
))
2784 while (p
+= len
, c
);
2786 constraints
[opno
] = p
;
2787 /* If this operand did not win somehow,
2788 this alternative loses. */
2792 /* This alternative won; the operands are ok.
2793 Change whichever operands this alternative says to change. */
2798 /* See if any earlyclobber operand conflicts with some other
2801 if (strict
> 0 && seen_earlyclobber_at
>= 0)
2802 for (eopno
= seen_earlyclobber_at
;
2803 eopno
< recog_data
.n_operands
;
2805 /* Ignore earlyclobber operands now in memory,
2806 because we would often report failure when we have
2807 two memory operands, one of which was formerly a REG. */
2808 if (earlyclobber
[eopno
]
2809 && REG_P (recog_data
.operand
[eopno
]))
2810 for (opno
= 0; opno
< recog_data
.n_operands
; opno
++)
2811 if ((MEM_P (recog_data
.operand
[opno
])
2812 || recog_data
.operand_type
[opno
] != OP_OUT
)
2814 /* Ignore things like match_operator operands. */
2815 && *recog_data
.constraints
[opno
] != 0
2816 && ! (matching_operands
[opno
] == eopno
2817 && operands_match_p (recog_data
.operand
[opno
],
2818 recog_data
.operand
[eopno
]))
2819 && ! safe_from_earlyclobber (recog_data
.operand
[opno
],
2820 recog_data
.operand
[eopno
]))
2825 while (--funny_match_index
>= 0)
2827 recog_data
.operand
[funny_match
[funny_match_index
].other
]
2828 = recog_data
.operand
[funny_match
[funny_match_index
].this_op
];
2832 /* For operands without < or > constraints reject side-effects. */
2833 if (recog_data
.is_asm
)
2835 for (opno
= 0; opno
< recog_data
.n_operands
; opno
++)
2836 if (MEM_P (recog_data
.operand
[opno
]))
2837 switch (GET_CODE (XEXP (recog_data
.operand
[opno
], 0)))
2845 if (strchr (recog_data
.constraints
[opno
], '<') == NULL
2846 && strchr (recog_data
.constraints
[opno
], '>')
2859 which_alternative
++;
2861 while (which_alternative
< recog_data
.n_alternatives
);
2863 which_alternative
= -1;
2864 /* If we are about to reject this, but we are not to test strictly,
2865 try a very loose test. Only return failure if it fails also. */
2867 return constrain_operands (-1, alternatives
);
2872 /* Return true iff OPERAND (assumed to be a REG rtx)
2873 is a hard reg in class CLASS when its regno is offset by OFFSET
2874 and changed to mode MODE.
2875 If REG occupies multiple hard regs, all of them must be in CLASS. */
2878 reg_fits_class_p (const_rtx operand
, reg_class_t cl
, int offset
,
2881 unsigned int regno
= REGNO (operand
);
2886 /* Regno must not be a pseudo register. Offset may be negative. */
2887 return (HARD_REGISTER_NUM_P (regno
)
2888 && HARD_REGISTER_NUM_P (regno
+ offset
)
2889 && in_hard_reg_set_p (reg_class_contents
[(int) cl
], mode
,
2893 /* Split single instruction. Helper function for split_all_insns and
2894 split_all_insns_noflow. Return last insn in the sequence if successful,
2895 or NULL if unsuccessful. */
2898 split_insn (rtx_insn
*insn
)
2900 /* Split insns here to get max fine-grain parallelism. */
2901 rtx_insn
*first
= PREV_INSN (insn
);
2902 rtx_insn
*last
= try_split (PATTERN (insn
), insn
, 1);
2903 rtx insn_set
, last_set
, note
;
2908 /* If the original instruction was a single set that was known to be
2909 equivalent to a constant, see if we can say the same about the last
2910 instruction in the split sequence. The two instructions must set
2911 the same destination. */
2912 insn_set
= single_set (insn
);
2915 last_set
= single_set (last
);
2916 if (last_set
&& rtx_equal_p (SET_DEST (last_set
), SET_DEST (insn_set
)))
2918 note
= find_reg_equal_equiv_note (insn
);
2919 if (note
&& CONSTANT_P (XEXP (note
, 0)))
2920 set_unique_reg_note (last
, REG_EQUAL
, XEXP (note
, 0));
2921 else if (CONSTANT_P (SET_SRC (insn_set
)))
2922 set_unique_reg_note (last
, REG_EQUAL
,
2923 copy_rtx (SET_SRC (insn_set
)));
2927 /* try_split returns the NOTE that INSN became. */
2928 SET_INSN_DELETED (insn
);
2930 /* ??? Coddle to md files that generate subregs in post-reload
2931 splitters instead of computing the proper hard register. */
2932 if (reload_completed
&& first
!= last
)
2934 first
= NEXT_INSN (first
);
2938 cleanup_subreg_operands (first
);
2941 first
= NEXT_INSN (first
);
2948 /* Split all insns in the function. If UPD_LIFE, update life info after. */
2951 split_all_insns (void)
2957 blocks
= sbitmap_alloc (last_basic_block_for_fn (cfun
));
2958 bitmap_clear (blocks
);
2961 FOR_EACH_BB_REVERSE_FN (bb
, cfun
)
2963 rtx_insn
*insn
, *next
;
2964 bool finish
= false;
2966 rtl_profile_for_bb (bb
);
2967 for (insn
= BB_HEAD (bb
); !finish
; insn
= next
)
2969 /* Can't use `next_real_insn' because that might go across
2970 CODE_LABELS and short-out basic blocks. */
2971 next
= NEXT_INSN (insn
);
2972 finish
= (insn
== BB_END (bb
));
2975 rtx set
= single_set (insn
);
2977 /* Don't split no-op move insns. These should silently
2978 disappear later in final. Splitting such insns would
2979 break the code that handles LIBCALL blocks. */
2980 if (set
&& set_noop_p (set
))
2982 /* Nops get in the way while scheduling, so delete them
2983 now if register allocation has already been done. It
2984 is too risky to try to do this before register
2985 allocation, and there are unlikely to be very many
2986 nops then anyways. */
2987 if (reload_completed
)
2988 delete_insn_and_edges (insn
);
2992 if (split_insn (insn
))
2994 bitmap_set_bit (blocks
, bb
->index
);
3002 default_rtl_profile ();
3004 find_many_sub_basic_blocks (blocks
);
3006 #ifdef ENABLE_CHECKING
3007 verify_flow_info ();
3010 sbitmap_free (blocks
);
3013 /* Same as split_all_insns, but do not expect CFG to be available.
3014 Used by machine dependent reorg passes. */
3017 split_all_insns_noflow (void)
3019 rtx_insn
*next
, *insn
;
3021 for (insn
= get_insns (); insn
; insn
= next
)
3023 next
= NEXT_INSN (insn
);
3026 /* Don't split no-op move insns. These should silently
3027 disappear later in final. Splitting such insns would
3028 break the code that handles LIBCALL blocks. */
3029 rtx set
= single_set (insn
);
3030 if (set
&& set_noop_p (set
))
3032 /* Nops get in the way while scheduling, so delete them
3033 now if register allocation has already been done. It
3034 is too risky to try to do this before register
3035 allocation, and there are unlikely to be very many
3038 ??? Should we use delete_insn when the CFG isn't valid? */
3039 if (reload_completed
)
3040 delete_insn_and_edges (insn
);
3049 #ifdef HAVE_peephole2
3050 struct peep2_insn_data
3056 static struct peep2_insn_data peep2_insn_data
[MAX_INSNS_PER_PEEP2
+ 1];
3057 static int peep2_current
;
3059 static bool peep2_do_rebuild_jump_labels
;
3060 static bool peep2_do_cleanup_cfg
;
3062 /* The number of instructions available to match a peep2. */
3063 int peep2_current_count
;
3065 /* A marker indicating the last insn of the block. The live_before regset
3066 for this element is correct, indicating DF_LIVE_OUT for the block. */
3067 #define PEEP2_EOB invalid_insn_rtx
3069 /* Wrap N to fit into the peep2_insn_data buffer. */
3072 peep2_buf_position (int n
)
3074 if (n
>= MAX_INSNS_PER_PEEP2
+ 1)
3075 n
-= MAX_INSNS_PER_PEEP2
+ 1;
3079 /* Return the Nth non-note insn after `current', or return NULL_RTX if it
3080 does not exist. Used by the recognizer to find the next insn to match
3081 in a multi-insn pattern. */
3084 peep2_next_insn (int n
)
3086 gcc_assert (n
<= peep2_current_count
);
3088 n
= peep2_buf_position (peep2_current
+ n
);
3090 return peep2_insn_data
[n
].insn
;
3093 /* Return true if REGNO is dead before the Nth non-note insn
3097 peep2_regno_dead_p (int ofs
, int regno
)
3099 gcc_assert (ofs
< MAX_INSNS_PER_PEEP2
+ 1);
3101 ofs
= peep2_buf_position (peep2_current
+ ofs
);
3103 gcc_assert (peep2_insn_data
[ofs
].insn
!= NULL_RTX
);
3105 return ! REGNO_REG_SET_P (peep2_insn_data
[ofs
].live_before
, regno
);
3108 /* Similarly for a REG. */
3111 peep2_reg_dead_p (int ofs
, rtx reg
)
3113 gcc_assert (ofs
< MAX_INSNS_PER_PEEP2
+ 1);
3115 ofs
= peep2_buf_position (peep2_current
+ ofs
);
3117 gcc_assert (peep2_insn_data
[ofs
].insn
!= NULL_RTX
);
3119 unsigned int end_regno
= END_REGNO (reg
);
3120 for (unsigned int regno
= REGNO (reg
); regno
< end_regno
; ++regno
)
3121 if (REGNO_REG_SET_P (peep2_insn_data
[ofs
].live_before
, regno
))
3126 /* Regno offset to be used in the register search. */
3127 static int search_ofs
;
3129 /* Try to find a hard register of mode MODE, matching the register class in
3130 CLASS_STR, which is available at the beginning of insn CURRENT_INSN and
3131 remains available until the end of LAST_INSN. LAST_INSN may be NULL_RTX,
3132 in which case the only condition is that the register must be available
3133 before CURRENT_INSN.
3134 Registers that already have bits set in REG_SET will not be considered.
3136 If an appropriate register is available, it will be returned and the
3137 corresponding bit(s) in REG_SET will be set; otherwise, NULL_RTX is
3141 peep2_find_free_register (int from
, int to
, const char *class_str
,
3142 machine_mode mode
, HARD_REG_SET
*reg_set
)
3149 gcc_assert (from
< MAX_INSNS_PER_PEEP2
+ 1);
3150 gcc_assert (to
< MAX_INSNS_PER_PEEP2
+ 1);
3152 from
= peep2_buf_position (peep2_current
+ from
);
3153 to
= peep2_buf_position (peep2_current
+ to
);
3155 gcc_assert (peep2_insn_data
[from
].insn
!= NULL_RTX
);
3156 REG_SET_TO_HARD_REG_SET (live
, peep2_insn_data
[from
].live_before
);
3160 gcc_assert (peep2_insn_data
[from
].insn
!= NULL_RTX
);
3162 /* Don't use registers set or clobbered by the insn. */
3163 FOR_EACH_INSN_DEF (def
, peep2_insn_data
[from
].insn
)
3164 SET_HARD_REG_BIT (live
, DF_REF_REGNO (def
));
3166 from
= peep2_buf_position (from
+ 1);
3169 cl
= reg_class_for_constraint (lookup_constraint (class_str
));
3171 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
3173 int raw_regno
, regno
, success
, j
;
3175 /* Distribute the free registers as much as possible. */
3176 raw_regno
= search_ofs
+ i
;
3177 if (raw_regno
>= FIRST_PSEUDO_REGISTER
)
3178 raw_regno
-= FIRST_PSEUDO_REGISTER
;
3179 #ifdef REG_ALLOC_ORDER
3180 regno
= reg_alloc_order
[raw_regno
];
3185 /* Can it support the mode we need? */
3186 if (! HARD_REGNO_MODE_OK (regno
, mode
))
3190 for (j
= 0; success
&& j
< hard_regno_nregs
[regno
][mode
]; j
++)
3192 /* Don't allocate fixed registers. */
3193 if (fixed_regs
[regno
+ j
])
3198 /* Don't allocate global registers. */
3199 if (global_regs
[regno
+ j
])
3204 /* Make sure the register is of the right class. */
3205 if (! TEST_HARD_REG_BIT (reg_class_contents
[cl
], regno
+ j
))
3210 /* And that we don't create an extra save/restore. */
3211 if (! call_used_regs
[regno
+ j
] && ! df_regs_ever_live_p (regno
+ j
))
3217 if (! targetm
.hard_regno_scratch_ok (regno
+ j
))
3223 /* And we don't clobber traceback for noreturn functions. */
3224 if ((regno
+ j
== FRAME_POINTER_REGNUM
3225 || regno
+ j
== HARD_FRAME_POINTER_REGNUM
)
3226 && (! reload_completed
|| frame_pointer_needed
))
3232 if (TEST_HARD_REG_BIT (*reg_set
, regno
+ j
)
3233 || TEST_HARD_REG_BIT (live
, regno
+ j
))
3242 add_to_hard_reg_set (reg_set
, mode
, regno
);
3244 /* Start the next search with the next register. */
3245 if (++raw_regno
>= FIRST_PSEUDO_REGISTER
)
3247 search_ofs
= raw_regno
;
3249 return gen_rtx_REG (mode
, regno
);
3257 /* Forget all currently tracked instructions, only remember current
3261 peep2_reinit_state (regset live
)
3265 /* Indicate that all slots except the last holds invalid data. */
3266 for (i
= 0; i
< MAX_INSNS_PER_PEEP2
; ++i
)
3267 peep2_insn_data
[i
].insn
= NULL
;
3268 peep2_current_count
= 0;
3270 /* Indicate that the last slot contains live_after data. */
3271 peep2_insn_data
[MAX_INSNS_PER_PEEP2
].insn
= PEEP2_EOB
;
3272 peep2_current
= MAX_INSNS_PER_PEEP2
;
3274 COPY_REG_SET (peep2_insn_data
[MAX_INSNS_PER_PEEP2
].live_before
, live
);
3277 /* While scanning basic block BB, we found a match of length MATCH_LEN,
3278 starting at INSN. Perform the replacement, removing the old insns and
3279 replacing them with ATTEMPT. Returns the last insn emitted, or NULL
3280 if the replacement is rejected. */
3283 peep2_attempt (basic_block bb
, rtx_insn
*insn
, int match_len
, rtx_insn
*attempt
)
3286 rtx_insn
*last
, *before_try
, *x
;
3287 rtx eh_note
, as_note
;
3290 bool was_call
= false;
3292 /* If we are splitting an RTX_FRAME_RELATED_P insn, do not allow it to
3293 match more than one insn, or to be split into more than one insn. */
3294 old_insn
= peep2_insn_data
[peep2_current
].insn
;
3295 if (RTX_FRAME_RELATED_P (old_insn
))
3297 bool any_note
= false;
3303 /* Look for one "active" insn. I.e. ignore any "clobber" insns that
3304 may be in the stream for the purpose of register allocation. */
3305 if (active_insn_p (attempt
))
3308 new_insn
= next_active_insn (attempt
);
3309 if (next_active_insn (new_insn
))
3312 /* We have a 1-1 replacement. Copy over any frame-related info. */
3313 RTX_FRAME_RELATED_P (new_insn
) = 1;
3315 /* Allow the backend to fill in a note during the split. */
3316 for (note
= REG_NOTES (new_insn
); note
; note
= XEXP (note
, 1))
3317 switch (REG_NOTE_KIND (note
))
3319 case REG_FRAME_RELATED_EXPR
:
3320 case REG_CFA_DEF_CFA
:
3321 case REG_CFA_ADJUST_CFA
:
3322 case REG_CFA_OFFSET
:
3323 case REG_CFA_REGISTER
:
3324 case REG_CFA_EXPRESSION
:
3325 case REG_CFA_RESTORE
:
3326 case REG_CFA_SET_VDRAP
:
3333 /* If the backend didn't supply a note, copy one over. */
3335 for (note
= REG_NOTES (old_insn
); note
; note
= XEXP (note
, 1))
3336 switch (REG_NOTE_KIND (note
))
3338 case REG_FRAME_RELATED_EXPR
:
3339 case REG_CFA_DEF_CFA
:
3340 case REG_CFA_ADJUST_CFA
:
3341 case REG_CFA_OFFSET
:
3342 case REG_CFA_REGISTER
:
3343 case REG_CFA_EXPRESSION
:
3344 case REG_CFA_RESTORE
:
3345 case REG_CFA_SET_VDRAP
:
3346 add_reg_note (new_insn
, REG_NOTE_KIND (note
), XEXP (note
, 0));
3353 /* If there still isn't a note, make sure the unwind info sees the
3354 same expression as before the split. */
3357 rtx old_set
, new_set
;
3359 /* The old insn had better have been simple, or annotated. */
3360 old_set
= single_set (old_insn
);
3361 gcc_assert (old_set
!= NULL
);
3363 new_set
= single_set (new_insn
);
3364 if (!new_set
|| !rtx_equal_p (new_set
, old_set
))
3365 add_reg_note (new_insn
, REG_FRAME_RELATED_EXPR
, old_set
);
3368 /* Copy prologue/epilogue status. This is required in order to keep
3369 proper placement of EPILOGUE_BEG and the DW_CFA_remember_state. */
3370 maybe_copy_prologue_epilogue_insn (old_insn
, new_insn
);
3373 /* If we are splitting a CALL_INSN, look for the CALL_INSN
3374 in SEQ and copy our CALL_INSN_FUNCTION_USAGE and other
3375 cfg-related call notes. */
3376 for (i
= 0; i
<= match_len
; ++i
)
3381 j
= peep2_buf_position (peep2_current
+ i
);
3382 old_insn
= peep2_insn_data
[j
].insn
;
3383 if (!CALL_P (old_insn
))
3388 while (new_insn
!= NULL_RTX
)
3390 if (CALL_P (new_insn
))
3392 new_insn
= NEXT_INSN (new_insn
);
3395 gcc_assert (new_insn
!= NULL_RTX
);
3397 CALL_INSN_FUNCTION_USAGE (new_insn
)
3398 = CALL_INSN_FUNCTION_USAGE (old_insn
);
3399 SIBLING_CALL_P (new_insn
) = SIBLING_CALL_P (old_insn
);
3401 for (note
= REG_NOTES (old_insn
);
3403 note
= XEXP (note
, 1))
3404 switch (REG_NOTE_KIND (note
))
3409 add_reg_note (new_insn
, REG_NOTE_KIND (note
),
3413 /* Discard all other reg notes. */
3417 /* Croak if there is another call in the sequence. */
3418 while (++i
<= match_len
)
3420 j
= peep2_buf_position (peep2_current
+ i
);
3421 old_insn
= peep2_insn_data
[j
].insn
;
3422 gcc_assert (!CALL_P (old_insn
));
3427 /* If we matched any instruction that had a REG_ARGS_SIZE, then
3428 move those notes over to the new sequence. */
3430 for (i
= match_len
; i
>= 0; --i
)
3432 int j
= peep2_buf_position (peep2_current
+ i
);
3433 old_insn
= peep2_insn_data
[j
].insn
;
3435 as_note
= find_reg_note (old_insn
, REG_ARGS_SIZE
, NULL
);
3440 i
= peep2_buf_position (peep2_current
+ match_len
);
3441 eh_note
= find_reg_note (peep2_insn_data
[i
].insn
, REG_EH_REGION
, NULL_RTX
);
3443 /* Replace the old sequence with the new. */
3444 rtx_insn
*peepinsn
= peep2_insn_data
[i
].insn
;
3445 last
= emit_insn_after_setloc (attempt
,
3446 peep2_insn_data
[i
].insn
,
3447 INSN_LOCATION (peepinsn
));
3448 before_try
= PREV_INSN (insn
);
3449 delete_insn_chain (insn
, peep2_insn_data
[i
].insn
, false);
3451 /* Re-insert the EH_REGION notes. */
3452 if (eh_note
|| (was_call
&& nonlocal_goto_handler_labels
))
3457 FOR_EACH_EDGE (eh_edge
, ei
, bb
->succs
)
3458 if (eh_edge
->flags
& (EDGE_EH
| EDGE_ABNORMAL_CALL
))
3462 copy_reg_eh_region_note_backward (eh_note
, last
, before_try
);
3465 for (x
= last
; x
!= before_try
; x
= PREV_INSN (x
))
3466 if (x
!= BB_END (bb
)
3467 && (can_throw_internal (x
)
3468 || can_nonlocal_goto (x
)))
3473 nfte
= split_block (bb
, x
);
3474 flags
= (eh_edge
->flags
3475 & (EDGE_EH
| EDGE_ABNORMAL
));
3477 flags
|= EDGE_ABNORMAL_CALL
;
3478 nehe
= make_edge (nfte
->src
, eh_edge
->dest
,
3481 nehe
->probability
= eh_edge
->probability
;
3483 = REG_BR_PROB_BASE
- nehe
->probability
;
3485 peep2_do_cleanup_cfg
|= purge_dead_edges (nfte
->dest
);
3490 /* Converting possibly trapping insn to non-trapping is
3491 possible. Zap dummy outgoing edges. */
3492 peep2_do_cleanup_cfg
|= purge_dead_edges (bb
);
3495 /* Re-insert the ARGS_SIZE notes. */
3497 fixup_args_size_notes (before_try
, last
, INTVAL (XEXP (as_note
, 0)));
3499 /* If we generated a jump instruction, it won't have
3500 JUMP_LABEL set. Recompute after we're done. */
3501 for (x
= last
; x
!= before_try
; x
= PREV_INSN (x
))
3504 peep2_do_rebuild_jump_labels
= true;
3511 /* After performing a replacement in basic block BB, fix up the life
3512 information in our buffer. LAST is the last of the insns that we
3513 emitted as a replacement. PREV is the insn before the start of
3514 the replacement. MATCH_LEN is the number of instructions that were
3515 matched, and which now need to be replaced in the buffer. */
3518 peep2_update_life (basic_block bb
, int match_len
, rtx_insn
*last
,
3521 int i
= peep2_buf_position (peep2_current
+ match_len
+ 1);
3525 INIT_REG_SET (&live
);
3526 COPY_REG_SET (&live
, peep2_insn_data
[i
].live_before
);
3528 gcc_assert (peep2_current_count
>= match_len
+ 1);
3529 peep2_current_count
-= match_len
+ 1;
3537 if (peep2_current_count
< MAX_INSNS_PER_PEEP2
)
3539 peep2_current_count
++;
3541 i
= MAX_INSNS_PER_PEEP2
;
3542 peep2_insn_data
[i
].insn
= x
;
3543 df_simulate_one_insn_backwards (bb
, x
, &live
);
3544 COPY_REG_SET (peep2_insn_data
[i
].live_before
, &live
);
3550 CLEAR_REG_SET (&live
);
3555 /* Add INSN, which is in BB, at the end of the peep2 insn buffer if possible.
3556 Return true if we added it, false otherwise. The caller will try to match
3557 peepholes against the buffer if we return false; otherwise it will try to
3558 add more instructions to the buffer. */
3561 peep2_fill_buffer (basic_block bb
, rtx_insn
*insn
, regset live
)
3565 /* Once we have filled the maximum number of insns the buffer can hold,
3566 allow the caller to match the insns against peepholes. We wait until
3567 the buffer is full in case the target has similar peepholes of different
3568 length; we always want to match the longest if possible. */
3569 if (peep2_current_count
== MAX_INSNS_PER_PEEP2
)
3572 /* If an insn has RTX_FRAME_RELATED_P set, do not allow it to be matched with
3573 any other pattern, lest it change the semantics of the frame info. */
3574 if (RTX_FRAME_RELATED_P (insn
))
3576 /* Let the buffer drain first. */
3577 if (peep2_current_count
> 0)
3579 /* Now the insn will be the only thing in the buffer. */
3582 pos
= peep2_buf_position (peep2_current
+ peep2_current_count
);
3583 peep2_insn_data
[pos
].insn
= insn
;
3584 COPY_REG_SET (peep2_insn_data
[pos
].live_before
, live
);
3585 peep2_current_count
++;
3587 df_simulate_one_insn_forwards (bb
, insn
, live
);
3591 /* Perform the peephole2 optimization pass. */
3594 peephole2_optimize (void)
3601 peep2_do_cleanup_cfg
= false;
3602 peep2_do_rebuild_jump_labels
= false;
3604 df_set_flags (DF_LR_RUN_DCE
);
3605 df_note_add_problem ();
3608 /* Initialize the regsets we're going to use. */
3609 for (i
= 0; i
< MAX_INSNS_PER_PEEP2
+ 1; ++i
)
3610 peep2_insn_data
[i
].live_before
= BITMAP_ALLOC (®_obstack
);
3612 live
= BITMAP_ALLOC (®_obstack
);
3614 FOR_EACH_BB_REVERSE_FN (bb
, cfun
)
3616 bool past_end
= false;
3619 rtl_profile_for_bb (bb
);
3621 /* Start up propagation. */
3622 bitmap_copy (live
, DF_LR_IN (bb
));
3623 df_simulate_initialize_forwards (bb
, live
);
3624 peep2_reinit_state (live
);
3626 insn
= BB_HEAD (bb
);
3629 rtx_insn
*attempt
, *head
;
3632 if (!past_end
&& !NONDEBUG_INSN_P (insn
))
3635 insn
= NEXT_INSN (insn
);
3636 if (insn
== NEXT_INSN (BB_END (bb
)))
3640 if (!past_end
&& peep2_fill_buffer (bb
, insn
, live
))
3643 /* If we did not fill an empty buffer, it signals the end of the
3645 if (peep2_current_count
== 0)
3648 /* The buffer filled to the current maximum, so try to match. */
3650 pos
= peep2_buf_position (peep2_current
+ peep2_current_count
);
3651 peep2_insn_data
[pos
].insn
= PEEP2_EOB
;
3652 COPY_REG_SET (peep2_insn_data
[pos
].live_before
, live
);
3654 /* Match the peephole. */
3655 head
= peep2_insn_data
[peep2_current
].insn
;
3656 attempt
= safe_as_a
<rtx_insn
*> (
3657 peephole2_insns (PATTERN (head
), head
, &match_len
));
3658 if (attempt
!= NULL
)
3660 rtx_insn
*last
= peep2_attempt (bb
, head
, match_len
, attempt
);
3663 peep2_update_life (bb
, match_len
, last
, PREV_INSN (attempt
));
3668 /* No match: advance the buffer by one insn. */
3669 peep2_current
= peep2_buf_position (peep2_current
+ 1);
3670 peep2_current_count
--;
3674 default_rtl_profile ();
3675 for (i
= 0; i
< MAX_INSNS_PER_PEEP2
+ 1; ++i
)
3676 BITMAP_FREE (peep2_insn_data
[i
].live_before
);
3678 if (peep2_do_rebuild_jump_labels
)
3679 rebuild_jump_labels (get_insns ());
3680 if (peep2_do_cleanup_cfg
)
3681 cleanup_cfg (CLEANUP_CFG_CHANGED
);
3683 #endif /* HAVE_peephole2 */
3685 /* Common predicates for use with define_bypass. */
3687 /* True if the dependency between OUT_INSN and IN_INSN is on the store
3688 data not the address operand(s) of the store. IN_INSN and OUT_INSN
3689 must be either a single_set or a PARALLEL with SETs inside. */
3692 store_data_bypass_p (rtx_insn
*out_insn
, rtx_insn
*in_insn
)
3694 rtx out_set
, in_set
;
3695 rtx out_pat
, in_pat
;
3696 rtx out_exp
, in_exp
;
3699 in_set
= single_set (in_insn
);
3702 if (!MEM_P (SET_DEST (in_set
)))
3705 out_set
= single_set (out_insn
);
3708 if (reg_mentioned_p (SET_DEST (out_set
), SET_DEST (in_set
)))
3713 out_pat
= PATTERN (out_insn
);
3715 if (GET_CODE (out_pat
) != PARALLEL
)
3718 for (i
= 0; i
< XVECLEN (out_pat
, 0); i
++)
3720 out_exp
= XVECEXP (out_pat
, 0, i
);
3722 if (GET_CODE (out_exp
) == CLOBBER
)
3725 gcc_assert (GET_CODE (out_exp
) == SET
);
3727 if (reg_mentioned_p (SET_DEST (out_exp
), SET_DEST (in_set
)))
3734 in_pat
= PATTERN (in_insn
);
3735 gcc_assert (GET_CODE (in_pat
) == PARALLEL
);
3737 for (i
= 0; i
< XVECLEN (in_pat
, 0); i
++)
3739 in_exp
= XVECEXP (in_pat
, 0, i
);
3741 if (GET_CODE (in_exp
) == CLOBBER
)
3744 gcc_assert (GET_CODE (in_exp
) == SET
);
3746 if (!MEM_P (SET_DEST (in_exp
)))
3749 out_set
= single_set (out_insn
);
3752 if (reg_mentioned_p (SET_DEST (out_set
), SET_DEST (in_exp
)))
3757 out_pat
= PATTERN (out_insn
);
3758 gcc_assert (GET_CODE (out_pat
) == PARALLEL
);
3760 for (j
= 0; j
< XVECLEN (out_pat
, 0); j
++)
3762 out_exp
= XVECEXP (out_pat
, 0, j
);
3764 if (GET_CODE (out_exp
) == CLOBBER
)
3767 gcc_assert (GET_CODE (out_exp
) == SET
);
3769 if (reg_mentioned_p (SET_DEST (out_exp
), SET_DEST (in_exp
)))
3779 /* True if the dependency between OUT_INSN and IN_INSN is in the IF_THEN_ELSE
3780 condition, and not the THEN or ELSE branch. OUT_INSN may be either a single
3781 or multiple set; IN_INSN should be single_set for truth, but for convenience
3782 of insn categorization may be any JUMP or CALL insn. */
3785 if_test_bypass_p (rtx_insn
*out_insn
, rtx_insn
*in_insn
)
3787 rtx out_set
, in_set
;
3789 in_set
= single_set (in_insn
);
3792 gcc_assert (JUMP_P (in_insn
) || CALL_P (in_insn
));
3796 if (GET_CODE (SET_SRC (in_set
)) != IF_THEN_ELSE
)
3798 in_set
= SET_SRC (in_set
);
3800 out_set
= single_set (out_insn
);
3803 if (reg_mentioned_p (SET_DEST (out_set
), XEXP (in_set
, 1))
3804 || reg_mentioned_p (SET_DEST (out_set
), XEXP (in_set
, 2)))
3812 out_pat
= PATTERN (out_insn
);
3813 gcc_assert (GET_CODE (out_pat
) == PARALLEL
);
3815 for (i
= 0; i
< XVECLEN (out_pat
, 0); i
++)
3817 rtx exp
= XVECEXP (out_pat
, 0, i
);
3819 if (GET_CODE (exp
) == CLOBBER
)
3822 gcc_assert (GET_CODE (exp
) == SET
);
3824 if (reg_mentioned_p (SET_DEST (out_set
), XEXP (in_set
, 1))
3825 || reg_mentioned_p (SET_DEST (out_set
), XEXP (in_set
, 2)))
3834 rest_of_handle_peephole2 (void)
3836 #ifdef HAVE_peephole2
3837 peephole2_optimize ();
3844 const pass_data pass_data_peephole2
=
3846 RTL_PASS
, /* type */
3847 "peephole2", /* name */
3848 OPTGROUP_NONE
, /* optinfo_flags */
3849 TV_PEEPHOLE2
, /* tv_id */
3850 0, /* properties_required */
3851 0, /* properties_provided */
3852 0, /* properties_destroyed */
3853 0, /* todo_flags_start */
3854 TODO_df_finish
, /* todo_flags_finish */
3857 class pass_peephole2
: public rtl_opt_pass
3860 pass_peephole2 (gcc::context
*ctxt
)
3861 : rtl_opt_pass (pass_data_peephole2
, ctxt
)
3864 /* opt_pass methods: */
3865 /* The epiphany backend creates a second instance of this pass, so we need
3867 opt_pass
* clone () { return new pass_peephole2 (m_ctxt
); }
3868 virtual bool gate (function
*) { return (optimize
> 0 && flag_peephole2
); }
3869 virtual unsigned int execute (function
*)
3871 return rest_of_handle_peephole2 ();
3874 }; // class pass_peephole2
3879 make_pass_peephole2 (gcc::context
*ctxt
)
3881 return new pass_peephole2 (ctxt
);
3886 const pass_data pass_data_split_all_insns
=
3888 RTL_PASS
, /* type */
3889 "split1", /* name */
3890 OPTGROUP_NONE
, /* optinfo_flags */
3891 TV_NONE
, /* tv_id */
3892 0, /* properties_required */
3893 0, /* properties_provided */
3894 0, /* properties_destroyed */
3895 0, /* todo_flags_start */
3896 0, /* todo_flags_finish */
3899 class pass_split_all_insns
: public rtl_opt_pass
3902 pass_split_all_insns (gcc::context
*ctxt
)
3903 : rtl_opt_pass (pass_data_split_all_insns
, ctxt
)
3906 /* opt_pass methods: */
3907 /* The epiphany backend creates a second instance of this pass, so
3908 we need a clone method. */
3909 opt_pass
* clone () { return new pass_split_all_insns (m_ctxt
); }
3910 virtual unsigned int execute (function
*)
3916 }; // class pass_split_all_insns
3921 make_pass_split_all_insns (gcc::context
*ctxt
)
3923 return new pass_split_all_insns (ctxt
);
3927 rest_of_handle_split_after_reload (void)
3929 /* If optimizing, then go ahead and split insns now. */
3939 const pass_data pass_data_split_after_reload
=
3941 RTL_PASS
, /* type */
3942 "split2", /* name */
3943 OPTGROUP_NONE
, /* optinfo_flags */
3944 TV_NONE
, /* tv_id */
3945 0, /* properties_required */
3946 0, /* properties_provided */
3947 0, /* properties_destroyed */
3948 0, /* todo_flags_start */
3949 0, /* todo_flags_finish */
3952 class pass_split_after_reload
: public rtl_opt_pass
3955 pass_split_after_reload (gcc::context
*ctxt
)
3956 : rtl_opt_pass (pass_data_split_after_reload
, ctxt
)
3959 /* opt_pass methods: */
3960 virtual unsigned int execute (function
*)
3962 return rest_of_handle_split_after_reload ();
3965 }; // class pass_split_after_reload
3970 make_pass_split_after_reload (gcc::context
*ctxt
)
3972 return new pass_split_after_reload (ctxt
);
3977 const pass_data pass_data_split_before_regstack
=
3979 RTL_PASS
, /* type */
3980 "split3", /* name */
3981 OPTGROUP_NONE
, /* optinfo_flags */
3982 TV_NONE
, /* tv_id */
3983 0, /* properties_required */
3984 0, /* properties_provided */
3985 0, /* properties_destroyed */
3986 0, /* todo_flags_start */
3987 0, /* todo_flags_finish */
3990 class pass_split_before_regstack
: public rtl_opt_pass
3993 pass_split_before_regstack (gcc::context
*ctxt
)
3994 : rtl_opt_pass (pass_data_split_before_regstack
, ctxt
)
3997 /* opt_pass methods: */
3998 virtual bool gate (function
*);
3999 virtual unsigned int execute (function
*)
4005 }; // class pass_split_before_regstack
4008 pass_split_before_regstack::gate (function
*)
4010 #if HAVE_ATTR_length && defined (STACK_REGS)
4011 /* If flow2 creates new instructions which need splitting
4012 and scheduling after reload is not done, they might not be
4013 split until final which doesn't allow splitting
4014 if HAVE_ATTR_length. */
4015 # ifdef INSN_SCHEDULING
4016 return (optimize
&& !flag_schedule_insns_after_reload
);
4028 make_pass_split_before_regstack (gcc::context
*ctxt
)
4030 return new pass_split_before_regstack (ctxt
);
4034 rest_of_handle_split_before_sched2 (void)
4036 #ifdef INSN_SCHEDULING
4044 const pass_data pass_data_split_before_sched2
=
4046 RTL_PASS
, /* type */
4047 "split4", /* name */
4048 OPTGROUP_NONE
, /* optinfo_flags */
4049 TV_NONE
, /* tv_id */
4050 0, /* properties_required */
4051 0, /* properties_provided */
4052 0, /* properties_destroyed */
4053 0, /* todo_flags_start */
4054 0, /* todo_flags_finish */
4057 class pass_split_before_sched2
: public rtl_opt_pass
4060 pass_split_before_sched2 (gcc::context
*ctxt
)
4061 : rtl_opt_pass (pass_data_split_before_sched2
, ctxt
)
4064 /* opt_pass methods: */
4065 virtual bool gate (function
*)
4067 #ifdef INSN_SCHEDULING
4068 return optimize
> 0 && flag_schedule_insns_after_reload
;
4074 virtual unsigned int execute (function
*)
4076 return rest_of_handle_split_before_sched2 ();
4079 }; // class pass_split_before_sched2
4084 make_pass_split_before_sched2 (gcc::context
*ctxt
)
4086 return new pass_split_before_sched2 (ctxt
);
4091 const pass_data pass_data_split_for_shorten_branches
=
4093 RTL_PASS
, /* type */
4094 "split5", /* name */
4095 OPTGROUP_NONE
, /* optinfo_flags */
4096 TV_NONE
, /* tv_id */
4097 0, /* properties_required */
4098 0, /* properties_provided */
4099 0, /* properties_destroyed */
4100 0, /* todo_flags_start */
4101 0, /* todo_flags_finish */
4104 class pass_split_for_shorten_branches
: public rtl_opt_pass
4107 pass_split_for_shorten_branches (gcc::context
*ctxt
)
4108 : rtl_opt_pass (pass_data_split_for_shorten_branches
, ctxt
)
4111 /* opt_pass methods: */
4112 virtual bool gate (function
*)
4114 /* The placement of the splitting that we do for shorten_branches
4115 depends on whether regstack is used by the target or not. */
4116 #if HAVE_ATTR_length && !defined (STACK_REGS)
4123 virtual unsigned int execute (function
*)
4125 return split_all_insns_noflow ();
4128 }; // class pass_split_for_shorten_branches
4133 make_pass_split_for_shorten_branches (gcc::context
*ctxt
)
4135 return new pass_split_for_shorten_branches (ctxt
);
4138 /* (Re)initialize the target information after a change in target. */
4143 /* The information is zero-initialized, so we don't need to do anything
4144 first time round. */
4145 if (!this_target_recog
->x_initialized
)
4147 this_target_recog
->x_initialized
= true;
4150 memset (this_target_recog
->x_bool_attr_masks
, 0,
4151 sizeof (this_target_recog
->x_bool_attr_masks
));
4152 for (int i
= 0; i
< LAST_INSN_CODE
; ++i
)
4153 if (this_target_recog
->x_op_alt
[i
])
4155 free (this_target_recog
->x_op_alt
[i
]);
4156 this_target_recog
->x_op_alt
[i
] = 0;