1 /* Compute register class preferences for pseudo-registers.
2 Copyright (C) 1987, 1988, 1991, 1992, 1993, 1994, 1995, 1996
3 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 3, or (at your option) any later
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
23 /* This file contains two passes of the compiler: reg_scan and reg_class.
24 It also defines some tables of information about the hardware registers
25 and a function init_reg_sets to initialize the tables. */
29 #include "coretypes.h"
31 #include "hard-reg-set.h"
36 #include "basic-block.h"
38 #include "addresses.h"
40 #include "insn-config.h"
50 #include "tree-pass.h"
53 /* Maximum register number used in this function, plus one. */
57 static void init_reg_sets_1 (void);
58 static void init_reg_autoinc (void);
60 /* If we have auto-increment or auto-decrement and we can have secondary
61 reloads, we are not allowed to use classes requiring secondary
62 reloads for pseudos auto-incremented since reload can't handle it. */
63 /* We leave it to target hooks to decide if we have secondary reloads, so
64 assume that we might have them. */
65 #if defined(AUTO_INC_DEC) /* */
66 #define FORBIDDEN_INC_DEC_CLASSES
69 /* Register tables used by many passes. */
71 /* Indexed by hard register number, contains 1 for registers
72 that are fixed use (stack pointer, pc, frame pointer, etc.).
73 These are the registers that cannot be used to allocate
74 a pseudo reg for general use. */
76 char fixed_regs
[FIRST_PSEUDO_REGISTER
];
78 /* Same info as a HARD_REG_SET. */
80 HARD_REG_SET fixed_reg_set
;
82 /* Data for initializing the above. */
84 static char initial_fixed_regs
[] = FIXED_REGISTERS
;
86 /* Indexed by hard register number, contains 1 for registers
87 that are fixed use or are clobbered by function calls.
88 These are the registers that cannot be used to allocate
89 a pseudo reg whose life crosses calls unless we are able
90 to save/restore them across the calls. */
92 char call_used_regs
[FIRST_PSEUDO_REGISTER
];
94 /* Same info as a HARD_REG_SET. */
96 HARD_REG_SET call_used_reg_set
;
98 /* HARD_REG_SET of registers we want to avoid caller saving. */
99 HARD_REG_SET losing_caller_save_reg_set
;
101 /* Data for initializing the above. */
103 static char initial_call_used_regs
[] = CALL_USED_REGISTERS
;
105 /* This is much like call_used_regs, except it doesn't have to
106 be a superset of FIXED_REGISTERS. This vector indicates
107 what is really call clobbered, and is used when defining
108 regs_invalidated_by_call. */
110 #ifdef CALL_REALLY_USED_REGISTERS
111 static char initial_call_really_used_regs
[] = CALL_REALLY_USED_REGISTERS
;
112 char call_really_used_regs
[FIRST_PSEUDO_REGISTER
];
115 #ifdef CALL_REALLY_USED_REGISTERS
116 #define CALL_REALLY_USED_REGNO_P(X) call_really_used_regs[X]
118 #define CALL_REALLY_USED_REGNO_P(X) call_used_regs[X]
122 /* Indexed by hard register number, contains 1 for registers that are
123 fixed use or call used registers that cannot hold quantities across
124 calls even if we are willing to save and restore them. call fixed
125 registers are a subset of call used registers. */
127 char call_fixed_regs
[FIRST_PSEUDO_REGISTER
];
129 /* The same info as a HARD_REG_SET. */
131 HARD_REG_SET call_fixed_reg_set
;
133 /* Indexed by hard register number, contains 1 for registers
134 that are being used for global register decls.
135 These must be exempt from ordinary flow analysis
136 and are also considered fixed. */
138 char global_regs
[FIRST_PSEUDO_REGISTER
];
140 /* Contains 1 for registers that are set or clobbered by calls. */
141 /* ??? Ideally, this would be just call_used_regs plus global_regs, but
142 for someone's bright idea to have call_used_regs strictly include
143 fixed_regs. Which leaves us guessing as to the set of fixed_regs
144 that are actually preserved. We know for sure that those associated
145 with the local stack frame are safe, but scant others. */
147 HARD_REG_SET regs_invalidated_by_call
;
149 /* Table of register numbers in the order in which to try to use them. */
150 #ifdef REG_ALLOC_ORDER
151 int reg_alloc_order
[FIRST_PSEUDO_REGISTER
] = REG_ALLOC_ORDER
;
153 /* The inverse of reg_alloc_order. */
154 int inv_reg_alloc_order
[FIRST_PSEUDO_REGISTER
];
157 /* For each reg class, a HARD_REG_SET saying which registers are in it. */
159 HARD_REG_SET reg_class_contents
[N_REG_CLASSES
];
161 /* The same information, but as an array of unsigned ints. We copy from
162 these unsigned ints to the table above. We do this so the tm.h files
163 do not have to be aware of the wordsize for machines with <= 64 regs.
164 Note that we hard-code 32 here, not HOST_BITS_PER_INT. */
167 ((FIRST_PSEUDO_REGISTER + (32 - 1)) / 32)
169 static const unsigned int_reg_class_contents
[N_REG_CLASSES
][N_REG_INTS
]
170 = REG_CLASS_CONTENTS
;
172 /* For each reg class, number of regs it contains. */
174 unsigned int reg_class_size
[N_REG_CLASSES
];
176 /* For each reg class, table listing all the containing classes. */
178 static enum reg_class reg_class_superclasses
[N_REG_CLASSES
][N_REG_CLASSES
];
180 /* For each reg class, table listing all the classes contained in it. */
182 static enum reg_class reg_class_subclasses
[N_REG_CLASSES
][N_REG_CLASSES
];
184 /* For each pair of reg classes,
185 a largest reg class contained in their union. */
187 enum reg_class reg_class_subunion
[N_REG_CLASSES
][N_REG_CLASSES
];
189 /* For each pair of reg classes,
190 the smallest reg class containing their union. */
192 enum reg_class reg_class_superunion
[N_REG_CLASSES
][N_REG_CLASSES
];
194 /* Array containing all of the register names. */
196 const char * reg_names
[FIRST_PSEUDO_REGISTER
];
198 /* Data for initializing the above. */
200 const char * initial_reg_names
[] = REGISTER_NAMES
;
202 /* Array containing all of the register class names. */
204 const char * reg_class_names
[] = REG_CLASS_NAMES
;
206 /* For each hard register, the widest mode object that it can contain.
207 This will be a MODE_INT mode if the register can hold integers. Otherwise
208 it will be a MODE_FLOAT or a MODE_CC mode, whichever is valid for the
211 enum machine_mode reg_raw_mode
[FIRST_PSEUDO_REGISTER
];
213 /* 1 if there is a register of given mode. */
215 bool have_regs_of_mode
[MAX_MACHINE_MODE
];
217 /* 1 if class does contain register of given mode. */
219 static char contains_reg_of_mode
[N_REG_CLASSES
] [MAX_MACHINE_MODE
];
221 typedef unsigned short move_table
[N_REG_CLASSES
];
223 /* Maximum cost of moving from a register in one class to a register in
224 another class. Based on REGISTER_MOVE_COST. */
226 static move_table
*move_cost
[MAX_MACHINE_MODE
];
228 /* Similar, but here we don't have to move if the first index is a subset
229 of the second so in that case the cost is zero. */
231 static move_table
*may_move_in_cost
[MAX_MACHINE_MODE
];
233 /* Similar, but here we don't have to move if the first index is a superset
234 of the second so in that case the cost is zero. */
236 static move_table
*may_move_out_cost
[MAX_MACHINE_MODE
];
238 /* Keep track of the last mode we initialized move costs for. */
239 static int last_mode_for_init_move_cost
;
241 #ifdef FORBIDDEN_INC_DEC_CLASSES
243 /* These are the classes that regs which are auto-incremented or decremented
246 static int forbidden_inc_dec_class
[N_REG_CLASSES
];
248 /* Indexed by n, is nonzero if (REG n) is used in an auto-inc or auto-dec
251 static char *in_inc_dec
;
253 #endif /* FORBIDDEN_INC_DEC_CLASSES */
255 /* Sample MEM values for use by memory_move_secondary_cost. */
257 static GTY(()) rtx top_of_stack
[MAX_MACHINE_MODE
];
259 /* No more global register variables may be declared; true once
260 regclass has been initialized. */
262 static int no_global_reg_vars
= 0;
264 /* Specify number of hard registers given machine mode occupy. */
265 unsigned char hard_regno_nregs
[FIRST_PSEUDO_REGISTER
][MAX_MACHINE_MODE
];
267 /* Given a register bitmap, turn on the bits in a HARD_REG_SET that
268 correspond to the hard registers, if any, set in that map. This
269 could be done far more efficiently by having all sorts of special-cases
270 with moving single words, but probably isn't worth the trouble. */
273 reg_set_to_hard_reg_set (HARD_REG_SET
*to
, const_bitmap from
)
278 EXECUTE_IF_SET_IN_BITMAP (from
, 0, i
, bi
)
280 if (i
>= FIRST_PSEUDO_REGISTER
)
282 SET_HARD_REG_BIT (*to
, i
);
287 /* Function called only once to initialize the above data on reg usage.
288 Once this is done, various switches may override. */
295 /* First copy the register information from the initial int form into
298 for (i
= 0; i
< N_REG_CLASSES
; i
++)
300 CLEAR_HARD_REG_SET (reg_class_contents
[i
]);
302 /* Note that we hard-code 32 here, not HOST_BITS_PER_INT. */
303 for (j
= 0; j
< FIRST_PSEUDO_REGISTER
; j
++)
304 if (int_reg_class_contents
[i
][j
/ 32]
305 & ((unsigned) 1 << (j
% 32)))
306 SET_HARD_REG_BIT (reg_class_contents
[i
], j
);
309 memset (global_regs
, 0, sizeof global_regs
);
311 /* Processing of command-line options like -ffixed needs to know the
312 initial set of register names, so initialize that now. */
313 gcc_assert (sizeof reg_names
== sizeof initial_reg_names
);
314 memcpy (reg_names
, initial_reg_names
, sizeof reg_names
);
317 /* Initialize may_move_cost and friends for mode M. */
320 init_move_cost (enum machine_mode m
)
322 static unsigned short last_move_cost
[N_REG_CLASSES
][N_REG_CLASSES
];
323 bool all_match
= true;
326 gcc_assert (have_regs_of_mode
[m
]);
327 for (i
= 0; i
< N_REG_CLASSES
; i
++)
328 if (contains_reg_of_mode
[i
][m
])
329 for (j
= 0; j
< N_REG_CLASSES
; j
++)
332 if (!contains_reg_of_mode
[j
][m
])
336 cost
= REGISTER_MOVE_COST (m
, i
, j
);
337 gcc_assert (cost
< 65535);
339 all_match
&= (last_move_cost
[i
][j
] == cost
);
340 last_move_cost
[i
][j
] = cost
;
342 if (all_match
&& last_mode_for_init_move_cost
!= -1)
344 move_cost
[m
] = move_cost
[last_mode_for_init_move_cost
];
345 may_move_in_cost
[m
] = may_move_in_cost
[last_mode_for_init_move_cost
];
346 may_move_out_cost
[m
] = may_move_out_cost
[last_mode_for_init_move_cost
];
349 last_mode_for_init_move_cost
= m
;
350 move_cost
[m
] = (move_table
*)xmalloc (sizeof (move_table
)
352 may_move_in_cost
[m
] = (move_table
*)xmalloc (sizeof (move_table
)
354 may_move_out_cost
[m
] = (move_table
*)xmalloc (sizeof (move_table
)
356 for (i
= 0; i
< N_REG_CLASSES
; i
++)
357 if (contains_reg_of_mode
[i
][m
])
358 for (j
= 0; j
< N_REG_CLASSES
; j
++)
361 enum reg_class
*p1
, *p2
;
363 if (last_move_cost
[i
][j
] == 65535)
365 move_cost
[m
][i
][j
] = 65535;
366 may_move_in_cost
[m
][i
][j
] = 65535;
367 may_move_out_cost
[m
][i
][j
] = 65535;
371 cost
= last_move_cost
[i
][j
];
373 for (p2
= ®_class_subclasses
[j
][0];
374 *p2
!= LIM_REG_CLASSES
; p2
++)
375 if (*p2
!= i
&& contains_reg_of_mode
[*p2
][m
])
376 cost
= MAX (cost
, move_cost
[m
][i
][*p2
]);
378 for (p1
= ®_class_subclasses
[i
][0];
379 *p1
!= LIM_REG_CLASSES
; p1
++)
380 if (*p1
!= j
&& contains_reg_of_mode
[*p1
][m
])
381 cost
= MAX (cost
, move_cost
[m
][*p1
][j
]);
383 gcc_assert (cost
<= 65535);
384 move_cost
[m
][i
][j
] = cost
;
386 if (reg_class_subset_p (i
, j
))
387 may_move_in_cost
[m
][i
][j
] = 0;
389 may_move_in_cost
[m
][i
][j
] = cost
;
391 if (reg_class_subset_p (j
, i
))
392 may_move_out_cost
[m
][i
][j
] = 0;
394 may_move_out_cost
[m
][i
][j
] = cost
;
398 for (j
= 0; j
< N_REG_CLASSES
; j
++)
400 move_cost
[m
][i
][j
] = 65535;
401 may_move_in_cost
[m
][i
][j
] = 65535;
402 may_move_out_cost
[m
][i
][j
] = 65535;
406 /* After switches have been processed, which perhaps alter
407 `fixed_regs' and `call_used_regs', convert them to HARD_REG_SETs. */
410 init_reg_sets_1 (void)
413 unsigned int /* enum machine_mode */ m
;
415 /* Sanity check: make sure the target macros FIXED_REGISTERS and
416 CALL_USED_REGISTERS had the right number of initializers. */
417 gcc_assert (sizeof fixed_regs
== sizeof initial_fixed_regs
);
418 gcc_assert (sizeof call_used_regs
== sizeof initial_call_used_regs
);
420 memcpy (fixed_regs
, initial_fixed_regs
, sizeof fixed_regs
);
421 memcpy (call_used_regs
, initial_call_used_regs
, sizeof call_used_regs
);
423 /* Likewise for call_really_used_regs. */
424 #ifdef CALL_REALLY_USED_REGISTERS
425 gcc_assert (sizeof call_really_used_regs
426 == sizeof initial_call_really_used_regs
);
427 memcpy (call_really_used_regs
, initial_call_really_used_regs
,
428 sizeof call_really_used_regs
);
431 /* And similarly for reg_names. */
432 gcc_assert (sizeof reg_names
== sizeof initial_reg_names
);
433 memcpy (reg_names
, initial_reg_names
, sizeof reg_names
);
435 #ifdef REG_ALLOC_ORDER
436 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
437 inv_reg_alloc_order
[reg_alloc_order
[i
]] = i
;
440 /* This macro allows the fixed or call-used registers
441 and the register classes to depend on target flags. */
443 #ifdef CONDITIONAL_REGISTER_USAGE
444 CONDITIONAL_REGISTER_USAGE
;
447 /* Compute number of hard regs in each class. */
449 memset (reg_class_size
, 0, sizeof reg_class_size
);
450 for (i
= 0; i
< N_REG_CLASSES
; i
++)
451 for (j
= 0; j
< FIRST_PSEUDO_REGISTER
; j
++)
452 if (TEST_HARD_REG_BIT (reg_class_contents
[i
], j
))
455 /* Initialize the table of subunions.
456 reg_class_subunion[I][J] gets the largest-numbered reg-class
457 that is contained in the union of classes I and J. */
459 memset (reg_class_subunion
, 0, sizeof reg_class_subunion
);
460 for (i
= 0; i
< N_REG_CLASSES
; i
++)
462 for (j
= 0; j
< N_REG_CLASSES
; j
++)
467 COPY_HARD_REG_SET (c
, reg_class_contents
[i
]);
468 IOR_HARD_REG_SET (c
, reg_class_contents
[j
]);
469 for (k
= 0; k
< N_REG_CLASSES
; k
++)
470 if (hard_reg_set_subset_p (reg_class_contents
[k
], c
)
471 && !hard_reg_set_subset_p (reg_class_contents
[k
],
473 [(int) reg_class_subunion
[i
][j
]]))
474 reg_class_subunion
[i
][j
] = (enum reg_class
) k
;
478 /* Initialize the table of superunions.
479 reg_class_superunion[I][J] gets the smallest-numbered reg-class
480 containing the union of classes I and J. */
482 memset (reg_class_superunion
, 0, sizeof reg_class_superunion
);
483 for (i
= 0; i
< N_REG_CLASSES
; i
++)
485 for (j
= 0; j
< N_REG_CLASSES
; j
++)
490 COPY_HARD_REG_SET (c
, reg_class_contents
[i
]);
491 IOR_HARD_REG_SET (c
, reg_class_contents
[j
]);
492 for (k
= 0; k
< N_REG_CLASSES
; k
++)
493 if (hard_reg_set_subset_p (c
, reg_class_contents
[k
]))
496 reg_class_superunion
[i
][j
] = (enum reg_class
) k
;
500 /* Initialize the tables of subclasses and superclasses of each reg class.
501 First clear the whole table, then add the elements as they are found. */
503 for (i
= 0; i
< N_REG_CLASSES
; i
++)
505 for (j
= 0; j
< N_REG_CLASSES
; j
++)
507 reg_class_superclasses
[i
][j
] = LIM_REG_CLASSES
;
508 reg_class_subclasses
[i
][j
] = LIM_REG_CLASSES
;
512 for (i
= 0; i
< N_REG_CLASSES
; i
++)
514 if (i
== (int) NO_REGS
)
517 for (j
= i
+ 1; j
< N_REG_CLASSES
; j
++)
518 if (hard_reg_set_subset_p (reg_class_contents
[i
],
519 reg_class_contents
[j
]))
521 /* Reg class I is a subclass of J.
522 Add J to the table of superclasses of I. */
525 p
= ®_class_superclasses
[i
][0];
526 while (*p
!= LIM_REG_CLASSES
) p
++;
527 *p
= (enum reg_class
) j
;
528 /* Add I to the table of superclasses of J. */
529 p
= ®_class_subclasses
[j
][0];
530 while (*p
!= LIM_REG_CLASSES
) p
++;
531 *p
= (enum reg_class
) i
;
535 /* Initialize "constant" tables. */
537 CLEAR_HARD_REG_SET (fixed_reg_set
);
538 CLEAR_HARD_REG_SET (call_used_reg_set
);
539 CLEAR_HARD_REG_SET (call_fixed_reg_set
);
540 CLEAR_HARD_REG_SET (regs_invalidated_by_call
);
541 CLEAR_HARD_REG_SET (losing_caller_save_reg_set
);
543 memcpy (call_fixed_regs
, fixed_regs
, sizeof call_fixed_regs
);
545 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
547 /* call_used_regs must include fixed_regs. */
548 gcc_assert (!fixed_regs
[i
] || call_used_regs
[i
]);
549 #ifdef CALL_REALLY_USED_REGISTERS
550 /* call_used_regs must include call_really_used_regs. */
551 gcc_assert (!call_really_used_regs
[i
] || call_used_regs
[i
]);
555 SET_HARD_REG_BIT (fixed_reg_set
, i
);
557 if (call_used_regs
[i
])
558 SET_HARD_REG_BIT (call_used_reg_set
, i
);
559 if (call_fixed_regs
[i
])
560 SET_HARD_REG_BIT (call_fixed_reg_set
, i
);
561 if (CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (i
)))
562 SET_HARD_REG_BIT (losing_caller_save_reg_set
, i
);
564 /* There are a couple of fixed registers that we know are safe to
565 exclude from being clobbered by calls:
567 The frame pointer is always preserved across calls. The arg pointer
568 is if it is fixed. The stack pointer usually is, unless
569 RETURN_POPS_ARGS, in which case an explicit CLOBBER will be present.
570 If we are generating PIC code, the PIC offset table register is
571 preserved across calls, though the target can override that. */
573 if (i
== STACK_POINTER_REGNUM
)
575 else if (global_regs
[i
])
576 SET_HARD_REG_BIT (regs_invalidated_by_call
, i
);
577 else if (i
== FRAME_POINTER_REGNUM
)
579 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
580 else if (i
== HARD_FRAME_POINTER_REGNUM
)
583 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
584 else if (i
== ARG_POINTER_REGNUM
&& fixed_regs
[i
])
587 #ifndef PIC_OFFSET_TABLE_REG_CALL_CLOBBERED
588 else if (i
== (unsigned) PIC_OFFSET_TABLE_REGNUM
&& fixed_regs
[i
])
591 else if (CALL_REALLY_USED_REGNO_P (i
))
592 SET_HARD_REG_BIT (regs_invalidated_by_call
, i
);
595 /* Preserve global registers if called more than once. */
596 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
600 fixed_regs
[i
] = call_used_regs
[i
] = call_fixed_regs
[i
] = 1;
601 SET_HARD_REG_BIT (fixed_reg_set
, i
);
602 SET_HARD_REG_BIT (call_used_reg_set
, i
);
603 SET_HARD_REG_BIT (call_fixed_reg_set
, i
);
607 memset (have_regs_of_mode
, 0, sizeof (have_regs_of_mode
));
608 memset (contains_reg_of_mode
, 0, sizeof (contains_reg_of_mode
));
609 for (m
= 0; m
< (unsigned int) MAX_MACHINE_MODE
; m
++)
611 HARD_REG_SET ok_regs
;
612 CLEAR_HARD_REG_SET (ok_regs
);
613 for (j
= 0; j
< FIRST_PSEUDO_REGISTER
; j
++)
614 if (!fixed_regs
[j
] && HARD_REGNO_MODE_OK (j
, m
))
615 SET_HARD_REG_BIT (ok_regs
, j
);
617 for (i
= 0; i
< N_REG_CLASSES
; i
++)
618 if ((unsigned) CLASS_MAX_NREGS (i
, m
) <= reg_class_size
[i
]
619 && hard_reg_set_intersect_p (ok_regs
, reg_class_contents
[i
]))
621 contains_reg_of_mode
[i
][m
] = 1;
622 have_regs_of_mode
[m
] = 1;
626 /* Reset move_cost and friends, making sure we only free shared
627 table entries once. */
628 for (i
= 0; i
< MAX_MACHINE_MODE
; i
++)
631 for (j
= 0; j
< i
&& move_cost
[i
] != move_cost
[j
]; j
++)
636 free (may_move_in_cost
[i
]);
637 free (may_move_out_cost
[i
]);
640 memset (move_cost
, 0, sizeof move_cost
);
641 memset (may_move_in_cost
, 0, sizeof may_move_in_cost
);
642 memset (may_move_out_cost
, 0, sizeof may_move_out_cost
);
643 last_mode_for_init_move_cost
= -1;
646 /* Compute the table of register modes.
647 These values are used to record death information for individual registers
648 (as opposed to a multi-register mode).
649 This function might be invoked more than once, if the target has support
650 for changing register usage conventions on a per-function basis.
654 init_reg_modes_target (void)
658 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
659 for (j
= 0; j
< MAX_MACHINE_MODE
; j
++)
660 hard_regno_nregs
[i
][j
] = HARD_REGNO_NREGS(i
, (enum machine_mode
)j
);
662 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
664 reg_raw_mode
[i
] = choose_hard_reg_mode (i
, 1, false);
666 /* If we couldn't find a valid mode, just use the previous mode.
667 ??? One situation in which we need to do this is on the mips where
668 HARD_REGNO_NREGS (fpreg, [SD]Fmode) returns 2. Ideally we'd like
669 to use DF mode for the even registers and VOIDmode for the odd
670 (for the cpu models where the odd ones are inaccessible). */
671 if (reg_raw_mode
[i
] == VOIDmode
)
672 reg_raw_mode
[i
] = i
== 0 ? word_mode
: reg_raw_mode
[i
-1];
676 /* Finish initializing the register sets and initialize the register modes.
677 This function might be invoked more than once, if the target has support
678 for changing register usage conventions on a per-function basis.
684 /* This finishes what was started by init_reg_sets, but couldn't be done
685 until after register usage was specified. */
691 /* Initialize some fake stack-frame MEM references for use in
692 memory_move_secondary_cost. */
695 init_fake_stack_mems (void)
700 for (i
= 0; i
< MAX_MACHINE_MODE
; i
++)
701 top_of_stack
[i
] = gen_rtx_MEM (i
, stack_pointer_rtx
);
706 /* Compute extra cost of moving registers to/from memory due to reloads.
707 Only needed if secondary reloads are required for memory moves. */
710 memory_move_secondary_cost (enum machine_mode mode
, enum reg_class
class, int in
)
712 enum reg_class altclass
;
713 int partial_cost
= 0;
714 /* We need a memory reference to feed to SECONDARY... macros. */
715 /* mem may be unused even if the SECONDARY_ macros are defined. */
716 rtx mem ATTRIBUTE_UNUSED
= top_of_stack
[(int) mode
];
719 altclass
= secondary_reload_class (in
? 1 : 0, class, mode
, mem
);
721 if (altclass
== NO_REGS
)
725 partial_cost
= REGISTER_MOVE_COST (mode
, altclass
, class);
727 partial_cost
= REGISTER_MOVE_COST (mode
, class, altclass
);
729 if (class == altclass
)
730 /* This isn't simply a copy-to-temporary situation. Can't guess
731 what it is, so MEMORY_MOVE_COST really ought not to be calling
734 I'm tempted to put in an assert here, but returning this will
735 probably only give poor estimates, which is what we would've
736 had before this code anyways. */
739 /* Check if the secondary reload register will also need a
741 return memory_move_secondary_cost (mode
, altclass
, in
) + partial_cost
;
744 /* Return a machine mode that is legitimate for hard reg REGNO and large
745 enough to save nregs. If we can't find one, return VOIDmode.
746 If CALL_SAVED is true, only consider modes that are call saved. */
749 choose_hard_reg_mode (unsigned int regno ATTRIBUTE_UNUSED
,
750 unsigned int nregs
, bool call_saved
)
752 unsigned int /* enum machine_mode */ m
;
753 enum machine_mode found_mode
= VOIDmode
, mode
;
755 /* We first look for the largest integer mode that can be validly
756 held in REGNO. If none, we look for the largest floating-point mode.
757 If we still didn't find a valid mode, try CCmode. */
759 for (mode
= GET_CLASS_NARROWEST_MODE (MODE_INT
);
761 mode
= GET_MODE_WIDER_MODE (mode
))
762 if ((unsigned) hard_regno_nregs
[regno
][mode
] == nregs
763 && HARD_REGNO_MODE_OK (regno
, mode
)
764 && (! call_saved
|| ! HARD_REGNO_CALL_PART_CLOBBERED (regno
, mode
)))
767 if (found_mode
!= VOIDmode
)
770 for (mode
= GET_CLASS_NARROWEST_MODE (MODE_FLOAT
);
772 mode
= GET_MODE_WIDER_MODE (mode
))
773 if ((unsigned) hard_regno_nregs
[regno
][mode
] == nregs
774 && HARD_REGNO_MODE_OK (regno
, mode
)
775 && (! call_saved
|| ! HARD_REGNO_CALL_PART_CLOBBERED (regno
, mode
)))
778 if (found_mode
!= VOIDmode
)
781 for (mode
= GET_CLASS_NARROWEST_MODE (MODE_VECTOR_FLOAT
);
783 mode
= GET_MODE_WIDER_MODE (mode
))
784 if ((unsigned) hard_regno_nregs
[regno
][mode
] == nregs
785 && HARD_REGNO_MODE_OK (regno
, mode
)
786 && (! call_saved
|| ! HARD_REGNO_CALL_PART_CLOBBERED (regno
, mode
)))
789 if (found_mode
!= VOIDmode
)
792 for (mode
= GET_CLASS_NARROWEST_MODE (MODE_VECTOR_INT
);
794 mode
= GET_MODE_WIDER_MODE (mode
))
795 if ((unsigned) hard_regno_nregs
[regno
][mode
] == nregs
796 && HARD_REGNO_MODE_OK (regno
, mode
)
797 && (! call_saved
|| ! HARD_REGNO_CALL_PART_CLOBBERED (regno
, mode
)))
800 if (found_mode
!= VOIDmode
)
803 /* Iterate over all of the CCmodes. */
804 for (m
= (unsigned int) CCmode
; m
< (unsigned int) NUM_MACHINE_MODES
; ++m
)
806 mode
= (enum machine_mode
) m
;
807 if ((unsigned) hard_regno_nregs
[regno
][mode
] == nregs
808 && HARD_REGNO_MODE_OK (regno
, mode
)
809 && (! call_saved
|| ! HARD_REGNO_CALL_PART_CLOBBERED (regno
, mode
)))
813 /* We can't find a mode valid for this register. */
817 /* Specify the usage characteristics of the register named NAME.
818 It should be a fixed register if FIXED and a
819 call-used register if CALL_USED. */
822 fix_register (const char *name
, int fixed
, int call_used
)
826 /* Decode the name and update the primary form of
827 the register info. */
829 if ((i
= decode_reg_name (name
)) >= 0)
831 if ((i
== STACK_POINTER_REGNUM
832 #ifdef HARD_FRAME_POINTER_REGNUM
833 || i
== HARD_FRAME_POINTER_REGNUM
835 || i
== FRAME_POINTER_REGNUM
838 && (fixed
== 0 || call_used
== 0))
840 static const char * const what_option
[2][2] = {
841 { "call-saved", "call-used" },
842 { "no-such-option", "fixed" }};
844 error ("can't use '%s' as a %s register", name
,
845 what_option
[fixed
][call_used
]);
849 initial_fixed_regs
[i
] = fixed
;
850 initial_call_used_regs
[i
] = call_used
;
851 #ifdef CALL_REALLY_USED_REGISTERS
853 initial_call_really_used_regs
[i
] = call_used
;
859 warning (0, "unknown register name: %s", name
);
863 /* Mark register number I as global. */
866 globalize_reg (int i
)
868 if (fixed_regs
[i
] == 0 && no_global_reg_vars
)
869 error ("global register variable follows a function definition");
873 warning (0, "register used for two global register variables");
877 if (call_used_regs
[i
] && ! fixed_regs
[i
])
878 warning (0, "call-clobbered register used for global register variable");
882 /* If we're globalizing the frame pointer, we need to set the
883 appropriate regs_invalidated_by_call bit, even if it's already
884 set in fixed_regs. */
885 if (i
!= STACK_POINTER_REGNUM
)
886 SET_HARD_REG_BIT (regs_invalidated_by_call
, i
);
888 /* If already fixed, nothing else to do. */
892 fixed_regs
[i
] = call_used_regs
[i
] = call_fixed_regs
[i
] = 1;
893 #ifdef CALL_REALLY_USED_REGISTERS
894 call_really_used_regs
[i
] = 1;
897 SET_HARD_REG_BIT (fixed_reg_set
, i
);
898 SET_HARD_REG_BIT (call_used_reg_set
, i
);
899 SET_HARD_REG_BIT (call_fixed_reg_set
, i
);
902 /* Now the data and code for the `regclass' pass, which happens
903 just before local-alloc. */
905 /* The `costs' struct records the cost of using a hard register of each class
906 and of using memory for each pseudo. We use this data to set up
907 register class preferences. */
911 int cost
[N_REG_CLASSES
];
915 /* Structure used to record preferences of given pseudo. */
918 /* (enum reg_class) prefclass is the preferred class. May be
919 NO_REGS if no class is better than memory. */
922 /* altclass is a register class that we should use for allocating
923 pseudo if no register in the preferred class is available.
924 If no register in this class is available, memory is preferred.
926 It might appear to be more general to have a bitmask of classes here,
927 but since it is recommended that there be a class corresponding to the
928 union of most major pair of classes, that generality is not required. */
932 /* Record the cost of each class for each pseudo. */
934 static struct costs
*costs
;
936 /* Initialized once, and used to initialize cost values for each insn. */
938 static struct costs init_cost
;
940 /* Record preferences of each pseudo.
941 This is available after `regclass' is run. */
943 static struct reg_pref
*reg_pref
;
945 /* Frequency of executions of current insn. */
947 static int frequency
;
949 static rtx
scan_one_insn (rtx
, int);
950 static void record_operand_costs (rtx
, struct costs
*, struct reg_pref
*);
951 static void dump_regclass (FILE *);
952 static void record_reg_classes (int, int, rtx
*, enum machine_mode
*,
953 const char **, rtx
, struct costs
*,
955 static int copy_cost (rtx
, enum machine_mode
, enum reg_class
, int,
956 secondary_reload_info
*);
957 static void record_address_regs (enum machine_mode
, rtx
, int, enum rtx_code
,
959 #ifdef FORBIDDEN_INC_DEC_CLASSES
960 static int auto_inc_dec_reg_p (rtx
, enum machine_mode
);
962 static void reg_scan_mark_refs (rtx
, rtx
);
964 /* Wrapper around REGNO_OK_FOR_INDEX_P, to allow pseudo registers. */
967 ok_for_index_p_nonstrict (rtx reg
)
969 unsigned regno
= REGNO (reg
);
970 return regno
>= FIRST_PSEUDO_REGISTER
|| REGNO_OK_FOR_INDEX_P (regno
);
973 /* A version of regno_ok_for_base_p for use during regclass, when all pseudos
974 should count as OK. Arguments as for regno_ok_for_base_p. */
977 ok_for_base_p_nonstrict (rtx reg
, enum machine_mode mode
,
978 enum rtx_code outer_code
, enum rtx_code index_code
)
980 unsigned regno
= REGNO (reg
);
981 if (regno
>= FIRST_PSEUDO_REGISTER
)
984 return ok_for_base_p_1 (regno
, mode
, outer_code
, index_code
);
987 /* Return the reg_class in which pseudo reg number REGNO is best allocated.
988 This function is sometimes called before the info has been computed.
989 When that happens, just return GENERAL_REGS, which is innocuous. */
992 reg_preferred_class (int regno
)
996 return (enum reg_class
) reg_pref
[regno
].prefclass
;
1000 reg_alternate_class (int regno
)
1005 return (enum reg_class
) reg_pref
[regno
].altclass
;
1008 /* Initialize some global data for this pass. */
1011 regclass_init (void)
1016 df_compute_regs_ever_live (true);
1018 init_cost
.mem_cost
= 10000;
1019 for (i
= 0; i
< N_REG_CLASSES
; i
++)
1020 init_cost
.cost
[i
] = 10000;
1022 /* This prevents dump_flow_info from losing if called
1023 before regclass is run. */
1026 /* No more global register variables may be declared. */
1027 no_global_reg_vars
= 1;
1031 struct tree_opt_pass pass_regclass_init
=
1033 "regclass", /* name */
1035 regclass_init
, /* execute */
1038 0, /* static_pass_number */
1040 0, /* properties_required */
1041 0, /* properties_provided */
1042 0, /* properties_destroyed */
1043 0, /* todo_flags_start */
1044 0, /* todo_flags_finish */
1050 /* Dump register costs. */
1052 dump_regclass (FILE *dump
)
1055 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
1057 int /* enum reg_class */ class;
1060 fprintf (dump
, " Register %i costs:", i
);
1061 for (class = 0; class < (int) N_REG_CLASSES
; class++)
1062 if (contains_reg_of_mode
[(enum reg_class
) class][PSEUDO_REGNO_MODE (i
)]
1063 #ifdef FORBIDDEN_INC_DEC_CLASSES
1065 || !forbidden_inc_dec_class
[(enum reg_class
) class])
1067 #ifdef CANNOT_CHANGE_MODE_CLASS
1068 && ! invalid_mode_change_p (i
, (enum reg_class
) class,
1069 PSEUDO_REGNO_MODE (i
))
1072 fprintf (dump
, " %s:%i", reg_class_names
[class],
1073 costs
[i
].cost
[(enum reg_class
) class]);
1074 fprintf (dump
, " MEM:%i\n", costs
[i
].mem_cost
);
1080 /* Calculate the costs of insn operands. */
1083 record_operand_costs (rtx insn
, struct costs
*op_costs
,
1084 struct reg_pref
*reg_pref
)
1086 const char *constraints
[MAX_RECOG_OPERANDS
];
1087 enum machine_mode modes
[MAX_RECOG_OPERANDS
];
1090 for (i
= 0; i
< recog_data
.n_operands
; i
++)
1092 constraints
[i
] = recog_data
.constraints
[i
];
1093 modes
[i
] = recog_data
.operand_mode
[i
];
1096 /* If we get here, we are set up to record the costs of all the
1097 operands for this insn. Start by initializing the costs.
1098 Then handle any address registers. Finally record the desired
1099 classes for any pseudos, doing it twice if some pair of
1100 operands are commutative. */
1102 for (i
= 0; i
< recog_data
.n_operands
; i
++)
1104 op_costs
[i
] = init_cost
;
1106 if (GET_CODE (recog_data
.operand
[i
]) == SUBREG
)
1107 recog_data
.operand
[i
] = SUBREG_REG (recog_data
.operand
[i
]);
1109 if (MEM_P (recog_data
.operand
[i
]))
1110 record_address_regs (GET_MODE (recog_data
.operand
[i
]),
1111 XEXP (recog_data
.operand
[i
], 0),
1112 0, MEM
, SCRATCH
, frequency
* 2);
1113 else if (constraints
[i
][0] == 'p'
1114 || EXTRA_ADDRESS_CONSTRAINT (constraints
[i
][0], constraints
[i
]))
1115 record_address_regs (VOIDmode
, recog_data
.operand
[i
], 0, ADDRESS
,
1116 SCRATCH
, frequency
* 2);
1119 /* Check for commutative in a separate loop so everything will
1120 have been initialized. We must do this even if one operand
1121 is a constant--see addsi3 in m68k.md. */
1123 for (i
= 0; i
< (int) recog_data
.n_operands
- 1; i
++)
1124 if (constraints
[i
][0] == '%')
1126 const char *xconstraints
[MAX_RECOG_OPERANDS
];
1129 /* Handle commutative operands by swapping the constraints.
1130 We assume the modes are the same. */
1132 for (j
= 0; j
< recog_data
.n_operands
; j
++)
1133 xconstraints
[j
] = constraints
[j
];
1135 xconstraints
[i
] = constraints
[i
+1];
1136 xconstraints
[i
+1] = constraints
[i
];
1137 record_reg_classes (recog_data
.n_alternatives
, recog_data
.n_operands
,
1138 recog_data
.operand
, modes
,
1139 xconstraints
, insn
, op_costs
, reg_pref
);
1142 record_reg_classes (recog_data
.n_alternatives
, recog_data
.n_operands
,
1143 recog_data
.operand
, modes
,
1144 constraints
, insn
, op_costs
, reg_pref
);
1147 /* Subroutine of regclass, processes one insn INSN. Scan it and record each
1148 time it would save code to put a certain register in a certain class.
1149 PASS, when nonzero, inhibits some optimizations which need only be done
1151 Return the last insn processed, so that the scan can be continued from
1155 scan_one_insn (rtx insn
, int pass ATTRIBUTE_UNUSED
)
1157 enum rtx_code pat_code
;
1160 struct costs op_costs
[MAX_RECOG_OPERANDS
];
1165 pat_code
= GET_CODE (PATTERN (insn
));
1167 || pat_code
== CLOBBER
1168 || pat_code
== ASM_INPUT
1169 || pat_code
== ADDR_VEC
1170 || pat_code
== ADDR_DIFF_VEC
)
1173 set
= single_set (insn
);
1174 extract_insn (insn
);
1176 /* If this insn loads a parameter from its stack slot, then
1177 it represents a savings, rather than a cost, if the
1178 parameter is stored in memory. Record this fact. */
1180 if (set
!= 0 && REG_P (SET_DEST (set
))
1181 && MEM_P (SET_SRC (set
))
1182 && (note
= find_reg_note (insn
, REG_EQUIV
,
1184 && MEM_P (XEXP (note
, 0)))
1186 costs
[REGNO (SET_DEST (set
))].mem_cost
1187 -= (MEMORY_MOVE_COST (GET_MODE (SET_DEST (set
)),
1190 record_address_regs (GET_MODE (SET_SRC (set
)), XEXP (SET_SRC (set
), 0),
1191 0, MEM
, SCRATCH
, frequency
* 2);
1195 record_operand_costs (insn
, op_costs
, reg_pref
);
1197 /* Now add the cost for each operand to the total costs for
1200 for (i
= 0; i
< recog_data
.n_operands
; i
++)
1201 if (REG_P (recog_data
.operand
[i
])
1202 && REGNO (recog_data
.operand
[i
]) >= FIRST_PSEUDO_REGISTER
)
1204 int regno
= REGNO (recog_data
.operand
[i
]);
1205 struct costs
*p
= &costs
[regno
], *q
= &op_costs
[i
];
1207 p
->mem_cost
+= q
->mem_cost
* frequency
;
1208 for (j
= 0; j
< N_REG_CLASSES
; j
++)
1209 p
->cost
[j
] += q
->cost
[j
] * frequency
;
1215 /* Initialize information about which register classes can be used for
1216 pseudos that are auto-incremented or auto-decremented. */
1219 init_reg_autoinc (void)
1221 #ifdef FORBIDDEN_INC_DEC_CLASSES
1224 memset (forbidden_inc_dec_class
, 0, sizeof forbidden_inc_dec_class
);
1225 for (i
= 0; i
< N_REG_CLASSES
; i
++)
1227 rtx r
= gen_rtx_raw_REG (VOIDmode
, 0);
1228 enum machine_mode m
;
1231 for (j
= 0; j
< FIRST_PSEUDO_REGISTER
; j
++)
1232 if (TEST_HARD_REG_BIT (reg_class_contents
[i
], j
))
1236 for (m
= VOIDmode
; (int) m
< (int) MAX_MACHINE_MODE
;
1237 m
= (enum machine_mode
) ((int) m
+ 1))
1238 if (HARD_REGNO_MODE_OK (j
, m
))
1240 /* ??? There are two assumptions here; that the base class does not
1241 depend on the exact outer code (POST_INC vs. PRE_INC etc.), and
1242 that it does not depend on the machine mode of the memory
1244 enum reg_class base_class
1245 = base_reg_class (VOIDmode
, POST_INC
, SCRATCH
);
1249 /* If a register is not directly suitable for an
1250 auto-increment or decrement addressing mode and
1251 requires secondary reloads, disallow its class from
1252 being used in such addresses. */
1254 if ((secondary_reload_class (1, base_class
, m
, r
)
1255 || secondary_reload_class (1, base_class
, m
, r
))
1256 && ! auto_inc_dec_reg_p (r
, m
))
1257 forbidden_inc_dec_class
[i
] = 1;
1261 #endif /* FORBIDDEN_INC_DEC_CLASSES */
1264 /* This is a pass of the compiler that scans all instructions
1265 and calculates the preferred class for each pseudo-register.
1266 This information can be accessed later by calling `reg_preferred_class'.
1267 This pass comes just before local register allocation. */
1270 regclass (rtx f
, int nregs
)
1275 max_regno
= max_reg_num ();
1279 reg_renumber
= xmalloc (max_regno
* sizeof (short));
1280 reg_pref
= XCNEWVEC (struct reg_pref
, max_regno
);
1281 memset (reg_renumber
, -1, max_regno
* sizeof (short));
1283 costs
= XNEWVEC (struct costs
, nregs
);
1285 #ifdef FORBIDDEN_INC_DEC_CLASSES
1287 in_inc_dec
= XNEWVEC (char, nregs
);
1289 #endif /* FORBIDDEN_INC_DEC_CLASSES */
1291 /* Normally we scan the insns once and determine the best class to use for
1292 each register. However, if -fexpensive_optimizations are on, we do so
1293 twice, the second time using the tentative best classes to guide the
1296 for (pass
= 0; pass
<= flag_expensive_optimizations
; pass
++)
1301 fprintf (dump_file
, "\n\nPass %i\n\n",pass
);
1302 /* Zero out our accumulation of the cost of each class for each reg. */
1304 memset (costs
, 0, nregs
* sizeof (struct costs
));
1306 #ifdef FORBIDDEN_INC_DEC_CLASSES
1307 memset (in_inc_dec
, 0, nregs
);
1310 /* Scan the instructions and record each time it would
1311 save code to put a certain register in a certain class. */
1315 frequency
= REG_FREQ_MAX
;
1316 for (insn
= f
; insn
; insn
= NEXT_INSN (insn
))
1317 insn
= scan_one_insn (insn
, pass
);
1322 /* Show that an insn inside a loop is likely to be executed three
1323 times more than insns outside a loop. This is much more
1324 aggressive than the assumptions made elsewhere and is being
1325 tried as an experiment. */
1326 frequency
= REG_FREQ_FROM_BB (bb
);
1327 for (insn
= BB_HEAD (bb
); ; insn
= NEXT_INSN (insn
))
1329 insn
= scan_one_insn (insn
, pass
);
1330 if (insn
== BB_END (bb
))
1335 /* Now for each register look at how desirable each class is
1336 and find which class is preferred. Store that in
1337 `prefclass'. Record in `altclass' the largest register
1338 class any of whose registers is better than memory. */
1342 dump_regclass (dump_file
);
1343 fprintf (dump_file
,"\n");
1345 for (i
= FIRST_PSEUDO_REGISTER
; i
< nregs
; i
++)
1347 int best_cost
= (1 << (HOST_BITS_PER_INT
- 2)) - 1;
1348 enum reg_class best
= ALL_REGS
, alt
= NO_REGS
;
1349 /* This is an enum reg_class, but we call it an int
1350 to save lots of casts. */
1352 struct costs
*p
= &costs
[i
];
1354 if (regno_reg_rtx
[i
] == NULL
)
1357 /* In non-optimizing compilation REG_N_REFS is not initialized
1359 if (optimize
&& !REG_N_REFS (i
) && !REG_N_SETS (i
))
1362 for (class = (int) ALL_REGS
- 1; class > 0; class--)
1364 /* Ignore classes that are too small for this operand or
1365 invalid for an operand that was auto-incremented. */
1366 if (!contains_reg_of_mode
[class][PSEUDO_REGNO_MODE (i
)]
1367 #ifdef FORBIDDEN_INC_DEC_CLASSES
1368 || (in_inc_dec
[i
] && forbidden_inc_dec_class
[class])
1370 #ifdef CANNOT_CHANGE_MODE_CLASS
1371 || invalid_mode_change_p (i
, (enum reg_class
) class,
1372 PSEUDO_REGNO_MODE (i
))
1376 else if (p
->cost
[class] < best_cost
)
1378 best_cost
= p
->cost
[class];
1379 best
= (enum reg_class
) class;
1381 else if (p
->cost
[class] == best_cost
)
1382 best
= reg_class_subunion
[(int) best
][class];
1385 /* If no register class is better than memory, use memory. */
1386 if (p
->mem_cost
< best_cost
)
1389 /* Record the alternate register class; i.e., a class for which
1390 every register in it is better than using memory. If adding a
1391 class would make a smaller class (i.e., no union of just those
1392 classes exists), skip that class. The major unions of classes
1393 should be provided as a register class. Don't do this if we
1394 will be doing it again later. */
1396 if ((pass
== 1 || dump_file
) || ! flag_expensive_optimizations
)
1397 for (class = 0; class < N_REG_CLASSES
; class++)
1398 if (p
->cost
[class] < p
->mem_cost
1399 && (reg_class_size
[(int) reg_class_subunion
[(int) alt
][class]]
1400 > reg_class_size
[(int) alt
])
1401 #ifdef FORBIDDEN_INC_DEC_CLASSES
1402 && ! (in_inc_dec
[i
] && forbidden_inc_dec_class
[class])
1404 #ifdef CANNOT_CHANGE_MODE_CLASS
1405 && ! invalid_mode_change_p (i
, (enum reg_class
) class,
1406 PSEUDO_REGNO_MODE (i
))
1409 alt
= reg_class_subunion
[(int) alt
][class];
1411 /* If we don't add any classes, nothing to try. */
1416 && (reg_pref
[i
].prefclass
!= (int) best
1417 || reg_pref
[i
].altclass
!= (int) alt
))
1419 fprintf (dump_file
, " Register %i", i
);
1420 if (alt
== ALL_REGS
|| best
== ALL_REGS
)
1421 fprintf (dump_file
, " pref %s\n", reg_class_names
[(int) best
]);
1422 else if (alt
== NO_REGS
)
1423 fprintf (dump_file
, " pref %s or none\n", reg_class_names
[(int) best
]);
1425 fprintf (dump_file
, " pref %s, else %s\n",
1426 reg_class_names
[(int) best
],
1427 reg_class_names
[(int) alt
]);
1430 /* We cast to (int) because (char) hits bugs in some compilers. */
1431 reg_pref
[i
].prefclass
= (int) best
;
1432 reg_pref
[i
].altclass
= (int) alt
;
1436 #ifdef FORBIDDEN_INC_DEC_CLASSES
1442 /* Record the cost of using memory or registers of various classes for
1443 the operands in INSN.
1445 N_ALTS is the number of alternatives.
1447 N_OPS is the number of operands.
1449 OPS is an array of the operands.
1451 MODES are the modes of the operands, in case any are VOIDmode.
1453 CONSTRAINTS are the constraints to use for the operands. This array
1454 is modified by this procedure.
1456 This procedure works alternative by alternative. For each alternative
1457 we assume that we will be able to allocate all pseudos to their ideal
1458 register class and calculate the cost of using that alternative. Then
1459 we compute for each operand that is a pseudo-register, the cost of
1460 having the pseudo allocated to each register class and using it in that
1461 alternative. To this cost is added the cost of the alternative.
1463 The cost of each class for this insn is its lowest cost among all the
1467 record_reg_classes (int n_alts
, int n_ops
, rtx
*ops
,
1468 enum machine_mode
*modes
, const char **constraints
,
1469 rtx insn
, struct costs
*op_costs
,
1470 struct reg_pref
*reg_pref
)
1476 /* Process each alternative, each time minimizing an operand's cost with
1477 the cost for each operand in that alternative. */
1479 for (alt
= 0; alt
< n_alts
; alt
++)
1481 struct costs this_op_costs
[MAX_RECOG_OPERANDS
];
1484 enum reg_class classes
[MAX_RECOG_OPERANDS
];
1485 int allows_mem
[MAX_RECOG_OPERANDS
];
1488 for (i
= 0; i
< n_ops
; i
++)
1490 const char *p
= constraints
[i
];
1492 enum machine_mode mode
= modes
[i
];
1493 int allows_addr
= 0;
1497 /* Initially show we know nothing about the register class. */
1498 classes
[i
] = NO_REGS
;
1501 /* If this operand has no constraints at all, we can conclude
1502 nothing about it since anything is valid. */
1506 if (REG_P (op
) && REGNO (op
) >= FIRST_PSEUDO_REGISTER
)
1507 memset (&this_op_costs
[i
], 0, sizeof this_op_costs
[i
]);
1512 /* If this alternative is only relevant when this operand
1513 matches a previous operand, we do different things depending
1514 on whether this operand is a pseudo-reg or not. We must process
1515 any modifiers for the operand before we can make this test. */
1517 while (*p
== '%' || *p
== '=' || *p
== '+' || *p
== '&')
1520 if (p
[0] >= '0' && p
[0] <= '0' + i
&& (p
[1] == ',' || p
[1] == 0))
1522 /* Copy class and whether memory is allowed from the matching
1523 alternative. Then perform any needed cost computations
1524 and/or adjustments. */
1526 classes
[i
] = classes
[j
];
1527 allows_mem
[i
] = allows_mem
[j
];
1529 if (!REG_P (op
) || REGNO (op
) < FIRST_PSEUDO_REGISTER
)
1531 /* If this matches the other operand, we have no added
1533 if (rtx_equal_p (ops
[j
], op
))
1536 /* If we can put the other operand into a register, add to
1537 the cost of this alternative the cost to copy this
1538 operand to the register used for the other operand. */
1540 else if (classes
[j
] != NO_REGS
)
1542 alt_cost
+= copy_cost (op
, mode
, classes
[j
], 1, NULL
);
1546 else if (!REG_P (ops
[j
])
1547 || REGNO (ops
[j
]) < FIRST_PSEUDO_REGISTER
)
1549 /* This op is a pseudo but the one it matches is not. */
1551 /* If we can't put the other operand into a register, this
1552 alternative can't be used. */
1554 if (classes
[j
] == NO_REGS
)
1557 /* Otherwise, add to the cost of this alternative the cost
1558 to copy the other operand to the register used for this
1562 alt_cost
+= copy_cost (ops
[j
], mode
, classes
[j
], 1, NULL
);
1566 /* The costs of this operand are not the same as the other
1567 operand since move costs are not symmetric. Moreover,
1568 if we cannot tie them, this alternative needs to do a
1569 copy, which is one instruction. */
1571 struct costs
*pp
= &this_op_costs
[i
];
1572 move_table
*intable
= NULL
;
1573 move_table
*outtable
= NULL
;
1574 int op_class
= (int) classes
[i
];
1576 if (!move_cost
[mode
])
1577 init_move_cost (mode
);
1578 intable
= may_move_in_cost
[mode
];
1579 outtable
= may_move_out_cost
[mode
];
1581 /* The loop is performance critical, so unswitch it manually.
1583 switch (recog_data
.operand_type
[i
])
1586 for (class = 0; class < N_REG_CLASSES
; class++)
1587 pp
->cost
[class] = (intable
[class][op_class
]
1588 + outtable
[op_class
][class]);
1591 for (class = 0; class < N_REG_CLASSES
; class++)
1592 pp
->cost
[class] = intable
[class][op_class
];
1595 for (class = 0; class < N_REG_CLASSES
; class++)
1596 pp
->cost
[class] = outtable
[op_class
][class];
1600 /* If the alternative actually allows memory, make things
1601 a bit cheaper since we won't need an extra insn to
1605 = ((recog_data
.operand_type
[i
] != OP_IN
1606 ? MEMORY_MOVE_COST (mode
, classes
[i
], 0)
1608 + (recog_data
.operand_type
[i
] != OP_OUT
1609 ? MEMORY_MOVE_COST (mode
, classes
[i
], 1)
1610 : 0) - allows_mem
[i
]);
1612 /* If we have assigned a class to this register in our
1613 first pass, add a cost to this alternative corresponding
1614 to what we would add if this register were not in the
1615 appropriate class. */
1617 if (reg_pref
&& reg_pref
[REGNO (op
)].prefclass
!= NO_REGS
)
1619 += (may_move_in_cost
[mode
]
1620 [(unsigned char) reg_pref
[REGNO (op
)].prefclass
]
1621 [(int) classes
[i
]]);
1623 if (REGNO (ops
[i
]) != REGNO (ops
[j
])
1624 && ! find_reg_note (insn
, REG_DEAD
, op
))
1627 /* This is in place of ordinary cost computation
1628 for this operand, so skip to the end of the
1629 alternative (should be just one character). */
1630 while (*p
&& *p
++ != ',')
1638 /* Scan all the constraint letters. See if the operand matches
1639 any of the constraints. Collect the valid register classes
1640 and see if this operand accepts memory. */
1649 /* Ignore the next letter for this pass. */
1655 case '!': case '#': case '&':
1656 case '0': case '1': case '2': case '3': case '4':
1657 case '5': case '6': case '7': case '8': case '9':
1662 win
= address_operand (op
, GET_MODE (op
));
1663 /* We know this operand is an address, so we want it to be
1664 allocated to a register that can be the base of an
1665 address, i.e. BASE_REG_CLASS. */
1667 = reg_class_subunion
[(int) classes
[i
]]
1668 [(int) base_reg_class (VOIDmode
, ADDRESS
, SCRATCH
)];
1671 case 'm': case 'o': case 'V':
1672 /* It doesn't seem worth distinguishing between offsettable
1673 and non-offsettable addresses here. */
1681 && (GET_CODE (XEXP (op
, 0)) == PRE_DEC
1682 || GET_CODE (XEXP (op
, 0)) == POST_DEC
))
1688 && (GET_CODE (XEXP (op
, 0)) == PRE_INC
1689 || GET_CODE (XEXP (op
, 0)) == POST_INC
))
1695 if (GET_CODE (op
) == CONST_DOUBLE
1696 || (GET_CODE (op
) == CONST_VECTOR
1697 && (GET_MODE_CLASS (GET_MODE (op
))
1698 == MODE_VECTOR_FLOAT
)))
1704 if (GET_CODE (op
) == CONST_DOUBLE
1705 && CONST_DOUBLE_OK_FOR_CONSTRAINT_P (op
, c
, p
))
1710 if (GET_CODE (op
) == CONST_INT
1711 || (GET_CODE (op
) == CONST_DOUBLE
1712 && GET_MODE (op
) == VOIDmode
))
1716 && (! flag_pic
|| LEGITIMATE_PIC_OPERAND_P (op
)))
1721 if (GET_CODE (op
) == CONST_INT
1722 || (GET_CODE (op
) == CONST_DOUBLE
1723 && GET_MODE (op
) == VOIDmode
))
1735 if (GET_CODE (op
) == CONST_INT
1736 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op
), c
, p
))
1747 && (! flag_pic
|| LEGITIMATE_PIC_OPERAND_P (op
))))
1752 = reg_class_subunion
[(int) classes
[i
]][(int) GENERAL_REGS
];
1756 if (REG_CLASS_FROM_CONSTRAINT (c
, p
) != NO_REGS
)
1758 = reg_class_subunion
[(int) classes
[i
]]
1759 [(int) REG_CLASS_FROM_CONSTRAINT (c
, p
)];
1760 #ifdef EXTRA_CONSTRAINT_STR
1761 else if (EXTRA_CONSTRAINT_STR (op
, c
, p
))
1764 if (EXTRA_MEMORY_CONSTRAINT (c
, p
))
1766 /* Every MEM can be reloaded to fit. */
1771 if (EXTRA_ADDRESS_CONSTRAINT (c
, p
))
1773 /* Every address can be reloaded to fit. */
1775 if (address_operand (op
, GET_MODE (op
)))
1777 /* We know this operand is an address, so we want it to
1778 be allocated to a register that can be the base of an
1779 address, i.e. BASE_REG_CLASS. */
1781 = reg_class_subunion
[(int) classes
[i
]]
1782 [(int) base_reg_class (VOIDmode
, ADDRESS
, SCRATCH
)];
1787 p
+= CONSTRAINT_LEN (c
, p
);
1794 /* How we account for this operand now depends on whether it is a
1795 pseudo register or not. If it is, we first check if any
1796 register classes are valid. If not, we ignore this alternative,
1797 since we want to assume that all pseudos get allocated for
1798 register preferencing. If some register class is valid, compute
1799 the costs of moving the pseudo into that class. */
1801 if (REG_P (op
) && REGNO (op
) >= FIRST_PSEUDO_REGISTER
)
1803 if (classes
[i
] == NO_REGS
)
1805 /* We must always fail if the operand is a REG, but
1806 we did not find a suitable class.
1808 Otherwise we may perform an uninitialized read
1809 from this_op_costs after the `continue' statement
1815 struct costs
*pp
= &this_op_costs
[i
];
1816 move_table
*intable
= NULL
;
1817 move_table
*outtable
= NULL
;
1818 int op_class
= (int) classes
[i
];
1820 if (!move_cost
[mode
])
1821 init_move_cost (mode
);
1822 intable
= may_move_in_cost
[mode
];
1823 outtable
= may_move_out_cost
[mode
];
1825 /* The loop is performance critical, so unswitch it manually.
1827 switch (recog_data
.operand_type
[i
])
1830 for (class = 0; class < N_REG_CLASSES
; class++)
1831 pp
->cost
[class] = (intable
[class][op_class
]
1832 + outtable
[op_class
][class]);
1835 for (class = 0; class < N_REG_CLASSES
; class++)
1836 pp
->cost
[class] = intable
[class][op_class
];
1839 for (class = 0; class < N_REG_CLASSES
; class++)
1840 pp
->cost
[class] = outtable
[op_class
][class];
1844 /* If the alternative actually allows memory, make things
1845 a bit cheaper since we won't need an extra insn to
1849 = ((recog_data
.operand_type
[i
] != OP_IN
1850 ? MEMORY_MOVE_COST (mode
, classes
[i
], 0)
1852 + (recog_data
.operand_type
[i
] != OP_OUT
1853 ? MEMORY_MOVE_COST (mode
, classes
[i
], 1)
1854 : 0) - allows_mem
[i
]);
1856 /* If we have assigned a class to this register in our
1857 first pass, add a cost to this alternative corresponding
1858 to what we would add if this register were not in the
1859 appropriate class. */
1861 if (reg_pref
&& reg_pref
[REGNO (op
)].prefclass
!= NO_REGS
)
1863 += (may_move_in_cost
[mode
]
1864 [(unsigned char) reg_pref
[REGNO (op
)].prefclass
]
1865 [(int) classes
[i
]]);
1869 /* Otherwise, if this alternative wins, either because we
1870 have already determined that or if we have a hard register of
1871 the proper class, there is no cost for this alternative. */
1875 && reg_fits_class_p (op
, classes
[i
], 0, GET_MODE (op
))))
1878 /* If registers are valid, the cost of this alternative includes
1879 copying the object to and/or from a register. */
1881 else if (classes
[i
] != NO_REGS
)
1883 if (recog_data
.operand_type
[i
] != OP_OUT
)
1884 alt_cost
+= copy_cost (op
, mode
, classes
[i
], 1, NULL
);
1886 if (recog_data
.operand_type
[i
] != OP_IN
)
1887 alt_cost
+= copy_cost (op
, mode
, classes
[i
], 0, NULL
);
1890 /* The only other way this alternative can be used is if this is a
1891 constant that could be placed into memory. */
1893 else if (CONSTANT_P (op
) && (allows_addr
|| allows_mem
[i
]))
1894 alt_cost
+= MEMORY_MOVE_COST (mode
, classes
[i
], 1);
1902 /* Finally, update the costs with the information we've calculated
1903 about this alternative. */
1905 for (i
= 0; i
< n_ops
; i
++)
1907 && REGNO (ops
[i
]) >= FIRST_PSEUDO_REGISTER
)
1909 struct costs
*pp
= &op_costs
[i
], *qq
= &this_op_costs
[i
];
1910 int scale
= 1 + (recog_data
.operand_type
[i
] == OP_INOUT
);
1912 pp
->mem_cost
= MIN (pp
->mem_cost
,
1913 (qq
->mem_cost
+ alt_cost
) * scale
);
1915 for (class = 0; class < N_REG_CLASSES
; class++)
1916 pp
->cost
[class] = MIN (pp
->cost
[class],
1917 (qq
->cost
[class] + alt_cost
) * scale
);
1921 /* If this insn is a single set copying operand 1 to operand 0
1922 and one operand is a pseudo with the other a hard reg or a pseudo
1923 that prefers a register that is in its own register class then
1924 we may want to adjust the cost of that register class to -1.
1926 Avoid the adjustment if the source does not die to avoid stressing of
1927 register allocator by preferrencing two colliding registers into single
1930 Also avoid the adjustment if a copy between registers of the class
1931 is expensive (ten times the cost of a default copy is considered
1932 arbitrarily expensive). This avoids losing when the preferred class
1933 is very expensive as the source of a copy instruction. */
1935 if ((set
= single_set (insn
)) != 0
1936 && ops
[0] == SET_DEST (set
) && ops
[1] == SET_SRC (set
)
1937 && REG_P (ops
[0]) && REG_P (ops
[1])
1938 && find_regno_note (insn
, REG_DEAD
, REGNO (ops
[1])))
1939 for (i
= 0; i
<= 1; i
++)
1940 if (REGNO (ops
[i
]) >= FIRST_PSEUDO_REGISTER
)
1942 unsigned int regno
= REGNO (ops
[!i
]);
1943 enum machine_mode mode
= GET_MODE (ops
[!i
]);
1946 if (regno
>= FIRST_PSEUDO_REGISTER
&& reg_pref
!= 0
1947 && reg_pref
[regno
].prefclass
!= NO_REGS
)
1949 enum reg_class pref
= reg_pref
[regno
].prefclass
;
1951 if ((reg_class_size
[(unsigned char) pref
]
1952 == (unsigned) CLASS_MAX_NREGS (pref
, mode
))
1953 && REGISTER_MOVE_COST (mode
, pref
, pref
) < 10 * 2)
1954 op_costs
[i
].cost
[(unsigned char) pref
] = -1;
1956 else if (regno
< FIRST_PSEUDO_REGISTER
)
1957 for (class = 0; class < N_REG_CLASSES
; class++)
1958 if (TEST_HARD_REG_BIT (reg_class_contents
[class], regno
)
1959 && reg_class_size
[class] == (unsigned) CLASS_MAX_NREGS (class, mode
))
1961 if (reg_class_size
[class] == 1)
1962 op_costs
[i
].cost
[class] = -1;
1963 else if (in_hard_reg_set_p (reg_class_contents
[class],
1965 op_costs
[i
].cost
[class] = -1;
1970 /* Compute the cost of loading X into (if TO_P is nonzero) or from (if
1971 TO_P is zero) a register of class CLASS in mode MODE.
1973 X must not be a pseudo. */
1976 copy_cost (rtx x
, enum machine_mode mode
, enum reg_class
class, int to_p
,
1977 secondary_reload_info
*prev_sri
)
1979 enum reg_class secondary_class
= NO_REGS
;
1980 secondary_reload_info sri
;
1982 /* If X is a SCRATCH, there is actually nothing to move since we are
1983 assuming optimal allocation. */
1985 if (GET_CODE (x
) == SCRATCH
)
1988 /* Get the class we will actually use for a reload. */
1989 class = PREFERRED_RELOAD_CLASS (x
, class);
1991 /* If we need a secondary reload for an intermediate, the
1992 cost is that to load the input into the intermediate register, then
1995 sri
.prev_sri
= prev_sri
;
1997 secondary_class
= targetm
.secondary_reload (to_p
, x
, class, mode
, &sri
);
1999 if (!move_cost
[mode
])
2000 init_move_cost (mode
);
2002 if (secondary_class
!= NO_REGS
)
2003 return (move_cost
[mode
][(int) secondary_class
][(int) class]
2005 + copy_cost (x
, mode
, secondary_class
, to_p
, &sri
));
2007 /* For memory, use the memory move cost, for (hard) registers, use the
2008 cost to move between the register classes, and use 2 for everything
2009 else (constants). */
2011 if (MEM_P (x
) || class == NO_REGS
)
2012 return sri
.extra_cost
+ MEMORY_MOVE_COST (mode
, class, to_p
);
2015 return (sri
.extra_cost
2016 + move_cost
[mode
][(int) REGNO_REG_CLASS (REGNO (x
))][(int) class]);
2019 /* If this is a constant, we may eventually want to call rtx_cost here. */
2020 return sri
.extra_cost
+ COSTS_N_INSNS (1);
2023 /* Record the pseudo registers we must reload into hard registers
2024 in a subexpression of a memory address, X.
2026 If CONTEXT is 0, we are looking at the base part of an address, otherwise we
2027 are looking at the index part.
2029 MODE is the mode of the memory reference; OUTER_CODE and INDEX_CODE
2030 give the context that the rtx appears in. These three arguments are
2031 passed down to base_reg_class.
2033 SCALE is twice the amount to multiply the cost by (it is twice so we
2034 can represent half-cost adjustments). */
2037 record_address_regs (enum machine_mode mode
, rtx x
, int context
,
2038 enum rtx_code outer_code
, enum rtx_code index_code
,
2041 enum rtx_code code
= GET_CODE (x
);
2042 enum reg_class
class;
2045 class = INDEX_REG_CLASS
;
2047 class = base_reg_class (mode
, outer_code
, index_code
);
2060 /* When we have an address that is a sum,
2061 we must determine whether registers are "base" or "index" regs.
2062 If there is a sum of two registers, we must choose one to be
2063 the "base". Luckily, we can use the REG_POINTER to make a good
2064 choice most of the time. We only need to do this on machines
2065 that can have two registers in an address and where the base
2066 and index register classes are different.
2068 ??? This code used to set REGNO_POINTER_FLAG in some cases, but
2069 that seems bogus since it should only be set when we are sure
2070 the register is being used as a pointer. */
2073 rtx arg0
= XEXP (x
, 0);
2074 rtx arg1
= XEXP (x
, 1);
2075 enum rtx_code code0
= GET_CODE (arg0
);
2076 enum rtx_code code1
= GET_CODE (arg1
);
2078 /* Look inside subregs. */
2079 if (code0
== SUBREG
)
2080 arg0
= SUBREG_REG (arg0
), code0
= GET_CODE (arg0
);
2081 if (code1
== SUBREG
)
2082 arg1
= SUBREG_REG (arg1
), code1
= GET_CODE (arg1
);
2084 /* If this machine only allows one register per address, it must
2085 be in the first operand. */
2087 if (MAX_REGS_PER_ADDRESS
== 1)
2088 record_address_regs (mode
, arg0
, 0, PLUS
, code1
, scale
);
2090 /* If index and base registers are the same on this machine, just
2091 record registers in any non-constant operands. We assume here,
2092 as well as in the tests below, that all addresses are in
2095 else if (INDEX_REG_CLASS
== base_reg_class (VOIDmode
, PLUS
, SCRATCH
))
2097 record_address_regs (mode
, arg0
, context
, PLUS
, code1
, scale
);
2098 if (! CONSTANT_P (arg1
))
2099 record_address_regs (mode
, arg1
, context
, PLUS
, code0
, scale
);
2102 /* If the second operand is a constant integer, it doesn't change
2103 what class the first operand must be. */
2105 else if (code1
== CONST_INT
|| code1
== CONST_DOUBLE
)
2106 record_address_regs (mode
, arg0
, context
, PLUS
, code1
, scale
);
2108 /* If the second operand is a symbolic constant, the first operand
2109 must be an index register. */
2111 else if (code1
== SYMBOL_REF
|| code1
== CONST
|| code1
== LABEL_REF
)
2112 record_address_regs (mode
, arg0
, 1, PLUS
, code1
, scale
);
2114 /* If both operands are registers but one is already a hard register
2115 of index or reg-base class, give the other the class that the
2116 hard register is not. */
2118 else if (code0
== REG
&& code1
== REG
2119 && REGNO (arg0
) < FIRST_PSEUDO_REGISTER
2120 && (ok_for_base_p_nonstrict (arg0
, mode
, PLUS
, REG
)
2121 || ok_for_index_p_nonstrict (arg0
)))
2122 record_address_regs (mode
, arg1
,
2123 ok_for_base_p_nonstrict (arg0
, mode
, PLUS
, REG
)
2126 else if (code0
== REG
&& code1
== REG
2127 && REGNO (arg1
) < FIRST_PSEUDO_REGISTER
2128 && (ok_for_base_p_nonstrict (arg1
, mode
, PLUS
, REG
)
2129 || ok_for_index_p_nonstrict (arg1
)))
2130 record_address_regs (mode
, arg0
,
2131 ok_for_base_p_nonstrict (arg1
, mode
, PLUS
, REG
)
2135 /* If one operand is known to be a pointer, it must be the base
2136 with the other operand the index. Likewise if the other operand
2139 else if ((code0
== REG
&& REG_POINTER (arg0
))
2142 record_address_regs (mode
, arg0
, 0, PLUS
, code1
, scale
);
2143 record_address_regs (mode
, arg1
, 1, PLUS
, code0
, scale
);
2145 else if ((code1
== REG
&& REG_POINTER (arg1
))
2148 record_address_regs (mode
, arg0
, 1, PLUS
, code1
, scale
);
2149 record_address_regs (mode
, arg1
, 0, PLUS
, code0
, scale
);
2152 /* Otherwise, count equal chances that each might be a base
2153 or index register. This case should be rare. */
2157 record_address_regs (mode
, arg0
, 0, PLUS
, code1
, scale
/ 2);
2158 record_address_regs (mode
, arg0
, 1, PLUS
, code1
, scale
/ 2);
2159 record_address_regs (mode
, arg1
, 0, PLUS
, code0
, scale
/ 2);
2160 record_address_regs (mode
, arg1
, 1, PLUS
, code0
, scale
/ 2);
2165 /* Double the importance of a pseudo register that is incremented
2166 or decremented, since it would take two extra insns
2167 if it ends up in the wrong place. */
2170 record_address_regs (mode
, XEXP (x
, 0), 0, code
,
2171 GET_CODE (XEXP (XEXP (x
, 1), 1)), 2 * scale
);
2172 if (REG_P (XEXP (XEXP (x
, 1), 1)))
2173 record_address_regs (mode
, XEXP (XEXP (x
, 1), 1), 1, code
, REG
,
2181 /* Double the importance of a pseudo register that is incremented
2182 or decremented, since it would take two extra insns
2183 if it ends up in the wrong place. If the operand is a pseudo,
2184 show it is being used in an INC_DEC context. */
2186 #ifdef FORBIDDEN_INC_DEC_CLASSES
2187 if (REG_P (XEXP (x
, 0))
2188 && REGNO (XEXP (x
, 0)) >= FIRST_PSEUDO_REGISTER
)
2189 in_inc_dec
[REGNO (XEXP (x
, 0))] = 1;
2192 record_address_regs (mode
, XEXP (x
, 0), 0, code
, SCRATCH
, 2 * scale
);
2197 struct costs
*pp
= &costs
[REGNO (x
)];
2200 pp
->mem_cost
+= (MEMORY_MOVE_COST (Pmode
, class, 1) * scale
) / 2;
2202 if (!move_cost
[Pmode
])
2203 init_move_cost (Pmode
);
2204 for (i
= 0; i
< N_REG_CLASSES
; i
++)
2205 pp
->cost
[i
] += (may_move_in_cost
[Pmode
][i
][(int) class] * scale
) / 2;
2211 const char *fmt
= GET_RTX_FORMAT (code
);
2213 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
2215 record_address_regs (mode
, XEXP (x
, i
), context
, code
, SCRATCH
,
2221 #ifdef FORBIDDEN_INC_DEC_CLASSES
2223 /* Return 1 if REG is valid as an auto-increment memory reference
2224 to an object of MODE. */
2227 auto_inc_dec_reg_p (rtx reg
, enum machine_mode mode
)
2229 if (HAVE_POST_INCREMENT
2230 && memory_address_p (mode
, gen_rtx_POST_INC (Pmode
, reg
)))
2233 if (HAVE_POST_DECREMENT
2234 && memory_address_p (mode
, gen_rtx_POST_DEC (Pmode
, reg
)))
2237 if (HAVE_PRE_INCREMENT
2238 && memory_address_p (mode
, gen_rtx_PRE_INC (Pmode
, reg
)))
2241 if (HAVE_PRE_DECREMENT
2242 && memory_address_p (mode
, gen_rtx_PRE_DEC (Pmode
, reg
)))
2249 /* Free up the space allocated by allocate_reg_info. */
2251 free_reg_info (void)
2261 free (reg_renumber
);
2262 reg_renumber
= NULL
;
2267 /* This is the `regscan' pass of the compiler, run just before cse and
2268 again just before loop. It finds the first and last use of each
2272 reg_scan (rtx f
, unsigned int nregs ATTRIBUTE_UNUSED
)
2276 timevar_push (TV_REG_SCAN
);
2278 for (insn
= f
; insn
; insn
= NEXT_INSN (insn
))
2281 reg_scan_mark_refs (PATTERN (insn
), insn
);
2282 if (REG_NOTES (insn
))
2283 reg_scan_mark_refs (REG_NOTES (insn
), insn
);
2286 timevar_pop (TV_REG_SCAN
);
2290 /* X is the expression to scan. INSN is the insn it appears in.
2291 NOTE_FLAG is nonzero if X is from INSN's notes rather than its body.
2292 We should only record information for REGs with numbers
2293 greater than or equal to MIN_REGNO. */
2295 extern struct tree_opt_pass
*current_pass
;
2298 reg_scan_mark_refs (rtx x
, rtx insn
)
2306 code
= GET_CODE (x
);
2325 reg_scan_mark_refs (XEXP (x
, 0), insn
);
2327 reg_scan_mark_refs (XEXP (x
, 1), insn
);
2332 reg_scan_mark_refs (XEXP (x
, 1), insn
);
2336 if (MEM_P (XEXP (x
, 0)))
2337 reg_scan_mark_refs (XEXP (XEXP (x
, 0), 0), insn
);
2341 /* Count a set of the destination if it is a register. */
2342 for (dest
= SET_DEST (x
);
2343 GET_CODE (dest
) == SUBREG
|| GET_CODE (dest
) == STRICT_LOW_PART
2344 || GET_CODE (dest
) == ZERO_EXTEND
;
2345 dest
= XEXP (dest
, 0))
2348 /* If this is setting a pseudo from another pseudo or the sum of a
2349 pseudo and a constant integer and the other pseudo is known to be
2350 a pointer, set the destination to be a pointer as well.
2352 Likewise if it is setting the destination from an address or from a
2353 value equivalent to an address or to the sum of an address and
2356 But don't do any of this if the pseudo corresponds to a user
2357 variable since it should have already been set as a pointer based
2360 if (REG_P (SET_DEST (x
))
2361 && REGNO (SET_DEST (x
)) >= FIRST_PSEUDO_REGISTER
2362 /* If the destination pseudo is set more than once, then other
2363 sets might not be to a pointer value (consider access to a
2364 union in two threads of control in the presence of global
2365 optimizations). So only set REG_POINTER on the destination
2366 pseudo if this is the only set of that pseudo. */
2367 && DF_REG_DEF_COUNT (REGNO (SET_DEST (x
))) == 1
2368 && ! REG_USERVAR_P (SET_DEST (x
))
2369 && ! REG_POINTER (SET_DEST (x
))
2370 && ((REG_P (SET_SRC (x
))
2371 && REG_POINTER (SET_SRC (x
)))
2372 || ((GET_CODE (SET_SRC (x
)) == PLUS
2373 || GET_CODE (SET_SRC (x
)) == LO_SUM
)
2374 && GET_CODE (XEXP (SET_SRC (x
), 1)) == CONST_INT
2375 && REG_P (XEXP (SET_SRC (x
), 0))
2376 && REG_POINTER (XEXP (SET_SRC (x
), 0)))
2377 || GET_CODE (SET_SRC (x
)) == CONST
2378 || GET_CODE (SET_SRC (x
)) == SYMBOL_REF
2379 || GET_CODE (SET_SRC (x
)) == LABEL_REF
2380 || (GET_CODE (SET_SRC (x
)) == HIGH
2381 && (GET_CODE (XEXP (SET_SRC (x
), 0)) == CONST
2382 || GET_CODE (XEXP (SET_SRC (x
), 0)) == SYMBOL_REF
2383 || GET_CODE (XEXP (SET_SRC (x
), 0)) == LABEL_REF
))
2384 || ((GET_CODE (SET_SRC (x
)) == PLUS
2385 || GET_CODE (SET_SRC (x
)) == LO_SUM
)
2386 && (GET_CODE (XEXP (SET_SRC (x
), 1)) == CONST
2387 || GET_CODE (XEXP (SET_SRC (x
), 1)) == SYMBOL_REF
2388 || GET_CODE (XEXP (SET_SRC (x
), 1)) == LABEL_REF
))
2389 || ((note
= find_reg_note (insn
, REG_EQUAL
, 0)) != 0
2390 && (GET_CODE (XEXP (note
, 0)) == CONST
2391 || GET_CODE (XEXP (note
, 0)) == SYMBOL_REF
2392 || GET_CODE (XEXP (note
, 0)) == LABEL_REF
))))
2393 REG_POINTER (SET_DEST (x
)) = 1;
2395 /* If this is setting a register from a register or from a simple
2396 conversion of a register, propagate REG_EXPR. */
2397 if (REG_P (dest
) && !REG_ATTRS (dest
))
2399 rtx src
= SET_SRC (x
);
2401 while (GET_CODE (src
) == SIGN_EXTEND
2402 || GET_CODE (src
) == ZERO_EXTEND
2403 || GET_CODE (src
) == TRUNCATE
2404 || (GET_CODE (src
) == SUBREG
&& subreg_lowpart_p (src
)))
2405 src
= XEXP (src
, 0);
2408 REG_ATTRS (dest
) = REG_ATTRS (src
);
2410 set_reg_attrs_from_mem (dest
, src
);
2413 /* ... fall through ... */
2417 const char *fmt
= GET_RTX_FORMAT (code
);
2419 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
2422 reg_scan_mark_refs (XEXP (x
, i
), insn
);
2423 else if (fmt
[i
] == 'E' && XVEC (x
, i
) != 0)
2426 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
2427 reg_scan_mark_refs (XVECEXP (x
, i
, j
), insn
);
2434 /* Return nonzero if C1 is a subset of C2, i.e., if every register in C1
2438 reg_class_subset_p (enum reg_class c1
, enum reg_class c2
)
2442 || hard_reg_set_subset_p (reg_class_contents
[(int) c1
],
2443 reg_class_contents
[(int) c2
]));
2446 /* Return nonzero if there is a register that is in both C1 and C2. */
2449 reg_classes_intersect_p (enum reg_class c1
, enum reg_class c2
)
2454 || hard_reg_set_intersect_p (reg_class_contents
[(int) c1
],
2455 reg_class_contents
[(int) c2
]));
2458 #ifdef CANNOT_CHANGE_MODE_CLASS
2460 struct subregs_of_mode_node
2463 unsigned char modes
[MAX_MACHINE_MODE
];
2466 static htab_t subregs_of_mode
;
2469 som_hash (const void *x
)
2471 const struct subregs_of_mode_node
*a
= x
;
2476 som_eq (const void *x
, const void *y
)
2478 const struct subregs_of_mode_node
*a
= x
;
2479 const struct subregs_of_mode_node
*b
= y
;
2480 return a
->block
== b
->block
;
2485 record_subregs_of_mode (rtx subreg
)
2487 struct subregs_of_mode_node dummy
, *node
;
2488 enum machine_mode mode
;
2492 if (!REG_P (SUBREG_REG (subreg
)))
2495 regno
= REGNO (SUBREG_REG (subreg
));
2496 mode
= GET_MODE (subreg
);
2498 if (regno
< FIRST_PSEUDO_REGISTER
)
2501 dummy
.block
= regno
& -8;
2502 slot
= htab_find_slot_with_hash (subregs_of_mode
, &dummy
,
2503 dummy
.block
, INSERT
);
2507 node
= XCNEW (struct subregs_of_mode_node
);
2508 node
->block
= regno
& -8;
2512 node
->modes
[mode
] |= 1 << (regno
& 7);
2516 /* Call record_subregs_of_mode for all the subregs in X. */
2519 find_subregs_of_mode (rtx x
)
2521 enum rtx_code code
= GET_CODE (x
);
2522 const char * const fmt
= GET_RTX_FORMAT (code
);
2526 record_subregs_of_mode (x
);
2528 /* Time for some deep diving. */
2529 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
2532 find_subregs_of_mode (XEXP (x
, i
));
2533 else if (fmt
[i
] == 'E')
2536 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
2537 find_subregs_of_mode (XVECEXP (x
, i
, j
));
2543 init_subregs_of_mode (void)
2548 if (subregs_of_mode
)
2549 htab_empty (subregs_of_mode
);
2551 subregs_of_mode
= htab_create (100, som_hash
, som_eq
, free
);
2554 FOR_BB_INSNS (bb
, insn
)
2556 find_subregs_of_mode (PATTERN (insn
));
2562 /* Set bits in *USED which correspond to registers which can't change
2563 their mode from FROM to any mode in which REGNO was encountered. */
2566 cannot_change_mode_set_regs (HARD_REG_SET
*used
, enum machine_mode from
,
2569 struct subregs_of_mode_node dummy
, *node
;
2570 enum machine_mode to
;
2574 gcc_assert (subregs_of_mode
);
2575 dummy
.block
= regno
& -8;
2576 node
= htab_find_with_hash (subregs_of_mode
, &dummy
, dummy
.block
);
2580 mask
= 1 << (regno
& 7);
2581 for (to
= VOIDmode
; to
< NUM_MACHINE_MODES
; to
++)
2582 if (node
->modes
[to
] & mask
)
2583 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
2584 if (!TEST_HARD_REG_BIT (*used
, i
)
2585 && REG_CANNOT_CHANGE_MODE_P (i
, from
, to
))
2586 SET_HARD_REG_BIT (*used
, i
);
2589 /* Return 1 if REGNO has had an invalid mode change in CLASS from FROM
2593 invalid_mode_change_p (unsigned int regno
,
2594 enum reg_class
class ATTRIBUTE_UNUSED
,
2595 enum machine_mode from
)
2597 struct subregs_of_mode_node dummy
, *node
;
2598 enum machine_mode to
;
2601 gcc_assert (subregs_of_mode
);
2602 dummy
.block
= regno
& -8;
2603 node
= htab_find_with_hash (subregs_of_mode
, &dummy
, dummy
.block
);
2607 mask
= 1 << (regno
& 7);
2608 for (to
= VOIDmode
; to
< NUM_MACHINE_MODES
; to
++)
2609 if (node
->modes
[to
] & mask
)
2610 if (CANNOT_CHANGE_MODE_CLASS (from
, to
, class))
2617 finish_subregs_of_mode (void)
2619 htab_delete (subregs_of_mode
);
2620 subregs_of_mode
= 0;
2625 init_subregs_of_mode (void)
2630 finish_subregs_of_mode (void)
2635 #endif /* CANNOT_CHANGE_MODE_CLASS */
2638 gate_subregs_of_mode_init (void)
2640 #ifdef CANNOT_CHANGE_MODE_CLASS
2647 struct tree_opt_pass pass_subregs_of_mode_init
=
2649 "subregs_of_mode_init", /* name */
2650 gate_subregs_of_mode_init
, /* gate */
2651 init_subregs_of_mode
, /* execute */
2654 0, /* static_pass_number */
2656 0, /* properties_required */
2657 0, /* properties_provided */
2658 0, /* properties_destroyed */
2659 0, /* todo_flags_start */
2660 0, /* todo_flags_finish */
2664 struct tree_opt_pass pass_subregs_of_mode_finish
=
2666 "subregs_of_mode_finish", /* name */
2667 gate_subregs_of_mode_init
, /* gate */
2668 finish_subregs_of_mode
, /* execute */
2671 0, /* static_pass_number */
2673 0, /* properties_required */
2674 0, /* properties_provided */
2675 0, /* properties_destroyed */
2676 0, /* todo_flags_start */
2677 0, /* todo_flags_finish */
2683 #include "gt-regclass.h"