1 /* Compute register class preferences for pseudo-registers.
2 Copyright (C) 1987, 1988, 1991, 1992, 1993, 1994, 1995, 1996
3 1997, 1998, 1999, 2000 Free Software Foundation, Inc.
5 This file is part of GNU CC.
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
23 /* This file contains two passes of the compiler: reg_scan and reg_class.
24 It also defines some tables of information about the hardware registers
25 and a function init_reg_sets to initialize the tables. */
31 #include "hard-reg-set.h"
33 #include "basic-block.h"
36 #include "insn-config.h"
44 #ifndef REGISTER_MOVE_COST
45 #define REGISTER_MOVE_COST(x, y) 2
48 static void init_reg_sets_1
PARAMS ((void));
49 static void init_reg_modes
PARAMS ((void));
51 /* If we have auto-increment or auto-decrement and we can have secondary
52 reloads, we are not allowed to use classes requiring secondary
53 reloads for pseudos auto-incremented since reload can't handle it. */
56 #if defined(SECONDARY_INPUT_RELOAD_CLASS) || defined(SECONDARY_OUTPUT_RELOAD_CLASS)
57 #define FORBIDDEN_INC_DEC_CLASSES
61 /* Register tables used by many passes. */
63 /* Indexed by hard register number, contains 1 for registers
64 that are fixed use (stack pointer, pc, frame pointer, etc.).
65 These are the registers that cannot be used to allocate
66 a pseudo reg for general use. */
68 char fixed_regs
[FIRST_PSEUDO_REGISTER
];
70 /* Same info as a HARD_REG_SET. */
72 HARD_REG_SET fixed_reg_set
;
74 /* Data for initializing the above. */
76 static char initial_fixed_regs
[] = FIXED_REGISTERS
;
78 /* Indexed by hard register number, contains 1 for registers
79 that are fixed use or are clobbered by function calls.
80 These are the registers that cannot be used to allocate
81 a pseudo reg whose life crosses calls unless we are able
82 to save/restore them across the calls. */
84 char call_used_regs
[FIRST_PSEUDO_REGISTER
];
86 /* Same info as a HARD_REG_SET. */
88 HARD_REG_SET call_used_reg_set
;
90 /* HARD_REG_SET of registers we want to avoid caller saving. */
91 HARD_REG_SET losing_caller_save_reg_set
;
93 /* Data for initializing the above. */
95 static char initial_call_used_regs
[] = CALL_USED_REGISTERS
;
97 /* Indexed by hard register number, contains 1 for registers that are
98 fixed use or call used registers that cannot hold quantities across
99 calls even if we are willing to save and restore them. call fixed
100 registers are a subset of call used registers. */
102 char call_fixed_regs
[FIRST_PSEUDO_REGISTER
];
104 /* The same info as a HARD_REG_SET. */
106 HARD_REG_SET call_fixed_reg_set
;
108 /* Number of non-fixed registers. */
110 int n_non_fixed_regs
;
112 /* Indexed by hard register number, contains 1 for registers
113 that are being used for global register decls.
114 These must be exempt from ordinary flow analysis
115 and are also considered fixed. */
117 char global_regs
[FIRST_PSEUDO_REGISTER
];
119 /* Table of register numbers in the order in which to try to use them. */
120 #ifdef REG_ALLOC_ORDER
121 int reg_alloc_order
[FIRST_PSEUDO_REGISTER
] = REG_ALLOC_ORDER
;
123 /* The inverse of reg_alloc_order. */
124 int inv_reg_alloc_order
[FIRST_PSEUDO_REGISTER
];
127 /* For each reg class, a HARD_REG_SET saying which registers are in it. */
129 HARD_REG_SET reg_class_contents
[N_REG_CLASSES
];
131 /* The same information, but as an array of unsigned ints. We copy from
132 these unsigned ints to the table above. We do this so the tm.h files
133 do not have to be aware of the wordsize for machines with <= 64 regs. */
136 ((FIRST_PSEUDO_REGISTER + (HOST_BITS_PER_INT - 1)) / HOST_BITS_PER_INT)
138 static unsigned int_reg_class_contents
[N_REG_CLASSES
][N_REG_INTS
]
139 = REG_CLASS_CONTENTS
;
141 /* For each reg class, number of regs it contains. */
143 unsigned int reg_class_size
[N_REG_CLASSES
];
145 /* For each reg class, table listing all the containing classes. */
147 enum reg_class reg_class_superclasses
[N_REG_CLASSES
][N_REG_CLASSES
];
149 /* For each reg class, table listing all the classes contained in it. */
151 enum reg_class reg_class_subclasses
[N_REG_CLASSES
][N_REG_CLASSES
];
153 /* For each pair of reg classes,
154 a largest reg class contained in their union. */
156 enum reg_class reg_class_subunion
[N_REG_CLASSES
][N_REG_CLASSES
];
158 /* For each pair of reg classes,
159 the smallest reg class containing their union. */
161 enum reg_class reg_class_superunion
[N_REG_CLASSES
][N_REG_CLASSES
];
163 /* Array containing all of the register names. Unless
164 DEBUG_REGISTER_NAMES is defined, use the copy in print-rtl.c. */
166 #ifdef DEBUG_REGISTER_NAMES
167 const char * reg_names
[] = REGISTER_NAMES
;
170 /* For each hard register, the widest mode object that it can contain.
171 This will be a MODE_INT mode if the register can hold integers. Otherwise
172 it will be a MODE_FLOAT or a MODE_CC mode, whichever is valid for the
175 enum machine_mode reg_raw_mode
[FIRST_PSEUDO_REGISTER
];
177 /* Maximum cost of moving from a register in one class to a register in
178 another class. Based on REGISTER_MOVE_COST. */
180 static int move_cost
[N_REG_CLASSES
][N_REG_CLASSES
];
182 /* Similar, but here we don't have to move if the first index is a subset
183 of the second so in that case the cost is zero. */
185 static int may_move_in_cost
[N_REG_CLASSES
][N_REG_CLASSES
];
187 /* Similar, but here we don't have to move if the first index is a superset
188 of the second so in that case the cost is zero. */
190 static int may_move_out_cost
[N_REG_CLASSES
][N_REG_CLASSES
];
192 #ifdef FORBIDDEN_INC_DEC_CLASSES
194 /* These are the classes that regs which are auto-incremented or decremented
197 static int forbidden_inc_dec_class
[N_REG_CLASSES
];
199 /* Indexed by n, is non-zero if (REG n) is used in an auto-inc or auto-dec
202 static char *in_inc_dec
;
204 #endif /* FORBIDDEN_INC_DEC_CLASSES */
206 #ifdef CLASS_CANNOT_CHANGE_SIZE
208 /* These are the classes containing only registers that can be used in
209 a SUBREG expression that changes the size of the register. */
211 static int class_can_change_size
[N_REG_CLASSES
];
213 /* Registers, including pseudos, which change size. */
215 static regset reg_changes_size
;
217 #endif /* CLASS_CANNOT_CHANGE_SIZE */
219 #ifdef HAVE_SECONDARY_RELOADS
221 /* Sample MEM values for use by memory_move_secondary_cost. */
223 static rtx top_of_stack
[MAX_MACHINE_MODE
];
225 #endif /* HAVE_SECONDARY_RELOADS */
227 /* Linked list of reg_info structures allocated for reg_n_info array.
228 Grouping all of the allocated structures together in one lump
229 means only one call to bzero to clear them, rather than n smaller
231 struct reg_info_data
{
232 struct reg_info_data
*next
; /* next set of reg_info structures */
233 size_t min_index
; /* minimum index # */
234 size_t max_index
; /* maximum index # */
235 char used_p
; /* non-zero if this has been used previously */
236 reg_info data
[1]; /* beginning of the reg_info data */
239 static struct reg_info_data
*reg_info_head
;
241 /* No more global register variables may be declared; true once
242 regclass has been initialized. */
244 static int no_global_reg_vars
= 0;
247 /* Function called only once to initialize the above data on reg usage.
248 Once this is done, various switches may override. */
255 /* First copy the register information from the initial int form into
258 for (i
= 0; i
< N_REG_CLASSES
; i
++)
260 CLEAR_HARD_REG_SET (reg_class_contents
[i
]);
262 for (j
= 0; j
< FIRST_PSEUDO_REGISTER
; j
++)
263 if (int_reg_class_contents
[i
][j
/ HOST_BITS_PER_INT
]
264 & ((unsigned) 1 << (j
% HOST_BITS_PER_INT
)))
265 SET_HARD_REG_BIT (reg_class_contents
[i
], j
);
268 bcopy (initial_fixed_regs
, fixed_regs
, sizeof fixed_regs
);
269 bcopy (initial_call_used_regs
, call_used_regs
, sizeof call_used_regs
);
270 bzero (global_regs
, sizeof global_regs
);
272 /* Do any additional initialization regsets may need */
273 INIT_ONCE_REG_SET ();
275 #ifdef REG_ALLOC_ORDER
276 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
277 inv_reg_alloc_order
[reg_alloc_order
[i
]] = i
;
281 /* After switches have been processed, which perhaps alter
282 `fixed_regs' and `call_used_regs', convert them to HARD_REG_SETs. */
287 register unsigned int i
, j
;
289 /* This macro allows the fixed or call-used registers
290 and the register classes to depend on target flags. */
292 #ifdef CONDITIONAL_REGISTER_USAGE
293 CONDITIONAL_REGISTER_USAGE
;
296 /* Compute number of hard regs in each class. */
298 bzero ((char *) reg_class_size
, sizeof reg_class_size
);
299 for (i
= 0; i
< N_REG_CLASSES
; i
++)
300 for (j
= 0; j
< FIRST_PSEUDO_REGISTER
; j
++)
301 if (TEST_HARD_REG_BIT (reg_class_contents
[i
], j
))
304 /* Initialize the table of subunions.
305 reg_class_subunion[I][J] gets the largest-numbered reg-class
306 that is contained in the union of classes I and J. */
308 for (i
= 0; i
< N_REG_CLASSES
; i
++)
310 for (j
= 0; j
< N_REG_CLASSES
; j
++)
313 register /* Declare it register if it's a scalar. */
318 COPY_HARD_REG_SET (c
, reg_class_contents
[i
]);
319 IOR_HARD_REG_SET (c
, reg_class_contents
[j
]);
320 for (k
= 0; k
< N_REG_CLASSES
; k
++)
322 GO_IF_HARD_REG_SUBSET (reg_class_contents
[k
], c
,
327 /* keep the largest subclass */ /* SPEE 900308 */
328 GO_IF_HARD_REG_SUBSET (reg_class_contents
[k
],
329 reg_class_contents
[(int) reg_class_subunion
[i
][j
]],
331 reg_class_subunion
[i
][j
] = (enum reg_class
) k
;
338 /* Initialize the table of superunions.
339 reg_class_superunion[I][J] gets the smallest-numbered reg-class
340 containing the union of classes I and J. */
342 for (i
= 0; i
< N_REG_CLASSES
; i
++)
344 for (j
= 0; j
< N_REG_CLASSES
; j
++)
347 register /* Declare it register if it's a scalar. */
352 COPY_HARD_REG_SET (c
, reg_class_contents
[i
]);
353 IOR_HARD_REG_SET (c
, reg_class_contents
[j
]);
354 for (k
= 0; k
< N_REG_CLASSES
; k
++)
355 GO_IF_HARD_REG_SUBSET (c
, reg_class_contents
[k
], superclass
);
358 reg_class_superunion
[i
][j
] = (enum reg_class
) k
;
362 /* Initialize the tables of subclasses and superclasses of each reg class.
363 First clear the whole table, then add the elements as they are found. */
365 for (i
= 0; i
< N_REG_CLASSES
; i
++)
367 for (j
= 0; j
< N_REG_CLASSES
; j
++)
369 reg_class_superclasses
[i
][j
] = LIM_REG_CLASSES
;
370 reg_class_subclasses
[i
][j
] = LIM_REG_CLASSES
;
374 for (i
= 0; i
< N_REG_CLASSES
; i
++)
376 if (i
== (int) NO_REGS
)
379 for (j
= i
+ 1; j
< N_REG_CLASSES
; j
++)
383 GO_IF_HARD_REG_SUBSET (reg_class_contents
[i
], reg_class_contents
[j
],
387 /* Reg class I is a subclass of J.
388 Add J to the table of superclasses of I. */
389 p
= ®_class_superclasses
[i
][0];
390 while (*p
!= LIM_REG_CLASSES
) p
++;
391 *p
= (enum reg_class
) j
;
392 /* Add I to the table of superclasses of J. */
393 p
= ®_class_subclasses
[j
][0];
394 while (*p
!= LIM_REG_CLASSES
) p
++;
395 *p
= (enum reg_class
) i
;
399 /* Initialize "constant" tables. */
401 CLEAR_HARD_REG_SET (fixed_reg_set
);
402 CLEAR_HARD_REG_SET (call_used_reg_set
);
403 CLEAR_HARD_REG_SET (call_fixed_reg_set
);
405 bcopy (fixed_regs
, call_fixed_regs
, sizeof call_fixed_regs
);
407 n_non_fixed_regs
= 0;
409 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
412 SET_HARD_REG_BIT (fixed_reg_set
, i
);
416 if (call_used_regs
[i
])
417 SET_HARD_REG_BIT (call_used_reg_set
, i
);
418 if (call_fixed_regs
[i
])
419 SET_HARD_REG_BIT (call_fixed_reg_set
, i
);
420 if (CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (i
)))
421 SET_HARD_REG_BIT (losing_caller_save_reg_set
, i
);
424 /* Initialize the move cost table. Find every subset of each class
425 and take the maximum cost of moving any subset to any other. */
427 for (i
= 0; i
< N_REG_CLASSES
; i
++)
428 for (j
= 0; j
< N_REG_CLASSES
; j
++)
430 int cost
= i
== j
? 2 : REGISTER_MOVE_COST (i
, j
);
431 enum reg_class
*p1
, *p2
;
433 for (p2
= ®_class_subclasses
[j
][0]; *p2
!= LIM_REG_CLASSES
; p2
++)
435 cost
= MAX (cost
, REGISTER_MOVE_COST (i
, *p2
));
437 for (p1
= ®_class_subclasses
[i
][0]; *p1
!= LIM_REG_CLASSES
; p1
++)
440 cost
= MAX (cost
, REGISTER_MOVE_COST (*p1
, j
));
442 for (p2
= ®_class_subclasses
[j
][0];
443 *p2
!= LIM_REG_CLASSES
; p2
++)
445 cost
= MAX (cost
, REGISTER_MOVE_COST (*p1
, *p2
));
448 move_cost
[i
][j
] = cost
;
450 if (reg_class_subset_p (i
, j
))
451 may_move_in_cost
[i
][j
] = 0;
453 may_move_in_cost
[i
][j
] = cost
;
455 if (reg_class_subset_p (j
, i
))
456 may_move_out_cost
[i
][j
] = 0;
458 may_move_out_cost
[i
][j
] = cost
;
461 #ifdef CLASS_CANNOT_CHANGE_SIZE
464 COMPL_HARD_REG_SET (c
, reg_class_contents
[CLASS_CANNOT_CHANGE_SIZE
]);
466 for (i
= 0; i
< N_REG_CLASSES
; i
++)
468 GO_IF_HARD_REG_SUBSET (reg_class_contents
[i
], c
, ok_class
);
469 class_can_change_size
[i
] = 0;
472 class_can_change_size
[i
] = 1;
475 #endif /* CLASS_CANNOT_CHANGE_SIZE */
478 /* Compute the table of register modes.
479 These values are used to record death information for individual registers
480 (as opposed to a multi-register mode). */
487 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
489 reg_raw_mode
[i
] = choose_hard_reg_mode (i
, 1);
491 /* If we couldn't find a valid mode, just use the previous mode.
492 ??? One situation in which we need to do this is on the mips where
493 HARD_REGNO_NREGS (fpreg, [SD]Fmode) returns 2. Ideally we'd like
494 to use DF mode for the even registers and VOIDmode for the odd
495 (for the cpu models where the odd ones are inaccessible). */
496 if (reg_raw_mode
[i
] == VOIDmode
)
497 reg_raw_mode
[i
] = i
== 0 ? word_mode
: reg_raw_mode
[i
-1];
501 /* Finish initializing the register sets and
502 initialize the register modes. */
507 /* This finishes what was started by init_reg_sets, but couldn't be done
508 until after register usage was specified. */
513 #ifdef HAVE_SECONDARY_RELOADS
515 /* Make some fake stack-frame MEM references for use in
516 memory_move_secondary_cost. */
519 for (i
= 0; i
< MAX_MACHINE_MODE
; i
++)
520 top_of_stack
[i
] = gen_rtx_MEM (i
, stack_pointer_rtx
);
521 ggc_add_rtx_root (top_of_stack
, MAX_MACHINE_MODE
);
526 #ifdef HAVE_SECONDARY_RELOADS
528 /* Compute extra cost of moving registers to/from memory due to reloads.
529 Only needed if secondary reloads are required for memory moves. */
532 memory_move_secondary_cost (mode
, class, in
)
533 enum machine_mode mode
;
534 enum reg_class
class;
537 enum reg_class altclass
;
538 int partial_cost
= 0;
539 /* We need a memory reference to feed to SECONDARY... macros. */
540 /* mem may be unused even if the SECONDARY_ macros are defined. */
541 rtx mem ATTRIBUTE_UNUSED
= top_of_stack
[(int) mode
];
546 #ifdef SECONDARY_INPUT_RELOAD_CLASS
547 altclass
= SECONDARY_INPUT_RELOAD_CLASS (class, mode
, mem
);
554 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
555 altclass
= SECONDARY_OUTPUT_RELOAD_CLASS (class, mode
, mem
);
561 if (altclass
== NO_REGS
)
565 partial_cost
= REGISTER_MOVE_COST (altclass
, class);
567 partial_cost
= REGISTER_MOVE_COST (class, altclass
);
569 if (class == altclass
)
570 /* This isn't simply a copy-to-temporary situation. Can't guess
571 what it is, so MEMORY_MOVE_COST really ought not to be calling
574 I'm tempted to put in an abort here, but returning this will
575 probably only give poor estimates, which is what we would've
576 had before this code anyways. */
579 /* Check if the secondary reload register will also need a
581 return memory_move_secondary_cost (mode
, altclass
, in
) + partial_cost
;
585 /* Return a machine mode that is legitimate for hard reg REGNO and large
586 enough to save nregs. If we can't find one, return VOIDmode. */
589 choose_hard_reg_mode (regno
, nregs
)
590 unsigned int regno ATTRIBUTE_UNUSED
;
593 enum machine_mode found_mode
= VOIDmode
, mode
;
595 /* We first look for the largest integer mode that can be validly
596 held in REGNO. If none, we look for the largest floating-point mode.
597 If we still didn't find a valid mode, try CCmode. */
599 for (mode
= GET_CLASS_NARROWEST_MODE (MODE_INT
);
601 mode
= GET_MODE_WIDER_MODE (mode
))
602 if (HARD_REGNO_NREGS (regno
, mode
) == nregs
603 && HARD_REGNO_MODE_OK (regno
, mode
))
606 if (found_mode
!= VOIDmode
)
609 for (mode
= GET_CLASS_NARROWEST_MODE (MODE_FLOAT
);
611 mode
= GET_MODE_WIDER_MODE (mode
))
612 if (HARD_REGNO_NREGS (regno
, mode
) == nregs
613 && HARD_REGNO_MODE_OK (regno
, mode
))
616 if (found_mode
!= VOIDmode
)
619 if (HARD_REGNO_NREGS (regno
, CCmode
) == nregs
620 && HARD_REGNO_MODE_OK (regno
, CCmode
))
623 /* We can't find a mode valid for this register. */
627 /* Specify the usage characteristics of the register named NAME.
628 It should be a fixed register if FIXED and a
629 call-used register if CALL_USED. */
632 fix_register (name
, fixed
, call_used
)
634 int fixed
, call_used
;
638 /* Decode the name and update the primary form of
639 the register info. */
641 if ((i
= decode_reg_name (name
)) >= 0)
643 if ((i
== STACK_POINTER_REGNUM
644 #ifdef HARD_FRAME_POINTER_REGNUM
645 || i
== HARD_FRAME_POINTER_REGNUM
647 || i
== FRAME_POINTER_REGNUM
650 && (fixed
== 0 || call_used
== 0))
652 static const char * const what_option
[2][2] = {
653 { "call-saved", "call-used" },
654 { "no-such-option", "fixed" }};
656 error ("can't use '%s' as a %s register", name
,
657 what_option
[fixed
][call_used
]);
661 fixed_regs
[i
] = fixed
;
662 call_used_regs
[i
] = call_used
;
667 warning ("unknown register name: %s", name
);
671 /* Mark register number I as global. */
677 if (fixed_regs
[i
] == 0 && no_global_reg_vars
)
678 error ("global register variable follows a function definition");
682 warning ("register used for two global register variables");
686 if (call_used_regs
[i
] && ! fixed_regs
[i
])
687 warning ("call-clobbered register used for global register variable");
691 /* If already fixed, nothing else to do. */
695 fixed_regs
[i
] = call_used_regs
[i
] = call_fixed_regs
[i
] = 1;
698 SET_HARD_REG_BIT (fixed_reg_set
, i
);
699 SET_HARD_REG_BIT (call_used_reg_set
, i
);
700 SET_HARD_REG_BIT (call_fixed_reg_set
, i
);
703 /* Now the data and code for the `regclass' pass, which happens
704 just before local-alloc. */
706 /* The `costs' struct records the cost of using a hard register of each class
707 and of using memory for each pseudo. We use this data to set up
708 register class preferences. */
712 int cost
[N_REG_CLASSES
];
716 /* Structure used to record preferrences of given pseudo. */
719 /* (enum reg_class) prefclass is the preferred class. */
722 /* altclass is a register class that we should use for allocating
723 pseudo if no register in the preferred class is available.
724 If no register in this class is available, memory is preferred.
726 It might appear to be more general to have a bitmask of classes here,
727 but since it is recommended that there be a class corresponding to the
728 union of most major pair of classes, that generality is not required. */
732 /* Record the cost of each class for each pseudo. */
734 static struct costs
*costs
;
736 /* Initialized once, and used to initialize cost values for each insn. */
738 static struct costs init_cost
;
740 /* Record preferrences of each pseudo.
741 This is available after `regclass' is run. */
743 static struct reg_pref
*reg_pref
;
745 /* Allocated buffers for reg_pref. */
747 static struct reg_pref
*reg_pref_buffer
;
749 /* Account for the fact that insns within a loop are executed very commonly,
750 but don't keep doing this as loops go too deep. */
752 static int loop_cost
;
754 static rtx scan_one_insn
PARAMS ((rtx
, int));
755 static void record_operand_costs
PARAMS ((rtx
, struct costs
*, struct reg_pref
*));
756 static void dump_regclass
PARAMS ((FILE *));
757 static void record_reg_classes
PARAMS ((int, int, rtx
*, enum machine_mode
*,
759 struct costs
*, struct reg_pref
*));
760 static int copy_cost
PARAMS ((rtx
, enum machine_mode
,
761 enum reg_class
, int));
762 static void record_address_regs
PARAMS ((rtx
, enum reg_class
, int));
763 #ifdef FORBIDDEN_INC_DEC_CLASSES
764 static int auto_inc_dec_reg_p
PARAMS ((rtx
, enum machine_mode
));
766 static void reg_scan_mark_refs
PARAMS ((rtx
, rtx
, int, unsigned int));
768 /* Return the reg_class in which pseudo reg number REGNO is best allocated.
769 This function is sometimes called before the info has been computed.
770 When that happens, just return GENERAL_REGS, which is innocuous. */
773 reg_preferred_class (regno
)
778 return (enum reg_class
) reg_pref
[regno
].prefclass
;
782 reg_alternate_class (regno
)
788 return (enum reg_class
) reg_pref
[regno
].altclass
;
791 /* Initialize some global data for this pass. */
798 init_cost
.mem_cost
= 10000;
799 for (i
= 0; i
< N_REG_CLASSES
; i
++)
800 init_cost
.cost
[i
] = 10000;
802 /* This prevents dump_flow_info from losing if called
803 before regclass is run. */
806 /* No more global register variables may be declared. */
807 no_global_reg_vars
= 1;
810 /* Dump register costs. */
815 static const char *const reg_class_names
[] = REG_CLASS_NAMES
;
817 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
819 enum reg_class
class;
822 fprintf (dump
, " Register %i costs:", i
);
823 for (class = 0; class < N_REG_CLASSES
; class++)
824 fprintf (dump
, " %s:%i", reg_class_names
[(int) class],
825 costs
[i
].cost
[class]);
826 fprintf (dump
, " MEM:%i\n", costs
[i
].mem_cost
);
832 /* Calculate the costs of insn operands. */
835 record_operand_costs (insn
, op_costs
, reg_pref
)
837 struct costs
*op_costs
;
838 struct reg_pref
*reg_pref
;
840 const char *constraints
[MAX_RECOG_OPERANDS
];
841 enum machine_mode modes
[MAX_RECOG_OPERANDS
];
844 for (i
= 0; i
< recog_data
.n_operands
; i
++)
846 constraints
[i
] = recog_data
.constraints
[i
];
847 modes
[i
] = recog_data
.operand_mode
[i
];
850 /* If we get here, we are set up to record the costs of all the
851 operands for this insn. Start by initializing the costs.
852 Then handle any address registers. Finally record the desired
853 classes for any pseudos, doing it twice if some pair of
854 operands are commutative. */
856 for (i
= 0; i
< recog_data
.n_operands
; i
++)
858 op_costs
[i
] = init_cost
;
860 if (GET_CODE (recog_data
.operand
[i
]) == SUBREG
)
862 rtx inner
= SUBREG_REG (recog_data
.operand
[i
]);
863 #ifdef CLASS_CANNOT_CHANGE_SIZE
864 if (GET_MODE_SIZE (modes
[i
]) != GET_MODE_SIZE (GET_MODE (inner
))
865 && GET_CODE (inner
) == REG
)
866 SET_REGNO_REG_SET (reg_changes_size
, REGNO (inner
));
868 recog_data
.operand
[i
] = inner
;
871 if (GET_CODE (recog_data
.operand
[i
]) == MEM
)
872 record_address_regs (XEXP (recog_data
.operand
[i
], 0),
873 BASE_REG_CLASS
, loop_cost
* 2);
874 else if (constraints
[i
][0] == 'p')
875 record_address_regs (recog_data
.operand
[i
],
876 BASE_REG_CLASS
, loop_cost
* 2);
879 /* Check for commutative in a separate loop so everything will
880 have been initialized. We must do this even if one operand
881 is a constant--see addsi3 in m68k.md. */
883 for (i
= 0; i
< (int) recog_data
.n_operands
- 1; i
++)
884 if (constraints
[i
][0] == '%')
886 const char *xconstraints
[MAX_RECOG_OPERANDS
];
889 /* Handle commutative operands by swapping the constraints.
890 We assume the modes are the same. */
892 for (j
= 0; j
< recog_data
.n_operands
; j
++)
893 xconstraints
[j
] = constraints
[j
];
895 xconstraints
[i
] = constraints
[i
+1];
896 xconstraints
[i
+1] = constraints
[i
];
897 record_reg_classes (recog_data
.n_alternatives
, recog_data
.n_operands
,
898 recog_data
.operand
, modes
,
899 xconstraints
, insn
, op_costs
, reg_pref
);
902 record_reg_classes (recog_data
.n_alternatives
, recog_data
.n_operands
,
903 recog_data
.operand
, modes
,
904 constraints
, insn
, op_costs
, reg_pref
);
907 /* Subroutine of regclass, processes one insn INSN. Scan it and record each
908 time it would save code to put a certain register in a certain class.
909 PASS, when nonzero, inhibits some optimizations which need only be done
911 Return the last insn processed, so that the scan can be continued from
915 scan_one_insn (insn
, pass
)
919 enum rtx_code code
= GET_CODE (insn
);
920 enum rtx_code pat_code
;
923 struct costs op_costs
[MAX_RECOG_OPERANDS
];
925 if (GET_RTX_CLASS (code
) != 'i')
928 pat_code
= GET_CODE (PATTERN (insn
));
930 || pat_code
== CLOBBER
931 || pat_code
== ASM_INPUT
932 || pat_code
== ADDR_VEC
933 || pat_code
== ADDR_DIFF_VEC
)
936 set
= single_set (insn
);
939 /* If this insn loads a parameter from its stack slot, then
940 it represents a savings, rather than a cost, if the
941 parameter is stored in memory. Record this fact. */
943 if (set
!= 0 && GET_CODE (SET_DEST (set
)) == REG
944 && GET_CODE (SET_SRC (set
)) == MEM
945 && (note
= find_reg_note (insn
, REG_EQUIV
,
947 && GET_CODE (XEXP (note
, 0)) == MEM
)
949 costs
[REGNO (SET_DEST (set
))].mem_cost
950 -= (MEMORY_MOVE_COST (GET_MODE (SET_DEST (set
)),
953 record_address_regs (XEXP (SET_SRC (set
), 0),
954 BASE_REG_CLASS
, loop_cost
* 2);
958 /* Improve handling of two-address insns such as
959 (set X (ashift CONST Y)) where CONST must be made to
960 match X. Change it into two insns: (set X CONST)
961 (set X (ashift X Y)). If we left this for reloading, it
962 would probably get three insns because X and Y might go
963 in the same place. This prevents X and Y from receiving
966 We can only do this if the modes of operands 0 and 1
967 (which might not be the same) are tieable and we only need
968 do this during our first pass. */
970 if (pass
== 0 && optimize
971 && recog_data
.n_operands
>= 3
972 && recog_data
.constraints
[1][0] == '0'
973 && recog_data
.constraints
[1][1] == 0
974 && CONSTANT_P (recog_data
.operand
[1])
975 && ! rtx_equal_p (recog_data
.operand
[0], recog_data
.operand
[1])
976 && ! rtx_equal_p (recog_data
.operand
[0], recog_data
.operand
[2])
977 && GET_CODE (recog_data
.operand
[0]) == REG
978 && MODES_TIEABLE_P (GET_MODE (recog_data
.operand
[0]),
979 recog_data
.operand_mode
[1]))
981 rtx previnsn
= prev_real_insn (insn
);
983 = gen_lowpart (recog_data
.operand_mode
[1],
984 recog_data
.operand
[0]);
986 = emit_insn_before (gen_move_insn (dest
, recog_data
.operand
[1]), insn
);
988 /* If this insn was the start of a basic block,
989 include the new insn in that block.
990 We need not check for code_label here;
991 while a basic block can start with a code_label,
992 INSN could not be at the beginning of that block. */
993 if (previnsn
== 0 || GET_CODE (previnsn
) == JUMP_INSN
)
996 for (b
= 0; b
< n_basic_blocks
; b
++)
997 if (insn
== BLOCK_HEAD (b
))
998 BLOCK_HEAD (b
) = newinsn
;
1001 /* This makes one more setting of new insns's dest. */
1002 REG_N_SETS (REGNO (recog_data
.operand
[0]))++;
1004 *recog_data
.operand_loc
[1] = recog_data
.operand
[0];
1005 for (i
= recog_data
.n_dups
- 1; i
>= 0; i
--)
1006 if (recog_data
.dup_num
[i
] == 1)
1007 *recog_data
.dup_loc
[i
] = recog_data
.operand
[0];
1009 return PREV_INSN (newinsn
);
1012 record_operand_costs (insn
, op_costs
, reg_pref
);
1014 /* Now add the cost for each operand to the total costs for
1017 for (i
= 0; i
< recog_data
.n_operands
; i
++)
1018 if (GET_CODE (recog_data
.operand
[i
]) == REG
1019 && REGNO (recog_data
.operand
[i
]) >= FIRST_PSEUDO_REGISTER
)
1021 int regno
= REGNO (recog_data
.operand
[i
]);
1022 struct costs
*p
= &costs
[regno
], *q
= &op_costs
[i
];
1024 p
->mem_cost
+= q
->mem_cost
* loop_cost
;
1025 for (j
= 0; j
< N_REG_CLASSES
; j
++)
1026 p
->cost
[j
] += q
->cost
[j
] * loop_cost
;
1032 /* This is a pass of the compiler that scans all instructions
1033 and calculates the preferred class for each pseudo-register.
1034 This information can be accessed later by calling `reg_preferred_class'.
1035 This pass comes just before local register allocation. */
1038 regclass (f
, nregs
, dump
)
1049 costs
= (struct costs
*) xmalloc (nregs
* sizeof (struct costs
));
1051 #ifdef CLASS_CANNOT_CHANGE_SIZE
1052 reg_changes_size
= BITMAP_XMALLOC();
1055 #ifdef FORBIDDEN_INC_DEC_CLASSES
1057 in_inc_dec
= (char *) xmalloc (nregs
);
1059 /* Initialize information about which register classes can be used for
1060 pseudos that are auto-incremented or auto-decremented. It would
1061 seem better to put this in init_reg_sets, but we need to be able
1062 to allocate rtx, which we can't do that early. */
1064 for (i
= 0; i
< N_REG_CLASSES
; i
++)
1066 rtx r
= gen_rtx_REG (VOIDmode
, 0);
1067 enum machine_mode m
;
1070 for (j
= 0; j
< FIRST_PSEUDO_REGISTER
; j
++)
1071 if (TEST_HARD_REG_BIT (reg_class_contents
[i
], j
))
1075 for (m
= VOIDmode
; (int) m
< (int) MAX_MACHINE_MODE
;
1076 m
= (enum machine_mode
) ((int) m
+ 1))
1077 if (HARD_REGNO_MODE_OK (j
, m
))
1081 /* If a register is not directly suitable for an
1082 auto-increment or decrement addressing mode and
1083 requires secondary reloads, disallow its class from
1084 being used in such addresses. */
1087 #ifdef SECONDARY_RELOAD_CLASS
1088 || (SECONDARY_RELOAD_CLASS (BASE_REG_CLASS
, m
, r
)
1091 #ifdef SECONDARY_INPUT_RELOAD_CLASS
1092 || (SECONDARY_INPUT_RELOAD_CLASS (BASE_REG_CLASS
, m
, r
)
1095 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
1096 || (SECONDARY_OUTPUT_RELOAD_CLASS (BASE_REG_CLASS
, m
, r
)
1101 && ! auto_inc_dec_reg_p (r
, m
))
1102 forbidden_inc_dec_class
[i
] = 1;
1106 #endif /* FORBIDDEN_INC_DEC_CLASSES */
1108 /* Normally we scan the insns once and determine the best class to use for
1109 each register. However, if -fexpensive_optimizations are on, we do so
1110 twice, the second time using the tentative best classes to guide the
1113 for (pass
= 0; pass
<= flag_expensive_optimizations
; pass
++)
1118 fprintf (dump
, "\n\nPass %i\n\n",pass
);
1119 /* Zero out our accumulation of the cost of each class for each reg. */
1121 bzero ((char *) costs
, nregs
* sizeof (struct costs
));
1123 #ifdef FORBIDDEN_INC_DEC_CLASSES
1124 bzero (in_inc_dec
, nregs
);
1127 /* Scan the instructions and record each time it would
1128 save code to put a certain register in a certain class. */
1133 for (insn
= f
; insn
; insn
= NEXT_INSN (insn
))
1134 insn
= scan_one_insn (insn
, pass
);
1137 for (index
= 0; index
< n_basic_blocks
; index
++)
1139 basic_block bb
= BASIC_BLOCK (index
);
1141 /* Show that an insn inside a loop is likely to be executed three
1142 times more than insns outside a loop. This is much more
1143 aggressive than the assumptions made elsewhere and is being
1144 tried as an experiment. */
1148 loop_cost
= 1 << (2 * MIN (bb
->loop_depth
, 5));
1149 for (insn
= bb
->head
; ; insn
= NEXT_INSN (insn
))
1151 insn
= scan_one_insn (insn
, pass
);
1152 if (insn
== bb
->end
)
1157 /* Now for each register look at how desirable each class is
1158 and find which class is preferred. Store that in
1159 `prefclass'. Record in `altclass' the largest register
1160 class any of whose registers is better than memory. */
1163 reg_pref
= reg_pref_buffer
;
1167 dump_regclass (dump
);
1168 fprintf (dump
,"\n");
1170 for (i
= FIRST_PSEUDO_REGISTER
; i
< nregs
; i
++)
1172 register int best_cost
= (1 << (HOST_BITS_PER_INT
- 2)) - 1;
1173 enum reg_class best
= ALL_REGS
, alt
= NO_REGS
;
1174 /* This is an enum reg_class, but we call it an int
1175 to save lots of casts. */
1177 register struct costs
*p
= &costs
[i
];
1179 /* In non-optimizing compilation REG_N_REFS is not initialized
1181 if (optimize
&& !REG_N_REFS (i
))
1184 for (class = (int) ALL_REGS
- 1; class > 0; class--)
1186 /* Ignore classes that are too small for this operand or
1187 invalid for a operand that was auto-incremented. */
1188 if (CLASS_MAX_NREGS (class, PSEUDO_REGNO_MODE (i
))
1189 > reg_class_size
[class]
1190 #ifdef FORBIDDEN_INC_DEC_CLASSES
1191 || (in_inc_dec
[i
] && forbidden_inc_dec_class
[class])
1193 #ifdef CLASS_CANNOT_CHANGE_SIZE
1194 || (REGNO_REG_SET_P (reg_changes_size
, i
)
1195 && ! class_can_change_size
[class])
1199 else if (p
->cost
[class] < best_cost
)
1201 best_cost
= p
->cost
[class];
1202 best
= (enum reg_class
) class;
1204 else if (p
->cost
[class] == best_cost
)
1205 best
= reg_class_subunion
[(int)best
][class];
1208 /* Record the alternate register class; i.e., a class for which
1209 every register in it is better than using memory. If adding a
1210 class would make a smaller class (i.e., no union of just those
1211 classes exists), skip that class. The major unions of classes
1212 should be provided as a register class. Don't do this if we
1213 will be doing it again later. */
1215 if ((pass
== 1 || dump
) || ! flag_expensive_optimizations
)
1216 for (class = 0; class < N_REG_CLASSES
; class++)
1217 if (p
->cost
[class] < p
->mem_cost
1218 && (reg_class_size
[(int) reg_class_subunion
[(int) alt
][class]]
1219 > reg_class_size
[(int) alt
])
1220 #ifdef FORBIDDEN_INC_DEC_CLASSES
1221 && ! (in_inc_dec
[i
] && forbidden_inc_dec_class
[class])
1223 #ifdef CLASS_CANNOT_CHANGE_SIZE
1224 && ! (REGNO_REG_SET_P (reg_changes_size
, i
)
1225 && ! class_can_change_size
[class])
1228 alt
= reg_class_subunion
[(int) alt
][class];
1230 /* If we don't add any classes, nothing to try. */
1235 && (reg_pref
[i
].prefclass
!= (int) best
1236 || reg_pref
[i
].altclass
!= (int) alt
))
1238 static const char *const reg_class_names
[] = REG_CLASS_NAMES
;
1239 fprintf (dump
, " Register %i", i
);
1240 if (alt
== ALL_REGS
|| best
== ALL_REGS
)
1241 fprintf (dump
, " pref %s\n", reg_class_names
[(int) best
]);
1242 else if (alt
== NO_REGS
)
1243 fprintf (dump
, " pref %s or none\n", reg_class_names
[(int) best
]);
1245 fprintf (dump
, " pref %s, else %s\n",
1246 reg_class_names
[(int) best
],
1247 reg_class_names
[(int) alt
]);
1250 /* We cast to (int) because (char) hits bugs in some compilers. */
1251 reg_pref
[i
].prefclass
= (int) best
;
1252 reg_pref
[i
].altclass
= (int) alt
;
1256 #ifdef FORBIDDEN_INC_DEC_CLASSES
1259 #ifdef CLASS_CANNOT_CHANGE_SIZE
1260 BITMAP_XFREE (reg_changes_size
);
1265 /* Record the cost of using memory or registers of various classes for
1266 the operands in INSN.
1268 N_ALTS is the number of alternatives.
1270 N_OPS is the number of operands.
1272 OPS is an array of the operands.
1274 MODES are the modes of the operands, in case any are VOIDmode.
1276 CONSTRAINTS are the constraints to use for the operands. This array
1277 is modified by this procedure.
1279 This procedure works alternative by alternative. For each alternative
1280 we assume that we will be able to allocate all pseudos to their ideal
1281 register class and calculate the cost of using that alternative. Then
1282 we compute for each operand that is a pseudo-register, the cost of
1283 having the pseudo allocated to each register class and using it in that
1284 alternative. To this cost is added the cost of the alternative.
1286 The cost of each class for this insn is its lowest cost among all the
1290 record_reg_classes (n_alts
, n_ops
, ops
, modes
,
1291 constraints
, insn
, op_costs
, reg_pref
)
1295 enum machine_mode
*modes
;
1296 const char **constraints
;
1298 struct costs
*op_costs
;
1299 struct reg_pref
*reg_pref
;
1305 /* Process each alternative, each time minimizing an operand's cost with
1306 the cost for each operand in that alternative. */
1308 for (alt
= 0; alt
< n_alts
; alt
++)
1310 struct costs this_op_costs
[MAX_RECOG_OPERANDS
];
1313 enum reg_class classes
[MAX_RECOG_OPERANDS
];
1314 int allows_mem
[MAX_RECOG_OPERANDS
];
1317 for (i
= 0; i
< n_ops
; i
++)
1319 const char *p
= constraints
[i
];
1321 enum machine_mode mode
= modes
[i
];
1322 int allows_addr
= 0;
1326 /* Initially show we know nothing about the register class. */
1327 classes
[i
] = NO_REGS
;
1330 /* If this operand has no constraints at all, we can conclude
1331 nothing about it since anything is valid. */
1335 if (GET_CODE (op
) == REG
&& REGNO (op
) >= FIRST_PSEUDO_REGISTER
)
1336 bzero ((char *) &this_op_costs
[i
], sizeof this_op_costs
[i
]);
1341 /* If this alternative is only relevant when this operand
1342 matches a previous operand, we do different things depending
1343 on whether this operand is a pseudo-reg or not. We must process
1344 any modifiers for the operand before we can make this test. */
1346 while (*p
== '%' || *p
== '=' || *p
== '+' || *p
== '&')
1349 if (p
[0] >= '0' && p
[0] <= '0' + i
&& (p
[1] == ',' || p
[1] == 0))
1351 /* Copy class and whether memory is allowed from the matching
1352 alternative. Then perform any needed cost computations
1353 and/or adjustments. */
1355 classes
[i
] = classes
[j
];
1356 allows_mem
[i
] = allows_mem
[j
];
1358 if (GET_CODE (op
) != REG
|| REGNO (op
) < FIRST_PSEUDO_REGISTER
)
1360 /* If this matches the other operand, we have no added
1362 if (rtx_equal_p (ops
[j
], op
))
1365 /* If we can put the other operand into a register, add to
1366 the cost of this alternative the cost to copy this
1367 operand to the register used for the other operand. */
1369 else if (classes
[j
] != NO_REGS
)
1370 alt_cost
+= copy_cost (op
, mode
, classes
[j
], 1), win
= 1;
1372 else if (GET_CODE (ops
[j
]) != REG
1373 || REGNO (ops
[j
]) < FIRST_PSEUDO_REGISTER
)
1375 /* This op is a pseudo but the one it matches is not. */
1377 /* If we can't put the other operand into a register, this
1378 alternative can't be used. */
1380 if (classes
[j
] == NO_REGS
)
1383 /* Otherwise, add to the cost of this alternative the cost
1384 to copy the other operand to the register used for this
1388 alt_cost
+= copy_cost (ops
[j
], mode
, classes
[j
], 1);
1392 /* The costs of this operand are not the same as the other
1393 operand since move costs are not symmetric. Moreover,
1394 if we cannot tie them, this alternative needs to do a
1395 copy, which is one instruction. */
1397 struct costs
*pp
= &this_op_costs
[i
];
1399 for (class = 0; class < N_REG_CLASSES
; class++)
1401 = ((recog_data
.operand_type
[i
] != OP_OUT
1402 ? may_move_in_cost
[class][(int) classes
[i
]]
1404 + (recog_data
.operand_type
[i
] != OP_IN
1405 ? may_move_out_cost
[(int) classes
[i
]][class]
1408 /* If the alternative actually allows memory, make things
1409 a bit cheaper since we won't need an extra insn to
1413 = ((recog_data
.operand_type
[i
] != OP_IN
1414 ? MEMORY_MOVE_COST (mode
, classes
[i
], 0)
1416 + (recog_data
.operand_type
[i
] != OP_OUT
1417 ? MEMORY_MOVE_COST (mode
, classes
[i
], 1)
1418 : 0) - allows_mem
[i
]);
1420 /* If we have assigned a class to this register in our
1421 first pass, add a cost to this alternative corresponding
1422 to what we would add if this register were not in the
1423 appropriate class. */
1427 += (may_move_in_cost
[(unsigned char) reg_pref
[REGNO (op
)].prefclass
]
1428 [(int) classes
[i
]]);
1430 if (REGNO (ops
[i
]) != REGNO (ops
[j
])
1431 && ! find_reg_note (insn
, REG_DEAD
, op
))
1434 /* This is in place of ordinary cost computation
1435 for this operand, so skip to the end of the
1436 alternative (should be just one character). */
1437 while (*p
&& *p
++ != ',')
1445 /* Scan all the constraint letters. See if the operand matches
1446 any of the constraints. Collect the valid register classes
1447 and see if this operand accepts memory. */
1449 while (*p
&& (c
= *p
++) != ',')
1453 /* Ignore the next letter for this pass. */
1459 case '!': case '#': case '&':
1460 case '0': case '1': case '2': case '3': case '4':
1461 case '5': case '6': case '7': case '8': case '9':
1466 win
= address_operand (op
, GET_MODE (op
));
1467 /* We know this operand is an address, so we want it to be
1468 allocated to a register that can be the base of an
1469 address, ie BASE_REG_CLASS. */
1471 = reg_class_subunion
[(int) classes
[i
]]
1472 [(int) BASE_REG_CLASS
];
1475 case 'm': case 'o': case 'V':
1476 /* It doesn't seem worth distinguishing between offsettable
1477 and non-offsettable addresses here. */
1479 if (GET_CODE (op
) == MEM
)
1484 if (GET_CODE (op
) == MEM
1485 && (GET_CODE (XEXP (op
, 0)) == PRE_DEC
1486 || GET_CODE (XEXP (op
, 0)) == POST_DEC
))
1491 if (GET_CODE (op
) == MEM
1492 && (GET_CODE (XEXP (op
, 0)) == PRE_INC
1493 || GET_CODE (XEXP (op
, 0)) == POST_INC
))
1498 #ifndef REAL_ARITHMETIC
1499 /* Match any floating double constant, but only if
1500 we can examine the bits of it reliably. */
1501 if ((HOST_FLOAT_FORMAT
!= TARGET_FLOAT_FORMAT
1502 || HOST_BITS_PER_WIDE_INT
!= BITS_PER_WORD
)
1503 && GET_MODE (op
) != VOIDmode
&& ! flag_pretend_float
)
1506 if (GET_CODE (op
) == CONST_DOUBLE
)
1511 if (GET_CODE (op
) == CONST_DOUBLE
)
1517 if (GET_CODE (op
) == CONST_DOUBLE
1518 && CONST_DOUBLE_OK_FOR_LETTER_P (op
, c
))
1523 if (GET_CODE (op
) == CONST_INT
1524 || (GET_CODE (op
) == CONST_DOUBLE
1525 && GET_MODE (op
) == VOIDmode
))
1529 #ifdef LEGITIMATE_PIC_OPERAND_P
1530 && (! flag_pic
|| LEGITIMATE_PIC_OPERAND_P (op
))
1537 if (GET_CODE (op
) == CONST_INT
1538 || (GET_CODE (op
) == CONST_DOUBLE
1539 && GET_MODE (op
) == VOIDmode
))
1551 if (GET_CODE (op
) == CONST_INT
1552 && CONST_OK_FOR_LETTER_P (INTVAL (op
), c
))
1560 #ifdef EXTRA_CONSTRAINT
1566 if (EXTRA_CONSTRAINT (op
, c
))
1572 if (GET_CODE (op
) == MEM
1574 #ifdef LEGITIMATE_PIC_OPERAND_P
1575 && (! flag_pic
|| LEGITIMATE_PIC_OPERAND_P (op
))
1582 = reg_class_subunion
[(int) classes
[i
]][(int) GENERAL_REGS
];
1587 = reg_class_subunion
[(int) classes
[i
]]
1588 [(int) REG_CLASS_FROM_LETTER (c
)];
1593 /* How we account for this operand now depends on whether it is a
1594 pseudo register or not. If it is, we first check if any
1595 register classes are valid. If not, we ignore this alternative,
1596 since we want to assume that all pseudos get allocated for
1597 register preferencing. If some register class is valid, compute
1598 the costs of moving the pseudo into that class. */
1600 if (GET_CODE (op
) == REG
&& REGNO (op
) >= FIRST_PSEUDO_REGISTER
)
1602 if (classes
[i
] == NO_REGS
)
1604 /* We must always fail if the operand is a REG, but
1605 we did not find a suitable class.
1607 Otherwise we may perform an uninitialized read
1608 from this_op_costs after the `continue' statement
1614 struct costs
*pp
= &this_op_costs
[i
];
1616 for (class = 0; class < N_REG_CLASSES
; class++)
1618 = ((recog_data
.operand_type
[i
] != OP_OUT
1619 ? may_move_in_cost
[class][(int) classes
[i
]]
1621 + (recog_data
.operand_type
[i
] != OP_IN
1622 ? may_move_out_cost
[(int) classes
[i
]][class]
1625 /* If the alternative actually allows memory, make things
1626 a bit cheaper since we won't need an extra insn to
1630 = ((recog_data
.operand_type
[i
] != OP_IN
1631 ? MEMORY_MOVE_COST (mode
, classes
[i
], 0)
1633 + (recog_data
.operand_type
[i
] != OP_OUT
1634 ? MEMORY_MOVE_COST (mode
, classes
[i
], 1)
1635 : 0) - allows_mem
[i
]);
1637 /* If we have assigned a class to this register in our
1638 first pass, add a cost to this alternative corresponding
1639 to what we would add if this register were not in the
1640 appropriate class. */
1644 += (may_move_in_cost
[(unsigned char) reg_pref
[REGNO (op
)].prefclass
]
1645 [(int) classes
[i
]]);
1649 /* Otherwise, if this alternative wins, either because we
1650 have already determined that or if we have a hard register of
1651 the proper class, there is no cost for this alternative. */
1654 || (GET_CODE (op
) == REG
1655 && reg_fits_class_p (op
, classes
[i
], 0, GET_MODE (op
))))
1658 /* If registers are valid, the cost of this alternative includes
1659 copying the object to and/or from a register. */
1661 else if (classes
[i
] != NO_REGS
)
1663 if (recog_data
.operand_type
[i
] != OP_OUT
)
1664 alt_cost
+= copy_cost (op
, mode
, classes
[i
], 1);
1666 if (recog_data
.operand_type
[i
] != OP_IN
)
1667 alt_cost
+= copy_cost (op
, mode
, classes
[i
], 0);
1670 /* The only other way this alternative can be used is if this is a
1671 constant that could be placed into memory. */
1673 else if (CONSTANT_P (op
) && (allows_addr
|| allows_mem
[i
]))
1674 alt_cost
+= MEMORY_MOVE_COST (mode
, classes
[i
], 1);
1682 /* Finally, update the costs with the information we've calculated
1683 about this alternative. */
1685 for (i
= 0; i
< n_ops
; i
++)
1686 if (GET_CODE (ops
[i
]) == REG
1687 && REGNO (ops
[i
]) >= FIRST_PSEUDO_REGISTER
)
1689 struct costs
*pp
= &op_costs
[i
], *qq
= &this_op_costs
[i
];
1690 int scale
= 1 + (recog_data
.operand_type
[i
] == OP_INOUT
);
1692 pp
->mem_cost
= MIN (pp
->mem_cost
,
1693 (qq
->mem_cost
+ alt_cost
) * scale
);
1695 for (class = 0; class < N_REG_CLASSES
; class++)
1696 pp
->cost
[class] = MIN (pp
->cost
[class],
1697 (qq
->cost
[class] + alt_cost
) * scale
);
1701 /* If this insn is a single set copying operand 1 to operand 0
1702 and one operand is a pseudo with the other a hard reg or a pseudo
1703 that prefers a register that is in its own register class then
1704 we may want to adjust the cost of that register class to -1.
1706 Avoid the adjustment if the source does not die to avoid stressing of
1707 register allocator by preferrencing two coliding registers into single
1710 Also avoid the adjustment if a copy between registers of the class
1711 is expensive (ten times the cost of a default copy is considered
1712 arbitrarily expensive). This avoids losing when the preferred class
1713 is very expensive as the source of a copy instruction. */
1715 if ((set
= single_set (insn
)) != 0
1716 && ops
[0] == SET_DEST (set
) && ops
[1] == SET_SRC (set
)
1717 && GET_CODE (ops
[0]) == REG
&& GET_CODE (ops
[1]) == REG
1718 && find_regno_note (insn
, REG_DEAD
, REGNO (ops
[1])))
1719 for (i
= 0; i
<= 1; i
++)
1720 if (REGNO (ops
[i
]) >= FIRST_PSEUDO_REGISTER
)
1722 unsigned int regno
= REGNO (ops
[!i
]);
1723 enum machine_mode mode
= GET_MODE (ops
[!i
]);
1727 if (regno
>= FIRST_PSEUDO_REGISTER
&& reg_pref
!= 0)
1729 enum reg_class pref
= reg_pref
[regno
].prefclass
;
1731 if ((reg_class_size
[(unsigned char) pref
]
1732 == CLASS_MAX_NREGS (pref
, mode
))
1733 && REGISTER_MOVE_COST (pref
, pref
) < 10 * 2)
1734 op_costs
[i
].cost
[(unsigned char) pref
] = -1;
1736 else if (regno
< FIRST_PSEUDO_REGISTER
)
1737 for (class = 0; class < N_REG_CLASSES
; class++)
1738 if (TEST_HARD_REG_BIT (reg_class_contents
[class], regno
)
1739 && reg_class_size
[class] == CLASS_MAX_NREGS (class, mode
))
1741 if (reg_class_size
[class] == 1)
1742 op_costs
[i
].cost
[class] = -1;
1745 for (nr
= 0; nr
< HARD_REGNO_NREGS (regno
, mode
); nr
++)
1747 if (! TEST_HARD_REG_BIT (reg_class_contents
[class],
1752 if (nr
== HARD_REGNO_NREGS (regno
,mode
))
1753 op_costs
[i
].cost
[class] = -1;
1759 /* Compute the cost of loading X into (if TO_P is non-zero) or from (if
1760 TO_P is zero) a register of class CLASS in mode MODE.
1762 X must not be a pseudo. */
1765 copy_cost (x
, mode
, class, to_p
)
1767 enum machine_mode mode ATTRIBUTE_UNUSED
;
1768 enum reg_class
class;
1769 int to_p ATTRIBUTE_UNUSED
;
1771 #ifdef HAVE_SECONDARY_RELOADS
1772 enum reg_class secondary_class
= NO_REGS
;
1775 /* If X is a SCRATCH, there is actually nothing to move since we are
1776 assuming optimal allocation. */
1778 if (GET_CODE (x
) == SCRATCH
)
1781 /* Get the class we will actually use for a reload. */
1782 class = PREFERRED_RELOAD_CLASS (x
, class);
1784 #ifdef HAVE_SECONDARY_RELOADS
1785 /* If we need a secondary reload (we assume here that we are using
1786 the secondary reload as an intermediate, not a scratch register), the
1787 cost is that to load the input into the intermediate register, then
1788 to copy them. We use a special value of TO_P to avoid recursion. */
1790 #ifdef SECONDARY_INPUT_RELOAD_CLASS
1792 secondary_class
= SECONDARY_INPUT_RELOAD_CLASS (class, mode
, x
);
1795 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
1797 secondary_class
= SECONDARY_OUTPUT_RELOAD_CLASS (class, mode
, x
);
1800 if (secondary_class
!= NO_REGS
)
1801 return (move_cost
[(int) secondary_class
][(int) class]
1802 + copy_cost (x
, mode
, secondary_class
, 2));
1803 #endif /* HAVE_SECONDARY_RELOADS */
1805 /* For memory, use the memory move cost, for (hard) registers, use the
1806 cost to move between the register classes, and use 2 for everything
1807 else (constants). */
1809 if (GET_CODE (x
) == MEM
|| class == NO_REGS
)
1810 return MEMORY_MOVE_COST (mode
, class, to_p
);
1812 else if (GET_CODE (x
) == REG
)
1813 return move_cost
[(int) REGNO_REG_CLASS (REGNO (x
))][(int) class];
1816 /* If this is a constant, we may eventually want to call rtx_cost here. */
1820 /* Record the pseudo registers we must reload into hard registers
1821 in a subexpression of a memory address, X.
1823 CLASS is the class that the register needs to be in and is either
1824 BASE_REG_CLASS or INDEX_REG_CLASS.
1826 SCALE is twice the amount to multiply the cost by (it is twice so we
1827 can represent half-cost adjustments). */
1830 record_address_regs (x
, class, scale
)
1832 enum reg_class
class;
1835 register enum rtx_code code
= GET_CODE (x
);
1848 /* When we have an address that is a sum,
1849 we must determine whether registers are "base" or "index" regs.
1850 If there is a sum of two registers, we must choose one to be
1851 the "base". Luckily, we can use the REGNO_POINTER_FLAG
1852 to make a good choice most of the time. We only need to do this
1853 on machines that can have two registers in an address and where
1854 the base and index register classes are different.
1856 ??? This code used to set REGNO_POINTER_FLAG in some cases, but
1857 that seems bogus since it should only be set when we are sure
1858 the register is being used as a pointer. */
1861 rtx arg0
= XEXP (x
, 0);
1862 rtx arg1
= XEXP (x
, 1);
1863 register enum rtx_code code0
= GET_CODE (arg0
);
1864 register enum rtx_code code1
= GET_CODE (arg1
);
1866 /* Look inside subregs. */
1867 if (code0
== SUBREG
)
1868 arg0
= SUBREG_REG (arg0
), code0
= GET_CODE (arg0
);
1869 if (code1
== SUBREG
)
1870 arg1
= SUBREG_REG (arg1
), code1
= GET_CODE (arg1
);
1872 /* If this machine only allows one register per address, it must
1873 be in the first operand. */
1875 if (MAX_REGS_PER_ADDRESS
== 1)
1876 record_address_regs (arg0
, class, scale
);
1878 /* If index and base registers are the same on this machine, just
1879 record registers in any non-constant operands. We assume here,
1880 as well as in the tests below, that all addresses are in
1883 else if (INDEX_REG_CLASS
== BASE_REG_CLASS
)
1885 record_address_regs (arg0
, class, scale
);
1886 if (! CONSTANT_P (arg1
))
1887 record_address_regs (arg1
, class, scale
);
1890 /* If the second operand is a constant integer, it doesn't change
1891 what class the first operand must be. */
1893 else if (code1
== CONST_INT
|| code1
== CONST_DOUBLE
)
1894 record_address_regs (arg0
, class, scale
);
1896 /* If the second operand is a symbolic constant, the first operand
1897 must be an index register. */
1899 else if (code1
== SYMBOL_REF
|| code1
== CONST
|| code1
== LABEL_REF
)
1900 record_address_regs (arg0
, INDEX_REG_CLASS
, scale
);
1902 /* If both operands are registers but one is already a hard register
1903 of index or base class, give the other the class that the hard
1906 #ifdef REG_OK_FOR_BASE_P
1907 else if (code0
== REG
&& code1
== REG
1908 && REGNO (arg0
) < FIRST_PSEUDO_REGISTER
1909 && (REG_OK_FOR_BASE_P (arg0
) || REG_OK_FOR_INDEX_P (arg0
)))
1910 record_address_regs (arg1
,
1911 REG_OK_FOR_BASE_P (arg0
)
1912 ? INDEX_REG_CLASS
: BASE_REG_CLASS
,
1914 else if (code0
== REG
&& code1
== REG
1915 && REGNO (arg1
) < FIRST_PSEUDO_REGISTER
1916 && (REG_OK_FOR_BASE_P (arg1
) || REG_OK_FOR_INDEX_P (arg1
)))
1917 record_address_regs (arg0
,
1918 REG_OK_FOR_BASE_P (arg1
)
1919 ? INDEX_REG_CLASS
: BASE_REG_CLASS
,
1923 /* If one operand is known to be a pointer, it must be the base
1924 with the other operand the index. Likewise if the other operand
1927 else if ((code0
== REG
&& REGNO_POINTER_FLAG (REGNO (arg0
)))
1930 record_address_regs (arg0
, BASE_REG_CLASS
, scale
);
1931 record_address_regs (arg1
, INDEX_REG_CLASS
, scale
);
1933 else if ((code1
== REG
&& REGNO_POINTER_FLAG (REGNO (arg1
)))
1936 record_address_regs (arg0
, INDEX_REG_CLASS
, scale
);
1937 record_address_regs (arg1
, BASE_REG_CLASS
, scale
);
1940 /* Otherwise, count equal chances that each might be a base
1941 or index register. This case should be rare. */
1945 record_address_regs (arg0
, BASE_REG_CLASS
, scale
/ 2);
1946 record_address_regs (arg0
, INDEX_REG_CLASS
, scale
/ 2);
1947 record_address_regs (arg1
, BASE_REG_CLASS
, scale
/ 2);
1948 record_address_regs (arg1
, INDEX_REG_CLASS
, scale
/ 2);
1957 /* Double the importance of a pseudo register that is incremented
1958 or decremented, since it would take two extra insns
1959 if it ends up in the wrong place. If the operand is a pseudo,
1960 show it is being used in an INC_DEC context. */
1962 #ifdef FORBIDDEN_INC_DEC_CLASSES
1963 if (GET_CODE (XEXP (x
, 0)) == REG
1964 && REGNO (XEXP (x
, 0)) >= FIRST_PSEUDO_REGISTER
)
1965 in_inc_dec
[REGNO (XEXP (x
, 0))] = 1;
1968 record_address_regs (XEXP (x
, 0), class, 2 * scale
);
1973 register struct costs
*pp
= &costs
[REGNO (x
)];
1976 pp
->mem_cost
+= (MEMORY_MOVE_COST (Pmode
, class, 1) * scale
) / 2;
1978 for (i
= 0; i
< N_REG_CLASSES
; i
++)
1979 pp
->cost
[i
] += (may_move_in_cost
[i
][(int) class] * scale
) / 2;
1985 register const char *fmt
= GET_RTX_FORMAT (code
);
1987 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
1989 record_address_regs (XEXP (x
, i
), class, scale
);
1994 #ifdef FORBIDDEN_INC_DEC_CLASSES
1996 /* Return 1 if REG is valid as an auto-increment memory reference
1997 to an object of MODE. */
2000 auto_inc_dec_reg_p (reg
, mode
)
2002 enum machine_mode mode
;
2004 if (HAVE_POST_INCREMENT
2005 && memory_address_p (mode
, gen_rtx_POST_INC (Pmode
, reg
)))
2008 if (HAVE_POST_DECREMENT
2009 && memory_address_p (mode
, gen_rtx_POST_DEC (Pmode
, reg
)))
2012 if (HAVE_PRE_INCREMENT
2013 && memory_address_p (mode
, gen_rtx_PRE_INC (Pmode
, reg
)))
2016 if (HAVE_PRE_DECREMENT
2017 && memory_address_p (mode
, gen_rtx_PRE_DEC (Pmode
, reg
)))
2024 static short *renumber
;
2025 static size_t regno_allocated
;
2026 static unsigned int reg_n_max
;
2028 /* Allocate enough space to hold NUM_REGS registers for the tables used for
2029 reg_scan and flow_analysis that are indexed by the register number. If
2030 NEW_P is non zero, initialize all of the registers, otherwise only
2031 initialize the new registers allocated. The same table is kept from
2032 function to function, only reallocating it when we need more room. If
2033 RENUMBER_P is non zero, allocate the reg_renumber array also. */
2036 allocate_reg_info (num_regs
, new_p
, renumber_p
)
2042 size_t size_renumber
;
2043 size_t min
= (new_p
) ? 0 : reg_n_max
;
2044 struct reg_info_data
*reg_data
;
2046 if (num_regs
> regno_allocated
)
2048 size_t old_allocated
= regno_allocated
;
2050 regno_allocated
= num_regs
+ (num_regs
/ 20); /* add some slop space */
2051 size_renumber
= regno_allocated
* sizeof (short);
2055 VARRAY_REG_INIT (reg_n_info
, regno_allocated
, "reg_n_info");
2056 renumber
= (short *) xmalloc (size_renumber
);
2057 reg_pref_buffer
= (struct reg_pref
*) xmalloc (regno_allocated
2058 * sizeof (struct reg_pref
));
2063 VARRAY_GROW (reg_n_info
, regno_allocated
);
2065 if (new_p
) /* if we're zapping everything, no need to realloc */
2067 free ((char *)renumber
);
2068 free ((char *)reg_pref
);
2069 renumber
= (short *) xmalloc (size_renumber
);
2070 reg_pref_buffer
= (struct reg_pref
*) xmalloc (regno_allocated
2071 * sizeof (struct reg_pref
));
2076 renumber
= (short *) xrealloc ((char *)renumber
, size_renumber
);
2077 reg_pref_buffer
= (struct reg_pref
*) xrealloc ((char *)reg_pref_buffer
,
2079 * sizeof (struct reg_pref
));
2083 size_info
= (regno_allocated
- old_allocated
) * sizeof (reg_info
)
2084 + sizeof (struct reg_info_data
) - sizeof (reg_info
);
2085 reg_data
= (struct reg_info_data
*) xcalloc (size_info
, 1);
2086 reg_data
->min_index
= old_allocated
;
2087 reg_data
->max_index
= regno_allocated
- 1;
2088 reg_data
->next
= reg_info_head
;
2089 reg_info_head
= reg_data
;
2092 reg_n_max
= num_regs
;
2095 /* Loop through each of the segments allocated for the actual
2096 reg_info pages, and set up the pointers, zero the pages, etc. */
2097 for (reg_data
= reg_info_head
;
2098 reg_data
&& reg_data
->max_index
>= min
;
2099 reg_data
= reg_data
->next
)
2101 size_t min_index
= reg_data
->min_index
;
2102 size_t max_index
= reg_data
->max_index
;
2103 size_t max
= MIN (max_index
, num_regs
);
2104 size_t local_min
= min
- min_index
;
2107 if (reg_data
->min_index
> num_regs
)
2110 if (min
< min_index
)
2112 if (!reg_data
->used_p
) /* page just allocated with calloc */
2113 reg_data
->used_p
= 1; /* no need to zero */
2115 bzero ((char *) ®_data
->data
[local_min
],
2116 sizeof (reg_info
) * (max
- min_index
- local_min
+ 1));
2118 for (i
= min_index
+local_min
; i
<= max
; i
++)
2120 VARRAY_REG (reg_n_info
, i
) = ®_data
->data
[i
-min_index
];
2121 REG_BASIC_BLOCK (i
) = REG_BLOCK_UNKNOWN
;
2123 reg_pref_buffer
[i
].prefclass
= (char) NO_REGS
;
2124 reg_pref_buffer
[i
].altclass
= (char) NO_REGS
;
2129 /* If {pref,alt}class have already been allocated, update the pointers to
2130 the newly realloced ones. */
2132 reg_pref
= reg_pref_buffer
;
2135 reg_renumber
= renumber
;
2137 /* Tell the regset code about the new number of registers */
2138 MAX_REGNO_REG_SET (num_regs
, new_p
, renumber_p
);
2141 /* Free up the space allocated by allocate_reg_info. */
2147 struct reg_info_data
*reg_data
;
2148 struct reg_info_data
*reg_next
;
2150 VARRAY_FREE (reg_n_info
);
2151 for (reg_data
= reg_info_head
; reg_data
; reg_data
= reg_next
)
2153 reg_next
= reg_data
->next
;
2154 free ((char *)reg_data
);
2157 free (reg_pref_buffer
);
2158 reg_pref_buffer
= (struct reg_pref
*)0;
2159 reg_info_head
= (struct reg_info_data
*)0;
2160 renumber
= (short *)0;
2162 regno_allocated
= 0;
2166 /* This is the `regscan' pass of the compiler, run just before cse
2167 and again just before loop.
2169 It finds the first and last use of each pseudo-register
2170 and records them in the vectors regno_first_uid, regno_last_uid
2171 and counts the number of sets in the vector reg_n_sets.
2173 REPEAT is nonzero the second time this is called. */
2175 /* Maximum number of parallel sets and clobbers in any insn in this fn.
2176 Always at least 3, since the combiner could put that many together
2177 and we want this to remain correct for all the remaining passes. */
2182 reg_scan (f
, nregs
, repeat
)
2185 int repeat ATTRIBUTE_UNUSED
;
2189 allocate_reg_info (nregs
, TRUE
, FALSE
);
2192 for (insn
= f
; insn
; insn
= NEXT_INSN (insn
))
2193 if (GET_CODE (insn
) == INSN
2194 || GET_CODE (insn
) == CALL_INSN
2195 || GET_CODE (insn
) == JUMP_INSN
)
2197 if (GET_CODE (PATTERN (insn
)) == PARALLEL
2198 && XVECLEN (PATTERN (insn
), 0) > max_parallel
)
2199 max_parallel
= XVECLEN (PATTERN (insn
), 0);
2200 reg_scan_mark_refs (PATTERN (insn
), insn
, 0, 0);
2202 if (REG_NOTES (insn
))
2203 reg_scan_mark_refs (REG_NOTES (insn
), insn
, 1, 0);
2207 /* Update 'regscan' information by looking at the insns
2208 from FIRST to LAST. Some new REGs have been created,
2209 and any REG with number greater than OLD_MAX_REGNO is
2210 such a REG. We only update information for those. */
2213 reg_scan_update (first
, last
, old_max_regno
)
2216 unsigned int old_max_regno
;
2220 allocate_reg_info (max_reg_num (), FALSE
, FALSE
);
2222 for (insn
= first
; insn
!= last
; insn
= NEXT_INSN (insn
))
2223 if (GET_CODE (insn
) == INSN
2224 || GET_CODE (insn
) == CALL_INSN
2225 || GET_CODE (insn
) == JUMP_INSN
)
2227 if (GET_CODE (PATTERN (insn
)) == PARALLEL
2228 && XVECLEN (PATTERN (insn
), 0) > max_parallel
)
2229 max_parallel
= XVECLEN (PATTERN (insn
), 0);
2230 reg_scan_mark_refs (PATTERN (insn
), insn
, 0, old_max_regno
);
2232 if (REG_NOTES (insn
))
2233 reg_scan_mark_refs (REG_NOTES (insn
), insn
, 1, old_max_regno
);
2237 /* X is the expression to scan. INSN is the insn it appears in.
2238 NOTE_FLAG is nonzero if X is from INSN's notes rather than its body.
2239 We should only record information for REGs with numbers
2240 greater than or equal to MIN_REGNO. */
2243 reg_scan_mark_refs (x
, insn
, note_flag
, min_regno
)
2247 unsigned int min_regno
;
2249 register enum rtx_code code
;
2253 code
= GET_CODE (x
);
2269 unsigned int regno
= REGNO (x
);
2271 if (regno
>= min_regno
)
2273 REGNO_LAST_NOTE_UID (regno
) = INSN_UID (insn
);
2275 REGNO_LAST_UID (regno
) = INSN_UID (insn
);
2276 if (REGNO_FIRST_UID (regno
) == 0)
2277 REGNO_FIRST_UID (regno
) = INSN_UID (insn
);
2284 reg_scan_mark_refs (XEXP (x
, 0), insn
, note_flag
, min_regno
);
2286 reg_scan_mark_refs (XEXP (x
, 1), insn
, note_flag
, min_regno
);
2291 reg_scan_mark_refs (XEXP (x
, 1), insn
, note_flag
, min_regno
);
2295 /* Count a set of the destination if it is a register. */
2296 for (dest
= SET_DEST (x
);
2297 GET_CODE (dest
) == SUBREG
|| GET_CODE (dest
) == STRICT_LOW_PART
2298 || GET_CODE (dest
) == ZERO_EXTEND
;
2299 dest
= XEXP (dest
, 0))
2302 if (GET_CODE (dest
) == REG
2303 && REGNO (dest
) >= min_regno
)
2304 REG_N_SETS (REGNO (dest
))++;
2306 /* If this is setting a pseudo from another pseudo or the sum of a
2307 pseudo and a constant integer and the other pseudo is known to be
2308 a pointer, set the destination to be a pointer as well.
2310 Likewise if it is setting the destination from an address or from a
2311 value equivalent to an address or to the sum of an address and
2314 But don't do any of this if the pseudo corresponds to a user
2315 variable since it should have already been set as a pointer based
2318 if (GET_CODE (SET_DEST (x
)) == REG
2319 && REGNO (SET_DEST (x
)) >= FIRST_PSEUDO_REGISTER
2320 && REGNO (SET_DEST (x
)) >= min_regno
2321 /* If the destination pseudo is set more than once, then other
2322 sets might not be to a pointer value (consider access to a
2323 union in two threads of control in the presense of global
2324 optimizations). So only set REGNO_POINTER_FLAG on the destination
2325 pseudo if this is the only set of that pseudo. */
2326 && REG_N_SETS (REGNO (SET_DEST (x
))) == 1
2327 && ! REG_USERVAR_P (SET_DEST (x
))
2328 && ! REGNO_POINTER_FLAG (REGNO (SET_DEST (x
)))
2329 && ((GET_CODE (SET_SRC (x
)) == REG
2330 && REGNO_POINTER_FLAG (REGNO (SET_SRC (x
))))
2331 || ((GET_CODE (SET_SRC (x
)) == PLUS
2332 || GET_CODE (SET_SRC (x
)) == LO_SUM
)
2333 && GET_CODE (XEXP (SET_SRC (x
), 1)) == CONST_INT
2334 && GET_CODE (XEXP (SET_SRC (x
), 0)) == REG
2335 && REGNO_POINTER_FLAG (REGNO (XEXP (SET_SRC (x
), 0))))
2336 || GET_CODE (SET_SRC (x
)) == CONST
2337 || GET_CODE (SET_SRC (x
)) == SYMBOL_REF
2338 || GET_CODE (SET_SRC (x
)) == LABEL_REF
2339 || (GET_CODE (SET_SRC (x
)) == HIGH
2340 && (GET_CODE (XEXP (SET_SRC (x
), 0)) == CONST
2341 || GET_CODE (XEXP (SET_SRC (x
), 0)) == SYMBOL_REF
2342 || GET_CODE (XEXP (SET_SRC (x
), 0)) == LABEL_REF
))
2343 || ((GET_CODE (SET_SRC (x
)) == PLUS
2344 || GET_CODE (SET_SRC (x
)) == LO_SUM
)
2345 && (GET_CODE (XEXP (SET_SRC (x
), 1)) == CONST
2346 || GET_CODE (XEXP (SET_SRC (x
), 1)) == SYMBOL_REF
2347 || GET_CODE (XEXP (SET_SRC (x
), 1)) == LABEL_REF
))
2348 || ((note
= find_reg_note (insn
, REG_EQUAL
, 0)) != 0
2349 && (GET_CODE (XEXP (note
, 0)) == CONST
2350 || GET_CODE (XEXP (note
, 0)) == SYMBOL_REF
2351 || GET_CODE (XEXP (note
, 0)) == LABEL_REF
))))
2352 REGNO_POINTER_FLAG (REGNO (SET_DEST (x
))) = 1;
2354 /* ... fall through ... */
2358 register const char *fmt
= GET_RTX_FORMAT (code
);
2360 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
2363 reg_scan_mark_refs (XEXP (x
, i
), insn
, note_flag
, min_regno
);
2364 else if (fmt
[i
] == 'E' && XVEC (x
, i
) != 0)
2367 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
2368 reg_scan_mark_refs (XVECEXP (x
, i
, j
), insn
, note_flag
, min_regno
);
2375 /* Return nonzero if C1 is a subset of C2, i.e., if every register in C1
2379 reg_class_subset_p (c1
, c2
)
2380 register enum reg_class c1
;
2381 register enum reg_class c2
;
2383 if (c1
== c2
) return 1;
2388 GO_IF_HARD_REG_SUBSET (reg_class_contents
[(int)c1
],
2389 reg_class_contents
[(int)c2
],
2394 /* Return nonzero if there is a register that is in both C1 and C2. */
2397 reg_classes_intersect_p (c1
, c2
)
2398 register enum reg_class c1
;
2399 register enum reg_class c2
;
2406 if (c1
== c2
) return 1;
2408 if (c1
== ALL_REGS
|| c2
== ALL_REGS
)
2411 COPY_HARD_REG_SET (c
, reg_class_contents
[(int) c1
]);
2412 AND_HARD_REG_SET (c
, reg_class_contents
[(int) c2
]);
2414 GO_IF_HARD_REG_SUBSET (c
, reg_class_contents
[(int) NO_REGS
], lose
);
2421 /* Release any memory allocated by register sets. */
2424 regset_release_memory ()
2426 bitmap_release_memory ();