1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001 Free Software Foundation, Inc.
5 This file is part of GNU CC.
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
26 #include "hard-reg-set.h"
30 #include "insn-config.h"
36 #include "basic-block.h"
45 /* This file contains the reload pass of the compiler, which is
46 run after register allocation has been done. It checks that
47 each insn is valid (operands required to be in registers really
48 are in registers of the proper class) and fixes up invalid ones
49 by copying values temporarily into registers for the insns
52 The results of register allocation are described by the vector
53 reg_renumber; the insns still contain pseudo regs, but reg_renumber
54 can be used to find which hard reg, if any, a pseudo reg is in.
56 The technique we always use is to free up a few hard regs that are
57 called ``reload regs'', and for each place where a pseudo reg
58 must be in a hard reg, copy it temporarily into one of the reload regs.
60 Reload regs are allocated locally for every instruction that needs
61 reloads. When there are pseudos which are allocated to a register that
62 has been chosen as a reload reg, such pseudos must be ``spilled''.
63 This means that they go to other hard regs, or to stack slots if no other
64 available hard regs can be found. Spilling can invalidate more
65 insns, requiring additional need for reloads, so we must keep checking
66 until the process stabilizes.
68 For machines with different classes of registers, we must keep track
69 of the register class needed for each reload, and make sure that
70 we allocate enough reload registers of each class.
72 The file reload.c contains the code that checks one insn for
73 validity and reports the reloads that it needs. This file
74 is in charge of scanning the entire rtl code, accumulating the
75 reload needs, spilling, assigning reload registers to use for
76 fixing up each insn, and generating the new insns to copy values
77 into the reload registers. */
79 #ifndef REGISTER_MOVE_COST
80 #define REGISTER_MOVE_COST(m, x, y) 2
84 #define LOCAL_REGNO(REGNO) 0
87 /* During reload_as_needed, element N contains a REG rtx for the hard reg
88 into which reg N has been reloaded (perhaps for a previous insn). */
89 static rtx
*reg_last_reload_reg
;
91 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
92 for an output reload that stores into reg N. */
93 static char *reg_has_output_reload
;
95 /* Indicates which hard regs are reload-registers for an output reload
96 in the current insn. */
97 static HARD_REG_SET reg_is_output_reload
;
99 /* Element N is the constant value to which pseudo reg N is equivalent,
100 or zero if pseudo reg N is not equivalent to a constant.
101 find_reloads looks at this in order to replace pseudo reg N
102 with the constant it stands for. */
103 rtx
*reg_equiv_constant
;
105 /* Element N is a memory location to which pseudo reg N is equivalent,
106 prior to any register elimination (such as frame pointer to stack
107 pointer). Depending on whether or not it is a valid address, this value
108 is transferred to either reg_equiv_address or reg_equiv_mem. */
109 rtx
*reg_equiv_memory_loc
;
111 /* Element N is the address of stack slot to which pseudo reg N is equivalent.
112 This is used when the address is not valid as a memory address
113 (because its displacement is too big for the machine.) */
114 rtx
*reg_equiv_address
;
116 /* Element N is the memory slot to which pseudo reg N is equivalent,
117 or zero if pseudo reg N is not equivalent to a memory slot. */
120 /* Widest width in which each pseudo reg is referred to (via subreg). */
121 static unsigned int *reg_max_ref_width
;
123 /* Element N is the list of insns that initialized reg N from its equivalent
124 constant or memory slot. */
125 static rtx
*reg_equiv_init
;
127 /* Vector to remember old contents of reg_renumber before spilling. */
128 static short *reg_old_renumber
;
130 /* During reload_as_needed, element N contains the last pseudo regno reloaded
131 into hard register N. If that pseudo reg occupied more than one register,
132 reg_reloaded_contents points to that pseudo for each spill register in
133 use; all of these must remain set for an inheritance to occur. */
134 static int reg_reloaded_contents
[FIRST_PSEUDO_REGISTER
];
136 /* During reload_as_needed, element N contains the insn for which
137 hard register N was last used. Its contents are significant only
138 when reg_reloaded_valid is set for this register. */
139 static rtx reg_reloaded_insn
[FIRST_PSEUDO_REGISTER
];
141 /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid */
142 static HARD_REG_SET reg_reloaded_valid
;
143 /* Indicate if the register was dead at the end of the reload.
144 This is only valid if reg_reloaded_contents is set and valid. */
145 static HARD_REG_SET reg_reloaded_dead
;
147 /* Number of spill-regs so far; number of valid elements of spill_regs. */
150 /* In parallel with spill_regs, contains REG rtx's for those regs.
151 Holds the last rtx used for any given reg, or 0 if it has never
152 been used for spilling yet. This rtx is reused, provided it has
154 static rtx spill_reg_rtx
[FIRST_PSEUDO_REGISTER
];
156 /* In parallel with spill_regs, contains nonzero for a spill reg
157 that was stored after the last time it was used.
158 The precise value is the insn generated to do the store. */
159 static rtx spill_reg_store
[FIRST_PSEUDO_REGISTER
];
161 /* This is the register that was stored with spill_reg_store. This is a
162 copy of reload_out / reload_out_reg when the value was stored; if
163 reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */
164 static rtx spill_reg_stored_to
[FIRST_PSEUDO_REGISTER
];
166 /* This table is the inverse mapping of spill_regs:
167 indexed by hard reg number,
168 it contains the position of that reg in spill_regs,
169 or -1 for something that is not in spill_regs.
171 ?!? This is no longer accurate. */
172 static short spill_reg_order
[FIRST_PSEUDO_REGISTER
];
174 /* This reg set indicates registers that can't be used as spill registers for
175 the currently processed insn. These are the hard registers which are live
176 during the insn, but not allocated to pseudos, as well as fixed
178 static HARD_REG_SET bad_spill_regs
;
180 /* These are the hard registers that can't be used as spill register for any
181 insn. This includes registers used for user variables and registers that
182 we can't eliminate. A register that appears in this set also can't be used
183 to retry register allocation. */
184 static HARD_REG_SET bad_spill_regs_global
;
186 /* Describes order of use of registers for reloading
187 of spilled pseudo-registers. `n_spills' is the number of
188 elements that are actually valid; new ones are added at the end.
190 Both spill_regs and spill_reg_order are used on two occasions:
191 once during find_reload_regs, where they keep track of the spill registers
192 for a single insn, but also during reload_as_needed where they show all
193 the registers ever used by reload. For the latter case, the information
194 is calculated during finish_spills. */
195 static short spill_regs
[FIRST_PSEUDO_REGISTER
];
197 /* This vector of reg sets indicates, for each pseudo, which hard registers
198 may not be used for retrying global allocation because the register was
199 formerly spilled from one of them. If we allowed reallocating a pseudo to
200 a register that it was already allocated to, reload might not
202 static HARD_REG_SET
*pseudo_previous_regs
;
204 /* This vector of reg sets indicates, for each pseudo, which hard
205 registers may not be used for retrying global allocation because they
206 are used as spill registers during one of the insns in which the
208 static HARD_REG_SET
*pseudo_forbidden_regs
;
210 /* All hard regs that have been used as spill registers for any insn are
211 marked in this set. */
212 static HARD_REG_SET used_spill_regs
;
214 /* Index of last register assigned as a spill register. We allocate in
215 a round-robin fashion. */
216 static int last_spill_reg
;
218 /* Nonzero if indirect addressing is supported on the machine; this means
219 that spilling (REG n) does not require reloading it into a register in
220 order to do (MEM (REG n)) or (MEM (PLUS (REG n) (CONST_INT c))). The
221 value indicates the level of indirect addressing supported, e.g., two
222 means that (MEM (MEM (REG n))) is also valid if (REG n) does not get
224 static char spill_indirect_levels
;
226 /* Nonzero if indirect addressing is supported when the innermost MEM is
227 of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to
228 which these are valid is the same as spill_indirect_levels, above. */
229 char indirect_symref_ok
;
231 /* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */
232 char double_reg_address_ok
;
234 /* Record the stack slot for each spilled hard register. */
235 static rtx spill_stack_slot
[FIRST_PSEUDO_REGISTER
];
237 /* Width allocated so far for that stack slot. */
238 static unsigned int spill_stack_slot_width
[FIRST_PSEUDO_REGISTER
];
240 /* Record which pseudos needed to be spilled. */
241 static regset_head spilled_pseudos
;
243 /* Used for communication between order_regs_for_reload and count_pseudo.
244 Used to avoid counting one pseudo twice. */
245 static regset_head pseudos_counted
;
247 /* First uid used by insns created by reload in this function.
248 Used in find_equiv_reg. */
249 int reload_first_uid
;
251 /* Flag set by local-alloc or global-alloc if anything is live in
252 a call-clobbered reg across calls. */
253 int caller_save_needed
;
255 /* Set to 1 while reload_as_needed is operating.
256 Required by some machines to handle any generated moves differently. */
257 int reload_in_progress
= 0;
259 /* These arrays record the insn_code of insns that may be needed to
260 perform input and output reloads of special objects. They provide a
261 place to pass a scratch register. */
262 enum insn_code reload_in_optab
[NUM_MACHINE_MODES
];
263 enum insn_code reload_out_optab
[NUM_MACHINE_MODES
];
265 /* This obstack is used for allocation of rtl during register elimination.
266 The allocated storage can be freed once find_reloads has processed the
268 struct obstack reload_obstack
;
270 /* Points to the beginning of the reload_obstack. All insn_chain structures
271 are allocated first. */
272 char *reload_startobj
;
274 /* The point after all insn_chain structures. Used to quickly deallocate
275 memory allocated in copy_reloads during calculate_needs_all_insns. */
276 char *reload_firstobj
;
278 /* This points before all local rtl generated by register elimination.
279 Used to quickly free all memory after processing one insn. */
280 static char *reload_insn_firstobj
;
282 #define obstack_chunk_alloc xmalloc
283 #define obstack_chunk_free free
285 /* List of insn_chain instructions, one for every insn that reload needs to
287 struct insn_chain
*reload_insn_chain
;
290 extern tree current_function_decl
;
292 extern union tree_node
*current_function_decl
;
295 /* List of all insns needing reloads. */
296 static struct insn_chain
*insns_need_reload
;
298 /* This structure is used to record information about register eliminations.
299 Each array entry describes one possible way of eliminating a register
300 in favor of another. If there is more than one way of eliminating a
301 particular register, the most preferred should be specified first. */
305 int from
; /* Register number to be eliminated. */
306 int to
; /* Register number used as replacement. */
307 int initial_offset
; /* Initial difference between values. */
308 int can_eliminate
; /* Non-zero if this elimination can be done. */
309 int can_eliminate_previous
; /* Value of CAN_ELIMINATE in previous scan over
310 insns made by reload. */
311 int offset
; /* Current offset between the two regs. */
312 int previous_offset
; /* Offset at end of previous insn. */
313 int ref_outside_mem
; /* "to" has been referenced outside a MEM. */
314 rtx from_rtx
; /* REG rtx for the register to be eliminated.
315 We cannot simply compare the number since
316 we might then spuriously replace a hard
317 register corresponding to a pseudo
318 assigned to the reg to be eliminated. */
319 rtx to_rtx
; /* REG rtx for the replacement. */
322 static struct elim_table
*reg_eliminate
= 0;
324 /* This is an intermediate structure to initialize the table. It has
325 exactly the members provided by ELIMINABLE_REGS. */
326 static struct elim_table_1
330 } reg_eliminate_1
[] =
332 /* If a set of eliminable registers was specified, define the table from it.
333 Otherwise, default to the normal case of the frame pointer being
334 replaced by the stack pointer. */
336 #ifdef ELIMINABLE_REGS
339 {{ FRAME_POINTER_REGNUM
, STACK_POINTER_REGNUM
}};
342 #define NUM_ELIMINABLE_REGS ARRAY_SIZE (reg_eliminate_1)
344 /* Record the number of pending eliminations that have an offset not equal
345 to their initial offset. If non-zero, we use a new copy of each
346 replacement result in any insns encountered. */
347 int num_not_at_initial_offset
;
349 /* Count the number of registers that we may be able to eliminate. */
350 static int num_eliminable
;
351 /* And the number of registers that are equivalent to a constant that
352 can be eliminated to frame_pointer / arg_pointer + constant. */
353 static int num_eliminable_invariants
;
355 /* For each label, we record the offset of each elimination. If we reach
356 a label by more than one path and an offset differs, we cannot do the
357 elimination. This information is indexed by the number of the label.
358 The first table is an array of flags that records whether we have yet
359 encountered a label and the second table is an array of arrays, one
360 entry in the latter array for each elimination. */
362 static char *offsets_known_at
;
363 static int (*offsets_at
)[NUM_ELIMINABLE_REGS
];
365 /* Number of labels in the current function. */
367 static int num_labels
;
369 static void replace_pseudos_in_call_usage
PARAMS((rtx
*,
372 static void maybe_fix_stack_asms
PARAMS ((void));
373 static void copy_reloads
PARAMS ((struct insn_chain
*));
374 static void calculate_needs_all_insns
PARAMS ((int));
375 static int find_reg
PARAMS ((struct insn_chain
*, int));
376 static void find_reload_regs
PARAMS ((struct insn_chain
*));
377 static void select_reload_regs
PARAMS ((void));
378 static void delete_caller_save_insns
PARAMS ((void));
380 static void spill_failure
PARAMS ((rtx
, enum reg_class
));
381 static void count_spilled_pseudo
PARAMS ((int, int, int));
382 static void delete_dead_insn
PARAMS ((rtx
));
383 static void alter_reg
PARAMS ((int, int));
384 static void set_label_offsets
PARAMS ((rtx
, rtx
, int));
385 static void check_eliminable_occurrences
PARAMS ((rtx
));
386 static void elimination_effects
PARAMS ((rtx
, enum machine_mode
));
387 static int eliminate_regs_in_insn
PARAMS ((rtx
, int));
388 static void update_eliminable_offsets
PARAMS ((void));
389 static void mark_not_eliminable
PARAMS ((rtx
, rtx
, void *));
390 static void set_initial_elim_offsets
PARAMS ((void));
391 static void verify_initial_elim_offsets
PARAMS ((void));
392 static void set_initial_label_offsets
PARAMS ((void));
393 static void set_offsets_for_label
PARAMS ((rtx
));
394 static void init_elim_table
PARAMS ((void));
395 static void update_eliminables
PARAMS ((HARD_REG_SET
*));
396 static void spill_hard_reg
PARAMS ((unsigned int, int));
397 static int finish_spills
PARAMS ((int));
398 static void ior_hard_reg_set
PARAMS ((HARD_REG_SET
*, HARD_REG_SET
*));
399 static void scan_paradoxical_subregs
PARAMS ((rtx
));
400 static void count_pseudo
PARAMS ((int));
401 static void order_regs_for_reload
PARAMS ((struct insn_chain
*));
402 static void reload_as_needed
PARAMS ((int));
403 static void forget_old_reloads_1
PARAMS ((rtx
, rtx
, void *));
404 static int reload_reg_class_lower
PARAMS ((const PTR
, const PTR
));
405 static void mark_reload_reg_in_use
PARAMS ((unsigned int, int,
408 static void clear_reload_reg_in_use
PARAMS ((unsigned int, int,
411 static int reload_reg_free_p
PARAMS ((unsigned int, int,
413 static int reload_reg_free_for_value_p
PARAMS ((int, int, int,
415 rtx
, rtx
, int, int));
416 static int free_for_value_p
PARAMS ((int, enum machine_mode
, int,
417 enum reload_type
, rtx
, rtx
,
419 static int reload_reg_reaches_end_p
PARAMS ((unsigned int, int,
421 static int allocate_reload_reg
PARAMS ((struct insn_chain
*, int,
423 static int conflicts_with_override
PARAMS ((rtx
));
424 static void failed_reload
PARAMS ((rtx
, int));
425 static int set_reload_reg
PARAMS ((int, int));
426 static void choose_reload_regs_init
PARAMS ((struct insn_chain
*, rtx
*));
427 static void choose_reload_regs
PARAMS ((struct insn_chain
*));
428 static void merge_assigned_reloads
PARAMS ((rtx
));
429 static void emit_input_reload_insns
PARAMS ((struct insn_chain
*,
430 struct reload
*, rtx
, int));
431 static void emit_output_reload_insns
PARAMS ((struct insn_chain
*,
432 struct reload
*, int));
433 static void do_input_reload
PARAMS ((struct insn_chain
*,
434 struct reload
*, int));
435 static void do_output_reload
PARAMS ((struct insn_chain
*,
436 struct reload
*, int));
437 static void emit_reload_insns
PARAMS ((struct insn_chain
*));
438 static void delete_output_reload
PARAMS ((rtx
, int, int));
439 static void delete_address_reloads
PARAMS ((rtx
, rtx
));
440 static void delete_address_reloads_1
PARAMS ((rtx
, rtx
, rtx
));
441 static rtx inc_for_reload
PARAMS ((rtx
, rtx
, rtx
, int));
442 static int constraint_accepts_reg_p
PARAMS ((const char *, rtx
));
443 static void reload_cse_regs_1
PARAMS ((rtx
));
444 static int reload_cse_noop_set_p
PARAMS ((rtx
));
445 static int reload_cse_simplify_set
PARAMS ((rtx
, rtx
));
446 static int reload_cse_simplify_operands
PARAMS ((rtx
));
447 static void reload_combine
PARAMS ((void));
448 static void reload_combine_note_use
PARAMS ((rtx
*, rtx
));
449 static void reload_combine_note_store
PARAMS ((rtx
, rtx
, void *));
450 static void reload_cse_move2add
PARAMS ((rtx
));
451 static void move2add_note_store
PARAMS ((rtx
, rtx
, void *));
453 static void add_auto_inc_notes
PARAMS ((rtx
, rtx
));
455 static void copy_eh_notes
PARAMS ((rtx
, rtx
));
456 static HOST_WIDE_INT sext_for_mode
PARAMS ((enum machine_mode
,
458 static void failed_reload
PARAMS ((rtx
, int));
459 static int set_reload_reg
PARAMS ((int, int));
460 static void reload_cse_delete_noop_set
PARAMS ((rtx
, rtx
));
461 static void reload_cse_simplify
PARAMS ((rtx
));
462 static void fixup_abnormal_edges
PARAMS ((void));
463 extern void dump_needs
PARAMS ((struct insn_chain
*));
465 /* Initialize the reload pass once per compilation. */
472 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
473 Set spill_indirect_levels to the number of levels such addressing is
474 permitted, zero if it is not permitted at all. */
477 = gen_rtx_MEM (Pmode
,
480 LAST_VIRTUAL_REGISTER
+ 1),
482 spill_indirect_levels
= 0;
484 while (memory_address_p (QImode
, tem
))
486 spill_indirect_levels
++;
487 tem
= gen_rtx_MEM (Pmode
, tem
);
490 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
492 tem
= gen_rtx_MEM (Pmode
, gen_rtx_SYMBOL_REF (Pmode
, "foo"));
493 indirect_symref_ok
= memory_address_p (QImode
, tem
);
495 /* See if reg+reg is a valid (and offsettable) address. */
497 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
499 tem
= gen_rtx_PLUS (Pmode
,
500 gen_rtx_REG (Pmode
, HARD_FRAME_POINTER_REGNUM
),
501 gen_rtx_REG (Pmode
, i
));
503 /* This way, we make sure that reg+reg is an offsettable address. */
504 tem
= plus_constant (tem
, 4);
506 if (memory_address_p (QImode
, tem
))
508 double_reg_address_ok
= 1;
513 /* Initialize obstack for our rtl allocation. */
514 gcc_obstack_init (&reload_obstack
);
515 reload_startobj
= (char *) obstack_alloc (&reload_obstack
, 0);
517 INIT_REG_SET (&spilled_pseudos
);
518 INIT_REG_SET (&pseudos_counted
);
521 /* List of insn chains that are currently unused. */
522 static struct insn_chain
*unused_insn_chains
= 0;
524 /* Allocate an empty insn_chain structure. */
528 struct insn_chain
*c
;
530 if (unused_insn_chains
== 0)
532 c
= (struct insn_chain
*)
533 obstack_alloc (&reload_obstack
, sizeof (struct insn_chain
));
534 INIT_REG_SET (&c
->live_throughout
);
535 INIT_REG_SET (&c
->dead_or_set
);
539 c
= unused_insn_chains
;
540 unused_insn_chains
= c
->next
;
542 c
->is_caller_save_insn
= 0;
543 c
->need_operand_change
= 0;
549 /* Small utility function to set all regs in hard reg set TO which are
550 allocated to pseudos in regset FROM. */
553 compute_use_by_pseudos (to
, from
)
559 EXECUTE_IF_SET_IN_REG_SET
560 (from
, FIRST_PSEUDO_REGISTER
, regno
,
562 int r
= reg_renumber
[regno
];
567 /* reload_combine uses the information from
568 BASIC_BLOCK->global_live_at_start, which might still
569 contain registers that have not actually been allocated
570 since they have an equivalence. */
571 if (! reload_completed
)
576 nregs
= HARD_REGNO_NREGS (r
, PSEUDO_REGNO_MODE (regno
));
578 SET_HARD_REG_BIT (*to
, r
+ nregs
);
583 /* Replace all pseudos found in LOC with their corresponding
587 replace_pseudos_in_call_usage (loc
, mem_mode
, usage
)
589 enum machine_mode mem_mode
;
603 unsigned int regno
= REGNO (x
);
605 if (regno
< FIRST_PSEUDO_REGISTER
)
608 x
= eliminate_regs (x
, mem_mode
, usage
);
612 replace_pseudos_in_call_usage (loc
, mem_mode
, usage
);
616 if (reg_equiv_constant
[regno
])
617 *loc
= reg_equiv_constant
[regno
];
618 else if (reg_equiv_mem
[regno
])
619 *loc
= reg_equiv_mem
[regno
];
620 else if (reg_equiv_address
[regno
])
621 *loc
= gen_rtx_MEM (GET_MODE (x
), reg_equiv_address
[regno
]);
622 else if (GET_CODE (regno_reg_rtx
[regno
]) != REG
623 || REGNO (regno_reg_rtx
[regno
]) != regno
)
624 *loc
= regno_reg_rtx
[regno
];
630 else if (code
== MEM
)
632 replace_pseudos_in_call_usage (& XEXP (x
, 0), GET_MODE (x
), usage
);
636 /* Process each of our operands recursively. */
637 fmt
= GET_RTX_FORMAT (code
);
638 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++, fmt
++)
640 replace_pseudos_in_call_usage (&XEXP (x
, i
), mem_mode
, usage
);
641 else if (*fmt
== 'E')
642 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
643 replace_pseudos_in_call_usage (& XVECEXP (x
, i
, j
), mem_mode
, usage
);
647 /* Global variables used by reload and its subroutines. */
649 /* Set during calculate_needs if an insn needs register elimination. */
650 static int something_needs_elimination
;
651 /* Set during calculate_needs if an insn needs an operand changed. */
652 int something_needs_operands_changed
;
654 /* Nonzero means we couldn't get enough spill regs. */
657 /* Main entry point for the reload pass.
659 FIRST is the first insn of the function being compiled.
661 GLOBAL nonzero means we were called from global_alloc
662 and should attempt to reallocate any pseudoregs that we
663 displace from hard regs we will use for reloads.
664 If GLOBAL is zero, we do not have enough information to do that,
665 so any pseudo reg that is spilled must go to the stack.
667 Return value is nonzero if reload failed
668 and we must not do any more for this function. */
671 reload (first
, global
)
677 register struct elim_table
*ep
;
679 /* The two pointers used to track the true location of the memory used
680 for label offsets. */
681 char *real_known_ptr
= NULL
;
682 int (*real_at_ptr
)[NUM_ELIMINABLE_REGS
];
684 /* Make sure even insns with volatile mem refs are recognizable. */
689 reload_firstobj
= (char *) obstack_alloc (&reload_obstack
, 0);
691 /* Make sure that the last insn in the chain
692 is not something that needs reloading. */
693 emit_note (NULL
, NOTE_INSN_DELETED
);
695 /* Enable find_equiv_reg to distinguish insns made by reload. */
696 reload_first_uid
= get_max_uid ();
698 #ifdef SECONDARY_MEMORY_NEEDED
699 /* Initialize the secondary memory table. */
700 clear_secondary_mem ();
703 /* We don't have a stack slot for any spill reg yet. */
704 memset ((char *) spill_stack_slot
, 0, sizeof spill_stack_slot
);
705 memset ((char *) spill_stack_slot_width
, 0, sizeof spill_stack_slot_width
);
707 /* Initialize the save area information for caller-save, in case some
711 /* Compute which hard registers are now in use
712 as homes for pseudo registers.
713 This is done here rather than (eg) in global_alloc
714 because this point is reached even if not optimizing. */
715 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
718 /* A function that receives a nonlocal goto must save all call-saved
720 if (current_function_has_nonlocal_label
)
721 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
722 if (! call_used_regs
[i
] && ! fixed_regs
[i
] && ! LOCAL_REGNO (i
))
723 regs_ever_live
[i
] = 1;
725 /* Find all the pseudo registers that didn't get hard regs
726 but do have known equivalent constants or memory slots.
727 These include parameters (known equivalent to parameter slots)
728 and cse'd or loop-moved constant memory addresses.
730 Record constant equivalents in reg_equiv_constant
731 so they will be substituted by find_reloads.
732 Record memory equivalents in reg_mem_equiv so they can
733 be substituted eventually by altering the REG-rtx's. */
735 reg_equiv_constant
= (rtx
*) xcalloc (max_regno
, sizeof (rtx
));
736 reg_equiv_memory_loc
= (rtx
*) xcalloc (max_regno
, sizeof (rtx
));
737 reg_equiv_mem
= (rtx
*) xcalloc (max_regno
, sizeof (rtx
));
738 reg_equiv_init
= (rtx
*) xcalloc (max_regno
, sizeof (rtx
));
739 reg_equiv_address
= (rtx
*) xcalloc (max_regno
, sizeof (rtx
));
740 reg_max_ref_width
= (unsigned int *) xcalloc (max_regno
, sizeof (int));
741 reg_old_renumber
= (short *) xcalloc (max_regno
, sizeof (short));
742 memcpy (reg_old_renumber
, reg_renumber
, max_regno
* sizeof (short));
743 pseudo_forbidden_regs
744 = (HARD_REG_SET
*) xmalloc (max_regno
* sizeof (HARD_REG_SET
));
746 = (HARD_REG_SET
*) xcalloc (max_regno
, sizeof (HARD_REG_SET
));
748 CLEAR_HARD_REG_SET (bad_spill_regs_global
);
750 /* Look for REG_EQUIV notes; record what each pseudo is equivalent to.
751 Also find all paradoxical subregs and find largest such for each pseudo.
752 On machines with small register classes, record hard registers that
753 are used for user variables. These can never be used for spills.
754 Also look for a "constant" REG_SETJMP. This means that all
755 caller-saved registers must be marked live. */
757 num_eliminable_invariants
= 0;
758 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
760 rtx set
= single_set (insn
);
762 if (GET_CODE (insn
) == CALL_INSN
763 && find_reg_note (insn
, REG_SETJMP
, NULL
))
764 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
765 if (! call_used_regs
[i
])
766 regs_ever_live
[i
] = 1;
768 if (set
!= 0 && GET_CODE (SET_DEST (set
)) == REG
)
770 rtx note
= find_reg_note (insn
, REG_EQUIV
, NULL_RTX
);
772 #ifdef LEGITIMATE_PIC_OPERAND_P
773 && (! function_invariant_p (XEXP (note
, 0))
775 || LEGITIMATE_PIC_OPERAND_P (XEXP (note
, 0)))
779 rtx x
= XEXP (note
, 0);
780 i
= REGNO (SET_DEST (set
));
781 if (i
> LAST_VIRTUAL_REGISTER
)
783 if (GET_CODE (x
) == MEM
)
785 /* If the operand is a PLUS, the MEM may be shared,
786 so make sure we have an unshared copy here. */
787 if (GET_CODE (XEXP (x
, 0)) == PLUS
)
790 reg_equiv_memory_loc
[i
] = x
;
792 else if (function_invariant_p (x
))
794 if (GET_CODE (x
) == PLUS
)
796 /* This is PLUS of frame pointer and a constant,
797 and might be shared. Unshare it. */
798 reg_equiv_constant
[i
] = copy_rtx (x
);
799 num_eliminable_invariants
++;
801 else if (x
== frame_pointer_rtx
802 || x
== arg_pointer_rtx
)
804 reg_equiv_constant
[i
] = x
;
805 num_eliminable_invariants
++;
807 else if (LEGITIMATE_CONSTANT_P (x
))
808 reg_equiv_constant
[i
] = x
;
810 reg_equiv_memory_loc
[i
]
811 = force_const_mem (GET_MODE (SET_DEST (set
)), x
);
816 /* If this register is being made equivalent to a MEM
817 and the MEM is not SET_SRC, the equivalencing insn
818 is one with the MEM as a SET_DEST and it occurs later.
819 So don't mark this insn now. */
820 if (GET_CODE (x
) != MEM
821 || rtx_equal_p (SET_SRC (set
), x
))
823 = gen_rtx_INSN_LIST (VOIDmode
, insn
, reg_equiv_init
[i
]);
828 /* If this insn is setting a MEM from a register equivalent to it,
829 this is the equivalencing insn. */
830 else if (set
&& GET_CODE (SET_DEST (set
)) == MEM
831 && GET_CODE (SET_SRC (set
)) == REG
832 && reg_equiv_memory_loc
[REGNO (SET_SRC (set
))]
833 && rtx_equal_p (SET_DEST (set
),
834 reg_equiv_memory_loc
[REGNO (SET_SRC (set
))]))
835 reg_equiv_init
[REGNO (SET_SRC (set
))]
836 = gen_rtx_INSN_LIST (VOIDmode
, insn
,
837 reg_equiv_init
[REGNO (SET_SRC (set
))]);
840 scan_paradoxical_subregs (PATTERN (insn
));
845 num_labels
= max_label_num () - get_first_label_num ();
847 /* Allocate the tables used to store offset information at labels. */
848 /* We used to use alloca here, but the size of what it would try to
849 allocate would occasionally cause it to exceed the stack limit and
850 cause a core dump. */
851 real_known_ptr
= xmalloc (num_labels
);
853 = (int (*)[NUM_ELIMINABLE_REGS
])
854 xmalloc (num_labels
* NUM_ELIMINABLE_REGS
* sizeof (int));
856 offsets_known_at
= real_known_ptr
- get_first_label_num ();
858 = (int (*)[NUM_ELIMINABLE_REGS
]) (real_at_ptr
- get_first_label_num ());
860 /* Alter each pseudo-reg rtx to contain its hard reg number.
861 Assign stack slots to the pseudos that lack hard regs or equivalents.
862 Do not touch virtual registers. */
864 for (i
= LAST_VIRTUAL_REGISTER
+ 1; i
< max_regno
; i
++)
867 /* If we have some registers we think can be eliminated, scan all insns to
868 see if there is an insn that sets one of these registers to something
869 other than itself plus a constant. If so, the register cannot be
870 eliminated. Doing this scan here eliminates an extra pass through the
871 main reload loop in the most common case where register elimination
873 for (insn
= first
; insn
&& num_eliminable
; insn
= NEXT_INSN (insn
))
874 if (GET_CODE (insn
) == INSN
|| GET_CODE (insn
) == JUMP_INSN
875 || GET_CODE (insn
) == CALL_INSN
)
876 note_stores (PATTERN (insn
), mark_not_eliminable
, NULL
);
878 maybe_fix_stack_asms ();
880 insns_need_reload
= 0;
881 something_needs_elimination
= 0;
883 /* Initialize to -1, which means take the first spill register. */
886 /* Spill any hard regs that we know we can't eliminate. */
887 CLEAR_HARD_REG_SET (used_spill_regs
);
888 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
889 if (! ep
->can_eliminate
)
890 spill_hard_reg (ep
->from
, 1);
892 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
893 if (frame_pointer_needed
)
894 spill_hard_reg (HARD_FRAME_POINTER_REGNUM
, 1);
896 finish_spills (global
);
898 /* From now on, we may need to generate moves differently. We may also
899 allow modifications of insns which cause them to not be recognized.
900 Any such modifications will be cleaned up during reload itself. */
901 reload_in_progress
= 1;
903 /* This loop scans the entire function each go-round
904 and repeats until one repetition spills no additional hard regs. */
907 int something_changed
;
910 HOST_WIDE_INT starting_frame_size
;
912 /* Round size of stack frame to stack_alignment_needed. This must be done
913 here because the stack size may be a part of the offset computation
914 for register elimination, and there might have been new stack slots
915 created in the last iteration of this loop. */
916 if (cfun
->stack_alignment_needed
)
917 assign_stack_local (BLKmode
, 0, cfun
->stack_alignment_needed
);
919 starting_frame_size
= get_frame_size ();
921 set_initial_elim_offsets ();
922 set_initial_label_offsets ();
924 /* For each pseudo register that has an equivalent location defined,
925 try to eliminate any eliminable registers (such as the frame pointer)
926 assuming initial offsets for the replacement register, which
929 If the resulting location is directly addressable, substitute
930 the MEM we just got directly for the old REG.
932 If it is not addressable but is a constant or the sum of a hard reg
933 and constant, it is probably not addressable because the constant is
934 out of range, in that case record the address; we will generate
935 hairy code to compute the address in a register each time it is
936 needed. Similarly if it is a hard register, but one that is not
937 valid as an address register.
939 If the location is not addressable, but does not have one of the
940 above forms, assign a stack slot. We have to do this to avoid the
941 potential of producing lots of reloads if, e.g., a location involves
942 a pseudo that didn't get a hard register and has an equivalent memory
943 location that also involves a pseudo that didn't get a hard register.
945 Perhaps at some point we will improve reload_when_needed handling
946 so this problem goes away. But that's very hairy. */
948 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
949 if (reg_renumber
[i
] < 0 && reg_equiv_memory_loc
[i
])
951 rtx x
= eliminate_regs (reg_equiv_memory_loc
[i
], 0, NULL_RTX
);
953 if (strict_memory_address_p (GET_MODE (regno_reg_rtx
[i
]),
955 reg_equiv_mem
[i
] = x
, reg_equiv_address
[i
] = 0;
956 else if (CONSTANT_P (XEXP (x
, 0))
957 || (GET_CODE (XEXP (x
, 0)) == REG
958 && REGNO (XEXP (x
, 0)) < FIRST_PSEUDO_REGISTER
)
959 || (GET_CODE (XEXP (x
, 0)) == PLUS
960 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == REG
961 && (REGNO (XEXP (XEXP (x
, 0), 0))
962 < FIRST_PSEUDO_REGISTER
)
963 && CONSTANT_P (XEXP (XEXP (x
, 0), 1))))
964 reg_equiv_address
[i
] = XEXP (x
, 0), reg_equiv_mem
[i
] = 0;
967 /* Make a new stack slot. Then indicate that something
968 changed so we go back and recompute offsets for
969 eliminable registers because the allocation of memory
970 below might change some offset. reg_equiv_{mem,address}
971 will be set up for this pseudo on the next pass around
973 reg_equiv_memory_loc
[i
] = 0;
974 reg_equiv_init
[i
] = 0;
979 if (caller_save_needed
)
982 /* If we allocated another stack slot, redo elimination bookkeeping. */
983 if (starting_frame_size
!= get_frame_size ())
986 if (caller_save_needed
)
988 save_call_clobbered_regs ();
989 /* That might have allocated new insn_chain structures. */
990 reload_firstobj
= (char *) obstack_alloc (&reload_obstack
, 0);
993 calculate_needs_all_insns (global
);
995 CLEAR_REG_SET (&spilled_pseudos
);
998 something_changed
= 0;
1000 /* If we allocated any new memory locations, make another pass
1001 since it might have changed elimination offsets. */
1002 if (starting_frame_size
!= get_frame_size ())
1003 something_changed
= 1;
1006 HARD_REG_SET to_spill
;
1007 CLEAR_HARD_REG_SET (to_spill
);
1008 update_eliminables (&to_spill
);
1009 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1010 if (TEST_HARD_REG_BIT (to_spill
, i
))
1012 spill_hard_reg (i
, 1);
1015 /* Regardless of the state of spills, if we previously had
1016 a register that we thought we could eliminate, but no can
1017 not eliminate, we must run another pass.
1019 Consider pseudos which have an entry in reg_equiv_* which
1020 reference an eliminable register. We must make another pass
1021 to update reg_equiv_* so that we do not substitute in the
1022 old value from when we thought the elimination could be
1024 something_changed
= 1;
1028 select_reload_regs ();
1032 if (insns_need_reload
!= 0 || did_spill
)
1033 something_changed
|= finish_spills (global
);
1035 if (! something_changed
)
1038 if (caller_save_needed
)
1039 delete_caller_save_insns ();
1041 obstack_free (&reload_obstack
, reload_firstobj
);
1044 /* If global-alloc was run, notify it of any register eliminations we have
1047 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
1048 if (ep
->can_eliminate
)
1049 mark_elimination (ep
->from
, ep
->to
);
1051 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
1052 If that insn didn't set the register (i.e., it copied the register to
1053 memory), just delete that insn instead of the equivalencing insn plus
1054 anything now dead. If we call delete_dead_insn on that insn, we may
1055 delete the insn that actually sets the register if the register dies
1056 there and that is incorrect. */
1058 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
1060 if (reg_renumber
[i
] < 0 && reg_equiv_init
[i
] != 0)
1063 for (list
= reg_equiv_init
[i
]; list
; list
= XEXP (list
, 1))
1065 rtx equiv_insn
= XEXP (list
, 0);
1066 if (GET_CODE (equiv_insn
) == NOTE
)
1068 if (reg_set_p (regno_reg_rtx
[i
], PATTERN (equiv_insn
)))
1069 delete_dead_insn (equiv_insn
);
1072 PUT_CODE (equiv_insn
, NOTE
);
1073 NOTE_SOURCE_FILE (equiv_insn
) = 0;
1074 NOTE_LINE_NUMBER (equiv_insn
) = NOTE_INSN_DELETED
;
1080 /* Use the reload registers where necessary
1081 by generating move instructions to move the must-be-register
1082 values into or out of the reload registers. */
1084 if (insns_need_reload
!= 0 || something_needs_elimination
1085 || something_needs_operands_changed
)
1087 HOST_WIDE_INT old_frame_size
= get_frame_size ();
1089 reload_as_needed (global
);
1091 if (old_frame_size
!= get_frame_size ())
1095 verify_initial_elim_offsets ();
1098 /* If we were able to eliminate the frame pointer, show that it is no
1099 longer live at the start of any basic block. If it ls live by
1100 virtue of being in a pseudo, that pseudo will be marked live
1101 and hence the frame pointer will be known to be live via that
1104 if (! frame_pointer_needed
)
1105 for (i
= 0; i
< n_basic_blocks
; i
++)
1106 CLEAR_REGNO_REG_SET (BASIC_BLOCK (i
)->global_live_at_start
,
1107 HARD_FRAME_POINTER_REGNUM
);
1109 /* Come here (with failure set nonzero) if we can't get enough spill regs
1110 and we decide not to abort about it. */
1113 CLEAR_REG_SET (&spilled_pseudos
);
1114 reload_in_progress
= 0;
1116 /* Now eliminate all pseudo regs by modifying them into
1117 their equivalent memory references.
1118 The REG-rtx's for the pseudos are modified in place,
1119 so all insns that used to refer to them now refer to memory.
1121 For a reg that has a reg_equiv_address, all those insns
1122 were changed by reloading so that no insns refer to it any longer;
1123 but the DECL_RTL of a variable decl may refer to it,
1124 and if so this causes the debugging info to mention the variable. */
1126 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
1131 int is_readonly
= 0;
1133 if (reg_equiv_memory_loc
[i
])
1135 in_struct
= MEM_IN_STRUCT_P (reg_equiv_memory_loc
[i
]);
1136 is_scalar
= MEM_SCALAR_P (reg_equiv_memory_loc
[i
]);
1137 is_readonly
= RTX_UNCHANGING_P (reg_equiv_memory_loc
[i
]);
1140 if (reg_equiv_mem
[i
])
1141 addr
= XEXP (reg_equiv_mem
[i
], 0);
1143 if (reg_equiv_address
[i
])
1144 addr
= reg_equiv_address
[i
];
1148 if (reg_renumber
[i
] < 0)
1150 rtx reg
= regno_reg_rtx
[i
];
1151 PUT_CODE (reg
, MEM
);
1152 XEXP (reg
, 0) = addr
;
1153 REG_USERVAR_P (reg
) = 0;
1154 RTX_UNCHANGING_P (reg
) = is_readonly
;
1155 MEM_IN_STRUCT_P (reg
) = in_struct
;
1156 MEM_SCALAR_P (reg
) = is_scalar
;
1157 /* We have no alias information about this newly created
1159 set_mem_alias_set (reg
, 0);
1161 else if (reg_equiv_mem
[i
])
1162 XEXP (reg_equiv_mem
[i
], 0) = addr
;
1166 /* We must set reload_completed now since the cleanup_subreg_operands call
1167 below will re-recognize each insn and reload may have generated insns
1168 which are only valid during and after reload. */
1169 reload_completed
= 1;
1171 /* Make a pass over all the insns and delete all USEs which we inserted
1172 only to tag a REG_EQUAL note on them. Remove all REG_DEAD and REG_UNUSED
1173 notes. Delete all CLOBBER insns that don't refer to the return value
1174 and simplify (subreg (reg)) operands. Also remove all REG_RETVAL and
1175 REG_LIBCALL notes since they are no longer useful or accurate. Strip
1176 and regenerate REG_INC notes that may have been moved around. */
1178 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
1183 if (GET_CODE (insn
) == CALL_INSN
)
1184 replace_pseudos_in_call_usage (& CALL_INSN_FUNCTION_USAGE (insn
),
1186 CALL_INSN_FUNCTION_USAGE (insn
));
1188 if ((GET_CODE (PATTERN (insn
)) == USE
1189 && find_reg_note (insn
, REG_EQUAL
, NULL_RTX
))
1190 || (GET_CODE (PATTERN (insn
)) == CLOBBER
1191 && (GET_CODE (XEXP (PATTERN (insn
), 0)) != REG
1192 || ! REG_FUNCTION_VALUE_P (XEXP (PATTERN (insn
), 0)))))
1194 PUT_CODE (insn
, NOTE
);
1195 NOTE_SOURCE_FILE (insn
) = 0;
1196 NOTE_LINE_NUMBER (insn
) = NOTE_INSN_DELETED
;
1200 pnote
= ®_NOTES (insn
);
1203 if (REG_NOTE_KIND (*pnote
) == REG_DEAD
1204 || REG_NOTE_KIND (*pnote
) == REG_UNUSED
1205 || REG_NOTE_KIND (*pnote
) == REG_INC
1206 || REG_NOTE_KIND (*pnote
) == REG_RETVAL
1207 || REG_NOTE_KIND (*pnote
) == REG_LIBCALL
)
1208 *pnote
= XEXP (*pnote
, 1);
1210 pnote
= &XEXP (*pnote
, 1);
1214 add_auto_inc_notes (insn
, PATTERN (insn
));
1217 /* And simplify (subreg (reg)) if it appears as an operand. */
1218 cleanup_subreg_operands (insn
);
1221 /* If we are doing stack checking, give a warning if this function's
1222 frame size is larger than we expect. */
1223 if (flag_stack_check
&& ! STACK_CHECK_BUILTIN
)
1225 HOST_WIDE_INT size
= get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE
;
1226 static int verbose_warned
= 0;
1228 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1229 if (regs_ever_live
[i
] && ! fixed_regs
[i
] && call_used_regs
[i
])
1230 size
+= UNITS_PER_WORD
;
1232 if (size
> STACK_CHECK_MAX_FRAME_SIZE
)
1234 warning ("frame size too large for reliable stack checking");
1235 if (! verbose_warned
)
1237 warning ("try reducing the number of local variables");
1243 /* Indicate that we no longer have known memory locations or constants. */
1244 if (reg_equiv_constant
)
1245 free (reg_equiv_constant
);
1246 reg_equiv_constant
= 0;
1247 if (reg_equiv_memory_loc
)
1248 free (reg_equiv_memory_loc
);
1249 reg_equiv_memory_loc
= 0;
1252 free (real_known_ptr
);
1256 free (reg_equiv_mem
);
1257 free (reg_equiv_init
);
1258 free (reg_equiv_address
);
1259 free (reg_max_ref_width
);
1260 free (reg_old_renumber
);
1261 free (pseudo_previous_regs
);
1262 free (pseudo_forbidden_regs
);
1264 CLEAR_HARD_REG_SET (used_spill_regs
);
1265 for (i
= 0; i
< n_spills
; i
++)
1266 SET_HARD_REG_BIT (used_spill_regs
, spill_regs
[i
]);
1268 /* Free all the insn_chain structures at once. */
1269 obstack_free (&reload_obstack
, reload_startobj
);
1270 unused_insn_chains
= 0;
1271 fixup_abnormal_edges ();
1276 /* Yet another special case. Unfortunately, reg-stack forces people to
1277 write incorrect clobbers in asm statements. These clobbers must not
1278 cause the register to appear in bad_spill_regs, otherwise we'll call
1279 fatal_insn later. We clear the corresponding regnos in the live
1280 register sets to avoid this.
1281 The whole thing is rather sick, I'm afraid. */
1284 maybe_fix_stack_asms ()
1287 const char *constraints
[MAX_RECOG_OPERANDS
];
1288 enum machine_mode operand_mode
[MAX_RECOG_OPERANDS
];
1289 struct insn_chain
*chain
;
1291 for (chain
= reload_insn_chain
; chain
!= 0; chain
= chain
->next
)
1294 HARD_REG_SET clobbered
, allowed
;
1297 if (! INSN_P (chain
->insn
)
1298 || (noperands
= asm_noperands (PATTERN (chain
->insn
))) < 0)
1300 pat
= PATTERN (chain
->insn
);
1301 if (GET_CODE (pat
) != PARALLEL
)
1304 CLEAR_HARD_REG_SET (clobbered
);
1305 CLEAR_HARD_REG_SET (allowed
);
1307 /* First, make a mask of all stack regs that are clobbered. */
1308 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
1310 rtx t
= XVECEXP (pat
, 0, i
);
1311 if (GET_CODE (t
) == CLOBBER
&& STACK_REG_P (XEXP (t
, 0)))
1312 SET_HARD_REG_BIT (clobbered
, REGNO (XEXP (t
, 0)));
1315 /* Get the operand values and constraints out of the insn. */
1316 decode_asm_operands (pat
, recog_data
.operand
, recog_data
.operand_loc
,
1317 constraints
, operand_mode
);
1319 /* For every operand, see what registers are allowed. */
1320 for (i
= 0; i
< noperands
; i
++)
1322 const char *p
= constraints
[i
];
1323 /* For every alternative, we compute the class of registers allowed
1324 for reloading in CLS, and merge its contents into the reg set
1326 int cls
= (int) NO_REGS
;
1332 if (c
== '\0' || c
== ',' || c
== '#')
1334 /* End of one alternative - mark the regs in the current
1335 class, and reset the class. */
1336 IOR_HARD_REG_SET (allowed
, reg_class_contents
[cls
]);
1341 } while (c
!= '\0' && c
!= ',');
1349 case '=': case '+': case '*': case '%': case '?': case '!':
1350 case '0': case '1': case '2': case '3': case '4': case 'm':
1351 case '<': case '>': case 'V': case 'o': case '&': case 'E':
1352 case 'F': case 's': case 'i': case 'n': case 'X': case 'I':
1353 case 'J': case 'K': case 'L': case 'M': case 'N': case 'O':
1358 cls
= (int) reg_class_subunion
[cls
][(int) BASE_REG_CLASS
];
1363 cls
= (int) reg_class_subunion
[cls
][(int) GENERAL_REGS
];
1367 cls
= (int) reg_class_subunion
[cls
][(int) REG_CLASS_FROM_LETTER (c
)];
1372 /* Those of the registers which are clobbered, but allowed by the
1373 constraints, must be usable as reload registers. So clear them
1374 out of the life information. */
1375 AND_HARD_REG_SET (allowed
, clobbered
);
1376 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1377 if (TEST_HARD_REG_BIT (allowed
, i
))
1379 CLEAR_REGNO_REG_SET (&chain
->live_throughout
, i
);
1380 CLEAR_REGNO_REG_SET (&chain
->dead_or_set
, i
);
1387 /* Copy the global variables n_reloads and rld into the corresponding elts
1390 copy_reloads (chain
)
1391 struct insn_chain
*chain
;
1393 chain
->n_reloads
= n_reloads
;
1395 = (struct reload
*) obstack_alloc (&reload_obstack
,
1396 n_reloads
* sizeof (struct reload
));
1397 memcpy (chain
->rld
, rld
, n_reloads
* sizeof (struct reload
));
1398 reload_insn_firstobj
= (char *) obstack_alloc (&reload_obstack
, 0);
1401 /* Walk the chain of insns, and determine for each whether it needs reloads
1402 and/or eliminations. Build the corresponding insns_need_reload list, and
1403 set something_needs_elimination as appropriate. */
1405 calculate_needs_all_insns (global
)
1408 struct insn_chain
**pprev_reload
= &insns_need_reload
;
1409 struct insn_chain
*chain
, *next
= 0;
1411 something_needs_elimination
= 0;
1413 reload_insn_firstobj
= (char *) obstack_alloc (&reload_obstack
, 0);
1414 for (chain
= reload_insn_chain
; chain
!= 0; chain
= next
)
1416 rtx insn
= chain
->insn
;
1420 /* Clear out the shortcuts. */
1421 chain
->n_reloads
= 0;
1422 chain
->need_elim
= 0;
1423 chain
->need_reload
= 0;
1424 chain
->need_operand_change
= 0;
1426 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1427 include REG_LABEL), we need to see what effects this has on the
1428 known offsets at labels. */
1430 if (GET_CODE (insn
) == CODE_LABEL
|| GET_CODE (insn
) == JUMP_INSN
1431 || (INSN_P (insn
) && REG_NOTES (insn
) != 0))
1432 set_label_offsets (insn
, insn
, 0);
1436 rtx old_body
= PATTERN (insn
);
1437 int old_code
= INSN_CODE (insn
);
1438 rtx old_notes
= REG_NOTES (insn
);
1439 int did_elimination
= 0;
1440 int operands_changed
= 0;
1441 rtx set
= single_set (insn
);
1443 /* Skip insns that only set an equivalence. */
1444 if (set
&& GET_CODE (SET_DEST (set
)) == REG
1445 && reg_renumber
[REGNO (SET_DEST (set
))] < 0
1446 && reg_equiv_constant
[REGNO (SET_DEST (set
))])
1449 /* If needed, eliminate any eliminable registers. */
1450 if (num_eliminable
|| num_eliminable_invariants
)
1451 did_elimination
= eliminate_regs_in_insn (insn
, 0);
1453 /* Analyze the instruction. */
1454 operands_changed
= find_reloads (insn
, 0, spill_indirect_levels
,
1455 global
, spill_reg_order
);
1457 /* If a no-op set needs more than one reload, this is likely
1458 to be something that needs input address reloads. We
1459 can't get rid of this cleanly later, and it is of no use
1460 anyway, so discard it now.
1461 We only do this when expensive_optimizations is enabled,
1462 since this complements reload inheritance / output
1463 reload deletion, and it can make debugging harder. */
1464 if (flag_expensive_optimizations
&& n_reloads
> 1)
1466 rtx set
= single_set (insn
);
1468 && SET_SRC (set
) == SET_DEST (set
)
1469 && GET_CODE (SET_SRC (set
)) == REG
1470 && REGNO (SET_SRC (set
)) >= FIRST_PSEUDO_REGISTER
)
1472 PUT_CODE (insn
, NOTE
);
1473 NOTE_SOURCE_FILE (insn
) = 0;
1474 NOTE_LINE_NUMBER (insn
) = NOTE_INSN_DELETED
;
1475 /* Delete it from the reload chain */
1477 chain
->prev
->next
= next
;
1479 reload_insn_chain
= next
;
1481 next
->prev
= chain
->prev
;
1482 chain
->next
= unused_insn_chains
;
1483 unused_insn_chains
= chain
;
1488 update_eliminable_offsets ();
1490 /* Remember for later shortcuts which insns had any reloads or
1491 register eliminations. */
1492 chain
->need_elim
= did_elimination
;
1493 chain
->need_reload
= n_reloads
> 0;
1494 chain
->need_operand_change
= operands_changed
;
1496 /* Discard any register replacements done. */
1497 if (did_elimination
)
1499 obstack_free (&reload_obstack
, reload_insn_firstobj
);
1500 PATTERN (insn
) = old_body
;
1501 INSN_CODE (insn
) = old_code
;
1502 REG_NOTES (insn
) = old_notes
;
1503 something_needs_elimination
= 1;
1506 something_needs_operands_changed
|= operands_changed
;
1510 copy_reloads (chain
);
1511 *pprev_reload
= chain
;
1512 pprev_reload
= &chain
->next_need_reload
;
1519 /* Comparison function for qsort to decide which of two reloads
1520 should be handled first. *P1 and *P2 are the reload numbers. */
1523 reload_reg_class_lower (r1p
, r2p
)
1527 register int r1
= *(const short *) r1p
, r2
= *(const short *) r2p
;
1530 /* Consider required reloads before optional ones. */
1531 t
= rld
[r1
].optional
- rld
[r2
].optional
;
1535 /* Count all solitary classes before non-solitary ones. */
1536 t
= ((reg_class_size
[(int) rld
[r2
].class] == 1)
1537 - (reg_class_size
[(int) rld
[r1
].class] == 1));
1541 /* Aside from solitaires, consider all multi-reg groups first. */
1542 t
= rld
[r2
].nregs
- rld
[r1
].nregs
;
1546 /* Consider reloads in order of increasing reg-class number. */
1547 t
= (int) rld
[r1
].class - (int) rld
[r2
].class;
1551 /* If reloads are equally urgent, sort by reload number,
1552 so that the results of qsort leave nothing to chance. */
1556 /* The cost of spilling each hard reg. */
1557 static int spill_cost
[FIRST_PSEUDO_REGISTER
];
1559 /* When spilling multiple hard registers, we use SPILL_COST for the first
1560 spilled hard reg and SPILL_ADD_COST for subsequent regs. SPILL_ADD_COST
1561 only the first hard reg for a multi-reg pseudo. */
1562 static int spill_add_cost
[FIRST_PSEUDO_REGISTER
];
1564 /* Update the spill cost arrays, considering that pseudo REG is live. */
1570 int freq
= REG_FREQ (reg
);
1571 int r
= reg_renumber
[reg
];
1574 if (REGNO_REG_SET_P (&pseudos_counted
, reg
)
1575 || REGNO_REG_SET_P (&spilled_pseudos
, reg
))
1578 SET_REGNO_REG_SET (&pseudos_counted
, reg
);
1583 spill_add_cost
[r
] += freq
;
1585 nregs
= HARD_REGNO_NREGS (r
, PSEUDO_REGNO_MODE (reg
));
1587 spill_cost
[r
+ nregs
] += freq
;
1590 /* Calculate the SPILL_COST and SPILL_ADD_COST arrays and determine the
1591 contents of BAD_SPILL_REGS for the insn described by CHAIN. */
1594 order_regs_for_reload (chain
)
1595 struct insn_chain
*chain
;
1598 HARD_REG_SET used_by_pseudos
;
1599 HARD_REG_SET used_by_pseudos2
;
1601 COPY_HARD_REG_SET (bad_spill_regs
, fixed_reg_set
);
1603 memset (spill_cost
, 0, sizeof spill_cost
);
1604 memset (spill_add_cost
, 0, sizeof spill_add_cost
);
1606 /* Count number of uses of each hard reg by pseudo regs allocated to it
1607 and then order them by decreasing use. First exclude hard registers
1608 that are live in or across this insn. */
1610 REG_SET_TO_HARD_REG_SET (used_by_pseudos
, &chain
->live_throughout
);
1611 REG_SET_TO_HARD_REG_SET (used_by_pseudos2
, &chain
->dead_or_set
);
1612 IOR_HARD_REG_SET (bad_spill_regs
, used_by_pseudos
);
1613 IOR_HARD_REG_SET (bad_spill_regs
, used_by_pseudos2
);
1615 /* Now find out which pseudos are allocated to it, and update
1617 CLEAR_REG_SET (&pseudos_counted
);
1619 EXECUTE_IF_SET_IN_REG_SET
1620 (&chain
->live_throughout
, FIRST_PSEUDO_REGISTER
, i
,
1624 EXECUTE_IF_SET_IN_REG_SET
1625 (&chain
->dead_or_set
, FIRST_PSEUDO_REGISTER
, i
,
1629 CLEAR_REG_SET (&pseudos_counted
);
1632 /* Vector of reload-numbers showing the order in which the reloads should
1634 static short reload_order
[MAX_RELOADS
];
1636 /* This is used to keep track of the spill regs used in one insn. */
1637 static HARD_REG_SET used_spill_regs_local
;
1639 /* We decided to spill hard register SPILLED, which has a size of
1640 SPILLED_NREGS. Determine how pseudo REG, which is live during the insn,
1641 is affected. We will add it to SPILLED_PSEUDOS if necessary, and we will
1642 update SPILL_COST/SPILL_ADD_COST. */
1645 count_spilled_pseudo (spilled
, spilled_nregs
, reg
)
1646 int spilled
, spilled_nregs
, reg
;
1648 int r
= reg_renumber
[reg
];
1649 int nregs
= HARD_REGNO_NREGS (r
, PSEUDO_REGNO_MODE (reg
));
1651 if (REGNO_REG_SET_P (&spilled_pseudos
, reg
)
1652 || spilled
+ spilled_nregs
<= r
|| r
+ nregs
<= spilled
)
1655 SET_REGNO_REG_SET (&spilled_pseudos
, reg
);
1657 spill_add_cost
[r
] -= REG_FREQ (reg
);
1659 spill_cost
[r
+ nregs
] -= REG_FREQ (reg
);
1662 /* Find reload register to use for reload number ORDER. */
1665 find_reg (chain
, order
)
1666 struct insn_chain
*chain
;
1669 int rnum
= reload_order
[order
];
1670 struct reload
*rl
= rld
+ rnum
;
1671 int best_cost
= INT_MAX
;
1675 HARD_REG_SET not_usable
;
1676 HARD_REG_SET used_by_other_reload
;
1678 COPY_HARD_REG_SET (not_usable
, bad_spill_regs
);
1679 IOR_HARD_REG_SET (not_usable
, bad_spill_regs_global
);
1680 IOR_COMPL_HARD_REG_SET (not_usable
, reg_class_contents
[rl
->class]);
1682 CLEAR_HARD_REG_SET (used_by_other_reload
);
1683 for (k
= 0; k
< order
; k
++)
1685 int other
= reload_order
[k
];
1687 if (rld
[other
].regno
>= 0 && reloads_conflict (other
, rnum
))
1688 for (j
= 0; j
< rld
[other
].nregs
; j
++)
1689 SET_HARD_REG_BIT (used_by_other_reload
, rld
[other
].regno
+ j
);
1692 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1694 unsigned int regno
= i
;
1696 if (! TEST_HARD_REG_BIT (not_usable
, regno
)
1697 && ! TEST_HARD_REG_BIT (used_by_other_reload
, regno
)
1698 && HARD_REGNO_MODE_OK (regno
, rl
->mode
))
1700 int this_cost
= spill_cost
[regno
];
1702 unsigned int this_nregs
= HARD_REGNO_NREGS (regno
, rl
->mode
);
1704 for (j
= 1; j
< this_nregs
; j
++)
1706 this_cost
+= spill_add_cost
[regno
+ j
];
1707 if ((TEST_HARD_REG_BIT (not_usable
, regno
+ j
))
1708 || TEST_HARD_REG_BIT (used_by_other_reload
, regno
+ j
))
1713 if (rl
->in
&& GET_CODE (rl
->in
) == REG
&& REGNO (rl
->in
) == regno
)
1715 if (rl
->out
&& GET_CODE (rl
->out
) == REG
&& REGNO (rl
->out
) == regno
)
1717 if (this_cost
< best_cost
1718 /* Among registers with equal cost, prefer caller-saved ones, or
1719 use REG_ALLOC_ORDER if it is defined. */
1720 || (this_cost
== best_cost
1721 #ifdef REG_ALLOC_ORDER
1722 && (inv_reg_alloc_order
[regno
]
1723 < inv_reg_alloc_order
[best_reg
])
1725 && call_used_regs
[regno
]
1726 && ! call_used_regs
[best_reg
]
1731 best_cost
= this_cost
;
1739 fprintf (rtl_dump_file
, "Using reg %d for reload %d\n", best_reg
, rnum
);
1741 rl
->nregs
= HARD_REGNO_NREGS (best_reg
, rl
->mode
);
1742 rl
->regno
= best_reg
;
1744 EXECUTE_IF_SET_IN_REG_SET
1745 (&chain
->live_throughout
, FIRST_PSEUDO_REGISTER
, j
,
1747 count_spilled_pseudo (best_reg
, rl
->nregs
, j
);
1750 EXECUTE_IF_SET_IN_REG_SET
1751 (&chain
->dead_or_set
, FIRST_PSEUDO_REGISTER
, j
,
1753 count_spilled_pseudo (best_reg
, rl
->nregs
, j
);
1756 for (i
= 0; i
< rl
->nregs
; i
++)
1758 if (spill_cost
[best_reg
+ i
] != 0
1759 || spill_add_cost
[best_reg
+ i
] != 0)
1761 SET_HARD_REG_BIT (used_spill_regs_local
, best_reg
+ i
);
1766 /* Find more reload regs to satisfy the remaining need of an insn, which
1768 Do it by ascending class number, since otherwise a reg
1769 might be spilled for a big class and might fail to count
1770 for a smaller class even though it belongs to that class. */
1773 find_reload_regs (chain
)
1774 struct insn_chain
*chain
;
1778 /* In order to be certain of getting the registers we need,
1779 we must sort the reloads into order of increasing register class.
1780 Then our grabbing of reload registers will parallel the process
1781 that provided the reload registers. */
1782 for (i
= 0; i
< chain
->n_reloads
; i
++)
1784 /* Show whether this reload already has a hard reg. */
1785 if (chain
->rld
[i
].reg_rtx
)
1787 int regno
= REGNO (chain
->rld
[i
].reg_rtx
);
1788 chain
->rld
[i
].regno
= regno
;
1790 = HARD_REGNO_NREGS (regno
, GET_MODE (chain
->rld
[i
].reg_rtx
));
1793 chain
->rld
[i
].regno
= -1;
1794 reload_order
[i
] = i
;
1797 n_reloads
= chain
->n_reloads
;
1798 memcpy (rld
, chain
->rld
, n_reloads
* sizeof (struct reload
));
1800 CLEAR_HARD_REG_SET (used_spill_regs_local
);
1803 fprintf (rtl_dump_file
, "Spilling for insn %d.\n", INSN_UID (chain
->insn
));
1805 qsort (reload_order
, n_reloads
, sizeof (short), reload_reg_class_lower
);
1807 /* Compute the order of preference for hard registers to spill. */
1809 order_regs_for_reload (chain
);
1811 for (i
= 0; i
< n_reloads
; i
++)
1813 int r
= reload_order
[i
];
1815 /* Ignore reloads that got marked inoperative. */
1816 if ((rld
[r
].out
!= 0 || rld
[r
].in
!= 0 || rld
[r
].secondary_p
)
1817 && ! rld
[r
].optional
1818 && rld
[r
].regno
== -1)
1819 if (! find_reg (chain
, i
))
1821 spill_failure (chain
->insn
, rld
[r
].class);
1827 COPY_HARD_REG_SET (chain
->used_spill_regs
, used_spill_regs_local
);
1828 IOR_HARD_REG_SET (used_spill_regs
, used_spill_regs_local
);
1830 memcpy (chain
->rld
, rld
, n_reloads
* sizeof (struct reload
));
1834 select_reload_regs ()
1836 struct insn_chain
*chain
;
1838 /* Try to satisfy the needs for each insn. */
1839 for (chain
= insns_need_reload
; chain
!= 0;
1840 chain
= chain
->next_need_reload
)
1841 find_reload_regs (chain
);
1844 /* Delete all insns that were inserted by emit_caller_save_insns during
1847 delete_caller_save_insns ()
1849 struct insn_chain
*c
= reload_insn_chain
;
1853 while (c
!= 0 && c
->is_caller_save_insn
)
1855 struct insn_chain
*next
= c
->next
;
1858 if (insn
== BLOCK_HEAD (c
->block
))
1859 BLOCK_HEAD (c
->block
) = NEXT_INSN (insn
);
1860 if (insn
== BLOCK_END (c
->block
))
1861 BLOCK_END (c
->block
) = PREV_INSN (insn
);
1862 if (c
== reload_insn_chain
)
1863 reload_insn_chain
= next
;
1865 if (NEXT_INSN (insn
) != 0)
1866 PREV_INSN (NEXT_INSN (insn
)) = PREV_INSN (insn
);
1867 if (PREV_INSN (insn
) != 0)
1868 NEXT_INSN (PREV_INSN (insn
)) = NEXT_INSN (insn
);
1871 next
->prev
= c
->prev
;
1873 c
->prev
->next
= next
;
1874 c
->next
= unused_insn_chains
;
1875 unused_insn_chains
= c
;
1883 /* Handle the failure to find a register to spill.
1884 INSN should be one of the insns which needed this particular spill reg. */
1887 spill_failure (insn
, class)
1889 enum reg_class
class;
1891 static const char *const reg_class_names
[] = REG_CLASS_NAMES
;
1892 if (asm_noperands (PATTERN (insn
)) >= 0)
1893 error_for_asm (insn
, "Can't find a register in class `%s' while reloading `asm'.",
1894 reg_class_names
[class]);
1897 error ("Unable to find a register to spill in class `%s'.",
1898 reg_class_names
[class]);
1899 fatal_insn ("This is the insn:", insn
);
1903 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
1904 data that is dead in INSN. */
1907 delete_dead_insn (insn
)
1910 rtx prev
= prev_real_insn (insn
);
1913 /* If the previous insn sets a register that dies in our insn, delete it
1915 if (prev
&& GET_CODE (PATTERN (prev
)) == SET
1916 && (prev_dest
= SET_DEST (PATTERN (prev
)), GET_CODE (prev_dest
) == REG
)
1917 && reg_mentioned_p (prev_dest
, PATTERN (insn
))
1918 && find_regno_note (insn
, REG_DEAD
, REGNO (prev_dest
))
1919 && ! side_effects_p (SET_SRC (PATTERN (prev
))))
1920 delete_dead_insn (prev
);
1922 PUT_CODE (insn
, NOTE
);
1923 NOTE_LINE_NUMBER (insn
) = NOTE_INSN_DELETED
;
1924 NOTE_SOURCE_FILE (insn
) = 0;
1927 /* Modify the home of pseudo-reg I.
1928 The new home is present in reg_renumber[I].
1930 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
1931 or it may be -1, meaning there is none or it is not relevant.
1932 This is used so that all pseudos spilled from a given hard reg
1933 can share one stack slot. */
1936 alter_reg (i
, from_reg
)
1940 /* When outputting an inline function, this can happen
1941 for a reg that isn't actually used. */
1942 if (regno_reg_rtx
[i
] == 0)
1945 /* If the reg got changed to a MEM at rtl-generation time,
1947 if (GET_CODE (regno_reg_rtx
[i
]) != REG
)
1950 /* Modify the reg-rtx to contain the new hard reg
1951 number or else to contain its pseudo reg number. */
1952 REGNO (regno_reg_rtx
[i
])
1953 = reg_renumber
[i
] >= 0 ? reg_renumber
[i
] : i
;
1955 /* If we have a pseudo that is needed but has no hard reg or equivalent,
1956 allocate a stack slot for it. */
1958 if (reg_renumber
[i
] < 0
1959 && REG_N_REFS (i
) > 0
1960 && reg_equiv_constant
[i
] == 0
1961 && reg_equiv_memory_loc
[i
] == 0)
1964 unsigned int inherent_size
= PSEUDO_REGNO_BYTES (i
);
1965 unsigned int total_size
= MAX (inherent_size
, reg_max_ref_width
[i
]);
1968 /* Each pseudo reg has an inherent size which comes from its own mode,
1969 and a total size which provides room for paradoxical subregs
1970 which refer to the pseudo reg in wider modes.
1972 We can use a slot already allocated if it provides both
1973 enough inherent space and enough total space.
1974 Otherwise, we allocate a new slot, making sure that it has no less
1975 inherent space, and no less total space, then the previous slot. */
1978 /* No known place to spill from => no slot to reuse. */
1979 x
= assign_stack_local (GET_MODE (regno_reg_rtx
[i
]), total_size
,
1980 inherent_size
== total_size
? 0 : -1);
1981 if (BYTES_BIG_ENDIAN
)
1982 /* Cancel the big-endian correction done in assign_stack_local.
1983 Get the address of the beginning of the slot.
1984 This is so we can do a big-endian correction unconditionally
1986 adjust
= inherent_size
- total_size
;
1988 RTX_UNCHANGING_P (x
) = RTX_UNCHANGING_P (regno_reg_rtx
[i
]);
1990 /* Nothing can alias this slot except this pseudo. */
1991 set_mem_alias_set (x
, new_alias_set ());
1994 /* Reuse a stack slot if possible. */
1995 else if (spill_stack_slot
[from_reg
] != 0
1996 && spill_stack_slot_width
[from_reg
] >= total_size
1997 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot
[from_reg
]))
1999 x
= spill_stack_slot
[from_reg
];
2001 /* Allocate a bigger slot. */
2004 /* Compute maximum size needed, both for inherent size
2005 and for total size. */
2006 enum machine_mode mode
= GET_MODE (regno_reg_rtx
[i
]);
2009 if (spill_stack_slot
[from_reg
])
2011 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot
[from_reg
]))
2013 mode
= GET_MODE (spill_stack_slot
[from_reg
]);
2014 if (spill_stack_slot_width
[from_reg
] > total_size
)
2015 total_size
= spill_stack_slot_width
[from_reg
];
2018 /* Make a slot with that size. */
2019 x
= assign_stack_local (mode
, total_size
,
2020 inherent_size
== total_size
? 0 : -1);
2023 /* All pseudos mapped to this slot can alias each other. */
2024 if (spill_stack_slot
[from_reg
])
2025 set_mem_alias_set (x
, MEM_ALIAS_SET (spill_stack_slot
[from_reg
]));
2027 set_mem_alias_set (x
, new_alias_set ());
2029 if (BYTES_BIG_ENDIAN
)
2031 /* Cancel the big-endian correction done in assign_stack_local.
2032 Get the address of the beginning of the slot.
2033 This is so we can do a big-endian correction unconditionally
2035 adjust
= GET_MODE_SIZE (mode
) - total_size
;
2037 stack_slot
= gen_rtx_MEM (mode_for_size (total_size
2040 plus_constant (XEXP (x
, 0), adjust
));
2043 spill_stack_slot
[from_reg
] = stack_slot
;
2044 spill_stack_slot_width
[from_reg
] = total_size
;
2047 /* On a big endian machine, the "address" of the slot
2048 is the address of the low part that fits its inherent mode. */
2049 if (BYTES_BIG_ENDIAN
&& inherent_size
< total_size
)
2050 adjust
+= (total_size
- inherent_size
);
2052 /* If we have any adjustment to make, or if the stack slot is the
2053 wrong mode, make a new stack slot. */
2054 if (adjust
!= 0 || GET_MODE (x
) != GET_MODE (regno_reg_rtx
[i
]))
2055 x
= adjust_address_nv (x
, GET_MODE (regno_reg_rtx
[i
]), adjust
);
2057 /* Save the stack slot for later. */
2058 reg_equiv_memory_loc
[i
] = x
;
2062 /* Mark the slots in regs_ever_live for the hard regs
2063 used by pseudo-reg number REGNO. */
2066 mark_home_live (regno
)
2069 register int i
, lim
;
2071 i
= reg_renumber
[regno
];
2074 lim
= i
+ HARD_REGNO_NREGS (i
, PSEUDO_REGNO_MODE (regno
));
2076 regs_ever_live
[i
++] = 1;
2079 /* This function handles the tracking of elimination offsets around branches.
2081 X is a piece of RTL being scanned.
2083 INSN is the insn that it came from, if any.
2085 INITIAL_P is non-zero if we are to set the offset to be the initial
2086 offset and zero if we are setting the offset of the label to be the
2090 set_label_offsets (x
, insn
, initial_p
)
2095 enum rtx_code code
= GET_CODE (x
);
2098 struct elim_table
*p
;
2103 if (LABEL_REF_NONLOCAL_P (x
))
2108 /* ... fall through ... */
2111 /* If we know nothing about this label, set the desired offsets. Note
2112 that this sets the offset at a label to be the offset before a label
2113 if we don't know anything about the label. This is not correct for
2114 the label after a BARRIER, but is the best guess we can make. If
2115 we guessed wrong, we will suppress an elimination that might have
2116 been possible had we been able to guess correctly. */
2118 if (! offsets_known_at
[CODE_LABEL_NUMBER (x
)])
2120 for (i
= 0; i
< NUM_ELIMINABLE_REGS
; i
++)
2121 offsets_at
[CODE_LABEL_NUMBER (x
)][i
]
2122 = (initial_p
? reg_eliminate
[i
].initial_offset
2123 : reg_eliminate
[i
].offset
);
2124 offsets_known_at
[CODE_LABEL_NUMBER (x
)] = 1;
2127 /* Otherwise, if this is the definition of a label and it is
2128 preceded by a BARRIER, set our offsets to the known offset of
2132 && (tem
= prev_nonnote_insn (insn
)) != 0
2133 && GET_CODE (tem
) == BARRIER
)
2134 set_offsets_for_label (insn
);
2136 /* If neither of the above cases is true, compare each offset
2137 with those previously recorded and suppress any eliminations
2138 where the offsets disagree. */
2140 for (i
= 0; i
< NUM_ELIMINABLE_REGS
; i
++)
2141 if (offsets_at
[CODE_LABEL_NUMBER (x
)][i
]
2142 != (initial_p
? reg_eliminate
[i
].initial_offset
2143 : reg_eliminate
[i
].offset
))
2144 reg_eliminate
[i
].can_eliminate
= 0;
2149 set_label_offsets (PATTERN (insn
), insn
, initial_p
);
2151 /* ... fall through ... */
2155 /* Any labels mentioned in REG_LABEL notes can be branched to indirectly
2156 and hence must have all eliminations at their initial offsets. */
2157 for (tem
= REG_NOTES (x
); tem
; tem
= XEXP (tem
, 1))
2158 if (REG_NOTE_KIND (tem
) == REG_LABEL
)
2159 set_label_offsets (XEXP (tem
, 0), insn
, 1);
2165 /* Each of the labels in the parallel or address vector must be
2166 at their initial offsets. We want the first field for PARALLEL
2167 and ADDR_VEC and the second field for ADDR_DIFF_VEC. */
2169 for (i
= 0; i
< (unsigned) XVECLEN (x
, code
== ADDR_DIFF_VEC
); i
++)
2170 set_label_offsets (XVECEXP (x
, code
== ADDR_DIFF_VEC
, i
),
2175 /* We only care about setting PC. If the source is not RETURN,
2176 IF_THEN_ELSE, or a label, disable any eliminations not at
2177 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2178 isn't one of those possibilities. For branches to a label,
2179 call ourselves recursively.
2181 Note that this can disable elimination unnecessarily when we have
2182 a non-local goto since it will look like a non-constant jump to
2183 someplace in the current function. This isn't a significant
2184 problem since such jumps will normally be when all elimination
2185 pairs are back to their initial offsets. */
2187 if (SET_DEST (x
) != pc_rtx
)
2190 switch (GET_CODE (SET_SRC (x
)))
2197 set_label_offsets (XEXP (SET_SRC (x
), 0), insn
, initial_p
);
2201 tem
= XEXP (SET_SRC (x
), 1);
2202 if (GET_CODE (tem
) == LABEL_REF
)
2203 set_label_offsets (XEXP (tem
, 0), insn
, initial_p
);
2204 else if (GET_CODE (tem
) != PC
&& GET_CODE (tem
) != RETURN
)
2207 tem
= XEXP (SET_SRC (x
), 2);
2208 if (GET_CODE (tem
) == LABEL_REF
)
2209 set_label_offsets (XEXP (tem
, 0), insn
, initial_p
);
2210 else if (GET_CODE (tem
) != PC
&& GET_CODE (tem
) != RETURN
)
2218 /* If we reach here, all eliminations must be at their initial
2219 offset because we are doing a jump to a variable address. */
2220 for (p
= reg_eliminate
; p
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; p
++)
2221 if (p
->offset
!= p
->initial_offset
)
2222 p
->can_eliminate
= 0;
2230 /* Scan X and replace any eliminable registers (such as fp) with a
2231 replacement (such as sp), plus an offset.
2233 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2234 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2235 MEM, we are allowed to replace a sum of a register and the constant zero
2236 with the register, which we cannot do outside a MEM. In addition, we need
2237 to record the fact that a register is referenced outside a MEM.
2239 If INSN is an insn, it is the insn containing X. If we replace a REG
2240 in a SET_DEST with an equivalent MEM and INSN is non-zero, write a
2241 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2242 the REG is being modified.
2244 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2245 That's used when we eliminate in expressions stored in notes.
2246 This means, do not set ref_outside_mem even if the reference
2249 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2250 replacements done assuming all offsets are at their initial values. If
2251 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2252 encounter, return the actual location so that find_reloads will do
2253 the proper thing. */
2256 eliminate_regs (x
, mem_mode
, insn
)
2258 enum machine_mode mem_mode
;
2261 enum rtx_code code
= GET_CODE (x
);
2262 struct elim_table
*ep
;
2269 if (! current_function_decl
)
2288 /* This is only for the benefit of the debugging backends, which call
2289 eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are
2290 removed after CSE. */
2291 new = eliminate_regs (XEXP (x
, 0), 0, insn
);
2292 if (GET_CODE (new) == MEM
)
2293 return XEXP (new, 0);
2299 /* First handle the case where we encounter a bare register that
2300 is eliminable. Replace it with a PLUS. */
2301 if (regno
< FIRST_PSEUDO_REGISTER
)
2303 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
2305 if (ep
->from_rtx
== x
&& ep
->can_eliminate
)
2306 return plus_constant (ep
->to_rtx
, ep
->previous_offset
);
2309 else if (reg_renumber
[regno
] < 0 && reg_equiv_constant
2310 && reg_equiv_constant
[regno
]
2311 && ! CONSTANT_P (reg_equiv_constant
[regno
]))
2312 return eliminate_regs (copy_rtx (reg_equiv_constant
[regno
]),
2316 /* You might think handling MINUS in a manner similar to PLUS is a
2317 good idea. It is not. It has been tried multiple times and every
2318 time the change has had to have been reverted.
2320 Other parts of reload know a PLUS is special (gen_reload for example)
2321 and require special code to handle code a reloaded PLUS operand.
2323 Also consider backends where the flags register is clobbered by a
2324 MINUS, but we can emit a PLUS that does not clobber flags (ia32,
2325 lea instruction comes to mind). If we try to reload a MINUS, we
2326 may kill the flags register that was holding a useful value.
2328 So, please before trying to handle MINUS, consider reload as a
2329 whole instead of this little section as well as the backend issues. */
2331 /* If this is the sum of an eliminable register and a constant, rework
2333 if (GET_CODE (XEXP (x
, 0)) == REG
2334 && REGNO (XEXP (x
, 0)) < FIRST_PSEUDO_REGISTER
2335 && CONSTANT_P (XEXP (x
, 1)))
2337 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
2339 if (ep
->from_rtx
== XEXP (x
, 0) && ep
->can_eliminate
)
2341 /* The only time we want to replace a PLUS with a REG (this
2342 occurs when the constant operand of the PLUS is the negative
2343 of the offset) is when we are inside a MEM. We won't want
2344 to do so at other times because that would change the
2345 structure of the insn in a way that reload can't handle.
2346 We special-case the commonest situation in
2347 eliminate_regs_in_insn, so just replace a PLUS with a
2348 PLUS here, unless inside a MEM. */
2349 if (mem_mode
!= 0 && GET_CODE (XEXP (x
, 1)) == CONST_INT
2350 && INTVAL (XEXP (x
, 1)) == - ep
->previous_offset
)
2353 return gen_rtx_PLUS (Pmode
, ep
->to_rtx
,
2354 plus_constant (XEXP (x
, 1),
2355 ep
->previous_offset
));
2358 /* If the register is not eliminable, we are done since the other
2359 operand is a constant. */
2363 /* If this is part of an address, we want to bring any constant to the
2364 outermost PLUS. We will do this by doing register replacement in
2365 our operands and seeing if a constant shows up in one of them.
2367 Note that there is no risk of modifying the structure of the insn,
2368 since we only get called for its operands, thus we are either
2369 modifying the address inside a MEM, or something like an address
2370 operand of a load-address insn. */
2373 rtx new0
= eliminate_regs (XEXP (x
, 0), mem_mode
, insn
);
2374 rtx new1
= eliminate_regs (XEXP (x
, 1), mem_mode
, insn
);
2376 if (new0
!= XEXP (x
, 0) || new1
!= XEXP (x
, 1))
2378 /* If one side is a PLUS and the other side is a pseudo that
2379 didn't get a hard register but has a reg_equiv_constant,
2380 we must replace the constant here since it may no longer
2381 be in the position of any operand. */
2382 if (GET_CODE (new0
) == PLUS
&& GET_CODE (new1
) == REG
2383 && REGNO (new1
) >= FIRST_PSEUDO_REGISTER
2384 && reg_renumber
[REGNO (new1
)] < 0
2385 && reg_equiv_constant
!= 0
2386 && reg_equiv_constant
[REGNO (new1
)] != 0)
2387 new1
= reg_equiv_constant
[REGNO (new1
)];
2388 else if (GET_CODE (new1
) == PLUS
&& GET_CODE (new0
) == REG
2389 && REGNO (new0
) >= FIRST_PSEUDO_REGISTER
2390 && reg_renumber
[REGNO (new0
)] < 0
2391 && reg_equiv_constant
[REGNO (new0
)] != 0)
2392 new0
= reg_equiv_constant
[REGNO (new0
)];
2394 new = form_sum (new0
, new1
);
2396 /* As above, if we are not inside a MEM we do not want to
2397 turn a PLUS into something else. We might try to do so here
2398 for an addition of 0 if we aren't optimizing. */
2399 if (! mem_mode
&& GET_CODE (new) != PLUS
)
2400 return gen_rtx_PLUS (GET_MODE (x
), new, const0_rtx
);
2408 /* If this is the product of an eliminable register and a
2409 constant, apply the distribute law and move the constant out
2410 so that we have (plus (mult ..) ..). This is needed in order
2411 to keep load-address insns valid. This case is pathological.
2412 We ignore the possibility of overflow here. */
2413 if (GET_CODE (XEXP (x
, 0)) == REG
2414 && REGNO (XEXP (x
, 0)) < FIRST_PSEUDO_REGISTER
2415 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
2416 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
2418 if (ep
->from_rtx
== XEXP (x
, 0) && ep
->can_eliminate
)
2421 /* Refs inside notes don't count for this purpose. */
2422 && ! (insn
!= 0 && (GET_CODE (insn
) == EXPR_LIST
2423 || GET_CODE (insn
) == INSN_LIST
)))
2424 ep
->ref_outside_mem
= 1;
2427 plus_constant (gen_rtx_MULT (Pmode
, ep
->to_rtx
, XEXP (x
, 1)),
2428 ep
->previous_offset
* INTVAL (XEXP (x
, 1)));
2431 /* ... fall through ... */
2435 /* See comments before PLUS about handling MINUS. */
2437 case DIV
: case UDIV
:
2438 case MOD
: case UMOD
:
2439 case AND
: case IOR
: case XOR
:
2440 case ROTATERT
: case ROTATE
:
2441 case ASHIFTRT
: case LSHIFTRT
: case ASHIFT
:
2443 case GE
: case GT
: case GEU
: case GTU
:
2444 case LE
: case LT
: case LEU
: case LTU
:
2446 rtx new0
= eliminate_regs (XEXP (x
, 0), mem_mode
, insn
);
2448 = XEXP (x
, 1) ? eliminate_regs (XEXP (x
, 1), mem_mode
, insn
) : 0;
2450 if (new0
!= XEXP (x
, 0) || new1
!= XEXP (x
, 1))
2451 return gen_rtx_fmt_ee (code
, GET_MODE (x
), new0
, new1
);
2456 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2459 new = eliminate_regs (XEXP (x
, 0), mem_mode
, insn
);
2460 if (new != XEXP (x
, 0))
2462 /* If this is a REG_DEAD note, it is not valid anymore.
2463 Using the eliminated version could result in creating a
2464 REG_DEAD note for the stack or frame pointer. */
2465 if (GET_MODE (x
) == REG_DEAD
)
2467 ? eliminate_regs (XEXP (x
, 1), mem_mode
, insn
)
2470 x
= gen_rtx_EXPR_LIST (REG_NOTE_KIND (x
), new, XEXP (x
, 1));
2474 /* ... fall through ... */
2477 /* Now do eliminations in the rest of the chain. If this was
2478 an EXPR_LIST, this might result in allocating more memory than is
2479 strictly needed, but it simplifies the code. */
2482 new = eliminate_regs (XEXP (x
, 1), mem_mode
, insn
);
2483 if (new != XEXP (x
, 1))
2484 return gen_rtx_fmt_ee (GET_CODE (x
), GET_MODE (x
), XEXP (x
, 0), new);
2492 case STRICT_LOW_PART
:
2494 case SIGN_EXTEND
: case ZERO_EXTEND
:
2495 case TRUNCATE
: case FLOAT_EXTEND
: case FLOAT_TRUNCATE
:
2496 case FLOAT
: case FIX
:
2497 case UNSIGNED_FIX
: case UNSIGNED_FLOAT
:
2501 new = eliminate_regs (XEXP (x
, 0), mem_mode
, insn
);
2502 if (new != XEXP (x
, 0))
2503 return gen_rtx_fmt_e (code
, GET_MODE (x
), new);
2507 /* Similar to above processing, but preserve SUBREG_BYTE.
2508 Convert (subreg (mem)) to (mem) if not paradoxical.
2509 Also, if we have a non-paradoxical (subreg (pseudo)) and the
2510 pseudo didn't get a hard reg, we must replace this with the
2511 eliminated version of the memory location because push_reloads
2512 may do the replacement in certain circumstances. */
2513 if (GET_CODE (SUBREG_REG (x
)) == REG
2514 && (GET_MODE_SIZE (GET_MODE (x
))
2515 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
2516 && reg_equiv_memory_loc
!= 0
2517 && reg_equiv_memory_loc
[REGNO (SUBREG_REG (x
))] != 0)
2519 new = SUBREG_REG (x
);
2522 new = eliminate_regs (SUBREG_REG (x
), mem_mode
, insn
);
2524 if (new != SUBREG_REG (x
))
2526 int x_size
= GET_MODE_SIZE (GET_MODE (x
));
2527 int new_size
= GET_MODE_SIZE (GET_MODE (new));
2529 if (GET_CODE (new) == MEM
2530 && ((x_size
< new_size
2531 #ifdef WORD_REGISTER_OPERATIONS
2532 /* On these machines, combine can create rtl of the form
2533 (set (subreg:m1 (reg:m2 R) 0) ...)
2534 where m1 < m2, and expects something interesting to
2535 happen to the entire word. Moreover, it will use the
2536 (reg:m2 R) later, expecting all bits to be preserved.
2537 So if the number of words is the same, preserve the
2538 subreg so that push_reloads can see it. */
2539 && ! ((x_size
- 1) / UNITS_PER_WORD
2540 == (new_size
-1 ) / UNITS_PER_WORD
)
2543 || x_size
== new_size
)
2546 int offset
= SUBREG_BYTE (x
);
2547 enum machine_mode mode
= GET_MODE (x
);
2549 PUT_MODE (new, mode
);
2550 XEXP (new, 0) = plus_constant (XEXP (new, 0), offset
);
2554 return gen_rtx_SUBREG (GET_MODE (x
), new, SUBREG_BYTE (x
));
2560 /* This is only for the benefit of the debugging backends, which call
2561 eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are
2562 removed after CSE. */
2563 if (GET_CODE (XEXP (x
, 0)) == ADDRESSOF
)
2564 return eliminate_regs (XEXP (XEXP (x
, 0), 0), 0, insn
);
2566 /* Our only special processing is to pass the mode of the MEM to our
2567 recursive call and copy the flags. While we are here, handle this
2568 case more efficiently. */
2570 replace_equiv_address_nv (x
,
2571 eliminate_regs (XEXP (x
, 0),
2572 GET_MODE (x
), insn
));
2575 /* Handle insn_list USE that a call to a pure function may generate. */
2576 new = eliminate_regs (XEXP (x
, 0), 0, insn
);
2577 if (new != XEXP (x
, 0))
2578 return gen_rtx_USE (GET_MODE (x
), new);
2590 /* Process each of our operands recursively. If any have changed, make a
2592 fmt
= GET_RTX_FORMAT (code
);
2593 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++, fmt
++)
2597 new = eliminate_regs (XEXP (x
, i
), mem_mode
, insn
);
2598 if (new != XEXP (x
, i
) && ! copied
)
2600 rtx new_x
= rtx_alloc (code
);
2602 (sizeof (*new_x
) - sizeof (new_x
->fld
)
2603 + sizeof (new_x
->fld
[0]) * GET_RTX_LENGTH (code
)));
2609 else if (*fmt
== 'E')
2612 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
2614 new = eliminate_regs (XVECEXP (x
, i
, j
), mem_mode
, insn
);
2615 if (new != XVECEXP (x
, i
, j
) && ! copied_vec
)
2617 rtvec new_v
= gen_rtvec_v (XVECLEN (x
, i
),
2621 rtx new_x
= rtx_alloc (code
);
2623 (sizeof (*new_x
) - sizeof (new_x
->fld
)
2624 + (sizeof (new_x
->fld
[0])
2625 * GET_RTX_LENGTH (code
))));
2629 XVEC (x
, i
) = new_v
;
2632 XVECEXP (x
, i
, j
) = new;
2640 /* Scan rtx X for modifications of elimination target registers. Update
2641 the table of eliminables to reflect the changed state. MEM_MODE is
2642 the mode of an enclosing MEM rtx, or VOIDmode if not within a MEM. */
2645 elimination_effects (x
, mem_mode
)
2647 enum machine_mode mem_mode
;
2650 enum rtx_code code
= GET_CODE (x
);
2651 struct elim_table
*ep
;
2677 /* First handle the case where we encounter a bare register that
2678 is eliminable. Replace it with a PLUS. */
2679 if (regno
< FIRST_PSEUDO_REGISTER
)
2681 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
2683 if (ep
->from_rtx
== x
&& ep
->can_eliminate
)
2686 ep
->ref_outside_mem
= 1;
2691 else if (reg_renumber
[regno
] < 0 && reg_equiv_constant
2692 && reg_equiv_constant
[regno
]
2693 && ! CONSTANT_P (reg_equiv_constant
[regno
]))
2694 elimination_effects (reg_equiv_constant
[regno
], mem_mode
);
2703 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
2704 if (ep
->to_rtx
== XEXP (x
, 0))
2706 int size
= GET_MODE_SIZE (mem_mode
);
2708 /* If more bytes than MEM_MODE are pushed, account for them. */
2709 #ifdef PUSH_ROUNDING
2710 if (ep
->to_rtx
== stack_pointer_rtx
)
2711 size
= PUSH_ROUNDING (size
);
2713 if (code
== PRE_DEC
|| code
== POST_DEC
)
2715 else if (code
== PRE_INC
|| code
== POST_INC
)
2717 else if ((code
== PRE_MODIFY
|| code
== POST_MODIFY
)
2718 && GET_CODE (XEXP (x
, 1)) == PLUS
2719 && XEXP (x
, 0) == XEXP (XEXP (x
, 1), 0)
2720 && CONSTANT_P (XEXP (XEXP (x
, 1), 1)))
2721 ep
->offset
-= INTVAL (XEXP (XEXP (x
, 1), 1));
2724 /* These two aren't unary operators. */
2725 if (code
== POST_MODIFY
|| code
== PRE_MODIFY
)
2728 /* Fall through to generic unary operation case. */
2729 case STRICT_LOW_PART
:
2731 case SIGN_EXTEND
: case ZERO_EXTEND
:
2732 case TRUNCATE
: case FLOAT_EXTEND
: case FLOAT_TRUNCATE
:
2733 case FLOAT
: case FIX
:
2734 case UNSIGNED_FIX
: case UNSIGNED_FLOAT
:
2738 elimination_effects (XEXP (x
, 0), mem_mode
);
2742 if (GET_CODE (SUBREG_REG (x
)) == REG
2743 && (GET_MODE_SIZE (GET_MODE (x
))
2744 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
2745 && reg_equiv_memory_loc
!= 0
2746 && reg_equiv_memory_loc
[REGNO (SUBREG_REG (x
))] != 0)
2749 elimination_effects (SUBREG_REG (x
), mem_mode
);
2753 /* If using a register that is the source of an eliminate we still
2754 think can be performed, note it cannot be performed since we don't
2755 know how this register is used. */
2756 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
2757 if (ep
->from_rtx
== XEXP (x
, 0))
2758 ep
->can_eliminate
= 0;
2760 elimination_effects (XEXP (x
, 0), mem_mode
);
2764 /* If clobbering a register that is the replacement register for an
2765 elimination we still think can be performed, note that it cannot
2766 be performed. Otherwise, we need not be concerned about it. */
2767 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
2768 if (ep
->to_rtx
== XEXP (x
, 0))
2769 ep
->can_eliminate
= 0;
2771 elimination_effects (XEXP (x
, 0), mem_mode
);
2775 /* Check for setting a register that we know about. */
2776 if (GET_CODE (SET_DEST (x
)) == REG
)
2778 /* See if this is setting the replacement register for an
2781 If DEST is the hard frame pointer, we do nothing because we
2782 assume that all assignments to the frame pointer are for
2783 non-local gotos and are being done at a time when they are valid
2784 and do not disturb anything else. Some machines want to
2785 eliminate a fake argument pointer (or even a fake frame pointer)
2786 with either the real frame or the stack pointer. Assignments to
2787 the hard frame pointer must not prevent this elimination. */
2789 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
2791 if (ep
->to_rtx
== SET_DEST (x
)
2792 && SET_DEST (x
) != hard_frame_pointer_rtx
)
2794 /* If it is being incremented, adjust the offset. Otherwise,
2795 this elimination can't be done. */
2796 rtx src
= SET_SRC (x
);
2798 if (GET_CODE (src
) == PLUS
2799 && XEXP (src
, 0) == SET_DEST (x
)
2800 && GET_CODE (XEXP (src
, 1)) == CONST_INT
)
2801 ep
->offset
-= INTVAL (XEXP (src
, 1));
2803 ep
->can_eliminate
= 0;
2807 elimination_effects (SET_DEST (x
), 0);
2808 elimination_effects (SET_SRC (x
), 0);
2812 if (GET_CODE (XEXP (x
, 0)) == ADDRESSOF
)
2815 /* Our only special processing is to pass the mode of the MEM to our
2817 elimination_effects (XEXP (x
, 0), GET_MODE (x
));
2824 fmt
= GET_RTX_FORMAT (code
);
2825 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++, fmt
++)
2828 elimination_effects (XEXP (x
, i
), mem_mode
);
2829 else if (*fmt
== 'E')
2830 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
2831 elimination_effects (XVECEXP (x
, i
, j
), mem_mode
);
2835 /* Descend through rtx X and verify that no references to eliminable registers
2836 remain. If any do remain, mark the involved register as not
2840 check_eliminable_occurrences (x
)
2850 code
= GET_CODE (x
);
2852 if (code
== REG
&& REGNO (x
) < FIRST_PSEUDO_REGISTER
)
2854 struct elim_table
*ep
;
2856 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
2857 if (ep
->from_rtx
== x
&& ep
->can_eliminate
)
2858 ep
->can_eliminate
= 0;
2862 fmt
= GET_RTX_FORMAT (code
);
2863 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++, fmt
++)
2866 check_eliminable_occurrences (XEXP (x
, i
));
2867 else if (*fmt
== 'E')
2870 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
2871 check_eliminable_occurrences (XVECEXP (x
, i
, j
));
2876 /* Scan INSN and eliminate all eliminable registers in it.
2878 If REPLACE is nonzero, do the replacement destructively. Also
2879 delete the insn as dead it if it is setting an eliminable register.
2881 If REPLACE is zero, do all our allocations in reload_obstack.
2883 If no eliminations were done and this insn doesn't require any elimination
2884 processing (these are not identical conditions: it might be updating sp,
2885 but not referencing fp; this needs to be seen during reload_as_needed so
2886 that the offset between fp and sp can be taken into consideration), zero
2887 is returned. Otherwise, 1 is returned. */
2890 eliminate_regs_in_insn (insn
, replace
)
2894 int icode
= recog_memoized (insn
);
2895 rtx old_body
= PATTERN (insn
);
2896 int insn_is_asm
= asm_noperands (old_body
) >= 0;
2897 rtx old_set
= single_set (insn
);
2901 rtx substed_operand
[MAX_RECOG_OPERANDS
];
2902 rtx orig_operand
[MAX_RECOG_OPERANDS
];
2903 struct elim_table
*ep
;
2905 if (! insn_is_asm
&& icode
< 0)
2907 if (GET_CODE (PATTERN (insn
)) == USE
2908 || GET_CODE (PATTERN (insn
)) == CLOBBER
2909 || GET_CODE (PATTERN (insn
)) == ADDR_VEC
2910 || GET_CODE (PATTERN (insn
)) == ADDR_DIFF_VEC
2911 || GET_CODE (PATTERN (insn
)) == ASM_INPUT
)
2916 if (old_set
!= 0 && GET_CODE (SET_DEST (old_set
)) == REG
2917 && REGNO (SET_DEST (old_set
)) < FIRST_PSEUDO_REGISTER
)
2919 /* Check for setting an eliminable register. */
2920 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
2921 if (ep
->from_rtx
== SET_DEST (old_set
) && ep
->can_eliminate
)
2923 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
2924 /* If this is setting the frame pointer register to the
2925 hardware frame pointer register and this is an elimination
2926 that will be done (tested above), this insn is really
2927 adjusting the frame pointer downward to compensate for
2928 the adjustment done before a nonlocal goto. */
2929 if (ep
->from
== FRAME_POINTER_REGNUM
2930 && ep
->to
== HARD_FRAME_POINTER_REGNUM
)
2932 rtx src
= SET_SRC (old_set
);
2933 int offset
= 0, ok
= 0;
2934 rtx prev_insn
, prev_set
;
2936 if (src
== ep
->to_rtx
)
2938 else if (GET_CODE (src
) == PLUS
2939 && GET_CODE (XEXP (src
, 0)) == CONST_INT
2940 && XEXP (src
, 1) == ep
->to_rtx
)
2941 offset
= INTVAL (XEXP (src
, 0)), ok
= 1;
2942 else if (GET_CODE (src
) == PLUS
2943 && GET_CODE (XEXP (src
, 1)) == CONST_INT
2944 && XEXP (src
, 0) == ep
->to_rtx
)
2945 offset
= INTVAL (XEXP (src
, 1)), ok
= 1;
2946 else if ((prev_insn
= prev_nonnote_insn (insn
)) != 0
2947 && (prev_set
= single_set (prev_insn
)) != 0
2948 && rtx_equal_p (SET_DEST (prev_set
), src
))
2950 src
= SET_SRC (prev_set
);
2951 if (src
== ep
->to_rtx
)
2953 else if (GET_CODE (src
) == PLUS
2954 && GET_CODE (XEXP (src
, 0)) == CONST_INT
2955 && XEXP (src
, 1) == ep
->to_rtx
)
2956 offset
= INTVAL (XEXP (src
, 0)), ok
= 1;
2957 else if (GET_CODE (src
) == PLUS
2958 && GET_CODE (XEXP (src
, 1)) == CONST_INT
2959 && XEXP (src
, 0) == ep
->to_rtx
)
2960 offset
= INTVAL (XEXP (src
, 1)), ok
= 1;
2966 = plus_constant (ep
->to_rtx
, offset
- ep
->offset
);
2968 new_body
= old_body
;
2971 new_body
= copy_insn (old_body
);
2972 if (REG_NOTES (insn
))
2973 REG_NOTES (insn
) = copy_insn_1 (REG_NOTES (insn
));
2975 PATTERN (insn
) = new_body
;
2976 old_set
= single_set (insn
);
2978 /* First see if this insn remains valid when we
2979 make the change. If not, keep the INSN_CODE
2980 the same and let reload fit it up. */
2981 validate_change (insn
, &SET_SRC (old_set
), src
, 1);
2982 validate_change (insn
, &SET_DEST (old_set
),
2984 if (! apply_change_group ())
2986 SET_SRC (old_set
) = src
;
2987 SET_DEST (old_set
) = ep
->to_rtx
;
2996 /* In this case this insn isn't serving a useful purpose. We
2997 will delete it in reload_as_needed once we know that this
2998 elimination is, in fact, being done.
3000 If REPLACE isn't set, we can't delete this insn, but needn't
3001 process it since it won't be used unless something changes. */
3004 delete_dead_insn (insn
);
3012 /* We allow one special case which happens to work on all machines we
3013 currently support: a single set with the source being a PLUS of an
3014 eliminable register and a constant. */
3016 && GET_CODE (SET_DEST (old_set
)) == REG
3017 && GET_CODE (SET_SRC (old_set
)) == PLUS
3018 && GET_CODE (XEXP (SET_SRC (old_set
), 0)) == REG
3019 && GET_CODE (XEXP (SET_SRC (old_set
), 1)) == CONST_INT
3020 && REGNO (XEXP (SET_SRC (old_set
), 0)) < FIRST_PSEUDO_REGISTER
)
3022 rtx reg
= XEXP (SET_SRC (old_set
), 0);
3023 int offset
= INTVAL (XEXP (SET_SRC (old_set
), 1));
3025 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3026 if (ep
->from_rtx
== reg
&& ep
->can_eliminate
)
3028 offset
+= ep
->offset
;
3033 /* We assume here that if we need a PARALLEL with
3034 CLOBBERs for this assignment, we can do with the
3035 MATCH_SCRATCHes that add_clobbers allocates.
3036 There's not much we can do if that doesn't work. */
3037 PATTERN (insn
) = gen_rtx_SET (VOIDmode
,
3041 INSN_CODE (insn
) = recog (PATTERN (insn
), insn
, &num_clobbers
);
3044 rtvec vec
= rtvec_alloc (num_clobbers
+ 1);
3046 vec
->elem
[0] = PATTERN (insn
);
3047 PATTERN (insn
) = gen_rtx_PARALLEL (VOIDmode
, vec
);
3048 add_clobbers (PATTERN (insn
), INSN_CODE (insn
));
3050 if (INSN_CODE (insn
) < 0)
3055 new_body
= old_body
;
3058 new_body
= copy_insn (old_body
);
3059 if (REG_NOTES (insn
))
3060 REG_NOTES (insn
) = copy_insn_1 (REG_NOTES (insn
));
3062 PATTERN (insn
) = new_body
;
3063 old_set
= single_set (insn
);
3065 XEXP (SET_SRC (old_set
), 0) = ep
->to_rtx
;
3066 XEXP (SET_SRC (old_set
), 1) = GEN_INT (offset
);
3069 /* This can't have an effect on elimination offsets, so skip right
3075 /* Determine the effects of this insn on elimination offsets. */
3076 elimination_effects (old_body
, 0);
3078 /* Eliminate all eliminable registers occurring in operands that
3079 can be handled by reload. */
3080 extract_insn (insn
);
3082 for (i
= 0; i
< recog_data
.n_operands
; i
++)
3084 orig_operand
[i
] = recog_data
.operand
[i
];
3085 substed_operand
[i
] = recog_data
.operand
[i
];
3087 /* For an asm statement, every operand is eliminable. */
3088 if (insn_is_asm
|| insn_data
[icode
].operand
[i
].eliminable
)
3090 /* Check for setting a register that we know about. */
3091 if (recog_data
.operand_type
[i
] != OP_IN
3092 && GET_CODE (orig_operand
[i
]) == REG
)
3094 /* If we are assigning to a register that can be eliminated, it
3095 must be as part of a PARALLEL, since the code above handles
3096 single SETs. We must indicate that we can no longer
3097 eliminate this reg. */
3098 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
3100 if (ep
->from_rtx
== orig_operand
[i
] && ep
->can_eliminate
)
3101 ep
->can_eliminate
= 0;
3104 substed_operand
[i
] = eliminate_regs (recog_data
.operand
[i
], 0,
3105 replace
? insn
: NULL_RTX
);
3106 if (substed_operand
[i
] != orig_operand
[i
])
3107 val
= any_changes
= 1;
3108 /* Terminate the search in check_eliminable_occurrences at
3110 *recog_data
.operand_loc
[i
] = 0;
3112 /* If an output operand changed from a REG to a MEM and INSN is an
3113 insn, write a CLOBBER insn. */
3114 if (recog_data
.operand_type
[i
] != OP_IN
3115 && GET_CODE (orig_operand
[i
]) == REG
3116 && GET_CODE (substed_operand
[i
]) == MEM
3118 emit_insn_after (gen_rtx_CLOBBER (VOIDmode
, orig_operand
[i
]),
3123 for (i
= 0; i
< recog_data
.n_dups
; i
++)
3124 *recog_data
.dup_loc
[i
]
3125 = *recog_data
.operand_loc
[(int) recog_data
.dup_num
[i
]];
3127 /* If any eliminable remain, they aren't eliminable anymore. */
3128 check_eliminable_occurrences (old_body
);
3130 /* Substitute the operands; the new values are in the substed_operand
3132 for (i
= 0; i
< recog_data
.n_operands
; i
++)
3133 *recog_data
.operand_loc
[i
] = substed_operand
[i
];
3134 for (i
= 0; i
< recog_data
.n_dups
; i
++)
3135 *recog_data
.dup_loc
[i
] = substed_operand
[(int) recog_data
.dup_num
[i
]];
3137 /* If we are replacing a body that was a (set X (plus Y Z)), try to
3138 re-recognize the insn. We do this in case we had a simple addition
3139 but now can do this as a load-address. This saves an insn in this
3141 If re-recognition fails, the old insn code number will still be used,
3142 and some register operands may have changed into PLUS expressions.
3143 These will be handled by find_reloads by loading them into a register
3148 /* If we aren't replacing things permanently and we changed something,
3149 make another copy to ensure that all the RTL is new. Otherwise
3150 things can go wrong if find_reload swaps commutative operands
3151 and one is inside RTL that has been copied while the other is not. */
3152 new_body
= old_body
;
3155 new_body
= copy_insn (old_body
);
3156 if (REG_NOTES (insn
))
3157 REG_NOTES (insn
) = copy_insn_1 (REG_NOTES (insn
));
3159 PATTERN (insn
) = new_body
;
3161 /* If we had a move insn but now we don't, rerecognize it. This will
3162 cause spurious re-recognition if the old move had a PARALLEL since
3163 the new one still will, but we can't call single_set without
3164 having put NEW_BODY into the insn and the re-recognition won't
3165 hurt in this rare case. */
3166 /* ??? Why this huge if statement - why don't we just rerecognize the
3170 && ((GET_CODE (SET_SRC (old_set
)) == REG
3171 && (GET_CODE (new_body
) != SET
3172 || GET_CODE (SET_SRC (new_body
)) != REG
))
3173 /* If this was a load from or store to memory, compare
3174 the MEM in recog_data.operand to the one in the insn.
3175 If they are not equal, then rerecognize the insn. */
3177 && ((GET_CODE (SET_SRC (old_set
)) == MEM
3178 && SET_SRC (old_set
) != recog_data
.operand
[1])
3179 || (GET_CODE (SET_DEST (old_set
)) == MEM
3180 && SET_DEST (old_set
) != recog_data
.operand
[0])))
3181 /* If this was an add insn before, rerecognize. */
3182 || GET_CODE (SET_SRC (old_set
)) == PLUS
))
3184 int new_icode
= recog (PATTERN (insn
), insn
, 0);
3186 INSN_CODE (insn
) = icode
;
3190 /* Restore the old body. If there were any changes to it, we made a copy
3191 of it while the changes were still in place, so we'll correctly return
3192 a modified insn below. */
3195 /* Restore the old body. */
3196 for (i
= 0; i
< recog_data
.n_operands
; i
++)
3197 *recog_data
.operand_loc
[i
] = orig_operand
[i
];
3198 for (i
= 0; i
< recog_data
.n_dups
; i
++)
3199 *recog_data
.dup_loc
[i
] = orig_operand
[(int) recog_data
.dup_num
[i
]];
3202 /* Update all elimination pairs to reflect the status after the current
3203 insn. The changes we make were determined by the earlier call to
3204 elimination_effects.
3206 We also detect a cases where register elimination cannot be done,
3207 namely, if a register would be both changed and referenced outside a MEM
3208 in the resulting insn since such an insn is often undefined and, even if
3209 not, we cannot know what meaning will be given to it. Note that it is
3210 valid to have a register used in an address in an insn that changes it
3211 (presumably with a pre- or post-increment or decrement).
3213 If anything changes, return nonzero. */
3215 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3217 if (ep
->previous_offset
!= ep
->offset
&& ep
->ref_outside_mem
)
3218 ep
->can_eliminate
= 0;
3220 ep
->ref_outside_mem
= 0;
3222 if (ep
->previous_offset
!= ep
->offset
)
3227 /* If we changed something, perform elimination in REG_NOTES. This is
3228 needed even when REPLACE is zero because a REG_DEAD note might refer
3229 to a register that we eliminate and could cause a different number
3230 of spill registers to be needed in the final reload pass than in
3232 if (val
&& REG_NOTES (insn
) != 0)
3233 REG_NOTES (insn
) = eliminate_regs (REG_NOTES (insn
), 0, REG_NOTES (insn
));
3238 /* Loop through all elimination pairs.
3239 Recalculate the number not at initial offset.
3241 Compute the maximum offset (minimum offset if the stack does not
3242 grow downward) for each elimination pair. */
3245 update_eliminable_offsets ()
3247 struct elim_table
*ep
;
3249 num_not_at_initial_offset
= 0;
3250 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3252 ep
->previous_offset
= ep
->offset
;
3253 if (ep
->can_eliminate
&& ep
->offset
!= ep
->initial_offset
)
3254 num_not_at_initial_offset
++;
3258 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3259 replacement we currently believe is valid, mark it as not eliminable if X
3260 modifies DEST in any way other than by adding a constant integer to it.
3262 If DEST is the frame pointer, we do nothing because we assume that
3263 all assignments to the hard frame pointer are nonlocal gotos and are being
3264 done at a time when they are valid and do not disturb anything else.
3265 Some machines want to eliminate a fake argument pointer with either the
3266 frame or stack pointer. Assignments to the hard frame pointer must not
3267 prevent this elimination.
3269 Called via note_stores from reload before starting its passes to scan
3270 the insns of the function. */
3273 mark_not_eliminable (dest
, x
, data
)
3276 void *data ATTRIBUTE_UNUSED
;
3278 register unsigned int i
;
3280 /* A SUBREG of a hard register here is just changing its mode. We should
3281 not see a SUBREG of an eliminable hard register, but check just in
3283 if (GET_CODE (dest
) == SUBREG
)
3284 dest
= SUBREG_REG (dest
);
3286 if (dest
== hard_frame_pointer_rtx
)
3289 for (i
= 0; i
< NUM_ELIMINABLE_REGS
; i
++)
3290 if (reg_eliminate
[i
].can_eliminate
&& dest
== reg_eliminate
[i
].to_rtx
3291 && (GET_CODE (x
) != SET
3292 || GET_CODE (SET_SRC (x
)) != PLUS
3293 || XEXP (SET_SRC (x
), 0) != dest
3294 || GET_CODE (XEXP (SET_SRC (x
), 1)) != CONST_INT
))
3296 reg_eliminate
[i
].can_eliminate_previous
3297 = reg_eliminate
[i
].can_eliminate
= 0;
3302 /* Verify that the initial elimination offsets did not change since the
3303 last call to set_initial_elim_offsets. This is used to catch cases
3304 where something illegal happened during reload_as_needed that could
3305 cause incorrect code to be generated if we did not check for it. */
3308 verify_initial_elim_offsets ()
3312 #ifdef ELIMINABLE_REGS
3313 struct elim_table
*ep
;
3315 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3317 INITIAL_ELIMINATION_OFFSET (ep
->from
, ep
->to
, t
);
3318 if (t
!= ep
->initial_offset
)
3322 INITIAL_FRAME_POINTER_OFFSET (t
);
3323 if (t
!= reg_eliminate
[0].initial_offset
)
3328 /* Reset all offsets on eliminable registers to their initial values. */
3331 set_initial_elim_offsets ()
3333 struct elim_table
*ep
= reg_eliminate
;
3335 #ifdef ELIMINABLE_REGS
3336 for (; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3338 INITIAL_ELIMINATION_OFFSET (ep
->from
, ep
->to
, ep
->initial_offset
);
3339 ep
->previous_offset
= ep
->offset
= ep
->initial_offset
;
3342 INITIAL_FRAME_POINTER_OFFSET (ep
->initial_offset
);
3343 ep
->previous_offset
= ep
->offset
= ep
->initial_offset
;
3346 num_not_at_initial_offset
= 0;
3349 /* Initialize the known label offsets.
3350 Set a known offset for each forced label to be at the initial offset
3351 of each elimination. We do this because we assume that all
3352 computed jumps occur from a location where each elimination is
3353 at its initial offset.
3354 For all other labels, show that we don't know the offsets. */
3357 set_initial_label_offsets ()
3360 memset ((char *) &offsets_known_at
[get_first_label_num ()], 0, num_labels
);
3362 for (x
= forced_labels
; x
; x
= XEXP (x
, 1))
3364 set_label_offsets (XEXP (x
, 0), NULL_RTX
, 1);
3367 /* Set all elimination offsets to the known values for the code label given
3371 set_offsets_for_label (insn
)
3375 int label_nr
= CODE_LABEL_NUMBER (insn
);
3376 struct elim_table
*ep
;
3378 num_not_at_initial_offset
= 0;
3379 for (i
= 0, ep
= reg_eliminate
; i
< NUM_ELIMINABLE_REGS
; ep
++, i
++)
3381 ep
->offset
= ep
->previous_offset
= offsets_at
[label_nr
][i
];
3382 if (ep
->can_eliminate
&& ep
->offset
!= ep
->initial_offset
)
3383 num_not_at_initial_offset
++;
3387 /* See if anything that happened changes which eliminations are valid.
3388 For example, on the Sparc, whether or not the frame pointer can
3389 be eliminated can depend on what registers have been used. We need
3390 not check some conditions again (such as flag_omit_frame_pointer)
3391 since they can't have changed. */
3394 update_eliminables (pset
)
3397 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3398 int previous_frame_pointer_needed
= frame_pointer_needed
;
3400 struct elim_table
*ep
;
3402 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3403 if ((ep
->from
== HARD_FRAME_POINTER_REGNUM
&& FRAME_POINTER_REQUIRED
)
3404 #ifdef ELIMINABLE_REGS
3405 || ! CAN_ELIMINATE (ep
->from
, ep
->to
)
3408 ep
->can_eliminate
= 0;
3410 /* Look for the case where we have discovered that we can't replace
3411 register A with register B and that means that we will now be
3412 trying to replace register A with register C. This means we can
3413 no longer replace register C with register B and we need to disable
3414 such an elimination, if it exists. This occurs often with A == ap,
3415 B == sp, and C == fp. */
3417 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3419 struct elim_table
*op
;
3420 register int new_to
= -1;
3422 if (! ep
->can_eliminate
&& ep
->can_eliminate_previous
)
3424 /* Find the current elimination for ep->from, if there is a
3426 for (op
= reg_eliminate
;
3427 op
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; op
++)
3428 if (op
->from
== ep
->from
&& op
->can_eliminate
)
3434 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
3436 for (op
= reg_eliminate
;
3437 op
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; op
++)
3438 if (op
->from
== new_to
&& op
->to
== ep
->to
)
3439 op
->can_eliminate
= 0;
3443 /* See if any registers that we thought we could eliminate the previous
3444 time are no longer eliminable. If so, something has changed and we
3445 must spill the register. Also, recompute the number of eliminable
3446 registers and see if the frame pointer is needed; it is if there is
3447 no elimination of the frame pointer that we can perform. */
3449 frame_pointer_needed
= 1;
3450 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3452 if (ep
->can_eliminate
&& ep
->from
== FRAME_POINTER_REGNUM
3453 && ep
->to
!= HARD_FRAME_POINTER_REGNUM
)
3454 frame_pointer_needed
= 0;
3456 if (! ep
->can_eliminate
&& ep
->can_eliminate_previous
)
3458 ep
->can_eliminate_previous
= 0;
3459 SET_HARD_REG_BIT (*pset
, ep
->from
);
3464 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3465 /* If we didn't need a frame pointer last time, but we do now, spill
3466 the hard frame pointer. */
3467 if (frame_pointer_needed
&& ! previous_frame_pointer_needed
)
3468 SET_HARD_REG_BIT (*pset
, HARD_FRAME_POINTER_REGNUM
);
3472 /* Initialize the table of registers to eliminate. */
3477 struct elim_table
*ep
;
3478 #ifdef ELIMINABLE_REGS
3479 struct elim_table_1
*ep1
;
3483 reg_eliminate
= (struct elim_table
*)
3484 xcalloc (sizeof (struct elim_table
), NUM_ELIMINABLE_REGS
);
3486 /* Does this function require a frame pointer? */
3488 frame_pointer_needed
= (! flag_omit_frame_pointer
3489 #ifdef EXIT_IGNORE_STACK
3490 /* ?? If EXIT_IGNORE_STACK is set, we will not save
3491 and restore sp for alloca. So we can't eliminate
3492 the frame pointer in that case. At some point,
3493 we should improve this by emitting the
3494 sp-adjusting insns for this case. */
3495 || (current_function_calls_alloca
3496 && EXIT_IGNORE_STACK
)
3498 || FRAME_POINTER_REQUIRED
);
3502 #ifdef ELIMINABLE_REGS
3503 for (ep
= reg_eliminate
, ep1
= reg_eliminate_1
;
3504 ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++, ep1
++)
3506 ep
->from
= ep1
->from
;
3508 ep
->can_eliminate
= ep
->can_eliminate_previous
3509 = (CAN_ELIMINATE (ep
->from
, ep
->to
)
3510 && ! (ep
->to
== STACK_POINTER_REGNUM
&& frame_pointer_needed
));
3513 reg_eliminate
[0].from
= reg_eliminate_1
[0].from
;
3514 reg_eliminate
[0].to
= reg_eliminate_1
[0].to
;
3515 reg_eliminate
[0].can_eliminate
= reg_eliminate
[0].can_eliminate_previous
3516 = ! frame_pointer_needed
;
3519 /* Count the number of eliminable registers and build the FROM and TO
3520 REG rtx's. Note that code in gen_rtx will cause, e.g.,
3521 gen_rtx (REG, Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
3522 We depend on this. */
3523 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3525 num_eliminable
+= ep
->can_eliminate
;
3526 ep
->from_rtx
= gen_rtx_REG (Pmode
, ep
->from
);
3527 ep
->to_rtx
= gen_rtx_REG (Pmode
, ep
->to
);
3531 /* Kick all pseudos out of hard register REGNO.
3533 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
3534 because we found we can't eliminate some register. In the case, no pseudos
3535 are allowed to be in the register, even if they are only in a block that
3536 doesn't require spill registers, unlike the case when we are spilling this
3537 hard reg to produce another spill register.
3539 Return nonzero if any pseudos needed to be kicked out. */
3542 spill_hard_reg (regno
, cant_eliminate
)
3550 SET_HARD_REG_BIT (bad_spill_regs_global
, regno
);
3551 regs_ever_live
[regno
] = 1;
3554 /* Spill every pseudo reg that was allocated to this reg
3555 or to something that overlaps this reg. */
3557 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
3558 if (reg_renumber
[i
] >= 0
3559 && (unsigned int) reg_renumber
[i
] <= regno
3560 && ((unsigned int) reg_renumber
[i
]
3561 + HARD_REGNO_NREGS ((unsigned int) reg_renumber
[i
],
3562 PSEUDO_REGNO_MODE (i
))
3564 SET_REGNO_REG_SET (&spilled_pseudos
, i
);
3567 /* I'm getting weird preprocessor errors if I use IOR_HARD_REG_SET
3568 from within EXECUTE_IF_SET_IN_REG_SET. Hence this awkwardness. */
3571 ior_hard_reg_set (set1
, set2
)
3572 HARD_REG_SET
*set1
, *set2
;
3574 IOR_HARD_REG_SET (*set1
, *set2
);
3577 /* After find_reload_regs has been run for all insn that need reloads,
3578 and/or spill_hard_regs was called, this function is used to actually
3579 spill pseudo registers and try to reallocate them. It also sets up the
3580 spill_regs array for use by choose_reload_regs. */
3583 finish_spills (global
)
3586 struct insn_chain
*chain
;
3587 int something_changed
= 0;
3590 /* Build the spill_regs array for the function. */
3591 /* If there are some registers still to eliminate and one of the spill regs
3592 wasn't ever used before, additional stack space may have to be
3593 allocated to store this register. Thus, we may have changed the offset
3594 between the stack and frame pointers, so mark that something has changed.
3596 One might think that we need only set VAL to 1 if this is a call-used
3597 register. However, the set of registers that must be saved by the
3598 prologue is not identical to the call-used set. For example, the
3599 register used by the call insn for the return PC is a call-used register,
3600 but must be saved by the prologue. */
3603 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
3604 if (TEST_HARD_REG_BIT (used_spill_regs
, i
))
3606 spill_reg_order
[i
] = n_spills
;
3607 spill_regs
[n_spills
++] = i
;
3608 if (num_eliminable
&& ! regs_ever_live
[i
])
3609 something_changed
= 1;
3610 regs_ever_live
[i
] = 1;
3613 spill_reg_order
[i
] = -1;
3615 EXECUTE_IF_SET_IN_REG_SET
3616 (&spilled_pseudos
, FIRST_PSEUDO_REGISTER
, i
,
3618 /* Record the current hard register the pseudo is allocated to in
3619 pseudo_previous_regs so we avoid reallocating it to the same
3620 hard reg in a later pass. */
3621 if (reg_renumber
[i
] < 0)
3624 SET_HARD_REG_BIT (pseudo_previous_regs
[i
], reg_renumber
[i
]);
3625 /* Mark it as no longer having a hard register home. */
3626 reg_renumber
[i
] = -1;
3627 /* We will need to scan everything again. */
3628 something_changed
= 1;
3631 /* Retry global register allocation if possible. */
3634 memset ((char *) pseudo_forbidden_regs
, 0, max_regno
* sizeof (HARD_REG_SET
));
3635 /* For every insn that needs reloads, set the registers used as spill
3636 regs in pseudo_forbidden_regs for every pseudo live across the
3638 for (chain
= insns_need_reload
; chain
; chain
= chain
->next_need_reload
)
3640 EXECUTE_IF_SET_IN_REG_SET
3641 (&chain
->live_throughout
, FIRST_PSEUDO_REGISTER
, i
,
3643 ior_hard_reg_set (pseudo_forbidden_regs
+ i
,
3644 &chain
->used_spill_regs
);
3646 EXECUTE_IF_SET_IN_REG_SET
3647 (&chain
->dead_or_set
, FIRST_PSEUDO_REGISTER
, i
,
3649 ior_hard_reg_set (pseudo_forbidden_regs
+ i
,
3650 &chain
->used_spill_regs
);
3654 /* Retry allocating the spilled pseudos. For each reg, merge the
3655 various reg sets that indicate which hard regs can't be used,
3656 and call retry_global_alloc.
3657 We change spill_pseudos here to only contain pseudos that did not
3658 get a new hard register. */
3659 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
3660 if (reg_old_renumber
[i
] != reg_renumber
[i
])
3662 HARD_REG_SET forbidden
;
3663 COPY_HARD_REG_SET (forbidden
, bad_spill_regs_global
);
3664 IOR_HARD_REG_SET (forbidden
, pseudo_forbidden_regs
[i
]);
3665 IOR_HARD_REG_SET (forbidden
, pseudo_previous_regs
[i
]);
3666 retry_global_alloc (i
, forbidden
);
3667 if (reg_renumber
[i
] >= 0)
3668 CLEAR_REGNO_REG_SET (&spilled_pseudos
, i
);
3672 /* Fix up the register information in the insn chain.
3673 This involves deleting those of the spilled pseudos which did not get
3674 a new hard register home from the live_{before,after} sets. */
3675 for (chain
= reload_insn_chain
; chain
; chain
= chain
->next
)
3677 HARD_REG_SET used_by_pseudos
;
3678 HARD_REG_SET used_by_pseudos2
;
3680 AND_COMPL_REG_SET (&chain
->live_throughout
, &spilled_pseudos
);
3681 AND_COMPL_REG_SET (&chain
->dead_or_set
, &spilled_pseudos
);
3683 /* Mark any unallocated hard regs as available for spills. That
3684 makes inheritance work somewhat better. */
3685 if (chain
->need_reload
)
3687 REG_SET_TO_HARD_REG_SET (used_by_pseudos
, &chain
->live_throughout
);
3688 REG_SET_TO_HARD_REG_SET (used_by_pseudos2
, &chain
->dead_or_set
);
3689 IOR_HARD_REG_SET (used_by_pseudos
, used_by_pseudos2
);
3691 /* Save the old value for the sanity test below. */
3692 COPY_HARD_REG_SET (used_by_pseudos2
, chain
->used_spill_regs
);
3694 compute_use_by_pseudos (&used_by_pseudos
, &chain
->live_throughout
);
3695 compute_use_by_pseudos (&used_by_pseudos
, &chain
->dead_or_set
);
3696 COMPL_HARD_REG_SET (chain
->used_spill_regs
, used_by_pseudos
);
3697 AND_HARD_REG_SET (chain
->used_spill_regs
, used_spill_regs
);
3699 /* Make sure we only enlarge the set. */
3700 GO_IF_HARD_REG_SUBSET (used_by_pseudos2
, chain
->used_spill_regs
, ok
);
3706 /* Let alter_reg modify the reg rtx's for the modified pseudos. */
3707 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
3709 int regno
= reg_renumber
[i
];
3710 if (reg_old_renumber
[i
] == regno
)
3713 alter_reg (i
, reg_old_renumber
[i
]);
3714 reg_old_renumber
[i
] = regno
;
3718 fprintf (rtl_dump_file
, " Register %d now on stack.\n\n", i
);
3720 fprintf (rtl_dump_file
, " Register %d now in %d.\n\n",
3721 i
, reg_renumber
[i
]);
3725 return something_changed
;
3728 /* Find all paradoxical subregs within X and update reg_max_ref_width.
3729 Also mark any hard registers used to store user variables as
3730 forbidden from being used for spill registers. */
3733 scan_paradoxical_subregs (x
)
3737 register const char *fmt
;
3738 register enum rtx_code code
= GET_CODE (x
);
3744 if (SMALL_REGISTER_CLASSES
&& REGNO (x
) < FIRST_PSEUDO_REGISTER
3745 && REG_USERVAR_P (x
))
3746 SET_HARD_REG_BIT (bad_spill_regs_global
, REGNO (x
));
3762 if (GET_CODE (SUBREG_REG (x
)) == REG
3763 && GET_MODE_SIZE (GET_MODE (x
)) > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
3764 reg_max_ref_width
[REGNO (SUBREG_REG (x
))]
3765 = GET_MODE_SIZE (GET_MODE (x
));
3772 fmt
= GET_RTX_FORMAT (code
);
3773 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
3776 scan_paradoxical_subregs (XEXP (x
, i
));
3777 else if (fmt
[i
] == 'E')
3780 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3781 scan_paradoxical_subregs (XVECEXP (x
, i
, j
));
3786 /* Reload pseudo-registers into hard regs around each insn as needed.
3787 Additional register load insns are output before the insn that needs it
3788 and perhaps store insns after insns that modify the reloaded pseudo reg.
3790 reg_last_reload_reg and reg_reloaded_contents keep track of
3791 which registers are already available in reload registers.
3792 We update these for the reloads that we perform,
3793 as the insns are scanned. */
3796 reload_as_needed (live_known
)
3799 struct insn_chain
*chain
;
3800 #if defined (AUTO_INC_DEC)
3805 memset ((char *) spill_reg_rtx
, 0, sizeof spill_reg_rtx
);
3806 memset ((char *) spill_reg_store
, 0, sizeof spill_reg_store
);
3807 reg_last_reload_reg
= (rtx
*) xcalloc (max_regno
, sizeof (rtx
));
3808 reg_has_output_reload
= (char *) xmalloc (max_regno
);
3809 CLEAR_HARD_REG_SET (reg_reloaded_valid
);
3811 set_initial_elim_offsets ();
3813 for (chain
= reload_insn_chain
; chain
; chain
= chain
->next
)
3816 rtx insn
= chain
->insn
;
3817 rtx old_next
= NEXT_INSN (insn
);
3819 /* If we pass a label, copy the offsets from the label information
3820 into the current offsets of each elimination. */
3821 if (GET_CODE (insn
) == CODE_LABEL
)
3822 set_offsets_for_label (insn
);
3824 else if (INSN_P (insn
))
3826 rtx oldpat
= PATTERN (insn
);
3828 /* If this is a USE and CLOBBER of a MEM, ensure that any
3829 references to eliminable registers have been removed. */
3831 if ((GET_CODE (PATTERN (insn
)) == USE
3832 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
3833 && GET_CODE (XEXP (PATTERN (insn
), 0)) == MEM
)
3834 XEXP (XEXP (PATTERN (insn
), 0), 0)
3835 = eliminate_regs (XEXP (XEXP (PATTERN (insn
), 0), 0),
3836 GET_MODE (XEXP (PATTERN (insn
), 0)),
3839 /* If we need to do register elimination processing, do so.
3840 This might delete the insn, in which case we are done. */
3841 if ((num_eliminable
|| num_eliminable_invariants
) && chain
->need_elim
)
3843 eliminate_regs_in_insn (insn
, 1);
3844 if (GET_CODE (insn
) == NOTE
)
3846 update_eliminable_offsets ();
3851 /* If need_elim is nonzero but need_reload is zero, one might think
3852 that we could simply set n_reloads to 0. However, find_reloads
3853 could have done some manipulation of the insn (such as swapping
3854 commutative operands), and these manipulations are lost during
3855 the first pass for every insn that needs register elimination.
3856 So the actions of find_reloads must be redone here. */
3858 if (! chain
->need_elim
&& ! chain
->need_reload
3859 && ! chain
->need_operand_change
)
3861 /* First find the pseudo regs that must be reloaded for this insn.
3862 This info is returned in the tables reload_... (see reload.h).
3863 Also modify the body of INSN by substituting RELOAD
3864 rtx's for those pseudo regs. */
3867 memset (reg_has_output_reload
, 0, max_regno
);
3868 CLEAR_HARD_REG_SET (reg_is_output_reload
);
3870 find_reloads (insn
, 1, spill_indirect_levels
, live_known
,
3876 rtx next
= NEXT_INSN (insn
);
3879 prev
= PREV_INSN (insn
);
3881 /* Now compute which reload regs to reload them into. Perhaps
3882 reusing reload regs from previous insns, or else output
3883 load insns to reload them. Maybe output store insns too.
3884 Record the choices of reload reg in reload_reg_rtx. */
3885 choose_reload_regs (chain
);
3887 /* Merge any reloads that we didn't combine for fear of
3888 increasing the number of spill registers needed but now
3889 discover can be safely merged. */
3890 if (SMALL_REGISTER_CLASSES
)
3891 merge_assigned_reloads (insn
);
3893 /* Generate the insns to reload operands into or out of
3894 their reload regs. */
3895 emit_reload_insns (chain
);
3897 /* Substitute the chosen reload regs from reload_reg_rtx
3898 into the insn's body (or perhaps into the bodies of other
3899 load and store insn that we just made for reloading
3900 and that we moved the structure into). */
3901 subst_reloads (insn
);
3903 /* If this was an ASM, make sure that all the reload insns
3904 we have generated are valid. If not, give an error
3907 if (asm_noperands (PATTERN (insn
)) >= 0)
3908 for (p
= NEXT_INSN (prev
); p
!= next
; p
= NEXT_INSN (p
))
3909 if (p
!= insn
&& INSN_P (p
)
3910 && (recog_memoized (p
) < 0
3911 || (extract_insn (p
), ! constrain_operands (1))))
3913 error_for_asm (insn
,
3914 "`asm' operand requires impossible reload");
3916 NOTE_SOURCE_FILE (p
) = 0;
3917 NOTE_LINE_NUMBER (p
) = NOTE_INSN_DELETED
;
3921 if (num_eliminable
&& chain
->need_elim
)
3922 update_eliminable_offsets ();
3924 /* Any previously reloaded spilled pseudo reg, stored in this insn,
3925 is no longer validly lying around to save a future reload.
3926 Note that this does not detect pseudos that were reloaded
3927 for this insn in order to be stored in
3928 (obeying register constraints). That is correct; such reload
3929 registers ARE still valid. */
3930 note_stores (oldpat
, forget_old_reloads_1
, NULL
);
3932 /* There may have been CLOBBER insns placed after INSN. So scan
3933 between INSN and NEXT and use them to forget old reloads. */
3934 for (x
= NEXT_INSN (insn
); x
!= old_next
; x
= NEXT_INSN (x
))
3935 if (GET_CODE (x
) == INSN
&& GET_CODE (PATTERN (x
)) == CLOBBER
)
3936 note_stores (PATTERN (x
), forget_old_reloads_1
, NULL
);
3939 /* Likewise for regs altered by auto-increment in this insn.
3940 REG_INC notes have been changed by reloading:
3941 find_reloads_address_1 records substitutions for them,
3942 which have been performed by subst_reloads above. */
3943 for (i
= n_reloads
- 1; i
>= 0; i
--)
3945 rtx in_reg
= rld
[i
].in_reg
;
3948 enum rtx_code code
= GET_CODE (in_reg
);
3949 /* PRE_INC / PRE_DEC will have the reload register ending up
3950 with the same value as the stack slot, but that doesn't
3951 hold true for POST_INC / POST_DEC. Either we have to
3952 convert the memory access to a true POST_INC / POST_DEC,
3953 or we can't use the reload register for inheritance. */
3954 if ((code
== POST_INC
|| code
== POST_DEC
)
3955 && TEST_HARD_REG_BIT (reg_reloaded_valid
,
3956 REGNO (rld
[i
].reg_rtx
))
3957 /* Make sure it is the inc/dec pseudo, and not
3958 some other (e.g. output operand) pseudo. */
3959 && (reg_reloaded_contents
[REGNO (rld
[i
].reg_rtx
)]
3960 == REGNO (XEXP (in_reg
, 0))))
3963 rtx reload_reg
= rld
[i
].reg_rtx
;
3964 enum machine_mode mode
= GET_MODE (reload_reg
);
3968 for (p
= PREV_INSN (old_next
); p
!= prev
; p
= PREV_INSN (p
))
3970 /* We really want to ignore REG_INC notes here, so
3971 use PATTERN (p) as argument to reg_set_p . */
3972 if (reg_set_p (reload_reg
, PATTERN (p
)))
3974 n
= count_occurrences (PATTERN (p
), reload_reg
, 0);
3979 n
= validate_replace_rtx (reload_reg
,
3980 gen_rtx (code
, mode
,
3984 /* We must also verify that the constraints
3985 are met after the replacement. */
3988 n
= constrain_operands (1);
3992 /* If the constraints were not met, then
3993 undo the replacement. */
3996 validate_replace_rtx (gen_rtx (code
, mode
,
4008 = gen_rtx_EXPR_LIST (REG_INC
, reload_reg
,
4010 /* Mark this as having an output reload so that the
4011 REG_INC processing code below won't invalidate
4012 the reload for inheritance. */
4013 SET_HARD_REG_BIT (reg_is_output_reload
,
4014 REGNO (reload_reg
));
4015 reg_has_output_reload
[REGNO (XEXP (in_reg
, 0))] = 1;
4018 forget_old_reloads_1 (XEXP (in_reg
, 0), NULL_RTX
,
4021 else if ((code
== PRE_INC
|| code
== PRE_DEC
)
4022 && TEST_HARD_REG_BIT (reg_reloaded_valid
,
4023 REGNO (rld
[i
].reg_rtx
))
4024 /* Make sure it is the inc/dec pseudo, and not
4025 some other (e.g. output operand) pseudo. */
4026 && (reg_reloaded_contents
[REGNO (rld
[i
].reg_rtx
)]
4027 == REGNO (XEXP (in_reg
, 0))))
4029 SET_HARD_REG_BIT (reg_is_output_reload
,
4030 REGNO (rld
[i
].reg_rtx
));
4031 reg_has_output_reload
[REGNO (XEXP (in_reg
, 0))] = 1;
4035 /* If a pseudo that got a hard register is auto-incremented,
4036 we must purge records of copying it into pseudos without
4038 for (x
= REG_NOTES (insn
); x
; x
= XEXP (x
, 1))
4039 if (REG_NOTE_KIND (x
) == REG_INC
)
4041 /* See if this pseudo reg was reloaded in this insn.
4042 If so, its last-reload info is still valid
4043 because it is based on this insn's reload. */
4044 for (i
= 0; i
< n_reloads
; i
++)
4045 if (rld
[i
].out
== XEXP (x
, 0))
4049 forget_old_reloads_1 (XEXP (x
, 0), NULL_RTX
, NULL
);
4053 /* A reload reg's contents are unknown after a label. */
4054 if (GET_CODE (insn
) == CODE_LABEL
)
4055 CLEAR_HARD_REG_SET (reg_reloaded_valid
);
4057 /* Don't assume a reload reg is still good after a call insn
4058 if it is a call-used reg. */
4059 else if (GET_CODE (insn
) == CALL_INSN
)
4060 AND_COMPL_HARD_REG_SET(reg_reloaded_valid
, call_used_reg_set
);
4064 free (reg_last_reload_reg
);
4065 free (reg_has_output_reload
);
4068 /* Discard all record of any value reloaded from X,
4069 or reloaded in X from someplace else;
4070 unless X is an output reload reg of the current insn.
4072 X may be a hard reg (the reload reg)
4073 or it may be a pseudo reg that was reloaded from. */
4076 forget_old_reloads_1 (x
, ignored
, data
)
4078 rtx ignored ATTRIBUTE_UNUSED
;
4079 void *data ATTRIBUTE_UNUSED
;
4085 /* note_stores does give us subregs of hard regs,
4086 subreg_regno_offset will abort if it is not a hard reg. */
4087 while (GET_CODE (x
) == SUBREG
)
4089 offset
+= subreg_regno_offset (REGNO (SUBREG_REG (x
)),
4090 GET_MODE (SUBREG_REG (x
)),
4096 if (GET_CODE (x
) != REG
)
4099 regno
= REGNO (x
) + offset
;
4101 if (regno
>= FIRST_PSEUDO_REGISTER
)
4107 nr
= HARD_REGNO_NREGS (regno
, GET_MODE (x
));
4108 /* Storing into a spilled-reg invalidates its contents.
4109 This can happen if a block-local pseudo is allocated to that reg
4110 and it wasn't spilled because this block's total need is 0.
4111 Then some insn might have an optional reload and use this reg. */
4112 for (i
= 0; i
< nr
; i
++)
4113 /* But don't do this if the reg actually serves as an output
4114 reload reg in the current instruction. */
4116 || ! TEST_HARD_REG_BIT (reg_is_output_reload
, regno
+ i
))
4118 CLEAR_HARD_REG_BIT (reg_reloaded_valid
, regno
+ i
);
4119 spill_reg_store
[regno
+ i
] = 0;
4123 /* Since value of X has changed,
4124 forget any value previously copied from it. */
4127 /* But don't forget a copy if this is the output reload
4128 that establishes the copy's validity. */
4129 if (n_reloads
== 0 || reg_has_output_reload
[regno
+ nr
] == 0)
4130 reg_last_reload_reg
[regno
+ nr
] = 0;
4133 /* The following HARD_REG_SETs indicate when each hard register is
4134 used for a reload of various parts of the current insn. */
4136 /* If reg is unavailable for all reloads. */
4137 static HARD_REG_SET reload_reg_unavailable
;
4138 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
4139 static HARD_REG_SET reload_reg_used
;
4140 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
4141 static HARD_REG_SET reload_reg_used_in_input_addr
[MAX_RECOG_OPERANDS
];
4142 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */
4143 static HARD_REG_SET reload_reg_used_in_inpaddr_addr
[MAX_RECOG_OPERANDS
];
4144 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
4145 static HARD_REG_SET reload_reg_used_in_output_addr
[MAX_RECOG_OPERANDS
];
4146 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */
4147 static HARD_REG_SET reload_reg_used_in_outaddr_addr
[MAX_RECOG_OPERANDS
];
4148 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
4149 static HARD_REG_SET reload_reg_used_in_input
[MAX_RECOG_OPERANDS
];
4150 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
4151 static HARD_REG_SET reload_reg_used_in_output
[MAX_RECOG_OPERANDS
];
4152 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
4153 static HARD_REG_SET reload_reg_used_in_op_addr
;
4154 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */
4155 static HARD_REG_SET reload_reg_used_in_op_addr_reload
;
4156 /* If reg is in use for a RELOAD_FOR_INSN reload. */
4157 static HARD_REG_SET reload_reg_used_in_insn
;
4158 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
4159 static HARD_REG_SET reload_reg_used_in_other_addr
;
4161 /* If reg is in use as a reload reg for any sort of reload. */
4162 static HARD_REG_SET reload_reg_used_at_all
;
4164 /* If reg is use as an inherited reload. We just mark the first register
4166 static HARD_REG_SET reload_reg_used_for_inherit
;
4168 /* Records which hard regs are used in any way, either as explicit use or
4169 by being allocated to a pseudo during any point of the current insn. */
4170 static HARD_REG_SET reg_used_in_insn
;
4172 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
4173 TYPE. MODE is used to indicate how many consecutive regs are
4177 mark_reload_reg_in_use (regno
, opnum
, type
, mode
)
4180 enum reload_type type
;
4181 enum machine_mode mode
;
4183 unsigned int nregs
= HARD_REGNO_NREGS (regno
, mode
);
4186 for (i
= regno
; i
< nregs
+ regno
; i
++)
4191 SET_HARD_REG_BIT (reload_reg_used
, i
);
4194 case RELOAD_FOR_INPUT_ADDRESS
:
4195 SET_HARD_REG_BIT (reload_reg_used_in_input_addr
[opnum
], i
);
4198 case RELOAD_FOR_INPADDR_ADDRESS
:
4199 SET_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[opnum
], i
);
4202 case RELOAD_FOR_OUTPUT_ADDRESS
:
4203 SET_HARD_REG_BIT (reload_reg_used_in_output_addr
[opnum
], i
);
4206 case RELOAD_FOR_OUTADDR_ADDRESS
:
4207 SET_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[opnum
], i
);
4210 case RELOAD_FOR_OPERAND_ADDRESS
:
4211 SET_HARD_REG_BIT (reload_reg_used_in_op_addr
, i
);
4214 case RELOAD_FOR_OPADDR_ADDR
:
4215 SET_HARD_REG_BIT (reload_reg_used_in_op_addr_reload
, i
);
4218 case RELOAD_FOR_OTHER_ADDRESS
:
4219 SET_HARD_REG_BIT (reload_reg_used_in_other_addr
, i
);
4222 case RELOAD_FOR_INPUT
:
4223 SET_HARD_REG_BIT (reload_reg_used_in_input
[opnum
], i
);
4226 case RELOAD_FOR_OUTPUT
:
4227 SET_HARD_REG_BIT (reload_reg_used_in_output
[opnum
], i
);
4230 case RELOAD_FOR_INSN
:
4231 SET_HARD_REG_BIT (reload_reg_used_in_insn
, i
);
4235 SET_HARD_REG_BIT (reload_reg_used_at_all
, i
);
4239 /* Similarly, but show REGNO is no longer in use for a reload. */
4242 clear_reload_reg_in_use (regno
, opnum
, type
, mode
)
4245 enum reload_type type
;
4246 enum machine_mode mode
;
4248 unsigned int nregs
= HARD_REGNO_NREGS (regno
, mode
);
4249 unsigned int start_regno
, end_regno
, r
;
4251 /* A complication is that for some reload types, inheritance might
4252 allow multiple reloads of the same types to share a reload register.
4253 We set check_opnum if we have to check only reloads with the same
4254 operand number, and check_any if we have to check all reloads. */
4255 int check_opnum
= 0;
4257 HARD_REG_SET
*used_in_set
;
4262 used_in_set
= &reload_reg_used
;
4265 case RELOAD_FOR_INPUT_ADDRESS
:
4266 used_in_set
= &reload_reg_used_in_input_addr
[opnum
];
4269 case RELOAD_FOR_INPADDR_ADDRESS
:
4271 used_in_set
= &reload_reg_used_in_inpaddr_addr
[opnum
];
4274 case RELOAD_FOR_OUTPUT_ADDRESS
:
4275 used_in_set
= &reload_reg_used_in_output_addr
[opnum
];
4278 case RELOAD_FOR_OUTADDR_ADDRESS
:
4280 used_in_set
= &reload_reg_used_in_outaddr_addr
[opnum
];
4283 case RELOAD_FOR_OPERAND_ADDRESS
:
4284 used_in_set
= &reload_reg_used_in_op_addr
;
4287 case RELOAD_FOR_OPADDR_ADDR
:
4289 used_in_set
= &reload_reg_used_in_op_addr_reload
;
4292 case RELOAD_FOR_OTHER_ADDRESS
:
4293 used_in_set
= &reload_reg_used_in_other_addr
;
4297 case RELOAD_FOR_INPUT
:
4298 used_in_set
= &reload_reg_used_in_input
[opnum
];
4301 case RELOAD_FOR_OUTPUT
:
4302 used_in_set
= &reload_reg_used_in_output
[opnum
];
4305 case RELOAD_FOR_INSN
:
4306 used_in_set
= &reload_reg_used_in_insn
;
4311 /* We resolve conflicts with remaining reloads of the same type by
4312 excluding the intervals of of reload registers by them from the
4313 interval of freed reload registers. Since we only keep track of
4314 one set of interval bounds, we might have to exclude somewhat
4315 more then what would be necessary if we used a HARD_REG_SET here.
4316 But this should only happen very infrequently, so there should
4317 be no reason to worry about it. */
4319 start_regno
= regno
;
4320 end_regno
= regno
+ nregs
;
4321 if (check_opnum
|| check_any
)
4323 for (i
= n_reloads
- 1; i
>= 0; i
--)
4325 if (rld
[i
].when_needed
== type
4326 && (check_any
|| rld
[i
].opnum
== opnum
)
4329 unsigned int conflict_start
= true_regnum (rld
[i
].reg_rtx
);
4330 unsigned int conflict_end
4332 + HARD_REGNO_NREGS (conflict_start
, rld
[i
].mode
));
4334 /* If there is an overlap with the first to-be-freed register,
4335 adjust the interval start. */
4336 if (conflict_start
<= start_regno
&& conflict_end
> start_regno
)
4337 start_regno
= conflict_end
;
4338 /* Otherwise, if there is a conflict with one of the other
4339 to-be-freed registers, adjust the interval end. */
4340 if (conflict_start
> start_regno
&& conflict_start
< end_regno
)
4341 end_regno
= conflict_start
;
4346 for (r
= start_regno
; r
< end_regno
; r
++)
4347 CLEAR_HARD_REG_BIT (*used_in_set
, r
);
4350 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
4351 specified by OPNUM and TYPE. */
4354 reload_reg_free_p (regno
, opnum
, type
)
4357 enum reload_type type
;
4361 /* In use for a RELOAD_OTHER means it's not available for anything. */
4362 if (TEST_HARD_REG_BIT (reload_reg_used
, regno
)
4363 || TEST_HARD_REG_BIT (reload_reg_unavailable
, regno
))
4369 /* In use for anything means we can't use it for RELOAD_OTHER. */
4370 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr
, regno
)
4371 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
)
4372 || TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
))
4375 for (i
= 0; i
< reload_n_operands
; i
++)
4376 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
4377 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
)
4378 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
4379 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
)
4380 || TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
)
4381 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
4386 case RELOAD_FOR_INPUT
:
4387 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
4388 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
))
4391 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload
, regno
))
4394 /* If it is used for some other input, can't use it. */
4395 for (i
= 0; i
< reload_n_operands
; i
++)
4396 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
4399 /* If it is used in a later operand's address, can't use it. */
4400 for (i
= opnum
+ 1; i
< reload_n_operands
; i
++)
4401 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
4402 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
))
4407 case RELOAD_FOR_INPUT_ADDRESS
:
4408 /* Can't use a register if it is used for an input address for this
4409 operand or used as an input in an earlier one. */
4410 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[opnum
], regno
)
4411 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[opnum
], regno
))
4414 for (i
= 0; i
< opnum
; i
++)
4415 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
4420 case RELOAD_FOR_INPADDR_ADDRESS
:
4421 /* Can't use a register if it is used for an input address
4422 for this operand or used as an input in an earlier
4424 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[opnum
], regno
))
4427 for (i
= 0; i
< opnum
; i
++)
4428 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
4433 case RELOAD_FOR_OUTPUT_ADDRESS
:
4434 /* Can't use a register if it is used for an output address for this
4435 operand or used as an output in this or a later operand. */
4436 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[opnum
], regno
))
4439 for (i
= opnum
; i
< reload_n_operands
; i
++)
4440 if (TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
4445 case RELOAD_FOR_OUTADDR_ADDRESS
:
4446 /* Can't use a register if it is used for an output address
4447 for this operand or used as an output in this or a
4449 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[opnum
], regno
))
4452 for (i
= opnum
; i
< reload_n_operands
; i
++)
4453 if (TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
4458 case RELOAD_FOR_OPERAND_ADDRESS
:
4459 for (i
= 0; i
< reload_n_operands
; i
++)
4460 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
4463 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
4464 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
));
4466 case RELOAD_FOR_OPADDR_ADDR
:
4467 for (i
= 0; i
< reload_n_operands
; i
++)
4468 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
4471 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload
, regno
));
4473 case RELOAD_FOR_OUTPUT
:
4474 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
4475 outputs, or an operand address for this or an earlier output. */
4476 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
))
4479 for (i
= 0; i
< reload_n_operands
; i
++)
4480 if (TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
4483 for (i
= 0; i
<= opnum
; i
++)
4484 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
4485 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
))
4490 case RELOAD_FOR_INSN
:
4491 for (i
= 0; i
< reload_n_operands
; i
++)
4492 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
)
4493 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
4496 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
4497 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
));
4499 case RELOAD_FOR_OTHER_ADDRESS
:
4500 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr
, regno
);
4505 /* Return 1 if the value in reload reg REGNO, as used by a reload
4506 needed for the part of the insn specified by OPNUM and TYPE,
4507 is still available in REGNO at the end of the insn.
4509 We can assume that the reload reg was already tested for availability
4510 at the time it is needed, and we should not check this again,
4511 in case the reg has already been marked in use. */
4514 reload_reg_reaches_end_p (regno
, opnum
, type
)
4517 enum reload_type type
;
4524 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
4525 its value must reach the end. */
4528 /* If this use is for part of the insn,
4529 its value reaches if no subsequent part uses the same register.
4530 Just like the above function, don't try to do this with lots
4533 case RELOAD_FOR_OTHER_ADDRESS
:
4534 /* Here we check for everything else, since these don't conflict
4535 with anything else and everything comes later. */
4537 for (i
= 0; i
< reload_n_operands
; i
++)
4538 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
4539 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
)
4540 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
)
4541 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
4542 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
)
4543 || TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
4546 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
)
4547 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
4548 && ! TEST_HARD_REG_BIT (reload_reg_used
, regno
));
4550 case RELOAD_FOR_INPUT_ADDRESS
:
4551 case RELOAD_FOR_INPADDR_ADDRESS
:
4552 /* Similar, except that we check only for this and subsequent inputs
4553 and the address of only subsequent inputs and we do not need
4554 to check for RELOAD_OTHER objects since they are known not to
4557 for (i
= opnum
; i
< reload_n_operands
; i
++)
4558 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
4561 for (i
= opnum
+ 1; i
< reload_n_operands
; i
++)
4562 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
4563 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
))
4566 for (i
= 0; i
< reload_n_operands
; i
++)
4567 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
4568 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
)
4569 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
4572 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload
, regno
))
4575 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
)
4576 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
4577 && !TEST_HARD_REG_BIT (reload_reg_used
, regno
));
4579 case RELOAD_FOR_INPUT
:
4580 /* Similar to input address, except we start at the next operand for
4581 both input and input address and we do not check for
4582 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
4585 for (i
= opnum
+ 1; i
< reload_n_operands
; i
++)
4586 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
4587 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
)
4588 || TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
4591 /* ... fall through ... */
4593 case RELOAD_FOR_OPERAND_ADDRESS
:
4594 /* Check outputs and their addresses. */
4596 for (i
= 0; i
< reload_n_operands
; i
++)
4597 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
4598 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
)
4599 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
4602 return (!TEST_HARD_REG_BIT (reload_reg_used
, regno
));
4604 case RELOAD_FOR_OPADDR_ADDR
:
4605 for (i
= 0; i
< reload_n_operands
; i
++)
4606 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
4607 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
)
4608 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
4611 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
)
4612 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
4613 && !TEST_HARD_REG_BIT (reload_reg_used
, regno
));
4615 case RELOAD_FOR_INSN
:
4616 /* These conflict with other outputs with RELOAD_OTHER. So
4617 we need only check for output addresses. */
4621 /* ... fall through ... */
4623 case RELOAD_FOR_OUTPUT
:
4624 case RELOAD_FOR_OUTPUT_ADDRESS
:
4625 case RELOAD_FOR_OUTADDR_ADDRESS
:
4626 /* We already know these can't conflict with a later output. So the
4627 only thing to check are later output addresses. */
4628 for (i
= opnum
+ 1; i
< reload_n_operands
; i
++)
4629 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
4630 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
))
4639 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
4642 This function uses the same algorithm as reload_reg_free_p above. */
4645 reloads_conflict (r1
, r2
)
4648 enum reload_type r1_type
= rld
[r1
].when_needed
;
4649 enum reload_type r2_type
= rld
[r2
].when_needed
;
4650 int r1_opnum
= rld
[r1
].opnum
;
4651 int r2_opnum
= rld
[r2
].opnum
;
4653 /* RELOAD_OTHER conflicts with everything. */
4654 if (r2_type
== RELOAD_OTHER
)
4657 /* Otherwise, check conflicts differently for each type. */
4661 case RELOAD_FOR_INPUT
:
4662 return (r2_type
== RELOAD_FOR_INSN
4663 || r2_type
== RELOAD_FOR_OPERAND_ADDRESS
4664 || r2_type
== RELOAD_FOR_OPADDR_ADDR
4665 || r2_type
== RELOAD_FOR_INPUT
4666 || ((r2_type
== RELOAD_FOR_INPUT_ADDRESS
4667 || r2_type
== RELOAD_FOR_INPADDR_ADDRESS
)
4668 && r2_opnum
> r1_opnum
));
4670 case RELOAD_FOR_INPUT_ADDRESS
:
4671 return ((r2_type
== RELOAD_FOR_INPUT_ADDRESS
&& r1_opnum
== r2_opnum
)
4672 || (r2_type
== RELOAD_FOR_INPUT
&& r2_opnum
< r1_opnum
));
4674 case RELOAD_FOR_INPADDR_ADDRESS
:
4675 return ((r2_type
== RELOAD_FOR_INPADDR_ADDRESS
&& r1_opnum
== r2_opnum
)
4676 || (r2_type
== RELOAD_FOR_INPUT
&& r2_opnum
< r1_opnum
));
4678 case RELOAD_FOR_OUTPUT_ADDRESS
:
4679 return ((r2_type
== RELOAD_FOR_OUTPUT_ADDRESS
&& r2_opnum
== r1_opnum
)
4680 || (r2_type
== RELOAD_FOR_OUTPUT
&& r2_opnum
>= r1_opnum
));
4682 case RELOAD_FOR_OUTADDR_ADDRESS
:
4683 return ((r2_type
== RELOAD_FOR_OUTADDR_ADDRESS
&& r2_opnum
== r1_opnum
)
4684 || (r2_type
== RELOAD_FOR_OUTPUT
&& r2_opnum
>= r1_opnum
));
4686 case RELOAD_FOR_OPERAND_ADDRESS
:
4687 return (r2_type
== RELOAD_FOR_INPUT
|| r2_type
== RELOAD_FOR_INSN
4688 || r2_type
== RELOAD_FOR_OPERAND_ADDRESS
);
4690 case RELOAD_FOR_OPADDR_ADDR
:
4691 return (r2_type
== RELOAD_FOR_INPUT
4692 || r2_type
== RELOAD_FOR_OPADDR_ADDR
);
4694 case RELOAD_FOR_OUTPUT
:
4695 return (r2_type
== RELOAD_FOR_INSN
|| r2_type
== RELOAD_FOR_OUTPUT
4696 || ((r2_type
== RELOAD_FOR_OUTPUT_ADDRESS
4697 || r2_type
== RELOAD_FOR_OUTADDR_ADDRESS
)
4698 && r2_opnum
<= r1_opnum
));
4700 case RELOAD_FOR_INSN
:
4701 return (r2_type
== RELOAD_FOR_INPUT
|| r2_type
== RELOAD_FOR_OUTPUT
4702 || r2_type
== RELOAD_FOR_INSN
4703 || r2_type
== RELOAD_FOR_OPERAND_ADDRESS
);
4705 case RELOAD_FOR_OTHER_ADDRESS
:
4706 return r2_type
== RELOAD_FOR_OTHER_ADDRESS
;
4716 /* Indexed by reload number, 1 if incoming value
4717 inherited from previous insns. */
4718 char reload_inherited
[MAX_RELOADS
];
4720 /* For an inherited reload, this is the insn the reload was inherited from,
4721 if we know it. Otherwise, this is 0. */
4722 rtx reload_inheritance_insn
[MAX_RELOADS
];
4724 /* If non-zero, this is a place to get the value of the reload,
4725 rather than using reload_in. */
4726 rtx reload_override_in
[MAX_RELOADS
];
4728 /* For each reload, the hard register number of the register used,
4729 or -1 if we did not need a register for this reload. */
4730 int reload_spill_index
[MAX_RELOADS
];
4732 /* Subroutine of free_for_value_p, used to check a single register.
4733 START_REGNO is the starting regno of the full reload register
4734 (possibly comprising multiple hard registers) that we are considering. */
4737 reload_reg_free_for_value_p (start_regno
, regno
, opnum
, type
, value
, out
,
4738 reloadnum
, ignore_address_reloads
)
4739 int start_regno
, regno
;
4741 enum reload_type type
;
4744 int ignore_address_reloads
;
4747 /* Set if we see an input reload that must not share its reload register
4748 with any new earlyclobber, but might otherwise share the reload
4749 register with an output or input-output reload. */
4750 int check_earlyclobber
= 0;
4754 if (TEST_HARD_REG_BIT (reload_reg_unavailable
, regno
))
4757 if (out
== const0_rtx
)
4763 /* We use some pseudo 'time' value to check if the lifetimes of the
4764 new register use would overlap with the one of a previous reload
4765 that is not read-only or uses a different value.
4766 The 'time' used doesn't have to be linear in any shape or form, just
4768 Some reload types use different 'buckets' for each operand.
4769 So there are MAX_RECOG_OPERANDS different time values for each
4771 We compute TIME1 as the time when the register for the prospective
4772 new reload ceases to be live, and TIME2 for each existing
4773 reload as the time when that the reload register of that reload
4775 Where there is little to be gained by exact lifetime calculations,
4776 we just make conservative assumptions, i.e. a longer lifetime;
4777 this is done in the 'default:' cases. */
4780 case RELOAD_FOR_OTHER_ADDRESS
:
4781 /* RELOAD_FOR_OTHER_ADDRESS conflicts with RELOAD_OTHER reloads. */
4782 time1
= copy
? 0 : 1;
4785 time1
= copy
? 1 : MAX_RECOG_OPERANDS
* 5 + 5;
4787 /* For each input, we may have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
4788 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 ,
4789 respectively, to the time values for these, we get distinct time
4790 values. To get distinct time values for each operand, we have to
4791 multiply opnum by at least three. We round that up to four because
4792 multiply by four is often cheaper. */
4793 case RELOAD_FOR_INPADDR_ADDRESS
:
4794 time1
= opnum
* 4 + 2;
4796 case RELOAD_FOR_INPUT_ADDRESS
:
4797 time1
= opnum
* 4 + 3;
4799 case RELOAD_FOR_INPUT
:
4800 /* All RELOAD_FOR_INPUT reloads remain live till the instruction
4801 executes (inclusive). */
4802 time1
= copy
? opnum
* 4 + 4 : MAX_RECOG_OPERANDS
* 4 + 3;
4804 case RELOAD_FOR_OPADDR_ADDR
:
4806 <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
4807 time1
= MAX_RECOG_OPERANDS
* 4 + 1;
4809 case RELOAD_FOR_OPERAND_ADDRESS
:
4810 /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn
4812 time1
= copy
? MAX_RECOG_OPERANDS
* 4 + 2 : MAX_RECOG_OPERANDS
* 4 + 3;
4814 case RELOAD_FOR_OUTADDR_ADDRESS
:
4815 time1
= MAX_RECOG_OPERANDS
* 4 + 4 + opnum
;
4817 case RELOAD_FOR_OUTPUT_ADDRESS
:
4818 time1
= MAX_RECOG_OPERANDS
* 4 + 5 + opnum
;
4821 time1
= MAX_RECOG_OPERANDS
* 5 + 5;
4824 for (i
= 0; i
< n_reloads
; i
++)
4826 rtx reg
= rld
[i
].reg_rtx
;
4827 if (reg
&& GET_CODE (reg
) == REG
4828 && ((unsigned) regno
- true_regnum (reg
)
4829 <= HARD_REGNO_NREGS (REGNO (reg
), GET_MODE (reg
)) - (unsigned)1)
4832 rtx other_input
= rld
[i
].in
;
4834 /* If the other reload loads the same input value, that
4835 will not cause a conflict only if it's loading it into
4836 the same register. */
4837 if (true_regnum (reg
) != start_regno
)
4838 other_input
= NULL_RTX
;
4839 if (! other_input
|| ! rtx_equal_p (other_input
, value
)
4840 || rld
[i
].out
|| out
)
4843 switch (rld
[i
].when_needed
)
4845 case RELOAD_FOR_OTHER_ADDRESS
:
4848 case RELOAD_FOR_INPADDR_ADDRESS
:
4849 /* find_reloads makes sure that a
4850 RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used
4851 by at most one - the first -
4852 RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the
4853 address reload is inherited, the address address reload
4854 goes away, so we can ignore this conflict. */
4855 if (type
== RELOAD_FOR_INPUT_ADDRESS
&& reloadnum
== i
+ 1
4856 && ignore_address_reloads
4857 /* Unless the RELOAD_FOR_INPUT is an auto_inc expression.
4858 Then the address address is still needed to store
4859 back the new address. */
4860 && ! rld
[reloadnum
].out
)
4862 /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its
4863 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS
4865 if (type
== RELOAD_FOR_INPUT
&& opnum
== rld
[i
].opnum
4866 && ignore_address_reloads
4867 /* Unless we are reloading an auto_inc expression. */
4868 && ! rld
[reloadnum
].out
)
4870 time2
= rld
[i
].opnum
* 4 + 2;
4872 case RELOAD_FOR_INPUT_ADDRESS
:
4873 if (type
== RELOAD_FOR_INPUT
&& opnum
== rld
[i
].opnum
4874 && ignore_address_reloads
4875 && ! rld
[reloadnum
].out
)
4877 time2
= rld
[i
].opnum
* 4 + 3;
4879 case RELOAD_FOR_INPUT
:
4880 time2
= rld
[i
].opnum
* 4 + 4;
4881 check_earlyclobber
= 1;
4883 /* rld[i].opnum * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4
4884 == MAX_RECOG_OPERAND * 4 */
4885 case RELOAD_FOR_OPADDR_ADDR
:
4886 if (type
== RELOAD_FOR_OPERAND_ADDRESS
&& reloadnum
== i
+ 1
4887 && ignore_address_reloads
4888 && ! rld
[reloadnum
].out
)
4890 time2
= MAX_RECOG_OPERANDS
* 4 + 1;
4892 case RELOAD_FOR_OPERAND_ADDRESS
:
4893 time2
= MAX_RECOG_OPERANDS
* 4 + 2;
4894 check_earlyclobber
= 1;
4896 case RELOAD_FOR_INSN
:
4897 time2
= MAX_RECOG_OPERANDS
* 4 + 3;
4899 case RELOAD_FOR_OUTPUT
:
4900 /* All RELOAD_FOR_OUTPUT reloads become live just after the
4901 instruction is executed. */
4902 time2
= MAX_RECOG_OPERANDS
* 4 + 4;
4904 /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with
4905 the RELOAD_FOR_OUTPUT reloads, so assign it the same time
4907 case RELOAD_FOR_OUTADDR_ADDRESS
:
4908 if (type
== RELOAD_FOR_OUTPUT_ADDRESS
&& reloadnum
== i
+ 1
4909 && ignore_address_reloads
4910 && ! rld
[reloadnum
].out
)
4912 time2
= MAX_RECOG_OPERANDS
* 4 + 4 + rld
[i
].opnum
;
4914 case RELOAD_FOR_OUTPUT_ADDRESS
:
4915 time2
= MAX_RECOG_OPERANDS
* 4 + 5 + rld
[i
].opnum
;
4918 /* If there is no conflict in the input part, handle this
4919 like an output reload. */
4920 if (! rld
[i
].in
|| rtx_equal_p (other_input
, value
))
4922 time2
= MAX_RECOG_OPERANDS
* 4 + 4;
4923 /* Earlyclobbered outputs must conflict with inputs. */
4924 if (earlyclobber_operand_p (rld
[i
].out
))
4925 time2
= MAX_RECOG_OPERANDS
* 4 + 3;
4930 /* RELOAD_OTHER might be live beyond instruction execution,
4931 but this is not obvious when we set time2 = 1. So check
4932 here if there might be a problem with the new reload
4933 clobbering the register used by the RELOAD_OTHER. */
4941 && (! rld
[i
].in
|| rld
[i
].out
4942 || ! rtx_equal_p (other_input
, value
)))
4943 || (out
&& rld
[reloadnum
].out_reg
4944 && time2
>= MAX_RECOG_OPERANDS
* 4 + 3))
4950 /* Earlyclobbered outputs must conflict with inputs. */
4951 if (check_earlyclobber
&& out
&& earlyclobber_operand_p (out
))
4957 /* Return 1 if the value in reload reg REGNO, as used by a reload
4958 needed for the part of the insn specified by OPNUM and TYPE,
4959 may be used to load VALUE into it.
4961 MODE is the mode in which the register is used, this is needed to
4962 determine how many hard regs to test.
4964 Other read-only reloads with the same value do not conflict
4965 unless OUT is non-zero and these other reloads have to live while
4966 output reloads live.
4967 If OUT is CONST0_RTX, this is a special case: it means that the
4968 test should not be for using register REGNO as reload register, but
4969 for copying from register REGNO into the reload register.
4971 RELOADNUM is the number of the reload we want to load this value for;
4972 a reload does not conflict with itself.
4974 When IGNORE_ADDRESS_RELOADS is set, we can not have conflicts with
4975 reloads that load an address for the very reload we are considering.
4977 The caller has to make sure that there is no conflict with the return
4981 free_for_value_p (regno
, mode
, opnum
, type
, value
, out
, reloadnum
,
4982 ignore_address_reloads
)
4984 enum machine_mode mode
;
4986 enum reload_type type
;
4989 int ignore_address_reloads
;
4991 int nregs
= HARD_REGNO_NREGS (regno
, mode
);
4993 if (! reload_reg_free_for_value_p (regno
, regno
+ nregs
, opnum
, type
,
4994 value
, out
, reloadnum
,
4995 ignore_address_reloads
))
5000 /* Determine whether the reload reg X overlaps any rtx'es used for
5001 overriding inheritance. Return nonzero if so. */
5004 conflicts_with_override (x
)
5008 for (i
= 0; i
< n_reloads
; i
++)
5009 if (reload_override_in
[i
]
5010 && reg_overlap_mentioned_p (x
, reload_override_in
[i
]))
5015 /* Give an error message saying we failed to find a reload for INSN,
5016 and clear out reload R. */
5018 failed_reload (insn
, r
)
5022 if (asm_noperands (PATTERN (insn
)) < 0)
5023 /* It's the compiler's fault. */
5024 fatal_insn ("Could not find a spill register", insn
);
5026 /* It's the user's fault; the operand's mode and constraint
5027 don't match. Disable this reload so we don't crash in final. */
5028 error_for_asm (insn
,
5029 "`asm' operand constraint incompatible with operand size");
5033 rld
[r
].optional
= 1;
5034 rld
[r
].secondary_p
= 1;
5037 /* I is the index in SPILL_REG_RTX of the reload register we are to allocate
5038 for reload R. If it's valid, get an rtx for it. Return nonzero if
5041 set_reload_reg (i
, r
)
5045 rtx reg
= spill_reg_rtx
[i
];
5047 if (reg
== 0 || GET_MODE (reg
) != rld
[r
].mode
)
5048 spill_reg_rtx
[i
] = reg
5049 = gen_rtx_REG (rld
[r
].mode
, spill_regs
[i
]);
5051 regno
= true_regnum (reg
);
5053 /* Detect when the reload reg can't hold the reload mode.
5054 This used to be one `if', but Sequent compiler can't handle that. */
5055 if (HARD_REGNO_MODE_OK (regno
, rld
[r
].mode
))
5057 enum machine_mode test_mode
= VOIDmode
;
5059 test_mode
= GET_MODE (rld
[r
].in
);
5060 /* If rld[r].in has VOIDmode, it means we will load it
5061 in whatever mode the reload reg has: to wit, rld[r].mode.
5062 We have already tested that for validity. */
5063 /* Aside from that, we need to test that the expressions
5064 to reload from or into have modes which are valid for this
5065 reload register. Otherwise the reload insns would be invalid. */
5066 if (! (rld
[r
].in
!= 0 && test_mode
!= VOIDmode
5067 && ! HARD_REGNO_MODE_OK (regno
, test_mode
)))
5068 if (! (rld
[r
].out
!= 0
5069 && ! HARD_REGNO_MODE_OK (regno
, GET_MODE (rld
[r
].out
))))
5071 /* The reg is OK. */
5074 /* Mark as in use for this insn the reload regs we use
5076 mark_reload_reg_in_use (spill_regs
[i
], rld
[r
].opnum
,
5077 rld
[r
].when_needed
, rld
[r
].mode
);
5079 rld
[r
].reg_rtx
= reg
;
5080 reload_spill_index
[r
] = spill_regs
[i
];
5087 /* Find a spill register to use as a reload register for reload R.
5088 LAST_RELOAD is non-zero if this is the last reload for the insn being
5091 Set rld[R].reg_rtx to the register allocated.
5093 We return 1 if successful, or 0 if we couldn't find a spill reg and
5094 we didn't change anything. */
5097 allocate_reload_reg (chain
, r
, last_reload
)
5098 struct insn_chain
*chain ATTRIBUTE_UNUSED
;
5104 /* If we put this reload ahead, thinking it is a group,
5105 then insist on finding a group. Otherwise we can grab a
5106 reg that some other reload needs.
5107 (That can happen when we have a 68000 DATA_OR_FP_REG
5108 which is a group of data regs or one fp reg.)
5109 We need not be so restrictive if there are no more reloads
5112 ??? Really it would be nicer to have smarter handling
5113 for that kind of reg class, where a problem like this is normal.
5114 Perhaps those classes should be avoided for reloading
5115 by use of more alternatives. */
5117 int force_group
= rld
[r
].nregs
> 1 && ! last_reload
;
5119 /* If we want a single register and haven't yet found one,
5120 take any reg in the right class and not in use.
5121 If we want a consecutive group, here is where we look for it.
5123 We use two passes so we can first look for reload regs to
5124 reuse, which are already in use for other reloads in this insn,
5125 and only then use additional registers.
5126 I think that maximizing reuse is needed to make sure we don't
5127 run out of reload regs. Suppose we have three reloads, and
5128 reloads A and B can share regs. These need two regs.
5129 Suppose A and B are given different regs.
5130 That leaves none for C. */
5131 for (pass
= 0; pass
< 2; pass
++)
5133 /* I is the index in spill_regs.
5134 We advance it round-robin between insns to use all spill regs
5135 equally, so that inherited reloads have a chance
5136 of leapfrogging each other. */
5140 for (count
= 0; count
< n_spills
; count
++)
5142 int class = (int) rld
[r
].class;
5148 regnum
= spill_regs
[i
];
5150 if ((reload_reg_free_p (regnum
, rld
[r
].opnum
,
5153 /* We check reload_reg_used to make sure we
5154 don't clobber the return register. */
5155 && ! TEST_HARD_REG_BIT (reload_reg_used
, regnum
)
5156 && free_for_value_p (regnum
, rld
[r
].mode
, rld
[r
].opnum
,
5157 rld
[r
].when_needed
, rld
[r
].in
,
5159 && TEST_HARD_REG_BIT (reg_class_contents
[class], regnum
)
5160 && HARD_REGNO_MODE_OK (regnum
, rld
[r
].mode
)
5161 /* Look first for regs to share, then for unshared. But
5162 don't share regs used for inherited reloads; they are
5163 the ones we want to preserve. */
5165 || (TEST_HARD_REG_BIT (reload_reg_used_at_all
,
5167 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit
,
5170 int nr
= HARD_REGNO_NREGS (regnum
, rld
[r
].mode
);
5171 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
5172 (on 68000) got us two FP regs. If NR is 1,
5173 we would reject both of them. */
5176 /* If we need only one reg, we have already won. */
5179 /* But reject a single reg if we demand a group. */
5184 /* Otherwise check that as many consecutive regs as we need
5185 are available here. */
5188 int regno
= regnum
+ nr
- 1;
5189 if (!(TEST_HARD_REG_BIT (reg_class_contents
[class], regno
)
5190 && spill_reg_order
[regno
] >= 0
5191 && reload_reg_free_p (regno
, rld
[r
].opnum
,
5192 rld
[r
].when_needed
)))
5201 /* If we found something on pass 1, omit pass 2. */
5202 if (count
< n_spills
)
5206 /* We should have found a spill register by now. */
5207 if (count
>= n_spills
)
5210 /* I is the index in SPILL_REG_RTX of the reload register we are to
5211 allocate. Get an rtx for it and find its register number. */
5213 return set_reload_reg (i
, r
);
5216 /* Initialize all the tables needed to allocate reload registers.
5217 CHAIN is the insn currently being processed; SAVE_RELOAD_REG_RTX
5218 is the array we use to restore the reg_rtx field for every reload. */
5221 choose_reload_regs_init (chain
, save_reload_reg_rtx
)
5222 struct insn_chain
*chain
;
5223 rtx
*save_reload_reg_rtx
;
5227 for (i
= 0; i
< n_reloads
; i
++)
5228 rld
[i
].reg_rtx
= save_reload_reg_rtx
[i
];
5230 memset (reload_inherited
, 0, MAX_RELOADS
);
5231 memset ((char *) reload_inheritance_insn
, 0, MAX_RELOADS
* sizeof (rtx
));
5232 memset ((char *) reload_override_in
, 0, MAX_RELOADS
* sizeof (rtx
));
5234 CLEAR_HARD_REG_SET (reload_reg_used
);
5235 CLEAR_HARD_REG_SET (reload_reg_used_at_all
);
5236 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr
);
5237 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload
);
5238 CLEAR_HARD_REG_SET (reload_reg_used_in_insn
);
5239 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr
);
5241 CLEAR_HARD_REG_SET (reg_used_in_insn
);
5244 REG_SET_TO_HARD_REG_SET (tmp
, &chain
->live_throughout
);
5245 IOR_HARD_REG_SET (reg_used_in_insn
, tmp
);
5246 REG_SET_TO_HARD_REG_SET (tmp
, &chain
->dead_or_set
);
5247 IOR_HARD_REG_SET (reg_used_in_insn
, tmp
);
5248 compute_use_by_pseudos (®_used_in_insn
, &chain
->live_throughout
);
5249 compute_use_by_pseudos (®_used_in_insn
, &chain
->dead_or_set
);
5252 for (i
= 0; i
< reload_n_operands
; i
++)
5254 CLEAR_HARD_REG_SET (reload_reg_used_in_output
[i
]);
5255 CLEAR_HARD_REG_SET (reload_reg_used_in_input
[i
]);
5256 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr
[i
]);
5257 CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr
[i
]);
5258 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr
[i
]);
5259 CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr
[i
]);
5262 COMPL_HARD_REG_SET (reload_reg_unavailable
, chain
->used_spill_regs
);
5264 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit
);
5266 for (i
= 0; i
< n_reloads
; i
++)
5267 /* If we have already decided to use a certain register,
5268 don't use it in another way. */
5270 mark_reload_reg_in_use (REGNO (rld
[i
].reg_rtx
), rld
[i
].opnum
,
5271 rld
[i
].when_needed
, rld
[i
].mode
);
5274 /* Assign hard reg targets for the pseudo-registers we must reload
5275 into hard regs for this insn.
5276 Also output the instructions to copy them in and out of the hard regs.
5278 For machines with register classes, we are responsible for
5279 finding a reload reg in the proper class. */
5282 choose_reload_regs (chain
)
5283 struct insn_chain
*chain
;
5285 rtx insn
= chain
->insn
;
5287 unsigned int max_group_size
= 1;
5288 enum reg_class group_class
= NO_REGS
;
5289 int pass
, win
, inheritance
;
5291 rtx save_reload_reg_rtx
[MAX_RELOADS
];
5293 /* In order to be certain of getting the registers we need,
5294 we must sort the reloads into order of increasing register class.
5295 Then our grabbing of reload registers will parallel the process
5296 that provided the reload registers.
5298 Also note whether any of the reloads wants a consecutive group of regs.
5299 If so, record the maximum size of the group desired and what
5300 register class contains all the groups needed by this insn. */
5302 for (j
= 0; j
< n_reloads
; j
++)
5304 reload_order
[j
] = j
;
5305 reload_spill_index
[j
] = -1;
5307 if (rld
[j
].nregs
> 1)
5309 max_group_size
= MAX (rld
[j
].nregs
, max_group_size
);
5311 = reg_class_superunion
[(int) rld
[j
].class][(int)group_class
];
5314 save_reload_reg_rtx
[j
] = rld
[j
].reg_rtx
;
5318 qsort (reload_order
, n_reloads
, sizeof (short), reload_reg_class_lower
);
5320 /* If -O, try first with inheritance, then turning it off.
5321 If not -O, don't do inheritance.
5322 Using inheritance when not optimizing leads to paradoxes
5323 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
5324 because one side of the comparison might be inherited. */
5326 for (inheritance
= optimize
> 0; inheritance
>= 0; inheritance
--)
5328 choose_reload_regs_init (chain
, save_reload_reg_rtx
);
5330 /* Process the reloads in order of preference just found.
5331 Beyond this point, subregs can be found in reload_reg_rtx.
5333 This used to look for an existing reloaded home for all of the
5334 reloads, and only then perform any new reloads. But that could lose
5335 if the reloads were done out of reg-class order because a later
5336 reload with a looser constraint might have an old home in a register
5337 needed by an earlier reload with a tighter constraint.
5339 To solve this, we make two passes over the reloads, in the order
5340 described above. In the first pass we try to inherit a reload
5341 from a previous insn. If there is a later reload that needs a
5342 class that is a proper subset of the class being processed, we must
5343 also allocate a spill register during the first pass.
5345 Then make a second pass over the reloads to allocate any reloads
5346 that haven't been given registers yet. */
5348 for (j
= 0; j
< n_reloads
; j
++)
5350 register int r
= reload_order
[j
];
5351 rtx search_equiv
= NULL_RTX
;
5353 /* Ignore reloads that got marked inoperative. */
5354 if (rld
[r
].out
== 0 && rld
[r
].in
== 0
5355 && ! rld
[r
].secondary_p
)
5358 /* If find_reloads chose to use reload_in or reload_out as a reload
5359 register, we don't need to chose one. Otherwise, try even if it
5360 found one since we might save an insn if we find the value lying
5362 Try also when reload_in is a pseudo without a hard reg. */
5363 if (rld
[r
].in
!= 0 && rld
[r
].reg_rtx
!= 0
5364 && (rtx_equal_p (rld
[r
].in
, rld
[r
].reg_rtx
)
5365 || (rtx_equal_p (rld
[r
].out
, rld
[r
].reg_rtx
)
5366 && GET_CODE (rld
[r
].in
) != MEM
5367 && true_regnum (rld
[r
].in
) < FIRST_PSEUDO_REGISTER
)))
5370 #if 0 /* No longer needed for correct operation.
5371 It might give better code, or might not; worth an experiment? */
5372 /* If this is an optional reload, we can't inherit from earlier insns
5373 until we are sure that any non-optional reloads have been allocated.
5374 The following code takes advantage of the fact that optional reloads
5375 are at the end of reload_order. */
5376 if (rld
[r
].optional
!= 0)
5377 for (i
= 0; i
< j
; i
++)
5378 if ((rld
[reload_order
[i
]].out
!= 0
5379 || rld
[reload_order
[i
]].in
!= 0
5380 || rld
[reload_order
[i
]].secondary_p
)
5381 && ! rld
[reload_order
[i
]].optional
5382 && rld
[reload_order
[i
]].reg_rtx
== 0)
5383 allocate_reload_reg (chain
, reload_order
[i
], 0);
5386 /* First see if this pseudo is already available as reloaded
5387 for a previous insn. We cannot try to inherit for reloads
5388 that are smaller than the maximum number of registers needed
5389 for groups unless the register we would allocate cannot be used
5392 We could check here to see if this is a secondary reload for
5393 an object that is already in a register of the desired class.
5394 This would avoid the need for the secondary reload register.
5395 But this is complex because we can't easily determine what
5396 objects might want to be loaded via this reload. So let a
5397 register be allocated here. In `emit_reload_insns' we suppress
5398 one of the loads in the case described above. */
5403 register int regno
= -1;
5404 enum machine_mode mode
= VOIDmode
;
5408 else if (GET_CODE (rld
[r
].in
) == REG
)
5410 regno
= REGNO (rld
[r
].in
);
5411 mode
= GET_MODE (rld
[r
].in
);
5413 else if (GET_CODE (rld
[r
].in_reg
) == REG
)
5415 regno
= REGNO (rld
[r
].in_reg
);
5416 mode
= GET_MODE (rld
[r
].in_reg
);
5418 else if (GET_CODE (rld
[r
].in_reg
) == SUBREG
5419 && GET_CODE (SUBREG_REG (rld
[r
].in_reg
)) == REG
)
5421 byte
= SUBREG_BYTE (rld
[r
].in_reg
);
5422 regno
= REGNO (SUBREG_REG (rld
[r
].in_reg
));
5423 if (regno
< FIRST_PSEUDO_REGISTER
)
5424 regno
= subreg_regno (rld
[r
].in_reg
);
5425 mode
= GET_MODE (rld
[r
].in_reg
);
5428 else if ((GET_CODE (rld
[r
].in_reg
) == PRE_INC
5429 || GET_CODE (rld
[r
].in_reg
) == PRE_DEC
5430 || GET_CODE (rld
[r
].in_reg
) == POST_INC
5431 || GET_CODE (rld
[r
].in_reg
) == POST_DEC
)
5432 && GET_CODE (XEXP (rld
[r
].in_reg
, 0)) == REG
)
5434 regno
= REGNO (XEXP (rld
[r
].in_reg
, 0));
5435 mode
= GET_MODE (XEXP (rld
[r
].in_reg
, 0));
5436 rld
[r
].out
= rld
[r
].in
;
5440 /* This won't work, since REGNO can be a pseudo reg number.
5441 Also, it takes much more hair to keep track of all the things
5442 that can invalidate an inherited reload of part of a pseudoreg. */
5443 else if (GET_CODE (rld
[r
].in
) == SUBREG
5444 && GET_CODE (SUBREG_REG (rld
[r
].in
)) == REG
)
5445 regno
= subreg_regno (rld
[r
].in
);
5448 if (regno
>= 0 && reg_last_reload_reg
[regno
] != 0)
5450 enum reg_class
class = rld
[r
].class, last_class
;
5451 rtx last_reg
= reg_last_reload_reg
[regno
];
5452 enum machine_mode need_mode
;
5454 i
= REGNO (last_reg
);
5455 i
+= subreg_regno_offset (i
, GET_MODE (last_reg
), byte
, mode
);
5456 last_class
= REGNO_REG_CLASS (i
);
5462 = smallest_mode_for_size (GET_MODE_SIZE (mode
) + byte
,
5463 GET_MODE_CLASS (mode
));
5466 #ifdef CLASS_CANNOT_CHANGE_MODE
5468 (reg_class_contents
[(int) CLASS_CANNOT_CHANGE_MODE
], i
)
5469 ? ! CLASS_CANNOT_CHANGE_MODE_P (GET_MODE (last_reg
),
5471 : (GET_MODE_SIZE (GET_MODE (last_reg
))
5472 >= GET_MODE_SIZE (need_mode
)))
5474 (GET_MODE_SIZE (GET_MODE (last_reg
))
5475 >= GET_MODE_SIZE (need_mode
))
5477 && reg_reloaded_contents
[i
] == regno
5478 && TEST_HARD_REG_BIT (reg_reloaded_valid
, i
)
5479 && HARD_REGNO_MODE_OK (i
, rld
[r
].mode
)
5480 && (TEST_HARD_REG_BIT (reg_class_contents
[(int) class], i
)
5481 /* Even if we can't use this register as a reload
5482 register, we might use it for reload_override_in,
5483 if copying it to the desired class is cheap
5485 || ((REGISTER_MOVE_COST (mode
, last_class
, class)
5486 < MEMORY_MOVE_COST (mode
, class, 1))
5487 #ifdef SECONDARY_INPUT_RELOAD_CLASS
5488 && (SECONDARY_INPUT_RELOAD_CLASS (class, mode
,
5492 #ifdef SECONDARY_MEMORY_NEEDED
5493 && ! SECONDARY_MEMORY_NEEDED (last_class
, class,
5498 && (rld
[r
].nregs
== max_group_size
5499 || ! TEST_HARD_REG_BIT (reg_class_contents
[(int) group_class
],
5501 && free_for_value_p (i
, rld
[r
].mode
, rld
[r
].opnum
,
5502 rld
[r
].when_needed
, rld
[r
].in
,
5505 /* If a group is needed, verify that all the subsequent
5506 registers still have their values intact. */
5507 int nr
= HARD_REGNO_NREGS (i
, rld
[r
].mode
);
5510 for (k
= 1; k
< nr
; k
++)
5511 if (reg_reloaded_contents
[i
+ k
] != regno
5512 || ! TEST_HARD_REG_BIT (reg_reloaded_valid
, i
+ k
))
5520 last_reg
= (GET_MODE (last_reg
) == mode
5521 ? last_reg
: gen_rtx_REG (mode
, i
));
5524 for (k
= 0; k
< nr
; k
++)
5525 bad_for_class
|= ! TEST_HARD_REG_BIT (reg_class_contents
[(int) rld
[r
].class],
5528 /* We found a register that contains the
5529 value we need. If this register is the
5530 same as an `earlyclobber' operand of the
5531 current insn, just mark it as a place to
5532 reload from since we can't use it as the
5533 reload register itself. */
5535 for (i1
= 0; i1
< n_earlyclobbers
; i1
++)
5536 if (reg_overlap_mentioned_for_reload_p
5537 (reg_last_reload_reg
[regno
],
5538 reload_earlyclobbers
[i1
]))
5541 if (i1
!= n_earlyclobbers
5542 || ! (free_for_value_p (i
, rld
[r
].mode
,
5544 rld
[r
].when_needed
, rld
[r
].in
,
5546 /* Don't use it if we'd clobber a pseudo reg. */
5547 || (TEST_HARD_REG_BIT (reg_used_in_insn
, i
)
5549 && ! TEST_HARD_REG_BIT (reg_reloaded_dead
, i
))
5550 /* Don't clobber the frame pointer. */
5551 || (i
== HARD_FRAME_POINTER_REGNUM
5553 /* Don't really use the inherited spill reg
5554 if we need it wider than we've got it. */
5555 || (GET_MODE_SIZE (rld
[r
].mode
)
5556 > GET_MODE_SIZE (mode
))
5559 /* If find_reloads chose reload_out as reload
5560 register, stay with it - that leaves the
5561 inherited register for subsequent reloads. */
5562 || (rld
[r
].out
&& rld
[r
].reg_rtx
5563 && rtx_equal_p (rld
[r
].out
, rld
[r
].reg_rtx
)))
5565 if (! rld
[r
].optional
)
5567 reload_override_in
[r
] = last_reg
;
5568 reload_inheritance_insn
[r
]
5569 = reg_reloaded_insn
[i
];
5575 /* We can use this as a reload reg. */
5576 /* Mark the register as in use for this part of
5578 mark_reload_reg_in_use (i
,
5582 rld
[r
].reg_rtx
= last_reg
;
5583 reload_inherited
[r
] = 1;
5584 reload_inheritance_insn
[r
]
5585 = reg_reloaded_insn
[i
];
5586 reload_spill_index
[r
] = i
;
5587 for (k
= 0; k
< nr
; k
++)
5588 SET_HARD_REG_BIT (reload_reg_used_for_inherit
,
5596 /* Here's another way to see if the value is already lying around. */
5599 && ! reload_inherited
[r
]
5601 && (CONSTANT_P (rld
[r
].in
)
5602 || GET_CODE (rld
[r
].in
) == PLUS
5603 || GET_CODE (rld
[r
].in
) == REG
5604 || GET_CODE (rld
[r
].in
) == MEM
)
5605 && (rld
[r
].nregs
== max_group_size
5606 || ! reg_classes_intersect_p (rld
[r
].class, group_class
)))
5607 search_equiv
= rld
[r
].in
;
5608 /* If this is an output reload from a simple move insn, look
5609 if an equivalence for the input is available. */
5610 else if (inheritance
&& rld
[r
].in
== 0 && rld
[r
].out
!= 0)
5612 rtx set
= single_set (insn
);
5615 && rtx_equal_p (rld
[r
].out
, SET_DEST (set
))
5616 && CONSTANT_P (SET_SRC (set
)))
5617 search_equiv
= SET_SRC (set
);
5623 = find_equiv_reg (search_equiv
, insn
, rld
[r
].class,
5624 -1, NULL
, 0, rld
[r
].mode
);
5629 if (GET_CODE (equiv
) == REG
)
5630 regno
= REGNO (equiv
);
5631 else if (GET_CODE (equiv
) == SUBREG
)
5633 /* This must be a SUBREG of a hard register.
5634 Make a new REG since this might be used in an
5635 address and not all machines support SUBREGs
5637 regno
= subreg_regno (equiv
);
5638 equiv
= gen_rtx_REG (rld
[r
].mode
, regno
);
5644 /* If we found a spill reg, reject it unless it is free
5645 and of the desired class. */
5647 && ((TEST_HARD_REG_BIT (reload_reg_used_at_all
, regno
)
5648 && ! free_for_value_p (regno
, rld
[r
].mode
,
5649 rld
[r
].opnum
, rld
[r
].when_needed
,
5650 rld
[r
].in
, rld
[r
].out
, r
, 1))
5651 || ! TEST_HARD_REG_BIT (reg_class_contents
[(int) rld
[r
].class],
5655 if (equiv
!= 0 && ! HARD_REGNO_MODE_OK (regno
, rld
[r
].mode
))
5658 /* We found a register that contains the value we need.
5659 If this register is the same as an `earlyclobber' operand
5660 of the current insn, just mark it as a place to reload from
5661 since we can't use it as the reload register itself. */
5664 for (i
= 0; i
< n_earlyclobbers
; i
++)
5665 if (reg_overlap_mentioned_for_reload_p (equiv
,
5666 reload_earlyclobbers
[i
]))
5668 if (! rld
[r
].optional
)
5669 reload_override_in
[r
] = equiv
;
5674 /* If the equiv register we have found is explicitly clobbered
5675 in the current insn, it depends on the reload type if we
5676 can use it, use it for reload_override_in, or not at all.
5677 In particular, we then can't use EQUIV for a
5678 RELOAD_FOR_OUTPUT_ADDRESS reload. */
5682 if (regno_clobbered_p (regno
, insn
, rld
[r
].mode
, 0))
5683 switch (rld
[r
].when_needed
)
5685 case RELOAD_FOR_OTHER_ADDRESS
:
5686 case RELOAD_FOR_INPADDR_ADDRESS
:
5687 case RELOAD_FOR_INPUT_ADDRESS
:
5688 case RELOAD_FOR_OPADDR_ADDR
:
5691 case RELOAD_FOR_INPUT
:
5692 case RELOAD_FOR_OPERAND_ADDRESS
:
5693 if (! rld
[r
].optional
)
5694 reload_override_in
[r
] = equiv
;
5700 else if (regno_clobbered_p (regno
, insn
, rld
[r
].mode
, 1))
5701 switch (rld
[r
].when_needed
)
5703 case RELOAD_FOR_OTHER_ADDRESS
:
5704 case RELOAD_FOR_INPADDR_ADDRESS
:
5705 case RELOAD_FOR_INPUT_ADDRESS
:
5706 case RELOAD_FOR_OPADDR_ADDR
:
5707 case RELOAD_FOR_OPERAND_ADDRESS
:
5708 case RELOAD_FOR_INPUT
:
5711 if (! rld
[r
].optional
)
5712 reload_override_in
[r
] = equiv
;
5720 /* If we found an equivalent reg, say no code need be generated
5721 to load it, and use it as our reload reg. */
5722 if (equiv
!= 0 && regno
!= HARD_FRAME_POINTER_REGNUM
)
5724 int nr
= HARD_REGNO_NREGS (regno
, rld
[r
].mode
);
5726 rld
[r
].reg_rtx
= equiv
;
5727 reload_inherited
[r
] = 1;
5729 /* If reg_reloaded_valid is not set for this register,
5730 there might be a stale spill_reg_store lying around.
5731 We must clear it, since otherwise emit_reload_insns
5732 might delete the store. */
5733 if (! TEST_HARD_REG_BIT (reg_reloaded_valid
, regno
))
5734 spill_reg_store
[regno
] = NULL_RTX
;
5735 /* If any of the hard registers in EQUIV are spill
5736 registers, mark them as in use for this insn. */
5737 for (k
= 0; k
< nr
; k
++)
5739 i
= spill_reg_order
[regno
+ k
];
5742 mark_reload_reg_in_use (regno
, rld
[r
].opnum
,
5745 SET_HARD_REG_BIT (reload_reg_used_for_inherit
,
5752 /* If we found a register to use already, or if this is an optional
5753 reload, we are done. */
5754 if (rld
[r
].reg_rtx
!= 0 || rld
[r
].optional
!= 0)
5758 /* No longer needed for correct operation. Might or might
5759 not give better code on the average. Want to experiment? */
5761 /* See if there is a later reload that has a class different from our
5762 class that intersects our class or that requires less register
5763 than our reload. If so, we must allocate a register to this
5764 reload now, since that reload might inherit a previous reload
5765 and take the only available register in our class. Don't do this
5766 for optional reloads since they will force all previous reloads
5767 to be allocated. Also don't do this for reloads that have been
5770 for (i
= j
+ 1; i
< n_reloads
; i
++)
5772 int s
= reload_order
[i
];
5774 if ((rld
[s
].in
== 0 && rld
[s
].out
== 0
5775 && ! rld
[s
].secondary_p
)
5779 if ((rld
[s
].class != rld
[r
].class
5780 && reg_classes_intersect_p (rld
[r
].class,
5782 || rld
[s
].nregs
< rld
[r
].nregs
)
5789 allocate_reload_reg (chain
, r
, j
== n_reloads
- 1);
5793 /* Now allocate reload registers for anything non-optional that
5794 didn't get one yet. */
5795 for (j
= 0; j
< n_reloads
; j
++)
5797 register int r
= reload_order
[j
];
5799 /* Ignore reloads that got marked inoperative. */
5800 if (rld
[r
].out
== 0 && rld
[r
].in
== 0 && ! rld
[r
].secondary_p
)
5803 /* Skip reloads that already have a register allocated or are
5805 if (rld
[r
].reg_rtx
!= 0 || rld
[r
].optional
)
5808 if (! allocate_reload_reg (chain
, r
, j
== n_reloads
- 1))
5812 /* If that loop got all the way, we have won. */
5819 /* Loop around and try without any inheritance. */
5824 /* First undo everything done by the failed attempt
5825 to allocate with inheritance. */
5826 choose_reload_regs_init (chain
, save_reload_reg_rtx
);
5828 /* Some sanity tests to verify that the reloads found in the first
5829 pass are identical to the ones we have now. */
5830 if (chain
->n_reloads
!= n_reloads
)
5833 for (i
= 0; i
< n_reloads
; i
++)
5835 if (chain
->rld
[i
].regno
< 0 || chain
->rld
[i
].reg_rtx
!= 0)
5837 if (chain
->rld
[i
].when_needed
!= rld
[i
].when_needed
)
5839 for (j
= 0; j
< n_spills
; j
++)
5840 if (spill_regs
[j
] == chain
->rld
[i
].regno
)
5841 if (! set_reload_reg (j
, i
))
5842 failed_reload (chain
->insn
, i
);
5846 /* If we thought we could inherit a reload, because it seemed that
5847 nothing else wanted the same reload register earlier in the insn,
5848 verify that assumption, now that all reloads have been assigned.
5849 Likewise for reloads where reload_override_in has been set. */
5851 /* If doing expensive optimizations, do one preliminary pass that doesn't
5852 cancel any inheritance, but removes reloads that have been needed only
5853 for reloads that we know can be inherited. */
5854 for (pass
= flag_expensive_optimizations
; pass
>= 0; pass
--)
5856 for (j
= 0; j
< n_reloads
; j
++)
5858 register int r
= reload_order
[j
];
5860 if (reload_inherited
[r
] && rld
[r
].reg_rtx
)
5861 check_reg
= rld
[r
].reg_rtx
;
5862 else if (reload_override_in
[r
]
5863 && (GET_CODE (reload_override_in
[r
]) == REG
5864 || GET_CODE (reload_override_in
[r
]) == SUBREG
))
5865 check_reg
= reload_override_in
[r
];
5868 if (! free_for_value_p (true_regnum (check_reg
), rld
[r
].mode
,
5869 rld
[r
].opnum
, rld
[r
].when_needed
, rld
[r
].in
,
5870 (reload_inherited
[r
]
5871 ? rld
[r
].out
: const0_rtx
),
5876 reload_inherited
[r
] = 0;
5877 reload_override_in
[r
] = 0;
5879 /* If we can inherit a RELOAD_FOR_INPUT, or can use a
5880 reload_override_in, then we do not need its related
5881 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads;
5882 likewise for other reload types.
5883 We handle this by removing a reload when its only replacement
5884 is mentioned in reload_in of the reload we are going to inherit.
5885 A special case are auto_inc expressions; even if the input is
5886 inherited, we still need the address for the output. We can
5887 recognize them because they have RELOAD_OUT set to RELOAD_IN.
5888 If we suceeded removing some reload and we are doing a preliminary
5889 pass just to remove such reloads, make another pass, since the
5890 removal of one reload might allow us to inherit another one. */
5892 && rld
[r
].out
!= rld
[r
].in
5893 && remove_address_replacements (rld
[r
].in
) && pass
)
5898 /* Now that reload_override_in is known valid,
5899 actually override reload_in. */
5900 for (j
= 0; j
< n_reloads
; j
++)
5901 if (reload_override_in
[j
])
5902 rld
[j
].in
= reload_override_in
[j
];
5904 /* If this reload won't be done because it has been cancelled or is
5905 optional and not inherited, clear reload_reg_rtx so other
5906 routines (such as subst_reloads) don't get confused. */
5907 for (j
= 0; j
< n_reloads
; j
++)
5908 if (rld
[j
].reg_rtx
!= 0
5909 && ((rld
[j
].optional
&& ! reload_inherited
[j
])
5910 || (rld
[j
].in
== 0 && rld
[j
].out
== 0
5911 && ! rld
[j
].secondary_p
)))
5913 int regno
= true_regnum (rld
[j
].reg_rtx
);
5915 if (spill_reg_order
[regno
] >= 0)
5916 clear_reload_reg_in_use (regno
, rld
[j
].opnum
,
5917 rld
[j
].when_needed
, rld
[j
].mode
);
5919 reload_spill_index
[j
] = -1;
5922 /* Record which pseudos and which spill regs have output reloads. */
5923 for (j
= 0; j
< n_reloads
; j
++)
5925 register int r
= reload_order
[j
];
5927 i
= reload_spill_index
[r
];
5929 /* I is nonneg if this reload uses a register.
5930 If rld[r].reg_rtx is 0, this is an optional reload
5931 that we opted to ignore. */
5932 if (rld
[r
].out_reg
!= 0 && GET_CODE (rld
[r
].out_reg
) == REG
5933 && rld
[r
].reg_rtx
!= 0)
5935 register int nregno
= REGNO (rld
[r
].out_reg
);
5938 if (nregno
< FIRST_PSEUDO_REGISTER
)
5939 nr
= HARD_REGNO_NREGS (nregno
, rld
[r
].mode
);
5942 reg_has_output_reload
[nregno
+ nr
] = 1;
5946 nr
= HARD_REGNO_NREGS (i
, rld
[r
].mode
);
5948 SET_HARD_REG_BIT (reg_is_output_reload
, i
+ nr
);
5951 if (rld
[r
].when_needed
!= RELOAD_OTHER
5952 && rld
[r
].when_needed
!= RELOAD_FOR_OUTPUT
5953 && rld
[r
].when_needed
!= RELOAD_FOR_INSN
)
5959 /* Deallocate the reload register for reload R. This is called from
5960 remove_address_replacements. */
5963 deallocate_reload_reg (r
)
5968 if (! rld
[r
].reg_rtx
)
5970 regno
= true_regnum (rld
[r
].reg_rtx
);
5972 if (spill_reg_order
[regno
] >= 0)
5973 clear_reload_reg_in_use (regno
, rld
[r
].opnum
, rld
[r
].when_needed
,
5975 reload_spill_index
[r
] = -1;
5978 /* If SMALL_REGISTER_CLASSES is non-zero, we may not have merged two
5979 reloads of the same item for fear that we might not have enough reload
5980 registers. However, normally they will get the same reload register
5981 and hence actually need not be loaded twice.
5983 Here we check for the most common case of this phenomenon: when we have
5984 a number of reloads for the same object, each of which were allocated
5985 the same reload_reg_rtx, that reload_reg_rtx is not used for any other
5986 reload, and is not modified in the insn itself. If we find such,
5987 merge all the reloads and set the resulting reload to RELOAD_OTHER.
5988 This will not increase the number of spill registers needed and will
5989 prevent redundant code. */
5992 merge_assigned_reloads (insn
)
5997 /* Scan all the reloads looking for ones that only load values and
5998 are not already RELOAD_OTHER and ones whose reload_reg_rtx are
5999 assigned and not modified by INSN. */
6001 for (i
= 0; i
< n_reloads
; i
++)
6003 int conflicting_input
= 0;
6004 int max_input_address_opnum
= -1;
6005 int min_conflicting_input_opnum
= MAX_RECOG_OPERANDS
;
6007 if (rld
[i
].in
== 0 || rld
[i
].when_needed
== RELOAD_OTHER
6008 || rld
[i
].out
!= 0 || rld
[i
].reg_rtx
== 0
6009 || reg_set_p (rld
[i
].reg_rtx
, insn
))
6012 /* Look at all other reloads. Ensure that the only use of this
6013 reload_reg_rtx is in a reload that just loads the same value
6014 as we do. Note that any secondary reloads must be of the identical
6015 class since the values, modes, and result registers are the
6016 same, so we need not do anything with any secondary reloads. */
6018 for (j
= 0; j
< n_reloads
; j
++)
6020 if (i
== j
|| rld
[j
].reg_rtx
== 0
6021 || ! reg_overlap_mentioned_p (rld
[j
].reg_rtx
,
6025 if (rld
[j
].when_needed
== RELOAD_FOR_INPUT_ADDRESS
6026 && rld
[j
].opnum
> max_input_address_opnum
)
6027 max_input_address_opnum
= rld
[j
].opnum
;
6029 /* If the reload regs aren't exactly the same (e.g, different modes)
6030 or if the values are different, we can't merge this reload.
6031 But if it is an input reload, we might still merge
6032 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_OTHER_ADDRESS reloads. */
6034 if (! rtx_equal_p (rld
[i
].reg_rtx
, rld
[j
].reg_rtx
)
6035 || rld
[j
].out
!= 0 || rld
[j
].in
== 0
6036 || ! rtx_equal_p (rld
[i
].in
, rld
[j
].in
))
6038 if (rld
[j
].when_needed
!= RELOAD_FOR_INPUT
6039 || ((rld
[i
].when_needed
!= RELOAD_FOR_INPUT_ADDRESS
6040 || rld
[i
].opnum
> rld
[j
].opnum
)
6041 && rld
[i
].when_needed
!= RELOAD_FOR_OTHER_ADDRESS
))
6043 conflicting_input
= 1;
6044 if (min_conflicting_input_opnum
> rld
[j
].opnum
)
6045 min_conflicting_input_opnum
= rld
[j
].opnum
;
6049 /* If all is OK, merge the reloads. Only set this to RELOAD_OTHER if
6050 we, in fact, found any matching reloads. */
6053 && max_input_address_opnum
<= min_conflicting_input_opnum
)
6055 for (j
= 0; j
< n_reloads
; j
++)
6056 if (i
!= j
&& rld
[j
].reg_rtx
!= 0
6057 && rtx_equal_p (rld
[i
].reg_rtx
, rld
[j
].reg_rtx
)
6058 && (! conflicting_input
6059 || rld
[j
].when_needed
== RELOAD_FOR_INPUT_ADDRESS
6060 || rld
[j
].when_needed
== RELOAD_FOR_OTHER_ADDRESS
))
6062 rld
[i
].when_needed
= RELOAD_OTHER
;
6064 reload_spill_index
[j
] = -1;
6065 transfer_replacements (i
, j
);
6068 /* If this is now RELOAD_OTHER, look for any reloads that load
6069 parts of this operand and set them to RELOAD_FOR_OTHER_ADDRESS
6070 if they were for inputs, RELOAD_OTHER for outputs. Note that
6071 this test is equivalent to looking for reloads for this operand
6074 if (rld
[i
].when_needed
== RELOAD_OTHER
)
6075 for (j
= 0; j
< n_reloads
; j
++)
6077 && rld
[j
].when_needed
!= RELOAD_OTHER
6078 && reg_overlap_mentioned_for_reload_p (rld
[j
].in
,
6081 = ((rld
[j
].when_needed
== RELOAD_FOR_INPUT_ADDRESS
6082 || rld
[j
].when_needed
== RELOAD_FOR_INPADDR_ADDRESS
)
6083 ? RELOAD_FOR_OTHER_ADDRESS
: RELOAD_OTHER
);
6088 /* These arrays are filled by emit_reload_insns and its subroutines. */
6089 static rtx input_reload_insns
[MAX_RECOG_OPERANDS
];
6090 static rtx other_input_address_reload_insns
= 0;
6091 static rtx other_input_reload_insns
= 0;
6092 static rtx input_address_reload_insns
[MAX_RECOG_OPERANDS
];
6093 static rtx inpaddr_address_reload_insns
[MAX_RECOG_OPERANDS
];
6094 static rtx output_reload_insns
[MAX_RECOG_OPERANDS
];
6095 static rtx output_address_reload_insns
[MAX_RECOG_OPERANDS
];
6096 static rtx outaddr_address_reload_insns
[MAX_RECOG_OPERANDS
];
6097 static rtx operand_reload_insns
= 0;
6098 static rtx other_operand_reload_insns
= 0;
6099 static rtx other_output_reload_insns
[MAX_RECOG_OPERANDS
];
6101 /* Values to be put in spill_reg_store are put here first. */
6102 static rtx new_spill_reg_store
[FIRST_PSEUDO_REGISTER
];
6103 static HARD_REG_SET reg_reloaded_died
;
6105 /* Generate insns to perform reload RL, which is for the insn in CHAIN and
6106 has the number J. OLD contains the value to be used as input. */
6109 emit_input_reload_insns (chain
, rl
, old
, j
)
6110 struct insn_chain
*chain
;
6115 rtx insn
= chain
->insn
;
6116 register rtx reloadreg
= rl
->reg_rtx
;
6117 rtx oldequiv_reg
= 0;
6120 enum machine_mode mode
;
6123 /* Determine the mode to reload in.
6124 This is very tricky because we have three to choose from.
6125 There is the mode the insn operand wants (rl->inmode).
6126 There is the mode of the reload register RELOADREG.
6127 There is the intrinsic mode of the operand, which we could find
6128 by stripping some SUBREGs.
6129 It turns out that RELOADREG's mode is irrelevant:
6130 we can change that arbitrarily.
6132 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
6133 then the reload reg may not support QImode moves, so use SImode.
6134 If foo is in memory due to spilling a pseudo reg, this is safe,
6135 because the QImode value is in the least significant part of a
6136 slot big enough for a SImode. If foo is some other sort of
6137 memory reference, then it is impossible to reload this case,
6138 so previous passes had better make sure this never happens.
6140 Then consider a one-word union which has SImode and one of its
6141 members is a float, being fetched as (SUBREG:SF union:SI).
6142 We must fetch that as SFmode because we could be loading into
6143 a float-only register. In this case OLD's mode is correct.
6145 Consider an immediate integer: it has VOIDmode. Here we need
6146 to get a mode from something else.
6148 In some cases, there is a fourth mode, the operand's
6149 containing mode. If the insn specifies a containing mode for
6150 this operand, it overrides all others.
6152 I am not sure whether the algorithm here is always right,
6153 but it does the right things in those cases. */
6155 mode
= GET_MODE (old
);
6156 if (mode
== VOIDmode
)
6159 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6160 /* If we need a secondary register for this operation, see if
6161 the value is already in a register in that class. Don't
6162 do this if the secondary register will be used as a scratch
6165 if (rl
->secondary_in_reload
>= 0
6166 && rl
->secondary_in_icode
== CODE_FOR_nothing
6169 = find_equiv_reg (old
, insn
,
6170 rld
[rl
->secondary_in_reload
].class,
6174 /* If reloading from memory, see if there is a register
6175 that already holds the same value. If so, reload from there.
6176 We can pass 0 as the reload_reg_p argument because
6177 any other reload has either already been emitted,
6178 in which case find_equiv_reg will see the reload-insn,
6179 or has yet to be emitted, in which case it doesn't matter
6180 because we will use this equiv reg right away. */
6182 if (oldequiv
== 0 && optimize
6183 && (GET_CODE (old
) == MEM
6184 || (GET_CODE (old
) == REG
6185 && REGNO (old
) >= FIRST_PSEUDO_REGISTER
6186 && reg_renumber
[REGNO (old
)] < 0)))
6187 oldequiv
= find_equiv_reg (old
, insn
, ALL_REGS
, -1, NULL
, 0, mode
);
6191 unsigned int regno
= true_regnum (oldequiv
);
6193 /* Don't use OLDEQUIV if any other reload changes it at an
6194 earlier stage of this insn or at this stage. */
6195 if (! free_for_value_p (regno
, rl
->mode
, rl
->opnum
, rl
->when_needed
,
6196 rl
->in
, const0_rtx
, j
, 0))
6199 /* If it is no cheaper to copy from OLDEQUIV into the
6200 reload register than it would be to move from memory,
6201 don't use it. Likewise, if we need a secondary register
6205 && ((REGNO_REG_CLASS (regno
) != rl
->class
6206 && (REGISTER_MOVE_COST (mode
, REGNO_REG_CLASS (regno
),
6208 >= MEMORY_MOVE_COST (mode
, rl
->class, 1)))
6209 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6210 || (SECONDARY_INPUT_RELOAD_CLASS (rl
->class,
6214 #ifdef SECONDARY_MEMORY_NEEDED
6215 || SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (regno
),
6223 /* delete_output_reload is only invoked properly if old contains
6224 the original pseudo register. Since this is replaced with a
6225 hard reg when RELOAD_OVERRIDE_IN is set, see if we can
6226 find the pseudo in RELOAD_IN_REG. */
6228 && reload_override_in
[j
]
6229 && GET_CODE (rl
->in_reg
) == REG
)
6236 else if (GET_CODE (oldequiv
) == REG
)
6237 oldequiv_reg
= oldequiv
;
6238 else if (GET_CODE (oldequiv
) == SUBREG
)
6239 oldequiv_reg
= SUBREG_REG (oldequiv
);
6241 /* If we are reloading from a register that was recently stored in
6242 with an output-reload, see if we can prove there was
6243 actually no need to store the old value in it. */
6245 if (optimize
&& GET_CODE (oldequiv
) == REG
6246 && REGNO (oldequiv
) < FIRST_PSEUDO_REGISTER
6247 && spill_reg_store
[REGNO (oldequiv
)]
6248 && GET_CODE (old
) == REG
6249 && (dead_or_set_p (insn
, spill_reg_stored_to
[REGNO (oldequiv
)])
6250 || rtx_equal_p (spill_reg_stored_to
[REGNO (oldequiv
)],
6252 delete_output_reload (insn
, j
, REGNO (oldequiv
));
6254 /* Encapsulate both RELOADREG and OLDEQUIV into that mode,
6255 then load RELOADREG from OLDEQUIV. Note that we cannot use
6256 gen_lowpart_common since it can do the wrong thing when
6257 RELOADREG has a multi-word mode. Note that RELOADREG
6258 must always be a REG here. */
6260 if (GET_MODE (reloadreg
) != mode
)
6261 reloadreg
= gen_rtx_REG (mode
, REGNO (reloadreg
));
6262 while (GET_CODE (oldequiv
) == SUBREG
&& GET_MODE (oldequiv
) != mode
)
6263 oldequiv
= SUBREG_REG (oldequiv
);
6264 if (GET_MODE (oldequiv
) != VOIDmode
6265 && mode
!= GET_MODE (oldequiv
))
6266 oldequiv
= gen_lowpart_SUBREG (mode
, oldequiv
);
6268 /* Switch to the right place to emit the reload insns. */
6269 switch (rl
->when_needed
)
6272 where
= &other_input_reload_insns
;
6274 case RELOAD_FOR_INPUT
:
6275 where
= &input_reload_insns
[rl
->opnum
];
6277 case RELOAD_FOR_INPUT_ADDRESS
:
6278 where
= &input_address_reload_insns
[rl
->opnum
];
6280 case RELOAD_FOR_INPADDR_ADDRESS
:
6281 where
= &inpaddr_address_reload_insns
[rl
->opnum
];
6283 case RELOAD_FOR_OUTPUT_ADDRESS
:
6284 where
= &output_address_reload_insns
[rl
->opnum
];
6286 case RELOAD_FOR_OUTADDR_ADDRESS
:
6287 where
= &outaddr_address_reload_insns
[rl
->opnum
];
6289 case RELOAD_FOR_OPERAND_ADDRESS
:
6290 where
= &operand_reload_insns
;
6292 case RELOAD_FOR_OPADDR_ADDR
:
6293 where
= &other_operand_reload_insns
;
6295 case RELOAD_FOR_OTHER_ADDRESS
:
6296 where
= &other_input_address_reload_insns
;
6302 push_to_sequence (*where
);
6304 /* Auto-increment addresses must be reloaded in a special way. */
6305 if (rl
->out
&& ! rl
->out_reg
)
6307 /* We are not going to bother supporting the case where a
6308 incremented register can't be copied directly from
6309 OLDEQUIV since this seems highly unlikely. */
6310 if (rl
->secondary_in_reload
>= 0)
6313 if (reload_inherited
[j
])
6314 oldequiv
= reloadreg
;
6316 old
= XEXP (rl
->in_reg
, 0);
6318 if (optimize
&& GET_CODE (oldequiv
) == REG
6319 && REGNO (oldequiv
) < FIRST_PSEUDO_REGISTER
6320 && spill_reg_store
[REGNO (oldequiv
)]
6321 && GET_CODE (old
) == REG
6322 && (dead_or_set_p (insn
,
6323 spill_reg_stored_to
[REGNO (oldequiv
)])
6324 || rtx_equal_p (spill_reg_stored_to
[REGNO (oldequiv
)],
6326 delete_output_reload (insn
, j
, REGNO (oldequiv
));
6328 /* Prevent normal processing of this reload. */
6330 /* Output a special code sequence for this case. */
6331 new_spill_reg_store
[REGNO (reloadreg
)]
6332 = inc_for_reload (reloadreg
, oldequiv
, rl
->out
,
6336 /* If we are reloading a pseudo-register that was set by the previous
6337 insn, see if we can get rid of that pseudo-register entirely
6338 by redirecting the previous insn into our reload register. */
6340 else if (optimize
&& GET_CODE (old
) == REG
6341 && REGNO (old
) >= FIRST_PSEUDO_REGISTER
6342 && dead_or_set_p (insn
, old
)
6343 /* This is unsafe if some other reload
6344 uses the same reg first. */
6345 && ! conflicts_with_override (reloadreg
)
6346 && free_for_value_p (REGNO (reloadreg
), rl
->mode
, rl
->opnum
,
6347 rl
->when_needed
, old
, rl
->out
, j
, 0))
6349 rtx temp
= PREV_INSN (insn
);
6350 while (temp
&& GET_CODE (temp
) == NOTE
)
6351 temp
= PREV_INSN (temp
);
6353 && GET_CODE (temp
) == INSN
6354 && GET_CODE (PATTERN (temp
)) == SET
6355 && SET_DEST (PATTERN (temp
)) == old
6356 /* Make sure we can access insn_operand_constraint. */
6357 && asm_noperands (PATTERN (temp
)) < 0
6358 /* This is unsafe if prev insn rejects our reload reg. */
6359 && constraint_accepts_reg_p (insn_data
[recog_memoized (temp
)].operand
[0].constraint
,
6361 /* This is unsafe if operand occurs more than once in current
6362 insn. Perhaps some occurrences aren't reloaded. */
6363 && count_occurrences (PATTERN (insn
), old
, 0) == 1
6364 /* Don't risk splitting a matching pair of operands. */
6365 && ! reg_mentioned_p (old
, SET_SRC (PATTERN (temp
))))
6367 /* Store into the reload register instead of the pseudo. */
6368 SET_DEST (PATTERN (temp
)) = reloadreg
;
6370 /* If the previous insn is an output reload, the source is
6371 a reload register, and its spill_reg_store entry will
6372 contain the previous destination. This is now
6374 if (GET_CODE (SET_SRC (PATTERN (temp
))) == REG
6375 && REGNO (SET_SRC (PATTERN (temp
))) < FIRST_PSEUDO_REGISTER
)
6377 spill_reg_store
[REGNO (SET_SRC (PATTERN (temp
)))] = 0;
6378 spill_reg_stored_to
[REGNO (SET_SRC (PATTERN (temp
)))] = 0;
6381 /* If these are the only uses of the pseudo reg,
6382 pretend for GDB it lives in the reload reg we used. */
6383 if (REG_N_DEATHS (REGNO (old
)) == 1
6384 && REG_N_SETS (REGNO (old
)) == 1)
6386 reg_renumber
[REGNO (old
)] = REGNO (rl
->reg_rtx
);
6387 alter_reg (REGNO (old
), -1);
6393 /* We can't do that, so output an insn to load RELOADREG. */
6395 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6396 /* If we have a secondary reload, pick up the secondary register
6397 and icode, if any. If OLDEQUIV and OLD are different or
6398 if this is an in-out reload, recompute whether or not we
6399 still need a secondary register and what the icode should
6400 be. If we still need a secondary register and the class or
6401 icode is different, go back to reloading from OLD if using
6402 OLDEQUIV means that we got the wrong type of register. We
6403 cannot have different class or icode due to an in-out reload
6404 because we don't make such reloads when both the input and
6405 output need secondary reload registers. */
6407 if (! special
&& rl
->secondary_in_reload
>= 0)
6409 rtx second_reload_reg
= 0;
6410 int secondary_reload
= rl
->secondary_in_reload
;
6411 rtx real_oldequiv
= oldequiv
;
6414 enum insn_code icode
;
6416 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
6417 and similarly for OLD.
6418 See comments in get_secondary_reload in reload.c. */
6419 /* If it is a pseudo that cannot be replaced with its
6420 equivalent MEM, we must fall back to reload_in, which
6421 will have all the necessary substitutions registered.
6422 Likewise for a pseudo that can't be replaced with its
6423 equivalent constant.
6425 Take extra care for subregs of such pseudos. Note that
6426 we cannot use reg_equiv_mem in this case because it is
6427 not in the right mode. */
6430 if (GET_CODE (tmp
) == SUBREG
)
6431 tmp
= SUBREG_REG (tmp
);
6432 if (GET_CODE (tmp
) == REG
6433 && REGNO (tmp
) >= FIRST_PSEUDO_REGISTER
6434 && (reg_equiv_memory_loc
[REGNO (tmp
)] != 0
6435 || reg_equiv_constant
[REGNO (tmp
)] != 0))
6437 if (! reg_equiv_mem
[REGNO (tmp
)]
6438 || num_not_at_initial_offset
6439 || GET_CODE (oldequiv
) == SUBREG
)
6440 real_oldequiv
= rl
->in
;
6442 real_oldequiv
= reg_equiv_mem
[REGNO (tmp
)];
6446 if (GET_CODE (tmp
) == SUBREG
)
6447 tmp
= SUBREG_REG (tmp
);
6448 if (GET_CODE (tmp
) == REG
6449 && REGNO (tmp
) >= FIRST_PSEUDO_REGISTER
6450 && (reg_equiv_memory_loc
[REGNO (tmp
)] != 0
6451 || reg_equiv_constant
[REGNO (tmp
)] != 0))
6453 if (! reg_equiv_mem
[REGNO (tmp
)]
6454 || num_not_at_initial_offset
6455 || GET_CODE (old
) == SUBREG
)
6458 real_old
= reg_equiv_mem
[REGNO (tmp
)];
6461 second_reload_reg
= rld
[secondary_reload
].reg_rtx
;
6462 icode
= rl
->secondary_in_icode
;
6464 if ((old
!= oldequiv
&& ! rtx_equal_p (old
, oldequiv
))
6465 || (rl
->in
!= 0 && rl
->out
!= 0))
6467 enum reg_class new_class
6468 = SECONDARY_INPUT_RELOAD_CLASS (rl
->class,
6469 mode
, real_oldequiv
);
6471 if (new_class
== NO_REGS
)
6472 second_reload_reg
= 0;
6475 enum insn_code new_icode
;
6476 enum machine_mode new_mode
;
6478 if (! TEST_HARD_REG_BIT (reg_class_contents
[(int) new_class
],
6479 REGNO (second_reload_reg
)))
6480 oldequiv
= old
, real_oldequiv
= real_old
;
6483 new_icode
= reload_in_optab
[(int) mode
];
6484 if (new_icode
!= CODE_FOR_nothing
6485 && ((insn_data
[(int) new_icode
].operand
[0].predicate
6486 && ! ((*insn_data
[(int) new_icode
].operand
[0].predicate
)
6488 || (insn_data
[(int) new_icode
].operand
[1].predicate
6489 && ! ((*insn_data
[(int) new_icode
].operand
[1].predicate
)
6490 (real_oldequiv
, mode
)))))
6491 new_icode
= CODE_FOR_nothing
;
6493 if (new_icode
== CODE_FOR_nothing
)
6496 new_mode
= insn_data
[(int) new_icode
].operand
[2].mode
;
6498 if (GET_MODE (second_reload_reg
) != new_mode
)
6500 if (!HARD_REGNO_MODE_OK (REGNO (second_reload_reg
),
6502 oldequiv
= old
, real_oldequiv
= real_old
;
6505 = gen_rtx_REG (new_mode
,
6506 REGNO (second_reload_reg
));
6512 /* If we still need a secondary reload register, check
6513 to see if it is being used as a scratch or intermediate
6514 register and generate code appropriately. If we need
6515 a scratch register, use REAL_OLDEQUIV since the form of
6516 the insn may depend on the actual address if it is
6519 if (second_reload_reg
)
6521 if (icode
!= CODE_FOR_nothing
)
6523 emit_insn (GEN_FCN (icode
) (reloadreg
, real_oldequiv
,
6524 second_reload_reg
));
6529 /* See if we need a scratch register to load the
6530 intermediate register (a tertiary reload). */
6531 enum insn_code tertiary_icode
6532 = rld
[secondary_reload
].secondary_in_icode
;
6534 if (tertiary_icode
!= CODE_FOR_nothing
)
6536 rtx third_reload_reg
6537 = rld
[rld
[secondary_reload
].secondary_in_reload
].reg_rtx
;
6539 emit_insn ((GEN_FCN (tertiary_icode
)
6540 (second_reload_reg
, real_oldequiv
,
6541 third_reload_reg
)));
6544 gen_reload (second_reload_reg
, real_oldequiv
,
6548 oldequiv
= second_reload_reg
;
6554 if (! special
&& ! rtx_equal_p (reloadreg
, oldequiv
))
6556 rtx real_oldequiv
= oldequiv
;
6558 if ((GET_CODE (oldequiv
) == REG
6559 && REGNO (oldequiv
) >= FIRST_PSEUDO_REGISTER
6560 && (reg_equiv_memory_loc
[REGNO (oldequiv
)] != 0
6561 || reg_equiv_constant
[REGNO (oldequiv
)] != 0))
6562 || (GET_CODE (oldequiv
) == SUBREG
6563 && GET_CODE (SUBREG_REG (oldequiv
)) == REG
6564 && (REGNO (SUBREG_REG (oldequiv
))
6565 >= FIRST_PSEUDO_REGISTER
)
6566 && ((reg_equiv_memory_loc
6567 [REGNO (SUBREG_REG (oldequiv
))] != 0)
6568 || (reg_equiv_constant
6569 [REGNO (SUBREG_REG (oldequiv
))] != 0)))
6570 || (CONSTANT_P (oldequiv
)
6571 && PREFERRED_RELOAD_CLASS (oldequiv
,
6572 REGNO_REG_CLASS (REGNO (reloadreg
))) == NO_REGS
))
6573 real_oldequiv
= rl
->in
;
6574 gen_reload (reloadreg
, real_oldequiv
, rl
->opnum
,
6578 if (flag_non_call_exceptions
)
6579 copy_eh_notes (insn
, get_insns ());
6581 /* End this sequence. */
6582 *where
= get_insns ();
6585 /* Update reload_override_in so that delete_address_reloads_1
6586 can see the actual register usage. */
6588 reload_override_in
[j
] = oldequiv
;
6591 /* Generate insns to for the output reload RL, which is for the insn described
6592 by CHAIN and has the number J. */
6594 emit_output_reload_insns (chain
, rl
, j
)
6595 struct insn_chain
*chain
;
6599 rtx reloadreg
= rl
->reg_rtx
;
6600 rtx insn
= chain
->insn
;
6603 enum machine_mode mode
= GET_MODE (old
);
6606 if (rl
->when_needed
== RELOAD_OTHER
)
6609 push_to_sequence (output_reload_insns
[rl
->opnum
]);
6611 /* Determine the mode to reload in.
6612 See comments above (for input reloading). */
6614 if (mode
== VOIDmode
)
6616 /* VOIDmode should never happen for an output. */
6617 if (asm_noperands (PATTERN (insn
)) < 0)
6618 /* It's the compiler's fault. */
6619 fatal_insn ("VOIDmode on an output", insn
);
6620 error_for_asm (insn
, "output operand is constant in `asm'");
6621 /* Prevent crash--use something we know is valid. */
6623 old
= gen_rtx_REG (mode
, REGNO (reloadreg
));
6626 if (GET_MODE (reloadreg
) != mode
)
6627 reloadreg
= gen_rtx_REG (mode
, REGNO (reloadreg
));
6629 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
6631 /* If we need two reload regs, set RELOADREG to the intermediate
6632 one, since it will be stored into OLD. We might need a secondary
6633 register only for an input reload, so check again here. */
6635 if (rl
->secondary_out_reload
>= 0)
6639 if (GET_CODE (old
) == REG
&& REGNO (old
) >= FIRST_PSEUDO_REGISTER
6640 && reg_equiv_mem
[REGNO (old
)] != 0)
6641 real_old
= reg_equiv_mem
[REGNO (old
)];
6643 if ((SECONDARY_OUTPUT_RELOAD_CLASS (rl
->class,
6647 rtx second_reloadreg
= reloadreg
;
6648 reloadreg
= rld
[rl
->secondary_out_reload
].reg_rtx
;
6650 /* See if RELOADREG is to be used as a scratch register
6651 or as an intermediate register. */
6652 if (rl
->secondary_out_icode
!= CODE_FOR_nothing
)
6654 emit_insn ((GEN_FCN (rl
->secondary_out_icode
)
6655 (real_old
, second_reloadreg
, reloadreg
)));
6660 /* See if we need both a scratch and intermediate reload
6663 int secondary_reload
= rl
->secondary_out_reload
;
6664 enum insn_code tertiary_icode
6665 = rld
[secondary_reload
].secondary_out_icode
;
6667 if (GET_MODE (reloadreg
) != mode
)
6668 reloadreg
= gen_rtx_REG (mode
, REGNO (reloadreg
));
6670 if (tertiary_icode
!= CODE_FOR_nothing
)
6673 = rld
[rld
[secondary_reload
].secondary_out_reload
].reg_rtx
;
6676 /* Copy primary reload reg to secondary reload reg.
6677 (Note that these have been swapped above, then
6678 secondary reload reg to OLD using our insn.) */
6680 /* If REAL_OLD is a paradoxical SUBREG, remove it
6681 and try to put the opposite SUBREG on
6683 if (GET_CODE (real_old
) == SUBREG
6684 && (GET_MODE_SIZE (GET_MODE (real_old
))
6685 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (real_old
))))
6686 && 0 != (tem
= gen_lowpart_common
6687 (GET_MODE (SUBREG_REG (real_old
)),
6689 real_old
= SUBREG_REG (real_old
), reloadreg
= tem
;
6691 gen_reload (reloadreg
, second_reloadreg
,
6692 rl
->opnum
, rl
->when_needed
);
6693 emit_insn ((GEN_FCN (tertiary_icode
)
6694 (real_old
, reloadreg
, third_reloadreg
)));
6699 /* Copy between the reload regs here and then to
6702 gen_reload (reloadreg
, second_reloadreg
,
6703 rl
->opnum
, rl
->when_needed
);
6709 /* Output the last reload insn. */
6714 /* Don't output the last reload if OLD is not the dest of
6715 INSN and is in the src and is clobbered by INSN. */
6716 if (! flag_expensive_optimizations
6717 || GET_CODE (old
) != REG
6718 || !(set
= single_set (insn
))
6719 || rtx_equal_p (old
, SET_DEST (set
))
6720 || !reg_mentioned_p (old
, SET_SRC (set
))
6721 || !regno_clobbered_p (REGNO (old
), insn
, rl
->mode
, 0))
6722 gen_reload (old
, reloadreg
, rl
->opnum
,
6726 /* Look at all insns we emitted, just to be safe. */
6727 for (p
= get_insns (); p
; p
= NEXT_INSN (p
))
6730 rtx pat
= PATTERN (p
);
6732 /* If this output reload doesn't come from a spill reg,
6733 clear any memory of reloaded copies of the pseudo reg.
6734 If this output reload comes from a spill reg,
6735 reg_has_output_reload will make this do nothing. */
6736 note_stores (pat
, forget_old_reloads_1
, NULL
);
6738 if (reg_mentioned_p (rl
->reg_rtx
, pat
))
6740 rtx set
= single_set (insn
);
6741 if (reload_spill_index
[j
] < 0
6743 && SET_SRC (set
) == rl
->reg_rtx
)
6745 int src
= REGNO (SET_SRC (set
));
6747 reload_spill_index
[j
] = src
;
6748 SET_HARD_REG_BIT (reg_is_output_reload
, src
);
6749 if (find_regno_note (insn
, REG_DEAD
, src
))
6750 SET_HARD_REG_BIT (reg_reloaded_died
, src
);
6752 if (REGNO (rl
->reg_rtx
) < FIRST_PSEUDO_REGISTER
)
6754 int s
= rl
->secondary_out_reload
;
6755 set
= single_set (p
);
6756 /* If this reload copies only to the secondary reload
6757 register, the secondary reload does the actual
6759 if (s
>= 0 && set
== NULL_RTX
)
6760 /* We can't tell what function the secondary reload
6761 has and where the actual store to the pseudo is
6762 made; leave new_spill_reg_store alone. */
6765 && SET_SRC (set
) == rl
->reg_rtx
6766 && SET_DEST (set
) == rld
[s
].reg_rtx
)
6768 /* Usually the next instruction will be the
6769 secondary reload insn; if we can confirm
6770 that it is, setting new_spill_reg_store to
6771 that insn will allow an extra optimization. */
6772 rtx s_reg
= rld
[s
].reg_rtx
;
6773 rtx next
= NEXT_INSN (p
);
6774 rld
[s
].out
= rl
->out
;
6775 rld
[s
].out_reg
= rl
->out_reg
;
6776 set
= single_set (next
);
6777 if (set
&& SET_SRC (set
) == s_reg
6778 && ! new_spill_reg_store
[REGNO (s_reg
)])
6780 SET_HARD_REG_BIT (reg_is_output_reload
,
6782 new_spill_reg_store
[REGNO (s_reg
)] = next
;
6786 new_spill_reg_store
[REGNO (rl
->reg_rtx
)] = p
;
6791 if (rl
->when_needed
== RELOAD_OTHER
)
6793 emit_insns (other_output_reload_insns
[rl
->opnum
]);
6794 other_output_reload_insns
[rl
->opnum
] = get_insns ();
6797 output_reload_insns
[rl
->opnum
] = get_insns ();
6799 if (flag_non_call_exceptions
)
6800 copy_eh_notes (insn
, get_insns ());
6805 /* Do input reloading for reload RL, which is for the insn described by CHAIN
6806 and has the number J. */
6808 do_input_reload (chain
, rl
, j
)
6809 struct insn_chain
*chain
;
6813 int expect_occurrences
= 1;
6814 rtx insn
= chain
->insn
;
6815 rtx old
= (rl
->in
&& GET_CODE (rl
->in
) == MEM
6816 ? rl
->in_reg
: rl
->in
);
6819 /* AUTO_INC reloads need to be handled even if inherited. We got an
6820 AUTO_INC reload if reload_out is set but reload_out_reg isn't. */
6821 && (! reload_inherited
[j
] || (rl
->out
&& ! rl
->out_reg
))
6822 && ! rtx_equal_p (rl
->reg_rtx
, old
)
6823 && rl
->reg_rtx
!= 0)
6824 emit_input_reload_insns (chain
, rld
+ j
, old
, j
);
6826 /* When inheriting a wider reload, we have a MEM in rl->in,
6827 e.g. inheriting a SImode output reload for
6828 (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */
6829 if (optimize
&& reload_inherited
[j
] && rl
->in
6830 && GET_CODE (rl
->in
) == MEM
6831 && GET_CODE (rl
->in_reg
) == MEM
6832 && reload_spill_index
[j
] >= 0
6833 && TEST_HARD_REG_BIT (reg_reloaded_valid
, reload_spill_index
[j
]))
6836 = count_occurrences (PATTERN (insn
), rl
->in
, 0) == 1 ? 0 : -1;
6837 rl
->in
= regno_reg_rtx
[reg_reloaded_contents
[reload_spill_index
[j
]]];
6840 /* If we are reloading a register that was recently stored in with an
6841 output-reload, see if we can prove there was
6842 actually no need to store the old value in it. */
6845 && (reload_inherited
[j
] || reload_override_in
[j
])
6847 && GET_CODE (rl
->reg_rtx
) == REG
6848 && spill_reg_store
[REGNO (rl
->reg_rtx
)] != 0
6850 /* There doesn't seem to be any reason to restrict this to pseudos
6851 and doing so loses in the case where we are copying from a
6852 register of the wrong class. */
6853 && (REGNO (spill_reg_stored_to
[REGNO (rl
->reg_rtx
)])
6854 >= FIRST_PSEUDO_REGISTER
)
6856 /* The insn might have already some references to stackslots
6857 replaced by MEMs, while reload_out_reg still names the
6859 && (dead_or_set_p (insn
,
6860 spill_reg_stored_to
[REGNO (rl
->reg_rtx
)])
6861 || rtx_equal_p (spill_reg_stored_to
[REGNO (rl
->reg_rtx
)],
6863 delete_output_reload (insn
, j
, REGNO (rl
->reg_rtx
));
6866 /* Do output reloading for reload RL, which is for the insn described by
6867 CHAIN and has the number J.
6868 ??? At some point we need to support handling output reloads of
6869 JUMP_INSNs or insns that set cc0. */
6871 do_output_reload (chain
, rl
, j
)
6872 struct insn_chain
*chain
;
6877 rtx insn
= chain
->insn
;
6878 /* If this is an output reload that stores something that is
6879 not loaded in this same reload, see if we can eliminate a previous
6881 rtx pseudo
= rl
->out_reg
;
6884 && GET_CODE (pseudo
) == REG
6885 && ! rtx_equal_p (rl
->in_reg
, pseudo
)
6886 && REGNO (pseudo
) >= FIRST_PSEUDO_REGISTER
6887 && reg_last_reload_reg
[REGNO (pseudo
)])
6889 int pseudo_no
= REGNO (pseudo
);
6890 int last_regno
= REGNO (reg_last_reload_reg
[pseudo_no
]);
6892 /* We don't need to test full validity of last_regno for
6893 inherit here; we only want to know if the store actually
6894 matches the pseudo. */
6895 if (TEST_HARD_REG_BIT (reg_reloaded_valid
, last_regno
)
6896 && reg_reloaded_contents
[last_regno
] == pseudo_no
6897 && spill_reg_store
[last_regno
]
6898 && rtx_equal_p (pseudo
, spill_reg_stored_to
[last_regno
]))
6899 delete_output_reload (insn
, j
, last_regno
);
6904 || rl
->reg_rtx
== old
6905 || rl
->reg_rtx
== 0)
6908 /* An output operand that dies right away does need a reload,
6909 but need not be copied from it. Show the new location in the
6911 if ((GET_CODE (old
) == REG
|| GET_CODE (old
) == SCRATCH
)
6912 && (note
= find_reg_note (insn
, REG_UNUSED
, old
)) != 0)
6914 XEXP (note
, 0) = rl
->reg_rtx
;
6917 /* Likewise for a SUBREG of an operand that dies. */
6918 else if (GET_CODE (old
) == SUBREG
6919 && GET_CODE (SUBREG_REG (old
)) == REG
6920 && 0 != (note
= find_reg_note (insn
, REG_UNUSED
,
6923 XEXP (note
, 0) = gen_lowpart_common (GET_MODE (old
),
6927 else if (GET_CODE (old
) == SCRATCH
)
6928 /* If we aren't optimizing, there won't be a REG_UNUSED note,
6929 but we don't want to make an output reload. */
6932 /* If is a JUMP_INSN, we can't support output reloads yet. */
6933 if (GET_CODE (insn
) == JUMP_INSN
)
6936 emit_output_reload_insns (chain
, rld
+ j
, j
);
6939 /* Output insns to reload values in and out of the chosen reload regs. */
6942 emit_reload_insns (chain
)
6943 struct insn_chain
*chain
;
6945 rtx insn
= chain
->insn
;
6948 rtx following_insn
= NEXT_INSN (insn
);
6949 rtx before_insn
= PREV_INSN (insn
);
6951 CLEAR_HARD_REG_SET (reg_reloaded_died
);
6953 for (j
= 0; j
< reload_n_operands
; j
++)
6954 input_reload_insns
[j
] = input_address_reload_insns
[j
]
6955 = inpaddr_address_reload_insns
[j
]
6956 = output_reload_insns
[j
] = output_address_reload_insns
[j
]
6957 = outaddr_address_reload_insns
[j
]
6958 = other_output_reload_insns
[j
] = 0;
6959 other_input_address_reload_insns
= 0;
6960 other_input_reload_insns
= 0;
6961 operand_reload_insns
= 0;
6962 other_operand_reload_insns
= 0;
6964 /* Dump reloads into the dump file. */
6967 fprintf (rtl_dump_file
, "\nReloads for insn # %d\n", INSN_UID (insn
));
6968 debug_reload_to_stream (rtl_dump_file
);
6971 /* Now output the instructions to copy the data into and out of the
6972 reload registers. Do these in the order that the reloads were reported,
6973 since reloads of base and index registers precede reloads of operands
6974 and the operands may need the base and index registers reloaded. */
6976 for (j
= 0; j
< n_reloads
; j
++)
6979 && REGNO (rld
[j
].reg_rtx
) < FIRST_PSEUDO_REGISTER
)
6980 new_spill_reg_store
[REGNO (rld
[j
].reg_rtx
)] = 0;
6982 do_input_reload (chain
, rld
+ j
, j
);
6983 do_output_reload (chain
, rld
+ j
, j
);
6986 /* Now write all the insns we made for reloads in the order expected by
6987 the allocation functions. Prior to the insn being reloaded, we write
6988 the following reloads:
6990 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
6992 RELOAD_OTHER reloads.
6994 For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
6995 by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
6996 RELOAD_FOR_INPUT reload for the operand.
6998 RELOAD_FOR_OPADDR_ADDRS reloads.
7000 RELOAD_FOR_OPERAND_ADDRESS reloads.
7002 After the insn being reloaded, we write the following:
7004 For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
7005 by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
7006 RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
7007 reloads for the operand. The RELOAD_OTHER output reloads are
7008 output in descending order by reload number. */
7010 emit_insns_before (other_input_address_reload_insns
, insn
);
7011 emit_insns_before (other_input_reload_insns
, insn
);
7013 for (j
= 0; j
< reload_n_operands
; j
++)
7015 emit_insns_before (inpaddr_address_reload_insns
[j
], insn
);
7016 emit_insns_before (input_address_reload_insns
[j
], insn
);
7017 emit_insns_before (input_reload_insns
[j
], insn
);
7020 emit_insns_before (other_operand_reload_insns
, insn
);
7021 emit_insns_before (operand_reload_insns
, insn
);
7023 for (j
= 0; j
< reload_n_operands
; j
++)
7025 emit_insns_before (outaddr_address_reload_insns
[j
], following_insn
);
7026 emit_insns_before (output_address_reload_insns
[j
], following_insn
);
7027 emit_insns_before (output_reload_insns
[j
], following_insn
);
7028 emit_insns_before (other_output_reload_insns
[j
], following_insn
);
7031 /* Keep basic block info up to date. */
7034 if (BLOCK_HEAD (chain
->block
) == insn
)
7035 BLOCK_HEAD (chain
->block
) = NEXT_INSN (before_insn
);
7036 if (BLOCK_END (chain
->block
) == insn
)
7037 BLOCK_END (chain
->block
) = PREV_INSN (following_insn
);
7040 /* For all the spill regs newly reloaded in this instruction,
7041 record what they were reloaded from, so subsequent instructions
7042 can inherit the reloads.
7044 Update spill_reg_store for the reloads of this insn.
7045 Copy the elements that were updated in the loop above. */
7047 for (j
= 0; j
< n_reloads
; j
++)
7049 register int r
= reload_order
[j
];
7050 register int i
= reload_spill_index
[r
];
7052 /* If this is a non-inherited input reload from a pseudo, we must
7053 clear any memory of a previous store to the same pseudo. Only do
7054 something if there will not be an output reload for the pseudo
7056 if (rld
[r
].in_reg
!= 0
7057 && ! (reload_inherited
[r
] || reload_override_in
[r
]))
7059 rtx reg
= rld
[r
].in_reg
;
7061 if (GET_CODE (reg
) == SUBREG
)
7062 reg
= SUBREG_REG (reg
);
7064 if (GET_CODE (reg
) == REG
7065 && REGNO (reg
) >= FIRST_PSEUDO_REGISTER
7066 && ! reg_has_output_reload
[REGNO (reg
)])
7068 int nregno
= REGNO (reg
);
7070 if (reg_last_reload_reg
[nregno
])
7072 int last_regno
= REGNO (reg_last_reload_reg
[nregno
]);
7074 if (reg_reloaded_contents
[last_regno
] == nregno
)
7075 spill_reg_store
[last_regno
] = 0;
7080 /* I is nonneg if this reload used a register.
7081 If rld[r].reg_rtx is 0, this is an optional reload
7082 that we opted to ignore. */
7084 if (i
>= 0 && rld
[r
].reg_rtx
!= 0)
7086 int nr
= HARD_REGNO_NREGS (i
, GET_MODE (rld
[r
].reg_rtx
));
7088 int part_reaches_end
= 0;
7089 int all_reaches_end
= 1;
7091 /* For a multi register reload, we need to check if all or part
7092 of the value lives to the end. */
7093 for (k
= 0; k
< nr
; k
++)
7095 if (reload_reg_reaches_end_p (i
+ k
, rld
[r
].opnum
,
7096 rld
[r
].when_needed
))
7097 part_reaches_end
= 1;
7099 all_reaches_end
= 0;
7102 /* Ignore reloads that don't reach the end of the insn in
7104 if (all_reaches_end
)
7106 /* First, clear out memory of what used to be in this spill reg.
7107 If consecutive registers are used, clear them all. */
7109 for (k
= 0; k
< nr
; k
++)
7110 CLEAR_HARD_REG_BIT (reg_reloaded_valid
, i
+ k
);
7112 /* Maybe the spill reg contains a copy of reload_out. */
7114 && (GET_CODE (rld
[r
].out
) == REG
7118 || GET_CODE (rld
[r
].out_reg
) == REG
))
7120 rtx out
= (GET_CODE (rld
[r
].out
) == REG
7124 /* AUTO_INC */ : XEXP (rld
[r
].in_reg
, 0));
7125 register int nregno
= REGNO (out
);
7126 int nnr
= (nregno
>= FIRST_PSEUDO_REGISTER
? 1
7127 : HARD_REGNO_NREGS (nregno
,
7128 GET_MODE (rld
[r
].reg_rtx
)));
7130 spill_reg_store
[i
] = new_spill_reg_store
[i
];
7131 spill_reg_stored_to
[i
] = out
;
7132 reg_last_reload_reg
[nregno
] = rld
[r
].reg_rtx
;
7134 /* If NREGNO is a hard register, it may occupy more than
7135 one register. If it does, say what is in the
7136 rest of the registers assuming that both registers
7137 agree on how many words the object takes. If not,
7138 invalidate the subsequent registers. */
7140 if (nregno
< FIRST_PSEUDO_REGISTER
)
7141 for (k
= 1; k
< nnr
; k
++)
7142 reg_last_reload_reg
[nregno
+ k
]
7144 ? gen_rtx_REG (reg_raw_mode
[REGNO (rld
[r
].reg_rtx
) + k
],
7145 REGNO (rld
[r
].reg_rtx
) + k
)
7148 /* Now do the inverse operation. */
7149 for (k
= 0; k
< nr
; k
++)
7151 CLEAR_HARD_REG_BIT (reg_reloaded_dead
, i
+ k
);
7152 reg_reloaded_contents
[i
+ k
]
7153 = (nregno
>= FIRST_PSEUDO_REGISTER
|| nr
!= nnr
7156 reg_reloaded_insn
[i
+ k
] = insn
;
7157 SET_HARD_REG_BIT (reg_reloaded_valid
, i
+ k
);
7161 /* Maybe the spill reg contains a copy of reload_in. Only do
7162 something if there will not be an output reload for
7163 the register being reloaded. */
7164 else if (rld
[r
].out_reg
== 0
7166 && ((GET_CODE (rld
[r
].in
) == REG
7167 && REGNO (rld
[r
].in
) >= FIRST_PSEUDO_REGISTER
7168 && ! reg_has_output_reload
[REGNO (rld
[r
].in
)])
7169 || (GET_CODE (rld
[r
].in_reg
) == REG
7170 && ! reg_has_output_reload
[REGNO (rld
[r
].in_reg
)]))
7171 && ! reg_set_p (rld
[r
].reg_rtx
, PATTERN (insn
)))
7173 register int nregno
;
7176 if (GET_CODE (rld
[r
].in
) == REG
7177 && REGNO (rld
[r
].in
) >= FIRST_PSEUDO_REGISTER
)
7178 nregno
= REGNO (rld
[r
].in
);
7179 else if (GET_CODE (rld
[r
].in_reg
) == REG
)
7180 nregno
= REGNO (rld
[r
].in_reg
);
7182 nregno
= REGNO (XEXP (rld
[r
].in_reg
, 0));
7184 nnr
= (nregno
>= FIRST_PSEUDO_REGISTER
? 1
7185 : HARD_REGNO_NREGS (nregno
,
7186 GET_MODE (rld
[r
].reg_rtx
)));
7188 reg_last_reload_reg
[nregno
] = rld
[r
].reg_rtx
;
7190 if (nregno
< FIRST_PSEUDO_REGISTER
)
7191 for (k
= 1; k
< nnr
; k
++)
7192 reg_last_reload_reg
[nregno
+ k
]
7194 ? gen_rtx_REG (reg_raw_mode
[REGNO (rld
[r
].reg_rtx
) + k
],
7195 REGNO (rld
[r
].reg_rtx
) + k
)
7198 /* Unless we inherited this reload, show we haven't
7199 recently done a store.
7200 Previous stores of inherited auto_inc expressions
7201 also have to be discarded. */
7202 if (! reload_inherited
[r
]
7203 || (rld
[r
].out
&& ! rld
[r
].out_reg
))
7204 spill_reg_store
[i
] = 0;
7206 for (k
= 0; k
< nr
; k
++)
7208 CLEAR_HARD_REG_BIT (reg_reloaded_dead
, i
+ k
);
7209 reg_reloaded_contents
[i
+ k
]
7210 = (nregno
>= FIRST_PSEUDO_REGISTER
|| nr
!= nnr
7213 reg_reloaded_insn
[i
+ k
] = insn
;
7214 SET_HARD_REG_BIT (reg_reloaded_valid
, i
+ k
);
7219 /* However, if part of the reload reaches the end, then we must
7220 invalidate the old info for the part that survives to the end. */
7221 else if (part_reaches_end
)
7223 for (k
= 0; k
< nr
; k
++)
7224 if (reload_reg_reaches_end_p (i
+ k
,
7226 rld
[r
].when_needed
))
7227 CLEAR_HARD_REG_BIT (reg_reloaded_valid
, i
+ k
);
7231 /* The following if-statement was #if 0'd in 1.34 (or before...).
7232 It's reenabled in 1.35 because supposedly nothing else
7233 deals with this problem. */
7235 /* If a register gets output-reloaded from a non-spill register,
7236 that invalidates any previous reloaded copy of it.
7237 But forget_old_reloads_1 won't get to see it, because
7238 it thinks only about the original insn. So invalidate it here. */
7239 if (i
< 0 && rld
[r
].out
!= 0
7240 && (GET_CODE (rld
[r
].out
) == REG
7241 || (GET_CODE (rld
[r
].out
) == MEM
7242 && GET_CODE (rld
[r
].out_reg
) == REG
)))
7244 rtx out
= (GET_CODE (rld
[r
].out
) == REG
7245 ? rld
[r
].out
: rld
[r
].out_reg
);
7246 register int nregno
= REGNO (out
);
7247 if (nregno
>= FIRST_PSEUDO_REGISTER
)
7249 rtx src_reg
, store_insn
= NULL_RTX
;
7251 reg_last_reload_reg
[nregno
] = 0;
7253 /* If we can find a hard register that is stored, record
7254 the storing insn so that we may delete this insn with
7255 delete_output_reload. */
7256 src_reg
= rld
[r
].reg_rtx
;
7258 /* If this is an optional reload, try to find the source reg
7259 from an input reload. */
7262 rtx set
= single_set (insn
);
7263 if (set
&& SET_DEST (set
) == rld
[r
].out
)
7267 src_reg
= SET_SRC (set
);
7269 for (k
= 0; k
< n_reloads
; k
++)
7271 if (rld
[k
].in
== src_reg
)
7273 src_reg
= rld
[k
].reg_rtx
;
7280 store_insn
= new_spill_reg_store
[REGNO (src_reg
)];
7281 if (src_reg
&& GET_CODE (src_reg
) == REG
7282 && REGNO (src_reg
) < FIRST_PSEUDO_REGISTER
)
7284 int src_regno
= REGNO (src_reg
);
7285 int nr
= HARD_REGNO_NREGS (src_regno
, rld
[r
].mode
);
7286 /* The place where to find a death note varies with
7287 PRESERVE_DEATH_INFO_REGNO_P . The condition is not
7288 necessarily checked exactly in the code that moves
7289 notes, so just check both locations. */
7290 rtx note
= find_regno_note (insn
, REG_DEAD
, src_regno
);
7292 note
= find_regno_note (store_insn
, REG_DEAD
, src_regno
);
7295 spill_reg_store
[src_regno
+ nr
] = store_insn
;
7296 spill_reg_stored_to
[src_regno
+ nr
] = out
;
7297 reg_reloaded_contents
[src_regno
+ nr
] = nregno
;
7298 reg_reloaded_insn
[src_regno
+ nr
] = store_insn
;
7299 CLEAR_HARD_REG_BIT (reg_reloaded_dead
, src_regno
+ nr
);
7300 SET_HARD_REG_BIT (reg_reloaded_valid
, src_regno
+ nr
);
7301 SET_HARD_REG_BIT (reg_is_output_reload
, src_regno
+ nr
);
7303 SET_HARD_REG_BIT (reg_reloaded_died
, src_regno
);
7305 CLEAR_HARD_REG_BIT (reg_reloaded_died
, src_regno
);
7307 reg_last_reload_reg
[nregno
] = src_reg
;
7312 int num_regs
= HARD_REGNO_NREGS (nregno
, GET_MODE (rld
[r
].out
));
7314 while (num_regs
-- > 0)
7315 reg_last_reload_reg
[nregno
+ num_regs
] = 0;
7319 IOR_HARD_REG_SET (reg_reloaded_dead
, reg_reloaded_died
);
7322 /* Emit code to perform a reload from IN (which may be a reload register) to
7323 OUT (which may also be a reload register). IN or OUT is from operand
7324 OPNUM with reload type TYPE.
7326 Returns first insn emitted. */
7329 gen_reload (out
, in
, opnum
, type
)
7333 enum reload_type type
;
7335 rtx last
= get_last_insn ();
7338 /* If IN is a paradoxical SUBREG, remove it and try to put the
7339 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
7340 if (GET_CODE (in
) == SUBREG
7341 && (GET_MODE_SIZE (GET_MODE (in
))
7342 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in
))))
7343 && (tem
= gen_lowpart_common (GET_MODE (SUBREG_REG (in
)), out
)) != 0)
7344 in
= SUBREG_REG (in
), out
= tem
;
7345 else if (GET_CODE (out
) == SUBREG
7346 && (GET_MODE_SIZE (GET_MODE (out
))
7347 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out
))))
7348 && (tem
= gen_lowpart_common (GET_MODE (SUBREG_REG (out
)), in
)) != 0)
7349 out
= SUBREG_REG (out
), in
= tem
;
7351 /* How to do this reload can get quite tricky. Normally, we are being
7352 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
7353 register that didn't get a hard register. In that case we can just
7354 call emit_move_insn.
7356 We can also be asked to reload a PLUS that adds a register or a MEM to
7357 another register, constant or MEM. This can occur during frame pointer
7358 elimination and while reloading addresses. This case is handled by
7359 trying to emit a single insn to perform the add. If it is not valid,
7360 we use a two insn sequence.
7362 Finally, we could be called to handle an 'o' constraint by putting
7363 an address into a register. In that case, we first try to do this
7364 with a named pattern of "reload_load_address". If no such pattern
7365 exists, we just emit a SET insn and hope for the best (it will normally
7366 be valid on machines that use 'o').
7368 This entire process is made complex because reload will never
7369 process the insns we generate here and so we must ensure that
7370 they will fit their constraints and also by the fact that parts of
7371 IN might be being reloaded separately and replaced with spill registers.
7372 Because of this, we are, in some sense, just guessing the right approach
7373 here. The one listed above seems to work.
7375 ??? At some point, this whole thing needs to be rethought. */
7377 if (GET_CODE (in
) == PLUS
7378 && (GET_CODE (XEXP (in
, 0)) == REG
7379 || GET_CODE (XEXP (in
, 0)) == SUBREG
7380 || GET_CODE (XEXP (in
, 0)) == MEM
)
7381 && (GET_CODE (XEXP (in
, 1)) == REG
7382 || GET_CODE (XEXP (in
, 1)) == SUBREG
7383 || CONSTANT_P (XEXP (in
, 1))
7384 || GET_CODE (XEXP (in
, 1)) == MEM
))
7386 /* We need to compute the sum of a register or a MEM and another
7387 register, constant, or MEM, and put it into the reload
7388 register. The best possible way of doing this is if the machine
7389 has a three-operand ADD insn that accepts the required operands.
7391 The simplest approach is to try to generate such an insn and see if it
7392 is recognized and matches its constraints. If so, it can be used.
7394 It might be better not to actually emit the insn unless it is valid,
7395 but we need to pass the insn as an operand to `recog' and
7396 `extract_insn' and it is simpler to emit and then delete the insn if
7397 not valid than to dummy things up. */
7399 rtx op0
, op1
, tem
, insn
;
7402 op0
= find_replacement (&XEXP (in
, 0));
7403 op1
= find_replacement (&XEXP (in
, 1));
7405 /* Since constraint checking is strict, commutativity won't be
7406 checked, so we need to do that here to avoid spurious failure
7407 if the add instruction is two-address and the second operand
7408 of the add is the same as the reload reg, which is frequently
7409 the case. If the insn would be A = B + A, rearrange it so
7410 it will be A = A + B as constrain_operands expects. */
7412 if (GET_CODE (XEXP (in
, 1)) == REG
7413 && REGNO (out
) == REGNO (XEXP (in
, 1)))
7414 tem
= op0
, op0
= op1
, op1
= tem
;
7416 if (op0
!= XEXP (in
, 0) || op1
!= XEXP (in
, 1))
7417 in
= gen_rtx_PLUS (GET_MODE (in
), op0
, op1
);
7419 insn
= emit_insn (gen_rtx_SET (VOIDmode
, out
, in
));
7420 code
= recog_memoized (insn
);
7424 extract_insn (insn
);
7425 /* We want constrain operands to treat this insn strictly in
7426 its validity determination, i.e., the way it would after reload
7428 if (constrain_operands (1))
7432 delete_insns_since (last
);
7434 /* If that failed, we must use a conservative two-insn sequence.
7436 Use a move to copy one operand into the reload register. Prefer
7437 to reload a constant, MEM or pseudo since the move patterns can
7438 handle an arbitrary operand. If OP1 is not a constant, MEM or
7439 pseudo and OP1 is not a valid operand for an add instruction, then
7442 After reloading one of the operands into the reload register, add
7443 the reload register to the output register.
7445 If there is another way to do this for a specific machine, a
7446 DEFINE_PEEPHOLE should be specified that recognizes the sequence
7449 code
= (int) add_optab
->handlers
[(int) GET_MODE (out
)].insn_code
;
7451 if (CONSTANT_P (op1
) || GET_CODE (op1
) == MEM
|| GET_CODE (op1
) == SUBREG
7452 || (GET_CODE (op1
) == REG
7453 && REGNO (op1
) >= FIRST_PSEUDO_REGISTER
)
7454 || (code
!= CODE_FOR_nothing
7455 && ! ((*insn_data
[code
].operand
[2].predicate
)
7456 (op1
, insn_data
[code
].operand
[2].mode
))))
7457 tem
= op0
, op0
= op1
, op1
= tem
;
7459 gen_reload (out
, op0
, opnum
, type
);
7461 /* If OP0 and OP1 are the same, we can use OUT for OP1.
7462 This fixes a problem on the 32K where the stack pointer cannot
7463 be used as an operand of an add insn. */
7465 if (rtx_equal_p (op0
, op1
))
7468 insn
= emit_insn (gen_add2_insn (out
, op1
));
7470 /* If that failed, copy the address register to the reload register.
7471 Then add the constant to the reload register. */
7473 code
= recog_memoized (insn
);
7477 extract_insn (insn
);
7478 /* We want constrain operands to treat this insn strictly in
7479 its validity determination, i.e., the way it would after reload
7481 if (constrain_operands (1))
7483 /* Add a REG_EQUIV note so that find_equiv_reg can find it. */
7485 = gen_rtx_EXPR_LIST (REG_EQUIV
, in
, REG_NOTES (insn
));
7490 delete_insns_since (last
);
7492 gen_reload (out
, op1
, opnum
, type
);
7493 insn
= emit_insn (gen_add2_insn (out
, op0
));
7494 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_EQUIV
, in
, REG_NOTES (insn
));
7497 #ifdef SECONDARY_MEMORY_NEEDED
7498 /* If we need a memory location to do the move, do it that way. */
7499 else if (GET_CODE (in
) == REG
&& REGNO (in
) < FIRST_PSEUDO_REGISTER
7500 && GET_CODE (out
) == REG
&& REGNO (out
) < FIRST_PSEUDO_REGISTER
7501 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (REGNO (in
)),
7502 REGNO_REG_CLASS (REGNO (out
)),
7505 /* Get the memory to use and rewrite both registers to its mode. */
7506 rtx loc
= get_secondary_mem (in
, GET_MODE (out
), opnum
, type
);
7508 if (GET_MODE (loc
) != GET_MODE (out
))
7509 out
= gen_rtx_REG (GET_MODE (loc
), REGNO (out
));
7511 if (GET_MODE (loc
) != GET_MODE (in
))
7512 in
= gen_rtx_REG (GET_MODE (loc
), REGNO (in
));
7514 gen_reload (loc
, in
, opnum
, type
);
7515 gen_reload (out
, loc
, opnum
, type
);
7519 /* If IN is a simple operand, use gen_move_insn. */
7520 else if (GET_RTX_CLASS (GET_CODE (in
)) == 'o' || GET_CODE (in
) == SUBREG
)
7521 emit_insn (gen_move_insn (out
, in
));
7523 #ifdef HAVE_reload_load_address
7524 else if (HAVE_reload_load_address
)
7525 emit_insn (gen_reload_load_address (out
, in
));
7528 /* Otherwise, just write (set OUT IN) and hope for the best. */
7530 emit_insn (gen_rtx_SET (VOIDmode
, out
, in
));
7532 /* Return the first insn emitted.
7533 We can not just return get_last_insn, because there may have
7534 been multiple instructions emitted. Also note that gen_move_insn may
7535 emit more than one insn itself, so we can not assume that there is one
7536 insn emitted per emit_insn_before call. */
7538 return last
? NEXT_INSN (last
) : get_insns ();
7541 /* Delete a previously made output-reload
7542 whose result we now believe is not needed.
7543 First we double-check.
7545 INSN is the insn now being processed.
7546 LAST_RELOAD_REG is the hard register number for which we want to delete
7547 the last output reload.
7548 J is the reload-number that originally used REG. The caller has made
7549 certain that reload J doesn't use REG any longer for input. */
7552 delete_output_reload (insn
, j
, last_reload_reg
)
7555 int last_reload_reg
;
7557 rtx output_reload_insn
= spill_reg_store
[last_reload_reg
];
7558 rtx reg
= spill_reg_stored_to
[last_reload_reg
];
7561 int n_inherited
= 0;
7565 /* Get the raw pseudo-register referred to. */
7567 while (GET_CODE (reg
) == SUBREG
)
7568 reg
= SUBREG_REG (reg
);
7569 substed
= reg_equiv_memory_loc
[REGNO (reg
)];
7571 /* This is unsafe if the operand occurs more often in the current
7572 insn than it is inherited. */
7573 for (k
= n_reloads
- 1; k
>= 0; k
--)
7575 rtx reg2
= rld
[k
].in
;
7578 if (GET_CODE (reg2
) == MEM
|| reload_override_in
[k
])
7579 reg2
= rld
[k
].in_reg
;
7581 if (rld
[k
].out
&& ! rld
[k
].out_reg
)
7582 reg2
= XEXP (rld
[k
].in_reg
, 0);
7584 while (GET_CODE (reg2
) == SUBREG
)
7585 reg2
= SUBREG_REG (reg2
);
7586 if (rtx_equal_p (reg2
, reg
))
7588 if (reload_inherited
[k
] || reload_override_in
[k
] || k
== j
)
7591 reg2
= rld
[k
].out_reg
;
7594 while (GET_CODE (reg2
) == SUBREG
)
7595 reg2
= XEXP (reg2
, 0);
7596 if (rtx_equal_p (reg2
, reg
))
7603 n_occurrences
= count_occurrences (PATTERN (insn
), reg
, 0);
7605 n_occurrences
+= count_occurrences (PATTERN (insn
),
7606 eliminate_regs (substed
, 0,
7608 if (n_occurrences
> n_inherited
)
7611 /* If the pseudo-reg we are reloading is no longer referenced
7612 anywhere between the store into it and here,
7613 and no jumps or labels intervene, then the value can get
7614 here through the reload reg alone.
7615 Otherwise, give up--return. */
7616 for (i1
= NEXT_INSN (output_reload_insn
);
7617 i1
!= insn
; i1
= NEXT_INSN (i1
))
7619 if (GET_CODE (i1
) == CODE_LABEL
|| GET_CODE (i1
) == JUMP_INSN
)
7621 if ((GET_CODE (i1
) == INSN
|| GET_CODE (i1
) == CALL_INSN
)
7622 && reg_mentioned_p (reg
, PATTERN (i1
)))
7624 /* If this is USE in front of INSN, we only have to check that
7625 there are no more references than accounted for by inheritance. */
7626 while (GET_CODE (i1
) == INSN
&& GET_CODE (PATTERN (i1
)) == USE
)
7628 n_occurrences
+= rtx_equal_p (reg
, XEXP (PATTERN (i1
), 0)) != 0;
7629 i1
= NEXT_INSN (i1
);
7631 if (n_occurrences
<= n_inherited
&& i1
== insn
)
7637 /* The caller has already checked that REG dies or is set in INSN.
7638 It has also checked that we are optimizing, and thus some inaccurancies
7639 in the debugging information are acceptable.
7640 So we could just delete output_reload_insn.
7641 But in some cases we can improve the debugging information without
7642 sacrificing optimization - maybe even improving the code:
7643 See if the pseudo reg has been completely replaced
7644 with reload regs. If so, delete the store insn
7645 and forget we had a stack slot for the pseudo. */
7646 if (rld
[j
].out
!= rld
[j
].in
7647 && REG_N_DEATHS (REGNO (reg
)) == 1
7648 && REG_N_SETS (REGNO (reg
)) == 1
7649 && REG_BASIC_BLOCK (REGNO (reg
)) >= 0
7650 && find_regno_note (insn
, REG_DEAD
, REGNO (reg
)))
7654 /* We know that it was used only between here
7655 and the beginning of the current basic block.
7656 (We also know that the last use before INSN was
7657 the output reload we are thinking of deleting, but never mind that.)
7658 Search that range; see if any ref remains. */
7659 for (i2
= PREV_INSN (insn
); i2
; i2
= PREV_INSN (i2
))
7661 rtx set
= single_set (i2
);
7663 /* Uses which just store in the pseudo don't count,
7664 since if they are the only uses, they are dead. */
7665 if (set
!= 0 && SET_DEST (set
) == reg
)
7667 if (GET_CODE (i2
) == CODE_LABEL
7668 || GET_CODE (i2
) == JUMP_INSN
)
7670 if ((GET_CODE (i2
) == INSN
|| GET_CODE (i2
) == CALL_INSN
)
7671 && reg_mentioned_p (reg
, PATTERN (i2
)))
7673 /* Some other ref remains; just delete the output reload we
7675 delete_address_reloads (output_reload_insn
, insn
);
7676 PUT_CODE (output_reload_insn
, NOTE
);
7677 NOTE_SOURCE_FILE (output_reload_insn
) = 0;
7678 NOTE_LINE_NUMBER (output_reload_insn
) = NOTE_INSN_DELETED
;
7683 /* Delete the now-dead stores into this pseudo. */
7684 for (i2
= PREV_INSN (insn
); i2
; i2
= PREV_INSN (i2
))
7686 rtx set
= single_set (i2
);
7688 if (set
!= 0 && SET_DEST (set
) == reg
)
7690 delete_address_reloads (i2
, insn
);
7691 /* This might be a basic block head,
7692 thus don't use delete_insn. */
7693 PUT_CODE (i2
, NOTE
);
7694 NOTE_SOURCE_FILE (i2
) = 0;
7695 NOTE_LINE_NUMBER (i2
) = NOTE_INSN_DELETED
;
7697 if (GET_CODE (i2
) == CODE_LABEL
7698 || GET_CODE (i2
) == JUMP_INSN
)
7702 /* For the debugging info,
7703 say the pseudo lives in this reload reg. */
7704 reg_renumber
[REGNO (reg
)] = REGNO (rld
[j
].reg_rtx
);
7705 alter_reg (REGNO (reg
), -1);
7707 delete_address_reloads (output_reload_insn
, insn
);
7708 PUT_CODE (output_reload_insn
, NOTE
);
7709 NOTE_SOURCE_FILE (output_reload_insn
) = 0;
7710 NOTE_LINE_NUMBER (output_reload_insn
) = NOTE_INSN_DELETED
;
7714 /* We are going to delete DEAD_INSN. Recursively delete loads of
7715 reload registers used in DEAD_INSN that are not used till CURRENT_INSN.
7716 CURRENT_INSN is being reloaded, so we have to check its reloads too. */
7718 delete_address_reloads (dead_insn
, current_insn
)
7719 rtx dead_insn
, current_insn
;
7721 rtx set
= single_set (dead_insn
);
7722 rtx set2
, dst
, prev
, next
;
7725 rtx dst
= SET_DEST (set
);
7726 if (GET_CODE (dst
) == MEM
)
7727 delete_address_reloads_1 (dead_insn
, XEXP (dst
, 0), current_insn
);
7729 /* If we deleted the store from a reloaded post_{in,de}c expression,
7730 we can delete the matching adds. */
7731 prev
= PREV_INSN (dead_insn
);
7732 next
= NEXT_INSN (dead_insn
);
7733 if (! prev
|| ! next
)
7735 set
= single_set (next
);
7736 set2
= single_set (prev
);
7738 || GET_CODE (SET_SRC (set
)) != PLUS
|| GET_CODE (SET_SRC (set2
)) != PLUS
7739 || GET_CODE (XEXP (SET_SRC (set
), 1)) != CONST_INT
7740 || GET_CODE (XEXP (SET_SRC (set2
), 1)) != CONST_INT
)
7742 dst
= SET_DEST (set
);
7743 if (! rtx_equal_p (dst
, SET_DEST (set2
))
7744 || ! rtx_equal_p (dst
, XEXP (SET_SRC (set
), 0))
7745 || ! rtx_equal_p (dst
, XEXP (SET_SRC (set2
), 0))
7746 || (INTVAL (XEXP (SET_SRC (set
), 1))
7747 != -INTVAL (XEXP (SET_SRC (set2
), 1))))
7753 /* Subfunction of delete_address_reloads: process registers found in X. */
7755 delete_address_reloads_1 (dead_insn
, x
, current_insn
)
7756 rtx dead_insn
, x
, current_insn
;
7758 rtx prev
, set
, dst
, i2
;
7760 enum rtx_code code
= GET_CODE (x
);
7764 const char *fmt
= GET_RTX_FORMAT (code
);
7765 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
7768 delete_address_reloads_1 (dead_insn
, XEXP (x
, i
), current_insn
);
7769 else if (fmt
[i
] == 'E')
7771 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
7772 delete_address_reloads_1 (dead_insn
, XVECEXP (x
, i
, j
),
7779 if (spill_reg_order
[REGNO (x
)] < 0)
7782 /* Scan backwards for the insn that sets x. This might be a way back due
7784 for (prev
= PREV_INSN (dead_insn
); prev
; prev
= PREV_INSN (prev
))
7786 code
= GET_CODE (prev
);
7787 if (code
== CODE_LABEL
|| code
== JUMP_INSN
)
7789 if (GET_RTX_CLASS (code
) != 'i')
7791 if (reg_set_p (x
, PATTERN (prev
)))
7793 if (reg_referenced_p (x
, PATTERN (prev
)))
7796 if (! prev
|| INSN_UID (prev
) < reload_first_uid
)
7798 /* Check that PREV only sets the reload register. */
7799 set
= single_set (prev
);
7802 dst
= SET_DEST (set
);
7803 if (GET_CODE (dst
) != REG
7804 || ! rtx_equal_p (dst
, x
))
7806 if (! reg_set_p (dst
, PATTERN (dead_insn
)))
7808 /* Check if DST was used in a later insn -
7809 it might have been inherited. */
7810 for (i2
= NEXT_INSN (dead_insn
); i2
; i2
= NEXT_INSN (i2
))
7812 if (GET_CODE (i2
) == CODE_LABEL
)
7816 if (reg_referenced_p (dst
, PATTERN (i2
)))
7818 /* If there is a reference to the register in the current insn,
7819 it might be loaded in a non-inherited reload. If no other
7820 reload uses it, that means the register is set before
7822 if (i2
== current_insn
)
7824 for (j
= n_reloads
- 1; j
>= 0; j
--)
7825 if ((rld
[j
].reg_rtx
== dst
&& reload_inherited
[j
])
7826 || reload_override_in
[j
] == dst
)
7828 for (j
= n_reloads
- 1; j
>= 0; j
--)
7829 if (rld
[j
].in
&& rld
[j
].reg_rtx
== dst
)
7836 if (GET_CODE (i2
) == JUMP_INSN
)
7838 /* If DST is still live at CURRENT_INSN, check if it is used for
7839 any reload. Note that even if CURRENT_INSN sets DST, we still
7840 have to check the reloads. */
7841 if (i2
== current_insn
)
7843 for (j
= n_reloads
- 1; j
>= 0; j
--)
7844 if ((rld
[j
].reg_rtx
== dst
&& reload_inherited
[j
])
7845 || reload_override_in
[j
] == dst
)
7847 /* ??? We can't finish the loop here, because dst might be
7848 allocated to a pseudo in this block if no reload in this
7849 block needs any of the clsses containing DST - see
7850 spill_hard_reg. There is no easy way to tell this, so we
7851 have to scan till the end of the basic block. */
7853 if (reg_set_p (dst
, PATTERN (i2
)))
7857 delete_address_reloads_1 (prev
, SET_SRC (set
), current_insn
);
7858 reg_reloaded_contents
[REGNO (dst
)] = -1;
7859 /* Can't use delete_insn here because PREV might be a basic block head. */
7860 PUT_CODE (prev
, NOTE
);
7861 NOTE_LINE_NUMBER (prev
) = NOTE_INSN_DELETED
;
7862 NOTE_SOURCE_FILE (prev
) = 0;
7865 /* Output reload-insns to reload VALUE into RELOADREG.
7866 VALUE is an autoincrement or autodecrement RTX whose operand
7867 is a register or memory location;
7868 so reloading involves incrementing that location.
7869 IN is either identical to VALUE, or some cheaper place to reload from.
7871 INC_AMOUNT is the number to increment or decrement by (always positive).
7872 This cannot be deduced from VALUE.
7874 Return the instruction that stores into RELOADREG. */
7877 inc_for_reload (reloadreg
, in
, value
, inc_amount
)
7882 /* REG or MEM to be copied and incremented. */
7883 rtx incloc
= XEXP (value
, 0);
7884 /* Nonzero if increment after copying. */
7885 int post
= (GET_CODE (value
) == POST_DEC
|| GET_CODE (value
) == POST_INC
);
7891 rtx real_in
= in
== value
? XEXP (in
, 0) : in
;
7893 /* No hard register is equivalent to this register after
7894 inc/dec operation. If REG_LAST_RELOAD_REG were non-zero,
7895 we could inc/dec that register as well (maybe even using it for
7896 the source), but I'm not sure it's worth worrying about. */
7897 if (GET_CODE (incloc
) == REG
)
7898 reg_last_reload_reg
[REGNO (incloc
)] = 0;
7900 if (GET_CODE (value
) == PRE_DEC
|| GET_CODE (value
) == POST_DEC
)
7901 inc_amount
= -inc_amount
;
7903 inc
= GEN_INT (inc_amount
);
7905 /* If this is post-increment, first copy the location to the reload reg. */
7906 if (post
&& real_in
!= reloadreg
)
7907 emit_insn (gen_move_insn (reloadreg
, real_in
));
7911 /* See if we can directly increment INCLOC. Use a method similar to
7912 that in gen_reload. */
7914 last
= get_last_insn ();
7915 add_insn
= emit_insn (gen_rtx_SET (VOIDmode
, incloc
,
7916 gen_rtx_PLUS (GET_MODE (incloc
),
7919 code
= recog_memoized (add_insn
);
7922 extract_insn (add_insn
);
7923 if (constrain_operands (1))
7925 /* If this is a pre-increment and we have incremented the value
7926 where it lives, copy the incremented value to RELOADREG to
7927 be used as an address. */
7930 emit_insn (gen_move_insn (reloadreg
, incloc
));
7935 delete_insns_since (last
);
7938 /* If couldn't do the increment directly, must increment in RELOADREG.
7939 The way we do this depends on whether this is pre- or post-increment.
7940 For pre-increment, copy INCLOC to the reload register, increment it
7941 there, then save back. */
7945 if (in
!= reloadreg
)
7946 emit_insn (gen_move_insn (reloadreg
, real_in
));
7947 emit_insn (gen_add2_insn (reloadreg
, inc
));
7948 store
= emit_insn (gen_move_insn (incloc
, reloadreg
));
7953 Because this might be a jump insn or a compare, and because RELOADREG
7954 may not be available after the insn in an input reload, we must do
7955 the incrementation before the insn being reloaded for.
7957 We have already copied IN to RELOADREG. Increment the copy in
7958 RELOADREG, save that back, then decrement RELOADREG so it has
7959 the original value. */
7961 emit_insn (gen_add2_insn (reloadreg
, inc
));
7962 store
= emit_insn (gen_move_insn (incloc
, reloadreg
));
7963 emit_insn (gen_add2_insn (reloadreg
, GEN_INT (-inc_amount
)));
7969 /* Return 1 if we are certain that the constraint-string STRING allows
7970 the hard register REG. Return 0 if we can't be sure of this. */
7973 constraint_accepts_reg_p (string
, reg
)
7978 int regno
= true_regnum (reg
);
7981 /* Initialize for first alternative. */
7983 /* Check that each alternative contains `g' or `r'. */
7985 switch (c
= *string
++)
7988 /* If an alternative lacks `g' or `r', we lose. */
7991 /* If an alternative lacks `g' or `r', we lose. */
7994 /* Initialize for next alternative. */
7999 /* Any general reg wins for this alternative. */
8000 if (TEST_HARD_REG_BIT (reg_class_contents
[(int) GENERAL_REGS
], regno
))
8004 /* Any reg in specified class wins for this alternative. */
8006 enum reg_class
class = REG_CLASS_FROM_LETTER (c
);
8008 if (TEST_HARD_REG_BIT (reg_class_contents
[(int) class], regno
))
8014 /* INSN is a no-op; delete it.
8015 If this sets the return value of the function, we must keep a USE around,
8016 in case this is in a different basic block than the final USE. Otherwise,
8017 we could loose important register lifeness information on
8018 SMALL_REGISTER_CLASSES machines, where return registers might be used as
8019 spills: subsequent passes assume that spill registers are dead at the end
8021 VALUE must be the return value in such a case, NULL otherwise. */
8023 reload_cse_delete_noop_set (insn
, value
)
8028 PATTERN (insn
) = gen_rtx_USE (VOIDmode
, value
);
8029 INSN_CODE (insn
) = -1;
8030 REG_NOTES (insn
) = NULL_RTX
;
8034 PUT_CODE (insn
, NOTE
);
8035 NOTE_LINE_NUMBER (insn
) = NOTE_INSN_DELETED
;
8036 NOTE_SOURCE_FILE (insn
) = 0;
8040 /* See whether a single set SET is a noop. */
8042 reload_cse_noop_set_p (set
)
8045 return rtx_equal_for_cselib_p (SET_DEST (set
), SET_SRC (set
));
8048 /* Try to simplify INSN. */
8050 reload_cse_simplify (insn
)
8053 rtx body
= PATTERN (insn
);
8055 if (GET_CODE (body
) == SET
)
8059 /* Simplify even if we may think it is a no-op.
8060 We may think a memory load of a value smaller than WORD_SIZE
8061 is redundant because we haven't taken into account possible
8062 implicit extension. reload_cse_simplify_set() will bring
8063 this out, so it's safer to simplify before we delete. */
8064 count
+= reload_cse_simplify_set (body
, insn
);
8066 if (!count
&& reload_cse_noop_set_p (body
))
8068 rtx value
= SET_DEST (body
);
8069 if (! REG_FUNCTION_VALUE_P (SET_DEST (body
)))
8071 reload_cse_delete_noop_set (insn
, value
);
8076 apply_change_group ();
8078 reload_cse_simplify_operands (insn
);
8080 else if (GET_CODE (body
) == PARALLEL
)
8084 rtx value
= NULL_RTX
;
8086 /* If every action in a PARALLEL is a noop, we can delete
8087 the entire PARALLEL. */
8088 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; --i
)
8090 rtx part
= XVECEXP (body
, 0, i
);
8091 if (GET_CODE (part
) == SET
)
8093 if (! reload_cse_noop_set_p (part
))
8095 if (REG_FUNCTION_VALUE_P (SET_DEST (part
)))
8099 value
= SET_DEST (part
);
8102 else if (GET_CODE (part
) != CLOBBER
)
8108 reload_cse_delete_noop_set (insn
, value
);
8109 /* We're done with this insn. */
8113 /* It's not a no-op, but we can try to simplify it. */
8114 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; --i
)
8115 if (GET_CODE (XVECEXP (body
, 0, i
)) == SET
)
8116 count
+= reload_cse_simplify_set (XVECEXP (body
, 0, i
), insn
);
8119 apply_change_group ();
8121 reload_cse_simplify_operands (insn
);
8125 /* Do a very simple CSE pass over the hard registers.
8127 This function detects no-op moves where we happened to assign two
8128 different pseudo-registers to the same hard register, and then
8129 copied one to the other. Reload will generate a useless
8130 instruction copying a register to itself.
8132 This function also detects cases where we load a value from memory
8133 into two different registers, and (if memory is more expensive than
8134 registers) changes it to simply copy the first register into the
8137 Another optimization is performed that scans the operands of each
8138 instruction to see whether the value is already available in a
8139 hard register. It then replaces the operand with the hard register
8140 if possible, much like an optional reload would. */
8143 reload_cse_regs_1 (first
)
8149 init_alias_analysis ();
8151 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
8154 reload_cse_simplify (insn
);
8156 cselib_process_insn (insn
);
8160 end_alias_analysis ();
8164 /* Call cse / combine like post-reload optimization phases.
8165 FIRST is the first instruction. */
8167 reload_cse_regs (first
)
8170 reload_cse_regs_1 (first
);
8172 reload_cse_move2add (first
);
8173 if (flag_expensive_optimizations
)
8174 reload_cse_regs_1 (first
);
8177 /* Try to simplify a single SET instruction. SET is the set pattern.
8178 INSN is the instruction it came from.
8179 This function only handles one case: if we set a register to a value
8180 which is not a register, we try to find that value in some other register
8181 and change the set into a register copy. */
8184 reload_cse_simplify_set (set
, insn
)
8191 enum reg_class dclass
;
8194 struct elt_loc_list
*l
;
8195 #ifdef LOAD_EXTEND_OP
8196 enum rtx_code extend_op
= NIL
;
8199 dreg
= true_regnum (SET_DEST (set
));
8203 src
= SET_SRC (set
);
8204 if (side_effects_p (src
) || true_regnum (src
) >= 0)
8207 dclass
= REGNO_REG_CLASS (dreg
);
8209 #ifdef LOAD_EXTEND_OP
8210 /* When replacing a memory with a register, we need to honor assumptions
8211 that combine made wrt the contents of sign bits. We'll do this by
8212 generating an extend instruction instead of a reg->reg copy. Thus
8213 the destination must be a register that we can widen. */
8214 if (GET_CODE (src
) == MEM
8215 && GET_MODE_BITSIZE (GET_MODE (src
)) < BITS_PER_WORD
8216 && (extend_op
= LOAD_EXTEND_OP (GET_MODE (src
))) != NIL
8217 && GET_CODE (SET_DEST (set
)) != REG
)
8221 /* If memory loads are cheaper than register copies, don't change them. */
8222 if (GET_CODE (src
) == MEM
)
8223 old_cost
= MEMORY_MOVE_COST (GET_MODE (src
), dclass
, 1);
8224 else if (CONSTANT_P (src
))
8225 old_cost
= rtx_cost (src
, SET
);
8226 else if (GET_CODE (src
) == REG
)
8227 old_cost
= REGISTER_MOVE_COST (GET_MODE (src
),
8228 REGNO_REG_CLASS (REGNO (src
)), dclass
);
8231 old_cost
= rtx_cost (src
, SET
);
8233 val
= cselib_lookup (src
, GET_MODE (SET_DEST (set
)), 0);
8236 for (l
= val
->locs
; l
; l
= l
->next
)
8238 rtx this_rtx
= l
->loc
;
8241 if (CONSTANT_P (this_rtx
) && ! references_value_p (this_rtx
, 0))
8243 #ifdef LOAD_EXTEND_OP
8244 if (extend_op
!= NIL
)
8246 HOST_WIDE_INT this_val
;
8248 /* ??? I'm lazy and don't wish to handle CONST_DOUBLE. Other
8249 constants, such as SYMBOL_REF, cannot be extended. */
8250 if (GET_CODE (this_rtx
) != CONST_INT
)
8253 this_val
= INTVAL (this_rtx
);
8257 this_val
&= GET_MODE_MASK (GET_MODE (src
));
8260 /* ??? In theory we're already extended. */
8261 if (this_val
== trunc_int_for_mode (this_val
, GET_MODE (src
)))
8266 this_rtx
= GEN_INT (this_val
);
8269 this_cost
= rtx_cost (this_rtx
, SET
);
8271 else if (GET_CODE (this_rtx
) == REG
)
8273 #ifdef LOAD_EXTEND_OP
8274 if (extend_op
!= NIL
)
8276 this_rtx
= gen_rtx_fmt_e (extend_op
, word_mode
, this_rtx
);
8277 this_cost
= rtx_cost (this_rtx
, SET
);
8281 this_cost
= REGISTER_MOVE_COST (GET_MODE (this_rtx
),
8282 REGNO_REG_CLASS (REGNO (this_rtx
)),
8288 /* If equal costs, prefer registers over anything else. That
8289 tends to lead to smaller instructions on some machines. */
8290 if (this_cost
< old_cost
8291 || (this_cost
== old_cost
8292 && GET_CODE (this_rtx
) == REG
8293 && GET_CODE (SET_SRC (set
)) != REG
))
8295 #ifdef LOAD_EXTEND_OP
8296 if (GET_MODE_BITSIZE (GET_MODE (SET_DEST (set
))) < BITS_PER_WORD
8297 && extend_op
!= NIL
)
8299 rtx wide_dest
= gen_rtx_REG (word_mode
, REGNO (SET_DEST (set
)));
8300 ORIGINAL_REGNO (wide_dest
) = ORIGINAL_REGNO (SET_DEST (set
));
8301 validate_change (insn
, &SET_DEST (set
), wide_dest
, 1);
8305 validate_change (insn
, &SET_SRC (set
), copy_rtx (this_rtx
), 1);
8306 old_cost
= this_cost
, did_change
= 1;
8313 /* Try to replace operands in INSN with equivalent values that are already
8314 in registers. This can be viewed as optional reloading.
8316 For each non-register operand in the insn, see if any hard regs are
8317 known to be equivalent to that operand. Record the alternatives which
8318 can accept these hard registers. Among all alternatives, select the
8319 ones which are better or equal to the one currently matching, where
8320 "better" is in terms of '?' and '!' constraints. Among the remaining
8321 alternatives, select the one which replaces most operands with
8325 reload_cse_simplify_operands (insn
)
8330 /* For each operand, all registers that are equivalent to it. */
8331 HARD_REG_SET equiv_regs
[MAX_RECOG_OPERANDS
];
8333 const char *constraints
[MAX_RECOG_OPERANDS
];
8335 /* Vector recording how bad an alternative is. */
8336 int *alternative_reject
;
8337 /* Vector recording how many registers can be introduced by choosing
8338 this alternative. */
8339 int *alternative_nregs
;
8340 /* Array of vectors recording, for each operand and each alternative,
8341 which hard register to substitute, or -1 if the operand should be
8343 int *op_alt_regno
[MAX_RECOG_OPERANDS
];
8344 /* Array of alternatives, sorted in order of decreasing desirability. */
8345 int *alternative_order
;
8346 rtx reg
= gen_rtx_REG (VOIDmode
, -1);
8348 extract_insn (insn
);
8350 if (recog_data
.n_alternatives
== 0 || recog_data
.n_operands
== 0)
8353 /* Figure out which alternative currently matches. */
8354 if (! constrain_operands (1))
8355 fatal_insn_not_found (insn
);
8357 alternative_reject
= (int *) alloca (recog_data
.n_alternatives
* sizeof (int));
8358 alternative_nregs
= (int *) alloca (recog_data
.n_alternatives
* sizeof (int));
8359 alternative_order
= (int *) alloca (recog_data
.n_alternatives
* sizeof (int));
8360 memset ((char *)alternative_reject
, 0, recog_data
.n_alternatives
* sizeof (int));
8361 memset ((char *)alternative_nregs
, 0, recog_data
.n_alternatives
* sizeof (int));
8363 /* For each operand, find out which regs are equivalent. */
8364 for (i
= 0; i
< recog_data
.n_operands
; i
++)
8367 struct elt_loc_list
*l
;
8369 CLEAR_HARD_REG_SET (equiv_regs
[i
]);
8371 /* cselib blows up on CODE_LABELs. Trying to fix that doesn't seem
8372 right, so avoid the problem here. Likewise if we have a constant
8373 and the insn pattern doesn't tell us the mode we need. */
8374 if (GET_CODE (recog_data
.operand
[i
]) == CODE_LABEL
8375 || (CONSTANT_P (recog_data
.operand
[i
])
8376 && recog_data
.operand_mode
[i
] == VOIDmode
))
8379 v
= cselib_lookup (recog_data
.operand
[i
], recog_data
.operand_mode
[i
], 0);
8383 for (l
= v
->locs
; l
; l
= l
->next
)
8384 if (GET_CODE (l
->loc
) == REG
)
8385 SET_HARD_REG_BIT (equiv_regs
[i
], REGNO (l
->loc
));
8388 for (i
= 0; i
< recog_data
.n_operands
; i
++)
8390 enum machine_mode mode
;
8394 op_alt_regno
[i
] = (int *) alloca (recog_data
.n_alternatives
* sizeof (int));
8395 for (j
= 0; j
< recog_data
.n_alternatives
; j
++)
8396 op_alt_regno
[i
][j
] = -1;
8398 p
= constraints
[i
] = recog_data
.constraints
[i
];
8399 mode
= recog_data
.operand_mode
[i
];
8401 /* Add the reject values for each alternative given by the constraints
8402 for this operand. */
8410 alternative_reject
[j
] += 3;
8412 alternative_reject
[j
] += 300;
8415 /* We won't change operands which are already registers. We
8416 also don't want to modify output operands. */
8417 regno
= true_regnum (recog_data
.operand
[i
]);
8419 || constraints
[i
][0] == '='
8420 || constraints
[i
][0] == '+')
8423 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
8425 int class = (int) NO_REGS
;
8427 if (! TEST_HARD_REG_BIT (equiv_regs
[i
], regno
))
8430 REGNO (reg
) = regno
;
8431 PUT_MODE (reg
, mode
);
8433 /* We found a register equal to this operand. Now look for all
8434 alternatives that can accept this register and have not been
8435 assigned a register they can use yet. */
8444 case '=': case '+': case '?':
8445 case '#': case '&': case '!':
8447 case '0': case '1': case '2': case '3': case '4':
8448 case '5': case '6': case '7': case '8': case '9':
8449 case 'm': case '<': case '>': case 'V': case 'o':
8450 case 'E': case 'F': case 'G': case 'H':
8451 case 's': case 'i': case 'n':
8452 case 'I': case 'J': case 'K': case 'L':
8453 case 'M': case 'N': case 'O': case 'P':
8455 /* These don't say anything we care about. */
8459 class = reg_class_subunion
[(int) class][(int) GENERAL_REGS
];
8464 = reg_class_subunion
[(int) class][(int) REG_CLASS_FROM_LETTER ((unsigned char)c
)];
8467 case ',': case '\0':
8468 /* See if REGNO fits this alternative, and set it up as the
8469 replacement register if we don't have one for this
8470 alternative yet and the operand being replaced is not
8471 a cheap CONST_INT. */
8472 if (op_alt_regno
[i
][j
] == -1
8473 && reg_fits_class_p (reg
, class, 0, mode
)
8474 && (GET_CODE (recog_data
.operand
[i
]) != CONST_INT
8475 || (rtx_cost (recog_data
.operand
[i
], SET
)
8476 > rtx_cost (reg
, SET
))))
8478 alternative_nregs
[j
]++;
8479 op_alt_regno
[i
][j
] = regno
;
8491 /* Record all alternatives which are better or equal to the currently
8492 matching one in the alternative_order array. */
8493 for (i
= j
= 0; i
< recog_data
.n_alternatives
; i
++)
8494 if (alternative_reject
[i
] <= alternative_reject
[which_alternative
])
8495 alternative_order
[j
++] = i
;
8496 recog_data
.n_alternatives
= j
;
8498 /* Sort it. Given a small number of alternatives, a dumb algorithm
8499 won't hurt too much. */
8500 for (i
= 0; i
< recog_data
.n_alternatives
- 1; i
++)
8503 int best_reject
= alternative_reject
[alternative_order
[i
]];
8504 int best_nregs
= alternative_nregs
[alternative_order
[i
]];
8507 for (j
= i
+ 1; j
< recog_data
.n_alternatives
; j
++)
8509 int this_reject
= alternative_reject
[alternative_order
[j
]];
8510 int this_nregs
= alternative_nregs
[alternative_order
[j
]];
8512 if (this_reject
< best_reject
8513 || (this_reject
== best_reject
&& this_nregs
< best_nregs
))
8516 best_reject
= this_reject
;
8517 best_nregs
= this_nregs
;
8521 tmp
= alternative_order
[best
];
8522 alternative_order
[best
] = alternative_order
[i
];
8523 alternative_order
[i
] = tmp
;
8526 /* Substitute the operands as determined by op_alt_regno for the best
8528 j
= alternative_order
[0];
8530 for (i
= 0; i
< recog_data
.n_operands
; i
++)
8532 enum machine_mode mode
= recog_data
.operand_mode
[i
];
8533 if (op_alt_regno
[i
][j
] == -1)
8536 validate_change (insn
, recog_data
.operand_loc
[i
],
8537 gen_rtx_REG (mode
, op_alt_regno
[i
][j
]), 1);
8540 for (i
= recog_data
.n_dups
- 1; i
>= 0; i
--)
8542 int op
= recog_data
.dup_num
[i
];
8543 enum machine_mode mode
= recog_data
.operand_mode
[op
];
8545 if (op_alt_regno
[op
][j
] == -1)
8548 validate_change (insn
, recog_data
.dup_loc
[i
],
8549 gen_rtx_REG (mode
, op_alt_regno
[op
][j
]), 1);
8552 return apply_change_group ();
8555 /* If reload couldn't use reg+reg+offset addressing, try to use reg+reg
8557 This code might also be useful when reload gave up on reg+reg addresssing
8558 because of clashes between the return register and INDEX_REG_CLASS. */
8560 /* The maximum number of uses of a register we can keep track of to
8561 replace them with reg+reg addressing. */
8562 #define RELOAD_COMBINE_MAX_USES 6
8564 /* INSN is the insn where a register has ben used, and USEP points to the
8565 location of the register within the rtl. */
8566 struct reg_use
{ rtx insn
, *usep
; };
8568 /* If the register is used in some unknown fashion, USE_INDEX is negative.
8569 If it is dead, USE_INDEX is RELOAD_COMBINE_MAX_USES, and STORE_RUID
8570 indicates where it becomes live again.
8571 Otherwise, USE_INDEX is the index of the last encountered use of the
8572 register (which is first among these we have seen since we scan backwards),
8573 OFFSET contains the constant offset that is added to the register in
8574 all encountered uses, and USE_RUID indicates the first encountered, i.e.
8575 last, of these uses.
8576 STORE_RUID is always meaningful if we only want to use a value in a
8577 register in a different place: it denotes the next insn in the insn
8578 stream (i.e. the last ecountered) that sets or clobbers the register. */
8581 struct reg_use reg_use
[RELOAD_COMBINE_MAX_USES
];
8586 } reg_state
[FIRST_PSEUDO_REGISTER
];
8588 /* Reverse linear uid. This is increased in reload_combine while scanning
8589 the instructions from last to first. It is used to set last_label_ruid
8590 and the store_ruid / use_ruid fields in reg_state. */
8591 static int reload_combine_ruid
;
8593 #define LABEL_LIVE(LABEL) \
8594 (label_live[CODE_LABEL_NUMBER (LABEL) - min_labelno])
8600 int first_index_reg
= -1;
8601 int last_index_reg
= 0;
8604 int last_label_ruid
;
8605 int min_labelno
, n_labels
;
8606 HARD_REG_SET ever_live_at_start
, *label_live
;
8608 /* If reg+reg can be used in offsetable memory adresses, the main chunk of
8609 reload has already used it where appropriate, so there is no use in
8610 trying to generate it now. */
8611 if (double_reg_address_ok
&& INDEX_REG_CLASS
!= NO_REGS
)
8614 /* To avoid wasting too much time later searching for an index register,
8615 determine the minimum and maximum index register numbers. */
8616 for (r
= 0; r
< FIRST_PSEUDO_REGISTER
; r
++)
8617 if (TEST_HARD_REG_BIT (reg_class_contents
[INDEX_REG_CLASS
], r
))
8619 if (first_index_reg
== -1)
8620 first_index_reg
= r
;
8625 /* If no index register is available, we can quit now. */
8626 if (first_index_reg
== -1)
8629 /* Set up LABEL_LIVE and EVER_LIVE_AT_START. The register lifetime
8630 information is a bit fuzzy immediately after reload, but it's
8631 still good enough to determine which registers are live at a jump
8633 min_labelno
= get_first_label_num ();
8634 n_labels
= max_label_num () - min_labelno
;
8635 label_live
= (HARD_REG_SET
*) xmalloc (n_labels
* sizeof (HARD_REG_SET
));
8636 CLEAR_HARD_REG_SET (ever_live_at_start
);
8638 for (i
= n_basic_blocks
- 1; i
>= 0; i
--)
8640 insn
= BLOCK_HEAD (i
);
8641 if (GET_CODE (insn
) == CODE_LABEL
)
8645 REG_SET_TO_HARD_REG_SET (live
,
8646 BASIC_BLOCK (i
)->global_live_at_start
);
8647 compute_use_by_pseudos (&live
,
8648 BASIC_BLOCK (i
)->global_live_at_start
);
8649 COPY_HARD_REG_SET (LABEL_LIVE (insn
), live
);
8650 IOR_HARD_REG_SET (ever_live_at_start
, live
);
8654 /* Initialize last_label_ruid, reload_combine_ruid and reg_state. */
8655 last_label_ruid
= reload_combine_ruid
= 0;
8656 for (r
= 0; r
< FIRST_PSEUDO_REGISTER
; r
++)
8658 reg_state
[r
].store_ruid
= reload_combine_ruid
;
8660 reg_state
[r
].use_index
= -1;
8662 reg_state
[r
].use_index
= RELOAD_COMBINE_MAX_USES
;
8665 for (insn
= get_last_insn (); insn
; insn
= PREV_INSN (insn
))
8669 /* We cannot do our optimization across labels. Invalidating all the use
8670 information we have would be costly, so we just note where the label
8671 is and then later disable any optimization that would cross it. */
8672 if (GET_CODE (insn
) == CODE_LABEL
)
8673 last_label_ruid
= reload_combine_ruid
;
8674 else if (GET_CODE (insn
) == BARRIER
)
8675 for (r
= 0; r
< FIRST_PSEUDO_REGISTER
; r
++)
8676 if (! fixed_regs
[r
])
8677 reg_state
[r
].use_index
= RELOAD_COMBINE_MAX_USES
;
8679 if (! INSN_P (insn
))
8682 reload_combine_ruid
++;
8684 /* Look for (set (REGX) (CONST_INT))
8685 (set (REGX) (PLUS (REGX) (REGY)))
8687 ... (MEM (REGX)) ...
8689 (set (REGZ) (CONST_INT))
8691 ... (MEM (PLUS (REGZ) (REGY)))... .
8693 First, check that we have (set (REGX) (PLUS (REGX) (REGY)))
8694 and that we know all uses of REGX before it dies. */
8695 set
= single_set (insn
);
8697 && GET_CODE (SET_DEST (set
)) == REG
8698 && (HARD_REGNO_NREGS (REGNO (SET_DEST (set
)),
8699 GET_MODE (SET_DEST (set
)))
8701 && GET_CODE (SET_SRC (set
)) == PLUS
8702 && GET_CODE (XEXP (SET_SRC (set
), 1)) == REG
8703 && rtx_equal_p (XEXP (SET_SRC (set
), 0), SET_DEST (set
))
8704 && last_label_ruid
< reg_state
[REGNO (SET_DEST (set
))].use_ruid
)
8706 rtx reg
= SET_DEST (set
);
8707 rtx plus
= SET_SRC (set
);
8708 rtx base
= XEXP (plus
, 1);
8709 rtx prev
= prev_nonnote_insn (insn
);
8710 rtx prev_set
= prev
? single_set (prev
) : NULL_RTX
;
8711 unsigned int regno
= REGNO (reg
);
8712 rtx const_reg
= NULL_RTX
;
8713 rtx reg_sum
= NULL_RTX
;
8715 /* Now, we need an index register.
8716 We'll set index_reg to this index register, const_reg to the
8717 register that is to be loaded with the constant
8718 (denoted as REGZ in the substitution illustration above),
8719 and reg_sum to the register-register that we want to use to
8720 substitute uses of REG (typically in MEMs) with.
8721 First check REG and BASE for being index registers;
8722 we can use them even if they are not dead. */
8723 if (TEST_HARD_REG_BIT (reg_class_contents
[INDEX_REG_CLASS
], regno
)
8724 || TEST_HARD_REG_BIT (reg_class_contents
[INDEX_REG_CLASS
],
8732 /* Otherwise, look for a free index register. Since we have
8733 checked above that neiter REG nor BASE are index registers,
8734 if we find anything at all, it will be different from these
8736 for (i
= first_index_reg
; i
<= last_index_reg
; i
++)
8738 if (TEST_HARD_REG_BIT (reg_class_contents
[INDEX_REG_CLASS
],
8740 && reg_state
[i
].use_index
== RELOAD_COMBINE_MAX_USES
8741 && reg_state
[i
].store_ruid
<= reg_state
[regno
].use_ruid
8742 && HARD_REGNO_NREGS (i
, GET_MODE (reg
)) == 1)
8744 rtx index_reg
= gen_rtx_REG (GET_MODE (reg
), i
);
8746 const_reg
= index_reg
;
8747 reg_sum
= gen_rtx_PLUS (GET_MODE (reg
), index_reg
, base
);
8753 /* Check that PREV_SET is indeed (set (REGX) (CONST_INT)) and that
8754 (REGY), i.e. BASE, is not clobbered before the last use we'll
8757 && GET_CODE (SET_SRC (prev_set
)) == CONST_INT
8758 && rtx_equal_p (SET_DEST (prev_set
), reg
)
8759 && reg_state
[regno
].use_index
>= 0
8760 && (reg_state
[REGNO (base
)].store_ruid
8761 <= reg_state
[regno
].use_ruid
)
8766 /* Change destination register and, if necessary, the
8767 constant value in PREV, the constant loading instruction. */
8768 validate_change (prev
, &SET_DEST (prev_set
), const_reg
, 1);
8769 if (reg_state
[regno
].offset
!= const0_rtx
)
8770 validate_change (prev
,
8771 &SET_SRC (prev_set
),
8772 GEN_INT (INTVAL (SET_SRC (prev_set
))
8773 + INTVAL (reg_state
[regno
].offset
)),
8776 /* Now for every use of REG that we have recorded, replace REG
8778 for (i
= reg_state
[regno
].use_index
;
8779 i
< RELOAD_COMBINE_MAX_USES
; i
++)
8780 validate_change (reg_state
[regno
].reg_use
[i
].insn
,
8781 reg_state
[regno
].reg_use
[i
].usep
,
8784 if (apply_change_group ())
8788 /* Delete the reg-reg addition. */
8789 PUT_CODE (insn
, NOTE
);
8790 NOTE_LINE_NUMBER (insn
) = NOTE_INSN_DELETED
;
8791 NOTE_SOURCE_FILE (insn
) = 0;
8793 if (reg_state
[regno
].offset
!= const0_rtx
)
8794 /* Previous REG_EQUIV / REG_EQUAL notes for PREV
8796 for (np
= ®_NOTES (prev
); *np
;)
8798 if (REG_NOTE_KIND (*np
) == REG_EQUAL
8799 || REG_NOTE_KIND (*np
) == REG_EQUIV
)
8800 *np
= XEXP (*np
, 1);
8802 np
= &XEXP (*np
, 1);
8805 reg_state
[regno
].use_index
= RELOAD_COMBINE_MAX_USES
;
8806 reg_state
[REGNO (const_reg
)].store_ruid
8807 = reload_combine_ruid
;
8813 note_stores (PATTERN (insn
), reload_combine_note_store
, NULL
);
8815 if (GET_CODE (insn
) == CALL_INSN
)
8819 for (r
= 0; r
< FIRST_PSEUDO_REGISTER
; r
++)
8820 if (call_used_regs
[r
])
8822 reg_state
[r
].use_index
= RELOAD_COMBINE_MAX_USES
;
8823 reg_state
[r
].store_ruid
= reload_combine_ruid
;
8826 for (link
= CALL_INSN_FUNCTION_USAGE (insn
); link
;
8827 link
= XEXP (link
, 1))
8829 rtx usage_rtx
= XEXP (XEXP (link
, 0), 0);
8830 if (GET_CODE (usage_rtx
) == REG
)
8833 unsigned int start_reg
= REGNO (usage_rtx
);
8834 unsigned int num_regs
=
8835 HARD_REGNO_NREGS (start_reg
, GET_MODE (usage_rtx
));
8836 unsigned int end_reg
= start_reg
+ num_regs
- 1;
8837 for (i
= start_reg
; i
<= end_reg
; i
++)
8838 if (GET_CODE (XEXP (link
, 0)) == CLOBBER
)
8840 reg_state
[i
].use_index
= RELOAD_COMBINE_MAX_USES
;
8841 reg_state
[i
].store_ruid
= reload_combine_ruid
;
8844 reg_state
[i
].use_index
= -1;
8849 else if (GET_CODE (insn
) == JUMP_INSN
8850 && GET_CODE (PATTERN (insn
)) != RETURN
)
8852 /* Non-spill registers might be used at the call destination in
8853 some unknown fashion, so we have to mark the unknown use. */
8856 if ((condjump_p (insn
) || condjump_in_parallel_p (insn
))
8857 && JUMP_LABEL (insn
))
8858 live
= &LABEL_LIVE (JUMP_LABEL (insn
));
8860 live
= &ever_live_at_start
;
8862 for (i
= FIRST_PSEUDO_REGISTER
- 1; i
>= 0; --i
)
8863 if (TEST_HARD_REG_BIT (*live
, i
))
8864 reg_state
[i
].use_index
= -1;
8867 reload_combine_note_use (&PATTERN (insn
), insn
);
8868 for (note
= REG_NOTES (insn
); note
; note
= XEXP (note
, 1))
8870 if (REG_NOTE_KIND (note
) == REG_INC
8871 && GET_CODE (XEXP (note
, 0)) == REG
)
8873 int regno
= REGNO (XEXP (note
, 0));
8875 reg_state
[regno
].store_ruid
= reload_combine_ruid
;
8876 reg_state
[regno
].use_index
= -1;
8884 /* Check if DST is a register or a subreg of a register; if it is,
8885 update reg_state[regno].store_ruid and reg_state[regno].use_index
8886 accordingly. Called via note_stores from reload_combine. */
8889 reload_combine_note_store (dst
, set
, data
)
8891 void *data ATTRIBUTE_UNUSED
;
8895 enum machine_mode mode
= GET_MODE (dst
);
8897 if (GET_CODE (dst
) == SUBREG
)
8899 regno
= subreg_regno_offset (REGNO (SUBREG_REG (dst
)),
8900 GET_MODE (SUBREG_REG (dst
)),
8903 dst
= SUBREG_REG (dst
);
8905 if (GET_CODE (dst
) != REG
)
8907 regno
+= REGNO (dst
);
8909 /* note_stores might have stripped a STRICT_LOW_PART, so we have to be
8910 careful with registers / register parts that are not full words.
8912 Similarly for ZERO_EXTRACT and SIGN_EXTRACT. */
8913 if (GET_CODE (set
) != SET
8914 || GET_CODE (SET_DEST (set
)) == ZERO_EXTRACT
8915 || GET_CODE (SET_DEST (set
)) == SIGN_EXTRACT
8916 || GET_CODE (SET_DEST (set
)) == STRICT_LOW_PART
)
8918 for (i
= HARD_REGNO_NREGS (regno
, mode
) - 1 + regno
; i
>= regno
; i
--)
8920 reg_state
[i
].use_index
= -1;
8921 reg_state
[i
].store_ruid
= reload_combine_ruid
;
8926 for (i
= HARD_REGNO_NREGS (regno
, mode
) - 1 + regno
; i
>= regno
; i
--)
8928 reg_state
[i
].store_ruid
= reload_combine_ruid
;
8929 reg_state
[i
].use_index
= RELOAD_COMBINE_MAX_USES
;
8934 /* XP points to a piece of rtl that has to be checked for any uses of
8936 *XP is the pattern of INSN, or a part of it.
8937 Called from reload_combine, and recursively by itself. */
8939 reload_combine_note_use (xp
, insn
)
8943 enum rtx_code code
= x
->code
;
8946 rtx offset
= const0_rtx
; /* For the REG case below. */
8951 if (GET_CODE (SET_DEST (x
)) == REG
)
8953 reload_combine_note_use (&SET_SRC (x
), insn
);
8959 /* If this is the USE of a return value, we can't change it. */
8960 if (GET_CODE (XEXP (x
, 0)) == REG
&& REG_FUNCTION_VALUE_P (XEXP (x
, 0)))
8962 /* Mark the return register as used in an unknown fashion. */
8963 rtx reg
= XEXP (x
, 0);
8964 int regno
= REGNO (reg
);
8965 int nregs
= HARD_REGNO_NREGS (regno
, GET_MODE (reg
));
8967 while (--nregs
>= 0)
8968 reg_state
[regno
+ nregs
].use_index
= -1;
8974 if (GET_CODE (SET_DEST (x
)) == REG
)
8979 /* We are interested in (plus (reg) (const_int)) . */
8980 if (GET_CODE (XEXP (x
, 0)) != REG
8981 || GET_CODE (XEXP (x
, 1)) != CONST_INT
)
8983 offset
= XEXP (x
, 1);
8988 int regno
= REGNO (x
);
8992 /* Some spurious USEs of pseudo registers might remain.
8993 Just ignore them. */
8994 if (regno
>= FIRST_PSEUDO_REGISTER
)
8997 nregs
= HARD_REGNO_NREGS (regno
, GET_MODE (x
));
8999 /* We can't substitute into multi-hard-reg uses. */
9002 while (--nregs
>= 0)
9003 reg_state
[regno
+ nregs
].use_index
= -1;
9007 /* If this register is already used in some unknown fashion, we
9009 If we decrement the index from zero to -1, we can't store more
9010 uses, so this register becomes used in an unknown fashion. */
9011 use_index
= --reg_state
[regno
].use_index
;
9015 if (use_index
!= RELOAD_COMBINE_MAX_USES
- 1)
9017 /* We have found another use for a register that is already
9018 used later. Check if the offsets match; if not, mark the
9019 register as used in an unknown fashion. */
9020 if (! rtx_equal_p (offset
, reg_state
[regno
].offset
))
9022 reg_state
[regno
].use_index
= -1;
9028 /* This is the first use of this register we have seen since we
9029 marked it as dead. */
9030 reg_state
[regno
].offset
= offset
;
9031 reg_state
[regno
].use_ruid
= reload_combine_ruid
;
9033 reg_state
[regno
].reg_use
[use_index
].insn
= insn
;
9034 reg_state
[regno
].reg_use
[use_index
].usep
= xp
;
9042 /* Recursively process the components of X. */
9043 fmt
= GET_RTX_FORMAT (code
);
9044 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
9047 reload_combine_note_use (&XEXP (x
, i
), insn
);
9048 else if (fmt
[i
] == 'E')
9050 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
9051 reload_combine_note_use (&XVECEXP (x
, i
, j
), insn
);
9056 /* See if we can reduce the cost of a constant by replacing a move
9057 with an add. We track situations in which a register is set to a
9058 constant or to a register plus a constant. */
9059 /* We cannot do our optimization across labels. Invalidating all the
9060 information about register contents we have would be costly, so we
9061 use move2add_last_label_luid to note where the label is and then
9062 later disable any optimization that would cross it.
9063 reg_offset[n] / reg_base_reg[n] / reg_mode[n] are only valid if
9064 reg_set_luid[n] is greater than last_label_luid[n] . */
9065 static int reg_set_luid
[FIRST_PSEUDO_REGISTER
];
9067 /* If reg_base_reg[n] is negative, register n has been set to
9068 reg_offset[n] in mode reg_mode[n] .
9069 If reg_base_reg[n] is non-negative, register n has been set to the
9070 sum of reg_offset[n] and the value of register reg_base_reg[n]
9071 before reg_set_luid[n], calculated in mode reg_mode[n] . */
9072 static HOST_WIDE_INT reg_offset
[FIRST_PSEUDO_REGISTER
];
9073 static int reg_base_reg
[FIRST_PSEUDO_REGISTER
];
9074 static enum machine_mode reg_mode
[FIRST_PSEUDO_REGISTER
];
9076 /* move2add_luid is linearily increased while scanning the instructions
9077 from first to last. It is used to set reg_set_luid in
9078 reload_cse_move2add and move2add_note_store. */
9079 static int move2add_luid
;
9081 /* move2add_last_label_luid is set whenever a label is found. Labels
9082 invalidate all previously collected reg_offset data. */
9083 static int move2add_last_label_luid
;
9085 /* Generate a CONST_INT and force it in the range of MODE. */
9087 static HOST_WIDE_INT
9088 sext_for_mode (mode
, value
)
9089 enum machine_mode mode
;
9090 HOST_WIDE_INT value
;
9092 HOST_WIDE_INT cval
= value
& GET_MODE_MASK (mode
);
9093 int width
= GET_MODE_BITSIZE (mode
);
9095 /* If MODE is narrower than HOST_WIDE_INT and CVAL is a negative number,
9097 if (width
> 0 && width
< HOST_BITS_PER_WIDE_INT
9098 && (cval
& ((HOST_WIDE_INT
) 1 << (width
- 1))) != 0)
9099 cval
|= (HOST_WIDE_INT
) -1 << width
;
9104 /* ??? We don't know how zero / sign extension is handled, hence we
9105 can't go from a narrower to a wider mode. */
9106 #define MODES_OK_FOR_MOVE2ADD(OUTMODE, INMODE) \
9107 (GET_MODE_SIZE (OUTMODE) == GET_MODE_SIZE (INMODE) \
9108 || (GET_MODE_SIZE (OUTMODE) <= GET_MODE_SIZE (INMODE) \
9109 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (OUTMODE), \
9110 GET_MODE_BITSIZE (INMODE))))
9113 reload_cse_move2add (first
)
9119 for (i
= FIRST_PSEUDO_REGISTER
- 1; i
>= 0; i
--)
9120 reg_set_luid
[i
] = 0;
9122 move2add_last_label_luid
= 0;
9124 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
), move2add_luid
++)
9128 if (GET_CODE (insn
) == CODE_LABEL
)
9130 move2add_last_label_luid
= move2add_luid
;
9131 /* We're going to increment move2add_luid twice after a
9132 label, so that we can use move2add_last_label_luid + 1 as
9133 the luid for constants. */
9137 if (! INSN_P (insn
))
9139 pat
= PATTERN (insn
);
9140 /* For simplicity, we only perform this optimization on
9141 straightforward SETs. */
9142 if (GET_CODE (pat
) == SET
9143 && GET_CODE (SET_DEST (pat
)) == REG
)
9145 rtx reg
= SET_DEST (pat
);
9146 int regno
= REGNO (reg
);
9147 rtx src
= SET_SRC (pat
);
9149 /* Check if we have valid information on the contents of this
9150 register in the mode of REG. */
9151 if (reg_set_luid
[regno
] > move2add_last_label_luid
9152 && MODES_OK_FOR_MOVE2ADD (GET_MODE (reg
), reg_mode
[regno
]))
9154 /* Try to transform (set (REGX) (CONST_INT A))
9156 (set (REGX) (CONST_INT B))
9158 (set (REGX) (CONST_INT A))
9160 (set (REGX) (plus (REGX) (CONST_INT B-A))) */
9162 if (GET_CODE (src
) == CONST_INT
&& reg_base_reg
[regno
] < 0)
9165 rtx new_src
= GEN_INT (sext_for_mode (GET_MODE (reg
),
9167 - reg_offset
[regno
]));
9168 /* (set (reg) (plus (reg) (const_int 0))) is not canonical;
9169 use (set (reg) (reg)) instead.
9170 We don't delete this insn, nor do we convert it into a
9171 note, to avoid losing register notes or the return
9172 value flag. jump2 already knowns how to get rid of
9174 if (new_src
== const0_rtx
)
9175 success
= validate_change (insn
, &SET_SRC (pat
), reg
, 0);
9176 else if (rtx_cost (new_src
, PLUS
) < rtx_cost (src
, SET
)
9177 && have_add2_insn (reg
, new_src
))
9178 success
= validate_change (insn
, &PATTERN (insn
),
9179 gen_add2_insn (reg
, new_src
), 0);
9180 reg_set_luid
[regno
] = move2add_luid
;
9181 reg_mode
[regno
] = GET_MODE (reg
);
9182 reg_offset
[regno
] = INTVAL (src
);
9186 /* Try to transform (set (REGX) (REGY))
9187 (set (REGX) (PLUS (REGX) (CONST_INT A)))
9190 (set (REGX) (PLUS (REGX) (CONST_INT B)))
9193 (set (REGX) (PLUS (REGX) (CONST_INT A)))
9195 (set (REGX) (plus (REGX) (CONST_INT B-A))) */
9196 else if (GET_CODE (src
) == REG
9197 && reg_set_luid
[regno
] == reg_set_luid
[REGNO (src
)]
9198 && reg_base_reg
[regno
] == reg_base_reg
[REGNO (src
)]
9199 && MODES_OK_FOR_MOVE2ADD (GET_MODE (reg
),
9200 reg_mode
[REGNO (src
)]))
9202 rtx next
= next_nonnote_insn (insn
);
9205 set
= single_set (next
);
9207 && SET_DEST (set
) == reg
9208 && GET_CODE (SET_SRC (set
)) == PLUS
9209 && XEXP (SET_SRC (set
), 0) == reg
9210 && GET_CODE (XEXP (SET_SRC (set
), 1)) == CONST_INT
)
9212 rtx src3
= XEXP (SET_SRC (set
), 1);
9213 HOST_WIDE_INT added_offset
= INTVAL (src3
);
9214 HOST_WIDE_INT base_offset
= reg_offset
[REGNO (src
)];
9215 HOST_WIDE_INT regno_offset
= reg_offset
[regno
];
9216 rtx new_src
= GEN_INT (sext_for_mode (GET_MODE (reg
),
9222 if (new_src
== const0_rtx
)
9223 /* See above why we create (set (reg) (reg)) here. */
9225 = validate_change (next
, &SET_SRC (set
), reg
, 0);
9226 else if ((rtx_cost (new_src
, PLUS
)
9227 < COSTS_N_INSNS (1) + rtx_cost (src3
, SET
))
9228 && have_add2_insn (reg
, new_src
))
9230 = validate_change (next
, &PATTERN (next
),
9231 gen_add2_insn (reg
, new_src
), 0);
9234 /* INSN might be the first insn in a basic block
9235 if the preceding insn is a conditional jump
9236 or a possible-throwing call. */
9237 PUT_CODE (insn
, NOTE
);
9238 NOTE_LINE_NUMBER (insn
) = NOTE_INSN_DELETED
;
9239 NOTE_SOURCE_FILE (insn
) = 0;
9242 reg_mode
[regno
] = GET_MODE (reg
);
9243 reg_offset
[regno
] = sext_for_mode (GET_MODE (reg
),
9252 for (note
= REG_NOTES (insn
); note
; note
= XEXP (note
, 1))
9254 if (REG_NOTE_KIND (note
) == REG_INC
9255 && GET_CODE (XEXP (note
, 0)) == REG
)
9257 /* Reset the information about this register. */
9258 int regno
= REGNO (XEXP (note
, 0));
9259 if (regno
< FIRST_PSEUDO_REGISTER
)
9260 reg_set_luid
[regno
] = 0;
9263 note_stores (PATTERN (insn
), move2add_note_store
, NULL
);
9264 /* If this is a CALL_INSN, all call used registers are stored with
9266 if (GET_CODE (insn
) == CALL_INSN
)
9268 for (i
= FIRST_PSEUDO_REGISTER
- 1; i
>= 0; i
--)
9270 if (call_used_regs
[i
])
9271 /* Reset the information about this register. */
9272 reg_set_luid
[i
] = 0;
9278 /* SET is a SET or CLOBBER that sets DST.
9279 Update reg_set_luid, reg_offset and reg_base_reg accordingly.
9280 Called from reload_cse_move2add via note_stores. */
9283 move2add_note_store (dst
, set
, data
)
9285 void *data ATTRIBUTE_UNUSED
;
9287 unsigned int regno
= 0;
9289 enum machine_mode mode
= GET_MODE (dst
);
9291 if (GET_CODE (dst
) == SUBREG
)
9293 regno
= subreg_regno_offset (REGNO (SUBREG_REG (dst
)),
9294 GET_MODE (SUBREG_REG (dst
)),
9297 dst
= SUBREG_REG (dst
);
9300 /* Some targets do argument pushes without adding REG_INC notes. */
9302 if (GET_CODE (dst
) == MEM
)
9304 dst
= XEXP (dst
, 0);
9305 if (GET_CODE (dst
) == PRE_INC
|| GET_CODE (dst
) == POST_DEC
9306 || GET_CODE (dst
) == PRE_DEC
|| GET_CODE (dst
) == POST_DEC
)
9307 reg_set_luid
[REGNO (XEXP (dst
, 0))] = 0;
9310 if (GET_CODE (dst
) != REG
)
9313 regno
+= REGNO (dst
);
9315 if (HARD_REGNO_NREGS (regno
, mode
) == 1 && GET_CODE (set
) == SET
9316 && GET_CODE (SET_DEST (set
)) != ZERO_EXTRACT
9317 && GET_CODE (SET_DEST (set
)) != SIGN_EXTRACT
9318 && GET_CODE (SET_DEST (set
)) != STRICT_LOW_PART
)
9320 rtx src
= SET_SRC (set
);
9322 HOST_WIDE_INT offset
;
9324 /* This may be different from mode, if SET_DEST (set) is a
9326 enum machine_mode dst_mode
= GET_MODE (dst
);
9328 switch (GET_CODE (src
))
9331 if (GET_CODE (XEXP (src
, 0)) == REG
)
9333 base_reg
= XEXP (src
, 0);
9335 if (GET_CODE (XEXP (src
, 1)) == CONST_INT
)
9336 offset
= INTVAL (XEXP (src
, 1));
9337 else if (GET_CODE (XEXP (src
, 1)) == REG
9338 && (reg_set_luid
[REGNO (XEXP (src
, 1))]
9339 > move2add_last_label_luid
)
9340 && (MODES_OK_FOR_MOVE2ADD
9341 (dst_mode
, reg_mode
[REGNO (XEXP (src
, 1))])))
9343 if (reg_base_reg
[REGNO (XEXP (src
, 1))] < 0)
9344 offset
= reg_offset
[REGNO (XEXP (src
, 1))];
9345 /* Maybe the first register is known to be a
9347 else if (reg_set_luid
[REGNO (base_reg
)]
9348 > move2add_last_label_luid
9349 && (MODES_OK_FOR_MOVE2ADD
9350 (dst_mode
, reg_mode
[REGNO (XEXP (src
, 1))]))
9351 && reg_base_reg
[REGNO (base_reg
)] < 0)
9353 offset
= reg_offset
[REGNO (base_reg
)];
9354 base_reg
= XEXP (src
, 1);
9373 /* Start tracking the register as a constant. */
9374 reg_base_reg
[regno
] = -1;
9375 reg_offset
[regno
] = INTVAL (SET_SRC (set
));
9376 /* We assign the same luid to all registers set to constants. */
9377 reg_set_luid
[regno
] = move2add_last_label_luid
+ 1;
9378 reg_mode
[regno
] = mode
;
9383 /* Invalidate the contents of the register. */
9384 reg_set_luid
[regno
] = 0;
9388 base_regno
= REGNO (base_reg
);
9389 /* If information about the base register is not valid, set it
9390 up as a new base register, pretending its value is known
9391 starting from the current insn. */
9392 if (reg_set_luid
[base_regno
] <= move2add_last_label_luid
)
9394 reg_base_reg
[base_regno
] = base_regno
;
9395 reg_offset
[base_regno
] = 0;
9396 reg_set_luid
[base_regno
] = move2add_luid
;
9397 reg_mode
[base_regno
] = mode
;
9399 else if (! MODES_OK_FOR_MOVE2ADD (dst_mode
,
9400 reg_mode
[base_regno
]))
9403 reg_mode
[regno
] = mode
;
9405 /* Copy base information from our base register. */
9406 reg_set_luid
[regno
] = reg_set_luid
[base_regno
];
9407 reg_base_reg
[regno
] = reg_base_reg
[base_regno
];
9409 /* Compute the sum of the offsets or constants. */
9410 reg_offset
[regno
] = sext_for_mode (dst_mode
,
9412 + reg_offset
[base_regno
]);
9416 unsigned int endregno
= regno
+ HARD_REGNO_NREGS (regno
, mode
);
9418 for (i
= regno
; i
< endregno
; i
++)
9419 /* Reset the information about this register. */
9420 reg_set_luid
[i
] = 0;
9426 add_auto_inc_notes (insn
, x
)
9430 enum rtx_code code
= GET_CODE (x
);
9434 if (code
== MEM
&& auto_inc_p (XEXP (x
, 0)))
9437 = gen_rtx_EXPR_LIST (REG_INC
, XEXP (XEXP (x
, 0), 0), REG_NOTES (insn
));
9441 /* Scan all the operand sub-expressions. */
9442 fmt
= GET_RTX_FORMAT (code
);
9443 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
9446 add_auto_inc_notes (insn
, XEXP (x
, i
));
9447 else if (fmt
[i
] == 'E')
9448 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
9449 add_auto_inc_notes (insn
, XVECEXP (x
, i
, j
));
9454 /* Copy EH notes from an insn to its reloads. */
9456 copy_eh_notes (insn
, x
)
9460 rtx eh_note
= find_reg_note (insn
, REG_EH_REGION
, NULL_RTX
);
9463 for (; x
!= 0; x
= NEXT_INSN (x
))
9465 if (may_trap_p (PATTERN (x
)))
9467 = gen_rtx_EXPR_LIST (REG_EH_REGION
, XEXP (eh_note
, 0),
9473 /* This is used by reload pass, that does emit some instructions after
9474 abnormal calls moving basic block end, but in fact it wants to emit
9475 them on the edge. Looks for abnormal call edges, find backward the
9476 proper call and fix the damage.
9478 Similar handle instructions throwing exceptions internally. */
9480 fixup_abnormal_edges ()
9483 bool inserted
= false;
9485 for (i
= 0; i
< n_basic_blocks
; i
++)
9487 basic_block bb
= BASIC_BLOCK (i
);
9490 /* Look for cases we are interested in - an calls or instructions causing
9492 for (e
= bb
->succ
; e
; e
= e
->succ_next
)
9494 if (e
->flags
& EDGE_ABNORMAL_CALL
)
9496 if ((e
->flags
& (EDGE_ABNORMAL
| EDGE_EH
))
9497 == (EDGE_ABNORMAL
| EDGE_EH
))
9500 if (e
&& GET_CODE (bb
->end
) != CALL_INSN
&& !can_throw_internal (bb
->end
))
9504 for (e
= bb
->succ
; e
; e
= e
->succ_next
)
9505 if (e
->flags
& EDGE_FALLTHRU
)
9507 /* Get past the new insns generated. Allow notes, as the insns may
9508 be already deleted. */
9509 while ((GET_CODE (insn
) == INSN
|| GET_CODE (insn
) == NOTE
)
9510 && !can_throw_internal (insn
)
9511 && insn
!= bb
->head
)
9512 insn
= PREV_INSN (insn
);
9513 if (GET_CODE (insn
) != CALL_INSN
&& !can_throw_internal (insn
))
9517 insn
= NEXT_INSN (insn
);
9518 while (insn
&& GET_CODE (insn
) == INSN
)
9520 next
= NEXT_INSN (insn
);
9521 insert_insn_on_edge (PATTERN (insn
), e
);
9522 flow_delete_insn (insn
);
9528 commit_edge_insertions ();