1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987, 88, 89, 92-98, 1999 Free Software Foundation, Inc.
4 This file is part of GNU CC.
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
26 #include "hard-reg-set.h"
29 #include "insn-config.h"
30 #include "insn-flags.h"
31 #include "insn-codes.h"
35 #include "basic-block.h"
42 /* This file contains the reload pass of the compiler, which is
43 run after register allocation has been done. It checks that
44 each insn is valid (operands required to be in registers really
45 are in registers of the proper class) and fixes up invalid ones
46 by copying values temporarily into registers for the insns
49 The results of register allocation are described by the vector
50 reg_renumber; the insns still contain pseudo regs, but reg_renumber
51 can be used to find which hard reg, if any, a pseudo reg is in.
53 The technique we always use is to free up a few hard regs that are
54 called ``reload regs'', and for each place where a pseudo reg
55 must be in a hard reg, copy it temporarily into one of the reload regs.
57 Reload regs are allocated locally for every instruction that needs
58 reloads. When there are pseudos which are allocated to a register that
59 has been chosen as a reload reg, such pseudos must be ``spilled''.
60 This means that they go to other hard regs, or to stack slots if no other
61 available hard regs can be found. Spilling can invalidate more
62 insns, requiring additional need for reloads, so we must keep checking
63 until the process stabilizes.
65 For machines with different classes of registers, we must keep track
66 of the register class needed for each reload, and make sure that
67 we allocate enough reload registers of each class.
69 The file reload.c contains the code that checks one insn for
70 validity and reports the reloads that it needs. This file
71 is in charge of scanning the entire rtl code, accumulating the
72 reload needs, spilling, assigning reload registers to use for
73 fixing up each insn, and generating the new insns to copy values
74 into the reload registers. */
77 #ifndef REGISTER_MOVE_COST
78 #define REGISTER_MOVE_COST(x, y) 2
81 /* During reload_as_needed, element N contains a REG rtx for the hard reg
82 into which reg N has been reloaded (perhaps for a previous insn). */
83 static rtx
*reg_last_reload_reg
;
85 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
86 for an output reload that stores into reg N. */
87 static char *reg_has_output_reload
;
89 /* Indicates which hard regs are reload-registers for an output reload
90 in the current insn. */
91 static HARD_REG_SET reg_is_output_reload
;
93 /* Element N is the constant value to which pseudo reg N is equivalent,
94 or zero if pseudo reg N is not equivalent to a constant.
95 find_reloads looks at this in order to replace pseudo reg N
96 with the constant it stands for. */
97 rtx
*reg_equiv_constant
;
99 /* Element N is a memory location to which pseudo reg N is equivalent,
100 prior to any register elimination (such as frame pointer to stack
101 pointer). Depending on whether or not it is a valid address, this value
102 is transferred to either reg_equiv_address or reg_equiv_mem. */
103 rtx
*reg_equiv_memory_loc
;
105 /* Element N is the address of stack slot to which pseudo reg N is equivalent.
106 This is used when the address is not valid as a memory address
107 (because its displacement is too big for the machine.) */
108 rtx
*reg_equiv_address
;
110 /* Element N is the memory slot to which pseudo reg N is equivalent,
111 or zero if pseudo reg N is not equivalent to a memory slot. */
114 /* Widest width in which each pseudo reg is referred to (via subreg). */
115 static int *reg_max_ref_width
;
117 /* Element N is the list of insns that initialized reg N from its equivalent
118 constant or memory slot. */
119 static rtx
*reg_equiv_init
;
121 /* Vector to remember old contents of reg_renumber before spilling. */
122 static short *reg_old_renumber
;
124 /* During reload_as_needed, element N contains the last pseudo regno reloaded
125 into hard register N. If that pseudo reg occupied more than one register,
126 reg_reloaded_contents points to that pseudo for each spill register in
127 use; all of these must remain set for an inheritance to occur. */
128 static int reg_reloaded_contents
[FIRST_PSEUDO_REGISTER
];
130 /* During reload_as_needed, element N contains the insn for which
131 hard register N was last used. Its contents are significant only
132 when reg_reloaded_valid is set for this register. */
133 static rtx reg_reloaded_insn
[FIRST_PSEUDO_REGISTER
];
135 /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid */
136 static HARD_REG_SET reg_reloaded_valid
;
137 /* Indicate if the register was dead at the end of the reload.
138 This is only valid if reg_reloaded_contents is set and valid. */
139 static HARD_REG_SET reg_reloaded_dead
;
141 /* Number of spill-regs so far; number of valid elements of spill_regs. */
144 /* In parallel with spill_regs, contains REG rtx's for those regs.
145 Holds the last rtx used for any given reg, or 0 if it has never
146 been used for spilling yet. This rtx is reused, provided it has
148 static rtx spill_reg_rtx
[FIRST_PSEUDO_REGISTER
];
150 /* In parallel with spill_regs, contains nonzero for a spill reg
151 that was stored after the last time it was used.
152 The precise value is the insn generated to do the store. */
153 static rtx spill_reg_store
[FIRST_PSEUDO_REGISTER
];
155 /* This is the register that was stored with spill_reg_store. This is a
156 copy of reload_out / reload_out_reg when the value was stored; if
157 reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */
158 static rtx spill_reg_stored_to
[FIRST_PSEUDO_REGISTER
];
160 /* This table is the inverse mapping of spill_regs:
161 indexed by hard reg number,
162 it contains the position of that reg in spill_regs,
163 or -1 for something that is not in spill_regs.
165 ?!? This is no longer accurate. */
166 static short spill_reg_order
[FIRST_PSEUDO_REGISTER
];
168 /* This reg set indicates registers that can't be used as spill registers for
169 the currently processed insn. These are the hard registers which are live
170 during the insn, but not allocated to pseudos, as well as fixed
172 static HARD_REG_SET bad_spill_regs
;
174 /* These are the hard registers that can't be used as spill register for any
175 insn. This includes registers used for user variables and registers that
176 we can't eliminate. A register that appears in this set also can't be used
177 to retry register allocation. */
178 static HARD_REG_SET bad_spill_regs_global
;
180 /* Describes order of use of registers for reloading
181 of spilled pseudo-registers. `n_spills' is the number of
182 elements that are actually valid; new ones are added at the end.
184 Both spill_regs and spill_reg_order are used on two occasions:
185 once during find_reload_regs, where they keep track of the spill registers
186 for a single insn, but also during reload_as_needed where they show all
187 the registers ever used by reload. For the latter case, the information
188 is calculated during finish_spills. */
189 static short spill_regs
[FIRST_PSEUDO_REGISTER
];
191 /* This vector of reg sets indicates, for each pseudo, which hard registers
192 may not be used for retrying global allocation because the register was
193 formerly spilled from one of them. If we allowed reallocating a pseudo to
194 a register that it was already allocated to, reload might not
196 static HARD_REG_SET
*pseudo_previous_regs
;
198 /* This vector of reg sets indicates, for each pseudo, which hard
199 registers may not be used for retrying global allocation because they
200 are used as spill registers during one of the insns in which the
202 static HARD_REG_SET
*pseudo_forbidden_regs
;
204 /* All hard regs that have been used as spill registers for any insn are
205 marked in this set. */
206 static HARD_REG_SET used_spill_regs
;
208 /* Index of last register assigned as a spill register. We allocate in
209 a round-robin fashion. */
210 static int last_spill_reg
;
212 /* Describes order of preference for putting regs into spill_regs.
213 Contains the numbers of all the hard regs, in order most preferred first.
214 This order is different for each function.
215 It is set up by order_regs_for_reload.
216 Empty elements at the end contain -1. */
217 static short potential_reload_regs
[FIRST_PSEUDO_REGISTER
];
219 /* Nonzero if indirect addressing is supported on the machine; this means
220 that spilling (REG n) does not require reloading it into a register in
221 order to do (MEM (REG n)) or (MEM (PLUS (REG n) (CONST_INT c))). The
222 value indicates the level of indirect addressing supported, e.g., two
223 means that (MEM (MEM (REG n))) is also valid if (REG n) does not get
225 static char spill_indirect_levels
;
227 /* Nonzero if indirect addressing is supported when the innermost MEM is
228 of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to
229 which these are valid is the same as spill_indirect_levels, above. */
230 char indirect_symref_ok
;
232 /* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */
233 char double_reg_address_ok
;
235 /* Record the stack slot for each spilled hard register. */
236 static rtx spill_stack_slot
[FIRST_PSEUDO_REGISTER
];
238 /* Width allocated so far for that stack slot. */
239 static int spill_stack_slot_width
[FIRST_PSEUDO_REGISTER
];
241 /* Record which pseudos needed to be spilled. */
242 static regset spilled_pseudos
;
244 /* First uid used by insns created by reload in this function.
245 Used in find_equiv_reg. */
246 int reload_first_uid
;
248 /* Flag set by local-alloc or global-alloc if anything is live in
249 a call-clobbered reg across calls. */
250 int caller_save_needed
;
252 /* Set to 1 while reload_as_needed is operating.
253 Required by some machines to handle any generated moves differently. */
254 int reload_in_progress
= 0;
256 /* These arrays record the insn_code of insns that may be needed to
257 perform input and output reloads of special objects. They provide a
258 place to pass a scratch register. */
259 enum insn_code reload_in_optab
[NUM_MACHINE_MODES
];
260 enum insn_code reload_out_optab
[NUM_MACHINE_MODES
];
262 /* This obstack is used for allocation of rtl during register elimination.
263 The allocated storage can be freed once find_reloads has processed the
265 struct obstack reload_obstack
;
267 /* Points to the beginning of the reload_obstack. All insn_chain structures
268 are allocated first. */
269 char *reload_startobj
;
271 /* The point after all insn_chain structures. Used to quickly deallocate
272 memory used while processing one insn. */
273 char *reload_firstobj
;
275 #define obstack_chunk_alloc xmalloc
276 #define obstack_chunk_free free
278 /* List of labels that must never be deleted. */
279 extern rtx forced_labels
;
281 /* List of insn_chain instructions, one for every insn that reload needs to
283 struct insn_chain
*reload_insn_chain
;
286 extern tree current_function_decl
;
288 extern union tree_node
*current_function_decl
;
291 /* List of all insns needing reloads. */
292 static struct insn_chain
*insns_need_reload
;
294 /* This structure is used to record information about register eliminations.
295 Each array entry describes one possible way of eliminating a register
296 in favor of another. If there is more than one way of eliminating a
297 particular register, the most preferred should be specified first. */
301 int from
; /* Register number to be eliminated. */
302 int to
; /* Register number used as replacement. */
303 int initial_offset
; /* Initial difference between values. */
304 int can_eliminate
; /* Non-zero if this elimination can be done. */
305 int can_eliminate_previous
; /* Value of CAN_ELIMINATE in previous scan over
306 insns made by reload. */
307 int offset
; /* Current offset between the two regs. */
308 int previous_offset
; /* Offset at end of previous insn. */
309 int ref_outside_mem
; /* "to" has been referenced outside a MEM. */
310 rtx from_rtx
; /* REG rtx for the register to be eliminated.
311 We cannot simply compare the number since
312 we might then spuriously replace a hard
313 register corresponding to a pseudo
314 assigned to the reg to be eliminated. */
315 rtx to_rtx
; /* REG rtx for the replacement. */
318 static struct elim_table
* reg_eliminate
= 0;
320 /* This is an intermediate structure to initialize the table. It has
321 exactly the members provided by ELIMINABLE_REGS. */
322 static struct elim_table_1
326 } reg_eliminate_1
[] =
328 /* If a set of eliminable registers was specified, define the table from it.
329 Otherwise, default to the normal case of the frame pointer being
330 replaced by the stack pointer. */
332 #ifdef ELIMINABLE_REGS
335 {{ FRAME_POINTER_REGNUM
, STACK_POINTER_REGNUM
}};
338 #define NUM_ELIMINABLE_REGS (sizeof reg_eliminate_1/sizeof reg_eliminate_1[0])
340 /* Record the number of pending eliminations that have an offset not equal
341 to their initial offset. If non-zero, we use a new copy of each
342 replacement result in any insns encountered. */
343 int num_not_at_initial_offset
;
345 /* Count the number of registers that we may be able to eliminate. */
346 static int num_eliminable
;
347 /* And the number of registers that are equivalent to a constant that
348 can be eliminated to frame_pointer / arg_pointer + constant. */
349 static int num_eliminable_invariants
;
351 /* For each label, we record the offset of each elimination. If we reach
352 a label by more than one path and an offset differs, we cannot do the
353 elimination. This information is indexed by the number of the label.
354 The first table is an array of flags that records whether we have yet
355 encountered a label and the second table is an array of arrays, one
356 entry in the latter array for each elimination. */
358 static char *offsets_known_at
;
359 static int (*offsets_at
)[NUM_ELIMINABLE_REGS
];
361 /* Number of labels in the current function. */
363 static int num_labels
;
365 struct hard_reg_n_uses
371 static void maybe_fix_stack_asms
PROTO((void));
372 static void calculate_needs_all_insns
PROTO((int));
373 static void calculate_needs
PROTO((struct insn_chain
*));
374 static void find_reload_regs
PROTO((struct insn_chain
*chain
,
376 static void find_tworeg_group
PROTO((struct insn_chain
*, int,
378 static void find_group
PROTO((struct insn_chain
*, int,
380 static int possible_group_p
PROTO((struct insn_chain
*, int));
381 static void count_possible_groups
PROTO((struct insn_chain
*, int));
382 static int modes_equiv_for_class_p
PROTO((enum machine_mode
,
385 static void delete_caller_save_insns
PROTO((void));
387 static void spill_failure
PROTO((rtx
));
388 static void new_spill_reg
PROTO((struct insn_chain
*, int, int,
390 static void maybe_mark_pseudo_spilled
PROTO((int));
391 static void delete_dead_insn
PROTO((rtx
));
392 static void alter_reg
PROTO((int, int));
393 static void set_label_offsets
PROTO((rtx
, rtx
, int));
394 static int eliminate_regs_in_insn
PROTO((rtx
, int));
395 static void update_eliminable_offsets
PROTO((void));
396 static void mark_not_eliminable
PROTO((rtx
, rtx
));
397 static void set_initial_elim_offsets
PROTO((void));
398 static void verify_initial_elim_offsets
PROTO((void));
399 static void set_initial_label_offsets
PROTO((void));
400 static void set_offsets_for_label
PROTO((rtx
));
401 static void init_elim_table
PROTO((void));
402 static void update_eliminables
PROTO((HARD_REG_SET
*));
403 static void spill_hard_reg
PROTO((int, FILE *, int));
404 static int finish_spills
PROTO((int, FILE *));
405 static void ior_hard_reg_set
PROTO((HARD_REG_SET
*, HARD_REG_SET
*));
406 static void scan_paradoxical_subregs
PROTO((rtx
));
407 static int hard_reg_use_compare
PROTO((const GENERIC_PTR
, const GENERIC_PTR
));
408 static void count_pseudo
PROTO((struct hard_reg_n_uses
*, int));
409 static void order_regs_for_reload
PROTO((struct insn_chain
*));
410 static void reload_as_needed
PROTO((int));
411 static void forget_old_reloads_1
PROTO((rtx
, rtx
));
412 static int reload_reg_class_lower
PROTO((const GENERIC_PTR
, const GENERIC_PTR
));
413 static void mark_reload_reg_in_use
PROTO((int, int, enum reload_type
,
415 static void clear_reload_reg_in_use
PROTO((int, int, enum reload_type
,
417 static int reload_reg_free_p
PROTO((int, int, enum reload_type
));
418 static int reload_reg_free_for_value_p
PROTO((int, int, enum reload_type
, rtx
, rtx
, int, int));
419 static int reload_reg_reaches_end_p
PROTO((int, int, enum reload_type
));
420 static int allocate_reload_reg
PROTO((struct insn_chain
*, int, int,
422 static void choose_reload_regs
PROTO((struct insn_chain
*));
423 static void merge_assigned_reloads
PROTO((rtx
));
424 static void emit_reload_insns
PROTO((struct insn_chain
*));
425 static void delete_output_reload
PROTO((rtx
, int, int));
426 static void delete_address_reloads
PROTO((rtx
, rtx
));
427 static void delete_address_reloads_1
PROTO((rtx
, rtx
, rtx
));
428 static rtx inc_for_reload
PROTO((rtx
, rtx
, rtx
, int));
429 static int constraint_accepts_reg_p
PROTO((char *, rtx
));
430 static void reload_cse_regs_1
PROTO((rtx
));
431 static void reload_cse_invalidate_regno
PROTO((int, enum machine_mode
, int));
432 static int reload_cse_mem_conflict_p
PROTO((rtx
, rtx
));
433 static void reload_cse_invalidate_mem
PROTO((rtx
));
434 static void reload_cse_invalidate_rtx
PROTO((rtx
, rtx
));
435 static int reload_cse_regno_equal_p
PROTO((int, rtx
, enum machine_mode
));
436 static int reload_cse_noop_set_p
PROTO((rtx
, rtx
));
437 static int reload_cse_simplify_set
PROTO((rtx
, rtx
));
438 static int reload_cse_simplify_operands
PROTO((rtx
));
439 static void reload_cse_check_clobber
PROTO((rtx
, rtx
));
440 static void reload_cse_record_set
PROTO((rtx
, rtx
));
441 static void reload_combine
PROTO((void));
442 static void reload_combine_note_use
PROTO((rtx
*, rtx
));
443 static void reload_combine_note_store
PROTO((rtx
, rtx
));
444 static void reload_cse_move2add
PROTO((rtx
));
445 static void move2add_note_store
PROTO((rtx
, rtx
));
447 /* Initialize the reload pass once per compilation. */
454 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
455 Set spill_indirect_levels to the number of levels such addressing is
456 permitted, zero if it is not permitted at all. */
459 = gen_rtx_MEM (Pmode
,
461 gen_rtx_REG (Pmode
, LAST_VIRTUAL_REGISTER
+ 1),
463 spill_indirect_levels
= 0;
465 while (memory_address_p (QImode
, tem
))
467 spill_indirect_levels
++;
468 tem
= gen_rtx_MEM (Pmode
, tem
);
471 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
473 tem
= gen_rtx_MEM (Pmode
, gen_rtx_SYMBOL_REF (Pmode
, "foo"));
474 indirect_symref_ok
= memory_address_p (QImode
, tem
);
476 /* See if reg+reg is a valid (and offsettable) address. */
478 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
480 tem
= gen_rtx_PLUS (Pmode
,
481 gen_rtx_REG (Pmode
, HARD_FRAME_POINTER_REGNUM
),
482 gen_rtx_REG (Pmode
, i
));
483 /* This way, we make sure that reg+reg is an offsettable address. */
484 tem
= plus_constant (tem
, 4);
486 if (memory_address_p (QImode
, tem
))
488 double_reg_address_ok
= 1;
493 /* Initialize obstack for our rtl allocation. */
494 gcc_obstack_init (&reload_obstack
);
495 reload_startobj
= (char *) obstack_alloc (&reload_obstack
, 0);
498 /* List of insn chains that are currently unused. */
499 static struct insn_chain
*unused_insn_chains
= 0;
501 /* Allocate an empty insn_chain structure. */
505 struct insn_chain
*c
;
507 if (unused_insn_chains
== 0)
509 c
= obstack_alloc (&reload_obstack
, sizeof (struct insn_chain
));
510 c
->live_before
= OBSTACK_ALLOC_REG_SET (&reload_obstack
);
511 c
->live_after
= OBSTACK_ALLOC_REG_SET (&reload_obstack
);
515 c
= unused_insn_chains
;
516 unused_insn_chains
= c
->next
;
518 c
->is_caller_save_insn
= 0;
519 c
->need_operand_change
= 0;
525 /* Small utility function to set all regs in hard reg set TO which are
526 allocated to pseudos in regset FROM. */
528 compute_use_by_pseudos (to
, from
)
533 EXECUTE_IF_SET_IN_REG_SET
534 (from
, FIRST_PSEUDO_REGISTER
, regno
,
536 int r
= reg_renumber
[regno
];
540 /* reload_combine uses the information from
541 basic_block_live_at_start, which might still contain registers
542 that have not actually been allocated since they have an
544 if (! reload_completed
)
549 nregs
= HARD_REGNO_NREGS (r
, PSEUDO_REGNO_MODE (regno
));
551 SET_HARD_REG_BIT (*to
, r
+ nregs
);
556 /* Global variables used by reload and its subroutines. */
558 /* Set during calculate_needs if an insn needs register elimination. */
559 static int something_needs_elimination
;
560 /* Set during calculate_needs if an insn needs an operand changed. */
561 int something_needs_operands_changed
;
563 /* Nonzero means we couldn't get enough spill regs. */
566 /* Main entry point for the reload pass.
568 FIRST is the first insn of the function being compiled.
570 GLOBAL nonzero means we were called from global_alloc
571 and should attempt to reallocate any pseudoregs that we
572 displace from hard regs we will use for reloads.
573 If GLOBAL is zero, we do not have enough information to do that,
574 so any pseudo reg that is spilled must go to the stack.
576 DUMPFILE is the global-reg debugging dump file stream, or 0.
577 If it is nonzero, messages are written to it to describe
578 which registers are seized as reload regs, which pseudo regs
579 are spilled from them, and where the pseudo regs are reallocated to.
581 Return value is nonzero if reload failed
582 and we must not do any more for this function. */
585 reload (first
, global
, dumpfile
)
592 register struct elim_table
*ep
;
594 /* The two pointers used to track the true location of the memory used
595 for label offsets. */
596 char *real_known_ptr
= NULL_PTR
;
597 int (*real_at_ptr
)[NUM_ELIMINABLE_REGS
];
599 /* Make sure even insns with volatile mem refs are recognizable. */
604 reload_firstobj
= (char *) obstack_alloc (&reload_obstack
, 0);
606 /* Make sure that the last insn in the chain
607 is not something that needs reloading. */
608 emit_note (NULL_PTR
, NOTE_INSN_DELETED
);
610 /* Enable find_equiv_reg to distinguish insns made by reload. */
611 reload_first_uid
= get_max_uid ();
613 #ifdef SECONDARY_MEMORY_NEEDED
614 /* Initialize the secondary memory table. */
615 clear_secondary_mem ();
618 /* We don't have a stack slot for any spill reg yet. */
619 bzero ((char *) spill_stack_slot
, sizeof spill_stack_slot
);
620 bzero ((char *) spill_stack_slot_width
, sizeof spill_stack_slot_width
);
622 /* Initialize the save area information for caller-save, in case some
626 /* Compute which hard registers are now in use
627 as homes for pseudo registers.
628 This is done here rather than (eg) in global_alloc
629 because this point is reached even if not optimizing. */
630 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
633 /* A function that receives a nonlocal goto must save all call-saved
635 if (current_function_has_nonlocal_label
)
636 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
638 if (! call_used_regs
[i
] && ! fixed_regs
[i
])
639 regs_ever_live
[i
] = 1;
642 /* Find all the pseudo registers that didn't get hard regs
643 but do have known equivalent constants or memory slots.
644 These include parameters (known equivalent to parameter slots)
645 and cse'd or loop-moved constant memory addresses.
647 Record constant equivalents in reg_equiv_constant
648 so they will be substituted by find_reloads.
649 Record memory equivalents in reg_mem_equiv so they can
650 be substituted eventually by altering the REG-rtx's. */
652 reg_equiv_constant
= (rtx
*) xmalloc (max_regno
* sizeof (rtx
));
653 bzero ((char *) reg_equiv_constant
, max_regno
* sizeof (rtx
));
654 reg_equiv_memory_loc
= (rtx
*) xmalloc (max_regno
* sizeof (rtx
));
655 bzero ((char *) reg_equiv_memory_loc
, max_regno
* sizeof (rtx
));
656 reg_equiv_mem
= (rtx
*) xmalloc (max_regno
* sizeof (rtx
));
657 bzero ((char *) reg_equiv_mem
, max_regno
* sizeof (rtx
));
658 reg_equiv_init
= (rtx
*) xmalloc (max_regno
* sizeof (rtx
));
659 bzero ((char *) reg_equiv_init
, max_regno
* sizeof (rtx
));
660 reg_equiv_address
= (rtx
*) xmalloc (max_regno
* sizeof (rtx
));
661 bzero ((char *) reg_equiv_address
, max_regno
* sizeof (rtx
));
662 reg_max_ref_width
= (int *) xmalloc (max_regno
* sizeof (int));
663 bzero ((char *) reg_max_ref_width
, max_regno
* sizeof (int));
664 reg_old_renumber
= (short *) xmalloc (max_regno
* sizeof (short));
665 bcopy (reg_renumber
, reg_old_renumber
, max_regno
* sizeof (short));
666 pseudo_forbidden_regs
667 = (HARD_REG_SET
*) xmalloc (max_regno
* sizeof (HARD_REG_SET
));
669 = (HARD_REG_SET
*) xmalloc (max_regno
* sizeof (HARD_REG_SET
));
671 CLEAR_HARD_REG_SET (bad_spill_regs_global
);
672 bzero ((char *) pseudo_previous_regs
, max_regno
* sizeof (HARD_REG_SET
));
674 /* Look for REG_EQUIV notes; record what each pseudo is equivalent to.
675 Also find all paradoxical subregs and find largest such for each pseudo.
676 On machines with small register classes, record hard registers that
677 are used for user variables. These can never be used for spills.
678 Also look for a "constant" NOTE_INSN_SETJMP. This means that all
679 caller-saved registers must be marked live. */
681 num_eliminable_invariants
= 0;
682 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
684 rtx set
= single_set (insn
);
686 if (GET_CODE (insn
) == NOTE
&& CONST_CALL_P (insn
)
687 && NOTE_LINE_NUMBER (insn
) == NOTE_INSN_SETJMP
)
688 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
689 if (! call_used_regs
[i
])
690 regs_ever_live
[i
] = 1;
692 if (set
!= 0 && GET_CODE (SET_DEST (set
)) == REG
)
694 rtx note
= find_reg_note (insn
, REG_EQUIV
, NULL_RTX
);
696 #ifdef LEGITIMATE_PIC_OPERAND_P
697 && (! function_invariant_p (XEXP (note
, 0))
699 || LEGITIMATE_PIC_OPERAND_P (XEXP (note
, 0)))
703 rtx x
= XEXP (note
, 0);
704 i
= REGNO (SET_DEST (set
));
705 if (i
> LAST_VIRTUAL_REGISTER
)
707 if (GET_CODE (x
) == MEM
)
709 /* If the operand is a PLUS, the MEM may be shared,
710 so make sure we have an unshared copy here. */
711 if (GET_CODE (XEXP (x
, 0)) == PLUS
)
714 reg_equiv_memory_loc
[i
] = x
;
716 else if (function_invariant_p (x
))
718 if (GET_CODE (x
) == PLUS
)
720 /* This is PLUS of frame pointer and a constant,
721 and might be shared. Unshare it. */
722 reg_equiv_constant
[i
] = copy_rtx (x
);
723 num_eliminable_invariants
++;
725 else if (x
== frame_pointer_rtx
726 || x
== arg_pointer_rtx
)
728 reg_equiv_constant
[i
] = x
;
729 num_eliminable_invariants
++;
731 else if (LEGITIMATE_CONSTANT_P (x
))
732 reg_equiv_constant
[i
] = x
;
734 reg_equiv_memory_loc
[i
]
735 = force_const_mem (GET_MODE (SET_DEST (set
)), x
);
740 /* If this register is being made equivalent to a MEM
741 and the MEM is not SET_SRC, the equivalencing insn
742 is one with the MEM as a SET_DEST and it occurs later.
743 So don't mark this insn now. */
744 if (GET_CODE (x
) != MEM
745 || rtx_equal_p (SET_SRC (set
), x
))
747 = gen_rtx_INSN_LIST (VOIDmode
, insn
, reg_equiv_init
[i
]);
752 /* If this insn is setting a MEM from a register equivalent to it,
753 this is the equivalencing insn. */
754 else if (set
&& GET_CODE (SET_DEST (set
)) == MEM
755 && GET_CODE (SET_SRC (set
)) == REG
756 && reg_equiv_memory_loc
[REGNO (SET_SRC (set
))]
757 && rtx_equal_p (SET_DEST (set
),
758 reg_equiv_memory_loc
[REGNO (SET_SRC (set
))]))
759 reg_equiv_init
[REGNO (SET_SRC (set
))]
760 = gen_rtx_INSN_LIST (VOIDmode
, insn
,
761 reg_equiv_init
[REGNO (SET_SRC (set
))]);
763 if (GET_RTX_CLASS (GET_CODE (insn
)) == 'i')
764 scan_paradoxical_subregs (PATTERN (insn
));
769 num_labels
= max_label_num () - get_first_label_num ();
771 /* Allocate the tables used to store offset information at labels. */
772 /* We used to use alloca here, but the size of what it would try to
773 allocate would occasionally cause it to exceed the stack limit and
774 cause a core dump. */
775 real_known_ptr
= xmalloc (num_labels
);
777 = (int (*)[NUM_ELIMINABLE_REGS
])
778 xmalloc (num_labels
* NUM_ELIMINABLE_REGS
* sizeof (int));
780 offsets_known_at
= real_known_ptr
- get_first_label_num ();
782 = (int (*)[NUM_ELIMINABLE_REGS
]) (real_at_ptr
- get_first_label_num ());
784 /* Alter each pseudo-reg rtx to contain its hard reg number.
785 Assign stack slots to the pseudos that lack hard regs or equivalents.
786 Do not touch virtual registers. */
788 for (i
= LAST_VIRTUAL_REGISTER
+ 1; i
< max_regno
; i
++)
791 /* If we have some registers we think can be eliminated, scan all insns to
792 see if there is an insn that sets one of these registers to something
793 other than itself plus a constant. If so, the register cannot be
794 eliminated. Doing this scan here eliminates an extra pass through the
795 main reload loop in the most common case where register elimination
797 for (insn
= first
; insn
&& num_eliminable
; insn
= NEXT_INSN (insn
))
798 if (GET_CODE (insn
) == INSN
|| GET_CODE (insn
) == JUMP_INSN
799 || GET_CODE (insn
) == CALL_INSN
)
800 note_stores (PATTERN (insn
), mark_not_eliminable
);
802 #ifndef REGISTER_CONSTRAINTS
803 /* If all the pseudo regs have hard regs,
804 except for those that are never referenced,
805 we know that no reloads are needed. */
806 /* But that is not true if there are register constraints, since
807 in that case some pseudos might be in the wrong kind of hard reg. */
809 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
810 if (reg_renumber
[i
] == -1 && REG_N_REFS (i
) != 0)
813 if (i
== max_regno
&& num_eliminable
== 0 && ! caller_save_needed
)
815 free (real_known_ptr
);
817 free (reg_equiv_constant
);
818 free (reg_equiv_memory_loc
);
819 free (reg_equiv_mem
);
820 free (reg_equiv_init
);
821 free (reg_equiv_address
);
822 free (reg_max_ref_width
);
823 free (reg_old_renumber
);
824 free (pseudo_previous_regs
);
825 free (pseudo_forbidden_regs
);
830 maybe_fix_stack_asms ();
832 insns_need_reload
= 0;
833 something_needs_elimination
= 0;
835 /* Initialize to -1, which means take the first spill register. */
838 spilled_pseudos
= ALLOCA_REG_SET ();
840 /* Spill any hard regs that we know we can't eliminate. */
841 CLEAR_HARD_REG_SET (used_spill_regs
);
842 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
843 if (! ep
->can_eliminate
)
844 spill_hard_reg (ep
->from
, dumpfile
, 1);
846 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
847 if (frame_pointer_needed
)
848 spill_hard_reg (HARD_FRAME_POINTER_REGNUM
, dumpfile
, 1);
850 finish_spills (global
, dumpfile
);
852 /* From now on, we may need to generate moves differently. We may also
853 allow modifications of insns which cause them to not be recognized.
854 Any such modifications will be cleaned up during reload itself. */
855 reload_in_progress
= 1;
857 /* This loop scans the entire function each go-round
858 and repeats until one repetition spills no additional hard regs. */
861 int something_changed
;
863 struct insn_chain
*chain
;
865 HOST_WIDE_INT starting_frame_size
;
867 /* Round size of stack frame to BIGGEST_ALIGNMENT. This must be done
868 here because the stack size may be a part of the offset computation
869 for register elimination, and there might have been new stack slots
870 created in the last iteration of this loop. */
871 assign_stack_local (BLKmode
, 0, 0);
873 starting_frame_size
= get_frame_size ();
875 set_initial_elim_offsets ();
876 set_initial_label_offsets ();
878 /* For each pseudo register that has an equivalent location defined,
879 try to eliminate any eliminable registers (such as the frame pointer)
880 assuming initial offsets for the replacement register, which
883 If the resulting location is directly addressable, substitute
884 the MEM we just got directly for the old REG.
886 If it is not addressable but is a constant or the sum of a hard reg
887 and constant, it is probably not addressable because the constant is
888 out of range, in that case record the address; we will generate
889 hairy code to compute the address in a register each time it is
890 needed. Similarly if it is a hard register, but one that is not
891 valid as an address register.
893 If the location is not addressable, but does not have one of the
894 above forms, assign a stack slot. We have to do this to avoid the
895 potential of producing lots of reloads if, e.g., a location involves
896 a pseudo that didn't get a hard register and has an equivalent memory
897 location that also involves a pseudo that didn't get a hard register.
899 Perhaps at some point we will improve reload_when_needed handling
900 so this problem goes away. But that's very hairy. */
902 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
903 if (reg_renumber
[i
] < 0 && reg_equiv_memory_loc
[i
])
905 rtx x
= eliminate_regs (reg_equiv_memory_loc
[i
], 0, NULL_RTX
);
907 if (strict_memory_address_p (GET_MODE (regno_reg_rtx
[i
]),
909 reg_equiv_mem
[i
] = x
, reg_equiv_address
[i
] = 0;
910 else if (CONSTANT_P (XEXP (x
, 0))
911 || (GET_CODE (XEXP (x
, 0)) == REG
912 && REGNO (XEXP (x
, 0)) < FIRST_PSEUDO_REGISTER
)
913 || (GET_CODE (XEXP (x
, 0)) == PLUS
914 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == REG
915 && (REGNO (XEXP (XEXP (x
, 0), 0))
916 < FIRST_PSEUDO_REGISTER
)
917 && CONSTANT_P (XEXP (XEXP (x
, 0), 1))))
918 reg_equiv_address
[i
] = XEXP (x
, 0), reg_equiv_mem
[i
] = 0;
921 /* Make a new stack slot. Then indicate that something
922 changed so we go back and recompute offsets for
923 eliminable registers because the allocation of memory
924 below might change some offset. reg_equiv_{mem,address}
925 will be set up for this pseudo on the next pass around
927 reg_equiv_memory_loc
[i
] = 0;
928 reg_equiv_init
[i
] = 0;
933 if (caller_save_needed
)
936 /* If we allocated another stack slot, redo elimination bookkeeping. */
937 if (starting_frame_size
!= get_frame_size ())
940 if (caller_save_needed
)
942 save_call_clobbered_regs ();
943 /* That might have allocated new insn_chain structures. */
944 reload_firstobj
= (char *) obstack_alloc (&reload_obstack
, 0);
947 calculate_needs_all_insns (global
);
949 CLEAR_REG_SET (spilled_pseudos
);
952 something_changed
= 0;
954 /* If we allocated any new memory locations, make another pass
955 since it might have changed elimination offsets. */
956 if (starting_frame_size
!= get_frame_size ())
957 something_changed
= 1;
960 HARD_REG_SET to_spill
;
961 CLEAR_HARD_REG_SET (to_spill
);
962 update_eliminables (&to_spill
);
963 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
964 if (TEST_HARD_REG_BIT (to_spill
, i
))
966 spill_hard_reg (i
, dumpfile
, 1);
969 /* Regardless of the state of spills, if we previously had
970 a register that we thought we could eliminate, but no can
971 not eliminate, we must run another pass.
973 Consider pseudos which have an entry in reg_equiv_* which
974 reference an eliminable register. We must make another pass
975 to update reg_equiv_* so that we do not substitute in the
976 old value from when we thought the elimination could be
978 something_changed
= 1;
982 CLEAR_HARD_REG_SET (used_spill_regs
);
983 /* Try to satisfy the needs for each insn. */
984 for (chain
= insns_need_reload
; chain
!= 0;
985 chain
= chain
->next_need_reload
)
986 find_reload_regs (chain
, dumpfile
);
991 if (insns_need_reload
!= 0 || did_spill
)
992 something_changed
|= finish_spills (global
, dumpfile
);
994 if (! something_changed
)
997 if (caller_save_needed
)
998 delete_caller_save_insns ();
1001 /* If global-alloc was run, notify it of any register eliminations we have
1004 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
1005 if (ep
->can_eliminate
)
1006 mark_elimination (ep
->from
, ep
->to
);
1008 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
1009 If that insn didn't set the register (i.e., it copied the register to
1010 memory), just delete that insn instead of the equivalencing insn plus
1011 anything now dead. If we call delete_dead_insn on that insn, we may
1012 delete the insn that actually sets the register if the register dies
1013 there and that is incorrect. */
1015 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
1017 if (reg_renumber
[i
] < 0 && reg_equiv_init
[i
] != 0)
1020 for (list
= reg_equiv_init
[i
]; list
; list
= XEXP (list
, 1))
1022 rtx equiv_insn
= XEXP (list
, 0);
1023 if (GET_CODE (equiv_insn
) == NOTE
)
1025 if (reg_set_p (regno_reg_rtx
[i
], PATTERN (equiv_insn
)))
1026 delete_dead_insn (equiv_insn
);
1029 PUT_CODE (equiv_insn
, NOTE
);
1030 NOTE_SOURCE_FILE (equiv_insn
) = 0;
1031 NOTE_LINE_NUMBER (equiv_insn
) = NOTE_INSN_DELETED
;
1037 /* Use the reload registers where necessary
1038 by generating move instructions to move the must-be-register
1039 values into or out of the reload registers. */
1041 if (insns_need_reload
!= 0 || something_needs_elimination
1042 || something_needs_operands_changed
)
1044 int old_frame_size
= get_frame_size ();
1046 reload_as_needed (global
);
1048 if (old_frame_size
!= get_frame_size ())
1052 verify_initial_elim_offsets ();
1055 /* If we were able to eliminate the frame pointer, show that it is no
1056 longer live at the start of any basic block. If it ls live by
1057 virtue of being in a pseudo, that pseudo will be marked live
1058 and hence the frame pointer will be known to be live via that
1061 if (! frame_pointer_needed
)
1062 for (i
= 0; i
< n_basic_blocks
; i
++)
1063 CLEAR_REGNO_REG_SET (basic_block_live_at_start
[i
],
1064 HARD_FRAME_POINTER_REGNUM
);
1066 /* Come here (with failure set nonzero) if we can't get enough spill regs
1067 and we decide not to abort about it. */
1070 reload_in_progress
= 0;
1072 /* Now eliminate all pseudo regs by modifying them into
1073 their equivalent memory references.
1074 The REG-rtx's for the pseudos are modified in place,
1075 so all insns that used to refer to them now refer to memory.
1077 For a reg that has a reg_equiv_address, all those insns
1078 were changed by reloading so that no insns refer to it any longer;
1079 but the DECL_RTL of a variable decl may refer to it,
1080 and if so this causes the debugging info to mention the variable. */
1082 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
1086 int is_readonly
= 0;
1088 if (reg_equiv_memory_loc
[i
])
1090 in_struct
= MEM_IN_STRUCT_P (reg_equiv_memory_loc
[i
]);
1091 is_readonly
= RTX_UNCHANGING_P (reg_equiv_memory_loc
[i
]);
1094 if (reg_equiv_mem
[i
])
1095 addr
= XEXP (reg_equiv_mem
[i
], 0);
1097 if (reg_equiv_address
[i
])
1098 addr
= reg_equiv_address
[i
];
1102 if (reg_renumber
[i
] < 0)
1104 rtx reg
= regno_reg_rtx
[i
];
1105 XEXP (reg
, 0) = addr
;
1106 REG_USERVAR_P (reg
) = 0;
1107 RTX_UNCHANGING_P (reg
) = is_readonly
;
1108 MEM_IN_STRUCT_P (reg
) = in_struct
;
1109 /* We have no alias information about this newly created
1111 MEM_ALIAS_SET (reg
) = 0;
1112 PUT_CODE (reg
, MEM
);
1114 else if (reg_equiv_mem
[i
])
1115 XEXP (reg_equiv_mem
[i
], 0) = addr
;
1119 /* We must set reload_completed now since the cleanup_subreg_operands call
1120 below will re-recognize each insn and reload may have generated insns
1121 which are only valid during and after reload. */
1122 reload_completed
= 1;
1124 /* Make a pass over all the insns and delete all USEs which we inserted
1125 only to tag a REG_EQUAL note on them. Remove all REG_DEAD and REG_UNUSED
1126 notes. Delete all CLOBBER insns and simplify (subreg (reg)) operands.
1127 Also remove all REG_RETVAL and REG_LIBCALL notes since they are no longer
1128 useful or accurate. */
1130 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
1131 if (GET_RTX_CLASS (GET_CODE (insn
)) == 'i')
1135 if ((GET_CODE (PATTERN (insn
)) == USE
1136 && find_reg_note (insn
, REG_EQUAL
, NULL_RTX
))
1137 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
1139 PUT_CODE (insn
, NOTE
);
1140 NOTE_SOURCE_FILE (insn
) = 0;
1141 NOTE_LINE_NUMBER (insn
) = NOTE_INSN_DELETED
;
1145 pnote
= ®_NOTES (insn
);
1148 if (REG_NOTE_KIND (*pnote
) == REG_DEAD
1149 || REG_NOTE_KIND (*pnote
) == REG_UNUSED
1150 || REG_NOTE_KIND (*pnote
) == REG_RETVAL
1151 || REG_NOTE_KIND (*pnote
) == REG_LIBCALL
)
1152 *pnote
= XEXP (*pnote
, 1);
1154 pnote
= &XEXP (*pnote
, 1);
1157 /* And simplify (subreg (reg)) if it appears as an operand. */
1158 cleanup_subreg_operands (insn
);
1161 /* If we are doing stack checking, give a warning if this function's
1162 frame size is larger than we expect. */
1163 if (flag_stack_check
&& ! STACK_CHECK_BUILTIN
)
1165 HOST_WIDE_INT size
= get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE
;
1167 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1168 if (regs_ever_live
[i
] && ! fixed_regs
[i
] && call_used_regs
[i
])
1169 size
+= UNITS_PER_WORD
;
1171 if (size
> STACK_CHECK_MAX_FRAME_SIZE
)
1172 warning ("frame size too large for reliable stack checking");
1175 /* Indicate that we no longer have known memory locations or constants. */
1176 if (reg_equiv_constant
)
1177 free (reg_equiv_constant
);
1178 reg_equiv_constant
= 0;
1179 if (reg_equiv_memory_loc
)
1180 free (reg_equiv_memory_loc
);
1181 reg_equiv_memory_loc
= 0;
1184 free (real_known_ptr
);
1188 free (reg_equiv_mem
);
1189 free (reg_equiv_init
);
1190 free (reg_equiv_address
);
1191 free (reg_max_ref_width
);
1192 free (reg_old_renumber
);
1193 free (pseudo_previous_regs
);
1194 free (pseudo_forbidden_regs
);
1196 FREE_REG_SET (spilled_pseudos
);
1198 CLEAR_HARD_REG_SET (used_spill_regs
);
1199 for (i
= 0; i
< n_spills
; i
++)
1200 SET_HARD_REG_BIT (used_spill_regs
, spill_regs
[i
]);
1202 /* Free all the insn_chain structures at once. */
1203 obstack_free (&reload_obstack
, reload_startobj
);
1204 unused_insn_chains
= 0;
1209 /* Yet another special case. Unfortunately, reg-stack forces people to
1210 write incorrect clobbers in asm statements. These clobbers must not
1211 cause the register to appear in bad_spill_regs, otherwise we'll call
1212 fatal_insn later. We clear the corresponding regnos in the live
1213 register sets to avoid this.
1214 The whole thing is rather sick, I'm afraid. */
1216 maybe_fix_stack_asms ()
1219 char *constraints
[MAX_RECOG_OPERANDS
];
1220 enum machine_mode operand_mode
[MAX_RECOG_OPERANDS
];
1221 struct insn_chain
*chain
;
1223 for (chain
= reload_insn_chain
; chain
!= 0; chain
= chain
->next
)
1226 HARD_REG_SET clobbered
, allowed
;
1229 if (GET_RTX_CLASS (GET_CODE (chain
->insn
)) != 'i'
1230 || (noperands
= asm_noperands (PATTERN (chain
->insn
))) < 0)
1232 pat
= PATTERN (chain
->insn
);
1233 if (GET_CODE (pat
) != PARALLEL
)
1236 CLEAR_HARD_REG_SET (clobbered
);
1237 CLEAR_HARD_REG_SET (allowed
);
1239 /* First, make a mask of all stack regs that are clobbered. */
1240 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
1242 rtx t
= XVECEXP (pat
, 0, i
);
1243 if (GET_CODE (t
) == CLOBBER
&& STACK_REG_P (XEXP (t
, 0)))
1244 SET_HARD_REG_BIT (clobbered
, REGNO (XEXP (t
, 0)));
1247 /* Get the operand values and constraints out of the insn. */
1248 decode_asm_operands (pat
, recog_operand
, recog_operand_loc
,
1249 constraints
, operand_mode
);
1251 /* For every operand, see what registers are allowed. */
1252 for (i
= 0; i
< noperands
; i
++)
1254 char *p
= constraints
[i
];
1255 /* For every alternative, we compute the class of registers allowed
1256 for reloading in CLS, and merge its contents into the reg set
1258 int cls
= (int) NO_REGS
;
1264 if (c
== '\0' || c
== ',' || c
== '#')
1266 /* End of one alternative - mark the regs in the current
1267 class, and reset the class. */
1268 IOR_HARD_REG_SET (allowed
, reg_class_contents
[cls
]);
1273 } while (c
!= '\0' && c
!= ',');
1281 case '=': case '+': case '*': case '%': case '?': case '!':
1282 case '0': case '1': case '2': case '3': case '4': case 'm':
1283 case '<': case '>': case 'V': case 'o': case '&': case 'E':
1284 case 'F': case 's': case 'i': case 'n': case 'X': case 'I':
1285 case 'J': case 'K': case 'L': case 'M': case 'N': case 'O':
1287 #ifdef EXTRA_CONSTRAINT
1288 case 'Q': case 'R': case 'S': case 'T': case 'U':
1293 cls
= (int) reg_class_subunion
[cls
][(int) BASE_REG_CLASS
];
1298 cls
= (int) reg_class_subunion
[cls
][(int) GENERAL_REGS
];
1302 cls
= (int) reg_class_subunion
[cls
][(int) REG_CLASS_FROM_LETTER (c
)];
1307 /* Those of the registers which are clobbered, but allowed by the
1308 constraints, must be usable as reload registers. So clear them
1309 out of the life information. */
1310 AND_HARD_REG_SET (allowed
, clobbered
);
1311 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1312 if (TEST_HARD_REG_BIT (allowed
, i
))
1314 CLEAR_REGNO_REG_SET (chain
->live_before
, i
);
1315 CLEAR_REGNO_REG_SET (chain
->live_after
, i
);
1323 /* Walk the chain of insns, and determine for each whether it needs reloads
1324 and/or eliminations. Build the corresponding insns_need_reload list, and
1325 set something_needs_elimination as appropriate. */
1327 calculate_needs_all_insns (global
)
1330 struct insn_chain
**pprev_reload
= &insns_need_reload
;
1331 struct insn_chain
**pchain
;
1333 something_needs_elimination
= 0;
1335 for (pchain
= &reload_insn_chain
; *pchain
!= 0; pchain
= &(*pchain
)->next
)
1338 struct insn_chain
*chain
;
1343 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1344 include REG_LABEL), we need to see what effects this has on the
1345 known offsets at labels. */
1347 if (GET_CODE (insn
) == CODE_LABEL
|| GET_CODE (insn
) == JUMP_INSN
1348 || (GET_RTX_CLASS (GET_CODE (insn
)) == 'i'
1349 && REG_NOTES (insn
) != 0))
1350 set_label_offsets (insn
, insn
, 0);
1352 if (GET_RTX_CLASS (GET_CODE (insn
)) == 'i')
1354 rtx old_body
= PATTERN (insn
);
1355 int old_code
= INSN_CODE (insn
);
1356 rtx old_notes
= REG_NOTES (insn
);
1357 int did_elimination
= 0;
1358 int operands_changed
= 0;
1359 rtx set
= single_set (insn
);
1361 /* Skip insns that only set an equivalence. */
1362 if (set
&& GET_CODE (SET_DEST (set
)) == REG
1363 && reg_renumber
[REGNO (SET_DEST (set
))] < 0
1364 && reg_equiv_constant
[REGNO (SET_DEST (set
))])
1367 /* If needed, eliminate any eliminable registers. */
1368 if (num_eliminable
|| num_eliminable_invariants
)
1369 did_elimination
= eliminate_regs_in_insn (insn
, 0);
1371 /* Analyze the instruction. */
1372 operands_changed
= find_reloads (insn
, 0, spill_indirect_levels
,
1373 global
, spill_reg_order
);
1375 /* If a no-op set needs more than one reload, this is likely
1376 to be something that needs input address reloads. We
1377 can't get rid of this cleanly later, and it is of no use
1378 anyway, so discard it now.
1379 We only do this when expensive_optimizations is enabled,
1380 since this complements reload inheritance / output
1381 reload deletion, and it can make debugging harder. */
1382 if (flag_expensive_optimizations
&& n_reloads
> 1)
1384 rtx set
= single_set (insn
);
1386 && SET_SRC (set
) == SET_DEST (set
)
1387 && GET_CODE (SET_SRC (set
)) == REG
1388 && REGNO (SET_SRC (set
)) >= FIRST_PSEUDO_REGISTER
)
1390 PUT_CODE (insn
, NOTE
);
1391 NOTE_SOURCE_FILE (insn
) = 0;
1392 NOTE_LINE_NUMBER (insn
) = NOTE_INSN_DELETED
;
1397 update_eliminable_offsets ();
1399 /* Remember for later shortcuts which insns had any reloads or
1400 register eliminations. */
1401 chain
->need_elim
= did_elimination
;
1402 chain
->need_reload
= n_reloads
> 0;
1403 chain
->need_operand_change
= operands_changed
;
1405 /* Discard any register replacements done. */
1406 if (did_elimination
)
1408 obstack_free (&reload_obstack
, reload_firstobj
);
1409 PATTERN (insn
) = old_body
;
1410 INSN_CODE (insn
) = old_code
;
1411 REG_NOTES (insn
) = old_notes
;
1412 something_needs_elimination
= 1;
1415 something_needs_operands_changed
|= operands_changed
;
1419 *pprev_reload
= chain
;
1420 pprev_reload
= &chain
->next_need_reload
;
1422 calculate_needs (chain
);
1429 /* Compute the most additional registers needed by one instruction,
1430 given by CHAIN. Collect information separately for each class of regs.
1432 To compute the number of reload registers of each class needed for an
1433 insn, we must simulate what choose_reload_regs can do. We do this by
1434 splitting an insn into an "input" and an "output" part. RELOAD_OTHER
1435 reloads are used in both. The input part uses those reloads,
1436 RELOAD_FOR_INPUT reloads, which must be live over the entire input section
1437 of reloads, and the maximum of all the RELOAD_FOR_INPUT_ADDRESS and
1438 RELOAD_FOR_OPERAND_ADDRESS reloads, which conflict with the inputs.
1440 The registers needed for output are RELOAD_OTHER and RELOAD_FOR_OUTPUT,
1441 which are live for the entire output portion, and the maximum of all the
1442 RELOAD_FOR_OUTPUT_ADDRESS reloads for each operand.
1444 The total number of registers needed is the maximum of the
1445 inputs and outputs. */
1448 calculate_needs (chain
)
1449 struct insn_chain
*chain
;
1453 /* Each `struct needs' corresponds to one RELOAD_... type. */
1457 struct needs output
;
1459 struct needs other_addr
;
1460 struct needs op_addr
;
1461 struct needs op_addr_reload
;
1462 struct needs in_addr
[MAX_RECOG_OPERANDS
];
1463 struct needs in_addr_addr
[MAX_RECOG_OPERANDS
];
1464 struct needs out_addr
[MAX_RECOG_OPERANDS
];
1465 struct needs out_addr_addr
[MAX_RECOG_OPERANDS
];
1468 bzero ((char *) chain
->group_size
, sizeof chain
->group_size
);
1469 for (i
= 0; i
< N_REG_CLASSES
; i
++)
1470 chain
->group_mode
[i
] = VOIDmode
;
1471 bzero ((char *) &insn_needs
, sizeof insn_needs
);
1473 /* Count each reload once in every class
1474 containing the reload's own class. */
1476 for (i
= 0; i
< n_reloads
; i
++)
1478 register enum reg_class
*p
;
1479 enum reg_class
class = reload_reg_class
[i
];
1481 enum machine_mode mode
;
1482 struct needs
*this_needs
;
1484 /* Don't count the dummy reloads, for which one of the
1485 regs mentioned in the insn can be used for reloading.
1486 Don't count optional reloads.
1487 Don't count reloads that got combined with others. */
1488 if (reload_reg_rtx
[i
] != 0
1489 || reload_optional
[i
] != 0
1490 || (reload_out
[i
] == 0 && reload_in
[i
] == 0
1491 && ! reload_secondary_p
[i
]))
1494 mode
= reload_inmode
[i
];
1495 if (GET_MODE_SIZE (reload_outmode
[i
]) > GET_MODE_SIZE (mode
))
1496 mode
= reload_outmode
[i
];
1497 size
= CLASS_MAX_NREGS (class, mode
);
1499 /* Decide which time-of-use to count this reload for. */
1500 switch (reload_when_needed
[i
])
1503 this_needs
= &insn_needs
.other
;
1505 case RELOAD_FOR_INPUT
:
1506 this_needs
= &insn_needs
.input
;
1508 case RELOAD_FOR_OUTPUT
:
1509 this_needs
= &insn_needs
.output
;
1511 case RELOAD_FOR_INSN
:
1512 this_needs
= &insn_needs
.insn
;
1514 case RELOAD_FOR_OTHER_ADDRESS
:
1515 this_needs
= &insn_needs
.other_addr
;
1517 case RELOAD_FOR_INPUT_ADDRESS
:
1518 this_needs
= &insn_needs
.in_addr
[reload_opnum
[i
]];
1520 case RELOAD_FOR_INPADDR_ADDRESS
:
1521 this_needs
= &insn_needs
.in_addr_addr
[reload_opnum
[i
]];
1523 case RELOAD_FOR_OUTPUT_ADDRESS
:
1524 this_needs
= &insn_needs
.out_addr
[reload_opnum
[i
]];
1526 case RELOAD_FOR_OUTADDR_ADDRESS
:
1527 this_needs
= &insn_needs
.out_addr_addr
[reload_opnum
[i
]];
1529 case RELOAD_FOR_OPERAND_ADDRESS
:
1530 this_needs
= &insn_needs
.op_addr
;
1532 case RELOAD_FOR_OPADDR_ADDR
:
1533 this_needs
= &insn_needs
.op_addr_reload
;
1541 enum machine_mode other_mode
, allocate_mode
;
1543 /* Count number of groups needed separately from
1544 number of individual regs needed. */
1545 this_needs
->groups
[(int) class]++;
1546 p
= reg_class_superclasses
[(int) class];
1547 while (*p
!= LIM_REG_CLASSES
)
1548 this_needs
->groups
[(int) *p
++]++;
1550 /* Record size and mode of a group of this class. */
1551 /* If more than one size group is needed,
1552 make all groups the largest needed size. */
1553 if (chain
->group_size
[(int) class] < size
)
1555 other_mode
= chain
->group_mode
[(int) class];
1556 allocate_mode
= mode
;
1558 chain
->group_size
[(int) class] = size
;
1559 chain
->group_mode
[(int) class] = mode
;
1564 allocate_mode
= chain
->group_mode
[(int) class];
1567 /* Crash if two dissimilar machine modes both need
1568 groups of consecutive regs of the same class. */
1570 if (other_mode
!= VOIDmode
&& other_mode
!= allocate_mode
1571 && ! modes_equiv_for_class_p (allocate_mode
,
1573 fatal_insn ("Two dissimilar machine modes both need groups of consecutive regs of the same class",
1578 this_needs
->regs
[(unsigned char)reload_nongroup
[i
]][(int) class] += 1;
1579 p
= reg_class_superclasses
[(int) class];
1580 while (*p
!= LIM_REG_CLASSES
)
1581 this_needs
->regs
[(unsigned char)reload_nongroup
[i
]][(int) *p
++] += 1;
1587 /* All reloads have been counted for this insn;
1588 now merge the various times of use.
1589 This sets insn_needs, etc., to the maximum total number
1590 of registers needed at any point in this insn. */
1592 for (i
= 0; i
< N_REG_CLASSES
; i
++)
1594 int j
, in_max
, out_max
;
1596 /* Compute normal and nongroup needs. */
1597 for (j
= 0; j
<= 1; j
++)
1600 for (in_max
= 0, out_max
= 0, k
= 0; k
< reload_n_operands
; k
++)
1602 in_max
= MAX (in_max
,
1603 (insn_needs
.in_addr
[k
].regs
[j
][i
]
1604 + insn_needs
.in_addr_addr
[k
].regs
[j
][i
]));
1605 out_max
= MAX (out_max
, insn_needs
.out_addr
[k
].regs
[j
][i
]);
1606 out_max
= MAX (out_max
,
1607 insn_needs
.out_addr_addr
[k
].regs
[j
][i
]);
1610 /* RELOAD_FOR_INSN reloads conflict with inputs, outputs,
1611 and operand addresses but not things used to reload
1612 them. Similarly, RELOAD_FOR_OPERAND_ADDRESS reloads
1613 don't conflict with things needed to reload inputs or
1616 in_max
= MAX (MAX (insn_needs
.op_addr
.regs
[j
][i
],
1617 insn_needs
.op_addr_reload
.regs
[j
][i
]),
1620 out_max
= MAX (out_max
, insn_needs
.insn
.regs
[j
][i
]);
1622 insn_needs
.input
.regs
[j
][i
]
1623 = MAX (insn_needs
.input
.regs
[j
][i
]
1624 + insn_needs
.op_addr
.regs
[j
][i
]
1625 + insn_needs
.insn
.regs
[j
][i
],
1626 in_max
+ insn_needs
.input
.regs
[j
][i
]);
1628 insn_needs
.output
.regs
[j
][i
] += out_max
;
1629 insn_needs
.other
.regs
[j
][i
]
1630 += MAX (MAX (insn_needs
.input
.regs
[j
][i
],
1631 insn_needs
.output
.regs
[j
][i
]),
1632 insn_needs
.other_addr
.regs
[j
][i
]);
1636 /* Now compute group needs. */
1637 for (in_max
= 0, out_max
= 0, j
= 0; j
< reload_n_operands
; j
++)
1639 in_max
= MAX (in_max
, insn_needs
.in_addr
[j
].groups
[i
]);
1640 in_max
= MAX (in_max
, insn_needs
.in_addr_addr
[j
].groups
[i
]);
1641 out_max
= MAX (out_max
, insn_needs
.out_addr
[j
].groups
[i
]);
1642 out_max
= MAX (out_max
, insn_needs
.out_addr_addr
[j
].groups
[i
]);
1645 in_max
= MAX (MAX (insn_needs
.op_addr
.groups
[i
],
1646 insn_needs
.op_addr_reload
.groups
[i
]),
1648 out_max
= MAX (out_max
, insn_needs
.insn
.groups
[i
]);
1650 insn_needs
.input
.groups
[i
]
1651 = MAX (insn_needs
.input
.groups
[i
]
1652 + insn_needs
.op_addr
.groups
[i
]
1653 + insn_needs
.insn
.groups
[i
],
1654 in_max
+ insn_needs
.input
.groups
[i
]);
1656 insn_needs
.output
.groups
[i
] += out_max
;
1657 insn_needs
.other
.groups
[i
]
1658 += MAX (MAX (insn_needs
.input
.groups
[i
],
1659 insn_needs
.output
.groups
[i
]),
1660 insn_needs
.other_addr
.groups
[i
]);
1663 /* Record the needs for later. */
1664 chain
->need
= insn_needs
.other
;
1667 /* Find a group of exactly 2 registers.
1669 First try to fill out the group by spilling a single register which
1670 would allow completion of the group.
1672 Then try to create a new group from a pair of registers, neither of
1673 which are explicitly used.
1675 Then try to create a group from any pair of registers. */
1678 find_tworeg_group (chain
, class, dumpfile
)
1679 struct insn_chain
*chain
;
1684 /* First, look for a register that will complete a group. */
1685 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1689 j
= potential_reload_regs
[i
];
1690 if (j
>= 0 && ! TEST_HARD_REG_BIT (bad_spill_regs
, j
)
1691 && ((j
> 0 && (other
= j
- 1, spill_reg_order
[other
] >= 0)
1692 && TEST_HARD_REG_BIT (reg_class_contents
[class], j
)
1693 && TEST_HARD_REG_BIT (reg_class_contents
[class], other
)
1694 && HARD_REGNO_MODE_OK (other
, chain
->group_mode
[class])
1695 && ! TEST_HARD_REG_BIT (chain
->counted_for_nongroups
, other
)
1696 /* We don't want one part of another group.
1697 We could get "two groups" that overlap! */
1698 && ! TEST_HARD_REG_BIT (chain
->counted_for_groups
, other
))
1699 || (j
< FIRST_PSEUDO_REGISTER
- 1
1700 && (other
= j
+ 1, spill_reg_order
[other
] >= 0)
1701 && TEST_HARD_REG_BIT (reg_class_contents
[class], j
)
1702 && TEST_HARD_REG_BIT (reg_class_contents
[class], other
)
1703 && HARD_REGNO_MODE_OK (j
, chain
->group_mode
[class])
1704 && ! TEST_HARD_REG_BIT (chain
->counted_for_nongroups
, other
)
1705 && ! TEST_HARD_REG_BIT (chain
->counted_for_groups
, other
))))
1707 register enum reg_class
*p
;
1709 /* We have found one that will complete a group,
1710 so count off one group as provided. */
1711 chain
->need
.groups
[class]--;
1712 p
= reg_class_superclasses
[class];
1713 while (*p
!= LIM_REG_CLASSES
)
1715 if (chain
->group_size
[(int) *p
] <= chain
->group_size
[class])
1716 chain
->need
.groups
[(int) *p
]--;
1720 /* Indicate both these regs are part of a group. */
1721 SET_HARD_REG_BIT (chain
->counted_for_groups
, j
);
1722 SET_HARD_REG_BIT (chain
->counted_for_groups
, other
);
1726 /* We can't complete a group, so start one. */
1727 if (i
== FIRST_PSEUDO_REGISTER
)
1728 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1731 j
= potential_reload_regs
[i
];
1732 /* Verify that J+1 is a potential reload reg. */
1733 for (k
= 0; k
< FIRST_PSEUDO_REGISTER
; k
++)
1734 if (potential_reload_regs
[k
] == j
+ 1)
1736 if (j
>= 0 && j
+ 1 < FIRST_PSEUDO_REGISTER
1737 && k
< FIRST_PSEUDO_REGISTER
1738 && spill_reg_order
[j
] < 0 && spill_reg_order
[j
+ 1] < 0
1739 && TEST_HARD_REG_BIT (reg_class_contents
[class], j
)
1740 && TEST_HARD_REG_BIT (reg_class_contents
[class], j
+ 1)
1741 && HARD_REGNO_MODE_OK (j
, chain
->group_mode
[class])
1742 && ! TEST_HARD_REG_BIT (chain
->counted_for_nongroups
, j
+ 1)
1743 && ! TEST_HARD_REG_BIT (bad_spill_regs
, j
+ 1))
1747 /* I should be the index in potential_reload_regs
1748 of the new reload reg we have found. */
1750 new_spill_reg (chain
, i
, class, 0, dumpfile
);
1753 /* Find a group of more than 2 registers.
1754 Look for a sufficient sequence of unspilled registers, and spill them all
1758 find_group (chain
, class, dumpfile
)
1759 struct insn_chain
*chain
;
1765 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1767 int j
= potential_reload_regs
[i
];
1770 && j
+ chain
->group_size
[class] <= FIRST_PSEUDO_REGISTER
1771 && HARD_REGNO_MODE_OK (j
, chain
->group_mode
[class]))
1774 /* Check each reg in the sequence. */
1775 for (k
= 0; k
< chain
->group_size
[class]; k
++)
1776 if (! (spill_reg_order
[j
+ k
] < 0
1777 && ! TEST_HARD_REG_BIT (bad_spill_regs
, j
+ k
)
1778 && TEST_HARD_REG_BIT (reg_class_contents
[class], j
+ k
)))
1780 /* We got a full sequence, so spill them all. */
1781 if (k
== chain
->group_size
[class])
1783 register enum reg_class
*p
;
1784 for (k
= 0; k
< chain
->group_size
[class]; k
++)
1787 SET_HARD_REG_BIT (chain
->counted_for_groups
, j
+ k
);
1788 for (idx
= 0; idx
< FIRST_PSEUDO_REGISTER
; idx
++)
1789 if (potential_reload_regs
[idx
] == j
+ k
)
1791 new_spill_reg (chain
, idx
, class, 0, dumpfile
);
1794 /* We have found one that will complete a group,
1795 so count off one group as provided. */
1796 chain
->need
.groups
[class]--;
1797 p
= reg_class_superclasses
[class];
1798 while (*p
!= LIM_REG_CLASSES
)
1800 if (chain
->group_size
[(int) *p
]
1801 <= chain
->group_size
[class])
1802 chain
->need
.groups
[(int) *p
]--;
1809 /* There are no groups left. */
1810 spill_failure (chain
->insn
);
1814 /* If pseudo REG conflicts with one of our reload registers, mark it as
1817 maybe_mark_pseudo_spilled (reg
)
1821 int r
= reg_renumber
[reg
];
1826 nregs
= HARD_REGNO_NREGS (r
, PSEUDO_REGNO_MODE (reg
));
1827 for (i
= 0; i
< n_spills
; i
++)
1828 if (r
<= spill_regs
[i
] && r
+ nregs
> spill_regs
[i
])
1830 SET_REGNO_REG_SET (spilled_pseudos
, reg
);
1835 /* Find more reload regs to satisfy the remaining need of an insn, which
1837 Do it by ascending class number, since otherwise a reg
1838 might be spilled for a big class and might fail to count
1839 for a smaller class even though it belongs to that class.
1841 Count spilled regs in `spills', and add entries to
1842 `spill_regs' and `spill_reg_order'.
1844 ??? Note there is a problem here.
1845 When there is a need for a group in a high-numbered class,
1846 and also need for non-group regs that come from a lower class,
1847 the non-group regs are chosen first. If there aren't many regs,
1848 they might leave no room for a group.
1850 This was happening on the 386. To fix it, we added the code
1851 that calls possible_group_p, so that the lower class won't
1852 break up the last possible group.
1854 Really fixing the problem would require changes above
1855 in counting the regs already spilled, and in choose_reload_regs.
1856 It might be hard to avoid introducing bugs there. */
1859 find_reload_regs (chain
, dumpfile
)
1860 struct insn_chain
*chain
;
1864 short *group_needs
= chain
->need
.groups
;
1865 short *simple_needs
= chain
->need
.regs
[0];
1866 short *nongroup_needs
= chain
->need
.regs
[1];
1869 fprintf (dumpfile
, "Spilling for insn %d.\n", INSN_UID (chain
->insn
));
1871 /* Compute the order of preference for hard registers to spill.
1872 Store them by decreasing preference in potential_reload_regs. */
1874 order_regs_for_reload (chain
);
1876 /* So far, no hard regs have been spilled. */
1878 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1879 spill_reg_order
[i
] = -1;
1881 CLEAR_HARD_REG_SET (chain
->used_spill_regs
);
1882 CLEAR_HARD_REG_SET (chain
->counted_for_groups
);
1883 CLEAR_HARD_REG_SET (chain
->counted_for_nongroups
);
1885 for (class = 0; class < N_REG_CLASSES
; class++)
1887 /* First get the groups of registers.
1888 If we got single registers first, we might fragment
1890 while (group_needs
[class] > 0)
1892 /* If any single spilled regs happen to form groups,
1893 count them now. Maybe we don't really need
1894 to spill another group. */
1895 count_possible_groups (chain
, class);
1897 if (group_needs
[class] <= 0)
1900 /* Groups of size 2, the only groups used on most machines,
1901 are treated specially. */
1902 if (chain
->group_size
[class] == 2)
1903 find_tworeg_group (chain
, class, dumpfile
);
1905 find_group (chain
, class, dumpfile
);
1910 /* Now similarly satisfy all need for single registers. */
1912 while (simple_needs
[class] > 0 || nongroup_needs
[class] > 0)
1914 /* If we spilled enough regs, but they weren't counted
1915 against the non-group need, see if we can count them now.
1916 If so, we can avoid some actual spilling. */
1917 if (simple_needs
[class] <= 0 && nongroup_needs
[class] > 0)
1918 for (i
= 0; i
< n_spills
; i
++)
1920 int regno
= spill_regs
[i
];
1921 if (TEST_HARD_REG_BIT (reg_class_contents
[class], regno
)
1922 && !TEST_HARD_REG_BIT (chain
->counted_for_groups
, regno
)
1923 && !TEST_HARD_REG_BIT (chain
->counted_for_nongroups
, regno
)
1924 && nongroup_needs
[class] > 0)
1926 register enum reg_class
*p
;
1928 SET_HARD_REG_BIT (chain
->counted_for_nongroups
, regno
);
1929 nongroup_needs
[class]--;
1930 p
= reg_class_superclasses
[class];
1931 while (*p
!= LIM_REG_CLASSES
)
1932 nongroup_needs
[(int) *p
++]--;
1936 if (simple_needs
[class] <= 0 && nongroup_needs
[class] <= 0)
1939 /* Consider the potential reload regs that aren't
1940 yet in use as reload regs, in order of preference.
1941 Find the most preferred one that's in this class. */
1943 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1945 int regno
= potential_reload_regs
[i
];
1947 && TEST_HARD_REG_BIT (reg_class_contents
[class], regno
)
1948 /* If this reg will not be available for groups,
1949 pick one that does not foreclose possible groups.
1950 This is a kludge, and not very general,
1951 but it should be sufficient to make the 386 work,
1952 and the problem should not occur on machines with
1954 && (nongroup_needs
[class] == 0
1955 || possible_group_p (chain
, regno
)))
1959 /* If we couldn't get a register, try to get one even if we
1960 might foreclose possible groups. This may cause problems
1961 later, but that's better than aborting now, since it is
1962 possible that we will, in fact, be able to form the needed
1963 group even with this allocation. */
1965 if (i
>= FIRST_PSEUDO_REGISTER
1966 && asm_noperands (chain
->insn
) < 0)
1967 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1968 if (potential_reload_regs
[i
] >= 0
1969 && TEST_HARD_REG_BIT (reg_class_contents
[class],
1970 potential_reload_regs
[i
]))
1973 /* I should be the index in potential_reload_regs
1974 of the new reload reg we have found. */
1976 new_spill_reg (chain
, i
, class, 1, dumpfile
);
1982 /* We know which hard regs to use, now mark the pseudos that live in them
1983 as needing to be kicked out. */
1984 EXECUTE_IF_SET_IN_REG_SET
1985 (chain
->live_before
, FIRST_PSEUDO_REGISTER
, i
,
1987 maybe_mark_pseudo_spilled (i
);
1989 EXECUTE_IF_SET_IN_REG_SET
1990 (chain
->live_after
, FIRST_PSEUDO_REGISTER
, i
,
1992 maybe_mark_pseudo_spilled (i
);
1995 IOR_HARD_REG_SET (used_spill_regs
, chain
->used_spill_regs
);
1999 dump_needs (chain
, dumpfile
)
2000 struct insn_chain
*chain
;
2003 static char *reg_class_names
[] = REG_CLASS_NAMES
;
2005 struct needs
*n
= &chain
->need
;
2007 for (i
= 0; i
< N_REG_CLASSES
; i
++)
2009 if (n
->regs
[i
][0] > 0)
2011 ";; Need %d reg%s of class %s.\n",
2012 n
->regs
[i
][0], n
->regs
[i
][0] == 1 ? "" : "s",
2013 reg_class_names
[i
]);
2014 if (n
->regs
[i
][1] > 0)
2016 ";; Need %d nongroup reg%s of class %s.\n",
2017 n
->regs
[i
][1], n
->regs
[i
][1] == 1 ? "" : "s",
2018 reg_class_names
[i
]);
2019 if (n
->groups
[i
] > 0)
2021 ";; Need %d group%s (%smode) of class %s.\n",
2022 n
->groups
[i
], n
->groups
[i
] == 1 ? "" : "s",
2023 mode_name
[(int) chain
->group_mode
[i
]],
2024 reg_class_names
[i
]);
2028 /* Delete all insns that were inserted by emit_caller_save_insns during
2031 delete_caller_save_insns ()
2033 struct insn_chain
*c
= reload_insn_chain
;
2037 while (c
!= 0 && c
->is_caller_save_insn
)
2039 struct insn_chain
*next
= c
->next
;
2042 if (insn
== BLOCK_HEAD (c
->block
))
2043 BLOCK_HEAD (c
->block
) = NEXT_INSN (insn
);
2044 if (insn
== BLOCK_END (c
->block
))
2045 BLOCK_END (c
->block
) = PREV_INSN (insn
);
2046 if (c
== reload_insn_chain
)
2047 reload_insn_chain
= next
;
2049 if (NEXT_INSN (insn
) != 0)
2050 PREV_INSN (NEXT_INSN (insn
)) = PREV_INSN (insn
);
2051 if (PREV_INSN (insn
) != 0)
2052 NEXT_INSN (PREV_INSN (insn
)) = NEXT_INSN (insn
);
2055 next
->prev
= c
->prev
;
2057 c
->prev
->next
= next
;
2058 c
->next
= unused_insn_chains
;
2059 unused_insn_chains
= c
;
2067 /* Nonzero if, after spilling reg REGNO for non-groups,
2068 it will still be possible to find a group if we still need one. */
2071 possible_group_p (chain
, regno
)
2072 struct insn_chain
*chain
;
2076 int class = (int) NO_REGS
;
2078 for (i
= 0; i
< (int) N_REG_CLASSES
; i
++)
2079 if (chain
->need
.groups
[i
] > 0)
2085 if (class == (int) NO_REGS
)
2088 /* Consider each pair of consecutive registers. */
2089 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
- 1; i
++)
2091 /* Ignore pairs that include reg REGNO. */
2092 if (i
== regno
|| i
+ 1 == regno
)
2095 /* Ignore pairs that are outside the class that needs the group.
2096 ??? Here we fail to handle the case where two different classes
2097 independently need groups. But this never happens with our
2098 current machine descriptions. */
2099 if (! (TEST_HARD_REG_BIT (reg_class_contents
[class], i
)
2100 && TEST_HARD_REG_BIT (reg_class_contents
[class], i
+ 1)))
2103 /* A pair of consecutive regs we can still spill does the trick. */
2104 if (spill_reg_order
[i
] < 0 && spill_reg_order
[i
+ 1] < 0
2105 && ! TEST_HARD_REG_BIT (bad_spill_regs
, i
)
2106 && ! TEST_HARD_REG_BIT (bad_spill_regs
, i
+ 1))
2109 /* A pair of one already spilled and one we can spill does it
2110 provided the one already spilled is not otherwise reserved. */
2111 if (spill_reg_order
[i
] < 0
2112 && ! TEST_HARD_REG_BIT (bad_spill_regs
, i
)
2113 && spill_reg_order
[i
+ 1] >= 0
2114 && ! TEST_HARD_REG_BIT (chain
->counted_for_groups
, i
+ 1)
2115 && ! TEST_HARD_REG_BIT (chain
->counted_for_nongroups
, i
+ 1))
2117 if (spill_reg_order
[i
+ 1] < 0
2118 && ! TEST_HARD_REG_BIT (bad_spill_regs
, i
+ 1)
2119 && spill_reg_order
[i
] >= 0
2120 && ! TEST_HARD_REG_BIT (chain
->counted_for_groups
, i
)
2121 && ! TEST_HARD_REG_BIT (chain
->counted_for_nongroups
, i
))
2128 /* Count any groups of CLASS that can be formed from the registers recently
2132 count_possible_groups (chain
, class)
2133 struct insn_chain
*chain
;
2139 /* Now find all consecutive groups of spilled registers
2140 and mark each group off against the need for such groups.
2141 But don't count them against ordinary need, yet. */
2143 if (chain
->group_size
[class] == 0)
2146 CLEAR_HARD_REG_SET (new);
2148 /* Make a mask of all the regs that are spill regs in class I. */
2149 for (i
= 0; i
< n_spills
; i
++)
2151 int regno
= spill_regs
[i
];
2153 if (TEST_HARD_REG_BIT (reg_class_contents
[class], regno
)
2154 && ! TEST_HARD_REG_BIT (chain
->counted_for_groups
, regno
)
2155 && ! TEST_HARD_REG_BIT (chain
->counted_for_nongroups
, regno
))
2156 SET_HARD_REG_BIT (new, regno
);
2159 /* Find each consecutive group of them. */
2160 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
&& chain
->need
.groups
[class] > 0; i
++)
2161 if (TEST_HARD_REG_BIT (new, i
)
2162 && i
+ chain
->group_size
[class] <= FIRST_PSEUDO_REGISTER
2163 && HARD_REGNO_MODE_OK (i
, chain
->group_mode
[class]))
2165 for (j
= 1; j
< chain
->group_size
[class]; j
++)
2166 if (! TEST_HARD_REG_BIT (new, i
+ j
))
2169 if (j
== chain
->group_size
[class])
2171 /* We found a group. Mark it off against this class's need for
2172 groups, and against each superclass too. */
2173 register enum reg_class
*p
;
2175 chain
->need
.groups
[class]--;
2176 p
= reg_class_superclasses
[class];
2177 while (*p
!= LIM_REG_CLASSES
)
2179 if (chain
->group_size
[(int) *p
] <= chain
->group_size
[class])
2180 chain
->need
.groups
[(int) *p
]--;
2184 /* Don't count these registers again. */
2185 for (j
= 0; j
< chain
->group_size
[class]; j
++)
2186 SET_HARD_REG_BIT (chain
->counted_for_groups
, i
+ j
);
2189 /* Skip to the last reg in this group. When i is incremented above,
2190 it will then point to the first reg of the next possible group. */
2195 /* ALLOCATE_MODE is a register mode that needs to be reloaded. OTHER_MODE is
2196 another mode that needs to be reloaded for the same register class CLASS.
2197 If any reg in CLASS allows ALLOCATE_MODE but not OTHER_MODE, fail.
2198 ALLOCATE_MODE will never be smaller than OTHER_MODE.
2200 This code used to also fail if any reg in CLASS allows OTHER_MODE but not
2201 ALLOCATE_MODE. This test is unnecessary, because we will never try to put
2202 something of mode ALLOCATE_MODE into an OTHER_MODE register. Testing this
2203 causes unnecessary failures on machines requiring alignment of register
2204 groups when the two modes are different sizes, because the larger mode has
2205 more strict alignment rules than the smaller mode. */
2208 modes_equiv_for_class_p (allocate_mode
, other_mode
, class)
2209 enum machine_mode allocate_mode
, other_mode
;
2210 enum reg_class
class;
2213 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
2215 if (TEST_HARD_REG_BIT (reg_class_contents
[(int) class], regno
)
2216 && HARD_REGNO_MODE_OK (regno
, allocate_mode
)
2217 && ! HARD_REGNO_MODE_OK (regno
, other_mode
))
2223 /* Handle the failure to find a register to spill.
2224 INSN should be one of the insns which needed this particular spill reg. */
2227 spill_failure (insn
)
2230 if (asm_noperands (PATTERN (insn
)) >= 0)
2231 error_for_asm (insn
, "`asm' needs too many reloads");
2233 fatal_insn ("Unable to find a register to spill.", insn
);
2236 /* Add a new register to the tables of available spill-registers.
2237 CHAIN is the insn for which the register will be used; we decrease the
2239 I is the index of this register in potential_reload_regs.
2240 CLASS is the regclass whose need is being satisfied.
2241 NONGROUP is 0 if this register is part of a group.
2242 DUMPFILE is the same as the one that `reload' got. */
2245 new_spill_reg (chain
, i
, class, nongroup
, dumpfile
)
2246 struct insn_chain
*chain
;
2252 register enum reg_class
*p
;
2253 int regno
= potential_reload_regs
[i
];
2255 if (i
>= FIRST_PSEUDO_REGISTER
)
2257 spill_failure (chain
->insn
);
2262 if (TEST_HARD_REG_BIT (bad_spill_regs
, regno
))
2264 static char *reg_class_names
[] = REG_CLASS_NAMES
;
2266 if (asm_noperands (PATTERN (chain
->insn
)) < 0)
2268 /* The error message is still correct - we know only that it wasn't
2269 an asm statement that caused the problem, but one of the global
2270 registers declared by the users might have screwed us. */
2271 error ("fixed or forbidden register %d (%s) was spilled for class %s.",
2272 regno
, reg_names
[regno
], reg_class_names
[class]);
2273 error ("This may be due to a compiler bug or to impossible asm");
2274 error ("statements or clauses.");
2275 fatal_insn ("This is the instruction:", chain
->insn
);
2277 error_for_asm (chain
->insn
, "Invalid `asm' statement:");
2278 error_for_asm (chain
->insn
,
2279 "fixed or forbidden register %d (%s) was spilled for class %s.",
2280 regno
, reg_names
[regno
], reg_class_names
[class]);
2285 /* Make reg REGNO an additional reload reg. */
2287 potential_reload_regs
[i
] = -1;
2288 spill_regs
[n_spills
] = regno
;
2289 spill_reg_order
[regno
] = n_spills
;
2291 fprintf (dumpfile
, "Spilling reg %d.\n", regno
);
2292 SET_HARD_REG_BIT (chain
->used_spill_regs
, regno
);
2294 /* Clear off the needs we just satisfied. */
2296 chain
->need
.regs
[0][class]--;
2297 p
= reg_class_superclasses
[class];
2298 while (*p
!= LIM_REG_CLASSES
)
2299 chain
->need
.regs
[0][(int) *p
++]--;
2301 if (nongroup
&& chain
->need
.regs
[1][class] > 0)
2303 SET_HARD_REG_BIT (chain
->counted_for_nongroups
, regno
);
2304 chain
->need
.regs
[1][class]--;
2305 p
= reg_class_superclasses
[class];
2306 while (*p
!= LIM_REG_CLASSES
)
2307 chain
->need
.regs
[1][(int) *p
++]--;
2313 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
2314 data that is dead in INSN. */
2317 delete_dead_insn (insn
)
2320 rtx prev
= prev_real_insn (insn
);
2323 /* If the previous insn sets a register that dies in our insn, delete it
2325 if (prev
&& GET_CODE (PATTERN (prev
)) == SET
2326 && (prev_dest
= SET_DEST (PATTERN (prev
)), GET_CODE (prev_dest
) == REG
)
2327 && reg_mentioned_p (prev_dest
, PATTERN (insn
))
2328 && find_regno_note (insn
, REG_DEAD
, REGNO (prev_dest
))
2329 && ! side_effects_p (SET_SRC (PATTERN (prev
))))
2330 delete_dead_insn (prev
);
2332 PUT_CODE (insn
, NOTE
);
2333 NOTE_LINE_NUMBER (insn
) = NOTE_INSN_DELETED
;
2334 NOTE_SOURCE_FILE (insn
) = 0;
2337 /* Modify the home of pseudo-reg I.
2338 The new home is present in reg_renumber[I].
2340 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
2341 or it may be -1, meaning there is none or it is not relevant.
2342 This is used so that all pseudos spilled from a given hard reg
2343 can share one stack slot. */
2346 alter_reg (i
, from_reg
)
2350 /* When outputting an inline function, this can happen
2351 for a reg that isn't actually used. */
2352 if (regno_reg_rtx
[i
] == 0)
2355 /* If the reg got changed to a MEM at rtl-generation time,
2357 if (GET_CODE (regno_reg_rtx
[i
]) != REG
)
2360 /* Modify the reg-rtx to contain the new hard reg
2361 number or else to contain its pseudo reg number. */
2362 REGNO (regno_reg_rtx
[i
])
2363 = reg_renumber
[i
] >= 0 ? reg_renumber
[i
] : i
;
2365 /* If we have a pseudo that is needed but has no hard reg or equivalent,
2366 allocate a stack slot for it. */
2368 if (reg_renumber
[i
] < 0
2369 && REG_N_REFS (i
) > 0
2370 && reg_equiv_constant
[i
] == 0
2371 && reg_equiv_memory_loc
[i
] == 0)
2374 int inherent_size
= PSEUDO_REGNO_BYTES (i
);
2375 int total_size
= MAX (inherent_size
, reg_max_ref_width
[i
]);
2378 /* Each pseudo reg has an inherent size which comes from its own mode,
2379 and a total size which provides room for paradoxical subregs
2380 which refer to the pseudo reg in wider modes.
2382 We can use a slot already allocated if it provides both
2383 enough inherent space and enough total space.
2384 Otherwise, we allocate a new slot, making sure that it has no less
2385 inherent space, and no less total space, then the previous slot. */
2388 /* No known place to spill from => no slot to reuse. */
2389 x
= assign_stack_local (GET_MODE (regno_reg_rtx
[i
]), total_size
,
2390 inherent_size
== total_size
? 0 : -1);
2391 if (BYTES_BIG_ENDIAN
)
2392 /* Cancel the big-endian correction done in assign_stack_local.
2393 Get the address of the beginning of the slot.
2394 This is so we can do a big-endian correction unconditionally
2396 adjust
= inherent_size
- total_size
;
2398 RTX_UNCHANGING_P (x
) = RTX_UNCHANGING_P (regno_reg_rtx
[i
]);
2400 /* Reuse a stack slot if possible. */
2401 else if (spill_stack_slot
[from_reg
] != 0
2402 && spill_stack_slot_width
[from_reg
] >= total_size
2403 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot
[from_reg
]))
2405 x
= spill_stack_slot
[from_reg
];
2406 /* Allocate a bigger slot. */
2409 /* Compute maximum size needed, both for inherent size
2410 and for total size. */
2411 enum machine_mode mode
= GET_MODE (regno_reg_rtx
[i
]);
2413 if (spill_stack_slot
[from_reg
])
2415 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot
[from_reg
]))
2417 mode
= GET_MODE (spill_stack_slot
[from_reg
]);
2418 if (spill_stack_slot_width
[from_reg
] > total_size
)
2419 total_size
= spill_stack_slot_width
[from_reg
];
2421 /* Make a slot with that size. */
2422 x
= assign_stack_local (mode
, total_size
,
2423 inherent_size
== total_size
? 0 : -1);
2425 if (BYTES_BIG_ENDIAN
)
2427 /* Cancel the big-endian correction done in assign_stack_local.
2428 Get the address of the beginning of the slot.
2429 This is so we can do a big-endian correction unconditionally
2431 adjust
= GET_MODE_SIZE (mode
) - total_size
;
2433 stack_slot
= gen_rtx_MEM (mode_for_size (total_size
2436 plus_constant (XEXP (x
, 0), adjust
));
2438 spill_stack_slot
[from_reg
] = stack_slot
;
2439 spill_stack_slot_width
[from_reg
] = total_size
;
2442 /* On a big endian machine, the "address" of the slot
2443 is the address of the low part that fits its inherent mode. */
2444 if (BYTES_BIG_ENDIAN
&& inherent_size
< total_size
)
2445 adjust
+= (total_size
- inherent_size
);
2447 /* If we have any adjustment to make, or if the stack slot is the
2448 wrong mode, make a new stack slot. */
2449 if (adjust
!= 0 || GET_MODE (x
) != GET_MODE (regno_reg_rtx
[i
]))
2451 x
= gen_rtx_MEM (GET_MODE (regno_reg_rtx
[i
]),
2452 plus_constant (XEXP (x
, 0), adjust
));
2454 /* If this was shared among registers, must ensure we never
2455 set it readonly since that can cause scheduling
2456 problems. Note we would only have in this adjustment
2457 case in any event, since the code above doesn't set it. */
2460 RTX_UNCHANGING_P (x
) = RTX_UNCHANGING_P (regno_reg_rtx
[i
]);
2463 /* Save the stack slot for later. */
2464 reg_equiv_memory_loc
[i
] = x
;
2468 /* Mark the slots in regs_ever_live for the hard regs
2469 used by pseudo-reg number REGNO. */
2472 mark_home_live (regno
)
2475 register int i
, lim
;
2476 i
= reg_renumber
[regno
];
2479 lim
= i
+ HARD_REGNO_NREGS (i
, PSEUDO_REGNO_MODE (regno
));
2481 regs_ever_live
[i
++] = 1;
2484 /* This function handles the tracking of elimination offsets around branches.
2486 X is a piece of RTL being scanned.
2488 INSN is the insn that it came from, if any.
2490 INITIAL_P is non-zero if we are to set the offset to be the initial
2491 offset and zero if we are setting the offset of the label to be the
2495 set_label_offsets (x
, insn
, initial_p
)
2500 enum rtx_code code
= GET_CODE (x
);
2503 struct elim_table
*p
;
2508 if (LABEL_REF_NONLOCAL_P (x
))
2513 /* ... fall through ... */
2516 /* If we know nothing about this label, set the desired offsets. Note
2517 that this sets the offset at a label to be the offset before a label
2518 if we don't know anything about the label. This is not correct for
2519 the label after a BARRIER, but is the best guess we can make. If
2520 we guessed wrong, we will suppress an elimination that might have
2521 been possible had we been able to guess correctly. */
2523 if (! offsets_known_at
[CODE_LABEL_NUMBER (x
)])
2525 for (i
= 0; i
< NUM_ELIMINABLE_REGS
; i
++)
2526 offsets_at
[CODE_LABEL_NUMBER (x
)][i
]
2527 = (initial_p
? reg_eliminate
[i
].initial_offset
2528 : reg_eliminate
[i
].offset
);
2529 offsets_known_at
[CODE_LABEL_NUMBER (x
)] = 1;
2532 /* Otherwise, if this is the definition of a label and it is
2533 preceded by a BARRIER, set our offsets to the known offset of
2537 && (tem
= prev_nonnote_insn (insn
)) != 0
2538 && GET_CODE (tem
) == BARRIER
)
2539 set_offsets_for_label (insn
);
2541 /* If neither of the above cases is true, compare each offset
2542 with those previously recorded and suppress any eliminations
2543 where the offsets disagree. */
2545 for (i
= 0; i
< NUM_ELIMINABLE_REGS
; i
++)
2546 if (offsets_at
[CODE_LABEL_NUMBER (x
)][i
]
2547 != (initial_p
? reg_eliminate
[i
].initial_offset
2548 : reg_eliminate
[i
].offset
))
2549 reg_eliminate
[i
].can_eliminate
= 0;
2554 set_label_offsets (PATTERN (insn
), insn
, initial_p
);
2556 /* ... fall through ... */
2560 /* Any labels mentioned in REG_LABEL notes can be branched to indirectly
2561 and hence must have all eliminations at their initial offsets. */
2562 for (tem
= REG_NOTES (x
); tem
; tem
= XEXP (tem
, 1))
2563 if (REG_NOTE_KIND (tem
) == REG_LABEL
)
2564 set_label_offsets (XEXP (tem
, 0), insn
, 1);
2569 /* Each of the labels in the address vector must be at their initial
2570 offsets. We want the first field for ADDR_VEC and the second
2571 field for ADDR_DIFF_VEC. */
2573 for (i
= 0; i
< (unsigned) XVECLEN (x
, code
== ADDR_DIFF_VEC
); i
++)
2574 set_label_offsets (XVECEXP (x
, code
== ADDR_DIFF_VEC
, i
),
2579 /* We only care about setting PC. If the source is not RETURN,
2580 IF_THEN_ELSE, or a label, disable any eliminations not at
2581 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2582 isn't one of those possibilities. For branches to a label,
2583 call ourselves recursively.
2585 Note that this can disable elimination unnecessarily when we have
2586 a non-local goto since it will look like a non-constant jump to
2587 someplace in the current function. This isn't a significant
2588 problem since such jumps will normally be when all elimination
2589 pairs are back to their initial offsets. */
2591 if (SET_DEST (x
) != pc_rtx
)
2594 switch (GET_CODE (SET_SRC (x
)))
2601 set_label_offsets (XEXP (SET_SRC (x
), 0), insn
, initial_p
);
2605 tem
= XEXP (SET_SRC (x
), 1);
2606 if (GET_CODE (tem
) == LABEL_REF
)
2607 set_label_offsets (XEXP (tem
, 0), insn
, initial_p
);
2608 else if (GET_CODE (tem
) != PC
&& GET_CODE (tem
) != RETURN
)
2611 tem
= XEXP (SET_SRC (x
), 2);
2612 if (GET_CODE (tem
) == LABEL_REF
)
2613 set_label_offsets (XEXP (tem
, 0), insn
, initial_p
);
2614 else if (GET_CODE (tem
) != PC
&& GET_CODE (tem
) != RETURN
)
2622 /* If we reach here, all eliminations must be at their initial
2623 offset because we are doing a jump to a variable address. */
2624 for (p
= reg_eliminate
; p
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; p
++)
2625 if (p
->offset
!= p
->initial_offset
)
2626 p
->can_eliminate
= 0;
2634 /* Used for communication between the next two function to properly share
2635 the vector for an ASM_OPERANDS. */
2637 static struct rtvec_def
*old_asm_operands_vec
, *new_asm_operands_vec
;
2639 /* Scan X and replace any eliminable registers (such as fp) with a
2640 replacement (such as sp), plus an offset.
2642 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2643 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2644 MEM, we are allowed to replace a sum of a register and the constant zero
2645 with the register, which we cannot do outside a MEM. In addition, we need
2646 to record the fact that a register is referenced outside a MEM.
2648 If INSN is an insn, it is the insn containing X. If we replace a REG
2649 in a SET_DEST with an equivalent MEM and INSN is non-zero, write a
2650 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2651 the REG is being modified.
2653 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2654 That's used when we eliminate in expressions stored in notes.
2655 This means, do not set ref_outside_mem even if the reference
2658 If we see a modification to a register we know about, take the
2659 appropriate action (see case SET, below).
2661 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2662 replacements done assuming all offsets are at their initial values. If
2663 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2664 encounter, return the actual location so that find_reloads will do
2665 the proper thing. */
2668 eliminate_regs (x
, mem_mode
, insn
)
2670 enum machine_mode mem_mode
;
2673 enum rtx_code code
= GET_CODE (x
);
2674 struct elim_table
*ep
;
2681 if (! current_function_decl
)
2700 /* This is only for the benefit of the debugging backends, which call
2701 eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are
2702 removed after CSE. */
2703 new = eliminate_regs (XEXP (x
, 0), 0, insn
);
2704 if (GET_CODE (new) == MEM
)
2705 return XEXP (new, 0);
2711 /* First handle the case where we encounter a bare register that
2712 is eliminable. Replace it with a PLUS. */
2713 if (regno
< FIRST_PSEUDO_REGISTER
)
2715 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
2717 if (ep
->from_rtx
== x
&& ep
->can_eliminate
)
2720 /* Refs inside notes don't count for this purpose. */
2721 && ! (insn
!= 0 && (GET_CODE (insn
) == EXPR_LIST
2722 || GET_CODE (insn
) == INSN_LIST
)))
2723 ep
->ref_outside_mem
= 1;
2724 return plus_constant (ep
->to_rtx
, ep
->previous_offset
);
2728 else if (reg_renumber
[regno
] < 0 && reg_equiv_constant
2729 && reg_equiv_constant
[regno
]
2730 && ! CONSTANT_P (reg_equiv_constant
[regno
]))
2731 return eliminate_regs (copy_rtx (reg_equiv_constant
[regno
]),
2736 /* If this is the sum of an eliminable register and a constant, rework
2738 if (GET_CODE (XEXP (x
, 0)) == REG
2739 && REGNO (XEXP (x
, 0)) < FIRST_PSEUDO_REGISTER
2740 && CONSTANT_P (XEXP (x
, 1)))
2742 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
2744 if (ep
->from_rtx
== XEXP (x
, 0) && ep
->can_eliminate
)
2747 /* Refs inside notes don't count for this purpose. */
2748 && ! (insn
!= 0 && (GET_CODE (insn
) == EXPR_LIST
2749 || GET_CODE (insn
) == INSN_LIST
)))
2750 ep
->ref_outside_mem
= 1;
2752 /* The only time we want to replace a PLUS with a REG (this
2753 occurs when the constant operand of the PLUS is the negative
2754 of the offset) is when we are inside a MEM. We won't want
2755 to do so at other times because that would change the
2756 structure of the insn in a way that reload can't handle.
2757 We special-case the commonest situation in
2758 eliminate_regs_in_insn, so just replace a PLUS with a
2759 PLUS here, unless inside a MEM. */
2760 if (mem_mode
!= 0 && GET_CODE (XEXP (x
, 1)) == CONST_INT
2761 && INTVAL (XEXP (x
, 1)) == - ep
->previous_offset
)
2764 return gen_rtx_PLUS (Pmode
, ep
->to_rtx
,
2765 plus_constant (XEXP (x
, 1),
2766 ep
->previous_offset
));
2769 /* If the register is not eliminable, we are done since the other
2770 operand is a constant. */
2774 /* If this is part of an address, we want to bring any constant to the
2775 outermost PLUS. We will do this by doing register replacement in
2776 our operands and seeing if a constant shows up in one of them.
2778 We assume here this is part of an address (or a "load address" insn)
2779 since an eliminable register is not likely to appear in any other
2782 If we have (plus (eliminable) (reg)), we want to produce
2783 (plus (plus (replacement) (reg) (const))). If this was part of a
2784 normal add insn, (plus (replacement) (reg)) will be pushed as a
2785 reload. This is the desired action. */
2788 rtx new0
= eliminate_regs (XEXP (x
, 0), mem_mode
, insn
);
2789 rtx new1
= eliminate_regs (XEXP (x
, 1), mem_mode
, insn
);
2791 if (new0
!= XEXP (x
, 0) || new1
!= XEXP (x
, 1))
2793 /* If one side is a PLUS and the other side is a pseudo that
2794 didn't get a hard register but has a reg_equiv_constant,
2795 we must replace the constant here since it may no longer
2796 be in the position of any operand. */
2797 if (GET_CODE (new0
) == PLUS
&& GET_CODE (new1
) == REG
2798 && REGNO (new1
) >= FIRST_PSEUDO_REGISTER
2799 && reg_renumber
[REGNO (new1
)] < 0
2800 && reg_equiv_constant
!= 0
2801 && reg_equiv_constant
[REGNO (new1
)] != 0)
2802 new1
= reg_equiv_constant
[REGNO (new1
)];
2803 else if (GET_CODE (new1
) == PLUS
&& GET_CODE (new0
) == REG
2804 && REGNO (new0
) >= FIRST_PSEUDO_REGISTER
2805 && reg_renumber
[REGNO (new0
)] < 0
2806 && reg_equiv_constant
[REGNO (new0
)] != 0)
2807 new0
= reg_equiv_constant
[REGNO (new0
)];
2809 new = form_sum (new0
, new1
);
2811 /* As above, if we are not inside a MEM we do not want to
2812 turn a PLUS into something else. We might try to do so here
2813 for an addition of 0 if we aren't optimizing. */
2814 if (! mem_mode
&& GET_CODE (new) != PLUS
)
2815 return gen_rtx_PLUS (GET_MODE (x
), new, const0_rtx
);
2823 /* If this is the product of an eliminable register and a
2824 constant, apply the distribute law and move the constant out
2825 so that we have (plus (mult ..) ..). This is needed in order
2826 to keep load-address insns valid. This case is pathological.
2827 We ignore the possibility of overflow here. */
2828 if (GET_CODE (XEXP (x
, 0)) == REG
2829 && REGNO (XEXP (x
, 0)) < FIRST_PSEUDO_REGISTER
2830 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
2831 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
2833 if (ep
->from_rtx
== XEXP (x
, 0) && ep
->can_eliminate
)
2836 /* Refs inside notes don't count for this purpose. */
2837 && ! (insn
!= 0 && (GET_CODE (insn
) == EXPR_LIST
2838 || GET_CODE (insn
) == INSN_LIST
)))
2839 ep
->ref_outside_mem
= 1;
2842 plus_constant (gen_rtx_MULT (Pmode
, ep
->to_rtx
, XEXP (x
, 1)),
2843 ep
->previous_offset
* INTVAL (XEXP (x
, 1)));
2846 /* ... fall through ... */
2851 case DIV
: case UDIV
:
2852 case MOD
: case UMOD
:
2853 case AND
: case IOR
: case XOR
:
2854 case ROTATERT
: case ROTATE
:
2855 case ASHIFTRT
: case LSHIFTRT
: case ASHIFT
:
2857 case GE
: case GT
: case GEU
: case GTU
:
2858 case LE
: case LT
: case LEU
: case LTU
:
2860 rtx new0
= eliminate_regs (XEXP (x
, 0), mem_mode
, insn
);
2862 = XEXP (x
, 1) ? eliminate_regs (XEXP (x
, 1), mem_mode
, insn
) : 0;
2864 if (new0
!= XEXP (x
, 0) || new1
!= XEXP (x
, 1))
2865 return gen_rtx_fmt_ee (code
, GET_MODE (x
), new0
, new1
);
2870 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2873 new = eliminate_regs (XEXP (x
, 0), mem_mode
, insn
);
2874 if (new != XEXP (x
, 0))
2875 x
= gen_rtx_EXPR_LIST (REG_NOTE_KIND (x
), new, XEXP (x
, 1));
2878 /* ... fall through ... */
2881 /* Now do eliminations in the rest of the chain. If this was
2882 an EXPR_LIST, this might result in allocating more memory than is
2883 strictly needed, but it simplifies the code. */
2886 new = eliminate_regs (XEXP (x
, 1), mem_mode
, insn
);
2887 if (new != XEXP (x
, 1))
2888 return gen_rtx_fmt_ee (GET_CODE (x
), GET_MODE (x
), XEXP (x
, 0), new);
2896 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
2897 if (ep
->to_rtx
== XEXP (x
, 0))
2899 int size
= GET_MODE_SIZE (mem_mode
);
2901 /* If more bytes than MEM_MODE are pushed, account for them. */
2902 #ifdef PUSH_ROUNDING
2903 if (ep
->to_rtx
== stack_pointer_rtx
)
2904 size
= PUSH_ROUNDING (size
);
2906 if (code
== PRE_DEC
|| code
== POST_DEC
)
2912 /* Fall through to generic unary operation case. */
2913 case STRICT_LOW_PART
:
2915 case SIGN_EXTEND
: case ZERO_EXTEND
:
2916 case TRUNCATE
: case FLOAT_EXTEND
: case FLOAT_TRUNCATE
:
2917 case FLOAT
: case FIX
:
2918 case UNSIGNED_FIX
: case UNSIGNED_FLOAT
:
2922 new = eliminate_regs (XEXP (x
, 0), mem_mode
, insn
);
2923 if (new != XEXP (x
, 0))
2924 return gen_rtx_fmt_e (code
, GET_MODE (x
), new);
2928 /* Similar to above processing, but preserve SUBREG_WORD.
2929 Convert (subreg (mem)) to (mem) if not paradoxical.
2930 Also, if we have a non-paradoxical (subreg (pseudo)) and the
2931 pseudo didn't get a hard reg, we must replace this with the
2932 eliminated version of the memory location because push_reloads
2933 may do the replacement in certain circumstances. */
2934 if (GET_CODE (SUBREG_REG (x
)) == REG
2935 && (GET_MODE_SIZE (GET_MODE (x
))
2936 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
2937 && reg_equiv_memory_loc
!= 0
2938 && reg_equiv_memory_loc
[REGNO (SUBREG_REG (x
))] != 0)
2941 new = eliminate_regs (reg_equiv_memory_loc
[REGNO (SUBREG_REG (x
))],
2944 /* If we didn't change anything, we must retain the pseudo. */
2945 if (new == reg_equiv_memory_loc
[REGNO (SUBREG_REG (x
))])
2946 new = SUBREG_REG (x
);
2949 /* In this case, we must show that the pseudo is used in this
2950 insn so that delete_output_reload will do the right thing. */
2951 if (insn
!= 0 && GET_CODE (insn
) != EXPR_LIST
2952 && GET_CODE (insn
) != INSN_LIST
)
2953 REG_NOTES (emit_insn_before (gen_rtx_USE (VOIDmode
,
2956 = gen_rtx_EXPR_LIST (REG_EQUAL
, new, NULL_RTX
);
2958 /* Ensure NEW isn't shared in case we have to reload it. */
2959 new = copy_rtx (new);
2962 new = SUBREG_REG (x
);
2966 new = eliminate_regs (SUBREG_REG (x
), mem_mode
, insn
);
2968 if (new != XEXP (x
, 0))
2970 int x_size
= GET_MODE_SIZE (GET_MODE (x
));
2971 int new_size
= GET_MODE_SIZE (GET_MODE (new));
2973 if (GET_CODE (new) == MEM
2974 && ((x_size
< new_size
2975 #ifdef WORD_REGISTER_OPERATIONS
2976 /* On these machines, combine can create rtl of the form
2977 (set (subreg:m1 (reg:m2 R) 0) ...)
2978 where m1 < m2, and expects something interesting to
2979 happen to the entire word. Moreover, it will use the
2980 (reg:m2 R) later, expecting all bits to be preserved.
2981 So if the number of words is the same, preserve the
2982 subreg so that push_reloads can see it. */
2983 && ! ((x_size
-1)/UNITS_PER_WORD
== (new_size
-1)/UNITS_PER_WORD
)
2986 || (x_size
== new_size
))
2989 int offset
= SUBREG_WORD (x
) * UNITS_PER_WORD
;
2990 enum machine_mode mode
= GET_MODE (x
);
2992 if (BYTES_BIG_ENDIAN
)
2993 offset
+= (MIN (UNITS_PER_WORD
,
2994 GET_MODE_SIZE (GET_MODE (new)))
2995 - MIN (UNITS_PER_WORD
, GET_MODE_SIZE (mode
)));
2997 PUT_MODE (new, mode
);
2998 XEXP (new, 0) = plus_constant (XEXP (new, 0), offset
);
3002 return gen_rtx_SUBREG (GET_MODE (x
), new, SUBREG_WORD (x
));
3008 /* If using a register that is the source of an eliminate we still
3009 think can be performed, note it cannot be performed since we don't
3010 know how this register is used. */
3011 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3012 if (ep
->from_rtx
== XEXP (x
, 0))
3013 ep
->can_eliminate
= 0;
3015 new = eliminate_regs (XEXP (x
, 0), mem_mode
, insn
);
3016 if (new != XEXP (x
, 0))
3017 return gen_rtx_fmt_e (code
, GET_MODE (x
), new);
3021 /* If clobbering a register that is the replacement register for an
3022 elimination we still think can be performed, note that it cannot
3023 be performed. Otherwise, we need not be concerned about it. */
3024 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3025 if (ep
->to_rtx
== XEXP (x
, 0))
3026 ep
->can_eliminate
= 0;
3028 new = eliminate_regs (XEXP (x
, 0), mem_mode
, insn
);
3029 if (new != XEXP (x
, 0))
3030 return gen_rtx_fmt_e (code
, GET_MODE (x
), new);
3036 /* Properly handle sharing input and constraint vectors. */
3037 if (ASM_OPERANDS_INPUT_VEC (x
) != old_asm_operands_vec
)
3039 /* When we come to a new vector not seen before,
3040 scan all its elements; keep the old vector if none
3041 of them changes; otherwise, make a copy. */
3042 old_asm_operands_vec
= ASM_OPERANDS_INPUT_VEC (x
);
3043 temp_vec
= (rtx
*) alloca (XVECLEN (x
, 3) * sizeof (rtx
));
3044 for (i
= 0; i
< ASM_OPERANDS_INPUT_LENGTH (x
); i
++)
3045 temp_vec
[i
] = eliminate_regs (ASM_OPERANDS_INPUT (x
, i
),
3048 for (i
= 0; i
< ASM_OPERANDS_INPUT_LENGTH (x
); i
++)
3049 if (temp_vec
[i
] != ASM_OPERANDS_INPUT (x
, i
))
3052 if (i
== ASM_OPERANDS_INPUT_LENGTH (x
))
3053 new_asm_operands_vec
= old_asm_operands_vec
;
3055 new_asm_operands_vec
3056 = gen_rtvec_v (ASM_OPERANDS_INPUT_LENGTH (x
), temp_vec
);
3059 /* If we had to copy the vector, copy the entire ASM_OPERANDS. */
3060 if (new_asm_operands_vec
== old_asm_operands_vec
)
3063 new = gen_rtx_ASM_OPERANDS (VOIDmode
, ASM_OPERANDS_TEMPLATE (x
),
3064 ASM_OPERANDS_OUTPUT_CONSTRAINT (x
),
3065 ASM_OPERANDS_OUTPUT_IDX (x
),
3066 new_asm_operands_vec
,
3067 ASM_OPERANDS_INPUT_CONSTRAINT_VEC (x
),
3068 ASM_OPERANDS_SOURCE_FILE (x
),
3069 ASM_OPERANDS_SOURCE_LINE (x
));
3070 new->volatil
= x
->volatil
;
3075 /* Check for setting a register that we know about. */
3076 if (GET_CODE (SET_DEST (x
)) == REG
)
3078 /* See if this is setting the replacement register for an
3081 If DEST is the hard frame pointer, we do nothing because we
3082 assume that all assignments to the frame pointer are for
3083 non-local gotos and are being done at a time when they are valid
3084 and do not disturb anything else. Some machines want to
3085 eliminate a fake argument pointer (or even a fake frame pointer)
3086 with either the real frame or the stack pointer. Assignments to
3087 the hard frame pointer must not prevent this elimination. */
3089 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
3091 if (ep
->to_rtx
== SET_DEST (x
)
3092 && SET_DEST (x
) != hard_frame_pointer_rtx
)
3094 /* If it is being incremented, adjust the offset. Otherwise,
3095 this elimination can't be done. */
3096 rtx src
= SET_SRC (x
);
3098 if (GET_CODE (src
) == PLUS
3099 && XEXP (src
, 0) == SET_DEST (x
)
3100 && GET_CODE (XEXP (src
, 1)) == CONST_INT
)
3101 ep
->offset
-= INTVAL (XEXP (src
, 1));
3103 ep
->can_eliminate
= 0;
3106 /* Now check to see we are assigning to a register that can be
3107 eliminated. If so, it must be as part of a PARALLEL, since we
3108 will not have been called if this is a single SET. So indicate
3109 that we can no longer eliminate this reg. */
3110 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
3112 if (ep
->from_rtx
== SET_DEST (x
) && ep
->can_eliminate
)
3113 ep
->can_eliminate
= 0;
3116 /* Now avoid the loop below in this common case. */
3118 rtx new0
= eliminate_regs (SET_DEST (x
), 0, insn
);
3119 rtx new1
= eliminate_regs (SET_SRC (x
), 0, insn
);
3121 /* If SET_DEST changed from a REG to a MEM and INSN is an insn,
3122 write a CLOBBER insn. */
3123 if (GET_CODE (SET_DEST (x
)) == REG
&& GET_CODE (new0
) == MEM
3124 && insn
!= 0 && GET_CODE (insn
) != EXPR_LIST
3125 && GET_CODE (insn
) != INSN_LIST
)
3126 emit_insn_after (gen_rtx_CLOBBER (VOIDmode
, SET_DEST (x
)), insn
);
3128 if (new0
!= SET_DEST (x
) || new1
!= SET_SRC (x
))
3129 return gen_rtx_SET (VOIDmode
, new0
, new1
);
3135 /* This is only for the benefit of the debugging backends, which call
3136 eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are
3137 removed after CSE. */
3138 if (GET_CODE (XEXP (x
, 0)) == ADDRESSOF
)
3139 return eliminate_regs (XEXP (XEXP (x
, 0), 0), 0, insn
);
3141 /* Our only special processing is to pass the mode of the MEM to our
3142 recursive call and copy the flags. While we are here, handle this
3143 case more efficiently. */
3144 new = eliminate_regs (XEXP (x
, 0), GET_MODE (x
), insn
);
3145 if (new != XEXP (x
, 0))
3147 new = gen_rtx_MEM (GET_MODE (x
), new);
3148 new->volatil
= x
->volatil
;
3149 new->unchanging
= x
->unchanging
;
3150 new->in_struct
= x
->in_struct
;
3160 /* Process each of our operands recursively. If any have changed, make a
3162 fmt
= GET_RTX_FORMAT (code
);
3163 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++, fmt
++)
3167 new = eliminate_regs (XEXP (x
, i
), mem_mode
, insn
);
3168 if (new != XEXP (x
, i
) && ! copied
)
3170 rtx new_x
= rtx_alloc (code
);
3171 bcopy ((char *) x
, (char *) new_x
,
3172 (sizeof (*new_x
) - sizeof (new_x
->fld
)
3173 + sizeof (new_x
->fld
[0]) * GET_RTX_LENGTH (code
)));
3179 else if (*fmt
== 'E')
3182 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
3184 new = eliminate_regs (XVECEXP (x
, i
, j
), mem_mode
, insn
);
3185 if (new != XVECEXP (x
, i
, j
) && ! copied_vec
)
3187 rtvec new_v
= gen_rtvec_vv (XVECLEN (x
, i
),
3191 rtx new_x
= rtx_alloc (code
);
3192 bcopy ((char *) x
, (char *) new_x
,
3193 (sizeof (*new_x
) - sizeof (new_x
->fld
)
3194 + (sizeof (new_x
->fld
[0])
3195 * GET_RTX_LENGTH (code
))));
3199 XVEC (x
, i
) = new_v
;
3202 XVECEXP (x
, i
, j
) = new;
3210 /* Scan INSN and eliminate all eliminable registers in it.
3212 If REPLACE is nonzero, do the replacement destructively. Also
3213 delete the insn as dead it if it is setting an eliminable register.
3215 If REPLACE is zero, do all our allocations in reload_obstack.
3217 If no eliminations were done and this insn doesn't require any elimination
3218 processing (these are not identical conditions: it might be updating sp,
3219 but not referencing fp; this needs to be seen during reload_as_needed so
3220 that the offset between fp and sp can be taken into consideration), zero
3221 is returned. Otherwise, 1 is returned. */
3224 eliminate_regs_in_insn (insn
, replace
)
3228 rtx old_body
= PATTERN (insn
);
3229 rtx old_set
= single_set (insn
);
3232 struct elim_table
*ep
;
3235 push_obstacks (&reload_obstack
, &reload_obstack
);
3237 if (old_set
!= 0 && GET_CODE (SET_DEST (old_set
)) == REG
3238 && REGNO (SET_DEST (old_set
)) < FIRST_PSEUDO_REGISTER
)
3240 /* Check for setting an eliminable register. */
3241 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3242 if (ep
->from_rtx
== SET_DEST (old_set
) && ep
->can_eliminate
)
3244 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3245 /* If this is setting the frame pointer register to the
3246 hardware frame pointer register and this is an elimination
3247 that will be done (tested above), this insn is really
3248 adjusting the frame pointer downward to compensate for
3249 the adjustment done before a nonlocal goto. */
3250 if (ep
->from
== FRAME_POINTER_REGNUM
3251 && ep
->to
== HARD_FRAME_POINTER_REGNUM
)
3253 rtx src
= SET_SRC (old_set
);
3254 int offset
= 0, ok
= 0;
3255 rtx prev_insn
, prev_set
;
3257 if (src
== ep
->to_rtx
)
3259 else if (GET_CODE (src
) == PLUS
3260 && GET_CODE (XEXP (src
, 0)) == CONST_INT
3261 && XEXP (src
, 1) == ep
->to_rtx
)
3262 offset
= INTVAL (XEXP (src
, 0)), ok
= 1;
3263 else if (GET_CODE (src
) == PLUS
3264 && GET_CODE (XEXP (src
, 1)) == CONST_INT
3265 && XEXP (src
, 0) == ep
->to_rtx
)
3266 offset
= INTVAL (XEXP (src
, 1)), ok
= 1;
3267 else if ((prev_insn
= prev_nonnote_insn (insn
)) != 0
3268 && (prev_set
= single_set (prev_insn
)) != 0
3269 && rtx_equal_p (SET_DEST (prev_set
), src
))
3271 src
= SET_SRC (prev_set
);
3272 if (src
== ep
->to_rtx
)
3274 else if (GET_CODE (src
) == PLUS
3275 && GET_CODE (XEXP (src
, 0)) == CONST_INT
3276 && XEXP (src
, 1) == ep
->to_rtx
)
3277 offset
= INTVAL (XEXP (src
, 0)), ok
= 1;
3278 else if (GET_CODE (src
) == PLUS
3279 && GET_CODE (XEXP (src
, 1)) == CONST_INT
3280 && XEXP (src
, 0) == ep
->to_rtx
)
3281 offset
= INTVAL (XEXP (src
, 1)), ok
= 1;
3289 = plus_constant (ep
->to_rtx
, offset
- ep
->offset
);
3291 /* First see if this insn remains valid when we
3292 make the change. If not, keep the INSN_CODE
3293 the same and let reload fit it up. */
3294 validate_change (insn
, &SET_SRC (old_set
), src
, 1);
3295 validate_change (insn
, &SET_DEST (old_set
),
3297 if (! apply_change_group ())
3299 SET_SRC (old_set
) = src
;
3300 SET_DEST (old_set
) = ep
->to_rtx
;
3310 /* In this case this insn isn't serving a useful purpose. We
3311 will delete it in reload_as_needed once we know that this
3312 elimination is, in fact, being done.
3314 If REPLACE isn't set, we can't delete this insn, but needn't
3315 process it since it won't be used unless something changes. */
3317 delete_dead_insn (insn
);
3322 /* Check for (set (reg) (plus (reg from) (offset))) where the offset
3323 in the insn is the negative of the offset in FROM. Substitute
3324 (set (reg) (reg to)) for the insn and change its code.
3326 We have to do this here, rather than in eliminate_regs, so that we can
3327 change the insn code. */
3329 if (GET_CODE (SET_SRC (old_set
)) == PLUS
3330 && GET_CODE (XEXP (SET_SRC (old_set
), 0)) == REG
3331 && GET_CODE (XEXP (SET_SRC (old_set
), 1)) == CONST_INT
)
3332 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
3334 if (ep
->from_rtx
== XEXP (SET_SRC (old_set
), 0)
3335 && ep
->can_eliminate
)
3337 /* We must stop at the first elimination that will be used.
3338 If this one would replace the PLUS with a REG, do it
3339 now. Otherwise, quit the loop and let eliminate_regs
3340 do its normal replacement. */
3341 if (ep
->offset
== - INTVAL (XEXP (SET_SRC (old_set
), 1)))
3343 /* We assume here that we don't need a PARALLEL of
3344 any CLOBBERs for this assignment. There's not
3345 much we can do if we do need it. */
3346 PATTERN (insn
) = gen_rtx_SET (VOIDmode
,
3349 INSN_CODE (insn
) = -1;
3358 old_asm_operands_vec
= 0;
3360 /* Replace the body of this insn with a substituted form. If we changed
3361 something, return non-zero.
3363 If we are replacing a body that was a (set X (plus Y Z)), try to
3364 re-recognize the insn. We do this in case we had a simple addition
3365 but now can do this as a load-address. This saves an insn in this
3368 new_body
= eliminate_regs (old_body
, 0, replace
? insn
: NULL_RTX
);
3369 if (new_body
!= old_body
)
3371 /* If we aren't replacing things permanently and we changed something,
3372 make another copy to ensure that all the RTL is new. Otherwise
3373 things can go wrong if find_reload swaps commutative operands
3374 and one is inside RTL that has been copied while the other is not. */
3376 /* Don't copy an asm_operands because (1) there's no need and (2)
3377 copy_rtx can't do it properly when there are multiple outputs. */
3378 if (! replace
&& asm_noperands (old_body
) < 0)
3379 new_body
= copy_rtx (new_body
);
3381 /* If we had a move insn but now we don't, rerecognize it. This will
3382 cause spurious re-recognition if the old move had a PARALLEL since
3383 the new one still will, but we can't call single_set without
3384 having put NEW_BODY into the insn and the re-recognition won't
3385 hurt in this rare case. */
3387 && ((GET_CODE (SET_SRC (old_set
)) == REG
3388 && (GET_CODE (new_body
) != SET
3389 || GET_CODE (SET_SRC (new_body
)) != REG
))
3390 /* If this was a load from or store to memory, compare
3391 the MEM in recog_operand to the one in the insn. If they
3392 are not equal, then rerecognize the insn. */
3394 && ((GET_CODE (SET_SRC (old_set
)) == MEM
3395 && SET_SRC (old_set
) != recog_operand
[1])
3396 || (GET_CODE (SET_DEST (old_set
)) == MEM
3397 && SET_DEST (old_set
) != recog_operand
[0])))
3398 /* If this was an add insn before, rerecognize. */
3399 || GET_CODE (SET_SRC (old_set
)) == PLUS
))
3401 if (! validate_change (insn
, &PATTERN (insn
), new_body
, 0))
3402 /* If recognition fails, store the new body anyway.
3403 It's normal to have recognition failures here
3404 due to bizarre memory addresses; reloading will fix them. */
3405 PATTERN (insn
) = new_body
;
3408 PATTERN (insn
) = new_body
;
3413 /* Loop through all elimination pairs. See if any have changed.
3415 We also detect a cases where register elimination cannot be done,
3416 namely, if a register would be both changed and referenced outside a MEM
3417 in the resulting insn since such an insn is often undefined and, even if
3418 not, we cannot know what meaning will be given to it. Note that it is
3419 valid to have a register used in an address in an insn that changes it
3420 (presumably with a pre- or post-increment or decrement).
3422 If anything changes, return nonzero. */
3424 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3426 if (ep
->previous_offset
!= ep
->offset
&& ep
->ref_outside_mem
)
3427 ep
->can_eliminate
= 0;
3429 ep
->ref_outside_mem
= 0;
3431 if (ep
->previous_offset
!= ep
->offset
)
3436 /* If we changed something, perform elimination in REG_NOTES. This is
3437 needed even when REPLACE is zero because a REG_DEAD note might refer
3438 to a register that we eliminate and could cause a different number
3439 of spill registers to be needed in the final reload pass than in
3441 if (val
&& REG_NOTES (insn
) != 0)
3442 REG_NOTES (insn
) = eliminate_regs (REG_NOTES (insn
), 0, REG_NOTES (insn
));
3450 /* Loop through all elimination pairs.
3451 Recalculate the number not at initial offset.
3453 Compute the maximum offset (minimum offset if the stack does not
3454 grow downward) for each elimination pair. */
3457 update_eliminable_offsets ()
3459 struct elim_table
*ep
;
3461 num_not_at_initial_offset
= 0;
3462 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3464 ep
->previous_offset
= ep
->offset
;
3465 if (ep
->can_eliminate
&& ep
->offset
!= ep
->initial_offset
)
3466 num_not_at_initial_offset
++;
3470 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3471 replacement we currently believe is valid, mark it as not eliminable if X
3472 modifies DEST in any way other than by adding a constant integer to it.
3474 If DEST is the frame pointer, we do nothing because we assume that
3475 all assignments to the hard frame pointer are nonlocal gotos and are being
3476 done at a time when they are valid and do not disturb anything else.
3477 Some machines want to eliminate a fake argument pointer with either the
3478 frame or stack pointer. Assignments to the hard frame pointer must not
3479 prevent this elimination.
3481 Called via note_stores from reload before starting its passes to scan
3482 the insns of the function. */
3485 mark_not_eliminable (dest
, x
)
3489 register unsigned int i
;
3491 /* A SUBREG of a hard register here is just changing its mode. We should
3492 not see a SUBREG of an eliminable hard register, but check just in
3494 if (GET_CODE (dest
) == SUBREG
)
3495 dest
= SUBREG_REG (dest
);
3497 if (dest
== hard_frame_pointer_rtx
)
3500 for (i
= 0; i
< NUM_ELIMINABLE_REGS
; i
++)
3501 if (reg_eliminate
[i
].can_eliminate
&& dest
== reg_eliminate
[i
].to_rtx
3502 && (GET_CODE (x
) != SET
3503 || GET_CODE (SET_SRC (x
)) != PLUS
3504 || XEXP (SET_SRC (x
), 0) != dest
3505 || GET_CODE (XEXP (SET_SRC (x
), 1)) != CONST_INT
))
3507 reg_eliminate
[i
].can_eliminate_previous
3508 = reg_eliminate
[i
].can_eliminate
= 0;
3513 /* Verify that the initial elimination offsets did not change since the
3514 last call to set_initial_elim_offsets. This is used to catch cases
3515 where something illegal happened during reload_as_needed that could
3516 cause incorrect code to be generated if we did not check for it. */
3518 verify_initial_elim_offsets ()
3522 #ifdef ELIMINABLE_REGS
3523 struct elim_table
*ep
;
3525 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3527 INITIAL_ELIMINATION_OFFSET (ep
->from
, ep
->to
, t
);
3528 if (t
!= ep
->initial_offset
)
3532 INITIAL_FRAME_POINTER_OFFSET (t
);
3533 if (t
!= reg_eliminate
[0].initial_offset
)
3538 /* Reset all offsets on eliminable registers to their initial values. */
3540 set_initial_elim_offsets ()
3542 struct elim_table
*ep
= reg_eliminate
;
3544 #ifdef ELIMINABLE_REGS
3545 for (; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3547 INITIAL_ELIMINATION_OFFSET (ep
->from
, ep
->to
, ep
->initial_offset
);
3548 ep
->previous_offset
= ep
->offset
= ep
->initial_offset
;
3551 INITIAL_FRAME_POINTER_OFFSET (ep
->initial_offset
);
3552 ep
->previous_offset
= ep
->offset
= ep
->initial_offset
;
3555 num_not_at_initial_offset
= 0;
3558 /* Initialize the known label offsets.
3559 Set a known offset for each forced label to be at the initial offset
3560 of each elimination. We do this because we assume that all
3561 computed jumps occur from a location where each elimination is
3562 at its initial offset.
3563 For all other labels, show that we don't know the offsets. */
3566 set_initial_label_offsets ()
3569 bzero ((char *) &offsets_known_at
[get_first_label_num ()], num_labels
);
3571 for (x
= forced_labels
; x
; x
= XEXP (x
, 1))
3573 set_label_offsets (XEXP (x
, 0), NULL_RTX
, 1);
3576 /* Set all elimination offsets to the known values for the code label given
3579 set_offsets_for_label (insn
)
3583 int label_nr
= CODE_LABEL_NUMBER (insn
);
3584 struct elim_table
*ep
;
3586 num_not_at_initial_offset
= 0;
3587 for (i
= 0, ep
= reg_eliminate
; i
< NUM_ELIMINABLE_REGS
; ep
++, i
++)
3589 ep
->offset
= ep
->previous_offset
= offsets_at
[label_nr
][i
];
3590 if (ep
->can_eliminate
&& ep
->offset
!= ep
->initial_offset
)
3591 num_not_at_initial_offset
++;
3595 /* See if anything that happened changes which eliminations are valid.
3596 For example, on the Sparc, whether or not the frame pointer can
3597 be eliminated can depend on what registers have been used. We need
3598 not check some conditions again (such as flag_omit_frame_pointer)
3599 since they can't have changed. */
3602 update_eliminables (pset
)
3605 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3606 int previous_frame_pointer_needed
= frame_pointer_needed
;
3608 struct elim_table
*ep
;
3610 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3611 if ((ep
->from
== HARD_FRAME_POINTER_REGNUM
&& FRAME_POINTER_REQUIRED
)
3612 #ifdef ELIMINABLE_REGS
3613 || ! CAN_ELIMINATE (ep
->from
, ep
->to
)
3616 ep
->can_eliminate
= 0;
3618 /* Look for the case where we have discovered that we can't replace
3619 register A with register B and that means that we will now be
3620 trying to replace register A with register C. This means we can
3621 no longer replace register C with register B and we need to disable
3622 such an elimination, if it exists. This occurs often with A == ap,
3623 B == sp, and C == fp. */
3625 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3627 struct elim_table
*op
;
3628 register int new_to
= -1;
3630 if (! ep
->can_eliminate
&& ep
->can_eliminate_previous
)
3632 /* Find the current elimination for ep->from, if there is a
3634 for (op
= reg_eliminate
;
3635 op
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; op
++)
3636 if (op
->from
== ep
->from
&& op
->can_eliminate
)
3642 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
3644 for (op
= reg_eliminate
;
3645 op
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; op
++)
3646 if (op
->from
== new_to
&& op
->to
== ep
->to
)
3647 op
->can_eliminate
= 0;
3651 /* See if any registers that we thought we could eliminate the previous
3652 time are no longer eliminable. If so, something has changed and we
3653 must spill the register. Also, recompute the number of eliminable
3654 registers and see if the frame pointer is needed; it is if there is
3655 no elimination of the frame pointer that we can perform. */
3657 frame_pointer_needed
= 1;
3658 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3660 if (ep
->can_eliminate
&& ep
->from
== FRAME_POINTER_REGNUM
3661 && ep
->to
!= HARD_FRAME_POINTER_REGNUM
)
3662 frame_pointer_needed
= 0;
3664 if (! ep
->can_eliminate
&& ep
->can_eliminate_previous
)
3666 ep
->can_eliminate_previous
= 0;
3667 SET_HARD_REG_BIT (*pset
, ep
->from
);
3672 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3673 /* If we didn't need a frame pointer last time, but we do now, spill
3674 the hard frame pointer. */
3675 if (frame_pointer_needed
&& ! previous_frame_pointer_needed
)
3676 SET_HARD_REG_BIT (*pset
, HARD_FRAME_POINTER_REGNUM
);
3680 /* Initialize the table of registers to eliminate. */
3684 struct elim_table
*ep
;
3685 #ifdef ELIMINABLE_REGS
3686 struct elim_table_1
*ep1
;
3691 reg_eliminate
= (struct elim_table
*)
3692 xmalloc(sizeof(struct elim_table
) * NUM_ELIMINABLE_REGS
);
3693 bzero ((PTR
) reg_eliminate
,
3694 sizeof(struct elim_table
) * NUM_ELIMINABLE_REGS
);
3697 /* Does this function require a frame pointer? */
3699 frame_pointer_needed
= (! flag_omit_frame_pointer
3700 #ifdef EXIT_IGNORE_STACK
3701 /* ?? If EXIT_IGNORE_STACK is set, we will not save
3702 and restore sp for alloca. So we can't eliminate
3703 the frame pointer in that case. At some point,
3704 we should improve this by emitting the
3705 sp-adjusting insns for this case. */
3706 || (current_function_calls_alloca
3707 && EXIT_IGNORE_STACK
)
3709 || FRAME_POINTER_REQUIRED
);
3713 #ifdef ELIMINABLE_REGS
3714 for (ep
= reg_eliminate
, ep1
= reg_eliminate_1
;
3715 ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++, ep1
++)
3717 ep
->from
= ep1
->from
;
3719 ep
->can_eliminate
= ep
->can_eliminate_previous
3720 = (CAN_ELIMINATE (ep
->from
, ep
->to
)
3721 && ! (ep
->to
== STACK_POINTER_REGNUM
&& frame_pointer_needed
));
3724 reg_eliminate
[0].from
= reg_eliminate_1
[0].from
;
3725 reg_eliminate
[0].to
= reg_eliminate_1
[0].to
;
3726 reg_eliminate
[0].can_eliminate
= reg_eliminate
[0].can_eliminate_previous
3727 = ! frame_pointer_needed
;
3730 /* Count the number of eliminable registers and build the FROM and TO
3731 REG rtx's. Note that code in gen_rtx will cause, e.g.,
3732 gen_rtx (REG, Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
3733 We depend on this. */
3734 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3736 num_eliminable
+= ep
->can_eliminate
;
3737 ep
->from_rtx
= gen_rtx_REG (Pmode
, ep
->from
);
3738 ep
->to_rtx
= gen_rtx_REG (Pmode
, ep
->to
);
3742 /* Kick all pseudos out of hard register REGNO.
3743 If DUMPFILE is nonzero, log actions taken on that file.
3745 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
3746 because we found we can't eliminate some register. In the case, no pseudos
3747 are allowed to be in the register, even if they are only in a block that
3748 doesn't require spill registers, unlike the case when we are spilling this
3749 hard reg to produce another spill register.
3751 Return nonzero if any pseudos needed to be kicked out. */
3754 spill_hard_reg (regno
, dumpfile
, cant_eliminate
)
3763 SET_HARD_REG_BIT (bad_spill_regs_global
, regno
);
3764 regs_ever_live
[regno
] = 1;
3767 /* Spill every pseudo reg that was allocated to this reg
3768 or to something that overlaps this reg. */
3770 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
3771 if (reg_renumber
[i
] >= 0
3772 && reg_renumber
[i
] <= regno
3774 + HARD_REGNO_NREGS (reg_renumber
[i
],
3775 PSEUDO_REGNO_MODE (i
))
3777 SET_REGNO_REG_SET (spilled_pseudos
, i
);
3780 /* I'm getting weird preprocessor errors if I use IOR_HARD_REG_SET
3781 from within EXECUTE_IF_SET_IN_REG_SET. Hence this awkwardness. */
3783 ior_hard_reg_set (set1
, set2
)
3784 HARD_REG_SET
*set1
, *set2
;
3786 IOR_HARD_REG_SET (*set1
, *set2
);
3789 /* After find_reload_regs has been run for all insn that need reloads,
3790 and/or spill_hard_regs was called, this function is used to actually
3791 spill pseudo registers and try to reallocate them. It also sets up the
3792 spill_regs array for use by choose_reload_regs. */
3795 finish_spills (global
, dumpfile
)
3799 struct insn_chain
*chain
;
3800 int something_changed
= 0;
3803 /* Build the spill_regs array for the function. */
3804 /* If there are some registers still to eliminate and one of the spill regs
3805 wasn't ever used before, additional stack space may have to be
3806 allocated to store this register. Thus, we may have changed the offset
3807 between the stack and frame pointers, so mark that something has changed.
3809 One might think that we need only set VAL to 1 if this is a call-used
3810 register. However, the set of registers that must be saved by the
3811 prologue is not identical to the call-used set. For example, the
3812 register used by the call insn for the return PC is a call-used register,
3813 but must be saved by the prologue. */
3816 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
3817 if (TEST_HARD_REG_BIT (used_spill_regs
, i
))
3819 spill_reg_order
[i
] = n_spills
;
3820 spill_regs
[n_spills
++] = i
;
3821 if (num_eliminable
&& ! regs_ever_live
[i
])
3822 something_changed
= 1;
3823 regs_ever_live
[i
] = 1;
3826 spill_reg_order
[i
] = -1;
3828 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
3829 if (REGNO_REG_SET_P (spilled_pseudos
, i
))
3831 /* Record the current hard register the pseudo is allocated to in
3832 pseudo_previous_regs so we avoid reallocating it to the same
3833 hard reg in a later pass. */
3834 if (reg_renumber
[i
] < 0)
3836 SET_HARD_REG_BIT (pseudo_previous_regs
[i
], reg_renumber
[i
]);
3837 /* Mark it as no longer having a hard register home. */
3838 reg_renumber
[i
] = -1;
3839 /* We will need to scan everything again. */
3840 something_changed
= 1;
3843 /* Retry global register allocation if possible. */
3846 bzero ((char *) pseudo_forbidden_regs
, max_regno
* sizeof (HARD_REG_SET
));
3847 /* For every insn that needs reloads, set the registers used as spill
3848 regs in pseudo_forbidden_regs for every pseudo live across the
3850 for (chain
= insns_need_reload
; chain
; chain
= chain
->next_need_reload
)
3852 EXECUTE_IF_SET_IN_REG_SET
3853 (chain
->live_before
, FIRST_PSEUDO_REGISTER
, i
,
3855 ior_hard_reg_set (pseudo_forbidden_regs
+ i
,
3856 &chain
->used_spill_regs
);
3858 EXECUTE_IF_SET_IN_REG_SET
3859 (chain
->live_after
, FIRST_PSEUDO_REGISTER
, i
,
3861 ior_hard_reg_set (pseudo_forbidden_regs
+ i
,
3862 &chain
->used_spill_regs
);
3866 /* Retry allocating the spilled pseudos. For each reg, merge the
3867 various reg sets that indicate which hard regs can't be used,
3868 and call retry_global_alloc.
3869 We change spill_pseudos here to only contain pseudos that did not
3870 get a new hard register. */
3871 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
3872 if (reg_old_renumber
[i
] != reg_renumber
[i
])
3874 HARD_REG_SET forbidden
;
3875 COPY_HARD_REG_SET (forbidden
, bad_spill_regs_global
);
3876 IOR_HARD_REG_SET (forbidden
, pseudo_forbidden_regs
[i
]);
3877 IOR_HARD_REG_SET (forbidden
, pseudo_previous_regs
[i
]);
3878 retry_global_alloc (i
, forbidden
);
3879 if (reg_renumber
[i
] >= 0)
3880 CLEAR_REGNO_REG_SET (spilled_pseudos
, i
);
3884 /* Fix up the register information in the insn chain.
3885 This involves deleting those of the spilled pseudos which did not get
3886 a new hard register home from the live_{before,after} sets. */
3887 for (chain
= reload_insn_chain
; chain
; chain
= chain
->next
)
3889 HARD_REG_SET used_by_pseudos
;
3890 HARD_REG_SET used_by_pseudos2
;
3892 AND_COMPL_REG_SET (chain
->live_before
, spilled_pseudos
);
3893 AND_COMPL_REG_SET (chain
->live_after
, spilled_pseudos
);
3895 /* Mark any unallocated hard regs as available for spills. That
3896 makes inheritance work somewhat better. */
3897 if (chain
->need_reload
)
3899 REG_SET_TO_HARD_REG_SET (used_by_pseudos
, chain
->live_before
);
3900 REG_SET_TO_HARD_REG_SET (used_by_pseudos2
, chain
->live_after
);
3901 IOR_HARD_REG_SET (used_by_pseudos
, used_by_pseudos2
);
3903 /* Save the old value for the sanity test below. */
3904 COPY_HARD_REG_SET (used_by_pseudos2
, chain
->used_spill_regs
);
3906 compute_use_by_pseudos (&used_by_pseudos
, chain
->live_before
);
3907 compute_use_by_pseudos (&used_by_pseudos
, chain
->live_after
);
3908 COMPL_HARD_REG_SET (chain
->used_spill_regs
, used_by_pseudos
);
3909 AND_HARD_REG_SET (chain
->used_spill_regs
, used_spill_regs
);
3911 /* Make sure we only enlarge the set. */
3912 GO_IF_HARD_REG_SUBSET (used_by_pseudos2
, chain
->used_spill_regs
, ok
);
3918 /* Let alter_reg modify the reg rtx's for the modified pseudos. */
3919 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
3921 int regno
= reg_renumber
[i
];
3922 if (reg_old_renumber
[i
] == regno
)
3925 alter_reg (i
, reg_old_renumber
[i
]);
3926 reg_old_renumber
[i
] = regno
;
3930 fprintf (dumpfile
, " Register %d now on stack.\n\n", i
);
3932 fprintf (dumpfile
, " Register %d now in %d.\n\n",
3933 i
, reg_renumber
[i
]);
3937 return something_changed
;
3940 /* Find all paradoxical subregs within X and update reg_max_ref_width.
3941 Also mark any hard registers used to store user variables as
3942 forbidden from being used for spill registers. */
3945 scan_paradoxical_subregs (x
)
3950 register enum rtx_code code
= GET_CODE (x
);
3956 if (SMALL_REGISTER_CLASSES
&& REGNO (x
) < FIRST_PSEUDO_REGISTER
3957 && REG_USERVAR_P (x
))
3958 SET_HARD_REG_BIT (bad_spill_regs_global
, REGNO (x
));
3974 if (GET_CODE (SUBREG_REG (x
)) == REG
3975 && GET_MODE_SIZE (GET_MODE (x
)) > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
3976 reg_max_ref_width
[REGNO (SUBREG_REG (x
))]
3977 = GET_MODE_SIZE (GET_MODE (x
));
3984 fmt
= GET_RTX_FORMAT (code
);
3985 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
3988 scan_paradoxical_subregs (XEXP (x
, i
));
3989 else if (fmt
[i
] == 'E')
3992 for (j
= XVECLEN (x
, i
) - 1; j
>=0; j
--)
3993 scan_paradoxical_subregs (XVECEXP (x
, i
, j
));
3999 hard_reg_use_compare (p1p
, p2p
)
4000 const GENERIC_PTR p1p
;
4001 const GENERIC_PTR p2p
;
4003 struct hard_reg_n_uses
*p1
= (struct hard_reg_n_uses
*)p1p
;
4004 struct hard_reg_n_uses
*p2
= (struct hard_reg_n_uses
*)p2p
;
4005 int bad1
= TEST_HARD_REG_BIT (bad_spill_regs
, p1
->regno
);
4006 int bad2
= TEST_HARD_REG_BIT (bad_spill_regs
, p2
->regno
);
4008 return p1
->regno
- p2
->regno
;
4013 if (p1
->uses
> p2
->uses
)
4015 if (p1
->uses
< p2
->uses
)
4017 /* If regs are equally good, sort by regno,
4018 so that the results of qsort leave nothing to chance. */
4019 return p1
->regno
- p2
->regno
;
4022 /* Used for communication between order_regs_for_reload and count_pseudo.
4023 Used to avoid counting one pseudo twice. */
4024 static regset pseudos_counted
;
4026 /* Update the costs in N_USES, considering that pseudo REG is live. */
4028 count_pseudo (n_uses
, reg
)
4029 struct hard_reg_n_uses
*n_uses
;
4032 int r
= reg_renumber
[reg
];
4035 if (REGNO_REG_SET_P (pseudos_counted
, reg
))
4037 SET_REGNO_REG_SET (pseudos_counted
, reg
);
4042 nregs
= HARD_REGNO_NREGS (r
, PSEUDO_REGNO_MODE (reg
));
4044 n_uses
[r
++].uses
+= REG_N_REFS (reg
);
4046 /* Choose the order to consider regs for use as reload registers
4047 based on how much trouble would be caused by spilling one.
4048 Store them in order of decreasing preference in potential_reload_regs. */
4051 order_regs_for_reload (chain
)
4052 struct insn_chain
*chain
;
4056 struct hard_reg_n_uses hard_reg_n_uses
[FIRST_PSEUDO_REGISTER
];
4058 pseudos_counted
= ALLOCA_REG_SET ();
4060 COPY_HARD_REG_SET (bad_spill_regs
, bad_spill_regs_global
);
4062 /* Count number of uses of each hard reg by pseudo regs allocated to it
4063 and then order them by decreasing use. */
4065 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
4069 hard_reg_n_uses
[i
].regno
= i
;
4070 hard_reg_n_uses
[i
].uses
= 0;
4072 /* Test the various reasons why we can't use a register for
4073 spilling in this insn. */
4075 || REGNO_REG_SET_P (chain
->live_before
, i
)
4076 || REGNO_REG_SET_P (chain
->live_after
, i
))
4078 SET_HARD_REG_BIT (bad_spill_regs
, i
);
4082 /* Now find out which pseudos are allocated to it, and update
4084 CLEAR_REG_SET (pseudos_counted
);
4086 EXECUTE_IF_SET_IN_REG_SET
4087 (chain
->live_before
, FIRST_PSEUDO_REGISTER
, j
,
4089 count_pseudo (hard_reg_n_uses
, j
);
4091 EXECUTE_IF_SET_IN_REG_SET
4092 (chain
->live_after
, FIRST_PSEUDO_REGISTER
, j
,
4094 count_pseudo (hard_reg_n_uses
, j
);
4098 FREE_REG_SET (pseudos_counted
);
4100 /* Prefer registers not so far used, for use in temporary loading.
4101 Among them, if REG_ALLOC_ORDER is defined, use that order.
4102 Otherwise, prefer registers not preserved by calls. */
4104 #ifdef REG_ALLOC_ORDER
4105 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
4107 int regno
= reg_alloc_order
[i
];
4109 if (hard_reg_n_uses
[regno
].uses
== 0
4110 && ! TEST_HARD_REG_BIT (bad_spill_regs
, regno
))
4111 potential_reload_regs
[o
++] = regno
;
4114 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
4116 if (hard_reg_n_uses
[i
].uses
== 0 && call_used_regs
[i
]
4117 && ! TEST_HARD_REG_BIT (bad_spill_regs
, i
))
4118 potential_reload_regs
[o
++] = i
;
4120 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
4122 if (hard_reg_n_uses
[i
].uses
== 0 && ! call_used_regs
[i
]
4123 && ! TEST_HARD_REG_BIT (bad_spill_regs
, i
))
4124 potential_reload_regs
[o
++] = i
;
4128 qsort (hard_reg_n_uses
, FIRST_PSEUDO_REGISTER
,
4129 sizeof hard_reg_n_uses
[0], hard_reg_use_compare
);
4131 /* Now add the regs that are already used,
4132 preferring those used less often. The fixed and otherwise forbidden
4133 registers will be at the end of this list. */
4135 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
4136 if (hard_reg_n_uses
[i
].uses
!= 0
4137 && ! TEST_HARD_REG_BIT (bad_spill_regs
, hard_reg_n_uses
[i
].regno
))
4138 potential_reload_regs
[o
++] = hard_reg_n_uses
[i
].regno
;
4139 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
4140 if (TEST_HARD_REG_BIT (bad_spill_regs
, hard_reg_n_uses
[i
].regno
))
4141 potential_reload_regs
[o
++] = hard_reg_n_uses
[i
].regno
;
4144 /* Reload pseudo-registers into hard regs around each insn as needed.
4145 Additional register load insns are output before the insn that needs it
4146 and perhaps store insns after insns that modify the reloaded pseudo reg.
4148 reg_last_reload_reg and reg_reloaded_contents keep track of
4149 which registers are already available in reload registers.
4150 We update these for the reloads that we perform,
4151 as the insns are scanned. */
4154 reload_as_needed (live_known
)
4157 struct insn_chain
*chain
;
4158 #if defined (AUTO_INC_DEC) || defined (INSN_CLOBBERS_REGNO_P)
4163 bzero ((char *) spill_reg_rtx
, sizeof spill_reg_rtx
);
4164 bzero ((char *) spill_reg_store
, sizeof spill_reg_store
);
4165 reg_last_reload_reg
= (rtx
*) alloca (max_regno
* sizeof (rtx
));
4166 bzero ((char *) reg_last_reload_reg
, max_regno
* sizeof (rtx
));
4167 reg_has_output_reload
= (char *) alloca (max_regno
);
4168 CLEAR_HARD_REG_SET (reg_reloaded_valid
);
4170 set_initial_elim_offsets ();
4172 for (chain
= reload_insn_chain
; chain
; chain
= chain
->next
)
4175 rtx insn
= chain
->insn
;
4176 rtx old_next
= NEXT_INSN (insn
);
4178 /* If we pass a label, copy the offsets from the label information
4179 into the current offsets of each elimination. */
4180 if (GET_CODE (insn
) == CODE_LABEL
)
4181 set_offsets_for_label (insn
);
4183 else if (GET_RTX_CLASS (GET_CODE (insn
)) == 'i')
4185 rtx oldpat
= PATTERN (insn
);
4187 /* If this is a USE and CLOBBER of a MEM, ensure that any
4188 references to eliminable registers have been removed. */
4190 if ((GET_CODE (PATTERN (insn
)) == USE
4191 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
4192 && GET_CODE (XEXP (PATTERN (insn
), 0)) == MEM
)
4193 XEXP (XEXP (PATTERN (insn
), 0), 0)
4194 = eliminate_regs (XEXP (XEXP (PATTERN (insn
), 0), 0),
4195 GET_MODE (XEXP (PATTERN (insn
), 0)),
4198 /* If we need to do register elimination processing, do so.
4199 This might delete the insn, in which case we are done. */
4200 if ((num_eliminable
|| num_eliminable_invariants
) && chain
->need_elim
)
4202 eliminate_regs_in_insn (insn
, 1);
4203 if (GET_CODE (insn
) == NOTE
)
4205 update_eliminable_offsets ();
4210 /* If need_elim is nonzero but need_reload is zero, one might think
4211 that we could simply set n_reloads to 0. However, find_reloads
4212 could have done some manipulation of the insn (such as swapping
4213 commutative operands), and these manipulations are lost during
4214 the first pass for every insn that needs register elimination.
4215 So the actions of find_reloads must be redone here. */
4217 if (! chain
->need_elim
&& ! chain
->need_reload
4218 && ! chain
->need_operand_change
)
4220 /* First find the pseudo regs that must be reloaded for this insn.
4221 This info is returned in the tables reload_... (see reload.h).
4222 Also modify the body of INSN by substituting RELOAD
4223 rtx's for those pseudo regs. */
4226 bzero (reg_has_output_reload
, max_regno
);
4227 CLEAR_HARD_REG_SET (reg_is_output_reload
);
4229 find_reloads (insn
, 1, spill_indirect_levels
, live_known
,
4233 if (num_eliminable
&& chain
->need_elim
)
4234 update_eliminable_offsets ();
4238 rtx next
= NEXT_INSN (insn
);
4241 prev
= PREV_INSN (insn
);
4243 /* Now compute which reload regs to reload them into. Perhaps
4244 reusing reload regs from previous insns, or else output
4245 load insns to reload them. Maybe output store insns too.
4246 Record the choices of reload reg in reload_reg_rtx. */
4247 choose_reload_regs (chain
);
4249 /* Merge any reloads that we didn't combine for fear of
4250 increasing the number of spill registers needed but now
4251 discover can be safely merged. */
4252 if (SMALL_REGISTER_CLASSES
)
4253 merge_assigned_reloads (insn
);
4255 /* Generate the insns to reload operands into or out of
4256 their reload regs. */
4257 emit_reload_insns (chain
);
4259 /* Substitute the chosen reload regs from reload_reg_rtx
4260 into the insn's body (or perhaps into the bodies of other
4261 load and store insn that we just made for reloading
4262 and that we moved the structure into). */
4265 /* If this was an ASM, make sure that all the reload insns
4266 we have generated are valid. If not, give an error
4269 if (asm_noperands (PATTERN (insn
)) >= 0)
4270 for (p
= NEXT_INSN (prev
); p
!= next
; p
= NEXT_INSN (p
))
4271 if (p
!= insn
&& GET_RTX_CLASS (GET_CODE (p
)) == 'i'
4272 && (recog_memoized (p
) < 0
4273 || (extract_insn (p
), ! constrain_operands (1))))
4275 error_for_asm (insn
,
4276 "`asm' operand requires impossible reload");
4278 NOTE_SOURCE_FILE (p
) = 0;
4279 NOTE_LINE_NUMBER (p
) = NOTE_INSN_DELETED
;
4282 /* Any previously reloaded spilled pseudo reg, stored in this insn,
4283 is no longer validly lying around to save a future reload.
4284 Note that this does not detect pseudos that were reloaded
4285 for this insn in order to be stored in
4286 (obeying register constraints). That is correct; such reload
4287 registers ARE still valid. */
4288 note_stores (oldpat
, forget_old_reloads_1
);
4290 /* There may have been CLOBBER insns placed after INSN. So scan
4291 between INSN and NEXT and use them to forget old reloads. */
4292 for (x
= NEXT_INSN (insn
); x
!= old_next
; x
= NEXT_INSN (x
))
4293 if (GET_CODE (x
) == INSN
&& GET_CODE (PATTERN (x
)) == CLOBBER
)
4294 note_stores (PATTERN (x
), forget_old_reloads_1
);
4297 /* Likewise for regs altered by auto-increment in this insn.
4298 REG_INC notes have been changed by reloading:
4299 find_reloads_address_1 records substitutions for them,
4300 which have been performed by subst_reloads above. */
4301 for (i
= n_reloads
- 1; i
>= 0; i
--)
4303 rtx in_reg
= reload_in_reg
[i
];
4306 enum rtx_code code
= GET_CODE (in_reg
);
4307 /* PRE_INC / PRE_DEC will have the reload register ending up
4308 with the same value as the stack slot, but that doesn't
4309 hold true for POST_INC / POST_DEC. Either we have to
4310 convert the memory access to a true POST_INC / POST_DEC,
4311 or we can't use the reload register for inheritance. */
4312 if ((code
== POST_INC
|| code
== POST_DEC
)
4313 && TEST_HARD_REG_BIT (reg_reloaded_valid
,
4314 REGNO (reload_reg_rtx
[i
]))
4315 /* Make sure it is the inc/dec pseudo, and not
4316 some other (e.g. output operand) pseudo. */
4317 && (reg_reloaded_contents
[REGNO (reload_reg_rtx
[i
])]
4318 == REGNO (XEXP (in_reg
, 0))))
4321 rtx reload_reg
= reload_reg_rtx
[i
];
4322 enum machine_mode mode
= GET_MODE (reload_reg
);
4326 for (p
= PREV_INSN (old_next
); p
!= prev
; p
= PREV_INSN (p
))
4328 /* We really want to ignore REG_INC notes here, so
4329 use PATTERN (p) as argument to reg_set_p . */
4330 if (reg_set_p (reload_reg
, PATTERN (p
)))
4332 n
= count_occurrences (PATTERN (p
), reload_reg
);
4337 n
= validate_replace_rtx (reload_reg
,
4338 gen_rtx (code
, mode
,
4342 /* We must also verify that the constraints
4343 are met after the replacement. */
4346 n
= constrain_operands (1);
4350 /* If the constraints were not met, then
4351 undo the replacement. */
4354 validate_replace_rtx (gen_rtx (code
, mode
,
4364 REG_NOTES (p
) = gen_rtx_EXPR_LIST (REG_INC
, reload_reg
,
4367 forget_old_reloads_1 (XEXP (in_reg
, 0), NULL_RTX
);
4371 #if 0 /* ??? Is this code obsolete now? Need to check carefully. */
4372 /* Likewise for regs altered by auto-increment in this insn.
4373 But note that the reg-notes are not changed by reloading:
4374 they still contain the pseudo-regs, not the spill regs. */
4375 for (x
= REG_NOTES (insn
); x
; x
= XEXP (x
, 1))
4376 if (REG_NOTE_KIND (x
) == REG_INC
)
4378 /* See if this pseudo reg was reloaded in this insn.
4379 If so, its last-reload info is still valid
4380 because it is based on this insn's reload. */
4381 for (i
= 0; i
< n_reloads
; i
++)
4382 if (reload_out
[i
] == XEXP (x
, 0))
4386 forget_old_reloads_1 (XEXP (x
, 0), NULL_RTX
);
4391 /* A reload reg's contents are unknown after a label. */
4392 if (GET_CODE (insn
) == CODE_LABEL
)
4393 CLEAR_HARD_REG_SET (reg_reloaded_valid
);
4395 /* Don't assume a reload reg is still good after a call insn
4396 if it is a call-used reg. */
4397 else if (GET_CODE (insn
) == CALL_INSN
)
4398 AND_COMPL_HARD_REG_SET(reg_reloaded_valid
, call_used_reg_set
);
4400 /* In case registers overlap, allow certain insns to invalidate
4401 particular hard registers. */
4403 #ifdef INSN_CLOBBERS_REGNO_P
4404 for (i
= 0 ; i
< FIRST_PSEUDO_REGISTER
; i
++)
4405 if (TEST_HARD_REG_BIT (reg_reloaded_valid
, i
)
4406 && INSN_CLOBBERS_REGNO_P (insn
, i
))
4407 CLEAR_HARD_REG_BIT (reg_reloaded_valid
, i
);
4416 /* Discard all record of any value reloaded from X,
4417 or reloaded in X from someplace else;
4418 unless X is an output reload reg of the current insn.
4420 X may be a hard reg (the reload reg)
4421 or it may be a pseudo reg that was reloaded from. */
4424 forget_old_reloads_1 (x
, ignored
)
4426 rtx ignored ATTRIBUTE_UNUSED
;
4432 /* note_stores does give us subregs of hard regs. */
4433 while (GET_CODE (x
) == SUBREG
)
4435 offset
+= SUBREG_WORD (x
);
4439 if (GET_CODE (x
) != REG
)
4442 regno
= REGNO (x
) + offset
;
4444 if (regno
>= FIRST_PSEUDO_REGISTER
)
4449 nr
= HARD_REGNO_NREGS (regno
, GET_MODE (x
));
4450 /* Storing into a spilled-reg invalidates its contents.
4451 This can happen if a block-local pseudo is allocated to that reg
4452 and it wasn't spilled because this block's total need is 0.
4453 Then some insn might have an optional reload and use this reg. */
4454 for (i
= 0; i
< nr
; i
++)
4455 /* But don't do this if the reg actually serves as an output
4456 reload reg in the current instruction. */
4458 || ! TEST_HARD_REG_BIT (reg_is_output_reload
, regno
+ i
))
4459 CLEAR_HARD_REG_BIT (reg_reloaded_valid
, regno
+ i
);
4462 /* Since value of X has changed,
4463 forget any value previously copied from it. */
4466 /* But don't forget a copy if this is the output reload
4467 that establishes the copy's validity. */
4468 if (n_reloads
== 0 || reg_has_output_reload
[regno
+ nr
] == 0)
4469 reg_last_reload_reg
[regno
+ nr
] = 0;
4472 /* For each reload, the mode of the reload register. */
4473 static enum machine_mode reload_mode
[MAX_RELOADS
];
4475 /* For each reload, the largest number of registers it will require. */
4476 static int reload_nregs
[MAX_RELOADS
];
4478 /* Comparison function for qsort to decide which of two reloads
4479 should be handled first. *P1 and *P2 are the reload numbers. */
4482 reload_reg_class_lower (r1p
, r2p
)
4483 const GENERIC_PTR r1p
;
4484 const GENERIC_PTR r2p
;
4486 register int r1
= *(short *)r1p
, r2
= *(short *)r2p
;
4489 /* Consider required reloads before optional ones. */
4490 t
= reload_optional
[r1
] - reload_optional
[r2
];
4494 /* Count all solitary classes before non-solitary ones. */
4495 t
= ((reg_class_size
[(int) reload_reg_class
[r2
]] == 1)
4496 - (reg_class_size
[(int) reload_reg_class
[r1
]] == 1));
4500 /* Aside from solitaires, consider all multi-reg groups first. */
4501 t
= reload_nregs
[r2
] - reload_nregs
[r1
];
4505 /* Consider reloads in order of increasing reg-class number. */
4506 t
= (int) reload_reg_class
[r1
] - (int) reload_reg_class
[r2
];
4510 /* If reloads are equally urgent, sort by reload number,
4511 so that the results of qsort leave nothing to chance. */
4515 /* The following HARD_REG_SETs indicate when each hard register is
4516 used for a reload of various parts of the current insn. */
4518 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
4519 static HARD_REG_SET reload_reg_used
;
4520 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
4521 static HARD_REG_SET reload_reg_used_in_input_addr
[MAX_RECOG_OPERANDS
];
4522 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */
4523 static HARD_REG_SET reload_reg_used_in_inpaddr_addr
[MAX_RECOG_OPERANDS
];
4524 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
4525 static HARD_REG_SET reload_reg_used_in_output_addr
[MAX_RECOG_OPERANDS
];
4526 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */
4527 static HARD_REG_SET reload_reg_used_in_outaddr_addr
[MAX_RECOG_OPERANDS
];
4528 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
4529 static HARD_REG_SET reload_reg_used_in_input
[MAX_RECOG_OPERANDS
];
4530 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
4531 static HARD_REG_SET reload_reg_used_in_output
[MAX_RECOG_OPERANDS
];
4532 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
4533 static HARD_REG_SET reload_reg_used_in_op_addr
;
4534 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */
4535 static HARD_REG_SET reload_reg_used_in_op_addr_reload
;
4536 /* If reg is in use for a RELOAD_FOR_INSN reload. */
4537 static HARD_REG_SET reload_reg_used_in_insn
;
4538 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
4539 static HARD_REG_SET reload_reg_used_in_other_addr
;
4541 /* If reg is in use as a reload reg for any sort of reload. */
4542 static HARD_REG_SET reload_reg_used_at_all
;
4544 /* If reg is use as an inherited reload. We just mark the first register
4546 static HARD_REG_SET reload_reg_used_for_inherit
;
4548 /* Records which hard regs are used in any way, either as explicit use or
4549 by being allocated to a pseudo during any point of the current insn. */
4550 static HARD_REG_SET reg_used_in_insn
;
4552 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
4553 TYPE. MODE is used to indicate how many consecutive regs are
4557 mark_reload_reg_in_use (regno
, opnum
, type
, mode
)
4560 enum reload_type type
;
4561 enum machine_mode mode
;
4563 int nregs
= HARD_REGNO_NREGS (regno
, mode
);
4566 for (i
= regno
; i
< nregs
+ regno
; i
++)
4571 SET_HARD_REG_BIT (reload_reg_used
, i
);
4574 case RELOAD_FOR_INPUT_ADDRESS
:
4575 SET_HARD_REG_BIT (reload_reg_used_in_input_addr
[opnum
], i
);
4578 case RELOAD_FOR_INPADDR_ADDRESS
:
4579 SET_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[opnum
], i
);
4582 case RELOAD_FOR_OUTPUT_ADDRESS
:
4583 SET_HARD_REG_BIT (reload_reg_used_in_output_addr
[opnum
], i
);
4586 case RELOAD_FOR_OUTADDR_ADDRESS
:
4587 SET_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[opnum
], i
);
4590 case RELOAD_FOR_OPERAND_ADDRESS
:
4591 SET_HARD_REG_BIT (reload_reg_used_in_op_addr
, i
);
4594 case RELOAD_FOR_OPADDR_ADDR
:
4595 SET_HARD_REG_BIT (reload_reg_used_in_op_addr_reload
, i
);
4598 case RELOAD_FOR_OTHER_ADDRESS
:
4599 SET_HARD_REG_BIT (reload_reg_used_in_other_addr
, i
);
4602 case RELOAD_FOR_INPUT
:
4603 SET_HARD_REG_BIT (reload_reg_used_in_input
[opnum
], i
);
4606 case RELOAD_FOR_OUTPUT
:
4607 SET_HARD_REG_BIT (reload_reg_used_in_output
[opnum
], i
);
4610 case RELOAD_FOR_INSN
:
4611 SET_HARD_REG_BIT (reload_reg_used_in_insn
, i
);
4615 SET_HARD_REG_BIT (reload_reg_used_at_all
, i
);
4619 /* Similarly, but show REGNO is no longer in use for a reload. */
4622 clear_reload_reg_in_use (regno
, opnum
, type
, mode
)
4625 enum reload_type type
;
4626 enum machine_mode mode
;
4628 int nregs
= HARD_REGNO_NREGS (regno
, mode
);
4629 int start_regno
, end_regno
;
4631 /* A complication is that for some reload types, inheritance might
4632 allow multiple reloads of the same types to share a reload register.
4633 We set check_opnum if we have to check only reloads with the same
4634 operand number, and check_any if we have to check all reloads. */
4635 int check_opnum
= 0;
4637 HARD_REG_SET
*used_in_set
;
4642 used_in_set
= &reload_reg_used
;
4645 case RELOAD_FOR_INPUT_ADDRESS
:
4646 used_in_set
= &reload_reg_used_in_input_addr
[opnum
];
4649 case RELOAD_FOR_INPADDR_ADDRESS
:
4651 used_in_set
= &reload_reg_used_in_inpaddr_addr
[opnum
];
4654 case RELOAD_FOR_OUTPUT_ADDRESS
:
4655 used_in_set
= &reload_reg_used_in_output_addr
[opnum
];
4658 case RELOAD_FOR_OUTADDR_ADDRESS
:
4660 used_in_set
= &reload_reg_used_in_outaddr_addr
[opnum
];
4663 case RELOAD_FOR_OPERAND_ADDRESS
:
4664 used_in_set
= &reload_reg_used_in_op_addr
;
4667 case RELOAD_FOR_OPADDR_ADDR
:
4669 used_in_set
= &reload_reg_used_in_op_addr_reload
;
4672 case RELOAD_FOR_OTHER_ADDRESS
:
4673 used_in_set
= &reload_reg_used_in_other_addr
;
4677 case RELOAD_FOR_INPUT
:
4678 used_in_set
= &reload_reg_used_in_input
[opnum
];
4681 case RELOAD_FOR_OUTPUT
:
4682 used_in_set
= &reload_reg_used_in_output
[opnum
];
4685 case RELOAD_FOR_INSN
:
4686 used_in_set
= &reload_reg_used_in_insn
;
4691 /* We resolve conflicts with remaining reloads of the same type by
4692 excluding the intervals of of reload registers by them from the
4693 interval of freed reload registers. Since we only keep track of
4694 one set of interval bounds, we might have to exclude somewhat
4695 more then what would be necessary if we used a HARD_REG_SET here.
4696 But this should only happen very infrequently, so there should
4697 be no reason to worry about it. */
4699 start_regno
= regno
;
4700 end_regno
= regno
+ nregs
;
4701 if (check_opnum
|| check_any
)
4703 for (i
= n_reloads
- 1; i
>= 0; i
--)
4705 if (reload_when_needed
[i
] == type
4706 && (check_any
|| reload_opnum
[i
] == opnum
)
4707 && reload_reg_rtx
[i
])
4709 int conflict_start
= true_regnum (reload_reg_rtx
[i
]);
4712 + HARD_REGNO_NREGS (conflict_start
, reload_mode
[i
]));
4714 /* If there is an overlap with the first to-be-freed register,
4715 adjust the interval start. */
4716 if (conflict_start
<= start_regno
&& conflict_end
> start_regno
)
4717 start_regno
= conflict_end
;
4718 /* Otherwise, if there is a conflict with one of the other
4719 to-be-freed registers, adjust the interval end. */
4720 if (conflict_start
> start_regno
&& conflict_start
< end_regno
)
4721 end_regno
= conflict_start
;
4725 for (i
= start_regno
; i
< end_regno
; i
++)
4726 CLEAR_HARD_REG_BIT (*used_in_set
, i
);
4729 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
4730 specified by OPNUM and TYPE. */
4733 reload_reg_free_p (regno
, opnum
, type
)
4736 enum reload_type type
;
4740 /* In use for a RELOAD_OTHER means it's not available for anything. */
4741 if (TEST_HARD_REG_BIT (reload_reg_used
, regno
))
4747 /* In use for anything means we can't use it for RELOAD_OTHER. */
4748 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr
, regno
)
4749 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
)
4750 || TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
))
4753 for (i
= 0; i
< reload_n_operands
; i
++)
4754 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
4755 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
)
4756 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
4757 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
)
4758 || TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
)
4759 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
4764 case RELOAD_FOR_INPUT
:
4765 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
4766 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
))
4769 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload
, regno
))
4772 /* If it is used for some other input, can't use it. */
4773 for (i
= 0; i
< reload_n_operands
; i
++)
4774 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
4777 /* If it is used in a later operand's address, can't use it. */
4778 for (i
= opnum
+ 1; i
< reload_n_operands
; i
++)
4779 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
4780 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
))
4785 case RELOAD_FOR_INPUT_ADDRESS
:
4786 /* Can't use a register if it is used for an input address for this
4787 operand or used as an input in an earlier one. */
4788 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[opnum
], regno
)
4789 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[opnum
], regno
))
4792 for (i
= 0; i
< opnum
; i
++)
4793 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
4798 case RELOAD_FOR_INPADDR_ADDRESS
:
4799 /* Can't use a register if it is used for an input address
4800 for this operand or used as an input in an earlier
4802 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[opnum
], regno
))
4805 for (i
= 0; i
< opnum
; i
++)
4806 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
4811 case RELOAD_FOR_OUTPUT_ADDRESS
:
4812 /* Can't use a register if it is used for an output address for this
4813 operand or used as an output in this or a later operand. */
4814 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[opnum
], regno
))
4817 for (i
= opnum
; i
< reload_n_operands
; i
++)
4818 if (TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
4823 case RELOAD_FOR_OUTADDR_ADDRESS
:
4824 /* Can't use a register if it is used for an output address
4825 for this operand or used as an output in this or a
4827 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[opnum
], regno
))
4830 for (i
= opnum
; i
< reload_n_operands
; i
++)
4831 if (TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
4836 case RELOAD_FOR_OPERAND_ADDRESS
:
4837 for (i
= 0; i
< reload_n_operands
; i
++)
4838 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
4841 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
4842 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
));
4844 case RELOAD_FOR_OPADDR_ADDR
:
4845 for (i
= 0; i
< reload_n_operands
; i
++)
4846 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
4849 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload
, regno
));
4851 case RELOAD_FOR_OUTPUT
:
4852 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
4853 outputs, or an operand address for this or an earlier output. */
4854 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
))
4857 for (i
= 0; i
< reload_n_operands
; i
++)
4858 if (TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
4861 for (i
= 0; i
<= opnum
; i
++)
4862 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
4863 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
))
4868 case RELOAD_FOR_INSN
:
4869 for (i
= 0; i
< reload_n_operands
; i
++)
4870 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
)
4871 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
4874 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
4875 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
));
4877 case RELOAD_FOR_OTHER_ADDRESS
:
4878 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr
, regno
);
4883 /* Return 1 if the value in reload reg REGNO, as used by a reload
4884 needed for the part of the insn specified by OPNUM and TYPE,
4885 is still available in REGNO at the end of the insn.
4887 We can assume that the reload reg was already tested for availability
4888 at the time it is needed, and we should not check this again,
4889 in case the reg has already been marked in use. */
4892 reload_reg_reaches_end_p (regno
, opnum
, type
)
4895 enum reload_type type
;
4902 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
4903 its value must reach the end. */
4906 /* If this use is for part of the insn,
4907 its value reaches if no subsequent part uses the same register.
4908 Just like the above function, don't try to do this with lots
4911 case RELOAD_FOR_OTHER_ADDRESS
:
4912 /* Here we check for everything else, since these don't conflict
4913 with anything else and everything comes later. */
4915 for (i
= 0; i
< reload_n_operands
; i
++)
4916 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
4917 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
)
4918 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
)
4919 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
4920 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
)
4921 || TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
4924 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
)
4925 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
4926 && ! TEST_HARD_REG_BIT (reload_reg_used
, regno
));
4928 case RELOAD_FOR_INPUT_ADDRESS
:
4929 case RELOAD_FOR_INPADDR_ADDRESS
:
4930 /* Similar, except that we check only for this and subsequent inputs
4931 and the address of only subsequent inputs and we do not need
4932 to check for RELOAD_OTHER objects since they are known not to
4935 for (i
= opnum
; i
< reload_n_operands
; i
++)
4936 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
4939 for (i
= opnum
+ 1; i
< reload_n_operands
; i
++)
4940 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
4941 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
))
4944 for (i
= 0; i
< reload_n_operands
; i
++)
4945 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
4946 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
)
4947 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
4950 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload
, regno
))
4953 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
)
4954 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
));
4956 case RELOAD_FOR_INPUT
:
4957 /* Similar to input address, except we start at the next operand for
4958 both input and input address and we do not check for
4959 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
4962 for (i
= opnum
+ 1; i
< reload_n_operands
; i
++)
4963 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
4964 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
)
4965 || TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
4968 /* ... fall through ... */
4970 case RELOAD_FOR_OPERAND_ADDRESS
:
4971 /* Check outputs and their addresses. */
4973 for (i
= 0; i
< reload_n_operands
; i
++)
4974 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
4975 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
)
4976 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
4981 case RELOAD_FOR_OPADDR_ADDR
:
4982 for (i
= 0; i
< reload_n_operands
; i
++)
4983 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
4984 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
)
4985 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
4988 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
)
4989 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
));
4991 case RELOAD_FOR_INSN
:
4992 /* These conflict with other outputs with RELOAD_OTHER. So
4993 we need only check for output addresses. */
4997 /* ... fall through ... */
4999 case RELOAD_FOR_OUTPUT
:
5000 case RELOAD_FOR_OUTPUT_ADDRESS
:
5001 case RELOAD_FOR_OUTADDR_ADDRESS
:
5002 /* We already know these can't conflict with a later output. So the
5003 only thing to check are later output addresses. */
5004 for (i
= opnum
+ 1; i
< reload_n_operands
; i
++)
5005 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
5006 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
))
5015 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
5018 This function uses the same algorithm as reload_reg_free_p above. */
5021 reloads_conflict (r1
, r2
)
5024 enum reload_type r1_type
= reload_when_needed
[r1
];
5025 enum reload_type r2_type
= reload_when_needed
[r2
];
5026 int r1_opnum
= reload_opnum
[r1
];
5027 int r2_opnum
= reload_opnum
[r2
];
5029 /* RELOAD_OTHER conflicts with everything. */
5030 if (r2_type
== RELOAD_OTHER
)
5033 /* Otherwise, check conflicts differently for each type. */
5037 case RELOAD_FOR_INPUT
:
5038 return (r2_type
== RELOAD_FOR_INSN
5039 || r2_type
== RELOAD_FOR_OPERAND_ADDRESS
5040 || r2_type
== RELOAD_FOR_OPADDR_ADDR
5041 || r2_type
== RELOAD_FOR_INPUT
5042 || ((r2_type
== RELOAD_FOR_INPUT_ADDRESS
5043 || r2_type
== RELOAD_FOR_INPADDR_ADDRESS
)
5044 && r2_opnum
> r1_opnum
));
5046 case RELOAD_FOR_INPUT_ADDRESS
:
5047 return ((r2_type
== RELOAD_FOR_INPUT_ADDRESS
&& r1_opnum
== r2_opnum
)
5048 || (r2_type
== RELOAD_FOR_INPUT
&& r2_opnum
< r1_opnum
));
5050 case RELOAD_FOR_INPADDR_ADDRESS
:
5051 return ((r2_type
== RELOAD_FOR_INPADDR_ADDRESS
&& r1_opnum
== r2_opnum
)
5052 || (r2_type
== RELOAD_FOR_INPUT
&& r2_opnum
< r1_opnum
));
5054 case RELOAD_FOR_OUTPUT_ADDRESS
:
5055 return ((r2_type
== RELOAD_FOR_OUTPUT_ADDRESS
&& r2_opnum
== r1_opnum
)
5056 || (r2_type
== RELOAD_FOR_OUTPUT
&& r2_opnum
>= r1_opnum
));
5058 case RELOAD_FOR_OUTADDR_ADDRESS
:
5059 return ((r2_type
== RELOAD_FOR_OUTADDR_ADDRESS
&& r2_opnum
== r1_opnum
)
5060 || (r2_type
== RELOAD_FOR_OUTPUT
&& r2_opnum
>= r1_opnum
));
5062 case RELOAD_FOR_OPERAND_ADDRESS
:
5063 return (r2_type
== RELOAD_FOR_INPUT
|| r2_type
== RELOAD_FOR_INSN
5064 || r2_type
== RELOAD_FOR_OPERAND_ADDRESS
);
5066 case RELOAD_FOR_OPADDR_ADDR
:
5067 return (r2_type
== RELOAD_FOR_INPUT
5068 || r2_type
== RELOAD_FOR_OPADDR_ADDR
);
5070 case RELOAD_FOR_OUTPUT
:
5071 return (r2_type
== RELOAD_FOR_INSN
|| r2_type
== RELOAD_FOR_OUTPUT
5072 || ((r2_type
== RELOAD_FOR_OUTPUT_ADDRESS
5073 || r2_type
== RELOAD_FOR_OUTADDR_ADDRESS
)
5074 && r2_opnum
>= r1_opnum
));
5076 case RELOAD_FOR_INSN
:
5077 return (r2_type
== RELOAD_FOR_INPUT
|| r2_type
== RELOAD_FOR_OUTPUT
5078 || r2_type
== RELOAD_FOR_INSN
5079 || r2_type
== RELOAD_FOR_OPERAND_ADDRESS
);
5081 case RELOAD_FOR_OTHER_ADDRESS
:
5082 return r2_type
== RELOAD_FOR_OTHER_ADDRESS
;
5092 /* Vector of reload-numbers showing the order in which the reloads should
5094 short reload_order
[MAX_RELOADS
];
5096 /* Indexed by reload number, 1 if incoming value
5097 inherited from previous insns. */
5098 char reload_inherited
[MAX_RELOADS
];
5100 /* For an inherited reload, this is the insn the reload was inherited from,
5101 if we know it. Otherwise, this is 0. */
5102 rtx reload_inheritance_insn
[MAX_RELOADS
];
5104 /* If non-zero, this is a place to get the value of the reload,
5105 rather than using reload_in. */
5106 rtx reload_override_in
[MAX_RELOADS
];
5108 /* For each reload, the hard register number of the register used,
5109 or -1 if we did not need a register for this reload. */
5110 int reload_spill_index
[MAX_RELOADS
];
5112 /* Return 1 if the value in reload reg REGNO, as used by a reload
5113 needed for the part of the insn specified by OPNUM and TYPE,
5114 may be used to load VALUE into it.
5116 Other read-only reloads with the same value do not conflict
5117 unless OUT is non-zero and these other reloads have to live while
5118 output reloads live.
5119 If OUT is CONST0_RTX, this is a special case: it means that the
5120 test should not be for using register REGNO as reload register, but
5121 for copying from register REGNO into the reload register.
5123 RELOADNUM is the number of the reload we want to load this value for;
5124 a reload does not conflict with itself.
5126 When IGNORE_ADDRESS_RELOADS is set, we can not have conflicts with
5127 reloads that load an address for the very reload we are considering.
5129 The caller has to make sure that there is no conflict with the return
5132 reload_reg_free_for_value_p (regno
, opnum
, type
, value
, out
, reloadnum
,
5133 ignore_address_reloads
)
5136 enum reload_type type
;
5139 int ignore_address_reloads
;
5145 if (out
== const0_rtx
)
5151 /* We use some pseudo 'time' value to check if the lifetimes of the
5152 new register use would overlap with the one of a previous reload
5153 that is not read-only or uses a different value.
5154 The 'time' used doesn't have to be linear in any shape or form, just
5156 Some reload types use different 'buckets' for each operand.
5157 So there are MAX_RECOG_OPERANDS different time values for each
5159 We compute TIME1 as the time when the register for the prospective
5160 new reload ceases to be live, and TIME2 for each existing
5161 reload as the time when that the reload register of that reload
5163 Where there is little to be gained by exact lifetime calculations,
5164 we just make conservative assumptions, i.e. a longer lifetime;
5165 this is done in the 'default:' cases. */
5168 case RELOAD_FOR_OTHER_ADDRESS
:
5172 time1
= copy
? 1 : MAX_RECOG_OPERANDS
* 5 + 5;
5174 /* For each input, we might have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
5175 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 ,
5176 respectively, to the time values for these, we get distinct time
5177 values. To get distinct time values for each operand, we have to
5178 multiply opnum by at least three. We round that up to four because
5179 multiply by four is often cheaper. */
5180 case RELOAD_FOR_INPADDR_ADDRESS
:
5181 time1
= opnum
* 4 + 2;
5183 case RELOAD_FOR_INPUT_ADDRESS
:
5184 time1
= opnum
* 4 + 3;
5186 case RELOAD_FOR_INPUT
:
5187 /* All RELOAD_FOR_INPUT reloads remain live till the instruction
5188 executes (inclusive). */
5189 time1
= copy
? opnum
* 4 + 4 : MAX_RECOG_OPERANDS
* 4 + 3;
5191 case RELOAD_FOR_OPADDR_ADDR
:
5193 <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
5194 time1
= MAX_RECOG_OPERANDS
* 4 + 1;
5196 case RELOAD_FOR_OPERAND_ADDRESS
:
5197 /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn
5199 time1
= copy
? MAX_RECOG_OPERANDS
* 4 + 2 : MAX_RECOG_OPERANDS
* 4 + 3;
5201 case RELOAD_FOR_OUTADDR_ADDRESS
:
5202 time1
= MAX_RECOG_OPERANDS
* 4 + 4 + opnum
;
5204 case RELOAD_FOR_OUTPUT_ADDRESS
:
5205 time1
= MAX_RECOG_OPERANDS
* 4 + 5 + opnum
;
5208 time1
= MAX_RECOG_OPERANDS
* 5 + 5;
5211 for (i
= 0; i
< n_reloads
; i
++)
5213 rtx reg
= reload_reg_rtx
[i
];
5214 if (reg
&& GET_CODE (reg
) == REG
5215 && ((unsigned) regno
- true_regnum (reg
)
5216 <= HARD_REGNO_NREGS (REGNO (reg
), GET_MODE (reg
)) - (unsigned)1)
5219 if (! reload_in
[i
] || ! rtx_equal_p (reload_in
[i
], value
)
5220 || reload_out
[i
] || out
)
5223 switch (reload_when_needed
[i
])
5225 case RELOAD_FOR_OTHER_ADDRESS
:
5228 case RELOAD_FOR_INPADDR_ADDRESS
:
5229 /* find_reloads makes sure that a
5230 RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used
5231 by at most one - the first -
5232 RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the
5233 address reload is inherited, the address address reload
5234 goes away, so we can ignore this conflict. */
5235 if (type
== RELOAD_FOR_INPUT_ADDRESS
&& reloadnum
== i
+ 1
5236 && ignore_address_reloads
5237 /* Unless the RELOAD_FOR_INPUT is an auto_inc expression.
5238 Then the address address is still needed to store
5239 back the new address. */
5240 && ! reload_out
[reloadnum
])
5242 /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its
5243 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS
5245 if (type
== RELOAD_FOR_INPUT
&& opnum
== reload_opnum
[i
]
5246 && ignore_address_reloads
5247 /* Unless we are reloading an auto_inc expression. */
5248 && ! reload_out
[reloadnum
])
5250 time2
= reload_opnum
[i
] * 4 + 2;
5252 case RELOAD_FOR_INPUT_ADDRESS
:
5253 if (type
== RELOAD_FOR_INPUT
&& opnum
== reload_opnum
[i
]
5254 && ignore_address_reloads
5255 && ! reload_out
[reloadnum
])
5257 time2
= reload_opnum
[i
] * 4 + 3;
5259 case RELOAD_FOR_INPUT
:
5260 time2
= reload_opnum
[i
] * 4 + 4;
5262 /* reload_opnum[i] * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4
5263 == MAX_RECOG_OPERAND * 4 */
5264 case RELOAD_FOR_OPADDR_ADDR
:
5265 if (type
== RELOAD_FOR_OPERAND_ADDRESS
&& reloadnum
== i
+ 1
5266 && ignore_address_reloads
5267 && ! reload_out
[reloadnum
])
5269 time2
= MAX_RECOG_OPERANDS
* 4 + 1;
5271 case RELOAD_FOR_OPERAND_ADDRESS
:
5272 time2
= MAX_RECOG_OPERANDS
* 4 + 2;
5274 case RELOAD_FOR_INSN
:
5275 time2
= MAX_RECOG_OPERANDS
* 4 + 3;
5277 case RELOAD_FOR_OUTPUT
:
5278 /* All RELOAD_FOR_OUTPUT reloads become live just after the
5279 instruction is executed. */
5280 time2
= MAX_RECOG_OPERANDS
* 4 + 4;
5282 /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with
5283 the RELOAD_FOR_OUTPUT reloads, so assign it the same time
5285 case RELOAD_FOR_OUTADDR_ADDRESS
:
5286 if (type
== RELOAD_FOR_OUTPUT_ADDRESS
&& reloadnum
== i
+ 1
5287 && ignore_address_reloads
5288 && ! reload_out
[reloadnum
])
5290 time2
= MAX_RECOG_OPERANDS
* 4 + 4 + reload_opnum
[i
];
5292 case RELOAD_FOR_OUTPUT_ADDRESS
:
5293 time2
= MAX_RECOG_OPERANDS
* 4 + 5 + reload_opnum
[i
];
5296 /* If there is no conflict in the input part, handle this
5297 like an output reload. */
5298 if (! reload_in
[i
] || rtx_equal_p (reload_in
[i
], value
))
5300 time2
= MAX_RECOG_OPERANDS
* 4 + 4;
5304 /* RELOAD_OTHER might be live beyond instruction execution,
5305 but this is not obvious when we set time2 = 1. So check
5306 here if there might be a problem with the new reload
5307 clobbering the register used by the RELOAD_OTHER. */
5315 && (! reload_in
[i
] || reload_out
[i
]
5316 || ! rtx_equal_p (reload_in
[i
], value
)))
5317 || (out
&& reload_out_reg
[reloadnum
]
5318 && time2
>= MAX_RECOG_OPERANDS
* 4 + 3))
5326 /* Find a spill register to use as a reload register for reload R.
5327 LAST_RELOAD is non-zero if this is the last reload for the insn being
5330 Set reload_reg_rtx[R] to the register allocated.
5332 If NOERROR is nonzero, we return 1 if successful,
5333 or 0 if we couldn't find a spill reg and we didn't change anything. */
5336 allocate_reload_reg (chain
, r
, last_reload
, noerror
)
5337 struct insn_chain
*chain
;
5342 rtx insn
= chain
->insn
;
5343 int i
, pass
, count
, regno
;
5346 /* If we put this reload ahead, thinking it is a group,
5347 then insist on finding a group. Otherwise we can grab a
5348 reg that some other reload needs.
5349 (That can happen when we have a 68000 DATA_OR_FP_REG
5350 which is a group of data regs or one fp reg.)
5351 We need not be so restrictive if there are no more reloads
5354 ??? Really it would be nicer to have smarter handling
5355 for that kind of reg class, where a problem like this is normal.
5356 Perhaps those classes should be avoided for reloading
5357 by use of more alternatives. */
5359 int force_group
= reload_nregs
[r
] > 1 && ! last_reload
;
5361 /* If we want a single register and haven't yet found one,
5362 take any reg in the right class and not in use.
5363 If we want a consecutive group, here is where we look for it.
5365 We use two passes so we can first look for reload regs to
5366 reuse, which are already in use for other reloads in this insn,
5367 and only then use additional registers.
5368 I think that maximizing reuse is needed to make sure we don't
5369 run out of reload regs. Suppose we have three reloads, and
5370 reloads A and B can share regs. These need two regs.
5371 Suppose A and B are given different regs.
5372 That leaves none for C. */
5373 for (pass
= 0; pass
< 2; pass
++)
5375 /* I is the index in spill_regs.
5376 We advance it round-robin between insns to use all spill regs
5377 equally, so that inherited reloads have a chance
5378 of leapfrogging each other. Don't do this, however, when we have
5379 group needs and failure would be fatal; if we only have a relatively
5380 small number of spill registers, and more than one of them has
5381 group needs, then by starting in the middle, we may end up
5382 allocating the first one in such a way that we are not left with
5383 sufficient groups to handle the rest. */
5385 if (noerror
|| ! force_group
)
5390 for (count
= 0; count
< n_spills
; count
++)
5392 int class = (int) reload_reg_class
[r
];
5398 regnum
= spill_regs
[i
];
5400 if ((reload_reg_free_p (regnum
, reload_opnum
[r
],
5401 reload_when_needed
[r
])
5403 /* We check reload_reg_used to make sure we
5404 don't clobber the return register. */
5405 && ! TEST_HARD_REG_BIT (reload_reg_used
, regnum
)
5406 && reload_reg_free_for_value_p (regnum
,
5408 reload_when_needed
[r
],
5410 reload_out
[r
], r
, 1)))
5411 && TEST_HARD_REG_BIT (reg_class_contents
[class], regnum
)
5412 && HARD_REGNO_MODE_OK (regnum
, reload_mode
[r
])
5413 /* Look first for regs to share, then for unshared. But
5414 don't share regs used for inherited reloads; they are
5415 the ones we want to preserve. */
5417 || (TEST_HARD_REG_BIT (reload_reg_used_at_all
,
5419 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit
,
5422 int nr
= HARD_REGNO_NREGS (regnum
, reload_mode
[r
]);
5423 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
5424 (on 68000) got us two FP regs. If NR is 1,
5425 we would reject both of them. */
5427 nr
= CLASS_MAX_NREGS (reload_reg_class
[r
], reload_mode
[r
]);
5428 /* If we need only one reg, we have already won. */
5431 /* But reject a single reg if we demand a group. */
5436 /* Otherwise check that as many consecutive regs as we need
5438 Also, don't use for a group registers that are
5439 needed for nongroups. */
5440 if (! TEST_HARD_REG_BIT (chain
->counted_for_nongroups
, regnum
))
5443 regno
= regnum
+ nr
- 1;
5444 if (!(TEST_HARD_REG_BIT (reg_class_contents
[class], regno
)
5445 && spill_reg_order
[regno
] >= 0
5446 && reload_reg_free_p (regno
, reload_opnum
[r
],
5447 reload_when_needed
[r
])
5448 && ! TEST_HARD_REG_BIT (chain
->counted_for_nongroups
,
5458 /* If we found something on pass 1, omit pass 2. */
5459 if (count
< n_spills
)
5463 /* We should have found a spill register by now. */
5464 if (count
== n_spills
)
5471 /* I is the index in SPILL_REG_RTX of the reload register we are to
5472 allocate. Get an rtx for it and find its register number. */
5474 new = spill_reg_rtx
[i
];
5476 if (new == 0 || GET_MODE (new) != reload_mode
[r
])
5477 spill_reg_rtx
[i
] = new
5478 = gen_rtx_REG (reload_mode
[r
], spill_regs
[i
]);
5480 regno
= true_regnum (new);
5482 /* Detect when the reload reg can't hold the reload mode.
5483 This used to be one `if', but Sequent compiler can't handle that. */
5484 if (HARD_REGNO_MODE_OK (regno
, reload_mode
[r
]))
5486 enum machine_mode test_mode
= VOIDmode
;
5488 test_mode
= GET_MODE (reload_in
[r
]);
5489 /* If reload_in[r] has VOIDmode, it means we will load it
5490 in whatever mode the reload reg has: to wit, reload_mode[r].
5491 We have already tested that for validity. */
5492 /* Aside from that, we need to test that the expressions
5493 to reload from or into have modes which are valid for this
5494 reload register. Otherwise the reload insns would be invalid. */
5495 if (! (reload_in
[r
] != 0 && test_mode
!= VOIDmode
5496 && ! HARD_REGNO_MODE_OK (regno
, test_mode
)))
5497 if (! (reload_out
[r
] != 0
5498 && ! HARD_REGNO_MODE_OK (regno
, GET_MODE (reload_out
[r
]))))
5500 /* The reg is OK. */
5503 /* Mark as in use for this insn the reload regs we use
5505 mark_reload_reg_in_use (spill_regs
[i
], reload_opnum
[r
],
5506 reload_when_needed
[r
], reload_mode
[r
]);
5508 reload_reg_rtx
[r
] = new;
5509 reload_spill_index
[r
] = spill_regs
[i
];
5514 /* The reg is not OK. */
5519 if (asm_noperands (PATTERN (insn
)) < 0)
5520 /* It's the compiler's fault. */
5521 fatal_insn ("Could not find a spill register", insn
);
5523 /* It's the user's fault; the operand's mode and constraint
5524 don't match. Disable this reload so we don't crash in final. */
5525 error_for_asm (insn
,
5526 "`asm' operand constraint incompatible with operand size");
5529 reload_reg_rtx
[r
] = 0;
5530 reload_optional
[r
] = 1;
5531 reload_secondary_p
[r
] = 1;
5536 /* Assign hard reg targets for the pseudo-registers we must reload
5537 into hard regs for this insn.
5538 Also output the instructions to copy them in and out of the hard regs.
5540 For machines with register classes, we are responsible for
5541 finding a reload reg in the proper class. */
5544 choose_reload_regs (chain
)
5545 struct insn_chain
*chain
;
5547 rtx insn
= chain
->insn
;
5549 int max_group_size
= 1;
5550 enum reg_class group_class
= NO_REGS
;
5554 rtx save_reload_reg_rtx
[MAX_RELOADS
];
5555 char save_reload_inherited
[MAX_RELOADS
];
5556 rtx save_reload_inheritance_insn
[MAX_RELOADS
];
5557 rtx save_reload_override_in
[MAX_RELOADS
];
5558 int save_reload_spill_index
[MAX_RELOADS
];
5559 HARD_REG_SET save_reload_reg_used
;
5560 HARD_REG_SET save_reload_reg_used_in_input_addr
[MAX_RECOG_OPERANDS
];
5561 HARD_REG_SET save_reload_reg_used_in_inpaddr_addr
[MAX_RECOG_OPERANDS
];
5562 HARD_REG_SET save_reload_reg_used_in_output_addr
[MAX_RECOG_OPERANDS
];
5563 HARD_REG_SET save_reload_reg_used_in_outaddr_addr
[MAX_RECOG_OPERANDS
];
5564 HARD_REG_SET save_reload_reg_used_in_input
[MAX_RECOG_OPERANDS
];
5565 HARD_REG_SET save_reload_reg_used_in_output
[MAX_RECOG_OPERANDS
];
5566 HARD_REG_SET save_reload_reg_used_in_op_addr
;
5567 HARD_REG_SET save_reload_reg_used_in_op_addr_reload
;
5568 HARD_REG_SET save_reload_reg_used_in_insn
;
5569 HARD_REG_SET save_reload_reg_used_in_other_addr
;
5570 HARD_REG_SET save_reload_reg_used_at_all
;
5572 bzero (reload_inherited
, MAX_RELOADS
);
5573 bzero ((char *) reload_inheritance_insn
, MAX_RELOADS
* sizeof (rtx
));
5574 bzero ((char *) reload_override_in
, MAX_RELOADS
* sizeof (rtx
));
5576 CLEAR_HARD_REG_SET (reload_reg_used
);
5577 CLEAR_HARD_REG_SET (reload_reg_used_at_all
);
5578 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr
);
5579 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload
);
5580 CLEAR_HARD_REG_SET (reload_reg_used_in_insn
);
5581 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr
);
5583 CLEAR_HARD_REG_SET (reg_used_in_insn
);
5586 REG_SET_TO_HARD_REG_SET (tmp
, chain
->live_before
);
5587 IOR_HARD_REG_SET (reg_used_in_insn
, tmp
);
5588 REG_SET_TO_HARD_REG_SET (tmp
, chain
->live_after
);
5589 IOR_HARD_REG_SET (reg_used_in_insn
, tmp
);
5590 compute_use_by_pseudos (®_used_in_insn
, chain
->live_before
);
5591 compute_use_by_pseudos (®_used_in_insn
, chain
->live_after
);
5593 for (i
= 0; i
< reload_n_operands
; i
++)
5595 CLEAR_HARD_REG_SET (reload_reg_used_in_output
[i
]);
5596 CLEAR_HARD_REG_SET (reload_reg_used_in_input
[i
]);
5597 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr
[i
]);
5598 CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr
[i
]);
5599 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr
[i
]);
5600 CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr
[i
]);
5603 IOR_COMPL_HARD_REG_SET (reload_reg_used
, chain
->used_spill_regs
);
5605 #if 0 /* Not needed, now that we can always retry without inheritance. */
5606 /* See if we have more mandatory reloads than spill regs.
5607 If so, then we cannot risk optimizations that could prevent
5608 reloads from sharing one spill register.
5610 Since we will try finding a better register than reload_reg_rtx
5611 unless it is equal to reload_in or reload_out, count such reloads. */
5615 for (j
= 0; j
< n_reloads
; j
++)
5616 if (! reload_optional
[j
]
5617 && (reload_in
[j
] != 0 || reload_out
[j
] != 0 || reload_secondary_p
[j
])
5618 && (reload_reg_rtx
[j
] == 0
5619 || (! rtx_equal_p (reload_reg_rtx
[j
], reload_in
[j
])
5620 && ! rtx_equal_p (reload_reg_rtx
[j
], reload_out
[j
]))))
5627 /* In order to be certain of getting the registers we need,
5628 we must sort the reloads into order of increasing register class.
5629 Then our grabbing of reload registers will parallel the process
5630 that provided the reload registers.
5632 Also note whether any of the reloads wants a consecutive group of regs.
5633 If so, record the maximum size of the group desired and what
5634 register class contains all the groups needed by this insn. */
5636 for (j
= 0; j
< n_reloads
; j
++)
5638 reload_order
[j
] = j
;
5639 reload_spill_index
[j
] = -1;
5642 = (reload_inmode
[j
] == VOIDmode
5643 || (GET_MODE_SIZE (reload_outmode
[j
])
5644 > GET_MODE_SIZE (reload_inmode
[j
])))
5645 ? reload_outmode
[j
] : reload_inmode
[j
];
5647 reload_nregs
[j
] = CLASS_MAX_NREGS (reload_reg_class
[j
], reload_mode
[j
]);
5649 if (reload_nregs
[j
] > 1)
5651 max_group_size
= MAX (reload_nregs
[j
], max_group_size
);
5652 group_class
= reg_class_superunion
[(int)reload_reg_class
[j
]][(int)group_class
];
5655 /* If we have already decided to use a certain register,
5656 don't use it in another way. */
5657 if (reload_reg_rtx
[j
])
5658 mark_reload_reg_in_use (REGNO (reload_reg_rtx
[j
]), reload_opnum
[j
],
5659 reload_when_needed
[j
], reload_mode
[j
]);
5663 qsort (reload_order
, n_reloads
, sizeof (short), reload_reg_class_lower
);
5665 bcopy ((char *) reload_reg_rtx
, (char *) save_reload_reg_rtx
,
5666 sizeof reload_reg_rtx
);
5667 bcopy (reload_inherited
, save_reload_inherited
, sizeof reload_inherited
);
5668 bcopy ((char *) reload_inheritance_insn
,
5669 (char *) save_reload_inheritance_insn
,
5670 sizeof reload_inheritance_insn
);
5671 bcopy ((char *) reload_override_in
, (char *) save_reload_override_in
,
5672 sizeof reload_override_in
);
5673 bcopy ((char *) reload_spill_index
, (char *) save_reload_spill_index
,
5674 sizeof reload_spill_index
);
5675 COPY_HARD_REG_SET (save_reload_reg_used
, reload_reg_used
);
5676 COPY_HARD_REG_SET (save_reload_reg_used_at_all
, reload_reg_used_at_all
);
5677 COPY_HARD_REG_SET (save_reload_reg_used_in_op_addr
,
5678 reload_reg_used_in_op_addr
);
5680 COPY_HARD_REG_SET (save_reload_reg_used_in_op_addr_reload
,
5681 reload_reg_used_in_op_addr_reload
);
5683 COPY_HARD_REG_SET (save_reload_reg_used_in_insn
,
5684 reload_reg_used_in_insn
);
5685 COPY_HARD_REG_SET (save_reload_reg_used_in_other_addr
,
5686 reload_reg_used_in_other_addr
);
5688 for (i
= 0; i
< reload_n_operands
; i
++)
5690 COPY_HARD_REG_SET (save_reload_reg_used_in_output
[i
],
5691 reload_reg_used_in_output
[i
]);
5692 COPY_HARD_REG_SET (save_reload_reg_used_in_input
[i
],
5693 reload_reg_used_in_input
[i
]);
5694 COPY_HARD_REG_SET (save_reload_reg_used_in_input_addr
[i
],
5695 reload_reg_used_in_input_addr
[i
]);
5696 COPY_HARD_REG_SET (save_reload_reg_used_in_inpaddr_addr
[i
],
5697 reload_reg_used_in_inpaddr_addr
[i
]);
5698 COPY_HARD_REG_SET (save_reload_reg_used_in_output_addr
[i
],
5699 reload_reg_used_in_output_addr
[i
]);
5700 COPY_HARD_REG_SET (save_reload_reg_used_in_outaddr_addr
[i
],
5701 reload_reg_used_in_outaddr_addr
[i
]);
5704 /* If -O, try first with inheritance, then turning it off.
5705 If not -O, don't do inheritance.
5706 Using inheritance when not optimizing leads to paradoxes
5707 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
5708 because one side of the comparison might be inherited. */
5710 for (inheritance
= optimize
> 0; inheritance
>= 0; inheritance
--)
5712 /* Process the reloads in order of preference just found.
5713 Beyond this point, subregs can be found in reload_reg_rtx.
5715 This used to look for an existing reloaded home for all
5716 of the reloads, and only then perform any new reloads.
5717 But that could lose if the reloads were done out of reg-class order
5718 because a later reload with a looser constraint might have an old
5719 home in a register needed by an earlier reload with a tighter constraint.
5721 To solve this, we make two passes over the reloads, in the order
5722 described above. In the first pass we try to inherit a reload
5723 from a previous insn. If there is a later reload that needs a
5724 class that is a proper subset of the class being processed, we must
5725 also allocate a spill register during the first pass.
5727 Then make a second pass over the reloads to allocate any reloads
5728 that haven't been given registers yet. */
5730 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit
);
5732 for (j
= 0; j
< n_reloads
; j
++)
5734 register int r
= reload_order
[j
];
5736 /* Ignore reloads that got marked inoperative. */
5737 if (reload_out
[r
] == 0 && reload_in
[r
] == 0
5738 && ! reload_secondary_p
[r
])
5741 /* If find_reloads chose to use reload_in or reload_out as a reload
5742 register, we don't need to chose one. Otherwise, try even if it
5743 found one since we might save an insn if we find the value lying
5745 Try also when reload_in is a pseudo without a hard reg. */
5746 if (reload_in
[r
] != 0 && reload_reg_rtx
[r
] != 0
5747 && (rtx_equal_p (reload_in
[r
], reload_reg_rtx
[r
])
5748 || (rtx_equal_p (reload_out
[r
], reload_reg_rtx
[r
])
5749 && GET_CODE (reload_in
[r
]) != MEM
5750 && true_regnum (reload_in
[r
]) < FIRST_PSEUDO_REGISTER
)))
5753 #if 0 /* No longer needed for correct operation.
5754 It might give better code, or might not; worth an experiment? */
5755 /* If this is an optional reload, we can't inherit from earlier insns
5756 until we are sure that any non-optional reloads have been allocated.
5757 The following code takes advantage of the fact that optional reloads
5758 are at the end of reload_order. */
5759 if (reload_optional
[r
] != 0)
5760 for (i
= 0; i
< j
; i
++)
5761 if ((reload_out
[reload_order
[i
]] != 0
5762 || reload_in
[reload_order
[i
]] != 0
5763 || reload_secondary_p
[reload_order
[i
]])
5764 && ! reload_optional
[reload_order
[i
]]
5765 && reload_reg_rtx
[reload_order
[i
]] == 0)
5766 allocate_reload_reg (chain
, reload_order
[i
], 0, inheritance
);
5769 /* First see if this pseudo is already available as reloaded
5770 for a previous insn. We cannot try to inherit for reloads
5771 that are smaller than the maximum number of registers needed
5772 for groups unless the register we would allocate cannot be used
5775 We could check here to see if this is a secondary reload for
5776 an object that is already in a register of the desired class.
5777 This would avoid the need for the secondary reload register.
5778 But this is complex because we can't easily determine what
5779 objects might want to be loaded via this reload. So let a
5780 register be allocated here. In `emit_reload_insns' we suppress
5781 one of the loads in the case described above. */
5786 register int regno
= -1;
5787 enum machine_mode mode
;
5789 if (reload_in
[r
] == 0)
5791 else if (GET_CODE (reload_in
[r
]) == REG
)
5793 regno
= REGNO (reload_in
[r
]);
5794 mode
= GET_MODE (reload_in
[r
]);
5796 else if (GET_CODE (reload_in_reg
[r
]) == REG
)
5798 regno
= REGNO (reload_in_reg
[r
]);
5799 mode
= GET_MODE (reload_in_reg
[r
]);
5801 else if (GET_CODE (reload_in_reg
[r
]) == SUBREG
5802 && GET_CODE (SUBREG_REG (reload_in_reg
[r
])) == REG
)
5804 word
= SUBREG_WORD (reload_in_reg
[r
]);
5805 regno
= REGNO (SUBREG_REG (reload_in_reg
[r
]));
5806 if (regno
< FIRST_PSEUDO_REGISTER
)
5808 mode
= GET_MODE (reload_in_reg
[r
]);
5811 else if ((GET_CODE (reload_in_reg
[r
]) == PRE_INC
5812 || GET_CODE (reload_in_reg
[r
]) == PRE_DEC
5813 || GET_CODE (reload_in_reg
[r
]) == POST_INC
5814 || GET_CODE (reload_in_reg
[r
]) == POST_DEC
)
5815 && GET_CODE (XEXP (reload_in_reg
[r
], 0)) == REG
)
5817 regno
= REGNO (XEXP (reload_in_reg
[r
], 0));
5818 mode
= GET_MODE (XEXP (reload_in_reg
[r
], 0));
5819 reload_out
[r
] = reload_in
[r
];
5823 /* This won't work, since REGNO can be a pseudo reg number.
5824 Also, it takes much more hair to keep track of all the things
5825 that can invalidate an inherited reload of part of a pseudoreg. */
5826 else if (GET_CODE (reload_in
[r
]) == SUBREG
5827 && GET_CODE (SUBREG_REG (reload_in
[r
])) == REG
)
5828 regno
= REGNO (SUBREG_REG (reload_in
[r
])) + SUBREG_WORD (reload_in
[r
]);
5831 if (regno
>= 0 && reg_last_reload_reg
[regno
] != 0)
5833 enum reg_class
class = reload_reg_class
[r
], last_class
;
5834 rtx last_reg
= reg_last_reload_reg
[regno
];
5836 i
= REGNO (last_reg
) + word
;
5837 last_class
= REGNO_REG_CLASS (i
);
5838 if ((GET_MODE_SIZE (GET_MODE (last_reg
))
5839 >= GET_MODE_SIZE (mode
) + word
* UNITS_PER_WORD
)
5840 && reg_reloaded_contents
[i
] == regno
5841 && TEST_HARD_REG_BIT (reg_reloaded_valid
, i
)
5842 && HARD_REGNO_MODE_OK (i
, reload_mode
[r
])
5843 && (TEST_HARD_REG_BIT (reg_class_contents
[(int) class], i
)
5844 /* Even if we can't use this register as a reload
5845 register, we might use it for reload_override_in,
5846 if copying it to the desired class is cheap
5848 || ((REGISTER_MOVE_COST (last_class
, class)
5849 < MEMORY_MOVE_COST (mode
, class, 1))
5850 #ifdef SECONDARY_INPUT_RELOAD_CLASS
5851 && (SECONDARY_INPUT_RELOAD_CLASS (class, mode
,
5855 #ifdef SECONDARY_MEMORY_NEEDED
5856 && ! SECONDARY_MEMORY_NEEDED (last_class
, class,
5861 && (reload_nregs
[r
] == max_group_size
5862 || ! TEST_HARD_REG_BIT (reg_class_contents
[(int) group_class
],
5864 && reload_reg_free_for_value_p (i
, reload_opnum
[r
],
5865 reload_when_needed
[r
],
5869 /* If a group is needed, verify that all the subsequent
5870 registers still have their values intact. */
5872 = HARD_REGNO_NREGS (i
, reload_mode
[r
]);
5875 for (k
= 1; k
< nr
; k
++)
5876 if (reg_reloaded_contents
[i
+ k
] != regno
5877 || ! TEST_HARD_REG_BIT (reg_reloaded_valid
, i
+ k
))
5884 last_reg
= (GET_MODE (last_reg
) == mode
5885 ? last_reg
: gen_rtx_REG (mode
, i
));
5887 /* We found a register that contains the
5888 value we need. If this register is the
5889 same as an `earlyclobber' operand of the
5890 current insn, just mark it as a place to
5891 reload from since we can't use it as the
5892 reload register itself. */
5894 for (i1
= 0; i1
< n_earlyclobbers
; i1
++)
5895 if (reg_overlap_mentioned_for_reload_p
5896 (reg_last_reload_reg
[regno
],
5897 reload_earlyclobbers
[i1
]))
5900 if (i1
!= n_earlyclobbers
5901 || ! (reload_reg_free_for_value_p
5902 (i
, reload_opnum
[r
], reload_when_needed
[r
],
5903 reload_in
[r
], reload_out
[r
], r
, 1))
5904 /* Don't use it if we'd clobber a pseudo reg. */
5905 || (TEST_HARD_REG_BIT (reg_used_in_insn
, i
)
5907 && ! TEST_HARD_REG_BIT (reg_reloaded_dead
, i
))
5908 /* Don't really use the inherited spill reg
5909 if we need it wider than we've got it. */
5910 || (GET_MODE_SIZE (reload_mode
[r
])
5911 > GET_MODE_SIZE (mode
))
5912 || ! TEST_HARD_REG_BIT (reg_class_contents
[(int) reload_reg_class
[r
]],
5915 /* If find_reloads chose reload_out as reload
5916 register, stay with it - that leaves the
5917 inherited register for subsequent reloads. */
5918 || (reload_out
[r
] && reload_reg_rtx
[r
]
5919 && rtx_equal_p (reload_out
[r
],
5920 reload_reg_rtx
[r
])))
5922 reload_override_in
[r
] = last_reg
;
5923 reload_inheritance_insn
[r
]
5924 = reg_reloaded_insn
[i
];
5929 /* We can use this as a reload reg. */
5930 /* Mark the register as in use for this part of
5932 mark_reload_reg_in_use (i
,
5934 reload_when_needed
[r
],
5936 reload_reg_rtx
[r
] = last_reg
;
5937 reload_inherited
[r
] = 1;
5938 reload_inheritance_insn
[r
]
5939 = reg_reloaded_insn
[i
];
5940 reload_spill_index
[r
] = i
;
5941 for (k
= 0; k
< nr
; k
++)
5942 SET_HARD_REG_BIT (reload_reg_used_for_inherit
,
5950 /* Here's another way to see if the value is already lying around. */
5952 && reload_in
[r
] != 0
5953 && ! reload_inherited
[r
]
5954 && reload_out
[r
] == 0
5955 && (CONSTANT_P (reload_in
[r
])
5956 || GET_CODE (reload_in
[r
]) == PLUS
5957 || GET_CODE (reload_in
[r
]) == REG
5958 || GET_CODE (reload_in
[r
]) == MEM
)
5959 && (reload_nregs
[r
] == max_group_size
5960 || ! reg_classes_intersect_p (reload_reg_class
[r
], group_class
)))
5963 = find_equiv_reg (reload_in
[r
], insn
, reload_reg_class
[r
],
5964 -1, NULL_PTR
, 0, reload_mode
[r
]);
5969 if (GET_CODE (equiv
) == REG
)
5970 regno
= REGNO (equiv
);
5971 else if (GET_CODE (equiv
) == SUBREG
)
5973 /* This must be a SUBREG of a hard register.
5974 Make a new REG since this might be used in an
5975 address and not all machines support SUBREGs
5977 regno
= REGNO (SUBREG_REG (equiv
)) + SUBREG_WORD (equiv
);
5978 equiv
= gen_rtx_REG (reload_mode
[r
], regno
);
5984 /* If we found a spill reg, reject it unless it is free
5985 and of the desired class. */
5987 && ((TEST_HARD_REG_BIT (reload_reg_used_at_all
, regno
)
5988 && ! reload_reg_free_for_value_p (regno
, reload_opnum
[r
],
5989 reload_when_needed
[r
],
5991 reload_out
[r
], r
, 1))
5992 || ! TEST_HARD_REG_BIT (reg_class_contents
[(int) reload_reg_class
[r
]],
5996 if (equiv
!= 0 && ! HARD_REGNO_MODE_OK (regno
, reload_mode
[r
]))
5999 /* We found a register that contains the value we need.
6000 If this register is the same as an `earlyclobber' operand
6001 of the current insn, just mark it as a place to reload from
6002 since we can't use it as the reload register itself. */
6005 for (i
= 0; i
< n_earlyclobbers
; i
++)
6006 if (reg_overlap_mentioned_for_reload_p (equiv
,
6007 reload_earlyclobbers
[i
]))
6009 reload_override_in
[r
] = equiv
;
6014 /* If the equiv register we have found is explicitly clobbered
6015 in the current insn, it depends on the reload type if we
6016 can use it, use it for reload_override_in, or not at all.
6017 In particular, we then can't use EQUIV for a
6018 RELOAD_FOR_OUTPUT_ADDRESS reload. */
6020 if (equiv
!= 0 && regno_clobbered_p (regno
, insn
))
6022 switch (reload_when_needed
[r
])
6024 case RELOAD_FOR_OTHER_ADDRESS
:
6025 case RELOAD_FOR_INPADDR_ADDRESS
:
6026 case RELOAD_FOR_INPUT_ADDRESS
:
6027 case RELOAD_FOR_OPADDR_ADDR
:
6030 case RELOAD_FOR_INPUT
:
6031 case RELOAD_FOR_OPERAND_ADDRESS
:
6032 reload_override_in
[r
] = equiv
;
6040 /* If we found an equivalent reg, say no code need be generated
6041 to load it, and use it as our reload reg. */
6042 if (equiv
!= 0 && regno
!= HARD_FRAME_POINTER_REGNUM
)
6044 int nr
= HARD_REGNO_NREGS (regno
, reload_mode
[r
]);
6046 reload_reg_rtx
[r
] = equiv
;
6047 reload_inherited
[r
] = 1;
6049 /* If reg_reloaded_valid is not set for this register,
6050 there might be a stale spill_reg_store lying around.
6051 We must clear it, since otherwise emit_reload_insns
6052 might delete the store. */
6053 if (! TEST_HARD_REG_BIT (reg_reloaded_valid
, regno
))
6054 spill_reg_store
[regno
] = NULL_RTX
;
6055 /* If any of the hard registers in EQUIV are spill
6056 registers, mark them as in use for this insn. */
6057 for (k
= 0; k
< nr
; k
++)
6059 i
= spill_reg_order
[regno
+ k
];
6062 mark_reload_reg_in_use (regno
, reload_opnum
[r
],
6063 reload_when_needed
[r
],
6065 SET_HARD_REG_BIT (reload_reg_used_for_inherit
,
6072 /* If we found a register to use already, or if this is an optional
6073 reload, we are done. */
6074 if (reload_reg_rtx
[r
] != 0 || reload_optional
[r
] != 0)
6077 #if 0 /* No longer needed for correct operation. Might or might not
6078 give better code on the average. Want to experiment? */
6080 /* See if there is a later reload that has a class different from our
6081 class that intersects our class or that requires less register
6082 than our reload. If so, we must allocate a register to this
6083 reload now, since that reload might inherit a previous reload
6084 and take the only available register in our class. Don't do this
6085 for optional reloads since they will force all previous reloads
6086 to be allocated. Also don't do this for reloads that have been
6089 for (i
= j
+ 1; i
< n_reloads
; i
++)
6091 int s
= reload_order
[i
];
6093 if ((reload_in
[s
] == 0 && reload_out
[s
] == 0
6094 && ! reload_secondary_p
[s
])
6095 || reload_optional
[s
])
6098 if ((reload_reg_class
[s
] != reload_reg_class
[r
]
6099 && reg_classes_intersect_p (reload_reg_class
[r
],
6100 reload_reg_class
[s
]))
6101 || reload_nregs
[s
] < reload_nregs
[r
])
6108 allocate_reload_reg (chain
, r
, j
== n_reloads
- 1, inheritance
);
6112 /* Now allocate reload registers for anything non-optional that
6113 didn't get one yet. */
6114 for (j
= 0; j
< n_reloads
; j
++)
6116 register int r
= reload_order
[j
];
6118 /* Ignore reloads that got marked inoperative. */
6119 if (reload_out
[r
] == 0 && reload_in
[r
] == 0 && ! reload_secondary_p
[r
])
6122 /* Skip reloads that already have a register allocated or are
6124 if (reload_reg_rtx
[r
] != 0 || reload_optional
[r
])
6127 if (! allocate_reload_reg (chain
, r
, j
== n_reloads
- 1, inheritance
))
6131 /* If that loop got all the way, we have won. */
6135 /* Loop around and try without any inheritance. */
6136 /* First undo everything done by the failed attempt
6137 to allocate with inheritance. */
6138 bcopy ((char *) save_reload_reg_rtx
, (char *) reload_reg_rtx
,
6139 sizeof reload_reg_rtx
);
6140 bcopy ((char *) save_reload_inherited
, (char *) reload_inherited
,
6141 sizeof reload_inherited
);
6142 bcopy ((char *) save_reload_inheritance_insn
,
6143 (char *) reload_inheritance_insn
,
6144 sizeof reload_inheritance_insn
);
6145 bcopy ((char *) save_reload_override_in
, (char *) reload_override_in
,
6146 sizeof reload_override_in
);
6147 bcopy ((char *) save_reload_spill_index
, (char *) reload_spill_index
,
6148 sizeof reload_spill_index
);
6149 COPY_HARD_REG_SET (reload_reg_used
, save_reload_reg_used
);
6150 COPY_HARD_REG_SET (reload_reg_used_at_all
, save_reload_reg_used_at_all
);
6151 COPY_HARD_REG_SET (reload_reg_used_in_op_addr
,
6152 save_reload_reg_used_in_op_addr
);
6153 COPY_HARD_REG_SET (reload_reg_used_in_op_addr_reload
,
6154 save_reload_reg_used_in_op_addr_reload
);
6155 COPY_HARD_REG_SET (reload_reg_used_in_insn
,
6156 save_reload_reg_used_in_insn
);
6157 COPY_HARD_REG_SET (reload_reg_used_in_other_addr
,
6158 save_reload_reg_used_in_other_addr
);
6160 for (i
= 0; i
< reload_n_operands
; i
++)
6162 COPY_HARD_REG_SET (reload_reg_used_in_input
[i
],
6163 save_reload_reg_used_in_input
[i
]);
6164 COPY_HARD_REG_SET (reload_reg_used_in_output
[i
],
6165 save_reload_reg_used_in_output
[i
]);
6166 COPY_HARD_REG_SET (reload_reg_used_in_input_addr
[i
],
6167 save_reload_reg_used_in_input_addr
[i
]);
6168 COPY_HARD_REG_SET (reload_reg_used_in_inpaddr_addr
[i
],
6169 save_reload_reg_used_in_inpaddr_addr
[i
]);
6170 COPY_HARD_REG_SET (reload_reg_used_in_output_addr
[i
],
6171 save_reload_reg_used_in_output_addr
[i
]);
6172 COPY_HARD_REG_SET (reload_reg_used_in_outaddr_addr
[i
],
6173 save_reload_reg_used_in_outaddr_addr
[i
]);
6177 /* If we thought we could inherit a reload, because it seemed that
6178 nothing else wanted the same reload register earlier in the insn,
6179 verify that assumption, now that all reloads have been assigned.
6180 Likewise for reloads where reload_override_in has been set. */
6182 /* If doing expensive optimizations, do one preliminary pass that doesn't
6183 cancel any inheritance, but removes reloads that have been needed only
6184 for reloads that we know can be inherited. */
6185 for (pass
= flag_expensive_optimizations
; pass
>= 0; pass
--)
6187 for (j
= 0; j
< n_reloads
; j
++)
6189 register int r
= reload_order
[j
];
6191 if (reload_inherited
[r
] && reload_reg_rtx
[r
])
6192 check_reg
= reload_reg_rtx
[r
];
6193 else if (reload_override_in
[r
]
6194 && (GET_CODE (reload_override_in
[r
]) == REG
6195 || GET_CODE (reload_override_in
[r
]) == SUBREG
))
6196 check_reg
= reload_override_in
[r
];
6199 if (! reload_reg_free_for_value_p (true_regnum (check_reg
),
6201 reload_when_needed
[r
],
6203 (reload_inherited
[r
]
6204 ? reload_out
[r
] : const0_rtx
),
6209 reload_inherited
[r
] = 0;
6210 reload_override_in
[r
] = 0;
6212 /* If we can inherit a RELOAD_FOR_INPUT, or can use a
6213 reload_override_in, then we do not need its related
6214 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads;
6215 likewise for other reload types.
6216 We handle this by removing a reload when its only replacement
6217 is mentioned in reload_in of the reload we are going to inherit.
6218 A special case are auto_inc expressions; even if the input is
6219 inherited, we still need the address for the output. We can
6220 recognize them because they have RELOAD_OUT set but not
6222 If we suceeded removing some reload and we are doing a preliminary
6223 pass just to remove such reloads, make another pass, since the
6224 removal of one reload might allow us to inherit another one. */
6225 else if ((! reload_out
[r
] || reload_out_reg
[r
])
6226 && remove_address_replacements (reload_in
[r
]) && pass
)
6231 /* Now that reload_override_in is known valid,
6232 actually override reload_in. */
6233 for (j
= 0; j
< n_reloads
; j
++)
6234 if (reload_override_in
[j
])
6235 reload_in
[j
] = reload_override_in
[j
];
6237 /* If this reload won't be done because it has been cancelled or is
6238 optional and not inherited, clear reload_reg_rtx so other
6239 routines (such as subst_reloads) don't get confused. */
6240 for (j
= 0; j
< n_reloads
; j
++)
6241 if (reload_reg_rtx
[j
] != 0
6242 && ((reload_optional
[j
] && ! reload_inherited
[j
])
6243 || (reload_in
[j
] == 0 && reload_out
[j
] == 0
6244 && ! reload_secondary_p
[j
])))
6246 int regno
= true_regnum (reload_reg_rtx
[j
]);
6248 if (spill_reg_order
[regno
] >= 0)
6249 clear_reload_reg_in_use (regno
, reload_opnum
[j
],
6250 reload_when_needed
[j
], reload_mode
[j
]);
6251 reload_reg_rtx
[j
] = 0;
6254 /* Record which pseudos and which spill regs have output reloads. */
6255 for (j
= 0; j
< n_reloads
; j
++)
6257 register int r
= reload_order
[j
];
6259 i
= reload_spill_index
[r
];
6261 /* I is nonneg if this reload uses a register.
6262 If reload_reg_rtx[r] is 0, this is an optional reload
6263 that we opted to ignore. */
6264 if (reload_out_reg
[r
] != 0 && GET_CODE (reload_out_reg
[r
]) == REG
6265 && reload_reg_rtx
[r
] != 0)
6267 register int nregno
= REGNO (reload_out_reg
[r
]);
6270 if (nregno
< FIRST_PSEUDO_REGISTER
)
6271 nr
= HARD_REGNO_NREGS (nregno
, reload_mode
[r
]);
6274 reg_has_output_reload
[nregno
+ nr
] = 1;
6278 nr
= HARD_REGNO_NREGS (i
, reload_mode
[r
]);
6280 SET_HARD_REG_BIT (reg_is_output_reload
, i
+ nr
);
6283 if (reload_when_needed
[r
] != RELOAD_OTHER
6284 && reload_when_needed
[r
] != RELOAD_FOR_OUTPUT
6285 && reload_when_needed
[r
] != RELOAD_FOR_INSN
)
6291 /* Deallocate the reload register for reload R. This is called from
6292 remove_address_replacements. */
6294 deallocate_reload_reg (r
)
6299 if (! reload_reg_rtx
[r
])
6301 regno
= true_regnum (reload_reg_rtx
[r
]);
6302 reload_reg_rtx
[r
] = 0;
6303 if (spill_reg_order
[regno
] >= 0)
6304 clear_reload_reg_in_use (regno
, reload_opnum
[r
], reload_when_needed
[r
],
6306 reload_spill_index
[r
] = -1;
6309 /* If SMALL_REGISTER_CLASSES is non-zero, we may not have merged two
6310 reloads of the same item for fear that we might not have enough reload
6311 registers. However, normally they will get the same reload register
6312 and hence actually need not be loaded twice.
6314 Here we check for the most common case of this phenomenon: when we have
6315 a number of reloads for the same object, each of which were allocated
6316 the same reload_reg_rtx, that reload_reg_rtx is not used for any other
6317 reload, and is not modified in the insn itself. If we find such,
6318 merge all the reloads and set the resulting reload to RELOAD_OTHER.
6319 This will not increase the number of spill registers needed and will
6320 prevent redundant code. */
6323 merge_assigned_reloads (insn
)
6328 /* Scan all the reloads looking for ones that only load values and
6329 are not already RELOAD_OTHER and ones whose reload_reg_rtx are
6330 assigned and not modified by INSN. */
6332 for (i
= 0; i
< n_reloads
; i
++)
6334 int conflicting_input
= 0;
6335 int max_input_address_opnum
= -1;
6336 int min_conflicting_input_opnum
= MAX_RECOG_OPERANDS
;
6338 if (reload_in
[i
] == 0 || reload_when_needed
[i
] == RELOAD_OTHER
6339 || reload_out
[i
] != 0 || reload_reg_rtx
[i
] == 0
6340 || reg_set_p (reload_reg_rtx
[i
], insn
))
6343 /* Look at all other reloads. Ensure that the only use of this
6344 reload_reg_rtx is in a reload that just loads the same value
6345 as we do. Note that any secondary reloads must be of the identical
6346 class since the values, modes, and result registers are the
6347 same, so we need not do anything with any secondary reloads. */
6349 for (j
= 0; j
< n_reloads
; j
++)
6351 if (i
== j
|| reload_reg_rtx
[j
] == 0
6352 || ! reg_overlap_mentioned_p (reload_reg_rtx
[j
],
6356 if (reload_when_needed
[j
] == RELOAD_FOR_INPUT_ADDRESS
6357 && reload_opnum
[j
] > max_input_address_opnum
)
6358 max_input_address_opnum
= reload_opnum
[j
];
6360 /* If the reload regs aren't exactly the same (e.g, different modes)
6361 or if the values are different, we can't merge this reload.
6362 But if it is an input reload, we might still merge
6363 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_OTHER_ADDRESS reloads. */
6365 if (! rtx_equal_p (reload_reg_rtx
[i
], reload_reg_rtx
[j
])
6366 || reload_out
[j
] != 0 || reload_in
[j
] == 0
6367 || ! rtx_equal_p (reload_in
[i
], reload_in
[j
]))
6369 if (reload_when_needed
[j
] != RELOAD_FOR_INPUT
6370 || ((reload_when_needed
[i
] != RELOAD_FOR_INPUT_ADDRESS
6371 || reload_opnum
[i
] > reload_opnum
[j
])
6372 && reload_when_needed
[i
] != RELOAD_FOR_OTHER_ADDRESS
))
6374 conflicting_input
= 1;
6375 if (min_conflicting_input_opnum
> reload_opnum
[j
])
6376 min_conflicting_input_opnum
= reload_opnum
[j
];
6380 /* If all is OK, merge the reloads. Only set this to RELOAD_OTHER if
6381 we, in fact, found any matching reloads. */
6384 && max_input_address_opnum
<= min_conflicting_input_opnum
)
6386 for (j
= 0; j
< n_reloads
; j
++)
6387 if (i
!= j
&& reload_reg_rtx
[j
] != 0
6388 && rtx_equal_p (reload_reg_rtx
[i
], reload_reg_rtx
[j
])
6389 && (! conflicting_input
6390 || reload_when_needed
[j
] == RELOAD_FOR_INPUT_ADDRESS
6391 || reload_when_needed
[j
] == RELOAD_FOR_OTHER_ADDRESS
))
6393 reload_when_needed
[i
] = RELOAD_OTHER
;
6395 reload_spill_index
[j
] = -1;
6396 transfer_replacements (i
, j
);
6399 /* If this is now RELOAD_OTHER, look for any reloads that load
6400 parts of this operand and set them to RELOAD_FOR_OTHER_ADDRESS
6401 if they were for inputs, RELOAD_OTHER for outputs. Note that
6402 this test is equivalent to looking for reloads for this operand
6405 if (reload_when_needed
[i
] == RELOAD_OTHER
)
6406 for (j
= 0; j
< n_reloads
; j
++)
6407 if (reload_in
[j
] != 0
6408 && reload_when_needed
[i
] != RELOAD_OTHER
6409 && reg_overlap_mentioned_for_reload_p (reload_in
[j
],
6411 reload_when_needed
[j
]
6412 = ((reload_when_needed
[i
] == RELOAD_FOR_INPUT_ADDRESS
6413 || reload_when_needed
[i
] == RELOAD_FOR_INPADDR_ADDRESS
)
6414 ? RELOAD_FOR_OTHER_ADDRESS
: RELOAD_OTHER
);
6420 /* Output insns to reload values in and out of the chosen reload regs. */
6423 emit_reload_insns (chain
)
6424 struct insn_chain
*chain
;
6426 rtx insn
= chain
->insn
;
6429 rtx input_reload_insns
[MAX_RECOG_OPERANDS
];
6430 rtx other_input_address_reload_insns
= 0;
6431 rtx other_input_reload_insns
= 0;
6432 rtx input_address_reload_insns
[MAX_RECOG_OPERANDS
];
6433 rtx inpaddr_address_reload_insns
[MAX_RECOG_OPERANDS
];
6434 rtx output_reload_insns
[MAX_RECOG_OPERANDS
];
6435 rtx output_address_reload_insns
[MAX_RECOG_OPERANDS
];
6436 rtx outaddr_address_reload_insns
[MAX_RECOG_OPERANDS
];
6437 rtx operand_reload_insns
= 0;
6438 rtx other_operand_reload_insns
= 0;
6439 rtx other_output_reload_insns
[MAX_RECOG_OPERANDS
];
6440 rtx following_insn
= NEXT_INSN (insn
);
6441 rtx before_insn
= PREV_INSN (insn
);
6443 /* Values to be put in spill_reg_store are put here first. */
6444 rtx new_spill_reg_store
[FIRST_PSEUDO_REGISTER
];
6445 HARD_REG_SET reg_reloaded_died
;
6447 CLEAR_HARD_REG_SET (reg_reloaded_died
);
6449 for (j
= 0; j
< reload_n_operands
; j
++)
6450 input_reload_insns
[j
] = input_address_reload_insns
[j
]
6451 = inpaddr_address_reload_insns
[j
]
6452 = output_reload_insns
[j
] = output_address_reload_insns
[j
]
6453 = outaddr_address_reload_insns
[j
]
6454 = other_output_reload_insns
[j
] = 0;
6456 /* Now output the instructions to copy the data into and out of the
6457 reload registers. Do these in the order that the reloads were reported,
6458 since reloads of base and index registers precede reloads of operands
6459 and the operands may need the base and index registers reloaded. */
6461 for (j
= 0; j
< n_reloads
; j
++)
6464 rtx oldequiv_reg
= 0;
6465 rtx this_reload_insn
= 0;
6466 int expect_occurrences
= 1;
6468 if (reload_reg_rtx
[j
]
6469 && REGNO (reload_reg_rtx
[j
]) < FIRST_PSEUDO_REGISTER
)
6470 new_spill_reg_store
[REGNO (reload_reg_rtx
[j
])] = 0;
6472 old
= (reload_in
[j
] && GET_CODE (reload_in
[j
]) == MEM
6473 ? reload_in_reg
[j
] : reload_in
[j
]);
6476 /* AUTO_INC reloads need to be handled even if inherited. We got an
6477 AUTO_INC reload if reload_out is set but reload_out_reg isn't. */
6478 && (! reload_inherited
[j
] || (reload_out
[j
] && ! reload_out_reg
[j
]))
6479 && ! rtx_equal_p (reload_reg_rtx
[j
], old
)
6480 && reload_reg_rtx
[j
] != 0)
6482 register rtx reloadreg
= reload_reg_rtx
[j
];
6484 enum machine_mode mode
;
6487 /* Determine the mode to reload in.
6488 This is very tricky because we have three to choose from.
6489 There is the mode the insn operand wants (reload_inmode[J]).
6490 There is the mode of the reload register RELOADREG.
6491 There is the intrinsic mode of the operand, which we could find
6492 by stripping some SUBREGs.
6493 It turns out that RELOADREG's mode is irrelevant:
6494 we can change that arbitrarily.
6496 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
6497 then the reload reg may not support QImode moves, so use SImode.
6498 If foo is in memory due to spilling a pseudo reg, this is safe,
6499 because the QImode value is in the least significant part of a
6500 slot big enough for a SImode. If foo is some other sort of
6501 memory reference, then it is impossible to reload this case,
6502 so previous passes had better make sure this never happens.
6504 Then consider a one-word union which has SImode and one of its
6505 members is a float, being fetched as (SUBREG:SF union:SI).
6506 We must fetch that as SFmode because we could be loading into
6507 a float-only register. In this case OLD's mode is correct.
6509 Consider an immediate integer: it has VOIDmode. Here we need
6510 to get a mode from something else.
6512 In some cases, there is a fourth mode, the operand's
6513 containing mode. If the insn specifies a containing mode for
6514 this operand, it overrides all others.
6516 I am not sure whether the algorithm here is always right,
6517 but it does the right things in those cases. */
6519 mode
= GET_MODE (old
);
6520 if (mode
== VOIDmode
)
6521 mode
= reload_inmode
[j
];
6523 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6524 /* If we need a secondary register for this operation, see if
6525 the value is already in a register in that class. Don't
6526 do this if the secondary register will be used as a scratch
6529 if (reload_secondary_in_reload
[j
] >= 0
6530 && reload_secondary_in_icode
[j
] == CODE_FOR_nothing
6533 = find_equiv_reg (old
, insn
,
6534 reload_reg_class
[reload_secondary_in_reload
[j
]],
6535 -1, NULL_PTR
, 0, mode
);
6538 /* If reloading from memory, see if there is a register
6539 that already holds the same value. If so, reload from there.
6540 We can pass 0 as the reload_reg_p argument because
6541 any other reload has either already been emitted,
6542 in which case find_equiv_reg will see the reload-insn,
6543 or has yet to be emitted, in which case it doesn't matter
6544 because we will use this equiv reg right away. */
6546 if (oldequiv
== 0 && optimize
6547 && (GET_CODE (old
) == MEM
6548 || (GET_CODE (old
) == REG
6549 && REGNO (old
) >= FIRST_PSEUDO_REGISTER
6550 && reg_renumber
[REGNO (old
)] < 0)))
6551 oldequiv
= find_equiv_reg (old
, insn
, ALL_REGS
,
6552 -1, NULL_PTR
, 0, mode
);
6556 int regno
= true_regnum (oldequiv
);
6558 /* Don't use OLDEQUIV if any other reload changes it at an
6559 earlier stage of this insn or at this stage. */
6560 if (! reload_reg_free_for_value_p (regno
, reload_opnum
[j
],
6561 reload_when_needed
[j
],
6562 reload_in
[j
], const0_rtx
, j
,
6566 /* If it is no cheaper to copy from OLDEQUIV into the
6567 reload register than it would be to move from memory,
6568 don't use it. Likewise, if we need a secondary register
6572 && ((REGNO_REG_CLASS (regno
) != reload_reg_class
[j
]
6573 && (REGISTER_MOVE_COST (REGNO_REG_CLASS (regno
),
6574 reload_reg_class
[j
])
6575 >= MEMORY_MOVE_COST (mode
, reload_reg_class
[j
], 1)))
6576 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6577 || (SECONDARY_INPUT_RELOAD_CLASS (reload_reg_class
[j
],
6581 #ifdef SECONDARY_MEMORY_NEEDED
6582 || SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (regno
),
6583 reload_reg_class
[j
],
6590 /* delete_output_reload is only invoked properly if old contains
6591 the original pseudo register. Since this is replaced with a
6592 hard reg when RELOAD_OVERRIDE_IN is set, see if we can
6593 find the pseudo in RELOAD_IN_REG. */
6595 && reload_override_in
[j
]
6596 && GET_CODE (reload_in_reg
[j
]) == REG
)
6599 old
= reload_in_reg
[j
];
6603 else if (GET_CODE (oldequiv
) == REG
)
6604 oldequiv_reg
= oldequiv
;
6605 else if (GET_CODE (oldequiv
) == SUBREG
)
6606 oldequiv_reg
= SUBREG_REG (oldequiv
);
6608 /* If we are reloading from a register that was recently stored in
6609 with an output-reload, see if we can prove there was
6610 actually no need to store the old value in it. */
6612 if (optimize
&& GET_CODE (oldequiv
) == REG
6613 && REGNO (oldequiv
) < FIRST_PSEUDO_REGISTER
6614 && spill_reg_store
[REGNO (oldequiv
)]
6615 && GET_CODE (old
) == REG
6616 && (dead_or_set_p (insn
, spill_reg_stored_to
[REGNO (oldequiv
)])
6617 || rtx_equal_p (spill_reg_stored_to
[REGNO (oldequiv
)],
6618 reload_out_reg
[j
])))
6619 delete_output_reload (insn
, j
, REGNO (oldequiv
));
6621 /* Encapsulate both RELOADREG and OLDEQUIV into that mode,
6622 then load RELOADREG from OLDEQUIV. Note that we cannot use
6623 gen_lowpart_common since it can do the wrong thing when
6624 RELOADREG has a multi-word mode. Note that RELOADREG
6625 must always be a REG here. */
6627 if (GET_MODE (reloadreg
) != mode
)
6628 reloadreg
= gen_rtx_REG (mode
, REGNO (reloadreg
));
6629 while (GET_CODE (oldequiv
) == SUBREG
&& GET_MODE (oldequiv
) != mode
)
6630 oldequiv
= SUBREG_REG (oldequiv
);
6631 if (GET_MODE (oldequiv
) != VOIDmode
6632 && mode
!= GET_MODE (oldequiv
))
6633 oldequiv
= gen_rtx_SUBREG (mode
, oldequiv
, 0);
6635 /* Switch to the right place to emit the reload insns. */
6636 switch (reload_when_needed
[j
])
6639 where
= &other_input_reload_insns
;
6641 case RELOAD_FOR_INPUT
:
6642 where
= &input_reload_insns
[reload_opnum
[j
]];
6644 case RELOAD_FOR_INPUT_ADDRESS
:
6645 where
= &input_address_reload_insns
[reload_opnum
[j
]];
6647 case RELOAD_FOR_INPADDR_ADDRESS
:
6648 where
= &inpaddr_address_reload_insns
[reload_opnum
[j
]];
6650 case RELOAD_FOR_OUTPUT_ADDRESS
:
6651 where
= &output_address_reload_insns
[reload_opnum
[j
]];
6653 case RELOAD_FOR_OUTADDR_ADDRESS
:
6654 where
= &outaddr_address_reload_insns
[reload_opnum
[j
]];
6656 case RELOAD_FOR_OPERAND_ADDRESS
:
6657 where
= &operand_reload_insns
;
6659 case RELOAD_FOR_OPADDR_ADDR
:
6660 where
= &other_operand_reload_insns
;
6662 case RELOAD_FOR_OTHER_ADDRESS
:
6663 where
= &other_input_address_reload_insns
;
6669 push_to_sequence (*where
);
6672 /* Auto-increment addresses must be reloaded in a special way. */
6673 if (reload_out
[j
] && ! reload_out_reg
[j
])
6675 /* We are not going to bother supporting the case where a
6676 incremented register can't be copied directly from
6677 OLDEQUIV since this seems highly unlikely. */
6678 if (reload_secondary_in_reload
[j
] >= 0)
6681 if (reload_inherited
[j
])
6682 oldequiv
= reloadreg
;
6684 old
= XEXP (reload_in_reg
[j
], 0);
6686 if (optimize
&& GET_CODE (oldequiv
) == REG
6687 && REGNO (oldequiv
) < FIRST_PSEUDO_REGISTER
6688 && spill_reg_store
[REGNO (oldequiv
)]
6689 && GET_CODE (old
) == REG
6690 && (dead_or_set_p (insn
,
6691 spill_reg_stored_to
[REGNO (oldequiv
)])
6692 || rtx_equal_p (spill_reg_stored_to
[REGNO (oldequiv
)],
6694 delete_output_reload (insn
, j
, REGNO (oldequiv
));
6696 /* Prevent normal processing of this reload. */
6698 /* Output a special code sequence for this case. */
6699 new_spill_reg_store
[REGNO (reloadreg
)]
6700 = inc_for_reload (reloadreg
, oldequiv
, reload_out
[j
],
6704 /* If we are reloading a pseudo-register that was set by the previous
6705 insn, see if we can get rid of that pseudo-register entirely
6706 by redirecting the previous insn into our reload register. */
6708 else if (optimize
&& GET_CODE (old
) == REG
6709 && REGNO (old
) >= FIRST_PSEUDO_REGISTER
6710 && dead_or_set_p (insn
, old
)
6711 /* This is unsafe if some other reload
6712 uses the same reg first. */
6713 && reload_reg_free_for_value_p (REGNO (reloadreg
),
6715 reload_when_needed
[j
],
6719 rtx temp
= PREV_INSN (insn
);
6720 while (temp
&& GET_CODE (temp
) == NOTE
)
6721 temp
= PREV_INSN (temp
);
6723 && GET_CODE (temp
) == INSN
6724 && GET_CODE (PATTERN (temp
)) == SET
6725 && SET_DEST (PATTERN (temp
)) == old
6726 /* Make sure we can access insn_operand_constraint. */
6727 && asm_noperands (PATTERN (temp
)) < 0
6728 /* This is unsafe if prev insn rejects our reload reg. */
6729 && constraint_accepts_reg_p (insn_operand_constraint
[recog_memoized (temp
)][0],
6731 /* This is unsafe if operand occurs more than once in current
6732 insn. Perhaps some occurrences aren't reloaded. */
6733 && count_occurrences (PATTERN (insn
), old
) == 1
6734 /* Don't risk splitting a matching pair of operands. */
6735 && ! reg_mentioned_p (old
, SET_SRC (PATTERN (temp
))))
6737 /* Store into the reload register instead of the pseudo. */
6738 SET_DEST (PATTERN (temp
)) = reloadreg
;
6740 /* If the previous insn is an output reload, the source is
6741 a reload register, and its spill_reg_store entry will
6742 contain the previous destination. This is now
6744 if (GET_CODE (SET_SRC (PATTERN (temp
))) == REG
6745 && REGNO (SET_SRC (PATTERN (temp
))) < FIRST_PSEUDO_REGISTER
)
6747 spill_reg_store
[REGNO (SET_SRC (PATTERN (temp
)))] = 0;
6748 spill_reg_stored_to
[REGNO (SET_SRC (PATTERN (temp
)))] = 0;
6751 /* If these are the only uses of the pseudo reg,
6752 pretend for GDB it lives in the reload reg we used. */
6753 if (REG_N_DEATHS (REGNO (old
)) == 1
6754 && REG_N_SETS (REGNO (old
)) == 1)
6756 reg_renumber
[REGNO (old
)] = REGNO (reload_reg_rtx
[j
]);
6757 alter_reg (REGNO (old
), -1);
6763 /* We can't do that, so output an insn to load RELOADREG. */
6767 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6768 rtx second_reload_reg
= 0;
6769 enum insn_code icode
;
6771 /* If we have a secondary reload, pick up the secondary register
6772 and icode, if any. If OLDEQUIV and OLD are different or
6773 if this is an in-out reload, recompute whether or not we
6774 still need a secondary register and what the icode should
6775 be. If we still need a secondary register and the class or
6776 icode is different, go back to reloading from OLD if using
6777 OLDEQUIV means that we got the wrong type of register. We
6778 cannot have different class or icode due to an in-out reload
6779 because we don't make such reloads when both the input and
6780 output need secondary reload registers. */
6782 if (reload_secondary_in_reload
[j
] >= 0)
6784 int secondary_reload
= reload_secondary_in_reload
[j
];
6785 rtx real_oldequiv
= oldequiv
;
6788 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
6789 and similarly for OLD.
6790 See comments in get_secondary_reload in reload.c. */
6791 /* If it is a pseudo that cannot be replaced with its
6792 equivalent MEM, we must fall back to reload_in, which
6793 will have all the necessary substitutions registered. */
6795 if (GET_CODE (oldequiv
) == REG
6796 && REGNO (oldequiv
) >= FIRST_PSEUDO_REGISTER
6797 && reg_equiv_memory_loc
[REGNO (oldequiv
)] != 0)
6799 if (reg_equiv_address
[REGNO (oldequiv
)]
6800 || num_not_at_initial_offset
)
6801 real_oldequiv
= reload_in
[j
];
6803 real_oldequiv
= reg_equiv_mem
[REGNO (oldequiv
)];
6806 if (GET_CODE (old
) == REG
6807 && REGNO (old
) >= FIRST_PSEUDO_REGISTER
6808 && reg_equiv_memory_loc
[REGNO (old
)] != 0)
6810 if (reg_equiv_address
[REGNO (old
)]
6811 || num_not_at_initial_offset
)
6812 real_old
= reload_in
[j
];
6814 real_old
= reg_equiv_mem
[REGNO (old
)];
6817 second_reload_reg
= reload_reg_rtx
[secondary_reload
];
6818 icode
= reload_secondary_in_icode
[j
];
6820 if ((old
!= oldequiv
&& ! rtx_equal_p (old
, oldequiv
))
6821 || (reload_in
[j
] != 0 && reload_out
[j
] != 0))
6823 enum reg_class new_class
6824 = SECONDARY_INPUT_RELOAD_CLASS (reload_reg_class
[j
],
6825 mode
, real_oldequiv
);
6827 if (new_class
== NO_REGS
)
6828 second_reload_reg
= 0;
6831 enum insn_code new_icode
;
6832 enum machine_mode new_mode
;
6834 if (! TEST_HARD_REG_BIT (reg_class_contents
[(int) new_class
],
6835 REGNO (second_reload_reg
)))
6836 oldequiv
= old
, real_oldequiv
= real_old
;
6839 new_icode
= reload_in_optab
[(int) mode
];
6840 if (new_icode
!= CODE_FOR_nothing
6841 && ((insn_operand_predicate
[(int) new_icode
][0]
6842 && ! ((*insn_operand_predicate
[(int) new_icode
][0])
6844 || (insn_operand_predicate
[(int) new_icode
][1]
6845 && ! ((*insn_operand_predicate
[(int) new_icode
][1])
6846 (real_oldequiv
, mode
)))))
6847 new_icode
= CODE_FOR_nothing
;
6849 if (new_icode
== CODE_FOR_nothing
)
6852 new_mode
= insn_operand_mode
[(int) new_icode
][2];
6854 if (GET_MODE (second_reload_reg
) != new_mode
)
6856 if (!HARD_REGNO_MODE_OK (REGNO (second_reload_reg
),
6858 oldequiv
= old
, real_oldequiv
= real_old
;
6861 = gen_rtx_REG (new_mode
,
6862 REGNO (second_reload_reg
));
6868 /* If we still need a secondary reload register, check
6869 to see if it is being used as a scratch or intermediate
6870 register and generate code appropriately. If we need
6871 a scratch register, use REAL_OLDEQUIV since the form of
6872 the insn may depend on the actual address if it is
6875 if (second_reload_reg
)
6877 if (icode
!= CODE_FOR_nothing
)
6879 emit_insn (GEN_FCN (icode
) (reloadreg
, real_oldequiv
,
6880 second_reload_reg
));
6885 /* See if we need a scratch register to load the
6886 intermediate register (a tertiary reload). */
6887 enum insn_code tertiary_icode
6888 = reload_secondary_in_icode
[secondary_reload
];
6890 if (tertiary_icode
!= CODE_FOR_nothing
)
6892 rtx third_reload_reg
6893 = reload_reg_rtx
[reload_secondary_in_reload
[secondary_reload
]];
6895 emit_insn ((GEN_FCN (tertiary_icode
)
6896 (second_reload_reg
, real_oldequiv
,
6897 third_reload_reg
)));
6900 gen_reload (second_reload_reg
, real_oldequiv
,
6902 reload_when_needed
[j
]);
6904 oldequiv
= second_reload_reg
;
6910 if (! special
&& ! rtx_equal_p (reloadreg
, oldequiv
))
6912 rtx real_oldequiv
= oldequiv
;
6914 if ((GET_CODE (oldequiv
) == REG
6915 && REGNO (oldequiv
) >= FIRST_PSEUDO_REGISTER
6916 && reg_equiv_memory_loc
[REGNO (oldequiv
)] != 0)
6917 || (GET_CODE (oldequiv
) == SUBREG
6918 && GET_CODE (SUBREG_REG (oldequiv
)) == REG
6919 && (REGNO (SUBREG_REG (oldequiv
))
6920 >= FIRST_PSEUDO_REGISTER
)
6921 && (reg_equiv_memory_loc
6922 [REGNO (SUBREG_REG (oldequiv
))] != 0)))
6923 real_oldequiv
= reload_in
[j
];
6924 gen_reload (reloadreg
, real_oldequiv
, reload_opnum
[j
],
6925 reload_when_needed
[j
]);
6930 this_reload_insn
= get_last_insn ();
6931 /* End this sequence. */
6932 *where
= get_insns ();
6935 /* Update reload_override_in so that delete_address_reloads_1
6936 can see the actual register usage. */
6938 reload_override_in
[j
] = oldequiv
;
6941 /* When inheriting a wider reload, we have a MEM in reload_in[j],
6942 e.g. inheriting a SImode output reload for
6943 (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */
6944 if (optimize
&& reload_inherited
[j
] && reload_in
[j
]
6945 && GET_CODE (reload_in
[j
]) == MEM
6946 && GET_CODE (reload_in_reg
[j
]) == MEM
6947 && reload_spill_index
[j
] >= 0
6948 && TEST_HARD_REG_BIT (reg_reloaded_valid
, reload_spill_index
[j
]))
6951 = count_occurrences (PATTERN (insn
), reload_in
[j
]) == 1 ? 0 : -1;
6953 = regno_reg_rtx
[reg_reloaded_contents
[reload_spill_index
[j
]]];
6956 /* If we are reloading a register that was recently stored in with an
6957 output-reload, see if we can prove there was
6958 actually no need to store the old value in it. */
6961 && (reload_inherited
[j
] || reload_override_in
[j
])
6962 && reload_reg_rtx
[j
]
6963 && GET_CODE (reload_reg_rtx
[j
]) == REG
6964 && spill_reg_store
[REGNO (reload_reg_rtx
[j
])] != 0
6966 /* There doesn't seem to be any reason to restrict this to pseudos
6967 and doing so loses in the case where we are copying from a
6968 register of the wrong class. */
6969 && REGNO (spill_reg_stored_to
[REGNO (reload_reg_rtx
[j
])])
6970 >= FIRST_PSEUDO_REGISTER
6972 /* The insn might have already some references to stackslots
6973 replaced by MEMs, while reload_out_reg still names the
6975 && (dead_or_set_p (insn
,
6976 spill_reg_stored_to
[REGNO (reload_reg_rtx
[j
])])
6977 || rtx_equal_p (spill_reg_stored_to
[REGNO (reload_reg_rtx
[j
])],
6978 reload_out_reg
[j
])))
6979 delete_output_reload (insn
, j
, REGNO (reload_reg_rtx
[j
]));
6981 /* Input-reloading is done. Now do output-reloading,
6982 storing the value from the reload-register after the main insn
6983 if reload_out[j] is nonzero.
6985 ??? At some point we need to support handling output reloads of
6986 JUMP_INSNs or insns that set cc0. */
6988 /* If this is an output reload that stores something that is
6989 not loaded in this same reload, see if we can eliminate a previous
6992 rtx pseudo
= reload_out_reg
[j
];
6995 && GET_CODE (pseudo
) == REG
6996 && ! rtx_equal_p (reload_in_reg
[j
], pseudo
)
6997 && REGNO (pseudo
) >= FIRST_PSEUDO_REGISTER
6998 && reg_last_reload_reg
[REGNO (pseudo
)])
7000 int pseudo_no
= REGNO (pseudo
);
7001 int last_regno
= REGNO (reg_last_reload_reg
[pseudo_no
]);
7003 /* We don't need to test full validity of last_regno for
7004 inherit here; we only want to know if the store actually
7005 matches the pseudo. */
7006 if (reg_reloaded_contents
[last_regno
] == pseudo_no
7007 && spill_reg_store
[last_regno
]
7008 && rtx_equal_p (pseudo
, spill_reg_stored_to
[last_regno
]))
7009 delete_output_reload (insn
, j
, last_regno
);
7013 old
= reload_out_reg
[j
];
7015 && reload_reg_rtx
[j
] != old
7016 && reload_reg_rtx
[j
] != 0)
7018 register rtx reloadreg
= reload_reg_rtx
[j
];
7019 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
7020 register rtx second_reloadreg
= 0;
7023 enum machine_mode mode
;
7026 /* An output operand that dies right away does need a reload,
7027 but need not be copied from it. Show the new location in the
7029 if ((GET_CODE (old
) == REG
|| GET_CODE (old
) == SCRATCH
)
7030 && (note
= find_reg_note (insn
, REG_UNUSED
, old
)) != 0)
7032 XEXP (note
, 0) = reload_reg_rtx
[j
];
7035 /* Likewise for a SUBREG of an operand that dies. */
7036 else if (GET_CODE (old
) == SUBREG
7037 && GET_CODE (SUBREG_REG (old
)) == REG
7038 && 0 != (note
= find_reg_note (insn
, REG_UNUSED
,
7041 XEXP (note
, 0) = gen_lowpart_common (GET_MODE (old
),
7045 else if (GET_CODE (old
) == SCRATCH
)
7046 /* If we aren't optimizing, there won't be a REG_UNUSED note,
7047 but we don't want to make an output reload. */
7051 /* Strip off of OLD any size-increasing SUBREGs such as
7052 (SUBREG:SI foo:QI 0). */
7054 while (GET_CODE (old
) == SUBREG
&& SUBREG_WORD (old
) == 0
7055 && (GET_MODE_SIZE (GET_MODE (old
))
7056 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (old
)))))
7057 old
= SUBREG_REG (old
);
7060 /* If is a JUMP_INSN, we can't support output reloads yet. */
7061 if (GET_CODE (insn
) == JUMP_INSN
)
7064 if (reload_when_needed
[j
] == RELOAD_OTHER
)
7067 push_to_sequence (output_reload_insns
[reload_opnum
[j
]]);
7069 old
= reload_out
[j
];
7071 /* Determine the mode to reload in.
7072 See comments above (for input reloading). */
7074 mode
= GET_MODE (old
);
7075 if (mode
== VOIDmode
)
7077 /* VOIDmode should never happen for an output. */
7078 if (asm_noperands (PATTERN (insn
)) < 0)
7079 /* It's the compiler's fault. */
7080 fatal_insn ("VOIDmode on an output", insn
);
7081 error_for_asm (insn
, "output operand is constant in `asm'");
7082 /* Prevent crash--use something we know is valid. */
7084 old
= gen_rtx_REG (mode
, REGNO (reloadreg
));
7087 if (GET_MODE (reloadreg
) != mode
)
7088 reloadreg
= gen_rtx_REG (mode
, REGNO (reloadreg
));
7090 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
7092 /* If we need two reload regs, set RELOADREG to the intermediate
7093 one, since it will be stored into OLD. We might need a secondary
7094 register only for an input reload, so check again here. */
7096 if (reload_secondary_out_reload
[j
] >= 0)
7100 if (GET_CODE (old
) == REG
&& REGNO (old
) >= FIRST_PSEUDO_REGISTER
7101 && reg_equiv_mem
[REGNO (old
)] != 0)
7102 real_old
= reg_equiv_mem
[REGNO (old
)];
7104 if((SECONDARY_OUTPUT_RELOAD_CLASS (reload_reg_class
[j
],
7108 second_reloadreg
= reloadreg
;
7109 reloadreg
= reload_reg_rtx
[reload_secondary_out_reload
[j
]];
7111 /* See if RELOADREG is to be used as a scratch register
7112 or as an intermediate register. */
7113 if (reload_secondary_out_icode
[j
] != CODE_FOR_nothing
)
7115 emit_insn ((GEN_FCN (reload_secondary_out_icode
[j
])
7116 (real_old
, second_reloadreg
, reloadreg
)));
7121 /* See if we need both a scratch and intermediate reload
7124 int secondary_reload
= reload_secondary_out_reload
[j
];
7125 enum insn_code tertiary_icode
7126 = reload_secondary_out_icode
[secondary_reload
];
7128 if (GET_MODE (reloadreg
) != mode
)
7129 reloadreg
= gen_rtx_REG (mode
, REGNO (reloadreg
));
7131 if (tertiary_icode
!= CODE_FOR_nothing
)
7134 = reload_reg_rtx
[reload_secondary_out_reload
[secondary_reload
]];
7137 /* Copy primary reload reg to secondary reload reg.
7138 (Note that these have been swapped above, then
7139 secondary reload reg to OLD using our insn. */
7141 /* If REAL_OLD is a paradoxical SUBREG, remove it
7142 and try to put the opposite SUBREG on
7144 if (GET_CODE (real_old
) == SUBREG
7145 && (GET_MODE_SIZE (GET_MODE (real_old
))
7146 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (real_old
))))
7147 && 0 != (tem
= gen_lowpart_common
7148 (GET_MODE (SUBREG_REG (real_old
)),
7150 real_old
= SUBREG_REG (real_old
), reloadreg
= tem
;
7152 gen_reload (reloadreg
, second_reloadreg
,
7153 reload_opnum
[j
], reload_when_needed
[j
]);
7154 emit_insn ((GEN_FCN (tertiary_icode
)
7155 (real_old
, reloadreg
, third_reloadreg
)));
7160 /* Copy between the reload regs here and then to
7163 gen_reload (reloadreg
, second_reloadreg
,
7164 reload_opnum
[j
], reload_when_needed
[j
]);
7170 /* Output the last reload insn. */
7175 /* Don't output the last reload if OLD is not the dest of
7176 INSN and is in the src and is clobbered by INSN. */
7177 if (! flag_expensive_optimizations
7178 || GET_CODE (old
) != REG
7179 || !(set
= single_set (insn
))
7180 || rtx_equal_p (old
, SET_DEST (set
))
7181 || !reg_mentioned_p (old
, SET_SRC (set
))
7182 || !regno_clobbered_p (REGNO (old
), insn
))
7183 gen_reload (old
, reloadreg
, reload_opnum
[j
],
7184 reload_when_needed
[j
]);
7187 /* Look at all insns we emitted, just to be safe. */
7188 for (p
= get_insns (); p
; p
= NEXT_INSN (p
))
7189 if (GET_RTX_CLASS (GET_CODE (p
)) == 'i')
7191 rtx pat
= PATTERN (p
);
7193 /* If this output reload doesn't come from a spill reg,
7194 clear any memory of reloaded copies of the pseudo reg.
7195 If this output reload comes from a spill reg,
7196 reg_has_output_reload will make this do nothing. */
7197 note_stores (pat
, forget_old_reloads_1
);
7199 if (reg_mentioned_p (reload_reg_rtx
[j
], pat
))
7201 rtx set
= single_set (insn
);
7202 if (reload_spill_index
[j
] < 0
7204 && SET_SRC (set
) == reload_reg_rtx
[j
])
7206 int src
= REGNO (SET_SRC (set
));
7208 reload_spill_index
[j
] = src
;
7209 SET_HARD_REG_BIT (reg_is_output_reload
, src
);
7210 if (find_regno_note (insn
, REG_DEAD
, src
))
7211 SET_HARD_REG_BIT (reg_reloaded_died
, src
);
7213 if (REGNO (reload_reg_rtx
[j
]) < FIRST_PSEUDO_REGISTER
)
7215 int s
= reload_secondary_out_reload
[j
];
7216 set
= single_set (p
);
7217 /* If this reload copies only to the secondary reload
7218 register, the secondary reload does the actual
7220 if (s
>= 0 && set
== NULL_RTX
)
7221 ; /* We can't tell what function the secondary reload
7222 has and where the actual store to the pseudo is
7223 made; leave new_spill_reg_store alone. */
7225 && SET_SRC (set
) == reload_reg_rtx
[j
]
7226 && SET_DEST (set
) == reload_reg_rtx
[s
])
7228 /* Usually the next instruction will be the
7229 secondary reload insn; if we can confirm
7230 that it is, setting new_spill_reg_store to
7231 that insn will allow an extra optimization. */
7232 rtx s_reg
= reload_reg_rtx
[s
];
7233 rtx next
= NEXT_INSN (p
);
7234 reload_out
[s
] = reload_out
[j
];
7235 reload_out_reg
[s
] = reload_out_reg
[j
];
7236 set
= single_set (next
);
7237 if (set
&& SET_SRC (set
) == s_reg
7238 && ! new_spill_reg_store
[REGNO (s_reg
)])
7240 SET_HARD_REG_BIT (reg_is_output_reload
,
7242 new_spill_reg_store
[REGNO (s_reg
)] = next
;
7246 new_spill_reg_store
[REGNO (reload_reg_rtx
[j
])] = p
;
7251 if (reload_when_needed
[j
] == RELOAD_OTHER
)
7253 emit_insns (other_output_reload_insns
[reload_opnum
[j
]]);
7254 other_output_reload_insns
[reload_opnum
[j
]] = get_insns ();
7257 output_reload_insns
[reload_opnum
[j
]] = get_insns ();
7263 /* Now write all the insns we made for reloads in the order expected by
7264 the allocation functions. Prior to the insn being reloaded, we write
7265 the following reloads:
7267 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
7269 RELOAD_OTHER reloads.
7271 For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
7272 by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
7273 RELOAD_FOR_INPUT reload for the operand.
7275 RELOAD_FOR_OPADDR_ADDRS reloads.
7277 RELOAD_FOR_OPERAND_ADDRESS reloads.
7279 After the insn being reloaded, we write the following:
7281 For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
7282 by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
7283 RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
7284 reloads for the operand. The RELOAD_OTHER output reloads are
7285 output in descending order by reload number. */
7287 emit_insns_before (other_input_address_reload_insns
, insn
);
7288 emit_insns_before (other_input_reload_insns
, insn
);
7290 for (j
= 0; j
< reload_n_operands
; j
++)
7292 emit_insns_before (inpaddr_address_reload_insns
[j
], insn
);
7293 emit_insns_before (input_address_reload_insns
[j
], insn
);
7294 emit_insns_before (input_reload_insns
[j
], insn
);
7297 emit_insns_before (other_operand_reload_insns
, insn
);
7298 emit_insns_before (operand_reload_insns
, insn
);
7300 for (j
= 0; j
< reload_n_operands
; j
++)
7302 emit_insns_before (outaddr_address_reload_insns
[j
], following_insn
);
7303 emit_insns_before (output_address_reload_insns
[j
], following_insn
);
7304 emit_insns_before (output_reload_insns
[j
], following_insn
);
7305 emit_insns_before (other_output_reload_insns
[j
], following_insn
);
7308 /* Keep basic block info up to date. */
7311 if (BLOCK_HEAD (chain
->block
) == insn
)
7312 BLOCK_HEAD (chain
->block
) = NEXT_INSN (before_insn
);
7313 if (BLOCK_END (chain
->block
) == insn
)
7314 BLOCK_END (chain
->block
) = PREV_INSN (following_insn
);
7317 /* For all the spill regs newly reloaded in this instruction,
7318 record what they were reloaded from, so subsequent instructions
7319 can inherit the reloads.
7321 Update spill_reg_store for the reloads of this insn.
7322 Copy the elements that were updated in the loop above. */
7324 for (j
= 0; j
< n_reloads
; j
++)
7326 register int r
= reload_order
[j
];
7327 register int i
= reload_spill_index
[r
];
7329 /* If this is a non-inherited input reload from a pseudo, we must
7330 clear any memory of a previous store to the same pseudo. Only do
7331 something if there will not be an output reload for the pseudo
7333 if (reload_in_reg
[r
] != 0
7334 && ! (reload_inherited
[r
] || reload_override_in
[r
]))
7336 rtx reg
= reload_in_reg
[r
];
7338 if (GET_CODE (reg
) == SUBREG
)
7339 reg
= SUBREG_REG (reg
);
7341 if (GET_CODE (reg
) == REG
7342 && REGNO (reg
) >= FIRST_PSEUDO_REGISTER
7343 && ! reg_has_output_reload
[REGNO (reg
)])
7345 int nregno
= REGNO (reg
);
7347 if (reg_last_reload_reg
[nregno
])
7349 int last_regno
= REGNO (reg_last_reload_reg
[nregno
]);
7351 if (reg_reloaded_contents
[last_regno
] == nregno
)
7352 spill_reg_store
[last_regno
] = 0;
7357 /* I is nonneg if this reload used a register.
7358 If reload_reg_rtx[r] is 0, this is an optional reload
7359 that we opted to ignore. */
7361 if (i
>= 0 && reload_reg_rtx
[r
] != 0)
7364 = HARD_REGNO_NREGS (i
, GET_MODE (reload_reg_rtx
[r
]));
7366 int part_reaches_end
= 0;
7367 int all_reaches_end
= 1;
7369 /* For a multi register reload, we need to check if all or part
7370 of the value lives to the end. */
7371 for (k
= 0; k
< nr
; k
++)
7373 if (reload_reg_reaches_end_p (i
+ k
, reload_opnum
[r
],
7374 reload_when_needed
[r
]))
7375 part_reaches_end
= 1;
7377 all_reaches_end
= 0;
7380 /* Ignore reloads that don't reach the end of the insn in
7382 if (all_reaches_end
)
7384 /* First, clear out memory of what used to be in this spill reg.
7385 If consecutive registers are used, clear them all. */
7387 for (k
= 0; k
< nr
; k
++)
7388 CLEAR_HARD_REG_BIT (reg_reloaded_valid
, i
+ k
);
7390 /* Maybe the spill reg contains a copy of reload_out. */
7391 if (reload_out
[r
] != 0
7392 && (GET_CODE (reload_out
[r
]) == REG
7394 || ! reload_out_reg
[r
]
7396 || GET_CODE (reload_out_reg
[r
]) == REG
))
7398 rtx out
= (GET_CODE (reload_out
[r
]) == REG
7402 /* AUTO_INC */ : XEXP (reload_in_reg
[r
], 0));
7403 register int nregno
= REGNO (out
);
7404 int nnr
= (nregno
>= FIRST_PSEUDO_REGISTER
? 1
7405 : HARD_REGNO_NREGS (nregno
,
7406 GET_MODE (reload_reg_rtx
[r
])));
7408 spill_reg_store
[i
] = new_spill_reg_store
[i
];
7409 spill_reg_stored_to
[i
] = out
;
7410 reg_last_reload_reg
[nregno
] = reload_reg_rtx
[r
];
7412 /* If NREGNO is a hard register, it may occupy more than
7413 one register. If it does, say what is in the
7414 rest of the registers assuming that both registers
7415 agree on how many words the object takes. If not,
7416 invalidate the subsequent registers. */
7418 if (nregno
< FIRST_PSEUDO_REGISTER
)
7419 for (k
= 1; k
< nnr
; k
++)
7420 reg_last_reload_reg
[nregno
+ k
]
7422 ? gen_rtx_REG (reg_raw_mode
[REGNO (reload_reg_rtx
[r
]) + k
],
7423 REGNO (reload_reg_rtx
[r
]) + k
)
7426 /* Now do the inverse operation. */
7427 for (k
= 0; k
< nr
; k
++)
7429 CLEAR_HARD_REG_BIT (reg_reloaded_dead
, i
+ k
);
7430 reg_reloaded_contents
[i
+ k
]
7431 = (nregno
>= FIRST_PSEUDO_REGISTER
|| nr
!= nnr
7434 reg_reloaded_insn
[i
+ k
] = insn
;
7435 SET_HARD_REG_BIT (reg_reloaded_valid
, i
+ k
);
7439 /* Maybe the spill reg contains a copy of reload_in. Only do
7440 something if there will not be an output reload for
7441 the register being reloaded. */
7442 else if (reload_out_reg
[r
] == 0
7443 && reload_in
[r
] != 0
7444 && ((GET_CODE (reload_in
[r
]) == REG
7445 && REGNO (reload_in
[r
]) >= FIRST_PSEUDO_REGISTER
7446 && ! reg_has_output_reload
[REGNO (reload_in
[r
])])
7447 || (GET_CODE (reload_in_reg
[r
]) == REG
7448 && ! reg_has_output_reload
[REGNO (reload_in_reg
[r
])]))
7449 && ! reg_set_p (reload_reg_rtx
[r
], PATTERN (insn
)))
7451 register int nregno
;
7454 if (GET_CODE (reload_in
[r
]) == REG
7455 && REGNO (reload_in
[r
]) >= FIRST_PSEUDO_REGISTER
)
7456 nregno
= REGNO (reload_in
[r
]);
7457 else if (GET_CODE (reload_in_reg
[r
]) == REG
)
7458 nregno
= REGNO (reload_in_reg
[r
]);
7460 nregno
= REGNO (XEXP (reload_in_reg
[r
], 0));
7462 nnr
= (nregno
>= FIRST_PSEUDO_REGISTER
? 1
7463 : HARD_REGNO_NREGS (nregno
,
7464 GET_MODE (reload_reg_rtx
[r
])));
7466 reg_last_reload_reg
[nregno
] = reload_reg_rtx
[r
];
7468 if (nregno
< FIRST_PSEUDO_REGISTER
)
7469 for (k
= 1; k
< nnr
; k
++)
7470 reg_last_reload_reg
[nregno
+ k
]
7472 ? gen_rtx_REG (reg_raw_mode
[REGNO (reload_reg_rtx
[r
]) + k
],
7473 REGNO (reload_reg_rtx
[r
]) + k
)
7476 /* Unless we inherited this reload, show we haven't
7477 recently done a store.
7478 Previous stores of inherited auto_inc expressions
7479 also have to be discarded. */
7480 if (! reload_inherited
[r
]
7481 || (reload_out
[r
] && ! reload_out_reg
[r
]))
7482 spill_reg_store
[i
] = 0;
7484 for (k
= 0; k
< nr
; k
++)
7486 CLEAR_HARD_REG_BIT (reg_reloaded_dead
, i
+ k
);
7487 reg_reloaded_contents
[i
+ k
]
7488 = (nregno
>= FIRST_PSEUDO_REGISTER
|| nr
!= nnr
7491 reg_reloaded_insn
[i
+ k
] = insn
;
7492 SET_HARD_REG_BIT (reg_reloaded_valid
, i
+ k
);
7497 /* However, if part of the reload reaches the end, then we must
7498 invalidate the old info for the part that survives to the end. */
7499 else if (part_reaches_end
)
7501 for (k
= 0; k
< nr
; k
++)
7502 if (reload_reg_reaches_end_p (i
+ k
,
7504 reload_when_needed
[r
]))
7505 CLEAR_HARD_REG_BIT (reg_reloaded_valid
, i
+ k
);
7509 /* The following if-statement was #if 0'd in 1.34 (or before...).
7510 It's reenabled in 1.35 because supposedly nothing else
7511 deals with this problem. */
7513 /* If a register gets output-reloaded from a non-spill register,
7514 that invalidates any previous reloaded copy of it.
7515 But forget_old_reloads_1 won't get to see it, because
7516 it thinks only about the original insn. So invalidate it here. */
7517 if (i
< 0 && reload_out
[r
] != 0
7518 && (GET_CODE (reload_out
[r
]) == REG
7519 || (GET_CODE (reload_out
[r
]) == MEM
7520 && GET_CODE (reload_out_reg
[r
]) == REG
)))
7522 rtx out
= (GET_CODE (reload_out
[r
]) == REG
7523 ? reload_out
[r
] : reload_out_reg
[r
]);
7524 register int nregno
= REGNO (out
);
7525 if (nregno
>= FIRST_PSEUDO_REGISTER
)
7527 rtx src_reg
, store_insn
;
7529 reg_last_reload_reg
[nregno
] = 0;
7531 /* If we can find a hard register that is stored, record
7532 the storing insn so that we may delete this insn with
7533 delete_output_reload. */
7534 src_reg
= reload_reg_rtx
[r
];
7536 /* If this is an optional reload, try to find the source reg
7537 from an input reload. */
7540 rtx set
= single_set (insn
);
7541 if (set
&& SET_DEST (set
) == reload_out
[r
])
7545 src_reg
= SET_SRC (set
);
7547 for (k
= 0; k
< n_reloads
; k
++)
7549 if (reload_in
[k
] == src_reg
)
7551 src_reg
= reload_reg_rtx
[k
];
7558 store_insn
= new_spill_reg_store
[REGNO (src_reg
)];
7559 if (src_reg
&& GET_CODE (src_reg
) == REG
7560 && REGNO (src_reg
) < FIRST_PSEUDO_REGISTER
)
7562 int src_regno
= REGNO (src_reg
);
7563 int nr
= HARD_REGNO_NREGS (src_regno
, reload_mode
[r
]);
7564 /* The place where to find a death note varies with
7565 PRESERVE_DEATH_INFO_REGNO_P . The condition is not
7566 necessarily checked exactly in the code that moves
7567 notes, so just check both locations. */
7568 rtx note
= find_regno_note (insn
, REG_DEAD
, src_regno
);
7570 note
= find_regno_note (store_insn
, REG_DEAD
, src_regno
);
7573 spill_reg_store
[src_regno
+ nr
] = store_insn
;
7574 spill_reg_stored_to
[src_regno
+ nr
] = out
;
7575 reg_reloaded_contents
[src_regno
+ nr
] = nregno
;
7576 reg_reloaded_insn
[src_regno
+ nr
] = store_insn
;
7577 CLEAR_HARD_REG_BIT (reg_reloaded_dead
, src_regno
+ nr
);
7578 SET_HARD_REG_BIT (reg_reloaded_valid
, src_regno
+ nr
);
7579 SET_HARD_REG_BIT (reg_is_output_reload
, src_regno
+ nr
);
7581 SET_HARD_REG_BIT (reg_reloaded_died
, src_regno
);
7583 CLEAR_HARD_REG_BIT (reg_reloaded_died
, src_regno
);
7585 reg_last_reload_reg
[nregno
] = src_reg
;
7590 int num_regs
= HARD_REGNO_NREGS (nregno
,GET_MODE (reload_out
[r
]));
7592 while (num_regs
-- > 0)
7593 reg_last_reload_reg
[nregno
+ num_regs
] = 0;
7597 IOR_HARD_REG_SET (reg_reloaded_dead
, reg_reloaded_died
);
7600 /* Emit code to perform a reload from IN (which may be a reload register) to
7601 OUT (which may also be a reload register). IN or OUT is from operand
7602 OPNUM with reload type TYPE.
7604 Returns first insn emitted. */
7607 gen_reload (out
, in
, opnum
, type
)
7611 enum reload_type type
;
7613 rtx last
= get_last_insn ();
7616 /* If IN is a paradoxical SUBREG, remove it and try to put the
7617 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
7618 if (GET_CODE (in
) == SUBREG
7619 && (GET_MODE_SIZE (GET_MODE (in
))
7620 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in
))))
7621 && (tem
= gen_lowpart_common (GET_MODE (SUBREG_REG (in
)), out
)) != 0)
7622 in
= SUBREG_REG (in
), out
= tem
;
7623 else if (GET_CODE (out
) == SUBREG
7624 && (GET_MODE_SIZE (GET_MODE (out
))
7625 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out
))))
7626 && (tem
= gen_lowpart_common (GET_MODE (SUBREG_REG (out
)), in
)) != 0)
7627 out
= SUBREG_REG (out
), in
= tem
;
7629 /* How to do this reload can get quite tricky. Normally, we are being
7630 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
7631 register that didn't get a hard register. In that case we can just
7632 call emit_move_insn.
7634 We can also be asked to reload a PLUS that adds a register or a MEM to
7635 another register, constant or MEM. This can occur during frame pointer
7636 elimination and while reloading addresses. This case is handled by
7637 trying to emit a single insn to perform the add. If it is not valid,
7638 we use a two insn sequence.
7640 Finally, we could be called to handle an 'o' constraint by putting
7641 an address into a register. In that case, we first try to do this
7642 with a named pattern of "reload_load_address". If no such pattern
7643 exists, we just emit a SET insn and hope for the best (it will normally
7644 be valid on machines that use 'o').
7646 This entire process is made complex because reload will never
7647 process the insns we generate here and so we must ensure that
7648 they will fit their constraints and also by the fact that parts of
7649 IN might be being reloaded separately and replaced with spill registers.
7650 Because of this, we are, in some sense, just guessing the right approach
7651 here. The one listed above seems to work.
7653 ??? At some point, this whole thing needs to be rethought. */
7655 if (GET_CODE (in
) == PLUS
7656 && (GET_CODE (XEXP (in
, 0)) == REG
7657 || GET_CODE (XEXP (in
, 0)) == SUBREG
7658 || GET_CODE (XEXP (in
, 0)) == MEM
)
7659 && (GET_CODE (XEXP (in
, 1)) == REG
7660 || GET_CODE (XEXP (in
, 1)) == SUBREG
7661 || CONSTANT_P (XEXP (in
, 1))
7662 || GET_CODE (XEXP (in
, 1)) == MEM
))
7664 /* We need to compute the sum of a register or a MEM and another
7665 register, constant, or MEM, and put it into the reload
7666 register. The best possible way of doing this is if the machine
7667 has a three-operand ADD insn that accepts the required operands.
7669 The simplest approach is to try to generate such an insn and see if it
7670 is recognized and matches its constraints. If so, it can be used.
7672 It might be better not to actually emit the insn unless it is valid,
7673 but we need to pass the insn as an operand to `recog' and
7674 `extract_insn' and it is simpler to emit and then delete the insn if
7675 not valid than to dummy things up. */
7677 rtx op0
, op1
, tem
, insn
;
7680 op0
= find_replacement (&XEXP (in
, 0));
7681 op1
= find_replacement (&XEXP (in
, 1));
7683 /* Since constraint checking is strict, commutativity won't be
7684 checked, so we need to do that here to avoid spurious failure
7685 if the add instruction is two-address and the second operand
7686 of the add is the same as the reload reg, which is frequently
7687 the case. If the insn would be A = B + A, rearrange it so
7688 it will be A = A + B as constrain_operands expects. */
7690 if (GET_CODE (XEXP (in
, 1)) == REG
7691 && REGNO (out
) == REGNO (XEXP (in
, 1)))
7692 tem
= op0
, op0
= op1
, op1
= tem
;
7694 if (op0
!= XEXP (in
, 0) || op1
!= XEXP (in
, 1))
7695 in
= gen_rtx_PLUS (GET_MODE (in
), op0
, op1
);
7697 insn
= emit_insn (gen_rtx_SET (VOIDmode
, out
, in
));
7698 code
= recog_memoized (insn
);
7702 extract_insn (insn
);
7703 /* We want constrain operands to treat this insn strictly in
7704 its validity determination, i.e., the way it would after reload
7706 if (constrain_operands (1))
7710 delete_insns_since (last
);
7712 /* If that failed, we must use a conservative two-insn sequence.
7713 use move to copy constant, MEM, or pseudo register to the reload
7714 register since "move" will be able to handle an arbitrary operand,
7715 unlike add which can't, in general. Then add the registers.
7717 If there is another way to do this for a specific machine, a
7718 DEFINE_PEEPHOLE should be specified that recognizes the sequence
7721 if (CONSTANT_P (op1
) || GET_CODE (op1
) == MEM
|| GET_CODE (op1
) == SUBREG
7722 || (GET_CODE (op1
) == REG
7723 && REGNO (op1
) >= FIRST_PSEUDO_REGISTER
))
7724 tem
= op0
, op0
= op1
, op1
= tem
;
7726 gen_reload (out
, op0
, opnum
, type
);
7728 /* If OP0 and OP1 are the same, we can use OUT for OP1.
7729 This fixes a problem on the 32K where the stack pointer cannot
7730 be used as an operand of an add insn. */
7732 if (rtx_equal_p (op0
, op1
))
7735 insn
= emit_insn (gen_add2_insn (out
, op1
));
7737 /* If that failed, copy the address register to the reload register.
7738 Then add the constant to the reload register. */
7740 code
= recog_memoized (insn
);
7744 extract_insn (insn
);
7745 /* We want constrain operands to treat this insn strictly in
7746 its validity determination, i.e., the way it would after reload
7748 if (constrain_operands (1))
7750 /* Add a REG_EQUIV note so that find_equiv_reg can find it. */
7752 = gen_rtx_EXPR_LIST (REG_EQUIV
, in
, REG_NOTES (insn
));
7757 delete_insns_since (last
);
7759 gen_reload (out
, op1
, opnum
, type
);
7760 insn
= emit_insn (gen_add2_insn (out
, op0
));
7761 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_EQUIV
, in
, REG_NOTES (insn
));
7764 #ifdef SECONDARY_MEMORY_NEEDED
7765 /* If we need a memory location to do the move, do it that way. */
7766 else if (GET_CODE (in
) == REG
&& REGNO (in
) < FIRST_PSEUDO_REGISTER
7767 && GET_CODE (out
) == REG
&& REGNO (out
) < FIRST_PSEUDO_REGISTER
7768 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (REGNO (in
)),
7769 REGNO_REG_CLASS (REGNO (out
)),
7772 /* Get the memory to use and rewrite both registers to its mode. */
7773 rtx loc
= get_secondary_mem (in
, GET_MODE (out
), opnum
, type
);
7775 if (GET_MODE (loc
) != GET_MODE (out
))
7776 out
= gen_rtx_REG (GET_MODE (loc
), REGNO (out
));
7778 if (GET_MODE (loc
) != GET_MODE (in
))
7779 in
= gen_rtx_REG (GET_MODE (loc
), REGNO (in
));
7781 gen_reload (loc
, in
, opnum
, type
);
7782 gen_reload (out
, loc
, opnum
, type
);
7786 /* If IN is a simple operand, use gen_move_insn. */
7787 else if (GET_RTX_CLASS (GET_CODE (in
)) == 'o' || GET_CODE (in
) == SUBREG
)
7788 emit_insn (gen_move_insn (out
, in
));
7790 #ifdef HAVE_reload_load_address
7791 else if (HAVE_reload_load_address
)
7792 emit_insn (gen_reload_load_address (out
, in
));
7795 /* Otherwise, just write (set OUT IN) and hope for the best. */
7797 emit_insn (gen_rtx_SET (VOIDmode
, out
, in
));
7799 /* Return the first insn emitted.
7800 We can not just return get_last_insn, because there may have
7801 been multiple instructions emitted. Also note that gen_move_insn may
7802 emit more than one insn itself, so we can not assume that there is one
7803 insn emitted per emit_insn_before call. */
7805 return last
? NEXT_INSN (last
) : get_insns ();
7808 /* Delete a previously made output-reload
7809 whose result we now believe is not needed.
7810 First we double-check.
7812 INSN is the insn now being processed.
7813 LAST_RELOAD_REG is the hard register number for which we want to delete
7814 the last output reload.
7815 J is the reload-number that originally used REG. The caller has made
7816 certain that reload J doesn't use REG any longer for input. */
7819 delete_output_reload (insn
, j
, last_reload_reg
)
7822 int last_reload_reg
;
7824 rtx output_reload_insn
= spill_reg_store
[last_reload_reg
];
7825 rtx reg
= spill_reg_stored_to
[last_reload_reg
];
7828 int n_inherited
= 0;
7832 /* Get the raw pseudo-register referred to. */
7834 while (GET_CODE (reg
) == SUBREG
)
7835 reg
= SUBREG_REG (reg
);
7836 substed
= reg_equiv_memory_loc
[REGNO (reg
)];
7838 /* This is unsafe if the operand occurs more often in the current
7839 insn than it is inherited. */
7840 for (k
= n_reloads
- 1; k
>= 0; k
--)
7842 rtx reg2
= reload_in
[k
];
7845 if (GET_CODE (reg2
) == MEM
|| reload_override_in
[k
])
7846 reg2
= reload_in_reg
[k
];
7848 if (reload_out
[k
] && ! reload_out_reg
[k
])
7849 reg2
= XEXP (reload_in_reg
[k
], 0);
7851 while (GET_CODE (reg2
) == SUBREG
)
7852 reg2
= SUBREG_REG (reg2
);
7853 if (rtx_equal_p (reg2
, reg
))
7855 if (reload_inherited
[k
] || reload_override_in
[k
] || k
== j
)
7858 reg2
= reload_out_reg
[k
];
7861 while (GET_CODE (reg2
) == SUBREG
)
7862 reg2
= XEXP (reg2
, 0);
7863 if (rtx_equal_p (reg2
, reg
))
7870 n_occurrences
= count_occurrences (PATTERN (insn
), reg
);
7872 n_occurrences
+= count_occurrences (PATTERN (insn
), substed
);
7873 if (n_occurrences
> n_inherited
)
7876 /* If the pseudo-reg we are reloading is no longer referenced
7877 anywhere between the store into it and here,
7878 and no jumps or labels intervene, then the value can get
7879 here through the reload reg alone.
7880 Otherwise, give up--return. */
7881 for (i1
= NEXT_INSN (output_reload_insn
);
7882 i1
!= insn
; i1
= NEXT_INSN (i1
))
7884 if (GET_CODE (i1
) == CODE_LABEL
|| GET_CODE (i1
) == JUMP_INSN
)
7886 if ((GET_CODE (i1
) == INSN
|| GET_CODE (i1
) == CALL_INSN
)
7887 && reg_mentioned_p (reg
, PATTERN (i1
)))
7889 /* If this is USE in front of INSN, we only have to check that
7890 there are no more references than accounted for by inheritance. */
7891 while (GET_CODE (i1
) == INSN
&& GET_CODE (PATTERN (i1
)) == USE
)
7893 n_occurrences
+= rtx_equal_p (reg
, XEXP (PATTERN (i1
), 0)) != 0;
7894 i1
= NEXT_INSN (i1
);
7896 if (n_occurrences
<= n_inherited
&& i1
== insn
)
7902 /* The caller has already checked that REG dies or is set in INSN.
7903 It has also checked that we are optimizing, and thus some inaccurancies
7904 in the debugging information are acceptable.
7905 So we could just delete output_reload_insn.
7906 But in some cases we can improve the debugging information without
7907 sacrificing optimization - maybe even improving the code:
7908 See if the pseudo reg has been completely replaced
7909 with reload regs. If so, delete the store insn
7910 and forget we had a stack slot for the pseudo. */
7911 if (reload_out
[j
] != reload_in
[j
]
7912 && REG_N_DEATHS (REGNO (reg
)) == 1
7913 && REG_N_SETS (REGNO (reg
)) == 1
7914 && REG_BASIC_BLOCK (REGNO (reg
)) >= 0
7915 && find_regno_note (insn
, REG_DEAD
, REGNO (reg
)))
7919 /* We know that it was used only between here
7920 and the beginning of the current basic block.
7921 (We also know that the last use before INSN was
7922 the output reload we are thinking of deleting, but never mind that.)
7923 Search that range; see if any ref remains. */
7924 for (i2
= PREV_INSN (insn
); i2
; i2
= PREV_INSN (i2
))
7926 rtx set
= single_set (i2
);
7928 /* Uses which just store in the pseudo don't count,
7929 since if they are the only uses, they are dead. */
7930 if (set
!= 0 && SET_DEST (set
) == reg
)
7932 if (GET_CODE (i2
) == CODE_LABEL
7933 || GET_CODE (i2
) == JUMP_INSN
)
7935 if ((GET_CODE (i2
) == INSN
|| GET_CODE (i2
) == CALL_INSN
)
7936 && reg_mentioned_p (reg
, PATTERN (i2
)))
7938 /* Some other ref remains; just delete the output reload we
7940 delete_address_reloads (output_reload_insn
, insn
);
7941 PUT_CODE (output_reload_insn
, NOTE
);
7942 NOTE_SOURCE_FILE (output_reload_insn
) = 0;
7943 NOTE_LINE_NUMBER (output_reload_insn
) = NOTE_INSN_DELETED
;
7948 /* Delete the now-dead stores into this pseudo. */
7949 for (i2
= PREV_INSN (insn
); i2
; i2
= PREV_INSN (i2
))
7951 rtx set
= single_set (i2
);
7953 if (set
!= 0 && SET_DEST (set
) == reg
)
7955 delete_address_reloads (i2
, insn
);
7956 /* This might be a basic block head,
7957 thus don't use delete_insn. */
7958 PUT_CODE (i2
, NOTE
);
7959 NOTE_SOURCE_FILE (i2
) = 0;
7960 NOTE_LINE_NUMBER (i2
) = NOTE_INSN_DELETED
;
7962 if (GET_CODE (i2
) == CODE_LABEL
7963 || GET_CODE (i2
) == JUMP_INSN
)
7967 /* For the debugging info,
7968 say the pseudo lives in this reload reg. */
7969 reg_renumber
[REGNO (reg
)] = REGNO (reload_reg_rtx
[j
]);
7970 alter_reg (REGNO (reg
), -1);
7972 delete_address_reloads (output_reload_insn
, insn
);
7973 PUT_CODE (output_reload_insn
, NOTE
);
7974 NOTE_SOURCE_FILE (output_reload_insn
) = 0;
7975 NOTE_LINE_NUMBER (output_reload_insn
) = NOTE_INSN_DELETED
;
7979 /* We are going to delete DEAD_INSN. Recursively delete loads of
7980 reload registers used in DEAD_INSN that are not used till CURRENT_INSN.
7981 CURRENT_INSN is being reloaded, so we have to check its reloads too. */
7983 delete_address_reloads (dead_insn
, current_insn
)
7984 rtx dead_insn
, current_insn
;
7986 rtx set
= single_set (dead_insn
);
7987 rtx set2
, dst
, prev
, next
;
7990 rtx dst
= SET_DEST (set
);
7991 if (GET_CODE (dst
) == MEM
)
7992 delete_address_reloads_1 (dead_insn
, XEXP (dst
, 0), current_insn
);
7994 /* If we deleted the store from a reloaded post_{in,de}c expression,
7995 we can delete the matching adds. */
7996 prev
= PREV_INSN (dead_insn
);
7997 next
= NEXT_INSN (dead_insn
);
7998 if (! prev
|| ! next
)
8000 set
= single_set (next
);
8001 set2
= single_set (prev
);
8003 || GET_CODE (SET_SRC (set
)) != PLUS
|| GET_CODE (SET_SRC (set2
)) != PLUS
8004 || GET_CODE (XEXP (SET_SRC (set
), 1)) != CONST_INT
8005 || GET_CODE (XEXP (SET_SRC (set2
), 1)) != CONST_INT
)
8007 dst
= SET_DEST (set
);
8008 if (! rtx_equal_p (dst
, SET_DEST (set2
))
8009 || ! rtx_equal_p (dst
, XEXP (SET_SRC (set
), 0))
8010 || ! rtx_equal_p (dst
, XEXP (SET_SRC (set2
), 0))
8011 || (INTVAL (XEXP (SET_SRC (set
), 1))
8012 != - INTVAL (XEXP (SET_SRC (set2
), 1))))
8018 /* Subfunction of delete_address_reloads: process registers found in X. */
8020 delete_address_reloads_1 (dead_insn
, x
, current_insn
)
8021 rtx dead_insn
, x
, current_insn
;
8023 rtx prev
, set
, dst
, i2
;
8025 enum rtx_code code
= GET_CODE (x
);
8029 char *fmt
= GET_RTX_FORMAT (code
);
8030 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
8033 delete_address_reloads_1 (dead_insn
, XEXP (x
, i
), current_insn
);
8034 else if (fmt
[i
] == 'E')
8036 for (j
= XVECLEN (x
, i
) - 1; j
>=0; j
--)
8037 delete_address_reloads_1 (dead_insn
, XVECEXP (x
, i
, j
),
8044 if (spill_reg_order
[REGNO (x
)] < 0)
8047 /* Scan backwards for the insn that sets x. This might be a way back due
8049 for (prev
= PREV_INSN (dead_insn
); prev
; prev
= PREV_INSN (prev
))
8051 code
= GET_CODE (prev
);
8052 if (code
== CODE_LABEL
|| code
== JUMP_INSN
)
8054 if (GET_RTX_CLASS (code
) != 'i')
8056 if (reg_set_p (x
, PATTERN (prev
)))
8058 if (reg_referenced_p (x
, PATTERN (prev
)))
8061 if (! prev
|| INSN_UID (prev
) < reload_first_uid
)
8063 /* Check that PREV only sets the reload register. */
8064 set
= single_set (prev
);
8067 dst
= SET_DEST (set
);
8068 if (GET_CODE (dst
) != REG
8069 || ! rtx_equal_p (dst
, x
))
8071 if (! reg_set_p (dst
, PATTERN (dead_insn
)))
8073 /* Check if DST was used in a later insn -
8074 it might have been inherited. */
8075 for (i2
= NEXT_INSN (dead_insn
); i2
; i2
= NEXT_INSN (i2
))
8077 if (GET_CODE (i2
) == CODE_LABEL
)
8079 if (GET_RTX_CLASS (GET_CODE (i2
)) != 'i')
8081 if (reg_referenced_p (dst
, PATTERN (i2
)))
8083 /* If there is a reference to the register in the current insn,
8084 it might be loaded in a non-inherited reload. If no other
8085 reload uses it, that means the register is set before
8087 if (i2
== current_insn
)
8089 for (j
= n_reloads
- 1; j
>= 0; j
--)
8090 if ((reload_reg_rtx
[j
] == dst
&& reload_inherited
[j
])
8091 || reload_override_in
[j
] == dst
)
8093 for (j
= n_reloads
- 1; j
>= 0; j
--)
8094 if (reload_in
[j
] && reload_reg_rtx
[j
] == dst
)
8101 if (GET_CODE (i2
) == JUMP_INSN
)
8103 if (reg_set_p (dst
, PATTERN (i2
)))
8105 /* If DST is still live at CURRENT_INSN, check if it is used for
8107 if (i2
== current_insn
)
8109 for (j
= n_reloads
- 1; j
>= 0; j
--)
8110 if ((reload_reg_rtx
[j
] == dst
&& reload_inherited
[j
])
8111 || reload_override_in
[j
] == dst
)
8113 /* ??? We can't finish the loop here, because dst might be
8114 allocated to a pseudo in this block if no reload in this
8115 block needs any of the clsses containing DST - see
8116 spill_hard_reg. There is no easy way to tell this, so we
8117 have to scan till the end of the basic block. */
8121 delete_address_reloads_1 (prev
, SET_SRC (set
), current_insn
);
8122 reg_reloaded_contents
[REGNO (dst
)] = -1;
8123 /* Can't use delete_insn here because PREV might be a basic block head. */
8124 PUT_CODE (prev
, NOTE
);
8125 NOTE_LINE_NUMBER (prev
) = NOTE_INSN_DELETED
;
8126 NOTE_SOURCE_FILE (prev
) = 0;
8129 /* Output reload-insns to reload VALUE into RELOADREG.
8130 VALUE is an autoincrement or autodecrement RTX whose operand
8131 is a register or memory location;
8132 so reloading involves incrementing that location.
8133 IN is either identical to VALUE, or some cheaper place to reload from.
8135 INC_AMOUNT is the number to increment or decrement by (always positive).
8136 This cannot be deduced from VALUE.
8138 Return the instruction that stores into RELOADREG. */
8141 inc_for_reload (reloadreg
, in
, value
, inc_amount
)
8146 /* REG or MEM to be copied and incremented. */
8147 rtx incloc
= XEXP (value
, 0);
8148 /* Nonzero if increment after copying. */
8149 int post
= (GET_CODE (value
) == POST_DEC
|| GET_CODE (value
) == POST_INC
);
8155 rtx real_in
= in
== value
? XEXP (in
, 0) : in
;
8157 /* No hard register is equivalent to this register after
8158 inc/dec operation. If REG_LAST_RELOAD_REG were non-zero,
8159 we could inc/dec that register as well (maybe even using it for
8160 the source), but I'm not sure it's worth worrying about. */
8161 if (GET_CODE (incloc
) == REG
)
8162 reg_last_reload_reg
[REGNO (incloc
)] = 0;
8164 if (GET_CODE (value
) == PRE_DEC
|| GET_CODE (value
) == POST_DEC
)
8165 inc_amount
= - inc_amount
;
8167 inc
= GEN_INT (inc_amount
);
8169 /* If this is post-increment, first copy the location to the reload reg. */
8170 if (post
&& real_in
!= reloadreg
)
8171 emit_insn (gen_move_insn (reloadreg
, real_in
));
8175 /* See if we can directly increment INCLOC. Use a method similar to
8176 that in gen_reload. */
8178 last
= get_last_insn ();
8179 add_insn
= emit_insn (gen_rtx_SET (VOIDmode
, incloc
,
8180 gen_rtx_PLUS (GET_MODE (incloc
),
8183 code
= recog_memoized (add_insn
);
8186 extract_insn (add_insn
);
8187 if (constrain_operands (1))
8189 /* If this is a pre-increment and we have incremented the value
8190 where it lives, copy the incremented value to RELOADREG to
8191 be used as an address. */
8194 emit_insn (gen_move_insn (reloadreg
, incloc
));
8199 delete_insns_since (last
);
8202 /* If couldn't do the increment directly, must increment in RELOADREG.
8203 The way we do this depends on whether this is pre- or post-increment.
8204 For pre-increment, copy INCLOC to the reload register, increment it
8205 there, then save back. */
8209 if (in
!= reloadreg
)
8210 emit_insn (gen_move_insn (reloadreg
, real_in
));
8211 emit_insn (gen_add2_insn (reloadreg
, inc
));
8212 store
= emit_insn (gen_move_insn (incloc
, reloadreg
));
8217 Because this might be a jump insn or a compare, and because RELOADREG
8218 may not be available after the insn in an input reload, we must do
8219 the incrementation before the insn being reloaded for.
8221 We have already copied IN to RELOADREG. Increment the copy in
8222 RELOADREG, save that back, then decrement RELOADREG so it has
8223 the original value. */
8225 emit_insn (gen_add2_insn (reloadreg
, inc
));
8226 store
= emit_insn (gen_move_insn (incloc
, reloadreg
));
8227 emit_insn (gen_add2_insn (reloadreg
, GEN_INT (-inc_amount
)));
8233 /* Return 1 if we are certain that the constraint-string STRING allows
8234 the hard register REG. Return 0 if we can't be sure of this. */
8237 constraint_accepts_reg_p (string
, reg
)
8242 int regno
= true_regnum (reg
);
8245 /* Initialize for first alternative. */
8247 /* Check that each alternative contains `g' or `r'. */
8249 switch (c
= *string
++)
8252 /* If an alternative lacks `g' or `r', we lose. */
8255 /* If an alternative lacks `g' or `r', we lose. */
8258 /* Initialize for next alternative. */
8263 /* Any general reg wins for this alternative. */
8264 if (TEST_HARD_REG_BIT (reg_class_contents
[(int) GENERAL_REGS
], regno
))
8268 /* Any reg in specified class wins for this alternative. */
8270 enum reg_class
class = REG_CLASS_FROM_LETTER (c
);
8272 if (TEST_HARD_REG_BIT (reg_class_contents
[(int) class], regno
))
8278 /* Return the number of places FIND appears within X, but don't count
8279 an occurrence if some SET_DEST is FIND. */
8282 count_occurrences (x
, find
)
8283 register rtx x
, find
;
8286 register enum rtx_code code
;
8287 register char *format_ptr
;
8295 code
= GET_CODE (x
);
8310 if (GET_CODE (find
) == MEM
&& rtx_equal_p (x
, find
))
8314 if (SET_DEST (x
) == find
)
8315 return count_occurrences (SET_SRC (x
), find
);
8322 format_ptr
= GET_RTX_FORMAT (code
);
8325 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++)
8327 switch (*format_ptr
++)
8330 count
+= count_occurrences (XEXP (x
, i
), find
);
8334 if (XVEC (x
, i
) != NULL
)
8336 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
8337 count
+= count_occurrences (XVECEXP (x
, i
, j
), find
);
8345 /* This array holds values which are equivalent to a hard register
8346 during reload_cse_regs. Each array element is an EXPR_LIST of
8347 values. Each time a hard register is set, we set the corresponding
8348 array element to the value. Each time a hard register is copied
8349 into memory, we add the memory location to the corresponding array
8350 element. We don't store values or memory addresses with side
8351 effects in this array.
8353 If the value is a CONST_INT, then the mode of the containing
8354 EXPR_LIST is the mode in which that CONST_INT was referenced.
8356 We sometimes clobber a specific entry in a list. In that case, we
8357 just set XEXP (list-entry, 0) to 0. */
8359 static rtx
*reg_values
;
8361 /* This is a preallocated REG rtx which we use as a temporary in
8362 reload_cse_invalidate_regno, so that we don't need to allocate a
8363 new one each time through a loop in that function. */
8365 static rtx invalidate_regno_rtx
;
8367 /* Invalidate any entries in reg_values which depend on REGNO,
8368 including those for REGNO itself. This is called if REGNO is
8369 changing. If CLOBBER is true, then always forget anything we
8370 currently know about REGNO. MODE is the mode of the assignment to
8371 REGNO, which is used to determine how many hard registers are being
8372 changed. If MODE is VOIDmode, then only REGNO is being changed;
8373 this is used when invalidating call clobbered registers across a
8377 reload_cse_invalidate_regno (regno
, mode
, clobber
)
8379 enum machine_mode mode
;
8385 /* Our callers don't always go through true_regnum; we may see a
8386 pseudo-register here from a CLOBBER or the like. We probably
8387 won't ever see a pseudo-register that has a real register number,
8388 for we check anyhow for safety. */
8389 if (regno
>= FIRST_PSEUDO_REGISTER
)
8390 regno
= reg_renumber
[regno
];
8394 if (mode
== VOIDmode
)
8395 endregno
= regno
+ 1;
8397 endregno
= regno
+ HARD_REGNO_NREGS (regno
, mode
);
8400 for (i
= regno
; i
< endregno
; i
++)
8403 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
8407 for (x
= reg_values
[i
]; x
; x
= XEXP (x
, 1))
8409 if (XEXP (x
, 0) != 0
8410 && refers_to_regno_p (regno
, endregno
, XEXP (x
, 0), NULL_PTR
))
8412 /* If this is the only entry on the list, clear
8413 reg_values[i]. Otherwise, just clear this entry on
8415 if (XEXP (x
, 1) == 0 && x
== reg_values
[i
])
8425 /* We must look at earlier registers, in case REGNO is part of a
8426 multi word value but is not the first register. If an earlier
8427 register has a value in a mode which overlaps REGNO, then we must
8428 invalidate that earlier register. Note that we do not need to
8429 check REGNO or later registers (we must not check REGNO itself,
8430 because we would incorrectly conclude that there was a conflict). */
8432 for (i
= 0; i
< regno
; i
++)
8436 for (x
= reg_values
[i
]; x
; x
= XEXP (x
, 1))
8438 if (XEXP (x
, 0) != 0)
8440 PUT_MODE (invalidate_regno_rtx
, GET_MODE (x
));
8441 REGNO (invalidate_regno_rtx
) = i
;
8442 if (refers_to_regno_p (regno
, endregno
, invalidate_regno_rtx
,
8445 reload_cse_invalidate_regno (i
, VOIDmode
, 1);
8453 /* The memory at address MEM_BASE is being changed.
8454 Return whether this change will invalidate VAL. */
8457 reload_cse_mem_conflict_p (mem_base
, val
)
8465 code
= GET_CODE (val
);
8468 /* Get rid of a few simple cases quickly. */
8481 if (GET_MODE (mem_base
) == BLKmode
8482 || GET_MODE (val
) == BLKmode
)
8484 if (anti_dependence (val
, mem_base
))
8486 /* The address may contain nested MEMs. */
8493 fmt
= GET_RTX_FORMAT (code
);
8495 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
8499 if (reload_cse_mem_conflict_p (mem_base
, XEXP (val
, i
)))
8502 else if (fmt
[i
] == 'E')
8506 for (j
= 0; j
< XVECLEN (val
, i
); j
++)
8507 if (reload_cse_mem_conflict_p (mem_base
, XVECEXP (val
, i
, j
)))
8515 /* Invalidate any entries in reg_values which are changed because of a
8516 store to MEM_RTX. If this is called because of a non-const call
8517 instruction, MEM_RTX is (mem:BLK const0_rtx). */
8520 reload_cse_invalidate_mem (mem_rtx
)
8525 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
8529 for (x
= reg_values
[i
]; x
; x
= XEXP (x
, 1))
8531 if (XEXP (x
, 0) != 0
8532 && reload_cse_mem_conflict_p (mem_rtx
, XEXP (x
, 0)))
8534 /* If this is the only entry on the list, clear
8535 reg_values[i]. Otherwise, just clear this entry on
8537 if (XEXP (x
, 1) == 0 && x
== reg_values
[i
])
8548 /* Invalidate DEST, which is being assigned to or clobbered. The
8549 second parameter exists so that this function can be passed to
8550 note_stores; it is ignored. */
8553 reload_cse_invalidate_rtx (dest
, ignore
)
8555 rtx ignore ATTRIBUTE_UNUSED
;
8557 while (GET_CODE (dest
) == STRICT_LOW_PART
8558 || GET_CODE (dest
) == SIGN_EXTRACT
8559 || GET_CODE (dest
) == ZERO_EXTRACT
8560 || GET_CODE (dest
) == SUBREG
)
8561 dest
= XEXP (dest
, 0);
8563 if (GET_CODE (dest
) == REG
)
8564 reload_cse_invalidate_regno (REGNO (dest
), GET_MODE (dest
), 1);
8565 else if (GET_CODE (dest
) == MEM
)
8566 reload_cse_invalidate_mem (dest
);
8569 /* Do a very simple CSE pass over the hard registers.
8571 This function detects no-op moves where we happened to assign two
8572 different pseudo-registers to the same hard register, and then
8573 copied one to the other. Reload will generate a useless
8574 instruction copying a register to itself.
8576 This function also detects cases where we load a value from memory
8577 into two different registers, and (if memory is more expensive than
8578 registers) changes it to simply copy the first register into the
8581 Another optimization is performed that scans the operands of each
8582 instruction to see whether the value is already available in a
8583 hard register. It then replaces the operand with the hard register
8584 if possible, much like an optional reload would. */
8587 reload_cse_regs_1 (first
)
8595 init_alias_analysis ();
8597 reg_values
= (rtx
*) alloca (FIRST_PSEUDO_REGISTER
* sizeof (rtx
));
8598 bzero ((char *)reg_values
, FIRST_PSEUDO_REGISTER
* sizeof (rtx
));
8600 /* Create our EXPR_LIST structures on reload_obstack, so that we can
8601 free them when we are done. */
8602 push_obstacks (&reload_obstack
, &reload_obstack
);
8603 firstobj
= (char *) obstack_alloc (&reload_obstack
, 0);
8605 /* We pass this to reload_cse_invalidate_mem to invalidate all of
8606 memory for a non-const call instruction. */
8607 callmem
= gen_rtx_MEM (BLKmode
, const0_rtx
);
8609 /* This is used in reload_cse_invalidate_regno to avoid consing a
8610 new REG in a loop in that function. */
8611 invalidate_regno_rtx
= gen_rtx_REG (VOIDmode
, 0);
8613 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
8617 if (GET_CODE (insn
) == CODE_LABEL
)
8619 /* Forget all the register values at a code label. We don't
8620 try to do anything clever around jumps. */
8621 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
8627 #ifdef NON_SAVING_SETJMP
8628 if (NON_SAVING_SETJMP
&& GET_CODE (insn
) == NOTE
8629 && NOTE_LINE_NUMBER (insn
) == NOTE_INSN_SETJMP
)
8631 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
8638 if (GET_RTX_CLASS (GET_CODE (insn
)) != 'i')
8641 /* If this is a call instruction, forget anything stored in a
8642 call clobbered register, or, if this is not a const call, in
8644 if (GET_CODE (insn
) == CALL_INSN
)
8646 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
8647 if (call_used_regs
[i
])
8648 reload_cse_invalidate_regno (i
, VOIDmode
, 1);
8650 if (! CONST_CALL_P (insn
))
8651 reload_cse_invalidate_mem (callmem
);
8654 body
= PATTERN (insn
);
8655 if (GET_CODE (body
) == SET
)
8658 if (reload_cse_noop_set_p (body
, insn
))
8660 /* If this sets the return value of the function, we must keep
8661 a USE around, in case this is in a different basic block
8662 than the final USE. Otherwise, we could loose important
8663 register lifeness information on SMALL_REGISTER_CLASSES
8664 machines, where return registers might be used as spills:
8665 subsequent passes assume that spill registers are dead at
8666 the end of a basic block. */
8667 if (REG_FUNCTION_VALUE_P (SET_DEST (body
)))
8670 PATTERN (insn
) = gen_rtx_USE (VOIDmode
, SET_DEST (body
));
8671 INSN_CODE (insn
) = -1;
8672 REG_NOTES (insn
) = NULL_RTX
;
8673 push_obstacks (&reload_obstack
, &reload_obstack
);
8677 PUT_CODE (insn
, NOTE
);
8678 NOTE_LINE_NUMBER (insn
) = NOTE_INSN_DELETED
;
8679 NOTE_SOURCE_FILE (insn
) = 0;
8682 /* We're done with this insn. */
8686 /* It's not a no-op, but we can try to simplify it. */
8687 count
+= reload_cse_simplify_set (body
, insn
);
8690 apply_change_group ();
8691 else if (asm_noperands (PATTERN (insn
)) < 0)
8692 reload_cse_simplify_operands (insn
);
8694 reload_cse_record_set (body
, body
);
8696 else if (GET_CODE (body
) == PARALLEL
)
8699 rtx value
= NULL_RTX
;
8701 /* If every action in a PARALLEL is a noop, we can delete
8702 the entire PARALLEL. */
8703 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; --i
)
8705 rtx part
= XVECEXP (body
, 0, i
);
8706 if (GET_CODE (part
) == SET
)
8708 if (! reload_cse_noop_set_p (part
, insn
))
8710 if (REG_FUNCTION_VALUE_P (SET_DEST (part
)))
8714 value
= SET_DEST (part
);
8717 else if (GET_CODE (part
) != CLOBBER
)
8725 PATTERN (insn
) = gen_rtx_USE (VOIDmode
, value
);
8726 INSN_CODE (insn
) = -1;
8727 REG_NOTES (insn
) = NULL_RTX
;
8728 push_obstacks (&reload_obstack
, &reload_obstack
);
8732 PUT_CODE (insn
, NOTE
);
8733 NOTE_LINE_NUMBER (insn
) = NOTE_INSN_DELETED
;
8734 NOTE_SOURCE_FILE (insn
) = 0;
8737 /* We're done with this insn. */
8741 /* It's not a no-op, but we can try to simplify it. */
8742 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; --i
)
8743 if (GET_CODE (XVECEXP (body
, 0, i
)) == SET
)
8744 count
+= reload_cse_simplify_set (XVECEXP (body
, 0, i
), insn
);
8747 apply_change_group ();
8748 else if (asm_noperands (PATTERN (insn
)) < 0)
8749 reload_cse_simplify_operands (insn
);
8751 /* Look through the PARALLEL and record the values being
8752 set, if possible. Also handle any CLOBBERs. */
8753 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; --i
)
8755 rtx x
= XVECEXP (body
, 0, i
);
8757 if (GET_CODE (x
) == SET
)
8758 reload_cse_record_set (x
, body
);
8760 note_stores (x
, reload_cse_invalidate_rtx
);
8764 note_stores (body
, reload_cse_invalidate_rtx
);
8767 /* Clobber any registers which appear in REG_INC notes. We
8768 could keep track of the changes to their values, but it is
8769 unlikely to help. */
8773 for (x
= REG_NOTES (insn
); x
; x
= XEXP (x
, 1))
8774 if (REG_NOTE_KIND (x
) == REG_INC
)
8775 reload_cse_invalidate_rtx (XEXP (x
, 0), NULL_RTX
);
8779 /* Look for any CLOBBERs in CALL_INSN_FUNCTION_USAGE, but only
8780 after we have processed the insn. */
8781 if (GET_CODE (insn
) == CALL_INSN
)
8785 for (x
= CALL_INSN_FUNCTION_USAGE (insn
); x
; x
= XEXP (x
, 1))
8786 if (GET_CODE (XEXP (x
, 0)) == CLOBBER
)
8787 reload_cse_invalidate_rtx (XEXP (XEXP (x
, 0), 0), NULL_RTX
);
8791 /* Free all the temporary structures we created, and go back to the
8792 regular obstacks. */
8793 obstack_free (&reload_obstack
, firstobj
);
8797 /* Call cse / combine like post-reload optimization phases.
8798 FIRST is the first instruction. */
8800 reload_cse_regs (first
)
8803 reload_cse_regs_1 (first
);
8805 reload_cse_move2add (first
);
8806 if (flag_expensive_optimizations
)
8807 reload_cse_regs_1 (first
);
8810 /* Return whether the values known for REGNO are equal to VAL. MODE
8811 is the mode of the object that VAL is being copied to; this matters
8812 if VAL is a CONST_INT. */
8815 reload_cse_regno_equal_p (regno
, val
, mode
)
8818 enum machine_mode mode
;
8825 for (x
= reg_values
[regno
]; x
; x
= XEXP (x
, 1))
8826 if (XEXP (x
, 0) != 0
8827 && rtx_equal_p (XEXP (x
, 0), val
)
8828 && (! flag_float_store
|| GET_CODE (XEXP (x
, 0)) != MEM
8829 || GET_MODE_CLASS (GET_MODE (x
)) != MODE_FLOAT
)
8830 && (GET_CODE (val
) != CONST_INT
8831 || mode
== GET_MODE (x
)
8832 || (GET_MODE_SIZE (mode
) < GET_MODE_SIZE (GET_MODE (x
))
8833 /* On a big endian machine if the value spans more than
8834 one register then this register holds the high part of
8835 it and we can't use it.
8837 ??? We should also compare with the high part of the
8839 && !(WORDS_BIG_ENDIAN
8840 && HARD_REGNO_NREGS (regno
, GET_MODE (x
)) > 1)
8841 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode
),
8842 GET_MODE_BITSIZE (GET_MODE (x
))))))
8848 /* See whether a single set is a noop. SET is the set instruction we
8849 are should check, and INSN is the instruction from which it came. */
8852 reload_cse_noop_set_p (set
, insn
)
8857 enum machine_mode dest_mode
;
8861 src
= SET_SRC (set
);
8862 dest
= SET_DEST (set
);
8863 dest_mode
= GET_MODE (dest
);
8865 if (side_effects_p (src
))
8868 dreg
= true_regnum (dest
);
8869 sreg
= true_regnum (src
);
8871 /* Check for setting a register to itself. In this case, we don't
8872 have to worry about REG_DEAD notes. */
8873 if (dreg
>= 0 && dreg
== sreg
)
8879 /* Check for setting a register to itself. */
8883 /* Check for setting a register to a value which we already know
8884 is in the register. */
8885 else if (reload_cse_regno_equal_p (dreg
, src
, dest_mode
))
8888 /* Check for setting a register DREG to another register SREG
8889 where SREG is equal to a value which is already in DREG. */
8894 for (x
= reg_values
[sreg
]; x
; x
= XEXP (x
, 1))
8898 if (XEXP (x
, 0) == 0)
8901 if (dest_mode
== GET_MODE (x
))
8903 else if (GET_MODE_BITSIZE (dest_mode
)
8904 < GET_MODE_BITSIZE (GET_MODE (x
)))
8905 tmp
= gen_lowpart_common (dest_mode
, XEXP (x
, 0));
8910 && reload_cse_regno_equal_p (dreg
, tmp
, dest_mode
))
8918 else if (GET_CODE (dest
) == MEM
)
8920 /* Check for storing a register to memory when we know that the
8921 register is equivalent to the memory location. */
8923 && reload_cse_regno_equal_p (sreg
, dest
, dest_mode
)
8924 && ! side_effects_p (dest
))
8931 /* Try to simplify a single SET instruction. SET is the set pattern.
8932 INSN is the instruction it came from.
8933 This function only handles one case: if we set a register to a value
8934 which is not a register, we try to find that value in some other register
8935 and change the set into a register copy. */
8938 reload_cse_simplify_set (set
, insn
)
8944 enum machine_mode dest_mode
;
8945 enum reg_class dclass
;
8948 dreg
= true_regnum (SET_DEST (set
));
8952 src
= SET_SRC (set
);
8953 if (side_effects_p (src
) || true_regnum (src
) >= 0)
8956 dclass
= REGNO_REG_CLASS (dreg
);
8958 /* If memory loads are cheaper than register copies, don't change them. */
8959 if (GET_CODE (src
) == MEM
8960 && MEMORY_MOVE_COST (GET_MODE (src
), dclass
, 1) < 2)
8963 /* If the constant is cheaper than a register, don't change it. */
8964 if (CONSTANT_P (src
)
8965 && rtx_cost (src
, SET
) < 2)
8968 dest_mode
= GET_MODE (SET_DEST (set
));
8969 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
8972 && REGISTER_MOVE_COST (REGNO_REG_CLASS (i
), dclass
) == 2
8973 && reload_cse_regno_equal_p (i
, src
, dest_mode
))
8977 /* Pop back to the real obstacks while changing the insn. */
8980 validated
= validate_change (insn
, &SET_SRC (set
),
8981 gen_rtx_REG (dest_mode
, i
), 1);
8983 /* Go back to the obstack we are using for temporary
8985 push_obstacks (&reload_obstack
, &reload_obstack
);
8994 /* Try to replace operands in INSN with equivalent values that are already
8995 in registers. This can be viewed as optional reloading.
8997 For each non-register operand in the insn, see if any hard regs are
8998 known to be equivalent to that operand. Record the alternatives which
8999 can accept these hard registers. Among all alternatives, select the
9000 ones which are better or equal to the one currently matching, where
9001 "better" is in terms of '?' and '!' constraints. Among the remaining
9002 alternatives, select the one which replaces most operands with
9006 reload_cse_simplify_operands (insn
)
9009 #ifdef REGISTER_CONSTRAINTS
9012 char *constraints
[MAX_RECOG_OPERANDS
];
9014 /* Vector recording how bad an alternative is. */
9015 int *alternative_reject
;
9016 /* Vector recording how many registers can be introduced by choosing
9017 this alternative. */
9018 int *alternative_nregs
;
9019 /* Array of vectors recording, for each operand and each alternative,
9020 which hard register to substitute, or -1 if the operand should be
9022 int *op_alt_regno
[MAX_RECOG_OPERANDS
];
9023 /* Array of alternatives, sorted in order of decreasing desirability. */
9024 int *alternative_order
;
9025 rtx reg
= gen_rtx_REG (VOIDmode
, -1);
9027 extract_insn (insn
);
9029 if (recog_n_alternatives
== 0 || recog_n_operands
== 0)
9032 /* Figure out which alternative currently matches. */
9033 if (! constrain_operands (1))
9034 fatal_insn_not_found (insn
);
9036 alternative_reject
= (int *) alloca (recog_n_alternatives
* sizeof (int));
9037 alternative_nregs
= (int *) alloca (recog_n_alternatives
* sizeof (int));
9038 alternative_order
= (int *) alloca (recog_n_alternatives
* sizeof (int));
9039 bzero ((char *)alternative_reject
, recog_n_alternatives
* sizeof (int));
9040 bzero ((char *)alternative_nregs
, recog_n_alternatives
* sizeof (int));
9042 for (i
= 0; i
< recog_n_operands
; i
++)
9044 enum machine_mode mode
;
9048 op_alt_regno
[i
] = (int *) alloca (recog_n_alternatives
* sizeof (int));
9049 for (j
= 0; j
< recog_n_alternatives
; j
++)
9050 op_alt_regno
[i
][j
] = -1;
9052 p
= constraints
[i
] = recog_constraints
[i
];
9053 mode
= recog_operand_mode
[i
];
9055 /* Add the reject values for each alternative given by the constraints
9056 for this operand. */
9064 alternative_reject
[j
] += 3;
9066 alternative_reject
[j
] += 300;
9069 /* We won't change operands which are already registers. We
9070 also don't want to modify output operands. */
9071 regno
= true_regnum (recog_operand
[i
]);
9073 || constraints
[i
][0] == '='
9074 || constraints
[i
][0] == '+')
9077 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
9079 int class = (int) NO_REGS
;
9081 if (! reload_cse_regno_equal_p (regno
, recog_operand
[i
], mode
))
9084 REGNO (reg
) = regno
;
9085 PUT_MODE (reg
, mode
);
9087 /* We found a register equal to this operand. Now look for all
9088 alternatives that can accept this register and have not been
9089 assigned a register they can use yet. */
9098 case '=': case '+': case '?':
9099 case '#': case '&': case '!':
9101 case '0': case '1': case '2': case '3': case '4':
9102 case 'm': case '<': case '>': case 'V': case 'o':
9103 case 'E': case 'F': case 'G': case 'H':
9104 case 's': case 'i': case 'n':
9105 case 'I': case 'J': case 'K': case 'L':
9106 case 'M': case 'N': case 'O': case 'P':
9107 #ifdef EXTRA_CONSTRAINT
9108 case 'Q': case 'R': case 'S': case 'T': case 'U':
9111 /* These don't say anything we care about. */
9115 class = reg_class_subunion
[(int) class][(int) GENERAL_REGS
];
9120 = reg_class_subunion
[(int) class][(int) REG_CLASS_FROM_LETTER ((unsigned char)c
)];
9123 case ',': case '\0':
9124 /* See if REGNO fits this alternative, and set it up as the
9125 replacement register if we don't have one for this
9126 alternative yet and the operand being replaced is not
9127 a cheap CONST_INT. */
9128 if (op_alt_regno
[i
][j
] == -1
9129 && reg_fits_class_p (reg
, class, 0, mode
)
9130 && (GET_CODE (recog_operand
[i
]) != CONST_INT
9131 || rtx_cost (recog_operand
[i
], SET
) > rtx_cost (reg
, SET
)))
9133 alternative_nregs
[j
]++;
9134 op_alt_regno
[i
][j
] = regno
;
9146 /* Record all alternatives which are better or equal to the currently
9147 matching one in the alternative_order array. */
9148 for (i
= j
= 0; i
< recog_n_alternatives
; i
++)
9149 if (alternative_reject
[i
] <= alternative_reject
[which_alternative
])
9150 alternative_order
[j
++] = i
;
9151 recog_n_alternatives
= j
;
9153 /* Sort it. Given a small number of alternatives, a dumb algorithm
9154 won't hurt too much. */
9155 for (i
= 0; i
< recog_n_alternatives
- 1; i
++)
9158 int best_reject
= alternative_reject
[alternative_order
[i
]];
9159 int best_nregs
= alternative_nregs
[alternative_order
[i
]];
9162 for (j
= i
+ 1; j
< recog_n_alternatives
; j
++)
9164 int this_reject
= alternative_reject
[alternative_order
[j
]];
9165 int this_nregs
= alternative_nregs
[alternative_order
[j
]];
9167 if (this_reject
< best_reject
9168 || (this_reject
== best_reject
&& this_nregs
< best_nregs
))
9171 best_reject
= this_reject
;
9172 best_nregs
= this_nregs
;
9176 tmp
= alternative_order
[best
];
9177 alternative_order
[best
] = alternative_order
[i
];
9178 alternative_order
[i
] = tmp
;
9181 /* Substitute the operands as determined by op_alt_regno for the best
9183 j
= alternative_order
[0];
9185 /* Pop back to the real obstacks while changing the insn. */
9188 for (i
= 0; i
< recog_n_operands
; i
++)
9190 enum machine_mode mode
= recog_operand_mode
[i
];
9191 if (op_alt_regno
[i
][j
] == -1)
9194 validate_change (insn
, recog_operand_loc
[i
],
9195 gen_rtx_REG (mode
, op_alt_regno
[i
][j
]), 1);
9198 for (i
= recog_n_dups
- 1; i
>= 0; i
--)
9200 int op
= recog_dup_num
[i
];
9201 enum machine_mode mode
= recog_operand_mode
[op
];
9203 if (op_alt_regno
[op
][j
] == -1)
9206 validate_change (insn
, recog_dup_loc
[i
],
9207 gen_rtx_REG (mode
, op_alt_regno
[op
][j
]), 1);
9210 /* Go back to the obstack we are using for temporary
9212 push_obstacks (&reload_obstack
, &reload_obstack
);
9214 return apply_change_group ();
9220 /* These two variables are used to pass information from
9221 reload_cse_record_set to reload_cse_check_clobber. */
9223 static int reload_cse_check_clobbered
;
9224 static rtx reload_cse_check_src
;
9226 /* See if DEST overlaps with RELOAD_CSE_CHECK_SRC. If it does, set
9227 RELOAD_CSE_CHECK_CLOBBERED. This is called via note_stores. The
9228 second argument, which is passed by note_stores, is ignored. */
9231 reload_cse_check_clobber (dest
, ignore
)
9233 rtx ignore ATTRIBUTE_UNUSED
;
9235 if (reg_overlap_mentioned_p (dest
, reload_cse_check_src
))
9236 reload_cse_check_clobbered
= 1;
9239 /* Record the result of a SET instruction. SET is the set pattern.
9240 BODY is the pattern of the insn that it came from. */
9243 reload_cse_record_set (set
, body
)
9249 enum machine_mode dest_mode
;
9251 dest
= SET_DEST (set
);
9252 src
= SET_SRC (set
);
9253 dreg
= true_regnum (dest
);
9254 sreg
= true_regnum (src
);
9255 dest_mode
= GET_MODE (dest
);
9257 /* Some machines don't define AUTO_INC_DEC, but they still use push
9258 instructions. We need to catch that case here in order to
9259 invalidate the stack pointer correctly. Note that invalidating
9260 the stack pointer is different from invalidating DEST. */
9262 while (GET_CODE (x
) == SUBREG
9263 || GET_CODE (x
) == ZERO_EXTRACT
9264 || GET_CODE (x
) == SIGN_EXTRACT
9265 || GET_CODE (x
) == STRICT_LOW_PART
)
9267 if (push_operand (x
, GET_MODE (x
)))
9269 reload_cse_invalidate_rtx (stack_pointer_rtx
, NULL_RTX
);
9270 reload_cse_invalidate_rtx (dest
, NULL_RTX
);
9274 /* We can only handle an assignment to a register, or a store of a
9275 register to a memory location. For other cases, we just clobber
9276 the destination. We also have to just clobber if there are side
9277 effects in SRC or DEST. */
9278 if ((dreg
< 0 && GET_CODE (dest
) != MEM
)
9279 || side_effects_p (src
)
9280 || side_effects_p (dest
))
9282 reload_cse_invalidate_rtx (dest
, NULL_RTX
);
9287 /* We don't try to handle values involving CC, because it's a pain
9288 to keep track of when they have to be invalidated. */
9289 if (reg_mentioned_p (cc0_rtx
, src
)
9290 || reg_mentioned_p (cc0_rtx
, dest
))
9292 reload_cse_invalidate_rtx (dest
, NULL_RTX
);
9297 /* If BODY is a PARALLEL, then we need to see whether the source of
9298 SET is clobbered by some other instruction in the PARALLEL. */
9299 if (GET_CODE (body
) == PARALLEL
)
9303 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; --i
)
9307 x
= XVECEXP (body
, 0, i
);
9311 reload_cse_check_clobbered
= 0;
9312 reload_cse_check_src
= src
;
9313 note_stores (x
, reload_cse_check_clobber
);
9314 if (reload_cse_check_clobbered
)
9316 reload_cse_invalidate_rtx (dest
, NULL_RTX
);
9326 /* This is an assignment to a register. Update the value we
9327 have stored for the register. */
9332 /* This is a copy from one register to another. Any values
9333 which were valid for SREG are now valid for DREG. If the
9334 mode changes, we use gen_lowpart_common to extract only
9335 the part of the value that is copied. */
9336 reg_values
[dreg
] = 0;
9337 for (x
= reg_values
[sreg
]; x
; x
= XEXP (x
, 1))
9341 if (XEXP (x
, 0) == 0)
9343 if (dest_mode
== GET_MODE (XEXP (x
, 0)))
9345 else if (GET_MODE_BITSIZE (dest_mode
)
9346 > GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))))
9349 tmp
= gen_lowpart_common (dest_mode
, XEXP (x
, 0));
9351 reg_values
[dreg
] = gen_rtx_EXPR_LIST (dest_mode
, tmp
,
9356 reg_values
[dreg
] = gen_rtx_EXPR_LIST (dest_mode
, src
, NULL_RTX
);
9358 /* We've changed DREG, so invalidate any values held by other
9359 registers that depend upon it. */
9360 reload_cse_invalidate_regno (dreg
, dest_mode
, 0);
9362 /* If this assignment changes more than one hard register,
9363 forget anything we know about the others. */
9364 for (i
= 1; i
< HARD_REGNO_NREGS (dreg
, dest_mode
); i
++)
9365 reg_values
[dreg
+ i
] = 0;
9367 else if (GET_CODE (dest
) == MEM
)
9369 /* Invalidate conflicting memory locations. */
9370 reload_cse_invalidate_mem (dest
);
9372 /* If we're storing a register to memory, add DEST to the list
9374 if (sreg
>= 0 && ! side_effects_p (dest
))
9375 reg_values
[sreg
] = gen_rtx_EXPR_LIST (dest_mode
, dest
,
9380 /* We should have bailed out earlier. */
9385 /* If reload couldn't use reg+reg+offset addressing, try to use reg+reg
9387 This code might also be useful when reload gave up on reg+reg addresssing
9388 because of clashes between the return register and INDEX_REG_CLASS. */
9390 /* The maximum number of uses of a register we can keep track of to
9391 replace them with reg+reg addressing. */
9392 #define RELOAD_COMBINE_MAX_USES 6
9394 /* INSN is the insn where a register has ben used, and USEP points to the
9395 location of the register within the rtl. */
9396 struct reg_use
{ rtx insn
, *usep
; };
9398 /* If the register is used in some unknown fashion, USE_INDEX is negative.
9399 If it is dead, USE_INDEX is RELOAD_COMBINE_MAX_USES, and STORE_RUID
9400 indicates where it becomes live again.
9401 Otherwise, USE_INDEX is the index of the last encountered use of the
9402 register (which is first among these we have seen since we scan backwards),
9403 OFFSET contains the constant offset that is added to the register in
9404 all encountered uses, and USE_RUID indicates the first encountered, i.e.
9405 last, of these uses.
9406 STORE_RUID is always meaningful if we only want to use a value in a
9407 register in a different place: it denotes the next insn in the insn
9408 stream (i.e. the last ecountered) that sets or clobbers the register. */
9411 struct reg_use reg_use
[RELOAD_COMBINE_MAX_USES
];
9416 } reg_state
[FIRST_PSEUDO_REGISTER
];
9418 /* Reverse linear uid. This is increased in reload_combine while scanning
9419 the instructions from last to first. It is used to set last_label_ruid
9420 and the store_ruid / use_ruid fields in reg_state. */
9421 static int reload_combine_ruid
;
9423 #define LABEL_LIVE(LABEL) \
9424 (label_live[CODE_LABEL_NUMBER (LABEL) - min_labelno])
9430 int first_index_reg
= 1, last_index_reg
= 0;
9432 int last_label_ruid
;
9433 int min_labelno
, n_labels
;
9434 HARD_REG_SET ever_live_at_start
, *label_live
;
9436 /* If reg+reg can be used in offsetable memory adresses, the main chunk of
9437 reload has already used it where appropriate, so there is no use in
9438 trying to generate it now. */
9439 if (double_reg_address_ok
&& INDEX_REG_CLASS
!= NO_REGS
)
9442 /* To avoid wasting too much time later searching for an index register,
9443 determine the minimum and maximum index register numbers. */
9444 for (i
= FIRST_PSEUDO_REGISTER
- 1; i
>= 0; --i
)
9446 if (TEST_HARD_REG_BIT (reg_class_contents
[INDEX_REG_CLASS
], i
))
9448 if (! last_index_reg
)
9450 first_index_reg
= i
;
9453 /* If no index register is available, we can quit now. */
9454 if (first_index_reg
> last_index_reg
)
9457 /* Set up LABEL_LIVE and EVER_LIVE_AT_START. The register lifetime
9458 information is a bit fuzzy immediately after reload, but it's
9459 still good enough to determine which registers are live at a jump
9461 min_labelno
= get_first_label_num ();
9462 n_labels
= max_label_num () - min_labelno
;
9463 label_live
= (HARD_REG_SET
*) xmalloc (n_labels
* sizeof (HARD_REG_SET
));
9464 CLEAR_HARD_REG_SET (ever_live_at_start
);
9465 for (i
= n_basic_blocks
- 1; i
>= 0; i
--)
9467 insn
= BLOCK_HEAD (i
);
9468 if (GET_CODE (insn
) == CODE_LABEL
)
9472 REG_SET_TO_HARD_REG_SET (live
, basic_block_live_at_start
[i
]);
9473 compute_use_by_pseudos (&live
, basic_block_live_at_start
[i
]);
9474 COPY_HARD_REG_SET (LABEL_LIVE (insn
), live
);
9475 IOR_HARD_REG_SET (ever_live_at_start
, live
);
9479 /* Initialize last_label_ruid, reload_combine_ruid and reg_state. */
9480 last_label_ruid
= reload_combine_ruid
= 0;
9481 for (i
= FIRST_PSEUDO_REGISTER
- 1; i
>= 0; --i
)
9483 reg_state
[i
].store_ruid
= reload_combine_ruid
;
9485 reg_state
[i
].use_index
= -1;
9487 reg_state
[i
].use_index
= RELOAD_COMBINE_MAX_USES
;
9490 for (insn
= get_last_insn (); insn
; insn
= PREV_INSN (insn
))
9494 /* We cannot do our optimization across labels. Invalidating all the use
9495 information we have would be costly, so we just note where the label
9496 is and then later disable any optimization that would cross it. */
9497 if (GET_CODE (insn
) == CODE_LABEL
)
9498 last_label_ruid
= reload_combine_ruid
;
9499 if (GET_CODE (insn
) == BARRIER
)
9501 for (i
= FIRST_PSEUDO_REGISTER
- 1; i
>= 0; --i
)
9502 reg_state
[i
].use_index
= RELOAD_COMBINE_MAX_USES
;
9504 if (GET_RTX_CLASS (GET_CODE (insn
)) != 'i')
9506 reload_combine_ruid
++;
9508 /* Look for (set (REGX) (CONST_INT))
9509 (set (REGX) (PLUS (REGX) (REGY)))
9511 ... (MEM (REGX)) ...
9513 (set (REGZ) (CONST_INT))
9515 ... (MEM (PLUS (REGZ) (REGY)))... .
9517 First, check that we have (set (REGX) (PLUS (REGX) (REGY)))
9518 and that we know all uses of REGX before it dies. */
9519 set
= single_set (insn
);
9521 && GET_CODE (SET_DEST (set
)) == REG
9522 && (HARD_REGNO_NREGS (REGNO (SET_DEST (set
)),
9523 GET_MODE (SET_DEST (set
)))
9525 && GET_CODE (SET_SRC (set
)) == PLUS
9526 && GET_CODE (XEXP (SET_SRC (set
), 1)) == REG
9527 && rtx_equal_p (XEXP (SET_SRC (set
), 0), SET_DEST (set
))
9528 && last_label_ruid
< reg_state
[REGNO (SET_DEST (set
))].use_ruid
)
9530 rtx reg
= SET_DEST (set
);
9531 rtx plus
= SET_SRC (set
);
9532 rtx base
= XEXP (plus
, 1);
9533 rtx prev
= prev_nonnote_insn (insn
);
9534 rtx prev_set
= prev
? single_set (prev
) : NULL_RTX
;
9535 int regno
= REGNO (reg
);
9537 rtx reg_sum
= NULL_RTX
;
9539 /* Now, we need an index register.
9540 We'll set index_reg to this index register, const_reg to the
9541 register that is to be loaded with the constant
9542 (denoted as REGZ in the substitution illustration above),
9543 and reg_sum to the register-register that we want to use to
9544 substitute uses of REG (typically in MEMs) with.
9545 First check REG and BASE for being index registers;
9546 we can use them even if they are not dead. */
9547 if (TEST_HARD_REG_BIT (reg_class_contents
[INDEX_REG_CLASS
], regno
)
9548 || TEST_HARD_REG_BIT (reg_class_contents
[INDEX_REG_CLASS
],
9556 /* Otherwise, look for a free index register. Since we have
9557 checked above that neiter REG nor BASE are index registers,
9558 if we find anything at all, it will be different from these
9560 for (i
= first_index_reg
; i
<= last_index_reg
; i
++)
9562 if (TEST_HARD_REG_BIT (reg_class_contents
[INDEX_REG_CLASS
], i
)
9563 && reg_state
[i
].use_index
== RELOAD_COMBINE_MAX_USES
9564 && reg_state
[i
].store_ruid
<= reg_state
[regno
].use_ruid
9565 && HARD_REGNO_NREGS (i
, GET_MODE (reg
)) == 1)
9567 rtx index_reg
= gen_rtx_REG (GET_MODE (reg
), i
);
9568 const_reg
= index_reg
;
9569 reg_sum
= gen_rtx_PLUS (GET_MODE (reg
), index_reg
, base
);
9574 /* Check that PREV_SET is indeed (set (REGX) (CONST_INT)) and that
9575 (REGY), i.e. BASE, is not clobbered before the last use we'll
9578 && GET_CODE (SET_SRC (prev_set
)) == CONST_INT
9579 && rtx_equal_p (SET_DEST (prev_set
), reg
)
9580 && reg_state
[regno
].use_index
>= 0
9581 && reg_state
[REGNO (base
)].store_ruid
<= reg_state
[regno
].use_ruid
9586 /* Change destination register and - if necessary - the
9587 constant value in PREV, the constant loading instruction. */
9588 validate_change (prev
, &SET_DEST (prev_set
), const_reg
, 1);
9589 if (reg_state
[regno
].offset
!= const0_rtx
)
9590 validate_change (prev
,
9591 &SET_SRC (prev_set
),
9592 GEN_INT (INTVAL (SET_SRC (prev_set
))
9593 + INTVAL (reg_state
[regno
].offset
)),
9595 /* Now for every use of REG that we have recorded, replace REG
9597 for (i
= reg_state
[regno
].use_index
;
9598 i
< RELOAD_COMBINE_MAX_USES
; i
++)
9599 validate_change (reg_state
[regno
].reg_use
[i
].insn
,
9600 reg_state
[regno
].reg_use
[i
].usep
,
9603 if (apply_change_group ())
9607 /* Delete the reg-reg addition. */
9608 PUT_CODE (insn
, NOTE
);
9609 NOTE_LINE_NUMBER (insn
) = NOTE_INSN_DELETED
;
9610 NOTE_SOURCE_FILE (insn
) = 0;
9612 if (reg_state
[regno
].offset
!= const0_rtx
)
9614 /* Previous REG_EQUIV / REG_EQUAL notes for PREV
9616 for (np
= ®_NOTES (prev
); *np
; )
9618 if (REG_NOTE_KIND (*np
) == REG_EQUAL
9619 || REG_NOTE_KIND (*np
) == REG_EQUIV
)
9620 *np
= XEXP (*np
, 1);
9622 np
= &XEXP (*np
, 1);
9625 reg_state
[regno
].use_index
= RELOAD_COMBINE_MAX_USES
;
9626 reg_state
[REGNO (const_reg
)].store_ruid
= reload_combine_ruid
;
9631 note_stores (PATTERN (insn
), reload_combine_note_store
);
9632 if (GET_CODE (insn
) == CALL_INSN
)
9636 for (i
= FIRST_PSEUDO_REGISTER
- 1; i
>= 0; --i
)
9638 if (call_used_regs
[i
])
9640 reg_state
[i
].use_index
= RELOAD_COMBINE_MAX_USES
;
9641 reg_state
[i
].store_ruid
= reload_combine_ruid
;
9644 for (link
= CALL_INSN_FUNCTION_USAGE (insn
); link
;
9645 link
= XEXP (link
, 1))
9647 rtx use
= XEXP (link
, 0);
9648 int regno
= REGNO (XEXP (use
, 0));
9649 if (GET_CODE (use
) == CLOBBER
)
9651 reg_state
[regno
].use_index
= RELOAD_COMBINE_MAX_USES
;
9652 reg_state
[regno
].store_ruid
= reload_combine_ruid
;
9655 reg_state
[regno
].use_index
= -1;
9658 if (GET_CODE (insn
) == JUMP_INSN
&& GET_CODE (PATTERN (insn
)) != RETURN
)
9660 /* Non-spill registers might be used at the call destination in
9661 some unknown fashion, so we have to mark the unknown use. */
9663 if ((condjump_p (insn
) || condjump_in_parallel_p (insn
))
9664 && JUMP_LABEL (insn
))
9665 live
= &LABEL_LIVE (JUMP_LABEL (insn
));
9667 live
= &ever_live_at_start
;
9668 for (i
= FIRST_PSEUDO_REGISTER
- 1; i
>= 0; --i
)
9670 if (TEST_HARD_REG_BIT (*live
, i
))
9671 reg_state
[i
].use_index
= -1;
9674 reload_combine_note_use (&PATTERN (insn
), insn
);
9675 for (note
= REG_NOTES (insn
); note
; note
= XEXP (note
, 1))
9677 if (REG_NOTE_KIND (note
) == REG_INC
9678 && GET_CODE (XEXP (note
, 0)) == REG
)
9680 int regno
= REGNO (XEXP (note
, 0));
9682 reg_state
[regno
].store_ruid
= reload_combine_ruid
;
9683 reg_state
[regno
].use_index
= -1;
9690 /* Check if DST is a register or a subreg of a register; if it is,
9691 update reg_state[regno].store_ruid and reg_state[regno].use_index
9692 accordingly. Called via note_stores from reload_combine.
9693 The second argument, SET, is ignored. */
9695 reload_combine_note_store (dst
, set
)
9696 rtx dst
, set ATTRIBUTE_UNUSED
;
9700 unsigned size
= GET_MODE_SIZE (GET_MODE (dst
));
9702 if (GET_CODE (dst
) == SUBREG
)
9704 regno
= SUBREG_WORD (dst
);
9705 dst
= SUBREG_REG (dst
);
9707 if (GET_CODE (dst
) != REG
)
9709 regno
+= REGNO (dst
);
9710 /* note_stores might have stripped a STRICT_LOW_PART, so we have to be
9711 careful with registers / register parts that are not full words. */
9712 if (size
< (unsigned) UNITS_PER_WORD
)
9714 reg_state
[regno
].use_index
= -1;
9715 reg_state
[regno
].store_ruid
= reload_combine_ruid
;
9719 for (i
= size
/ UNITS_PER_WORD
- 1 + regno
; i
>= regno
; i
--)
9721 reg_state
[i
].store_ruid
= reload_combine_ruid
;
9722 reg_state
[i
].use_index
= RELOAD_COMBINE_MAX_USES
;
9727 /* XP points to a piece of rtl that has to be checked for any uses of
9729 *XP is the pattern of INSN, or a part of it.
9730 Called from reload_combine, and recursively by itself. */
9732 reload_combine_note_use (xp
, insn
)
9736 enum rtx_code code
= x
->code
;
9739 rtx offset
= const0_rtx
; /* For the REG case below. */
9744 if (GET_CODE (SET_DEST (x
)) == REG
)
9746 reload_combine_note_use (&SET_SRC (x
), insn
);
9752 if (GET_CODE (SET_DEST (x
)) == REG
)
9757 /* We are interested in (plus (reg) (const_int)) . */
9758 if (GET_CODE (XEXP (x
, 0)) != REG
|| GET_CODE (XEXP (x
, 1)) != CONST_INT
)
9760 offset
= XEXP (x
, 1);
9765 int regno
= REGNO (x
);
9768 /* Some spurious USEs of pseudo registers might remain.
9769 Just ignore them. */
9770 if (regno
>= FIRST_PSEUDO_REGISTER
)
9773 /* If this register is already used in some unknown fashion, we
9775 If we decrement the index from zero to -1, we can't store more
9776 uses, so this register becomes used in an unknown fashion. */
9777 use_index
= --reg_state
[regno
].use_index
;
9781 if (use_index
!= RELOAD_COMBINE_MAX_USES
- 1)
9783 /* We have found another use for a register that is already
9784 used later. Check if the offsets match; if not, mark the
9785 register as used in an unknown fashion. */
9786 if (! rtx_equal_p (offset
, reg_state
[regno
].offset
))
9788 reg_state
[regno
].use_index
= -1;
9794 /* This is the first use of this register we have seen since we
9795 marked it as dead. */
9796 reg_state
[regno
].offset
= offset
;
9797 reg_state
[regno
].use_ruid
= reload_combine_ruid
;
9799 reg_state
[regno
].reg_use
[use_index
].insn
= insn
;
9800 reg_state
[regno
].reg_use
[use_index
].usep
= xp
;
9808 /* Recursively process the components of X. */
9809 fmt
= GET_RTX_FORMAT (code
);
9810 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
9813 reload_combine_note_use (&XEXP (x
, i
), insn
);
9814 else if (fmt
[i
] == 'E')
9816 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
9817 reload_combine_note_use (&XVECEXP (x
, i
, j
), insn
);
9822 /* See if we can reduce the cost of a constant by replacing a move with
9824 /* We cannot do our optimization across labels. Invalidating all the
9825 information about register contents we have would be costly, so we
9826 use last_label_luid (local variable of reload_cse_move2add) to note
9827 where the label is and then later disable any optimization that would
9829 reg_offset[n] / reg_base_reg[n] / reg_mode[n] are only valid if
9830 reg_set_luid[n] is larger than last_label_luid[n] . */
9831 static int reg_set_luid
[FIRST_PSEUDO_REGISTER
];
9832 /* reg_offset[n] has to be CONST_INT for it and reg_base_reg[n] /
9833 reg_mode[n] to be valid.
9834 If reg_offset[n] is a CONST_INT and reg_base_reg[n] is negative, register n
9835 has been set to reg_offset[n] in mode reg_mode[n] .
9836 If reg_offset[n] is a CONST_INT and reg_base_reg[n] is non-negative,
9837 register n has been set to the sum of reg_offset[n] and register
9838 reg_base_reg[n], calculated in mode reg_mode[n] . */
9839 static rtx reg_offset
[FIRST_PSEUDO_REGISTER
];
9840 static int reg_base_reg
[FIRST_PSEUDO_REGISTER
];
9841 static enum machine_mode reg_mode
[FIRST_PSEUDO_REGISTER
];
9842 /* move2add_luid is linearily increased while scanning the instructions
9843 from first to last. It is used to set reg_set_luid in
9844 reload_cse_move2add and move2add_note_store. */
9845 static int move2add_luid
;
9848 reload_cse_move2add (first
)
9853 int last_label_luid
;
9855 for (i
= FIRST_PSEUDO_REGISTER
-1; i
>= 0; i
--)
9856 reg_set_luid
[i
] = 0;
9858 last_label_luid
= 0;
9860 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
), move2add_luid
++)
9864 if (GET_CODE (insn
) == CODE_LABEL
)
9865 last_label_luid
= move2add_luid
;
9866 if (GET_RTX_CLASS (GET_CODE (insn
)) != 'i')
9868 pat
= PATTERN (insn
);
9869 /* For simplicity, we only perform this optimization on
9870 straightforward SETs. */
9871 if (GET_CODE (pat
) == SET
9872 && GET_CODE (SET_DEST (pat
)) == REG
)
9874 rtx reg
= SET_DEST (pat
);
9875 int regno
= REGNO (reg
);
9876 rtx src
= SET_SRC (pat
);
9878 /* Check if we have valid information on the contents of this
9879 register in the mode of REG. */
9880 /* ??? We don't know how zero / sign extension is handled, hence
9881 we can't go from a narrower to a wider mode. */
9882 if (reg_set_luid
[regno
] > last_label_luid
9883 && (GET_MODE_SIZE (GET_MODE (reg
))
9884 <= GET_MODE_SIZE (reg_mode
[regno
]))
9885 && GET_CODE (reg_offset
[regno
]) == CONST_INT
)
9887 /* Try to transform (set (REGX) (CONST_INT A))
9889 (set (REGX) (CONST_INT B))
9891 (set (REGX) (CONST_INT A))
9893 (set (REGX) (plus (REGX) (CONST_INT B-A))) */
9895 if (GET_CODE (src
) == CONST_INT
&& reg_base_reg
[regno
] < 0)
9898 rtx new_src
= GEN_INT (INTVAL (src
)
9899 - INTVAL (reg_offset
[regno
]));
9900 /* (set (reg) (plus (reg) (const_int 0))) is not canonical;
9901 use (set (reg) (reg)) instead.
9902 We don't delete this insn, nor do we convert it into a
9903 note, to avoid losing register notes or the return
9904 value flag. jump2 already knowns how to get rid of
9906 if (new_src
== const0_rtx
)
9907 success
= validate_change (insn
, &SET_SRC (pat
), reg
, 0);
9908 else if (rtx_cost (new_src
, PLUS
) < rtx_cost (src
, SET
)
9909 && have_add2_insn (GET_MODE (reg
)))
9910 success
= validate_change (insn
, &PATTERN (insn
),
9911 gen_add2_insn (reg
, new_src
), 0);
9912 reg_set_luid
[regno
] = move2add_luid
;
9913 reg_mode
[regno
] = GET_MODE (reg
);
9914 reg_offset
[regno
] = src
;
9918 /* Try to transform (set (REGX) (REGY))
9919 (set (REGX) (PLUS (REGX) (CONST_INT A)))
9922 (set (REGX) (PLUS (REGX) (CONST_INT B)))
9925 (set (REGX) (PLUS (REGX) (CONST_INT A)))
9927 (set (REGX) (plus (REGX) (CONST_INT B-A))) */
9928 else if (GET_CODE (src
) == REG
9929 && reg_base_reg
[regno
] == REGNO (src
)
9930 && reg_set_luid
[regno
] > reg_set_luid
[REGNO (src
)])
9932 rtx next
= next_nonnote_insn (insn
);
9935 set
= single_set (next
);
9938 && SET_DEST (set
) == reg
9939 && GET_CODE (SET_SRC (set
)) == PLUS
9940 && XEXP (SET_SRC (set
), 0) == reg
9941 && GET_CODE (XEXP (SET_SRC (set
), 1)) == CONST_INT
)
9943 rtx src3
= XEXP (SET_SRC (set
), 1);
9944 rtx new_src
= GEN_INT (INTVAL (src3
)
9945 - INTVAL (reg_offset
[regno
]));
9948 if (new_src
== const0_rtx
)
9949 /* See above why we create (set (reg) (reg)) here. */
9951 = validate_change (next
, &SET_SRC (set
), reg
, 0);
9952 else if ((rtx_cost (new_src
, PLUS
)
9953 < 2 + rtx_cost (src3
, SET
))
9954 && have_add2_insn (GET_MODE (reg
)))
9956 = validate_change (next
, &PATTERN (next
),
9957 gen_add2_insn (reg
, new_src
), 0);
9960 /* INSN might be the first insn in a basic block
9961 if the preceding insn is a conditional jump
9962 or a possible-throwing call. */
9963 PUT_CODE (insn
, NOTE
);
9964 NOTE_LINE_NUMBER (insn
) = NOTE_INSN_DELETED
;
9965 NOTE_SOURCE_FILE (insn
) = 0;
9968 reg_set_luid
[regno
] = move2add_luid
;
9969 reg_mode
[regno
] = GET_MODE (reg
);
9970 reg_offset
[regno
] = src3
;
9977 for (note
= REG_NOTES (insn
); note
; note
= XEXP (note
, 1))
9979 if (REG_NOTE_KIND (note
) == REG_INC
9980 && GET_CODE (XEXP (note
, 0)) == REG
)
9982 /* Indicate that this register has been recently written to,
9983 but the exact contents are not available. */
9984 int regno
= REGNO (XEXP (note
, 0));
9985 if (regno
< FIRST_PSEUDO_REGISTER
)
9987 reg_set_luid
[regno
] = move2add_luid
;
9988 reg_offset
[regno
] = note
;
9992 note_stores (PATTERN (insn
), move2add_note_store
);
9993 /* If this is a CALL_INSN, all call used registers are stored with
9995 if (GET_CODE (insn
) == CALL_INSN
)
9997 for (i
= FIRST_PSEUDO_REGISTER
-1; i
>= 0; i
--)
9999 if (call_used_regs
[i
])
10001 reg_set_luid
[i
] = move2add_luid
;
10002 reg_offset
[i
] = insn
; /* Invalidate contents. */
10009 /* SET is a SET or CLOBBER that sets DST.
10010 Update reg_set_luid, reg_offset and reg_base_reg accordingly.
10011 Called from reload_cse_move2add via note_stores. */
10013 move2add_note_store (dst
, set
)
10019 enum machine_mode mode
= GET_MODE (dst
);
10020 if (GET_CODE (dst
) == SUBREG
)
10022 regno
= SUBREG_WORD (dst
);
10023 dst
= SUBREG_REG (dst
);
10025 if (GET_CODE (dst
) != REG
)
10028 regno
+= REGNO (dst
);
10030 if (HARD_REGNO_NREGS (regno
, mode
) == 1 && GET_CODE (set
) == SET
)
10032 rtx src
= SET_SRC (set
);
10034 reg_mode
[regno
] = mode
;
10035 switch (GET_CODE (src
))
10039 rtx src0
= XEXP (src
, 0);
10040 if (GET_CODE (src0
) == REG
)
10042 if (REGNO (src0
) != regno
10043 || reg_offset
[regno
] != const0_rtx
)
10045 reg_base_reg
[regno
] = REGNO (src0
);
10046 reg_set_luid
[regno
] = move2add_luid
;
10048 reg_offset
[regno
] = XEXP (src
, 1);
10051 reg_set_luid
[regno
] = move2add_luid
;
10052 reg_offset
[regno
] = set
; /* Invalidate contents. */
10057 reg_base_reg
[regno
] = REGNO (SET_SRC (set
));
10058 reg_offset
[regno
] = const0_rtx
;
10059 reg_set_luid
[regno
] = move2add_luid
;
10063 reg_base_reg
[regno
] = -1;
10064 reg_offset
[regno
] = SET_SRC (set
);
10065 reg_set_luid
[regno
] = move2add_luid
;
10071 for (i
= regno
+ HARD_REGNO_NREGS (regno
, mode
) - 1; i
>= regno
; i
--)
10073 /* Indicate that this register has been recently written to,
10074 but the exact contents are not available. */
10075 reg_set_luid
[i
] = move2add_luid
;
10076 reg_offset
[i
] = dst
;