1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 3, or (at your option) any later
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
24 #include "coretypes.h"
28 #include "hard-reg-set.h"
32 #include "insn-config.h"
38 #include "addresses.h"
39 #include "basic-block.h"
51 /* This file contains the reload pass of the compiler, which is
52 run after register allocation has been done. It checks that
53 each insn is valid (operands required to be in registers really
54 are in registers of the proper class) and fixes up invalid ones
55 by copying values temporarily into registers for the insns
58 The results of register allocation are described by the vector
59 reg_renumber; the insns still contain pseudo regs, but reg_renumber
60 can be used to find which hard reg, if any, a pseudo reg is in.
62 The technique we always use is to free up a few hard regs that are
63 called ``reload regs'', and for each place where a pseudo reg
64 must be in a hard reg, copy it temporarily into one of the reload regs.
66 Reload regs are allocated locally for every instruction that needs
67 reloads. When there are pseudos which are allocated to a register that
68 has been chosen as a reload reg, such pseudos must be ``spilled''.
69 This means that they go to other hard regs, or to stack slots if no other
70 available hard regs can be found. Spilling can invalidate more
71 insns, requiring additional need for reloads, so we must keep checking
72 until the process stabilizes.
74 For machines with different classes of registers, we must keep track
75 of the register class needed for each reload, and make sure that
76 we allocate enough reload registers of each class.
78 The file reload.c contains the code that checks one insn for
79 validity and reports the reloads that it needs. This file
80 is in charge of scanning the entire rtl code, accumulating the
81 reload needs, spilling, assigning reload registers to use for
82 fixing up each insn, and generating the new insns to copy values
83 into the reload registers. */
85 /* During reload_as_needed, element N contains a REG rtx for the hard reg
86 into which reg N has been reloaded (perhaps for a previous insn). */
87 static rtx
*reg_last_reload_reg
;
89 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
90 for an output reload that stores into reg N. */
91 static regset_head reg_has_output_reload
;
93 /* Indicates which hard regs are reload-registers for an output reload
94 in the current insn. */
95 static HARD_REG_SET reg_is_output_reload
;
97 /* Element N is the constant value to which pseudo reg N is equivalent,
98 or zero if pseudo reg N is not equivalent to a constant.
99 find_reloads looks at this in order to replace pseudo reg N
100 with the constant it stands for. */
101 rtx
*reg_equiv_constant
;
103 /* Element N is an invariant value to which pseudo reg N is equivalent.
104 eliminate_regs_in_insn uses this to replace pseudos in particular
106 rtx
*reg_equiv_invariant
;
108 /* Element N is a memory location to which pseudo reg N is equivalent,
109 prior to any register elimination (such as frame pointer to stack
110 pointer). Depending on whether or not it is a valid address, this value
111 is transferred to either reg_equiv_address or reg_equiv_mem. */
112 rtx
*reg_equiv_memory_loc
;
114 /* We allocate reg_equiv_memory_loc inside a varray so that the garbage
115 collector can keep track of what is inside. */
116 VEC(rtx
,gc
) *reg_equiv_memory_loc_vec
;
118 /* Element N is the address of stack slot to which pseudo reg N is equivalent.
119 This is used when the address is not valid as a memory address
120 (because its displacement is too big for the machine.) */
121 rtx
*reg_equiv_address
;
123 /* Element N is the memory slot to which pseudo reg N is equivalent,
124 or zero if pseudo reg N is not equivalent to a memory slot. */
127 /* Element N is an EXPR_LIST of REG_EQUIVs containing MEMs with
128 alternate representations of the location of pseudo reg N. */
129 rtx
*reg_equiv_alt_mem_list
;
131 /* Widest width in which each pseudo reg is referred to (via subreg). */
132 static unsigned int *reg_max_ref_width
;
134 /* Element N is the list of insns that initialized reg N from its equivalent
135 constant or memory slot. */
137 int reg_equiv_init_size
;
139 /* Vector to remember old contents of reg_renumber before spilling. */
140 static short *reg_old_renumber
;
142 /* During reload_as_needed, element N contains the last pseudo regno reloaded
143 into hard register N. If that pseudo reg occupied more than one register,
144 reg_reloaded_contents points to that pseudo for each spill register in
145 use; all of these must remain set for an inheritance to occur. */
146 static int reg_reloaded_contents
[FIRST_PSEUDO_REGISTER
];
148 /* During reload_as_needed, element N contains the insn for which
149 hard register N was last used. Its contents are significant only
150 when reg_reloaded_valid is set for this register. */
151 static rtx reg_reloaded_insn
[FIRST_PSEUDO_REGISTER
];
153 /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid. */
154 static HARD_REG_SET reg_reloaded_valid
;
155 /* Indicate if the register was dead at the end of the reload.
156 This is only valid if reg_reloaded_contents is set and valid. */
157 static HARD_REG_SET reg_reloaded_dead
;
159 /* Indicate whether the register's current value is one that is not
160 safe to retain across a call, even for registers that are normally
161 call-saved. This is only meaningful for members of reg_reloaded_valid. */
162 static HARD_REG_SET reg_reloaded_call_part_clobbered
;
164 /* Number of spill-regs so far; number of valid elements of spill_regs. */
167 /* In parallel with spill_regs, contains REG rtx's for those regs.
168 Holds the last rtx used for any given reg, or 0 if it has never
169 been used for spilling yet. This rtx is reused, provided it has
171 static rtx spill_reg_rtx
[FIRST_PSEUDO_REGISTER
];
173 /* In parallel with spill_regs, contains nonzero for a spill reg
174 that was stored after the last time it was used.
175 The precise value is the insn generated to do the store. */
176 static rtx spill_reg_store
[FIRST_PSEUDO_REGISTER
];
178 /* This is the register that was stored with spill_reg_store. This is a
179 copy of reload_out / reload_out_reg when the value was stored; if
180 reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */
181 static rtx spill_reg_stored_to
[FIRST_PSEUDO_REGISTER
];
183 /* This table is the inverse mapping of spill_regs:
184 indexed by hard reg number,
185 it contains the position of that reg in spill_regs,
186 or -1 for something that is not in spill_regs.
188 ?!? This is no longer accurate. */
189 static short spill_reg_order
[FIRST_PSEUDO_REGISTER
];
191 /* This reg set indicates registers that can't be used as spill registers for
192 the currently processed insn. These are the hard registers which are live
193 during the insn, but not allocated to pseudos, as well as fixed
195 static HARD_REG_SET bad_spill_regs
;
197 /* These are the hard registers that can't be used as spill register for any
198 insn. This includes registers used for user variables and registers that
199 we can't eliminate. A register that appears in this set also can't be used
200 to retry register allocation. */
201 static HARD_REG_SET bad_spill_regs_global
;
203 /* Describes order of use of registers for reloading
204 of spilled pseudo-registers. `n_spills' is the number of
205 elements that are actually valid; new ones are added at the end.
207 Both spill_regs and spill_reg_order are used on two occasions:
208 once during find_reload_regs, where they keep track of the spill registers
209 for a single insn, but also during reload_as_needed where they show all
210 the registers ever used by reload. For the latter case, the information
211 is calculated during finish_spills. */
212 static short spill_regs
[FIRST_PSEUDO_REGISTER
];
214 /* This vector of reg sets indicates, for each pseudo, which hard registers
215 may not be used for retrying global allocation because the register was
216 formerly spilled from one of them. If we allowed reallocating a pseudo to
217 a register that it was already allocated to, reload might not
219 static HARD_REG_SET
*pseudo_previous_regs
;
221 /* This vector of reg sets indicates, for each pseudo, which hard
222 registers may not be used for retrying global allocation because they
223 are used as spill registers during one of the insns in which the
225 static HARD_REG_SET
*pseudo_forbidden_regs
;
227 /* All hard regs that have been used as spill registers for any insn are
228 marked in this set. */
229 static HARD_REG_SET used_spill_regs
;
231 /* Index of last register assigned as a spill register. We allocate in
232 a round-robin fashion. */
233 static int last_spill_reg
;
235 /* Nonzero if indirect addressing is supported on the machine; this means
236 that spilling (REG n) does not require reloading it into a register in
237 order to do (MEM (REG n)) or (MEM (PLUS (REG n) (CONST_INT c))). The
238 value indicates the level of indirect addressing supported, e.g., two
239 means that (MEM (MEM (REG n))) is also valid if (REG n) does not get
241 static char spill_indirect_levels
;
243 /* Nonzero if indirect addressing is supported when the innermost MEM is
244 of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to
245 which these are valid is the same as spill_indirect_levels, above. */
246 char indirect_symref_ok
;
248 /* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */
249 char double_reg_address_ok
;
251 /* Record the stack slot for each spilled hard register. */
252 static rtx spill_stack_slot
[FIRST_PSEUDO_REGISTER
];
254 /* Width allocated so far for that stack slot. */
255 static unsigned int spill_stack_slot_width
[FIRST_PSEUDO_REGISTER
];
257 /* Record which pseudos needed to be spilled. */
258 static regset_head spilled_pseudos
;
260 /* Used for communication between order_regs_for_reload and count_pseudo.
261 Used to avoid counting one pseudo twice. */
262 static regset_head pseudos_counted
;
264 /* First uid used by insns created by reload in this function.
265 Used in find_equiv_reg. */
266 int reload_first_uid
;
268 /* Flag set by local-alloc or global-alloc if anything is live in
269 a call-clobbered reg across calls. */
270 int caller_save_needed
;
272 /* Set to 1 while reload_as_needed is operating.
273 Required by some machines to handle any generated moves differently. */
274 int reload_in_progress
= 0;
276 /* These arrays record the insn_code of insns that may be needed to
277 perform input and output reloads of special objects. They provide a
278 place to pass a scratch register. */
279 enum insn_code reload_in_optab
[NUM_MACHINE_MODES
];
280 enum insn_code reload_out_optab
[NUM_MACHINE_MODES
];
282 /* This obstack is used for allocation of rtl during register elimination.
283 The allocated storage can be freed once find_reloads has processed the
285 static struct obstack reload_obstack
;
287 /* Points to the beginning of the reload_obstack. All insn_chain structures
288 are allocated first. */
289 static char *reload_startobj
;
291 /* The point after all insn_chain structures. Used to quickly deallocate
292 memory allocated in copy_reloads during calculate_needs_all_insns. */
293 static char *reload_firstobj
;
295 /* This points before all local rtl generated by register elimination.
296 Used to quickly free all memory after processing one insn. */
297 static char *reload_insn_firstobj
;
299 /* List of insn_chain instructions, one for every insn that reload needs to
301 struct insn_chain
*reload_insn_chain
;
303 /* List of all insns needing reloads. */
304 static struct insn_chain
*insns_need_reload
;
306 /* This structure is used to record information about register eliminations.
307 Each array entry describes one possible way of eliminating a register
308 in favor of another. If there is more than one way of eliminating a
309 particular register, the most preferred should be specified first. */
313 int from
; /* Register number to be eliminated. */
314 int to
; /* Register number used as replacement. */
315 HOST_WIDE_INT initial_offset
; /* Initial difference between values. */
316 int can_eliminate
; /* Nonzero if this elimination can be done. */
317 int can_eliminate_previous
; /* Value of CAN_ELIMINATE in previous scan over
318 insns made by reload. */
319 HOST_WIDE_INT offset
; /* Current offset between the two regs. */
320 HOST_WIDE_INT previous_offset
;/* Offset at end of previous insn. */
321 int ref_outside_mem
; /* "to" has been referenced outside a MEM. */
322 rtx from_rtx
; /* REG rtx for the register to be eliminated.
323 We cannot simply compare the number since
324 we might then spuriously replace a hard
325 register corresponding to a pseudo
326 assigned to the reg to be eliminated. */
327 rtx to_rtx
; /* REG rtx for the replacement. */
330 static struct elim_table
*reg_eliminate
= 0;
332 /* This is an intermediate structure to initialize the table. It has
333 exactly the members provided by ELIMINABLE_REGS. */
334 static const struct elim_table_1
338 } reg_eliminate_1
[] =
340 /* If a set of eliminable registers was specified, define the table from it.
341 Otherwise, default to the normal case of the frame pointer being
342 replaced by the stack pointer. */
344 #ifdef ELIMINABLE_REGS
347 {{ FRAME_POINTER_REGNUM
, STACK_POINTER_REGNUM
}};
350 #define NUM_ELIMINABLE_REGS ARRAY_SIZE (reg_eliminate_1)
352 /* Record the number of pending eliminations that have an offset not equal
353 to their initial offset. If nonzero, we use a new copy of each
354 replacement result in any insns encountered. */
355 int num_not_at_initial_offset
;
357 /* Count the number of registers that we may be able to eliminate. */
358 static int num_eliminable
;
359 /* And the number of registers that are equivalent to a constant that
360 can be eliminated to frame_pointer / arg_pointer + constant. */
361 static int num_eliminable_invariants
;
363 /* For each label, we record the offset of each elimination. If we reach
364 a label by more than one path and an offset differs, we cannot do the
365 elimination. This information is indexed by the difference of the
366 number of the label and the first label number. We can't offset the
367 pointer itself as this can cause problems on machines with segmented
368 memory. The first table is an array of flags that records whether we
369 have yet encountered a label and the second table is an array of arrays,
370 one entry in the latter array for each elimination. */
372 static int first_label_num
;
373 static char *offsets_known_at
;
374 static HOST_WIDE_INT (*offsets_at
)[NUM_ELIMINABLE_REGS
];
376 /* Number of labels in the current function. */
378 static int num_labels
;
380 static void replace_pseudos_in (rtx
*, enum machine_mode
, rtx
);
381 static void maybe_fix_stack_asms (void);
382 static void copy_reloads (struct insn_chain
*);
383 static void calculate_needs_all_insns (int);
384 static int find_reg (struct insn_chain
*, int);
385 static void find_reload_regs (struct insn_chain
*);
386 static void select_reload_regs (void);
387 static void delete_caller_save_insns (void);
389 static void spill_failure (rtx
, enum reg_class
);
390 static void count_spilled_pseudo (int, int, int);
391 static void delete_dead_insn (rtx
);
392 static void alter_reg (int, int);
393 static void set_label_offsets (rtx
, rtx
, int);
394 static void check_eliminable_occurrences (rtx
);
395 static void elimination_effects (rtx
, enum machine_mode
);
396 static int eliminate_regs_in_insn (rtx
, int);
397 static void update_eliminable_offsets (void);
398 static void mark_not_eliminable (rtx
, const_rtx
, void *);
399 static void set_initial_elim_offsets (void);
400 static bool verify_initial_elim_offsets (void);
401 static void set_initial_label_offsets (void);
402 static void set_offsets_for_label (rtx
);
403 static void init_elim_table (void);
404 static void update_eliminables (HARD_REG_SET
*);
405 static void spill_hard_reg (unsigned int, int);
406 static int finish_spills (int);
407 static void scan_paradoxical_subregs (rtx
);
408 static void count_pseudo (int);
409 static void order_regs_for_reload (struct insn_chain
*);
410 static void reload_as_needed (int);
411 static void forget_old_reloads_1 (rtx
, const_rtx
, void *);
412 static void forget_marked_reloads (regset
);
413 static int reload_reg_class_lower (const void *, const void *);
414 static void mark_reload_reg_in_use (unsigned int, int, enum reload_type
,
416 static void clear_reload_reg_in_use (unsigned int, int, enum reload_type
,
418 static int reload_reg_free_p (unsigned int, int, enum reload_type
);
419 static int reload_reg_free_for_value_p (int, int, int, enum reload_type
,
421 static int free_for_value_p (int, enum machine_mode
, int, enum reload_type
,
423 static int reload_reg_reaches_end_p (unsigned int, int, enum reload_type
);
424 static int allocate_reload_reg (struct insn_chain
*, int, int);
425 static int conflicts_with_override (rtx
);
426 static void failed_reload (rtx
, int);
427 static int set_reload_reg (int, int);
428 static void choose_reload_regs_init (struct insn_chain
*, rtx
*);
429 static void choose_reload_regs (struct insn_chain
*);
430 static void merge_assigned_reloads (rtx
);
431 static void emit_input_reload_insns (struct insn_chain
*, struct reload
*,
433 static void emit_output_reload_insns (struct insn_chain
*, struct reload
*,
435 static void do_input_reload (struct insn_chain
*, struct reload
*, int);
436 static void do_output_reload (struct insn_chain
*, struct reload
*, int);
437 static void emit_reload_insns (struct insn_chain
*);
438 static void delete_output_reload (rtx
, int, int, rtx
);
439 static void delete_address_reloads (rtx
, rtx
);
440 static void delete_address_reloads_1 (rtx
, rtx
, rtx
);
441 static rtx
inc_for_reload (rtx
, rtx
, rtx
, int);
443 static void add_auto_inc_notes (rtx
, rtx
);
445 static void copy_eh_notes (rtx
, rtx
);
446 static int reloads_conflict (int, int);
447 static rtx
gen_reload (rtx
, rtx
, int, enum reload_type
);
448 static rtx
emit_insn_if_valid_for_reload (rtx
);
450 /* Initialize the reload pass. This is called at the beginning of compilation
451 and may be called again if the target is reinitialized. */
458 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
459 Set spill_indirect_levels to the number of levels such addressing is
460 permitted, zero if it is not permitted at all. */
463 = gen_rtx_MEM (Pmode
,
466 LAST_VIRTUAL_REGISTER
+ 1),
468 spill_indirect_levels
= 0;
470 while (memory_address_p (QImode
, tem
))
472 spill_indirect_levels
++;
473 tem
= gen_rtx_MEM (Pmode
, tem
);
476 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
478 tem
= gen_rtx_MEM (Pmode
, gen_rtx_SYMBOL_REF (Pmode
, "foo"));
479 indirect_symref_ok
= memory_address_p (QImode
, tem
);
481 /* See if reg+reg is a valid (and offsettable) address. */
483 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
485 tem
= gen_rtx_PLUS (Pmode
,
486 gen_rtx_REG (Pmode
, HARD_FRAME_POINTER_REGNUM
),
487 gen_rtx_REG (Pmode
, i
));
489 /* This way, we make sure that reg+reg is an offsettable address. */
490 tem
= plus_constant (tem
, 4);
492 if (memory_address_p (QImode
, tem
))
494 double_reg_address_ok
= 1;
499 /* Initialize obstack for our rtl allocation. */
500 gcc_obstack_init (&reload_obstack
);
501 reload_startobj
= obstack_alloc (&reload_obstack
, 0);
503 INIT_REG_SET (&spilled_pseudos
);
504 INIT_REG_SET (&pseudos_counted
);
507 /* List of insn chains that are currently unused. */
508 static struct insn_chain
*unused_insn_chains
= 0;
510 /* Allocate an empty insn_chain structure. */
512 new_insn_chain (void)
514 struct insn_chain
*c
;
516 if (unused_insn_chains
== 0)
518 c
= obstack_alloc (&reload_obstack
, sizeof (struct insn_chain
));
519 INIT_REG_SET (&c
->live_throughout
);
520 INIT_REG_SET (&c
->dead_or_set
);
524 c
= unused_insn_chains
;
525 unused_insn_chains
= c
->next
;
527 c
->is_caller_save_insn
= 0;
528 c
->need_operand_change
= 0;
534 /* Small utility function to set all regs in hard reg set TO which are
535 allocated to pseudos in regset FROM. */
538 compute_use_by_pseudos (HARD_REG_SET
*to
, regset from
)
541 reg_set_iterator rsi
;
543 EXECUTE_IF_SET_IN_REG_SET (from
, FIRST_PSEUDO_REGISTER
, regno
, rsi
)
545 int r
= reg_renumber
[regno
];
549 /* reload_combine uses the information from
550 DF_LIVE_IN (BASIC_BLOCK), which might still
551 contain registers that have not actually been allocated
552 since they have an equivalence. */
553 gcc_assert (reload_completed
);
556 add_to_hard_reg_set (to
, PSEUDO_REGNO_MODE (regno
), r
);
560 /* Replace all pseudos found in LOC with their corresponding
564 replace_pseudos_in (rtx
*loc
, enum machine_mode mem_mode
, rtx usage
)
577 unsigned int regno
= REGNO (x
);
579 if (regno
< FIRST_PSEUDO_REGISTER
)
582 x
= eliminate_regs (x
, mem_mode
, usage
);
586 replace_pseudos_in (loc
, mem_mode
, usage
);
590 if (reg_equiv_constant
[regno
])
591 *loc
= reg_equiv_constant
[regno
];
592 else if (reg_equiv_mem
[regno
])
593 *loc
= reg_equiv_mem
[regno
];
594 else if (reg_equiv_address
[regno
])
595 *loc
= gen_rtx_MEM (GET_MODE (x
), reg_equiv_address
[regno
]);
598 gcc_assert (!REG_P (regno_reg_rtx
[regno
])
599 || REGNO (regno_reg_rtx
[regno
]) != regno
);
600 *loc
= regno_reg_rtx
[regno
];
605 else if (code
== MEM
)
607 replace_pseudos_in (& XEXP (x
, 0), GET_MODE (x
), usage
);
611 /* Process each of our operands recursively. */
612 fmt
= GET_RTX_FORMAT (code
);
613 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++, fmt
++)
615 replace_pseudos_in (&XEXP (x
, i
), mem_mode
, usage
);
616 else if (*fmt
== 'E')
617 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
618 replace_pseudos_in (& XVECEXP (x
, i
, j
), mem_mode
, usage
);
621 /* Determine if the current function has an exception receiver block
622 that reaches the exit block via non-exceptional edges */
625 has_nonexceptional_receiver (void)
629 basic_block
*tos
, *worklist
, bb
;
631 /* If we're not optimizing, then just err on the safe side. */
635 /* First determine which blocks can reach exit via normal paths. */
636 tos
= worklist
= xmalloc (sizeof (basic_block
) * (n_basic_blocks
+ 1));
639 bb
->flags
&= ~BB_REACHABLE
;
641 /* Place the exit block on our worklist. */
642 EXIT_BLOCK_PTR
->flags
|= BB_REACHABLE
;
643 *tos
++ = EXIT_BLOCK_PTR
;
645 /* Iterate: find everything reachable from what we've already seen. */
646 while (tos
!= worklist
)
650 FOR_EACH_EDGE (e
, ei
, bb
->preds
)
651 if (!(e
->flags
& EDGE_ABNORMAL
))
653 basic_block src
= e
->src
;
655 if (!(src
->flags
& BB_REACHABLE
))
657 src
->flags
|= BB_REACHABLE
;
664 /* Now see if there's a reachable block with an exceptional incoming
667 if (bb
->flags
& BB_REACHABLE
)
668 FOR_EACH_EDGE (e
, ei
, bb
->preds
)
669 if (e
->flags
& EDGE_ABNORMAL
)
672 /* No exceptional block reached exit unexceptionally. */
677 /* Global variables used by reload and its subroutines. */
679 /* Set during calculate_needs if an insn needs register elimination. */
680 static int something_needs_elimination
;
681 /* Set during calculate_needs if an insn needs an operand changed. */
682 static int something_needs_operands_changed
;
684 /* Nonzero means we couldn't get enough spill regs. */
687 /* Main entry point for the reload pass.
689 FIRST is the first insn of the function being compiled.
691 GLOBAL nonzero means we were called from global_alloc
692 and should attempt to reallocate any pseudoregs that we
693 displace from hard regs we will use for reloads.
694 If GLOBAL is zero, we do not have enough information to do that,
695 so any pseudo reg that is spilled must go to the stack.
697 Return value is nonzero if reload failed
698 and we must not do any more for this function. */
701 reload (rtx first
, int global
)
705 struct elim_table
*ep
;
708 /* Make sure even insns with volatile mem refs are recognizable. */
713 reload_firstobj
= obstack_alloc (&reload_obstack
, 0);
715 /* Make sure that the last insn in the chain
716 is not something that needs reloading. */
717 emit_note (NOTE_INSN_DELETED
);
719 /* Enable find_equiv_reg to distinguish insns made by reload. */
720 reload_first_uid
= get_max_uid ();
722 #ifdef SECONDARY_MEMORY_NEEDED
723 /* Initialize the secondary memory table. */
724 clear_secondary_mem ();
727 /* We don't have a stack slot for any spill reg yet. */
728 memset (spill_stack_slot
, 0, sizeof spill_stack_slot
);
729 memset (spill_stack_slot_width
, 0, sizeof spill_stack_slot_width
);
731 /* Initialize the save area information for caller-save, in case some
735 /* Compute which hard registers are now in use
736 as homes for pseudo registers.
737 This is done here rather than (eg) in global_alloc
738 because this point is reached even if not optimizing. */
739 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
742 /* A function that has a nonlocal label that can reach the exit
743 block via non-exceptional paths must save all call-saved
745 if (cfun
->has_nonlocal_label
746 && has_nonexceptional_receiver ())
747 crtl
->saves_all_registers
= 1;
749 if (crtl
->saves_all_registers
)
750 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
751 if (! call_used_regs
[i
] && ! fixed_regs
[i
] && ! LOCAL_REGNO (i
))
752 df_set_regs_ever_live (i
, true);
754 /* Find all the pseudo registers that didn't get hard regs
755 but do have known equivalent constants or memory slots.
756 These include parameters (known equivalent to parameter slots)
757 and cse'd or loop-moved constant memory addresses.
759 Record constant equivalents in reg_equiv_constant
760 so they will be substituted by find_reloads.
761 Record memory equivalents in reg_mem_equiv so they can
762 be substituted eventually by altering the REG-rtx's. */
764 reg_equiv_constant
= XCNEWVEC (rtx
, max_regno
);
765 reg_equiv_invariant
= XCNEWVEC (rtx
, max_regno
);
766 reg_equiv_mem
= XCNEWVEC (rtx
, max_regno
);
767 reg_equiv_alt_mem_list
= XCNEWVEC (rtx
, max_regno
);
768 reg_equiv_address
= XCNEWVEC (rtx
, max_regno
);
769 reg_max_ref_width
= XCNEWVEC (unsigned int, max_regno
);
770 reg_old_renumber
= XCNEWVEC (short, max_regno
);
771 memcpy (reg_old_renumber
, reg_renumber
, max_regno
* sizeof (short));
772 pseudo_forbidden_regs
= XNEWVEC (HARD_REG_SET
, max_regno
);
773 pseudo_previous_regs
= XCNEWVEC (HARD_REG_SET
, max_regno
);
775 CLEAR_HARD_REG_SET (bad_spill_regs_global
);
777 /* Look for REG_EQUIV notes; record what each pseudo is equivalent
778 to. Also find all paradoxical subregs and find largest such for
781 num_eliminable_invariants
= 0;
782 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
784 rtx set
= single_set (insn
);
786 /* We may introduce USEs that we want to remove at the end, so
787 we'll mark them with QImode. Make sure there are no
788 previously-marked insns left by say regmove. */
789 if (INSN_P (insn
) && GET_CODE (PATTERN (insn
)) == USE
790 && GET_MODE (insn
) != VOIDmode
)
791 PUT_MODE (insn
, VOIDmode
);
794 scan_paradoxical_subregs (PATTERN (insn
));
796 if (set
!= 0 && REG_P (SET_DEST (set
)))
798 rtx note
= find_reg_note (insn
, REG_EQUIV
, NULL_RTX
);
804 i
= REGNO (SET_DEST (set
));
807 if (i
<= LAST_VIRTUAL_REGISTER
)
810 if (! function_invariant_p (x
)
812 /* A function invariant is often CONSTANT_P but may
813 include a register. We promise to only pass
814 CONSTANT_P objects to LEGITIMATE_PIC_OPERAND_P. */
816 && LEGITIMATE_PIC_OPERAND_P (x
)))
818 /* It can happen that a REG_EQUIV note contains a MEM
819 that is not a legitimate memory operand. As later
820 stages of reload assume that all addresses found
821 in the reg_equiv_* arrays were originally legitimate,
822 we ignore such REG_EQUIV notes. */
823 if (memory_operand (x
, VOIDmode
))
825 /* Always unshare the equivalence, so we can
826 substitute into this insn without touching the
828 reg_equiv_memory_loc
[i
] = copy_rtx (x
);
830 else if (function_invariant_p (x
))
832 if (GET_CODE (x
) == PLUS
)
834 /* This is PLUS of frame pointer and a constant,
835 and might be shared. Unshare it. */
836 reg_equiv_invariant
[i
] = copy_rtx (x
);
837 num_eliminable_invariants
++;
839 else if (x
== frame_pointer_rtx
|| x
== arg_pointer_rtx
)
841 reg_equiv_invariant
[i
] = x
;
842 num_eliminable_invariants
++;
844 else if (LEGITIMATE_CONSTANT_P (x
))
845 reg_equiv_constant
[i
] = x
;
848 reg_equiv_memory_loc
[i
]
849 = force_const_mem (GET_MODE (SET_DEST (set
)), x
);
850 if (! reg_equiv_memory_loc
[i
])
851 reg_equiv_init
[i
] = NULL_RTX
;
856 reg_equiv_init
[i
] = NULL_RTX
;
861 reg_equiv_init
[i
] = NULL_RTX
;
866 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
867 if (reg_equiv_init
[i
])
869 fprintf (dump_file
, "init_insns for %u: ", i
);
870 print_inline_rtx (dump_file
, reg_equiv_init
[i
], 20);
871 fprintf (dump_file
, "\n");
876 first_label_num
= get_first_label_num ();
877 num_labels
= max_label_num () - first_label_num
;
879 /* Allocate the tables used to store offset information at labels. */
880 /* We used to use alloca here, but the size of what it would try to
881 allocate would occasionally cause it to exceed the stack limit and
882 cause a core dump. */
883 offsets_known_at
= XNEWVEC (char, num_labels
);
884 offsets_at
= (HOST_WIDE_INT (*)[NUM_ELIMINABLE_REGS
]) xmalloc (num_labels
* NUM_ELIMINABLE_REGS
* sizeof (HOST_WIDE_INT
));
886 /* Alter each pseudo-reg rtx to contain its hard reg number.
887 Assign stack slots to the pseudos that lack hard regs or equivalents.
888 Do not touch virtual registers. */
890 for (i
= LAST_VIRTUAL_REGISTER
+ 1; i
< max_regno
; i
++)
893 /* If we have some registers we think can be eliminated, scan all insns to
894 see if there is an insn that sets one of these registers to something
895 other than itself plus a constant. If so, the register cannot be
896 eliminated. Doing this scan here eliminates an extra pass through the
897 main reload loop in the most common case where register elimination
899 for (insn
= first
; insn
&& num_eliminable
; insn
= NEXT_INSN (insn
))
901 note_stores (PATTERN (insn
), mark_not_eliminable
, NULL
);
903 maybe_fix_stack_asms ();
905 insns_need_reload
= 0;
906 something_needs_elimination
= 0;
908 /* Initialize to -1, which means take the first spill register. */
911 /* Spill any hard regs that we know we can't eliminate. */
912 CLEAR_HARD_REG_SET (used_spill_regs
);
913 /* There can be multiple ways to eliminate a register;
914 they should be listed adjacently.
915 Elimination for any register fails only if all possible ways fail. */
916 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; )
919 int can_eliminate
= 0;
922 can_eliminate
|= ep
->can_eliminate
;
925 while (ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
] && ep
->from
== from
);
927 spill_hard_reg (from
, 1);
930 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
931 if (frame_pointer_needed
)
932 spill_hard_reg (HARD_FRAME_POINTER_REGNUM
, 1);
934 finish_spills (global
);
936 /* From now on, we may need to generate moves differently. We may also
937 allow modifications of insns which cause them to not be recognized.
938 Any such modifications will be cleaned up during reload itself. */
939 reload_in_progress
= 1;
941 /* This loop scans the entire function each go-round
942 and repeats until one repetition spills no additional hard regs. */
945 int something_changed
;
947 HOST_WIDE_INT starting_frame_size
;
949 starting_frame_size
= get_frame_size ();
951 set_initial_elim_offsets ();
952 set_initial_label_offsets ();
954 /* For each pseudo register that has an equivalent location defined,
955 try to eliminate any eliminable registers (such as the frame pointer)
956 assuming initial offsets for the replacement register, which
959 If the resulting location is directly addressable, substitute
960 the MEM we just got directly for the old REG.
962 If it is not addressable but is a constant or the sum of a hard reg
963 and constant, it is probably not addressable because the constant is
964 out of range, in that case record the address; we will generate
965 hairy code to compute the address in a register each time it is
966 needed. Similarly if it is a hard register, but one that is not
967 valid as an address register.
969 If the location is not addressable, but does not have one of the
970 above forms, assign a stack slot. We have to do this to avoid the
971 potential of producing lots of reloads if, e.g., a location involves
972 a pseudo that didn't get a hard register and has an equivalent memory
973 location that also involves a pseudo that didn't get a hard register.
975 Perhaps at some point we will improve reload_when_needed handling
976 so this problem goes away. But that's very hairy. */
978 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
979 if (reg_renumber
[i
] < 0 && reg_equiv_memory_loc
[i
])
981 rtx x
= eliminate_regs (reg_equiv_memory_loc
[i
], 0, NULL_RTX
);
983 if (strict_memory_address_p (GET_MODE (regno_reg_rtx
[i
]),
985 reg_equiv_mem
[i
] = x
, reg_equiv_address
[i
] = 0;
986 else if (CONSTANT_P (XEXP (x
, 0))
987 || (REG_P (XEXP (x
, 0))
988 && REGNO (XEXP (x
, 0)) < FIRST_PSEUDO_REGISTER
)
989 || (GET_CODE (XEXP (x
, 0)) == PLUS
990 && REG_P (XEXP (XEXP (x
, 0), 0))
991 && (REGNO (XEXP (XEXP (x
, 0), 0))
992 < FIRST_PSEUDO_REGISTER
)
993 && CONSTANT_P (XEXP (XEXP (x
, 0), 1))))
994 reg_equiv_address
[i
] = XEXP (x
, 0), reg_equiv_mem
[i
] = 0;
997 /* Make a new stack slot. Then indicate that something
998 changed so we go back and recompute offsets for
999 eliminable registers because the allocation of memory
1000 below might change some offset. reg_equiv_{mem,address}
1001 will be set up for this pseudo on the next pass around
1003 reg_equiv_memory_loc
[i
] = 0;
1004 reg_equiv_init
[i
] = 0;
1009 if (caller_save_needed
)
1010 setup_save_areas ();
1012 /* If we allocated another stack slot, redo elimination bookkeeping. */
1013 if (starting_frame_size
!= get_frame_size ())
1015 if (starting_frame_size
&& crtl
->stack_alignment_needed
)
1017 /* If we have a stack frame, we must align it now. The
1018 stack size may be a part of the offset computation for
1019 register elimination. So if this changes the stack size,
1020 then repeat the elimination bookkeeping. We don't
1021 realign when there is no stack, as that will cause a
1022 stack frame when none is needed should
1023 STARTING_FRAME_OFFSET not be already aligned to
1025 assign_stack_local (BLKmode
, 0, crtl
->stack_alignment_needed
);
1026 if (starting_frame_size
!= get_frame_size ())
1030 if (caller_save_needed
)
1032 save_call_clobbered_regs ();
1033 /* That might have allocated new insn_chain structures. */
1034 reload_firstobj
= obstack_alloc (&reload_obstack
, 0);
1037 calculate_needs_all_insns (global
);
1039 CLEAR_REG_SET (&spilled_pseudos
);
1042 something_changed
= 0;
1044 /* If we allocated any new memory locations, make another pass
1045 since it might have changed elimination offsets. */
1046 if (starting_frame_size
!= get_frame_size ())
1047 something_changed
= 1;
1049 /* Even if the frame size remained the same, we might still have
1050 changed elimination offsets, e.g. if find_reloads called
1051 force_const_mem requiring the back end to allocate a constant
1052 pool base register that needs to be saved on the stack. */
1053 else if (!verify_initial_elim_offsets ())
1054 something_changed
= 1;
1057 HARD_REG_SET to_spill
;
1058 CLEAR_HARD_REG_SET (to_spill
);
1059 update_eliminables (&to_spill
);
1060 AND_COMPL_HARD_REG_SET (used_spill_regs
, to_spill
);
1062 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1063 if (TEST_HARD_REG_BIT (to_spill
, i
))
1065 spill_hard_reg (i
, 1);
1068 /* Regardless of the state of spills, if we previously had
1069 a register that we thought we could eliminate, but now can
1070 not eliminate, we must run another pass.
1072 Consider pseudos which have an entry in reg_equiv_* which
1073 reference an eliminable register. We must make another pass
1074 to update reg_equiv_* so that we do not substitute in the
1075 old value from when we thought the elimination could be
1077 something_changed
= 1;
1081 select_reload_regs ();
1085 if (insns_need_reload
!= 0 || did_spill
)
1086 something_changed
|= finish_spills (global
);
1088 if (! something_changed
)
1091 if (caller_save_needed
)
1092 delete_caller_save_insns ();
1094 obstack_free (&reload_obstack
, reload_firstobj
);
1097 /* If global-alloc was run, notify it of any register eliminations we have
1100 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
1101 if (ep
->can_eliminate
)
1102 mark_elimination (ep
->from
, ep
->to
);
1104 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
1105 If that insn didn't set the register (i.e., it copied the register to
1106 memory), just delete that insn instead of the equivalencing insn plus
1107 anything now dead. If we call delete_dead_insn on that insn, we may
1108 delete the insn that actually sets the register if the register dies
1109 there and that is incorrect. */
1111 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
1113 if (reg_renumber
[i
] < 0 && reg_equiv_init
[i
] != 0)
1116 for (list
= reg_equiv_init
[i
]; list
; list
= XEXP (list
, 1))
1118 rtx equiv_insn
= XEXP (list
, 0);
1120 /* If we already deleted the insn or if it may trap, we can't
1121 delete it. The latter case shouldn't happen, but can
1122 if an insn has a variable address, gets a REG_EH_REGION
1123 note added to it, and then gets converted into a load
1124 from a constant address. */
1125 if (NOTE_P (equiv_insn
)
1126 || can_throw_internal (equiv_insn
))
1128 else if (reg_set_p (regno_reg_rtx
[i
], PATTERN (equiv_insn
)))
1129 delete_dead_insn (equiv_insn
);
1131 SET_INSN_DELETED (equiv_insn
);
1136 /* Use the reload registers where necessary
1137 by generating move instructions to move the must-be-register
1138 values into or out of the reload registers. */
1140 if (insns_need_reload
!= 0 || something_needs_elimination
1141 || something_needs_operands_changed
)
1143 HOST_WIDE_INT old_frame_size
= get_frame_size ();
1145 reload_as_needed (global
);
1147 gcc_assert (old_frame_size
== get_frame_size ());
1149 gcc_assert (verify_initial_elim_offsets ());
1152 /* If we were able to eliminate the frame pointer, show that it is no
1153 longer live at the start of any basic block. If it ls live by
1154 virtue of being in a pseudo, that pseudo will be marked live
1155 and hence the frame pointer will be known to be live via that
1158 if (! frame_pointer_needed
)
1160 bitmap_clear_bit (df_get_live_in (bb
), HARD_FRAME_POINTER_REGNUM
);
1162 /* Come here (with failure set nonzero) if we can't get enough spill
1166 CLEAR_REG_SET (&spilled_pseudos
);
1167 reload_in_progress
= 0;
1169 /* Now eliminate all pseudo regs by modifying them into
1170 their equivalent memory references.
1171 The REG-rtx's for the pseudos are modified in place,
1172 so all insns that used to refer to them now refer to memory.
1174 For a reg that has a reg_equiv_address, all those insns
1175 were changed by reloading so that no insns refer to it any longer;
1176 but the DECL_RTL of a variable decl may refer to it,
1177 and if so this causes the debugging info to mention the variable. */
1179 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
1183 if (reg_equiv_mem
[i
])
1184 addr
= XEXP (reg_equiv_mem
[i
], 0);
1186 if (reg_equiv_address
[i
])
1187 addr
= reg_equiv_address
[i
];
1191 if (reg_renumber
[i
] < 0)
1193 rtx reg
= regno_reg_rtx
[i
];
1195 REG_USERVAR_P (reg
) = 0;
1196 PUT_CODE (reg
, MEM
);
1197 XEXP (reg
, 0) = addr
;
1198 if (reg_equiv_memory_loc
[i
])
1199 MEM_COPY_ATTRIBUTES (reg
, reg_equiv_memory_loc
[i
]);
1202 MEM_IN_STRUCT_P (reg
) = MEM_SCALAR_P (reg
) = 0;
1203 MEM_ATTRS (reg
) = 0;
1205 MEM_NOTRAP_P (reg
) = 1;
1207 else if (reg_equiv_mem
[i
])
1208 XEXP (reg_equiv_mem
[i
], 0) = addr
;
1212 /* We must set reload_completed now since the cleanup_subreg_operands call
1213 below will re-recognize each insn and reload may have generated insns
1214 which are only valid during and after reload. */
1215 reload_completed
= 1;
1217 /* Make a pass over all the insns and delete all USEs which we inserted
1218 only to tag a REG_EQUAL note on them. Remove all REG_DEAD and REG_UNUSED
1219 notes. Delete all CLOBBER insns, except those that refer to the return
1220 value and the special mem:BLK CLOBBERs added to prevent the scheduler
1221 from misarranging variable-array code, and simplify (subreg (reg))
1222 operands. Also remove all REG_RETVAL and REG_LIBCALL notes since they
1223 are no longer useful or accurate. Strip and regenerate REG_INC notes
1224 that may have been moved around. */
1226 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
1232 replace_pseudos_in (& CALL_INSN_FUNCTION_USAGE (insn
),
1233 VOIDmode
, CALL_INSN_FUNCTION_USAGE (insn
));
1235 if ((GET_CODE (PATTERN (insn
)) == USE
1236 /* We mark with QImode USEs introduced by reload itself. */
1237 && (GET_MODE (insn
) == QImode
1238 || find_reg_note (insn
, REG_EQUAL
, NULL_RTX
)))
1239 || (GET_CODE (PATTERN (insn
)) == CLOBBER
1240 && (!MEM_P (XEXP (PATTERN (insn
), 0))
1241 || GET_MODE (XEXP (PATTERN (insn
), 0)) != BLKmode
1242 || (GET_CODE (XEXP (XEXP (PATTERN (insn
), 0), 0)) != SCRATCH
1243 && XEXP (XEXP (PATTERN (insn
), 0), 0)
1244 != stack_pointer_rtx
))
1245 && (!REG_P (XEXP (PATTERN (insn
), 0))
1246 || ! REG_FUNCTION_VALUE_P (XEXP (PATTERN (insn
), 0)))))
1252 /* Some CLOBBERs may survive until here and still reference unassigned
1253 pseudos with const equivalent, which may in turn cause ICE in later
1254 passes if the reference remains in place. */
1255 if (GET_CODE (PATTERN (insn
)) == CLOBBER
)
1256 replace_pseudos_in (& XEXP (PATTERN (insn
), 0),
1257 VOIDmode
, PATTERN (insn
));
1259 /* Discard obvious no-ops, even without -O. This optimization
1260 is fast and doesn't interfere with debugging. */
1261 if (NONJUMP_INSN_P (insn
)
1262 && GET_CODE (PATTERN (insn
)) == SET
1263 && REG_P (SET_SRC (PATTERN (insn
)))
1264 && REG_P (SET_DEST (PATTERN (insn
)))
1265 && (REGNO (SET_SRC (PATTERN (insn
)))
1266 == REGNO (SET_DEST (PATTERN (insn
)))))
1272 pnote
= ®_NOTES (insn
);
1275 if (REG_NOTE_KIND (*pnote
) == REG_DEAD
1276 || REG_NOTE_KIND (*pnote
) == REG_UNUSED
1277 || REG_NOTE_KIND (*pnote
) == REG_INC
1278 || REG_NOTE_KIND (*pnote
) == REG_RETVAL
1279 || REG_NOTE_KIND (*pnote
) == REG_LIBCALL
)
1280 *pnote
= XEXP (*pnote
, 1);
1282 pnote
= &XEXP (*pnote
, 1);
1286 add_auto_inc_notes (insn
, PATTERN (insn
));
1289 /* Simplify (subreg (reg)) if it appears as an operand. */
1290 cleanup_subreg_operands (insn
);
1292 /* Clean up invalid ASMs so that they don't confuse later passes.
1294 if (asm_noperands (PATTERN (insn
)) >= 0)
1296 extract_insn (insn
);
1297 if (!constrain_operands (1))
1299 error_for_asm (insn
,
1300 "%<asm%> operand has impossible constraints");
1307 /* If we are doing stack checking, give a warning if this function's
1308 frame size is larger than we expect. */
1309 if (flag_stack_check
&& ! STACK_CHECK_BUILTIN
)
1311 HOST_WIDE_INT size
= get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE
;
1312 static int verbose_warned
= 0;
1314 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1315 if (df_regs_ever_live_p (i
) && ! fixed_regs
[i
] && call_used_regs
[i
])
1316 size
+= UNITS_PER_WORD
;
1318 if (size
> STACK_CHECK_MAX_FRAME_SIZE
)
1320 warning (0, "frame size too large for reliable stack checking");
1321 if (! verbose_warned
)
1323 warning (0, "try reducing the number of local variables");
1329 /* Indicate that we no longer have known memory locations or constants. */
1330 if (reg_equiv_constant
)
1331 free (reg_equiv_constant
);
1332 if (reg_equiv_invariant
)
1333 free (reg_equiv_invariant
);
1334 reg_equiv_constant
= 0;
1335 reg_equiv_invariant
= 0;
1336 VEC_free (rtx
, gc
, reg_equiv_memory_loc_vec
);
1337 reg_equiv_memory_loc
= 0;
1339 if (offsets_known_at
)
1340 free (offsets_known_at
);
1344 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1345 if (reg_equiv_alt_mem_list
[i
])
1346 free_EXPR_LIST_list (®_equiv_alt_mem_list
[i
]);
1347 free (reg_equiv_alt_mem_list
);
1349 free (reg_equiv_mem
);
1351 free (reg_equiv_address
);
1352 free (reg_max_ref_width
);
1353 free (reg_old_renumber
);
1354 free (pseudo_previous_regs
);
1355 free (pseudo_forbidden_regs
);
1357 CLEAR_HARD_REG_SET (used_spill_regs
);
1358 for (i
= 0; i
< n_spills
; i
++)
1359 SET_HARD_REG_BIT (used_spill_regs
, spill_regs
[i
]);
1361 /* Free all the insn_chain structures at once. */
1362 obstack_free (&reload_obstack
, reload_startobj
);
1363 unused_insn_chains
= 0;
1364 fixup_abnormal_edges ();
1366 /* Replacing pseudos with their memory equivalents might have
1367 created shared rtx. Subsequent passes would get confused
1368 by this, so unshare everything here. */
1369 unshare_all_rtl_again (first
);
1371 #ifdef STACK_BOUNDARY
1372 /* init_emit has set the alignment of the hard frame pointer
1373 to STACK_BOUNDARY. It is very likely no longer valid if
1374 the hard frame pointer was used for register allocation. */
1375 if (!frame_pointer_needed
)
1376 REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM
) = BITS_PER_UNIT
;
1382 /* Yet another special case. Unfortunately, reg-stack forces people to
1383 write incorrect clobbers in asm statements. These clobbers must not
1384 cause the register to appear in bad_spill_regs, otherwise we'll call
1385 fatal_insn later. We clear the corresponding regnos in the live
1386 register sets to avoid this.
1387 The whole thing is rather sick, I'm afraid. */
1390 maybe_fix_stack_asms (void)
1393 const char *constraints
[MAX_RECOG_OPERANDS
];
1394 enum machine_mode operand_mode
[MAX_RECOG_OPERANDS
];
1395 struct insn_chain
*chain
;
1397 for (chain
= reload_insn_chain
; chain
!= 0; chain
= chain
->next
)
1400 HARD_REG_SET clobbered
, allowed
;
1403 if (! INSN_P (chain
->insn
)
1404 || (noperands
= asm_noperands (PATTERN (chain
->insn
))) < 0)
1406 pat
= PATTERN (chain
->insn
);
1407 if (GET_CODE (pat
) != PARALLEL
)
1410 CLEAR_HARD_REG_SET (clobbered
);
1411 CLEAR_HARD_REG_SET (allowed
);
1413 /* First, make a mask of all stack regs that are clobbered. */
1414 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
1416 rtx t
= XVECEXP (pat
, 0, i
);
1417 if (GET_CODE (t
) == CLOBBER
&& STACK_REG_P (XEXP (t
, 0)))
1418 SET_HARD_REG_BIT (clobbered
, REGNO (XEXP (t
, 0)));
1421 /* Get the operand values and constraints out of the insn. */
1422 decode_asm_operands (pat
, recog_data
.operand
, recog_data
.operand_loc
,
1423 constraints
, operand_mode
, NULL
);
1425 /* For every operand, see what registers are allowed. */
1426 for (i
= 0; i
< noperands
; i
++)
1428 const char *p
= constraints
[i
];
1429 /* For every alternative, we compute the class of registers allowed
1430 for reloading in CLS, and merge its contents into the reg set
1432 int cls
= (int) NO_REGS
;
1438 if (c
== '\0' || c
== ',' || c
== '#')
1440 /* End of one alternative - mark the regs in the current
1441 class, and reset the class. */
1442 IOR_HARD_REG_SET (allowed
, reg_class_contents
[cls
]);
1448 } while (c
!= '\0' && c
!= ',');
1456 case '=': case '+': case '*': case '%': case '?': case '!':
1457 case '0': case '1': case '2': case '3': case '4': case '<':
1458 case '>': case 'V': case 'o': case '&': case 'E': case 'F':
1459 case 's': case 'i': case 'n': case 'X': case 'I': case 'J':
1460 case 'K': case 'L': case 'M': case 'N': case 'O': case 'P':
1461 case TARGET_MEM_CONSTRAINT
:
1465 cls
= (int) reg_class_subunion
[cls
]
1466 [(int) base_reg_class (VOIDmode
, ADDRESS
, SCRATCH
)];
1471 cls
= (int) reg_class_subunion
[cls
][(int) GENERAL_REGS
];
1475 if (EXTRA_ADDRESS_CONSTRAINT (c
, p
))
1476 cls
= (int) reg_class_subunion
[cls
]
1477 [(int) base_reg_class (VOIDmode
, ADDRESS
, SCRATCH
)];
1479 cls
= (int) reg_class_subunion
[cls
]
1480 [(int) REG_CLASS_FROM_CONSTRAINT (c
, p
)];
1482 p
+= CONSTRAINT_LEN (c
, p
);
1485 /* Those of the registers which are clobbered, but allowed by the
1486 constraints, must be usable as reload registers. So clear them
1487 out of the life information. */
1488 AND_HARD_REG_SET (allowed
, clobbered
);
1489 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1490 if (TEST_HARD_REG_BIT (allowed
, i
))
1492 CLEAR_REGNO_REG_SET (&chain
->live_throughout
, i
);
1493 CLEAR_REGNO_REG_SET (&chain
->dead_or_set
, i
);
1500 /* Copy the global variables n_reloads and rld into the corresponding elts
1503 copy_reloads (struct insn_chain
*chain
)
1505 chain
->n_reloads
= n_reloads
;
1506 chain
->rld
= obstack_alloc (&reload_obstack
,
1507 n_reloads
* sizeof (struct reload
));
1508 memcpy (chain
->rld
, rld
, n_reloads
* sizeof (struct reload
));
1509 reload_insn_firstobj
= obstack_alloc (&reload_obstack
, 0);
1512 /* Walk the chain of insns, and determine for each whether it needs reloads
1513 and/or eliminations. Build the corresponding insns_need_reload list, and
1514 set something_needs_elimination as appropriate. */
1516 calculate_needs_all_insns (int global
)
1518 struct insn_chain
**pprev_reload
= &insns_need_reload
;
1519 struct insn_chain
*chain
, *next
= 0;
1521 something_needs_elimination
= 0;
1523 reload_insn_firstobj
= obstack_alloc (&reload_obstack
, 0);
1524 for (chain
= reload_insn_chain
; chain
!= 0; chain
= next
)
1526 rtx insn
= chain
->insn
;
1530 /* Clear out the shortcuts. */
1531 chain
->n_reloads
= 0;
1532 chain
->need_elim
= 0;
1533 chain
->need_reload
= 0;
1534 chain
->need_operand_change
= 0;
1536 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1537 include REG_LABEL_OPERAND and REG_LABEL_TARGET), we need to see
1538 what effects this has on the known offsets at labels. */
1540 if (LABEL_P (insn
) || JUMP_P (insn
)
1541 || (INSN_P (insn
) && REG_NOTES (insn
) != 0))
1542 set_label_offsets (insn
, insn
, 0);
1546 rtx old_body
= PATTERN (insn
);
1547 int old_code
= INSN_CODE (insn
);
1548 rtx old_notes
= REG_NOTES (insn
);
1549 int did_elimination
= 0;
1550 int operands_changed
= 0;
1551 rtx set
= single_set (insn
);
1553 /* Skip insns that only set an equivalence. */
1554 if (set
&& REG_P (SET_DEST (set
))
1555 && reg_renumber
[REGNO (SET_DEST (set
))] < 0
1556 && (reg_equiv_constant
[REGNO (SET_DEST (set
))]
1557 || (reg_equiv_invariant
[REGNO (SET_DEST (set
))]))
1558 && reg_equiv_init
[REGNO (SET_DEST (set
))])
1561 /* If needed, eliminate any eliminable registers. */
1562 if (num_eliminable
|| num_eliminable_invariants
)
1563 did_elimination
= eliminate_regs_in_insn (insn
, 0);
1565 /* Analyze the instruction. */
1566 operands_changed
= find_reloads (insn
, 0, spill_indirect_levels
,
1567 global
, spill_reg_order
);
1569 /* If a no-op set needs more than one reload, this is likely
1570 to be something that needs input address reloads. We
1571 can't get rid of this cleanly later, and it is of no use
1572 anyway, so discard it now.
1573 We only do this when expensive_optimizations is enabled,
1574 since this complements reload inheritance / output
1575 reload deletion, and it can make debugging harder. */
1576 if (flag_expensive_optimizations
&& n_reloads
> 1)
1578 rtx set
= single_set (insn
);
1580 && SET_SRC (set
) == SET_DEST (set
)
1581 && REG_P (SET_SRC (set
))
1582 && REGNO (SET_SRC (set
)) >= FIRST_PSEUDO_REGISTER
)
1585 /* Delete it from the reload chain. */
1587 chain
->prev
->next
= next
;
1589 reload_insn_chain
= next
;
1591 next
->prev
= chain
->prev
;
1592 chain
->next
= unused_insn_chains
;
1593 unused_insn_chains
= chain
;
1598 update_eliminable_offsets ();
1600 /* Remember for later shortcuts which insns had any reloads or
1601 register eliminations. */
1602 chain
->need_elim
= did_elimination
;
1603 chain
->need_reload
= n_reloads
> 0;
1604 chain
->need_operand_change
= operands_changed
;
1606 /* Discard any register replacements done. */
1607 if (did_elimination
)
1609 obstack_free (&reload_obstack
, reload_insn_firstobj
);
1610 PATTERN (insn
) = old_body
;
1611 INSN_CODE (insn
) = old_code
;
1612 REG_NOTES (insn
) = old_notes
;
1613 something_needs_elimination
= 1;
1616 something_needs_operands_changed
|= operands_changed
;
1620 copy_reloads (chain
);
1621 *pprev_reload
= chain
;
1622 pprev_reload
= &chain
->next_need_reload
;
1629 /* Comparison function for qsort to decide which of two reloads
1630 should be handled first. *P1 and *P2 are the reload numbers. */
1633 reload_reg_class_lower (const void *r1p
, const void *r2p
)
1635 int r1
= *(const short *) r1p
, r2
= *(const short *) r2p
;
1638 /* Consider required reloads before optional ones. */
1639 t
= rld
[r1
].optional
- rld
[r2
].optional
;
1643 /* Count all solitary classes before non-solitary ones. */
1644 t
= ((reg_class_size
[(int) rld
[r2
].class] == 1)
1645 - (reg_class_size
[(int) rld
[r1
].class] == 1));
1649 /* Aside from solitaires, consider all multi-reg groups first. */
1650 t
= rld
[r2
].nregs
- rld
[r1
].nregs
;
1654 /* Consider reloads in order of increasing reg-class number. */
1655 t
= (int) rld
[r1
].class - (int) rld
[r2
].class;
1659 /* If reloads are equally urgent, sort by reload number,
1660 so that the results of qsort leave nothing to chance. */
1664 /* The cost of spilling each hard reg. */
1665 static int spill_cost
[FIRST_PSEUDO_REGISTER
];
1667 /* When spilling multiple hard registers, we use SPILL_COST for the first
1668 spilled hard reg and SPILL_ADD_COST for subsequent regs. SPILL_ADD_COST
1669 only the first hard reg for a multi-reg pseudo. */
1670 static int spill_add_cost
[FIRST_PSEUDO_REGISTER
];
1672 /* Update the spill cost arrays, considering that pseudo REG is live. */
1675 count_pseudo (int reg
)
1677 int freq
= REG_FREQ (reg
);
1678 int r
= reg_renumber
[reg
];
1681 if (REGNO_REG_SET_P (&pseudos_counted
, reg
)
1682 || REGNO_REG_SET_P (&spilled_pseudos
, reg
))
1685 SET_REGNO_REG_SET (&pseudos_counted
, reg
);
1687 gcc_assert (r
>= 0);
1689 spill_add_cost
[r
] += freq
;
1691 nregs
= hard_regno_nregs
[r
][PSEUDO_REGNO_MODE (reg
)];
1693 spill_cost
[r
+ nregs
] += freq
;
1696 /* Calculate the SPILL_COST and SPILL_ADD_COST arrays and determine the
1697 contents of BAD_SPILL_REGS for the insn described by CHAIN. */
1700 order_regs_for_reload (struct insn_chain
*chain
)
1703 HARD_REG_SET used_by_pseudos
;
1704 HARD_REG_SET used_by_pseudos2
;
1705 reg_set_iterator rsi
;
1707 COPY_HARD_REG_SET (bad_spill_regs
, fixed_reg_set
);
1709 memset (spill_cost
, 0, sizeof spill_cost
);
1710 memset (spill_add_cost
, 0, sizeof spill_add_cost
);
1712 /* Count number of uses of each hard reg by pseudo regs allocated to it
1713 and then order them by decreasing use. First exclude hard registers
1714 that are live in or across this insn. */
1716 REG_SET_TO_HARD_REG_SET (used_by_pseudos
, &chain
->live_throughout
);
1717 REG_SET_TO_HARD_REG_SET (used_by_pseudos2
, &chain
->dead_or_set
);
1718 IOR_HARD_REG_SET (bad_spill_regs
, used_by_pseudos
);
1719 IOR_HARD_REG_SET (bad_spill_regs
, used_by_pseudos2
);
1721 /* Now find out which pseudos are allocated to it, and update
1723 CLEAR_REG_SET (&pseudos_counted
);
1725 EXECUTE_IF_SET_IN_REG_SET
1726 (&chain
->live_throughout
, FIRST_PSEUDO_REGISTER
, i
, rsi
)
1730 EXECUTE_IF_SET_IN_REG_SET
1731 (&chain
->dead_or_set
, FIRST_PSEUDO_REGISTER
, i
, rsi
)
1735 CLEAR_REG_SET (&pseudos_counted
);
1738 /* Vector of reload-numbers showing the order in which the reloads should
1740 static short reload_order
[MAX_RELOADS
];
1742 /* This is used to keep track of the spill regs used in one insn. */
1743 static HARD_REG_SET used_spill_regs_local
;
1745 /* We decided to spill hard register SPILLED, which has a size of
1746 SPILLED_NREGS. Determine how pseudo REG, which is live during the insn,
1747 is affected. We will add it to SPILLED_PSEUDOS if necessary, and we will
1748 update SPILL_COST/SPILL_ADD_COST. */
1751 count_spilled_pseudo (int spilled
, int spilled_nregs
, int reg
)
1753 int r
= reg_renumber
[reg
];
1754 int nregs
= hard_regno_nregs
[r
][PSEUDO_REGNO_MODE (reg
)];
1756 if (REGNO_REG_SET_P (&spilled_pseudos
, reg
)
1757 || spilled
+ spilled_nregs
<= r
|| r
+ nregs
<= spilled
)
1760 SET_REGNO_REG_SET (&spilled_pseudos
, reg
);
1762 spill_add_cost
[r
] -= REG_FREQ (reg
);
1764 spill_cost
[r
+ nregs
] -= REG_FREQ (reg
);
1767 /* Find reload register to use for reload number ORDER. */
1770 find_reg (struct insn_chain
*chain
, int order
)
1772 int rnum
= reload_order
[order
];
1773 struct reload
*rl
= rld
+ rnum
;
1774 int best_cost
= INT_MAX
;
1778 HARD_REG_SET not_usable
;
1779 HARD_REG_SET used_by_other_reload
;
1780 reg_set_iterator rsi
;
1782 COPY_HARD_REG_SET (not_usable
, bad_spill_regs
);
1783 IOR_HARD_REG_SET (not_usable
, bad_spill_regs_global
);
1784 IOR_COMPL_HARD_REG_SET (not_usable
, reg_class_contents
[rl
->class]);
1786 CLEAR_HARD_REG_SET (used_by_other_reload
);
1787 for (k
= 0; k
< order
; k
++)
1789 int other
= reload_order
[k
];
1791 if (rld
[other
].regno
>= 0 && reloads_conflict (other
, rnum
))
1792 for (j
= 0; j
< rld
[other
].nregs
; j
++)
1793 SET_HARD_REG_BIT (used_by_other_reload
, rld
[other
].regno
+ j
);
1796 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1798 unsigned int regno
= i
;
1800 if (! TEST_HARD_REG_BIT (not_usable
, regno
)
1801 && ! TEST_HARD_REG_BIT (used_by_other_reload
, regno
)
1802 && HARD_REGNO_MODE_OK (regno
, rl
->mode
))
1804 int this_cost
= spill_cost
[regno
];
1806 unsigned int this_nregs
= hard_regno_nregs
[regno
][rl
->mode
];
1808 for (j
= 1; j
< this_nregs
; j
++)
1810 this_cost
+= spill_add_cost
[regno
+ j
];
1811 if ((TEST_HARD_REG_BIT (not_usable
, regno
+ j
))
1812 || TEST_HARD_REG_BIT (used_by_other_reload
, regno
+ j
))
1817 if (rl
->in
&& REG_P (rl
->in
) && REGNO (rl
->in
) == regno
)
1819 if (rl
->out
&& REG_P (rl
->out
) && REGNO (rl
->out
) == regno
)
1821 if (this_cost
< best_cost
1822 /* Among registers with equal cost, prefer caller-saved ones, or
1823 use REG_ALLOC_ORDER if it is defined. */
1824 || (this_cost
== best_cost
1825 #ifdef REG_ALLOC_ORDER
1826 && (inv_reg_alloc_order
[regno
]
1827 < inv_reg_alloc_order
[best_reg
])
1829 && call_used_regs
[regno
]
1830 && ! call_used_regs
[best_reg
]
1835 best_cost
= this_cost
;
1843 fprintf (dump_file
, "Using reg %d for reload %d\n", best_reg
, rnum
);
1845 rl
->nregs
= hard_regno_nregs
[best_reg
][rl
->mode
];
1846 rl
->regno
= best_reg
;
1848 EXECUTE_IF_SET_IN_REG_SET
1849 (&chain
->live_throughout
, FIRST_PSEUDO_REGISTER
, j
, rsi
)
1851 count_spilled_pseudo (best_reg
, rl
->nregs
, j
);
1854 EXECUTE_IF_SET_IN_REG_SET
1855 (&chain
->dead_or_set
, FIRST_PSEUDO_REGISTER
, j
, rsi
)
1857 count_spilled_pseudo (best_reg
, rl
->nregs
, j
);
1860 for (i
= 0; i
< rl
->nregs
; i
++)
1862 gcc_assert (spill_cost
[best_reg
+ i
] == 0);
1863 gcc_assert (spill_add_cost
[best_reg
+ i
] == 0);
1864 SET_HARD_REG_BIT (used_spill_regs_local
, best_reg
+ i
);
1869 /* Find more reload regs to satisfy the remaining need of an insn, which
1871 Do it by ascending class number, since otherwise a reg
1872 might be spilled for a big class and might fail to count
1873 for a smaller class even though it belongs to that class. */
1876 find_reload_regs (struct insn_chain
*chain
)
1880 /* In order to be certain of getting the registers we need,
1881 we must sort the reloads into order of increasing register class.
1882 Then our grabbing of reload registers will parallel the process
1883 that provided the reload registers. */
1884 for (i
= 0; i
< chain
->n_reloads
; i
++)
1886 /* Show whether this reload already has a hard reg. */
1887 if (chain
->rld
[i
].reg_rtx
)
1889 int regno
= REGNO (chain
->rld
[i
].reg_rtx
);
1890 chain
->rld
[i
].regno
= regno
;
1892 = hard_regno_nregs
[regno
][GET_MODE (chain
->rld
[i
].reg_rtx
)];
1895 chain
->rld
[i
].regno
= -1;
1896 reload_order
[i
] = i
;
1899 n_reloads
= chain
->n_reloads
;
1900 memcpy (rld
, chain
->rld
, n_reloads
* sizeof (struct reload
));
1902 CLEAR_HARD_REG_SET (used_spill_regs_local
);
1905 fprintf (dump_file
, "Spilling for insn %d.\n", INSN_UID (chain
->insn
));
1907 qsort (reload_order
, n_reloads
, sizeof (short), reload_reg_class_lower
);
1909 /* Compute the order of preference for hard registers to spill. */
1911 order_regs_for_reload (chain
);
1913 for (i
= 0; i
< n_reloads
; i
++)
1915 int r
= reload_order
[i
];
1917 /* Ignore reloads that got marked inoperative. */
1918 if ((rld
[r
].out
!= 0 || rld
[r
].in
!= 0 || rld
[r
].secondary_p
)
1919 && ! rld
[r
].optional
1920 && rld
[r
].regno
== -1)
1921 if (! find_reg (chain
, i
))
1924 fprintf (dump_file
, "reload failure for reload %d\n", r
);
1925 spill_failure (chain
->insn
, rld
[r
].class);
1931 COPY_HARD_REG_SET (chain
->used_spill_regs
, used_spill_regs_local
);
1932 IOR_HARD_REG_SET (used_spill_regs
, used_spill_regs_local
);
1934 memcpy (chain
->rld
, rld
, n_reloads
* sizeof (struct reload
));
1938 select_reload_regs (void)
1940 struct insn_chain
*chain
;
1942 /* Try to satisfy the needs for each insn. */
1943 for (chain
= insns_need_reload
; chain
!= 0;
1944 chain
= chain
->next_need_reload
)
1945 find_reload_regs (chain
);
1948 /* Delete all insns that were inserted by emit_caller_save_insns during
1951 delete_caller_save_insns (void)
1953 struct insn_chain
*c
= reload_insn_chain
;
1957 while (c
!= 0 && c
->is_caller_save_insn
)
1959 struct insn_chain
*next
= c
->next
;
1962 if (c
== reload_insn_chain
)
1963 reload_insn_chain
= next
;
1967 next
->prev
= c
->prev
;
1969 c
->prev
->next
= next
;
1970 c
->next
= unused_insn_chains
;
1971 unused_insn_chains
= c
;
1979 /* Handle the failure to find a register to spill.
1980 INSN should be one of the insns which needed this particular spill reg. */
1983 spill_failure (rtx insn
, enum reg_class
class)
1985 if (asm_noperands (PATTERN (insn
)) >= 0)
1986 error_for_asm (insn
, "can't find a register in class %qs while "
1987 "reloading %<asm%>",
1988 reg_class_names
[class]);
1991 error ("unable to find a register to spill in class %qs",
1992 reg_class_names
[class]);
1996 fprintf (dump_file
, "\nReloads for insn # %d\n", INSN_UID (insn
));
1997 debug_reload_to_stream (dump_file
);
1999 fatal_insn ("this is the insn:", insn
);
2003 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
2004 data that is dead in INSN. */
2007 delete_dead_insn (rtx insn
)
2009 rtx prev
= prev_real_insn (insn
);
2012 /* If the previous insn sets a register that dies in our insn, delete it
2014 if (prev
&& GET_CODE (PATTERN (prev
)) == SET
2015 && (prev_dest
= SET_DEST (PATTERN (prev
)), REG_P (prev_dest
))
2016 && reg_mentioned_p (prev_dest
, PATTERN (insn
))
2017 && find_regno_note (insn
, REG_DEAD
, REGNO (prev_dest
))
2018 && ! side_effects_p (SET_SRC (PATTERN (prev
))))
2019 delete_dead_insn (prev
);
2021 SET_INSN_DELETED (insn
);
2024 /* Modify the home of pseudo-reg I.
2025 The new home is present in reg_renumber[I].
2027 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
2028 or it may be -1, meaning there is none or it is not relevant.
2029 This is used so that all pseudos spilled from a given hard reg
2030 can share one stack slot. */
2033 alter_reg (int i
, int from_reg
)
2035 /* When outputting an inline function, this can happen
2036 for a reg that isn't actually used. */
2037 if (regno_reg_rtx
[i
] == 0)
2040 /* If the reg got changed to a MEM at rtl-generation time,
2042 if (!REG_P (regno_reg_rtx
[i
]))
2045 /* Modify the reg-rtx to contain the new hard reg
2046 number or else to contain its pseudo reg number. */
2047 SET_REGNO (regno_reg_rtx
[i
],
2048 reg_renumber
[i
] >= 0 ? reg_renumber
[i
] : i
);
2050 /* If we have a pseudo that is needed but has no hard reg or equivalent,
2051 allocate a stack slot for it. */
2053 if (reg_renumber
[i
] < 0
2054 && REG_N_REFS (i
) > 0
2055 && reg_equiv_constant
[i
] == 0
2056 && (reg_equiv_invariant
[i
] == 0 || reg_equiv_init
[i
] == 0)
2057 && reg_equiv_memory_loc
[i
] == 0)
2060 enum machine_mode mode
= GET_MODE (regno_reg_rtx
[i
]);
2061 unsigned int inherent_size
= PSEUDO_REGNO_BYTES (i
);
2062 unsigned int inherent_align
= GET_MODE_ALIGNMENT (mode
);
2063 unsigned int total_size
= MAX (inherent_size
, reg_max_ref_width
[i
]);
2064 unsigned int min_align
= reg_max_ref_width
[i
] * BITS_PER_UNIT
;
2067 /* Each pseudo reg has an inherent size which comes from its own mode,
2068 and a total size which provides room for paradoxical subregs
2069 which refer to the pseudo reg in wider modes.
2071 We can use a slot already allocated if it provides both
2072 enough inherent space and enough total space.
2073 Otherwise, we allocate a new slot, making sure that it has no less
2074 inherent space, and no less total space, then the previous slot. */
2077 alias_set_type alias_set
= new_alias_set ();
2079 /* No known place to spill from => no slot to reuse. */
2080 x
= assign_stack_local (mode
, total_size
,
2081 min_align
> inherent_align
2082 || total_size
> inherent_size
? -1 : 0);
2083 if (BYTES_BIG_ENDIAN
)
2084 /* Cancel the big-endian correction done in assign_stack_local.
2085 Get the address of the beginning of the slot.
2086 This is so we can do a big-endian correction unconditionally
2088 adjust
= inherent_size
- total_size
;
2090 /* Nothing can alias this slot except this pseudo. */
2091 set_mem_alias_set (x
, alias_set
);
2092 dse_record_singleton_alias_set (alias_set
, mode
);
2095 /* Reuse a stack slot if possible. */
2096 else if (spill_stack_slot
[from_reg
] != 0
2097 && spill_stack_slot_width
[from_reg
] >= total_size
2098 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot
[from_reg
]))
2100 && MEM_ALIGN (spill_stack_slot
[from_reg
]) >= min_align
)
2101 x
= spill_stack_slot
[from_reg
];
2102 /* Allocate a bigger slot. */
2105 /* Compute maximum size needed, both for inherent size
2106 and for total size. */
2109 if (spill_stack_slot
[from_reg
])
2111 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot
[from_reg
]))
2113 mode
= GET_MODE (spill_stack_slot
[from_reg
]);
2114 if (spill_stack_slot_width
[from_reg
] > total_size
)
2115 total_size
= spill_stack_slot_width
[from_reg
];
2116 if (MEM_ALIGN (spill_stack_slot
[from_reg
]) > min_align
)
2117 min_align
= MEM_ALIGN (spill_stack_slot
[from_reg
]);
2120 /* Make a slot with that size. */
2121 x
= assign_stack_local (mode
, total_size
,
2122 min_align
> inherent_align
2123 || total_size
> inherent_size
? -1 : 0);
2126 /* All pseudos mapped to this slot can alias each other. */
2127 if (spill_stack_slot
[from_reg
])
2129 alias_set_type alias_set
2130 = MEM_ALIAS_SET (spill_stack_slot
[from_reg
]);
2131 set_mem_alias_set (x
, alias_set
);
2132 dse_invalidate_singleton_alias_set (alias_set
);
2136 alias_set_type alias_set
= new_alias_set ();
2137 set_mem_alias_set (x
, alias_set
);
2138 dse_record_singleton_alias_set (alias_set
, mode
);
2141 if (BYTES_BIG_ENDIAN
)
2143 /* Cancel the big-endian correction done in assign_stack_local.
2144 Get the address of the beginning of the slot.
2145 This is so we can do a big-endian correction unconditionally
2147 adjust
= GET_MODE_SIZE (mode
) - total_size
;
2150 = adjust_address_nv (x
, mode_for_size (total_size
2156 spill_stack_slot
[from_reg
] = stack_slot
;
2157 spill_stack_slot_width
[from_reg
] = total_size
;
2160 /* On a big endian machine, the "address" of the slot
2161 is the address of the low part that fits its inherent mode. */
2162 if (BYTES_BIG_ENDIAN
&& inherent_size
< total_size
)
2163 adjust
+= (total_size
- inherent_size
);
2165 /* If we have any adjustment to make, or if the stack slot is the
2166 wrong mode, make a new stack slot. */
2167 x
= adjust_address_nv (x
, GET_MODE (regno_reg_rtx
[i
]), adjust
);
2169 /* If we have a decl for the original register, set it for the
2170 memory. If this is a shared MEM, make a copy. */
2171 if (REG_EXPR (regno_reg_rtx
[i
])
2172 && DECL_P (REG_EXPR (regno_reg_rtx
[i
])))
2174 rtx decl
= DECL_RTL_IF_SET (REG_EXPR (regno_reg_rtx
[i
]));
2176 /* We can do this only for the DECLs home pseudo, not for
2177 any copies of it, since otherwise when the stack slot
2178 is reused, nonoverlapping_memrefs_p might think they
2180 if (decl
&& REG_P (decl
) && REGNO (decl
) == (unsigned) i
)
2182 if (from_reg
!= -1 && spill_stack_slot
[from_reg
] == x
)
2185 set_mem_attrs_from_reg (x
, regno_reg_rtx
[i
]);
2189 /* Save the stack slot for later. */
2190 reg_equiv_memory_loc
[i
] = x
;
2194 /* Mark the slots in regs_ever_live for the hard regs used by
2195 pseudo-reg number REGNO, accessed in MODE. */
2198 mark_home_live_1 (int regno
, enum machine_mode mode
)
2202 i
= reg_renumber
[regno
];
2205 lim
= end_hard_regno (mode
, i
);
2207 df_set_regs_ever_live(i
++, true);
2210 /* Mark the slots in regs_ever_live for the hard regs
2211 used by pseudo-reg number REGNO. */
2214 mark_home_live (int regno
)
2216 if (reg_renumber
[regno
] >= 0)
2217 mark_home_live_1 (regno
, PSEUDO_REGNO_MODE (regno
));
2220 /* This function handles the tracking of elimination offsets around branches.
2222 X is a piece of RTL being scanned.
2224 INSN is the insn that it came from, if any.
2226 INITIAL_P is nonzero if we are to set the offset to be the initial
2227 offset and zero if we are setting the offset of the label to be the
2231 set_label_offsets (rtx x
, rtx insn
, int initial_p
)
2233 enum rtx_code code
= GET_CODE (x
);
2236 struct elim_table
*p
;
2241 if (LABEL_REF_NONLOCAL_P (x
))
2246 /* ... fall through ... */
2249 /* If we know nothing about this label, set the desired offsets. Note
2250 that this sets the offset at a label to be the offset before a label
2251 if we don't know anything about the label. This is not correct for
2252 the label after a BARRIER, but is the best guess we can make. If
2253 we guessed wrong, we will suppress an elimination that might have
2254 been possible had we been able to guess correctly. */
2256 if (! offsets_known_at
[CODE_LABEL_NUMBER (x
) - first_label_num
])
2258 for (i
= 0; i
< NUM_ELIMINABLE_REGS
; i
++)
2259 offsets_at
[CODE_LABEL_NUMBER (x
) - first_label_num
][i
]
2260 = (initial_p
? reg_eliminate
[i
].initial_offset
2261 : reg_eliminate
[i
].offset
);
2262 offsets_known_at
[CODE_LABEL_NUMBER (x
) - first_label_num
] = 1;
2265 /* Otherwise, if this is the definition of a label and it is
2266 preceded by a BARRIER, set our offsets to the known offset of
2270 && (tem
= prev_nonnote_insn (insn
)) != 0
2272 set_offsets_for_label (insn
);
2274 /* If neither of the above cases is true, compare each offset
2275 with those previously recorded and suppress any eliminations
2276 where the offsets disagree. */
2278 for (i
= 0; i
< NUM_ELIMINABLE_REGS
; i
++)
2279 if (offsets_at
[CODE_LABEL_NUMBER (x
) - first_label_num
][i
]
2280 != (initial_p
? reg_eliminate
[i
].initial_offset
2281 : reg_eliminate
[i
].offset
))
2282 reg_eliminate
[i
].can_eliminate
= 0;
2287 set_label_offsets (PATTERN (insn
), insn
, initial_p
);
2289 /* ... fall through ... */
2293 /* Any labels mentioned in REG_LABEL_OPERAND notes can be branched
2294 to indirectly and hence must have all eliminations at their
2296 for (tem
= REG_NOTES (x
); tem
; tem
= XEXP (tem
, 1))
2297 if (REG_NOTE_KIND (tem
) == REG_LABEL_OPERAND
)
2298 set_label_offsets (XEXP (tem
, 0), insn
, 1);
2304 /* Each of the labels in the parallel or address vector must be
2305 at their initial offsets. We want the first field for PARALLEL
2306 and ADDR_VEC and the second field for ADDR_DIFF_VEC. */
2308 for (i
= 0; i
< (unsigned) XVECLEN (x
, code
== ADDR_DIFF_VEC
); i
++)
2309 set_label_offsets (XVECEXP (x
, code
== ADDR_DIFF_VEC
, i
),
2314 /* We only care about setting PC. If the source is not RETURN,
2315 IF_THEN_ELSE, or a label, disable any eliminations not at
2316 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2317 isn't one of those possibilities. For branches to a label,
2318 call ourselves recursively.
2320 Note that this can disable elimination unnecessarily when we have
2321 a non-local goto since it will look like a non-constant jump to
2322 someplace in the current function. This isn't a significant
2323 problem since such jumps will normally be when all elimination
2324 pairs are back to their initial offsets. */
2326 if (SET_DEST (x
) != pc_rtx
)
2329 switch (GET_CODE (SET_SRC (x
)))
2336 set_label_offsets (SET_SRC (x
), insn
, initial_p
);
2340 tem
= XEXP (SET_SRC (x
), 1);
2341 if (GET_CODE (tem
) == LABEL_REF
)
2342 set_label_offsets (XEXP (tem
, 0), insn
, initial_p
);
2343 else if (GET_CODE (tem
) != PC
&& GET_CODE (tem
) != RETURN
)
2346 tem
= XEXP (SET_SRC (x
), 2);
2347 if (GET_CODE (tem
) == LABEL_REF
)
2348 set_label_offsets (XEXP (tem
, 0), insn
, initial_p
);
2349 else if (GET_CODE (tem
) != PC
&& GET_CODE (tem
) != RETURN
)
2357 /* If we reach here, all eliminations must be at their initial
2358 offset because we are doing a jump to a variable address. */
2359 for (p
= reg_eliminate
; p
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; p
++)
2360 if (p
->offset
!= p
->initial_offset
)
2361 p
->can_eliminate
= 0;
2369 /* Scan X and replace any eliminable registers (such as fp) with a
2370 replacement (such as sp), plus an offset.
2372 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2373 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2374 MEM, we are allowed to replace a sum of a register and the constant zero
2375 with the register, which we cannot do outside a MEM. In addition, we need
2376 to record the fact that a register is referenced outside a MEM.
2378 If INSN is an insn, it is the insn containing X. If we replace a REG
2379 in a SET_DEST with an equivalent MEM and INSN is nonzero, write a
2380 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2381 the REG is being modified.
2383 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2384 That's used when we eliminate in expressions stored in notes.
2385 This means, do not set ref_outside_mem even if the reference
2388 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2389 replacements done assuming all offsets are at their initial values. If
2390 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2391 encounter, return the actual location so that find_reloads will do
2392 the proper thing. */
2395 eliminate_regs_1 (rtx x
, enum machine_mode mem_mode
, rtx insn
,
2396 bool may_use_invariant
)
2398 enum rtx_code code
= GET_CODE (x
);
2399 struct elim_table
*ep
;
2406 if (! current_function_decl
)
2429 /* First handle the case where we encounter a bare register that
2430 is eliminable. Replace it with a PLUS. */
2431 if (regno
< FIRST_PSEUDO_REGISTER
)
2433 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
2435 if (ep
->from_rtx
== x
&& ep
->can_eliminate
)
2436 return plus_constant (ep
->to_rtx
, ep
->previous_offset
);
2439 else if (reg_renumber
&& reg_renumber
[regno
] < 0
2440 && reg_equiv_invariant
&& reg_equiv_invariant
[regno
])
2442 if (may_use_invariant
)
2443 return eliminate_regs_1 (copy_rtx (reg_equiv_invariant
[regno
]),
2444 mem_mode
, insn
, true);
2445 /* There exists at least one use of REGNO that cannot be
2446 eliminated. Prevent the defining insn from being deleted. */
2447 reg_equiv_init
[regno
] = NULL_RTX
;
2448 alter_reg (regno
, -1);
2452 /* You might think handling MINUS in a manner similar to PLUS is a
2453 good idea. It is not. It has been tried multiple times and every
2454 time the change has had to have been reverted.
2456 Other parts of reload know a PLUS is special (gen_reload for example)
2457 and require special code to handle code a reloaded PLUS operand.
2459 Also consider backends where the flags register is clobbered by a
2460 MINUS, but we can emit a PLUS that does not clobber flags (IA-32,
2461 lea instruction comes to mind). If we try to reload a MINUS, we
2462 may kill the flags register that was holding a useful value.
2464 So, please before trying to handle MINUS, consider reload as a
2465 whole instead of this little section as well as the backend issues. */
2467 /* If this is the sum of an eliminable register and a constant, rework
2469 if (REG_P (XEXP (x
, 0))
2470 && REGNO (XEXP (x
, 0)) < FIRST_PSEUDO_REGISTER
2471 && CONSTANT_P (XEXP (x
, 1)))
2473 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
2475 if (ep
->from_rtx
== XEXP (x
, 0) && ep
->can_eliminate
)
2477 /* The only time we want to replace a PLUS with a REG (this
2478 occurs when the constant operand of the PLUS is the negative
2479 of the offset) is when we are inside a MEM. We won't want
2480 to do so at other times because that would change the
2481 structure of the insn in a way that reload can't handle.
2482 We special-case the commonest situation in
2483 eliminate_regs_in_insn, so just replace a PLUS with a
2484 PLUS here, unless inside a MEM. */
2485 if (mem_mode
!= 0 && GET_CODE (XEXP (x
, 1)) == CONST_INT
2486 && INTVAL (XEXP (x
, 1)) == - ep
->previous_offset
)
2489 return gen_rtx_PLUS (Pmode
, ep
->to_rtx
,
2490 plus_constant (XEXP (x
, 1),
2491 ep
->previous_offset
));
2494 /* If the register is not eliminable, we are done since the other
2495 operand is a constant. */
2499 /* If this is part of an address, we want to bring any constant to the
2500 outermost PLUS. We will do this by doing register replacement in
2501 our operands and seeing if a constant shows up in one of them.
2503 Note that there is no risk of modifying the structure of the insn,
2504 since we only get called for its operands, thus we are either
2505 modifying the address inside a MEM, or something like an address
2506 operand of a load-address insn. */
2509 rtx new0
= eliminate_regs_1 (XEXP (x
, 0), mem_mode
, insn
, true);
2510 rtx new1
= eliminate_regs_1 (XEXP (x
, 1), mem_mode
, insn
, true);
2512 if (reg_renumber
&& (new0
!= XEXP (x
, 0) || new1
!= XEXP (x
, 1)))
2514 /* If one side is a PLUS and the other side is a pseudo that
2515 didn't get a hard register but has a reg_equiv_constant,
2516 we must replace the constant here since it may no longer
2517 be in the position of any operand. */
2518 if (GET_CODE (new0
) == PLUS
&& REG_P (new1
)
2519 && REGNO (new1
) >= FIRST_PSEUDO_REGISTER
2520 && reg_renumber
[REGNO (new1
)] < 0
2521 && reg_equiv_constant
!= 0
2522 && reg_equiv_constant
[REGNO (new1
)] != 0)
2523 new1
= reg_equiv_constant
[REGNO (new1
)];
2524 else if (GET_CODE (new1
) == PLUS
&& REG_P (new0
)
2525 && REGNO (new0
) >= FIRST_PSEUDO_REGISTER
2526 && reg_renumber
[REGNO (new0
)] < 0
2527 && reg_equiv_constant
[REGNO (new0
)] != 0)
2528 new0
= reg_equiv_constant
[REGNO (new0
)];
2530 new = form_sum (new0
, new1
);
2532 /* As above, if we are not inside a MEM we do not want to
2533 turn a PLUS into something else. We might try to do so here
2534 for an addition of 0 if we aren't optimizing. */
2535 if (! mem_mode
&& GET_CODE (new) != PLUS
)
2536 return gen_rtx_PLUS (GET_MODE (x
), new, const0_rtx
);
2544 /* If this is the product of an eliminable register and a
2545 constant, apply the distribute law and move the constant out
2546 so that we have (plus (mult ..) ..). This is needed in order
2547 to keep load-address insns valid. This case is pathological.
2548 We ignore the possibility of overflow here. */
2549 if (REG_P (XEXP (x
, 0))
2550 && REGNO (XEXP (x
, 0)) < FIRST_PSEUDO_REGISTER
2551 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
2552 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
2554 if (ep
->from_rtx
== XEXP (x
, 0) && ep
->can_eliminate
)
2557 /* Refs inside notes don't count for this purpose. */
2558 && ! (insn
!= 0 && (GET_CODE (insn
) == EXPR_LIST
2559 || GET_CODE (insn
) == INSN_LIST
)))
2560 ep
->ref_outside_mem
= 1;
2563 plus_constant (gen_rtx_MULT (Pmode
, ep
->to_rtx
, XEXP (x
, 1)),
2564 ep
->previous_offset
* INTVAL (XEXP (x
, 1)));
2567 /* ... fall through ... */
2571 /* See comments before PLUS about handling MINUS. */
2573 case DIV
: case UDIV
:
2574 case MOD
: case UMOD
:
2575 case AND
: case IOR
: case XOR
:
2576 case ROTATERT
: case ROTATE
:
2577 case ASHIFTRT
: case LSHIFTRT
: case ASHIFT
:
2579 case GE
: case GT
: case GEU
: case GTU
:
2580 case LE
: case LT
: case LEU
: case LTU
:
2582 rtx new0
= eliminate_regs_1 (XEXP (x
, 0), mem_mode
, insn
, false);
2583 rtx new1
= XEXP (x
, 1)
2584 ? eliminate_regs_1 (XEXP (x
, 1), mem_mode
, insn
, false) : 0;
2586 if (new0
!= XEXP (x
, 0) || new1
!= XEXP (x
, 1))
2587 return gen_rtx_fmt_ee (code
, GET_MODE (x
), new0
, new1
);
2592 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2595 new = eliminate_regs_1 (XEXP (x
, 0), mem_mode
, insn
, true);
2596 if (new != XEXP (x
, 0))
2598 /* If this is a REG_DEAD note, it is not valid anymore.
2599 Using the eliminated version could result in creating a
2600 REG_DEAD note for the stack or frame pointer. */
2601 if (GET_MODE (x
) == REG_DEAD
)
2603 ? eliminate_regs_1 (XEXP (x
, 1), mem_mode
, insn
, true)
2606 x
= gen_rtx_EXPR_LIST (REG_NOTE_KIND (x
), new, XEXP (x
, 1));
2610 /* ... fall through ... */
2613 /* Now do eliminations in the rest of the chain. If this was
2614 an EXPR_LIST, this might result in allocating more memory than is
2615 strictly needed, but it simplifies the code. */
2618 new = eliminate_regs_1 (XEXP (x
, 1), mem_mode
, insn
, true);
2619 if (new != XEXP (x
, 1))
2621 gen_rtx_fmt_ee (GET_CODE (x
), GET_MODE (x
), XEXP (x
, 0), new);
2629 /* We do not support elimination of a register that is modified.
2630 elimination_effects has already make sure that this does not
2636 /* We do not support elimination of a register that is modified.
2637 elimination_effects has already make sure that this does not
2638 happen. The only remaining case we need to consider here is
2639 that the increment value may be an eliminable register. */
2640 if (GET_CODE (XEXP (x
, 1)) == PLUS
2641 && XEXP (XEXP (x
, 1), 0) == XEXP (x
, 0))
2643 rtx
new = eliminate_regs_1 (XEXP (XEXP (x
, 1), 1), mem_mode
,
2646 if (new != XEXP (XEXP (x
, 1), 1))
2647 return gen_rtx_fmt_ee (code
, GET_MODE (x
), XEXP (x
, 0),
2648 gen_rtx_PLUS (GET_MODE (x
),
2653 case STRICT_LOW_PART
:
2655 case SIGN_EXTEND
: case ZERO_EXTEND
:
2656 case TRUNCATE
: case FLOAT_EXTEND
: case FLOAT_TRUNCATE
:
2657 case FLOAT
: case FIX
:
2658 case UNSIGNED_FIX
: case UNSIGNED_FLOAT
:
2667 new = eliminate_regs_1 (XEXP (x
, 0), mem_mode
, insn
, false);
2668 if (new != XEXP (x
, 0))
2669 return gen_rtx_fmt_e (code
, GET_MODE (x
), new);
2673 /* Similar to above processing, but preserve SUBREG_BYTE.
2674 Convert (subreg (mem)) to (mem) if not paradoxical.
2675 Also, if we have a non-paradoxical (subreg (pseudo)) and the
2676 pseudo didn't get a hard reg, we must replace this with the
2677 eliminated version of the memory location because push_reload
2678 may do the replacement in certain circumstances. */
2679 if (REG_P (SUBREG_REG (x
))
2680 && (GET_MODE_SIZE (GET_MODE (x
))
2681 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
2682 && reg_equiv_memory_loc
!= 0
2683 && reg_equiv_memory_loc
[REGNO (SUBREG_REG (x
))] != 0)
2685 new = SUBREG_REG (x
);
2688 new = eliminate_regs_1 (SUBREG_REG (x
), mem_mode
, insn
, false);
2690 if (new != SUBREG_REG (x
))
2692 int x_size
= GET_MODE_SIZE (GET_MODE (x
));
2693 int new_size
= GET_MODE_SIZE (GET_MODE (new));
2696 && ((x_size
< new_size
2697 #ifdef WORD_REGISTER_OPERATIONS
2698 /* On these machines, combine can create rtl of the form
2699 (set (subreg:m1 (reg:m2 R) 0) ...)
2700 where m1 < m2, and expects something interesting to
2701 happen to the entire word. Moreover, it will use the
2702 (reg:m2 R) later, expecting all bits to be preserved.
2703 So if the number of words is the same, preserve the
2704 subreg so that push_reload can see it. */
2705 && ! ((x_size
- 1) / UNITS_PER_WORD
2706 == (new_size
-1 ) / UNITS_PER_WORD
)
2709 || x_size
== new_size
)
2711 return adjust_address_nv (new, GET_MODE (x
), SUBREG_BYTE (x
));
2713 return gen_rtx_SUBREG (GET_MODE (x
), new, SUBREG_BYTE (x
));
2719 /* Our only special processing is to pass the mode of the MEM to our
2720 recursive call and copy the flags. While we are here, handle this
2721 case more efficiently. */
2723 replace_equiv_address_nv (x
,
2724 eliminate_regs_1 (XEXP (x
, 0), GET_MODE (x
),
2728 /* Handle insn_list USE that a call to a pure function may generate. */
2729 new = eliminate_regs_1 (XEXP (x
, 0), 0, insn
, false);
2730 if (new != XEXP (x
, 0))
2731 return gen_rtx_USE (GET_MODE (x
), new);
2743 /* Process each of our operands recursively. If any have changed, make a
2745 fmt
= GET_RTX_FORMAT (code
);
2746 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++, fmt
++)
2750 new = eliminate_regs_1 (XEXP (x
, i
), mem_mode
, insn
, false);
2751 if (new != XEXP (x
, i
) && ! copied
)
2753 x
= shallow_copy_rtx (x
);
2758 else if (*fmt
== 'E')
2761 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
2763 new = eliminate_regs_1 (XVECEXP (x
, i
, j
), mem_mode
, insn
, false);
2764 if (new != XVECEXP (x
, i
, j
) && ! copied_vec
)
2766 rtvec new_v
= gen_rtvec_v (XVECLEN (x
, i
),
2770 x
= shallow_copy_rtx (x
);
2773 XVEC (x
, i
) = new_v
;
2776 XVECEXP (x
, i
, j
) = new;
2785 eliminate_regs (rtx x
, enum machine_mode mem_mode
, rtx insn
)
2787 return eliminate_regs_1 (x
, mem_mode
, insn
, false);
2790 /* Scan rtx X for modifications of elimination target registers. Update
2791 the table of eliminables to reflect the changed state. MEM_MODE is
2792 the mode of an enclosing MEM rtx, or VOIDmode if not within a MEM. */
2795 elimination_effects (rtx x
, enum machine_mode mem_mode
)
2797 enum rtx_code code
= GET_CODE (x
);
2798 struct elim_table
*ep
;
2823 /* First handle the case where we encounter a bare register that
2824 is eliminable. Replace it with a PLUS. */
2825 if (regno
< FIRST_PSEUDO_REGISTER
)
2827 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
2829 if (ep
->from_rtx
== x
&& ep
->can_eliminate
)
2832 ep
->ref_outside_mem
= 1;
2837 else if (reg_renumber
[regno
] < 0 && reg_equiv_constant
2838 && reg_equiv_constant
[regno
]
2839 && ! function_invariant_p (reg_equiv_constant
[regno
]))
2840 elimination_effects (reg_equiv_constant
[regno
], mem_mode
);
2849 /* If we modify the source of an elimination rule, disable it. */
2850 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
2851 if (ep
->from_rtx
== XEXP (x
, 0))
2852 ep
->can_eliminate
= 0;
2854 /* If we modify the target of an elimination rule by adding a constant,
2855 update its offset. If we modify the target in any other way, we'll
2856 have to disable the rule as well. */
2857 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
2858 if (ep
->to_rtx
== XEXP (x
, 0))
2860 int size
= GET_MODE_SIZE (mem_mode
);
2862 /* If more bytes than MEM_MODE are pushed, account for them. */
2863 #ifdef PUSH_ROUNDING
2864 if (ep
->to_rtx
== stack_pointer_rtx
)
2865 size
= PUSH_ROUNDING (size
);
2867 if (code
== PRE_DEC
|| code
== POST_DEC
)
2869 else if (code
== PRE_INC
|| code
== POST_INC
)
2871 else if (code
== PRE_MODIFY
|| code
== POST_MODIFY
)
2873 if (GET_CODE (XEXP (x
, 1)) == PLUS
2874 && XEXP (x
, 0) == XEXP (XEXP (x
, 1), 0)
2875 && CONST_INT_P (XEXP (XEXP (x
, 1), 1)))
2876 ep
->offset
-= INTVAL (XEXP (XEXP (x
, 1), 1));
2878 ep
->can_eliminate
= 0;
2882 /* These two aren't unary operators. */
2883 if (code
== POST_MODIFY
|| code
== PRE_MODIFY
)
2886 /* Fall through to generic unary operation case. */
2887 case STRICT_LOW_PART
:
2889 case SIGN_EXTEND
: case ZERO_EXTEND
:
2890 case TRUNCATE
: case FLOAT_EXTEND
: case FLOAT_TRUNCATE
:
2891 case FLOAT
: case FIX
:
2892 case UNSIGNED_FIX
: case UNSIGNED_FLOAT
:
2901 elimination_effects (XEXP (x
, 0), mem_mode
);
2905 if (REG_P (SUBREG_REG (x
))
2906 && (GET_MODE_SIZE (GET_MODE (x
))
2907 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
2908 && reg_equiv_memory_loc
!= 0
2909 && reg_equiv_memory_loc
[REGNO (SUBREG_REG (x
))] != 0)
2912 elimination_effects (SUBREG_REG (x
), mem_mode
);
2916 /* If using a register that is the source of an eliminate we still
2917 think can be performed, note it cannot be performed since we don't
2918 know how this register is used. */
2919 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
2920 if (ep
->from_rtx
== XEXP (x
, 0))
2921 ep
->can_eliminate
= 0;
2923 elimination_effects (XEXP (x
, 0), mem_mode
);
2927 /* If clobbering a register that is the replacement register for an
2928 elimination we still think can be performed, note that it cannot
2929 be performed. Otherwise, we need not be concerned about it. */
2930 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
2931 if (ep
->to_rtx
== XEXP (x
, 0))
2932 ep
->can_eliminate
= 0;
2934 elimination_effects (XEXP (x
, 0), mem_mode
);
2938 /* Check for setting a register that we know about. */
2939 if (REG_P (SET_DEST (x
)))
2941 /* See if this is setting the replacement register for an
2944 If DEST is the hard frame pointer, we do nothing because we
2945 assume that all assignments to the frame pointer are for
2946 non-local gotos and are being done at a time when they are valid
2947 and do not disturb anything else. Some machines want to
2948 eliminate a fake argument pointer (or even a fake frame pointer)
2949 with either the real frame or the stack pointer. Assignments to
2950 the hard frame pointer must not prevent this elimination. */
2952 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
2954 if (ep
->to_rtx
== SET_DEST (x
)
2955 && SET_DEST (x
) != hard_frame_pointer_rtx
)
2957 /* If it is being incremented, adjust the offset. Otherwise,
2958 this elimination can't be done. */
2959 rtx src
= SET_SRC (x
);
2961 if (GET_CODE (src
) == PLUS
2962 && XEXP (src
, 0) == SET_DEST (x
)
2963 && GET_CODE (XEXP (src
, 1)) == CONST_INT
)
2964 ep
->offset
-= INTVAL (XEXP (src
, 1));
2966 ep
->can_eliminate
= 0;
2970 elimination_effects (SET_DEST (x
), 0);
2971 elimination_effects (SET_SRC (x
), 0);
2975 /* Our only special processing is to pass the mode of the MEM to our
2977 elimination_effects (XEXP (x
, 0), GET_MODE (x
));
2984 fmt
= GET_RTX_FORMAT (code
);
2985 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++, fmt
++)
2988 elimination_effects (XEXP (x
, i
), mem_mode
);
2989 else if (*fmt
== 'E')
2990 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
2991 elimination_effects (XVECEXP (x
, i
, j
), mem_mode
);
2995 /* Descend through rtx X and verify that no references to eliminable registers
2996 remain. If any do remain, mark the involved register as not
3000 check_eliminable_occurrences (rtx x
)
3009 code
= GET_CODE (x
);
3011 if (code
== REG
&& REGNO (x
) < FIRST_PSEUDO_REGISTER
)
3013 struct elim_table
*ep
;
3015 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3016 if (ep
->from_rtx
== x
)
3017 ep
->can_eliminate
= 0;
3021 fmt
= GET_RTX_FORMAT (code
);
3022 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++, fmt
++)
3025 check_eliminable_occurrences (XEXP (x
, i
));
3026 else if (*fmt
== 'E')
3029 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
3030 check_eliminable_occurrences (XVECEXP (x
, i
, j
));
3035 /* Scan INSN and eliminate all eliminable registers in it.
3037 If REPLACE is nonzero, do the replacement destructively. Also
3038 delete the insn as dead it if it is setting an eliminable register.
3040 If REPLACE is zero, do all our allocations in reload_obstack.
3042 If no eliminations were done and this insn doesn't require any elimination
3043 processing (these are not identical conditions: it might be updating sp,
3044 but not referencing fp; this needs to be seen during reload_as_needed so
3045 that the offset between fp and sp can be taken into consideration), zero
3046 is returned. Otherwise, 1 is returned. */
3049 eliminate_regs_in_insn (rtx insn
, int replace
)
3051 int icode
= recog_memoized (insn
);
3052 rtx old_body
= PATTERN (insn
);
3053 int insn_is_asm
= asm_noperands (old_body
) >= 0;
3054 rtx old_set
= single_set (insn
);
3058 rtx substed_operand
[MAX_RECOG_OPERANDS
];
3059 rtx orig_operand
[MAX_RECOG_OPERANDS
];
3060 struct elim_table
*ep
;
3061 rtx plus_src
, plus_cst_src
;
3063 if (! insn_is_asm
&& icode
< 0)
3065 gcc_assert (GET_CODE (PATTERN (insn
)) == USE
3066 || GET_CODE (PATTERN (insn
)) == CLOBBER
3067 || GET_CODE (PATTERN (insn
)) == ADDR_VEC
3068 || GET_CODE (PATTERN (insn
)) == ADDR_DIFF_VEC
3069 || GET_CODE (PATTERN (insn
)) == ASM_INPUT
);
3073 if (old_set
!= 0 && REG_P (SET_DEST (old_set
))
3074 && REGNO (SET_DEST (old_set
)) < FIRST_PSEUDO_REGISTER
)
3076 /* Check for setting an eliminable register. */
3077 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3078 if (ep
->from_rtx
== SET_DEST (old_set
) && ep
->can_eliminate
)
3080 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3081 /* If this is setting the frame pointer register to the
3082 hardware frame pointer register and this is an elimination
3083 that will be done (tested above), this insn is really
3084 adjusting the frame pointer downward to compensate for
3085 the adjustment done before a nonlocal goto. */
3086 if (ep
->from
== FRAME_POINTER_REGNUM
3087 && ep
->to
== HARD_FRAME_POINTER_REGNUM
)
3089 rtx base
= SET_SRC (old_set
);
3090 rtx base_insn
= insn
;
3091 HOST_WIDE_INT offset
= 0;
3093 while (base
!= ep
->to_rtx
)
3095 rtx prev_insn
, prev_set
;
3097 if (GET_CODE (base
) == PLUS
3098 && GET_CODE (XEXP (base
, 1)) == CONST_INT
)
3100 offset
+= INTVAL (XEXP (base
, 1));
3101 base
= XEXP (base
, 0);
3103 else if ((prev_insn
= prev_nonnote_insn (base_insn
)) != 0
3104 && (prev_set
= single_set (prev_insn
)) != 0
3105 && rtx_equal_p (SET_DEST (prev_set
), base
))
3107 base
= SET_SRC (prev_set
);
3108 base_insn
= prev_insn
;
3114 if (base
== ep
->to_rtx
)
3117 = plus_constant (ep
->to_rtx
, offset
- ep
->offset
);
3119 new_body
= old_body
;
3122 new_body
= copy_insn (old_body
);
3123 if (REG_NOTES (insn
))
3124 REG_NOTES (insn
) = copy_insn_1 (REG_NOTES (insn
));
3126 PATTERN (insn
) = new_body
;
3127 old_set
= single_set (insn
);
3129 /* First see if this insn remains valid when we
3130 make the change. If not, keep the INSN_CODE
3131 the same and let reload fit it up. */
3132 validate_change (insn
, &SET_SRC (old_set
), src
, 1);
3133 validate_change (insn
, &SET_DEST (old_set
),
3135 if (! apply_change_group ())
3137 SET_SRC (old_set
) = src
;
3138 SET_DEST (old_set
) = ep
->to_rtx
;
3147 /* In this case this insn isn't serving a useful purpose. We
3148 will delete it in reload_as_needed once we know that this
3149 elimination is, in fact, being done.
3151 If REPLACE isn't set, we can't delete this insn, but needn't
3152 process it since it won't be used unless something changes. */
3155 delete_dead_insn (insn
);
3163 /* We allow one special case which happens to work on all machines we
3164 currently support: a single set with the source or a REG_EQUAL
3165 note being a PLUS of an eliminable register and a constant. */
3166 plus_src
= plus_cst_src
= 0;
3167 if (old_set
&& REG_P (SET_DEST (old_set
)))
3169 if (GET_CODE (SET_SRC (old_set
)) == PLUS
)
3170 plus_src
= SET_SRC (old_set
);
3171 /* First see if the source is of the form (plus (...) CST). */
3173 && GET_CODE (XEXP (plus_src
, 1)) == CONST_INT
)
3174 plus_cst_src
= plus_src
;
3175 else if (REG_P (SET_SRC (old_set
))
3178 /* Otherwise, see if we have a REG_EQUAL note of the form
3179 (plus (...) CST). */
3181 for (links
= REG_NOTES (insn
); links
; links
= XEXP (links
, 1))
3183 if ((REG_NOTE_KIND (links
) == REG_EQUAL
3184 || REG_NOTE_KIND (links
) == REG_EQUIV
)
3185 && GET_CODE (XEXP (links
, 0)) == PLUS
3186 && GET_CODE (XEXP (XEXP (links
, 0), 1)) == CONST_INT
)
3188 plus_cst_src
= XEXP (links
, 0);
3194 /* Check that the first operand of the PLUS is a hard reg or
3195 the lowpart subreg of one. */
3198 rtx reg
= XEXP (plus_cst_src
, 0);
3199 if (GET_CODE (reg
) == SUBREG
&& subreg_lowpart_p (reg
))
3200 reg
= SUBREG_REG (reg
);
3202 if (!REG_P (reg
) || REGNO (reg
) >= FIRST_PSEUDO_REGISTER
)
3208 rtx reg
= XEXP (plus_cst_src
, 0);
3209 HOST_WIDE_INT offset
= INTVAL (XEXP (plus_cst_src
, 1));
3211 if (GET_CODE (reg
) == SUBREG
)
3212 reg
= SUBREG_REG (reg
);
3214 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3215 if (ep
->from_rtx
== reg
&& ep
->can_eliminate
)
3217 rtx to_rtx
= ep
->to_rtx
;
3218 offset
+= ep
->offset
;
3219 offset
= trunc_int_for_mode (offset
, GET_MODE (reg
));
3221 if (GET_CODE (XEXP (plus_cst_src
, 0)) == SUBREG
)
3222 to_rtx
= gen_lowpart (GET_MODE (XEXP (plus_cst_src
, 0)),
3224 /* If we have a nonzero offset, and the source is already
3225 a simple REG, the following transformation would
3226 increase the cost of the insn by replacing a simple REG
3227 with (plus (reg sp) CST). So try only when we already
3228 had a PLUS before. */
3229 if (offset
== 0 || plus_src
)
3231 rtx new_src
= plus_constant (to_rtx
, offset
);
3233 new_body
= old_body
;
3236 new_body
= copy_insn (old_body
);
3237 if (REG_NOTES (insn
))
3238 REG_NOTES (insn
) = copy_insn_1 (REG_NOTES (insn
));
3240 PATTERN (insn
) = new_body
;
3241 old_set
= single_set (insn
);
3243 /* First see if this insn remains valid when we make the
3244 change. If not, try to replace the whole pattern with
3245 a simple set (this may help if the original insn was a
3246 PARALLEL that was only recognized as single_set due to
3247 REG_UNUSED notes). If this isn't valid either, keep
3248 the INSN_CODE the same and let reload fix it up. */
3249 if (!validate_change (insn
, &SET_SRC (old_set
), new_src
, 0))
3251 rtx new_pat
= gen_rtx_SET (VOIDmode
,
3252 SET_DEST (old_set
), new_src
);
3254 if (!validate_change (insn
, &PATTERN (insn
), new_pat
, 0))
3255 SET_SRC (old_set
) = new_src
;
3262 /* This can't have an effect on elimination offsets, so skip right
3268 /* Determine the effects of this insn on elimination offsets. */
3269 elimination_effects (old_body
, 0);
3271 /* Eliminate all eliminable registers occurring in operands that
3272 can be handled by reload. */
3273 extract_insn (insn
);
3274 for (i
= 0; i
< recog_data
.n_operands
; i
++)
3276 orig_operand
[i
] = recog_data
.operand
[i
];
3277 substed_operand
[i
] = recog_data
.operand
[i
];
3279 /* For an asm statement, every operand is eliminable. */
3280 if (insn_is_asm
|| insn_data
[icode
].operand
[i
].eliminable
)
3282 bool is_set_src
, in_plus
;
3284 /* Check for setting a register that we know about. */
3285 if (recog_data
.operand_type
[i
] != OP_IN
3286 && REG_P (orig_operand
[i
]))
3288 /* If we are assigning to a register that can be eliminated, it
3289 must be as part of a PARALLEL, since the code above handles
3290 single SETs. We must indicate that we can no longer
3291 eliminate this reg. */
3292 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
3294 if (ep
->from_rtx
== orig_operand
[i
])
3295 ep
->can_eliminate
= 0;
3298 /* Companion to the above plus substitution, we can allow
3299 invariants as the source of a plain move. */
3301 if (old_set
&& recog_data
.operand_loc
[i
] == &SET_SRC (old_set
))
3305 && (recog_data
.operand_loc
[i
] == &XEXP (plus_src
, 0)
3306 || recog_data
.operand_loc
[i
] == &XEXP (plus_src
, 1)))
3310 = eliminate_regs_1 (recog_data
.operand
[i
], 0,
3311 replace
? insn
: NULL_RTX
,
3312 is_set_src
|| in_plus
);
3313 if (substed_operand
[i
] != orig_operand
[i
])
3315 /* Terminate the search in check_eliminable_occurrences at
3317 *recog_data
.operand_loc
[i
] = 0;
3319 /* If an output operand changed from a REG to a MEM and INSN is an
3320 insn, write a CLOBBER insn. */
3321 if (recog_data
.operand_type
[i
] != OP_IN
3322 && REG_P (orig_operand
[i
])
3323 && MEM_P (substed_operand
[i
])
3325 emit_insn_after (gen_clobber (orig_operand
[i
]), insn
);
3329 for (i
= 0; i
< recog_data
.n_dups
; i
++)
3330 *recog_data
.dup_loc
[i
]
3331 = *recog_data
.operand_loc
[(int) recog_data
.dup_num
[i
]];
3333 /* If any eliminable remain, they aren't eliminable anymore. */
3334 check_eliminable_occurrences (old_body
);
3336 /* Substitute the operands; the new values are in the substed_operand
3338 for (i
= 0; i
< recog_data
.n_operands
; i
++)
3339 *recog_data
.operand_loc
[i
] = substed_operand
[i
];
3340 for (i
= 0; i
< recog_data
.n_dups
; i
++)
3341 *recog_data
.dup_loc
[i
] = substed_operand
[(int) recog_data
.dup_num
[i
]];
3343 /* If we are replacing a body that was a (set X (plus Y Z)), try to
3344 re-recognize the insn. We do this in case we had a simple addition
3345 but now can do this as a load-address. This saves an insn in this
3347 If re-recognition fails, the old insn code number will still be used,
3348 and some register operands may have changed into PLUS expressions.
3349 These will be handled by find_reloads by loading them into a register
3354 /* If we aren't replacing things permanently and we changed something,
3355 make another copy to ensure that all the RTL is new. Otherwise
3356 things can go wrong if find_reload swaps commutative operands
3357 and one is inside RTL that has been copied while the other is not. */
3358 new_body
= old_body
;
3361 new_body
= copy_insn (old_body
);
3362 if (REG_NOTES (insn
))
3363 REG_NOTES (insn
) = copy_insn_1 (REG_NOTES (insn
));
3365 PATTERN (insn
) = new_body
;
3367 /* If we had a move insn but now we don't, rerecognize it. This will
3368 cause spurious re-recognition if the old move had a PARALLEL since
3369 the new one still will, but we can't call single_set without
3370 having put NEW_BODY into the insn and the re-recognition won't
3371 hurt in this rare case. */
3372 /* ??? Why this huge if statement - why don't we just rerecognize the
3376 && ((REG_P (SET_SRC (old_set
))
3377 && (GET_CODE (new_body
) != SET
3378 || !REG_P (SET_SRC (new_body
))))
3379 /* If this was a load from or store to memory, compare
3380 the MEM in recog_data.operand to the one in the insn.
3381 If they are not equal, then rerecognize the insn. */
3383 && ((MEM_P (SET_SRC (old_set
))
3384 && SET_SRC (old_set
) != recog_data
.operand
[1])
3385 || (MEM_P (SET_DEST (old_set
))
3386 && SET_DEST (old_set
) != recog_data
.operand
[0])))
3387 /* If this was an add insn before, rerecognize. */
3388 || GET_CODE (SET_SRC (old_set
)) == PLUS
))
3390 int new_icode
= recog (PATTERN (insn
), insn
, 0);
3392 INSN_CODE (insn
) = new_icode
;
3396 /* Restore the old body. If there were any changes to it, we made a copy
3397 of it while the changes were still in place, so we'll correctly return
3398 a modified insn below. */
3401 /* Restore the old body. */
3402 for (i
= 0; i
< recog_data
.n_operands
; i
++)
3403 *recog_data
.operand_loc
[i
] = orig_operand
[i
];
3404 for (i
= 0; i
< recog_data
.n_dups
; i
++)
3405 *recog_data
.dup_loc
[i
] = orig_operand
[(int) recog_data
.dup_num
[i
]];
3408 /* Update all elimination pairs to reflect the status after the current
3409 insn. The changes we make were determined by the earlier call to
3410 elimination_effects.
3412 We also detect cases where register elimination cannot be done,
3413 namely, if a register would be both changed and referenced outside a MEM
3414 in the resulting insn since such an insn is often undefined and, even if
3415 not, we cannot know what meaning will be given to it. Note that it is
3416 valid to have a register used in an address in an insn that changes it
3417 (presumably with a pre- or post-increment or decrement).
3419 If anything changes, return nonzero. */
3421 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3423 if (ep
->previous_offset
!= ep
->offset
&& ep
->ref_outside_mem
)
3424 ep
->can_eliminate
= 0;
3426 ep
->ref_outside_mem
= 0;
3428 if (ep
->previous_offset
!= ep
->offset
)
3433 /* If we changed something, perform elimination in REG_NOTES. This is
3434 needed even when REPLACE is zero because a REG_DEAD note might refer
3435 to a register that we eliminate and could cause a different number
3436 of spill registers to be needed in the final reload pass than in
3438 if (val
&& REG_NOTES (insn
) != 0)
3440 = eliminate_regs_1 (REG_NOTES (insn
), 0, REG_NOTES (insn
), true);
3445 /* Loop through all elimination pairs.
3446 Recalculate the number not at initial offset.
3448 Compute the maximum offset (minimum offset if the stack does not
3449 grow downward) for each elimination pair. */
3452 update_eliminable_offsets (void)
3454 struct elim_table
*ep
;
3456 num_not_at_initial_offset
= 0;
3457 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3459 ep
->previous_offset
= ep
->offset
;
3460 if (ep
->can_eliminate
&& ep
->offset
!= ep
->initial_offset
)
3461 num_not_at_initial_offset
++;
3465 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3466 replacement we currently believe is valid, mark it as not eliminable if X
3467 modifies DEST in any way other than by adding a constant integer to it.
3469 If DEST is the frame pointer, we do nothing because we assume that
3470 all assignments to the hard frame pointer are nonlocal gotos and are being
3471 done at a time when they are valid and do not disturb anything else.
3472 Some machines want to eliminate a fake argument pointer with either the
3473 frame or stack pointer. Assignments to the hard frame pointer must not
3474 prevent this elimination.
3476 Called via note_stores from reload before starting its passes to scan
3477 the insns of the function. */
3480 mark_not_eliminable (rtx dest
, const_rtx x
, void *data ATTRIBUTE_UNUSED
)
3484 /* A SUBREG of a hard register here is just changing its mode. We should
3485 not see a SUBREG of an eliminable hard register, but check just in
3487 if (GET_CODE (dest
) == SUBREG
)
3488 dest
= SUBREG_REG (dest
);
3490 if (dest
== hard_frame_pointer_rtx
)
3493 for (i
= 0; i
< NUM_ELIMINABLE_REGS
; i
++)
3494 if (reg_eliminate
[i
].can_eliminate
&& dest
== reg_eliminate
[i
].to_rtx
3495 && (GET_CODE (x
) != SET
3496 || GET_CODE (SET_SRC (x
)) != PLUS
3497 || XEXP (SET_SRC (x
), 0) != dest
3498 || GET_CODE (XEXP (SET_SRC (x
), 1)) != CONST_INT
))
3500 reg_eliminate
[i
].can_eliminate_previous
3501 = reg_eliminate
[i
].can_eliminate
= 0;
3506 /* Verify that the initial elimination offsets did not change since the
3507 last call to set_initial_elim_offsets. This is used to catch cases
3508 where something illegal happened during reload_as_needed that could
3509 cause incorrect code to be generated if we did not check for it. */
3512 verify_initial_elim_offsets (void)
3516 if (!num_eliminable
)
3519 #ifdef ELIMINABLE_REGS
3521 struct elim_table
*ep
;
3523 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3525 INITIAL_ELIMINATION_OFFSET (ep
->from
, ep
->to
, t
);
3526 if (t
!= ep
->initial_offset
)
3531 INITIAL_FRAME_POINTER_OFFSET (t
);
3532 if (t
!= reg_eliminate
[0].initial_offset
)
3539 /* Reset all offsets on eliminable registers to their initial values. */
3542 set_initial_elim_offsets (void)
3544 struct elim_table
*ep
= reg_eliminate
;
3546 #ifdef ELIMINABLE_REGS
3547 for (; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3549 INITIAL_ELIMINATION_OFFSET (ep
->from
, ep
->to
, ep
->initial_offset
);
3550 ep
->previous_offset
= ep
->offset
= ep
->initial_offset
;
3553 INITIAL_FRAME_POINTER_OFFSET (ep
->initial_offset
);
3554 ep
->previous_offset
= ep
->offset
= ep
->initial_offset
;
3557 num_not_at_initial_offset
= 0;
3560 /* Subroutine of set_initial_label_offsets called via for_each_eh_label. */
3563 set_initial_eh_label_offset (rtx label
)
3565 set_label_offsets (label
, NULL_RTX
, 1);
3568 /* Initialize the known label offsets.
3569 Set a known offset for each forced label to be at the initial offset
3570 of each elimination. We do this because we assume that all
3571 computed jumps occur from a location where each elimination is
3572 at its initial offset.
3573 For all other labels, show that we don't know the offsets. */
3576 set_initial_label_offsets (void)
3579 memset (offsets_known_at
, 0, num_labels
);
3581 for (x
= forced_labels
; x
; x
= XEXP (x
, 1))
3583 set_label_offsets (XEXP (x
, 0), NULL_RTX
, 1);
3585 for_each_eh_label (set_initial_eh_label_offset
);
3588 /* Set all elimination offsets to the known values for the code label given
3592 set_offsets_for_label (rtx insn
)
3595 int label_nr
= CODE_LABEL_NUMBER (insn
);
3596 struct elim_table
*ep
;
3598 num_not_at_initial_offset
= 0;
3599 for (i
= 0, ep
= reg_eliminate
; i
< NUM_ELIMINABLE_REGS
; ep
++, i
++)
3601 ep
->offset
= ep
->previous_offset
3602 = offsets_at
[label_nr
- first_label_num
][i
];
3603 if (ep
->can_eliminate
&& ep
->offset
!= ep
->initial_offset
)
3604 num_not_at_initial_offset
++;
3608 /* See if anything that happened changes which eliminations are valid.
3609 For example, on the SPARC, whether or not the frame pointer can
3610 be eliminated can depend on what registers have been used. We need
3611 not check some conditions again (such as flag_omit_frame_pointer)
3612 since they can't have changed. */
3615 update_eliminables (HARD_REG_SET
*pset
)
3617 int previous_frame_pointer_needed
= frame_pointer_needed
;
3618 struct elim_table
*ep
;
3620 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3621 if ((ep
->from
== HARD_FRAME_POINTER_REGNUM
&& FRAME_POINTER_REQUIRED
)
3622 #ifdef ELIMINABLE_REGS
3623 || ! CAN_ELIMINATE (ep
->from
, ep
->to
)
3626 ep
->can_eliminate
= 0;
3628 /* Look for the case where we have discovered that we can't replace
3629 register A with register B and that means that we will now be
3630 trying to replace register A with register C. This means we can
3631 no longer replace register C with register B and we need to disable
3632 such an elimination, if it exists. This occurs often with A == ap,
3633 B == sp, and C == fp. */
3635 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3637 struct elim_table
*op
;
3640 if (! ep
->can_eliminate
&& ep
->can_eliminate_previous
)
3642 /* Find the current elimination for ep->from, if there is a
3644 for (op
= reg_eliminate
;
3645 op
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; op
++)
3646 if (op
->from
== ep
->from
&& op
->can_eliminate
)
3652 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
3654 for (op
= reg_eliminate
;
3655 op
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; op
++)
3656 if (op
->from
== new_to
&& op
->to
== ep
->to
)
3657 op
->can_eliminate
= 0;
3661 /* See if any registers that we thought we could eliminate the previous
3662 time are no longer eliminable. If so, something has changed and we
3663 must spill the register. Also, recompute the number of eliminable
3664 registers and see if the frame pointer is needed; it is if there is
3665 no elimination of the frame pointer that we can perform. */
3667 frame_pointer_needed
= 1;
3668 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3670 if (ep
->can_eliminate
&& ep
->from
== FRAME_POINTER_REGNUM
3671 && ep
->to
!= HARD_FRAME_POINTER_REGNUM
)
3672 frame_pointer_needed
= 0;
3674 if (! ep
->can_eliminate
&& ep
->can_eliminate_previous
)
3676 ep
->can_eliminate_previous
= 0;
3677 SET_HARD_REG_BIT (*pset
, ep
->from
);
3682 /* If we didn't need a frame pointer last time, but we do now, spill
3683 the hard frame pointer. */
3684 if (frame_pointer_needed
&& ! previous_frame_pointer_needed
)
3685 SET_HARD_REG_BIT (*pset
, HARD_FRAME_POINTER_REGNUM
);
3688 /* Return true if X is used as the target register of an elimination. */
3691 elimination_target_reg_p (rtx x
)
3693 struct elim_table
*ep
;
3695 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3696 if (ep
->to_rtx
== x
&& ep
->can_eliminate
)
3702 /* Initialize the table of registers to eliminate. */
3705 init_elim_table (void)
3707 struct elim_table
*ep
;
3708 #ifdef ELIMINABLE_REGS
3709 const struct elim_table_1
*ep1
;
3713 reg_eliminate
= xcalloc (sizeof (struct elim_table
), NUM_ELIMINABLE_REGS
);
3715 /* Does this function require a frame pointer? */
3717 frame_pointer_needed
= (! flag_omit_frame_pointer
3718 /* ?? If EXIT_IGNORE_STACK is set, we will not save
3719 and restore sp for alloca. So we can't eliminate
3720 the frame pointer in that case. At some point,
3721 we should improve this by emitting the
3722 sp-adjusting insns for this case. */
3723 || (cfun
->calls_alloca
3724 && EXIT_IGNORE_STACK
)
3725 || crtl
->accesses_prior_frames
3726 || FRAME_POINTER_REQUIRED
);
3730 #ifdef ELIMINABLE_REGS
3731 for (ep
= reg_eliminate
, ep1
= reg_eliminate_1
;
3732 ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++, ep1
++)
3734 ep
->from
= ep1
->from
;
3736 ep
->can_eliminate
= ep
->can_eliminate_previous
3737 = (CAN_ELIMINATE (ep
->from
, ep
->to
)
3738 && ! (ep
->to
== STACK_POINTER_REGNUM
&& frame_pointer_needed
));
3741 reg_eliminate
[0].from
= reg_eliminate_1
[0].from
;
3742 reg_eliminate
[0].to
= reg_eliminate_1
[0].to
;
3743 reg_eliminate
[0].can_eliminate
= reg_eliminate
[0].can_eliminate_previous
3744 = ! frame_pointer_needed
;
3747 /* Count the number of eliminable registers and build the FROM and TO
3748 REG rtx's. Note that code in gen_rtx_REG will cause, e.g.,
3749 gen_rtx_REG (Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
3750 We depend on this. */
3751 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3753 num_eliminable
+= ep
->can_eliminate
;
3754 ep
->from_rtx
= gen_rtx_REG (Pmode
, ep
->from
);
3755 ep
->to_rtx
= gen_rtx_REG (Pmode
, ep
->to
);
3759 /* Kick all pseudos out of hard register REGNO.
3761 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
3762 because we found we can't eliminate some register. In the case, no pseudos
3763 are allowed to be in the register, even if they are only in a block that
3764 doesn't require spill registers, unlike the case when we are spilling this
3765 hard reg to produce another spill register.
3767 Return nonzero if any pseudos needed to be kicked out. */
3770 spill_hard_reg (unsigned int regno
, int cant_eliminate
)
3776 SET_HARD_REG_BIT (bad_spill_regs_global
, regno
);
3777 df_set_regs_ever_live (regno
, true);
3780 /* Spill every pseudo reg that was allocated to this reg
3781 or to something that overlaps this reg. */
3783 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
3784 if (reg_renumber
[i
] >= 0
3785 && (unsigned int) reg_renumber
[i
] <= regno
3786 && end_hard_regno (PSEUDO_REGNO_MODE (i
), reg_renumber
[i
]) > regno
)
3787 SET_REGNO_REG_SET (&spilled_pseudos
, i
);
3790 /* After find_reload_regs has been run for all insn that need reloads,
3791 and/or spill_hard_regs was called, this function is used to actually
3792 spill pseudo registers and try to reallocate them. It also sets up the
3793 spill_regs array for use by choose_reload_regs. */
3796 finish_spills (int global
)
3798 struct insn_chain
*chain
;
3799 int something_changed
= 0;
3801 reg_set_iterator rsi
;
3803 /* Build the spill_regs array for the function. */
3804 /* If there are some registers still to eliminate and one of the spill regs
3805 wasn't ever used before, additional stack space may have to be
3806 allocated to store this register. Thus, we may have changed the offset
3807 between the stack and frame pointers, so mark that something has changed.
3809 One might think that we need only set VAL to 1 if this is a call-used
3810 register. However, the set of registers that must be saved by the
3811 prologue is not identical to the call-used set. For example, the
3812 register used by the call insn for the return PC is a call-used register,
3813 but must be saved by the prologue. */
3816 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
3817 if (TEST_HARD_REG_BIT (used_spill_regs
, i
))
3819 spill_reg_order
[i
] = n_spills
;
3820 spill_regs
[n_spills
++] = i
;
3821 if (num_eliminable
&& ! df_regs_ever_live_p (i
))
3822 something_changed
= 1;
3823 df_set_regs_ever_live (i
, true);
3826 spill_reg_order
[i
] = -1;
3828 EXECUTE_IF_SET_IN_REG_SET (&spilled_pseudos
, FIRST_PSEUDO_REGISTER
, i
, rsi
)
3830 /* Record the current hard register the pseudo is allocated to in
3831 pseudo_previous_regs so we avoid reallocating it to the same
3832 hard reg in a later pass. */
3833 gcc_assert (reg_renumber
[i
] >= 0);
3835 SET_HARD_REG_BIT (pseudo_previous_regs
[i
], reg_renumber
[i
]);
3836 /* Mark it as no longer having a hard register home. */
3837 reg_renumber
[i
] = -1;
3838 /* We will need to scan everything again. */
3839 something_changed
= 1;
3842 /* Retry global register allocation if possible. */
3845 memset (pseudo_forbidden_regs
, 0, max_regno
* sizeof (HARD_REG_SET
));
3846 /* For every insn that needs reloads, set the registers used as spill
3847 regs in pseudo_forbidden_regs for every pseudo live across the
3849 for (chain
= insns_need_reload
; chain
; chain
= chain
->next_need_reload
)
3851 EXECUTE_IF_SET_IN_REG_SET
3852 (&chain
->live_throughout
, FIRST_PSEUDO_REGISTER
, i
, rsi
)
3854 IOR_HARD_REG_SET (pseudo_forbidden_regs
[i
],
3855 chain
->used_spill_regs
);
3857 EXECUTE_IF_SET_IN_REG_SET
3858 (&chain
->dead_or_set
, FIRST_PSEUDO_REGISTER
, i
, rsi
)
3860 IOR_HARD_REG_SET (pseudo_forbidden_regs
[i
],
3861 chain
->used_spill_regs
);
3865 /* Retry allocating the spilled pseudos. For each reg, merge the
3866 various reg sets that indicate which hard regs can't be used,
3867 and call retry_global_alloc.
3868 We change spill_pseudos here to only contain pseudos that did not
3869 get a new hard register. */
3870 for (i
= FIRST_PSEUDO_REGISTER
; i
< (unsigned)max_regno
; i
++)
3871 if (reg_old_renumber
[i
] != reg_renumber
[i
])
3873 HARD_REG_SET forbidden
;
3874 COPY_HARD_REG_SET (forbidden
, bad_spill_regs_global
);
3875 IOR_HARD_REG_SET (forbidden
, pseudo_forbidden_regs
[i
]);
3876 IOR_HARD_REG_SET (forbidden
, pseudo_previous_regs
[i
]);
3877 retry_global_alloc (i
, forbidden
);
3878 if (reg_renumber
[i
] >= 0)
3879 CLEAR_REGNO_REG_SET (&spilled_pseudos
, i
);
3883 /* Fix up the register information in the insn chain.
3884 This involves deleting those of the spilled pseudos which did not get
3885 a new hard register home from the live_{before,after} sets. */
3886 for (chain
= reload_insn_chain
; chain
; chain
= chain
->next
)
3888 HARD_REG_SET used_by_pseudos
;
3889 HARD_REG_SET used_by_pseudos2
;
3891 AND_COMPL_REG_SET (&chain
->live_throughout
, &spilled_pseudos
);
3892 AND_COMPL_REG_SET (&chain
->dead_or_set
, &spilled_pseudos
);
3894 /* Mark any unallocated hard regs as available for spills. That
3895 makes inheritance work somewhat better. */
3896 if (chain
->need_reload
)
3898 REG_SET_TO_HARD_REG_SET (used_by_pseudos
, &chain
->live_throughout
);
3899 REG_SET_TO_HARD_REG_SET (used_by_pseudos2
, &chain
->dead_or_set
);
3900 IOR_HARD_REG_SET (used_by_pseudos
, used_by_pseudos2
);
3902 /* Save the old value for the sanity test below. */
3903 COPY_HARD_REG_SET (used_by_pseudos2
, chain
->used_spill_regs
);
3905 compute_use_by_pseudos (&used_by_pseudos
, &chain
->live_throughout
);
3906 compute_use_by_pseudos (&used_by_pseudos
, &chain
->dead_or_set
);
3907 COMPL_HARD_REG_SET (chain
->used_spill_regs
, used_by_pseudos
);
3908 AND_HARD_REG_SET (chain
->used_spill_regs
, used_spill_regs
);
3910 /* Make sure we only enlarge the set. */
3911 gcc_assert (hard_reg_set_subset_p (used_by_pseudos2
,
3912 chain
->used_spill_regs
));
3916 /* Let alter_reg modify the reg rtx's for the modified pseudos. */
3917 for (i
= FIRST_PSEUDO_REGISTER
; i
< (unsigned)max_regno
; i
++)
3919 int regno
= reg_renumber
[i
];
3920 if (reg_old_renumber
[i
] == regno
)
3923 alter_reg (i
, reg_old_renumber
[i
]);
3924 reg_old_renumber
[i
] = regno
;
3928 fprintf (dump_file
, " Register %d now on stack.\n\n", i
);
3930 fprintf (dump_file
, " Register %d now in %d.\n\n",
3931 i
, reg_renumber
[i
]);
3935 return something_changed
;
3938 /* Find all paradoxical subregs within X and update reg_max_ref_width. */
3941 scan_paradoxical_subregs (rtx x
)
3945 enum rtx_code code
= GET_CODE (x
);
3956 case CONST_VECTOR
: /* shouldn't happen, but just in case. */
3964 if (REG_P (SUBREG_REG (x
))
3965 && (GET_MODE_SIZE (GET_MODE (x
))
3966 > reg_max_ref_width
[REGNO (SUBREG_REG (x
))]))
3968 reg_max_ref_width
[REGNO (SUBREG_REG (x
))]
3969 = GET_MODE_SIZE (GET_MODE (x
));
3970 mark_home_live_1 (REGNO (SUBREG_REG (x
)), GET_MODE (x
));
3978 fmt
= GET_RTX_FORMAT (code
);
3979 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
3982 scan_paradoxical_subregs (XEXP (x
, i
));
3983 else if (fmt
[i
] == 'E')
3986 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3987 scan_paradoxical_subregs (XVECEXP (x
, i
, j
));
3992 /* A subroutine of reload_as_needed. If INSN has a REG_EH_REGION note,
3993 examine all of the reload insns between PREV and NEXT exclusive, and
3994 annotate all that may trap. */
3997 fixup_eh_region_note (rtx insn
, rtx prev
, rtx next
)
3999 rtx note
= find_reg_note (insn
, REG_EH_REGION
, NULL_RTX
);
4000 unsigned int trap_count
;
4006 if (may_trap_p (PATTERN (insn
)))
4010 remove_note (insn
, note
);
4014 for (i
= NEXT_INSN (prev
); i
!= next
; i
= NEXT_INSN (i
))
4015 if (INSN_P (i
) && i
!= insn
&& may_trap_p (PATTERN (i
)))
4019 = gen_rtx_EXPR_LIST (REG_EH_REGION
, XEXP (note
, 0), REG_NOTES (i
));
4023 /* Reload pseudo-registers into hard regs around each insn as needed.
4024 Additional register load insns are output before the insn that needs it
4025 and perhaps store insns after insns that modify the reloaded pseudo reg.
4027 reg_last_reload_reg and reg_reloaded_contents keep track of
4028 which registers are already available in reload registers.
4029 We update these for the reloads that we perform,
4030 as the insns are scanned. */
4033 reload_as_needed (int live_known
)
4035 struct insn_chain
*chain
;
4036 #if defined (AUTO_INC_DEC)
4041 memset (spill_reg_rtx
, 0, sizeof spill_reg_rtx
);
4042 memset (spill_reg_store
, 0, sizeof spill_reg_store
);
4043 reg_last_reload_reg
= XCNEWVEC (rtx
, max_regno
);
4044 INIT_REG_SET (®_has_output_reload
);
4045 CLEAR_HARD_REG_SET (reg_reloaded_valid
);
4046 CLEAR_HARD_REG_SET (reg_reloaded_call_part_clobbered
);
4048 set_initial_elim_offsets ();
4050 for (chain
= reload_insn_chain
; chain
; chain
= chain
->next
)
4053 rtx insn
= chain
->insn
;
4054 rtx old_next
= NEXT_INSN (insn
);
4056 /* If we pass a label, copy the offsets from the label information
4057 into the current offsets of each elimination. */
4059 set_offsets_for_label (insn
);
4061 else if (INSN_P (insn
))
4063 regset_head regs_to_forget
;
4064 INIT_REG_SET (®s_to_forget
);
4065 note_stores (PATTERN (insn
), forget_old_reloads_1
, ®s_to_forget
);
4067 /* If this is a USE and CLOBBER of a MEM, ensure that any
4068 references to eliminable registers have been removed. */
4070 if ((GET_CODE (PATTERN (insn
)) == USE
4071 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
4072 && MEM_P (XEXP (PATTERN (insn
), 0)))
4073 XEXP (XEXP (PATTERN (insn
), 0), 0)
4074 = eliminate_regs (XEXP (XEXP (PATTERN (insn
), 0), 0),
4075 GET_MODE (XEXP (PATTERN (insn
), 0)),
4078 /* If we need to do register elimination processing, do so.
4079 This might delete the insn, in which case we are done. */
4080 if ((num_eliminable
|| num_eliminable_invariants
) && chain
->need_elim
)
4082 eliminate_regs_in_insn (insn
, 1);
4085 update_eliminable_offsets ();
4086 CLEAR_REG_SET (®s_to_forget
);
4091 /* If need_elim is nonzero but need_reload is zero, one might think
4092 that we could simply set n_reloads to 0. However, find_reloads
4093 could have done some manipulation of the insn (such as swapping
4094 commutative operands), and these manipulations are lost during
4095 the first pass for every insn that needs register elimination.
4096 So the actions of find_reloads must be redone here. */
4098 if (! chain
->need_elim
&& ! chain
->need_reload
4099 && ! chain
->need_operand_change
)
4101 /* First find the pseudo regs that must be reloaded for this insn.
4102 This info is returned in the tables reload_... (see reload.h).
4103 Also modify the body of INSN by substituting RELOAD
4104 rtx's for those pseudo regs. */
4107 CLEAR_REG_SET (®_has_output_reload
);
4108 CLEAR_HARD_REG_SET (reg_is_output_reload
);
4110 find_reloads (insn
, 1, spill_indirect_levels
, live_known
,
4116 rtx next
= NEXT_INSN (insn
);
4119 prev
= PREV_INSN (insn
);
4121 /* Now compute which reload regs to reload them into. Perhaps
4122 reusing reload regs from previous insns, or else output
4123 load insns to reload them. Maybe output store insns too.
4124 Record the choices of reload reg in reload_reg_rtx. */
4125 choose_reload_regs (chain
);
4127 /* Merge any reloads that we didn't combine for fear of
4128 increasing the number of spill registers needed but now
4129 discover can be safely merged. */
4130 if (SMALL_REGISTER_CLASSES
)
4131 merge_assigned_reloads (insn
);
4133 /* Generate the insns to reload operands into or out of
4134 their reload regs. */
4135 emit_reload_insns (chain
);
4137 /* Substitute the chosen reload regs from reload_reg_rtx
4138 into the insn's body (or perhaps into the bodies of other
4139 load and store insn that we just made for reloading
4140 and that we moved the structure into). */
4141 subst_reloads (insn
);
4143 /* Adjust the exception region notes for loads and stores. */
4144 if (flag_non_call_exceptions
&& !CALL_P (insn
))
4145 fixup_eh_region_note (insn
, prev
, next
);
4147 /* If this was an ASM, make sure that all the reload insns
4148 we have generated are valid. If not, give an error
4150 if (asm_noperands (PATTERN (insn
)) >= 0)
4151 for (p
= NEXT_INSN (prev
); p
!= next
; p
= NEXT_INSN (p
))
4152 if (p
!= insn
&& INSN_P (p
)
4153 && GET_CODE (PATTERN (p
)) != USE
4154 && (recog_memoized (p
) < 0
4155 || (extract_insn (p
), ! constrain_operands (1))))
4157 error_for_asm (insn
,
4158 "%<asm%> operand requires "
4159 "impossible reload");
4164 if (num_eliminable
&& chain
->need_elim
)
4165 update_eliminable_offsets ();
4167 /* Any previously reloaded spilled pseudo reg, stored in this insn,
4168 is no longer validly lying around to save a future reload.
4169 Note that this does not detect pseudos that were reloaded
4170 for this insn in order to be stored in
4171 (obeying register constraints). That is correct; such reload
4172 registers ARE still valid. */
4173 forget_marked_reloads (®s_to_forget
);
4174 CLEAR_REG_SET (®s_to_forget
);
4176 /* There may have been CLOBBER insns placed after INSN. So scan
4177 between INSN and NEXT and use them to forget old reloads. */
4178 for (x
= NEXT_INSN (insn
); x
!= old_next
; x
= NEXT_INSN (x
))
4179 if (NONJUMP_INSN_P (x
) && GET_CODE (PATTERN (x
)) == CLOBBER
)
4180 note_stores (PATTERN (x
), forget_old_reloads_1
, NULL
);
4183 /* Likewise for regs altered by auto-increment in this insn.
4184 REG_INC notes have been changed by reloading:
4185 find_reloads_address_1 records substitutions for them,
4186 which have been performed by subst_reloads above. */
4187 for (i
= n_reloads
- 1; i
>= 0; i
--)
4189 rtx in_reg
= rld
[i
].in_reg
;
4192 enum rtx_code code
= GET_CODE (in_reg
);
4193 /* PRE_INC / PRE_DEC will have the reload register ending up
4194 with the same value as the stack slot, but that doesn't
4195 hold true for POST_INC / POST_DEC. Either we have to
4196 convert the memory access to a true POST_INC / POST_DEC,
4197 or we can't use the reload register for inheritance. */
4198 if ((code
== POST_INC
|| code
== POST_DEC
)
4199 && TEST_HARD_REG_BIT (reg_reloaded_valid
,
4200 REGNO (rld
[i
].reg_rtx
))
4201 /* Make sure it is the inc/dec pseudo, and not
4202 some other (e.g. output operand) pseudo. */
4203 && ((unsigned) reg_reloaded_contents
[REGNO (rld
[i
].reg_rtx
)]
4204 == REGNO (XEXP (in_reg
, 0))))
4207 rtx reload_reg
= rld
[i
].reg_rtx
;
4208 enum machine_mode mode
= GET_MODE (reload_reg
);
4212 for (p
= PREV_INSN (old_next
); p
!= prev
; p
= PREV_INSN (p
))
4214 /* We really want to ignore REG_INC notes here, so
4215 use PATTERN (p) as argument to reg_set_p . */
4216 if (reg_set_p (reload_reg
, PATTERN (p
)))
4218 n
= count_occurrences (PATTERN (p
), reload_reg
, 0);
4223 n
= validate_replace_rtx (reload_reg
,
4224 gen_rtx_fmt_e (code
,
4229 /* We must also verify that the constraints
4230 are met after the replacement. */
4233 n
= constrain_operands (1);
4237 /* If the constraints were not met, then
4238 undo the replacement. */
4241 validate_replace_rtx (gen_rtx_fmt_e (code
,
4254 = gen_rtx_EXPR_LIST (REG_INC
, reload_reg
,
4256 /* Mark this as having an output reload so that the
4257 REG_INC processing code below won't invalidate
4258 the reload for inheritance. */
4259 SET_HARD_REG_BIT (reg_is_output_reload
,
4260 REGNO (reload_reg
));
4261 SET_REGNO_REG_SET (®_has_output_reload
,
4262 REGNO (XEXP (in_reg
, 0)));
4265 forget_old_reloads_1 (XEXP (in_reg
, 0), NULL_RTX
,
4268 else if ((code
== PRE_INC
|| code
== PRE_DEC
)
4269 && TEST_HARD_REG_BIT (reg_reloaded_valid
,
4270 REGNO (rld
[i
].reg_rtx
))
4271 /* Make sure it is the inc/dec pseudo, and not
4272 some other (e.g. output operand) pseudo. */
4273 && ((unsigned) reg_reloaded_contents
[REGNO (rld
[i
].reg_rtx
)]
4274 == REGNO (XEXP (in_reg
, 0))))
4276 SET_HARD_REG_BIT (reg_is_output_reload
,
4277 REGNO (rld
[i
].reg_rtx
));
4278 SET_REGNO_REG_SET (®_has_output_reload
,
4279 REGNO (XEXP (in_reg
, 0)));
4283 /* If a pseudo that got a hard register is auto-incremented,
4284 we must purge records of copying it into pseudos without
4286 for (x
= REG_NOTES (insn
); x
; x
= XEXP (x
, 1))
4287 if (REG_NOTE_KIND (x
) == REG_INC
)
4289 /* See if this pseudo reg was reloaded in this insn.
4290 If so, its last-reload info is still valid
4291 because it is based on this insn's reload. */
4292 for (i
= 0; i
< n_reloads
; i
++)
4293 if (rld
[i
].out
== XEXP (x
, 0))
4297 forget_old_reloads_1 (XEXP (x
, 0), NULL_RTX
, NULL
);
4301 /* A reload reg's contents are unknown after a label. */
4303 CLEAR_HARD_REG_SET (reg_reloaded_valid
);
4305 /* Don't assume a reload reg is still good after a call insn
4306 if it is a call-used reg, or if it contains a value that will
4307 be partially clobbered by the call. */
4308 else if (CALL_P (insn
))
4310 AND_COMPL_HARD_REG_SET (reg_reloaded_valid
, call_used_reg_set
);
4311 AND_COMPL_HARD_REG_SET (reg_reloaded_valid
, reg_reloaded_call_part_clobbered
);
4316 free (reg_last_reload_reg
);
4317 CLEAR_REG_SET (®_has_output_reload
);
4320 /* Discard all record of any value reloaded from X,
4321 or reloaded in X from someplace else;
4322 unless X is an output reload reg of the current insn.
4324 X may be a hard reg (the reload reg)
4325 or it may be a pseudo reg that was reloaded from.
4327 When DATA is non-NULL just mark the registers in regset
4328 to be forgotten later. */
4331 forget_old_reloads_1 (rtx x
, const_rtx ignored ATTRIBUTE_UNUSED
,
4336 regset regs
= (regset
) data
;
4338 /* note_stores does give us subregs of hard regs,
4339 subreg_regno_offset requires a hard reg. */
4340 while (GET_CODE (x
) == SUBREG
)
4342 /* We ignore the subreg offset when calculating the regno,
4343 because we are using the entire underlying hard register
4353 if (regno
>= FIRST_PSEUDO_REGISTER
)
4359 nr
= hard_regno_nregs
[regno
][GET_MODE (x
)];
4360 /* Storing into a spilled-reg invalidates its contents.
4361 This can happen if a block-local pseudo is allocated to that reg
4362 and it wasn't spilled because this block's total need is 0.
4363 Then some insn might have an optional reload and use this reg. */
4365 for (i
= 0; i
< nr
; i
++)
4366 /* But don't do this if the reg actually serves as an output
4367 reload reg in the current instruction. */
4369 || ! TEST_HARD_REG_BIT (reg_is_output_reload
, regno
+ i
))
4371 CLEAR_HARD_REG_BIT (reg_reloaded_valid
, regno
+ i
);
4372 spill_reg_store
[regno
+ i
] = 0;
4378 SET_REGNO_REG_SET (regs
, regno
+ nr
);
4381 /* Since value of X has changed,
4382 forget any value previously copied from it. */
4385 /* But don't forget a copy if this is the output reload
4386 that establishes the copy's validity. */
4388 || !REGNO_REG_SET_P (®_has_output_reload
, regno
+ nr
))
4389 reg_last_reload_reg
[regno
+ nr
] = 0;
4393 /* Forget the reloads marked in regset by previous function. */
4395 forget_marked_reloads (regset regs
)
4398 reg_set_iterator rsi
;
4399 EXECUTE_IF_SET_IN_REG_SET (regs
, 0, reg
, rsi
)
4401 if (reg
< FIRST_PSEUDO_REGISTER
4402 /* But don't do this if the reg actually serves as an output
4403 reload reg in the current instruction. */
4405 || ! TEST_HARD_REG_BIT (reg_is_output_reload
, reg
)))
4407 CLEAR_HARD_REG_BIT (reg_reloaded_valid
, reg
);
4408 spill_reg_store
[reg
] = 0;
4411 || !REGNO_REG_SET_P (®_has_output_reload
, reg
))
4412 reg_last_reload_reg
[reg
] = 0;
4416 /* The following HARD_REG_SETs indicate when each hard register is
4417 used for a reload of various parts of the current insn. */
4419 /* If reg is unavailable for all reloads. */
4420 static HARD_REG_SET reload_reg_unavailable
;
4421 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
4422 static HARD_REG_SET reload_reg_used
;
4423 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
4424 static HARD_REG_SET reload_reg_used_in_input_addr
[MAX_RECOG_OPERANDS
];
4425 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */
4426 static HARD_REG_SET reload_reg_used_in_inpaddr_addr
[MAX_RECOG_OPERANDS
];
4427 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
4428 static HARD_REG_SET reload_reg_used_in_output_addr
[MAX_RECOG_OPERANDS
];
4429 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */
4430 static HARD_REG_SET reload_reg_used_in_outaddr_addr
[MAX_RECOG_OPERANDS
];
4431 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
4432 static HARD_REG_SET reload_reg_used_in_input
[MAX_RECOG_OPERANDS
];
4433 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
4434 static HARD_REG_SET reload_reg_used_in_output
[MAX_RECOG_OPERANDS
];
4435 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
4436 static HARD_REG_SET reload_reg_used_in_op_addr
;
4437 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */
4438 static HARD_REG_SET reload_reg_used_in_op_addr_reload
;
4439 /* If reg is in use for a RELOAD_FOR_INSN reload. */
4440 static HARD_REG_SET reload_reg_used_in_insn
;
4441 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
4442 static HARD_REG_SET reload_reg_used_in_other_addr
;
4444 /* If reg is in use as a reload reg for any sort of reload. */
4445 static HARD_REG_SET reload_reg_used_at_all
;
4447 /* If reg is use as an inherited reload. We just mark the first register
4449 static HARD_REG_SET reload_reg_used_for_inherit
;
4451 /* Records which hard regs are used in any way, either as explicit use or
4452 by being allocated to a pseudo during any point of the current insn. */
4453 static HARD_REG_SET reg_used_in_insn
;
4455 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
4456 TYPE. MODE is used to indicate how many consecutive regs are
4460 mark_reload_reg_in_use (unsigned int regno
, int opnum
, enum reload_type type
,
4461 enum machine_mode mode
)
4463 unsigned int nregs
= hard_regno_nregs
[regno
][mode
];
4466 for (i
= regno
; i
< nregs
+ regno
; i
++)
4471 SET_HARD_REG_BIT (reload_reg_used
, i
);
4474 case RELOAD_FOR_INPUT_ADDRESS
:
4475 SET_HARD_REG_BIT (reload_reg_used_in_input_addr
[opnum
], i
);
4478 case RELOAD_FOR_INPADDR_ADDRESS
:
4479 SET_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[opnum
], i
);
4482 case RELOAD_FOR_OUTPUT_ADDRESS
:
4483 SET_HARD_REG_BIT (reload_reg_used_in_output_addr
[opnum
], i
);
4486 case RELOAD_FOR_OUTADDR_ADDRESS
:
4487 SET_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[opnum
], i
);
4490 case RELOAD_FOR_OPERAND_ADDRESS
:
4491 SET_HARD_REG_BIT (reload_reg_used_in_op_addr
, i
);
4494 case RELOAD_FOR_OPADDR_ADDR
:
4495 SET_HARD_REG_BIT (reload_reg_used_in_op_addr_reload
, i
);
4498 case RELOAD_FOR_OTHER_ADDRESS
:
4499 SET_HARD_REG_BIT (reload_reg_used_in_other_addr
, i
);
4502 case RELOAD_FOR_INPUT
:
4503 SET_HARD_REG_BIT (reload_reg_used_in_input
[opnum
], i
);
4506 case RELOAD_FOR_OUTPUT
:
4507 SET_HARD_REG_BIT (reload_reg_used_in_output
[opnum
], i
);
4510 case RELOAD_FOR_INSN
:
4511 SET_HARD_REG_BIT (reload_reg_used_in_insn
, i
);
4515 SET_HARD_REG_BIT (reload_reg_used_at_all
, i
);
4519 /* Similarly, but show REGNO is no longer in use for a reload. */
4522 clear_reload_reg_in_use (unsigned int regno
, int opnum
,
4523 enum reload_type type
, enum machine_mode mode
)
4525 unsigned int nregs
= hard_regno_nregs
[regno
][mode
];
4526 unsigned int start_regno
, end_regno
, r
;
4528 /* A complication is that for some reload types, inheritance might
4529 allow multiple reloads of the same types to share a reload register.
4530 We set check_opnum if we have to check only reloads with the same
4531 operand number, and check_any if we have to check all reloads. */
4532 int check_opnum
= 0;
4534 HARD_REG_SET
*used_in_set
;
4539 used_in_set
= &reload_reg_used
;
4542 case RELOAD_FOR_INPUT_ADDRESS
:
4543 used_in_set
= &reload_reg_used_in_input_addr
[opnum
];
4546 case RELOAD_FOR_INPADDR_ADDRESS
:
4548 used_in_set
= &reload_reg_used_in_inpaddr_addr
[opnum
];
4551 case RELOAD_FOR_OUTPUT_ADDRESS
:
4552 used_in_set
= &reload_reg_used_in_output_addr
[opnum
];
4555 case RELOAD_FOR_OUTADDR_ADDRESS
:
4557 used_in_set
= &reload_reg_used_in_outaddr_addr
[opnum
];
4560 case RELOAD_FOR_OPERAND_ADDRESS
:
4561 used_in_set
= &reload_reg_used_in_op_addr
;
4564 case RELOAD_FOR_OPADDR_ADDR
:
4566 used_in_set
= &reload_reg_used_in_op_addr_reload
;
4569 case RELOAD_FOR_OTHER_ADDRESS
:
4570 used_in_set
= &reload_reg_used_in_other_addr
;
4574 case RELOAD_FOR_INPUT
:
4575 used_in_set
= &reload_reg_used_in_input
[opnum
];
4578 case RELOAD_FOR_OUTPUT
:
4579 used_in_set
= &reload_reg_used_in_output
[opnum
];
4582 case RELOAD_FOR_INSN
:
4583 used_in_set
= &reload_reg_used_in_insn
;
4588 /* We resolve conflicts with remaining reloads of the same type by
4589 excluding the intervals of reload registers by them from the
4590 interval of freed reload registers. Since we only keep track of
4591 one set of interval bounds, we might have to exclude somewhat
4592 more than what would be necessary if we used a HARD_REG_SET here.
4593 But this should only happen very infrequently, so there should
4594 be no reason to worry about it. */
4596 start_regno
= regno
;
4597 end_regno
= regno
+ nregs
;
4598 if (check_opnum
|| check_any
)
4600 for (i
= n_reloads
- 1; i
>= 0; i
--)
4602 if (rld
[i
].when_needed
== type
4603 && (check_any
|| rld
[i
].opnum
== opnum
)
4606 unsigned int conflict_start
= true_regnum (rld
[i
].reg_rtx
);
4607 unsigned int conflict_end
4608 = end_hard_regno (rld
[i
].mode
, conflict_start
);
4610 /* If there is an overlap with the first to-be-freed register,
4611 adjust the interval start. */
4612 if (conflict_start
<= start_regno
&& conflict_end
> start_regno
)
4613 start_regno
= conflict_end
;
4614 /* Otherwise, if there is a conflict with one of the other
4615 to-be-freed registers, adjust the interval end. */
4616 if (conflict_start
> start_regno
&& conflict_start
< end_regno
)
4617 end_regno
= conflict_start
;
4622 for (r
= start_regno
; r
< end_regno
; r
++)
4623 CLEAR_HARD_REG_BIT (*used_in_set
, r
);
4626 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
4627 specified by OPNUM and TYPE. */
4630 reload_reg_free_p (unsigned int regno
, int opnum
, enum reload_type type
)
4634 /* In use for a RELOAD_OTHER means it's not available for anything. */
4635 if (TEST_HARD_REG_BIT (reload_reg_used
, regno
)
4636 || TEST_HARD_REG_BIT (reload_reg_unavailable
, regno
))
4642 /* In use for anything means we can't use it for RELOAD_OTHER. */
4643 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr
, regno
)
4644 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
)
4645 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload
, regno
)
4646 || TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
))
4649 for (i
= 0; i
< reload_n_operands
; i
++)
4650 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
4651 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
)
4652 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
4653 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
)
4654 || TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
)
4655 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
4660 case RELOAD_FOR_INPUT
:
4661 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
4662 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
))
4665 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload
, regno
))
4668 /* If it is used for some other input, can't use it. */
4669 for (i
= 0; i
< reload_n_operands
; i
++)
4670 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
4673 /* If it is used in a later operand's address, can't use it. */
4674 for (i
= opnum
+ 1; i
< reload_n_operands
; i
++)
4675 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
4676 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
))
4681 case RELOAD_FOR_INPUT_ADDRESS
:
4682 /* Can't use a register if it is used for an input address for this
4683 operand or used as an input in an earlier one. */
4684 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[opnum
], regno
)
4685 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[opnum
], regno
))
4688 for (i
= 0; i
< opnum
; i
++)
4689 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
4694 case RELOAD_FOR_INPADDR_ADDRESS
:
4695 /* Can't use a register if it is used for an input address
4696 for this operand or used as an input in an earlier
4698 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[opnum
], regno
))
4701 for (i
= 0; i
< opnum
; i
++)
4702 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
4707 case RELOAD_FOR_OUTPUT_ADDRESS
:
4708 /* Can't use a register if it is used for an output address for this
4709 operand or used as an output in this or a later operand. Note
4710 that multiple output operands are emitted in reverse order, so
4711 the conflicting ones are those with lower indices. */
4712 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[opnum
], regno
))
4715 for (i
= 0; i
<= opnum
; i
++)
4716 if (TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
4721 case RELOAD_FOR_OUTADDR_ADDRESS
:
4722 /* Can't use a register if it is used for an output address
4723 for this operand or used as an output in this or a
4724 later operand. Note that multiple output operands are
4725 emitted in reverse order, so the conflicting ones are
4726 those with lower indices. */
4727 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[opnum
], regno
))
4730 for (i
= 0; i
<= opnum
; i
++)
4731 if (TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
4736 case RELOAD_FOR_OPERAND_ADDRESS
:
4737 for (i
= 0; i
< reload_n_operands
; i
++)
4738 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
4741 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
4742 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
));
4744 case RELOAD_FOR_OPADDR_ADDR
:
4745 for (i
= 0; i
< reload_n_operands
; i
++)
4746 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
4749 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload
, regno
));
4751 case RELOAD_FOR_OUTPUT
:
4752 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
4753 outputs, or an operand address for this or an earlier output.
4754 Note that multiple output operands are emitted in reverse order,
4755 so the conflicting ones are those with higher indices. */
4756 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
))
4759 for (i
= 0; i
< reload_n_operands
; i
++)
4760 if (TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
4763 for (i
= opnum
; i
< reload_n_operands
; i
++)
4764 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
4765 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
))
4770 case RELOAD_FOR_INSN
:
4771 for (i
= 0; i
< reload_n_operands
; i
++)
4772 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
)
4773 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
4776 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
4777 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
));
4779 case RELOAD_FOR_OTHER_ADDRESS
:
4780 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr
, regno
);
4787 /* Return 1 if the value in reload reg REGNO, as used by a reload
4788 needed for the part of the insn specified by OPNUM and TYPE,
4789 is still available in REGNO at the end of the insn.
4791 We can assume that the reload reg was already tested for availability
4792 at the time it is needed, and we should not check this again,
4793 in case the reg has already been marked in use. */
4796 reload_reg_reaches_end_p (unsigned int regno
, int opnum
, enum reload_type type
)
4803 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
4804 its value must reach the end. */
4807 /* If this use is for part of the insn,
4808 its value reaches if no subsequent part uses the same register.
4809 Just like the above function, don't try to do this with lots
4812 case RELOAD_FOR_OTHER_ADDRESS
:
4813 /* Here we check for everything else, since these don't conflict
4814 with anything else and everything comes later. */
4816 for (i
= 0; i
< reload_n_operands
; i
++)
4817 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
4818 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
)
4819 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
)
4820 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
4821 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
)
4822 || TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
4825 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
)
4826 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload
, regno
)
4827 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
4828 && ! TEST_HARD_REG_BIT (reload_reg_used
, regno
));
4830 case RELOAD_FOR_INPUT_ADDRESS
:
4831 case RELOAD_FOR_INPADDR_ADDRESS
:
4832 /* Similar, except that we check only for this and subsequent inputs
4833 and the address of only subsequent inputs and we do not need
4834 to check for RELOAD_OTHER objects since they are known not to
4837 for (i
= opnum
; i
< reload_n_operands
; i
++)
4838 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
4841 for (i
= opnum
+ 1; i
< reload_n_operands
; i
++)
4842 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
4843 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
))
4846 for (i
= 0; i
< reload_n_operands
; i
++)
4847 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
4848 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
)
4849 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
4852 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload
, regno
))
4855 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
)
4856 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
4857 && !TEST_HARD_REG_BIT (reload_reg_used
, regno
));
4859 case RELOAD_FOR_INPUT
:
4860 /* Similar to input address, except we start at the next operand for
4861 both input and input address and we do not check for
4862 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
4865 for (i
= opnum
+ 1; i
< reload_n_operands
; i
++)
4866 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
4867 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
)
4868 || TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
4871 /* ... fall through ... */
4873 case RELOAD_FOR_OPERAND_ADDRESS
:
4874 /* Check outputs and their addresses. */
4876 for (i
= 0; i
< reload_n_operands
; i
++)
4877 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
4878 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
)
4879 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
4882 return (!TEST_HARD_REG_BIT (reload_reg_used
, regno
));
4884 case RELOAD_FOR_OPADDR_ADDR
:
4885 for (i
= 0; i
< reload_n_operands
; i
++)
4886 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
4887 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
)
4888 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
4891 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
)
4892 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
4893 && !TEST_HARD_REG_BIT (reload_reg_used
, regno
));
4895 case RELOAD_FOR_INSN
:
4896 /* These conflict with other outputs with RELOAD_OTHER. So
4897 we need only check for output addresses. */
4899 opnum
= reload_n_operands
;
4901 /* ... fall through ... */
4903 case RELOAD_FOR_OUTPUT
:
4904 case RELOAD_FOR_OUTPUT_ADDRESS
:
4905 case RELOAD_FOR_OUTADDR_ADDRESS
:
4906 /* We already know these can't conflict with a later output. So the
4907 only thing to check are later output addresses.
4908 Note that multiple output operands are emitted in reverse order,
4909 so the conflicting ones are those with lower indices. */
4910 for (i
= 0; i
< opnum
; i
++)
4911 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
4912 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
))
4922 /* Like reload_reg_reaches_end_p, but check that the condition holds for
4923 every register in the range [REGNO, REGNO + NREGS). */
4926 reload_regs_reach_end_p (unsigned int regno
, int nregs
,
4927 int opnum
, enum reload_type type
)
4931 for (i
= 0; i
< nregs
; i
++)
4932 if (!reload_reg_reaches_end_p (regno
+ i
, opnum
, type
))
4938 /* Returns whether R1 and R2 are uniquely chained: the value of one
4939 is used by the other, and that value is not used by any other
4940 reload for this insn. This is used to partially undo the decision
4941 made in find_reloads when in the case of multiple
4942 RELOAD_FOR_OPERAND_ADDRESS reloads it converts all
4943 RELOAD_FOR_OPADDR_ADDR reloads into RELOAD_FOR_OPERAND_ADDRESS
4944 reloads. This code tries to avoid the conflict created by that
4945 change. It might be cleaner to explicitly keep track of which
4946 RELOAD_FOR_OPADDR_ADDR reload is associated with which
4947 RELOAD_FOR_OPERAND_ADDRESS reload, rather than to try to detect
4948 this after the fact. */
4950 reloads_unique_chain_p (int r1
, int r2
)
4954 /* We only check input reloads. */
4955 if (! rld
[r1
].in
|| ! rld
[r2
].in
)
4958 /* Avoid anything with output reloads. */
4959 if (rld
[r1
].out
|| rld
[r2
].out
)
4962 /* "chained" means one reload is a component of the other reload,
4963 not the same as the other reload. */
4964 if (rld
[r1
].opnum
!= rld
[r2
].opnum
4965 || rtx_equal_p (rld
[r1
].in
, rld
[r2
].in
)
4966 || rld
[r1
].optional
|| rld
[r2
].optional
4967 || ! (reg_mentioned_p (rld
[r1
].in
, rld
[r2
].in
)
4968 || reg_mentioned_p (rld
[r2
].in
, rld
[r1
].in
)))
4971 for (i
= 0; i
< n_reloads
; i
++)
4972 /* Look for input reloads that aren't our two */
4973 if (i
!= r1
&& i
!= r2
&& rld
[i
].in
)
4975 /* If our reload is mentioned at all, it isn't a simple chain. */
4976 if (reg_mentioned_p (rld
[r1
].in
, rld
[i
].in
))
4982 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
4985 This function uses the same algorithm as reload_reg_free_p above. */
4988 reloads_conflict (int r1
, int r2
)
4990 enum reload_type r1_type
= rld
[r1
].when_needed
;
4991 enum reload_type r2_type
= rld
[r2
].when_needed
;
4992 int r1_opnum
= rld
[r1
].opnum
;
4993 int r2_opnum
= rld
[r2
].opnum
;
4995 /* RELOAD_OTHER conflicts with everything. */
4996 if (r2_type
== RELOAD_OTHER
)
4999 /* Otherwise, check conflicts differently for each type. */
5003 case RELOAD_FOR_INPUT
:
5004 return (r2_type
== RELOAD_FOR_INSN
5005 || r2_type
== RELOAD_FOR_OPERAND_ADDRESS
5006 || r2_type
== RELOAD_FOR_OPADDR_ADDR
5007 || r2_type
== RELOAD_FOR_INPUT
5008 || ((r2_type
== RELOAD_FOR_INPUT_ADDRESS
5009 || r2_type
== RELOAD_FOR_INPADDR_ADDRESS
)
5010 && r2_opnum
> r1_opnum
));
5012 case RELOAD_FOR_INPUT_ADDRESS
:
5013 return ((r2_type
== RELOAD_FOR_INPUT_ADDRESS
&& r1_opnum
== r2_opnum
)
5014 || (r2_type
== RELOAD_FOR_INPUT
&& r2_opnum
< r1_opnum
));
5016 case RELOAD_FOR_INPADDR_ADDRESS
:
5017 return ((r2_type
== RELOAD_FOR_INPADDR_ADDRESS
&& r1_opnum
== r2_opnum
)
5018 || (r2_type
== RELOAD_FOR_INPUT
&& r2_opnum
< r1_opnum
));
5020 case RELOAD_FOR_OUTPUT_ADDRESS
:
5021 return ((r2_type
== RELOAD_FOR_OUTPUT_ADDRESS
&& r2_opnum
== r1_opnum
)
5022 || (r2_type
== RELOAD_FOR_OUTPUT
&& r2_opnum
<= r1_opnum
));
5024 case RELOAD_FOR_OUTADDR_ADDRESS
:
5025 return ((r2_type
== RELOAD_FOR_OUTADDR_ADDRESS
&& r2_opnum
== r1_opnum
)
5026 || (r2_type
== RELOAD_FOR_OUTPUT
&& r2_opnum
<= r1_opnum
));
5028 case RELOAD_FOR_OPERAND_ADDRESS
:
5029 return (r2_type
== RELOAD_FOR_INPUT
|| r2_type
== RELOAD_FOR_INSN
5030 || (r2_type
== RELOAD_FOR_OPERAND_ADDRESS
5031 && !reloads_unique_chain_p (r1
, r2
)));
5033 case RELOAD_FOR_OPADDR_ADDR
:
5034 return (r2_type
== RELOAD_FOR_INPUT
5035 || r2_type
== RELOAD_FOR_OPADDR_ADDR
);
5037 case RELOAD_FOR_OUTPUT
:
5038 return (r2_type
== RELOAD_FOR_INSN
|| r2_type
== RELOAD_FOR_OUTPUT
5039 || ((r2_type
== RELOAD_FOR_OUTPUT_ADDRESS
5040 || r2_type
== RELOAD_FOR_OUTADDR_ADDRESS
)
5041 && r2_opnum
>= r1_opnum
));
5043 case RELOAD_FOR_INSN
:
5044 return (r2_type
== RELOAD_FOR_INPUT
|| r2_type
== RELOAD_FOR_OUTPUT
5045 || r2_type
== RELOAD_FOR_INSN
5046 || r2_type
== RELOAD_FOR_OPERAND_ADDRESS
);
5048 case RELOAD_FOR_OTHER_ADDRESS
:
5049 return r2_type
== RELOAD_FOR_OTHER_ADDRESS
;
5059 /* Indexed by reload number, 1 if incoming value
5060 inherited from previous insns. */
5061 static char reload_inherited
[MAX_RELOADS
];
5063 /* For an inherited reload, this is the insn the reload was inherited from,
5064 if we know it. Otherwise, this is 0. */
5065 static rtx reload_inheritance_insn
[MAX_RELOADS
];
5067 /* If nonzero, this is a place to get the value of the reload,
5068 rather than using reload_in. */
5069 static rtx reload_override_in
[MAX_RELOADS
];
5071 /* For each reload, the hard register number of the register used,
5072 or -1 if we did not need a register for this reload. */
5073 static int reload_spill_index
[MAX_RELOADS
];
5075 /* Index X is the value of rld[X].reg_rtx, adjusted for the input mode. */
5076 static rtx reload_reg_rtx_for_input
[MAX_RELOADS
];
5078 /* Index X is the value of rld[X].reg_rtx, adjusted for the output mode. */
5079 static rtx reload_reg_rtx_for_output
[MAX_RELOADS
];
5081 /* Subroutine of free_for_value_p, used to check a single register.
5082 START_REGNO is the starting regno of the full reload register
5083 (possibly comprising multiple hard registers) that we are considering. */
5086 reload_reg_free_for_value_p (int start_regno
, int regno
, int opnum
,
5087 enum reload_type type
, rtx value
, rtx out
,
5088 int reloadnum
, int ignore_address_reloads
)
5091 /* Set if we see an input reload that must not share its reload register
5092 with any new earlyclobber, but might otherwise share the reload
5093 register with an output or input-output reload. */
5094 int check_earlyclobber
= 0;
5098 if (TEST_HARD_REG_BIT (reload_reg_unavailable
, regno
))
5101 if (out
== const0_rtx
)
5107 /* We use some pseudo 'time' value to check if the lifetimes of the
5108 new register use would overlap with the one of a previous reload
5109 that is not read-only or uses a different value.
5110 The 'time' used doesn't have to be linear in any shape or form, just
5112 Some reload types use different 'buckets' for each operand.
5113 So there are MAX_RECOG_OPERANDS different time values for each
5115 We compute TIME1 as the time when the register for the prospective
5116 new reload ceases to be live, and TIME2 for each existing
5117 reload as the time when that the reload register of that reload
5119 Where there is little to be gained by exact lifetime calculations,
5120 we just make conservative assumptions, i.e. a longer lifetime;
5121 this is done in the 'default:' cases. */
5124 case RELOAD_FOR_OTHER_ADDRESS
:
5125 /* RELOAD_FOR_OTHER_ADDRESS conflicts with RELOAD_OTHER reloads. */
5126 time1
= copy
? 0 : 1;
5129 time1
= copy
? 1 : MAX_RECOG_OPERANDS
* 5 + 5;
5131 /* For each input, we may have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
5132 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 ,
5133 respectively, to the time values for these, we get distinct time
5134 values. To get distinct time values for each operand, we have to
5135 multiply opnum by at least three. We round that up to four because
5136 multiply by four is often cheaper. */
5137 case RELOAD_FOR_INPADDR_ADDRESS
:
5138 time1
= opnum
* 4 + 2;
5140 case RELOAD_FOR_INPUT_ADDRESS
:
5141 time1
= opnum
* 4 + 3;
5143 case RELOAD_FOR_INPUT
:
5144 /* All RELOAD_FOR_INPUT reloads remain live till the instruction
5145 executes (inclusive). */
5146 time1
= copy
? opnum
* 4 + 4 : MAX_RECOG_OPERANDS
* 4 + 3;
5148 case RELOAD_FOR_OPADDR_ADDR
:
5150 <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
5151 time1
= MAX_RECOG_OPERANDS
* 4 + 1;
5153 case RELOAD_FOR_OPERAND_ADDRESS
:
5154 /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn
5156 time1
= copy
? MAX_RECOG_OPERANDS
* 4 + 2 : MAX_RECOG_OPERANDS
* 4 + 3;
5158 case RELOAD_FOR_OUTADDR_ADDRESS
:
5159 time1
= MAX_RECOG_OPERANDS
* 4 + 4 + opnum
;
5161 case RELOAD_FOR_OUTPUT_ADDRESS
:
5162 time1
= MAX_RECOG_OPERANDS
* 4 + 5 + opnum
;
5165 time1
= MAX_RECOG_OPERANDS
* 5 + 5;
5168 for (i
= 0; i
< n_reloads
; i
++)
5170 rtx reg
= rld
[i
].reg_rtx
;
5171 if (reg
&& REG_P (reg
)
5172 && ((unsigned) regno
- true_regnum (reg
)
5173 <= hard_regno_nregs
[REGNO (reg
)][GET_MODE (reg
)] - (unsigned) 1)
5176 rtx other_input
= rld
[i
].in
;
5178 /* If the other reload loads the same input value, that
5179 will not cause a conflict only if it's loading it into
5180 the same register. */
5181 if (true_regnum (reg
) != start_regno
)
5182 other_input
= NULL_RTX
;
5183 if (! other_input
|| ! rtx_equal_p (other_input
, value
)
5184 || rld
[i
].out
|| out
)
5187 switch (rld
[i
].when_needed
)
5189 case RELOAD_FOR_OTHER_ADDRESS
:
5192 case RELOAD_FOR_INPADDR_ADDRESS
:
5193 /* find_reloads makes sure that a
5194 RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used
5195 by at most one - the first -
5196 RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the
5197 address reload is inherited, the address address reload
5198 goes away, so we can ignore this conflict. */
5199 if (type
== RELOAD_FOR_INPUT_ADDRESS
&& reloadnum
== i
+ 1
5200 && ignore_address_reloads
5201 /* Unless the RELOAD_FOR_INPUT is an auto_inc expression.
5202 Then the address address is still needed to store
5203 back the new address. */
5204 && ! rld
[reloadnum
].out
)
5206 /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its
5207 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS
5209 if (type
== RELOAD_FOR_INPUT
&& opnum
== rld
[i
].opnum
5210 && ignore_address_reloads
5211 /* Unless we are reloading an auto_inc expression. */
5212 && ! rld
[reloadnum
].out
)
5214 time2
= rld
[i
].opnum
* 4 + 2;
5216 case RELOAD_FOR_INPUT_ADDRESS
:
5217 if (type
== RELOAD_FOR_INPUT
&& opnum
== rld
[i
].opnum
5218 && ignore_address_reloads
5219 && ! rld
[reloadnum
].out
)
5221 time2
= rld
[i
].opnum
* 4 + 3;
5223 case RELOAD_FOR_INPUT
:
5224 time2
= rld
[i
].opnum
* 4 + 4;
5225 check_earlyclobber
= 1;
5227 /* rld[i].opnum * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4
5228 == MAX_RECOG_OPERAND * 4 */
5229 case RELOAD_FOR_OPADDR_ADDR
:
5230 if (type
== RELOAD_FOR_OPERAND_ADDRESS
&& reloadnum
== i
+ 1
5231 && ignore_address_reloads
5232 && ! rld
[reloadnum
].out
)
5234 time2
= MAX_RECOG_OPERANDS
* 4 + 1;
5236 case RELOAD_FOR_OPERAND_ADDRESS
:
5237 time2
= MAX_RECOG_OPERANDS
* 4 + 2;
5238 check_earlyclobber
= 1;
5240 case RELOAD_FOR_INSN
:
5241 time2
= MAX_RECOG_OPERANDS
* 4 + 3;
5243 case RELOAD_FOR_OUTPUT
:
5244 /* All RELOAD_FOR_OUTPUT reloads become live just after the
5245 instruction is executed. */
5246 time2
= MAX_RECOG_OPERANDS
* 4 + 4;
5248 /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with
5249 the RELOAD_FOR_OUTPUT reloads, so assign it the same time
5251 case RELOAD_FOR_OUTADDR_ADDRESS
:
5252 if (type
== RELOAD_FOR_OUTPUT_ADDRESS
&& reloadnum
== i
+ 1
5253 && ignore_address_reloads
5254 && ! rld
[reloadnum
].out
)
5256 time2
= MAX_RECOG_OPERANDS
* 4 + 4 + rld
[i
].opnum
;
5258 case RELOAD_FOR_OUTPUT_ADDRESS
:
5259 time2
= MAX_RECOG_OPERANDS
* 4 + 5 + rld
[i
].opnum
;
5262 /* If there is no conflict in the input part, handle this
5263 like an output reload. */
5264 if (! rld
[i
].in
|| rtx_equal_p (other_input
, value
))
5266 time2
= MAX_RECOG_OPERANDS
* 4 + 4;
5267 /* Earlyclobbered outputs must conflict with inputs. */
5268 if (earlyclobber_operand_p (rld
[i
].out
))
5269 time2
= MAX_RECOG_OPERANDS
* 4 + 3;
5274 /* RELOAD_OTHER might be live beyond instruction execution,
5275 but this is not obvious when we set time2 = 1. So check
5276 here if there might be a problem with the new reload
5277 clobbering the register used by the RELOAD_OTHER. */
5285 && (! rld
[i
].in
|| rld
[i
].out
5286 || ! rtx_equal_p (other_input
, value
)))
5287 || (out
&& rld
[reloadnum
].out_reg
5288 && time2
>= MAX_RECOG_OPERANDS
* 4 + 3))
5294 /* Earlyclobbered outputs must conflict with inputs. */
5295 if (check_earlyclobber
&& out
&& earlyclobber_operand_p (out
))
5301 /* Return 1 if the value in reload reg REGNO, as used by a reload
5302 needed for the part of the insn specified by OPNUM and TYPE,
5303 may be used to load VALUE into it.
5305 MODE is the mode in which the register is used, this is needed to
5306 determine how many hard regs to test.
5308 Other read-only reloads with the same value do not conflict
5309 unless OUT is nonzero and these other reloads have to live while
5310 output reloads live.
5311 If OUT is CONST0_RTX, this is a special case: it means that the
5312 test should not be for using register REGNO as reload register, but
5313 for copying from register REGNO into the reload register.
5315 RELOADNUM is the number of the reload we want to load this value for;
5316 a reload does not conflict with itself.
5318 When IGNORE_ADDRESS_RELOADS is set, we can not have conflicts with
5319 reloads that load an address for the very reload we are considering.
5321 The caller has to make sure that there is no conflict with the return
5325 free_for_value_p (int regno
, enum machine_mode mode
, int opnum
,
5326 enum reload_type type
, rtx value
, rtx out
, int reloadnum
,
5327 int ignore_address_reloads
)
5329 int nregs
= hard_regno_nregs
[regno
][mode
];
5331 if (! reload_reg_free_for_value_p (regno
, regno
+ nregs
, opnum
, type
,
5332 value
, out
, reloadnum
,
5333 ignore_address_reloads
))
5338 /* Return nonzero if the rtx X is invariant over the current function. */
5339 /* ??? Actually, the places where we use this expect exactly what is
5340 tested here, and not everything that is function invariant. In
5341 particular, the frame pointer and arg pointer are special cased;
5342 pic_offset_table_rtx is not, and we must not spill these things to
5346 function_invariant_p (const_rtx x
)
5350 if (x
== frame_pointer_rtx
|| x
== arg_pointer_rtx
)
5352 if (GET_CODE (x
) == PLUS
5353 && (XEXP (x
, 0) == frame_pointer_rtx
|| XEXP (x
, 0) == arg_pointer_rtx
)
5354 && CONSTANT_P (XEXP (x
, 1)))
5359 /* Determine whether the reload reg X overlaps any rtx'es used for
5360 overriding inheritance. Return nonzero if so. */
5363 conflicts_with_override (rtx x
)
5366 for (i
= 0; i
< n_reloads
; i
++)
5367 if (reload_override_in
[i
]
5368 && reg_overlap_mentioned_p (x
, reload_override_in
[i
]))
5373 /* Give an error message saying we failed to find a reload for INSN,
5374 and clear out reload R. */
5376 failed_reload (rtx insn
, int r
)
5378 if (asm_noperands (PATTERN (insn
)) < 0)
5379 /* It's the compiler's fault. */
5380 fatal_insn ("could not find a spill register", insn
);
5382 /* It's the user's fault; the operand's mode and constraint
5383 don't match. Disable this reload so we don't crash in final. */
5384 error_for_asm (insn
,
5385 "%<asm%> operand constraint incompatible with operand size");
5389 rld
[r
].optional
= 1;
5390 rld
[r
].secondary_p
= 1;
5393 /* I is the index in SPILL_REG_RTX of the reload register we are to allocate
5394 for reload R. If it's valid, get an rtx for it. Return nonzero if
5397 set_reload_reg (int i
, int r
)
5400 rtx reg
= spill_reg_rtx
[i
];
5402 if (reg
== 0 || GET_MODE (reg
) != rld
[r
].mode
)
5403 spill_reg_rtx
[i
] = reg
5404 = gen_rtx_REG (rld
[r
].mode
, spill_regs
[i
]);
5406 regno
= true_regnum (reg
);
5408 /* Detect when the reload reg can't hold the reload mode.
5409 This used to be one `if', but Sequent compiler can't handle that. */
5410 if (HARD_REGNO_MODE_OK (regno
, rld
[r
].mode
))
5412 enum machine_mode test_mode
= VOIDmode
;
5414 test_mode
= GET_MODE (rld
[r
].in
);
5415 /* If rld[r].in has VOIDmode, it means we will load it
5416 in whatever mode the reload reg has: to wit, rld[r].mode.
5417 We have already tested that for validity. */
5418 /* Aside from that, we need to test that the expressions
5419 to reload from or into have modes which are valid for this
5420 reload register. Otherwise the reload insns would be invalid. */
5421 if (! (rld
[r
].in
!= 0 && test_mode
!= VOIDmode
5422 && ! HARD_REGNO_MODE_OK (regno
, test_mode
)))
5423 if (! (rld
[r
].out
!= 0
5424 && ! HARD_REGNO_MODE_OK (regno
, GET_MODE (rld
[r
].out
))))
5426 /* The reg is OK. */
5429 /* Mark as in use for this insn the reload regs we use
5431 mark_reload_reg_in_use (spill_regs
[i
], rld
[r
].opnum
,
5432 rld
[r
].when_needed
, rld
[r
].mode
);
5434 rld
[r
].reg_rtx
= reg
;
5435 reload_spill_index
[r
] = spill_regs
[i
];
5442 /* Find a spill register to use as a reload register for reload R.
5443 LAST_RELOAD is nonzero if this is the last reload for the insn being
5446 Set rld[R].reg_rtx to the register allocated.
5448 We return 1 if successful, or 0 if we couldn't find a spill reg and
5449 we didn't change anything. */
5452 allocate_reload_reg (struct insn_chain
*chain ATTRIBUTE_UNUSED
, int r
,
5457 /* If we put this reload ahead, thinking it is a group,
5458 then insist on finding a group. Otherwise we can grab a
5459 reg that some other reload needs.
5460 (That can happen when we have a 68000 DATA_OR_FP_REG
5461 which is a group of data regs or one fp reg.)
5462 We need not be so restrictive if there are no more reloads
5465 ??? Really it would be nicer to have smarter handling
5466 for that kind of reg class, where a problem like this is normal.
5467 Perhaps those classes should be avoided for reloading
5468 by use of more alternatives. */
5470 int force_group
= rld
[r
].nregs
> 1 && ! last_reload
;
5472 /* If we want a single register and haven't yet found one,
5473 take any reg in the right class and not in use.
5474 If we want a consecutive group, here is where we look for it.
5476 We use two passes so we can first look for reload regs to
5477 reuse, which are already in use for other reloads in this insn,
5478 and only then use additional registers.
5479 I think that maximizing reuse is needed to make sure we don't
5480 run out of reload regs. Suppose we have three reloads, and
5481 reloads A and B can share regs. These need two regs.
5482 Suppose A and B are given different regs.
5483 That leaves none for C. */
5484 for (pass
= 0; pass
< 2; pass
++)
5486 /* I is the index in spill_regs.
5487 We advance it round-robin between insns to use all spill regs
5488 equally, so that inherited reloads have a chance
5489 of leapfrogging each other. */
5493 for (count
= 0; count
< n_spills
; count
++)
5495 int class = (int) rld
[r
].class;
5501 regnum
= spill_regs
[i
];
5503 if ((reload_reg_free_p (regnum
, rld
[r
].opnum
,
5506 /* We check reload_reg_used to make sure we
5507 don't clobber the return register. */
5508 && ! TEST_HARD_REG_BIT (reload_reg_used
, regnum
)
5509 && free_for_value_p (regnum
, rld
[r
].mode
, rld
[r
].opnum
,
5510 rld
[r
].when_needed
, rld
[r
].in
,
5512 && TEST_HARD_REG_BIT (reg_class_contents
[class], regnum
)
5513 && HARD_REGNO_MODE_OK (regnum
, rld
[r
].mode
)
5514 /* Look first for regs to share, then for unshared. But
5515 don't share regs used for inherited reloads; they are
5516 the ones we want to preserve. */
5518 || (TEST_HARD_REG_BIT (reload_reg_used_at_all
,
5520 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit
,
5523 int nr
= hard_regno_nregs
[regnum
][rld
[r
].mode
];
5524 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
5525 (on 68000) got us two FP regs. If NR is 1,
5526 we would reject both of them. */
5529 /* If we need only one reg, we have already won. */
5532 /* But reject a single reg if we demand a group. */
5537 /* Otherwise check that as many consecutive regs as we need
5538 are available here. */
5541 int regno
= regnum
+ nr
- 1;
5542 if (!(TEST_HARD_REG_BIT (reg_class_contents
[class], regno
)
5543 && spill_reg_order
[regno
] >= 0
5544 && reload_reg_free_p (regno
, rld
[r
].opnum
,
5545 rld
[r
].when_needed
)))
5554 /* If we found something on pass 1, omit pass 2. */
5555 if (count
< n_spills
)
5559 /* We should have found a spill register by now. */
5560 if (count
>= n_spills
)
5563 /* I is the index in SPILL_REG_RTX of the reload register we are to
5564 allocate. Get an rtx for it and find its register number. */
5566 return set_reload_reg (i
, r
);
5569 /* Initialize all the tables needed to allocate reload registers.
5570 CHAIN is the insn currently being processed; SAVE_RELOAD_REG_RTX
5571 is the array we use to restore the reg_rtx field for every reload. */
5574 choose_reload_regs_init (struct insn_chain
*chain
, rtx
*save_reload_reg_rtx
)
5578 for (i
= 0; i
< n_reloads
; i
++)
5579 rld
[i
].reg_rtx
= save_reload_reg_rtx
[i
];
5581 memset (reload_inherited
, 0, MAX_RELOADS
);
5582 memset (reload_inheritance_insn
, 0, MAX_RELOADS
* sizeof (rtx
));
5583 memset (reload_override_in
, 0, MAX_RELOADS
* sizeof (rtx
));
5585 CLEAR_HARD_REG_SET (reload_reg_used
);
5586 CLEAR_HARD_REG_SET (reload_reg_used_at_all
);
5587 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr
);
5588 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload
);
5589 CLEAR_HARD_REG_SET (reload_reg_used_in_insn
);
5590 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr
);
5592 CLEAR_HARD_REG_SET (reg_used_in_insn
);
5595 REG_SET_TO_HARD_REG_SET (tmp
, &chain
->live_throughout
);
5596 IOR_HARD_REG_SET (reg_used_in_insn
, tmp
);
5597 REG_SET_TO_HARD_REG_SET (tmp
, &chain
->dead_or_set
);
5598 IOR_HARD_REG_SET (reg_used_in_insn
, tmp
);
5599 compute_use_by_pseudos (®_used_in_insn
, &chain
->live_throughout
);
5600 compute_use_by_pseudos (®_used_in_insn
, &chain
->dead_or_set
);
5603 for (i
= 0; i
< reload_n_operands
; i
++)
5605 CLEAR_HARD_REG_SET (reload_reg_used_in_output
[i
]);
5606 CLEAR_HARD_REG_SET (reload_reg_used_in_input
[i
]);
5607 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr
[i
]);
5608 CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr
[i
]);
5609 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr
[i
]);
5610 CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr
[i
]);
5613 COMPL_HARD_REG_SET (reload_reg_unavailable
, chain
->used_spill_regs
);
5615 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit
);
5617 for (i
= 0; i
< n_reloads
; i
++)
5618 /* If we have already decided to use a certain register,
5619 don't use it in another way. */
5621 mark_reload_reg_in_use (REGNO (rld
[i
].reg_rtx
), rld
[i
].opnum
,
5622 rld
[i
].when_needed
, rld
[i
].mode
);
5625 /* Assign hard reg targets for the pseudo-registers we must reload
5626 into hard regs for this insn.
5627 Also output the instructions to copy them in and out of the hard regs.
5629 For machines with register classes, we are responsible for
5630 finding a reload reg in the proper class. */
5633 choose_reload_regs (struct insn_chain
*chain
)
5635 rtx insn
= chain
->insn
;
5637 unsigned int max_group_size
= 1;
5638 enum reg_class group_class
= NO_REGS
;
5639 int pass
, win
, inheritance
;
5641 rtx save_reload_reg_rtx
[MAX_RELOADS
];
5643 /* In order to be certain of getting the registers we need,
5644 we must sort the reloads into order of increasing register class.
5645 Then our grabbing of reload registers will parallel the process
5646 that provided the reload registers.
5648 Also note whether any of the reloads wants a consecutive group of regs.
5649 If so, record the maximum size of the group desired and what
5650 register class contains all the groups needed by this insn. */
5652 for (j
= 0; j
< n_reloads
; j
++)
5654 reload_order
[j
] = j
;
5655 if (rld
[j
].reg_rtx
!= NULL_RTX
)
5657 gcc_assert (REG_P (rld
[j
].reg_rtx
)
5658 && HARD_REGISTER_P (rld
[j
].reg_rtx
));
5659 reload_spill_index
[j
] = REGNO (rld
[j
].reg_rtx
);
5662 reload_spill_index
[j
] = -1;
5664 if (rld
[j
].nregs
> 1)
5666 max_group_size
= MAX (rld
[j
].nregs
, max_group_size
);
5668 = reg_class_superunion
[(int) rld
[j
].class][(int) group_class
];
5671 save_reload_reg_rtx
[j
] = rld
[j
].reg_rtx
;
5675 qsort (reload_order
, n_reloads
, sizeof (short), reload_reg_class_lower
);
5677 /* If -O, try first with inheritance, then turning it off.
5678 If not -O, don't do inheritance.
5679 Using inheritance when not optimizing leads to paradoxes
5680 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
5681 because one side of the comparison might be inherited. */
5683 for (inheritance
= optimize
> 0; inheritance
>= 0; inheritance
--)
5685 choose_reload_regs_init (chain
, save_reload_reg_rtx
);
5687 /* Process the reloads in order of preference just found.
5688 Beyond this point, subregs can be found in reload_reg_rtx.
5690 This used to look for an existing reloaded home for all of the
5691 reloads, and only then perform any new reloads. But that could lose
5692 if the reloads were done out of reg-class order because a later
5693 reload with a looser constraint might have an old home in a register
5694 needed by an earlier reload with a tighter constraint.
5696 To solve this, we make two passes over the reloads, in the order
5697 described above. In the first pass we try to inherit a reload
5698 from a previous insn. If there is a later reload that needs a
5699 class that is a proper subset of the class being processed, we must
5700 also allocate a spill register during the first pass.
5702 Then make a second pass over the reloads to allocate any reloads
5703 that haven't been given registers yet. */
5705 for (j
= 0; j
< n_reloads
; j
++)
5707 int r
= reload_order
[j
];
5708 rtx search_equiv
= NULL_RTX
;
5710 /* Ignore reloads that got marked inoperative. */
5711 if (rld
[r
].out
== 0 && rld
[r
].in
== 0
5712 && ! rld
[r
].secondary_p
)
5715 /* If find_reloads chose to use reload_in or reload_out as a reload
5716 register, we don't need to chose one. Otherwise, try even if it
5717 found one since we might save an insn if we find the value lying
5719 Try also when reload_in is a pseudo without a hard reg. */
5720 if (rld
[r
].in
!= 0 && rld
[r
].reg_rtx
!= 0
5721 && (rtx_equal_p (rld
[r
].in
, rld
[r
].reg_rtx
)
5722 || (rtx_equal_p (rld
[r
].out
, rld
[r
].reg_rtx
)
5723 && !MEM_P (rld
[r
].in
)
5724 && true_regnum (rld
[r
].in
) < FIRST_PSEUDO_REGISTER
)))
5727 #if 0 /* No longer needed for correct operation.
5728 It might give better code, or might not; worth an experiment? */
5729 /* If this is an optional reload, we can't inherit from earlier insns
5730 until we are sure that any non-optional reloads have been allocated.
5731 The following code takes advantage of the fact that optional reloads
5732 are at the end of reload_order. */
5733 if (rld
[r
].optional
!= 0)
5734 for (i
= 0; i
< j
; i
++)
5735 if ((rld
[reload_order
[i
]].out
!= 0
5736 || rld
[reload_order
[i
]].in
!= 0
5737 || rld
[reload_order
[i
]].secondary_p
)
5738 && ! rld
[reload_order
[i
]].optional
5739 && rld
[reload_order
[i
]].reg_rtx
== 0)
5740 allocate_reload_reg (chain
, reload_order
[i
], 0);
5743 /* First see if this pseudo is already available as reloaded
5744 for a previous insn. We cannot try to inherit for reloads
5745 that are smaller than the maximum number of registers needed
5746 for groups unless the register we would allocate cannot be used
5749 We could check here to see if this is a secondary reload for
5750 an object that is already in a register of the desired class.
5751 This would avoid the need for the secondary reload register.
5752 But this is complex because we can't easily determine what
5753 objects might want to be loaded via this reload. So let a
5754 register be allocated here. In `emit_reload_insns' we suppress
5755 one of the loads in the case described above. */
5761 enum machine_mode mode
= VOIDmode
;
5765 else if (REG_P (rld
[r
].in
))
5767 regno
= REGNO (rld
[r
].in
);
5768 mode
= GET_MODE (rld
[r
].in
);
5770 else if (REG_P (rld
[r
].in_reg
))
5772 regno
= REGNO (rld
[r
].in_reg
);
5773 mode
= GET_MODE (rld
[r
].in_reg
);
5775 else if (GET_CODE (rld
[r
].in_reg
) == SUBREG
5776 && REG_P (SUBREG_REG (rld
[r
].in_reg
)))
5778 regno
= REGNO (SUBREG_REG (rld
[r
].in_reg
));
5779 if (regno
< FIRST_PSEUDO_REGISTER
)
5780 regno
= subreg_regno (rld
[r
].in_reg
);
5782 byte
= SUBREG_BYTE (rld
[r
].in_reg
);
5783 mode
= GET_MODE (rld
[r
].in_reg
);
5786 else if (GET_RTX_CLASS (GET_CODE (rld
[r
].in_reg
)) == RTX_AUTOINC
5787 && REG_P (XEXP (rld
[r
].in_reg
, 0)))
5789 regno
= REGNO (XEXP (rld
[r
].in_reg
, 0));
5790 mode
= GET_MODE (XEXP (rld
[r
].in_reg
, 0));
5791 rld
[r
].out
= rld
[r
].in
;
5795 /* This won't work, since REGNO can be a pseudo reg number.
5796 Also, it takes much more hair to keep track of all the things
5797 that can invalidate an inherited reload of part of a pseudoreg. */
5798 else if (GET_CODE (rld
[r
].in
) == SUBREG
5799 && REG_P (SUBREG_REG (rld
[r
].in
)))
5800 regno
= subreg_regno (rld
[r
].in
);
5804 && reg_last_reload_reg
[regno
] != 0
5805 #ifdef CANNOT_CHANGE_MODE_CLASS
5806 /* Verify that the register it's in can be used in
5808 && !REG_CANNOT_CHANGE_MODE_P (REGNO (reg_last_reload_reg
[regno
]),
5809 GET_MODE (reg_last_reload_reg
[regno
]),
5814 enum reg_class
class = rld
[r
].class, last_class
;
5815 rtx last_reg
= reg_last_reload_reg
[regno
];
5816 enum machine_mode need_mode
;
5818 i
= REGNO (last_reg
);
5819 i
+= subreg_regno_offset (i
, GET_MODE (last_reg
), byte
, mode
);
5820 last_class
= REGNO_REG_CLASS (i
);
5826 = smallest_mode_for_size (GET_MODE_BITSIZE (mode
)
5827 + byte
* BITS_PER_UNIT
,
5828 GET_MODE_CLASS (mode
));
5830 if ((GET_MODE_SIZE (GET_MODE (last_reg
))
5831 >= GET_MODE_SIZE (need_mode
))
5832 && reg_reloaded_contents
[i
] == regno
5833 && TEST_HARD_REG_BIT (reg_reloaded_valid
, i
)
5834 && HARD_REGNO_MODE_OK (i
, rld
[r
].mode
)
5835 && (TEST_HARD_REG_BIT (reg_class_contents
[(int) class], i
)
5836 /* Even if we can't use this register as a reload
5837 register, we might use it for reload_override_in,
5838 if copying it to the desired class is cheap
5840 || ((REGISTER_MOVE_COST (mode
, last_class
, class)
5841 < MEMORY_MOVE_COST (mode
, class, 1))
5842 && (secondary_reload_class (1, class, mode
,
5845 #ifdef SECONDARY_MEMORY_NEEDED
5846 && ! SECONDARY_MEMORY_NEEDED (last_class
, class,
5851 && (rld
[r
].nregs
== max_group_size
5852 || ! TEST_HARD_REG_BIT (reg_class_contents
[(int) group_class
],
5854 && free_for_value_p (i
, rld
[r
].mode
, rld
[r
].opnum
,
5855 rld
[r
].when_needed
, rld
[r
].in
,
5858 /* If a group is needed, verify that all the subsequent
5859 registers still have their values intact. */
5860 int nr
= hard_regno_nregs
[i
][rld
[r
].mode
];
5863 for (k
= 1; k
< nr
; k
++)
5864 if (reg_reloaded_contents
[i
+ k
] != regno
5865 || ! TEST_HARD_REG_BIT (reg_reloaded_valid
, i
+ k
))
5873 last_reg
= (GET_MODE (last_reg
) == mode
5874 ? last_reg
: gen_rtx_REG (mode
, i
));
5877 for (k
= 0; k
< nr
; k
++)
5878 bad_for_class
|= ! TEST_HARD_REG_BIT (reg_class_contents
[(int) rld
[r
].class],
5881 /* We found a register that contains the
5882 value we need. If this register is the
5883 same as an `earlyclobber' operand of the
5884 current insn, just mark it as a place to
5885 reload from since we can't use it as the
5886 reload register itself. */
5888 for (i1
= 0; i1
< n_earlyclobbers
; i1
++)
5889 if (reg_overlap_mentioned_for_reload_p
5890 (reg_last_reload_reg
[regno
],
5891 reload_earlyclobbers
[i1
]))
5894 if (i1
!= n_earlyclobbers
5895 || ! (free_for_value_p (i
, rld
[r
].mode
,
5897 rld
[r
].when_needed
, rld
[r
].in
,
5899 /* Don't use it if we'd clobber a pseudo reg. */
5900 || (TEST_HARD_REG_BIT (reg_used_in_insn
, i
)
5902 && ! TEST_HARD_REG_BIT (reg_reloaded_dead
, i
))
5903 /* Don't clobber the frame pointer. */
5904 || (i
== HARD_FRAME_POINTER_REGNUM
5905 && frame_pointer_needed
5907 /* Don't really use the inherited spill reg
5908 if we need it wider than we've got it. */
5909 || (GET_MODE_SIZE (rld
[r
].mode
)
5910 > GET_MODE_SIZE (mode
))
5913 /* If find_reloads chose reload_out as reload
5914 register, stay with it - that leaves the
5915 inherited register for subsequent reloads. */
5916 || (rld
[r
].out
&& rld
[r
].reg_rtx
5917 && rtx_equal_p (rld
[r
].out
, rld
[r
].reg_rtx
)))
5919 if (! rld
[r
].optional
)
5921 reload_override_in
[r
] = last_reg
;
5922 reload_inheritance_insn
[r
]
5923 = reg_reloaded_insn
[i
];
5929 /* We can use this as a reload reg. */
5930 /* Mark the register as in use for this part of
5932 mark_reload_reg_in_use (i
,
5936 rld
[r
].reg_rtx
= last_reg
;
5937 reload_inherited
[r
] = 1;
5938 reload_inheritance_insn
[r
]
5939 = reg_reloaded_insn
[i
];
5940 reload_spill_index
[r
] = i
;
5941 for (k
= 0; k
< nr
; k
++)
5942 SET_HARD_REG_BIT (reload_reg_used_for_inherit
,
5950 /* Here's another way to see if the value is already lying around. */
5953 && ! reload_inherited
[r
]
5955 && (CONSTANT_P (rld
[r
].in
)
5956 || GET_CODE (rld
[r
].in
) == PLUS
5957 || REG_P (rld
[r
].in
)
5958 || MEM_P (rld
[r
].in
))
5959 && (rld
[r
].nregs
== max_group_size
5960 || ! reg_classes_intersect_p (rld
[r
].class, group_class
)))
5961 search_equiv
= rld
[r
].in
;
5962 /* If this is an output reload from a simple move insn, look
5963 if an equivalence for the input is available. */
5964 else if (inheritance
&& rld
[r
].in
== 0 && rld
[r
].out
!= 0)
5966 rtx set
= single_set (insn
);
5969 && rtx_equal_p (rld
[r
].out
, SET_DEST (set
))
5970 && CONSTANT_P (SET_SRC (set
)))
5971 search_equiv
= SET_SRC (set
);
5977 = find_equiv_reg (search_equiv
, insn
, rld
[r
].class,
5978 -1, NULL
, 0, rld
[r
].mode
);
5984 regno
= REGNO (equiv
);
5987 /* This must be a SUBREG of a hard register.
5988 Make a new REG since this might be used in an
5989 address and not all machines support SUBREGs
5991 gcc_assert (GET_CODE (equiv
) == SUBREG
);
5992 regno
= subreg_regno (equiv
);
5993 equiv
= gen_rtx_REG (rld
[r
].mode
, regno
);
5994 /* If we choose EQUIV as the reload register, but the
5995 loop below decides to cancel the inheritance, we'll
5996 end up reloading EQUIV in rld[r].mode, not the mode
5997 it had originally. That isn't safe when EQUIV isn't
5998 available as a spill register since its value might
5999 still be live at this point. */
6000 for (i
= regno
; i
< regno
+ (int) rld
[r
].nregs
; i
++)
6001 if (TEST_HARD_REG_BIT (reload_reg_unavailable
, i
))
6006 /* If we found a spill reg, reject it unless it is free
6007 and of the desired class. */
6011 int bad_for_class
= 0;
6012 int max_regno
= regno
+ rld
[r
].nregs
;
6014 for (i
= regno
; i
< max_regno
; i
++)
6016 regs_used
|= TEST_HARD_REG_BIT (reload_reg_used_at_all
,
6018 bad_for_class
|= ! TEST_HARD_REG_BIT (reg_class_contents
[(int) rld
[r
].class],
6023 && ! free_for_value_p (regno
, rld
[r
].mode
,
6024 rld
[r
].opnum
, rld
[r
].when_needed
,
6025 rld
[r
].in
, rld
[r
].out
, r
, 1))
6030 if (equiv
!= 0 && ! HARD_REGNO_MODE_OK (regno
, rld
[r
].mode
))
6033 /* We found a register that contains the value we need.
6034 If this register is the same as an `earlyclobber' operand
6035 of the current insn, just mark it as a place to reload from
6036 since we can't use it as the reload register itself. */
6039 for (i
= 0; i
< n_earlyclobbers
; i
++)
6040 if (reg_overlap_mentioned_for_reload_p (equiv
,
6041 reload_earlyclobbers
[i
]))
6043 if (! rld
[r
].optional
)
6044 reload_override_in
[r
] = equiv
;
6049 /* If the equiv register we have found is explicitly clobbered
6050 in the current insn, it depends on the reload type if we
6051 can use it, use it for reload_override_in, or not at all.
6052 In particular, we then can't use EQUIV for a
6053 RELOAD_FOR_OUTPUT_ADDRESS reload. */
6057 if (regno_clobbered_p (regno
, insn
, rld
[r
].mode
, 2))
6058 switch (rld
[r
].when_needed
)
6060 case RELOAD_FOR_OTHER_ADDRESS
:
6061 case RELOAD_FOR_INPADDR_ADDRESS
:
6062 case RELOAD_FOR_INPUT_ADDRESS
:
6063 case RELOAD_FOR_OPADDR_ADDR
:
6066 case RELOAD_FOR_INPUT
:
6067 case RELOAD_FOR_OPERAND_ADDRESS
:
6068 if (! rld
[r
].optional
)
6069 reload_override_in
[r
] = equiv
;
6075 else if (regno_clobbered_p (regno
, insn
, rld
[r
].mode
, 1))
6076 switch (rld
[r
].when_needed
)
6078 case RELOAD_FOR_OTHER_ADDRESS
:
6079 case RELOAD_FOR_INPADDR_ADDRESS
:
6080 case RELOAD_FOR_INPUT_ADDRESS
:
6081 case RELOAD_FOR_OPADDR_ADDR
:
6082 case RELOAD_FOR_OPERAND_ADDRESS
:
6083 case RELOAD_FOR_INPUT
:
6086 if (! rld
[r
].optional
)
6087 reload_override_in
[r
] = equiv
;
6095 /* If we found an equivalent reg, say no code need be generated
6096 to load it, and use it as our reload reg. */
6098 && (regno
!= HARD_FRAME_POINTER_REGNUM
6099 || !frame_pointer_needed
))
6101 int nr
= hard_regno_nregs
[regno
][rld
[r
].mode
];
6103 rld
[r
].reg_rtx
= equiv
;
6104 reload_inherited
[r
] = 1;
6106 /* If reg_reloaded_valid is not set for this register,
6107 there might be a stale spill_reg_store lying around.
6108 We must clear it, since otherwise emit_reload_insns
6109 might delete the store. */
6110 if (! TEST_HARD_REG_BIT (reg_reloaded_valid
, regno
))
6111 spill_reg_store
[regno
] = NULL_RTX
;
6112 /* If any of the hard registers in EQUIV are spill
6113 registers, mark them as in use for this insn. */
6114 for (k
= 0; k
< nr
; k
++)
6116 i
= spill_reg_order
[regno
+ k
];
6119 mark_reload_reg_in_use (regno
, rld
[r
].opnum
,
6122 SET_HARD_REG_BIT (reload_reg_used_for_inherit
,
6129 /* If we found a register to use already, or if this is an optional
6130 reload, we are done. */
6131 if (rld
[r
].reg_rtx
!= 0 || rld
[r
].optional
!= 0)
6135 /* No longer needed for correct operation. Might or might
6136 not give better code on the average. Want to experiment? */
6138 /* See if there is a later reload that has a class different from our
6139 class that intersects our class or that requires less register
6140 than our reload. If so, we must allocate a register to this
6141 reload now, since that reload might inherit a previous reload
6142 and take the only available register in our class. Don't do this
6143 for optional reloads since they will force all previous reloads
6144 to be allocated. Also don't do this for reloads that have been
6147 for (i
= j
+ 1; i
< n_reloads
; i
++)
6149 int s
= reload_order
[i
];
6151 if ((rld
[s
].in
== 0 && rld
[s
].out
== 0
6152 && ! rld
[s
].secondary_p
)
6156 if ((rld
[s
].class != rld
[r
].class
6157 && reg_classes_intersect_p (rld
[r
].class,
6159 || rld
[s
].nregs
< rld
[r
].nregs
)
6166 allocate_reload_reg (chain
, r
, j
== n_reloads
- 1);
6170 /* Now allocate reload registers for anything non-optional that
6171 didn't get one yet. */
6172 for (j
= 0; j
< n_reloads
; j
++)
6174 int r
= reload_order
[j
];
6176 /* Ignore reloads that got marked inoperative. */
6177 if (rld
[r
].out
== 0 && rld
[r
].in
== 0 && ! rld
[r
].secondary_p
)
6180 /* Skip reloads that already have a register allocated or are
6182 if (rld
[r
].reg_rtx
!= 0 || rld
[r
].optional
)
6185 if (! allocate_reload_reg (chain
, r
, j
== n_reloads
- 1))
6189 /* If that loop got all the way, we have won. */
6196 /* Loop around and try without any inheritance. */
6201 /* First undo everything done by the failed attempt
6202 to allocate with inheritance. */
6203 choose_reload_regs_init (chain
, save_reload_reg_rtx
);
6205 /* Some sanity tests to verify that the reloads found in the first
6206 pass are identical to the ones we have now. */
6207 gcc_assert (chain
->n_reloads
== n_reloads
);
6209 for (i
= 0; i
< n_reloads
; i
++)
6211 if (chain
->rld
[i
].regno
< 0 || chain
->rld
[i
].reg_rtx
!= 0)
6213 gcc_assert (chain
->rld
[i
].when_needed
== rld
[i
].when_needed
);
6214 for (j
= 0; j
< n_spills
; j
++)
6215 if (spill_regs
[j
] == chain
->rld
[i
].regno
)
6216 if (! set_reload_reg (j
, i
))
6217 failed_reload (chain
->insn
, i
);
6221 /* If we thought we could inherit a reload, because it seemed that
6222 nothing else wanted the same reload register earlier in the insn,
6223 verify that assumption, now that all reloads have been assigned.
6224 Likewise for reloads where reload_override_in has been set. */
6226 /* If doing expensive optimizations, do one preliminary pass that doesn't
6227 cancel any inheritance, but removes reloads that have been needed only
6228 for reloads that we know can be inherited. */
6229 for (pass
= flag_expensive_optimizations
; pass
>= 0; pass
--)
6231 for (j
= 0; j
< n_reloads
; j
++)
6233 int r
= reload_order
[j
];
6235 if (reload_inherited
[r
] && rld
[r
].reg_rtx
)
6236 check_reg
= rld
[r
].reg_rtx
;
6237 else if (reload_override_in
[r
]
6238 && (REG_P (reload_override_in
[r
])
6239 || GET_CODE (reload_override_in
[r
]) == SUBREG
))
6240 check_reg
= reload_override_in
[r
];
6243 if (! free_for_value_p (true_regnum (check_reg
), rld
[r
].mode
,
6244 rld
[r
].opnum
, rld
[r
].when_needed
, rld
[r
].in
,
6245 (reload_inherited
[r
]
6246 ? rld
[r
].out
: const0_rtx
),
6251 reload_inherited
[r
] = 0;
6252 reload_override_in
[r
] = 0;
6254 /* If we can inherit a RELOAD_FOR_INPUT, or can use a
6255 reload_override_in, then we do not need its related
6256 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads;
6257 likewise for other reload types.
6258 We handle this by removing a reload when its only replacement
6259 is mentioned in reload_in of the reload we are going to inherit.
6260 A special case are auto_inc expressions; even if the input is
6261 inherited, we still need the address for the output. We can
6262 recognize them because they have RELOAD_OUT set to RELOAD_IN.
6263 If we succeeded removing some reload and we are doing a preliminary
6264 pass just to remove such reloads, make another pass, since the
6265 removal of one reload might allow us to inherit another one. */
6267 && rld
[r
].out
!= rld
[r
].in
6268 && remove_address_replacements (rld
[r
].in
) && pass
)
6273 /* Now that reload_override_in is known valid,
6274 actually override reload_in. */
6275 for (j
= 0; j
< n_reloads
; j
++)
6276 if (reload_override_in
[j
])
6277 rld
[j
].in
= reload_override_in
[j
];
6279 /* If this reload won't be done because it has been canceled or is
6280 optional and not inherited, clear reload_reg_rtx so other
6281 routines (such as subst_reloads) don't get confused. */
6282 for (j
= 0; j
< n_reloads
; j
++)
6283 if (rld
[j
].reg_rtx
!= 0
6284 && ((rld
[j
].optional
&& ! reload_inherited
[j
])
6285 || (rld
[j
].in
== 0 && rld
[j
].out
== 0
6286 && ! rld
[j
].secondary_p
)))
6288 int regno
= true_regnum (rld
[j
].reg_rtx
);
6290 if (spill_reg_order
[regno
] >= 0)
6291 clear_reload_reg_in_use (regno
, rld
[j
].opnum
,
6292 rld
[j
].when_needed
, rld
[j
].mode
);
6294 reload_spill_index
[j
] = -1;
6297 /* Record which pseudos and which spill regs have output reloads. */
6298 for (j
= 0; j
< n_reloads
; j
++)
6300 int r
= reload_order
[j
];
6302 i
= reload_spill_index
[r
];
6304 /* I is nonneg if this reload uses a register.
6305 If rld[r].reg_rtx is 0, this is an optional reload
6306 that we opted to ignore. */
6307 if (rld
[r
].out_reg
!= 0 && REG_P (rld
[r
].out_reg
)
6308 && rld
[r
].reg_rtx
!= 0)
6310 int nregno
= REGNO (rld
[r
].out_reg
);
6313 if (nregno
< FIRST_PSEUDO_REGISTER
)
6314 nr
= hard_regno_nregs
[nregno
][rld
[r
].mode
];
6317 SET_REGNO_REG_SET (®_has_output_reload
,
6322 nr
= hard_regno_nregs
[i
][rld
[r
].mode
];
6324 SET_HARD_REG_BIT (reg_is_output_reload
, i
+ nr
);
6327 gcc_assert (rld
[r
].when_needed
== RELOAD_OTHER
6328 || rld
[r
].when_needed
== RELOAD_FOR_OUTPUT
6329 || rld
[r
].when_needed
== RELOAD_FOR_INSN
);
6334 /* Deallocate the reload register for reload R. This is called from
6335 remove_address_replacements. */
6338 deallocate_reload_reg (int r
)
6342 if (! rld
[r
].reg_rtx
)
6344 regno
= true_regnum (rld
[r
].reg_rtx
);
6346 if (spill_reg_order
[regno
] >= 0)
6347 clear_reload_reg_in_use (regno
, rld
[r
].opnum
, rld
[r
].when_needed
,
6349 reload_spill_index
[r
] = -1;
6352 /* If SMALL_REGISTER_CLASSES is nonzero, we may not have merged two
6353 reloads of the same item for fear that we might not have enough reload
6354 registers. However, normally they will get the same reload register
6355 and hence actually need not be loaded twice.
6357 Here we check for the most common case of this phenomenon: when we have
6358 a number of reloads for the same object, each of which were allocated
6359 the same reload_reg_rtx, that reload_reg_rtx is not used for any other
6360 reload, and is not modified in the insn itself. If we find such,
6361 merge all the reloads and set the resulting reload to RELOAD_OTHER.
6362 This will not increase the number of spill registers needed and will
6363 prevent redundant code. */
6366 merge_assigned_reloads (rtx insn
)
6370 /* Scan all the reloads looking for ones that only load values and
6371 are not already RELOAD_OTHER and ones whose reload_reg_rtx are
6372 assigned and not modified by INSN. */
6374 for (i
= 0; i
< n_reloads
; i
++)
6376 int conflicting_input
= 0;
6377 int max_input_address_opnum
= -1;
6378 int min_conflicting_input_opnum
= MAX_RECOG_OPERANDS
;
6380 if (rld
[i
].in
== 0 || rld
[i
].when_needed
== RELOAD_OTHER
6381 || rld
[i
].out
!= 0 || rld
[i
].reg_rtx
== 0
6382 || reg_set_p (rld
[i
].reg_rtx
, insn
))
6385 /* Look at all other reloads. Ensure that the only use of this
6386 reload_reg_rtx is in a reload that just loads the same value
6387 as we do. Note that any secondary reloads must be of the identical
6388 class since the values, modes, and result registers are the
6389 same, so we need not do anything with any secondary reloads. */
6391 for (j
= 0; j
< n_reloads
; j
++)
6393 if (i
== j
|| rld
[j
].reg_rtx
== 0
6394 || ! reg_overlap_mentioned_p (rld
[j
].reg_rtx
,
6398 if (rld
[j
].when_needed
== RELOAD_FOR_INPUT_ADDRESS
6399 && rld
[j
].opnum
> max_input_address_opnum
)
6400 max_input_address_opnum
= rld
[j
].opnum
;
6402 /* If the reload regs aren't exactly the same (e.g, different modes)
6403 or if the values are different, we can't merge this reload.
6404 But if it is an input reload, we might still merge
6405 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_OTHER_ADDRESS reloads. */
6407 if (! rtx_equal_p (rld
[i
].reg_rtx
, rld
[j
].reg_rtx
)
6408 || rld
[j
].out
!= 0 || rld
[j
].in
== 0
6409 || ! rtx_equal_p (rld
[i
].in
, rld
[j
].in
))
6411 if (rld
[j
].when_needed
!= RELOAD_FOR_INPUT
6412 || ((rld
[i
].when_needed
!= RELOAD_FOR_INPUT_ADDRESS
6413 || rld
[i
].opnum
> rld
[j
].opnum
)
6414 && rld
[i
].when_needed
!= RELOAD_FOR_OTHER_ADDRESS
))
6416 conflicting_input
= 1;
6417 if (min_conflicting_input_opnum
> rld
[j
].opnum
)
6418 min_conflicting_input_opnum
= rld
[j
].opnum
;
6422 /* If all is OK, merge the reloads. Only set this to RELOAD_OTHER if
6423 we, in fact, found any matching reloads. */
6426 && max_input_address_opnum
<= min_conflicting_input_opnum
)
6428 gcc_assert (rld
[i
].when_needed
!= RELOAD_FOR_OUTPUT
);
6430 for (j
= 0; j
< n_reloads
; j
++)
6431 if (i
!= j
&& rld
[j
].reg_rtx
!= 0
6432 && rtx_equal_p (rld
[i
].reg_rtx
, rld
[j
].reg_rtx
)
6433 && (! conflicting_input
6434 || rld
[j
].when_needed
== RELOAD_FOR_INPUT_ADDRESS
6435 || rld
[j
].when_needed
== RELOAD_FOR_OTHER_ADDRESS
))
6437 rld
[i
].when_needed
= RELOAD_OTHER
;
6439 reload_spill_index
[j
] = -1;
6440 transfer_replacements (i
, j
);
6443 /* If this is now RELOAD_OTHER, look for any reloads that
6444 load parts of this operand and set them to
6445 RELOAD_FOR_OTHER_ADDRESS if they were for inputs,
6446 RELOAD_OTHER for outputs. Note that this test is
6447 equivalent to looking for reloads for this operand
6450 We must take special care with RELOAD_FOR_OUTPUT_ADDRESS;
6451 it may share registers with a RELOAD_FOR_INPUT, so we can
6452 not change it to RELOAD_FOR_OTHER_ADDRESS. We should
6453 never need to, since we do not modify RELOAD_FOR_OUTPUT.
6455 It is possible that the RELOAD_FOR_OPERAND_ADDRESS
6456 instruction is assigned the same register as the earlier
6457 RELOAD_FOR_OTHER_ADDRESS instruction. Merging these two
6458 instructions will cause the RELOAD_FOR_OTHER_ADDRESS
6459 instruction to be deleted later on. */
6461 if (rld
[i
].when_needed
== RELOAD_OTHER
)
6462 for (j
= 0; j
< n_reloads
; j
++)
6464 && rld
[j
].when_needed
!= RELOAD_OTHER
6465 && rld
[j
].when_needed
!= RELOAD_FOR_OTHER_ADDRESS
6466 && rld
[j
].when_needed
!= RELOAD_FOR_OUTPUT_ADDRESS
6467 && rld
[j
].when_needed
!= RELOAD_FOR_OPERAND_ADDRESS
6468 && (! conflicting_input
6469 || rld
[j
].when_needed
== RELOAD_FOR_INPUT_ADDRESS
6470 || rld
[j
].when_needed
== RELOAD_FOR_INPADDR_ADDRESS
)
6471 && reg_overlap_mentioned_for_reload_p (rld
[j
].in
,
6477 = ((rld
[j
].when_needed
== RELOAD_FOR_INPUT_ADDRESS
6478 || rld
[j
].when_needed
== RELOAD_FOR_INPADDR_ADDRESS
)
6479 ? RELOAD_FOR_OTHER_ADDRESS
: RELOAD_OTHER
);
6481 /* Check to see if we accidentally converted two
6482 reloads that use the same reload register with
6483 different inputs to the same type. If so, the
6484 resulting code won't work. */
6486 for (k
= 0; k
< j
; k
++)
6487 gcc_assert (rld
[k
].in
== 0 || rld
[k
].reg_rtx
== 0
6488 || rld
[k
].when_needed
!= rld
[j
].when_needed
6489 || !rtx_equal_p (rld
[k
].reg_rtx
,
6491 || rtx_equal_p (rld
[k
].in
,
6498 /* These arrays are filled by emit_reload_insns and its subroutines. */
6499 static rtx input_reload_insns
[MAX_RECOG_OPERANDS
];
6500 static rtx other_input_address_reload_insns
= 0;
6501 static rtx other_input_reload_insns
= 0;
6502 static rtx input_address_reload_insns
[MAX_RECOG_OPERANDS
];
6503 static rtx inpaddr_address_reload_insns
[MAX_RECOG_OPERANDS
];
6504 static rtx output_reload_insns
[MAX_RECOG_OPERANDS
];
6505 static rtx output_address_reload_insns
[MAX_RECOG_OPERANDS
];
6506 static rtx outaddr_address_reload_insns
[MAX_RECOG_OPERANDS
];
6507 static rtx operand_reload_insns
= 0;
6508 static rtx other_operand_reload_insns
= 0;
6509 static rtx other_output_reload_insns
[MAX_RECOG_OPERANDS
];
6511 /* Values to be put in spill_reg_store are put here first. */
6512 static rtx new_spill_reg_store
[FIRST_PSEUDO_REGISTER
];
6513 static HARD_REG_SET reg_reloaded_died
;
6515 /* Check if *RELOAD_REG is suitable as an intermediate or scratch register
6516 of class NEW_CLASS with mode NEW_MODE. Or alternatively, if alt_reload_reg
6517 is nonzero, if that is suitable. On success, change *RELOAD_REG to the
6518 adjusted register, and return true. Otherwise, return false. */
6520 reload_adjust_reg_for_temp (rtx
*reload_reg
, rtx alt_reload_reg
,
6521 enum reg_class new_class
,
6522 enum machine_mode new_mode
)
6527 for (reg
= *reload_reg
; reg
; reg
= alt_reload_reg
, alt_reload_reg
= 0)
6529 unsigned regno
= REGNO (reg
);
6531 if (!TEST_HARD_REG_BIT (reg_class_contents
[(int) new_class
], regno
))
6533 if (GET_MODE (reg
) != new_mode
)
6535 if (!HARD_REGNO_MODE_OK (regno
, new_mode
))
6537 if (hard_regno_nregs
[regno
][new_mode
]
6538 > hard_regno_nregs
[regno
][GET_MODE (reg
)])
6540 reg
= reload_adjust_reg_for_mode (reg
, new_mode
);
6548 /* Check if *RELOAD_REG is suitable as a scratch register for the reload
6549 pattern with insn_code ICODE, or alternatively, if alt_reload_reg is
6550 nonzero, if that is suitable. On success, change *RELOAD_REG to the
6551 adjusted register, and return true. Otherwise, return false. */
6553 reload_adjust_reg_for_icode (rtx
*reload_reg
, rtx alt_reload_reg
,
6554 enum insn_code icode
)
6557 enum reg_class new_class
= scratch_reload_class (icode
);
6558 enum machine_mode new_mode
= insn_data
[(int) icode
].operand
[2].mode
;
6560 return reload_adjust_reg_for_temp (reload_reg
, alt_reload_reg
,
6561 new_class
, new_mode
);
6564 /* Generate insns to perform reload RL, which is for the insn in CHAIN and
6565 has the number J. OLD contains the value to be used as input. */
6568 emit_input_reload_insns (struct insn_chain
*chain
, struct reload
*rl
,
6571 rtx insn
= chain
->insn
;
6573 rtx oldequiv_reg
= 0;
6576 enum machine_mode mode
;
6579 /* delete_output_reload is only invoked properly if old contains
6580 the original pseudo register. Since this is replaced with a
6581 hard reg when RELOAD_OVERRIDE_IN is set, see if we can
6582 find the pseudo in RELOAD_IN_REG. */
6583 if (reload_override_in
[j
]
6584 && REG_P (rl
->in_reg
))
6591 else if (REG_P (oldequiv
))
6592 oldequiv_reg
= oldequiv
;
6593 else if (GET_CODE (oldequiv
) == SUBREG
)
6594 oldequiv_reg
= SUBREG_REG (oldequiv
);
6596 reloadreg
= reload_reg_rtx_for_input
[j
];
6597 mode
= GET_MODE (reloadreg
);
6599 /* If we are reloading from a register that was recently stored in
6600 with an output-reload, see if we can prove there was
6601 actually no need to store the old value in it. */
6603 if (optimize
&& REG_P (oldequiv
)
6604 && REGNO (oldequiv
) < FIRST_PSEUDO_REGISTER
6605 && spill_reg_store
[REGNO (oldequiv
)]
6607 && (dead_or_set_p (insn
, spill_reg_stored_to
[REGNO (oldequiv
)])
6608 || rtx_equal_p (spill_reg_stored_to
[REGNO (oldequiv
)],
6610 delete_output_reload (insn
, j
, REGNO (oldequiv
), reloadreg
);
6612 /* Encapsulate OLDEQUIV into the reload mode, then load RELOADREG from
6615 while (GET_CODE (oldequiv
) == SUBREG
&& GET_MODE (oldequiv
) != mode
)
6616 oldequiv
= SUBREG_REG (oldequiv
);
6617 if (GET_MODE (oldequiv
) != VOIDmode
6618 && mode
!= GET_MODE (oldequiv
))
6619 oldequiv
= gen_lowpart_SUBREG (mode
, oldequiv
);
6621 /* Switch to the right place to emit the reload insns. */
6622 switch (rl
->when_needed
)
6625 where
= &other_input_reload_insns
;
6627 case RELOAD_FOR_INPUT
:
6628 where
= &input_reload_insns
[rl
->opnum
];
6630 case RELOAD_FOR_INPUT_ADDRESS
:
6631 where
= &input_address_reload_insns
[rl
->opnum
];
6633 case RELOAD_FOR_INPADDR_ADDRESS
:
6634 where
= &inpaddr_address_reload_insns
[rl
->opnum
];
6636 case RELOAD_FOR_OUTPUT_ADDRESS
:
6637 where
= &output_address_reload_insns
[rl
->opnum
];
6639 case RELOAD_FOR_OUTADDR_ADDRESS
:
6640 where
= &outaddr_address_reload_insns
[rl
->opnum
];
6642 case RELOAD_FOR_OPERAND_ADDRESS
:
6643 where
= &operand_reload_insns
;
6645 case RELOAD_FOR_OPADDR_ADDR
:
6646 where
= &other_operand_reload_insns
;
6648 case RELOAD_FOR_OTHER_ADDRESS
:
6649 where
= &other_input_address_reload_insns
;
6655 push_to_sequence (*where
);
6657 /* Auto-increment addresses must be reloaded in a special way. */
6658 if (rl
->out
&& ! rl
->out_reg
)
6660 /* We are not going to bother supporting the case where a
6661 incremented register can't be copied directly from
6662 OLDEQUIV since this seems highly unlikely. */
6663 gcc_assert (rl
->secondary_in_reload
< 0);
6665 if (reload_inherited
[j
])
6666 oldequiv
= reloadreg
;
6668 old
= XEXP (rl
->in_reg
, 0);
6670 if (optimize
&& REG_P (oldequiv
)
6671 && REGNO (oldequiv
) < FIRST_PSEUDO_REGISTER
6672 && spill_reg_store
[REGNO (oldequiv
)]
6674 && (dead_or_set_p (insn
,
6675 spill_reg_stored_to
[REGNO (oldequiv
)])
6676 || rtx_equal_p (spill_reg_stored_to
[REGNO (oldequiv
)],
6678 delete_output_reload (insn
, j
, REGNO (oldequiv
), reloadreg
);
6680 /* Prevent normal processing of this reload. */
6682 /* Output a special code sequence for this case. */
6683 new_spill_reg_store
[REGNO (reloadreg
)]
6684 = inc_for_reload (reloadreg
, oldequiv
, rl
->out
,
6688 /* If we are reloading a pseudo-register that was set by the previous
6689 insn, see if we can get rid of that pseudo-register entirely
6690 by redirecting the previous insn into our reload register. */
6692 else if (optimize
&& REG_P (old
)
6693 && REGNO (old
) >= FIRST_PSEUDO_REGISTER
6694 && dead_or_set_p (insn
, old
)
6695 /* This is unsafe if some other reload
6696 uses the same reg first. */
6697 && ! conflicts_with_override (reloadreg
)
6698 && free_for_value_p (REGNO (reloadreg
), rl
->mode
, rl
->opnum
,
6699 rl
->when_needed
, old
, rl
->out
, j
, 0))
6701 rtx temp
= PREV_INSN (insn
);
6702 while (temp
&& NOTE_P (temp
))
6703 temp
= PREV_INSN (temp
);
6705 && NONJUMP_INSN_P (temp
)
6706 && GET_CODE (PATTERN (temp
)) == SET
6707 && SET_DEST (PATTERN (temp
)) == old
6708 /* Make sure we can access insn_operand_constraint. */
6709 && asm_noperands (PATTERN (temp
)) < 0
6710 /* This is unsafe if operand occurs more than once in current
6711 insn. Perhaps some occurrences aren't reloaded. */
6712 && count_occurrences (PATTERN (insn
), old
, 0) == 1)
6714 rtx old
= SET_DEST (PATTERN (temp
));
6715 /* Store into the reload register instead of the pseudo. */
6716 SET_DEST (PATTERN (temp
)) = reloadreg
;
6718 /* Verify that resulting insn is valid. */
6719 extract_insn (temp
);
6720 if (constrain_operands (1))
6722 /* If the previous insn is an output reload, the source is
6723 a reload register, and its spill_reg_store entry will
6724 contain the previous destination. This is now
6726 if (REG_P (SET_SRC (PATTERN (temp
)))
6727 && REGNO (SET_SRC (PATTERN (temp
))) < FIRST_PSEUDO_REGISTER
)
6729 spill_reg_store
[REGNO (SET_SRC (PATTERN (temp
)))] = 0;
6730 spill_reg_stored_to
[REGNO (SET_SRC (PATTERN (temp
)))] = 0;
6733 /* If these are the only uses of the pseudo reg,
6734 pretend for GDB it lives in the reload reg we used. */
6735 if (REG_N_DEATHS (REGNO (old
)) == 1
6736 && REG_N_SETS (REGNO (old
)) == 1)
6738 reg_renumber
[REGNO (old
)] = REGNO (reloadreg
);
6739 alter_reg (REGNO (old
), -1);
6745 SET_DEST (PATTERN (temp
)) = old
;
6750 /* We can't do that, so output an insn to load RELOADREG. */
6752 /* If we have a secondary reload, pick up the secondary register
6753 and icode, if any. If OLDEQUIV and OLD are different or
6754 if this is an in-out reload, recompute whether or not we
6755 still need a secondary register and what the icode should
6756 be. If we still need a secondary register and the class or
6757 icode is different, go back to reloading from OLD if using
6758 OLDEQUIV means that we got the wrong type of register. We
6759 cannot have different class or icode due to an in-out reload
6760 because we don't make such reloads when both the input and
6761 output need secondary reload registers. */
6763 if (! special
&& rl
->secondary_in_reload
>= 0)
6765 rtx second_reload_reg
= 0;
6766 rtx third_reload_reg
= 0;
6767 int secondary_reload
= rl
->secondary_in_reload
;
6768 rtx real_oldequiv
= oldequiv
;
6771 enum insn_code icode
;
6772 enum insn_code tertiary_icode
= CODE_FOR_nothing
;
6774 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
6775 and similarly for OLD.
6776 See comments in get_secondary_reload in reload.c. */
6777 /* If it is a pseudo that cannot be replaced with its
6778 equivalent MEM, we must fall back to reload_in, which
6779 will have all the necessary substitutions registered.
6780 Likewise for a pseudo that can't be replaced with its
6781 equivalent constant.
6783 Take extra care for subregs of such pseudos. Note that
6784 we cannot use reg_equiv_mem in this case because it is
6785 not in the right mode. */
6788 if (GET_CODE (tmp
) == SUBREG
)
6789 tmp
= SUBREG_REG (tmp
);
6791 && REGNO (tmp
) >= FIRST_PSEUDO_REGISTER
6792 && (reg_equiv_memory_loc
[REGNO (tmp
)] != 0
6793 || reg_equiv_constant
[REGNO (tmp
)] != 0))
6795 if (! reg_equiv_mem
[REGNO (tmp
)]
6796 || num_not_at_initial_offset
6797 || GET_CODE (oldequiv
) == SUBREG
)
6798 real_oldequiv
= rl
->in
;
6800 real_oldequiv
= reg_equiv_mem
[REGNO (tmp
)];
6804 if (GET_CODE (tmp
) == SUBREG
)
6805 tmp
= SUBREG_REG (tmp
);
6807 && REGNO (tmp
) >= FIRST_PSEUDO_REGISTER
6808 && (reg_equiv_memory_loc
[REGNO (tmp
)] != 0
6809 || reg_equiv_constant
[REGNO (tmp
)] != 0))
6811 if (! reg_equiv_mem
[REGNO (tmp
)]
6812 || num_not_at_initial_offset
6813 || GET_CODE (old
) == SUBREG
)
6816 real_old
= reg_equiv_mem
[REGNO (tmp
)];
6819 second_reload_reg
= rld
[secondary_reload
].reg_rtx
;
6820 if (rld
[secondary_reload
].secondary_in_reload
>= 0)
6822 int tertiary_reload
= rld
[secondary_reload
].secondary_in_reload
;
6824 third_reload_reg
= rld
[tertiary_reload
].reg_rtx
;
6825 tertiary_icode
= rld
[secondary_reload
].secondary_in_icode
;
6826 /* We'd have to add more code for quartary reloads. */
6827 gcc_assert (rld
[tertiary_reload
].secondary_in_reload
< 0);
6829 icode
= rl
->secondary_in_icode
;
6831 if ((old
!= oldequiv
&& ! rtx_equal_p (old
, oldequiv
))
6832 || (rl
->in
!= 0 && rl
->out
!= 0))
6834 secondary_reload_info sri
, sri2
;
6835 enum reg_class new_class
, new_t_class
;
6837 sri
.icode
= CODE_FOR_nothing
;
6838 sri
.prev_sri
= NULL
;
6839 new_class
= targetm
.secondary_reload (1, real_oldequiv
, rl
->class,
6842 if (new_class
== NO_REGS
&& sri
.icode
== CODE_FOR_nothing
)
6843 second_reload_reg
= 0;
6844 else if (new_class
== NO_REGS
)
6846 if (reload_adjust_reg_for_icode (&second_reload_reg
,
6847 third_reload_reg
, sri
.icode
))
6848 icode
= sri
.icode
, third_reload_reg
= 0;
6850 oldequiv
= old
, real_oldequiv
= real_old
;
6852 else if (sri
.icode
!= CODE_FOR_nothing
)
6853 /* We currently lack a way to express this in reloads. */
6857 sri2
.icode
= CODE_FOR_nothing
;
6858 sri2
.prev_sri
= &sri
;
6859 new_t_class
= targetm
.secondary_reload (1, real_oldequiv
,
6860 new_class
, mode
, &sri
);
6861 if (new_t_class
== NO_REGS
&& sri2
.icode
== CODE_FOR_nothing
)
6863 if (reload_adjust_reg_for_temp (&second_reload_reg
,
6866 third_reload_reg
= 0, tertiary_icode
= sri2
.icode
;
6868 oldequiv
= old
, real_oldequiv
= real_old
;
6870 else if (new_t_class
== NO_REGS
&& sri2
.icode
!= CODE_FOR_nothing
)
6872 rtx intermediate
= second_reload_reg
;
6874 if (reload_adjust_reg_for_temp (&intermediate
, NULL
,
6876 && reload_adjust_reg_for_icode (&third_reload_reg
, NULL
,
6879 second_reload_reg
= intermediate
;
6880 tertiary_icode
= sri2
.icode
;
6883 oldequiv
= old
, real_oldequiv
= real_old
;
6885 else if (new_t_class
!= NO_REGS
&& sri2
.icode
== CODE_FOR_nothing
)
6887 rtx intermediate
= second_reload_reg
;
6889 if (reload_adjust_reg_for_temp (&intermediate
, NULL
,
6891 && reload_adjust_reg_for_temp (&third_reload_reg
, NULL
,
6894 second_reload_reg
= intermediate
;
6895 tertiary_icode
= sri2
.icode
;
6898 oldequiv
= old
, real_oldequiv
= real_old
;
6901 /* This could be handled more intelligently too. */
6902 oldequiv
= old
, real_oldequiv
= real_old
;
6906 /* If we still need a secondary reload register, check
6907 to see if it is being used as a scratch or intermediate
6908 register and generate code appropriately. If we need
6909 a scratch register, use REAL_OLDEQUIV since the form of
6910 the insn may depend on the actual address if it is
6913 if (second_reload_reg
)
6915 if (icode
!= CODE_FOR_nothing
)
6917 /* We'd have to add extra code to handle this case. */
6918 gcc_assert (!third_reload_reg
);
6920 emit_insn (GEN_FCN (icode
) (reloadreg
, real_oldequiv
,
6921 second_reload_reg
));
6926 /* See if we need a scratch register to load the
6927 intermediate register (a tertiary reload). */
6928 if (tertiary_icode
!= CODE_FOR_nothing
)
6930 emit_insn ((GEN_FCN (tertiary_icode
)
6931 (second_reload_reg
, real_oldequiv
,
6932 third_reload_reg
)));
6934 else if (third_reload_reg
)
6936 gen_reload (third_reload_reg
, real_oldequiv
,
6939 gen_reload (second_reload_reg
, third_reload_reg
,
6944 gen_reload (second_reload_reg
, real_oldequiv
,
6948 oldequiv
= second_reload_reg
;
6953 if (! special
&& ! rtx_equal_p (reloadreg
, oldequiv
))
6955 rtx real_oldequiv
= oldequiv
;
6957 if ((REG_P (oldequiv
)
6958 && REGNO (oldequiv
) >= FIRST_PSEUDO_REGISTER
6959 && (reg_equiv_memory_loc
[REGNO (oldequiv
)] != 0
6960 || reg_equiv_constant
[REGNO (oldequiv
)] != 0))
6961 || (GET_CODE (oldequiv
) == SUBREG
6962 && REG_P (SUBREG_REG (oldequiv
))
6963 && (REGNO (SUBREG_REG (oldequiv
))
6964 >= FIRST_PSEUDO_REGISTER
)
6965 && ((reg_equiv_memory_loc
6966 [REGNO (SUBREG_REG (oldequiv
))] != 0)
6967 || (reg_equiv_constant
6968 [REGNO (SUBREG_REG (oldequiv
))] != 0)))
6969 || (CONSTANT_P (oldequiv
)
6970 && (PREFERRED_RELOAD_CLASS (oldequiv
,
6971 REGNO_REG_CLASS (REGNO (reloadreg
)))
6973 real_oldequiv
= rl
->in
;
6974 gen_reload (reloadreg
, real_oldequiv
, rl
->opnum
,
6978 if (flag_non_call_exceptions
)
6979 copy_eh_notes (insn
, get_insns ());
6981 /* End this sequence. */
6982 *where
= get_insns ();
6985 /* Update reload_override_in so that delete_address_reloads_1
6986 can see the actual register usage. */
6988 reload_override_in
[j
] = oldequiv
;
6991 /* Generate insns to for the output reload RL, which is for the insn described
6992 by CHAIN and has the number J. */
6994 emit_output_reload_insns (struct insn_chain
*chain
, struct reload
*rl
,
6998 rtx insn
= chain
->insn
;
7001 enum machine_mode mode
;
7005 if (rl
->when_needed
== RELOAD_OTHER
)
7008 push_to_sequence (output_reload_insns
[rl
->opnum
]);
7010 rl_reg_rtx
= reload_reg_rtx_for_output
[j
];
7011 mode
= GET_MODE (rl_reg_rtx
);
7013 reloadreg
= rl_reg_rtx
;
7015 /* If we need two reload regs, set RELOADREG to the intermediate
7016 one, since it will be stored into OLD. We might need a secondary
7017 register only for an input reload, so check again here. */
7019 if (rl
->secondary_out_reload
>= 0)
7022 int secondary_reload
= rl
->secondary_out_reload
;
7023 int tertiary_reload
= rld
[secondary_reload
].secondary_out_reload
;
7025 if (REG_P (old
) && REGNO (old
) >= FIRST_PSEUDO_REGISTER
7026 && reg_equiv_mem
[REGNO (old
)] != 0)
7027 real_old
= reg_equiv_mem
[REGNO (old
)];
7029 if (secondary_reload_class (0, rl
->class, mode
, real_old
) != NO_REGS
)
7031 rtx second_reloadreg
= reloadreg
;
7032 reloadreg
= rld
[secondary_reload
].reg_rtx
;
7034 /* See if RELOADREG is to be used as a scratch register
7035 or as an intermediate register. */
7036 if (rl
->secondary_out_icode
!= CODE_FOR_nothing
)
7038 /* We'd have to add extra code to handle this case. */
7039 gcc_assert (tertiary_reload
< 0);
7041 emit_insn ((GEN_FCN (rl
->secondary_out_icode
)
7042 (real_old
, second_reloadreg
, reloadreg
)));
7047 /* See if we need both a scratch and intermediate reload
7050 enum insn_code tertiary_icode
7051 = rld
[secondary_reload
].secondary_out_icode
;
7053 /* We'd have to add more code for quartary reloads. */
7054 gcc_assert (tertiary_reload
< 0
7055 || rld
[tertiary_reload
].secondary_out_reload
< 0);
7057 if (GET_MODE (reloadreg
) != mode
)
7058 reloadreg
= reload_adjust_reg_for_mode (reloadreg
, mode
);
7060 if (tertiary_icode
!= CODE_FOR_nothing
)
7062 rtx third_reloadreg
= rld
[tertiary_reload
].reg_rtx
;
7065 /* Copy primary reload reg to secondary reload reg.
7066 (Note that these have been swapped above, then
7067 secondary reload reg to OLD using our insn.) */
7069 /* If REAL_OLD is a paradoxical SUBREG, remove it
7070 and try to put the opposite SUBREG on
7072 if (GET_CODE (real_old
) == SUBREG
7073 && (GET_MODE_SIZE (GET_MODE (real_old
))
7074 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (real_old
))))
7075 && 0 != (tem
= gen_lowpart_common
7076 (GET_MODE (SUBREG_REG (real_old
)),
7078 real_old
= SUBREG_REG (real_old
), reloadreg
= tem
;
7080 gen_reload (reloadreg
, second_reloadreg
,
7081 rl
->opnum
, rl
->when_needed
);
7082 emit_insn ((GEN_FCN (tertiary_icode
)
7083 (real_old
, reloadreg
, third_reloadreg
)));
7089 /* Copy between the reload regs here and then to
7092 gen_reload (reloadreg
, second_reloadreg
,
7093 rl
->opnum
, rl
->when_needed
);
7094 if (tertiary_reload
>= 0)
7096 rtx third_reloadreg
= rld
[tertiary_reload
].reg_rtx
;
7098 gen_reload (third_reloadreg
, reloadreg
,
7099 rl
->opnum
, rl
->when_needed
);
7100 reloadreg
= third_reloadreg
;
7107 /* Output the last reload insn. */
7112 /* Don't output the last reload if OLD is not the dest of
7113 INSN and is in the src and is clobbered by INSN. */
7114 if (! flag_expensive_optimizations
7116 || !(set
= single_set (insn
))
7117 || rtx_equal_p (old
, SET_DEST (set
))
7118 || !reg_mentioned_p (old
, SET_SRC (set
))
7119 || !((REGNO (old
) < FIRST_PSEUDO_REGISTER
)
7120 && regno_clobbered_p (REGNO (old
), insn
, rl
->mode
, 0)))
7121 gen_reload (old
, reloadreg
, rl
->opnum
,
7125 /* Look at all insns we emitted, just to be safe. */
7126 for (p
= get_insns (); p
; p
= NEXT_INSN (p
))
7129 rtx pat
= PATTERN (p
);
7131 /* If this output reload doesn't come from a spill reg,
7132 clear any memory of reloaded copies of the pseudo reg.
7133 If this output reload comes from a spill reg,
7134 reg_has_output_reload will make this do nothing. */
7135 note_stores (pat
, forget_old_reloads_1
, NULL
);
7137 if (reg_mentioned_p (rl_reg_rtx
, pat
))
7139 rtx set
= single_set (insn
);
7140 if (reload_spill_index
[j
] < 0
7142 && SET_SRC (set
) == rl_reg_rtx
)
7144 int src
= REGNO (SET_SRC (set
));
7146 reload_spill_index
[j
] = src
;
7147 SET_HARD_REG_BIT (reg_is_output_reload
, src
);
7148 if (find_regno_note (insn
, REG_DEAD
, src
))
7149 SET_HARD_REG_BIT (reg_reloaded_died
, src
);
7151 if (HARD_REGISTER_P (rl_reg_rtx
))
7153 int s
= rl
->secondary_out_reload
;
7154 set
= single_set (p
);
7155 /* If this reload copies only to the secondary reload
7156 register, the secondary reload does the actual
7158 if (s
>= 0 && set
== NULL_RTX
)
7159 /* We can't tell what function the secondary reload
7160 has and where the actual store to the pseudo is
7161 made; leave new_spill_reg_store alone. */
7164 && SET_SRC (set
) == rl_reg_rtx
7165 && SET_DEST (set
) == rld
[s
].reg_rtx
)
7167 /* Usually the next instruction will be the
7168 secondary reload insn; if we can confirm
7169 that it is, setting new_spill_reg_store to
7170 that insn will allow an extra optimization. */
7171 rtx s_reg
= rld
[s
].reg_rtx
;
7172 rtx next
= NEXT_INSN (p
);
7173 rld
[s
].out
= rl
->out
;
7174 rld
[s
].out_reg
= rl
->out_reg
;
7175 set
= single_set (next
);
7176 if (set
&& SET_SRC (set
) == s_reg
7177 && ! new_spill_reg_store
[REGNO (s_reg
)])
7179 SET_HARD_REG_BIT (reg_is_output_reload
,
7181 new_spill_reg_store
[REGNO (s_reg
)] = next
;
7185 new_spill_reg_store
[REGNO (rl_reg_rtx
)] = p
;
7190 if (rl
->when_needed
== RELOAD_OTHER
)
7192 emit_insn (other_output_reload_insns
[rl
->opnum
]);
7193 other_output_reload_insns
[rl
->opnum
] = get_insns ();
7196 output_reload_insns
[rl
->opnum
] = get_insns ();
7198 if (flag_non_call_exceptions
)
7199 copy_eh_notes (insn
, get_insns ());
7204 /* Do input reloading for reload RL, which is for the insn described by CHAIN
7205 and has the number J. */
7207 do_input_reload (struct insn_chain
*chain
, struct reload
*rl
, int j
)
7209 rtx insn
= chain
->insn
;
7210 rtx old
= (rl
->in
&& MEM_P (rl
->in
)
7211 ? rl
->in_reg
: rl
->in
);
7212 rtx reg_rtx
= rl
->reg_rtx
;
7216 enum machine_mode mode
;
7218 /* Determine the mode to reload in.
7219 This is very tricky because we have three to choose from.
7220 There is the mode the insn operand wants (rl->inmode).
7221 There is the mode of the reload register RELOADREG.
7222 There is the intrinsic mode of the operand, which we could find
7223 by stripping some SUBREGs.
7224 It turns out that RELOADREG's mode is irrelevant:
7225 we can change that arbitrarily.
7227 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
7228 then the reload reg may not support QImode moves, so use SImode.
7229 If foo is in memory due to spilling a pseudo reg, this is safe,
7230 because the QImode value is in the least significant part of a
7231 slot big enough for a SImode. If foo is some other sort of
7232 memory reference, then it is impossible to reload this case,
7233 so previous passes had better make sure this never happens.
7235 Then consider a one-word union which has SImode and one of its
7236 members is a float, being fetched as (SUBREG:SF union:SI).
7237 We must fetch that as SFmode because we could be loading into
7238 a float-only register. In this case OLD's mode is correct.
7240 Consider an immediate integer: it has VOIDmode. Here we need
7241 to get a mode from something else.
7243 In some cases, there is a fourth mode, the operand's
7244 containing mode. If the insn specifies a containing mode for
7245 this operand, it overrides all others.
7247 I am not sure whether the algorithm here is always right,
7248 but it does the right things in those cases. */
7250 mode
= GET_MODE (old
);
7251 if (mode
== VOIDmode
)
7254 /* We cannot use gen_lowpart_common since it can do the wrong thing
7255 when REG_RTX has a multi-word mode. Note that REG_RTX must
7256 always be a REG here. */
7257 if (GET_MODE (reg_rtx
) != mode
)
7258 reg_rtx
= reload_adjust_reg_for_mode (reg_rtx
, mode
);
7260 reload_reg_rtx_for_input
[j
] = reg_rtx
;
7263 /* AUTO_INC reloads need to be handled even if inherited. We got an
7264 AUTO_INC reload if reload_out is set but reload_out_reg isn't. */
7265 && (! reload_inherited
[j
] || (rl
->out
&& ! rl
->out_reg
))
7266 && ! rtx_equal_p (reg_rtx
, old
)
7268 emit_input_reload_insns (chain
, rld
+ j
, old
, j
);
7270 /* When inheriting a wider reload, we have a MEM in rl->in,
7271 e.g. inheriting a SImode output reload for
7272 (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */
7273 if (optimize
&& reload_inherited
[j
] && rl
->in
7275 && MEM_P (rl
->in_reg
)
7276 && reload_spill_index
[j
] >= 0
7277 && TEST_HARD_REG_BIT (reg_reloaded_valid
, reload_spill_index
[j
]))
7278 rl
->in
= regno_reg_rtx
[reg_reloaded_contents
[reload_spill_index
[j
]]];
7280 /* If we are reloading a register that was recently stored in with an
7281 output-reload, see if we can prove there was
7282 actually no need to store the old value in it. */
7285 && (reload_inherited
[j
] || reload_override_in
[j
])
7288 && spill_reg_store
[REGNO (reg_rtx
)] != 0
7290 /* There doesn't seem to be any reason to restrict this to pseudos
7291 and doing so loses in the case where we are copying from a
7292 register of the wrong class. */
7293 && !HARD_REGISTER_P (spill_reg_stored_to
[REGNO (reg_rtx
)])
7295 /* The insn might have already some references to stackslots
7296 replaced by MEMs, while reload_out_reg still names the
7298 && (dead_or_set_p (insn
, spill_reg_stored_to
[REGNO (reg_rtx
)])
7299 || rtx_equal_p (spill_reg_stored_to
[REGNO (reg_rtx
)], rl
->out_reg
)))
7300 delete_output_reload (insn
, j
, REGNO (reg_rtx
), reg_rtx
);
7303 /* Do output reloading for reload RL, which is for the insn described by
7304 CHAIN and has the number J.
7305 ??? At some point we need to support handling output reloads of
7306 JUMP_INSNs or insns that set cc0. */
7308 do_output_reload (struct insn_chain
*chain
, struct reload
*rl
, int j
)
7311 rtx insn
= chain
->insn
;
7312 /* If this is an output reload that stores something that is
7313 not loaded in this same reload, see if we can eliminate a previous
7315 rtx pseudo
= rl
->out_reg
;
7316 rtx reg_rtx
= rl
->reg_rtx
;
7318 if (rl
->out
&& reg_rtx
)
7320 enum machine_mode mode
;
7322 /* Determine the mode to reload in.
7323 See comments above (for input reloading). */
7324 mode
= GET_MODE (rl
->out
);
7325 if (mode
== VOIDmode
)
7327 /* VOIDmode should never happen for an output. */
7328 if (asm_noperands (PATTERN (insn
)) < 0)
7329 /* It's the compiler's fault. */
7330 fatal_insn ("VOIDmode on an output", insn
);
7331 error_for_asm (insn
, "output operand is constant in %<asm%>");
7332 /* Prevent crash--use something we know is valid. */
7334 rl
->out
= gen_rtx_REG (mode
, REGNO (reg_rtx
));
7336 if (GET_MODE (reg_rtx
) != mode
)
7337 reg_rtx
= reload_adjust_reg_for_mode (reg_rtx
, mode
);
7339 reload_reg_rtx_for_output
[j
] = reg_rtx
;
7344 && ! rtx_equal_p (rl
->in_reg
, pseudo
)
7345 && REGNO (pseudo
) >= FIRST_PSEUDO_REGISTER
7346 && reg_last_reload_reg
[REGNO (pseudo
)])
7348 int pseudo_no
= REGNO (pseudo
);
7349 int last_regno
= REGNO (reg_last_reload_reg
[pseudo_no
]);
7351 /* We don't need to test full validity of last_regno for
7352 inherit here; we only want to know if the store actually
7353 matches the pseudo. */
7354 if (TEST_HARD_REG_BIT (reg_reloaded_valid
, last_regno
)
7355 && reg_reloaded_contents
[last_regno
] == pseudo_no
7356 && spill_reg_store
[last_regno
]
7357 && rtx_equal_p (pseudo
, spill_reg_stored_to
[last_regno
]))
7358 delete_output_reload (insn
, j
, last_regno
, reg_rtx
);
7364 || rtx_equal_p (old
, reg_rtx
))
7367 /* An output operand that dies right away does need a reload,
7368 but need not be copied from it. Show the new location in the
7370 if ((REG_P (old
) || GET_CODE (old
) == SCRATCH
)
7371 && (note
= find_reg_note (insn
, REG_UNUSED
, old
)) != 0)
7373 XEXP (note
, 0) = reg_rtx
;
7376 /* Likewise for a SUBREG of an operand that dies. */
7377 else if (GET_CODE (old
) == SUBREG
7378 && REG_P (SUBREG_REG (old
))
7379 && 0 != (note
= find_reg_note (insn
, REG_UNUSED
,
7382 XEXP (note
, 0) = gen_lowpart_common (GET_MODE (old
), reg_rtx
);
7385 else if (GET_CODE (old
) == SCRATCH
)
7386 /* If we aren't optimizing, there won't be a REG_UNUSED note,
7387 but we don't want to make an output reload. */
7390 /* If is a JUMP_INSN, we can't support output reloads yet. */
7391 gcc_assert (NONJUMP_INSN_P (insn
));
7393 emit_output_reload_insns (chain
, rld
+ j
, j
);
7396 /* A reload copies values of MODE from register SRC to register DEST.
7397 Return true if it can be treated for inheritance purposes like a
7398 group of reloads, each one reloading a single hard register. The
7399 caller has already checked that (reg:MODE SRC) and (reg:MODE DEST)
7400 occupy the same number of hard registers. */
7403 inherit_piecemeal_p (int dest ATTRIBUTE_UNUSED
,
7404 int src ATTRIBUTE_UNUSED
,
7405 enum machine_mode mode ATTRIBUTE_UNUSED
)
7407 #ifdef CANNOT_CHANGE_MODE_CLASS
7408 return (!REG_CANNOT_CHANGE_MODE_P (dest
, mode
, reg_raw_mode
[dest
])
7409 && !REG_CANNOT_CHANGE_MODE_P (src
, mode
, reg_raw_mode
[src
]));
7415 /* Output insns to reload values in and out of the chosen reload regs. */
7418 emit_reload_insns (struct insn_chain
*chain
)
7420 rtx insn
= chain
->insn
;
7424 CLEAR_HARD_REG_SET (reg_reloaded_died
);
7426 for (j
= 0; j
< reload_n_operands
; j
++)
7427 input_reload_insns
[j
] = input_address_reload_insns
[j
]
7428 = inpaddr_address_reload_insns
[j
]
7429 = output_reload_insns
[j
] = output_address_reload_insns
[j
]
7430 = outaddr_address_reload_insns
[j
]
7431 = other_output_reload_insns
[j
] = 0;
7432 other_input_address_reload_insns
= 0;
7433 other_input_reload_insns
= 0;
7434 operand_reload_insns
= 0;
7435 other_operand_reload_insns
= 0;
7437 /* Dump reloads into the dump file. */
7440 fprintf (dump_file
, "\nReloads for insn # %d\n", INSN_UID (insn
));
7441 debug_reload_to_stream (dump_file
);
7444 /* Now output the instructions to copy the data into and out of the
7445 reload registers. Do these in the order that the reloads were reported,
7446 since reloads of base and index registers precede reloads of operands
7447 and the operands may need the base and index registers reloaded. */
7449 for (j
= 0; j
< n_reloads
; j
++)
7451 if (rld
[j
].reg_rtx
&& HARD_REGISTER_P (rld
[j
].reg_rtx
))
7455 for (i
= REGNO (rld
[j
].reg_rtx
); i
< END_REGNO (rld
[j
].reg_rtx
); i
++)
7456 new_spill_reg_store
[i
] = 0;
7459 do_input_reload (chain
, rld
+ j
, j
);
7460 do_output_reload (chain
, rld
+ j
, j
);
7463 /* Now write all the insns we made for reloads in the order expected by
7464 the allocation functions. Prior to the insn being reloaded, we write
7465 the following reloads:
7467 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
7469 RELOAD_OTHER reloads.
7471 For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
7472 by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
7473 RELOAD_FOR_INPUT reload for the operand.
7475 RELOAD_FOR_OPADDR_ADDRS reloads.
7477 RELOAD_FOR_OPERAND_ADDRESS reloads.
7479 After the insn being reloaded, we write the following:
7481 For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
7482 by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
7483 RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
7484 reloads for the operand. The RELOAD_OTHER output reloads are
7485 output in descending order by reload number. */
7487 emit_insn_before (other_input_address_reload_insns
, insn
);
7488 emit_insn_before (other_input_reload_insns
, insn
);
7490 for (j
= 0; j
< reload_n_operands
; j
++)
7492 emit_insn_before (inpaddr_address_reload_insns
[j
], insn
);
7493 emit_insn_before (input_address_reload_insns
[j
], insn
);
7494 emit_insn_before (input_reload_insns
[j
], insn
);
7497 emit_insn_before (other_operand_reload_insns
, insn
);
7498 emit_insn_before (operand_reload_insns
, insn
);
7500 for (j
= 0; j
< reload_n_operands
; j
++)
7502 rtx x
= emit_insn_after (outaddr_address_reload_insns
[j
], insn
);
7503 x
= emit_insn_after (output_address_reload_insns
[j
], x
);
7504 x
= emit_insn_after (output_reload_insns
[j
], x
);
7505 emit_insn_after (other_output_reload_insns
[j
], x
);
7508 /* For all the spill regs newly reloaded in this instruction,
7509 record what they were reloaded from, so subsequent instructions
7510 can inherit the reloads.
7512 Update spill_reg_store for the reloads of this insn.
7513 Copy the elements that were updated in the loop above. */
7515 for (j
= 0; j
< n_reloads
; j
++)
7517 int r
= reload_order
[j
];
7518 int i
= reload_spill_index
[r
];
7520 /* If this is a non-inherited input reload from a pseudo, we must
7521 clear any memory of a previous store to the same pseudo. Only do
7522 something if there will not be an output reload for the pseudo
7524 if (rld
[r
].in_reg
!= 0
7525 && ! (reload_inherited
[r
] || reload_override_in
[r
]))
7527 rtx reg
= rld
[r
].in_reg
;
7529 if (GET_CODE (reg
) == SUBREG
)
7530 reg
= SUBREG_REG (reg
);
7533 && REGNO (reg
) >= FIRST_PSEUDO_REGISTER
7534 && !REGNO_REG_SET_P (®_has_output_reload
, REGNO (reg
)))
7536 int nregno
= REGNO (reg
);
7538 if (reg_last_reload_reg
[nregno
])
7540 int last_regno
= REGNO (reg_last_reload_reg
[nregno
]);
7542 if (reg_reloaded_contents
[last_regno
] == nregno
)
7543 spill_reg_store
[last_regno
] = 0;
7548 /* I is nonneg if this reload used a register.
7549 If rld[r].reg_rtx is 0, this is an optional reload
7550 that we opted to ignore. */
7552 if (i
>= 0 && rld
[r
].reg_rtx
!= 0)
7554 int nr
= hard_regno_nregs
[i
][GET_MODE (rld
[r
].reg_rtx
)];
7557 /* For a multi register reload, we need to check if all or part
7558 of the value lives to the end. */
7559 for (k
= 0; k
< nr
; k
++)
7560 if (reload_reg_reaches_end_p (i
+ k
, rld
[r
].opnum
,
7561 rld
[r
].when_needed
))
7562 CLEAR_HARD_REG_BIT (reg_reloaded_valid
, i
+ k
);
7564 /* Maybe the spill reg contains a copy of reload_out. */
7566 && (REG_P (rld
[r
].out
)
7570 || REG_P (rld
[r
].out_reg
)))
7573 enum machine_mode mode
;
7576 reg
= reload_reg_rtx_for_output
[r
];
7577 mode
= GET_MODE (reg
);
7578 regno
= REGNO (reg
);
7579 nregs
= hard_regno_nregs
[regno
][mode
];
7580 if (reload_regs_reach_end_p (regno
, nregs
, rld
[r
].opnum
,
7581 rld
[r
].when_needed
))
7583 rtx out
= (REG_P (rld
[r
].out
)
7587 /* AUTO_INC */ : XEXP (rld
[r
].in_reg
, 0));
7588 int out_regno
= REGNO (out
);
7589 int out_nregs
= (!HARD_REGISTER_NUM_P (out_regno
) ? 1
7590 : hard_regno_nregs
[out_regno
][mode
]);
7593 spill_reg_store
[regno
] = new_spill_reg_store
[regno
];
7594 spill_reg_stored_to
[regno
] = out
;
7595 reg_last_reload_reg
[out_regno
] = reg
;
7597 piecemeal
= (HARD_REGISTER_NUM_P (out_regno
)
7598 && nregs
== out_nregs
7599 && inherit_piecemeal_p (out_regno
, regno
, mode
));
7601 /* If OUT_REGNO is a hard register, it may occupy more than
7602 one register. If it does, say what is in the
7603 rest of the registers assuming that both registers
7604 agree on how many words the object takes. If not,
7605 invalidate the subsequent registers. */
7607 if (HARD_REGISTER_NUM_P (out_regno
))
7608 for (k
= 1; k
< out_nregs
; k
++)
7609 reg_last_reload_reg
[out_regno
+ k
]
7610 = (piecemeal
? regno_reg_rtx
[regno
+ k
] : 0);
7612 /* Now do the inverse operation. */
7613 for (k
= 0; k
< nregs
; k
++)
7615 CLEAR_HARD_REG_BIT (reg_reloaded_dead
, regno
+ k
);
7616 reg_reloaded_contents
[regno
+ k
]
7617 = (!HARD_REGISTER_NUM_P (out_regno
) || !piecemeal
7620 reg_reloaded_insn
[regno
+ k
] = insn
;
7621 SET_HARD_REG_BIT (reg_reloaded_valid
, regno
+ k
);
7622 if (HARD_REGNO_CALL_PART_CLOBBERED (regno
+ k
, mode
))
7623 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered
,
7626 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered
,
7631 /* Maybe the spill reg contains a copy of reload_in. Only do
7632 something if there will not be an output reload for
7633 the register being reloaded. */
7634 else if (rld
[r
].out_reg
== 0
7636 && ((REG_P (rld
[r
].in
)
7637 && !HARD_REGISTER_P (rld
[r
].in
)
7638 && !REGNO_REG_SET_P (®_has_output_reload
,
7640 || (REG_P (rld
[r
].in_reg
)
7641 && !REGNO_REG_SET_P (®_has_output_reload
,
7642 REGNO (rld
[r
].in_reg
))))
7643 && !reg_set_p (reload_reg_rtx_for_input
[r
], PATTERN (insn
)))
7646 enum machine_mode mode
;
7649 reg
= reload_reg_rtx_for_input
[r
];
7650 mode
= GET_MODE (reg
);
7651 regno
= REGNO (reg
);
7652 nregs
= hard_regno_nregs
[regno
][mode
];
7653 if (reload_regs_reach_end_p (regno
, nregs
, rld
[r
].opnum
,
7654 rld
[r
].when_needed
))
7661 if (REG_P (rld
[r
].in
)
7662 && REGNO (rld
[r
].in
) >= FIRST_PSEUDO_REGISTER
)
7664 else if (REG_P (rld
[r
].in_reg
))
7667 in
= XEXP (rld
[r
].in_reg
, 0);
7668 in_regno
= REGNO (in
);
7670 in_nregs
= (!HARD_REGISTER_NUM_P (in_regno
) ? 1
7671 : hard_regno_nregs
[in_regno
][mode
]);
7673 reg_last_reload_reg
[in_regno
] = reg
;
7675 piecemeal
= (HARD_REGISTER_NUM_P (in_regno
)
7676 && nregs
== in_nregs
7677 && inherit_piecemeal_p (regno
, in_regno
, mode
));
7679 if (HARD_REGISTER_NUM_P (in_regno
))
7680 for (k
= 1; k
< in_nregs
; k
++)
7681 reg_last_reload_reg
[in_regno
+ k
]
7682 = (piecemeal
? regno_reg_rtx
[regno
+ k
] : 0);
7684 /* Unless we inherited this reload, show we haven't
7685 recently done a store.
7686 Previous stores of inherited auto_inc expressions
7687 also have to be discarded. */
7688 if (! reload_inherited
[r
]
7689 || (rld
[r
].out
&& ! rld
[r
].out_reg
))
7690 spill_reg_store
[regno
] = 0;
7692 for (k
= 0; k
< nregs
; k
++)
7694 CLEAR_HARD_REG_BIT (reg_reloaded_dead
, regno
+ k
);
7695 reg_reloaded_contents
[regno
+ k
]
7696 = (!HARD_REGISTER_NUM_P (in_regno
) || !piecemeal
7699 reg_reloaded_insn
[regno
+ k
] = insn
;
7700 SET_HARD_REG_BIT (reg_reloaded_valid
, regno
+ k
);
7701 if (HARD_REGNO_CALL_PART_CLOBBERED (regno
+ k
, mode
))
7702 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered
,
7705 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered
,
7712 /* The following if-statement was #if 0'd in 1.34 (or before...).
7713 It's reenabled in 1.35 because supposedly nothing else
7714 deals with this problem. */
7716 /* If a register gets output-reloaded from a non-spill register,
7717 that invalidates any previous reloaded copy of it.
7718 But forget_old_reloads_1 won't get to see it, because
7719 it thinks only about the original insn. So invalidate it here.
7720 Also do the same thing for RELOAD_OTHER constraints where the
7721 output is discarded. */
7723 && ((rld
[r
].out
!= 0
7724 && (REG_P (rld
[r
].out
)
7725 || (MEM_P (rld
[r
].out
)
7726 && REG_P (rld
[r
].out_reg
))))
7727 || (rld
[r
].out
== 0 && rld
[r
].out_reg
7728 && REG_P (rld
[r
].out_reg
))))
7730 rtx out
= ((rld
[r
].out
&& REG_P (rld
[r
].out
))
7731 ? rld
[r
].out
: rld
[r
].out_reg
);
7732 int out_regno
= REGNO (out
);
7733 enum machine_mode mode
= GET_MODE (out
);
7735 /* REG_RTX is now set or clobbered by the main instruction.
7736 As the comment above explains, forget_old_reloads_1 only
7737 sees the original instruction, and there is no guarantee
7738 that the original instruction also clobbered REG_RTX.
7739 For example, if find_reloads sees that the input side of
7740 a matched operand pair dies in this instruction, it may
7741 use the input register as the reload register.
7743 Calling forget_old_reloads_1 is a waste of effort if
7744 REG_RTX is also the output register.
7746 If we know that REG_RTX holds the value of a pseudo
7747 register, the code after the call will record that fact. */
7748 if (rld
[r
].reg_rtx
&& rld
[r
].reg_rtx
!= out
)
7749 forget_old_reloads_1 (rld
[r
].reg_rtx
, NULL_RTX
, NULL
);
7751 if (!HARD_REGISTER_NUM_P (out_regno
))
7753 rtx src_reg
, store_insn
= NULL_RTX
;
7755 reg_last_reload_reg
[out_regno
] = 0;
7757 /* If we can find a hard register that is stored, record
7758 the storing insn so that we may delete this insn with
7759 delete_output_reload. */
7760 src_reg
= reload_reg_rtx_for_output
[r
];
7762 /* If this is an optional reload, try to find the source reg
7763 from an input reload. */
7766 rtx set
= single_set (insn
);
7767 if (set
&& SET_DEST (set
) == rld
[r
].out
)
7771 src_reg
= SET_SRC (set
);
7773 for (k
= 0; k
< n_reloads
; k
++)
7775 if (rld
[k
].in
== src_reg
)
7777 src_reg
= reload_reg_rtx_for_input
[k
];
7784 store_insn
= new_spill_reg_store
[REGNO (src_reg
)];
7785 if (src_reg
&& REG_P (src_reg
)
7786 && REGNO (src_reg
) < FIRST_PSEUDO_REGISTER
)
7788 int src_regno
, src_nregs
, k
;
7791 gcc_assert (GET_MODE (src_reg
) == mode
);
7792 src_regno
= REGNO (src_reg
);
7793 src_nregs
= hard_regno_nregs
[src_regno
][mode
];
7794 /* The place where to find a death note varies with
7795 PRESERVE_DEATH_INFO_REGNO_P . The condition is not
7796 necessarily checked exactly in the code that moves
7797 notes, so just check both locations. */
7798 note
= find_regno_note (insn
, REG_DEAD
, src_regno
);
7799 if (! note
&& store_insn
)
7800 note
= find_regno_note (store_insn
, REG_DEAD
, src_regno
);
7801 for (k
= 0; k
< src_nregs
; k
++)
7803 spill_reg_store
[src_regno
+ k
] = store_insn
;
7804 spill_reg_stored_to
[src_regno
+ k
] = out
;
7805 reg_reloaded_contents
[src_regno
+ k
] = out_regno
;
7806 reg_reloaded_insn
[src_regno
+ k
] = store_insn
;
7807 CLEAR_HARD_REG_BIT (reg_reloaded_dead
, src_regno
+ k
);
7808 SET_HARD_REG_BIT (reg_reloaded_valid
, src_regno
+ k
);
7809 if (HARD_REGNO_CALL_PART_CLOBBERED (src_regno
+ k
,
7811 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered
,
7814 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered
,
7816 SET_HARD_REG_BIT (reg_is_output_reload
, src_regno
+ k
);
7818 SET_HARD_REG_BIT (reg_reloaded_died
, src_regno
);
7820 CLEAR_HARD_REG_BIT (reg_reloaded_died
, src_regno
);
7822 reg_last_reload_reg
[out_regno
] = src_reg
;
7823 /* We have to set reg_has_output_reload here, or else
7824 forget_old_reloads_1 will clear reg_last_reload_reg
7826 SET_REGNO_REG_SET (®_has_output_reload
,
7832 int k
, out_nregs
= hard_regno_nregs
[out_regno
][mode
];
7834 for (k
= 0; k
< out_nregs
; k
++)
7835 reg_last_reload_reg
[out_regno
+ k
] = 0;
7839 IOR_HARD_REG_SET (reg_reloaded_dead
, reg_reloaded_died
);
7842 /* Go through the motions to emit INSN and test if it is strictly valid.
7843 Return the emitted insn if valid, else return NULL. */
7846 emit_insn_if_valid_for_reload (rtx insn
)
7848 rtx last
= get_last_insn ();
7851 insn
= emit_insn (insn
);
7852 code
= recog_memoized (insn
);
7856 extract_insn (insn
);
7857 /* We want constrain operands to treat this insn strictly in its
7858 validity determination, i.e., the way it would after reload has
7860 if (constrain_operands (1))
7864 delete_insns_since (last
);
7868 /* Emit code to perform a reload from IN (which may be a reload register) to
7869 OUT (which may also be a reload register). IN or OUT is from operand
7870 OPNUM with reload type TYPE.
7872 Returns first insn emitted. */
7875 gen_reload (rtx out
, rtx in
, int opnum
, enum reload_type type
)
7877 rtx last
= get_last_insn ();
7880 /* If IN is a paradoxical SUBREG, remove it and try to put the
7881 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
7882 if (GET_CODE (in
) == SUBREG
7883 && (GET_MODE_SIZE (GET_MODE (in
))
7884 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in
))))
7885 && (tem
= gen_lowpart_common (GET_MODE (SUBREG_REG (in
)), out
)) != 0)
7886 in
= SUBREG_REG (in
), out
= tem
;
7887 else if (GET_CODE (out
) == SUBREG
7888 && (GET_MODE_SIZE (GET_MODE (out
))
7889 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out
))))
7890 && (tem
= gen_lowpart_common (GET_MODE (SUBREG_REG (out
)), in
)) != 0)
7891 out
= SUBREG_REG (out
), in
= tem
;
7893 /* How to do this reload can get quite tricky. Normally, we are being
7894 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
7895 register that didn't get a hard register. In that case we can just
7896 call emit_move_insn.
7898 We can also be asked to reload a PLUS that adds a register or a MEM to
7899 another register, constant or MEM. This can occur during frame pointer
7900 elimination and while reloading addresses. This case is handled by
7901 trying to emit a single insn to perform the add. If it is not valid,
7902 we use a two insn sequence.
7904 Or we can be asked to reload an unary operand that was a fragment of
7905 an addressing mode, into a register. If it isn't recognized as-is,
7906 we try making the unop operand and the reload-register the same:
7907 (set reg:X (unop:X expr:Y))
7908 -> (set reg:Y expr:Y) (set reg:X (unop:X reg:Y)).
7910 Finally, we could be called to handle an 'o' constraint by putting
7911 an address into a register. In that case, we first try to do this
7912 with a named pattern of "reload_load_address". If no such pattern
7913 exists, we just emit a SET insn and hope for the best (it will normally
7914 be valid on machines that use 'o').
7916 This entire process is made complex because reload will never
7917 process the insns we generate here and so we must ensure that
7918 they will fit their constraints and also by the fact that parts of
7919 IN might be being reloaded separately and replaced with spill registers.
7920 Because of this, we are, in some sense, just guessing the right approach
7921 here. The one listed above seems to work.
7923 ??? At some point, this whole thing needs to be rethought. */
7925 if (GET_CODE (in
) == PLUS
7926 && (REG_P (XEXP (in
, 0))
7927 || GET_CODE (XEXP (in
, 0)) == SUBREG
7928 || MEM_P (XEXP (in
, 0)))
7929 && (REG_P (XEXP (in
, 1))
7930 || GET_CODE (XEXP (in
, 1)) == SUBREG
7931 || CONSTANT_P (XEXP (in
, 1))
7932 || MEM_P (XEXP (in
, 1))))
7934 /* We need to compute the sum of a register or a MEM and another
7935 register, constant, or MEM, and put it into the reload
7936 register. The best possible way of doing this is if the machine
7937 has a three-operand ADD insn that accepts the required operands.
7939 The simplest approach is to try to generate such an insn and see if it
7940 is recognized and matches its constraints. If so, it can be used.
7942 It might be better not to actually emit the insn unless it is valid,
7943 but we need to pass the insn as an operand to `recog' and
7944 `extract_insn' and it is simpler to emit and then delete the insn if
7945 not valid than to dummy things up. */
7947 rtx op0
, op1
, tem
, insn
;
7950 op0
= find_replacement (&XEXP (in
, 0));
7951 op1
= find_replacement (&XEXP (in
, 1));
7953 /* Since constraint checking is strict, commutativity won't be
7954 checked, so we need to do that here to avoid spurious failure
7955 if the add instruction is two-address and the second operand
7956 of the add is the same as the reload reg, which is frequently
7957 the case. If the insn would be A = B + A, rearrange it so
7958 it will be A = A + B as constrain_operands expects. */
7960 if (REG_P (XEXP (in
, 1))
7961 && REGNO (out
) == REGNO (XEXP (in
, 1)))
7962 tem
= op0
, op0
= op1
, op1
= tem
;
7964 if (op0
!= XEXP (in
, 0) || op1
!= XEXP (in
, 1))
7965 in
= gen_rtx_PLUS (GET_MODE (in
), op0
, op1
);
7967 insn
= emit_insn_if_valid_for_reload (gen_rtx_SET (VOIDmode
, out
, in
));
7971 /* If that failed, we must use a conservative two-insn sequence.
7973 Use a move to copy one operand into the reload register. Prefer
7974 to reload a constant, MEM or pseudo since the move patterns can
7975 handle an arbitrary operand. If OP1 is not a constant, MEM or
7976 pseudo and OP1 is not a valid operand for an add instruction, then
7979 After reloading one of the operands into the reload register, add
7980 the reload register to the output register.
7982 If there is another way to do this for a specific machine, a
7983 DEFINE_PEEPHOLE should be specified that recognizes the sequence
7986 code
= (int) optab_handler (add_optab
, GET_MODE (out
))->insn_code
;
7988 if (CONSTANT_P (op1
) || MEM_P (op1
) || GET_CODE (op1
) == SUBREG
7990 && REGNO (op1
) >= FIRST_PSEUDO_REGISTER
)
7991 || (code
!= CODE_FOR_nothing
7992 && ! ((*insn_data
[code
].operand
[2].predicate
)
7993 (op1
, insn_data
[code
].operand
[2].mode
))))
7994 tem
= op0
, op0
= op1
, op1
= tem
;
7996 gen_reload (out
, op0
, opnum
, type
);
7998 /* If OP0 and OP1 are the same, we can use OUT for OP1.
7999 This fixes a problem on the 32K where the stack pointer cannot
8000 be used as an operand of an add insn. */
8002 if (rtx_equal_p (op0
, op1
))
8005 insn
= emit_insn_if_valid_for_reload (gen_add2_insn (out
, op1
));
8008 /* Add a REG_EQUIV note so that find_equiv_reg can find it. */
8009 set_unique_reg_note (insn
, REG_EQUIV
, in
);
8013 /* If that failed, copy the address register to the reload register.
8014 Then add the constant to the reload register. */
8016 gcc_assert (!reg_overlap_mentioned_p (out
, op0
));
8017 gen_reload (out
, op1
, opnum
, type
);
8018 insn
= emit_insn (gen_add2_insn (out
, op0
));
8019 set_unique_reg_note (insn
, REG_EQUIV
, in
);
8022 #ifdef SECONDARY_MEMORY_NEEDED
8023 /* If we need a memory location to do the move, do it that way. */
8024 else if ((REG_P (in
) || GET_CODE (in
) == SUBREG
)
8025 && reg_or_subregno (in
) < FIRST_PSEUDO_REGISTER
8026 && (REG_P (out
) || GET_CODE (out
) == SUBREG
)
8027 && reg_or_subregno (out
) < FIRST_PSEUDO_REGISTER
8028 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (reg_or_subregno (in
)),
8029 REGNO_REG_CLASS (reg_or_subregno (out
)),
8032 /* Get the memory to use and rewrite both registers to its mode. */
8033 rtx loc
= get_secondary_mem (in
, GET_MODE (out
), opnum
, type
);
8035 if (GET_MODE (loc
) != GET_MODE (out
))
8036 out
= gen_rtx_REG (GET_MODE (loc
), REGNO (out
));
8038 if (GET_MODE (loc
) != GET_MODE (in
))
8039 in
= gen_rtx_REG (GET_MODE (loc
), REGNO (in
));
8041 gen_reload (loc
, in
, opnum
, type
);
8042 gen_reload (out
, loc
, opnum
, type
);
8045 else if (REG_P (out
) && UNARY_P (in
))
8052 op1
= find_replacement (&XEXP (in
, 0));
8053 if (op1
!= XEXP (in
, 0))
8054 in
= gen_rtx_fmt_e (GET_CODE (in
), GET_MODE (in
), op1
);
8056 /* First, try a plain SET. */
8057 set
= emit_insn_if_valid_for_reload (gen_rtx_SET (VOIDmode
, out
, in
));
8061 /* If that failed, move the inner operand to the reload
8062 register, and try the same unop with the inner expression
8063 replaced with the reload register. */
8065 if (GET_MODE (op1
) != GET_MODE (out
))
8066 out_moded
= gen_rtx_REG (GET_MODE (op1
), REGNO (out
));
8070 gen_reload (out_moded
, op1
, opnum
, type
);
8073 = gen_rtx_SET (VOIDmode
, out
,
8074 gen_rtx_fmt_e (GET_CODE (in
), GET_MODE (in
),
8076 insn
= emit_insn_if_valid_for_reload (insn
);
8079 set_unique_reg_note (insn
, REG_EQUIV
, in
);
8083 fatal_insn ("Failure trying to reload:", set
);
8085 /* If IN is a simple operand, use gen_move_insn. */
8086 else if (OBJECT_P (in
) || GET_CODE (in
) == SUBREG
)
8088 tem
= emit_insn (gen_move_insn (out
, in
));
8089 /* IN may contain a LABEL_REF, if so add a REG_LABEL_OPERAND note. */
8090 mark_jump_label (in
, tem
, 0);
8093 #ifdef HAVE_reload_load_address
8094 else if (HAVE_reload_load_address
)
8095 emit_insn (gen_reload_load_address (out
, in
));
8098 /* Otherwise, just write (set OUT IN) and hope for the best. */
8100 emit_insn (gen_rtx_SET (VOIDmode
, out
, in
));
8102 /* Return the first insn emitted.
8103 We can not just return get_last_insn, because there may have
8104 been multiple instructions emitted. Also note that gen_move_insn may
8105 emit more than one insn itself, so we can not assume that there is one
8106 insn emitted per emit_insn_before call. */
8108 return last
? NEXT_INSN (last
) : get_insns ();
8111 /* Delete a previously made output-reload whose result we now believe
8112 is not needed. First we double-check.
8114 INSN is the insn now being processed.
8115 LAST_RELOAD_REG is the hard register number for which we want to delete
8116 the last output reload.
8117 J is the reload-number that originally used REG. The caller has made
8118 certain that reload J doesn't use REG any longer for input.
8119 NEW_RELOAD_REG is reload register that reload J is using for REG. */
8122 delete_output_reload (rtx insn
, int j
, int last_reload_reg
, rtx new_reload_reg
)
8124 rtx output_reload_insn
= spill_reg_store
[last_reload_reg
];
8125 rtx reg
= spill_reg_stored_to
[last_reload_reg
];
8128 int n_inherited
= 0;
8132 /* It is possible that this reload has been only used to set another reload
8133 we eliminated earlier and thus deleted this instruction too. */
8134 if (INSN_DELETED_P (output_reload_insn
))
8137 /* Get the raw pseudo-register referred to. */
8139 while (GET_CODE (reg
) == SUBREG
)
8140 reg
= SUBREG_REG (reg
);
8141 substed
= reg_equiv_memory_loc
[REGNO (reg
)];
8143 /* This is unsafe if the operand occurs more often in the current
8144 insn than it is inherited. */
8145 for (k
= n_reloads
- 1; k
>= 0; k
--)
8147 rtx reg2
= rld
[k
].in
;
8150 if (MEM_P (reg2
) || reload_override_in
[k
])
8151 reg2
= rld
[k
].in_reg
;
8153 if (rld
[k
].out
&& ! rld
[k
].out_reg
)
8154 reg2
= XEXP (rld
[k
].in_reg
, 0);
8156 while (GET_CODE (reg2
) == SUBREG
)
8157 reg2
= SUBREG_REG (reg2
);
8158 if (rtx_equal_p (reg2
, reg
))
8160 if (reload_inherited
[k
] || reload_override_in
[k
] || k
== j
)
8166 n_occurrences
= count_occurrences (PATTERN (insn
), reg
, 0);
8167 if (CALL_P (insn
) && CALL_INSN_FUNCTION_USAGE (insn
))
8168 n_occurrences
+= count_occurrences (CALL_INSN_FUNCTION_USAGE (insn
),
8171 n_occurrences
+= count_occurrences (PATTERN (insn
),
8172 eliminate_regs (substed
, 0,
8174 for (i1
= reg_equiv_alt_mem_list
[REGNO (reg
)]; i1
; i1
= XEXP (i1
, 1))
8176 gcc_assert (!rtx_equal_p (XEXP (i1
, 0), substed
));
8177 n_occurrences
+= count_occurrences (PATTERN (insn
), XEXP (i1
, 0), 0);
8179 if (n_occurrences
> n_inherited
)
8182 /* If the pseudo-reg we are reloading is no longer referenced
8183 anywhere between the store into it and here,
8184 and we're within the same basic block, then the value can only
8185 pass through the reload reg and end up here.
8186 Otherwise, give up--return. */
8187 for (i1
= NEXT_INSN (output_reload_insn
);
8188 i1
!= insn
; i1
= NEXT_INSN (i1
))
8190 if (NOTE_INSN_BASIC_BLOCK_P (i1
))
8192 if ((NONJUMP_INSN_P (i1
) || CALL_P (i1
))
8193 && reg_mentioned_p (reg
, PATTERN (i1
)))
8195 /* If this is USE in front of INSN, we only have to check that
8196 there are no more references than accounted for by inheritance. */
8197 while (NONJUMP_INSN_P (i1
) && GET_CODE (PATTERN (i1
)) == USE
)
8199 n_occurrences
+= rtx_equal_p (reg
, XEXP (PATTERN (i1
), 0)) != 0;
8200 i1
= NEXT_INSN (i1
);
8202 if (n_occurrences
<= n_inherited
&& i1
== insn
)
8208 /* We will be deleting the insn. Remove the spill reg information. */
8209 for (k
= hard_regno_nregs
[last_reload_reg
][GET_MODE (reg
)]; k
-- > 0; )
8211 spill_reg_store
[last_reload_reg
+ k
] = 0;
8212 spill_reg_stored_to
[last_reload_reg
+ k
] = 0;
8215 /* The caller has already checked that REG dies or is set in INSN.
8216 It has also checked that we are optimizing, and thus some
8217 inaccuracies in the debugging information are acceptable.
8218 So we could just delete output_reload_insn. But in some cases
8219 we can improve the debugging information without sacrificing
8220 optimization - maybe even improving the code: See if the pseudo
8221 reg has been completely replaced with reload regs. If so, delete
8222 the store insn and forget we had a stack slot for the pseudo. */
8223 if (rld
[j
].out
!= rld
[j
].in
8224 && REG_N_DEATHS (REGNO (reg
)) == 1
8225 && REG_N_SETS (REGNO (reg
)) == 1
8226 && REG_BASIC_BLOCK (REGNO (reg
)) >= NUM_FIXED_BLOCKS
8227 && find_regno_note (insn
, REG_DEAD
, REGNO (reg
)))
8231 /* We know that it was used only between here and the beginning of
8232 the current basic block. (We also know that the last use before
8233 INSN was the output reload we are thinking of deleting, but never
8234 mind that.) Search that range; see if any ref remains. */
8235 for (i2
= PREV_INSN (insn
); i2
; i2
= PREV_INSN (i2
))
8237 rtx set
= single_set (i2
);
8239 /* Uses which just store in the pseudo don't count,
8240 since if they are the only uses, they are dead. */
8241 if (set
!= 0 && SET_DEST (set
) == reg
)
8246 if ((NONJUMP_INSN_P (i2
) || CALL_P (i2
))
8247 && reg_mentioned_p (reg
, PATTERN (i2
)))
8249 /* Some other ref remains; just delete the output reload we
8251 delete_address_reloads (output_reload_insn
, insn
);
8252 delete_insn (output_reload_insn
);
8257 /* Delete the now-dead stores into this pseudo. Note that this
8258 loop also takes care of deleting output_reload_insn. */
8259 for (i2
= PREV_INSN (insn
); i2
; i2
= PREV_INSN (i2
))
8261 rtx set
= single_set (i2
);
8263 if (set
!= 0 && SET_DEST (set
) == reg
)
8265 delete_address_reloads (i2
, insn
);
8273 /* For the debugging info, say the pseudo lives in this reload reg. */
8274 reg_renumber
[REGNO (reg
)] = REGNO (new_reload_reg
);
8275 alter_reg (REGNO (reg
), -1);
8279 delete_address_reloads (output_reload_insn
, insn
);
8280 delete_insn (output_reload_insn
);
8284 /* We are going to delete DEAD_INSN. Recursively delete loads of
8285 reload registers used in DEAD_INSN that are not used till CURRENT_INSN.
8286 CURRENT_INSN is being reloaded, so we have to check its reloads too. */
8288 delete_address_reloads (rtx dead_insn
, rtx current_insn
)
8290 rtx set
= single_set (dead_insn
);
8291 rtx set2
, dst
, prev
, next
;
8294 rtx dst
= SET_DEST (set
);
8296 delete_address_reloads_1 (dead_insn
, XEXP (dst
, 0), current_insn
);
8298 /* If we deleted the store from a reloaded post_{in,de}c expression,
8299 we can delete the matching adds. */
8300 prev
= PREV_INSN (dead_insn
);
8301 next
= NEXT_INSN (dead_insn
);
8302 if (! prev
|| ! next
)
8304 set
= single_set (next
);
8305 set2
= single_set (prev
);
8307 || GET_CODE (SET_SRC (set
)) != PLUS
|| GET_CODE (SET_SRC (set2
)) != PLUS
8308 || GET_CODE (XEXP (SET_SRC (set
), 1)) != CONST_INT
8309 || GET_CODE (XEXP (SET_SRC (set2
), 1)) != CONST_INT
)
8311 dst
= SET_DEST (set
);
8312 if (! rtx_equal_p (dst
, SET_DEST (set2
))
8313 || ! rtx_equal_p (dst
, XEXP (SET_SRC (set
), 0))
8314 || ! rtx_equal_p (dst
, XEXP (SET_SRC (set2
), 0))
8315 || (INTVAL (XEXP (SET_SRC (set
), 1))
8316 != -INTVAL (XEXP (SET_SRC (set2
), 1))))
8318 delete_related_insns (prev
);
8319 delete_related_insns (next
);
8322 /* Subfunction of delete_address_reloads: process registers found in X. */
8324 delete_address_reloads_1 (rtx dead_insn
, rtx x
, rtx current_insn
)
8326 rtx prev
, set
, dst
, i2
;
8328 enum rtx_code code
= GET_CODE (x
);
8332 const char *fmt
= GET_RTX_FORMAT (code
);
8333 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
8336 delete_address_reloads_1 (dead_insn
, XEXP (x
, i
), current_insn
);
8337 else if (fmt
[i
] == 'E')
8339 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
8340 delete_address_reloads_1 (dead_insn
, XVECEXP (x
, i
, j
),
8347 if (spill_reg_order
[REGNO (x
)] < 0)
8350 /* Scan backwards for the insn that sets x. This might be a way back due
8352 for (prev
= PREV_INSN (dead_insn
); prev
; prev
= PREV_INSN (prev
))
8354 code
= GET_CODE (prev
);
8355 if (code
== CODE_LABEL
|| code
== JUMP_INSN
)
8359 if (reg_set_p (x
, PATTERN (prev
)))
8361 if (reg_referenced_p (x
, PATTERN (prev
)))
8364 if (! prev
|| INSN_UID (prev
) < reload_first_uid
)
8366 /* Check that PREV only sets the reload register. */
8367 set
= single_set (prev
);
8370 dst
= SET_DEST (set
);
8372 || ! rtx_equal_p (dst
, x
))
8374 if (! reg_set_p (dst
, PATTERN (dead_insn
)))
8376 /* Check if DST was used in a later insn -
8377 it might have been inherited. */
8378 for (i2
= NEXT_INSN (dead_insn
); i2
; i2
= NEXT_INSN (i2
))
8384 if (reg_referenced_p (dst
, PATTERN (i2
)))
8386 /* If there is a reference to the register in the current insn,
8387 it might be loaded in a non-inherited reload. If no other
8388 reload uses it, that means the register is set before
8390 if (i2
== current_insn
)
8392 for (j
= n_reloads
- 1; j
>= 0; j
--)
8393 if ((rld
[j
].reg_rtx
== dst
&& reload_inherited
[j
])
8394 || reload_override_in
[j
] == dst
)
8396 for (j
= n_reloads
- 1; j
>= 0; j
--)
8397 if (rld
[j
].in
&& rld
[j
].reg_rtx
== dst
)
8406 /* If DST is still live at CURRENT_INSN, check if it is used for
8407 any reload. Note that even if CURRENT_INSN sets DST, we still
8408 have to check the reloads. */
8409 if (i2
== current_insn
)
8411 for (j
= n_reloads
- 1; j
>= 0; j
--)
8412 if ((rld
[j
].reg_rtx
== dst
&& reload_inherited
[j
])
8413 || reload_override_in
[j
] == dst
)
8415 /* ??? We can't finish the loop here, because dst might be
8416 allocated to a pseudo in this block if no reload in this
8417 block needs any of the classes containing DST - see
8418 spill_hard_reg. There is no easy way to tell this, so we
8419 have to scan till the end of the basic block. */
8421 if (reg_set_p (dst
, PATTERN (i2
)))
8425 delete_address_reloads_1 (prev
, SET_SRC (set
), current_insn
);
8426 reg_reloaded_contents
[REGNO (dst
)] = -1;
8430 /* Output reload-insns to reload VALUE into RELOADREG.
8431 VALUE is an autoincrement or autodecrement RTX whose operand
8432 is a register or memory location;
8433 so reloading involves incrementing that location.
8434 IN is either identical to VALUE, or some cheaper place to reload from.
8436 INC_AMOUNT is the number to increment or decrement by (always positive).
8437 This cannot be deduced from VALUE.
8439 Return the instruction that stores into RELOADREG. */
8442 inc_for_reload (rtx reloadreg
, rtx in
, rtx value
, int inc_amount
)
8444 /* REG or MEM to be copied and incremented. */
8445 rtx incloc
= find_replacement (&XEXP (value
, 0));
8446 /* Nonzero if increment after copying. */
8447 int post
= (GET_CODE (value
) == POST_DEC
|| GET_CODE (value
) == POST_INC
8448 || GET_CODE (value
) == POST_MODIFY
);
8454 rtx real_in
= in
== value
? incloc
: in
;
8456 /* No hard register is equivalent to this register after
8457 inc/dec operation. If REG_LAST_RELOAD_REG were nonzero,
8458 we could inc/dec that register as well (maybe even using it for
8459 the source), but I'm not sure it's worth worrying about. */
8461 reg_last_reload_reg
[REGNO (incloc
)] = 0;
8463 if (GET_CODE (value
) == PRE_MODIFY
|| GET_CODE (value
) == POST_MODIFY
)
8465 gcc_assert (GET_CODE (XEXP (value
, 1)) == PLUS
);
8466 inc
= find_replacement (&XEXP (XEXP (value
, 1), 1));
8470 if (GET_CODE (value
) == PRE_DEC
|| GET_CODE (value
) == POST_DEC
)
8471 inc_amount
= -inc_amount
;
8473 inc
= GEN_INT (inc_amount
);
8476 /* If this is post-increment, first copy the location to the reload reg. */
8477 if (post
&& real_in
!= reloadreg
)
8478 emit_insn (gen_move_insn (reloadreg
, real_in
));
8482 /* See if we can directly increment INCLOC. Use a method similar to
8483 that in gen_reload. */
8485 last
= get_last_insn ();
8486 add_insn
= emit_insn (gen_rtx_SET (VOIDmode
, incloc
,
8487 gen_rtx_PLUS (GET_MODE (incloc
),
8490 code
= recog_memoized (add_insn
);
8493 extract_insn (add_insn
);
8494 if (constrain_operands (1))
8496 /* If this is a pre-increment and we have incremented the value
8497 where it lives, copy the incremented value to RELOADREG to
8498 be used as an address. */
8501 emit_insn (gen_move_insn (reloadreg
, incloc
));
8506 delete_insns_since (last
);
8509 /* If couldn't do the increment directly, must increment in RELOADREG.
8510 The way we do this depends on whether this is pre- or post-increment.
8511 For pre-increment, copy INCLOC to the reload register, increment it
8512 there, then save back. */
8516 if (in
!= reloadreg
)
8517 emit_insn (gen_move_insn (reloadreg
, real_in
));
8518 emit_insn (gen_add2_insn (reloadreg
, inc
));
8519 store
= emit_insn (gen_move_insn (incloc
, reloadreg
));
8524 Because this might be a jump insn or a compare, and because RELOADREG
8525 may not be available after the insn in an input reload, we must do
8526 the incrementation before the insn being reloaded for.
8528 We have already copied IN to RELOADREG. Increment the copy in
8529 RELOADREG, save that back, then decrement RELOADREG so it has
8530 the original value. */
8532 emit_insn (gen_add2_insn (reloadreg
, inc
));
8533 store
= emit_insn (gen_move_insn (incloc
, reloadreg
));
8534 if (GET_CODE (inc
) == CONST_INT
)
8535 emit_insn (gen_add2_insn (reloadreg
, GEN_INT (-INTVAL (inc
))));
8537 emit_insn (gen_sub2_insn (reloadreg
, inc
));
8545 add_auto_inc_notes (rtx insn
, rtx x
)
8547 enum rtx_code code
= GET_CODE (x
);
8551 if (code
== MEM
&& auto_inc_p (XEXP (x
, 0)))
8554 = gen_rtx_EXPR_LIST (REG_INC
, XEXP (XEXP (x
, 0), 0), REG_NOTES (insn
));
8558 /* Scan all the operand sub-expressions. */
8559 fmt
= GET_RTX_FORMAT (code
);
8560 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
8563 add_auto_inc_notes (insn
, XEXP (x
, i
));
8564 else if (fmt
[i
] == 'E')
8565 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
8566 add_auto_inc_notes (insn
, XVECEXP (x
, i
, j
));
8571 /* Copy EH notes from an insn to its reloads. */
8573 copy_eh_notes (rtx insn
, rtx x
)
8575 rtx eh_note
= find_reg_note (insn
, REG_EH_REGION
, NULL_RTX
);
8578 for (; x
!= 0; x
= NEXT_INSN (x
))
8580 if (may_trap_p (PATTERN (x
)))
8582 = gen_rtx_EXPR_LIST (REG_EH_REGION
, XEXP (eh_note
, 0),
8588 /* This is used by reload pass, that does emit some instructions after
8589 abnormal calls moving basic block end, but in fact it wants to emit
8590 them on the edge. Looks for abnormal call edges, find backward the
8591 proper call and fix the damage.
8593 Similar handle instructions throwing exceptions internally. */
8595 fixup_abnormal_edges (void)
8597 bool inserted
= false;
8605 /* Look for cases we are interested in - calls or instructions causing
8607 FOR_EACH_EDGE (e
, ei
, bb
->succs
)
8609 if (e
->flags
& EDGE_ABNORMAL_CALL
)
8611 if ((e
->flags
& (EDGE_ABNORMAL
| EDGE_EH
))
8612 == (EDGE_ABNORMAL
| EDGE_EH
))
8615 if (e
&& !CALL_P (BB_END (bb
))
8616 && !can_throw_internal (BB_END (bb
)))
8620 /* Get past the new insns generated. Allow notes, as the insns
8621 may be already deleted. */
8623 while ((NONJUMP_INSN_P (insn
) || NOTE_P (insn
))
8624 && !can_throw_internal (insn
)
8625 && insn
!= BB_HEAD (bb
))
8626 insn
= PREV_INSN (insn
);
8628 if (CALL_P (insn
) || can_throw_internal (insn
))
8632 stop
= NEXT_INSN (BB_END (bb
));
8634 insn
= NEXT_INSN (insn
);
8636 FOR_EACH_EDGE (e
, ei
, bb
->succs
)
8637 if (e
->flags
& EDGE_FALLTHRU
)
8640 while (insn
&& insn
!= stop
)
8642 next
= NEXT_INSN (insn
);
8647 /* Sometimes there's still the return value USE.
8648 If it's placed after a trapping call (i.e. that
8649 call is the last insn anyway), we have no fallthru
8650 edge. Simply delete this use and don't try to insert
8651 on the non-existent edge. */
8652 if (GET_CODE (PATTERN (insn
)) != USE
)
8654 /* We're not deleting it, we're moving it. */
8655 INSN_DELETED_P (insn
) = 0;
8656 PREV_INSN (insn
) = NULL_RTX
;
8657 NEXT_INSN (insn
) = NULL_RTX
;
8659 insert_insn_on_edge (insn
, e
);
8663 else if (!BARRIER_P (insn
))
8664 set_block_for_insn (insn
, NULL
);
8669 /* It may be that we don't find any such trapping insn. In this
8670 case we discovered quite late that the insn that had been
8671 marked as can_throw_internal in fact couldn't trap at all.
8672 So we should in fact delete the EH edges out of the block. */
8674 purge_dead_edges (bb
);
8678 /* We've possibly turned single trapping insn into multiple ones. */
8679 if (flag_non_call_exceptions
)
8682 blocks
= sbitmap_alloc (last_basic_block
);
8683 sbitmap_ones (blocks
);
8684 find_many_sub_basic_blocks (blocks
);
8685 sbitmap_free (blocks
);
8689 commit_edge_insertions ();
8691 #ifdef ENABLE_CHECKING
8692 /* Verify that we didn't turn one trapping insn into many, and that
8693 we found and corrected all of the problems wrt fixups on the
8695 verify_flow_info ();