1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
24 #include "coretypes.h"
28 #include "hard-reg-set.h"
32 #include "insn-config.h"
38 #include "basic-block.h"
47 /* This file contains the reload pass of the compiler, which is
48 run after register allocation has been done. It checks that
49 each insn is valid (operands required to be in registers really
50 are in registers of the proper class) and fixes up invalid ones
51 by copying values temporarily into registers for the insns
54 The results of register allocation are described by the vector
55 reg_renumber; the insns still contain pseudo regs, but reg_renumber
56 can be used to find which hard reg, if any, a pseudo reg is in.
58 The technique we always use is to free up a few hard regs that are
59 called ``reload regs'', and for each place where a pseudo reg
60 must be in a hard reg, copy it temporarily into one of the reload regs.
62 Reload regs are allocated locally for every instruction that needs
63 reloads. When there are pseudos which are allocated to a register that
64 has been chosen as a reload reg, such pseudos must be ``spilled''.
65 This means that they go to other hard regs, or to stack slots if no other
66 available hard regs can be found. Spilling can invalidate more
67 insns, requiring additional need for reloads, so we must keep checking
68 until the process stabilizes.
70 For machines with different classes of registers, we must keep track
71 of the register class needed for each reload, and make sure that
72 we allocate enough reload registers of each class.
74 The file reload.c contains the code that checks one insn for
75 validity and reports the reloads that it needs. This file
76 is in charge of scanning the entire rtl code, accumulating the
77 reload needs, spilling, assigning reload registers to use for
78 fixing up each insn, and generating the new insns to copy values
79 into the reload registers. */
82 #define LOCAL_REGNO(REGNO) 0
85 /* During reload_as_needed, element N contains a REG rtx for the hard reg
86 into which reg N has been reloaded (perhaps for a previous insn). */
87 static rtx
*reg_last_reload_reg
;
89 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
90 for an output reload that stores into reg N. */
91 static char *reg_has_output_reload
;
93 /* Indicates which hard regs are reload-registers for an output reload
94 in the current insn. */
95 static HARD_REG_SET reg_is_output_reload
;
97 /* Element N is the constant value to which pseudo reg N is equivalent,
98 or zero if pseudo reg N is not equivalent to a constant.
99 find_reloads looks at this in order to replace pseudo reg N
100 with the constant it stands for. */
101 rtx
*reg_equiv_constant
;
103 /* Element N is a memory location to which pseudo reg N is equivalent,
104 prior to any register elimination (such as frame pointer to stack
105 pointer). Depending on whether or not it is a valid address, this value
106 is transferred to either reg_equiv_address or reg_equiv_mem. */
107 rtx
*reg_equiv_memory_loc
;
109 /* Element N is the address of stack slot to which pseudo reg N is equivalent.
110 This is used when the address is not valid as a memory address
111 (because its displacement is too big for the machine.) */
112 rtx
*reg_equiv_address
;
114 /* Element N is the memory slot to which pseudo reg N is equivalent,
115 or zero if pseudo reg N is not equivalent to a memory slot. */
118 /* Widest width in which each pseudo reg is referred to (via subreg). */
119 static unsigned int *reg_max_ref_width
;
121 /* Element N is the list of insns that initialized reg N from its equivalent
122 constant or memory slot. */
123 static rtx
*reg_equiv_init
;
125 /* Vector to remember old contents of reg_renumber before spilling. */
126 static short *reg_old_renumber
;
128 /* During reload_as_needed, element N contains the last pseudo regno reloaded
129 into hard register N. If that pseudo reg occupied more than one register,
130 reg_reloaded_contents points to that pseudo for each spill register in
131 use; all of these must remain set for an inheritance to occur. */
132 static int reg_reloaded_contents
[FIRST_PSEUDO_REGISTER
];
134 /* During reload_as_needed, element N contains the insn for which
135 hard register N was last used. Its contents are significant only
136 when reg_reloaded_valid is set for this register. */
137 static rtx reg_reloaded_insn
[FIRST_PSEUDO_REGISTER
];
139 /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid. */
140 static HARD_REG_SET reg_reloaded_valid
;
141 /* Indicate if the register was dead at the end of the reload.
142 This is only valid if reg_reloaded_contents is set and valid. */
143 static HARD_REG_SET reg_reloaded_dead
;
145 /* Number of spill-regs so far; number of valid elements of spill_regs. */
148 /* In parallel with spill_regs, contains REG rtx's for those regs.
149 Holds the last rtx used for any given reg, or 0 if it has never
150 been used for spilling yet. This rtx is reused, provided it has
152 static rtx spill_reg_rtx
[FIRST_PSEUDO_REGISTER
];
154 /* In parallel with spill_regs, contains nonzero for a spill reg
155 that was stored after the last time it was used.
156 The precise value is the insn generated to do the store. */
157 static rtx spill_reg_store
[FIRST_PSEUDO_REGISTER
];
159 /* This is the register that was stored with spill_reg_store. This is a
160 copy of reload_out / reload_out_reg when the value was stored; if
161 reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */
162 static rtx spill_reg_stored_to
[FIRST_PSEUDO_REGISTER
];
164 /* This table is the inverse mapping of spill_regs:
165 indexed by hard reg number,
166 it contains the position of that reg in spill_regs,
167 or -1 for something that is not in spill_regs.
169 ?!? This is no longer accurate. */
170 static short spill_reg_order
[FIRST_PSEUDO_REGISTER
];
172 /* This reg set indicates registers that can't be used as spill registers for
173 the currently processed insn. These are the hard registers which are live
174 during the insn, but not allocated to pseudos, as well as fixed
176 static HARD_REG_SET bad_spill_regs
;
178 /* These are the hard registers that can't be used as spill register for any
179 insn. This includes registers used for user variables and registers that
180 we can't eliminate. A register that appears in this set also can't be used
181 to retry register allocation. */
182 static HARD_REG_SET bad_spill_regs_global
;
184 /* Describes order of use of registers for reloading
185 of spilled pseudo-registers. `n_spills' is the number of
186 elements that are actually valid; new ones are added at the end.
188 Both spill_regs and spill_reg_order are used on two occasions:
189 once during find_reload_regs, where they keep track of the spill registers
190 for a single insn, but also during reload_as_needed where they show all
191 the registers ever used by reload. For the latter case, the information
192 is calculated during finish_spills. */
193 static short spill_regs
[FIRST_PSEUDO_REGISTER
];
195 /* This vector of reg sets indicates, for each pseudo, which hard registers
196 may not be used for retrying global allocation because the register was
197 formerly spilled from one of them. If we allowed reallocating a pseudo to
198 a register that it was already allocated to, reload might not
200 static HARD_REG_SET
*pseudo_previous_regs
;
202 /* This vector of reg sets indicates, for each pseudo, which hard
203 registers may not be used for retrying global allocation because they
204 are used as spill registers during one of the insns in which the
206 static HARD_REG_SET
*pseudo_forbidden_regs
;
208 /* All hard regs that have been used as spill registers for any insn are
209 marked in this set. */
210 static HARD_REG_SET used_spill_regs
;
212 /* Index of last register assigned as a spill register. We allocate in
213 a round-robin fashion. */
214 static int last_spill_reg
;
216 /* Nonzero if indirect addressing is supported on the machine; this means
217 that spilling (REG n) does not require reloading it into a register in
218 order to do (MEM (REG n)) or (MEM (PLUS (REG n) (CONST_INT c))). The
219 value indicates the level of indirect addressing supported, e.g., two
220 means that (MEM (MEM (REG n))) is also valid if (REG n) does not get
222 static char spill_indirect_levels
;
224 /* Nonzero if indirect addressing is supported when the innermost MEM is
225 of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to
226 which these are valid is the same as spill_indirect_levels, above. */
227 char indirect_symref_ok
;
229 /* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */
230 char double_reg_address_ok
;
232 /* Record the stack slot for each spilled hard register. */
233 static rtx spill_stack_slot
[FIRST_PSEUDO_REGISTER
];
235 /* Width allocated so far for that stack slot. */
236 static unsigned int spill_stack_slot_width
[FIRST_PSEUDO_REGISTER
];
238 /* Record which pseudos needed to be spilled. */
239 static regset_head spilled_pseudos
;
241 /* Used for communication between order_regs_for_reload and count_pseudo.
242 Used to avoid counting one pseudo twice. */
243 static regset_head pseudos_counted
;
245 /* First uid used by insns created by reload in this function.
246 Used in find_equiv_reg. */
247 int reload_first_uid
;
249 /* Flag set by local-alloc or global-alloc if anything is live in
250 a call-clobbered reg across calls. */
251 int caller_save_needed
;
253 /* Set to 1 while reload_as_needed is operating.
254 Required by some machines to handle any generated moves differently. */
255 int reload_in_progress
= 0;
257 /* These arrays record the insn_code of insns that may be needed to
258 perform input and output reloads of special objects. They provide a
259 place to pass a scratch register. */
260 enum insn_code reload_in_optab
[NUM_MACHINE_MODES
];
261 enum insn_code reload_out_optab
[NUM_MACHINE_MODES
];
263 /* This obstack is used for allocation of rtl during register elimination.
264 The allocated storage can be freed once find_reloads has processed the
266 struct obstack reload_obstack
;
268 /* Points to the beginning of the reload_obstack. All insn_chain structures
269 are allocated first. */
270 char *reload_startobj
;
272 /* The point after all insn_chain structures. Used to quickly deallocate
273 memory allocated in copy_reloads during calculate_needs_all_insns. */
274 char *reload_firstobj
;
276 /* This points before all local rtl generated by register elimination.
277 Used to quickly free all memory after processing one insn. */
278 static char *reload_insn_firstobj
;
280 /* List of insn_chain instructions, one for every insn that reload needs to
282 struct insn_chain
*reload_insn_chain
;
284 /* List of all insns needing reloads. */
285 static struct insn_chain
*insns_need_reload
;
287 /* This structure is used to record information about register eliminations.
288 Each array entry describes one possible way of eliminating a register
289 in favor of another. If there is more than one way of eliminating a
290 particular register, the most preferred should be specified first. */
294 int from
; /* Register number to be eliminated. */
295 int to
; /* Register number used as replacement. */
296 HOST_WIDE_INT initial_offset
; /* Initial difference between values. */
297 int can_eliminate
; /* Nonzero if this elimination can be done. */
298 int can_eliminate_previous
; /* Value of CAN_ELIMINATE in previous scan over
299 insns made by reload. */
300 HOST_WIDE_INT offset
; /* Current offset between the two regs. */
301 HOST_WIDE_INT previous_offset
;/* Offset at end of previous insn. */
302 int ref_outside_mem
; /* "to" has been referenced outside a MEM. */
303 rtx from_rtx
; /* REG rtx for the register to be eliminated.
304 We cannot simply compare the number since
305 we might then spuriously replace a hard
306 register corresponding to a pseudo
307 assigned to the reg to be eliminated. */
308 rtx to_rtx
; /* REG rtx for the replacement. */
311 static struct elim_table
*reg_eliminate
= 0;
313 /* This is an intermediate structure to initialize the table. It has
314 exactly the members provided by ELIMINABLE_REGS. */
315 static const struct elim_table_1
319 } reg_eliminate_1
[] =
321 /* If a set of eliminable registers was specified, define the table from it.
322 Otherwise, default to the normal case of the frame pointer being
323 replaced by the stack pointer. */
325 #ifdef ELIMINABLE_REGS
328 {{ FRAME_POINTER_REGNUM
, STACK_POINTER_REGNUM
}};
331 #define NUM_ELIMINABLE_REGS ARRAY_SIZE (reg_eliminate_1)
333 /* Record the number of pending eliminations that have an offset not equal
334 to their initial offset. If nonzero, we use a new copy of each
335 replacement result in any insns encountered. */
336 int num_not_at_initial_offset
;
338 /* Count the number of registers that we may be able to eliminate. */
339 static int num_eliminable
;
340 /* And the number of registers that are equivalent to a constant that
341 can be eliminated to frame_pointer / arg_pointer + constant. */
342 static int num_eliminable_invariants
;
344 /* For each label, we record the offset of each elimination. If we reach
345 a label by more than one path and an offset differs, we cannot do the
346 elimination. This information is indexed by the difference of the
347 number of the label and the first label number. We can't offset the
348 pointer itself as this can cause problems on machines with segmented
349 memory. The first table is an array of flags that records whether we
350 have yet encountered a label and the second table is an array of arrays,
351 one entry in the latter array for each elimination. */
353 static int first_label_num
;
354 static char *offsets_known_at
;
355 static HOST_WIDE_INT (*offsets_at
)[NUM_ELIMINABLE_REGS
];
357 /* Number of labels in the current function. */
359 static int num_labels
;
361 static void replace_pseudos_in (rtx
*, enum machine_mode
, rtx
);
362 static void maybe_fix_stack_asms (void);
363 static void copy_reloads (struct insn_chain
*);
364 static void calculate_needs_all_insns (int);
365 static int find_reg (struct insn_chain
*, int);
366 static void find_reload_regs (struct insn_chain
*);
367 static void select_reload_regs (void);
368 static void delete_caller_save_insns (void);
370 static void spill_failure (rtx
, enum reg_class
);
371 static void count_spilled_pseudo (int, int, int);
372 static void delete_dead_insn (rtx
);
373 static void alter_reg (int, int);
374 static void set_label_offsets (rtx
, rtx
, int);
375 static void check_eliminable_occurrences (rtx
);
376 static void elimination_effects (rtx
, enum machine_mode
);
377 static int eliminate_regs_in_insn (rtx
, int);
378 static void update_eliminable_offsets (void);
379 static void mark_not_eliminable (rtx
, rtx
, void *);
380 static void set_initial_elim_offsets (void);
381 static void verify_initial_elim_offsets (void);
382 static void set_initial_label_offsets (void);
383 static void set_offsets_for_label (rtx
);
384 static void init_elim_table (void);
385 static void update_eliminables (HARD_REG_SET
*);
386 static void spill_hard_reg (unsigned int, int);
387 static int finish_spills (int);
388 static void ior_hard_reg_set (HARD_REG_SET
*, HARD_REG_SET
*);
389 static void scan_paradoxical_subregs (rtx
);
390 static void count_pseudo (int);
391 static void order_regs_for_reload (struct insn_chain
*);
392 static void reload_as_needed (int);
393 static void forget_old_reloads_1 (rtx
, rtx
, void *);
394 static int reload_reg_class_lower (const void *, const void *);
395 static void mark_reload_reg_in_use (unsigned int, int, enum reload_type
,
397 static void clear_reload_reg_in_use (unsigned int, int, enum reload_type
,
399 static int reload_reg_free_p (unsigned int, int, enum reload_type
);
400 static int reload_reg_free_for_value_p (int, int, int, enum reload_type
,
402 static int free_for_value_p (int, enum machine_mode
, int, enum reload_type
,
404 static int reload_reg_reaches_end_p (unsigned int, int, enum reload_type
);
405 static int allocate_reload_reg (struct insn_chain
*, int, int);
406 static int conflicts_with_override (rtx
);
407 static void failed_reload (rtx
, int);
408 static int set_reload_reg (int, int);
409 static void choose_reload_regs_init (struct insn_chain
*, rtx
*);
410 static void choose_reload_regs (struct insn_chain
*);
411 static void merge_assigned_reloads (rtx
);
412 static void emit_input_reload_insns (struct insn_chain
*, struct reload
*,
414 static void emit_output_reload_insns (struct insn_chain
*, struct reload
*,
416 static void do_input_reload (struct insn_chain
*, struct reload
*, int);
417 static void do_output_reload (struct insn_chain
*, struct reload
*, int);
418 static void emit_reload_insns (struct insn_chain
*);
419 static void delete_output_reload (rtx
, int, int);
420 static void delete_address_reloads (rtx
, rtx
);
421 static void delete_address_reloads_1 (rtx
, rtx
, rtx
);
422 static rtx
inc_for_reload (rtx
, rtx
, rtx
, int);
424 static void add_auto_inc_notes (rtx
, rtx
);
426 static void copy_eh_notes (rtx
, rtx
);
428 /* Initialize the reload pass once per compilation. */
435 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
436 Set spill_indirect_levels to the number of levels such addressing is
437 permitted, zero if it is not permitted at all. */
440 = gen_rtx_MEM (Pmode
,
443 LAST_VIRTUAL_REGISTER
+ 1),
445 spill_indirect_levels
= 0;
447 while (memory_address_p (QImode
, tem
))
449 spill_indirect_levels
++;
450 tem
= gen_rtx_MEM (Pmode
, tem
);
453 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
455 tem
= gen_rtx_MEM (Pmode
, gen_rtx_SYMBOL_REF (Pmode
, "foo"));
456 indirect_symref_ok
= memory_address_p (QImode
, tem
);
458 /* See if reg+reg is a valid (and offsettable) address. */
460 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
462 tem
= gen_rtx_PLUS (Pmode
,
463 gen_rtx_REG (Pmode
, HARD_FRAME_POINTER_REGNUM
),
464 gen_rtx_REG (Pmode
, i
));
466 /* This way, we make sure that reg+reg is an offsettable address. */
467 tem
= plus_constant (tem
, 4);
469 if (memory_address_p (QImode
, tem
))
471 double_reg_address_ok
= 1;
476 /* Initialize obstack for our rtl allocation. */
477 gcc_obstack_init (&reload_obstack
);
478 reload_startobj
= obstack_alloc (&reload_obstack
, 0);
480 INIT_REG_SET (&spilled_pseudos
);
481 INIT_REG_SET (&pseudos_counted
);
484 /* List of insn chains that are currently unused. */
485 static struct insn_chain
*unused_insn_chains
= 0;
487 /* Allocate an empty insn_chain structure. */
489 new_insn_chain (void)
491 struct insn_chain
*c
;
493 if (unused_insn_chains
== 0)
495 c
= obstack_alloc (&reload_obstack
, sizeof (struct insn_chain
));
496 INIT_REG_SET (&c
->live_throughout
);
497 INIT_REG_SET (&c
->dead_or_set
);
501 c
= unused_insn_chains
;
502 unused_insn_chains
= c
->next
;
504 c
->is_caller_save_insn
= 0;
505 c
->need_operand_change
= 0;
511 /* Small utility function to set all regs in hard reg set TO which are
512 allocated to pseudos in regset FROM. */
515 compute_use_by_pseudos (HARD_REG_SET
*to
, regset from
)
519 EXECUTE_IF_SET_IN_REG_SET
520 (from
, FIRST_PSEUDO_REGISTER
, regno
,
522 int r
= reg_renumber
[regno
];
527 /* reload_combine uses the information from
528 BASIC_BLOCK->global_live_at_start, which might still
529 contain registers that have not actually been allocated
530 since they have an equivalence. */
531 if (! reload_completed
)
536 nregs
= HARD_REGNO_NREGS (r
, PSEUDO_REGNO_MODE (regno
));
538 SET_HARD_REG_BIT (*to
, r
+ nregs
);
543 /* Replace all pseudos found in LOC with their corresponding
547 replace_pseudos_in (rtx
*loc
, enum machine_mode mem_mode
, rtx usage
)
560 unsigned int regno
= REGNO (x
);
562 if (regno
< FIRST_PSEUDO_REGISTER
)
565 x
= eliminate_regs (x
, mem_mode
, usage
);
569 replace_pseudos_in (loc
, mem_mode
, usage
);
573 if (reg_equiv_constant
[regno
])
574 *loc
= reg_equiv_constant
[regno
];
575 else if (reg_equiv_mem
[regno
])
576 *loc
= reg_equiv_mem
[regno
];
577 else if (reg_equiv_address
[regno
])
578 *loc
= gen_rtx_MEM (GET_MODE (x
), reg_equiv_address
[regno
]);
579 else if (GET_CODE (regno_reg_rtx
[regno
]) != REG
580 || REGNO (regno_reg_rtx
[regno
]) != regno
)
581 *loc
= regno_reg_rtx
[regno
];
587 else if (code
== MEM
)
589 replace_pseudos_in (& XEXP (x
, 0), GET_MODE (x
), usage
);
593 /* Process each of our operands recursively. */
594 fmt
= GET_RTX_FORMAT (code
);
595 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++, fmt
++)
597 replace_pseudos_in (&XEXP (x
, i
), mem_mode
, usage
);
598 else if (*fmt
== 'E')
599 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
600 replace_pseudos_in (& XVECEXP (x
, i
, j
), mem_mode
, usage
);
604 /* Global variables used by reload and its subroutines. */
606 /* Set during calculate_needs if an insn needs register elimination. */
607 static int something_needs_elimination
;
608 /* Set during calculate_needs if an insn needs an operand changed. */
609 int something_needs_operands_changed
;
611 /* Nonzero means we couldn't get enough spill regs. */
614 /* Main entry point for the reload pass.
616 FIRST is the first insn of the function being compiled.
618 GLOBAL nonzero means we were called from global_alloc
619 and should attempt to reallocate any pseudoregs that we
620 displace from hard regs we will use for reloads.
621 If GLOBAL is zero, we do not have enough information to do that,
622 so any pseudo reg that is spilled must go to the stack.
624 Return value is nonzero if reload failed
625 and we must not do any more for this function. */
628 reload (rtx first
, int global
)
632 struct elim_table
*ep
;
635 /* Make sure even insns with volatile mem refs are recognizable. */
640 reload_firstobj
= obstack_alloc (&reload_obstack
, 0);
642 /* Make sure that the last insn in the chain
643 is not something that needs reloading. */
644 emit_note (NOTE_INSN_DELETED
);
646 /* Enable find_equiv_reg to distinguish insns made by reload. */
647 reload_first_uid
= get_max_uid ();
649 #ifdef SECONDARY_MEMORY_NEEDED
650 /* Initialize the secondary memory table. */
651 clear_secondary_mem ();
654 /* We don't have a stack slot for any spill reg yet. */
655 memset (spill_stack_slot
, 0, sizeof spill_stack_slot
);
656 memset (spill_stack_slot_width
, 0, sizeof spill_stack_slot_width
);
658 /* Initialize the save area information for caller-save, in case some
662 /* Compute which hard registers are now in use
663 as homes for pseudo registers.
664 This is done here rather than (eg) in global_alloc
665 because this point is reached even if not optimizing. */
666 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
669 /* A function that receives a nonlocal goto must save all call-saved
671 if (current_function_has_nonlocal_label
)
672 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
673 if (! call_used_regs
[i
] && ! fixed_regs
[i
] && ! LOCAL_REGNO (i
))
674 regs_ever_live
[i
] = 1;
676 #ifdef NON_SAVING_SETJMP
677 /* A function that calls setjmp should save and restore all the
678 call-saved registers on a system where longjmp clobbers them. */
679 if (NON_SAVING_SETJMP
&& current_function_calls_setjmp
)
681 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
682 if (! call_used_regs
[i
])
683 regs_ever_live
[i
] = 1;
687 /* Find all the pseudo registers that didn't get hard regs
688 but do have known equivalent constants or memory slots.
689 These include parameters (known equivalent to parameter slots)
690 and cse'd or loop-moved constant memory addresses.
692 Record constant equivalents in reg_equiv_constant
693 so they will be substituted by find_reloads.
694 Record memory equivalents in reg_mem_equiv so they can
695 be substituted eventually by altering the REG-rtx's. */
697 reg_equiv_constant
= xcalloc (max_regno
, sizeof (rtx
));
698 reg_equiv_mem
= xcalloc (max_regno
, sizeof (rtx
));
699 reg_equiv_init
= xcalloc (max_regno
, sizeof (rtx
));
700 reg_equiv_address
= xcalloc (max_regno
, sizeof (rtx
));
701 reg_max_ref_width
= xcalloc (max_regno
, sizeof (int));
702 reg_old_renumber
= xcalloc (max_regno
, sizeof (short));
703 memcpy (reg_old_renumber
, reg_renumber
, max_regno
* sizeof (short));
704 pseudo_forbidden_regs
= xmalloc (max_regno
* sizeof (HARD_REG_SET
));
705 pseudo_previous_regs
= xcalloc (max_regno
, sizeof (HARD_REG_SET
));
707 CLEAR_HARD_REG_SET (bad_spill_regs_global
);
709 /* Look for REG_EQUIV notes; record what each pseudo is equivalent to.
710 Also find all paradoxical subregs and find largest such for each pseudo.
711 On machines with small register classes, record hard registers that
712 are used for user variables. These can never be used for spills. */
714 num_eliminable_invariants
= 0;
715 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
717 rtx set
= single_set (insn
);
719 /* We may introduce USEs that we want to remove at the end, so
720 we'll mark them with QImode. Make sure there are no
721 previously-marked insns left by say regmove. */
722 if (INSN_P (insn
) && GET_CODE (PATTERN (insn
)) == USE
723 && GET_MODE (insn
) != VOIDmode
)
724 PUT_MODE (insn
, VOIDmode
);
726 if (set
!= 0 && GET_CODE (SET_DEST (set
)) == REG
)
728 rtx note
= find_reg_note (insn
, REG_EQUIV
, NULL_RTX
);
730 #ifdef LEGITIMATE_PIC_OPERAND_P
731 && (! function_invariant_p (XEXP (note
, 0))
733 /* A function invariant is often CONSTANT_P but may
734 include a register. We promise to only pass
735 CONSTANT_P objects to LEGITIMATE_PIC_OPERAND_P. */
736 || (CONSTANT_P (XEXP (note
, 0))
737 && LEGITIMATE_PIC_OPERAND_P (XEXP (note
, 0))))
741 rtx x
= XEXP (note
, 0);
742 i
= REGNO (SET_DEST (set
));
743 if (i
> LAST_VIRTUAL_REGISTER
)
745 /* It can happen that a REG_EQUIV note contains a MEM
746 that is not a legitimate memory operand. As later
747 stages of reload assume that all addresses found
748 in the reg_equiv_* arrays were originally legitimate,
749 we ignore such REG_EQUIV notes. */
750 if (memory_operand (x
, VOIDmode
))
752 /* Always unshare the equivalence, so we can
753 substitute into this insn without touching the
755 reg_equiv_memory_loc
[i
] = copy_rtx (x
);
757 else if (function_invariant_p (x
))
759 if (GET_CODE (x
) == PLUS
)
761 /* This is PLUS of frame pointer and a constant,
762 and might be shared. Unshare it. */
763 reg_equiv_constant
[i
] = copy_rtx (x
);
764 num_eliminable_invariants
++;
766 else if (x
== frame_pointer_rtx
767 || x
== arg_pointer_rtx
)
769 reg_equiv_constant
[i
] = x
;
770 num_eliminable_invariants
++;
772 else if (LEGITIMATE_CONSTANT_P (x
))
773 reg_equiv_constant
[i
] = x
;
776 reg_equiv_memory_loc
[i
]
777 = force_const_mem (GET_MODE (SET_DEST (set
)), x
);
778 if (!reg_equiv_memory_loc
[i
])
785 /* If this register is being made equivalent to a MEM
786 and the MEM is not SET_SRC, the equivalencing insn
787 is one with the MEM as a SET_DEST and it occurs later.
788 So don't mark this insn now. */
789 if (GET_CODE (x
) != MEM
790 || rtx_equal_p (SET_SRC (set
), x
))
792 = gen_rtx_INSN_LIST (VOIDmode
, insn
, reg_equiv_init
[i
]);
797 /* If this insn is setting a MEM from a register equivalent to it,
798 this is the equivalencing insn. */
799 else if (set
&& GET_CODE (SET_DEST (set
)) == MEM
800 && GET_CODE (SET_SRC (set
)) == REG
801 && reg_equiv_memory_loc
[REGNO (SET_SRC (set
))]
802 && rtx_equal_p (SET_DEST (set
),
803 reg_equiv_memory_loc
[REGNO (SET_SRC (set
))]))
804 reg_equiv_init
[REGNO (SET_SRC (set
))]
805 = gen_rtx_INSN_LIST (VOIDmode
, insn
,
806 reg_equiv_init
[REGNO (SET_SRC (set
))]);
809 scan_paradoxical_subregs (PATTERN (insn
));
814 first_label_num
= get_first_label_num ();
815 num_labels
= max_label_num () - first_label_num
;
817 /* Allocate the tables used to store offset information at labels. */
818 /* We used to use alloca here, but the size of what it would try to
819 allocate would occasionally cause it to exceed the stack limit and
820 cause a core dump. */
821 offsets_known_at
= xmalloc (num_labels
);
822 offsets_at
= xmalloc (num_labels
* NUM_ELIMINABLE_REGS
* sizeof (HOST_WIDE_INT
));
824 /* Alter each pseudo-reg rtx to contain its hard reg number.
825 Assign stack slots to the pseudos that lack hard regs or equivalents.
826 Do not touch virtual registers. */
828 for (i
= LAST_VIRTUAL_REGISTER
+ 1; i
< max_regno
; i
++)
831 /* If we have some registers we think can be eliminated, scan all insns to
832 see if there is an insn that sets one of these registers to something
833 other than itself plus a constant. If so, the register cannot be
834 eliminated. Doing this scan here eliminates an extra pass through the
835 main reload loop in the most common case where register elimination
837 for (insn
= first
; insn
&& num_eliminable
; insn
= NEXT_INSN (insn
))
838 if (GET_CODE (insn
) == INSN
|| GET_CODE (insn
) == JUMP_INSN
839 || GET_CODE (insn
) == CALL_INSN
)
840 note_stores (PATTERN (insn
), mark_not_eliminable
, NULL
);
842 maybe_fix_stack_asms ();
844 insns_need_reload
= 0;
845 something_needs_elimination
= 0;
847 /* Initialize to -1, which means take the first spill register. */
850 /* Spill any hard regs that we know we can't eliminate. */
851 CLEAR_HARD_REG_SET (used_spill_regs
);
852 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
853 if (! ep
->can_eliminate
)
854 spill_hard_reg (ep
->from
, 1);
856 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
857 if (frame_pointer_needed
)
858 spill_hard_reg (HARD_FRAME_POINTER_REGNUM
, 1);
860 finish_spills (global
);
862 /* From now on, we may need to generate moves differently. We may also
863 allow modifications of insns which cause them to not be recognized.
864 Any such modifications will be cleaned up during reload itself. */
865 reload_in_progress
= 1;
867 /* This loop scans the entire function each go-round
868 and repeats until one repetition spills no additional hard regs. */
871 int something_changed
;
874 HOST_WIDE_INT starting_frame_size
;
876 /* Round size of stack frame to stack_alignment_needed. This must be done
877 here because the stack size may be a part of the offset computation
878 for register elimination, and there might have been new stack slots
879 created in the last iteration of this loop. */
880 if (cfun
->stack_alignment_needed
)
881 assign_stack_local (BLKmode
, 0, cfun
->stack_alignment_needed
);
883 starting_frame_size
= get_frame_size ();
885 set_initial_elim_offsets ();
886 set_initial_label_offsets ();
888 /* For each pseudo register that has an equivalent location defined,
889 try to eliminate any eliminable registers (such as the frame pointer)
890 assuming initial offsets for the replacement register, which
893 If the resulting location is directly addressable, substitute
894 the MEM we just got directly for the old REG.
896 If it is not addressable but is a constant or the sum of a hard reg
897 and constant, it is probably not addressable because the constant is
898 out of range, in that case record the address; we will generate
899 hairy code to compute the address in a register each time it is
900 needed. Similarly if it is a hard register, but one that is not
901 valid as an address register.
903 If the location is not addressable, but does not have one of the
904 above forms, assign a stack slot. We have to do this to avoid the
905 potential of producing lots of reloads if, e.g., a location involves
906 a pseudo that didn't get a hard register and has an equivalent memory
907 location that also involves a pseudo that didn't get a hard register.
909 Perhaps at some point we will improve reload_when_needed handling
910 so this problem goes away. But that's very hairy. */
912 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
913 if (reg_renumber
[i
] < 0 && reg_equiv_memory_loc
[i
])
915 rtx x
= eliminate_regs (reg_equiv_memory_loc
[i
], 0, NULL_RTX
);
917 if (strict_memory_address_p (GET_MODE (regno_reg_rtx
[i
]),
919 reg_equiv_mem
[i
] = x
, reg_equiv_address
[i
] = 0;
920 else if (CONSTANT_P (XEXP (x
, 0))
921 || (GET_CODE (XEXP (x
, 0)) == REG
922 && REGNO (XEXP (x
, 0)) < FIRST_PSEUDO_REGISTER
)
923 || (GET_CODE (XEXP (x
, 0)) == PLUS
924 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == REG
925 && (REGNO (XEXP (XEXP (x
, 0), 0))
926 < FIRST_PSEUDO_REGISTER
)
927 && CONSTANT_P (XEXP (XEXP (x
, 0), 1))))
928 reg_equiv_address
[i
] = XEXP (x
, 0), reg_equiv_mem
[i
] = 0;
931 /* Make a new stack slot. Then indicate that something
932 changed so we go back and recompute offsets for
933 eliminable registers because the allocation of memory
934 below might change some offset. reg_equiv_{mem,address}
935 will be set up for this pseudo on the next pass around
937 reg_equiv_memory_loc
[i
] = 0;
938 reg_equiv_init
[i
] = 0;
943 if (caller_save_needed
)
946 /* If we allocated another stack slot, redo elimination bookkeeping. */
947 if (starting_frame_size
!= get_frame_size ())
950 if (caller_save_needed
)
952 save_call_clobbered_regs ();
953 /* That might have allocated new insn_chain structures. */
954 reload_firstobj
= obstack_alloc (&reload_obstack
, 0);
957 calculate_needs_all_insns (global
);
959 CLEAR_REG_SET (&spilled_pseudos
);
962 something_changed
= 0;
964 /* If we allocated any new memory locations, make another pass
965 since it might have changed elimination offsets. */
966 if (starting_frame_size
!= get_frame_size ())
967 something_changed
= 1;
970 HARD_REG_SET to_spill
;
971 CLEAR_HARD_REG_SET (to_spill
);
972 update_eliminables (&to_spill
);
973 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
974 if (TEST_HARD_REG_BIT (to_spill
, i
))
976 spill_hard_reg (i
, 1);
979 /* Regardless of the state of spills, if we previously had
980 a register that we thought we could eliminate, but now can
981 not eliminate, we must run another pass.
983 Consider pseudos which have an entry in reg_equiv_* which
984 reference an eliminable register. We must make another pass
985 to update reg_equiv_* so that we do not substitute in the
986 old value from when we thought the elimination could be
988 something_changed
= 1;
992 select_reload_regs ();
996 if (insns_need_reload
!= 0 || did_spill
)
997 something_changed
|= finish_spills (global
);
999 if (! something_changed
)
1002 if (caller_save_needed
)
1003 delete_caller_save_insns ();
1005 obstack_free (&reload_obstack
, reload_firstobj
);
1008 /* If global-alloc was run, notify it of any register eliminations we have
1011 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
1012 if (ep
->can_eliminate
)
1013 mark_elimination (ep
->from
, ep
->to
);
1015 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
1016 If that insn didn't set the register (i.e., it copied the register to
1017 memory), just delete that insn instead of the equivalencing insn plus
1018 anything now dead. If we call delete_dead_insn on that insn, we may
1019 delete the insn that actually sets the register if the register dies
1020 there and that is incorrect. */
1022 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
1024 if (reg_renumber
[i
] < 0 && reg_equiv_init
[i
] != 0)
1027 for (list
= reg_equiv_init
[i
]; list
; list
= XEXP (list
, 1))
1029 rtx equiv_insn
= XEXP (list
, 0);
1031 /* If we already deleted the insn or if it may trap, we can't
1032 delete it. The latter case shouldn't happen, but can
1033 if an insn has a variable address, gets a REG_EH_REGION
1034 note added to it, and then gets converted into an load
1035 from a constant address. */
1036 if (GET_CODE (equiv_insn
) == NOTE
1037 || can_throw_internal (equiv_insn
))
1039 else if (reg_set_p (regno_reg_rtx
[i
], PATTERN (equiv_insn
)))
1040 delete_dead_insn (equiv_insn
);
1043 PUT_CODE (equiv_insn
, NOTE
);
1044 NOTE_SOURCE_FILE (equiv_insn
) = 0;
1045 NOTE_LINE_NUMBER (equiv_insn
) = NOTE_INSN_DELETED
;
1051 /* Use the reload registers where necessary
1052 by generating move instructions to move the must-be-register
1053 values into or out of the reload registers. */
1055 if (insns_need_reload
!= 0 || something_needs_elimination
1056 || something_needs_operands_changed
)
1058 HOST_WIDE_INT old_frame_size
= get_frame_size ();
1060 reload_as_needed (global
);
1062 if (old_frame_size
!= get_frame_size ())
1066 verify_initial_elim_offsets ();
1069 /* If we were able to eliminate the frame pointer, show that it is no
1070 longer live at the start of any basic block. If it ls live by
1071 virtue of being in a pseudo, that pseudo will be marked live
1072 and hence the frame pointer will be known to be live via that
1075 if (! frame_pointer_needed
)
1077 CLEAR_REGNO_REG_SET (bb
->global_live_at_start
,
1078 HARD_FRAME_POINTER_REGNUM
);
1080 /* Come here (with failure set nonzero) if we can't get enough spill regs
1081 and we decide not to abort about it. */
1084 CLEAR_REG_SET (&spilled_pseudos
);
1085 reload_in_progress
= 0;
1087 /* Now eliminate all pseudo regs by modifying them into
1088 their equivalent memory references.
1089 The REG-rtx's for the pseudos are modified in place,
1090 so all insns that used to refer to them now refer to memory.
1092 For a reg that has a reg_equiv_address, all those insns
1093 were changed by reloading so that no insns refer to it any longer;
1094 but the DECL_RTL of a variable decl may refer to it,
1095 and if so this causes the debugging info to mention the variable. */
1097 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
1101 if (reg_equiv_mem
[i
])
1102 addr
= XEXP (reg_equiv_mem
[i
], 0);
1104 if (reg_equiv_address
[i
])
1105 addr
= reg_equiv_address
[i
];
1109 if (reg_renumber
[i
] < 0)
1111 rtx reg
= regno_reg_rtx
[i
];
1113 REG_USERVAR_P (reg
) = 0;
1114 PUT_CODE (reg
, MEM
);
1115 XEXP (reg
, 0) = addr
;
1116 if (reg_equiv_memory_loc
[i
])
1117 MEM_COPY_ATTRIBUTES (reg
, reg_equiv_memory_loc
[i
]);
1120 RTX_UNCHANGING_P (reg
) = MEM_IN_STRUCT_P (reg
)
1121 = MEM_SCALAR_P (reg
) = 0;
1122 MEM_ATTRS (reg
) = 0;
1125 else if (reg_equiv_mem
[i
])
1126 XEXP (reg_equiv_mem
[i
], 0) = addr
;
1130 /* We must set reload_completed now since the cleanup_subreg_operands call
1131 below will re-recognize each insn and reload may have generated insns
1132 which are only valid during and after reload. */
1133 reload_completed
= 1;
1135 /* Make a pass over all the insns and delete all USEs which we inserted
1136 only to tag a REG_EQUAL note on them. Remove all REG_DEAD and REG_UNUSED
1137 notes. Delete all CLOBBER insns, except those that refer to the return
1138 value and the special mem:BLK CLOBBERs added to prevent the scheduler
1139 from misarranging variable-array code, and simplify (subreg (reg))
1140 operands. Also remove all REG_RETVAL and REG_LIBCALL notes since they
1141 are no longer useful or accurate. Strip and regenerate REG_INC notes
1142 that may have been moved around. */
1144 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
1149 if (GET_CODE (insn
) == CALL_INSN
)
1150 replace_pseudos_in (& CALL_INSN_FUNCTION_USAGE (insn
),
1151 VOIDmode
, CALL_INSN_FUNCTION_USAGE (insn
));
1153 if ((GET_CODE (PATTERN (insn
)) == USE
1154 /* We mark with QImode USEs introduced by reload itself. */
1155 && (GET_MODE (insn
) == QImode
1156 || find_reg_note (insn
, REG_EQUAL
, NULL_RTX
)))
1157 || (GET_CODE (PATTERN (insn
)) == CLOBBER
1158 && (GET_CODE (XEXP (PATTERN (insn
), 0)) != MEM
1159 || GET_MODE (XEXP (PATTERN (insn
), 0)) != BLKmode
1160 || (GET_CODE (XEXP (XEXP (PATTERN (insn
), 0), 0)) != SCRATCH
1161 && XEXP (XEXP (PATTERN (insn
), 0), 0)
1162 != stack_pointer_rtx
))
1163 && (GET_CODE (XEXP (PATTERN (insn
), 0)) != REG
1164 || ! REG_FUNCTION_VALUE_P (XEXP (PATTERN (insn
), 0)))))
1170 /* Some CLOBBERs may survive until here and still reference unassigned
1171 pseudos with const equivalent, which may in turn cause ICE in later
1172 passes if the reference remains in place. */
1173 if (GET_CODE (PATTERN (insn
)) == CLOBBER
)
1174 replace_pseudos_in (& XEXP (PATTERN (insn
), 0),
1175 VOIDmode
, PATTERN (insn
));
1177 pnote
= ®_NOTES (insn
);
1180 if (REG_NOTE_KIND (*pnote
) == REG_DEAD
1181 || REG_NOTE_KIND (*pnote
) == REG_UNUSED
1182 || REG_NOTE_KIND (*pnote
) == REG_INC
1183 || REG_NOTE_KIND (*pnote
) == REG_RETVAL
1184 || REG_NOTE_KIND (*pnote
) == REG_LIBCALL
)
1185 *pnote
= XEXP (*pnote
, 1);
1187 pnote
= &XEXP (*pnote
, 1);
1191 add_auto_inc_notes (insn
, PATTERN (insn
));
1194 /* And simplify (subreg (reg)) if it appears as an operand. */
1195 cleanup_subreg_operands (insn
);
1198 /* If we are doing stack checking, give a warning if this function's
1199 frame size is larger than we expect. */
1200 if (flag_stack_check
&& ! STACK_CHECK_BUILTIN
)
1202 HOST_WIDE_INT size
= get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE
;
1203 static int verbose_warned
= 0;
1205 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1206 if (regs_ever_live
[i
] && ! fixed_regs
[i
] && call_used_regs
[i
])
1207 size
+= UNITS_PER_WORD
;
1209 if (size
> STACK_CHECK_MAX_FRAME_SIZE
)
1211 warning ("frame size too large for reliable stack checking");
1212 if (! verbose_warned
)
1214 warning ("try reducing the number of local variables");
1220 /* Indicate that we no longer have known memory locations or constants. */
1221 if (reg_equiv_constant
)
1222 free (reg_equiv_constant
);
1223 reg_equiv_constant
= 0;
1224 if (reg_equiv_memory_loc
)
1225 free (reg_equiv_memory_loc
);
1226 reg_equiv_memory_loc
= 0;
1228 if (offsets_known_at
)
1229 free (offsets_known_at
);
1233 free (reg_equiv_mem
);
1234 free (reg_equiv_init
);
1235 free (reg_equiv_address
);
1236 free (reg_max_ref_width
);
1237 free (reg_old_renumber
);
1238 free (pseudo_previous_regs
);
1239 free (pseudo_forbidden_regs
);
1241 CLEAR_HARD_REG_SET (used_spill_regs
);
1242 for (i
= 0; i
< n_spills
; i
++)
1243 SET_HARD_REG_BIT (used_spill_regs
, spill_regs
[i
]);
1245 /* Free all the insn_chain structures at once. */
1246 obstack_free (&reload_obstack
, reload_startobj
);
1247 unused_insn_chains
= 0;
1248 fixup_abnormal_edges ();
1250 /* Replacing pseudos with their memory equivalents might have
1251 created shared rtx. Subsequent passes would get confused
1252 by this, so unshare everything here. */
1253 unshare_all_rtl_again (first
);
1255 #ifdef STACK_BOUNDARY
1256 /* init_emit has set the alignment of the hard frame pointer
1257 to STACK_BOUNDARY. It is very likely no longer valid if
1258 the hard frame pointer was used for register allocation. */
1259 if (!frame_pointer_needed
)
1260 REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM
) = BITS_PER_UNIT
;
1266 /* Yet another special case. Unfortunately, reg-stack forces people to
1267 write incorrect clobbers in asm statements. These clobbers must not
1268 cause the register to appear in bad_spill_regs, otherwise we'll call
1269 fatal_insn later. We clear the corresponding regnos in the live
1270 register sets to avoid this.
1271 The whole thing is rather sick, I'm afraid. */
1274 maybe_fix_stack_asms (void)
1277 const char *constraints
[MAX_RECOG_OPERANDS
];
1278 enum machine_mode operand_mode
[MAX_RECOG_OPERANDS
];
1279 struct insn_chain
*chain
;
1281 for (chain
= reload_insn_chain
; chain
!= 0; chain
= chain
->next
)
1284 HARD_REG_SET clobbered
, allowed
;
1287 if (! INSN_P (chain
->insn
)
1288 || (noperands
= asm_noperands (PATTERN (chain
->insn
))) < 0)
1290 pat
= PATTERN (chain
->insn
);
1291 if (GET_CODE (pat
) != PARALLEL
)
1294 CLEAR_HARD_REG_SET (clobbered
);
1295 CLEAR_HARD_REG_SET (allowed
);
1297 /* First, make a mask of all stack regs that are clobbered. */
1298 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
1300 rtx t
= XVECEXP (pat
, 0, i
);
1301 if (GET_CODE (t
) == CLOBBER
&& STACK_REG_P (XEXP (t
, 0)))
1302 SET_HARD_REG_BIT (clobbered
, REGNO (XEXP (t
, 0)));
1305 /* Get the operand values and constraints out of the insn. */
1306 decode_asm_operands (pat
, recog_data
.operand
, recog_data
.operand_loc
,
1307 constraints
, operand_mode
);
1309 /* For every operand, see what registers are allowed. */
1310 for (i
= 0; i
< noperands
; i
++)
1312 const char *p
= constraints
[i
];
1313 /* For every alternative, we compute the class of registers allowed
1314 for reloading in CLS, and merge its contents into the reg set
1316 int cls
= (int) NO_REGS
;
1322 if (c
== '\0' || c
== ',' || c
== '#')
1324 /* End of one alternative - mark the regs in the current
1325 class, and reset the class. */
1326 IOR_HARD_REG_SET (allowed
, reg_class_contents
[cls
]);
1332 } while (c
!= '\0' && c
!= ',');
1340 case '=': case '+': case '*': case '%': case '?': case '!':
1341 case '0': case '1': case '2': case '3': case '4': case 'm':
1342 case '<': case '>': case 'V': case 'o': case '&': case 'E':
1343 case 'F': case 's': case 'i': case 'n': case 'X': case 'I':
1344 case 'J': case 'K': case 'L': case 'M': case 'N': case 'O':
1349 cls
= (int) reg_class_subunion
[cls
]
1350 [(int) MODE_BASE_REG_CLASS (VOIDmode
)];
1355 cls
= (int) reg_class_subunion
[cls
][(int) GENERAL_REGS
];
1359 if (EXTRA_ADDRESS_CONSTRAINT (c
, p
))
1360 cls
= (int) reg_class_subunion
[cls
]
1361 [(int) MODE_BASE_REG_CLASS (VOIDmode
)];
1363 cls
= (int) reg_class_subunion
[cls
]
1364 [(int) REG_CLASS_FROM_CONSTRAINT (c
, p
)];
1366 p
+= CONSTRAINT_LEN (c
, p
);
1369 /* Those of the registers which are clobbered, but allowed by the
1370 constraints, must be usable as reload registers. So clear them
1371 out of the life information. */
1372 AND_HARD_REG_SET (allowed
, clobbered
);
1373 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1374 if (TEST_HARD_REG_BIT (allowed
, i
))
1376 CLEAR_REGNO_REG_SET (&chain
->live_throughout
, i
);
1377 CLEAR_REGNO_REG_SET (&chain
->dead_or_set
, i
);
1384 /* Copy the global variables n_reloads and rld into the corresponding elts
1387 copy_reloads (struct insn_chain
*chain
)
1389 chain
->n_reloads
= n_reloads
;
1390 chain
->rld
= obstack_alloc (&reload_obstack
,
1391 n_reloads
* sizeof (struct reload
));
1392 memcpy (chain
->rld
, rld
, n_reloads
* sizeof (struct reload
));
1393 reload_insn_firstobj
= obstack_alloc (&reload_obstack
, 0);
1396 /* Walk the chain of insns, and determine for each whether it needs reloads
1397 and/or eliminations. Build the corresponding insns_need_reload list, and
1398 set something_needs_elimination as appropriate. */
1400 calculate_needs_all_insns (int global
)
1402 struct insn_chain
**pprev_reload
= &insns_need_reload
;
1403 struct insn_chain
*chain
, *next
= 0;
1405 something_needs_elimination
= 0;
1407 reload_insn_firstobj
= obstack_alloc (&reload_obstack
, 0);
1408 for (chain
= reload_insn_chain
; chain
!= 0; chain
= next
)
1410 rtx insn
= chain
->insn
;
1414 /* Clear out the shortcuts. */
1415 chain
->n_reloads
= 0;
1416 chain
->need_elim
= 0;
1417 chain
->need_reload
= 0;
1418 chain
->need_operand_change
= 0;
1420 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1421 include REG_LABEL), we need to see what effects this has on the
1422 known offsets at labels. */
1424 if (GET_CODE (insn
) == CODE_LABEL
|| GET_CODE (insn
) == JUMP_INSN
1425 || (INSN_P (insn
) && REG_NOTES (insn
) != 0))
1426 set_label_offsets (insn
, insn
, 0);
1430 rtx old_body
= PATTERN (insn
);
1431 int old_code
= INSN_CODE (insn
);
1432 rtx old_notes
= REG_NOTES (insn
);
1433 int did_elimination
= 0;
1434 int operands_changed
= 0;
1435 rtx set
= single_set (insn
);
1437 /* Skip insns that only set an equivalence. */
1438 if (set
&& GET_CODE (SET_DEST (set
)) == REG
1439 && reg_renumber
[REGNO (SET_DEST (set
))] < 0
1440 && reg_equiv_constant
[REGNO (SET_DEST (set
))])
1443 /* If needed, eliminate any eliminable registers. */
1444 if (num_eliminable
|| num_eliminable_invariants
)
1445 did_elimination
= eliminate_regs_in_insn (insn
, 0);
1447 /* Analyze the instruction. */
1448 operands_changed
= find_reloads (insn
, 0, spill_indirect_levels
,
1449 global
, spill_reg_order
);
1451 /* If a no-op set needs more than one reload, this is likely
1452 to be something that needs input address reloads. We
1453 can't get rid of this cleanly later, and it is of no use
1454 anyway, so discard it now.
1455 We only do this when expensive_optimizations is enabled,
1456 since this complements reload inheritance / output
1457 reload deletion, and it can make debugging harder. */
1458 if (flag_expensive_optimizations
&& n_reloads
> 1)
1460 rtx set
= single_set (insn
);
1462 && SET_SRC (set
) == SET_DEST (set
)
1463 && GET_CODE (SET_SRC (set
)) == REG
1464 && REGNO (SET_SRC (set
)) >= FIRST_PSEUDO_REGISTER
)
1467 /* Delete it from the reload chain. */
1469 chain
->prev
->next
= next
;
1471 reload_insn_chain
= next
;
1473 next
->prev
= chain
->prev
;
1474 chain
->next
= unused_insn_chains
;
1475 unused_insn_chains
= chain
;
1480 update_eliminable_offsets ();
1482 /* Remember for later shortcuts which insns had any reloads or
1483 register eliminations. */
1484 chain
->need_elim
= did_elimination
;
1485 chain
->need_reload
= n_reloads
> 0;
1486 chain
->need_operand_change
= operands_changed
;
1488 /* Discard any register replacements done. */
1489 if (did_elimination
)
1491 obstack_free (&reload_obstack
, reload_insn_firstobj
);
1492 PATTERN (insn
) = old_body
;
1493 INSN_CODE (insn
) = old_code
;
1494 REG_NOTES (insn
) = old_notes
;
1495 something_needs_elimination
= 1;
1498 something_needs_operands_changed
|= operands_changed
;
1502 copy_reloads (chain
);
1503 *pprev_reload
= chain
;
1504 pprev_reload
= &chain
->next_need_reload
;
1511 /* Comparison function for qsort to decide which of two reloads
1512 should be handled first. *P1 and *P2 are the reload numbers. */
1515 reload_reg_class_lower (const void *r1p
, const void *r2p
)
1517 int r1
= *(const short *) r1p
, r2
= *(const short *) r2p
;
1520 /* Consider required reloads before optional ones. */
1521 t
= rld
[r1
].optional
- rld
[r2
].optional
;
1525 /* Count all solitary classes before non-solitary ones. */
1526 t
= ((reg_class_size
[(int) rld
[r2
].class] == 1)
1527 - (reg_class_size
[(int) rld
[r1
].class] == 1));
1531 /* Aside from solitaires, consider all multi-reg groups first. */
1532 t
= rld
[r2
].nregs
- rld
[r1
].nregs
;
1536 /* Consider reloads in order of increasing reg-class number. */
1537 t
= (int) rld
[r1
].class - (int) rld
[r2
].class;
1541 /* If reloads are equally urgent, sort by reload number,
1542 so that the results of qsort leave nothing to chance. */
1546 /* The cost of spilling each hard reg. */
1547 static int spill_cost
[FIRST_PSEUDO_REGISTER
];
1549 /* When spilling multiple hard registers, we use SPILL_COST for the first
1550 spilled hard reg and SPILL_ADD_COST for subsequent regs. SPILL_ADD_COST
1551 only the first hard reg for a multi-reg pseudo. */
1552 static int spill_add_cost
[FIRST_PSEUDO_REGISTER
];
1554 /* Update the spill cost arrays, considering that pseudo REG is live. */
1557 count_pseudo (int reg
)
1559 int freq
= REG_FREQ (reg
);
1560 int r
= reg_renumber
[reg
];
1563 if (REGNO_REG_SET_P (&pseudos_counted
, reg
)
1564 || REGNO_REG_SET_P (&spilled_pseudos
, reg
))
1567 SET_REGNO_REG_SET (&pseudos_counted
, reg
);
1572 spill_add_cost
[r
] += freq
;
1574 nregs
= HARD_REGNO_NREGS (r
, PSEUDO_REGNO_MODE (reg
));
1576 spill_cost
[r
+ nregs
] += freq
;
1579 /* Calculate the SPILL_COST and SPILL_ADD_COST arrays and determine the
1580 contents of BAD_SPILL_REGS for the insn described by CHAIN. */
1583 order_regs_for_reload (struct insn_chain
*chain
)
1586 HARD_REG_SET used_by_pseudos
;
1587 HARD_REG_SET used_by_pseudos2
;
1589 COPY_HARD_REG_SET (bad_spill_regs
, fixed_reg_set
);
1591 memset (spill_cost
, 0, sizeof spill_cost
);
1592 memset (spill_add_cost
, 0, sizeof spill_add_cost
);
1594 /* Count number of uses of each hard reg by pseudo regs allocated to it
1595 and then order them by decreasing use. First exclude hard registers
1596 that are live in or across this insn. */
1598 REG_SET_TO_HARD_REG_SET (used_by_pseudos
, &chain
->live_throughout
);
1599 REG_SET_TO_HARD_REG_SET (used_by_pseudos2
, &chain
->dead_or_set
);
1600 IOR_HARD_REG_SET (bad_spill_regs
, used_by_pseudos
);
1601 IOR_HARD_REG_SET (bad_spill_regs
, used_by_pseudos2
);
1603 /* Now find out which pseudos are allocated to it, and update
1605 CLEAR_REG_SET (&pseudos_counted
);
1607 EXECUTE_IF_SET_IN_REG_SET
1608 (&chain
->live_throughout
, FIRST_PSEUDO_REGISTER
, i
,
1612 EXECUTE_IF_SET_IN_REG_SET
1613 (&chain
->dead_or_set
, FIRST_PSEUDO_REGISTER
, i
,
1617 CLEAR_REG_SET (&pseudos_counted
);
1620 /* Vector of reload-numbers showing the order in which the reloads should
1622 static short reload_order
[MAX_RELOADS
];
1624 /* This is used to keep track of the spill regs used in one insn. */
1625 static HARD_REG_SET used_spill_regs_local
;
1627 /* We decided to spill hard register SPILLED, which has a size of
1628 SPILLED_NREGS. Determine how pseudo REG, which is live during the insn,
1629 is affected. We will add it to SPILLED_PSEUDOS if necessary, and we will
1630 update SPILL_COST/SPILL_ADD_COST. */
1633 count_spilled_pseudo (int spilled
, int spilled_nregs
, int reg
)
1635 int r
= reg_renumber
[reg
];
1636 int nregs
= HARD_REGNO_NREGS (r
, PSEUDO_REGNO_MODE (reg
));
1638 if (REGNO_REG_SET_P (&spilled_pseudos
, reg
)
1639 || spilled
+ spilled_nregs
<= r
|| r
+ nregs
<= spilled
)
1642 SET_REGNO_REG_SET (&spilled_pseudos
, reg
);
1644 spill_add_cost
[r
] -= REG_FREQ (reg
);
1646 spill_cost
[r
+ nregs
] -= REG_FREQ (reg
);
1649 /* Find reload register to use for reload number ORDER. */
1652 find_reg (struct insn_chain
*chain
, int order
)
1654 int rnum
= reload_order
[order
];
1655 struct reload
*rl
= rld
+ rnum
;
1656 int best_cost
= INT_MAX
;
1660 HARD_REG_SET not_usable
;
1661 HARD_REG_SET used_by_other_reload
;
1663 COPY_HARD_REG_SET (not_usable
, bad_spill_regs
);
1664 IOR_HARD_REG_SET (not_usable
, bad_spill_regs_global
);
1665 IOR_COMPL_HARD_REG_SET (not_usable
, reg_class_contents
[rl
->class]);
1667 CLEAR_HARD_REG_SET (used_by_other_reload
);
1668 for (k
= 0; k
< order
; k
++)
1670 int other
= reload_order
[k
];
1672 if (rld
[other
].regno
>= 0 && reloads_conflict (other
, rnum
))
1673 for (j
= 0; j
< rld
[other
].nregs
; j
++)
1674 SET_HARD_REG_BIT (used_by_other_reload
, rld
[other
].regno
+ j
);
1677 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1679 unsigned int regno
= i
;
1681 if (! TEST_HARD_REG_BIT (not_usable
, regno
)
1682 && ! TEST_HARD_REG_BIT (used_by_other_reload
, regno
)
1683 && HARD_REGNO_MODE_OK (regno
, rl
->mode
))
1685 int this_cost
= spill_cost
[regno
];
1687 unsigned int this_nregs
= HARD_REGNO_NREGS (regno
, rl
->mode
);
1689 for (j
= 1; j
< this_nregs
; j
++)
1691 this_cost
+= spill_add_cost
[regno
+ j
];
1692 if ((TEST_HARD_REG_BIT (not_usable
, regno
+ j
))
1693 || TEST_HARD_REG_BIT (used_by_other_reload
, regno
+ j
))
1698 if (rl
->in
&& GET_CODE (rl
->in
) == REG
&& REGNO (rl
->in
) == regno
)
1700 if (rl
->out
&& GET_CODE (rl
->out
) == REG
&& REGNO (rl
->out
) == regno
)
1702 if (this_cost
< best_cost
1703 /* Among registers with equal cost, prefer caller-saved ones, or
1704 use REG_ALLOC_ORDER if it is defined. */
1705 || (this_cost
== best_cost
1706 #ifdef REG_ALLOC_ORDER
1707 && (inv_reg_alloc_order
[regno
]
1708 < inv_reg_alloc_order
[best_reg
])
1710 && call_used_regs
[regno
]
1711 && ! call_used_regs
[best_reg
]
1716 best_cost
= this_cost
;
1724 fprintf (rtl_dump_file
, "Using reg %d for reload %d\n", best_reg
, rnum
);
1726 rl
->nregs
= HARD_REGNO_NREGS (best_reg
, rl
->mode
);
1727 rl
->regno
= best_reg
;
1729 EXECUTE_IF_SET_IN_REG_SET
1730 (&chain
->live_throughout
, FIRST_PSEUDO_REGISTER
, j
,
1732 count_spilled_pseudo (best_reg
, rl
->nregs
, j
);
1735 EXECUTE_IF_SET_IN_REG_SET
1736 (&chain
->dead_or_set
, FIRST_PSEUDO_REGISTER
, j
,
1738 count_spilled_pseudo (best_reg
, rl
->nregs
, j
);
1741 for (i
= 0; i
< rl
->nregs
; i
++)
1743 if (spill_cost
[best_reg
+ i
] != 0
1744 || spill_add_cost
[best_reg
+ i
] != 0)
1746 SET_HARD_REG_BIT (used_spill_regs_local
, best_reg
+ i
);
1751 /* Find more reload regs to satisfy the remaining need of an insn, which
1753 Do it by ascending class number, since otherwise a reg
1754 might be spilled for a big class and might fail to count
1755 for a smaller class even though it belongs to that class. */
1758 find_reload_regs (struct insn_chain
*chain
)
1762 /* In order to be certain of getting the registers we need,
1763 we must sort the reloads into order of increasing register class.
1764 Then our grabbing of reload registers will parallel the process
1765 that provided the reload registers. */
1766 for (i
= 0; i
< chain
->n_reloads
; i
++)
1768 /* Show whether this reload already has a hard reg. */
1769 if (chain
->rld
[i
].reg_rtx
)
1771 int regno
= REGNO (chain
->rld
[i
].reg_rtx
);
1772 chain
->rld
[i
].regno
= regno
;
1774 = HARD_REGNO_NREGS (regno
, GET_MODE (chain
->rld
[i
].reg_rtx
));
1777 chain
->rld
[i
].regno
= -1;
1778 reload_order
[i
] = i
;
1781 n_reloads
= chain
->n_reloads
;
1782 memcpy (rld
, chain
->rld
, n_reloads
* sizeof (struct reload
));
1784 CLEAR_HARD_REG_SET (used_spill_regs_local
);
1787 fprintf (rtl_dump_file
, "Spilling for insn %d.\n", INSN_UID (chain
->insn
));
1789 qsort (reload_order
, n_reloads
, sizeof (short), reload_reg_class_lower
);
1791 /* Compute the order of preference for hard registers to spill. */
1793 order_regs_for_reload (chain
);
1795 for (i
= 0; i
< n_reloads
; i
++)
1797 int r
= reload_order
[i
];
1799 /* Ignore reloads that got marked inoperative. */
1800 if ((rld
[r
].out
!= 0 || rld
[r
].in
!= 0 || rld
[r
].secondary_p
)
1801 && ! rld
[r
].optional
1802 && rld
[r
].regno
== -1)
1803 if (! find_reg (chain
, i
))
1805 spill_failure (chain
->insn
, rld
[r
].class);
1811 COPY_HARD_REG_SET (chain
->used_spill_regs
, used_spill_regs_local
);
1812 IOR_HARD_REG_SET (used_spill_regs
, used_spill_regs_local
);
1814 memcpy (chain
->rld
, rld
, n_reloads
* sizeof (struct reload
));
1818 select_reload_regs (void)
1820 struct insn_chain
*chain
;
1822 /* Try to satisfy the needs for each insn. */
1823 for (chain
= insns_need_reload
; chain
!= 0;
1824 chain
= chain
->next_need_reload
)
1825 find_reload_regs (chain
);
1828 /* Delete all insns that were inserted by emit_caller_save_insns during
1831 delete_caller_save_insns (void)
1833 struct insn_chain
*c
= reload_insn_chain
;
1837 while (c
!= 0 && c
->is_caller_save_insn
)
1839 struct insn_chain
*next
= c
->next
;
1842 if (c
== reload_insn_chain
)
1843 reload_insn_chain
= next
;
1847 next
->prev
= c
->prev
;
1849 c
->prev
->next
= next
;
1850 c
->next
= unused_insn_chains
;
1851 unused_insn_chains
= c
;
1859 /* Handle the failure to find a register to spill.
1860 INSN should be one of the insns which needed this particular spill reg. */
1863 spill_failure (rtx insn
, enum reg_class
class)
1865 static const char *const reg_class_names
[] = REG_CLASS_NAMES
;
1866 if (asm_noperands (PATTERN (insn
)) >= 0)
1867 error_for_asm (insn
, "can't find a register in class `%s' while reloading `asm'",
1868 reg_class_names
[class]);
1871 error ("unable to find a register to spill in class `%s'",
1872 reg_class_names
[class]);
1873 fatal_insn ("this is the insn:", insn
);
1877 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
1878 data that is dead in INSN. */
1881 delete_dead_insn (rtx insn
)
1883 rtx prev
= prev_real_insn (insn
);
1886 /* If the previous insn sets a register that dies in our insn, delete it
1888 if (prev
&& GET_CODE (PATTERN (prev
)) == SET
1889 && (prev_dest
= SET_DEST (PATTERN (prev
)), GET_CODE (prev_dest
) == REG
)
1890 && reg_mentioned_p (prev_dest
, PATTERN (insn
))
1891 && find_regno_note (insn
, REG_DEAD
, REGNO (prev_dest
))
1892 && ! side_effects_p (SET_SRC (PATTERN (prev
))))
1893 delete_dead_insn (prev
);
1895 PUT_CODE (insn
, NOTE
);
1896 NOTE_LINE_NUMBER (insn
) = NOTE_INSN_DELETED
;
1897 NOTE_SOURCE_FILE (insn
) = 0;
1900 /* Modify the home of pseudo-reg I.
1901 The new home is present in reg_renumber[I].
1903 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
1904 or it may be -1, meaning there is none or it is not relevant.
1905 This is used so that all pseudos spilled from a given hard reg
1906 can share one stack slot. */
1909 alter_reg (int i
, int from_reg
)
1911 /* When outputting an inline function, this can happen
1912 for a reg that isn't actually used. */
1913 if (regno_reg_rtx
[i
] == 0)
1916 /* If the reg got changed to a MEM at rtl-generation time,
1918 if (GET_CODE (regno_reg_rtx
[i
]) != REG
)
1921 /* Modify the reg-rtx to contain the new hard reg
1922 number or else to contain its pseudo reg number. */
1923 REGNO (regno_reg_rtx
[i
])
1924 = reg_renumber
[i
] >= 0 ? reg_renumber
[i
] : i
;
1926 /* If we have a pseudo that is needed but has no hard reg or equivalent,
1927 allocate a stack slot for it. */
1929 if (reg_renumber
[i
] < 0
1930 && REG_N_REFS (i
) > 0
1931 && reg_equiv_constant
[i
] == 0
1932 && reg_equiv_memory_loc
[i
] == 0)
1935 unsigned int inherent_size
= PSEUDO_REGNO_BYTES (i
);
1936 unsigned int total_size
= MAX (inherent_size
, reg_max_ref_width
[i
]);
1939 /* Each pseudo reg has an inherent size which comes from its own mode,
1940 and a total size which provides room for paradoxical subregs
1941 which refer to the pseudo reg in wider modes.
1943 We can use a slot already allocated if it provides both
1944 enough inherent space and enough total space.
1945 Otherwise, we allocate a new slot, making sure that it has no less
1946 inherent space, and no less total space, then the previous slot. */
1949 /* No known place to spill from => no slot to reuse. */
1950 x
= assign_stack_local (GET_MODE (regno_reg_rtx
[i
]), total_size
,
1951 inherent_size
== total_size
? 0 : -1);
1952 if (BYTES_BIG_ENDIAN
)
1953 /* Cancel the big-endian correction done in assign_stack_local.
1954 Get the address of the beginning of the slot.
1955 This is so we can do a big-endian correction unconditionally
1957 adjust
= inherent_size
- total_size
;
1959 RTX_UNCHANGING_P (x
) = RTX_UNCHANGING_P (regno_reg_rtx
[i
]);
1961 /* Nothing can alias this slot except this pseudo. */
1962 set_mem_alias_set (x
, new_alias_set ());
1965 /* Reuse a stack slot if possible. */
1966 else if (spill_stack_slot
[from_reg
] != 0
1967 && spill_stack_slot_width
[from_reg
] >= total_size
1968 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot
[from_reg
]))
1970 x
= spill_stack_slot
[from_reg
];
1972 /* Allocate a bigger slot. */
1975 /* Compute maximum size needed, both for inherent size
1976 and for total size. */
1977 enum machine_mode mode
= GET_MODE (regno_reg_rtx
[i
]);
1980 if (spill_stack_slot
[from_reg
])
1982 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot
[from_reg
]))
1984 mode
= GET_MODE (spill_stack_slot
[from_reg
]);
1985 if (spill_stack_slot_width
[from_reg
] > total_size
)
1986 total_size
= spill_stack_slot_width
[from_reg
];
1989 /* Make a slot with that size. */
1990 x
= assign_stack_local (mode
, total_size
,
1991 inherent_size
== total_size
? 0 : -1);
1994 /* All pseudos mapped to this slot can alias each other. */
1995 if (spill_stack_slot
[from_reg
])
1996 set_mem_alias_set (x
, MEM_ALIAS_SET (spill_stack_slot
[from_reg
]));
1998 set_mem_alias_set (x
, new_alias_set ());
2000 if (BYTES_BIG_ENDIAN
)
2002 /* Cancel the big-endian correction done in assign_stack_local.
2003 Get the address of the beginning of the slot.
2004 This is so we can do a big-endian correction unconditionally
2006 adjust
= GET_MODE_SIZE (mode
) - total_size
;
2009 = adjust_address_nv (x
, mode_for_size (total_size
2015 spill_stack_slot
[from_reg
] = stack_slot
;
2016 spill_stack_slot_width
[from_reg
] = total_size
;
2019 /* On a big endian machine, the "address" of the slot
2020 is the address of the low part that fits its inherent mode. */
2021 if (BYTES_BIG_ENDIAN
&& inherent_size
< total_size
)
2022 adjust
+= (total_size
- inherent_size
);
2024 /* If we have any adjustment to make, or if the stack slot is the
2025 wrong mode, make a new stack slot. */
2026 x
= adjust_address_nv (x
, GET_MODE (regno_reg_rtx
[i
]), adjust
);
2028 /* If we have a decl for the original register, set it for the
2029 memory. If this is a shared MEM, make a copy. */
2030 if (REG_EXPR (regno_reg_rtx
[i
])
2031 && TREE_CODE_CLASS (TREE_CODE (REG_EXPR (regno_reg_rtx
[i
]))) == 'd')
2033 rtx decl
= DECL_RTL_IF_SET (REG_EXPR (regno_reg_rtx
[i
]));
2035 /* We can do this only for the DECLs home pseudo, not for
2036 any copies of it, since otherwise when the stack slot
2037 is reused, nonoverlapping_memrefs_p might think they
2039 if (decl
&& GET_CODE (decl
) == REG
&& REGNO (decl
) == (unsigned) i
)
2041 if (from_reg
!= -1 && spill_stack_slot
[from_reg
] == x
)
2044 set_mem_attrs_from_reg (x
, regno_reg_rtx
[i
]);
2048 /* Save the stack slot for later. */
2049 reg_equiv_memory_loc
[i
] = x
;
2053 /* Mark the slots in regs_ever_live for the hard regs
2054 used by pseudo-reg number REGNO. */
2057 mark_home_live (int regno
)
2061 i
= reg_renumber
[regno
];
2064 lim
= i
+ HARD_REGNO_NREGS (i
, PSEUDO_REGNO_MODE (regno
));
2066 regs_ever_live
[i
++] = 1;
2069 /* This function handles the tracking of elimination offsets around branches.
2071 X is a piece of RTL being scanned.
2073 INSN is the insn that it came from, if any.
2075 INITIAL_P is nonzero if we are to set the offset to be the initial
2076 offset and zero if we are setting the offset of the label to be the
2080 set_label_offsets (rtx x
, rtx insn
, int initial_p
)
2082 enum rtx_code code
= GET_CODE (x
);
2085 struct elim_table
*p
;
2090 if (LABEL_REF_NONLOCAL_P (x
))
2095 /* ... fall through ... */
2098 /* If we know nothing about this label, set the desired offsets. Note
2099 that this sets the offset at a label to be the offset before a label
2100 if we don't know anything about the label. This is not correct for
2101 the label after a BARRIER, but is the best guess we can make. If
2102 we guessed wrong, we will suppress an elimination that might have
2103 been possible had we been able to guess correctly. */
2105 if (! offsets_known_at
[CODE_LABEL_NUMBER (x
) - first_label_num
])
2107 for (i
= 0; i
< NUM_ELIMINABLE_REGS
; i
++)
2108 offsets_at
[CODE_LABEL_NUMBER (x
) - first_label_num
][i
]
2109 = (initial_p
? reg_eliminate
[i
].initial_offset
2110 : reg_eliminate
[i
].offset
);
2111 offsets_known_at
[CODE_LABEL_NUMBER (x
) - first_label_num
] = 1;
2114 /* Otherwise, if this is the definition of a label and it is
2115 preceded by a BARRIER, set our offsets to the known offset of
2119 && (tem
= prev_nonnote_insn (insn
)) != 0
2120 && GET_CODE (tem
) == BARRIER
)
2121 set_offsets_for_label (insn
);
2123 /* If neither of the above cases is true, compare each offset
2124 with those previously recorded and suppress any eliminations
2125 where the offsets disagree. */
2127 for (i
= 0; i
< NUM_ELIMINABLE_REGS
; i
++)
2128 if (offsets_at
[CODE_LABEL_NUMBER (x
) - first_label_num
][i
]
2129 != (initial_p
? reg_eliminate
[i
].initial_offset
2130 : reg_eliminate
[i
].offset
))
2131 reg_eliminate
[i
].can_eliminate
= 0;
2136 set_label_offsets (PATTERN (insn
), insn
, initial_p
);
2138 /* ... fall through ... */
2142 /* Any labels mentioned in REG_LABEL notes can be branched to indirectly
2143 and hence must have all eliminations at their initial offsets. */
2144 for (tem
= REG_NOTES (x
); tem
; tem
= XEXP (tem
, 1))
2145 if (REG_NOTE_KIND (tem
) == REG_LABEL
)
2146 set_label_offsets (XEXP (tem
, 0), insn
, 1);
2152 /* Each of the labels in the parallel or address vector must be
2153 at their initial offsets. We want the first field for PARALLEL
2154 and ADDR_VEC and the second field for ADDR_DIFF_VEC. */
2156 for (i
= 0; i
< (unsigned) XVECLEN (x
, code
== ADDR_DIFF_VEC
); i
++)
2157 set_label_offsets (XVECEXP (x
, code
== ADDR_DIFF_VEC
, i
),
2162 /* We only care about setting PC. If the source is not RETURN,
2163 IF_THEN_ELSE, or a label, disable any eliminations not at
2164 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2165 isn't one of those possibilities. For branches to a label,
2166 call ourselves recursively.
2168 Note that this can disable elimination unnecessarily when we have
2169 a non-local goto since it will look like a non-constant jump to
2170 someplace in the current function. This isn't a significant
2171 problem since such jumps will normally be when all elimination
2172 pairs are back to their initial offsets. */
2174 if (SET_DEST (x
) != pc_rtx
)
2177 switch (GET_CODE (SET_SRC (x
)))
2184 set_label_offsets (XEXP (SET_SRC (x
), 0), insn
, initial_p
);
2188 tem
= XEXP (SET_SRC (x
), 1);
2189 if (GET_CODE (tem
) == LABEL_REF
)
2190 set_label_offsets (XEXP (tem
, 0), insn
, initial_p
);
2191 else if (GET_CODE (tem
) != PC
&& GET_CODE (tem
) != RETURN
)
2194 tem
= XEXP (SET_SRC (x
), 2);
2195 if (GET_CODE (tem
) == LABEL_REF
)
2196 set_label_offsets (XEXP (tem
, 0), insn
, initial_p
);
2197 else if (GET_CODE (tem
) != PC
&& GET_CODE (tem
) != RETURN
)
2205 /* If we reach here, all eliminations must be at their initial
2206 offset because we are doing a jump to a variable address. */
2207 for (p
= reg_eliminate
; p
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; p
++)
2208 if (p
->offset
!= p
->initial_offset
)
2209 p
->can_eliminate
= 0;
2217 /* Scan X and replace any eliminable registers (such as fp) with a
2218 replacement (such as sp), plus an offset.
2220 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2221 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2222 MEM, we are allowed to replace a sum of a register and the constant zero
2223 with the register, which we cannot do outside a MEM. In addition, we need
2224 to record the fact that a register is referenced outside a MEM.
2226 If INSN is an insn, it is the insn containing X. If we replace a REG
2227 in a SET_DEST with an equivalent MEM and INSN is nonzero, write a
2228 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2229 the REG is being modified.
2231 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2232 That's used when we eliminate in expressions stored in notes.
2233 This means, do not set ref_outside_mem even if the reference
2236 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2237 replacements done assuming all offsets are at their initial values. If
2238 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2239 encounter, return the actual location so that find_reloads will do
2240 the proper thing. */
2243 eliminate_regs (rtx x
, enum machine_mode mem_mode
, rtx insn
)
2245 enum rtx_code code
= GET_CODE (x
);
2246 struct elim_table
*ep
;
2253 if (! current_function_decl
)
2273 /* This is only for the benefit of the debugging backends, which call
2274 eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are
2275 removed after CSE. */
2276 new = eliminate_regs (XEXP (x
, 0), 0, insn
);
2277 if (GET_CODE (new) == MEM
)
2278 return XEXP (new, 0);
2284 /* First handle the case where we encounter a bare register that
2285 is eliminable. Replace it with a PLUS. */
2286 if (regno
< FIRST_PSEUDO_REGISTER
)
2288 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
2290 if (ep
->from_rtx
== x
&& ep
->can_eliminate
)
2291 return plus_constant (ep
->to_rtx
, ep
->previous_offset
);
2294 else if (reg_renumber
&& reg_renumber
[regno
] < 0
2295 && reg_equiv_constant
&& reg_equiv_constant
[regno
]
2296 && ! CONSTANT_P (reg_equiv_constant
[regno
]))
2297 return eliminate_regs (copy_rtx (reg_equiv_constant
[regno
]),
2301 /* You might think handling MINUS in a manner similar to PLUS is a
2302 good idea. It is not. It has been tried multiple times and every
2303 time the change has had to have been reverted.
2305 Other parts of reload know a PLUS is special (gen_reload for example)
2306 and require special code to handle code a reloaded PLUS operand.
2308 Also consider backends where the flags register is clobbered by a
2309 MINUS, but we can emit a PLUS that does not clobber flags (ia32,
2310 lea instruction comes to mind). If we try to reload a MINUS, we
2311 may kill the flags register that was holding a useful value.
2313 So, please before trying to handle MINUS, consider reload as a
2314 whole instead of this little section as well as the backend issues. */
2316 /* If this is the sum of an eliminable register and a constant, rework
2318 if (GET_CODE (XEXP (x
, 0)) == REG
2319 && REGNO (XEXP (x
, 0)) < FIRST_PSEUDO_REGISTER
2320 && CONSTANT_P (XEXP (x
, 1)))
2322 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
2324 if (ep
->from_rtx
== XEXP (x
, 0) && ep
->can_eliminate
)
2326 /* The only time we want to replace a PLUS with a REG (this
2327 occurs when the constant operand of the PLUS is the negative
2328 of the offset) is when we are inside a MEM. We won't want
2329 to do so at other times because that would change the
2330 structure of the insn in a way that reload can't handle.
2331 We special-case the commonest situation in
2332 eliminate_regs_in_insn, so just replace a PLUS with a
2333 PLUS here, unless inside a MEM. */
2334 if (mem_mode
!= 0 && GET_CODE (XEXP (x
, 1)) == CONST_INT
2335 && INTVAL (XEXP (x
, 1)) == - ep
->previous_offset
)
2338 return gen_rtx_PLUS (Pmode
, ep
->to_rtx
,
2339 plus_constant (XEXP (x
, 1),
2340 ep
->previous_offset
));
2343 /* If the register is not eliminable, we are done since the other
2344 operand is a constant. */
2348 /* If this is part of an address, we want to bring any constant to the
2349 outermost PLUS. We will do this by doing register replacement in
2350 our operands and seeing if a constant shows up in one of them.
2352 Note that there is no risk of modifying the structure of the insn,
2353 since we only get called for its operands, thus we are either
2354 modifying the address inside a MEM, or something like an address
2355 operand of a load-address insn. */
2358 rtx new0
= eliminate_regs (XEXP (x
, 0), mem_mode
, insn
);
2359 rtx new1
= eliminate_regs (XEXP (x
, 1), mem_mode
, insn
);
2361 if (reg_renumber
&& (new0
!= XEXP (x
, 0) || new1
!= XEXP (x
, 1)))
2363 /* If one side is a PLUS and the other side is a pseudo that
2364 didn't get a hard register but has a reg_equiv_constant,
2365 we must replace the constant here since it may no longer
2366 be in the position of any operand. */
2367 if (GET_CODE (new0
) == PLUS
&& GET_CODE (new1
) == REG
2368 && REGNO (new1
) >= FIRST_PSEUDO_REGISTER
2369 && reg_renumber
[REGNO (new1
)] < 0
2370 && reg_equiv_constant
!= 0
2371 && reg_equiv_constant
[REGNO (new1
)] != 0)
2372 new1
= reg_equiv_constant
[REGNO (new1
)];
2373 else if (GET_CODE (new1
) == PLUS
&& GET_CODE (new0
) == REG
2374 && REGNO (new0
) >= FIRST_PSEUDO_REGISTER
2375 && reg_renumber
[REGNO (new0
)] < 0
2376 && reg_equiv_constant
[REGNO (new0
)] != 0)
2377 new0
= reg_equiv_constant
[REGNO (new0
)];
2379 new = form_sum (new0
, new1
);
2381 /* As above, if we are not inside a MEM we do not want to
2382 turn a PLUS into something else. We might try to do so here
2383 for an addition of 0 if we aren't optimizing. */
2384 if (! mem_mode
&& GET_CODE (new) != PLUS
)
2385 return gen_rtx_PLUS (GET_MODE (x
), new, const0_rtx
);
2393 /* If this is the product of an eliminable register and a
2394 constant, apply the distribute law and move the constant out
2395 so that we have (plus (mult ..) ..). This is needed in order
2396 to keep load-address insns valid. This case is pathological.
2397 We ignore the possibility of overflow here. */
2398 if (GET_CODE (XEXP (x
, 0)) == REG
2399 && REGNO (XEXP (x
, 0)) < FIRST_PSEUDO_REGISTER
2400 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
2401 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
2403 if (ep
->from_rtx
== XEXP (x
, 0) && ep
->can_eliminate
)
2406 /* Refs inside notes don't count for this purpose. */
2407 && ! (insn
!= 0 && (GET_CODE (insn
) == EXPR_LIST
2408 || GET_CODE (insn
) == INSN_LIST
)))
2409 ep
->ref_outside_mem
= 1;
2412 plus_constant (gen_rtx_MULT (Pmode
, ep
->to_rtx
, XEXP (x
, 1)),
2413 ep
->previous_offset
* INTVAL (XEXP (x
, 1)));
2416 /* ... fall through ... */
2420 /* See comments before PLUS about handling MINUS. */
2422 case DIV
: case UDIV
:
2423 case MOD
: case UMOD
:
2424 case AND
: case IOR
: case XOR
:
2425 case ROTATERT
: case ROTATE
:
2426 case ASHIFTRT
: case LSHIFTRT
: case ASHIFT
:
2428 case GE
: case GT
: case GEU
: case GTU
:
2429 case LE
: case LT
: case LEU
: case LTU
:
2431 rtx new0
= eliminate_regs (XEXP (x
, 0), mem_mode
, insn
);
2433 = XEXP (x
, 1) ? eliminate_regs (XEXP (x
, 1), mem_mode
, insn
) : 0;
2435 if (new0
!= XEXP (x
, 0) || new1
!= XEXP (x
, 1))
2436 return gen_rtx_fmt_ee (code
, GET_MODE (x
), new0
, new1
);
2441 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2444 new = eliminate_regs (XEXP (x
, 0), mem_mode
, insn
);
2445 if (new != XEXP (x
, 0))
2447 /* If this is a REG_DEAD note, it is not valid anymore.
2448 Using the eliminated version could result in creating a
2449 REG_DEAD note for the stack or frame pointer. */
2450 if (GET_MODE (x
) == REG_DEAD
)
2452 ? eliminate_regs (XEXP (x
, 1), mem_mode
, insn
)
2455 x
= gen_rtx_EXPR_LIST (REG_NOTE_KIND (x
), new, XEXP (x
, 1));
2459 /* ... fall through ... */
2462 /* Now do eliminations in the rest of the chain. If this was
2463 an EXPR_LIST, this might result in allocating more memory than is
2464 strictly needed, but it simplifies the code. */
2467 new = eliminate_regs (XEXP (x
, 1), mem_mode
, insn
);
2468 if (new != XEXP (x
, 1))
2470 gen_rtx_fmt_ee (GET_CODE (x
), GET_MODE (x
), XEXP (x
, 0), new);
2478 case STRICT_LOW_PART
:
2480 case SIGN_EXTEND
: case ZERO_EXTEND
:
2481 case TRUNCATE
: case FLOAT_EXTEND
: case FLOAT_TRUNCATE
:
2482 case FLOAT
: case FIX
:
2483 case UNSIGNED_FIX
: case UNSIGNED_FLOAT
:
2491 new = eliminate_regs (XEXP (x
, 0), mem_mode
, insn
);
2492 if (new != XEXP (x
, 0))
2493 return gen_rtx_fmt_e (code
, GET_MODE (x
), new);
2497 /* Similar to above processing, but preserve SUBREG_BYTE.
2498 Convert (subreg (mem)) to (mem) if not paradoxical.
2499 Also, if we have a non-paradoxical (subreg (pseudo)) and the
2500 pseudo didn't get a hard reg, we must replace this with the
2501 eliminated version of the memory location because push_reload
2502 may do the replacement in certain circumstances. */
2503 if (GET_CODE (SUBREG_REG (x
)) == REG
2504 && (GET_MODE_SIZE (GET_MODE (x
))
2505 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
2506 && reg_equiv_memory_loc
!= 0
2507 && reg_equiv_memory_loc
[REGNO (SUBREG_REG (x
))] != 0)
2509 new = SUBREG_REG (x
);
2512 new = eliminate_regs (SUBREG_REG (x
), mem_mode
, insn
);
2514 if (new != SUBREG_REG (x
))
2516 int x_size
= GET_MODE_SIZE (GET_MODE (x
));
2517 int new_size
= GET_MODE_SIZE (GET_MODE (new));
2519 if (GET_CODE (new) == MEM
2520 && ((x_size
< new_size
2521 #ifdef WORD_REGISTER_OPERATIONS
2522 /* On these machines, combine can create rtl of the form
2523 (set (subreg:m1 (reg:m2 R) 0) ...)
2524 where m1 < m2, and expects something interesting to
2525 happen to the entire word. Moreover, it will use the
2526 (reg:m2 R) later, expecting all bits to be preserved.
2527 So if the number of words is the same, preserve the
2528 subreg so that push_reload can see it. */
2529 && ! ((x_size
- 1) / UNITS_PER_WORD
2530 == (new_size
-1 ) / UNITS_PER_WORD
)
2533 || x_size
== new_size
)
2535 return adjust_address_nv (new, GET_MODE (x
), SUBREG_BYTE (x
));
2537 return gen_rtx_SUBREG (GET_MODE (x
), new, SUBREG_BYTE (x
));
2543 /* This is only for the benefit of the debugging backends, which call
2544 eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are
2545 removed after CSE. */
2546 if (GET_CODE (XEXP (x
, 0)) == ADDRESSOF
)
2547 return eliminate_regs (XEXP (XEXP (x
, 0), 0), 0, insn
);
2549 /* Our only special processing is to pass the mode of the MEM to our
2550 recursive call and copy the flags. While we are here, handle this
2551 case more efficiently. */
2553 replace_equiv_address_nv (x
,
2554 eliminate_regs (XEXP (x
, 0),
2555 GET_MODE (x
), insn
));
2558 /* Handle insn_list USE that a call to a pure function may generate. */
2559 new = eliminate_regs (XEXP (x
, 0), 0, insn
);
2560 if (new != XEXP (x
, 0))
2561 return gen_rtx_USE (GET_MODE (x
), new);
2573 /* Process each of our operands recursively. If any have changed, make a
2575 fmt
= GET_RTX_FORMAT (code
);
2576 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++, fmt
++)
2580 new = eliminate_regs (XEXP (x
, i
), mem_mode
, insn
);
2581 if (new != XEXP (x
, i
) && ! copied
)
2583 rtx new_x
= rtx_alloc (code
);
2584 memcpy (new_x
, x
, RTX_SIZE (code
));
2590 else if (*fmt
== 'E')
2593 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
2595 new = eliminate_regs (XVECEXP (x
, i
, j
), mem_mode
, insn
);
2596 if (new != XVECEXP (x
, i
, j
) && ! copied_vec
)
2598 rtvec new_v
= gen_rtvec_v (XVECLEN (x
, i
),
2602 rtx new_x
= rtx_alloc (code
);
2603 memcpy (new_x
, x
, RTX_SIZE (code
));
2607 XVEC (x
, i
) = new_v
;
2610 XVECEXP (x
, i
, j
) = new;
2618 /* Scan rtx X for modifications of elimination target registers. Update
2619 the table of eliminables to reflect the changed state. MEM_MODE is
2620 the mode of an enclosing MEM rtx, or VOIDmode if not within a MEM. */
2623 elimination_effects (rtx x
, enum machine_mode mem_mode
)
2625 enum rtx_code code
= GET_CODE (x
);
2626 struct elim_table
*ep
;
2653 /* First handle the case where we encounter a bare register that
2654 is eliminable. Replace it with a PLUS. */
2655 if (regno
< FIRST_PSEUDO_REGISTER
)
2657 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
2659 if (ep
->from_rtx
== x
&& ep
->can_eliminate
)
2662 ep
->ref_outside_mem
= 1;
2667 else if (reg_renumber
[regno
] < 0 && reg_equiv_constant
2668 && reg_equiv_constant
[regno
]
2669 && ! function_invariant_p (reg_equiv_constant
[regno
]))
2670 elimination_effects (reg_equiv_constant
[regno
], mem_mode
);
2679 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
2680 if (ep
->to_rtx
== XEXP (x
, 0))
2682 int size
= GET_MODE_SIZE (mem_mode
);
2684 /* If more bytes than MEM_MODE are pushed, account for them. */
2685 #ifdef PUSH_ROUNDING
2686 if (ep
->to_rtx
== stack_pointer_rtx
)
2687 size
= PUSH_ROUNDING (size
);
2689 if (code
== PRE_DEC
|| code
== POST_DEC
)
2691 else if (code
== PRE_INC
|| code
== POST_INC
)
2693 else if ((code
== PRE_MODIFY
|| code
== POST_MODIFY
)
2694 && GET_CODE (XEXP (x
, 1)) == PLUS
2695 && XEXP (x
, 0) == XEXP (XEXP (x
, 1), 0)
2696 && CONSTANT_P (XEXP (XEXP (x
, 1), 1)))
2697 ep
->offset
-= INTVAL (XEXP (XEXP (x
, 1), 1));
2700 /* These two aren't unary operators. */
2701 if (code
== POST_MODIFY
|| code
== PRE_MODIFY
)
2704 /* Fall through to generic unary operation case. */
2705 case STRICT_LOW_PART
:
2707 case SIGN_EXTEND
: case ZERO_EXTEND
:
2708 case TRUNCATE
: case FLOAT_EXTEND
: case FLOAT_TRUNCATE
:
2709 case FLOAT
: case FIX
:
2710 case UNSIGNED_FIX
: case UNSIGNED_FLOAT
:
2718 elimination_effects (XEXP (x
, 0), mem_mode
);
2722 if (GET_CODE (SUBREG_REG (x
)) == REG
2723 && (GET_MODE_SIZE (GET_MODE (x
))
2724 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
2725 && reg_equiv_memory_loc
!= 0
2726 && reg_equiv_memory_loc
[REGNO (SUBREG_REG (x
))] != 0)
2729 elimination_effects (SUBREG_REG (x
), mem_mode
);
2733 /* If using a register that is the source of an eliminate we still
2734 think can be performed, note it cannot be performed since we don't
2735 know how this register is used. */
2736 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
2737 if (ep
->from_rtx
== XEXP (x
, 0))
2738 ep
->can_eliminate
= 0;
2740 elimination_effects (XEXP (x
, 0), mem_mode
);
2744 /* If clobbering a register that is the replacement register for an
2745 elimination we still think can be performed, note that it cannot
2746 be performed. Otherwise, we need not be concerned about it. */
2747 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
2748 if (ep
->to_rtx
== XEXP (x
, 0))
2749 ep
->can_eliminate
= 0;
2751 elimination_effects (XEXP (x
, 0), mem_mode
);
2755 /* Check for setting a register that we know about. */
2756 if (GET_CODE (SET_DEST (x
)) == REG
)
2758 /* See if this is setting the replacement register for an
2761 If DEST is the hard frame pointer, we do nothing because we
2762 assume that all assignments to the frame pointer are for
2763 non-local gotos and are being done at a time when they are valid
2764 and do not disturb anything else. Some machines want to
2765 eliminate a fake argument pointer (or even a fake frame pointer)
2766 with either the real frame or the stack pointer. Assignments to
2767 the hard frame pointer must not prevent this elimination. */
2769 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
2771 if (ep
->to_rtx
== SET_DEST (x
)
2772 && SET_DEST (x
) != hard_frame_pointer_rtx
)
2774 /* If it is being incremented, adjust the offset. Otherwise,
2775 this elimination can't be done. */
2776 rtx src
= SET_SRC (x
);
2778 if (GET_CODE (src
) == PLUS
2779 && XEXP (src
, 0) == SET_DEST (x
)
2780 && GET_CODE (XEXP (src
, 1)) == CONST_INT
)
2781 ep
->offset
-= INTVAL (XEXP (src
, 1));
2783 ep
->can_eliminate
= 0;
2787 elimination_effects (SET_DEST (x
), 0);
2788 elimination_effects (SET_SRC (x
), 0);
2792 if (GET_CODE (XEXP (x
, 0)) == ADDRESSOF
)
2795 /* Our only special processing is to pass the mode of the MEM to our
2797 elimination_effects (XEXP (x
, 0), GET_MODE (x
));
2804 fmt
= GET_RTX_FORMAT (code
);
2805 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++, fmt
++)
2808 elimination_effects (XEXP (x
, i
), mem_mode
);
2809 else if (*fmt
== 'E')
2810 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
2811 elimination_effects (XVECEXP (x
, i
, j
), mem_mode
);
2815 /* Descend through rtx X and verify that no references to eliminable registers
2816 remain. If any do remain, mark the involved register as not
2820 check_eliminable_occurrences (rtx x
)
2829 code
= GET_CODE (x
);
2831 if (code
== REG
&& REGNO (x
) < FIRST_PSEUDO_REGISTER
)
2833 struct elim_table
*ep
;
2835 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
2836 if (ep
->from_rtx
== x
&& ep
->can_eliminate
)
2837 ep
->can_eliminate
= 0;
2841 fmt
= GET_RTX_FORMAT (code
);
2842 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++, fmt
++)
2845 check_eliminable_occurrences (XEXP (x
, i
));
2846 else if (*fmt
== 'E')
2849 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
2850 check_eliminable_occurrences (XVECEXP (x
, i
, j
));
2855 /* Scan INSN and eliminate all eliminable registers in it.
2857 If REPLACE is nonzero, do the replacement destructively. Also
2858 delete the insn as dead it if it is setting an eliminable register.
2860 If REPLACE is zero, do all our allocations in reload_obstack.
2862 If no eliminations were done and this insn doesn't require any elimination
2863 processing (these are not identical conditions: it might be updating sp,
2864 but not referencing fp; this needs to be seen during reload_as_needed so
2865 that the offset between fp and sp can be taken into consideration), zero
2866 is returned. Otherwise, 1 is returned. */
2869 eliminate_regs_in_insn (rtx insn
, int replace
)
2871 int icode
= recog_memoized (insn
);
2872 rtx old_body
= PATTERN (insn
);
2873 int insn_is_asm
= asm_noperands (old_body
) >= 0;
2874 rtx old_set
= single_set (insn
);
2878 rtx substed_operand
[MAX_RECOG_OPERANDS
];
2879 rtx orig_operand
[MAX_RECOG_OPERANDS
];
2880 struct elim_table
*ep
;
2882 if (! insn_is_asm
&& icode
< 0)
2884 if (GET_CODE (PATTERN (insn
)) == USE
2885 || GET_CODE (PATTERN (insn
)) == CLOBBER
2886 || GET_CODE (PATTERN (insn
)) == ADDR_VEC
2887 || GET_CODE (PATTERN (insn
)) == ADDR_DIFF_VEC
2888 || GET_CODE (PATTERN (insn
)) == ASM_INPUT
)
2893 if (old_set
!= 0 && GET_CODE (SET_DEST (old_set
)) == REG
2894 && REGNO (SET_DEST (old_set
)) < FIRST_PSEUDO_REGISTER
)
2896 /* Check for setting an eliminable register. */
2897 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
2898 if (ep
->from_rtx
== SET_DEST (old_set
) && ep
->can_eliminate
)
2900 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
2901 /* If this is setting the frame pointer register to the
2902 hardware frame pointer register and this is an elimination
2903 that will be done (tested above), this insn is really
2904 adjusting the frame pointer downward to compensate for
2905 the adjustment done before a nonlocal goto. */
2906 if (ep
->from
== FRAME_POINTER_REGNUM
2907 && ep
->to
== HARD_FRAME_POINTER_REGNUM
)
2909 rtx base
= SET_SRC (old_set
);
2910 rtx base_insn
= insn
;
2911 HOST_WIDE_INT offset
= 0;
2913 while (base
!= ep
->to_rtx
)
2915 rtx prev_insn
, prev_set
;
2917 if (GET_CODE (base
) == PLUS
2918 && GET_CODE (XEXP (base
, 1)) == CONST_INT
)
2920 offset
+= INTVAL (XEXP (base
, 1));
2921 base
= XEXP (base
, 0);
2923 else if ((prev_insn
= prev_nonnote_insn (base_insn
)) != 0
2924 && (prev_set
= single_set (prev_insn
)) != 0
2925 && rtx_equal_p (SET_DEST (prev_set
), base
))
2927 base
= SET_SRC (prev_set
);
2928 base_insn
= prev_insn
;
2934 if (base
== ep
->to_rtx
)
2937 = plus_constant (ep
->to_rtx
, offset
- ep
->offset
);
2939 new_body
= old_body
;
2942 new_body
= copy_insn (old_body
);
2943 if (REG_NOTES (insn
))
2944 REG_NOTES (insn
) = copy_insn_1 (REG_NOTES (insn
));
2946 PATTERN (insn
) = new_body
;
2947 old_set
= single_set (insn
);
2949 /* First see if this insn remains valid when we
2950 make the change. If not, keep the INSN_CODE
2951 the same and let reload fit it up. */
2952 validate_change (insn
, &SET_SRC (old_set
), src
, 1);
2953 validate_change (insn
, &SET_DEST (old_set
),
2955 if (! apply_change_group ())
2957 SET_SRC (old_set
) = src
;
2958 SET_DEST (old_set
) = ep
->to_rtx
;
2967 /* In this case this insn isn't serving a useful purpose. We
2968 will delete it in reload_as_needed once we know that this
2969 elimination is, in fact, being done.
2971 If REPLACE isn't set, we can't delete this insn, but needn't
2972 process it since it won't be used unless something changes. */
2975 delete_dead_insn (insn
);
2983 /* We allow one special case which happens to work on all machines we
2984 currently support: a single set with the source being a PLUS of an
2985 eliminable register and a constant. */
2987 && GET_CODE (SET_DEST (old_set
)) == REG
2988 && GET_CODE (SET_SRC (old_set
)) == PLUS
2989 && GET_CODE (XEXP (SET_SRC (old_set
), 0)) == REG
2990 && GET_CODE (XEXP (SET_SRC (old_set
), 1)) == CONST_INT
2991 && REGNO (XEXP (SET_SRC (old_set
), 0)) < FIRST_PSEUDO_REGISTER
)
2993 rtx reg
= XEXP (SET_SRC (old_set
), 0);
2994 HOST_WIDE_INT offset
= INTVAL (XEXP (SET_SRC (old_set
), 1));
2996 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
2997 if (ep
->from_rtx
== reg
&& ep
->can_eliminate
)
2999 offset
+= ep
->offset
;
3004 /* We assume here that if we need a PARALLEL with
3005 CLOBBERs for this assignment, we can do with the
3006 MATCH_SCRATCHes that add_clobbers allocates.
3007 There's not much we can do if that doesn't work. */
3008 PATTERN (insn
) = gen_rtx_SET (VOIDmode
,
3012 INSN_CODE (insn
) = recog (PATTERN (insn
), insn
, &num_clobbers
);
3015 rtvec vec
= rtvec_alloc (num_clobbers
+ 1);
3017 vec
->elem
[0] = PATTERN (insn
);
3018 PATTERN (insn
) = gen_rtx_PARALLEL (VOIDmode
, vec
);
3019 add_clobbers (PATTERN (insn
), INSN_CODE (insn
));
3021 if (INSN_CODE (insn
) < 0)
3026 new_body
= old_body
;
3029 new_body
= copy_insn (old_body
);
3030 if (REG_NOTES (insn
))
3031 REG_NOTES (insn
) = copy_insn_1 (REG_NOTES (insn
));
3033 PATTERN (insn
) = new_body
;
3034 old_set
= single_set (insn
);
3036 XEXP (SET_SRC (old_set
), 0) = ep
->to_rtx
;
3037 XEXP (SET_SRC (old_set
), 1) = GEN_INT (offset
);
3040 /* This can't have an effect on elimination offsets, so skip right
3046 /* Determine the effects of this insn on elimination offsets. */
3047 elimination_effects (old_body
, 0);
3049 /* Eliminate all eliminable registers occurring in operands that
3050 can be handled by reload. */
3051 extract_insn (insn
);
3052 for (i
= 0; i
< recog_data
.n_operands
; i
++)
3054 orig_operand
[i
] = recog_data
.operand
[i
];
3055 substed_operand
[i
] = recog_data
.operand
[i
];
3057 /* For an asm statement, every operand is eliminable. */
3058 if (insn_is_asm
|| insn_data
[icode
].operand
[i
].eliminable
)
3060 /* Check for setting a register that we know about. */
3061 if (recog_data
.operand_type
[i
] != OP_IN
3062 && GET_CODE (orig_operand
[i
]) == REG
)
3064 /* If we are assigning to a register that can be eliminated, it
3065 must be as part of a PARALLEL, since the code above handles
3066 single SETs. We must indicate that we can no longer
3067 eliminate this reg. */
3068 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
3070 if (ep
->from_rtx
== orig_operand
[i
] && ep
->can_eliminate
)
3071 ep
->can_eliminate
= 0;
3074 substed_operand
[i
] = eliminate_regs (recog_data
.operand
[i
], 0,
3075 replace
? insn
: NULL_RTX
);
3076 if (substed_operand
[i
] != orig_operand
[i
])
3078 /* Terminate the search in check_eliminable_occurrences at
3080 *recog_data
.operand_loc
[i
] = 0;
3082 /* If an output operand changed from a REG to a MEM and INSN is an
3083 insn, write a CLOBBER insn. */
3084 if (recog_data
.operand_type
[i
] != OP_IN
3085 && GET_CODE (orig_operand
[i
]) == REG
3086 && GET_CODE (substed_operand
[i
]) == MEM
3088 emit_insn_after (gen_rtx_CLOBBER (VOIDmode
, orig_operand
[i
]),
3093 for (i
= 0; i
< recog_data
.n_dups
; i
++)
3094 *recog_data
.dup_loc
[i
]
3095 = *recog_data
.operand_loc
[(int) recog_data
.dup_num
[i
]];
3097 /* If any eliminable remain, they aren't eliminable anymore. */
3098 check_eliminable_occurrences (old_body
);
3100 /* Substitute the operands; the new values are in the substed_operand
3102 for (i
= 0; i
< recog_data
.n_operands
; i
++)
3103 *recog_data
.operand_loc
[i
] = substed_operand
[i
];
3104 for (i
= 0; i
< recog_data
.n_dups
; i
++)
3105 *recog_data
.dup_loc
[i
] = substed_operand
[(int) recog_data
.dup_num
[i
]];
3107 /* If we are replacing a body that was a (set X (plus Y Z)), try to
3108 re-recognize the insn. We do this in case we had a simple addition
3109 but now can do this as a load-address. This saves an insn in this
3111 If re-recognition fails, the old insn code number will still be used,
3112 and some register operands may have changed into PLUS expressions.
3113 These will be handled by find_reloads by loading them into a register
3118 /* If we aren't replacing things permanently and we changed something,
3119 make another copy to ensure that all the RTL is new. Otherwise
3120 things can go wrong if find_reload swaps commutative operands
3121 and one is inside RTL that has been copied while the other is not. */
3122 new_body
= old_body
;
3125 new_body
= copy_insn (old_body
);
3126 if (REG_NOTES (insn
))
3127 REG_NOTES (insn
) = copy_insn_1 (REG_NOTES (insn
));
3129 PATTERN (insn
) = new_body
;
3131 /* If we had a move insn but now we don't, rerecognize it. This will
3132 cause spurious re-recognition if the old move had a PARALLEL since
3133 the new one still will, but we can't call single_set without
3134 having put NEW_BODY into the insn and the re-recognition won't
3135 hurt in this rare case. */
3136 /* ??? Why this huge if statement - why don't we just rerecognize the
3140 && ((GET_CODE (SET_SRC (old_set
)) == REG
3141 && (GET_CODE (new_body
) != SET
3142 || GET_CODE (SET_SRC (new_body
)) != REG
))
3143 /* If this was a load from or store to memory, compare
3144 the MEM in recog_data.operand to the one in the insn.
3145 If they are not equal, then rerecognize the insn. */
3147 && ((GET_CODE (SET_SRC (old_set
)) == MEM
3148 && SET_SRC (old_set
) != recog_data
.operand
[1])
3149 || (GET_CODE (SET_DEST (old_set
)) == MEM
3150 && SET_DEST (old_set
) != recog_data
.operand
[0])))
3151 /* If this was an add insn before, rerecognize. */
3152 || GET_CODE (SET_SRC (old_set
)) == PLUS
))
3154 int new_icode
= recog (PATTERN (insn
), insn
, 0);
3156 INSN_CODE (insn
) = icode
;
3160 /* Restore the old body. If there were any changes to it, we made a copy
3161 of it while the changes were still in place, so we'll correctly return
3162 a modified insn below. */
3165 /* Restore the old body. */
3166 for (i
= 0; i
< recog_data
.n_operands
; i
++)
3167 *recog_data
.operand_loc
[i
] = orig_operand
[i
];
3168 for (i
= 0; i
< recog_data
.n_dups
; i
++)
3169 *recog_data
.dup_loc
[i
] = orig_operand
[(int) recog_data
.dup_num
[i
]];
3172 /* Update all elimination pairs to reflect the status after the current
3173 insn. The changes we make were determined by the earlier call to
3174 elimination_effects.
3176 We also detect cases where register elimination cannot be done,
3177 namely, if a register would be both changed and referenced outside a MEM
3178 in the resulting insn since such an insn is often undefined and, even if
3179 not, we cannot know what meaning will be given to it. Note that it is
3180 valid to have a register used in an address in an insn that changes it
3181 (presumably with a pre- or post-increment or decrement).
3183 If anything changes, return nonzero. */
3185 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3187 if (ep
->previous_offset
!= ep
->offset
&& ep
->ref_outside_mem
)
3188 ep
->can_eliminate
= 0;
3190 ep
->ref_outside_mem
= 0;
3192 if (ep
->previous_offset
!= ep
->offset
)
3197 /* If we changed something, perform elimination in REG_NOTES. This is
3198 needed even when REPLACE is zero because a REG_DEAD note might refer
3199 to a register that we eliminate and could cause a different number
3200 of spill registers to be needed in the final reload pass than in
3202 if (val
&& REG_NOTES (insn
) != 0)
3203 REG_NOTES (insn
) = eliminate_regs (REG_NOTES (insn
), 0, REG_NOTES (insn
));
3208 /* Loop through all elimination pairs.
3209 Recalculate the number not at initial offset.
3211 Compute the maximum offset (minimum offset if the stack does not
3212 grow downward) for each elimination pair. */
3215 update_eliminable_offsets (void)
3217 struct elim_table
*ep
;
3219 num_not_at_initial_offset
= 0;
3220 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3222 ep
->previous_offset
= ep
->offset
;
3223 if (ep
->can_eliminate
&& ep
->offset
!= ep
->initial_offset
)
3224 num_not_at_initial_offset
++;
3228 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3229 replacement we currently believe is valid, mark it as not eliminable if X
3230 modifies DEST in any way other than by adding a constant integer to it.
3232 If DEST is the frame pointer, we do nothing because we assume that
3233 all assignments to the hard frame pointer are nonlocal gotos and are being
3234 done at a time when they are valid and do not disturb anything else.
3235 Some machines want to eliminate a fake argument pointer with either the
3236 frame or stack pointer. Assignments to the hard frame pointer must not
3237 prevent this elimination.
3239 Called via note_stores from reload before starting its passes to scan
3240 the insns of the function. */
3243 mark_not_eliminable (rtx dest
, rtx x
, void *data ATTRIBUTE_UNUSED
)
3247 /* A SUBREG of a hard register here is just changing its mode. We should
3248 not see a SUBREG of an eliminable hard register, but check just in
3250 if (GET_CODE (dest
) == SUBREG
)
3251 dest
= SUBREG_REG (dest
);
3253 if (dest
== hard_frame_pointer_rtx
)
3256 for (i
= 0; i
< NUM_ELIMINABLE_REGS
; i
++)
3257 if (reg_eliminate
[i
].can_eliminate
&& dest
== reg_eliminate
[i
].to_rtx
3258 && (GET_CODE (x
) != SET
3259 || GET_CODE (SET_SRC (x
)) != PLUS
3260 || XEXP (SET_SRC (x
), 0) != dest
3261 || GET_CODE (XEXP (SET_SRC (x
), 1)) != CONST_INT
))
3263 reg_eliminate
[i
].can_eliminate_previous
3264 = reg_eliminate
[i
].can_eliminate
= 0;
3269 /* Verify that the initial elimination offsets did not change since the
3270 last call to set_initial_elim_offsets. This is used to catch cases
3271 where something illegal happened during reload_as_needed that could
3272 cause incorrect code to be generated if we did not check for it. */
3275 verify_initial_elim_offsets (void)
3279 #ifdef ELIMINABLE_REGS
3280 struct elim_table
*ep
;
3282 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3284 INITIAL_ELIMINATION_OFFSET (ep
->from
, ep
->to
, t
);
3285 if (t
!= ep
->initial_offset
)
3289 INITIAL_FRAME_POINTER_OFFSET (t
);
3290 if (t
!= reg_eliminate
[0].initial_offset
)
3295 /* Reset all offsets on eliminable registers to their initial values. */
3298 set_initial_elim_offsets (void)
3300 struct elim_table
*ep
= reg_eliminate
;
3302 #ifdef ELIMINABLE_REGS
3303 for (; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3305 INITIAL_ELIMINATION_OFFSET (ep
->from
, ep
->to
, ep
->initial_offset
);
3306 ep
->previous_offset
= ep
->offset
= ep
->initial_offset
;
3309 INITIAL_FRAME_POINTER_OFFSET (ep
->initial_offset
);
3310 ep
->previous_offset
= ep
->offset
= ep
->initial_offset
;
3313 num_not_at_initial_offset
= 0;
3316 /* Initialize the known label offsets.
3317 Set a known offset for each forced label to be at the initial offset
3318 of each elimination. We do this because we assume that all
3319 computed jumps occur from a location where each elimination is
3320 at its initial offset.
3321 For all other labels, show that we don't know the offsets. */
3324 set_initial_label_offsets (void)
3327 memset (offsets_known_at
, 0, num_labels
);
3329 for (x
= forced_labels
; x
; x
= XEXP (x
, 1))
3331 set_label_offsets (XEXP (x
, 0), NULL_RTX
, 1);
3334 /* Set all elimination offsets to the known values for the code label given
3338 set_offsets_for_label (rtx insn
)
3341 int label_nr
= CODE_LABEL_NUMBER (insn
);
3342 struct elim_table
*ep
;
3344 num_not_at_initial_offset
= 0;
3345 for (i
= 0, ep
= reg_eliminate
; i
< NUM_ELIMINABLE_REGS
; ep
++, i
++)
3347 ep
->offset
= ep
->previous_offset
3348 = offsets_at
[label_nr
- first_label_num
][i
];
3349 if (ep
->can_eliminate
&& ep
->offset
!= ep
->initial_offset
)
3350 num_not_at_initial_offset
++;
3354 /* See if anything that happened changes which eliminations are valid.
3355 For example, on the SPARC, whether or not the frame pointer can
3356 be eliminated can depend on what registers have been used. We need
3357 not check some conditions again (such as flag_omit_frame_pointer)
3358 since they can't have changed. */
3361 update_eliminables (HARD_REG_SET
*pset
)
3363 int previous_frame_pointer_needed
= frame_pointer_needed
;
3364 struct elim_table
*ep
;
3366 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3367 if ((ep
->from
== HARD_FRAME_POINTER_REGNUM
&& FRAME_POINTER_REQUIRED
)
3368 #ifdef ELIMINABLE_REGS
3369 || ! CAN_ELIMINATE (ep
->from
, ep
->to
)
3372 ep
->can_eliminate
= 0;
3374 /* Look for the case where we have discovered that we can't replace
3375 register A with register B and that means that we will now be
3376 trying to replace register A with register C. This means we can
3377 no longer replace register C with register B and we need to disable
3378 such an elimination, if it exists. This occurs often with A == ap,
3379 B == sp, and C == fp. */
3381 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3383 struct elim_table
*op
;
3386 if (! ep
->can_eliminate
&& ep
->can_eliminate_previous
)
3388 /* Find the current elimination for ep->from, if there is a
3390 for (op
= reg_eliminate
;
3391 op
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; op
++)
3392 if (op
->from
== ep
->from
&& op
->can_eliminate
)
3398 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
3400 for (op
= reg_eliminate
;
3401 op
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; op
++)
3402 if (op
->from
== new_to
&& op
->to
== ep
->to
)
3403 op
->can_eliminate
= 0;
3407 /* See if any registers that we thought we could eliminate the previous
3408 time are no longer eliminable. If so, something has changed and we
3409 must spill the register. Also, recompute the number of eliminable
3410 registers and see if the frame pointer is needed; it is if there is
3411 no elimination of the frame pointer that we can perform. */
3413 frame_pointer_needed
= 1;
3414 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3416 if (ep
->can_eliminate
&& ep
->from
== FRAME_POINTER_REGNUM
3417 && ep
->to
!= HARD_FRAME_POINTER_REGNUM
)
3418 frame_pointer_needed
= 0;
3420 if (! ep
->can_eliminate
&& ep
->can_eliminate_previous
)
3422 ep
->can_eliminate_previous
= 0;
3423 SET_HARD_REG_BIT (*pset
, ep
->from
);
3428 /* If we didn't need a frame pointer last time, but we do now, spill
3429 the hard frame pointer. */
3430 if (frame_pointer_needed
&& ! previous_frame_pointer_needed
)
3431 SET_HARD_REG_BIT (*pset
, HARD_FRAME_POINTER_REGNUM
);
3434 /* Initialize the table of registers to eliminate. */
3437 init_elim_table (void)
3439 struct elim_table
*ep
;
3440 #ifdef ELIMINABLE_REGS
3441 const struct elim_table_1
*ep1
;
3445 reg_eliminate
= xcalloc (sizeof (struct elim_table
), NUM_ELIMINABLE_REGS
);
3447 /* Does this function require a frame pointer? */
3449 frame_pointer_needed
= (! flag_omit_frame_pointer
3450 #ifdef EXIT_IGNORE_STACK
3451 /* ?? If EXIT_IGNORE_STACK is set, we will not save
3452 and restore sp for alloca. So we can't eliminate
3453 the frame pointer in that case. At some point,
3454 we should improve this by emitting the
3455 sp-adjusting insns for this case. */
3456 || (current_function_calls_alloca
3457 && EXIT_IGNORE_STACK
)
3459 || FRAME_POINTER_REQUIRED
);
3463 #ifdef ELIMINABLE_REGS
3464 for (ep
= reg_eliminate
, ep1
= reg_eliminate_1
;
3465 ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++, ep1
++)
3467 ep
->from
= ep1
->from
;
3469 ep
->can_eliminate
= ep
->can_eliminate_previous
3470 = (CAN_ELIMINATE (ep
->from
, ep
->to
)
3471 && ! (ep
->to
== STACK_POINTER_REGNUM
&& frame_pointer_needed
));
3474 reg_eliminate
[0].from
= reg_eliminate_1
[0].from
;
3475 reg_eliminate
[0].to
= reg_eliminate_1
[0].to
;
3476 reg_eliminate
[0].can_eliminate
= reg_eliminate
[0].can_eliminate_previous
3477 = ! frame_pointer_needed
;
3480 /* Count the number of eliminable registers and build the FROM and TO
3481 REG rtx's. Note that code in gen_rtx will cause, e.g.,
3482 gen_rtx (REG, Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
3483 We depend on this. */
3484 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3486 num_eliminable
+= ep
->can_eliminate
;
3487 ep
->from_rtx
= gen_rtx_REG (Pmode
, ep
->from
);
3488 ep
->to_rtx
= gen_rtx_REG (Pmode
, ep
->to
);
3492 /* Kick all pseudos out of hard register REGNO.
3494 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
3495 because we found we can't eliminate some register. In the case, no pseudos
3496 are allowed to be in the register, even if they are only in a block that
3497 doesn't require spill registers, unlike the case when we are spilling this
3498 hard reg to produce another spill register.
3500 Return nonzero if any pseudos needed to be kicked out. */
3503 spill_hard_reg (unsigned int regno
, int cant_eliminate
)
3509 SET_HARD_REG_BIT (bad_spill_regs_global
, regno
);
3510 regs_ever_live
[regno
] = 1;
3513 /* Spill every pseudo reg that was allocated to this reg
3514 or to something that overlaps this reg. */
3516 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
3517 if (reg_renumber
[i
] >= 0
3518 && (unsigned int) reg_renumber
[i
] <= regno
3519 && ((unsigned int) reg_renumber
[i
]
3520 + HARD_REGNO_NREGS ((unsigned int) reg_renumber
[i
],
3521 PSEUDO_REGNO_MODE (i
))
3523 SET_REGNO_REG_SET (&spilled_pseudos
, i
);
3526 /* I'm getting weird preprocessor errors if I use IOR_HARD_REG_SET
3527 from within EXECUTE_IF_SET_IN_REG_SET. Hence this awkwardness. */
3530 ior_hard_reg_set (HARD_REG_SET
*set1
, HARD_REG_SET
*set2
)
3532 IOR_HARD_REG_SET (*set1
, *set2
);
3535 /* After find_reload_regs has been run for all insn that need reloads,
3536 and/or spill_hard_regs was called, this function is used to actually
3537 spill pseudo registers and try to reallocate them. It also sets up the
3538 spill_regs array for use by choose_reload_regs. */
3541 finish_spills (int global
)
3543 struct insn_chain
*chain
;
3544 int something_changed
= 0;
3547 /* Build the spill_regs array for the function. */
3548 /* If there are some registers still to eliminate and one of the spill regs
3549 wasn't ever used before, additional stack space may have to be
3550 allocated to store this register. Thus, we may have changed the offset
3551 between the stack and frame pointers, so mark that something has changed.
3553 One might think that we need only set VAL to 1 if this is a call-used
3554 register. However, the set of registers that must be saved by the
3555 prologue is not identical to the call-used set. For example, the
3556 register used by the call insn for the return PC is a call-used register,
3557 but must be saved by the prologue. */
3560 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
3561 if (TEST_HARD_REG_BIT (used_spill_regs
, i
))
3563 spill_reg_order
[i
] = n_spills
;
3564 spill_regs
[n_spills
++] = i
;
3565 if (num_eliminable
&& ! regs_ever_live
[i
])
3566 something_changed
= 1;
3567 regs_ever_live
[i
] = 1;
3570 spill_reg_order
[i
] = -1;
3572 EXECUTE_IF_SET_IN_REG_SET
3573 (&spilled_pseudos
, FIRST_PSEUDO_REGISTER
, i
,
3575 /* Record the current hard register the pseudo is allocated to in
3576 pseudo_previous_regs so we avoid reallocating it to the same
3577 hard reg in a later pass. */
3578 if (reg_renumber
[i
] < 0)
3581 SET_HARD_REG_BIT (pseudo_previous_regs
[i
], reg_renumber
[i
]);
3582 /* Mark it as no longer having a hard register home. */
3583 reg_renumber
[i
] = -1;
3584 /* We will need to scan everything again. */
3585 something_changed
= 1;
3588 /* Retry global register allocation if possible. */
3591 memset (pseudo_forbidden_regs
, 0, max_regno
* sizeof (HARD_REG_SET
));
3592 /* For every insn that needs reloads, set the registers used as spill
3593 regs in pseudo_forbidden_regs for every pseudo live across the
3595 for (chain
= insns_need_reload
; chain
; chain
= chain
->next_need_reload
)
3597 EXECUTE_IF_SET_IN_REG_SET
3598 (&chain
->live_throughout
, FIRST_PSEUDO_REGISTER
, i
,
3600 ior_hard_reg_set (pseudo_forbidden_regs
+ i
,
3601 &chain
->used_spill_regs
);
3603 EXECUTE_IF_SET_IN_REG_SET
3604 (&chain
->dead_or_set
, FIRST_PSEUDO_REGISTER
, i
,
3606 ior_hard_reg_set (pseudo_forbidden_regs
+ i
,
3607 &chain
->used_spill_regs
);
3611 /* Retry allocating the spilled pseudos. For each reg, merge the
3612 various reg sets that indicate which hard regs can't be used,
3613 and call retry_global_alloc.
3614 We change spill_pseudos here to only contain pseudos that did not
3615 get a new hard register. */
3616 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
3617 if (reg_old_renumber
[i
] != reg_renumber
[i
])
3619 HARD_REG_SET forbidden
;
3620 COPY_HARD_REG_SET (forbidden
, bad_spill_regs_global
);
3621 IOR_HARD_REG_SET (forbidden
, pseudo_forbidden_regs
[i
]);
3622 IOR_HARD_REG_SET (forbidden
, pseudo_previous_regs
[i
]);
3623 retry_global_alloc (i
, forbidden
);
3624 if (reg_renumber
[i
] >= 0)
3625 CLEAR_REGNO_REG_SET (&spilled_pseudos
, i
);
3629 /* Fix up the register information in the insn chain.
3630 This involves deleting those of the spilled pseudos which did not get
3631 a new hard register home from the live_{before,after} sets. */
3632 for (chain
= reload_insn_chain
; chain
; chain
= chain
->next
)
3634 HARD_REG_SET used_by_pseudos
;
3635 HARD_REG_SET used_by_pseudos2
;
3637 AND_COMPL_REG_SET (&chain
->live_throughout
, &spilled_pseudos
);
3638 AND_COMPL_REG_SET (&chain
->dead_or_set
, &spilled_pseudos
);
3640 /* Mark any unallocated hard regs as available for spills. That
3641 makes inheritance work somewhat better. */
3642 if (chain
->need_reload
)
3644 REG_SET_TO_HARD_REG_SET (used_by_pseudos
, &chain
->live_throughout
);
3645 REG_SET_TO_HARD_REG_SET (used_by_pseudos2
, &chain
->dead_or_set
);
3646 IOR_HARD_REG_SET (used_by_pseudos
, used_by_pseudos2
);
3648 /* Save the old value for the sanity test below. */
3649 COPY_HARD_REG_SET (used_by_pseudos2
, chain
->used_spill_regs
);
3651 compute_use_by_pseudos (&used_by_pseudos
, &chain
->live_throughout
);
3652 compute_use_by_pseudos (&used_by_pseudos
, &chain
->dead_or_set
);
3653 COMPL_HARD_REG_SET (chain
->used_spill_regs
, used_by_pseudos
);
3654 AND_HARD_REG_SET (chain
->used_spill_regs
, used_spill_regs
);
3656 /* Make sure we only enlarge the set. */
3657 GO_IF_HARD_REG_SUBSET (used_by_pseudos2
, chain
->used_spill_regs
, ok
);
3663 /* Let alter_reg modify the reg rtx's for the modified pseudos. */
3664 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
3666 int regno
= reg_renumber
[i
];
3667 if (reg_old_renumber
[i
] == regno
)
3670 alter_reg (i
, reg_old_renumber
[i
]);
3671 reg_old_renumber
[i
] = regno
;
3675 fprintf (rtl_dump_file
, " Register %d now on stack.\n\n", i
);
3677 fprintf (rtl_dump_file
, " Register %d now in %d.\n\n",
3678 i
, reg_renumber
[i
]);
3682 return something_changed
;
3685 /* Find all paradoxical subregs within X and update reg_max_ref_width.
3686 Also mark any hard registers used to store user variables as
3687 forbidden from being used for spill registers. */
3690 scan_paradoxical_subregs (rtx x
)
3694 enum rtx_code code
= GET_CODE (x
);
3700 if (SMALL_REGISTER_CLASSES
&& REGNO (x
) < FIRST_PSEUDO_REGISTER
3701 && REG_USERVAR_P (x
))
3702 SET_HARD_REG_BIT (bad_spill_regs_global
, REGNO (x
));
3711 case CONST_VECTOR
: /* shouldn't happen, but just in case. */
3719 if (GET_CODE (SUBREG_REG (x
)) == REG
3720 && GET_MODE_SIZE (GET_MODE (x
)) > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
3721 reg_max_ref_width
[REGNO (SUBREG_REG (x
))]
3722 = GET_MODE_SIZE (GET_MODE (x
));
3729 fmt
= GET_RTX_FORMAT (code
);
3730 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
3733 scan_paradoxical_subregs (XEXP (x
, i
));
3734 else if (fmt
[i
] == 'E')
3737 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3738 scan_paradoxical_subregs (XVECEXP (x
, i
, j
));
3743 /* Reload pseudo-registers into hard regs around each insn as needed.
3744 Additional register load insns are output before the insn that needs it
3745 and perhaps store insns after insns that modify the reloaded pseudo reg.
3747 reg_last_reload_reg and reg_reloaded_contents keep track of
3748 which registers are already available in reload registers.
3749 We update these for the reloads that we perform,
3750 as the insns are scanned. */
3753 reload_as_needed (int live_known
)
3755 struct insn_chain
*chain
;
3756 #if defined (AUTO_INC_DEC)
3761 memset (spill_reg_rtx
, 0, sizeof spill_reg_rtx
);
3762 memset (spill_reg_store
, 0, sizeof spill_reg_store
);
3763 reg_last_reload_reg
= xcalloc (max_regno
, sizeof (rtx
));
3764 reg_has_output_reload
= xmalloc (max_regno
);
3765 CLEAR_HARD_REG_SET (reg_reloaded_valid
);
3767 set_initial_elim_offsets ();
3769 for (chain
= reload_insn_chain
; chain
; chain
= chain
->next
)
3772 rtx insn
= chain
->insn
;
3773 rtx old_next
= NEXT_INSN (insn
);
3775 /* If we pass a label, copy the offsets from the label information
3776 into the current offsets of each elimination. */
3777 if (GET_CODE (insn
) == CODE_LABEL
)
3778 set_offsets_for_label (insn
);
3780 else if (INSN_P (insn
))
3782 rtx oldpat
= copy_rtx (PATTERN (insn
));
3784 /* If this is a USE and CLOBBER of a MEM, ensure that any
3785 references to eliminable registers have been removed. */
3787 if ((GET_CODE (PATTERN (insn
)) == USE
3788 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
3789 && GET_CODE (XEXP (PATTERN (insn
), 0)) == MEM
)
3790 XEXP (XEXP (PATTERN (insn
), 0), 0)
3791 = eliminate_regs (XEXP (XEXP (PATTERN (insn
), 0), 0),
3792 GET_MODE (XEXP (PATTERN (insn
), 0)),
3795 /* If we need to do register elimination processing, do so.
3796 This might delete the insn, in which case we are done. */
3797 if ((num_eliminable
|| num_eliminable_invariants
) && chain
->need_elim
)
3799 eliminate_regs_in_insn (insn
, 1);
3800 if (GET_CODE (insn
) == NOTE
)
3802 update_eliminable_offsets ();
3807 /* If need_elim is nonzero but need_reload is zero, one might think
3808 that we could simply set n_reloads to 0. However, find_reloads
3809 could have done some manipulation of the insn (such as swapping
3810 commutative operands), and these manipulations are lost during
3811 the first pass for every insn that needs register elimination.
3812 So the actions of find_reloads must be redone here. */
3814 if (! chain
->need_elim
&& ! chain
->need_reload
3815 && ! chain
->need_operand_change
)
3817 /* First find the pseudo regs that must be reloaded for this insn.
3818 This info is returned in the tables reload_... (see reload.h).
3819 Also modify the body of INSN by substituting RELOAD
3820 rtx's for those pseudo regs. */
3823 memset (reg_has_output_reload
, 0, max_regno
);
3824 CLEAR_HARD_REG_SET (reg_is_output_reload
);
3826 find_reloads (insn
, 1, spill_indirect_levels
, live_known
,
3832 rtx next
= NEXT_INSN (insn
);
3835 prev
= PREV_INSN (insn
);
3837 /* Now compute which reload regs to reload them into. Perhaps
3838 reusing reload regs from previous insns, or else output
3839 load insns to reload them. Maybe output store insns too.
3840 Record the choices of reload reg in reload_reg_rtx. */
3841 choose_reload_regs (chain
);
3843 /* Merge any reloads that we didn't combine for fear of
3844 increasing the number of spill registers needed but now
3845 discover can be safely merged. */
3846 if (SMALL_REGISTER_CLASSES
)
3847 merge_assigned_reloads (insn
);
3849 /* Generate the insns to reload operands into or out of
3850 their reload regs. */
3851 emit_reload_insns (chain
);
3853 /* Substitute the chosen reload regs from reload_reg_rtx
3854 into the insn's body (or perhaps into the bodies of other
3855 load and store insn that we just made for reloading
3856 and that we moved the structure into). */
3857 subst_reloads (insn
);
3859 /* If this was an ASM, make sure that all the reload insns
3860 we have generated are valid. If not, give an error
3863 if (asm_noperands (PATTERN (insn
)) >= 0)
3864 for (p
= NEXT_INSN (prev
); p
!= next
; p
= NEXT_INSN (p
))
3865 if (p
!= insn
&& INSN_P (p
)
3866 && GET_CODE (PATTERN (p
)) != USE
3867 && (recog_memoized (p
) < 0
3868 || (extract_insn (p
), ! constrain_operands (1))))
3870 error_for_asm (insn
,
3871 "`asm' operand requires impossible reload");
3876 if (num_eliminable
&& chain
->need_elim
)
3877 update_eliminable_offsets ();
3879 /* Any previously reloaded spilled pseudo reg, stored in this insn,
3880 is no longer validly lying around to save a future reload.
3881 Note that this does not detect pseudos that were reloaded
3882 for this insn in order to be stored in
3883 (obeying register constraints). That is correct; such reload
3884 registers ARE still valid. */
3885 note_stores (oldpat
, forget_old_reloads_1
, NULL
);
3887 /* There may have been CLOBBER insns placed after INSN. So scan
3888 between INSN and NEXT and use them to forget old reloads. */
3889 for (x
= NEXT_INSN (insn
); x
!= old_next
; x
= NEXT_INSN (x
))
3890 if (GET_CODE (x
) == INSN
&& GET_CODE (PATTERN (x
)) == CLOBBER
)
3891 note_stores (PATTERN (x
), forget_old_reloads_1
, NULL
);
3894 /* Likewise for regs altered by auto-increment in this insn.
3895 REG_INC notes have been changed by reloading:
3896 find_reloads_address_1 records substitutions for them,
3897 which have been performed by subst_reloads above. */
3898 for (i
= n_reloads
- 1; i
>= 0; i
--)
3900 rtx in_reg
= rld
[i
].in_reg
;
3903 enum rtx_code code
= GET_CODE (in_reg
);
3904 /* PRE_INC / PRE_DEC will have the reload register ending up
3905 with the same value as the stack slot, but that doesn't
3906 hold true for POST_INC / POST_DEC. Either we have to
3907 convert the memory access to a true POST_INC / POST_DEC,
3908 or we can't use the reload register for inheritance. */
3909 if ((code
== POST_INC
|| code
== POST_DEC
)
3910 && TEST_HARD_REG_BIT (reg_reloaded_valid
,
3911 REGNO (rld
[i
].reg_rtx
))
3912 /* Make sure it is the inc/dec pseudo, and not
3913 some other (e.g. output operand) pseudo. */
3914 && ((unsigned) reg_reloaded_contents
[REGNO (rld
[i
].reg_rtx
)]
3915 == REGNO (XEXP (in_reg
, 0))))
3918 rtx reload_reg
= rld
[i
].reg_rtx
;
3919 enum machine_mode mode
= GET_MODE (reload_reg
);
3923 for (p
= PREV_INSN (old_next
); p
!= prev
; p
= PREV_INSN (p
))
3925 /* We really want to ignore REG_INC notes here, so
3926 use PATTERN (p) as argument to reg_set_p . */
3927 if (reg_set_p (reload_reg
, PATTERN (p
)))
3929 n
= count_occurrences (PATTERN (p
), reload_reg
, 0);
3934 n
= validate_replace_rtx (reload_reg
,
3935 gen_rtx (code
, mode
,
3939 /* We must also verify that the constraints
3940 are met after the replacement. */
3943 n
= constrain_operands (1);
3947 /* If the constraints were not met, then
3948 undo the replacement. */
3951 validate_replace_rtx (gen_rtx (code
, mode
,
3963 = gen_rtx_EXPR_LIST (REG_INC
, reload_reg
,
3965 /* Mark this as having an output reload so that the
3966 REG_INC processing code below won't invalidate
3967 the reload for inheritance. */
3968 SET_HARD_REG_BIT (reg_is_output_reload
,
3969 REGNO (reload_reg
));
3970 reg_has_output_reload
[REGNO (XEXP (in_reg
, 0))] = 1;
3973 forget_old_reloads_1 (XEXP (in_reg
, 0), NULL_RTX
,
3976 else if ((code
== PRE_INC
|| code
== PRE_DEC
)
3977 && TEST_HARD_REG_BIT (reg_reloaded_valid
,
3978 REGNO (rld
[i
].reg_rtx
))
3979 /* Make sure it is the inc/dec pseudo, and not
3980 some other (e.g. output operand) pseudo. */
3981 && ((unsigned) reg_reloaded_contents
[REGNO (rld
[i
].reg_rtx
)]
3982 == REGNO (XEXP (in_reg
, 0))))
3984 SET_HARD_REG_BIT (reg_is_output_reload
,
3985 REGNO (rld
[i
].reg_rtx
));
3986 reg_has_output_reload
[REGNO (XEXP (in_reg
, 0))] = 1;
3990 /* If a pseudo that got a hard register is auto-incremented,
3991 we must purge records of copying it into pseudos without
3993 for (x
= REG_NOTES (insn
); x
; x
= XEXP (x
, 1))
3994 if (REG_NOTE_KIND (x
) == REG_INC
)
3996 /* See if this pseudo reg was reloaded in this insn.
3997 If so, its last-reload info is still valid
3998 because it is based on this insn's reload. */
3999 for (i
= 0; i
< n_reloads
; i
++)
4000 if (rld
[i
].out
== XEXP (x
, 0))
4004 forget_old_reloads_1 (XEXP (x
, 0), NULL_RTX
, NULL
);
4008 /* A reload reg's contents are unknown after a label. */
4009 if (GET_CODE (insn
) == CODE_LABEL
)
4010 CLEAR_HARD_REG_SET (reg_reloaded_valid
);
4012 /* Don't assume a reload reg is still good after a call insn
4013 if it is a call-used reg. */
4014 else if (GET_CODE (insn
) == CALL_INSN
)
4015 AND_COMPL_HARD_REG_SET (reg_reloaded_valid
, call_used_reg_set
);
4019 free (reg_last_reload_reg
);
4020 free (reg_has_output_reload
);
4023 /* Discard all record of any value reloaded from X,
4024 or reloaded in X from someplace else;
4025 unless X is an output reload reg of the current insn.
4027 X may be a hard reg (the reload reg)
4028 or it may be a pseudo reg that was reloaded from. */
4031 forget_old_reloads_1 (rtx x
, rtx ignored ATTRIBUTE_UNUSED
,
4032 void *data ATTRIBUTE_UNUSED
)
4037 /* note_stores does give us subregs of hard regs,
4038 subreg_regno_offset will abort if it is not a hard reg. */
4039 while (GET_CODE (x
) == SUBREG
)
4041 /* We ignore the subreg offset when calculating the regno,
4042 because we are using the entire underlying hard register
4047 if (GET_CODE (x
) != REG
)
4052 if (regno
>= FIRST_PSEUDO_REGISTER
)
4058 nr
= HARD_REGNO_NREGS (regno
, GET_MODE (x
));
4059 /* Storing into a spilled-reg invalidates its contents.
4060 This can happen if a block-local pseudo is allocated to that reg
4061 and it wasn't spilled because this block's total need is 0.
4062 Then some insn might have an optional reload and use this reg. */
4063 for (i
= 0; i
< nr
; i
++)
4064 /* But don't do this if the reg actually serves as an output
4065 reload reg in the current instruction. */
4067 || ! TEST_HARD_REG_BIT (reg_is_output_reload
, regno
+ i
))
4069 CLEAR_HARD_REG_BIT (reg_reloaded_valid
, regno
+ i
);
4070 spill_reg_store
[regno
+ i
] = 0;
4074 /* Since value of X has changed,
4075 forget any value previously copied from it. */
4078 /* But don't forget a copy if this is the output reload
4079 that establishes the copy's validity. */
4080 if (n_reloads
== 0 || reg_has_output_reload
[regno
+ nr
] == 0)
4081 reg_last_reload_reg
[regno
+ nr
] = 0;
4084 /* The following HARD_REG_SETs indicate when each hard register is
4085 used for a reload of various parts of the current insn. */
4087 /* If reg is unavailable for all reloads. */
4088 static HARD_REG_SET reload_reg_unavailable
;
4089 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
4090 static HARD_REG_SET reload_reg_used
;
4091 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
4092 static HARD_REG_SET reload_reg_used_in_input_addr
[MAX_RECOG_OPERANDS
];
4093 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */
4094 static HARD_REG_SET reload_reg_used_in_inpaddr_addr
[MAX_RECOG_OPERANDS
];
4095 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
4096 static HARD_REG_SET reload_reg_used_in_output_addr
[MAX_RECOG_OPERANDS
];
4097 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */
4098 static HARD_REG_SET reload_reg_used_in_outaddr_addr
[MAX_RECOG_OPERANDS
];
4099 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
4100 static HARD_REG_SET reload_reg_used_in_input
[MAX_RECOG_OPERANDS
];
4101 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
4102 static HARD_REG_SET reload_reg_used_in_output
[MAX_RECOG_OPERANDS
];
4103 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
4104 static HARD_REG_SET reload_reg_used_in_op_addr
;
4105 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */
4106 static HARD_REG_SET reload_reg_used_in_op_addr_reload
;
4107 /* If reg is in use for a RELOAD_FOR_INSN reload. */
4108 static HARD_REG_SET reload_reg_used_in_insn
;
4109 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
4110 static HARD_REG_SET reload_reg_used_in_other_addr
;
4112 /* If reg is in use as a reload reg for any sort of reload. */
4113 static HARD_REG_SET reload_reg_used_at_all
;
4115 /* If reg is use as an inherited reload. We just mark the first register
4117 static HARD_REG_SET reload_reg_used_for_inherit
;
4119 /* Records which hard regs are used in any way, either as explicit use or
4120 by being allocated to a pseudo during any point of the current insn. */
4121 static HARD_REG_SET reg_used_in_insn
;
4123 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
4124 TYPE. MODE is used to indicate how many consecutive regs are
4128 mark_reload_reg_in_use (unsigned int regno
, int opnum
, enum reload_type type
,
4129 enum machine_mode mode
)
4131 unsigned int nregs
= HARD_REGNO_NREGS (regno
, mode
);
4134 for (i
= regno
; i
< nregs
+ regno
; i
++)
4139 SET_HARD_REG_BIT (reload_reg_used
, i
);
4142 case RELOAD_FOR_INPUT_ADDRESS
:
4143 SET_HARD_REG_BIT (reload_reg_used_in_input_addr
[opnum
], i
);
4146 case RELOAD_FOR_INPADDR_ADDRESS
:
4147 SET_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[opnum
], i
);
4150 case RELOAD_FOR_OUTPUT_ADDRESS
:
4151 SET_HARD_REG_BIT (reload_reg_used_in_output_addr
[opnum
], i
);
4154 case RELOAD_FOR_OUTADDR_ADDRESS
:
4155 SET_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[opnum
], i
);
4158 case RELOAD_FOR_OPERAND_ADDRESS
:
4159 SET_HARD_REG_BIT (reload_reg_used_in_op_addr
, i
);
4162 case RELOAD_FOR_OPADDR_ADDR
:
4163 SET_HARD_REG_BIT (reload_reg_used_in_op_addr_reload
, i
);
4166 case RELOAD_FOR_OTHER_ADDRESS
:
4167 SET_HARD_REG_BIT (reload_reg_used_in_other_addr
, i
);
4170 case RELOAD_FOR_INPUT
:
4171 SET_HARD_REG_BIT (reload_reg_used_in_input
[opnum
], i
);
4174 case RELOAD_FOR_OUTPUT
:
4175 SET_HARD_REG_BIT (reload_reg_used_in_output
[opnum
], i
);
4178 case RELOAD_FOR_INSN
:
4179 SET_HARD_REG_BIT (reload_reg_used_in_insn
, i
);
4183 SET_HARD_REG_BIT (reload_reg_used_at_all
, i
);
4187 /* Similarly, but show REGNO is no longer in use for a reload. */
4190 clear_reload_reg_in_use (unsigned int regno
, int opnum
,
4191 enum reload_type type
, enum machine_mode mode
)
4193 unsigned int nregs
= HARD_REGNO_NREGS (regno
, mode
);
4194 unsigned int start_regno
, end_regno
, r
;
4196 /* A complication is that for some reload types, inheritance might
4197 allow multiple reloads of the same types to share a reload register.
4198 We set check_opnum if we have to check only reloads with the same
4199 operand number, and check_any if we have to check all reloads. */
4200 int check_opnum
= 0;
4202 HARD_REG_SET
*used_in_set
;
4207 used_in_set
= &reload_reg_used
;
4210 case RELOAD_FOR_INPUT_ADDRESS
:
4211 used_in_set
= &reload_reg_used_in_input_addr
[opnum
];
4214 case RELOAD_FOR_INPADDR_ADDRESS
:
4216 used_in_set
= &reload_reg_used_in_inpaddr_addr
[opnum
];
4219 case RELOAD_FOR_OUTPUT_ADDRESS
:
4220 used_in_set
= &reload_reg_used_in_output_addr
[opnum
];
4223 case RELOAD_FOR_OUTADDR_ADDRESS
:
4225 used_in_set
= &reload_reg_used_in_outaddr_addr
[opnum
];
4228 case RELOAD_FOR_OPERAND_ADDRESS
:
4229 used_in_set
= &reload_reg_used_in_op_addr
;
4232 case RELOAD_FOR_OPADDR_ADDR
:
4234 used_in_set
= &reload_reg_used_in_op_addr_reload
;
4237 case RELOAD_FOR_OTHER_ADDRESS
:
4238 used_in_set
= &reload_reg_used_in_other_addr
;
4242 case RELOAD_FOR_INPUT
:
4243 used_in_set
= &reload_reg_used_in_input
[opnum
];
4246 case RELOAD_FOR_OUTPUT
:
4247 used_in_set
= &reload_reg_used_in_output
[opnum
];
4250 case RELOAD_FOR_INSN
:
4251 used_in_set
= &reload_reg_used_in_insn
;
4256 /* We resolve conflicts with remaining reloads of the same type by
4257 excluding the intervals of reload registers by them from the
4258 interval of freed reload registers. Since we only keep track of
4259 one set of interval bounds, we might have to exclude somewhat
4260 more than what would be necessary if we used a HARD_REG_SET here.
4261 But this should only happen very infrequently, so there should
4262 be no reason to worry about it. */
4264 start_regno
= regno
;
4265 end_regno
= regno
+ nregs
;
4266 if (check_opnum
|| check_any
)
4268 for (i
= n_reloads
- 1; i
>= 0; i
--)
4270 if (rld
[i
].when_needed
== type
4271 && (check_any
|| rld
[i
].opnum
== opnum
)
4274 unsigned int conflict_start
= true_regnum (rld
[i
].reg_rtx
);
4275 unsigned int conflict_end
4277 + HARD_REGNO_NREGS (conflict_start
, rld
[i
].mode
));
4279 /* If there is an overlap with the first to-be-freed register,
4280 adjust the interval start. */
4281 if (conflict_start
<= start_regno
&& conflict_end
> start_regno
)
4282 start_regno
= conflict_end
;
4283 /* Otherwise, if there is a conflict with one of the other
4284 to-be-freed registers, adjust the interval end. */
4285 if (conflict_start
> start_regno
&& conflict_start
< end_regno
)
4286 end_regno
= conflict_start
;
4291 for (r
= start_regno
; r
< end_regno
; r
++)
4292 CLEAR_HARD_REG_BIT (*used_in_set
, r
);
4295 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
4296 specified by OPNUM and TYPE. */
4299 reload_reg_free_p (unsigned int regno
, int opnum
, enum reload_type type
)
4303 /* In use for a RELOAD_OTHER means it's not available for anything. */
4304 if (TEST_HARD_REG_BIT (reload_reg_used
, regno
)
4305 || TEST_HARD_REG_BIT (reload_reg_unavailable
, regno
))
4311 /* In use for anything means we can't use it for RELOAD_OTHER. */
4312 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr
, regno
)
4313 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
)
4314 || TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
))
4317 for (i
= 0; i
< reload_n_operands
; i
++)
4318 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
4319 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
)
4320 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
4321 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
)
4322 || TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
)
4323 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
4328 case RELOAD_FOR_INPUT
:
4329 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
4330 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
))
4333 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload
, regno
))
4336 /* If it is used for some other input, can't use it. */
4337 for (i
= 0; i
< reload_n_operands
; i
++)
4338 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
4341 /* If it is used in a later operand's address, can't use it. */
4342 for (i
= opnum
+ 1; i
< reload_n_operands
; i
++)
4343 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
4344 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
))
4349 case RELOAD_FOR_INPUT_ADDRESS
:
4350 /* Can't use a register if it is used for an input address for this
4351 operand or used as an input in an earlier one. */
4352 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[opnum
], regno
)
4353 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[opnum
], regno
))
4356 for (i
= 0; i
< opnum
; i
++)
4357 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
4362 case RELOAD_FOR_INPADDR_ADDRESS
:
4363 /* Can't use a register if it is used for an input address
4364 for this operand or used as an input in an earlier
4366 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[opnum
], regno
))
4369 for (i
= 0; i
< opnum
; i
++)
4370 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
4375 case RELOAD_FOR_OUTPUT_ADDRESS
:
4376 /* Can't use a register if it is used for an output address for this
4377 operand or used as an output in this or a later operand. Note
4378 that multiple output operands are emitted in reverse order, so
4379 the conflicting ones are those with lower indices. */
4380 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[opnum
], regno
))
4383 for (i
= 0; i
<= opnum
; i
++)
4384 if (TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
4389 case RELOAD_FOR_OUTADDR_ADDRESS
:
4390 /* Can't use a register if it is used for an output address
4391 for this operand or used as an output in this or a
4392 later operand. Note that multiple output operands are
4393 emitted in reverse order, so the conflicting ones are
4394 those with lower indices. */
4395 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[opnum
], regno
))
4398 for (i
= 0; i
<= opnum
; i
++)
4399 if (TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
4404 case RELOAD_FOR_OPERAND_ADDRESS
:
4405 for (i
= 0; i
< reload_n_operands
; i
++)
4406 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
4409 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
4410 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
));
4412 case RELOAD_FOR_OPADDR_ADDR
:
4413 for (i
= 0; i
< reload_n_operands
; i
++)
4414 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
4417 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload
, regno
));
4419 case RELOAD_FOR_OUTPUT
:
4420 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
4421 outputs, or an operand address for this or an earlier output.
4422 Note that multiple output operands are emitted in reverse order,
4423 so the conflicting ones are those with higher indices. */
4424 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
))
4427 for (i
= 0; i
< reload_n_operands
; i
++)
4428 if (TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
4431 for (i
= opnum
; i
< reload_n_operands
; i
++)
4432 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
4433 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
))
4438 case RELOAD_FOR_INSN
:
4439 for (i
= 0; i
< reload_n_operands
; i
++)
4440 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
)
4441 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
4444 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
4445 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
));
4447 case RELOAD_FOR_OTHER_ADDRESS
:
4448 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr
, regno
);
4453 /* Return 1 if the value in reload reg REGNO, as used by a reload
4454 needed for the part of the insn specified by OPNUM and TYPE,
4455 is still available in REGNO at the end of the insn.
4457 We can assume that the reload reg was already tested for availability
4458 at the time it is needed, and we should not check this again,
4459 in case the reg has already been marked in use. */
4462 reload_reg_reaches_end_p (unsigned int regno
, int opnum
, enum reload_type type
)
4469 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
4470 its value must reach the end. */
4473 /* If this use is for part of the insn,
4474 its value reaches if no subsequent part uses the same register.
4475 Just like the above function, don't try to do this with lots
4478 case RELOAD_FOR_OTHER_ADDRESS
:
4479 /* Here we check for everything else, since these don't conflict
4480 with anything else and everything comes later. */
4482 for (i
= 0; i
< reload_n_operands
; i
++)
4483 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
4484 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
)
4485 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
)
4486 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
4487 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
)
4488 || TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
4491 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
)
4492 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
4493 && ! TEST_HARD_REG_BIT (reload_reg_used
, regno
));
4495 case RELOAD_FOR_INPUT_ADDRESS
:
4496 case RELOAD_FOR_INPADDR_ADDRESS
:
4497 /* Similar, except that we check only for this and subsequent inputs
4498 and the address of only subsequent inputs and we do not need
4499 to check for RELOAD_OTHER objects since they are known not to
4502 for (i
= opnum
; i
< reload_n_operands
; i
++)
4503 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
4506 for (i
= opnum
+ 1; i
< reload_n_operands
; i
++)
4507 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
4508 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
))
4511 for (i
= 0; i
< reload_n_operands
; i
++)
4512 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
4513 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
)
4514 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
4517 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload
, regno
))
4520 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
)
4521 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
4522 && !TEST_HARD_REG_BIT (reload_reg_used
, regno
));
4524 case RELOAD_FOR_INPUT
:
4525 /* Similar to input address, except we start at the next operand for
4526 both input and input address and we do not check for
4527 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
4530 for (i
= opnum
+ 1; i
< reload_n_operands
; i
++)
4531 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
4532 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
)
4533 || TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
4536 /* ... fall through ... */
4538 case RELOAD_FOR_OPERAND_ADDRESS
:
4539 /* Check outputs and their addresses. */
4541 for (i
= 0; i
< reload_n_operands
; i
++)
4542 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
4543 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
)
4544 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
4547 return (!TEST_HARD_REG_BIT (reload_reg_used
, regno
));
4549 case RELOAD_FOR_OPADDR_ADDR
:
4550 for (i
= 0; i
< reload_n_operands
; i
++)
4551 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
4552 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
)
4553 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
4556 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
)
4557 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
4558 && !TEST_HARD_REG_BIT (reload_reg_used
, regno
));
4560 case RELOAD_FOR_INSN
:
4561 /* These conflict with other outputs with RELOAD_OTHER. So
4562 we need only check for output addresses. */
4564 opnum
= reload_n_operands
;
4566 /* ... fall through ... */
4568 case RELOAD_FOR_OUTPUT
:
4569 case RELOAD_FOR_OUTPUT_ADDRESS
:
4570 case RELOAD_FOR_OUTADDR_ADDRESS
:
4571 /* We already know these can't conflict with a later output. So the
4572 only thing to check are later output addresses.
4573 Note that multiple output operands are emitted in reverse order,
4574 so the conflicting ones are those with lower indices. */
4575 for (i
= 0; i
< opnum
; i
++)
4576 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
4577 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
))
4586 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
4589 This function uses the same algorithm as reload_reg_free_p above. */
4592 reloads_conflict (int r1
, int r2
)
4594 enum reload_type r1_type
= rld
[r1
].when_needed
;
4595 enum reload_type r2_type
= rld
[r2
].when_needed
;
4596 int r1_opnum
= rld
[r1
].opnum
;
4597 int r2_opnum
= rld
[r2
].opnum
;
4599 /* RELOAD_OTHER conflicts with everything. */
4600 if (r2_type
== RELOAD_OTHER
)
4603 /* Otherwise, check conflicts differently for each type. */
4607 case RELOAD_FOR_INPUT
:
4608 return (r2_type
== RELOAD_FOR_INSN
4609 || r2_type
== RELOAD_FOR_OPERAND_ADDRESS
4610 || r2_type
== RELOAD_FOR_OPADDR_ADDR
4611 || r2_type
== RELOAD_FOR_INPUT
4612 || ((r2_type
== RELOAD_FOR_INPUT_ADDRESS
4613 || r2_type
== RELOAD_FOR_INPADDR_ADDRESS
)
4614 && r2_opnum
> r1_opnum
));
4616 case RELOAD_FOR_INPUT_ADDRESS
:
4617 return ((r2_type
== RELOAD_FOR_INPUT_ADDRESS
&& r1_opnum
== r2_opnum
)
4618 || (r2_type
== RELOAD_FOR_INPUT
&& r2_opnum
< r1_opnum
));
4620 case RELOAD_FOR_INPADDR_ADDRESS
:
4621 return ((r2_type
== RELOAD_FOR_INPADDR_ADDRESS
&& r1_opnum
== r2_opnum
)
4622 || (r2_type
== RELOAD_FOR_INPUT
&& r2_opnum
< r1_opnum
));
4624 case RELOAD_FOR_OUTPUT_ADDRESS
:
4625 return ((r2_type
== RELOAD_FOR_OUTPUT_ADDRESS
&& r2_opnum
== r1_opnum
)
4626 || (r2_type
== RELOAD_FOR_OUTPUT
&& r2_opnum
<= r1_opnum
));
4628 case RELOAD_FOR_OUTADDR_ADDRESS
:
4629 return ((r2_type
== RELOAD_FOR_OUTADDR_ADDRESS
&& r2_opnum
== r1_opnum
)
4630 || (r2_type
== RELOAD_FOR_OUTPUT
&& r2_opnum
<= r1_opnum
));
4632 case RELOAD_FOR_OPERAND_ADDRESS
:
4633 return (r2_type
== RELOAD_FOR_INPUT
|| r2_type
== RELOAD_FOR_INSN
4634 || r2_type
== RELOAD_FOR_OPERAND_ADDRESS
);
4636 case RELOAD_FOR_OPADDR_ADDR
:
4637 return (r2_type
== RELOAD_FOR_INPUT
4638 || r2_type
== RELOAD_FOR_OPADDR_ADDR
);
4640 case RELOAD_FOR_OUTPUT
:
4641 return (r2_type
== RELOAD_FOR_INSN
|| r2_type
== RELOAD_FOR_OUTPUT
4642 || ((r2_type
== RELOAD_FOR_OUTPUT_ADDRESS
4643 || r2_type
== RELOAD_FOR_OUTADDR_ADDRESS
)
4644 && r2_opnum
>= r1_opnum
));
4646 case RELOAD_FOR_INSN
:
4647 return (r2_type
== RELOAD_FOR_INPUT
|| r2_type
== RELOAD_FOR_OUTPUT
4648 || r2_type
== RELOAD_FOR_INSN
4649 || r2_type
== RELOAD_FOR_OPERAND_ADDRESS
);
4651 case RELOAD_FOR_OTHER_ADDRESS
:
4652 return r2_type
== RELOAD_FOR_OTHER_ADDRESS
;
4662 /* Indexed by reload number, 1 if incoming value
4663 inherited from previous insns. */
4664 char reload_inherited
[MAX_RELOADS
];
4666 /* For an inherited reload, this is the insn the reload was inherited from,
4667 if we know it. Otherwise, this is 0. */
4668 rtx reload_inheritance_insn
[MAX_RELOADS
];
4670 /* If nonzero, this is a place to get the value of the reload,
4671 rather than using reload_in. */
4672 rtx reload_override_in
[MAX_RELOADS
];
4674 /* For each reload, the hard register number of the register used,
4675 or -1 if we did not need a register for this reload. */
4676 int reload_spill_index
[MAX_RELOADS
];
4678 /* Subroutine of free_for_value_p, used to check a single register.
4679 START_REGNO is the starting regno of the full reload register
4680 (possibly comprising multiple hard registers) that we are considering. */
4683 reload_reg_free_for_value_p (int start_regno
, int regno
, int opnum
,
4684 enum reload_type type
, rtx value
, rtx out
,
4685 int reloadnum
, int ignore_address_reloads
)
4688 /* Set if we see an input reload that must not share its reload register
4689 with any new earlyclobber, but might otherwise share the reload
4690 register with an output or input-output reload. */
4691 int check_earlyclobber
= 0;
4695 if (TEST_HARD_REG_BIT (reload_reg_unavailable
, regno
))
4698 if (out
== const0_rtx
)
4704 /* We use some pseudo 'time' value to check if the lifetimes of the
4705 new register use would overlap with the one of a previous reload
4706 that is not read-only or uses a different value.
4707 The 'time' used doesn't have to be linear in any shape or form, just
4709 Some reload types use different 'buckets' for each operand.
4710 So there are MAX_RECOG_OPERANDS different time values for each
4712 We compute TIME1 as the time when the register for the prospective
4713 new reload ceases to be live, and TIME2 for each existing
4714 reload as the time when that the reload register of that reload
4716 Where there is little to be gained by exact lifetime calculations,
4717 we just make conservative assumptions, i.e. a longer lifetime;
4718 this is done in the 'default:' cases. */
4721 case RELOAD_FOR_OTHER_ADDRESS
:
4722 /* RELOAD_FOR_OTHER_ADDRESS conflicts with RELOAD_OTHER reloads. */
4723 time1
= copy
? 0 : 1;
4726 time1
= copy
? 1 : MAX_RECOG_OPERANDS
* 5 + 5;
4728 /* For each input, we may have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
4729 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 ,
4730 respectively, to the time values for these, we get distinct time
4731 values. To get distinct time values for each operand, we have to
4732 multiply opnum by at least three. We round that up to four because
4733 multiply by four is often cheaper. */
4734 case RELOAD_FOR_INPADDR_ADDRESS
:
4735 time1
= opnum
* 4 + 2;
4737 case RELOAD_FOR_INPUT_ADDRESS
:
4738 time1
= opnum
* 4 + 3;
4740 case RELOAD_FOR_INPUT
:
4741 /* All RELOAD_FOR_INPUT reloads remain live till the instruction
4742 executes (inclusive). */
4743 time1
= copy
? opnum
* 4 + 4 : MAX_RECOG_OPERANDS
* 4 + 3;
4745 case RELOAD_FOR_OPADDR_ADDR
:
4747 <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
4748 time1
= MAX_RECOG_OPERANDS
* 4 + 1;
4750 case RELOAD_FOR_OPERAND_ADDRESS
:
4751 /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn
4753 time1
= copy
? MAX_RECOG_OPERANDS
* 4 + 2 : MAX_RECOG_OPERANDS
* 4 + 3;
4755 case RELOAD_FOR_OUTADDR_ADDRESS
:
4756 time1
= MAX_RECOG_OPERANDS
* 4 + 4 + opnum
;
4758 case RELOAD_FOR_OUTPUT_ADDRESS
:
4759 time1
= MAX_RECOG_OPERANDS
* 4 + 5 + opnum
;
4762 time1
= MAX_RECOG_OPERANDS
* 5 + 5;
4765 for (i
= 0; i
< n_reloads
; i
++)
4767 rtx reg
= rld
[i
].reg_rtx
;
4768 if (reg
&& GET_CODE (reg
) == REG
4769 && ((unsigned) regno
- true_regnum (reg
)
4770 <= HARD_REGNO_NREGS (REGNO (reg
), GET_MODE (reg
)) - (unsigned) 1)
4773 rtx other_input
= rld
[i
].in
;
4775 /* If the other reload loads the same input value, that
4776 will not cause a conflict only if it's loading it into
4777 the same register. */
4778 if (true_regnum (reg
) != start_regno
)
4779 other_input
= NULL_RTX
;
4780 if (! other_input
|| ! rtx_equal_p (other_input
, value
)
4781 || rld
[i
].out
|| out
)
4784 switch (rld
[i
].when_needed
)
4786 case RELOAD_FOR_OTHER_ADDRESS
:
4789 case RELOAD_FOR_INPADDR_ADDRESS
:
4790 /* find_reloads makes sure that a
4791 RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used
4792 by at most one - the first -
4793 RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the
4794 address reload is inherited, the address address reload
4795 goes away, so we can ignore this conflict. */
4796 if (type
== RELOAD_FOR_INPUT_ADDRESS
&& reloadnum
== i
+ 1
4797 && ignore_address_reloads
4798 /* Unless the RELOAD_FOR_INPUT is an auto_inc expression.
4799 Then the address address is still needed to store
4800 back the new address. */
4801 && ! rld
[reloadnum
].out
)
4803 /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its
4804 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS
4806 if (type
== RELOAD_FOR_INPUT
&& opnum
== rld
[i
].opnum
4807 && ignore_address_reloads
4808 /* Unless we are reloading an auto_inc expression. */
4809 && ! rld
[reloadnum
].out
)
4811 time2
= rld
[i
].opnum
* 4 + 2;
4813 case RELOAD_FOR_INPUT_ADDRESS
:
4814 if (type
== RELOAD_FOR_INPUT
&& opnum
== rld
[i
].opnum
4815 && ignore_address_reloads
4816 && ! rld
[reloadnum
].out
)
4818 time2
= rld
[i
].opnum
* 4 + 3;
4820 case RELOAD_FOR_INPUT
:
4821 time2
= rld
[i
].opnum
* 4 + 4;
4822 check_earlyclobber
= 1;
4824 /* rld[i].opnum * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4
4825 == MAX_RECOG_OPERAND * 4 */
4826 case RELOAD_FOR_OPADDR_ADDR
:
4827 if (type
== RELOAD_FOR_OPERAND_ADDRESS
&& reloadnum
== i
+ 1
4828 && ignore_address_reloads
4829 && ! rld
[reloadnum
].out
)
4831 time2
= MAX_RECOG_OPERANDS
* 4 + 1;
4833 case RELOAD_FOR_OPERAND_ADDRESS
:
4834 time2
= MAX_RECOG_OPERANDS
* 4 + 2;
4835 check_earlyclobber
= 1;
4837 case RELOAD_FOR_INSN
:
4838 time2
= MAX_RECOG_OPERANDS
* 4 + 3;
4840 case RELOAD_FOR_OUTPUT
:
4841 /* All RELOAD_FOR_OUTPUT reloads become live just after the
4842 instruction is executed. */
4843 time2
= MAX_RECOG_OPERANDS
* 4 + 4;
4845 /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with
4846 the RELOAD_FOR_OUTPUT reloads, so assign it the same time
4848 case RELOAD_FOR_OUTADDR_ADDRESS
:
4849 if (type
== RELOAD_FOR_OUTPUT_ADDRESS
&& reloadnum
== i
+ 1
4850 && ignore_address_reloads
4851 && ! rld
[reloadnum
].out
)
4853 time2
= MAX_RECOG_OPERANDS
* 4 + 4 + rld
[i
].opnum
;
4855 case RELOAD_FOR_OUTPUT_ADDRESS
:
4856 time2
= MAX_RECOG_OPERANDS
* 4 + 5 + rld
[i
].opnum
;
4859 /* If there is no conflict in the input part, handle this
4860 like an output reload. */
4861 if (! rld
[i
].in
|| rtx_equal_p (other_input
, value
))
4863 time2
= MAX_RECOG_OPERANDS
* 4 + 4;
4864 /* Earlyclobbered outputs must conflict with inputs. */
4865 if (earlyclobber_operand_p (rld
[i
].out
))
4866 time2
= MAX_RECOG_OPERANDS
* 4 + 3;
4871 /* RELOAD_OTHER might be live beyond instruction execution,
4872 but this is not obvious when we set time2 = 1. So check
4873 here if there might be a problem with the new reload
4874 clobbering the register used by the RELOAD_OTHER. */
4882 && (! rld
[i
].in
|| rld
[i
].out
4883 || ! rtx_equal_p (other_input
, value
)))
4884 || (out
&& rld
[reloadnum
].out_reg
4885 && time2
>= MAX_RECOG_OPERANDS
* 4 + 3))
4891 /* Earlyclobbered outputs must conflict with inputs. */
4892 if (check_earlyclobber
&& out
&& earlyclobber_operand_p (out
))
4898 /* Return 1 if the value in reload reg REGNO, as used by a reload
4899 needed for the part of the insn specified by OPNUM and TYPE,
4900 may be used to load VALUE into it.
4902 MODE is the mode in which the register is used, this is needed to
4903 determine how many hard regs to test.
4905 Other read-only reloads with the same value do not conflict
4906 unless OUT is nonzero and these other reloads have to live while
4907 output reloads live.
4908 If OUT is CONST0_RTX, this is a special case: it means that the
4909 test should not be for using register REGNO as reload register, but
4910 for copying from register REGNO into the reload register.
4912 RELOADNUM is the number of the reload we want to load this value for;
4913 a reload does not conflict with itself.
4915 When IGNORE_ADDRESS_RELOADS is set, we can not have conflicts with
4916 reloads that load an address for the very reload we are considering.
4918 The caller has to make sure that there is no conflict with the return
4922 free_for_value_p (int regno
, enum machine_mode mode
, int opnum
,
4923 enum reload_type type
, rtx value
, rtx out
, int reloadnum
,
4924 int ignore_address_reloads
)
4926 int nregs
= HARD_REGNO_NREGS (regno
, mode
);
4928 if (! reload_reg_free_for_value_p (regno
, regno
+ nregs
, opnum
, type
,
4929 value
, out
, reloadnum
,
4930 ignore_address_reloads
))
4935 /* Determine whether the reload reg X overlaps any rtx'es used for
4936 overriding inheritance. Return nonzero if so. */
4939 conflicts_with_override (rtx x
)
4942 for (i
= 0; i
< n_reloads
; i
++)
4943 if (reload_override_in
[i
]
4944 && reg_overlap_mentioned_p (x
, reload_override_in
[i
]))
4949 /* Give an error message saying we failed to find a reload for INSN,
4950 and clear out reload R. */
4952 failed_reload (rtx insn
, int r
)
4954 if (asm_noperands (PATTERN (insn
)) < 0)
4955 /* It's the compiler's fault. */
4956 fatal_insn ("could not find a spill register", insn
);
4958 /* It's the user's fault; the operand's mode and constraint
4959 don't match. Disable this reload so we don't crash in final. */
4960 error_for_asm (insn
,
4961 "`asm' operand constraint incompatible with operand size");
4965 rld
[r
].optional
= 1;
4966 rld
[r
].secondary_p
= 1;
4969 /* I is the index in SPILL_REG_RTX of the reload register we are to allocate
4970 for reload R. If it's valid, get an rtx for it. Return nonzero if
4973 set_reload_reg (int i
, int r
)
4976 rtx reg
= spill_reg_rtx
[i
];
4978 if (reg
== 0 || GET_MODE (reg
) != rld
[r
].mode
)
4979 spill_reg_rtx
[i
] = reg
4980 = gen_rtx_REG (rld
[r
].mode
, spill_regs
[i
]);
4982 regno
= true_regnum (reg
);
4984 /* Detect when the reload reg can't hold the reload mode.
4985 This used to be one `if', but Sequent compiler can't handle that. */
4986 if (HARD_REGNO_MODE_OK (regno
, rld
[r
].mode
))
4988 enum machine_mode test_mode
= VOIDmode
;
4990 test_mode
= GET_MODE (rld
[r
].in
);
4991 /* If rld[r].in has VOIDmode, it means we will load it
4992 in whatever mode the reload reg has: to wit, rld[r].mode.
4993 We have already tested that for validity. */
4994 /* Aside from that, we need to test that the expressions
4995 to reload from or into have modes which are valid for this
4996 reload register. Otherwise the reload insns would be invalid. */
4997 if (! (rld
[r
].in
!= 0 && test_mode
!= VOIDmode
4998 && ! HARD_REGNO_MODE_OK (regno
, test_mode
)))
4999 if (! (rld
[r
].out
!= 0
5000 && ! HARD_REGNO_MODE_OK (regno
, GET_MODE (rld
[r
].out
))))
5002 /* The reg is OK. */
5005 /* Mark as in use for this insn the reload regs we use
5007 mark_reload_reg_in_use (spill_regs
[i
], rld
[r
].opnum
,
5008 rld
[r
].when_needed
, rld
[r
].mode
);
5010 rld
[r
].reg_rtx
= reg
;
5011 reload_spill_index
[r
] = spill_regs
[i
];
5018 /* Find a spill register to use as a reload register for reload R.
5019 LAST_RELOAD is nonzero if this is the last reload for the insn being
5022 Set rld[R].reg_rtx to the register allocated.
5024 We return 1 if successful, or 0 if we couldn't find a spill reg and
5025 we didn't change anything. */
5028 allocate_reload_reg (struct insn_chain
*chain ATTRIBUTE_UNUSED
, int r
,
5033 /* If we put this reload ahead, thinking it is a group,
5034 then insist on finding a group. Otherwise we can grab a
5035 reg that some other reload needs.
5036 (That can happen when we have a 68000 DATA_OR_FP_REG
5037 which is a group of data regs or one fp reg.)
5038 We need not be so restrictive if there are no more reloads
5041 ??? Really it would be nicer to have smarter handling
5042 for that kind of reg class, where a problem like this is normal.
5043 Perhaps those classes should be avoided for reloading
5044 by use of more alternatives. */
5046 int force_group
= rld
[r
].nregs
> 1 && ! last_reload
;
5048 /* If we want a single register and haven't yet found one,
5049 take any reg in the right class and not in use.
5050 If we want a consecutive group, here is where we look for it.
5052 We use two passes so we can first look for reload regs to
5053 reuse, which are already in use for other reloads in this insn,
5054 and only then use additional registers.
5055 I think that maximizing reuse is needed to make sure we don't
5056 run out of reload regs. Suppose we have three reloads, and
5057 reloads A and B can share regs. These need two regs.
5058 Suppose A and B are given different regs.
5059 That leaves none for C. */
5060 for (pass
= 0; pass
< 2; pass
++)
5062 /* I is the index in spill_regs.
5063 We advance it round-robin between insns to use all spill regs
5064 equally, so that inherited reloads have a chance
5065 of leapfrogging each other. */
5069 for (count
= 0; count
< n_spills
; count
++)
5071 int class = (int) rld
[r
].class;
5077 regnum
= spill_regs
[i
];
5079 if ((reload_reg_free_p (regnum
, rld
[r
].opnum
,
5082 /* We check reload_reg_used to make sure we
5083 don't clobber the return register. */
5084 && ! TEST_HARD_REG_BIT (reload_reg_used
, regnum
)
5085 && free_for_value_p (regnum
, rld
[r
].mode
, rld
[r
].opnum
,
5086 rld
[r
].when_needed
, rld
[r
].in
,
5088 && TEST_HARD_REG_BIT (reg_class_contents
[class], regnum
)
5089 && HARD_REGNO_MODE_OK (regnum
, rld
[r
].mode
)
5090 /* Look first for regs to share, then for unshared. But
5091 don't share regs used for inherited reloads; they are
5092 the ones we want to preserve. */
5094 || (TEST_HARD_REG_BIT (reload_reg_used_at_all
,
5096 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit
,
5099 int nr
= HARD_REGNO_NREGS (regnum
, rld
[r
].mode
);
5100 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
5101 (on 68000) got us two FP regs. If NR is 1,
5102 we would reject both of them. */
5105 /* If we need only one reg, we have already won. */
5108 /* But reject a single reg if we demand a group. */
5113 /* Otherwise check that as many consecutive regs as we need
5114 are available here. */
5117 int regno
= regnum
+ nr
- 1;
5118 if (!(TEST_HARD_REG_BIT (reg_class_contents
[class], regno
)
5119 && spill_reg_order
[regno
] >= 0
5120 && reload_reg_free_p (regno
, rld
[r
].opnum
,
5121 rld
[r
].when_needed
)))
5130 /* If we found something on pass 1, omit pass 2. */
5131 if (count
< n_spills
)
5135 /* We should have found a spill register by now. */
5136 if (count
>= n_spills
)
5139 /* I is the index in SPILL_REG_RTX of the reload register we are to
5140 allocate. Get an rtx for it and find its register number. */
5142 return set_reload_reg (i
, r
);
5145 /* Initialize all the tables needed to allocate reload registers.
5146 CHAIN is the insn currently being processed; SAVE_RELOAD_REG_RTX
5147 is the array we use to restore the reg_rtx field for every reload. */
5150 choose_reload_regs_init (struct insn_chain
*chain
, rtx
*save_reload_reg_rtx
)
5154 for (i
= 0; i
< n_reloads
; i
++)
5155 rld
[i
].reg_rtx
= save_reload_reg_rtx
[i
];
5157 memset (reload_inherited
, 0, MAX_RELOADS
);
5158 memset (reload_inheritance_insn
, 0, MAX_RELOADS
* sizeof (rtx
));
5159 memset (reload_override_in
, 0, MAX_RELOADS
* sizeof (rtx
));
5161 CLEAR_HARD_REG_SET (reload_reg_used
);
5162 CLEAR_HARD_REG_SET (reload_reg_used_at_all
);
5163 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr
);
5164 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload
);
5165 CLEAR_HARD_REG_SET (reload_reg_used_in_insn
);
5166 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr
);
5168 CLEAR_HARD_REG_SET (reg_used_in_insn
);
5171 REG_SET_TO_HARD_REG_SET (tmp
, &chain
->live_throughout
);
5172 IOR_HARD_REG_SET (reg_used_in_insn
, tmp
);
5173 REG_SET_TO_HARD_REG_SET (tmp
, &chain
->dead_or_set
);
5174 IOR_HARD_REG_SET (reg_used_in_insn
, tmp
);
5175 compute_use_by_pseudos (®_used_in_insn
, &chain
->live_throughout
);
5176 compute_use_by_pseudos (®_used_in_insn
, &chain
->dead_or_set
);
5179 for (i
= 0; i
< reload_n_operands
; i
++)
5181 CLEAR_HARD_REG_SET (reload_reg_used_in_output
[i
]);
5182 CLEAR_HARD_REG_SET (reload_reg_used_in_input
[i
]);
5183 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr
[i
]);
5184 CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr
[i
]);
5185 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr
[i
]);
5186 CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr
[i
]);
5189 COMPL_HARD_REG_SET (reload_reg_unavailable
, chain
->used_spill_regs
);
5191 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit
);
5193 for (i
= 0; i
< n_reloads
; i
++)
5194 /* If we have already decided to use a certain register,
5195 don't use it in another way. */
5197 mark_reload_reg_in_use (REGNO (rld
[i
].reg_rtx
), rld
[i
].opnum
,
5198 rld
[i
].when_needed
, rld
[i
].mode
);
5201 /* Assign hard reg targets for the pseudo-registers we must reload
5202 into hard regs for this insn.
5203 Also output the instructions to copy them in and out of the hard regs.
5205 For machines with register classes, we are responsible for
5206 finding a reload reg in the proper class. */
5209 choose_reload_regs (struct insn_chain
*chain
)
5211 rtx insn
= chain
->insn
;
5213 unsigned int max_group_size
= 1;
5214 enum reg_class group_class
= NO_REGS
;
5215 int pass
, win
, inheritance
;
5217 rtx save_reload_reg_rtx
[MAX_RELOADS
];
5219 /* In order to be certain of getting the registers we need,
5220 we must sort the reloads into order of increasing register class.
5221 Then our grabbing of reload registers will parallel the process
5222 that provided the reload registers.
5224 Also note whether any of the reloads wants a consecutive group of regs.
5225 If so, record the maximum size of the group desired and what
5226 register class contains all the groups needed by this insn. */
5228 for (j
= 0; j
< n_reloads
; j
++)
5230 reload_order
[j
] = j
;
5231 reload_spill_index
[j
] = -1;
5233 if (rld
[j
].nregs
> 1)
5235 max_group_size
= MAX (rld
[j
].nregs
, max_group_size
);
5237 = reg_class_superunion
[(int) rld
[j
].class][(int) group_class
];
5240 save_reload_reg_rtx
[j
] = rld
[j
].reg_rtx
;
5244 qsort (reload_order
, n_reloads
, sizeof (short), reload_reg_class_lower
);
5246 /* If -O, try first with inheritance, then turning it off.
5247 If not -O, don't do inheritance.
5248 Using inheritance when not optimizing leads to paradoxes
5249 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
5250 because one side of the comparison might be inherited. */
5252 for (inheritance
= optimize
> 0; inheritance
>= 0; inheritance
--)
5254 choose_reload_regs_init (chain
, save_reload_reg_rtx
);
5256 /* Process the reloads in order of preference just found.
5257 Beyond this point, subregs can be found in reload_reg_rtx.
5259 This used to look for an existing reloaded home for all of the
5260 reloads, and only then perform any new reloads. But that could lose
5261 if the reloads were done out of reg-class order because a later
5262 reload with a looser constraint might have an old home in a register
5263 needed by an earlier reload with a tighter constraint.
5265 To solve this, we make two passes over the reloads, in the order
5266 described above. In the first pass we try to inherit a reload
5267 from a previous insn. If there is a later reload that needs a
5268 class that is a proper subset of the class being processed, we must
5269 also allocate a spill register during the first pass.
5271 Then make a second pass over the reloads to allocate any reloads
5272 that haven't been given registers yet. */
5274 for (j
= 0; j
< n_reloads
; j
++)
5276 int r
= reload_order
[j
];
5277 rtx search_equiv
= NULL_RTX
;
5279 /* Ignore reloads that got marked inoperative. */
5280 if (rld
[r
].out
== 0 && rld
[r
].in
== 0
5281 && ! rld
[r
].secondary_p
)
5284 /* If find_reloads chose to use reload_in or reload_out as a reload
5285 register, we don't need to chose one. Otherwise, try even if it
5286 found one since we might save an insn if we find the value lying
5288 Try also when reload_in is a pseudo without a hard reg. */
5289 if (rld
[r
].in
!= 0 && rld
[r
].reg_rtx
!= 0
5290 && (rtx_equal_p (rld
[r
].in
, rld
[r
].reg_rtx
)
5291 || (rtx_equal_p (rld
[r
].out
, rld
[r
].reg_rtx
)
5292 && GET_CODE (rld
[r
].in
) != MEM
5293 && true_regnum (rld
[r
].in
) < FIRST_PSEUDO_REGISTER
)))
5296 #if 0 /* No longer needed for correct operation.
5297 It might give better code, or might not; worth an experiment? */
5298 /* If this is an optional reload, we can't inherit from earlier insns
5299 until we are sure that any non-optional reloads have been allocated.
5300 The following code takes advantage of the fact that optional reloads
5301 are at the end of reload_order. */
5302 if (rld
[r
].optional
!= 0)
5303 for (i
= 0; i
< j
; i
++)
5304 if ((rld
[reload_order
[i
]].out
!= 0
5305 || rld
[reload_order
[i
]].in
!= 0
5306 || rld
[reload_order
[i
]].secondary_p
)
5307 && ! rld
[reload_order
[i
]].optional
5308 && rld
[reload_order
[i
]].reg_rtx
== 0)
5309 allocate_reload_reg (chain
, reload_order
[i
], 0);
5312 /* First see if this pseudo is already available as reloaded
5313 for a previous insn. We cannot try to inherit for reloads
5314 that are smaller than the maximum number of registers needed
5315 for groups unless the register we would allocate cannot be used
5318 We could check here to see if this is a secondary reload for
5319 an object that is already in a register of the desired class.
5320 This would avoid the need for the secondary reload register.
5321 But this is complex because we can't easily determine what
5322 objects might want to be loaded via this reload. So let a
5323 register be allocated here. In `emit_reload_insns' we suppress
5324 one of the loads in the case described above. */
5330 enum machine_mode mode
= VOIDmode
;
5334 else if (GET_CODE (rld
[r
].in
) == REG
)
5336 regno
= REGNO (rld
[r
].in
);
5337 mode
= GET_MODE (rld
[r
].in
);
5339 else if (GET_CODE (rld
[r
].in_reg
) == REG
)
5341 regno
= REGNO (rld
[r
].in_reg
);
5342 mode
= GET_MODE (rld
[r
].in_reg
);
5344 else if (GET_CODE (rld
[r
].in_reg
) == SUBREG
5345 && GET_CODE (SUBREG_REG (rld
[r
].in_reg
)) == REG
)
5347 byte
= SUBREG_BYTE (rld
[r
].in_reg
);
5348 regno
= REGNO (SUBREG_REG (rld
[r
].in_reg
));
5349 if (regno
< FIRST_PSEUDO_REGISTER
)
5350 regno
= subreg_regno (rld
[r
].in_reg
);
5351 mode
= GET_MODE (rld
[r
].in_reg
);
5354 else if ((GET_CODE (rld
[r
].in_reg
) == PRE_INC
5355 || GET_CODE (rld
[r
].in_reg
) == PRE_DEC
5356 || GET_CODE (rld
[r
].in_reg
) == POST_INC
5357 || GET_CODE (rld
[r
].in_reg
) == POST_DEC
)
5358 && GET_CODE (XEXP (rld
[r
].in_reg
, 0)) == REG
)
5360 regno
= REGNO (XEXP (rld
[r
].in_reg
, 0));
5361 mode
= GET_MODE (XEXP (rld
[r
].in_reg
, 0));
5362 rld
[r
].out
= rld
[r
].in
;
5366 /* This won't work, since REGNO can be a pseudo reg number.
5367 Also, it takes much more hair to keep track of all the things
5368 that can invalidate an inherited reload of part of a pseudoreg. */
5369 else if (GET_CODE (rld
[r
].in
) == SUBREG
5370 && GET_CODE (SUBREG_REG (rld
[r
].in
)) == REG
)
5371 regno
= subreg_regno (rld
[r
].in
);
5374 if (regno
>= 0 && reg_last_reload_reg
[regno
] != 0)
5376 enum reg_class
class = rld
[r
].class, last_class
;
5377 rtx last_reg
= reg_last_reload_reg
[regno
];
5378 enum machine_mode need_mode
;
5380 i
= REGNO (last_reg
);
5381 i
+= subreg_regno_offset (i
, GET_MODE (last_reg
), byte
, mode
);
5382 last_class
= REGNO_REG_CLASS (i
);
5388 = smallest_mode_for_size (GET_MODE_SIZE (mode
) + byte
,
5389 GET_MODE_CLASS (mode
));
5392 #ifdef CANNOT_CHANGE_MODE_CLASS
5393 (!REG_CANNOT_CHANGE_MODE_P (i
, GET_MODE (last_reg
),
5397 (GET_MODE_SIZE (GET_MODE (last_reg
))
5398 >= GET_MODE_SIZE (need_mode
))
5399 #ifdef CANNOT_CHANGE_MODE_CLASS
5402 && reg_reloaded_contents
[i
] == regno
5403 && TEST_HARD_REG_BIT (reg_reloaded_valid
, i
)
5404 && HARD_REGNO_MODE_OK (i
, rld
[r
].mode
)
5405 && (TEST_HARD_REG_BIT (reg_class_contents
[(int) class], i
)
5406 /* Even if we can't use this register as a reload
5407 register, we might use it for reload_override_in,
5408 if copying it to the desired class is cheap
5410 || ((REGISTER_MOVE_COST (mode
, last_class
, class)
5411 < MEMORY_MOVE_COST (mode
, class, 1))
5412 #ifdef SECONDARY_INPUT_RELOAD_CLASS
5413 && (SECONDARY_INPUT_RELOAD_CLASS (class, mode
,
5417 #ifdef SECONDARY_MEMORY_NEEDED
5418 && ! SECONDARY_MEMORY_NEEDED (last_class
, class,
5423 && (rld
[r
].nregs
== max_group_size
5424 || ! TEST_HARD_REG_BIT (reg_class_contents
[(int) group_class
],
5426 && free_for_value_p (i
, rld
[r
].mode
, rld
[r
].opnum
,
5427 rld
[r
].when_needed
, rld
[r
].in
,
5430 /* If a group is needed, verify that all the subsequent
5431 registers still have their values intact. */
5432 int nr
= HARD_REGNO_NREGS (i
, rld
[r
].mode
);
5435 for (k
= 1; k
< nr
; k
++)
5436 if (reg_reloaded_contents
[i
+ k
] != regno
5437 || ! TEST_HARD_REG_BIT (reg_reloaded_valid
, i
+ k
))
5445 last_reg
= (GET_MODE (last_reg
) == mode
5446 ? last_reg
: gen_rtx_REG (mode
, i
));
5449 for (k
= 0; k
< nr
; k
++)
5450 bad_for_class
|= ! TEST_HARD_REG_BIT (reg_class_contents
[(int) rld
[r
].class],
5453 /* We found a register that contains the
5454 value we need. If this register is the
5455 same as an `earlyclobber' operand of the
5456 current insn, just mark it as a place to
5457 reload from since we can't use it as the
5458 reload register itself. */
5460 for (i1
= 0; i1
< n_earlyclobbers
; i1
++)
5461 if (reg_overlap_mentioned_for_reload_p
5462 (reg_last_reload_reg
[regno
],
5463 reload_earlyclobbers
[i1
]))
5466 if (i1
!= n_earlyclobbers
5467 || ! (free_for_value_p (i
, rld
[r
].mode
,
5469 rld
[r
].when_needed
, rld
[r
].in
,
5471 /* Don't use it if we'd clobber a pseudo reg. */
5472 || (TEST_HARD_REG_BIT (reg_used_in_insn
, i
)
5474 && ! TEST_HARD_REG_BIT (reg_reloaded_dead
, i
))
5475 /* Don't clobber the frame pointer. */
5476 || (i
== HARD_FRAME_POINTER_REGNUM
5477 && frame_pointer_needed
5479 /* Don't really use the inherited spill reg
5480 if we need it wider than we've got it. */
5481 || (GET_MODE_SIZE (rld
[r
].mode
)
5482 > GET_MODE_SIZE (mode
))
5485 /* If find_reloads chose reload_out as reload
5486 register, stay with it - that leaves the
5487 inherited register for subsequent reloads. */
5488 || (rld
[r
].out
&& rld
[r
].reg_rtx
5489 && rtx_equal_p (rld
[r
].out
, rld
[r
].reg_rtx
)))
5491 if (! rld
[r
].optional
)
5493 reload_override_in
[r
] = last_reg
;
5494 reload_inheritance_insn
[r
]
5495 = reg_reloaded_insn
[i
];
5501 /* We can use this as a reload reg. */
5502 /* Mark the register as in use for this part of
5504 mark_reload_reg_in_use (i
,
5508 rld
[r
].reg_rtx
= last_reg
;
5509 reload_inherited
[r
] = 1;
5510 reload_inheritance_insn
[r
]
5511 = reg_reloaded_insn
[i
];
5512 reload_spill_index
[r
] = i
;
5513 for (k
= 0; k
< nr
; k
++)
5514 SET_HARD_REG_BIT (reload_reg_used_for_inherit
,
5522 /* Here's another way to see if the value is already lying around. */
5525 && ! reload_inherited
[r
]
5527 && (CONSTANT_P (rld
[r
].in
)
5528 || GET_CODE (rld
[r
].in
) == PLUS
5529 || GET_CODE (rld
[r
].in
) == REG
5530 || GET_CODE (rld
[r
].in
) == MEM
)
5531 && (rld
[r
].nregs
== max_group_size
5532 || ! reg_classes_intersect_p (rld
[r
].class, group_class
)))
5533 search_equiv
= rld
[r
].in
;
5534 /* If this is an output reload from a simple move insn, look
5535 if an equivalence for the input is available. */
5536 else if (inheritance
&& rld
[r
].in
== 0 && rld
[r
].out
!= 0)
5538 rtx set
= single_set (insn
);
5541 && rtx_equal_p (rld
[r
].out
, SET_DEST (set
))
5542 && CONSTANT_P (SET_SRC (set
)))
5543 search_equiv
= SET_SRC (set
);
5549 = find_equiv_reg (search_equiv
, insn
, rld
[r
].class,
5550 -1, NULL
, 0, rld
[r
].mode
);
5555 if (GET_CODE (equiv
) == REG
)
5556 regno
= REGNO (equiv
);
5557 else if (GET_CODE (equiv
) == SUBREG
)
5559 /* This must be a SUBREG of a hard register.
5560 Make a new REG since this might be used in an
5561 address and not all machines support SUBREGs
5563 regno
= subreg_regno (equiv
);
5564 equiv
= gen_rtx_REG (rld
[r
].mode
, regno
);
5570 /* If we found a spill reg, reject it unless it is free
5571 and of the desired class. */
5575 int bad_for_class
= 0;
5576 int max_regno
= regno
+ rld
[r
].nregs
;
5578 for (i
= regno
; i
< max_regno
; i
++)
5580 regs_used
|= TEST_HARD_REG_BIT (reload_reg_used_at_all
,
5582 bad_for_class
|= ! TEST_HARD_REG_BIT (reg_class_contents
[(int) rld
[r
].class],
5587 && ! free_for_value_p (regno
, rld
[r
].mode
,
5588 rld
[r
].opnum
, rld
[r
].when_needed
,
5589 rld
[r
].in
, rld
[r
].out
, r
, 1))
5594 if (equiv
!= 0 && ! HARD_REGNO_MODE_OK (regno
, rld
[r
].mode
))
5597 /* We found a register that contains the value we need.
5598 If this register is the same as an `earlyclobber' operand
5599 of the current insn, just mark it as a place to reload from
5600 since we can't use it as the reload register itself. */
5603 for (i
= 0; i
< n_earlyclobbers
; i
++)
5604 if (reg_overlap_mentioned_for_reload_p (equiv
,
5605 reload_earlyclobbers
[i
]))
5607 if (! rld
[r
].optional
)
5608 reload_override_in
[r
] = equiv
;
5613 /* If the equiv register we have found is explicitly clobbered
5614 in the current insn, it depends on the reload type if we
5615 can use it, use it for reload_override_in, or not at all.
5616 In particular, we then can't use EQUIV for a
5617 RELOAD_FOR_OUTPUT_ADDRESS reload. */
5621 if (regno_clobbered_p (regno
, insn
, rld
[r
].mode
, 0))
5622 switch (rld
[r
].when_needed
)
5624 case RELOAD_FOR_OTHER_ADDRESS
:
5625 case RELOAD_FOR_INPADDR_ADDRESS
:
5626 case RELOAD_FOR_INPUT_ADDRESS
:
5627 case RELOAD_FOR_OPADDR_ADDR
:
5630 case RELOAD_FOR_INPUT
:
5631 case RELOAD_FOR_OPERAND_ADDRESS
:
5632 if (! rld
[r
].optional
)
5633 reload_override_in
[r
] = equiv
;
5639 else if (regno_clobbered_p (regno
, insn
, rld
[r
].mode
, 1))
5640 switch (rld
[r
].when_needed
)
5642 case RELOAD_FOR_OTHER_ADDRESS
:
5643 case RELOAD_FOR_INPADDR_ADDRESS
:
5644 case RELOAD_FOR_INPUT_ADDRESS
:
5645 case RELOAD_FOR_OPADDR_ADDR
:
5646 case RELOAD_FOR_OPERAND_ADDRESS
:
5647 case RELOAD_FOR_INPUT
:
5650 if (! rld
[r
].optional
)
5651 reload_override_in
[r
] = equiv
;
5659 /* If we found an equivalent reg, say no code need be generated
5660 to load it, and use it as our reload reg. */
5662 && (regno
!= HARD_FRAME_POINTER_REGNUM
5663 || !frame_pointer_needed
))
5665 int nr
= HARD_REGNO_NREGS (regno
, rld
[r
].mode
);
5667 rld
[r
].reg_rtx
= equiv
;
5668 reload_inherited
[r
] = 1;
5670 /* If reg_reloaded_valid is not set for this register,
5671 there might be a stale spill_reg_store lying around.
5672 We must clear it, since otherwise emit_reload_insns
5673 might delete the store. */
5674 if (! TEST_HARD_REG_BIT (reg_reloaded_valid
, regno
))
5675 spill_reg_store
[regno
] = NULL_RTX
;
5676 /* If any of the hard registers in EQUIV are spill
5677 registers, mark them as in use for this insn. */
5678 for (k
= 0; k
< nr
; k
++)
5680 i
= spill_reg_order
[regno
+ k
];
5683 mark_reload_reg_in_use (regno
, rld
[r
].opnum
,
5686 SET_HARD_REG_BIT (reload_reg_used_for_inherit
,
5693 /* If we found a register to use already, or if this is an optional
5694 reload, we are done. */
5695 if (rld
[r
].reg_rtx
!= 0 || rld
[r
].optional
!= 0)
5699 /* No longer needed for correct operation. Might or might
5700 not give better code on the average. Want to experiment? */
5702 /* See if there is a later reload that has a class different from our
5703 class that intersects our class or that requires less register
5704 than our reload. If so, we must allocate a register to this
5705 reload now, since that reload might inherit a previous reload
5706 and take the only available register in our class. Don't do this
5707 for optional reloads since they will force all previous reloads
5708 to be allocated. Also don't do this for reloads that have been
5711 for (i
= j
+ 1; i
< n_reloads
; i
++)
5713 int s
= reload_order
[i
];
5715 if ((rld
[s
].in
== 0 && rld
[s
].out
== 0
5716 && ! rld
[s
].secondary_p
)
5720 if ((rld
[s
].class != rld
[r
].class
5721 && reg_classes_intersect_p (rld
[r
].class,
5723 || rld
[s
].nregs
< rld
[r
].nregs
)
5730 allocate_reload_reg (chain
, r
, j
== n_reloads
- 1);
5734 /* Now allocate reload registers for anything non-optional that
5735 didn't get one yet. */
5736 for (j
= 0; j
< n_reloads
; j
++)
5738 int r
= reload_order
[j
];
5740 /* Ignore reloads that got marked inoperative. */
5741 if (rld
[r
].out
== 0 && rld
[r
].in
== 0 && ! rld
[r
].secondary_p
)
5744 /* Skip reloads that already have a register allocated or are
5746 if (rld
[r
].reg_rtx
!= 0 || rld
[r
].optional
)
5749 if (! allocate_reload_reg (chain
, r
, j
== n_reloads
- 1))
5753 /* If that loop got all the way, we have won. */
5760 /* Loop around and try without any inheritance. */
5765 /* First undo everything done by the failed attempt
5766 to allocate with inheritance. */
5767 choose_reload_regs_init (chain
, save_reload_reg_rtx
);
5769 /* Some sanity tests to verify that the reloads found in the first
5770 pass are identical to the ones we have now. */
5771 if (chain
->n_reloads
!= n_reloads
)
5774 for (i
= 0; i
< n_reloads
; i
++)
5776 if (chain
->rld
[i
].regno
< 0 || chain
->rld
[i
].reg_rtx
!= 0)
5778 if (chain
->rld
[i
].when_needed
!= rld
[i
].when_needed
)
5780 for (j
= 0; j
< n_spills
; j
++)
5781 if (spill_regs
[j
] == chain
->rld
[i
].regno
)
5782 if (! set_reload_reg (j
, i
))
5783 failed_reload (chain
->insn
, i
);
5787 /* If we thought we could inherit a reload, because it seemed that
5788 nothing else wanted the same reload register earlier in the insn,
5789 verify that assumption, now that all reloads have been assigned.
5790 Likewise for reloads where reload_override_in has been set. */
5792 /* If doing expensive optimizations, do one preliminary pass that doesn't
5793 cancel any inheritance, but removes reloads that have been needed only
5794 for reloads that we know can be inherited. */
5795 for (pass
= flag_expensive_optimizations
; pass
>= 0; pass
--)
5797 for (j
= 0; j
< n_reloads
; j
++)
5799 int r
= reload_order
[j
];
5801 if (reload_inherited
[r
] && rld
[r
].reg_rtx
)
5802 check_reg
= rld
[r
].reg_rtx
;
5803 else if (reload_override_in
[r
]
5804 && (GET_CODE (reload_override_in
[r
]) == REG
5805 || GET_CODE (reload_override_in
[r
]) == SUBREG
))
5806 check_reg
= reload_override_in
[r
];
5809 if (! free_for_value_p (true_regnum (check_reg
), rld
[r
].mode
,
5810 rld
[r
].opnum
, rld
[r
].when_needed
, rld
[r
].in
,
5811 (reload_inherited
[r
]
5812 ? rld
[r
].out
: const0_rtx
),
5817 reload_inherited
[r
] = 0;
5818 reload_override_in
[r
] = 0;
5820 /* If we can inherit a RELOAD_FOR_INPUT, or can use a
5821 reload_override_in, then we do not need its related
5822 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads;
5823 likewise for other reload types.
5824 We handle this by removing a reload when its only replacement
5825 is mentioned in reload_in of the reload we are going to inherit.
5826 A special case are auto_inc expressions; even if the input is
5827 inherited, we still need the address for the output. We can
5828 recognize them because they have RELOAD_OUT set to RELOAD_IN.
5829 If we succeeded removing some reload and we are doing a preliminary
5830 pass just to remove such reloads, make another pass, since the
5831 removal of one reload might allow us to inherit another one. */
5833 && rld
[r
].out
!= rld
[r
].in
5834 && remove_address_replacements (rld
[r
].in
) && pass
)
5839 /* Now that reload_override_in is known valid,
5840 actually override reload_in. */
5841 for (j
= 0; j
< n_reloads
; j
++)
5842 if (reload_override_in
[j
])
5843 rld
[j
].in
= reload_override_in
[j
];
5845 /* If this reload won't be done because it has been canceled or is
5846 optional and not inherited, clear reload_reg_rtx so other
5847 routines (such as subst_reloads) don't get confused. */
5848 for (j
= 0; j
< n_reloads
; j
++)
5849 if (rld
[j
].reg_rtx
!= 0
5850 && ((rld
[j
].optional
&& ! reload_inherited
[j
])
5851 || (rld
[j
].in
== 0 && rld
[j
].out
== 0
5852 && ! rld
[j
].secondary_p
)))
5854 int regno
= true_regnum (rld
[j
].reg_rtx
);
5856 if (spill_reg_order
[regno
] >= 0)
5857 clear_reload_reg_in_use (regno
, rld
[j
].opnum
,
5858 rld
[j
].when_needed
, rld
[j
].mode
);
5860 reload_spill_index
[j
] = -1;
5863 /* Record which pseudos and which spill regs have output reloads. */
5864 for (j
= 0; j
< n_reloads
; j
++)
5866 int r
= reload_order
[j
];
5868 i
= reload_spill_index
[r
];
5870 /* I is nonneg if this reload uses a register.
5871 If rld[r].reg_rtx is 0, this is an optional reload
5872 that we opted to ignore. */
5873 if (rld
[r
].out_reg
!= 0 && GET_CODE (rld
[r
].out_reg
) == REG
5874 && rld
[r
].reg_rtx
!= 0)
5876 int nregno
= REGNO (rld
[r
].out_reg
);
5879 if (nregno
< FIRST_PSEUDO_REGISTER
)
5880 nr
= HARD_REGNO_NREGS (nregno
, rld
[r
].mode
);
5883 reg_has_output_reload
[nregno
+ nr
] = 1;
5887 nr
= HARD_REGNO_NREGS (i
, rld
[r
].mode
);
5889 SET_HARD_REG_BIT (reg_is_output_reload
, i
+ nr
);
5892 if (rld
[r
].when_needed
!= RELOAD_OTHER
5893 && rld
[r
].when_needed
!= RELOAD_FOR_OUTPUT
5894 && rld
[r
].when_needed
!= RELOAD_FOR_INSN
)
5900 /* Deallocate the reload register for reload R. This is called from
5901 remove_address_replacements. */
5904 deallocate_reload_reg (int r
)
5908 if (! rld
[r
].reg_rtx
)
5910 regno
= true_regnum (rld
[r
].reg_rtx
);
5912 if (spill_reg_order
[regno
] >= 0)
5913 clear_reload_reg_in_use (regno
, rld
[r
].opnum
, rld
[r
].when_needed
,
5915 reload_spill_index
[r
] = -1;
5918 /* If SMALL_REGISTER_CLASSES is nonzero, we may not have merged two
5919 reloads of the same item for fear that we might not have enough reload
5920 registers. However, normally they will get the same reload register
5921 and hence actually need not be loaded twice.
5923 Here we check for the most common case of this phenomenon: when we have
5924 a number of reloads for the same object, each of which were allocated
5925 the same reload_reg_rtx, that reload_reg_rtx is not used for any other
5926 reload, and is not modified in the insn itself. If we find such,
5927 merge all the reloads and set the resulting reload to RELOAD_OTHER.
5928 This will not increase the number of spill registers needed and will
5929 prevent redundant code. */
5932 merge_assigned_reloads (rtx insn
)
5936 /* Scan all the reloads looking for ones that only load values and
5937 are not already RELOAD_OTHER and ones whose reload_reg_rtx are
5938 assigned and not modified by INSN. */
5940 for (i
= 0; i
< n_reloads
; i
++)
5942 int conflicting_input
= 0;
5943 int max_input_address_opnum
= -1;
5944 int min_conflicting_input_opnum
= MAX_RECOG_OPERANDS
;
5946 if (rld
[i
].in
== 0 || rld
[i
].when_needed
== RELOAD_OTHER
5947 || rld
[i
].out
!= 0 || rld
[i
].reg_rtx
== 0
5948 || reg_set_p (rld
[i
].reg_rtx
, insn
))
5951 /* Look at all other reloads. Ensure that the only use of this
5952 reload_reg_rtx is in a reload that just loads the same value
5953 as we do. Note that any secondary reloads must be of the identical
5954 class since the values, modes, and result registers are the
5955 same, so we need not do anything with any secondary reloads. */
5957 for (j
= 0; j
< n_reloads
; j
++)
5959 if (i
== j
|| rld
[j
].reg_rtx
== 0
5960 || ! reg_overlap_mentioned_p (rld
[j
].reg_rtx
,
5964 if (rld
[j
].when_needed
== RELOAD_FOR_INPUT_ADDRESS
5965 && rld
[j
].opnum
> max_input_address_opnum
)
5966 max_input_address_opnum
= rld
[j
].opnum
;
5968 /* If the reload regs aren't exactly the same (e.g, different modes)
5969 or if the values are different, we can't merge this reload.
5970 But if it is an input reload, we might still merge
5971 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_OTHER_ADDRESS reloads. */
5973 if (! rtx_equal_p (rld
[i
].reg_rtx
, rld
[j
].reg_rtx
)
5974 || rld
[j
].out
!= 0 || rld
[j
].in
== 0
5975 || ! rtx_equal_p (rld
[i
].in
, rld
[j
].in
))
5977 if (rld
[j
].when_needed
!= RELOAD_FOR_INPUT
5978 || ((rld
[i
].when_needed
!= RELOAD_FOR_INPUT_ADDRESS
5979 || rld
[i
].opnum
> rld
[j
].opnum
)
5980 && rld
[i
].when_needed
!= RELOAD_FOR_OTHER_ADDRESS
))
5982 conflicting_input
= 1;
5983 if (min_conflicting_input_opnum
> rld
[j
].opnum
)
5984 min_conflicting_input_opnum
= rld
[j
].opnum
;
5988 /* If all is OK, merge the reloads. Only set this to RELOAD_OTHER if
5989 we, in fact, found any matching reloads. */
5992 && max_input_address_opnum
<= min_conflicting_input_opnum
)
5994 for (j
= 0; j
< n_reloads
; j
++)
5995 if (i
!= j
&& rld
[j
].reg_rtx
!= 0
5996 && rtx_equal_p (rld
[i
].reg_rtx
, rld
[j
].reg_rtx
)
5997 && (! conflicting_input
5998 || rld
[j
].when_needed
== RELOAD_FOR_INPUT_ADDRESS
5999 || rld
[j
].when_needed
== RELOAD_FOR_OTHER_ADDRESS
))
6001 rld
[i
].when_needed
= RELOAD_OTHER
;
6003 reload_spill_index
[j
] = -1;
6004 transfer_replacements (i
, j
);
6007 /* If this is now RELOAD_OTHER, look for any reloads that load
6008 parts of this operand and set them to RELOAD_FOR_OTHER_ADDRESS
6009 if they were for inputs, RELOAD_OTHER for outputs. Note that
6010 this test is equivalent to looking for reloads for this operand
6012 /* We must take special care when there are two or more reloads to
6013 be merged and a RELOAD_FOR_OUTPUT_ADDRESS reload that loads the
6014 same value or a part of it; we must not change its type if there
6015 is a conflicting input. */
6017 if (rld
[i
].when_needed
== RELOAD_OTHER
)
6018 for (j
= 0; j
< n_reloads
; j
++)
6020 && rld
[j
].when_needed
!= RELOAD_OTHER
6021 && rld
[j
].when_needed
!= RELOAD_FOR_OTHER_ADDRESS
6022 && (! conflicting_input
6023 || rld
[j
].when_needed
== RELOAD_FOR_INPUT_ADDRESS
6024 || rld
[j
].when_needed
== RELOAD_FOR_INPADDR_ADDRESS
)
6025 && reg_overlap_mentioned_for_reload_p (rld
[j
].in
,
6031 = ((rld
[j
].when_needed
== RELOAD_FOR_INPUT_ADDRESS
6032 || rld
[j
].when_needed
== RELOAD_FOR_INPADDR_ADDRESS
)
6033 ? RELOAD_FOR_OTHER_ADDRESS
: RELOAD_OTHER
);
6035 /* Check to see if we accidentally converted two reloads
6036 that use the same reload register with different inputs
6037 to the same type. If so, the resulting code won't work,
6040 for (k
= 0; k
< j
; k
++)
6041 if (rld
[k
].in
!= 0 && rld
[k
].reg_rtx
!= 0
6042 && rld
[k
].when_needed
== rld
[j
].when_needed
6043 && rtx_equal_p (rld
[k
].reg_rtx
, rld
[j
].reg_rtx
)
6044 && ! rtx_equal_p (rld
[k
].in
, rld
[j
].in
))
6051 /* These arrays are filled by emit_reload_insns and its subroutines. */
6052 static rtx input_reload_insns
[MAX_RECOG_OPERANDS
];
6053 static rtx other_input_address_reload_insns
= 0;
6054 static rtx other_input_reload_insns
= 0;
6055 static rtx input_address_reload_insns
[MAX_RECOG_OPERANDS
];
6056 static rtx inpaddr_address_reload_insns
[MAX_RECOG_OPERANDS
];
6057 static rtx output_reload_insns
[MAX_RECOG_OPERANDS
];
6058 static rtx output_address_reload_insns
[MAX_RECOG_OPERANDS
];
6059 static rtx outaddr_address_reload_insns
[MAX_RECOG_OPERANDS
];
6060 static rtx operand_reload_insns
= 0;
6061 static rtx other_operand_reload_insns
= 0;
6062 static rtx other_output_reload_insns
[MAX_RECOG_OPERANDS
];
6064 /* Values to be put in spill_reg_store are put here first. */
6065 static rtx new_spill_reg_store
[FIRST_PSEUDO_REGISTER
];
6066 static HARD_REG_SET reg_reloaded_died
;
6068 /* Generate insns to perform reload RL, which is for the insn in CHAIN and
6069 has the number J. OLD contains the value to be used as input. */
6072 emit_input_reload_insns (struct insn_chain
*chain
, struct reload
*rl
,
6075 rtx insn
= chain
->insn
;
6076 rtx reloadreg
= rl
->reg_rtx
;
6077 rtx oldequiv_reg
= 0;
6080 enum machine_mode mode
;
6083 /* Determine the mode to reload in.
6084 This is very tricky because we have three to choose from.
6085 There is the mode the insn operand wants (rl->inmode).
6086 There is the mode of the reload register RELOADREG.
6087 There is the intrinsic mode of the operand, which we could find
6088 by stripping some SUBREGs.
6089 It turns out that RELOADREG's mode is irrelevant:
6090 we can change that arbitrarily.
6092 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
6093 then the reload reg may not support QImode moves, so use SImode.
6094 If foo is in memory due to spilling a pseudo reg, this is safe,
6095 because the QImode value is in the least significant part of a
6096 slot big enough for a SImode. If foo is some other sort of
6097 memory reference, then it is impossible to reload this case,
6098 so previous passes had better make sure this never happens.
6100 Then consider a one-word union which has SImode and one of its
6101 members is a float, being fetched as (SUBREG:SF union:SI).
6102 We must fetch that as SFmode because we could be loading into
6103 a float-only register. In this case OLD's mode is correct.
6105 Consider an immediate integer: it has VOIDmode. Here we need
6106 to get a mode from something else.
6108 In some cases, there is a fourth mode, the operand's
6109 containing mode. If the insn specifies a containing mode for
6110 this operand, it overrides all others.
6112 I am not sure whether the algorithm here is always right,
6113 but it does the right things in those cases. */
6115 mode
= GET_MODE (old
);
6116 if (mode
== VOIDmode
)
6119 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6120 /* If we need a secondary register for this operation, see if
6121 the value is already in a register in that class. Don't
6122 do this if the secondary register will be used as a scratch
6125 if (rl
->secondary_in_reload
>= 0
6126 && rl
->secondary_in_icode
== CODE_FOR_nothing
6129 = find_equiv_reg (old
, insn
,
6130 rld
[rl
->secondary_in_reload
].class,
6134 /* If reloading from memory, see if there is a register
6135 that already holds the same value. If so, reload from there.
6136 We can pass 0 as the reload_reg_p argument because
6137 any other reload has either already been emitted,
6138 in which case find_equiv_reg will see the reload-insn,
6139 or has yet to be emitted, in which case it doesn't matter
6140 because we will use this equiv reg right away. */
6142 if (oldequiv
== 0 && optimize
6143 && (GET_CODE (old
) == MEM
6144 || (GET_CODE (old
) == REG
6145 && REGNO (old
) >= FIRST_PSEUDO_REGISTER
6146 && reg_renumber
[REGNO (old
)] < 0)))
6147 oldequiv
= find_equiv_reg (old
, insn
, ALL_REGS
, -1, NULL
, 0, mode
);
6151 unsigned int regno
= true_regnum (oldequiv
);
6153 /* Don't use OLDEQUIV if any other reload changes it at an
6154 earlier stage of this insn or at this stage. */
6155 if (! free_for_value_p (regno
, rl
->mode
, rl
->opnum
, rl
->when_needed
,
6156 rl
->in
, const0_rtx
, j
, 0))
6159 /* If it is no cheaper to copy from OLDEQUIV into the
6160 reload register than it would be to move from memory,
6161 don't use it. Likewise, if we need a secondary register
6165 && (((enum reg_class
) REGNO_REG_CLASS (regno
) != rl
->class
6166 && (REGISTER_MOVE_COST (mode
, REGNO_REG_CLASS (regno
),
6168 >= MEMORY_MOVE_COST (mode
, rl
->class, 1)))
6169 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6170 || (SECONDARY_INPUT_RELOAD_CLASS (rl
->class,
6174 #ifdef SECONDARY_MEMORY_NEEDED
6175 || SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (regno
),
6183 /* delete_output_reload is only invoked properly if old contains
6184 the original pseudo register. Since this is replaced with a
6185 hard reg when RELOAD_OVERRIDE_IN is set, see if we can
6186 find the pseudo in RELOAD_IN_REG. */
6188 && reload_override_in
[j
]
6189 && GET_CODE (rl
->in_reg
) == REG
)
6196 else if (GET_CODE (oldequiv
) == REG
)
6197 oldequiv_reg
= oldequiv
;
6198 else if (GET_CODE (oldequiv
) == SUBREG
)
6199 oldequiv_reg
= SUBREG_REG (oldequiv
);
6201 /* If we are reloading from a register that was recently stored in
6202 with an output-reload, see if we can prove there was
6203 actually no need to store the old value in it. */
6205 if (optimize
&& GET_CODE (oldequiv
) == REG
6206 && REGNO (oldequiv
) < FIRST_PSEUDO_REGISTER
6207 && spill_reg_store
[REGNO (oldequiv
)]
6208 && GET_CODE (old
) == REG
6209 && (dead_or_set_p (insn
, spill_reg_stored_to
[REGNO (oldequiv
)])
6210 || rtx_equal_p (spill_reg_stored_to
[REGNO (oldequiv
)],
6212 delete_output_reload (insn
, j
, REGNO (oldequiv
));
6214 /* Encapsulate both RELOADREG and OLDEQUIV into that mode,
6215 then load RELOADREG from OLDEQUIV. Note that we cannot use
6216 gen_lowpart_common since it can do the wrong thing when
6217 RELOADREG has a multi-word mode. Note that RELOADREG
6218 must always be a REG here. */
6220 if (GET_MODE (reloadreg
) != mode
)
6221 reloadreg
= reload_adjust_reg_for_mode (reloadreg
, mode
);
6222 while (GET_CODE (oldequiv
) == SUBREG
&& GET_MODE (oldequiv
) != mode
)
6223 oldequiv
= SUBREG_REG (oldequiv
);
6224 if (GET_MODE (oldequiv
) != VOIDmode
6225 && mode
!= GET_MODE (oldequiv
))
6226 oldequiv
= gen_lowpart_SUBREG (mode
, oldequiv
);
6228 /* Switch to the right place to emit the reload insns. */
6229 switch (rl
->when_needed
)
6232 where
= &other_input_reload_insns
;
6234 case RELOAD_FOR_INPUT
:
6235 where
= &input_reload_insns
[rl
->opnum
];
6237 case RELOAD_FOR_INPUT_ADDRESS
:
6238 where
= &input_address_reload_insns
[rl
->opnum
];
6240 case RELOAD_FOR_INPADDR_ADDRESS
:
6241 where
= &inpaddr_address_reload_insns
[rl
->opnum
];
6243 case RELOAD_FOR_OUTPUT_ADDRESS
:
6244 where
= &output_address_reload_insns
[rl
->opnum
];
6246 case RELOAD_FOR_OUTADDR_ADDRESS
:
6247 where
= &outaddr_address_reload_insns
[rl
->opnum
];
6249 case RELOAD_FOR_OPERAND_ADDRESS
:
6250 where
= &operand_reload_insns
;
6252 case RELOAD_FOR_OPADDR_ADDR
:
6253 where
= &other_operand_reload_insns
;
6255 case RELOAD_FOR_OTHER_ADDRESS
:
6256 where
= &other_input_address_reload_insns
;
6262 push_to_sequence (*where
);
6264 /* Auto-increment addresses must be reloaded in a special way. */
6265 if (rl
->out
&& ! rl
->out_reg
)
6267 /* We are not going to bother supporting the case where a
6268 incremented register can't be copied directly from
6269 OLDEQUIV since this seems highly unlikely. */
6270 if (rl
->secondary_in_reload
>= 0)
6273 if (reload_inherited
[j
])
6274 oldequiv
= reloadreg
;
6276 old
= XEXP (rl
->in_reg
, 0);
6278 if (optimize
&& GET_CODE (oldequiv
) == REG
6279 && REGNO (oldequiv
) < FIRST_PSEUDO_REGISTER
6280 && spill_reg_store
[REGNO (oldequiv
)]
6281 && GET_CODE (old
) == REG
6282 && (dead_or_set_p (insn
,
6283 spill_reg_stored_to
[REGNO (oldequiv
)])
6284 || rtx_equal_p (spill_reg_stored_to
[REGNO (oldequiv
)],
6286 delete_output_reload (insn
, j
, REGNO (oldequiv
));
6288 /* Prevent normal processing of this reload. */
6290 /* Output a special code sequence for this case. */
6291 new_spill_reg_store
[REGNO (reloadreg
)]
6292 = inc_for_reload (reloadreg
, oldequiv
, rl
->out
,
6296 /* If we are reloading a pseudo-register that was set by the previous
6297 insn, see if we can get rid of that pseudo-register entirely
6298 by redirecting the previous insn into our reload register. */
6300 else if (optimize
&& GET_CODE (old
) == REG
6301 && REGNO (old
) >= FIRST_PSEUDO_REGISTER
6302 && dead_or_set_p (insn
, old
)
6303 /* This is unsafe if some other reload
6304 uses the same reg first. */
6305 && ! conflicts_with_override (reloadreg
)
6306 && free_for_value_p (REGNO (reloadreg
), rl
->mode
, rl
->opnum
,
6307 rl
->when_needed
, old
, rl
->out
, j
, 0))
6309 rtx temp
= PREV_INSN (insn
);
6310 while (temp
&& GET_CODE (temp
) == NOTE
)
6311 temp
= PREV_INSN (temp
);
6313 && GET_CODE (temp
) == INSN
6314 && GET_CODE (PATTERN (temp
)) == SET
6315 && SET_DEST (PATTERN (temp
)) == old
6316 /* Make sure we can access insn_operand_constraint. */
6317 && asm_noperands (PATTERN (temp
)) < 0
6318 /* This is unsafe if operand occurs more than once in current
6319 insn. Perhaps some occurrences aren't reloaded. */
6320 && count_occurrences (PATTERN (insn
), old
, 0) == 1)
6322 rtx old
= SET_DEST (PATTERN (temp
));
6323 /* Store into the reload register instead of the pseudo. */
6324 SET_DEST (PATTERN (temp
)) = reloadreg
;
6326 /* Verify that resulting insn is valid. */
6327 extract_insn (temp
);
6328 if (constrain_operands (1))
6330 /* If the previous insn is an output reload, the source is
6331 a reload register, and its spill_reg_store entry will
6332 contain the previous destination. This is now
6334 if (GET_CODE (SET_SRC (PATTERN (temp
))) == REG
6335 && REGNO (SET_SRC (PATTERN (temp
))) < FIRST_PSEUDO_REGISTER
)
6337 spill_reg_store
[REGNO (SET_SRC (PATTERN (temp
)))] = 0;
6338 spill_reg_stored_to
[REGNO (SET_SRC (PATTERN (temp
)))] = 0;
6341 /* If these are the only uses of the pseudo reg,
6342 pretend for GDB it lives in the reload reg we used. */
6343 if (REG_N_DEATHS (REGNO (old
)) == 1
6344 && REG_N_SETS (REGNO (old
)) == 1)
6346 reg_renumber
[REGNO (old
)] = REGNO (rl
->reg_rtx
);
6347 alter_reg (REGNO (old
), -1);
6353 SET_DEST (PATTERN (temp
)) = old
;
6358 /* We can't do that, so output an insn to load RELOADREG. */
6360 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6361 /* If we have a secondary reload, pick up the secondary register
6362 and icode, if any. If OLDEQUIV and OLD are different or
6363 if this is an in-out reload, recompute whether or not we
6364 still need a secondary register and what the icode should
6365 be. If we still need a secondary register and the class or
6366 icode is different, go back to reloading from OLD if using
6367 OLDEQUIV means that we got the wrong type of register. We
6368 cannot have different class or icode due to an in-out reload
6369 because we don't make such reloads when both the input and
6370 output need secondary reload registers. */
6372 if (! special
&& rl
->secondary_in_reload
>= 0)
6374 rtx second_reload_reg
= 0;
6375 int secondary_reload
= rl
->secondary_in_reload
;
6376 rtx real_oldequiv
= oldequiv
;
6379 enum insn_code icode
;
6381 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
6382 and similarly for OLD.
6383 See comments in get_secondary_reload in reload.c. */
6384 /* If it is a pseudo that cannot be replaced with its
6385 equivalent MEM, we must fall back to reload_in, which
6386 will have all the necessary substitutions registered.
6387 Likewise for a pseudo that can't be replaced with its
6388 equivalent constant.
6390 Take extra care for subregs of such pseudos. Note that
6391 we cannot use reg_equiv_mem in this case because it is
6392 not in the right mode. */
6395 if (GET_CODE (tmp
) == SUBREG
)
6396 tmp
= SUBREG_REG (tmp
);
6397 if (GET_CODE (tmp
) == REG
6398 && REGNO (tmp
) >= FIRST_PSEUDO_REGISTER
6399 && (reg_equiv_memory_loc
[REGNO (tmp
)] != 0
6400 || reg_equiv_constant
[REGNO (tmp
)] != 0))
6402 if (! reg_equiv_mem
[REGNO (tmp
)]
6403 || num_not_at_initial_offset
6404 || GET_CODE (oldequiv
) == SUBREG
)
6405 real_oldequiv
= rl
->in
;
6407 real_oldequiv
= reg_equiv_mem
[REGNO (tmp
)];
6411 if (GET_CODE (tmp
) == SUBREG
)
6412 tmp
= SUBREG_REG (tmp
);
6413 if (GET_CODE (tmp
) == REG
6414 && REGNO (tmp
) >= FIRST_PSEUDO_REGISTER
6415 && (reg_equiv_memory_loc
[REGNO (tmp
)] != 0
6416 || reg_equiv_constant
[REGNO (tmp
)] != 0))
6418 if (! reg_equiv_mem
[REGNO (tmp
)]
6419 || num_not_at_initial_offset
6420 || GET_CODE (old
) == SUBREG
)
6423 real_old
= reg_equiv_mem
[REGNO (tmp
)];
6426 second_reload_reg
= rld
[secondary_reload
].reg_rtx
;
6427 icode
= rl
->secondary_in_icode
;
6429 if ((old
!= oldequiv
&& ! rtx_equal_p (old
, oldequiv
))
6430 || (rl
->in
!= 0 && rl
->out
!= 0))
6432 enum reg_class new_class
6433 = SECONDARY_INPUT_RELOAD_CLASS (rl
->class,
6434 mode
, real_oldequiv
);
6436 if (new_class
== NO_REGS
)
6437 second_reload_reg
= 0;
6440 enum insn_code new_icode
;
6441 enum machine_mode new_mode
;
6443 if (! TEST_HARD_REG_BIT (reg_class_contents
[(int) new_class
],
6444 REGNO (second_reload_reg
)))
6445 oldequiv
= old
, real_oldequiv
= real_old
;
6448 new_icode
= reload_in_optab
[(int) mode
];
6449 if (new_icode
!= CODE_FOR_nothing
6450 && ((insn_data
[(int) new_icode
].operand
[0].predicate
6451 && ! ((*insn_data
[(int) new_icode
].operand
[0].predicate
)
6453 || (insn_data
[(int) new_icode
].operand
[1].predicate
6454 && ! ((*insn_data
[(int) new_icode
].operand
[1].predicate
)
6455 (real_oldequiv
, mode
)))))
6456 new_icode
= CODE_FOR_nothing
;
6458 if (new_icode
== CODE_FOR_nothing
)
6461 new_mode
= insn_data
[(int) new_icode
].operand
[2].mode
;
6463 if (GET_MODE (second_reload_reg
) != new_mode
)
6465 if (!HARD_REGNO_MODE_OK (REGNO (second_reload_reg
),
6467 oldequiv
= old
, real_oldequiv
= real_old
;
6470 = reload_adjust_reg_for_mode (second_reload_reg
,
6477 /* If we still need a secondary reload register, check
6478 to see if it is being used as a scratch or intermediate
6479 register and generate code appropriately. If we need
6480 a scratch register, use REAL_OLDEQUIV since the form of
6481 the insn may depend on the actual address if it is
6484 if (second_reload_reg
)
6486 if (icode
!= CODE_FOR_nothing
)
6488 emit_insn (GEN_FCN (icode
) (reloadreg
, real_oldequiv
,
6489 second_reload_reg
));
6494 /* See if we need a scratch register to load the
6495 intermediate register (a tertiary reload). */
6496 enum insn_code tertiary_icode
6497 = rld
[secondary_reload
].secondary_in_icode
;
6499 if (tertiary_icode
!= CODE_FOR_nothing
)
6501 rtx third_reload_reg
6502 = rld
[rld
[secondary_reload
].secondary_in_reload
].reg_rtx
;
6504 emit_insn ((GEN_FCN (tertiary_icode
)
6505 (second_reload_reg
, real_oldequiv
,
6506 third_reload_reg
)));
6509 gen_reload (second_reload_reg
, real_oldequiv
,
6513 oldequiv
= second_reload_reg
;
6519 if (! special
&& ! rtx_equal_p (reloadreg
, oldequiv
))
6521 rtx real_oldequiv
= oldequiv
;
6523 if ((GET_CODE (oldequiv
) == REG
6524 && REGNO (oldequiv
) >= FIRST_PSEUDO_REGISTER
6525 && (reg_equiv_memory_loc
[REGNO (oldequiv
)] != 0
6526 || reg_equiv_constant
[REGNO (oldequiv
)] != 0))
6527 || (GET_CODE (oldequiv
) == SUBREG
6528 && GET_CODE (SUBREG_REG (oldequiv
)) == REG
6529 && (REGNO (SUBREG_REG (oldequiv
))
6530 >= FIRST_PSEUDO_REGISTER
)
6531 && ((reg_equiv_memory_loc
6532 [REGNO (SUBREG_REG (oldequiv
))] != 0)
6533 || (reg_equiv_constant
6534 [REGNO (SUBREG_REG (oldequiv
))] != 0)))
6535 || (CONSTANT_P (oldequiv
)
6536 && (PREFERRED_RELOAD_CLASS (oldequiv
,
6537 REGNO_REG_CLASS (REGNO (reloadreg
)))
6539 real_oldequiv
= rl
->in
;
6540 gen_reload (reloadreg
, real_oldequiv
, rl
->opnum
,
6544 if (flag_non_call_exceptions
)
6545 copy_eh_notes (insn
, get_insns ());
6547 /* End this sequence. */
6548 *where
= get_insns ();
6551 /* Update reload_override_in so that delete_address_reloads_1
6552 can see the actual register usage. */
6554 reload_override_in
[j
] = oldequiv
;
6557 /* Generate insns to for the output reload RL, which is for the insn described
6558 by CHAIN and has the number J. */
6560 emit_output_reload_insns (struct insn_chain
*chain
, struct reload
*rl
,
6563 rtx reloadreg
= rl
->reg_rtx
;
6564 rtx insn
= chain
->insn
;
6567 enum machine_mode mode
= GET_MODE (old
);
6570 if (rl
->when_needed
== RELOAD_OTHER
)
6573 push_to_sequence (output_reload_insns
[rl
->opnum
]);
6575 /* Determine the mode to reload in.
6576 See comments above (for input reloading). */
6578 if (mode
== VOIDmode
)
6580 /* VOIDmode should never happen for an output. */
6581 if (asm_noperands (PATTERN (insn
)) < 0)
6582 /* It's the compiler's fault. */
6583 fatal_insn ("VOIDmode on an output", insn
);
6584 error_for_asm (insn
, "output operand is constant in `asm'");
6585 /* Prevent crash--use something we know is valid. */
6587 old
= gen_rtx_REG (mode
, REGNO (reloadreg
));
6590 if (GET_MODE (reloadreg
) != mode
)
6591 reloadreg
= reload_adjust_reg_for_mode (reloadreg
, mode
);
6593 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
6595 /* If we need two reload regs, set RELOADREG to the intermediate
6596 one, since it will be stored into OLD. We might need a secondary
6597 register only for an input reload, so check again here. */
6599 if (rl
->secondary_out_reload
>= 0)
6603 if (GET_CODE (old
) == REG
&& REGNO (old
) >= FIRST_PSEUDO_REGISTER
6604 && reg_equiv_mem
[REGNO (old
)] != 0)
6605 real_old
= reg_equiv_mem
[REGNO (old
)];
6607 if ((SECONDARY_OUTPUT_RELOAD_CLASS (rl
->class,
6611 rtx second_reloadreg
= reloadreg
;
6612 reloadreg
= rld
[rl
->secondary_out_reload
].reg_rtx
;
6614 /* See if RELOADREG is to be used as a scratch register
6615 or as an intermediate register. */
6616 if (rl
->secondary_out_icode
!= CODE_FOR_nothing
)
6618 emit_insn ((GEN_FCN (rl
->secondary_out_icode
)
6619 (real_old
, second_reloadreg
, reloadreg
)));
6624 /* See if we need both a scratch and intermediate reload
6627 int secondary_reload
= rl
->secondary_out_reload
;
6628 enum insn_code tertiary_icode
6629 = rld
[secondary_reload
].secondary_out_icode
;
6631 if (GET_MODE (reloadreg
) != mode
)
6632 reloadreg
= reload_adjust_reg_for_mode (reloadreg
, mode
);
6634 if (tertiary_icode
!= CODE_FOR_nothing
)
6637 = rld
[rld
[secondary_reload
].secondary_out_reload
].reg_rtx
;
6640 /* Copy primary reload reg to secondary reload reg.
6641 (Note that these have been swapped above, then
6642 secondary reload reg to OLD using our insn.) */
6644 /* If REAL_OLD is a paradoxical SUBREG, remove it
6645 and try to put the opposite SUBREG on
6647 if (GET_CODE (real_old
) == SUBREG
6648 && (GET_MODE_SIZE (GET_MODE (real_old
))
6649 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (real_old
))))
6650 && 0 != (tem
= gen_lowpart_common
6651 (GET_MODE (SUBREG_REG (real_old
)),
6653 real_old
= SUBREG_REG (real_old
), reloadreg
= tem
;
6655 gen_reload (reloadreg
, second_reloadreg
,
6656 rl
->opnum
, rl
->when_needed
);
6657 emit_insn ((GEN_FCN (tertiary_icode
)
6658 (real_old
, reloadreg
, third_reloadreg
)));
6663 /* Copy between the reload regs here and then to
6666 gen_reload (reloadreg
, second_reloadreg
,
6667 rl
->opnum
, rl
->when_needed
);
6673 /* Output the last reload insn. */
6678 /* Don't output the last reload if OLD is not the dest of
6679 INSN and is in the src and is clobbered by INSN. */
6680 if (! flag_expensive_optimizations
6681 || GET_CODE (old
) != REG
6682 || !(set
= single_set (insn
))
6683 || rtx_equal_p (old
, SET_DEST (set
))
6684 || !reg_mentioned_p (old
, SET_SRC (set
))
6685 || !regno_clobbered_p (REGNO (old
), insn
, rl
->mode
, 0))
6686 gen_reload (old
, reloadreg
, rl
->opnum
,
6690 /* Look at all insns we emitted, just to be safe. */
6691 for (p
= get_insns (); p
; p
= NEXT_INSN (p
))
6694 rtx pat
= PATTERN (p
);
6696 /* If this output reload doesn't come from a spill reg,
6697 clear any memory of reloaded copies of the pseudo reg.
6698 If this output reload comes from a spill reg,
6699 reg_has_output_reload will make this do nothing. */
6700 note_stores (pat
, forget_old_reloads_1
, NULL
);
6702 if (reg_mentioned_p (rl
->reg_rtx
, pat
))
6704 rtx set
= single_set (insn
);
6705 if (reload_spill_index
[j
] < 0
6707 && SET_SRC (set
) == rl
->reg_rtx
)
6709 int src
= REGNO (SET_SRC (set
));
6711 reload_spill_index
[j
] = src
;
6712 SET_HARD_REG_BIT (reg_is_output_reload
, src
);
6713 if (find_regno_note (insn
, REG_DEAD
, src
))
6714 SET_HARD_REG_BIT (reg_reloaded_died
, src
);
6716 if (REGNO (rl
->reg_rtx
) < FIRST_PSEUDO_REGISTER
)
6718 int s
= rl
->secondary_out_reload
;
6719 set
= single_set (p
);
6720 /* If this reload copies only to the secondary reload
6721 register, the secondary reload does the actual
6723 if (s
>= 0 && set
== NULL_RTX
)
6724 /* We can't tell what function the secondary reload
6725 has and where the actual store to the pseudo is
6726 made; leave new_spill_reg_store alone. */
6729 && SET_SRC (set
) == rl
->reg_rtx
6730 && SET_DEST (set
) == rld
[s
].reg_rtx
)
6732 /* Usually the next instruction will be the
6733 secondary reload insn; if we can confirm
6734 that it is, setting new_spill_reg_store to
6735 that insn will allow an extra optimization. */
6736 rtx s_reg
= rld
[s
].reg_rtx
;
6737 rtx next
= NEXT_INSN (p
);
6738 rld
[s
].out
= rl
->out
;
6739 rld
[s
].out_reg
= rl
->out_reg
;
6740 set
= single_set (next
);
6741 if (set
&& SET_SRC (set
) == s_reg
6742 && ! new_spill_reg_store
[REGNO (s_reg
)])
6744 SET_HARD_REG_BIT (reg_is_output_reload
,
6746 new_spill_reg_store
[REGNO (s_reg
)] = next
;
6750 new_spill_reg_store
[REGNO (rl
->reg_rtx
)] = p
;
6755 if (rl
->when_needed
== RELOAD_OTHER
)
6757 emit_insn (other_output_reload_insns
[rl
->opnum
]);
6758 other_output_reload_insns
[rl
->opnum
] = get_insns ();
6761 output_reload_insns
[rl
->opnum
] = get_insns ();
6763 if (flag_non_call_exceptions
)
6764 copy_eh_notes (insn
, get_insns ());
6769 /* Do input reloading for reload RL, which is for the insn described by CHAIN
6770 and has the number J. */
6772 do_input_reload (struct insn_chain
*chain
, struct reload
*rl
, int j
)
6774 rtx insn
= chain
->insn
;
6775 rtx old
= (rl
->in
&& GET_CODE (rl
->in
) == MEM
6776 ? rl
->in_reg
: rl
->in
);
6779 /* AUTO_INC reloads need to be handled even if inherited. We got an
6780 AUTO_INC reload if reload_out is set but reload_out_reg isn't. */
6781 && (! reload_inherited
[j
] || (rl
->out
&& ! rl
->out_reg
))
6782 && ! rtx_equal_p (rl
->reg_rtx
, old
)
6783 && rl
->reg_rtx
!= 0)
6784 emit_input_reload_insns (chain
, rld
+ j
, old
, j
);
6786 /* When inheriting a wider reload, we have a MEM in rl->in,
6787 e.g. inheriting a SImode output reload for
6788 (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */
6789 if (optimize
&& reload_inherited
[j
] && rl
->in
6790 && GET_CODE (rl
->in
) == MEM
6791 && GET_CODE (rl
->in_reg
) == MEM
6792 && reload_spill_index
[j
] >= 0
6793 && TEST_HARD_REG_BIT (reg_reloaded_valid
, reload_spill_index
[j
]))
6794 rl
->in
= regno_reg_rtx
[reg_reloaded_contents
[reload_spill_index
[j
]]];
6796 /* If we are reloading a register that was recently stored in with an
6797 output-reload, see if we can prove there was
6798 actually no need to store the old value in it. */
6801 && (reload_inherited
[j
] || reload_override_in
[j
])
6803 && GET_CODE (rl
->reg_rtx
) == REG
6804 && spill_reg_store
[REGNO (rl
->reg_rtx
)] != 0
6806 /* There doesn't seem to be any reason to restrict this to pseudos
6807 and doing so loses in the case where we are copying from a
6808 register of the wrong class. */
6809 && (REGNO (spill_reg_stored_to
[REGNO (rl
->reg_rtx
)])
6810 >= FIRST_PSEUDO_REGISTER
)
6812 /* The insn might have already some references to stackslots
6813 replaced by MEMs, while reload_out_reg still names the
6815 && (dead_or_set_p (insn
,
6816 spill_reg_stored_to
[REGNO (rl
->reg_rtx
)])
6817 || rtx_equal_p (spill_reg_stored_to
[REGNO (rl
->reg_rtx
)],
6819 delete_output_reload (insn
, j
, REGNO (rl
->reg_rtx
));
6822 /* Do output reloading for reload RL, which is for the insn described by
6823 CHAIN and has the number J.
6824 ??? At some point we need to support handling output reloads of
6825 JUMP_INSNs or insns that set cc0. */
6827 do_output_reload (struct insn_chain
*chain
, struct reload
*rl
, int j
)
6830 rtx insn
= chain
->insn
;
6831 /* If this is an output reload that stores something that is
6832 not loaded in this same reload, see if we can eliminate a previous
6834 rtx pseudo
= rl
->out_reg
;
6838 && GET_CODE (pseudo
) == REG
6839 && ! rtx_equal_p (rl
->in_reg
, pseudo
)
6840 && REGNO (pseudo
) >= FIRST_PSEUDO_REGISTER
6841 && reg_last_reload_reg
[REGNO (pseudo
)])
6843 int pseudo_no
= REGNO (pseudo
);
6844 int last_regno
= REGNO (reg_last_reload_reg
[pseudo_no
]);
6846 /* We don't need to test full validity of last_regno for
6847 inherit here; we only want to know if the store actually
6848 matches the pseudo. */
6849 if (TEST_HARD_REG_BIT (reg_reloaded_valid
, last_regno
)
6850 && reg_reloaded_contents
[last_regno
] == pseudo_no
6851 && spill_reg_store
[last_regno
]
6852 && rtx_equal_p (pseudo
, spill_reg_stored_to
[last_regno
]))
6853 delete_output_reload (insn
, j
, last_regno
);
6858 || rl
->reg_rtx
== old
6859 || rl
->reg_rtx
== 0)
6862 /* An output operand that dies right away does need a reload,
6863 but need not be copied from it. Show the new location in the
6865 if ((GET_CODE (old
) == REG
|| GET_CODE (old
) == SCRATCH
)
6866 && (note
= find_reg_note (insn
, REG_UNUSED
, old
)) != 0)
6868 XEXP (note
, 0) = rl
->reg_rtx
;
6871 /* Likewise for a SUBREG of an operand that dies. */
6872 else if (GET_CODE (old
) == SUBREG
6873 && GET_CODE (SUBREG_REG (old
)) == REG
6874 && 0 != (note
= find_reg_note (insn
, REG_UNUSED
,
6877 XEXP (note
, 0) = gen_lowpart_common (GET_MODE (old
),
6881 else if (GET_CODE (old
) == SCRATCH
)
6882 /* If we aren't optimizing, there won't be a REG_UNUSED note,
6883 but we don't want to make an output reload. */
6886 /* If is a JUMP_INSN, we can't support output reloads yet. */
6887 if (GET_CODE (insn
) == JUMP_INSN
)
6890 emit_output_reload_insns (chain
, rld
+ j
, j
);
6893 /* Output insns to reload values in and out of the chosen reload regs. */
6896 emit_reload_insns (struct insn_chain
*chain
)
6898 rtx insn
= chain
->insn
;
6902 CLEAR_HARD_REG_SET (reg_reloaded_died
);
6904 for (j
= 0; j
< reload_n_operands
; j
++)
6905 input_reload_insns
[j
] = input_address_reload_insns
[j
]
6906 = inpaddr_address_reload_insns
[j
]
6907 = output_reload_insns
[j
] = output_address_reload_insns
[j
]
6908 = outaddr_address_reload_insns
[j
]
6909 = other_output_reload_insns
[j
] = 0;
6910 other_input_address_reload_insns
= 0;
6911 other_input_reload_insns
= 0;
6912 operand_reload_insns
= 0;
6913 other_operand_reload_insns
= 0;
6915 /* Dump reloads into the dump file. */
6918 fprintf (rtl_dump_file
, "\nReloads for insn # %d\n", INSN_UID (insn
));
6919 debug_reload_to_stream (rtl_dump_file
);
6922 /* Now output the instructions to copy the data into and out of the
6923 reload registers. Do these in the order that the reloads were reported,
6924 since reloads of base and index registers precede reloads of operands
6925 and the operands may need the base and index registers reloaded. */
6927 for (j
= 0; j
< n_reloads
; j
++)
6930 && REGNO (rld
[j
].reg_rtx
) < FIRST_PSEUDO_REGISTER
)
6931 new_spill_reg_store
[REGNO (rld
[j
].reg_rtx
)] = 0;
6933 do_input_reload (chain
, rld
+ j
, j
);
6934 do_output_reload (chain
, rld
+ j
, j
);
6937 /* Now write all the insns we made for reloads in the order expected by
6938 the allocation functions. Prior to the insn being reloaded, we write
6939 the following reloads:
6941 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
6943 RELOAD_OTHER reloads.
6945 For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
6946 by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
6947 RELOAD_FOR_INPUT reload for the operand.
6949 RELOAD_FOR_OPADDR_ADDRS reloads.
6951 RELOAD_FOR_OPERAND_ADDRESS reloads.
6953 After the insn being reloaded, we write the following:
6955 For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
6956 by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
6957 RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
6958 reloads for the operand. The RELOAD_OTHER output reloads are
6959 output in descending order by reload number. */
6961 emit_insn_before (other_input_address_reload_insns
, insn
);
6962 emit_insn_before (other_input_reload_insns
, insn
);
6964 for (j
= 0; j
< reload_n_operands
; j
++)
6966 emit_insn_before (inpaddr_address_reload_insns
[j
], insn
);
6967 emit_insn_before (input_address_reload_insns
[j
], insn
);
6968 emit_insn_before (input_reload_insns
[j
], insn
);
6971 emit_insn_before (other_operand_reload_insns
, insn
);
6972 emit_insn_before (operand_reload_insns
, insn
);
6974 for (j
= 0; j
< reload_n_operands
; j
++)
6976 rtx x
= emit_insn_after (outaddr_address_reload_insns
[j
], insn
);
6977 x
= emit_insn_after (output_address_reload_insns
[j
], x
);
6978 x
= emit_insn_after (output_reload_insns
[j
], x
);
6979 emit_insn_after (other_output_reload_insns
[j
], x
);
6982 /* For all the spill regs newly reloaded in this instruction,
6983 record what they were reloaded from, so subsequent instructions
6984 can inherit the reloads.
6986 Update spill_reg_store for the reloads of this insn.
6987 Copy the elements that were updated in the loop above. */
6989 for (j
= 0; j
< n_reloads
; j
++)
6991 int r
= reload_order
[j
];
6992 int i
= reload_spill_index
[r
];
6994 /* If this is a non-inherited input reload from a pseudo, we must
6995 clear any memory of a previous store to the same pseudo. Only do
6996 something if there will not be an output reload for the pseudo
6998 if (rld
[r
].in_reg
!= 0
6999 && ! (reload_inherited
[r
] || reload_override_in
[r
]))
7001 rtx reg
= rld
[r
].in_reg
;
7003 if (GET_CODE (reg
) == SUBREG
)
7004 reg
= SUBREG_REG (reg
);
7006 if (GET_CODE (reg
) == REG
7007 && REGNO (reg
) >= FIRST_PSEUDO_REGISTER
7008 && ! reg_has_output_reload
[REGNO (reg
)])
7010 int nregno
= REGNO (reg
);
7012 if (reg_last_reload_reg
[nregno
])
7014 int last_regno
= REGNO (reg_last_reload_reg
[nregno
]);
7016 if (reg_reloaded_contents
[last_regno
] == nregno
)
7017 spill_reg_store
[last_regno
] = 0;
7022 /* I is nonneg if this reload used a register.
7023 If rld[r].reg_rtx is 0, this is an optional reload
7024 that we opted to ignore. */
7026 if (i
>= 0 && rld
[r
].reg_rtx
!= 0)
7028 int nr
= HARD_REGNO_NREGS (i
, GET_MODE (rld
[r
].reg_rtx
));
7030 int part_reaches_end
= 0;
7031 int all_reaches_end
= 1;
7033 /* For a multi register reload, we need to check if all or part
7034 of the value lives to the end. */
7035 for (k
= 0; k
< nr
; k
++)
7037 if (reload_reg_reaches_end_p (i
+ k
, rld
[r
].opnum
,
7038 rld
[r
].when_needed
))
7039 part_reaches_end
= 1;
7041 all_reaches_end
= 0;
7044 /* Ignore reloads that don't reach the end of the insn in
7046 if (all_reaches_end
)
7048 /* First, clear out memory of what used to be in this spill reg.
7049 If consecutive registers are used, clear them all. */
7051 for (k
= 0; k
< nr
; k
++)
7052 CLEAR_HARD_REG_BIT (reg_reloaded_valid
, i
+ k
);
7054 /* Maybe the spill reg contains a copy of reload_out. */
7056 && (GET_CODE (rld
[r
].out
) == REG
7060 || GET_CODE (rld
[r
].out_reg
) == REG
))
7062 rtx out
= (GET_CODE (rld
[r
].out
) == REG
7066 /* AUTO_INC */ : XEXP (rld
[r
].in_reg
, 0));
7067 int nregno
= REGNO (out
);
7068 int nnr
= (nregno
>= FIRST_PSEUDO_REGISTER
? 1
7069 : HARD_REGNO_NREGS (nregno
,
7070 GET_MODE (rld
[r
].reg_rtx
)));
7072 spill_reg_store
[i
] = new_spill_reg_store
[i
];
7073 spill_reg_stored_to
[i
] = out
;
7074 reg_last_reload_reg
[nregno
] = rld
[r
].reg_rtx
;
7076 /* If NREGNO is a hard register, it may occupy more than
7077 one register. If it does, say what is in the
7078 rest of the registers assuming that both registers
7079 agree on how many words the object takes. If not,
7080 invalidate the subsequent registers. */
7082 if (nregno
< FIRST_PSEUDO_REGISTER
)
7083 for (k
= 1; k
< nnr
; k
++)
7084 reg_last_reload_reg
[nregno
+ k
]
7086 ? regno_reg_rtx
[REGNO (rld
[r
].reg_rtx
) + k
]
7089 /* Now do the inverse operation. */
7090 for (k
= 0; k
< nr
; k
++)
7092 CLEAR_HARD_REG_BIT (reg_reloaded_dead
, i
+ k
);
7093 reg_reloaded_contents
[i
+ k
]
7094 = (nregno
>= FIRST_PSEUDO_REGISTER
|| nr
!= nnr
7097 reg_reloaded_insn
[i
+ k
] = insn
;
7098 SET_HARD_REG_BIT (reg_reloaded_valid
, i
+ k
);
7102 /* Maybe the spill reg contains a copy of reload_in. Only do
7103 something if there will not be an output reload for
7104 the register being reloaded. */
7105 else if (rld
[r
].out_reg
== 0
7107 && ((GET_CODE (rld
[r
].in
) == REG
7108 && REGNO (rld
[r
].in
) >= FIRST_PSEUDO_REGISTER
7109 && ! reg_has_output_reload
[REGNO (rld
[r
].in
)])
7110 || (GET_CODE (rld
[r
].in_reg
) == REG
7111 && ! reg_has_output_reload
[REGNO (rld
[r
].in_reg
)]))
7112 && ! reg_set_p (rld
[r
].reg_rtx
, PATTERN (insn
)))
7117 if (GET_CODE (rld
[r
].in
) == REG
7118 && REGNO (rld
[r
].in
) >= FIRST_PSEUDO_REGISTER
)
7119 nregno
= REGNO (rld
[r
].in
);
7120 else if (GET_CODE (rld
[r
].in_reg
) == REG
)
7121 nregno
= REGNO (rld
[r
].in_reg
);
7123 nregno
= REGNO (XEXP (rld
[r
].in_reg
, 0));
7125 nnr
= (nregno
>= FIRST_PSEUDO_REGISTER
? 1
7126 : HARD_REGNO_NREGS (nregno
,
7127 GET_MODE (rld
[r
].reg_rtx
)));
7129 reg_last_reload_reg
[nregno
] = rld
[r
].reg_rtx
;
7131 if (nregno
< FIRST_PSEUDO_REGISTER
)
7132 for (k
= 1; k
< nnr
; k
++)
7133 reg_last_reload_reg
[nregno
+ k
]
7135 ? regno_reg_rtx
[REGNO (rld
[r
].reg_rtx
) + k
]
7138 /* Unless we inherited this reload, show we haven't
7139 recently done a store.
7140 Previous stores of inherited auto_inc expressions
7141 also have to be discarded. */
7142 if (! reload_inherited
[r
]
7143 || (rld
[r
].out
&& ! rld
[r
].out_reg
))
7144 spill_reg_store
[i
] = 0;
7146 for (k
= 0; k
< nr
; k
++)
7148 CLEAR_HARD_REG_BIT (reg_reloaded_dead
, i
+ k
);
7149 reg_reloaded_contents
[i
+ k
]
7150 = (nregno
>= FIRST_PSEUDO_REGISTER
|| nr
!= nnr
7153 reg_reloaded_insn
[i
+ k
] = insn
;
7154 SET_HARD_REG_BIT (reg_reloaded_valid
, i
+ k
);
7159 /* However, if part of the reload reaches the end, then we must
7160 invalidate the old info for the part that survives to the end. */
7161 else if (part_reaches_end
)
7163 for (k
= 0; k
< nr
; k
++)
7164 if (reload_reg_reaches_end_p (i
+ k
,
7166 rld
[r
].when_needed
))
7167 CLEAR_HARD_REG_BIT (reg_reloaded_valid
, i
+ k
);
7171 /* The following if-statement was #if 0'd in 1.34 (or before...).
7172 It's reenabled in 1.35 because supposedly nothing else
7173 deals with this problem. */
7175 /* If a register gets output-reloaded from a non-spill register,
7176 that invalidates any previous reloaded copy of it.
7177 But forget_old_reloads_1 won't get to see it, because
7178 it thinks only about the original insn. So invalidate it here. */
7179 if (i
< 0 && rld
[r
].out
!= 0
7180 && (GET_CODE (rld
[r
].out
) == REG
7181 || (GET_CODE (rld
[r
].out
) == MEM
7182 && GET_CODE (rld
[r
].out_reg
) == REG
)))
7184 rtx out
= (GET_CODE (rld
[r
].out
) == REG
7185 ? rld
[r
].out
: rld
[r
].out_reg
);
7186 int nregno
= REGNO (out
);
7187 if (nregno
>= FIRST_PSEUDO_REGISTER
)
7189 rtx src_reg
, store_insn
= NULL_RTX
;
7191 reg_last_reload_reg
[nregno
] = 0;
7193 /* If we can find a hard register that is stored, record
7194 the storing insn so that we may delete this insn with
7195 delete_output_reload. */
7196 src_reg
= rld
[r
].reg_rtx
;
7198 /* If this is an optional reload, try to find the source reg
7199 from an input reload. */
7202 rtx set
= single_set (insn
);
7203 if (set
&& SET_DEST (set
) == rld
[r
].out
)
7207 src_reg
= SET_SRC (set
);
7209 for (k
= 0; k
< n_reloads
; k
++)
7211 if (rld
[k
].in
== src_reg
)
7213 src_reg
= rld
[k
].reg_rtx
;
7220 store_insn
= new_spill_reg_store
[REGNO (src_reg
)];
7221 if (src_reg
&& GET_CODE (src_reg
) == REG
7222 && REGNO (src_reg
) < FIRST_PSEUDO_REGISTER
)
7224 int src_regno
= REGNO (src_reg
);
7225 int nr
= HARD_REGNO_NREGS (src_regno
, rld
[r
].mode
);
7226 /* The place where to find a death note varies with
7227 PRESERVE_DEATH_INFO_REGNO_P . The condition is not
7228 necessarily checked exactly in the code that moves
7229 notes, so just check both locations. */
7230 rtx note
= find_regno_note (insn
, REG_DEAD
, src_regno
);
7231 if (! note
&& store_insn
)
7232 note
= find_regno_note (store_insn
, REG_DEAD
, src_regno
);
7235 spill_reg_store
[src_regno
+ nr
] = store_insn
;
7236 spill_reg_stored_to
[src_regno
+ nr
] = out
;
7237 reg_reloaded_contents
[src_regno
+ nr
] = nregno
;
7238 reg_reloaded_insn
[src_regno
+ nr
] = store_insn
;
7239 CLEAR_HARD_REG_BIT (reg_reloaded_dead
, src_regno
+ nr
);
7240 SET_HARD_REG_BIT (reg_reloaded_valid
, src_regno
+ nr
);
7241 SET_HARD_REG_BIT (reg_is_output_reload
, src_regno
+ nr
);
7243 SET_HARD_REG_BIT (reg_reloaded_died
, src_regno
);
7245 CLEAR_HARD_REG_BIT (reg_reloaded_died
, src_regno
);
7247 reg_last_reload_reg
[nregno
] = src_reg
;
7252 int num_regs
= HARD_REGNO_NREGS (nregno
, GET_MODE (rld
[r
].out
));
7254 while (num_regs
-- > 0)
7255 reg_last_reload_reg
[nregno
+ num_regs
] = 0;
7259 IOR_HARD_REG_SET (reg_reloaded_dead
, reg_reloaded_died
);
7262 /* Emit code to perform a reload from IN (which may be a reload register) to
7263 OUT (which may also be a reload register). IN or OUT is from operand
7264 OPNUM with reload type TYPE.
7266 Returns first insn emitted. */
7269 gen_reload (rtx out
, rtx in
, int opnum
, enum reload_type type
)
7271 rtx last
= get_last_insn ();
7274 /* If IN is a paradoxical SUBREG, remove it and try to put the
7275 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
7276 if (GET_CODE (in
) == SUBREG
7277 && (GET_MODE_SIZE (GET_MODE (in
))
7278 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in
))))
7279 && (tem
= gen_lowpart_common (GET_MODE (SUBREG_REG (in
)), out
)) != 0)
7280 in
= SUBREG_REG (in
), out
= tem
;
7281 else if (GET_CODE (out
) == SUBREG
7282 && (GET_MODE_SIZE (GET_MODE (out
))
7283 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out
))))
7284 && (tem
= gen_lowpart_common (GET_MODE (SUBREG_REG (out
)), in
)) != 0)
7285 out
= SUBREG_REG (out
), in
= tem
;
7287 /* How to do this reload can get quite tricky. Normally, we are being
7288 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
7289 register that didn't get a hard register. In that case we can just
7290 call emit_move_insn.
7292 We can also be asked to reload a PLUS that adds a register or a MEM to
7293 another register, constant or MEM. This can occur during frame pointer
7294 elimination and while reloading addresses. This case is handled by
7295 trying to emit a single insn to perform the add. If it is not valid,
7296 we use a two insn sequence.
7298 Finally, we could be called to handle an 'o' constraint by putting
7299 an address into a register. In that case, we first try to do this
7300 with a named pattern of "reload_load_address". If no such pattern
7301 exists, we just emit a SET insn and hope for the best (it will normally
7302 be valid on machines that use 'o').
7304 This entire process is made complex because reload will never
7305 process the insns we generate here and so we must ensure that
7306 they will fit their constraints and also by the fact that parts of
7307 IN might be being reloaded separately and replaced with spill registers.
7308 Because of this, we are, in some sense, just guessing the right approach
7309 here. The one listed above seems to work.
7311 ??? At some point, this whole thing needs to be rethought. */
7313 if (GET_CODE (in
) == PLUS
7314 && (GET_CODE (XEXP (in
, 0)) == REG
7315 || GET_CODE (XEXP (in
, 0)) == SUBREG
7316 || GET_CODE (XEXP (in
, 0)) == MEM
)
7317 && (GET_CODE (XEXP (in
, 1)) == REG
7318 || GET_CODE (XEXP (in
, 1)) == SUBREG
7319 || CONSTANT_P (XEXP (in
, 1))
7320 || GET_CODE (XEXP (in
, 1)) == MEM
))
7322 /* We need to compute the sum of a register or a MEM and another
7323 register, constant, or MEM, and put it into the reload
7324 register. The best possible way of doing this is if the machine
7325 has a three-operand ADD insn that accepts the required operands.
7327 The simplest approach is to try to generate such an insn and see if it
7328 is recognized and matches its constraints. If so, it can be used.
7330 It might be better not to actually emit the insn unless it is valid,
7331 but we need to pass the insn as an operand to `recog' and
7332 `extract_insn' and it is simpler to emit and then delete the insn if
7333 not valid than to dummy things up. */
7335 rtx op0
, op1
, tem
, insn
;
7338 op0
= find_replacement (&XEXP (in
, 0));
7339 op1
= find_replacement (&XEXP (in
, 1));
7341 /* Since constraint checking is strict, commutativity won't be
7342 checked, so we need to do that here to avoid spurious failure
7343 if the add instruction is two-address and the second operand
7344 of the add is the same as the reload reg, which is frequently
7345 the case. If the insn would be A = B + A, rearrange it so
7346 it will be A = A + B as constrain_operands expects. */
7348 if (GET_CODE (XEXP (in
, 1)) == REG
7349 && REGNO (out
) == REGNO (XEXP (in
, 1)))
7350 tem
= op0
, op0
= op1
, op1
= tem
;
7352 if (op0
!= XEXP (in
, 0) || op1
!= XEXP (in
, 1))
7353 in
= gen_rtx_PLUS (GET_MODE (in
), op0
, op1
);
7355 insn
= emit_insn (gen_rtx_SET (VOIDmode
, out
, in
));
7356 code
= recog_memoized (insn
);
7360 extract_insn (insn
);
7361 /* We want constrain operands to treat this insn strictly in
7362 its validity determination, i.e., the way it would after reload
7364 if (constrain_operands (1))
7368 delete_insns_since (last
);
7370 /* If that failed, we must use a conservative two-insn sequence.
7372 Use a move to copy one operand into the reload register. Prefer
7373 to reload a constant, MEM or pseudo since the move patterns can
7374 handle an arbitrary operand. If OP1 is not a constant, MEM or
7375 pseudo and OP1 is not a valid operand for an add instruction, then
7378 After reloading one of the operands into the reload register, add
7379 the reload register to the output register.
7381 If there is another way to do this for a specific machine, a
7382 DEFINE_PEEPHOLE should be specified that recognizes the sequence
7385 code
= (int) add_optab
->handlers
[(int) GET_MODE (out
)].insn_code
;
7387 if (CONSTANT_P (op1
) || GET_CODE (op1
) == MEM
|| GET_CODE (op1
) == SUBREG
7388 || (GET_CODE (op1
) == REG
7389 && REGNO (op1
) >= FIRST_PSEUDO_REGISTER
)
7390 || (code
!= CODE_FOR_nothing
7391 && ! ((*insn_data
[code
].operand
[2].predicate
)
7392 (op1
, insn_data
[code
].operand
[2].mode
))))
7393 tem
= op0
, op0
= op1
, op1
= tem
;
7395 gen_reload (out
, op0
, opnum
, type
);
7397 /* If OP0 and OP1 are the same, we can use OUT for OP1.
7398 This fixes a problem on the 32K where the stack pointer cannot
7399 be used as an operand of an add insn. */
7401 if (rtx_equal_p (op0
, op1
))
7404 insn
= emit_insn (gen_add2_insn (out
, op1
));
7406 /* If that failed, copy the address register to the reload register.
7407 Then add the constant to the reload register. */
7409 code
= recog_memoized (insn
);
7413 extract_insn (insn
);
7414 /* We want constrain operands to treat this insn strictly in
7415 its validity determination, i.e., the way it would after reload
7417 if (constrain_operands (1))
7419 /* Add a REG_EQUIV note so that find_equiv_reg can find it. */
7421 = gen_rtx_EXPR_LIST (REG_EQUIV
, in
, REG_NOTES (insn
));
7426 delete_insns_since (last
);
7428 gen_reload (out
, op1
, opnum
, type
);
7429 insn
= emit_insn (gen_add2_insn (out
, op0
));
7430 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_EQUIV
, in
, REG_NOTES (insn
));
7433 #ifdef SECONDARY_MEMORY_NEEDED
7434 /* If we need a memory location to do the move, do it that way. */
7435 else if ((GET_CODE (in
) == REG
|| GET_CODE (in
) == SUBREG
)
7436 && reg_or_subregno (in
) < FIRST_PSEUDO_REGISTER
7437 && (GET_CODE (out
) == REG
|| GET_CODE (out
) == SUBREG
)
7438 && reg_or_subregno (out
) < FIRST_PSEUDO_REGISTER
7439 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (reg_or_subregno (in
)),
7440 REGNO_REG_CLASS (reg_or_subregno (out
)),
7443 /* Get the memory to use and rewrite both registers to its mode. */
7444 rtx loc
= get_secondary_mem (in
, GET_MODE (out
), opnum
, type
);
7446 if (GET_MODE (loc
) != GET_MODE (out
))
7447 out
= gen_rtx_REG (GET_MODE (loc
), REGNO (out
));
7449 if (GET_MODE (loc
) != GET_MODE (in
))
7450 in
= gen_rtx_REG (GET_MODE (loc
), REGNO (in
));
7452 gen_reload (loc
, in
, opnum
, type
);
7453 gen_reload (out
, loc
, opnum
, type
);
7457 /* If IN is a simple operand, use gen_move_insn. */
7458 else if (GET_RTX_CLASS (GET_CODE (in
)) == 'o' || GET_CODE (in
) == SUBREG
)
7459 emit_insn (gen_move_insn (out
, in
));
7461 #ifdef HAVE_reload_load_address
7462 else if (HAVE_reload_load_address
)
7463 emit_insn (gen_reload_load_address (out
, in
));
7466 /* Otherwise, just write (set OUT IN) and hope for the best. */
7468 emit_insn (gen_rtx_SET (VOIDmode
, out
, in
));
7470 /* Return the first insn emitted.
7471 We can not just return get_last_insn, because there may have
7472 been multiple instructions emitted. Also note that gen_move_insn may
7473 emit more than one insn itself, so we can not assume that there is one
7474 insn emitted per emit_insn_before call. */
7476 return last
? NEXT_INSN (last
) : get_insns ();
7479 /* Delete a previously made output-reload whose result we now believe
7480 is not needed. First we double-check.
7482 INSN is the insn now being processed.
7483 LAST_RELOAD_REG is the hard register number for which we want to delete
7484 the last output reload.
7485 J is the reload-number that originally used REG. The caller has made
7486 certain that reload J doesn't use REG any longer for input. */
7489 delete_output_reload (rtx insn
, int j
, int last_reload_reg
)
7491 rtx output_reload_insn
= spill_reg_store
[last_reload_reg
];
7492 rtx reg
= spill_reg_stored_to
[last_reload_reg
];
7495 int n_inherited
= 0;
7499 /* It is possible that this reload has been only used to set another reload
7500 we eliminated earlier and thus deleted this instruction too. */
7501 if (INSN_DELETED_P (output_reload_insn
))
7504 /* Get the raw pseudo-register referred to. */
7506 while (GET_CODE (reg
) == SUBREG
)
7507 reg
= SUBREG_REG (reg
);
7508 substed
= reg_equiv_memory_loc
[REGNO (reg
)];
7510 /* This is unsafe if the operand occurs more often in the current
7511 insn than it is inherited. */
7512 for (k
= n_reloads
- 1; k
>= 0; k
--)
7514 rtx reg2
= rld
[k
].in
;
7517 if (GET_CODE (reg2
) == MEM
|| reload_override_in
[k
])
7518 reg2
= rld
[k
].in_reg
;
7520 if (rld
[k
].out
&& ! rld
[k
].out_reg
)
7521 reg2
= XEXP (rld
[k
].in_reg
, 0);
7523 while (GET_CODE (reg2
) == SUBREG
)
7524 reg2
= SUBREG_REG (reg2
);
7525 if (rtx_equal_p (reg2
, reg
))
7527 if (reload_inherited
[k
] || reload_override_in
[k
] || k
== j
)
7530 reg2
= rld
[k
].out_reg
;
7533 while (GET_CODE (reg2
) == SUBREG
)
7534 reg2
= XEXP (reg2
, 0);
7535 if (rtx_equal_p (reg2
, reg
))
7542 n_occurrences
= count_occurrences (PATTERN (insn
), reg
, 0);
7544 n_occurrences
+= count_occurrences (PATTERN (insn
),
7545 eliminate_regs (substed
, 0,
7547 if (n_occurrences
> n_inherited
)
7550 /* If the pseudo-reg we are reloading is no longer referenced
7551 anywhere between the store into it and here,
7552 and no jumps or labels intervene, then the value can get
7553 here through the reload reg alone.
7554 Otherwise, give up--return. */
7555 for (i1
= NEXT_INSN (output_reload_insn
);
7556 i1
!= insn
; i1
= NEXT_INSN (i1
))
7558 if (GET_CODE (i1
) == CODE_LABEL
|| GET_CODE (i1
) == JUMP_INSN
)
7560 if ((GET_CODE (i1
) == INSN
|| GET_CODE (i1
) == CALL_INSN
)
7561 && reg_mentioned_p (reg
, PATTERN (i1
)))
7563 /* If this is USE in front of INSN, we only have to check that
7564 there are no more references than accounted for by inheritance. */
7565 while (GET_CODE (i1
) == INSN
&& GET_CODE (PATTERN (i1
)) == USE
)
7567 n_occurrences
+= rtx_equal_p (reg
, XEXP (PATTERN (i1
), 0)) != 0;
7568 i1
= NEXT_INSN (i1
);
7570 if (n_occurrences
<= n_inherited
&& i1
== insn
)
7576 /* We will be deleting the insn. Remove the spill reg information. */
7577 for (k
= HARD_REGNO_NREGS (last_reload_reg
, GET_MODE (reg
)); k
-- > 0; )
7579 spill_reg_store
[last_reload_reg
+ k
] = 0;
7580 spill_reg_stored_to
[last_reload_reg
+ k
] = 0;
7583 /* The caller has already checked that REG dies or is set in INSN.
7584 It has also checked that we are optimizing, and thus some
7585 inaccuracies in the debugging information are acceptable.
7586 So we could just delete output_reload_insn. But in some cases
7587 we can improve the debugging information without sacrificing
7588 optimization - maybe even improving the code: See if the pseudo
7589 reg has been completely replaced with reload regs. If so, delete
7590 the store insn and forget we had a stack slot for the pseudo. */
7591 if (rld
[j
].out
!= rld
[j
].in
7592 && REG_N_DEATHS (REGNO (reg
)) == 1
7593 && REG_N_SETS (REGNO (reg
)) == 1
7594 && REG_BASIC_BLOCK (REGNO (reg
)) >= 0
7595 && find_regno_note (insn
, REG_DEAD
, REGNO (reg
)))
7599 /* We know that it was used only between here and the beginning of
7600 the current basic block. (We also know that the last use before
7601 INSN was the output reload we are thinking of deleting, but never
7602 mind that.) Search that range; see if any ref remains. */
7603 for (i2
= PREV_INSN (insn
); i2
; i2
= PREV_INSN (i2
))
7605 rtx set
= single_set (i2
);
7607 /* Uses which just store in the pseudo don't count,
7608 since if they are the only uses, they are dead. */
7609 if (set
!= 0 && SET_DEST (set
) == reg
)
7611 if (GET_CODE (i2
) == CODE_LABEL
7612 || GET_CODE (i2
) == JUMP_INSN
)
7614 if ((GET_CODE (i2
) == INSN
|| GET_CODE (i2
) == CALL_INSN
)
7615 && reg_mentioned_p (reg
, PATTERN (i2
)))
7617 /* Some other ref remains; just delete the output reload we
7619 delete_address_reloads (output_reload_insn
, insn
);
7620 delete_insn (output_reload_insn
);
7625 /* Delete the now-dead stores into this pseudo. Note that this
7626 loop also takes care of deleting output_reload_insn. */
7627 for (i2
= PREV_INSN (insn
); i2
; i2
= PREV_INSN (i2
))
7629 rtx set
= single_set (i2
);
7631 if (set
!= 0 && SET_DEST (set
) == reg
)
7633 delete_address_reloads (i2
, insn
);
7636 if (GET_CODE (i2
) == CODE_LABEL
7637 || GET_CODE (i2
) == JUMP_INSN
)
7641 /* For the debugging info, say the pseudo lives in this reload reg. */
7642 reg_renumber
[REGNO (reg
)] = REGNO (rld
[j
].reg_rtx
);
7643 alter_reg (REGNO (reg
), -1);
7647 delete_address_reloads (output_reload_insn
, insn
);
7648 delete_insn (output_reload_insn
);
7652 /* We are going to delete DEAD_INSN. Recursively delete loads of
7653 reload registers used in DEAD_INSN that are not used till CURRENT_INSN.
7654 CURRENT_INSN is being reloaded, so we have to check its reloads too. */
7656 delete_address_reloads (rtx dead_insn
, rtx current_insn
)
7658 rtx set
= single_set (dead_insn
);
7659 rtx set2
, dst
, prev
, next
;
7662 rtx dst
= SET_DEST (set
);
7663 if (GET_CODE (dst
) == MEM
)
7664 delete_address_reloads_1 (dead_insn
, XEXP (dst
, 0), current_insn
);
7666 /* If we deleted the store from a reloaded post_{in,de}c expression,
7667 we can delete the matching adds. */
7668 prev
= PREV_INSN (dead_insn
);
7669 next
= NEXT_INSN (dead_insn
);
7670 if (! prev
|| ! next
)
7672 set
= single_set (next
);
7673 set2
= single_set (prev
);
7675 || GET_CODE (SET_SRC (set
)) != PLUS
|| GET_CODE (SET_SRC (set2
)) != PLUS
7676 || GET_CODE (XEXP (SET_SRC (set
), 1)) != CONST_INT
7677 || GET_CODE (XEXP (SET_SRC (set2
), 1)) != CONST_INT
)
7679 dst
= SET_DEST (set
);
7680 if (! rtx_equal_p (dst
, SET_DEST (set2
))
7681 || ! rtx_equal_p (dst
, XEXP (SET_SRC (set
), 0))
7682 || ! rtx_equal_p (dst
, XEXP (SET_SRC (set2
), 0))
7683 || (INTVAL (XEXP (SET_SRC (set
), 1))
7684 != -INTVAL (XEXP (SET_SRC (set2
), 1))))
7686 delete_related_insns (prev
);
7687 delete_related_insns (next
);
7690 /* Subfunction of delete_address_reloads: process registers found in X. */
7692 delete_address_reloads_1 (rtx dead_insn
, rtx x
, rtx current_insn
)
7694 rtx prev
, set
, dst
, i2
;
7696 enum rtx_code code
= GET_CODE (x
);
7700 const char *fmt
= GET_RTX_FORMAT (code
);
7701 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
7704 delete_address_reloads_1 (dead_insn
, XEXP (x
, i
), current_insn
);
7705 else if (fmt
[i
] == 'E')
7707 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
7708 delete_address_reloads_1 (dead_insn
, XVECEXP (x
, i
, j
),
7715 if (spill_reg_order
[REGNO (x
)] < 0)
7718 /* Scan backwards for the insn that sets x. This might be a way back due
7720 for (prev
= PREV_INSN (dead_insn
); prev
; prev
= PREV_INSN (prev
))
7722 code
= GET_CODE (prev
);
7723 if (code
== CODE_LABEL
|| code
== JUMP_INSN
)
7725 if (GET_RTX_CLASS (code
) != 'i')
7727 if (reg_set_p (x
, PATTERN (prev
)))
7729 if (reg_referenced_p (x
, PATTERN (prev
)))
7732 if (! prev
|| INSN_UID (prev
) < reload_first_uid
)
7734 /* Check that PREV only sets the reload register. */
7735 set
= single_set (prev
);
7738 dst
= SET_DEST (set
);
7739 if (GET_CODE (dst
) != REG
7740 || ! rtx_equal_p (dst
, x
))
7742 if (! reg_set_p (dst
, PATTERN (dead_insn
)))
7744 /* Check if DST was used in a later insn -
7745 it might have been inherited. */
7746 for (i2
= NEXT_INSN (dead_insn
); i2
; i2
= NEXT_INSN (i2
))
7748 if (GET_CODE (i2
) == CODE_LABEL
)
7752 if (reg_referenced_p (dst
, PATTERN (i2
)))
7754 /* If there is a reference to the register in the current insn,
7755 it might be loaded in a non-inherited reload. If no other
7756 reload uses it, that means the register is set before
7758 if (i2
== current_insn
)
7760 for (j
= n_reloads
- 1; j
>= 0; j
--)
7761 if ((rld
[j
].reg_rtx
== dst
&& reload_inherited
[j
])
7762 || reload_override_in
[j
] == dst
)
7764 for (j
= n_reloads
- 1; j
>= 0; j
--)
7765 if (rld
[j
].in
&& rld
[j
].reg_rtx
== dst
)
7772 if (GET_CODE (i2
) == JUMP_INSN
)
7774 /* If DST is still live at CURRENT_INSN, check if it is used for
7775 any reload. Note that even if CURRENT_INSN sets DST, we still
7776 have to check the reloads. */
7777 if (i2
== current_insn
)
7779 for (j
= n_reloads
- 1; j
>= 0; j
--)
7780 if ((rld
[j
].reg_rtx
== dst
&& reload_inherited
[j
])
7781 || reload_override_in
[j
] == dst
)
7783 /* ??? We can't finish the loop here, because dst might be
7784 allocated to a pseudo in this block if no reload in this
7785 block needs any of the classes containing DST - see
7786 spill_hard_reg. There is no easy way to tell this, so we
7787 have to scan till the end of the basic block. */
7789 if (reg_set_p (dst
, PATTERN (i2
)))
7793 delete_address_reloads_1 (prev
, SET_SRC (set
), current_insn
);
7794 reg_reloaded_contents
[REGNO (dst
)] = -1;
7798 /* Output reload-insns to reload VALUE into RELOADREG.
7799 VALUE is an autoincrement or autodecrement RTX whose operand
7800 is a register or memory location;
7801 so reloading involves incrementing that location.
7802 IN is either identical to VALUE, or some cheaper place to reload from.
7804 INC_AMOUNT is the number to increment or decrement by (always positive).
7805 This cannot be deduced from VALUE.
7807 Return the instruction that stores into RELOADREG. */
7810 inc_for_reload (rtx reloadreg
, rtx in
, rtx value
, int inc_amount
)
7812 /* REG or MEM to be copied and incremented. */
7813 rtx incloc
= XEXP (value
, 0);
7814 /* Nonzero if increment after copying. */
7815 int post
= (GET_CODE (value
) == POST_DEC
|| GET_CODE (value
) == POST_INC
);
7821 rtx real_in
= in
== value
? XEXP (in
, 0) : in
;
7823 /* No hard register is equivalent to this register after
7824 inc/dec operation. If REG_LAST_RELOAD_REG were nonzero,
7825 we could inc/dec that register as well (maybe even using it for
7826 the source), but I'm not sure it's worth worrying about. */
7827 if (GET_CODE (incloc
) == REG
)
7828 reg_last_reload_reg
[REGNO (incloc
)] = 0;
7830 if (GET_CODE (value
) == PRE_DEC
|| GET_CODE (value
) == POST_DEC
)
7831 inc_amount
= -inc_amount
;
7833 inc
= GEN_INT (inc_amount
);
7835 /* If this is post-increment, first copy the location to the reload reg. */
7836 if (post
&& real_in
!= reloadreg
)
7837 emit_insn (gen_move_insn (reloadreg
, real_in
));
7841 /* See if we can directly increment INCLOC. Use a method similar to
7842 that in gen_reload. */
7844 last
= get_last_insn ();
7845 add_insn
= emit_insn (gen_rtx_SET (VOIDmode
, incloc
,
7846 gen_rtx_PLUS (GET_MODE (incloc
),
7849 code
= recog_memoized (add_insn
);
7852 extract_insn (add_insn
);
7853 if (constrain_operands (1))
7855 /* If this is a pre-increment and we have incremented the value
7856 where it lives, copy the incremented value to RELOADREG to
7857 be used as an address. */
7860 emit_insn (gen_move_insn (reloadreg
, incloc
));
7865 delete_insns_since (last
);
7868 /* If couldn't do the increment directly, must increment in RELOADREG.
7869 The way we do this depends on whether this is pre- or post-increment.
7870 For pre-increment, copy INCLOC to the reload register, increment it
7871 there, then save back. */
7875 if (in
!= reloadreg
)
7876 emit_insn (gen_move_insn (reloadreg
, real_in
));
7877 emit_insn (gen_add2_insn (reloadreg
, inc
));
7878 store
= emit_insn (gen_move_insn (incloc
, reloadreg
));
7883 Because this might be a jump insn or a compare, and because RELOADREG
7884 may not be available after the insn in an input reload, we must do
7885 the incrementation before the insn being reloaded for.
7887 We have already copied IN to RELOADREG. Increment the copy in
7888 RELOADREG, save that back, then decrement RELOADREG so it has
7889 the original value. */
7891 emit_insn (gen_add2_insn (reloadreg
, inc
));
7892 store
= emit_insn (gen_move_insn (incloc
, reloadreg
));
7893 emit_insn (gen_add2_insn (reloadreg
, GEN_INT (-inc_amount
)));
7901 add_auto_inc_notes (rtx insn
, rtx x
)
7903 enum rtx_code code
= GET_CODE (x
);
7907 if (code
== MEM
&& auto_inc_p (XEXP (x
, 0)))
7910 = gen_rtx_EXPR_LIST (REG_INC
, XEXP (XEXP (x
, 0), 0), REG_NOTES (insn
));
7914 /* Scan all the operand sub-expressions. */
7915 fmt
= GET_RTX_FORMAT (code
);
7916 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
7919 add_auto_inc_notes (insn
, XEXP (x
, i
));
7920 else if (fmt
[i
] == 'E')
7921 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
7922 add_auto_inc_notes (insn
, XVECEXP (x
, i
, j
));
7927 /* Copy EH notes from an insn to its reloads. */
7929 copy_eh_notes (rtx insn
, rtx x
)
7931 rtx eh_note
= find_reg_note (insn
, REG_EH_REGION
, NULL_RTX
);
7934 for (; x
!= 0; x
= NEXT_INSN (x
))
7936 if (may_trap_p (PATTERN (x
)))
7938 = gen_rtx_EXPR_LIST (REG_EH_REGION
, XEXP (eh_note
, 0),
7944 /* This is used by reload pass, that does emit some instructions after
7945 abnormal calls moving basic block end, but in fact it wants to emit
7946 them on the edge. Looks for abnormal call edges, find backward the
7947 proper call and fix the damage.
7949 Similar handle instructions throwing exceptions internally. */
7951 fixup_abnormal_edges (void)
7953 bool inserted
= false;
7960 /* Look for cases we are interested in - calls or instructions causing
7962 for (e
= bb
->succ
; e
; e
= e
->succ_next
)
7964 if (e
->flags
& EDGE_ABNORMAL_CALL
)
7966 if ((e
->flags
& (EDGE_ABNORMAL
| EDGE_EH
))
7967 == (EDGE_ABNORMAL
| EDGE_EH
))
7970 if (e
&& GET_CODE (bb
->end
) != CALL_INSN
&& !can_throw_internal (bb
->end
))
7972 rtx insn
= bb
->end
, stop
= NEXT_INSN (bb
->end
);
7974 for (e
= bb
->succ
; e
; e
= e
->succ_next
)
7975 if (e
->flags
& EDGE_FALLTHRU
)
7977 /* Get past the new insns generated. Allow notes, as the insns may
7978 be already deleted. */
7979 while ((GET_CODE (insn
) == INSN
|| GET_CODE (insn
) == NOTE
)
7980 && !can_throw_internal (insn
)
7981 && insn
!= bb
->head
)
7982 insn
= PREV_INSN (insn
);
7983 if (GET_CODE (insn
) != CALL_INSN
&& !can_throw_internal (insn
))
7987 insn
= NEXT_INSN (insn
);
7988 while (insn
&& insn
!= stop
)
7990 next
= NEXT_INSN (insn
);
7995 /* Sometimes there's still the return value USE.
7996 If it's placed after a trapping call (i.e. that
7997 call is the last insn anyway), we have no fallthru
7998 edge. Simply delete this use and don't try to insert
7999 on the non-existent edge. */
8000 if (GET_CODE (PATTERN (insn
)) != USE
)
8002 /* We're not deleting it, we're moving it. */
8003 INSN_DELETED_P (insn
) = 0;
8004 PREV_INSN (insn
) = NULL_RTX
;
8005 NEXT_INSN (insn
) = NULL_RTX
;
8007 insert_insn_on_edge (insn
, e
);
8014 /* We've possibly turned single trapping insn into multiple ones. */
8015 if (flag_non_call_exceptions
)
8018 blocks
= sbitmap_alloc (last_basic_block
);
8019 sbitmap_ones (blocks
);
8020 find_many_sub_basic_blocks (blocks
);
8023 commit_edge_insertions ();