1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987-2014 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify it under
7 the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 3, or (at your option) any later
11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
22 #include "coretypes.h"
26 #include "hard-reg-set.h"
27 #include "rtl-error.h"
30 #include "insn-config.h"
41 #include "addresses.h"
42 #include "basic-block.h"
54 /* This file contains the reload pass of the compiler, which is
55 run after register allocation has been done. It checks that
56 each insn is valid (operands required to be in registers really
57 are in registers of the proper class) and fixes up invalid ones
58 by copying values temporarily into registers for the insns
61 The results of register allocation are described by the vector
62 reg_renumber; the insns still contain pseudo regs, but reg_renumber
63 can be used to find which hard reg, if any, a pseudo reg is in.
65 The technique we always use is to free up a few hard regs that are
66 called ``reload regs'', and for each place where a pseudo reg
67 must be in a hard reg, copy it temporarily into one of the reload regs.
69 Reload regs are allocated locally for every instruction that needs
70 reloads. When there are pseudos which are allocated to a register that
71 has been chosen as a reload reg, such pseudos must be ``spilled''.
72 This means that they go to other hard regs, or to stack slots if no other
73 available hard regs can be found. Spilling can invalidate more
74 insns, requiring additional need for reloads, so we must keep checking
75 until the process stabilizes.
77 For machines with different classes of registers, we must keep track
78 of the register class needed for each reload, and make sure that
79 we allocate enough reload registers of each class.
81 The file reload.c contains the code that checks one insn for
82 validity and reports the reloads that it needs. This file
83 is in charge of scanning the entire rtl code, accumulating the
84 reload needs, spilling, assigning reload registers to use for
85 fixing up each insn, and generating the new insns to copy values
86 into the reload registers. */
88 struct target_reload default_target_reload
;
90 struct target_reload
*this_target_reload
= &default_target_reload
;
93 #define spill_indirect_levels \
94 (this_target_reload->x_spill_indirect_levels)
96 /* During reload_as_needed, element N contains a REG rtx for the hard reg
97 into which reg N has been reloaded (perhaps for a previous insn). */
98 static rtx
*reg_last_reload_reg
;
100 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
101 for an output reload that stores into reg N. */
102 static regset_head reg_has_output_reload
;
104 /* Indicates which hard regs are reload-registers for an output reload
105 in the current insn. */
106 static HARD_REG_SET reg_is_output_reload
;
108 /* Widest width in which each pseudo reg is referred to (via subreg). */
109 static unsigned int *reg_max_ref_width
;
111 /* Vector to remember old contents of reg_renumber before spilling. */
112 static short *reg_old_renumber
;
114 /* During reload_as_needed, element N contains the last pseudo regno reloaded
115 into hard register N. If that pseudo reg occupied more than one register,
116 reg_reloaded_contents points to that pseudo for each spill register in
117 use; all of these must remain set for an inheritance to occur. */
118 static int reg_reloaded_contents
[FIRST_PSEUDO_REGISTER
];
120 /* During reload_as_needed, element N contains the insn for which
121 hard register N was last used. Its contents are significant only
122 when reg_reloaded_valid is set for this register. */
123 static rtx_insn
*reg_reloaded_insn
[FIRST_PSEUDO_REGISTER
];
125 /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid. */
126 static HARD_REG_SET reg_reloaded_valid
;
127 /* Indicate if the register was dead at the end of the reload.
128 This is only valid if reg_reloaded_contents is set and valid. */
129 static HARD_REG_SET reg_reloaded_dead
;
131 /* Indicate whether the register's current value is one that is not
132 safe to retain across a call, even for registers that are normally
133 call-saved. This is only meaningful for members of reg_reloaded_valid. */
134 static HARD_REG_SET reg_reloaded_call_part_clobbered
;
136 /* Number of spill-regs so far; number of valid elements of spill_regs. */
139 /* In parallel with spill_regs, contains REG rtx's for those regs.
140 Holds the last rtx used for any given reg, or 0 if it has never
141 been used for spilling yet. This rtx is reused, provided it has
143 static rtx spill_reg_rtx
[FIRST_PSEUDO_REGISTER
];
145 /* In parallel with spill_regs, contains nonzero for a spill reg
146 that was stored after the last time it was used.
147 The precise value is the insn generated to do the store. */
148 static rtx_insn
*spill_reg_store
[FIRST_PSEUDO_REGISTER
];
150 /* This is the register that was stored with spill_reg_store. This is a
151 copy of reload_out / reload_out_reg when the value was stored; if
152 reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */
153 static rtx spill_reg_stored_to
[FIRST_PSEUDO_REGISTER
];
155 /* This table is the inverse mapping of spill_regs:
156 indexed by hard reg number,
157 it contains the position of that reg in spill_regs,
158 or -1 for something that is not in spill_regs.
160 ?!? This is no longer accurate. */
161 static short spill_reg_order
[FIRST_PSEUDO_REGISTER
];
163 /* This reg set indicates registers that can't be used as spill registers for
164 the currently processed insn. These are the hard registers which are live
165 during the insn, but not allocated to pseudos, as well as fixed
167 static HARD_REG_SET bad_spill_regs
;
169 /* These are the hard registers that can't be used as spill register for any
170 insn. This includes registers used for user variables and registers that
171 we can't eliminate. A register that appears in this set also can't be used
172 to retry register allocation. */
173 static HARD_REG_SET bad_spill_regs_global
;
175 /* Describes order of use of registers for reloading
176 of spilled pseudo-registers. `n_spills' is the number of
177 elements that are actually valid; new ones are added at the end.
179 Both spill_regs and spill_reg_order are used on two occasions:
180 once during find_reload_regs, where they keep track of the spill registers
181 for a single insn, but also during reload_as_needed where they show all
182 the registers ever used by reload. For the latter case, the information
183 is calculated during finish_spills. */
184 static short spill_regs
[FIRST_PSEUDO_REGISTER
];
186 /* This vector of reg sets indicates, for each pseudo, which hard registers
187 may not be used for retrying global allocation because the register was
188 formerly spilled from one of them. If we allowed reallocating a pseudo to
189 a register that it was already allocated to, reload might not
191 static HARD_REG_SET
*pseudo_previous_regs
;
193 /* This vector of reg sets indicates, for each pseudo, which hard
194 registers may not be used for retrying global allocation because they
195 are used as spill registers during one of the insns in which the
197 static HARD_REG_SET
*pseudo_forbidden_regs
;
199 /* All hard regs that have been used as spill registers for any insn are
200 marked in this set. */
201 static HARD_REG_SET used_spill_regs
;
203 /* Index of last register assigned as a spill register. We allocate in
204 a round-robin fashion. */
205 static int last_spill_reg
;
207 /* Record the stack slot for each spilled hard register. */
208 static rtx spill_stack_slot
[FIRST_PSEUDO_REGISTER
];
210 /* Width allocated so far for that stack slot. */
211 static unsigned int spill_stack_slot_width
[FIRST_PSEUDO_REGISTER
];
213 /* Record which pseudos needed to be spilled. */
214 static regset_head spilled_pseudos
;
216 /* Record which pseudos changed their allocation in finish_spills. */
217 static regset_head changed_allocation_pseudos
;
219 /* Used for communication between order_regs_for_reload and count_pseudo.
220 Used to avoid counting one pseudo twice. */
221 static regset_head pseudos_counted
;
223 /* First uid used by insns created by reload in this function.
224 Used in find_equiv_reg. */
225 int reload_first_uid
;
227 /* Flag set by local-alloc or global-alloc if anything is live in
228 a call-clobbered reg across calls. */
229 int caller_save_needed
;
231 /* Set to 1 while reload_as_needed is operating.
232 Required by some machines to handle any generated moves differently. */
233 int reload_in_progress
= 0;
235 /* This obstack is used for allocation of rtl during register elimination.
236 The allocated storage can be freed once find_reloads has processed the
238 static struct obstack reload_obstack
;
240 /* Points to the beginning of the reload_obstack. All insn_chain structures
241 are allocated first. */
242 static char *reload_startobj
;
244 /* The point after all insn_chain structures. Used to quickly deallocate
245 memory allocated in copy_reloads during calculate_needs_all_insns. */
246 static char *reload_firstobj
;
248 /* This points before all local rtl generated by register elimination.
249 Used to quickly free all memory after processing one insn. */
250 static char *reload_insn_firstobj
;
252 /* List of insn_chain instructions, one for every insn that reload needs to
254 struct insn_chain
*reload_insn_chain
;
256 /* TRUE if we potentially left dead insns in the insn stream and want to
257 run DCE immediately after reload, FALSE otherwise. */
258 static bool need_dce
;
260 /* List of all insns needing reloads. */
261 static struct insn_chain
*insns_need_reload
;
263 /* This structure is used to record information about register eliminations.
264 Each array entry describes one possible way of eliminating a register
265 in favor of another. If there is more than one way of eliminating a
266 particular register, the most preferred should be specified first. */
270 int from
; /* Register number to be eliminated. */
271 int to
; /* Register number used as replacement. */
272 HOST_WIDE_INT initial_offset
; /* Initial difference between values. */
273 int can_eliminate
; /* Nonzero if this elimination can be done. */
274 int can_eliminate_previous
; /* Value returned by TARGET_CAN_ELIMINATE
275 target hook in previous scan over insns
277 HOST_WIDE_INT offset
; /* Current offset between the two regs. */
278 HOST_WIDE_INT previous_offset
;/* Offset at end of previous insn. */
279 int ref_outside_mem
; /* "to" has been referenced outside a MEM. */
280 rtx from_rtx
; /* REG rtx for the register to be eliminated.
281 We cannot simply compare the number since
282 we might then spuriously replace a hard
283 register corresponding to a pseudo
284 assigned to the reg to be eliminated. */
285 rtx to_rtx
; /* REG rtx for the replacement. */
288 static struct elim_table
*reg_eliminate
= 0;
290 /* This is an intermediate structure to initialize the table. It has
291 exactly the members provided by ELIMINABLE_REGS. */
292 static const struct elim_table_1
296 } reg_eliminate_1
[] =
298 /* If a set of eliminable registers was specified, define the table from it.
299 Otherwise, default to the normal case of the frame pointer being
300 replaced by the stack pointer. */
302 #ifdef ELIMINABLE_REGS
305 {{ FRAME_POINTER_REGNUM
, STACK_POINTER_REGNUM
}};
308 #define NUM_ELIMINABLE_REGS ARRAY_SIZE (reg_eliminate_1)
310 /* Record the number of pending eliminations that have an offset not equal
311 to their initial offset. If nonzero, we use a new copy of each
312 replacement result in any insns encountered. */
313 int num_not_at_initial_offset
;
315 /* Count the number of registers that we may be able to eliminate. */
316 static int num_eliminable
;
317 /* And the number of registers that are equivalent to a constant that
318 can be eliminated to frame_pointer / arg_pointer + constant. */
319 static int num_eliminable_invariants
;
321 /* For each label, we record the offset of each elimination. If we reach
322 a label by more than one path and an offset differs, we cannot do the
323 elimination. This information is indexed by the difference of the
324 number of the label and the first label number. We can't offset the
325 pointer itself as this can cause problems on machines with segmented
326 memory. The first table is an array of flags that records whether we
327 have yet encountered a label and the second table is an array of arrays,
328 one entry in the latter array for each elimination. */
330 static int first_label_num
;
331 static char *offsets_known_at
;
332 static HOST_WIDE_INT (*offsets_at
)[NUM_ELIMINABLE_REGS
];
334 vec
<reg_equivs_t
, va_gc
> *reg_equivs
;
336 /* Stack of addresses where an rtx has been changed. We can undo the
337 changes by popping items off the stack and restoring the original
338 value at each location.
340 We use this simplistic undo capability rather than copy_rtx as copy_rtx
341 will not make a deep copy of a normally sharable rtx, such as
342 (const (plus (symbol_ref) (const_int))). If such an expression appears
343 as R1 in gen_reload_chain_without_interm_reg_p, then a shared
344 rtx expression would be changed. See PR 42431. */
347 static vec
<rtx_p
> substitute_stack
;
349 /* Number of labels in the current function. */
351 static int num_labels
;
353 static void replace_pseudos_in (rtx
*, enum machine_mode
, rtx
);
354 static void maybe_fix_stack_asms (void);
355 static void copy_reloads (struct insn_chain
*);
356 static void calculate_needs_all_insns (int);
357 static int find_reg (struct insn_chain
*, int);
358 static void find_reload_regs (struct insn_chain
*);
359 static void select_reload_regs (void);
360 static void delete_caller_save_insns (void);
362 static void spill_failure (rtx_insn
*, enum reg_class
);
363 static void count_spilled_pseudo (int, int, int);
364 static void delete_dead_insn (rtx_insn
*);
365 static void alter_reg (int, int, bool);
366 static void set_label_offsets (rtx
, rtx_insn
*, int);
367 static void check_eliminable_occurrences (rtx
);
368 static void elimination_effects (rtx
, enum machine_mode
);
369 static rtx
eliminate_regs_1 (rtx
, enum machine_mode
, rtx
, bool, bool);
370 static int eliminate_regs_in_insn (rtx_insn
*, int);
371 static void update_eliminable_offsets (void);
372 static void mark_not_eliminable (rtx
, const_rtx
, void *);
373 static void set_initial_elim_offsets (void);
374 static bool verify_initial_elim_offsets (void);
375 static void set_initial_label_offsets (void);
376 static void set_offsets_for_label (rtx_insn
*);
377 static void init_eliminable_invariants (rtx_insn
*, bool);
378 static void init_elim_table (void);
379 static void free_reg_equiv (void);
380 static void update_eliminables (HARD_REG_SET
*);
381 static bool update_eliminables_and_spill (void);
382 static void elimination_costs_in_insn (rtx_insn
*);
383 static void spill_hard_reg (unsigned int, int);
384 static int finish_spills (int);
385 static void scan_paradoxical_subregs (rtx
);
386 static void count_pseudo (int);
387 static void order_regs_for_reload (struct insn_chain
*);
388 static void reload_as_needed (int);
389 static void forget_old_reloads_1 (rtx
, const_rtx
, void *);
390 static void forget_marked_reloads (regset
);
391 static int reload_reg_class_lower (const void *, const void *);
392 static void mark_reload_reg_in_use (unsigned int, int, enum reload_type
,
394 static void clear_reload_reg_in_use (unsigned int, int, enum reload_type
,
396 static int reload_reg_free_p (unsigned int, int, enum reload_type
);
397 static int reload_reg_free_for_value_p (int, int, int, enum reload_type
,
399 static int free_for_value_p (int, enum machine_mode
, int, enum reload_type
,
401 static int allocate_reload_reg (struct insn_chain
*, int, int);
402 static int conflicts_with_override (rtx
);
403 static void failed_reload (rtx_insn
*, int);
404 static int set_reload_reg (int, int);
405 static void choose_reload_regs_init (struct insn_chain
*, rtx
*);
406 static void choose_reload_regs (struct insn_chain
*);
407 static void emit_input_reload_insns (struct insn_chain
*, struct reload
*,
409 static void emit_output_reload_insns (struct insn_chain
*, struct reload
*,
411 static void do_input_reload (struct insn_chain
*, struct reload
*, int);
412 static void do_output_reload (struct insn_chain
*, struct reload
*, int);
413 static void emit_reload_insns (struct insn_chain
*);
414 static void delete_output_reload (rtx_insn
*, int, int, rtx
);
415 static void delete_address_reloads (rtx_insn
*, rtx_insn
*);
416 static void delete_address_reloads_1 (rtx_insn
*, rtx
, rtx_insn
*);
417 static void inc_for_reload (rtx
, rtx
, rtx
, int);
419 static void add_auto_inc_notes (rtx_insn
*, rtx
);
421 static void substitute (rtx
*, const_rtx
, rtx
);
422 static bool gen_reload_chain_without_interm_reg_p (int, int);
423 static int reloads_conflict (int, int);
424 static rtx_insn
*gen_reload (rtx
, rtx
, int, enum reload_type
);
425 static rtx_insn
*emit_insn_if_valid_for_reload (rtx
);
427 /* Initialize the reload pass. This is called at the beginning of compilation
428 and may be called again if the target is reinitialized. */
435 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
436 Set spill_indirect_levels to the number of levels such addressing is
437 permitted, zero if it is not permitted at all. */
440 = gen_rtx_MEM (Pmode
,
443 LAST_VIRTUAL_REGISTER
+ 1),
444 gen_int_mode (4, Pmode
)));
445 spill_indirect_levels
= 0;
447 while (memory_address_p (QImode
, tem
))
449 spill_indirect_levels
++;
450 tem
= gen_rtx_MEM (Pmode
, tem
);
453 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
455 tem
= gen_rtx_MEM (Pmode
, gen_rtx_SYMBOL_REF (Pmode
, "foo"));
456 indirect_symref_ok
= memory_address_p (QImode
, tem
);
458 /* See if reg+reg is a valid (and offsettable) address. */
460 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
462 tem
= gen_rtx_PLUS (Pmode
,
463 gen_rtx_REG (Pmode
, HARD_FRAME_POINTER_REGNUM
),
464 gen_rtx_REG (Pmode
, i
));
466 /* This way, we make sure that reg+reg is an offsettable address. */
467 tem
= plus_constant (Pmode
, tem
, 4);
469 if (memory_address_p (QImode
, tem
))
471 double_reg_address_ok
= 1;
476 /* Initialize obstack for our rtl allocation. */
477 if (reload_startobj
== NULL
)
479 gcc_obstack_init (&reload_obstack
);
480 reload_startobj
= XOBNEWVAR (&reload_obstack
, char, 0);
483 INIT_REG_SET (&spilled_pseudos
);
484 INIT_REG_SET (&changed_allocation_pseudos
);
485 INIT_REG_SET (&pseudos_counted
);
488 /* List of insn chains that are currently unused. */
489 static struct insn_chain
*unused_insn_chains
= 0;
491 /* Allocate an empty insn_chain structure. */
493 new_insn_chain (void)
495 struct insn_chain
*c
;
497 if (unused_insn_chains
== 0)
499 c
= XOBNEW (&reload_obstack
, struct insn_chain
);
500 INIT_REG_SET (&c
->live_throughout
);
501 INIT_REG_SET (&c
->dead_or_set
);
505 c
= unused_insn_chains
;
506 unused_insn_chains
= c
->next
;
508 c
->is_caller_save_insn
= 0;
509 c
->need_operand_change
= 0;
515 /* Small utility function to set all regs in hard reg set TO which are
516 allocated to pseudos in regset FROM. */
519 compute_use_by_pseudos (HARD_REG_SET
*to
, regset from
)
522 reg_set_iterator rsi
;
524 EXECUTE_IF_SET_IN_REG_SET (from
, FIRST_PSEUDO_REGISTER
, regno
, rsi
)
526 int r
= reg_renumber
[regno
];
530 /* reload_combine uses the information from DF_LIVE_IN,
531 which might still contain registers that have not
532 actually been allocated since they have an
534 gcc_assert (ira_conflicts_p
|| reload_completed
);
537 add_to_hard_reg_set (to
, PSEUDO_REGNO_MODE (regno
), r
);
541 /* Replace all pseudos found in LOC with their corresponding
545 replace_pseudos_in (rtx
*loc
, enum machine_mode mem_mode
, rtx usage
)
558 unsigned int regno
= REGNO (x
);
560 if (regno
< FIRST_PSEUDO_REGISTER
)
563 x
= eliminate_regs_1 (x
, mem_mode
, usage
, true, false);
567 replace_pseudos_in (loc
, mem_mode
, usage
);
571 if (reg_equiv_constant (regno
))
572 *loc
= reg_equiv_constant (regno
);
573 else if (reg_equiv_invariant (regno
))
574 *loc
= reg_equiv_invariant (regno
);
575 else if (reg_equiv_mem (regno
))
576 *loc
= reg_equiv_mem (regno
);
577 else if (reg_equiv_address (regno
))
578 *loc
= gen_rtx_MEM (GET_MODE (x
), reg_equiv_address (regno
));
581 gcc_assert (!REG_P (regno_reg_rtx
[regno
])
582 || REGNO (regno_reg_rtx
[regno
]) != regno
);
583 *loc
= regno_reg_rtx
[regno
];
588 else if (code
== MEM
)
590 replace_pseudos_in (& XEXP (x
, 0), GET_MODE (x
), usage
);
594 /* Process each of our operands recursively. */
595 fmt
= GET_RTX_FORMAT (code
);
596 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++, fmt
++)
598 replace_pseudos_in (&XEXP (x
, i
), mem_mode
, usage
);
599 else if (*fmt
== 'E')
600 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
601 replace_pseudos_in (& XVECEXP (x
, i
, j
), mem_mode
, usage
);
604 /* Determine if the current function has an exception receiver block
605 that reaches the exit block via non-exceptional edges */
608 has_nonexceptional_receiver (void)
612 basic_block
*tos
, *worklist
, bb
;
614 /* If we're not optimizing, then just err on the safe side. */
618 /* First determine which blocks can reach exit via normal paths. */
619 tos
= worklist
= XNEWVEC (basic_block
, n_basic_blocks_for_fn (cfun
) + 1);
621 FOR_EACH_BB_FN (bb
, cfun
)
622 bb
->flags
&= ~BB_REACHABLE
;
624 /* Place the exit block on our worklist. */
625 EXIT_BLOCK_PTR_FOR_FN (cfun
)->flags
|= BB_REACHABLE
;
626 *tos
++ = EXIT_BLOCK_PTR_FOR_FN (cfun
);
628 /* Iterate: find everything reachable from what we've already seen. */
629 while (tos
!= worklist
)
633 FOR_EACH_EDGE (e
, ei
, bb
->preds
)
634 if (!(e
->flags
& EDGE_ABNORMAL
))
636 basic_block src
= e
->src
;
638 if (!(src
->flags
& BB_REACHABLE
))
640 src
->flags
|= BB_REACHABLE
;
647 /* Now see if there's a reachable block with an exceptional incoming
649 FOR_EACH_BB_FN (bb
, cfun
)
650 if (bb
->flags
& BB_REACHABLE
&& bb_has_abnormal_pred (bb
))
653 /* No exceptional block reached exit unexceptionally. */
657 /* Grow (or allocate) the REG_EQUIVS array from its current size (which may be
658 zero elements) to MAX_REG_NUM elements.
660 Initialize all new fields to NULL and update REG_EQUIVS_SIZE. */
662 grow_reg_equivs (void)
664 int old_size
= vec_safe_length (reg_equivs
);
665 int max_regno
= max_reg_num ();
669 memset (&ze
, 0, sizeof (reg_equivs_t
));
670 vec_safe_reserve (reg_equivs
, max_regno
);
671 for (i
= old_size
; i
< max_regno
; i
++)
672 reg_equivs
->quick_insert (i
, ze
);
676 /* Global variables used by reload and its subroutines. */
678 /* The current basic block while in calculate_elim_costs_all_insns. */
679 static basic_block elim_bb
;
681 /* Set during calculate_needs if an insn needs register elimination. */
682 static int something_needs_elimination
;
683 /* Set during calculate_needs if an insn needs an operand changed. */
684 static int something_needs_operands_changed
;
685 /* Set by alter_regs if we spilled a register to the stack. */
686 static bool something_was_spilled
;
688 /* Nonzero means we couldn't get enough spill regs. */
691 /* Temporary array of pseudo-register number. */
692 static int *temp_pseudo_reg_arr
;
694 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
695 If that insn didn't set the register (i.e., it copied the register to
696 memory), just delete that insn instead of the equivalencing insn plus
697 anything now dead. If we call delete_dead_insn on that insn, we may
698 delete the insn that actually sets the register if the register dies
699 there and that is incorrect. */
703 for (int i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
705 if (reg_renumber
[i
] < 0 && reg_equiv_init (i
) != 0)
708 for (list
= reg_equiv_init (i
); list
; list
= XEXP (list
, 1))
710 rtx_insn
*equiv_insn
= as_a
<rtx_insn
*> (XEXP (list
, 0));
712 /* If we already deleted the insn or if it may trap, we can't
713 delete it. The latter case shouldn't happen, but can
714 if an insn has a variable address, gets a REG_EH_REGION
715 note added to it, and then gets converted into a load
716 from a constant address. */
717 if (NOTE_P (equiv_insn
)
718 || can_throw_internal (equiv_insn
))
720 else if (reg_set_p (regno_reg_rtx
[i
], PATTERN (equiv_insn
)))
721 delete_dead_insn (equiv_insn
);
723 SET_INSN_DELETED (equiv_insn
);
729 /* Return true if remove_init_insns will delete INSN. */
731 will_delete_init_insn_p (rtx_insn
*insn
)
733 rtx set
= single_set (insn
);
734 if (!set
|| !REG_P (SET_DEST (set
)))
736 unsigned regno
= REGNO (SET_DEST (set
));
738 if (can_throw_internal (insn
))
741 if (regno
< FIRST_PSEUDO_REGISTER
|| reg_renumber
[regno
] >= 0)
744 for (rtx list
= reg_equiv_init (regno
); list
; list
= XEXP (list
, 1))
746 rtx equiv_insn
= XEXP (list
, 0);
747 if (equiv_insn
== insn
)
753 /* Main entry point for the reload pass.
755 FIRST is the first insn of the function being compiled.
757 GLOBAL nonzero means we were called from global_alloc
758 and should attempt to reallocate any pseudoregs that we
759 displace from hard regs we will use for reloads.
760 If GLOBAL is zero, we do not have enough information to do that,
761 so any pseudo reg that is spilled must go to the stack.
763 Return value is TRUE if reload likely left dead insns in the
764 stream and a DCE pass should be run to elimiante them. Else the
765 return value is FALSE. */
768 reload (rtx_insn
*first
, int global
)
772 struct elim_table
*ep
;
776 /* Make sure even insns with volatile mem refs are recognizable. */
781 reload_firstobj
= XOBNEWVAR (&reload_obstack
, char, 0);
783 /* Make sure that the last insn in the chain
784 is not something that needs reloading. */
785 emit_note (NOTE_INSN_DELETED
);
787 /* Enable find_equiv_reg to distinguish insns made by reload. */
788 reload_first_uid
= get_max_uid ();
790 #ifdef SECONDARY_MEMORY_NEEDED
791 /* Initialize the secondary memory table. */
792 clear_secondary_mem ();
795 /* We don't have a stack slot for any spill reg yet. */
796 memset (spill_stack_slot
, 0, sizeof spill_stack_slot
);
797 memset (spill_stack_slot_width
, 0, sizeof spill_stack_slot_width
);
799 /* Initialize the save area information for caller-save, in case some
803 /* Compute which hard registers are now in use
804 as homes for pseudo registers.
805 This is done here rather than (eg) in global_alloc
806 because this point is reached even if not optimizing. */
807 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
810 /* A function that has a nonlocal label that can reach the exit
811 block via non-exceptional paths must save all call-saved
813 if (cfun
->has_nonlocal_label
814 && has_nonexceptional_receiver ())
815 crtl
->saves_all_registers
= 1;
817 if (crtl
->saves_all_registers
)
818 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
819 if (! call_used_regs
[i
] && ! fixed_regs
[i
] && ! LOCAL_REGNO (i
))
820 df_set_regs_ever_live (i
, true);
822 /* Find all the pseudo registers that didn't get hard regs
823 but do have known equivalent constants or memory slots.
824 These include parameters (known equivalent to parameter slots)
825 and cse'd or loop-moved constant memory addresses.
827 Record constant equivalents in reg_equiv_constant
828 so they will be substituted by find_reloads.
829 Record memory equivalents in reg_mem_equiv so they can
830 be substituted eventually by altering the REG-rtx's. */
833 reg_old_renumber
= XCNEWVEC (short, max_regno
);
834 memcpy (reg_old_renumber
, reg_renumber
, max_regno
* sizeof (short));
835 pseudo_forbidden_regs
= XNEWVEC (HARD_REG_SET
, max_regno
);
836 pseudo_previous_regs
= XCNEWVEC (HARD_REG_SET
, max_regno
);
838 CLEAR_HARD_REG_SET (bad_spill_regs_global
);
840 init_eliminable_invariants (first
, true);
843 /* Alter each pseudo-reg rtx to contain its hard reg number. Assign
844 stack slots to the pseudos that lack hard regs or equivalents.
845 Do not touch virtual registers. */
847 temp_pseudo_reg_arr
= XNEWVEC (int, max_regno
- LAST_VIRTUAL_REGISTER
- 1);
848 for (n
= 0, i
= LAST_VIRTUAL_REGISTER
+ 1; i
< max_regno
; i
++)
849 temp_pseudo_reg_arr
[n
++] = i
;
852 /* Ask IRA to order pseudo-registers for better stack slot
854 ira_sort_regnos_for_alter_reg (temp_pseudo_reg_arr
, n
, reg_max_ref_width
);
856 for (i
= 0; i
< n
; i
++)
857 alter_reg (temp_pseudo_reg_arr
[i
], -1, false);
859 /* If we have some registers we think can be eliminated, scan all insns to
860 see if there is an insn that sets one of these registers to something
861 other than itself plus a constant. If so, the register cannot be
862 eliminated. Doing this scan here eliminates an extra pass through the
863 main reload loop in the most common case where register elimination
865 for (insn
= first
; insn
&& num_eliminable
; insn
= NEXT_INSN (insn
))
867 note_stores (PATTERN (insn
), mark_not_eliminable
, NULL
);
869 maybe_fix_stack_asms ();
871 insns_need_reload
= 0;
872 something_needs_elimination
= 0;
874 /* Initialize to -1, which means take the first spill register. */
877 /* Spill any hard regs that we know we can't eliminate. */
878 CLEAR_HARD_REG_SET (used_spill_regs
);
879 /* There can be multiple ways to eliminate a register;
880 they should be listed adjacently.
881 Elimination for any register fails only if all possible ways fail. */
882 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; )
885 int can_eliminate
= 0;
888 can_eliminate
|= ep
->can_eliminate
;
891 while (ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
] && ep
->from
== from
);
893 spill_hard_reg (from
, 1);
896 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
897 if (frame_pointer_needed
)
898 spill_hard_reg (HARD_FRAME_POINTER_REGNUM
, 1);
900 finish_spills (global
);
902 /* From now on, we may need to generate moves differently. We may also
903 allow modifications of insns which cause them to not be recognized.
904 Any such modifications will be cleaned up during reload itself. */
905 reload_in_progress
= 1;
907 /* This loop scans the entire function each go-round
908 and repeats until one repetition spills no additional hard regs. */
911 int something_changed
;
913 HOST_WIDE_INT starting_frame_size
;
915 starting_frame_size
= get_frame_size ();
916 something_was_spilled
= false;
918 set_initial_elim_offsets ();
919 set_initial_label_offsets ();
921 /* For each pseudo register that has an equivalent location defined,
922 try to eliminate any eliminable registers (such as the frame pointer)
923 assuming initial offsets for the replacement register, which
926 If the resulting location is directly addressable, substitute
927 the MEM we just got directly for the old REG.
929 If it is not addressable but is a constant or the sum of a hard reg
930 and constant, it is probably not addressable because the constant is
931 out of range, in that case record the address; we will generate
932 hairy code to compute the address in a register each time it is
933 needed. Similarly if it is a hard register, but one that is not
934 valid as an address register.
936 If the location is not addressable, but does not have one of the
937 above forms, assign a stack slot. We have to do this to avoid the
938 potential of producing lots of reloads if, e.g., a location involves
939 a pseudo that didn't get a hard register and has an equivalent memory
940 location that also involves a pseudo that didn't get a hard register.
942 Perhaps at some point we will improve reload_when_needed handling
943 so this problem goes away. But that's very hairy. */
945 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
946 if (reg_renumber
[i
] < 0 && reg_equiv_memory_loc (i
))
948 rtx x
= eliminate_regs (reg_equiv_memory_loc (i
), VOIDmode
,
951 if (strict_memory_address_addr_space_p
952 (GET_MODE (regno_reg_rtx
[i
]), XEXP (x
, 0),
954 reg_equiv_mem (i
) = x
, reg_equiv_address (i
) = 0;
955 else if (CONSTANT_P (XEXP (x
, 0))
956 || (REG_P (XEXP (x
, 0))
957 && REGNO (XEXP (x
, 0)) < FIRST_PSEUDO_REGISTER
)
958 || (GET_CODE (XEXP (x
, 0)) == PLUS
959 && REG_P (XEXP (XEXP (x
, 0), 0))
960 && (REGNO (XEXP (XEXP (x
, 0), 0))
961 < FIRST_PSEUDO_REGISTER
)
962 && CONSTANT_P (XEXP (XEXP (x
, 0), 1))))
963 reg_equiv_address (i
) = XEXP (x
, 0), reg_equiv_mem (i
) = 0;
966 /* Make a new stack slot. Then indicate that something
967 changed so we go back and recompute offsets for
968 eliminable registers because the allocation of memory
969 below might change some offset. reg_equiv_{mem,address}
970 will be set up for this pseudo on the next pass around
972 reg_equiv_memory_loc (i
) = 0;
973 reg_equiv_init (i
) = 0;
974 alter_reg (i
, -1, true);
978 if (caller_save_needed
)
981 if (starting_frame_size
&& crtl
->stack_alignment_needed
)
983 /* If we have a stack frame, we must align it now. The
984 stack size may be a part of the offset computation for
985 register elimination. So if this changes the stack size,
986 then repeat the elimination bookkeeping. We don't
987 realign when there is no stack, as that will cause a
988 stack frame when none is needed should
989 STARTING_FRAME_OFFSET not be already aligned to
991 assign_stack_local (BLKmode
, 0, crtl
->stack_alignment_needed
);
993 /* If we allocated another stack slot, redo elimination bookkeeping. */
994 if (something_was_spilled
|| starting_frame_size
!= get_frame_size ())
996 update_eliminables_and_spill ();
1000 if (caller_save_needed
)
1002 save_call_clobbered_regs ();
1003 /* That might have allocated new insn_chain structures. */
1004 reload_firstobj
= XOBNEWVAR (&reload_obstack
, char, 0);
1007 calculate_needs_all_insns (global
);
1009 if (! ira_conflicts_p
)
1010 /* Don't do it for IRA. We need this info because we don't
1011 change live_throughout and dead_or_set for chains when IRA
1013 CLEAR_REG_SET (&spilled_pseudos
);
1017 something_changed
= 0;
1019 /* If we allocated any new memory locations, make another pass
1020 since it might have changed elimination offsets. */
1021 if (something_was_spilled
|| starting_frame_size
!= get_frame_size ())
1022 something_changed
= 1;
1024 /* Even if the frame size remained the same, we might still have
1025 changed elimination offsets, e.g. if find_reloads called
1026 force_const_mem requiring the back end to allocate a constant
1027 pool base register that needs to be saved on the stack. */
1028 else if (!verify_initial_elim_offsets ())
1029 something_changed
= 1;
1031 if (update_eliminables_and_spill ())
1034 something_changed
= 1;
1037 select_reload_regs ();
1041 if (insns_need_reload
!= 0 || did_spill
)
1042 something_changed
|= finish_spills (global
);
1044 if (! something_changed
)
1047 if (caller_save_needed
)
1048 delete_caller_save_insns ();
1050 obstack_free (&reload_obstack
, reload_firstobj
);
1053 /* If global-alloc was run, notify it of any register eliminations we have
1056 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
1057 if (ep
->can_eliminate
)
1058 mark_elimination (ep
->from
, ep
->to
);
1060 remove_init_insns ();
1062 /* Use the reload registers where necessary
1063 by generating move instructions to move the must-be-register
1064 values into or out of the reload registers. */
1066 if (insns_need_reload
!= 0 || something_needs_elimination
1067 || something_needs_operands_changed
)
1069 HOST_WIDE_INT old_frame_size
= get_frame_size ();
1071 reload_as_needed (global
);
1073 gcc_assert (old_frame_size
== get_frame_size ());
1075 gcc_assert (verify_initial_elim_offsets ());
1078 /* If we were able to eliminate the frame pointer, show that it is no
1079 longer live at the start of any basic block. If it ls live by
1080 virtue of being in a pseudo, that pseudo will be marked live
1081 and hence the frame pointer will be known to be live via that
1084 if (! frame_pointer_needed
)
1085 FOR_EACH_BB_FN (bb
, cfun
)
1086 bitmap_clear_bit (df_get_live_in (bb
), HARD_FRAME_POINTER_REGNUM
);
1088 /* Come here (with failure set nonzero) if we can't get enough spill
1092 CLEAR_REG_SET (&changed_allocation_pseudos
);
1093 CLEAR_REG_SET (&spilled_pseudos
);
1094 reload_in_progress
= 0;
1096 /* Now eliminate all pseudo regs by modifying them into
1097 their equivalent memory references.
1098 The REG-rtx's for the pseudos are modified in place,
1099 so all insns that used to refer to them now refer to memory.
1101 For a reg that has a reg_equiv_address, all those insns
1102 were changed by reloading so that no insns refer to it any longer;
1103 but the DECL_RTL of a variable decl may refer to it,
1104 and if so this causes the debugging info to mention the variable. */
1106 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
1110 if (reg_equiv_mem (i
))
1111 addr
= XEXP (reg_equiv_mem (i
), 0);
1113 if (reg_equiv_address (i
))
1114 addr
= reg_equiv_address (i
);
1118 if (reg_renumber
[i
] < 0)
1120 rtx reg
= regno_reg_rtx
[i
];
1122 REG_USERVAR_P (reg
) = 0;
1123 PUT_CODE (reg
, MEM
);
1124 XEXP (reg
, 0) = addr
;
1125 if (reg_equiv_memory_loc (i
))
1126 MEM_COPY_ATTRIBUTES (reg
, reg_equiv_memory_loc (i
));
1128 MEM_ATTRS (reg
) = 0;
1129 MEM_NOTRAP_P (reg
) = 1;
1131 else if (reg_equiv_mem (i
))
1132 XEXP (reg_equiv_mem (i
), 0) = addr
;
1135 /* We don't want complex addressing modes in debug insns
1136 if simpler ones will do, so delegitimize equivalences
1138 if (MAY_HAVE_DEBUG_INSNS
&& reg_renumber
[i
] < 0)
1140 rtx reg
= regno_reg_rtx
[i
];
1144 if (reg_equiv_constant (i
))
1145 equiv
= reg_equiv_constant (i
);
1146 else if (reg_equiv_invariant (i
))
1147 equiv
= reg_equiv_invariant (i
);
1148 else if (reg
&& MEM_P (reg
))
1149 equiv
= targetm
.delegitimize_address (reg
);
1150 else if (reg
&& REG_P (reg
) && (int)REGNO (reg
) != i
)
1156 for (use
= DF_REG_USE_CHAIN (i
); use
; use
= next
)
1158 insn
= DF_REF_INSN (use
);
1160 /* Make sure the next ref is for a different instruction,
1161 so that we're not affected by the rescan. */
1162 next
= DF_REF_NEXT_REG (use
);
1163 while (next
&& DF_REF_INSN (next
) == insn
)
1164 next
= DF_REF_NEXT_REG (next
);
1166 if (DEBUG_INSN_P (insn
))
1170 INSN_VAR_LOCATION_LOC (insn
) = gen_rtx_UNKNOWN_VAR_LOC ();
1171 df_insn_rescan_debug_internal (insn
);
1174 INSN_VAR_LOCATION_LOC (insn
)
1175 = simplify_replace_rtx (INSN_VAR_LOCATION_LOC (insn
),
1182 /* We must set reload_completed now since the cleanup_subreg_operands call
1183 below will re-recognize each insn and reload may have generated insns
1184 which are only valid during and after reload. */
1185 reload_completed
= 1;
1187 /* Make a pass over all the insns and delete all USEs which we inserted
1188 only to tag a REG_EQUAL note on them. Remove all REG_DEAD and REG_UNUSED
1189 notes. Delete all CLOBBER insns, except those that refer to the return
1190 value and the special mem:BLK CLOBBERs added to prevent the scheduler
1191 from misarranging variable-array code, and simplify (subreg (reg))
1192 operands. Strip and regenerate REG_INC notes that may have been moved
1195 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
1201 replace_pseudos_in (& CALL_INSN_FUNCTION_USAGE (insn
),
1202 VOIDmode
, CALL_INSN_FUNCTION_USAGE (insn
));
1204 if ((GET_CODE (PATTERN (insn
)) == USE
1205 /* We mark with QImode USEs introduced by reload itself. */
1206 && (GET_MODE (insn
) == QImode
1207 || find_reg_note (insn
, REG_EQUAL
, NULL_RTX
)))
1208 || (GET_CODE (PATTERN (insn
)) == CLOBBER
1209 && (!MEM_P (XEXP (PATTERN (insn
), 0))
1210 || GET_MODE (XEXP (PATTERN (insn
), 0)) != BLKmode
1211 || (GET_CODE (XEXP (XEXP (PATTERN (insn
), 0), 0)) != SCRATCH
1212 && XEXP (XEXP (PATTERN (insn
), 0), 0)
1213 != stack_pointer_rtx
))
1214 && (!REG_P (XEXP (PATTERN (insn
), 0))
1215 || ! REG_FUNCTION_VALUE_P (XEXP (PATTERN (insn
), 0)))))
1221 /* Some CLOBBERs may survive until here and still reference unassigned
1222 pseudos with const equivalent, which may in turn cause ICE in later
1223 passes if the reference remains in place. */
1224 if (GET_CODE (PATTERN (insn
)) == CLOBBER
)
1225 replace_pseudos_in (& XEXP (PATTERN (insn
), 0),
1226 VOIDmode
, PATTERN (insn
));
1228 /* Discard obvious no-ops, even without -O. This optimization
1229 is fast and doesn't interfere with debugging. */
1230 if (NONJUMP_INSN_P (insn
)
1231 && GET_CODE (PATTERN (insn
)) == SET
1232 && REG_P (SET_SRC (PATTERN (insn
)))
1233 && REG_P (SET_DEST (PATTERN (insn
)))
1234 && (REGNO (SET_SRC (PATTERN (insn
)))
1235 == REGNO (SET_DEST (PATTERN (insn
)))))
1241 pnote
= ®_NOTES (insn
);
1244 if (REG_NOTE_KIND (*pnote
) == REG_DEAD
1245 || REG_NOTE_KIND (*pnote
) == REG_UNUSED
1246 || REG_NOTE_KIND (*pnote
) == REG_INC
)
1247 *pnote
= XEXP (*pnote
, 1);
1249 pnote
= &XEXP (*pnote
, 1);
1253 add_auto_inc_notes (insn
, PATTERN (insn
));
1256 /* Simplify (subreg (reg)) if it appears as an operand. */
1257 cleanup_subreg_operands (insn
);
1259 /* Clean up invalid ASMs so that they don't confuse later passes.
1261 if (asm_noperands (PATTERN (insn
)) >= 0)
1263 extract_insn (insn
);
1264 if (!constrain_operands (1))
1266 error_for_asm (insn
,
1267 "%<asm%> operand has impossible constraints");
1274 /* If we are doing generic stack checking, give a warning if this
1275 function's frame size is larger than we expect. */
1276 if (flag_stack_check
== GENERIC_STACK_CHECK
)
1278 HOST_WIDE_INT size
= get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE
;
1279 static int verbose_warned
= 0;
1281 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1282 if (df_regs_ever_live_p (i
) && ! fixed_regs
[i
] && call_used_regs
[i
])
1283 size
+= UNITS_PER_WORD
;
1285 if (size
> STACK_CHECK_MAX_FRAME_SIZE
)
1287 warning (0, "frame size too large for reliable stack checking");
1288 if (! verbose_warned
)
1290 warning (0, "try reducing the number of local variables");
1296 free (temp_pseudo_reg_arr
);
1298 /* Indicate that we no longer have known memory locations or constants. */
1301 free (reg_max_ref_width
);
1302 free (reg_old_renumber
);
1303 free (pseudo_previous_regs
);
1304 free (pseudo_forbidden_regs
);
1306 CLEAR_HARD_REG_SET (used_spill_regs
);
1307 for (i
= 0; i
< n_spills
; i
++)
1308 SET_HARD_REG_BIT (used_spill_regs
, spill_regs
[i
]);
1310 /* Free all the insn_chain structures at once. */
1311 obstack_free (&reload_obstack
, reload_startobj
);
1312 unused_insn_chains
= 0;
1314 inserted
= fixup_abnormal_edges ();
1316 /* We've possibly turned single trapping insn into multiple ones. */
1317 if (cfun
->can_throw_non_call_exceptions
)
1320 blocks
= sbitmap_alloc (last_basic_block_for_fn (cfun
));
1321 bitmap_ones (blocks
);
1322 find_many_sub_basic_blocks (blocks
);
1323 sbitmap_free (blocks
);
1327 commit_edge_insertions ();
1329 /* Replacing pseudos with their memory equivalents might have
1330 created shared rtx. Subsequent passes would get confused
1331 by this, so unshare everything here. */
1332 unshare_all_rtl_again (first
);
1334 #ifdef STACK_BOUNDARY
1335 /* init_emit has set the alignment of the hard frame pointer
1336 to STACK_BOUNDARY. It is very likely no longer valid if
1337 the hard frame pointer was used for register allocation. */
1338 if (!frame_pointer_needed
)
1339 REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM
) = BITS_PER_UNIT
;
1342 substitute_stack
.release ();
1344 gcc_assert (bitmap_empty_p (&spilled_pseudos
));
1346 reload_completed
= !failure
;
1351 /* Yet another special case. Unfortunately, reg-stack forces people to
1352 write incorrect clobbers in asm statements. These clobbers must not
1353 cause the register to appear in bad_spill_regs, otherwise we'll call
1354 fatal_insn later. We clear the corresponding regnos in the live
1355 register sets to avoid this.
1356 The whole thing is rather sick, I'm afraid. */
1359 maybe_fix_stack_asms (void)
1362 const char *constraints
[MAX_RECOG_OPERANDS
];
1363 enum machine_mode operand_mode
[MAX_RECOG_OPERANDS
];
1364 struct insn_chain
*chain
;
1366 for (chain
= reload_insn_chain
; chain
!= 0; chain
= chain
->next
)
1369 HARD_REG_SET clobbered
, allowed
;
1372 if (! INSN_P (chain
->insn
)
1373 || (noperands
= asm_noperands (PATTERN (chain
->insn
))) < 0)
1375 pat
= PATTERN (chain
->insn
);
1376 if (GET_CODE (pat
) != PARALLEL
)
1379 CLEAR_HARD_REG_SET (clobbered
);
1380 CLEAR_HARD_REG_SET (allowed
);
1382 /* First, make a mask of all stack regs that are clobbered. */
1383 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
1385 rtx t
= XVECEXP (pat
, 0, i
);
1386 if (GET_CODE (t
) == CLOBBER
&& STACK_REG_P (XEXP (t
, 0)))
1387 SET_HARD_REG_BIT (clobbered
, REGNO (XEXP (t
, 0)));
1390 /* Get the operand values and constraints out of the insn. */
1391 decode_asm_operands (pat
, recog_data
.operand
, recog_data
.operand_loc
,
1392 constraints
, operand_mode
, NULL
);
1394 /* For every operand, see what registers are allowed. */
1395 for (i
= 0; i
< noperands
; i
++)
1397 const char *p
= constraints
[i
];
1398 /* For every alternative, we compute the class of registers allowed
1399 for reloading in CLS, and merge its contents into the reg set
1401 int cls
= (int) NO_REGS
;
1407 if (c
== '\0' || c
== ',' || c
== '#')
1409 /* End of one alternative - mark the regs in the current
1410 class, and reset the class. */
1411 IOR_HARD_REG_SET (allowed
, reg_class_contents
[cls
]);
1417 } while (c
!= '\0' && c
!= ',');
1426 cls
= (int) reg_class_subunion
[cls
][(int) GENERAL_REGS
];
1430 enum constraint_num cn
= lookup_constraint (p
);
1431 if (insn_extra_address_constraint (cn
))
1432 cls
= (int) reg_class_subunion
[cls
]
1433 [(int) base_reg_class (VOIDmode
, ADDR_SPACE_GENERIC
,
1436 cls
= (int) reg_class_subunion
[cls
]
1437 [reg_class_for_constraint (cn
)];
1440 p
+= CONSTRAINT_LEN (c
, p
);
1443 /* Those of the registers which are clobbered, but allowed by the
1444 constraints, must be usable as reload registers. So clear them
1445 out of the life information. */
1446 AND_HARD_REG_SET (allowed
, clobbered
);
1447 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1448 if (TEST_HARD_REG_BIT (allowed
, i
))
1450 CLEAR_REGNO_REG_SET (&chain
->live_throughout
, i
);
1451 CLEAR_REGNO_REG_SET (&chain
->dead_or_set
, i
);
1458 /* Copy the global variables n_reloads and rld into the corresponding elts
1461 copy_reloads (struct insn_chain
*chain
)
1463 chain
->n_reloads
= n_reloads
;
1464 chain
->rld
= XOBNEWVEC (&reload_obstack
, struct reload
, n_reloads
);
1465 memcpy (chain
->rld
, rld
, n_reloads
* sizeof (struct reload
));
1466 reload_insn_firstobj
= XOBNEWVAR (&reload_obstack
, char, 0);
1469 /* Walk the chain of insns, and determine for each whether it needs reloads
1470 and/or eliminations. Build the corresponding insns_need_reload list, and
1471 set something_needs_elimination as appropriate. */
1473 calculate_needs_all_insns (int global
)
1475 struct insn_chain
**pprev_reload
= &insns_need_reload
;
1476 struct insn_chain
*chain
, *next
= 0;
1478 something_needs_elimination
= 0;
1480 reload_insn_firstobj
= XOBNEWVAR (&reload_obstack
, char, 0);
1481 for (chain
= reload_insn_chain
; chain
!= 0; chain
= next
)
1483 rtx_insn
*insn
= chain
->insn
;
1487 /* Clear out the shortcuts. */
1488 chain
->n_reloads
= 0;
1489 chain
->need_elim
= 0;
1490 chain
->need_reload
= 0;
1491 chain
->need_operand_change
= 0;
1493 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1494 include REG_LABEL_OPERAND and REG_LABEL_TARGET), we need to see
1495 what effects this has on the known offsets at labels. */
1497 if (LABEL_P (insn
) || JUMP_P (insn
) || JUMP_TABLE_DATA_P (insn
)
1498 || (INSN_P (insn
) && REG_NOTES (insn
) != 0))
1499 set_label_offsets (insn
, insn
, 0);
1503 rtx old_body
= PATTERN (insn
);
1504 int old_code
= INSN_CODE (insn
);
1505 rtx old_notes
= REG_NOTES (insn
);
1506 int did_elimination
= 0;
1507 int operands_changed
= 0;
1509 /* Skip insns that only set an equivalence. */
1510 if (will_delete_init_insn_p (insn
))
1513 /* If needed, eliminate any eliminable registers. */
1514 if (num_eliminable
|| num_eliminable_invariants
)
1515 did_elimination
= eliminate_regs_in_insn (insn
, 0);
1517 /* Analyze the instruction. */
1518 operands_changed
= find_reloads (insn
, 0, spill_indirect_levels
,
1519 global
, spill_reg_order
);
1521 /* If a no-op set needs more than one reload, this is likely
1522 to be something that needs input address reloads. We
1523 can't get rid of this cleanly later, and it is of no use
1524 anyway, so discard it now.
1525 We only do this when expensive_optimizations is enabled,
1526 since this complements reload inheritance / output
1527 reload deletion, and it can make debugging harder. */
1528 if (flag_expensive_optimizations
&& n_reloads
> 1)
1530 rtx set
= single_set (insn
);
1533 ((SET_SRC (set
) == SET_DEST (set
)
1534 && REG_P (SET_SRC (set
))
1535 && REGNO (SET_SRC (set
)) >= FIRST_PSEUDO_REGISTER
)
1536 || (REG_P (SET_SRC (set
)) && REG_P (SET_DEST (set
))
1537 && reg_renumber
[REGNO (SET_SRC (set
))] < 0
1538 && reg_renumber
[REGNO (SET_DEST (set
))] < 0
1539 && reg_equiv_memory_loc (REGNO (SET_SRC (set
))) != NULL
1540 && reg_equiv_memory_loc (REGNO (SET_DEST (set
))) != NULL
1541 && rtx_equal_p (reg_equiv_memory_loc (REGNO (SET_SRC (set
))),
1542 reg_equiv_memory_loc (REGNO (SET_DEST (set
)))))))
1544 if (ira_conflicts_p
)
1545 /* Inform IRA about the insn deletion. */
1546 ira_mark_memory_move_deletion (REGNO (SET_DEST (set
)),
1547 REGNO (SET_SRC (set
)));
1549 /* Delete it from the reload chain. */
1551 chain
->prev
->next
= next
;
1553 reload_insn_chain
= next
;
1555 next
->prev
= chain
->prev
;
1556 chain
->next
= unused_insn_chains
;
1557 unused_insn_chains
= chain
;
1562 update_eliminable_offsets ();
1564 /* Remember for later shortcuts which insns had any reloads or
1565 register eliminations. */
1566 chain
->need_elim
= did_elimination
;
1567 chain
->need_reload
= n_reloads
> 0;
1568 chain
->need_operand_change
= operands_changed
;
1570 /* Discard any register replacements done. */
1571 if (did_elimination
)
1573 obstack_free (&reload_obstack
, reload_insn_firstobj
);
1574 PATTERN (insn
) = old_body
;
1575 INSN_CODE (insn
) = old_code
;
1576 REG_NOTES (insn
) = old_notes
;
1577 something_needs_elimination
= 1;
1580 something_needs_operands_changed
|= operands_changed
;
1584 copy_reloads (chain
);
1585 *pprev_reload
= chain
;
1586 pprev_reload
= &chain
->next_need_reload
;
1593 /* This function is called from the register allocator to set up estimates
1594 for the cost of eliminating pseudos which have REG_EQUIV equivalences to
1595 an invariant. The structure is similar to calculate_needs_all_insns. */
1598 calculate_elim_costs_all_insns (void)
1600 int *reg_equiv_init_cost
;
1604 reg_equiv_init_cost
= XCNEWVEC (int, max_regno
);
1606 init_eliminable_invariants (get_insns (), false);
1608 set_initial_elim_offsets ();
1609 set_initial_label_offsets ();
1611 FOR_EACH_BB_FN (bb
, cfun
)
1616 FOR_BB_INSNS (bb
, insn
)
1618 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1619 include REG_LABEL_OPERAND and REG_LABEL_TARGET), we need to see
1620 what effects this has on the known offsets at labels. */
1622 if (LABEL_P (insn
) || JUMP_P (insn
) || JUMP_TABLE_DATA_P (insn
)
1623 || (INSN_P (insn
) && REG_NOTES (insn
) != 0))
1624 set_label_offsets (insn
, insn
, 0);
1628 rtx set
= single_set (insn
);
1630 /* Skip insns that only set an equivalence. */
1631 if (set
&& REG_P (SET_DEST (set
))
1632 && reg_renumber
[REGNO (SET_DEST (set
))] < 0
1633 && (reg_equiv_constant (REGNO (SET_DEST (set
)))
1634 || reg_equiv_invariant (REGNO (SET_DEST (set
)))))
1636 unsigned regno
= REGNO (SET_DEST (set
));
1637 rtx init
= reg_equiv_init (regno
);
1640 rtx t
= eliminate_regs_1 (SET_SRC (set
), VOIDmode
, insn
,
1642 int cost
= set_src_cost (t
, optimize_bb_for_speed_p (bb
));
1643 int freq
= REG_FREQ_FROM_BB (bb
);
1645 reg_equiv_init_cost
[regno
] = cost
* freq
;
1649 /* If needed, eliminate any eliminable registers. */
1650 if (num_eliminable
|| num_eliminable_invariants
)
1651 elimination_costs_in_insn (insn
);
1654 update_eliminable_offsets ();
1658 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
1660 if (reg_equiv_invariant (i
))
1662 if (reg_equiv_init (i
))
1664 int cost
= reg_equiv_init_cost
[i
];
1667 "Reg %d has equivalence, initial gains %d\n", i
, cost
);
1669 ira_adjust_equiv_reg_cost (i
, cost
);
1675 "Reg %d had equivalence, but can't be eliminated\n",
1677 ira_adjust_equiv_reg_cost (i
, 0);
1682 free (reg_equiv_init_cost
);
1683 free (offsets_known_at
);
1686 offsets_known_at
= NULL
;
1689 /* Comparison function for qsort to decide which of two reloads
1690 should be handled first. *P1 and *P2 are the reload numbers. */
1693 reload_reg_class_lower (const void *r1p
, const void *r2p
)
1695 int r1
= *(const short *) r1p
, r2
= *(const short *) r2p
;
1698 /* Consider required reloads before optional ones. */
1699 t
= rld
[r1
].optional
- rld
[r2
].optional
;
1703 /* Count all solitary classes before non-solitary ones. */
1704 t
= ((reg_class_size
[(int) rld
[r2
].rclass
] == 1)
1705 - (reg_class_size
[(int) rld
[r1
].rclass
] == 1));
1709 /* Aside from solitaires, consider all multi-reg groups first. */
1710 t
= rld
[r2
].nregs
- rld
[r1
].nregs
;
1714 /* Consider reloads in order of increasing reg-class number. */
1715 t
= (int) rld
[r1
].rclass
- (int) rld
[r2
].rclass
;
1719 /* If reloads are equally urgent, sort by reload number,
1720 so that the results of qsort leave nothing to chance. */
1724 /* The cost of spilling each hard reg. */
1725 static int spill_cost
[FIRST_PSEUDO_REGISTER
];
1727 /* When spilling multiple hard registers, we use SPILL_COST for the first
1728 spilled hard reg and SPILL_ADD_COST for subsequent regs. SPILL_ADD_COST
1729 only the first hard reg for a multi-reg pseudo. */
1730 static int spill_add_cost
[FIRST_PSEUDO_REGISTER
];
1732 /* Map of hard regno to pseudo regno currently occupying the hard
1734 static int hard_regno_to_pseudo_regno
[FIRST_PSEUDO_REGISTER
];
1736 /* Update the spill cost arrays, considering that pseudo REG is live. */
1739 count_pseudo (int reg
)
1741 int freq
= REG_FREQ (reg
);
1742 int r
= reg_renumber
[reg
];
1745 /* Ignore spilled pseudo-registers which can be here only if IRA is used. */
1746 if (ira_conflicts_p
&& r
< 0)
1749 if (REGNO_REG_SET_P (&pseudos_counted
, reg
)
1750 || REGNO_REG_SET_P (&spilled_pseudos
, reg
))
1753 SET_REGNO_REG_SET (&pseudos_counted
, reg
);
1755 gcc_assert (r
>= 0);
1757 spill_add_cost
[r
] += freq
;
1758 nregs
= hard_regno_nregs
[r
][PSEUDO_REGNO_MODE (reg
)];
1761 hard_regno_to_pseudo_regno
[r
+ nregs
] = reg
;
1762 spill_cost
[r
+ nregs
] += freq
;
1766 /* Calculate the SPILL_COST and SPILL_ADD_COST arrays and determine the
1767 contents of BAD_SPILL_REGS for the insn described by CHAIN. */
1770 order_regs_for_reload (struct insn_chain
*chain
)
1773 HARD_REG_SET used_by_pseudos
;
1774 HARD_REG_SET used_by_pseudos2
;
1775 reg_set_iterator rsi
;
1777 COPY_HARD_REG_SET (bad_spill_regs
, fixed_reg_set
);
1779 memset (spill_cost
, 0, sizeof spill_cost
);
1780 memset (spill_add_cost
, 0, sizeof spill_add_cost
);
1781 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1782 hard_regno_to_pseudo_regno
[i
] = -1;
1784 /* Count number of uses of each hard reg by pseudo regs allocated to it
1785 and then order them by decreasing use. First exclude hard registers
1786 that are live in or across this insn. */
1788 REG_SET_TO_HARD_REG_SET (used_by_pseudos
, &chain
->live_throughout
);
1789 REG_SET_TO_HARD_REG_SET (used_by_pseudos2
, &chain
->dead_or_set
);
1790 IOR_HARD_REG_SET (bad_spill_regs
, used_by_pseudos
);
1791 IOR_HARD_REG_SET (bad_spill_regs
, used_by_pseudos2
);
1793 /* Now find out which pseudos are allocated to it, and update
1795 CLEAR_REG_SET (&pseudos_counted
);
1797 EXECUTE_IF_SET_IN_REG_SET
1798 (&chain
->live_throughout
, FIRST_PSEUDO_REGISTER
, i
, rsi
)
1802 EXECUTE_IF_SET_IN_REG_SET
1803 (&chain
->dead_or_set
, FIRST_PSEUDO_REGISTER
, i
, rsi
)
1807 CLEAR_REG_SET (&pseudos_counted
);
1810 /* Vector of reload-numbers showing the order in which the reloads should
1812 static short reload_order
[MAX_RELOADS
];
1814 /* This is used to keep track of the spill regs used in one insn. */
1815 static HARD_REG_SET used_spill_regs_local
;
1817 /* We decided to spill hard register SPILLED, which has a size of
1818 SPILLED_NREGS. Determine how pseudo REG, which is live during the insn,
1819 is affected. We will add it to SPILLED_PSEUDOS if necessary, and we will
1820 update SPILL_COST/SPILL_ADD_COST. */
1823 count_spilled_pseudo (int spilled
, int spilled_nregs
, int reg
)
1825 int freq
= REG_FREQ (reg
);
1826 int r
= reg_renumber
[reg
];
1829 /* Ignore spilled pseudo-registers which can be here only if IRA is used. */
1830 if (ira_conflicts_p
&& r
< 0)
1833 gcc_assert (r
>= 0);
1835 nregs
= hard_regno_nregs
[r
][PSEUDO_REGNO_MODE (reg
)];
1837 if (REGNO_REG_SET_P (&spilled_pseudos
, reg
)
1838 || spilled
+ spilled_nregs
<= r
|| r
+ nregs
<= spilled
)
1841 SET_REGNO_REG_SET (&spilled_pseudos
, reg
);
1843 spill_add_cost
[r
] -= freq
;
1846 hard_regno_to_pseudo_regno
[r
+ nregs
] = -1;
1847 spill_cost
[r
+ nregs
] -= freq
;
1851 /* Find reload register to use for reload number ORDER. */
1854 find_reg (struct insn_chain
*chain
, int order
)
1856 int rnum
= reload_order
[order
];
1857 struct reload
*rl
= rld
+ rnum
;
1858 int best_cost
= INT_MAX
;
1860 unsigned int i
, j
, n
;
1862 HARD_REG_SET not_usable
;
1863 HARD_REG_SET used_by_other_reload
;
1864 reg_set_iterator rsi
;
1865 static int regno_pseudo_regs
[FIRST_PSEUDO_REGISTER
];
1866 static int best_regno_pseudo_regs
[FIRST_PSEUDO_REGISTER
];
1868 COPY_HARD_REG_SET (not_usable
, bad_spill_regs
);
1869 IOR_HARD_REG_SET (not_usable
, bad_spill_regs_global
);
1870 IOR_COMPL_HARD_REG_SET (not_usable
, reg_class_contents
[rl
->rclass
]);
1872 CLEAR_HARD_REG_SET (used_by_other_reload
);
1873 for (k
= 0; k
< order
; k
++)
1875 int other
= reload_order
[k
];
1877 if (rld
[other
].regno
>= 0 && reloads_conflict (other
, rnum
))
1878 for (j
= 0; j
< rld
[other
].nregs
; j
++)
1879 SET_HARD_REG_BIT (used_by_other_reload
, rld
[other
].regno
+ j
);
1882 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1884 #ifdef REG_ALLOC_ORDER
1885 unsigned int regno
= reg_alloc_order
[i
];
1887 unsigned int regno
= i
;
1890 if (! TEST_HARD_REG_BIT (not_usable
, regno
)
1891 && ! TEST_HARD_REG_BIT (used_by_other_reload
, regno
)
1892 && HARD_REGNO_MODE_OK (regno
, rl
->mode
))
1894 int this_cost
= spill_cost
[regno
];
1896 unsigned int this_nregs
= hard_regno_nregs
[regno
][rl
->mode
];
1898 for (j
= 1; j
< this_nregs
; j
++)
1900 this_cost
+= spill_add_cost
[regno
+ j
];
1901 if ((TEST_HARD_REG_BIT (not_usable
, regno
+ j
))
1902 || TEST_HARD_REG_BIT (used_by_other_reload
, regno
+ j
))
1908 if (ira_conflicts_p
)
1910 /* Ask IRA to find a better pseudo-register for
1912 for (n
= j
= 0; j
< this_nregs
; j
++)
1914 int r
= hard_regno_to_pseudo_regno
[regno
+ j
];
1918 if (n
== 0 || regno_pseudo_regs
[n
- 1] != r
)
1919 regno_pseudo_regs
[n
++] = r
;
1921 regno_pseudo_regs
[n
++] = -1;
1923 || ira_better_spill_reload_regno_p (regno_pseudo_regs
,
1924 best_regno_pseudo_regs
,
1931 best_regno_pseudo_regs
[j
] = regno_pseudo_regs
[j
];
1932 if (regno_pseudo_regs
[j
] < 0)
1939 if (rl
->in
&& REG_P (rl
->in
) && REGNO (rl
->in
) == regno
)
1941 if (rl
->out
&& REG_P (rl
->out
) && REGNO (rl
->out
) == regno
)
1943 if (this_cost
< best_cost
1944 /* Among registers with equal cost, prefer caller-saved ones, or
1945 use REG_ALLOC_ORDER if it is defined. */
1946 || (this_cost
== best_cost
1947 #ifdef REG_ALLOC_ORDER
1948 && (inv_reg_alloc_order
[regno
]
1949 < inv_reg_alloc_order
[best_reg
])
1951 && call_used_regs
[regno
]
1952 && ! call_used_regs
[best_reg
]
1957 best_cost
= this_cost
;
1965 fprintf (dump_file
, "Using reg %d for reload %d\n", best_reg
, rnum
);
1967 rl
->nregs
= hard_regno_nregs
[best_reg
][rl
->mode
];
1968 rl
->regno
= best_reg
;
1970 EXECUTE_IF_SET_IN_REG_SET
1971 (&chain
->live_throughout
, FIRST_PSEUDO_REGISTER
, j
, rsi
)
1973 count_spilled_pseudo (best_reg
, rl
->nregs
, j
);
1976 EXECUTE_IF_SET_IN_REG_SET
1977 (&chain
->dead_or_set
, FIRST_PSEUDO_REGISTER
, j
, rsi
)
1979 count_spilled_pseudo (best_reg
, rl
->nregs
, j
);
1982 for (i
= 0; i
< rl
->nregs
; i
++)
1984 gcc_assert (spill_cost
[best_reg
+ i
] == 0);
1985 gcc_assert (spill_add_cost
[best_reg
+ i
] == 0);
1986 gcc_assert (hard_regno_to_pseudo_regno
[best_reg
+ i
] == -1);
1987 SET_HARD_REG_BIT (used_spill_regs_local
, best_reg
+ i
);
1992 /* Find more reload regs to satisfy the remaining need of an insn, which
1994 Do it by ascending class number, since otherwise a reg
1995 might be spilled for a big class and might fail to count
1996 for a smaller class even though it belongs to that class. */
1999 find_reload_regs (struct insn_chain
*chain
)
2003 /* In order to be certain of getting the registers we need,
2004 we must sort the reloads into order of increasing register class.
2005 Then our grabbing of reload registers will parallel the process
2006 that provided the reload registers. */
2007 for (i
= 0; i
< chain
->n_reloads
; i
++)
2009 /* Show whether this reload already has a hard reg. */
2010 if (chain
->rld
[i
].reg_rtx
)
2012 int regno
= REGNO (chain
->rld
[i
].reg_rtx
);
2013 chain
->rld
[i
].regno
= regno
;
2015 = hard_regno_nregs
[regno
][GET_MODE (chain
->rld
[i
].reg_rtx
)];
2018 chain
->rld
[i
].regno
= -1;
2019 reload_order
[i
] = i
;
2022 n_reloads
= chain
->n_reloads
;
2023 memcpy (rld
, chain
->rld
, n_reloads
* sizeof (struct reload
));
2025 CLEAR_HARD_REG_SET (used_spill_regs_local
);
2028 fprintf (dump_file
, "Spilling for insn %d.\n", INSN_UID (chain
->insn
));
2030 qsort (reload_order
, n_reloads
, sizeof (short), reload_reg_class_lower
);
2032 /* Compute the order of preference for hard registers to spill. */
2034 order_regs_for_reload (chain
);
2036 for (i
= 0; i
< n_reloads
; i
++)
2038 int r
= reload_order
[i
];
2040 /* Ignore reloads that got marked inoperative. */
2041 if ((rld
[r
].out
!= 0 || rld
[r
].in
!= 0 || rld
[r
].secondary_p
)
2042 && ! rld
[r
].optional
2043 && rld
[r
].regno
== -1)
2044 if (! find_reg (chain
, i
))
2047 fprintf (dump_file
, "reload failure for reload %d\n", r
);
2048 spill_failure (chain
->insn
, rld
[r
].rclass
);
2054 COPY_HARD_REG_SET (chain
->used_spill_regs
, used_spill_regs_local
);
2055 IOR_HARD_REG_SET (used_spill_regs
, used_spill_regs_local
);
2057 memcpy (chain
->rld
, rld
, n_reloads
* sizeof (struct reload
));
2061 select_reload_regs (void)
2063 struct insn_chain
*chain
;
2065 /* Try to satisfy the needs for each insn. */
2066 for (chain
= insns_need_reload
; chain
!= 0;
2067 chain
= chain
->next_need_reload
)
2068 find_reload_regs (chain
);
2071 /* Delete all insns that were inserted by emit_caller_save_insns during
2074 delete_caller_save_insns (void)
2076 struct insn_chain
*c
= reload_insn_chain
;
2080 while (c
!= 0 && c
->is_caller_save_insn
)
2082 struct insn_chain
*next
= c
->next
;
2083 rtx_insn
*insn
= c
->insn
;
2085 if (c
== reload_insn_chain
)
2086 reload_insn_chain
= next
;
2090 next
->prev
= c
->prev
;
2092 c
->prev
->next
= next
;
2093 c
->next
= unused_insn_chains
;
2094 unused_insn_chains
= c
;
2102 /* Handle the failure to find a register to spill.
2103 INSN should be one of the insns which needed this particular spill reg. */
2106 spill_failure (rtx_insn
*insn
, enum reg_class rclass
)
2108 if (asm_noperands (PATTERN (insn
)) >= 0)
2109 error_for_asm (insn
, "can%'t find a register in class %qs while "
2110 "reloading %<asm%>",
2111 reg_class_names
[rclass
]);
2114 error ("unable to find a register to spill in class %qs",
2115 reg_class_names
[rclass
]);
2119 fprintf (dump_file
, "\nReloads for insn # %d\n", INSN_UID (insn
));
2120 debug_reload_to_stream (dump_file
);
2122 fatal_insn ("this is the insn:", insn
);
2126 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
2127 data that is dead in INSN. */
2130 delete_dead_insn (rtx_insn
*insn
)
2132 rtx_insn
*prev
= prev_active_insn (insn
);
2135 /* If the previous insn sets a register that dies in our insn make
2136 a note that we want to run DCE immediately after reload.
2138 We used to delete the previous insn & recurse, but that's wrong for
2139 block local equivalences. Instead of trying to figure out the exact
2140 circumstances where we can delete the potentially dead insns, just
2141 let DCE do the job. */
2142 if (prev
&& BLOCK_FOR_INSN (prev
) == BLOCK_FOR_INSN (insn
)
2143 && GET_CODE (PATTERN (prev
)) == SET
2144 && (prev_dest
= SET_DEST (PATTERN (prev
)), REG_P (prev_dest
))
2145 && reg_mentioned_p (prev_dest
, PATTERN (insn
))
2146 && find_regno_note (insn
, REG_DEAD
, REGNO (prev_dest
))
2147 && ! side_effects_p (SET_SRC (PATTERN (prev
))))
2150 SET_INSN_DELETED (insn
);
2153 /* Modify the home of pseudo-reg I.
2154 The new home is present in reg_renumber[I].
2156 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
2157 or it may be -1, meaning there is none or it is not relevant.
2158 This is used so that all pseudos spilled from a given hard reg
2159 can share one stack slot. */
2162 alter_reg (int i
, int from_reg
, bool dont_share_p
)
2164 /* When outputting an inline function, this can happen
2165 for a reg that isn't actually used. */
2166 if (regno_reg_rtx
[i
] == 0)
2169 /* If the reg got changed to a MEM at rtl-generation time,
2171 if (!REG_P (regno_reg_rtx
[i
]))
2174 /* Modify the reg-rtx to contain the new hard reg
2175 number or else to contain its pseudo reg number. */
2176 SET_REGNO (regno_reg_rtx
[i
],
2177 reg_renumber
[i
] >= 0 ? reg_renumber
[i
] : i
);
2179 /* If we have a pseudo that is needed but has no hard reg or equivalent,
2180 allocate a stack slot for it. */
2182 if (reg_renumber
[i
] < 0
2183 && REG_N_REFS (i
) > 0
2184 && reg_equiv_constant (i
) == 0
2185 && (reg_equiv_invariant (i
) == 0
2186 || reg_equiv_init (i
) == 0)
2187 && reg_equiv_memory_loc (i
) == 0)
2190 enum machine_mode mode
= GET_MODE (regno_reg_rtx
[i
]);
2191 unsigned int inherent_size
= PSEUDO_REGNO_BYTES (i
);
2192 unsigned int inherent_align
= GET_MODE_ALIGNMENT (mode
);
2193 unsigned int total_size
= MAX (inherent_size
, reg_max_ref_width
[i
]);
2194 unsigned int min_align
= reg_max_ref_width
[i
] * BITS_PER_UNIT
;
2197 something_was_spilled
= true;
2199 if (ira_conflicts_p
)
2201 /* Mark the spill for IRA. */
2202 SET_REGNO_REG_SET (&spilled_pseudos
, i
);
2204 x
= ira_reuse_stack_slot (i
, inherent_size
, total_size
);
2210 /* Each pseudo reg has an inherent size which comes from its own mode,
2211 and a total size which provides room for paradoxical subregs
2212 which refer to the pseudo reg in wider modes.
2214 We can use a slot already allocated if it provides both
2215 enough inherent space and enough total space.
2216 Otherwise, we allocate a new slot, making sure that it has no less
2217 inherent space, and no less total space, then the previous slot. */
2218 else if (from_reg
== -1 || (!dont_share_p
&& ira_conflicts_p
))
2222 /* No known place to spill from => no slot to reuse. */
2223 x
= assign_stack_local (mode
, total_size
,
2224 min_align
> inherent_align
2225 || total_size
> inherent_size
? -1 : 0);
2229 /* Cancel the big-endian correction done in assign_stack_local.
2230 Get the address of the beginning of the slot. This is so we
2231 can do a big-endian correction unconditionally below. */
2232 if (BYTES_BIG_ENDIAN
)
2234 adjust
= inherent_size
- total_size
;
2237 = adjust_address_nv (x
, mode_for_size (total_size
2243 if (! dont_share_p
&& ira_conflicts_p
)
2244 /* Inform IRA about allocation a new stack slot. */
2245 ira_mark_new_stack_slot (stack_slot
, i
, total_size
);
2248 /* Reuse a stack slot if possible. */
2249 else if (spill_stack_slot
[from_reg
] != 0
2250 && spill_stack_slot_width
[from_reg
] >= total_size
2251 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot
[from_reg
]))
2253 && MEM_ALIGN (spill_stack_slot
[from_reg
]) >= min_align
)
2254 x
= spill_stack_slot
[from_reg
];
2256 /* Allocate a bigger slot. */
2259 /* Compute maximum size needed, both for inherent size
2260 and for total size. */
2263 if (spill_stack_slot
[from_reg
])
2265 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot
[from_reg
]))
2267 mode
= GET_MODE (spill_stack_slot
[from_reg
]);
2268 if (spill_stack_slot_width
[from_reg
] > total_size
)
2269 total_size
= spill_stack_slot_width
[from_reg
];
2270 if (MEM_ALIGN (spill_stack_slot
[from_reg
]) > min_align
)
2271 min_align
= MEM_ALIGN (spill_stack_slot
[from_reg
]);
2274 /* Make a slot with that size. */
2275 x
= assign_stack_local (mode
, total_size
,
2276 min_align
> inherent_align
2277 || total_size
> inherent_size
? -1 : 0);
2280 /* Cancel the big-endian correction done in assign_stack_local.
2281 Get the address of the beginning of the slot. This is so we
2282 can do a big-endian correction unconditionally below. */
2283 if (BYTES_BIG_ENDIAN
)
2285 adjust
= GET_MODE_SIZE (mode
) - total_size
;
2288 = adjust_address_nv (x
, mode_for_size (total_size
2294 spill_stack_slot
[from_reg
] = stack_slot
;
2295 spill_stack_slot_width
[from_reg
] = total_size
;
2298 /* On a big endian machine, the "address" of the slot
2299 is the address of the low part that fits its inherent mode. */
2300 if (BYTES_BIG_ENDIAN
&& inherent_size
< total_size
)
2301 adjust
+= (total_size
- inherent_size
);
2303 /* If we have any adjustment to make, or if the stack slot is the
2304 wrong mode, make a new stack slot. */
2305 x
= adjust_address_nv (x
, GET_MODE (regno_reg_rtx
[i
]), adjust
);
2307 /* Set all of the memory attributes as appropriate for a spill. */
2308 set_mem_attrs_for_spill (x
);
2310 /* Save the stack slot for later. */
2311 reg_equiv_memory_loc (i
) = x
;
2315 /* Mark the slots in regs_ever_live for the hard regs used by
2316 pseudo-reg number REGNO, accessed in MODE. */
2319 mark_home_live_1 (int regno
, enum machine_mode mode
)
2323 i
= reg_renumber
[regno
];
2326 lim
= end_hard_regno (mode
, i
);
2328 df_set_regs_ever_live (i
++, true);
2331 /* Mark the slots in regs_ever_live for the hard regs
2332 used by pseudo-reg number REGNO. */
2335 mark_home_live (int regno
)
2337 if (reg_renumber
[regno
] >= 0)
2338 mark_home_live_1 (regno
, PSEUDO_REGNO_MODE (regno
));
2341 /* This function handles the tracking of elimination offsets around branches.
2343 X is a piece of RTL being scanned.
2345 INSN is the insn that it came from, if any.
2347 INITIAL_P is nonzero if we are to set the offset to be the initial
2348 offset and zero if we are setting the offset of the label to be the
2352 set_label_offsets (rtx x
, rtx_insn
*insn
, int initial_p
)
2354 enum rtx_code code
= GET_CODE (x
);
2357 struct elim_table
*p
;
2362 if (LABEL_REF_NONLOCAL_P (x
))
2365 x
= LABEL_REF_LABEL (x
);
2367 /* ... fall through ... */
2370 /* If we know nothing about this label, set the desired offsets. Note
2371 that this sets the offset at a label to be the offset before a label
2372 if we don't know anything about the label. This is not correct for
2373 the label after a BARRIER, but is the best guess we can make. If
2374 we guessed wrong, we will suppress an elimination that might have
2375 been possible had we been able to guess correctly. */
2377 if (! offsets_known_at
[CODE_LABEL_NUMBER (x
) - first_label_num
])
2379 for (i
= 0; i
< NUM_ELIMINABLE_REGS
; i
++)
2380 offsets_at
[CODE_LABEL_NUMBER (x
) - first_label_num
][i
]
2381 = (initial_p
? reg_eliminate
[i
].initial_offset
2382 : reg_eliminate
[i
].offset
);
2383 offsets_known_at
[CODE_LABEL_NUMBER (x
) - first_label_num
] = 1;
2386 /* Otherwise, if this is the definition of a label and it is
2387 preceded by a BARRIER, set our offsets to the known offset of
2391 && (tem
= prev_nonnote_insn (insn
)) != 0
2393 set_offsets_for_label (insn
);
2395 /* If neither of the above cases is true, compare each offset
2396 with those previously recorded and suppress any eliminations
2397 where the offsets disagree. */
2399 for (i
= 0; i
< NUM_ELIMINABLE_REGS
; i
++)
2400 if (offsets_at
[CODE_LABEL_NUMBER (x
) - first_label_num
][i
]
2401 != (initial_p
? reg_eliminate
[i
].initial_offset
2402 : reg_eliminate
[i
].offset
))
2403 reg_eliminate
[i
].can_eliminate
= 0;
2407 case JUMP_TABLE_DATA
:
2408 set_label_offsets (PATTERN (insn
), insn
, initial_p
);
2412 set_label_offsets (PATTERN (insn
), insn
, initial_p
);
2414 /* ... fall through ... */
2418 /* Any labels mentioned in REG_LABEL_OPERAND notes can be branched
2419 to indirectly and hence must have all eliminations at their
2421 for (tem
= REG_NOTES (x
); tem
; tem
= XEXP (tem
, 1))
2422 if (REG_NOTE_KIND (tem
) == REG_LABEL_OPERAND
)
2423 set_label_offsets (XEXP (tem
, 0), insn
, 1);
2429 /* Each of the labels in the parallel or address vector must be
2430 at their initial offsets. We want the first field for PARALLEL
2431 and ADDR_VEC and the second field for ADDR_DIFF_VEC. */
2433 for (i
= 0; i
< (unsigned) XVECLEN (x
, code
== ADDR_DIFF_VEC
); i
++)
2434 set_label_offsets (XVECEXP (x
, code
== ADDR_DIFF_VEC
, i
),
2439 /* We only care about setting PC. If the source is not RETURN,
2440 IF_THEN_ELSE, or a label, disable any eliminations not at
2441 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2442 isn't one of those possibilities. For branches to a label,
2443 call ourselves recursively.
2445 Note that this can disable elimination unnecessarily when we have
2446 a non-local goto since it will look like a non-constant jump to
2447 someplace in the current function. This isn't a significant
2448 problem since such jumps will normally be when all elimination
2449 pairs are back to their initial offsets. */
2451 if (SET_DEST (x
) != pc_rtx
)
2454 switch (GET_CODE (SET_SRC (x
)))
2461 set_label_offsets (SET_SRC (x
), insn
, initial_p
);
2465 tem
= XEXP (SET_SRC (x
), 1);
2466 if (GET_CODE (tem
) == LABEL_REF
)
2467 set_label_offsets (LABEL_REF_LABEL (tem
), insn
, initial_p
);
2468 else if (GET_CODE (tem
) != PC
&& GET_CODE (tem
) != RETURN
)
2471 tem
= XEXP (SET_SRC (x
), 2);
2472 if (GET_CODE (tem
) == LABEL_REF
)
2473 set_label_offsets (LABEL_REF_LABEL (tem
), insn
, initial_p
);
2474 else if (GET_CODE (tem
) != PC
&& GET_CODE (tem
) != RETURN
)
2482 /* If we reach here, all eliminations must be at their initial
2483 offset because we are doing a jump to a variable address. */
2484 for (p
= reg_eliminate
; p
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; p
++)
2485 if (p
->offset
!= p
->initial_offset
)
2486 p
->can_eliminate
= 0;
2494 /* This function examines every reg that occurs in X and adjusts the
2495 costs for its elimination which are gathered by IRA. INSN is the
2496 insn in which X occurs. We do not recurse into MEM expressions. */
2499 note_reg_elim_costly (const_rtx x
, rtx insn
)
2501 subrtx_iterator::array_type array
;
2502 FOR_EACH_SUBRTX (iter
, array
, x
, NONCONST
)
2504 const_rtx x
= *iter
;
2506 iter
.skip_subrtxes ();
2508 && REGNO (x
) >= FIRST_PSEUDO_REGISTER
2509 && reg_equiv_init (REGNO (x
))
2510 && reg_equiv_invariant (REGNO (x
)))
2512 rtx t
= reg_equiv_invariant (REGNO (x
));
2513 rtx new_rtx
= eliminate_regs_1 (t
, Pmode
, insn
, true, true);
2514 int cost
= set_src_cost (new_rtx
, optimize_bb_for_speed_p (elim_bb
));
2515 int freq
= REG_FREQ_FROM_BB (elim_bb
);
2518 ira_adjust_equiv_reg_cost (REGNO (x
), -cost
* freq
);
2523 /* Scan X and replace any eliminable registers (such as fp) with a
2524 replacement (such as sp), plus an offset.
2526 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2527 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2528 MEM, we are allowed to replace a sum of a register and the constant zero
2529 with the register, which we cannot do outside a MEM. In addition, we need
2530 to record the fact that a register is referenced outside a MEM.
2532 If INSN is an insn, it is the insn containing X. If we replace a REG
2533 in a SET_DEST with an equivalent MEM and INSN is nonzero, write a
2534 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2535 the REG is being modified.
2537 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2538 That's used when we eliminate in expressions stored in notes.
2539 This means, do not set ref_outside_mem even if the reference
2542 If FOR_COSTS is true, we are being called before reload in order to
2543 estimate the costs of keeping registers with an equivalence unallocated.
2545 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2546 replacements done assuming all offsets are at their initial values. If
2547 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2548 encounter, return the actual location so that find_reloads will do
2549 the proper thing. */
2552 eliminate_regs_1 (rtx x
, enum machine_mode mem_mode
, rtx insn
,
2553 bool may_use_invariant
, bool for_costs
)
2555 enum rtx_code code
= GET_CODE (x
);
2556 struct elim_table
*ep
;
2563 if (! current_function_decl
)
2583 /* First handle the case where we encounter a bare register that
2584 is eliminable. Replace it with a PLUS. */
2585 if (regno
< FIRST_PSEUDO_REGISTER
)
2587 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
2589 if (ep
->from_rtx
== x
&& ep
->can_eliminate
)
2590 return plus_constant (Pmode
, ep
->to_rtx
, ep
->previous_offset
);
2593 else if (reg_renumber
&& reg_renumber
[regno
] < 0
2595 && reg_equiv_invariant (regno
))
2597 if (may_use_invariant
|| (insn
&& DEBUG_INSN_P (insn
)))
2598 return eliminate_regs_1 (copy_rtx (reg_equiv_invariant (regno
)),
2599 mem_mode
, insn
, true, for_costs
);
2600 /* There exists at least one use of REGNO that cannot be
2601 eliminated. Prevent the defining insn from being deleted. */
2602 reg_equiv_init (regno
) = NULL_RTX
;
2604 alter_reg (regno
, -1, true);
2608 /* You might think handling MINUS in a manner similar to PLUS is a
2609 good idea. It is not. It has been tried multiple times and every
2610 time the change has had to have been reverted.
2612 Other parts of reload know a PLUS is special (gen_reload for example)
2613 and require special code to handle code a reloaded PLUS operand.
2615 Also consider backends where the flags register is clobbered by a
2616 MINUS, but we can emit a PLUS that does not clobber flags (IA-32,
2617 lea instruction comes to mind). If we try to reload a MINUS, we
2618 may kill the flags register that was holding a useful value.
2620 So, please before trying to handle MINUS, consider reload as a
2621 whole instead of this little section as well as the backend issues. */
2623 /* If this is the sum of an eliminable register and a constant, rework
2625 if (REG_P (XEXP (x
, 0))
2626 && REGNO (XEXP (x
, 0)) < FIRST_PSEUDO_REGISTER
2627 && CONSTANT_P (XEXP (x
, 1)))
2629 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
2631 if (ep
->from_rtx
== XEXP (x
, 0) && ep
->can_eliminate
)
2633 /* The only time we want to replace a PLUS with a REG (this
2634 occurs when the constant operand of the PLUS is the negative
2635 of the offset) is when we are inside a MEM. We won't want
2636 to do so at other times because that would change the
2637 structure of the insn in a way that reload can't handle.
2638 We special-case the commonest situation in
2639 eliminate_regs_in_insn, so just replace a PLUS with a
2640 PLUS here, unless inside a MEM. */
2641 if (mem_mode
!= 0 && CONST_INT_P (XEXP (x
, 1))
2642 && INTVAL (XEXP (x
, 1)) == - ep
->previous_offset
)
2645 return gen_rtx_PLUS (Pmode
, ep
->to_rtx
,
2646 plus_constant (Pmode
, XEXP (x
, 1),
2647 ep
->previous_offset
));
2650 /* If the register is not eliminable, we are done since the other
2651 operand is a constant. */
2655 /* If this is part of an address, we want to bring any constant to the
2656 outermost PLUS. We will do this by doing register replacement in
2657 our operands and seeing if a constant shows up in one of them.
2659 Note that there is no risk of modifying the structure of the insn,
2660 since we only get called for its operands, thus we are either
2661 modifying the address inside a MEM, or something like an address
2662 operand of a load-address insn. */
2665 rtx new0
= eliminate_regs_1 (XEXP (x
, 0), mem_mode
, insn
, true,
2667 rtx new1
= eliminate_regs_1 (XEXP (x
, 1), mem_mode
, insn
, true,
2670 if (reg_renumber
&& (new0
!= XEXP (x
, 0) || new1
!= XEXP (x
, 1)))
2672 /* If one side is a PLUS and the other side is a pseudo that
2673 didn't get a hard register but has a reg_equiv_constant,
2674 we must replace the constant here since it may no longer
2675 be in the position of any operand. */
2676 if (GET_CODE (new0
) == PLUS
&& REG_P (new1
)
2677 && REGNO (new1
) >= FIRST_PSEUDO_REGISTER
2678 && reg_renumber
[REGNO (new1
)] < 0
2680 && reg_equiv_constant (REGNO (new1
)) != 0)
2681 new1
= reg_equiv_constant (REGNO (new1
));
2682 else if (GET_CODE (new1
) == PLUS
&& REG_P (new0
)
2683 && REGNO (new0
) >= FIRST_PSEUDO_REGISTER
2684 && reg_renumber
[REGNO (new0
)] < 0
2685 && reg_equiv_constant (REGNO (new0
)) != 0)
2686 new0
= reg_equiv_constant (REGNO (new0
));
2688 new_rtx
= form_sum (GET_MODE (x
), new0
, new1
);
2690 /* As above, if we are not inside a MEM we do not want to
2691 turn a PLUS into something else. We might try to do so here
2692 for an addition of 0 if we aren't optimizing. */
2693 if (! mem_mode
&& GET_CODE (new_rtx
) != PLUS
)
2694 return gen_rtx_PLUS (GET_MODE (x
), new_rtx
, const0_rtx
);
2702 /* If this is the product of an eliminable register and a
2703 constant, apply the distribute law and move the constant out
2704 so that we have (plus (mult ..) ..). This is needed in order
2705 to keep load-address insns valid. This case is pathological.
2706 We ignore the possibility of overflow here. */
2707 if (REG_P (XEXP (x
, 0))
2708 && REGNO (XEXP (x
, 0)) < FIRST_PSEUDO_REGISTER
2709 && CONST_INT_P (XEXP (x
, 1)))
2710 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
2712 if (ep
->from_rtx
== XEXP (x
, 0) && ep
->can_eliminate
)
2715 /* Refs inside notes or in DEBUG_INSNs don't count for
2717 && ! (insn
!= 0 && (GET_CODE (insn
) == EXPR_LIST
2718 || GET_CODE (insn
) == INSN_LIST
2719 || DEBUG_INSN_P (insn
))))
2720 ep
->ref_outside_mem
= 1;
2723 plus_constant (Pmode
,
2724 gen_rtx_MULT (Pmode
, ep
->to_rtx
, XEXP (x
, 1)),
2725 ep
->previous_offset
* INTVAL (XEXP (x
, 1)));
2728 /* ... fall through ... */
2732 /* See comments before PLUS about handling MINUS. */
2734 case DIV
: case UDIV
:
2735 case MOD
: case UMOD
:
2736 case AND
: case IOR
: case XOR
:
2737 case ROTATERT
: case ROTATE
:
2738 case ASHIFTRT
: case LSHIFTRT
: case ASHIFT
:
2740 case GE
: case GT
: case GEU
: case GTU
:
2741 case LE
: case LT
: case LEU
: case LTU
:
2743 rtx new0
= eliminate_regs_1 (XEXP (x
, 0), mem_mode
, insn
, false,
2745 rtx new1
= XEXP (x
, 1)
2746 ? eliminate_regs_1 (XEXP (x
, 1), mem_mode
, insn
, false,
2749 if (new0
!= XEXP (x
, 0) || new1
!= XEXP (x
, 1))
2750 return gen_rtx_fmt_ee (code
, GET_MODE (x
), new0
, new1
);
2755 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2758 new_rtx
= eliminate_regs_1 (XEXP (x
, 0), mem_mode
, insn
, true,
2760 if (new_rtx
!= XEXP (x
, 0))
2762 /* If this is a REG_DEAD note, it is not valid anymore.
2763 Using the eliminated version could result in creating a
2764 REG_DEAD note for the stack or frame pointer. */
2765 if (REG_NOTE_KIND (x
) == REG_DEAD
)
2767 ? eliminate_regs_1 (XEXP (x
, 1), mem_mode
, insn
, true,
2771 x
= alloc_reg_note (REG_NOTE_KIND (x
), new_rtx
, XEXP (x
, 1));
2775 /* ... fall through ... */
2779 /* Now do eliminations in the rest of the chain. If this was
2780 an EXPR_LIST, this might result in allocating more memory than is
2781 strictly needed, but it simplifies the code. */
2784 new_rtx
= eliminate_regs_1 (XEXP (x
, 1), mem_mode
, insn
, true,
2786 if (new_rtx
!= XEXP (x
, 1))
2788 gen_rtx_fmt_ee (GET_CODE (x
), GET_MODE (x
), XEXP (x
, 0), new_rtx
);
2796 /* We do not support elimination of a register that is modified.
2797 elimination_effects has already make sure that this does not
2803 /* We do not support elimination of a register that is modified.
2804 elimination_effects has already make sure that this does not
2805 happen. The only remaining case we need to consider here is
2806 that the increment value may be an eliminable register. */
2807 if (GET_CODE (XEXP (x
, 1)) == PLUS
2808 && XEXP (XEXP (x
, 1), 0) == XEXP (x
, 0))
2810 rtx new_rtx
= eliminate_regs_1 (XEXP (XEXP (x
, 1), 1), mem_mode
,
2811 insn
, true, for_costs
);
2813 if (new_rtx
!= XEXP (XEXP (x
, 1), 1))
2814 return gen_rtx_fmt_ee (code
, GET_MODE (x
), XEXP (x
, 0),
2815 gen_rtx_PLUS (GET_MODE (x
),
2816 XEXP (x
, 0), new_rtx
));
2820 case STRICT_LOW_PART
:
2822 case SIGN_EXTEND
: case ZERO_EXTEND
:
2823 case TRUNCATE
: case FLOAT_EXTEND
: case FLOAT_TRUNCATE
:
2824 case FLOAT
: case FIX
:
2825 case UNSIGNED_FIX
: case UNSIGNED_FLOAT
:
2834 new_rtx
= eliminate_regs_1 (XEXP (x
, 0), mem_mode
, insn
, false,
2836 if (new_rtx
!= XEXP (x
, 0))
2837 return gen_rtx_fmt_e (code
, GET_MODE (x
), new_rtx
);
2841 /* Similar to above processing, but preserve SUBREG_BYTE.
2842 Convert (subreg (mem)) to (mem) if not paradoxical.
2843 Also, if we have a non-paradoxical (subreg (pseudo)) and the
2844 pseudo didn't get a hard reg, we must replace this with the
2845 eliminated version of the memory location because push_reload
2846 may do the replacement in certain circumstances. */
2847 if (REG_P (SUBREG_REG (x
))
2848 && !paradoxical_subreg_p (x
)
2850 && reg_equiv_memory_loc (REGNO (SUBREG_REG (x
))) != 0)
2852 new_rtx
= SUBREG_REG (x
);
2855 new_rtx
= eliminate_regs_1 (SUBREG_REG (x
), mem_mode
, insn
, false, for_costs
);
2857 if (new_rtx
!= SUBREG_REG (x
))
2859 int x_size
= GET_MODE_SIZE (GET_MODE (x
));
2860 int new_size
= GET_MODE_SIZE (GET_MODE (new_rtx
));
2863 && ((x_size
< new_size
2864 #ifdef WORD_REGISTER_OPERATIONS
2865 /* On these machines, combine can create rtl of the form
2866 (set (subreg:m1 (reg:m2 R) 0) ...)
2867 where m1 < m2, and expects something interesting to
2868 happen to the entire word. Moreover, it will use the
2869 (reg:m2 R) later, expecting all bits to be preserved.
2870 So if the number of words is the same, preserve the
2871 subreg so that push_reload can see it. */
2872 && ! ((x_size
- 1) / UNITS_PER_WORD
2873 == (new_size
-1 ) / UNITS_PER_WORD
)
2876 || x_size
== new_size
)
2878 return adjust_address_nv (new_rtx
, GET_MODE (x
), SUBREG_BYTE (x
));
2880 return gen_rtx_SUBREG (GET_MODE (x
), new_rtx
, SUBREG_BYTE (x
));
2886 /* Our only special processing is to pass the mode of the MEM to our
2887 recursive call and copy the flags. While we are here, handle this
2888 case more efficiently. */
2890 new_rtx
= eliminate_regs_1 (XEXP (x
, 0), GET_MODE (x
), insn
, true,
2893 && memory_address_p (GET_MODE (x
), XEXP (x
, 0))
2894 && !memory_address_p (GET_MODE (x
), new_rtx
))
2895 note_reg_elim_costly (XEXP (x
, 0), insn
);
2897 return replace_equiv_address_nv (x
, new_rtx
);
2900 /* Handle insn_list USE that a call to a pure function may generate. */
2901 new_rtx
= eliminate_regs_1 (XEXP (x
, 0), VOIDmode
, insn
, false,
2903 if (new_rtx
!= XEXP (x
, 0))
2904 return gen_rtx_USE (GET_MODE (x
), new_rtx
);
2909 gcc_assert (insn
&& DEBUG_INSN_P (insn
));
2919 /* Process each of our operands recursively. If any have changed, make a
2921 fmt
= GET_RTX_FORMAT (code
);
2922 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++, fmt
++)
2926 new_rtx
= eliminate_regs_1 (XEXP (x
, i
), mem_mode
, insn
, false,
2928 if (new_rtx
!= XEXP (x
, i
) && ! copied
)
2930 x
= shallow_copy_rtx (x
);
2933 XEXP (x
, i
) = new_rtx
;
2935 else if (*fmt
== 'E')
2938 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
2940 new_rtx
= eliminate_regs_1 (XVECEXP (x
, i
, j
), mem_mode
, insn
, false,
2942 if (new_rtx
!= XVECEXP (x
, i
, j
) && ! copied_vec
)
2944 rtvec new_v
= gen_rtvec_v (XVECLEN (x
, i
),
2948 x
= shallow_copy_rtx (x
);
2951 XVEC (x
, i
) = new_v
;
2954 XVECEXP (x
, i
, j
) = new_rtx
;
2963 eliminate_regs (rtx x
, enum machine_mode mem_mode
, rtx insn
)
2965 return eliminate_regs_1 (x
, mem_mode
, insn
, false, false);
2968 /* Scan rtx X for modifications of elimination target registers. Update
2969 the table of eliminables to reflect the changed state. MEM_MODE is
2970 the mode of an enclosing MEM rtx, or VOIDmode if not within a MEM. */
2973 elimination_effects (rtx x
, enum machine_mode mem_mode
)
2975 enum rtx_code code
= GET_CODE (x
);
2976 struct elim_table
*ep
;
2998 /* First handle the case where we encounter a bare register that
2999 is eliminable. Replace it with a PLUS. */
3000 if (regno
< FIRST_PSEUDO_REGISTER
)
3002 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
3004 if (ep
->from_rtx
== x
&& ep
->can_eliminate
)
3007 ep
->ref_outside_mem
= 1;
3012 else if (reg_renumber
[regno
] < 0
3014 && reg_equiv_constant (regno
)
3015 && ! function_invariant_p (reg_equiv_constant (regno
)))
3016 elimination_effects (reg_equiv_constant (regno
), mem_mode
);
3025 /* If we modify the source of an elimination rule, disable it. */
3026 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3027 if (ep
->from_rtx
== XEXP (x
, 0))
3028 ep
->can_eliminate
= 0;
3030 /* If we modify the target of an elimination rule by adding a constant,
3031 update its offset. If we modify the target in any other way, we'll
3032 have to disable the rule as well. */
3033 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3034 if (ep
->to_rtx
== XEXP (x
, 0))
3036 int size
= GET_MODE_SIZE (mem_mode
);
3038 /* If more bytes than MEM_MODE are pushed, account for them. */
3039 #ifdef PUSH_ROUNDING
3040 if (ep
->to_rtx
== stack_pointer_rtx
)
3041 size
= PUSH_ROUNDING (size
);
3043 if (code
== PRE_DEC
|| code
== POST_DEC
)
3045 else if (code
== PRE_INC
|| code
== POST_INC
)
3047 else if (code
== PRE_MODIFY
|| code
== POST_MODIFY
)
3049 if (GET_CODE (XEXP (x
, 1)) == PLUS
3050 && XEXP (x
, 0) == XEXP (XEXP (x
, 1), 0)
3051 && CONST_INT_P (XEXP (XEXP (x
, 1), 1)))
3052 ep
->offset
-= INTVAL (XEXP (XEXP (x
, 1), 1));
3054 ep
->can_eliminate
= 0;
3058 /* These two aren't unary operators. */
3059 if (code
== POST_MODIFY
|| code
== PRE_MODIFY
)
3062 /* Fall through to generic unary operation case. */
3063 case STRICT_LOW_PART
:
3065 case SIGN_EXTEND
: case ZERO_EXTEND
:
3066 case TRUNCATE
: case FLOAT_EXTEND
: case FLOAT_TRUNCATE
:
3067 case FLOAT
: case FIX
:
3068 case UNSIGNED_FIX
: case UNSIGNED_FLOAT
:
3077 elimination_effects (XEXP (x
, 0), mem_mode
);
3081 if (REG_P (SUBREG_REG (x
))
3082 && (GET_MODE_SIZE (GET_MODE (x
))
3083 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
3085 && reg_equiv_memory_loc (REGNO (SUBREG_REG (x
))) != 0)
3088 elimination_effects (SUBREG_REG (x
), mem_mode
);
3092 /* If using a register that is the source of an eliminate we still
3093 think can be performed, note it cannot be performed since we don't
3094 know how this register is used. */
3095 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3096 if (ep
->from_rtx
== XEXP (x
, 0))
3097 ep
->can_eliminate
= 0;
3099 elimination_effects (XEXP (x
, 0), mem_mode
);
3103 /* If clobbering a register that is the replacement register for an
3104 elimination we still think can be performed, note that it cannot
3105 be performed. Otherwise, we need not be concerned about it. */
3106 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3107 if (ep
->to_rtx
== XEXP (x
, 0))
3108 ep
->can_eliminate
= 0;
3110 elimination_effects (XEXP (x
, 0), mem_mode
);
3114 /* Check for setting a register that we know about. */
3115 if (REG_P (SET_DEST (x
)))
3117 /* See if this is setting the replacement register for an
3120 If DEST is the hard frame pointer, we do nothing because we
3121 assume that all assignments to the frame pointer are for
3122 non-local gotos and are being done at a time when they are valid
3123 and do not disturb anything else. Some machines want to
3124 eliminate a fake argument pointer (or even a fake frame pointer)
3125 with either the real frame or the stack pointer. Assignments to
3126 the hard frame pointer must not prevent this elimination. */
3128 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
3130 if (ep
->to_rtx
== SET_DEST (x
)
3131 && SET_DEST (x
) != hard_frame_pointer_rtx
)
3133 /* If it is being incremented, adjust the offset. Otherwise,
3134 this elimination can't be done. */
3135 rtx src
= SET_SRC (x
);
3137 if (GET_CODE (src
) == PLUS
3138 && XEXP (src
, 0) == SET_DEST (x
)
3139 && CONST_INT_P (XEXP (src
, 1)))
3140 ep
->offset
-= INTVAL (XEXP (src
, 1));
3142 ep
->can_eliminate
= 0;
3146 elimination_effects (SET_DEST (x
), VOIDmode
);
3147 elimination_effects (SET_SRC (x
), VOIDmode
);
3151 /* Our only special processing is to pass the mode of the MEM to our
3153 elimination_effects (XEXP (x
, 0), GET_MODE (x
));
3160 fmt
= GET_RTX_FORMAT (code
);
3161 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++, fmt
++)
3164 elimination_effects (XEXP (x
, i
), mem_mode
);
3165 else if (*fmt
== 'E')
3166 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
3167 elimination_effects (XVECEXP (x
, i
, j
), mem_mode
);
3171 /* Descend through rtx X and verify that no references to eliminable registers
3172 remain. If any do remain, mark the involved register as not
3176 check_eliminable_occurrences (rtx x
)
3185 code
= GET_CODE (x
);
3187 if (code
== REG
&& REGNO (x
) < FIRST_PSEUDO_REGISTER
)
3189 struct elim_table
*ep
;
3191 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3192 if (ep
->from_rtx
== x
)
3193 ep
->can_eliminate
= 0;
3197 fmt
= GET_RTX_FORMAT (code
);
3198 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++, fmt
++)
3201 check_eliminable_occurrences (XEXP (x
, i
));
3202 else if (*fmt
== 'E')
3205 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
3206 check_eliminable_occurrences (XVECEXP (x
, i
, j
));
3211 /* Scan INSN and eliminate all eliminable registers in it.
3213 If REPLACE is nonzero, do the replacement destructively. Also
3214 delete the insn as dead it if it is setting an eliminable register.
3216 If REPLACE is zero, do all our allocations in reload_obstack.
3218 If no eliminations were done and this insn doesn't require any elimination
3219 processing (these are not identical conditions: it might be updating sp,
3220 but not referencing fp; this needs to be seen during reload_as_needed so
3221 that the offset between fp and sp can be taken into consideration), zero
3222 is returned. Otherwise, 1 is returned. */
3225 eliminate_regs_in_insn (rtx_insn
*insn
, int replace
)
3227 int icode
= recog_memoized (insn
);
3228 rtx old_body
= PATTERN (insn
);
3229 int insn_is_asm
= asm_noperands (old_body
) >= 0;
3230 rtx old_set
= single_set (insn
);
3234 rtx substed_operand
[MAX_RECOG_OPERANDS
];
3235 rtx orig_operand
[MAX_RECOG_OPERANDS
];
3236 struct elim_table
*ep
;
3237 rtx plus_src
, plus_cst_src
;
3239 if (! insn_is_asm
&& icode
< 0)
3241 gcc_assert (DEBUG_INSN_P (insn
)
3242 || GET_CODE (PATTERN (insn
)) == USE
3243 || GET_CODE (PATTERN (insn
)) == CLOBBER
3244 || GET_CODE (PATTERN (insn
)) == ASM_INPUT
);
3245 if (DEBUG_INSN_P (insn
))
3246 INSN_VAR_LOCATION_LOC (insn
)
3247 = eliminate_regs (INSN_VAR_LOCATION_LOC (insn
), VOIDmode
, insn
);
3251 if (old_set
!= 0 && REG_P (SET_DEST (old_set
))
3252 && REGNO (SET_DEST (old_set
)) < FIRST_PSEUDO_REGISTER
)
3254 /* Check for setting an eliminable register. */
3255 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3256 if (ep
->from_rtx
== SET_DEST (old_set
) && ep
->can_eliminate
)
3258 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
3259 /* If this is setting the frame pointer register to the
3260 hardware frame pointer register and this is an elimination
3261 that will be done (tested above), this insn is really
3262 adjusting the frame pointer downward to compensate for
3263 the adjustment done before a nonlocal goto. */
3264 if (ep
->from
== FRAME_POINTER_REGNUM
3265 && ep
->to
== HARD_FRAME_POINTER_REGNUM
)
3267 rtx base
= SET_SRC (old_set
);
3268 rtx_insn
*base_insn
= insn
;
3269 HOST_WIDE_INT offset
= 0;
3271 while (base
!= ep
->to_rtx
)
3273 rtx_insn
*prev_insn
;
3276 if (GET_CODE (base
) == PLUS
3277 && CONST_INT_P (XEXP (base
, 1)))
3279 offset
+= INTVAL (XEXP (base
, 1));
3280 base
= XEXP (base
, 0);
3282 else if ((prev_insn
= prev_nonnote_insn (base_insn
)) != 0
3283 && (prev_set
= single_set (prev_insn
)) != 0
3284 && rtx_equal_p (SET_DEST (prev_set
), base
))
3286 base
= SET_SRC (prev_set
);
3287 base_insn
= prev_insn
;
3293 if (base
== ep
->to_rtx
)
3295 rtx src
= plus_constant (Pmode
, ep
->to_rtx
,
3296 offset
- ep
->offset
);
3298 new_body
= old_body
;
3301 new_body
= copy_insn (old_body
);
3302 if (REG_NOTES (insn
))
3303 REG_NOTES (insn
) = copy_insn_1 (REG_NOTES (insn
));
3305 PATTERN (insn
) = new_body
;
3306 old_set
= single_set (insn
);
3308 /* First see if this insn remains valid when we
3309 make the change. If not, keep the INSN_CODE
3310 the same and let reload fit it up. */
3311 validate_change (insn
, &SET_SRC (old_set
), src
, 1);
3312 validate_change (insn
, &SET_DEST (old_set
),
3314 if (! apply_change_group ())
3316 SET_SRC (old_set
) = src
;
3317 SET_DEST (old_set
) = ep
->to_rtx
;
3326 /* In this case this insn isn't serving a useful purpose. We
3327 will delete it in reload_as_needed once we know that this
3328 elimination is, in fact, being done.
3330 If REPLACE isn't set, we can't delete this insn, but needn't
3331 process it since it won't be used unless something changes. */
3334 delete_dead_insn (insn
);
3342 /* We allow one special case which happens to work on all machines we
3343 currently support: a single set with the source or a REG_EQUAL
3344 note being a PLUS of an eliminable register and a constant. */
3345 plus_src
= plus_cst_src
= 0;
3346 if (old_set
&& REG_P (SET_DEST (old_set
)))
3348 if (GET_CODE (SET_SRC (old_set
)) == PLUS
)
3349 plus_src
= SET_SRC (old_set
);
3350 /* First see if the source is of the form (plus (...) CST). */
3352 && CONST_INT_P (XEXP (plus_src
, 1)))
3353 plus_cst_src
= plus_src
;
3354 else if (REG_P (SET_SRC (old_set
))
3357 /* Otherwise, see if we have a REG_EQUAL note of the form
3358 (plus (...) CST). */
3360 for (links
= REG_NOTES (insn
); links
; links
= XEXP (links
, 1))
3362 if ((REG_NOTE_KIND (links
) == REG_EQUAL
3363 || REG_NOTE_KIND (links
) == REG_EQUIV
)
3364 && GET_CODE (XEXP (links
, 0)) == PLUS
3365 && CONST_INT_P (XEXP (XEXP (links
, 0), 1)))
3367 plus_cst_src
= XEXP (links
, 0);
3373 /* Check that the first operand of the PLUS is a hard reg or
3374 the lowpart subreg of one. */
3377 rtx reg
= XEXP (plus_cst_src
, 0);
3378 if (GET_CODE (reg
) == SUBREG
&& subreg_lowpart_p (reg
))
3379 reg
= SUBREG_REG (reg
);
3381 if (!REG_P (reg
) || REGNO (reg
) >= FIRST_PSEUDO_REGISTER
)
3387 rtx reg
= XEXP (plus_cst_src
, 0);
3388 HOST_WIDE_INT offset
= INTVAL (XEXP (plus_cst_src
, 1));
3390 if (GET_CODE (reg
) == SUBREG
)
3391 reg
= SUBREG_REG (reg
);
3393 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3394 if (ep
->from_rtx
== reg
&& ep
->can_eliminate
)
3396 rtx to_rtx
= ep
->to_rtx
;
3397 offset
+= ep
->offset
;
3398 offset
= trunc_int_for_mode (offset
, GET_MODE (plus_cst_src
));
3400 if (GET_CODE (XEXP (plus_cst_src
, 0)) == SUBREG
)
3401 to_rtx
= gen_lowpart (GET_MODE (XEXP (plus_cst_src
, 0)),
3403 /* If we have a nonzero offset, and the source is already
3404 a simple REG, the following transformation would
3405 increase the cost of the insn by replacing a simple REG
3406 with (plus (reg sp) CST). So try only when we already
3407 had a PLUS before. */
3408 if (offset
== 0 || plus_src
)
3410 rtx new_src
= plus_constant (GET_MODE (to_rtx
),
3413 new_body
= old_body
;
3416 new_body
= copy_insn (old_body
);
3417 if (REG_NOTES (insn
))
3418 REG_NOTES (insn
) = copy_insn_1 (REG_NOTES (insn
));
3420 PATTERN (insn
) = new_body
;
3421 old_set
= single_set (insn
);
3423 /* First see if this insn remains valid when we make the
3424 change. If not, try to replace the whole pattern with
3425 a simple set (this may help if the original insn was a
3426 PARALLEL that was only recognized as single_set due to
3427 REG_UNUSED notes). If this isn't valid either, keep
3428 the INSN_CODE the same and let reload fix it up. */
3429 if (!validate_change (insn
, &SET_SRC (old_set
), new_src
, 0))
3431 rtx new_pat
= gen_rtx_SET (VOIDmode
,
3432 SET_DEST (old_set
), new_src
);
3434 if (!validate_change (insn
, &PATTERN (insn
), new_pat
, 0))
3435 SET_SRC (old_set
) = new_src
;
3442 /* This can't have an effect on elimination offsets, so skip right
3448 /* Determine the effects of this insn on elimination offsets. */
3449 elimination_effects (old_body
, VOIDmode
);
3451 /* Eliminate all eliminable registers occurring in operands that
3452 can be handled by reload. */
3453 extract_insn (insn
);
3454 for (i
= 0; i
< recog_data
.n_operands
; i
++)
3456 orig_operand
[i
] = recog_data
.operand
[i
];
3457 substed_operand
[i
] = recog_data
.operand
[i
];
3459 /* For an asm statement, every operand is eliminable. */
3460 if (insn_is_asm
|| insn_data
[icode
].operand
[i
].eliminable
)
3462 bool is_set_src
, in_plus
;
3464 /* Check for setting a register that we know about. */
3465 if (recog_data
.operand_type
[i
] != OP_IN
3466 && REG_P (orig_operand
[i
]))
3468 /* If we are assigning to a register that can be eliminated, it
3469 must be as part of a PARALLEL, since the code above handles
3470 single SETs. We must indicate that we can no longer
3471 eliminate this reg. */
3472 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
3474 if (ep
->from_rtx
== orig_operand
[i
])
3475 ep
->can_eliminate
= 0;
3478 /* Companion to the above plus substitution, we can allow
3479 invariants as the source of a plain move. */
3482 && recog_data
.operand_loc
[i
] == &SET_SRC (old_set
))
3486 && (recog_data
.operand_loc
[i
] == &XEXP (plus_src
, 0)
3487 || recog_data
.operand_loc
[i
] == &XEXP (plus_src
, 1)))
3491 = eliminate_regs_1 (recog_data
.operand
[i
], VOIDmode
,
3492 replace
? insn
: NULL_RTX
,
3493 is_set_src
|| in_plus
, false);
3494 if (substed_operand
[i
] != orig_operand
[i
])
3496 /* Terminate the search in check_eliminable_occurrences at
3498 *recog_data
.operand_loc
[i
] = 0;
3500 /* If an output operand changed from a REG to a MEM and INSN is an
3501 insn, write a CLOBBER insn. */
3502 if (recog_data
.operand_type
[i
] != OP_IN
3503 && REG_P (orig_operand
[i
])
3504 && MEM_P (substed_operand
[i
])
3506 emit_insn_after (gen_clobber (orig_operand
[i
]), insn
);
3510 for (i
= 0; i
< recog_data
.n_dups
; i
++)
3511 *recog_data
.dup_loc
[i
]
3512 = *recog_data
.operand_loc
[(int) recog_data
.dup_num
[i
]];
3514 /* If any eliminable remain, they aren't eliminable anymore. */
3515 check_eliminable_occurrences (old_body
);
3517 /* Substitute the operands; the new values are in the substed_operand
3519 for (i
= 0; i
< recog_data
.n_operands
; i
++)
3520 *recog_data
.operand_loc
[i
] = substed_operand
[i
];
3521 for (i
= 0; i
< recog_data
.n_dups
; i
++)
3522 *recog_data
.dup_loc
[i
] = substed_operand
[(int) recog_data
.dup_num
[i
]];
3524 /* If we are replacing a body that was a (set X (plus Y Z)), try to
3525 re-recognize the insn. We do this in case we had a simple addition
3526 but now can do this as a load-address. This saves an insn in this
3528 If re-recognition fails, the old insn code number will still be used,
3529 and some register operands may have changed into PLUS expressions.
3530 These will be handled by find_reloads by loading them into a register
3535 /* If we aren't replacing things permanently and we changed something,
3536 make another copy to ensure that all the RTL is new. Otherwise
3537 things can go wrong if find_reload swaps commutative operands
3538 and one is inside RTL that has been copied while the other is not. */
3539 new_body
= old_body
;
3542 new_body
= copy_insn (old_body
);
3543 if (REG_NOTES (insn
))
3544 REG_NOTES (insn
) = copy_insn_1 (REG_NOTES (insn
));
3546 PATTERN (insn
) = new_body
;
3548 /* If we had a move insn but now we don't, rerecognize it. This will
3549 cause spurious re-recognition if the old move had a PARALLEL since
3550 the new one still will, but we can't call single_set without
3551 having put NEW_BODY into the insn and the re-recognition won't
3552 hurt in this rare case. */
3553 /* ??? Why this huge if statement - why don't we just rerecognize the
3557 && ((REG_P (SET_SRC (old_set
))
3558 && (GET_CODE (new_body
) != SET
3559 || !REG_P (SET_SRC (new_body
))))
3560 /* If this was a load from or store to memory, compare
3561 the MEM in recog_data.operand to the one in the insn.
3562 If they are not equal, then rerecognize the insn. */
3564 && ((MEM_P (SET_SRC (old_set
))
3565 && SET_SRC (old_set
) != recog_data
.operand
[1])
3566 || (MEM_P (SET_DEST (old_set
))
3567 && SET_DEST (old_set
) != recog_data
.operand
[0])))
3568 /* If this was an add insn before, rerecognize. */
3569 || GET_CODE (SET_SRC (old_set
)) == PLUS
))
3571 int new_icode
= recog (PATTERN (insn
), insn
, 0);
3573 INSN_CODE (insn
) = new_icode
;
3577 /* Restore the old body. If there were any changes to it, we made a copy
3578 of it while the changes were still in place, so we'll correctly return
3579 a modified insn below. */
3582 /* Restore the old body. */
3583 for (i
= 0; i
< recog_data
.n_operands
; i
++)
3584 /* Restoring a top-level match_parallel would clobber the new_body
3585 we installed in the insn. */
3586 if (recog_data
.operand_loc
[i
] != &PATTERN (insn
))
3587 *recog_data
.operand_loc
[i
] = orig_operand
[i
];
3588 for (i
= 0; i
< recog_data
.n_dups
; i
++)
3589 *recog_data
.dup_loc
[i
] = orig_operand
[(int) recog_data
.dup_num
[i
]];
3592 /* Update all elimination pairs to reflect the status after the current
3593 insn. The changes we make were determined by the earlier call to
3594 elimination_effects.
3596 We also detect cases where register elimination cannot be done,
3597 namely, if a register would be both changed and referenced outside a MEM
3598 in the resulting insn since such an insn is often undefined and, even if
3599 not, we cannot know what meaning will be given to it. Note that it is
3600 valid to have a register used in an address in an insn that changes it
3601 (presumably with a pre- or post-increment or decrement).
3603 If anything changes, return nonzero. */
3605 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3607 if (ep
->previous_offset
!= ep
->offset
&& ep
->ref_outside_mem
)
3608 ep
->can_eliminate
= 0;
3610 ep
->ref_outside_mem
= 0;
3612 if (ep
->previous_offset
!= ep
->offset
)
3617 /* If we changed something, perform elimination in REG_NOTES. This is
3618 needed even when REPLACE is zero because a REG_DEAD note might refer
3619 to a register that we eliminate and could cause a different number
3620 of spill registers to be needed in the final reload pass than in
3622 if (val
&& REG_NOTES (insn
) != 0)
3624 = eliminate_regs_1 (REG_NOTES (insn
), VOIDmode
, REG_NOTES (insn
), true,
3630 /* Like eliminate_regs_in_insn, but only estimate costs for the use of the
3631 register allocator. INSN is the instruction we need to examine, we perform
3632 eliminations in its operands and record cases where eliminating a reg with
3633 an invariant equivalence would add extra cost. */
3636 elimination_costs_in_insn (rtx_insn
*insn
)
3638 int icode
= recog_memoized (insn
);
3639 rtx old_body
= PATTERN (insn
);
3640 int insn_is_asm
= asm_noperands (old_body
) >= 0;
3641 rtx old_set
= single_set (insn
);
3643 rtx orig_operand
[MAX_RECOG_OPERANDS
];
3644 rtx orig_dup
[MAX_RECOG_OPERANDS
];
3645 struct elim_table
*ep
;
3646 rtx plus_src
, plus_cst_src
;
3649 if (! insn_is_asm
&& icode
< 0)
3651 gcc_assert (DEBUG_INSN_P (insn
)
3652 || GET_CODE (PATTERN (insn
)) == USE
3653 || GET_CODE (PATTERN (insn
)) == CLOBBER
3654 || GET_CODE (PATTERN (insn
)) == ASM_INPUT
);
3658 if (old_set
!= 0 && REG_P (SET_DEST (old_set
))
3659 && REGNO (SET_DEST (old_set
)) < FIRST_PSEUDO_REGISTER
)
3661 /* Check for setting an eliminable register. */
3662 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3663 if (ep
->from_rtx
== SET_DEST (old_set
) && ep
->can_eliminate
)
3667 /* We allow one special case which happens to work on all machines we
3668 currently support: a single set with the source or a REG_EQUAL
3669 note being a PLUS of an eliminable register and a constant. */
3670 plus_src
= plus_cst_src
= 0;
3672 if (old_set
&& REG_P (SET_DEST (old_set
)))
3675 if (GET_CODE (SET_SRC (old_set
)) == PLUS
)
3676 plus_src
= SET_SRC (old_set
);
3677 /* First see if the source is of the form (plus (...) CST). */
3679 && CONST_INT_P (XEXP (plus_src
, 1)))
3680 plus_cst_src
= plus_src
;
3681 else if (REG_P (SET_SRC (old_set
))
3684 /* Otherwise, see if we have a REG_EQUAL note of the form
3685 (plus (...) CST). */
3687 for (links
= REG_NOTES (insn
); links
; links
= XEXP (links
, 1))
3689 if ((REG_NOTE_KIND (links
) == REG_EQUAL
3690 || REG_NOTE_KIND (links
) == REG_EQUIV
)
3691 && GET_CODE (XEXP (links
, 0)) == PLUS
3692 && CONST_INT_P (XEXP (XEXP (links
, 0), 1)))
3694 plus_cst_src
= XEXP (links
, 0);
3701 /* Determine the effects of this insn on elimination offsets. */
3702 elimination_effects (old_body
, VOIDmode
);
3704 /* Eliminate all eliminable registers occurring in operands that
3705 can be handled by reload. */
3706 extract_insn (insn
);
3707 for (i
= 0; i
< recog_data
.n_dups
; i
++)
3708 orig_dup
[i
] = *recog_data
.dup_loc
[i
];
3710 for (i
= 0; i
< recog_data
.n_operands
; i
++)
3712 orig_operand
[i
] = recog_data
.operand
[i
];
3714 /* For an asm statement, every operand is eliminable. */
3715 if (insn_is_asm
|| insn_data
[icode
].operand
[i
].eliminable
)
3717 bool is_set_src
, in_plus
;
3719 /* Check for setting a register that we know about. */
3720 if (recog_data
.operand_type
[i
] != OP_IN
3721 && REG_P (orig_operand
[i
]))
3723 /* If we are assigning to a register that can be eliminated, it
3724 must be as part of a PARALLEL, since the code above handles
3725 single SETs. We must indicate that we can no longer
3726 eliminate this reg. */
3727 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
3729 if (ep
->from_rtx
== orig_operand
[i
])
3730 ep
->can_eliminate
= 0;
3733 /* Companion to the above plus substitution, we can allow
3734 invariants as the source of a plain move. */
3736 if (old_set
&& recog_data
.operand_loc
[i
] == &SET_SRC (old_set
))
3738 if (is_set_src
&& !sets_reg_p
)
3739 note_reg_elim_costly (SET_SRC (old_set
), insn
);
3741 if (plus_src
&& sets_reg_p
3742 && (recog_data
.operand_loc
[i
] == &XEXP (plus_src
, 0)
3743 || recog_data
.operand_loc
[i
] == &XEXP (plus_src
, 1)))
3746 eliminate_regs_1 (recog_data
.operand
[i
], VOIDmode
,
3748 is_set_src
|| in_plus
, true);
3749 /* Terminate the search in check_eliminable_occurrences at
3751 *recog_data
.operand_loc
[i
] = 0;
3755 for (i
= 0; i
< recog_data
.n_dups
; i
++)
3756 *recog_data
.dup_loc
[i
]
3757 = *recog_data
.operand_loc
[(int) recog_data
.dup_num
[i
]];
3759 /* If any eliminable remain, they aren't eliminable anymore. */
3760 check_eliminable_occurrences (old_body
);
3762 /* Restore the old body. */
3763 for (i
= 0; i
< recog_data
.n_operands
; i
++)
3764 *recog_data
.operand_loc
[i
] = orig_operand
[i
];
3765 for (i
= 0; i
< recog_data
.n_dups
; i
++)
3766 *recog_data
.dup_loc
[i
] = orig_dup
[i
];
3768 /* Update all elimination pairs to reflect the status after the current
3769 insn. The changes we make were determined by the earlier call to
3770 elimination_effects. */
3772 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3774 if (ep
->previous_offset
!= ep
->offset
&& ep
->ref_outside_mem
)
3775 ep
->can_eliminate
= 0;
3777 ep
->ref_outside_mem
= 0;
3783 /* Loop through all elimination pairs.
3784 Recalculate the number not at initial offset.
3786 Compute the maximum offset (minimum offset if the stack does not
3787 grow downward) for each elimination pair. */
3790 update_eliminable_offsets (void)
3792 struct elim_table
*ep
;
3794 num_not_at_initial_offset
= 0;
3795 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3797 ep
->previous_offset
= ep
->offset
;
3798 if (ep
->can_eliminate
&& ep
->offset
!= ep
->initial_offset
)
3799 num_not_at_initial_offset
++;
3803 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3804 replacement we currently believe is valid, mark it as not eliminable if X
3805 modifies DEST in any way other than by adding a constant integer to it.
3807 If DEST is the frame pointer, we do nothing because we assume that
3808 all assignments to the hard frame pointer are nonlocal gotos and are being
3809 done at a time when they are valid and do not disturb anything else.
3810 Some machines want to eliminate a fake argument pointer with either the
3811 frame or stack pointer. Assignments to the hard frame pointer must not
3812 prevent this elimination.
3814 Called via note_stores from reload before starting its passes to scan
3815 the insns of the function. */
3818 mark_not_eliminable (rtx dest
, const_rtx x
, void *data ATTRIBUTE_UNUSED
)
3822 /* A SUBREG of a hard register here is just changing its mode. We should
3823 not see a SUBREG of an eliminable hard register, but check just in
3825 if (GET_CODE (dest
) == SUBREG
)
3826 dest
= SUBREG_REG (dest
);
3828 if (dest
== hard_frame_pointer_rtx
)
3831 for (i
= 0; i
< NUM_ELIMINABLE_REGS
; i
++)
3832 if (reg_eliminate
[i
].can_eliminate
&& dest
== reg_eliminate
[i
].to_rtx
3833 && (GET_CODE (x
) != SET
3834 || GET_CODE (SET_SRC (x
)) != PLUS
3835 || XEXP (SET_SRC (x
), 0) != dest
3836 || !CONST_INT_P (XEXP (SET_SRC (x
), 1))))
3838 reg_eliminate
[i
].can_eliminate_previous
3839 = reg_eliminate
[i
].can_eliminate
= 0;
3844 /* Verify that the initial elimination offsets did not change since the
3845 last call to set_initial_elim_offsets. This is used to catch cases
3846 where something illegal happened during reload_as_needed that could
3847 cause incorrect code to be generated if we did not check for it. */
3850 verify_initial_elim_offsets (void)
3854 if (!num_eliminable
)
3857 #ifdef ELIMINABLE_REGS
3859 struct elim_table
*ep
;
3861 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3863 INITIAL_ELIMINATION_OFFSET (ep
->from
, ep
->to
, t
);
3864 if (t
!= ep
->initial_offset
)
3869 INITIAL_FRAME_POINTER_OFFSET (t
);
3870 if (t
!= reg_eliminate
[0].initial_offset
)
3877 /* Reset all offsets on eliminable registers to their initial values. */
3880 set_initial_elim_offsets (void)
3882 struct elim_table
*ep
= reg_eliminate
;
3884 #ifdef ELIMINABLE_REGS
3885 for (; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3887 INITIAL_ELIMINATION_OFFSET (ep
->from
, ep
->to
, ep
->initial_offset
);
3888 ep
->previous_offset
= ep
->offset
= ep
->initial_offset
;
3891 INITIAL_FRAME_POINTER_OFFSET (ep
->initial_offset
);
3892 ep
->previous_offset
= ep
->offset
= ep
->initial_offset
;
3895 num_not_at_initial_offset
= 0;
3898 /* Subroutine of set_initial_label_offsets called via for_each_eh_label. */
3901 set_initial_eh_label_offset (rtx label
)
3903 set_label_offsets (label
, NULL
, 1);
3906 /* Initialize the known label offsets.
3907 Set a known offset for each forced label to be at the initial offset
3908 of each elimination. We do this because we assume that all
3909 computed jumps occur from a location where each elimination is
3910 at its initial offset.
3911 For all other labels, show that we don't know the offsets. */
3914 set_initial_label_offsets (void)
3916 memset (offsets_known_at
, 0, num_labels
);
3918 for (rtx_insn_list
*x
= forced_labels
; x
; x
= x
->next ())
3920 set_label_offsets (x
->insn (), NULL
, 1);
3922 for (rtx_insn_list
*x
= nonlocal_goto_handler_labels
; x
; x
= x
->next ())
3924 set_label_offsets (x
->insn (), NULL
, 1);
3926 for_each_eh_label (set_initial_eh_label_offset
);
3929 /* Set all elimination offsets to the known values for the code label given
3933 set_offsets_for_label (rtx_insn
*insn
)
3936 int label_nr
= CODE_LABEL_NUMBER (insn
);
3937 struct elim_table
*ep
;
3939 num_not_at_initial_offset
= 0;
3940 for (i
= 0, ep
= reg_eliminate
; i
< NUM_ELIMINABLE_REGS
; ep
++, i
++)
3942 ep
->offset
= ep
->previous_offset
3943 = offsets_at
[label_nr
- first_label_num
][i
];
3944 if (ep
->can_eliminate
&& ep
->offset
!= ep
->initial_offset
)
3945 num_not_at_initial_offset
++;
3949 /* See if anything that happened changes which eliminations are valid.
3950 For example, on the SPARC, whether or not the frame pointer can
3951 be eliminated can depend on what registers have been used. We need
3952 not check some conditions again (such as flag_omit_frame_pointer)
3953 since they can't have changed. */
3956 update_eliminables (HARD_REG_SET
*pset
)
3958 int previous_frame_pointer_needed
= frame_pointer_needed
;
3959 struct elim_table
*ep
;
3961 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3962 if ((ep
->from
== HARD_FRAME_POINTER_REGNUM
3963 && targetm
.frame_pointer_required ())
3964 #ifdef ELIMINABLE_REGS
3965 || ! targetm
.can_eliminate (ep
->from
, ep
->to
)
3968 ep
->can_eliminate
= 0;
3970 /* Look for the case where we have discovered that we can't replace
3971 register A with register B and that means that we will now be
3972 trying to replace register A with register C. This means we can
3973 no longer replace register C with register B and we need to disable
3974 such an elimination, if it exists. This occurs often with A == ap,
3975 B == sp, and C == fp. */
3977 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3979 struct elim_table
*op
;
3982 if (! ep
->can_eliminate
&& ep
->can_eliminate_previous
)
3984 /* Find the current elimination for ep->from, if there is a
3986 for (op
= reg_eliminate
;
3987 op
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; op
++)
3988 if (op
->from
== ep
->from
&& op
->can_eliminate
)
3994 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
3996 for (op
= reg_eliminate
;
3997 op
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; op
++)
3998 if (op
->from
== new_to
&& op
->to
== ep
->to
)
3999 op
->can_eliminate
= 0;
4003 /* See if any registers that we thought we could eliminate the previous
4004 time are no longer eliminable. If so, something has changed and we
4005 must spill the register. Also, recompute the number of eliminable
4006 registers and see if the frame pointer is needed; it is if there is
4007 no elimination of the frame pointer that we can perform. */
4009 frame_pointer_needed
= 1;
4010 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
4012 if (ep
->can_eliminate
4013 && ep
->from
== FRAME_POINTER_REGNUM
4014 && ep
->to
!= HARD_FRAME_POINTER_REGNUM
4015 && (! SUPPORTS_STACK_ALIGNMENT
4016 || ! crtl
->stack_realign_needed
))
4017 frame_pointer_needed
= 0;
4019 if (! ep
->can_eliminate
&& ep
->can_eliminate_previous
)
4021 ep
->can_eliminate_previous
= 0;
4022 SET_HARD_REG_BIT (*pset
, ep
->from
);
4027 /* If we didn't need a frame pointer last time, but we do now, spill
4028 the hard frame pointer. */
4029 if (frame_pointer_needed
&& ! previous_frame_pointer_needed
)
4030 SET_HARD_REG_BIT (*pset
, HARD_FRAME_POINTER_REGNUM
);
4033 /* Call update_eliminables an spill any registers we can't eliminate anymore.
4034 Return true iff a register was spilled. */
4037 update_eliminables_and_spill (void)
4040 bool did_spill
= false;
4041 HARD_REG_SET to_spill
;
4042 CLEAR_HARD_REG_SET (to_spill
);
4043 update_eliminables (&to_spill
);
4044 AND_COMPL_HARD_REG_SET (used_spill_regs
, to_spill
);
4046 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
4047 if (TEST_HARD_REG_BIT (to_spill
, i
))
4049 spill_hard_reg (i
, 1);
4052 /* Regardless of the state of spills, if we previously had
4053 a register that we thought we could eliminate, but now can
4054 not eliminate, we must run another pass.
4056 Consider pseudos which have an entry in reg_equiv_* which
4057 reference an eliminable register. We must make another pass
4058 to update reg_equiv_* so that we do not substitute in the
4059 old value from when we thought the elimination could be
4065 /* Return true if X is used as the target register of an elimination. */
4068 elimination_target_reg_p (rtx x
)
4070 struct elim_table
*ep
;
4072 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
4073 if (ep
->to_rtx
== x
&& ep
->can_eliminate
)
4079 /* Initialize the table of registers to eliminate.
4080 Pre-condition: global flag frame_pointer_needed has been set before
4081 calling this function. */
4084 init_elim_table (void)
4086 struct elim_table
*ep
;
4087 #ifdef ELIMINABLE_REGS
4088 const struct elim_table_1
*ep1
;
4092 reg_eliminate
= XCNEWVEC (struct elim_table
, NUM_ELIMINABLE_REGS
);
4096 #ifdef ELIMINABLE_REGS
4097 for (ep
= reg_eliminate
, ep1
= reg_eliminate_1
;
4098 ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++, ep1
++)
4100 ep
->from
= ep1
->from
;
4102 ep
->can_eliminate
= ep
->can_eliminate_previous
4103 = (targetm
.can_eliminate (ep
->from
, ep
->to
)
4104 && ! (ep
->to
== STACK_POINTER_REGNUM
4105 && frame_pointer_needed
4106 && (! SUPPORTS_STACK_ALIGNMENT
4107 || ! stack_realign_fp
)));
4110 reg_eliminate
[0].from
= reg_eliminate_1
[0].from
;
4111 reg_eliminate
[0].to
= reg_eliminate_1
[0].to
;
4112 reg_eliminate
[0].can_eliminate
= reg_eliminate
[0].can_eliminate_previous
4113 = ! frame_pointer_needed
;
4116 /* Count the number of eliminable registers and build the FROM and TO
4117 REG rtx's. Note that code in gen_rtx_REG will cause, e.g.,
4118 gen_rtx_REG (Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
4119 We depend on this. */
4120 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
4122 num_eliminable
+= ep
->can_eliminate
;
4123 ep
->from_rtx
= gen_rtx_REG (Pmode
, ep
->from
);
4124 ep
->to_rtx
= gen_rtx_REG (Pmode
, ep
->to
);
4128 /* Find all the pseudo registers that didn't get hard regs
4129 but do have known equivalent constants or memory slots.
4130 These include parameters (known equivalent to parameter slots)
4131 and cse'd or loop-moved constant memory addresses.
4133 Record constant equivalents in reg_equiv_constant
4134 so they will be substituted by find_reloads.
4135 Record memory equivalents in reg_mem_equiv so they can
4136 be substituted eventually by altering the REG-rtx's. */
4139 init_eliminable_invariants (rtx_insn
*first
, bool do_subregs
)
4146 reg_max_ref_width
= XCNEWVEC (unsigned int, max_regno
);
4148 reg_max_ref_width
= NULL
;
4150 num_eliminable_invariants
= 0;
4152 first_label_num
= get_first_label_num ();
4153 num_labels
= max_label_num () - first_label_num
;
4155 /* Allocate the tables used to store offset information at labels. */
4156 offsets_known_at
= XNEWVEC (char, num_labels
);
4157 offsets_at
= (HOST_WIDE_INT (*)[NUM_ELIMINABLE_REGS
]) xmalloc (num_labels
* NUM_ELIMINABLE_REGS
* sizeof (HOST_WIDE_INT
));
4159 /* Look for REG_EQUIV notes; record what each pseudo is equivalent
4160 to. If DO_SUBREGS is true, also find all paradoxical subregs and
4161 find largest such for each pseudo. FIRST is the head of the insn
4164 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
4166 rtx set
= single_set (insn
);
4168 /* We may introduce USEs that we want to remove at the end, so
4169 we'll mark them with QImode. Make sure there are no
4170 previously-marked insns left by say regmove. */
4171 if (INSN_P (insn
) && GET_CODE (PATTERN (insn
)) == USE
4172 && GET_MODE (insn
) != VOIDmode
)
4173 PUT_MODE (insn
, VOIDmode
);
4175 if (do_subregs
&& NONDEBUG_INSN_P (insn
))
4176 scan_paradoxical_subregs (PATTERN (insn
));
4178 if (set
!= 0 && REG_P (SET_DEST (set
)))
4180 rtx note
= find_reg_note (insn
, REG_EQUIV
, NULL_RTX
);
4186 i
= REGNO (SET_DEST (set
));
4189 if (i
<= LAST_VIRTUAL_REGISTER
)
4192 /* If flag_pic and we have constant, verify it's legitimate. */
4194 || !flag_pic
|| LEGITIMATE_PIC_OPERAND_P (x
))
4196 /* It can happen that a REG_EQUIV note contains a MEM
4197 that is not a legitimate memory operand. As later
4198 stages of reload assume that all addresses found
4199 in the reg_equiv_* arrays were originally legitimate,
4200 we ignore such REG_EQUIV notes. */
4201 if (memory_operand (x
, VOIDmode
))
4203 /* Always unshare the equivalence, so we can
4204 substitute into this insn without touching the
4206 reg_equiv_memory_loc (i
) = copy_rtx (x
);
4208 else if (function_invariant_p (x
))
4210 enum machine_mode mode
;
4212 mode
= GET_MODE (SET_DEST (set
));
4213 if (GET_CODE (x
) == PLUS
)
4215 /* This is PLUS of frame pointer and a constant,
4216 and might be shared. Unshare it. */
4217 reg_equiv_invariant (i
) = copy_rtx (x
);
4218 num_eliminable_invariants
++;
4220 else if (x
== frame_pointer_rtx
|| x
== arg_pointer_rtx
)
4222 reg_equiv_invariant (i
) = x
;
4223 num_eliminable_invariants
++;
4225 else if (targetm
.legitimate_constant_p (mode
, x
))
4226 reg_equiv_constant (i
) = x
;
4229 reg_equiv_memory_loc (i
) = force_const_mem (mode
, x
);
4230 if (! reg_equiv_memory_loc (i
))
4231 reg_equiv_init (i
) = NULL_RTX
;
4236 reg_equiv_init (i
) = NULL_RTX
;
4241 reg_equiv_init (i
) = NULL_RTX
;
4246 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
4247 if (reg_equiv_init (i
))
4249 fprintf (dump_file
, "init_insns for %u: ", i
);
4250 print_inline_rtx (dump_file
, reg_equiv_init (i
), 20);
4251 fprintf (dump_file
, "\n");
4255 /* Indicate that we no longer have known memory locations or constants.
4256 Free all data involved in tracking these. */
4259 free_reg_equiv (void)
4263 free (offsets_known_at
);
4266 offsets_known_at
= 0;
4268 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
4269 if (reg_equiv_alt_mem_list (i
))
4270 free_EXPR_LIST_list (®_equiv_alt_mem_list (i
));
4271 vec_free (reg_equivs
);
4274 /* Kick all pseudos out of hard register REGNO.
4276 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
4277 because we found we can't eliminate some register. In the case, no pseudos
4278 are allowed to be in the register, even if they are only in a block that
4279 doesn't require spill registers, unlike the case when we are spilling this
4280 hard reg to produce another spill register.
4282 Return nonzero if any pseudos needed to be kicked out. */
4285 spill_hard_reg (unsigned int regno
, int cant_eliminate
)
4291 SET_HARD_REG_BIT (bad_spill_regs_global
, regno
);
4292 df_set_regs_ever_live (regno
, true);
4295 /* Spill every pseudo reg that was allocated to this reg
4296 or to something that overlaps this reg. */
4298 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
4299 if (reg_renumber
[i
] >= 0
4300 && (unsigned int) reg_renumber
[i
] <= regno
4301 && end_hard_regno (PSEUDO_REGNO_MODE (i
), reg_renumber
[i
]) > regno
)
4302 SET_REGNO_REG_SET (&spilled_pseudos
, i
);
4305 /* After find_reload_regs has been run for all insn that need reloads,
4306 and/or spill_hard_regs was called, this function is used to actually
4307 spill pseudo registers and try to reallocate them. It also sets up the
4308 spill_regs array for use by choose_reload_regs. */
4311 finish_spills (int global
)
4313 struct insn_chain
*chain
;
4314 int something_changed
= 0;
4316 reg_set_iterator rsi
;
4318 /* Build the spill_regs array for the function. */
4319 /* If there are some registers still to eliminate and one of the spill regs
4320 wasn't ever used before, additional stack space may have to be
4321 allocated to store this register. Thus, we may have changed the offset
4322 between the stack and frame pointers, so mark that something has changed.
4324 One might think that we need only set VAL to 1 if this is a call-used
4325 register. However, the set of registers that must be saved by the
4326 prologue is not identical to the call-used set. For example, the
4327 register used by the call insn for the return PC is a call-used register,
4328 but must be saved by the prologue. */
4331 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
4332 if (TEST_HARD_REG_BIT (used_spill_regs
, i
))
4334 spill_reg_order
[i
] = n_spills
;
4335 spill_regs
[n_spills
++] = i
;
4336 if (num_eliminable
&& ! df_regs_ever_live_p (i
))
4337 something_changed
= 1;
4338 df_set_regs_ever_live (i
, true);
4341 spill_reg_order
[i
] = -1;
4343 EXECUTE_IF_SET_IN_REG_SET (&spilled_pseudos
, FIRST_PSEUDO_REGISTER
, i
, rsi
)
4344 if (! ira_conflicts_p
|| reg_renumber
[i
] >= 0)
4346 /* Record the current hard register the pseudo is allocated to
4347 in pseudo_previous_regs so we avoid reallocating it to the
4348 same hard reg in a later pass. */
4349 gcc_assert (reg_renumber
[i
] >= 0);
4351 SET_HARD_REG_BIT (pseudo_previous_regs
[i
], reg_renumber
[i
]);
4352 /* Mark it as no longer having a hard register home. */
4353 reg_renumber
[i
] = -1;
4354 if (ira_conflicts_p
)
4355 /* Inform IRA about the change. */
4356 ira_mark_allocation_change (i
);
4357 /* We will need to scan everything again. */
4358 something_changed
= 1;
4361 /* Retry global register allocation if possible. */
4362 if (global
&& ira_conflicts_p
)
4366 memset (pseudo_forbidden_regs
, 0, max_regno
* sizeof (HARD_REG_SET
));
4367 /* For every insn that needs reloads, set the registers used as spill
4368 regs in pseudo_forbidden_regs for every pseudo live across the
4370 for (chain
= insns_need_reload
; chain
; chain
= chain
->next_need_reload
)
4372 EXECUTE_IF_SET_IN_REG_SET
4373 (&chain
->live_throughout
, FIRST_PSEUDO_REGISTER
, i
, rsi
)
4375 IOR_HARD_REG_SET (pseudo_forbidden_regs
[i
],
4376 chain
->used_spill_regs
);
4378 EXECUTE_IF_SET_IN_REG_SET
4379 (&chain
->dead_or_set
, FIRST_PSEUDO_REGISTER
, i
, rsi
)
4381 IOR_HARD_REG_SET (pseudo_forbidden_regs
[i
],
4382 chain
->used_spill_regs
);
4386 /* Retry allocating the pseudos spilled in IRA and the
4387 reload. For each reg, merge the various reg sets that
4388 indicate which hard regs can't be used, and call
4389 ira_reassign_pseudos. */
4390 for (n
= 0, i
= FIRST_PSEUDO_REGISTER
; i
< (unsigned) max_regno
; i
++)
4391 if (reg_old_renumber
[i
] != reg_renumber
[i
])
4393 if (reg_renumber
[i
] < 0)
4394 temp_pseudo_reg_arr
[n
++] = i
;
4396 CLEAR_REGNO_REG_SET (&spilled_pseudos
, i
);
4398 if (ira_reassign_pseudos (temp_pseudo_reg_arr
, n
,
4399 bad_spill_regs_global
,
4400 pseudo_forbidden_regs
, pseudo_previous_regs
,
4402 something_changed
= 1;
4404 /* Fix up the register information in the insn chain.
4405 This involves deleting those of the spilled pseudos which did not get
4406 a new hard register home from the live_{before,after} sets. */
4407 for (chain
= reload_insn_chain
; chain
; chain
= chain
->next
)
4409 HARD_REG_SET used_by_pseudos
;
4410 HARD_REG_SET used_by_pseudos2
;
4412 if (! ira_conflicts_p
)
4414 /* Don't do it for IRA because IRA and the reload still can
4415 assign hard registers to the spilled pseudos on next
4416 reload iterations. */
4417 AND_COMPL_REG_SET (&chain
->live_throughout
, &spilled_pseudos
);
4418 AND_COMPL_REG_SET (&chain
->dead_or_set
, &spilled_pseudos
);
4420 /* Mark any unallocated hard regs as available for spills. That
4421 makes inheritance work somewhat better. */
4422 if (chain
->need_reload
)
4424 REG_SET_TO_HARD_REG_SET (used_by_pseudos
, &chain
->live_throughout
);
4425 REG_SET_TO_HARD_REG_SET (used_by_pseudos2
, &chain
->dead_or_set
);
4426 IOR_HARD_REG_SET (used_by_pseudos
, used_by_pseudos2
);
4428 compute_use_by_pseudos (&used_by_pseudos
, &chain
->live_throughout
);
4429 compute_use_by_pseudos (&used_by_pseudos
, &chain
->dead_or_set
);
4430 /* Value of chain->used_spill_regs from previous iteration
4431 may be not included in the value calculated here because
4432 of possible removing caller-saves insns (see function
4433 delete_caller_save_insns. */
4434 COMPL_HARD_REG_SET (chain
->used_spill_regs
, used_by_pseudos
);
4435 AND_HARD_REG_SET (chain
->used_spill_regs
, used_spill_regs
);
4439 CLEAR_REG_SET (&changed_allocation_pseudos
);
4440 /* Let alter_reg modify the reg rtx's for the modified pseudos. */
4441 for (i
= FIRST_PSEUDO_REGISTER
; i
< (unsigned)max_regno
; i
++)
4443 int regno
= reg_renumber
[i
];
4444 if (reg_old_renumber
[i
] == regno
)
4447 SET_REGNO_REG_SET (&changed_allocation_pseudos
, i
);
4449 alter_reg (i
, reg_old_renumber
[i
], false);
4450 reg_old_renumber
[i
] = regno
;
4454 fprintf (dump_file
, " Register %d now on stack.\n\n", i
);
4456 fprintf (dump_file
, " Register %d now in %d.\n\n",
4457 i
, reg_renumber
[i
]);
4461 return something_changed
;
4464 /* Find all paradoxical subregs within X and update reg_max_ref_width. */
4467 scan_paradoxical_subregs (rtx x
)
4471 enum rtx_code code
= GET_CODE (x
);
4487 if (REG_P (SUBREG_REG (x
))
4488 && (GET_MODE_SIZE (GET_MODE (x
))
4489 > reg_max_ref_width
[REGNO (SUBREG_REG (x
))]))
4491 reg_max_ref_width
[REGNO (SUBREG_REG (x
))]
4492 = GET_MODE_SIZE (GET_MODE (x
));
4493 mark_home_live_1 (REGNO (SUBREG_REG (x
)), GET_MODE (x
));
4501 fmt
= GET_RTX_FORMAT (code
);
4502 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
4505 scan_paradoxical_subregs (XEXP (x
, i
));
4506 else if (fmt
[i
] == 'E')
4509 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
4510 scan_paradoxical_subregs (XVECEXP (x
, i
, j
));
4515 /* *OP_PTR and *OTHER_PTR are two operands to a conceptual reload.
4516 If *OP_PTR is a paradoxical subreg, try to remove that subreg
4517 and apply the corresponding narrowing subreg to *OTHER_PTR.
4518 Return true if the operands were changed, false otherwise. */
4521 strip_paradoxical_subreg (rtx
*op_ptr
, rtx
*other_ptr
)
4523 rtx op
, inner
, other
, tem
;
4526 if (!paradoxical_subreg_p (op
))
4528 inner
= SUBREG_REG (op
);
4531 tem
= gen_lowpart_common (GET_MODE (inner
), other
);
4535 /* If the lowpart operation turned a hard register into a subreg,
4536 rather than simplifying it to another hard register, then the
4537 mode change cannot be properly represented. For example, OTHER
4538 might be valid in its current mode, but not in the new one. */
4539 if (GET_CODE (tem
) == SUBREG
4541 && HARD_REGISTER_P (other
))
4549 /* A subroutine of reload_as_needed. If INSN has a REG_EH_REGION note,
4550 examine all of the reload insns between PREV and NEXT exclusive, and
4551 annotate all that may trap. */
4554 fixup_eh_region_note (rtx_insn
*insn
, rtx_insn
*prev
, rtx_insn
*next
)
4556 rtx note
= find_reg_note (insn
, REG_EH_REGION
, NULL_RTX
);
4559 if (!insn_could_throw_p (insn
))
4560 remove_note (insn
, note
);
4561 copy_reg_eh_region_note_forward (note
, NEXT_INSN (prev
), next
);
4564 /* Reload pseudo-registers into hard regs around each insn as needed.
4565 Additional register load insns are output before the insn that needs it
4566 and perhaps store insns after insns that modify the reloaded pseudo reg.
4568 reg_last_reload_reg and reg_reloaded_contents keep track of
4569 which registers are already available in reload registers.
4570 We update these for the reloads that we perform,
4571 as the insns are scanned. */
4574 reload_as_needed (int live_known
)
4576 struct insn_chain
*chain
;
4577 #if defined (AUTO_INC_DEC)
4582 memset (spill_reg_rtx
, 0, sizeof spill_reg_rtx
);
4583 memset (spill_reg_store
, 0, sizeof spill_reg_store
);
4584 reg_last_reload_reg
= XCNEWVEC (rtx
, max_regno
);
4585 INIT_REG_SET (®_has_output_reload
);
4586 CLEAR_HARD_REG_SET (reg_reloaded_valid
);
4587 CLEAR_HARD_REG_SET (reg_reloaded_call_part_clobbered
);
4589 set_initial_elim_offsets ();
4591 /* Generate a marker insn that we will move around. */
4592 marker
= emit_note (NOTE_INSN_DELETED
);
4593 unlink_insn_chain (marker
, marker
);
4595 for (chain
= reload_insn_chain
; chain
; chain
= chain
->next
)
4598 rtx_insn
*insn
= chain
->insn
;
4599 rtx_insn
*old_next
= NEXT_INSN (insn
);
4601 rtx_insn
*old_prev
= PREV_INSN (insn
);
4604 if (will_delete_init_insn_p (insn
))
4607 /* If we pass a label, copy the offsets from the label information
4608 into the current offsets of each elimination. */
4610 set_offsets_for_label (insn
);
4612 else if (INSN_P (insn
))
4614 regset_head regs_to_forget
;
4615 INIT_REG_SET (®s_to_forget
);
4616 note_stores (PATTERN (insn
), forget_old_reloads_1
, ®s_to_forget
);
4618 /* If this is a USE and CLOBBER of a MEM, ensure that any
4619 references to eliminable registers have been removed. */
4621 if ((GET_CODE (PATTERN (insn
)) == USE
4622 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
4623 && MEM_P (XEXP (PATTERN (insn
), 0)))
4624 XEXP (XEXP (PATTERN (insn
), 0), 0)
4625 = eliminate_regs (XEXP (XEXP (PATTERN (insn
), 0), 0),
4626 GET_MODE (XEXP (PATTERN (insn
), 0)),
4629 /* If we need to do register elimination processing, do so.
4630 This might delete the insn, in which case we are done. */
4631 if ((num_eliminable
|| num_eliminable_invariants
) && chain
->need_elim
)
4633 eliminate_regs_in_insn (insn
, 1);
4636 update_eliminable_offsets ();
4637 CLEAR_REG_SET (®s_to_forget
);
4642 /* If need_elim is nonzero but need_reload is zero, one might think
4643 that we could simply set n_reloads to 0. However, find_reloads
4644 could have done some manipulation of the insn (such as swapping
4645 commutative operands), and these manipulations are lost during
4646 the first pass for every insn that needs register elimination.
4647 So the actions of find_reloads must be redone here. */
4649 if (! chain
->need_elim
&& ! chain
->need_reload
4650 && ! chain
->need_operand_change
)
4652 /* First find the pseudo regs that must be reloaded for this insn.
4653 This info is returned in the tables reload_... (see reload.h).
4654 Also modify the body of INSN by substituting RELOAD
4655 rtx's for those pseudo regs. */
4658 CLEAR_REG_SET (®_has_output_reload
);
4659 CLEAR_HARD_REG_SET (reg_is_output_reload
);
4661 find_reloads (insn
, 1, spill_indirect_levels
, live_known
,
4667 rtx_insn
*next
= NEXT_INSN (insn
);
4669 /* ??? PREV can get deleted by reload inheritance.
4670 Work around this by emitting a marker note. */
4671 prev
= PREV_INSN (insn
);
4672 reorder_insns_nobb (marker
, marker
, prev
);
4674 /* Now compute which reload regs to reload them into. Perhaps
4675 reusing reload regs from previous insns, or else output
4676 load insns to reload them. Maybe output store insns too.
4677 Record the choices of reload reg in reload_reg_rtx. */
4678 choose_reload_regs (chain
);
4680 /* Generate the insns to reload operands into or out of
4681 their reload regs. */
4682 emit_reload_insns (chain
);
4684 /* Substitute the chosen reload regs from reload_reg_rtx
4685 into the insn's body (or perhaps into the bodies of other
4686 load and store insn that we just made for reloading
4687 and that we moved the structure into). */
4688 subst_reloads (insn
);
4690 prev
= PREV_INSN (marker
);
4691 unlink_insn_chain (marker
, marker
);
4693 /* Adjust the exception region notes for loads and stores. */
4694 if (cfun
->can_throw_non_call_exceptions
&& !CALL_P (insn
))
4695 fixup_eh_region_note (insn
, prev
, next
);
4697 /* Adjust the location of REG_ARGS_SIZE. */
4698 rtx p
= find_reg_note (insn
, REG_ARGS_SIZE
, NULL_RTX
);
4701 remove_note (insn
, p
);
4702 fixup_args_size_notes (prev
, PREV_INSN (next
),
4703 INTVAL (XEXP (p
, 0)));
4706 /* If this was an ASM, make sure that all the reload insns
4707 we have generated are valid. If not, give an error
4709 if (asm_noperands (PATTERN (insn
)) >= 0)
4710 for (rtx_insn
*p
= NEXT_INSN (prev
);
4713 if (p
!= insn
&& INSN_P (p
)
4714 && GET_CODE (PATTERN (p
)) != USE
4715 && (recog_memoized (p
) < 0
4716 || (extract_insn (p
), ! constrain_operands (1))))
4718 error_for_asm (insn
,
4719 "%<asm%> operand requires "
4720 "impossible reload");
4725 if (num_eliminable
&& chain
->need_elim
)
4726 update_eliminable_offsets ();
4728 /* Any previously reloaded spilled pseudo reg, stored in this insn,
4729 is no longer validly lying around to save a future reload.
4730 Note that this does not detect pseudos that were reloaded
4731 for this insn in order to be stored in
4732 (obeying register constraints). That is correct; such reload
4733 registers ARE still valid. */
4734 forget_marked_reloads (®s_to_forget
);
4735 CLEAR_REG_SET (®s_to_forget
);
4737 /* There may have been CLOBBER insns placed after INSN. So scan
4738 between INSN and NEXT and use them to forget old reloads. */
4739 for (rtx_insn
*x
= NEXT_INSN (insn
); x
!= old_next
; x
= NEXT_INSN (x
))
4740 if (NONJUMP_INSN_P (x
) && GET_CODE (PATTERN (x
)) == CLOBBER
)
4741 note_stores (PATTERN (x
), forget_old_reloads_1
, NULL
);
4744 /* Likewise for regs altered by auto-increment in this insn.
4745 REG_INC notes have been changed by reloading:
4746 find_reloads_address_1 records substitutions for them,
4747 which have been performed by subst_reloads above. */
4748 for (i
= n_reloads
- 1; i
>= 0; i
--)
4750 rtx in_reg
= rld
[i
].in_reg
;
4753 enum rtx_code code
= GET_CODE (in_reg
);
4754 /* PRE_INC / PRE_DEC will have the reload register ending up
4755 with the same value as the stack slot, but that doesn't
4756 hold true for POST_INC / POST_DEC. Either we have to
4757 convert the memory access to a true POST_INC / POST_DEC,
4758 or we can't use the reload register for inheritance. */
4759 if ((code
== POST_INC
|| code
== POST_DEC
)
4760 && TEST_HARD_REG_BIT (reg_reloaded_valid
,
4761 REGNO (rld
[i
].reg_rtx
))
4762 /* Make sure it is the inc/dec pseudo, and not
4763 some other (e.g. output operand) pseudo. */
4764 && ((unsigned) reg_reloaded_contents
[REGNO (rld
[i
].reg_rtx
)]
4765 == REGNO (XEXP (in_reg
, 0))))
4768 rtx reload_reg
= rld
[i
].reg_rtx
;
4769 enum machine_mode mode
= GET_MODE (reload_reg
);
4773 for (p
= PREV_INSN (old_next
); p
!= prev
; p
= PREV_INSN (p
))
4775 /* We really want to ignore REG_INC notes here, so
4776 use PATTERN (p) as argument to reg_set_p . */
4777 if (reg_set_p (reload_reg
, PATTERN (p
)))
4779 n
= count_occurrences (PATTERN (p
), reload_reg
, 0);
4785 = gen_rtx_fmt_e (code
, mode
, reload_reg
);
4787 validate_replace_rtx_group (reload_reg
,
4789 n
= verify_changes (0);
4791 /* We must also verify that the constraints
4792 are met after the replacement. Make sure
4793 extract_insn is only called for an insn
4794 where the replacements were found to be
4799 n
= constrain_operands (1);
4802 /* If the constraints were not met, then
4803 undo the replacement, else confirm it. */
4807 confirm_change_group ();
4813 add_reg_note (p
, REG_INC
, reload_reg
);
4814 /* Mark this as having an output reload so that the
4815 REG_INC processing code below won't invalidate
4816 the reload for inheritance. */
4817 SET_HARD_REG_BIT (reg_is_output_reload
,
4818 REGNO (reload_reg
));
4819 SET_REGNO_REG_SET (®_has_output_reload
,
4820 REGNO (XEXP (in_reg
, 0)));
4823 forget_old_reloads_1 (XEXP (in_reg
, 0), NULL_RTX
,
4826 else if ((code
== PRE_INC
|| code
== PRE_DEC
)
4827 && TEST_HARD_REG_BIT (reg_reloaded_valid
,
4828 REGNO (rld
[i
].reg_rtx
))
4829 /* Make sure it is the inc/dec pseudo, and not
4830 some other (e.g. output operand) pseudo. */
4831 && ((unsigned) reg_reloaded_contents
[REGNO (rld
[i
].reg_rtx
)]
4832 == REGNO (XEXP (in_reg
, 0))))
4834 SET_HARD_REG_BIT (reg_is_output_reload
,
4835 REGNO (rld
[i
].reg_rtx
));
4836 SET_REGNO_REG_SET (®_has_output_reload
,
4837 REGNO (XEXP (in_reg
, 0)));
4839 else if (code
== PRE_INC
|| code
== PRE_DEC
4840 || code
== POST_INC
|| code
== POST_DEC
)
4842 int in_regno
= REGNO (XEXP (in_reg
, 0));
4844 if (reg_last_reload_reg
[in_regno
] != NULL_RTX
)
4847 bool forget_p
= true;
4849 in_hard_regno
= REGNO (reg_last_reload_reg
[in_regno
]);
4850 if (TEST_HARD_REG_BIT (reg_reloaded_valid
,
4853 for (rtx_insn
*x
= (old_prev
?
4854 NEXT_INSN (old_prev
) : insn
);
4857 if (x
== reg_reloaded_insn
[in_hard_regno
])
4863 /* If for some reasons, we didn't set up
4864 reg_last_reload_reg in this insn,
4865 invalidate inheritance from previous
4866 insns for the incremented/decremented
4867 register. Such registers will be not in
4868 reg_has_output_reload. Invalidate it
4869 also if the corresponding element in
4870 reg_reloaded_insn is also
4873 forget_old_reloads_1 (XEXP (in_reg
, 0),
4879 /* If a pseudo that got a hard register is auto-incremented,
4880 we must purge records of copying it into pseudos without
4882 for (rtx x
= REG_NOTES (insn
); x
; x
= XEXP (x
, 1))
4883 if (REG_NOTE_KIND (x
) == REG_INC
)
4885 /* See if this pseudo reg was reloaded in this insn.
4886 If so, its last-reload info is still valid
4887 because it is based on this insn's reload. */
4888 for (i
= 0; i
< n_reloads
; i
++)
4889 if (rld
[i
].out
== XEXP (x
, 0))
4893 forget_old_reloads_1 (XEXP (x
, 0), NULL_RTX
, NULL
);
4897 /* A reload reg's contents are unknown after a label. */
4899 CLEAR_HARD_REG_SET (reg_reloaded_valid
);
4901 /* Don't assume a reload reg is still good after a call insn
4902 if it is a call-used reg, or if it contains a value that will
4903 be partially clobbered by the call. */
4904 else if (CALL_P (insn
))
4906 AND_COMPL_HARD_REG_SET (reg_reloaded_valid
, call_used_reg_set
);
4907 AND_COMPL_HARD_REG_SET (reg_reloaded_valid
, reg_reloaded_call_part_clobbered
);
4909 /* If this is a call to a setjmp-type function, we must not
4910 reuse any reload reg contents across the call; that will
4911 just be clobbered by other uses of the register in later
4912 code, before the longjmp. */
4913 if (find_reg_note (insn
, REG_SETJMP
, NULL_RTX
))
4914 CLEAR_HARD_REG_SET (reg_reloaded_valid
);
4919 free (reg_last_reload_reg
);
4920 CLEAR_REG_SET (®_has_output_reload
);
4923 /* Discard all record of any value reloaded from X,
4924 or reloaded in X from someplace else;
4925 unless X is an output reload reg of the current insn.
4927 X may be a hard reg (the reload reg)
4928 or it may be a pseudo reg that was reloaded from.
4930 When DATA is non-NULL just mark the registers in regset
4931 to be forgotten later. */
4934 forget_old_reloads_1 (rtx x
, const_rtx ignored ATTRIBUTE_UNUSED
,
4939 regset regs
= (regset
) data
;
4941 /* note_stores does give us subregs of hard regs,
4942 subreg_regno_offset requires a hard reg. */
4943 while (GET_CODE (x
) == SUBREG
)
4945 /* We ignore the subreg offset when calculating the regno,
4946 because we are using the entire underlying hard register
4956 if (regno
>= FIRST_PSEUDO_REGISTER
)
4962 nr
= hard_regno_nregs
[regno
][GET_MODE (x
)];
4963 /* Storing into a spilled-reg invalidates its contents.
4964 This can happen if a block-local pseudo is allocated to that reg
4965 and it wasn't spilled because this block's total need is 0.
4966 Then some insn might have an optional reload and use this reg. */
4968 for (i
= 0; i
< nr
; i
++)
4969 /* But don't do this if the reg actually serves as an output
4970 reload reg in the current instruction. */
4972 || ! TEST_HARD_REG_BIT (reg_is_output_reload
, regno
+ i
))
4974 CLEAR_HARD_REG_BIT (reg_reloaded_valid
, regno
+ i
);
4975 spill_reg_store
[regno
+ i
] = 0;
4981 SET_REGNO_REG_SET (regs
, regno
+ nr
);
4984 /* Since value of X has changed,
4985 forget any value previously copied from it. */
4988 /* But don't forget a copy if this is the output reload
4989 that establishes the copy's validity. */
4991 || !REGNO_REG_SET_P (®_has_output_reload
, regno
+ nr
))
4992 reg_last_reload_reg
[regno
+ nr
] = 0;
4996 /* Forget the reloads marked in regset by previous function. */
4998 forget_marked_reloads (regset regs
)
5001 reg_set_iterator rsi
;
5002 EXECUTE_IF_SET_IN_REG_SET (regs
, 0, reg
, rsi
)
5004 if (reg
< FIRST_PSEUDO_REGISTER
5005 /* But don't do this if the reg actually serves as an output
5006 reload reg in the current instruction. */
5008 || ! TEST_HARD_REG_BIT (reg_is_output_reload
, reg
)))
5010 CLEAR_HARD_REG_BIT (reg_reloaded_valid
, reg
);
5011 spill_reg_store
[reg
] = 0;
5014 || !REGNO_REG_SET_P (®_has_output_reload
, reg
))
5015 reg_last_reload_reg
[reg
] = 0;
5019 /* The following HARD_REG_SETs indicate when each hard register is
5020 used for a reload of various parts of the current insn. */
5022 /* If reg is unavailable for all reloads. */
5023 static HARD_REG_SET reload_reg_unavailable
;
5024 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
5025 static HARD_REG_SET reload_reg_used
;
5026 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
5027 static HARD_REG_SET reload_reg_used_in_input_addr
[MAX_RECOG_OPERANDS
];
5028 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */
5029 static HARD_REG_SET reload_reg_used_in_inpaddr_addr
[MAX_RECOG_OPERANDS
];
5030 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
5031 static HARD_REG_SET reload_reg_used_in_output_addr
[MAX_RECOG_OPERANDS
];
5032 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */
5033 static HARD_REG_SET reload_reg_used_in_outaddr_addr
[MAX_RECOG_OPERANDS
];
5034 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
5035 static HARD_REG_SET reload_reg_used_in_input
[MAX_RECOG_OPERANDS
];
5036 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
5037 static HARD_REG_SET reload_reg_used_in_output
[MAX_RECOG_OPERANDS
];
5038 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
5039 static HARD_REG_SET reload_reg_used_in_op_addr
;
5040 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */
5041 static HARD_REG_SET reload_reg_used_in_op_addr_reload
;
5042 /* If reg is in use for a RELOAD_FOR_INSN reload. */
5043 static HARD_REG_SET reload_reg_used_in_insn
;
5044 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
5045 static HARD_REG_SET reload_reg_used_in_other_addr
;
5047 /* If reg is in use as a reload reg for any sort of reload. */
5048 static HARD_REG_SET reload_reg_used_at_all
;
5050 /* If reg is use as an inherited reload. We just mark the first register
5052 static HARD_REG_SET reload_reg_used_for_inherit
;
5054 /* Records which hard regs are used in any way, either as explicit use or
5055 by being allocated to a pseudo during any point of the current insn. */
5056 static HARD_REG_SET reg_used_in_insn
;
5058 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
5059 TYPE. MODE is used to indicate how many consecutive regs are
5063 mark_reload_reg_in_use (unsigned int regno
, int opnum
, enum reload_type type
,
5064 enum machine_mode mode
)
5069 add_to_hard_reg_set (&reload_reg_used
, mode
, regno
);
5072 case RELOAD_FOR_INPUT_ADDRESS
:
5073 add_to_hard_reg_set (&reload_reg_used_in_input_addr
[opnum
], mode
, regno
);
5076 case RELOAD_FOR_INPADDR_ADDRESS
:
5077 add_to_hard_reg_set (&reload_reg_used_in_inpaddr_addr
[opnum
], mode
, regno
);
5080 case RELOAD_FOR_OUTPUT_ADDRESS
:
5081 add_to_hard_reg_set (&reload_reg_used_in_output_addr
[opnum
], mode
, regno
);
5084 case RELOAD_FOR_OUTADDR_ADDRESS
:
5085 add_to_hard_reg_set (&reload_reg_used_in_outaddr_addr
[opnum
], mode
, regno
);
5088 case RELOAD_FOR_OPERAND_ADDRESS
:
5089 add_to_hard_reg_set (&reload_reg_used_in_op_addr
, mode
, regno
);
5092 case RELOAD_FOR_OPADDR_ADDR
:
5093 add_to_hard_reg_set (&reload_reg_used_in_op_addr_reload
, mode
, regno
);
5096 case RELOAD_FOR_OTHER_ADDRESS
:
5097 add_to_hard_reg_set (&reload_reg_used_in_other_addr
, mode
, regno
);
5100 case RELOAD_FOR_INPUT
:
5101 add_to_hard_reg_set (&reload_reg_used_in_input
[opnum
], mode
, regno
);
5104 case RELOAD_FOR_OUTPUT
:
5105 add_to_hard_reg_set (&reload_reg_used_in_output
[opnum
], mode
, regno
);
5108 case RELOAD_FOR_INSN
:
5109 add_to_hard_reg_set (&reload_reg_used_in_insn
, mode
, regno
);
5113 add_to_hard_reg_set (&reload_reg_used_at_all
, mode
, regno
);
5116 /* Similarly, but show REGNO is no longer in use for a reload. */
5119 clear_reload_reg_in_use (unsigned int regno
, int opnum
,
5120 enum reload_type type
, enum machine_mode mode
)
5122 unsigned int nregs
= hard_regno_nregs
[regno
][mode
];
5123 unsigned int start_regno
, end_regno
, r
;
5125 /* A complication is that for some reload types, inheritance might
5126 allow multiple reloads of the same types to share a reload register.
5127 We set check_opnum if we have to check only reloads with the same
5128 operand number, and check_any if we have to check all reloads. */
5129 int check_opnum
= 0;
5131 HARD_REG_SET
*used_in_set
;
5136 used_in_set
= &reload_reg_used
;
5139 case RELOAD_FOR_INPUT_ADDRESS
:
5140 used_in_set
= &reload_reg_used_in_input_addr
[opnum
];
5143 case RELOAD_FOR_INPADDR_ADDRESS
:
5145 used_in_set
= &reload_reg_used_in_inpaddr_addr
[opnum
];
5148 case RELOAD_FOR_OUTPUT_ADDRESS
:
5149 used_in_set
= &reload_reg_used_in_output_addr
[opnum
];
5152 case RELOAD_FOR_OUTADDR_ADDRESS
:
5154 used_in_set
= &reload_reg_used_in_outaddr_addr
[opnum
];
5157 case RELOAD_FOR_OPERAND_ADDRESS
:
5158 used_in_set
= &reload_reg_used_in_op_addr
;
5161 case RELOAD_FOR_OPADDR_ADDR
:
5163 used_in_set
= &reload_reg_used_in_op_addr_reload
;
5166 case RELOAD_FOR_OTHER_ADDRESS
:
5167 used_in_set
= &reload_reg_used_in_other_addr
;
5171 case RELOAD_FOR_INPUT
:
5172 used_in_set
= &reload_reg_used_in_input
[opnum
];
5175 case RELOAD_FOR_OUTPUT
:
5176 used_in_set
= &reload_reg_used_in_output
[opnum
];
5179 case RELOAD_FOR_INSN
:
5180 used_in_set
= &reload_reg_used_in_insn
;
5185 /* We resolve conflicts with remaining reloads of the same type by
5186 excluding the intervals of reload registers by them from the
5187 interval of freed reload registers. Since we only keep track of
5188 one set of interval bounds, we might have to exclude somewhat
5189 more than what would be necessary if we used a HARD_REG_SET here.
5190 But this should only happen very infrequently, so there should
5191 be no reason to worry about it. */
5193 start_regno
= regno
;
5194 end_regno
= regno
+ nregs
;
5195 if (check_opnum
|| check_any
)
5197 for (i
= n_reloads
- 1; i
>= 0; i
--)
5199 if (rld
[i
].when_needed
== type
5200 && (check_any
|| rld
[i
].opnum
== opnum
)
5203 unsigned int conflict_start
= true_regnum (rld
[i
].reg_rtx
);
5204 unsigned int conflict_end
5205 = end_hard_regno (rld
[i
].mode
, conflict_start
);
5207 /* If there is an overlap with the first to-be-freed register,
5208 adjust the interval start. */
5209 if (conflict_start
<= start_regno
&& conflict_end
> start_regno
)
5210 start_regno
= conflict_end
;
5211 /* Otherwise, if there is a conflict with one of the other
5212 to-be-freed registers, adjust the interval end. */
5213 if (conflict_start
> start_regno
&& conflict_start
< end_regno
)
5214 end_regno
= conflict_start
;
5219 for (r
= start_regno
; r
< end_regno
; r
++)
5220 CLEAR_HARD_REG_BIT (*used_in_set
, r
);
5223 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
5224 specified by OPNUM and TYPE. */
5227 reload_reg_free_p (unsigned int regno
, int opnum
, enum reload_type type
)
5231 /* In use for a RELOAD_OTHER means it's not available for anything. */
5232 if (TEST_HARD_REG_BIT (reload_reg_used
, regno
)
5233 || TEST_HARD_REG_BIT (reload_reg_unavailable
, regno
))
5239 /* In use for anything means we can't use it for RELOAD_OTHER. */
5240 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr
, regno
)
5241 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
)
5242 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload
, regno
)
5243 || TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
))
5246 for (i
= 0; i
< reload_n_operands
; i
++)
5247 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
5248 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
)
5249 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
5250 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
)
5251 || TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
)
5252 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
5257 case RELOAD_FOR_INPUT
:
5258 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
5259 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
))
5262 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload
, regno
))
5265 /* If it is used for some other input, can't use it. */
5266 for (i
= 0; i
< reload_n_operands
; i
++)
5267 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
5270 /* If it is used in a later operand's address, can't use it. */
5271 for (i
= opnum
+ 1; i
< reload_n_operands
; i
++)
5272 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
5273 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
))
5278 case RELOAD_FOR_INPUT_ADDRESS
:
5279 /* Can't use a register if it is used for an input address for this
5280 operand or used as an input in an earlier one. */
5281 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[opnum
], regno
)
5282 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[opnum
], regno
))
5285 for (i
= 0; i
< opnum
; i
++)
5286 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
5291 case RELOAD_FOR_INPADDR_ADDRESS
:
5292 /* Can't use a register if it is used for an input address
5293 for this operand or used as an input in an earlier
5295 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[opnum
], regno
))
5298 for (i
= 0; i
< opnum
; i
++)
5299 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
5304 case RELOAD_FOR_OUTPUT_ADDRESS
:
5305 /* Can't use a register if it is used for an output address for this
5306 operand or used as an output in this or a later operand. Note
5307 that multiple output operands are emitted in reverse order, so
5308 the conflicting ones are those with lower indices. */
5309 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[opnum
], regno
))
5312 for (i
= 0; i
<= opnum
; i
++)
5313 if (TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
5318 case RELOAD_FOR_OUTADDR_ADDRESS
:
5319 /* Can't use a register if it is used for an output address
5320 for this operand or used as an output in this or a
5321 later operand. Note that multiple output operands are
5322 emitted in reverse order, so the conflicting ones are
5323 those with lower indices. */
5324 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[opnum
], regno
))
5327 for (i
= 0; i
<= opnum
; i
++)
5328 if (TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
5333 case RELOAD_FOR_OPERAND_ADDRESS
:
5334 for (i
= 0; i
< reload_n_operands
; i
++)
5335 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
5338 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
5339 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
));
5341 case RELOAD_FOR_OPADDR_ADDR
:
5342 for (i
= 0; i
< reload_n_operands
; i
++)
5343 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
5346 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload
, regno
));
5348 case RELOAD_FOR_OUTPUT
:
5349 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
5350 outputs, or an operand address for this or an earlier output.
5351 Note that multiple output operands are emitted in reverse order,
5352 so the conflicting ones are those with higher indices. */
5353 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
))
5356 for (i
= 0; i
< reload_n_operands
; i
++)
5357 if (TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
5360 for (i
= opnum
; i
< reload_n_operands
; i
++)
5361 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
5362 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
))
5367 case RELOAD_FOR_INSN
:
5368 for (i
= 0; i
< reload_n_operands
; i
++)
5369 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
)
5370 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
5373 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
5374 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
));
5376 case RELOAD_FOR_OTHER_ADDRESS
:
5377 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr
, regno
);
5384 /* Return 1 if the value in reload reg REGNO, as used by the reload with
5385 the number RELOADNUM, is still available in REGNO at the end of the insn.
5387 We can assume that the reload reg was already tested for availability
5388 at the time it is needed, and we should not check this again,
5389 in case the reg has already been marked in use. */
5392 reload_reg_reaches_end_p (unsigned int regno
, int reloadnum
)
5394 int opnum
= rld
[reloadnum
].opnum
;
5395 enum reload_type type
= rld
[reloadnum
].when_needed
;
5398 /* See if there is a reload with the same type for this operand, using
5399 the same register. This case is not handled by the code below. */
5400 for (i
= reloadnum
+ 1; i
< n_reloads
; i
++)
5405 if (rld
[i
].opnum
!= opnum
|| rld
[i
].when_needed
!= type
)
5407 reg
= rld
[i
].reg_rtx
;
5408 if (reg
== NULL_RTX
)
5410 nregs
= hard_regno_nregs
[REGNO (reg
)][GET_MODE (reg
)];
5411 if (regno
>= REGNO (reg
) && regno
< REGNO (reg
) + nregs
)
5418 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
5419 its value must reach the end. */
5422 /* If this use is for part of the insn,
5423 its value reaches if no subsequent part uses the same register.
5424 Just like the above function, don't try to do this with lots
5427 case RELOAD_FOR_OTHER_ADDRESS
:
5428 /* Here we check for everything else, since these don't conflict
5429 with anything else and everything comes later. */
5431 for (i
= 0; i
< reload_n_operands
; i
++)
5432 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
5433 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
)
5434 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
)
5435 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
5436 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
)
5437 || TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
5440 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
)
5441 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload
, regno
)
5442 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
5443 && ! TEST_HARD_REG_BIT (reload_reg_used
, regno
));
5445 case RELOAD_FOR_INPUT_ADDRESS
:
5446 case RELOAD_FOR_INPADDR_ADDRESS
:
5447 /* Similar, except that we check only for this and subsequent inputs
5448 and the address of only subsequent inputs and we do not need
5449 to check for RELOAD_OTHER objects since they are known not to
5452 for (i
= opnum
; i
< reload_n_operands
; i
++)
5453 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
5456 /* Reload register of reload with type RELOAD_FOR_INPADDR_ADDRESS
5457 could be killed if the register is also used by reload with type
5458 RELOAD_FOR_INPUT_ADDRESS, so check it. */
5459 if (type
== RELOAD_FOR_INPADDR_ADDRESS
5460 && TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[opnum
], regno
))
5463 for (i
= opnum
+ 1; i
< reload_n_operands
; i
++)
5464 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
5465 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
))
5468 for (i
= 0; i
< reload_n_operands
; i
++)
5469 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
5470 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
)
5471 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
5474 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload
, regno
))
5477 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
)
5478 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
5479 && !TEST_HARD_REG_BIT (reload_reg_used
, regno
));
5481 case RELOAD_FOR_INPUT
:
5482 /* Similar to input address, except we start at the next operand for
5483 both input and input address and we do not check for
5484 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
5487 for (i
= opnum
+ 1; i
< reload_n_operands
; i
++)
5488 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
5489 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
)
5490 || TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
5493 /* ... fall through ... */
5495 case RELOAD_FOR_OPERAND_ADDRESS
:
5496 /* Check outputs and their addresses. */
5498 for (i
= 0; i
< reload_n_operands
; i
++)
5499 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
5500 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
)
5501 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
5504 return (!TEST_HARD_REG_BIT (reload_reg_used
, regno
));
5506 case RELOAD_FOR_OPADDR_ADDR
:
5507 for (i
= 0; i
< reload_n_operands
; i
++)
5508 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
5509 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
)
5510 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
5513 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
)
5514 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
5515 && !TEST_HARD_REG_BIT (reload_reg_used
, regno
));
5517 case RELOAD_FOR_INSN
:
5518 /* These conflict with other outputs with RELOAD_OTHER. So
5519 we need only check for output addresses. */
5521 opnum
= reload_n_operands
;
5523 /* ... fall through ... */
5525 case RELOAD_FOR_OUTPUT
:
5526 case RELOAD_FOR_OUTPUT_ADDRESS
:
5527 case RELOAD_FOR_OUTADDR_ADDRESS
:
5528 /* We already know these can't conflict with a later output. So the
5529 only thing to check are later output addresses.
5530 Note that multiple output operands are emitted in reverse order,
5531 so the conflicting ones are those with lower indices. */
5532 for (i
= 0; i
< opnum
; i
++)
5533 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
5534 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
))
5537 /* Reload register of reload with type RELOAD_FOR_OUTADDR_ADDRESS
5538 could be killed if the register is also used by reload with type
5539 RELOAD_FOR_OUTPUT_ADDRESS, so check it. */
5540 if (type
== RELOAD_FOR_OUTADDR_ADDRESS
5541 && TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[opnum
], regno
))
5551 /* Like reload_reg_reaches_end_p, but check that the condition holds for
5552 every register in REG. */
5555 reload_reg_rtx_reaches_end_p (rtx reg
, int reloadnum
)
5559 for (i
= REGNO (reg
); i
< END_REGNO (reg
); i
++)
5560 if (!reload_reg_reaches_end_p (i
, reloadnum
))
5566 /* Returns whether R1 and R2 are uniquely chained: the value of one
5567 is used by the other, and that value is not used by any other
5568 reload for this insn. This is used to partially undo the decision
5569 made in find_reloads when in the case of multiple
5570 RELOAD_FOR_OPERAND_ADDRESS reloads it converts all
5571 RELOAD_FOR_OPADDR_ADDR reloads into RELOAD_FOR_OPERAND_ADDRESS
5572 reloads. This code tries to avoid the conflict created by that
5573 change. It might be cleaner to explicitly keep track of which
5574 RELOAD_FOR_OPADDR_ADDR reload is associated with which
5575 RELOAD_FOR_OPERAND_ADDRESS reload, rather than to try to detect
5576 this after the fact. */
5578 reloads_unique_chain_p (int r1
, int r2
)
5582 /* We only check input reloads. */
5583 if (! rld
[r1
].in
|| ! rld
[r2
].in
)
5586 /* Avoid anything with output reloads. */
5587 if (rld
[r1
].out
|| rld
[r2
].out
)
5590 /* "chained" means one reload is a component of the other reload,
5591 not the same as the other reload. */
5592 if (rld
[r1
].opnum
!= rld
[r2
].opnum
5593 || rtx_equal_p (rld
[r1
].in
, rld
[r2
].in
)
5594 || rld
[r1
].optional
|| rld
[r2
].optional
5595 || ! (reg_mentioned_p (rld
[r1
].in
, rld
[r2
].in
)
5596 || reg_mentioned_p (rld
[r2
].in
, rld
[r1
].in
)))
5599 /* The following loop assumes that r1 is the reload that feeds r2. */
5607 for (i
= 0; i
< n_reloads
; i
++)
5608 /* Look for input reloads that aren't our two */
5609 if (i
!= r1
&& i
!= r2
&& rld
[i
].in
)
5611 /* If our reload is mentioned at all, it isn't a simple chain. */
5612 if (reg_mentioned_p (rld
[r1
].in
, rld
[i
].in
))
5618 /* The recursive function change all occurrences of WHAT in *WHERE
5621 substitute (rtx
*where
, const_rtx what
, rtx repl
)
5630 if (*where
== what
|| rtx_equal_p (*where
, what
))
5632 /* Record the location of the changed rtx. */
5633 substitute_stack
.safe_push (where
);
5638 code
= GET_CODE (*where
);
5639 fmt
= GET_RTX_FORMAT (code
);
5640 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
5646 for (j
= XVECLEN (*where
, i
) - 1; j
>= 0; j
--)
5647 substitute (&XVECEXP (*where
, i
, j
), what
, repl
);
5649 else if (fmt
[i
] == 'e')
5650 substitute (&XEXP (*where
, i
), what
, repl
);
5654 /* The function returns TRUE if chain of reload R1 and R2 (in any
5655 order) can be evaluated without usage of intermediate register for
5656 the reload containing another reload. It is important to see
5657 gen_reload to understand what the function is trying to do. As an
5658 example, let us have reload chain
5661 r1: <something> + const
5663 and reload R2 got reload reg HR. The function returns true if
5664 there is a correct insn HR = HR + <something>. Otherwise,
5665 gen_reload will use intermediate register (and this is the reload
5666 reg for R1) to reload <something>.
5668 We need this function to find a conflict for chain reloads. In our
5669 example, if HR = HR + <something> is incorrect insn, then we cannot
5670 use HR as a reload register for R2. If we do use it then we get a
5679 gen_reload_chain_without_interm_reg_p (int r1
, int r2
)
5681 /* Assume other cases in gen_reload are not possible for
5682 chain reloads or do need an intermediate hard registers. */
5687 rtx_insn
*last
= get_last_insn ();
5689 /* Make r2 a component of r1. */
5690 if (reg_mentioned_p (rld
[r1
].in
, rld
[r2
].in
))
5696 gcc_assert (reg_mentioned_p (rld
[r2
].in
, rld
[r1
].in
));
5697 regno
= rld
[r1
].regno
>= 0 ? rld
[r1
].regno
: rld
[r2
].regno
;
5698 gcc_assert (regno
>= 0);
5699 out
= gen_rtx_REG (rld
[r1
].mode
, regno
);
5701 substitute (&in
, rld
[r2
].in
, gen_rtx_REG (rld
[r2
].mode
, regno
));
5703 /* If IN is a paradoxical SUBREG, remove it and try to put the
5704 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
5705 strip_paradoxical_subreg (&in
, &out
);
5707 if (GET_CODE (in
) == PLUS
5708 && (REG_P (XEXP (in
, 0))
5709 || GET_CODE (XEXP (in
, 0)) == SUBREG
5710 || MEM_P (XEXP (in
, 0)))
5711 && (REG_P (XEXP (in
, 1))
5712 || GET_CODE (XEXP (in
, 1)) == SUBREG
5713 || CONSTANT_P (XEXP (in
, 1))
5714 || MEM_P (XEXP (in
, 1))))
5716 insn
= emit_insn (gen_rtx_SET (VOIDmode
, out
, in
));
5717 code
= recog_memoized (insn
);
5722 extract_insn (insn
);
5723 /* We want constrain operands to treat this insn strictly in
5724 its validity determination, i.e., the way it would after
5725 reload has completed. */
5726 result
= constrain_operands (1);
5729 delete_insns_since (last
);
5732 /* Restore the original value at each changed address within R1. */
5733 while (!substitute_stack
.is_empty ())
5735 rtx
*where
= substitute_stack
.pop ();
5736 *where
= rld
[r2
].in
;
5742 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
5745 This function uses the same algorithm as reload_reg_free_p above. */
5748 reloads_conflict (int r1
, int r2
)
5750 enum reload_type r1_type
= rld
[r1
].when_needed
;
5751 enum reload_type r2_type
= rld
[r2
].when_needed
;
5752 int r1_opnum
= rld
[r1
].opnum
;
5753 int r2_opnum
= rld
[r2
].opnum
;
5755 /* RELOAD_OTHER conflicts with everything. */
5756 if (r2_type
== RELOAD_OTHER
)
5759 /* Otherwise, check conflicts differently for each type. */
5763 case RELOAD_FOR_INPUT
:
5764 return (r2_type
== RELOAD_FOR_INSN
5765 || r2_type
== RELOAD_FOR_OPERAND_ADDRESS
5766 || r2_type
== RELOAD_FOR_OPADDR_ADDR
5767 || r2_type
== RELOAD_FOR_INPUT
5768 || ((r2_type
== RELOAD_FOR_INPUT_ADDRESS
5769 || r2_type
== RELOAD_FOR_INPADDR_ADDRESS
)
5770 && r2_opnum
> r1_opnum
));
5772 case RELOAD_FOR_INPUT_ADDRESS
:
5773 return ((r2_type
== RELOAD_FOR_INPUT_ADDRESS
&& r1_opnum
== r2_opnum
)
5774 || (r2_type
== RELOAD_FOR_INPUT
&& r2_opnum
< r1_opnum
));
5776 case RELOAD_FOR_INPADDR_ADDRESS
:
5777 return ((r2_type
== RELOAD_FOR_INPADDR_ADDRESS
&& r1_opnum
== r2_opnum
)
5778 || (r2_type
== RELOAD_FOR_INPUT
&& r2_opnum
< r1_opnum
));
5780 case RELOAD_FOR_OUTPUT_ADDRESS
:
5781 return ((r2_type
== RELOAD_FOR_OUTPUT_ADDRESS
&& r2_opnum
== r1_opnum
)
5782 || (r2_type
== RELOAD_FOR_OUTPUT
&& r2_opnum
<= r1_opnum
));
5784 case RELOAD_FOR_OUTADDR_ADDRESS
:
5785 return ((r2_type
== RELOAD_FOR_OUTADDR_ADDRESS
&& r2_opnum
== r1_opnum
)
5786 || (r2_type
== RELOAD_FOR_OUTPUT
&& r2_opnum
<= r1_opnum
));
5788 case RELOAD_FOR_OPERAND_ADDRESS
:
5789 return (r2_type
== RELOAD_FOR_INPUT
|| r2_type
== RELOAD_FOR_INSN
5790 || (r2_type
== RELOAD_FOR_OPERAND_ADDRESS
5791 && (!reloads_unique_chain_p (r1
, r2
)
5792 || !gen_reload_chain_without_interm_reg_p (r1
, r2
))));
5794 case RELOAD_FOR_OPADDR_ADDR
:
5795 return (r2_type
== RELOAD_FOR_INPUT
5796 || r2_type
== RELOAD_FOR_OPADDR_ADDR
);
5798 case RELOAD_FOR_OUTPUT
:
5799 return (r2_type
== RELOAD_FOR_INSN
|| r2_type
== RELOAD_FOR_OUTPUT
5800 || ((r2_type
== RELOAD_FOR_OUTPUT_ADDRESS
5801 || r2_type
== RELOAD_FOR_OUTADDR_ADDRESS
)
5802 && r2_opnum
>= r1_opnum
));
5804 case RELOAD_FOR_INSN
:
5805 return (r2_type
== RELOAD_FOR_INPUT
|| r2_type
== RELOAD_FOR_OUTPUT
5806 || r2_type
== RELOAD_FOR_INSN
5807 || r2_type
== RELOAD_FOR_OPERAND_ADDRESS
);
5809 case RELOAD_FOR_OTHER_ADDRESS
:
5810 return r2_type
== RELOAD_FOR_OTHER_ADDRESS
;
5820 /* Indexed by reload number, 1 if incoming value
5821 inherited from previous insns. */
5822 static char reload_inherited
[MAX_RELOADS
];
5824 /* For an inherited reload, this is the insn the reload was inherited from,
5825 if we know it. Otherwise, this is 0. */
5826 static rtx_insn
*reload_inheritance_insn
[MAX_RELOADS
];
5828 /* If nonzero, this is a place to get the value of the reload,
5829 rather than using reload_in. */
5830 static rtx reload_override_in
[MAX_RELOADS
];
5832 /* For each reload, the hard register number of the register used,
5833 or -1 if we did not need a register for this reload. */
5834 static int reload_spill_index
[MAX_RELOADS
];
5836 /* Index X is the value of rld[X].reg_rtx, adjusted for the input mode. */
5837 static rtx reload_reg_rtx_for_input
[MAX_RELOADS
];
5839 /* Index X is the value of rld[X].reg_rtx, adjusted for the output mode. */
5840 static rtx reload_reg_rtx_for_output
[MAX_RELOADS
];
5842 /* Subroutine of free_for_value_p, used to check a single register.
5843 START_REGNO is the starting regno of the full reload register
5844 (possibly comprising multiple hard registers) that we are considering. */
5847 reload_reg_free_for_value_p (int start_regno
, int regno
, int opnum
,
5848 enum reload_type type
, rtx value
, rtx out
,
5849 int reloadnum
, int ignore_address_reloads
)
5852 /* Set if we see an input reload that must not share its reload register
5853 with any new earlyclobber, but might otherwise share the reload
5854 register with an output or input-output reload. */
5855 int check_earlyclobber
= 0;
5859 if (TEST_HARD_REG_BIT (reload_reg_unavailable
, regno
))
5862 if (out
== const0_rtx
)
5868 /* We use some pseudo 'time' value to check if the lifetimes of the
5869 new register use would overlap with the one of a previous reload
5870 that is not read-only or uses a different value.
5871 The 'time' used doesn't have to be linear in any shape or form, just
5873 Some reload types use different 'buckets' for each operand.
5874 So there are MAX_RECOG_OPERANDS different time values for each
5876 We compute TIME1 as the time when the register for the prospective
5877 new reload ceases to be live, and TIME2 for each existing
5878 reload as the time when that the reload register of that reload
5880 Where there is little to be gained by exact lifetime calculations,
5881 we just make conservative assumptions, i.e. a longer lifetime;
5882 this is done in the 'default:' cases. */
5885 case RELOAD_FOR_OTHER_ADDRESS
:
5886 /* RELOAD_FOR_OTHER_ADDRESS conflicts with RELOAD_OTHER reloads. */
5887 time1
= copy
? 0 : 1;
5890 time1
= copy
? 1 : MAX_RECOG_OPERANDS
* 5 + 5;
5892 /* For each input, we may have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
5893 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 ,
5894 respectively, to the time values for these, we get distinct time
5895 values. To get distinct time values for each operand, we have to
5896 multiply opnum by at least three. We round that up to four because
5897 multiply by four is often cheaper. */
5898 case RELOAD_FOR_INPADDR_ADDRESS
:
5899 time1
= opnum
* 4 + 2;
5901 case RELOAD_FOR_INPUT_ADDRESS
:
5902 time1
= opnum
* 4 + 3;
5904 case RELOAD_FOR_INPUT
:
5905 /* All RELOAD_FOR_INPUT reloads remain live till the instruction
5906 executes (inclusive). */
5907 time1
= copy
? opnum
* 4 + 4 : MAX_RECOG_OPERANDS
* 4 + 3;
5909 case RELOAD_FOR_OPADDR_ADDR
:
5911 <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
5912 time1
= MAX_RECOG_OPERANDS
* 4 + 1;
5914 case RELOAD_FOR_OPERAND_ADDRESS
:
5915 /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn
5917 time1
= copy
? MAX_RECOG_OPERANDS
* 4 + 2 : MAX_RECOG_OPERANDS
* 4 + 3;
5919 case RELOAD_FOR_OUTADDR_ADDRESS
:
5920 time1
= MAX_RECOG_OPERANDS
* 4 + 4 + opnum
;
5922 case RELOAD_FOR_OUTPUT_ADDRESS
:
5923 time1
= MAX_RECOG_OPERANDS
* 4 + 5 + opnum
;
5926 time1
= MAX_RECOG_OPERANDS
* 5 + 5;
5929 for (i
= 0; i
< n_reloads
; i
++)
5931 rtx reg
= rld
[i
].reg_rtx
;
5932 if (reg
&& REG_P (reg
)
5933 && ((unsigned) regno
- true_regnum (reg
)
5934 <= hard_regno_nregs
[REGNO (reg
)][GET_MODE (reg
)] - (unsigned) 1)
5937 rtx other_input
= rld
[i
].in
;
5939 /* If the other reload loads the same input value, that
5940 will not cause a conflict only if it's loading it into
5941 the same register. */
5942 if (true_regnum (reg
) != start_regno
)
5943 other_input
= NULL_RTX
;
5944 if (! other_input
|| ! rtx_equal_p (other_input
, value
)
5945 || rld
[i
].out
|| out
)
5948 switch (rld
[i
].when_needed
)
5950 case RELOAD_FOR_OTHER_ADDRESS
:
5953 case RELOAD_FOR_INPADDR_ADDRESS
:
5954 /* find_reloads makes sure that a
5955 RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used
5956 by at most one - the first -
5957 RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the
5958 address reload is inherited, the address address reload
5959 goes away, so we can ignore this conflict. */
5960 if (type
== RELOAD_FOR_INPUT_ADDRESS
&& reloadnum
== i
+ 1
5961 && ignore_address_reloads
5962 /* Unless the RELOAD_FOR_INPUT is an auto_inc expression.
5963 Then the address address is still needed to store
5964 back the new address. */
5965 && ! rld
[reloadnum
].out
)
5967 /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its
5968 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS
5970 if (type
== RELOAD_FOR_INPUT
&& opnum
== rld
[i
].opnum
5971 && ignore_address_reloads
5972 /* Unless we are reloading an auto_inc expression. */
5973 && ! rld
[reloadnum
].out
)
5975 time2
= rld
[i
].opnum
* 4 + 2;
5977 case RELOAD_FOR_INPUT_ADDRESS
:
5978 if (type
== RELOAD_FOR_INPUT
&& opnum
== rld
[i
].opnum
5979 && ignore_address_reloads
5980 && ! rld
[reloadnum
].out
)
5982 time2
= rld
[i
].opnum
* 4 + 3;
5984 case RELOAD_FOR_INPUT
:
5985 time2
= rld
[i
].opnum
* 4 + 4;
5986 check_earlyclobber
= 1;
5988 /* rld[i].opnum * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4
5989 == MAX_RECOG_OPERAND * 4 */
5990 case RELOAD_FOR_OPADDR_ADDR
:
5991 if (type
== RELOAD_FOR_OPERAND_ADDRESS
&& reloadnum
== i
+ 1
5992 && ignore_address_reloads
5993 && ! rld
[reloadnum
].out
)
5995 time2
= MAX_RECOG_OPERANDS
* 4 + 1;
5997 case RELOAD_FOR_OPERAND_ADDRESS
:
5998 time2
= MAX_RECOG_OPERANDS
* 4 + 2;
5999 check_earlyclobber
= 1;
6001 case RELOAD_FOR_INSN
:
6002 time2
= MAX_RECOG_OPERANDS
* 4 + 3;
6004 case RELOAD_FOR_OUTPUT
:
6005 /* All RELOAD_FOR_OUTPUT reloads become live just after the
6006 instruction is executed. */
6007 time2
= MAX_RECOG_OPERANDS
* 4 + 4;
6009 /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with
6010 the RELOAD_FOR_OUTPUT reloads, so assign it the same time
6012 case RELOAD_FOR_OUTADDR_ADDRESS
:
6013 if (type
== RELOAD_FOR_OUTPUT_ADDRESS
&& reloadnum
== i
+ 1
6014 && ignore_address_reloads
6015 && ! rld
[reloadnum
].out
)
6017 time2
= MAX_RECOG_OPERANDS
* 4 + 4 + rld
[i
].opnum
;
6019 case RELOAD_FOR_OUTPUT_ADDRESS
:
6020 time2
= MAX_RECOG_OPERANDS
* 4 + 5 + rld
[i
].opnum
;
6023 /* If there is no conflict in the input part, handle this
6024 like an output reload. */
6025 if (! rld
[i
].in
|| rtx_equal_p (other_input
, value
))
6027 time2
= MAX_RECOG_OPERANDS
* 4 + 4;
6028 /* Earlyclobbered outputs must conflict with inputs. */
6029 if (earlyclobber_operand_p (rld
[i
].out
))
6030 time2
= MAX_RECOG_OPERANDS
* 4 + 3;
6035 /* RELOAD_OTHER might be live beyond instruction execution,
6036 but this is not obvious when we set time2 = 1. So check
6037 here if there might be a problem with the new reload
6038 clobbering the register used by the RELOAD_OTHER. */
6046 && (! rld
[i
].in
|| rld
[i
].out
6047 || ! rtx_equal_p (other_input
, value
)))
6048 || (out
&& rld
[reloadnum
].out_reg
6049 && time2
>= MAX_RECOG_OPERANDS
* 4 + 3))
6055 /* Earlyclobbered outputs must conflict with inputs. */
6056 if (check_earlyclobber
&& out
&& earlyclobber_operand_p (out
))
6062 /* Return 1 if the value in reload reg REGNO, as used by a reload
6063 needed for the part of the insn specified by OPNUM and TYPE,
6064 may be used to load VALUE into it.
6066 MODE is the mode in which the register is used, this is needed to
6067 determine how many hard regs to test.
6069 Other read-only reloads with the same value do not conflict
6070 unless OUT is nonzero and these other reloads have to live while
6071 output reloads live.
6072 If OUT is CONST0_RTX, this is a special case: it means that the
6073 test should not be for using register REGNO as reload register, but
6074 for copying from register REGNO into the reload register.
6076 RELOADNUM is the number of the reload we want to load this value for;
6077 a reload does not conflict with itself.
6079 When IGNORE_ADDRESS_RELOADS is set, we can not have conflicts with
6080 reloads that load an address for the very reload we are considering.
6082 The caller has to make sure that there is no conflict with the return
6086 free_for_value_p (int regno
, enum machine_mode mode
, int opnum
,
6087 enum reload_type type
, rtx value
, rtx out
, int reloadnum
,
6088 int ignore_address_reloads
)
6090 int nregs
= hard_regno_nregs
[regno
][mode
];
6092 if (! reload_reg_free_for_value_p (regno
, regno
+ nregs
, opnum
, type
,
6093 value
, out
, reloadnum
,
6094 ignore_address_reloads
))
6099 /* Return nonzero if the rtx X is invariant over the current function. */
6100 /* ??? Actually, the places where we use this expect exactly what is
6101 tested here, and not everything that is function invariant. In
6102 particular, the frame pointer and arg pointer are special cased;
6103 pic_offset_table_rtx is not, and we must not spill these things to
6107 function_invariant_p (const_rtx x
)
6111 if (x
== frame_pointer_rtx
|| x
== arg_pointer_rtx
)
6113 if (GET_CODE (x
) == PLUS
6114 && (XEXP (x
, 0) == frame_pointer_rtx
|| XEXP (x
, 0) == arg_pointer_rtx
)
6115 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
6120 /* Determine whether the reload reg X overlaps any rtx'es used for
6121 overriding inheritance. Return nonzero if so. */
6124 conflicts_with_override (rtx x
)
6127 for (i
= 0; i
< n_reloads
; i
++)
6128 if (reload_override_in
[i
]
6129 && reg_overlap_mentioned_p (x
, reload_override_in
[i
]))
6134 /* Give an error message saying we failed to find a reload for INSN,
6135 and clear out reload R. */
6137 failed_reload (rtx_insn
*insn
, int r
)
6139 if (asm_noperands (PATTERN (insn
)) < 0)
6140 /* It's the compiler's fault. */
6141 fatal_insn ("could not find a spill register", insn
);
6143 /* It's the user's fault; the operand's mode and constraint
6144 don't match. Disable this reload so we don't crash in final. */
6145 error_for_asm (insn
,
6146 "%<asm%> operand constraint incompatible with operand size");
6150 rld
[r
].optional
= 1;
6151 rld
[r
].secondary_p
= 1;
6154 /* I is the index in SPILL_REG_RTX of the reload register we are to allocate
6155 for reload R. If it's valid, get an rtx for it. Return nonzero if
6158 set_reload_reg (int i
, int r
)
6160 /* regno is 'set but not used' if HARD_REGNO_MODE_OK doesn't use its first
6162 int regno ATTRIBUTE_UNUSED
;
6163 rtx reg
= spill_reg_rtx
[i
];
6165 if (reg
== 0 || GET_MODE (reg
) != rld
[r
].mode
)
6166 spill_reg_rtx
[i
] = reg
6167 = gen_rtx_REG (rld
[r
].mode
, spill_regs
[i
]);
6169 regno
= true_regnum (reg
);
6171 /* Detect when the reload reg can't hold the reload mode.
6172 This used to be one `if', but Sequent compiler can't handle that. */
6173 if (HARD_REGNO_MODE_OK (regno
, rld
[r
].mode
))
6175 enum machine_mode test_mode
= VOIDmode
;
6177 test_mode
= GET_MODE (rld
[r
].in
);
6178 /* If rld[r].in has VOIDmode, it means we will load it
6179 in whatever mode the reload reg has: to wit, rld[r].mode.
6180 We have already tested that for validity. */
6181 /* Aside from that, we need to test that the expressions
6182 to reload from or into have modes which are valid for this
6183 reload register. Otherwise the reload insns would be invalid. */
6184 if (! (rld
[r
].in
!= 0 && test_mode
!= VOIDmode
6185 && ! HARD_REGNO_MODE_OK (regno
, test_mode
)))
6186 if (! (rld
[r
].out
!= 0
6187 && ! HARD_REGNO_MODE_OK (regno
, GET_MODE (rld
[r
].out
))))
6189 /* The reg is OK. */
6192 /* Mark as in use for this insn the reload regs we use
6194 mark_reload_reg_in_use (spill_regs
[i
], rld
[r
].opnum
,
6195 rld
[r
].when_needed
, rld
[r
].mode
);
6197 rld
[r
].reg_rtx
= reg
;
6198 reload_spill_index
[r
] = spill_regs
[i
];
6205 /* Find a spill register to use as a reload register for reload R.
6206 LAST_RELOAD is nonzero if this is the last reload for the insn being
6209 Set rld[R].reg_rtx to the register allocated.
6211 We return 1 if successful, or 0 if we couldn't find a spill reg and
6212 we didn't change anything. */
6215 allocate_reload_reg (struct insn_chain
*chain ATTRIBUTE_UNUSED
, int r
,
6220 /* If we put this reload ahead, thinking it is a group,
6221 then insist on finding a group. Otherwise we can grab a
6222 reg that some other reload needs.
6223 (That can happen when we have a 68000 DATA_OR_FP_REG
6224 which is a group of data regs or one fp reg.)
6225 We need not be so restrictive if there are no more reloads
6228 ??? Really it would be nicer to have smarter handling
6229 for that kind of reg class, where a problem like this is normal.
6230 Perhaps those classes should be avoided for reloading
6231 by use of more alternatives. */
6233 int force_group
= rld
[r
].nregs
> 1 && ! last_reload
;
6235 /* If we want a single register and haven't yet found one,
6236 take any reg in the right class and not in use.
6237 If we want a consecutive group, here is where we look for it.
6239 We use three passes so we can first look for reload regs to
6240 reuse, which are already in use for other reloads in this insn,
6241 and only then use additional registers which are not "bad", then
6242 finally any register.
6244 I think that maximizing reuse is needed to make sure we don't
6245 run out of reload regs. Suppose we have three reloads, and
6246 reloads A and B can share regs. These need two regs.
6247 Suppose A and B are given different regs.
6248 That leaves none for C. */
6249 for (pass
= 0; pass
< 3; pass
++)
6251 /* I is the index in spill_regs.
6252 We advance it round-robin between insns to use all spill regs
6253 equally, so that inherited reloads have a chance
6254 of leapfrogging each other. */
6258 for (count
= 0; count
< n_spills
; count
++)
6260 int rclass
= (int) rld
[r
].rclass
;
6266 regnum
= spill_regs
[i
];
6268 if ((reload_reg_free_p (regnum
, rld
[r
].opnum
,
6271 /* We check reload_reg_used to make sure we
6272 don't clobber the return register. */
6273 && ! TEST_HARD_REG_BIT (reload_reg_used
, regnum
)
6274 && free_for_value_p (regnum
, rld
[r
].mode
, rld
[r
].opnum
,
6275 rld
[r
].when_needed
, rld
[r
].in
,
6277 && TEST_HARD_REG_BIT (reg_class_contents
[rclass
], regnum
)
6278 && HARD_REGNO_MODE_OK (regnum
, rld
[r
].mode
)
6279 /* Look first for regs to share, then for unshared. But
6280 don't share regs used for inherited reloads; they are
6281 the ones we want to preserve. */
6283 || (TEST_HARD_REG_BIT (reload_reg_used_at_all
,
6285 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit
,
6288 int nr
= hard_regno_nregs
[regnum
][rld
[r
].mode
];
6290 /* During the second pass we want to avoid reload registers
6291 which are "bad" for this reload. */
6293 && ira_bad_reload_regno (regnum
, rld
[r
].in
, rld
[r
].out
))
6296 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
6297 (on 68000) got us two FP regs. If NR is 1,
6298 we would reject both of them. */
6301 /* If we need only one reg, we have already won. */
6304 /* But reject a single reg if we demand a group. */
6309 /* Otherwise check that as many consecutive regs as we need
6310 are available here. */
6313 int regno
= regnum
+ nr
- 1;
6314 if (!(TEST_HARD_REG_BIT (reg_class_contents
[rclass
], regno
)
6315 && spill_reg_order
[regno
] >= 0
6316 && reload_reg_free_p (regno
, rld
[r
].opnum
,
6317 rld
[r
].when_needed
)))
6326 /* If we found something on the current pass, omit later passes. */
6327 if (count
< n_spills
)
6331 /* We should have found a spill register by now. */
6332 if (count
>= n_spills
)
6335 /* I is the index in SPILL_REG_RTX of the reload register we are to
6336 allocate. Get an rtx for it and find its register number. */
6338 return set_reload_reg (i
, r
);
6341 /* Initialize all the tables needed to allocate reload registers.
6342 CHAIN is the insn currently being processed; SAVE_RELOAD_REG_RTX
6343 is the array we use to restore the reg_rtx field for every reload. */
6346 choose_reload_regs_init (struct insn_chain
*chain
, rtx
*save_reload_reg_rtx
)
6350 for (i
= 0; i
< n_reloads
; i
++)
6351 rld
[i
].reg_rtx
= save_reload_reg_rtx
[i
];
6353 memset (reload_inherited
, 0, MAX_RELOADS
);
6354 memset (reload_inheritance_insn
, 0, MAX_RELOADS
* sizeof (rtx
));
6355 memset (reload_override_in
, 0, MAX_RELOADS
* sizeof (rtx
));
6357 CLEAR_HARD_REG_SET (reload_reg_used
);
6358 CLEAR_HARD_REG_SET (reload_reg_used_at_all
);
6359 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr
);
6360 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload
);
6361 CLEAR_HARD_REG_SET (reload_reg_used_in_insn
);
6362 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr
);
6364 CLEAR_HARD_REG_SET (reg_used_in_insn
);
6367 REG_SET_TO_HARD_REG_SET (tmp
, &chain
->live_throughout
);
6368 IOR_HARD_REG_SET (reg_used_in_insn
, tmp
);
6369 REG_SET_TO_HARD_REG_SET (tmp
, &chain
->dead_or_set
);
6370 IOR_HARD_REG_SET (reg_used_in_insn
, tmp
);
6371 compute_use_by_pseudos (®_used_in_insn
, &chain
->live_throughout
);
6372 compute_use_by_pseudos (®_used_in_insn
, &chain
->dead_or_set
);
6375 for (i
= 0; i
< reload_n_operands
; i
++)
6377 CLEAR_HARD_REG_SET (reload_reg_used_in_output
[i
]);
6378 CLEAR_HARD_REG_SET (reload_reg_used_in_input
[i
]);
6379 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr
[i
]);
6380 CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr
[i
]);
6381 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr
[i
]);
6382 CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr
[i
]);
6385 COMPL_HARD_REG_SET (reload_reg_unavailable
, chain
->used_spill_regs
);
6387 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit
);
6389 for (i
= 0; i
< n_reloads
; i
++)
6390 /* If we have already decided to use a certain register,
6391 don't use it in another way. */
6393 mark_reload_reg_in_use (REGNO (rld
[i
].reg_rtx
), rld
[i
].opnum
,
6394 rld
[i
].when_needed
, rld
[i
].mode
);
6397 #ifdef SECONDARY_MEMORY_NEEDED
6398 /* If X is not a subreg, return it unmodified. If it is a subreg,
6399 look up whether we made a replacement for the SUBREG_REG. Return
6400 either the replacement or the SUBREG_REG. */
6403 replaced_subreg (rtx x
)
6405 if (GET_CODE (x
) == SUBREG
)
6406 return find_replacement (&SUBREG_REG (x
));
6411 /* Compute the offset to pass to subreg_regno_offset, for a pseudo of
6412 mode OUTERMODE that is available in a hard reg of mode INNERMODE.
6413 SUBREG is non-NULL if the pseudo is a subreg whose reg is a pseudo,
6414 otherwise it is NULL. */
6417 compute_reload_subreg_offset (enum machine_mode outermode
,
6419 enum machine_mode innermode
)
6422 enum machine_mode middlemode
;
6425 return subreg_lowpart_offset (outermode
, innermode
);
6427 outer_offset
= SUBREG_BYTE (subreg
);
6428 middlemode
= GET_MODE (SUBREG_REG (subreg
));
6430 /* If SUBREG is paradoxical then return the normal lowpart offset
6431 for OUTERMODE and INNERMODE. Our caller has already checked
6432 that OUTERMODE fits in INNERMODE. */
6433 if (outer_offset
== 0
6434 && GET_MODE_SIZE (outermode
) > GET_MODE_SIZE (middlemode
))
6435 return subreg_lowpart_offset (outermode
, innermode
);
6437 /* SUBREG is normal, but may not be lowpart; return OUTER_OFFSET
6438 plus the normal lowpart offset for MIDDLEMODE and INNERMODE. */
6439 return outer_offset
+ subreg_lowpart_offset (middlemode
, innermode
);
6442 /* Assign hard reg targets for the pseudo-registers we must reload
6443 into hard regs for this insn.
6444 Also output the instructions to copy them in and out of the hard regs.
6446 For machines with register classes, we are responsible for
6447 finding a reload reg in the proper class. */
6450 choose_reload_regs (struct insn_chain
*chain
)
6452 rtx_insn
*insn
= chain
->insn
;
6454 unsigned int max_group_size
= 1;
6455 enum reg_class group_class
= NO_REGS
;
6456 int pass
, win
, inheritance
;
6458 rtx save_reload_reg_rtx
[MAX_RELOADS
];
6460 /* In order to be certain of getting the registers we need,
6461 we must sort the reloads into order of increasing register class.
6462 Then our grabbing of reload registers will parallel the process
6463 that provided the reload registers.
6465 Also note whether any of the reloads wants a consecutive group of regs.
6466 If so, record the maximum size of the group desired and what
6467 register class contains all the groups needed by this insn. */
6469 for (j
= 0; j
< n_reloads
; j
++)
6471 reload_order
[j
] = j
;
6472 if (rld
[j
].reg_rtx
!= NULL_RTX
)
6474 gcc_assert (REG_P (rld
[j
].reg_rtx
)
6475 && HARD_REGISTER_P (rld
[j
].reg_rtx
));
6476 reload_spill_index
[j
] = REGNO (rld
[j
].reg_rtx
);
6479 reload_spill_index
[j
] = -1;
6481 if (rld
[j
].nregs
> 1)
6483 max_group_size
= MAX (rld
[j
].nregs
, max_group_size
);
6485 = reg_class_superunion
[(int) rld
[j
].rclass
][(int) group_class
];
6488 save_reload_reg_rtx
[j
] = rld
[j
].reg_rtx
;
6492 qsort (reload_order
, n_reloads
, sizeof (short), reload_reg_class_lower
);
6494 /* If -O, try first with inheritance, then turning it off.
6495 If not -O, don't do inheritance.
6496 Using inheritance when not optimizing leads to paradoxes
6497 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
6498 because one side of the comparison might be inherited. */
6500 for (inheritance
= optimize
> 0; inheritance
>= 0; inheritance
--)
6502 choose_reload_regs_init (chain
, save_reload_reg_rtx
);
6504 /* Process the reloads in order of preference just found.
6505 Beyond this point, subregs can be found in reload_reg_rtx.
6507 This used to look for an existing reloaded home for all of the
6508 reloads, and only then perform any new reloads. But that could lose
6509 if the reloads were done out of reg-class order because a later
6510 reload with a looser constraint might have an old home in a register
6511 needed by an earlier reload with a tighter constraint.
6513 To solve this, we make two passes over the reloads, in the order
6514 described above. In the first pass we try to inherit a reload
6515 from a previous insn. If there is a later reload that needs a
6516 class that is a proper subset of the class being processed, we must
6517 also allocate a spill register during the first pass.
6519 Then make a second pass over the reloads to allocate any reloads
6520 that haven't been given registers yet. */
6522 for (j
= 0; j
< n_reloads
; j
++)
6524 int r
= reload_order
[j
];
6525 rtx search_equiv
= NULL_RTX
;
6527 /* Ignore reloads that got marked inoperative. */
6528 if (rld
[r
].out
== 0 && rld
[r
].in
== 0
6529 && ! rld
[r
].secondary_p
)
6532 /* If find_reloads chose to use reload_in or reload_out as a reload
6533 register, we don't need to chose one. Otherwise, try even if it
6534 found one since we might save an insn if we find the value lying
6536 Try also when reload_in is a pseudo without a hard reg. */
6537 if (rld
[r
].in
!= 0 && rld
[r
].reg_rtx
!= 0
6538 && (rtx_equal_p (rld
[r
].in
, rld
[r
].reg_rtx
)
6539 || (rtx_equal_p (rld
[r
].out
, rld
[r
].reg_rtx
)
6540 && !MEM_P (rld
[r
].in
)
6541 && true_regnum (rld
[r
].in
) < FIRST_PSEUDO_REGISTER
)))
6544 #if 0 /* No longer needed for correct operation.
6545 It might give better code, or might not; worth an experiment? */
6546 /* If this is an optional reload, we can't inherit from earlier insns
6547 until we are sure that any non-optional reloads have been allocated.
6548 The following code takes advantage of the fact that optional reloads
6549 are at the end of reload_order. */
6550 if (rld
[r
].optional
!= 0)
6551 for (i
= 0; i
< j
; i
++)
6552 if ((rld
[reload_order
[i
]].out
!= 0
6553 || rld
[reload_order
[i
]].in
!= 0
6554 || rld
[reload_order
[i
]].secondary_p
)
6555 && ! rld
[reload_order
[i
]].optional
6556 && rld
[reload_order
[i
]].reg_rtx
== 0)
6557 allocate_reload_reg (chain
, reload_order
[i
], 0);
6560 /* First see if this pseudo is already available as reloaded
6561 for a previous insn. We cannot try to inherit for reloads
6562 that are smaller than the maximum number of registers needed
6563 for groups unless the register we would allocate cannot be used
6566 We could check here to see if this is a secondary reload for
6567 an object that is already in a register of the desired class.
6568 This would avoid the need for the secondary reload register.
6569 But this is complex because we can't easily determine what
6570 objects might want to be loaded via this reload. So let a
6571 register be allocated here. In `emit_reload_insns' we suppress
6572 one of the loads in the case described above. */
6578 enum machine_mode mode
= VOIDmode
;
6579 rtx subreg
= NULL_RTX
;
6583 else if (REG_P (rld
[r
].in
))
6585 regno
= REGNO (rld
[r
].in
);
6586 mode
= GET_MODE (rld
[r
].in
);
6588 else if (REG_P (rld
[r
].in_reg
))
6590 regno
= REGNO (rld
[r
].in_reg
);
6591 mode
= GET_MODE (rld
[r
].in_reg
);
6593 else if (GET_CODE (rld
[r
].in_reg
) == SUBREG
6594 && REG_P (SUBREG_REG (rld
[r
].in_reg
)))
6596 regno
= REGNO (SUBREG_REG (rld
[r
].in_reg
));
6597 if (regno
< FIRST_PSEUDO_REGISTER
)
6598 regno
= subreg_regno (rld
[r
].in_reg
);
6601 subreg
= rld
[r
].in_reg
;
6602 byte
= SUBREG_BYTE (subreg
);
6604 mode
= GET_MODE (rld
[r
].in_reg
);
6607 else if (GET_RTX_CLASS (GET_CODE (rld
[r
].in_reg
)) == RTX_AUTOINC
6608 && REG_P (XEXP (rld
[r
].in_reg
, 0)))
6610 regno
= REGNO (XEXP (rld
[r
].in_reg
, 0));
6611 mode
= GET_MODE (XEXP (rld
[r
].in_reg
, 0));
6612 rld
[r
].out
= rld
[r
].in
;
6616 /* This won't work, since REGNO can be a pseudo reg number.
6617 Also, it takes much more hair to keep track of all the things
6618 that can invalidate an inherited reload of part of a pseudoreg. */
6619 else if (GET_CODE (rld
[r
].in
) == SUBREG
6620 && REG_P (SUBREG_REG (rld
[r
].in
)))
6621 regno
= subreg_regno (rld
[r
].in
);
6625 && reg_last_reload_reg
[regno
] != 0
6626 && (GET_MODE_SIZE (GET_MODE (reg_last_reload_reg
[regno
]))
6627 >= GET_MODE_SIZE (mode
) + byte
)
6628 #ifdef CANNOT_CHANGE_MODE_CLASS
6629 /* Verify that the register it's in can be used in
6631 && !REG_CANNOT_CHANGE_MODE_P (REGNO (reg_last_reload_reg
[regno
]),
6632 GET_MODE (reg_last_reload_reg
[regno
]),
6637 enum reg_class rclass
= rld
[r
].rclass
, last_class
;
6638 rtx last_reg
= reg_last_reload_reg
[regno
];
6640 i
= REGNO (last_reg
);
6641 byte
= compute_reload_subreg_offset (mode
,
6643 GET_MODE (last_reg
));
6644 i
+= subreg_regno_offset (i
, GET_MODE (last_reg
), byte
, mode
);
6645 last_class
= REGNO_REG_CLASS (i
);
6647 if (reg_reloaded_contents
[i
] == regno
6648 && TEST_HARD_REG_BIT (reg_reloaded_valid
, i
)
6649 && HARD_REGNO_MODE_OK (i
, rld
[r
].mode
)
6650 && (TEST_HARD_REG_BIT (reg_class_contents
[(int) rclass
], i
)
6651 /* Even if we can't use this register as a reload
6652 register, we might use it for reload_override_in,
6653 if copying it to the desired class is cheap
6655 || ((register_move_cost (mode
, last_class
, rclass
)
6656 < memory_move_cost (mode
, rclass
, true))
6657 && (secondary_reload_class (1, rclass
, mode
,
6660 #ifdef SECONDARY_MEMORY_NEEDED
6661 && ! SECONDARY_MEMORY_NEEDED (last_class
, rclass
,
6666 && (rld
[r
].nregs
== max_group_size
6667 || ! TEST_HARD_REG_BIT (reg_class_contents
[(int) group_class
],
6669 && free_for_value_p (i
, rld
[r
].mode
, rld
[r
].opnum
,
6670 rld
[r
].when_needed
, rld
[r
].in
,
6673 /* If a group is needed, verify that all the subsequent
6674 registers still have their values intact. */
6675 int nr
= hard_regno_nregs
[i
][rld
[r
].mode
];
6678 for (k
= 1; k
< nr
; k
++)
6679 if (reg_reloaded_contents
[i
+ k
] != regno
6680 || ! TEST_HARD_REG_BIT (reg_reloaded_valid
, i
+ k
))
6688 last_reg
= (GET_MODE (last_reg
) == mode
6689 ? last_reg
: gen_rtx_REG (mode
, i
));
6692 for (k
= 0; k
< nr
; k
++)
6693 bad_for_class
|= ! TEST_HARD_REG_BIT (reg_class_contents
[(int) rld
[r
].rclass
],
6696 /* We found a register that contains the
6697 value we need. If this register is the
6698 same as an `earlyclobber' operand of the
6699 current insn, just mark it as a place to
6700 reload from since we can't use it as the
6701 reload register itself. */
6703 for (i1
= 0; i1
< n_earlyclobbers
; i1
++)
6704 if (reg_overlap_mentioned_for_reload_p
6705 (reg_last_reload_reg
[regno
],
6706 reload_earlyclobbers
[i1
]))
6709 if (i1
!= n_earlyclobbers
6710 || ! (free_for_value_p (i
, rld
[r
].mode
,
6712 rld
[r
].when_needed
, rld
[r
].in
,
6714 /* Don't use it if we'd clobber a pseudo reg. */
6715 || (TEST_HARD_REG_BIT (reg_used_in_insn
, i
)
6717 && ! TEST_HARD_REG_BIT (reg_reloaded_dead
, i
))
6718 /* Don't clobber the frame pointer. */
6719 || (i
== HARD_FRAME_POINTER_REGNUM
6720 && frame_pointer_needed
6722 /* Don't really use the inherited spill reg
6723 if we need it wider than we've got it. */
6724 || (GET_MODE_SIZE (rld
[r
].mode
)
6725 > GET_MODE_SIZE (mode
))
6728 /* If find_reloads chose reload_out as reload
6729 register, stay with it - that leaves the
6730 inherited register for subsequent reloads. */
6731 || (rld
[r
].out
&& rld
[r
].reg_rtx
6732 && rtx_equal_p (rld
[r
].out
, rld
[r
].reg_rtx
)))
6734 if (! rld
[r
].optional
)
6736 reload_override_in
[r
] = last_reg
;
6737 reload_inheritance_insn
[r
]
6738 = reg_reloaded_insn
[i
];
6744 /* We can use this as a reload reg. */
6745 /* Mark the register as in use for this part of
6747 mark_reload_reg_in_use (i
,
6751 rld
[r
].reg_rtx
= last_reg
;
6752 reload_inherited
[r
] = 1;
6753 reload_inheritance_insn
[r
]
6754 = reg_reloaded_insn
[i
];
6755 reload_spill_index
[r
] = i
;
6756 for (k
= 0; k
< nr
; k
++)
6757 SET_HARD_REG_BIT (reload_reg_used_for_inherit
,
6765 /* Here's another way to see if the value is already lying around. */
6768 && ! reload_inherited
[r
]
6770 && (CONSTANT_P (rld
[r
].in
)
6771 || GET_CODE (rld
[r
].in
) == PLUS
6772 || REG_P (rld
[r
].in
)
6773 || MEM_P (rld
[r
].in
))
6774 && (rld
[r
].nregs
== max_group_size
6775 || ! reg_classes_intersect_p (rld
[r
].rclass
, group_class
)))
6776 search_equiv
= rld
[r
].in
;
6781 = find_equiv_reg (search_equiv
, insn
, rld
[r
].rclass
,
6782 -1, NULL
, 0, rld
[r
].mode
);
6788 regno
= REGNO (equiv
);
6791 /* This must be a SUBREG of a hard register.
6792 Make a new REG since this might be used in an
6793 address and not all machines support SUBREGs
6795 gcc_assert (GET_CODE (equiv
) == SUBREG
);
6796 regno
= subreg_regno (equiv
);
6797 equiv
= gen_rtx_REG (rld
[r
].mode
, regno
);
6798 /* If we choose EQUIV as the reload register, but the
6799 loop below decides to cancel the inheritance, we'll
6800 end up reloading EQUIV in rld[r].mode, not the mode
6801 it had originally. That isn't safe when EQUIV isn't
6802 available as a spill register since its value might
6803 still be live at this point. */
6804 for (i
= regno
; i
< regno
+ (int) rld
[r
].nregs
; i
++)
6805 if (TEST_HARD_REG_BIT (reload_reg_unavailable
, i
))
6810 /* If we found a spill reg, reject it unless it is free
6811 and of the desired class. */
6815 int bad_for_class
= 0;
6816 int max_regno
= regno
+ rld
[r
].nregs
;
6818 for (i
= regno
; i
< max_regno
; i
++)
6820 regs_used
|= TEST_HARD_REG_BIT (reload_reg_used_at_all
,
6822 bad_for_class
|= ! TEST_HARD_REG_BIT (reg_class_contents
[(int) rld
[r
].rclass
],
6827 && ! free_for_value_p (regno
, rld
[r
].mode
,
6828 rld
[r
].opnum
, rld
[r
].when_needed
,
6829 rld
[r
].in
, rld
[r
].out
, r
, 1))
6834 if (equiv
!= 0 && ! HARD_REGNO_MODE_OK (regno
, rld
[r
].mode
))
6837 /* We found a register that contains the value we need.
6838 If this register is the same as an `earlyclobber' operand
6839 of the current insn, just mark it as a place to reload from
6840 since we can't use it as the reload register itself. */
6843 for (i
= 0; i
< n_earlyclobbers
; i
++)
6844 if (reg_overlap_mentioned_for_reload_p (equiv
,
6845 reload_earlyclobbers
[i
]))
6847 if (! rld
[r
].optional
)
6848 reload_override_in
[r
] = equiv
;
6853 /* If the equiv register we have found is explicitly clobbered
6854 in the current insn, it depends on the reload type if we
6855 can use it, use it for reload_override_in, or not at all.
6856 In particular, we then can't use EQUIV for a
6857 RELOAD_FOR_OUTPUT_ADDRESS reload. */
6861 if (regno_clobbered_p (regno
, insn
, rld
[r
].mode
, 2))
6862 switch (rld
[r
].when_needed
)
6864 case RELOAD_FOR_OTHER_ADDRESS
:
6865 case RELOAD_FOR_INPADDR_ADDRESS
:
6866 case RELOAD_FOR_INPUT_ADDRESS
:
6867 case RELOAD_FOR_OPADDR_ADDR
:
6870 case RELOAD_FOR_INPUT
:
6871 case RELOAD_FOR_OPERAND_ADDRESS
:
6872 if (! rld
[r
].optional
)
6873 reload_override_in
[r
] = equiv
;
6879 else if (regno_clobbered_p (regno
, insn
, rld
[r
].mode
, 1))
6880 switch (rld
[r
].when_needed
)
6882 case RELOAD_FOR_OTHER_ADDRESS
:
6883 case RELOAD_FOR_INPADDR_ADDRESS
:
6884 case RELOAD_FOR_INPUT_ADDRESS
:
6885 case RELOAD_FOR_OPADDR_ADDR
:
6886 case RELOAD_FOR_OPERAND_ADDRESS
:
6887 case RELOAD_FOR_INPUT
:
6890 if (! rld
[r
].optional
)
6891 reload_override_in
[r
] = equiv
;
6899 /* If we found an equivalent reg, say no code need be generated
6900 to load it, and use it as our reload reg. */
6902 && (regno
!= HARD_FRAME_POINTER_REGNUM
6903 || !frame_pointer_needed
))
6905 int nr
= hard_regno_nregs
[regno
][rld
[r
].mode
];
6907 rld
[r
].reg_rtx
= equiv
;
6908 reload_spill_index
[r
] = regno
;
6909 reload_inherited
[r
] = 1;
6911 /* If reg_reloaded_valid is not set for this register,
6912 there might be a stale spill_reg_store lying around.
6913 We must clear it, since otherwise emit_reload_insns
6914 might delete the store. */
6915 if (! TEST_HARD_REG_BIT (reg_reloaded_valid
, regno
))
6916 spill_reg_store
[regno
] = NULL
;
6917 /* If any of the hard registers in EQUIV are spill
6918 registers, mark them as in use for this insn. */
6919 for (k
= 0; k
< nr
; k
++)
6921 i
= spill_reg_order
[regno
+ k
];
6924 mark_reload_reg_in_use (regno
, rld
[r
].opnum
,
6927 SET_HARD_REG_BIT (reload_reg_used_for_inherit
,
6934 /* If we found a register to use already, or if this is an optional
6935 reload, we are done. */
6936 if (rld
[r
].reg_rtx
!= 0 || rld
[r
].optional
!= 0)
6940 /* No longer needed for correct operation. Might or might
6941 not give better code on the average. Want to experiment? */
6943 /* See if there is a later reload that has a class different from our
6944 class that intersects our class or that requires less register
6945 than our reload. If so, we must allocate a register to this
6946 reload now, since that reload might inherit a previous reload
6947 and take the only available register in our class. Don't do this
6948 for optional reloads since they will force all previous reloads
6949 to be allocated. Also don't do this for reloads that have been
6952 for (i
= j
+ 1; i
< n_reloads
; i
++)
6954 int s
= reload_order
[i
];
6956 if ((rld
[s
].in
== 0 && rld
[s
].out
== 0
6957 && ! rld
[s
].secondary_p
)
6961 if ((rld
[s
].rclass
!= rld
[r
].rclass
6962 && reg_classes_intersect_p (rld
[r
].rclass
,
6964 || rld
[s
].nregs
< rld
[r
].nregs
)
6971 allocate_reload_reg (chain
, r
, j
== n_reloads
- 1);
6975 /* Now allocate reload registers for anything non-optional that
6976 didn't get one yet. */
6977 for (j
= 0; j
< n_reloads
; j
++)
6979 int r
= reload_order
[j
];
6981 /* Ignore reloads that got marked inoperative. */
6982 if (rld
[r
].out
== 0 && rld
[r
].in
== 0 && ! rld
[r
].secondary_p
)
6985 /* Skip reloads that already have a register allocated or are
6987 if (rld
[r
].reg_rtx
!= 0 || rld
[r
].optional
)
6990 if (! allocate_reload_reg (chain
, r
, j
== n_reloads
- 1))
6994 /* If that loop got all the way, we have won. */
7001 /* Loop around and try without any inheritance. */
7006 /* First undo everything done by the failed attempt
7007 to allocate with inheritance. */
7008 choose_reload_regs_init (chain
, save_reload_reg_rtx
);
7010 /* Some sanity tests to verify that the reloads found in the first
7011 pass are identical to the ones we have now. */
7012 gcc_assert (chain
->n_reloads
== n_reloads
);
7014 for (i
= 0; i
< n_reloads
; i
++)
7016 if (chain
->rld
[i
].regno
< 0 || chain
->rld
[i
].reg_rtx
!= 0)
7018 gcc_assert (chain
->rld
[i
].when_needed
== rld
[i
].when_needed
);
7019 for (j
= 0; j
< n_spills
; j
++)
7020 if (spill_regs
[j
] == chain
->rld
[i
].regno
)
7021 if (! set_reload_reg (j
, i
))
7022 failed_reload (chain
->insn
, i
);
7026 /* If we thought we could inherit a reload, because it seemed that
7027 nothing else wanted the same reload register earlier in the insn,
7028 verify that assumption, now that all reloads have been assigned.
7029 Likewise for reloads where reload_override_in has been set. */
7031 /* If doing expensive optimizations, do one preliminary pass that doesn't
7032 cancel any inheritance, but removes reloads that have been needed only
7033 for reloads that we know can be inherited. */
7034 for (pass
= flag_expensive_optimizations
; pass
>= 0; pass
--)
7036 for (j
= 0; j
< n_reloads
; j
++)
7038 int r
= reload_order
[j
];
7040 #ifdef SECONDARY_MEMORY_NEEDED
7043 if (reload_inherited
[r
] && rld
[r
].reg_rtx
)
7044 check_reg
= rld
[r
].reg_rtx
;
7045 else if (reload_override_in
[r
]
7046 && (REG_P (reload_override_in
[r
])
7047 || GET_CODE (reload_override_in
[r
]) == SUBREG
))
7048 check_reg
= reload_override_in
[r
];
7051 if (! free_for_value_p (true_regnum (check_reg
), rld
[r
].mode
,
7052 rld
[r
].opnum
, rld
[r
].when_needed
, rld
[r
].in
,
7053 (reload_inherited
[r
]
7054 ? rld
[r
].out
: const0_rtx
),
7059 reload_inherited
[r
] = 0;
7060 reload_override_in
[r
] = 0;
7062 /* If we can inherit a RELOAD_FOR_INPUT, or can use a
7063 reload_override_in, then we do not need its related
7064 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads;
7065 likewise for other reload types.
7066 We handle this by removing a reload when its only replacement
7067 is mentioned in reload_in of the reload we are going to inherit.
7068 A special case are auto_inc expressions; even if the input is
7069 inherited, we still need the address for the output. We can
7070 recognize them because they have RELOAD_OUT set to RELOAD_IN.
7071 If we succeeded removing some reload and we are doing a preliminary
7072 pass just to remove such reloads, make another pass, since the
7073 removal of one reload might allow us to inherit another one. */
7075 && rld
[r
].out
!= rld
[r
].in
7076 && remove_address_replacements (rld
[r
].in
))
7081 #ifdef SECONDARY_MEMORY_NEEDED
7082 /* If we needed a memory location for the reload, we also have to
7083 remove its related reloads. */
7085 && rld
[r
].out
!= rld
[r
].in
7086 && (tem
= replaced_subreg (rld
[r
].in
), REG_P (tem
))
7087 && REGNO (tem
) < FIRST_PSEUDO_REGISTER
7088 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (REGNO (tem
)),
7089 rld
[r
].rclass
, rld
[r
].inmode
)
7090 && remove_address_replacements
7091 (get_secondary_mem (tem
, rld
[r
].inmode
, rld
[r
].opnum
,
7092 rld
[r
].when_needed
)))
7101 /* Now that reload_override_in is known valid,
7102 actually override reload_in. */
7103 for (j
= 0; j
< n_reloads
; j
++)
7104 if (reload_override_in
[j
])
7105 rld
[j
].in
= reload_override_in
[j
];
7107 /* If this reload won't be done because it has been canceled or is
7108 optional and not inherited, clear reload_reg_rtx so other
7109 routines (such as subst_reloads) don't get confused. */
7110 for (j
= 0; j
< n_reloads
; j
++)
7111 if (rld
[j
].reg_rtx
!= 0
7112 && ((rld
[j
].optional
&& ! reload_inherited
[j
])
7113 || (rld
[j
].in
== 0 && rld
[j
].out
== 0
7114 && ! rld
[j
].secondary_p
)))
7116 int regno
= true_regnum (rld
[j
].reg_rtx
);
7118 if (spill_reg_order
[regno
] >= 0)
7119 clear_reload_reg_in_use (regno
, rld
[j
].opnum
,
7120 rld
[j
].when_needed
, rld
[j
].mode
);
7122 reload_spill_index
[j
] = -1;
7125 /* Record which pseudos and which spill regs have output reloads. */
7126 for (j
= 0; j
< n_reloads
; j
++)
7128 int r
= reload_order
[j
];
7130 i
= reload_spill_index
[r
];
7132 /* I is nonneg if this reload uses a register.
7133 If rld[r].reg_rtx is 0, this is an optional reload
7134 that we opted to ignore. */
7135 if (rld
[r
].out_reg
!= 0 && REG_P (rld
[r
].out_reg
)
7136 && rld
[r
].reg_rtx
!= 0)
7138 int nregno
= REGNO (rld
[r
].out_reg
);
7141 if (nregno
< FIRST_PSEUDO_REGISTER
)
7142 nr
= hard_regno_nregs
[nregno
][rld
[r
].mode
];
7145 SET_REGNO_REG_SET (®_has_output_reload
,
7149 add_to_hard_reg_set (®_is_output_reload
, rld
[r
].mode
, i
);
7151 gcc_assert (rld
[r
].when_needed
== RELOAD_OTHER
7152 || rld
[r
].when_needed
== RELOAD_FOR_OUTPUT
7153 || rld
[r
].when_needed
== RELOAD_FOR_INSN
);
7158 /* Deallocate the reload register for reload R. This is called from
7159 remove_address_replacements. */
7162 deallocate_reload_reg (int r
)
7166 if (! rld
[r
].reg_rtx
)
7168 regno
= true_regnum (rld
[r
].reg_rtx
);
7170 if (spill_reg_order
[regno
] >= 0)
7171 clear_reload_reg_in_use (regno
, rld
[r
].opnum
, rld
[r
].when_needed
,
7173 reload_spill_index
[r
] = -1;
7176 /* These arrays are filled by emit_reload_insns and its subroutines. */
7177 static rtx_insn
*input_reload_insns
[MAX_RECOG_OPERANDS
];
7178 static rtx_insn
*other_input_address_reload_insns
= 0;
7179 static rtx_insn
*other_input_reload_insns
= 0;
7180 static rtx_insn
*input_address_reload_insns
[MAX_RECOG_OPERANDS
];
7181 static rtx_insn
*inpaddr_address_reload_insns
[MAX_RECOG_OPERANDS
];
7182 static rtx_insn
*output_reload_insns
[MAX_RECOG_OPERANDS
];
7183 static rtx_insn
*output_address_reload_insns
[MAX_RECOG_OPERANDS
];
7184 static rtx_insn
*outaddr_address_reload_insns
[MAX_RECOG_OPERANDS
];
7185 static rtx_insn
*operand_reload_insns
= 0;
7186 static rtx_insn
*other_operand_reload_insns
= 0;
7187 static rtx_insn
*other_output_reload_insns
[MAX_RECOG_OPERANDS
];
7189 /* Values to be put in spill_reg_store are put here first. Instructions
7190 must only be placed here if the associated reload register reaches
7191 the end of the instruction's reload sequence. */
7192 static rtx_insn
*new_spill_reg_store
[FIRST_PSEUDO_REGISTER
];
7193 static HARD_REG_SET reg_reloaded_died
;
7195 /* Check if *RELOAD_REG is suitable as an intermediate or scratch register
7196 of class NEW_CLASS with mode NEW_MODE. Or alternatively, if alt_reload_reg
7197 is nonzero, if that is suitable. On success, change *RELOAD_REG to the
7198 adjusted register, and return true. Otherwise, return false. */
7200 reload_adjust_reg_for_temp (rtx
*reload_reg
, rtx alt_reload_reg
,
7201 enum reg_class new_class
,
7202 enum machine_mode new_mode
)
7207 for (reg
= *reload_reg
; reg
; reg
= alt_reload_reg
, alt_reload_reg
= 0)
7209 unsigned regno
= REGNO (reg
);
7211 if (!TEST_HARD_REG_BIT (reg_class_contents
[(int) new_class
], regno
))
7213 if (GET_MODE (reg
) != new_mode
)
7215 if (!HARD_REGNO_MODE_OK (regno
, new_mode
))
7217 if (hard_regno_nregs
[regno
][new_mode
]
7218 > hard_regno_nregs
[regno
][GET_MODE (reg
)])
7220 reg
= reload_adjust_reg_for_mode (reg
, new_mode
);
7228 /* Check if *RELOAD_REG is suitable as a scratch register for the reload
7229 pattern with insn_code ICODE, or alternatively, if alt_reload_reg is
7230 nonzero, if that is suitable. On success, change *RELOAD_REG to the
7231 adjusted register, and return true. Otherwise, return false. */
7233 reload_adjust_reg_for_icode (rtx
*reload_reg
, rtx alt_reload_reg
,
7234 enum insn_code icode
)
7237 enum reg_class new_class
= scratch_reload_class (icode
);
7238 enum machine_mode new_mode
= insn_data
[(int) icode
].operand
[2].mode
;
7240 return reload_adjust_reg_for_temp (reload_reg
, alt_reload_reg
,
7241 new_class
, new_mode
);
7244 /* Generate insns to perform reload RL, which is for the insn in CHAIN and
7245 has the number J. OLD contains the value to be used as input. */
7248 emit_input_reload_insns (struct insn_chain
*chain
, struct reload
*rl
,
7251 rtx_insn
*insn
= chain
->insn
;
7253 rtx oldequiv_reg
= 0;
7256 enum machine_mode mode
;
7259 /* delete_output_reload is only invoked properly if old contains
7260 the original pseudo register. Since this is replaced with a
7261 hard reg when RELOAD_OVERRIDE_IN is set, see if we can
7262 find the pseudo in RELOAD_IN_REG. This is also used to
7263 determine whether a secondary reload is needed. */
7264 if (reload_override_in
[j
]
7265 && (REG_P (rl
->in_reg
)
7266 || (GET_CODE (rl
->in_reg
) == SUBREG
7267 && REG_P (SUBREG_REG (rl
->in_reg
)))))
7274 else if (REG_P (oldequiv
))
7275 oldequiv_reg
= oldequiv
;
7276 else if (GET_CODE (oldequiv
) == SUBREG
)
7277 oldequiv_reg
= SUBREG_REG (oldequiv
);
7279 reloadreg
= reload_reg_rtx_for_input
[j
];
7280 mode
= GET_MODE (reloadreg
);
7282 /* If we are reloading from a register that was recently stored in
7283 with an output-reload, see if we can prove there was
7284 actually no need to store the old value in it. */
7286 if (optimize
&& REG_P (oldequiv
)
7287 && REGNO (oldequiv
) < FIRST_PSEUDO_REGISTER
7288 && spill_reg_store
[REGNO (oldequiv
)]
7290 && (dead_or_set_p (insn
, spill_reg_stored_to
[REGNO (oldequiv
)])
7291 || rtx_equal_p (spill_reg_stored_to
[REGNO (oldequiv
)],
7293 delete_output_reload (insn
, j
, REGNO (oldequiv
), reloadreg
);
7295 /* Encapsulate OLDEQUIV into the reload mode, then load RELOADREG from
7298 while (GET_CODE (oldequiv
) == SUBREG
&& GET_MODE (oldequiv
) != mode
)
7299 oldequiv
= SUBREG_REG (oldequiv
);
7300 if (GET_MODE (oldequiv
) != VOIDmode
7301 && mode
!= GET_MODE (oldequiv
))
7302 oldequiv
= gen_lowpart_SUBREG (mode
, oldequiv
);
7304 /* Switch to the right place to emit the reload insns. */
7305 switch (rl
->when_needed
)
7308 where
= &other_input_reload_insns
;
7310 case RELOAD_FOR_INPUT
:
7311 where
= &input_reload_insns
[rl
->opnum
];
7313 case RELOAD_FOR_INPUT_ADDRESS
:
7314 where
= &input_address_reload_insns
[rl
->opnum
];
7316 case RELOAD_FOR_INPADDR_ADDRESS
:
7317 where
= &inpaddr_address_reload_insns
[rl
->opnum
];
7319 case RELOAD_FOR_OUTPUT_ADDRESS
:
7320 where
= &output_address_reload_insns
[rl
->opnum
];
7322 case RELOAD_FOR_OUTADDR_ADDRESS
:
7323 where
= &outaddr_address_reload_insns
[rl
->opnum
];
7325 case RELOAD_FOR_OPERAND_ADDRESS
:
7326 where
= &operand_reload_insns
;
7328 case RELOAD_FOR_OPADDR_ADDR
:
7329 where
= &other_operand_reload_insns
;
7331 case RELOAD_FOR_OTHER_ADDRESS
:
7332 where
= &other_input_address_reload_insns
;
7338 push_to_sequence (*where
);
7340 /* Auto-increment addresses must be reloaded in a special way. */
7341 if (rl
->out
&& ! rl
->out_reg
)
7343 /* We are not going to bother supporting the case where a
7344 incremented register can't be copied directly from
7345 OLDEQUIV since this seems highly unlikely. */
7346 gcc_assert (rl
->secondary_in_reload
< 0);
7348 if (reload_inherited
[j
])
7349 oldequiv
= reloadreg
;
7351 old
= XEXP (rl
->in_reg
, 0);
7353 /* Prevent normal processing of this reload. */
7355 /* Output a special code sequence for this case. */
7356 inc_for_reload (reloadreg
, oldequiv
, rl
->out
, rl
->inc
);
7359 /* If we are reloading a pseudo-register that was set by the previous
7360 insn, see if we can get rid of that pseudo-register entirely
7361 by redirecting the previous insn into our reload register. */
7363 else if (optimize
&& REG_P (old
)
7364 && REGNO (old
) >= FIRST_PSEUDO_REGISTER
7365 && dead_or_set_p (insn
, old
)
7366 /* This is unsafe if some other reload
7367 uses the same reg first. */
7368 && ! conflicts_with_override (reloadreg
)
7369 && free_for_value_p (REGNO (reloadreg
), rl
->mode
, rl
->opnum
,
7370 rl
->when_needed
, old
, rl
->out
, j
, 0))
7372 rtx_insn
*temp
= PREV_INSN (insn
);
7373 while (temp
&& (NOTE_P (temp
) || DEBUG_INSN_P (temp
)))
7374 temp
= PREV_INSN (temp
);
7376 && NONJUMP_INSN_P (temp
)
7377 && GET_CODE (PATTERN (temp
)) == SET
7378 && SET_DEST (PATTERN (temp
)) == old
7379 /* Make sure we can access insn_operand_constraint. */
7380 && asm_noperands (PATTERN (temp
)) < 0
7381 /* This is unsafe if operand occurs more than once in current
7382 insn. Perhaps some occurrences aren't reloaded. */
7383 && count_occurrences (PATTERN (insn
), old
, 0) == 1)
7385 rtx old
= SET_DEST (PATTERN (temp
));
7386 /* Store into the reload register instead of the pseudo. */
7387 SET_DEST (PATTERN (temp
)) = reloadreg
;
7389 /* Verify that resulting insn is valid.
7391 Note that we have replaced the destination of TEMP with
7392 RELOADREG. If TEMP references RELOADREG within an
7393 autoincrement addressing mode, then the resulting insn
7394 is ill-formed and we must reject this optimization. */
7395 extract_insn (temp
);
7396 if (constrain_operands (1)
7398 && ! find_reg_note (temp
, REG_INC
, reloadreg
)
7402 /* If the previous insn is an output reload, the source is
7403 a reload register, and its spill_reg_store entry will
7404 contain the previous destination. This is now
7406 if (REG_P (SET_SRC (PATTERN (temp
)))
7407 && REGNO (SET_SRC (PATTERN (temp
))) < FIRST_PSEUDO_REGISTER
)
7409 spill_reg_store
[REGNO (SET_SRC (PATTERN (temp
)))] = 0;
7410 spill_reg_stored_to
[REGNO (SET_SRC (PATTERN (temp
)))] = 0;
7413 /* If these are the only uses of the pseudo reg,
7414 pretend for GDB it lives in the reload reg we used. */
7415 if (REG_N_DEATHS (REGNO (old
)) == 1
7416 && REG_N_SETS (REGNO (old
)) == 1)
7418 reg_renumber
[REGNO (old
)] = REGNO (reloadreg
);
7419 if (ira_conflicts_p
)
7420 /* Inform IRA about the change. */
7421 ira_mark_allocation_change (REGNO (old
));
7422 alter_reg (REGNO (old
), -1, false);
7426 /* Adjust any debug insns between temp and insn. */
7427 while ((temp
= NEXT_INSN (temp
)) != insn
)
7428 if (DEBUG_INSN_P (temp
))
7429 replace_rtx (PATTERN (temp
), old
, reloadreg
);
7431 gcc_assert (NOTE_P (temp
));
7435 SET_DEST (PATTERN (temp
)) = old
;
7440 /* We can't do that, so output an insn to load RELOADREG. */
7442 /* If we have a secondary reload, pick up the secondary register
7443 and icode, if any. If OLDEQUIV and OLD are different or
7444 if this is an in-out reload, recompute whether or not we
7445 still need a secondary register and what the icode should
7446 be. If we still need a secondary register and the class or
7447 icode is different, go back to reloading from OLD if using
7448 OLDEQUIV means that we got the wrong type of register. We
7449 cannot have different class or icode due to an in-out reload
7450 because we don't make such reloads when both the input and
7451 output need secondary reload registers. */
7453 if (! special
&& rl
->secondary_in_reload
>= 0)
7455 rtx second_reload_reg
= 0;
7456 rtx third_reload_reg
= 0;
7457 int secondary_reload
= rl
->secondary_in_reload
;
7458 rtx real_oldequiv
= oldequiv
;
7461 enum insn_code icode
;
7462 enum insn_code tertiary_icode
= CODE_FOR_nothing
;
7464 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
7465 and similarly for OLD.
7466 See comments in get_secondary_reload in reload.c. */
7467 /* If it is a pseudo that cannot be replaced with its
7468 equivalent MEM, we must fall back to reload_in, which
7469 will have all the necessary substitutions registered.
7470 Likewise for a pseudo that can't be replaced with its
7471 equivalent constant.
7473 Take extra care for subregs of such pseudos. Note that
7474 we cannot use reg_equiv_mem in this case because it is
7475 not in the right mode. */
7478 if (GET_CODE (tmp
) == SUBREG
)
7479 tmp
= SUBREG_REG (tmp
);
7481 && REGNO (tmp
) >= FIRST_PSEUDO_REGISTER
7482 && (reg_equiv_memory_loc (REGNO (tmp
)) != 0
7483 || reg_equiv_constant (REGNO (tmp
)) != 0))
7485 if (! reg_equiv_mem (REGNO (tmp
))
7486 || num_not_at_initial_offset
7487 || GET_CODE (oldequiv
) == SUBREG
)
7488 real_oldequiv
= rl
->in
;
7490 real_oldequiv
= reg_equiv_mem (REGNO (tmp
));
7494 if (GET_CODE (tmp
) == SUBREG
)
7495 tmp
= SUBREG_REG (tmp
);
7497 && REGNO (tmp
) >= FIRST_PSEUDO_REGISTER
7498 && (reg_equiv_memory_loc (REGNO (tmp
)) != 0
7499 || reg_equiv_constant (REGNO (tmp
)) != 0))
7501 if (! reg_equiv_mem (REGNO (tmp
))
7502 || num_not_at_initial_offset
7503 || GET_CODE (old
) == SUBREG
)
7506 real_old
= reg_equiv_mem (REGNO (tmp
));
7509 second_reload_reg
= rld
[secondary_reload
].reg_rtx
;
7510 if (rld
[secondary_reload
].secondary_in_reload
>= 0)
7512 int tertiary_reload
= rld
[secondary_reload
].secondary_in_reload
;
7514 third_reload_reg
= rld
[tertiary_reload
].reg_rtx
;
7515 tertiary_icode
= rld
[secondary_reload
].secondary_in_icode
;
7516 /* We'd have to add more code for quartary reloads. */
7517 gcc_assert (rld
[tertiary_reload
].secondary_in_reload
< 0);
7519 icode
= rl
->secondary_in_icode
;
7521 if ((old
!= oldequiv
&& ! rtx_equal_p (old
, oldequiv
))
7522 || (rl
->in
!= 0 && rl
->out
!= 0))
7524 secondary_reload_info sri
, sri2
;
7525 enum reg_class new_class
, new_t_class
;
7527 sri
.icode
= CODE_FOR_nothing
;
7528 sri
.prev_sri
= NULL
;
7530 = (enum reg_class
) targetm
.secondary_reload (1, real_oldequiv
,
7534 if (new_class
== NO_REGS
&& sri
.icode
== CODE_FOR_nothing
)
7535 second_reload_reg
= 0;
7536 else if (new_class
== NO_REGS
)
7538 if (reload_adjust_reg_for_icode (&second_reload_reg
,
7540 (enum insn_code
) sri
.icode
))
7542 icode
= (enum insn_code
) sri
.icode
;
7543 third_reload_reg
= 0;
7548 real_oldequiv
= real_old
;
7551 else if (sri
.icode
!= CODE_FOR_nothing
)
7552 /* We currently lack a way to express this in reloads. */
7556 sri2
.icode
= CODE_FOR_nothing
;
7557 sri2
.prev_sri
= &sri
;
7559 = (enum reg_class
) targetm
.secondary_reload (1, real_oldequiv
,
7562 if (new_t_class
== NO_REGS
&& sri2
.icode
== CODE_FOR_nothing
)
7564 if (reload_adjust_reg_for_temp (&second_reload_reg
,
7568 third_reload_reg
= 0;
7569 tertiary_icode
= (enum insn_code
) sri2
.icode
;
7574 real_oldequiv
= real_old
;
7577 else if (new_t_class
== NO_REGS
&& sri2
.icode
!= CODE_FOR_nothing
)
7579 rtx intermediate
= second_reload_reg
;
7581 if (reload_adjust_reg_for_temp (&intermediate
, NULL
,
7583 && reload_adjust_reg_for_icode (&third_reload_reg
, NULL
,
7587 second_reload_reg
= intermediate
;
7588 tertiary_icode
= (enum insn_code
) sri2
.icode
;
7593 real_oldequiv
= real_old
;
7596 else if (new_t_class
!= NO_REGS
&& sri2
.icode
== CODE_FOR_nothing
)
7598 rtx intermediate
= second_reload_reg
;
7600 if (reload_adjust_reg_for_temp (&intermediate
, NULL
,
7602 && reload_adjust_reg_for_temp (&third_reload_reg
, NULL
,
7605 second_reload_reg
= intermediate
;
7606 tertiary_icode
= (enum insn_code
) sri2
.icode
;
7611 real_oldequiv
= real_old
;
7616 /* This could be handled more intelligently too. */
7618 real_oldequiv
= real_old
;
7623 /* If we still need a secondary reload register, check
7624 to see if it is being used as a scratch or intermediate
7625 register and generate code appropriately. If we need
7626 a scratch register, use REAL_OLDEQUIV since the form of
7627 the insn may depend on the actual address if it is
7630 if (second_reload_reg
)
7632 if (icode
!= CODE_FOR_nothing
)
7634 /* We'd have to add extra code to handle this case. */
7635 gcc_assert (!third_reload_reg
);
7637 emit_insn (GEN_FCN (icode
) (reloadreg
, real_oldequiv
,
7638 second_reload_reg
));
7643 /* See if we need a scratch register to load the
7644 intermediate register (a tertiary reload). */
7645 if (tertiary_icode
!= CODE_FOR_nothing
)
7647 emit_insn ((GEN_FCN (tertiary_icode
)
7648 (second_reload_reg
, real_oldequiv
,
7649 third_reload_reg
)));
7651 else if (third_reload_reg
)
7653 gen_reload (third_reload_reg
, real_oldequiv
,
7656 gen_reload (second_reload_reg
, third_reload_reg
,
7661 gen_reload (second_reload_reg
, real_oldequiv
,
7665 oldequiv
= second_reload_reg
;
7670 if (! special
&& ! rtx_equal_p (reloadreg
, oldequiv
))
7672 rtx real_oldequiv
= oldequiv
;
7674 if ((REG_P (oldequiv
)
7675 && REGNO (oldequiv
) >= FIRST_PSEUDO_REGISTER
7676 && (reg_equiv_memory_loc (REGNO (oldequiv
)) != 0
7677 || reg_equiv_constant (REGNO (oldequiv
)) != 0))
7678 || (GET_CODE (oldequiv
) == SUBREG
7679 && REG_P (SUBREG_REG (oldequiv
))
7680 && (REGNO (SUBREG_REG (oldequiv
))
7681 >= FIRST_PSEUDO_REGISTER
)
7682 && ((reg_equiv_memory_loc (REGNO (SUBREG_REG (oldequiv
))) != 0)
7683 || (reg_equiv_constant (REGNO (SUBREG_REG (oldequiv
))) != 0)))
7684 || (CONSTANT_P (oldequiv
)
7685 && (targetm
.preferred_reload_class (oldequiv
,
7686 REGNO_REG_CLASS (REGNO (reloadreg
)))
7688 real_oldequiv
= rl
->in
;
7689 gen_reload (reloadreg
, real_oldequiv
, rl
->opnum
,
7693 if (cfun
->can_throw_non_call_exceptions
)
7694 copy_reg_eh_region_note_forward (insn
, get_insns (), NULL
);
7696 /* End this sequence. */
7697 *where
= get_insns ();
7700 /* Update reload_override_in so that delete_address_reloads_1
7701 can see the actual register usage. */
7703 reload_override_in
[j
] = oldequiv
;
7706 /* Generate insns to for the output reload RL, which is for the insn described
7707 by CHAIN and has the number J. */
7709 emit_output_reload_insns (struct insn_chain
*chain
, struct reload
*rl
,
7713 rtx_insn
*insn
= chain
->insn
;
7716 enum machine_mode mode
;
7720 if (rl
->when_needed
== RELOAD_OTHER
)
7723 push_to_sequence (output_reload_insns
[rl
->opnum
]);
7725 rl_reg_rtx
= reload_reg_rtx_for_output
[j
];
7726 mode
= GET_MODE (rl_reg_rtx
);
7728 reloadreg
= rl_reg_rtx
;
7730 /* If we need two reload regs, set RELOADREG to the intermediate
7731 one, since it will be stored into OLD. We might need a secondary
7732 register only for an input reload, so check again here. */
7734 if (rl
->secondary_out_reload
>= 0)
7737 int secondary_reload
= rl
->secondary_out_reload
;
7738 int tertiary_reload
= rld
[secondary_reload
].secondary_out_reload
;
7740 if (REG_P (old
) && REGNO (old
) >= FIRST_PSEUDO_REGISTER
7741 && reg_equiv_mem (REGNO (old
)) != 0)
7742 real_old
= reg_equiv_mem (REGNO (old
));
7744 if (secondary_reload_class (0, rl
->rclass
, mode
, real_old
) != NO_REGS
)
7746 rtx second_reloadreg
= reloadreg
;
7747 reloadreg
= rld
[secondary_reload
].reg_rtx
;
7749 /* See if RELOADREG is to be used as a scratch register
7750 or as an intermediate register. */
7751 if (rl
->secondary_out_icode
!= CODE_FOR_nothing
)
7753 /* We'd have to add extra code to handle this case. */
7754 gcc_assert (tertiary_reload
< 0);
7756 emit_insn ((GEN_FCN (rl
->secondary_out_icode
)
7757 (real_old
, second_reloadreg
, reloadreg
)));
7762 /* See if we need both a scratch and intermediate reload
7765 enum insn_code tertiary_icode
7766 = rld
[secondary_reload
].secondary_out_icode
;
7768 /* We'd have to add more code for quartary reloads. */
7769 gcc_assert (tertiary_reload
< 0
7770 || rld
[tertiary_reload
].secondary_out_reload
< 0);
7772 if (GET_MODE (reloadreg
) != mode
)
7773 reloadreg
= reload_adjust_reg_for_mode (reloadreg
, mode
);
7775 if (tertiary_icode
!= CODE_FOR_nothing
)
7777 rtx third_reloadreg
= rld
[tertiary_reload
].reg_rtx
;
7779 /* Copy primary reload reg to secondary reload reg.
7780 (Note that these have been swapped above, then
7781 secondary reload reg to OLD using our insn.) */
7783 /* If REAL_OLD is a paradoxical SUBREG, remove it
7784 and try to put the opposite SUBREG on
7786 strip_paradoxical_subreg (&real_old
, &reloadreg
);
7788 gen_reload (reloadreg
, second_reloadreg
,
7789 rl
->opnum
, rl
->when_needed
);
7790 emit_insn ((GEN_FCN (tertiary_icode
)
7791 (real_old
, reloadreg
, third_reloadreg
)));
7797 /* Copy between the reload regs here and then to
7800 gen_reload (reloadreg
, second_reloadreg
,
7801 rl
->opnum
, rl
->when_needed
);
7802 if (tertiary_reload
>= 0)
7804 rtx third_reloadreg
= rld
[tertiary_reload
].reg_rtx
;
7806 gen_reload (third_reloadreg
, reloadreg
,
7807 rl
->opnum
, rl
->when_needed
);
7808 reloadreg
= third_reloadreg
;
7815 /* Output the last reload insn. */
7820 /* Don't output the last reload if OLD is not the dest of
7821 INSN and is in the src and is clobbered by INSN. */
7822 if (! flag_expensive_optimizations
7824 || !(set
= single_set (insn
))
7825 || rtx_equal_p (old
, SET_DEST (set
))
7826 || !reg_mentioned_p (old
, SET_SRC (set
))
7827 || !((REGNO (old
) < FIRST_PSEUDO_REGISTER
)
7828 && regno_clobbered_p (REGNO (old
), insn
, rl
->mode
, 0)))
7829 gen_reload (old
, reloadreg
, rl
->opnum
,
7833 /* Look at all insns we emitted, just to be safe. */
7834 for (p
= get_insns (); p
; p
= NEXT_INSN (p
))
7837 rtx pat
= PATTERN (p
);
7839 /* If this output reload doesn't come from a spill reg,
7840 clear any memory of reloaded copies of the pseudo reg.
7841 If this output reload comes from a spill reg,
7842 reg_has_output_reload will make this do nothing. */
7843 note_stores (pat
, forget_old_reloads_1
, NULL
);
7845 if (reg_mentioned_p (rl_reg_rtx
, pat
))
7847 rtx set
= single_set (insn
);
7848 if (reload_spill_index
[j
] < 0
7850 && SET_SRC (set
) == rl_reg_rtx
)
7852 int src
= REGNO (SET_SRC (set
));
7854 reload_spill_index
[j
] = src
;
7855 SET_HARD_REG_BIT (reg_is_output_reload
, src
);
7856 if (find_regno_note (insn
, REG_DEAD
, src
))
7857 SET_HARD_REG_BIT (reg_reloaded_died
, src
);
7859 if (HARD_REGISTER_P (rl_reg_rtx
))
7861 int s
= rl
->secondary_out_reload
;
7862 set
= single_set (p
);
7863 /* If this reload copies only to the secondary reload
7864 register, the secondary reload does the actual
7866 if (s
>= 0 && set
== NULL_RTX
)
7867 /* We can't tell what function the secondary reload
7868 has and where the actual store to the pseudo is
7869 made; leave new_spill_reg_store alone. */
7872 && SET_SRC (set
) == rl_reg_rtx
7873 && SET_DEST (set
) == rld
[s
].reg_rtx
)
7875 /* Usually the next instruction will be the
7876 secondary reload insn; if we can confirm
7877 that it is, setting new_spill_reg_store to
7878 that insn will allow an extra optimization. */
7879 rtx s_reg
= rld
[s
].reg_rtx
;
7880 rtx_insn
*next
= NEXT_INSN (p
);
7881 rld
[s
].out
= rl
->out
;
7882 rld
[s
].out_reg
= rl
->out_reg
;
7883 set
= single_set (next
);
7884 if (set
&& SET_SRC (set
) == s_reg
7885 && reload_reg_rtx_reaches_end_p (s_reg
, s
))
7887 SET_HARD_REG_BIT (reg_is_output_reload
,
7889 new_spill_reg_store
[REGNO (s_reg
)] = next
;
7892 else if (reload_reg_rtx_reaches_end_p (rl_reg_rtx
, j
))
7893 new_spill_reg_store
[REGNO (rl_reg_rtx
)] = p
;
7898 if (rl
->when_needed
== RELOAD_OTHER
)
7900 emit_insn (other_output_reload_insns
[rl
->opnum
]);
7901 other_output_reload_insns
[rl
->opnum
] = get_insns ();
7904 output_reload_insns
[rl
->opnum
] = get_insns ();
7906 if (cfun
->can_throw_non_call_exceptions
)
7907 copy_reg_eh_region_note_forward (insn
, get_insns (), NULL
);
7912 /* Do input reloading for reload RL, which is for the insn described by CHAIN
7913 and has the number J. */
7915 do_input_reload (struct insn_chain
*chain
, struct reload
*rl
, int j
)
7917 rtx_insn
*insn
= chain
->insn
;
7918 rtx old
= (rl
->in
&& MEM_P (rl
->in
)
7919 ? rl
->in_reg
: rl
->in
);
7920 rtx reg_rtx
= rl
->reg_rtx
;
7924 enum machine_mode mode
;
7926 /* Determine the mode to reload in.
7927 This is very tricky because we have three to choose from.
7928 There is the mode the insn operand wants (rl->inmode).
7929 There is the mode of the reload register RELOADREG.
7930 There is the intrinsic mode of the operand, which we could find
7931 by stripping some SUBREGs.
7932 It turns out that RELOADREG's mode is irrelevant:
7933 we can change that arbitrarily.
7935 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
7936 then the reload reg may not support QImode moves, so use SImode.
7937 If foo is in memory due to spilling a pseudo reg, this is safe,
7938 because the QImode value is in the least significant part of a
7939 slot big enough for a SImode. If foo is some other sort of
7940 memory reference, then it is impossible to reload this case,
7941 so previous passes had better make sure this never happens.
7943 Then consider a one-word union which has SImode and one of its
7944 members is a float, being fetched as (SUBREG:SF union:SI).
7945 We must fetch that as SFmode because we could be loading into
7946 a float-only register. In this case OLD's mode is correct.
7948 Consider an immediate integer: it has VOIDmode. Here we need
7949 to get a mode from something else.
7951 In some cases, there is a fourth mode, the operand's
7952 containing mode. If the insn specifies a containing mode for
7953 this operand, it overrides all others.
7955 I am not sure whether the algorithm here is always right,
7956 but it does the right things in those cases. */
7958 mode
= GET_MODE (old
);
7959 if (mode
== VOIDmode
)
7962 /* We cannot use gen_lowpart_common since it can do the wrong thing
7963 when REG_RTX has a multi-word mode. Note that REG_RTX must
7964 always be a REG here. */
7965 if (GET_MODE (reg_rtx
) != mode
)
7966 reg_rtx
= reload_adjust_reg_for_mode (reg_rtx
, mode
);
7968 reload_reg_rtx_for_input
[j
] = reg_rtx
;
7971 /* AUTO_INC reloads need to be handled even if inherited. We got an
7972 AUTO_INC reload if reload_out is set but reload_out_reg isn't. */
7973 && (! reload_inherited
[j
] || (rl
->out
&& ! rl
->out_reg
))
7974 && ! rtx_equal_p (reg_rtx
, old
)
7976 emit_input_reload_insns (chain
, rld
+ j
, old
, j
);
7978 /* When inheriting a wider reload, we have a MEM in rl->in,
7979 e.g. inheriting a SImode output reload for
7980 (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */
7981 if (optimize
&& reload_inherited
[j
] && rl
->in
7983 && MEM_P (rl
->in_reg
)
7984 && reload_spill_index
[j
] >= 0
7985 && TEST_HARD_REG_BIT (reg_reloaded_valid
, reload_spill_index
[j
]))
7986 rl
->in
= regno_reg_rtx
[reg_reloaded_contents
[reload_spill_index
[j
]]];
7988 /* If we are reloading a register that was recently stored in with an
7989 output-reload, see if we can prove there was
7990 actually no need to store the old value in it. */
7993 && (reload_inherited
[j
] || reload_override_in
[j
])
7996 && spill_reg_store
[REGNO (reg_rtx
)] != 0
7998 /* There doesn't seem to be any reason to restrict this to pseudos
7999 and doing so loses in the case where we are copying from a
8000 register of the wrong class. */
8001 && !HARD_REGISTER_P (spill_reg_stored_to
[REGNO (reg_rtx
)])
8003 /* The insn might have already some references to stackslots
8004 replaced by MEMs, while reload_out_reg still names the
8006 && (dead_or_set_p (insn
, spill_reg_stored_to
[REGNO (reg_rtx
)])
8007 || rtx_equal_p (spill_reg_stored_to
[REGNO (reg_rtx
)], rl
->out_reg
)))
8008 delete_output_reload (insn
, j
, REGNO (reg_rtx
), reg_rtx
);
8011 /* Do output reloading for reload RL, which is for the insn described by
8012 CHAIN and has the number J.
8013 ??? At some point we need to support handling output reloads of
8014 JUMP_INSNs or insns that set cc0. */
8016 do_output_reload (struct insn_chain
*chain
, struct reload
*rl
, int j
)
8019 rtx_insn
*insn
= chain
->insn
;
8020 /* If this is an output reload that stores something that is
8021 not loaded in this same reload, see if we can eliminate a previous
8023 rtx pseudo
= rl
->out_reg
;
8024 rtx reg_rtx
= rl
->reg_rtx
;
8026 if (rl
->out
&& reg_rtx
)
8028 enum machine_mode mode
;
8030 /* Determine the mode to reload in.
8031 See comments above (for input reloading). */
8032 mode
= GET_MODE (rl
->out
);
8033 if (mode
== VOIDmode
)
8035 /* VOIDmode should never happen for an output. */
8036 if (asm_noperands (PATTERN (insn
)) < 0)
8037 /* It's the compiler's fault. */
8038 fatal_insn ("VOIDmode on an output", insn
);
8039 error_for_asm (insn
, "output operand is constant in %<asm%>");
8040 /* Prevent crash--use something we know is valid. */
8042 rl
->out
= gen_rtx_REG (mode
, REGNO (reg_rtx
));
8044 if (GET_MODE (reg_rtx
) != mode
)
8045 reg_rtx
= reload_adjust_reg_for_mode (reg_rtx
, mode
);
8047 reload_reg_rtx_for_output
[j
] = reg_rtx
;
8052 && ! rtx_equal_p (rl
->in_reg
, pseudo
)
8053 && REGNO (pseudo
) >= FIRST_PSEUDO_REGISTER
8054 && reg_last_reload_reg
[REGNO (pseudo
)])
8056 int pseudo_no
= REGNO (pseudo
);
8057 int last_regno
= REGNO (reg_last_reload_reg
[pseudo_no
]);
8059 /* We don't need to test full validity of last_regno for
8060 inherit here; we only want to know if the store actually
8061 matches the pseudo. */
8062 if (TEST_HARD_REG_BIT (reg_reloaded_valid
, last_regno
)
8063 && reg_reloaded_contents
[last_regno
] == pseudo_no
8064 && spill_reg_store
[last_regno
]
8065 && rtx_equal_p (pseudo
, spill_reg_stored_to
[last_regno
]))
8066 delete_output_reload (insn
, j
, last_regno
, reg_rtx
);
8072 || rtx_equal_p (old
, reg_rtx
))
8075 /* An output operand that dies right away does need a reload,
8076 but need not be copied from it. Show the new location in the
8078 if ((REG_P (old
) || GET_CODE (old
) == SCRATCH
)
8079 && (note
= find_reg_note (insn
, REG_UNUSED
, old
)) != 0)
8081 XEXP (note
, 0) = reg_rtx
;
8084 /* Likewise for a SUBREG of an operand that dies. */
8085 else if (GET_CODE (old
) == SUBREG
8086 && REG_P (SUBREG_REG (old
))
8087 && 0 != (note
= find_reg_note (insn
, REG_UNUSED
,
8090 XEXP (note
, 0) = gen_lowpart_common (GET_MODE (old
), reg_rtx
);
8093 else if (GET_CODE (old
) == SCRATCH
)
8094 /* If we aren't optimizing, there won't be a REG_UNUSED note,
8095 but we don't want to make an output reload. */
8098 /* If is a JUMP_INSN, we can't support output reloads yet. */
8099 gcc_assert (NONJUMP_INSN_P (insn
));
8101 emit_output_reload_insns (chain
, rld
+ j
, j
);
8104 /* A reload copies values of MODE from register SRC to register DEST.
8105 Return true if it can be treated for inheritance purposes like a
8106 group of reloads, each one reloading a single hard register. The
8107 caller has already checked that (reg:MODE SRC) and (reg:MODE DEST)
8108 occupy the same number of hard registers. */
8111 inherit_piecemeal_p (int dest ATTRIBUTE_UNUSED
,
8112 int src ATTRIBUTE_UNUSED
,
8113 enum machine_mode mode ATTRIBUTE_UNUSED
)
8115 #ifdef CANNOT_CHANGE_MODE_CLASS
8116 return (!REG_CANNOT_CHANGE_MODE_P (dest
, mode
, reg_raw_mode
[dest
])
8117 && !REG_CANNOT_CHANGE_MODE_P (src
, mode
, reg_raw_mode
[src
]));
8123 /* Output insns to reload values in and out of the chosen reload regs. */
8126 emit_reload_insns (struct insn_chain
*chain
)
8128 rtx_insn
*insn
= chain
->insn
;
8132 CLEAR_HARD_REG_SET (reg_reloaded_died
);
8134 for (j
= 0; j
< reload_n_operands
; j
++)
8135 input_reload_insns
[j
] = input_address_reload_insns
[j
]
8136 = inpaddr_address_reload_insns
[j
]
8137 = output_reload_insns
[j
] = output_address_reload_insns
[j
]
8138 = outaddr_address_reload_insns
[j
]
8139 = other_output_reload_insns
[j
] = 0;
8140 other_input_address_reload_insns
= 0;
8141 other_input_reload_insns
= 0;
8142 operand_reload_insns
= 0;
8143 other_operand_reload_insns
= 0;
8145 /* Dump reloads into the dump file. */
8148 fprintf (dump_file
, "\nReloads for insn # %d\n", INSN_UID (insn
));
8149 debug_reload_to_stream (dump_file
);
8152 for (j
= 0; j
< n_reloads
; j
++)
8153 if (rld
[j
].reg_rtx
&& HARD_REGISTER_P (rld
[j
].reg_rtx
))
8157 for (i
= REGNO (rld
[j
].reg_rtx
); i
< END_REGNO (rld
[j
].reg_rtx
); i
++)
8158 new_spill_reg_store
[i
] = 0;
8161 /* Now output the instructions to copy the data into and out of the
8162 reload registers. Do these in the order that the reloads were reported,
8163 since reloads of base and index registers precede reloads of operands
8164 and the operands may need the base and index registers reloaded. */
8166 for (j
= 0; j
< n_reloads
; j
++)
8168 do_input_reload (chain
, rld
+ j
, j
);
8169 do_output_reload (chain
, rld
+ j
, j
);
8172 /* Now write all the insns we made for reloads in the order expected by
8173 the allocation functions. Prior to the insn being reloaded, we write
8174 the following reloads:
8176 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
8178 RELOAD_OTHER reloads.
8180 For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
8181 by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
8182 RELOAD_FOR_INPUT reload for the operand.
8184 RELOAD_FOR_OPADDR_ADDRS reloads.
8186 RELOAD_FOR_OPERAND_ADDRESS reloads.
8188 After the insn being reloaded, we write the following:
8190 For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
8191 by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
8192 RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
8193 reloads for the operand. The RELOAD_OTHER output reloads are
8194 output in descending order by reload number. */
8196 emit_insn_before (other_input_address_reload_insns
, insn
);
8197 emit_insn_before (other_input_reload_insns
, insn
);
8199 for (j
= 0; j
< reload_n_operands
; j
++)
8201 emit_insn_before (inpaddr_address_reload_insns
[j
], insn
);
8202 emit_insn_before (input_address_reload_insns
[j
], insn
);
8203 emit_insn_before (input_reload_insns
[j
], insn
);
8206 emit_insn_before (other_operand_reload_insns
, insn
);
8207 emit_insn_before (operand_reload_insns
, insn
);
8209 for (j
= 0; j
< reload_n_operands
; j
++)
8211 rtx x
= emit_insn_after (outaddr_address_reload_insns
[j
], insn
);
8212 x
= emit_insn_after (output_address_reload_insns
[j
], x
);
8213 x
= emit_insn_after (output_reload_insns
[j
], x
);
8214 emit_insn_after (other_output_reload_insns
[j
], x
);
8217 /* For all the spill regs newly reloaded in this instruction,
8218 record what they were reloaded from, so subsequent instructions
8219 can inherit the reloads.
8221 Update spill_reg_store for the reloads of this insn.
8222 Copy the elements that were updated in the loop above. */
8224 for (j
= 0; j
< n_reloads
; j
++)
8226 int r
= reload_order
[j
];
8227 int i
= reload_spill_index
[r
];
8229 /* If this is a non-inherited input reload from a pseudo, we must
8230 clear any memory of a previous store to the same pseudo. Only do
8231 something if there will not be an output reload for the pseudo
8233 if (rld
[r
].in_reg
!= 0
8234 && ! (reload_inherited
[r
] || reload_override_in
[r
]))
8236 rtx reg
= rld
[r
].in_reg
;
8238 if (GET_CODE (reg
) == SUBREG
)
8239 reg
= SUBREG_REG (reg
);
8242 && REGNO (reg
) >= FIRST_PSEUDO_REGISTER
8243 && !REGNO_REG_SET_P (®_has_output_reload
, REGNO (reg
)))
8245 int nregno
= REGNO (reg
);
8247 if (reg_last_reload_reg
[nregno
])
8249 int last_regno
= REGNO (reg_last_reload_reg
[nregno
]);
8251 if (reg_reloaded_contents
[last_regno
] == nregno
)
8252 spill_reg_store
[last_regno
] = 0;
8257 /* I is nonneg if this reload used a register.
8258 If rld[r].reg_rtx is 0, this is an optional reload
8259 that we opted to ignore. */
8261 if (i
>= 0 && rld
[r
].reg_rtx
!= 0)
8263 int nr
= hard_regno_nregs
[i
][GET_MODE (rld
[r
].reg_rtx
)];
8266 /* For a multi register reload, we need to check if all or part
8267 of the value lives to the end. */
8268 for (k
= 0; k
< nr
; k
++)
8269 if (reload_reg_reaches_end_p (i
+ k
, r
))
8270 CLEAR_HARD_REG_BIT (reg_reloaded_valid
, i
+ k
);
8272 /* Maybe the spill reg contains a copy of reload_out. */
8274 && (REG_P (rld
[r
].out
)
8276 ? REG_P (rld
[r
].out_reg
)
8277 /* The reload value is an auto-modification of
8278 some kind. For PRE_INC, POST_INC, PRE_DEC
8279 and POST_DEC, we record an equivalence
8280 between the reload register and the operand
8281 on the optimistic assumption that we can make
8282 the equivalence hold. reload_as_needed must
8283 then either make it hold or invalidate the
8286 PRE_MODIFY and POST_MODIFY addresses are reloaded
8287 somewhat differently, and allowing them here leads
8289 : (GET_CODE (rld
[r
].out
) != POST_MODIFY
8290 && GET_CODE (rld
[r
].out
) != PRE_MODIFY
))))
8294 reg
= reload_reg_rtx_for_output
[r
];
8295 if (reload_reg_rtx_reaches_end_p (reg
, r
))
8297 enum machine_mode mode
= GET_MODE (reg
);
8298 int regno
= REGNO (reg
);
8299 int nregs
= hard_regno_nregs
[regno
][mode
];
8300 rtx out
= (REG_P (rld
[r
].out
)
8304 /* AUTO_INC */ : XEXP (rld
[r
].in_reg
, 0));
8305 int out_regno
= REGNO (out
);
8306 int out_nregs
= (!HARD_REGISTER_NUM_P (out_regno
) ? 1
8307 : hard_regno_nregs
[out_regno
][mode
]);
8310 spill_reg_store
[regno
] = new_spill_reg_store
[regno
];
8311 spill_reg_stored_to
[regno
] = out
;
8312 reg_last_reload_reg
[out_regno
] = reg
;
8314 piecemeal
= (HARD_REGISTER_NUM_P (out_regno
)
8315 && nregs
== out_nregs
8316 && inherit_piecemeal_p (out_regno
, regno
, mode
));
8318 /* If OUT_REGNO is a hard register, it may occupy more than
8319 one register. If it does, say what is in the
8320 rest of the registers assuming that both registers
8321 agree on how many words the object takes. If not,
8322 invalidate the subsequent registers. */
8324 if (HARD_REGISTER_NUM_P (out_regno
))
8325 for (k
= 1; k
< out_nregs
; k
++)
8326 reg_last_reload_reg
[out_regno
+ k
]
8327 = (piecemeal
? regno_reg_rtx
[regno
+ k
] : 0);
8329 /* Now do the inverse operation. */
8330 for (k
= 0; k
< nregs
; k
++)
8332 CLEAR_HARD_REG_BIT (reg_reloaded_dead
, regno
+ k
);
8333 reg_reloaded_contents
[regno
+ k
]
8334 = (!HARD_REGISTER_NUM_P (out_regno
) || !piecemeal
8337 reg_reloaded_insn
[regno
+ k
] = insn
;
8338 SET_HARD_REG_BIT (reg_reloaded_valid
, regno
+ k
);
8339 if (HARD_REGNO_CALL_PART_CLOBBERED (regno
+ k
, mode
))
8340 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered
,
8343 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered
,
8348 /* Maybe the spill reg contains a copy of reload_in. Only do
8349 something if there will not be an output reload for
8350 the register being reloaded. */
8351 else if (rld
[r
].out_reg
== 0
8353 && ((REG_P (rld
[r
].in
)
8354 && !HARD_REGISTER_P (rld
[r
].in
)
8355 && !REGNO_REG_SET_P (®_has_output_reload
,
8357 || (REG_P (rld
[r
].in_reg
)
8358 && !REGNO_REG_SET_P (®_has_output_reload
,
8359 REGNO (rld
[r
].in_reg
))))
8360 && !reg_set_p (reload_reg_rtx_for_input
[r
], PATTERN (insn
)))
8364 reg
= reload_reg_rtx_for_input
[r
];
8365 if (reload_reg_rtx_reaches_end_p (reg
, r
))
8367 enum machine_mode mode
;
8375 mode
= GET_MODE (reg
);
8376 regno
= REGNO (reg
);
8377 nregs
= hard_regno_nregs
[regno
][mode
];
8378 if (REG_P (rld
[r
].in
)
8379 && REGNO (rld
[r
].in
) >= FIRST_PSEUDO_REGISTER
)
8381 else if (REG_P (rld
[r
].in_reg
))
8384 in
= XEXP (rld
[r
].in_reg
, 0);
8385 in_regno
= REGNO (in
);
8387 in_nregs
= (!HARD_REGISTER_NUM_P (in_regno
) ? 1
8388 : hard_regno_nregs
[in_regno
][mode
]);
8390 reg_last_reload_reg
[in_regno
] = reg
;
8392 piecemeal
= (HARD_REGISTER_NUM_P (in_regno
)
8393 && nregs
== in_nregs
8394 && inherit_piecemeal_p (regno
, in_regno
, mode
));
8396 if (HARD_REGISTER_NUM_P (in_regno
))
8397 for (k
= 1; k
< in_nregs
; k
++)
8398 reg_last_reload_reg
[in_regno
+ k
]
8399 = (piecemeal
? regno_reg_rtx
[regno
+ k
] : 0);
8401 /* Unless we inherited this reload, show we haven't
8402 recently done a store.
8403 Previous stores of inherited auto_inc expressions
8404 also have to be discarded. */
8405 if (! reload_inherited
[r
]
8406 || (rld
[r
].out
&& ! rld
[r
].out_reg
))
8407 spill_reg_store
[regno
] = 0;
8409 for (k
= 0; k
< nregs
; k
++)
8411 CLEAR_HARD_REG_BIT (reg_reloaded_dead
, regno
+ k
);
8412 reg_reloaded_contents
[regno
+ k
]
8413 = (!HARD_REGISTER_NUM_P (in_regno
) || !piecemeal
8416 reg_reloaded_insn
[regno
+ k
] = insn
;
8417 SET_HARD_REG_BIT (reg_reloaded_valid
, regno
+ k
);
8418 if (HARD_REGNO_CALL_PART_CLOBBERED (regno
+ k
, mode
))
8419 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered
,
8422 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered
,
8429 /* The following if-statement was #if 0'd in 1.34 (or before...).
8430 It's reenabled in 1.35 because supposedly nothing else
8431 deals with this problem. */
8433 /* If a register gets output-reloaded from a non-spill register,
8434 that invalidates any previous reloaded copy of it.
8435 But forget_old_reloads_1 won't get to see it, because
8436 it thinks only about the original insn. So invalidate it here.
8437 Also do the same thing for RELOAD_OTHER constraints where the
8438 output is discarded. */
8440 && ((rld
[r
].out
!= 0
8441 && (REG_P (rld
[r
].out
)
8442 || (MEM_P (rld
[r
].out
)
8443 && REG_P (rld
[r
].out_reg
))))
8444 || (rld
[r
].out
== 0 && rld
[r
].out_reg
8445 && REG_P (rld
[r
].out_reg
))))
8447 rtx out
= ((rld
[r
].out
&& REG_P (rld
[r
].out
))
8448 ? rld
[r
].out
: rld
[r
].out_reg
);
8449 int out_regno
= REGNO (out
);
8450 enum machine_mode mode
= GET_MODE (out
);
8452 /* REG_RTX is now set or clobbered by the main instruction.
8453 As the comment above explains, forget_old_reloads_1 only
8454 sees the original instruction, and there is no guarantee
8455 that the original instruction also clobbered REG_RTX.
8456 For example, if find_reloads sees that the input side of
8457 a matched operand pair dies in this instruction, it may
8458 use the input register as the reload register.
8460 Calling forget_old_reloads_1 is a waste of effort if
8461 REG_RTX is also the output register.
8463 If we know that REG_RTX holds the value of a pseudo
8464 register, the code after the call will record that fact. */
8465 if (rld
[r
].reg_rtx
&& rld
[r
].reg_rtx
!= out
)
8466 forget_old_reloads_1 (rld
[r
].reg_rtx
, NULL_RTX
, NULL
);
8468 if (!HARD_REGISTER_NUM_P (out_regno
))
8471 rtx_insn
*store_insn
= NULL
;
8473 reg_last_reload_reg
[out_regno
] = 0;
8475 /* If we can find a hard register that is stored, record
8476 the storing insn so that we may delete this insn with
8477 delete_output_reload. */
8478 src_reg
= reload_reg_rtx_for_output
[r
];
8482 if (reload_reg_rtx_reaches_end_p (src_reg
, r
))
8483 store_insn
= new_spill_reg_store
[REGNO (src_reg
)];
8489 /* If this is an optional reload, try to find the
8490 source reg from an input reload. */
8491 rtx set
= single_set (insn
);
8492 if (set
&& SET_DEST (set
) == rld
[r
].out
)
8496 src_reg
= SET_SRC (set
);
8498 for (k
= 0; k
< n_reloads
; k
++)
8500 if (rld
[k
].in
== src_reg
)
8502 src_reg
= reload_reg_rtx_for_input
[k
];
8508 if (src_reg
&& REG_P (src_reg
)
8509 && REGNO (src_reg
) < FIRST_PSEUDO_REGISTER
)
8511 int src_regno
, src_nregs
, k
;
8514 gcc_assert (GET_MODE (src_reg
) == mode
);
8515 src_regno
= REGNO (src_reg
);
8516 src_nregs
= hard_regno_nregs
[src_regno
][mode
];
8517 /* The place where to find a death note varies with
8518 PRESERVE_DEATH_INFO_REGNO_P . The condition is not
8519 necessarily checked exactly in the code that moves
8520 notes, so just check both locations. */
8521 note
= find_regno_note (insn
, REG_DEAD
, src_regno
);
8522 if (! note
&& store_insn
)
8523 note
= find_regno_note (store_insn
, REG_DEAD
, src_regno
);
8524 for (k
= 0; k
< src_nregs
; k
++)
8526 spill_reg_store
[src_regno
+ k
] = store_insn
;
8527 spill_reg_stored_to
[src_regno
+ k
] = out
;
8528 reg_reloaded_contents
[src_regno
+ k
] = out_regno
;
8529 reg_reloaded_insn
[src_regno
+ k
] = store_insn
;
8530 CLEAR_HARD_REG_BIT (reg_reloaded_dead
, src_regno
+ k
);
8531 SET_HARD_REG_BIT (reg_reloaded_valid
, src_regno
+ k
);
8532 if (HARD_REGNO_CALL_PART_CLOBBERED (src_regno
+ k
,
8534 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered
,
8537 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered
,
8539 SET_HARD_REG_BIT (reg_is_output_reload
, src_regno
+ k
);
8541 SET_HARD_REG_BIT (reg_reloaded_died
, src_regno
);
8543 CLEAR_HARD_REG_BIT (reg_reloaded_died
, src_regno
);
8545 reg_last_reload_reg
[out_regno
] = src_reg
;
8546 /* We have to set reg_has_output_reload here, or else
8547 forget_old_reloads_1 will clear reg_last_reload_reg
8549 SET_REGNO_REG_SET (®_has_output_reload
,
8555 int k
, out_nregs
= hard_regno_nregs
[out_regno
][mode
];
8557 for (k
= 0; k
< out_nregs
; k
++)
8558 reg_last_reload_reg
[out_regno
+ k
] = 0;
8562 IOR_HARD_REG_SET (reg_reloaded_dead
, reg_reloaded_died
);
8565 /* Go through the motions to emit INSN and test if it is strictly valid.
8566 Return the emitted insn if valid, else return NULL. */
8569 emit_insn_if_valid_for_reload (rtx pat
)
8571 rtx_insn
*last
= get_last_insn ();
8574 rtx_insn
*insn
= emit_insn (pat
);
8575 code
= recog_memoized (insn
);
8579 extract_insn (insn
);
8580 /* We want constrain operands to treat this insn strictly in its
8581 validity determination, i.e., the way it would after reload has
8583 if (constrain_operands (1))
8587 delete_insns_since (last
);
8591 /* Emit code to perform a reload from IN (which may be a reload register) to
8592 OUT (which may also be a reload register). IN or OUT is from operand
8593 OPNUM with reload type TYPE.
8595 Returns first insn emitted. */
8598 gen_reload (rtx out
, rtx in
, int opnum
, enum reload_type type
)
8600 rtx_insn
*last
= get_last_insn ();
8602 #ifdef SECONDARY_MEMORY_NEEDED
8606 /* If IN is a paradoxical SUBREG, remove it and try to put the
8607 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
8608 if (!strip_paradoxical_subreg (&in
, &out
))
8609 strip_paradoxical_subreg (&out
, &in
);
8611 /* How to do this reload can get quite tricky. Normally, we are being
8612 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
8613 register that didn't get a hard register. In that case we can just
8614 call emit_move_insn.
8616 We can also be asked to reload a PLUS that adds a register or a MEM to
8617 another register, constant or MEM. This can occur during frame pointer
8618 elimination and while reloading addresses. This case is handled by
8619 trying to emit a single insn to perform the add. If it is not valid,
8620 we use a two insn sequence.
8622 Or we can be asked to reload an unary operand that was a fragment of
8623 an addressing mode, into a register. If it isn't recognized as-is,
8624 we try making the unop operand and the reload-register the same:
8625 (set reg:X (unop:X expr:Y))
8626 -> (set reg:Y expr:Y) (set reg:X (unop:X reg:Y)).
8628 Finally, we could be called to handle an 'o' constraint by putting
8629 an address into a register. In that case, we first try to do this
8630 with a named pattern of "reload_load_address". If no such pattern
8631 exists, we just emit a SET insn and hope for the best (it will normally
8632 be valid on machines that use 'o').
8634 This entire process is made complex because reload will never
8635 process the insns we generate here and so we must ensure that
8636 they will fit their constraints and also by the fact that parts of
8637 IN might be being reloaded separately and replaced with spill registers.
8638 Because of this, we are, in some sense, just guessing the right approach
8639 here. The one listed above seems to work.
8641 ??? At some point, this whole thing needs to be rethought. */
8643 if (GET_CODE (in
) == PLUS
8644 && (REG_P (XEXP (in
, 0))
8645 || GET_CODE (XEXP (in
, 0)) == SUBREG
8646 || MEM_P (XEXP (in
, 0)))
8647 && (REG_P (XEXP (in
, 1))
8648 || GET_CODE (XEXP (in
, 1)) == SUBREG
8649 || CONSTANT_P (XEXP (in
, 1))
8650 || MEM_P (XEXP (in
, 1))))
8652 /* We need to compute the sum of a register or a MEM and another
8653 register, constant, or MEM, and put it into the reload
8654 register. The best possible way of doing this is if the machine
8655 has a three-operand ADD insn that accepts the required operands.
8657 The simplest approach is to try to generate such an insn and see if it
8658 is recognized and matches its constraints. If so, it can be used.
8660 It might be better not to actually emit the insn unless it is valid,
8661 but we need to pass the insn as an operand to `recog' and
8662 `extract_insn' and it is simpler to emit and then delete the insn if
8663 not valid than to dummy things up. */
8667 enum insn_code code
;
8669 op0
= find_replacement (&XEXP (in
, 0));
8670 op1
= find_replacement (&XEXP (in
, 1));
8672 /* Since constraint checking is strict, commutativity won't be
8673 checked, so we need to do that here to avoid spurious failure
8674 if the add instruction is two-address and the second operand
8675 of the add is the same as the reload reg, which is frequently
8676 the case. If the insn would be A = B + A, rearrange it so
8677 it will be A = A + B as constrain_operands expects. */
8679 if (REG_P (XEXP (in
, 1))
8680 && REGNO (out
) == REGNO (XEXP (in
, 1)))
8681 tem
= op0
, op0
= op1
, op1
= tem
;
8683 if (op0
!= XEXP (in
, 0) || op1
!= XEXP (in
, 1))
8684 in
= gen_rtx_PLUS (GET_MODE (in
), op0
, op1
);
8686 insn
= emit_insn_if_valid_for_reload (gen_rtx_SET (VOIDmode
, out
, in
));
8690 /* If that failed, we must use a conservative two-insn sequence.
8692 Use a move to copy one operand into the reload register. Prefer
8693 to reload a constant, MEM or pseudo since the move patterns can
8694 handle an arbitrary operand. If OP1 is not a constant, MEM or
8695 pseudo and OP1 is not a valid operand for an add instruction, then
8698 After reloading one of the operands into the reload register, add
8699 the reload register to the output register.
8701 If there is another way to do this for a specific machine, a
8702 DEFINE_PEEPHOLE should be specified that recognizes the sequence
8705 code
= optab_handler (add_optab
, GET_MODE (out
));
8707 if (CONSTANT_P (op1
) || MEM_P (op1
) || GET_CODE (op1
) == SUBREG
8709 && REGNO (op1
) >= FIRST_PSEUDO_REGISTER
)
8710 || (code
!= CODE_FOR_nothing
8711 && !insn_operand_matches (code
, 2, op1
)))
8712 tem
= op0
, op0
= op1
, op1
= tem
;
8714 gen_reload (out
, op0
, opnum
, type
);
8716 /* If OP0 and OP1 are the same, we can use OUT for OP1.
8717 This fixes a problem on the 32K where the stack pointer cannot
8718 be used as an operand of an add insn. */
8720 if (rtx_equal_p (op0
, op1
))
8723 insn
= emit_insn_if_valid_for_reload (gen_add2_insn (out
, op1
));
8726 /* Add a REG_EQUIV note so that find_equiv_reg can find it. */
8727 set_dst_reg_note (insn
, REG_EQUIV
, in
, out
);
8731 /* If that failed, copy the address register to the reload register.
8732 Then add the constant to the reload register. */
8734 gcc_assert (!reg_overlap_mentioned_p (out
, op0
));
8735 gen_reload (out
, op1
, opnum
, type
);
8736 insn
= emit_insn (gen_add2_insn (out
, op0
));
8737 set_dst_reg_note (insn
, REG_EQUIV
, in
, out
);
8740 #ifdef SECONDARY_MEMORY_NEEDED
8741 /* If we need a memory location to do the move, do it that way. */
8742 else if ((tem1
= replaced_subreg (in
), tem2
= replaced_subreg (out
),
8743 (REG_P (tem1
) && REG_P (tem2
)))
8744 && REGNO (tem1
) < FIRST_PSEUDO_REGISTER
8745 && REGNO (tem2
) < FIRST_PSEUDO_REGISTER
8746 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (REGNO (tem1
)),
8747 REGNO_REG_CLASS (REGNO (tem2
)),
8750 /* Get the memory to use and rewrite both registers to its mode. */
8751 rtx loc
= get_secondary_mem (in
, GET_MODE (out
), opnum
, type
);
8753 if (GET_MODE (loc
) != GET_MODE (out
))
8754 out
= gen_rtx_REG (GET_MODE (loc
), reg_or_subregno (out
));
8756 if (GET_MODE (loc
) != GET_MODE (in
))
8757 in
= gen_rtx_REG (GET_MODE (loc
), reg_or_subregno (in
));
8759 gen_reload (loc
, in
, opnum
, type
);
8760 gen_reload (out
, loc
, opnum
, type
);
8763 else if (REG_P (out
) && UNARY_P (in
))
8770 op1
= find_replacement (&XEXP (in
, 0));
8771 if (op1
!= XEXP (in
, 0))
8772 in
= gen_rtx_fmt_e (GET_CODE (in
), GET_MODE (in
), op1
);
8774 /* First, try a plain SET. */
8775 set
= emit_insn_if_valid_for_reload (gen_rtx_SET (VOIDmode
, out
, in
));
8779 /* If that failed, move the inner operand to the reload
8780 register, and try the same unop with the inner expression
8781 replaced with the reload register. */
8783 if (GET_MODE (op1
) != GET_MODE (out
))
8784 out_moded
= gen_rtx_REG (GET_MODE (op1
), REGNO (out
));
8788 gen_reload (out_moded
, op1
, opnum
, type
);
8791 = gen_rtx_SET (VOIDmode
, out
,
8792 gen_rtx_fmt_e (GET_CODE (in
), GET_MODE (in
),
8794 insn
= emit_insn_if_valid_for_reload (insn
);
8797 set_unique_reg_note (insn
, REG_EQUIV
, in
);
8798 return as_a
<rtx_insn
*> (insn
);
8801 fatal_insn ("failure trying to reload:", set
);
8803 /* If IN is a simple operand, use gen_move_insn. */
8804 else if (OBJECT_P (in
) || GET_CODE (in
) == SUBREG
)
8806 tem
= emit_insn (gen_move_insn (out
, in
));
8807 /* IN may contain a LABEL_REF, if so add a REG_LABEL_OPERAND note. */
8808 mark_jump_label (in
, tem
, 0);
8811 #ifdef HAVE_reload_load_address
8812 else if (HAVE_reload_load_address
)
8813 emit_insn (gen_reload_load_address (out
, in
));
8816 /* Otherwise, just write (set OUT IN) and hope for the best. */
8818 emit_insn (gen_rtx_SET (VOIDmode
, out
, in
));
8820 /* Return the first insn emitted.
8821 We can not just return get_last_insn, because there may have
8822 been multiple instructions emitted. Also note that gen_move_insn may
8823 emit more than one insn itself, so we can not assume that there is one
8824 insn emitted per emit_insn_before call. */
8826 return last
? NEXT_INSN (last
) : get_insns ();
8829 /* Delete a previously made output-reload whose result we now believe
8830 is not needed. First we double-check.
8832 INSN is the insn now being processed.
8833 LAST_RELOAD_REG is the hard register number for which we want to delete
8834 the last output reload.
8835 J is the reload-number that originally used REG. The caller has made
8836 certain that reload J doesn't use REG any longer for input.
8837 NEW_RELOAD_REG is reload register that reload J is using for REG. */
8840 delete_output_reload (rtx_insn
*insn
, int j
, int last_reload_reg
,
8843 rtx_insn
*output_reload_insn
= spill_reg_store
[last_reload_reg
];
8844 rtx reg
= spill_reg_stored_to
[last_reload_reg
];
8847 int n_inherited
= 0;
8852 /* It is possible that this reload has been only used to set another reload
8853 we eliminated earlier and thus deleted this instruction too. */
8854 if (output_reload_insn
->deleted ())
8857 /* Get the raw pseudo-register referred to. */
8859 while (GET_CODE (reg
) == SUBREG
)
8860 reg
= SUBREG_REG (reg
);
8861 substed
= reg_equiv_memory_loc (REGNO (reg
));
8863 /* This is unsafe if the operand occurs more often in the current
8864 insn than it is inherited. */
8865 for (k
= n_reloads
- 1; k
>= 0; k
--)
8867 rtx reg2
= rld
[k
].in
;
8870 if (MEM_P (reg2
) || reload_override_in
[k
])
8871 reg2
= rld
[k
].in_reg
;
8873 if (rld
[k
].out
&& ! rld
[k
].out_reg
)
8874 reg2
= XEXP (rld
[k
].in_reg
, 0);
8876 while (GET_CODE (reg2
) == SUBREG
)
8877 reg2
= SUBREG_REG (reg2
);
8878 if (rtx_equal_p (reg2
, reg
))
8880 if (reload_inherited
[k
] || reload_override_in
[k
] || k
== j
)
8886 n_occurrences
= count_occurrences (PATTERN (insn
), reg
, 0);
8887 if (CALL_P (insn
) && CALL_INSN_FUNCTION_USAGE (insn
))
8888 n_occurrences
+= count_occurrences (CALL_INSN_FUNCTION_USAGE (insn
),
8891 n_occurrences
+= count_occurrences (PATTERN (insn
),
8892 eliminate_regs (substed
, VOIDmode
,
8894 for (rtx i1
= reg_equiv_alt_mem_list (REGNO (reg
)); i1
; i1
= XEXP (i1
, 1))
8896 gcc_assert (!rtx_equal_p (XEXP (i1
, 0), substed
));
8897 n_occurrences
+= count_occurrences (PATTERN (insn
), XEXP (i1
, 0), 0);
8899 if (n_occurrences
> n_inherited
)
8902 regno
= REGNO (reg
);
8903 if (regno
>= FIRST_PSEUDO_REGISTER
)
8906 nregs
= hard_regno_nregs
[regno
][GET_MODE (reg
)];
8908 /* If the pseudo-reg we are reloading is no longer referenced
8909 anywhere between the store into it and here,
8910 and we're within the same basic block, then the value can only
8911 pass through the reload reg and end up here.
8912 Otherwise, give up--return. */
8913 for (rtx_insn
*i1
= NEXT_INSN (output_reload_insn
);
8914 i1
!= insn
; i1
= NEXT_INSN (i1
))
8916 if (NOTE_INSN_BASIC_BLOCK_P (i1
))
8918 if ((NONJUMP_INSN_P (i1
) || CALL_P (i1
))
8919 && refers_to_regno_p (regno
, regno
+ nregs
, PATTERN (i1
), NULL
))
8921 /* If this is USE in front of INSN, we only have to check that
8922 there are no more references than accounted for by inheritance. */
8923 while (NONJUMP_INSN_P (i1
) && GET_CODE (PATTERN (i1
)) == USE
)
8925 n_occurrences
+= rtx_equal_p (reg
, XEXP (PATTERN (i1
), 0)) != 0;
8926 i1
= NEXT_INSN (i1
);
8928 if (n_occurrences
<= n_inherited
&& i1
== insn
)
8934 /* We will be deleting the insn. Remove the spill reg information. */
8935 for (k
= hard_regno_nregs
[last_reload_reg
][GET_MODE (reg
)]; k
-- > 0; )
8937 spill_reg_store
[last_reload_reg
+ k
] = 0;
8938 spill_reg_stored_to
[last_reload_reg
+ k
] = 0;
8941 /* The caller has already checked that REG dies or is set in INSN.
8942 It has also checked that we are optimizing, and thus some
8943 inaccuracies in the debugging information are acceptable.
8944 So we could just delete output_reload_insn. But in some cases
8945 we can improve the debugging information without sacrificing
8946 optimization - maybe even improving the code: See if the pseudo
8947 reg has been completely replaced with reload regs. If so, delete
8948 the store insn and forget we had a stack slot for the pseudo. */
8949 if (rld
[j
].out
!= rld
[j
].in
8950 && REG_N_DEATHS (REGNO (reg
)) == 1
8951 && REG_N_SETS (REGNO (reg
)) == 1
8952 && REG_BASIC_BLOCK (REGNO (reg
)) >= NUM_FIXED_BLOCKS
8953 && find_regno_note (insn
, REG_DEAD
, REGNO (reg
)))
8957 /* We know that it was used only between here and the beginning of
8958 the current basic block. (We also know that the last use before
8959 INSN was the output reload we are thinking of deleting, but never
8960 mind that.) Search that range; see if any ref remains. */
8961 for (i2
= PREV_INSN (insn
); i2
; i2
= PREV_INSN (i2
))
8963 rtx set
= single_set (i2
);
8965 /* Uses which just store in the pseudo don't count,
8966 since if they are the only uses, they are dead. */
8967 if (set
!= 0 && SET_DEST (set
) == reg
)
8969 if (LABEL_P (i2
) || JUMP_P (i2
))
8971 if ((NONJUMP_INSN_P (i2
) || CALL_P (i2
))
8972 && reg_mentioned_p (reg
, PATTERN (i2
)))
8974 /* Some other ref remains; just delete the output reload we
8976 delete_address_reloads (output_reload_insn
, insn
);
8977 delete_insn (output_reload_insn
);
8982 /* Delete the now-dead stores into this pseudo. Note that this
8983 loop also takes care of deleting output_reload_insn. */
8984 for (i2
= PREV_INSN (insn
); i2
; i2
= PREV_INSN (i2
))
8986 rtx set
= single_set (i2
);
8988 if (set
!= 0 && SET_DEST (set
) == reg
)
8990 delete_address_reloads (i2
, insn
);
8993 if (LABEL_P (i2
) || JUMP_P (i2
))
8997 /* For the debugging info, say the pseudo lives in this reload reg. */
8998 reg_renumber
[REGNO (reg
)] = REGNO (new_reload_reg
);
8999 if (ira_conflicts_p
)
9000 /* Inform IRA about the change. */
9001 ira_mark_allocation_change (REGNO (reg
));
9002 alter_reg (REGNO (reg
), -1, false);
9006 delete_address_reloads (output_reload_insn
, insn
);
9007 delete_insn (output_reload_insn
);
9011 /* We are going to delete DEAD_INSN. Recursively delete loads of
9012 reload registers used in DEAD_INSN that are not used till CURRENT_INSN.
9013 CURRENT_INSN is being reloaded, so we have to check its reloads too. */
9015 delete_address_reloads (rtx_insn
*dead_insn
, rtx_insn
*current_insn
)
9017 rtx set
= single_set (dead_insn
);
9019 rtx_insn
*prev
, *next
;
9022 rtx dst
= SET_DEST (set
);
9024 delete_address_reloads_1 (dead_insn
, XEXP (dst
, 0), current_insn
);
9026 /* If we deleted the store from a reloaded post_{in,de}c expression,
9027 we can delete the matching adds. */
9028 prev
= PREV_INSN (dead_insn
);
9029 next
= NEXT_INSN (dead_insn
);
9030 if (! prev
|| ! next
)
9032 set
= single_set (next
);
9033 set2
= single_set (prev
);
9035 || GET_CODE (SET_SRC (set
)) != PLUS
|| GET_CODE (SET_SRC (set2
)) != PLUS
9036 || !CONST_INT_P (XEXP (SET_SRC (set
), 1))
9037 || !CONST_INT_P (XEXP (SET_SRC (set2
), 1)))
9039 dst
= SET_DEST (set
);
9040 if (! rtx_equal_p (dst
, SET_DEST (set2
))
9041 || ! rtx_equal_p (dst
, XEXP (SET_SRC (set
), 0))
9042 || ! rtx_equal_p (dst
, XEXP (SET_SRC (set2
), 0))
9043 || (INTVAL (XEXP (SET_SRC (set
), 1))
9044 != -INTVAL (XEXP (SET_SRC (set2
), 1))))
9046 delete_related_insns (prev
);
9047 delete_related_insns (next
);
9050 /* Subfunction of delete_address_reloads: process registers found in X. */
9052 delete_address_reloads_1 (rtx_insn
*dead_insn
, rtx x
, rtx_insn
*current_insn
)
9054 rtx_insn
*prev
, *i2
;
9057 enum rtx_code code
= GET_CODE (x
);
9061 const char *fmt
= GET_RTX_FORMAT (code
);
9062 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
9065 delete_address_reloads_1 (dead_insn
, XEXP (x
, i
), current_insn
);
9066 else if (fmt
[i
] == 'E')
9068 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
9069 delete_address_reloads_1 (dead_insn
, XVECEXP (x
, i
, j
),
9076 if (spill_reg_order
[REGNO (x
)] < 0)
9079 /* Scan backwards for the insn that sets x. This might be a way back due
9081 for (prev
= PREV_INSN (dead_insn
); prev
; prev
= PREV_INSN (prev
))
9083 code
= GET_CODE (prev
);
9084 if (code
== CODE_LABEL
|| code
== JUMP_INSN
)
9088 if (reg_set_p (x
, PATTERN (prev
)))
9090 if (reg_referenced_p (x
, PATTERN (prev
)))
9093 if (! prev
|| INSN_UID (prev
) < reload_first_uid
)
9095 /* Check that PREV only sets the reload register. */
9096 set
= single_set (prev
);
9099 dst
= SET_DEST (set
);
9101 || ! rtx_equal_p (dst
, x
))
9103 if (! reg_set_p (dst
, PATTERN (dead_insn
)))
9105 /* Check if DST was used in a later insn -
9106 it might have been inherited. */
9107 for (i2
= NEXT_INSN (dead_insn
); i2
; i2
= NEXT_INSN (i2
))
9113 if (reg_referenced_p (dst
, PATTERN (i2
)))
9115 /* If there is a reference to the register in the current insn,
9116 it might be loaded in a non-inherited reload. If no other
9117 reload uses it, that means the register is set before
9119 if (i2
== current_insn
)
9121 for (j
= n_reloads
- 1; j
>= 0; j
--)
9122 if ((rld
[j
].reg_rtx
== dst
&& reload_inherited
[j
])
9123 || reload_override_in
[j
] == dst
)
9125 for (j
= n_reloads
- 1; j
>= 0; j
--)
9126 if (rld
[j
].in
&& rld
[j
].reg_rtx
== dst
)
9135 /* If DST is still live at CURRENT_INSN, check if it is used for
9136 any reload. Note that even if CURRENT_INSN sets DST, we still
9137 have to check the reloads. */
9138 if (i2
== current_insn
)
9140 for (j
= n_reloads
- 1; j
>= 0; j
--)
9141 if ((rld
[j
].reg_rtx
== dst
&& reload_inherited
[j
])
9142 || reload_override_in
[j
] == dst
)
9144 /* ??? We can't finish the loop here, because dst might be
9145 allocated to a pseudo in this block if no reload in this
9146 block needs any of the classes containing DST - see
9147 spill_hard_reg. There is no easy way to tell this, so we
9148 have to scan till the end of the basic block. */
9150 if (reg_set_p (dst
, PATTERN (i2
)))
9154 delete_address_reloads_1 (prev
, SET_SRC (set
), current_insn
);
9155 reg_reloaded_contents
[REGNO (dst
)] = -1;
9159 /* Output reload-insns to reload VALUE into RELOADREG.
9160 VALUE is an autoincrement or autodecrement RTX whose operand
9161 is a register or memory location;
9162 so reloading involves incrementing that location.
9163 IN is either identical to VALUE, or some cheaper place to reload from.
9165 INC_AMOUNT is the number to increment or decrement by (always positive).
9166 This cannot be deduced from VALUE. */
9169 inc_for_reload (rtx reloadreg
, rtx in
, rtx value
, int inc_amount
)
9171 /* REG or MEM to be copied and incremented. */
9172 rtx incloc
= find_replacement (&XEXP (value
, 0));
9173 /* Nonzero if increment after copying. */
9174 int post
= (GET_CODE (value
) == POST_DEC
|| GET_CODE (value
) == POST_INC
9175 || GET_CODE (value
) == POST_MODIFY
);
9180 rtx real_in
= in
== value
? incloc
: in
;
9182 /* No hard register is equivalent to this register after
9183 inc/dec operation. If REG_LAST_RELOAD_REG were nonzero,
9184 we could inc/dec that register as well (maybe even using it for
9185 the source), but I'm not sure it's worth worrying about. */
9187 reg_last_reload_reg
[REGNO (incloc
)] = 0;
9189 if (GET_CODE (value
) == PRE_MODIFY
|| GET_CODE (value
) == POST_MODIFY
)
9191 gcc_assert (GET_CODE (XEXP (value
, 1)) == PLUS
);
9192 inc
= find_replacement (&XEXP (XEXP (value
, 1), 1));
9196 if (GET_CODE (value
) == PRE_DEC
|| GET_CODE (value
) == POST_DEC
)
9197 inc_amount
= -inc_amount
;
9199 inc
= GEN_INT (inc_amount
);
9202 /* If this is post-increment, first copy the location to the reload reg. */
9203 if (post
&& real_in
!= reloadreg
)
9204 emit_insn (gen_move_insn (reloadreg
, real_in
));
9208 /* See if we can directly increment INCLOC. Use a method similar to
9209 that in gen_reload. */
9211 last
= get_last_insn ();
9212 add_insn
= emit_insn (gen_rtx_SET (VOIDmode
, incloc
,
9213 gen_rtx_PLUS (GET_MODE (incloc
),
9216 code
= recog_memoized (add_insn
);
9219 extract_insn (add_insn
);
9220 if (constrain_operands (1))
9222 /* If this is a pre-increment and we have incremented the value
9223 where it lives, copy the incremented value to RELOADREG to
9224 be used as an address. */
9227 emit_insn (gen_move_insn (reloadreg
, incloc
));
9231 delete_insns_since (last
);
9234 /* If couldn't do the increment directly, must increment in RELOADREG.
9235 The way we do this depends on whether this is pre- or post-increment.
9236 For pre-increment, copy INCLOC to the reload register, increment it
9237 there, then save back. */
9241 if (in
!= reloadreg
)
9242 emit_insn (gen_move_insn (reloadreg
, real_in
));
9243 emit_insn (gen_add2_insn (reloadreg
, inc
));
9244 emit_insn (gen_move_insn (incloc
, reloadreg
));
9249 Because this might be a jump insn or a compare, and because RELOADREG
9250 may not be available after the insn in an input reload, we must do
9251 the incrementation before the insn being reloaded for.
9253 We have already copied IN to RELOADREG. Increment the copy in
9254 RELOADREG, save that back, then decrement RELOADREG so it has
9255 the original value. */
9257 emit_insn (gen_add2_insn (reloadreg
, inc
));
9258 emit_insn (gen_move_insn (incloc
, reloadreg
));
9259 if (CONST_INT_P (inc
))
9260 emit_insn (gen_add2_insn (reloadreg
,
9261 gen_int_mode (-INTVAL (inc
),
9262 GET_MODE (reloadreg
))));
9264 emit_insn (gen_sub2_insn (reloadreg
, inc
));
9270 add_auto_inc_notes (rtx_insn
*insn
, rtx x
)
9272 enum rtx_code code
= GET_CODE (x
);
9276 if (code
== MEM
&& auto_inc_p (XEXP (x
, 0)))
9278 add_reg_note (insn
, REG_INC
, XEXP (XEXP (x
, 0), 0));
9282 /* Scan all the operand sub-expressions. */
9283 fmt
= GET_RTX_FORMAT (code
);
9284 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
9287 add_auto_inc_notes (insn
, XEXP (x
, i
));
9288 else if (fmt
[i
] == 'E')
9289 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
9290 add_auto_inc_notes (insn
, XVECEXP (x
, i
, j
));