1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987-2013 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify it under
7 the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 3, or (at your option) any later
11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
22 #include "coretypes.h"
26 #include "hard-reg-set.h"
27 #include "rtl-error.h"
30 #include "insn-config.h"
37 #include "addresses.h"
38 #include "basic-block.h"
49 /* This file contains the reload pass of the compiler, which is
50 run after register allocation has been done. It checks that
51 each insn is valid (operands required to be in registers really
52 are in registers of the proper class) and fixes up invalid ones
53 by copying values temporarily into registers for the insns
56 The results of register allocation are described by the vector
57 reg_renumber; the insns still contain pseudo regs, but reg_renumber
58 can be used to find which hard reg, if any, a pseudo reg is in.
60 The technique we always use is to free up a few hard regs that are
61 called ``reload regs'', and for each place where a pseudo reg
62 must be in a hard reg, copy it temporarily into one of the reload regs.
64 Reload regs are allocated locally for every instruction that needs
65 reloads. When there are pseudos which are allocated to a register that
66 has been chosen as a reload reg, such pseudos must be ``spilled''.
67 This means that they go to other hard regs, or to stack slots if no other
68 available hard regs can be found. Spilling can invalidate more
69 insns, requiring additional need for reloads, so we must keep checking
70 until the process stabilizes.
72 For machines with different classes of registers, we must keep track
73 of the register class needed for each reload, and make sure that
74 we allocate enough reload registers of each class.
76 The file reload.c contains the code that checks one insn for
77 validity and reports the reloads that it needs. This file
78 is in charge of scanning the entire rtl code, accumulating the
79 reload needs, spilling, assigning reload registers to use for
80 fixing up each insn, and generating the new insns to copy values
81 into the reload registers. */
83 struct target_reload default_target_reload
;
85 struct target_reload
*this_target_reload
= &default_target_reload
;
88 #define spill_indirect_levels \
89 (this_target_reload->x_spill_indirect_levels)
91 /* During reload_as_needed, element N contains a REG rtx for the hard reg
92 into which reg N has been reloaded (perhaps for a previous insn). */
93 static rtx
*reg_last_reload_reg
;
95 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
96 for an output reload that stores into reg N. */
97 static regset_head reg_has_output_reload
;
99 /* Indicates which hard regs are reload-registers for an output reload
100 in the current insn. */
101 static HARD_REG_SET reg_is_output_reload
;
103 /* Widest width in which each pseudo reg is referred to (via subreg). */
104 static unsigned int *reg_max_ref_width
;
106 /* Vector to remember old contents of reg_renumber before spilling. */
107 static short *reg_old_renumber
;
109 /* During reload_as_needed, element N contains the last pseudo regno reloaded
110 into hard register N. If that pseudo reg occupied more than one register,
111 reg_reloaded_contents points to that pseudo for each spill register in
112 use; all of these must remain set for an inheritance to occur. */
113 static int reg_reloaded_contents
[FIRST_PSEUDO_REGISTER
];
115 /* During reload_as_needed, element N contains the insn for which
116 hard register N was last used. Its contents are significant only
117 when reg_reloaded_valid is set for this register. */
118 static rtx reg_reloaded_insn
[FIRST_PSEUDO_REGISTER
];
120 /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid. */
121 static HARD_REG_SET reg_reloaded_valid
;
122 /* Indicate if the register was dead at the end of the reload.
123 This is only valid if reg_reloaded_contents is set and valid. */
124 static HARD_REG_SET reg_reloaded_dead
;
126 /* Indicate whether the register's current value is one that is not
127 safe to retain across a call, even for registers that are normally
128 call-saved. This is only meaningful for members of reg_reloaded_valid. */
129 static HARD_REG_SET reg_reloaded_call_part_clobbered
;
131 /* Number of spill-regs so far; number of valid elements of spill_regs. */
134 /* In parallel with spill_regs, contains REG rtx's for those regs.
135 Holds the last rtx used for any given reg, or 0 if it has never
136 been used for spilling yet. This rtx is reused, provided it has
138 static rtx spill_reg_rtx
[FIRST_PSEUDO_REGISTER
];
140 /* In parallel with spill_regs, contains nonzero for a spill reg
141 that was stored after the last time it was used.
142 The precise value is the insn generated to do the store. */
143 static rtx spill_reg_store
[FIRST_PSEUDO_REGISTER
];
145 /* This is the register that was stored with spill_reg_store. This is a
146 copy of reload_out / reload_out_reg when the value was stored; if
147 reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */
148 static rtx spill_reg_stored_to
[FIRST_PSEUDO_REGISTER
];
150 /* This table is the inverse mapping of spill_regs:
151 indexed by hard reg number,
152 it contains the position of that reg in spill_regs,
153 or -1 for something that is not in spill_regs.
155 ?!? This is no longer accurate. */
156 static short spill_reg_order
[FIRST_PSEUDO_REGISTER
];
158 /* This reg set indicates registers that can't be used as spill registers for
159 the currently processed insn. These are the hard registers which are live
160 during the insn, but not allocated to pseudos, as well as fixed
162 static HARD_REG_SET bad_spill_regs
;
164 /* These are the hard registers that can't be used as spill register for any
165 insn. This includes registers used for user variables and registers that
166 we can't eliminate. A register that appears in this set also can't be used
167 to retry register allocation. */
168 static HARD_REG_SET bad_spill_regs_global
;
170 /* Describes order of use of registers for reloading
171 of spilled pseudo-registers. `n_spills' is the number of
172 elements that are actually valid; new ones are added at the end.
174 Both spill_regs and spill_reg_order are used on two occasions:
175 once during find_reload_regs, where they keep track of the spill registers
176 for a single insn, but also during reload_as_needed where they show all
177 the registers ever used by reload. For the latter case, the information
178 is calculated during finish_spills. */
179 static short spill_regs
[FIRST_PSEUDO_REGISTER
];
181 /* This vector of reg sets indicates, for each pseudo, which hard registers
182 may not be used for retrying global allocation because the register was
183 formerly spilled from one of them. If we allowed reallocating a pseudo to
184 a register that it was already allocated to, reload might not
186 static HARD_REG_SET
*pseudo_previous_regs
;
188 /* This vector of reg sets indicates, for each pseudo, which hard
189 registers may not be used for retrying global allocation because they
190 are used as spill registers during one of the insns in which the
192 static HARD_REG_SET
*pseudo_forbidden_regs
;
194 /* All hard regs that have been used as spill registers for any insn are
195 marked in this set. */
196 static HARD_REG_SET used_spill_regs
;
198 /* Index of last register assigned as a spill register. We allocate in
199 a round-robin fashion. */
200 static int last_spill_reg
;
202 /* Record the stack slot for each spilled hard register. */
203 static rtx spill_stack_slot
[FIRST_PSEUDO_REGISTER
];
205 /* Width allocated so far for that stack slot. */
206 static unsigned int spill_stack_slot_width
[FIRST_PSEUDO_REGISTER
];
208 /* Record which pseudos needed to be spilled. */
209 static regset_head spilled_pseudos
;
211 /* Record which pseudos changed their allocation in finish_spills. */
212 static regset_head changed_allocation_pseudos
;
214 /* Used for communication between order_regs_for_reload and count_pseudo.
215 Used to avoid counting one pseudo twice. */
216 static regset_head pseudos_counted
;
218 /* First uid used by insns created by reload in this function.
219 Used in find_equiv_reg. */
220 int reload_first_uid
;
222 /* Flag set by local-alloc or global-alloc if anything is live in
223 a call-clobbered reg across calls. */
224 int caller_save_needed
;
226 /* Set to 1 while reload_as_needed is operating.
227 Required by some machines to handle any generated moves differently. */
228 int reload_in_progress
= 0;
230 /* This obstack is used for allocation of rtl during register elimination.
231 The allocated storage can be freed once find_reloads has processed the
233 static struct obstack reload_obstack
;
235 /* Points to the beginning of the reload_obstack. All insn_chain structures
236 are allocated first. */
237 static char *reload_startobj
;
239 /* The point after all insn_chain structures. Used to quickly deallocate
240 memory allocated in copy_reloads during calculate_needs_all_insns. */
241 static char *reload_firstobj
;
243 /* This points before all local rtl generated by register elimination.
244 Used to quickly free all memory after processing one insn. */
245 static char *reload_insn_firstobj
;
247 /* List of insn_chain instructions, one for every insn that reload needs to
249 struct insn_chain
*reload_insn_chain
;
251 /* TRUE if we potentially left dead insns in the insn stream and want to
252 run DCE immediately after reload, FALSE otherwise. */
253 static bool need_dce
;
255 /* List of all insns needing reloads. */
256 static struct insn_chain
*insns_need_reload
;
258 /* This structure is used to record information about register eliminations.
259 Each array entry describes one possible way of eliminating a register
260 in favor of another. If there is more than one way of eliminating a
261 particular register, the most preferred should be specified first. */
265 int from
; /* Register number to be eliminated. */
266 int to
; /* Register number used as replacement. */
267 HOST_WIDE_INT initial_offset
; /* Initial difference between values. */
268 int can_eliminate
; /* Nonzero if this elimination can be done. */
269 int can_eliminate_previous
; /* Value returned by TARGET_CAN_ELIMINATE
270 target hook in previous scan over insns
272 HOST_WIDE_INT offset
; /* Current offset between the two regs. */
273 HOST_WIDE_INT previous_offset
;/* Offset at end of previous insn. */
274 int ref_outside_mem
; /* "to" has been referenced outside a MEM. */
275 rtx from_rtx
; /* REG rtx for the register to be eliminated.
276 We cannot simply compare the number since
277 we might then spuriously replace a hard
278 register corresponding to a pseudo
279 assigned to the reg to be eliminated. */
280 rtx to_rtx
; /* REG rtx for the replacement. */
283 static struct elim_table
*reg_eliminate
= 0;
285 /* This is an intermediate structure to initialize the table. It has
286 exactly the members provided by ELIMINABLE_REGS. */
287 static const struct elim_table_1
291 } reg_eliminate_1
[] =
293 /* If a set of eliminable registers was specified, define the table from it.
294 Otherwise, default to the normal case of the frame pointer being
295 replaced by the stack pointer. */
297 #ifdef ELIMINABLE_REGS
300 {{ FRAME_POINTER_REGNUM
, STACK_POINTER_REGNUM
}};
303 #define NUM_ELIMINABLE_REGS ARRAY_SIZE (reg_eliminate_1)
305 /* Record the number of pending eliminations that have an offset not equal
306 to their initial offset. If nonzero, we use a new copy of each
307 replacement result in any insns encountered. */
308 int num_not_at_initial_offset
;
310 /* Count the number of registers that we may be able to eliminate. */
311 static int num_eliminable
;
312 /* And the number of registers that are equivalent to a constant that
313 can be eliminated to frame_pointer / arg_pointer + constant. */
314 static int num_eliminable_invariants
;
316 /* For each label, we record the offset of each elimination. If we reach
317 a label by more than one path and an offset differs, we cannot do the
318 elimination. This information is indexed by the difference of the
319 number of the label and the first label number. We can't offset the
320 pointer itself as this can cause problems on machines with segmented
321 memory. The first table is an array of flags that records whether we
322 have yet encountered a label and the second table is an array of arrays,
323 one entry in the latter array for each elimination. */
325 static int first_label_num
;
326 static char *offsets_known_at
;
327 static HOST_WIDE_INT (*offsets_at
)[NUM_ELIMINABLE_REGS
];
329 vec
<reg_equivs_t
, va_gc
> *reg_equivs
;
331 /* Stack of addresses where an rtx has been changed. We can undo the
332 changes by popping items off the stack and restoring the original
333 value at each location.
335 We use this simplistic undo capability rather than copy_rtx as copy_rtx
336 will not make a deep copy of a normally sharable rtx, such as
337 (const (plus (symbol_ref) (const_int))). If such an expression appears
338 as R1 in gen_reload_chain_without_interm_reg_p, then a shared
339 rtx expression would be changed. See PR 42431. */
342 static vec
<rtx_p
> substitute_stack
;
344 /* Number of labels in the current function. */
346 static int num_labels
;
348 static void replace_pseudos_in (rtx
*, enum machine_mode
, rtx
);
349 static void maybe_fix_stack_asms (void);
350 static void copy_reloads (struct insn_chain
*);
351 static void calculate_needs_all_insns (int);
352 static int find_reg (struct insn_chain
*, int);
353 static void find_reload_regs (struct insn_chain
*);
354 static void select_reload_regs (void);
355 static void delete_caller_save_insns (void);
357 static void spill_failure (rtx
, enum reg_class
);
358 static void count_spilled_pseudo (int, int, int);
359 static void delete_dead_insn (rtx
);
360 static void alter_reg (int, int, bool);
361 static void set_label_offsets (rtx
, rtx
, int);
362 static void check_eliminable_occurrences (rtx
);
363 static void elimination_effects (rtx
, enum machine_mode
);
364 static rtx
eliminate_regs_1 (rtx
, enum machine_mode
, rtx
, bool, bool);
365 static int eliminate_regs_in_insn (rtx
, int);
366 static void update_eliminable_offsets (void);
367 static void mark_not_eliminable (rtx
, const_rtx
, void *);
368 static void set_initial_elim_offsets (void);
369 static bool verify_initial_elim_offsets (void);
370 static void set_initial_label_offsets (void);
371 static void set_offsets_for_label (rtx
);
372 static void init_eliminable_invariants (rtx
, bool);
373 static void init_elim_table (void);
374 static void free_reg_equiv (void);
375 static void update_eliminables (HARD_REG_SET
*);
376 static void elimination_costs_in_insn (rtx
);
377 static void spill_hard_reg (unsigned int, int);
378 static int finish_spills (int);
379 static void scan_paradoxical_subregs (rtx
);
380 static void count_pseudo (int);
381 static void order_regs_for_reload (struct insn_chain
*);
382 static void reload_as_needed (int);
383 static void forget_old_reloads_1 (rtx
, const_rtx
, void *);
384 static void forget_marked_reloads (regset
);
385 static int reload_reg_class_lower (const void *, const void *);
386 static void mark_reload_reg_in_use (unsigned int, int, enum reload_type
,
388 static void clear_reload_reg_in_use (unsigned int, int, enum reload_type
,
390 static int reload_reg_free_p (unsigned int, int, enum reload_type
);
391 static int reload_reg_free_for_value_p (int, int, int, enum reload_type
,
393 static int free_for_value_p (int, enum machine_mode
, int, enum reload_type
,
395 static int allocate_reload_reg (struct insn_chain
*, int, int);
396 static int conflicts_with_override (rtx
);
397 static void failed_reload (rtx
, int);
398 static int set_reload_reg (int, int);
399 static void choose_reload_regs_init (struct insn_chain
*, rtx
*);
400 static void choose_reload_regs (struct insn_chain
*);
401 static void emit_input_reload_insns (struct insn_chain
*, struct reload
*,
403 static void emit_output_reload_insns (struct insn_chain
*, struct reload
*,
405 static void do_input_reload (struct insn_chain
*, struct reload
*, int);
406 static void do_output_reload (struct insn_chain
*, struct reload
*, int);
407 static void emit_reload_insns (struct insn_chain
*);
408 static void delete_output_reload (rtx
, int, int, rtx
);
409 static void delete_address_reloads (rtx
, rtx
);
410 static void delete_address_reloads_1 (rtx
, rtx
, rtx
);
411 static void inc_for_reload (rtx
, rtx
, rtx
, int);
413 static void add_auto_inc_notes (rtx
, rtx
);
415 static void substitute (rtx
*, const_rtx
, rtx
);
416 static bool gen_reload_chain_without_interm_reg_p (int, int);
417 static int reloads_conflict (int, int);
418 static rtx
gen_reload (rtx
, rtx
, int, enum reload_type
);
419 static rtx
emit_insn_if_valid_for_reload (rtx
);
421 /* Initialize the reload pass. This is called at the beginning of compilation
422 and may be called again if the target is reinitialized. */
429 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
430 Set spill_indirect_levels to the number of levels such addressing is
431 permitted, zero if it is not permitted at all. */
434 = gen_rtx_MEM (Pmode
,
437 LAST_VIRTUAL_REGISTER
+ 1),
439 spill_indirect_levels
= 0;
441 while (memory_address_p (QImode
, tem
))
443 spill_indirect_levels
++;
444 tem
= gen_rtx_MEM (Pmode
, tem
);
447 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
449 tem
= gen_rtx_MEM (Pmode
, gen_rtx_SYMBOL_REF (Pmode
, "foo"));
450 indirect_symref_ok
= memory_address_p (QImode
, tem
);
452 /* See if reg+reg is a valid (and offsettable) address. */
454 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
456 tem
= gen_rtx_PLUS (Pmode
,
457 gen_rtx_REG (Pmode
, HARD_FRAME_POINTER_REGNUM
),
458 gen_rtx_REG (Pmode
, i
));
460 /* This way, we make sure that reg+reg is an offsettable address. */
461 tem
= plus_constant (Pmode
, tem
, 4);
463 if (memory_address_p (QImode
, tem
))
465 double_reg_address_ok
= 1;
470 /* Initialize obstack for our rtl allocation. */
471 if (reload_startobj
== NULL
)
473 gcc_obstack_init (&reload_obstack
);
474 reload_startobj
= XOBNEWVAR (&reload_obstack
, char, 0);
477 INIT_REG_SET (&spilled_pseudos
);
478 INIT_REG_SET (&changed_allocation_pseudos
);
479 INIT_REG_SET (&pseudos_counted
);
482 /* List of insn chains that are currently unused. */
483 static struct insn_chain
*unused_insn_chains
= 0;
485 /* Allocate an empty insn_chain structure. */
487 new_insn_chain (void)
489 struct insn_chain
*c
;
491 if (unused_insn_chains
== 0)
493 c
= XOBNEW (&reload_obstack
, struct insn_chain
);
494 INIT_REG_SET (&c
->live_throughout
);
495 INIT_REG_SET (&c
->dead_or_set
);
499 c
= unused_insn_chains
;
500 unused_insn_chains
= c
->next
;
502 c
->is_caller_save_insn
= 0;
503 c
->need_operand_change
= 0;
509 /* Small utility function to set all regs in hard reg set TO which are
510 allocated to pseudos in regset FROM. */
513 compute_use_by_pseudos (HARD_REG_SET
*to
, regset from
)
516 reg_set_iterator rsi
;
518 EXECUTE_IF_SET_IN_REG_SET (from
, FIRST_PSEUDO_REGISTER
, regno
, rsi
)
520 int r
= reg_renumber
[regno
];
524 /* reload_combine uses the information from DF_LIVE_IN,
525 which might still contain registers that have not
526 actually been allocated since they have an
528 gcc_assert (ira_conflicts_p
|| reload_completed
);
531 add_to_hard_reg_set (to
, PSEUDO_REGNO_MODE (regno
), r
);
535 /* Replace all pseudos found in LOC with their corresponding
539 replace_pseudos_in (rtx
*loc
, enum machine_mode mem_mode
, rtx usage
)
552 unsigned int regno
= REGNO (x
);
554 if (regno
< FIRST_PSEUDO_REGISTER
)
557 x
= eliminate_regs_1 (x
, mem_mode
, usage
, true, false);
561 replace_pseudos_in (loc
, mem_mode
, usage
);
565 if (reg_equiv_constant (regno
))
566 *loc
= reg_equiv_constant (regno
);
567 else if (reg_equiv_invariant (regno
))
568 *loc
= reg_equiv_invariant (regno
);
569 else if (reg_equiv_mem (regno
))
570 *loc
= reg_equiv_mem (regno
);
571 else if (reg_equiv_address (regno
))
572 *loc
= gen_rtx_MEM (GET_MODE (x
), reg_equiv_address (regno
));
575 gcc_assert (!REG_P (regno_reg_rtx
[regno
])
576 || REGNO (regno_reg_rtx
[regno
]) != regno
);
577 *loc
= regno_reg_rtx
[regno
];
582 else if (code
== MEM
)
584 replace_pseudos_in (& XEXP (x
, 0), GET_MODE (x
), usage
);
588 /* Process each of our operands recursively. */
589 fmt
= GET_RTX_FORMAT (code
);
590 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++, fmt
++)
592 replace_pseudos_in (&XEXP (x
, i
), mem_mode
, usage
);
593 else if (*fmt
== 'E')
594 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
595 replace_pseudos_in (& XVECEXP (x
, i
, j
), mem_mode
, usage
);
598 /* Determine if the current function has an exception receiver block
599 that reaches the exit block via non-exceptional edges */
602 has_nonexceptional_receiver (void)
606 basic_block
*tos
, *worklist
, bb
;
608 /* If we're not optimizing, then just err on the safe side. */
612 /* First determine which blocks can reach exit via normal paths. */
613 tos
= worklist
= XNEWVEC (basic_block
, n_basic_blocks
+ 1);
616 bb
->flags
&= ~BB_REACHABLE
;
618 /* Place the exit block on our worklist. */
619 EXIT_BLOCK_PTR
->flags
|= BB_REACHABLE
;
620 *tos
++ = EXIT_BLOCK_PTR
;
622 /* Iterate: find everything reachable from what we've already seen. */
623 while (tos
!= worklist
)
627 FOR_EACH_EDGE (e
, ei
, bb
->preds
)
628 if (!(e
->flags
& EDGE_ABNORMAL
))
630 basic_block src
= e
->src
;
632 if (!(src
->flags
& BB_REACHABLE
))
634 src
->flags
|= BB_REACHABLE
;
641 /* Now see if there's a reachable block with an exceptional incoming
644 if (bb
->flags
& BB_REACHABLE
&& bb_has_abnormal_pred (bb
))
647 /* No exceptional block reached exit unexceptionally. */
651 /* Grow (or allocate) the REG_EQUIVS array from its current size (which may be
652 zero elements) to MAX_REG_NUM elements.
654 Initialize all new fields to NULL and update REG_EQUIVS_SIZE. */
656 grow_reg_equivs (void)
658 int old_size
= vec_safe_length (reg_equivs
);
659 int max_regno
= max_reg_num ();
663 memset (&ze
, 0, sizeof (reg_equivs_t
));
664 vec_safe_reserve (reg_equivs
, max_regno
);
665 for (i
= old_size
; i
< max_regno
; i
++)
666 reg_equivs
->quick_insert (i
, ze
);
670 /* Global variables used by reload and its subroutines. */
672 /* The current basic block while in calculate_elim_costs_all_insns. */
673 static basic_block elim_bb
;
675 /* Set during calculate_needs if an insn needs register elimination. */
676 static int something_needs_elimination
;
677 /* Set during calculate_needs if an insn needs an operand changed. */
678 static int something_needs_operands_changed
;
679 /* Set by alter_regs if we spilled a register to the stack. */
680 static bool something_was_spilled
;
682 /* Nonzero means we couldn't get enough spill regs. */
685 /* Temporary array of pseudo-register number. */
686 static int *temp_pseudo_reg_arr
;
688 /* Main entry point for the reload pass.
690 FIRST is the first insn of the function being compiled.
692 GLOBAL nonzero means we were called from global_alloc
693 and should attempt to reallocate any pseudoregs that we
694 displace from hard regs we will use for reloads.
695 If GLOBAL is zero, we do not have enough information to do that,
696 so any pseudo reg that is spilled must go to the stack.
698 Return value is TRUE if reload likely left dead insns in the
699 stream and a DCE pass should be run to elimiante them. Else the
700 return value is FALSE. */
703 reload (rtx first
, int global
)
707 struct elim_table
*ep
;
711 /* Make sure even insns with volatile mem refs are recognizable. */
716 reload_firstobj
= XOBNEWVAR (&reload_obstack
, char, 0);
718 /* Make sure that the last insn in the chain
719 is not something that needs reloading. */
720 emit_note (NOTE_INSN_DELETED
);
722 /* Enable find_equiv_reg to distinguish insns made by reload. */
723 reload_first_uid
= get_max_uid ();
725 #ifdef SECONDARY_MEMORY_NEEDED
726 /* Initialize the secondary memory table. */
727 clear_secondary_mem ();
730 /* We don't have a stack slot for any spill reg yet. */
731 memset (spill_stack_slot
, 0, sizeof spill_stack_slot
);
732 memset (spill_stack_slot_width
, 0, sizeof spill_stack_slot_width
);
734 /* Initialize the save area information for caller-save, in case some
738 /* Compute which hard registers are now in use
739 as homes for pseudo registers.
740 This is done here rather than (eg) in global_alloc
741 because this point is reached even if not optimizing. */
742 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
745 /* A function that has a nonlocal label that can reach the exit
746 block via non-exceptional paths must save all call-saved
748 if (cfun
->has_nonlocal_label
749 && has_nonexceptional_receiver ())
750 crtl
->saves_all_registers
= 1;
752 if (crtl
->saves_all_registers
)
753 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
754 if (! call_used_regs
[i
] && ! fixed_regs
[i
] && ! LOCAL_REGNO (i
))
755 df_set_regs_ever_live (i
, true);
757 /* Find all the pseudo registers that didn't get hard regs
758 but do have known equivalent constants or memory slots.
759 These include parameters (known equivalent to parameter slots)
760 and cse'd or loop-moved constant memory addresses.
762 Record constant equivalents in reg_equiv_constant
763 so they will be substituted by find_reloads.
764 Record memory equivalents in reg_mem_equiv so they can
765 be substituted eventually by altering the REG-rtx's. */
768 reg_old_renumber
= XCNEWVEC (short, max_regno
);
769 memcpy (reg_old_renumber
, reg_renumber
, max_regno
* sizeof (short));
770 pseudo_forbidden_regs
= XNEWVEC (HARD_REG_SET
, max_regno
);
771 pseudo_previous_regs
= XCNEWVEC (HARD_REG_SET
, max_regno
);
773 CLEAR_HARD_REG_SET (bad_spill_regs_global
);
775 init_eliminable_invariants (first
, true);
778 /* Alter each pseudo-reg rtx to contain its hard reg number. Assign
779 stack slots to the pseudos that lack hard regs or equivalents.
780 Do not touch virtual registers. */
782 temp_pseudo_reg_arr
= XNEWVEC (int, max_regno
- LAST_VIRTUAL_REGISTER
- 1);
783 for (n
= 0, i
= LAST_VIRTUAL_REGISTER
+ 1; i
< max_regno
; i
++)
784 temp_pseudo_reg_arr
[n
++] = i
;
787 /* Ask IRA to order pseudo-registers for better stack slot
789 ira_sort_regnos_for_alter_reg (temp_pseudo_reg_arr
, n
, reg_max_ref_width
);
791 for (i
= 0; i
< n
; i
++)
792 alter_reg (temp_pseudo_reg_arr
[i
], -1, false);
794 /* If we have some registers we think can be eliminated, scan all insns to
795 see if there is an insn that sets one of these registers to something
796 other than itself plus a constant. If so, the register cannot be
797 eliminated. Doing this scan here eliminates an extra pass through the
798 main reload loop in the most common case where register elimination
800 for (insn
= first
; insn
&& num_eliminable
; insn
= NEXT_INSN (insn
))
802 note_stores (PATTERN (insn
), mark_not_eliminable
, NULL
);
804 maybe_fix_stack_asms ();
806 insns_need_reload
= 0;
807 something_needs_elimination
= 0;
809 /* Initialize to -1, which means take the first spill register. */
812 /* Spill any hard regs that we know we can't eliminate. */
813 CLEAR_HARD_REG_SET (used_spill_regs
);
814 /* There can be multiple ways to eliminate a register;
815 they should be listed adjacently.
816 Elimination for any register fails only if all possible ways fail. */
817 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; )
820 int can_eliminate
= 0;
823 can_eliminate
|= ep
->can_eliminate
;
826 while (ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
] && ep
->from
== from
);
828 spill_hard_reg (from
, 1);
831 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
832 if (frame_pointer_needed
)
833 spill_hard_reg (HARD_FRAME_POINTER_REGNUM
, 1);
835 finish_spills (global
);
837 /* From now on, we may need to generate moves differently. We may also
838 allow modifications of insns which cause them to not be recognized.
839 Any such modifications will be cleaned up during reload itself. */
840 reload_in_progress
= 1;
842 /* This loop scans the entire function each go-round
843 and repeats until one repetition spills no additional hard regs. */
846 int something_changed
;
848 HOST_WIDE_INT starting_frame_size
;
850 starting_frame_size
= get_frame_size ();
851 something_was_spilled
= false;
853 set_initial_elim_offsets ();
854 set_initial_label_offsets ();
856 /* For each pseudo register that has an equivalent location defined,
857 try to eliminate any eliminable registers (such as the frame pointer)
858 assuming initial offsets for the replacement register, which
861 If the resulting location is directly addressable, substitute
862 the MEM we just got directly for the old REG.
864 If it is not addressable but is a constant or the sum of a hard reg
865 and constant, it is probably not addressable because the constant is
866 out of range, in that case record the address; we will generate
867 hairy code to compute the address in a register each time it is
868 needed. Similarly if it is a hard register, but one that is not
869 valid as an address register.
871 If the location is not addressable, but does not have one of the
872 above forms, assign a stack slot. We have to do this to avoid the
873 potential of producing lots of reloads if, e.g., a location involves
874 a pseudo that didn't get a hard register and has an equivalent memory
875 location that also involves a pseudo that didn't get a hard register.
877 Perhaps at some point we will improve reload_when_needed handling
878 so this problem goes away. But that's very hairy. */
880 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
881 if (reg_renumber
[i
] < 0 && reg_equiv_memory_loc (i
))
883 rtx x
= eliminate_regs (reg_equiv_memory_loc (i
), VOIDmode
,
886 if (strict_memory_address_addr_space_p
887 (GET_MODE (regno_reg_rtx
[i
]), XEXP (x
, 0),
889 reg_equiv_mem (i
) = x
, reg_equiv_address (i
) = 0;
890 else if (CONSTANT_P (XEXP (x
, 0))
891 || (REG_P (XEXP (x
, 0))
892 && REGNO (XEXP (x
, 0)) < FIRST_PSEUDO_REGISTER
)
893 || (GET_CODE (XEXP (x
, 0)) == PLUS
894 && REG_P (XEXP (XEXP (x
, 0), 0))
895 && (REGNO (XEXP (XEXP (x
, 0), 0))
896 < FIRST_PSEUDO_REGISTER
)
897 && CONSTANT_P (XEXP (XEXP (x
, 0), 1))))
898 reg_equiv_address (i
) = XEXP (x
, 0), reg_equiv_mem (i
) = 0;
901 /* Make a new stack slot. Then indicate that something
902 changed so we go back and recompute offsets for
903 eliminable registers because the allocation of memory
904 below might change some offset. reg_equiv_{mem,address}
905 will be set up for this pseudo on the next pass around
907 reg_equiv_memory_loc (i
) = 0;
908 reg_equiv_init (i
) = 0;
909 alter_reg (i
, -1, true);
913 if (caller_save_needed
)
916 /* If we allocated another stack slot, redo elimination bookkeeping. */
917 if (something_was_spilled
|| starting_frame_size
!= get_frame_size ())
919 if (starting_frame_size
&& crtl
->stack_alignment_needed
)
921 /* If we have a stack frame, we must align it now. The
922 stack size may be a part of the offset computation for
923 register elimination. So if this changes the stack size,
924 then repeat the elimination bookkeeping. We don't
925 realign when there is no stack, as that will cause a
926 stack frame when none is needed should
927 STARTING_FRAME_OFFSET not be already aligned to
929 assign_stack_local (BLKmode
, 0, crtl
->stack_alignment_needed
);
930 if (starting_frame_size
!= get_frame_size ())
934 if (caller_save_needed
)
936 save_call_clobbered_regs ();
937 /* That might have allocated new insn_chain structures. */
938 reload_firstobj
= XOBNEWVAR (&reload_obstack
, char, 0);
941 calculate_needs_all_insns (global
);
943 if (! ira_conflicts_p
)
944 /* Don't do it for IRA. We need this info because we don't
945 change live_throughout and dead_or_set for chains when IRA
947 CLEAR_REG_SET (&spilled_pseudos
);
951 something_changed
= 0;
953 /* If we allocated any new memory locations, make another pass
954 since it might have changed elimination offsets. */
955 if (something_was_spilled
|| starting_frame_size
!= get_frame_size ())
956 something_changed
= 1;
958 /* Even if the frame size remained the same, we might still have
959 changed elimination offsets, e.g. if find_reloads called
960 force_const_mem requiring the back end to allocate a constant
961 pool base register that needs to be saved on the stack. */
962 else if (!verify_initial_elim_offsets ())
963 something_changed
= 1;
966 HARD_REG_SET to_spill
;
967 CLEAR_HARD_REG_SET (to_spill
);
968 update_eliminables (&to_spill
);
969 AND_COMPL_HARD_REG_SET (used_spill_regs
, to_spill
);
971 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
972 if (TEST_HARD_REG_BIT (to_spill
, i
))
974 spill_hard_reg (i
, 1);
977 /* Regardless of the state of spills, if we previously had
978 a register that we thought we could eliminate, but now can
979 not eliminate, we must run another pass.
981 Consider pseudos which have an entry in reg_equiv_* which
982 reference an eliminable register. We must make another pass
983 to update reg_equiv_* so that we do not substitute in the
984 old value from when we thought the elimination could be
986 something_changed
= 1;
990 select_reload_regs ();
994 if (insns_need_reload
!= 0 || did_spill
)
995 something_changed
|= finish_spills (global
);
997 if (! something_changed
)
1000 if (caller_save_needed
)
1001 delete_caller_save_insns ();
1003 obstack_free (&reload_obstack
, reload_firstobj
);
1006 /* If global-alloc was run, notify it of any register eliminations we have
1009 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
1010 if (ep
->can_eliminate
)
1011 mark_elimination (ep
->from
, ep
->to
);
1013 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
1014 If that insn didn't set the register (i.e., it copied the register to
1015 memory), just delete that insn instead of the equivalencing insn plus
1016 anything now dead. If we call delete_dead_insn on that insn, we may
1017 delete the insn that actually sets the register if the register dies
1018 there and that is incorrect. */
1020 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
1022 if (reg_renumber
[i
] < 0 && reg_equiv_init (i
) != 0)
1025 for (list
= reg_equiv_init (i
); list
; list
= XEXP (list
, 1))
1027 rtx equiv_insn
= XEXP (list
, 0);
1029 /* If we already deleted the insn or if it may trap, we can't
1030 delete it. The latter case shouldn't happen, but can
1031 if an insn has a variable address, gets a REG_EH_REGION
1032 note added to it, and then gets converted into a load
1033 from a constant address. */
1034 if (NOTE_P (equiv_insn
)
1035 || can_throw_internal (equiv_insn
))
1037 else if (reg_set_p (regno_reg_rtx
[i
], PATTERN (equiv_insn
)))
1038 delete_dead_insn (equiv_insn
);
1040 SET_INSN_DELETED (equiv_insn
);
1045 /* Use the reload registers where necessary
1046 by generating move instructions to move the must-be-register
1047 values into or out of the reload registers. */
1049 if (insns_need_reload
!= 0 || something_needs_elimination
1050 || something_needs_operands_changed
)
1052 HOST_WIDE_INT old_frame_size
= get_frame_size ();
1054 reload_as_needed (global
);
1056 gcc_assert (old_frame_size
== get_frame_size ());
1058 gcc_assert (verify_initial_elim_offsets ());
1061 /* If we were able to eliminate the frame pointer, show that it is no
1062 longer live at the start of any basic block. If it ls live by
1063 virtue of being in a pseudo, that pseudo will be marked live
1064 and hence the frame pointer will be known to be live via that
1067 if (! frame_pointer_needed
)
1069 bitmap_clear_bit (df_get_live_in (bb
), HARD_FRAME_POINTER_REGNUM
);
1071 /* Come here (with failure set nonzero) if we can't get enough spill
1075 CLEAR_REG_SET (&changed_allocation_pseudos
);
1076 CLEAR_REG_SET (&spilled_pseudos
);
1077 reload_in_progress
= 0;
1079 /* Now eliminate all pseudo regs by modifying them into
1080 their equivalent memory references.
1081 The REG-rtx's for the pseudos are modified in place,
1082 so all insns that used to refer to them now refer to memory.
1084 For a reg that has a reg_equiv_address, all those insns
1085 were changed by reloading so that no insns refer to it any longer;
1086 but the DECL_RTL of a variable decl may refer to it,
1087 and if so this causes the debugging info to mention the variable. */
1089 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
1093 if (reg_equiv_mem (i
))
1094 addr
= XEXP (reg_equiv_mem (i
), 0);
1096 if (reg_equiv_address (i
))
1097 addr
= reg_equiv_address (i
);
1101 if (reg_renumber
[i
] < 0)
1103 rtx reg
= regno_reg_rtx
[i
];
1105 REG_USERVAR_P (reg
) = 0;
1106 PUT_CODE (reg
, MEM
);
1107 XEXP (reg
, 0) = addr
;
1108 if (reg_equiv_memory_loc (i
))
1109 MEM_COPY_ATTRIBUTES (reg
, reg_equiv_memory_loc (i
));
1111 MEM_ATTRS (reg
) = 0;
1112 MEM_NOTRAP_P (reg
) = 1;
1114 else if (reg_equiv_mem (i
))
1115 XEXP (reg_equiv_mem (i
), 0) = addr
;
1118 /* We don't want complex addressing modes in debug insns
1119 if simpler ones will do, so delegitimize equivalences
1121 if (MAY_HAVE_DEBUG_INSNS
&& reg_renumber
[i
] < 0)
1123 rtx reg
= regno_reg_rtx
[i
];
1127 if (reg_equiv_constant (i
))
1128 equiv
= reg_equiv_constant (i
);
1129 else if (reg_equiv_invariant (i
))
1130 equiv
= reg_equiv_invariant (i
);
1131 else if (reg
&& MEM_P (reg
))
1132 equiv
= targetm
.delegitimize_address (reg
);
1133 else if (reg
&& REG_P (reg
) && (int)REGNO (reg
) != i
)
1139 for (use
= DF_REG_USE_CHAIN (i
); use
; use
= next
)
1141 insn
= DF_REF_INSN (use
);
1143 /* Make sure the next ref is for a different instruction,
1144 so that we're not affected by the rescan. */
1145 next
= DF_REF_NEXT_REG (use
);
1146 while (next
&& DF_REF_INSN (next
) == insn
)
1147 next
= DF_REF_NEXT_REG (next
);
1149 if (DEBUG_INSN_P (insn
))
1153 INSN_VAR_LOCATION_LOC (insn
) = gen_rtx_UNKNOWN_VAR_LOC ();
1154 df_insn_rescan_debug_internal (insn
);
1157 INSN_VAR_LOCATION_LOC (insn
)
1158 = simplify_replace_rtx (INSN_VAR_LOCATION_LOC (insn
),
1165 /* We must set reload_completed now since the cleanup_subreg_operands call
1166 below will re-recognize each insn and reload may have generated insns
1167 which are only valid during and after reload. */
1168 reload_completed
= 1;
1170 /* Make a pass over all the insns and delete all USEs which we inserted
1171 only to tag a REG_EQUAL note on them. Remove all REG_DEAD and REG_UNUSED
1172 notes. Delete all CLOBBER insns, except those that refer to the return
1173 value and the special mem:BLK CLOBBERs added to prevent the scheduler
1174 from misarranging variable-array code, and simplify (subreg (reg))
1175 operands. Strip and regenerate REG_INC notes that may have been moved
1178 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
1184 replace_pseudos_in (& CALL_INSN_FUNCTION_USAGE (insn
),
1185 VOIDmode
, CALL_INSN_FUNCTION_USAGE (insn
));
1187 if ((GET_CODE (PATTERN (insn
)) == USE
1188 /* We mark with QImode USEs introduced by reload itself. */
1189 && (GET_MODE (insn
) == QImode
1190 || find_reg_note (insn
, REG_EQUAL
, NULL_RTX
)))
1191 || (GET_CODE (PATTERN (insn
)) == CLOBBER
1192 && (!MEM_P (XEXP (PATTERN (insn
), 0))
1193 || GET_MODE (XEXP (PATTERN (insn
), 0)) != BLKmode
1194 || (GET_CODE (XEXP (XEXP (PATTERN (insn
), 0), 0)) != SCRATCH
1195 && XEXP (XEXP (PATTERN (insn
), 0), 0)
1196 != stack_pointer_rtx
))
1197 && (!REG_P (XEXP (PATTERN (insn
), 0))
1198 || ! REG_FUNCTION_VALUE_P (XEXP (PATTERN (insn
), 0)))))
1204 /* Some CLOBBERs may survive until here and still reference unassigned
1205 pseudos with const equivalent, which may in turn cause ICE in later
1206 passes if the reference remains in place. */
1207 if (GET_CODE (PATTERN (insn
)) == CLOBBER
)
1208 replace_pseudos_in (& XEXP (PATTERN (insn
), 0),
1209 VOIDmode
, PATTERN (insn
));
1211 /* Discard obvious no-ops, even without -O. This optimization
1212 is fast and doesn't interfere with debugging. */
1213 if (NONJUMP_INSN_P (insn
)
1214 && GET_CODE (PATTERN (insn
)) == SET
1215 && REG_P (SET_SRC (PATTERN (insn
)))
1216 && REG_P (SET_DEST (PATTERN (insn
)))
1217 && (REGNO (SET_SRC (PATTERN (insn
)))
1218 == REGNO (SET_DEST (PATTERN (insn
)))))
1224 pnote
= ®_NOTES (insn
);
1227 if (REG_NOTE_KIND (*pnote
) == REG_DEAD
1228 || REG_NOTE_KIND (*pnote
) == REG_UNUSED
1229 || REG_NOTE_KIND (*pnote
) == REG_INC
)
1230 *pnote
= XEXP (*pnote
, 1);
1232 pnote
= &XEXP (*pnote
, 1);
1236 add_auto_inc_notes (insn
, PATTERN (insn
));
1239 /* Simplify (subreg (reg)) if it appears as an operand. */
1240 cleanup_subreg_operands (insn
);
1242 /* Clean up invalid ASMs so that they don't confuse later passes.
1244 if (asm_noperands (PATTERN (insn
)) >= 0)
1246 extract_insn (insn
);
1247 if (!constrain_operands (1))
1249 error_for_asm (insn
,
1250 "%<asm%> operand has impossible constraints");
1257 /* If we are doing generic stack checking, give a warning if this
1258 function's frame size is larger than we expect. */
1259 if (flag_stack_check
== GENERIC_STACK_CHECK
)
1261 HOST_WIDE_INT size
= get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE
;
1262 static int verbose_warned
= 0;
1264 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1265 if (df_regs_ever_live_p (i
) && ! fixed_regs
[i
] && call_used_regs
[i
])
1266 size
+= UNITS_PER_WORD
;
1268 if (size
> STACK_CHECK_MAX_FRAME_SIZE
)
1270 warning (0, "frame size too large for reliable stack checking");
1271 if (! verbose_warned
)
1273 warning (0, "try reducing the number of local variables");
1279 free (temp_pseudo_reg_arr
);
1281 /* Indicate that we no longer have known memory locations or constants. */
1284 free (reg_max_ref_width
);
1285 free (reg_old_renumber
);
1286 free (pseudo_previous_regs
);
1287 free (pseudo_forbidden_regs
);
1289 CLEAR_HARD_REG_SET (used_spill_regs
);
1290 for (i
= 0; i
< n_spills
; i
++)
1291 SET_HARD_REG_BIT (used_spill_regs
, spill_regs
[i
]);
1293 /* Free all the insn_chain structures at once. */
1294 obstack_free (&reload_obstack
, reload_startobj
);
1295 unused_insn_chains
= 0;
1297 inserted
= fixup_abnormal_edges ();
1299 /* We've possibly turned single trapping insn into multiple ones. */
1300 if (cfun
->can_throw_non_call_exceptions
)
1303 blocks
= sbitmap_alloc (last_basic_block
);
1304 bitmap_ones (blocks
);
1305 find_many_sub_basic_blocks (blocks
);
1306 sbitmap_free (blocks
);
1310 commit_edge_insertions ();
1312 /* Replacing pseudos with their memory equivalents might have
1313 created shared rtx. Subsequent passes would get confused
1314 by this, so unshare everything here. */
1315 unshare_all_rtl_again (first
);
1317 #ifdef STACK_BOUNDARY
1318 /* init_emit has set the alignment of the hard frame pointer
1319 to STACK_BOUNDARY. It is very likely no longer valid if
1320 the hard frame pointer was used for register allocation. */
1321 if (!frame_pointer_needed
)
1322 REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM
) = BITS_PER_UNIT
;
1325 substitute_stack
.release ();
1327 gcc_assert (bitmap_empty_p (&spilled_pseudos
));
1329 reload_completed
= !failure
;
1334 /* Yet another special case. Unfortunately, reg-stack forces people to
1335 write incorrect clobbers in asm statements. These clobbers must not
1336 cause the register to appear in bad_spill_regs, otherwise we'll call
1337 fatal_insn later. We clear the corresponding regnos in the live
1338 register sets to avoid this.
1339 The whole thing is rather sick, I'm afraid. */
1342 maybe_fix_stack_asms (void)
1345 const char *constraints
[MAX_RECOG_OPERANDS
];
1346 enum machine_mode operand_mode
[MAX_RECOG_OPERANDS
];
1347 struct insn_chain
*chain
;
1349 for (chain
= reload_insn_chain
; chain
!= 0; chain
= chain
->next
)
1352 HARD_REG_SET clobbered
, allowed
;
1355 if (! INSN_P (chain
->insn
)
1356 || (noperands
= asm_noperands (PATTERN (chain
->insn
))) < 0)
1358 pat
= PATTERN (chain
->insn
);
1359 if (GET_CODE (pat
) != PARALLEL
)
1362 CLEAR_HARD_REG_SET (clobbered
);
1363 CLEAR_HARD_REG_SET (allowed
);
1365 /* First, make a mask of all stack regs that are clobbered. */
1366 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
1368 rtx t
= XVECEXP (pat
, 0, i
);
1369 if (GET_CODE (t
) == CLOBBER
&& STACK_REG_P (XEXP (t
, 0)))
1370 SET_HARD_REG_BIT (clobbered
, REGNO (XEXP (t
, 0)));
1373 /* Get the operand values and constraints out of the insn. */
1374 decode_asm_operands (pat
, recog_data
.operand
, recog_data
.operand_loc
,
1375 constraints
, operand_mode
, NULL
);
1377 /* For every operand, see what registers are allowed. */
1378 for (i
= 0; i
< noperands
; i
++)
1380 const char *p
= constraints
[i
];
1381 /* For every alternative, we compute the class of registers allowed
1382 for reloading in CLS, and merge its contents into the reg set
1384 int cls
= (int) NO_REGS
;
1390 if (c
== '\0' || c
== ',' || c
== '#')
1392 /* End of one alternative - mark the regs in the current
1393 class, and reset the class. */
1394 IOR_HARD_REG_SET (allowed
, reg_class_contents
[cls
]);
1400 } while (c
!= '\0' && c
!= ',');
1408 case '=': case '+': case '*': case '%': case '?': case '!':
1409 case '0': case '1': case '2': case '3': case '4': case '<':
1410 case '>': case 'V': case 'o': case '&': case 'E': case 'F':
1411 case 's': case 'i': case 'n': case 'X': case 'I': case 'J':
1412 case 'K': case 'L': case 'M': case 'N': case 'O': case 'P':
1413 case TARGET_MEM_CONSTRAINT
:
1417 cls
= (int) reg_class_subunion
[cls
]
1418 [(int) base_reg_class (VOIDmode
, ADDR_SPACE_GENERIC
,
1424 cls
= (int) reg_class_subunion
[cls
][(int) GENERAL_REGS
];
1428 if (EXTRA_ADDRESS_CONSTRAINT (c
, p
))
1429 cls
= (int) reg_class_subunion
[cls
]
1430 [(int) base_reg_class (VOIDmode
, ADDR_SPACE_GENERIC
,
1433 cls
= (int) reg_class_subunion
[cls
]
1434 [(int) REG_CLASS_FROM_CONSTRAINT (c
, p
)];
1436 p
+= CONSTRAINT_LEN (c
, p
);
1439 /* Those of the registers which are clobbered, but allowed by the
1440 constraints, must be usable as reload registers. So clear them
1441 out of the life information. */
1442 AND_HARD_REG_SET (allowed
, clobbered
);
1443 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1444 if (TEST_HARD_REG_BIT (allowed
, i
))
1446 CLEAR_REGNO_REG_SET (&chain
->live_throughout
, i
);
1447 CLEAR_REGNO_REG_SET (&chain
->dead_or_set
, i
);
1454 /* Copy the global variables n_reloads and rld into the corresponding elts
1457 copy_reloads (struct insn_chain
*chain
)
1459 chain
->n_reloads
= n_reloads
;
1460 chain
->rld
= XOBNEWVEC (&reload_obstack
, struct reload
, n_reloads
);
1461 memcpy (chain
->rld
, rld
, n_reloads
* sizeof (struct reload
));
1462 reload_insn_firstobj
= XOBNEWVAR (&reload_obstack
, char, 0);
1465 /* Walk the chain of insns, and determine for each whether it needs reloads
1466 and/or eliminations. Build the corresponding insns_need_reload list, and
1467 set something_needs_elimination as appropriate. */
1469 calculate_needs_all_insns (int global
)
1471 struct insn_chain
**pprev_reload
= &insns_need_reload
;
1472 struct insn_chain
*chain
, *next
= 0;
1474 something_needs_elimination
= 0;
1476 reload_insn_firstobj
= XOBNEWVAR (&reload_obstack
, char, 0);
1477 for (chain
= reload_insn_chain
; chain
!= 0; chain
= next
)
1479 rtx insn
= chain
->insn
;
1483 /* Clear out the shortcuts. */
1484 chain
->n_reloads
= 0;
1485 chain
->need_elim
= 0;
1486 chain
->need_reload
= 0;
1487 chain
->need_operand_change
= 0;
1489 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1490 include REG_LABEL_OPERAND and REG_LABEL_TARGET), we need to see
1491 what effects this has on the known offsets at labels. */
1493 if (LABEL_P (insn
) || JUMP_P (insn
)
1494 || (INSN_P (insn
) && REG_NOTES (insn
) != 0))
1495 set_label_offsets (insn
, insn
, 0);
1499 rtx old_body
= PATTERN (insn
);
1500 int old_code
= INSN_CODE (insn
);
1501 rtx old_notes
= REG_NOTES (insn
);
1502 int did_elimination
= 0;
1503 int operands_changed
= 0;
1504 rtx set
= single_set (insn
);
1506 /* Skip insns that only set an equivalence. */
1507 if (set
&& REG_P (SET_DEST (set
))
1508 && reg_renumber
[REGNO (SET_DEST (set
))] < 0
1509 && (reg_equiv_constant (REGNO (SET_DEST (set
)))
1510 || (reg_equiv_invariant (REGNO (SET_DEST (set
)))))
1511 && reg_equiv_init (REGNO (SET_DEST (set
))))
1514 /* If needed, eliminate any eliminable registers. */
1515 if (num_eliminable
|| num_eliminable_invariants
)
1516 did_elimination
= eliminate_regs_in_insn (insn
, 0);
1518 /* Analyze the instruction. */
1519 operands_changed
= find_reloads (insn
, 0, spill_indirect_levels
,
1520 global
, spill_reg_order
);
1522 /* If a no-op set needs more than one reload, this is likely
1523 to be something that needs input address reloads. We
1524 can't get rid of this cleanly later, and it is of no use
1525 anyway, so discard it now.
1526 We only do this when expensive_optimizations is enabled,
1527 since this complements reload inheritance / output
1528 reload deletion, and it can make debugging harder. */
1529 if (flag_expensive_optimizations
&& n_reloads
> 1)
1531 rtx set
= single_set (insn
);
1534 ((SET_SRC (set
) == SET_DEST (set
)
1535 && REG_P (SET_SRC (set
))
1536 && REGNO (SET_SRC (set
)) >= FIRST_PSEUDO_REGISTER
)
1537 || (REG_P (SET_SRC (set
)) && REG_P (SET_DEST (set
))
1538 && reg_renumber
[REGNO (SET_SRC (set
))] < 0
1539 && reg_renumber
[REGNO (SET_DEST (set
))] < 0
1540 && reg_equiv_memory_loc (REGNO (SET_SRC (set
))) != NULL
1541 && reg_equiv_memory_loc (REGNO (SET_DEST (set
))) != NULL
1542 && rtx_equal_p (reg_equiv_memory_loc (REGNO (SET_SRC (set
))),
1543 reg_equiv_memory_loc (REGNO (SET_DEST (set
)))))))
1545 if (ira_conflicts_p
)
1546 /* Inform IRA about the insn deletion. */
1547 ira_mark_memory_move_deletion (REGNO (SET_DEST (set
)),
1548 REGNO (SET_SRC (set
)));
1550 /* Delete it from the reload chain. */
1552 chain
->prev
->next
= next
;
1554 reload_insn_chain
= next
;
1556 next
->prev
= chain
->prev
;
1557 chain
->next
= unused_insn_chains
;
1558 unused_insn_chains
= chain
;
1563 update_eliminable_offsets ();
1565 /* Remember for later shortcuts which insns had any reloads or
1566 register eliminations. */
1567 chain
->need_elim
= did_elimination
;
1568 chain
->need_reload
= n_reloads
> 0;
1569 chain
->need_operand_change
= operands_changed
;
1571 /* Discard any register replacements done. */
1572 if (did_elimination
)
1574 obstack_free (&reload_obstack
, reload_insn_firstobj
);
1575 PATTERN (insn
) = old_body
;
1576 INSN_CODE (insn
) = old_code
;
1577 REG_NOTES (insn
) = old_notes
;
1578 something_needs_elimination
= 1;
1581 something_needs_operands_changed
|= operands_changed
;
1585 copy_reloads (chain
);
1586 *pprev_reload
= chain
;
1587 pprev_reload
= &chain
->next_need_reload
;
1594 /* This function is called from the register allocator to set up estimates
1595 for the cost of eliminating pseudos which have REG_EQUIV equivalences to
1596 an invariant. The structure is similar to calculate_needs_all_insns. */
1599 calculate_elim_costs_all_insns (void)
1601 int *reg_equiv_init_cost
;
1605 reg_equiv_init_cost
= XCNEWVEC (int, max_regno
);
1607 init_eliminable_invariants (get_insns (), false);
1609 set_initial_elim_offsets ();
1610 set_initial_label_offsets ();
1617 FOR_BB_INSNS (bb
, insn
)
1619 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1620 include REG_LABEL_OPERAND and REG_LABEL_TARGET), we need to see
1621 what effects this has on the known offsets at labels. */
1623 if (LABEL_P (insn
) || JUMP_P (insn
)
1624 || (INSN_P (insn
) && REG_NOTES (insn
) != 0))
1625 set_label_offsets (insn
, insn
, 0);
1629 rtx set
= single_set (insn
);
1631 /* Skip insns that only set an equivalence. */
1632 if (set
&& REG_P (SET_DEST (set
))
1633 && reg_renumber
[REGNO (SET_DEST (set
))] < 0
1634 && (reg_equiv_constant (REGNO (SET_DEST (set
)))
1635 || reg_equiv_invariant (REGNO (SET_DEST (set
)))))
1637 unsigned regno
= REGNO (SET_DEST (set
));
1638 rtx init
= reg_equiv_init (regno
);
1641 rtx t
= eliminate_regs_1 (SET_SRC (set
), VOIDmode
, insn
,
1643 int cost
= set_src_cost (t
, optimize_bb_for_speed_p (bb
));
1644 int freq
= REG_FREQ_FROM_BB (bb
);
1646 reg_equiv_init_cost
[regno
] = cost
* freq
;
1650 /* If needed, eliminate any eliminable registers. */
1651 if (num_eliminable
|| num_eliminable_invariants
)
1652 elimination_costs_in_insn (insn
);
1655 update_eliminable_offsets ();
1659 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
1661 if (reg_equiv_invariant (i
))
1663 if (reg_equiv_init (i
))
1665 int cost
= reg_equiv_init_cost
[i
];
1668 "Reg %d has equivalence, initial gains %d\n", i
, cost
);
1670 ira_adjust_equiv_reg_cost (i
, cost
);
1676 "Reg %d had equivalence, but can't be eliminated\n",
1678 ira_adjust_equiv_reg_cost (i
, 0);
1683 free (reg_equiv_init_cost
);
1684 free (offsets_known_at
);
1687 offsets_known_at
= NULL
;
1690 /* Comparison function for qsort to decide which of two reloads
1691 should be handled first. *P1 and *P2 are the reload numbers. */
1694 reload_reg_class_lower (const void *r1p
, const void *r2p
)
1696 int r1
= *(const short *) r1p
, r2
= *(const short *) r2p
;
1699 /* Consider required reloads before optional ones. */
1700 t
= rld
[r1
].optional
- rld
[r2
].optional
;
1704 /* Count all solitary classes before non-solitary ones. */
1705 t
= ((reg_class_size
[(int) rld
[r2
].rclass
] == 1)
1706 - (reg_class_size
[(int) rld
[r1
].rclass
] == 1));
1710 /* Aside from solitaires, consider all multi-reg groups first. */
1711 t
= rld
[r2
].nregs
- rld
[r1
].nregs
;
1715 /* Consider reloads in order of increasing reg-class number. */
1716 t
= (int) rld
[r1
].rclass
- (int) rld
[r2
].rclass
;
1720 /* If reloads are equally urgent, sort by reload number,
1721 so that the results of qsort leave nothing to chance. */
1725 /* The cost of spilling each hard reg. */
1726 static int spill_cost
[FIRST_PSEUDO_REGISTER
];
1728 /* When spilling multiple hard registers, we use SPILL_COST for the first
1729 spilled hard reg and SPILL_ADD_COST for subsequent regs. SPILL_ADD_COST
1730 only the first hard reg for a multi-reg pseudo. */
1731 static int spill_add_cost
[FIRST_PSEUDO_REGISTER
];
1733 /* Map of hard regno to pseudo regno currently occupying the hard
1735 static int hard_regno_to_pseudo_regno
[FIRST_PSEUDO_REGISTER
];
1737 /* Update the spill cost arrays, considering that pseudo REG is live. */
1740 count_pseudo (int reg
)
1742 int freq
= REG_FREQ (reg
);
1743 int r
= reg_renumber
[reg
];
1746 /* Ignore spilled pseudo-registers which can be here only if IRA is used. */
1747 if (ira_conflicts_p
&& r
< 0)
1750 if (REGNO_REG_SET_P (&pseudos_counted
, reg
)
1751 || REGNO_REG_SET_P (&spilled_pseudos
, reg
))
1754 SET_REGNO_REG_SET (&pseudos_counted
, reg
);
1756 gcc_assert (r
>= 0);
1758 spill_add_cost
[r
] += freq
;
1759 nregs
= hard_regno_nregs
[r
][PSEUDO_REGNO_MODE (reg
)];
1762 hard_regno_to_pseudo_regno
[r
+ nregs
] = reg
;
1763 spill_cost
[r
+ nregs
] += freq
;
1767 /* Calculate the SPILL_COST and SPILL_ADD_COST arrays and determine the
1768 contents of BAD_SPILL_REGS for the insn described by CHAIN. */
1771 order_regs_for_reload (struct insn_chain
*chain
)
1774 HARD_REG_SET used_by_pseudos
;
1775 HARD_REG_SET used_by_pseudos2
;
1776 reg_set_iterator rsi
;
1778 COPY_HARD_REG_SET (bad_spill_regs
, fixed_reg_set
);
1780 memset (spill_cost
, 0, sizeof spill_cost
);
1781 memset (spill_add_cost
, 0, sizeof spill_add_cost
);
1782 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1783 hard_regno_to_pseudo_regno
[i
] = -1;
1785 /* Count number of uses of each hard reg by pseudo regs allocated to it
1786 and then order them by decreasing use. First exclude hard registers
1787 that are live in or across this insn. */
1789 REG_SET_TO_HARD_REG_SET (used_by_pseudos
, &chain
->live_throughout
);
1790 REG_SET_TO_HARD_REG_SET (used_by_pseudos2
, &chain
->dead_or_set
);
1791 IOR_HARD_REG_SET (bad_spill_regs
, used_by_pseudos
);
1792 IOR_HARD_REG_SET (bad_spill_regs
, used_by_pseudos2
);
1794 /* Now find out which pseudos are allocated to it, and update
1796 CLEAR_REG_SET (&pseudos_counted
);
1798 EXECUTE_IF_SET_IN_REG_SET
1799 (&chain
->live_throughout
, FIRST_PSEUDO_REGISTER
, i
, rsi
)
1803 EXECUTE_IF_SET_IN_REG_SET
1804 (&chain
->dead_or_set
, FIRST_PSEUDO_REGISTER
, i
, rsi
)
1808 CLEAR_REG_SET (&pseudos_counted
);
1811 /* Vector of reload-numbers showing the order in which the reloads should
1813 static short reload_order
[MAX_RELOADS
];
1815 /* This is used to keep track of the spill regs used in one insn. */
1816 static HARD_REG_SET used_spill_regs_local
;
1818 /* We decided to spill hard register SPILLED, which has a size of
1819 SPILLED_NREGS. Determine how pseudo REG, which is live during the insn,
1820 is affected. We will add it to SPILLED_PSEUDOS if necessary, and we will
1821 update SPILL_COST/SPILL_ADD_COST. */
1824 count_spilled_pseudo (int spilled
, int spilled_nregs
, int reg
)
1826 int freq
= REG_FREQ (reg
);
1827 int r
= reg_renumber
[reg
];
1830 /* Ignore spilled pseudo-registers which can be here only if IRA is used. */
1831 if (ira_conflicts_p
&& r
< 0)
1834 gcc_assert (r
>= 0);
1836 nregs
= hard_regno_nregs
[r
][PSEUDO_REGNO_MODE (reg
)];
1838 if (REGNO_REG_SET_P (&spilled_pseudos
, reg
)
1839 || spilled
+ spilled_nregs
<= r
|| r
+ nregs
<= spilled
)
1842 SET_REGNO_REG_SET (&spilled_pseudos
, reg
);
1844 spill_add_cost
[r
] -= freq
;
1847 hard_regno_to_pseudo_regno
[r
+ nregs
] = -1;
1848 spill_cost
[r
+ nregs
] -= freq
;
1852 /* Find reload register to use for reload number ORDER. */
1855 find_reg (struct insn_chain
*chain
, int order
)
1857 int rnum
= reload_order
[order
];
1858 struct reload
*rl
= rld
+ rnum
;
1859 int best_cost
= INT_MAX
;
1861 unsigned int i
, j
, n
;
1863 HARD_REG_SET not_usable
;
1864 HARD_REG_SET used_by_other_reload
;
1865 reg_set_iterator rsi
;
1866 static int regno_pseudo_regs
[FIRST_PSEUDO_REGISTER
];
1867 static int best_regno_pseudo_regs
[FIRST_PSEUDO_REGISTER
];
1869 COPY_HARD_REG_SET (not_usable
, bad_spill_regs
);
1870 IOR_HARD_REG_SET (not_usable
, bad_spill_regs_global
);
1871 IOR_COMPL_HARD_REG_SET (not_usable
, reg_class_contents
[rl
->rclass
]);
1873 CLEAR_HARD_REG_SET (used_by_other_reload
);
1874 for (k
= 0; k
< order
; k
++)
1876 int other
= reload_order
[k
];
1878 if (rld
[other
].regno
>= 0 && reloads_conflict (other
, rnum
))
1879 for (j
= 0; j
< rld
[other
].nregs
; j
++)
1880 SET_HARD_REG_BIT (used_by_other_reload
, rld
[other
].regno
+ j
);
1883 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1885 #ifdef REG_ALLOC_ORDER
1886 unsigned int regno
= reg_alloc_order
[i
];
1888 unsigned int regno
= i
;
1891 if (! TEST_HARD_REG_BIT (not_usable
, regno
)
1892 && ! TEST_HARD_REG_BIT (used_by_other_reload
, regno
)
1893 && HARD_REGNO_MODE_OK (regno
, rl
->mode
))
1895 int this_cost
= spill_cost
[regno
];
1897 unsigned int this_nregs
= hard_regno_nregs
[regno
][rl
->mode
];
1899 for (j
= 1; j
< this_nregs
; j
++)
1901 this_cost
+= spill_add_cost
[regno
+ j
];
1902 if ((TEST_HARD_REG_BIT (not_usable
, regno
+ j
))
1903 || TEST_HARD_REG_BIT (used_by_other_reload
, regno
+ j
))
1909 if (ira_conflicts_p
)
1911 /* Ask IRA to find a better pseudo-register for
1913 for (n
= j
= 0; j
< this_nregs
; j
++)
1915 int r
= hard_regno_to_pseudo_regno
[regno
+ j
];
1919 if (n
== 0 || regno_pseudo_regs
[n
- 1] != r
)
1920 regno_pseudo_regs
[n
++] = r
;
1922 regno_pseudo_regs
[n
++] = -1;
1924 || ira_better_spill_reload_regno_p (regno_pseudo_regs
,
1925 best_regno_pseudo_regs
,
1932 best_regno_pseudo_regs
[j
] = regno_pseudo_regs
[j
];
1933 if (regno_pseudo_regs
[j
] < 0)
1940 if (rl
->in
&& REG_P (rl
->in
) && REGNO (rl
->in
) == regno
)
1942 if (rl
->out
&& REG_P (rl
->out
) && REGNO (rl
->out
) == regno
)
1944 if (this_cost
< best_cost
1945 /* Among registers with equal cost, prefer caller-saved ones, or
1946 use REG_ALLOC_ORDER if it is defined. */
1947 || (this_cost
== best_cost
1948 #ifdef REG_ALLOC_ORDER
1949 && (inv_reg_alloc_order
[regno
]
1950 < inv_reg_alloc_order
[best_reg
])
1952 && call_used_regs
[regno
]
1953 && ! call_used_regs
[best_reg
]
1958 best_cost
= this_cost
;
1966 fprintf (dump_file
, "Using reg %d for reload %d\n", best_reg
, rnum
);
1968 rl
->nregs
= hard_regno_nregs
[best_reg
][rl
->mode
];
1969 rl
->regno
= best_reg
;
1971 EXECUTE_IF_SET_IN_REG_SET
1972 (&chain
->live_throughout
, FIRST_PSEUDO_REGISTER
, j
, rsi
)
1974 count_spilled_pseudo (best_reg
, rl
->nregs
, j
);
1977 EXECUTE_IF_SET_IN_REG_SET
1978 (&chain
->dead_or_set
, FIRST_PSEUDO_REGISTER
, j
, rsi
)
1980 count_spilled_pseudo (best_reg
, rl
->nregs
, j
);
1983 for (i
= 0; i
< rl
->nregs
; i
++)
1985 gcc_assert (spill_cost
[best_reg
+ i
] == 0);
1986 gcc_assert (spill_add_cost
[best_reg
+ i
] == 0);
1987 gcc_assert (hard_regno_to_pseudo_regno
[best_reg
+ i
] == -1);
1988 SET_HARD_REG_BIT (used_spill_regs_local
, best_reg
+ i
);
1993 /* Find more reload regs to satisfy the remaining need of an insn, which
1995 Do it by ascending class number, since otherwise a reg
1996 might be spilled for a big class and might fail to count
1997 for a smaller class even though it belongs to that class. */
2000 find_reload_regs (struct insn_chain
*chain
)
2004 /* In order to be certain of getting the registers we need,
2005 we must sort the reloads into order of increasing register class.
2006 Then our grabbing of reload registers will parallel the process
2007 that provided the reload registers. */
2008 for (i
= 0; i
< chain
->n_reloads
; i
++)
2010 /* Show whether this reload already has a hard reg. */
2011 if (chain
->rld
[i
].reg_rtx
)
2013 int regno
= REGNO (chain
->rld
[i
].reg_rtx
);
2014 chain
->rld
[i
].regno
= regno
;
2016 = hard_regno_nregs
[regno
][GET_MODE (chain
->rld
[i
].reg_rtx
)];
2019 chain
->rld
[i
].regno
= -1;
2020 reload_order
[i
] = i
;
2023 n_reloads
= chain
->n_reloads
;
2024 memcpy (rld
, chain
->rld
, n_reloads
* sizeof (struct reload
));
2026 CLEAR_HARD_REG_SET (used_spill_regs_local
);
2029 fprintf (dump_file
, "Spilling for insn %d.\n", INSN_UID (chain
->insn
));
2031 qsort (reload_order
, n_reloads
, sizeof (short), reload_reg_class_lower
);
2033 /* Compute the order of preference for hard registers to spill. */
2035 order_regs_for_reload (chain
);
2037 for (i
= 0; i
< n_reloads
; i
++)
2039 int r
= reload_order
[i
];
2041 /* Ignore reloads that got marked inoperative. */
2042 if ((rld
[r
].out
!= 0 || rld
[r
].in
!= 0 || rld
[r
].secondary_p
)
2043 && ! rld
[r
].optional
2044 && rld
[r
].regno
== -1)
2045 if (! find_reg (chain
, i
))
2048 fprintf (dump_file
, "reload failure for reload %d\n", r
);
2049 spill_failure (chain
->insn
, rld
[r
].rclass
);
2055 COPY_HARD_REG_SET (chain
->used_spill_regs
, used_spill_regs_local
);
2056 IOR_HARD_REG_SET (used_spill_regs
, used_spill_regs_local
);
2058 memcpy (chain
->rld
, rld
, n_reloads
* sizeof (struct reload
));
2062 select_reload_regs (void)
2064 struct insn_chain
*chain
;
2066 /* Try to satisfy the needs for each insn. */
2067 for (chain
= insns_need_reload
; chain
!= 0;
2068 chain
= chain
->next_need_reload
)
2069 find_reload_regs (chain
);
2072 /* Delete all insns that were inserted by emit_caller_save_insns during
2075 delete_caller_save_insns (void)
2077 struct insn_chain
*c
= reload_insn_chain
;
2081 while (c
!= 0 && c
->is_caller_save_insn
)
2083 struct insn_chain
*next
= c
->next
;
2086 if (c
== reload_insn_chain
)
2087 reload_insn_chain
= next
;
2091 next
->prev
= c
->prev
;
2093 c
->prev
->next
= next
;
2094 c
->next
= unused_insn_chains
;
2095 unused_insn_chains
= c
;
2103 /* Handle the failure to find a register to spill.
2104 INSN should be one of the insns which needed this particular spill reg. */
2107 spill_failure (rtx insn
, enum reg_class rclass
)
2109 if (asm_noperands (PATTERN (insn
)) >= 0)
2110 error_for_asm (insn
, "can%'t find a register in class %qs while "
2111 "reloading %<asm%>",
2112 reg_class_names
[rclass
]);
2115 error ("unable to find a register to spill in class %qs",
2116 reg_class_names
[rclass
]);
2120 fprintf (dump_file
, "\nReloads for insn # %d\n", INSN_UID (insn
));
2121 debug_reload_to_stream (dump_file
);
2123 fatal_insn ("this is the insn:", insn
);
2127 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
2128 data that is dead in INSN. */
2131 delete_dead_insn (rtx insn
)
2133 rtx prev
= prev_active_insn (insn
);
2136 /* If the previous insn sets a register that dies in our insn make
2137 a note that we want to run DCE immediately after reload.
2139 We used to delete the previous insn & recurse, but that's wrong for
2140 block local equivalences. Instead of trying to figure out the exact
2141 circumstances where we can delete the potentially dead insns, just
2142 let DCE do the job. */
2143 if (prev
&& GET_CODE (PATTERN (prev
)) == SET
2144 && (prev_dest
= SET_DEST (PATTERN (prev
)), REG_P (prev_dest
))
2145 && reg_mentioned_p (prev_dest
, PATTERN (insn
))
2146 && find_regno_note (insn
, REG_DEAD
, REGNO (prev_dest
))
2147 && ! side_effects_p (SET_SRC (PATTERN (prev
))))
2150 SET_INSN_DELETED (insn
);
2153 /* Modify the home of pseudo-reg I.
2154 The new home is present in reg_renumber[I].
2156 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
2157 or it may be -1, meaning there is none or it is not relevant.
2158 This is used so that all pseudos spilled from a given hard reg
2159 can share one stack slot. */
2162 alter_reg (int i
, int from_reg
, bool dont_share_p
)
2164 /* When outputting an inline function, this can happen
2165 for a reg that isn't actually used. */
2166 if (regno_reg_rtx
[i
] == 0)
2169 /* If the reg got changed to a MEM at rtl-generation time,
2171 if (!REG_P (regno_reg_rtx
[i
]))
2174 /* Modify the reg-rtx to contain the new hard reg
2175 number or else to contain its pseudo reg number. */
2176 SET_REGNO (regno_reg_rtx
[i
],
2177 reg_renumber
[i
] >= 0 ? reg_renumber
[i
] : i
);
2179 /* If we have a pseudo that is needed but has no hard reg or equivalent,
2180 allocate a stack slot for it. */
2182 if (reg_renumber
[i
] < 0
2183 && REG_N_REFS (i
) > 0
2184 && reg_equiv_constant (i
) == 0
2185 && (reg_equiv_invariant (i
) == 0
2186 || reg_equiv_init (i
) == 0)
2187 && reg_equiv_memory_loc (i
) == 0)
2190 enum machine_mode mode
= GET_MODE (regno_reg_rtx
[i
]);
2191 unsigned int inherent_size
= PSEUDO_REGNO_BYTES (i
);
2192 unsigned int inherent_align
= GET_MODE_ALIGNMENT (mode
);
2193 unsigned int total_size
= MAX (inherent_size
, reg_max_ref_width
[i
]);
2194 unsigned int min_align
= reg_max_ref_width
[i
] * BITS_PER_UNIT
;
2197 something_was_spilled
= true;
2199 if (ira_conflicts_p
)
2201 /* Mark the spill for IRA. */
2202 SET_REGNO_REG_SET (&spilled_pseudos
, i
);
2204 x
= ira_reuse_stack_slot (i
, inherent_size
, total_size
);
2210 /* Each pseudo reg has an inherent size which comes from its own mode,
2211 and a total size which provides room for paradoxical subregs
2212 which refer to the pseudo reg in wider modes.
2214 We can use a slot already allocated if it provides both
2215 enough inherent space and enough total space.
2216 Otherwise, we allocate a new slot, making sure that it has no less
2217 inherent space, and no less total space, then the previous slot. */
2218 else if (from_reg
== -1 || (!dont_share_p
&& ira_conflicts_p
))
2222 /* No known place to spill from => no slot to reuse. */
2223 x
= assign_stack_local (mode
, total_size
,
2224 min_align
> inherent_align
2225 || total_size
> inherent_size
? -1 : 0);
2229 /* Cancel the big-endian correction done in assign_stack_local.
2230 Get the address of the beginning of the slot. This is so we
2231 can do a big-endian correction unconditionally below. */
2232 if (BYTES_BIG_ENDIAN
)
2234 adjust
= inherent_size
- total_size
;
2237 = adjust_address_nv (x
, mode_for_size (total_size
2243 if (! dont_share_p
&& ira_conflicts_p
)
2244 /* Inform IRA about allocation a new stack slot. */
2245 ira_mark_new_stack_slot (stack_slot
, i
, total_size
);
2248 /* Reuse a stack slot if possible. */
2249 else if (spill_stack_slot
[from_reg
] != 0
2250 && spill_stack_slot_width
[from_reg
] >= total_size
2251 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot
[from_reg
]))
2253 && MEM_ALIGN (spill_stack_slot
[from_reg
]) >= min_align
)
2254 x
= spill_stack_slot
[from_reg
];
2256 /* Allocate a bigger slot. */
2259 /* Compute maximum size needed, both for inherent size
2260 and for total size. */
2263 if (spill_stack_slot
[from_reg
])
2265 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot
[from_reg
]))
2267 mode
= GET_MODE (spill_stack_slot
[from_reg
]);
2268 if (spill_stack_slot_width
[from_reg
] > total_size
)
2269 total_size
= spill_stack_slot_width
[from_reg
];
2270 if (MEM_ALIGN (spill_stack_slot
[from_reg
]) > min_align
)
2271 min_align
= MEM_ALIGN (spill_stack_slot
[from_reg
]);
2274 /* Make a slot with that size. */
2275 x
= assign_stack_local (mode
, total_size
,
2276 min_align
> inherent_align
2277 || total_size
> inherent_size
? -1 : 0);
2280 /* Cancel the big-endian correction done in assign_stack_local.
2281 Get the address of the beginning of the slot. This is so we
2282 can do a big-endian correction unconditionally below. */
2283 if (BYTES_BIG_ENDIAN
)
2285 adjust
= GET_MODE_SIZE (mode
) - total_size
;
2288 = adjust_address_nv (x
, mode_for_size (total_size
2294 spill_stack_slot
[from_reg
] = stack_slot
;
2295 spill_stack_slot_width
[from_reg
] = total_size
;
2298 /* On a big endian machine, the "address" of the slot
2299 is the address of the low part that fits its inherent mode. */
2300 if (BYTES_BIG_ENDIAN
&& inherent_size
< total_size
)
2301 adjust
+= (total_size
- inherent_size
);
2303 /* If we have any adjustment to make, or if the stack slot is the
2304 wrong mode, make a new stack slot. */
2305 x
= adjust_address_nv (x
, GET_MODE (regno_reg_rtx
[i
]), adjust
);
2307 /* Set all of the memory attributes as appropriate for a spill. */
2308 set_mem_attrs_for_spill (x
);
2310 /* Save the stack slot for later. */
2311 reg_equiv_memory_loc (i
) = x
;
2315 /* Mark the slots in regs_ever_live for the hard regs used by
2316 pseudo-reg number REGNO, accessed in MODE. */
2319 mark_home_live_1 (int regno
, enum machine_mode mode
)
2323 i
= reg_renumber
[regno
];
2326 lim
= end_hard_regno (mode
, i
);
2328 df_set_regs_ever_live(i
++, true);
2331 /* Mark the slots in regs_ever_live for the hard regs
2332 used by pseudo-reg number REGNO. */
2335 mark_home_live (int regno
)
2337 if (reg_renumber
[regno
] >= 0)
2338 mark_home_live_1 (regno
, PSEUDO_REGNO_MODE (regno
));
2341 /* This function handles the tracking of elimination offsets around branches.
2343 X is a piece of RTL being scanned.
2345 INSN is the insn that it came from, if any.
2347 INITIAL_P is nonzero if we are to set the offset to be the initial
2348 offset and zero if we are setting the offset of the label to be the
2352 set_label_offsets (rtx x
, rtx insn
, int initial_p
)
2354 enum rtx_code code
= GET_CODE (x
);
2357 struct elim_table
*p
;
2362 if (LABEL_REF_NONLOCAL_P (x
))
2367 /* ... fall through ... */
2370 /* If we know nothing about this label, set the desired offsets. Note
2371 that this sets the offset at a label to be the offset before a label
2372 if we don't know anything about the label. This is not correct for
2373 the label after a BARRIER, but is the best guess we can make. If
2374 we guessed wrong, we will suppress an elimination that might have
2375 been possible had we been able to guess correctly. */
2377 if (! offsets_known_at
[CODE_LABEL_NUMBER (x
) - first_label_num
])
2379 for (i
= 0; i
< NUM_ELIMINABLE_REGS
; i
++)
2380 offsets_at
[CODE_LABEL_NUMBER (x
) - first_label_num
][i
]
2381 = (initial_p
? reg_eliminate
[i
].initial_offset
2382 : reg_eliminate
[i
].offset
);
2383 offsets_known_at
[CODE_LABEL_NUMBER (x
) - first_label_num
] = 1;
2386 /* Otherwise, if this is the definition of a label and it is
2387 preceded by a BARRIER, set our offsets to the known offset of
2391 && (tem
= prev_nonnote_insn (insn
)) != 0
2393 set_offsets_for_label (insn
);
2395 /* If neither of the above cases is true, compare each offset
2396 with those previously recorded and suppress any eliminations
2397 where the offsets disagree. */
2399 for (i
= 0; i
< NUM_ELIMINABLE_REGS
; i
++)
2400 if (offsets_at
[CODE_LABEL_NUMBER (x
) - first_label_num
][i
]
2401 != (initial_p
? reg_eliminate
[i
].initial_offset
2402 : reg_eliminate
[i
].offset
))
2403 reg_eliminate
[i
].can_eliminate
= 0;
2408 set_label_offsets (PATTERN (insn
), insn
, initial_p
);
2410 /* ... fall through ... */
2414 /* Any labels mentioned in REG_LABEL_OPERAND notes can be branched
2415 to indirectly and hence must have all eliminations at their
2417 for (tem
= REG_NOTES (x
); tem
; tem
= XEXP (tem
, 1))
2418 if (REG_NOTE_KIND (tem
) == REG_LABEL_OPERAND
)
2419 set_label_offsets (XEXP (tem
, 0), insn
, 1);
2425 /* Each of the labels in the parallel or address vector must be
2426 at their initial offsets. We want the first field for PARALLEL
2427 and ADDR_VEC and the second field for ADDR_DIFF_VEC. */
2429 for (i
= 0; i
< (unsigned) XVECLEN (x
, code
== ADDR_DIFF_VEC
); i
++)
2430 set_label_offsets (XVECEXP (x
, code
== ADDR_DIFF_VEC
, i
),
2435 /* We only care about setting PC. If the source is not RETURN,
2436 IF_THEN_ELSE, or a label, disable any eliminations not at
2437 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2438 isn't one of those possibilities. For branches to a label,
2439 call ourselves recursively.
2441 Note that this can disable elimination unnecessarily when we have
2442 a non-local goto since it will look like a non-constant jump to
2443 someplace in the current function. This isn't a significant
2444 problem since such jumps will normally be when all elimination
2445 pairs are back to their initial offsets. */
2447 if (SET_DEST (x
) != pc_rtx
)
2450 switch (GET_CODE (SET_SRC (x
)))
2457 set_label_offsets (SET_SRC (x
), insn
, initial_p
);
2461 tem
= XEXP (SET_SRC (x
), 1);
2462 if (GET_CODE (tem
) == LABEL_REF
)
2463 set_label_offsets (XEXP (tem
, 0), insn
, initial_p
);
2464 else if (GET_CODE (tem
) != PC
&& GET_CODE (tem
) != RETURN
)
2467 tem
= XEXP (SET_SRC (x
), 2);
2468 if (GET_CODE (tem
) == LABEL_REF
)
2469 set_label_offsets (XEXP (tem
, 0), insn
, initial_p
);
2470 else if (GET_CODE (tem
) != PC
&& GET_CODE (tem
) != RETURN
)
2478 /* If we reach here, all eliminations must be at their initial
2479 offset because we are doing a jump to a variable address. */
2480 for (p
= reg_eliminate
; p
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; p
++)
2481 if (p
->offset
!= p
->initial_offset
)
2482 p
->can_eliminate
= 0;
2490 /* Called through for_each_rtx, this function examines every reg that occurs
2491 in PX and adjusts the costs for its elimination which are gathered by IRA.
2492 DATA is the insn in which PX occurs. We do not recurse into MEM
2496 note_reg_elim_costly (rtx
*px
, void *data
)
2498 rtx insn
= (rtx
)data
;
2505 && REGNO (x
) >= FIRST_PSEUDO_REGISTER
2506 && reg_equiv_init (REGNO (x
))
2507 && reg_equiv_invariant (REGNO (x
)))
2509 rtx t
= reg_equiv_invariant (REGNO (x
));
2510 rtx new_rtx
= eliminate_regs_1 (t
, Pmode
, insn
, true, true);
2511 int cost
= set_src_cost (new_rtx
, optimize_bb_for_speed_p (elim_bb
));
2512 int freq
= REG_FREQ_FROM_BB (elim_bb
);
2515 ira_adjust_equiv_reg_cost (REGNO (x
), -cost
* freq
);
2520 /* Scan X and replace any eliminable registers (such as fp) with a
2521 replacement (such as sp), plus an offset.
2523 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2524 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2525 MEM, we are allowed to replace a sum of a register and the constant zero
2526 with the register, which we cannot do outside a MEM. In addition, we need
2527 to record the fact that a register is referenced outside a MEM.
2529 If INSN is an insn, it is the insn containing X. If we replace a REG
2530 in a SET_DEST with an equivalent MEM and INSN is nonzero, write a
2531 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2532 the REG is being modified.
2534 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2535 That's used when we eliminate in expressions stored in notes.
2536 This means, do not set ref_outside_mem even if the reference
2539 If FOR_COSTS is true, we are being called before reload in order to
2540 estimate the costs of keeping registers with an equivalence unallocated.
2542 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2543 replacements done assuming all offsets are at their initial values. If
2544 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2545 encounter, return the actual location so that find_reloads will do
2546 the proper thing. */
2549 eliminate_regs_1 (rtx x
, enum machine_mode mem_mode
, rtx insn
,
2550 bool may_use_invariant
, bool for_costs
)
2552 enum rtx_code code
= GET_CODE (x
);
2553 struct elim_table
*ep
;
2560 if (! current_function_decl
)
2580 /* First handle the case where we encounter a bare register that
2581 is eliminable. Replace it with a PLUS. */
2582 if (regno
< FIRST_PSEUDO_REGISTER
)
2584 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
2586 if (ep
->from_rtx
== x
&& ep
->can_eliminate
)
2587 return plus_constant (Pmode
, ep
->to_rtx
, ep
->previous_offset
);
2590 else if (reg_renumber
&& reg_renumber
[regno
] < 0
2592 && reg_equiv_invariant (regno
))
2594 if (may_use_invariant
|| (insn
&& DEBUG_INSN_P (insn
)))
2595 return eliminate_regs_1 (copy_rtx (reg_equiv_invariant (regno
)),
2596 mem_mode
, insn
, true, for_costs
);
2597 /* There exists at least one use of REGNO that cannot be
2598 eliminated. Prevent the defining insn from being deleted. */
2599 reg_equiv_init (regno
) = NULL_RTX
;
2601 alter_reg (regno
, -1, true);
2605 /* You might think handling MINUS in a manner similar to PLUS is a
2606 good idea. It is not. It has been tried multiple times and every
2607 time the change has had to have been reverted.
2609 Other parts of reload know a PLUS is special (gen_reload for example)
2610 and require special code to handle code a reloaded PLUS operand.
2612 Also consider backends where the flags register is clobbered by a
2613 MINUS, but we can emit a PLUS that does not clobber flags (IA-32,
2614 lea instruction comes to mind). If we try to reload a MINUS, we
2615 may kill the flags register that was holding a useful value.
2617 So, please before trying to handle MINUS, consider reload as a
2618 whole instead of this little section as well as the backend issues. */
2620 /* If this is the sum of an eliminable register and a constant, rework
2622 if (REG_P (XEXP (x
, 0))
2623 && REGNO (XEXP (x
, 0)) < FIRST_PSEUDO_REGISTER
2624 && CONSTANT_P (XEXP (x
, 1)))
2626 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
2628 if (ep
->from_rtx
== XEXP (x
, 0) && ep
->can_eliminate
)
2630 /* The only time we want to replace a PLUS with a REG (this
2631 occurs when the constant operand of the PLUS is the negative
2632 of the offset) is when we are inside a MEM. We won't want
2633 to do so at other times because that would change the
2634 structure of the insn in a way that reload can't handle.
2635 We special-case the commonest situation in
2636 eliminate_regs_in_insn, so just replace a PLUS with a
2637 PLUS here, unless inside a MEM. */
2638 if (mem_mode
!= 0 && CONST_INT_P (XEXP (x
, 1))
2639 && INTVAL (XEXP (x
, 1)) == - ep
->previous_offset
)
2642 return gen_rtx_PLUS (Pmode
, ep
->to_rtx
,
2643 plus_constant (Pmode
, XEXP (x
, 1),
2644 ep
->previous_offset
));
2647 /* If the register is not eliminable, we are done since the other
2648 operand is a constant. */
2652 /* If this is part of an address, we want to bring any constant to the
2653 outermost PLUS. We will do this by doing register replacement in
2654 our operands and seeing if a constant shows up in one of them.
2656 Note that there is no risk of modifying the structure of the insn,
2657 since we only get called for its operands, thus we are either
2658 modifying the address inside a MEM, or something like an address
2659 operand of a load-address insn. */
2662 rtx new0
= eliminate_regs_1 (XEXP (x
, 0), mem_mode
, insn
, true,
2664 rtx new1
= eliminate_regs_1 (XEXP (x
, 1), mem_mode
, insn
, true,
2667 if (reg_renumber
&& (new0
!= XEXP (x
, 0) || new1
!= XEXP (x
, 1)))
2669 /* If one side is a PLUS and the other side is a pseudo that
2670 didn't get a hard register but has a reg_equiv_constant,
2671 we must replace the constant here since it may no longer
2672 be in the position of any operand. */
2673 if (GET_CODE (new0
) == PLUS
&& REG_P (new1
)
2674 && REGNO (new1
) >= FIRST_PSEUDO_REGISTER
2675 && reg_renumber
[REGNO (new1
)] < 0
2677 && reg_equiv_constant (REGNO (new1
)) != 0)
2678 new1
= reg_equiv_constant (REGNO (new1
));
2679 else if (GET_CODE (new1
) == PLUS
&& REG_P (new0
)
2680 && REGNO (new0
) >= FIRST_PSEUDO_REGISTER
2681 && reg_renumber
[REGNO (new0
)] < 0
2682 && reg_equiv_constant (REGNO (new0
)) != 0)
2683 new0
= reg_equiv_constant (REGNO (new0
));
2685 new_rtx
= form_sum (GET_MODE (x
), new0
, new1
);
2687 /* As above, if we are not inside a MEM we do not want to
2688 turn a PLUS into something else. We might try to do so here
2689 for an addition of 0 if we aren't optimizing. */
2690 if (! mem_mode
&& GET_CODE (new_rtx
) != PLUS
)
2691 return gen_rtx_PLUS (GET_MODE (x
), new_rtx
, const0_rtx
);
2699 /* If this is the product of an eliminable register and a
2700 constant, apply the distribute law and move the constant out
2701 so that we have (plus (mult ..) ..). This is needed in order
2702 to keep load-address insns valid. This case is pathological.
2703 We ignore the possibility of overflow here. */
2704 if (REG_P (XEXP (x
, 0))
2705 && REGNO (XEXP (x
, 0)) < FIRST_PSEUDO_REGISTER
2706 && CONST_INT_P (XEXP (x
, 1)))
2707 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
2709 if (ep
->from_rtx
== XEXP (x
, 0) && ep
->can_eliminate
)
2712 /* Refs inside notes or in DEBUG_INSNs don't count for
2714 && ! (insn
!= 0 && (GET_CODE (insn
) == EXPR_LIST
2715 || GET_CODE (insn
) == INSN_LIST
2716 || DEBUG_INSN_P (insn
))))
2717 ep
->ref_outside_mem
= 1;
2720 plus_constant (Pmode
,
2721 gen_rtx_MULT (Pmode
, ep
->to_rtx
, XEXP (x
, 1)),
2722 ep
->previous_offset
* INTVAL (XEXP (x
, 1)));
2725 /* ... fall through ... */
2729 /* See comments before PLUS about handling MINUS. */
2731 case DIV
: case UDIV
:
2732 case MOD
: case UMOD
:
2733 case AND
: case IOR
: case XOR
:
2734 case ROTATERT
: case ROTATE
:
2735 case ASHIFTRT
: case LSHIFTRT
: case ASHIFT
:
2737 case GE
: case GT
: case GEU
: case GTU
:
2738 case LE
: case LT
: case LEU
: case LTU
:
2740 rtx new0
= eliminate_regs_1 (XEXP (x
, 0), mem_mode
, insn
, false,
2742 rtx new1
= XEXP (x
, 1)
2743 ? eliminate_regs_1 (XEXP (x
, 1), mem_mode
, insn
, false,
2746 if (new0
!= XEXP (x
, 0) || new1
!= XEXP (x
, 1))
2747 return gen_rtx_fmt_ee (code
, GET_MODE (x
), new0
, new1
);
2752 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2755 new_rtx
= eliminate_regs_1 (XEXP (x
, 0), mem_mode
, insn
, true,
2757 if (new_rtx
!= XEXP (x
, 0))
2759 /* If this is a REG_DEAD note, it is not valid anymore.
2760 Using the eliminated version could result in creating a
2761 REG_DEAD note for the stack or frame pointer. */
2762 if (REG_NOTE_KIND (x
) == REG_DEAD
)
2764 ? eliminate_regs_1 (XEXP (x
, 1), mem_mode
, insn
, true,
2768 x
= alloc_reg_note (REG_NOTE_KIND (x
), new_rtx
, XEXP (x
, 1));
2772 /* ... fall through ... */
2775 /* Now do eliminations in the rest of the chain. If this was
2776 an EXPR_LIST, this might result in allocating more memory than is
2777 strictly needed, but it simplifies the code. */
2780 new_rtx
= eliminate_regs_1 (XEXP (x
, 1), mem_mode
, insn
, true,
2782 if (new_rtx
!= XEXP (x
, 1))
2784 gen_rtx_fmt_ee (GET_CODE (x
), GET_MODE (x
), XEXP (x
, 0), new_rtx
);
2792 /* We do not support elimination of a register that is modified.
2793 elimination_effects has already make sure that this does not
2799 /* We do not support elimination of a register that is modified.
2800 elimination_effects has already make sure that this does not
2801 happen. The only remaining case we need to consider here is
2802 that the increment value may be an eliminable register. */
2803 if (GET_CODE (XEXP (x
, 1)) == PLUS
2804 && XEXP (XEXP (x
, 1), 0) == XEXP (x
, 0))
2806 rtx new_rtx
= eliminate_regs_1 (XEXP (XEXP (x
, 1), 1), mem_mode
,
2807 insn
, true, for_costs
);
2809 if (new_rtx
!= XEXP (XEXP (x
, 1), 1))
2810 return gen_rtx_fmt_ee (code
, GET_MODE (x
), XEXP (x
, 0),
2811 gen_rtx_PLUS (GET_MODE (x
),
2812 XEXP (x
, 0), new_rtx
));
2816 case STRICT_LOW_PART
:
2818 case SIGN_EXTEND
: case ZERO_EXTEND
:
2819 case TRUNCATE
: case FLOAT_EXTEND
: case FLOAT_TRUNCATE
:
2820 case FLOAT
: case FIX
:
2821 case UNSIGNED_FIX
: case UNSIGNED_FLOAT
:
2830 new_rtx
= eliminate_regs_1 (XEXP (x
, 0), mem_mode
, insn
, false,
2832 if (new_rtx
!= XEXP (x
, 0))
2833 return gen_rtx_fmt_e (code
, GET_MODE (x
), new_rtx
);
2837 /* Similar to above processing, but preserve SUBREG_BYTE.
2838 Convert (subreg (mem)) to (mem) if not paradoxical.
2839 Also, if we have a non-paradoxical (subreg (pseudo)) and the
2840 pseudo didn't get a hard reg, we must replace this with the
2841 eliminated version of the memory location because push_reload
2842 may do the replacement in certain circumstances. */
2843 if (REG_P (SUBREG_REG (x
))
2844 && !paradoxical_subreg_p (x
)
2846 && reg_equiv_memory_loc (REGNO (SUBREG_REG (x
))) != 0)
2848 new_rtx
= SUBREG_REG (x
);
2851 new_rtx
= eliminate_regs_1 (SUBREG_REG (x
), mem_mode
, insn
, false, for_costs
);
2853 if (new_rtx
!= SUBREG_REG (x
))
2855 int x_size
= GET_MODE_SIZE (GET_MODE (x
));
2856 int new_size
= GET_MODE_SIZE (GET_MODE (new_rtx
));
2859 && ((x_size
< new_size
2860 #ifdef WORD_REGISTER_OPERATIONS
2861 /* On these machines, combine can create rtl of the form
2862 (set (subreg:m1 (reg:m2 R) 0) ...)
2863 where m1 < m2, and expects something interesting to
2864 happen to the entire word. Moreover, it will use the
2865 (reg:m2 R) later, expecting all bits to be preserved.
2866 So if the number of words is the same, preserve the
2867 subreg so that push_reload can see it. */
2868 && ! ((x_size
- 1) / UNITS_PER_WORD
2869 == (new_size
-1 ) / UNITS_PER_WORD
)
2872 || x_size
== new_size
)
2874 return adjust_address_nv (new_rtx
, GET_MODE (x
), SUBREG_BYTE (x
));
2876 return gen_rtx_SUBREG (GET_MODE (x
), new_rtx
, SUBREG_BYTE (x
));
2882 /* Our only special processing is to pass the mode of the MEM to our
2883 recursive call and copy the flags. While we are here, handle this
2884 case more efficiently. */
2886 new_rtx
= eliminate_regs_1 (XEXP (x
, 0), GET_MODE (x
), insn
, true,
2889 && memory_address_p (GET_MODE (x
), XEXP (x
, 0))
2890 && !memory_address_p (GET_MODE (x
), new_rtx
))
2891 for_each_rtx (&XEXP (x
, 0), note_reg_elim_costly
, insn
);
2893 return replace_equiv_address_nv (x
, new_rtx
);
2896 /* Handle insn_list USE that a call to a pure function may generate. */
2897 new_rtx
= eliminate_regs_1 (XEXP (x
, 0), VOIDmode
, insn
, false,
2899 if (new_rtx
!= XEXP (x
, 0))
2900 return gen_rtx_USE (GET_MODE (x
), new_rtx
);
2905 gcc_assert (insn
&& DEBUG_INSN_P (insn
));
2915 /* Process each of our operands recursively. If any have changed, make a
2917 fmt
= GET_RTX_FORMAT (code
);
2918 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++, fmt
++)
2922 new_rtx
= eliminate_regs_1 (XEXP (x
, i
), mem_mode
, insn
, false,
2924 if (new_rtx
!= XEXP (x
, i
) && ! copied
)
2926 x
= shallow_copy_rtx (x
);
2929 XEXP (x
, i
) = new_rtx
;
2931 else if (*fmt
== 'E')
2934 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
2936 new_rtx
= eliminate_regs_1 (XVECEXP (x
, i
, j
), mem_mode
, insn
, false,
2938 if (new_rtx
!= XVECEXP (x
, i
, j
) && ! copied_vec
)
2940 rtvec new_v
= gen_rtvec_v (XVECLEN (x
, i
),
2944 x
= shallow_copy_rtx (x
);
2947 XVEC (x
, i
) = new_v
;
2950 XVECEXP (x
, i
, j
) = new_rtx
;
2959 eliminate_regs (rtx x
, enum machine_mode mem_mode
, rtx insn
)
2961 return eliminate_regs_1 (x
, mem_mode
, insn
, false, false);
2964 /* Scan rtx X for modifications of elimination target registers. Update
2965 the table of eliminables to reflect the changed state. MEM_MODE is
2966 the mode of an enclosing MEM rtx, or VOIDmode if not within a MEM. */
2969 elimination_effects (rtx x
, enum machine_mode mem_mode
)
2971 enum rtx_code code
= GET_CODE (x
);
2972 struct elim_table
*ep
;
2994 /* First handle the case where we encounter a bare register that
2995 is eliminable. Replace it with a PLUS. */
2996 if (regno
< FIRST_PSEUDO_REGISTER
)
2998 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
3000 if (ep
->from_rtx
== x
&& ep
->can_eliminate
)
3003 ep
->ref_outside_mem
= 1;
3008 else if (reg_renumber
[regno
] < 0
3010 && reg_equiv_constant (regno
)
3011 && ! function_invariant_p (reg_equiv_constant (regno
)))
3012 elimination_effects (reg_equiv_constant (regno
), mem_mode
);
3021 /* If we modify the source of an elimination rule, disable it. */
3022 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3023 if (ep
->from_rtx
== XEXP (x
, 0))
3024 ep
->can_eliminate
= 0;
3026 /* If we modify the target of an elimination rule by adding a constant,
3027 update its offset. If we modify the target in any other way, we'll
3028 have to disable the rule as well. */
3029 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3030 if (ep
->to_rtx
== XEXP (x
, 0))
3032 int size
= GET_MODE_SIZE (mem_mode
);
3034 /* If more bytes than MEM_MODE are pushed, account for them. */
3035 #ifdef PUSH_ROUNDING
3036 if (ep
->to_rtx
== stack_pointer_rtx
)
3037 size
= PUSH_ROUNDING (size
);
3039 if (code
== PRE_DEC
|| code
== POST_DEC
)
3041 else if (code
== PRE_INC
|| code
== POST_INC
)
3043 else if (code
== PRE_MODIFY
|| code
== POST_MODIFY
)
3045 if (GET_CODE (XEXP (x
, 1)) == PLUS
3046 && XEXP (x
, 0) == XEXP (XEXP (x
, 1), 0)
3047 && CONST_INT_P (XEXP (XEXP (x
, 1), 1)))
3048 ep
->offset
-= INTVAL (XEXP (XEXP (x
, 1), 1));
3050 ep
->can_eliminate
= 0;
3054 /* These two aren't unary operators. */
3055 if (code
== POST_MODIFY
|| code
== PRE_MODIFY
)
3058 /* Fall through to generic unary operation case. */
3059 case STRICT_LOW_PART
:
3061 case SIGN_EXTEND
: case ZERO_EXTEND
:
3062 case TRUNCATE
: case FLOAT_EXTEND
: case FLOAT_TRUNCATE
:
3063 case FLOAT
: case FIX
:
3064 case UNSIGNED_FIX
: case UNSIGNED_FLOAT
:
3073 elimination_effects (XEXP (x
, 0), mem_mode
);
3077 if (REG_P (SUBREG_REG (x
))
3078 && (GET_MODE_SIZE (GET_MODE (x
))
3079 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
3081 && reg_equiv_memory_loc (REGNO (SUBREG_REG (x
))) != 0)
3084 elimination_effects (SUBREG_REG (x
), mem_mode
);
3088 /* If using a register that is the source of an eliminate we still
3089 think can be performed, note it cannot be performed since we don't
3090 know how this register is used. */
3091 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3092 if (ep
->from_rtx
== XEXP (x
, 0))
3093 ep
->can_eliminate
= 0;
3095 elimination_effects (XEXP (x
, 0), mem_mode
);
3099 /* If clobbering a register that is the replacement register for an
3100 elimination we still think can be performed, note that it cannot
3101 be performed. Otherwise, we need not be concerned about it. */
3102 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3103 if (ep
->to_rtx
== XEXP (x
, 0))
3104 ep
->can_eliminate
= 0;
3106 elimination_effects (XEXP (x
, 0), mem_mode
);
3110 /* Check for setting a register that we know about. */
3111 if (REG_P (SET_DEST (x
)))
3113 /* See if this is setting the replacement register for an
3116 If DEST is the hard frame pointer, we do nothing because we
3117 assume that all assignments to the frame pointer are for
3118 non-local gotos and are being done at a time when they are valid
3119 and do not disturb anything else. Some machines want to
3120 eliminate a fake argument pointer (or even a fake frame pointer)
3121 with either the real frame or the stack pointer. Assignments to
3122 the hard frame pointer must not prevent this elimination. */
3124 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
3126 if (ep
->to_rtx
== SET_DEST (x
)
3127 && SET_DEST (x
) != hard_frame_pointer_rtx
)
3129 /* If it is being incremented, adjust the offset. Otherwise,
3130 this elimination can't be done. */
3131 rtx src
= SET_SRC (x
);
3133 if (GET_CODE (src
) == PLUS
3134 && XEXP (src
, 0) == SET_DEST (x
)
3135 && CONST_INT_P (XEXP (src
, 1)))
3136 ep
->offset
-= INTVAL (XEXP (src
, 1));
3138 ep
->can_eliminate
= 0;
3142 elimination_effects (SET_DEST (x
), VOIDmode
);
3143 elimination_effects (SET_SRC (x
), VOIDmode
);
3147 /* Our only special processing is to pass the mode of the MEM to our
3149 elimination_effects (XEXP (x
, 0), GET_MODE (x
));
3156 fmt
= GET_RTX_FORMAT (code
);
3157 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++, fmt
++)
3160 elimination_effects (XEXP (x
, i
), mem_mode
);
3161 else if (*fmt
== 'E')
3162 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
3163 elimination_effects (XVECEXP (x
, i
, j
), mem_mode
);
3167 /* Descend through rtx X and verify that no references to eliminable registers
3168 remain. If any do remain, mark the involved register as not
3172 check_eliminable_occurrences (rtx x
)
3181 code
= GET_CODE (x
);
3183 if (code
== REG
&& REGNO (x
) < FIRST_PSEUDO_REGISTER
)
3185 struct elim_table
*ep
;
3187 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3188 if (ep
->from_rtx
== x
)
3189 ep
->can_eliminate
= 0;
3193 fmt
= GET_RTX_FORMAT (code
);
3194 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++, fmt
++)
3197 check_eliminable_occurrences (XEXP (x
, i
));
3198 else if (*fmt
== 'E')
3201 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
3202 check_eliminable_occurrences (XVECEXP (x
, i
, j
));
3207 /* Scan INSN and eliminate all eliminable registers in it.
3209 If REPLACE is nonzero, do the replacement destructively. Also
3210 delete the insn as dead it if it is setting an eliminable register.
3212 If REPLACE is zero, do all our allocations in reload_obstack.
3214 If no eliminations were done and this insn doesn't require any elimination
3215 processing (these are not identical conditions: it might be updating sp,
3216 but not referencing fp; this needs to be seen during reload_as_needed so
3217 that the offset between fp and sp can be taken into consideration), zero
3218 is returned. Otherwise, 1 is returned. */
3221 eliminate_regs_in_insn (rtx insn
, int replace
)
3223 int icode
= recog_memoized (insn
);
3224 rtx old_body
= PATTERN (insn
);
3225 int insn_is_asm
= asm_noperands (old_body
) >= 0;
3226 rtx old_set
= single_set (insn
);
3230 rtx substed_operand
[MAX_RECOG_OPERANDS
];
3231 rtx orig_operand
[MAX_RECOG_OPERANDS
];
3232 struct elim_table
*ep
;
3233 rtx plus_src
, plus_cst_src
;
3235 if (! insn_is_asm
&& icode
< 0)
3237 gcc_assert (JUMP_TABLE_DATA_P (insn
)
3238 || GET_CODE (PATTERN (insn
)) == USE
3239 || GET_CODE (PATTERN (insn
)) == CLOBBER
3240 || GET_CODE (PATTERN (insn
)) == ASM_INPUT
3241 || DEBUG_INSN_P (insn
));
3242 if (DEBUG_INSN_P (insn
))
3243 INSN_VAR_LOCATION_LOC (insn
)
3244 = eliminate_regs (INSN_VAR_LOCATION_LOC (insn
), VOIDmode
, insn
);
3248 if (old_set
!= 0 && REG_P (SET_DEST (old_set
))
3249 && REGNO (SET_DEST (old_set
)) < FIRST_PSEUDO_REGISTER
)
3251 /* Check for setting an eliminable register. */
3252 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3253 if (ep
->from_rtx
== SET_DEST (old_set
) && ep
->can_eliminate
)
3255 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
3256 /* If this is setting the frame pointer register to the
3257 hardware frame pointer register and this is an elimination
3258 that will be done (tested above), this insn is really
3259 adjusting the frame pointer downward to compensate for
3260 the adjustment done before a nonlocal goto. */
3261 if (ep
->from
== FRAME_POINTER_REGNUM
3262 && ep
->to
== HARD_FRAME_POINTER_REGNUM
)
3264 rtx base
= SET_SRC (old_set
);
3265 rtx base_insn
= insn
;
3266 HOST_WIDE_INT offset
= 0;
3268 while (base
!= ep
->to_rtx
)
3270 rtx prev_insn
, prev_set
;
3272 if (GET_CODE (base
) == PLUS
3273 && CONST_INT_P (XEXP (base
, 1)))
3275 offset
+= INTVAL (XEXP (base
, 1));
3276 base
= XEXP (base
, 0);
3278 else if ((prev_insn
= prev_nonnote_insn (base_insn
)) != 0
3279 && (prev_set
= single_set (prev_insn
)) != 0
3280 && rtx_equal_p (SET_DEST (prev_set
), base
))
3282 base
= SET_SRC (prev_set
);
3283 base_insn
= prev_insn
;
3289 if (base
== ep
->to_rtx
)
3291 rtx src
= plus_constant (Pmode
, ep
->to_rtx
,
3292 offset
- ep
->offset
);
3294 new_body
= old_body
;
3297 new_body
= copy_insn (old_body
);
3298 if (REG_NOTES (insn
))
3299 REG_NOTES (insn
) = copy_insn_1 (REG_NOTES (insn
));
3301 PATTERN (insn
) = new_body
;
3302 old_set
= single_set (insn
);
3304 /* First see if this insn remains valid when we
3305 make the change. If not, keep the INSN_CODE
3306 the same and let reload fit it up. */
3307 validate_change (insn
, &SET_SRC (old_set
), src
, 1);
3308 validate_change (insn
, &SET_DEST (old_set
),
3310 if (! apply_change_group ())
3312 SET_SRC (old_set
) = src
;
3313 SET_DEST (old_set
) = ep
->to_rtx
;
3322 /* In this case this insn isn't serving a useful purpose. We
3323 will delete it in reload_as_needed once we know that this
3324 elimination is, in fact, being done.
3326 If REPLACE isn't set, we can't delete this insn, but needn't
3327 process it since it won't be used unless something changes. */
3330 delete_dead_insn (insn
);
3338 /* We allow one special case which happens to work on all machines we
3339 currently support: a single set with the source or a REG_EQUAL
3340 note being a PLUS of an eliminable register and a constant. */
3341 plus_src
= plus_cst_src
= 0;
3342 if (old_set
&& REG_P (SET_DEST (old_set
)))
3344 if (GET_CODE (SET_SRC (old_set
)) == PLUS
)
3345 plus_src
= SET_SRC (old_set
);
3346 /* First see if the source is of the form (plus (...) CST). */
3348 && CONST_INT_P (XEXP (plus_src
, 1)))
3349 plus_cst_src
= plus_src
;
3350 else if (REG_P (SET_SRC (old_set
))
3353 /* Otherwise, see if we have a REG_EQUAL note of the form
3354 (plus (...) CST). */
3356 for (links
= REG_NOTES (insn
); links
; links
= XEXP (links
, 1))
3358 if ((REG_NOTE_KIND (links
) == REG_EQUAL
3359 || REG_NOTE_KIND (links
) == REG_EQUIV
)
3360 && GET_CODE (XEXP (links
, 0)) == PLUS
3361 && CONST_INT_P (XEXP (XEXP (links
, 0), 1)))
3363 plus_cst_src
= XEXP (links
, 0);
3369 /* Check that the first operand of the PLUS is a hard reg or
3370 the lowpart subreg of one. */
3373 rtx reg
= XEXP (plus_cst_src
, 0);
3374 if (GET_CODE (reg
) == SUBREG
&& subreg_lowpart_p (reg
))
3375 reg
= SUBREG_REG (reg
);
3377 if (!REG_P (reg
) || REGNO (reg
) >= FIRST_PSEUDO_REGISTER
)
3383 rtx reg
= XEXP (plus_cst_src
, 0);
3384 HOST_WIDE_INT offset
= INTVAL (XEXP (plus_cst_src
, 1));
3386 if (GET_CODE (reg
) == SUBREG
)
3387 reg
= SUBREG_REG (reg
);
3389 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3390 if (ep
->from_rtx
== reg
&& ep
->can_eliminate
)
3392 rtx to_rtx
= ep
->to_rtx
;
3393 offset
+= ep
->offset
;
3394 offset
= trunc_int_for_mode (offset
, GET_MODE (plus_cst_src
));
3396 if (GET_CODE (XEXP (plus_cst_src
, 0)) == SUBREG
)
3397 to_rtx
= gen_lowpart (GET_MODE (XEXP (plus_cst_src
, 0)),
3399 /* If we have a nonzero offset, and the source is already
3400 a simple REG, the following transformation would
3401 increase the cost of the insn by replacing a simple REG
3402 with (plus (reg sp) CST). So try only when we already
3403 had a PLUS before. */
3404 if (offset
== 0 || plus_src
)
3406 rtx new_src
= plus_constant (GET_MODE (to_rtx
),
3409 new_body
= old_body
;
3412 new_body
= copy_insn (old_body
);
3413 if (REG_NOTES (insn
))
3414 REG_NOTES (insn
) = copy_insn_1 (REG_NOTES (insn
));
3416 PATTERN (insn
) = new_body
;
3417 old_set
= single_set (insn
);
3419 /* First see if this insn remains valid when we make the
3420 change. If not, try to replace the whole pattern with
3421 a simple set (this may help if the original insn was a
3422 PARALLEL that was only recognized as single_set due to
3423 REG_UNUSED notes). If this isn't valid either, keep
3424 the INSN_CODE the same and let reload fix it up. */
3425 if (!validate_change (insn
, &SET_SRC (old_set
), new_src
, 0))
3427 rtx new_pat
= gen_rtx_SET (VOIDmode
,
3428 SET_DEST (old_set
), new_src
);
3430 if (!validate_change (insn
, &PATTERN (insn
), new_pat
, 0))
3431 SET_SRC (old_set
) = new_src
;
3438 /* This can't have an effect on elimination offsets, so skip right
3444 /* Determine the effects of this insn on elimination offsets. */
3445 elimination_effects (old_body
, VOIDmode
);
3447 /* Eliminate all eliminable registers occurring in operands that
3448 can be handled by reload. */
3449 extract_insn (insn
);
3450 for (i
= 0; i
< recog_data
.n_operands
; i
++)
3452 orig_operand
[i
] = recog_data
.operand
[i
];
3453 substed_operand
[i
] = recog_data
.operand
[i
];
3455 /* For an asm statement, every operand is eliminable. */
3456 if (insn_is_asm
|| insn_data
[icode
].operand
[i
].eliminable
)
3458 bool is_set_src
, in_plus
;
3460 /* Check for setting a register that we know about. */
3461 if (recog_data
.operand_type
[i
] != OP_IN
3462 && REG_P (orig_operand
[i
]))
3464 /* If we are assigning to a register that can be eliminated, it
3465 must be as part of a PARALLEL, since the code above handles
3466 single SETs. We must indicate that we can no longer
3467 eliminate this reg. */
3468 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
3470 if (ep
->from_rtx
== orig_operand
[i
])
3471 ep
->can_eliminate
= 0;
3474 /* Companion to the above plus substitution, we can allow
3475 invariants as the source of a plain move. */
3478 && recog_data
.operand_loc
[i
] == &SET_SRC (old_set
))
3482 && (recog_data
.operand_loc
[i
] == &XEXP (plus_src
, 0)
3483 || recog_data
.operand_loc
[i
] == &XEXP (plus_src
, 1)))
3487 = eliminate_regs_1 (recog_data
.operand
[i
], VOIDmode
,
3488 replace
? insn
: NULL_RTX
,
3489 is_set_src
|| in_plus
, false);
3490 if (substed_operand
[i
] != orig_operand
[i
])
3492 /* Terminate the search in check_eliminable_occurrences at
3494 *recog_data
.operand_loc
[i
] = 0;
3496 /* If an output operand changed from a REG to a MEM and INSN is an
3497 insn, write a CLOBBER insn. */
3498 if (recog_data
.operand_type
[i
] != OP_IN
3499 && REG_P (orig_operand
[i
])
3500 && MEM_P (substed_operand
[i
])
3502 emit_insn_after (gen_clobber (orig_operand
[i
]), insn
);
3506 for (i
= 0; i
< recog_data
.n_dups
; i
++)
3507 *recog_data
.dup_loc
[i
]
3508 = *recog_data
.operand_loc
[(int) recog_data
.dup_num
[i
]];
3510 /* If any eliminable remain, they aren't eliminable anymore. */
3511 check_eliminable_occurrences (old_body
);
3513 /* Substitute the operands; the new values are in the substed_operand
3515 for (i
= 0; i
< recog_data
.n_operands
; i
++)
3516 *recog_data
.operand_loc
[i
] = substed_operand
[i
];
3517 for (i
= 0; i
< recog_data
.n_dups
; i
++)
3518 *recog_data
.dup_loc
[i
] = substed_operand
[(int) recog_data
.dup_num
[i
]];
3520 /* If we are replacing a body that was a (set X (plus Y Z)), try to
3521 re-recognize the insn. We do this in case we had a simple addition
3522 but now can do this as a load-address. This saves an insn in this
3524 If re-recognition fails, the old insn code number will still be used,
3525 and some register operands may have changed into PLUS expressions.
3526 These will be handled by find_reloads by loading them into a register
3531 /* If we aren't replacing things permanently and we changed something,
3532 make another copy to ensure that all the RTL is new. Otherwise
3533 things can go wrong if find_reload swaps commutative operands
3534 and one is inside RTL that has been copied while the other is not. */
3535 new_body
= old_body
;
3538 new_body
= copy_insn (old_body
);
3539 if (REG_NOTES (insn
))
3540 REG_NOTES (insn
) = copy_insn_1 (REG_NOTES (insn
));
3542 PATTERN (insn
) = new_body
;
3544 /* If we had a move insn but now we don't, rerecognize it. This will
3545 cause spurious re-recognition if the old move had a PARALLEL since
3546 the new one still will, but we can't call single_set without
3547 having put NEW_BODY into the insn and the re-recognition won't
3548 hurt in this rare case. */
3549 /* ??? Why this huge if statement - why don't we just rerecognize the
3553 && ((REG_P (SET_SRC (old_set
))
3554 && (GET_CODE (new_body
) != SET
3555 || !REG_P (SET_SRC (new_body
))))
3556 /* If this was a load from or store to memory, compare
3557 the MEM in recog_data.operand to the one in the insn.
3558 If they are not equal, then rerecognize the insn. */
3560 && ((MEM_P (SET_SRC (old_set
))
3561 && SET_SRC (old_set
) != recog_data
.operand
[1])
3562 || (MEM_P (SET_DEST (old_set
))
3563 && SET_DEST (old_set
) != recog_data
.operand
[0])))
3564 /* If this was an add insn before, rerecognize. */
3565 || GET_CODE (SET_SRC (old_set
)) == PLUS
))
3567 int new_icode
= recog (PATTERN (insn
), insn
, 0);
3569 INSN_CODE (insn
) = new_icode
;
3573 /* Restore the old body. If there were any changes to it, we made a copy
3574 of it while the changes were still in place, so we'll correctly return
3575 a modified insn below. */
3578 /* Restore the old body. */
3579 for (i
= 0; i
< recog_data
.n_operands
; i
++)
3580 /* Restoring a top-level match_parallel would clobber the new_body
3581 we installed in the insn. */
3582 if (recog_data
.operand_loc
[i
] != &PATTERN (insn
))
3583 *recog_data
.operand_loc
[i
] = orig_operand
[i
];
3584 for (i
= 0; i
< recog_data
.n_dups
; i
++)
3585 *recog_data
.dup_loc
[i
] = orig_operand
[(int) recog_data
.dup_num
[i
]];
3588 /* Update all elimination pairs to reflect the status after the current
3589 insn. The changes we make were determined by the earlier call to
3590 elimination_effects.
3592 We also detect cases where register elimination cannot be done,
3593 namely, if a register would be both changed and referenced outside a MEM
3594 in the resulting insn since such an insn is often undefined and, even if
3595 not, we cannot know what meaning will be given to it. Note that it is
3596 valid to have a register used in an address in an insn that changes it
3597 (presumably with a pre- or post-increment or decrement).
3599 If anything changes, return nonzero. */
3601 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3603 if (ep
->previous_offset
!= ep
->offset
&& ep
->ref_outside_mem
)
3604 ep
->can_eliminate
= 0;
3606 ep
->ref_outside_mem
= 0;
3608 if (ep
->previous_offset
!= ep
->offset
)
3613 /* If we changed something, perform elimination in REG_NOTES. This is
3614 needed even when REPLACE is zero because a REG_DEAD note might refer
3615 to a register that we eliminate and could cause a different number
3616 of spill registers to be needed in the final reload pass than in
3618 if (val
&& REG_NOTES (insn
) != 0)
3620 = eliminate_regs_1 (REG_NOTES (insn
), VOIDmode
, REG_NOTES (insn
), true,
3626 /* Like eliminate_regs_in_insn, but only estimate costs for the use of the
3627 register allocator. INSN is the instruction we need to examine, we perform
3628 eliminations in its operands and record cases where eliminating a reg with
3629 an invariant equivalence would add extra cost. */
3632 elimination_costs_in_insn (rtx insn
)
3634 int icode
= recog_memoized (insn
);
3635 rtx old_body
= PATTERN (insn
);
3636 int insn_is_asm
= asm_noperands (old_body
) >= 0;
3637 rtx old_set
= single_set (insn
);
3639 rtx orig_operand
[MAX_RECOG_OPERANDS
];
3640 rtx orig_dup
[MAX_RECOG_OPERANDS
];
3641 struct elim_table
*ep
;
3642 rtx plus_src
, plus_cst_src
;
3645 if (! insn_is_asm
&& icode
< 0)
3647 gcc_assert (JUMP_TABLE_DATA_P (insn
)
3648 || GET_CODE (PATTERN (insn
)) == USE
3649 || GET_CODE (PATTERN (insn
)) == CLOBBER
3650 || GET_CODE (PATTERN (insn
)) == ASM_INPUT
3651 || DEBUG_INSN_P (insn
));
3655 if (old_set
!= 0 && REG_P (SET_DEST (old_set
))
3656 && REGNO (SET_DEST (old_set
)) < FIRST_PSEUDO_REGISTER
)
3658 /* Check for setting an eliminable register. */
3659 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3660 if (ep
->from_rtx
== SET_DEST (old_set
) && ep
->can_eliminate
)
3664 /* We allow one special case which happens to work on all machines we
3665 currently support: a single set with the source or a REG_EQUAL
3666 note being a PLUS of an eliminable register and a constant. */
3667 plus_src
= plus_cst_src
= 0;
3669 if (old_set
&& REG_P (SET_DEST (old_set
)))
3672 if (GET_CODE (SET_SRC (old_set
)) == PLUS
)
3673 plus_src
= SET_SRC (old_set
);
3674 /* First see if the source is of the form (plus (...) CST). */
3676 && CONST_INT_P (XEXP (plus_src
, 1)))
3677 plus_cst_src
= plus_src
;
3678 else if (REG_P (SET_SRC (old_set
))
3681 /* Otherwise, see if we have a REG_EQUAL note of the form
3682 (plus (...) CST). */
3684 for (links
= REG_NOTES (insn
); links
; links
= XEXP (links
, 1))
3686 if ((REG_NOTE_KIND (links
) == REG_EQUAL
3687 || REG_NOTE_KIND (links
) == REG_EQUIV
)
3688 && GET_CODE (XEXP (links
, 0)) == PLUS
3689 && CONST_INT_P (XEXP (XEXP (links
, 0), 1)))
3691 plus_cst_src
= XEXP (links
, 0);
3698 /* Determine the effects of this insn on elimination offsets. */
3699 elimination_effects (old_body
, VOIDmode
);
3701 /* Eliminate all eliminable registers occurring in operands that
3702 can be handled by reload. */
3703 extract_insn (insn
);
3704 for (i
= 0; i
< recog_data
.n_dups
; i
++)
3705 orig_dup
[i
] = *recog_data
.dup_loc
[i
];
3707 for (i
= 0; i
< recog_data
.n_operands
; i
++)
3709 orig_operand
[i
] = recog_data
.operand
[i
];
3711 /* For an asm statement, every operand is eliminable. */
3712 if (insn_is_asm
|| insn_data
[icode
].operand
[i
].eliminable
)
3714 bool is_set_src
, in_plus
;
3716 /* Check for setting a register that we know about. */
3717 if (recog_data
.operand_type
[i
] != OP_IN
3718 && REG_P (orig_operand
[i
]))
3720 /* If we are assigning to a register that can be eliminated, it
3721 must be as part of a PARALLEL, since the code above handles
3722 single SETs. We must indicate that we can no longer
3723 eliminate this reg. */
3724 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
3726 if (ep
->from_rtx
== orig_operand
[i
])
3727 ep
->can_eliminate
= 0;
3730 /* Companion to the above plus substitution, we can allow
3731 invariants as the source of a plain move. */
3733 if (old_set
&& recog_data
.operand_loc
[i
] == &SET_SRC (old_set
))
3735 if (is_set_src
&& !sets_reg_p
)
3736 note_reg_elim_costly (&SET_SRC (old_set
), insn
);
3738 if (plus_src
&& sets_reg_p
3739 && (recog_data
.operand_loc
[i
] == &XEXP (plus_src
, 0)
3740 || recog_data
.operand_loc
[i
] == &XEXP (plus_src
, 1)))
3743 eliminate_regs_1 (recog_data
.operand
[i
], VOIDmode
,
3745 is_set_src
|| in_plus
, true);
3746 /* Terminate the search in check_eliminable_occurrences at
3748 *recog_data
.operand_loc
[i
] = 0;
3752 for (i
= 0; i
< recog_data
.n_dups
; i
++)
3753 *recog_data
.dup_loc
[i
]
3754 = *recog_data
.operand_loc
[(int) recog_data
.dup_num
[i
]];
3756 /* If any eliminable remain, they aren't eliminable anymore. */
3757 check_eliminable_occurrences (old_body
);
3759 /* Restore the old body. */
3760 for (i
= 0; i
< recog_data
.n_operands
; i
++)
3761 *recog_data
.operand_loc
[i
] = orig_operand
[i
];
3762 for (i
= 0; i
< recog_data
.n_dups
; i
++)
3763 *recog_data
.dup_loc
[i
] = orig_dup
[i
];
3765 /* Update all elimination pairs to reflect the status after the current
3766 insn. The changes we make were determined by the earlier call to
3767 elimination_effects. */
3769 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3771 if (ep
->previous_offset
!= ep
->offset
&& ep
->ref_outside_mem
)
3772 ep
->can_eliminate
= 0;
3774 ep
->ref_outside_mem
= 0;
3780 /* Loop through all elimination pairs.
3781 Recalculate the number not at initial offset.
3783 Compute the maximum offset (minimum offset if the stack does not
3784 grow downward) for each elimination pair. */
3787 update_eliminable_offsets (void)
3789 struct elim_table
*ep
;
3791 num_not_at_initial_offset
= 0;
3792 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3794 ep
->previous_offset
= ep
->offset
;
3795 if (ep
->can_eliminate
&& ep
->offset
!= ep
->initial_offset
)
3796 num_not_at_initial_offset
++;
3800 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3801 replacement we currently believe is valid, mark it as not eliminable if X
3802 modifies DEST in any way other than by adding a constant integer to it.
3804 If DEST is the frame pointer, we do nothing because we assume that
3805 all assignments to the hard frame pointer are nonlocal gotos and are being
3806 done at a time when they are valid and do not disturb anything else.
3807 Some machines want to eliminate a fake argument pointer with either the
3808 frame or stack pointer. Assignments to the hard frame pointer must not
3809 prevent this elimination.
3811 Called via note_stores from reload before starting its passes to scan
3812 the insns of the function. */
3815 mark_not_eliminable (rtx dest
, const_rtx x
, void *data ATTRIBUTE_UNUSED
)
3819 /* A SUBREG of a hard register here is just changing its mode. We should
3820 not see a SUBREG of an eliminable hard register, but check just in
3822 if (GET_CODE (dest
) == SUBREG
)
3823 dest
= SUBREG_REG (dest
);
3825 if (dest
== hard_frame_pointer_rtx
)
3828 for (i
= 0; i
< NUM_ELIMINABLE_REGS
; i
++)
3829 if (reg_eliminate
[i
].can_eliminate
&& dest
== reg_eliminate
[i
].to_rtx
3830 && (GET_CODE (x
) != SET
3831 || GET_CODE (SET_SRC (x
)) != PLUS
3832 || XEXP (SET_SRC (x
), 0) != dest
3833 || !CONST_INT_P (XEXP (SET_SRC (x
), 1))))
3835 reg_eliminate
[i
].can_eliminate_previous
3836 = reg_eliminate
[i
].can_eliminate
= 0;
3841 /* Verify that the initial elimination offsets did not change since the
3842 last call to set_initial_elim_offsets. This is used to catch cases
3843 where something illegal happened during reload_as_needed that could
3844 cause incorrect code to be generated if we did not check for it. */
3847 verify_initial_elim_offsets (void)
3851 if (!num_eliminable
)
3854 #ifdef ELIMINABLE_REGS
3856 struct elim_table
*ep
;
3858 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3860 INITIAL_ELIMINATION_OFFSET (ep
->from
, ep
->to
, t
);
3861 if (t
!= ep
->initial_offset
)
3866 INITIAL_FRAME_POINTER_OFFSET (t
);
3867 if (t
!= reg_eliminate
[0].initial_offset
)
3874 /* Reset all offsets on eliminable registers to their initial values. */
3877 set_initial_elim_offsets (void)
3879 struct elim_table
*ep
= reg_eliminate
;
3881 #ifdef ELIMINABLE_REGS
3882 for (; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3884 INITIAL_ELIMINATION_OFFSET (ep
->from
, ep
->to
, ep
->initial_offset
);
3885 ep
->previous_offset
= ep
->offset
= ep
->initial_offset
;
3888 INITIAL_FRAME_POINTER_OFFSET (ep
->initial_offset
);
3889 ep
->previous_offset
= ep
->offset
= ep
->initial_offset
;
3892 num_not_at_initial_offset
= 0;
3895 /* Subroutine of set_initial_label_offsets called via for_each_eh_label. */
3898 set_initial_eh_label_offset (rtx label
)
3900 set_label_offsets (label
, NULL_RTX
, 1);
3903 /* Initialize the known label offsets.
3904 Set a known offset for each forced label to be at the initial offset
3905 of each elimination. We do this because we assume that all
3906 computed jumps occur from a location where each elimination is
3907 at its initial offset.
3908 For all other labels, show that we don't know the offsets. */
3911 set_initial_label_offsets (void)
3914 memset (offsets_known_at
, 0, num_labels
);
3916 for (x
= forced_labels
; x
; x
= XEXP (x
, 1))
3918 set_label_offsets (XEXP (x
, 0), NULL_RTX
, 1);
3920 for (x
= nonlocal_goto_handler_labels
; x
; x
= XEXP (x
, 1))
3922 set_label_offsets (XEXP (x
, 0), NULL_RTX
, 1);
3924 for_each_eh_label (set_initial_eh_label_offset
);
3927 /* Set all elimination offsets to the known values for the code label given
3931 set_offsets_for_label (rtx insn
)
3934 int label_nr
= CODE_LABEL_NUMBER (insn
);
3935 struct elim_table
*ep
;
3937 num_not_at_initial_offset
= 0;
3938 for (i
= 0, ep
= reg_eliminate
; i
< NUM_ELIMINABLE_REGS
; ep
++, i
++)
3940 ep
->offset
= ep
->previous_offset
3941 = offsets_at
[label_nr
- first_label_num
][i
];
3942 if (ep
->can_eliminate
&& ep
->offset
!= ep
->initial_offset
)
3943 num_not_at_initial_offset
++;
3947 /* See if anything that happened changes which eliminations are valid.
3948 For example, on the SPARC, whether or not the frame pointer can
3949 be eliminated can depend on what registers have been used. We need
3950 not check some conditions again (such as flag_omit_frame_pointer)
3951 since they can't have changed. */
3954 update_eliminables (HARD_REG_SET
*pset
)
3956 int previous_frame_pointer_needed
= frame_pointer_needed
;
3957 struct elim_table
*ep
;
3959 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3960 if ((ep
->from
== HARD_FRAME_POINTER_REGNUM
3961 && targetm
.frame_pointer_required ())
3962 #ifdef ELIMINABLE_REGS
3963 || ! targetm
.can_eliminate (ep
->from
, ep
->to
)
3966 ep
->can_eliminate
= 0;
3968 /* Look for the case where we have discovered that we can't replace
3969 register A with register B and that means that we will now be
3970 trying to replace register A with register C. This means we can
3971 no longer replace register C with register B and we need to disable
3972 such an elimination, if it exists. This occurs often with A == ap,
3973 B == sp, and C == fp. */
3975 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3977 struct elim_table
*op
;
3980 if (! ep
->can_eliminate
&& ep
->can_eliminate_previous
)
3982 /* Find the current elimination for ep->from, if there is a
3984 for (op
= reg_eliminate
;
3985 op
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; op
++)
3986 if (op
->from
== ep
->from
&& op
->can_eliminate
)
3992 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
3994 for (op
= reg_eliminate
;
3995 op
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; op
++)
3996 if (op
->from
== new_to
&& op
->to
== ep
->to
)
3997 op
->can_eliminate
= 0;
4001 /* See if any registers that we thought we could eliminate the previous
4002 time are no longer eliminable. If so, something has changed and we
4003 must spill the register. Also, recompute the number of eliminable
4004 registers and see if the frame pointer is needed; it is if there is
4005 no elimination of the frame pointer that we can perform. */
4007 frame_pointer_needed
= 1;
4008 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
4010 if (ep
->can_eliminate
4011 && ep
->from
== FRAME_POINTER_REGNUM
4012 && ep
->to
!= HARD_FRAME_POINTER_REGNUM
4013 && (! SUPPORTS_STACK_ALIGNMENT
4014 || ! crtl
->stack_realign_needed
))
4015 frame_pointer_needed
= 0;
4017 if (! ep
->can_eliminate
&& ep
->can_eliminate_previous
)
4019 ep
->can_eliminate_previous
= 0;
4020 SET_HARD_REG_BIT (*pset
, ep
->from
);
4025 /* If we didn't need a frame pointer last time, but we do now, spill
4026 the hard frame pointer. */
4027 if (frame_pointer_needed
&& ! previous_frame_pointer_needed
)
4028 SET_HARD_REG_BIT (*pset
, HARD_FRAME_POINTER_REGNUM
);
4031 /* Return true if X is used as the target register of an elimination. */
4034 elimination_target_reg_p (rtx x
)
4036 struct elim_table
*ep
;
4038 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
4039 if (ep
->to_rtx
== x
&& ep
->can_eliminate
)
4045 /* Initialize the table of registers to eliminate.
4046 Pre-condition: global flag frame_pointer_needed has been set before
4047 calling this function. */
4050 init_elim_table (void)
4052 struct elim_table
*ep
;
4053 #ifdef ELIMINABLE_REGS
4054 const struct elim_table_1
*ep1
;
4058 reg_eliminate
= XCNEWVEC (struct elim_table
, NUM_ELIMINABLE_REGS
);
4062 #ifdef ELIMINABLE_REGS
4063 for (ep
= reg_eliminate
, ep1
= reg_eliminate_1
;
4064 ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++, ep1
++)
4066 ep
->from
= ep1
->from
;
4068 ep
->can_eliminate
= ep
->can_eliminate_previous
4069 = (targetm
.can_eliminate (ep
->from
, ep
->to
)
4070 && ! (ep
->to
== STACK_POINTER_REGNUM
4071 && frame_pointer_needed
4072 && (! SUPPORTS_STACK_ALIGNMENT
4073 || ! stack_realign_fp
)));
4076 reg_eliminate
[0].from
= reg_eliminate_1
[0].from
;
4077 reg_eliminate
[0].to
= reg_eliminate_1
[0].to
;
4078 reg_eliminate
[0].can_eliminate
= reg_eliminate
[0].can_eliminate_previous
4079 = ! frame_pointer_needed
;
4082 /* Count the number of eliminable registers and build the FROM and TO
4083 REG rtx's. Note that code in gen_rtx_REG will cause, e.g.,
4084 gen_rtx_REG (Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
4085 We depend on this. */
4086 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
4088 num_eliminable
+= ep
->can_eliminate
;
4089 ep
->from_rtx
= gen_rtx_REG (Pmode
, ep
->from
);
4090 ep
->to_rtx
= gen_rtx_REG (Pmode
, ep
->to
);
4094 /* Find all the pseudo registers that didn't get hard regs
4095 but do have known equivalent constants or memory slots.
4096 These include parameters (known equivalent to parameter slots)
4097 and cse'd or loop-moved constant memory addresses.
4099 Record constant equivalents in reg_equiv_constant
4100 so they will be substituted by find_reloads.
4101 Record memory equivalents in reg_mem_equiv so they can
4102 be substituted eventually by altering the REG-rtx's. */
4105 init_eliminable_invariants (rtx first
, bool do_subregs
)
4112 reg_max_ref_width
= XCNEWVEC (unsigned int, max_regno
);
4114 reg_max_ref_width
= NULL
;
4116 num_eliminable_invariants
= 0;
4118 first_label_num
= get_first_label_num ();
4119 num_labels
= max_label_num () - first_label_num
;
4121 /* Allocate the tables used to store offset information at labels. */
4122 offsets_known_at
= XNEWVEC (char, num_labels
);
4123 offsets_at
= (HOST_WIDE_INT (*)[NUM_ELIMINABLE_REGS
]) xmalloc (num_labels
* NUM_ELIMINABLE_REGS
* sizeof (HOST_WIDE_INT
));
4125 /* Look for REG_EQUIV notes; record what each pseudo is equivalent
4126 to. If DO_SUBREGS is true, also find all paradoxical subregs and
4127 find largest such for each pseudo. FIRST is the head of the insn
4130 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
4132 rtx set
= single_set (insn
);
4134 /* We may introduce USEs that we want to remove at the end, so
4135 we'll mark them with QImode. Make sure there are no
4136 previously-marked insns left by say regmove. */
4137 if (INSN_P (insn
) && GET_CODE (PATTERN (insn
)) == USE
4138 && GET_MODE (insn
) != VOIDmode
)
4139 PUT_MODE (insn
, VOIDmode
);
4141 if (do_subregs
&& NONDEBUG_INSN_P (insn
))
4142 scan_paradoxical_subregs (PATTERN (insn
));
4144 if (set
!= 0 && REG_P (SET_DEST (set
)))
4146 rtx note
= find_reg_note (insn
, REG_EQUIV
, NULL_RTX
);
4152 i
= REGNO (SET_DEST (set
));
4155 if (i
<= LAST_VIRTUAL_REGISTER
)
4158 /* If flag_pic and we have constant, verify it's legitimate. */
4160 || !flag_pic
|| LEGITIMATE_PIC_OPERAND_P (x
))
4162 /* It can happen that a REG_EQUIV note contains a MEM
4163 that is not a legitimate memory operand. As later
4164 stages of reload assume that all addresses found
4165 in the reg_equiv_* arrays were originally legitimate,
4166 we ignore such REG_EQUIV notes. */
4167 if (memory_operand (x
, VOIDmode
))
4169 /* Always unshare the equivalence, so we can
4170 substitute into this insn without touching the
4172 reg_equiv_memory_loc (i
) = copy_rtx (x
);
4174 else if (function_invariant_p (x
))
4176 enum machine_mode mode
;
4178 mode
= GET_MODE (SET_DEST (set
));
4179 if (GET_CODE (x
) == PLUS
)
4181 /* This is PLUS of frame pointer and a constant,
4182 and might be shared. Unshare it. */
4183 reg_equiv_invariant (i
) = copy_rtx (x
);
4184 num_eliminable_invariants
++;
4186 else if (x
== frame_pointer_rtx
|| x
== arg_pointer_rtx
)
4188 reg_equiv_invariant (i
) = x
;
4189 num_eliminable_invariants
++;
4191 else if (targetm
.legitimate_constant_p (mode
, x
))
4192 reg_equiv_constant (i
) = x
;
4195 reg_equiv_memory_loc (i
) = force_const_mem (mode
, x
);
4196 if (! reg_equiv_memory_loc (i
))
4197 reg_equiv_init (i
) = NULL_RTX
;
4202 reg_equiv_init (i
) = NULL_RTX
;
4207 reg_equiv_init (i
) = NULL_RTX
;
4212 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
4213 if (reg_equiv_init (i
))
4215 fprintf (dump_file
, "init_insns for %u: ", i
);
4216 print_inline_rtx (dump_file
, reg_equiv_init (i
), 20);
4217 fprintf (dump_file
, "\n");
4221 /* Indicate that we no longer have known memory locations or constants.
4222 Free all data involved in tracking these. */
4225 free_reg_equiv (void)
4229 free (offsets_known_at
);
4232 offsets_known_at
= 0;
4234 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
4235 if (reg_equiv_alt_mem_list (i
))
4236 free_EXPR_LIST_list (®_equiv_alt_mem_list (i
));
4237 vec_free (reg_equivs
);
4240 /* Kick all pseudos out of hard register REGNO.
4242 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
4243 because we found we can't eliminate some register. In the case, no pseudos
4244 are allowed to be in the register, even if they are only in a block that
4245 doesn't require spill registers, unlike the case when we are spilling this
4246 hard reg to produce another spill register.
4248 Return nonzero if any pseudos needed to be kicked out. */
4251 spill_hard_reg (unsigned int regno
, int cant_eliminate
)
4257 SET_HARD_REG_BIT (bad_spill_regs_global
, regno
);
4258 df_set_regs_ever_live (regno
, true);
4261 /* Spill every pseudo reg that was allocated to this reg
4262 or to something that overlaps this reg. */
4264 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
4265 if (reg_renumber
[i
] >= 0
4266 && (unsigned int) reg_renumber
[i
] <= regno
4267 && end_hard_regno (PSEUDO_REGNO_MODE (i
), reg_renumber
[i
]) > regno
)
4268 SET_REGNO_REG_SET (&spilled_pseudos
, i
);
4271 /* After find_reload_regs has been run for all insn that need reloads,
4272 and/or spill_hard_regs was called, this function is used to actually
4273 spill pseudo registers and try to reallocate them. It also sets up the
4274 spill_regs array for use by choose_reload_regs. */
4277 finish_spills (int global
)
4279 struct insn_chain
*chain
;
4280 int something_changed
= 0;
4282 reg_set_iterator rsi
;
4284 /* Build the spill_regs array for the function. */
4285 /* If there are some registers still to eliminate and one of the spill regs
4286 wasn't ever used before, additional stack space may have to be
4287 allocated to store this register. Thus, we may have changed the offset
4288 between the stack and frame pointers, so mark that something has changed.
4290 One might think that we need only set VAL to 1 if this is a call-used
4291 register. However, the set of registers that must be saved by the
4292 prologue is not identical to the call-used set. For example, the
4293 register used by the call insn for the return PC is a call-used register,
4294 but must be saved by the prologue. */
4297 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
4298 if (TEST_HARD_REG_BIT (used_spill_regs
, i
))
4300 spill_reg_order
[i
] = n_spills
;
4301 spill_regs
[n_spills
++] = i
;
4302 if (num_eliminable
&& ! df_regs_ever_live_p (i
))
4303 something_changed
= 1;
4304 df_set_regs_ever_live (i
, true);
4307 spill_reg_order
[i
] = -1;
4309 EXECUTE_IF_SET_IN_REG_SET (&spilled_pseudos
, FIRST_PSEUDO_REGISTER
, i
, rsi
)
4310 if (! ira_conflicts_p
|| reg_renumber
[i
] >= 0)
4312 /* Record the current hard register the pseudo is allocated to
4313 in pseudo_previous_regs so we avoid reallocating it to the
4314 same hard reg in a later pass. */
4315 gcc_assert (reg_renumber
[i
] >= 0);
4317 SET_HARD_REG_BIT (pseudo_previous_regs
[i
], reg_renumber
[i
]);
4318 /* Mark it as no longer having a hard register home. */
4319 reg_renumber
[i
] = -1;
4320 if (ira_conflicts_p
)
4321 /* Inform IRA about the change. */
4322 ira_mark_allocation_change (i
);
4323 /* We will need to scan everything again. */
4324 something_changed
= 1;
4327 /* Retry global register allocation if possible. */
4328 if (global
&& ira_conflicts_p
)
4332 memset (pseudo_forbidden_regs
, 0, max_regno
* sizeof (HARD_REG_SET
));
4333 /* For every insn that needs reloads, set the registers used as spill
4334 regs in pseudo_forbidden_regs for every pseudo live across the
4336 for (chain
= insns_need_reload
; chain
; chain
= chain
->next_need_reload
)
4338 EXECUTE_IF_SET_IN_REG_SET
4339 (&chain
->live_throughout
, FIRST_PSEUDO_REGISTER
, i
, rsi
)
4341 IOR_HARD_REG_SET (pseudo_forbidden_regs
[i
],
4342 chain
->used_spill_regs
);
4344 EXECUTE_IF_SET_IN_REG_SET
4345 (&chain
->dead_or_set
, FIRST_PSEUDO_REGISTER
, i
, rsi
)
4347 IOR_HARD_REG_SET (pseudo_forbidden_regs
[i
],
4348 chain
->used_spill_regs
);
4352 /* Retry allocating the pseudos spilled in IRA and the
4353 reload. For each reg, merge the various reg sets that
4354 indicate which hard regs can't be used, and call
4355 ira_reassign_pseudos. */
4356 for (n
= 0, i
= FIRST_PSEUDO_REGISTER
; i
< (unsigned) max_regno
; i
++)
4357 if (reg_old_renumber
[i
] != reg_renumber
[i
])
4359 if (reg_renumber
[i
] < 0)
4360 temp_pseudo_reg_arr
[n
++] = i
;
4362 CLEAR_REGNO_REG_SET (&spilled_pseudos
, i
);
4364 if (ira_reassign_pseudos (temp_pseudo_reg_arr
, n
,
4365 bad_spill_regs_global
,
4366 pseudo_forbidden_regs
, pseudo_previous_regs
,
4368 something_changed
= 1;
4370 /* Fix up the register information in the insn chain.
4371 This involves deleting those of the spilled pseudos which did not get
4372 a new hard register home from the live_{before,after} sets. */
4373 for (chain
= reload_insn_chain
; chain
; chain
= chain
->next
)
4375 HARD_REG_SET used_by_pseudos
;
4376 HARD_REG_SET used_by_pseudos2
;
4378 if (! ira_conflicts_p
)
4380 /* Don't do it for IRA because IRA and the reload still can
4381 assign hard registers to the spilled pseudos on next
4382 reload iterations. */
4383 AND_COMPL_REG_SET (&chain
->live_throughout
, &spilled_pseudos
);
4384 AND_COMPL_REG_SET (&chain
->dead_or_set
, &spilled_pseudos
);
4386 /* Mark any unallocated hard regs as available for spills. That
4387 makes inheritance work somewhat better. */
4388 if (chain
->need_reload
)
4390 REG_SET_TO_HARD_REG_SET (used_by_pseudos
, &chain
->live_throughout
);
4391 REG_SET_TO_HARD_REG_SET (used_by_pseudos2
, &chain
->dead_or_set
);
4392 IOR_HARD_REG_SET (used_by_pseudos
, used_by_pseudos2
);
4394 compute_use_by_pseudos (&used_by_pseudos
, &chain
->live_throughout
);
4395 compute_use_by_pseudos (&used_by_pseudos
, &chain
->dead_or_set
);
4396 /* Value of chain->used_spill_regs from previous iteration
4397 may be not included in the value calculated here because
4398 of possible removing caller-saves insns (see function
4399 delete_caller_save_insns. */
4400 COMPL_HARD_REG_SET (chain
->used_spill_regs
, used_by_pseudos
);
4401 AND_HARD_REG_SET (chain
->used_spill_regs
, used_spill_regs
);
4405 CLEAR_REG_SET (&changed_allocation_pseudos
);
4406 /* Let alter_reg modify the reg rtx's for the modified pseudos. */
4407 for (i
= FIRST_PSEUDO_REGISTER
; i
< (unsigned)max_regno
; i
++)
4409 int regno
= reg_renumber
[i
];
4410 if (reg_old_renumber
[i
] == regno
)
4413 SET_REGNO_REG_SET (&changed_allocation_pseudos
, i
);
4415 alter_reg (i
, reg_old_renumber
[i
], false);
4416 reg_old_renumber
[i
] = regno
;
4420 fprintf (dump_file
, " Register %d now on stack.\n\n", i
);
4422 fprintf (dump_file
, " Register %d now in %d.\n\n",
4423 i
, reg_renumber
[i
]);
4427 return something_changed
;
4430 /* Find all paradoxical subregs within X and update reg_max_ref_width. */
4433 scan_paradoxical_subregs (rtx x
)
4437 enum rtx_code code
= GET_CODE (x
);
4453 if (REG_P (SUBREG_REG (x
))
4454 && (GET_MODE_SIZE (GET_MODE (x
))
4455 > reg_max_ref_width
[REGNO (SUBREG_REG (x
))]))
4457 reg_max_ref_width
[REGNO (SUBREG_REG (x
))]
4458 = GET_MODE_SIZE (GET_MODE (x
));
4459 mark_home_live_1 (REGNO (SUBREG_REG (x
)), GET_MODE (x
));
4467 fmt
= GET_RTX_FORMAT (code
);
4468 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
4471 scan_paradoxical_subregs (XEXP (x
, i
));
4472 else if (fmt
[i
] == 'E')
4475 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
4476 scan_paradoxical_subregs (XVECEXP (x
, i
, j
));
4481 /* *OP_PTR and *OTHER_PTR are two operands to a conceptual reload.
4482 If *OP_PTR is a paradoxical subreg, try to remove that subreg
4483 and apply the corresponding narrowing subreg to *OTHER_PTR.
4484 Return true if the operands were changed, false otherwise. */
4487 strip_paradoxical_subreg (rtx
*op_ptr
, rtx
*other_ptr
)
4489 rtx op
, inner
, other
, tem
;
4492 if (!paradoxical_subreg_p (op
))
4494 inner
= SUBREG_REG (op
);
4497 tem
= gen_lowpart_common (GET_MODE (inner
), other
);
4501 /* If the lowpart operation turned a hard register into a subreg,
4502 rather than simplifying it to another hard register, then the
4503 mode change cannot be properly represented. For example, OTHER
4504 might be valid in its current mode, but not in the new one. */
4505 if (GET_CODE (tem
) == SUBREG
4507 && HARD_REGISTER_P (other
))
4515 /* A subroutine of reload_as_needed. If INSN has a REG_EH_REGION note,
4516 examine all of the reload insns between PREV and NEXT exclusive, and
4517 annotate all that may trap. */
4520 fixup_eh_region_note (rtx insn
, rtx prev
, rtx next
)
4522 rtx note
= find_reg_note (insn
, REG_EH_REGION
, NULL_RTX
);
4525 if (!insn_could_throw_p (insn
))
4526 remove_note (insn
, note
);
4527 copy_reg_eh_region_note_forward (note
, NEXT_INSN (prev
), next
);
4530 /* Reload pseudo-registers into hard regs around each insn as needed.
4531 Additional register load insns are output before the insn that needs it
4532 and perhaps store insns after insns that modify the reloaded pseudo reg.
4534 reg_last_reload_reg and reg_reloaded_contents keep track of
4535 which registers are already available in reload registers.
4536 We update these for the reloads that we perform,
4537 as the insns are scanned. */
4540 reload_as_needed (int live_known
)
4542 struct insn_chain
*chain
;
4543 #if defined (AUTO_INC_DEC)
4548 memset (spill_reg_rtx
, 0, sizeof spill_reg_rtx
);
4549 memset (spill_reg_store
, 0, sizeof spill_reg_store
);
4550 reg_last_reload_reg
= XCNEWVEC (rtx
, max_regno
);
4551 INIT_REG_SET (®_has_output_reload
);
4552 CLEAR_HARD_REG_SET (reg_reloaded_valid
);
4553 CLEAR_HARD_REG_SET (reg_reloaded_call_part_clobbered
);
4555 set_initial_elim_offsets ();
4557 /* Generate a marker insn that we will move around. */
4558 marker
= emit_note (NOTE_INSN_DELETED
);
4559 unlink_insn_chain (marker
, marker
);
4561 for (chain
= reload_insn_chain
; chain
; chain
= chain
->next
)
4564 rtx insn
= chain
->insn
;
4565 rtx old_next
= NEXT_INSN (insn
);
4567 rtx old_prev
= PREV_INSN (insn
);
4570 /* If we pass a label, copy the offsets from the label information
4571 into the current offsets of each elimination. */
4573 set_offsets_for_label (insn
);
4575 else if (INSN_P (insn
))
4577 regset_head regs_to_forget
;
4578 INIT_REG_SET (®s_to_forget
);
4579 note_stores (PATTERN (insn
), forget_old_reloads_1
, ®s_to_forget
);
4581 /* If this is a USE and CLOBBER of a MEM, ensure that any
4582 references to eliminable registers have been removed. */
4584 if ((GET_CODE (PATTERN (insn
)) == USE
4585 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
4586 && MEM_P (XEXP (PATTERN (insn
), 0)))
4587 XEXP (XEXP (PATTERN (insn
), 0), 0)
4588 = eliminate_regs (XEXP (XEXP (PATTERN (insn
), 0), 0),
4589 GET_MODE (XEXP (PATTERN (insn
), 0)),
4592 /* If we need to do register elimination processing, do so.
4593 This might delete the insn, in which case we are done. */
4594 if ((num_eliminable
|| num_eliminable_invariants
) && chain
->need_elim
)
4596 eliminate_regs_in_insn (insn
, 1);
4599 update_eliminable_offsets ();
4600 CLEAR_REG_SET (®s_to_forget
);
4605 /* If need_elim is nonzero but need_reload is zero, one might think
4606 that we could simply set n_reloads to 0. However, find_reloads
4607 could have done some manipulation of the insn (such as swapping
4608 commutative operands), and these manipulations are lost during
4609 the first pass for every insn that needs register elimination.
4610 So the actions of find_reloads must be redone here. */
4612 if (! chain
->need_elim
&& ! chain
->need_reload
4613 && ! chain
->need_operand_change
)
4615 /* First find the pseudo regs that must be reloaded for this insn.
4616 This info is returned in the tables reload_... (see reload.h).
4617 Also modify the body of INSN by substituting RELOAD
4618 rtx's for those pseudo regs. */
4621 CLEAR_REG_SET (®_has_output_reload
);
4622 CLEAR_HARD_REG_SET (reg_is_output_reload
);
4624 find_reloads (insn
, 1, spill_indirect_levels
, live_known
,
4630 rtx next
= NEXT_INSN (insn
);
4633 /* ??? PREV can get deleted by reload inheritance.
4634 Work around this by emitting a marker note. */
4635 prev
= PREV_INSN (insn
);
4636 reorder_insns_nobb (marker
, marker
, prev
);
4638 /* Now compute which reload regs to reload them into. Perhaps
4639 reusing reload regs from previous insns, or else output
4640 load insns to reload them. Maybe output store insns too.
4641 Record the choices of reload reg in reload_reg_rtx. */
4642 choose_reload_regs (chain
);
4644 /* Generate the insns to reload operands into or out of
4645 their reload regs. */
4646 emit_reload_insns (chain
);
4648 /* Substitute the chosen reload regs from reload_reg_rtx
4649 into the insn's body (or perhaps into the bodies of other
4650 load and store insn that we just made for reloading
4651 and that we moved the structure into). */
4652 subst_reloads (insn
);
4654 prev
= PREV_INSN (marker
);
4655 unlink_insn_chain (marker
, marker
);
4657 /* Adjust the exception region notes for loads and stores. */
4658 if (cfun
->can_throw_non_call_exceptions
&& !CALL_P (insn
))
4659 fixup_eh_region_note (insn
, prev
, next
);
4661 /* Adjust the location of REG_ARGS_SIZE. */
4662 p
= find_reg_note (insn
, REG_ARGS_SIZE
, NULL_RTX
);
4665 remove_note (insn
, p
);
4666 fixup_args_size_notes (prev
, PREV_INSN (next
),
4667 INTVAL (XEXP (p
, 0)));
4670 /* If this was an ASM, make sure that all the reload insns
4671 we have generated are valid. If not, give an error
4673 if (asm_noperands (PATTERN (insn
)) >= 0)
4674 for (p
= NEXT_INSN (prev
); p
!= next
; p
= NEXT_INSN (p
))
4675 if (p
!= insn
&& INSN_P (p
)
4676 && GET_CODE (PATTERN (p
)) != USE
4677 && (recog_memoized (p
) < 0
4678 || (extract_insn (p
), ! constrain_operands (1))))
4680 error_for_asm (insn
,
4681 "%<asm%> operand requires "
4682 "impossible reload");
4687 if (num_eliminable
&& chain
->need_elim
)
4688 update_eliminable_offsets ();
4690 /* Any previously reloaded spilled pseudo reg, stored in this insn,
4691 is no longer validly lying around to save a future reload.
4692 Note that this does not detect pseudos that were reloaded
4693 for this insn in order to be stored in
4694 (obeying register constraints). That is correct; such reload
4695 registers ARE still valid. */
4696 forget_marked_reloads (®s_to_forget
);
4697 CLEAR_REG_SET (®s_to_forget
);
4699 /* There may have been CLOBBER insns placed after INSN. So scan
4700 between INSN and NEXT and use them to forget old reloads. */
4701 for (x
= NEXT_INSN (insn
); x
!= old_next
; x
= NEXT_INSN (x
))
4702 if (NONJUMP_INSN_P (x
) && GET_CODE (PATTERN (x
)) == CLOBBER
)
4703 note_stores (PATTERN (x
), forget_old_reloads_1
, NULL
);
4706 /* Likewise for regs altered by auto-increment in this insn.
4707 REG_INC notes have been changed by reloading:
4708 find_reloads_address_1 records substitutions for them,
4709 which have been performed by subst_reloads above. */
4710 for (i
= n_reloads
- 1; i
>= 0; i
--)
4712 rtx in_reg
= rld
[i
].in_reg
;
4715 enum rtx_code code
= GET_CODE (in_reg
);
4716 /* PRE_INC / PRE_DEC will have the reload register ending up
4717 with the same value as the stack slot, but that doesn't
4718 hold true for POST_INC / POST_DEC. Either we have to
4719 convert the memory access to a true POST_INC / POST_DEC,
4720 or we can't use the reload register for inheritance. */
4721 if ((code
== POST_INC
|| code
== POST_DEC
)
4722 && TEST_HARD_REG_BIT (reg_reloaded_valid
,
4723 REGNO (rld
[i
].reg_rtx
))
4724 /* Make sure it is the inc/dec pseudo, and not
4725 some other (e.g. output operand) pseudo. */
4726 && ((unsigned) reg_reloaded_contents
[REGNO (rld
[i
].reg_rtx
)]
4727 == REGNO (XEXP (in_reg
, 0))))
4730 rtx reload_reg
= rld
[i
].reg_rtx
;
4731 enum machine_mode mode
= GET_MODE (reload_reg
);
4735 for (p
= PREV_INSN (old_next
); p
!= prev
; p
= PREV_INSN (p
))
4737 /* We really want to ignore REG_INC notes here, so
4738 use PATTERN (p) as argument to reg_set_p . */
4739 if (reg_set_p (reload_reg
, PATTERN (p
)))
4741 n
= count_occurrences (PATTERN (p
), reload_reg
, 0);
4747 = gen_rtx_fmt_e (code
, mode
, reload_reg
);
4749 validate_replace_rtx_group (reload_reg
,
4751 n
= verify_changes (0);
4753 /* We must also verify that the constraints
4754 are met after the replacement. Make sure
4755 extract_insn is only called for an insn
4756 where the replacements were found to be
4761 n
= constrain_operands (1);
4764 /* If the constraints were not met, then
4765 undo the replacement, else confirm it. */
4769 confirm_change_group ();
4775 add_reg_note (p
, REG_INC
, reload_reg
);
4776 /* Mark this as having an output reload so that the
4777 REG_INC processing code below won't invalidate
4778 the reload for inheritance. */
4779 SET_HARD_REG_BIT (reg_is_output_reload
,
4780 REGNO (reload_reg
));
4781 SET_REGNO_REG_SET (®_has_output_reload
,
4782 REGNO (XEXP (in_reg
, 0)));
4785 forget_old_reloads_1 (XEXP (in_reg
, 0), NULL_RTX
,
4788 else if ((code
== PRE_INC
|| code
== PRE_DEC
)
4789 && TEST_HARD_REG_BIT (reg_reloaded_valid
,
4790 REGNO (rld
[i
].reg_rtx
))
4791 /* Make sure it is the inc/dec pseudo, and not
4792 some other (e.g. output operand) pseudo. */
4793 && ((unsigned) reg_reloaded_contents
[REGNO (rld
[i
].reg_rtx
)]
4794 == REGNO (XEXP (in_reg
, 0))))
4796 SET_HARD_REG_BIT (reg_is_output_reload
,
4797 REGNO (rld
[i
].reg_rtx
));
4798 SET_REGNO_REG_SET (®_has_output_reload
,
4799 REGNO (XEXP (in_reg
, 0)));
4801 else if (code
== PRE_INC
|| code
== PRE_DEC
4802 || code
== POST_INC
|| code
== POST_DEC
)
4804 int in_regno
= REGNO (XEXP (in_reg
, 0));
4806 if (reg_last_reload_reg
[in_regno
] != NULL_RTX
)
4809 bool forget_p
= true;
4811 in_hard_regno
= REGNO (reg_last_reload_reg
[in_regno
]);
4812 if (TEST_HARD_REG_BIT (reg_reloaded_valid
,
4815 for (x
= old_prev
? NEXT_INSN (old_prev
) : insn
;
4818 if (x
== reg_reloaded_insn
[in_hard_regno
])
4824 /* If for some reasons, we didn't set up
4825 reg_last_reload_reg in this insn,
4826 invalidate inheritance from previous
4827 insns for the incremented/decremented
4828 register. Such registers will be not in
4829 reg_has_output_reload. Invalidate it
4830 also if the corresponding element in
4831 reg_reloaded_insn is also
4834 forget_old_reloads_1 (XEXP (in_reg
, 0),
4840 /* If a pseudo that got a hard register is auto-incremented,
4841 we must purge records of copying it into pseudos without
4843 for (x
= REG_NOTES (insn
); x
; x
= XEXP (x
, 1))
4844 if (REG_NOTE_KIND (x
) == REG_INC
)
4846 /* See if this pseudo reg was reloaded in this insn.
4847 If so, its last-reload info is still valid
4848 because it is based on this insn's reload. */
4849 for (i
= 0; i
< n_reloads
; i
++)
4850 if (rld
[i
].out
== XEXP (x
, 0))
4854 forget_old_reloads_1 (XEXP (x
, 0), NULL_RTX
, NULL
);
4858 /* A reload reg's contents are unknown after a label. */
4860 CLEAR_HARD_REG_SET (reg_reloaded_valid
);
4862 /* Don't assume a reload reg is still good after a call insn
4863 if it is a call-used reg, or if it contains a value that will
4864 be partially clobbered by the call. */
4865 else if (CALL_P (insn
))
4867 AND_COMPL_HARD_REG_SET (reg_reloaded_valid
, call_used_reg_set
);
4868 AND_COMPL_HARD_REG_SET (reg_reloaded_valid
, reg_reloaded_call_part_clobbered
);
4870 /* If this is a call to a setjmp-type function, we must not
4871 reuse any reload reg contents across the call; that will
4872 just be clobbered by other uses of the register in later
4873 code, before the longjmp. */
4874 if (find_reg_note (insn
, REG_SETJMP
, NULL_RTX
))
4875 CLEAR_HARD_REG_SET (reg_reloaded_valid
);
4880 free (reg_last_reload_reg
);
4881 CLEAR_REG_SET (®_has_output_reload
);
4884 /* Discard all record of any value reloaded from X,
4885 or reloaded in X from someplace else;
4886 unless X is an output reload reg of the current insn.
4888 X may be a hard reg (the reload reg)
4889 or it may be a pseudo reg that was reloaded from.
4891 When DATA is non-NULL just mark the registers in regset
4892 to be forgotten later. */
4895 forget_old_reloads_1 (rtx x
, const_rtx ignored ATTRIBUTE_UNUSED
,
4900 regset regs
= (regset
) data
;
4902 /* note_stores does give us subregs of hard regs,
4903 subreg_regno_offset requires a hard reg. */
4904 while (GET_CODE (x
) == SUBREG
)
4906 /* We ignore the subreg offset when calculating the regno,
4907 because we are using the entire underlying hard register
4917 if (regno
>= FIRST_PSEUDO_REGISTER
)
4923 nr
= hard_regno_nregs
[regno
][GET_MODE (x
)];
4924 /* Storing into a spilled-reg invalidates its contents.
4925 This can happen if a block-local pseudo is allocated to that reg
4926 and it wasn't spilled because this block's total need is 0.
4927 Then some insn might have an optional reload and use this reg. */
4929 for (i
= 0; i
< nr
; i
++)
4930 /* But don't do this if the reg actually serves as an output
4931 reload reg in the current instruction. */
4933 || ! TEST_HARD_REG_BIT (reg_is_output_reload
, regno
+ i
))
4935 CLEAR_HARD_REG_BIT (reg_reloaded_valid
, regno
+ i
);
4936 spill_reg_store
[regno
+ i
] = 0;
4942 SET_REGNO_REG_SET (regs
, regno
+ nr
);
4945 /* Since value of X has changed,
4946 forget any value previously copied from it. */
4949 /* But don't forget a copy if this is the output reload
4950 that establishes the copy's validity. */
4952 || !REGNO_REG_SET_P (®_has_output_reload
, regno
+ nr
))
4953 reg_last_reload_reg
[regno
+ nr
] = 0;
4957 /* Forget the reloads marked in regset by previous function. */
4959 forget_marked_reloads (regset regs
)
4962 reg_set_iterator rsi
;
4963 EXECUTE_IF_SET_IN_REG_SET (regs
, 0, reg
, rsi
)
4965 if (reg
< FIRST_PSEUDO_REGISTER
4966 /* But don't do this if the reg actually serves as an output
4967 reload reg in the current instruction. */
4969 || ! TEST_HARD_REG_BIT (reg_is_output_reload
, reg
)))
4971 CLEAR_HARD_REG_BIT (reg_reloaded_valid
, reg
);
4972 spill_reg_store
[reg
] = 0;
4975 || !REGNO_REG_SET_P (®_has_output_reload
, reg
))
4976 reg_last_reload_reg
[reg
] = 0;
4980 /* The following HARD_REG_SETs indicate when each hard register is
4981 used for a reload of various parts of the current insn. */
4983 /* If reg is unavailable for all reloads. */
4984 static HARD_REG_SET reload_reg_unavailable
;
4985 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
4986 static HARD_REG_SET reload_reg_used
;
4987 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
4988 static HARD_REG_SET reload_reg_used_in_input_addr
[MAX_RECOG_OPERANDS
];
4989 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */
4990 static HARD_REG_SET reload_reg_used_in_inpaddr_addr
[MAX_RECOG_OPERANDS
];
4991 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
4992 static HARD_REG_SET reload_reg_used_in_output_addr
[MAX_RECOG_OPERANDS
];
4993 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */
4994 static HARD_REG_SET reload_reg_used_in_outaddr_addr
[MAX_RECOG_OPERANDS
];
4995 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
4996 static HARD_REG_SET reload_reg_used_in_input
[MAX_RECOG_OPERANDS
];
4997 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
4998 static HARD_REG_SET reload_reg_used_in_output
[MAX_RECOG_OPERANDS
];
4999 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
5000 static HARD_REG_SET reload_reg_used_in_op_addr
;
5001 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */
5002 static HARD_REG_SET reload_reg_used_in_op_addr_reload
;
5003 /* If reg is in use for a RELOAD_FOR_INSN reload. */
5004 static HARD_REG_SET reload_reg_used_in_insn
;
5005 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
5006 static HARD_REG_SET reload_reg_used_in_other_addr
;
5008 /* If reg is in use as a reload reg for any sort of reload. */
5009 static HARD_REG_SET reload_reg_used_at_all
;
5011 /* If reg is use as an inherited reload. We just mark the first register
5013 static HARD_REG_SET reload_reg_used_for_inherit
;
5015 /* Records which hard regs are used in any way, either as explicit use or
5016 by being allocated to a pseudo during any point of the current insn. */
5017 static HARD_REG_SET reg_used_in_insn
;
5019 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
5020 TYPE. MODE is used to indicate how many consecutive regs are
5024 mark_reload_reg_in_use (unsigned int regno
, int opnum
, enum reload_type type
,
5025 enum machine_mode mode
)
5030 add_to_hard_reg_set (&reload_reg_used
, mode
, regno
);
5033 case RELOAD_FOR_INPUT_ADDRESS
:
5034 add_to_hard_reg_set (&reload_reg_used_in_input_addr
[opnum
], mode
, regno
);
5037 case RELOAD_FOR_INPADDR_ADDRESS
:
5038 add_to_hard_reg_set (&reload_reg_used_in_inpaddr_addr
[opnum
], mode
, regno
);
5041 case RELOAD_FOR_OUTPUT_ADDRESS
:
5042 add_to_hard_reg_set (&reload_reg_used_in_output_addr
[opnum
], mode
, regno
);
5045 case RELOAD_FOR_OUTADDR_ADDRESS
:
5046 add_to_hard_reg_set (&reload_reg_used_in_outaddr_addr
[opnum
], mode
, regno
);
5049 case RELOAD_FOR_OPERAND_ADDRESS
:
5050 add_to_hard_reg_set (&reload_reg_used_in_op_addr
, mode
, regno
);
5053 case RELOAD_FOR_OPADDR_ADDR
:
5054 add_to_hard_reg_set (&reload_reg_used_in_op_addr_reload
, mode
, regno
);
5057 case RELOAD_FOR_OTHER_ADDRESS
:
5058 add_to_hard_reg_set (&reload_reg_used_in_other_addr
, mode
, regno
);
5061 case RELOAD_FOR_INPUT
:
5062 add_to_hard_reg_set (&reload_reg_used_in_input
[opnum
], mode
, regno
);
5065 case RELOAD_FOR_OUTPUT
:
5066 add_to_hard_reg_set (&reload_reg_used_in_output
[opnum
], mode
, regno
);
5069 case RELOAD_FOR_INSN
:
5070 add_to_hard_reg_set (&reload_reg_used_in_insn
, mode
, regno
);
5074 add_to_hard_reg_set (&reload_reg_used_at_all
, mode
, regno
);
5077 /* Similarly, but show REGNO is no longer in use for a reload. */
5080 clear_reload_reg_in_use (unsigned int regno
, int opnum
,
5081 enum reload_type type
, enum machine_mode mode
)
5083 unsigned int nregs
= hard_regno_nregs
[regno
][mode
];
5084 unsigned int start_regno
, end_regno
, r
;
5086 /* A complication is that for some reload types, inheritance might
5087 allow multiple reloads of the same types to share a reload register.
5088 We set check_opnum if we have to check only reloads with the same
5089 operand number, and check_any if we have to check all reloads. */
5090 int check_opnum
= 0;
5092 HARD_REG_SET
*used_in_set
;
5097 used_in_set
= &reload_reg_used
;
5100 case RELOAD_FOR_INPUT_ADDRESS
:
5101 used_in_set
= &reload_reg_used_in_input_addr
[opnum
];
5104 case RELOAD_FOR_INPADDR_ADDRESS
:
5106 used_in_set
= &reload_reg_used_in_inpaddr_addr
[opnum
];
5109 case RELOAD_FOR_OUTPUT_ADDRESS
:
5110 used_in_set
= &reload_reg_used_in_output_addr
[opnum
];
5113 case RELOAD_FOR_OUTADDR_ADDRESS
:
5115 used_in_set
= &reload_reg_used_in_outaddr_addr
[opnum
];
5118 case RELOAD_FOR_OPERAND_ADDRESS
:
5119 used_in_set
= &reload_reg_used_in_op_addr
;
5122 case RELOAD_FOR_OPADDR_ADDR
:
5124 used_in_set
= &reload_reg_used_in_op_addr_reload
;
5127 case RELOAD_FOR_OTHER_ADDRESS
:
5128 used_in_set
= &reload_reg_used_in_other_addr
;
5132 case RELOAD_FOR_INPUT
:
5133 used_in_set
= &reload_reg_used_in_input
[opnum
];
5136 case RELOAD_FOR_OUTPUT
:
5137 used_in_set
= &reload_reg_used_in_output
[opnum
];
5140 case RELOAD_FOR_INSN
:
5141 used_in_set
= &reload_reg_used_in_insn
;
5146 /* We resolve conflicts with remaining reloads of the same type by
5147 excluding the intervals of reload registers by them from the
5148 interval of freed reload registers. Since we only keep track of
5149 one set of interval bounds, we might have to exclude somewhat
5150 more than what would be necessary if we used a HARD_REG_SET here.
5151 But this should only happen very infrequently, so there should
5152 be no reason to worry about it. */
5154 start_regno
= regno
;
5155 end_regno
= regno
+ nregs
;
5156 if (check_opnum
|| check_any
)
5158 for (i
= n_reloads
- 1; i
>= 0; i
--)
5160 if (rld
[i
].when_needed
== type
5161 && (check_any
|| rld
[i
].opnum
== opnum
)
5164 unsigned int conflict_start
= true_regnum (rld
[i
].reg_rtx
);
5165 unsigned int conflict_end
5166 = end_hard_regno (rld
[i
].mode
, conflict_start
);
5168 /* If there is an overlap with the first to-be-freed register,
5169 adjust the interval start. */
5170 if (conflict_start
<= start_regno
&& conflict_end
> start_regno
)
5171 start_regno
= conflict_end
;
5172 /* Otherwise, if there is a conflict with one of the other
5173 to-be-freed registers, adjust the interval end. */
5174 if (conflict_start
> start_regno
&& conflict_start
< end_regno
)
5175 end_regno
= conflict_start
;
5180 for (r
= start_regno
; r
< end_regno
; r
++)
5181 CLEAR_HARD_REG_BIT (*used_in_set
, r
);
5184 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
5185 specified by OPNUM and TYPE. */
5188 reload_reg_free_p (unsigned int regno
, int opnum
, enum reload_type type
)
5192 /* In use for a RELOAD_OTHER means it's not available for anything. */
5193 if (TEST_HARD_REG_BIT (reload_reg_used
, regno
)
5194 || TEST_HARD_REG_BIT (reload_reg_unavailable
, regno
))
5200 /* In use for anything means we can't use it for RELOAD_OTHER. */
5201 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr
, regno
)
5202 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
)
5203 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload
, regno
)
5204 || TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
))
5207 for (i
= 0; i
< reload_n_operands
; i
++)
5208 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
5209 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
)
5210 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
5211 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
)
5212 || TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
)
5213 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
5218 case RELOAD_FOR_INPUT
:
5219 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
5220 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
))
5223 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload
, regno
))
5226 /* If it is used for some other input, can't use it. */
5227 for (i
= 0; i
< reload_n_operands
; i
++)
5228 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
5231 /* If it is used in a later operand's address, can't use it. */
5232 for (i
= opnum
+ 1; i
< reload_n_operands
; i
++)
5233 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
5234 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
))
5239 case RELOAD_FOR_INPUT_ADDRESS
:
5240 /* Can't use a register if it is used for an input address for this
5241 operand or used as an input in an earlier one. */
5242 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[opnum
], regno
)
5243 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[opnum
], regno
))
5246 for (i
= 0; i
< opnum
; i
++)
5247 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
5252 case RELOAD_FOR_INPADDR_ADDRESS
:
5253 /* Can't use a register if it is used for an input address
5254 for this operand or used as an input in an earlier
5256 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[opnum
], regno
))
5259 for (i
= 0; i
< opnum
; i
++)
5260 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
5265 case RELOAD_FOR_OUTPUT_ADDRESS
:
5266 /* Can't use a register if it is used for an output address for this
5267 operand or used as an output in this or a later operand. Note
5268 that multiple output operands are emitted in reverse order, so
5269 the conflicting ones are those with lower indices. */
5270 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[opnum
], regno
))
5273 for (i
= 0; i
<= opnum
; i
++)
5274 if (TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
5279 case RELOAD_FOR_OUTADDR_ADDRESS
:
5280 /* Can't use a register if it is used for an output address
5281 for this operand or used as an output in this or a
5282 later operand. Note that multiple output operands are
5283 emitted in reverse order, so the conflicting ones are
5284 those with lower indices. */
5285 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[opnum
], regno
))
5288 for (i
= 0; i
<= opnum
; i
++)
5289 if (TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
5294 case RELOAD_FOR_OPERAND_ADDRESS
:
5295 for (i
= 0; i
< reload_n_operands
; i
++)
5296 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
5299 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
5300 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
));
5302 case RELOAD_FOR_OPADDR_ADDR
:
5303 for (i
= 0; i
< reload_n_operands
; i
++)
5304 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
5307 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload
, regno
));
5309 case RELOAD_FOR_OUTPUT
:
5310 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
5311 outputs, or an operand address for this or an earlier output.
5312 Note that multiple output operands are emitted in reverse order,
5313 so the conflicting ones are those with higher indices. */
5314 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
))
5317 for (i
= 0; i
< reload_n_operands
; i
++)
5318 if (TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
5321 for (i
= opnum
; i
< reload_n_operands
; i
++)
5322 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
5323 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
))
5328 case RELOAD_FOR_INSN
:
5329 for (i
= 0; i
< reload_n_operands
; i
++)
5330 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
)
5331 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
5334 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
5335 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
));
5337 case RELOAD_FOR_OTHER_ADDRESS
:
5338 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr
, regno
);
5345 /* Return 1 if the value in reload reg REGNO, as used by the reload with
5346 the number RELOADNUM, is still available in REGNO at the end of the insn.
5348 We can assume that the reload reg was already tested for availability
5349 at the time it is needed, and we should not check this again,
5350 in case the reg has already been marked in use. */
5353 reload_reg_reaches_end_p (unsigned int regno
, int reloadnum
)
5355 int opnum
= rld
[reloadnum
].opnum
;
5356 enum reload_type type
= rld
[reloadnum
].when_needed
;
5359 /* See if there is a reload with the same type for this operand, using
5360 the same register. This case is not handled by the code below. */
5361 for (i
= reloadnum
+ 1; i
< n_reloads
; i
++)
5366 if (rld
[i
].opnum
!= opnum
|| rld
[i
].when_needed
!= type
)
5368 reg
= rld
[i
].reg_rtx
;
5369 if (reg
== NULL_RTX
)
5371 nregs
= hard_regno_nregs
[REGNO (reg
)][GET_MODE (reg
)];
5372 if (regno
>= REGNO (reg
) && regno
< REGNO (reg
) + nregs
)
5379 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
5380 its value must reach the end. */
5383 /* If this use is for part of the insn,
5384 its value reaches if no subsequent part uses the same register.
5385 Just like the above function, don't try to do this with lots
5388 case RELOAD_FOR_OTHER_ADDRESS
:
5389 /* Here we check for everything else, since these don't conflict
5390 with anything else and everything comes later. */
5392 for (i
= 0; i
< reload_n_operands
; i
++)
5393 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
5394 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
)
5395 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
)
5396 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
5397 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
)
5398 || TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
5401 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
)
5402 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload
, regno
)
5403 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
5404 && ! TEST_HARD_REG_BIT (reload_reg_used
, regno
));
5406 case RELOAD_FOR_INPUT_ADDRESS
:
5407 case RELOAD_FOR_INPADDR_ADDRESS
:
5408 /* Similar, except that we check only for this and subsequent inputs
5409 and the address of only subsequent inputs and we do not need
5410 to check for RELOAD_OTHER objects since they are known not to
5413 for (i
= opnum
; i
< reload_n_operands
; i
++)
5414 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
5417 /* Reload register of reload with type RELOAD_FOR_INPADDR_ADDRESS
5418 could be killed if the register is also used by reload with type
5419 RELOAD_FOR_INPUT_ADDRESS, so check it. */
5420 if (type
== RELOAD_FOR_INPADDR_ADDRESS
5421 && TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[opnum
], regno
))
5424 for (i
= opnum
+ 1; i
< reload_n_operands
; i
++)
5425 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
5426 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
))
5429 for (i
= 0; i
< reload_n_operands
; i
++)
5430 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
5431 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
)
5432 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
5435 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload
, regno
))
5438 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
)
5439 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
5440 && !TEST_HARD_REG_BIT (reload_reg_used
, regno
));
5442 case RELOAD_FOR_INPUT
:
5443 /* Similar to input address, except we start at the next operand for
5444 both input and input address and we do not check for
5445 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
5448 for (i
= opnum
+ 1; i
< reload_n_operands
; i
++)
5449 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
5450 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
)
5451 || TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
5454 /* ... fall through ... */
5456 case RELOAD_FOR_OPERAND_ADDRESS
:
5457 /* Check outputs and their addresses. */
5459 for (i
= 0; i
< reload_n_operands
; i
++)
5460 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
5461 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
)
5462 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
5465 return (!TEST_HARD_REG_BIT (reload_reg_used
, regno
));
5467 case RELOAD_FOR_OPADDR_ADDR
:
5468 for (i
= 0; i
< reload_n_operands
; i
++)
5469 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
5470 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
)
5471 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
5474 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
)
5475 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
5476 && !TEST_HARD_REG_BIT (reload_reg_used
, regno
));
5478 case RELOAD_FOR_INSN
:
5479 /* These conflict with other outputs with RELOAD_OTHER. So
5480 we need only check for output addresses. */
5482 opnum
= reload_n_operands
;
5484 /* ... fall through ... */
5486 case RELOAD_FOR_OUTPUT
:
5487 case RELOAD_FOR_OUTPUT_ADDRESS
:
5488 case RELOAD_FOR_OUTADDR_ADDRESS
:
5489 /* We already know these can't conflict with a later output. So the
5490 only thing to check are later output addresses.
5491 Note that multiple output operands are emitted in reverse order,
5492 so the conflicting ones are those with lower indices. */
5493 for (i
= 0; i
< opnum
; i
++)
5494 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
5495 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
))
5498 /* Reload register of reload with type RELOAD_FOR_OUTADDR_ADDRESS
5499 could be killed if the register is also used by reload with type
5500 RELOAD_FOR_OUTPUT_ADDRESS, so check it. */
5501 if (type
== RELOAD_FOR_OUTADDR_ADDRESS
5502 && TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[opnum
], regno
))
5512 /* Like reload_reg_reaches_end_p, but check that the condition holds for
5513 every register in REG. */
5516 reload_reg_rtx_reaches_end_p (rtx reg
, int reloadnum
)
5520 for (i
= REGNO (reg
); i
< END_REGNO (reg
); i
++)
5521 if (!reload_reg_reaches_end_p (i
, reloadnum
))
5527 /* Returns whether R1 and R2 are uniquely chained: the value of one
5528 is used by the other, and that value is not used by any other
5529 reload for this insn. This is used to partially undo the decision
5530 made in find_reloads when in the case of multiple
5531 RELOAD_FOR_OPERAND_ADDRESS reloads it converts all
5532 RELOAD_FOR_OPADDR_ADDR reloads into RELOAD_FOR_OPERAND_ADDRESS
5533 reloads. This code tries to avoid the conflict created by that
5534 change. It might be cleaner to explicitly keep track of which
5535 RELOAD_FOR_OPADDR_ADDR reload is associated with which
5536 RELOAD_FOR_OPERAND_ADDRESS reload, rather than to try to detect
5537 this after the fact. */
5539 reloads_unique_chain_p (int r1
, int r2
)
5543 /* We only check input reloads. */
5544 if (! rld
[r1
].in
|| ! rld
[r2
].in
)
5547 /* Avoid anything with output reloads. */
5548 if (rld
[r1
].out
|| rld
[r2
].out
)
5551 /* "chained" means one reload is a component of the other reload,
5552 not the same as the other reload. */
5553 if (rld
[r1
].opnum
!= rld
[r2
].opnum
5554 || rtx_equal_p (rld
[r1
].in
, rld
[r2
].in
)
5555 || rld
[r1
].optional
|| rld
[r2
].optional
5556 || ! (reg_mentioned_p (rld
[r1
].in
, rld
[r2
].in
)
5557 || reg_mentioned_p (rld
[r2
].in
, rld
[r1
].in
)))
5560 for (i
= 0; i
< n_reloads
; i
++)
5561 /* Look for input reloads that aren't our two */
5562 if (i
!= r1
&& i
!= r2
&& rld
[i
].in
)
5564 /* If our reload is mentioned at all, it isn't a simple chain. */
5565 if (reg_mentioned_p (rld
[r1
].in
, rld
[i
].in
))
5571 /* The recursive function change all occurrences of WHAT in *WHERE
5574 substitute (rtx
*where
, const_rtx what
, rtx repl
)
5583 if (*where
== what
|| rtx_equal_p (*where
, what
))
5585 /* Record the location of the changed rtx. */
5586 substitute_stack
.safe_push (where
);
5591 code
= GET_CODE (*where
);
5592 fmt
= GET_RTX_FORMAT (code
);
5593 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
5599 for (j
= XVECLEN (*where
, i
) - 1; j
>= 0; j
--)
5600 substitute (&XVECEXP (*where
, i
, j
), what
, repl
);
5602 else if (fmt
[i
] == 'e')
5603 substitute (&XEXP (*where
, i
), what
, repl
);
5607 /* The function returns TRUE if chain of reload R1 and R2 (in any
5608 order) can be evaluated without usage of intermediate register for
5609 the reload containing another reload. It is important to see
5610 gen_reload to understand what the function is trying to do. As an
5611 example, let us have reload chain
5614 r1: <something> + const
5616 and reload R2 got reload reg HR. The function returns true if
5617 there is a correct insn HR = HR + <something>. Otherwise,
5618 gen_reload will use intermediate register (and this is the reload
5619 reg for R1) to reload <something>.
5621 We need this function to find a conflict for chain reloads. In our
5622 example, if HR = HR + <something> is incorrect insn, then we cannot
5623 use HR as a reload register for R2. If we do use it then we get a
5632 gen_reload_chain_without_interm_reg_p (int r1
, int r2
)
5634 /* Assume other cases in gen_reload are not possible for
5635 chain reloads or do need an intermediate hard registers. */
5639 rtx last
= get_last_insn ();
5641 /* Make r2 a component of r1. */
5642 if (reg_mentioned_p (rld
[r1
].in
, rld
[r2
].in
))
5648 gcc_assert (reg_mentioned_p (rld
[r2
].in
, rld
[r1
].in
));
5649 regno
= rld
[r1
].regno
>= 0 ? rld
[r1
].regno
: rld
[r2
].regno
;
5650 gcc_assert (regno
>= 0);
5651 out
= gen_rtx_REG (rld
[r1
].mode
, regno
);
5653 substitute (&in
, rld
[r2
].in
, gen_rtx_REG (rld
[r2
].mode
, regno
));
5655 /* If IN is a paradoxical SUBREG, remove it and try to put the
5656 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
5657 strip_paradoxical_subreg (&in
, &out
);
5659 if (GET_CODE (in
) == PLUS
5660 && (REG_P (XEXP (in
, 0))
5661 || GET_CODE (XEXP (in
, 0)) == SUBREG
5662 || MEM_P (XEXP (in
, 0)))
5663 && (REG_P (XEXP (in
, 1))
5664 || GET_CODE (XEXP (in
, 1)) == SUBREG
5665 || CONSTANT_P (XEXP (in
, 1))
5666 || MEM_P (XEXP (in
, 1))))
5668 insn
= emit_insn (gen_rtx_SET (VOIDmode
, out
, in
));
5669 code
= recog_memoized (insn
);
5674 extract_insn (insn
);
5675 /* We want constrain operands to treat this insn strictly in
5676 its validity determination, i.e., the way it would after
5677 reload has completed. */
5678 result
= constrain_operands (1);
5681 delete_insns_since (last
);
5684 /* Restore the original value at each changed address within R1. */
5685 while (!substitute_stack
.is_empty ())
5687 rtx
*where
= substitute_stack
.pop ();
5688 *where
= rld
[r2
].in
;
5694 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
5697 This function uses the same algorithm as reload_reg_free_p above. */
5700 reloads_conflict (int r1
, int r2
)
5702 enum reload_type r1_type
= rld
[r1
].when_needed
;
5703 enum reload_type r2_type
= rld
[r2
].when_needed
;
5704 int r1_opnum
= rld
[r1
].opnum
;
5705 int r2_opnum
= rld
[r2
].opnum
;
5707 /* RELOAD_OTHER conflicts with everything. */
5708 if (r2_type
== RELOAD_OTHER
)
5711 /* Otherwise, check conflicts differently for each type. */
5715 case RELOAD_FOR_INPUT
:
5716 return (r2_type
== RELOAD_FOR_INSN
5717 || r2_type
== RELOAD_FOR_OPERAND_ADDRESS
5718 || r2_type
== RELOAD_FOR_OPADDR_ADDR
5719 || r2_type
== RELOAD_FOR_INPUT
5720 || ((r2_type
== RELOAD_FOR_INPUT_ADDRESS
5721 || r2_type
== RELOAD_FOR_INPADDR_ADDRESS
)
5722 && r2_opnum
> r1_opnum
));
5724 case RELOAD_FOR_INPUT_ADDRESS
:
5725 return ((r2_type
== RELOAD_FOR_INPUT_ADDRESS
&& r1_opnum
== r2_opnum
)
5726 || (r2_type
== RELOAD_FOR_INPUT
&& r2_opnum
< r1_opnum
));
5728 case RELOAD_FOR_INPADDR_ADDRESS
:
5729 return ((r2_type
== RELOAD_FOR_INPADDR_ADDRESS
&& r1_opnum
== r2_opnum
)
5730 || (r2_type
== RELOAD_FOR_INPUT
&& r2_opnum
< r1_opnum
));
5732 case RELOAD_FOR_OUTPUT_ADDRESS
:
5733 return ((r2_type
== RELOAD_FOR_OUTPUT_ADDRESS
&& r2_opnum
== r1_opnum
)
5734 || (r2_type
== RELOAD_FOR_OUTPUT
&& r2_opnum
<= r1_opnum
));
5736 case RELOAD_FOR_OUTADDR_ADDRESS
:
5737 return ((r2_type
== RELOAD_FOR_OUTADDR_ADDRESS
&& r2_opnum
== r1_opnum
)
5738 || (r2_type
== RELOAD_FOR_OUTPUT
&& r2_opnum
<= r1_opnum
));
5740 case RELOAD_FOR_OPERAND_ADDRESS
:
5741 return (r2_type
== RELOAD_FOR_INPUT
|| r2_type
== RELOAD_FOR_INSN
5742 || (r2_type
== RELOAD_FOR_OPERAND_ADDRESS
5743 && (!reloads_unique_chain_p (r1
, r2
)
5744 || !gen_reload_chain_without_interm_reg_p (r1
, r2
))));
5746 case RELOAD_FOR_OPADDR_ADDR
:
5747 return (r2_type
== RELOAD_FOR_INPUT
5748 || r2_type
== RELOAD_FOR_OPADDR_ADDR
);
5750 case RELOAD_FOR_OUTPUT
:
5751 return (r2_type
== RELOAD_FOR_INSN
|| r2_type
== RELOAD_FOR_OUTPUT
5752 || ((r2_type
== RELOAD_FOR_OUTPUT_ADDRESS
5753 || r2_type
== RELOAD_FOR_OUTADDR_ADDRESS
)
5754 && r2_opnum
>= r1_opnum
));
5756 case RELOAD_FOR_INSN
:
5757 return (r2_type
== RELOAD_FOR_INPUT
|| r2_type
== RELOAD_FOR_OUTPUT
5758 || r2_type
== RELOAD_FOR_INSN
5759 || r2_type
== RELOAD_FOR_OPERAND_ADDRESS
);
5761 case RELOAD_FOR_OTHER_ADDRESS
:
5762 return r2_type
== RELOAD_FOR_OTHER_ADDRESS
;
5772 /* Indexed by reload number, 1 if incoming value
5773 inherited from previous insns. */
5774 static char reload_inherited
[MAX_RELOADS
];
5776 /* For an inherited reload, this is the insn the reload was inherited from,
5777 if we know it. Otherwise, this is 0. */
5778 static rtx reload_inheritance_insn
[MAX_RELOADS
];
5780 /* If nonzero, this is a place to get the value of the reload,
5781 rather than using reload_in. */
5782 static rtx reload_override_in
[MAX_RELOADS
];
5784 /* For each reload, the hard register number of the register used,
5785 or -1 if we did not need a register for this reload. */
5786 static int reload_spill_index
[MAX_RELOADS
];
5788 /* Index X is the value of rld[X].reg_rtx, adjusted for the input mode. */
5789 static rtx reload_reg_rtx_for_input
[MAX_RELOADS
];
5791 /* Index X is the value of rld[X].reg_rtx, adjusted for the output mode. */
5792 static rtx reload_reg_rtx_for_output
[MAX_RELOADS
];
5794 /* Subroutine of free_for_value_p, used to check a single register.
5795 START_REGNO is the starting regno of the full reload register
5796 (possibly comprising multiple hard registers) that we are considering. */
5799 reload_reg_free_for_value_p (int start_regno
, int regno
, int opnum
,
5800 enum reload_type type
, rtx value
, rtx out
,
5801 int reloadnum
, int ignore_address_reloads
)
5804 /* Set if we see an input reload that must not share its reload register
5805 with any new earlyclobber, but might otherwise share the reload
5806 register with an output or input-output reload. */
5807 int check_earlyclobber
= 0;
5811 if (TEST_HARD_REG_BIT (reload_reg_unavailable
, regno
))
5814 if (out
== const0_rtx
)
5820 /* We use some pseudo 'time' value to check if the lifetimes of the
5821 new register use would overlap with the one of a previous reload
5822 that is not read-only or uses a different value.
5823 The 'time' used doesn't have to be linear in any shape or form, just
5825 Some reload types use different 'buckets' for each operand.
5826 So there are MAX_RECOG_OPERANDS different time values for each
5828 We compute TIME1 as the time when the register for the prospective
5829 new reload ceases to be live, and TIME2 for each existing
5830 reload as the time when that the reload register of that reload
5832 Where there is little to be gained by exact lifetime calculations,
5833 we just make conservative assumptions, i.e. a longer lifetime;
5834 this is done in the 'default:' cases. */
5837 case RELOAD_FOR_OTHER_ADDRESS
:
5838 /* RELOAD_FOR_OTHER_ADDRESS conflicts with RELOAD_OTHER reloads. */
5839 time1
= copy
? 0 : 1;
5842 time1
= copy
? 1 : MAX_RECOG_OPERANDS
* 5 + 5;
5844 /* For each input, we may have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
5845 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 ,
5846 respectively, to the time values for these, we get distinct time
5847 values. To get distinct time values for each operand, we have to
5848 multiply opnum by at least three. We round that up to four because
5849 multiply by four is often cheaper. */
5850 case RELOAD_FOR_INPADDR_ADDRESS
:
5851 time1
= opnum
* 4 + 2;
5853 case RELOAD_FOR_INPUT_ADDRESS
:
5854 time1
= opnum
* 4 + 3;
5856 case RELOAD_FOR_INPUT
:
5857 /* All RELOAD_FOR_INPUT reloads remain live till the instruction
5858 executes (inclusive). */
5859 time1
= copy
? opnum
* 4 + 4 : MAX_RECOG_OPERANDS
* 4 + 3;
5861 case RELOAD_FOR_OPADDR_ADDR
:
5863 <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
5864 time1
= MAX_RECOG_OPERANDS
* 4 + 1;
5866 case RELOAD_FOR_OPERAND_ADDRESS
:
5867 /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn
5869 time1
= copy
? MAX_RECOG_OPERANDS
* 4 + 2 : MAX_RECOG_OPERANDS
* 4 + 3;
5871 case RELOAD_FOR_OUTADDR_ADDRESS
:
5872 time1
= MAX_RECOG_OPERANDS
* 4 + 4 + opnum
;
5874 case RELOAD_FOR_OUTPUT_ADDRESS
:
5875 time1
= MAX_RECOG_OPERANDS
* 4 + 5 + opnum
;
5878 time1
= MAX_RECOG_OPERANDS
* 5 + 5;
5881 for (i
= 0; i
< n_reloads
; i
++)
5883 rtx reg
= rld
[i
].reg_rtx
;
5884 if (reg
&& REG_P (reg
)
5885 && ((unsigned) regno
- true_regnum (reg
)
5886 <= hard_regno_nregs
[REGNO (reg
)][GET_MODE (reg
)] - (unsigned) 1)
5889 rtx other_input
= rld
[i
].in
;
5891 /* If the other reload loads the same input value, that
5892 will not cause a conflict only if it's loading it into
5893 the same register. */
5894 if (true_regnum (reg
) != start_regno
)
5895 other_input
= NULL_RTX
;
5896 if (! other_input
|| ! rtx_equal_p (other_input
, value
)
5897 || rld
[i
].out
|| out
)
5900 switch (rld
[i
].when_needed
)
5902 case RELOAD_FOR_OTHER_ADDRESS
:
5905 case RELOAD_FOR_INPADDR_ADDRESS
:
5906 /* find_reloads makes sure that a
5907 RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used
5908 by at most one - the first -
5909 RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the
5910 address reload is inherited, the address address reload
5911 goes away, so we can ignore this conflict. */
5912 if (type
== RELOAD_FOR_INPUT_ADDRESS
&& reloadnum
== i
+ 1
5913 && ignore_address_reloads
5914 /* Unless the RELOAD_FOR_INPUT is an auto_inc expression.
5915 Then the address address is still needed to store
5916 back the new address. */
5917 && ! rld
[reloadnum
].out
)
5919 /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its
5920 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS
5922 if (type
== RELOAD_FOR_INPUT
&& opnum
== rld
[i
].opnum
5923 && ignore_address_reloads
5924 /* Unless we are reloading an auto_inc expression. */
5925 && ! rld
[reloadnum
].out
)
5927 time2
= rld
[i
].opnum
* 4 + 2;
5929 case RELOAD_FOR_INPUT_ADDRESS
:
5930 if (type
== RELOAD_FOR_INPUT
&& opnum
== rld
[i
].opnum
5931 && ignore_address_reloads
5932 && ! rld
[reloadnum
].out
)
5934 time2
= rld
[i
].opnum
* 4 + 3;
5936 case RELOAD_FOR_INPUT
:
5937 time2
= rld
[i
].opnum
* 4 + 4;
5938 check_earlyclobber
= 1;
5940 /* rld[i].opnum * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4
5941 == MAX_RECOG_OPERAND * 4 */
5942 case RELOAD_FOR_OPADDR_ADDR
:
5943 if (type
== RELOAD_FOR_OPERAND_ADDRESS
&& reloadnum
== i
+ 1
5944 && ignore_address_reloads
5945 && ! rld
[reloadnum
].out
)
5947 time2
= MAX_RECOG_OPERANDS
* 4 + 1;
5949 case RELOAD_FOR_OPERAND_ADDRESS
:
5950 time2
= MAX_RECOG_OPERANDS
* 4 + 2;
5951 check_earlyclobber
= 1;
5953 case RELOAD_FOR_INSN
:
5954 time2
= MAX_RECOG_OPERANDS
* 4 + 3;
5956 case RELOAD_FOR_OUTPUT
:
5957 /* All RELOAD_FOR_OUTPUT reloads become live just after the
5958 instruction is executed. */
5959 time2
= MAX_RECOG_OPERANDS
* 4 + 4;
5961 /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with
5962 the RELOAD_FOR_OUTPUT reloads, so assign it the same time
5964 case RELOAD_FOR_OUTADDR_ADDRESS
:
5965 if (type
== RELOAD_FOR_OUTPUT_ADDRESS
&& reloadnum
== i
+ 1
5966 && ignore_address_reloads
5967 && ! rld
[reloadnum
].out
)
5969 time2
= MAX_RECOG_OPERANDS
* 4 + 4 + rld
[i
].opnum
;
5971 case RELOAD_FOR_OUTPUT_ADDRESS
:
5972 time2
= MAX_RECOG_OPERANDS
* 4 + 5 + rld
[i
].opnum
;
5975 /* If there is no conflict in the input part, handle this
5976 like an output reload. */
5977 if (! rld
[i
].in
|| rtx_equal_p (other_input
, value
))
5979 time2
= MAX_RECOG_OPERANDS
* 4 + 4;
5980 /* Earlyclobbered outputs must conflict with inputs. */
5981 if (earlyclobber_operand_p (rld
[i
].out
))
5982 time2
= MAX_RECOG_OPERANDS
* 4 + 3;
5987 /* RELOAD_OTHER might be live beyond instruction execution,
5988 but this is not obvious when we set time2 = 1. So check
5989 here if there might be a problem with the new reload
5990 clobbering the register used by the RELOAD_OTHER. */
5998 && (! rld
[i
].in
|| rld
[i
].out
5999 || ! rtx_equal_p (other_input
, value
)))
6000 || (out
&& rld
[reloadnum
].out_reg
6001 && time2
>= MAX_RECOG_OPERANDS
* 4 + 3))
6007 /* Earlyclobbered outputs must conflict with inputs. */
6008 if (check_earlyclobber
&& out
&& earlyclobber_operand_p (out
))
6014 /* Return 1 if the value in reload reg REGNO, as used by a reload
6015 needed for the part of the insn specified by OPNUM and TYPE,
6016 may be used to load VALUE into it.
6018 MODE is the mode in which the register is used, this is needed to
6019 determine how many hard regs to test.
6021 Other read-only reloads with the same value do not conflict
6022 unless OUT is nonzero and these other reloads have to live while
6023 output reloads live.
6024 If OUT is CONST0_RTX, this is a special case: it means that the
6025 test should not be for using register REGNO as reload register, but
6026 for copying from register REGNO into the reload register.
6028 RELOADNUM is the number of the reload we want to load this value for;
6029 a reload does not conflict with itself.
6031 When IGNORE_ADDRESS_RELOADS is set, we can not have conflicts with
6032 reloads that load an address for the very reload we are considering.
6034 The caller has to make sure that there is no conflict with the return
6038 free_for_value_p (int regno
, enum machine_mode mode
, int opnum
,
6039 enum reload_type type
, rtx value
, rtx out
, int reloadnum
,
6040 int ignore_address_reloads
)
6042 int nregs
= hard_regno_nregs
[regno
][mode
];
6044 if (! reload_reg_free_for_value_p (regno
, regno
+ nregs
, opnum
, type
,
6045 value
, out
, reloadnum
,
6046 ignore_address_reloads
))
6051 /* Return nonzero if the rtx X is invariant over the current function. */
6052 /* ??? Actually, the places where we use this expect exactly what is
6053 tested here, and not everything that is function invariant. In
6054 particular, the frame pointer and arg pointer are special cased;
6055 pic_offset_table_rtx is not, and we must not spill these things to
6059 function_invariant_p (const_rtx x
)
6063 if (x
== frame_pointer_rtx
|| x
== arg_pointer_rtx
)
6065 if (GET_CODE (x
) == PLUS
6066 && (XEXP (x
, 0) == frame_pointer_rtx
|| XEXP (x
, 0) == arg_pointer_rtx
)
6067 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
6072 /* Determine whether the reload reg X overlaps any rtx'es used for
6073 overriding inheritance. Return nonzero if so. */
6076 conflicts_with_override (rtx x
)
6079 for (i
= 0; i
< n_reloads
; i
++)
6080 if (reload_override_in
[i
]
6081 && reg_overlap_mentioned_p (x
, reload_override_in
[i
]))
6086 /* Give an error message saying we failed to find a reload for INSN,
6087 and clear out reload R. */
6089 failed_reload (rtx insn
, int r
)
6091 if (asm_noperands (PATTERN (insn
)) < 0)
6092 /* It's the compiler's fault. */
6093 fatal_insn ("could not find a spill register", insn
);
6095 /* It's the user's fault; the operand's mode and constraint
6096 don't match. Disable this reload so we don't crash in final. */
6097 error_for_asm (insn
,
6098 "%<asm%> operand constraint incompatible with operand size");
6102 rld
[r
].optional
= 1;
6103 rld
[r
].secondary_p
= 1;
6106 /* I is the index in SPILL_REG_RTX of the reload register we are to allocate
6107 for reload R. If it's valid, get an rtx for it. Return nonzero if
6110 set_reload_reg (int i
, int r
)
6112 /* regno is 'set but not used' if HARD_REGNO_MODE_OK doesn't use its first
6114 int regno ATTRIBUTE_UNUSED
;
6115 rtx reg
= spill_reg_rtx
[i
];
6117 if (reg
== 0 || GET_MODE (reg
) != rld
[r
].mode
)
6118 spill_reg_rtx
[i
] = reg
6119 = gen_rtx_REG (rld
[r
].mode
, spill_regs
[i
]);
6121 regno
= true_regnum (reg
);
6123 /* Detect when the reload reg can't hold the reload mode.
6124 This used to be one `if', but Sequent compiler can't handle that. */
6125 if (HARD_REGNO_MODE_OK (regno
, rld
[r
].mode
))
6127 enum machine_mode test_mode
= VOIDmode
;
6129 test_mode
= GET_MODE (rld
[r
].in
);
6130 /* If rld[r].in has VOIDmode, it means we will load it
6131 in whatever mode the reload reg has: to wit, rld[r].mode.
6132 We have already tested that for validity. */
6133 /* Aside from that, we need to test that the expressions
6134 to reload from or into have modes which are valid for this
6135 reload register. Otherwise the reload insns would be invalid. */
6136 if (! (rld
[r
].in
!= 0 && test_mode
!= VOIDmode
6137 && ! HARD_REGNO_MODE_OK (regno
, test_mode
)))
6138 if (! (rld
[r
].out
!= 0
6139 && ! HARD_REGNO_MODE_OK (regno
, GET_MODE (rld
[r
].out
))))
6141 /* The reg is OK. */
6144 /* Mark as in use for this insn the reload regs we use
6146 mark_reload_reg_in_use (spill_regs
[i
], rld
[r
].opnum
,
6147 rld
[r
].when_needed
, rld
[r
].mode
);
6149 rld
[r
].reg_rtx
= reg
;
6150 reload_spill_index
[r
] = spill_regs
[i
];
6157 /* Find a spill register to use as a reload register for reload R.
6158 LAST_RELOAD is nonzero if this is the last reload for the insn being
6161 Set rld[R].reg_rtx to the register allocated.
6163 We return 1 if successful, or 0 if we couldn't find a spill reg and
6164 we didn't change anything. */
6167 allocate_reload_reg (struct insn_chain
*chain ATTRIBUTE_UNUSED
, int r
,
6172 /* If we put this reload ahead, thinking it is a group,
6173 then insist on finding a group. Otherwise we can grab a
6174 reg that some other reload needs.
6175 (That can happen when we have a 68000 DATA_OR_FP_REG
6176 which is a group of data regs or one fp reg.)
6177 We need not be so restrictive if there are no more reloads
6180 ??? Really it would be nicer to have smarter handling
6181 for that kind of reg class, where a problem like this is normal.
6182 Perhaps those classes should be avoided for reloading
6183 by use of more alternatives. */
6185 int force_group
= rld
[r
].nregs
> 1 && ! last_reload
;
6187 /* If we want a single register and haven't yet found one,
6188 take any reg in the right class and not in use.
6189 If we want a consecutive group, here is where we look for it.
6191 We use three passes so we can first look for reload regs to
6192 reuse, which are already in use for other reloads in this insn,
6193 and only then use additional registers which are not "bad", then
6194 finally any register.
6196 I think that maximizing reuse is needed to make sure we don't
6197 run out of reload regs. Suppose we have three reloads, and
6198 reloads A and B can share regs. These need two regs.
6199 Suppose A and B are given different regs.
6200 That leaves none for C. */
6201 for (pass
= 0; pass
< 3; pass
++)
6203 /* I is the index in spill_regs.
6204 We advance it round-robin between insns to use all spill regs
6205 equally, so that inherited reloads have a chance
6206 of leapfrogging each other. */
6210 for (count
= 0; count
< n_spills
; count
++)
6212 int rclass
= (int) rld
[r
].rclass
;
6218 regnum
= spill_regs
[i
];
6220 if ((reload_reg_free_p (regnum
, rld
[r
].opnum
,
6223 /* We check reload_reg_used to make sure we
6224 don't clobber the return register. */
6225 && ! TEST_HARD_REG_BIT (reload_reg_used
, regnum
)
6226 && free_for_value_p (regnum
, rld
[r
].mode
, rld
[r
].opnum
,
6227 rld
[r
].when_needed
, rld
[r
].in
,
6229 && TEST_HARD_REG_BIT (reg_class_contents
[rclass
], regnum
)
6230 && HARD_REGNO_MODE_OK (regnum
, rld
[r
].mode
)
6231 /* Look first for regs to share, then for unshared. But
6232 don't share regs used for inherited reloads; they are
6233 the ones we want to preserve. */
6235 || (TEST_HARD_REG_BIT (reload_reg_used_at_all
,
6237 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit
,
6240 int nr
= hard_regno_nregs
[regnum
][rld
[r
].mode
];
6242 /* During the second pass we want to avoid reload registers
6243 which are "bad" for this reload. */
6245 && ira_bad_reload_regno (regnum
, rld
[r
].in
, rld
[r
].out
))
6248 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
6249 (on 68000) got us two FP regs. If NR is 1,
6250 we would reject both of them. */
6253 /* If we need only one reg, we have already won. */
6256 /* But reject a single reg if we demand a group. */
6261 /* Otherwise check that as many consecutive regs as we need
6262 are available here. */
6265 int regno
= regnum
+ nr
- 1;
6266 if (!(TEST_HARD_REG_BIT (reg_class_contents
[rclass
], regno
)
6267 && spill_reg_order
[regno
] >= 0
6268 && reload_reg_free_p (regno
, rld
[r
].opnum
,
6269 rld
[r
].when_needed
)))
6278 /* If we found something on the current pass, omit later passes. */
6279 if (count
< n_spills
)
6283 /* We should have found a spill register by now. */
6284 if (count
>= n_spills
)
6287 /* I is the index in SPILL_REG_RTX of the reload register we are to
6288 allocate. Get an rtx for it and find its register number. */
6290 return set_reload_reg (i
, r
);
6293 /* Initialize all the tables needed to allocate reload registers.
6294 CHAIN is the insn currently being processed; SAVE_RELOAD_REG_RTX
6295 is the array we use to restore the reg_rtx field for every reload. */
6298 choose_reload_regs_init (struct insn_chain
*chain
, rtx
*save_reload_reg_rtx
)
6302 for (i
= 0; i
< n_reloads
; i
++)
6303 rld
[i
].reg_rtx
= save_reload_reg_rtx
[i
];
6305 memset (reload_inherited
, 0, MAX_RELOADS
);
6306 memset (reload_inheritance_insn
, 0, MAX_RELOADS
* sizeof (rtx
));
6307 memset (reload_override_in
, 0, MAX_RELOADS
* sizeof (rtx
));
6309 CLEAR_HARD_REG_SET (reload_reg_used
);
6310 CLEAR_HARD_REG_SET (reload_reg_used_at_all
);
6311 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr
);
6312 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload
);
6313 CLEAR_HARD_REG_SET (reload_reg_used_in_insn
);
6314 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr
);
6316 CLEAR_HARD_REG_SET (reg_used_in_insn
);
6319 REG_SET_TO_HARD_REG_SET (tmp
, &chain
->live_throughout
);
6320 IOR_HARD_REG_SET (reg_used_in_insn
, tmp
);
6321 REG_SET_TO_HARD_REG_SET (tmp
, &chain
->dead_or_set
);
6322 IOR_HARD_REG_SET (reg_used_in_insn
, tmp
);
6323 compute_use_by_pseudos (®_used_in_insn
, &chain
->live_throughout
);
6324 compute_use_by_pseudos (®_used_in_insn
, &chain
->dead_or_set
);
6327 for (i
= 0; i
< reload_n_operands
; i
++)
6329 CLEAR_HARD_REG_SET (reload_reg_used_in_output
[i
]);
6330 CLEAR_HARD_REG_SET (reload_reg_used_in_input
[i
]);
6331 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr
[i
]);
6332 CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr
[i
]);
6333 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr
[i
]);
6334 CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr
[i
]);
6337 COMPL_HARD_REG_SET (reload_reg_unavailable
, chain
->used_spill_regs
);
6339 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit
);
6341 for (i
= 0; i
< n_reloads
; i
++)
6342 /* If we have already decided to use a certain register,
6343 don't use it in another way. */
6345 mark_reload_reg_in_use (REGNO (rld
[i
].reg_rtx
), rld
[i
].opnum
,
6346 rld
[i
].when_needed
, rld
[i
].mode
);
6349 #ifdef SECONDARY_MEMORY_NEEDED
6350 /* If X is not a subreg, return it unmodified. If it is a subreg,
6351 look up whether we made a replacement for the SUBREG_REG. Return
6352 either the replacement or the SUBREG_REG. */
6355 replaced_subreg (rtx x
)
6357 if (GET_CODE (x
) == SUBREG
)
6358 return find_replacement (&SUBREG_REG (x
));
6363 /* Assign hard reg targets for the pseudo-registers we must reload
6364 into hard regs for this insn.
6365 Also output the instructions to copy them in and out of the hard regs.
6367 For machines with register classes, we are responsible for
6368 finding a reload reg in the proper class. */
6371 choose_reload_regs (struct insn_chain
*chain
)
6373 rtx insn
= chain
->insn
;
6375 unsigned int max_group_size
= 1;
6376 enum reg_class group_class
= NO_REGS
;
6377 int pass
, win
, inheritance
;
6379 rtx save_reload_reg_rtx
[MAX_RELOADS
];
6381 /* In order to be certain of getting the registers we need,
6382 we must sort the reloads into order of increasing register class.
6383 Then our grabbing of reload registers will parallel the process
6384 that provided the reload registers.
6386 Also note whether any of the reloads wants a consecutive group of regs.
6387 If so, record the maximum size of the group desired and what
6388 register class contains all the groups needed by this insn. */
6390 for (j
= 0; j
< n_reloads
; j
++)
6392 reload_order
[j
] = j
;
6393 if (rld
[j
].reg_rtx
!= NULL_RTX
)
6395 gcc_assert (REG_P (rld
[j
].reg_rtx
)
6396 && HARD_REGISTER_P (rld
[j
].reg_rtx
));
6397 reload_spill_index
[j
] = REGNO (rld
[j
].reg_rtx
);
6400 reload_spill_index
[j
] = -1;
6402 if (rld
[j
].nregs
> 1)
6404 max_group_size
= MAX (rld
[j
].nregs
, max_group_size
);
6406 = reg_class_superunion
[(int) rld
[j
].rclass
][(int) group_class
];
6409 save_reload_reg_rtx
[j
] = rld
[j
].reg_rtx
;
6413 qsort (reload_order
, n_reloads
, sizeof (short), reload_reg_class_lower
);
6415 /* If -O, try first with inheritance, then turning it off.
6416 If not -O, don't do inheritance.
6417 Using inheritance when not optimizing leads to paradoxes
6418 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
6419 because one side of the comparison might be inherited. */
6421 for (inheritance
= optimize
> 0; inheritance
>= 0; inheritance
--)
6423 choose_reload_regs_init (chain
, save_reload_reg_rtx
);
6425 /* Process the reloads in order of preference just found.
6426 Beyond this point, subregs can be found in reload_reg_rtx.
6428 This used to look for an existing reloaded home for all of the
6429 reloads, and only then perform any new reloads. But that could lose
6430 if the reloads were done out of reg-class order because a later
6431 reload with a looser constraint might have an old home in a register
6432 needed by an earlier reload with a tighter constraint.
6434 To solve this, we make two passes over the reloads, in the order
6435 described above. In the first pass we try to inherit a reload
6436 from a previous insn. If there is a later reload that needs a
6437 class that is a proper subset of the class being processed, we must
6438 also allocate a spill register during the first pass.
6440 Then make a second pass over the reloads to allocate any reloads
6441 that haven't been given registers yet. */
6443 for (j
= 0; j
< n_reloads
; j
++)
6445 int r
= reload_order
[j
];
6446 rtx search_equiv
= NULL_RTX
;
6448 /* Ignore reloads that got marked inoperative. */
6449 if (rld
[r
].out
== 0 && rld
[r
].in
== 0
6450 && ! rld
[r
].secondary_p
)
6453 /* If find_reloads chose to use reload_in or reload_out as a reload
6454 register, we don't need to chose one. Otherwise, try even if it
6455 found one since we might save an insn if we find the value lying
6457 Try also when reload_in is a pseudo without a hard reg. */
6458 if (rld
[r
].in
!= 0 && rld
[r
].reg_rtx
!= 0
6459 && (rtx_equal_p (rld
[r
].in
, rld
[r
].reg_rtx
)
6460 || (rtx_equal_p (rld
[r
].out
, rld
[r
].reg_rtx
)
6461 && !MEM_P (rld
[r
].in
)
6462 && true_regnum (rld
[r
].in
) < FIRST_PSEUDO_REGISTER
)))
6465 #if 0 /* No longer needed for correct operation.
6466 It might give better code, or might not; worth an experiment? */
6467 /* If this is an optional reload, we can't inherit from earlier insns
6468 until we are sure that any non-optional reloads have been allocated.
6469 The following code takes advantage of the fact that optional reloads
6470 are at the end of reload_order. */
6471 if (rld
[r
].optional
!= 0)
6472 for (i
= 0; i
< j
; i
++)
6473 if ((rld
[reload_order
[i
]].out
!= 0
6474 || rld
[reload_order
[i
]].in
!= 0
6475 || rld
[reload_order
[i
]].secondary_p
)
6476 && ! rld
[reload_order
[i
]].optional
6477 && rld
[reload_order
[i
]].reg_rtx
== 0)
6478 allocate_reload_reg (chain
, reload_order
[i
], 0);
6481 /* First see if this pseudo is already available as reloaded
6482 for a previous insn. We cannot try to inherit for reloads
6483 that are smaller than the maximum number of registers needed
6484 for groups unless the register we would allocate cannot be used
6487 We could check here to see if this is a secondary reload for
6488 an object that is already in a register of the desired class.
6489 This would avoid the need for the secondary reload register.
6490 But this is complex because we can't easily determine what
6491 objects might want to be loaded via this reload. So let a
6492 register be allocated here. In `emit_reload_insns' we suppress
6493 one of the loads in the case described above. */
6499 enum machine_mode mode
= VOIDmode
;
6503 else if (REG_P (rld
[r
].in
))
6505 regno
= REGNO (rld
[r
].in
);
6506 mode
= GET_MODE (rld
[r
].in
);
6508 else if (REG_P (rld
[r
].in_reg
))
6510 regno
= REGNO (rld
[r
].in_reg
);
6511 mode
= GET_MODE (rld
[r
].in_reg
);
6513 else if (GET_CODE (rld
[r
].in_reg
) == SUBREG
6514 && REG_P (SUBREG_REG (rld
[r
].in_reg
)))
6516 regno
= REGNO (SUBREG_REG (rld
[r
].in_reg
));
6517 if (regno
< FIRST_PSEUDO_REGISTER
)
6518 regno
= subreg_regno (rld
[r
].in_reg
);
6520 byte
= SUBREG_BYTE (rld
[r
].in_reg
);
6521 mode
= GET_MODE (rld
[r
].in_reg
);
6524 else if (GET_RTX_CLASS (GET_CODE (rld
[r
].in_reg
)) == RTX_AUTOINC
6525 && REG_P (XEXP (rld
[r
].in_reg
, 0)))
6527 regno
= REGNO (XEXP (rld
[r
].in_reg
, 0));
6528 mode
= GET_MODE (XEXP (rld
[r
].in_reg
, 0));
6529 rld
[r
].out
= rld
[r
].in
;
6533 /* This won't work, since REGNO can be a pseudo reg number.
6534 Also, it takes much more hair to keep track of all the things
6535 that can invalidate an inherited reload of part of a pseudoreg. */
6536 else if (GET_CODE (rld
[r
].in
) == SUBREG
6537 && REG_P (SUBREG_REG (rld
[r
].in
)))
6538 regno
= subreg_regno (rld
[r
].in
);
6542 && reg_last_reload_reg
[regno
] != 0
6543 && (GET_MODE_SIZE (GET_MODE (reg_last_reload_reg
[regno
]))
6544 >= GET_MODE_SIZE (mode
) + byte
)
6545 #ifdef CANNOT_CHANGE_MODE_CLASS
6546 /* Verify that the register it's in can be used in
6548 && !REG_CANNOT_CHANGE_MODE_P (REGNO (reg_last_reload_reg
[regno
]),
6549 GET_MODE (reg_last_reload_reg
[regno
]),
6554 enum reg_class rclass
= rld
[r
].rclass
, last_class
;
6555 rtx last_reg
= reg_last_reload_reg
[regno
];
6557 i
= REGNO (last_reg
);
6558 i
+= subreg_regno_offset (i
, GET_MODE (last_reg
), byte
, mode
);
6559 last_class
= REGNO_REG_CLASS (i
);
6561 if (reg_reloaded_contents
[i
] == regno
6562 && TEST_HARD_REG_BIT (reg_reloaded_valid
, i
)
6563 && HARD_REGNO_MODE_OK (i
, rld
[r
].mode
)
6564 && (TEST_HARD_REG_BIT (reg_class_contents
[(int) rclass
], i
)
6565 /* Even if we can't use this register as a reload
6566 register, we might use it for reload_override_in,
6567 if copying it to the desired class is cheap
6569 || ((register_move_cost (mode
, last_class
, rclass
)
6570 < memory_move_cost (mode
, rclass
, true))
6571 && (secondary_reload_class (1, rclass
, mode
,
6574 #ifdef SECONDARY_MEMORY_NEEDED
6575 && ! SECONDARY_MEMORY_NEEDED (last_class
, rclass
,
6580 && (rld
[r
].nregs
== max_group_size
6581 || ! TEST_HARD_REG_BIT (reg_class_contents
[(int) group_class
],
6583 && free_for_value_p (i
, rld
[r
].mode
, rld
[r
].opnum
,
6584 rld
[r
].when_needed
, rld
[r
].in
,
6587 /* If a group is needed, verify that all the subsequent
6588 registers still have their values intact. */
6589 int nr
= hard_regno_nregs
[i
][rld
[r
].mode
];
6592 for (k
= 1; k
< nr
; k
++)
6593 if (reg_reloaded_contents
[i
+ k
] != regno
6594 || ! TEST_HARD_REG_BIT (reg_reloaded_valid
, i
+ k
))
6602 last_reg
= (GET_MODE (last_reg
) == mode
6603 ? last_reg
: gen_rtx_REG (mode
, i
));
6606 for (k
= 0; k
< nr
; k
++)
6607 bad_for_class
|= ! TEST_HARD_REG_BIT (reg_class_contents
[(int) rld
[r
].rclass
],
6610 /* We found a register that contains the
6611 value we need. If this register is the
6612 same as an `earlyclobber' operand of the
6613 current insn, just mark it as a place to
6614 reload from since we can't use it as the
6615 reload register itself. */
6617 for (i1
= 0; i1
< n_earlyclobbers
; i1
++)
6618 if (reg_overlap_mentioned_for_reload_p
6619 (reg_last_reload_reg
[regno
],
6620 reload_earlyclobbers
[i1
]))
6623 if (i1
!= n_earlyclobbers
6624 || ! (free_for_value_p (i
, rld
[r
].mode
,
6626 rld
[r
].when_needed
, rld
[r
].in
,
6628 /* Don't use it if we'd clobber a pseudo reg. */
6629 || (TEST_HARD_REG_BIT (reg_used_in_insn
, i
)
6631 && ! TEST_HARD_REG_BIT (reg_reloaded_dead
, i
))
6632 /* Don't clobber the frame pointer. */
6633 || (i
== HARD_FRAME_POINTER_REGNUM
6634 && frame_pointer_needed
6636 /* Don't really use the inherited spill reg
6637 if we need it wider than we've got it. */
6638 || (GET_MODE_SIZE (rld
[r
].mode
)
6639 > GET_MODE_SIZE (mode
))
6642 /* If find_reloads chose reload_out as reload
6643 register, stay with it - that leaves the
6644 inherited register for subsequent reloads. */
6645 || (rld
[r
].out
&& rld
[r
].reg_rtx
6646 && rtx_equal_p (rld
[r
].out
, rld
[r
].reg_rtx
)))
6648 if (! rld
[r
].optional
)
6650 reload_override_in
[r
] = last_reg
;
6651 reload_inheritance_insn
[r
]
6652 = reg_reloaded_insn
[i
];
6658 /* We can use this as a reload reg. */
6659 /* Mark the register as in use for this part of
6661 mark_reload_reg_in_use (i
,
6665 rld
[r
].reg_rtx
= last_reg
;
6666 reload_inherited
[r
] = 1;
6667 reload_inheritance_insn
[r
]
6668 = reg_reloaded_insn
[i
];
6669 reload_spill_index
[r
] = i
;
6670 for (k
= 0; k
< nr
; k
++)
6671 SET_HARD_REG_BIT (reload_reg_used_for_inherit
,
6679 /* Here's another way to see if the value is already lying around. */
6682 && ! reload_inherited
[r
]
6684 && (CONSTANT_P (rld
[r
].in
)
6685 || GET_CODE (rld
[r
].in
) == PLUS
6686 || REG_P (rld
[r
].in
)
6687 || MEM_P (rld
[r
].in
))
6688 && (rld
[r
].nregs
== max_group_size
6689 || ! reg_classes_intersect_p (rld
[r
].rclass
, group_class
)))
6690 search_equiv
= rld
[r
].in
;
6695 = find_equiv_reg (search_equiv
, insn
, rld
[r
].rclass
,
6696 -1, NULL
, 0, rld
[r
].mode
);
6702 regno
= REGNO (equiv
);
6705 /* This must be a SUBREG of a hard register.
6706 Make a new REG since this might be used in an
6707 address and not all machines support SUBREGs
6709 gcc_assert (GET_CODE (equiv
) == SUBREG
);
6710 regno
= subreg_regno (equiv
);
6711 equiv
= gen_rtx_REG (rld
[r
].mode
, regno
);
6712 /* If we choose EQUIV as the reload register, but the
6713 loop below decides to cancel the inheritance, we'll
6714 end up reloading EQUIV in rld[r].mode, not the mode
6715 it had originally. That isn't safe when EQUIV isn't
6716 available as a spill register since its value might
6717 still be live at this point. */
6718 for (i
= regno
; i
< regno
+ (int) rld
[r
].nregs
; i
++)
6719 if (TEST_HARD_REG_BIT (reload_reg_unavailable
, i
))
6724 /* If we found a spill reg, reject it unless it is free
6725 and of the desired class. */
6729 int bad_for_class
= 0;
6730 int max_regno
= regno
+ rld
[r
].nregs
;
6732 for (i
= regno
; i
< max_regno
; i
++)
6734 regs_used
|= TEST_HARD_REG_BIT (reload_reg_used_at_all
,
6736 bad_for_class
|= ! TEST_HARD_REG_BIT (reg_class_contents
[(int) rld
[r
].rclass
],
6741 && ! free_for_value_p (regno
, rld
[r
].mode
,
6742 rld
[r
].opnum
, rld
[r
].when_needed
,
6743 rld
[r
].in
, rld
[r
].out
, r
, 1))
6748 if (equiv
!= 0 && ! HARD_REGNO_MODE_OK (regno
, rld
[r
].mode
))
6751 /* We found a register that contains the value we need.
6752 If this register is the same as an `earlyclobber' operand
6753 of the current insn, just mark it as a place to reload from
6754 since we can't use it as the reload register itself. */
6757 for (i
= 0; i
< n_earlyclobbers
; i
++)
6758 if (reg_overlap_mentioned_for_reload_p (equiv
,
6759 reload_earlyclobbers
[i
]))
6761 if (! rld
[r
].optional
)
6762 reload_override_in
[r
] = equiv
;
6767 /* If the equiv register we have found is explicitly clobbered
6768 in the current insn, it depends on the reload type if we
6769 can use it, use it for reload_override_in, or not at all.
6770 In particular, we then can't use EQUIV for a
6771 RELOAD_FOR_OUTPUT_ADDRESS reload. */
6775 if (regno_clobbered_p (regno
, insn
, rld
[r
].mode
, 2))
6776 switch (rld
[r
].when_needed
)
6778 case RELOAD_FOR_OTHER_ADDRESS
:
6779 case RELOAD_FOR_INPADDR_ADDRESS
:
6780 case RELOAD_FOR_INPUT_ADDRESS
:
6781 case RELOAD_FOR_OPADDR_ADDR
:
6784 case RELOAD_FOR_INPUT
:
6785 case RELOAD_FOR_OPERAND_ADDRESS
:
6786 if (! rld
[r
].optional
)
6787 reload_override_in
[r
] = equiv
;
6793 else if (regno_clobbered_p (regno
, insn
, rld
[r
].mode
, 1))
6794 switch (rld
[r
].when_needed
)
6796 case RELOAD_FOR_OTHER_ADDRESS
:
6797 case RELOAD_FOR_INPADDR_ADDRESS
:
6798 case RELOAD_FOR_INPUT_ADDRESS
:
6799 case RELOAD_FOR_OPADDR_ADDR
:
6800 case RELOAD_FOR_OPERAND_ADDRESS
:
6801 case RELOAD_FOR_INPUT
:
6804 if (! rld
[r
].optional
)
6805 reload_override_in
[r
] = equiv
;
6813 /* If we found an equivalent reg, say no code need be generated
6814 to load it, and use it as our reload reg. */
6816 && (regno
!= HARD_FRAME_POINTER_REGNUM
6817 || !frame_pointer_needed
))
6819 int nr
= hard_regno_nregs
[regno
][rld
[r
].mode
];
6821 rld
[r
].reg_rtx
= equiv
;
6822 reload_spill_index
[r
] = regno
;
6823 reload_inherited
[r
] = 1;
6825 /* If reg_reloaded_valid is not set for this register,
6826 there might be a stale spill_reg_store lying around.
6827 We must clear it, since otherwise emit_reload_insns
6828 might delete the store. */
6829 if (! TEST_HARD_REG_BIT (reg_reloaded_valid
, regno
))
6830 spill_reg_store
[regno
] = NULL_RTX
;
6831 /* If any of the hard registers in EQUIV are spill
6832 registers, mark them as in use for this insn. */
6833 for (k
= 0; k
< nr
; k
++)
6835 i
= spill_reg_order
[regno
+ k
];
6838 mark_reload_reg_in_use (regno
, rld
[r
].opnum
,
6841 SET_HARD_REG_BIT (reload_reg_used_for_inherit
,
6848 /* If we found a register to use already, or if this is an optional
6849 reload, we are done. */
6850 if (rld
[r
].reg_rtx
!= 0 || rld
[r
].optional
!= 0)
6854 /* No longer needed for correct operation. Might or might
6855 not give better code on the average. Want to experiment? */
6857 /* See if there is a later reload that has a class different from our
6858 class that intersects our class or that requires less register
6859 than our reload. If so, we must allocate a register to this
6860 reload now, since that reload might inherit a previous reload
6861 and take the only available register in our class. Don't do this
6862 for optional reloads since they will force all previous reloads
6863 to be allocated. Also don't do this for reloads that have been
6866 for (i
= j
+ 1; i
< n_reloads
; i
++)
6868 int s
= reload_order
[i
];
6870 if ((rld
[s
].in
== 0 && rld
[s
].out
== 0
6871 && ! rld
[s
].secondary_p
)
6875 if ((rld
[s
].rclass
!= rld
[r
].rclass
6876 && reg_classes_intersect_p (rld
[r
].rclass
,
6878 || rld
[s
].nregs
< rld
[r
].nregs
)
6885 allocate_reload_reg (chain
, r
, j
== n_reloads
- 1);
6889 /* Now allocate reload registers for anything non-optional that
6890 didn't get one yet. */
6891 for (j
= 0; j
< n_reloads
; j
++)
6893 int r
= reload_order
[j
];
6895 /* Ignore reloads that got marked inoperative. */
6896 if (rld
[r
].out
== 0 && rld
[r
].in
== 0 && ! rld
[r
].secondary_p
)
6899 /* Skip reloads that already have a register allocated or are
6901 if (rld
[r
].reg_rtx
!= 0 || rld
[r
].optional
)
6904 if (! allocate_reload_reg (chain
, r
, j
== n_reloads
- 1))
6908 /* If that loop got all the way, we have won. */
6915 /* Loop around and try without any inheritance. */
6920 /* First undo everything done by the failed attempt
6921 to allocate with inheritance. */
6922 choose_reload_regs_init (chain
, save_reload_reg_rtx
);
6924 /* Some sanity tests to verify that the reloads found in the first
6925 pass are identical to the ones we have now. */
6926 gcc_assert (chain
->n_reloads
== n_reloads
);
6928 for (i
= 0; i
< n_reloads
; i
++)
6930 if (chain
->rld
[i
].regno
< 0 || chain
->rld
[i
].reg_rtx
!= 0)
6932 gcc_assert (chain
->rld
[i
].when_needed
== rld
[i
].when_needed
);
6933 for (j
= 0; j
< n_spills
; j
++)
6934 if (spill_regs
[j
] == chain
->rld
[i
].regno
)
6935 if (! set_reload_reg (j
, i
))
6936 failed_reload (chain
->insn
, i
);
6940 /* If we thought we could inherit a reload, because it seemed that
6941 nothing else wanted the same reload register earlier in the insn,
6942 verify that assumption, now that all reloads have been assigned.
6943 Likewise for reloads where reload_override_in has been set. */
6945 /* If doing expensive optimizations, do one preliminary pass that doesn't
6946 cancel any inheritance, but removes reloads that have been needed only
6947 for reloads that we know can be inherited. */
6948 for (pass
= flag_expensive_optimizations
; pass
>= 0; pass
--)
6950 for (j
= 0; j
< n_reloads
; j
++)
6952 int r
= reload_order
[j
];
6954 #ifdef SECONDARY_MEMORY_NEEDED
6957 if (reload_inherited
[r
] && rld
[r
].reg_rtx
)
6958 check_reg
= rld
[r
].reg_rtx
;
6959 else if (reload_override_in
[r
]
6960 && (REG_P (reload_override_in
[r
])
6961 || GET_CODE (reload_override_in
[r
]) == SUBREG
))
6962 check_reg
= reload_override_in
[r
];
6965 if (! free_for_value_p (true_regnum (check_reg
), rld
[r
].mode
,
6966 rld
[r
].opnum
, rld
[r
].when_needed
, rld
[r
].in
,
6967 (reload_inherited
[r
]
6968 ? rld
[r
].out
: const0_rtx
),
6973 reload_inherited
[r
] = 0;
6974 reload_override_in
[r
] = 0;
6976 /* If we can inherit a RELOAD_FOR_INPUT, or can use a
6977 reload_override_in, then we do not need its related
6978 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads;
6979 likewise for other reload types.
6980 We handle this by removing a reload when its only replacement
6981 is mentioned in reload_in of the reload we are going to inherit.
6982 A special case are auto_inc expressions; even if the input is
6983 inherited, we still need the address for the output. We can
6984 recognize them because they have RELOAD_OUT set to RELOAD_IN.
6985 If we succeeded removing some reload and we are doing a preliminary
6986 pass just to remove such reloads, make another pass, since the
6987 removal of one reload might allow us to inherit another one. */
6989 && rld
[r
].out
!= rld
[r
].in
6990 && remove_address_replacements (rld
[r
].in
))
6995 #ifdef SECONDARY_MEMORY_NEEDED
6996 /* If we needed a memory location for the reload, we also have to
6997 remove its related reloads. */
6999 && rld
[r
].out
!= rld
[r
].in
7000 && (tem
= replaced_subreg (rld
[r
].in
), REG_P (tem
))
7001 && REGNO (tem
) < FIRST_PSEUDO_REGISTER
7002 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (REGNO (tem
)),
7003 rld
[r
].rclass
, rld
[r
].inmode
)
7004 && remove_address_replacements
7005 (get_secondary_mem (tem
, rld
[r
].inmode
, rld
[r
].opnum
,
7006 rld
[r
].when_needed
)))
7015 /* Now that reload_override_in is known valid,
7016 actually override reload_in. */
7017 for (j
= 0; j
< n_reloads
; j
++)
7018 if (reload_override_in
[j
])
7019 rld
[j
].in
= reload_override_in
[j
];
7021 /* If this reload won't be done because it has been canceled or is
7022 optional and not inherited, clear reload_reg_rtx so other
7023 routines (such as subst_reloads) don't get confused. */
7024 for (j
= 0; j
< n_reloads
; j
++)
7025 if (rld
[j
].reg_rtx
!= 0
7026 && ((rld
[j
].optional
&& ! reload_inherited
[j
])
7027 || (rld
[j
].in
== 0 && rld
[j
].out
== 0
7028 && ! rld
[j
].secondary_p
)))
7030 int regno
= true_regnum (rld
[j
].reg_rtx
);
7032 if (spill_reg_order
[regno
] >= 0)
7033 clear_reload_reg_in_use (regno
, rld
[j
].opnum
,
7034 rld
[j
].when_needed
, rld
[j
].mode
);
7036 reload_spill_index
[j
] = -1;
7039 /* Record which pseudos and which spill regs have output reloads. */
7040 for (j
= 0; j
< n_reloads
; j
++)
7042 int r
= reload_order
[j
];
7044 i
= reload_spill_index
[r
];
7046 /* I is nonneg if this reload uses a register.
7047 If rld[r].reg_rtx is 0, this is an optional reload
7048 that we opted to ignore. */
7049 if (rld
[r
].out_reg
!= 0 && REG_P (rld
[r
].out_reg
)
7050 && rld
[r
].reg_rtx
!= 0)
7052 int nregno
= REGNO (rld
[r
].out_reg
);
7055 if (nregno
< FIRST_PSEUDO_REGISTER
)
7056 nr
= hard_regno_nregs
[nregno
][rld
[r
].mode
];
7059 SET_REGNO_REG_SET (®_has_output_reload
,
7063 add_to_hard_reg_set (®_is_output_reload
, rld
[r
].mode
, i
);
7065 gcc_assert (rld
[r
].when_needed
== RELOAD_OTHER
7066 || rld
[r
].when_needed
== RELOAD_FOR_OUTPUT
7067 || rld
[r
].when_needed
== RELOAD_FOR_INSN
);
7072 /* Deallocate the reload register for reload R. This is called from
7073 remove_address_replacements. */
7076 deallocate_reload_reg (int r
)
7080 if (! rld
[r
].reg_rtx
)
7082 regno
= true_regnum (rld
[r
].reg_rtx
);
7084 if (spill_reg_order
[regno
] >= 0)
7085 clear_reload_reg_in_use (regno
, rld
[r
].opnum
, rld
[r
].when_needed
,
7087 reload_spill_index
[r
] = -1;
7090 /* These arrays are filled by emit_reload_insns and its subroutines. */
7091 static rtx input_reload_insns
[MAX_RECOG_OPERANDS
];
7092 static rtx other_input_address_reload_insns
= 0;
7093 static rtx other_input_reload_insns
= 0;
7094 static rtx input_address_reload_insns
[MAX_RECOG_OPERANDS
];
7095 static rtx inpaddr_address_reload_insns
[MAX_RECOG_OPERANDS
];
7096 static rtx output_reload_insns
[MAX_RECOG_OPERANDS
];
7097 static rtx output_address_reload_insns
[MAX_RECOG_OPERANDS
];
7098 static rtx outaddr_address_reload_insns
[MAX_RECOG_OPERANDS
];
7099 static rtx operand_reload_insns
= 0;
7100 static rtx other_operand_reload_insns
= 0;
7101 static rtx other_output_reload_insns
[MAX_RECOG_OPERANDS
];
7103 /* Values to be put in spill_reg_store are put here first. Instructions
7104 must only be placed here if the associated reload register reaches
7105 the end of the instruction's reload sequence. */
7106 static rtx new_spill_reg_store
[FIRST_PSEUDO_REGISTER
];
7107 static HARD_REG_SET reg_reloaded_died
;
7109 /* Check if *RELOAD_REG is suitable as an intermediate or scratch register
7110 of class NEW_CLASS with mode NEW_MODE. Or alternatively, if alt_reload_reg
7111 is nonzero, if that is suitable. On success, change *RELOAD_REG to the
7112 adjusted register, and return true. Otherwise, return false. */
7114 reload_adjust_reg_for_temp (rtx
*reload_reg
, rtx alt_reload_reg
,
7115 enum reg_class new_class
,
7116 enum machine_mode new_mode
)
7121 for (reg
= *reload_reg
; reg
; reg
= alt_reload_reg
, alt_reload_reg
= 0)
7123 unsigned regno
= REGNO (reg
);
7125 if (!TEST_HARD_REG_BIT (reg_class_contents
[(int) new_class
], regno
))
7127 if (GET_MODE (reg
) != new_mode
)
7129 if (!HARD_REGNO_MODE_OK (regno
, new_mode
))
7131 if (hard_regno_nregs
[regno
][new_mode
]
7132 > hard_regno_nregs
[regno
][GET_MODE (reg
)])
7134 reg
= reload_adjust_reg_for_mode (reg
, new_mode
);
7142 /* Check if *RELOAD_REG is suitable as a scratch register for the reload
7143 pattern with insn_code ICODE, or alternatively, if alt_reload_reg is
7144 nonzero, if that is suitable. On success, change *RELOAD_REG to the
7145 adjusted register, and return true. Otherwise, return false. */
7147 reload_adjust_reg_for_icode (rtx
*reload_reg
, rtx alt_reload_reg
,
7148 enum insn_code icode
)
7151 enum reg_class new_class
= scratch_reload_class (icode
);
7152 enum machine_mode new_mode
= insn_data
[(int) icode
].operand
[2].mode
;
7154 return reload_adjust_reg_for_temp (reload_reg
, alt_reload_reg
,
7155 new_class
, new_mode
);
7158 /* Generate insns to perform reload RL, which is for the insn in CHAIN and
7159 has the number J. OLD contains the value to be used as input. */
7162 emit_input_reload_insns (struct insn_chain
*chain
, struct reload
*rl
,
7165 rtx insn
= chain
->insn
;
7167 rtx oldequiv_reg
= 0;
7170 enum machine_mode mode
;
7173 /* delete_output_reload is only invoked properly if old contains
7174 the original pseudo register. Since this is replaced with a
7175 hard reg when RELOAD_OVERRIDE_IN is set, see if we can
7176 find the pseudo in RELOAD_IN_REG. */
7177 if (reload_override_in
[j
]
7178 && REG_P (rl
->in_reg
))
7185 else if (REG_P (oldequiv
))
7186 oldequiv_reg
= oldequiv
;
7187 else if (GET_CODE (oldequiv
) == SUBREG
)
7188 oldequiv_reg
= SUBREG_REG (oldequiv
);
7190 reloadreg
= reload_reg_rtx_for_input
[j
];
7191 mode
= GET_MODE (reloadreg
);
7193 /* If we are reloading from a register that was recently stored in
7194 with an output-reload, see if we can prove there was
7195 actually no need to store the old value in it. */
7197 if (optimize
&& REG_P (oldequiv
)
7198 && REGNO (oldequiv
) < FIRST_PSEUDO_REGISTER
7199 && spill_reg_store
[REGNO (oldequiv
)]
7201 && (dead_or_set_p (insn
, spill_reg_stored_to
[REGNO (oldequiv
)])
7202 || rtx_equal_p (spill_reg_stored_to
[REGNO (oldequiv
)],
7204 delete_output_reload (insn
, j
, REGNO (oldequiv
), reloadreg
);
7206 /* Encapsulate OLDEQUIV into the reload mode, then load RELOADREG from
7209 while (GET_CODE (oldequiv
) == SUBREG
&& GET_MODE (oldequiv
) != mode
)
7210 oldequiv
= SUBREG_REG (oldequiv
);
7211 if (GET_MODE (oldequiv
) != VOIDmode
7212 && mode
!= GET_MODE (oldequiv
))
7213 oldequiv
= gen_lowpart_SUBREG (mode
, oldequiv
);
7215 /* Switch to the right place to emit the reload insns. */
7216 switch (rl
->when_needed
)
7219 where
= &other_input_reload_insns
;
7221 case RELOAD_FOR_INPUT
:
7222 where
= &input_reload_insns
[rl
->opnum
];
7224 case RELOAD_FOR_INPUT_ADDRESS
:
7225 where
= &input_address_reload_insns
[rl
->opnum
];
7227 case RELOAD_FOR_INPADDR_ADDRESS
:
7228 where
= &inpaddr_address_reload_insns
[rl
->opnum
];
7230 case RELOAD_FOR_OUTPUT_ADDRESS
:
7231 where
= &output_address_reload_insns
[rl
->opnum
];
7233 case RELOAD_FOR_OUTADDR_ADDRESS
:
7234 where
= &outaddr_address_reload_insns
[rl
->opnum
];
7236 case RELOAD_FOR_OPERAND_ADDRESS
:
7237 where
= &operand_reload_insns
;
7239 case RELOAD_FOR_OPADDR_ADDR
:
7240 where
= &other_operand_reload_insns
;
7242 case RELOAD_FOR_OTHER_ADDRESS
:
7243 where
= &other_input_address_reload_insns
;
7249 push_to_sequence (*where
);
7251 /* Auto-increment addresses must be reloaded in a special way. */
7252 if (rl
->out
&& ! rl
->out_reg
)
7254 /* We are not going to bother supporting the case where a
7255 incremented register can't be copied directly from
7256 OLDEQUIV since this seems highly unlikely. */
7257 gcc_assert (rl
->secondary_in_reload
< 0);
7259 if (reload_inherited
[j
])
7260 oldequiv
= reloadreg
;
7262 old
= XEXP (rl
->in_reg
, 0);
7264 /* Prevent normal processing of this reload. */
7266 /* Output a special code sequence for this case. */
7267 inc_for_reload (reloadreg
, oldequiv
, rl
->out
, rl
->inc
);
7270 /* If we are reloading a pseudo-register that was set by the previous
7271 insn, see if we can get rid of that pseudo-register entirely
7272 by redirecting the previous insn into our reload register. */
7274 else if (optimize
&& REG_P (old
)
7275 && REGNO (old
) >= FIRST_PSEUDO_REGISTER
7276 && dead_or_set_p (insn
, old
)
7277 /* This is unsafe if some other reload
7278 uses the same reg first. */
7279 && ! conflicts_with_override (reloadreg
)
7280 && free_for_value_p (REGNO (reloadreg
), rl
->mode
, rl
->opnum
,
7281 rl
->when_needed
, old
, rl
->out
, j
, 0))
7283 rtx temp
= PREV_INSN (insn
);
7284 while (temp
&& (NOTE_P (temp
) || DEBUG_INSN_P (temp
)))
7285 temp
= PREV_INSN (temp
);
7287 && NONJUMP_INSN_P (temp
)
7288 && GET_CODE (PATTERN (temp
)) == SET
7289 && SET_DEST (PATTERN (temp
)) == old
7290 /* Make sure we can access insn_operand_constraint. */
7291 && asm_noperands (PATTERN (temp
)) < 0
7292 /* This is unsafe if operand occurs more than once in current
7293 insn. Perhaps some occurrences aren't reloaded. */
7294 && count_occurrences (PATTERN (insn
), old
, 0) == 1)
7296 rtx old
= SET_DEST (PATTERN (temp
));
7297 /* Store into the reload register instead of the pseudo. */
7298 SET_DEST (PATTERN (temp
)) = reloadreg
;
7300 /* Verify that resulting insn is valid. */
7301 extract_insn (temp
);
7302 if (constrain_operands (1))
7304 /* If the previous insn is an output reload, the source is
7305 a reload register, and its spill_reg_store entry will
7306 contain the previous destination. This is now
7308 if (REG_P (SET_SRC (PATTERN (temp
)))
7309 && REGNO (SET_SRC (PATTERN (temp
))) < FIRST_PSEUDO_REGISTER
)
7311 spill_reg_store
[REGNO (SET_SRC (PATTERN (temp
)))] = 0;
7312 spill_reg_stored_to
[REGNO (SET_SRC (PATTERN (temp
)))] = 0;
7315 /* If these are the only uses of the pseudo reg,
7316 pretend for GDB it lives in the reload reg we used. */
7317 if (REG_N_DEATHS (REGNO (old
)) == 1
7318 && REG_N_SETS (REGNO (old
)) == 1)
7320 reg_renumber
[REGNO (old
)] = REGNO (reloadreg
);
7321 if (ira_conflicts_p
)
7322 /* Inform IRA about the change. */
7323 ira_mark_allocation_change (REGNO (old
));
7324 alter_reg (REGNO (old
), -1, false);
7328 /* Adjust any debug insns between temp and insn. */
7329 while ((temp
= NEXT_INSN (temp
)) != insn
)
7330 if (DEBUG_INSN_P (temp
))
7331 replace_rtx (PATTERN (temp
), old
, reloadreg
);
7333 gcc_assert (NOTE_P (temp
));
7337 SET_DEST (PATTERN (temp
)) = old
;
7342 /* We can't do that, so output an insn to load RELOADREG. */
7344 /* If we have a secondary reload, pick up the secondary register
7345 and icode, if any. If OLDEQUIV and OLD are different or
7346 if this is an in-out reload, recompute whether or not we
7347 still need a secondary register and what the icode should
7348 be. If we still need a secondary register and the class or
7349 icode is different, go back to reloading from OLD if using
7350 OLDEQUIV means that we got the wrong type of register. We
7351 cannot have different class or icode due to an in-out reload
7352 because we don't make such reloads when both the input and
7353 output need secondary reload registers. */
7355 if (! special
&& rl
->secondary_in_reload
>= 0)
7357 rtx second_reload_reg
= 0;
7358 rtx third_reload_reg
= 0;
7359 int secondary_reload
= rl
->secondary_in_reload
;
7360 rtx real_oldequiv
= oldequiv
;
7363 enum insn_code icode
;
7364 enum insn_code tertiary_icode
= CODE_FOR_nothing
;
7366 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
7367 and similarly for OLD.
7368 See comments in get_secondary_reload in reload.c. */
7369 /* If it is a pseudo that cannot be replaced with its
7370 equivalent MEM, we must fall back to reload_in, which
7371 will have all the necessary substitutions registered.
7372 Likewise for a pseudo that can't be replaced with its
7373 equivalent constant.
7375 Take extra care for subregs of such pseudos. Note that
7376 we cannot use reg_equiv_mem in this case because it is
7377 not in the right mode. */
7380 if (GET_CODE (tmp
) == SUBREG
)
7381 tmp
= SUBREG_REG (tmp
);
7383 && REGNO (tmp
) >= FIRST_PSEUDO_REGISTER
7384 && (reg_equiv_memory_loc (REGNO (tmp
)) != 0
7385 || reg_equiv_constant (REGNO (tmp
)) != 0))
7387 if (! reg_equiv_mem (REGNO (tmp
))
7388 || num_not_at_initial_offset
7389 || GET_CODE (oldequiv
) == SUBREG
)
7390 real_oldequiv
= rl
->in
;
7392 real_oldequiv
= reg_equiv_mem (REGNO (tmp
));
7396 if (GET_CODE (tmp
) == SUBREG
)
7397 tmp
= SUBREG_REG (tmp
);
7399 && REGNO (tmp
) >= FIRST_PSEUDO_REGISTER
7400 && (reg_equiv_memory_loc (REGNO (tmp
)) != 0
7401 || reg_equiv_constant (REGNO (tmp
)) != 0))
7403 if (! reg_equiv_mem (REGNO (tmp
))
7404 || num_not_at_initial_offset
7405 || GET_CODE (old
) == SUBREG
)
7408 real_old
= reg_equiv_mem (REGNO (tmp
));
7411 second_reload_reg
= rld
[secondary_reload
].reg_rtx
;
7412 if (rld
[secondary_reload
].secondary_in_reload
>= 0)
7414 int tertiary_reload
= rld
[secondary_reload
].secondary_in_reload
;
7416 third_reload_reg
= rld
[tertiary_reload
].reg_rtx
;
7417 tertiary_icode
= rld
[secondary_reload
].secondary_in_icode
;
7418 /* We'd have to add more code for quartary reloads. */
7419 gcc_assert (rld
[tertiary_reload
].secondary_in_reload
< 0);
7421 icode
= rl
->secondary_in_icode
;
7423 if ((old
!= oldequiv
&& ! rtx_equal_p (old
, oldequiv
))
7424 || (rl
->in
!= 0 && rl
->out
!= 0))
7426 secondary_reload_info sri
, sri2
;
7427 enum reg_class new_class
, new_t_class
;
7429 sri
.icode
= CODE_FOR_nothing
;
7430 sri
.prev_sri
= NULL
;
7432 = (enum reg_class
) targetm
.secondary_reload (1, real_oldequiv
,
7436 if (new_class
== NO_REGS
&& sri
.icode
== CODE_FOR_nothing
)
7437 second_reload_reg
= 0;
7438 else if (new_class
== NO_REGS
)
7440 if (reload_adjust_reg_for_icode (&second_reload_reg
,
7442 (enum insn_code
) sri
.icode
))
7444 icode
= (enum insn_code
) sri
.icode
;
7445 third_reload_reg
= 0;
7450 real_oldequiv
= real_old
;
7453 else if (sri
.icode
!= CODE_FOR_nothing
)
7454 /* We currently lack a way to express this in reloads. */
7458 sri2
.icode
= CODE_FOR_nothing
;
7459 sri2
.prev_sri
= &sri
;
7461 = (enum reg_class
) targetm
.secondary_reload (1, real_oldequiv
,
7464 if (new_t_class
== NO_REGS
&& sri2
.icode
== CODE_FOR_nothing
)
7466 if (reload_adjust_reg_for_temp (&second_reload_reg
,
7470 third_reload_reg
= 0;
7471 tertiary_icode
= (enum insn_code
) sri2
.icode
;
7476 real_oldequiv
= real_old
;
7479 else if (new_t_class
== NO_REGS
&& sri2
.icode
!= CODE_FOR_nothing
)
7481 rtx intermediate
= second_reload_reg
;
7483 if (reload_adjust_reg_for_temp (&intermediate
, NULL
,
7485 && reload_adjust_reg_for_icode (&third_reload_reg
, NULL
,
7489 second_reload_reg
= intermediate
;
7490 tertiary_icode
= (enum insn_code
) sri2
.icode
;
7495 real_oldequiv
= real_old
;
7498 else if (new_t_class
!= NO_REGS
&& sri2
.icode
== CODE_FOR_nothing
)
7500 rtx intermediate
= second_reload_reg
;
7502 if (reload_adjust_reg_for_temp (&intermediate
, NULL
,
7504 && reload_adjust_reg_for_temp (&third_reload_reg
, NULL
,
7507 second_reload_reg
= intermediate
;
7508 tertiary_icode
= (enum insn_code
) sri2
.icode
;
7513 real_oldequiv
= real_old
;
7518 /* This could be handled more intelligently too. */
7520 real_oldequiv
= real_old
;
7525 /* If we still need a secondary reload register, check
7526 to see if it is being used as a scratch or intermediate
7527 register and generate code appropriately. If we need
7528 a scratch register, use REAL_OLDEQUIV since the form of
7529 the insn may depend on the actual address if it is
7532 if (second_reload_reg
)
7534 if (icode
!= CODE_FOR_nothing
)
7536 /* We'd have to add extra code to handle this case. */
7537 gcc_assert (!third_reload_reg
);
7539 emit_insn (GEN_FCN (icode
) (reloadreg
, real_oldequiv
,
7540 second_reload_reg
));
7545 /* See if we need a scratch register to load the
7546 intermediate register (a tertiary reload). */
7547 if (tertiary_icode
!= CODE_FOR_nothing
)
7549 emit_insn ((GEN_FCN (tertiary_icode
)
7550 (second_reload_reg
, real_oldequiv
,
7551 third_reload_reg
)));
7553 else if (third_reload_reg
)
7555 gen_reload (third_reload_reg
, real_oldequiv
,
7558 gen_reload (second_reload_reg
, third_reload_reg
,
7563 gen_reload (second_reload_reg
, real_oldequiv
,
7567 oldequiv
= second_reload_reg
;
7572 if (! special
&& ! rtx_equal_p (reloadreg
, oldequiv
))
7574 rtx real_oldequiv
= oldequiv
;
7576 if ((REG_P (oldequiv
)
7577 && REGNO (oldequiv
) >= FIRST_PSEUDO_REGISTER
7578 && (reg_equiv_memory_loc (REGNO (oldequiv
)) != 0
7579 || reg_equiv_constant (REGNO (oldequiv
)) != 0))
7580 || (GET_CODE (oldequiv
) == SUBREG
7581 && REG_P (SUBREG_REG (oldequiv
))
7582 && (REGNO (SUBREG_REG (oldequiv
))
7583 >= FIRST_PSEUDO_REGISTER
)
7584 && ((reg_equiv_memory_loc (REGNO (SUBREG_REG (oldequiv
))) != 0)
7585 || (reg_equiv_constant (REGNO (SUBREG_REG (oldequiv
))) != 0)))
7586 || (CONSTANT_P (oldequiv
)
7587 && (targetm
.preferred_reload_class (oldequiv
,
7588 REGNO_REG_CLASS (REGNO (reloadreg
)))
7590 real_oldequiv
= rl
->in
;
7591 gen_reload (reloadreg
, real_oldequiv
, rl
->opnum
,
7595 if (cfun
->can_throw_non_call_exceptions
)
7596 copy_reg_eh_region_note_forward (insn
, get_insns (), NULL
);
7598 /* End this sequence. */
7599 *where
= get_insns ();
7602 /* Update reload_override_in so that delete_address_reloads_1
7603 can see the actual register usage. */
7605 reload_override_in
[j
] = oldequiv
;
7608 /* Generate insns to for the output reload RL, which is for the insn described
7609 by CHAIN and has the number J. */
7611 emit_output_reload_insns (struct insn_chain
*chain
, struct reload
*rl
,
7615 rtx insn
= chain
->insn
;
7618 enum machine_mode mode
;
7622 if (rl
->when_needed
== RELOAD_OTHER
)
7625 push_to_sequence (output_reload_insns
[rl
->opnum
]);
7627 rl_reg_rtx
= reload_reg_rtx_for_output
[j
];
7628 mode
= GET_MODE (rl_reg_rtx
);
7630 reloadreg
= rl_reg_rtx
;
7632 /* If we need two reload regs, set RELOADREG to the intermediate
7633 one, since it will be stored into OLD. We might need a secondary
7634 register only for an input reload, so check again here. */
7636 if (rl
->secondary_out_reload
>= 0)
7639 int secondary_reload
= rl
->secondary_out_reload
;
7640 int tertiary_reload
= rld
[secondary_reload
].secondary_out_reload
;
7642 if (REG_P (old
) && REGNO (old
) >= FIRST_PSEUDO_REGISTER
7643 && reg_equiv_mem (REGNO (old
)) != 0)
7644 real_old
= reg_equiv_mem (REGNO (old
));
7646 if (secondary_reload_class (0, rl
->rclass
, mode
, real_old
) != NO_REGS
)
7648 rtx second_reloadreg
= reloadreg
;
7649 reloadreg
= rld
[secondary_reload
].reg_rtx
;
7651 /* See if RELOADREG is to be used as a scratch register
7652 or as an intermediate register. */
7653 if (rl
->secondary_out_icode
!= CODE_FOR_nothing
)
7655 /* We'd have to add extra code to handle this case. */
7656 gcc_assert (tertiary_reload
< 0);
7658 emit_insn ((GEN_FCN (rl
->secondary_out_icode
)
7659 (real_old
, second_reloadreg
, reloadreg
)));
7664 /* See if we need both a scratch and intermediate reload
7667 enum insn_code tertiary_icode
7668 = rld
[secondary_reload
].secondary_out_icode
;
7670 /* We'd have to add more code for quartary reloads. */
7671 gcc_assert (tertiary_reload
< 0
7672 || rld
[tertiary_reload
].secondary_out_reload
< 0);
7674 if (GET_MODE (reloadreg
) != mode
)
7675 reloadreg
= reload_adjust_reg_for_mode (reloadreg
, mode
);
7677 if (tertiary_icode
!= CODE_FOR_nothing
)
7679 rtx third_reloadreg
= rld
[tertiary_reload
].reg_rtx
;
7681 /* Copy primary reload reg to secondary reload reg.
7682 (Note that these have been swapped above, then
7683 secondary reload reg to OLD using our insn.) */
7685 /* If REAL_OLD is a paradoxical SUBREG, remove it
7686 and try to put the opposite SUBREG on
7688 strip_paradoxical_subreg (&real_old
, &reloadreg
);
7690 gen_reload (reloadreg
, second_reloadreg
,
7691 rl
->opnum
, rl
->when_needed
);
7692 emit_insn ((GEN_FCN (tertiary_icode
)
7693 (real_old
, reloadreg
, third_reloadreg
)));
7699 /* Copy between the reload regs here and then to
7702 gen_reload (reloadreg
, second_reloadreg
,
7703 rl
->opnum
, rl
->when_needed
);
7704 if (tertiary_reload
>= 0)
7706 rtx third_reloadreg
= rld
[tertiary_reload
].reg_rtx
;
7708 gen_reload (third_reloadreg
, reloadreg
,
7709 rl
->opnum
, rl
->when_needed
);
7710 reloadreg
= third_reloadreg
;
7717 /* Output the last reload insn. */
7722 /* Don't output the last reload if OLD is not the dest of
7723 INSN and is in the src and is clobbered by INSN. */
7724 if (! flag_expensive_optimizations
7726 || !(set
= single_set (insn
))
7727 || rtx_equal_p (old
, SET_DEST (set
))
7728 || !reg_mentioned_p (old
, SET_SRC (set
))
7729 || !((REGNO (old
) < FIRST_PSEUDO_REGISTER
)
7730 && regno_clobbered_p (REGNO (old
), insn
, rl
->mode
, 0)))
7731 gen_reload (old
, reloadreg
, rl
->opnum
,
7735 /* Look at all insns we emitted, just to be safe. */
7736 for (p
= get_insns (); p
; p
= NEXT_INSN (p
))
7739 rtx pat
= PATTERN (p
);
7741 /* If this output reload doesn't come from a spill reg,
7742 clear any memory of reloaded copies of the pseudo reg.
7743 If this output reload comes from a spill reg,
7744 reg_has_output_reload will make this do nothing. */
7745 note_stores (pat
, forget_old_reloads_1
, NULL
);
7747 if (reg_mentioned_p (rl_reg_rtx
, pat
))
7749 rtx set
= single_set (insn
);
7750 if (reload_spill_index
[j
] < 0
7752 && SET_SRC (set
) == rl_reg_rtx
)
7754 int src
= REGNO (SET_SRC (set
));
7756 reload_spill_index
[j
] = src
;
7757 SET_HARD_REG_BIT (reg_is_output_reload
, src
);
7758 if (find_regno_note (insn
, REG_DEAD
, src
))
7759 SET_HARD_REG_BIT (reg_reloaded_died
, src
);
7761 if (HARD_REGISTER_P (rl_reg_rtx
))
7763 int s
= rl
->secondary_out_reload
;
7764 set
= single_set (p
);
7765 /* If this reload copies only to the secondary reload
7766 register, the secondary reload does the actual
7768 if (s
>= 0 && set
== NULL_RTX
)
7769 /* We can't tell what function the secondary reload
7770 has and where the actual store to the pseudo is
7771 made; leave new_spill_reg_store alone. */
7774 && SET_SRC (set
) == rl_reg_rtx
7775 && SET_DEST (set
) == rld
[s
].reg_rtx
)
7777 /* Usually the next instruction will be the
7778 secondary reload insn; if we can confirm
7779 that it is, setting new_spill_reg_store to
7780 that insn will allow an extra optimization. */
7781 rtx s_reg
= rld
[s
].reg_rtx
;
7782 rtx next
= NEXT_INSN (p
);
7783 rld
[s
].out
= rl
->out
;
7784 rld
[s
].out_reg
= rl
->out_reg
;
7785 set
= single_set (next
);
7786 if (set
&& SET_SRC (set
) == s_reg
7787 && reload_reg_rtx_reaches_end_p (s_reg
, s
))
7789 SET_HARD_REG_BIT (reg_is_output_reload
,
7791 new_spill_reg_store
[REGNO (s_reg
)] = next
;
7794 else if (reload_reg_rtx_reaches_end_p (rl_reg_rtx
, j
))
7795 new_spill_reg_store
[REGNO (rl_reg_rtx
)] = p
;
7800 if (rl
->when_needed
== RELOAD_OTHER
)
7802 emit_insn (other_output_reload_insns
[rl
->opnum
]);
7803 other_output_reload_insns
[rl
->opnum
] = get_insns ();
7806 output_reload_insns
[rl
->opnum
] = get_insns ();
7808 if (cfun
->can_throw_non_call_exceptions
)
7809 copy_reg_eh_region_note_forward (insn
, get_insns (), NULL
);
7814 /* Do input reloading for reload RL, which is for the insn described by CHAIN
7815 and has the number J. */
7817 do_input_reload (struct insn_chain
*chain
, struct reload
*rl
, int j
)
7819 rtx insn
= chain
->insn
;
7820 rtx old
= (rl
->in
&& MEM_P (rl
->in
)
7821 ? rl
->in_reg
: rl
->in
);
7822 rtx reg_rtx
= rl
->reg_rtx
;
7826 enum machine_mode mode
;
7828 /* Determine the mode to reload in.
7829 This is very tricky because we have three to choose from.
7830 There is the mode the insn operand wants (rl->inmode).
7831 There is the mode of the reload register RELOADREG.
7832 There is the intrinsic mode of the operand, which we could find
7833 by stripping some SUBREGs.
7834 It turns out that RELOADREG's mode is irrelevant:
7835 we can change that arbitrarily.
7837 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
7838 then the reload reg may not support QImode moves, so use SImode.
7839 If foo is in memory due to spilling a pseudo reg, this is safe,
7840 because the QImode value is in the least significant part of a
7841 slot big enough for a SImode. If foo is some other sort of
7842 memory reference, then it is impossible to reload this case,
7843 so previous passes had better make sure this never happens.
7845 Then consider a one-word union which has SImode and one of its
7846 members is a float, being fetched as (SUBREG:SF union:SI).
7847 We must fetch that as SFmode because we could be loading into
7848 a float-only register. In this case OLD's mode is correct.
7850 Consider an immediate integer: it has VOIDmode. Here we need
7851 to get a mode from something else.
7853 In some cases, there is a fourth mode, the operand's
7854 containing mode. If the insn specifies a containing mode for
7855 this operand, it overrides all others.
7857 I am not sure whether the algorithm here is always right,
7858 but it does the right things in those cases. */
7860 mode
= GET_MODE (old
);
7861 if (mode
== VOIDmode
)
7864 /* We cannot use gen_lowpart_common since it can do the wrong thing
7865 when REG_RTX has a multi-word mode. Note that REG_RTX must
7866 always be a REG here. */
7867 if (GET_MODE (reg_rtx
) != mode
)
7868 reg_rtx
= reload_adjust_reg_for_mode (reg_rtx
, mode
);
7870 reload_reg_rtx_for_input
[j
] = reg_rtx
;
7873 /* AUTO_INC reloads need to be handled even if inherited. We got an
7874 AUTO_INC reload if reload_out is set but reload_out_reg isn't. */
7875 && (! reload_inherited
[j
] || (rl
->out
&& ! rl
->out_reg
))
7876 && ! rtx_equal_p (reg_rtx
, old
)
7878 emit_input_reload_insns (chain
, rld
+ j
, old
, j
);
7880 /* When inheriting a wider reload, we have a MEM in rl->in,
7881 e.g. inheriting a SImode output reload for
7882 (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */
7883 if (optimize
&& reload_inherited
[j
] && rl
->in
7885 && MEM_P (rl
->in_reg
)
7886 && reload_spill_index
[j
] >= 0
7887 && TEST_HARD_REG_BIT (reg_reloaded_valid
, reload_spill_index
[j
]))
7888 rl
->in
= regno_reg_rtx
[reg_reloaded_contents
[reload_spill_index
[j
]]];
7890 /* If we are reloading a register that was recently stored in with an
7891 output-reload, see if we can prove there was
7892 actually no need to store the old value in it. */
7895 && (reload_inherited
[j
] || reload_override_in
[j
])
7898 && spill_reg_store
[REGNO (reg_rtx
)] != 0
7900 /* There doesn't seem to be any reason to restrict this to pseudos
7901 and doing so loses in the case where we are copying from a
7902 register of the wrong class. */
7903 && !HARD_REGISTER_P (spill_reg_stored_to
[REGNO (reg_rtx
)])
7905 /* The insn might have already some references to stackslots
7906 replaced by MEMs, while reload_out_reg still names the
7908 && (dead_or_set_p (insn
, spill_reg_stored_to
[REGNO (reg_rtx
)])
7909 || rtx_equal_p (spill_reg_stored_to
[REGNO (reg_rtx
)], rl
->out_reg
)))
7910 delete_output_reload (insn
, j
, REGNO (reg_rtx
), reg_rtx
);
7913 /* Do output reloading for reload RL, which is for the insn described by
7914 CHAIN and has the number J.
7915 ??? At some point we need to support handling output reloads of
7916 JUMP_INSNs or insns that set cc0. */
7918 do_output_reload (struct insn_chain
*chain
, struct reload
*rl
, int j
)
7921 rtx insn
= chain
->insn
;
7922 /* If this is an output reload that stores something that is
7923 not loaded in this same reload, see if we can eliminate a previous
7925 rtx pseudo
= rl
->out_reg
;
7926 rtx reg_rtx
= rl
->reg_rtx
;
7928 if (rl
->out
&& reg_rtx
)
7930 enum machine_mode mode
;
7932 /* Determine the mode to reload in.
7933 See comments above (for input reloading). */
7934 mode
= GET_MODE (rl
->out
);
7935 if (mode
== VOIDmode
)
7937 /* VOIDmode should never happen for an output. */
7938 if (asm_noperands (PATTERN (insn
)) < 0)
7939 /* It's the compiler's fault. */
7940 fatal_insn ("VOIDmode on an output", insn
);
7941 error_for_asm (insn
, "output operand is constant in %<asm%>");
7942 /* Prevent crash--use something we know is valid. */
7944 rl
->out
= gen_rtx_REG (mode
, REGNO (reg_rtx
));
7946 if (GET_MODE (reg_rtx
) != mode
)
7947 reg_rtx
= reload_adjust_reg_for_mode (reg_rtx
, mode
);
7949 reload_reg_rtx_for_output
[j
] = reg_rtx
;
7954 && ! rtx_equal_p (rl
->in_reg
, pseudo
)
7955 && REGNO (pseudo
) >= FIRST_PSEUDO_REGISTER
7956 && reg_last_reload_reg
[REGNO (pseudo
)])
7958 int pseudo_no
= REGNO (pseudo
);
7959 int last_regno
= REGNO (reg_last_reload_reg
[pseudo_no
]);
7961 /* We don't need to test full validity of last_regno for
7962 inherit here; we only want to know if the store actually
7963 matches the pseudo. */
7964 if (TEST_HARD_REG_BIT (reg_reloaded_valid
, last_regno
)
7965 && reg_reloaded_contents
[last_regno
] == pseudo_no
7966 && spill_reg_store
[last_regno
]
7967 && rtx_equal_p (pseudo
, spill_reg_stored_to
[last_regno
]))
7968 delete_output_reload (insn
, j
, last_regno
, reg_rtx
);
7974 || rtx_equal_p (old
, reg_rtx
))
7977 /* An output operand that dies right away does need a reload,
7978 but need not be copied from it. Show the new location in the
7980 if ((REG_P (old
) || GET_CODE (old
) == SCRATCH
)
7981 && (note
= find_reg_note (insn
, REG_UNUSED
, old
)) != 0)
7983 XEXP (note
, 0) = reg_rtx
;
7986 /* Likewise for a SUBREG of an operand that dies. */
7987 else if (GET_CODE (old
) == SUBREG
7988 && REG_P (SUBREG_REG (old
))
7989 && 0 != (note
= find_reg_note (insn
, REG_UNUSED
,
7992 XEXP (note
, 0) = gen_lowpart_common (GET_MODE (old
), reg_rtx
);
7995 else if (GET_CODE (old
) == SCRATCH
)
7996 /* If we aren't optimizing, there won't be a REG_UNUSED note,
7997 but we don't want to make an output reload. */
8000 /* If is a JUMP_INSN, we can't support output reloads yet. */
8001 gcc_assert (NONJUMP_INSN_P (insn
));
8003 emit_output_reload_insns (chain
, rld
+ j
, j
);
8006 /* A reload copies values of MODE from register SRC to register DEST.
8007 Return true if it can be treated for inheritance purposes like a
8008 group of reloads, each one reloading a single hard register. The
8009 caller has already checked that (reg:MODE SRC) and (reg:MODE DEST)
8010 occupy the same number of hard registers. */
8013 inherit_piecemeal_p (int dest ATTRIBUTE_UNUSED
,
8014 int src ATTRIBUTE_UNUSED
,
8015 enum machine_mode mode ATTRIBUTE_UNUSED
)
8017 #ifdef CANNOT_CHANGE_MODE_CLASS
8018 return (!REG_CANNOT_CHANGE_MODE_P (dest
, mode
, reg_raw_mode
[dest
])
8019 && !REG_CANNOT_CHANGE_MODE_P (src
, mode
, reg_raw_mode
[src
]));
8025 /* Output insns to reload values in and out of the chosen reload regs. */
8028 emit_reload_insns (struct insn_chain
*chain
)
8030 rtx insn
= chain
->insn
;
8034 CLEAR_HARD_REG_SET (reg_reloaded_died
);
8036 for (j
= 0; j
< reload_n_operands
; j
++)
8037 input_reload_insns
[j
] = input_address_reload_insns
[j
]
8038 = inpaddr_address_reload_insns
[j
]
8039 = output_reload_insns
[j
] = output_address_reload_insns
[j
]
8040 = outaddr_address_reload_insns
[j
]
8041 = other_output_reload_insns
[j
] = 0;
8042 other_input_address_reload_insns
= 0;
8043 other_input_reload_insns
= 0;
8044 operand_reload_insns
= 0;
8045 other_operand_reload_insns
= 0;
8047 /* Dump reloads into the dump file. */
8050 fprintf (dump_file
, "\nReloads for insn # %d\n", INSN_UID (insn
));
8051 debug_reload_to_stream (dump_file
);
8054 for (j
= 0; j
< n_reloads
; j
++)
8055 if (rld
[j
].reg_rtx
&& HARD_REGISTER_P (rld
[j
].reg_rtx
))
8059 for (i
= REGNO (rld
[j
].reg_rtx
); i
< END_REGNO (rld
[j
].reg_rtx
); i
++)
8060 new_spill_reg_store
[i
] = 0;
8063 /* Now output the instructions to copy the data into and out of the
8064 reload registers. Do these in the order that the reloads were reported,
8065 since reloads of base and index registers precede reloads of operands
8066 and the operands may need the base and index registers reloaded. */
8068 for (j
= 0; j
< n_reloads
; j
++)
8070 do_input_reload (chain
, rld
+ j
, j
);
8071 do_output_reload (chain
, rld
+ j
, j
);
8074 /* Now write all the insns we made for reloads in the order expected by
8075 the allocation functions. Prior to the insn being reloaded, we write
8076 the following reloads:
8078 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
8080 RELOAD_OTHER reloads.
8082 For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
8083 by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
8084 RELOAD_FOR_INPUT reload for the operand.
8086 RELOAD_FOR_OPADDR_ADDRS reloads.
8088 RELOAD_FOR_OPERAND_ADDRESS reloads.
8090 After the insn being reloaded, we write the following:
8092 For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
8093 by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
8094 RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
8095 reloads for the operand. The RELOAD_OTHER output reloads are
8096 output in descending order by reload number. */
8098 emit_insn_before (other_input_address_reload_insns
, insn
);
8099 emit_insn_before (other_input_reload_insns
, insn
);
8101 for (j
= 0; j
< reload_n_operands
; j
++)
8103 emit_insn_before (inpaddr_address_reload_insns
[j
], insn
);
8104 emit_insn_before (input_address_reload_insns
[j
], insn
);
8105 emit_insn_before (input_reload_insns
[j
], insn
);
8108 emit_insn_before (other_operand_reload_insns
, insn
);
8109 emit_insn_before (operand_reload_insns
, insn
);
8111 for (j
= 0; j
< reload_n_operands
; j
++)
8113 rtx x
= emit_insn_after (outaddr_address_reload_insns
[j
], insn
);
8114 x
= emit_insn_after (output_address_reload_insns
[j
], x
);
8115 x
= emit_insn_after (output_reload_insns
[j
], x
);
8116 emit_insn_after (other_output_reload_insns
[j
], x
);
8119 /* For all the spill regs newly reloaded in this instruction,
8120 record what they were reloaded from, so subsequent instructions
8121 can inherit the reloads.
8123 Update spill_reg_store for the reloads of this insn.
8124 Copy the elements that were updated in the loop above. */
8126 for (j
= 0; j
< n_reloads
; j
++)
8128 int r
= reload_order
[j
];
8129 int i
= reload_spill_index
[r
];
8131 /* If this is a non-inherited input reload from a pseudo, we must
8132 clear any memory of a previous store to the same pseudo. Only do
8133 something if there will not be an output reload for the pseudo
8135 if (rld
[r
].in_reg
!= 0
8136 && ! (reload_inherited
[r
] || reload_override_in
[r
]))
8138 rtx reg
= rld
[r
].in_reg
;
8140 if (GET_CODE (reg
) == SUBREG
)
8141 reg
= SUBREG_REG (reg
);
8144 && REGNO (reg
) >= FIRST_PSEUDO_REGISTER
8145 && !REGNO_REG_SET_P (®_has_output_reload
, REGNO (reg
)))
8147 int nregno
= REGNO (reg
);
8149 if (reg_last_reload_reg
[nregno
])
8151 int last_regno
= REGNO (reg_last_reload_reg
[nregno
]);
8153 if (reg_reloaded_contents
[last_regno
] == nregno
)
8154 spill_reg_store
[last_regno
] = 0;
8159 /* I is nonneg if this reload used a register.
8160 If rld[r].reg_rtx is 0, this is an optional reload
8161 that we opted to ignore. */
8163 if (i
>= 0 && rld
[r
].reg_rtx
!= 0)
8165 int nr
= hard_regno_nregs
[i
][GET_MODE (rld
[r
].reg_rtx
)];
8168 /* For a multi register reload, we need to check if all or part
8169 of the value lives to the end. */
8170 for (k
= 0; k
< nr
; k
++)
8171 if (reload_reg_reaches_end_p (i
+ k
, r
))
8172 CLEAR_HARD_REG_BIT (reg_reloaded_valid
, i
+ k
);
8174 /* Maybe the spill reg contains a copy of reload_out. */
8176 && (REG_P (rld
[r
].out
)
8178 ? REG_P (rld
[r
].out_reg
)
8179 /* The reload value is an auto-modification of
8180 some kind. For PRE_INC, POST_INC, PRE_DEC
8181 and POST_DEC, we record an equivalence
8182 between the reload register and the operand
8183 on the optimistic assumption that we can make
8184 the equivalence hold. reload_as_needed must
8185 then either make it hold or invalidate the
8188 PRE_MODIFY and POST_MODIFY addresses are reloaded
8189 somewhat differently, and allowing them here leads
8191 : (GET_CODE (rld
[r
].out
) != POST_MODIFY
8192 && GET_CODE (rld
[r
].out
) != PRE_MODIFY
))))
8196 reg
= reload_reg_rtx_for_output
[r
];
8197 if (reload_reg_rtx_reaches_end_p (reg
, r
))
8199 enum machine_mode mode
= GET_MODE (reg
);
8200 int regno
= REGNO (reg
);
8201 int nregs
= hard_regno_nregs
[regno
][mode
];
8202 rtx out
= (REG_P (rld
[r
].out
)
8206 /* AUTO_INC */ : XEXP (rld
[r
].in_reg
, 0));
8207 int out_regno
= REGNO (out
);
8208 int out_nregs
= (!HARD_REGISTER_NUM_P (out_regno
) ? 1
8209 : hard_regno_nregs
[out_regno
][mode
]);
8212 spill_reg_store
[regno
] = new_spill_reg_store
[regno
];
8213 spill_reg_stored_to
[regno
] = out
;
8214 reg_last_reload_reg
[out_regno
] = reg
;
8216 piecemeal
= (HARD_REGISTER_NUM_P (out_regno
)
8217 && nregs
== out_nregs
8218 && inherit_piecemeal_p (out_regno
, regno
, mode
));
8220 /* If OUT_REGNO is a hard register, it may occupy more than
8221 one register. If it does, say what is in the
8222 rest of the registers assuming that both registers
8223 agree on how many words the object takes. If not,
8224 invalidate the subsequent registers. */
8226 if (HARD_REGISTER_NUM_P (out_regno
))
8227 for (k
= 1; k
< out_nregs
; k
++)
8228 reg_last_reload_reg
[out_regno
+ k
]
8229 = (piecemeal
? regno_reg_rtx
[regno
+ k
] : 0);
8231 /* Now do the inverse operation. */
8232 for (k
= 0; k
< nregs
; k
++)
8234 CLEAR_HARD_REG_BIT (reg_reloaded_dead
, regno
+ k
);
8235 reg_reloaded_contents
[regno
+ k
]
8236 = (!HARD_REGISTER_NUM_P (out_regno
) || !piecemeal
8239 reg_reloaded_insn
[regno
+ k
] = insn
;
8240 SET_HARD_REG_BIT (reg_reloaded_valid
, regno
+ k
);
8241 if (HARD_REGNO_CALL_PART_CLOBBERED (regno
+ k
, mode
))
8242 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered
,
8245 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered
,
8250 /* Maybe the spill reg contains a copy of reload_in. Only do
8251 something if there will not be an output reload for
8252 the register being reloaded. */
8253 else if (rld
[r
].out_reg
== 0
8255 && ((REG_P (rld
[r
].in
)
8256 && !HARD_REGISTER_P (rld
[r
].in
)
8257 && !REGNO_REG_SET_P (®_has_output_reload
,
8259 || (REG_P (rld
[r
].in_reg
)
8260 && !REGNO_REG_SET_P (®_has_output_reload
,
8261 REGNO (rld
[r
].in_reg
))))
8262 && !reg_set_p (reload_reg_rtx_for_input
[r
], PATTERN (insn
)))
8266 reg
= reload_reg_rtx_for_input
[r
];
8267 if (reload_reg_rtx_reaches_end_p (reg
, r
))
8269 enum machine_mode mode
;
8277 mode
= GET_MODE (reg
);
8278 regno
= REGNO (reg
);
8279 nregs
= hard_regno_nregs
[regno
][mode
];
8280 if (REG_P (rld
[r
].in
)
8281 && REGNO (rld
[r
].in
) >= FIRST_PSEUDO_REGISTER
)
8283 else if (REG_P (rld
[r
].in_reg
))
8286 in
= XEXP (rld
[r
].in_reg
, 0);
8287 in_regno
= REGNO (in
);
8289 in_nregs
= (!HARD_REGISTER_NUM_P (in_regno
) ? 1
8290 : hard_regno_nregs
[in_regno
][mode
]);
8292 reg_last_reload_reg
[in_regno
] = reg
;
8294 piecemeal
= (HARD_REGISTER_NUM_P (in_regno
)
8295 && nregs
== in_nregs
8296 && inherit_piecemeal_p (regno
, in_regno
, mode
));
8298 if (HARD_REGISTER_NUM_P (in_regno
))
8299 for (k
= 1; k
< in_nregs
; k
++)
8300 reg_last_reload_reg
[in_regno
+ k
]
8301 = (piecemeal
? regno_reg_rtx
[regno
+ k
] : 0);
8303 /* Unless we inherited this reload, show we haven't
8304 recently done a store.
8305 Previous stores of inherited auto_inc expressions
8306 also have to be discarded. */
8307 if (! reload_inherited
[r
]
8308 || (rld
[r
].out
&& ! rld
[r
].out_reg
))
8309 spill_reg_store
[regno
] = 0;
8311 for (k
= 0; k
< nregs
; k
++)
8313 CLEAR_HARD_REG_BIT (reg_reloaded_dead
, regno
+ k
);
8314 reg_reloaded_contents
[regno
+ k
]
8315 = (!HARD_REGISTER_NUM_P (in_regno
) || !piecemeal
8318 reg_reloaded_insn
[regno
+ k
] = insn
;
8319 SET_HARD_REG_BIT (reg_reloaded_valid
, regno
+ k
);
8320 if (HARD_REGNO_CALL_PART_CLOBBERED (regno
+ k
, mode
))
8321 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered
,
8324 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered
,
8331 /* The following if-statement was #if 0'd in 1.34 (or before...).
8332 It's reenabled in 1.35 because supposedly nothing else
8333 deals with this problem. */
8335 /* If a register gets output-reloaded from a non-spill register,
8336 that invalidates any previous reloaded copy of it.
8337 But forget_old_reloads_1 won't get to see it, because
8338 it thinks only about the original insn. So invalidate it here.
8339 Also do the same thing for RELOAD_OTHER constraints where the
8340 output is discarded. */
8342 && ((rld
[r
].out
!= 0
8343 && (REG_P (rld
[r
].out
)
8344 || (MEM_P (rld
[r
].out
)
8345 && REG_P (rld
[r
].out_reg
))))
8346 || (rld
[r
].out
== 0 && rld
[r
].out_reg
8347 && REG_P (rld
[r
].out_reg
))))
8349 rtx out
= ((rld
[r
].out
&& REG_P (rld
[r
].out
))
8350 ? rld
[r
].out
: rld
[r
].out_reg
);
8351 int out_regno
= REGNO (out
);
8352 enum machine_mode mode
= GET_MODE (out
);
8354 /* REG_RTX is now set or clobbered by the main instruction.
8355 As the comment above explains, forget_old_reloads_1 only
8356 sees the original instruction, and there is no guarantee
8357 that the original instruction also clobbered REG_RTX.
8358 For example, if find_reloads sees that the input side of
8359 a matched operand pair dies in this instruction, it may
8360 use the input register as the reload register.
8362 Calling forget_old_reloads_1 is a waste of effort if
8363 REG_RTX is also the output register.
8365 If we know that REG_RTX holds the value of a pseudo
8366 register, the code after the call will record that fact. */
8367 if (rld
[r
].reg_rtx
&& rld
[r
].reg_rtx
!= out
)
8368 forget_old_reloads_1 (rld
[r
].reg_rtx
, NULL_RTX
, NULL
);
8370 if (!HARD_REGISTER_NUM_P (out_regno
))
8372 rtx src_reg
, store_insn
= NULL_RTX
;
8374 reg_last_reload_reg
[out_regno
] = 0;
8376 /* If we can find a hard register that is stored, record
8377 the storing insn so that we may delete this insn with
8378 delete_output_reload. */
8379 src_reg
= reload_reg_rtx_for_output
[r
];
8383 if (reload_reg_rtx_reaches_end_p (src_reg
, r
))
8384 store_insn
= new_spill_reg_store
[REGNO (src_reg
)];
8390 /* If this is an optional reload, try to find the
8391 source reg from an input reload. */
8392 rtx set
= single_set (insn
);
8393 if (set
&& SET_DEST (set
) == rld
[r
].out
)
8397 src_reg
= SET_SRC (set
);
8399 for (k
= 0; k
< n_reloads
; k
++)
8401 if (rld
[k
].in
== src_reg
)
8403 src_reg
= reload_reg_rtx_for_input
[k
];
8409 if (src_reg
&& REG_P (src_reg
)
8410 && REGNO (src_reg
) < FIRST_PSEUDO_REGISTER
)
8412 int src_regno
, src_nregs
, k
;
8415 gcc_assert (GET_MODE (src_reg
) == mode
);
8416 src_regno
= REGNO (src_reg
);
8417 src_nregs
= hard_regno_nregs
[src_regno
][mode
];
8418 /* The place where to find a death note varies with
8419 PRESERVE_DEATH_INFO_REGNO_P . The condition is not
8420 necessarily checked exactly in the code that moves
8421 notes, so just check both locations. */
8422 note
= find_regno_note (insn
, REG_DEAD
, src_regno
);
8423 if (! note
&& store_insn
)
8424 note
= find_regno_note (store_insn
, REG_DEAD
, src_regno
);
8425 for (k
= 0; k
< src_nregs
; k
++)
8427 spill_reg_store
[src_regno
+ k
] = store_insn
;
8428 spill_reg_stored_to
[src_regno
+ k
] = out
;
8429 reg_reloaded_contents
[src_regno
+ k
] = out_regno
;
8430 reg_reloaded_insn
[src_regno
+ k
] = store_insn
;
8431 CLEAR_HARD_REG_BIT (reg_reloaded_dead
, src_regno
+ k
);
8432 SET_HARD_REG_BIT (reg_reloaded_valid
, src_regno
+ k
);
8433 if (HARD_REGNO_CALL_PART_CLOBBERED (src_regno
+ k
,
8435 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered
,
8438 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered
,
8440 SET_HARD_REG_BIT (reg_is_output_reload
, src_regno
+ k
);
8442 SET_HARD_REG_BIT (reg_reloaded_died
, src_regno
);
8444 CLEAR_HARD_REG_BIT (reg_reloaded_died
, src_regno
);
8446 reg_last_reload_reg
[out_regno
] = src_reg
;
8447 /* We have to set reg_has_output_reload here, or else
8448 forget_old_reloads_1 will clear reg_last_reload_reg
8450 SET_REGNO_REG_SET (®_has_output_reload
,
8456 int k
, out_nregs
= hard_regno_nregs
[out_regno
][mode
];
8458 for (k
= 0; k
< out_nregs
; k
++)
8459 reg_last_reload_reg
[out_regno
+ k
] = 0;
8463 IOR_HARD_REG_SET (reg_reloaded_dead
, reg_reloaded_died
);
8466 /* Go through the motions to emit INSN and test if it is strictly valid.
8467 Return the emitted insn if valid, else return NULL. */
8470 emit_insn_if_valid_for_reload (rtx insn
)
8472 rtx last
= get_last_insn ();
8475 insn
= emit_insn (insn
);
8476 code
= recog_memoized (insn
);
8480 extract_insn (insn
);
8481 /* We want constrain operands to treat this insn strictly in its
8482 validity determination, i.e., the way it would after reload has
8484 if (constrain_operands (1))
8488 delete_insns_since (last
);
8492 /* Emit code to perform a reload from IN (which may be a reload register) to
8493 OUT (which may also be a reload register). IN or OUT is from operand
8494 OPNUM with reload type TYPE.
8496 Returns first insn emitted. */
8499 gen_reload (rtx out
, rtx in
, int opnum
, enum reload_type type
)
8501 rtx last
= get_last_insn ();
8503 #ifdef SECONDARY_MEMORY_NEEDED
8507 /* If IN is a paradoxical SUBREG, remove it and try to put the
8508 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
8509 if (!strip_paradoxical_subreg (&in
, &out
))
8510 strip_paradoxical_subreg (&out
, &in
);
8512 /* How to do this reload can get quite tricky. Normally, we are being
8513 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
8514 register that didn't get a hard register. In that case we can just
8515 call emit_move_insn.
8517 We can also be asked to reload a PLUS that adds a register or a MEM to
8518 another register, constant or MEM. This can occur during frame pointer
8519 elimination and while reloading addresses. This case is handled by
8520 trying to emit a single insn to perform the add. If it is not valid,
8521 we use a two insn sequence.
8523 Or we can be asked to reload an unary operand that was a fragment of
8524 an addressing mode, into a register. If it isn't recognized as-is,
8525 we try making the unop operand and the reload-register the same:
8526 (set reg:X (unop:X expr:Y))
8527 -> (set reg:Y expr:Y) (set reg:X (unop:X reg:Y)).
8529 Finally, we could be called to handle an 'o' constraint by putting
8530 an address into a register. In that case, we first try to do this
8531 with a named pattern of "reload_load_address". If no such pattern
8532 exists, we just emit a SET insn and hope for the best (it will normally
8533 be valid on machines that use 'o').
8535 This entire process is made complex because reload will never
8536 process the insns we generate here and so we must ensure that
8537 they will fit their constraints and also by the fact that parts of
8538 IN might be being reloaded separately and replaced with spill registers.
8539 Because of this, we are, in some sense, just guessing the right approach
8540 here. The one listed above seems to work.
8542 ??? At some point, this whole thing needs to be rethought. */
8544 if (GET_CODE (in
) == PLUS
8545 && (REG_P (XEXP (in
, 0))
8546 || GET_CODE (XEXP (in
, 0)) == SUBREG
8547 || MEM_P (XEXP (in
, 0)))
8548 && (REG_P (XEXP (in
, 1))
8549 || GET_CODE (XEXP (in
, 1)) == SUBREG
8550 || CONSTANT_P (XEXP (in
, 1))
8551 || MEM_P (XEXP (in
, 1))))
8553 /* We need to compute the sum of a register or a MEM and another
8554 register, constant, or MEM, and put it into the reload
8555 register. The best possible way of doing this is if the machine
8556 has a three-operand ADD insn that accepts the required operands.
8558 The simplest approach is to try to generate such an insn and see if it
8559 is recognized and matches its constraints. If so, it can be used.
8561 It might be better not to actually emit the insn unless it is valid,
8562 but we need to pass the insn as an operand to `recog' and
8563 `extract_insn' and it is simpler to emit and then delete the insn if
8564 not valid than to dummy things up. */
8566 rtx op0
, op1
, tem
, insn
;
8567 enum insn_code code
;
8569 op0
= find_replacement (&XEXP (in
, 0));
8570 op1
= find_replacement (&XEXP (in
, 1));
8572 /* Since constraint checking is strict, commutativity won't be
8573 checked, so we need to do that here to avoid spurious failure
8574 if the add instruction is two-address and the second operand
8575 of the add is the same as the reload reg, which is frequently
8576 the case. If the insn would be A = B + A, rearrange it so
8577 it will be A = A + B as constrain_operands expects. */
8579 if (REG_P (XEXP (in
, 1))
8580 && REGNO (out
) == REGNO (XEXP (in
, 1)))
8581 tem
= op0
, op0
= op1
, op1
= tem
;
8583 if (op0
!= XEXP (in
, 0) || op1
!= XEXP (in
, 1))
8584 in
= gen_rtx_PLUS (GET_MODE (in
), op0
, op1
);
8586 insn
= emit_insn_if_valid_for_reload (gen_rtx_SET (VOIDmode
, out
, in
));
8590 /* If that failed, we must use a conservative two-insn sequence.
8592 Use a move to copy one operand into the reload register. Prefer
8593 to reload a constant, MEM or pseudo since the move patterns can
8594 handle an arbitrary operand. If OP1 is not a constant, MEM or
8595 pseudo and OP1 is not a valid operand for an add instruction, then
8598 After reloading one of the operands into the reload register, add
8599 the reload register to the output register.
8601 If there is another way to do this for a specific machine, a
8602 DEFINE_PEEPHOLE should be specified that recognizes the sequence
8605 code
= optab_handler (add_optab
, GET_MODE (out
));
8607 if (CONSTANT_P (op1
) || MEM_P (op1
) || GET_CODE (op1
) == SUBREG
8609 && REGNO (op1
) >= FIRST_PSEUDO_REGISTER
)
8610 || (code
!= CODE_FOR_nothing
8611 && !insn_operand_matches (code
, 2, op1
)))
8612 tem
= op0
, op0
= op1
, op1
= tem
;
8614 gen_reload (out
, op0
, opnum
, type
);
8616 /* If OP0 and OP1 are the same, we can use OUT for OP1.
8617 This fixes a problem on the 32K where the stack pointer cannot
8618 be used as an operand of an add insn. */
8620 if (rtx_equal_p (op0
, op1
))
8623 insn
= emit_insn_if_valid_for_reload (gen_add2_insn (out
, op1
));
8626 /* Add a REG_EQUIV note so that find_equiv_reg can find it. */
8627 set_dst_reg_note (insn
, REG_EQUIV
, in
, out
);
8631 /* If that failed, copy the address register to the reload register.
8632 Then add the constant to the reload register. */
8634 gcc_assert (!reg_overlap_mentioned_p (out
, op0
));
8635 gen_reload (out
, op1
, opnum
, type
);
8636 insn
= emit_insn (gen_add2_insn (out
, op0
));
8637 set_dst_reg_note (insn
, REG_EQUIV
, in
, out
);
8640 #ifdef SECONDARY_MEMORY_NEEDED
8641 /* If we need a memory location to do the move, do it that way. */
8642 else if ((tem1
= replaced_subreg (in
), tem2
= replaced_subreg (out
),
8643 (REG_P (tem1
) && REG_P (tem2
)))
8644 && REGNO (tem1
) < FIRST_PSEUDO_REGISTER
8645 && REGNO (tem2
) < FIRST_PSEUDO_REGISTER
8646 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (REGNO (tem1
)),
8647 REGNO_REG_CLASS (REGNO (tem2
)),
8650 /* Get the memory to use and rewrite both registers to its mode. */
8651 rtx loc
= get_secondary_mem (in
, GET_MODE (out
), opnum
, type
);
8653 if (GET_MODE (loc
) != GET_MODE (out
))
8654 out
= gen_rtx_REG (GET_MODE (loc
), reg_or_subregno (out
));
8656 if (GET_MODE (loc
) != GET_MODE (in
))
8657 in
= gen_rtx_REG (GET_MODE (loc
), reg_or_subregno (in
));
8659 gen_reload (loc
, in
, opnum
, type
);
8660 gen_reload (out
, loc
, opnum
, type
);
8663 else if (REG_P (out
) && UNARY_P (in
))
8670 op1
= find_replacement (&XEXP (in
, 0));
8671 if (op1
!= XEXP (in
, 0))
8672 in
= gen_rtx_fmt_e (GET_CODE (in
), GET_MODE (in
), op1
);
8674 /* First, try a plain SET. */
8675 set
= emit_insn_if_valid_for_reload (gen_rtx_SET (VOIDmode
, out
, in
));
8679 /* If that failed, move the inner operand to the reload
8680 register, and try the same unop with the inner expression
8681 replaced with the reload register. */
8683 if (GET_MODE (op1
) != GET_MODE (out
))
8684 out_moded
= gen_rtx_REG (GET_MODE (op1
), REGNO (out
));
8688 gen_reload (out_moded
, op1
, opnum
, type
);
8691 = gen_rtx_SET (VOIDmode
, out
,
8692 gen_rtx_fmt_e (GET_CODE (in
), GET_MODE (in
),
8694 insn
= emit_insn_if_valid_for_reload (insn
);
8697 set_unique_reg_note (insn
, REG_EQUIV
, in
);
8701 fatal_insn ("failure trying to reload:", set
);
8703 /* If IN is a simple operand, use gen_move_insn. */
8704 else if (OBJECT_P (in
) || GET_CODE (in
) == SUBREG
)
8706 tem
= emit_insn (gen_move_insn (out
, in
));
8707 /* IN may contain a LABEL_REF, if so add a REG_LABEL_OPERAND note. */
8708 mark_jump_label (in
, tem
, 0);
8711 #ifdef HAVE_reload_load_address
8712 else if (HAVE_reload_load_address
)
8713 emit_insn (gen_reload_load_address (out
, in
));
8716 /* Otherwise, just write (set OUT IN) and hope for the best. */
8718 emit_insn (gen_rtx_SET (VOIDmode
, out
, in
));
8720 /* Return the first insn emitted.
8721 We can not just return get_last_insn, because there may have
8722 been multiple instructions emitted. Also note that gen_move_insn may
8723 emit more than one insn itself, so we can not assume that there is one
8724 insn emitted per emit_insn_before call. */
8726 return last
? NEXT_INSN (last
) : get_insns ();
8729 /* Delete a previously made output-reload whose result we now believe
8730 is not needed. First we double-check.
8732 INSN is the insn now being processed.
8733 LAST_RELOAD_REG is the hard register number for which we want to delete
8734 the last output reload.
8735 J is the reload-number that originally used REG. The caller has made
8736 certain that reload J doesn't use REG any longer for input.
8737 NEW_RELOAD_REG is reload register that reload J is using for REG. */
8740 delete_output_reload (rtx insn
, int j
, int last_reload_reg
, rtx new_reload_reg
)
8742 rtx output_reload_insn
= spill_reg_store
[last_reload_reg
];
8743 rtx reg
= spill_reg_stored_to
[last_reload_reg
];
8746 int n_inherited
= 0;
8752 /* It is possible that this reload has been only used to set another reload
8753 we eliminated earlier and thus deleted this instruction too. */
8754 if (INSN_DELETED_P (output_reload_insn
))
8757 /* Get the raw pseudo-register referred to. */
8759 while (GET_CODE (reg
) == SUBREG
)
8760 reg
= SUBREG_REG (reg
);
8761 substed
= reg_equiv_memory_loc (REGNO (reg
));
8763 /* This is unsafe if the operand occurs more often in the current
8764 insn than it is inherited. */
8765 for (k
= n_reloads
- 1; k
>= 0; k
--)
8767 rtx reg2
= rld
[k
].in
;
8770 if (MEM_P (reg2
) || reload_override_in
[k
])
8771 reg2
= rld
[k
].in_reg
;
8773 if (rld
[k
].out
&& ! rld
[k
].out_reg
)
8774 reg2
= XEXP (rld
[k
].in_reg
, 0);
8776 while (GET_CODE (reg2
) == SUBREG
)
8777 reg2
= SUBREG_REG (reg2
);
8778 if (rtx_equal_p (reg2
, reg
))
8780 if (reload_inherited
[k
] || reload_override_in
[k
] || k
== j
)
8786 n_occurrences
= count_occurrences (PATTERN (insn
), reg
, 0);
8787 if (CALL_P (insn
) && CALL_INSN_FUNCTION_USAGE (insn
))
8788 n_occurrences
+= count_occurrences (CALL_INSN_FUNCTION_USAGE (insn
),
8791 n_occurrences
+= count_occurrences (PATTERN (insn
),
8792 eliminate_regs (substed
, VOIDmode
,
8794 for (i1
= reg_equiv_alt_mem_list (REGNO (reg
)); i1
; i1
= XEXP (i1
, 1))
8796 gcc_assert (!rtx_equal_p (XEXP (i1
, 0), substed
));
8797 n_occurrences
+= count_occurrences (PATTERN (insn
), XEXP (i1
, 0), 0);
8799 if (n_occurrences
> n_inherited
)
8802 regno
= REGNO (reg
);
8803 if (regno
>= FIRST_PSEUDO_REGISTER
)
8806 nregs
= hard_regno_nregs
[regno
][GET_MODE (reg
)];
8808 /* If the pseudo-reg we are reloading is no longer referenced
8809 anywhere between the store into it and here,
8810 and we're within the same basic block, then the value can only
8811 pass through the reload reg and end up here.
8812 Otherwise, give up--return. */
8813 for (i1
= NEXT_INSN (output_reload_insn
);
8814 i1
!= insn
; i1
= NEXT_INSN (i1
))
8816 if (NOTE_INSN_BASIC_BLOCK_P (i1
))
8818 if ((NONJUMP_INSN_P (i1
) || CALL_P (i1
))
8819 && refers_to_regno_p (regno
, regno
+ nregs
, PATTERN (i1
), NULL
))
8821 /* If this is USE in front of INSN, we only have to check that
8822 there are no more references than accounted for by inheritance. */
8823 while (NONJUMP_INSN_P (i1
) && GET_CODE (PATTERN (i1
)) == USE
)
8825 n_occurrences
+= rtx_equal_p (reg
, XEXP (PATTERN (i1
), 0)) != 0;
8826 i1
= NEXT_INSN (i1
);
8828 if (n_occurrences
<= n_inherited
&& i1
== insn
)
8834 /* We will be deleting the insn. Remove the spill reg information. */
8835 for (k
= hard_regno_nregs
[last_reload_reg
][GET_MODE (reg
)]; k
-- > 0; )
8837 spill_reg_store
[last_reload_reg
+ k
] = 0;
8838 spill_reg_stored_to
[last_reload_reg
+ k
] = 0;
8841 /* The caller has already checked that REG dies or is set in INSN.
8842 It has also checked that we are optimizing, and thus some
8843 inaccuracies in the debugging information are acceptable.
8844 So we could just delete output_reload_insn. But in some cases
8845 we can improve the debugging information without sacrificing
8846 optimization - maybe even improving the code: See if the pseudo
8847 reg has been completely replaced with reload regs. If so, delete
8848 the store insn and forget we had a stack slot for the pseudo. */
8849 if (rld
[j
].out
!= rld
[j
].in
8850 && REG_N_DEATHS (REGNO (reg
)) == 1
8851 && REG_N_SETS (REGNO (reg
)) == 1
8852 && REG_BASIC_BLOCK (REGNO (reg
)) >= NUM_FIXED_BLOCKS
8853 && find_regno_note (insn
, REG_DEAD
, REGNO (reg
)))
8857 /* We know that it was used only between here and the beginning of
8858 the current basic block. (We also know that the last use before
8859 INSN was the output reload we are thinking of deleting, but never
8860 mind that.) Search that range; see if any ref remains. */
8861 for (i2
= PREV_INSN (insn
); i2
; i2
= PREV_INSN (i2
))
8863 rtx set
= single_set (i2
);
8865 /* Uses which just store in the pseudo don't count,
8866 since if they are the only uses, they are dead. */
8867 if (set
!= 0 && SET_DEST (set
) == reg
)
8872 if ((NONJUMP_INSN_P (i2
) || CALL_P (i2
))
8873 && reg_mentioned_p (reg
, PATTERN (i2
)))
8875 /* Some other ref remains; just delete the output reload we
8877 delete_address_reloads (output_reload_insn
, insn
);
8878 delete_insn (output_reload_insn
);
8883 /* Delete the now-dead stores into this pseudo. Note that this
8884 loop also takes care of deleting output_reload_insn. */
8885 for (i2
= PREV_INSN (insn
); i2
; i2
= PREV_INSN (i2
))
8887 rtx set
= single_set (i2
);
8889 if (set
!= 0 && SET_DEST (set
) == reg
)
8891 delete_address_reloads (i2
, insn
);
8899 /* For the debugging info, say the pseudo lives in this reload reg. */
8900 reg_renumber
[REGNO (reg
)] = REGNO (new_reload_reg
);
8901 if (ira_conflicts_p
)
8902 /* Inform IRA about the change. */
8903 ira_mark_allocation_change (REGNO (reg
));
8904 alter_reg (REGNO (reg
), -1, false);
8908 delete_address_reloads (output_reload_insn
, insn
);
8909 delete_insn (output_reload_insn
);
8913 /* We are going to delete DEAD_INSN. Recursively delete loads of
8914 reload registers used in DEAD_INSN that are not used till CURRENT_INSN.
8915 CURRENT_INSN is being reloaded, so we have to check its reloads too. */
8917 delete_address_reloads (rtx dead_insn
, rtx current_insn
)
8919 rtx set
= single_set (dead_insn
);
8920 rtx set2
, dst
, prev
, next
;
8923 rtx dst
= SET_DEST (set
);
8925 delete_address_reloads_1 (dead_insn
, XEXP (dst
, 0), current_insn
);
8927 /* If we deleted the store from a reloaded post_{in,de}c expression,
8928 we can delete the matching adds. */
8929 prev
= PREV_INSN (dead_insn
);
8930 next
= NEXT_INSN (dead_insn
);
8931 if (! prev
|| ! next
)
8933 set
= single_set (next
);
8934 set2
= single_set (prev
);
8936 || GET_CODE (SET_SRC (set
)) != PLUS
|| GET_CODE (SET_SRC (set2
)) != PLUS
8937 || !CONST_INT_P (XEXP (SET_SRC (set
), 1))
8938 || !CONST_INT_P (XEXP (SET_SRC (set2
), 1)))
8940 dst
= SET_DEST (set
);
8941 if (! rtx_equal_p (dst
, SET_DEST (set2
))
8942 || ! rtx_equal_p (dst
, XEXP (SET_SRC (set
), 0))
8943 || ! rtx_equal_p (dst
, XEXP (SET_SRC (set2
), 0))
8944 || (INTVAL (XEXP (SET_SRC (set
), 1))
8945 != -INTVAL (XEXP (SET_SRC (set2
), 1))))
8947 delete_related_insns (prev
);
8948 delete_related_insns (next
);
8951 /* Subfunction of delete_address_reloads: process registers found in X. */
8953 delete_address_reloads_1 (rtx dead_insn
, rtx x
, rtx current_insn
)
8955 rtx prev
, set
, dst
, i2
;
8957 enum rtx_code code
= GET_CODE (x
);
8961 const char *fmt
= GET_RTX_FORMAT (code
);
8962 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
8965 delete_address_reloads_1 (dead_insn
, XEXP (x
, i
), current_insn
);
8966 else if (fmt
[i
] == 'E')
8968 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
8969 delete_address_reloads_1 (dead_insn
, XVECEXP (x
, i
, j
),
8976 if (spill_reg_order
[REGNO (x
)] < 0)
8979 /* Scan backwards for the insn that sets x. This might be a way back due
8981 for (prev
= PREV_INSN (dead_insn
); prev
; prev
= PREV_INSN (prev
))
8983 code
= GET_CODE (prev
);
8984 if (code
== CODE_LABEL
|| code
== JUMP_INSN
)
8988 if (reg_set_p (x
, PATTERN (prev
)))
8990 if (reg_referenced_p (x
, PATTERN (prev
)))
8993 if (! prev
|| INSN_UID (prev
) < reload_first_uid
)
8995 /* Check that PREV only sets the reload register. */
8996 set
= single_set (prev
);
8999 dst
= SET_DEST (set
);
9001 || ! rtx_equal_p (dst
, x
))
9003 if (! reg_set_p (dst
, PATTERN (dead_insn
)))
9005 /* Check if DST was used in a later insn -
9006 it might have been inherited. */
9007 for (i2
= NEXT_INSN (dead_insn
); i2
; i2
= NEXT_INSN (i2
))
9013 if (reg_referenced_p (dst
, PATTERN (i2
)))
9015 /* If there is a reference to the register in the current insn,
9016 it might be loaded in a non-inherited reload. If no other
9017 reload uses it, that means the register is set before
9019 if (i2
== current_insn
)
9021 for (j
= n_reloads
- 1; j
>= 0; j
--)
9022 if ((rld
[j
].reg_rtx
== dst
&& reload_inherited
[j
])
9023 || reload_override_in
[j
] == dst
)
9025 for (j
= n_reloads
- 1; j
>= 0; j
--)
9026 if (rld
[j
].in
&& rld
[j
].reg_rtx
== dst
)
9035 /* If DST is still live at CURRENT_INSN, check if it is used for
9036 any reload. Note that even if CURRENT_INSN sets DST, we still
9037 have to check the reloads. */
9038 if (i2
== current_insn
)
9040 for (j
= n_reloads
- 1; j
>= 0; j
--)
9041 if ((rld
[j
].reg_rtx
== dst
&& reload_inherited
[j
])
9042 || reload_override_in
[j
] == dst
)
9044 /* ??? We can't finish the loop here, because dst might be
9045 allocated to a pseudo in this block if no reload in this
9046 block needs any of the classes containing DST - see
9047 spill_hard_reg. There is no easy way to tell this, so we
9048 have to scan till the end of the basic block. */
9050 if (reg_set_p (dst
, PATTERN (i2
)))
9054 delete_address_reloads_1 (prev
, SET_SRC (set
), current_insn
);
9055 reg_reloaded_contents
[REGNO (dst
)] = -1;
9059 /* Output reload-insns to reload VALUE into RELOADREG.
9060 VALUE is an autoincrement or autodecrement RTX whose operand
9061 is a register or memory location;
9062 so reloading involves incrementing that location.
9063 IN is either identical to VALUE, or some cheaper place to reload from.
9065 INC_AMOUNT is the number to increment or decrement by (always positive).
9066 This cannot be deduced from VALUE. */
9069 inc_for_reload (rtx reloadreg
, rtx in
, rtx value
, int inc_amount
)
9071 /* REG or MEM to be copied and incremented. */
9072 rtx incloc
= find_replacement (&XEXP (value
, 0));
9073 /* Nonzero if increment after copying. */
9074 int post
= (GET_CODE (value
) == POST_DEC
|| GET_CODE (value
) == POST_INC
9075 || GET_CODE (value
) == POST_MODIFY
);
9080 rtx real_in
= in
== value
? incloc
: in
;
9082 /* No hard register is equivalent to this register after
9083 inc/dec operation. If REG_LAST_RELOAD_REG were nonzero,
9084 we could inc/dec that register as well (maybe even using it for
9085 the source), but I'm not sure it's worth worrying about. */
9087 reg_last_reload_reg
[REGNO (incloc
)] = 0;
9089 if (GET_CODE (value
) == PRE_MODIFY
|| GET_CODE (value
) == POST_MODIFY
)
9091 gcc_assert (GET_CODE (XEXP (value
, 1)) == PLUS
);
9092 inc
= find_replacement (&XEXP (XEXP (value
, 1), 1));
9096 if (GET_CODE (value
) == PRE_DEC
|| GET_CODE (value
) == POST_DEC
)
9097 inc_amount
= -inc_amount
;
9099 inc
= GEN_INT (inc_amount
);
9102 /* If this is post-increment, first copy the location to the reload reg. */
9103 if (post
&& real_in
!= reloadreg
)
9104 emit_insn (gen_move_insn (reloadreg
, real_in
));
9108 /* See if we can directly increment INCLOC. Use a method similar to
9109 that in gen_reload. */
9111 last
= get_last_insn ();
9112 add_insn
= emit_insn (gen_rtx_SET (VOIDmode
, incloc
,
9113 gen_rtx_PLUS (GET_MODE (incloc
),
9116 code
= recog_memoized (add_insn
);
9119 extract_insn (add_insn
);
9120 if (constrain_operands (1))
9122 /* If this is a pre-increment and we have incremented the value
9123 where it lives, copy the incremented value to RELOADREG to
9124 be used as an address. */
9127 emit_insn (gen_move_insn (reloadreg
, incloc
));
9131 delete_insns_since (last
);
9134 /* If couldn't do the increment directly, must increment in RELOADREG.
9135 The way we do this depends on whether this is pre- or post-increment.
9136 For pre-increment, copy INCLOC to the reload register, increment it
9137 there, then save back. */
9141 if (in
!= reloadreg
)
9142 emit_insn (gen_move_insn (reloadreg
, real_in
));
9143 emit_insn (gen_add2_insn (reloadreg
, inc
));
9144 emit_insn (gen_move_insn (incloc
, reloadreg
));
9149 Because this might be a jump insn or a compare, and because RELOADREG
9150 may not be available after the insn in an input reload, we must do
9151 the incrementation before the insn being reloaded for.
9153 We have already copied IN to RELOADREG. Increment the copy in
9154 RELOADREG, save that back, then decrement RELOADREG so it has
9155 the original value. */
9157 emit_insn (gen_add2_insn (reloadreg
, inc
));
9158 emit_insn (gen_move_insn (incloc
, reloadreg
));
9159 if (CONST_INT_P (inc
))
9160 emit_insn (gen_add2_insn (reloadreg
, GEN_INT (-INTVAL (inc
))));
9162 emit_insn (gen_sub2_insn (reloadreg
, inc
));
9168 add_auto_inc_notes (rtx insn
, rtx x
)
9170 enum rtx_code code
= GET_CODE (x
);
9174 if (code
== MEM
&& auto_inc_p (XEXP (x
, 0)))
9176 add_reg_note (insn
, REG_INC
, XEXP (XEXP (x
, 0), 0));
9180 /* Scan all the operand sub-expressions. */
9181 fmt
= GET_RTX_FORMAT (code
);
9182 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
9185 add_auto_inc_notes (insn
, XEXP (x
, i
));
9186 else if (fmt
[i
] == 'E')
9187 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
9188 add_auto_inc_notes (insn
, XVECEXP (x
, i
, j
));