1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987-2019 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify it under
7 the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 3, or (at your option) any later
11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
22 #include "coretypes.h"
36 #include "rtl-error.h"
38 #include "addresses.h"
46 /* This file contains the reload pass of the compiler, which is
47 run after register allocation has been done. It checks that
48 each insn is valid (operands required to be in registers really
49 are in registers of the proper class) and fixes up invalid ones
50 by copying values temporarily into registers for the insns
53 The results of register allocation are described by the vector
54 reg_renumber; the insns still contain pseudo regs, but reg_renumber
55 can be used to find which hard reg, if any, a pseudo reg is in.
57 The technique we always use is to free up a few hard regs that are
58 called ``reload regs'', and for each place where a pseudo reg
59 must be in a hard reg, copy it temporarily into one of the reload regs.
61 Reload regs are allocated locally for every instruction that needs
62 reloads. When there are pseudos which are allocated to a register that
63 has been chosen as a reload reg, such pseudos must be ``spilled''.
64 This means that they go to other hard regs, or to stack slots if no other
65 available hard regs can be found. Spilling can invalidate more
66 insns, requiring additional need for reloads, so we must keep checking
67 until the process stabilizes.
69 For machines with different classes of registers, we must keep track
70 of the register class needed for each reload, and make sure that
71 we allocate enough reload registers of each class.
73 The file reload.c contains the code that checks one insn for
74 validity and reports the reloads that it needs. This file
75 is in charge of scanning the entire rtl code, accumulating the
76 reload needs, spilling, assigning reload registers to use for
77 fixing up each insn, and generating the new insns to copy values
78 into the reload registers. */
80 struct target_reload default_target_reload
;
82 struct target_reload
*this_target_reload
= &default_target_reload
;
85 #define spill_indirect_levels \
86 (this_target_reload->x_spill_indirect_levels)
88 /* During reload_as_needed, element N contains a REG rtx for the hard reg
89 into which reg N has been reloaded (perhaps for a previous insn). */
90 static rtx
*reg_last_reload_reg
;
92 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
93 for an output reload that stores into reg N. */
94 static regset_head reg_has_output_reload
;
96 /* Indicates which hard regs are reload-registers for an output reload
97 in the current insn. */
98 static HARD_REG_SET reg_is_output_reload
;
100 /* Widest mode in which each pseudo reg is referred to (via subreg). */
101 static machine_mode
*reg_max_ref_mode
;
103 /* Vector to remember old contents of reg_renumber before spilling. */
104 static short *reg_old_renumber
;
106 /* During reload_as_needed, element N contains the last pseudo regno reloaded
107 into hard register N. If that pseudo reg occupied more than one register,
108 reg_reloaded_contents points to that pseudo for each spill register in
109 use; all of these must remain set for an inheritance to occur. */
110 static int reg_reloaded_contents
[FIRST_PSEUDO_REGISTER
];
112 /* During reload_as_needed, element N contains the insn for which
113 hard register N was last used. Its contents are significant only
114 when reg_reloaded_valid is set for this register. */
115 static rtx_insn
*reg_reloaded_insn
[FIRST_PSEUDO_REGISTER
];
117 /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid. */
118 static HARD_REG_SET reg_reloaded_valid
;
119 /* Indicate if the register was dead at the end of the reload.
120 This is only valid if reg_reloaded_contents is set and valid. */
121 static HARD_REG_SET reg_reloaded_dead
;
123 /* Indicate whether the register's current value is one that is not
124 safe to retain across a call, even for registers that are normally
125 call-saved. This is only meaningful for members of reg_reloaded_valid. */
126 static HARD_REG_SET reg_reloaded_call_part_clobbered
;
128 /* Number of spill-regs so far; number of valid elements of spill_regs. */
131 /* In parallel with spill_regs, contains REG rtx's for those regs.
132 Holds the last rtx used for any given reg, or 0 if it has never
133 been used for spilling yet. This rtx is reused, provided it has
135 static rtx spill_reg_rtx
[FIRST_PSEUDO_REGISTER
];
137 /* In parallel with spill_regs, contains nonzero for a spill reg
138 that was stored after the last time it was used.
139 The precise value is the insn generated to do the store. */
140 static rtx_insn
*spill_reg_store
[FIRST_PSEUDO_REGISTER
];
142 /* This is the register that was stored with spill_reg_store. This is a
143 copy of reload_out / reload_out_reg when the value was stored; if
144 reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */
145 static rtx spill_reg_stored_to
[FIRST_PSEUDO_REGISTER
];
147 /* This table is the inverse mapping of spill_regs:
148 indexed by hard reg number,
149 it contains the position of that reg in spill_regs,
150 or -1 for something that is not in spill_regs.
152 ?!? This is no longer accurate. */
153 static short spill_reg_order
[FIRST_PSEUDO_REGISTER
];
155 /* This reg set indicates registers that can't be used as spill registers for
156 the currently processed insn. These are the hard registers which are live
157 during the insn, but not allocated to pseudos, as well as fixed
159 static HARD_REG_SET bad_spill_regs
;
161 /* These are the hard registers that can't be used as spill register for any
162 insn. This includes registers used for user variables and registers that
163 we can't eliminate. A register that appears in this set also can't be used
164 to retry register allocation. */
165 static HARD_REG_SET bad_spill_regs_global
;
167 /* Describes order of use of registers for reloading
168 of spilled pseudo-registers. `n_spills' is the number of
169 elements that are actually valid; new ones are added at the end.
171 Both spill_regs and spill_reg_order are used on two occasions:
172 once during find_reload_regs, where they keep track of the spill registers
173 for a single insn, but also during reload_as_needed where they show all
174 the registers ever used by reload. For the latter case, the information
175 is calculated during finish_spills. */
176 static short spill_regs
[FIRST_PSEUDO_REGISTER
];
178 /* This vector of reg sets indicates, for each pseudo, which hard registers
179 may not be used for retrying global allocation because the register was
180 formerly spilled from one of them. If we allowed reallocating a pseudo to
181 a register that it was already allocated to, reload might not
183 static HARD_REG_SET
*pseudo_previous_regs
;
185 /* This vector of reg sets indicates, for each pseudo, which hard
186 registers may not be used for retrying global allocation because they
187 are used as spill registers during one of the insns in which the
189 static HARD_REG_SET
*pseudo_forbidden_regs
;
191 /* All hard regs that have been used as spill registers for any insn are
192 marked in this set. */
193 static HARD_REG_SET used_spill_regs
;
195 /* Index of last register assigned as a spill register. We allocate in
196 a round-robin fashion. */
197 static int last_spill_reg
;
199 /* Record the stack slot for each spilled hard register. */
200 static rtx spill_stack_slot
[FIRST_PSEUDO_REGISTER
];
202 /* Width allocated so far for that stack slot. */
203 static poly_uint64_pod spill_stack_slot_width
[FIRST_PSEUDO_REGISTER
];
205 /* Record which pseudos needed to be spilled. */
206 static regset_head spilled_pseudos
;
208 /* Record which pseudos changed their allocation in finish_spills. */
209 static regset_head changed_allocation_pseudos
;
211 /* Used for communication between order_regs_for_reload and count_pseudo.
212 Used to avoid counting one pseudo twice. */
213 static regset_head pseudos_counted
;
215 /* First uid used by insns created by reload in this function.
216 Used in find_equiv_reg. */
217 int reload_first_uid
;
219 /* Flag set by local-alloc or global-alloc if anything is live in
220 a call-clobbered reg across calls. */
221 int caller_save_needed
;
223 /* Set to 1 while reload_as_needed is operating.
224 Required by some machines to handle any generated moves differently. */
225 int reload_in_progress
= 0;
227 /* This obstack is used for allocation of rtl during register elimination.
228 The allocated storage can be freed once find_reloads has processed the
230 static struct obstack reload_obstack
;
232 /* Points to the beginning of the reload_obstack. All insn_chain structures
233 are allocated first. */
234 static char *reload_startobj
;
236 /* The point after all insn_chain structures. Used to quickly deallocate
237 memory allocated in copy_reloads during calculate_needs_all_insns. */
238 static char *reload_firstobj
;
240 /* This points before all local rtl generated by register elimination.
241 Used to quickly free all memory after processing one insn. */
242 static char *reload_insn_firstobj
;
244 /* List of insn_chain instructions, one for every insn that reload needs to
246 class insn_chain
*reload_insn_chain
;
248 /* TRUE if we potentially left dead insns in the insn stream and want to
249 run DCE immediately after reload, FALSE otherwise. */
250 static bool need_dce
;
252 /* List of all insns needing reloads. */
253 static class insn_chain
*insns_need_reload
;
255 /* This structure is used to record information about register eliminations.
256 Each array entry describes one possible way of eliminating a register
257 in favor of another. If there is more than one way of eliminating a
258 particular register, the most preferred should be specified first. */
262 int from
; /* Register number to be eliminated. */
263 int to
; /* Register number used as replacement. */
264 poly_int64_pod initial_offset
; /* Initial difference between values. */
265 int can_eliminate
; /* Nonzero if this elimination can be done. */
266 int can_eliminate_previous
; /* Value returned by TARGET_CAN_ELIMINATE
267 target hook in previous scan over insns
269 poly_int64_pod offset
; /* Current offset between the two regs. */
270 poly_int64_pod previous_offset
; /* Offset at end of previous insn. */
271 int ref_outside_mem
; /* "to" has been referenced outside a MEM. */
272 rtx from_rtx
; /* REG rtx for the register to be eliminated.
273 We cannot simply compare the number since
274 we might then spuriously replace a hard
275 register corresponding to a pseudo
276 assigned to the reg to be eliminated. */
277 rtx to_rtx
; /* REG rtx for the replacement. */
280 static struct elim_table
*reg_eliminate
= 0;
282 /* This is an intermediate structure to initialize the table. It has
283 exactly the members provided by ELIMINABLE_REGS. */
284 static const struct elim_table_1
288 } reg_eliminate_1
[] =
292 #define NUM_ELIMINABLE_REGS ARRAY_SIZE (reg_eliminate_1)
294 /* Record the number of pending eliminations that have an offset not equal
295 to their initial offset. If nonzero, we use a new copy of each
296 replacement result in any insns encountered. */
297 int num_not_at_initial_offset
;
299 /* Count the number of registers that we may be able to eliminate. */
300 static int num_eliminable
;
301 /* And the number of registers that are equivalent to a constant that
302 can be eliminated to frame_pointer / arg_pointer + constant. */
303 static int num_eliminable_invariants
;
305 /* For each label, we record the offset of each elimination. If we reach
306 a label by more than one path and an offset differs, we cannot do the
307 elimination. This information is indexed by the difference of the
308 number of the label and the first label number. We can't offset the
309 pointer itself as this can cause problems on machines with segmented
310 memory. The first table is an array of flags that records whether we
311 have yet encountered a label and the second table is an array of arrays,
312 one entry in the latter array for each elimination. */
314 static int first_label_num
;
315 static char *offsets_known_at
;
316 static poly_int64_pod (*offsets_at
)[NUM_ELIMINABLE_REGS
];
318 vec
<reg_equivs_t
, va_gc
> *reg_equivs
;
320 /* Stack of addresses where an rtx has been changed. We can undo the
321 changes by popping items off the stack and restoring the original
322 value at each location.
324 We use this simplistic undo capability rather than copy_rtx as copy_rtx
325 will not make a deep copy of a normally sharable rtx, such as
326 (const (plus (symbol_ref) (const_int))). If such an expression appears
327 as R1 in gen_reload_chain_without_interm_reg_p, then a shared
328 rtx expression would be changed. See PR 42431. */
331 static vec
<rtx_p
> substitute_stack
;
333 /* Number of labels in the current function. */
335 static int num_labels
;
337 static void replace_pseudos_in (rtx
*, machine_mode
, rtx
);
338 static void maybe_fix_stack_asms (void);
339 static void copy_reloads (class insn_chain
*);
340 static void calculate_needs_all_insns (int);
341 static int find_reg (class insn_chain
*, int);
342 static void find_reload_regs (class insn_chain
*);
343 static void select_reload_regs (void);
344 static void delete_caller_save_insns (void);
346 static void spill_failure (rtx_insn
*, enum reg_class
);
347 static void count_spilled_pseudo (int, int, int);
348 static void delete_dead_insn (rtx_insn
*);
349 static void alter_reg (int, int, bool);
350 static void set_label_offsets (rtx
, rtx_insn
*, int);
351 static void check_eliminable_occurrences (rtx
);
352 static void elimination_effects (rtx
, machine_mode
);
353 static rtx
eliminate_regs_1 (rtx
, machine_mode
, rtx
, bool, bool);
354 static int eliminate_regs_in_insn (rtx_insn
*, int);
355 static void update_eliminable_offsets (void);
356 static void mark_not_eliminable (rtx
, const_rtx
, void *);
357 static void set_initial_elim_offsets (void);
358 static bool verify_initial_elim_offsets (void);
359 static void set_initial_label_offsets (void);
360 static void set_offsets_for_label (rtx_insn
*);
361 static void init_eliminable_invariants (rtx_insn
*, bool);
362 static void init_elim_table (void);
363 static void free_reg_equiv (void);
364 static void update_eliminables (HARD_REG_SET
*);
365 static bool update_eliminables_and_spill (void);
366 static void elimination_costs_in_insn (rtx_insn
*);
367 static void spill_hard_reg (unsigned int, int);
368 static int finish_spills (int);
369 static void scan_paradoxical_subregs (rtx
);
370 static void count_pseudo (int);
371 static void order_regs_for_reload (class insn_chain
*);
372 static void reload_as_needed (int);
373 static void forget_old_reloads_1 (rtx
, const_rtx
, void *);
374 static void forget_marked_reloads (regset
);
375 static int reload_reg_class_lower (const void *, const void *);
376 static void mark_reload_reg_in_use (unsigned int, int, enum reload_type
,
378 static void clear_reload_reg_in_use (unsigned int, int, enum reload_type
,
380 static int reload_reg_free_p (unsigned int, int, enum reload_type
);
381 static int reload_reg_free_for_value_p (int, int, int, enum reload_type
,
383 static int free_for_value_p (int, machine_mode
, int, enum reload_type
,
385 static int allocate_reload_reg (class insn_chain
*, int, int);
386 static int conflicts_with_override (rtx
);
387 static void failed_reload (rtx_insn
*, int);
388 static int set_reload_reg (int, int);
389 static void choose_reload_regs_init (class insn_chain
*, rtx
*);
390 static void choose_reload_regs (class insn_chain
*);
391 static void emit_input_reload_insns (class insn_chain
*, struct reload
*,
393 static void emit_output_reload_insns (class insn_chain
*, struct reload
*,
395 static void do_input_reload (class insn_chain
*, struct reload
*, int);
396 static void do_output_reload (class insn_chain
*, struct reload
*, int);
397 static void emit_reload_insns (class insn_chain
*);
398 static void delete_output_reload (rtx_insn
*, int, int, rtx
);
399 static void delete_address_reloads (rtx_insn
*, rtx_insn
*);
400 static void delete_address_reloads_1 (rtx_insn
*, rtx
, rtx_insn
*);
401 static void inc_for_reload (rtx
, rtx
, rtx
, poly_int64
);
402 static void add_auto_inc_notes (rtx_insn
*, rtx
);
403 static void substitute (rtx
*, const_rtx
, rtx
);
404 static bool gen_reload_chain_without_interm_reg_p (int, int);
405 static int reloads_conflict (int, int);
406 static rtx_insn
*gen_reload (rtx
, rtx
, int, enum reload_type
);
407 static rtx_insn
*emit_insn_if_valid_for_reload (rtx
);
409 /* Initialize the reload pass. This is called at the beginning of compilation
410 and may be called again if the target is reinitialized. */
417 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
418 Set spill_indirect_levels to the number of levels such addressing is
419 permitted, zero if it is not permitted at all. */
422 = gen_rtx_MEM (Pmode
,
425 LAST_VIRTUAL_REGISTER
+ 1),
426 gen_int_mode (4, Pmode
)));
427 spill_indirect_levels
= 0;
429 while (memory_address_p (QImode
, tem
))
431 spill_indirect_levels
++;
432 tem
= gen_rtx_MEM (Pmode
, tem
);
435 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
437 tem
= gen_rtx_MEM (Pmode
, gen_rtx_SYMBOL_REF (Pmode
, "foo"));
438 indirect_symref_ok
= memory_address_p (QImode
, tem
);
440 /* See if reg+reg is a valid (and offsettable) address. */
442 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
444 tem
= gen_rtx_PLUS (Pmode
,
445 gen_rtx_REG (Pmode
, HARD_FRAME_POINTER_REGNUM
),
446 gen_rtx_REG (Pmode
, i
));
448 /* This way, we make sure that reg+reg is an offsettable address. */
449 tem
= plus_constant (Pmode
, tem
, 4);
451 for (int mode
= 0; mode
< MAX_MACHINE_MODE
; mode
++)
452 if (!double_reg_address_ok
[mode
]
453 && memory_address_p ((enum machine_mode
)mode
, tem
))
454 double_reg_address_ok
[mode
] = 1;
457 /* Initialize obstack for our rtl allocation. */
458 if (reload_startobj
== NULL
)
460 gcc_obstack_init (&reload_obstack
);
461 reload_startobj
= XOBNEWVAR (&reload_obstack
, char, 0);
464 INIT_REG_SET (&spilled_pseudos
);
465 INIT_REG_SET (&changed_allocation_pseudos
);
466 INIT_REG_SET (&pseudos_counted
);
469 /* List of insn chains that are currently unused. */
470 static class insn_chain
*unused_insn_chains
= 0;
472 /* Allocate an empty insn_chain structure. */
474 new_insn_chain (void)
478 if (unused_insn_chains
== 0)
480 c
= XOBNEW (&reload_obstack
, class insn_chain
);
481 INIT_REG_SET (&c
->live_throughout
);
482 INIT_REG_SET (&c
->dead_or_set
);
486 c
= unused_insn_chains
;
487 unused_insn_chains
= c
->next
;
489 c
->is_caller_save_insn
= 0;
490 c
->need_operand_change
= 0;
496 /* Small utility function to set all regs in hard reg set TO which are
497 allocated to pseudos in regset FROM. */
500 compute_use_by_pseudos (HARD_REG_SET
*to
, regset from
)
503 reg_set_iterator rsi
;
505 EXECUTE_IF_SET_IN_REG_SET (from
, FIRST_PSEUDO_REGISTER
, regno
, rsi
)
507 int r
= reg_renumber
[regno
];
511 /* reload_combine uses the information from DF_LIVE_IN,
512 which might still contain registers that have not
513 actually been allocated since they have an
515 gcc_assert (ira_conflicts_p
|| reload_completed
);
518 add_to_hard_reg_set (to
, PSEUDO_REGNO_MODE (regno
), r
);
522 /* Replace all pseudos found in LOC with their corresponding
526 replace_pseudos_in (rtx
*loc
, machine_mode mem_mode
, rtx usage
)
539 unsigned int regno
= REGNO (x
);
541 if (regno
< FIRST_PSEUDO_REGISTER
)
544 x
= eliminate_regs_1 (x
, mem_mode
, usage
, true, false);
548 replace_pseudos_in (loc
, mem_mode
, usage
);
552 if (reg_equiv_constant (regno
))
553 *loc
= reg_equiv_constant (regno
);
554 else if (reg_equiv_invariant (regno
))
555 *loc
= reg_equiv_invariant (regno
);
556 else if (reg_equiv_mem (regno
))
557 *loc
= reg_equiv_mem (regno
);
558 else if (reg_equiv_address (regno
))
559 *loc
= gen_rtx_MEM (GET_MODE (x
), reg_equiv_address (regno
));
562 gcc_assert (!REG_P (regno_reg_rtx
[regno
])
563 || REGNO (regno_reg_rtx
[regno
]) != regno
);
564 *loc
= regno_reg_rtx
[regno
];
569 else if (code
== MEM
)
571 replace_pseudos_in (& XEXP (x
, 0), GET_MODE (x
), usage
);
575 /* Process each of our operands recursively. */
576 fmt
= GET_RTX_FORMAT (code
);
577 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++, fmt
++)
579 replace_pseudos_in (&XEXP (x
, i
), mem_mode
, usage
);
580 else if (*fmt
== 'E')
581 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
582 replace_pseudos_in (& XVECEXP (x
, i
, j
), mem_mode
, usage
);
585 /* Determine if the current function has an exception receiver block
586 that reaches the exit block via non-exceptional edges */
589 has_nonexceptional_receiver (void)
593 basic_block
*tos
, *worklist
, bb
;
595 /* If we're not optimizing, then just err on the safe side. */
599 /* First determine which blocks can reach exit via normal paths. */
600 tos
= worklist
= XNEWVEC (basic_block
, n_basic_blocks_for_fn (cfun
) + 1);
602 FOR_EACH_BB_FN (bb
, cfun
)
603 bb
->flags
&= ~BB_REACHABLE
;
605 /* Place the exit block on our worklist. */
606 EXIT_BLOCK_PTR_FOR_FN (cfun
)->flags
|= BB_REACHABLE
;
607 *tos
++ = EXIT_BLOCK_PTR_FOR_FN (cfun
);
609 /* Iterate: find everything reachable from what we've already seen. */
610 while (tos
!= worklist
)
614 FOR_EACH_EDGE (e
, ei
, bb
->preds
)
615 if (!(e
->flags
& EDGE_ABNORMAL
))
617 basic_block src
= e
->src
;
619 if (!(src
->flags
& BB_REACHABLE
))
621 src
->flags
|= BB_REACHABLE
;
628 /* Now see if there's a reachable block with an exceptional incoming
630 FOR_EACH_BB_FN (bb
, cfun
)
631 if (bb
->flags
& BB_REACHABLE
&& bb_has_abnormal_pred (bb
))
634 /* No exceptional block reached exit unexceptionally. */
638 /* Grow (or allocate) the REG_EQUIVS array from its current size (which may be
639 zero elements) to MAX_REG_NUM elements.
641 Initialize all new fields to NULL and update REG_EQUIVS_SIZE. */
643 grow_reg_equivs (void)
645 int old_size
= vec_safe_length (reg_equivs
);
646 int max_regno
= max_reg_num ();
650 memset (&ze
, 0, sizeof (reg_equivs_t
));
651 vec_safe_reserve (reg_equivs
, max_regno
);
652 for (i
= old_size
; i
< max_regno
; i
++)
653 reg_equivs
->quick_insert (i
, ze
);
657 /* Global variables used by reload and its subroutines. */
659 /* The current basic block while in calculate_elim_costs_all_insns. */
660 static basic_block elim_bb
;
662 /* Set during calculate_needs if an insn needs register elimination. */
663 static int something_needs_elimination
;
664 /* Set during calculate_needs if an insn needs an operand changed. */
665 static int something_needs_operands_changed
;
666 /* Set by alter_regs if we spilled a register to the stack. */
667 static bool something_was_spilled
;
669 /* Nonzero means we couldn't get enough spill regs. */
672 /* Temporary array of pseudo-register number. */
673 static int *temp_pseudo_reg_arr
;
675 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
676 If that insn didn't set the register (i.e., it copied the register to
677 memory), just delete that insn instead of the equivalencing insn plus
678 anything now dead. If we call delete_dead_insn on that insn, we may
679 delete the insn that actually sets the register if the register dies
680 there and that is incorrect. */
684 for (int i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
686 if (reg_renumber
[i
] < 0 && reg_equiv_init (i
) != 0)
689 for (list
= reg_equiv_init (i
); list
; list
= XEXP (list
, 1))
691 rtx_insn
*equiv_insn
= as_a
<rtx_insn
*> (XEXP (list
, 0));
693 /* If we already deleted the insn or if it may trap, we can't
694 delete it. The latter case shouldn't happen, but can
695 if an insn has a variable address, gets a REG_EH_REGION
696 note added to it, and then gets converted into a load
697 from a constant address. */
698 if (NOTE_P (equiv_insn
)
699 || can_throw_internal (equiv_insn
))
701 else if (reg_set_p (regno_reg_rtx
[i
], PATTERN (equiv_insn
)))
702 delete_dead_insn (equiv_insn
);
704 SET_INSN_DELETED (equiv_insn
);
710 /* Return true if remove_init_insns will delete INSN. */
712 will_delete_init_insn_p (rtx_insn
*insn
)
714 rtx set
= single_set (insn
);
715 if (!set
|| !REG_P (SET_DEST (set
)))
717 unsigned regno
= REGNO (SET_DEST (set
));
719 if (can_throw_internal (insn
))
722 if (regno
< FIRST_PSEUDO_REGISTER
|| reg_renumber
[regno
] >= 0)
725 for (rtx list
= reg_equiv_init (regno
); list
; list
= XEXP (list
, 1))
727 rtx equiv_insn
= XEXP (list
, 0);
728 if (equiv_insn
== insn
)
734 /* Main entry point for the reload pass.
736 FIRST is the first insn of the function being compiled.
738 GLOBAL nonzero means we were called from global_alloc
739 and should attempt to reallocate any pseudoregs that we
740 displace from hard regs we will use for reloads.
741 If GLOBAL is zero, we do not have enough information to do that,
742 so any pseudo reg that is spilled must go to the stack.
744 Return value is TRUE if reload likely left dead insns in the
745 stream and a DCE pass should be run to elimiante them. Else the
746 return value is FALSE. */
749 reload (rtx_insn
*first
, int global
)
753 struct elim_table
*ep
;
757 /* Make sure even insns with volatile mem refs are recognizable. */
762 reload_firstobj
= XOBNEWVAR (&reload_obstack
, char, 0);
764 /* Make sure that the last insn in the chain
765 is not something that needs reloading. */
766 emit_note (NOTE_INSN_DELETED
);
768 /* Enable find_equiv_reg to distinguish insns made by reload. */
769 reload_first_uid
= get_max_uid ();
771 /* Initialize the secondary memory table. */
772 clear_secondary_mem ();
774 /* We don't have a stack slot for any spill reg yet. */
775 memset (spill_stack_slot
, 0, sizeof spill_stack_slot
);
776 memset (spill_stack_slot_width
, 0, sizeof spill_stack_slot_width
);
778 /* Initialize the save area information for caller-save, in case some
782 /* Compute which hard registers are now in use
783 as homes for pseudo registers.
784 This is done here rather than (eg) in global_alloc
785 because this point is reached even if not optimizing. */
786 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
789 /* A function that has a nonlocal label that can reach the exit
790 block via non-exceptional paths must save all call-saved
792 if (cfun
->has_nonlocal_label
793 && has_nonexceptional_receiver ())
794 crtl
->saves_all_registers
= 1;
796 if (crtl
->saves_all_registers
)
797 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
798 if (! call_used_regs
[i
] && ! fixed_regs
[i
] && ! LOCAL_REGNO (i
))
799 df_set_regs_ever_live (i
, true);
801 /* Find all the pseudo registers that didn't get hard regs
802 but do have known equivalent constants or memory slots.
803 These include parameters (known equivalent to parameter slots)
804 and cse'd or loop-moved constant memory addresses.
806 Record constant equivalents in reg_equiv_constant
807 so they will be substituted by find_reloads.
808 Record memory equivalents in reg_mem_equiv so they can
809 be substituted eventually by altering the REG-rtx's. */
812 reg_old_renumber
= XCNEWVEC (short, max_regno
);
813 memcpy (reg_old_renumber
, reg_renumber
, max_regno
* sizeof (short));
814 pseudo_forbidden_regs
= XNEWVEC (HARD_REG_SET
, max_regno
);
815 pseudo_previous_regs
= XCNEWVEC (HARD_REG_SET
, max_regno
);
817 CLEAR_HARD_REG_SET (bad_spill_regs_global
);
819 init_eliminable_invariants (first
, true);
822 /* Alter each pseudo-reg rtx to contain its hard reg number. Assign
823 stack slots to the pseudos that lack hard regs or equivalents.
824 Do not touch virtual registers. */
826 temp_pseudo_reg_arr
= XNEWVEC (int, max_regno
- LAST_VIRTUAL_REGISTER
- 1);
827 for (n
= 0, i
= LAST_VIRTUAL_REGISTER
+ 1; i
< max_regno
; i
++)
828 temp_pseudo_reg_arr
[n
++] = i
;
831 /* Ask IRA to order pseudo-registers for better stack slot
833 ira_sort_regnos_for_alter_reg (temp_pseudo_reg_arr
, n
, reg_max_ref_mode
);
835 for (i
= 0; i
< n
; i
++)
836 alter_reg (temp_pseudo_reg_arr
[i
], -1, false);
838 /* If we have some registers we think can be eliminated, scan all insns to
839 see if there is an insn that sets one of these registers to something
840 other than itself plus a constant. If so, the register cannot be
841 eliminated. Doing this scan here eliminates an extra pass through the
842 main reload loop in the most common case where register elimination
844 for (insn
= first
; insn
&& num_eliminable
; insn
= NEXT_INSN (insn
))
846 note_pattern_stores (PATTERN (insn
), mark_not_eliminable
, NULL
);
848 maybe_fix_stack_asms ();
850 insns_need_reload
= 0;
851 something_needs_elimination
= 0;
853 /* Initialize to -1, which means take the first spill register. */
856 /* Spill any hard regs that we know we can't eliminate. */
857 CLEAR_HARD_REG_SET (used_spill_regs
);
858 /* There can be multiple ways to eliminate a register;
859 they should be listed adjacently.
860 Elimination for any register fails only if all possible ways fail. */
861 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; )
864 int can_eliminate
= 0;
867 can_eliminate
|= ep
->can_eliminate
;
870 while (ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
] && ep
->from
== from
);
872 spill_hard_reg (from
, 1);
875 if (!HARD_FRAME_POINTER_IS_FRAME_POINTER
&& frame_pointer_needed
)
876 spill_hard_reg (HARD_FRAME_POINTER_REGNUM
, 1);
878 finish_spills (global
);
880 /* From now on, we may need to generate moves differently. We may also
881 allow modifications of insns which cause them to not be recognized.
882 Any such modifications will be cleaned up during reload itself. */
883 reload_in_progress
= 1;
885 /* This loop scans the entire function each go-round
886 and repeats until one repetition spills no additional hard regs. */
889 int something_changed
;
890 poly_int64 starting_frame_size
;
892 starting_frame_size
= get_frame_size ();
893 something_was_spilled
= false;
895 set_initial_elim_offsets ();
896 set_initial_label_offsets ();
898 /* For each pseudo register that has an equivalent location defined,
899 try to eliminate any eliminable registers (such as the frame pointer)
900 assuming initial offsets for the replacement register, which
903 If the resulting location is directly addressable, substitute
904 the MEM we just got directly for the old REG.
906 If it is not addressable but is a constant or the sum of a hard reg
907 and constant, it is probably not addressable because the constant is
908 out of range, in that case record the address; we will generate
909 hairy code to compute the address in a register each time it is
910 needed. Similarly if it is a hard register, but one that is not
911 valid as an address register.
913 If the location is not addressable, but does not have one of the
914 above forms, assign a stack slot. We have to do this to avoid the
915 potential of producing lots of reloads if, e.g., a location involves
916 a pseudo that didn't get a hard register and has an equivalent memory
917 location that also involves a pseudo that didn't get a hard register.
919 Perhaps at some point we will improve reload_when_needed handling
920 so this problem goes away. But that's very hairy. */
922 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
923 if (reg_renumber
[i
] < 0 && reg_equiv_memory_loc (i
))
925 rtx x
= eliminate_regs (reg_equiv_memory_loc (i
), VOIDmode
,
928 if (strict_memory_address_addr_space_p
929 (GET_MODE (regno_reg_rtx
[i
]), XEXP (x
, 0),
931 reg_equiv_mem (i
) = x
, reg_equiv_address (i
) = 0;
932 else if (CONSTANT_P (XEXP (x
, 0))
933 || (REG_P (XEXP (x
, 0))
934 && REGNO (XEXP (x
, 0)) < FIRST_PSEUDO_REGISTER
)
935 || (GET_CODE (XEXP (x
, 0)) == PLUS
936 && REG_P (XEXP (XEXP (x
, 0), 0))
937 && (REGNO (XEXP (XEXP (x
, 0), 0))
938 < FIRST_PSEUDO_REGISTER
)
939 && CONSTANT_P (XEXP (XEXP (x
, 0), 1))))
940 reg_equiv_address (i
) = XEXP (x
, 0), reg_equiv_mem (i
) = 0;
943 /* Make a new stack slot. Then indicate that something
944 changed so we go back and recompute offsets for
945 eliminable registers because the allocation of memory
946 below might change some offset. reg_equiv_{mem,address}
947 will be set up for this pseudo on the next pass around
949 reg_equiv_memory_loc (i
) = 0;
950 reg_equiv_init (i
) = 0;
951 alter_reg (i
, -1, true);
955 if (caller_save_needed
)
958 if (maybe_ne (starting_frame_size
, 0) && crtl
->stack_alignment_needed
)
960 /* If we have a stack frame, we must align it now. The
961 stack size may be a part of the offset computation for
962 register elimination. So if this changes the stack size,
963 then repeat the elimination bookkeeping. We don't
964 realign when there is no stack, as that will cause a
965 stack frame when none is needed should
966 TARGET_STARTING_FRAME_OFFSET not be already aligned to
968 assign_stack_local (BLKmode
, 0, crtl
->stack_alignment_needed
);
970 /* If we allocated another stack slot, redo elimination bookkeeping. */
971 if (something_was_spilled
972 || maybe_ne (starting_frame_size
, get_frame_size ()))
974 if (update_eliminables_and_spill ())
979 if (caller_save_needed
)
981 save_call_clobbered_regs ();
982 /* That might have allocated new insn_chain structures. */
983 reload_firstobj
= XOBNEWVAR (&reload_obstack
, char, 0);
986 calculate_needs_all_insns (global
);
988 if (! ira_conflicts_p
)
989 /* Don't do it for IRA. We need this info because we don't
990 change live_throughout and dead_or_set for chains when IRA
992 CLEAR_REG_SET (&spilled_pseudos
);
994 something_changed
= 0;
996 /* If we allocated any new memory locations, make another pass
997 since it might have changed elimination offsets. */
998 if (something_was_spilled
999 || maybe_ne (starting_frame_size
, get_frame_size ()))
1000 something_changed
= 1;
1002 /* Even if the frame size remained the same, we might still have
1003 changed elimination offsets, e.g. if find_reloads called
1004 force_const_mem requiring the back end to allocate a constant
1005 pool base register that needs to be saved on the stack. */
1006 else if (!verify_initial_elim_offsets ())
1007 something_changed
= 1;
1009 if (update_eliminables_and_spill ())
1012 something_changed
= 1;
1016 select_reload_regs ();
1019 if (insns_need_reload
)
1020 something_changed
|= finish_spills (global
);
1023 if (! something_changed
)
1026 if (caller_save_needed
)
1027 delete_caller_save_insns ();
1029 obstack_free (&reload_obstack
, reload_firstobj
);
1032 /* If global-alloc was run, notify it of any register eliminations we have
1035 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
1036 if (ep
->can_eliminate
)
1037 mark_elimination (ep
->from
, ep
->to
);
1039 remove_init_insns ();
1041 /* Use the reload registers where necessary
1042 by generating move instructions to move the must-be-register
1043 values into or out of the reload registers. */
1045 if (insns_need_reload
!= 0 || something_needs_elimination
1046 || something_needs_operands_changed
)
1048 poly_int64 old_frame_size
= get_frame_size ();
1050 reload_as_needed (global
);
1052 gcc_assert (known_eq (old_frame_size
, get_frame_size ()));
1054 gcc_assert (verify_initial_elim_offsets ());
1057 /* If we were able to eliminate the frame pointer, show that it is no
1058 longer live at the start of any basic block. If it ls live by
1059 virtue of being in a pseudo, that pseudo will be marked live
1060 and hence the frame pointer will be known to be live via that
1063 if (! frame_pointer_needed
)
1064 FOR_EACH_BB_FN (bb
, cfun
)
1065 bitmap_clear_bit (df_get_live_in (bb
), HARD_FRAME_POINTER_REGNUM
);
1067 /* Come here (with failure set nonzero) if we can't get enough spill
1071 CLEAR_REG_SET (&changed_allocation_pseudos
);
1072 CLEAR_REG_SET (&spilled_pseudos
);
1073 reload_in_progress
= 0;
1075 /* Now eliminate all pseudo regs by modifying them into
1076 their equivalent memory references.
1077 The REG-rtx's for the pseudos are modified in place,
1078 so all insns that used to refer to them now refer to memory.
1080 For a reg that has a reg_equiv_address, all those insns
1081 were changed by reloading so that no insns refer to it any longer;
1082 but the DECL_RTL of a variable decl may refer to it,
1083 and if so this causes the debugging info to mention the variable. */
1085 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
1089 if (reg_equiv_mem (i
))
1090 addr
= XEXP (reg_equiv_mem (i
), 0);
1092 if (reg_equiv_address (i
))
1093 addr
= reg_equiv_address (i
);
1097 if (reg_renumber
[i
] < 0)
1099 rtx reg
= regno_reg_rtx
[i
];
1101 REG_USERVAR_P (reg
) = 0;
1102 PUT_CODE (reg
, MEM
);
1103 XEXP (reg
, 0) = addr
;
1104 if (reg_equiv_memory_loc (i
))
1105 MEM_COPY_ATTRIBUTES (reg
, reg_equiv_memory_loc (i
));
1107 MEM_ATTRS (reg
) = 0;
1108 MEM_NOTRAP_P (reg
) = 1;
1110 else if (reg_equiv_mem (i
))
1111 XEXP (reg_equiv_mem (i
), 0) = addr
;
1114 /* We don't want complex addressing modes in debug insns
1115 if simpler ones will do, so delegitimize equivalences
1117 if (MAY_HAVE_DEBUG_BIND_INSNS
&& reg_renumber
[i
] < 0)
1119 rtx reg
= regno_reg_rtx
[i
];
1123 if (reg_equiv_constant (i
))
1124 equiv
= reg_equiv_constant (i
);
1125 else if (reg_equiv_invariant (i
))
1126 equiv
= reg_equiv_invariant (i
);
1127 else if (reg
&& MEM_P (reg
))
1128 equiv
= targetm
.delegitimize_address (reg
);
1129 else if (reg
&& REG_P (reg
) && (int)REGNO (reg
) != i
)
1135 for (use
= DF_REG_USE_CHAIN (i
); use
; use
= next
)
1137 insn
= DF_REF_INSN (use
);
1139 /* Make sure the next ref is for a different instruction,
1140 so that we're not affected by the rescan. */
1141 next
= DF_REF_NEXT_REG (use
);
1142 while (next
&& DF_REF_INSN (next
) == insn
)
1143 next
= DF_REF_NEXT_REG (next
);
1145 if (DEBUG_BIND_INSN_P (insn
))
1149 INSN_VAR_LOCATION_LOC (insn
) = gen_rtx_UNKNOWN_VAR_LOC ();
1150 df_insn_rescan_debug_internal (insn
);
1153 INSN_VAR_LOCATION_LOC (insn
)
1154 = simplify_replace_rtx (INSN_VAR_LOCATION_LOC (insn
),
1161 /* We must set reload_completed now since the cleanup_subreg_operands call
1162 below will re-recognize each insn and reload may have generated insns
1163 which are only valid during and after reload. */
1164 reload_completed
= 1;
1166 /* Make a pass over all the insns and delete all USEs which we inserted
1167 only to tag a REG_EQUAL note on them. Remove all REG_DEAD and REG_UNUSED
1168 notes. Delete all CLOBBER insns, except those that refer to the return
1169 value and the special mem:BLK CLOBBERs added to prevent the scheduler
1170 from misarranging variable-array code, and simplify (subreg (reg))
1171 operands. Strip and regenerate REG_INC notes that may have been moved
1174 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
1180 replace_pseudos_in (& CALL_INSN_FUNCTION_USAGE (insn
),
1181 VOIDmode
, CALL_INSN_FUNCTION_USAGE (insn
));
1183 if ((GET_CODE (PATTERN (insn
)) == USE
1184 /* We mark with QImode USEs introduced by reload itself. */
1185 && (GET_MODE (insn
) == QImode
1186 || find_reg_note (insn
, REG_EQUAL
, NULL_RTX
)))
1187 || (GET_CODE (PATTERN (insn
)) == CLOBBER
1188 && (!MEM_P (XEXP (PATTERN (insn
), 0))
1189 || GET_MODE (XEXP (PATTERN (insn
), 0)) != BLKmode
1190 || (GET_CODE (XEXP (XEXP (PATTERN (insn
), 0), 0)) != SCRATCH
1191 && XEXP (XEXP (PATTERN (insn
), 0), 0)
1192 != stack_pointer_rtx
))
1193 && (!REG_P (XEXP (PATTERN (insn
), 0))
1194 || ! REG_FUNCTION_VALUE_P (XEXP (PATTERN (insn
), 0)))))
1200 /* Some CLOBBERs may survive until here and still reference unassigned
1201 pseudos with const equivalent, which may in turn cause ICE in later
1202 passes if the reference remains in place. */
1203 if (GET_CODE (PATTERN (insn
)) == CLOBBER
)
1204 replace_pseudos_in (& XEXP (PATTERN (insn
), 0),
1205 VOIDmode
, PATTERN (insn
));
1207 /* Discard obvious no-ops, even without -O. This optimization
1208 is fast and doesn't interfere with debugging. */
1209 if (NONJUMP_INSN_P (insn
)
1210 && GET_CODE (PATTERN (insn
)) == SET
1211 && REG_P (SET_SRC (PATTERN (insn
)))
1212 && REG_P (SET_DEST (PATTERN (insn
)))
1213 && (REGNO (SET_SRC (PATTERN (insn
)))
1214 == REGNO (SET_DEST (PATTERN (insn
)))))
1220 pnote
= ®_NOTES (insn
);
1223 if (REG_NOTE_KIND (*pnote
) == REG_DEAD
1224 || REG_NOTE_KIND (*pnote
) == REG_UNUSED
1225 || REG_NOTE_KIND (*pnote
) == REG_INC
)
1226 *pnote
= XEXP (*pnote
, 1);
1228 pnote
= &XEXP (*pnote
, 1);
1232 add_auto_inc_notes (insn
, PATTERN (insn
));
1234 /* Simplify (subreg (reg)) if it appears as an operand. */
1235 cleanup_subreg_operands (insn
);
1237 /* Clean up invalid ASMs so that they don't confuse later passes.
1239 if (asm_noperands (PATTERN (insn
)) >= 0)
1241 extract_insn (insn
);
1242 if (!constrain_operands (1, get_enabled_alternatives (insn
)))
1244 error_for_asm (insn
,
1245 "%<asm%> operand has impossible constraints");
1252 free (temp_pseudo_reg_arr
);
1254 /* Indicate that we no longer have known memory locations or constants. */
1257 free (reg_max_ref_mode
);
1258 free (reg_old_renumber
);
1259 free (pseudo_previous_regs
);
1260 free (pseudo_forbidden_regs
);
1262 CLEAR_HARD_REG_SET (used_spill_regs
);
1263 for (i
= 0; i
< n_spills
; i
++)
1264 SET_HARD_REG_BIT (used_spill_regs
, spill_regs
[i
]);
1266 /* Free all the insn_chain structures at once. */
1267 obstack_free (&reload_obstack
, reload_startobj
);
1268 unused_insn_chains
= 0;
1270 inserted
= fixup_abnormal_edges ();
1272 /* We've possibly turned single trapping insn into multiple ones. */
1273 if (cfun
->can_throw_non_call_exceptions
)
1275 auto_sbitmap
blocks (last_basic_block_for_fn (cfun
));
1276 bitmap_ones (blocks
);
1277 find_many_sub_basic_blocks (blocks
);
1281 commit_edge_insertions ();
1283 /* Replacing pseudos with their memory equivalents might have
1284 created shared rtx. Subsequent passes would get confused
1285 by this, so unshare everything here. */
1286 unshare_all_rtl_again (first
);
1288 #ifdef STACK_BOUNDARY
1289 /* init_emit has set the alignment of the hard frame pointer
1290 to STACK_BOUNDARY. It is very likely no longer valid if
1291 the hard frame pointer was used for register allocation. */
1292 if (!frame_pointer_needed
)
1293 REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM
) = BITS_PER_UNIT
;
1296 substitute_stack
.release ();
1298 gcc_assert (bitmap_empty_p (&spilled_pseudos
));
1300 reload_completed
= !failure
;
1305 /* Yet another special case. Unfortunately, reg-stack forces people to
1306 write incorrect clobbers in asm statements. These clobbers must not
1307 cause the register to appear in bad_spill_regs, otherwise we'll call
1308 fatal_insn later. We clear the corresponding regnos in the live
1309 register sets to avoid this.
1310 The whole thing is rather sick, I'm afraid. */
1313 maybe_fix_stack_asms (void)
1316 const char *constraints
[MAX_RECOG_OPERANDS
];
1317 machine_mode operand_mode
[MAX_RECOG_OPERANDS
];
1318 class insn_chain
*chain
;
1320 for (chain
= reload_insn_chain
; chain
!= 0; chain
= chain
->next
)
1323 HARD_REG_SET clobbered
, allowed
;
1326 if (! INSN_P (chain
->insn
)
1327 || (noperands
= asm_noperands (PATTERN (chain
->insn
))) < 0)
1329 pat
= PATTERN (chain
->insn
);
1330 if (GET_CODE (pat
) != PARALLEL
)
1333 CLEAR_HARD_REG_SET (clobbered
);
1334 CLEAR_HARD_REG_SET (allowed
);
1336 /* First, make a mask of all stack regs that are clobbered. */
1337 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
1339 rtx t
= XVECEXP (pat
, 0, i
);
1340 if (GET_CODE (t
) == CLOBBER
&& STACK_REG_P (XEXP (t
, 0)))
1341 SET_HARD_REG_BIT (clobbered
, REGNO (XEXP (t
, 0)));
1342 /* CLOBBER_HIGH is only supported for LRA. */
1343 gcc_assert (GET_CODE (t
) != CLOBBER_HIGH
);
1346 /* Get the operand values and constraints out of the insn. */
1347 decode_asm_operands (pat
, recog_data
.operand
, recog_data
.operand_loc
,
1348 constraints
, operand_mode
, NULL
);
1350 /* For every operand, see what registers are allowed. */
1351 for (i
= 0; i
< noperands
; i
++)
1353 const char *p
= constraints
[i
];
1354 /* For every alternative, we compute the class of registers allowed
1355 for reloading in CLS, and merge its contents into the reg set
1357 int cls
= (int) NO_REGS
;
1363 if (c
== '\0' || c
== ',' || c
== '#')
1365 /* End of one alternative - mark the regs in the current
1366 class, and reset the class. */
1367 allowed
|= reg_class_contents
[cls
];
1373 } while (c
!= '\0' && c
!= ',');
1382 cls
= (int) reg_class_subunion
[cls
][(int) GENERAL_REGS
];
1386 enum constraint_num cn
= lookup_constraint (p
);
1387 if (insn_extra_address_constraint (cn
))
1388 cls
= (int) reg_class_subunion
[cls
]
1389 [(int) base_reg_class (VOIDmode
, ADDR_SPACE_GENERIC
,
1392 cls
= (int) reg_class_subunion
[cls
]
1393 [reg_class_for_constraint (cn
)];
1396 p
+= CONSTRAINT_LEN (c
, p
);
1399 /* Those of the registers which are clobbered, but allowed by the
1400 constraints, must be usable as reload registers. So clear them
1401 out of the life information. */
1402 allowed
&= clobbered
;
1403 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1404 if (TEST_HARD_REG_BIT (allowed
, i
))
1406 CLEAR_REGNO_REG_SET (&chain
->live_throughout
, i
);
1407 CLEAR_REGNO_REG_SET (&chain
->dead_or_set
, i
);
1414 /* Copy the global variables n_reloads and rld into the corresponding elts
1417 copy_reloads (class insn_chain
*chain
)
1419 chain
->n_reloads
= n_reloads
;
1420 chain
->rld
= XOBNEWVEC (&reload_obstack
, struct reload
, n_reloads
);
1421 memcpy (chain
->rld
, rld
, n_reloads
* sizeof (struct reload
));
1422 reload_insn_firstobj
= XOBNEWVAR (&reload_obstack
, char, 0);
1425 /* Walk the chain of insns, and determine for each whether it needs reloads
1426 and/or eliminations. Build the corresponding insns_need_reload list, and
1427 set something_needs_elimination as appropriate. */
1429 calculate_needs_all_insns (int global
)
1431 class insn_chain
**pprev_reload
= &insns_need_reload
;
1432 class insn_chain
*chain
, *next
= 0;
1434 something_needs_elimination
= 0;
1436 reload_insn_firstobj
= XOBNEWVAR (&reload_obstack
, char, 0);
1437 for (chain
= reload_insn_chain
; chain
!= 0; chain
= next
)
1439 rtx_insn
*insn
= chain
->insn
;
1443 /* Clear out the shortcuts. */
1444 chain
->n_reloads
= 0;
1445 chain
->need_elim
= 0;
1446 chain
->need_reload
= 0;
1447 chain
->need_operand_change
= 0;
1449 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1450 include REG_LABEL_OPERAND and REG_LABEL_TARGET), we need to see
1451 what effects this has on the known offsets at labels. */
1453 if (LABEL_P (insn
) || JUMP_P (insn
) || JUMP_TABLE_DATA_P (insn
)
1454 || (INSN_P (insn
) && REG_NOTES (insn
) != 0))
1455 set_label_offsets (insn
, insn
, 0);
1459 rtx old_body
= PATTERN (insn
);
1460 int old_code
= INSN_CODE (insn
);
1461 rtx old_notes
= REG_NOTES (insn
);
1462 int did_elimination
= 0;
1463 int operands_changed
= 0;
1465 /* Skip insns that only set an equivalence. */
1466 if (will_delete_init_insn_p (insn
))
1469 /* If needed, eliminate any eliminable registers. */
1470 if (num_eliminable
|| num_eliminable_invariants
)
1471 did_elimination
= eliminate_regs_in_insn (insn
, 0);
1473 /* Analyze the instruction. */
1474 operands_changed
= find_reloads (insn
, 0, spill_indirect_levels
,
1475 global
, spill_reg_order
);
1477 /* If a no-op set needs more than one reload, this is likely
1478 to be something that needs input address reloads. We
1479 can't get rid of this cleanly later, and it is of no use
1480 anyway, so discard it now.
1481 We only do this when expensive_optimizations is enabled,
1482 since this complements reload inheritance / output
1483 reload deletion, and it can make debugging harder. */
1484 if (flag_expensive_optimizations
&& n_reloads
> 1)
1486 rtx set
= single_set (insn
);
1489 ((SET_SRC (set
) == SET_DEST (set
)
1490 && REG_P (SET_SRC (set
))
1491 && REGNO (SET_SRC (set
)) >= FIRST_PSEUDO_REGISTER
)
1492 || (REG_P (SET_SRC (set
)) && REG_P (SET_DEST (set
))
1493 && reg_renumber
[REGNO (SET_SRC (set
))] < 0
1494 && reg_renumber
[REGNO (SET_DEST (set
))] < 0
1495 && reg_equiv_memory_loc (REGNO (SET_SRC (set
))) != NULL
1496 && reg_equiv_memory_loc (REGNO (SET_DEST (set
))) != NULL
1497 && rtx_equal_p (reg_equiv_memory_loc (REGNO (SET_SRC (set
))),
1498 reg_equiv_memory_loc (REGNO (SET_DEST (set
)))))))
1500 if (ira_conflicts_p
)
1501 /* Inform IRA about the insn deletion. */
1502 ira_mark_memory_move_deletion (REGNO (SET_DEST (set
)),
1503 REGNO (SET_SRC (set
)));
1505 /* Delete it from the reload chain. */
1507 chain
->prev
->next
= next
;
1509 reload_insn_chain
= next
;
1511 next
->prev
= chain
->prev
;
1512 chain
->next
= unused_insn_chains
;
1513 unused_insn_chains
= chain
;
1518 update_eliminable_offsets ();
1520 /* Remember for later shortcuts which insns had any reloads or
1521 register eliminations. */
1522 chain
->need_elim
= did_elimination
;
1523 chain
->need_reload
= n_reloads
> 0;
1524 chain
->need_operand_change
= operands_changed
;
1526 /* Discard any register replacements done. */
1527 if (did_elimination
)
1529 obstack_free (&reload_obstack
, reload_insn_firstobj
);
1530 PATTERN (insn
) = old_body
;
1531 INSN_CODE (insn
) = old_code
;
1532 REG_NOTES (insn
) = old_notes
;
1533 something_needs_elimination
= 1;
1536 something_needs_operands_changed
|= operands_changed
;
1540 copy_reloads (chain
);
1541 *pprev_reload
= chain
;
1542 pprev_reload
= &chain
->next_need_reload
;
1549 /* This function is called from the register allocator to set up estimates
1550 for the cost of eliminating pseudos which have REG_EQUIV equivalences to
1551 an invariant. The structure is similar to calculate_needs_all_insns. */
1554 calculate_elim_costs_all_insns (void)
1556 int *reg_equiv_init_cost
;
1560 reg_equiv_init_cost
= XCNEWVEC (int, max_regno
);
1562 init_eliminable_invariants (get_insns (), false);
1564 set_initial_elim_offsets ();
1565 set_initial_label_offsets ();
1567 FOR_EACH_BB_FN (bb
, cfun
)
1572 FOR_BB_INSNS (bb
, insn
)
1574 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1575 include REG_LABEL_OPERAND and REG_LABEL_TARGET), we need to see
1576 what effects this has on the known offsets at labels. */
1578 if (LABEL_P (insn
) || JUMP_P (insn
) || JUMP_TABLE_DATA_P (insn
)
1579 || (INSN_P (insn
) && REG_NOTES (insn
) != 0))
1580 set_label_offsets (insn
, insn
, 0);
1584 rtx set
= single_set (insn
);
1586 /* Skip insns that only set an equivalence. */
1587 if (set
&& REG_P (SET_DEST (set
))
1588 && reg_renumber
[REGNO (SET_DEST (set
))] < 0
1589 && (reg_equiv_constant (REGNO (SET_DEST (set
)))
1590 || reg_equiv_invariant (REGNO (SET_DEST (set
)))))
1592 unsigned regno
= REGNO (SET_DEST (set
));
1593 rtx_insn_list
*init
= reg_equiv_init (regno
);
1596 rtx t
= eliminate_regs_1 (SET_SRC (set
), VOIDmode
, insn
,
1598 machine_mode mode
= GET_MODE (SET_DEST (set
));
1599 int cost
= set_src_cost (t
, mode
,
1600 optimize_bb_for_speed_p (bb
));
1601 int freq
= REG_FREQ_FROM_BB (bb
);
1603 reg_equiv_init_cost
[regno
] = cost
* freq
;
1607 /* If needed, eliminate any eliminable registers. */
1608 if (num_eliminable
|| num_eliminable_invariants
)
1609 elimination_costs_in_insn (insn
);
1612 update_eliminable_offsets ();
1616 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
1618 if (reg_equiv_invariant (i
))
1620 if (reg_equiv_init (i
))
1622 int cost
= reg_equiv_init_cost
[i
];
1625 "Reg %d has equivalence, initial gains %d\n", i
, cost
);
1627 ira_adjust_equiv_reg_cost (i
, cost
);
1633 "Reg %d had equivalence, but can't be eliminated\n",
1635 ira_adjust_equiv_reg_cost (i
, 0);
1640 free (reg_equiv_init_cost
);
1641 free (offsets_known_at
);
1644 offsets_known_at
= NULL
;
1647 /* Comparison function for qsort to decide which of two reloads
1648 should be handled first. *P1 and *P2 are the reload numbers. */
1651 reload_reg_class_lower (const void *r1p
, const void *r2p
)
1653 int r1
= *(const short *) r1p
, r2
= *(const short *) r2p
;
1656 /* Consider required reloads before optional ones. */
1657 t
= rld
[r1
].optional
- rld
[r2
].optional
;
1661 /* Count all solitary classes before non-solitary ones. */
1662 t
= ((reg_class_size
[(int) rld
[r2
].rclass
] == 1)
1663 - (reg_class_size
[(int) rld
[r1
].rclass
] == 1));
1667 /* Aside from solitaires, consider all multi-reg groups first. */
1668 t
= rld
[r2
].nregs
- rld
[r1
].nregs
;
1672 /* Consider reloads in order of increasing reg-class number. */
1673 t
= (int) rld
[r1
].rclass
- (int) rld
[r2
].rclass
;
1677 /* If reloads are equally urgent, sort by reload number,
1678 so that the results of qsort leave nothing to chance. */
1682 /* The cost of spilling each hard reg. */
1683 static int spill_cost
[FIRST_PSEUDO_REGISTER
];
1685 /* When spilling multiple hard registers, we use SPILL_COST for the first
1686 spilled hard reg and SPILL_ADD_COST for subsequent regs. SPILL_ADD_COST
1687 only the first hard reg for a multi-reg pseudo. */
1688 static int spill_add_cost
[FIRST_PSEUDO_REGISTER
];
1690 /* Map of hard regno to pseudo regno currently occupying the hard
1692 static int hard_regno_to_pseudo_regno
[FIRST_PSEUDO_REGISTER
];
1694 /* Update the spill cost arrays, considering that pseudo REG is live. */
1697 count_pseudo (int reg
)
1699 int freq
= REG_FREQ (reg
);
1700 int r
= reg_renumber
[reg
];
1703 /* Ignore spilled pseudo-registers which can be here only if IRA is used. */
1704 if (ira_conflicts_p
&& r
< 0)
1707 if (REGNO_REG_SET_P (&pseudos_counted
, reg
)
1708 || REGNO_REG_SET_P (&spilled_pseudos
, reg
))
1711 SET_REGNO_REG_SET (&pseudos_counted
, reg
);
1713 gcc_assert (r
>= 0);
1715 spill_add_cost
[r
] += freq
;
1716 nregs
= hard_regno_nregs (r
, PSEUDO_REGNO_MODE (reg
));
1719 hard_regno_to_pseudo_regno
[r
+ nregs
] = reg
;
1720 spill_cost
[r
+ nregs
] += freq
;
1724 /* Calculate the SPILL_COST and SPILL_ADD_COST arrays and determine the
1725 contents of BAD_SPILL_REGS for the insn described by CHAIN. */
1728 order_regs_for_reload (class insn_chain
*chain
)
1731 HARD_REG_SET used_by_pseudos
;
1732 HARD_REG_SET used_by_pseudos2
;
1733 reg_set_iterator rsi
;
1735 bad_spill_regs
= fixed_reg_set
;
1737 memset (spill_cost
, 0, sizeof spill_cost
);
1738 memset (spill_add_cost
, 0, sizeof spill_add_cost
);
1739 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1740 hard_regno_to_pseudo_regno
[i
] = -1;
1742 /* Count number of uses of each hard reg by pseudo regs allocated to it
1743 and then order them by decreasing use. First exclude hard registers
1744 that are live in or across this insn. */
1746 REG_SET_TO_HARD_REG_SET (used_by_pseudos
, &chain
->live_throughout
);
1747 REG_SET_TO_HARD_REG_SET (used_by_pseudos2
, &chain
->dead_or_set
);
1748 bad_spill_regs
|= used_by_pseudos
;
1749 bad_spill_regs
|= used_by_pseudos2
;
1751 /* Now find out which pseudos are allocated to it, and update
1753 CLEAR_REG_SET (&pseudos_counted
);
1755 EXECUTE_IF_SET_IN_REG_SET
1756 (&chain
->live_throughout
, FIRST_PSEUDO_REGISTER
, i
, rsi
)
1760 EXECUTE_IF_SET_IN_REG_SET
1761 (&chain
->dead_or_set
, FIRST_PSEUDO_REGISTER
, i
, rsi
)
1765 CLEAR_REG_SET (&pseudos_counted
);
1768 /* Vector of reload-numbers showing the order in which the reloads should
1770 static short reload_order
[MAX_RELOADS
];
1772 /* This is used to keep track of the spill regs used in one insn. */
1773 static HARD_REG_SET used_spill_regs_local
;
1775 /* We decided to spill hard register SPILLED, which has a size of
1776 SPILLED_NREGS. Determine how pseudo REG, which is live during the insn,
1777 is affected. We will add it to SPILLED_PSEUDOS if necessary, and we will
1778 update SPILL_COST/SPILL_ADD_COST. */
1781 count_spilled_pseudo (int spilled
, int spilled_nregs
, int reg
)
1783 int freq
= REG_FREQ (reg
);
1784 int r
= reg_renumber
[reg
];
1787 /* Ignore spilled pseudo-registers which can be here only if IRA is used. */
1788 if (ira_conflicts_p
&& r
< 0)
1791 gcc_assert (r
>= 0);
1793 nregs
= hard_regno_nregs (r
, PSEUDO_REGNO_MODE (reg
));
1795 if (REGNO_REG_SET_P (&spilled_pseudos
, reg
)
1796 || spilled
+ spilled_nregs
<= r
|| r
+ nregs
<= spilled
)
1799 SET_REGNO_REG_SET (&spilled_pseudos
, reg
);
1801 spill_add_cost
[r
] -= freq
;
1804 hard_regno_to_pseudo_regno
[r
+ nregs
] = -1;
1805 spill_cost
[r
+ nregs
] -= freq
;
1809 /* Find reload register to use for reload number ORDER. */
1812 find_reg (class insn_chain
*chain
, int order
)
1814 int rnum
= reload_order
[order
];
1815 struct reload
*rl
= rld
+ rnum
;
1816 int best_cost
= INT_MAX
;
1818 unsigned int i
, j
, n
;
1820 HARD_REG_SET not_usable
;
1821 HARD_REG_SET used_by_other_reload
;
1822 reg_set_iterator rsi
;
1823 static int regno_pseudo_regs
[FIRST_PSEUDO_REGISTER
];
1824 static int best_regno_pseudo_regs
[FIRST_PSEUDO_REGISTER
];
1826 not_usable
= bad_spill_regs
| bad_spill_regs_global
;
1827 IOR_COMPL_HARD_REG_SET (not_usable
, reg_class_contents
[rl
->rclass
]);
1829 CLEAR_HARD_REG_SET (used_by_other_reload
);
1830 for (k
= 0; k
< order
; k
++)
1832 int other
= reload_order
[k
];
1834 if (rld
[other
].regno
>= 0 && reloads_conflict (other
, rnum
))
1835 for (j
= 0; j
< rld
[other
].nregs
; j
++)
1836 SET_HARD_REG_BIT (used_by_other_reload
, rld
[other
].regno
+ j
);
1839 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1841 #ifdef REG_ALLOC_ORDER
1842 unsigned int regno
= reg_alloc_order
[i
];
1844 unsigned int regno
= i
;
1847 if (! TEST_HARD_REG_BIT (not_usable
, regno
)
1848 && ! TEST_HARD_REG_BIT (used_by_other_reload
, regno
)
1849 && targetm
.hard_regno_mode_ok (regno
, rl
->mode
))
1851 int this_cost
= spill_cost
[regno
];
1853 unsigned int this_nregs
= hard_regno_nregs (regno
, rl
->mode
);
1855 for (j
= 1; j
< this_nregs
; j
++)
1857 this_cost
+= spill_add_cost
[regno
+ j
];
1858 if ((TEST_HARD_REG_BIT (not_usable
, regno
+ j
))
1859 || TEST_HARD_REG_BIT (used_by_other_reload
, regno
+ j
))
1865 if (ira_conflicts_p
)
1867 /* Ask IRA to find a better pseudo-register for
1869 for (n
= j
= 0; j
< this_nregs
; j
++)
1871 int r
= hard_regno_to_pseudo_regno
[regno
+ j
];
1875 if (n
== 0 || regno_pseudo_regs
[n
- 1] != r
)
1876 regno_pseudo_regs
[n
++] = r
;
1878 regno_pseudo_regs
[n
++] = -1;
1880 || ira_better_spill_reload_regno_p (regno_pseudo_regs
,
1881 best_regno_pseudo_regs
,
1888 best_regno_pseudo_regs
[j
] = regno_pseudo_regs
[j
];
1889 if (regno_pseudo_regs
[j
] < 0)
1896 if (rl
->in
&& REG_P (rl
->in
) && REGNO (rl
->in
) == regno
)
1898 if (rl
->out
&& REG_P (rl
->out
) && REGNO (rl
->out
) == regno
)
1900 if (this_cost
< best_cost
1901 /* Among registers with equal cost, prefer caller-saved ones, or
1902 use REG_ALLOC_ORDER if it is defined. */
1903 || (this_cost
== best_cost
1904 #ifdef REG_ALLOC_ORDER
1905 && (inv_reg_alloc_order
[regno
]
1906 < inv_reg_alloc_order
[best_reg
])
1908 && call_used_regs
[regno
]
1909 && ! call_used_regs
[best_reg
]
1914 best_cost
= this_cost
;
1922 fprintf (dump_file
, "Using reg %d for reload %d\n", best_reg
, rnum
);
1924 rl
->nregs
= hard_regno_nregs (best_reg
, rl
->mode
);
1925 rl
->regno
= best_reg
;
1927 EXECUTE_IF_SET_IN_REG_SET
1928 (&chain
->live_throughout
, FIRST_PSEUDO_REGISTER
, j
, rsi
)
1930 count_spilled_pseudo (best_reg
, rl
->nregs
, j
);
1933 EXECUTE_IF_SET_IN_REG_SET
1934 (&chain
->dead_or_set
, FIRST_PSEUDO_REGISTER
, j
, rsi
)
1936 count_spilled_pseudo (best_reg
, rl
->nregs
, j
);
1939 for (i
= 0; i
< rl
->nregs
; i
++)
1941 gcc_assert (spill_cost
[best_reg
+ i
] == 0);
1942 gcc_assert (spill_add_cost
[best_reg
+ i
] == 0);
1943 gcc_assert (hard_regno_to_pseudo_regno
[best_reg
+ i
] == -1);
1944 SET_HARD_REG_BIT (used_spill_regs_local
, best_reg
+ i
);
1949 /* Find more reload regs to satisfy the remaining need of an insn, which
1951 Do it by ascending class number, since otherwise a reg
1952 might be spilled for a big class and might fail to count
1953 for a smaller class even though it belongs to that class. */
1956 find_reload_regs (class insn_chain
*chain
)
1960 /* In order to be certain of getting the registers we need,
1961 we must sort the reloads into order of increasing register class.
1962 Then our grabbing of reload registers will parallel the process
1963 that provided the reload registers. */
1964 for (i
= 0; i
< chain
->n_reloads
; i
++)
1966 /* Show whether this reload already has a hard reg. */
1967 if (chain
->rld
[i
].reg_rtx
)
1969 chain
->rld
[i
].regno
= REGNO (chain
->rld
[i
].reg_rtx
);
1970 chain
->rld
[i
].nregs
= REG_NREGS (chain
->rld
[i
].reg_rtx
);
1973 chain
->rld
[i
].regno
= -1;
1974 reload_order
[i
] = i
;
1977 n_reloads
= chain
->n_reloads
;
1978 memcpy (rld
, chain
->rld
, n_reloads
* sizeof (struct reload
));
1980 CLEAR_HARD_REG_SET (used_spill_regs_local
);
1983 fprintf (dump_file
, "Spilling for insn %d.\n", INSN_UID (chain
->insn
));
1985 qsort (reload_order
, n_reloads
, sizeof (short), reload_reg_class_lower
);
1987 /* Compute the order of preference for hard registers to spill. */
1989 order_regs_for_reload (chain
);
1991 for (i
= 0; i
< n_reloads
; i
++)
1993 int r
= reload_order
[i
];
1995 /* Ignore reloads that got marked inoperative. */
1996 if ((rld
[r
].out
!= 0 || rld
[r
].in
!= 0 || rld
[r
].secondary_p
)
1997 && ! rld
[r
].optional
1998 && rld
[r
].regno
== -1)
1999 if (! find_reg (chain
, i
))
2002 fprintf (dump_file
, "reload failure for reload %d\n", r
);
2003 spill_failure (chain
->insn
, rld
[r
].rclass
);
2009 chain
->used_spill_regs
= used_spill_regs_local
;
2010 used_spill_regs
|= used_spill_regs_local
;
2012 memcpy (chain
->rld
, rld
, n_reloads
* sizeof (struct reload
));
2016 select_reload_regs (void)
2018 class insn_chain
*chain
;
2020 /* Try to satisfy the needs for each insn. */
2021 for (chain
= insns_need_reload
; chain
!= 0;
2022 chain
= chain
->next_need_reload
)
2023 find_reload_regs (chain
);
2026 /* Delete all insns that were inserted by emit_caller_save_insns during
2029 delete_caller_save_insns (void)
2031 class insn_chain
*c
= reload_insn_chain
;
2035 while (c
!= 0 && c
->is_caller_save_insn
)
2037 class insn_chain
*next
= c
->next
;
2038 rtx_insn
*insn
= c
->insn
;
2040 if (c
== reload_insn_chain
)
2041 reload_insn_chain
= next
;
2045 next
->prev
= c
->prev
;
2047 c
->prev
->next
= next
;
2048 c
->next
= unused_insn_chains
;
2049 unused_insn_chains
= c
;
2057 /* Handle the failure to find a register to spill.
2058 INSN should be one of the insns which needed this particular spill reg. */
2061 spill_failure (rtx_insn
*insn
, enum reg_class rclass
)
2063 if (asm_noperands (PATTERN (insn
)) >= 0)
2064 error_for_asm (insn
, "cannot find a register in class %qs while "
2065 "reloading %<asm%>",
2066 reg_class_names
[rclass
]);
2069 error ("unable to find a register to spill in class %qs",
2070 reg_class_names
[rclass
]);
2074 fprintf (dump_file
, "\nReloads for insn # %d\n", INSN_UID (insn
));
2075 debug_reload_to_stream (dump_file
);
2077 fatal_insn ("this is the insn:", insn
);
2081 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
2082 data that is dead in INSN. */
2085 delete_dead_insn (rtx_insn
*insn
)
2087 rtx_insn
*prev
= prev_active_insn (insn
);
2090 /* If the previous insn sets a register that dies in our insn make
2091 a note that we want to run DCE immediately after reload.
2093 We used to delete the previous insn & recurse, but that's wrong for
2094 block local equivalences. Instead of trying to figure out the exact
2095 circumstances where we can delete the potentially dead insns, just
2096 let DCE do the job. */
2097 if (prev
&& BLOCK_FOR_INSN (prev
) == BLOCK_FOR_INSN (insn
)
2098 && GET_CODE (PATTERN (prev
)) == SET
2099 && (prev_dest
= SET_DEST (PATTERN (prev
)), REG_P (prev_dest
))
2100 && reg_mentioned_p (prev_dest
, PATTERN (insn
))
2101 && find_regno_note (insn
, REG_DEAD
, REGNO (prev_dest
))
2102 && ! side_effects_p (SET_SRC (PATTERN (prev
))))
2105 SET_INSN_DELETED (insn
);
2108 /* Modify the home of pseudo-reg I.
2109 The new home is present in reg_renumber[I].
2111 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
2112 or it may be -1, meaning there is none or it is not relevant.
2113 This is used so that all pseudos spilled from a given hard reg
2114 can share one stack slot. */
2117 alter_reg (int i
, int from_reg
, bool dont_share_p
)
2119 /* When outputting an inline function, this can happen
2120 for a reg that isn't actually used. */
2121 if (regno_reg_rtx
[i
] == 0)
2124 /* If the reg got changed to a MEM at rtl-generation time,
2126 if (!REG_P (regno_reg_rtx
[i
]))
2129 /* Modify the reg-rtx to contain the new hard reg
2130 number or else to contain its pseudo reg number. */
2131 SET_REGNO (regno_reg_rtx
[i
],
2132 reg_renumber
[i
] >= 0 ? reg_renumber
[i
] : i
);
2134 /* If we have a pseudo that is needed but has no hard reg or equivalent,
2135 allocate a stack slot for it. */
2137 if (reg_renumber
[i
] < 0
2138 && REG_N_REFS (i
) > 0
2139 && reg_equiv_constant (i
) == 0
2140 && (reg_equiv_invariant (i
) == 0
2141 || reg_equiv_init (i
) == 0)
2142 && reg_equiv_memory_loc (i
) == 0)
2145 machine_mode mode
= GET_MODE (regno_reg_rtx
[i
]);
2146 poly_uint64 inherent_size
= GET_MODE_SIZE (mode
);
2147 unsigned int inherent_align
= GET_MODE_ALIGNMENT (mode
);
2148 machine_mode wider_mode
= wider_subreg_mode (mode
, reg_max_ref_mode
[i
]);
2149 poly_uint64 total_size
= GET_MODE_SIZE (wider_mode
);
2150 /* ??? Seems strange to derive the minimum alignment from the size,
2151 but that's the traditional behavior. For polynomial-size modes,
2152 the natural extension is to use the minimum possible size. */
2153 unsigned int min_align
2154 = constant_lower_bound (GET_MODE_BITSIZE (reg_max_ref_mode
[i
]));
2155 poly_int64 adjust
= 0;
2157 something_was_spilled
= true;
2159 if (ira_conflicts_p
)
2161 /* Mark the spill for IRA. */
2162 SET_REGNO_REG_SET (&spilled_pseudos
, i
);
2164 x
= ira_reuse_stack_slot (i
, inherent_size
, total_size
);
2170 /* Each pseudo reg has an inherent size which comes from its own mode,
2171 and a total size which provides room for paradoxical subregs
2172 which refer to the pseudo reg in wider modes.
2174 We can use a slot already allocated if it provides both
2175 enough inherent space and enough total space.
2176 Otherwise, we allocate a new slot, making sure that it has no less
2177 inherent space, and no less total space, then the previous slot. */
2178 else if (from_reg
== -1 || (!dont_share_p
&& ira_conflicts_p
))
2182 /* The sizes are taken from a subreg operation, which guarantees
2183 that they're ordered. */
2184 gcc_checking_assert (ordered_p (total_size
, inherent_size
));
2186 /* No known place to spill from => no slot to reuse. */
2187 x
= assign_stack_local (mode
, total_size
,
2188 min_align
> inherent_align
2189 || maybe_gt (total_size
, inherent_size
)
2194 /* Cancel the big-endian correction done in assign_stack_local.
2195 Get the address of the beginning of the slot. This is so we
2196 can do a big-endian correction unconditionally below. */
2197 if (BYTES_BIG_ENDIAN
)
2199 adjust
= inherent_size
- total_size
;
2200 if (maybe_ne (adjust
, 0))
2202 poly_uint64 total_bits
= total_size
* BITS_PER_UNIT
;
2203 machine_mode mem_mode
2204 = int_mode_for_size (total_bits
, 1).else_blk ();
2205 stack_slot
= adjust_address_nv (x
, mem_mode
, adjust
);
2209 if (! dont_share_p
&& ira_conflicts_p
)
2210 /* Inform IRA about allocation a new stack slot. */
2211 ira_mark_new_stack_slot (stack_slot
, i
, total_size
);
2214 /* Reuse a stack slot if possible. */
2215 else if (spill_stack_slot
[from_reg
] != 0
2216 && known_ge (spill_stack_slot_width
[from_reg
], total_size
)
2217 && known_ge (GET_MODE_SIZE
2218 (GET_MODE (spill_stack_slot
[from_reg
])),
2220 && MEM_ALIGN (spill_stack_slot
[from_reg
]) >= min_align
)
2221 x
= spill_stack_slot
[from_reg
];
2223 /* Allocate a bigger slot. */
2226 /* Compute maximum size needed, both for inherent size
2227 and for total size. */
2230 if (spill_stack_slot
[from_reg
])
2232 if (partial_subreg_p (mode
,
2233 GET_MODE (spill_stack_slot
[from_reg
])))
2234 mode
= GET_MODE (spill_stack_slot
[from_reg
]);
2235 total_size
= ordered_max (total_size
,
2236 spill_stack_slot_width
[from_reg
]);
2237 if (MEM_ALIGN (spill_stack_slot
[from_reg
]) > min_align
)
2238 min_align
= MEM_ALIGN (spill_stack_slot
[from_reg
]);
2241 /* The sizes are taken from a subreg operation, which guarantees
2242 that they're ordered. */
2243 gcc_checking_assert (ordered_p (total_size
, inherent_size
));
2245 /* Make a slot with that size. */
2246 x
= assign_stack_local (mode
, total_size
,
2247 min_align
> inherent_align
2248 || maybe_gt (total_size
, inherent_size
)
2252 /* Cancel the big-endian correction done in assign_stack_local.
2253 Get the address of the beginning of the slot. This is so we
2254 can do a big-endian correction unconditionally below. */
2255 if (BYTES_BIG_ENDIAN
)
2257 adjust
= GET_MODE_SIZE (mode
) - total_size
;
2258 if (maybe_ne (adjust
, 0))
2260 poly_uint64 total_bits
= total_size
* BITS_PER_UNIT
;
2261 machine_mode mem_mode
2262 = int_mode_for_size (total_bits
, 1).else_blk ();
2263 stack_slot
= adjust_address_nv (x
, mem_mode
, adjust
);
2267 spill_stack_slot
[from_reg
] = stack_slot
;
2268 spill_stack_slot_width
[from_reg
] = total_size
;
2271 /* On a big endian machine, the "address" of the slot
2272 is the address of the low part that fits its inherent mode. */
2273 adjust
+= subreg_size_lowpart_offset (inherent_size
, total_size
);
2275 /* If we have any adjustment to make, or if the stack slot is the
2276 wrong mode, make a new stack slot. */
2277 x
= adjust_address_nv (x
, GET_MODE (regno_reg_rtx
[i
]), adjust
);
2279 /* Set all of the memory attributes as appropriate for a spill. */
2280 set_mem_attrs_for_spill (x
);
2282 /* Save the stack slot for later. */
2283 reg_equiv_memory_loc (i
) = x
;
2287 /* Mark the slots in regs_ever_live for the hard regs used by
2288 pseudo-reg number REGNO, accessed in MODE. */
2291 mark_home_live_1 (int regno
, machine_mode mode
)
2295 i
= reg_renumber
[regno
];
2298 lim
= end_hard_regno (mode
, i
);
2300 df_set_regs_ever_live (i
++, true);
2303 /* Mark the slots in regs_ever_live for the hard regs
2304 used by pseudo-reg number REGNO. */
2307 mark_home_live (int regno
)
2309 if (reg_renumber
[regno
] >= 0)
2310 mark_home_live_1 (regno
, PSEUDO_REGNO_MODE (regno
));
2313 /* This function handles the tracking of elimination offsets around branches.
2315 X is a piece of RTL being scanned.
2317 INSN is the insn that it came from, if any.
2319 INITIAL_P is nonzero if we are to set the offset to be the initial
2320 offset and zero if we are setting the offset of the label to be the
2324 set_label_offsets (rtx x
, rtx_insn
*insn
, int initial_p
)
2326 enum rtx_code code
= GET_CODE (x
);
2329 struct elim_table
*p
;
2334 if (LABEL_REF_NONLOCAL_P (x
))
2337 x
= label_ref_label (x
);
2342 /* If we know nothing about this label, set the desired offsets. Note
2343 that this sets the offset at a label to be the offset before a label
2344 if we don't know anything about the label. This is not correct for
2345 the label after a BARRIER, but is the best guess we can make. If
2346 we guessed wrong, we will suppress an elimination that might have
2347 been possible had we been able to guess correctly. */
2349 if (! offsets_known_at
[CODE_LABEL_NUMBER (x
) - first_label_num
])
2351 for (i
= 0; i
< NUM_ELIMINABLE_REGS
; i
++)
2352 offsets_at
[CODE_LABEL_NUMBER (x
) - first_label_num
][i
]
2353 = (initial_p
? reg_eliminate
[i
].initial_offset
2354 : reg_eliminate
[i
].offset
);
2355 offsets_known_at
[CODE_LABEL_NUMBER (x
) - first_label_num
] = 1;
2358 /* Otherwise, if this is the definition of a label and it is
2359 preceded by a BARRIER, set our offsets to the known offset of
2363 && (tem
= prev_nonnote_insn (insn
)) != 0
2365 set_offsets_for_label (insn
);
2367 /* If neither of the above cases is true, compare each offset
2368 with those previously recorded and suppress any eliminations
2369 where the offsets disagree. */
2371 for (i
= 0; i
< NUM_ELIMINABLE_REGS
; i
++)
2372 if (maybe_ne (offsets_at
[CODE_LABEL_NUMBER (x
) - first_label_num
][i
],
2373 (initial_p
? reg_eliminate
[i
].initial_offset
2374 : reg_eliminate
[i
].offset
)))
2375 reg_eliminate
[i
].can_eliminate
= 0;
2379 case JUMP_TABLE_DATA
:
2380 set_label_offsets (PATTERN (insn
), insn
, initial_p
);
2384 set_label_offsets (PATTERN (insn
), insn
, initial_p
);
2390 /* Any labels mentioned in REG_LABEL_OPERAND notes can be branched
2391 to indirectly and hence must have all eliminations at their
2393 for (tem
= REG_NOTES (x
); tem
; tem
= XEXP (tem
, 1))
2394 if (REG_NOTE_KIND (tem
) == REG_LABEL_OPERAND
)
2395 set_label_offsets (XEXP (tem
, 0), insn
, 1);
2401 /* Each of the labels in the parallel or address vector must be
2402 at their initial offsets. We want the first field for PARALLEL
2403 and ADDR_VEC and the second field for ADDR_DIFF_VEC. */
2405 for (i
= 0; i
< (unsigned) XVECLEN (x
, code
== ADDR_DIFF_VEC
); i
++)
2406 set_label_offsets (XVECEXP (x
, code
== ADDR_DIFF_VEC
, i
),
2411 /* We only care about setting PC. If the source is not RETURN,
2412 IF_THEN_ELSE, or a label, disable any eliminations not at
2413 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2414 isn't one of those possibilities. For branches to a label,
2415 call ourselves recursively.
2417 Note that this can disable elimination unnecessarily when we have
2418 a non-local goto since it will look like a non-constant jump to
2419 someplace in the current function. This isn't a significant
2420 problem since such jumps will normally be when all elimination
2421 pairs are back to their initial offsets. */
2423 if (SET_DEST (x
) != pc_rtx
)
2426 switch (GET_CODE (SET_SRC (x
)))
2433 set_label_offsets (SET_SRC (x
), insn
, initial_p
);
2437 tem
= XEXP (SET_SRC (x
), 1);
2438 if (GET_CODE (tem
) == LABEL_REF
)
2439 set_label_offsets (label_ref_label (tem
), insn
, initial_p
);
2440 else if (GET_CODE (tem
) != PC
&& GET_CODE (tem
) != RETURN
)
2443 tem
= XEXP (SET_SRC (x
), 2);
2444 if (GET_CODE (tem
) == LABEL_REF
)
2445 set_label_offsets (label_ref_label (tem
), insn
, initial_p
);
2446 else if (GET_CODE (tem
) != PC
&& GET_CODE (tem
) != RETURN
)
2454 /* If we reach here, all eliminations must be at their initial
2455 offset because we are doing a jump to a variable address. */
2456 for (p
= reg_eliminate
; p
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; p
++)
2457 if (maybe_ne (p
->offset
, p
->initial_offset
))
2458 p
->can_eliminate
= 0;
2466 /* This function examines every reg that occurs in X and adjusts the
2467 costs for its elimination which are gathered by IRA. INSN is the
2468 insn in which X occurs. We do not recurse into MEM expressions. */
2471 note_reg_elim_costly (const_rtx x
, rtx insn
)
2473 subrtx_iterator::array_type array
;
2474 FOR_EACH_SUBRTX (iter
, array
, x
, NONCONST
)
2476 const_rtx x
= *iter
;
2478 iter
.skip_subrtxes ();
2480 && REGNO (x
) >= FIRST_PSEUDO_REGISTER
2481 && reg_equiv_init (REGNO (x
))
2482 && reg_equiv_invariant (REGNO (x
)))
2484 rtx t
= reg_equiv_invariant (REGNO (x
));
2485 rtx new_rtx
= eliminate_regs_1 (t
, Pmode
, insn
, true, true);
2486 int cost
= set_src_cost (new_rtx
, Pmode
,
2487 optimize_bb_for_speed_p (elim_bb
));
2488 int freq
= REG_FREQ_FROM_BB (elim_bb
);
2491 ira_adjust_equiv_reg_cost (REGNO (x
), -cost
* freq
);
2496 /* Scan X and replace any eliminable registers (such as fp) with a
2497 replacement (such as sp), plus an offset.
2499 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2500 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2501 MEM, we are allowed to replace a sum of a register and the constant zero
2502 with the register, which we cannot do outside a MEM. In addition, we need
2503 to record the fact that a register is referenced outside a MEM.
2505 If INSN is an insn, it is the insn containing X. If we replace a REG
2506 in a SET_DEST with an equivalent MEM and INSN is nonzero, write a
2507 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2508 the REG is being modified.
2510 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2511 That's used when we eliminate in expressions stored in notes.
2512 This means, do not set ref_outside_mem even if the reference
2515 If FOR_COSTS is true, we are being called before reload in order to
2516 estimate the costs of keeping registers with an equivalence unallocated.
2518 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2519 replacements done assuming all offsets are at their initial values. If
2520 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2521 encounter, return the actual location so that find_reloads will do
2522 the proper thing. */
2525 eliminate_regs_1 (rtx x
, machine_mode mem_mode
, rtx insn
,
2526 bool may_use_invariant
, bool for_costs
)
2528 enum rtx_code code
= GET_CODE (x
);
2529 struct elim_table
*ep
;
2536 if (! current_function_decl
)
2556 /* First handle the case where we encounter a bare register that
2557 is eliminable. Replace it with a PLUS. */
2558 if (regno
< FIRST_PSEUDO_REGISTER
)
2560 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
2562 if (ep
->from_rtx
== x
&& ep
->can_eliminate
)
2563 return plus_constant (Pmode
, ep
->to_rtx
, ep
->previous_offset
);
2566 else if (reg_renumber
&& reg_renumber
[regno
] < 0
2568 && reg_equiv_invariant (regno
))
2570 if (may_use_invariant
|| (insn
&& DEBUG_INSN_P (insn
)))
2571 return eliminate_regs_1 (copy_rtx (reg_equiv_invariant (regno
)),
2572 mem_mode
, insn
, true, for_costs
);
2573 /* There exists at least one use of REGNO that cannot be
2574 eliminated. Prevent the defining insn from being deleted. */
2575 reg_equiv_init (regno
) = NULL
;
2577 alter_reg (regno
, -1, true);
2581 /* You might think handling MINUS in a manner similar to PLUS is a
2582 good idea. It is not. It has been tried multiple times and every
2583 time the change has had to have been reverted.
2585 Other parts of reload know a PLUS is special (gen_reload for example)
2586 and require special code to handle code a reloaded PLUS operand.
2588 Also consider backends where the flags register is clobbered by a
2589 MINUS, but we can emit a PLUS that does not clobber flags (IA-32,
2590 lea instruction comes to mind). If we try to reload a MINUS, we
2591 may kill the flags register that was holding a useful value.
2593 So, please before trying to handle MINUS, consider reload as a
2594 whole instead of this little section as well as the backend issues. */
2596 /* If this is the sum of an eliminable register and a constant, rework
2598 if (REG_P (XEXP (x
, 0))
2599 && REGNO (XEXP (x
, 0)) < FIRST_PSEUDO_REGISTER
2600 && CONSTANT_P (XEXP (x
, 1)))
2602 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
2604 if (ep
->from_rtx
== XEXP (x
, 0) && ep
->can_eliminate
)
2606 /* The only time we want to replace a PLUS with a REG (this
2607 occurs when the constant operand of the PLUS is the negative
2608 of the offset) is when we are inside a MEM. We won't want
2609 to do so at other times because that would change the
2610 structure of the insn in a way that reload can't handle.
2611 We special-case the commonest situation in
2612 eliminate_regs_in_insn, so just replace a PLUS with a
2613 PLUS here, unless inside a MEM. */
2615 && CONST_INT_P (XEXP (x
, 1))
2616 && known_eq (INTVAL (XEXP (x
, 1)), -ep
->previous_offset
))
2619 return gen_rtx_PLUS (Pmode
, ep
->to_rtx
,
2620 plus_constant (Pmode
, XEXP (x
, 1),
2621 ep
->previous_offset
));
2624 /* If the register is not eliminable, we are done since the other
2625 operand is a constant. */
2629 /* If this is part of an address, we want to bring any constant to the
2630 outermost PLUS. We will do this by doing register replacement in
2631 our operands and seeing if a constant shows up in one of them.
2633 Note that there is no risk of modifying the structure of the insn,
2634 since we only get called for its operands, thus we are either
2635 modifying the address inside a MEM, or something like an address
2636 operand of a load-address insn. */
2639 rtx new0
= eliminate_regs_1 (XEXP (x
, 0), mem_mode
, insn
, true,
2641 rtx new1
= eliminate_regs_1 (XEXP (x
, 1), mem_mode
, insn
, true,
2644 if (reg_renumber
&& (new0
!= XEXP (x
, 0) || new1
!= XEXP (x
, 1)))
2646 /* If one side is a PLUS and the other side is a pseudo that
2647 didn't get a hard register but has a reg_equiv_constant,
2648 we must replace the constant here since it may no longer
2649 be in the position of any operand. */
2650 if (GET_CODE (new0
) == PLUS
&& REG_P (new1
)
2651 && REGNO (new1
) >= FIRST_PSEUDO_REGISTER
2652 && reg_renumber
[REGNO (new1
)] < 0
2654 && reg_equiv_constant (REGNO (new1
)) != 0)
2655 new1
= reg_equiv_constant (REGNO (new1
));
2656 else if (GET_CODE (new1
) == PLUS
&& REG_P (new0
)
2657 && REGNO (new0
) >= FIRST_PSEUDO_REGISTER
2658 && reg_renumber
[REGNO (new0
)] < 0
2659 && reg_equiv_constant (REGNO (new0
)) != 0)
2660 new0
= reg_equiv_constant (REGNO (new0
));
2662 new_rtx
= form_sum (GET_MODE (x
), new0
, new1
);
2664 /* As above, if we are not inside a MEM we do not want to
2665 turn a PLUS into something else. We might try to do so here
2666 for an addition of 0 if we aren't optimizing. */
2667 if (! mem_mode
&& GET_CODE (new_rtx
) != PLUS
)
2668 return gen_rtx_PLUS (GET_MODE (x
), new_rtx
, const0_rtx
);
2676 /* If this is the product of an eliminable register and a
2677 constant, apply the distribute law and move the constant out
2678 so that we have (plus (mult ..) ..). This is needed in order
2679 to keep load-address insns valid. This case is pathological.
2680 We ignore the possibility of overflow here. */
2681 if (REG_P (XEXP (x
, 0))
2682 && REGNO (XEXP (x
, 0)) < FIRST_PSEUDO_REGISTER
2683 && CONST_INT_P (XEXP (x
, 1)))
2684 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
2686 if (ep
->from_rtx
== XEXP (x
, 0) && ep
->can_eliminate
)
2689 /* Refs inside notes or in DEBUG_INSNs don't count for
2691 && ! (insn
!= 0 && (GET_CODE (insn
) == EXPR_LIST
2692 || GET_CODE (insn
) == INSN_LIST
2693 || DEBUG_INSN_P (insn
))))
2694 ep
->ref_outside_mem
= 1;
2697 plus_constant (Pmode
,
2698 gen_rtx_MULT (Pmode
, ep
->to_rtx
, XEXP (x
, 1)),
2699 ep
->previous_offset
* INTVAL (XEXP (x
, 1)));
2706 /* See comments before PLUS about handling MINUS. */
2708 case DIV
: case UDIV
:
2709 case MOD
: case UMOD
:
2710 case AND
: case IOR
: case XOR
:
2711 case ROTATERT
: case ROTATE
:
2712 case ASHIFTRT
: case LSHIFTRT
: case ASHIFT
:
2714 case GE
: case GT
: case GEU
: case GTU
:
2715 case LE
: case LT
: case LEU
: case LTU
:
2717 rtx new0
= eliminate_regs_1 (XEXP (x
, 0), mem_mode
, insn
, false,
2719 rtx new1
= XEXP (x
, 1)
2720 ? eliminate_regs_1 (XEXP (x
, 1), mem_mode
, insn
, false,
2723 if (new0
!= XEXP (x
, 0) || new1
!= XEXP (x
, 1))
2724 return gen_rtx_fmt_ee (code
, GET_MODE (x
), new0
, new1
);
2729 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2732 new_rtx
= eliminate_regs_1 (XEXP (x
, 0), mem_mode
, insn
, true,
2734 if (new_rtx
!= XEXP (x
, 0))
2736 /* If this is a REG_DEAD note, it is not valid anymore.
2737 Using the eliminated version could result in creating a
2738 REG_DEAD note for the stack or frame pointer. */
2739 if (REG_NOTE_KIND (x
) == REG_DEAD
)
2741 ? eliminate_regs_1 (XEXP (x
, 1), mem_mode
, insn
, true,
2745 x
= alloc_reg_note (REG_NOTE_KIND (x
), new_rtx
, XEXP (x
, 1));
2753 /* Now do eliminations in the rest of the chain. If this was
2754 an EXPR_LIST, this might result in allocating more memory than is
2755 strictly needed, but it simplifies the code. */
2758 new_rtx
= eliminate_regs_1 (XEXP (x
, 1), mem_mode
, insn
, true,
2760 if (new_rtx
!= XEXP (x
, 1))
2762 gen_rtx_fmt_ee (GET_CODE (x
), GET_MODE (x
), XEXP (x
, 0), new_rtx
);
2770 /* We do not support elimination of a register that is modified.
2771 elimination_effects has already make sure that this does not
2777 /* We do not support elimination of a register that is modified.
2778 elimination_effects has already make sure that this does not
2779 happen. The only remaining case we need to consider here is
2780 that the increment value may be an eliminable register. */
2781 if (GET_CODE (XEXP (x
, 1)) == PLUS
2782 && XEXP (XEXP (x
, 1), 0) == XEXP (x
, 0))
2784 rtx new_rtx
= eliminate_regs_1 (XEXP (XEXP (x
, 1), 1), mem_mode
,
2785 insn
, true, for_costs
);
2787 if (new_rtx
!= XEXP (XEXP (x
, 1), 1))
2788 return gen_rtx_fmt_ee (code
, GET_MODE (x
), XEXP (x
, 0),
2789 gen_rtx_PLUS (GET_MODE (x
),
2790 XEXP (x
, 0), new_rtx
));
2794 case STRICT_LOW_PART
:
2796 case SIGN_EXTEND
: case ZERO_EXTEND
:
2797 case TRUNCATE
: case FLOAT_EXTEND
: case FLOAT_TRUNCATE
:
2798 case FLOAT
: case FIX
:
2799 case UNSIGNED_FIX
: case UNSIGNED_FLOAT
:
2808 new_rtx
= eliminate_regs_1 (XEXP (x
, 0), mem_mode
, insn
, false,
2810 if (new_rtx
!= XEXP (x
, 0))
2811 return gen_rtx_fmt_e (code
, GET_MODE (x
), new_rtx
);
2815 /* Similar to above processing, but preserve SUBREG_BYTE.
2816 Convert (subreg (mem)) to (mem) if not paradoxical.
2817 Also, if we have a non-paradoxical (subreg (pseudo)) and the
2818 pseudo didn't get a hard reg, we must replace this with the
2819 eliminated version of the memory location because push_reload
2820 may do the replacement in certain circumstances. */
2821 if (REG_P (SUBREG_REG (x
))
2822 && !paradoxical_subreg_p (x
)
2824 && reg_equiv_memory_loc (REGNO (SUBREG_REG (x
))) != 0)
2826 new_rtx
= SUBREG_REG (x
);
2829 new_rtx
= eliminate_regs_1 (SUBREG_REG (x
), mem_mode
, insn
, false, for_costs
);
2831 if (new_rtx
!= SUBREG_REG (x
))
2833 poly_int64 x_size
= GET_MODE_SIZE (GET_MODE (x
));
2834 poly_int64 new_size
= GET_MODE_SIZE (GET_MODE (new_rtx
));
2837 && ((partial_subreg_p (GET_MODE (x
), GET_MODE (new_rtx
))
2838 /* On RISC machines, combine can create rtl of the form
2839 (set (subreg:m1 (reg:m2 R) 0) ...)
2840 where m1 < m2, and expects something interesting to
2841 happen to the entire word. Moreover, it will use the
2842 (reg:m2 R) later, expecting all bits to be preserved.
2843 So if the number of words is the same, preserve the
2844 subreg so that push_reload can see it. */
2845 && !(WORD_REGISTER_OPERATIONS
2846 && known_equal_after_align_down (x_size
- 1,
2849 || known_eq (x_size
, new_size
))
2851 return adjust_address_nv (new_rtx
, GET_MODE (x
), SUBREG_BYTE (x
));
2852 else if (insn
&& GET_CODE (insn
) == DEBUG_INSN
)
2853 return gen_rtx_raw_SUBREG (GET_MODE (x
), new_rtx
, SUBREG_BYTE (x
));
2855 return gen_rtx_SUBREG (GET_MODE (x
), new_rtx
, SUBREG_BYTE (x
));
2861 /* Our only special processing is to pass the mode of the MEM to our
2862 recursive call and copy the flags. While we are here, handle this
2863 case more efficiently. */
2865 new_rtx
= eliminate_regs_1 (XEXP (x
, 0), GET_MODE (x
), insn
, true,
2868 && memory_address_p (GET_MODE (x
), XEXP (x
, 0))
2869 && !memory_address_p (GET_MODE (x
), new_rtx
))
2870 note_reg_elim_costly (XEXP (x
, 0), insn
);
2872 return replace_equiv_address_nv (x
, new_rtx
);
2875 /* Handle insn_list USE that a call to a pure function may generate. */
2876 new_rtx
= eliminate_regs_1 (XEXP (x
, 0), VOIDmode
, insn
, false,
2878 if (new_rtx
!= XEXP (x
, 0))
2879 return gen_rtx_USE (GET_MODE (x
), new_rtx
);
2885 gcc_assert (insn
&& DEBUG_INSN_P (insn
));
2895 /* Process each of our operands recursively. If any have changed, make a
2897 fmt
= GET_RTX_FORMAT (code
);
2898 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++, fmt
++)
2902 new_rtx
= eliminate_regs_1 (XEXP (x
, i
), mem_mode
, insn
, false,
2904 if (new_rtx
!= XEXP (x
, i
) && ! copied
)
2906 x
= shallow_copy_rtx (x
);
2909 XEXP (x
, i
) = new_rtx
;
2911 else if (*fmt
== 'E')
2914 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
2916 new_rtx
= eliminate_regs_1 (XVECEXP (x
, i
, j
), mem_mode
, insn
, false,
2918 if (new_rtx
!= XVECEXP (x
, i
, j
) && ! copied_vec
)
2920 rtvec new_v
= gen_rtvec_v (XVECLEN (x
, i
),
2924 x
= shallow_copy_rtx (x
);
2927 XVEC (x
, i
) = new_v
;
2930 XVECEXP (x
, i
, j
) = new_rtx
;
2939 eliminate_regs (rtx x
, machine_mode mem_mode
, rtx insn
)
2941 if (reg_eliminate
== NULL
)
2943 gcc_assert (targetm
.no_register_allocation
);
2946 return eliminate_regs_1 (x
, mem_mode
, insn
, false, false);
2949 /* Scan rtx X for modifications of elimination target registers. Update
2950 the table of eliminables to reflect the changed state. MEM_MODE is
2951 the mode of an enclosing MEM rtx, or VOIDmode if not within a MEM. */
2954 elimination_effects (rtx x
, machine_mode mem_mode
)
2956 enum rtx_code code
= GET_CODE (x
);
2957 struct elim_table
*ep
;
2979 /* First handle the case where we encounter a bare register that
2980 is eliminable. Replace it with a PLUS. */
2981 if (regno
< FIRST_PSEUDO_REGISTER
)
2983 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
2985 if (ep
->from_rtx
== x
&& ep
->can_eliminate
)
2988 ep
->ref_outside_mem
= 1;
2993 else if (reg_renumber
[regno
] < 0
2995 && reg_equiv_constant (regno
)
2996 && ! function_invariant_p (reg_equiv_constant (regno
)))
2997 elimination_effects (reg_equiv_constant (regno
), mem_mode
);
3006 /* If we modify the source of an elimination rule, disable it. */
3007 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3008 if (ep
->from_rtx
== XEXP (x
, 0))
3009 ep
->can_eliminate
= 0;
3011 /* If we modify the target of an elimination rule by adding a constant,
3012 update its offset. If we modify the target in any other way, we'll
3013 have to disable the rule as well. */
3014 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3015 if (ep
->to_rtx
== XEXP (x
, 0))
3017 poly_int64 size
= GET_MODE_SIZE (mem_mode
);
3019 /* If more bytes than MEM_MODE are pushed, account for them. */
3020 #ifdef PUSH_ROUNDING
3021 if (ep
->to_rtx
== stack_pointer_rtx
)
3022 size
= PUSH_ROUNDING (size
);
3024 if (code
== PRE_DEC
|| code
== POST_DEC
)
3026 else if (code
== PRE_INC
|| code
== POST_INC
)
3028 else if (code
== PRE_MODIFY
|| code
== POST_MODIFY
)
3030 if (GET_CODE (XEXP (x
, 1)) == PLUS
3031 && XEXP (x
, 0) == XEXP (XEXP (x
, 1), 0)
3032 && CONST_INT_P (XEXP (XEXP (x
, 1), 1)))
3033 ep
->offset
-= INTVAL (XEXP (XEXP (x
, 1), 1));
3035 ep
->can_eliminate
= 0;
3039 /* These two aren't unary operators. */
3040 if (code
== POST_MODIFY
|| code
== PRE_MODIFY
)
3043 /* Fall through to generic unary operation case. */
3045 case STRICT_LOW_PART
:
3047 case SIGN_EXTEND
: case ZERO_EXTEND
:
3048 case TRUNCATE
: case FLOAT_EXTEND
: case FLOAT_TRUNCATE
:
3049 case FLOAT
: case FIX
:
3050 case UNSIGNED_FIX
: case UNSIGNED_FLOAT
:
3059 elimination_effects (XEXP (x
, 0), mem_mode
);
3063 if (REG_P (SUBREG_REG (x
))
3064 && !paradoxical_subreg_p (x
)
3066 && reg_equiv_memory_loc (REGNO (SUBREG_REG (x
))) != 0)
3069 elimination_effects (SUBREG_REG (x
), mem_mode
);
3073 /* If using a register that is the source of an eliminate we still
3074 think can be performed, note it cannot be performed since we don't
3075 know how this register is used. */
3076 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3077 if (ep
->from_rtx
== XEXP (x
, 0))
3078 ep
->can_eliminate
= 0;
3080 elimination_effects (XEXP (x
, 0), mem_mode
);
3084 /* If clobbering a register that is the replacement register for an
3085 elimination we still think can be performed, note that it cannot
3086 be performed. Otherwise, we need not be concerned about it. */
3087 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3088 if (ep
->to_rtx
== XEXP (x
, 0))
3089 ep
->can_eliminate
= 0;
3091 elimination_effects (XEXP (x
, 0), mem_mode
);
3095 /* CLOBBER_HIGH is only supported for LRA. */
3099 /* Check for setting a register that we know about. */
3100 if (REG_P (SET_DEST (x
)))
3102 /* See if this is setting the replacement register for an
3105 If DEST is the hard frame pointer, we do nothing because we
3106 assume that all assignments to the frame pointer are for
3107 non-local gotos and are being done at a time when they are valid
3108 and do not disturb anything else. Some machines want to
3109 eliminate a fake argument pointer (or even a fake frame pointer)
3110 with either the real frame or the stack pointer. Assignments to
3111 the hard frame pointer must not prevent this elimination. */
3113 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
3115 if (ep
->to_rtx
== SET_DEST (x
)
3116 && SET_DEST (x
) != hard_frame_pointer_rtx
)
3118 /* If it is being incremented, adjust the offset. Otherwise,
3119 this elimination can't be done. */
3120 rtx src
= SET_SRC (x
);
3122 if (GET_CODE (src
) == PLUS
3123 && XEXP (src
, 0) == SET_DEST (x
)
3124 && CONST_INT_P (XEXP (src
, 1)))
3125 ep
->offset
-= INTVAL (XEXP (src
, 1));
3127 ep
->can_eliminate
= 0;
3131 elimination_effects (SET_DEST (x
), VOIDmode
);
3132 elimination_effects (SET_SRC (x
), VOIDmode
);
3136 /* Our only special processing is to pass the mode of the MEM to our
3138 elimination_effects (XEXP (x
, 0), GET_MODE (x
));
3145 fmt
= GET_RTX_FORMAT (code
);
3146 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++, fmt
++)
3149 elimination_effects (XEXP (x
, i
), mem_mode
);
3150 else if (*fmt
== 'E')
3151 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
3152 elimination_effects (XVECEXP (x
, i
, j
), mem_mode
);
3156 /* Descend through rtx X and verify that no references to eliminable registers
3157 remain. If any do remain, mark the involved register as not
3161 check_eliminable_occurrences (rtx x
)
3170 code
= GET_CODE (x
);
3172 if (code
== REG
&& REGNO (x
) < FIRST_PSEUDO_REGISTER
)
3174 struct elim_table
*ep
;
3176 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3177 if (ep
->from_rtx
== x
)
3178 ep
->can_eliminate
= 0;
3182 fmt
= GET_RTX_FORMAT (code
);
3183 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++, fmt
++)
3186 check_eliminable_occurrences (XEXP (x
, i
));
3187 else if (*fmt
== 'E')
3190 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
3191 check_eliminable_occurrences (XVECEXP (x
, i
, j
));
3196 /* Scan INSN and eliminate all eliminable registers in it.
3198 If REPLACE is nonzero, do the replacement destructively. Also
3199 delete the insn as dead it if it is setting an eliminable register.
3201 If REPLACE is zero, do all our allocations in reload_obstack.
3203 If no eliminations were done and this insn doesn't require any elimination
3204 processing (these are not identical conditions: it might be updating sp,
3205 but not referencing fp; this needs to be seen during reload_as_needed so
3206 that the offset between fp and sp can be taken into consideration), zero
3207 is returned. Otherwise, 1 is returned. */
3210 eliminate_regs_in_insn (rtx_insn
*insn
, int replace
)
3212 int icode
= recog_memoized (insn
);
3213 rtx old_body
= PATTERN (insn
);
3214 int insn_is_asm
= asm_noperands (old_body
) >= 0;
3215 rtx old_set
= single_set (insn
);
3219 rtx substed_operand
[MAX_RECOG_OPERANDS
];
3220 rtx orig_operand
[MAX_RECOG_OPERANDS
];
3221 struct elim_table
*ep
;
3222 rtx plus_src
, plus_cst_src
;
3224 if (! insn_is_asm
&& icode
< 0)
3226 gcc_assert (DEBUG_INSN_P (insn
)
3227 || GET_CODE (PATTERN (insn
)) == USE
3228 || GET_CODE (PATTERN (insn
)) == CLOBBER
3229 || GET_CODE (PATTERN (insn
)) == ASM_INPUT
);
3230 if (DEBUG_BIND_INSN_P (insn
))
3231 INSN_VAR_LOCATION_LOC (insn
)
3232 = eliminate_regs (INSN_VAR_LOCATION_LOC (insn
), VOIDmode
, insn
);
3236 /* We allow one special case which happens to work on all machines we
3237 currently support: a single set with the source or a REG_EQUAL
3238 note being a PLUS of an eliminable register and a constant. */
3239 plus_src
= plus_cst_src
= 0;
3240 if (old_set
&& REG_P (SET_DEST (old_set
)))
3242 if (GET_CODE (SET_SRC (old_set
)) == PLUS
)
3243 plus_src
= SET_SRC (old_set
);
3244 /* First see if the source is of the form (plus (...) CST). */
3246 && CONST_INT_P (XEXP (plus_src
, 1)))
3247 plus_cst_src
= plus_src
;
3248 else if (REG_P (SET_SRC (old_set
))
3251 /* Otherwise, see if we have a REG_EQUAL note of the form
3252 (plus (...) CST). */
3254 for (links
= REG_NOTES (insn
); links
; links
= XEXP (links
, 1))
3256 if ((REG_NOTE_KIND (links
) == REG_EQUAL
3257 || REG_NOTE_KIND (links
) == REG_EQUIV
)
3258 && GET_CODE (XEXP (links
, 0)) == PLUS
3259 && CONST_INT_P (XEXP (XEXP (links
, 0), 1)))
3261 plus_cst_src
= XEXP (links
, 0);
3267 /* Check that the first operand of the PLUS is a hard reg or
3268 the lowpart subreg of one. */
3271 rtx reg
= XEXP (plus_cst_src
, 0);
3272 if (GET_CODE (reg
) == SUBREG
&& subreg_lowpart_p (reg
))
3273 reg
= SUBREG_REG (reg
);
3275 if (!REG_P (reg
) || REGNO (reg
) >= FIRST_PSEUDO_REGISTER
)
3281 rtx reg
= XEXP (plus_cst_src
, 0);
3282 poly_int64 offset
= INTVAL (XEXP (plus_cst_src
, 1));
3284 if (GET_CODE (reg
) == SUBREG
)
3285 reg
= SUBREG_REG (reg
);
3287 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3288 if (ep
->from_rtx
== reg
&& ep
->can_eliminate
)
3290 rtx to_rtx
= ep
->to_rtx
;
3291 offset
+= ep
->offset
;
3292 offset
= trunc_int_for_mode (offset
, GET_MODE (plus_cst_src
));
3294 if (GET_CODE (XEXP (plus_cst_src
, 0)) == SUBREG
)
3295 to_rtx
= gen_lowpart (GET_MODE (XEXP (plus_cst_src
, 0)),
3297 /* If we have a nonzero offset, and the source is already
3298 a simple REG, the following transformation would
3299 increase the cost of the insn by replacing a simple REG
3300 with (plus (reg sp) CST). So try only when we already
3301 had a PLUS before. */
3302 if (known_eq (offset
, 0) || plus_src
)
3304 rtx new_src
= plus_constant (GET_MODE (to_rtx
),
3307 new_body
= old_body
;
3310 new_body
= copy_insn (old_body
);
3311 if (REG_NOTES (insn
))
3312 REG_NOTES (insn
) = copy_insn_1 (REG_NOTES (insn
));
3314 PATTERN (insn
) = new_body
;
3315 old_set
= single_set (insn
);
3317 /* First see if this insn remains valid when we make the
3318 change. If not, try to replace the whole pattern with
3319 a simple set (this may help if the original insn was a
3320 PARALLEL that was only recognized as single_set due to
3321 REG_UNUSED notes). If this isn't valid either, keep
3322 the INSN_CODE the same and let reload fix it up. */
3323 if (!validate_change (insn
, &SET_SRC (old_set
), new_src
, 0))
3325 rtx new_pat
= gen_rtx_SET (SET_DEST (old_set
), new_src
);
3327 if (!validate_change (insn
, &PATTERN (insn
), new_pat
, 0))
3328 SET_SRC (old_set
) = new_src
;
3335 /* This can't have an effect on elimination offsets, so skip right
3341 /* Determine the effects of this insn on elimination offsets. */
3342 elimination_effects (old_body
, VOIDmode
);
3344 /* Eliminate all eliminable registers occurring in operands that
3345 can be handled by reload. */
3346 extract_insn (insn
);
3347 for (i
= 0; i
< recog_data
.n_operands
; i
++)
3349 orig_operand
[i
] = recog_data
.operand
[i
];
3350 substed_operand
[i
] = recog_data
.operand
[i
];
3352 /* For an asm statement, every operand is eliminable. */
3353 if (insn_is_asm
|| insn_data
[icode
].operand
[i
].eliminable
)
3355 bool is_set_src
, in_plus
;
3357 /* Check for setting a register that we know about. */
3358 if (recog_data
.operand_type
[i
] != OP_IN
3359 && REG_P (orig_operand
[i
]))
3361 /* If we are assigning to a register that can be eliminated, it
3362 must be as part of a PARALLEL, since the code above handles
3363 single SETs. We must indicate that we can no longer
3364 eliminate this reg. */
3365 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
3367 if (ep
->from_rtx
== orig_operand
[i
])
3368 ep
->can_eliminate
= 0;
3371 /* Companion to the above plus substitution, we can allow
3372 invariants as the source of a plain move. */
3375 && recog_data
.operand_loc
[i
] == &SET_SRC (old_set
))
3379 && (recog_data
.operand_loc
[i
] == &XEXP (plus_src
, 0)
3380 || recog_data
.operand_loc
[i
] == &XEXP (plus_src
, 1)))
3384 = eliminate_regs_1 (recog_data
.operand
[i
], VOIDmode
,
3385 replace
? insn
: NULL_RTX
,
3386 is_set_src
|| in_plus
, false);
3387 if (substed_operand
[i
] != orig_operand
[i
])
3389 /* Terminate the search in check_eliminable_occurrences at
3391 *recog_data
.operand_loc
[i
] = 0;
3393 /* If an output operand changed from a REG to a MEM and INSN is an
3394 insn, write a CLOBBER insn. */
3395 if (recog_data
.operand_type
[i
] != OP_IN
3396 && REG_P (orig_operand
[i
])
3397 && MEM_P (substed_operand
[i
])
3399 emit_insn_after (gen_clobber (orig_operand
[i
]), insn
);
3403 for (i
= 0; i
< recog_data
.n_dups
; i
++)
3404 *recog_data
.dup_loc
[i
]
3405 = *recog_data
.operand_loc
[(int) recog_data
.dup_num
[i
]];
3407 /* If any eliminable remain, they aren't eliminable anymore. */
3408 check_eliminable_occurrences (old_body
);
3410 /* Substitute the operands; the new values are in the substed_operand
3412 for (i
= 0; i
< recog_data
.n_operands
; i
++)
3413 *recog_data
.operand_loc
[i
] = substed_operand
[i
];
3414 for (i
= 0; i
< recog_data
.n_dups
; i
++)
3415 *recog_data
.dup_loc
[i
] = substed_operand
[(int) recog_data
.dup_num
[i
]];
3417 /* If we are replacing a body that was a (set X (plus Y Z)), try to
3418 re-recognize the insn. We do this in case we had a simple addition
3419 but now can do this as a load-address. This saves an insn in this
3421 If re-recognition fails, the old insn code number will still be used,
3422 and some register operands may have changed into PLUS expressions.
3423 These will be handled by find_reloads by loading them into a register
3428 /* If we aren't replacing things permanently and we changed something,
3429 make another copy to ensure that all the RTL is new. Otherwise
3430 things can go wrong if find_reload swaps commutative operands
3431 and one is inside RTL that has been copied while the other is not. */
3432 new_body
= old_body
;
3435 new_body
= copy_insn (old_body
);
3436 if (REG_NOTES (insn
))
3437 REG_NOTES (insn
) = copy_insn_1 (REG_NOTES (insn
));
3439 PATTERN (insn
) = new_body
;
3441 /* If we had a move insn but now we don't, rerecognize it. This will
3442 cause spurious re-recognition if the old move had a PARALLEL since
3443 the new one still will, but we can't call single_set without
3444 having put NEW_BODY into the insn and the re-recognition won't
3445 hurt in this rare case. */
3446 /* ??? Why this huge if statement - why don't we just rerecognize the
3450 && ((REG_P (SET_SRC (old_set
))
3451 && (GET_CODE (new_body
) != SET
3452 || !REG_P (SET_SRC (new_body
))))
3453 /* If this was a load from or store to memory, compare
3454 the MEM in recog_data.operand to the one in the insn.
3455 If they are not equal, then rerecognize the insn. */
3457 && ((MEM_P (SET_SRC (old_set
))
3458 && SET_SRC (old_set
) != recog_data
.operand
[1])
3459 || (MEM_P (SET_DEST (old_set
))
3460 && SET_DEST (old_set
) != recog_data
.operand
[0])))
3461 /* If this was an add insn before, rerecognize. */
3462 || GET_CODE (SET_SRC (old_set
)) == PLUS
))
3464 int new_icode
= recog (PATTERN (insn
), insn
, 0);
3466 INSN_CODE (insn
) = new_icode
;
3470 /* Restore the old body. If there were any changes to it, we made a copy
3471 of it while the changes were still in place, so we'll correctly return
3472 a modified insn below. */
3475 /* Restore the old body. */
3476 for (i
= 0; i
< recog_data
.n_operands
; i
++)
3477 /* Restoring a top-level match_parallel would clobber the new_body
3478 we installed in the insn. */
3479 if (recog_data
.operand_loc
[i
] != &PATTERN (insn
))
3480 *recog_data
.operand_loc
[i
] = orig_operand
[i
];
3481 for (i
= 0; i
< recog_data
.n_dups
; i
++)
3482 *recog_data
.dup_loc
[i
] = orig_operand
[(int) recog_data
.dup_num
[i
]];
3485 /* Update all elimination pairs to reflect the status after the current
3486 insn. The changes we make were determined by the earlier call to
3487 elimination_effects.
3489 We also detect cases where register elimination cannot be done,
3490 namely, if a register would be both changed and referenced outside a MEM
3491 in the resulting insn since such an insn is often undefined and, even if
3492 not, we cannot know what meaning will be given to it. Note that it is
3493 valid to have a register used in an address in an insn that changes it
3494 (presumably with a pre- or post-increment or decrement).
3496 If anything changes, return nonzero. */
3498 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3500 if (maybe_ne (ep
->previous_offset
, ep
->offset
) && ep
->ref_outside_mem
)
3501 ep
->can_eliminate
= 0;
3503 ep
->ref_outside_mem
= 0;
3505 if (maybe_ne (ep
->previous_offset
, ep
->offset
))
3510 /* If we changed something, perform elimination in REG_NOTES. This is
3511 needed even when REPLACE is zero because a REG_DEAD note might refer
3512 to a register that we eliminate and could cause a different number
3513 of spill registers to be needed in the final reload pass than in
3515 if (val
&& REG_NOTES (insn
) != 0)
3517 = eliminate_regs_1 (REG_NOTES (insn
), VOIDmode
, REG_NOTES (insn
), true,
3523 /* Like eliminate_regs_in_insn, but only estimate costs for the use of the
3524 register allocator. INSN is the instruction we need to examine, we perform
3525 eliminations in its operands and record cases where eliminating a reg with
3526 an invariant equivalence would add extra cost. */
3528 #pragma GCC diagnostic push
3529 #pragma GCC diagnostic warning "-Wmaybe-uninitialized"
3531 elimination_costs_in_insn (rtx_insn
*insn
)
3533 int icode
= recog_memoized (insn
);
3534 rtx old_body
= PATTERN (insn
);
3535 int insn_is_asm
= asm_noperands (old_body
) >= 0;
3536 rtx old_set
= single_set (insn
);
3538 rtx orig_operand
[MAX_RECOG_OPERANDS
];
3539 rtx orig_dup
[MAX_RECOG_OPERANDS
];
3540 struct elim_table
*ep
;
3541 rtx plus_src
, plus_cst_src
;
3544 if (! insn_is_asm
&& icode
< 0)
3546 gcc_assert (DEBUG_INSN_P (insn
)
3547 || GET_CODE (PATTERN (insn
)) == USE
3548 || GET_CODE (PATTERN (insn
)) == CLOBBER
3549 || GET_CODE (PATTERN (insn
)) == ASM_INPUT
);
3553 if (old_set
!= 0 && REG_P (SET_DEST (old_set
))
3554 && REGNO (SET_DEST (old_set
)) < FIRST_PSEUDO_REGISTER
)
3556 /* Check for setting an eliminable register. */
3557 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3558 if (ep
->from_rtx
== SET_DEST (old_set
) && ep
->can_eliminate
)
3562 /* We allow one special case which happens to work on all machines we
3563 currently support: a single set with the source or a REG_EQUAL
3564 note being a PLUS of an eliminable register and a constant. */
3565 plus_src
= plus_cst_src
= 0;
3567 if (old_set
&& REG_P (SET_DEST (old_set
)))
3570 if (GET_CODE (SET_SRC (old_set
)) == PLUS
)
3571 plus_src
= SET_SRC (old_set
);
3572 /* First see if the source is of the form (plus (...) CST). */
3574 && CONST_INT_P (XEXP (plus_src
, 1)))
3575 plus_cst_src
= plus_src
;
3576 else if (REG_P (SET_SRC (old_set
))
3579 /* Otherwise, see if we have a REG_EQUAL note of the form
3580 (plus (...) CST). */
3582 for (links
= REG_NOTES (insn
); links
; links
= XEXP (links
, 1))
3584 if ((REG_NOTE_KIND (links
) == REG_EQUAL
3585 || REG_NOTE_KIND (links
) == REG_EQUIV
)
3586 && GET_CODE (XEXP (links
, 0)) == PLUS
3587 && CONST_INT_P (XEXP (XEXP (links
, 0), 1)))
3589 plus_cst_src
= XEXP (links
, 0);
3596 /* Determine the effects of this insn on elimination offsets. */
3597 elimination_effects (old_body
, VOIDmode
);
3599 /* Eliminate all eliminable registers occurring in operands that
3600 can be handled by reload. */
3601 extract_insn (insn
);
3602 int n_dups
= recog_data
.n_dups
;
3603 for (i
= 0; i
< n_dups
; i
++)
3604 orig_dup
[i
] = *recog_data
.dup_loc
[i
];
3606 int n_operands
= recog_data
.n_operands
;
3607 for (i
= 0; i
< n_operands
; i
++)
3609 orig_operand
[i
] = recog_data
.operand
[i
];
3611 /* For an asm statement, every operand is eliminable. */
3612 if (insn_is_asm
|| insn_data
[icode
].operand
[i
].eliminable
)
3614 bool is_set_src
, in_plus
;
3616 /* Check for setting a register that we know about. */
3617 if (recog_data
.operand_type
[i
] != OP_IN
3618 && REG_P (orig_operand
[i
]))
3620 /* If we are assigning to a register that can be eliminated, it
3621 must be as part of a PARALLEL, since the code above handles
3622 single SETs. We must indicate that we can no longer
3623 eliminate this reg. */
3624 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
3626 if (ep
->from_rtx
== orig_operand
[i
])
3627 ep
->can_eliminate
= 0;
3630 /* Companion to the above plus substitution, we can allow
3631 invariants as the source of a plain move. */
3633 if (old_set
&& recog_data
.operand_loc
[i
] == &SET_SRC (old_set
))
3635 if (is_set_src
&& !sets_reg_p
)
3636 note_reg_elim_costly (SET_SRC (old_set
), insn
);
3638 if (plus_src
&& sets_reg_p
3639 && (recog_data
.operand_loc
[i
] == &XEXP (plus_src
, 0)
3640 || recog_data
.operand_loc
[i
] == &XEXP (plus_src
, 1)))
3643 eliminate_regs_1 (recog_data
.operand
[i
], VOIDmode
,
3645 is_set_src
|| in_plus
, true);
3646 /* Terminate the search in check_eliminable_occurrences at
3648 *recog_data
.operand_loc
[i
] = 0;
3652 for (i
= 0; i
< n_dups
; i
++)
3653 *recog_data
.dup_loc
[i
]
3654 = *recog_data
.operand_loc
[(int) recog_data
.dup_num
[i
]];
3656 /* If any eliminable remain, they aren't eliminable anymore. */
3657 check_eliminable_occurrences (old_body
);
3659 /* Restore the old body. */
3660 for (i
= 0; i
< n_operands
; i
++)
3661 *recog_data
.operand_loc
[i
] = orig_operand
[i
];
3662 for (i
= 0; i
< n_dups
; i
++)
3663 *recog_data
.dup_loc
[i
] = orig_dup
[i
];
3665 /* Update all elimination pairs to reflect the status after the current
3666 insn. The changes we make were determined by the earlier call to
3667 elimination_effects. */
3669 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3671 if (maybe_ne (ep
->previous_offset
, ep
->offset
) && ep
->ref_outside_mem
)
3672 ep
->can_eliminate
= 0;
3674 ep
->ref_outside_mem
= 0;
3679 #pragma GCC diagnostic pop
3681 /* Loop through all elimination pairs.
3682 Recalculate the number not at initial offset.
3684 Compute the maximum offset (minimum offset if the stack does not
3685 grow downward) for each elimination pair. */
3688 update_eliminable_offsets (void)
3690 struct elim_table
*ep
;
3692 num_not_at_initial_offset
= 0;
3693 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3695 ep
->previous_offset
= ep
->offset
;
3696 if (ep
->can_eliminate
&& maybe_ne (ep
->offset
, ep
->initial_offset
))
3697 num_not_at_initial_offset
++;
3701 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3702 replacement we currently believe is valid, mark it as not eliminable if X
3703 modifies DEST in any way other than by adding a constant integer to it.
3705 If DEST is the frame pointer, we do nothing because we assume that
3706 all assignments to the hard frame pointer are nonlocal gotos and are being
3707 done at a time when they are valid and do not disturb anything else.
3708 Some machines want to eliminate a fake argument pointer with either the
3709 frame or stack pointer. Assignments to the hard frame pointer must not
3710 prevent this elimination.
3712 Called via note_stores from reload before starting its passes to scan
3713 the insns of the function. */
3716 mark_not_eliminable (rtx dest
, const_rtx x
, void *data ATTRIBUTE_UNUSED
)
3720 /* A SUBREG of a hard register here is just changing its mode. We should
3721 not see a SUBREG of an eliminable hard register, but check just in
3723 if (GET_CODE (dest
) == SUBREG
)
3724 dest
= SUBREG_REG (dest
);
3726 if (dest
== hard_frame_pointer_rtx
)
3729 /* CLOBBER_HIGH is only supported for LRA. */
3730 gcc_assert (GET_CODE (x
) != CLOBBER_HIGH
);
3732 for (i
= 0; i
< NUM_ELIMINABLE_REGS
; i
++)
3733 if (reg_eliminate
[i
].can_eliminate
&& dest
== reg_eliminate
[i
].to_rtx
3734 && (GET_CODE (x
) != SET
3735 || GET_CODE (SET_SRC (x
)) != PLUS
3736 || XEXP (SET_SRC (x
), 0) != dest
3737 || !CONST_INT_P (XEXP (SET_SRC (x
), 1))))
3739 reg_eliminate
[i
].can_eliminate_previous
3740 = reg_eliminate
[i
].can_eliminate
= 0;
3745 /* Verify that the initial elimination offsets did not change since the
3746 last call to set_initial_elim_offsets. This is used to catch cases
3747 where something illegal happened during reload_as_needed that could
3748 cause incorrect code to be generated if we did not check for it. */
3751 verify_initial_elim_offsets (void)
3754 struct elim_table
*ep
;
3756 if (!num_eliminable
)
3759 targetm
.compute_frame_layout ();
3760 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3762 INITIAL_ELIMINATION_OFFSET (ep
->from
, ep
->to
, t
);
3763 if (maybe_ne (t
, ep
->initial_offset
))
3770 /* Reset all offsets on eliminable registers to their initial values. */
3773 set_initial_elim_offsets (void)
3775 struct elim_table
*ep
= reg_eliminate
;
3777 targetm
.compute_frame_layout ();
3778 for (; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3780 INITIAL_ELIMINATION_OFFSET (ep
->from
, ep
->to
, ep
->initial_offset
);
3781 ep
->previous_offset
= ep
->offset
= ep
->initial_offset
;
3784 num_not_at_initial_offset
= 0;
3787 /* Subroutine of set_initial_label_offsets called via for_each_eh_label. */
3790 set_initial_eh_label_offset (rtx label
)
3792 set_label_offsets (label
, NULL
, 1);
3795 /* Initialize the known label offsets.
3796 Set a known offset for each forced label to be at the initial offset
3797 of each elimination. We do this because we assume that all
3798 computed jumps occur from a location where each elimination is
3799 at its initial offset.
3800 For all other labels, show that we don't know the offsets. */
3803 set_initial_label_offsets (void)
3805 memset (offsets_known_at
, 0, num_labels
);
3809 FOR_EACH_VEC_SAFE_ELT (forced_labels
, i
, insn
)
3810 set_label_offsets (insn
, NULL
, 1);
3812 for (rtx_insn_list
*x
= nonlocal_goto_handler_labels
; x
; x
= x
->next ())
3814 set_label_offsets (x
->insn (), NULL
, 1);
3816 for_each_eh_label (set_initial_eh_label_offset
);
3819 /* Set all elimination offsets to the known values for the code label given
3823 set_offsets_for_label (rtx_insn
*insn
)
3826 int label_nr
= CODE_LABEL_NUMBER (insn
);
3827 struct elim_table
*ep
;
3829 num_not_at_initial_offset
= 0;
3830 for (i
= 0, ep
= reg_eliminate
; i
< NUM_ELIMINABLE_REGS
; ep
++, i
++)
3832 ep
->offset
= ep
->previous_offset
3833 = offsets_at
[label_nr
- first_label_num
][i
];
3834 if (ep
->can_eliminate
&& maybe_ne (ep
->offset
, ep
->initial_offset
))
3835 num_not_at_initial_offset
++;
3839 /* See if anything that happened changes which eliminations are valid.
3840 For example, on the SPARC, whether or not the frame pointer can
3841 be eliminated can depend on what registers have been used. We need
3842 not check some conditions again (such as flag_omit_frame_pointer)
3843 since they can't have changed. */
3846 update_eliminables (HARD_REG_SET
*pset
)
3848 int previous_frame_pointer_needed
= frame_pointer_needed
;
3849 struct elim_table
*ep
;
3851 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3852 if ((ep
->from
== HARD_FRAME_POINTER_REGNUM
3853 && targetm
.frame_pointer_required ())
3854 || ! targetm
.can_eliminate (ep
->from
, ep
->to
)
3856 ep
->can_eliminate
= 0;
3858 /* Look for the case where we have discovered that we can't replace
3859 register A with register B and that means that we will now be
3860 trying to replace register A with register C. This means we can
3861 no longer replace register C with register B and we need to disable
3862 such an elimination, if it exists. This occurs often with A == ap,
3863 B == sp, and C == fp. */
3865 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3867 struct elim_table
*op
;
3870 if (! ep
->can_eliminate
&& ep
->can_eliminate_previous
)
3872 /* Find the current elimination for ep->from, if there is a
3874 for (op
= reg_eliminate
;
3875 op
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; op
++)
3876 if (op
->from
== ep
->from
&& op
->can_eliminate
)
3882 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
3884 for (op
= reg_eliminate
;
3885 op
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; op
++)
3886 if (op
->from
== new_to
&& op
->to
== ep
->to
)
3887 op
->can_eliminate
= 0;
3891 /* See if any registers that we thought we could eliminate the previous
3892 time are no longer eliminable. If so, something has changed and we
3893 must spill the register. Also, recompute the number of eliminable
3894 registers and see if the frame pointer is needed; it is if there is
3895 no elimination of the frame pointer that we can perform. */
3897 frame_pointer_needed
= 1;
3898 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3900 if (ep
->can_eliminate
3901 && ep
->from
== FRAME_POINTER_REGNUM
3902 && ep
->to
!= HARD_FRAME_POINTER_REGNUM
3903 && (! SUPPORTS_STACK_ALIGNMENT
3904 || ! crtl
->stack_realign_needed
))
3905 frame_pointer_needed
= 0;
3907 if (! ep
->can_eliminate
&& ep
->can_eliminate_previous
)
3909 ep
->can_eliminate_previous
= 0;
3910 SET_HARD_REG_BIT (*pset
, ep
->from
);
3915 /* If we didn't need a frame pointer last time, but we do now, spill
3916 the hard frame pointer. */
3917 if (frame_pointer_needed
&& ! previous_frame_pointer_needed
)
3918 SET_HARD_REG_BIT (*pset
, HARD_FRAME_POINTER_REGNUM
);
3921 /* Call update_eliminables an spill any registers we can't eliminate anymore.
3922 Return true iff a register was spilled. */
3925 update_eliminables_and_spill (void)
3928 bool did_spill
= false;
3929 HARD_REG_SET to_spill
;
3930 CLEAR_HARD_REG_SET (to_spill
);
3931 update_eliminables (&to_spill
);
3932 AND_COMPL_HARD_REG_SET (used_spill_regs
, to_spill
);
3934 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
3935 if (TEST_HARD_REG_BIT (to_spill
, i
))
3937 spill_hard_reg (i
, 1);
3940 /* Regardless of the state of spills, if we previously had
3941 a register that we thought we could eliminate, but now
3942 cannot eliminate, we must run another pass.
3944 Consider pseudos which have an entry in reg_equiv_* which
3945 reference an eliminable register. We must make another pass
3946 to update reg_equiv_* so that we do not substitute in the
3947 old value from when we thought the elimination could be
3953 /* Return true if X is used as the target register of an elimination. */
3956 elimination_target_reg_p (rtx x
)
3958 struct elim_table
*ep
;
3960 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3961 if (ep
->to_rtx
== x
&& ep
->can_eliminate
)
3967 /* Initialize the table of registers to eliminate.
3968 Pre-condition: global flag frame_pointer_needed has been set before
3969 calling this function. */
3972 init_elim_table (void)
3974 struct elim_table
*ep
;
3975 const struct elim_table_1
*ep1
;
3978 reg_eliminate
= XCNEWVEC (struct elim_table
, NUM_ELIMINABLE_REGS
);
3982 for (ep
= reg_eliminate
, ep1
= reg_eliminate_1
;
3983 ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++, ep1
++)
3985 ep
->from
= ep1
->from
;
3987 ep
->can_eliminate
= ep
->can_eliminate_previous
3988 = (targetm
.can_eliminate (ep
->from
, ep
->to
)
3989 && ! (ep
->to
== STACK_POINTER_REGNUM
3990 && frame_pointer_needed
3991 && (! SUPPORTS_STACK_ALIGNMENT
3992 || ! stack_realign_fp
)));
3995 /* Count the number of eliminable registers and build the FROM and TO
3996 REG rtx's. Note that code in gen_rtx_REG will cause, e.g.,
3997 gen_rtx_REG (Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
3998 We depend on this. */
3999 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
4001 num_eliminable
+= ep
->can_eliminate
;
4002 ep
->from_rtx
= gen_rtx_REG (Pmode
, ep
->from
);
4003 ep
->to_rtx
= gen_rtx_REG (Pmode
, ep
->to
);
4007 /* Find all the pseudo registers that didn't get hard regs
4008 but do have known equivalent constants or memory slots.
4009 These include parameters (known equivalent to parameter slots)
4010 and cse'd or loop-moved constant memory addresses.
4012 Record constant equivalents in reg_equiv_constant
4013 so they will be substituted by find_reloads.
4014 Record memory equivalents in reg_mem_equiv so they can
4015 be substituted eventually by altering the REG-rtx's. */
4018 init_eliminable_invariants (rtx_insn
*first
, bool do_subregs
)
4025 reg_max_ref_mode
= XCNEWVEC (machine_mode
, max_regno
);
4027 reg_max_ref_mode
= NULL
;
4029 num_eliminable_invariants
= 0;
4031 first_label_num
= get_first_label_num ();
4032 num_labels
= max_label_num () - first_label_num
;
4034 /* Allocate the tables used to store offset information at labels. */
4035 offsets_known_at
= XNEWVEC (char, num_labels
);
4036 offsets_at
= (poly_int64_pod (*)[NUM_ELIMINABLE_REGS
])
4037 xmalloc (num_labels
* NUM_ELIMINABLE_REGS
* sizeof (poly_int64
));
4039 /* Look for REG_EQUIV notes; record what each pseudo is equivalent
4040 to. If DO_SUBREGS is true, also find all paradoxical subregs and
4041 find largest such for each pseudo. FIRST is the head of the insn
4044 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
4046 rtx set
= single_set (insn
);
4048 /* We may introduce USEs that we want to remove at the end, so
4049 we'll mark them with QImode. Make sure there are no
4050 previously-marked insns left by say regmove. */
4051 if (INSN_P (insn
) && GET_CODE (PATTERN (insn
)) == USE
4052 && GET_MODE (insn
) != VOIDmode
)
4053 PUT_MODE (insn
, VOIDmode
);
4055 if (do_subregs
&& NONDEBUG_INSN_P (insn
))
4056 scan_paradoxical_subregs (PATTERN (insn
));
4058 if (set
!= 0 && REG_P (SET_DEST (set
)))
4060 rtx note
= find_reg_note (insn
, REG_EQUIV
, NULL_RTX
);
4066 i
= REGNO (SET_DEST (set
));
4069 if (i
<= LAST_VIRTUAL_REGISTER
)
4072 /* If flag_pic and we have constant, verify it's legitimate. */
4074 || !flag_pic
|| LEGITIMATE_PIC_OPERAND_P (x
))
4076 /* It can happen that a REG_EQUIV note contains a MEM
4077 that is not a legitimate memory operand. As later
4078 stages of reload assume that all addresses found
4079 in the reg_equiv_* arrays were originally legitimate,
4080 we ignore such REG_EQUIV notes. */
4081 if (memory_operand (x
, VOIDmode
))
4083 /* Always unshare the equivalence, so we can
4084 substitute into this insn without touching the
4086 reg_equiv_memory_loc (i
) = copy_rtx (x
);
4088 else if (function_invariant_p (x
))
4092 mode
= GET_MODE (SET_DEST (set
));
4093 if (GET_CODE (x
) == PLUS
)
4095 /* This is PLUS of frame pointer and a constant,
4096 and might be shared. Unshare it. */
4097 reg_equiv_invariant (i
) = copy_rtx (x
);
4098 num_eliminable_invariants
++;
4100 else if (x
== frame_pointer_rtx
|| x
== arg_pointer_rtx
)
4102 reg_equiv_invariant (i
) = x
;
4103 num_eliminable_invariants
++;
4105 else if (targetm
.legitimate_constant_p (mode
, x
))
4106 reg_equiv_constant (i
) = x
;
4109 reg_equiv_memory_loc (i
) = force_const_mem (mode
, x
);
4110 if (! reg_equiv_memory_loc (i
))
4111 reg_equiv_init (i
) = NULL
;
4116 reg_equiv_init (i
) = NULL
;
4121 reg_equiv_init (i
) = NULL
;
4126 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
4127 if (reg_equiv_init (i
))
4129 fprintf (dump_file
, "init_insns for %u: ", i
);
4130 print_inline_rtx (dump_file
, reg_equiv_init (i
), 20);
4131 fprintf (dump_file
, "\n");
4135 /* Indicate that we no longer have known memory locations or constants.
4136 Free all data involved in tracking these. */
4139 free_reg_equiv (void)
4143 free (offsets_known_at
);
4146 offsets_known_at
= 0;
4148 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
4149 if (reg_equiv_alt_mem_list (i
))
4150 free_EXPR_LIST_list (®_equiv_alt_mem_list (i
));
4151 vec_free (reg_equivs
);
4154 /* Kick all pseudos out of hard register REGNO.
4156 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
4157 because we found we can't eliminate some register. In the case, no pseudos
4158 are allowed to be in the register, even if they are only in a block that
4159 doesn't require spill registers, unlike the case when we are spilling this
4160 hard reg to produce another spill register.
4162 Return nonzero if any pseudos needed to be kicked out. */
4165 spill_hard_reg (unsigned int regno
, int cant_eliminate
)
4171 SET_HARD_REG_BIT (bad_spill_regs_global
, regno
);
4172 df_set_regs_ever_live (regno
, true);
4175 /* Spill every pseudo reg that was allocated to this reg
4176 or to something that overlaps this reg. */
4178 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
4179 if (reg_renumber
[i
] >= 0
4180 && (unsigned int) reg_renumber
[i
] <= regno
4181 && end_hard_regno (PSEUDO_REGNO_MODE (i
), reg_renumber
[i
]) > regno
)
4182 SET_REGNO_REG_SET (&spilled_pseudos
, i
);
4185 /* After spill_hard_reg was called and/or find_reload_regs was run for all
4186 insns that need reloads, this function is used to actually spill pseudo
4187 registers and try to reallocate them. It also sets up the spill_regs
4188 array for use by choose_reload_regs.
4190 GLOBAL nonzero means we should attempt to reallocate any pseudo registers
4191 that we displace from hard registers. */
4194 finish_spills (int global
)
4196 class insn_chain
*chain
;
4197 int something_changed
= 0;
4199 reg_set_iterator rsi
;
4201 /* Build the spill_regs array for the function. */
4202 /* If there are some registers still to eliminate and one of the spill regs
4203 wasn't ever used before, additional stack space may have to be
4204 allocated to store this register. Thus, we may have changed the offset
4205 between the stack and frame pointers, so mark that something has changed.
4207 One might think that we need only set VAL to 1 if this is a call-used
4208 register. However, the set of registers that must be saved by the
4209 prologue is not identical to the call-used set. For example, the
4210 register used by the call insn for the return PC is a call-used register,
4211 but must be saved by the prologue. */
4214 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
4215 if (TEST_HARD_REG_BIT (used_spill_regs
, i
))
4217 spill_reg_order
[i
] = n_spills
;
4218 spill_regs
[n_spills
++] = i
;
4219 if (num_eliminable
&& ! df_regs_ever_live_p (i
))
4220 something_changed
= 1;
4221 df_set_regs_ever_live (i
, true);
4224 spill_reg_order
[i
] = -1;
4226 EXECUTE_IF_SET_IN_REG_SET (&spilled_pseudos
, FIRST_PSEUDO_REGISTER
, i
, rsi
)
4227 if (reg_renumber
[i
] >= 0)
4229 SET_HARD_REG_BIT (pseudo_previous_regs
[i
], reg_renumber
[i
]);
4230 /* Mark it as no longer having a hard register home. */
4231 reg_renumber
[i
] = -1;
4232 if (ira_conflicts_p
)
4233 /* Inform IRA about the change. */
4234 ira_mark_allocation_change (i
);
4235 /* We will need to scan everything again. */
4236 something_changed
= 1;
4239 /* Retry global register allocation if possible. */
4240 if (global
&& ira_conflicts_p
)
4244 memset (pseudo_forbidden_regs
, 0, max_regno
* sizeof (HARD_REG_SET
));
4245 /* For every insn that needs reloads, set the registers used as spill
4246 regs in pseudo_forbidden_regs for every pseudo live across the
4248 for (chain
= insns_need_reload
; chain
; chain
= chain
->next_need_reload
)
4250 EXECUTE_IF_SET_IN_REG_SET
4251 (&chain
->live_throughout
, FIRST_PSEUDO_REGISTER
, i
, rsi
)
4253 pseudo_forbidden_regs
[i
] |= chain
->used_spill_regs
;
4255 EXECUTE_IF_SET_IN_REG_SET
4256 (&chain
->dead_or_set
, FIRST_PSEUDO_REGISTER
, i
, rsi
)
4258 pseudo_forbidden_regs
[i
] |= chain
->used_spill_regs
;
4262 /* Retry allocating the pseudos spilled in IRA and the
4263 reload. For each reg, merge the various reg sets that
4264 indicate which hard regs can't be used, and call
4265 ira_reassign_pseudos. */
4266 for (n
= 0, i
= FIRST_PSEUDO_REGISTER
; i
< (unsigned) max_regno
; i
++)
4267 if (reg_old_renumber
[i
] != reg_renumber
[i
])
4269 if (reg_renumber
[i
] < 0)
4270 temp_pseudo_reg_arr
[n
++] = i
;
4272 CLEAR_REGNO_REG_SET (&spilled_pseudos
, i
);
4274 if (ira_reassign_pseudos (temp_pseudo_reg_arr
, n
,
4275 bad_spill_regs_global
,
4276 pseudo_forbidden_regs
, pseudo_previous_regs
,
4278 something_changed
= 1;
4280 /* Fix up the register information in the insn chain.
4281 This involves deleting those of the spilled pseudos which did not get
4282 a new hard register home from the live_{before,after} sets. */
4283 for (chain
= reload_insn_chain
; chain
; chain
= chain
->next
)
4285 HARD_REG_SET used_by_pseudos
;
4286 HARD_REG_SET used_by_pseudos2
;
4288 if (! ira_conflicts_p
)
4290 /* Don't do it for IRA because IRA and the reload still can
4291 assign hard registers to the spilled pseudos on next
4292 reload iterations. */
4293 AND_COMPL_REG_SET (&chain
->live_throughout
, &spilled_pseudos
);
4294 AND_COMPL_REG_SET (&chain
->dead_or_set
, &spilled_pseudos
);
4296 /* Mark any unallocated hard regs as available for spills. That
4297 makes inheritance work somewhat better. */
4298 if (chain
->need_reload
)
4300 REG_SET_TO_HARD_REG_SET (used_by_pseudos
, &chain
->live_throughout
);
4301 REG_SET_TO_HARD_REG_SET (used_by_pseudos2
, &chain
->dead_or_set
);
4302 used_by_pseudos
|= used_by_pseudos2
;
4304 compute_use_by_pseudos (&used_by_pseudos
, &chain
->live_throughout
);
4305 compute_use_by_pseudos (&used_by_pseudos
, &chain
->dead_or_set
);
4306 /* Value of chain->used_spill_regs from previous iteration
4307 may be not included in the value calculated here because
4308 of possible removing caller-saves insns (see function
4309 delete_caller_save_insns. */
4310 chain
->used_spill_regs
= ~used_by_pseudos
& used_spill_regs
;
4314 CLEAR_REG_SET (&changed_allocation_pseudos
);
4315 /* Let alter_reg modify the reg rtx's for the modified pseudos. */
4316 for (i
= FIRST_PSEUDO_REGISTER
; i
< (unsigned)max_regno
; i
++)
4318 int regno
= reg_renumber
[i
];
4319 if (reg_old_renumber
[i
] == regno
)
4322 SET_REGNO_REG_SET (&changed_allocation_pseudos
, i
);
4324 alter_reg (i
, reg_old_renumber
[i
], false);
4325 reg_old_renumber
[i
] = regno
;
4329 fprintf (dump_file
, " Register %d now on stack.\n\n", i
);
4331 fprintf (dump_file
, " Register %d now in %d.\n\n",
4332 i
, reg_renumber
[i
]);
4336 return something_changed
;
4339 /* Find all paradoxical subregs within X and update reg_max_ref_mode. */
4342 scan_paradoxical_subregs (rtx x
)
4346 enum rtx_code code
= GET_CODE (x
);
4363 if (REG_P (SUBREG_REG (x
)))
4365 unsigned int regno
= REGNO (SUBREG_REG (x
));
4366 if (partial_subreg_p (reg_max_ref_mode
[regno
], GET_MODE (x
)))
4368 reg_max_ref_mode
[regno
] = GET_MODE (x
);
4369 mark_home_live_1 (regno
, GET_MODE (x
));
4378 fmt
= GET_RTX_FORMAT (code
);
4379 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
4382 scan_paradoxical_subregs (XEXP (x
, i
));
4383 else if (fmt
[i
] == 'E')
4386 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
4387 scan_paradoxical_subregs (XVECEXP (x
, i
, j
));
4392 /* *OP_PTR and *OTHER_PTR are two operands to a conceptual reload.
4393 If *OP_PTR is a paradoxical subreg, try to remove that subreg
4394 and apply the corresponding narrowing subreg to *OTHER_PTR.
4395 Return true if the operands were changed, false otherwise. */
4398 strip_paradoxical_subreg (rtx
*op_ptr
, rtx
*other_ptr
)
4400 rtx op
, inner
, other
, tem
;
4403 if (!paradoxical_subreg_p (op
))
4405 inner
= SUBREG_REG (op
);
4408 tem
= gen_lowpart_common (GET_MODE (inner
), other
);
4412 /* If the lowpart operation turned a hard register into a subreg,
4413 rather than simplifying it to another hard register, then the
4414 mode change cannot be properly represented. For example, OTHER
4415 might be valid in its current mode, but not in the new one. */
4416 if (GET_CODE (tem
) == SUBREG
4418 && HARD_REGISTER_P (other
))
4426 /* A subroutine of reload_as_needed. If INSN has a REG_EH_REGION note,
4427 examine all of the reload insns between PREV and NEXT exclusive, and
4428 annotate all that may trap. */
4431 fixup_eh_region_note (rtx_insn
*insn
, rtx_insn
*prev
, rtx_insn
*next
)
4433 rtx note
= find_reg_note (insn
, REG_EH_REGION
, NULL_RTX
);
4436 if (!insn_could_throw_p (insn
))
4437 remove_note (insn
, note
);
4438 copy_reg_eh_region_note_forward (note
, NEXT_INSN (prev
), next
);
4441 /* Reload pseudo-registers into hard regs around each insn as needed.
4442 Additional register load insns are output before the insn that needs it
4443 and perhaps store insns after insns that modify the reloaded pseudo reg.
4445 reg_last_reload_reg and reg_reloaded_contents keep track of
4446 which registers are already available in reload registers.
4447 We update these for the reloads that we perform,
4448 as the insns are scanned. */
4451 reload_as_needed (int live_known
)
4453 class insn_chain
*chain
;
4459 memset (spill_reg_rtx
, 0, sizeof spill_reg_rtx
);
4460 memset (spill_reg_store
, 0, sizeof spill_reg_store
);
4461 reg_last_reload_reg
= XCNEWVEC (rtx
, max_regno
);
4462 INIT_REG_SET (®_has_output_reload
);
4463 CLEAR_HARD_REG_SET (reg_reloaded_valid
);
4464 CLEAR_HARD_REG_SET (reg_reloaded_call_part_clobbered
);
4466 set_initial_elim_offsets ();
4468 /* Generate a marker insn that we will move around. */
4469 marker
= emit_note (NOTE_INSN_DELETED
);
4470 unlink_insn_chain (marker
, marker
);
4472 for (chain
= reload_insn_chain
; chain
; chain
= chain
->next
)
4475 rtx_insn
*insn
= chain
->insn
;
4476 rtx_insn
*old_next
= NEXT_INSN (insn
);
4478 rtx_insn
*old_prev
= PREV_INSN (insn
);
4481 if (will_delete_init_insn_p (insn
))
4484 /* If we pass a label, copy the offsets from the label information
4485 into the current offsets of each elimination. */
4487 set_offsets_for_label (insn
);
4489 else if (INSN_P (insn
))
4491 regset_head regs_to_forget
;
4492 INIT_REG_SET (®s_to_forget
);
4493 note_stores (insn
, forget_old_reloads_1
, ®s_to_forget
);
4495 /* If this is a USE and CLOBBER of a MEM, ensure that any
4496 references to eliminable registers have been removed. */
4498 if ((GET_CODE (PATTERN (insn
)) == USE
4499 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
4500 && MEM_P (XEXP (PATTERN (insn
), 0)))
4501 XEXP (XEXP (PATTERN (insn
), 0), 0)
4502 = eliminate_regs (XEXP (XEXP (PATTERN (insn
), 0), 0),
4503 GET_MODE (XEXP (PATTERN (insn
), 0)),
4506 /* If we need to do register elimination processing, do so.
4507 This might delete the insn, in which case we are done. */
4508 if ((num_eliminable
|| num_eliminable_invariants
) && chain
->need_elim
)
4510 eliminate_regs_in_insn (insn
, 1);
4513 update_eliminable_offsets ();
4514 CLEAR_REG_SET (®s_to_forget
);
4519 /* If need_elim is nonzero but need_reload is zero, one might think
4520 that we could simply set n_reloads to 0. However, find_reloads
4521 could have done some manipulation of the insn (such as swapping
4522 commutative operands), and these manipulations are lost during
4523 the first pass for every insn that needs register elimination.
4524 So the actions of find_reloads must be redone here. */
4526 if (! chain
->need_elim
&& ! chain
->need_reload
4527 && ! chain
->need_operand_change
)
4529 /* First find the pseudo regs that must be reloaded for this insn.
4530 This info is returned in the tables reload_... (see reload.h).
4531 Also modify the body of INSN by substituting RELOAD
4532 rtx's for those pseudo regs. */
4535 CLEAR_REG_SET (®_has_output_reload
);
4536 CLEAR_HARD_REG_SET (reg_is_output_reload
);
4538 find_reloads (insn
, 1, spill_indirect_levels
, live_known
,
4544 rtx_insn
*next
= NEXT_INSN (insn
);
4546 /* ??? PREV can get deleted by reload inheritance.
4547 Work around this by emitting a marker note. */
4548 prev
= PREV_INSN (insn
);
4549 reorder_insns_nobb (marker
, marker
, prev
);
4551 /* Now compute which reload regs to reload them into. Perhaps
4552 reusing reload regs from previous insns, or else output
4553 load insns to reload them. Maybe output store insns too.
4554 Record the choices of reload reg in reload_reg_rtx. */
4555 choose_reload_regs (chain
);
4557 /* Generate the insns to reload operands into or out of
4558 their reload regs. */
4559 emit_reload_insns (chain
);
4561 /* Substitute the chosen reload regs from reload_reg_rtx
4562 into the insn's body (or perhaps into the bodies of other
4563 load and store insn that we just made for reloading
4564 and that we moved the structure into). */
4565 subst_reloads (insn
);
4567 prev
= PREV_INSN (marker
);
4568 unlink_insn_chain (marker
, marker
);
4570 /* Adjust the exception region notes for loads and stores. */
4571 if (cfun
->can_throw_non_call_exceptions
&& !CALL_P (insn
))
4572 fixup_eh_region_note (insn
, prev
, next
);
4574 /* Adjust the location of REG_ARGS_SIZE. */
4575 rtx p
= find_reg_note (insn
, REG_ARGS_SIZE
, NULL_RTX
);
4578 remove_note (insn
, p
);
4579 fixup_args_size_notes (prev
, PREV_INSN (next
),
4583 /* If this was an ASM, make sure that all the reload insns
4584 we have generated are valid. If not, give an error
4586 if (asm_noperands (PATTERN (insn
)) >= 0)
4587 for (rtx_insn
*p
= NEXT_INSN (prev
);
4590 if (p
!= insn
&& INSN_P (p
)
4591 && GET_CODE (PATTERN (p
)) != USE
4592 && (recog_memoized (p
) < 0
4593 || (extract_insn (p
),
4594 !(constrain_operands (1,
4595 get_enabled_alternatives (p
))))))
4597 error_for_asm (insn
,
4598 "%<asm%> operand requires "
4599 "impossible reload");
4604 if (num_eliminable
&& chain
->need_elim
)
4605 update_eliminable_offsets ();
4607 /* Any previously reloaded spilled pseudo reg, stored in this insn,
4608 is no longer validly lying around to save a future reload.
4609 Note that this does not detect pseudos that were reloaded
4610 for this insn in order to be stored in
4611 (obeying register constraints). That is correct; such reload
4612 registers ARE still valid. */
4613 forget_marked_reloads (®s_to_forget
);
4614 CLEAR_REG_SET (®s_to_forget
);
4616 /* There may have been CLOBBER insns placed after INSN. So scan
4617 between INSN and NEXT and use them to forget old reloads. */
4618 for (rtx_insn
*x
= NEXT_INSN (insn
); x
!= old_next
; x
= NEXT_INSN (x
))
4619 if (NONJUMP_INSN_P (x
) && GET_CODE (PATTERN (x
)) == CLOBBER
)
4620 note_stores (x
, forget_old_reloads_1
, NULL
);
4623 /* Likewise for regs altered by auto-increment in this insn.
4624 REG_INC notes have been changed by reloading:
4625 find_reloads_address_1 records substitutions for them,
4626 which have been performed by subst_reloads above. */
4627 for (i
= n_reloads
- 1; i
>= 0; i
--)
4629 rtx in_reg
= rld
[i
].in_reg
;
4632 enum rtx_code code
= GET_CODE (in_reg
);
4633 /* PRE_INC / PRE_DEC will have the reload register ending up
4634 with the same value as the stack slot, but that doesn't
4635 hold true for POST_INC / POST_DEC. Either we have to
4636 convert the memory access to a true POST_INC / POST_DEC,
4637 or we can't use the reload register for inheritance. */
4638 if ((code
== POST_INC
|| code
== POST_DEC
)
4639 && TEST_HARD_REG_BIT (reg_reloaded_valid
,
4640 REGNO (rld
[i
].reg_rtx
))
4641 /* Make sure it is the inc/dec pseudo, and not
4642 some other (e.g. output operand) pseudo. */
4643 && ((unsigned) reg_reloaded_contents
[REGNO (rld
[i
].reg_rtx
)]
4644 == REGNO (XEXP (in_reg
, 0))))
4647 rtx reload_reg
= rld
[i
].reg_rtx
;
4648 machine_mode mode
= GET_MODE (reload_reg
);
4652 for (p
= PREV_INSN (old_next
); p
!= prev
; p
= PREV_INSN (p
))
4654 /* We really want to ignore REG_INC notes here, so
4655 use PATTERN (p) as argument to reg_set_p . */
4656 if (reg_set_p (reload_reg
, PATTERN (p
)))
4658 n
= count_occurrences (PATTERN (p
), reload_reg
, 0);
4664 = gen_rtx_fmt_e (code
, mode
, reload_reg
);
4666 validate_replace_rtx_group (reload_reg
,
4668 n
= verify_changes (0);
4670 /* We must also verify that the constraints
4671 are met after the replacement. Make sure
4672 extract_insn is only called for an insn
4673 where the replacements were found to be
4678 n
= constrain_operands (1,
4679 get_enabled_alternatives (p
));
4682 /* If the constraints were not met, then
4683 undo the replacement, else confirm it. */
4687 confirm_change_group ();
4693 add_reg_note (p
, REG_INC
, reload_reg
);
4694 /* Mark this as having an output reload so that the
4695 REG_INC processing code below won't invalidate
4696 the reload for inheritance. */
4697 SET_HARD_REG_BIT (reg_is_output_reload
,
4698 REGNO (reload_reg
));
4699 SET_REGNO_REG_SET (®_has_output_reload
,
4700 REGNO (XEXP (in_reg
, 0)));
4703 forget_old_reloads_1 (XEXP (in_reg
, 0), NULL_RTX
,
4706 else if ((code
== PRE_INC
|| code
== PRE_DEC
)
4707 && TEST_HARD_REG_BIT (reg_reloaded_valid
,
4708 REGNO (rld
[i
].reg_rtx
))
4709 /* Make sure it is the inc/dec pseudo, and not
4710 some other (e.g. output operand) pseudo. */
4711 && ((unsigned) reg_reloaded_contents
[REGNO (rld
[i
].reg_rtx
)]
4712 == REGNO (XEXP (in_reg
, 0))))
4714 SET_HARD_REG_BIT (reg_is_output_reload
,
4715 REGNO (rld
[i
].reg_rtx
));
4716 SET_REGNO_REG_SET (®_has_output_reload
,
4717 REGNO (XEXP (in_reg
, 0)));
4719 else if (code
== PRE_INC
|| code
== PRE_DEC
4720 || code
== POST_INC
|| code
== POST_DEC
)
4722 int in_regno
= REGNO (XEXP (in_reg
, 0));
4724 if (reg_last_reload_reg
[in_regno
] != NULL_RTX
)
4727 bool forget_p
= true;
4729 in_hard_regno
= REGNO (reg_last_reload_reg
[in_regno
]);
4730 if (TEST_HARD_REG_BIT (reg_reloaded_valid
,
4733 for (rtx_insn
*x
= (old_prev
?
4734 NEXT_INSN (old_prev
) : insn
);
4737 if (x
== reg_reloaded_insn
[in_hard_regno
])
4743 /* If for some reasons, we didn't set up
4744 reg_last_reload_reg in this insn,
4745 invalidate inheritance from previous
4746 insns for the incremented/decremented
4747 register. Such registers will be not in
4748 reg_has_output_reload. Invalidate it
4749 also if the corresponding element in
4750 reg_reloaded_insn is also
4753 forget_old_reloads_1 (XEXP (in_reg
, 0),
4759 /* If a pseudo that got a hard register is auto-incremented,
4760 we must purge records of copying it into pseudos without
4762 for (rtx x
= REG_NOTES (insn
); x
; x
= XEXP (x
, 1))
4763 if (REG_NOTE_KIND (x
) == REG_INC
)
4765 /* See if this pseudo reg was reloaded in this insn.
4766 If so, its last-reload info is still valid
4767 because it is based on this insn's reload. */
4768 for (i
= 0; i
< n_reloads
; i
++)
4769 if (rld
[i
].out
== XEXP (x
, 0))
4773 forget_old_reloads_1 (XEXP (x
, 0), NULL_RTX
, NULL
);
4777 /* A reload reg's contents are unknown after a label. */
4779 CLEAR_HARD_REG_SET (reg_reloaded_valid
);
4781 /* Don't assume a reload reg is still good after a call insn
4782 if it is a call-used reg, or if it contains a value that will
4783 be partially clobbered by the call. */
4784 else if (CALL_P (insn
))
4786 AND_COMPL_HARD_REG_SET (reg_reloaded_valid
, call_used_reg_set
);
4787 AND_COMPL_HARD_REG_SET (reg_reloaded_valid
, reg_reloaded_call_part_clobbered
);
4789 /* If this is a call to a setjmp-type function, we must not
4790 reuse any reload reg contents across the call; that will
4791 just be clobbered by other uses of the register in later
4792 code, before the longjmp. */
4793 if (find_reg_note (insn
, REG_SETJMP
, NULL_RTX
))
4794 CLEAR_HARD_REG_SET (reg_reloaded_valid
);
4799 free (reg_last_reload_reg
);
4800 CLEAR_REG_SET (®_has_output_reload
);
4803 /* Discard all record of any value reloaded from X,
4804 or reloaded in X from someplace else;
4805 unless X is an output reload reg of the current insn.
4807 X may be a hard reg (the reload reg)
4808 or it may be a pseudo reg that was reloaded from.
4810 When DATA is non-NULL just mark the registers in regset
4811 to be forgotten later. */
4814 forget_old_reloads_1 (rtx x
, const_rtx setter
,
4819 regset regs
= (regset
) data
;
4821 /* note_stores does give us subregs of hard regs,
4822 subreg_regno_offset requires a hard reg. */
4823 while (GET_CODE (x
) == SUBREG
)
4825 /* We ignore the subreg offset when calculating the regno,
4826 because we are using the entire underlying hard register
4834 /* CLOBBER_HIGH is only supported for LRA. */
4835 gcc_assert (setter
== NULL_RTX
|| GET_CODE (setter
) != CLOBBER_HIGH
);
4839 if (regno
>= FIRST_PSEUDO_REGISTER
)
4846 /* Storing into a spilled-reg invalidates its contents.
4847 This can happen if a block-local pseudo is allocated to that reg
4848 and it wasn't spilled because this block's total need is 0.
4849 Then some insn might have an optional reload and use this reg. */
4851 for (i
= 0; i
< nr
; i
++)
4852 /* But don't do this if the reg actually serves as an output
4853 reload reg in the current instruction. */
4855 || ! TEST_HARD_REG_BIT (reg_is_output_reload
, regno
+ i
))
4857 CLEAR_HARD_REG_BIT (reg_reloaded_valid
, regno
+ i
);
4858 spill_reg_store
[regno
+ i
] = 0;
4864 SET_REGNO_REG_SET (regs
, regno
+ nr
);
4867 /* Since value of X has changed,
4868 forget any value previously copied from it. */
4871 /* But don't forget a copy if this is the output reload
4872 that establishes the copy's validity. */
4874 || !REGNO_REG_SET_P (®_has_output_reload
, regno
+ nr
))
4875 reg_last_reload_reg
[regno
+ nr
] = 0;
4879 /* Forget the reloads marked in regset by previous function. */
4881 forget_marked_reloads (regset regs
)
4884 reg_set_iterator rsi
;
4885 EXECUTE_IF_SET_IN_REG_SET (regs
, 0, reg
, rsi
)
4887 if (reg
< FIRST_PSEUDO_REGISTER
4888 /* But don't do this if the reg actually serves as an output
4889 reload reg in the current instruction. */
4891 || ! TEST_HARD_REG_BIT (reg_is_output_reload
, reg
)))
4893 CLEAR_HARD_REG_BIT (reg_reloaded_valid
, reg
);
4894 spill_reg_store
[reg
] = 0;
4897 || !REGNO_REG_SET_P (®_has_output_reload
, reg
))
4898 reg_last_reload_reg
[reg
] = 0;
4902 /* The following HARD_REG_SETs indicate when each hard register is
4903 used for a reload of various parts of the current insn. */
4905 /* If reg is unavailable for all reloads. */
4906 static HARD_REG_SET reload_reg_unavailable
;
4907 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
4908 static HARD_REG_SET reload_reg_used
;
4909 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
4910 static HARD_REG_SET reload_reg_used_in_input_addr
[MAX_RECOG_OPERANDS
];
4911 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */
4912 static HARD_REG_SET reload_reg_used_in_inpaddr_addr
[MAX_RECOG_OPERANDS
];
4913 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
4914 static HARD_REG_SET reload_reg_used_in_output_addr
[MAX_RECOG_OPERANDS
];
4915 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */
4916 static HARD_REG_SET reload_reg_used_in_outaddr_addr
[MAX_RECOG_OPERANDS
];
4917 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
4918 static HARD_REG_SET reload_reg_used_in_input
[MAX_RECOG_OPERANDS
];
4919 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
4920 static HARD_REG_SET reload_reg_used_in_output
[MAX_RECOG_OPERANDS
];
4921 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
4922 static HARD_REG_SET reload_reg_used_in_op_addr
;
4923 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */
4924 static HARD_REG_SET reload_reg_used_in_op_addr_reload
;
4925 /* If reg is in use for a RELOAD_FOR_INSN reload. */
4926 static HARD_REG_SET reload_reg_used_in_insn
;
4927 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
4928 static HARD_REG_SET reload_reg_used_in_other_addr
;
4930 /* If reg is in use as a reload reg for any sort of reload. */
4931 static HARD_REG_SET reload_reg_used_at_all
;
4933 /* If reg is use as an inherited reload. We just mark the first register
4935 static HARD_REG_SET reload_reg_used_for_inherit
;
4937 /* Records which hard regs are used in any way, either as explicit use or
4938 by being allocated to a pseudo during any point of the current insn. */
4939 static HARD_REG_SET reg_used_in_insn
;
4941 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
4942 TYPE. MODE is used to indicate how many consecutive regs are
4946 mark_reload_reg_in_use (unsigned int regno
, int opnum
, enum reload_type type
,
4952 add_to_hard_reg_set (&reload_reg_used
, mode
, regno
);
4955 case RELOAD_FOR_INPUT_ADDRESS
:
4956 add_to_hard_reg_set (&reload_reg_used_in_input_addr
[opnum
], mode
, regno
);
4959 case RELOAD_FOR_INPADDR_ADDRESS
:
4960 add_to_hard_reg_set (&reload_reg_used_in_inpaddr_addr
[opnum
], mode
, regno
);
4963 case RELOAD_FOR_OUTPUT_ADDRESS
:
4964 add_to_hard_reg_set (&reload_reg_used_in_output_addr
[opnum
], mode
, regno
);
4967 case RELOAD_FOR_OUTADDR_ADDRESS
:
4968 add_to_hard_reg_set (&reload_reg_used_in_outaddr_addr
[opnum
], mode
, regno
);
4971 case RELOAD_FOR_OPERAND_ADDRESS
:
4972 add_to_hard_reg_set (&reload_reg_used_in_op_addr
, mode
, regno
);
4975 case RELOAD_FOR_OPADDR_ADDR
:
4976 add_to_hard_reg_set (&reload_reg_used_in_op_addr_reload
, mode
, regno
);
4979 case RELOAD_FOR_OTHER_ADDRESS
:
4980 add_to_hard_reg_set (&reload_reg_used_in_other_addr
, mode
, regno
);
4983 case RELOAD_FOR_INPUT
:
4984 add_to_hard_reg_set (&reload_reg_used_in_input
[opnum
], mode
, regno
);
4987 case RELOAD_FOR_OUTPUT
:
4988 add_to_hard_reg_set (&reload_reg_used_in_output
[opnum
], mode
, regno
);
4991 case RELOAD_FOR_INSN
:
4992 add_to_hard_reg_set (&reload_reg_used_in_insn
, mode
, regno
);
4996 add_to_hard_reg_set (&reload_reg_used_at_all
, mode
, regno
);
4999 /* Similarly, but show REGNO is no longer in use for a reload. */
5002 clear_reload_reg_in_use (unsigned int regno
, int opnum
,
5003 enum reload_type type
, machine_mode mode
)
5005 unsigned int nregs
= hard_regno_nregs (regno
, mode
);
5006 unsigned int start_regno
, end_regno
, r
;
5008 /* A complication is that for some reload types, inheritance might
5009 allow multiple reloads of the same types to share a reload register.
5010 We set check_opnum if we have to check only reloads with the same
5011 operand number, and check_any if we have to check all reloads. */
5012 int check_opnum
= 0;
5014 HARD_REG_SET
*used_in_set
;
5019 used_in_set
= &reload_reg_used
;
5022 case RELOAD_FOR_INPUT_ADDRESS
:
5023 used_in_set
= &reload_reg_used_in_input_addr
[opnum
];
5026 case RELOAD_FOR_INPADDR_ADDRESS
:
5028 used_in_set
= &reload_reg_used_in_inpaddr_addr
[opnum
];
5031 case RELOAD_FOR_OUTPUT_ADDRESS
:
5032 used_in_set
= &reload_reg_used_in_output_addr
[opnum
];
5035 case RELOAD_FOR_OUTADDR_ADDRESS
:
5037 used_in_set
= &reload_reg_used_in_outaddr_addr
[opnum
];
5040 case RELOAD_FOR_OPERAND_ADDRESS
:
5041 used_in_set
= &reload_reg_used_in_op_addr
;
5044 case RELOAD_FOR_OPADDR_ADDR
:
5046 used_in_set
= &reload_reg_used_in_op_addr_reload
;
5049 case RELOAD_FOR_OTHER_ADDRESS
:
5050 used_in_set
= &reload_reg_used_in_other_addr
;
5054 case RELOAD_FOR_INPUT
:
5055 used_in_set
= &reload_reg_used_in_input
[opnum
];
5058 case RELOAD_FOR_OUTPUT
:
5059 used_in_set
= &reload_reg_used_in_output
[opnum
];
5062 case RELOAD_FOR_INSN
:
5063 used_in_set
= &reload_reg_used_in_insn
;
5068 /* We resolve conflicts with remaining reloads of the same type by
5069 excluding the intervals of reload registers by them from the
5070 interval of freed reload registers. Since we only keep track of
5071 one set of interval bounds, we might have to exclude somewhat
5072 more than what would be necessary if we used a HARD_REG_SET here.
5073 But this should only happen very infrequently, so there should
5074 be no reason to worry about it. */
5076 start_regno
= regno
;
5077 end_regno
= regno
+ nregs
;
5078 if (check_opnum
|| check_any
)
5080 for (i
= n_reloads
- 1; i
>= 0; i
--)
5082 if (rld
[i
].when_needed
== type
5083 && (check_any
|| rld
[i
].opnum
== opnum
)
5086 unsigned int conflict_start
= true_regnum (rld
[i
].reg_rtx
);
5087 unsigned int conflict_end
5088 = end_hard_regno (rld
[i
].mode
, conflict_start
);
5090 /* If there is an overlap with the first to-be-freed register,
5091 adjust the interval start. */
5092 if (conflict_start
<= start_regno
&& conflict_end
> start_regno
)
5093 start_regno
= conflict_end
;
5094 /* Otherwise, if there is a conflict with one of the other
5095 to-be-freed registers, adjust the interval end. */
5096 if (conflict_start
> start_regno
&& conflict_start
< end_regno
)
5097 end_regno
= conflict_start
;
5102 for (r
= start_regno
; r
< end_regno
; r
++)
5103 CLEAR_HARD_REG_BIT (*used_in_set
, r
);
5106 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
5107 specified by OPNUM and TYPE. */
5110 reload_reg_free_p (unsigned int regno
, int opnum
, enum reload_type type
)
5114 /* In use for a RELOAD_OTHER means it's not available for anything. */
5115 if (TEST_HARD_REG_BIT (reload_reg_used
, regno
)
5116 || TEST_HARD_REG_BIT (reload_reg_unavailable
, regno
))
5122 /* In use for anything means we can't use it for RELOAD_OTHER. */
5123 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr
, regno
)
5124 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
)
5125 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload
, regno
)
5126 || TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
))
5129 for (i
= 0; i
< reload_n_operands
; i
++)
5130 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
5131 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
)
5132 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
5133 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
)
5134 || TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
)
5135 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
5140 case RELOAD_FOR_INPUT
:
5141 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
5142 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
))
5145 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload
, regno
))
5148 /* If it is used for some other input, can't use it. */
5149 for (i
= 0; i
< reload_n_operands
; i
++)
5150 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
5153 /* If it is used in a later operand's address, can't use it. */
5154 for (i
= opnum
+ 1; i
< reload_n_operands
; i
++)
5155 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
5156 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
))
5161 case RELOAD_FOR_INPUT_ADDRESS
:
5162 /* Can't use a register if it is used for an input address for this
5163 operand or used as an input in an earlier one. */
5164 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[opnum
], regno
)
5165 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[opnum
], regno
))
5168 for (i
= 0; i
< opnum
; i
++)
5169 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
5174 case RELOAD_FOR_INPADDR_ADDRESS
:
5175 /* Can't use a register if it is used for an input address
5176 for this operand or used as an input in an earlier
5178 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[opnum
], regno
))
5181 for (i
= 0; i
< opnum
; i
++)
5182 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
5187 case RELOAD_FOR_OUTPUT_ADDRESS
:
5188 /* Can't use a register if it is used for an output address for this
5189 operand or used as an output in this or a later operand. Note
5190 that multiple output operands are emitted in reverse order, so
5191 the conflicting ones are those with lower indices. */
5192 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[opnum
], regno
))
5195 for (i
= 0; i
<= opnum
; i
++)
5196 if (TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
5201 case RELOAD_FOR_OUTADDR_ADDRESS
:
5202 /* Can't use a register if it is used for an output address
5203 for this operand or used as an output in this or a
5204 later operand. Note that multiple output operands are
5205 emitted in reverse order, so the conflicting ones are
5206 those with lower indices. */
5207 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[opnum
], regno
))
5210 for (i
= 0; i
<= opnum
; i
++)
5211 if (TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
5216 case RELOAD_FOR_OPERAND_ADDRESS
:
5217 for (i
= 0; i
< reload_n_operands
; i
++)
5218 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
5221 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
5222 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
));
5224 case RELOAD_FOR_OPADDR_ADDR
:
5225 for (i
= 0; i
< reload_n_operands
; i
++)
5226 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
5229 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload
, regno
));
5231 case RELOAD_FOR_OUTPUT
:
5232 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
5233 outputs, or an operand address for this or an earlier output.
5234 Note that multiple output operands are emitted in reverse order,
5235 so the conflicting ones are those with higher indices. */
5236 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
))
5239 for (i
= 0; i
< reload_n_operands
; i
++)
5240 if (TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
5243 for (i
= opnum
; i
< reload_n_operands
; i
++)
5244 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
5245 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
))
5250 case RELOAD_FOR_INSN
:
5251 for (i
= 0; i
< reload_n_operands
; i
++)
5252 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
)
5253 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
5256 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
5257 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
));
5259 case RELOAD_FOR_OTHER_ADDRESS
:
5260 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr
, regno
);
5267 /* Return 1 if the value in reload reg REGNO, as used by the reload with
5268 the number RELOADNUM, is still available in REGNO at the end of the insn.
5270 We can assume that the reload reg was already tested for availability
5271 at the time it is needed, and we should not check this again,
5272 in case the reg has already been marked in use. */
5275 reload_reg_reaches_end_p (unsigned int regno
, int reloadnum
)
5277 int opnum
= rld
[reloadnum
].opnum
;
5278 enum reload_type type
= rld
[reloadnum
].when_needed
;
5281 /* See if there is a reload with the same type for this operand, using
5282 the same register. This case is not handled by the code below. */
5283 for (i
= reloadnum
+ 1; i
< n_reloads
; i
++)
5287 if (rld
[i
].opnum
!= opnum
|| rld
[i
].when_needed
!= type
)
5289 reg
= rld
[i
].reg_rtx
;
5290 if (reg
== NULL_RTX
)
5292 if (regno
>= REGNO (reg
) && regno
< END_REGNO (reg
))
5299 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
5300 its value must reach the end. */
5303 /* If this use is for part of the insn,
5304 its value reaches if no subsequent part uses the same register.
5305 Just like the above function, don't try to do this with lots
5308 case RELOAD_FOR_OTHER_ADDRESS
:
5309 /* Here we check for everything else, since these don't conflict
5310 with anything else and everything comes later. */
5312 for (i
= 0; i
< reload_n_operands
; i
++)
5313 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
5314 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
)
5315 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
)
5316 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
5317 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
)
5318 || TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
5321 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
)
5322 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload
, regno
)
5323 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
5324 && ! TEST_HARD_REG_BIT (reload_reg_used
, regno
));
5326 case RELOAD_FOR_INPUT_ADDRESS
:
5327 case RELOAD_FOR_INPADDR_ADDRESS
:
5328 /* Similar, except that we check only for this and subsequent inputs
5329 and the address of only subsequent inputs and we do not need
5330 to check for RELOAD_OTHER objects since they are known not to
5333 for (i
= opnum
; i
< reload_n_operands
; i
++)
5334 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
5337 /* Reload register of reload with type RELOAD_FOR_INPADDR_ADDRESS
5338 could be killed if the register is also used by reload with type
5339 RELOAD_FOR_INPUT_ADDRESS, so check it. */
5340 if (type
== RELOAD_FOR_INPADDR_ADDRESS
5341 && TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[opnum
], regno
))
5344 for (i
= opnum
+ 1; i
< reload_n_operands
; i
++)
5345 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
5346 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
))
5349 for (i
= 0; i
< reload_n_operands
; i
++)
5350 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
5351 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
)
5352 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
5355 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload
, regno
))
5358 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
)
5359 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
5360 && !TEST_HARD_REG_BIT (reload_reg_used
, regno
));
5362 case RELOAD_FOR_INPUT
:
5363 /* Similar to input address, except we start at the next operand for
5364 both input and input address and we do not check for
5365 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
5368 for (i
= opnum
+ 1; i
< reload_n_operands
; i
++)
5369 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
5370 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
)
5371 || TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
5374 /* ... fall through ... */
5376 case RELOAD_FOR_OPERAND_ADDRESS
:
5377 /* Check outputs and their addresses. */
5379 for (i
= 0; i
< reload_n_operands
; i
++)
5380 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
5381 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
)
5382 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
5385 return (!TEST_HARD_REG_BIT (reload_reg_used
, regno
));
5387 case RELOAD_FOR_OPADDR_ADDR
:
5388 for (i
= 0; i
< reload_n_operands
; i
++)
5389 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
5390 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
)
5391 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
5394 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
)
5395 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
5396 && !TEST_HARD_REG_BIT (reload_reg_used
, regno
));
5398 case RELOAD_FOR_INSN
:
5399 /* These conflict with other outputs with RELOAD_OTHER. So
5400 we need only check for output addresses. */
5402 opnum
= reload_n_operands
;
5406 case RELOAD_FOR_OUTPUT
:
5407 case RELOAD_FOR_OUTPUT_ADDRESS
:
5408 case RELOAD_FOR_OUTADDR_ADDRESS
:
5409 /* We already know these can't conflict with a later output. So the
5410 only thing to check are later output addresses.
5411 Note that multiple output operands are emitted in reverse order,
5412 so the conflicting ones are those with lower indices. */
5413 for (i
= 0; i
< opnum
; i
++)
5414 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
5415 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
))
5418 /* Reload register of reload with type RELOAD_FOR_OUTADDR_ADDRESS
5419 could be killed if the register is also used by reload with type
5420 RELOAD_FOR_OUTPUT_ADDRESS, so check it. */
5421 if (type
== RELOAD_FOR_OUTADDR_ADDRESS
5422 && TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[opnum
], regno
))
5432 /* Like reload_reg_reaches_end_p, but check that the condition holds for
5433 every register in REG. */
5436 reload_reg_rtx_reaches_end_p (rtx reg
, int reloadnum
)
5440 for (i
= REGNO (reg
); i
< END_REGNO (reg
); i
++)
5441 if (!reload_reg_reaches_end_p (i
, reloadnum
))
5447 /* Returns whether R1 and R2 are uniquely chained: the value of one
5448 is used by the other, and that value is not used by any other
5449 reload for this insn. This is used to partially undo the decision
5450 made in find_reloads when in the case of multiple
5451 RELOAD_FOR_OPERAND_ADDRESS reloads it converts all
5452 RELOAD_FOR_OPADDR_ADDR reloads into RELOAD_FOR_OPERAND_ADDRESS
5453 reloads. This code tries to avoid the conflict created by that
5454 change. It might be cleaner to explicitly keep track of which
5455 RELOAD_FOR_OPADDR_ADDR reload is associated with which
5456 RELOAD_FOR_OPERAND_ADDRESS reload, rather than to try to detect
5457 this after the fact. */
5459 reloads_unique_chain_p (int r1
, int r2
)
5463 /* We only check input reloads. */
5464 if (! rld
[r1
].in
|| ! rld
[r2
].in
)
5467 /* Avoid anything with output reloads. */
5468 if (rld
[r1
].out
|| rld
[r2
].out
)
5471 /* "chained" means one reload is a component of the other reload,
5472 not the same as the other reload. */
5473 if (rld
[r1
].opnum
!= rld
[r2
].opnum
5474 || rtx_equal_p (rld
[r1
].in
, rld
[r2
].in
)
5475 || rld
[r1
].optional
|| rld
[r2
].optional
5476 || ! (reg_mentioned_p (rld
[r1
].in
, rld
[r2
].in
)
5477 || reg_mentioned_p (rld
[r2
].in
, rld
[r1
].in
)))
5480 /* The following loop assumes that r1 is the reload that feeds r2. */
5484 for (i
= 0; i
< n_reloads
; i
++)
5485 /* Look for input reloads that aren't our two */
5486 if (i
!= r1
&& i
!= r2
&& rld
[i
].in
)
5488 /* If our reload is mentioned at all, it isn't a simple chain. */
5489 if (reg_mentioned_p (rld
[r1
].in
, rld
[i
].in
))
5495 /* The recursive function change all occurrences of WHAT in *WHERE
5498 substitute (rtx
*where
, const_rtx what
, rtx repl
)
5507 if (*where
== what
|| rtx_equal_p (*where
, what
))
5509 /* Record the location of the changed rtx. */
5510 substitute_stack
.safe_push (where
);
5515 code
= GET_CODE (*where
);
5516 fmt
= GET_RTX_FORMAT (code
);
5517 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
5523 for (j
= XVECLEN (*where
, i
) - 1; j
>= 0; j
--)
5524 substitute (&XVECEXP (*where
, i
, j
), what
, repl
);
5526 else if (fmt
[i
] == 'e')
5527 substitute (&XEXP (*where
, i
), what
, repl
);
5531 /* The function returns TRUE if chain of reload R1 and R2 (in any
5532 order) can be evaluated without usage of intermediate register for
5533 the reload containing another reload. It is important to see
5534 gen_reload to understand what the function is trying to do. As an
5535 example, let us have reload chain
5538 r1: <something> + const
5540 and reload R2 got reload reg HR. The function returns true if
5541 there is a correct insn HR = HR + <something>. Otherwise,
5542 gen_reload will use intermediate register (and this is the reload
5543 reg for R1) to reload <something>.
5545 We need this function to find a conflict for chain reloads. In our
5546 example, if HR = HR + <something> is incorrect insn, then we cannot
5547 use HR as a reload register for R2. If we do use it then we get a
5556 gen_reload_chain_without_interm_reg_p (int r1
, int r2
)
5558 /* Assume other cases in gen_reload are not possible for
5559 chain reloads or do need an intermediate hard registers. */
5564 rtx_insn
*last
= get_last_insn ();
5566 /* Make r2 a component of r1. */
5567 if (reg_mentioned_p (rld
[r1
].in
, rld
[r2
].in
))
5570 gcc_assert (reg_mentioned_p (rld
[r2
].in
, rld
[r1
].in
));
5571 regno
= rld
[r1
].regno
>= 0 ? rld
[r1
].regno
: rld
[r2
].regno
;
5572 gcc_assert (regno
>= 0);
5573 out
= gen_rtx_REG (rld
[r1
].mode
, regno
);
5575 substitute (&in
, rld
[r2
].in
, gen_rtx_REG (rld
[r2
].mode
, regno
));
5577 /* If IN is a paradoxical SUBREG, remove it and try to put the
5578 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
5579 strip_paradoxical_subreg (&in
, &out
);
5581 if (GET_CODE (in
) == PLUS
5582 && (REG_P (XEXP (in
, 0))
5583 || GET_CODE (XEXP (in
, 0)) == SUBREG
5584 || MEM_P (XEXP (in
, 0)))
5585 && (REG_P (XEXP (in
, 1))
5586 || GET_CODE (XEXP (in
, 1)) == SUBREG
5587 || CONSTANT_P (XEXP (in
, 1))
5588 || MEM_P (XEXP (in
, 1))))
5590 insn
= emit_insn (gen_rtx_SET (out
, in
));
5591 code
= recog_memoized (insn
);
5596 extract_insn (insn
);
5597 /* We want constrain operands to treat this insn strictly in
5598 its validity determination, i.e., the way it would after
5599 reload has completed. */
5600 result
= constrain_operands (1, get_enabled_alternatives (insn
));
5603 delete_insns_since (last
);
5606 /* Restore the original value at each changed address within R1. */
5607 while (!substitute_stack
.is_empty ())
5609 rtx
*where
= substitute_stack
.pop ();
5610 *where
= rld
[r2
].in
;
5616 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
5619 This function uses the same algorithm as reload_reg_free_p above. */
5622 reloads_conflict (int r1
, int r2
)
5624 enum reload_type r1_type
= rld
[r1
].when_needed
;
5625 enum reload_type r2_type
= rld
[r2
].when_needed
;
5626 int r1_opnum
= rld
[r1
].opnum
;
5627 int r2_opnum
= rld
[r2
].opnum
;
5629 /* RELOAD_OTHER conflicts with everything. */
5630 if (r2_type
== RELOAD_OTHER
)
5633 /* Otherwise, check conflicts differently for each type. */
5637 case RELOAD_FOR_INPUT
:
5638 return (r2_type
== RELOAD_FOR_INSN
5639 || r2_type
== RELOAD_FOR_OPERAND_ADDRESS
5640 || r2_type
== RELOAD_FOR_OPADDR_ADDR
5641 || r2_type
== RELOAD_FOR_INPUT
5642 || ((r2_type
== RELOAD_FOR_INPUT_ADDRESS
5643 || r2_type
== RELOAD_FOR_INPADDR_ADDRESS
)
5644 && r2_opnum
> r1_opnum
));
5646 case RELOAD_FOR_INPUT_ADDRESS
:
5647 return ((r2_type
== RELOAD_FOR_INPUT_ADDRESS
&& r1_opnum
== r2_opnum
)
5648 || (r2_type
== RELOAD_FOR_INPUT
&& r2_opnum
< r1_opnum
));
5650 case RELOAD_FOR_INPADDR_ADDRESS
:
5651 return ((r2_type
== RELOAD_FOR_INPADDR_ADDRESS
&& r1_opnum
== r2_opnum
)
5652 || (r2_type
== RELOAD_FOR_INPUT
&& r2_opnum
< r1_opnum
));
5654 case RELOAD_FOR_OUTPUT_ADDRESS
:
5655 return ((r2_type
== RELOAD_FOR_OUTPUT_ADDRESS
&& r2_opnum
== r1_opnum
)
5656 || (r2_type
== RELOAD_FOR_OUTPUT
&& r2_opnum
<= r1_opnum
));
5658 case RELOAD_FOR_OUTADDR_ADDRESS
:
5659 return ((r2_type
== RELOAD_FOR_OUTADDR_ADDRESS
&& r2_opnum
== r1_opnum
)
5660 || (r2_type
== RELOAD_FOR_OUTPUT
&& r2_opnum
<= r1_opnum
));
5662 case RELOAD_FOR_OPERAND_ADDRESS
:
5663 return (r2_type
== RELOAD_FOR_INPUT
|| r2_type
== RELOAD_FOR_INSN
5664 || (r2_type
== RELOAD_FOR_OPERAND_ADDRESS
5665 && (!reloads_unique_chain_p (r1
, r2
)
5666 || !gen_reload_chain_without_interm_reg_p (r1
, r2
))));
5668 case RELOAD_FOR_OPADDR_ADDR
:
5669 return (r2_type
== RELOAD_FOR_INPUT
5670 || r2_type
== RELOAD_FOR_OPADDR_ADDR
);
5672 case RELOAD_FOR_OUTPUT
:
5673 return (r2_type
== RELOAD_FOR_INSN
|| r2_type
== RELOAD_FOR_OUTPUT
5674 || ((r2_type
== RELOAD_FOR_OUTPUT_ADDRESS
5675 || r2_type
== RELOAD_FOR_OUTADDR_ADDRESS
)
5676 && r2_opnum
>= r1_opnum
));
5678 case RELOAD_FOR_INSN
:
5679 return (r2_type
== RELOAD_FOR_INPUT
|| r2_type
== RELOAD_FOR_OUTPUT
5680 || r2_type
== RELOAD_FOR_INSN
5681 || r2_type
== RELOAD_FOR_OPERAND_ADDRESS
);
5683 case RELOAD_FOR_OTHER_ADDRESS
:
5684 return r2_type
== RELOAD_FOR_OTHER_ADDRESS
;
5694 /* Indexed by reload number, 1 if incoming value
5695 inherited from previous insns. */
5696 static char reload_inherited
[MAX_RELOADS
];
5698 /* For an inherited reload, this is the insn the reload was inherited from,
5699 if we know it. Otherwise, this is 0. */
5700 static rtx_insn
*reload_inheritance_insn
[MAX_RELOADS
];
5702 /* If nonzero, this is a place to get the value of the reload,
5703 rather than using reload_in. */
5704 static rtx reload_override_in
[MAX_RELOADS
];
5706 /* For each reload, the hard register number of the register used,
5707 or -1 if we did not need a register for this reload. */
5708 static int reload_spill_index
[MAX_RELOADS
];
5710 /* Index X is the value of rld[X].reg_rtx, adjusted for the input mode. */
5711 static rtx reload_reg_rtx_for_input
[MAX_RELOADS
];
5713 /* Index X is the value of rld[X].reg_rtx, adjusted for the output mode. */
5714 static rtx reload_reg_rtx_for_output
[MAX_RELOADS
];
5716 /* Subroutine of free_for_value_p, used to check a single register.
5717 START_REGNO is the starting regno of the full reload register
5718 (possibly comprising multiple hard registers) that we are considering. */
5721 reload_reg_free_for_value_p (int start_regno
, int regno
, int opnum
,
5722 enum reload_type type
, rtx value
, rtx out
,
5723 int reloadnum
, int ignore_address_reloads
)
5726 /* Set if we see an input reload that must not share its reload register
5727 with any new earlyclobber, but might otherwise share the reload
5728 register with an output or input-output reload. */
5729 int check_earlyclobber
= 0;
5733 if (TEST_HARD_REG_BIT (reload_reg_unavailable
, regno
))
5736 if (out
== const0_rtx
)
5742 /* We use some pseudo 'time' value to check if the lifetimes of the
5743 new register use would overlap with the one of a previous reload
5744 that is not read-only or uses a different value.
5745 The 'time' used doesn't have to be linear in any shape or form, just
5747 Some reload types use different 'buckets' for each operand.
5748 So there are MAX_RECOG_OPERANDS different time values for each
5750 We compute TIME1 as the time when the register for the prospective
5751 new reload ceases to be live, and TIME2 for each existing
5752 reload as the time when that the reload register of that reload
5754 Where there is little to be gained by exact lifetime calculations,
5755 we just make conservative assumptions, i.e. a longer lifetime;
5756 this is done in the 'default:' cases. */
5759 case RELOAD_FOR_OTHER_ADDRESS
:
5760 /* RELOAD_FOR_OTHER_ADDRESS conflicts with RELOAD_OTHER reloads. */
5761 time1
= copy
? 0 : 1;
5764 time1
= copy
? 1 : MAX_RECOG_OPERANDS
* 5 + 5;
5766 /* For each input, we may have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
5767 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 ,
5768 respectively, to the time values for these, we get distinct time
5769 values. To get distinct time values for each operand, we have to
5770 multiply opnum by at least three. We round that up to four because
5771 multiply by four is often cheaper. */
5772 case RELOAD_FOR_INPADDR_ADDRESS
:
5773 time1
= opnum
* 4 + 2;
5775 case RELOAD_FOR_INPUT_ADDRESS
:
5776 time1
= opnum
* 4 + 3;
5778 case RELOAD_FOR_INPUT
:
5779 /* All RELOAD_FOR_INPUT reloads remain live till the instruction
5780 executes (inclusive). */
5781 time1
= copy
? opnum
* 4 + 4 : MAX_RECOG_OPERANDS
* 4 + 3;
5783 case RELOAD_FOR_OPADDR_ADDR
:
5785 <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
5786 time1
= MAX_RECOG_OPERANDS
* 4 + 1;
5788 case RELOAD_FOR_OPERAND_ADDRESS
:
5789 /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn
5791 time1
= copy
? MAX_RECOG_OPERANDS
* 4 + 2 : MAX_RECOG_OPERANDS
* 4 + 3;
5793 case RELOAD_FOR_OUTADDR_ADDRESS
:
5794 time1
= MAX_RECOG_OPERANDS
* 4 + 4 + opnum
;
5796 case RELOAD_FOR_OUTPUT_ADDRESS
:
5797 time1
= MAX_RECOG_OPERANDS
* 4 + 5 + opnum
;
5800 time1
= MAX_RECOG_OPERANDS
* 5 + 5;
5803 for (i
= 0; i
< n_reloads
; i
++)
5805 rtx reg
= rld
[i
].reg_rtx
;
5806 if (reg
&& REG_P (reg
)
5807 && (unsigned) regno
- true_regnum (reg
) < REG_NREGS (reg
)
5810 rtx other_input
= rld
[i
].in
;
5812 /* If the other reload loads the same input value, that
5813 will not cause a conflict only if it's loading it into
5814 the same register. */
5815 if (true_regnum (reg
) != start_regno
)
5816 other_input
= NULL_RTX
;
5817 if (! other_input
|| ! rtx_equal_p (other_input
, value
)
5818 || rld
[i
].out
|| out
)
5821 switch (rld
[i
].when_needed
)
5823 case RELOAD_FOR_OTHER_ADDRESS
:
5826 case RELOAD_FOR_INPADDR_ADDRESS
:
5827 /* find_reloads makes sure that a
5828 RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used
5829 by at most one - the first -
5830 RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the
5831 address reload is inherited, the address address reload
5832 goes away, so we can ignore this conflict. */
5833 if (type
== RELOAD_FOR_INPUT_ADDRESS
&& reloadnum
== i
+ 1
5834 && ignore_address_reloads
5835 /* Unless the RELOAD_FOR_INPUT is an auto_inc expression.
5836 Then the address address is still needed to store
5837 back the new address. */
5838 && ! rld
[reloadnum
].out
)
5840 /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its
5841 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS
5843 if (type
== RELOAD_FOR_INPUT
&& opnum
== rld
[i
].opnum
5844 && ignore_address_reloads
5845 /* Unless we are reloading an auto_inc expression. */
5846 && ! rld
[reloadnum
].out
)
5848 time2
= rld
[i
].opnum
* 4 + 2;
5850 case RELOAD_FOR_INPUT_ADDRESS
:
5851 if (type
== RELOAD_FOR_INPUT
&& opnum
== rld
[i
].opnum
5852 && ignore_address_reloads
5853 && ! rld
[reloadnum
].out
)
5855 time2
= rld
[i
].opnum
* 4 + 3;
5857 case RELOAD_FOR_INPUT
:
5858 time2
= rld
[i
].opnum
* 4 + 4;
5859 check_earlyclobber
= 1;
5861 /* rld[i].opnum * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4
5862 == MAX_RECOG_OPERAND * 4 */
5863 case RELOAD_FOR_OPADDR_ADDR
:
5864 if (type
== RELOAD_FOR_OPERAND_ADDRESS
&& reloadnum
== i
+ 1
5865 && ignore_address_reloads
5866 && ! rld
[reloadnum
].out
)
5868 time2
= MAX_RECOG_OPERANDS
* 4 + 1;
5870 case RELOAD_FOR_OPERAND_ADDRESS
:
5871 time2
= MAX_RECOG_OPERANDS
* 4 + 2;
5872 check_earlyclobber
= 1;
5874 case RELOAD_FOR_INSN
:
5875 time2
= MAX_RECOG_OPERANDS
* 4 + 3;
5877 case RELOAD_FOR_OUTPUT
:
5878 /* All RELOAD_FOR_OUTPUT reloads become live just after the
5879 instruction is executed. */
5880 time2
= MAX_RECOG_OPERANDS
* 4 + 4;
5882 /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with
5883 the RELOAD_FOR_OUTPUT reloads, so assign it the same time
5885 case RELOAD_FOR_OUTADDR_ADDRESS
:
5886 if (type
== RELOAD_FOR_OUTPUT_ADDRESS
&& reloadnum
== i
+ 1
5887 && ignore_address_reloads
5888 && ! rld
[reloadnum
].out
)
5890 time2
= MAX_RECOG_OPERANDS
* 4 + 4 + rld
[i
].opnum
;
5892 case RELOAD_FOR_OUTPUT_ADDRESS
:
5893 time2
= MAX_RECOG_OPERANDS
* 4 + 5 + rld
[i
].opnum
;
5896 /* If there is no conflict in the input part, handle this
5897 like an output reload. */
5898 if (! rld
[i
].in
|| rtx_equal_p (other_input
, value
))
5900 time2
= MAX_RECOG_OPERANDS
* 4 + 4;
5901 /* Earlyclobbered outputs must conflict with inputs. */
5902 if (earlyclobber_operand_p (rld
[i
].out
))
5903 time2
= MAX_RECOG_OPERANDS
* 4 + 3;
5908 /* RELOAD_OTHER might be live beyond instruction execution,
5909 but this is not obvious when we set time2 = 1. So check
5910 here if there might be a problem with the new reload
5911 clobbering the register used by the RELOAD_OTHER. */
5919 && (! rld
[i
].in
|| rld
[i
].out
5920 || ! rtx_equal_p (other_input
, value
)))
5921 || (out
&& rld
[reloadnum
].out_reg
5922 && time2
>= MAX_RECOG_OPERANDS
* 4 + 3))
5928 /* Earlyclobbered outputs must conflict with inputs. */
5929 if (check_earlyclobber
&& out
&& earlyclobber_operand_p (out
))
5935 /* Return 1 if the value in reload reg REGNO, as used by a reload
5936 needed for the part of the insn specified by OPNUM and TYPE,
5937 may be used to load VALUE into it.
5939 MODE is the mode in which the register is used, this is needed to
5940 determine how many hard regs to test.
5942 Other read-only reloads with the same value do not conflict
5943 unless OUT is nonzero and these other reloads have to live while
5944 output reloads live.
5945 If OUT is CONST0_RTX, this is a special case: it means that the
5946 test should not be for using register REGNO as reload register, but
5947 for copying from register REGNO into the reload register.
5949 RELOADNUM is the number of the reload we want to load this value for;
5950 a reload does not conflict with itself.
5952 When IGNORE_ADDRESS_RELOADS is set, we cannot have conflicts with
5953 reloads that load an address for the very reload we are considering.
5955 The caller has to make sure that there is no conflict with the return
5959 free_for_value_p (int regno
, machine_mode mode
, int opnum
,
5960 enum reload_type type
, rtx value
, rtx out
, int reloadnum
,
5961 int ignore_address_reloads
)
5963 int nregs
= hard_regno_nregs (regno
, mode
);
5965 if (! reload_reg_free_for_value_p (regno
, regno
+ nregs
, opnum
, type
,
5966 value
, out
, reloadnum
,
5967 ignore_address_reloads
))
5972 /* Return nonzero if the rtx X is invariant over the current function. */
5973 /* ??? Actually, the places where we use this expect exactly what is
5974 tested here, and not everything that is function invariant. In
5975 particular, the frame pointer and arg pointer are special cased;
5976 pic_offset_table_rtx is not, and we must not spill these things to
5980 function_invariant_p (const_rtx x
)
5984 if (x
== frame_pointer_rtx
|| x
== arg_pointer_rtx
)
5986 if (GET_CODE (x
) == PLUS
5987 && (XEXP (x
, 0) == frame_pointer_rtx
|| XEXP (x
, 0) == arg_pointer_rtx
)
5988 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
5993 /* Determine whether the reload reg X overlaps any rtx'es used for
5994 overriding inheritance. Return nonzero if so. */
5997 conflicts_with_override (rtx x
)
6000 for (i
= 0; i
< n_reloads
; i
++)
6001 if (reload_override_in
[i
]
6002 && reg_overlap_mentioned_p (x
, reload_override_in
[i
]))
6007 /* Give an error message saying we failed to find a reload for INSN,
6008 and clear out reload R. */
6010 failed_reload (rtx_insn
*insn
, int r
)
6012 if (asm_noperands (PATTERN (insn
)) < 0)
6013 /* It's the compiler's fault. */
6014 fatal_insn ("could not find a spill register", insn
);
6016 /* It's the user's fault; the operand's mode and constraint
6017 don't match. Disable this reload so we don't crash in final. */
6018 error_for_asm (insn
,
6019 "%<asm%> operand constraint incompatible with operand size");
6023 rld
[r
].optional
= 1;
6024 rld
[r
].secondary_p
= 1;
6027 /* I is the index in SPILL_REG_RTX of the reload register we are to allocate
6028 for reload R. If it's valid, get an rtx for it. Return nonzero if
6031 set_reload_reg (int i
, int r
)
6034 rtx reg
= spill_reg_rtx
[i
];
6036 if (reg
== 0 || GET_MODE (reg
) != rld
[r
].mode
)
6037 spill_reg_rtx
[i
] = reg
6038 = gen_rtx_REG (rld
[r
].mode
, spill_regs
[i
]);
6040 regno
= true_regnum (reg
);
6042 /* Detect when the reload reg can't hold the reload mode.
6043 This used to be one `if', but Sequent compiler can't handle that. */
6044 if (targetm
.hard_regno_mode_ok (regno
, rld
[r
].mode
))
6046 machine_mode test_mode
= VOIDmode
;
6048 test_mode
= GET_MODE (rld
[r
].in
);
6049 /* If rld[r].in has VOIDmode, it means we will load it
6050 in whatever mode the reload reg has: to wit, rld[r].mode.
6051 We have already tested that for validity. */
6052 /* Aside from that, we need to test that the expressions
6053 to reload from or into have modes which are valid for this
6054 reload register. Otherwise the reload insns would be invalid. */
6055 if (! (rld
[r
].in
!= 0 && test_mode
!= VOIDmode
6056 && !targetm
.hard_regno_mode_ok (regno
, test_mode
)))
6057 if (! (rld
[r
].out
!= 0
6058 && !targetm
.hard_regno_mode_ok (regno
, GET_MODE (rld
[r
].out
))))
6060 /* The reg is OK. */
6063 /* Mark as in use for this insn the reload regs we use
6065 mark_reload_reg_in_use (spill_regs
[i
], rld
[r
].opnum
,
6066 rld
[r
].when_needed
, rld
[r
].mode
);
6068 rld
[r
].reg_rtx
= reg
;
6069 reload_spill_index
[r
] = spill_regs
[i
];
6076 /* Find a spill register to use as a reload register for reload R.
6077 LAST_RELOAD is nonzero if this is the last reload for the insn being
6080 Set rld[R].reg_rtx to the register allocated.
6082 We return 1 if successful, or 0 if we couldn't find a spill reg and
6083 we didn't change anything. */
6086 allocate_reload_reg (class insn_chain
*chain ATTRIBUTE_UNUSED
, int r
,
6091 /* If we put this reload ahead, thinking it is a group,
6092 then insist on finding a group. Otherwise we can grab a
6093 reg that some other reload needs.
6094 (That can happen when we have a 68000 DATA_OR_FP_REG
6095 which is a group of data regs or one fp reg.)
6096 We need not be so restrictive if there are no more reloads
6099 ??? Really it would be nicer to have smarter handling
6100 for that kind of reg class, where a problem like this is normal.
6101 Perhaps those classes should be avoided for reloading
6102 by use of more alternatives. */
6104 int force_group
= rld
[r
].nregs
> 1 && ! last_reload
;
6106 /* If we want a single register and haven't yet found one,
6107 take any reg in the right class and not in use.
6108 If we want a consecutive group, here is where we look for it.
6110 We use three passes so we can first look for reload regs to
6111 reuse, which are already in use for other reloads in this insn,
6112 and only then use additional registers which are not "bad", then
6113 finally any register.
6115 I think that maximizing reuse is needed to make sure we don't
6116 run out of reload regs. Suppose we have three reloads, and
6117 reloads A and B can share regs. These need two regs.
6118 Suppose A and B are given different regs.
6119 That leaves none for C. */
6120 for (pass
= 0; pass
< 3; pass
++)
6122 /* I is the index in spill_regs.
6123 We advance it round-robin between insns to use all spill regs
6124 equally, so that inherited reloads have a chance
6125 of leapfrogging each other. */
6129 for (count
= 0; count
< n_spills
; count
++)
6131 int rclass
= (int) rld
[r
].rclass
;
6137 regnum
= spill_regs
[i
];
6139 if ((reload_reg_free_p (regnum
, rld
[r
].opnum
,
6142 /* We check reload_reg_used to make sure we
6143 don't clobber the return register. */
6144 && ! TEST_HARD_REG_BIT (reload_reg_used
, regnum
)
6145 && free_for_value_p (regnum
, rld
[r
].mode
, rld
[r
].opnum
,
6146 rld
[r
].when_needed
, rld
[r
].in
,
6148 && TEST_HARD_REG_BIT (reg_class_contents
[rclass
], regnum
)
6149 && targetm
.hard_regno_mode_ok (regnum
, rld
[r
].mode
)
6150 /* Look first for regs to share, then for unshared. But
6151 don't share regs used for inherited reloads; they are
6152 the ones we want to preserve. */
6154 || (TEST_HARD_REG_BIT (reload_reg_used_at_all
,
6156 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit
,
6159 int nr
= hard_regno_nregs (regnum
, rld
[r
].mode
);
6161 /* During the second pass we want to avoid reload registers
6162 which are "bad" for this reload. */
6164 && ira_bad_reload_regno (regnum
, rld
[r
].in
, rld
[r
].out
))
6167 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
6168 (on 68000) got us two FP regs. If NR is 1,
6169 we would reject both of them. */
6172 /* If we need only one reg, we have already won. */
6175 /* But reject a single reg if we demand a group. */
6180 /* Otherwise check that as many consecutive regs as we need
6181 are available here. */
6184 int regno
= regnum
+ nr
- 1;
6185 if (!(TEST_HARD_REG_BIT (reg_class_contents
[rclass
], regno
)
6186 && spill_reg_order
[regno
] >= 0
6187 && reload_reg_free_p (regno
, rld
[r
].opnum
,
6188 rld
[r
].when_needed
)))
6197 /* If we found something on the current pass, omit later passes. */
6198 if (count
< n_spills
)
6202 /* We should have found a spill register by now. */
6203 if (count
>= n_spills
)
6206 /* I is the index in SPILL_REG_RTX of the reload register we are to
6207 allocate. Get an rtx for it and find its register number. */
6209 return set_reload_reg (i
, r
);
6212 /* Initialize all the tables needed to allocate reload registers.
6213 CHAIN is the insn currently being processed; SAVE_RELOAD_REG_RTX
6214 is the array we use to restore the reg_rtx field for every reload. */
6217 choose_reload_regs_init (class insn_chain
*chain
, rtx
*save_reload_reg_rtx
)
6221 for (i
= 0; i
< n_reloads
; i
++)
6222 rld
[i
].reg_rtx
= save_reload_reg_rtx
[i
];
6224 memset (reload_inherited
, 0, MAX_RELOADS
);
6225 memset (reload_inheritance_insn
, 0, MAX_RELOADS
* sizeof (rtx
));
6226 memset (reload_override_in
, 0, MAX_RELOADS
* sizeof (rtx
));
6228 CLEAR_HARD_REG_SET (reload_reg_used
);
6229 CLEAR_HARD_REG_SET (reload_reg_used_at_all
);
6230 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr
);
6231 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload
);
6232 CLEAR_HARD_REG_SET (reload_reg_used_in_insn
);
6233 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr
);
6235 CLEAR_HARD_REG_SET (reg_used_in_insn
);
6238 REG_SET_TO_HARD_REG_SET (tmp
, &chain
->live_throughout
);
6239 reg_used_in_insn
|= tmp
;
6240 REG_SET_TO_HARD_REG_SET (tmp
, &chain
->dead_or_set
);
6241 reg_used_in_insn
|= tmp
;
6242 compute_use_by_pseudos (®_used_in_insn
, &chain
->live_throughout
);
6243 compute_use_by_pseudos (®_used_in_insn
, &chain
->dead_or_set
);
6246 for (i
= 0; i
< reload_n_operands
; i
++)
6248 CLEAR_HARD_REG_SET (reload_reg_used_in_output
[i
]);
6249 CLEAR_HARD_REG_SET (reload_reg_used_in_input
[i
]);
6250 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr
[i
]);
6251 CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr
[i
]);
6252 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr
[i
]);
6253 CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr
[i
]);
6256 reload_reg_unavailable
= ~chain
->used_spill_regs
;
6258 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit
);
6260 for (i
= 0; i
< n_reloads
; i
++)
6261 /* If we have already decided to use a certain register,
6262 don't use it in another way. */
6264 mark_reload_reg_in_use (REGNO (rld
[i
].reg_rtx
), rld
[i
].opnum
,
6265 rld
[i
].when_needed
, rld
[i
].mode
);
6268 /* If X is not a subreg, return it unmodified. If it is a subreg,
6269 look up whether we made a replacement for the SUBREG_REG. Return
6270 either the replacement or the SUBREG_REG. */
6273 replaced_subreg (rtx x
)
6275 if (GET_CODE (x
) == SUBREG
)
6276 return find_replacement (&SUBREG_REG (x
));
6280 /* Compute the offset to pass to subreg_regno_offset, for a pseudo of
6281 mode OUTERMODE that is available in a hard reg of mode INNERMODE.
6282 SUBREG is non-NULL if the pseudo is a subreg whose reg is a pseudo,
6283 otherwise it is NULL. */
6286 compute_reload_subreg_offset (machine_mode outermode
,
6288 machine_mode innermode
)
6290 poly_int64 outer_offset
;
6291 machine_mode middlemode
;
6294 return subreg_lowpart_offset (outermode
, innermode
);
6296 outer_offset
= SUBREG_BYTE (subreg
);
6297 middlemode
= GET_MODE (SUBREG_REG (subreg
));
6299 /* If SUBREG is paradoxical then return the normal lowpart offset
6300 for OUTERMODE and INNERMODE. Our caller has already checked
6301 that OUTERMODE fits in INNERMODE. */
6302 if (paradoxical_subreg_p (outermode
, middlemode
))
6303 return subreg_lowpart_offset (outermode
, innermode
);
6305 /* SUBREG is normal, but may not be lowpart; return OUTER_OFFSET
6306 plus the normal lowpart offset for MIDDLEMODE and INNERMODE. */
6307 return outer_offset
+ subreg_lowpart_offset (middlemode
, innermode
);
6310 /* Assign hard reg targets for the pseudo-registers we must reload
6311 into hard regs for this insn.
6312 Also output the instructions to copy them in and out of the hard regs.
6314 For machines with register classes, we are responsible for
6315 finding a reload reg in the proper class. */
6318 choose_reload_regs (class insn_chain
*chain
)
6320 rtx_insn
*insn
= chain
->insn
;
6322 unsigned int max_group_size
= 1;
6323 enum reg_class group_class
= NO_REGS
;
6324 int pass
, win
, inheritance
;
6326 rtx save_reload_reg_rtx
[MAX_RELOADS
];
6328 /* In order to be certain of getting the registers we need,
6329 we must sort the reloads into order of increasing register class.
6330 Then our grabbing of reload registers will parallel the process
6331 that provided the reload registers.
6333 Also note whether any of the reloads wants a consecutive group of regs.
6334 If so, record the maximum size of the group desired and what
6335 register class contains all the groups needed by this insn. */
6337 for (j
= 0; j
< n_reloads
; j
++)
6339 reload_order
[j
] = j
;
6340 if (rld
[j
].reg_rtx
!= NULL_RTX
)
6342 gcc_assert (REG_P (rld
[j
].reg_rtx
)
6343 && HARD_REGISTER_P (rld
[j
].reg_rtx
));
6344 reload_spill_index
[j
] = REGNO (rld
[j
].reg_rtx
);
6347 reload_spill_index
[j
] = -1;
6349 if (rld
[j
].nregs
> 1)
6351 max_group_size
= MAX (rld
[j
].nregs
, max_group_size
);
6353 = reg_class_superunion
[(int) rld
[j
].rclass
][(int) group_class
];
6356 save_reload_reg_rtx
[j
] = rld
[j
].reg_rtx
;
6360 qsort (reload_order
, n_reloads
, sizeof (short), reload_reg_class_lower
);
6362 /* If -O, try first with inheritance, then turning it off.
6363 If not -O, don't do inheritance.
6364 Using inheritance when not optimizing leads to paradoxes
6365 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
6366 because one side of the comparison might be inherited. */
6368 for (inheritance
= optimize
> 0; inheritance
>= 0; inheritance
--)
6370 choose_reload_regs_init (chain
, save_reload_reg_rtx
);
6372 /* Process the reloads in order of preference just found.
6373 Beyond this point, subregs can be found in reload_reg_rtx.
6375 This used to look for an existing reloaded home for all of the
6376 reloads, and only then perform any new reloads. But that could lose
6377 if the reloads were done out of reg-class order because a later
6378 reload with a looser constraint might have an old home in a register
6379 needed by an earlier reload with a tighter constraint.
6381 To solve this, we make two passes over the reloads, in the order
6382 described above. In the first pass we try to inherit a reload
6383 from a previous insn. If there is a later reload that needs a
6384 class that is a proper subset of the class being processed, we must
6385 also allocate a spill register during the first pass.
6387 Then make a second pass over the reloads to allocate any reloads
6388 that haven't been given registers yet. */
6390 for (j
= 0; j
< n_reloads
; j
++)
6392 int r
= reload_order
[j
];
6393 rtx search_equiv
= NULL_RTX
;
6395 /* Ignore reloads that got marked inoperative. */
6396 if (rld
[r
].out
== 0 && rld
[r
].in
== 0
6397 && ! rld
[r
].secondary_p
)
6400 /* If find_reloads chose to use reload_in or reload_out as a reload
6401 register, we don't need to chose one. Otherwise, try even if it
6402 found one since we might save an insn if we find the value lying
6404 Try also when reload_in is a pseudo without a hard reg. */
6405 if (rld
[r
].in
!= 0 && rld
[r
].reg_rtx
!= 0
6406 && (rtx_equal_p (rld
[r
].in
, rld
[r
].reg_rtx
)
6407 || (rtx_equal_p (rld
[r
].out
, rld
[r
].reg_rtx
)
6408 && !MEM_P (rld
[r
].in
)
6409 && true_regnum (rld
[r
].in
) < FIRST_PSEUDO_REGISTER
)))
6412 #if 0 /* No longer needed for correct operation.
6413 It might give better code, or might not; worth an experiment? */
6414 /* If this is an optional reload, we can't inherit from earlier insns
6415 until we are sure that any non-optional reloads have been allocated.
6416 The following code takes advantage of the fact that optional reloads
6417 are at the end of reload_order. */
6418 if (rld
[r
].optional
!= 0)
6419 for (i
= 0; i
< j
; i
++)
6420 if ((rld
[reload_order
[i
]].out
!= 0
6421 || rld
[reload_order
[i
]].in
!= 0
6422 || rld
[reload_order
[i
]].secondary_p
)
6423 && ! rld
[reload_order
[i
]].optional
6424 && rld
[reload_order
[i
]].reg_rtx
== 0)
6425 allocate_reload_reg (chain
, reload_order
[i
], 0);
6428 /* First see if this pseudo is already available as reloaded
6429 for a previous insn. We cannot try to inherit for reloads
6430 that are smaller than the maximum number of registers needed
6431 for groups unless the register we would allocate cannot be used
6434 We could check here to see if this is a secondary reload for
6435 an object that is already in a register of the desired class.
6436 This would avoid the need for the secondary reload register.
6437 But this is complex because we can't easily determine what
6438 objects might want to be loaded via this reload. So let a
6439 register be allocated here. In `emit_reload_insns' we suppress
6440 one of the loads in the case described above. */
6444 poly_int64 byte
= 0;
6446 machine_mode mode
= VOIDmode
;
6447 rtx subreg
= NULL_RTX
;
6451 else if (REG_P (rld
[r
].in
))
6453 regno
= REGNO (rld
[r
].in
);
6454 mode
= GET_MODE (rld
[r
].in
);
6456 else if (REG_P (rld
[r
].in_reg
))
6458 regno
= REGNO (rld
[r
].in_reg
);
6459 mode
= GET_MODE (rld
[r
].in_reg
);
6461 else if (GET_CODE (rld
[r
].in_reg
) == SUBREG
6462 && REG_P (SUBREG_REG (rld
[r
].in_reg
)))
6464 regno
= REGNO (SUBREG_REG (rld
[r
].in_reg
));
6465 if (regno
< FIRST_PSEUDO_REGISTER
)
6466 regno
= subreg_regno (rld
[r
].in_reg
);
6469 subreg
= rld
[r
].in_reg
;
6470 byte
= SUBREG_BYTE (subreg
);
6472 mode
= GET_MODE (rld
[r
].in_reg
);
6475 else if (GET_RTX_CLASS (GET_CODE (rld
[r
].in_reg
)) == RTX_AUTOINC
6476 && REG_P (XEXP (rld
[r
].in_reg
, 0)))
6478 regno
= REGNO (XEXP (rld
[r
].in_reg
, 0));
6479 mode
= GET_MODE (XEXP (rld
[r
].in_reg
, 0));
6480 rld
[r
].out
= rld
[r
].in
;
6484 /* This won't work, since REGNO can be a pseudo reg number.
6485 Also, it takes much more hair to keep track of all the things
6486 that can invalidate an inherited reload of part of a pseudoreg. */
6487 else if (GET_CODE (rld
[r
].in
) == SUBREG
6488 && REG_P (SUBREG_REG (rld
[r
].in
)))
6489 regno
= subreg_regno (rld
[r
].in
);
6493 && reg_last_reload_reg
[regno
] != 0
6495 (GET_MODE_SIZE (GET_MODE (reg_last_reload_reg
[regno
])),
6496 GET_MODE_SIZE (mode
) + byte
))
6497 /* Verify that the register it's in can be used in
6499 && (REG_CAN_CHANGE_MODE_P
6500 (REGNO (reg_last_reload_reg
[regno
]),
6501 GET_MODE (reg_last_reload_reg
[regno
]),
6504 enum reg_class rclass
= rld
[r
].rclass
, last_class
;
6505 rtx last_reg
= reg_last_reload_reg
[regno
];
6507 i
= REGNO (last_reg
);
6508 byte
= compute_reload_subreg_offset (mode
,
6510 GET_MODE (last_reg
));
6511 i
+= subreg_regno_offset (i
, GET_MODE (last_reg
), byte
, mode
);
6512 last_class
= REGNO_REG_CLASS (i
);
6514 if (reg_reloaded_contents
[i
] == regno
6515 && TEST_HARD_REG_BIT (reg_reloaded_valid
, i
)
6516 && targetm
.hard_regno_mode_ok (i
, rld
[r
].mode
)
6517 && (TEST_HARD_REG_BIT (reg_class_contents
[(int) rclass
], i
)
6518 /* Even if we can't use this register as a reload
6519 register, we might use it for reload_override_in,
6520 if copying it to the desired class is cheap
6522 || ((register_move_cost (mode
, last_class
, rclass
)
6523 < memory_move_cost (mode
, rclass
, true))
6524 && (secondary_reload_class (1, rclass
, mode
,
6527 && !(targetm
.secondary_memory_needed
6528 (mode
, last_class
, rclass
))))
6529 && (rld
[r
].nregs
== max_group_size
6530 || ! TEST_HARD_REG_BIT (reg_class_contents
[(int) group_class
],
6532 && free_for_value_p (i
, rld
[r
].mode
, rld
[r
].opnum
,
6533 rld
[r
].when_needed
, rld
[r
].in
,
6536 /* If a group is needed, verify that all the subsequent
6537 registers still have their values intact. */
6538 int nr
= hard_regno_nregs (i
, rld
[r
].mode
);
6541 for (k
= 1; k
< nr
; k
++)
6542 if (reg_reloaded_contents
[i
+ k
] != regno
6543 || ! TEST_HARD_REG_BIT (reg_reloaded_valid
, i
+ k
))
6551 last_reg
= (GET_MODE (last_reg
) == mode
6552 ? last_reg
: gen_rtx_REG (mode
, i
));
6555 for (k
= 0; k
< nr
; k
++)
6556 bad_for_class
|= ! TEST_HARD_REG_BIT (reg_class_contents
[(int) rld
[r
].rclass
],
6559 /* We found a register that contains the
6560 value we need. If this register is the
6561 same as an `earlyclobber' operand of the
6562 current insn, just mark it as a place to
6563 reload from since we can't use it as the
6564 reload register itself. */
6566 for (i1
= 0; i1
< n_earlyclobbers
; i1
++)
6567 if (reg_overlap_mentioned_for_reload_p
6568 (reg_last_reload_reg
[regno
],
6569 reload_earlyclobbers
[i1
]))
6572 if (i1
!= n_earlyclobbers
6573 || ! (free_for_value_p (i
, rld
[r
].mode
,
6575 rld
[r
].when_needed
, rld
[r
].in
,
6577 /* Don't use it if we'd clobber a pseudo reg. */
6578 || (TEST_HARD_REG_BIT (reg_used_in_insn
, i
)
6580 && ! TEST_HARD_REG_BIT (reg_reloaded_dead
, i
))
6581 /* Don't clobber the frame pointer. */
6582 || (i
== HARD_FRAME_POINTER_REGNUM
6583 && frame_pointer_needed
6585 /* Don't really use the inherited spill reg
6586 if we need it wider than we've got it. */
6587 || paradoxical_subreg_p (rld
[r
].mode
, mode
)
6590 /* If find_reloads chose reload_out as reload
6591 register, stay with it - that leaves the
6592 inherited register for subsequent reloads. */
6593 || (rld
[r
].out
&& rld
[r
].reg_rtx
6594 && rtx_equal_p (rld
[r
].out
, rld
[r
].reg_rtx
)))
6596 if (! rld
[r
].optional
)
6598 reload_override_in
[r
] = last_reg
;
6599 reload_inheritance_insn
[r
]
6600 = reg_reloaded_insn
[i
];
6606 /* We can use this as a reload reg. */
6607 /* Mark the register as in use for this part of
6609 mark_reload_reg_in_use (i
,
6613 rld
[r
].reg_rtx
= last_reg
;
6614 reload_inherited
[r
] = 1;
6615 reload_inheritance_insn
[r
]
6616 = reg_reloaded_insn
[i
];
6617 reload_spill_index
[r
] = i
;
6618 for (k
= 0; k
< nr
; k
++)
6619 SET_HARD_REG_BIT (reload_reg_used_for_inherit
,
6627 /* Here's another way to see if the value is already lying around. */
6630 && ! reload_inherited
[r
]
6632 && (CONSTANT_P (rld
[r
].in
)
6633 || GET_CODE (rld
[r
].in
) == PLUS
6634 || REG_P (rld
[r
].in
)
6635 || MEM_P (rld
[r
].in
))
6636 && (rld
[r
].nregs
== max_group_size
6637 || ! reg_classes_intersect_p (rld
[r
].rclass
, group_class
)))
6638 search_equiv
= rld
[r
].in
;
6643 = find_equiv_reg (search_equiv
, insn
, rld
[r
].rclass
,
6644 -1, NULL
, 0, rld
[r
].mode
);
6650 regno
= REGNO (equiv
);
6653 /* This must be a SUBREG of a hard register.
6654 Make a new REG since this might be used in an
6655 address and not all machines support SUBREGs
6657 gcc_assert (GET_CODE (equiv
) == SUBREG
);
6658 regno
= subreg_regno (equiv
);
6659 equiv
= gen_rtx_REG (rld
[r
].mode
, regno
);
6660 /* If we choose EQUIV as the reload register, but the
6661 loop below decides to cancel the inheritance, we'll
6662 end up reloading EQUIV in rld[r].mode, not the mode
6663 it had originally. That isn't safe when EQUIV isn't
6664 available as a spill register since its value might
6665 still be live at this point. */
6666 for (i
= regno
; i
< regno
+ (int) rld
[r
].nregs
; i
++)
6667 if (TEST_HARD_REG_BIT (reload_reg_unavailable
, i
))
6672 /* If we found a spill reg, reject it unless it is free
6673 and of the desired class. */
6677 int bad_for_class
= 0;
6678 int max_regno
= regno
+ rld
[r
].nregs
;
6680 for (i
= regno
; i
< max_regno
; i
++)
6682 regs_used
|= TEST_HARD_REG_BIT (reload_reg_used_at_all
,
6684 bad_for_class
|= ! TEST_HARD_REG_BIT (reg_class_contents
[(int) rld
[r
].rclass
],
6689 && ! free_for_value_p (regno
, rld
[r
].mode
,
6690 rld
[r
].opnum
, rld
[r
].when_needed
,
6691 rld
[r
].in
, rld
[r
].out
, r
, 1))
6697 && !targetm
.hard_regno_mode_ok (regno
, rld
[r
].mode
))
6700 /* We found a register that contains the value we need.
6701 If this register is the same as an `earlyclobber' operand
6702 of the current insn, just mark it as a place to reload from
6703 since we can't use it as the reload register itself. */
6706 for (i
= 0; i
< n_earlyclobbers
; i
++)
6707 if (reg_overlap_mentioned_for_reload_p (equiv
,
6708 reload_earlyclobbers
[i
]))
6710 if (! rld
[r
].optional
)
6711 reload_override_in
[r
] = equiv
;
6716 /* If the equiv register we have found is explicitly clobbered
6717 in the current insn, it depends on the reload type if we
6718 can use it, use it for reload_override_in, or not at all.
6719 In particular, we then can't use EQUIV for a
6720 RELOAD_FOR_OUTPUT_ADDRESS reload. */
6724 if (regno_clobbered_p (regno
, insn
, rld
[r
].mode
, 2))
6725 switch (rld
[r
].when_needed
)
6727 case RELOAD_FOR_OTHER_ADDRESS
:
6728 case RELOAD_FOR_INPADDR_ADDRESS
:
6729 case RELOAD_FOR_INPUT_ADDRESS
:
6730 case RELOAD_FOR_OPADDR_ADDR
:
6733 case RELOAD_FOR_INPUT
:
6734 case RELOAD_FOR_OPERAND_ADDRESS
:
6735 if (! rld
[r
].optional
)
6736 reload_override_in
[r
] = equiv
;
6742 else if (regno_clobbered_p (regno
, insn
, rld
[r
].mode
, 1))
6743 switch (rld
[r
].when_needed
)
6745 case RELOAD_FOR_OTHER_ADDRESS
:
6746 case RELOAD_FOR_INPADDR_ADDRESS
:
6747 case RELOAD_FOR_INPUT_ADDRESS
:
6748 case RELOAD_FOR_OPADDR_ADDR
:
6749 case RELOAD_FOR_OPERAND_ADDRESS
:
6750 case RELOAD_FOR_INPUT
:
6753 if (! rld
[r
].optional
)
6754 reload_override_in
[r
] = equiv
;
6762 /* If we found an equivalent reg, say no code need be generated
6763 to load it, and use it as our reload reg. */
6765 && (regno
!= HARD_FRAME_POINTER_REGNUM
6766 || !frame_pointer_needed
))
6768 int nr
= hard_regno_nregs (regno
, rld
[r
].mode
);
6770 rld
[r
].reg_rtx
= equiv
;
6771 reload_spill_index
[r
] = regno
;
6772 reload_inherited
[r
] = 1;
6774 /* If reg_reloaded_valid is not set for this register,
6775 there might be a stale spill_reg_store lying around.
6776 We must clear it, since otherwise emit_reload_insns
6777 might delete the store. */
6778 if (! TEST_HARD_REG_BIT (reg_reloaded_valid
, regno
))
6779 spill_reg_store
[regno
] = NULL
;
6780 /* If any of the hard registers in EQUIV are spill
6781 registers, mark them as in use for this insn. */
6782 for (k
= 0; k
< nr
; k
++)
6784 i
= spill_reg_order
[regno
+ k
];
6787 mark_reload_reg_in_use (regno
, rld
[r
].opnum
,
6790 SET_HARD_REG_BIT (reload_reg_used_for_inherit
,
6797 /* If we found a register to use already, or if this is an optional
6798 reload, we are done. */
6799 if (rld
[r
].reg_rtx
!= 0 || rld
[r
].optional
!= 0)
6803 /* No longer needed for correct operation. Might or might
6804 not give better code on the average. Want to experiment? */
6806 /* See if there is a later reload that has a class different from our
6807 class that intersects our class or that requires less register
6808 than our reload. If so, we must allocate a register to this
6809 reload now, since that reload might inherit a previous reload
6810 and take the only available register in our class. Don't do this
6811 for optional reloads since they will force all previous reloads
6812 to be allocated. Also don't do this for reloads that have been
6815 for (i
= j
+ 1; i
< n_reloads
; i
++)
6817 int s
= reload_order
[i
];
6819 if ((rld
[s
].in
== 0 && rld
[s
].out
== 0
6820 && ! rld
[s
].secondary_p
)
6824 if ((rld
[s
].rclass
!= rld
[r
].rclass
6825 && reg_classes_intersect_p (rld
[r
].rclass
,
6827 || rld
[s
].nregs
< rld
[r
].nregs
)
6834 allocate_reload_reg (chain
, r
, j
== n_reloads
- 1);
6838 /* Now allocate reload registers for anything non-optional that
6839 didn't get one yet. */
6840 for (j
= 0; j
< n_reloads
; j
++)
6842 int r
= reload_order
[j
];
6844 /* Ignore reloads that got marked inoperative. */
6845 if (rld
[r
].out
== 0 && rld
[r
].in
== 0 && ! rld
[r
].secondary_p
)
6848 /* Skip reloads that already have a register allocated or are
6850 if (rld
[r
].reg_rtx
!= 0 || rld
[r
].optional
)
6853 if (! allocate_reload_reg (chain
, r
, j
== n_reloads
- 1))
6857 /* If that loop got all the way, we have won. */
6864 /* Loop around and try without any inheritance. */
6869 /* First undo everything done by the failed attempt
6870 to allocate with inheritance. */
6871 choose_reload_regs_init (chain
, save_reload_reg_rtx
);
6873 /* Some sanity tests to verify that the reloads found in the first
6874 pass are identical to the ones we have now. */
6875 gcc_assert (chain
->n_reloads
== n_reloads
);
6877 for (i
= 0; i
< n_reloads
; i
++)
6879 if (chain
->rld
[i
].regno
< 0 || chain
->rld
[i
].reg_rtx
!= 0)
6881 gcc_assert (chain
->rld
[i
].when_needed
== rld
[i
].when_needed
);
6882 for (j
= 0; j
< n_spills
; j
++)
6883 if (spill_regs
[j
] == chain
->rld
[i
].regno
)
6884 if (! set_reload_reg (j
, i
))
6885 failed_reload (chain
->insn
, i
);
6889 /* If we thought we could inherit a reload, because it seemed that
6890 nothing else wanted the same reload register earlier in the insn,
6891 verify that assumption, now that all reloads have been assigned.
6892 Likewise for reloads where reload_override_in has been set. */
6894 /* If doing expensive optimizations, do one preliminary pass that doesn't
6895 cancel any inheritance, but removes reloads that have been needed only
6896 for reloads that we know can be inherited. */
6897 for (pass
= flag_expensive_optimizations
; pass
>= 0; pass
--)
6899 for (j
= 0; j
< n_reloads
; j
++)
6901 int r
= reload_order
[j
];
6904 if (reload_inherited
[r
] && rld
[r
].reg_rtx
)
6905 check_reg
= rld
[r
].reg_rtx
;
6906 else if (reload_override_in
[r
]
6907 && (REG_P (reload_override_in
[r
])
6908 || GET_CODE (reload_override_in
[r
]) == SUBREG
))
6909 check_reg
= reload_override_in
[r
];
6912 if (! free_for_value_p (true_regnum (check_reg
), rld
[r
].mode
,
6913 rld
[r
].opnum
, rld
[r
].when_needed
, rld
[r
].in
,
6914 (reload_inherited
[r
]
6915 ? rld
[r
].out
: const0_rtx
),
6920 reload_inherited
[r
] = 0;
6921 reload_override_in
[r
] = 0;
6923 /* If we can inherit a RELOAD_FOR_INPUT, or can use a
6924 reload_override_in, then we do not need its related
6925 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads;
6926 likewise for other reload types.
6927 We handle this by removing a reload when its only replacement
6928 is mentioned in reload_in of the reload we are going to inherit.
6929 A special case are auto_inc expressions; even if the input is
6930 inherited, we still need the address for the output. We can
6931 recognize them because they have RELOAD_OUT set to RELOAD_IN.
6932 If we succeeded removing some reload and we are doing a preliminary
6933 pass just to remove such reloads, make another pass, since the
6934 removal of one reload might allow us to inherit another one. */
6936 && rld
[r
].out
!= rld
[r
].in
6937 && remove_address_replacements (rld
[r
].in
))
6942 /* If we needed a memory location for the reload, we also have to
6943 remove its related reloads. */
6945 && rld
[r
].out
!= rld
[r
].in
6946 && (tem
= replaced_subreg (rld
[r
].in
), REG_P (tem
))
6947 && REGNO (tem
) < FIRST_PSEUDO_REGISTER
6948 && (targetm
.secondary_memory_needed
6949 (rld
[r
].inmode
, REGNO_REG_CLASS (REGNO (tem
)),
6951 && remove_address_replacements
6952 (get_secondary_mem (tem
, rld
[r
].inmode
, rld
[r
].opnum
,
6953 rld
[r
].when_needed
)))
6961 /* Now that reload_override_in is known valid,
6962 actually override reload_in. */
6963 for (j
= 0; j
< n_reloads
; j
++)
6964 if (reload_override_in
[j
])
6965 rld
[j
].in
= reload_override_in
[j
];
6967 /* If this reload won't be done because it has been canceled or is
6968 optional and not inherited, clear reload_reg_rtx so other
6969 routines (such as subst_reloads) don't get confused. */
6970 for (j
= 0; j
< n_reloads
; j
++)
6971 if (rld
[j
].reg_rtx
!= 0
6972 && ((rld
[j
].optional
&& ! reload_inherited
[j
])
6973 || (rld
[j
].in
== 0 && rld
[j
].out
== 0
6974 && ! rld
[j
].secondary_p
)))
6976 int regno
= true_regnum (rld
[j
].reg_rtx
);
6978 if (spill_reg_order
[regno
] >= 0)
6979 clear_reload_reg_in_use (regno
, rld
[j
].opnum
,
6980 rld
[j
].when_needed
, rld
[j
].mode
);
6982 reload_spill_index
[j
] = -1;
6985 /* Record which pseudos and which spill regs have output reloads. */
6986 for (j
= 0; j
< n_reloads
; j
++)
6988 int r
= reload_order
[j
];
6990 i
= reload_spill_index
[r
];
6992 /* I is nonneg if this reload uses a register.
6993 If rld[r].reg_rtx is 0, this is an optional reload
6994 that we opted to ignore. */
6995 if (rld
[r
].out_reg
!= 0 && REG_P (rld
[r
].out_reg
)
6996 && rld
[r
].reg_rtx
!= 0)
6998 int nregno
= REGNO (rld
[r
].out_reg
);
7001 if (nregno
< FIRST_PSEUDO_REGISTER
)
7002 nr
= hard_regno_nregs (nregno
, rld
[r
].mode
);
7005 SET_REGNO_REG_SET (®_has_output_reload
,
7009 add_to_hard_reg_set (®_is_output_reload
, rld
[r
].mode
, i
);
7011 gcc_assert (rld
[r
].when_needed
== RELOAD_OTHER
7012 || rld
[r
].when_needed
== RELOAD_FOR_OUTPUT
7013 || rld
[r
].when_needed
== RELOAD_FOR_INSN
);
7018 /* Deallocate the reload register for reload R. This is called from
7019 remove_address_replacements. */
7022 deallocate_reload_reg (int r
)
7026 if (! rld
[r
].reg_rtx
)
7028 regno
= true_regnum (rld
[r
].reg_rtx
);
7030 if (spill_reg_order
[regno
] >= 0)
7031 clear_reload_reg_in_use (regno
, rld
[r
].opnum
, rld
[r
].when_needed
,
7033 reload_spill_index
[r
] = -1;
7036 /* These arrays are filled by emit_reload_insns and its subroutines. */
7037 static rtx_insn
*input_reload_insns
[MAX_RECOG_OPERANDS
];
7038 static rtx_insn
*other_input_address_reload_insns
= 0;
7039 static rtx_insn
*other_input_reload_insns
= 0;
7040 static rtx_insn
*input_address_reload_insns
[MAX_RECOG_OPERANDS
];
7041 static rtx_insn
*inpaddr_address_reload_insns
[MAX_RECOG_OPERANDS
];
7042 static rtx_insn
*output_reload_insns
[MAX_RECOG_OPERANDS
];
7043 static rtx_insn
*output_address_reload_insns
[MAX_RECOG_OPERANDS
];
7044 static rtx_insn
*outaddr_address_reload_insns
[MAX_RECOG_OPERANDS
];
7045 static rtx_insn
*operand_reload_insns
= 0;
7046 static rtx_insn
*other_operand_reload_insns
= 0;
7047 static rtx_insn
*other_output_reload_insns
[MAX_RECOG_OPERANDS
];
7049 /* Values to be put in spill_reg_store are put here first. Instructions
7050 must only be placed here if the associated reload register reaches
7051 the end of the instruction's reload sequence. */
7052 static rtx_insn
*new_spill_reg_store
[FIRST_PSEUDO_REGISTER
];
7053 static HARD_REG_SET reg_reloaded_died
;
7055 /* Check if *RELOAD_REG is suitable as an intermediate or scratch register
7056 of class NEW_CLASS with mode NEW_MODE. Or alternatively, if alt_reload_reg
7057 is nonzero, if that is suitable. On success, change *RELOAD_REG to the
7058 adjusted register, and return true. Otherwise, return false. */
7060 reload_adjust_reg_for_temp (rtx
*reload_reg
, rtx alt_reload_reg
,
7061 enum reg_class new_class
,
7062 machine_mode new_mode
)
7067 for (reg
= *reload_reg
; reg
; reg
= alt_reload_reg
, alt_reload_reg
= 0)
7069 unsigned regno
= REGNO (reg
);
7071 if (!TEST_HARD_REG_BIT (reg_class_contents
[(int) new_class
], regno
))
7073 if (GET_MODE (reg
) != new_mode
)
7075 if (!targetm
.hard_regno_mode_ok (regno
, new_mode
))
7077 if (hard_regno_nregs (regno
, new_mode
) > REG_NREGS (reg
))
7079 reg
= reload_adjust_reg_for_mode (reg
, new_mode
);
7087 /* Check if *RELOAD_REG is suitable as a scratch register for the reload
7088 pattern with insn_code ICODE, or alternatively, if alt_reload_reg is
7089 nonzero, if that is suitable. On success, change *RELOAD_REG to the
7090 adjusted register, and return true. Otherwise, return false. */
7092 reload_adjust_reg_for_icode (rtx
*reload_reg
, rtx alt_reload_reg
,
7093 enum insn_code icode
)
7096 enum reg_class new_class
= scratch_reload_class (icode
);
7097 machine_mode new_mode
= insn_data
[(int) icode
].operand
[2].mode
;
7099 return reload_adjust_reg_for_temp (reload_reg
, alt_reload_reg
,
7100 new_class
, new_mode
);
7103 /* Generate insns to perform reload RL, which is for the insn in CHAIN and
7104 has the number J. OLD contains the value to be used as input. */
7107 emit_input_reload_insns (class insn_chain
*chain
, struct reload
*rl
,
7110 rtx_insn
*insn
= chain
->insn
;
7112 rtx oldequiv_reg
= 0;
7118 /* delete_output_reload is only invoked properly if old contains
7119 the original pseudo register. Since this is replaced with a
7120 hard reg when RELOAD_OVERRIDE_IN is set, see if we can
7121 find the pseudo in RELOAD_IN_REG. This is also used to
7122 determine whether a secondary reload is needed. */
7123 if (reload_override_in
[j
]
7124 && (REG_P (rl
->in_reg
)
7125 || (GET_CODE (rl
->in_reg
) == SUBREG
7126 && REG_P (SUBREG_REG (rl
->in_reg
)))))
7133 else if (REG_P (oldequiv
))
7134 oldequiv_reg
= oldequiv
;
7135 else if (GET_CODE (oldequiv
) == SUBREG
)
7136 oldequiv_reg
= SUBREG_REG (oldequiv
);
7138 reloadreg
= reload_reg_rtx_for_input
[j
];
7139 mode
= GET_MODE (reloadreg
);
7141 /* If we are reloading from a register that was recently stored in
7142 with an output-reload, see if we can prove there was
7143 actually no need to store the old value in it. */
7145 if (optimize
&& REG_P (oldequiv
)
7146 && REGNO (oldequiv
) < FIRST_PSEUDO_REGISTER
7147 && spill_reg_store
[REGNO (oldequiv
)]
7149 && (dead_or_set_p (insn
, spill_reg_stored_to
[REGNO (oldequiv
)])
7150 || rtx_equal_p (spill_reg_stored_to
[REGNO (oldequiv
)],
7152 delete_output_reload (insn
, j
, REGNO (oldequiv
), reloadreg
);
7154 /* Encapsulate OLDEQUIV into the reload mode, then load RELOADREG from
7157 while (GET_CODE (oldequiv
) == SUBREG
&& GET_MODE (oldequiv
) != mode
)
7158 oldequiv
= SUBREG_REG (oldequiv
);
7159 if (GET_MODE (oldequiv
) != VOIDmode
7160 && mode
!= GET_MODE (oldequiv
))
7161 oldequiv
= gen_lowpart_SUBREG (mode
, oldequiv
);
7163 /* Switch to the right place to emit the reload insns. */
7164 switch (rl
->when_needed
)
7167 where
= &other_input_reload_insns
;
7169 case RELOAD_FOR_INPUT
:
7170 where
= &input_reload_insns
[rl
->opnum
];
7172 case RELOAD_FOR_INPUT_ADDRESS
:
7173 where
= &input_address_reload_insns
[rl
->opnum
];
7175 case RELOAD_FOR_INPADDR_ADDRESS
:
7176 where
= &inpaddr_address_reload_insns
[rl
->opnum
];
7178 case RELOAD_FOR_OUTPUT_ADDRESS
:
7179 where
= &output_address_reload_insns
[rl
->opnum
];
7181 case RELOAD_FOR_OUTADDR_ADDRESS
:
7182 where
= &outaddr_address_reload_insns
[rl
->opnum
];
7184 case RELOAD_FOR_OPERAND_ADDRESS
:
7185 where
= &operand_reload_insns
;
7187 case RELOAD_FOR_OPADDR_ADDR
:
7188 where
= &other_operand_reload_insns
;
7190 case RELOAD_FOR_OTHER_ADDRESS
:
7191 where
= &other_input_address_reload_insns
;
7197 push_to_sequence (*where
);
7199 /* Auto-increment addresses must be reloaded in a special way. */
7200 if (rl
->out
&& ! rl
->out_reg
)
7202 /* We are not going to bother supporting the case where a
7203 incremented register can't be copied directly from
7204 OLDEQUIV since this seems highly unlikely. */
7205 gcc_assert (rl
->secondary_in_reload
< 0);
7207 if (reload_inherited
[j
])
7208 oldequiv
= reloadreg
;
7210 old
= XEXP (rl
->in_reg
, 0);
7212 /* Prevent normal processing of this reload. */
7214 /* Output a special code sequence for this case. */
7215 inc_for_reload (reloadreg
, oldequiv
, rl
->out
, rl
->inc
);
7218 /* If we are reloading a pseudo-register that was set by the previous
7219 insn, see if we can get rid of that pseudo-register entirely
7220 by redirecting the previous insn into our reload register. */
7222 else if (optimize
&& REG_P (old
)
7223 && REGNO (old
) >= FIRST_PSEUDO_REGISTER
7224 && dead_or_set_p (insn
, old
)
7225 /* This is unsafe if some other reload
7226 uses the same reg first. */
7227 && ! conflicts_with_override (reloadreg
)
7228 && free_for_value_p (REGNO (reloadreg
), rl
->mode
, rl
->opnum
,
7229 rl
->when_needed
, old
, rl
->out
, j
, 0))
7231 rtx_insn
*temp
= PREV_INSN (insn
);
7232 while (temp
&& (NOTE_P (temp
) || DEBUG_INSN_P (temp
)))
7233 temp
= PREV_INSN (temp
);
7235 && NONJUMP_INSN_P (temp
)
7236 && GET_CODE (PATTERN (temp
)) == SET
7237 && SET_DEST (PATTERN (temp
)) == old
7238 /* Make sure we can access insn_operand_constraint. */
7239 && asm_noperands (PATTERN (temp
)) < 0
7240 /* This is unsafe if operand occurs more than once in current
7241 insn. Perhaps some occurrences aren't reloaded. */
7242 && count_occurrences (PATTERN (insn
), old
, 0) == 1)
7244 rtx old
= SET_DEST (PATTERN (temp
));
7245 /* Store into the reload register instead of the pseudo. */
7246 SET_DEST (PATTERN (temp
)) = reloadreg
;
7248 /* Verify that resulting insn is valid.
7250 Note that we have replaced the destination of TEMP with
7251 RELOADREG. If TEMP references RELOADREG within an
7252 autoincrement addressing mode, then the resulting insn
7253 is ill-formed and we must reject this optimization. */
7254 extract_insn (temp
);
7255 if (constrain_operands (1, get_enabled_alternatives (temp
))
7256 && (!AUTO_INC_DEC
|| ! find_reg_note (temp
, REG_INC
, reloadreg
)))
7258 /* If the previous insn is an output reload, the source is
7259 a reload register, and its spill_reg_store entry will
7260 contain the previous destination. This is now
7262 if (REG_P (SET_SRC (PATTERN (temp
)))
7263 && REGNO (SET_SRC (PATTERN (temp
))) < FIRST_PSEUDO_REGISTER
)
7265 spill_reg_store
[REGNO (SET_SRC (PATTERN (temp
)))] = 0;
7266 spill_reg_stored_to
[REGNO (SET_SRC (PATTERN (temp
)))] = 0;
7269 /* If these are the only uses of the pseudo reg,
7270 pretend for GDB it lives in the reload reg we used. */
7271 if (REG_N_DEATHS (REGNO (old
)) == 1
7272 && REG_N_SETS (REGNO (old
)) == 1)
7274 reg_renumber
[REGNO (old
)] = REGNO (reloadreg
);
7275 if (ira_conflicts_p
)
7276 /* Inform IRA about the change. */
7277 ira_mark_allocation_change (REGNO (old
));
7278 alter_reg (REGNO (old
), -1, false);
7282 /* Adjust any debug insns between temp and insn. */
7283 while ((temp
= NEXT_INSN (temp
)) != insn
)
7284 if (DEBUG_BIND_INSN_P (temp
))
7285 INSN_VAR_LOCATION_LOC (temp
)
7286 = simplify_replace_rtx (INSN_VAR_LOCATION_LOC (temp
),
7289 gcc_assert (DEBUG_INSN_P (temp
) || NOTE_P (temp
));
7293 SET_DEST (PATTERN (temp
)) = old
;
7298 /* We can't do that, so output an insn to load RELOADREG. */
7300 /* If we have a secondary reload, pick up the secondary register
7301 and icode, if any. If OLDEQUIV and OLD are different or
7302 if this is an in-out reload, recompute whether or not we
7303 still need a secondary register and what the icode should
7304 be. If we still need a secondary register and the class or
7305 icode is different, go back to reloading from OLD if using
7306 OLDEQUIV means that we got the wrong type of register. We
7307 cannot have different class or icode due to an in-out reload
7308 because we don't make such reloads when both the input and
7309 output need secondary reload registers. */
7311 if (! special
&& rl
->secondary_in_reload
>= 0)
7313 rtx second_reload_reg
= 0;
7314 rtx third_reload_reg
= 0;
7315 int secondary_reload
= rl
->secondary_in_reload
;
7316 rtx real_oldequiv
= oldequiv
;
7319 enum insn_code icode
;
7320 enum insn_code tertiary_icode
= CODE_FOR_nothing
;
7322 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
7323 and similarly for OLD.
7324 See comments in get_secondary_reload in reload.c. */
7325 /* If it is a pseudo that cannot be replaced with its
7326 equivalent MEM, we must fall back to reload_in, which
7327 will have all the necessary substitutions registered.
7328 Likewise for a pseudo that can't be replaced with its
7329 equivalent constant.
7331 Take extra care for subregs of such pseudos. Note that
7332 we cannot use reg_equiv_mem in this case because it is
7333 not in the right mode. */
7336 if (GET_CODE (tmp
) == SUBREG
)
7337 tmp
= SUBREG_REG (tmp
);
7339 && REGNO (tmp
) >= FIRST_PSEUDO_REGISTER
7340 && (reg_equiv_memory_loc (REGNO (tmp
)) != 0
7341 || reg_equiv_constant (REGNO (tmp
)) != 0))
7343 if (! reg_equiv_mem (REGNO (tmp
))
7344 || num_not_at_initial_offset
7345 || GET_CODE (oldequiv
) == SUBREG
)
7346 real_oldequiv
= rl
->in
;
7348 real_oldequiv
= reg_equiv_mem (REGNO (tmp
));
7352 if (GET_CODE (tmp
) == SUBREG
)
7353 tmp
= SUBREG_REG (tmp
);
7355 && REGNO (tmp
) >= FIRST_PSEUDO_REGISTER
7356 && (reg_equiv_memory_loc (REGNO (tmp
)) != 0
7357 || reg_equiv_constant (REGNO (tmp
)) != 0))
7359 if (! reg_equiv_mem (REGNO (tmp
))
7360 || num_not_at_initial_offset
7361 || GET_CODE (old
) == SUBREG
)
7364 real_old
= reg_equiv_mem (REGNO (tmp
));
7367 second_reload_reg
= rld
[secondary_reload
].reg_rtx
;
7368 if (rld
[secondary_reload
].secondary_in_reload
>= 0)
7370 int tertiary_reload
= rld
[secondary_reload
].secondary_in_reload
;
7372 third_reload_reg
= rld
[tertiary_reload
].reg_rtx
;
7373 tertiary_icode
= rld
[secondary_reload
].secondary_in_icode
;
7374 /* We'd have to add more code for quartary reloads. */
7375 gcc_assert (rld
[tertiary_reload
].secondary_in_reload
< 0);
7377 icode
= rl
->secondary_in_icode
;
7379 if ((old
!= oldequiv
&& ! rtx_equal_p (old
, oldequiv
))
7380 || (rl
->in
!= 0 && rl
->out
!= 0))
7382 secondary_reload_info sri
, sri2
;
7383 enum reg_class new_class
, new_t_class
;
7385 sri
.icode
= CODE_FOR_nothing
;
7386 sri
.prev_sri
= NULL
;
7388 = (enum reg_class
) targetm
.secondary_reload (1, real_oldequiv
,
7392 if (new_class
== NO_REGS
&& sri
.icode
== CODE_FOR_nothing
)
7393 second_reload_reg
= 0;
7394 else if (new_class
== NO_REGS
)
7396 if (reload_adjust_reg_for_icode (&second_reload_reg
,
7398 (enum insn_code
) sri
.icode
))
7400 icode
= (enum insn_code
) sri
.icode
;
7401 third_reload_reg
= 0;
7406 real_oldequiv
= real_old
;
7409 else if (sri
.icode
!= CODE_FOR_nothing
)
7410 /* We currently lack a way to express this in reloads. */
7414 sri2
.icode
= CODE_FOR_nothing
;
7415 sri2
.prev_sri
= &sri
;
7417 = (enum reg_class
) targetm
.secondary_reload (1, real_oldequiv
,
7420 if (new_t_class
== NO_REGS
&& sri2
.icode
== CODE_FOR_nothing
)
7422 if (reload_adjust_reg_for_temp (&second_reload_reg
,
7426 third_reload_reg
= 0;
7427 tertiary_icode
= (enum insn_code
) sri2
.icode
;
7432 real_oldequiv
= real_old
;
7435 else if (new_t_class
== NO_REGS
&& sri2
.icode
!= CODE_FOR_nothing
)
7437 rtx intermediate
= second_reload_reg
;
7439 if (reload_adjust_reg_for_temp (&intermediate
, NULL
,
7441 && reload_adjust_reg_for_icode (&third_reload_reg
, NULL
,
7445 second_reload_reg
= intermediate
;
7446 tertiary_icode
= (enum insn_code
) sri2
.icode
;
7451 real_oldequiv
= real_old
;
7454 else if (new_t_class
!= NO_REGS
&& sri2
.icode
== CODE_FOR_nothing
)
7456 rtx intermediate
= second_reload_reg
;
7458 if (reload_adjust_reg_for_temp (&intermediate
, NULL
,
7460 && reload_adjust_reg_for_temp (&third_reload_reg
, NULL
,
7463 second_reload_reg
= intermediate
;
7464 tertiary_icode
= (enum insn_code
) sri2
.icode
;
7469 real_oldequiv
= real_old
;
7474 /* This could be handled more intelligently too. */
7476 real_oldequiv
= real_old
;
7481 /* If we still need a secondary reload register, check
7482 to see if it is being used as a scratch or intermediate
7483 register and generate code appropriately. If we need
7484 a scratch register, use REAL_OLDEQUIV since the form of
7485 the insn may depend on the actual address if it is
7488 if (second_reload_reg
)
7490 if (icode
!= CODE_FOR_nothing
)
7492 /* We'd have to add extra code to handle this case. */
7493 gcc_assert (!third_reload_reg
);
7495 emit_insn (GEN_FCN (icode
) (reloadreg
, real_oldequiv
,
7496 second_reload_reg
));
7501 /* See if we need a scratch register to load the
7502 intermediate register (a tertiary reload). */
7503 if (tertiary_icode
!= CODE_FOR_nothing
)
7505 emit_insn ((GEN_FCN (tertiary_icode
)
7506 (second_reload_reg
, real_oldequiv
,
7507 third_reload_reg
)));
7509 else if (third_reload_reg
)
7511 gen_reload (third_reload_reg
, real_oldequiv
,
7514 gen_reload (second_reload_reg
, third_reload_reg
,
7519 gen_reload (second_reload_reg
, real_oldequiv
,
7523 oldequiv
= second_reload_reg
;
7528 if (! special
&& ! rtx_equal_p (reloadreg
, oldequiv
))
7530 rtx real_oldequiv
= oldequiv
;
7532 if ((REG_P (oldequiv
)
7533 && REGNO (oldequiv
) >= FIRST_PSEUDO_REGISTER
7534 && (reg_equiv_memory_loc (REGNO (oldequiv
)) != 0
7535 || reg_equiv_constant (REGNO (oldequiv
)) != 0))
7536 || (GET_CODE (oldequiv
) == SUBREG
7537 && REG_P (SUBREG_REG (oldequiv
))
7538 && (REGNO (SUBREG_REG (oldequiv
))
7539 >= FIRST_PSEUDO_REGISTER
)
7540 && ((reg_equiv_memory_loc (REGNO (SUBREG_REG (oldequiv
))) != 0)
7541 || (reg_equiv_constant (REGNO (SUBREG_REG (oldequiv
))) != 0)))
7542 || (CONSTANT_P (oldequiv
)
7543 && (targetm
.preferred_reload_class (oldequiv
,
7544 REGNO_REG_CLASS (REGNO (reloadreg
)))
7546 real_oldequiv
= rl
->in
;
7547 gen_reload (reloadreg
, real_oldequiv
, rl
->opnum
,
7551 if (cfun
->can_throw_non_call_exceptions
)
7552 copy_reg_eh_region_note_forward (insn
, get_insns (), NULL
);
7554 /* End this sequence. */
7555 *where
= get_insns ();
7558 /* Update reload_override_in so that delete_address_reloads_1
7559 can see the actual register usage. */
7561 reload_override_in
[j
] = oldequiv
;
7564 /* Generate insns to for the output reload RL, which is for the insn described
7565 by CHAIN and has the number J. */
7567 emit_output_reload_insns (class insn_chain
*chain
, struct reload
*rl
,
7571 rtx_insn
*insn
= chain
->insn
;
7578 if (rl
->when_needed
== RELOAD_OTHER
)
7581 push_to_sequence (output_reload_insns
[rl
->opnum
]);
7583 rl_reg_rtx
= reload_reg_rtx_for_output
[j
];
7584 mode
= GET_MODE (rl_reg_rtx
);
7586 reloadreg
= rl_reg_rtx
;
7588 /* If we need two reload regs, set RELOADREG to the intermediate
7589 one, since it will be stored into OLD. We might need a secondary
7590 register only for an input reload, so check again here. */
7592 if (rl
->secondary_out_reload
>= 0)
7595 int secondary_reload
= rl
->secondary_out_reload
;
7596 int tertiary_reload
= rld
[secondary_reload
].secondary_out_reload
;
7598 if (REG_P (old
) && REGNO (old
) >= FIRST_PSEUDO_REGISTER
7599 && reg_equiv_mem (REGNO (old
)) != 0)
7600 real_old
= reg_equiv_mem (REGNO (old
));
7602 if (secondary_reload_class (0, rl
->rclass
, mode
, real_old
) != NO_REGS
)
7604 rtx second_reloadreg
= reloadreg
;
7605 reloadreg
= rld
[secondary_reload
].reg_rtx
;
7607 /* See if RELOADREG is to be used as a scratch register
7608 or as an intermediate register. */
7609 if (rl
->secondary_out_icode
!= CODE_FOR_nothing
)
7611 /* We'd have to add extra code to handle this case. */
7612 gcc_assert (tertiary_reload
< 0);
7614 emit_insn ((GEN_FCN (rl
->secondary_out_icode
)
7615 (real_old
, second_reloadreg
, reloadreg
)));
7620 /* See if we need both a scratch and intermediate reload
7623 enum insn_code tertiary_icode
7624 = rld
[secondary_reload
].secondary_out_icode
;
7626 /* We'd have to add more code for quartary reloads. */
7627 gcc_assert (tertiary_reload
< 0
7628 || rld
[tertiary_reload
].secondary_out_reload
< 0);
7630 if (GET_MODE (reloadreg
) != mode
)
7631 reloadreg
= reload_adjust_reg_for_mode (reloadreg
, mode
);
7633 if (tertiary_icode
!= CODE_FOR_nothing
)
7635 rtx third_reloadreg
= rld
[tertiary_reload
].reg_rtx
;
7637 /* Copy primary reload reg to secondary reload reg.
7638 (Note that these have been swapped above, then
7639 secondary reload reg to OLD using our insn.) */
7641 /* If REAL_OLD is a paradoxical SUBREG, remove it
7642 and try to put the opposite SUBREG on
7644 strip_paradoxical_subreg (&real_old
, &reloadreg
);
7646 gen_reload (reloadreg
, second_reloadreg
,
7647 rl
->opnum
, rl
->when_needed
);
7648 emit_insn ((GEN_FCN (tertiary_icode
)
7649 (real_old
, reloadreg
, third_reloadreg
)));
7655 /* Copy between the reload regs here and then to
7658 gen_reload (reloadreg
, second_reloadreg
,
7659 rl
->opnum
, rl
->when_needed
);
7660 if (tertiary_reload
>= 0)
7662 rtx third_reloadreg
= rld
[tertiary_reload
].reg_rtx
;
7664 gen_reload (third_reloadreg
, reloadreg
,
7665 rl
->opnum
, rl
->when_needed
);
7666 reloadreg
= third_reloadreg
;
7673 /* Output the last reload insn. */
7678 /* Don't output the last reload if OLD is not the dest of
7679 INSN and is in the src and is clobbered by INSN. */
7680 if (! flag_expensive_optimizations
7682 || !(set
= single_set (insn
))
7683 || rtx_equal_p (old
, SET_DEST (set
))
7684 || !reg_mentioned_p (old
, SET_SRC (set
))
7685 || !((REGNO (old
) < FIRST_PSEUDO_REGISTER
)
7686 && regno_clobbered_p (REGNO (old
), insn
, rl
->mode
, 0)))
7687 gen_reload (old
, reloadreg
, rl
->opnum
,
7691 /* Look at all insns we emitted, just to be safe. */
7692 for (p
= get_insns (); p
; p
= NEXT_INSN (p
))
7695 rtx pat
= PATTERN (p
);
7697 /* If this output reload doesn't come from a spill reg,
7698 clear any memory of reloaded copies of the pseudo reg.
7699 If this output reload comes from a spill reg,
7700 reg_has_output_reload will make this do nothing. */
7701 note_stores (p
, forget_old_reloads_1
, NULL
);
7703 if (reg_mentioned_p (rl_reg_rtx
, pat
))
7705 rtx set
= single_set (insn
);
7706 if (reload_spill_index
[j
] < 0
7708 && SET_SRC (set
) == rl_reg_rtx
)
7710 int src
= REGNO (SET_SRC (set
));
7712 reload_spill_index
[j
] = src
;
7713 SET_HARD_REG_BIT (reg_is_output_reload
, src
);
7714 if (find_regno_note (insn
, REG_DEAD
, src
))
7715 SET_HARD_REG_BIT (reg_reloaded_died
, src
);
7717 if (HARD_REGISTER_P (rl_reg_rtx
))
7719 int s
= rl
->secondary_out_reload
;
7720 set
= single_set (p
);
7721 /* If this reload copies only to the secondary reload
7722 register, the secondary reload does the actual
7724 if (s
>= 0 && set
== NULL_RTX
)
7725 /* We can't tell what function the secondary reload
7726 has and where the actual store to the pseudo is
7727 made; leave new_spill_reg_store alone. */
7730 && SET_SRC (set
) == rl_reg_rtx
7731 && SET_DEST (set
) == rld
[s
].reg_rtx
)
7733 /* Usually the next instruction will be the
7734 secondary reload insn; if we can confirm
7735 that it is, setting new_spill_reg_store to
7736 that insn will allow an extra optimization. */
7737 rtx s_reg
= rld
[s
].reg_rtx
;
7738 rtx_insn
*next
= NEXT_INSN (p
);
7739 rld
[s
].out
= rl
->out
;
7740 rld
[s
].out_reg
= rl
->out_reg
;
7741 set
= single_set (next
);
7742 if (set
&& SET_SRC (set
) == s_reg
7743 && reload_reg_rtx_reaches_end_p (s_reg
, s
))
7745 SET_HARD_REG_BIT (reg_is_output_reload
,
7747 new_spill_reg_store
[REGNO (s_reg
)] = next
;
7750 else if (reload_reg_rtx_reaches_end_p (rl_reg_rtx
, j
))
7751 new_spill_reg_store
[REGNO (rl_reg_rtx
)] = p
;
7756 if (rl
->when_needed
== RELOAD_OTHER
)
7758 emit_insn (other_output_reload_insns
[rl
->opnum
]);
7759 other_output_reload_insns
[rl
->opnum
] = get_insns ();
7762 output_reload_insns
[rl
->opnum
] = get_insns ();
7764 if (cfun
->can_throw_non_call_exceptions
)
7765 copy_reg_eh_region_note_forward (insn
, get_insns (), NULL
);
7770 /* Do input reloading for reload RL, which is for the insn described by CHAIN
7771 and has the number J. */
7773 do_input_reload (class insn_chain
*chain
, struct reload
*rl
, int j
)
7775 rtx_insn
*insn
= chain
->insn
;
7776 rtx old
= (rl
->in
&& MEM_P (rl
->in
)
7777 ? rl
->in_reg
: rl
->in
);
7778 rtx reg_rtx
= rl
->reg_rtx
;
7784 /* Determine the mode to reload in.
7785 This is very tricky because we have three to choose from.
7786 There is the mode the insn operand wants (rl->inmode).
7787 There is the mode of the reload register RELOADREG.
7788 There is the intrinsic mode of the operand, which we could find
7789 by stripping some SUBREGs.
7790 It turns out that RELOADREG's mode is irrelevant:
7791 we can change that arbitrarily.
7793 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
7794 then the reload reg may not support QImode moves, so use SImode.
7795 If foo is in memory due to spilling a pseudo reg, this is safe,
7796 because the QImode value is in the least significant part of a
7797 slot big enough for a SImode. If foo is some other sort of
7798 memory reference, then it is impossible to reload this case,
7799 so previous passes had better make sure this never happens.
7801 Then consider a one-word union which has SImode and one of its
7802 members is a float, being fetched as (SUBREG:SF union:SI).
7803 We must fetch that as SFmode because we could be loading into
7804 a float-only register. In this case OLD's mode is correct.
7806 Consider an immediate integer: it has VOIDmode. Here we need
7807 to get a mode from something else.
7809 In some cases, there is a fourth mode, the operand's
7810 containing mode. If the insn specifies a containing mode for
7811 this operand, it overrides all others.
7813 I am not sure whether the algorithm here is always right,
7814 but it does the right things in those cases. */
7816 mode
= GET_MODE (old
);
7817 if (mode
== VOIDmode
)
7820 /* We cannot use gen_lowpart_common since it can do the wrong thing
7821 when REG_RTX has a multi-word mode. Note that REG_RTX must
7822 always be a REG here. */
7823 if (GET_MODE (reg_rtx
) != mode
)
7824 reg_rtx
= reload_adjust_reg_for_mode (reg_rtx
, mode
);
7826 reload_reg_rtx_for_input
[j
] = reg_rtx
;
7829 /* AUTO_INC reloads need to be handled even if inherited. We got an
7830 AUTO_INC reload if reload_out is set but reload_out_reg isn't. */
7831 && (! reload_inherited
[j
] || (rl
->out
&& ! rl
->out_reg
))
7832 && ! rtx_equal_p (reg_rtx
, old
)
7834 emit_input_reload_insns (chain
, rld
+ j
, old
, j
);
7836 /* When inheriting a wider reload, we have a MEM in rl->in,
7837 e.g. inheriting a SImode output reload for
7838 (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */
7839 if (optimize
&& reload_inherited
[j
] && rl
->in
7841 && MEM_P (rl
->in_reg
)
7842 && reload_spill_index
[j
] >= 0
7843 && TEST_HARD_REG_BIT (reg_reloaded_valid
, reload_spill_index
[j
]))
7844 rl
->in
= regno_reg_rtx
[reg_reloaded_contents
[reload_spill_index
[j
]]];
7846 /* If we are reloading a register that was recently stored in with an
7847 output-reload, see if we can prove there was
7848 actually no need to store the old value in it. */
7851 && (reload_inherited
[j
] || reload_override_in
[j
])
7854 && spill_reg_store
[REGNO (reg_rtx
)] != 0
7856 /* There doesn't seem to be any reason to restrict this to pseudos
7857 and doing so loses in the case where we are copying from a
7858 register of the wrong class. */
7859 && !HARD_REGISTER_P (spill_reg_stored_to
[REGNO (reg_rtx
)])
7861 /* The insn might have already some references to stackslots
7862 replaced by MEMs, while reload_out_reg still names the
7864 && (dead_or_set_p (insn
, spill_reg_stored_to
[REGNO (reg_rtx
)])
7865 || rtx_equal_p (spill_reg_stored_to
[REGNO (reg_rtx
)], rl
->out_reg
)))
7866 delete_output_reload (insn
, j
, REGNO (reg_rtx
), reg_rtx
);
7869 /* Do output reloading for reload RL, which is for the insn described by
7870 CHAIN and has the number J.
7871 ??? At some point we need to support handling output reloads of
7872 JUMP_INSNs or insns that set cc0. */
7874 do_output_reload (class insn_chain
*chain
, struct reload
*rl
, int j
)
7877 rtx_insn
*insn
= chain
->insn
;
7878 /* If this is an output reload that stores something that is
7879 not loaded in this same reload, see if we can eliminate a previous
7881 rtx pseudo
= rl
->out_reg
;
7882 rtx reg_rtx
= rl
->reg_rtx
;
7884 if (rl
->out
&& reg_rtx
)
7888 /* Determine the mode to reload in.
7889 See comments above (for input reloading). */
7890 mode
= GET_MODE (rl
->out
);
7891 if (mode
== VOIDmode
)
7893 /* VOIDmode should never happen for an output. */
7894 if (asm_noperands (PATTERN (insn
)) < 0)
7895 /* It's the compiler's fault. */
7896 fatal_insn ("VOIDmode on an output", insn
);
7897 error_for_asm (insn
, "output operand is constant in %<asm%>");
7898 /* Prevent crash--use something we know is valid. */
7900 rl
->out
= gen_rtx_REG (mode
, REGNO (reg_rtx
));
7902 if (GET_MODE (reg_rtx
) != mode
)
7903 reg_rtx
= reload_adjust_reg_for_mode (reg_rtx
, mode
);
7905 reload_reg_rtx_for_output
[j
] = reg_rtx
;
7910 && ! rtx_equal_p (rl
->in_reg
, pseudo
)
7911 && REGNO (pseudo
) >= FIRST_PSEUDO_REGISTER
7912 && reg_last_reload_reg
[REGNO (pseudo
)])
7914 int pseudo_no
= REGNO (pseudo
);
7915 int last_regno
= REGNO (reg_last_reload_reg
[pseudo_no
]);
7917 /* We don't need to test full validity of last_regno for
7918 inherit here; we only want to know if the store actually
7919 matches the pseudo. */
7920 if (TEST_HARD_REG_BIT (reg_reloaded_valid
, last_regno
)
7921 && reg_reloaded_contents
[last_regno
] == pseudo_no
7922 && spill_reg_store
[last_regno
]
7923 && rtx_equal_p (pseudo
, spill_reg_stored_to
[last_regno
]))
7924 delete_output_reload (insn
, j
, last_regno
, reg_rtx
);
7930 || rtx_equal_p (old
, reg_rtx
))
7933 /* An output operand that dies right away does need a reload,
7934 but need not be copied from it. Show the new location in the
7936 if ((REG_P (old
) || GET_CODE (old
) == SCRATCH
)
7937 && (note
= find_reg_note (insn
, REG_UNUSED
, old
)) != 0)
7939 XEXP (note
, 0) = reg_rtx
;
7942 /* Likewise for a SUBREG of an operand that dies. */
7943 else if (GET_CODE (old
) == SUBREG
7944 && REG_P (SUBREG_REG (old
))
7945 && (note
= find_reg_note (insn
, REG_UNUSED
,
7946 SUBREG_REG (old
))) != 0)
7948 XEXP (note
, 0) = gen_lowpart_common (GET_MODE (old
), reg_rtx
);
7951 else if (GET_CODE (old
) == SCRATCH
)
7952 /* If we aren't optimizing, there won't be a REG_UNUSED note,
7953 but we don't want to make an output reload. */
7956 /* If is a JUMP_INSN, we can't support output reloads yet. */
7957 gcc_assert (NONJUMP_INSN_P (insn
));
7959 emit_output_reload_insns (chain
, rld
+ j
, j
);
7962 /* A reload copies values of MODE from register SRC to register DEST.
7963 Return true if it can be treated for inheritance purposes like a
7964 group of reloads, each one reloading a single hard register. The
7965 caller has already checked that (reg:MODE SRC) and (reg:MODE DEST)
7966 occupy the same number of hard registers. */
7969 inherit_piecemeal_p (int dest ATTRIBUTE_UNUSED
,
7970 int src ATTRIBUTE_UNUSED
,
7971 machine_mode mode ATTRIBUTE_UNUSED
)
7973 return (REG_CAN_CHANGE_MODE_P (dest
, mode
, reg_raw_mode
[dest
])
7974 && REG_CAN_CHANGE_MODE_P (src
, mode
, reg_raw_mode
[src
]));
7977 /* Output insns to reload values in and out of the chosen reload regs. */
7980 emit_reload_insns (class insn_chain
*chain
)
7982 rtx_insn
*insn
= chain
->insn
;
7986 CLEAR_HARD_REG_SET (reg_reloaded_died
);
7988 for (j
= 0; j
< reload_n_operands
; j
++)
7989 input_reload_insns
[j
] = input_address_reload_insns
[j
]
7990 = inpaddr_address_reload_insns
[j
]
7991 = output_reload_insns
[j
] = output_address_reload_insns
[j
]
7992 = outaddr_address_reload_insns
[j
]
7993 = other_output_reload_insns
[j
] = 0;
7994 other_input_address_reload_insns
= 0;
7995 other_input_reload_insns
= 0;
7996 operand_reload_insns
= 0;
7997 other_operand_reload_insns
= 0;
7999 /* Dump reloads into the dump file. */
8002 fprintf (dump_file
, "\nReloads for insn # %d\n", INSN_UID (insn
));
8003 debug_reload_to_stream (dump_file
);
8006 for (j
= 0; j
< n_reloads
; j
++)
8007 if (rld
[j
].reg_rtx
&& HARD_REGISTER_P (rld
[j
].reg_rtx
))
8011 for (i
= REGNO (rld
[j
].reg_rtx
); i
< END_REGNO (rld
[j
].reg_rtx
); i
++)
8012 new_spill_reg_store
[i
] = 0;
8015 /* Now output the instructions to copy the data into and out of the
8016 reload registers. Do these in the order that the reloads were reported,
8017 since reloads of base and index registers precede reloads of operands
8018 and the operands may need the base and index registers reloaded. */
8020 for (j
= 0; j
< n_reloads
; j
++)
8022 do_input_reload (chain
, rld
+ j
, j
);
8023 do_output_reload (chain
, rld
+ j
, j
);
8026 /* Now write all the insns we made for reloads in the order expected by
8027 the allocation functions. Prior to the insn being reloaded, we write
8028 the following reloads:
8030 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
8032 RELOAD_OTHER reloads.
8034 For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
8035 by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
8036 RELOAD_FOR_INPUT reload for the operand.
8038 RELOAD_FOR_OPADDR_ADDRS reloads.
8040 RELOAD_FOR_OPERAND_ADDRESS reloads.
8042 After the insn being reloaded, we write the following:
8044 For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
8045 by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
8046 RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
8047 reloads for the operand. The RELOAD_OTHER output reloads are
8048 output in descending order by reload number. */
8050 emit_insn_before (other_input_address_reload_insns
, insn
);
8051 emit_insn_before (other_input_reload_insns
, insn
);
8053 for (j
= 0; j
< reload_n_operands
; j
++)
8055 emit_insn_before (inpaddr_address_reload_insns
[j
], insn
);
8056 emit_insn_before (input_address_reload_insns
[j
], insn
);
8057 emit_insn_before (input_reload_insns
[j
], insn
);
8060 emit_insn_before (other_operand_reload_insns
, insn
);
8061 emit_insn_before (operand_reload_insns
, insn
);
8063 for (j
= 0; j
< reload_n_operands
; j
++)
8065 rtx_insn
*x
= emit_insn_after (outaddr_address_reload_insns
[j
], insn
);
8066 x
= emit_insn_after (output_address_reload_insns
[j
], x
);
8067 x
= emit_insn_after (output_reload_insns
[j
], x
);
8068 emit_insn_after (other_output_reload_insns
[j
], x
);
8071 /* For all the spill regs newly reloaded in this instruction,
8072 record what they were reloaded from, so subsequent instructions
8073 can inherit the reloads.
8075 Update spill_reg_store for the reloads of this insn.
8076 Copy the elements that were updated in the loop above. */
8078 for (j
= 0; j
< n_reloads
; j
++)
8080 int r
= reload_order
[j
];
8081 int i
= reload_spill_index
[r
];
8083 /* If this is a non-inherited input reload from a pseudo, we must
8084 clear any memory of a previous store to the same pseudo. Only do
8085 something if there will not be an output reload for the pseudo
8087 if (rld
[r
].in_reg
!= 0
8088 && ! (reload_inherited
[r
] || reload_override_in
[r
]))
8090 rtx reg
= rld
[r
].in_reg
;
8092 if (GET_CODE (reg
) == SUBREG
)
8093 reg
= SUBREG_REG (reg
);
8096 && REGNO (reg
) >= FIRST_PSEUDO_REGISTER
8097 && !REGNO_REG_SET_P (®_has_output_reload
, REGNO (reg
)))
8099 int nregno
= REGNO (reg
);
8101 if (reg_last_reload_reg
[nregno
])
8103 int last_regno
= REGNO (reg_last_reload_reg
[nregno
]);
8105 if (reg_reloaded_contents
[last_regno
] == nregno
)
8106 spill_reg_store
[last_regno
] = 0;
8111 /* I is nonneg if this reload used a register.
8112 If rld[r].reg_rtx is 0, this is an optional reload
8113 that we opted to ignore. */
8115 if (i
>= 0 && rld
[r
].reg_rtx
!= 0)
8117 int nr
= hard_regno_nregs (i
, GET_MODE (rld
[r
].reg_rtx
));
8120 /* For a multi register reload, we need to check if all or part
8121 of the value lives to the end. */
8122 for (k
= 0; k
< nr
; k
++)
8123 if (reload_reg_reaches_end_p (i
+ k
, r
))
8124 CLEAR_HARD_REG_BIT (reg_reloaded_valid
, i
+ k
);
8126 /* Maybe the spill reg contains a copy of reload_out. */
8128 && (REG_P (rld
[r
].out
)
8130 ? REG_P (rld
[r
].out_reg
)
8131 /* The reload value is an auto-modification of
8132 some kind. For PRE_INC, POST_INC, PRE_DEC
8133 and POST_DEC, we record an equivalence
8134 between the reload register and the operand
8135 on the optimistic assumption that we can make
8136 the equivalence hold. reload_as_needed must
8137 then either make it hold or invalidate the
8140 PRE_MODIFY and POST_MODIFY addresses are reloaded
8141 somewhat differently, and allowing them here leads
8143 : (GET_CODE (rld
[r
].out
) != POST_MODIFY
8144 && GET_CODE (rld
[r
].out
) != PRE_MODIFY
))))
8148 reg
= reload_reg_rtx_for_output
[r
];
8149 if (reload_reg_rtx_reaches_end_p (reg
, r
))
8151 machine_mode mode
= GET_MODE (reg
);
8152 int regno
= REGNO (reg
);
8153 int nregs
= REG_NREGS (reg
);
8154 rtx out
= (REG_P (rld
[r
].out
)
8158 /* AUTO_INC */ : XEXP (rld
[r
].in_reg
, 0));
8159 int out_regno
= REGNO (out
);
8160 int out_nregs
= (!HARD_REGISTER_NUM_P (out_regno
) ? 1
8161 : hard_regno_nregs (out_regno
, mode
));
8164 spill_reg_store
[regno
] = new_spill_reg_store
[regno
];
8165 spill_reg_stored_to
[regno
] = out
;
8166 reg_last_reload_reg
[out_regno
] = reg
;
8168 piecemeal
= (HARD_REGISTER_NUM_P (out_regno
)
8169 && nregs
== out_nregs
8170 && inherit_piecemeal_p (out_regno
, regno
, mode
));
8172 /* If OUT_REGNO is a hard register, it may occupy more than
8173 one register. If it does, say what is in the
8174 rest of the registers assuming that both registers
8175 agree on how many words the object takes. If not,
8176 invalidate the subsequent registers. */
8178 if (HARD_REGISTER_NUM_P (out_regno
))
8179 for (k
= 1; k
< out_nregs
; k
++)
8180 reg_last_reload_reg
[out_regno
+ k
]
8181 = (piecemeal
? regno_reg_rtx
[regno
+ k
] : 0);
8183 /* Now do the inverse operation. */
8184 for (k
= 0; k
< nregs
; k
++)
8186 CLEAR_HARD_REG_BIT (reg_reloaded_dead
, regno
+ k
);
8187 reg_reloaded_contents
[regno
+ k
]
8188 = (!HARD_REGISTER_NUM_P (out_regno
) || !piecemeal
8191 reg_reloaded_insn
[regno
+ k
] = insn
;
8192 SET_HARD_REG_BIT (reg_reloaded_valid
, regno
+ k
);
8193 if (targetm
.hard_regno_call_part_clobbered (NULL
,
8196 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered
,
8199 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered
,
8204 /* Maybe the spill reg contains a copy of reload_in. Only do
8205 something if there will not be an output reload for
8206 the register being reloaded. */
8207 else if (rld
[r
].out_reg
== 0
8209 && ((REG_P (rld
[r
].in
)
8210 && !HARD_REGISTER_P (rld
[r
].in
)
8211 && !REGNO_REG_SET_P (®_has_output_reload
,
8213 || (REG_P (rld
[r
].in_reg
)
8214 && !REGNO_REG_SET_P (®_has_output_reload
,
8215 REGNO (rld
[r
].in_reg
))))
8216 && !reg_set_p (reload_reg_rtx_for_input
[r
], PATTERN (insn
)))
8220 reg
= reload_reg_rtx_for_input
[r
];
8221 if (reload_reg_rtx_reaches_end_p (reg
, r
))
8231 mode
= GET_MODE (reg
);
8232 regno
= REGNO (reg
);
8233 nregs
= REG_NREGS (reg
);
8234 if (REG_P (rld
[r
].in
)
8235 && REGNO (rld
[r
].in
) >= FIRST_PSEUDO_REGISTER
)
8237 else if (REG_P (rld
[r
].in_reg
))
8240 in
= XEXP (rld
[r
].in_reg
, 0);
8241 in_regno
= REGNO (in
);
8243 in_nregs
= (!HARD_REGISTER_NUM_P (in_regno
) ? 1
8244 : hard_regno_nregs (in_regno
, mode
));
8246 reg_last_reload_reg
[in_regno
] = reg
;
8248 piecemeal
= (HARD_REGISTER_NUM_P (in_regno
)
8249 && nregs
== in_nregs
8250 && inherit_piecemeal_p (regno
, in_regno
, mode
));
8252 if (HARD_REGISTER_NUM_P (in_regno
))
8253 for (k
= 1; k
< in_nregs
; k
++)
8254 reg_last_reload_reg
[in_regno
+ k
]
8255 = (piecemeal
? regno_reg_rtx
[regno
+ k
] : 0);
8257 /* Unless we inherited this reload, show we haven't
8258 recently done a store.
8259 Previous stores of inherited auto_inc expressions
8260 also have to be discarded. */
8261 if (! reload_inherited
[r
]
8262 || (rld
[r
].out
&& ! rld
[r
].out_reg
))
8263 spill_reg_store
[regno
] = 0;
8265 for (k
= 0; k
< nregs
; k
++)
8267 CLEAR_HARD_REG_BIT (reg_reloaded_dead
, regno
+ k
);
8268 reg_reloaded_contents
[regno
+ k
]
8269 = (!HARD_REGISTER_NUM_P (in_regno
) || !piecemeal
8272 reg_reloaded_insn
[regno
+ k
] = insn
;
8273 SET_HARD_REG_BIT (reg_reloaded_valid
, regno
+ k
);
8274 if (targetm
.hard_regno_call_part_clobbered (NULL
,
8277 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered
,
8280 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered
,
8287 /* The following if-statement was #if 0'd in 1.34 (or before...).
8288 It's reenabled in 1.35 because supposedly nothing else
8289 deals with this problem. */
8291 /* If a register gets output-reloaded from a non-spill register,
8292 that invalidates any previous reloaded copy of it.
8293 But forget_old_reloads_1 won't get to see it, because
8294 it thinks only about the original insn. So invalidate it here.
8295 Also do the same thing for RELOAD_OTHER constraints where the
8296 output is discarded. */
8298 && ((rld
[r
].out
!= 0
8299 && (REG_P (rld
[r
].out
)
8300 || (MEM_P (rld
[r
].out
)
8301 && REG_P (rld
[r
].out_reg
))))
8302 || (rld
[r
].out
== 0 && rld
[r
].out_reg
8303 && REG_P (rld
[r
].out_reg
))))
8305 rtx out
= ((rld
[r
].out
&& REG_P (rld
[r
].out
))
8306 ? rld
[r
].out
: rld
[r
].out_reg
);
8307 int out_regno
= REGNO (out
);
8308 machine_mode mode
= GET_MODE (out
);
8310 /* REG_RTX is now set or clobbered by the main instruction.
8311 As the comment above explains, forget_old_reloads_1 only
8312 sees the original instruction, and there is no guarantee
8313 that the original instruction also clobbered REG_RTX.
8314 For example, if find_reloads sees that the input side of
8315 a matched operand pair dies in this instruction, it may
8316 use the input register as the reload register.
8318 Calling forget_old_reloads_1 is a waste of effort if
8319 REG_RTX is also the output register.
8321 If we know that REG_RTX holds the value of a pseudo
8322 register, the code after the call will record that fact. */
8323 if (rld
[r
].reg_rtx
&& rld
[r
].reg_rtx
!= out
)
8324 forget_old_reloads_1 (rld
[r
].reg_rtx
, NULL_RTX
, NULL
);
8326 if (!HARD_REGISTER_NUM_P (out_regno
))
8329 rtx_insn
*store_insn
= NULL
;
8331 reg_last_reload_reg
[out_regno
] = 0;
8333 /* If we can find a hard register that is stored, record
8334 the storing insn so that we may delete this insn with
8335 delete_output_reload. */
8336 src_reg
= reload_reg_rtx_for_output
[r
];
8340 if (reload_reg_rtx_reaches_end_p (src_reg
, r
))
8341 store_insn
= new_spill_reg_store
[REGNO (src_reg
)];
8347 /* If this is an optional reload, try to find the
8348 source reg from an input reload. */
8349 rtx set
= single_set (insn
);
8350 if (set
&& SET_DEST (set
) == rld
[r
].out
)
8354 src_reg
= SET_SRC (set
);
8356 for (k
= 0; k
< n_reloads
; k
++)
8358 if (rld
[k
].in
== src_reg
)
8360 src_reg
= reload_reg_rtx_for_input
[k
];
8366 if (src_reg
&& REG_P (src_reg
)
8367 && REGNO (src_reg
) < FIRST_PSEUDO_REGISTER
)
8369 int src_regno
, src_nregs
, k
;
8372 gcc_assert (GET_MODE (src_reg
) == mode
);
8373 src_regno
= REGNO (src_reg
);
8374 src_nregs
= hard_regno_nregs (src_regno
, mode
);
8375 /* The place where to find a death note varies with
8376 PRESERVE_DEATH_INFO_REGNO_P . The condition is not
8377 necessarily checked exactly in the code that moves
8378 notes, so just check both locations. */
8379 note
= find_regno_note (insn
, REG_DEAD
, src_regno
);
8380 if (! note
&& store_insn
)
8381 note
= find_regno_note (store_insn
, REG_DEAD
, src_regno
);
8382 for (k
= 0; k
< src_nregs
; k
++)
8384 spill_reg_store
[src_regno
+ k
] = store_insn
;
8385 spill_reg_stored_to
[src_regno
+ k
] = out
;
8386 reg_reloaded_contents
[src_regno
+ k
] = out_regno
;
8387 reg_reloaded_insn
[src_regno
+ k
] = store_insn
;
8388 CLEAR_HARD_REG_BIT (reg_reloaded_dead
, src_regno
+ k
);
8389 SET_HARD_REG_BIT (reg_reloaded_valid
, src_regno
+ k
);
8390 if (targetm
.hard_regno_call_part_clobbered
8391 (NULL
, src_regno
+ k
, mode
))
8392 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered
,
8395 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered
,
8397 SET_HARD_REG_BIT (reg_is_output_reload
, src_regno
+ k
);
8399 SET_HARD_REG_BIT (reg_reloaded_died
, src_regno
);
8401 CLEAR_HARD_REG_BIT (reg_reloaded_died
, src_regno
);
8403 reg_last_reload_reg
[out_regno
] = src_reg
;
8404 /* We have to set reg_has_output_reload here, or else
8405 forget_old_reloads_1 will clear reg_last_reload_reg
8407 SET_REGNO_REG_SET (®_has_output_reload
,
8413 int k
, out_nregs
= hard_regno_nregs (out_regno
, mode
);
8415 for (k
= 0; k
< out_nregs
; k
++)
8416 reg_last_reload_reg
[out_regno
+ k
] = 0;
8420 reg_reloaded_dead
|= reg_reloaded_died
;
8423 /* Go through the motions to emit INSN and test if it is strictly valid.
8424 Return the emitted insn if valid, else return NULL. */
8427 emit_insn_if_valid_for_reload (rtx pat
)
8429 rtx_insn
*last
= get_last_insn ();
8432 rtx_insn
*insn
= emit_insn (pat
);
8433 code
= recog_memoized (insn
);
8437 extract_insn (insn
);
8438 /* We want constrain operands to treat this insn strictly in its
8439 validity determination, i.e., the way it would after reload has
8441 if (constrain_operands (1, get_enabled_alternatives (insn
)))
8445 delete_insns_since (last
);
8449 /* Emit code to perform a reload from IN (which may be a reload register) to
8450 OUT (which may also be a reload register). IN or OUT is from operand
8451 OPNUM with reload type TYPE.
8453 Returns first insn emitted. */
8456 gen_reload (rtx out
, rtx in
, int opnum
, enum reload_type type
)
8458 rtx_insn
*last
= get_last_insn ();
8462 /* If IN is a paradoxical SUBREG, remove it and try to put the
8463 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
8464 if (!strip_paradoxical_subreg (&in
, &out
))
8465 strip_paradoxical_subreg (&out
, &in
);
8467 /* How to do this reload can get quite tricky. Normally, we are being
8468 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
8469 register that didn't get a hard register. In that case we can just
8470 call emit_move_insn.
8472 We can also be asked to reload a PLUS that adds a register or a MEM to
8473 another register, constant or MEM. This can occur during frame pointer
8474 elimination and while reloading addresses. This case is handled by
8475 trying to emit a single insn to perform the add. If it is not valid,
8476 we use a two insn sequence.
8478 Or we can be asked to reload an unary operand that was a fragment of
8479 an addressing mode, into a register. If it isn't recognized as-is,
8480 we try making the unop operand and the reload-register the same:
8481 (set reg:X (unop:X expr:Y))
8482 -> (set reg:Y expr:Y) (set reg:X (unop:X reg:Y)).
8484 Finally, we could be called to handle an 'o' constraint by putting
8485 an address into a register. In that case, we first try to do this
8486 with a named pattern of "reload_load_address". If no such pattern
8487 exists, we just emit a SET insn and hope for the best (it will normally
8488 be valid on machines that use 'o').
8490 This entire process is made complex because reload will never
8491 process the insns we generate here and so we must ensure that
8492 they will fit their constraints and also by the fact that parts of
8493 IN might be being reloaded separately and replaced with spill registers.
8494 Because of this, we are, in some sense, just guessing the right approach
8495 here. The one listed above seems to work.
8497 ??? At some point, this whole thing needs to be rethought. */
8499 if (GET_CODE (in
) == PLUS
8500 && (REG_P (XEXP (in
, 0))
8501 || GET_CODE (XEXP (in
, 0)) == SUBREG
8502 || MEM_P (XEXP (in
, 0)))
8503 && (REG_P (XEXP (in
, 1))
8504 || GET_CODE (XEXP (in
, 1)) == SUBREG
8505 || CONSTANT_P (XEXP (in
, 1))
8506 || MEM_P (XEXP (in
, 1))))
8508 /* We need to compute the sum of a register or a MEM and another
8509 register, constant, or MEM, and put it into the reload
8510 register. The best possible way of doing this is if the machine
8511 has a three-operand ADD insn that accepts the required operands.
8513 The simplest approach is to try to generate such an insn and see if it
8514 is recognized and matches its constraints. If so, it can be used.
8516 It might be better not to actually emit the insn unless it is valid,
8517 but we need to pass the insn as an operand to `recog' and
8518 `extract_insn' and it is simpler to emit and then delete the insn if
8519 not valid than to dummy things up. */
8523 enum insn_code code
;
8525 op0
= find_replacement (&XEXP (in
, 0));
8526 op1
= find_replacement (&XEXP (in
, 1));
8528 /* Since constraint checking is strict, commutativity won't be
8529 checked, so we need to do that here to avoid spurious failure
8530 if the add instruction is two-address and the second operand
8531 of the add is the same as the reload reg, which is frequently
8532 the case. If the insn would be A = B + A, rearrange it so
8533 it will be A = A + B as constrain_operands expects. */
8535 if (REG_P (XEXP (in
, 1))
8536 && REGNO (out
) == REGNO (XEXP (in
, 1)))
8537 tem
= op0
, op0
= op1
, op1
= tem
;
8539 if (op0
!= XEXP (in
, 0) || op1
!= XEXP (in
, 1))
8540 in
= gen_rtx_PLUS (GET_MODE (in
), op0
, op1
);
8542 insn
= emit_insn_if_valid_for_reload (gen_rtx_SET (out
, in
));
8546 /* If that failed, we must use a conservative two-insn sequence.
8548 Use a move to copy one operand into the reload register. Prefer
8549 to reload a constant, MEM or pseudo since the move patterns can
8550 handle an arbitrary operand. If OP1 is not a constant, MEM or
8551 pseudo and OP1 is not a valid operand for an add instruction, then
8554 After reloading one of the operands into the reload register, add
8555 the reload register to the output register.
8557 If there is another way to do this for a specific machine, a
8558 DEFINE_PEEPHOLE should be specified that recognizes the sequence
8561 code
= optab_handler (add_optab
, GET_MODE (out
));
8563 if (CONSTANT_P (op1
) || MEM_P (op1
) || GET_CODE (op1
) == SUBREG
8565 && REGNO (op1
) >= FIRST_PSEUDO_REGISTER
)
8566 || (code
!= CODE_FOR_nothing
8567 && !insn_operand_matches (code
, 2, op1
)))
8568 tem
= op0
, op0
= op1
, op1
= tem
;
8570 gen_reload (out
, op0
, opnum
, type
);
8572 /* If OP0 and OP1 are the same, we can use OUT for OP1.
8573 This fixes a problem on the 32K where the stack pointer cannot
8574 be used as an operand of an add insn. */
8576 if (rtx_equal_p (op0
, op1
))
8579 insn
= emit_insn_if_valid_for_reload (gen_add2_insn (out
, op1
));
8582 /* Add a REG_EQUIV note so that find_equiv_reg can find it. */
8583 set_dst_reg_note (insn
, REG_EQUIV
, in
, out
);
8587 /* If that failed, copy the address register to the reload register.
8588 Then add the constant to the reload register. */
8590 gcc_assert (!reg_overlap_mentioned_p (out
, op0
));
8591 gen_reload (out
, op1
, opnum
, type
);
8592 insn
= emit_insn (gen_add2_insn (out
, op0
));
8593 set_dst_reg_note (insn
, REG_EQUIV
, in
, out
);
8596 /* If we need a memory location to do the move, do it that way. */
8597 else if ((tem1
= replaced_subreg (in
), tem2
= replaced_subreg (out
),
8598 (REG_P (tem1
) && REG_P (tem2
)))
8599 && REGNO (tem1
) < FIRST_PSEUDO_REGISTER
8600 && REGNO (tem2
) < FIRST_PSEUDO_REGISTER
8601 && targetm
.secondary_memory_needed (GET_MODE (out
),
8602 REGNO_REG_CLASS (REGNO (tem1
)),
8603 REGNO_REG_CLASS (REGNO (tem2
))))
8605 /* Get the memory to use and rewrite both registers to its mode. */
8606 rtx loc
= get_secondary_mem (in
, GET_MODE (out
), opnum
, type
);
8608 if (GET_MODE (loc
) != GET_MODE (out
))
8609 out
= gen_rtx_REG (GET_MODE (loc
), reg_or_subregno (out
));
8611 if (GET_MODE (loc
) != GET_MODE (in
))
8612 in
= gen_rtx_REG (GET_MODE (loc
), reg_or_subregno (in
));
8614 gen_reload (loc
, in
, opnum
, type
);
8615 gen_reload (out
, loc
, opnum
, type
);
8617 else if (REG_P (out
) && UNARY_P (in
))
8623 op1
= find_replacement (&XEXP (in
, 0));
8624 if (op1
!= XEXP (in
, 0))
8625 in
= gen_rtx_fmt_e (GET_CODE (in
), GET_MODE (in
), op1
);
8627 /* First, try a plain SET. */
8628 set
= emit_insn_if_valid_for_reload (gen_rtx_SET (out
, in
));
8632 /* If that failed, move the inner operand to the reload
8633 register, and try the same unop with the inner expression
8634 replaced with the reload register. */
8636 if (GET_MODE (op1
) != GET_MODE (out
))
8637 out_moded
= gen_rtx_REG (GET_MODE (op1
), REGNO (out
));
8641 gen_reload (out_moded
, op1
, opnum
, type
);
8643 rtx temp
= gen_rtx_SET (out
, gen_rtx_fmt_e (GET_CODE (in
), GET_MODE (in
),
8645 rtx_insn
*insn
= emit_insn_if_valid_for_reload (temp
);
8648 set_unique_reg_note (insn
, REG_EQUIV
, in
);
8652 fatal_insn ("failure trying to reload:", set
);
8654 /* If IN is a simple operand, use gen_move_insn. */
8655 else if (OBJECT_P (in
) || GET_CODE (in
) == SUBREG
)
8657 tem
= emit_insn (gen_move_insn (out
, in
));
8658 /* IN may contain a LABEL_REF, if so add a REG_LABEL_OPERAND note. */
8659 mark_jump_label (in
, tem
, 0);
8662 else if (targetm
.have_reload_load_address ())
8663 emit_insn (targetm
.gen_reload_load_address (out
, in
));
8665 /* Otherwise, just write (set OUT IN) and hope for the best. */
8667 emit_insn (gen_rtx_SET (out
, in
));
8669 /* Return the first insn emitted.
8670 We cannot just return get_last_insn, because there may have
8671 been multiple instructions emitted. Also note that gen_move_insn may
8672 emit more than one insn itself, so we cannot assume that there is one
8673 insn emitted per emit_insn_before call. */
8675 return last
? NEXT_INSN (last
) : get_insns ();
8678 /* Delete a previously made output-reload whose result we now believe
8679 is not needed. First we double-check.
8681 INSN is the insn now being processed.
8682 LAST_RELOAD_REG is the hard register number for which we want to delete
8683 the last output reload.
8684 J is the reload-number that originally used REG. The caller has made
8685 certain that reload J doesn't use REG any longer for input.
8686 NEW_RELOAD_REG is reload register that reload J is using for REG. */
8689 delete_output_reload (rtx_insn
*insn
, int j
, int last_reload_reg
,
8692 rtx_insn
*output_reload_insn
= spill_reg_store
[last_reload_reg
];
8693 rtx reg
= spill_reg_stored_to
[last_reload_reg
];
8696 int n_inherited
= 0;
8701 /* It is possible that this reload has been only used to set another reload
8702 we eliminated earlier and thus deleted this instruction too. */
8703 if (output_reload_insn
->deleted ())
8706 /* Get the raw pseudo-register referred to. */
8708 while (GET_CODE (reg
) == SUBREG
)
8709 reg
= SUBREG_REG (reg
);
8710 substed
= reg_equiv_memory_loc (REGNO (reg
));
8712 /* This is unsafe if the operand occurs more often in the current
8713 insn than it is inherited. */
8714 for (k
= n_reloads
- 1; k
>= 0; k
--)
8716 rtx reg2
= rld
[k
].in
;
8719 if (MEM_P (reg2
) || reload_override_in
[k
])
8720 reg2
= rld
[k
].in_reg
;
8722 if (AUTO_INC_DEC
&& rld
[k
].out
&& ! rld
[k
].out_reg
)
8723 reg2
= XEXP (rld
[k
].in_reg
, 0);
8725 while (GET_CODE (reg2
) == SUBREG
)
8726 reg2
= SUBREG_REG (reg2
);
8727 if (rtx_equal_p (reg2
, reg
))
8729 if (reload_inherited
[k
] || reload_override_in
[k
] || k
== j
)
8735 n_occurrences
= count_occurrences (PATTERN (insn
), reg
, 0);
8736 if (CALL_P (insn
) && CALL_INSN_FUNCTION_USAGE (insn
))
8737 n_occurrences
+= count_occurrences (CALL_INSN_FUNCTION_USAGE (insn
),
8740 n_occurrences
+= count_occurrences (PATTERN (insn
),
8741 eliminate_regs (substed
, VOIDmode
,
8743 for (rtx i1
= reg_equiv_alt_mem_list (REGNO (reg
)); i1
; i1
= XEXP (i1
, 1))
8745 gcc_assert (!rtx_equal_p (XEXP (i1
, 0), substed
));
8746 n_occurrences
+= count_occurrences (PATTERN (insn
), XEXP (i1
, 0), 0);
8748 if (n_occurrences
> n_inherited
)
8751 regno
= REGNO (reg
);
8752 nregs
= REG_NREGS (reg
);
8754 /* If the pseudo-reg we are reloading is no longer referenced
8755 anywhere between the store into it and here,
8756 and we're within the same basic block, then the value can only
8757 pass through the reload reg and end up here.
8758 Otherwise, give up--return. */
8759 for (rtx_insn
*i1
= NEXT_INSN (output_reload_insn
);
8760 i1
!= insn
; i1
= NEXT_INSN (i1
))
8762 if (NOTE_INSN_BASIC_BLOCK_P (i1
))
8764 if ((NONJUMP_INSN_P (i1
) || CALL_P (i1
))
8765 && refers_to_regno_p (regno
, regno
+ nregs
, PATTERN (i1
), NULL
))
8767 /* If this is USE in front of INSN, we only have to check that
8768 there are no more references than accounted for by inheritance. */
8769 while (NONJUMP_INSN_P (i1
) && GET_CODE (PATTERN (i1
)) == USE
)
8771 n_occurrences
+= rtx_equal_p (reg
, XEXP (PATTERN (i1
), 0)) != 0;
8772 i1
= NEXT_INSN (i1
);
8774 if (n_occurrences
<= n_inherited
&& i1
== insn
)
8780 /* We will be deleting the insn. Remove the spill reg information. */
8781 for (k
= hard_regno_nregs (last_reload_reg
, GET_MODE (reg
)); k
-- > 0; )
8783 spill_reg_store
[last_reload_reg
+ k
] = 0;
8784 spill_reg_stored_to
[last_reload_reg
+ k
] = 0;
8787 /* The caller has already checked that REG dies or is set in INSN.
8788 It has also checked that we are optimizing, and thus some
8789 inaccuracies in the debugging information are acceptable.
8790 So we could just delete output_reload_insn. But in some cases
8791 we can improve the debugging information without sacrificing
8792 optimization - maybe even improving the code: See if the pseudo
8793 reg has been completely replaced with reload regs. If so, delete
8794 the store insn and forget we had a stack slot for the pseudo. */
8795 if (rld
[j
].out
!= rld
[j
].in
8796 && REG_N_DEATHS (REGNO (reg
)) == 1
8797 && REG_N_SETS (REGNO (reg
)) == 1
8798 && REG_BASIC_BLOCK (REGNO (reg
)) >= NUM_FIXED_BLOCKS
8799 && find_regno_note (insn
, REG_DEAD
, REGNO (reg
)))
8803 /* We know that it was used only between here and the beginning of
8804 the current basic block. (We also know that the last use before
8805 INSN was the output reload we are thinking of deleting, but never
8806 mind that.) Search that range; see if any ref remains. */
8807 for (i2
= PREV_INSN (insn
); i2
; i2
= PREV_INSN (i2
))
8809 rtx set
= single_set (i2
);
8811 /* Uses which just store in the pseudo don't count,
8812 since if they are the only uses, they are dead. */
8813 if (set
!= 0 && SET_DEST (set
) == reg
)
8815 if (LABEL_P (i2
) || JUMP_P (i2
))
8817 if ((NONJUMP_INSN_P (i2
) || CALL_P (i2
))
8818 && reg_mentioned_p (reg
, PATTERN (i2
)))
8820 /* Some other ref remains; just delete the output reload we
8822 delete_address_reloads (output_reload_insn
, insn
);
8823 delete_insn (output_reload_insn
);
8828 /* Delete the now-dead stores into this pseudo. Note that this
8829 loop also takes care of deleting output_reload_insn. */
8830 for (i2
= PREV_INSN (insn
); i2
; i2
= PREV_INSN (i2
))
8832 rtx set
= single_set (i2
);
8834 if (set
!= 0 && SET_DEST (set
) == reg
)
8836 delete_address_reloads (i2
, insn
);
8839 if (LABEL_P (i2
) || JUMP_P (i2
))
8843 /* For the debugging info, say the pseudo lives in this reload reg. */
8844 reg_renumber
[REGNO (reg
)] = REGNO (new_reload_reg
);
8845 if (ira_conflicts_p
)
8846 /* Inform IRA about the change. */
8847 ira_mark_allocation_change (REGNO (reg
));
8848 alter_reg (REGNO (reg
), -1, false);
8852 delete_address_reloads (output_reload_insn
, insn
);
8853 delete_insn (output_reload_insn
);
8857 /* We are going to delete DEAD_INSN. Recursively delete loads of
8858 reload registers used in DEAD_INSN that are not used till CURRENT_INSN.
8859 CURRENT_INSN is being reloaded, so we have to check its reloads too. */
8861 delete_address_reloads (rtx_insn
*dead_insn
, rtx_insn
*current_insn
)
8863 rtx set
= single_set (dead_insn
);
8865 rtx_insn
*prev
, *next
;
8868 rtx dst
= SET_DEST (set
);
8870 delete_address_reloads_1 (dead_insn
, XEXP (dst
, 0), current_insn
);
8872 /* If we deleted the store from a reloaded post_{in,de}c expression,
8873 we can delete the matching adds. */
8874 prev
= PREV_INSN (dead_insn
);
8875 next
= NEXT_INSN (dead_insn
);
8876 if (! prev
|| ! next
)
8878 set
= single_set (next
);
8879 set2
= single_set (prev
);
8881 || GET_CODE (SET_SRC (set
)) != PLUS
|| GET_CODE (SET_SRC (set2
)) != PLUS
8882 || !CONST_INT_P (XEXP (SET_SRC (set
), 1))
8883 || !CONST_INT_P (XEXP (SET_SRC (set2
), 1)))
8885 dst
= SET_DEST (set
);
8886 if (! rtx_equal_p (dst
, SET_DEST (set2
))
8887 || ! rtx_equal_p (dst
, XEXP (SET_SRC (set
), 0))
8888 || ! rtx_equal_p (dst
, XEXP (SET_SRC (set2
), 0))
8889 || (INTVAL (XEXP (SET_SRC (set
), 1))
8890 != -INTVAL (XEXP (SET_SRC (set2
), 1))))
8892 delete_related_insns (prev
);
8893 delete_related_insns (next
);
8896 /* Subfunction of delete_address_reloads: process registers found in X. */
8898 delete_address_reloads_1 (rtx_insn
*dead_insn
, rtx x
, rtx_insn
*current_insn
)
8900 rtx_insn
*prev
, *i2
;
8903 enum rtx_code code
= GET_CODE (x
);
8907 const char *fmt
= GET_RTX_FORMAT (code
);
8908 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
8911 delete_address_reloads_1 (dead_insn
, XEXP (x
, i
), current_insn
);
8912 else if (fmt
[i
] == 'E')
8914 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
8915 delete_address_reloads_1 (dead_insn
, XVECEXP (x
, i
, j
),
8922 if (spill_reg_order
[REGNO (x
)] < 0)
8925 /* Scan backwards for the insn that sets x. This might be a way back due
8927 for (prev
= PREV_INSN (dead_insn
); prev
; prev
= PREV_INSN (prev
))
8929 code
= GET_CODE (prev
);
8930 if (code
== CODE_LABEL
|| code
== JUMP_INSN
)
8934 if (reg_set_p (x
, PATTERN (prev
)))
8936 if (reg_referenced_p (x
, PATTERN (prev
)))
8939 if (! prev
|| INSN_UID (prev
) < reload_first_uid
)
8941 /* Check that PREV only sets the reload register. */
8942 set
= single_set (prev
);
8945 dst
= SET_DEST (set
);
8947 || ! rtx_equal_p (dst
, x
))
8949 if (! reg_set_p (dst
, PATTERN (dead_insn
)))
8951 /* Check if DST was used in a later insn -
8952 it might have been inherited. */
8953 for (i2
= NEXT_INSN (dead_insn
); i2
; i2
= NEXT_INSN (i2
))
8959 if (reg_referenced_p (dst
, PATTERN (i2
)))
8961 /* If there is a reference to the register in the current insn,
8962 it might be loaded in a non-inherited reload. If no other
8963 reload uses it, that means the register is set before
8965 if (i2
== current_insn
)
8967 for (j
= n_reloads
- 1; j
>= 0; j
--)
8968 if ((rld
[j
].reg_rtx
== dst
&& reload_inherited
[j
])
8969 || reload_override_in
[j
] == dst
)
8971 for (j
= n_reloads
- 1; j
>= 0; j
--)
8972 if (rld
[j
].in
&& rld
[j
].reg_rtx
== dst
)
8981 /* If DST is still live at CURRENT_INSN, check if it is used for
8982 any reload. Note that even if CURRENT_INSN sets DST, we still
8983 have to check the reloads. */
8984 if (i2
== current_insn
)
8986 for (j
= n_reloads
- 1; j
>= 0; j
--)
8987 if ((rld
[j
].reg_rtx
== dst
&& reload_inherited
[j
])
8988 || reload_override_in
[j
] == dst
)
8990 /* ??? We can't finish the loop here, because dst might be
8991 allocated to a pseudo in this block if no reload in this
8992 block needs any of the classes containing DST - see
8993 spill_hard_reg. There is no easy way to tell this, so we
8994 have to scan till the end of the basic block. */
8996 if (reg_set_p (dst
, PATTERN (i2
)))
9000 delete_address_reloads_1 (prev
, SET_SRC (set
), current_insn
);
9001 reg_reloaded_contents
[REGNO (dst
)] = -1;
9005 /* Output reload-insns to reload VALUE into RELOADREG.
9006 VALUE is an autoincrement or autodecrement RTX whose operand
9007 is a register or memory location;
9008 so reloading involves incrementing that location.
9009 IN is either identical to VALUE, or some cheaper place to reload from.
9011 INC_AMOUNT is the number to increment or decrement by (always positive).
9012 This cannot be deduced from VALUE. */
9015 inc_for_reload (rtx reloadreg
, rtx in
, rtx value
, poly_int64 inc_amount
)
9017 /* REG or MEM to be copied and incremented. */
9018 rtx incloc
= find_replacement (&XEXP (value
, 0));
9019 /* Nonzero if increment after copying. */
9020 int post
= (GET_CODE (value
) == POST_DEC
|| GET_CODE (value
) == POST_INC
9021 || GET_CODE (value
) == POST_MODIFY
);
9026 rtx real_in
= in
== value
? incloc
: in
;
9028 /* No hard register is equivalent to this register after
9029 inc/dec operation. If REG_LAST_RELOAD_REG were nonzero,
9030 we could inc/dec that register as well (maybe even using it for
9031 the source), but I'm not sure it's worth worrying about. */
9033 reg_last_reload_reg
[REGNO (incloc
)] = 0;
9035 if (GET_CODE (value
) == PRE_MODIFY
|| GET_CODE (value
) == POST_MODIFY
)
9037 gcc_assert (GET_CODE (XEXP (value
, 1)) == PLUS
);
9038 inc
= find_replacement (&XEXP (XEXP (value
, 1), 1));
9042 if (GET_CODE (value
) == PRE_DEC
|| GET_CODE (value
) == POST_DEC
)
9043 inc_amount
= -inc_amount
;
9045 inc
= gen_int_mode (inc_amount
, Pmode
);
9048 /* If this is post-increment, first copy the location to the reload reg. */
9049 if (post
&& real_in
!= reloadreg
)
9050 emit_insn (gen_move_insn (reloadreg
, real_in
));
9054 /* See if we can directly increment INCLOC. Use a method similar to
9055 that in gen_reload. */
9057 last
= get_last_insn ();
9058 add_insn
= emit_insn (gen_rtx_SET (incloc
,
9059 gen_rtx_PLUS (GET_MODE (incloc
),
9062 code
= recog_memoized (add_insn
);
9065 extract_insn (add_insn
);
9066 if (constrain_operands (1, get_enabled_alternatives (add_insn
)))
9068 /* If this is a pre-increment and we have incremented the value
9069 where it lives, copy the incremented value to RELOADREG to
9070 be used as an address. */
9073 emit_insn (gen_move_insn (reloadreg
, incloc
));
9077 delete_insns_since (last
);
9080 /* If couldn't do the increment directly, must increment in RELOADREG.
9081 The way we do this depends on whether this is pre- or post-increment.
9082 For pre-increment, copy INCLOC to the reload register, increment it
9083 there, then save back. */
9087 if (in
!= reloadreg
)
9088 emit_insn (gen_move_insn (reloadreg
, real_in
));
9089 emit_insn (gen_add2_insn (reloadreg
, inc
));
9090 emit_insn (gen_move_insn (incloc
, reloadreg
));
9095 Because this might be a jump insn or a compare, and because RELOADREG
9096 may not be available after the insn in an input reload, we must do
9097 the incrementation before the insn being reloaded for.
9099 We have already copied IN to RELOADREG. Increment the copy in
9100 RELOADREG, save that back, then decrement RELOADREG so it has
9101 the original value. */
9103 emit_insn (gen_add2_insn (reloadreg
, inc
));
9104 emit_insn (gen_move_insn (incloc
, reloadreg
));
9105 if (CONST_INT_P (inc
))
9106 emit_insn (gen_add2_insn (reloadreg
,
9107 gen_int_mode (-INTVAL (inc
),
9108 GET_MODE (reloadreg
))));
9110 emit_insn (gen_sub2_insn (reloadreg
, inc
));
9115 add_auto_inc_notes (rtx_insn
*insn
, rtx x
)
9117 enum rtx_code code
= GET_CODE (x
);
9121 if (code
== MEM
&& auto_inc_p (XEXP (x
, 0)))
9123 add_reg_note (insn
, REG_INC
, XEXP (XEXP (x
, 0), 0));
9127 /* Scan all the operand sub-expressions. */
9128 fmt
= GET_RTX_FORMAT (code
);
9129 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
9132 add_auto_inc_notes (insn
, XEXP (x
, i
));
9133 else if (fmt
[i
] == 'E')
9134 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
9135 add_auto_inc_notes (insn
, XVECEXP (x
, i
, j
));