1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987-2014 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify it under
7 the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 3, or (at your option) any later
11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
22 #include "coretypes.h"
26 #include "hard-reg-set.h"
27 #include "rtl-error.h"
30 #include "insn-config.h"
37 #include "addresses.h"
38 #include "basic-block.h"
49 /* This file contains the reload pass of the compiler, which is
50 run after register allocation has been done. It checks that
51 each insn is valid (operands required to be in registers really
52 are in registers of the proper class) and fixes up invalid ones
53 by copying values temporarily into registers for the insns
56 The results of register allocation are described by the vector
57 reg_renumber; the insns still contain pseudo regs, but reg_renumber
58 can be used to find which hard reg, if any, a pseudo reg is in.
60 The technique we always use is to free up a few hard regs that are
61 called ``reload regs'', and for each place where a pseudo reg
62 must be in a hard reg, copy it temporarily into one of the reload regs.
64 Reload regs are allocated locally for every instruction that needs
65 reloads. When there are pseudos which are allocated to a register that
66 has been chosen as a reload reg, such pseudos must be ``spilled''.
67 This means that they go to other hard regs, or to stack slots if no other
68 available hard regs can be found. Spilling can invalidate more
69 insns, requiring additional need for reloads, so we must keep checking
70 until the process stabilizes.
72 For machines with different classes of registers, we must keep track
73 of the register class needed for each reload, and make sure that
74 we allocate enough reload registers of each class.
76 The file reload.c contains the code that checks one insn for
77 validity and reports the reloads that it needs. This file
78 is in charge of scanning the entire rtl code, accumulating the
79 reload needs, spilling, assigning reload registers to use for
80 fixing up each insn, and generating the new insns to copy values
81 into the reload registers. */
83 struct target_reload default_target_reload
;
85 struct target_reload
*this_target_reload
= &default_target_reload
;
88 #define spill_indirect_levels \
89 (this_target_reload->x_spill_indirect_levels)
91 /* During reload_as_needed, element N contains a REG rtx for the hard reg
92 into which reg N has been reloaded (perhaps for a previous insn). */
93 static rtx
*reg_last_reload_reg
;
95 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
96 for an output reload that stores into reg N. */
97 static regset_head reg_has_output_reload
;
99 /* Indicates which hard regs are reload-registers for an output reload
100 in the current insn. */
101 static HARD_REG_SET reg_is_output_reload
;
103 /* Widest width in which each pseudo reg is referred to (via subreg). */
104 static unsigned int *reg_max_ref_width
;
106 /* Vector to remember old contents of reg_renumber before spilling. */
107 static short *reg_old_renumber
;
109 /* During reload_as_needed, element N contains the last pseudo regno reloaded
110 into hard register N. If that pseudo reg occupied more than one register,
111 reg_reloaded_contents points to that pseudo for each spill register in
112 use; all of these must remain set for an inheritance to occur. */
113 static int reg_reloaded_contents
[FIRST_PSEUDO_REGISTER
];
115 /* During reload_as_needed, element N contains the insn for which
116 hard register N was last used. Its contents are significant only
117 when reg_reloaded_valid is set for this register. */
118 static rtx reg_reloaded_insn
[FIRST_PSEUDO_REGISTER
];
120 /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid. */
121 static HARD_REG_SET reg_reloaded_valid
;
122 /* Indicate if the register was dead at the end of the reload.
123 This is only valid if reg_reloaded_contents is set and valid. */
124 static HARD_REG_SET reg_reloaded_dead
;
126 /* Indicate whether the register's current value is one that is not
127 safe to retain across a call, even for registers that are normally
128 call-saved. This is only meaningful for members of reg_reloaded_valid. */
129 static HARD_REG_SET reg_reloaded_call_part_clobbered
;
131 /* Number of spill-regs so far; number of valid elements of spill_regs. */
134 /* In parallel with spill_regs, contains REG rtx's for those regs.
135 Holds the last rtx used for any given reg, or 0 if it has never
136 been used for spilling yet. This rtx is reused, provided it has
138 static rtx spill_reg_rtx
[FIRST_PSEUDO_REGISTER
];
140 /* In parallel with spill_regs, contains nonzero for a spill reg
141 that was stored after the last time it was used.
142 The precise value is the insn generated to do the store. */
143 static rtx spill_reg_store
[FIRST_PSEUDO_REGISTER
];
145 /* This is the register that was stored with spill_reg_store. This is a
146 copy of reload_out / reload_out_reg when the value was stored; if
147 reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */
148 static rtx spill_reg_stored_to
[FIRST_PSEUDO_REGISTER
];
150 /* This table is the inverse mapping of spill_regs:
151 indexed by hard reg number,
152 it contains the position of that reg in spill_regs,
153 or -1 for something that is not in spill_regs.
155 ?!? This is no longer accurate. */
156 static short spill_reg_order
[FIRST_PSEUDO_REGISTER
];
158 /* This reg set indicates registers that can't be used as spill registers for
159 the currently processed insn. These are the hard registers which are live
160 during the insn, but not allocated to pseudos, as well as fixed
162 static HARD_REG_SET bad_spill_regs
;
164 /* These are the hard registers that can't be used as spill register for any
165 insn. This includes registers used for user variables and registers that
166 we can't eliminate. A register that appears in this set also can't be used
167 to retry register allocation. */
168 static HARD_REG_SET bad_spill_regs_global
;
170 /* Describes order of use of registers for reloading
171 of spilled pseudo-registers. `n_spills' is the number of
172 elements that are actually valid; new ones are added at the end.
174 Both spill_regs and spill_reg_order are used on two occasions:
175 once during find_reload_regs, where they keep track of the spill registers
176 for a single insn, but also during reload_as_needed where they show all
177 the registers ever used by reload. For the latter case, the information
178 is calculated during finish_spills. */
179 static short spill_regs
[FIRST_PSEUDO_REGISTER
];
181 /* This vector of reg sets indicates, for each pseudo, which hard registers
182 may not be used for retrying global allocation because the register was
183 formerly spilled from one of them. If we allowed reallocating a pseudo to
184 a register that it was already allocated to, reload might not
186 static HARD_REG_SET
*pseudo_previous_regs
;
188 /* This vector of reg sets indicates, for each pseudo, which hard
189 registers may not be used for retrying global allocation because they
190 are used as spill registers during one of the insns in which the
192 static HARD_REG_SET
*pseudo_forbidden_regs
;
194 /* All hard regs that have been used as spill registers for any insn are
195 marked in this set. */
196 static HARD_REG_SET used_spill_regs
;
198 /* Index of last register assigned as a spill register. We allocate in
199 a round-robin fashion. */
200 static int last_spill_reg
;
202 /* Record the stack slot for each spilled hard register. */
203 static rtx spill_stack_slot
[FIRST_PSEUDO_REGISTER
];
205 /* Width allocated so far for that stack slot. */
206 static unsigned int spill_stack_slot_width
[FIRST_PSEUDO_REGISTER
];
208 /* Record which pseudos needed to be spilled. */
209 static regset_head spilled_pseudos
;
211 /* Record which pseudos changed their allocation in finish_spills. */
212 static regset_head changed_allocation_pseudos
;
214 /* Used for communication between order_regs_for_reload and count_pseudo.
215 Used to avoid counting one pseudo twice. */
216 static regset_head pseudos_counted
;
218 /* First uid used by insns created by reload in this function.
219 Used in find_equiv_reg. */
220 int reload_first_uid
;
222 /* Flag set by local-alloc or global-alloc if anything is live in
223 a call-clobbered reg across calls. */
224 int caller_save_needed
;
226 /* Set to 1 while reload_as_needed is operating.
227 Required by some machines to handle any generated moves differently. */
228 int reload_in_progress
= 0;
230 /* This obstack is used for allocation of rtl during register elimination.
231 The allocated storage can be freed once find_reloads has processed the
233 static struct obstack reload_obstack
;
235 /* Points to the beginning of the reload_obstack. All insn_chain structures
236 are allocated first. */
237 static char *reload_startobj
;
239 /* The point after all insn_chain structures. Used to quickly deallocate
240 memory allocated in copy_reloads during calculate_needs_all_insns. */
241 static char *reload_firstobj
;
243 /* This points before all local rtl generated by register elimination.
244 Used to quickly free all memory after processing one insn. */
245 static char *reload_insn_firstobj
;
247 /* List of insn_chain instructions, one for every insn that reload needs to
249 struct insn_chain
*reload_insn_chain
;
251 /* TRUE if we potentially left dead insns in the insn stream and want to
252 run DCE immediately after reload, FALSE otherwise. */
253 static bool need_dce
;
255 /* List of all insns needing reloads. */
256 static struct insn_chain
*insns_need_reload
;
258 /* This structure is used to record information about register eliminations.
259 Each array entry describes one possible way of eliminating a register
260 in favor of another. If there is more than one way of eliminating a
261 particular register, the most preferred should be specified first. */
265 int from
; /* Register number to be eliminated. */
266 int to
; /* Register number used as replacement. */
267 HOST_WIDE_INT initial_offset
; /* Initial difference between values. */
268 int can_eliminate
; /* Nonzero if this elimination can be done. */
269 int can_eliminate_previous
; /* Value returned by TARGET_CAN_ELIMINATE
270 target hook in previous scan over insns
272 HOST_WIDE_INT offset
; /* Current offset between the two regs. */
273 HOST_WIDE_INT previous_offset
;/* Offset at end of previous insn. */
274 int ref_outside_mem
; /* "to" has been referenced outside a MEM. */
275 rtx from_rtx
; /* REG rtx for the register to be eliminated.
276 We cannot simply compare the number since
277 we might then spuriously replace a hard
278 register corresponding to a pseudo
279 assigned to the reg to be eliminated. */
280 rtx to_rtx
; /* REG rtx for the replacement. */
283 static struct elim_table
*reg_eliminate
= 0;
285 /* This is an intermediate structure to initialize the table. It has
286 exactly the members provided by ELIMINABLE_REGS. */
287 static const struct elim_table_1
291 } reg_eliminate_1
[] =
293 /* If a set of eliminable registers was specified, define the table from it.
294 Otherwise, default to the normal case of the frame pointer being
295 replaced by the stack pointer. */
297 #ifdef ELIMINABLE_REGS
300 {{ FRAME_POINTER_REGNUM
, STACK_POINTER_REGNUM
}};
303 #define NUM_ELIMINABLE_REGS ARRAY_SIZE (reg_eliminate_1)
305 /* Record the number of pending eliminations that have an offset not equal
306 to their initial offset. If nonzero, we use a new copy of each
307 replacement result in any insns encountered. */
308 int num_not_at_initial_offset
;
310 /* Count the number of registers that we may be able to eliminate. */
311 static int num_eliminable
;
312 /* And the number of registers that are equivalent to a constant that
313 can be eliminated to frame_pointer / arg_pointer + constant. */
314 static int num_eliminable_invariants
;
316 /* For each label, we record the offset of each elimination. If we reach
317 a label by more than one path and an offset differs, we cannot do the
318 elimination. This information is indexed by the difference of the
319 number of the label and the first label number. We can't offset the
320 pointer itself as this can cause problems on machines with segmented
321 memory. The first table is an array of flags that records whether we
322 have yet encountered a label and the second table is an array of arrays,
323 one entry in the latter array for each elimination. */
325 static int first_label_num
;
326 static char *offsets_known_at
;
327 static HOST_WIDE_INT (*offsets_at
)[NUM_ELIMINABLE_REGS
];
329 vec
<reg_equivs_t
, va_gc
> *reg_equivs
;
331 /* Stack of addresses where an rtx has been changed. We can undo the
332 changes by popping items off the stack and restoring the original
333 value at each location.
335 We use this simplistic undo capability rather than copy_rtx as copy_rtx
336 will not make a deep copy of a normally sharable rtx, such as
337 (const (plus (symbol_ref) (const_int))). If such an expression appears
338 as R1 in gen_reload_chain_without_interm_reg_p, then a shared
339 rtx expression would be changed. See PR 42431. */
342 static vec
<rtx_p
> substitute_stack
;
344 /* Number of labels in the current function. */
346 static int num_labels
;
348 static void replace_pseudos_in (rtx
*, enum machine_mode
, rtx
);
349 static void maybe_fix_stack_asms (void);
350 static void copy_reloads (struct insn_chain
*);
351 static void calculate_needs_all_insns (int);
352 static int find_reg (struct insn_chain
*, int);
353 static void find_reload_regs (struct insn_chain
*);
354 static void select_reload_regs (void);
355 static void delete_caller_save_insns (void);
357 static void spill_failure (rtx
, enum reg_class
);
358 static void count_spilled_pseudo (int, int, int);
359 static void delete_dead_insn (rtx
);
360 static void alter_reg (int, int, bool);
361 static void set_label_offsets (rtx
, rtx
, int);
362 static void check_eliminable_occurrences (rtx
);
363 static void elimination_effects (rtx
, enum machine_mode
);
364 static rtx
eliminate_regs_1 (rtx
, enum machine_mode
, rtx
, bool, bool);
365 static int eliminate_regs_in_insn (rtx
, int);
366 static void update_eliminable_offsets (void);
367 static void mark_not_eliminable (rtx
, const_rtx
, void *);
368 static void set_initial_elim_offsets (void);
369 static bool verify_initial_elim_offsets (void);
370 static void set_initial_label_offsets (void);
371 static void set_offsets_for_label (rtx
);
372 static void init_eliminable_invariants (rtx
, bool);
373 static void init_elim_table (void);
374 static void free_reg_equiv (void);
375 static void update_eliminables (HARD_REG_SET
*);
376 static bool update_eliminables_and_spill (void);
377 static void elimination_costs_in_insn (rtx
);
378 static void spill_hard_reg (unsigned int, int);
379 static int finish_spills (int);
380 static void scan_paradoxical_subregs (rtx
);
381 static void count_pseudo (int);
382 static void order_regs_for_reload (struct insn_chain
*);
383 static void reload_as_needed (int);
384 static void forget_old_reloads_1 (rtx
, const_rtx
, void *);
385 static void forget_marked_reloads (regset
);
386 static int reload_reg_class_lower (const void *, const void *);
387 static void mark_reload_reg_in_use (unsigned int, int, enum reload_type
,
389 static void clear_reload_reg_in_use (unsigned int, int, enum reload_type
,
391 static int reload_reg_free_p (unsigned int, int, enum reload_type
);
392 static int reload_reg_free_for_value_p (int, int, int, enum reload_type
,
394 static int free_for_value_p (int, enum machine_mode
, int, enum reload_type
,
396 static int allocate_reload_reg (struct insn_chain
*, int, int);
397 static int conflicts_with_override (rtx
);
398 static void failed_reload (rtx
, int);
399 static int set_reload_reg (int, int);
400 static void choose_reload_regs_init (struct insn_chain
*, rtx
*);
401 static void choose_reload_regs (struct insn_chain
*);
402 static void emit_input_reload_insns (struct insn_chain
*, struct reload
*,
404 static void emit_output_reload_insns (struct insn_chain
*, struct reload
*,
406 static void do_input_reload (struct insn_chain
*, struct reload
*, int);
407 static void do_output_reload (struct insn_chain
*, struct reload
*, int);
408 static void emit_reload_insns (struct insn_chain
*);
409 static void delete_output_reload (rtx
, int, int, rtx
);
410 static void delete_address_reloads (rtx
, rtx
);
411 static void delete_address_reloads_1 (rtx
, rtx
, rtx
);
412 static void inc_for_reload (rtx
, rtx
, rtx
, int);
414 static void add_auto_inc_notes (rtx
, rtx
);
416 static void substitute (rtx
*, const_rtx
, rtx
);
417 static bool gen_reload_chain_without_interm_reg_p (int, int);
418 static int reloads_conflict (int, int);
419 static rtx
gen_reload (rtx
, rtx
, int, enum reload_type
);
420 static rtx
emit_insn_if_valid_for_reload (rtx
);
422 /* Initialize the reload pass. This is called at the beginning of compilation
423 and may be called again if the target is reinitialized. */
430 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
431 Set spill_indirect_levels to the number of levels such addressing is
432 permitted, zero if it is not permitted at all. */
435 = gen_rtx_MEM (Pmode
,
438 LAST_VIRTUAL_REGISTER
+ 1),
439 gen_int_mode (4, Pmode
)));
440 spill_indirect_levels
= 0;
442 while (memory_address_p (QImode
, tem
))
444 spill_indirect_levels
++;
445 tem
= gen_rtx_MEM (Pmode
, tem
);
448 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
450 tem
= gen_rtx_MEM (Pmode
, gen_rtx_SYMBOL_REF (Pmode
, "foo"));
451 indirect_symref_ok
= memory_address_p (QImode
, tem
);
453 /* See if reg+reg is a valid (and offsettable) address. */
455 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
457 tem
= gen_rtx_PLUS (Pmode
,
458 gen_rtx_REG (Pmode
, HARD_FRAME_POINTER_REGNUM
),
459 gen_rtx_REG (Pmode
, i
));
461 /* This way, we make sure that reg+reg is an offsettable address. */
462 tem
= plus_constant (Pmode
, tem
, 4);
464 if (memory_address_p (QImode
, tem
))
466 double_reg_address_ok
= 1;
471 /* Initialize obstack for our rtl allocation. */
472 if (reload_startobj
== NULL
)
474 gcc_obstack_init (&reload_obstack
);
475 reload_startobj
= XOBNEWVAR (&reload_obstack
, char, 0);
478 INIT_REG_SET (&spilled_pseudos
);
479 INIT_REG_SET (&changed_allocation_pseudos
);
480 INIT_REG_SET (&pseudos_counted
);
483 /* List of insn chains that are currently unused. */
484 static struct insn_chain
*unused_insn_chains
= 0;
486 /* Allocate an empty insn_chain structure. */
488 new_insn_chain (void)
490 struct insn_chain
*c
;
492 if (unused_insn_chains
== 0)
494 c
= XOBNEW (&reload_obstack
, struct insn_chain
);
495 INIT_REG_SET (&c
->live_throughout
);
496 INIT_REG_SET (&c
->dead_or_set
);
500 c
= unused_insn_chains
;
501 unused_insn_chains
= c
->next
;
503 c
->is_caller_save_insn
= 0;
504 c
->need_operand_change
= 0;
510 /* Small utility function to set all regs in hard reg set TO which are
511 allocated to pseudos in regset FROM. */
514 compute_use_by_pseudos (HARD_REG_SET
*to
, regset from
)
517 reg_set_iterator rsi
;
519 EXECUTE_IF_SET_IN_REG_SET (from
, FIRST_PSEUDO_REGISTER
, regno
, rsi
)
521 int r
= reg_renumber
[regno
];
525 /* reload_combine uses the information from DF_LIVE_IN,
526 which might still contain registers that have not
527 actually been allocated since they have an
529 gcc_assert (ira_conflicts_p
|| reload_completed
);
532 add_to_hard_reg_set (to
, PSEUDO_REGNO_MODE (regno
), r
);
536 /* Replace all pseudos found in LOC with their corresponding
540 replace_pseudos_in (rtx
*loc
, enum machine_mode mem_mode
, rtx usage
)
553 unsigned int regno
= REGNO (x
);
555 if (regno
< FIRST_PSEUDO_REGISTER
)
558 x
= eliminate_regs_1 (x
, mem_mode
, usage
, true, false);
562 replace_pseudos_in (loc
, mem_mode
, usage
);
566 if (reg_equiv_constant (regno
))
567 *loc
= reg_equiv_constant (regno
);
568 else if (reg_equiv_invariant (regno
))
569 *loc
= reg_equiv_invariant (regno
);
570 else if (reg_equiv_mem (regno
))
571 *loc
= reg_equiv_mem (regno
);
572 else if (reg_equiv_address (regno
))
573 *loc
= gen_rtx_MEM (GET_MODE (x
), reg_equiv_address (regno
));
576 gcc_assert (!REG_P (regno_reg_rtx
[regno
])
577 || REGNO (regno_reg_rtx
[regno
]) != regno
);
578 *loc
= regno_reg_rtx
[regno
];
583 else if (code
== MEM
)
585 replace_pseudos_in (& XEXP (x
, 0), GET_MODE (x
), usage
);
589 /* Process each of our operands recursively. */
590 fmt
= GET_RTX_FORMAT (code
);
591 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++, fmt
++)
593 replace_pseudos_in (&XEXP (x
, i
), mem_mode
, usage
);
594 else if (*fmt
== 'E')
595 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
596 replace_pseudos_in (& XVECEXP (x
, i
, j
), mem_mode
, usage
);
599 /* Determine if the current function has an exception receiver block
600 that reaches the exit block via non-exceptional edges */
603 has_nonexceptional_receiver (void)
607 basic_block
*tos
, *worklist
, bb
;
609 /* If we're not optimizing, then just err on the safe side. */
613 /* First determine which blocks can reach exit via normal paths. */
614 tos
= worklist
= XNEWVEC (basic_block
, n_basic_blocks_for_fn (cfun
) + 1);
616 FOR_EACH_BB_FN (bb
, cfun
)
617 bb
->flags
&= ~BB_REACHABLE
;
619 /* Place the exit block on our worklist. */
620 EXIT_BLOCK_PTR_FOR_FN (cfun
)->flags
|= BB_REACHABLE
;
621 *tos
++ = EXIT_BLOCK_PTR_FOR_FN (cfun
);
623 /* Iterate: find everything reachable from what we've already seen. */
624 while (tos
!= worklist
)
628 FOR_EACH_EDGE (e
, ei
, bb
->preds
)
629 if (!(e
->flags
& EDGE_ABNORMAL
))
631 basic_block src
= e
->src
;
633 if (!(src
->flags
& BB_REACHABLE
))
635 src
->flags
|= BB_REACHABLE
;
642 /* Now see if there's a reachable block with an exceptional incoming
644 FOR_EACH_BB_FN (bb
, cfun
)
645 if (bb
->flags
& BB_REACHABLE
&& bb_has_abnormal_pred (bb
))
648 /* No exceptional block reached exit unexceptionally. */
652 /* Grow (or allocate) the REG_EQUIVS array from its current size (which may be
653 zero elements) to MAX_REG_NUM elements.
655 Initialize all new fields to NULL and update REG_EQUIVS_SIZE. */
657 grow_reg_equivs (void)
659 int old_size
= vec_safe_length (reg_equivs
);
660 int max_regno
= max_reg_num ();
664 memset (&ze
, 0, sizeof (reg_equivs_t
));
665 vec_safe_reserve (reg_equivs
, max_regno
);
666 for (i
= old_size
; i
< max_regno
; i
++)
667 reg_equivs
->quick_insert (i
, ze
);
671 /* Global variables used by reload and its subroutines. */
673 /* The current basic block while in calculate_elim_costs_all_insns. */
674 static basic_block elim_bb
;
676 /* Set during calculate_needs if an insn needs register elimination. */
677 static int something_needs_elimination
;
678 /* Set during calculate_needs if an insn needs an operand changed. */
679 static int something_needs_operands_changed
;
680 /* Set by alter_regs if we spilled a register to the stack. */
681 static bool something_was_spilled
;
683 /* Nonzero means we couldn't get enough spill regs. */
686 /* Temporary array of pseudo-register number. */
687 static int *temp_pseudo_reg_arr
;
689 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
690 If that insn didn't set the register (i.e., it copied the register to
691 memory), just delete that insn instead of the equivalencing insn plus
692 anything now dead. If we call delete_dead_insn on that insn, we may
693 delete the insn that actually sets the register if the register dies
694 there and that is incorrect. */
698 for (int i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
700 if (reg_renumber
[i
] < 0 && reg_equiv_init (i
) != 0)
703 for (list
= reg_equiv_init (i
); list
; list
= XEXP (list
, 1))
705 rtx equiv_insn
= XEXP (list
, 0);
707 /* If we already deleted the insn or if it may trap, we can't
708 delete it. The latter case shouldn't happen, but can
709 if an insn has a variable address, gets a REG_EH_REGION
710 note added to it, and then gets converted into a load
711 from a constant address. */
712 if (NOTE_P (equiv_insn
)
713 || can_throw_internal (equiv_insn
))
715 else if (reg_set_p (regno_reg_rtx
[i
], PATTERN (equiv_insn
)))
716 delete_dead_insn (equiv_insn
);
718 SET_INSN_DELETED (equiv_insn
);
724 /* Return true if remove_init_insns will delete INSN. */
726 will_delete_init_insn_p (rtx insn
)
728 rtx set
= single_set (insn
);
729 if (!set
|| !REG_P (SET_DEST (set
)))
731 unsigned regno
= REGNO (SET_DEST (set
));
733 if (can_throw_internal (insn
))
736 if (regno
< FIRST_PSEUDO_REGISTER
|| reg_renumber
[regno
] >= 0)
739 for (rtx list
= reg_equiv_init (regno
); list
; list
= XEXP (list
, 1))
741 rtx equiv_insn
= XEXP (list
, 0);
742 if (equiv_insn
== insn
)
748 /* Main entry point for the reload pass.
750 FIRST is the first insn of the function being compiled.
752 GLOBAL nonzero means we were called from global_alloc
753 and should attempt to reallocate any pseudoregs that we
754 displace from hard regs we will use for reloads.
755 If GLOBAL is zero, we do not have enough information to do that,
756 so any pseudo reg that is spilled must go to the stack.
758 Return value is TRUE if reload likely left dead insns in the
759 stream and a DCE pass should be run to elimiante them. Else the
760 return value is FALSE. */
763 reload (rtx first
, int global
)
767 struct elim_table
*ep
;
771 /* Make sure even insns with volatile mem refs are recognizable. */
776 reload_firstobj
= XOBNEWVAR (&reload_obstack
, char, 0);
778 /* Make sure that the last insn in the chain
779 is not something that needs reloading. */
780 emit_note (NOTE_INSN_DELETED
);
782 /* Enable find_equiv_reg to distinguish insns made by reload. */
783 reload_first_uid
= get_max_uid ();
785 #ifdef SECONDARY_MEMORY_NEEDED
786 /* Initialize the secondary memory table. */
787 clear_secondary_mem ();
790 /* We don't have a stack slot for any spill reg yet. */
791 memset (spill_stack_slot
, 0, sizeof spill_stack_slot
);
792 memset (spill_stack_slot_width
, 0, sizeof spill_stack_slot_width
);
794 /* Initialize the save area information for caller-save, in case some
798 /* Compute which hard registers are now in use
799 as homes for pseudo registers.
800 This is done here rather than (eg) in global_alloc
801 because this point is reached even if not optimizing. */
802 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
805 /* A function that has a nonlocal label that can reach the exit
806 block via non-exceptional paths must save all call-saved
808 if (cfun
->has_nonlocal_label
809 && has_nonexceptional_receiver ())
810 crtl
->saves_all_registers
= 1;
812 if (crtl
->saves_all_registers
)
813 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
814 if (! call_used_regs
[i
] && ! fixed_regs
[i
] && ! LOCAL_REGNO (i
))
815 df_set_regs_ever_live (i
, true);
817 /* Find all the pseudo registers that didn't get hard regs
818 but do have known equivalent constants or memory slots.
819 These include parameters (known equivalent to parameter slots)
820 and cse'd or loop-moved constant memory addresses.
822 Record constant equivalents in reg_equiv_constant
823 so they will be substituted by find_reloads.
824 Record memory equivalents in reg_mem_equiv so they can
825 be substituted eventually by altering the REG-rtx's. */
828 reg_old_renumber
= XCNEWVEC (short, max_regno
);
829 memcpy (reg_old_renumber
, reg_renumber
, max_regno
* sizeof (short));
830 pseudo_forbidden_regs
= XNEWVEC (HARD_REG_SET
, max_regno
);
831 pseudo_previous_regs
= XCNEWVEC (HARD_REG_SET
, max_regno
);
833 CLEAR_HARD_REG_SET (bad_spill_regs_global
);
835 init_eliminable_invariants (first
, true);
838 /* Alter each pseudo-reg rtx to contain its hard reg number. Assign
839 stack slots to the pseudos that lack hard regs or equivalents.
840 Do not touch virtual registers. */
842 temp_pseudo_reg_arr
= XNEWVEC (int, max_regno
- LAST_VIRTUAL_REGISTER
- 1);
843 for (n
= 0, i
= LAST_VIRTUAL_REGISTER
+ 1; i
< max_regno
; i
++)
844 temp_pseudo_reg_arr
[n
++] = i
;
847 /* Ask IRA to order pseudo-registers for better stack slot
849 ira_sort_regnos_for_alter_reg (temp_pseudo_reg_arr
, n
, reg_max_ref_width
);
851 for (i
= 0; i
< n
; i
++)
852 alter_reg (temp_pseudo_reg_arr
[i
], -1, false);
854 /* If we have some registers we think can be eliminated, scan all insns to
855 see if there is an insn that sets one of these registers to something
856 other than itself plus a constant. If so, the register cannot be
857 eliminated. Doing this scan here eliminates an extra pass through the
858 main reload loop in the most common case where register elimination
860 for (insn
= first
; insn
&& num_eliminable
; insn
= NEXT_INSN (insn
))
862 note_stores (PATTERN (insn
), mark_not_eliminable
, NULL
);
864 maybe_fix_stack_asms ();
866 insns_need_reload
= 0;
867 something_needs_elimination
= 0;
869 /* Initialize to -1, which means take the first spill register. */
872 /* Spill any hard regs that we know we can't eliminate. */
873 CLEAR_HARD_REG_SET (used_spill_regs
);
874 /* There can be multiple ways to eliminate a register;
875 they should be listed adjacently.
876 Elimination for any register fails only if all possible ways fail. */
877 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; )
880 int can_eliminate
= 0;
883 can_eliminate
|= ep
->can_eliminate
;
886 while (ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
] && ep
->from
== from
);
888 spill_hard_reg (from
, 1);
891 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
892 if (frame_pointer_needed
)
893 spill_hard_reg (HARD_FRAME_POINTER_REGNUM
, 1);
895 finish_spills (global
);
897 /* From now on, we may need to generate moves differently. We may also
898 allow modifications of insns which cause them to not be recognized.
899 Any such modifications will be cleaned up during reload itself. */
900 reload_in_progress
= 1;
902 /* This loop scans the entire function each go-round
903 and repeats until one repetition spills no additional hard regs. */
906 int something_changed
;
908 HOST_WIDE_INT starting_frame_size
;
910 starting_frame_size
= get_frame_size ();
911 something_was_spilled
= false;
913 set_initial_elim_offsets ();
914 set_initial_label_offsets ();
916 /* For each pseudo register that has an equivalent location defined,
917 try to eliminate any eliminable registers (such as the frame pointer)
918 assuming initial offsets for the replacement register, which
921 If the resulting location is directly addressable, substitute
922 the MEM we just got directly for the old REG.
924 If it is not addressable but is a constant or the sum of a hard reg
925 and constant, it is probably not addressable because the constant is
926 out of range, in that case record the address; we will generate
927 hairy code to compute the address in a register each time it is
928 needed. Similarly if it is a hard register, but one that is not
929 valid as an address register.
931 If the location is not addressable, but does not have one of the
932 above forms, assign a stack slot. We have to do this to avoid the
933 potential of producing lots of reloads if, e.g., a location involves
934 a pseudo that didn't get a hard register and has an equivalent memory
935 location that also involves a pseudo that didn't get a hard register.
937 Perhaps at some point we will improve reload_when_needed handling
938 so this problem goes away. But that's very hairy. */
940 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
941 if (reg_renumber
[i
] < 0 && reg_equiv_memory_loc (i
))
943 rtx x
= eliminate_regs (reg_equiv_memory_loc (i
), VOIDmode
,
946 if (strict_memory_address_addr_space_p
947 (GET_MODE (regno_reg_rtx
[i
]), XEXP (x
, 0),
949 reg_equiv_mem (i
) = x
, reg_equiv_address (i
) = 0;
950 else if (CONSTANT_P (XEXP (x
, 0))
951 || (REG_P (XEXP (x
, 0))
952 && REGNO (XEXP (x
, 0)) < FIRST_PSEUDO_REGISTER
)
953 || (GET_CODE (XEXP (x
, 0)) == PLUS
954 && REG_P (XEXP (XEXP (x
, 0), 0))
955 && (REGNO (XEXP (XEXP (x
, 0), 0))
956 < FIRST_PSEUDO_REGISTER
)
957 && CONSTANT_P (XEXP (XEXP (x
, 0), 1))))
958 reg_equiv_address (i
) = XEXP (x
, 0), reg_equiv_mem (i
) = 0;
961 /* Make a new stack slot. Then indicate that something
962 changed so we go back and recompute offsets for
963 eliminable registers because the allocation of memory
964 below might change some offset. reg_equiv_{mem,address}
965 will be set up for this pseudo on the next pass around
967 reg_equiv_memory_loc (i
) = 0;
968 reg_equiv_init (i
) = 0;
969 alter_reg (i
, -1, true);
973 if (caller_save_needed
)
976 if (starting_frame_size
&& crtl
->stack_alignment_needed
)
978 /* If we have a stack frame, we must align it now. The
979 stack size may be a part of the offset computation for
980 register elimination. So if this changes the stack size,
981 then repeat the elimination bookkeeping. We don't
982 realign when there is no stack, as that will cause a
983 stack frame when none is needed should
984 STARTING_FRAME_OFFSET not be already aligned to
986 assign_stack_local (BLKmode
, 0, crtl
->stack_alignment_needed
);
988 /* If we allocated another stack slot, redo elimination bookkeeping. */
989 if (something_was_spilled
|| starting_frame_size
!= get_frame_size ())
991 update_eliminables_and_spill ();
995 if (caller_save_needed
)
997 save_call_clobbered_regs ();
998 /* That might have allocated new insn_chain structures. */
999 reload_firstobj
= XOBNEWVAR (&reload_obstack
, char, 0);
1002 calculate_needs_all_insns (global
);
1004 if (! ira_conflicts_p
)
1005 /* Don't do it for IRA. We need this info because we don't
1006 change live_throughout and dead_or_set for chains when IRA
1008 CLEAR_REG_SET (&spilled_pseudos
);
1012 something_changed
= 0;
1014 /* If we allocated any new memory locations, make another pass
1015 since it might have changed elimination offsets. */
1016 if (something_was_spilled
|| starting_frame_size
!= get_frame_size ())
1017 something_changed
= 1;
1019 /* Even if the frame size remained the same, we might still have
1020 changed elimination offsets, e.g. if find_reloads called
1021 force_const_mem requiring the back end to allocate a constant
1022 pool base register that needs to be saved on the stack. */
1023 else if (!verify_initial_elim_offsets ())
1024 something_changed
= 1;
1026 if (update_eliminables_and_spill ())
1029 something_changed
= 1;
1032 select_reload_regs ();
1036 if (insns_need_reload
!= 0 || did_spill
)
1037 something_changed
|= finish_spills (global
);
1039 if (! something_changed
)
1042 if (caller_save_needed
)
1043 delete_caller_save_insns ();
1045 obstack_free (&reload_obstack
, reload_firstobj
);
1048 /* If global-alloc was run, notify it of any register eliminations we have
1051 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
1052 if (ep
->can_eliminate
)
1053 mark_elimination (ep
->from
, ep
->to
);
1055 remove_init_insns ();
1057 /* Use the reload registers where necessary
1058 by generating move instructions to move the must-be-register
1059 values into or out of the reload registers. */
1061 if (insns_need_reload
!= 0 || something_needs_elimination
1062 || something_needs_operands_changed
)
1064 HOST_WIDE_INT old_frame_size
= get_frame_size ();
1066 reload_as_needed (global
);
1068 gcc_assert (old_frame_size
== get_frame_size ());
1070 gcc_assert (verify_initial_elim_offsets ());
1073 /* If we were able to eliminate the frame pointer, show that it is no
1074 longer live at the start of any basic block. If it ls live by
1075 virtue of being in a pseudo, that pseudo will be marked live
1076 and hence the frame pointer will be known to be live via that
1079 if (! frame_pointer_needed
)
1080 FOR_EACH_BB_FN (bb
, cfun
)
1081 bitmap_clear_bit (df_get_live_in (bb
), HARD_FRAME_POINTER_REGNUM
);
1083 /* Come here (with failure set nonzero) if we can't get enough spill
1087 CLEAR_REG_SET (&changed_allocation_pseudos
);
1088 CLEAR_REG_SET (&spilled_pseudos
);
1089 reload_in_progress
= 0;
1091 /* Now eliminate all pseudo regs by modifying them into
1092 their equivalent memory references.
1093 The REG-rtx's for the pseudos are modified in place,
1094 so all insns that used to refer to them now refer to memory.
1096 For a reg that has a reg_equiv_address, all those insns
1097 were changed by reloading so that no insns refer to it any longer;
1098 but the DECL_RTL of a variable decl may refer to it,
1099 and if so this causes the debugging info to mention the variable. */
1101 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
1105 if (reg_equiv_mem (i
))
1106 addr
= XEXP (reg_equiv_mem (i
), 0);
1108 if (reg_equiv_address (i
))
1109 addr
= reg_equiv_address (i
);
1113 if (reg_renumber
[i
] < 0)
1115 rtx reg
= regno_reg_rtx
[i
];
1117 REG_USERVAR_P (reg
) = 0;
1118 PUT_CODE (reg
, MEM
);
1119 XEXP (reg
, 0) = addr
;
1120 if (reg_equiv_memory_loc (i
))
1121 MEM_COPY_ATTRIBUTES (reg
, reg_equiv_memory_loc (i
));
1123 MEM_ATTRS (reg
) = 0;
1124 MEM_NOTRAP_P (reg
) = 1;
1126 else if (reg_equiv_mem (i
))
1127 XEXP (reg_equiv_mem (i
), 0) = addr
;
1130 /* We don't want complex addressing modes in debug insns
1131 if simpler ones will do, so delegitimize equivalences
1133 if (MAY_HAVE_DEBUG_INSNS
&& reg_renumber
[i
] < 0)
1135 rtx reg
= regno_reg_rtx
[i
];
1139 if (reg_equiv_constant (i
))
1140 equiv
= reg_equiv_constant (i
);
1141 else if (reg_equiv_invariant (i
))
1142 equiv
= reg_equiv_invariant (i
);
1143 else if (reg
&& MEM_P (reg
))
1144 equiv
= targetm
.delegitimize_address (reg
);
1145 else if (reg
&& REG_P (reg
) && (int)REGNO (reg
) != i
)
1151 for (use
= DF_REG_USE_CHAIN (i
); use
; use
= next
)
1153 insn
= DF_REF_INSN (use
);
1155 /* Make sure the next ref is for a different instruction,
1156 so that we're not affected by the rescan. */
1157 next
= DF_REF_NEXT_REG (use
);
1158 while (next
&& DF_REF_INSN (next
) == insn
)
1159 next
= DF_REF_NEXT_REG (next
);
1161 if (DEBUG_INSN_P (insn
))
1165 INSN_VAR_LOCATION_LOC (insn
) = gen_rtx_UNKNOWN_VAR_LOC ();
1166 df_insn_rescan_debug_internal (insn
);
1169 INSN_VAR_LOCATION_LOC (insn
)
1170 = simplify_replace_rtx (INSN_VAR_LOCATION_LOC (insn
),
1177 /* We must set reload_completed now since the cleanup_subreg_operands call
1178 below will re-recognize each insn and reload may have generated insns
1179 which are only valid during and after reload. */
1180 reload_completed
= 1;
1182 /* Make a pass over all the insns and delete all USEs which we inserted
1183 only to tag a REG_EQUAL note on them. Remove all REG_DEAD and REG_UNUSED
1184 notes. Delete all CLOBBER insns, except those that refer to the return
1185 value and the special mem:BLK CLOBBERs added to prevent the scheduler
1186 from misarranging variable-array code, and simplify (subreg (reg))
1187 operands. Strip and regenerate REG_INC notes that may have been moved
1190 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
1196 replace_pseudos_in (& CALL_INSN_FUNCTION_USAGE (insn
),
1197 VOIDmode
, CALL_INSN_FUNCTION_USAGE (insn
));
1199 if ((GET_CODE (PATTERN (insn
)) == USE
1200 /* We mark with QImode USEs introduced by reload itself. */
1201 && (GET_MODE (insn
) == QImode
1202 || find_reg_note (insn
, REG_EQUAL
, NULL_RTX
)))
1203 || (GET_CODE (PATTERN (insn
)) == CLOBBER
1204 && (!MEM_P (XEXP (PATTERN (insn
), 0))
1205 || GET_MODE (XEXP (PATTERN (insn
), 0)) != BLKmode
1206 || (GET_CODE (XEXP (XEXP (PATTERN (insn
), 0), 0)) != SCRATCH
1207 && XEXP (XEXP (PATTERN (insn
), 0), 0)
1208 != stack_pointer_rtx
))
1209 && (!REG_P (XEXP (PATTERN (insn
), 0))
1210 || ! REG_FUNCTION_VALUE_P (XEXP (PATTERN (insn
), 0)))))
1216 /* Some CLOBBERs may survive until here and still reference unassigned
1217 pseudos with const equivalent, which may in turn cause ICE in later
1218 passes if the reference remains in place. */
1219 if (GET_CODE (PATTERN (insn
)) == CLOBBER
)
1220 replace_pseudos_in (& XEXP (PATTERN (insn
), 0),
1221 VOIDmode
, PATTERN (insn
));
1223 /* Discard obvious no-ops, even without -O. This optimization
1224 is fast and doesn't interfere with debugging. */
1225 if (NONJUMP_INSN_P (insn
)
1226 && GET_CODE (PATTERN (insn
)) == SET
1227 && REG_P (SET_SRC (PATTERN (insn
)))
1228 && REG_P (SET_DEST (PATTERN (insn
)))
1229 && (REGNO (SET_SRC (PATTERN (insn
)))
1230 == REGNO (SET_DEST (PATTERN (insn
)))))
1236 pnote
= ®_NOTES (insn
);
1239 if (REG_NOTE_KIND (*pnote
) == REG_DEAD
1240 || REG_NOTE_KIND (*pnote
) == REG_UNUSED
1241 || REG_NOTE_KIND (*pnote
) == REG_INC
)
1242 *pnote
= XEXP (*pnote
, 1);
1244 pnote
= &XEXP (*pnote
, 1);
1248 add_auto_inc_notes (insn
, PATTERN (insn
));
1251 /* Simplify (subreg (reg)) if it appears as an operand. */
1252 cleanup_subreg_operands (insn
);
1254 /* Clean up invalid ASMs so that they don't confuse later passes.
1256 if (asm_noperands (PATTERN (insn
)) >= 0)
1258 extract_insn (insn
);
1259 if (!constrain_operands (1))
1261 error_for_asm (insn
,
1262 "%<asm%> operand has impossible constraints");
1269 /* If we are doing generic stack checking, give a warning if this
1270 function's frame size is larger than we expect. */
1271 if (flag_stack_check
== GENERIC_STACK_CHECK
)
1273 HOST_WIDE_INT size
= get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE
;
1274 static int verbose_warned
= 0;
1276 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1277 if (df_regs_ever_live_p (i
) && ! fixed_regs
[i
] && call_used_regs
[i
])
1278 size
+= UNITS_PER_WORD
;
1280 if (size
> STACK_CHECK_MAX_FRAME_SIZE
)
1282 warning (0, "frame size too large for reliable stack checking");
1283 if (! verbose_warned
)
1285 warning (0, "try reducing the number of local variables");
1291 free (temp_pseudo_reg_arr
);
1293 /* Indicate that we no longer have known memory locations or constants. */
1296 free (reg_max_ref_width
);
1297 free (reg_old_renumber
);
1298 free (pseudo_previous_regs
);
1299 free (pseudo_forbidden_regs
);
1301 CLEAR_HARD_REG_SET (used_spill_regs
);
1302 for (i
= 0; i
< n_spills
; i
++)
1303 SET_HARD_REG_BIT (used_spill_regs
, spill_regs
[i
]);
1305 /* Free all the insn_chain structures at once. */
1306 obstack_free (&reload_obstack
, reload_startobj
);
1307 unused_insn_chains
= 0;
1309 inserted
= fixup_abnormal_edges ();
1311 /* We've possibly turned single trapping insn into multiple ones. */
1312 if (cfun
->can_throw_non_call_exceptions
)
1315 blocks
= sbitmap_alloc (last_basic_block_for_fn (cfun
));
1316 bitmap_ones (blocks
);
1317 find_many_sub_basic_blocks (blocks
);
1318 sbitmap_free (blocks
);
1322 commit_edge_insertions ();
1324 /* Replacing pseudos with their memory equivalents might have
1325 created shared rtx. Subsequent passes would get confused
1326 by this, so unshare everything here. */
1327 unshare_all_rtl_again (first
);
1329 #ifdef STACK_BOUNDARY
1330 /* init_emit has set the alignment of the hard frame pointer
1331 to STACK_BOUNDARY. It is very likely no longer valid if
1332 the hard frame pointer was used for register allocation. */
1333 if (!frame_pointer_needed
)
1334 REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM
) = BITS_PER_UNIT
;
1337 substitute_stack
.release ();
1339 gcc_assert (bitmap_empty_p (&spilled_pseudos
));
1341 reload_completed
= !failure
;
1346 /* Yet another special case. Unfortunately, reg-stack forces people to
1347 write incorrect clobbers in asm statements. These clobbers must not
1348 cause the register to appear in bad_spill_regs, otherwise we'll call
1349 fatal_insn later. We clear the corresponding regnos in the live
1350 register sets to avoid this.
1351 The whole thing is rather sick, I'm afraid. */
1354 maybe_fix_stack_asms (void)
1357 const char *constraints
[MAX_RECOG_OPERANDS
];
1358 enum machine_mode operand_mode
[MAX_RECOG_OPERANDS
];
1359 struct insn_chain
*chain
;
1361 for (chain
= reload_insn_chain
; chain
!= 0; chain
= chain
->next
)
1364 HARD_REG_SET clobbered
, allowed
;
1367 if (! INSN_P (chain
->insn
)
1368 || (noperands
= asm_noperands (PATTERN (chain
->insn
))) < 0)
1370 pat
= PATTERN (chain
->insn
);
1371 if (GET_CODE (pat
) != PARALLEL
)
1374 CLEAR_HARD_REG_SET (clobbered
);
1375 CLEAR_HARD_REG_SET (allowed
);
1377 /* First, make a mask of all stack regs that are clobbered. */
1378 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
1380 rtx t
= XVECEXP (pat
, 0, i
);
1381 if (GET_CODE (t
) == CLOBBER
&& STACK_REG_P (XEXP (t
, 0)))
1382 SET_HARD_REG_BIT (clobbered
, REGNO (XEXP (t
, 0)));
1385 /* Get the operand values and constraints out of the insn. */
1386 decode_asm_operands (pat
, recog_data
.operand
, recog_data
.operand_loc
,
1387 constraints
, operand_mode
, NULL
);
1389 /* For every operand, see what registers are allowed. */
1390 for (i
= 0; i
< noperands
; i
++)
1392 const char *p
= constraints
[i
];
1393 /* For every alternative, we compute the class of registers allowed
1394 for reloading in CLS, and merge its contents into the reg set
1396 int cls
= (int) NO_REGS
;
1402 if (c
== '\0' || c
== ',' || c
== '#')
1404 /* End of one alternative - mark the regs in the current
1405 class, and reset the class. */
1406 IOR_HARD_REG_SET (allowed
, reg_class_contents
[cls
]);
1412 } while (c
!= '\0' && c
!= ',');
1421 cls
= (int) reg_class_subunion
[cls
][(int) GENERAL_REGS
];
1425 enum constraint_num cn
= lookup_constraint (p
);
1426 if (insn_extra_address_constraint (cn
))
1427 cls
= (int) reg_class_subunion
[cls
]
1428 [(int) base_reg_class (VOIDmode
, ADDR_SPACE_GENERIC
,
1431 cls
= (int) reg_class_subunion
[cls
]
1432 [reg_class_for_constraint (cn
)];
1435 p
+= CONSTRAINT_LEN (c
, p
);
1438 /* Those of the registers which are clobbered, but allowed by the
1439 constraints, must be usable as reload registers. So clear them
1440 out of the life information. */
1441 AND_HARD_REG_SET (allowed
, clobbered
);
1442 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1443 if (TEST_HARD_REG_BIT (allowed
, i
))
1445 CLEAR_REGNO_REG_SET (&chain
->live_throughout
, i
);
1446 CLEAR_REGNO_REG_SET (&chain
->dead_or_set
, i
);
1453 /* Copy the global variables n_reloads and rld into the corresponding elts
1456 copy_reloads (struct insn_chain
*chain
)
1458 chain
->n_reloads
= n_reloads
;
1459 chain
->rld
= XOBNEWVEC (&reload_obstack
, struct reload
, n_reloads
);
1460 memcpy (chain
->rld
, rld
, n_reloads
* sizeof (struct reload
));
1461 reload_insn_firstobj
= XOBNEWVAR (&reload_obstack
, char, 0);
1464 /* Walk the chain of insns, and determine for each whether it needs reloads
1465 and/or eliminations. Build the corresponding insns_need_reload list, and
1466 set something_needs_elimination as appropriate. */
1468 calculate_needs_all_insns (int global
)
1470 struct insn_chain
**pprev_reload
= &insns_need_reload
;
1471 struct insn_chain
*chain
, *next
= 0;
1473 something_needs_elimination
= 0;
1475 reload_insn_firstobj
= XOBNEWVAR (&reload_obstack
, char, 0);
1476 for (chain
= reload_insn_chain
; chain
!= 0; chain
= next
)
1478 rtx insn
= chain
->insn
;
1482 /* Clear out the shortcuts. */
1483 chain
->n_reloads
= 0;
1484 chain
->need_elim
= 0;
1485 chain
->need_reload
= 0;
1486 chain
->need_operand_change
= 0;
1488 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1489 include REG_LABEL_OPERAND and REG_LABEL_TARGET), we need to see
1490 what effects this has on the known offsets at labels. */
1492 if (LABEL_P (insn
) || JUMP_P (insn
) || JUMP_TABLE_DATA_P (insn
)
1493 || (INSN_P (insn
) && REG_NOTES (insn
) != 0))
1494 set_label_offsets (insn
, insn
, 0);
1498 rtx old_body
= PATTERN (insn
);
1499 int old_code
= INSN_CODE (insn
);
1500 rtx old_notes
= REG_NOTES (insn
);
1501 int did_elimination
= 0;
1502 int operands_changed
= 0;
1504 /* Skip insns that only set an equivalence. */
1505 if (will_delete_init_insn_p (insn
))
1508 /* If needed, eliminate any eliminable registers. */
1509 if (num_eliminable
|| num_eliminable_invariants
)
1510 did_elimination
= eliminate_regs_in_insn (insn
, 0);
1512 /* Analyze the instruction. */
1513 operands_changed
= find_reloads (insn
, 0, spill_indirect_levels
,
1514 global
, spill_reg_order
);
1516 /* If a no-op set needs more than one reload, this is likely
1517 to be something that needs input address reloads. We
1518 can't get rid of this cleanly later, and it is of no use
1519 anyway, so discard it now.
1520 We only do this when expensive_optimizations is enabled,
1521 since this complements reload inheritance / output
1522 reload deletion, and it can make debugging harder. */
1523 if (flag_expensive_optimizations
&& n_reloads
> 1)
1525 rtx set
= single_set (insn
);
1528 ((SET_SRC (set
) == SET_DEST (set
)
1529 && REG_P (SET_SRC (set
))
1530 && REGNO (SET_SRC (set
)) >= FIRST_PSEUDO_REGISTER
)
1531 || (REG_P (SET_SRC (set
)) && REG_P (SET_DEST (set
))
1532 && reg_renumber
[REGNO (SET_SRC (set
))] < 0
1533 && reg_renumber
[REGNO (SET_DEST (set
))] < 0
1534 && reg_equiv_memory_loc (REGNO (SET_SRC (set
))) != NULL
1535 && reg_equiv_memory_loc (REGNO (SET_DEST (set
))) != NULL
1536 && rtx_equal_p (reg_equiv_memory_loc (REGNO (SET_SRC (set
))),
1537 reg_equiv_memory_loc (REGNO (SET_DEST (set
)))))))
1539 if (ira_conflicts_p
)
1540 /* Inform IRA about the insn deletion. */
1541 ira_mark_memory_move_deletion (REGNO (SET_DEST (set
)),
1542 REGNO (SET_SRC (set
)));
1544 /* Delete it from the reload chain. */
1546 chain
->prev
->next
= next
;
1548 reload_insn_chain
= next
;
1550 next
->prev
= chain
->prev
;
1551 chain
->next
= unused_insn_chains
;
1552 unused_insn_chains
= chain
;
1557 update_eliminable_offsets ();
1559 /* Remember for later shortcuts which insns had any reloads or
1560 register eliminations. */
1561 chain
->need_elim
= did_elimination
;
1562 chain
->need_reload
= n_reloads
> 0;
1563 chain
->need_operand_change
= operands_changed
;
1565 /* Discard any register replacements done. */
1566 if (did_elimination
)
1568 obstack_free (&reload_obstack
, reload_insn_firstobj
);
1569 PATTERN (insn
) = old_body
;
1570 INSN_CODE (insn
) = old_code
;
1571 REG_NOTES (insn
) = old_notes
;
1572 something_needs_elimination
= 1;
1575 something_needs_operands_changed
|= operands_changed
;
1579 copy_reloads (chain
);
1580 *pprev_reload
= chain
;
1581 pprev_reload
= &chain
->next_need_reload
;
1588 /* This function is called from the register allocator to set up estimates
1589 for the cost of eliminating pseudos which have REG_EQUIV equivalences to
1590 an invariant. The structure is similar to calculate_needs_all_insns. */
1593 calculate_elim_costs_all_insns (void)
1595 int *reg_equiv_init_cost
;
1599 reg_equiv_init_cost
= XCNEWVEC (int, max_regno
);
1601 init_eliminable_invariants (get_insns (), false);
1603 set_initial_elim_offsets ();
1604 set_initial_label_offsets ();
1606 FOR_EACH_BB_FN (bb
, cfun
)
1611 FOR_BB_INSNS (bb
, insn
)
1613 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1614 include REG_LABEL_OPERAND and REG_LABEL_TARGET), we need to see
1615 what effects this has on the known offsets at labels. */
1617 if (LABEL_P (insn
) || JUMP_P (insn
) || JUMP_TABLE_DATA_P (insn
)
1618 || (INSN_P (insn
) && REG_NOTES (insn
) != 0))
1619 set_label_offsets (insn
, insn
, 0);
1623 rtx set
= single_set (insn
);
1625 /* Skip insns that only set an equivalence. */
1626 if (set
&& REG_P (SET_DEST (set
))
1627 && reg_renumber
[REGNO (SET_DEST (set
))] < 0
1628 && (reg_equiv_constant (REGNO (SET_DEST (set
)))
1629 || reg_equiv_invariant (REGNO (SET_DEST (set
)))))
1631 unsigned regno
= REGNO (SET_DEST (set
));
1632 rtx init
= reg_equiv_init (regno
);
1635 rtx t
= eliminate_regs_1 (SET_SRC (set
), VOIDmode
, insn
,
1637 int cost
= set_src_cost (t
, optimize_bb_for_speed_p (bb
));
1638 int freq
= REG_FREQ_FROM_BB (bb
);
1640 reg_equiv_init_cost
[regno
] = cost
* freq
;
1644 /* If needed, eliminate any eliminable registers. */
1645 if (num_eliminable
|| num_eliminable_invariants
)
1646 elimination_costs_in_insn (insn
);
1649 update_eliminable_offsets ();
1653 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
1655 if (reg_equiv_invariant (i
))
1657 if (reg_equiv_init (i
))
1659 int cost
= reg_equiv_init_cost
[i
];
1662 "Reg %d has equivalence, initial gains %d\n", i
, cost
);
1664 ira_adjust_equiv_reg_cost (i
, cost
);
1670 "Reg %d had equivalence, but can't be eliminated\n",
1672 ira_adjust_equiv_reg_cost (i
, 0);
1677 free (reg_equiv_init_cost
);
1678 free (offsets_known_at
);
1681 offsets_known_at
= NULL
;
1684 /* Comparison function for qsort to decide which of two reloads
1685 should be handled first. *P1 and *P2 are the reload numbers. */
1688 reload_reg_class_lower (const void *r1p
, const void *r2p
)
1690 int r1
= *(const short *) r1p
, r2
= *(const short *) r2p
;
1693 /* Consider required reloads before optional ones. */
1694 t
= rld
[r1
].optional
- rld
[r2
].optional
;
1698 /* Count all solitary classes before non-solitary ones. */
1699 t
= ((reg_class_size
[(int) rld
[r2
].rclass
] == 1)
1700 - (reg_class_size
[(int) rld
[r1
].rclass
] == 1));
1704 /* Aside from solitaires, consider all multi-reg groups first. */
1705 t
= rld
[r2
].nregs
- rld
[r1
].nregs
;
1709 /* Consider reloads in order of increasing reg-class number. */
1710 t
= (int) rld
[r1
].rclass
- (int) rld
[r2
].rclass
;
1714 /* If reloads are equally urgent, sort by reload number,
1715 so that the results of qsort leave nothing to chance. */
1719 /* The cost of spilling each hard reg. */
1720 static int spill_cost
[FIRST_PSEUDO_REGISTER
];
1722 /* When spilling multiple hard registers, we use SPILL_COST for the first
1723 spilled hard reg and SPILL_ADD_COST for subsequent regs. SPILL_ADD_COST
1724 only the first hard reg for a multi-reg pseudo. */
1725 static int spill_add_cost
[FIRST_PSEUDO_REGISTER
];
1727 /* Map of hard regno to pseudo regno currently occupying the hard
1729 static int hard_regno_to_pseudo_regno
[FIRST_PSEUDO_REGISTER
];
1731 /* Update the spill cost arrays, considering that pseudo REG is live. */
1734 count_pseudo (int reg
)
1736 int freq
= REG_FREQ (reg
);
1737 int r
= reg_renumber
[reg
];
1740 /* Ignore spilled pseudo-registers which can be here only if IRA is used. */
1741 if (ira_conflicts_p
&& r
< 0)
1744 if (REGNO_REG_SET_P (&pseudos_counted
, reg
)
1745 || REGNO_REG_SET_P (&spilled_pseudos
, reg
))
1748 SET_REGNO_REG_SET (&pseudos_counted
, reg
);
1750 gcc_assert (r
>= 0);
1752 spill_add_cost
[r
] += freq
;
1753 nregs
= hard_regno_nregs
[r
][PSEUDO_REGNO_MODE (reg
)];
1756 hard_regno_to_pseudo_regno
[r
+ nregs
] = reg
;
1757 spill_cost
[r
+ nregs
] += freq
;
1761 /* Calculate the SPILL_COST and SPILL_ADD_COST arrays and determine the
1762 contents of BAD_SPILL_REGS for the insn described by CHAIN. */
1765 order_regs_for_reload (struct insn_chain
*chain
)
1768 HARD_REG_SET used_by_pseudos
;
1769 HARD_REG_SET used_by_pseudos2
;
1770 reg_set_iterator rsi
;
1772 COPY_HARD_REG_SET (bad_spill_regs
, fixed_reg_set
);
1774 memset (spill_cost
, 0, sizeof spill_cost
);
1775 memset (spill_add_cost
, 0, sizeof spill_add_cost
);
1776 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1777 hard_regno_to_pseudo_regno
[i
] = -1;
1779 /* Count number of uses of each hard reg by pseudo regs allocated to it
1780 and then order them by decreasing use. First exclude hard registers
1781 that are live in or across this insn. */
1783 REG_SET_TO_HARD_REG_SET (used_by_pseudos
, &chain
->live_throughout
);
1784 REG_SET_TO_HARD_REG_SET (used_by_pseudos2
, &chain
->dead_or_set
);
1785 IOR_HARD_REG_SET (bad_spill_regs
, used_by_pseudos
);
1786 IOR_HARD_REG_SET (bad_spill_regs
, used_by_pseudos2
);
1788 /* Now find out which pseudos are allocated to it, and update
1790 CLEAR_REG_SET (&pseudos_counted
);
1792 EXECUTE_IF_SET_IN_REG_SET
1793 (&chain
->live_throughout
, FIRST_PSEUDO_REGISTER
, i
, rsi
)
1797 EXECUTE_IF_SET_IN_REG_SET
1798 (&chain
->dead_or_set
, FIRST_PSEUDO_REGISTER
, i
, rsi
)
1802 CLEAR_REG_SET (&pseudos_counted
);
1805 /* Vector of reload-numbers showing the order in which the reloads should
1807 static short reload_order
[MAX_RELOADS
];
1809 /* This is used to keep track of the spill regs used in one insn. */
1810 static HARD_REG_SET used_spill_regs_local
;
1812 /* We decided to spill hard register SPILLED, which has a size of
1813 SPILLED_NREGS. Determine how pseudo REG, which is live during the insn,
1814 is affected. We will add it to SPILLED_PSEUDOS if necessary, and we will
1815 update SPILL_COST/SPILL_ADD_COST. */
1818 count_spilled_pseudo (int spilled
, int spilled_nregs
, int reg
)
1820 int freq
= REG_FREQ (reg
);
1821 int r
= reg_renumber
[reg
];
1824 /* Ignore spilled pseudo-registers which can be here only if IRA is used. */
1825 if (ira_conflicts_p
&& r
< 0)
1828 gcc_assert (r
>= 0);
1830 nregs
= hard_regno_nregs
[r
][PSEUDO_REGNO_MODE (reg
)];
1832 if (REGNO_REG_SET_P (&spilled_pseudos
, reg
)
1833 || spilled
+ spilled_nregs
<= r
|| r
+ nregs
<= spilled
)
1836 SET_REGNO_REG_SET (&spilled_pseudos
, reg
);
1838 spill_add_cost
[r
] -= freq
;
1841 hard_regno_to_pseudo_regno
[r
+ nregs
] = -1;
1842 spill_cost
[r
+ nregs
] -= freq
;
1846 /* Find reload register to use for reload number ORDER. */
1849 find_reg (struct insn_chain
*chain
, int order
)
1851 int rnum
= reload_order
[order
];
1852 struct reload
*rl
= rld
+ rnum
;
1853 int best_cost
= INT_MAX
;
1855 unsigned int i
, j
, n
;
1857 HARD_REG_SET not_usable
;
1858 HARD_REG_SET used_by_other_reload
;
1859 reg_set_iterator rsi
;
1860 static int regno_pseudo_regs
[FIRST_PSEUDO_REGISTER
];
1861 static int best_regno_pseudo_regs
[FIRST_PSEUDO_REGISTER
];
1863 COPY_HARD_REG_SET (not_usable
, bad_spill_regs
);
1864 IOR_HARD_REG_SET (not_usable
, bad_spill_regs_global
);
1865 IOR_COMPL_HARD_REG_SET (not_usable
, reg_class_contents
[rl
->rclass
]);
1867 CLEAR_HARD_REG_SET (used_by_other_reload
);
1868 for (k
= 0; k
< order
; k
++)
1870 int other
= reload_order
[k
];
1872 if (rld
[other
].regno
>= 0 && reloads_conflict (other
, rnum
))
1873 for (j
= 0; j
< rld
[other
].nregs
; j
++)
1874 SET_HARD_REG_BIT (used_by_other_reload
, rld
[other
].regno
+ j
);
1877 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1879 #ifdef REG_ALLOC_ORDER
1880 unsigned int regno
= reg_alloc_order
[i
];
1882 unsigned int regno
= i
;
1885 if (! TEST_HARD_REG_BIT (not_usable
, regno
)
1886 && ! TEST_HARD_REG_BIT (used_by_other_reload
, regno
)
1887 && HARD_REGNO_MODE_OK (regno
, rl
->mode
))
1889 int this_cost
= spill_cost
[regno
];
1891 unsigned int this_nregs
= hard_regno_nregs
[regno
][rl
->mode
];
1893 for (j
= 1; j
< this_nregs
; j
++)
1895 this_cost
+= spill_add_cost
[regno
+ j
];
1896 if ((TEST_HARD_REG_BIT (not_usable
, regno
+ j
))
1897 || TEST_HARD_REG_BIT (used_by_other_reload
, regno
+ j
))
1903 if (ira_conflicts_p
)
1905 /* Ask IRA to find a better pseudo-register for
1907 for (n
= j
= 0; j
< this_nregs
; j
++)
1909 int r
= hard_regno_to_pseudo_regno
[regno
+ j
];
1913 if (n
== 0 || regno_pseudo_regs
[n
- 1] != r
)
1914 regno_pseudo_regs
[n
++] = r
;
1916 regno_pseudo_regs
[n
++] = -1;
1918 || ira_better_spill_reload_regno_p (regno_pseudo_regs
,
1919 best_regno_pseudo_regs
,
1926 best_regno_pseudo_regs
[j
] = regno_pseudo_regs
[j
];
1927 if (regno_pseudo_regs
[j
] < 0)
1934 if (rl
->in
&& REG_P (rl
->in
) && REGNO (rl
->in
) == regno
)
1936 if (rl
->out
&& REG_P (rl
->out
) && REGNO (rl
->out
) == regno
)
1938 if (this_cost
< best_cost
1939 /* Among registers with equal cost, prefer caller-saved ones, or
1940 use REG_ALLOC_ORDER if it is defined. */
1941 || (this_cost
== best_cost
1942 #ifdef REG_ALLOC_ORDER
1943 && (inv_reg_alloc_order
[regno
]
1944 < inv_reg_alloc_order
[best_reg
])
1946 && call_used_regs
[regno
]
1947 && ! call_used_regs
[best_reg
]
1952 best_cost
= this_cost
;
1960 fprintf (dump_file
, "Using reg %d for reload %d\n", best_reg
, rnum
);
1962 rl
->nregs
= hard_regno_nregs
[best_reg
][rl
->mode
];
1963 rl
->regno
= best_reg
;
1965 EXECUTE_IF_SET_IN_REG_SET
1966 (&chain
->live_throughout
, FIRST_PSEUDO_REGISTER
, j
, rsi
)
1968 count_spilled_pseudo (best_reg
, rl
->nregs
, j
);
1971 EXECUTE_IF_SET_IN_REG_SET
1972 (&chain
->dead_or_set
, FIRST_PSEUDO_REGISTER
, j
, rsi
)
1974 count_spilled_pseudo (best_reg
, rl
->nregs
, j
);
1977 for (i
= 0; i
< rl
->nregs
; i
++)
1979 gcc_assert (spill_cost
[best_reg
+ i
] == 0);
1980 gcc_assert (spill_add_cost
[best_reg
+ i
] == 0);
1981 gcc_assert (hard_regno_to_pseudo_regno
[best_reg
+ i
] == -1);
1982 SET_HARD_REG_BIT (used_spill_regs_local
, best_reg
+ i
);
1987 /* Find more reload regs to satisfy the remaining need of an insn, which
1989 Do it by ascending class number, since otherwise a reg
1990 might be spilled for a big class and might fail to count
1991 for a smaller class even though it belongs to that class. */
1994 find_reload_regs (struct insn_chain
*chain
)
1998 /* In order to be certain of getting the registers we need,
1999 we must sort the reloads into order of increasing register class.
2000 Then our grabbing of reload registers will parallel the process
2001 that provided the reload registers. */
2002 for (i
= 0; i
< chain
->n_reloads
; i
++)
2004 /* Show whether this reload already has a hard reg. */
2005 if (chain
->rld
[i
].reg_rtx
)
2007 int regno
= REGNO (chain
->rld
[i
].reg_rtx
);
2008 chain
->rld
[i
].regno
= regno
;
2010 = hard_regno_nregs
[regno
][GET_MODE (chain
->rld
[i
].reg_rtx
)];
2013 chain
->rld
[i
].regno
= -1;
2014 reload_order
[i
] = i
;
2017 n_reloads
= chain
->n_reloads
;
2018 memcpy (rld
, chain
->rld
, n_reloads
* sizeof (struct reload
));
2020 CLEAR_HARD_REG_SET (used_spill_regs_local
);
2023 fprintf (dump_file
, "Spilling for insn %d.\n", INSN_UID (chain
->insn
));
2025 qsort (reload_order
, n_reloads
, sizeof (short), reload_reg_class_lower
);
2027 /* Compute the order of preference for hard registers to spill. */
2029 order_regs_for_reload (chain
);
2031 for (i
= 0; i
< n_reloads
; i
++)
2033 int r
= reload_order
[i
];
2035 /* Ignore reloads that got marked inoperative. */
2036 if ((rld
[r
].out
!= 0 || rld
[r
].in
!= 0 || rld
[r
].secondary_p
)
2037 && ! rld
[r
].optional
2038 && rld
[r
].regno
== -1)
2039 if (! find_reg (chain
, i
))
2042 fprintf (dump_file
, "reload failure for reload %d\n", r
);
2043 spill_failure (chain
->insn
, rld
[r
].rclass
);
2049 COPY_HARD_REG_SET (chain
->used_spill_regs
, used_spill_regs_local
);
2050 IOR_HARD_REG_SET (used_spill_regs
, used_spill_regs_local
);
2052 memcpy (chain
->rld
, rld
, n_reloads
* sizeof (struct reload
));
2056 select_reload_regs (void)
2058 struct insn_chain
*chain
;
2060 /* Try to satisfy the needs for each insn. */
2061 for (chain
= insns_need_reload
; chain
!= 0;
2062 chain
= chain
->next_need_reload
)
2063 find_reload_regs (chain
);
2066 /* Delete all insns that were inserted by emit_caller_save_insns during
2069 delete_caller_save_insns (void)
2071 struct insn_chain
*c
= reload_insn_chain
;
2075 while (c
!= 0 && c
->is_caller_save_insn
)
2077 struct insn_chain
*next
= c
->next
;
2080 if (c
== reload_insn_chain
)
2081 reload_insn_chain
= next
;
2085 next
->prev
= c
->prev
;
2087 c
->prev
->next
= next
;
2088 c
->next
= unused_insn_chains
;
2089 unused_insn_chains
= c
;
2097 /* Handle the failure to find a register to spill.
2098 INSN should be one of the insns which needed this particular spill reg. */
2101 spill_failure (rtx insn
, enum reg_class rclass
)
2103 if (asm_noperands (PATTERN (insn
)) >= 0)
2104 error_for_asm (insn
, "can%'t find a register in class %qs while "
2105 "reloading %<asm%>",
2106 reg_class_names
[rclass
]);
2109 error ("unable to find a register to spill in class %qs",
2110 reg_class_names
[rclass
]);
2114 fprintf (dump_file
, "\nReloads for insn # %d\n", INSN_UID (insn
));
2115 debug_reload_to_stream (dump_file
);
2117 fatal_insn ("this is the insn:", insn
);
2121 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
2122 data that is dead in INSN. */
2125 delete_dead_insn (rtx insn
)
2127 rtx prev
= prev_active_insn (insn
);
2130 /* If the previous insn sets a register that dies in our insn make
2131 a note that we want to run DCE immediately after reload.
2133 We used to delete the previous insn & recurse, but that's wrong for
2134 block local equivalences. Instead of trying to figure out the exact
2135 circumstances where we can delete the potentially dead insns, just
2136 let DCE do the job. */
2137 if (prev
&& BLOCK_FOR_INSN (prev
) == BLOCK_FOR_INSN (insn
)
2138 && GET_CODE (PATTERN (prev
)) == SET
2139 && (prev_dest
= SET_DEST (PATTERN (prev
)), REG_P (prev_dest
))
2140 && reg_mentioned_p (prev_dest
, PATTERN (insn
))
2141 && find_regno_note (insn
, REG_DEAD
, REGNO (prev_dest
))
2142 && ! side_effects_p (SET_SRC (PATTERN (prev
))))
2145 SET_INSN_DELETED (insn
);
2148 /* Modify the home of pseudo-reg I.
2149 The new home is present in reg_renumber[I].
2151 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
2152 or it may be -1, meaning there is none or it is not relevant.
2153 This is used so that all pseudos spilled from a given hard reg
2154 can share one stack slot. */
2157 alter_reg (int i
, int from_reg
, bool dont_share_p
)
2159 /* When outputting an inline function, this can happen
2160 for a reg that isn't actually used. */
2161 if (regno_reg_rtx
[i
] == 0)
2164 /* If the reg got changed to a MEM at rtl-generation time,
2166 if (!REG_P (regno_reg_rtx
[i
]))
2169 /* Modify the reg-rtx to contain the new hard reg
2170 number or else to contain its pseudo reg number. */
2171 SET_REGNO (regno_reg_rtx
[i
],
2172 reg_renumber
[i
] >= 0 ? reg_renumber
[i
] : i
);
2174 /* If we have a pseudo that is needed but has no hard reg or equivalent,
2175 allocate a stack slot for it. */
2177 if (reg_renumber
[i
] < 0
2178 && REG_N_REFS (i
) > 0
2179 && reg_equiv_constant (i
) == 0
2180 && (reg_equiv_invariant (i
) == 0
2181 || reg_equiv_init (i
) == 0)
2182 && reg_equiv_memory_loc (i
) == 0)
2185 enum machine_mode mode
= GET_MODE (regno_reg_rtx
[i
]);
2186 unsigned int inherent_size
= PSEUDO_REGNO_BYTES (i
);
2187 unsigned int inherent_align
= GET_MODE_ALIGNMENT (mode
);
2188 unsigned int total_size
= MAX (inherent_size
, reg_max_ref_width
[i
]);
2189 unsigned int min_align
= reg_max_ref_width
[i
] * BITS_PER_UNIT
;
2192 something_was_spilled
= true;
2194 if (ira_conflicts_p
)
2196 /* Mark the spill for IRA. */
2197 SET_REGNO_REG_SET (&spilled_pseudos
, i
);
2199 x
= ira_reuse_stack_slot (i
, inherent_size
, total_size
);
2205 /* Each pseudo reg has an inherent size which comes from its own mode,
2206 and a total size which provides room for paradoxical subregs
2207 which refer to the pseudo reg in wider modes.
2209 We can use a slot already allocated if it provides both
2210 enough inherent space and enough total space.
2211 Otherwise, we allocate a new slot, making sure that it has no less
2212 inherent space, and no less total space, then the previous slot. */
2213 else if (from_reg
== -1 || (!dont_share_p
&& ira_conflicts_p
))
2217 /* No known place to spill from => no slot to reuse. */
2218 x
= assign_stack_local (mode
, total_size
,
2219 min_align
> inherent_align
2220 || total_size
> inherent_size
? -1 : 0);
2224 /* Cancel the big-endian correction done in assign_stack_local.
2225 Get the address of the beginning of the slot. This is so we
2226 can do a big-endian correction unconditionally below. */
2227 if (BYTES_BIG_ENDIAN
)
2229 adjust
= inherent_size
- total_size
;
2232 = adjust_address_nv (x
, mode_for_size (total_size
2238 if (! dont_share_p
&& ira_conflicts_p
)
2239 /* Inform IRA about allocation a new stack slot. */
2240 ira_mark_new_stack_slot (stack_slot
, i
, total_size
);
2243 /* Reuse a stack slot if possible. */
2244 else if (spill_stack_slot
[from_reg
] != 0
2245 && spill_stack_slot_width
[from_reg
] >= total_size
2246 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot
[from_reg
]))
2248 && MEM_ALIGN (spill_stack_slot
[from_reg
]) >= min_align
)
2249 x
= spill_stack_slot
[from_reg
];
2251 /* Allocate a bigger slot. */
2254 /* Compute maximum size needed, both for inherent size
2255 and for total size. */
2258 if (spill_stack_slot
[from_reg
])
2260 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot
[from_reg
]))
2262 mode
= GET_MODE (spill_stack_slot
[from_reg
]);
2263 if (spill_stack_slot_width
[from_reg
] > total_size
)
2264 total_size
= spill_stack_slot_width
[from_reg
];
2265 if (MEM_ALIGN (spill_stack_slot
[from_reg
]) > min_align
)
2266 min_align
= MEM_ALIGN (spill_stack_slot
[from_reg
]);
2269 /* Make a slot with that size. */
2270 x
= assign_stack_local (mode
, total_size
,
2271 min_align
> inherent_align
2272 || total_size
> inherent_size
? -1 : 0);
2275 /* Cancel the big-endian correction done in assign_stack_local.
2276 Get the address of the beginning of the slot. This is so we
2277 can do a big-endian correction unconditionally below. */
2278 if (BYTES_BIG_ENDIAN
)
2280 adjust
= GET_MODE_SIZE (mode
) - total_size
;
2283 = adjust_address_nv (x
, mode_for_size (total_size
2289 spill_stack_slot
[from_reg
] = stack_slot
;
2290 spill_stack_slot_width
[from_reg
] = total_size
;
2293 /* On a big endian machine, the "address" of the slot
2294 is the address of the low part that fits its inherent mode. */
2295 if (BYTES_BIG_ENDIAN
&& inherent_size
< total_size
)
2296 adjust
+= (total_size
- inherent_size
);
2298 /* If we have any adjustment to make, or if the stack slot is the
2299 wrong mode, make a new stack slot. */
2300 x
= adjust_address_nv (x
, GET_MODE (regno_reg_rtx
[i
]), adjust
);
2302 /* Set all of the memory attributes as appropriate for a spill. */
2303 set_mem_attrs_for_spill (x
);
2305 /* Save the stack slot for later. */
2306 reg_equiv_memory_loc (i
) = x
;
2310 /* Mark the slots in regs_ever_live for the hard regs used by
2311 pseudo-reg number REGNO, accessed in MODE. */
2314 mark_home_live_1 (int regno
, enum machine_mode mode
)
2318 i
= reg_renumber
[regno
];
2321 lim
= end_hard_regno (mode
, i
);
2323 df_set_regs_ever_live (i
++, true);
2326 /* Mark the slots in regs_ever_live for the hard regs
2327 used by pseudo-reg number REGNO. */
2330 mark_home_live (int regno
)
2332 if (reg_renumber
[regno
] >= 0)
2333 mark_home_live_1 (regno
, PSEUDO_REGNO_MODE (regno
));
2336 /* This function handles the tracking of elimination offsets around branches.
2338 X is a piece of RTL being scanned.
2340 INSN is the insn that it came from, if any.
2342 INITIAL_P is nonzero if we are to set the offset to be the initial
2343 offset and zero if we are setting the offset of the label to be the
2347 set_label_offsets (rtx x
, rtx insn
, int initial_p
)
2349 enum rtx_code code
= GET_CODE (x
);
2352 struct elim_table
*p
;
2357 if (LABEL_REF_NONLOCAL_P (x
))
2362 /* ... fall through ... */
2365 /* If we know nothing about this label, set the desired offsets. Note
2366 that this sets the offset at a label to be the offset before a label
2367 if we don't know anything about the label. This is not correct for
2368 the label after a BARRIER, but is the best guess we can make. If
2369 we guessed wrong, we will suppress an elimination that might have
2370 been possible had we been able to guess correctly. */
2372 if (! offsets_known_at
[CODE_LABEL_NUMBER (x
) - first_label_num
])
2374 for (i
= 0; i
< NUM_ELIMINABLE_REGS
; i
++)
2375 offsets_at
[CODE_LABEL_NUMBER (x
) - first_label_num
][i
]
2376 = (initial_p
? reg_eliminate
[i
].initial_offset
2377 : reg_eliminate
[i
].offset
);
2378 offsets_known_at
[CODE_LABEL_NUMBER (x
) - first_label_num
] = 1;
2381 /* Otherwise, if this is the definition of a label and it is
2382 preceded by a BARRIER, set our offsets to the known offset of
2386 && (tem
= prev_nonnote_insn (insn
)) != 0
2388 set_offsets_for_label (insn
);
2390 /* If neither of the above cases is true, compare each offset
2391 with those previously recorded and suppress any eliminations
2392 where the offsets disagree. */
2394 for (i
= 0; i
< NUM_ELIMINABLE_REGS
; i
++)
2395 if (offsets_at
[CODE_LABEL_NUMBER (x
) - first_label_num
][i
]
2396 != (initial_p
? reg_eliminate
[i
].initial_offset
2397 : reg_eliminate
[i
].offset
))
2398 reg_eliminate
[i
].can_eliminate
= 0;
2402 case JUMP_TABLE_DATA
:
2403 set_label_offsets (PATTERN (insn
), insn
, initial_p
);
2407 set_label_offsets (PATTERN (insn
), insn
, initial_p
);
2409 /* ... fall through ... */
2413 /* Any labels mentioned in REG_LABEL_OPERAND notes can be branched
2414 to indirectly and hence must have all eliminations at their
2416 for (tem
= REG_NOTES (x
); tem
; tem
= XEXP (tem
, 1))
2417 if (REG_NOTE_KIND (tem
) == REG_LABEL_OPERAND
)
2418 set_label_offsets (XEXP (tem
, 0), insn
, 1);
2424 /* Each of the labels in the parallel or address vector must be
2425 at their initial offsets. We want the first field for PARALLEL
2426 and ADDR_VEC and the second field for ADDR_DIFF_VEC. */
2428 for (i
= 0; i
< (unsigned) XVECLEN (x
, code
== ADDR_DIFF_VEC
); i
++)
2429 set_label_offsets (XVECEXP (x
, code
== ADDR_DIFF_VEC
, i
),
2434 /* We only care about setting PC. If the source is not RETURN,
2435 IF_THEN_ELSE, or a label, disable any eliminations not at
2436 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2437 isn't one of those possibilities. For branches to a label,
2438 call ourselves recursively.
2440 Note that this can disable elimination unnecessarily when we have
2441 a non-local goto since it will look like a non-constant jump to
2442 someplace in the current function. This isn't a significant
2443 problem since such jumps will normally be when all elimination
2444 pairs are back to their initial offsets. */
2446 if (SET_DEST (x
) != pc_rtx
)
2449 switch (GET_CODE (SET_SRC (x
)))
2456 set_label_offsets (SET_SRC (x
), insn
, initial_p
);
2460 tem
= XEXP (SET_SRC (x
), 1);
2461 if (GET_CODE (tem
) == LABEL_REF
)
2462 set_label_offsets (XEXP (tem
, 0), insn
, initial_p
);
2463 else if (GET_CODE (tem
) != PC
&& GET_CODE (tem
) != RETURN
)
2466 tem
= XEXP (SET_SRC (x
), 2);
2467 if (GET_CODE (tem
) == LABEL_REF
)
2468 set_label_offsets (XEXP (tem
, 0), insn
, initial_p
);
2469 else if (GET_CODE (tem
) != PC
&& GET_CODE (tem
) != RETURN
)
2477 /* If we reach here, all eliminations must be at their initial
2478 offset because we are doing a jump to a variable address. */
2479 for (p
= reg_eliminate
; p
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; p
++)
2480 if (p
->offset
!= p
->initial_offset
)
2481 p
->can_eliminate
= 0;
2489 /* Called through for_each_rtx, this function examines every reg that occurs
2490 in PX and adjusts the costs for its elimination which are gathered by IRA.
2491 DATA is the insn in which PX occurs. We do not recurse into MEM
2495 note_reg_elim_costly (rtx
*px
, void *data
)
2497 rtx insn
= (rtx
)data
;
2504 && REGNO (x
) >= FIRST_PSEUDO_REGISTER
2505 && reg_equiv_init (REGNO (x
))
2506 && reg_equiv_invariant (REGNO (x
)))
2508 rtx t
= reg_equiv_invariant (REGNO (x
));
2509 rtx new_rtx
= eliminate_regs_1 (t
, Pmode
, insn
, true, true);
2510 int cost
= set_src_cost (new_rtx
, optimize_bb_for_speed_p (elim_bb
));
2511 int freq
= REG_FREQ_FROM_BB (elim_bb
);
2514 ira_adjust_equiv_reg_cost (REGNO (x
), -cost
* freq
);
2519 /* Scan X and replace any eliminable registers (such as fp) with a
2520 replacement (such as sp), plus an offset.
2522 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2523 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2524 MEM, we are allowed to replace a sum of a register and the constant zero
2525 with the register, which we cannot do outside a MEM. In addition, we need
2526 to record the fact that a register is referenced outside a MEM.
2528 If INSN is an insn, it is the insn containing X. If we replace a REG
2529 in a SET_DEST with an equivalent MEM and INSN is nonzero, write a
2530 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2531 the REG is being modified.
2533 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2534 That's used when we eliminate in expressions stored in notes.
2535 This means, do not set ref_outside_mem even if the reference
2538 If FOR_COSTS is true, we are being called before reload in order to
2539 estimate the costs of keeping registers with an equivalence unallocated.
2541 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2542 replacements done assuming all offsets are at their initial values. If
2543 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2544 encounter, return the actual location so that find_reloads will do
2545 the proper thing. */
2548 eliminate_regs_1 (rtx x
, enum machine_mode mem_mode
, rtx insn
,
2549 bool may_use_invariant
, bool for_costs
)
2551 enum rtx_code code
= GET_CODE (x
);
2552 struct elim_table
*ep
;
2559 if (! current_function_decl
)
2579 /* First handle the case where we encounter a bare register that
2580 is eliminable. Replace it with a PLUS. */
2581 if (regno
< FIRST_PSEUDO_REGISTER
)
2583 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
2585 if (ep
->from_rtx
== x
&& ep
->can_eliminate
)
2586 return plus_constant (Pmode
, ep
->to_rtx
, ep
->previous_offset
);
2589 else if (reg_renumber
&& reg_renumber
[regno
] < 0
2591 && reg_equiv_invariant (regno
))
2593 if (may_use_invariant
|| (insn
&& DEBUG_INSN_P (insn
)))
2594 return eliminate_regs_1 (copy_rtx (reg_equiv_invariant (regno
)),
2595 mem_mode
, insn
, true, for_costs
);
2596 /* There exists at least one use of REGNO that cannot be
2597 eliminated. Prevent the defining insn from being deleted. */
2598 reg_equiv_init (regno
) = NULL_RTX
;
2600 alter_reg (regno
, -1, true);
2604 /* You might think handling MINUS in a manner similar to PLUS is a
2605 good idea. It is not. It has been tried multiple times and every
2606 time the change has had to have been reverted.
2608 Other parts of reload know a PLUS is special (gen_reload for example)
2609 and require special code to handle code a reloaded PLUS operand.
2611 Also consider backends where the flags register is clobbered by a
2612 MINUS, but we can emit a PLUS that does not clobber flags (IA-32,
2613 lea instruction comes to mind). If we try to reload a MINUS, we
2614 may kill the flags register that was holding a useful value.
2616 So, please before trying to handle MINUS, consider reload as a
2617 whole instead of this little section as well as the backend issues. */
2619 /* If this is the sum of an eliminable register and a constant, rework
2621 if (REG_P (XEXP (x
, 0))
2622 && REGNO (XEXP (x
, 0)) < FIRST_PSEUDO_REGISTER
2623 && CONSTANT_P (XEXP (x
, 1)))
2625 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
2627 if (ep
->from_rtx
== XEXP (x
, 0) && ep
->can_eliminate
)
2629 /* The only time we want to replace a PLUS with a REG (this
2630 occurs when the constant operand of the PLUS is the negative
2631 of the offset) is when we are inside a MEM. We won't want
2632 to do so at other times because that would change the
2633 structure of the insn in a way that reload can't handle.
2634 We special-case the commonest situation in
2635 eliminate_regs_in_insn, so just replace a PLUS with a
2636 PLUS here, unless inside a MEM. */
2637 if (mem_mode
!= 0 && CONST_INT_P (XEXP (x
, 1))
2638 && INTVAL (XEXP (x
, 1)) == - ep
->previous_offset
)
2641 return gen_rtx_PLUS (Pmode
, ep
->to_rtx
,
2642 plus_constant (Pmode
, XEXP (x
, 1),
2643 ep
->previous_offset
));
2646 /* If the register is not eliminable, we are done since the other
2647 operand is a constant. */
2651 /* If this is part of an address, we want to bring any constant to the
2652 outermost PLUS. We will do this by doing register replacement in
2653 our operands and seeing if a constant shows up in one of them.
2655 Note that there is no risk of modifying the structure of the insn,
2656 since we only get called for its operands, thus we are either
2657 modifying the address inside a MEM, or something like an address
2658 operand of a load-address insn. */
2661 rtx new0
= eliminate_regs_1 (XEXP (x
, 0), mem_mode
, insn
, true,
2663 rtx new1
= eliminate_regs_1 (XEXP (x
, 1), mem_mode
, insn
, true,
2666 if (reg_renumber
&& (new0
!= XEXP (x
, 0) || new1
!= XEXP (x
, 1)))
2668 /* If one side is a PLUS and the other side is a pseudo that
2669 didn't get a hard register but has a reg_equiv_constant,
2670 we must replace the constant here since it may no longer
2671 be in the position of any operand. */
2672 if (GET_CODE (new0
) == PLUS
&& REG_P (new1
)
2673 && REGNO (new1
) >= FIRST_PSEUDO_REGISTER
2674 && reg_renumber
[REGNO (new1
)] < 0
2676 && reg_equiv_constant (REGNO (new1
)) != 0)
2677 new1
= reg_equiv_constant (REGNO (new1
));
2678 else if (GET_CODE (new1
) == PLUS
&& REG_P (new0
)
2679 && REGNO (new0
) >= FIRST_PSEUDO_REGISTER
2680 && reg_renumber
[REGNO (new0
)] < 0
2681 && reg_equiv_constant (REGNO (new0
)) != 0)
2682 new0
= reg_equiv_constant (REGNO (new0
));
2684 new_rtx
= form_sum (GET_MODE (x
), new0
, new1
);
2686 /* As above, if we are not inside a MEM we do not want to
2687 turn a PLUS into something else. We might try to do so here
2688 for an addition of 0 if we aren't optimizing. */
2689 if (! mem_mode
&& GET_CODE (new_rtx
) != PLUS
)
2690 return gen_rtx_PLUS (GET_MODE (x
), new_rtx
, const0_rtx
);
2698 /* If this is the product of an eliminable register and a
2699 constant, apply the distribute law and move the constant out
2700 so that we have (plus (mult ..) ..). This is needed in order
2701 to keep load-address insns valid. This case is pathological.
2702 We ignore the possibility of overflow here. */
2703 if (REG_P (XEXP (x
, 0))
2704 && REGNO (XEXP (x
, 0)) < FIRST_PSEUDO_REGISTER
2705 && CONST_INT_P (XEXP (x
, 1)))
2706 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
2708 if (ep
->from_rtx
== XEXP (x
, 0) && ep
->can_eliminate
)
2711 /* Refs inside notes or in DEBUG_INSNs don't count for
2713 && ! (insn
!= 0 && (GET_CODE (insn
) == EXPR_LIST
2714 || GET_CODE (insn
) == INSN_LIST
2715 || DEBUG_INSN_P (insn
))))
2716 ep
->ref_outside_mem
= 1;
2719 plus_constant (Pmode
,
2720 gen_rtx_MULT (Pmode
, ep
->to_rtx
, XEXP (x
, 1)),
2721 ep
->previous_offset
* INTVAL (XEXP (x
, 1)));
2724 /* ... fall through ... */
2728 /* See comments before PLUS about handling MINUS. */
2730 case DIV
: case UDIV
:
2731 case MOD
: case UMOD
:
2732 case AND
: case IOR
: case XOR
:
2733 case ROTATERT
: case ROTATE
:
2734 case ASHIFTRT
: case LSHIFTRT
: case ASHIFT
:
2736 case GE
: case GT
: case GEU
: case GTU
:
2737 case LE
: case LT
: case LEU
: case LTU
:
2739 rtx new0
= eliminate_regs_1 (XEXP (x
, 0), mem_mode
, insn
, false,
2741 rtx new1
= XEXP (x
, 1)
2742 ? eliminate_regs_1 (XEXP (x
, 1), mem_mode
, insn
, false,
2745 if (new0
!= XEXP (x
, 0) || new1
!= XEXP (x
, 1))
2746 return gen_rtx_fmt_ee (code
, GET_MODE (x
), new0
, new1
);
2751 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2754 new_rtx
= eliminate_regs_1 (XEXP (x
, 0), mem_mode
, insn
, true,
2756 if (new_rtx
!= XEXP (x
, 0))
2758 /* If this is a REG_DEAD note, it is not valid anymore.
2759 Using the eliminated version could result in creating a
2760 REG_DEAD note for the stack or frame pointer. */
2761 if (REG_NOTE_KIND (x
) == REG_DEAD
)
2763 ? eliminate_regs_1 (XEXP (x
, 1), mem_mode
, insn
, true,
2767 x
= alloc_reg_note (REG_NOTE_KIND (x
), new_rtx
, XEXP (x
, 1));
2771 /* ... fall through ... */
2775 /* Now do eliminations in the rest of the chain. If this was
2776 an EXPR_LIST, this might result in allocating more memory than is
2777 strictly needed, but it simplifies the code. */
2780 new_rtx
= eliminate_regs_1 (XEXP (x
, 1), mem_mode
, insn
, true,
2782 if (new_rtx
!= XEXP (x
, 1))
2784 gen_rtx_fmt_ee (GET_CODE (x
), GET_MODE (x
), XEXP (x
, 0), new_rtx
);
2792 /* We do not support elimination of a register that is modified.
2793 elimination_effects has already make sure that this does not
2799 /* We do not support elimination of a register that is modified.
2800 elimination_effects has already make sure that this does not
2801 happen. The only remaining case we need to consider here is
2802 that the increment value may be an eliminable register. */
2803 if (GET_CODE (XEXP (x
, 1)) == PLUS
2804 && XEXP (XEXP (x
, 1), 0) == XEXP (x
, 0))
2806 rtx new_rtx
= eliminate_regs_1 (XEXP (XEXP (x
, 1), 1), mem_mode
,
2807 insn
, true, for_costs
);
2809 if (new_rtx
!= XEXP (XEXP (x
, 1), 1))
2810 return gen_rtx_fmt_ee (code
, GET_MODE (x
), XEXP (x
, 0),
2811 gen_rtx_PLUS (GET_MODE (x
),
2812 XEXP (x
, 0), new_rtx
));
2816 case STRICT_LOW_PART
:
2818 case SIGN_EXTEND
: case ZERO_EXTEND
:
2819 case TRUNCATE
: case FLOAT_EXTEND
: case FLOAT_TRUNCATE
:
2820 case FLOAT
: case FIX
:
2821 case UNSIGNED_FIX
: case UNSIGNED_FLOAT
:
2830 new_rtx
= eliminate_regs_1 (XEXP (x
, 0), mem_mode
, insn
, false,
2832 if (new_rtx
!= XEXP (x
, 0))
2833 return gen_rtx_fmt_e (code
, GET_MODE (x
), new_rtx
);
2837 /* Similar to above processing, but preserve SUBREG_BYTE.
2838 Convert (subreg (mem)) to (mem) if not paradoxical.
2839 Also, if we have a non-paradoxical (subreg (pseudo)) and the
2840 pseudo didn't get a hard reg, we must replace this with the
2841 eliminated version of the memory location because push_reload
2842 may do the replacement in certain circumstances. */
2843 if (REG_P (SUBREG_REG (x
))
2844 && !paradoxical_subreg_p (x
)
2846 && reg_equiv_memory_loc (REGNO (SUBREG_REG (x
))) != 0)
2848 new_rtx
= SUBREG_REG (x
);
2851 new_rtx
= eliminate_regs_1 (SUBREG_REG (x
), mem_mode
, insn
, false, for_costs
);
2853 if (new_rtx
!= SUBREG_REG (x
))
2855 int x_size
= GET_MODE_SIZE (GET_MODE (x
));
2856 int new_size
= GET_MODE_SIZE (GET_MODE (new_rtx
));
2859 && ((x_size
< new_size
2860 #ifdef WORD_REGISTER_OPERATIONS
2861 /* On these machines, combine can create rtl of the form
2862 (set (subreg:m1 (reg:m2 R) 0) ...)
2863 where m1 < m2, and expects something interesting to
2864 happen to the entire word. Moreover, it will use the
2865 (reg:m2 R) later, expecting all bits to be preserved.
2866 So if the number of words is the same, preserve the
2867 subreg so that push_reload can see it. */
2868 && ! ((x_size
- 1) / UNITS_PER_WORD
2869 == (new_size
-1 ) / UNITS_PER_WORD
)
2872 || x_size
== new_size
)
2874 return adjust_address_nv (new_rtx
, GET_MODE (x
), SUBREG_BYTE (x
));
2876 return gen_rtx_SUBREG (GET_MODE (x
), new_rtx
, SUBREG_BYTE (x
));
2882 /* Our only special processing is to pass the mode of the MEM to our
2883 recursive call and copy the flags. While we are here, handle this
2884 case more efficiently. */
2886 new_rtx
= eliminate_regs_1 (XEXP (x
, 0), GET_MODE (x
), insn
, true,
2889 && memory_address_p (GET_MODE (x
), XEXP (x
, 0))
2890 && !memory_address_p (GET_MODE (x
), new_rtx
))
2891 for_each_rtx (&XEXP (x
, 0), note_reg_elim_costly
, insn
);
2893 return replace_equiv_address_nv (x
, new_rtx
);
2896 /* Handle insn_list USE that a call to a pure function may generate. */
2897 new_rtx
= eliminate_regs_1 (XEXP (x
, 0), VOIDmode
, insn
, false,
2899 if (new_rtx
!= XEXP (x
, 0))
2900 return gen_rtx_USE (GET_MODE (x
), new_rtx
);
2905 gcc_assert (insn
&& DEBUG_INSN_P (insn
));
2915 /* Process each of our operands recursively. If any have changed, make a
2917 fmt
= GET_RTX_FORMAT (code
);
2918 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++, fmt
++)
2922 new_rtx
= eliminate_regs_1 (XEXP (x
, i
), mem_mode
, insn
, false,
2924 if (new_rtx
!= XEXP (x
, i
) && ! copied
)
2926 x
= shallow_copy_rtx (x
);
2929 XEXP (x
, i
) = new_rtx
;
2931 else if (*fmt
== 'E')
2934 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
2936 new_rtx
= eliminate_regs_1 (XVECEXP (x
, i
, j
), mem_mode
, insn
, false,
2938 if (new_rtx
!= XVECEXP (x
, i
, j
) && ! copied_vec
)
2940 rtvec new_v
= gen_rtvec_v (XVECLEN (x
, i
),
2944 x
= shallow_copy_rtx (x
);
2947 XVEC (x
, i
) = new_v
;
2950 XVECEXP (x
, i
, j
) = new_rtx
;
2959 eliminate_regs (rtx x
, enum machine_mode mem_mode
, rtx insn
)
2961 return eliminate_regs_1 (x
, mem_mode
, insn
, false, false);
2964 /* Scan rtx X for modifications of elimination target registers. Update
2965 the table of eliminables to reflect the changed state. MEM_MODE is
2966 the mode of an enclosing MEM rtx, or VOIDmode if not within a MEM. */
2969 elimination_effects (rtx x
, enum machine_mode mem_mode
)
2971 enum rtx_code code
= GET_CODE (x
);
2972 struct elim_table
*ep
;
2994 /* First handle the case where we encounter a bare register that
2995 is eliminable. Replace it with a PLUS. */
2996 if (regno
< FIRST_PSEUDO_REGISTER
)
2998 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
3000 if (ep
->from_rtx
== x
&& ep
->can_eliminate
)
3003 ep
->ref_outside_mem
= 1;
3008 else if (reg_renumber
[regno
] < 0
3010 && reg_equiv_constant (regno
)
3011 && ! function_invariant_p (reg_equiv_constant (regno
)))
3012 elimination_effects (reg_equiv_constant (regno
), mem_mode
);
3021 /* If we modify the source of an elimination rule, disable it. */
3022 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3023 if (ep
->from_rtx
== XEXP (x
, 0))
3024 ep
->can_eliminate
= 0;
3026 /* If we modify the target of an elimination rule by adding a constant,
3027 update its offset. If we modify the target in any other way, we'll
3028 have to disable the rule as well. */
3029 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3030 if (ep
->to_rtx
== XEXP (x
, 0))
3032 int size
= GET_MODE_SIZE (mem_mode
);
3034 /* If more bytes than MEM_MODE are pushed, account for them. */
3035 #ifdef PUSH_ROUNDING
3036 if (ep
->to_rtx
== stack_pointer_rtx
)
3037 size
= PUSH_ROUNDING (size
);
3039 if (code
== PRE_DEC
|| code
== POST_DEC
)
3041 else if (code
== PRE_INC
|| code
== POST_INC
)
3043 else if (code
== PRE_MODIFY
|| code
== POST_MODIFY
)
3045 if (GET_CODE (XEXP (x
, 1)) == PLUS
3046 && XEXP (x
, 0) == XEXP (XEXP (x
, 1), 0)
3047 && CONST_INT_P (XEXP (XEXP (x
, 1), 1)))
3048 ep
->offset
-= INTVAL (XEXP (XEXP (x
, 1), 1));
3050 ep
->can_eliminate
= 0;
3054 /* These two aren't unary operators. */
3055 if (code
== POST_MODIFY
|| code
== PRE_MODIFY
)
3058 /* Fall through to generic unary operation case. */
3059 case STRICT_LOW_PART
:
3061 case SIGN_EXTEND
: case ZERO_EXTEND
:
3062 case TRUNCATE
: case FLOAT_EXTEND
: case FLOAT_TRUNCATE
:
3063 case FLOAT
: case FIX
:
3064 case UNSIGNED_FIX
: case UNSIGNED_FLOAT
:
3073 elimination_effects (XEXP (x
, 0), mem_mode
);
3077 if (REG_P (SUBREG_REG (x
))
3078 && (GET_MODE_SIZE (GET_MODE (x
))
3079 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
3081 && reg_equiv_memory_loc (REGNO (SUBREG_REG (x
))) != 0)
3084 elimination_effects (SUBREG_REG (x
), mem_mode
);
3088 /* If using a register that is the source of an eliminate we still
3089 think can be performed, note it cannot be performed since we don't
3090 know how this register is used. */
3091 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3092 if (ep
->from_rtx
== XEXP (x
, 0))
3093 ep
->can_eliminate
= 0;
3095 elimination_effects (XEXP (x
, 0), mem_mode
);
3099 /* If clobbering a register that is the replacement register for an
3100 elimination we still think can be performed, note that it cannot
3101 be performed. Otherwise, we need not be concerned about it. */
3102 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3103 if (ep
->to_rtx
== XEXP (x
, 0))
3104 ep
->can_eliminate
= 0;
3106 elimination_effects (XEXP (x
, 0), mem_mode
);
3110 /* Check for setting a register that we know about. */
3111 if (REG_P (SET_DEST (x
)))
3113 /* See if this is setting the replacement register for an
3116 If DEST is the hard frame pointer, we do nothing because we
3117 assume that all assignments to the frame pointer are for
3118 non-local gotos and are being done at a time when they are valid
3119 and do not disturb anything else. Some machines want to
3120 eliminate a fake argument pointer (or even a fake frame pointer)
3121 with either the real frame or the stack pointer. Assignments to
3122 the hard frame pointer must not prevent this elimination. */
3124 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
3126 if (ep
->to_rtx
== SET_DEST (x
)
3127 && SET_DEST (x
) != hard_frame_pointer_rtx
)
3129 /* If it is being incremented, adjust the offset. Otherwise,
3130 this elimination can't be done. */
3131 rtx src
= SET_SRC (x
);
3133 if (GET_CODE (src
) == PLUS
3134 && XEXP (src
, 0) == SET_DEST (x
)
3135 && CONST_INT_P (XEXP (src
, 1)))
3136 ep
->offset
-= INTVAL (XEXP (src
, 1));
3138 ep
->can_eliminate
= 0;
3142 elimination_effects (SET_DEST (x
), VOIDmode
);
3143 elimination_effects (SET_SRC (x
), VOIDmode
);
3147 /* Our only special processing is to pass the mode of the MEM to our
3149 elimination_effects (XEXP (x
, 0), GET_MODE (x
));
3156 fmt
= GET_RTX_FORMAT (code
);
3157 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++, fmt
++)
3160 elimination_effects (XEXP (x
, i
), mem_mode
);
3161 else if (*fmt
== 'E')
3162 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
3163 elimination_effects (XVECEXP (x
, i
, j
), mem_mode
);
3167 /* Descend through rtx X and verify that no references to eliminable registers
3168 remain. If any do remain, mark the involved register as not
3172 check_eliminable_occurrences (rtx x
)
3181 code
= GET_CODE (x
);
3183 if (code
== REG
&& REGNO (x
) < FIRST_PSEUDO_REGISTER
)
3185 struct elim_table
*ep
;
3187 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3188 if (ep
->from_rtx
== x
)
3189 ep
->can_eliminate
= 0;
3193 fmt
= GET_RTX_FORMAT (code
);
3194 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++, fmt
++)
3197 check_eliminable_occurrences (XEXP (x
, i
));
3198 else if (*fmt
== 'E')
3201 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
3202 check_eliminable_occurrences (XVECEXP (x
, i
, j
));
3207 /* Scan INSN and eliminate all eliminable registers in it.
3209 If REPLACE is nonzero, do the replacement destructively. Also
3210 delete the insn as dead it if it is setting an eliminable register.
3212 If REPLACE is zero, do all our allocations in reload_obstack.
3214 If no eliminations were done and this insn doesn't require any elimination
3215 processing (these are not identical conditions: it might be updating sp,
3216 but not referencing fp; this needs to be seen during reload_as_needed so
3217 that the offset between fp and sp can be taken into consideration), zero
3218 is returned. Otherwise, 1 is returned. */
3221 eliminate_regs_in_insn (rtx insn
, int replace
)
3223 int icode
= recog_memoized (insn
);
3224 rtx old_body
= PATTERN (insn
);
3225 int insn_is_asm
= asm_noperands (old_body
) >= 0;
3226 rtx old_set
= single_set (insn
);
3230 rtx substed_operand
[MAX_RECOG_OPERANDS
];
3231 rtx orig_operand
[MAX_RECOG_OPERANDS
];
3232 struct elim_table
*ep
;
3233 rtx plus_src
, plus_cst_src
;
3235 if (! insn_is_asm
&& icode
< 0)
3237 gcc_assert (DEBUG_INSN_P (insn
)
3238 || GET_CODE (PATTERN (insn
)) == USE
3239 || GET_CODE (PATTERN (insn
)) == CLOBBER
3240 || GET_CODE (PATTERN (insn
)) == ASM_INPUT
);
3241 if (DEBUG_INSN_P (insn
))
3242 INSN_VAR_LOCATION_LOC (insn
)
3243 = eliminate_regs (INSN_VAR_LOCATION_LOC (insn
), VOIDmode
, insn
);
3247 if (old_set
!= 0 && REG_P (SET_DEST (old_set
))
3248 && REGNO (SET_DEST (old_set
)) < FIRST_PSEUDO_REGISTER
)
3250 /* Check for setting an eliminable register. */
3251 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3252 if (ep
->from_rtx
== SET_DEST (old_set
) && ep
->can_eliminate
)
3254 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
3255 /* If this is setting the frame pointer register to the
3256 hardware frame pointer register and this is an elimination
3257 that will be done (tested above), this insn is really
3258 adjusting the frame pointer downward to compensate for
3259 the adjustment done before a nonlocal goto. */
3260 if (ep
->from
== FRAME_POINTER_REGNUM
3261 && ep
->to
== HARD_FRAME_POINTER_REGNUM
)
3263 rtx base
= SET_SRC (old_set
);
3264 rtx base_insn
= insn
;
3265 HOST_WIDE_INT offset
= 0;
3267 while (base
!= ep
->to_rtx
)
3269 rtx prev_insn
, prev_set
;
3271 if (GET_CODE (base
) == PLUS
3272 && CONST_INT_P (XEXP (base
, 1)))
3274 offset
+= INTVAL (XEXP (base
, 1));
3275 base
= XEXP (base
, 0);
3277 else if ((prev_insn
= prev_nonnote_insn (base_insn
)) != 0
3278 && (prev_set
= single_set (prev_insn
)) != 0
3279 && rtx_equal_p (SET_DEST (prev_set
), base
))
3281 base
= SET_SRC (prev_set
);
3282 base_insn
= prev_insn
;
3288 if (base
== ep
->to_rtx
)
3290 rtx src
= plus_constant (Pmode
, ep
->to_rtx
,
3291 offset
- ep
->offset
);
3293 new_body
= old_body
;
3296 new_body
= copy_insn (old_body
);
3297 if (REG_NOTES (insn
))
3298 REG_NOTES (insn
) = copy_insn_1 (REG_NOTES (insn
));
3300 PATTERN (insn
) = new_body
;
3301 old_set
= single_set (insn
);
3303 /* First see if this insn remains valid when we
3304 make the change. If not, keep the INSN_CODE
3305 the same and let reload fit it up. */
3306 validate_change (insn
, &SET_SRC (old_set
), src
, 1);
3307 validate_change (insn
, &SET_DEST (old_set
),
3309 if (! apply_change_group ())
3311 SET_SRC (old_set
) = src
;
3312 SET_DEST (old_set
) = ep
->to_rtx
;
3321 /* In this case this insn isn't serving a useful purpose. We
3322 will delete it in reload_as_needed once we know that this
3323 elimination is, in fact, being done.
3325 If REPLACE isn't set, we can't delete this insn, but needn't
3326 process it since it won't be used unless something changes. */
3329 delete_dead_insn (insn
);
3337 /* We allow one special case which happens to work on all machines we
3338 currently support: a single set with the source or a REG_EQUAL
3339 note being a PLUS of an eliminable register and a constant. */
3340 plus_src
= plus_cst_src
= 0;
3341 if (old_set
&& REG_P (SET_DEST (old_set
)))
3343 if (GET_CODE (SET_SRC (old_set
)) == PLUS
)
3344 plus_src
= SET_SRC (old_set
);
3345 /* First see if the source is of the form (plus (...) CST). */
3347 && CONST_INT_P (XEXP (plus_src
, 1)))
3348 plus_cst_src
= plus_src
;
3349 else if (REG_P (SET_SRC (old_set
))
3352 /* Otherwise, see if we have a REG_EQUAL note of the form
3353 (plus (...) CST). */
3355 for (links
= REG_NOTES (insn
); links
; links
= XEXP (links
, 1))
3357 if ((REG_NOTE_KIND (links
) == REG_EQUAL
3358 || REG_NOTE_KIND (links
) == REG_EQUIV
)
3359 && GET_CODE (XEXP (links
, 0)) == PLUS
3360 && CONST_INT_P (XEXP (XEXP (links
, 0), 1)))
3362 plus_cst_src
= XEXP (links
, 0);
3368 /* Check that the first operand of the PLUS is a hard reg or
3369 the lowpart subreg of one. */
3372 rtx reg
= XEXP (plus_cst_src
, 0);
3373 if (GET_CODE (reg
) == SUBREG
&& subreg_lowpart_p (reg
))
3374 reg
= SUBREG_REG (reg
);
3376 if (!REG_P (reg
) || REGNO (reg
) >= FIRST_PSEUDO_REGISTER
)
3382 rtx reg
= XEXP (plus_cst_src
, 0);
3383 HOST_WIDE_INT offset
= INTVAL (XEXP (plus_cst_src
, 1));
3385 if (GET_CODE (reg
) == SUBREG
)
3386 reg
= SUBREG_REG (reg
);
3388 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3389 if (ep
->from_rtx
== reg
&& ep
->can_eliminate
)
3391 rtx to_rtx
= ep
->to_rtx
;
3392 offset
+= ep
->offset
;
3393 offset
= trunc_int_for_mode (offset
, GET_MODE (plus_cst_src
));
3395 if (GET_CODE (XEXP (plus_cst_src
, 0)) == SUBREG
)
3396 to_rtx
= gen_lowpart (GET_MODE (XEXP (plus_cst_src
, 0)),
3398 /* If we have a nonzero offset, and the source is already
3399 a simple REG, the following transformation would
3400 increase the cost of the insn by replacing a simple REG
3401 with (plus (reg sp) CST). So try only when we already
3402 had a PLUS before. */
3403 if (offset
== 0 || plus_src
)
3405 rtx new_src
= plus_constant (GET_MODE (to_rtx
),
3408 new_body
= old_body
;
3411 new_body
= copy_insn (old_body
);
3412 if (REG_NOTES (insn
))
3413 REG_NOTES (insn
) = copy_insn_1 (REG_NOTES (insn
));
3415 PATTERN (insn
) = new_body
;
3416 old_set
= single_set (insn
);
3418 /* First see if this insn remains valid when we make the
3419 change. If not, try to replace the whole pattern with
3420 a simple set (this may help if the original insn was a
3421 PARALLEL that was only recognized as single_set due to
3422 REG_UNUSED notes). If this isn't valid either, keep
3423 the INSN_CODE the same and let reload fix it up. */
3424 if (!validate_change (insn
, &SET_SRC (old_set
), new_src
, 0))
3426 rtx new_pat
= gen_rtx_SET (VOIDmode
,
3427 SET_DEST (old_set
), new_src
);
3429 if (!validate_change (insn
, &PATTERN (insn
), new_pat
, 0))
3430 SET_SRC (old_set
) = new_src
;
3437 /* This can't have an effect on elimination offsets, so skip right
3443 /* Determine the effects of this insn on elimination offsets. */
3444 elimination_effects (old_body
, VOIDmode
);
3446 /* Eliminate all eliminable registers occurring in operands that
3447 can be handled by reload. */
3448 extract_insn (insn
);
3449 for (i
= 0; i
< recog_data
.n_operands
; i
++)
3451 orig_operand
[i
] = recog_data
.operand
[i
];
3452 substed_operand
[i
] = recog_data
.operand
[i
];
3454 /* For an asm statement, every operand is eliminable. */
3455 if (insn_is_asm
|| insn_data
[icode
].operand
[i
].eliminable
)
3457 bool is_set_src
, in_plus
;
3459 /* Check for setting a register that we know about. */
3460 if (recog_data
.operand_type
[i
] != OP_IN
3461 && REG_P (orig_operand
[i
]))
3463 /* If we are assigning to a register that can be eliminated, it
3464 must be as part of a PARALLEL, since the code above handles
3465 single SETs. We must indicate that we can no longer
3466 eliminate this reg. */
3467 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
3469 if (ep
->from_rtx
== orig_operand
[i
])
3470 ep
->can_eliminate
= 0;
3473 /* Companion to the above plus substitution, we can allow
3474 invariants as the source of a plain move. */
3477 && recog_data
.operand_loc
[i
] == &SET_SRC (old_set
))
3481 && (recog_data
.operand_loc
[i
] == &XEXP (plus_src
, 0)
3482 || recog_data
.operand_loc
[i
] == &XEXP (plus_src
, 1)))
3486 = eliminate_regs_1 (recog_data
.operand
[i
], VOIDmode
,
3487 replace
? insn
: NULL_RTX
,
3488 is_set_src
|| in_plus
, false);
3489 if (substed_operand
[i
] != orig_operand
[i
])
3491 /* Terminate the search in check_eliminable_occurrences at
3493 *recog_data
.operand_loc
[i
] = 0;
3495 /* If an output operand changed from a REG to a MEM and INSN is an
3496 insn, write a CLOBBER insn. */
3497 if (recog_data
.operand_type
[i
] != OP_IN
3498 && REG_P (orig_operand
[i
])
3499 && MEM_P (substed_operand
[i
])
3501 emit_insn_after (gen_clobber (orig_operand
[i
]), insn
);
3505 for (i
= 0; i
< recog_data
.n_dups
; i
++)
3506 *recog_data
.dup_loc
[i
]
3507 = *recog_data
.operand_loc
[(int) recog_data
.dup_num
[i
]];
3509 /* If any eliminable remain, they aren't eliminable anymore. */
3510 check_eliminable_occurrences (old_body
);
3512 /* Substitute the operands; the new values are in the substed_operand
3514 for (i
= 0; i
< recog_data
.n_operands
; i
++)
3515 *recog_data
.operand_loc
[i
] = substed_operand
[i
];
3516 for (i
= 0; i
< recog_data
.n_dups
; i
++)
3517 *recog_data
.dup_loc
[i
] = substed_operand
[(int) recog_data
.dup_num
[i
]];
3519 /* If we are replacing a body that was a (set X (plus Y Z)), try to
3520 re-recognize the insn. We do this in case we had a simple addition
3521 but now can do this as a load-address. This saves an insn in this
3523 If re-recognition fails, the old insn code number will still be used,
3524 and some register operands may have changed into PLUS expressions.
3525 These will be handled by find_reloads by loading them into a register
3530 /* If we aren't replacing things permanently and we changed something,
3531 make another copy to ensure that all the RTL is new. Otherwise
3532 things can go wrong if find_reload swaps commutative operands
3533 and one is inside RTL that has been copied while the other is not. */
3534 new_body
= old_body
;
3537 new_body
= copy_insn (old_body
);
3538 if (REG_NOTES (insn
))
3539 REG_NOTES (insn
) = copy_insn_1 (REG_NOTES (insn
));
3541 PATTERN (insn
) = new_body
;
3543 /* If we had a move insn but now we don't, rerecognize it. This will
3544 cause spurious re-recognition if the old move had a PARALLEL since
3545 the new one still will, but we can't call single_set without
3546 having put NEW_BODY into the insn and the re-recognition won't
3547 hurt in this rare case. */
3548 /* ??? Why this huge if statement - why don't we just rerecognize the
3552 && ((REG_P (SET_SRC (old_set
))
3553 && (GET_CODE (new_body
) != SET
3554 || !REG_P (SET_SRC (new_body
))))
3555 /* If this was a load from or store to memory, compare
3556 the MEM in recog_data.operand to the one in the insn.
3557 If they are not equal, then rerecognize the insn. */
3559 && ((MEM_P (SET_SRC (old_set
))
3560 && SET_SRC (old_set
) != recog_data
.operand
[1])
3561 || (MEM_P (SET_DEST (old_set
))
3562 && SET_DEST (old_set
) != recog_data
.operand
[0])))
3563 /* If this was an add insn before, rerecognize. */
3564 || GET_CODE (SET_SRC (old_set
)) == PLUS
))
3566 int new_icode
= recog (PATTERN (insn
), insn
, 0);
3568 INSN_CODE (insn
) = new_icode
;
3572 /* Restore the old body. If there were any changes to it, we made a copy
3573 of it while the changes were still in place, so we'll correctly return
3574 a modified insn below. */
3577 /* Restore the old body. */
3578 for (i
= 0; i
< recog_data
.n_operands
; i
++)
3579 /* Restoring a top-level match_parallel would clobber the new_body
3580 we installed in the insn. */
3581 if (recog_data
.operand_loc
[i
] != &PATTERN (insn
))
3582 *recog_data
.operand_loc
[i
] = orig_operand
[i
];
3583 for (i
= 0; i
< recog_data
.n_dups
; i
++)
3584 *recog_data
.dup_loc
[i
] = orig_operand
[(int) recog_data
.dup_num
[i
]];
3587 /* Update all elimination pairs to reflect the status after the current
3588 insn. The changes we make were determined by the earlier call to
3589 elimination_effects.
3591 We also detect cases where register elimination cannot be done,
3592 namely, if a register would be both changed and referenced outside a MEM
3593 in the resulting insn since such an insn is often undefined and, even if
3594 not, we cannot know what meaning will be given to it. Note that it is
3595 valid to have a register used in an address in an insn that changes it
3596 (presumably with a pre- or post-increment or decrement).
3598 If anything changes, return nonzero. */
3600 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3602 if (ep
->previous_offset
!= ep
->offset
&& ep
->ref_outside_mem
)
3603 ep
->can_eliminate
= 0;
3605 ep
->ref_outside_mem
= 0;
3607 if (ep
->previous_offset
!= ep
->offset
)
3612 /* If we changed something, perform elimination in REG_NOTES. This is
3613 needed even when REPLACE is zero because a REG_DEAD note might refer
3614 to a register that we eliminate and could cause a different number
3615 of spill registers to be needed in the final reload pass than in
3617 if (val
&& REG_NOTES (insn
) != 0)
3619 = eliminate_regs_1 (REG_NOTES (insn
), VOIDmode
, REG_NOTES (insn
), true,
3625 /* Like eliminate_regs_in_insn, but only estimate costs for the use of the
3626 register allocator. INSN is the instruction we need to examine, we perform
3627 eliminations in its operands and record cases where eliminating a reg with
3628 an invariant equivalence would add extra cost. */
3631 elimination_costs_in_insn (rtx insn
)
3633 int icode
= recog_memoized (insn
);
3634 rtx old_body
= PATTERN (insn
);
3635 int insn_is_asm
= asm_noperands (old_body
) >= 0;
3636 rtx old_set
= single_set (insn
);
3638 rtx orig_operand
[MAX_RECOG_OPERANDS
];
3639 rtx orig_dup
[MAX_RECOG_OPERANDS
];
3640 struct elim_table
*ep
;
3641 rtx plus_src
, plus_cst_src
;
3644 if (! insn_is_asm
&& icode
< 0)
3646 gcc_assert (DEBUG_INSN_P (insn
)
3647 || GET_CODE (PATTERN (insn
)) == USE
3648 || GET_CODE (PATTERN (insn
)) == CLOBBER
3649 || GET_CODE (PATTERN (insn
)) == ASM_INPUT
);
3653 if (old_set
!= 0 && REG_P (SET_DEST (old_set
))
3654 && REGNO (SET_DEST (old_set
)) < FIRST_PSEUDO_REGISTER
)
3656 /* Check for setting an eliminable register. */
3657 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3658 if (ep
->from_rtx
== SET_DEST (old_set
) && ep
->can_eliminate
)
3662 /* We allow one special case which happens to work on all machines we
3663 currently support: a single set with the source or a REG_EQUAL
3664 note being a PLUS of an eliminable register and a constant. */
3665 plus_src
= plus_cst_src
= 0;
3667 if (old_set
&& REG_P (SET_DEST (old_set
)))
3670 if (GET_CODE (SET_SRC (old_set
)) == PLUS
)
3671 plus_src
= SET_SRC (old_set
);
3672 /* First see if the source is of the form (plus (...) CST). */
3674 && CONST_INT_P (XEXP (plus_src
, 1)))
3675 plus_cst_src
= plus_src
;
3676 else if (REG_P (SET_SRC (old_set
))
3679 /* Otherwise, see if we have a REG_EQUAL note of the form
3680 (plus (...) CST). */
3682 for (links
= REG_NOTES (insn
); links
; links
= XEXP (links
, 1))
3684 if ((REG_NOTE_KIND (links
) == REG_EQUAL
3685 || REG_NOTE_KIND (links
) == REG_EQUIV
)
3686 && GET_CODE (XEXP (links
, 0)) == PLUS
3687 && CONST_INT_P (XEXP (XEXP (links
, 0), 1)))
3689 plus_cst_src
= XEXP (links
, 0);
3696 /* Determine the effects of this insn on elimination offsets. */
3697 elimination_effects (old_body
, VOIDmode
);
3699 /* Eliminate all eliminable registers occurring in operands that
3700 can be handled by reload. */
3701 extract_insn (insn
);
3702 for (i
= 0; i
< recog_data
.n_dups
; i
++)
3703 orig_dup
[i
] = *recog_data
.dup_loc
[i
];
3705 for (i
= 0; i
< recog_data
.n_operands
; i
++)
3707 orig_operand
[i
] = recog_data
.operand
[i
];
3709 /* For an asm statement, every operand is eliminable. */
3710 if (insn_is_asm
|| insn_data
[icode
].operand
[i
].eliminable
)
3712 bool is_set_src
, in_plus
;
3714 /* Check for setting a register that we know about. */
3715 if (recog_data
.operand_type
[i
] != OP_IN
3716 && REG_P (orig_operand
[i
]))
3718 /* If we are assigning to a register that can be eliminated, it
3719 must be as part of a PARALLEL, since the code above handles
3720 single SETs. We must indicate that we can no longer
3721 eliminate this reg. */
3722 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
3724 if (ep
->from_rtx
== orig_operand
[i
])
3725 ep
->can_eliminate
= 0;
3728 /* Companion to the above plus substitution, we can allow
3729 invariants as the source of a plain move. */
3731 if (old_set
&& recog_data
.operand_loc
[i
] == &SET_SRC (old_set
))
3733 if (is_set_src
&& !sets_reg_p
)
3734 note_reg_elim_costly (&SET_SRC (old_set
), insn
);
3736 if (plus_src
&& sets_reg_p
3737 && (recog_data
.operand_loc
[i
] == &XEXP (plus_src
, 0)
3738 || recog_data
.operand_loc
[i
] == &XEXP (plus_src
, 1)))
3741 eliminate_regs_1 (recog_data
.operand
[i
], VOIDmode
,
3743 is_set_src
|| in_plus
, true);
3744 /* Terminate the search in check_eliminable_occurrences at
3746 *recog_data
.operand_loc
[i
] = 0;
3750 for (i
= 0; i
< recog_data
.n_dups
; i
++)
3751 *recog_data
.dup_loc
[i
]
3752 = *recog_data
.operand_loc
[(int) recog_data
.dup_num
[i
]];
3754 /* If any eliminable remain, they aren't eliminable anymore. */
3755 check_eliminable_occurrences (old_body
);
3757 /* Restore the old body. */
3758 for (i
= 0; i
< recog_data
.n_operands
; i
++)
3759 *recog_data
.operand_loc
[i
] = orig_operand
[i
];
3760 for (i
= 0; i
< recog_data
.n_dups
; i
++)
3761 *recog_data
.dup_loc
[i
] = orig_dup
[i
];
3763 /* Update all elimination pairs to reflect the status after the current
3764 insn. The changes we make were determined by the earlier call to
3765 elimination_effects. */
3767 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3769 if (ep
->previous_offset
!= ep
->offset
&& ep
->ref_outside_mem
)
3770 ep
->can_eliminate
= 0;
3772 ep
->ref_outside_mem
= 0;
3778 /* Loop through all elimination pairs.
3779 Recalculate the number not at initial offset.
3781 Compute the maximum offset (minimum offset if the stack does not
3782 grow downward) for each elimination pair. */
3785 update_eliminable_offsets (void)
3787 struct elim_table
*ep
;
3789 num_not_at_initial_offset
= 0;
3790 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3792 ep
->previous_offset
= ep
->offset
;
3793 if (ep
->can_eliminate
&& ep
->offset
!= ep
->initial_offset
)
3794 num_not_at_initial_offset
++;
3798 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3799 replacement we currently believe is valid, mark it as not eliminable if X
3800 modifies DEST in any way other than by adding a constant integer to it.
3802 If DEST is the frame pointer, we do nothing because we assume that
3803 all assignments to the hard frame pointer are nonlocal gotos and are being
3804 done at a time when they are valid and do not disturb anything else.
3805 Some machines want to eliminate a fake argument pointer with either the
3806 frame or stack pointer. Assignments to the hard frame pointer must not
3807 prevent this elimination.
3809 Called via note_stores from reload before starting its passes to scan
3810 the insns of the function. */
3813 mark_not_eliminable (rtx dest
, const_rtx x
, void *data ATTRIBUTE_UNUSED
)
3817 /* A SUBREG of a hard register here is just changing its mode. We should
3818 not see a SUBREG of an eliminable hard register, but check just in
3820 if (GET_CODE (dest
) == SUBREG
)
3821 dest
= SUBREG_REG (dest
);
3823 if (dest
== hard_frame_pointer_rtx
)
3826 for (i
= 0; i
< NUM_ELIMINABLE_REGS
; i
++)
3827 if (reg_eliminate
[i
].can_eliminate
&& dest
== reg_eliminate
[i
].to_rtx
3828 && (GET_CODE (x
) != SET
3829 || GET_CODE (SET_SRC (x
)) != PLUS
3830 || XEXP (SET_SRC (x
), 0) != dest
3831 || !CONST_INT_P (XEXP (SET_SRC (x
), 1))))
3833 reg_eliminate
[i
].can_eliminate_previous
3834 = reg_eliminate
[i
].can_eliminate
= 0;
3839 /* Verify that the initial elimination offsets did not change since the
3840 last call to set_initial_elim_offsets. This is used to catch cases
3841 where something illegal happened during reload_as_needed that could
3842 cause incorrect code to be generated if we did not check for it. */
3845 verify_initial_elim_offsets (void)
3849 if (!num_eliminable
)
3852 #ifdef ELIMINABLE_REGS
3854 struct elim_table
*ep
;
3856 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3858 INITIAL_ELIMINATION_OFFSET (ep
->from
, ep
->to
, t
);
3859 if (t
!= ep
->initial_offset
)
3864 INITIAL_FRAME_POINTER_OFFSET (t
);
3865 if (t
!= reg_eliminate
[0].initial_offset
)
3872 /* Reset all offsets on eliminable registers to their initial values. */
3875 set_initial_elim_offsets (void)
3877 struct elim_table
*ep
= reg_eliminate
;
3879 #ifdef ELIMINABLE_REGS
3880 for (; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3882 INITIAL_ELIMINATION_OFFSET (ep
->from
, ep
->to
, ep
->initial_offset
);
3883 ep
->previous_offset
= ep
->offset
= ep
->initial_offset
;
3886 INITIAL_FRAME_POINTER_OFFSET (ep
->initial_offset
);
3887 ep
->previous_offset
= ep
->offset
= ep
->initial_offset
;
3890 num_not_at_initial_offset
= 0;
3893 /* Subroutine of set_initial_label_offsets called via for_each_eh_label. */
3896 set_initial_eh_label_offset (rtx label
)
3898 set_label_offsets (label
, NULL_RTX
, 1);
3901 /* Initialize the known label offsets.
3902 Set a known offset for each forced label to be at the initial offset
3903 of each elimination. We do this because we assume that all
3904 computed jumps occur from a location where each elimination is
3905 at its initial offset.
3906 For all other labels, show that we don't know the offsets. */
3909 set_initial_label_offsets (void)
3912 memset (offsets_known_at
, 0, num_labels
);
3914 for (x
= forced_labels
; x
; x
= XEXP (x
, 1))
3916 set_label_offsets (XEXP (x
, 0), NULL_RTX
, 1);
3918 for (x
= nonlocal_goto_handler_labels
; x
; x
= XEXP (x
, 1))
3920 set_label_offsets (XEXP (x
, 0), NULL_RTX
, 1);
3922 for_each_eh_label (set_initial_eh_label_offset
);
3925 /* Set all elimination offsets to the known values for the code label given
3929 set_offsets_for_label (rtx insn
)
3932 int label_nr
= CODE_LABEL_NUMBER (insn
);
3933 struct elim_table
*ep
;
3935 num_not_at_initial_offset
= 0;
3936 for (i
= 0, ep
= reg_eliminate
; i
< NUM_ELIMINABLE_REGS
; ep
++, i
++)
3938 ep
->offset
= ep
->previous_offset
3939 = offsets_at
[label_nr
- first_label_num
][i
];
3940 if (ep
->can_eliminate
&& ep
->offset
!= ep
->initial_offset
)
3941 num_not_at_initial_offset
++;
3945 /* See if anything that happened changes which eliminations are valid.
3946 For example, on the SPARC, whether or not the frame pointer can
3947 be eliminated can depend on what registers have been used. We need
3948 not check some conditions again (such as flag_omit_frame_pointer)
3949 since they can't have changed. */
3952 update_eliminables (HARD_REG_SET
*pset
)
3954 int previous_frame_pointer_needed
= frame_pointer_needed
;
3955 struct elim_table
*ep
;
3957 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3958 if ((ep
->from
== HARD_FRAME_POINTER_REGNUM
3959 && targetm
.frame_pointer_required ())
3960 #ifdef ELIMINABLE_REGS
3961 || ! targetm
.can_eliminate (ep
->from
, ep
->to
)
3964 ep
->can_eliminate
= 0;
3966 /* Look for the case where we have discovered that we can't replace
3967 register A with register B and that means that we will now be
3968 trying to replace register A with register C. This means we can
3969 no longer replace register C with register B and we need to disable
3970 such an elimination, if it exists. This occurs often with A == ap,
3971 B == sp, and C == fp. */
3973 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3975 struct elim_table
*op
;
3978 if (! ep
->can_eliminate
&& ep
->can_eliminate_previous
)
3980 /* Find the current elimination for ep->from, if there is a
3982 for (op
= reg_eliminate
;
3983 op
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; op
++)
3984 if (op
->from
== ep
->from
&& op
->can_eliminate
)
3990 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
3992 for (op
= reg_eliminate
;
3993 op
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; op
++)
3994 if (op
->from
== new_to
&& op
->to
== ep
->to
)
3995 op
->can_eliminate
= 0;
3999 /* See if any registers that we thought we could eliminate the previous
4000 time are no longer eliminable. If so, something has changed and we
4001 must spill the register. Also, recompute the number of eliminable
4002 registers and see if the frame pointer is needed; it is if there is
4003 no elimination of the frame pointer that we can perform. */
4005 frame_pointer_needed
= 1;
4006 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
4008 if (ep
->can_eliminate
4009 && ep
->from
== FRAME_POINTER_REGNUM
4010 && ep
->to
!= HARD_FRAME_POINTER_REGNUM
4011 && (! SUPPORTS_STACK_ALIGNMENT
4012 || ! crtl
->stack_realign_needed
))
4013 frame_pointer_needed
= 0;
4015 if (! ep
->can_eliminate
&& ep
->can_eliminate_previous
)
4017 ep
->can_eliminate_previous
= 0;
4018 SET_HARD_REG_BIT (*pset
, ep
->from
);
4023 /* If we didn't need a frame pointer last time, but we do now, spill
4024 the hard frame pointer. */
4025 if (frame_pointer_needed
&& ! previous_frame_pointer_needed
)
4026 SET_HARD_REG_BIT (*pset
, HARD_FRAME_POINTER_REGNUM
);
4029 /* Call update_eliminables an spill any registers we can't eliminate anymore.
4030 Return true iff a register was spilled. */
4033 update_eliminables_and_spill (void)
4036 bool did_spill
= false;
4037 HARD_REG_SET to_spill
;
4038 CLEAR_HARD_REG_SET (to_spill
);
4039 update_eliminables (&to_spill
);
4040 AND_COMPL_HARD_REG_SET (used_spill_regs
, to_spill
);
4042 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
4043 if (TEST_HARD_REG_BIT (to_spill
, i
))
4045 spill_hard_reg (i
, 1);
4048 /* Regardless of the state of spills, if we previously had
4049 a register that we thought we could eliminate, but now can
4050 not eliminate, we must run another pass.
4052 Consider pseudos which have an entry in reg_equiv_* which
4053 reference an eliminable register. We must make another pass
4054 to update reg_equiv_* so that we do not substitute in the
4055 old value from when we thought the elimination could be
4061 /* Return true if X is used as the target register of an elimination. */
4064 elimination_target_reg_p (rtx x
)
4066 struct elim_table
*ep
;
4068 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
4069 if (ep
->to_rtx
== x
&& ep
->can_eliminate
)
4075 /* Initialize the table of registers to eliminate.
4076 Pre-condition: global flag frame_pointer_needed has been set before
4077 calling this function. */
4080 init_elim_table (void)
4082 struct elim_table
*ep
;
4083 #ifdef ELIMINABLE_REGS
4084 const struct elim_table_1
*ep1
;
4088 reg_eliminate
= XCNEWVEC (struct elim_table
, NUM_ELIMINABLE_REGS
);
4092 #ifdef ELIMINABLE_REGS
4093 for (ep
= reg_eliminate
, ep1
= reg_eliminate_1
;
4094 ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++, ep1
++)
4096 ep
->from
= ep1
->from
;
4098 ep
->can_eliminate
= ep
->can_eliminate_previous
4099 = (targetm
.can_eliminate (ep
->from
, ep
->to
)
4100 && ! (ep
->to
== STACK_POINTER_REGNUM
4101 && frame_pointer_needed
4102 && (! SUPPORTS_STACK_ALIGNMENT
4103 || ! stack_realign_fp
)));
4106 reg_eliminate
[0].from
= reg_eliminate_1
[0].from
;
4107 reg_eliminate
[0].to
= reg_eliminate_1
[0].to
;
4108 reg_eliminate
[0].can_eliminate
= reg_eliminate
[0].can_eliminate_previous
4109 = ! frame_pointer_needed
;
4112 /* Count the number of eliminable registers and build the FROM and TO
4113 REG rtx's. Note that code in gen_rtx_REG will cause, e.g.,
4114 gen_rtx_REG (Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
4115 We depend on this. */
4116 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
4118 num_eliminable
+= ep
->can_eliminate
;
4119 ep
->from_rtx
= gen_rtx_REG (Pmode
, ep
->from
);
4120 ep
->to_rtx
= gen_rtx_REG (Pmode
, ep
->to
);
4124 /* Find all the pseudo registers that didn't get hard regs
4125 but do have known equivalent constants or memory slots.
4126 These include parameters (known equivalent to parameter slots)
4127 and cse'd or loop-moved constant memory addresses.
4129 Record constant equivalents in reg_equiv_constant
4130 so they will be substituted by find_reloads.
4131 Record memory equivalents in reg_mem_equiv so they can
4132 be substituted eventually by altering the REG-rtx's. */
4135 init_eliminable_invariants (rtx first
, bool do_subregs
)
4142 reg_max_ref_width
= XCNEWVEC (unsigned int, max_regno
);
4144 reg_max_ref_width
= NULL
;
4146 num_eliminable_invariants
= 0;
4148 first_label_num
= get_first_label_num ();
4149 num_labels
= max_label_num () - first_label_num
;
4151 /* Allocate the tables used to store offset information at labels. */
4152 offsets_known_at
= XNEWVEC (char, num_labels
);
4153 offsets_at
= (HOST_WIDE_INT (*)[NUM_ELIMINABLE_REGS
]) xmalloc (num_labels
* NUM_ELIMINABLE_REGS
* sizeof (HOST_WIDE_INT
));
4155 /* Look for REG_EQUIV notes; record what each pseudo is equivalent
4156 to. If DO_SUBREGS is true, also find all paradoxical subregs and
4157 find largest such for each pseudo. FIRST is the head of the insn
4160 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
4162 rtx set
= single_set (insn
);
4164 /* We may introduce USEs that we want to remove at the end, so
4165 we'll mark them with QImode. Make sure there are no
4166 previously-marked insns left by say regmove. */
4167 if (INSN_P (insn
) && GET_CODE (PATTERN (insn
)) == USE
4168 && GET_MODE (insn
) != VOIDmode
)
4169 PUT_MODE (insn
, VOIDmode
);
4171 if (do_subregs
&& NONDEBUG_INSN_P (insn
))
4172 scan_paradoxical_subregs (PATTERN (insn
));
4174 if (set
!= 0 && REG_P (SET_DEST (set
)))
4176 rtx note
= find_reg_note (insn
, REG_EQUIV
, NULL_RTX
);
4182 i
= REGNO (SET_DEST (set
));
4185 if (i
<= LAST_VIRTUAL_REGISTER
)
4188 /* If flag_pic and we have constant, verify it's legitimate. */
4190 || !flag_pic
|| LEGITIMATE_PIC_OPERAND_P (x
))
4192 /* It can happen that a REG_EQUIV note contains a MEM
4193 that is not a legitimate memory operand. As later
4194 stages of reload assume that all addresses found
4195 in the reg_equiv_* arrays were originally legitimate,
4196 we ignore such REG_EQUIV notes. */
4197 if (memory_operand (x
, VOIDmode
))
4199 /* Always unshare the equivalence, so we can
4200 substitute into this insn without touching the
4202 reg_equiv_memory_loc (i
) = copy_rtx (x
);
4204 else if (function_invariant_p (x
))
4206 enum machine_mode mode
;
4208 mode
= GET_MODE (SET_DEST (set
));
4209 if (GET_CODE (x
) == PLUS
)
4211 /* This is PLUS of frame pointer and a constant,
4212 and might be shared. Unshare it. */
4213 reg_equiv_invariant (i
) = copy_rtx (x
);
4214 num_eliminable_invariants
++;
4216 else if (x
== frame_pointer_rtx
|| x
== arg_pointer_rtx
)
4218 reg_equiv_invariant (i
) = x
;
4219 num_eliminable_invariants
++;
4221 else if (targetm
.legitimate_constant_p (mode
, x
))
4222 reg_equiv_constant (i
) = x
;
4225 reg_equiv_memory_loc (i
) = force_const_mem (mode
, x
);
4226 if (! reg_equiv_memory_loc (i
))
4227 reg_equiv_init (i
) = NULL_RTX
;
4232 reg_equiv_init (i
) = NULL_RTX
;
4237 reg_equiv_init (i
) = NULL_RTX
;
4242 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
4243 if (reg_equiv_init (i
))
4245 fprintf (dump_file
, "init_insns for %u: ", i
);
4246 print_inline_rtx (dump_file
, reg_equiv_init (i
), 20);
4247 fprintf (dump_file
, "\n");
4251 /* Indicate that we no longer have known memory locations or constants.
4252 Free all data involved in tracking these. */
4255 free_reg_equiv (void)
4259 free (offsets_known_at
);
4262 offsets_known_at
= 0;
4264 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
4265 if (reg_equiv_alt_mem_list (i
))
4266 free_EXPR_LIST_list (®_equiv_alt_mem_list (i
));
4267 vec_free (reg_equivs
);
4270 /* Kick all pseudos out of hard register REGNO.
4272 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
4273 because we found we can't eliminate some register. In the case, no pseudos
4274 are allowed to be in the register, even if they are only in a block that
4275 doesn't require spill registers, unlike the case when we are spilling this
4276 hard reg to produce another spill register.
4278 Return nonzero if any pseudos needed to be kicked out. */
4281 spill_hard_reg (unsigned int regno
, int cant_eliminate
)
4287 SET_HARD_REG_BIT (bad_spill_regs_global
, regno
);
4288 df_set_regs_ever_live (regno
, true);
4291 /* Spill every pseudo reg that was allocated to this reg
4292 or to something that overlaps this reg. */
4294 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
4295 if (reg_renumber
[i
] >= 0
4296 && (unsigned int) reg_renumber
[i
] <= regno
4297 && end_hard_regno (PSEUDO_REGNO_MODE (i
), reg_renumber
[i
]) > regno
)
4298 SET_REGNO_REG_SET (&spilled_pseudos
, i
);
4301 /* After find_reload_regs has been run for all insn that need reloads,
4302 and/or spill_hard_regs was called, this function is used to actually
4303 spill pseudo registers and try to reallocate them. It also sets up the
4304 spill_regs array for use by choose_reload_regs. */
4307 finish_spills (int global
)
4309 struct insn_chain
*chain
;
4310 int something_changed
= 0;
4312 reg_set_iterator rsi
;
4314 /* Build the spill_regs array for the function. */
4315 /* If there are some registers still to eliminate and one of the spill regs
4316 wasn't ever used before, additional stack space may have to be
4317 allocated to store this register. Thus, we may have changed the offset
4318 between the stack and frame pointers, so mark that something has changed.
4320 One might think that we need only set VAL to 1 if this is a call-used
4321 register. However, the set of registers that must be saved by the
4322 prologue is not identical to the call-used set. For example, the
4323 register used by the call insn for the return PC is a call-used register,
4324 but must be saved by the prologue. */
4327 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
4328 if (TEST_HARD_REG_BIT (used_spill_regs
, i
))
4330 spill_reg_order
[i
] = n_spills
;
4331 spill_regs
[n_spills
++] = i
;
4332 if (num_eliminable
&& ! df_regs_ever_live_p (i
))
4333 something_changed
= 1;
4334 df_set_regs_ever_live (i
, true);
4337 spill_reg_order
[i
] = -1;
4339 EXECUTE_IF_SET_IN_REG_SET (&spilled_pseudos
, FIRST_PSEUDO_REGISTER
, i
, rsi
)
4340 if (! ira_conflicts_p
|| reg_renumber
[i
] >= 0)
4342 /* Record the current hard register the pseudo is allocated to
4343 in pseudo_previous_regs so we avoid reallocating it to the
4344 same hard reg in a later pass. */
4345 gcc_assert (reg_renumber
[i
] >= 0);
4347 SET_HARD_REG_BIT (pseudo_previous_regs
[i
], reg_renumber
[i
]);
4348 /* Mark it as no longer having a hard register home. */
4349 reg_renumber
[i
] = -1;
4350 if (ira_conflicts_p
)
4351 /* Inform IRA about the change. */
4352 ira_mark_allocation_change (i
);
4353 /* We will need to scan everything again. */
4354 something_changed
= 1;
4357 /* Retry global register allocation if possible. */
4358 if (global
&& ira_conflicts_p
)
4362 memset (pseudo_forbidden_regs
, 0, max_regno
* sizeof (HARD_REG_SET
));
4363 /* For every insn that needs reloads, set the registers used as spill
4364 regs in pseudo_forbidden_regs for every pseudo live across the
4366 for (chain
= insns_need_reload
; chain
; chain
= chain
->next_need_reload
)
4368 EXECUTE_IF_SET_IN_REG_SET
4369 (&chain
->live_throughout
, FIRST_PSEUDO_REGISTER
, i
, rsi
)
4371 IOR_HARD_REG_SET (pseudo_forbidden_regs
[i
],
4372 chain
->used_spill_regs
);
4374 EXECUTE_IF_SET_IN_REG_SET
4375 (&chain
->dead_or_set
, FIRST_PSEUDO_REGISTER
, i
, rsi
)
4377 IOR_HARD_REG_SET (pseudo_forbidden_regs
[i
],
4378 chain
->used_spill_regs
);
4382 /* Retry allocating the pseudos spilled in IRA and the
4383 reload. For each reg, merge the various reg sets that
4384 indicate which hard regs can't be used, and call
4385 ira_reassign_pseudos. */
4386 for (n
= 0, i
= FIRST_PSEUDO_REGISTER
; i
< (unsigned) max_regno
; i
++)
4387 if (reg_old_renumber
[i
] != reg_renumber
[i
])
4389 if (reg_renumber
[i
] < 0)
4390 temp_pseudo_reg_arr
[n
++] = i
;
4392 CLEAR_REGNO_REG_SET (&spilled_pseudos
, i
);
4394 if (ira_reassign_pseudos (temp_pseudo_reg_arr
, n
,
4395 bad_spill_regs_global
,
4396 pseudo_forbidden_regs
, pseudo_previous_regs
,
4398 something_changed
= 1;
4400 /* Fix up the register information in the insn chain.
4401 This involves deleting those of the spilled pseudos which did not get
4402 a new hard register home from the live_{before,after} sets. */
4403 for (chain
= reload_insn_chain
; chain
; chain
= chain
->next
)
4405 HARD_REG_SET used_by_pseudos
;
4406 HARD_REG_SET used_by_pseudos2
;
4408 if (! ira_conflicts_p
)
4410 /* Don't do it for IRA because IRA and the reload still can
4411 assign hard registers to the spilled pseudos on next
4412 reload iterations. */
4413 AND_COMPL_REG_SET (&chain
->live_throughout
, &spilled_pseudos
);
4414 AND_COMPL_REG_SET (&chain
->dead_or_set
, &spilled_pseudos
);
4416 /* Mark any unallocated hard regs as available for spills. That
4417 makes inheritance work somewhat better. */
4418 if (chain
->need_reload
)
4420 REG_SET_TO_HARD_REG_SET (used_by_pseudos
, &chain
->live_throughout
);
4421 REG_SET_TO_HARD_REG_SET (used_by_pseudos2
, &chain
->dead_or_set
);
4422 IOR_HARD_REG_SET (used_by_pseudos
, used_by_pseudos2
);
4424 compute_use_by_pseudos (&used_by_pseudos
, &chain
->live_throughout
);
4425 compute_use_by_pseudos (&used_by_pseudos
, &chain
->dead_or_set
);
4426 /* Value of chain->used_spill_regs from previous iteration
4427 may be not included in the value calculated here because
4428 of possible removing caller-saves insns (see function
4429 delete_caller_save_insns. */
4430 COMPL_HARD_REG_SET (chain
->used_spill_regs
, used_by_pseudos
);
4431 AND_HARD_REG_SET (chain
->used_spill_regs
, used_spill_regs
);
4435 CLEAR_REG_SET (&changed_allocation_pseudos
);
4436 /* Let alter_reg modify the reg rtx's for the modified pseudos. */
4437 for (i
= FIRST_PSEUDO_REGISTER
; i
< (unsigned)max_regno
; i
++)
4439 int regno
= reg_renumber
[i
];
4440 if (reg_old_renumber
[i
] == regno
)
4443 SET_REGNO_REG_SET (&changed_allocation_pseudos
, i
);
4445 alter_reg (i
, reg_old_renumber
[i
], false);
4446 reg_old_renumber
[i
] = regno
;
4450 fprintf (dump_file
, " Register %d now on stack.\n\n", i
);
4452 fprintf (dump_file
, " Register %d now in %d.\n\n",
4453 i
, reg_renumber
[i
]);
4457 return something_changed
;
4460 /* Find all paradoxical subregs within X and update reg_max_ref_width. */
4463 scan_paradoxical_subregs (rtx x
)
4467 enum rtx_code code
= GET_CODE (x
);
4483 if (REG_P (SUBREG_REG (x
))
4484 && (GET_MODE_SIZE (GET_MODE (x
))
4485 > reg_max_ref_width
[REGNO (SUBREG_REG (x
))]))
4487 reg_max_ref_width
[REGNO (SUBREG_REG (x
))]
4488 = GET_MODE_SIZE (GET_MODE (x
));
4489 mark_home_live_1 (REGNO (SUBREG_REG (x
)), GET_MODE (x
));
4497 fmt
= GET_RTX_FORMAT (code
);
4498 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
4501 scan_paradoxical_subregs (XEXP (x
, i
));
4502 else if (fmt
[i
] == 'E')
4505 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
4506 scan_paradoxical_subregs (XVECEXP (x
, i
, j
));
4511 /* *OP_PTR and *OTHER_PTR are two operands to a conceptual reload.
4512 If *OP_PTR is a paradoxical subreg, try to remove that subreg
4513 and apply the corresponding narrowing subreg to *OTHER_PTR.
4514 Return true if the operands were changed, false otherwise. */
4517 strip_paradoxical_subreg (rtx
*op_ptr
, rtx
*other_ptr
)
4519 rtx op
, inner
, other
, tem
;
4522 if (!paradoxical_subreg_p (op
))
4524 inner
= SUBREG_REG (op
);
4527 tem
= gen_lowpart_common (GET_MODE (inner
), other
);
4531 /* If the lowpart operation turned a hard register into a subreg,
4532 rather than simplifying it to another hard register, then the
4533 mode change cannot be properly represented. For example, OTHER
4534 might be valid in its current mode, but not in the new one. */
4535 if (GET_CODE (tem
) == SUBREG
4537 && HARD_REGISTER_P (other
))
4545 /* A subroutine of reload_as_needed. If INSN has a REG_EH_REGION note,
4546 examine all of the reload insns between PREV and NEXT exclusive, and
4547 annotate all that may trap. */
4550 fixup_eh_region_note (rtx insn
, rtx prev
, rtx next
)
4552 rtx note
= find_reg_note (insn
, REG_EH_REGION
, NULL_RTX
);
4555 if (!insn_could_throw_p (insn
))
4556 remove_note (insn
, note
);
4557 copy_reg_eh_region_note_forward (note
, NEXT_INSN (prev
), next
);
4560 /* Reload pseudo-registers into hard regs around each insn as needed.
4561 Additional register load insns are output before the insn that needs it
4562 and perhaps store insns after insns that modify the reloaded pseudo reg.
4564 reg_last_reload_reg and reg_reloaded_contents keep track of
4565 which registers are already available in reload registers.
4566 We update these for the reloads that we perform,
4567 as the insns are scanned. */
4570 reload_as_needed (int live_known
)
4572 struct insn_chain
*chain
;
4573 #if defined (AUTO_INC_DEC)
4579 memset (spill_reg_rtx
, 0, sizeof spill_reg_rtx
);
4580 memset (spill_reg_store
, 0, sizeof spill_reg_store
);
4581 reg_last_reload_reg
= XCNEWVEC (rtx
, max_regno
);
4582 INIT_REG_SET (®_has_output_reload
);
4583 CLEAR_HARD_REG_SET (reg_reloaded_valid
);
4584 CLEAR_HARD_REG_SET (reg_reloaded_call_part_clobbered
);
4586 set_initial_elim_offsets ();
4588 /* Generate a marker insn that we will move around. */
4589 marker
= emit_note (NOTE_INSN_DELETED
);
4590 unlink_insn_chain (marker
, marker
);
4592 for (chain
= reload_insn_chain
; chain
; chain
= chain
->next
)
4595 rtx insn
= chain
->insn
;
4596 rtx old_next
= NEXT_INSN (insn
);
4598 rtx old_prev
= PREV_INSN (insn
);
4601 if (will_delete_init_insn_p (insn
))
4604 /* If we pass a label, copy the offsets from the label information
4605 into the current offsets of each elimination. */
4607 set_offsets_for_label (insn
);
4609 else if (INSN_P (insn
))
4611 regset_head regs_to_forget
;
4612 INIT_REG_SET (®s_to_forget
);
4613 note_stores (PATTERN (insn
), forget_old_reloads_1
, ®s_to_forget
);
4615 /* If this is a USE and CLOBBER of a MEM, ensure that any
4616 references to eliminable registers have been removed. */
4618 if ((GET_CODE (PATTERN (insn
)) == USE
4619 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
4620 && MEM_P (XEXP (PATTERN (insn
), 0)))
4621 XEXP (XEXP (PATTERN (insn
), 0), 0)
4622 = eliminate_regs (XEXP (XEXP (PATTERN (insn
), 0), 0),
4623 GET_MODE (XEXP (PATTERN (insn
), 0)),
4626 /* If we need to do register elimination processing, do so.
4627 This might delete the insn, in which case we are done. */
4628 if ((num_eliminable
|| num_eliminable_invariants
) && chain
->need_elim
)
4630 eliminate_regs_in_insn (insn
, 1);
4633 update_eliminable_offsets ();
4634 CLEAR_REG_SET (®s_to_forget
);
4639 /* If need_elim is nonzero but need_reload is zero, one might think
4640 that we could simply set n_reloads to 0. However, find_reloads
4641 could have done some manipulation of the insn (such as swapping
4642 commutative operands), and these manipulations are lost during
4643 the first pass for every insn that needs register elimination.
4644 So the actions of find_reloads must be redone here. */
4646 if (! chain
->need_elim
&& ! chain
->need_reload
4647 && ! chain
->need_operand_change
)
4649 /* First find the pseudo regs that must be reloaded for this insn.
4650 This info is returned in the tables reload_... (see reload.h).
4651 Also modify the body of INSN by substituting RELOAD
4652 rtx's for those pseudo regs. */
4655 CLEAR_REG_SET (®_has_output_reload
);
4656 CLEAR_HARD_REG_SET (reg_is_output_reload
);
4658 find_reloads (insn
, 1, spill_indirect_levels
, live_known
,
4664 rtx next
= NEXT_INSN (insn
);
4667 /* ??? PREV can get deleted by reload inheritance.
4668 Work around this by emitting a marker note. */
4669 prev
= PREV_INSN (insn
);
4670 reorder_insns_nobb (marker
, marker
, prev
);
4672 /* Now compute which reload regs to reload them into. Perhaps
4673 reusing reload regs from previous insns, or else output
4674 load insns to reload them. Maybe output store insns too.
4675 Record the choices of reload reg in reload_reg_rtx. */
4676 choose_reload_regs (chain
);
4678 /* Generate the insns to reload operands into or out of
4679 their reload regs. */
4680 emit_reload_insns (chain
);
4682 /* Substitute the chosen reload regs from reload_reg_rtx
4683 into the insn's body (or perhaps into the bodies of other
4684 load and store insn that we just made for reloading
4685 and that we moved the structure into). */
4686 subst_reloads (insn
);
4688 prev
= PREV_INSN (marker
);
4689 unlink_insn_chain (marker
, marker
);
4691 /* Adjust the exception region notes for loads and stores. */
4692 if (cfun
->can_throw_non_call_exceptions
&& !CALL_P (insn
))
4693 fixup_eh_region_note (insn
, prev
, next
);
4695 /* Adjust the location of REG_ARGS_SIZE. */
4696 p
= find_reg_note (insn
, REG_ARGS_SIZE
, NULL_RTX
);
4699 remove_note (insn
, p
);
4700 fixup_args_size_notes (prev
, PREV_INSN (next
),
4701 INTVAL (XEXP (p
, 0)));
4704 /* If this was an ASM, make sure that all the reload insns
4705 we have generated are valid. If not, give an error
4707 if (asm_noperands (PATTERN (insn
)) >= 0)
4708 for (p
= NEXT_INSN (prev
); p
!= next
; p
= NEXT_INSN (p
))
4709 if (p
!= insn
&& INSN_P (p
)
4710 && GET_CODE (PATTERN (p
)) != USE
4711 && (recog_memoized (p
) < 0
4712 || (extract_insn (p
), ! constrain_operands (1))))
4714 error_for_asm (insn
,
4715 "%<asm%> operand requires "
4716 "impossible reload");
4721 if (num_eliminable
&& chain
->need_elim
)
4722 update_eliminable_offsets ();
4724 /* Any previously reloaded spilled pseudo reg, stored in this insn,
4725 is no longer validly lying around to save a future reload.
4726 Note that this does not detect pseudos that were reloaded
4727 for this insn in order to be stored in
4728 (obeying register constraints). That is correct; such reload
4729 registers ARE still valid. */
4730 forget_marked_reloads (®s_to_forget
);
4731 CLEAR_REG_SET (®s_to_forget
);
4733 /* There may have been CLOBBER insns placed after INSN. So scan
4734 between INSN and NEXT and use them to forget old reloads. */
4735 for (x
= NEXT_INSN (insn
); x
!= old_next
; x
= NEXT_INSN (x
))
4736 if (NONJUMP_INSN_P (x
) && GET_CODE (PATTERN (x
)) == CLOBBER
)
4737 note_stores (PATTERN (x
), forget_old_reloads_1
, NULL
);
4740 /* Likewise for regs altered by auto-increment in this insn.
4741 REG_INC notes have been changed by reloading:
4742 find_reloads_address_1 records substitutions for them,
4743 which have been performed by subst_reloads above. */
4744 for (i
= n_reloads
- 1; i
>= 0; i
--)
4746 rtx in_reg
= rld
[i
].in_reg
;
4749 enum rtx_code code
= GET_CODE (in_reg
);
4750 /* PRE_INC / PRE_DEC will have the reload register ending up
4751 with the same value as the stack slot, but that doesn't
4752 hold true for POST_INC / POST_DEC. Either we have to
4753 convert the memory access to a true POST_INC / POST_DEC,
4754 or we can't use the reload register for inheritance. */
4755 if ((code
== POST_INC
|| code
== POST_DEC
)
4756 && TEST_HARD_REG_BIT (reg_reloaded_valid
,
4757 REGNO (rld
[i
].reg_rtx
))
4758 /* Make sure it is the inc/dec pseudo, and not
4759 some other (e.g. output operand) pseudo. */
4760 && ((unsigned) reg_reloaded_contents
[REGNO (rld
[i
].reg_rtx
)]
4761 == REGNO (XEXP (in_reg
, 0))))
4764 rtx reload_reg
= rld
[i
].reg_rtx
;
4765 enum machine_mode mode
= GET_MODE (reload_reg
);
4769 for (p
= PREV_INSN (old_next
); p
!= prev
; p
= PREV_INSN (p
))
4771 /* We really want to ignore REG_INC notes here, so
4772 use PATTERN (p) as argument to reg_set_p . */
4773 if (reg_set_p (reload_reg
, PATTERN (p
)))
4775 n
= count_occurrences (PATTERN (p
), reload_reg
, 0);
4781 = gen_rtx_fmt_e (code
, mode
, reload_reg
);
4783 validate_replace_rtx_group (reload_reg
,
4785 n
= verify_changes (0);
4787 /* We must also verify that the constraints
4788 are met after the replacement. Make sure
4789 extract_insn is only called for an insn
4790 where the replacements were found to be
4795 n
= constrain_operands (1);
4798 /* If the constraints were not met, then
4799 undo the replacement, else confirm it. */
4803 confirm_change_group ();
4809 add_reg_note (p
, REG_INC
, reload_reg
);
4810 /* Mark this as having an output reload so that the
4811 REG_INC processing code below won't invalidate
4812 the reload for inheritance. */
4813 SET_HARD_REG_BIT (reg_is_output_reload
,
4814 REGNO (reload_reg
));
4815 SET_REGNO_REG_SET (®_has_output_reload
,
4816 REGNO (XEXP (in_reg
, 0)));
4819 forget_old_reloads_1 (XEXP (in_reg
, 0), NULL_RTX
,
4822 else if ((code
== PRE_INC
|| code
== PRE_DEC
)
4823 && TEST_HARD_REG_BIT (reg_reloaded_valid
,
4824 REGNO (rld
[i
].reg_rtx
))
4825 /* Make sure it is the inc/dec pseudo, and not
4826 some other (e.g. output operand) pseudo. */
4827 && ((unsigned) reg_reloaded_contents
[REGNO (rld
[i
].reg_rtx
)]
4828 == REGNO (XEXP (in_reg
, 0))))
4830 SET_HARD_REG_BIT (reg_is_output_reload
,
4831 REGNO (rld
[i
].reg_rtx
));
4832 SET_REGNO_REG_SET (®_has_output_reload
,
4833 REGNO (XEXP (in_reg
, 0)));
4835 else if (code
== PRE_INC
|| code
== PRE_DEC
4836 || code
== POST_INC
|| code
== POST_DEC
)
4838 int in_regno
= REGNO (XEXP (in_reg
, 0));
4840 if (reg_last_reload_reg
[in_regno
] != NULL_RTX
)
4843 bool forget_p
= true;
4845 in_hard_regno
= REGNO (reg_last_reload_reg
[in_regno
]);
4846 if (TEST_HARD_REG_BIT (reg_reloaded_valid
,
4849 for (x
= old_prev
? NEXT_INSN (old_prev
) : insn
;
4852 if (x
== reg_reloaded_insn
[in_hard_regno
])
4858 /* If for some reasons, we didn't set up
4859 reg_last_reload_reg in this insn,
4860 invalidate inheritance from previous
4861 insns for the incremented/decremented
4862 register. Such registers will be not in
4863 reg_has_output_reload. Invalidate it
4864 also if the corresponding element in
4865 reg_reloaded_insn is also
4868 forget_old_reloads_1 (XEXP (in_reg
, 0),
4874 /* If a pseudo that got a hard register is auto-incremented,
4875 we must purge records of copying it into pseudos without
4877 for (x
= REG_NOTES (insn
); x
; x
= XEXP (x
, 1))
4878 if (REG_NOTE_KIND (x
) == REG_INC
)
4880 /* See if this pseudo reg was reloaded in this insn.
4881 If so, its last-reload info is still valid
4882 because it is based on this insn's reload. */
4883 for (i
= 0; i
< n_reloads
; i
++)
4884 if (rld
[i
].out
== XEXP (x
, 0))
4888 forget_old_reloads_1 (XEXP (x
, 0), NULL_RTX
, NULL
);
4892 /* A reload reg's contents are unknown after a label. */
4894 CLEAR_HARD_REG_SET (reg_reloaded_valid
);
4896 /* Don't assume a reload reg is still good after a call insn
4897 if it is a call-used reg, or if it contains a value that will
4898 be partially clobbered by the call. */
4899 else if (CALL_P (insn
))
4901 AND_COMPL_HARD_REG_SET (reg_reloaded_valid
, call_used_reg_set
);
4902 AND_COMPL_HARD_REG_SET (reg_reloaded_valid
, reg_reloaded_call_part_clobbered
);
4904 /* If this is a call to a setjmp-type function, we must not
4905 reuse any reload reg contents across the call; that will
4906 just be clobbered by other uses of the register in later
4907 code, before the longjmp. */
4908 if (find_reg_note (insn
, REG_SETJMP
, NULL_RTX
))
4909 CLEAR_HARD_REG_SET (reg_reloaded_valid
);
4914 free (reg_last_reload_reg
);
4915 CLEAR_REG_SET (®_has_output_reload
);
4918 /* Discard all record of any value reloaded from X,
4919 or reloaded in X from someplace else;
4920 unless X is an output reload reg of the current insn.
4922 X may be a hard reg (the reload reg)
4923 or it may be a pseudo reg that was reloaded from.
4925 When DATA is non-NULL just mark the registers in regset
4926 to be forgotten later. */
4929 forget_old_reloads_1 (rtx x
, const_rtx ignored ATTRIBUTE_UNUSED
,
4934 regset regs
= (regset
) data
;
4936 /* note_stores does give us subregs of hard regs,
4937 subreg_regno_offset requires a hard reg. */
4938 while (GET_CODE (x
) == SUBREG
)
4940 /* We ignore the subreg offset when calculating the regno,
4941 because we are using the entire underlying hard register
4951 if (regno
>= FIRST_PSEUDO_REGISTER
)
4957 nr
= hard_regno_nregs
[regno
][GET_MODE (x
)];
4958 /* Storing into a spilled-reg invalidates its contents.
4959 This can happen if a block-local pseudo is allocated to that reg
4960 and it wasn't spilled because this block's total need is 0.
4961 Then some insn might have an optional reload and use this reg. */
4963 for (i
= 0; i
< nr
; i
++)
4964 /* But don't do this if the reg actually serves as an output
4965 reload reg in the current instruction. */
4967 || ! TEST_HARD_REG_BIT (reg_is_output_reload
, regno
+ i
))
4969 CLEAR_HARD_REG_BIT (reg_reloaded_valid
, regno
+ i
);
4970 spill_reg_store
[regno
+ i
] = 0;
4976 SET_REGNO_REG_SET (regs
, regno
+ nr
);
4979 /* Since value of X has changed,
4980 forget any value previously copied from it. */
4983 /* But don't forget a copy if this is the output reload
4984 that establishes the copy's validity. */
4986 || !REGNO_REG_SET_P (®_has_output_reload
, regno
+ nr
))
4987 reg_last_reload_reg
[regno
+ nr
] = 0;
4991 /* Forget the reloads marked in regset by previous function. */
4993 forget_marked_reloads (regset regs
)
4996 reg_set_iterator rsi
;
4997 EXECUTE_IF_SET_IN_REG_SET (regs
, 0, reg
, rsi
)
4999 if (reg
< FIRST_PSEUDO_REGISTER
5000 /* But don't do this if the reg actually serves as an output
5001 reload reg in the current instruction. */
5003 || ! TEST_HARD_REG_BIT (reg_is_output_reload
, reg
)))
5005 CLEAR_HARD_REG_BIT (reg_reloaded_valid
, reg
);
5006 spill_reg_store
[reg
] = 0;
5009 || !REGNO_REG_SET_P (®_has_output_reload
, reg
))
5010 reg_last_reload_reg
[reg
] = 0;
5014 /* The following HARD_REG_SETs indicate when each hard register is
5015 used for a reload of various parts of the current insn. */
5017 /* If reg is unavailable for all reloads. */
5018 static HARD_REG_SET reload_reg_unavailable
;
5019 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
5020 static HARD_REG_SET reload_reg_used
;
5021 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
5022 static HARD_REG_SET reload_reg_used_in_input_addr
[MAX_RECOG_OPERANDS
];
5023 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */
5024 static HARD_REG_SET reload_reg_used_in_inpaddr_addr
[MAX_RECOG_OPERANDS
];
5025 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
5026 static HARD_REG_SET reload_reg_used_in_output_addr
[MAX_RECOG_OPERANDS
];
5027 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */
5028 static HARD_REG_SET reload_reg_used_in_outaddr_addr
[MAX_RECOG_OPERANDS
];
5029 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
5030 static HARD_REG_SET reload_reg_used_in_input
[MAX_RECOG_OPERANDS
];
5031 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
5032 static HARD_REG_SET reload_reg_used_in_output
[MAX_RECOG_OPERANDS
];
5033 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
5034 static HARD_REG_SET reload_reg_used_in_op_addr
;
5035 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */
5036 static HARD_REG_SET reload_reg_used_in_op_addr_reload
;
5037 /* If reg is in use for a RELOAD_FOR_INSN reload. */
5038 static HARD_REG_SET reload_reg_used_in_insn
;
5039 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
5040 static HARD_REG_SET reload_reg_used_in_other_addr
;
5042 /* If reg is in use as a reload reg for any sort of reload. */
5043 static HARD_REG_SET reload_reg_used_at_all
;
5045 /* If reg is use as an inherited reload. We just mark the first register
5047 static HARD_REG_SET reload_reg_used_for_inherit
;
5049 /* Records which hard regs are used in any way, either as explicit use or
5050 by being allocated to a pseudo during any point of the current insn. */
5051 static HARD_REG_SET reg_used_in_insn
;
5053 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
5054 TYPE. MODE is used to indicate how many consecutive regs are
5058 mark_reload_reg_in_use (unsigned int regno
, int opnum
, enum reload_type type
,
5059 enum machine_mode mode
)
5064 add_to_hard_reg_set (&reload_reg_used
, mode
, regno
);
5067 case RELOAD_FOR_INPUT_ADDRESS
:
5068 add_to_hard_reg_set (&reload_reg_used_in_input_addr
[opnum
], mode
, regno
);
5071 case RELOAD_FOR_INPADDR_ADDRESS
:
5072 add_to_hard_reg_set (&reload_reg_used_in_inpaddr_addr
[opnum
], mode
, regno
);
5075 case RELOAD_FOR_OUTPUT_ADDRESS
:
5076 add_to_hard_reg_set (&reload_reg_used_in_output_addr
[opnum
], mode
, regno
);
5079 case RELOAD_FOR_OUTADDR_ADDRESS
:
5080 add_to_hard_reg_set (&reload_reg_used_in_outaddr_addr
[opnum
], mode
, regno
);
5083 case RELOAD_FOR_OPERAND_ADDRESS
:
5084 add_to_hard_reg_set (&reload_reg_used_in_op_addr
, mode
, regno
);
5087 case RELOAD_FOR_OPADDR_ADDR
:
5088 add_to_hard_reg_set (&reload_reg_used_in_op_addr_reload
, mode
, regno
);
5091 case RELOAD_FOR_OTHER_ADDRESS
:
5092 add_to_hard_reg_set (&reload_reg_used_in_other_addr
, mode
, regno
);
5095 case RELOAD_FOR_INPUT
:
5096 add_to_hard_reg_set (&reload_reg_used_in_input
[opnum
], mode
, regno
);
5099 case RELOAD_FOR_OUTPUT
:
5100 add_to_hard_reg_set (&reload_reg_used_in_output
[opnum
], mode
, regno
);
5103 case RELOAD_FOR_INSN
:
5104 add_to_hard_reg_set (&reload_reg_used_in_insn
, mode
, regno
);
5108 add_to_hard_reg_set (&reload_reg_used_at_all
, mode
, regno
);
5111 /* Similarly, but show REGNO is no longer in use for a reload. */
5114 clear_reload_reg_in_use (unsigned int regno
, int opnum
,
5115 enum reload_type type
, enum machine_mode mode
)
5117 unsigned int nregs
= hard_regno_nregs
[regno
][mode
];
5118 unsigned int start_regno
, end_regno
, r
;
5120 /* A complication is that for some reload types, inheritance might
5121 allow multiple reloads of the same types to share a reload register.
5122 We set check_opnum if we have to check only reloads with the same
5123 operand number, and check_any if we have to check all reloads. */
5124 int check_opnum
= 0;
5126 HARD_REG_SET
*used_in_set
;
5131 used_in_set
= &reload_reg_used
;
5134 case RELOAD_FOR_INPUT_ADDRESS
:
5135 used_in_set
= &reload_reg_used_in_input_addr
[opnum
];
5138 case RELOAD_FOR_INPADDR_ADDRESS
:
5140 used_in_set
= &reload_reg_used_in_inpaddr_addr
[opnum
];
5143 case RELOAD_FOR_OUTPUT_ADDRESS
:
5144 used_in_set
= &reload_reg_used_in_output_addr
[opnum
];
5147 case RELOAD_FOR_OUTADDR_ADDRESS
:
5149 used_in_set
= &reload_reg_used_in_outaddr_addr
[opnum
];
5152 case RELOAD_FOR_OPERAND_ADDRESS
:
5153 used_in_set
= &reload_reg_used_in_op_addr
;
5156 case RELOAD_FOR_OPADDR_ADDR
:
5158 used_in_set
= &reload_reg_used_in_op_addr_reload
;
5161 case RELOAD_FOR_OTHER_ADDRESS
:
5162 used_in_set
= &reload_reg_used_in_other_addr
;
5166 case RELOAD_FOR_INPUT
:
5167 used_in_set
= &reload_reg_used_in_input
[opnum
];
5170 case RELOAD_FOR_OUTPUT
:
5171 used_in_set
= &reload_reg_used_in_output
[opnum
];
5174 case RELOAD_FOR_INSN
:
5175 used_in_set
= &reload_reg_used_in_insn
;
5180 /* We resolve conflicts with remaining reloads of the same type by
5181 excluding the intervals of reload registers by them from the
5182 interval of freed reload registers. Since we only keep track of
5183 one set of interval bounds, we might have to exclude somewhat
5184 more than what would be necessary if we used a HARD_REG_SET here.
5185 But this should only happen very infrequently, so there should
5186 be no reason to worry about it. */
5188 start_regno
= regno
;
5189 end_regno
= regno
+ nregs
;
5190 if (check_opnum
|| check_any
)
5192 for (i
= n_reloads
- 1; i
>= 0; i
--)
5194 if (rld
[i
].when_needed
== type
5195 && (check_any
|| rld
[i
].opnum
== opnum
)
5198 unsigned int conflict_start
= true_regnum (rld
[i
].reg_rtx
);
5199 unsigned int conflict_end
5200 = end_hard_regno (rld
[i
].mode
, conflict_start
);
5202 /* If there is an overlap with the first to-be-freed register,
5203 adjust the interval start. */
5204 if (conflict_start
<= start_regno
&& conflict_end
> start_regno
)
5205 start_regno
= conflict_end
;
5206 /* Otherwise, if there is a conflict with one of the other
5207 to-be-freed registers, adjust the interval end. */
5208 if (conflict_start
> start_regno
&& conflict_start
< end_regno
)
5209 end_regno
= conflict_start
;
5214 for (r
= start_regno
; r
< end_regno
; r
++)
5215 CLEAR_HARD_REG_BIT (*used_in_set
, r
);
5218 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
5219 specified by OPNUM and TYPE. */
5222 reload_reg_free_p (unsigned int regno
, int opnum
, enum reload_type type
)
5226 /* In use for a RELOAD_OTHER means it's not available for anything. */
5227 if (TEST_HARD_REG_BIT (reload_reg_used
, regno
)
5228 || TEST_HARD_REG_BIT (reload_reg_unavailable
, regno
))
5234 /* In use for anything means we can't use it for RELOAD_OTHER. */
5235 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr
, regno
)
5236 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
)
5237 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload
, regno
)
5238 || TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
))
5241 for (i
= 0; i
< reload_n_operands
; i
++)
5242 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
5243 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
)
5244 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
5245 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
)
5246 || TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
)
5247 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
5252 case RELOAD_FOR_INPUT
:
5253 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
5254 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
))
5257 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload
, regno
))
5260 /* If it is used for some other input, can't use it. */
5261 for (i
= 0; i
< reload_n_operands
; i
++)
5262 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
5265 /* If it is used in a later operand's address, can't use it. */
5266 for (i
= opnum
+ 1; i
< reload_n_operands
; i
++)
5267 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
5268 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
))
5273 case RELOAD_FOR_INPUT_ADDRESS
:
5274 /* Can't use a register if it is used for an input address for this
5275 operand or used as an input in an earlier one. */
5276 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[opnum
], regno
)
5277 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[opnum
], regno
))
5280 for (i
= 0; i
< opnum
; i
++)
5281 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
5286 case RELOAD_FOR_INPADDR_ADDRESS
:
5287 /* Can't use a register if it is used for an input address
5288 for this operand or used as an input in an earlier
5290 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[opnum
], regno
))
5293 for (i
= 0; i
< opnum
; i
++)
5294 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
5299 case RELOAD_FOR_OUTPUT_ADDRESS
:
5300 /* Can't use a register if it is used for an output address for this
5301 operand or used as an output in this or a later operand. Note
5302 that multiple output operands are emitted in reverse order, so
5303 the conflicting ones are those with lower indices. */
5304 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[opnum
], regno
))
5307 for (i
= 0; i
<= opnum
; i
++)
5308 if (TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
5313 case RELOAD_FOR_OUTADDR_ADDRESS
:
5314 /* Can't use a register if it is used for an output address
5315 for this operand or used as an output in this or a
5316 later operand. Note that multiple output operands are
5317 emitted in reverse order, so the conflicting ones are
5318 those with lower indices. */
5319 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[opnum
], regno
))
5322 for (i
= 0; i
<= opnum
; i
++)
5323 if (TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
5328 case RELOAD_FOR_OPERAND_ADDRESS
:
5329 for (i
= 0; i
< reload_n_operands
; i
++)
5330 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
5333 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
5334 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
));
5336 case RELOAD_FOR_OPADDR_ADDR
:
5337 for (i
= 0; i
< reload_n_operands
; i
++)
5338 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
5341 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload
, regno
));
5343 case RELOAD_FOR_OUTPUT
:
5344 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
5345 outputs, or an operand address for this or an earlier output.
5346 Note that multiple output operands are emitted in reverse order,
5347 so the conflicting ones are those with higher indices. */
5348 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
))
5351 for (i
= 0; i
< reload_n_operands
; i
++)
5352 if (TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
5355 for (i
= opnum
; i
< reload_n_operands
; i
++)
5356 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
5357 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
))
5362 case RELOAD_FOR_INSN
:
5363 for (i
= 0; i
< reload_n_operands
; i
++)
5364 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
)
5365 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
5368 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
5369 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
));
5371 case RELOAD_FOR_OTHER_ADDRESS
:
5372 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr
, regno
);
5379 /* Return 1 if the value in reload reg REGNO, as used by the reload with
5380 the number RELOADNUM, is still available in REGNO at the end of the insn.
5382 We can assume that the reload reg was already tested for availability
5383 at the time it is needed, and we should not check this again,
5384 in case the reg has already been marked in use. */
5387 reload_reg_reaches_end_p (unsigned int regno
, int reloadnum
)
5389 int opnum
= rld
[reloadnum
].opnum
;
5390 enum reload_type type
= rld
[reloadnum
].when_needed
;
5393 /* See if there is a reload with the same type for this operand, using
5394 the same register. This case is not handled by the code below. */
5395 for (i
= reloadnum
+ 1; i
< n_reloads
; i
++)
5400 if (rld
[i
].opnum
!= opnum
|| rld
[i
].when_needed
!= type
)
5402 reg
= rld
[i
].reg_rtx
;
5403 if (reg
== NULL_RTX
)
5405 nregs
= hard_regno_nregs
[REGNO (reg
)][GET_MODE (reg
)];
5406 if (regno
>= REGNO (reg
) && regno
< REGNO (reg
) + nregs
)
5413 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
5414 its value must reach the end. */
5417 /* If this use is for part of the insn,
5418 its value reaches if no subsequent part uses the same register.
5419 Just like the above function, don't try to do this with lots
5422 case RELOAD_FOR_OTHER_ADDRESS
:
5423 /* Here we check for everything else, since these don't conflict
5424 with anything else and everything comes later. */
5426 for (i
= 0; i
< reload_n_operands
; i
++)
5427 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
5428 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
)
5429 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
)
5430 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
5431 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
)
5432 || TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
5435 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
)
5436 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload
, regno
)
5437 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
5438 && ! TEST_HARD_REG_BIT (reload_reg_used
, regno
));
5440 case RELOAD_FOR_INPUT_ADDRESS
:
5441 case RELOAD_FOR_INPADDR_ADDRESS
:
5442 /* Similar, except that we check only for this and subsequent inputs
5443 and the address of only subsequent inputs and we do not need
5444 to check for RELOAD_OTHER objects since they are known not to
5447 for (i
= opnum
; i
< reload_n_operands
; i
++)
5448 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
5451 /* Reload register of reload with type RELOAD_FOR_INPADDR_ADDRESS
5452 could be killed if the register is also used by reload with type
5453 RELOAD_FOR_INPUT_ADDRESS, so check it. */
5454 if (type
== RELOAD_FOR_INPADDR_ADDRESS
5455 && TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[opnum
], regno
))
5458 for (i
= opnum
+ 1; i
< reload_n_operands
; i
++)
5459 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
5460 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
))
5463 for (i
= 0; i
< reload_n_operands
; i
++)
5464 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
5465 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
)
5466 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
5469 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload
, regno
))
5472 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
)
5473 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
5474 && !TEST_HARD_REG_BIT (reload_reg_used
, regno
));
5476 case RELOAD_FOR_INPUT
:
5477 /* Similar to input address, except we start at the next operand for
5478 both input and input address and we do not check for
5479 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
5482 for (i
= opnum
+ 1; i
< reload_n_operands
; i
++)
5483 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
5484 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
)
5485 || TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
5488 /* ... fall through ... */
5490 case RELOAD_FOR_OPERAND_ADDRESS
:
5491 /* Check outputs and their addresses. */
5493 for (i
= 0; i
< reload_n_operands
; i
++)
5494 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
5495 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
)
5496 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
5499 return (!TEST_HARD_REG_BIT (reload_reg_used
, regno
));
5501 case RELOAD_FOR_OPADDR_ADDR
:
5502 for (i
= 0; i
< reload_n_operands
; i
++)
5503 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
5504 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
)
5505 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
5508 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
)
5509 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
5510 && !TEST_HARD_REG_BIT (reload_reg_used
, regno
));
5512 case RELOAD_FOR_INSN
:
5513 /* These conflict with other outputs with RELOAD_OTHER. So
5514 we need only check for output addresses. */
5516 opnum
= reload_n_operands
;
5518 /* ... fall through ... */
5520 case RELOAD_FOR_OUTPUT
:
5521 case RELOAD_FOR_OUTPUT_ADDRESS
:
5522 case RELOAD_FOR_OUTADDR_ADDRESS
:
5523 /* We already know these can't conflict with a later output. So the
5524 only thing to check are later output addresses.
5525 Note that multiple output operands are emitted in reverse order,
5526 so the conflicting ones are those with lower indices. */
5527 for (i
= 0; i
< opnum
; i
++)
5528 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
5529 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
))
5532 /* Reload register of reload with type RELOAD_FOR_OUTADDR_ADDRESS
5533 could be killed if the register is also used by reload with type
5534 RELOAD_FOR_OUTPUT_ADDRESS, so check it. */
5535 if (type
== RELOAD_FOR_OUTADDR_ADDRESS
5536 && TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[opnum
], regno
))
5546 /* Like reload_reg_reaches_end_p, but check that the condition holds for
5547 every register in REG. */
5550 reload_reg_rtx_reaches_end_p (rtx reg
, int reloadnum
)
5554 for (i
= REGNO (reg
); i
< END_REGNO (reg
); i
++)
5555 if (!reload_reg_reaches_end_p (i
, reloadnum
))
5561 /* Returns whether R1 and R2 are uniquely chained: the value of one
5562 is used by the other, and that value is not used by any other
5563 reload for this insn. This is used to partially undo the decision
5564 made in find_reloads when in the case of multiple
5565 RELOAD_FOR_OPERAND_ADDRESS reloads it converts all
5566 RELOAD_FOR_OPADDR_ADDR reloads into RELOAD_FOR_OPERAND_ADDRESS
5567 reloads. This code tries to avoid the conflict created by that
5568 change. It might be cleaner to explicitly keep track of which
5569 RELOAD_FOR_OPADDR_ADDR reload is associated with which
5570 RELOAD_FOR_OPERAND_ADDRESS reload, rather than to try to detect
5571 this after the fact. */
5573 reloads_unique_chain_p (int r1
, int r2
)
5577 /* We only check input reloads. */
5578 if (! rld
[r1
].in
|| ! rld
[r2
].in
)
5581 /* Avoid anything with output reloads. */
5582 if (rld
[r1
].out
|| rld
[r2
].out
)
5585 /* "chained" means one reload is a component of the other reload,
5586 not the same as the other reload. */
5587 if (rld
[r1
].opnum
!= rld
[r2
].opnum
5588 || rtx_equal_p (rld
[r1
].in
, rld
[r2
].in
)
5589 || rld
[r1
].optional
|| rld
[r2
].optional
5590 || ! (reg_mentioned_p (rld
[r1
].in
, rld
[r2
].in
)
5591 || reg_mentioned_p (rld
[r2
].in
, rld
[r1
].in
)))
5594 /* The following loop assumes that r1 is the reload that feeds r2. */
5602 for (i
= 0; i
< n_reloads
; i
++)
5603 /* Look for input reloads that aren't our two */
5604 if (i
!= r1
&& i
!= r2
&& rld
[i
].in
)
5606 /* If our reload is mentioned at all, it isn't a simple chain. */
5607 if (reg_mentioned_p (rld
[r1
].in
, rld
[i
].in
))
5613 /* The recursive function change all occurrences of WHAT in *WHERE
5616 substitute (rtx
*where
, const_rtx what
, rtx repl
)
5625 if (*where
== what
|| rtx_equal_p (*where
, what
))
5627 /* Record the location of the changed rtx. */
5628 substitute_stack
.safe_push (where
);
5633 code
= GET_CODE (*where
);
5634 fmt
= GET_RTX_FORMAT (code
);
5635 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
5641 for (j
= XVECLEN (*where
, i
) - 1; j
>= 0; j
--)
5642 substitute (&XVECEXP (*where
, i
, j
), what
, repl
);
5644 else if (fmt
[i
] == 'e')
5645 substitute (&XEXP (*where
, i
), what
, repl
);
5649 /* The function returns TRUE if chain of reload R1 and R2 (in any
5650 order) can be evaluated without usage of intermediate register for
5651 the reload containing another reload. It is important to see
5652 gen_reload to understand what the function is trying to do. As an
5653 example, let us have reload chain
5656 r1: <something> + const
5658 and reload R2 got reload reg HR. The function returns true if
5659 there is a correct insn HR = HR + <something>. Otherwise,
5660 gen_reload will use intermediate register (and this is the reload
5661 reg for R1) to reload <something>.
5663 We need this function to find a conflict for chain reloads. In our
5664 example, if HR = HR + <something> is incorrect insn, then we cannot
5665 use HR as a reload register for R2. If we do use it then we get a
5674 gen_reload_chain_without_interm_reg_p (int r1
, int r2
)
5676 /* Assume other cases in gen_reload are not possible for
5677 chain reloads or do need an intermediate hard registers. */
5681 rtx last
= get_last_insn ();
5683 /* Make r2 a component of r1. */
5684 if (reg_mentioned_p (rld
[r1
].in
, rld
[r2
].in
))
5690 gcc_assert (reg_mentioned_p (rld
[r2
].in
, rld
[r1
].in
));
5691 regno
= rld
[r1
].regno
>= 0 ? rld
[r1
].regno
: rld
[r2
].regno
;
5692 gcc_assert (regno
>= 0);
5693 out
= gen_rtx_REG (rld
[r1
].mode
, regno
);
5695 substitute (&in
, rld
[r2
].in
, gen_rtx_REG (rld
[r2
].mode
, regno
));
5697 /* If IN is a paradoxical SUBREG, remove it and try to put the
5698 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
5699 strip_paradoxical_subreg (&in
, &out
);
5701 if (GET_CODE (in
) == PLUS
5702 && (REG_P (XEXP (in
, 0))
5703 || GET_CODE (XEXP (in
, 0)) == SUBREG
5704 || MEM_P (XEXP (in
, 0)))
5705 && (REG_P (XEXP (in
, 1))
5706 || GET_CODE (XEXP (in
, 1)) == SUBREG
5707 || CONSTANT_P (XEXP (in
, 1))
5708 || MEM_P (XEXP (in
, 1))))
5710 insn
= emit_insn (gen_rtx_SET (VOIDmode
, out
, in
));
5711 code
= recog_memoized (insn
);
5716 extract_insn (insn
);
5717 /* We want constrain operands to treat this insn strictly in
5718 its validity determination, i.e., the way it would after
5719 reload has completed. */
5720 result
= constrain_operands (1);
5723 delete_insns_since (last
);
5726 /* Restore the original value at each changed address within R1. */
5727 while (!substitute_stack
.is_empty ())
5729 rtx
*where
= substitute_stack
.pop ();
5730 *where
= rld
[r2
].in
;
5736 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
5739 This function uses the same algorithm as reload_reg_free_p above. */
5742 reloads_conflict (int r1
, int r2
)
5744 enum reload_type r1_type
= rld
[r1
].when_needed
;
5745 enum reload_type r2_type
= rld
[r2
].when_needed
;
5746 int r1_opnum
= rld
[r1
].opnum
;
5747 int r2_opnum
= rld
[r2
].opnum
;
5749 /* RELOAD_OTHER conflicts with everything. */
5750 if (r2_type
== RELOAD_OTHER
)
5753 /* Otherwise, check conflicts differently for each type. */
5757 case RELOAD_FOR_INPUT
:
5758 return (r2_type
== RELOAD_FOR_INSN
5759 || r2_type
== RELOAD_FOR_OPERAND_ADDRESS
5760 || r2_type
== RELOAD_FOR_OPADDR_ADDR
5761 || r2_type
== RELOAD_FOR_INPUT
5762 || ((r2_type
== RELOAD_FOR_INPUT_ADDRESS
5763 || r2_type
== RELOAD_FOR_INPADDR_ADDRESS
)
5764 && r2_opnum
> r1_opnum
));
5766 case RELOAD_FOR_INPUT_ADDRESS
:
5767 return ((r2_type
== RELOAD_FOR_INPUT_ADDRESS
&& r1_opnum
== r2_opnum
)
5768 || (r2_type
== RELOAD_FOR_INPUT
&& r2_opnum
< r1_opnum
));
5770 case RELOAD_FOR_INPADDR_ADDRESS
:
5771 return ((r2_type
== RELOAD_FOR_INPADDR_ADDRESS
&& r1_opnum
== r2_opnum
)
5772 || (r2_type
== RELOAD_FOR_INPUT
&& r2_opnum
< r1_opnum
));
5774 case RELOAD_FOR_OUTPUT_ADDRESS
:
5775 return ((r2_type
== RELOAD_FOR_OUTPUT_ADDRESS
&& r2_opnum
== r1_opnum
)
5776 || (r2_type
== RELOAD_FOR_OUTPUT
&& r2_opnum
<= r1_opnum
));
5778 case RELOAD_FOR_OUTADDR_ADDRESS
:
5779 return ((r2_type
== RELOAD_FOR_OUTADDR_ADDRESS
&& r2_opnum
== r1_opnum
)
5780 || (r2_type
== RELOAD_FOR_OUTPUT
&& r2_opnum
<= r1_opnum
));
5782 case RELOAD_FOR_OPERAND_ADDRESS
:
5783 return (r2_type
== RELOAD_FOR_INPUT
|| r2_type
== RELOAD_FOR_INSN
5784 || (r2_type
== RELOAD_FOR_OPERAND_ADDRESS
5785 && (!reloads_unique_chain_p (r1
, r2
)
5786 || !gen_reload_chain_without_interm_reg_p (r1
, r2
))));
5788 case RELOAD_FOR_OPADDR_ADDR
:
5789 return (r2_type
== RELOAD_FOR_INPUT
5790 || r2_type
== RELOAD_FOR_OPADDR_ADDR
);
5792 case RELOAD_FOR_OUTPUT
:
5793 return (r2_type
== RELOAD_FOR_INSN
|| r2_type
== RELOAD_FOR_OUTPUT
5794 || ((r2_type
== RELOAD_FOR_OUTPUT_ADDRESS
5795 || r2_type
== RELOAD_FOR_OUTADDR_ADDRESS
)
5796 && r2_opnum
>= r1_opnum
));
5798 case RELOAD_FOR_INSN
:
5799 return (r2_type
== RELOAD_FOR_INPUT
|| r2_type
== RELOAD_FOR_OUTPUT
5800 || r2_type
== RELOAD_FOR_INSN
5801 || r2_type
== RELOAD_FOR_OPERAND_ADDRESS
);
5803 case RELOAD_FOR_OTHER_ADDRESS
:
5804 return r2_type
== RELOAD_FOR_OTHER_ADDRESS
;
5814 /* Indexed by reload number, 1 if incoming value
5815 inherited from previous insns. */
5816 static char reload_inherited
[MAX_RELOADS
];
5818 /* For an inherited reload, this is the insn the reload was inherited from,
5819 if we know it. Otherwise, this is 0. */
5820 static rtx reload_inheritance_insn
[MAX_RELOADS
];
5822 /* If nonzero, this is a place to get the value of the reload,
5823 rather than using reload_in. */
5824 static rtx reload_override_in
[MAX_RELOADS
];
5826 /* For each reload, the hard register number of the register used,
5827 or -1 if we did not need a register for this reload. */
5828 static int reload_spill_index
[MAX_RELOADS
];
5830 /* Index X is the value of rld[X].reg_rtx, adjusted for the input mode. */
5831 static rtx reload_reg_rtx_for_input
[MAX_RELOADS
];
5833 /* Index X is the value of rld[X].reg_rtx, adjusted for the output mode. */
5834 static rtx reload_reg_rtx_for_output
[MAX_RELOADS
];
5836 /* Subroutine of free_for_value_p, used to check a single register.
5837 START_REGNO is the starting regno of the full reload register
5838 (possibly comprising multiple hard registers) that we are considering. */
5841 reload_reg_free_for_value_p (int start_regno
, int regno
, int opnum
,
5842 enum reload_type type
, rtx value
, rtx out
,
5843 int reloadnum
, int ignore_address_reloads
)
5846 /* Set if we see an input reload that must not share its reload register
5847 with any new earlyclobber, but might otherwise share the reload
5848 register with an output or input-output reload. */
5849 int check_earlyclobber
= 0;
5853 if (TEST_HARD_REG_BIT (reload_reg_unavailable
, regno
))
5856 if (out
== const0_rtx
)
5862 /* We use some pseudo 'time' value to check if the lifetimes of the
5863 new register use would overlap with the one of a previous reload
5864 that is not read-only or uses a different value.
5865 The 'time' used doesn't have to be linear in any shape or form, just
5867 Some reload types use different 'buckets' for each operand.
5868 So there are MAX_RECOG_OPERANDS different time values for each
5870 We compute TIME1 as the time when the register for the prospective
5871 new reload ceases to be live, and TIME2 for each existing
5872 reload as the time when that the reload register of that reload
5874 Where there is little to be gained by exact lifetime calculations,
5875 we just make conservative assumptions, i.e. a longer lifetime;
5876 this is done in the 'default:' cases. */
5879 case RELOAD_FOR_OTHER_ADDRESS
:
5880 /* RELOAD_FOR_OTHER_ADDRESS conflicts with RELOAD_OTHER reloads. */
5881 time1
= copy
? 0 : 1;
5884 time1
= copy
? 1 : MAX_RECOG_OPERANDS
* 5 + 5;
5886 /* For each input, we may have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
5887 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 ,
5888 respectively, to the time values for these, we get distinct time
5889 values. To get distinct time values for each operand, we have to
5890 multiply opnum by at least three. We round that up to four because
5891 multiply by four is often cheaper. */
5892 case RELOAD_FOR_INPADDR_ADDRESS
:
5893 time1
= opnum
* 4 + 2;
5895 case RELOAD_FOR_INPUT_ADDRESS
:
5896 time1
= opnum
* 4 + 3;
5898 case RELOAD_FOR_INPUT
:
5899 /* All RELOAD_FOR_INPUT reloads remain live till the instruction
5900 executes (inclusive). */
5901 time1
= copy
? opnum
* 4 + 4 : MAX_RECOG_OPERANDS
* 4 + 3;
5903 case RELOAD_FOR_OPADDR_ADDR
:
5905 <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
5906 time1
= MAX_RECOG_OPERANDS
* 4 + 1;
5908 case RELOAD_FOR_OPERAND_ADDRESS
:
5909 /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn
5911 time1
= copy
? MAX_RECOG_OPERANDS
* 4 + 2 : MAX_RECOG_OPERANDS
* 4 + 3;
5913 case RELOAD_FOR_OUTADDR_ADDRESS
:
5914 time1
= MAX_RECOG_OPERANDS
* 4 + 4 + opnum
;
5916 case RELOAD_FOR_OUTPUT_ADDRESS
:
5917 time1
= MAX_RECOG_OPERANDS
* 4 + 5 + opnum
;
5920 time1
= MAX_RECOG_OPERANDS
* 5 + 5;
5923 for (i
= 0; i
< n_reloads
; i
++)
5925 rtx reg
= rld
[i
].reg_rtx
;
5926 if (reg
&& REG_P (reg
)
5927 && ((unsigned) regno
- true_regnum (reg
)
5928 <= hard_regno_nregs
[REGNO (reg
)][GET_MODE (reg
)] - (unsigned) 1)
5931 rtx other_input
= rld
[i
].in
;
5933 /* If the other reload loads the same input value, that
5934 will not cause a conflict only if it's loading it into
5935 the same register. */
5936 if (true_regnum (reg
) != start_regno
)
5937 other_input
= NULL_RTX
;
5938 if (! other_input
|| ! rtx_equal_p (other_input
, value
)
5939 || rld
[i
].out
|| out
)
5942 switch (rld
[i
].when_needed
)
5944 case RELOAD_FOR_OTHER_ADDRESS
:
5947 case RELOAD_FOR_INPADDR_ADDRESS
:
5948 /* find_reloads makes sure that a
5949 RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used
5950 by at most one - the first -
5951 RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the
5952 address reload is inherited, the address address reload
5953 goes away, so we can ignore this conflict. */
5954 if (type
== RELOAD_FOR_INPUT_ADDRESS
&& reloadnum
== i
+ 1
5955 && ignore_address_reloads
5956 /* Unless the RELOAD_FOR_INPUT is an auto_inc expression.
5957 Then the address address is still needed to store
5958 back the new address. */
5959 && ! rld
[reloadnum
].out
)
5961 /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its
5962 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS
5964 if (type
== RELOAD_FOR_INPUT
&& opnum
== rld
[i
].opnum
5965 && ignore_address_reloads
5966 /* Unless we are reloading an auto_inc expression. */
5967 && ! rld
[reloadnum
].out
)
5969 time2
= rld
[i
].opnum
* 4 + 2;
5971 case RELOAD_FOR_INPUT_ADDRESS
:
5972 if (type
== RELOAD_FOR_INPUT
&& opnum
== rld
[i
].opnum
5973 && ignore_address_reloads
5974 && ! rld
[reloadnum
].out
)
5976 time2
= rld
[i
].opnum
* 4 + 3;
5978 case RELOAD_FOR_INPUT
:
5979 time2
= rld
[i
].opnum
* 4 + 4;
5980 check_earlyclobber
= 1;
5982 /* rld[i].opnum * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4
5983 == MAX_RECOG_OPERAND * 4 */
5984 case RELOAD_FOR_OPADDR_ADDR
:
5985 if (type
== RELOAD_FOR_OPERAND_ADDRESS
&& reloadnum
== i
+ 1
5986 && ignore_address_reloads
5987 && ! rld
[reloadnum
].out
)
5989 time2
= MAX_RECOG_OPERANDS
* 4 + 1;
5991 case RELOAD_FOR_OPERAND_ADDRESS
:
5992 time2
= MAX_RECOG_OPERANDS
* 4 + 2;
5993 check_earlyclobber
= 1;
5995 case RELOAD_FOR_INSN
:
5996 time2
= MAX_RECOG_OPERANDS
* 4 + 3;
5998 case RELOAD_FOR_OUTPUT
:
5999 /* All RELOAD_FOR_OUTPUT reloads become live just after the
6000 instruction is executed. */
6001 time2
= MAX_RECOG_OPERANDS
* 4 + 4;
6003 /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with
6004 the RELOAD_FOR_OUTPUT reloads, so assign it the same time
6006 case RELOAD_FOR_OUTADDR_ADDRESS
:
6007 if (type
== RELOAD_FOR_OUTPUT_ADDRESS
&& reloadnum
== i
+ 1
6008 && ignore_address_reloads
6009 && ! rld
[reloadnum
].out
)
6011 time2
= MAX_RECOG_OPERANDS
* 4 + 4 + rld
[i
].opnum
;
6013 case RELOAD_FOR_OUTPUT_ADDRESS
:
6014 time2
= MAX_RECOG_OPERANDS
* 4 + 5 + rld
[i
].opnum
;
6017 /* If there is no conflict in the input part, handle this
6018 like an output reload. */
6019 if (! rld
[i
].in
|| rtx_equal_p (other_input
, value
))
6021 time2
= MAX_RECOG_OPERANDS
* 4 + 4;
6022 /* Earlyclobbered outputs must conflict with inputs. */
6023 if (earlyclobber_operand_p (rld
[i
].out
))
6024 time2
= MAX_RECOG_OPERANDS
* 4 + 3;
6029 /* RELOAD_OTHER might be live beyond instruction execution,
6030 but this is not obvious when we set time2 = 1. So check
6031 here if there might be a problem with the new reload
6032 clobbering the register used by the RELOAD_OTHER. */
6040 && (! rld
[i
].in
|| rld
[i
].out
6041 || ! rtx_equal_p (other_input
, value
)))
6042 || (out
&& rld
[reloadnum
].out_reg
6043 && time2
>= MAX_RECOG_OPERANDS
* 4 + 3))
6049 /* Earlyclobbered outputs must conflict with inputs. */
6050 if (check_earlyclobber
&& out
&& earlyclobber_operand_p (out
))
6056 /* Return 1 if the value in reload reg REGNO, as used by a reload
6057 needed for the part of the insn specified by OPNUM and TYPE,
6058 may be used to load VALUE into it.
6060 MODE is the mode in which the register is used, this is needed to
6061 determine how many hard regs to test.
6063 Other read-only reloads with the same value do not conflict
6064 unless OUT is nonzero and these other reloads have to live while
6065 output reloads live.
6066 If OUT is CONST0_RTX, this is a special case: it means that the
6067 test should not be for using register REGNO as reload register, but
6068 for copying from register REGNO into the reload register.
6070 RELOADNUM is the number of the reload we want to load this value for;
6071 a reload does not conflict with itself.
6073 When IGNORE_ADDRESS_RELOADS is set, we can not have conflicts with
6074 reloads that load an address for the very reload we are considering.
6076 The caller has to make sure that there is no conflict with the return
6080 free_for_value_p (int regno
, enum machine_mode mode
, int opnum
,
6081 enum reload_type type
, rtx value
, rtx out
, int reloadnum
,
6082 int ignore_address_reloads
)
6084 int nregs
= hard_regno_nregs
[regno
][mode
];
6086 if (! reload_reg_free_for_value_p (regno
, regno
+ nregs
, opnum
, type
,
6087 value
, out
, reloadnum
,
6088 ignore_address_reloads
))
6093 /* Return nonzero if the rtx X is invariant over the current function. */
6094 /* ??? Actually, the places where we use this expect exactly what is
6095 tested here, and not everything that is function invariant. In
6096 particular, the frame pointer and arg pointer are special cased;
6097 pic_offset_table_rtx is not, and we must not spill these things to
6101 function_invariant_p (const_rtx x
)
6105 if (x
== frame_pointer_rtx
|| x
== arg_pointer_rtx
)
6107 if (GET_CODE (x
) == PLUS
6108 && (XEXP (x
, 0) == frame_pointer_rtx
|| XEXP (x
, 0) == arg_pointer_rtx
)
6109 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
6114 /* Determine whether the reload reg X overlaps any rtx'es used for
6115 overriding inheritance. Return nonzero if so. */
6118 conflicts_with_override (rtx x
)
6121 for (i
= 0; i
< n_reloads
; i
++)
6122 if (reload_override_in
[i
]
6123 && reg_overlap_mentioned_p (x
, reload_override_in
[i
]))
6128 /* Give an error message saying we failed to find a reload for INSN,
6129 and clear out reload R. */
6131 failed_reload (rtx insn
, int r
)
6133 if (asm_noperands (PATTERN (insn
)) < 0)
6134 /* It's the compiler's fault. */
6135 fatal_insn ("could not find a spill register", insn
);
6137 /* It's the user's fault; the operand's mode and constraint
6138 don't match. Disable this reload so we don't crash in final. */
6139 error_for_asm (insn
,
6140 "%<asm%> operand constraint incompatible with operand size");
6144 rld
[r
].optional
= 1;
6145 rld
[r
].secondary_p
= 1;
6148 /* I is the index in SPILL_REG_RTX of the reload register we are to allocate
6149 for reload R. If it's valid, get an rtx for it. Return nonzero if
6152 set_reload_reg (int i
, int r
)
6154 /* regno is 'set but not used' if HARD_REGNO_MODE_OK doesn't use its first
6156 int regno ATTRIBUTE_UNUSED
;
6157 rtx reg
= spill_reg_rtx
[i
];
6159 if (reg
== 0 || GET_MODE (reg
) != rld
[r
].mode
)
6160 spill_reg_rtx
[i
] = reg
6161 = gen_rtx_REG (rld
[r
].mode
, spill_regs
[i
]);
6163 regno
= true_regnum (reg
);
6165 /* Detect when the reload reg can't hold the reload mode.
6166 This used to be one `if', but Sequent compiler can't handle that. */
6167 if (HARD_REGNO_MODE_OK (regno
, rld
[r
].mode
))
6169 enum machine_mode test_mode
= VOIDmode
;
6171 test_mode
= GET_MODE (rld
[r
].in
);
6172 /* If rld[r].in has VOIDmode, it means we will load it
6173 in whatever mode the reload reg has: to wit, rld[r].mode.
6174 We have already tested that for validity. */
6175 /* Aside from that, we need to test that the expressions
6176 to reload from or into have modes which are valid for this
6177 reload register. Otherwise the reload insns would be invalid. */
6178 if (! (rld
[r
].in
!= 0 && test_mode
!= VOIDmode
6179 && ! HARD_REGNO_MODE_OK (regno
, test_mode
)))
6180 if (! (rld
[r
].out
!= 0
6181 && ! HARD_REGNO_MODE_OK (regno
, GET_MODE (rld
[r
].out
))))
6183 /* The reg is OK. */
6186 /* Mark as in use for this insn the reload regs we use
6188 mark_reload_reg_in_use (spill_regs
[i
], rld
[r
].opnum
,
6189 rld
[r
].when_needed
, rld
[r
].mode
);
6191 rld
[r
].reg_rtx
= reg
;
6192 reload_spill_index
[r
] = spill_regs
[i
];
6199 /* Find a spill register to use as a reload register for reload R.
6200 LAST_RELOAD is nonzero if this is the last reload for the insn being
6203 Set rld[R].reg_rtx to the register allocated.
6205 We return 1 if successful, or 0 if we couldn't find a spill reg and
6206 we didn't change anything. */
6209 allocate_reload_reg (struct insn_chain
*chain ATTRIBUTE_UNUSED
, int r
,
6214 /* If we put this reload ahead, thinking it is a group,
6215 then insist on finding a group. Otherwise we can grab a
6216 reg that some other reload needs.
6217 (That can happen when we have a 68000 DATA_OR_FP_REG
6218 which is a group of data regs or one fp reg.)
6219 We need not be so restrictive if there are no more reloads
6222 ??? Really it would be nicer to have smarter handling
6223 for that kind of reg class, where a problem like this is normal.
6224 Perhaps those classes should be avoided for reloading
6225 by use of more alternatives. */
6227 int force_group
= rld
[r
].nregs
> 1 && ! last_reload
;
6229 /* If we want a single register and haven't yet found one,
6230 take any reg in the right class and not in use.
6231 If we want a consecutive group, here is where we look for it.
6233 We use three passes so we can first look for reload regs to
6234 reuse, which are already in use for other reloads in this insn,
6235 and only then use additional registers which are not "bad", then
6236 finally any register.
6238 I think that maximizing reuse is needed to make sure we don't
6239 run out of reload regs. Suppose we have three reloads, and
6240 reloads A and B can share regs. These need two regs.
6241 Suppose A and B are given different regs.
6242 That leaves none for C. */
6243 for (pass
= 0; pass
< 3; pass
++)
6245 /* I is the index in spill_regs.
6246 We advance it round-robin between insns to use all spill regs
6247 equally, so that inherited reloads have a chance
6248 of leapfrogging each other. */
6252 for (count
= 0; count
< n_spills
; count
++)
6254 int rclass
= (int) rld
[r
].rclass
;
6260 regnum
= spill_regs
[i
];
6262 if ((reload_reg_free_p (regnum
, rld
[r
].opnum
,
6265 /* We check reload_reg_used to make sure we
6266 don't clobber the return register. */
6267 && ! TEST_HARD_REG_BIT (reload_reg_used
, regnum
)
6268 && free_for_value_p (regnum
, rld
[r
].mode
, rld
[r
].opnum
,
6269 rld
[r
].when_needed
, rld
[r
].in
,
6271 && TEST_HARD_REG_BIT (reg_class_contents
[rclass
], regnum
)
6272 && HARD_REGNO_MODE_OK (regnum
, rld
[r
].mode
)
6273 /* Look first for regs to share, then for unshared. But
6274 don't share regs used for inherited reloads; they are
6275 the ones we want to preserve. */
6277 || (TEST_HARD_REG_BIT (reload_reg_used_at_all
,
6279 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit
,
6282 int nr
= hard_regno_nregs
[regnum
][rld
[r
].mode
];
6284 /* During the second pass we want to avoid reload registers
6285 which are "bad" for this reload. */
6287 && ira_bad_reload_regno (regnum
, rld
[r
].in
, rld
[r
].out
))
6290 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
6291 (on 68000) got us two FP regs. If NR is 1,
6292 we would reject both of them. */
6295 /* If we need only one reg, we have already won. */
6298 /* But reject a single reg if we demand a group. */
6303 /* Otherwise check that as many consecutive regs as we need
6304 are available here. */
6307 int regno
= regnum
+ nr
- 1;
6308 if (!(TEST_HARD_REG_BIT (reg_class_contents
[rclass
], regno
)
6309 && spill_reg_order
[regno
] >= 0
6310 && reload_reg_free_p (regno
, rld
[r
].opnum
,
6311 rld
[r
].when_needed
)))
6320 /* If we found something on the current pass, omit later passes. */
6321 if (count
< n_spills
)
6325 /* We should have found a spill register by now. */
6326 if (count
>= n_spills
)
6329 /* I is the index in SPILL_REG_RTX of the reload register we are to
6330 allocate. Get an rtx for it and find its register number. */
6332 return set_reload_reg (i
, r
);
6335 /* Initialize all the tables needed to allocate reload registers.
6336 CHAIN is the insn currently being processed; SAVE_RELOAD_REG_RTX
6337 is the array we use to restore the reg_rtx field for every reload. */
6340 choose_reload_regs_init (struct insn_chain
*chain
, rtx
*save_reload_reg_rtx
)
6344 for (i
= 0; i
< n_reloads
; i
++)
6345 rld
[i
].reg_rtx
= save_reload_reg_rtx
[i
];
6347 memset (reload_inherited
, 0, MAX_RELOADS
);
6348 memset (reload_inheritance_insn
, 0, MAX_RELOADS
* sizeof (rtx
));
6349 memset (reload_override_in
, 0, MAX_RELOADS
* sizeof (rtx
));
6351 CLEAR_HARD_REG_SET (reload_reg_used
);
6352 CLEAR_HARD_REG_SET (reload_reg_used_at_all
);
6353 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr
);
6354 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload
);
6355 CLEAR_HARD_REG_SET (reload_reg_used_in_insn
);
6356 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr
);
6358 CLEAR_HARD_REG_SET (reg_used_in_insn
);
6361 REG_SET_TO_HARD_REG_SET (tmp
, &chain
->live_throughout
);
6362 IOR_HARD_REG_SET (reg_used_in_insn
, tmp
);
6363 REG_SET_TO_HARD_REG_SET (tmp
, &chain
->dead_or_set
);
6364 IOR_HARD_REG_SET (reg_used_in_insn
, tmp
);
6365 compute_use_by_pseudos (®_used_in_insn
, &chain
->live_throughout
);
6366 compute_use_by_pseudos (®_used_in_insn
, &chain
->dead_or_set
);
6369 for (i
= 0; i
< reload_n_operands
; i
++)
6371 CLEAR_HARD_REG_SET (reload_reg_used_in_output
[i
]);
6372 CLEAR_HARD_REG_SET (reload_reg_used_in_input
[i
]);
6373 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr
[i
]);
6374 CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr
[i
]);
6375 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr
[i
]);
6376 CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr
[i
]);
6379 COMPL_HARD_REG_SET (reload_reg_unavailable
, chain
->used_spill_regs
);
6381 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit
);
6383 for (i
= 0; i
< n_reloads
; i
++)
6384 /* If we have already decided to use a certain register,
6385 don't use it in another way. */
6387 mark_reload_reg_in_use (REGNO (rld
[i
].reg_rtx
), rld
[i
].opnum
,
6388 rld
[i
].when_needed
, rld
[i
].mode
);
6391 #ifdef SECONDARY_MEMORY_NEEDED
6392 /* If X is not a subreg, return it unmodified. If it is a subreg,
6393 look up whether we made a replacement for the SUBREG_REG. Return
6394 either the replacement or the SUBREG_REG. */
6397 replaced_subreg (rtx x
)
6399 if (GET_CODE (x
) == SUBREG
)
6400 return find_replacement (&SUBREG_REG (x
));
6405 /* Compute the offset to pass to subreg_regno_offset, for a pseudo of
6406 mode OUTERMODE that is available in a hard reg of mode INNERMODE.
6407 SUBREG is non-NULL if the pseudo is a subreg whose reg is a pseudo,
6408 otherwise it is NULL. */
6411 compute_reload_subreg_offset (enum machine_mode outermode
,
6413 enum machine_mode innermode
)
6416 enum machine_mode middlemode
;
6419 return subreg_lowpart_offset (outermode
, innermode
);
6421 outer_offset
= SUBREG_BYTE (subreg
);
6422 middlemode
= GET_MODE (SUBREG_REG (subreg
));
6424 /* If SUBREG is paradoxical then return the normal lowpart offset
6425 for OUTERMODE and INNERMODE. Our caller has already checked
6426 that OUTERMODE fits in INNERMODE. */
6427 if (outer_offset
== 0
6428 && GET_MODE_SIZE (outermode
) > GET_MODE_SIZE (middlemode
))
6429 return subreg_lowpart_offset (outermode
, innermode
);
6431 /* SUBREG is normal, but may not be lowpart; return OUTER_OFFSET
6432 plus the normal lowpart offset for MIDDLEMODE and INNERMODE. */
6433 return outer_offset
+ subreg_lowpart_offset (middlemode
, innermode
);
6436 /* Assign hard reg targets for the pseudo-registers we must reload
6437 into hard regs for this insn.
6438 Also output the instructions to copy them in and out of the hard regs.
6440 For machines with register classes, we are responsible for
6441 finding a reload reg in the proper class. */
6444 choose_reload_regs (struct insn_chain
*chain
)
6446 rtx insn
= chain
->insn
;
6448 unsigned int max_group_size
= 1;
6449 enum reg_class group_class
= NO_REGS
;
6450 int pass
, win
, inheritance
;
6452 rtx save_reload_reg_rtx
[MAX_RELOADS
];
6454 /* In order to be certain of getting the registers we need,
6455 we must sort the reloads into order of increasing register class.
6456 Then our grabbing of reload registers will parallel the process
6457 that provided the reload registers.
6459 Also note whether any of the reloads wants a consecutive group of regs.
6460 If so, record the maximum size of the group desired and what
6461 register class contains all the groups needed by this insn. */
6463 for (j
= 0; j
< n_reloads
; j
++)
6465 reload_order
[j
] = j
;
6466 if (rld
[j
].reg_rtx
!= NULL_RTX
)
6468 gcc_assert (REG_P (rld
[j
].reg_rtx
)
6469 && HARD_REGISTER_P (rld
[j
].reg_rtx
));
6470 reload_spill_index
[j
] = REGNO (rld
[j
].reg_rtx
);
6473 reload_spill_index
[j
] = -1;
6475 if (rld
[j
].nregs
> 1)
6477 max_group_size
= MAX (rld
[j
].nregs
, max_group_size
);
6479 = reg_class_superunion
[(int) rld
[j
].rclass
][(int) group_class
];
6482 save_reload_reg_rtx
[j
] = rld
[j
].reg_rtx
;
6486 qsort (reload_order
, n_reloads
, sizeof (short), reload_reg_class_lower
);
6488 /* If -O, try first with inheritance, then turning it off.
6489 If not -O, don't do inheritance.
6490 Using inheritance when not optimizing leads to paradoxes
6491 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
6492 because one side of the comparison might be inherited. */
6494 for (inheritance
= optimize
> 0; inheritance
>= 0; inheritance
--)
6496 choose_reload_regs_init (chain
, save_reload_reg_rtx
);
6498 /* Process the reloads in order of preference just found.
6499 Beyond this point, subregs can be found in reload_reg_rtx.
6501 This used to look for an existing reloaded home for all of the
6502 reloads, and only then perform any new reloads. But that could lose
6503 if the reloads were done out of reg-class order because a later
6504 reload with a looser constraint might have an old home in a register
6505 needed by an earlier reload with a tighter constraint.
6507 To solve this, we make two passes over the reloads, in the order
6508 described above. In the first pass we try to inherit a reload
6509 from a previous insn. If there is a later reload that needs a
6510 class that is a proper subset of the class being processed, we must
6511 also allocate a spill register during the first pass.
6513 Then make a second pass over the reloads to allocate any reloads
6514 that haven't been given registers yet. */
6516 for (j
= 0; j
< n_reloads
; j
++)
6518 int r
= reload_order
[j
];
6519 rtx search_equiv
= NULL_RTX
;
6521 /* Ignore reloads that got marked inoperative. */
6522 if (rld
[r
].out
== 0 && rld
[r
].in
== 0
6523 && ! rld
[r
].secondary_p
)
6526 /* If find_reloads chose to use reload_in or reload_out as a reload
6527 register, we don't need to chose one. Otherwise, try even if it
6528 found one since we might save an insn if we find the value lying
6530 Try also when reload_in is a pseudo without a hard reg. */
6531 if (rld
[r
].in
!= 0 && rld
[r
].reg_rtx
!= 0
6532 && (rtx_equal_p (rld
[r
].in
, rld
[r
].reg_rtx
)
6533 || (rtx_equal_p (rld
[r
].out
, rld
[r
].reg_rtx
)
6534 && !MEM_P (rld
[r
].in
)
6535 && true_regnum (rld
[r
].in
) < FIRST_PSEUDO_REGISTER
)))
6538 #if 0 /* No longer needed for correct operation.
6539 It might give better code, or might not; worth an experiment? */
6540 /* If this is an optional reload, we can't inherit from earlier insns
6541 until we are sure that any non-optional reloads have been allocated.
6542 The following code takes advantage of the fact that optional reloads
6543 are at the end of reload_order. */
6544 if (rld
[r
].optional
!= 0)
6545 for (i
= 0; i
< j
; i
++)
6546 if ((rld
[reload_order
[i
]].out
!= 0
6547 || rld
[reload_order
[i
]].in
!= 0
6548 || rld
[reload_order
[i
]].secondary_p
)
6549 && ! rld
[reload_order
[i
]].optional
6550 && rld
[reload_order
[i
]].reg_rtx
== 0)
6551 allocate_reload_reg (chain
, reload_order
[i
], 0);
6554 /* First see if this pseudo is already available as reloaded
6555 for a previous insn. We cannot try to inherit for reloads
6556 that are smaller than the maximum number of registers needed
6557 for groups unless the register we would allocate cannot be used
6560 We could check here to see if this is a secondary reload for
6561 an object that is already in a register of the desired class.
6562 This would avoid the need for the secondary reload register.
6563 But this is complex because we can't easily determine what
6564 objects might want to be loaded via this reload. So let a
6565 register be allocated here. In `emit_reload_insns' we suppress
6566 one of the loads in the case described above. */
6572 enum machine_mode mode
= VOIDmode
;
6573 rtx subreg
= NULL_RTX
;
6577 else if (REG_P (rld
[r
].in
))
6579 regno
= REGNO (rld
[r
].in
);
6580 mode
= GET_MODE (rld
[r
].in
);
6582 else if (REG_P (rld
[r
].in_reg
))
6584 regno
= REGNO (rld
[r
].in_reg
);
6585 mode
= GET_MODE (rld
[r
].in_reg
);
6587 else if (GET_CODE (rld
[r
].in_reg
) == SUBREG
6588 && REG_P (SUBREG_REG (rld
[r
].in_reg
)))
6590 regno
= REGNO (SUBREG_REG (rld
[r
].in_reg
));
6591 if (regno
< FIRST_PSEUDO_REGISTER
)
6592 regno
= subreg_regno (rld
[r
].in_reg
);
6595 subreg
= rld
[r
].in_reg
;
6596 byte
= SUBREG_BYTE (subreg
);
6598 mode
= GET_MODE (rld
[r
].in_reg
);
6601 else if (GET_RTX_CLASS (GET_CODE (rld
[r
].in_reg
)) == RTX_AUTOINC
6602 && REG_P (XEXP (rld
[r
].in_reg
, 0)))
6604 regno
= REGNO (XEXP (rld
[r
].in_reg
, 0));
6605 mode
= GET_MODE (XEXP (rld
[r
].in_reg
, 0));
6606 rld
[r
].out
= rld
[r
].in
;
6610 /* This won't work, since REGNO can be a pseudo reg number.
6611 Also, it takes much more hair to keep track of all the things
6612 that can invalidate an inherited reload of part of a pseudoreg. */
6613 else if (GET_CODE (rld
[r
].in
) == SUBREG
6614 && REG_P (SUBREG_REG (rld
[r
].in
)))
6615 regno
= subreg_regno (rld
[r
].in
);
6619 && reg_last_reload_reg
[regno
] != 0
6620 && (GET_MODE_SIZE (GET_MODE (reg_last_reload_reg
[regno
]))
6621 >= GET_MODE_SIZE (mode
) + byte
)
6622 #ifdef CANNOT_CHANGE_MODE_CLASS
6623 /* Verify that the register it's in can be used in
6625 && !REG_CANNOT_CHANGE_MODE_P (REGNO (reg_last_reload_reg
[regno
]),
6626 GET_MODE (reg_last_reload_reg
[regno
]),
6631 enum reg_class rclass
= rld
[r
].rclass
, last_class
;
6632 rtx last_reg
= reg_last_reload_reg
[regno
];
6634 i
= REGNO (last_reg
);
6635 byte
= compute_reload_subreg_offset (mode
,
6637 GET_MODE (last_reg
));
6638 i
+= subreg_regno_offset (i
, GET_MODE (last_reg
), byte
, mode
);
6639 last_class
= REGNO_REG_CLASS (i
);
6641 if (reg_reloaded_contents
[i
] == regno
6642 && TEST_HARD_REG_BIT (reg_reloaded_valid
, i
)
6643 && HARD_REGNO_MODE_OK (i
, rld
[r
].mode
)
6644 && (TEST_HARD_REG_BIT (reg_class_contents
[(int) rclass
], i
)
6645 /* Even if we can't use this register as a reload
6646 register, we might use it for reload_override_in,
6647 if copying it to the desired class is cheap
6649 || ((register_move_cost (mode
, last_class
, rclass
)
6650 < memory_move_cost (mode
, rclass
, true))
6651 && (secondary_reload_class (1, rclass
, mode
,
6654 #ifdef SECONDARY_MEMORY_NEEDED
6655 && ! SECONDARY_MEMORY_NEEDED (last_class
, rclass
,
6660 && (rld
[r
].nregs
== max_group_size
6661 || ! TEST_HARD_REG_BIT (reg_class_contents
[(int) group_class
],
6663 && free_for_value_p (i
, rld
[r
].mode
, rld
[r
].opnum
,
6664 rld
[r
].when_needed
, rld
[r
].in
,
6667 /* If a group is needed, verify that all the subsequent
6668 registers still have their values intact. */
6669 int nr
= hard_regno_nregs
[i
][rld
[r
].mode
];
6672 for (k
= 1; k
< nr
; k
++)
6673 if (reg_reloaded_contents
[i
+ k
] != regno
6674 || ! TEST_HARD_REG_BIT (reg_reloaded_valid
, i
+ k
))
6682 last_reg
= (GET_MODE (last_reg
) == mode
6683 ? last_reg
: gen_rtx_REG (mode
, i
));
6686 for (k
= 0; k
< nr
; k
++)
6687 bad_for_class
|= ! TEST_HARD_REG_BIT (reg_class_contents
[(int) rld
[r
].rclass
],
6690 /* We found a register that contains the
6691 value we need. If this register is the
6692 same as an `earlyclobber' operand of the
6693 current insn, just mark it as a place to
6694 reload from since we can't use it as the
6695 reload register itself. */
6697 for (i1
= 0; i1
< n_earlyclobbers
; i1
++)
6698 if (reg_overlap_mentioned_for_reload_p
6699 (reg_last_reload_reg
[regno
],
6700 reload_earlyclobbers
[i1
]))
6703 if (i1
!= n_earlyclobbers
6704 || ! (free_for_value_p (i
, rld
[r
].mode
,
6706 rld
[r
].when_needed
, rld
[r
].in
,
6708 /* Don't use it if we'd clobber a pseudo reg. */
6709 || (TEST_HARD_REG_BIT (reg_used_in_insn
, i
)
6711 && ! TEST_HARD_REG_BIT (reg_reloaded_dead
, i
))
6712 /* Don't clobber the frame pointer. */
6713 || (i
== HARD_FRAME_POINTER_REGNUM
6714 && frame_pointer_needed
6716 /* Don't really use the inherited spill reg
6717 if we need it wider than we've got it. */
6718 || (GET_MODE_SIZE (rld
[r
].mode
)
6719 > GET_MODE_SIZE (mode
))
6722 /* If find_reloads chose reload_out as reload
6723 register, stay with it - that leaves the
6724 inherited register for subsequent reloads. */
6725 || (rld
[r
].out
&& rld
[r
].reg_rtx
6726 && rtx_equal_p (rld
[r
].out
, rld
[r
].reg_rtx
)))
6728 if (! rld
[r
].optional
)
6730 reload_override_in
[r
] = last_reg
;
6731 reload_inheritance_insn
[r
]
6732 = reg_reloaded_insn
[i
];
6738 /* We can use this as a reload reg. */
6739 /* Mark the register as in use for this part of
6741 mark_reload_reg_in_use (i
,
6745 rld
[r
].reg_rtx
= last_reg
;
6746 reload_inherited
[r
] = 1;
6747 reload_inheritance_insn
[r
]
6748 = reg_reloaded_insn
[i
];
6749 reload_spill_index
[r
] = i
;
6750 for (k
= 0; k
< nr
; k
++)
6751 SET_HARD_REG_BIT (reload_reg_used_for_inherit
,
6759 /* Here's another way to see if the value is already lying around. */
6762 && ! reload_inherited
[r
]
6764 && (CONSTANT_P (rld
[r
].in
)
6765 || GET_CODE (rld
[r
].in
) == PLUS
6766 || REG_P (rld
[r
].in
)
6767 || MEM_P (rld
[r
].in
))
6768 && (rld
[r
].nregs
== max_group_size
6769 || ! reg_classes_intersect_p (rld
[r
].rclass
, group_class
)))
6770 search_equiv
= rld
[r
].in
;
6775 = find_equiv_reg (search_equiv
, insn
, rld
[r
].rclass
,
6776 -1, NULL
, 0, rld
[r
].mode
);
6782 regno
= REGNO (equiv
);
6785 /* This must be a SUBREG of a hard register.
6786 Make a new REG since this might be used in an
6787 address and not all machines support SUBREGs
6789 gcc_assert (GET_CODE (equiv
) == SUBREG
);
6790 regno
= subreg_regno (equiv
);
6791 equiv
= gen_rtx_REG (rld
[r
].mode
, regno
);
6792 /* If we choose EQUIV as the reload register, but the
6793 loop below decides to cancel the inheritance, we'll
6794 end up reloading EQUIV in rld[r].mode, not the mode
6795 it had originally. That isn't safe when EQUIV isn't
6796 available as a spill register since its value might
6797 still be live at this point. */
6798 for (i
= regno
; i
< regno
+ (int) rld
[r
].nregs
; i
++)
6799 if (TEST_HARD_REG_BIT (reload_reg_unavailable
, i
))
6804 /* If we found a spill reg, reject it unless it is free
6805 and of the desired class. */
6809 int bad_for_class
= 0;
6810 int max_regno
= regno
+ rld
[r
].nregs
;
6812 for (i
= regno
; i
< max_regno
; i
++)
6814 regs_used
|= TEST_HARD_REG_BIT (reload_reg_used_at_all
,
6816 bad_for_class
|= ! TEST_HARD_REG_BIT (reg_class_contents
[(int) rld
[r
].rclass
],
6821 && ! free_for_value_p (regno
, rld
[r
].mode
,
6822 rld
[r
].opnum
, rld
[r
].when_needed
,
6823 rld
[r
].in
, rld
[r
].out
, r
, 1))
6828 if (equiv
!= 0 && ! HARD_REGNO_MODE_OK (regno
, rld
[r
].mode
))
6831 /* We found a register that contains the value we need.
6832 If this register is the same as an `earlyclobber' operand
6833 of the current insn, just mark it as a place to reload from
6834 since we can't use it as the reload register itself. */
6837 for (i
= 0; i
< n_earlyclobbers
; i
++)
6838 if (reg_overlap_mentioned_for_reload_p (equiv
,
6839 reload_earlyclobbers
[i
]))
6841 if (! rld
[r
].optional
)
6842 reload_override_in
[r
] = equiv
;
6847 /* If the equiv register we have found is explicitly clobbered
6848 in the current insn, it depends on the reload type if we
6849 can use it, use it for reload_override_in, or not at all.
6850 In particular, we then can't use EQUIV for a
6851 RELOAD_FOR_OUTPUT_ADDRESS reload. */
6855 if (regno_clobbered_p (regno
, insn
, rld
[r
].mode
, 2))
6856 switch (rld
[r
].when_needed
)
6858 case RELOAD_FOR_OTHER_ADDRESS
:
6859 case RELOAD_FOR_INPADDR_ADDRESS
:
6860 case RELOAD_FOR_INPUT_ADDRESS
:
6861 case RELOAD_FOR_OPADDR_ADDR
:
6864 case RELOAD_FOR_INPUT
:
6865 case RELOAD_FOR_OPERAND_ADDRESS
:
6866 if (! rld
[r
].optional
)
6867 reload_override_in
[r
] = equiv
;
6873 else if (regno_clobbered_p (regno
, insn
, rld
[r
].mode
, 1))
6874 switch (rld
[r
].when_needed
)
6876 case RELOAD_FOR_OTHER_ADDRESS
:
6877 case RELOAD_FOR_INPADDR_ADDRESS
:
6878 case RELOAD_FOR_INPUT_ADDRESS
:
6879 case RELOAD_FOR_OPADDR_ADDR
:
6880 case RELOAD_FOR_OPERAND_ADDRESS
:
6881 case RELOAD_FOR_INPUT
:
6884 if (! rld
[r
].optional
)
6885 reload_override_in
[r
] = equiv
;
6893 /* If we found an equivalent reg, say no code need be generated
6894 to load it, and use it as our reload reg. */
6896 && (regno
!= HARD_FRAME_POINTER_REGNUM
6897 || !frame_pointer_needed
))
6899 int nr
= hard_regno_nregs
[regno
][rld
[r
].mode
];
6901 rld
[r
].reg_rtx
= equiv
;
6902 reload_spill_index
[r
] = regno
;
6903 reload_inherited
[r
] = 1;
6905 /* If reg_reloaded_valid is not set for this register,
6906 there might be a stale spill_reg_store lying around.
6907 We must clear it, since otherwise emit_reload_insns
6908 might delete the store. */
6909 if (! TEST_HARD_REG_BIT (reg_reloaded_valid
, regno
))
6910 spill_reg_store
[regno
] = NULL_RTX
;
6911 /* If any of the hard registers in EQUIV are spill
6912 registers, mark them as in use for this insn. */
6913 for (k
= 0; k
< nr
; k
++)
6915 i
= spill_reg_order
[regno
+ k
];
6918 mark_reload_reg_in_use (regno
, rld
[r
].opnum
,
6921 SET_HARD_REG_BIT (reload_reg_used_for_inherit
,
6928 /* If we found a register to use already, or if this is an optional
6929 reload, we are done. */
6930 if (rld
[r
].reg_rtx
!= 0 || rld
[r
].optional
!= 0)
6934 /* No longer needed for correct operation. Might or might
6935 not give better code on the average. Want to experiment? */
6937 /* See if there is a later reload that has a class different from our
6938 class that intersects our class or that requires less register
6939 than our reload. If so, we must allocate a register to this
6940 reload now, since that reload might inherit a previous reload
6941 and take the only available register in our class. Don't do this
6942 for optional reloads since they will force all previous reloads
6943 to be allocated. Also don't do this for reloads that have been
6946 for (i
= j
+ 1; i
< n_reloads
; i
++)
6948 int s
= reload_order
[i
];
6950 if ((rld
[s
].in
== 0 && rld
[s
].out
== 0
6951 && ! rld
[s
].secondary_p
)
6955 if ((rld
[s
].rclass
!= rld
[r
].rclass
6956 && reg_classes_intersect_p (rld
[r
].rclass
,
6958 || rld
[s
].nregs
< rld
[r
].nregs
)
6965 allocate_reload_reg (chain
, r
, j
== n_reloads
- 1);
6969 /* Now allocate reload registers for anything non-optional that
6970 didn't get one yet. */
6971 for (j
= 0; j
< n_reloads
; j
++)
6973 int r
= reload_order
[j
];
6975 /* Ignore reloads that got marked inoperative. */
6976 if (rld
[r
].out
== 0 && rld
[r
].in
== 0 && ! rld
[r
].secondary_p
)
6979 /* Skip reloads that already have a register allocated or are
6981 if (rld
[r
].reg_rtx
!= 0 || rld
[r
].optional
)
6984 if (! allocate_reload_reg (chain
, r
, j
== n_reloads
- 1))
6988 /* If that loop got all the way, we have won. */
6995 /* Loop around and try without any inheritance. */
7000 /* First undo everything done by the failed attempt
7001 to allocate with inheritance. */
7002 choose_reload_regs_init (chain
, save_reload_reg_rtx
);
7004 /* Some sanity tests to verify that the reloads found in the first
7005 pass are identical to the ones we have now. */
7006 gcc_assert (chain
->n_reloads
== n_reloads
);
7008 for (i
= 0; i
< n_reloads
; i
++)
7010 if (chain
->rld
[i
].regno
< 0 || chain
->rld
[i
].reg_rtx
!= 0)
7012 gcc_assert (chain
->rld
[i
].when_needed
== rld
[i
].when_needed
);
7013 for (j
= 0; j
< n_spills
; j
++)
7014 if (spill_regs
[j
] == chain
->rld
[i
].regno
)
7015 if (! set_reload_reg (j
, i
))
7016 failed_reload (chain
->insn
, i
);
7020 /* If we thought we could inherit a reload, because it seemed that
7021 nothing else wanted the same reload register earlier in the insn,
7022 verify that assumption, now that all reloads have been assigned.
7023 Likewise for reloads where reload_override_in has been set. */
7025 /* If doing expensive optimizations, do one preliminary pass that doesn't
7026 cancel any inheritance, but removes reloads that have been needed only
7027 for reloads that we know can be inherited. */
7028 for (pass
= flag_expensive_optimizations
; pass
>= 0; pass
--)
7030 for (j
= 0; j
< n_reloads
; j
++)
7032 int r
= reload_order
[j
];
7034 #ifdef SECONDARY_MEMORY_NEEDED
7037 if (reload_inherited
[r
] && rld
[r
].reg_rtx
)
7038 check_reg
= rld
[r
].reg_rtx
;
7039 else if (reload_override_in
[r
]
7040 && (REG_P (reload_override_in
[r
])
7041 || GET_CODE (reload_override_in
[r
]) == SUBREG
))
7042 check_reg
= reload_override_in
[r
];
7045 if (! free_for_value_p (true_regnum (check_reg
), rld
[r
].mode
,
7046 rld
[r
].opnum
, rld
[r
].when_needed
, rld
[r
].in
,
7047 (reload_inherited
[r
]
7048 ? rld
[r
].out
: const0_rtx
),
7053 reload_inherited
[r
] = 0;
7054 reload_override_in
[r
] = 0;
7056 /* If we can inherit a RELOAD_FOR_INPUT, or can use a
7057 reload_override_in, then we do not need its related
7058 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads;
7059 likewise for other reload types.
7060 We handle this by removing a reload when its only replacement
7061 is mentioned in reload_in of the reload we are going to inherit.
7062 A special case are auto_inc expressions; even if the input is
7063 inherited, we still need the address for the output. We can
7064 recognize them because they have RELOAD_OUT set to RELOAD_IN.
7065 If we succeeded removing some reload and we are doing a preliminary
7066 pass just to remove such reloads, make another pass, since the
7067 removal of one reload might allow us to inherit another one. */
7069 && rld
[r
].out
!= rld
[r
].in
7070 && remove_address_replacements (rld
[r
].in
))
7075 #ifdef SECONDARY_MEMORY_NEEDED
7076 /* If we needed a memory location for the reload, we also have to
7077 remove its related reloads. */
7079 && rld
[r
].out
!= rld
[r
].in
7080 && (tem
= replaced_subreg (rld
[r
].in
), REG_P (tem
))
7081 && REGNO (tem
) < FIRST_PSEUDO_REGISTER
7082 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (REGNO (tem
)),
7083 rld
[r
].rclass
, rld
[r
].inmode
)
7084 && remove_address_replacements
7085 (get_secondary_mem (tem
, rld
[r
].inmode
, rld
[r
].opnum
,
7086 rld
[r
].when_needed
)))
7095 /* Now that reload_override_in is known valid,
7096 actually override reload_in. */
7097 for (j
= 0; j
< n_reloads
; j
++)
7098 if (reload_override_in
[j
])
7099 rld
[j
].in
= reload_override_in
[j
];
7101 /* If this reload won't be done because it has been canceled or is
7102 optional and not inherited, clear reload_reg_rtx so other
7103 routines (such as subst_reloads) don't get confused. */
7104 for (j
= 0; j
< n_reloads
; j
++)
7105 if (rld
[j
].reg_rtx
!= 0
7106 && ((rld
[j
].optional
&& ! reload_inherited
[j
])
7107 || (rld
[j
].in
== 0 && rld
[j
].out
== 0
7108 && ! rld
[j
].secondary_p
)))
7110 int regno
= true_regnum (rld
[j
].reg_rtx
);
7112 if (spill_reg_order
[regno
] >= 0)
7113 clear_reload_reg_in_use (regno
, rld
[j
].opnum
,
7114 rld
[j
].when_needed
, rld
[j
].mode
);
7116 reload_spill_index
[j
] = -1;
7119 /* Record which pseudos and which spill regs have output reloads. */
7120 for (j
= 0; j
< n_reloads
; j
++)
7122 int r
= reload_order
[j
];
7124 i
= reload_spill_index
[r
];
7126 /* I is nonneg if this reload uses a register.
7127 If rld[r].reg_rtx is 0, this is an optional reload
7128 that we opted to ignore. */
7129 if (rld
[r
].out_reg
!= 0 && REG_P (rld
[r
].out_reg
)
7130 && rld
[r
].reg_rtx
!= 0)
7132 int nregno
= REGNO (rld
[r
].out_reg
);
7135 if (nregno
< FIRST_PSEUDO_REGISTER
)
7136 nr
= hard_regno_nregs
[nregno
][rld
[r
].mode
];
7139 SET_REGNO_REG_SET (®_has_output_reload
,
7143 add_to_hard_reg_set (®_is_output_reload
, rld
[r
].mode
, i
);
7145 gcc_assert (rld
[r
].when_needed
== RELOAD_OTHER
7146 || rld
[r
].when_needed
== RELOAD_FOR_OUTPUT
7147 || rld
[r
].when_needed
== RELOAD_FOR_INSN
);
7152 /* Deallocate the reload register for reload R. This is called from
7153 remove_address_replacements. */
7156 deallocate_reload_reg (int r
)
7160 if (! rld
[r
].reg_rtx
)
7162 regno
= true_regnum (rld
[r
].reg_rtx
);
7164 if (spill_reg_order
[regno
] >= 0)
7165 clear_reload_reg_in_use (regno
, rld
[r
].opnum
, rld
[r
].when_needed
,
7167 reload_spill_index
[r
] = -1;
7170 /* These arrays are filled by emit_reload_insns and its subroutines. */
7171 static rtx input_reload_insns
[MAX_RECOG_OPERANDS
];
7172 static rtx other_input_address_reload_insns
= 0;
7173 static rtx other_input_reload_insns
= 0;
7174 static rtx input_address_reload_insns
[MAX_RECOG_OPERANDS
];
7175 static rtx inpaddr_address_reload_insns
[MAX_RECOG_OPERANDS
];
7176 static rtx output_reload_insns
[MAX_RECOG_OPERANDS
];
7177 static rtx output_address_reload_insns
[MAX_RECOG_OPERANDS
];
7178 static rtx outaddr_address_reload_insns
[MAX_RECOG_OPERANDS
];
7179 static rtx operand_reload_insns
= 0;
7180 static rtx other_operand_reload_insns
= 0;
7181 static rtx other_output_reload_insns
[MAX_RECOG_OPERANDS
];
7183 /* Values to be put in spill_reg_store are put here first. Instructions
7184 must only be placed here if the associated reload register reaches
7185 the end of the instruction's reload sequence. */
7186 static rtx new_spill_reg_store
[FIRST_PSEUDO_REGISTER
];
7187 static HARD_REG_SET reg_reloaded_died
;
7189 /* Check if *RELOAD_REG is suitable as an intermediate or scratch register
7190 of class NEW_CLASS with mode NEW_MODE. Or alternatively, if alt_reload_reg
7191 is nonzero, if that is suitable. On success, change *RELOAD_REG to the
7192 adjusted register, and return true. Otherwise, return false. */
7194 reload_adjust_reg_for_temp (rtx
*reload_reg
, rtx alt_reload_reg
,
7195 enum reg_class new_class
,
7196 enum machine_mode new_mode
)
7201 for (reg
= *reload_reg
; reg
; reg
= alt_reload_reg
, alt_reload_reg
= 0)
7203 unsigned regno
= REGNO (reg
);
7205 if (!TEST_HARD_REG_BIT (reg_class_contents
[(int) new_class
], regno
))
7207 if (GET_MODE (reg
) != new_mode
)
7209 if (!HARD_REGNO_MODE_OK (regno
, new_mode
))
7211 if (hard_regno_nregs
[regno
][new_mode
]
7212 > hard_regno_nregs
[regno
][GET_MODE (reg
)])
7214 reg
= reload_adjust_reg_for_mode (reg
, new_mode
);
7222 /* Check if *RELOAD_REG is suitable as a scratch register for the reload
7223 pattern with insn_code ICODE, or alternatively, if alt_reload_reg is
7224 nonzero, if that is suitable. On success, change *RELOAD_REG to the
7225 adjusted register, and return true. Otherwise, return false. */
7227 reload_adjust_reg_for_icode (rtx
*reload_reg
, rtx alt_reload_reg
,
7228 enum insn_code icode
)
7231 enum reg_class new_class
= scratch_reload_class (icode
);
7232 enum machine_mode new_mode
= insn_data
[(int) icode
].operand
[2].mode
;
7234 return reload_adjust_reg_for_temp (reload_reg
, alt_reload_reg
,
7235 new_class
, new_mode
);
7238 /* Generate insns to perform reload RL, which is for the insn in CHAIN and
7239 has the number J. OLD contains the value to be used as input. */
7242 emit_input_reload_insns (struct insn_chain
*chain
, struct reload
*rl
,
7245 rtx insn
= chain
->insn
;
7247 rtx oldequiv_reg
= 0;
7250 enum machine_mode mode
;
7253 /* delete_output_reload is only invoked properly if old contains
7254 the original pseudo register. Since this is replaced with a
7255 hard reg when RELOAD_OVERRIDE_IN is set, see if we can
7256 find the pseudo in RELOAD_IN_REG. This is also used to
7257 determine whether a secondary reload is needed. */
7258 if (reload_override_in
[j
]
7259 && (REG_P (rl
->in_reg
)
7260 || (GET_CODE (rl
->in_reg
) == SUBREG
7261 && REG_P (SUBREG_REG (rl
->in_reg
)))))
7268 else if (REG_P (oldequiv
))
7269 oldequiv_reg
= oldequiv
;
7270 else if (GET_CODE (oldequiv
) == SUBREG
)
7271 oldequiv_reg
= SUBREG_REG (oldequiv
);
7273 reloadreg
= reload_reg_rtx_for_input
[j
];
7274 mode
= GET_MODE (reloadreg
);
7276 /* If we are reloading from a register that was recently stored in
7277 with an output-reload, see if we can prove there was
7278 actually no need to store the old value in it. */
7280 if (optimize
&& REG_P (oldequiv
)
7281 && REGNO (oldequiv
) < FIRST_PSEUDO_REGISTER
7282 && spill_reg_store
[REGNO (oldequiv
)]
7284 && (dead_or_set_p (insn
, spill_reg_stored_to
[REGNO (oldequiv
)])
7285 || rtx_equal_p (spill_reg_stored_to
[REGNO (oldequiv
)],
7287 delete_output_reload (insn
, j
, REGNO (oldequiv
), reloadreg
);
7289 /* Encapsulate OLDEQUIV into the reload mode, then load RELOADREG from
7292 while (GET_CODE (oldequiv
) == SUBREG
&& GET_MODE (oldequiv
) != mode
)
7293 oldequiv
= SUBREG_REG (oldequiv
);
7294 if (GET_MODE (oldequiv
) != VOIDmode
7295 && mode
!= GET_MODE (oldequiv
))
7296 oldequiv
= gen_lowpart_SUBREG (mode
, oldequiv
);
7298 /* Switch to the right place to emit the reload insns. */
7299 switch (rl
->when_needed
)
7302 where
= &other_input_reload_insns
;
7304 case RELOAD_FOR_INPUT
:
7305 where
= &input_reload_insns
[rl
->opnum
];
7307 case RELOAD_FOR_INPUT_ADDRESS
:
7308 where
= &input_address_reload_insns
[rl
->opnum
];
7310 case RELOAD_FOR_INPADDR_ADDRESS
:
7311 where
= &inpaddr_address_reload_insns
[rl
->opnum
];
7313 case RELOAD_FOR_OUTPUT_ADDRESS
:
7314 where
= &output_address_reload_insns
[rl
->opnum
];
7316 case RELOAD_FOR_OUTADDR_ADDRESS
:
7317 where
= &outaddr_address_reload_insns
[rl
->opnum
];
7319 case RELOAD_FOR_OPERAND_ADDRESS
:
7320 where
= &operand_reload_insns
;
7322 case RELOAD_FOR_OPADDR_ADDR
:
7323 where
= &other_operand_reload_insns
;
7325 case RELOAD_FOR_OTHER_ADDRESS
:
7326 where
= &other_input_address_reload_insns
;
7332 push_to_sequence (*where
);
7334 /* Auto-increment addresses must be reloaded in a special way. */
7335 if (rl
->out
&& ! rl
->out_reg
)
7337 /* We are not going to bother supporting the case where a
7338 incremented register can't be copied directly from
7339 OLDEQUIV since this seems highly unlikely. */
7340 gcc_assert (rl
->secondary_in_reload
< 0);
7342 if (reload_inherited
[j
])
7343 oldequiv
= reloadreg
;
7345 old
= XEXP (rl
->in_reg
, 0);
7347 /* Prevent normal processing of this reload. */
7349 /* Output a special code sequence for this case. */
7350 inc_for_reload (reloadreg
, oldequiv
, rl
->out
, rl
->inc
);
7353 /* If we are reloading a pseudo-register that was set by the previous
7354 insn, see if we can get rid of that pseudo-register entirely
7355 by redirecting the previous insn into our reload register. */
7357 else if (optimize
&& REG_P (old
)
7358 && REGNO (old
) >= FIRST_PSEUDO_REGISTER
7359 && dead_or_set_p (insn
, old
)
7360 /* This is unsafe if some other reload
7361 uses the same reg first. */
7362 && ! conflicts_with_override (reloadreg
)
7363 && free_for_value_p (REGNO (reloadreg
), rl
->mode
, rl
->opnum
,
7364 rl
->when_needed
, old
, rl
->out
, j
, 0))
7366 rtx temp
= PREV_INSN (insn
);
7367 while (temp
&& (NOTE_P (temp
) || DEBUG_INSN_P (temp
)))
7368 temp
= PREV_INSN (temp
);
7370 && NONJUMP_INSN_P (temp
)
7371 && GET_CODE (PATTERN (temp
)) == SET
7372 && SET_DEST (PATTERN (temp
)) == old
7373 /* Make sure we can access insn_operand_constraint. */
7374 && asm_noperands (PATTERN (temp
)) < 0
7375 /* This is unsafe if operand occurs more than once in current
7376 insn. Perhaps some occurrences aren't reloaded. */
7377 && count_occurrences (PATTERN (insn
), old
, 0) == 1)
7379 rtx old
= SET_DEST (PATTERN (temp
));
7380 /* Store into the reload register instead of the pseudo. */
7381 SET_DEST (PATTERN (temp
)) = reloadreg
;
7383 /* Verify that resulting insn is valid.
7385 Note that we have replaced the destination of TEMP with
7386 RELOADREG. If TEMP references RELOADREG within an
7387 autoincrement addressing mode, then the resulting insn
7388 is ill-formed and we must reject this optimization. */
7389 extract_insn (temp
);
7390 if (constrain_operands (1)
7392 && ! find_reg_note (temp
, REG_INC
, reloadreg
)
7396 /* If the previous insn is an output reload, the source is
7397 a reload register, and its spill_reg_store entry will
7398 contain the previous destination. This is now
7400 if (REG_P (SET_SRC (PATTERN (temp
)))
7401 && REGNO (SET_SRC (PATTERN (temp
))) < FIRST_PSEUDO_REGISTER
)
7403 spill_reg_store
[REGNO (SET_SRC (PATTERN (temp
)))] = 0;
7404 spill_reg_stored_to
[REGNO (SET_SRC (PATTERN (temp
)))] = 0;
7407 /* If these are the only uses of the pseudo reg,
7408 pretend for GDB it lives in the reload reg we used. */
7409 if (REG_N_DEATHS (REGNO (old
)) == 1
7410 && REG_N_SETS (REGNO (old
)) == 1)
7412 reg_renumber
[REGNO (old
)] = REGNO (reloadreg
);
7413 if (ira_conflicts_p
)
7414 /* Inform IRA about the change. */
7415 ira_mark_allocation_change (REGNO (old
));
7416 alter_reg (REGNO (old
), -1, false);
7420 /* Adjust any debug insns between temp and insn. */
7421 while ((temp
= NEXT_INSN (temp
)) != insn
)
7422 if (DEBUG_INSN_P (temp
))
7423 replace_rtx (PATTERN (temp
), old
, reloadreg
);
7425 gcc_assert (NOTE_P (temp
));
7429 SET_DEST (PATTERN (temp
)) = old
;
7434 /* We can't do that, so output an insn to load RELOADREG. */
7436 /* If we have a secondary reload, pick up the secondary register
7437 and icode, if any. If OLDEQUIV and OLD are different or
7438 if this is an in-out reload, recompute whether or not we
7439 still need a secondary register and what the icode should
7440 be. If we still need a secondary register and the class or
7441 icode is different, go back to reloading from OLD if using
7442 OLDEQUIV means that we got the wrong type of register. We
7443 cannot have different class or icode due to an in-out reload
7444 because we don't make such reloads when both the input and
7445 output need secondary reload registers. */
7447 if (! special
&& rl
->secondary_in_reload
>= 0)
7449 rtx second_reload_reg
= 0;
7450 rtx third_reload_reg
= 0;
7451 int secondary_reload
= rl
->secondary_in_reload
;
7452 rtx real_oldequiv
= oldequiv
;
7455 enum insn_code icode
;
7456 enum insn_code tertiary_icode
= CODE_FOR_nothing
;
7458 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
7459 and similarly for OLD.
7460 See comments in get_secondary_reload in reload.c. */
7461 /* If it is a pseudo that cannot be replaced with its
7462 equivalent MEM, we must fall back to reload_in, which
7463 will have all the necessary substitutions registered.
7464 Likewise for a pseudo that can't be replaced with its
7465 equivalent constant.
7467 Take extra care for subregs of such pseudos. Note that
7468 we cannot use reg_equiv_mem in this case because it is
7469 not in the right mode. */
7472 if (GET_CODE (tmp
) == SUBREG
)
7473 tmp
= SUBREG_REG (tmp
);
7475 && REGNO (tmp
) >= FIRST_PSEUDO_REGISTER
7476 && (reg_equiv_memory_loc (REGNO (tmp
)) != 0
7477 || reg_equiv_constant (REGNO (tmp
)) != 0))
7479 if (! reg_equiv_mem (REGNO (tmp
))
7480 || num_not_at_initial_offset
7481 || GET_CODE (oldequiv
) == SUBREG
)
7482 real_oldequiv
= rl
->in
;
7484 real_oldequiv
= reg_equiv_mem (REGNO (tmp
));
7488 if (GET_CODE (tmp
) == SUBREG
)
7489 tmp
= SUBREG_REG (tmp
);
7491 && REGNO (tmp
) >= FIRST_PSEUDO_REGISTER
7492 && (reg_equiv_memory_loc (REGNO (tmp
)) != 0
7493 || reg_equiv_constant (REGNO (tmp
)) != 0))
7495 if (! reg_equiv_mem (REGNO (tmp
))
7496 || num_not_at_initial_offset
7497 || GET_CODE (old
) == SUBREG
)
7500 real_old
= reg_equiv_mem (REGNO (tmp
));
7503 second_reload_reg
= rld
[secondary_reload
].reg_rtx
;
7504 if (rld
[secondary_reload
].secondary_in_reload
>= 0)
7506 int tertiary_reload
= rld
[secondary_reload
].secondary_in_reload
;
7508 third_reload_reg
= rld
[tertiary_reload
].reg_rtx
;
7509 tertiary_icode
= rld
[secondary_reload
].secondary_in_icode
;
7510 /* We'd have to add more code for quartary reloads. */
7511 gcc_assert (rld
[tertiary_reload
].secondary_in_reload
< 0);
7513 icode
= rl
->secondary_in_icode
;
7515 if ((old
!= oldequiv
&& ! rtx_equal_p (old
, oldequiv
))
7516 || (rl
->in
!= 0 && rl
->out
!= 0))
7518 secondary_reload_info sri
, sri2
;
7519 enum reg_class new_class
, new_t_class
;
7521 sri
.icode
= CODE_FOR_nothing
;
7522 sri
.prev_sri
= NULL
;
7524 = (enum reg_class
) targetm
.secondary_reload (1, real_oldequiv
,
7528 if (new_class
== NO_REGS
&& sri
.icode
== CODE_FOR_nothing
)
7529 second_reload_reg
= 0;
7530 else if (new_class
== NO_REGS
)
7532 if (reload_adjust_reg_for_icode (&second_reload_reg
,
7534 (enum insn_code
) sri
.icode
))
7536 icode
= (enum insn_code
) sri
.icode
;
7537 third_reload_reg
= 0;
7542 real_oldequiv
= real_old
;
7545 else if (sri
.icode
!= CODE_FOR_nothing
)
7546 /* We currently lack a way to express this in reloads. */
7550 sri2
.icode
= CODE_FOR_nothing
;
7551 sri2
.prev_sri
= &sri
;
7553 = (enum reg_class
) targetm
.secondary_reload (1, real_oldequiv
,
7556 if (new_t_class
== NO_REGS
&& sri2
.icode
== CODE_FOR_nothing
)
7558 if (reload_adjust_reg_for_temp (&second_reload_reg
,
7562 third_reload_reg
= 0;
7563 tertiary_icode
= (enum insn_code
) sri2
.icode
;
7568 real_oldequiv
= real_old
;
7571 else if (new_t_class
== NO_REGS
&& sri2
.icode
!= CODE_FOR_nothing
)
7573 rtx intermediate
= second_reload_reg
;
7575 if (reload_adjust_reg_for_temp (&intermediate
, NULL
,
7577 && reload_adjust_reg_for_icode (&third_reload_reg
, NULL
,
7581 second_reload_reg
= intermediate
;
7582 tertiary_icode
= (enum insn_code
) sri2
.icode
;
7587 real_oldequiv
= real_old
;
7590 else if (new_t_class
!= NO_REGS
&& sri2
.icode
== CODE_FOR_nothing
)
7592 rtx intermediate
= second_reload_reg
;
7594 if (reload_adjust_reg_for_temp (&intermediate
, NULL
,
7596 && reload_adjust_reg_for_temp (&third_reload_reg
, NULL
,
7599 second_reload_reg
= intermediate
;
7600 tertiary_icode
= (enum insn_code
) sri2
.icode
;
7605 real_oldequiv
= real_old
;
7610 /* This could be handled more intelligently too. */
7612 real_oldequiv
= real_old
;
7617 /* If we still need a secondary reload register, check
7618 to see if it is being used as a scratch or intermediate
7619 register and generate code appropriately. If we need
7620 a scratch register, use REAL_OLDEQUIV since the form of
7621 the insn may depend on the actual address if it is
7624 if (second_reload_reg
)
7626 if (icode
!= CODE_FOR_nothing
)
7628 /* We'd have to add extra code to handle this case. */
7629 gcc_assert (!third_reload_reg
);
7631 emit_insn (GEN_FCN (icode
) (reloadreg
, real_oldequiv
,
7632 second_reload_reg
));
7637 /* See if we need a scratch register to load the
7638 intermediate register (a tertiary reload). */
7639 if (tertiary_icode
!= CODE_FOR_nothing
)
7641 emit_insn ((GEN_FCN (tertiary_icode
)
7642 (second_reload_reg
, real_oldequiv
,
7643 third_reload_reg
)));
7645 else if (third_reload_reg
)
7647 gen_reload (third_reload_reg
, real_oldequiv
,
7650 gen_reload (second_reload_reg
, third_reload_reg
,
7655 gen_reload (second_reload_reg
, real_oldequiv
,
7659 oldequiv
= second_reload_reg
;
7664 if (! special
&& ! rtx_equal_p (reloadreg
, oldequiv
))
7666 rtx real_oldequiv
= oldequiv
;
7668 if ((REG_P (oldequiv
)
7669 && REGNO (oldequiv
) >= FIRST_PSEUDO_REGISTER
7670 && (reg_equiv_memory_loc (REGNO (oldequiv
)) != 0
7671 || reg_equiv_constant (REGNO (oldequiv
)) != 0))
7672 || (GET_CODE (oldequiv
) == SUBREG
7673 && REG_P (SUBREG_REG (oldequiv
))
7674 && (REGNO (SUBREG_REG (oldequiv
))
7675 >= FIRST_PSEUDO_REGISTER
)
7676 && ((reg_equiv_memory_loc (REGNO (SUBREG_REG (oldequiv
))) != 0)
7677 || (reg_equiv_constant (REGNO (SUBREG_REG (oldequiv
))) != 0)))
7678 || (CONSTANT_P (oldequiv
)
7679 && (targetm
.preferred_reload_class (oldequiv
,
7680 REGNO_REG_CLASS (REGNO (reloadreg
)))
7682 real_oldequiv
= rl
->in
;
7683 gen_reload (reloadreg
, real_oldequiv
, rl
->opnum
,
7687 if (cfun
->can_throw_non_call_exceptions
)
7688 copy_reg_eh_region_note_forward (insn
, get_insns (), NULL
);
7690 /* End this sequence. */
7691 *where
= get_insns ();
7694 /* Update reload_override_in so that delete_address_reloads_1
7695 can see the actual register usage. */
7697 reload_override_in
[j
] = oldequiv
;
7700 /* Generate insns to for the output reload RL, which is for the insn described
7701 by CHAIN and has the number J. */
7703 emit_output_reload_insns (struct insn_chain
*chain
, struct reload
*rl
,
7707 rtx insn
= chain
->insn
;
7710 enum machine_mode mode
;
7714 if (rl
->when_needed
== RELOAD_OTHER
)
7717 push_to_sequence (output_reload_insns
[rl
->opnum
]);
7719 rl_reg_rtx
= reload_reg_rtx_for_output
[j
];
7720 mode
= GET_MODE (rl_reg_rtx
);
7722 reloadreg
= rl_reg_rtx
;
7724 /* If we need two reload regs, set RELOADREG to the intermediate
7725 one, since it will be stored into OLD. We might need a secondary
7726 register only for an input reload, so check again here. */
7728 if (rl
->secondary_out_reload
>= 0)
7731 int secondary_reload
= rl
->secondary_out_reload
;
7732 int tertiary_reload
= rld
[secondary_reload
].secondary_out_reload
;
7734 if (REG_P (old
) && REGNO (old
) >= FIRST_PSEUDO_REGISTER
7735 && reg_equiv_mem (REGNO (old
)) != 0)
7736 real_old
= reg_equiv_mem (REGNO (old
));
7738 if (secondary_reload_class (0, rl
->rclass
, mode
, real_old
) != NO_REGS
)
7740 rtx second_reloadreg
= reloadreg
;
7741 reloadreg
= rld
[secondary_reload
].reg_rtx
;
7743 /* See if RELOADREG is to be used as a scratch register
7744 or as an intermediate register. */
7745 if (rl
->secondary_out_icode
!= CODE_FOR_nothing
)
7747 /* We'd have to add extra code to handle this case. */
7748 gcc_assert (tertiary_reload
< 0);
7750 emit_insn ((GEN_FCN (rl
->secondary_out_icode
)
7751 (real_old
, second_reloadreg
, reloadreg
)));
7756 /* See if we need both a scratch and intermediate reload
7759 enum insn_code tertiary_icode
7760 = rld
[secondary_reload
].secondary_out_icode
;
7762 /* We'd have to add more code for quartary reloads. */
7763 gcc_assert (tertiary_reload
< 0
7764 || rld
[tertiary_reload
].secondary_out_reload
< 0);
7766 if (GET_MODE (reloadreg
) != mode
)
7767 reloadreg
= reload_adjust_reg_for_mode (reloadreg
, mode
);
7769 if (tertiary_icode
!= CODE_FOR_nothing
)
7771 rtx third_reloadreg
= rld
[tertiary_reload
].reg_rtx
;
7773 /* Copy primary reload reg to secondary reload reg.
7774 (Note that these have been swapped above, then
7775 secondary reload reg to OLD using our insn.) */
7777 /* If REAL_OLD is a paradoxical SUBREG, remove it
7778 and try to put the opposite SUBREG on
7780 strip_paradoxical_subreg (&real_old
, &reloadreg
);
7782 gen_reload (reloadreg
, second_reloadreg
,
7783 rl
->opnum
, rl
->when_needed
);
7784 emit_insn ((GEN_FCN (tertiary_icode
)
7785 (real_old
, reloadreg
, third_reloadreg
)));
7791 /* Copy between the reload regs here and then to
7794 gen_reload (reloadreg
, second_reloadreg
,
7795 rl
->opnum
, rl
->when_needed
);
7796 if (tertiary_reload
>= 0)
7798 rtx third_reloadreg
= rld
[tertiary_reload
].reg_rtx
;
7800 gen_reload (third_reloadreg
, reloadreg
,
7801 rl
->opnum
, rl
->when_needed
);
7802 reloadreg
= third_reloadreg
;
7809 /* Output the last reload insn. */
7814 /* Don't output the last reload if OLD is not the dest of
7815 INSN and is in the src and is clobbered by INSN. */
7816 if (! flag_expensive_optimizations
7818 || !(set
= single_set (insn
))
7819 || rtx_equal_p (old
, SET_DEST (set
))
7820 || !reg_mentioned_p (old
, SET_SRC (set
))
7821 || !((REGNO (old
) < FIRST_PSEUDO_REGISTER
)
7822 && regno_clobbered_p (REGNO (old
), insn
, rl
->mode
, 0)))
7823 gen_reload (old
, reloadreg
, rl
->opnum
,
7827 /* Look at all insns we emitted, just to be safe. */
7828 for (p
= get_insns (); p
; p
= NEXT_INSN (p
))
7831 rtx pat
= PATTERN (p
);
7833 /* If this output reload doesn't come from a spill reg,
7834 clear any memory of reloaded copies of the pseudo reg.
7835 If this output reload comes from a spill reg,
7836 reg_has_output_reload will make this do nothing. */
7837 note_stores (pat
, forget_old_reloads_1
, NULL
);
7839 if (reg_mentioned_p (rl_reg_rtx
, pat
))
7841 rtx set
= single_set (insn
);
7842 if (reload_spill_index
[j
] < 0
7844 && SET_SRC (set
) == rl_reg_rtx
)
7846 int src
= REGNO (SET_SRC (set
));
7848 reload_spill_index
[j
] = src
;
7849 SET_HARD_REG_BIT (reg_is_output_reload
, src
);
7850 if (find_regno_note (insn
, REG_DEAD
, src
))
7851 SET_HARD_REG_BIT (reg_reloaded_died
, src
);
7853 if (HARD_REGISTER_P (rl_reg_rtx
))
7855 int s
= rl
->secondary_out_reload
;
7856 set
= single_set (p
);
7857 /* If this reload copies only to the secondary reload
7858 register, the secondary reload does the actual
7860 if (s
>= 0 && set
== NULL_RTX
)
7861 /* We can't tell what function the secondary reload
7862 has and where the actual store to the pseudo is
7863 made; leave new_spill_reg_store alone. */
7866 && SET_SRC (set
) == rl_reg_rtx
7867 && SET_DEST (set
) == rld
[s
].reg_rtx
)
7869 /* Usually the next instruction will be the
7870 secondary reload insn; if we can confirm
7871 that it is, setting new_spill_reg_store to
7872 that insn will allow an extra optimization. */
7873 rtx s_reg
= rld
[s
].reg_rtx
;
7874 rtx next
= NEXT_INSN (p
);
7875 rld
[s
].out
= rl
->out
;
7876 rld
[s
].out_reg
= rl
->out_reg
;
7877 set
= single_set (next
);
7878 if (set
&& SET_SRC (set
) == s_reg
7879 && reload_reg_rtx_reaches_end_p (s_reg
, s
))
7881 SET_HARD_REG_BIT (reg_is_output_reload
,
7883 new_spill_reg_store
[REGNO (s_reg
)] = next
;
7886 else if (reload_reg_rtx_reaches_end_p (rl_reg_rtx
, j
))
7887 new_spill_reg_store
[REGNO (rl_reg_rtx
)] = p
;
7892 if (rl
->when_needed
== RELOAD_OTHER
)
7894 emit_insn (other_output_reload_insns
[rl
->opnum
]);
7895 other_output_reload_insns
[rl
->opnum
] = get_insns ();
7898 output_reload_insns
[rl
->opnum
] = get_insns ();
7900 if (cfun
->can_throw_non_call_exceptions
)
7901 copy_reg_eh_region_note_forward (insn
, get_insns (), NULL
);
7906 /* Do input reloading for reload RL, which is for the insn described by CHAIN
7907 and has the number J. */
7909 do_input_reload (struct insn_chain
*chain
, struct reload
*rl
, int j
)
7911 rtx insn
= chain
->insn
;
7912 rtx old
= (rl
->in
&& MEM_P (rl
->in
)
7913 ? rl
->in_reg
: rl
->in
);
7914 rtx reg_rtx
= rl
->reg_rtx
;
7918 enum machine_mode mode
;
7920 /* Determine the mode to reload in.
7921 This is very tricky because we have three to choose from.
7922 There is the mode the insn operand wants (rl->inmode).
7923 There is the mode of the reload register RELOADREG.
7924 There is the intrinsic mode of the operand, which we could find
7925 by stripping some SUBREGs.
7926 It turns out that RELOADREG's mode is irrelevant:
7927 we can change that arbitrarily.
7929 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
7930 then the reload reg may not support QImode moves, so use SImode.
7931 If foo is in memory due to spilling a pseudo reg, this is safe,
7932 because the QImode value is in the least significant part of a
7933 slot big enough for a SImode. If foo is some other sort of
7934 memory reference, then it is impossible to reload this case,
7935 so previous passes had better make sure this never happens.
7937 Then consider a one-word union which has SImode and one of its
7938 members is a float, being fetched as (SUBREG:SF union:SI).
7939 We must fetch that as SFmode because we could be loading into
7940 a float-only register. In this case OLD's mode is correct.
7942 Consider an immediate integer: it has VOIDmode. Here we need
7943 to get a mode from something else.
7945 In some cases, there is a fourth mode, the operand's
7946 containing mode. If the insn specifies a containing mode for
7947 this operand, it overrides all others.
7949 I am not sure whether the algorithm here is always right,
7950 but it does the right things in those cases. */
7952 mode
= GET_MODE (old
);
7953 if (mode
== VOIDmode
)
7956 /* We cannot use gen_lowpart_common since it can do the wrong thing
7957 when REG_RTX has a multi-word mode. Note that REG_RTX must
7958 always be a REG here. */
7959 if (GET_MODE (reg_rtx
) != mode
)
7960 reg_rtx
= reload_adjust_reg_for_mode (reg_rtx
, mode
);
7962 reload_reg_rtx_for_input
[j
] = reg_rtx
;
7965 /* AUTO_INC reloads need to be handled even if inherited. We got an
7966 AUTO_INC reload if reload_out is set but reload_out_reg isn't. */
7967 && (! reload_inherited
[j
] || (rl
->out
&& ! rl
->out_reg
))
7968 && ! rtx_equal_p (reg_rtx
, old
)
7970 emit_input_reload_insns (chain
, rld
+ j
, old
, j
);
7972 /* When inheriting a wider reload, we have a MEM in rl->in,
7973 e.g. inheriting a SImode output reload for
7974 (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */
7975 if (optimize
&& reload_inherited
[j
] && rl
->in
7977 && MEM_P (rl
->in_reg
)
7978 && reload_spill_index
[j
] >= 0
7979 && TEST_HARD_REG_BIT (reg_reloaded_valid
, reload_spill_index
[j
]))
7980 rl
->in
= regno_reg_rtx
[reg_reloaded_contents
[reload_spill_index
[j
]]];
7982 /* If we are reloading a register that was recently stored in with an
7983 output-reload, see if we can prove there was
7984 actually no need to store the old value in it. */
7987 && (reload_inherited
[j
] || reload_override_in
[j
])
7990 && spill_reg_store
[REGNO (reg_rtx
)] != 0
7992 /* There doesn't seem to be any reason to restrict this to pseudos
7993 and doing so loses in the case where we are copying from a
7994 register of the wrong class. */
7995 && !HARD_REGISTER_P (spill_reg_stored_to
[REGNO (reg_rtx
)])
7997 /* The insn might have already some references to stackslots
7998 replaced by MEMs, while reload_out_reg still names the
8000 && (dead_or_set_p (insn
, spill_reg_stored_to
[REGNO (reg_rtx
)])
8001 || rtx_equal_p (spill_reg_stored_to
[REGNO (reg_rtx
)], rl
->out_reg
)))
8002 delete_output_reload (insn
, j
, REGNO (reg_rtx
), reg_rtx
);
8005 /* Do output reloading for reload RL, which is for the insn described by
8006 CHAIN and has the number J.
8007 ??? At some point we need to support handling output reloads of
8008 JUMP_INSNs or insns that set cc0. */
8010 do_output_reload (struct insn_chain
*chain
, struct reload
*rl
, int j
)
8013 rtx insn
= chain
->insn
;
8014 /* If this is an output reload that stores something that is
8015 not loaded in this same reload, see if we can eliminate a previous
8017 rtx pseudo
= rl
->out_reg
;
8018 rtx reg_rtx
= rl
->reg_rtx
;
8020 if (rl
->out
&& reg_rtx
)
8022 enum machine_mode mode
;
8024 /* Determine the mode to reload in.
8025 See comments above (for input reloading). */
8026 mode
= GET_MODE (rl
->out
);
8027 if (mode
== VOIDmode
)
8029 /* VOIDmode should never happen for an output. */
8030 if (asm_noperands (PATTERN (insn
)) < 0)
8031 /* It's the compiler's fault. */
8032 fatal_insn ("VOIDmode on an output", insn
);
8033 error_for_asm (insn
, "output operand is constant in %<asm%>");
8034 /* Prevent crash--use something we know is valid. */
8036 rl
->out
= gen_rtx_REG (mode
, REGNO (reg_rtx
));
8038 if (GET_MODE (reg_rtx
) != mode
)
8039 reg_rtx
= reload_adjust_reg_for_mode (reg_rtx
, mode
);
8041 reload_reg_rtx_for_output
[j
] = reg_rtx
;
8046 && ! rtx_equal_p (rl
->in_reg
, pseudo
)
8047 && REGNO (pseudo
) >= FIRST_PSEUDO_REGISTER
8048 && reg_last_reload_reg
[REGNO (pseudo
)])
8050 int pseudo_no
= REGNO (pseudo
);
8051 int last_regno
= REGNO (reg_last_reload_reg
[pseudo_no
]);
8053 /* We don't need to test full validity of last_regno for
8054 inherit here; we only want to know if the store actually
8055 matches the pseudo. */
8056 if (TEST_HARD_REG_BIT (reg_reloaded_valid
, last_regno
)
8057 && reg_reloaded_contents
[last_regno
] == pseudo_no
8058 && spill_reg_store
[last_regno
]
8059 && rtx_equal_p (pseudo
, spill_reg_stored_to
[last_regno
]))
8060 delete_output_reload (insn
, j
, last_regno
, reg_rtx
);
8066 || rtx_equal_p (old
, reg_rtx
))
8069 /* An output operand that dies right away does need a reload,
8070 but need not be copied from it. Show the new location in the
8072 if ((REG_P (old
) || GET_CODE (old
) == SCRATCH
)
8073 && (note
= find_reg_note (insn
, REG_UNUSED
, old
)) != 0)
8075 XEXP (note
, 0) = reg_rtx
;
8078 /* Likewise for a SUBREG of an operand that dies. */
8079 else if (GET_CODE (old
) == SUBREG
8080 && REG_P (SUBREG_REG (old
))
8081 && 0 != (note
= find_reg_note (insn
, REG_UNUSED
,
8084 XEXP (note
, 0) = gen_lowpart_common (GET_MODE (old
), reg_rtx
);
8087 else if (GET_CODE (old
) == SCRATCH
)
8088 /* If we aren't optimizing, there won't be a REG_UNUSED note,
8089 but we don't want to make an output reload. */
8092 /* If is a JUMP_INSN, we can't support output reloads yet. */
8093 gcc_assert (NONJUMP_INSN_P (insn
));
8095 emit_output_reload_insns (chain
, rld
+ j
, j
);
8098 /* A reload copies values of MODE from register SRC to register DEST.
8099 Return true if it can be treated for inheritance purposes like a
8100 group of reloads, each one reloading a single hard register. The
8101 caller has already checked that (reg:MODE SRC) and (reg:MODE DEST)
8102 occupy the same number of hard registers. */
8105 inherit_piecemeal_p (int dest ATTRIBUTE_UNUSED
,
8106 int src ATTRIBUTE_UNUSED
,
8107 enum machine_mode mode ATTRIBUTE_UNUSED
)
8109 #ifdef CANNOT_CHANGE_MODE_CLASS
8110 return (!REG_CANNOT_CHANGE_MODE_P (dest
, mode
, reg_raw_mode
[dest
])
8111 && !REG_CANNOT_CHANGE_MODE_P (src
, mode
, reg_raw_mode
[src
]));
8117 /* Output insns to reload values in and out of the chosen reload regs. */
8120 emit_reload_insns (struct insn_chain
*chain
)
8122 rtx insn
= chain
->insn
;
8126 CLEAR_HARD_REG_SET (reg_reloaded_died
);
8128 for (j
= 0; j
< reload_n_operands
; j
++)
8129 input_reload_insns
[j
] = input_address_reload_insns
[j
]
8130 = inpaddr_address_reload_insns
[j
]
8131 = output_reload_insns
[j
] = output_address_reload_insns
[j
]
8132 = outaddr_address_reload_insns
[j
]
8133 = other_output_reload_insns
[j
] = 0;
8134 other_input_address_reload_insns
= 0;
8135 other_input_reload_insns
= 0;
8136 operand_reload_insns
= 0;
8137 other_operand_reload_insns
= 0;
8139 /* Dump reloads into the dump file. */
8142 fprintf (dump_file
, "\nReloads for insn # %d\n", INSN_UID (insn
));
8143 debug_reload_to_stream (dump_file
);
8146 for (j
= 0; j
< n_reloads
; j
++)
8147 if (rld
[j
].reg_rtx
&& HARD_REGISTER_P (rld
[j
].reg_rtx
))
8151 for (i
= REGNO (rld
[j
].reg_rtx
); i
< END_REGNO (rld
[j
].reg_rtx
); i
++)
8152 new_spill_reg_store
[i
] = 0;
8155 /* Now output the instructions to copy the data into and out of the
8156 reload registers. Do these in the order that the reloads were reported,
8157 since reloads of base and index registers precede reloads of operands
8158 and the operands may need the base and index registers reloaded. */
8160 for (j
= 0; j
< n_reloads
; j
++)
8162 do_input_reload (chain
, rld
+ j
, j
);
8163 do_output_reload (chain
, rld
+ j
, j
);
8166 /* Now write all the insns we made for reloads in the order expected by
8167 the allocation functions. Prior to the insn being reloaded, we write
8168 the following reloads:
8170 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
8172 RELOAD_OTHER reloads.
8174 For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
8175 by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
8176 RELOAD_FOR_INPUT reload for the operand.
8178 RELOAD_FOR_OPADDR_ADDRS reloads.
8180 RELOAD_FOR_OPERAND_ADDRESS reloads.
8182 After the insn being reloaded, we write the following:
8184 For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
8185 by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
8186 RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
8187 reloads for the operand. The RELOAD_OTHER output reloads are
8188 output in descending order by reload number. */
8190 emit_insn_before (other_input_address_reload_insns
, insn
);
8191 emit_insn_before (other_input_reload_insns
, insn
);
8193 for (j
= 0; j
< reload_n_operands
; j
++)
8195 emit_insn_before (inpaddr_address_reload_insns
[j
], insn
);
8196 emit_insn_before (input_address_reload_insns
[j
], insn
);
8197 emit_insn_before (input_reload_insns
[j
], insn
);
8200 emit_insn_before (other_operand_reload_insns
, insn
);
8201 emit_insn_before (operand_reload_insns
, insn
);
8203 for (j
= 0; j
< reload_n_operands
; j
++)
8205 rtx x
= emit_insn_after (outaddr_address_reload_insns
[j
], insn
);
8206 x
= emit_insn_after (output_address_reload_insns
[j
], x
);
8207 x
= emit_insn_after (output_reload_insns
[j
], x
);
8208 emit_insn_after (other_output_reload_insns
[j
], x
);
8211 /* For all the spill regs newly reloaded in this instruction,
8212 record what they were reloaded from, so subsequent instructions
8213 can inherit the reloads.
8215 Update spill_reg_store for the reloads of this insn.
8216 Copy the elements that were updated in the loop above. */
8218 for (j
= 0; j
< n_reloads
; j
++)
8220 int r
= reload_order
[j
];
8221 int i
= reload_spill_index
[r
];
8223 /* If this is a non-inherited input reload from a pseudo, we must
8224 clear any memory of a previous store to the same pseudo. Only do
8225 something if there will not be an output reload for the pseudo
8227 if (rld
[r
].in_reg
!= 0
8228 && ! (reload_inherited
[r
] || reload_override_in
[r
]))
8230 rtx reg
= rld
[r
].in_reg
;
8232 if (GET_CODE (reg
) == SUBREG
)
8233 reg
= SUBREG_REG (reg
);
8236 && REGNO (reg
) >= FIRST_PSEUDO_REGISTER
8237 && !REGNO_REG_SET_P (®_has_output_reload
, REGNO (reg
)))
8239 int nregno
= REGNO (reg
);
8241 if (reg_last_reload_reg
[nregno
])
8243 int last_regno
= REGNO (reg_last_reload_reg
[nregno
]);
8245 if (reg_reloaded_contents
[last_regno
] == nregno
)
8246 spill_reg_store
[last_regno
] = 0;
8251 /* I is nonneg if this reload used a register.
8252 If rld[r].reg_rtx is 0, this is an optional reload
8253 that we opted to ignore. */
8255 if (i
>= 0 && rld
[r
].reg_rtx
!= 0)
8257 int nr
= hard_regno_nregs
[i
][GET_MODE (rld
[r
].reg_rtx
)];
8260 /* For a multi register reload, we need to check if all or part
8261 of the value lives to the end. */
8262 for (k
= 0; k
< nr
; k
++)
8263 if (reload_reg_reaches_end_p (i
+ k
, r
))
8264 CLEAR_HARD_REG_BIT (reg_reloaded_valid
, i
+ k
);
8266 /* Maybe the spill reg contains a copy of reload_out. */
8268 && (REG_P (rld
[r
].out
)
8270 ? REG_P (rld
[r
].out_reg
)
8271 /* The reload value is an auto-modification of
8272 some kind. For PRE_INC, POST_INC, PRE_DEC
8273 and POST_DEC, we record an equivalence
8274 between the reload register and the operand
8275 on the optimistic assumption that we can make
8276 the equivalence hold. reload_as_needed must
8277 then either make it hold or invalidate the
8280 PRE_MODIFY and POST_MODIFY addresses are reloaded
8281 somewhat differently, and allowing them here leads
8283 : (GET_CODE (rld
[r
].out
) != POST_MODIFY
8284 && GET_CODE (rld
[r
].out
) != PRE_MODIFY
))))
8288 reg
= reload_reg_rtx_for_output
[r
];
8289 if (reload_reg_rtx_reaches_end_p (reg
, r
))
8291 enum machine_mode mode
= GET_MODE (reg
);
8292 int regno
= REGNO (reg
);
8293 int nregs
= hard_regno_nregs
[regno
][mode
];
8294 rtx out
= (REG_P (rld
[r
].out
)
8298 /* AUTO_INC */ : XEXP (rld
[r
].in_reg
, 0));
8299 int out_regno
= REGNO (out
);
8300 int out_nregs
= (!HARD_REGISTER_NUM_P (out_regno
) ? 1
8301 : hard_regno_nregs
[out_regno
][mode
]);
8304 spill_reg_store
[regno
] = new_spill_reg_store
[regno
];
8305 spill_reg_stored_to
[regno
] = out
;
8306 reg_last_reload_reg
[out_regno
] = reg
;
8308 piecemeal
= (HARD_REGISTER_NUM_P (out_regno
)
8309 && nregs
== out_nregs
8310 && inherit_piecemeal_p (out_regno
, regno
, mode
));
8312 /* If OUT_REGNO is a hard register, it may occupy more than
8313 one register. If it does, say what is in the
8314 rest of the registers assuming that both registers
8315 agree on how many words the object takes. If not,
8316 invalidate the subsequent registers. */
8318 if (HARD_REGISTER_NUM_P (out_regno
))
8319 for (k
= 1; k
< out_nregs
; k
++)
8320 reg_last_reload_reg
[out_regno
+ k
]
8321 = (piecemeal
? regno_reg_rtx
[regno
+ k
] : 0);
8323 /* Now do the inverse operation. */
8324 for (k
= 0; k
< nregs
; k
++)
8326 CLEAR_HARD_REG_BIT (reg_reloaded_dead
, regno
+ k
);
8327 reg_reloaded_contents
[regno
+ k
]
8328 = (!HARD_REGISTER_NUM_P (out_regno
) || !piecemeal
8331 reg_reloaded_insn
[regno
+ k
] = insn
;
8332 SET_HARD_REG_BIT (reg_reloaded_valid
, regno
+ k
);
8333 if (HARD_REGNO_CALL_PART_CLOBBERED (regno
+ k
, mode
))
8334 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered
,
8337 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered
,
8342 /* Maybe the spill reg contains a copy of reload_in. Only do
8343 something if there will not be an output reload for
8344 the register being reloaded. */
8345 else if (rld
[r
].out_reg
== 0
8347 && ((REG_P (rld
[r
].in
)
8348 && !HARD_REGISTER_P (rld
[r
].in
)
8349 && !REGNO_REG_SET_P (®_has_output_reload
,
8351 || (REG_P (rld
[r
].in_reg
)
8352 && !REGNO_REG_SET_P (®_has_output_reload
,
8353 REGNO (rld
[r
].in_reg
))))
8354 && !reg_set_p (reload_reg_rtx_for_input
[r
], PATTERN (insn
)))
8358 reg
= reload_reg_rtx_for_input
[r
];
8359 if (reload_reg_rtx_reaches_end_p (reg
, r
))
8361 enum machine_mode mode
;
8369 mode
= GET_MODE (reg
);
8370 regno
= REGNO (reg
);
8371 nregs
= hard_regno_nregs
[regno
][mode
];
8372 if (REG_P (rld
[r
].in
)
8373 && REGNO (rld
[r
].in
) >= FIRST_PSEUDO_REGISTER
)
8375 else if (REG_P (rld
[r
].in_reg
))
8378 in
= XEXP (rld
[r
].in_reg
, 0);
8379 in_regno
= REGNO (in
);
8381 in_nregs
= (!HARD_REGISTER_NUM_P (in_regno
) ? 1
8382 : hard_regno_nregs
[in_regno
][mode
]);
8384 reg_last_reload_reg
[in_regno
] = reg
;
8386 piecemeal
= (HARD_REGISTER_NUM_P (in_regno
)
8387 && nregs
== in_nregs
8388 && inherit_piecemeal_p (regno
, in_regno
, mode
));
8390 if (HARD_REGISTER_NUM_P (in_regno
))
8391 for (k
= 1; k
< in_nregs
; k
++)
8392 reg_last_reload_reg
[in_regno
+ k
]
8393 = (piecemeal
? regno_reg_rtx
[regno
+ k
] : 0);
8395 /* Unless we inherited this reload, show we haven't
8396 recently done a store.
8397 Previous stores of inherited auto_inc expressions
8398 also have to be discarded. */
8399 if (! reload_inherited
[r
]
8400 || (rld
[r
].out
&& ! rld
[r
].out_reg
))
8401 spill_reg_store
[regno
] = 0;
8403 for (k
= 0; k
< nregs
; k
++)
8405 CLEAR_HARD_REG_BIT (reg_reloaded_dead
, regno
+ k
);
8406 reg_reloaded_contents
[regno
+ k
]
8407 = (!HARD_REGISTER_NUM_P (in_regno
) || !piecemeal
8410 reg_reloaded_insn
[regno
+ k
] = insn
;
8411 SET_HARD_REG_BIT (reg_reloaded_valid
, regno
+ k
);
8412 if (HARD_REGNO_CALL_PART_CLOBBERED (regno
+ k
, mode
))
8413 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered
,
8416 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered
,
8423 /* The following if-statement was #if 0'd in 1.34 (or before...).
8424 It's reenabled in 1.35 because supposedly nothing else
8425 deals with this problem. */
8427 /* If a register gets output-reloaded from a non-spill register,
8428 that invalidates any previous reloaded copy of it.
8429 But forget_old_reloads_1 won't get to see it, because
8430 it thinks only about the original insn. So invalidate it here.
8431 Also do the same thing for RELOAD_OTHER constraints where the
8432 output is discarded. */
8434 && ((rld
[r
].out
!= 0
8435 && (REG_P (rld
[r
].out
)
8436 || (MEM_P (rld
[r
].out
)
8437 && REG_P (rld
[r
].out_reg
))))
8438 || (rld
[r
].out
== 0 && rld
[r
].out_reg
8439 && REG_P (rld
[r
].out_reg
))))
8441 rtx out
= ((rld
[r
].out
&& REG_P (rld
[r
].out
))
8442 ? rld
[r
].out
: rld
[r
].out_reg
);
8443 int out_regno
= REGNO (out
);
8444 enum machine_mode mode
= GET_MODE (out
);
8446 /* REG_RTX is now set or clobbered by the main instruction.
8447 As the comment above explains, forget_old_reloads_1 only
8448 sees the original instruction, and there is no guarantee
8449 that the original instruction also clobbered REG_RTX.
8450 For example, if find_reloads sees that the input side of
8451 a matched operand pair dies in this instruction, it may
8452 use the input register as the reload register.
8454 Calling forget_old_reloads_1 is a waste of effort if
8455 REG_RTX is also the output register.
8457 If we know that REG_RTX holds the value of a pseudo
8458 register, the code after the call will record that fact. */
8459 if (rld
[r
].reg_rtx
&& rld
[r
].reg_rtx
!= out
)
8460 forget_old_reloads_1 (rld
[r
].reg_rtx
, NULL_RTX
, NULL
);
8462 if (!HARD_REGISTER_NUM_P (out_regno
))
8464 rtx src_reg
, store_insn
= NULL_RTX
;
8466 reg_last_reload_reg
[out_regno
] = 0;
8468 /* If we can find a hard register that is stored, record
8469 the storing insn so that we may delete this insn with
8470 delete_output_reload. */
8471 src_reg
= reload_reg_rtx_for_output
[r
];
8475 if (reload_reg_rtx_reaches_end_p (src_reg
, r
))
8476 store_insn
= new_spill_reg_store
[REGNO (src_reg
)];
8482 /* If this is an optional reload, try to find the
8483 source reg from an input reload. */
8484 rtx set
= single_set (insn
);
8485 if (set
&& SET_DEST (set
) == rld
[r
].out
)
8489 src_reg
= SET_SRC (set
);
8491 for (k
= 0; k
< n_reloads
; k
++)
8493 if (rld
[k
].in
== src_reg
)
8495 src_reg
= reload_reg_rtx_for_input
[k
];
8501 if (src_reg
&& REG_P (src_reg
)
8502 && REGNO (src_reg
) < FIRST_PSEUDO_REGISTER
)
8504 int src_regno
, src_nregs
, k
;
8507 gcc_assert (GET_MODE (src_reg
) == mode
);
8508 src_regno
= REGNO (src_reg
);
8509 src_nregs
= hard_regno_nregs
[src_regno
][mode
];
8510 /* The place where to find a death note varies with
8511 PRESERVE_DEATH_INFO_REGNO_P . The condition is not
8512 necessarily checked exactly in the code that moves
8513 notes, so just check both locations. */
8514 note
= find_regno_note (insn
, REG_DEAD
, src_regno
);
8515 if (! note
&& store_insn
)
8516 note
= find_regno_note (store_insn
, REG_DEAD
, src_regno
);
8517 for (k
= 0; k
< src_nregs
; k
++)
8519 spill_reg_store
[src_regno
+ k
] = store_insn
;
8520 spill_reg_stored_to
[src_regno
+ k
] = out
;
8521 reg_reloaded_contents
[src_regno
+ k
] = out_regno
;
8522 reg_reloaded_insn
[src_regno
+ k
] = store_insn
;
8523 CLEAR_HARD_REG_BIT (reg_reloaded_dead
, src_regno
+ k
);
8524 SET_HARD_REG_BIT (reg_reloaded_valid
, src_regno
+ k
);
8525 if (HARD_REGNO_CALL_PART_CLOBBERED (src_regno
+ k
,
8527 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered
,
8530 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered
,
8532 SET_HARD_REG_BIT (reg_is_output_reload
, src_regno
+ k
);
8534 SET_HARD_REG_BIT (reg_reloaded_died
, src_regno
);
8536 CLEAR_HARD_REG_BIT (reg_reloaded_died
, src_regno
);
8538 reg_last_reload_reg
[out_regno
] = src_reg
;
8539 /* We have to set reg_has_output_reload here, or else
8540 forget_old_reloads_1 will clear reg_last_reload_reg
8542 SET_REGNO_REG_SET (®_has_output_reload
,
8548 int k
, out_nregs
= hard_regno_nregs
[out_regno
][mode
];
8550 for (k
= 0; k
< out_nregs
; k
++)
8551 reg_last_reload_reg
[out_regno
+ k
] = 0;
8555 IOR_HARD_REG_SET (reg_reloaded_dead
, reg_reloaded_died
);
8558 /* Go through the motions to emit INSN and test if it is strictly valid.
8559 Return the emitted insn if valid, else return NULL. */
8562 emit_insn_if_valid_for_reload (rtx insn
)
8564 rtx last
= get_last_insn ();
8567 insn
= emit_insn (insn
);
8568 code
= recog_memoized (insn
);
8572 extract_insn (insn
);
8573 /* We want constrain operands to treat this insn strictly in its
8574 validity determination, i.e., the way it would after reload has
8576 if (constrain_operands (1))
8580 delete_insns_since (last
);
8584 /* Emit code to perform a reload from IN (which may be a reload register) to
8585 OUT (which may also be a reload register). IN or OUT is from operand
8586 OPNUM with reload type TYPE.
8588 Returns first insn emitted. */
8591 gen_reload (rtx out
, rtx in
, int opnum
, enum reload_type type
)
8593 rtx last
= get_last_insn ();
8595 #ifdef SECONDARY_MEMORY_NEEDED
8599 /* If IN is a paradoxical SUBREG, remove it and try to put the
8600 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
8601 if (!strip_paradoxical_subreg (&in
, &out
))
8602 strip_paradoxical_subreg (&out
, &in
);
8604 /* How to do this reload can get quite tricky. Normally, we are being
8605 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
8606 register that didn't get a hard register. In that case we can just
8607 call emit_move_insn.
8609 We can also be asked to reload a PLUS that adds a register or a MEM to
8610 another register, constant or MEM. This can occur during frame pointer
8611 elimination and while reloading addresses. This case is handled by
8612 trying to emit a single insn to perform the add. If it is not valid,
8613 we use a two insn sequence.
8615 Or we can be asked to reload an unary operand that was a fragment of
8616 an addressing mode, into a register. If it isn't recognized as-is,
8617 we try making the unop operand and the reload-register the same:
8618 (set reg:X (unop:X expr:Y))
8619 -> (set reg:Y expr:Y) (set reg:X (unop:X reg:Y)).
8621 Finally, we could be called to handle an 'o' constraint by putting
8622 an address into a register. In that case, we first try to do this
8623 with a named pattern of "reload_load_address". If no such pattern
8624 exists, we just emit a SET insn and hope for the best (it will normally
8625 be valid on machines that use 'o').
8627 This entire process is made complex because reload will never
8628 process the insns we generate here and so we must ensure that
8629 they will fit their constraints and also by the fact that parts of
8630 IN might be being reloaded separately and replaced with spill registers.
8631 Because of this, we are, in some sense, just guessing the right approach
8632 here. The one listed above seems to work.
8634 ??? At some point, this whole thing needs to be rethought. */
8636 if (GET_CODE (in
) == PLUS
8637 && (REG_P (XEXP (in
, 0))
8638 || GET_CODE (XEXP (in
, 0)) == SUBREG
8639 || MEM_P (XEXP (in
, 0)))
8640 && (REG_P (XEXP (in
, 1))
8641 || GET_CODE (XEXP (in
, 1)) == SUBREG
8642 || CONSTANT_P (XEXP (in
, 1))
8643 || MEM_P (XEXP (in
, 1))))
8645 /* We need to compute the sum of a register or a MEM and another
8646 register, constant, or MEM, and put it into the reload
8647 register. The best possible way of doing this is if the machine
8648 has a three-operand ADD insn that accepts the required operands.
8650 The simplest approach is to try to generate such an insn and see if it
8651 is recognized and matches its constraints. If so, it can be used.
8653 It might be better not to actually emit the insn unless it is valid,
8654 but we need to pass the insn as an operand to `recog' and
8655 `extract_insn' and it is simpler to emit and then delete the insn if
8656 not valid than to dummy things up. */
8658 rtx op0
, op1
, tem
, insn
;
8659 enum insn_code code
;
8661 op0
= find_replacement (&XEXP (in
, 0));
8662 op1
= find_replacement (&XEXP (in
, 1));
8664 /* Since constraint checking is strict, commutativity won't be
8665 checked, so we need to do that here to avoid spurious failure
8666 if the add instruction is two-address and the second operand
8667 of the add is the same as the reload reg, which is frequently
8668 the case. If the insn would be A = B + A, rearrange it so
8669 it will be A = A + B as constrain_operands expects. */
8671 if (REG_P (XEXP (in
, 1))
8672 && REGNO (out
) == REGNO (XEXP (in
, 1)))
8673 tem
= op0
, op0
= op1
, op1
= tem
;
8675 if (op0
!= XEXP (in
, 0) || op1
!= XEXP (in
, 1))
8676 in
= gen_rtx_PLUS (GET_MODE (in
), op0
, op1
);
8678 insn
= emit_insn_if_valid_for_reload (gen_rtx_SET (VOIDmode
, out
, in
));
8682 /* If that failed, we must use a conservative two-insn sequence.
8684 Use a move to copy one operand into the reload register. Prefer
8685 to reload a constant, MEM or pseudo since the move patterns can
8686 handle an arbitrary operand. If OP1 is not a constant, MEM or
8687 pseudo and OP1 is not a valid operand for an add instruction, then
8690 After reloading one of the operands into the reload register, add
8691 the reload register to the output register.
8693 If there is another way to do this for a specific machine, a
8694 DEFINE_PEEPHOLE should be specified that recognizes the sequence
8697 code
= optab_handler (add_optab
, GET_MODE (out
));
8699 if (CONSTANT_P (op1
) || MEM_P (op1
) || GET_CODE (op1
) == SUBREG
8701 && REGNO (op1
) >= FIRST_PSEUDO_REGISTER
)
8702 || (code
!= CODE_FOR_nothing
8703 && !insn_operand_matches (code
, 2, op1
)))
8704 tem
= op0
, op0
= op1
, op1
= tem
;
8706 gen_reload (out
, op0
, opnum
, type
);
8708 /* If OP0 and OP1 are the same, we can use OUT for OP1.
8709 This fixes a problem on the 32K where the stack pointer cannot
8710 be used as an operand of an add insn. */
8712 if (rtx_equal_p (op0
, op1
))
8715 insn
= emit_insn_if_valid_for_reload (gen_add2_insn (out
, op1
));
8718 /* Add a REG_EQUIV note so that find_equiv_reg can find it. */
8719 set_dst_reg_note (insn
, REG_EQUIV
, in
, out
);
8723 /* If that failed, copy the address register to the reload register.
8724 Then add the constant to the reload register. */
8726 gcc_assert (!reg_overlap_mentioned_p (out
, op0
));
8727 gen_reload (out
, op1
, opnum
, type
);
8728 insn
= emit_insn (gen_add2_insn (out
, op0
));
8729 set_dst_reg_note (insn
, REG_EQUIV
, in
, out
);
8732 #ifdef SECONDARY_MEMORY_NEEDED
8733 /* If we need a memory location to do the move, do it that way. */
8734 else if ((tem1
= replaced_subreg (in
), tem2
= replaced_subreg (out
),
8735 (REG_P (tem1
) && REG_P (tem2
)))
8736 && REGNO (tem1
) < FIRST_PSEUDO_REGISTER
8737 && REGNO (tem2
) < FIRST_PSEUDO_REGISTER
8738 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (REGNO (tem1
)),
8739 REGNO_REG_CLASS (REGNO (tem2
)),
8742 /* Get the memory to use and rewrite both registers to its mode. */
8743 rtx loc
= get_secondary_mem (in
, GET_MODE (out
), opnum
, type
);
8745 if (GET_MODE (loc
) != GET_MODE (out
))
8746 out
= gen_rtx_REG (GET_MODE (loc
), reg_or_subregno (out
));
8748 if (GET_MODE (loc
) != GET_MODE (in
))
8749 in
= gen_rtx_REG (GET_MODE (loc
), reg_or_subregno (in
));
8751 gen_reload (loc
, in
, opnum
, type
);
8752 gen_reload (out
, loc
, opnum
, type
);
8755 else if (REG_P (out
) && UNARY_P (in
))
8762 op1
= find_replacement (&XEXP (in
, 0));
8763 if (op1
!= XEXP (in
, 0))
8764 in
= gen_rtx_fmt_e (GET_CODE (in
), GET_MODE (in
), op1
);
8766 /* First, try a plain SET. */
8767 set
= emit_insn_if_valid_for_reload (gen_rtx_SET (VOIDmode
, out
, in
));
8771 /* If that failed, move the inner operand to the reload
8772 register, and try the same unop with the inner expression
8773 replaced with the reload register. */
8775 if (GET_MODE (op1
) != GET_MODE (out
))
8776 out_moded
= gen_rtx_REG (GET_MODE (op1
), REGNO (out
));
8780 gen_reload (out_moded
, op1
, opnum
, type
);
8783 = gen_rtx_SET (VOIDmode
, out
,
8784 gen_rtx_fmt_e (GET_CODE (in
), GET_MODE (in
),
8786 insn
= emit_insn_if_valid_for_reload (insn
);
8789 set_unique_reg_note (insn
, REG_EQUIV
, in
);
8793 fatal_insn ("failure trying to reload:", set
);
8795 /* If IN is a simple operand, use gen_move_insn. */
8796 else if (OBJECT_P (in
) || GET_CODE (in
) == SUBREG
)
8798 tem
= emit_insn (gen_move_insn (out
, in
));
8799 /* IN may contain a LABEL_REF, if so add a REG_LABEL_OPERAND note. */
8800 mark_jump_label (in
, tem
, 0);
8803 #ifdef HAVE_reload_load_address
8804 else if (HAVE_reload_load_address
)
8805 emit_insn (gen_reload_load_address (out
, in
));
8808 /* Otherwise, just write (set OUT IN) and hope for the best. */
8810 emit_insn (gen_rtx_SET (VOIDmode
, out
, in
));
8812 /* Return the first insn emitted.
8813 We can not just return get_last_insn, because there may have
8814 been multiple instructions emitted. Also note that gen_move_insn may
8815 emit more than one insn itself, so we can not assume that there is one
8816 insn emitted per emit_insn_before call. */
8818 return last
? NEXT_INSN (last
) : get_insns ();
8821 /* Delete a previously made output-reload whose result we now believe
8822 is not needed. First we double-check.
8824 INSN is the insn now being processed.
8825 LAST_RELOAD_REG is the hard register number for which we want to delete
8826 the last output reload.
8827 J is the reload-number that originally used REG. The caller has made
8828 certain that reload J doesn't use REG any longer for input.
8829 NEW_RELOAD_REG is reload register that reload J is using for REG. */
8832 delete_output_reload (rtx insn
, int j
, int last_reload_reg
, rtx new_reload_reg
)
8834 rtx output_reload_insn
= spill_reg_store
[last_reload_reg
];
8835 rtx reg
= spill_reg_stored_to
[last_reload_reg
];
8838 int n_inherited
= 0;
8844 /* It is possible that this reload has been only used to set another reload
8845 we eliminated earlier and thus deleted this instruction too. */
8846 if (INSN_DELETED_P (output_reload_insn
))
8849 /* Get the raw pseudo-register referred to. */
8851 while (GET_CODE (reg
) == SUBREG
)
8852 reg
= SUBREG_REG (reg
);
8853 substed
= reg_equiv_memory_loc (REGNO (reg
));
8855 /* This is unsafe if the operand occurs more often in the current
8856 insn than it is inherited. */
8857 for (k
= n_reloads
- 1; k
>= 0; k
--)
8859 rtx reg2
= rld
[k
].in
;
8862 if (MEM_P (reg2
) || reload_override_in
[k
])
8863 reg2
= rld
[k
].in_reg
;
8865 if (rld
[k
].out
&& ! rld
[k
].out_reg
)
8866 reg2
= XEXP (rld
[k
].in_reg
, 0);
8868 while (GET_CODE (reg2
) == SUBREG
)
8869 reg2
= SUBREG_REG (reg2
);
8870 if (rtx_equal_p (reg2
, reg
))
8872 if (reload_inherited
[k
] || reload_override_in
[k
] || k
== j
)
8878 n_occurrences
= count_occurrences (PATTERN (insn
), reg
, 0);
8879 if (CALL_P (insn
) && CALL_INSN_FUNCTION_USAGE (insn
))
8880 n_occurrences
+= count_occurrences (CALL_INSN_FUNCTION_USAGE (insn
),
8883 n_occurrences
+= count_occurrences (PATTERN (insn
),
8884 eliminate_regs (substed
, VOIDmode
,
8886 for (i1
= reg_equiv_alt_mem_list (REGNO (reg
)); i1
; i1
= XEXP (i1
, 1))
8888 gcc_assert (!rtx_equal_p (XEXP (i1
, 0), substed
));
8889 n_occurrences
+= count_occurrences (PATTERN (insn
), XEXP (i1
, 0), 0);
8891 if (n_occurrences
> n_inherited
)
8894 regno
= REGNO (reg
);
8895 if (regno
>= FIRST_PSEUDO_REGISTER
)
8898 nregs
= hard_regno_nregs
[regno
][GET_MODE (reg
)];
8900 /* If the pseudo-reg we are reloading is no longer referenced
8901 anywhere between the store into it and here,
8902 and we're within the same basic block, then the value can only
8903 pass through the reload reg and end up here.
8904 Otherwise, give up--return. */
8905 for (i1
= NEXT_INSN (output_reload_insn
);
8906 i1
!= insn
; i1
= NEXT_INSN (i1
))
8908 if (NOTE_INSN_BASIC_BLOCK_P (i1
))
8910 if ((NONJUMP_INSN_P (i1
) || CALL_P (i1
))
8911 && refers_to_regno_p (regno
, regno
+ nregs
, PATTERN (i1
), NULL
))
8913 /* If this is USE in front of INSN, we only have to check that
8914 there are no more references than accounted for by inheritance. */
8915 while (NONJUMP_INSN_P (i1
) && GET_CODE (PATTERN (i1
)) == USE
)
8917 n_occurrences
+= rtx_equal_p (reg
, XEXP (PATTERN (i1
), 0)) != 0;
8918 i1
= NEXT_INSN (i1
);
8920 if (n_occurrences
<= n_inherited
&& i1
== insn
)
8926 /* We will be deleting the insn. Remove the spill reg information. */
8927 for (k
= hard_regno_nregs
[last_reload_reg
][GET_MODE (reg
)]; k
-- > 0; )
8929 spill_reg_store
[last_reload_reg
+ k
] = 0;
8930 spill_reg_stored_to
[last_reload_reg
+ k
] = 0;
8933 /* The caller has already checked that REG dies or is set in INSN.
8934 It has also checked that we are optimizing, and thus some
8935 inaccuracies in the debugging information are acceptable.
8936 So we could just delete output_reload_insn. But in some cases
8937 we can improve the debugging information without sacrificing
8938 optimization - maybe even improving the code: See if the pseudo
8939 reg has been completely replaced with reload regs. If so, delete
8940 the store insn and forget we had a stack slot for the pseudo. */
8941 if (rld
[j
].out
!= rld
[j
].in
8942 && REG_N_DEATHS (REGNO (reg
)) == 1
8943 && REG_N_SETS (REGNO (reg
)) == 1
8944 && REG_BASIC_BLOCK (REGNO (reg
)) >= NUM_FIXED_BLOCKS
8945 && find_regno_note (insn
, REG_DEAD
, REGNO (reg
)))
8949 /* We know that it was used only between here and the beginning of
8950 the current basic block. (We also know that the last use before
8951 INSN was the output reload we are thinking of deleting, but never
8952 mind that.) Search that range; see if any ref remains. */
8953 for (i2
= PREV_INSN (insn
); i2
; i2
= PREV_INSN (i2
))
8955 rtx set
= single_set (i2
);
8957 /* Uses which just store in the pseudo don't count,
8958 since if they are the only uses, they are dead. */
8959 if (set
!= 0 && SET_DEST (set
) == reg
)
8961 if (LABEL_P (i2
) || JUMP_P (i2
))
8963 if ((NONJUMP_INSN_P (i2
) || CALL_P (i2
))
8964 && reg_mentioned_p (reg
, PATTERN (i2
)))
8966 /* Some other ref remains; just delete the output reload we
8968 delete_address_reloads (output_reload_insn
, insn
);
8969 delete_insn (output_reload_insn
);
8974 /* Delete the now-dead stores into this pseudo. Note that this
8975 loop also takes care of deleting output_reload_insn. */
8976 for (i2
= PREV_INSN (insn
); i2
; i2
= PREV_INSN (i2
))
8978 rtx set
= single_set (i2
);
8980 if (set
!= 0 && SET_DEST (set
) == reg
)
8982 delete_address_reloads (i2
, insn
);
8985 if (LABEL_P (i2
) || JUMP_P (i2
))
8989 /* For the debugging info, say the pseudo lives in this reload reg. */
8990 reg_renumber
[REGNO (reg
)] = REGNO (new_reload_reg
);
8991 if (ira_conflicts_p
)
8992 /* Inform IRA about the change. */
8993 ira_mark_allocation_change (REGNO (reg
));
8994 alter_reg (REGNO (reg
), -1, false);
8998 delete_address_reloads (output_reload_insn
, insn
);
8999 delete_insn (output_reload_insn
);
9003 /* We are going to delete DEAD_INSN. Recursively delete loads of
9004 reload registers used in DEAD_INSN that are not used till CURRENT_INSN.
9005 CURRENT_INSN is being reloaded, so we have to check its reloads too. */
9007 delete_address_reloads (rtx dead_insn
, rtx current_insn
)
9009 rtx set
= single_set (dead_insn
);
9010 rtx set2
, dst
, prev
, next
;
9013 rtx dst
= SET_DEST (set
);
9015 delete_address_reloads_1 (dead_insn
, XEXP (dst
, 0), current_insn
);
9017 /* If we deleted the store from a reloaded post_{in,de}c expression,
9018 we can delete the matching adds. */
9019 prev
= PREV_INSN (dead_insn
);
9020 next
= NEXT_INSN (dead_insn
);
9021 if (! prev
|| ! next
)
9023 set
= single_set (next
);
9024 set2
= single_set (prev
);
9026 || GET_CODE (SET_SRC (set
)) != PLUS
|| GET_CODE (SET_SRC (set2
)) != PLUS
9027 || !CONST_INT_P (XEXP (SET_SRC (set
), 1))
9028 || !CONST_INT_P (XEXP (SET_SRC (set2
), 1)))
9030 dst
= SET_DEST (set
);
9031 if (! rtx_equal_p (dst
, SET_DEST (set2
))
9032 || ! rtx_equal_p (dst
, XEXP (SET_SRC (set
), 0))
9033 || ! rtx_equal_p (dst
, XEXP (SET_SRC (set2
), 0))
9034 || (INTVAL (XEXP (SET_SRC (set
), 1))
9035 != -INTVAL (XEXP (SET_SRC (set2
), 1))))
9037 delete_related_insns (prev
);
9038 delete_related_insns (next
);
9041 /* Subfunction of delete_address_reloads: process registers found in X. */
9043 delete_address_reloads_1 (rtx dead_insn
, rtx x
, rtx current_insn
)
9045 rtx prev
, set
, dst
, i2
;
9047 enum rtx_code code
= GET_CODE (x
);
9051 const char *fmt
= GET_RTX_FORMAT (code
);
9052 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
9055 delete_address_reloads_1 (dead_insn
, XEXP (x
, i
), current_insn
);
9056 else if (fmt
[i
] == 'E')
9058 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
9059 delete_address_reloads_1 (dead_insn
, XVECEXP (x
, i
, j
),
9066 if (spill_reg_order
[REGNO (x
)] < 0)
9069 /* Scan backwards for the insn that sets x. This might be a way back due
9071 for (prev
= PREV_INSN (dead_insn
); prev
; prev
= PREV_INSN (prev
))
9073 code
= GET_CODE (prev
);
9074 if (code
== CODE_LABEL
|| code
== JUMP_INSN
)
9078 if (reg_set_p (x
, PATTERN (prev
)))
9080 if (reg_referenced_p (x
, PATTERN (prev
)))
9083 if (! prev
|| INSN_UID (prev
) < reload_first_uid
)
9085 /* Check that PREV only sets the reload register. */
9086 set
= single_set (prev
);
9089 dst
= SET_DEST (set
);
9091 || ! rtx_equal_p (dst
, x
))
9093 if (! reg_set_p (dst
, PATTERN (dead_insn
)))
9095 /* Check if DST was used in a later insn -
9096 it might have been inherited. */
9097 for (i2
= NEXT_INSN (dead_insn
); i2
; i2
= NEXT_INSN (i2
))
9103 if (reg_referenced_p (dst
, PATTERN (i2
)))
9105 /* If there is a reference to the register in the current insn,
9106 it might be loaded in a non-inherited reload. If no other
9107 reload uses it, that means the register is set before
9109 if (i2
== current_insn
)
9111 for (j
= n_reloads
- 1; j
>= 0; j
--)
9112 if ((rld
[j
].reg_rtx
== dst
&& reload_inherited
[j
])
9113 || reload_override_in
[j
] == dst
)
9115 for (j
= n_reloads
- 1; j
>= 0; j
--)
9116 if (rld
[j
].in
&& rld
[j
].reg_rtx
== dst
)
9125 /* If DST is still live at CURRENT_INSN, check if it is used for
9126 any reload. Note that even if CURRENT_INSN sets DST, we still
9127 have to check the reloads. */
9128 if (i2
== current_insn
)
9130 for (j
= n_reloads
- 1; j
>= 0; j
--)
9131 if ((rld
[j
].reg_rtx
== dst
&& reload_inherited
[j
])
9132 || reload_override_in
[j
] == dst
)
9134 /* ??? We can't finish the loop here, because dst might be
9135 allocated to a pseudo in this block if no reload in this
9136 block needs any of the classes containing DST - see
9137 spill_hard_reg. There is no easy way to tell this, so we
9138 have to scan till the end of the basic block. */
9140 if (reg_set_p (dst
, PATTERN (i2
)))
9144 delete_address_reloads_1 (prev
, SET_SRC (set
), current_insn
);
9145 reg_reloaded_contents
[REGNO (dst
)] = -1;
9149 /* Output reload-insns to reload VALUE into RELOADREG.
9150 VALUE is an autoincrement or autodecrement RTX whose operand
9151 is a register or memory location;
9152 so reloading involves incrementing that location.
9153 IN is either identical to VALUE, or some cheaper place to reload from.
9155 INC_AMOUNT is the number to increment or decrement by (always positive).
9156 This cannot be deduced from VALUE. */
9159 inc_for_reload (rtx reloadreg
, rtx in
, rtx value
, int inc_amount
)
9161 /* REG or MEM to be copied and incremented. */
9162 rtx incloc
= find_replacement (&XEXP (value
, 0));
9163 /* Nonzero if increment after copying. */
9164 int post
= (GET_CODE (value
) == POST_DEC
|| GET_CODE (value
) == POST_INC
9165 || GET_CODE (value
) == POST_MODIFY
);
9170 rtx real_in
= in
== value
? incloc
: in
;
9172 /* No hard register is equivalent to this register after
9173 inc/dec operation. If REG_LAST_RELOAD_REG were nonzero,
9174 we could inc/dec that register as well (maybe even using it for
9175 the source), but I'm not sure it's worth worrying about. */
9177 reg_last_reload_reg
[REGNO (incloc
)] = 0;
9179 if (GET_CODE (value
) == PRE_MODIFY
|| GET_CODE (value
) == POST_MODIFY
)
9181 gcc_assert (GET_CODE (XEXP (value
, 1)) == PLUS
);
9182 inc
= find_replacement (&XEXP (XEXP (value
, 1), 1));
9186 if (GET_CODE (value
) == PRE_DEC
|| GET_CODE (value
) == POST_DEC
)
9187 inc_amount
= -inc_amount
;
9189 inc
= GEN_INT (inc_amount
);
9192 /* If this is post-increment, first copy the location to the reload reg. */
9193 if (post
&& real_in
!= reloadreg
)
9194 emit_insn (gen_move_insn (reloadreg
, real_in
));
9198 /* See if we can directly increment INCLOC. Use a method similar to
9199 that in gen_reload. */
9201 last
= get_last_insn ();
9202 add_insn
= emit_insn (gen_rtx_SET (VOIDmode
, incloc
,
9203 gen_rtx_PLUS (GET_MODE (incloc
),
9206 code
= recog_memoized (add_insn
);
9209 extract_insn (add_insn
);
9210 if (constrain_operands (1))
9212 /* If this is a pre-increment and we have incremented the value
9213 where it lives, copy the incremented value to RELOADREG to
9214 be used as an address. */
9217 emit_insn (gen_move_insn (reloadreg
, incloc
));
9221 delete_insns_since (last
);
9224 /* If couldn't do the increment directly, must increment in RELOADREG.
9225 The way we do this depends on whether this is pre- or post-increment.
9226 For pre-increment, copy INCLOC to the reload register, increment it
9227 there, then save back. */
9231 if (in
!= reloadreg
)
9232 emit_insn (gen_move_insn (reloadreg
, real_in
));
9233 emit_insn (gen_add2_insn (reloadreg
, inc
));
9234 emit_insn (gen_move_insn (incloc
, reloadreg
));
9239 Because this might be a jump insn or a compare, and because RELOADREG
9240 may not be available after the insn in an input reload, we must do
9241 the incrementation before the insn being reloaded for.
9243 We have already copied IN to RELOADREG. Increment the copy in
9244 RELOADREG, save that back, then decrement RELOADREG so it has
9245 the original value. */
9247 emit_insn (gen_add2_insn (reloadreg
, inc
));
9248 emit_insn (gen_move_insn (incloc
, reloadreg
));
9249 if (CONST_INT_P (inc
))
9250 emit_insn (gen_add2_insn (reloadreg
,
9251 gen_int_mode (-INTVAL (inc
),
9252 GET_MODE (reloadreg
))));
9254 emit_insn (gen_sub2_insn (reloadreg
, inc
));
9260 add_auto_inc_notes (rtx insn
, rtx x
)
9262 enum rtx_code code
= GET_CODE (x
);
9266 if (code
== MEM
&& auto_inc_p (XEXP (x
, 0)))
9268 add_reg_note (insn
, REG_INC
, XEXP (XEXP (x
, 0), 0));
9272 /* Scan all the operand sub-expressions. */
9273 fmt
= GET_RTX_FORMAT (code
);
9274 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
9277 add_auto_inc_notes (insn
, XEXP (x
, i
));
9278 else if (fmt
[i
] == 'E')
9279 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
9280 add_auto_inc_notes (insn
, XVECEXP (x
, i
, j
));