1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006 Free Software Foundation,
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 2, or (at your option) any later
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING. If not, write to the Free
20 Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
25 #include "coretypes.h"
29 #include "hard-reg-set.h"
33 #include "insn-config.h"
39 #include "addresses.h"
40 #include "basic-block.h"
50 /* This file contains the reload pass of the compiler, which is
51 run after register allocation has been done. It checks that
52 each insn is valid (operands required to be in registers really
53 are in registers of the proper class) and fixes up invalid ones
54 by copying values temporarily into registers for the insns
57 The results of register allocation are described by the vector
58 reg_renumber; the insns still contain pseudo regs, but reg_renumber
59 can be used to find which hard reg, if any, a pseudo reg is in.
61 The technique we always use is to free up a few hard regs that are
62 called ``reload regs'', and for each place where a pseudo reg
63 must be in a hard reg, copy it temporarily into one of the reload regs.
65 Reload regs are allocated locally for every instruction that needs
66 reloads. When there are pseudos which are allocated to a register that
67 has been chosen as a reload reg, such pseudos must be ``spilled''.
68 This means that they go to other hard regs, or to stack slots if no other
69 available hard regs can be found. Spilling can invalidate more
70 insns, requiring additional need for reloads, so we must keep checking
71 until the process stabilizes.
73 For machines with different classes of registers, we must keep track
74 of the register class needed for each reload, and make sure that
75 we allocate enough reload registers of each class.
77 The file reload.c contains the code that checks one insn for
78 validity and reports the reloads that it needs. This file
79 is in charge of scanning the entire rtl code, accumulating the
80 reload needs, spilling, assigning reload registers to use for
81 fixing up each insn, and generating the new insns to copy values
82 into the reload registers. */
84 /* During reload_as_needed, element N contains a REG rtx for the hard reg
85 into which reg N has been reloaded (perhaps for a previous insn). */
86 static rtx
*reg_last_reload_reg
;
88 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
89 for an output reload that stores into reg N. */
90 static char *reg_has_output_reload
;
92 /* Indicates which hard regs are reload-registers for an output reload
93 in the current insn. */
94 static HARD_REG_SET reg_is_output_reload
;
96 /* Element N is the constant value to which pseudo reg N is equivalent,
97 or zero if pseudo reg N is not equivalent to a constant.
98 find_reloads looks at this in order to replace pseudo reg N
99 with the constant it stands for. */
100 rtx
*reg_equiv_constant
;
102 /* Element N is an invariant value to which pseudo reg N is equivalent.
103 eliminate_regs_in_insn uses this to replace pseudos in particular
105 rtx
*reg_equiv_invariant
;
107 /* Element N is a memory location to which pseudo reg N is equivalent,
108 prior to any register elimination (such as frame pointer to stack
109 pointer). Depending on whether or not it is a valid address, this value
110 is transferred to either reg_equiv_address or reg_equiv_mem. */
111 rtx
*reg_equiv_memory_loc
;
113 /* We allocate reg_equiv_memory_loc inside a varray so that the garbage
114 collector can keep track of what is inside. */
115 varray_type reg_equiv_memory_loc_varray
;
117 /* Element N is the address of stack slot to which pseudo reg N is equivalent.
118 This is used when the address is not valid as a memory address
119 (because its displacement is too big for the machine.) */
120 rtx
*reg_equiv_address
;
122 /* Element N is the memory slot to which pseudo reg N is equivalent,
123 or zero if pseudo reg N is not equivalent to a memory slot. */
126 /* Widest width in which each pseudo reg is referred to (via subreg). */
127 static unsigned int *reg_max_ref_width
;
129 /* Element N is the list of insns that initialized reg N from its equivalent
130 constant or memory slot. */
132 int reg_equiv_init_size
;
134 /* Vector to remember old contents of reg_renumber before spilling. */
135 static short *reg_old_renumber
;
137 /* During reload_as_needed, element N contains the last pseudo regno reloaded
138 into hard register N. If that pseudo reg occupied more than one register,
139 reg_reloaded_contents points to that pseudo for each spill register in
140 use; all of these must remain set for an inheritance to occur. */
141 static int reg_reloaded_contents
[FIRST_PSEUDO_REGISTER
];
143 /* During reload_as_needed, element N contains the insn for which
144 hard register N was last used. Its contents are significant only
145 when reg_reloaded_valid is set for this register. */
146 static rtx reg_reloaded_insn
[FIRST_PSEUDO_REGISTER
];
148 /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid. */
149 static HARD_REG_SET reg_reloaded_valid
;
150 /* Indicate if the register was dead at the end of the reload.
151 This is only valid if reg_reloaded_contents is set and valid. */
152 static HARD_REG_SET reg_reloaded_dead
;
154 /* Indicate whether the register's current value is one that is not
155 safe to retain across a call, even for registers that are normally
157 static HARD_REG_SET reg_reloaded_call_part_clobbered
;
159 /* Number of spill-regs so far; number of valid elements of spill_regs. */
162 /* In parallel with spill_regs, contains REG rtx's for those regs.
163 Holds the last rtx used for any given reg, or 0 if it has never
164 been used for spilling yet. This rtx is reused, provided it has
166 static rtx spill_reg_rtx
[FIRST_PSEUDO_REGISTER
];
168 /* In parallel with spill_regs, contains nonzero for a spill reg
169 that was stored after the last time it was used.
170 The precise value is the insn generated to do the store. */
171 static rtx spill_reg_store
[FIRST_PSEUDO_REGISTER
];
173 /* This is the register that was stored with spill_reg_store. This is a
174 copy of reload_out / reload_out_reg when the value was stored; if
175 reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */
176 static rtx spill_reg_stored_to
[FIRST_PSEUDO_REGISTER
];
178 /* This table is the inverse mapping of spill_regs:
179 indexed by hard reg number,
180 it contains the position of that reg in spill_regs,
181 or -1 for something that is not in spill_regs.
183 ?!? This is no longer accurate. */
184 static short spill_reg_order
[FIRST_PSEUDO_REGISTER
];
186 /* This reg set indicates registers that can't be used as spill registers for
187 the currently processed insn. These are the hard registers which are live
188 during the insn, but not allocated to pseudos, as well as fixed
190 static HARD_REG_SET bad_spill_regs
;
192 /* These are the hard registers that can't be used as spill register for any
193 insn. This includes registers used for user variables and registers that
194 we can't eliminate. A register that appears in this set also can't be used
195 to retry register allocation. */
196 static HARD_REG_SET bad_spill_regs_global
;
198 /* Describes order of use of registers for reloading
199 of spilled pseudo-registers. `n_spills' is the number of
200 elements that are actually valid; new ones are added at the end.
202 Both spill_regs and spill_reg_order are used on two occasions:
203 once during find_reload_regs, where they keep track of the spill registers
204 for a single insn, but also during reload_as_needed where they show all
205 the registers ever used by reload. For the latter case, the information
206 is calculated during finish_spills. */
207 static short spill_regs
[FIRST_PSEUDO_REGISTER
];
209 /* This vector of reg sets indicates, for each pseudo, which hard registers
210 may not be used for retrying global allocation because the register was
211 formerly spilled from one of them. If we allowed reallocating a pseudo to
212 a register that it was already allocated to, reload might not
214 static HARD_REG_SET
*pseudo_previous_regs
;
216 /* This vector of reg sets indicates, for each pseudo, which hard
217 registers may not be used for retrying global allocation because they
218 are used as spill registers during one of the insns in which the
220 static HARD_REG_SET
*pseudo_forbidden_regs
;
222 /* All hard regs that have been used as spill registers for any insn are
223 marked in this set. */
224 static HARD_REG_SET used_spill_regs
;
226 /* Index of last register assigned as a spill register. We allocate in
227 a round-robin fashion. */
228 static int last_spill_reg
;
230 /* Nonzero if indirect addressing is supported on the machine; this means
231 that spilling (REG n) does not require reloading it into a register in
232 order to do (MEM (REG n)) or (MEM (PLUS (REG n) (CONST_INT c))). The
233 value indicates the level of indirect addressing supported, e.g., two
234 means that (MEM (MEM (REG n))) is also valid if (REG n) does not get
236 static char spill_indirect_levels
;
238 /* Nonzero if indirect addressing is supported when the innermost MEM is
239 of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to
240 which these are valid is the same as spill_indirect_levels, above. */
241 char indirect_symref_ok
;
243 /* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */
244 char double_reg_address_ok
;
246 /* Record the stack slot for each spilled hard register. */
247 static rtx spill_stack_slot
[FIRST_PSEUDO_REGISTER
];
249 /* Width allocated so far for that stack slot. */
250 static unsigned int spill_stack_slot_width
[FIRST_PSEUDO_REGISTER
];
252 /* Record which pseudos needed to be spilled. */
253 static regset_head spilled_pseudos
;
255 /* Used for communication between order_regs_for_reload and count_pseudo.
256 Used to avoid counting one pseudo twice. */
257 static regset_head pseudos_counted
;
259 /* First uid used by insns created by reload in this function.
260 Used in find_equiv_reg. */
261 int reload_first_uid
;
263 /* Flag set by local-alloc or global-alloc if anything is live in
264 a call-clobbered reg across calls. */
265 int caller_save_needed
;
267 /* Set to 1 while reload_as_needed is operating.
268 Required by some machines to handle any generated moves differently. */
269 int reload_in_progress
= 0;
271 /* These arrays record the insn_code of insns that may be needed to
272 perform input and output reloads of special objects. They provide a
273 place to pass a scratch register. */
274 enum insn_code reload_in_optab
[NUM_MACHINE_MODES
];
275 enum insn_code reload_out_optab
[NUM_MACHINE_MODES
];
277 /* This obstack is used for allocation of rtl during register elimination.
278 The allocated storage can be freed once find_reloads has processed the
280 static struct obstack reload_obstack
;
282 /* Points to the beginning of the reload_obstack. All insn_chain structures
283 are allocated first. */
284 static char *reload_startobj
;
286 /* The point after all insn_chain structures. Used to quickly deallocate
287 memory allocated in copy_reloads during calculate_needs_all_insns. */
288 static char *reload_firstobj
;
290 /* This points before all local rtl generated by register elimination.
291 Used to quickly free all memory after processing one insn. */
292 static char *reload_insn_firstobj
;
294 /* List of insn_chain instructions, one for every insn that reload needs to
296 struct insn_chain
*reload_insn_chain
;
298 /* List of all insns needing reloads. */
299 static struct insn_chain
*insns_need_reload
;
301 /* This structure is used to record information about register eliminations.
302 Each array entry describes one possible way of eliminating a register
303 in favor of another. If there is more than one way of eliminating a
304 particular register, the most preferred should be specified first. */
308 int from
; /* Register number to be eliminated. */
309 int to
; /* Register number used as replacement. */
310 HOST_WIDE_INT initial_offset
; /* Initial difference between values. */
311 int can_eliminate
; /* Nonzero if this elimination can be done. */
312 int can_eliminate_previous
; /* Value of CAN_ELIMINATE in previous scan over
313 insns made by reload. */
314 HOST_WIDE_INT offset
; /* Current offset between the two regs. */
315 HOST_WIDE_INT previous_offset
;/* Offset at end of previous insn. */
316 int ref_outside_mem
; /* "to" has been referenced outside a MEM. */
317 rtx from_rtx
; /* REG rtx for the register to be eliminated.
318 We cannot simply compare the number since
319 we might then spuriously replace a hard
320 register corresponding to a pseudo
321 assigned to the reg to be eliminated. */
322 rtx to_rtx
; /* REG rtx for the replacement. */
325 static struct elim_table
*reg_eliminate
= 0;
327 /* This is an intermediate structure to initialize the table. It has
328 exactly the members provided by ELIMINABLE_REGS. */
329 static const struct elim_table_1
333 } reg_eliminate_1
[] =
335 /* If a set of eliminable registers was specified, define the table from it.
336 Otherwise, default to the normal case of the frame pointer being
337 replaced by the stack pointer. */
339 #ifdef ELIMINABLE_REGS
342 {{ FRAME_POINTER_REGNUM
, STACK_POINTER_REGNUM
}};
345 #define NUM_ELIMINABLE_REGS ARRAY_SIZE (reg_eliminate_1)
347 /* Record the number of pending eliminations that have an offset not equal
348 to their initial offset. If nonzero, we use a new copy of each
349 replacement result in any insns encountered. */
350 int num_not_at_initial_offset
;
352 /* Count the number of registers that we may be able to eliminate. */
353 static int num_eliminable
;
354 /* And the number of registers that are equivalent to a constant that
355 can be eliminated to frame_pointer / arg_pointer + constant. */
356 static int num_eliminable_invariants
;
358 /* For each label, we record the offset of each elimination. If we reach
359 a label by more than one path and an offset differs, we cannot do the
360 elimination. This information is indexed by the difference of the
361 number of the label and the first label number. We can't offset the
362 pointer itself as this can cause problems on machines with segmented
363 memory. The first table is an array of flags that records whether we
364 have yet encountered a label and the second table is an array of arrays,
365 one entry in the latter array for each elimination. */
367 static int first_label_num
;
368 static char *offsets_known_at
;
369 static HOST_WIDE_INT (*offsets_at
)[NUM_ELIMINABLE_REGS
];
371 /* Number of labels in the current function. */
373 static int num_labels
;
375 static void replace_pseudos_in (rtx
*, enum machine_mode
, rtx
);
376 static void maybe_fix_stack_asms (void);
377 static void copy_reloads (struct insn_chain
*);
378 static void calculate_needs_all_insns (int);
379 static int find_reg (struct insn_chain
*, int);
380 static void find_reload_regs (struct insn_chain
*);
381 static void select_reload_regs (void);
382 static void delete_caller_save_insns (void);
384 static void spill_failure (rtx
, enum reg_class
);
385 static void count_spilled_pseudo (int, int, int);
386 static void delete_dead_insn (rtx
);
387 static void alter_reg (int, int);
388 static void set_label_offsets (rtx
, rtx
, int);
389 static void check_eliminable_occurrences (rtx
);
390 static void elimination_effects (rtx
, enum machine_mode
);
391 static int eliminate_regs_in_insn (rtx
, int);
392 static void update_eliminable_offsets (void);
393 static void mark_not_eliminable (rtx
, rtx
, void *);
394 static void set_initial_elim_offsets (void);
395 static bool verify_initial_elim_offsets (void);
396 static void set_initial_label_offsets (void);
397 static void set_offsets_for_label (rtx
);
398 static void init_elim_table (void);
399 static void update_eliminables (HARD_REG_SET
*);
400 static void spill_hard_reg (unsigned int, int);
401 static int finish_spills (int);
402 static void scan_paradoxical_subregs (rtx
);
403 static void count_pseudo (int);
404 static void order_regs_for_reload (struct insn_chain
*);
405 static void reload_as_needed (int);
406 static void forget_old_reloads_1 (rtx
, rtx
, void *);
407 static int reload_reg_class_lower (const void *, const void *);
408 static void mark_reload_reg_in_use (unsigned int, int, enum reload_type
,
410 static void clear_reload_reg_in_use (unsigned int, int, enum reload_type
,
412 static int reload_reg_free_p (unsigned int, int, enum reload_type
);
413 static int reload_reg_free_for_value_p (int, int, int, enum reload_type
,
415 static int free_for_value_p (int, enum machine_mode
, int, enum reload_type
,
417 static int reload_reg_reaches_end_p (unsigned int, int, enum reload_type
);
418 static int allocate_reload_reg (struct insn_chain
*, int, int);
419 static int conflicts_with_override (rtx
);
420 static void failed_reload (rtx
, int);
421 static int set_reload_reg (int, int);
422 static void choose_reload_regs_init (struct insn_chain
*, rtx
*);
423 static void choose_reload_regs (struct insn_chain
*);
424 static void merge_assigned_reloads (rtx
);
425 static void emit_input_reload_insns (struct insn_chain
*, struct reload
*,
427 static void emit_output_reload_insns (struct insn_chain
*, struct reload
*,
429 static void do_input_reload (struct insn_chain
*, struct reload
*, int);
430 static void do_output_reload (struct insn_chain
*, struct reload
*, int);
431 static bool inherit_piecemeal_p (int, int);
432 static void emit_reload_insns (struct insn_chain
*);
433 static void delete_output_reload (rtx
, int, int);
434 static void delete_address_reloads (rtx
, rtx
);
435 static void delete_address_reloads_1 (rtx
, rtx
, rtx
);
436 static rtx
inc_for_reload (rtx
, rtx
, rtx
, int);
438 static void add_auto_inc_notes (rtx
, rtx
);
440 static void copy_eh_notes (rtx
, rtx
);
441 static int reloads_conflict (int, int);
442 static rtx
gen_reload (rtx
, rtx
, int, enum reload_type
);
443 static rtx
emit_insn_if_valid_for_reload (rtx
);
445 /* Initialize the reload pass once per compilation. */
452 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
453 Set spill_indirect_levels to the number of levels such addressing is
454 permitted, zero if it is not permitted at all. */
457 = gen_rtx_MEM (Pmode
,
460 LAST_VIRTUAL_REGISTER
+ 1),
462 spill_indirect_levels
= 0;
464 while (memory_address_p (QImode
, tem
))
466 spill_indirect_levels
++;
467 tem
= gen_rtx_MEM (Pmode
, tem
);
470 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
472 tem
= gen_rtx_MEM (Pmode
, gen_rtx_SYMBOL_REF (Pmode
, "foo"));
473 indirect_symref_ok
= memory_address_p (QImode
, tem
);
475 /* See if reg+reg is a valid (and offsettable) address. */
477 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
479 tem
= gen_rtx_PLUS (Pmode
,
480 gen_rtx_REG (Pmode
, HARD_FRAME_POINTER_REGNUM
),
481 gen_rtx_REG (Pmode
, i
));
483 /* This way, we make sure that reg+reg is an offsettable address. */
484 tem
= plus_constant (tem
, 4);
486 if (memory_address_p (QImode
, tem
))
488 double_reg_address_ok
= 1;
493 /* Initialize obstack for our rtl allocation. */
494 gcc_obstack_init (&reload_obstack
);
495 reload_startobj
= obstack_alloc (&reload_obstack
, 0);
497 INIT_REG_SET (&spilled_pseudos
);
498 INIT_REG_SET (&pseudos_counted
);
499 VARRAY_RTX_INIT (reg_equiv_memory_loc_varray
, 0, "reg_equiv_memory_loc");
502 /* List of insn chains that are currently unused. */
503 static struct insn_chain
*unused_insn_chains
= 0;
505 /* Allocate an empty insn_chain structure. */
507 new_insn_chain (void)
509 struct insn_chain
*c
;
511 if (unused_insn_chains
== 0)
513 c
= obstack_alloc (&reload_obstack
, sizeof (struct insn_chain
));
514 INIT_REG_SET (&c
->live_throughout
);
515 INIT_REG_SET (&c
->dead_or_set
);
519 c
= unused_insn_chains
;
520 unused_insn_chains
= c
->next
;
522 c
->is_caller_save_insn
= 0;
523 c
->need_operand_change
= 0;
529 /* Small utility function to set all regs in hard reg set TO which are
530 allocated to pseudos in regset FROM. */
533 compute_use_by_pseudos (HARD_REG_SET
*to
, regset from
)
536 reg_set_iterator rsi
;
538 EXECUTE_IF_SET_IN_REG_SET (from
, FIRST_PSEUDO_REGISTER
, regno
, rsi
)
540 int r
= reg_renumber
[regno
];
545 /* reload_combine uses the information from
546 BASIC_BLOCK->global_live_at_start, which might still
547 contain registers that have not actually been allocated
548 since they have an equivalence. */
549 gcc_assert (reload_completed
);
553 nregs
= hard_regno_nregs
[r
][PSEUDO_REGNO_MODE (regno
)];
555 SET_HARD_REG_BIT (*to
, r
+ nregs
);
560 /* Replace all pseudos found in LOC with their corresponding
564 replace_pseudos_in (rtx
*loc
, enum machine_mode mem_mode
, rtx usage
)
577 unsigned int regno
= REGNO (x
);
579 if (regno
< FIRST_PSEUDO_REGISTER
)
582 x
= eliminate_regs (x
, mem_mode
, usage
);
586 replace_pseudos_in (loc
, mem_mode
, usage
);
590 if (reg_equiv_constant
[regno
])
591 *loc
= reg_equiv_constant
[regno
];
592 else if (reg_equiv_mem
[regno
])
593 *loc
= reg_equiv_mem
[regno
];
594 else if (reg_equiv_address
[regno
])
595 *loc
= gen_rtx_MEM (GET_MODE (x
), reg_equiv_address
[regno
]);
598 gcc_assert (!REG_P (regno_reg_rtx
[regno
])
599 || REGNO (regno_reg_rtx
[regno
]) != regno
);
600 *loc
= regno_reg_rtx
[regno
];
605 else if (code
== MEM
)
607 replace_pseudos_in (& XEXP (x
, 0), GET_MODE (x
), usage
);
611 /* Process each of our operands recursively. */
612 fmt
= GET_RTX_FORMAT (code
);
613 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++, fmt
++)
615 replace_pseudos_in (&XEXP (x
, i
), mem_mode
, usage
);
616 else if (*fmt
== 'E')
617 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
618 replace_pseudos_in (& XVECEXP (x
, i
, j
), mem_mode
, usage
);
622 /* Global variables used by reload and its subroutines. */
624 /* Set during calculate_needs if an insn needs register elimination. */
625 static int something_needs_elimination
;
626 /* Set during calculate_needs if an insn needs an operand changed. */
627 static int something_needs_operands_changed
;
629 /* Nonzero means we couldn't get enough spill regs. */
632 /* Main entry point for the reload pass.
634 FIRST is the first insn of the function being compiled.
636 GLOBAL nonzero means we were called from global_alloc
637 and should attempt to reallocate any pseudoregs that we
638 displace from hard regs we will use for reloads.
639 If GLOBAL is zero, we do not have enough information to do that,
640 so any pseudo reg that is spilled must go to the stack.
642 Return value is nonzero if reload failed
643 and we must not do any more for this function. */
646 reload (rtx first
, int global
)
650 struct elim_table
*ep
;
653 /* Make sure even insns with volatile mem refs are recognizable. */
658 reload_firstobj
= obstack_alloc (&reload_obstack
, 0);
660 /* Make sure that the last insn in the chain
661 is not something that needs reloading. */
662 emit_note (NOTE_INSN_DELETED
);
664 /* Enable find_equiv_reg to distinguish insns made by reload. */
665 reload_first_uid
= get_max_uid ();
667 #ifdef SECONDARY_MEMORY_NEEDED
668 /* Initialize the secondary memory table. */
669 clear_secondary_mem ();
672 /* We don't have a stack slot for any spill reg yet. */
673 memset (spill_stack_slot
, 0, sizeof spill_stack_slot
);
674 memset (spill_stack_slot_width
, 0, sizeof spill_stack_slot_width
);
676 /* Initialize the save area information for caller-save, in case some
680 /* Compute which hard registers are now in use
681 as homes for pseudo registers.
682 This is done here rather than (eg) in global_alloc
683 because this point is reached even if not optimizing. */
684 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
687 /* A function that receives a nonlocal goto must save all call-saved
689 if (current_function_has_nonlocal_label
)
690 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
691 if (! call_used_regs
[i
] && ! fixed_regs
[i
] && ! LOCAL_REGNO (i
))
692 regs_ever_live
[i
] = 1;
694 /* Find all the pseudo registers that didn't get hard regs
695 but do have known equivalent constants or memory slots.
696 These include parameters (known equivalent to parameter slots)
697 and cse'd or loop-moved constant memory addresses.
699 Record constant equivalents in reg_equiv_constant
700 so they will be substituted by find_reloads.
701 Record memory equivalents in reg_mem_equiv so they can
702 be substituted eventually by altering the REG-rtx's. */
704 reg_equiv_constant
= XCNEWVEC (rtx
, max_regno
);
705 reg_equiv_invariant
= XCNEWVEC (rtx
, max_regno
);
706 reg_equiv_mem
= XCNEWVEC (rtx
, max_regno
);
707 reg_equiv_address
= XCNEWVEC (rtx
, max_regno
);
708 reg_max_ref_width
= XCNEWVEC (unsigned int, max_regno
);
709 reg_old_renumber
= XCNEWVEC (short, max_regno
);
710 memcpy (reg_old_renumber
, reg_renumber
, max_regno
* sizeof (short));
711 pseudo_forbidden_regs
= XNEWVEC (HARD_REG_SET
, max_regno
);
712 pseudo_previous_regs
= XCNEWVEC (HARD_REG_SET
, max_regno
);
714 CLEAR_HARD_REG_SET (bad_spill_regs_global
);
716 /* Look for REG_EQUIV notes; record what each pseudo is equivalent
717 to. Also find all paradoxical subregs and find largest such for
720 num_eliminable_invariants
= 0;
721 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
723 rtx set
= single_set (insn
);
725 /* We may introduce USEs that we want to remove at the end, so
726 we'll mark them with QImode. Make sure there are no
727 previously-marked insns left by say regmove. */
728 if (INSN_P (insn
) && GET_CODE (PATTERN (insn
)) == USE
729 && GET_MODE (insn
) != VOIDmode
)
730 PUT_MODE (insn
, VOIDmode
);
733 scan_paradoxical_subregs (PATTERN (insn
));
735 if (set
!= 0 && REG_P (SET_DEST (set
)))
737 rtx note
= find_reg_note (insn
, REG_EQUIV
, NULL_RTX
);
743 i
= REGNO (SET_DEST (set
));
746 if (i
<= LAST_VIRTUAL_REGISTER
)
749 if (! function_invariant_p (x
)
751 /* A function invariant is often CONSTANT_P but may
752 include a register. We promise to only pass
753 CONSTANT_P objects to LEGITIMATE_PIC_OPERAND_P. */
755 && LEGITIMATE_PIC_OPERAND_P (x
)))
757 /* It can happen that a REG_EQUIV note contains a MEM
758 that is not a legitimate memory operand. As later
759 stages of reload assume that all addresses found
760 in the reg_equiv_* arrays were originally legitimate,
761 we ignore such REG_EQUIV notes. */
762 if (memory_operand (x
, VOIDmode
))
764 /* Always unshare the equivalence, so we can
765 substitute into this insn without touching the
767 reg_equiv_memory_loc
[i
] = copy_rtx (x
);
769 else if (function_invariant_p (x
))
771 if (GET_CODE (x
) == PLUS
)
773 /* This is PLUS of frame pointer and a constant,
774 and might be shared. Unshare it. */
775 reg_equiv_invariant
[i
] = copy_rtx (x
);
776 num_eliminable_invariants
++;
778 else if (x
== frame_pointer_rtx
|| x
== arg_pointer_rtx
)
780 reg_equiv_invariant
[i
] = x
;
781 num_eliminable_invariants
++;
783 else if (LEGITIMATE_CONSTANT_P (x
))
784 reg_equiv_constant
[i
] = x
;
787 reg_equiv_memory_loc
[i
]
788 = force_const_mem (GET_MODE (SET_DEST (set
)), x
);
789 if (! reg_equiv_memory_loc
[i
])
790 reg_equiv_init
[i
] = NULL_RTX
;
795 reg_equiv_init
[i
] = NULL_RTX
;
800 reg_equiv_init
[i
] = NULL_RTX
;
805 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
806 if (reg_equiv_init
[i
])
808 fprintf (dump_file
, "init_insns for %u: ", i
);
809 print_inline_rtx (dump_file
, reg_equiv_init
[i
], 20);
810 fprintf (dump_file
, "\n");
815 first_label_num
= get_first_label_num ();
816 num_labels
= max_label_num () - first_label_num
;
818 /* Allocate the tables used to store offset information at labels. */
819 /* We used to use alloca here, but the size of what it would try to
820 allocate would occasionally cause it to exceed the stack limit and
821 cause a core dump. */
822 offsets_known_at
= XNEWVEC (char, num_labels
);
823 offsets_at
= (HOST_WIDE_INT (*)[NUM_ELIMINABLE_REGS
]) xmalloc (num_labels
* NUM_ELIMINABLE_REGS
* sizeof (HOST_WIDE_INT
));
825 /* Alter each pseudo-reg rtx to contain its hard reg number.
826 Assign stack slots to the pseudos that lack hard regs or equivalents.
827 Do not touch virtual registers. */
829 for (i
= LAST_VIRTUAL_REGISTER
+ 1; i
< max_regno
; i
++)
832 /* If we have some registers we think can be eliminated, scan all insns to
833 see if there is an insn that sets one of these registers to something
834 other than itself plus a constant. If so, the register cannot be
835 eliminated. Doing this scan here eliminates an extra pass through the
836 main reload loop in the most common case where register elimination
838 for (insn
= first
; insn
&& num_eliminable
; insn
= NEXT_INSN (insn
))
840 note_stores (PATTERN (insn
), mark_not_eliminable
, NULL
);
842 maybe_fix_stack_asms ();
844 insns_need_reload
= 0;
845 something_needs_elimination
= 0;
847 /* Initialize to -1, which means take the first spill register. */
850 /* Spill any hard regs that we know we can't eliminate. */
851 CLEAR_HARD_REG_SET (used_spill_regs
);
852 /* There can be multiple ways to eliminate a register;
853 they should be listed adjacently.
854 Elimination for any register fails only if all possible ways fail. */
855 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; )
858 int can_eliminate
= 0;
861 can_eliminate
|= ep
->can_eliminate
;
864 while (ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
] && ep
->from
== from
);
866 spill_hard_reg (from
, 1);
869 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
870 if (frame_pointer_needed
)
871 spill_hard_reg (HARD_FRAME_POINTER_REGNUM
, 1);
873 finish_spills (global
);
875 /* From now on, we may need to generate moves differently. We may also
876 allow modifications of insns which cause them to not be recognized.
877 Any such modifications will be cleaned up during reload itself. */
878 reload_in_progress
= 1;
880 /* This loop scans the entire function each go-round
881 and repeats until one repetition spills no additional hard regs. */
884 int something_changed
;
887 HOST_WIDE_INT starting_frame_size
;
889 /* Round size of stack frame to stack_alignment_needed. This must be done
890 here because the stack size may be a part of the offset computation
891 for register elimination, and there might have been new stack slots
892 created in the last iteration of this loop. */
893 if (cfun
->stack_alignment_needed
)
894 assign_stack_local (BLKmode
, 0, cfun
->stack_alignment_needed
);
896 starting_frame_size
= get_frame_size ();
898 set_initial_elim_offsets ();
899 set_initial_label_offsets ();
901 /* For each pseudo register that has an equivalent location defined,
902 try to eliminate any eliminable registers (such as the frame pointer)
903 assuming initial offsets for the replacement register, which
906 If the resulting location is directly addressable, substitute
907 the MEM we just got directly for the old REG.
909 If it is not addressable but is a constant or the sum of a hard reg
910 and constant, it is probably not addressable because the constant is
911 out of range, in that case record the address; we will generate
912 hairy code to compute the address in a register each time it is
913 needed. Similarly if it is a hard register, but one that is not
914 valid as an address register.
916 If the location is not addressable, but does not have one of the
917 above forms, assign a stack slot. We have to do this to avoid the
918 potential of producing lots of reloads if, e.g., a location involves
919 a pseudo that didn't get a hard register and has an equivalent memory
920 location that also involves a pseudo that didn't get a hard register.
922 Perhaps at some point we will improve reload_when_needed handling
923 so this problem goes away. But that's very hairy. */
925 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
926 if (reg_renumber
[i
] < 0 && reg_equiv_memory_loc
[i
])
928 rtx x
= eliminate_regs (reg_equiv_memory_loc
[i
], 0, NULL_RTX
);
930 if (strict_memory_address_p (GET_MODE (regno_reg_rtx
[i
]),
932 reg_equiv_mem
[i
] = x
, reg_equiv_address
[i
] = 0;
933 else if (CONSTANT_P (XEXP (x
, 0))
934 || (REG_P (XEXP (x
, 0))
935 && REGNO (XEXP (x
, 0)) < FIRST_PSEUDO_REGISTER
)
936 || (GET_CODE (XEXP (x
, 0)) == PLUS
937 && REG_P (XEXP (XEXP (x
, 0), 0))
938 && (REGNO (XEXP (XEXP (x
, 0), 0))
939 < FIRST_PSEUDO_REGISTER
)
940 && CONSTANT_P (XEXP (XEXP (x
, 0), 1))))
941 reg_equiv_address
[i
] = XEXP (x
, 0), reg_equiv_mem
[i
] = 0;
944 /* Make a new stack slot. Then indicate that something
945 changed so we go back and recompute offsets for
946 eliminable registers because the allocation of memory
947 below might change some offset. reg_equiv_{mem,address}
948 will be set up for this pseudo on the next pass around
950 reg_equiv_memory_loc
[i
] = 0;
951 reg_equiv_init
[i
] = 0;
956 if (caller_save_needed
)
959 /* If we allocated another stack slot, redo elimination bookkeeping. */
960 if (starting_frame_size
!= get_frame_size ())
963 if (caller_save_needed
)
965 save_call_clobbered_regs ();
966 /* That might have allocated new insn_chain structures. */
967 reload_firstobj
= obstack_alloc (&reload_obstack
, 0);
970 calculate_needs_all_insns (global
);
972 CLEAR_REG_SET (&spilled_pseudos
);
975 something_changed
= 0;
977 /* If we allocated any new memory locations, make another pass
978 since it might have changed elimination offsets. */
979 if (starting_frame_size
!= get_frame_size ())
980 something_changed
= 1;
982 /* Even if the frame size remained the same, we might still have
983 changed elimination offsets, e.g. if find_reloads called
984 force_const_mem requiring the back end to allocate a constant
985 pool base register that needs to be saved on the stack. */
986 else if (!verify_initial_elim_offsets ())
987 something_changed
= 1;
990 HARD_REG_SET to_spill
;
991 CLEAR_HARD_REG_SET (to_spill
);
992 update_eliminables (&to_spill
);
993 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
994 if (TEST_HARD_REG_BIT (to_spill
, i
))
996 spill_hard_reg (i
, 1);
999 /* Regardless of the state of spills, if we previously had
1000 a register that we thought we could eliminate, but now can
1001 not eliminate, we must run another pass.
1003 Consider pseudos which have an entry in reg_equiv_* which
1004 reference an eliminable register. We must make another pass
1005 to update reg_equiv_* so that we do not substitute in the
1006 old value from when we thought the elimination could be
1008 something_changed
= 1;
1012 select_reload_regs ();
1016 if (insns_need_reload
!= 0 || did_spill
)
1017 something_changed
|= finish_spills (global
);
1019 if (! something_changed
)
1022 if (caller_save_needed
)
1023 delete_caller_save_insns ();
1025 obstack_free (&reload_obstack
, reload_firstobj
);
1028 /* If global-alloc was run, notify it of any register eliminations we have
1031 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
1032 if (ep
->can_eliminate
)
1033 mark_elimination (ep
->from
, ep
->to
);
1035 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
1036 If that insn didn't set the register (i.e., it copied the register to
1037 memory), just delete that insn instead of the equivalencing insn plus
1038 anything now dead. If we call delete_dead_insn on that insn, we may
1039 delete the insn that actually sets the register if the register dies
1040 there and that is incorrect. */
1042 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
1044 if (reg_renumber
[i
] < 0 && reg_equiv_init
[i
] != 0)
1047 for (list
= reg_equiv_init
[i
]; list
; list
= XEXP (list
, 1))
1049 rtx equiv_insn
= XEXP (list
, 0);
1051 /* If we already deleted the insn or if it may trap, we can't
1052 delete it. The latter case shouldn't happen, but can
1053 if an insn has a variable address, gets a REG_EH_REGION
1054 note added to it, and then gets converted into a load
1055 from a constant address. */
1056 if (NOTE_P (equiv_insn
)
1057 || can_throw_internal (equiv_insn
))
1059 else if (reg_set_p (regno_reg_rtx
[i
], PATTERN (equiv_insn
)))
1060 delete_dead_insn (equiv_insn
);
1062 SET_INSN_DELETED (equiv_insn
);
1067 /* Use the reload registers where necessary
1068 by generating move instructions to move the must-be-register
1069 values into or out of the reload registers. */
1071 if (insns_need_reload
!= 0 || something_needs_elimination
1072 || something_needs_operands_changed
)
1074 HOST_WIDE_INT old_frame_size
= get_frame_size ();
1076 reload_as_needed (global
);
1078 gcc_assert (old_frame_size
== get_frame_size ());
1080 gcc_assert (verify_initial_elim_offsets ());
1083 /* If we were able to eliminate the frame pointer, show that it is no
1084 longer live at the start of any basic block. If it ls live by
1085 virtue of being in a pseudo, that pseudo will be marked live
1086 and hence the frame pointer will be known to be live via that
1089 if (! frame_pointer_needed
)
1091 CLEAR_REGNO_REG_SET (bb
->il
.rtl
->global_live_at_start
,
1092 HARD_FRAME_POINTER_REGNUM
);
1094 /* Come here (with failure set nonzero) if we can't get enough spill
1098 CLEAR_REG_SET (&spilled_pseudos
);
1099 reload_in_progress
= 0;
1101 /* Now eliminate all pseudo regs by modifying them into
1102 their equivalent memory references.
1103 The REG-rtx's for the pseudos are modified in place,
1104 so all insns that used to refer to them now refer to memory.
1106 For a reg that has a reg_equiv_address, all those insns
1107 were changed by reloading so that no insns refer to it any longer;
1108 but the DECL_RTL of a variable decl may refer to it,
1109 and if so this causes the debugging info to mention the variable. */
1111 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
1115 if (reg_equiv_mem
[i
])
1116 addr
= XEXP (reg_equiv_mem
[i
], 0);
1118 if (reg_equiv_address
[i
])
1119 addr
= reg_equiv_address
[i
];
1123 if (reg_renumber
[i
] < 0)
1125 rtx reg
= regno_reg_rtx
[i
];
1127 REG_USERVAR_P (reg
) = 0;
1128 PUT_CODE (reg
, MEM
);
1129 XEXP (reg
, 0) = addr
;
1130 if (reg_equiv_memory_loc
[i
])
1131 MEM_COPY_ATTRIBUTES (reg
, reg_equiv_memory_loc
[i
]);
1134 MEM_IN_STRUCT_P (reg
) = MEM_SCALAR_P (reg
) = 0;
1135 MEM_ATTRS (reg
) = 0;
1137 MEM_NOTRAP_P (reg
) = 1;
1139 else if (reg_equiv_mem
[i
])
1140 XEXP (reg_equiv_mem
[i
], 0) = addr
;
1144 /* We must set reload_completed now since the cleanup_subreg_operands call
1145 below will re-recognize each insn and reload may have generated insns
1146 which are only valid during and after reload. */
1147 reload_completed
= 1;
1149 /* Make a pass over all the insns and delete all USEs which we inserted
1150 only to tag a REG_EQUAL note on them. Remove all REG_DEAD and REG_UNUSED
1151 notes. Delete all CLOBBER insns, except those that refer to the return
1152 value and the special mem:BLK CLOBBERs added to prevent the scheduler
1153 from misarranging variable-array code, and simplify (subreg (reg))
1154 operands. Also remove all REG_RETVAL and REG_LIBCALL notes since they
1155 are no longer useful or accurate. Strip and regenerate REG_INC notes
1156 that may have been moved around. */
1158 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
1164 replace_pseudos_in (& CALL_INSN_FUNCTION_USAGE (insn
),
1165 VOIDmode
, CALL_INSN_FUNCTION_USAGE (insn
));
1167 if ((GET_CODE (PATTERN (insn
)) == USE
1168 /* We mark with QImode USEs introduced by reload itself. */
1169 && (GET_MODE (insn
) == QImode
1170 || find_reg_note (insn
, REG_EQUAL
, NULL_RTX
)))
1171 || (GET_CODE (PATTERN (insn
)) == CLOBBER
1172 && (!MEM_P (XEXP (PATTERN (insn
), 0))
1173 || GET_MODE (XEXP (PATTERN (insn
), 0)) != BLKmode
1174 || (GET_CODE (XEXP (XEXP (PATTERN (insn
), 0), 0)) != SCRATCH
1175 && XEXP (XEXP (PATTERN (insn
), 0), 0)
1176 != stack_pointer_rtx
))
1177 && (!REG_P (XEXP (PATTERN (insn
), 0))
1178 || ! REG_FUNCTION_VALUE_P (XEXP (PATTERN (insn
), 0)))))
1184 /* Some CLOBBERs may survive until here and still reference unassigned
1185 pseudos with const equivalent, which may in turn cause ICE in later
1186 passes if the reference remains in place. */
1187 if (GET_CODE (PATTERN (insn
)) == CLOBBER
)
1188 replace_pseudos_in (& XEXP (PATTERN (insn
), 0),
1189 VOIDmode
, PATTERN (insn
));
1191 /* Discard obvious no-ops, even without -O. This optimization
1192 is fast and doesn't interfere with debugging. */
1193 if (NONJUMP_INSN_P (insn
)
1194 && GET_CODE (PATTERN (insn
)) == SET
1195 && REG_P (SET_SRC (PATTERN (insn
)))
1196 && REG_P (SET_DEST (PATTERN (insn
)))
1197 && (REGNO (SET_SRC (PATTERN (insn
)))
1198 == REGNO (SET_DEST (PATTERN (insn
)))))
1204 pnote
= ®_NOTES (insn
);
1207 if (REG_NOTE_KIND (*pnote
) == REG_DEAD
1208 || REG_NOTE_KIND (*pnote
) == REG_UNUSED
1209 || REG_NOTE_KIND (*pnote
) == REG_INC
1210 || REG_NOTE_KIND (*pnote
) == REG_RETVAL
1211 || REG_NOTE_KIND (*pnote
) == REG_LIBCALL
)
1212 *pnote
= XEXP (*pnote
, 1);
1214 pnote
= &XEXP (*pnote
, 1);
1218 add_auto_inc_notes (insn
, PATTERN (insn
));
1221 /* And simplify (subreg (reg)) if it appears as an operand. */
1222 cleanup_subreg_operands (insn
);
1225 /* If we are doing stack checking, give a warning if this function's
1226 frame size is larger than we expect. */
1227 if (flag_stack_check
&& ! STACK_CHECK_BUILTIN
)
1229 HOST_WIDE_INT size
= get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE
;
1230 static int verbose_warned
= 0;
1232 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1233 if (regs_ever_live
[i
] && ! fixed_regs
[i
] && call_used_regs
[i
])
1234 size
+= UNITS_PER_WORD
;
1236 if (size
> STACK_CHECK_MAX_FRAME_SIZE
)
1238 warning (0, "frame size too large for reliable stack checking");
1239 if (! verbose_warned
)
1241 warning (0, "try reducing the number of local variables");
1247 /* Indicate that we no longer have known memory locations or constants. */
1248 if (reg_equiv_constant
)
1249 free (reg_equiv_constant
);
1250 if (reg_equiv_invariant
)
1251 free (reg_equiv_invariant
);
1252 reg_equiv_constant
= 0;
1253 reg_equiv_invariant
= 0;
1254 VARRAY_GROW (reg_equiv_memory_loc_varray
, 0);
1255 reg_equiv_memory_loc
= 0;
1257 if (offsets_known_at
)
1258 free (offsets_known_at
);
1262 free (reg_equiv_mem
);
1264 free (reg_equiv_address
);
1265 free (reg_max_ref_width
);
1266 free (reg_old_renumber
);
1267 free (pseudo_previous_regs
);
1268 free (pseudo_forbidden_regs
);
1270 CLEAR_HARD_REG_SET (used_spill_regs
);
1271 for (i
= 0; i
< n_spills
; i
++)
1272 SET_HARD_REG_BIT (used_spill_regs
, spill_regs
[i
]);
1274 /* Free all the insn_chain structures at once. */
1275 obstack_free (&reload_obstack
, reload_startobj
);
1276 unused_insn_chains
= 0;
1277 fixup_abnormal_edges ();
1279 /* Replacing pseudos with their memory equivalents might have
1280 created shared rtx. Subsequent passes would get confused
1281 by this, so unshare everything here. */
1282 unshare_all_rtl_again (first
);
1284 #ifdef STACK_BOUNDARY
1285 /* init_emit has set the alignment of the hard frame pointer
1286 to STACK_BOUNDARY. It is very likely no longer valid if
1287 the hard frame pointer was used for register allocation. */
1288 if (!frame_pointer_needed
)
1289 REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM
) = BITS_PER_UNIT
;
1295 /* Yet another special case. Unfortunately, reg-stack forces people to
1296 write incorrect clobbers in asm statements. These clobbers must not
1297 cause the register to appear in bad_spill_regs, otherwise we'll call
1298 fatal_insn later. We clear the corresponding regnos in the live
1299 register sets to avoid this.
1300 The whole thing is rather sick, I'm afraid. */
1303 maybe_fix_stack_asms (void)
1306 const char *constraints
[MAX_RECOG_OPERANDS
];
1307 enum machine_mode operand_mode
[MAX_RECOG_OPERANDS
];
1308 struct insn_chain
*chain
;
1310 for (chain
= reload_insn_chain
; chain
!= 0; chain
= chain
->next
)
1313 HARD_REG_SET clobbered
, allowed
;
1316 if (! INSN_P (chain
->insn
)
1317 || (noperands
= asm_noperands (PATTERN (chain
->insn
))) < 0)
1319 pat
= PATTERN (chain
->insn
);
1320 if (GET_CODE (pat
) != PARALLEL
)
1323 CLEAR_HARD_REG_SET (clobbered
);
1324 CLEAR_HARD_REG_SET (allowed
);
1326 /* First, make a mask of all stack regs that are clobbered. */
1327 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
1329 rtx t
= XVECEXP (pat
, 0, i
);
1330 if (GET_CODE (t
) == CLOBBER
&& STACK_REG_P (XEXP (t
, 0)))
1331 SET_HARD_REG_BIT (clobbered
, REGNO (XEXP (t
, 0)));
1334 /* Get the operand values and constraints out of the insn. */
1335 decode_asm_operands (pat
, recog_data
.operand
, recog_data
.operand_loc
,
1336 constraints
, operand_mode
);
1338 /* For every operand, see what registers are allowed. */
1339 for (i
= 0; i
< noperands
; i
++)
1341 const char *p
= constraints
[i
];
1342 /* For every alternative, we compute the class of registers allowed
1343 for reloading in CLS, and merge its contents into the reg set
1345 int cls
= (int) NO_REGS
;
1351 if (c
== '\0' || c
== ',' || c
== '#')
1353 /* End of one alternative - mark the regs in the current
1354 class, and reset the class. */
1355 IOR_HARD_REG_SET (allowed
, reg_class_contents
[cls
]);
1361 } while (c
!= '\0' && c
!= ',');
1369 case '=': case '+': case '*': case '%': case '?': case '!':
1370 case '0': case '1': case '2': case '3': case '4': case 'm':
1371 case '<': case '>': case 'V': case 'o': case '&': case 'E':
1372 case 'F': case 's': case 'i': case 'n': case 'X': case 'I':
1373 case 'J': case 'K': case 'L': case 'M': case 'N': case 'O':
1378 cls
= (int) reg_class_subunion
[cls
]
1379 [(int) base_reg_class (VOIDmode
, ADDRESS
, SCRATCH
)];
1384 cls
= (int) reg_class_subunion
[cls
][(int) GENERAL_REGS
];
1388 if (EXTRA_ADDRESS_CONSTRAINT (c
, p
))
1389 cls
= (int) reg_class_subunion
[cls
]
1390 [(int) base_reg_class (VOIDmode
, ADDRESS
, SCRATCH
)];
1392 cls
= (int) reg_class_subunion
[cls
]
1393 [(int) REG_CLASS_FROM_CONSTRAINT (c
, p
)];
1395 p
+= CONSTRAINT_LEN (c
, p
);
1398 /* Those of the registers which are clobbered, but allowed by the
1399 constraints, must be usable as reload registers. So clear them
1400 out of the life information. */
1401 AND_HARD_REG_SET (allowed
, clobbered
);
1402 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1403 if (TEST_HARD_REG_BIT (allowed
, i
))
1405 CLEAR_REGNO_REG_SET (&chain
->live_throughout
, i
);
1406 CLEAR_REGNO_REG_SET (&chain
->dead_or_set
, i
);
1413 /* Copy the global variables n_reloads and rld into the corresponding elts
1416 copy_reloads (struct insn_chain
*chain
)
1418 chain
->n_reloads
= n_reloads
;
1419 chain
->rld
= obstack_alloc (&reload_obstack
,
1420 n_reloads
* sizeof (struct reload
));
1421 memcpy (chain
->rld
, rld
, n_reloads
* sizeof (struct reload
));
1422 reload_insn_firstobj
= obstack_alloc (&reload_obstack
, 0);
1425 /* Walk the chain of insns, and determine for each whether it needs reloads
1426 and/or eliminations. Build the corresponding insns_need_reload list, and
1427 set something_needs_elimination as appropriate. */
1429 calculate_needs_all_insns (int global
)
1431 struct insn_chain
**pprev_reload
= &insns_need_reload
;
1432 struct insn_chain
*chain
, *next
= 0;
1434 something_needs_elimination
= 0;
1436 reload_insn_firstobj
= obstack_alloc (&reload_obstack
, 0);
1437 for (chain
= reload_insn_chain
; chain
!= 0; chain
= next
)
1439 rtx insn
= chain
->insn
;
1443 /* Clear out the shortcuts. */
1444 chain
->n_reloads
= 0;
1445 chain
->need_elim
= 0;
1446 chain
->need_reload
= 0;
1447 chain
->need_operand_change
= 0;
1449 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1450 include REG_LABEL), we need to see what effects this has on the
1451 known offsets at labels. */
1453 if (LABEL_P (insn
) || JUMP_P (insn
)
1454 || (INSN_P (insn
) && REG_NOTES (insn
) != 0))
1455 set_label_offsets (insn
, insn
, 0);
1459 rtx old_body
= PATTERN (insn
);
1460 int old_code
= INSN_CODE (insn
);
1461 rtx old_notes
= REG_NOTES (insn
);
1462 int did_elimination
= 0;
1463 int operands_changed
= 0;
1464 rtx set
= single_set (insn
);
1466 /* Skip insns that only set an equivalence. */
1467 if (set
&& REG_P (SET_DEST (set
))
1468 && reg_renumber
[REGNO (SET_DEST (set
))] < 0
1469 && (reg_equiv_constant
[REGNO (SET_DEST (set
))]
1470 || (reg_equiv_invariant
[REGNO (SET_DEST (set
))]))
1471 && reg_equiv_init
[REGNO (SET_DEST (set
))])
1474 /* If needed, eliminate any eliminable registers. */
1475 if (num_eliminable
|| num_eliminable_invariants
)
1476 did_elimination
= eliminate_regs_in_insn (insn
, 0);
1478 /* Analyze the instruction. */
1479 operands_changed
= find_reloads (insn
, 0, spill_indirect_levels
,
1480 global
, spill_reg_order
);
1482 /* If a no-op set needs more than one reload, this is likely
1483 to be something that needs input address reloads. We
1484 can't get rid of this cleanly later, and it is of no use
1485 anyway, so discard it now.
1486 We only do this when expensive_optimizations is enabled,
1487 since this complements reload inheritance / output
1488 reload deletion, and it can make debugging harder. */
1489 if (flag_expensive_optimizations
&& n_reloads
> 1)
1491 rtx set
= single_set (insn
);
1493 && SET_SRC (set
) == SET_DEST (set
)
1494 && REG_P (SET_SRC (set
))
1495 && REGNO (SET_SRC (set
)) >= FIRST_PSEUDO_REGISTER
)
1498 /* Delete it from the reload chain. */
1500 chain
->prev
->next
= next
;
1502 reload_insn_chain
= next
;
1504 next
->prev
= chain
->prev
;
1505 chain
->next
= unused_insn_chains
;
1506 unused_insn_chains
= chain
;
1511 update_eliminable_offsets ();
1513 /* Remember for later shortcuts which insns had any reloads or
1514 register eliminations. */
1515 chain
->need_elim
= did_elimination
;
1516 chain
->need_reload
= n_reloads
> 0;
1517 chain
->need_operand_change
= operands_changed
;
1519 /* Discard any register replacements done. */
1520 if (did_elimination
)
1522 obstack_free (&reload_obstack
, reload_insn_firstobj
);
1523 PATTERN (insn
) = old_body
;
1524 INSN_CODE (insn
) = old_code
;
1525 REG_NOTES (insn
) = old_notes
;
1526 something_needs_elimination
= 1;
1529 something_needs_operands_changed
|= operands_changed
;
1533 copy_reloads (chain
);
1534 *pprev_reload
= chain
;
1535 pprev_reload
= &chain
->next_need_reload
;
1542 /* Comparison function for qsort to decide which of two reloads
1543 should be handled first. *P1 and *P2 are the reload numbers. */
1546 reload_reg_class_lower (const void *r1p
, const void *r2p
)
1548 int r1
= *(const short *) r1p
, r2
= *(const short *) r2p
;
1551 /* Consider required reloads before optional ones. */
1552 t
= rld
[r1
].optional
- rld
[r2
].optional
;
1556 /* Count all solitary classes before non-solitary ones. */
1557 t
= ((reg_class_size
[(int) rld
[r2
].class] == 1)
1558 - (reg_class_size
[(int) rld
[r1
].class] == 1));
1562 /* Aside from solitaires, consider all multi-reg groups first. */
1563 t
= rld
[r2
].nregs
- rld
[r1
].nregs
;
1567 /* Consider reloads in order of increasing reg-class number. */
1568 t
= (int) rld
[r1
].class - (int) rld
[r2
].class;
1572 /* If reloads are equally urgent, sort by reload number,
1573 so that the results of qsort leave nothing to chance. */
1577 /* The cost of spilling each hard reg. */
1578 static int spill_cost
[FIRST_PSEUDO_REGISTER
];
1580 /* When spilling multiple hard registers, we use SPILL_COST for the first
1581 spilled hard reg and SPILL_ADD_COST for subsequent regs. SPILL_ADD_COST
1582 only the first hard reg for a multi-reg pseudo. */
1583 static int spill_add_cost
[FIRST_PSEUDO_REGISTER
];
1585 /* Update the spill cost arrays, considering that pseudo REG is live. */
1588 count_pseudo (int reg
)
1590 int freq
= REG_FREQ (reg
);
1591 int r
= reg_renumber
[reg
];
1594 if (REGNO_REG_SET_P (&pseudos_counted
, reg
)
1595 || REGNO_REG_SET_P (&spilled_pseudos
, reg
))
1598 SET_REGNO_REG_SET (&pseudos_counted
, reg
);
1600 gcc_assert (r
>= 0);
1602 spill_add_cost
[r
] += freq
;
1604 nregs
= hard_regno_nregs
[r
][PSEUDO_REGNO_MODE (reg
)];
1606 spill_cost
[r
+ nregs
] += freq
;
1609 /* Calculate the SPILL_COST and SPILL_ADD_COST arrays and determine the
1610 contents of BAD_SPILL_REGS for the insn described by CHAIN. */
1613 order_regs_for_reload (struct insn_chain
*chain
)
1616 HARD_REG_SET used_by_pseudos
;
1617 HARD_REG_SET used_by_pseudos2
;
1618 reg_set_iterator rsi
;
1620 COPY_HARD_REG_SET (bad_spill_regs
, fixed_reg_set
);
1622 memset (spill_cost
, 0, sizeof spill_cost
);
1623 memset (spill_add_cost
, 0, sizeof spill_add_cost
);
1625 /* Count number of uses of each hard reg by pseudo regs allocated to it
1626 and then order them by decreasing use. First exclude hard registers
1627 that are live in or across this insn. */
1629 REG_SET_TO_HARD_REG_SET (used_by_pseudos
, &chain
->live_throughout
);
1630 REG_SET_TO_HARD_REG_SET (used_by_pseudos2
, &chain
->dead_or_set
);
1631 IOR_HARD_REG_SET (bad_spill_regs
, used_by_pseudos
);
1632 IOR_HARD_REG_SET (bad_spill_regs
, used_by_pseudos2
);
1634 /* Now find out which pseudos are allocated to it, and update
1636 CLEAR_REG_SET (&pseudos_counted
);
1638 EXECUTE_IF_SET_IN_REG_SET
1639 (&chain
->live_throughout
, FIRST_PSEUDO_REGISTER
, i
, rsi
)
1643 EXECUTE_IF_SET_IN_REG_SET
1644 (&chain
->dead_or_set
, FIRST_PSEUDO_REGISTER
, i
, rsi
)
1648 CLEAR_REG_SET (&pseudos_counted
);
1651 /* Vector of reload-numbers showing the order in which the reloads should
1653 static short reload_order
[MAX_RELOADS
];
1655 /* This is used to keep track of the spill regs used in one insn. */
1656 static HARD_REG_SET used_spill_regs_local
;
1658 /* We decided to spill hard register SPILLED, which has a size of
1659 SPILLED_NREGS. Determine how pseudo REG, which is live during the insn,
1660 is affected. We will add it to SPILLED_PSEUDOS if necessary, and we will
1661 update SPILL_COST/SPILL_ADD_COST. */
1664 count_spilled_pseudo (int spilled
, int spilled_nregs
, int reg
)
1666 int r
= reg_renumber
[reg
];
1667 int nregs
= hard_regno_nregs
[r
][PSEUDO_REGNO_MODE (reg
)];
1669 if (REGNO_REG_SET_P (&spilled_pseudos
, reg
)
1670 || spilled
+ spilled_nregs
<= r
|| r
+ nregs
<= spilled
)
1673 SET_REGNO_REG_SET (&spilled_pseudos
, reg
);
1675 spill_add_cost
[r
] -= REG_FREQ (reg
);
1677 spill_cost
[r
+ nregs
] -= REG_FREQ (reg
);
1680 /* Find reload register to use for reload number ORDER. */
1683 find_reg (struct insn_chain
*chain
, int order
)
1685 int rnum
= reload_order
[order
];
1686 struct reload
*rl
= rld
+ rnum
;
1687 int best_cost
= INT_MAX
;
1691 HARD_REG_SET not_usable
;
1692 HARD_REG_SET used_by_other_reload
;
1693 reg_set_iterator rsi
;
1695 COPY_HARD_REG_SET (not_usable
, bad_spill_regs
);
1696 IOR_HARD_REG_SET (not_usable
, bad_spill_regs_global
);
1697 IOR_COMPL_HARD_REG_SET (not_usable
, reg_class_contents
[rl
->class]);
1699 CLEAR_HARD_REG_SET (used_by_other_reload
);
1700 for (k
= 0; k
< order
; k
++)
1702 int other
= reload_order
[k
];
1704 if (rld
[other
].regno
>= 0 && reloads_conflict (other
, rnum
))
1705 for (j
= 0; j
< rld
[other
].nregs
; j
++)
1706 SET_HARD_REG_BIT (used_by_other_reload
, rld
[other
].regno
+ j
);
1709 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1711 unsigned int regno
= i
;
1713 if (! TEST_HARD_REG_BIT (not_usable
, regno
)
1714 && ! TEST_HARD_REG_BIT (used_by_other_reload
, regno
)
1715 && HARD_REGNO_MODE_OK (regno
, rl
->mode
))
1717 int this_cost
= spill_cost
[regno
];
1719 unsigned int this_nregs
= hard_regno_nregs
[regno
][rl
->mode
];
1721 for (j
= 1; j
< this_nregs
; j
++)
1723 this_cost
+= spill_add_cost
[regno
+ j
];
1724 if ((TEST_HARD_REG_BIT (not_usable
, regno
+ j
))
1725 || TEST_HARD_REG_BIT (used_by_other_reload
, regno
+ j
))
1730 if (rl
->in
&& REG_P (rl
->in
) && REGNO (rl
->in
) == regno
)
1732 if (rl
->out
&& REG_P (rl
->out
) && REGNO (rl
->out
) == regno
)
1734 if (this_cost
< best_cost
1735 /* Among registers with equal cost, prefer caller-saved ones, or
1736 use REG_ALLOC_ORDER if it is defined. */
1737 || (this_cost
== best_cost
1738 #ifdef REG_ALLOC_ORDER
1739 && (inv_reg_alloc_order
[regno
]
1740 < inv_reg_alloc_order
[best_reg
])
1742 && call_used_regs
[regno
]
1743 && ! call_used_regs
[best_reg
]
1748 best_cost
= this_cost
;
1756 fprintf (dump_file
, "Using reg %d for reload %d\n", best_reg
, rnum
);
1758 rl
->nregs
= hard_regno_nregs
[best_reg
][rl
->mode
];
1759 rl
->regno
= best_reg
;
1761 EXECUTE_IF_SET_IN_REG_SET
1762 (&chain
->live_throughout
, FIRST_PSEUDO_REGISTER
, j
, rsi
)
1764 count_spilled_pseudo (best_reg
, rl
->nregs
, j
);
1767 EXECUTE_IF_SET_IN_REG_SET
1768 (&chain
->dead_or_set
, FIRST_PSEUDO_REGISTER
, j
, rsi
)
1770 count_spilled_pseudo (best_reg
, rl
->nregs
, j
);
1773 for (i
= 0; i
< rl
->nregs
; i
++)
1775 gcc_assert (spill_cost
[best_reg
+ i
] == 0);
1776 gcc_assert (spill_add_cost
[best_reg
+ i
] == 0);
1777 SET_HARD_REG_BIT (used_spill_regs_local
, best_reg
+ i
);
1782 /* Find more reload regs to satisfy the remaining need of an insn, which
1784 Do it by ascending class number, since otherwise a reg
1785 might be spilled for a big class and might fail to count
1786 for a smaller class even though it belongs to that class. */
1789 find_reload_regs (struct insn_chain
*chain
)
1793 /* In order to be certain of getting the registers we need,
1794 we must sort the reloads into order of increasing register class.
1795 Then our grabbing of reload registers will parallel the process
1796 that provided the reload registers. */
1797 for (i
= 0; i
< chain
->n_reloads
; i
++)
1799 /* Show whether this reload already has a hard reg. */
1800 if (chain
->rld
[i
].reg_rtx
)
1802 int regno
= REGNO (chain
->rld
[i
].reg_rtx
);
1803 chain
->rld
[i
].regno
= regno
;
1805 = hard_regno_nregs
[regno
][GET_MODE (chain
->rld
[i
].reg_rtx
)];
1808 chain
->rld
[i
].regno
= -1;
1809 reload_order
[i
] = i
;
1812 n_reloads
= chain
->n_reloads
;
1813 memcpy (rld
, chain
->rld
, n_reloads
* sizeof (struct reload
));
1815 CLEAR_HARD_REG_SET (used_spill_regs_local
);
1818 fprintf (dump_file
, "Spilling for insn %d.\n", INSN_UID (chain
->insn
));
1820 qsort (reload_order
, n_reloads
, sizeof (short), reload_reg_class_lower
);
1822 /* Compute the order of preference for hard registers to spill. */
1824 order_regs_for_reload (chain
);
1826 for (i
= 0; i
< n_reloads
; i
++)
1828 int r
= reload_order
[i
];
1830 /* Ignore reloads that got marked inoperative. */
1831 if ((rld
[r
].out
!= 0 || rld
[r
].in
!= 0 || rld
[r
].secondary_p
)
1832 && ! rld
[r
].optional
1833 && rld
[r
].regno
== -1)
1834 if (! find_reg (chain
, i
))
1837 fprintf(dump_file
, "reload failure for reload %d\n", r
);
1838 spill_failure (chain
->insn
, rld
[r
].class);
1844 COPY_HARD_REG_SET (chain
->used_spill_regs
, used_spill_regs_local
);
1845 IOR_HARD_REG_SET (used_spill_regs
, used_spill_regs_local
);
1847 memcpy (chain
->rld
, rld
, n_reloads
* sizeof (struct reload
));
1851 select_reload_regs (void)
1853 struct insn_chain
*chain
;
1855 /* Try to satisfy the needs for each insn. */
1856 for (chain
= insns_need_reload
; chain
!= 0;
1857 chain
= chain
->next_need_reload
)
1858 find_reload_regs (chain
);
1861 /* Delete all insns that were inserted by emit_caller_save_insns during
1864 delete_caller_save_insns (void)
1866 struct insn_chain
*c
= reload_insn_chain
;
1870 while (c
!= 0 && c
->is_caller_save_insn
)
1872 struct insn_chain
*next
= c
->next
;
1875 if (c
== reload_insn_chain
)
1876 reload_insn_chain
= next
;
1880 next
->prev
= c
->prev
;
1882 c
->prev
->next
= next
;
1883 c
->next
= unused_insn_chains
;
1884 unused_insn_chains
= c
;
1892 /* Handle the failure to find a register to spill.
1893 INSN should be one of the insns which needed this particular spill reg. */
1896 spill_failure (rtx insn
, enum reg_class
class)
1898 if (asm_noperands (PATTERN (insn
)) >= 0)
1899 error_for_asm (insn
, "can't find a register in class %qs while "
1900 "reloading %<asm%>",
1901 reg_class_names
[class]);
1904 error ("unable to find a register to spill in class %qs",
1905 reg_class_names
[class]);
1909 fprintf (dump_file
, "\nReloads for insn # %d\n", INSN_UID (insn
));
1910 debug_reload_to_stream (dump_file
);
1912 fatal_insn ("this is the insn:", insn
);
1916 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
1917 data that is dead in INSN. */
1920 delete_dead_insn (rtx insn
)
1922 rtx prev
= prev_real_insn (insn
);
1925 /* If the previous insn sets a register that dies in our insn, delete it
1927 if (prev
&& GET_CODE (PATTERN (prev
)) == SET
1928 && (prev_dest
= SET_DEST (PATTERN (prev
)), REG_P (prev_dest
))
1929 && reg_mentioned_p (prev_dest
, PATTERN (insn
))
1930 && find_regno_note (insn
, REG_DEAD
, REGNO (prev_dest
))
1931 && ! side_effects_p (SET_SRC (PATTERN (prev
))))
1932 delete_dead_insn (prev
);
1934 SET_INSN_DELETED (insn
);
1937 /* Modify the home of pseudo-reg I.
1938 The new home is present in reg_renumber[I].
1940 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
1941 or it may be -1, meaning there is none or it is not relevant.
1942 This is used so that all pseudos spilled from a given hard reg
1943 can share one stack slot. */
1946 alter_reg (int i
, int from_reg
)
1948 /* When outputting an inline function, this can happen
1949 for a reg that isn't actually used. */
1950 if (regno_reg_rtx
[i
] == 0)
1953 /* If the reg got changed to a MEM at rtl-generation time,
1955 if (!REG_P (regno_reg_rtx
[i
]))
1958 /* Modify the reg-rtx to contain the new hard reg
1959 number or else to contain its pseudo reg number. */
1960 REGNO (regno_reg_rtx
[i
])
1961 = reg_renumber
[i
] >= 0 ? reg_renumber
[i
] : i
;
1963 /* If we have a pseudo that is needed but has no hard reg or equivalent,
1964 allocate a stack slot for it. */
1966 if (reg_renumber
[i
] < 0
1967 && REG_N_REFS (i
) > 0
1968 && reg_equiv_constant
[i
] == 0
1969 && (reg_equiv_invariant
[i
] == 0 || reg_equiv_init
[i
] == 0)
1970 && reg_equiv_memory_loc
[i
] == 0)
1973 unsigned int inherent_size
= PSEUDO_REGNO_BYTES (i
);
1974 unsigned int total_size
= MAX (inherent_size
, reg_max_ref_width
[i
]);
1977 /* Each pseudo reg has an inherent size which comes from its own mode,
1978 and a total size which provides room for paradoxical subregs
1979 which refer to the pseudo reg in wider modes.
1981 We can use a slot already allocated if it provides both
1982 enough inherent space and enough total space.
1983 Otherwise, we allocate a new slot, making sure that it has no less
1984 inherent space, and no less total space, then the previous slot. */
1987 /* No known place to spill from => no slot to reuse. */
1988 x
= assign_stack_local (GET_MODE (regno_reg_rtx
[i
]), total_size
,
1989 inherent_size
== total_size
? 0 : -1);
1990 if (BYTES_BIG_ENDIAN
)
1991 /* Cancel the big-endian correction done in assign_stack_local.
1992 Get the address of the beginning of the slot.
1993 This is so we can do a big-endian correction unconditionally
1995 adjust
= inherent_size
- total_size
;
1997 /* Nothing can alias this slot except this pseudo. */
1998 set_mem_alias_set (x
, new_alias_set ());
2001 /* Reuse a stack slot if possible. */
2002 else if (spill_stack_slot
[from_reg
] != 0
2003 && spill_stack_slot_width
[from_reg
] >= total_size
2004 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot
[from_reg
]))
2006 x
= spill_stack_slot
[from_reg
];
2008 /* Allocate a bigger slot. */
2011 /* Compute maximum size needed, both for inherent size
2012 and for total size. */
2013 enum machine_mode mode
= GET_MODE (regno_reg_rtx
[i
]);
2016 if (spill_stack_slot
[from_reg
])
2018 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot
[from_reg
]))
2020 mode
= GET_MODE (spill_stack_slot
[from_reg
]);
2021 if (spill_stack_slot_width
[from_reg
] > total_size
)
2022 total_size
= spill_stack_slot_width
[from_reg
];
2025 /* Make a slot with that size. */
2026 x
= assign_stack_local (mode
, total_size
,
2027 inherent_size
== total_size
? 0 : -1);
2030 /* All pseudos mapped to this slot can alias each other. */
2031 if (spill_stack_slot
[from_reg
])
2032 set_mem_alias_set (x
, MEM_ALIAS_SET (spill_stack_slot
[from_reg
]));
2034 set_mem_alias_set (x
, new_alias_set ());
2036 if (BYTES_BIG_ENDIAN
)
2038 /* Cancel the big-endian correction done in assign_stack_local.
2039 Get the address of the beginning of the slot.
2040 This is so we can do a big-endian correction unconditionally
2042 adjust
= GET_MODE_SIZE (mode
) - total_size
;
2045 = adjust_address_nv (x
, mode_for_size (total_size
2051 spill_stack_slot
[from_reg
] = stack_slot
;
2052 spill_stack_slot_width
[from_reg
] = total_size
;
2055 /* On a big endian machine, the "address" of the slot
2056 is the address of the low part that fits its inherent mode. */
2057 if (BYTES_BIG_ENDIAN
&& inherent_size
< total_size
)
2058 adjust
+= (total_size
- inherent_size
);
2060 /* If we have any adjustment to make, or if the stack slot is the
2061 wrong mode, make a new stack slot. */
2062 x
= adjust_address_nv (x
, GET_MODE (regno_reg_rtx
[i
]), adjust
);
2064 /* If we have a decl for the original register, set it for the
2065 memory. If this is a shared MEM, make a copy. */
2066 if (REG_EXPR (regno_reg_rtx
[i
])
2067 && DECL_P (REG_EXPR (regno_reg_rtx
[i
])))
2069 rtx decl
= DECL_RTL_IF_SET (REG_EXPR (regno_reg_rtx
[i
]));
2071 /* We can do this only for the DECLs home pseudo, not for
2072 any copies of it, since otherwise when the stack slot
2073 is reused, nonoverlapping_memrefs_p might think they
2075 if (decl
&& REG_P (decl
) && REGNO (decl
) == (unsigned) i
)
2077 if (from_reg
!= -1 && spill_stack_slot
[from_reg
] == x
)
2080 set_mem_attrs_from_reg (x
, regno_reg_rtx
[i
]);
2084 /* Save the stack slot for later. */
2085 reg_equiv_memory_loc
[i
] = x
;
2089 /* Mark the slots in regs_ever_live for the hard regs
2090 used by pseudo-reg number REGNO. */
2093 mark_home_live (int regno
)
2097 i
= reg_renumber
[regno
];
2100 lim
= i
+ hard_regno_nregs
[i
][PSEUDO_REGNO_MODE (regno
)];
2102 regs_ever_live
[i
++] = 1;
2105 /* This function handles the tracking of elimination offsets around branches.
2107 X is a piece of RTL being scanned.
2109 INSN is the insn that it came from, if any.
2111 INITIAL_P is nonzero if we are to set the offset to be the initial
2112 offset and zero if we are setting the offset of the label to be the
2116 set_label_offsets (rtx x
, rtx insn
, int initial_p
)
2118 enum rtx_code code
= GET_CODE (x
);
2121 struct elim_table
*p
;
2126 if (LABEL_REF_NONLOCAL_P (x
))
2131 /* ... fall through ... */
2134 /* If we know nothing about this label, set the desired offsets. Note
2135 that this sets the offset at a label to be the offset before a label
2136 if we don't know anything about the label. This is not correct for
2137 the label after a BARRIER, but is the best guess we can make. If
2138 we guessed wrong, we will suppress an elimination that might have
2139 been possible had we been able to guess correctly. */
2141 if (! offsets_known_at
[CODE_LABEL_NUMBER (x
) - first_label_num
])
2143 for (i
= 0; i
< NUM_ELIMINABLE_REGS
; i
++)
2144 offsets_at
[CODE_LABEL_NUMBER (x
) - first_label_num
][i
]
2145 = (initial_p
? reg_eliminate
[i
].initial_offset
2146 : reg_eliminate
[i
].offset
);
2147 offsets_known_at
[CODE_LABEL_NUMBER (x
) - first_label_num
] = 1;
2150 /* Otherwise, if this is the definition of a label and it is
2151 preceded by a BARRIER, set our offsets to the known offset of
2155 && (tem
= prev_nonnote_insn (insn
)) != 0
2157 set_offsets_for_label (insn
);
2159 /* If neither of the above cases is true, compare each offset
2160 with those previously recorded and suppress any eliminations
2161 where the offsets disagree. */
2163 for (i
= 0; i
< NUM_ELIMINABLE_REGS
; i
++)
2164 if (offsets_at
[CODE_LABEL_NUMBER (x
) - first_label_num
][i
]
2165 != (initial_p
? reg_eliminate
[i
].initial_offset
2166 : reg_eliminate
[i
].offset
))
2167 reg_eliminate
[i
].can_eliminate
= 0;
2172 set_label_offsets (PATTERN (insn
), insn
, initial_p
);
2174 /* ... fall through ... */
2178 /* Any labels mentioned in REG_LABEL notes can be branched to indirectly
2179 and hence must have all eliminations at their initial offsets. */
2180 for (tem
= REG_NOTES (x
); tem
; tem
= XEXP (tem
, 1))
2181 if (REG_NOTE_KIND (tem
) == REG_LABEL
)
2182 set_label_offsets (XEXP (tem
, 0), insn
, 1);
2188 /* Each of the labels in the parallel or address vector must be
2189 at their initial offsets. We want the first field for PARALLEL
2190 and ADDR_VEC and the second field for ADDR_DIFF_VEC. */
2192 for (i
= 0; i
< (unsigned) XVECLEN (x
, code
== ADDR_DIFF_VEC
); i
++)
2193 set_label_offsets (XVECEXP (x
, code
== ADDR_DIFF_VEC
, i
),
2198 /* We only care about setting PC. If the source is not RETURN,
2199 IF_THEN_ELSE, or a label, disable any eliminations not at
2200 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2201 isn't one of those possibilities. For branches to a label,
2202 call ourselves recursively.
2204 Note that this can disable elimination unnecessarily when we have
2205 a non-local goto since it will look like a non-constant jump to
2206 someplace in the current function. This isn't a significant
2207 problem since such jumps will normally be when all elimination
2208 pairs are back to their initial offsets. */
2210 if (SET_DEST (x
) != pc_rtx
)
2213 switch (GET_CODE (SET_SRC (x
)))
2220 set_label_offsets (SET_SRC (x
), insn
, initial_p
);
2224 tem
= XEXP (SET_SRC (x
), 1);
2225 if (GET_CODE (tem
) == LABEL_REF
)
2226 set_label_offsets (XEXP (tem
, 0), insn
, initial_p
);
2227 else if (GET_CODE (tem
) != PC
&& GET_CODE (tem
) != RETURN
)
2230 tem
= XEXP (SET_SRC (x
), 2);
2231 if (GET_CODE (tem
) == LABEL_REF
)
2232 set_label_offsets (XEXP (tem
, 0), insn
, initial_p
);
2233 else if (GET_CODE (tem
) != PC
&& GET_CODE (tem
) != RETURN
)
2241 /* If we reach here, all eliminations must be at their initial
2242 offset because we are doing a jump to a variable address. */
2243 for (p
= reg_eliminate
; p
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; p
++)
2244 if (p
->offset
!= p
->initial_offset
)
2245 p
->can_eliminate
= 0;
2253 /* Scan X and replace any eliminable registers (such as fp) with a
2254 replacement (such as sp), plus an offset.
2256 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2257 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2258 MEM, we are allowed to replace a sum of a register and the constant zero
2259 with the register, which we cannot do outside a MEM. In addition, we need
2260 to record the fact that a register is referenced outside a MEM.
2262 If INSN is an insn, it is the insn containing X. If we replace a REG
2263 in a SET_DEST with an equivalent MEM and INSN is nonzero, write a
2264 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2265 the REG is being modified.
2267 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2268 That's used when we eliminate in expressions stored in notes.
2269 This means, do not set ref_outside_mem even if the reference
2272 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2273 replacements done assuming all offsets are at their initial values. If
2274 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2275 encounter, return the actual location so that find_reloads will do
2276 the proper thing. */
2279 eliminate_regs_1 (rtx x
, enum machine_mode mem_mode
, rtx insn
,
2280 bool may_use_invariant
)
2282 enum rtx_code code
= GET_CODE (x
);
2283 struct elim_table
*ep
;
2290 if (! current_function_decl
)
2312 /* First handle the case where we encounter a bare register that
2313 is eliminable. Replace it with a PLUS. */
2314 if (regno
< FIRST_PSEUDO_REGISTER
)
2316 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
2318 if (ep
->from_rtx
== x
&& ep
->can_eliminate
)
2319 return plus_constant (ep
->to_rtx
, ep
->previous_offset
);
2322 else if (reg_renumber
&& reg_renumber
[regno
] < 0
2323 && reg_equiv_invariant
&& reg_equiv_invariant
[regno
])
2325 if (may_use_invariant
)
2326 return eliminate_regs_1 (copy_rtx (reg_equiv_invariant
[regno
]),
2327 mem_mode
, insn
, true);
2328 /* There exists at least one use of REGNO that cannot be
2329 eliminated. Prevent the defining insn from being deleted. */
2330 reg_equiv_init
[regno
] = NULL_RTX
;
2331 alter_reg (regno
, -1);
2335 /* You might think handling MINUS in a manner similar to PLUS is a
2336 good idea. It is not. It has been tried multiple times and every
2337 time the change has had to have been reverted.
2339 Other parts of reload know a PLUS is special (gen_reload for example)
2340 and require special code to handle code a reloaded PLUS operand.
2342 Also consider backends where the flags register is clobbered by a
2343 MINUS, but we can emit a PLUS that does not clobber flags (IA-32,
2344 lea instruction comes to mind). If we try to reload a MINUS, we
2345 may kill the flags register that was holding a useful value.
2347 So, please before trying to handle MINUS, consider reload as a
2348 whole instead of this little section as well as the backend issues. */
2350 /* If this is the sum of an eliminable register and a constant, rework
2352 if (REG_P (XEXP (x
, 0))
2353 && REGNO (XEXP (x
, 0)) < FIRST_PSEUDO_REGISTER
2354 && CONSTANT_P (XEXP (x
, 1)))
2356 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
2358 if (ep
->from_rtx
== XEXP (x
, 0) && ep
->can_eliminate
)
2360 /* The only time we want to replace a PLUS with a REG (this
2361 occurs when the constant operand of the PLUS is the negative
2362 of the offset) is when we are inside a MEM. We won't want
2363 to do so at other times because that would change the
2364 structure of the insn in a way that reload can't handle.
2365 We special-case the commonest situation in
2366 eliminate_regs_in_insn, so just replace a PLUS with a
2367 PLUS here, unless inside a MEM. */
2368 if (mem_mode
!= 0 && GET_CODE (XEXP (x
, 1)) == CONST_INT
2369 && INTVAL (XEXP (x
, 1)) == - ep
->previous_offset
)
2372 return gen_rtx_PLUS (Pmode
, ep
->to_rtx
,
2373 plus_constant (XEXP (x
, 1),
2374 ep
->previous_offset
));
2377 /* If the register is not eliminable, we are done since the other
2378 operand is a constant. */
2382 /* If this is part of an address, we want to bring any constant to the
2383 outermost PLUS. We will do this by doing register replacement in
2384 our operands and seeing if a constant shows up in one of them.
2386 Note that there is no risk of modifying the structure of the insn,
2387 since we only get called for its operands, thus we are either
2388 modifying the address inside a MEM, or something like an address
2389 operand of a load-address insn. */
2392 rtx new0
= eliminate_regs_1 (XEXP (x
, 0), mem_mode
, insn
, true);
2393 rtx new1
= eliminate_regs_1 (XEXP (x
, 1), mem_mode
, insn
, true);
2395 if (reg_renumber
&& (new0
!= XEXP (x
, 0) || new1
!= XEXP (x
, 1)))
2397 /* If one side is a PLUS and the other side is a pseudo that
2398 didn't get a hard register but has a reg_equiv_constant,
2399 we must replace the constant here since it may no longer
2400 be in the position of any operand. */
2401 if (GET_CODE (new0
) == PLUS
&& REG_P (new1
)
2402 && REGNO (new1
) >= FIRST_PSEUDO_REGISTER
2403 && reg_renumber
[REGNO (new1
)] < 0
2404 && reg_equiv_constant
!= 0
2405 && reg_equiv_constant
[REGNO (new1
)] != 0)
2406 new1
= reg_equiv_constant
[REGNO (new1
)];
2407 else if (GET_CODE (new1
) == PLUS
&& REG_P (new0
)
2408 && REGNO (new0
) >= FIRST_PSEUDO_REGISTER
2409 && reg_renumber
[REGNO (new0
)] < 0
2410 && reg_equiv_constant
[REGNO (new0
)] != 0)
2411 new0
= reg_equiv_constant
[REGNO (new0
)];
2413 new = form_sum (new0
, new1
);
2415 /* As above, if we are not inside a MEM we do not want to
2416 turn a PLUS into something else. We might try to do so here
2417 for an addition of 0 if we aren't optimizing. */
2418 if (! mem_mode
&& GET_CODE (new) != PLUS
)
2419 return gen_rtx_PLUS (GET_MODE (x
), new, const0_rtx
);
2427 /* If this is the product of an eliminable register and a
2428 constant, apply the distribute law and move the constant out
2429 so that we have (plus (mult ..) ..). This is needed in order
2430 to keep load-address insns valid. This case is pathological.
2431 We ignore the possibility of overflow here. */
2432 if (REG_P (XEXP (x
, 0))
2433 && REGNO (XEXP (x
, 0)) < FIRST_PSEUDO_REGISTER
2434 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
2435 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
2437 if (ep
->from_rtx
== XEXP (x
, 0) && ep
->can_eliminate
)
2440 /* Refs inside notes don't count for this purpose. */
2441 && ! (insn
!= 0 && (GET_CODE (insn
) == EXPR_LIST
2442 || GET_CODE (insn
) == INSN_LIST
)))
2443 ep
->ref_outside_mem
= 1;
2446 plus_constant (gen_rtx_MULT (Pmode
, ep
->to_rtx
, XEXP (x
, 1)),
2447 ep
->previous_offset
* INTVAL (XEXP (x
, 1)));
2450 /* ... fall through ... */
2454 /* See comments before PLUS about handling MINUS. */
2456 case DIV
: case UDIV
:
2457 case MOD
: case UMOD
:
2458 case AND
: case IOR
: case XOR
:
2459 case ROTATERT
: case ROTATE
:
2460 case ASHIFTRT
: case LSHIFTRT
: case ASHIFT
:
2462 case GE
: case GT
: case GEU
: case GTU
:
2463 case LE
: case LT
: case LEU
: case LTU
:
2465 rtx new0
= eliminate_regs_1 (XEXP (x
, 0), mem_mode
, insn
, false);
2466 rtx new1
= XEXP (x
, 1)
2467 ? eliminate_regs_1 (XEXP (x
, 1), mem_mode
, insn
, false) : 0;
2469 if (new0
!= XEXP (x
, 0) || new1
!= XEXP (x
, 1))
2470 return gen_rtx_fmt_ee (code
, GET_MODE (x
), new0
, new1
);
2475 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2478 new = eliminate_regs_1 (XEXP (x
, 0), mem_mode
, insn
, true);
2479 if (new != XEXP (x
, 0))
2481 /* If this is a REG_DEAD note, it is not valid anymore.
2482 Using the eliminated version could result in creating a
2483 REG_DEAD note for the stack or frame pointer. */
2484 if (GET_MODE (x
) == REG_DEAD
)
2486 ? eliminate_regs_1 (XEXP (x
, 1), mem_mode
, insn
, true)
2489 x
= gen_rtx_EXPR_LIST (REG_NOTE_KIND (x
), new, XEXP (x
, 1));
2493 /* ... fall through ... */
2496 /* Now do eliminations in the rest of the chain. If this was
2497 an EXPR_LIST, this might result in allocating more memory than is
2498 strictly needed, but it simplifies the code. */
2501 new = eliminate_regs_1 (XEXP (x
, 1), mem_mode
, insn
, true);
2502 if (new != XEXP (x
, 1))
2504 gen_rtx_fmt_ee (GET_CODE (x
), GET_MODE (x
), XEXP (x
, 0), new);
2512 case STRICT_LOW_PART
:
2514 case SIGN_EXTEND
: case ZERO_EXTEND
:
2515 case TRUNCATE
: case FLOAT_EXTEND
: case FLOAT_TRUNCATE
:
2516 case FLOAT
: case FIX
:
2517 case UNSIGNED_FIX
: case UNSIGNED_FLOAT
:
2525 new = eliminate_regs_1 (XEXP (x
, 0), mem_mode
, insn
, false);
2526 if (new != XEXP (x
, 0))
2527 return gen_rtx_fmt_e (code
, GET_MODE (x
), new);
2531 /* Similar to above processing, but preserve SUBREG_BYTE.
2532 Convert (subreg (mem)) to (mem) if not paradoxical.
2533 Also, if we have a non-paradoxical (subreg (pseudo)) and the
2534 pseudo didn't get a hard reg, we must replace this with the
2535 eliminated version of the memory location because push_reload
2536 may do the replacement in certain circumstances. */
2537 if (REG_P (SUBREG_REG (x
))
2538 && (GET_MODE_SIZE (GET_MODE (x
))
2539 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
2540 && reg_equiv_memory_loc
!= 0
2541 && reg_equiv_memory_loc
[REGNO (SUBREG_REG (x
))] != 0)
2543 new = SUBREG_REG (x
);
2546 new = eliminate_regs_1 (SUBREG_REG (x
), mem_mode
, insn
, false);
2548 if (new != SUBREG_REG (x
))
2550 int x_size
= GET_MODE_SIZE (GET_MODE (x
));
2551 int new_size
= GET_MODE_SIZE (GET_MODE (new));
2554 && ((x_size
< new_size
2555 #ifdef WORD_REGISTER_OPERATIONS
2556 /* On these machines, combine can create rtl of the form
2557 (set (subreg:m1 (reg:m2 R) 0) ...)
2558 where m1 < m2, and expects something interesting to
2559 happen to the entire word. Moreover, it will use the
2560 (reg:m2 R) later, expecting all bits to be preserved.
2561 So if the number of words is the same, preserve the
2562 subreg so that push_reload can see it. */
2563 && ! ((x_size
- 1) / UNITS_PER_WORD
2564 == (new_size
-1 ) / UNITS_PER_WORD
)
2567 || x_size
== new_size
)
2569 return adjust_address_nv (new, GET_MODE (x
), SUBREG_BYTE (x
));
2571 return gen_rtx_SUBREG (GET_MODE (x
), new, SUBREG_BYTE (x
));
2577 /* Our only special processing is to pass the mode of the MEM to our
2578 recursive call and copy the flags. While we are here, handle this
2579 case more efficiently. */
2581 replace_equiv_address_nv (x
,
2582 eliminate_regs_1 (XEXP (x
, 0), GET_MODE (x
),
2586 /* Handle insn_list USE that a call to a pure function may generate. */
2587 new = eliminate_regs_1 (XEXP (x
, 0), 0, insn
, false);
2588 if (new != XEXP (x
, 0))
2589 return gen_rtx_USE (GET_MODE (x
), new);
2601 /* Process each of our operands recursively. If any have changed, make a
2603 fmt
= GET_RTX_FORMAT (code
);
2604 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++, fmt
++)
2608 new = eliminate_regs_1 (XEXP (x
, i
), mem_mode
, insn
, false);
2609 if (new != XEXP (x
, i
) && ! copied
)
2611 x
= shallow_copy_rtx (x
);
2616 else if (*fmt
== 'E')
2619 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
2621 new = eliminate_regs_1 (XVECEXP (x
, i
, j
), mem_mode
, insn
, false);
2622 if (new != XVECEXP (x
, i
, j
) && ! copied_vec
)
2624 rtvec new_v
= gen_rtvec_v (XVECLEN (x
, i
),
2628 x
= shallow_copy_rtx (x
);
2631 XVEC (x
, i
) = new_v
;
2634 XVECEXP (x
, i
, j
) = new;
2643 eliminate_regs (rtx x
, enum machine_mode mem_mode
, rtx insn
)
2645 return eliminate_regs_1 (x
, mem_mode
, insn
, false);
2648 /* Scan rtx X for modifications of elimination target registers. Update
2649 the table of eliminables to reflect the changed state. MEM_MODE is
2650 the mode of an enclosing MEM rtx, or VOIDmode if not within a MEM. */
2653 elimination_effects (rtx x
, enum machine_mode mem_mode
)
2655 enum rtx_code code
= GET_CODE (x
);
2656 struct elim_table
*ep
;
2680 /* First handle the case where we encounter a bare register that
2681 is eliminable. Replace it with a PLUS. */
2682 if (regno
< FIRST_PSEUDO_REGISTER
)
2684 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
2686 if (ep
->from_rtx
== x
&& ep
->can_eliminate
)
2689 ep
->ref_outside_mem
= 1;
2694 else if (reg_renumber
[regno
] < 0 && reg_equiv_constant
2695 && reg_equiv_constant
[regno
]
2696 && ! function_invariant_p (reg_equiv_constant
[regno
]))
2697 elimination_effects (reg_equiv_constant
[regno
], mem_mode
);
2706 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
2707 if (ep
->to_rtx
== XEXP (x
, 0))
2709 int size
= GET_MODE_SIZE (mem_mode
);
2711 /* If more bytes than MEM_MODE are pushed, account for them. */
2712 #ifdef PUSH_ROUNDING
2713 if (ep
->to_rtx
== stack_pointer_rtx
)
2714 size
= PUSH_ROUNDING (size
);
2716 if (code
== PRE_DEC
|| code
== POST_DEC
)
2718 else if (code
== PRE_INC
|| code
== POST_INC
)
2720 else if ((code
== PRE_MODIFY
|| code
== POST_MODIFY
)
2721 && GET_CODE (XEXP (x
, 1)) == PLUS
2722 && XEXP (x
, 0) == XEXP (XEXP (x
, 1), 0)
2723 && CONSTANT_P (XEXP (XEXP (x
, 1), 1)))
2724 ep
->offset
-= INTVAL (XEXP (XEXP (x
, 1), 1));
2727 /* These two aren't unary operators. */
2728 if (code
== POST_MODIFY
|| code
== PRE_MODIFY
)
2731 /* Fall through to generic unary operation case. */
2732 case STRICT_LOW_PART
:
2734 case SIGN_EXTEND
: case ZERO_EXTEND
:
2735 case TRUNCATE
: case FLOAT_EXTEND
: case FLOAT_TRUNCATE
:
2736 case FLOAT
: case FIX
:
2737 case UNSIGNED_FIX
: case UNSIGNED_FLOAT
:
2745 elimination_effects (XEXP (x
, 0), mem_mode
);
2749 if (REG_P (SUBREG_REG (x
))
2750 && (GET_MODE_SIZE (GET_MODE (x
))
2751 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
2752 && reg_equiv_memory_loc
!= 0
2753 && reg_equiv_memory_loc
[REGNO (SUBREG_REG (x
))] != 0)
2756 elimination_effects (SUBREG_REG (x
), mem_mode
);
2760 /* If using a register that is the source of an eliminate we still
2761 think can be performed, note it cannot be performed since we don't
2762 know how this register is used. */
2763 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
2764 if (ep
->from_rtx
== XEXP (x
, 0))
2765 ep
->can_eliminate
= 0;
2767 elimination_effects (XEXP (x
, 0), mem_mode
);
2771 /* If clobbering a register that is the replacement register for an
2772 elimination we still think can be performed, note that it cannot
2773 be performed. Otherwise, we need not be concerned about it. */
2774 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
2775 if (ep
->to_rtx
== XEXP (x
, 0))
2776 ep
->can_eliminate
= 0;
2778 elimination_effects (XEXP (x
, 0), mem_mode
);
2782 /* Check for setting a register that we know about. */
2783 if (REG_P (SET_DEST (x
)))
2785 /* See if this is setting the replacement register for an
2788 If DEST is the hard frame pointer, we do nothing because we
2789 assume that all assignments to the frame pointer are for
2790 non-local gotos and are being done at a time when they are valid
2791 and do not disturb anything else. Some machines want to
2792 eliminate a fake argument pointer (or even a fake frame pointer)
2793 with either the real frame or the stack pointer. Assignments to
2794 the hard frame pointer must not prevent this elimination. */
2796 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
2798 if (ep
->to_rtx
== SET_DEST (x
)
2799 && SET_DEST (x
) != hard_frame_pointer_rtx
)
2801 /* If it is being incremented, adjust the offset. Otherwise,
2802 this elimination can't be done. */
2803 rtx src
= SET_SRC (x
);
2805 if (GET_CODE (src
) == PLUS
2806 && XEXP (src
, 0) == SET_DEST (x
)
2807 && GET_CODE (XEXP (src
, 1)) == CONST_INT
)
2808 ep
->offset
-= INTVAL (XEXP (src
, 1));
2810 ep
->can_eliminate
= 0;
2814 elimination_effects (SET_DEST (x
), 0);
2815 elimination_effects (SET_SRC (x
), 0);
2819 /* Our only special processing is to pass the mode of the MEM to our
2821 elimination_effects (XEXP (x
, 0), GET_MODE (x
));
2828 fmt
= GET_RTX_FORMAT (code
);
2829 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++, fmt
++)
2832 elimination_effects (XEXP (x
, i
), mem_mode
);
2833 else if (*fmt
== 'E')
2834 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
2835 elimination_effects (XVECEXP (x
, i
, j
), mem_mode
);
2839 /* Descend through rtx X and verify that no references to eliminable registers
2840 remain. If any do remain, mark the involved register as not
2844 check_eliminable_occurrences (rtx x
)
2853 code
= GET_CODE (x
);
2855 if (code
== REG
&& REGNO (x
) < FIRST_PSEUDO_REGISTER
)
2857 struct elim_table
*ep
;
2859 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
2860 if (ep
->from_rtx
== x
)
2861 ep
->can_eliminate
= 0;
2865 fmt
= GET_RTX_FORMAT (code
);
2866 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++, fmt
++)
2869 check_eliminable_occurrences (XEXP (x
, i
));
2870 else if (*fmt
== 'E')
2873 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
2874 check_eliminable_occurrences (XVECEXP (x
, i
, j
));
2879 /* Scan INSN and eliminate all eliminable registers in it.
2881 If REPLACE is nonzero, do the replacement destructively. Also
2882 delete the insn as dead it if it is setting an eliminable register.
2884 If REPLACE is zero, do all our allocations in reload_obstack.
2886 If no eliminations were done and this insn doesn't require any elimination
2887 processing (these are not identical conditions: it might be updating sp,
2888 but not referencing fp; this needs to be seen during reload_as_needed so
2889 that the offset between fp and sp can be taken into consideration), zero
2890 is returned. Otherwise, 1 is returned. */
2893 eliminate_regs_in_insn (rtx insn
, int replace
)
2895 int icode
= recog_memoized (insn
);
2896 rtx old_body
= PATTERN (insn
);
2897 int insn_is_asm
= asm_noperands (old_body
) >= 0;
2898 rtx old_set
= single_set (insn
);
2902 rtx substed_operand
[MAX_RECOG_OPERANDS
];
2903 rtx orig_operand
[MAX_RECOG_OPERANDS
];
2904 struct elim_table
*ep
;
2905 rtx plus_src
, plus_cst_src
;
2907 if (! insn_is_asm
&& icode
< 0)
2909 gcc_assert (GET_CODE (PATTERN (insn
)) == USE
2910 || GET_CODE (PATTERN (insn
)) == CLOBBER
2911 || GET_CODE (PATTERN (insn
)) == ADDR_VEC
2912 || GET_CODE (PATTERN (insn
)) == ADDR_DIFF_VEC
2913 || GET_CODE (PATTERN (insn
)) == ASM_INPUT
);
2917 if (old_set
!= 0 && REG_P (SET_DEST (old_set
))
2918 && REGNO (SET_DEST (old_set
)) < FIRST_PSEUDO_REGISTER
)
2920 /* Check for setting an eliminable register. */
2921 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
2922 if (ep
->from_rtx
== SET_DEST (old_set
) && ep
->can_eliminate
)
2924 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
2925 /* If this is setting the frame pointer register to the
2926 hardware frame pointer register and this is an elimination
2927 that will be done (tested above), this insn is really
2928 adjusting the frame pointer downward to compensate for
2929 the adjustment done before a nonlocal goto. */
2930 if (ep
->from
== FRAME_POINTER_REGNUM
2931 && ep
->to
== HARD_FRAME_POINTER_REGNUM
)
2933 rtx base
= SET_SRC (old_set
);
2934 rtx base_insn
= insn
;
2935 HOST_WIDE_INT offset
= 0;
2937 while (base
!= ep
->to_rtx
)
2939 rtx prev_insn
, prev_set
;
2941 if (GET_CODE (base
) == PLUS
2942 && GET_CODE (XEXP (base
, 1)) == CONST_INT
)
2944 offset
+= INTVAL (XEXP (base
, 1));
2945 base
= XEXP (base
, 0);
2947 else if ((prev_insn
= prev_nonnote_insn (base_insn
)) != 0
2948 && (prev_set
= single_set (prev_insn
)) != 0
2949 && rtx_equal_p (SET_DEST (prev_set
), base
))
2951 base
= SET_SRC (prev_set
);
2952 base_insn
= prev_insn
;
2958 if (base
== ep
->to_rtx
)
2961 = plus_constant (ep
->to_rtx
, offset
- ep
->offset
);
2963 new_body
= old_body
;
2966 new_body
= copy_insn (old_body
);
2967 if (REG_NOTES (insn
))
2968 REG_NOTES (insn
) = copy_insn_1 (REG_NOTES (insn
));
2970 PATTERN (insn
) = new_body
;
2971 old_set
= single_set (insn
);
2973 /* First see if this insn remains valid when we
2974 make the change. If not, keep the INSN_CODE
2975 the same and let reload fit it up. */
2976 validate_change (insn
, &SET_SRC (old_set
), src
, 1);
2977 validate_change (insn
, &SET_DEST (old_set
),
2979 if (! apply_change_group ())
2981 SET_SRC (old_set
) = src
;
2982 SET_DEST (old_set
) = ep
->to_rtx
;
2991 /* In this case this insn isn't serving a useful purpose. We
2992 will delete it in reload_as_needed once we know that this
2993 elimination is, in fact, being done.
2995 If REPLACE isn't set, we can't delete this insn, but needn't
2996 process it since it won't be used unless something changes. */
2999 delete_dead_insn (insn
);
3007 /* We allow one special case which happens to work on all machines we
3008 currently support: a single set with the source or a REG_EQUAL
3009 note being a PLUS of an eliminable register and a constant. */
3010 plus_src
= plus_cst_src
= 0;
3011 if (old_set
&& REG_P (SET_DEST (old_set
)))
3013 if (GET_CODE (SET_SRC (old_set
)) == PLUS
)
3014 plus_src
= SET_SRC (old_set
);
3015 /* First see if the source is of the form (plus (...) CST). */
3017 && GET_CODE (XEXP (plus_src
, 1)) == CONST_INT
)
3018 plus_cst_src
= plus_src
;
3019 else if (REG_P (SET_SRC (old_set
))
3022 /* Otherwise, see if we have a REG_EQUAL note of the form
3023 (plus (...) CST). */
3025 for (links
= REG_NOTES (insn
); links
; links
= XEXP (links
, 1))
3027 if (REG_NOTE_KIND (links
) == REG_EQUAL
3028 && GET_CODE (XEXP (links
, 0)) == PLUS
3029 && GET_CODE (XEXP (XEXP (links
, 0), 1)) == CONST_INT
)
3031 plus_cst_src
= XEXP (links
, 0);
3037 /* Check that the first operand of the PLUS is a hard reg or
3038 the lowpart subreg of one. */
3041 rtx reg
= XEXP (plus_cst_src
, 0);
3042 if (GET_CODE (reg
) == SUBREG
&& subreg_lowpart_p (reg
))
3043 reg
= SUBREG_REG (reg
);
3045 if (!REG_P (reg
) || REGNO (reg
) >= FIRST_PSEUDO_REGISTER
)
3051 rtx reg
= XEXP (plus_cst_src
, 0);
3052 HOST_WIDE_INT offset
= INTVAL (XEXP (plus_cst_src
, 1));
3054 if (GET_CODE (reg
) == SUBREG
)
3055 reg
= SUBREG_REG (reg
);
3057 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3058 if (ep
->from_rtx
== reg
&& ep
->can_eliminate
)
3060 rtx to_rtx
= ep
->to_rtx
;
3061 offset
+= ep
->offset
;
3063 if (GET_CODE (XEXP (plus_cst_src
, 0)) == SUBREG
)
3064 to_rtx
= gen_lowpart (GET_MODE (XEXP (plus_cst_src
, 0)),
3069 /* We assume here that if we need a PARALLEL with
3070 CLOBBERs for this assignment, we can do with the
3071 MATCH_SCRATCHes that add_clobbers allocates.
3072 There's not much we can do if that doesn't work. */
3073 PATTERN (insn
) = gen_rtx_SET (VOIDmode
,
3077 INSN_CODE (insn
) = recog (PATTERN (insn
), insn
, &num_clobbers
);
3080 rtvec vec
= rtvec_alloc (num_clobbers
+ 1);
3082 vec
->elem
[0] = PATTERN (insn
);
3083 PATTERN (insn
) = gen_rtx_PARALLEL (VOIDmode
, vec
);
3084 add_clobbers (PATTERN (insn
), INSN_CODE (insn
));
3086 gcc_assert (INSN_CODE (insn
) >= 0);
3088 /* If we have a nonzero offset, and the source is already
3089 a simple REG, the following transformation would
3090 increase the cost of the insn by replacing a simple REG
3091 with (plus (reg sp) CST). So try only when we already
3092 had a PLUS before. */
3095 new_body
= old_body
;
3098 new_body
= copy_insn (old_body
);
3099 if (REG_NOTES (insn
))
3100 REG_NOTES (insn
) = copy_insn_1 (REG_NOTES (insn
));
3102 PATTERN (insn
) = new_body
;
3103 old_set
= single_set (insn
);
3105 XEXP (SET_SRC (old_set
), 0) = to_rtx
;
3106 XEXP (SET_SRC (old_set
), 1) = GEN_INT (offset
);
3112 /* This can't have an effect on elimination offsets, so skip right
3118 /* Determine the effects of this insn on elimination offsets. */
3119 elimination_effects (old_body
, 0);
3121 /* Eliminate all eliminable registers occurring in operands that
3122 can be handled by reload. */
3123 extract_insn (insn
);
3124 for (i
= 0; i
< recog_data
.n_operands
; i
++)
3126 orig_operand
[i
] = recog_data
.operand
[i
];
3127 substed_operand
[i
] = recog_data
.operand
[i
];
3129 /* For an asm statement, every operand is eliminable. */
3130 if (insn_is_asm
|| insn_data
[icode
].operand
[i
].eliminable
)
3132 bool is_set_src
, in_plus
;
3134 /* Check for setting a register that we know about. */
3135 if (recog_data
.operand_type
[i
] != OP_IN
3136 && REG_P (orig_operand
[i
]))
3138 /* If we are assigning to a register that can be eliminated, it
3139 must be as part of a PARALLEL, since the code above handles
3140 single SETs. We must indicate that we can no longer
3141 eliminate this reg. */
3142 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
3144 if (ep
->from_rtx
== orig_operand
[i
])
3145 ep
->can_eliminate
= 0;
3148 /* Companion to the above plus substitution, we can allow
3149 invariants as the source of a plain move. */
3151 if (old_set
&& recog_data
.operand_loc
[i
] == &SET_SRC (old_set
))
3155 && (recog_data
.operand_loc
[i
] == &XEXP (plus_src
, 0)
3156 || recog_data
.operand_loc
[i
] == &XEXP (plus_src
, 1)))
3160 = eliminate_regs_1 (recog_data
.operand
[i
], 0,
3161 replace
? insn
: NULL_RTX
,
3162 is_set_src
|| in_plus
);
3163 if (substed_operand
[i
] != orig_operand
[i
])
3165 /* Terminate the search in check_eliminable_occurrences at
3167 *recog_data
.operand_loc
[i
] = 0;
3169 /* If an output operand changed from a REG to a MEM and INSN is an
3170 insn, write a CLOBBER insn. */
3171 if (recog_data
.operand_type
[i
] != OP_IN
3172 && REG_P (orig_operand
[i
])
3173 && MEM_P (substed_operand
[i
])
3175 emit_insn_after (gen_rtx_CLOBBER (VOIDmode
, orig_operand
[i
]),
3180 for (i
= 0; i
< recog_data
.n_dups
; i
++)
3181 *recog_data
.dup_loc
[i
]
3182 = *recog_data
.operand_loc
[(int) recog_data
.dup_num
[i
]];
3184 /* If any eliminable remain, they aren't eliminable anymore. */
3185 check_eliminable_occurrences (old_body
);
3187 /* Substitute the operands; the new values are in the substed_operand
3189 for (i
= 0; i
< recog_data
.n_operands
; i
++)
3190 *recog_data
.operand_loc
[i
] = substed_operand
[i
];
3191 for (i
= 0; i
< recog_data
.n_dups
; i
++)
3192 *recog_data
.dup_loc
[i
] = substed_operand
[(int) recog_data
.dup_num
[i
]];
3194 /* If we are replacing a body that was a (set X (plus Y Z)), try to
3195 re-recognize the insn. We do this in case we had a simple addition
3196 but now can do this as a load-address. This saves an insn in this
3198 If re-recognition fails, the old insn code number will still be used,
3199 and some register operands may have changed into PLUS expressions.
3200 These will be handled by find_reloads by loading them into a register
3205 /* If we aren't replacing things permanently and we changed something,
3206 make another copy to ensure that all the RTL is new. Otherwise
3207 things can go wrong if find_reload swaps commutative operands
3208 and one is inside RTL that has been copied while the other is not. */
3209 new_body
= old_body
;
3212 new_body
= copy_insn (old_body
);
3213 if (REG_NOTES (insn
))
3214 REG_NOTES (insn
) = copy_insn_1 (REG_NOTES (insn
));
3216 PATTERN (insn
) = new_body
;
3218 /* If we had a move insn but now we don't, rerecognize it. This will
3219 cause spurious re-recognition if the old move had a PARALLEL since
3220 the new one still will, but we can't call single_set without
3221 having put NEW_BODY into the insn and the re-recognition won't
3222 hurt in this rare case. */
3223 /* ??? Why this huge if statement - why don't we just rerecognize the
3227 && ((REG_P (SET_SRC (old_set
))
3228 && (GET_CODE (new_body
) != SET
3229 || !REG_P (SET_SRC (new_body
))))
3230 /* If this was a load from or store to memory, compare
3231 the MEM in recog_data.operand to the one in the insn.
3232 If they are not equal, then rerecognize the insn. */
3234 && ((MEM_P (SET_SRC (old_set
))
3235 && SET_SRC (old_set
) != recog_data
.operand
[1])
3236 || (MEM_P (SET_DEST (old_set
))
3237 && SET_DEST (old_set
) != recog_data
.operand
[0])))
3238 /* If this was an add insn before, rerecognize. */
3239 || GET_CODE (SET_SRC (old_set
)) == PLUS
))
3241 int new_icode
= recog (PATTERN (insn
), insn
, 0);
3243 INSN_CODE (insn
) = new_icode
;
3247 /* Restore the old body. If there were any changes to it, we made a copy
3248 of it while the changes were still in place, so we'll correctly return
3249 a modified insn below. */
3252 /* Restore the old body. */
3253 for (i
= 0; i
< recog_data
.n_operands
; i
++)
3254 *recog_data
.operand_loc
[i
] = orig_operand
[i
];
3255 for (i
= 0; i
< recog_data
.n_dups
; i
++)
3256 *recog_data
.dup_loc
[i
] = orig_operand
[(int) recog_data
.dup_num
[i
]];
3259 /* Update all elimination pairs to reflect the status after the current
3260 insn. The changes we make were determined by the earlier call to
3261 elimination_effects.
3263 We also detect cases where register elimination cannot be done,
3264 namely, if a register would be both changed and referenced outside a MEM
3265 in the resulting insn since such an insn is often undefined and, even if
3266 not, we cannot know what meaning will be given to it. Note that it is
3267 valid to have a register used in an address in an insn that changes it
3268 (presumably with a pre- or post-increment or decrement).
3270 If anything changes, return nonzero. */
3272 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3274 if (ep
->previous_offset
!= ep
->offset
&& ep
->ref_outside_mem
)
3275 ep
->can_eliminate
= 0;
3277 ep
->ref_outside_mem
= 0;
3279 if (ep
->previous_offset
!= ep
->offset
)
3284 /* If we changed something, perform elimination in REG_NOTES. This is
3285 needed even when REPLACE is zero because a REG_DEAD note might refer
3286 to a register that we eliminate and could cause a different number
3287 of spill registers to be needed in the final reload pass than in
3289 if (val
&& REG_NOTES (insn
) != 0)
3291 = eliminate_regs_1 (REG_NOTES (insn
), 0, REG_NOTES (insn
), true);
3296 /* Loop through all elimination pairs.
3297 Recalculate the number not at initial offset.
3299 Compute the maximum offset (minimum offset if the stack does not
3300 grow downward) for each elimination pair. */
3303 update_eliminable_offsets (void)
3305 struct elim_table
*ep
;
3307 num_not_at_initial_offset
= 0;
3308 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3310 ep
->previous_offset
= ep
->offset
;
3311 if (ep
->can_eliminate
&& ep
->offset
!= ep
->initial_offset
)
3312 num_not_at_initial_offset
++;
3316 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3317 replacement we currently believe is valid, mark it as not eliminable if X
3318 modifies DEST in any way other than by adding a constant integer to it.
3320 If DEST is the frame pointer, we do nothing because we assume that
3321 all assignments to the hard frame pointer are nonlocal gotos and are being
3322 done at a time when they are valid and do not disturb anything else.
3323 Some machines want to eliminate a fake argument pointer with either the
3324 frame or stack pointer. Assignments to the hard frame pointer must not
3325 prevent this elimination.
3327 Called via note_stores from reload before starting its passes to scan
3328 the insns of the function. */
3331 mark_not_eliminable (rtx dest
, rtx x
, void *data ATTRIBUTE_UNUSED
)
3335 /* A SUBREG of a hard register here is just changing its mode. We should
3336 not see a SUBREG of an eliminable hard register, but check just in
3338 if (GET_CODE (dest
) == SUBREG
)
3339 dest
= SUBREG_REG (dest
);
3341 if (dest
== hard_frame_pointer_rtx
)
3344 for (i
= 0; i
< NUM_ELIMINABLE_REGS
; i
++)
3345 if (reg_eliminate
[i
].can_eliminate
&& dest
== reg_eliminate
[i
].to_rtx
3346 && (GET_CODE (x
) != SET
3347 || GET_CODE (SET_SRC (x
)) != PLUS
3348 || XEXP (SET_SRC (x
), 0) != dest
3349 || GET_CODE (XEXP (SET_SRC (x
), 1)) != CONST_INT
))
3351 reg_eliminate
[i
].can_eliminate_previous
3352 = reg_eliminate
[i
].can_eliminate
= 0;
3357 /* Verify that the initial elimination offsets did not change since the
3358 last call to set_initial_elim_offsets. This is used to catch cases
3359 where something illegal happened during reload_as_needed that could
3360 cause incorrect code to be generated if we did not check for it. */
3363 verify_initial_elim_offsets (void)
3367 if (!num_eliminable
)
3370 #ifdef ELIMINABLE_REGS
3372 struct elim_table
*ep
;
3374 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3376 INITIAL_ELIMINATION_OFFSET (ep
->from
, ep
->to
, t
);
3377 if (t
!= ep
->initial_offset
)
3382 INITIAL_FRAME_POINTER_OFFSET (t
);
3383 if (t
!= reg_eliminate
[0].initial_offset
)
3390 /* Reset all offsets on eliminable registers to their initial values. */
3393 set_initial_elim_offsets (void)
3395 struct elim_table
*ep
= reg_eliminate
;
3397 #ifdef ELIMINABLE_REGS
3398 for (; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3400 INITIAL_ELIMINATION_OFFSET (ep
->from
, ep
->to
, ep
->initial_offset
);
3401 ep
->previous_offset
= ep
->offset
= ep
->initial_offset
;
3404 INITIAL_FRAME_POINTER_OFFSET (ep
->initial_offset
);
3405 ep
->previous_offset
= ep
->offset
= ep
->initial_offset
;
3408 num_not_at_initial_offset
= 0;
3411 /* Subroutine of set_initial_label_offsets called via for_each_eh_label. */
3414 set_initial_eh_label_offset (rtx label
)
3416 set_label_offsets (label
, NULL_RTX
, 1);
3419 /* Initialize the known label offsets.
3420 Set a known offset for each forced label to be at the initial offset
3421 of each elimination. We do this because we assume that all
3422 computed jumps occur from a location where each elimination is
3423 at its initial offset.
3424 For all other labels, show that we don't know the offsets. */
3427 set_initial_label_offsets (void)
3430 memset (offsets_known_at
, 0, num_labels
);
3432 for (x
= forced_labels
; x
; x
= XEXP (x
, 1))
3434 set_label_offsets (XEXP (x
, 0), NULL_RTX
, 1);
3436 for_each_eh_label (set_initial_eh_label_offset
);
3439 /* Set all elimination offsets to the known values for the code label given
3443 set_offsets_for_label (rtx insn
)
3446 int label_nr
= CODE_LABEL_NUMBER (insn
);
3447 struct elim_table
*ep
;
3449 num_not_at_initial_offset
= 0;
3450 for (i
= 0, ep
= reg_eliminate
; i
< NUM_ELIMINABLE_REGS
; ep
++, i
++)
3452 ep
->offset
= ep
->previous_offset
3453 = offsets_at
[label_nr
- first_label_num
][i
];
3454 if (ep
->can_eliminate
&& ep
->offset
!= ep
->initial_offset
)
3455 num_not_at_initial_offset
++;
3459 /* See if anything that happened changes which eliminations are valid.
3460 For example, on the SPARC, whether or not the frame pointer can
3461 be eliminated can depend on what registers have been used. We need
3462 not check some conditions again (such as flag_omit_frame_pointer)
3463 since they can't have changed. */
3466 update_eliminables (HARD_REG_SET
*pset
)
3468 int previous_frame_pointer_needed
= frame_pointer_needed
;
3469 struct elim_table
*ep
;
3471 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3472 if ((ep
->from
== HARD_FRAME_POINTER_REGNUM
&& FRAME_POINTER_REQUIRED
)
3473 #ifdef ELIMINABLE_REGS
3474 || ! CAN_ELIMINATE (ep
->from
, ep
->to
)
3477 ep
->can_eliminate
= 0;
3479 /* Look for the case where we have discovered that we can't replace
3480 register A with register B and that means that we will now be
3481 trying to replace register A with register C. This means we can
3482 no longer replace register C with register B and we need to disable
3483 such an elimination, if it exists. This occurs often with A == ap,
3484 B == sp, and C == fp. */
3486 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3488 struct elim_table
*op
;
3491 if (! ep
->can_eliminate
&& ep
->can_eliminate_previous
)
3493 /* Find the current elimination for ep->from, if there is a
3495 for (op
= reg_eliminate
;
3496 op
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; op
++)
3497 if (op
->from
== ep
->from
&& op
->can_eliminate
)
3503 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
3505 for (op
= reg_eliminate
;
3506 op
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; op
++)
3507 if (op
->from
== new_to
&& op
->to
== ep
->to
)
3508 op
->can_eliminate
= 0;
3512 /* See if any registers that we thought we could eliminate the previous
3513 time are no longer eliminable. If so, something has changed and we
3514 must spill the register. Also, recompute the number of eliminable
3515 registers and see if the frame pointer is needed; it is if there is
3516 no elimination of the frame pointer that we can perform. */
3518 frame_pointer_needed
= 1;
3519 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3521 if (ep
->can_eliminate
&& ep
->from
== FRAME_POINTER_REGNUM
3522 && ep
->to
!= HARD_FRAME_POINTER_REGNUM
)
3523 frame_pointer_needed
= 0;
3525 if (! ep
->can_eliminate
&& ep
->can_eliminate_previous
)
3527 ep
->can_eliminate_previous
= 0;
3528 SET_HARD_REG_BIT (*pset
, ep
->from
);
3533 /* If we didn't need a frame pointer last time, but we do now, spill
3534 the hard frame pointer. */
3535 if (frame_pointer_needed
&& ! previous_frame_pointer_needed
)
3536 SET_HARD_REG_BIT (*pset
, HARD_FRAME_POINTER_REGNUM
);
3539 /* Initialize the table of registers to eliminate. */
3542 init_elim_table (void)
3544 struct elim_table
*ep
;
3545 #ifdef ELIMINABLE_REGS
3546 const struct elim_table_1
*ep1
;
3550 reg_eliminate
= xcalloc (sizeof (struct elim_table
), NUM_ELIMINABLE_REGS
);
3552 /* Does this function require a frame pointer? */
3554 frame_pointer_needed
= (! flag_omit_frame_pointer
3555 /* ?? If EXIT_IGNORE_STACK is set, we will not save
3556 and restore sp for alloca. So we can't eliminate
3557 the frame pointer in that case. At some point,
3558 we should improve this by emitting the
3559 sp-adjusting insns for this case. */
3560 || (current_function_calls_alloca
3561 && EXIT_IGNORE_STACK
)
3562 || current_function_accesses_prior_frames
3563 || FRAME_POINTER_REQUIRED
);
3567 #ifdef ELIMINABLE_REGS
3568 for (ep
= reg_eliminate
, ep1
= reg_eliminate_1
;
3569 ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++, ep1
++)
3571 ep
->from
= ep1
->from
;
3573 ep
->can_eliminate
= ep
->can_eliminate_previous
3574 = (CAN_ELIMINATE (ep
->from
, ep
->to
)
3575 && ! (ep
->to
== STACK_POINTER_REGNUM
&& frame_pointer_needed
));
3578 reg_eliminate
[0].from
= reg_eliminate_1
[0].from
;
3579 reg_eliminate
[0].to
= reg_eliminate_1
[0].to
;
3580 reg_eliminate
[0].can_eliminate
= reg_eliminate
[0].can_eliminate_previous
3581 = ! frame_pointer_needed
;
3584 /* Count the number of eliminable registers and build the FROM and TO
3585 REG rtx's. Note that code in gen_rtx_REG will cause, e.g.,
3586 gen_rtx_REG (Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
3587 We depend on this. */
3588 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3590 num_eliminable
+= ep
->can_eliminate
;
3591 ep
->from_rtx
= gen_rtx_REG (Pmode
, ep
->from
);
3592 ep
->to_rtx
= gen_rtx_REG (Pmode
, ep
->to
);
3596 /* Kick all pseudos out of hard register REGNO.
3598 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
3599 because we found we can't eliminate some register. In the case, no pseudos
3600 are allowed to be in the register, even if they are only in a block that
3601 doesn't require spill registers, unlike the case when we are spilling this
3602 hard reg to produce another spill register.
3604 Return nonzero if any pseudos needed to be kicked out. */
3607 spill_hard_reg (unsigned int regno
, int cant_eliminate
)
3613 SET_HARD_REG_BIT (bad_spill_regs_global
, regno
);
3614 regs_ever_live
[regno
] = 1;
3617 /* Spill every pseudo reg that was allocated to this reg
3618 or to something that overlaps this reg. */
3620 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
3621 if (reg_renumber
[i
] >= 0
3622 && (unsigned int) reg_renumber
[i
] <= regno
3623 && ((unsigned int) reg_renumber
[i
]
3624 + hard_regno_nregs
[(unsigned int) reg_renumber
[i
]]
3625 [PSEUDO_REGNO_MODE (i
)]
3627 SET_REGNO_REG_SET (&spilled_pseudos
, i
);
3630 /* After find_reload_regs has been run for all insn that need reloads,
3631 and/or spill_hard_regs was called, this function is used to actually
3632 spill pseudo registers and try to reallocate them. It also sets up the
3633 spill_regs array for use by choose_reload_regs. */
3636 finish_spills (int global
)
3638 struct insn_chain
*chain
;
3639 int something_changed
= 0;
3641 reg_set_iterator rsi
;
3643 /* Build the spill_regs array for the function. */
3644 /* If there are some registers still to eliminate and one of the spill regs
3645 wasn't ever used before, additional stack space may have to be
3646 allocated to store this register. Thus, we may have changed the offset
3647 between the stack and frame pointers, so mark that something has changed.
3649 One might think that we need only set VAL to 1 if this is a call-used
3650 register. However, the set of registers that must be saved by the
3651 prologue is not identical to the call-used set. For example, the
3652 register used by the call insn for the return PC is a call-used register,
3653 but must be saved by the prologue. */
3656 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
3657 if (TEST_HARD_REG_BIT (used_spill_regs
, i
))
3659 spill_reg_order
[i
] = n_spills
;
3660 spill_regs
[n_spills
++] = i
;
3661 if (num_eliminable
&& ! regs_ever_live
[i
])
3662 something_changed
= 1;
3663 regs_ever_live
[i
] = 1;
3666 spill_reg_order
[i
] = -1;
3668 EXECUTE_IF_SET_IN_REG_SET (&spilled_pseudos
, FIRST_PSEUDO_REGISTER
, i
, rsi
)
3670 /* Record the current hard register the pseudo is allocated to in
3671 pseudo_previous_regs so we avoid reallocating it to the same
3672 hard reg in a later pass. */
3673 gcc_assert (reg_renumber
[i
] >= 0);
3675 SET_HARD_REG_BIT (pseudo_previous_regs
[i
], reg_renumber
[i
]);
3676 /* Mark it as no longer having a hard register home. */
3677 reg_renumber
[i
] = -1;
3678 /* We will need to scan everything again. */
3679 something_changed
= 1;
3682 /* Retry global register allocation if possible. */
3685 memset (pseudo_forbidden_regs
, 0, max_regno
* sizeof (HARD_REG_SET
));
3686 /* For every insn that needs reloads, set the registers used as spill
3687 regs in pseudo_forbidden_regs for every pseudo live across the
3689 for (chain
= insns_need_reload
; chain
; chain
= chain
->next_need_reload
)
3691 EXECUTE_IF_SET_IN_REG_SET
3692 (&chain
->live_throughout
, FIRST_PSEUDO_REGISTER
, i
, rsi
)
3694 IOR_HARD_REG_SET (pseudo_forbidden_regs
[i
],
3695 chain
->used_spill_regs
);
3697 EXECUTE_IF_SET_IN_REG_SET
3698 (&chain
->dead_or_set
, FIRST_PSEUDO_REGISTER
, i
, rsi
)
3700 IOR_HARD_REG_SET (pseudo_forbidden_regs
[i
],
3701 chain
->used_spill_regs
);
3705 /* Retry allocating the spilled pseudos. For each reg, merge the
3706 various reg sets that indicate which hard regs can't be used,
3707 and call retry_global_alloc.
3708 We change spill_pseudos here to only contain pseudos that did not
3709 get a new hard register. */
3710 for (i
= FIRST_PSEUDO_REGISTER
; i
< (unsigned)max_regno
; i
++)
3711 if (reg_old_renumber
[i
] != reg_renumber
[i
])
3713 HARD_REG_SET forbidden
;
3714 COPY_HARD_REG_SET (forbidden
, bad_spill_regs_global
);
3715 IOR_HARD_REG_SET (forbidden
, pseudo_forbidden_regs
[i
]);
3716 IOR_HARD_REG_SET (forbidden
, pseudo_previous_regs
[i
]);
3717 retry_global_alloc (i
, forbidden
);
3718 if (reg_renumber
[i
] >= 0)
3719 CLEAR_REGNO_REG_SET (&spilled_pseudos
, i
);
3723 /* Fix up the register information in the insn chain.
3724 This involves deleting those of the spilled pseudos which did not get
3725 a new hard register home from the live_{before,after} sets. */
3726 for (chain
= reload_insn_chain
; chain
; chain
= chain
->next
)
3728 HARD_REG_SET used_by_pseudos
;
3729 HARD_REG_SET used_by_pseudos2
;
3731 AND_COMPL_REG_SET (&chain
->live_throughout
, &spilled_pseudos
);
3732 AND_COMPL_REG_SET (&chain
->dead_or_set
, &spilled_pseudos
);
3734 /* Mark any unallocated hard regs as available for spills. That
3735 makes inheritance work somewhat better. */
3736 if (chain
->need_reload
)
3738 REG_SET_TO_HARD_REG_SET (used_by_pseudos
, &chain
->live_throughout
);
3739 REG_SET_TO_HARD_REG_SET (used_by_pseudos2
, &chain
->dead_or_set
);
3740 IOR_HARD_REG_SET (used_by_pseudos
, used_by_pseudos2
);
3742 /* Save the old value for the sanity test below. */
3743 COPY_HARD_REG_SET (used_by_pseudos2
, chain
->used_spill_regs
);
3745 compute_use_by_pseudos (&used_by_pseudos
, &chain
->live_throughout
);
3746 compute_use_by_pseudos (&used_by_pseudos
, &chain
->dead_or_set
);
3747 COMPL_HARD_REG_SET (chain
->used_spill_regs
, used_by_pseudos
);
3748 AND_HARD_REG_SET (chain
->used_spill_regs
, used_spill_regs
);
3750 /* Make sure we only enlarge the set. */
3751 GO_IF_HARD_REG_SUBSET (used_by_pseudos2
, chain
->used_spill_regs
, ok
);
3757 /* Let alter_reg modify the reg rtx's for the modified pseudos. */
3758 for (i
= FIRST_PSEUDO_REGISTER
; i
< (unsigned)max_regno
; i
++)
3760 int regno
= reg_renumber
[i
];
3761 if (reg_old_renumber
[i
] == regno
)
3764 alter_reg (i
, reg_old_renumber
[i
]);
3765 reg_old_renumber
[i
] = regno
;
3769 fprintf (dump_file
, " Register %d now on stack.\n\n", i
);
3771 fprintf (dump_file
, " Register %d now in %d.\n\n",
3772 i
, reg_renumber
[i
]);
3776 return something_changed
;
3779 /* Find all paradoxical subregs within X and update reg_max_ref_width. */
3782 scan_paradoxical_subregs (rtx x
)
3786 enum rtx_code code
= GET_CODE (x
);
3796 case CONST_VECTOR
: /* shouldn't happen, but just in case. */
3804 if (REG_P (SUBREG_REG (x
))
3805 && GET_MODE_SIZE (GET_MODE (x
)) > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
3806 reg_max_ref_width
[REGNO (SUBREG_REG (x
))]
3807 = GET_MODE_SIZE (GET_MODE (x
));
3814 fmt
= GET_RTX_FORMAT (code
);
3815 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
3818 scan_paradoxical_subregs (XEXP (x
, i
));
3819 else if (fmt
[i
] == 'E')
3822 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3823 scan_paradoxical_subregs (XVECEXP (x
, i
, j
));
3828 /* A subroutine of reload_as_needed. If INSN has a REG_EH_REGION note,
3829 examine all of the reload insns between PREV and NEXT exclusive, and
3830 annotate all that may trap. */
3833 fixup_eh_region_note (rtx insn
, rtx prev
, rtx next
)
3835 rtx note
= find_reg_note (insn
, REG_EH_REGION
, NULL_RTX
);
3836 unsigned int trap_count
;
3842 if (may_trap_p (PATTERN (insn
)))
3846 remove_note (insn
, note
);
3850 for (i
= NEXT_INSN (prev
); i
!= next
; i
= NEXT_INSN (i
))
3851 if (INSN_P (i
) && i
!= insn
&& may_trap_p (PATTERN (i
)))
3855 = gen_rtx_EXPR_LIST (REG_EH_REGION
, XEXP (note
, 0), REG_NOTES (i
));
3859 /* Reload pseudo-registers into hard regs around each insn as needed.
3860 Additional register load insns are output before the insn that needs it
3861 and perhaps store insns after insns that modify the reloaded pseudo reg.
3863 reg_last_reload_reg and reg_reloaded_contents keep track of
3864 which registers are already available in reload registers.
3865 We update these for the reloads that we perform,
3866 as the insns are scanned. */
3869 reload_as_needed (int live_known
)
3871 struct insn_chain
*chain
;
3872 #if defined (AUTO_INC_DEC)
3877 memset (spill_reg_rtx
, 0, sizeof spill_reg_rtx
);
3878 memset (spill_reg_store
, 0, sizeof spill_reg_store
);
3879 reg_last_reload_reg
= XCNEWVEC (rtx
, max_regno
);
3880 reg_has_output_reload
= XNEWVEC (char, max_regno
);
3881 CLEAR_HARD_REG_SET (reg_reloaded_valid
);
3882 CLEAR_HARD_REG_SET (reg_reloaded_call_part_clobbered
);
3884 set_initial_elim_offsets ();
3886 for (chain
= reload_insn_chain
; chain
; chain
= chain
->next
)
3889 rtx insn
= chain
->insn
;
3890 rtx old_next
= NEXT_INSN (insn
);
3892 /* If we pass a label, copy the offsets from the label information
3893 into the current offsets of each elimination. */
3895 set_offsets_for_label (insn
);
3897 else if (INSN_P (insn
))
3899 rtx oldpat
= copy_rtx (PATTERN (insn
));
3901 /* If this is a USE and CLOBBER of a MEM, ensure that any
3902 references to eliminable registers have been removed. */
3904 if ((GET_CODE (PATTERN (insn
)) == USE
3905 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
3906 && MEM_P (XEXP (PATTERN (insn
), 0)))
3907 XEXP (XEXP (PATTERN (insn
), 0), 0)
3908 = eliminate_regs (XEXP (XEXP (PATTERN (insn
), 0), 0),
3909 GET_MODE (XEXP (PATTERN (insn
), 0)),
3912 /* If we need to do register elimination processing, do so.
3913 This might delete the insn, in which case we are done. */
3914 if ((num_eliminable
|| num_eliminable_invariants
) && chain
->need_elim
)
3916 eliminate_regs_in_insn (insn
, 1);
3919 update_eliminable_offsets ();
3924 /* If need_elim is nonzero but need_reload is zero, one might think
3925 that we could simply set n_reloads to 0. However, find_reloads
3926 could have done some manipulation of the insn (such as swapping
3927 commutative operands), and these manipulations are lost during
3928 the first pass for every insn that needs register elimination.
3929 So the actions of find_reloads must be redone here. */
3931 if (! chain
->need_elim
&& ! chain
->need_reload
3932 && ! chain
->need_operand_change
)
3934 /* First find the pseudo regs that must be reloaded for this insn.
3935 This info is returned in the tables reload_... (see reload.h).
3936 Also modify the body of INSN by substituting RELOAD
3937 rtx's for those pseudo regs. */
3940 memset (reg_has_output_reload
, 0, max_regno
);
3941 CLEAR_HARD_REG_SET (reg_is_output_reload
);
3943 find_reloads (insn
, 1, spill_indirect_levels
, live_known
,
3949 rtx next
= NEXT_INSN (insn
);
3952 prev
= PREV_INSN (insn
);
3954 /* Now compute which reload regs to reload them into. Perhaps
3955 reusing reload regs from previous insns, or else output
3956 load insns to reload them. Maybe output store insns too.
3957 Record the choices of reload reg in reload_reg_rtx. */
3958 choose_reload_regs (chain
);
3960 /* Merge any reloads that we didn't combine for fear of
3961 increasing the number of spill registers needed but now
3962 discover can be safely merged. */
3963 if (SMALL_REGISTER_CLASSES
)
3964 merge_assigned_reloads (insn
);
3966 /* Generate the insns to reload operands into or out of
3967 their reload regs. */
3968 emit_reload_insns (chain
);
3970 /* Substitute the chosen reload regs from reload_reg_rtx
3971 into the insn's body (or perhaps into the bodies of other
3972 load and store insn that we just made for reloading
3973 and that we moved the structure into). */
3974 subst_reloads (insn
);
3976 /* Adjust the exception region notes for loads and stores. */
3977 if (flag_non_call_exceptions
&& !CALL_P (insn
))
3978 fixup_eh_region_note (insn
, prev
, next
);
3980 /* If this was an ASM, make sure that all the reload insns
3981 we have generated are valid. If not, give an error
3983 if (asm_noperands (PATTERN (insn
)) >= 0)
3984 for (p
= NEXT_INSN (prev
); p
!= next
; p
= NEXT_INSN (p
))
3985 if (p
!= insn
&& INSN_P (p
)
3986 && GET_CODE (PATTERN (p
)) != USE
3987 && (recog_memoized (p
) < 0
3988 || (extract_insn (p
), ! constrain_operands (1))))
3990 error_for_asm (insn
,
3991 "%<asm%> operand requires "
3992 "impossible reload");
3997 if (num_eliminable
&& chain
->need_elim
)
3998 update_eliminable_offsets ();
4000 /* Any previously reloaded spilled pseudo reg, stored in this insn,
4001 is no longer validly lying around to save a future reload.
4002 Note that this does not detect pseudos that were reloaded
4003 for this insn in order to be stored in
4004 (obeying register constraints). That is correct; such reload
4005 registers ARE still valid. */
4006 note_stores (oldpat
, forget_old_reloads_1
, NULL
);
4008 /* There may have been CLOBBER insns placed after INSN. So scan
4009 between INSN and NEXT and use them to forget old reloads. */
4010 for (x
= NEXT_INSN (insn
); x
!= old_next
; x
= NEXT_INSN (x
))
4011 if (NONJUMP_INSN_P (x
) && GET_CODE (PATTERN (x
)) == CLOBBER
)
4012 note_stores (PATTERN (x
), forget_old_reloads_1
, NULL
);
4015 /* Likewise for regs altered by auto-increment in this insn.
4016 REG_INC notes have been changed by reloading:
4017 find_reloads_address_1 records substitutions for them,
4018 which have been performed by subst_reloads above. */
4019 for (i
= n_reloads
- 1; i
>= 0; i
--)
4021 rtx in_reg
= rld
[i
].in_reg
;
4024 enum rtx_code code
= GET_CODE (in_reg
);
4025 /* PRE_INC / PRE_DEC will have the reload register ending up
4026 with the same value as the stack slot, but that doesn't
4027 hold true for POST_INC / POST_DEC. Either we have to
4028 convert the memory access to a true POST_INC / POST_DEC,
4029 or we can't use the reload register for inheritance. */
4030 if ((code
== POST_INC
|| code
== POST_DEC
)
4031 && TEST_HARD_REG_BIT (reg_reloaded_valid
,
4032 REGNO (rld
[i
].reg_rtx
))
4033 /* Make sure it is the inc/dec pseudo, and not
4034 some other (e.g. output operand) pseudo. */
4035 && ((unsigned) reg_reloaded_contents
[REGNO (rld
[i
].reg_rtx
)]
4036 == REGNO (XEXP (in_reg
, 0))))
4039 rtx reload_reg
= rld
[i
].reg_rtx
;
4040 enum machine_mode mode
= GET_MODE (reload_reg
);
4044 for (p
= PREV_INSN (old_next
); p
!= prev
; p
= PREV_INSN (p
))
4046 /* We really want to ignore REG_INC notes here, so
4047 use PATTERN (p) as argument to reg_set_p . */
4048 if (reg_set_p (reload_reg
, PATTERN (p
)))
4050 n
= count_occurrences (PATTERN (p
), reload_reg
, 0);
4055 n
= validate_replace_rtx (reload_reg
,
4056 gen_rtx_fmt_e (code
,
4061 /* We must also verify that the constraints
4062 are met after the replacement. */
4065 n
= constrain_operands (1);
4069 /* If the constraints were not met, then
4070 undo the replacement. */
4073 validate_replace_rtx (gen_rtx_fmt_e (code
,
4086 = gen_rtx_EXPR_LIST (REG_INC
, reload_reg
,
4088 /* Mark this as having an output reload so that the
4089 REG_INC processing code below won't invalidate
4090 the reload for inheritance. */
4091 SET_HARD_REG_BIT (reg_is_output_reload
,
4092 REGNO (reload_reg
));
4093 reg_has_output_reload
[REGNO (XEXP (in_reg
, 0))] = 1;
4096 forget_old_reloads_1 (XEXP (in_reg
, 0), NULL_RTX
,
4099 else if ((code
== PRE_INC
|| code
== PRE_DEC
)
4100 && TEST_HARD_REG_BIT (reg_reloaded_valid
,
4101 REGNO (rld
[i
].reg_rtx
))
4102 /* Make sure it is the inc/dec pseudo, and not
4103 some other (e.g. output operand) pseudo. */
4104 && ((unsigned) reg_reloaded_contents
[REGNO (rld
[i
].reg_rtx
)]
4105 == REGNO (XEXP (in_reg
, 0))))
4107 SET_HARD_REG_BIT (reg_is_output_reload
,
4108 REGNO (rld
[i
].reg_rtx
));
4109 reg_has_output_reload
[REGNO (XEXP (in_reg
, 0))] = 1;
4113 /* If a pseudo that got a hard register is auto-incremented,
4114 we must purge records of copying it into pseudos without
4116 for (x
= REG_NOTES (insn
); x
; x
= XEXP (x
, 1))
4117 if (REG_NOTE_KIND (x
) == REG_INC
)
4119 /* See if this pseudo reg was reloaded in this insn.
4120 If so, its last-reload info is still valid
4121 because it is based on this insn's reload. */
4122 for (i
= 0; i
< n_reloads
; i
++)
4123 if (rld
[i
].out
== XEXP (x
, 0))
4127 forget_old_reloads_1 (XEXP (x
, 0), NULL_RTX
, NULL
);
4131 /* A reload reg's contents are unknown after a label. */
4133 CLEAR_HARD_REG_SET (reg_reloaded_valid
);
4135 /* Don't assume a reload reg is still good after a call insn
4136 if it is a call-used reg, or if it contains a value that will
4137 be partially clobbered by the call. */
4138 else if (CALL_P (insn
))
4140 AND_COMPL_HARD_REG_SET (reg_reloaded_valid
, call_used_reg_set
);
4141 AND_COMPL_HARD_REG_SET (reg_reloaded_valid
, reg_reloaded_call_part_clobbered
);
4146 free (reg_last_reload_reg
);
4147 free (reg_has_output_reload
);
4150 /* Discard all record of any value reloaded from X,
4151 or reloaded in X from someplace else;
4152 unless X is an output reload reg of the current insn.
4154 X may be a hard reg (the reload reg)
4155 or it may be a pseudo reg that was reloaded from. */
4158 forget_old_reloads_1 (rtx x
, rtx ignored ATTRIBUTE_UNUSED
,
4159 void *data ATTRIBUTE_UNUSED
)
4164 /* note_stores does give us subregs of hard regs,
4165 subreg_regno_offset requires a hard reg. */
4166 while (GET_CODE (x
) == SUBREG
)
4168 /* We ignore the subreg offset when calculating the regno,
4169 because we are using the entire underlying hard register
4179 if (regno
>= FIRST_PSEUDO_REGISTER
)
4185 nr
= hard_regno_nregs
[regno
][GET_MODE (x
)];
4186 /* Storing into a spilled-reg invalidates its contents.
4187 This can happen if a block-local pseudo is allocated to that reg
4188 and it wasn't spilled because this block's total need is 0.
4189 Then some insn might have an optional reload and use this reg. */
4190 for (i
= 0; i
< nr
; i
++)
4191 /* But don't do this if the reg actually serves as an output
4192 reload reg in the current instruction. */
4194 || ! TEST_HARD_REG_BIT (reg_is_output_reload
, regno
+ i
))
4196 CLEAR_HARD_REG_BIT (reg_reloaded_valid
, regno
+ i
);
4197 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered
, regno
+ i
);
4198 spill_reg_store
[regno
+ i
] = 0;
4202 /* Since value of X has changed,
4203 forget any value previously copied from it. */
4206 /* But don't forget a copy if this is the output reload
4207 that establishes the copy's validity. */
4208 if (n_reloads
== 0 || reg_has_output_reload
[regno
+ nr
] == 0)
4209 reg_last_reload_reg
[regno
+ nr
] = 0;
4212 /* The following HARD_REG_SETs indicate when each hard register is
4213 used for a reload of various parts of the current insn. */
4215 /* If reg is unavailable for all reloads. */
4216 static HARD_REG_SET reload_reg_unavailable
;
4217 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
4218 static HARD_REG_SET reload_reg_used
;
4219 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
4220 static HARD_REG_SET reload_reg_used_in_input_addr
[MAX_RECOG_OPERANDS
];
4221 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */
4222 static HARD_REG_SET reload_reg_used_in_inpaddr_addr
[MAX_RECOG_OPERANDS
];
4223 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
4224 static HARD_REG_SET reload_reg_used_in_output_addr
[MAX_RECOG_OPERANDS
];
4225 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */
4226 static HARD_REG_SET reload_reg_used_in_outaddr_addr
[MAX_RECOG_OPERANDS
];
4227 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
4228 static HARD_REG_SET reload_reg_used_in_input
[MAX_RECOG_OPERANDS
];
4229 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
4230 static HARD_REG_SET reload_reg_used_in_output
[MAX_RECOG_OPERANDS
];
4231 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
4232 static HARD_REG_SET reload_reg_used_in_op_addr
;
4233 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */
4234 static HARD_REG_SET reload_reg_used_in_op_addr_reload
;
4235 /* If reg is in use for a RELOAD_FOR_INSN reload. */
4236 static HARD_REG_SET reload_reg_used_in_insn
;
4237 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
4238 static HARD_REG_SET reload_reg_used_in_other_addr
;
4240 /* If reg is in use as a reload reg for any sort of reload. */
4241 static HARD_REG_SET reload_reg_used_at_all
;
4243 /* If reg is use as an inherited reload. We just mark the first register
4245 static HARD_REG_SET reload_reg_used_for_inherit
;
4247 /* Records which hard regs are used in any way, either as explicit use or
4248 by being allocated to a pseudo during any point of the current insn. */
4249 static HARD_REG_SET reg_used_in_insn
;
4251 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
4252 TYPE. MODE is used to indicate how many consecutive regs are
4256 mark_reload_reg_in_use (unsigned int regno
, int opnum
, enum reload_type type
,
4257 enum machine_mode mode
)
4259 unsigned int nregs
= hard_regno_nregs
[regno
][mode
];
4262 for (i
= regno
; i
< nregs
+ regno
; i
++)
4267 SET_HARD_REG_BIT (reload_reg_used
, i
);
4270 case RELOAD_FOR_INPUT_ADDRESS
:
4271 SET_HARD_REG_BIT (reload_reg_used_in_input_addr
[opnum
], i
);
4274 case RELOAD_FOR_INPADDR_ADDRESS
:
4275 SET_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[opnum
], i
);
4278 case RELOAD_FOR_OUTPUT_ADDRESS
:
4279 SET_HARD_REG_BIT (reload_reg_used_in_output_addr
[opnum
], i
);
4282 case RELOAD_FOR_OUTADDR_ADDRESS
:
4283 SET_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[opnum
], i
);
4286 case RELOAD_FOR_OPERAND_ADDRESS
:
4287 SET_HARD_REG_BIT (reload_reg_used_in_op_addr
, i
);
4290 case RELOAD_FOR_OPADDR_ADDR
:
4291 SET_HARD_REG_BIT (reload_reg_used_in_op_addr_reload
, i
);
4294 case RELOAD_FOR_OTHER_ADDRESS
:
4295 SET_HARD_REG_BIT (reload_reg_used_in_other_addr
, i
);
4298 case RELOAD_FOR_INPUT
:
4299 SET_HARD_REG_BIT (reload_reg_used_in_input
[opnum
], i
);
4302 case RELOAD_FOR_OUTPUT
:
4303 SET_HARD_REG_BIT (reload_reg_used_in_output
[opnum
], i
);
4306 case RELOAD_FOR_INSN
:
4307 SET_HARD_REG_BIT (reload_reg_used_in_insn
, i
);
4311 SET_HARD_REG_BIT (reload_reg_used_at_all
, i
);
4315 /* Similarly, but show REGNO is no longer in use for a reload. */
4318 clear_reload_reg_in_use (unsigned int regno
, int opnum
,
4319 enum reload_type type
, enum machine_mode mode
)
4321 unsigned int nregs
= hard_regno_nregs
[regno
][mode
];
4322 unsigned int start_regno
, end_regno
, r
;
4324 /* A complication is that for some reload types, inheritance might
4325 allow multiple reloads of the same types to share a reload register.
4326 We set check_opnum if we have to check only reloads with the same
4327 operand number, and check_any if we have to check all reloads. */
4328 int check_opnum
= 0;
4330 HARD_REG_SET
*used_in_set
;
4335 used_in_set
= &reload_reg_used
;
4338 case RELOAD_FOR_INPUT_ADDRESS
:
4339 used_in_set
= &reload_reg_used_in_input_addr
[opnum
];
4342 case RELOAD_FOR_INPADDR_ADDRESS
:
4344 used_in_set
= &reload_reg_used_in_inpaddr_addr
[opnum
];
4347 case RELOAD_FOR_OUTPUT_ADDRESS
:
4348 used_in_set
= &reload_reg_used_in_output_addr
[opnum
];
4351 case RELOAD_FOR_OUTADDR_ADDRESS
:
4353 used_in_set
= &reload_reg_used_in_outaddr_addr
[opnum
];
4356 case RELOAD_FOR_OPERAND_ADDRESS
:
4357 used_in_set
= &reload_reg_used_in_op_addr
;
4360 case RELOAD_FOR_OPADDR_ADDR
:
4362 used_in_set
= &reload_reg_used_in_op_addr_reload
;
4365 case RELOAD_FOR_OTHER_ADDRESS
:
4366 used_in_set
= &reload_reg_used_in_other_addr
;
4370 case RELOAD_FOR_INPUT
:
4371 used_in_set
= &reload_reg_used_in_input
[opnum
];
4374 case RELOAD_FOR_OUTPUT
:
4375 used_in_set
= &reload_reg_used_in_output
[opnum
];
4378 case RELOAD_FOR_INSN
:
4379 used_in_set
= &reload_reg_used_in_insn
;
4384 /* We resolve conflicts with remaining reloads of the same type by
4385 excluding the intervals of reload registers by them from the
4386 interval of freed reload registers. Since we only keep track of
4387 one set of interval bounds, we might have to exclude somewhat
4388 more than what would be necessary if we used a HARD_REG_SET here.
4389 But this should only happen very infrequently, so there should
4390 be no reason to worry about it. */
4392 start_regno
= regno
;
4393 end_regno
= regno
+ nregs
;
4394 if (check_opnum
|| check_any
)
4396 for (i
= n_reloads
- 1; i
>= 0; i
--)
4398 if (rld
[i
].when_needed
== type
4399 && (check_any
|| rld
[i
].opnum
== opnum
)
4402 unsigned int conflict_start
= true_regnum (rld
[i
].reg_rtx
);
4403 unsigned int conflict_end
4405 + hard_regno_nregs
[conflict_start
][rld
[i
].mode
]);
4407 /* If there is an overlap with the first to-be-freed register,
4408 adjust the interval start. */
4409 if (conflict_start
<= start_regno
&& conflict_end
> start_regno
)
4410 start_regno
= conflict_end
;
4411 /* Otherwise, if there is a conflict with one of the other
4412 to-be-freed registers, adjust the interval end. */
4413 if (conflict_start
> start_regno
&& conflict_start
< end_regno
)
4414 end_regno
= conflict_start
;
4419 for (r
= start_regno
; r
< end_regno
; r
++)
4420 CLEAR_HARD_REG_BIT (*used_in_set
, r
);
4423 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
4424 specified by OPNUM and TYPE. */
4427 reload_reg_free_p (unsigned int regno
, int opnum
, enum reload_type type
)
4431 /* In use for a RELOAD_OTHER means it's not available for anything. */
4432 if (TEST_HARD_REG_BIT (reload_reg_used
, regno
)
4433 || TEST_HARD_REG_BIT (reload_reg_unavailable
, regno
))
4439 /* In use for anything means we can't use it for RELOAD_OTHER. */
4440 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr
, regno
)
4441 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
)
4442 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload
, regno
)
4443 || TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
))
4446 for (i
= 0; i
< reload_n_operands
; i
++)
4447 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
4448 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
)
4449 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
4450 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
)
4451 || TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
)
4452 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
4457 case RELOAD_FOR_INPUT
:
4458 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
4459 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
))
4462 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload
, regno
))
4465 /* If it is used for some other input, can't use it. */
4466 for (i
= 0; i
< reload_n_operands
; i
++)
4467 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
4470 /* If it is used in a later operand's address, can't use it. */
4471 for (i
= opnum
+ 1; i
< reload_n_operands
; i
++)
4472 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
4473 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
))
4478 case RELOAD_FOR_INPUT_ADDRESS
:
4479 /* Can't use a register if it is used for an input address for this
4480 operand or used as an input in an earlier one. */
4481 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[opnum
], regno
)
4482 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[opnum
], regno
))
4485 for (i
= 0; i
< opnum
; i
++)
4486 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
4491 case RELOAD_FOR_INPADDR_ADDRESS
:
4492 /* Can't use a register if it is used for an input address
4493 for this operand or used as an input in an earlier
4495 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[opnum
], regno
))
4498 for (i
= 0; i
< opnum
; i
++)
4499 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
4504 case RELOAD_FOR_OUTPUT_ADDRESS
:
4505 /* Can't use a register if it is used for an output address for this
4506 operand or used as an output in this or a later operand. Note
4507 that multiple output operands are emitted in reverse order, so
4508 the conflicting ones are those with lower indices. */
4509 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[opnum
], regno
))
4512 for (i
= 0; i
<= opnum
; i
++)
4513 if (TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
4518 case RELOAD_FOR_OUTADDR_ADDRESS
:
4519 /* Can't use a register if it is used for an output address
4520 for this operand or used as an output in this or a
4521 later operand. Note that multiple output operands are
4522 emitted in reverse order, so the conflicting ones are
4523 those with lower indices. */
4524 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[opnum
], regno
))
4527 for (i
= 0; i
<= opnum
; i
++)
4528 if (TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
4533 case RELOAD_FOR_OPERAND_ADDRESS
:
4534 for (i
= 0; i
< reload_n_operands
; i
++)
4535 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
4538 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
4539 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
));
4541 case RELOAD_FOR_OPADDR_ADDR
:
4542 for (i
= 0; i
< reload_n_operands
; i
++)
4543 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
4546 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload
, regno
));
4548 case RELOAD_FOR_OUTPUT
:
4549 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
4550 outputs, or an operand address for this or an earlier output.
4551 Note that multiple output operands are emitted in reverse order,
4552 so the conflicting ones are those with higher indices. */
4553 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
))
4556 for (i
= 0; i
< reload_n_operands
; i
++)
4557 if (TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
4560 for (i
= opnum
; i
< reload_n_operands
; i
++)
4561 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
4562 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
))
4567 case RELOAD_FOR_INSN
:
4568 for (i
= 0; i
< reload_n_operands
; i
++)
4569 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
)
4570 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
4573 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
4574 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
));
4576 case RELOAD_FOR_OTHER_ADDRESS
:
4577 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr
, regno
);
4584 /* Return 1 if the value in reload reg REGNO, as used by a reload
4585 needed for the part of the insn specified by OPNUM and TYPE,
4586 is still available in REGNO at the end of the insn.
4588 We can assume that the reload reg was already tested for availability
4589 at the time it is needed, and we should not check this again,
4590 in case the reg has already been marked in use. */
4593 reload_reg_reaches_end_p (unsigned int regno
, int opnum
, enum reload_type type
)
4600 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
4601 its value must reach the end. */
4604 /* If this use is for part of the insn,
4605 its value reaches if no subsequent part uses the same register.
4606 Just like the above function, don't try to do this with lots
4609 case RELOAD_FOR_OTHER_ADDRESS
:
4610 /* Here we check for everything else, since these don't conflict
4611 with anything else and everything comes later. */
4613 for (i
= 0; i
< reload_n_operands
; i
++)
4614 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
4615 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
)
4616 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
)
4617 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
4618 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
)
4619 || TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
4622 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
)
4623 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload
, regno
)
4624 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
4625 && ! TEST_HARD_REG_BIT (reload_reg_used
, regno
));
4627 case RELOAD_FOR_INPUT_ADDRESS
:
4628 case RELOAD_FOR_INPADDR_ADDRESS
:
4629 /* Similar, except that we check only for this and subsequent inputs
4630 and the address of only subsequent inputs and we do not need
4631 to check for RELOAD_OTHER objects since they are known not to
4634 for (i
= opnum
; i
< reload_n_operands
; i
++)
4635 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
4638 for (i
= opnum
+ 1; i
< reload_n_operands
; i
++)
4639 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
4640 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
))
4643 for (i
= 0; i
< reload_n_operands
; i
++)
4644 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
4645 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
)
4646 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
4649 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload
, regno
))
4652 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
)
4653 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
4654 && !TEST_HARD_REG_BIT (reload_reg_used
, regno
));
4656 case RELOAD_FOR_INPUT
:
4657 /* Similar to input address, except we start at the next operand for
4658 both input and input address and we do not check for
4659 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
4662 for (i
= opnum
+ 1; i
< reload_n_operands
; i
++)
4663 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
4664 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
)
4665 || TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
4668 /* ... fall through ... */
4670 case RELOAD_FOR_OPERAND_ADDRESS
:
4671 /* Check outputs and their addresses. */
4673 for (i
= 0; i
< reload_n_operands
; i
++)
4674 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
4675 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
)
4676 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
4679 return (!TEST_HARD_REG_BIT (reload_reg_used
, regno
));
4681 case RELOAD_FOR_OPADDR_ADDR
:
4682 for (i
= 0; i
< reload_n_operands
; i
++)
4683 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
4684 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
)
4685 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
4688 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
)
4689 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
4690 && !TEST_HARD_REG_BIT (reload_reg_used
, regno
));
4692 case RELOAD_FOR_INSN
:
4693 /* These conflict with other outputs with RELOAD_OTHER. So
4694 we need only check for output addresses. */
4696 opnum
= reload_n_operands
;
4698 /* ... fall through ... */
4700 case RELOAD_FOR_OUTPUT
:
4701 case RELOAD_FOR_OUTPUT_ADDRESS
:
4702 case RELOAD_FOR_OUTADDR_ADDRESS
:
4703 /* We already know these can't conflict with a later output. So the
4704 only thing to check are later output addresses.
4705 Note that multiple output operands are emitted in reverse order,
4706 so the conflicting ones are those with lower indices. */
4707 for (i
= 0; i
< opnum
; i
++)
4708 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
4709 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
))
4719 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
4722 This function uses the same algorithm as reload_reg_free_p above. */
4725 reloads_conflict (int r1
, int r2
)
4727 enum reload_type r1_type
= rld
[r1
].when_needed
;
4728 enum reload_type r2_type
= rld
[r2
].when_needed
;
4729 int r1_opnum
= rld
[r1
].opnum
;
4730 int r2_opnum
= rld
[r2
].opnum
;
4732 /* RELOAD_OTHER conflicts with everything. */
4733 if (r2_type
== RELOAD_OTHER
)
4736 /* Otherwise, check conflicts differently for each type. */
4740 case RELOAD_FOR_INPUT
:
4741 return (r2_type
== RELOAD_FOR_INSN
4742 || r2_type
== RELOAD_FOR_OPERAND_ADDRESS
4743 || r2_type
== RELOAD_FOR_OPADDR_ADDR
4744 || r2_type
== RELOAD_FOR_INPUT
4745 || ((r2_type
== RELOAD_FOR_INPUT_ADDRESS
4746 || r2_type
== RELOAD_FOR_INPADDR_ADDRESS
)
4747 && r2_opnum
> r1_opnum
));
4749 case RELOAD_FOR_INPUT_ADDRESS
:
4750 return ((r2_type
== RELOAD_FOR_INPUT_ADDRESS
&& r1_opnum
== r2_opnum
)
4751 || (r2_type
== RELOAD_FOR_INPUT
&& r2_opnum
< r1_opnum
));
4753 case RELOAD_FOR_INPADDR_ADDRESS
:
4754 return ((r2_type
== RELOAD_FOR_INPADDR_ADDRESS
&& r1_opnum
== r2_opnum
)
4755 || (r2_type
== RELOAD_FOR_INPUT
&& r2_opnum
< r1_opnum
));
4757 case RELOAD_FOR_OUTPUT_ADDRESS
:
4758 return ((r2_type
== RELOAD_FOR_OUTPUT_ADDRESS
&& r2_opnum
== r1_opnum
)
4759 || (r2_type
== RELOAD_FOR_OUTPUT
&& r2_opnum
<= r1_opnum
));
4761 case RELOAD_FOR_OUTADDR_ADDRESS
:
4762 return ((r2_type
== RELOAD_FOR_OUTADDR_ADDRESS
&& r2_opnum
== r1_opnum
)
4763 || (r2_type
== RELOAD_FOR_OUTPUT
&& r2_opnum
<= r1_opnum
));
4765 case RELOAD_FOR_OPERAND_ADDRESS
:
4766 return (r2_type
== RELOAD_FOR_INPUT
|| r2_type
== RELOAD_FOR_INSN
4767 || r2_type
== RELOAD_FOR_OPERAND_ADDRESS
);
4769 case RELOAD_FOR_OPADDR_ADDR
:
4770 return (r2_type
== RELOAD_FOR_INPUT
4771 || r2_type
== RELOAD_FOR_OPADDR_ADDR
);
4773 case RELOAD_FOR_OUTPUT
:
4774 return (r2_type
== RELOAD_FOR_INSN
|| r2_type
== RELOAD_FOR_OUTPUT
4775 || ((r2_type
== RELOAD_FOR_OUTPUT_ADDRESS
4776 || r2_type
== RELOAD_FOR_OUTADDR_ADDRESS
)
4777 && r2_opnum
>= r1_opnum
));
4779 case RELOAD_FOR_INSN
:
4780 return (r2_type
== RELOAD_FOR_INPUT
|| r2_type
== RELOAD_FOR_OUTPUT
4781 || r2_type
== RELOAD_FOR_INSN
4782 || r2_type
== RELOAD_FOR_OPERAND_ADDRESS
);
4784 case RELOAD_FOR_OTHER_ADDRESS
:
4785 return r2_type
== RELOAD_FOR_OTHER_ADDRESS
;
4795 /* Indexed by reload number, 1 if incoming value
4796 inherited from previous insns. */
4797 static char reload_inherited
[MAX_RELOADS
];
4799 /* For an inherited reload, this is the insn the reload was inherited from,
4800 if we know it. Otherwise, this is 0. */
4801 static rtx reload_inheritance_insn
[MAX_RELOADS
];
4803 /* If nonzero, this is a place to get the value of the reload,
4804 rather than using reload_in. */
4805 static rtx reload_override_in
[MAX_RELOADS
];
4807 /* For each reload, the hard register number of the register used,
4808 or -1 if we did not need a register for this reload. */
4809 static int reload_spill_index
[MAX_RELOADS
];
4811 /* Subroutine of free_for_value_p, used to check a single register.
4812 START_REGNO is the starting regno of the full reload register
4813 (possibly comprising multiple hard registers) that we are considering. */
4816 reload_reg_free_for_value_p (int start_regno
, int regno
, int opnum
,
4817 enum reload_type type
, rtx value
, rtx out
,
4818 int reloadnum
, int ignore_address_reloads
)
4821 /* Set if we see an input reload that must not share its reload register
4822 with any new earlyclobber, but might otherwise share the reload
4823 register with an output or input-output reload. */
4824 int check_earlyclobber
= 0;
4828 if (TEST_HARD_REG_BIT (reload_reg_unavailable
, regno
))
4831 if (out
== const0_rtx
)
4837 /* We use some pseudo 'time' value to check if the lifetimes of the
4838 new register use would overlap with the one of a previous reload
4839 that is not read-only or uses a different value.
4840 The 'time' used doesn't have to be linear in any shape or form, just
4842 Some reload types use different 'buckets' for each operand.
4843 So there are MAX_RECOG_OPERANDS different time values for each
4845 We compute TIME1 as the time when the register for the prospective
4846 new reload ceases to be live, and TIME2 for each existing
4847 reload as the time when that the reload register of that reload
4849 Where there is little to be gained by exact lifetime calculations,
4850 we just make conservative assumptions, i.e. a longer lifetime;
4851 this is done in the 'default:' cases. */
4854 case RELOAD_FOR_OTHER_ADDRESS
:
4855 /* RELOAD_FOR_OTHER_ADDRESS conflicts with RELOAD_OTHER reloads. */
4856 time1
= copy
? 0 : 1;
4859 time1
= copy
? 1 : MAX_RECOG_OPERANDS
* 5 + 5;
4861 /* For each input, we may have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
4862 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 ,
4863 respectively, to the time values for these, we get distinct time
4864 values. To get distinct time values for each operand, we have to
4865 multiply opnum by at least three. We round that up to four because
4866 multiply by four is often cheaper. */
4867 case RELOAD_FOR_INPADDR_ADDRESS
:
4868 time1
= opnum
* 4 + 2;
4870 case RELOAD_FOR_INPUT_ADDRESS
:
4871 time1
= opnum
* 4 + 3;
4873 case RELOAD_FOR_INPUT
:
4874 /* All RELOAD_FOR_INPUT reloads remain live till the instruction
4875 executes (inclusive). */
4876 time1
= copy
? opnum
* 4 + 4 : MAX_RECOG_OPERANDS
* 4 + 3;
4878 case RELOAD_FOR_OPADDR_ADDR
:
4880 <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
4881 time1
= MAX_RECOG_OPERANDS
* 4 + 1;
4883 case RELOAD_FOR_OPERAND_ADDRESS
:
4884 /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn
4886 time1
= copy
? MAX_RECOG_OPERANDS
* 4 + 2 : MAX_RECOG_OPERANDS
* 4 + 3;
4888 case RELOAD_FOR_OUTADDR_ADDRESS
:
4889 time1
= MAX_RECOG_OPERANDS
* 4 + 4 + opnum
;
4891 case RELOAD_FOR_OUTPUT_ADDRESS
:
4892 time1
= MAX_RECOG_OPERANDS
* 4 + 5 + opnum
;
4895 time1
= MAX_RECOG_OPERANDS
* 5 + 5;
4898 for (i
= 0; i
< n_reloads
; i
++)
4900 rtx reg
= rld
[i
].reg_rtx
;
4901 if (reg
&& REG_P (reg
)
4902 && ((unsigned) regno
- true_regnum (reg
)
4903 <= hard_regno_nregs
[REGNO (reg
)][GET_MODE (reg
)] - (unsigned) 1)
4906 rtx other_input
= rld
[i
].in
;
4908 /* If the other reload loads the same input value, that
4909 will not cause a conflict only if it's loading it into
4910 the same register. */
4911 if (true_regnum (reg
) != start_regno
)
4912 other_input
= NULL_RTX
;
4913 if (! other_input
|| ! rtx_equal_p (other_input
, value
)
4914 || rld
[i
].out
|| out
)
4917 switch (rld
[i
].when_needed
)
4919 case RELOAD_FOR_OTHER_ADDRESS
:
4922 case RELOAD_FOR_INPADDR_ADDRESS
:
4923 /* find_reloads makes sure that a
4924 RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used
4925 by at most one - the first -
4926 RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the
4927 address reload is inherited, the address address reload
4928 goes away, so we can ignore this conflict. */
4929 if (type
== RELOAD_FOR_INPUT_ADDRESS
&& reloadnum
== i
+ 1
4930 && ignore_address_reloads
4931 /* Unless the RELOAD_FOR_INPUT is an auto_inc expression.
4932 Then the address address is still needed to store
4933 back the new address. */
4934 && ! rld
[reloadnum
].out
)
4936 /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its
4937 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS
4939 if (type
== RELOAD_FOR_INPUT
&& opnum
== rld
[i
].opnum
4940 && ignore_address_reloads
4941 /* Unless we are reloading an auto_inc expression. */
4942 && ! rld
[reloadnum
].out
)
4944 time2
= rld
[i
].opnum
* 4 + 2;
4946 case RELOAD_FOR_INPUT_ADDRESS
:
4947 if (type
== RELOAD_FOR_INPUT
&& opnum
== rld
[i
].opnum
4948 && ignore_address_reloads
4949 && ! rld
[reloadnum
].out
)
4951 time2
= rld
[i
].opnum
* 4 + 3;
4953 case RELOAD_FOR_INPUT
:
4954 time2
= rld
[i
].opnum
* 4 + 4;
4955 check_earlyclobber
= 1;
4957 /* rld[i].opnum * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4
4958 == MAX_RECOG_OPERAND * 4 */
4959 case RELOAD_FOR_OPADDR_ADDR
:
4960 if (type
== RELOAD_FOR_OPERAND_ADDRESS
&& reloadnum
== i
+ 1
4961 && ignore_address_reloads
4962 && ! rld
[reloadnum
].out
)
4964 time2
= MAX_RECOG_OPERANDS
* 4 + 1;
4966 case RELOAD_FOR_OPERAND_ADDRESS
:
4967 time2
= MAX_RECOG_OPERANDS
* 4 + 2;
4968 check_earlyclobber
= 1;
4970 case RELOAD_FOR_INSN
:
4971 time2
= MAX_RECOG_OPERANDS
* 4 + 3;
4973 case RELOAD_FOR_OUTPUT
:
4974 /* All RELOAD_FOR_OUTPUT reloads become live just after the
4975 instruction is executed. */
4976 time2
= MAX_RECOG_OPERANDS
* 4 + 4;
4978 /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with
4979 the RELOAD_FOR_OUTPUT reloads, so assign it the same time
4981 case RELOAD_FOR_OUTADDR_ADDRESS
:
4982 if (type
== RELOAD_FOR_OUTPUT_ADDRESS
&& reloadnum
== i
+ 1
4983 && ignore_address_reloads
4984 && ! rld
[reloadnum
].out
)
4986 time2
= MAX_RECOG_OPERANDS
* 4 + 4 + rld
[i
].opnum
;
4988 case RELOAD_FOR_OUTPUT_ADDRESS
:
4989 time2
= MAX_RECOG_OPERANDS
* 4 + 5 + rld
[i
].opnum
;
4992 /* If there is no conflict in the input part, handle this
4993 like an output reload. */
4994 if (! rld
[i
].in
|| rtx_equal_p (other_input
, value
))
4996 time2
= MAX_RECOG_OPERANDS
* 4 + 4;
4997 /* Earlyclobbered outputs must conflict with inputs. */
4998 if (earlyclobber_operand_p (rld
[i
].out
))
4999 time2
= MAX_RECOG_OPERANDS
* 4 + 3;
5004 /* RELOAD_OTHER might be live beyond instruction execution,
5005 but this is not obvious when we set time2 = 1. So check
5006 here if there might be a problem with the new reload
5007 clobbering the register used by the RELOAD_OTHER. */
5015 && (! rld
[i
].in
|| rld
[i
].out
5016 || ! rtx_equal_p (other_input
, value
)))
5017 || (out
&& rld
[reloadnum
].out_reg
5018 && time2
>= MAX_RECOG_OPERANDS
* 4 + 3))
5024 /* Earlyclobbered outputs must conflict with inputs. */
5025 if (check_earlyclobber
&& out
&& earlyclobber_operand_p (out
))
5031 /* Return 1 if the value in reload reg REGNO, as used by a reload
5032 needed for the part of the insn specified by OPNUM and TYPE,
5033 may be used to load VALUE into it.
5035 MODE is the mode in which the register is used, this is needed to
5036 determine how many hard regs to test.
5038 Other read-only reloads with the same value do not conflict
5039 unless OUT is nonzero and these other reloads have to live while
5040 output reloads live.
5041 If OUT is CONST0_RTX, this is a special case: it means that the
5042 test should not be for using register REGNO as reload register, but
5043 for copying from register REGNO into the reload register.
5045 RELOADNUM is the number of the reload we want to load this value for;
5046 a reload does not conflict with itself.
5048 When IGNORE_ADDRESS_RELOADS is set, we can not have conflicts with
5049 reloads that load an address for the very reload we are considering.
5051 The caller has to make sure that there is no conflict with the return
5055 free_for_value_p (int regno
, enum machine_mode mode
, int opnum
,
5056 enum reload_type type
, rtx value
, rtx out
, int reloadnum
,
5057 int ignore_address_reloads
)
5059 int nregs
= hard_regno_nregs
[regno
][mode
];
5061 if (! reload_reg_free_for_value_p (regno
, regno
+ nregs
, opnum
, type
,
5062 value
, out
, reloadnum
,
5063 ignore_address_reloads
))
5068 /* Return nonzero if the rtx X is invariant over the current function. */
5069 /* ??? Actually, the places where we use this expect exactly what is
5070 tested here, and not everything that is function invariant. In
5071 particular, the frame pointer and arg pointer are special cased;
5072 pic_offset_table_rtx is not, and we must not spill these things to
5076 function_invariant_p (rtx x
)
5080 if (x
== frame_pointer_rtx
|| x
== arg_pointer_rtx
)
5082 if (GET_CODE (x
) == PLUS
5083 && (XEXP (x
, 0) == frame_pointer_rtx
|| XEXP (x
, 0) == arg_pointer_rtx
)
5084 && CONSTANT_P (XEXP (x
, 1)))
5089 /* Determine whether the reload reg X overlaps any rtx'es used for
5090 overriding inheritance. Return nonzero if so. */
5093 conflicts_with_override (rtx x
)
5096 for (i
= 0; i
< n_reloads
; i
++)
5097 if (reload_override_in
[i
]
5098 && reg_overlap_mentioned_p (x
, reload_override_in
[i
]))
5103 /* Give an error message saying we failed to find a reload for INSN,
5104 and clear out reload R. */
5106 failed_reload (rtx insn
, int r
)
5108 if (asm_noperands (PATTERN (insn
)) < 0)
5109 /* It's the compiler's fault. */
5110 fatal_insn ("could not find a spill register", insn
);
5112 /* It's the user's fault; the operand's mode and constraint
5113 don't match. Disable this reload so we don't crash in final. */
5114 error_for_asm (insn
,
5115 "%<asm%> operand constraint incompatible with operand size");
5119 rld
[r
].optional
= 1;
5120 rld
[r
].secondary_p
= 1;
5123 /* I is the index in SPILL_REG_RTX of the reload register we are to allocate
5124 for reload R. If it's valid, get an rtx for it. Return nonzero if
5127 set_reload_reg (int i
, int r
)
5130 rtx reg
= spill_reg_rtx
[i
];
5132 if (reg
== 0 || GET_MODE (reg
) != rld
[r
].mode
)
5133 spill_reg_rtx
[i
] = reg
5134 = gen_rtx_REG (rld
[r
].mode
, spill_regs
[i
]);
5136 regno
= true_regnum (reg
);
5138 /* Detect when the reload reg can't hold the reload mode.
5139 This used to be one `if', but Sequent compiler can't handle that. */
5140 if (HARD_REGNO_MODE_OK (regno
, rld
[r
].mode
))
5142 enum machine_mode test_mode
= VOIDmode
;
5144 test_mode
= GET_MODE (rld
[r
].in
);
5145 /* If rld[r].in has VOIDmode, it means we will load it
5146 in whatever mode the reload reg has: to wit, rld[r].mode.
5147 We have already tested that for validity. */
5148 /* Aside from that, we need to test that the expressions
5149 to reload from or into have modes which are valid for this
5150 reload register. Otherwise the reload insns would be invalid. */
5151 if (! (rld
[r
].in
!= 0 && test_mode
!= VOIDmode
5152 && ! HARD_REGNO_MODE_OK (regno
, test_mode
)))
5153 if (! (rld
[r
].out
!= 0
5154 && ! HARD_REGNO_MODE_OK (regno
, GET_MODE (rld
[r
].out
))))
5156 /* The reg is OK. */
5159 /* Mark as in use for this insn the reload regs we use
5161 mark_reload_reg_in_use (spill_regs
[i
], rld
[r
].opnum
,
5162 rld
[r
].when_needed
, rld
[r
].mode
);
5164 rld
[r
].reg_rtx
= reg
;
5165 reload_spill_index
[r
] = spill_regs
[i
];
5172 /* Find a spill register to use as a reload register for reload R.
5173 LAST_RELOAD is nonzero if this is the last reload for the insn being
5176 Set rld[R].reg_rtx to the register allocated.
5178 We return 1 if successful, or 0 if we couldn't find a spill reg and
5179 we didn't change anything. */
5182 allocate_reload_reg (struct insn_chain
*chain ATTRIBUTE_UNUSED
, int r
,
5187 /* If we put this reload ahead, thinking it is a group,
5188 then insist on finding a group. Otherwise we can grab a
5189 reg that some other reload needs.
5190 (That can happen when we have a 68000 DATA_OR_FP_REG
5191 which is a group of data regs or one fp reg.)
5192 We need not be so restrictive if there are no more reloads
5195 ??? Really it would be nicer to have smarter handling
5196 for that kind of reg class, where a problem like this is normal.
5197 Perhaps those classes should be avoided for reloading
5198 by use of more alternatives. */
5200 int force_group
= rld
[r
].nregs
> 1 && ! last_reload
;
5202 /* If we want a single register and haven't yet found one,
5203 take any reg in the right class and not in use.
5204 If we want a consecutive group, here is where we look for it.
5206 We use two passes so we can first look for reload regs to
5207 reuse, which are already in use for other reloads in this insn,
5208 and only then use additional registers.
5209 I think that maximizing reuse is needed to make sure we don't
5210 run out of reload regs. Suppose we have three reloads, and
5211 reloads A and B can share regs. These need two regs.
5212 Suppose A and B are given different regs.
5213 That leaves none for C. */
5214 for (pass
= 0; pass
< 2; pass
++)
5216 /* I is the index in spill_regs.
5217 We advance it round-robin between insns to use all spill regs
5218 equally, so that inherited reloads have a chance
5219 of leapfrogging each other. */
5223 for (count
= 0; count
< n_spills
; count
++)
5225 int class = (int) rld
[r
].class;
5231 regnum
= spill_regs
[i
];
5233 if ((reload_reg_free_p (regnum
, rld
[r
].opnum
,
5236 /* We check reload_reg_used to make sure we
5237 don't clobber the return register. */
5238 && ! TEST_HARD_REG_BIT (reload_reg_used
, regnum
)
5239 && free_for_value_p (regnum
, rld
[r
].mode
, rld
[r
].opnum
,
5240 rld
[r
].when_needed
, rld
[r
].in
,
5242 && TEST_HARD_REG_BIT (reg_class_contents
[class], regnum
)
5243 && HARD_REGNO_MODE_OK (regnum
, rld
[r
].mode
)
5244 /* Look first for regs to share, then for unshared. But
5245 don't share regs used for inherited reloads; they are
5246 the ones we want to preserve. */
5248 || (TEST_HARD_REG_BIT (reload_reg_used_at_all
,
5250 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit
,
5253 int nr
= hard_regno_nregs
[regnum
][rld
[r
].mode
];
5254 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
5255 (on 68000) got us two FP regs. If NR is 1,
5256 we would reject both of them. */
5259 /* If we need only one reg, we have already won. */
5262 /* But reject a single reg if we demand a group. */
5267 /* Otherwise check that as many consecutive regs as we need
5268 are available here. */
5271 int regno
= regnum
+ nr
- 1;
5272 if (!(TEST_HARD_REG_BIT (reg_class_contents
[class], regno
)
5273 && spill_reg_order
[regno
] >= 0
5274 && reload_reg_free_p (regno
, rld
[r
].opnum
,
5275 rld
[r
].when_needed
)))
5284 /* If we found something on pass 1, omit pass 2. */
5285 if (count
< n_spills
)
5289 /* We should have found a spill register by now. */
5290 if (count
>= n_spills
)
5293 /* I is the index in SPILL_REG_RTX of the reload register we are to
5294 allocate. Get an rtx for it and find its register number. */
5296 return set_reload_reg (i
, r
);
5299 /* Initialize all the tables needed to allocate reload registers.
5300 CHAIN is the insn currently being processed; SAVE_RELOAD_REG_RTX
5301 is the array we use to restore the reg_rtx field for every reload. */
5304 choose_reload_regs_init (struct insn_chain
*chain
, rtx
*save_reload_reg_rtx
)
5308 for (i
= 0; i
< n_reloads
; i
++)
5309 rld
[i
].reg_rtx
= save_reload_reg_rtx
[i
];
5311 memset (reload_inherited
, 0, MAX_RELOADS
);
5312 memset (reload_inheritance_insn
, 0, MAX_RELOADS
* sizeof (rtx
));
5313 memset (reload_override_in
, 0, MAX_RELOADS
* sizeof (rtx
));
5315 CLEAR_HARD_REG_SET (reload_reg_used
);
5316 CLEAR_HARD_REG_SET (reload_reg_used_at_all
);
5317 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr
);
5318 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload
);
5319 CLEAR_HARD_REG_SET (reload_reg_used_in_insn
);
5320 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr
);
5322 CLEAR_HARD_REG_SET (reg_used_in_insn
);
5325 REG_SET_TO_HARD_REG_SET (tmp
, &chain
->live_throughout
);
5326 IOR_HARD_REG_SET (reg_used_in_insn
, tmp
);
5327 REG_SET_TO_HARD_REG_SET (tmp
, &chain
->dead_or_set
);
5328 IOR_HARD_REG_SET (reg_used_in_insn
, tmp
);
5329 compute_use_by_pseudos (®_used_in_insn
, &chain
->live_throughout
);
5330 compute_use_by_pseudos (®_used_in_insn
, &chain
->dead_or_set
);
5333 for (i
= 0; i
< reload_n_operands
; i
++)
5335 CLEAR_HARD_REG_SET (reload_reg_used_in_output
[i
]);
5336 CLEAR_HARD_REG_SET (reload_reg_used_in_input
[i
]);
5337 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr
[i
]);
5338 CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr
[i
]);
5339 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr
[i
]);
5340 CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr
[i
]);
5343 COMPL_HARD_REG_SET (reload_reg_unavailable
, chain
->used_spill_regs
);
5345 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit
);
5347 for (i
= 0; i
< n_reloads
; i
++)
5348 /* If we have already decided to use a certain register,
5349 don't use it in another way. */
5351 mark_reload_reg_in_use (REGNO (rld
[i
].reg_rtx
), rld
[i
].opnum
,
5352 rld
[i
].when_needed
, rld
[i
].mode
);
5355 /* Assign hard reg targets for the pseudo-registers we must reload
5356 into hard regs for this insn.
5357 Also output the instructions to copy them in and out of the hard regs.
5359 For machines with register classes, we are responsible for
5360 finding a reload reg in the proper class. */
5363 choose_reload_regs (struct insn_chain
*chain
)
5365 rtx insn
= chain
->insn
;
5367 unsigned int max_group_size
= 1;
5368 enum reg_class group_class
= NO_REGS
;
5369 int pass
, win
, inheritance
;
5371 rtx save_reload_reg_rtx
[MAX_RELOADS
];
5373 /* In order to be certain of getting the registers we need,
5374 we must sort the reloads into order of increasing register class.
5375 Then our grabbing of reload registers will parallel the process
5376 that provided the reload registers.
5378 Also note whether any of the reloads wants a consecutive group of regs.
5379 If so, record the maximum size of the group desired and what
5380 register class contains all the groups needed by this insn. */
5382 for (j
= 0; j
< n_reloads
; j
++)
5384 reload_order
[j
] = j
;
5385 reload_spill_index
[j
] = -1;
5387 if (rld
[j
].nregs
> 1)
5389 max_group_size
= MAX (rld
[j
].nregs
, max_group_size
);
5391 = reg_class_superunion
[(int) rld
[j
].class][(int) group_class
];
5394 save_reload_reg_rtx
[j
] = rld
[j
].reg_rtx
;
5398 qsort (reload_order
, n_reloads
, sizeof (short), reload_reg_class_lower
);
5400 /* If -O, try first with inheritance, then turning it off.
5401 If not -O, don't do inheritance.
5402 Using inheritance when not optimizing leads to paradoxes
5403 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
5404 because one side of the comparison might be inherited. */
5406 for (inheritance
= optimize
> 0; inheritance
>= 0; inheritance
--)
5408 choose_reload_regs_init (chain
, save_reload_reg_rtx
);
5410 /* Process the reloads in order of preference just found.
5411 Beyond this point, subregs can be found in reload_reg_rtx.
5413 This used to look for an existing reloaded home for all of the
5414 reloads, and only then perform any new reloads. But that could lose
5415 if the reloads were done out of reg-class order because a later
5416 reload with a looser constraint might have an old home in a register
5417 needed by an earlier reload with a tighter constraint.
5419 To solve this, we make two passes over the reloads, in the order
5420 described above. In the first pass we try to inherit a reload
5421 from a previous insn. If there is a later reload that needs a
5422 class that is a proper subset of the class being processed, we must
5423 also allocate a spill register during the first pass.
5425 Then make a second pass over the reloads to allocate any reloads
5426 that haven't been given registers yet. */
5428 for (j
= 0; j
< n_reloads
; j
++)
5430 int r
= reload_order
[j
];
5431 rtx search_equiv
= NULL_RTX
;
5433 /* Ignore reloads that got marked inoperative. */
5434 if (rld
[r
].out
== 0 && rld
[r
].in
== 0
5435 && ! rld
[r
].secondary_p
)
5438 /* If find_reloads chose to use reload_in or reload_out as a reload
5439 register, we don't need to chose one. Otherwise, try even if it
5440 found one since we might save an insn if we find the value lying
5442 Try also when reload_in is a pseudo without a hard reg. */
5443 if (rld
[r
].in
!= 0 && rld
[r
].reg_rtx
!= 0
5444 && (rtx_equal_p (rld
[r
].in
, rld
[r
].reg_rtx
)
5445 || (rtx_equal_p (rld
[r
].out
, rld
[r
].reg_rtx
)
5446 && !MEM_P (rld
[r
].in
)
5447 && true_regnum (rld
[r
].in
) < FIRST_PSEUDO_REGISTER
)))
5450 #if 0 /* No longer needed for correct operation.
5451 It might give better code, or might not; worth an experiment? */
5452 /* If this is an optional reload, we can't inherit from earlier insns
5453 until we are sure that any non-optional reloads have been allocated.
5454 The following code takes advantage of the fact that optional reloads
5455 are at the end of reload_order. */
5456 if (rld
[r
].optional
!= 0)
5457 for (i
= 0; i
< j
; i
++)
5458 if ((rld
[reload_order
[i
]].out
!= 0
5459 || rld
[reload_order
[i
]].in
!= 0
5460 || rld
[reload_order
[i
]].secondary_p
)
5461 && ! rld
[reload_order
[i
]].optional
5462 && rld
[reload_order
[i
]].reg_rtx
== 0)
5463 allocate_reload_reg (chain
, reload_order
[i
], 0);
5466 /* First see if this pseudo is already available as reloaded
5467 for a previous insn. We cannot try to inherit for reloads
5468 that are smaller than the maximum number of registers needed
5469 for groups unless the register we would allocate cannot be used
5472 We could check here to see if this is a secondary reload for
5473 an object that is already in a register of the desired class.
5474 This would avoid the need for the secondary reload register.
5475 But this is complex because we can't easily determine what
5476 objects might want to be loaded via this reload. So let a
5477 register be allocated here. In `emit_reload_insns' we suppress
5478 one of the loads in the case described above. */
5484 enum machine_mode mode
= VOIDmode
;
5488 else if (REG_P (rld
[r
].in
))
5490 regno
= REGNO (rld
[r
].in
);
5491 mode
= GET_MODE (rld
[r
].in
);
5493 else if (REG_P (rld
[r
].in_reg
))
5495 regno
= REGNO (rld
[r
].in_reg
);
5496 mode
= GET_MODE (rld
[r
].in_reg
);
5498 else if (GET_CODE (rld
[r
].in_reg
) == SUBREG
5499 && REG_P (SUBREG_REG (rld
[r
].in_reg
)))
5501 byte
= SUBREG_BYTE (rld
[r
].in_reg
);
5502 regno
= REGNO (SUBREG_REG (rld
[r
].in_reg
));
5503 if (regno
< FIRST_PSEUDO_REGISTER
)
5504 regno
= subreg_regno (rld
[r
].in_reg
);
5505 mode
= GET_MODE (rld
[r
].in_reg
);
5508 else if ((GET_CODE (rld
[r
].in_reg
) == PRE_INC
5509 || GET_CODE (rld
[r
].in_reg
) == PRE_DEC
5510 || GET_CODE (rld
[r
].in_reg
) == POST_INC
5511 || GET_CODE (rld
[r
].in_reg
) == POST_DEC
)
5512 && REG_P (XEXP (rld
[r
].in_reg
, 0)))
5514 regno
= REGNO (XEXP (rld
[r
].in_reg
, 0));
5515 mode
= GET_MODE (XEXP (rld
[r
].in_reg
, 0));
5516 rld
[r
].out
= rld
[r
].in
;
5520 /* This won't work, since REGNO can be a pseudo reg number.
5521 Also, it takes much more hair to keep track of all the things
5522 that can invalidate an inherited reload of part of a pseudoreg. */
5523 else if (GET_CODE (rld
[r
].in
) == SUBREG
5524 && REG_P (SUBREG_REG (rld
[r
].in
)))
5525 regno
= subreg_regno (rld
[r
].in
);
5528 if (regno
>= 0 && reg_last_reload_reg
[regno
] != 0)
5530 enum reg_class
class = rld
[r
].class, last_class
;
5531 rtx last_reg
= reg_last_reload_reg
[regno
];
5532 enum machine_mode need_mode
;
5534 i
= REGNO (last_reg
);
5535 i
+= subreg_regno_offset (i
, GET_MODE (last_reg
), byte
, mode
);
5536 last_class
= REGNO_REG_CLASS (i
);
5542 = smallest_mode_for_size (GET_MODE_BITSIZE (mode
)
5543 + byte
* BITS_PER_UNIT
,
5544 GET_MODE_CLASS (mode
));
5546 if ((GET_MODE_SIZE (GET_MODE (last_reg
))
5547 >= GET_MODE_SIZE (need_mode
))
5548 #ifdef CANNOT_CHANGE_MODE_CLASS
5549 /* Verify that the register in "i" can be obtained
5551 && !REG_CANNOT_CHANGE_MODE_P (REGNO (last_reg
),
5552 GET_MODE (last_reg
),
5555 && reg_reloaded_contents
[i
] == regno
5556 && TEST_HARD_REG_BIT (reg_reloaded_valid
, i
)
5557 && HARD_REGNO_MODE_OK (i
, rld
[r
].mode
)
5558 && (TEST_HARD_REG_BIT (reg_class_contents
[(int) class], i
)
5559 /* Even if we can't use this register as a reload
5560 register, we might use it for reload_override_in,
5561 if copying it to the desired class is cheap
5563 || ((REGISTER_MOVE_COST (mode
, last_class
, class)
5564 < MEMORY_MOVE_COST (mode
, class, 1))
5565 && (secondary_reload_class (1, class, mode
,
5568 #ifdef SECONDARY_MEMORY_NEEDED
5569 && ! SECONDARY_MEMORY_NEEDED (last_class
, class,
5574 && (rld
[r
].nregs
== max_group_size
5575 || ! TEST_HARD_REG_BIT (reg_class_contents
[(int) group_class
],
5577 && free_for_value_p (i
, rld
[r
].mode
, rld
[r
].opnum
,
5578 rld
[r
].when_needed
, rld
[r
].in
,
5581 /* If a group is needed, verify that all the subsequent
5582 registers still have their values intact. */
5583 int nr
= hard_regno_nregs
[i
][rld
[r
].mode
];
5586 for (k
= 1; k
< nr
; k
++)
5587 if (reg_reloaded_contents
[i
+ k
] != regno
5588 || ! TEST_HARD_REG_BIT (reg_reloaded_valid
, i
+ k
))
5596 last_reg
= (GET_MODE (last_reg
) == mode
5597 ? last_reg
: gen_rtx_REG (mode
, i
));
5600 for (k
= 0; k
< nr
; k
++)
5601 bad_for_class
|= ! TEST_HARD_REG_BIT (reg_class_contents
[(int) rld
[r
].class],
5604 /* We found a register that contains the
5605 value we need. If this register is the
5606 same as an `earlyclobber' operand of the
5607 current insn, just mark it as a place to
5608 reload from since we can't use it as the
5609 reload register itself. */
5611 for (i1
= 0; i1
< n_earlyclobbers
; i1
++)
5612 if (reg_overlap_mentioned_for_reload_p
5613 (reg_last_reload_reg
[regno
],
5614 reload_earlyclobbers
[i1
]))
5617 if (i1
!= n_earlyclobbers
5618 || ! (free_for_value_p (i
, rld
[r
].mode
,
5620 rld
[r
].when_needed
, rld
[r
].in
,
5622 /* Don't use it if we'd clobber a pseudo reg. */
5623 || (TEST_HARD_REG_BIT (reg_used_in_insn
, i
)
5625 && ! TEST_HARD_REG_BIT (reg_reloaded_dead
, i
))
5626 /* Don't clobber the frame pointer. */
5627 || (i
== HARD_FRAME_POINTER_REGNUM
5628 && frame_pointer_needed
5630 /* Don't really use the inherited spill reg
5631 if we need it wider than we've got it. */
5632 || (GET_MODE_SIZE (rld
[r
].mode
)
5633 > GET_MODE_SIZE (mode
))
5636 /* If find_reloads chose reload_out as reload
5637 register, stay with it - that leaves the
5638 inherited register for subsequent reloads. */
5639 || (rld
[r
].out
&& rld
[r
].reg_rtx
5640 && rtx_equal_p (rld
[r
].out
, rld
[r
].reg_rtx
)))
5642 if (! rld
[r
].optional
)
5644 reload_override_in
[r
] = last_reg
;
5645 reload_inheritance_insn
[r
]
5646 = reg_reloaded_insn
[i
];
5652 /* We can use this as a reload reg. */
5653 /* Mark the register as in use for this part of
5655 mark_reload_reg_in_use (i
,
5659 rld
[r
].reg_rtx
= last_reg
;
5660 reload_inherited
[r
] = 1;
5661 reload_inheritance_insn
[r
]
5662 = reg_reloaded_insn
[i
];
5663 reload_spill_index
[r
] = i
;
5664 for (k
= 0; k
< nr
; k
++)
5665 SET_HARD_REG_BIT (reload_reg_used_for_inherit
,
5673 /* Here's another way to see if the value is already lying around. */
5676 && ! reload_inherited
[r
]
5678 && (CONSTANT_P (rld
[r
].in
)
5679 || GET_CODE (rld
[r
].in
) == PLUS
5680 || REG_P (rld
[r
].in
)
5681 || MEM_P (rld
[r
].in
))
5682 && (rld
[r
].nregs
== max_group_size
5683 || ! reg_classes_intersect_p (rld
[r
].class, group_class
)))
5684 search_equiv
= rld
[r
].in
;
5685 /* If this is an output reload from a simple move insn, look
5686 if an equivalence for the input is available. */
5687 else if (inheritance
&& rld
[r
].in
== 0 && rld
[r
].out
!= 0)
5689 rtx set
= single_set (insn
);
5692 && rtx_equal_p (rld
[r
].out
, SET_DEST (set
))
5693 && CONSTANT_P (SET_SRC (set
)))
5694 search_equiv
= SET_SRC (set
);
5700 = find_equiv_reg (search_equiv
, insn
, rld
[r
].class,
5701 -1, NULL
, 0, rld
[r
].mode
);
5707 regno
= REGNO (equiv
);
5710 /* This must be a SUBREG of a hard register.
5711 Make a new REG since this might be used in an
5712 address and not all machines support SUBREGs
5714 gcc_assert (GET_CODE (equiv
) == SUBREG
);
5715 regno
= subreg_regno (equiv
);
5716 equiv
= gen_rtx_REG (rld
[r
].mode
, regno
);
5717 /* If we choose EQUIV as the reload register, but the
5718 loop below decides to cancel the inheritance, we'll
5719 end up reloading EQUIV in rld[r].mode, not the mode
5720 it had originally. That isn't safe when EQUIV isn't
5721 available as a spill register since its value might
5722 still be live at this point. */
5723 for (i
= regno
; i
< regno
+ (int) rld
[r
].nregs
; i
++)
5724 if (TEST_HARD_REG_BIT (reload_reg_unavailable
, i
))
5729 /* If we found a spill reg, reject it unless it is free
5730 and of the desired class. */
5734 int bad_for_class
= 0;
5735 int max_regno
= regno
+ rld
[r
].nregs
;
5737 for (i
= regno
; i
< max_regno
; i
++)
5739 regs_used
|= TEST_HARD_REG_BIT (reload_reg_used_at_all
,
5741 bad_for_class
|= ! TEST_HARD_REG_BIT (reg_class_contents
[(int) rld
[r
].class],
5746 && ! free_for_value_p (regno
, rld
[r
].mode
,
5747 rld
[r
].opnum
, rld
[r
].when_needed
,
5748 rld
[r
].in
, rld
[r
].out
, r
, 1))
5753 if (equiv
!= 0 && ! HARD_REGNO_MODE_OK (regno
, rld
[r
].mode
))
5756 /* We found a register that contains the value we need.
5757 If this register is the same as an `earlyclobber' operand
5758 of the current insn, just mark it as a place to reload from
5759 since we can't use it as the reload register itself. */
5762 for (i
= 0; i
< n_earlyclobbers
; i
++)
5763 if (reg_overlap_mentioned_for_reload_p (equiv
,
5764 reload_earlyclobbers
[i
]))
5766 if (! rld
[r
].optional
)
5767 reload_override_in
[r
] = equiv
;
5772 /* If the equiv register we have found is explicitly clobbered
5773 in the current insn, it depends on the reload type if we
5774 can use it, use it for reload_override_in, or not at all.
5775 In particular, we then can't use EQUIV for a
5776 RELOAD_FOR_OUTPUT_ADDRESS reload. */
5780 if (regno_clobbered_p (regno
, insn
, rld
[r
].mode
, 2))
5781 switch (rld
[r
].when_needed
)
5783 case RELOAD_FOR_OTHER_ADDRESS
:
5784 case RELOAD_FOR_INPADDR_ADDRESS
:
5785 case RELOAD_FOR_INPUT_ADDRESS
:
5786 case RELOAD_FOR_OPADDR_ADDR
:
5789 case RELOAD_FOR_INPUT
:
5790 case RELOAD_FOR_OPERAND_ADDRESS
:
5791 if (! rld
[r
].optional
)
5792 reload_override_in
[r
] = equiv
;
5798 else if (regno_clobbered_p (regno
, insn
, rld
[r
].mode
, 1))
5799 switch (rld
[r
].when_needed
)
5801 case RELOAD_FOR_OTHER_ADDRESS
:
5802 case RELOAD_FOR_INPADDR_ADDRESS
:
5803 case RELOAD_FOR_INPUT_ADDRESS
:
5804 case RELOAD_FOR_OPADDR_ADDR
:
5805 case RELOAD_FOR_OPERAND_ADDRESS
:
5806 case RELOAD_FOR_INPUT
:
5809 if (! rld
[r
].optional
)
5810 reload_override_in
[r
] = equiv
;
5818 /* If we found an equivalent reg, say no code need be generated
5819 to load it, and use it as our reload reg. */
5821 && (regno
!= HARD_FRAME_POINTER_REGNUM
5822 || !frame_pointer_needed
))
5824 int nr
= hard_regno_nregs
[regno
][rld
[r
].mode
];
5826 rld
[r
].reg_rtx
= equiv
;
5827 reload_inherited
[r
] = 1;
5829 /* If reg_reloaded_valid is not set for this register,
5830 there might be a stale spill_reg_store lying around.
5831 We must clear it, since otherwise emit_reload_insns
5832 might delete the store. */
5833 if (! TEST_HARD_REG_BIT (reg_reloaded_valid
, regno
))
5834 spill_reg_store
[regno
] = NULL_RTX
;
5835 /* If any of the hard registers in EQUIV are spill
5836 registers, mark them as in use for this insn. */
5837 for (k
= 0; k
< nr
; k
++)
5839 i
= spill_reg_order
[regno
+ k
];
5842 mark_reload_reg_in_use (regno
, rld
[r
].opnum
,
5845 SET_HARD_REG_BIT (reload_reg_used_for_inherit
,
5852 /* If we found a register to use already, or if this is an optional
5853 reload, we are done. */
5854 if (rld
[r
].reg_rtx
!= 0 || rld
[r
].optional
!= 0)
5858 /* No longer needed for correct operation. Might or might
5859 not give better code on the average. Want to experiment? */
5861 /* See if there is a later reload that has a class different from our
5862 class that intersects our class or that requires less register
5863 than our reload. If so, we must allocate a register to this
5864 reload now, since that reload might inherit a previous reload
5865 and take the only available register in our class. Don't do this
5866 for optional reloads since they will force all previous reloads
5867 to be allocated. Also don't do this for reloads that have been
5870 for (i
= j
+ 1; i
< n_reloads
; i
++)
5872 int s
= reload_order
[i
];
5874 if ((rld
[s
].in
== 0 && rld
[s
].out
== 0
5875 && ! rld
[s
].secondary_p
)
5879 if ((rld
[s
].class != rld
[r
].class
5880 && reg_classes_intersect_p (rld
[r
].class,
5882 || rld
[s
].nregs
< rld
[r
].nregs
)
5889 allocate_reload_reg (chain
, r
, j
== n_reloads
- 1);
5893 /* Now allocate reload registers for anything non-optional that
5894 didn't get one yet. */
5895 for (j
= 0; j
< n_reloads
; j
++)
5897 int r
= reload_order
[j
];
5899 /* Ignore reloads that got marked inoperative. */
5900 if (rld
[r
].out
== 0 && rld
[r
].in
== 0 && ! rld
[r
].secondary_p
)
5903 /* Skip reloads that already have a register allocated or are
5905 if (rld
[r
].reg_rtx
!= 0 || rld
[r
].optional
)
5908 if (! allocate_reload_reg (chain
, r
, j
== n_reloads
- 1))
5912 /* If that loop got all the way, we have won. */
5919 /* Loop around and try without any inheritance. */
5924 /* First undo everything done by the failed attempt
5925 to allocate with inheritance. */
5926 choose_reload_regs_init (chain
, save_reload_reg_rtx
);
5928 /* Some sanity tests to verify that the reloads found in the first
5929 pass are identical to the ones we have now. */
5930 gcc_assert (chain
->n_reloads
== n_reloads
);
5932 for (i
= 0; i
< n_reloads
; i
++)
5934 if (chain
->rld
[i
].regno
< 0 || chain
->rld
[i
].reg_rtx
!= 0)
5936 gcc_assert (chain
->rld
[i
].when_needed
== rld
[i
].when_needed
);
5937 for (j
= 0; j
< n_spills
; j
++)
5938 if (spill_regs
[j
] == chain
->rld
[i
].regno
)
5939 if (! set_reload_reg (j
, i
))
5940 failed_reload (chain
->insn
, i
);
5944 /* If we thought we could inherit a reload, because it seemed that
5945 nothing else wanted the same reload register earlier in the insn,
5946 verify that assumption, now that all reloads have been assigned.
5947 Likewise for reloads where reload_override_in has been set. */
5949 /* If doing expensive optimizations, do one preliminary pass that doesn't
5950 cancel any inheritance, but removes reloads that have been needed only
5951 for reloads that we know can be inherited. */
5952 for (pass
= flag_expensive_optimizations
; pass
>= 0; pass
--)
5954 for (j
= 0; j
< n_reloads
; j
++)
5956 int r
= reload_order
[j
];
5958 if (reload_inherited
[r
] && rld
[r
].reg_rtx
)
5959 check_reg
= rld
[r
].reg_rtx
;
5960 else if (reload_override_in
[r
]
5961 && (REG_P (reload_override_in
[r
])
5962 || GET_CODE (reload_override_in
[r
]) == SUBREG
))
5963 check_reg
= reload_override_in
[r
];
5966 if (! free_for_value_p (true_regnum (check_reg
), rld
[r
].mode
,
5967 rld
[r
].opnum
, rld
[r
].when_needed
, rld
[r
].in
,
5968 (reload_inherited
[r
]
5969 ? rld
[r
].out
: const0_rtx
),
5974 reload_inherited
[r
] = 0;
5975 reload_override_in
[r
] = 0;
5977 /* If we can inherit a RELOAD_FOR_INPUT, or can use a
5978 reload_override_in, then we do not need its related
5979 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads;
5980 likewise for other reload types.
5981 We handle this by removing a reload when its only replacement
5982 is mentioned in reload_in of the reload we are going to inherit.
5983 A special case are auto_inc expressions; even if the input is
5984 inherited, we still need the address for the output. We can
5985 recognize them because they have RELOAD_OUT set to RELOAD_IN.
5986 If we succeeded removing some reload and we are doing a preliminary
5987 pass just to remove such reloads, make another pass, since the
5988 removal of one reload might allow us to inherit another one. */
5990 && rld
[r
].out
!= rld
[r
].in
5991 && remove_address_replacements (rld
[r
].in
) && pass
)
5996 /* Now that reload_override_in is known valid,
5997 actually override reload_in. */
5998 for (j
= 0; j
< n_reloads
; j
++)
5999 if (reload_override_in
[j
])
6000 rld
[j
].in
= reload_override_in
[j
];
6002 /* If this reload won't be done because it has been canceled or is
6003 optional and not inherited, clear reload_reg_rtx so other
6004 routines (such as subst_reloads) don't get confused. */
6005 for (j
= 0; j
< n_reloads
; j
++)
6006 if (rld
[j
].reg_rtx
!= 0
6007 && ((rld
[j
].optional
&& ! reload_inherited
[j
])
6008 || (rld
[j
].in
== 0 && rld
[j
].out
== 0
6009 && ! rld
[j
].secondary_p
)))
6011 int regno
= true_regnum (rld
[j
].reg_rtx
);
6013 if (spill_reg_order
[regno
] >= 0)
6014 clear_reload_reg_in_use (regno
, rld
[j
].opnum
,
6015 rld
[j
].when_needed
, rld
[j
].mode
);
6017 reload_spill_index
[j
] = -1;
6020 /* Record which pseudos and which spill regs have output reloads. */
6021 for (j
= 0; j
< n_reloads
; j
++)
6023 int r
= reload_order
[j
];
6025 i
= reload_spill_index
[r
];
6027 /* I is nonneg if this reload uses a register.
6028 If rld[r].reg_rtx is 0, this is an optional reload
6029 that we opted to ignore. */
6030 if (rld
[r
].out_reg
!= 0 && REG_P (rld
[r
].out_reg
)
6031 && rld
[r
].reg_rtx
!= 0)
6033 int nregno
= REGNO (rld
[r
].out_reg
);
6036 if (nregno
< FIRST_PSEUDO_REGISTER
)
6037 nr
= hard_regno_nregs
[nregno
][rld
[r
].mode
];
6040 reg_has_output_reload
[nregno
+ nr
] = 1;
6044 nr
= hard_regno_nregs
[i
][rld
[r
].mode
];
6046 SET_HARD_REG_BIT (reg_is_output_reload
, i
+ nr
);
6049 gcc_assert (rld
[r
].when_needed
== RELOAD_OTHER
6050 || rld
[r
].when_needed
== RELOAD_FOR_OUTPUT
6051 || rld
[r
].when_needed
== RELOAD_FOR_INSN
);
6056 /* Deallocate the reload register for reload R. This is called from
6057 remove_address_replacements. */
6060 deallocate_reload_reg (int r
)
6064 if (! rld
[r
].reg_rtx
)
6066 regno
= true_regnum (rld
[r
].reg_rtx
);
6068 if (spill_reg_order
[regno
] >= 0)
6069 clear_reload_reg_in_use (regno
, rld
[r
].opnum
, rld
[r
].when_needed
,
6071 reload_spill_index
[r
] = -1;
6074 /* If SMALL_REGISTER_CLASSES is nonzero, we may not have merged two
6075 reloads of the same item for fear that we might not have enough reload
6076 registers. However, normally they will get the same reload register
6077 and hence actually need not be loaded twice.
6079 Here we check for the most common case of this phenomenon: when we have
6080 a number of reloads for the same object, each of which were allocated
6081 the same reload_reg_rtx, that reload_reg_rtx is not used for any other
6082 reload, and is not modified in the insn itself. If we find such,
6083 merge all the reloads and set the resulting reload to RELOAD_OTHER.
6084 This will not increase the number of spill registers needed and will
6085 prevent redundant code. */
6088 merge_assigned_reloads (rtx insn
)
6092 /* Scan all the reloads looking for ones that only load values and
6093 are not already RELOAD_OTHER and ones whose reload_reg_rtx are
6094 assigned and not modified by INSN. */
6096 for (i
= 0; i
< n_reloads
; i
++)
6098 int conflicting_input
= 0;
6099 int max_input_address_opnum
= -1;
6100 int min_conflicting_input_opnum
= MAX_RECOG_OPERANDS
;
6102 if (rld
[i
].in
== 0 || rld
[i
].when_needed
== RELOAD_OTHER
6103 || rld
[i
].out
!= 0 || rld
[i
].reg_rtx
== 0
6104 || reg_set_p (rld
[i
].reg_rtx
, insn
))
6107 /* Look at all other reloads. Ensure that the only use of this
6108 reload_reg_rtx is in a reload that just loads the same value
6109 as we do. Note that any secondary reloads must be of the identical
6110 class since the values, modes, and result registers are the
6111 same, so we need not do anything with any secondary reloads. */
6113 for (j
= 0; j
< n_reloads
; j
++)
6115 if (i
== j
|| rld
[j
].reg_rtx
== 0
6116 || ! reg_overlap_mentioned_p (rld
[j
].reg_rtx
,
6120 if (rld
[j
].when_needed
== RELOAD_FOR_INPUT_ADDRESS
6121 && rld
[j
].opnum
> max_input_address_opnum
)
6122 max_input_address_opnum
= rld
[j
].opnum
;
6124 /* If the reload regs aren't exactly the same (e.g, different modes)
6125 or if the values are different, we can't merge this reload.
6126 But if it is an input reload, we might still merge
6127 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_OTHER_ADDRESS reloads. */
6129 if (! rtx_equal_p (rld
[i
].reg_rtx
, rld
[j
].reg_rtx
)
6130 || rld
[j
].out
!= 0 || rld
[j
].in
== 0
6131 || ! rtx_equal_p (rld
[i
].in
, rld
[j
].in
))
6133 if (rld
[j
].when_needed
!= RELOAD_FOR_INPUT
6134 || ((rld
[i
].when_needed
!= RELOAD_FOR_INPUT_ADDRESS
6135 || rld
[i
].opnum
> rld
[j
].opnum
)
6136 && rld
[i
].when_needed
!= RELOAD_FOR_OTHER_ADDRESS
))
6138 conflicting_input
= 1;
6139 if (min_conflicting_input_opnum
> rld
[j
].opnum
)
6140 min_conflicting_input_opnum
= rld
[j
].opnum
;
6144 /* If all is OK, merge the reloads. Only set this to RELOAD_OTHER if
6145 we, in fact, found any matching reloads. */
6148 && max_input_address_opnum
<= min_conflicting_input_opnum
)
6150 gcc_assert (rld
[i
].when_needed
!= RELOAD_FOR_OUTPUT
);
6152 for (j
= 0; j
< n_reloads
; j
++)
6153 if (i
!= j
&& rld
[j
].reg_rtx
!= 0
6154 && rtx_equal_p (rld
[i
].reg_rtx
, rld
[j
].reg_rtx
)
6155 && (! conflicting_input
6156 || rld
[j
].when_needed
== RELOAD_FOR_INPUT_ADDRESS
6157 || rld
[j
].when_needed
== RELOAD_FOR_OTHER_ADDRESS
))
6159 rld
[i
].when_needed
= RELOAD_OTHER
;
6161 reload_spill_index
[j
] = -1;
6162 transfer_replacements (i
, j
);
6165 /* If this is now RELOAD_OTHER, look for any reloads that load
6166 parts of this operand and set them to RELOAD_FOR_OTHER_ADDRESS
6167 if they were for inputs, RELOAD_OTHER for outputs. Note that
6168 this test is equivalent to looking for reloads for this operand
6170 /* We must take special care with RELOAD_FOR_OUTPUT_ADDRESS; it may
6171 share registers with a RELOAD_FOR_INPUT, so we can not change it
6172 to RELOAD_FOR_OTHER_ADDRESS. We should never need to, since we
6173 do not modify RELOAD_FOR_OUTPUT. */
6175 if (rld
[i
].when_needed
== RELOAD_OTHER
)
6176 for (j
= 0; j
< n_reloads
; j
++)
6178 && rld
[j
].when_needed
!= RELOAD_OTHER
6179 && rld
[j
].when_needed
!= RELOAD_FOR_OTHER_ADDRESS
6180 && rld
[j
].when_needed
!= RELOAD_FOR_OUTPUT_ADDRESS
6181 && (! conflicting_input
6182 || rld
[j
].when_needed
== RELOAD_FOR_INPUT_ADDRESS
6183 || rld
[j
].when_needed
== RELOAD_FOR_INPADDR_ADDRESS
)
6184 && reg_overlap_mentioned_for_reload_p (rld
[j
].in
,
6190 = ((rld
[j
].when_needed
== RELOAD_FOR_INPUT_ADDRESS
6191 || rld
[j
].when_needed
== RELOAD_FOR_INPADDR_ADDRESS
)
6192 ? RELOAD_FOR_OTHER_ADDRESS
: RELOAD_OTHER
);
6194 /* Check to see if we accidentally converted two
6195 reloads that use the same reload register with
6196 different inputs to the same type. If so, the
6197 resulting code won't work. */
6199 for (k
= 0; k
< j
; k
++)
6200 gcc_assert (rld
[k
].in
== 0 || rld
[k
].reg_rtx
== 0
6201 || rld
[k
].when_needed
!= rld
[j
].when_needed
6202 || !rtx_equal_p (rld
[k
].reg_rtx
,
6204 || rtx_equal_p (rld
[k
].in
,
6211 /* These arrays are filled by emit_reload_insns and its subroutines. */
6212 static rtx input_reload_insns
[MAX_RECOG_OPERANDS
];
6213 static rtx other_input_address_reload_insns
= 0;
6214 static rtx other_input_reload_insns
= 0;
6215 static rtx input_address_reload_insns
[MAX_RECOG_OPERANDS
];
6216 static rtx inpaddr_address_reload_insns
[MAX_RECOG_OPERANDS
];
6217 static rtx output_reload_insns
[MAX_RECOG_OPERANDS
];
6218 static rtx output_address_reload_insns
[MAX_RECOG_OPERANDS
];
6219 static rtx outaddr_address_reload_insns
[MAX_RECOG_OPERANDS
];
6220 static rtx operand_reload_insns
= 0;
6221 static rtx other_operand_reload_insns
= 0;
6222 static rtx other_output_reload_insns
[MAX_RECOG_OPERANDS
];
6224 /* Values to be put in spill_reg_store are put here first. */
6225 static rtx new_spill_reg_store
[FIRST_PSEUDO_REGISTER
];
6226 static HARD_REG_SET reg_reloaded_died
;
6228 /* Check if *RELOAD_REG is suitable as an intermediate or scratch register
6229 of class NEW_CLASS with mode NEW_MODE. Or alternatively, if alt_reload_reg
6230 is nonzero, if that is suitable. On success, change *RELOAD_REG to the
6231 adjusted register, and return true. Otherwise, return false. */
6233 reload_adjust_reg_for_temp (rtx
*reload_reg
, rtx alt_reload_reg
,
6234 enum reg_class new_class
,
6235 enum machine_mode new_mode
)
6240 for (reg
= *reload_reg
; reg
; reg
= alt_reload_reg
, alt_reload_reg
= 0)
6242 unsigned regno
= REGNO (reg
);
6244 if (!TEST_HARD_REG_BIT (reg_class_contents
[(int) new_class
], regno
))
6246 if (GET_MODE (reg
) != new_mode
)
6248 if (!HARD_REGNO_MODE_OK (regno
, new_mode
))
6250 if (hard_regno_nregs
[regno
][new_mode
]
6251 > hard_regno_nregs
[regno
][GET_MODE (reg
)])
6253 reg
= reload_adjust_reg_for_mode (reg
, new_mode
);
6261 /* Check if *RELOAD_REG is suitable as a scratch register for the reload
6262 pattern with insn_code ICODE, or alternatively, if alt_reload_reg is
6263 nonzero, if that is suitable. On success, change *RELOAD_REG to the
6264 adjusted register, and return true. Otherwise, return false. */
6266 reload_adjust_reg_for_icode (rtx
*reload_reg
, rtx alt_reload_reg
,
6267 enum insn_code icode
)
6270 enum reg_class new_class
= scratch_reload_class (icode
);
6271 enum machine_mode new_mode
= insn_data
[(int) icode
].operand
[2].mode
;
6273 return reload_adjust_reg_for_temp (reload_reg
, alt_reload_reg
,
6274 new_class
, new_mode
);
6277 /* Generate insns to perform reload RL, which is for the insn in CHAIN and
6278 has the number J. OLD contains the value to be used as input. */
6281 emit_input_reload_insns (struct insn_chain
*chain
, struct reload
*rl
,
6284 rtx insn
= chain
->insn
;
6285 rtx reloadreg
= rl
->reg_rtx
;
6286 rtx oldequiv_reg
= 0;
6289 enum machine_mode mode
;
6292 /* Determine the mode to reload in.
6293 This is very tricky because we have three to choose from.
6294 There is the mode the insn operand wants (rl->inmode).
6295 There is the mode of the reload register RELOADREG.
6296 There is the intrinsic mode of the operand, which we could find
6297 by stripping some SUBREGs.
6298 It turns out that RELOADREG's mode is irrelevant:
6299 we can change that arbitrarily.
6301 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
6302 then the reload reg may not support QImode moves, so use SImode.
6303 If foo is in memory due to spilling a pseudo reg, this is safe,
6304 because the QImode value is in the least significant part of a
6305 slot big enough for a SImode. If foo is some other sort of
6306 memory reference, then it is impossible to reload this case,
6307 so previous passes had better make sure this never happens.
6309 Then consider a one-word union which has SImode and one of its
6310 members is a float, being fetched as (SUBREG:SF union:SI).
6311 We must fetch that as SFmode because we could be loading into
6312 a float-only register. In this case OLD's mode is correct.
6314 Consider an immediate integer: it has VOIDmode. Here we need
6315 to get a mode from something else.
6317 In some cases, there is a fourth mode, the operand's
6318 containing mode. If the insn specifies a containing mode for
6319 this operand, it overrides all others.
6321 I am not sure whether the algorithm here is always right,
6322 but it does the right things in those cases. */
6324 mode
= GET_MODE (old
);
6325 if (mode
== VOIDmode
)
6328 /* delete_output_reload is only invoked properly if old contains
6329 the original pseudo register. Since this is replaced with a
6330 hard reg when RELOAD_OVERRIDE_IN is set, see if we can
6331 find the pseudo in RELOAD_IN_REG. */
6332 if (reload_override_in
[j
]
6333 && REG_P (rl
->in_reg
))
6340 else if (REG_P (oldequiv
))
6341 oldequiv_reg
= oldequiv
;
6342 else if (GET_CODE (oldequiv
) == SUBREG
)
6343 oldequiv_reg
= SUBREG_REG (oldequiv
);
6345 /* If we are reloading from a register that was recently stored in
6346 with an output-reload, see if we can prove there was
6347 actually no need to store the old value in it. */
6349 if (optimize
&& REG_P (oldequiv
)
6350 && REGNO (oldequiv
) < FIRST_PSEUDO_REGISTER
6351 && spill_reg_store
[REGNO (oldequiv
)]
6353 && (dead_or_set_p (insn
, spill_reg_stored_to
[REGNO (oldequiv
)])
6354 || rtx_equal_p (spill_reg_stored_to
[REGNO (oldequiv
)],
6356 delete_output_reload (insn
, j
, REGNO (oldequiv
));
6358 /* Encapsulate both RELOADREG and OLDEQUIV into that mode,
6359 then load RELOADREG from OLDEQUIV. Note that we cannot use
6360 gen_lowpart_common since it can do the wrong thing when
6361 RELOADREG has a multi-word mode. Note that RELOADREG
6362 must always be a REG here. */
6364 if (GET_MODE (reloadreg
) != mode
)
6365 reloadreg
= reload_adjust_reg_for_mode (reloadreg
, mode
);
6366 while (GET_CODE (oldequiv
) == SUBREG
&& GET_MODE (oldequiv
) != mode
)
6367 oldequiv
= SUBREG_REG (oldequiv
);
6368 if (GET_MODE (oldequiv
) != VOIDmode
6369 && mode
!= GET_MODE (oldequiv
))
6370 oldequiv
= gen_lowpart_SUBREG (mode
, oldequiv
);
6372 /* Switch to the right place to emit the reload insns. */
6373 switch (rl
->when_needed
)
6376 where
= &other_input_reload_insns
;
6378 case RELOAD_FOR_INPUT
:
6379 where
= &input_reload_insns
[rl
->opnum
];
6381 case RELOAD_FOR_INPUT_ADDRESS
:
6382 where
= &input_address_reload_insns
[rl
->opnum
];
6384 case RELOAD_FOR_INPADDR_ADDRESS
:
6385 where
= &inpaddr_address_reload_insns
[rl
->opnum
];
6387 case RELOAD_FOR_OUTPUT_ADDRESS
:
6388 where
= &output_address_reload_insns
[rl
->opnum
];
6390 case RELOAD_FOR_OUTADDR_ADDRESS
:
6391 where
= &outaddr_address_reload_insns
[rl
->opnum
];
6393 case RELOAD_FOR_OPERAND_ADDRESS
:
6394 where
= &operand_reload_insns
;
6396 case RELOAD_FOR_OPADDR_ADDR
:
6397 where
= &other_operand_reload_insns
;
6399 case RELOAD_FOR_OTHER_ADDRESS
:
6400 where
= &other_input_address_reload_insns
;
6406 push_to_sequence (*where
);
6408 /* Auto-increment addresses must be reloaded in a special way. */
6409 if (rl
->out
&& ! rl
->out_reg
)
6411 /* We are not going to bother supporting the case where a
6412 incremented register can't be copied directly from
6413 OLDEQUIV since this seems highly unlikely. */
6414 gcc_assert (rl
->secondary_in_reload
< 0);
6416 if (reload_inherited
[j
])
6417 oldequiv
= reloadreg
;
6419 old
= XEXP (rl
->in_reg
, 0);
6421 if (optimize
&& REG_P (oldequiv
)
6422 && REGNO (oldequiv
) < FIRST_PSEUDO_REGISTER
6423 && spill_reg_store
[REGNO (oldequiv
)]
6425 && (dead_or_set_p (insn
,
6426 spill_reg_stored_to
[REGNO (oldequiv
)])
6427 || rtx_equal_p (spill_reg_stored_to
[REGNO (oldequiv
)],
6429 delete_output_reload (insn
, j
, REGNO (oldequiv
));
6431 /* Prevent normal processing of this reload. */
6433 /* Output a special code sequence for this case. */
6434 new_spill_reg_store
[REGNO (reloadreg
)]
6435 = inc_for_reload (reloadreg
, oldequiv
, rl
->out
,
6439 /* If we are reloading a pseudo-register that was set by the previous
6440 insn, see if we can get rid of that pseudo-register entirely
6441 by redirecting the previous insn into our reload register. */
6443 else if (optimize
&& REG_P (old
)
6444 && REGNO (old
) >= FIRST_PSEUDO_REGISTER
6445 && dead_or_set_p (insn
, old
)
6446 /* This is unsafe if some other reload
6447 uses the same reg first. */
6448 && ! conflicts_with_override (reloadreg
)
6449 && free_for_value_p (REGNO (reloadreg
), rl
->mode
, rl
->opnum
,
6450 rl
->when_needed
, old
, rl
->out
, j
, 0))
6452 rtx temp
= PREV_INSN (insn
);
6453 while (temp
&& NOTE_P (temp
))
6454 temp
= PREV_INSN (temp
);
6456 && NONJUMP_INSN_P (temp
)
6457 && GET_CODE (PATTERN (temp
)) == SET
6458 && SET_DEST (PATTERN (temp
)) == old
6459 /* Make sure we can access insn_operand_constraint. */
6460 && asm_noperands (PATTERN (temp
)) < 0
6461 /* This is unsafe if operand occurs more than once in current
6462 insn. Perhaps some occurrences aren't reloaded. */
6463 && count_occurrences (PATTERN (insn
), old
, 0) == 1)
6465 rtx old
= SET_DEST (PATTERN (temp
));
6466 /* Store into the reload register instead of the pseudo. */
6467 SET_DEST (PATTERN (temp
)) = reloadreg
;
6469 /* Verify that resulting insn is valid. */
6470 extract_insn (temp
);
6471 if (constrain_operands (1))
6473 /* If the previous insn is an output reload, the source is
6474 a reload register, and its spill_reg_store entry will
6475 contain the previous destination. This is now
6477 if (REG_P (SET_SRC (PATTERN (temp
)))
6478 && REGNO (SET_SRC (PATTERN (temp
))) < FIRST_PSEUDO_REGISTER
)
6480 spill_reg_store
[REGNO (SET_SRC (PATTERN (temp
)))] = 0;
6481 spill_reg_stored_to
[REGNO (SET_SRC (PATTERN (temp
)))] = 0;
6484 /* If these are the only uses of the pseudo reg,
6485 pretend for GDB it lives in the reload reg we used. */
6486 if (REG_N_DEATHS (REGNO (old
)) == 1
6487 && REG_N_SETS (REGNO (old
)) == 1)
6489 reg_renumber
[REGNO (old
)] = REGNO (rl
->reg_rtx
);
6490 alter_reg (REGNO (old
), -1);
6496 SET_DEST (PATTERN (temp
)) = old
;
6501 /* We can't do that, so output an insn to load RELOADREG. */
6503 /* If we have a secondary reload, pick up the secondary register
6504 and icode, if any. If OLDEQUIV and OLD are different or
6505 if this is an in-out reload, recompute whether or not we
6506 still need a secondary register and what the icode should
6507 be. If we still need a secondary register and the class or
6508 icode is different, go back to reloading from OLD if using
6509 OLDEQUIV means that we got the wrong type of register. We
6510 cannot have different class or icode due to an in-out reload
6511 because we don't make such reloads when both the input and
6512 output need secondary reload registers. */
6514 if (! special
&& rl
->secondary_in_reload
>= 0)
6516 rtx second_reload_reg
= 0;
6517 rtx third_reload_reg
= 0;
6518 int secondary_reload
= rl
->secondary_in_reload
;
6519 rtx real_oldequiv
= oldequiv
;
6522 enum insn_code icode
;
6523 enum insn_code tertiary_icode
= CODE_FOR_nothing
;
6525 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
6526 and similarly for OLD.
6527 See comments in get_secondary_reload in reload.c. */
6528 /* If it is a pseudo that cannot be replaced with its
6529 equivalent MEM, we must fall back to reload_in, which
6530 will have all the necessary substitutions registered.
6531 Likewise for a pseudo that can't be replaced with its
6532 equivalent constant.
6534 Take extra care for subregs of such pseudos. Note that
6535 we cannot use reg_equiv_mem in this case because it is
6536 not in the right mode. */
6539 if (GET_CODE (tmp
) == SUBREG
)
6540 tmp
= SUBREG_REG (tmp
);
6542 && REGNO (tmp
) >= FIRST_PSEUDO_REGISTER
6543 && (reg_equiv_memory_loc
[REGNO (tmp
)] != 0
6544 || reg_equiv_constant
[REGNO (tmp
)] != 0))
6546 if (! reg_equiv_mem
[REGNO (tmp
)]
6547 || num_not_at_initial_offset
6548 || GET_CODE (oldequiv
) == SUBREG
)
6549 real_oldequiv
= rl
->in
;
6551 real_oldequiv
= reg_equiv_mem
[REGNO (tmp
)];
6555 if (GET_CODE (tmp
) == SUBREG
)
6556 tmp
= SUBREG_REG (tmp
);
6558 && REGNO (tmp
) >= FIRST_PSEUDO_REGISTER
6559 && (reg_equiv_memory_loc
[REGNO (tmp
)] != 0
6560 || reg_equiv_constant
[REGNO (tmp
)] != 0))
6562 if (! reg_equiv_mem
[REGNO (tmp
)]
6563 || num_not_at_initial_offset
6564 || GET_CODE (old
) == SUBREG
)
6567 real_old
= reg_equiv_mem
[REGNO (tmp
)];
6570 second_reload_reg
= rld
[secondary_reload
].reg_rtx
;
6571 if (rld
[secondary_reload
].secondary_in_reload
>= 0)
6573 int tertiary_reload
= rld
[secondary_reload
].secondary_in_reload
;
6575 third_reload_reg
= rld
[tertiary_reload
].reg_rtx
;
6576 tertiary_icode
= rld
[secondary_reload
].secondary_in_icode
;
6577 /* We'd have to add more code for quartary reloads. */
6578 gcc_assert (rld
[tertiary_reload
].secondary_in_reload
< 0);
6580 icode
= rl
->secondary_in_icode
;
6582 if ((old
!= oldequiv
&& ! rtx_equal_p (old
, oldequiv
))
6583 || (rl
->in
!= 0 && rl
->out
!= 0))
6585 secondary_reload_info sri
, sri2
;
6586 enum reg_class new_class
, new_t_class
;
6588 sri
.icode
= CODE_FOR_nothing
;
6589 sri
.prev_sri
= NULL
;
6590 new_class
= targetm
.secondary_reload (1, real_oldequiv
, rl
->class,
6593 if (new_class
== NO_REGS
&& sri
.icode
== CODE_FOR_nothing
)
6594 second_reload_reg
= 0;
6595 else if (new_class
== NO_REGS
)
6597 if (reload_adjust_reg_for_icode (&second_reload_reg
,
6598 third_reload_reg
, sri
.icode
))
6599 icode
= sri
.icode
, third_reload_reg
= 0;
6601 oldequiv
= old
, real_oldequiv
= real_old
;
6603 else if (sri
.icode
!= CODE_FOR_nothing
)
6604 /* We currently lack a way to express this in reloads. */
6608 sri2
.icode
= CODE_FOR_nothing
;
6609 sri2
.prev_sri
= &sri
;
6610 new_t_class
= targetm
.secondary_reload (1, real_oldequiv
,
6611 new_class
, mode
, &sri
);
6612 if (new_t_class
== NO_REGS
&& sri2
.icode
== CODE_FOR_nothing
)
6614 if (reload_adjust_reg_for_temp (&second_reload_reg
,
6617 third_reload_reg
= 0, tertiary_icode
= sri2
.icode
;
6619 oldequiv
= old
, real_oldequiv
= real_old
;
6621 else if (new_t_class
== NO_REGS
&& sri2
.icode
!= CODE_FOR_nothing
)
6623 rtx intermediate
= second_reload_reg
;
6625 if (reload_adjust_reg_for_temp (&intermediate
, NULL
,
6627 && reload_adjust_reg_for_icode (&third_reload_reg
, NULL
,
6630 second_reload_reg
= intermediate
;
6631 tertiary_icode
= sri2
.icode
;
6634 oldequiv
= old
, real_oldequiv
= real_old
;
6636 else if (new_t_class
!= NO_REGS
&& sri2
.icode
== CODE_FOR_nothing
)
6638 rtx intermediate
= second_reload_reg
;
6640 if (reload_adjust_reg_for_temp (&intermediate
, NULL
,
6642 && reload_adjust_reg_for_temp (&third_reload_reg
, NULL
,
6645 second_reload_reg
= intermediate
;
6646 tertiary_icode
= sri2
.icode
;
6649 oldequiv
= old
, real_oldequiv
= real_old
;
6652 /* This could be handled more intelligently too. */
6653 oldequiv
= old
, real_oldequiv
= real_old
;
6657 /* If we still need a secondary reload register, check
6658 to see if it is being used as a scratch or intermediate
6659 register and generate code appropriately. If we need
6660 a scratch register, use REAL_OLDEQUIV since the form of
6661 the insn may depend on the actual address if it is
6664 if (second_reload_reg
)
6666 if (icode
!= CODE_FOR_nothing
)
6668 /* We'd have to add extra code to handle this case. */
6669 gcc_assert (!third_reload_reg
);
6671 emit_insn (GEN_FCN (icode
) (reloadreg
, real_oldequiv
,
6672 second_reload_reg
));
6677 /* See if we need a scratch register to load the
6678 intermediate register (a tertiary reload). */
6679 if (tertiary_icode
!= CODE_FOR_nothing
)
6681 emit_insn ((GEN_FCN (tertiary_icode
)
6682 (second_reload_reg
, real_oldequiv
,
6683 third_reload_reg
)));
6685 else if (third_reload_reg
)
6687 gen_reload (third_reload_reg
, real_oldequiv
,
6690 gen_reload (second_reload_reg
, third_reload_reg
,
6695 gen_reload (second_reload_reg
, real_oldequiv
,
6699 oldequiv
= second_reload_reg
;
6704 if (! special
&& ! rtx_equal_p (reloadreg
, oldequiv
))
6706 rtx real_oldequiv
= oldequiv
;
6708 if ((REG_P (oldequiv
)
6709 && REGNO (oldequiv
) >= FIRST_PSEUDO_REGISTER
6710 && (reg_equiv_memory_loc
[REGNO (oldequiv
)] != 0
6711 || reg_equiv_constant
[REGNO (oldequiv
)] != 0))
6712 || (GET_CODE (oldequiv
) == SUBREG
6713 && REG_P (SUBREG_REG (oldequiv
))
6714 && (REGNO (SUBREG_REG (oldequiv
))
6715 >= FIRST_PSEUDO_REGISTER
)
6716 && ((reg_equiv_memory_loc
6717 [REGNO (SUBREG_REG (oldequiv
))] != 0)
6718 || (reg_equiv_constant
6719 [REGNO (SUBREG_REG (oldequiv
))] != 0)))
6720 || (CONSTANT_P (oldequiv
)
6721 && (PREFERRED_RELOAD_CLASS (oldequiv
,
6722 REGNO_REG_CLASS (REGNO (reloadreg
)))
6724 real_oldequiv
= rl
->in
;
6725 gen_reload (reloadreg
, real_oldequiv
, rl
->opnum
,
6729 if (flag_non_call_exceptions
)
6730 copy_eh_notes (insn
, get_insns ());
6732 /* End this sequence. */
6733 *where
= get_insns ();
6736 /* Update reload_override_in so that delete_address_reloads_1
6737 can see the actual register usage. */
6739 reload_override_in
[j
] = oldequiv
;
6742 /* Generate insns to for the output reload RL, which is for the insn described
6743 by CHAIN and has the number J. */
6745 emit_output_reload_insns (struct insn_chain
*chain
, struct reload
*rl
,
6748 rtx reloadreg
= rl
->reg_rtx
;
6749 rtx insn
= chain
->insn
;
6752 enum machine_mode mode
= GET_MODE (old
);
6755 if (rl
->when_needed
== RELOAD_OTHER
)
6758 push_to_sequence (output_reload_insns
[rl
->opnum
]);
6760 /* Determine the mode to reload in.
6761 See comments above (for input reloading). */
6763 if (mode
== VOIDmode
)
6765 /* VOIDmode should never happen for an output. */
6766 if (asm_noperands (PATTERN (insn
)) < 0)
6767 /* It's the compiler's fault. */
6768 fatal_insn ("VOIDmode on an output", insn
);
6769 error_for_asm (insn
, "output operand is constant in %<asm%>");
6770 /* Prevent crash--use something we know is valid. */
6772 old
= gen_rtx_REG (mode
, REGNO (reloadreg
));
6775 if (GET_MODE (reloadreg
) != mode
)
6776 reloadreg
= reload_adjust_reg_for_mode (reloadreg
, mode
);
6778 /* If we need two reload regs, set RELOADREG to the intermediate
6779 one, since it will be stored into OLD. We might need a secondary
6780 register only for an input reload, so check again here. */
6782 if (rl
->secondary_out_reload
>= 0)
6785 int secondary_reload
= rl
->secondary_out_reload
;
6786 int tertiary_reload
= rld
[secondary_reload
].secondary_out_reload
;
6788 if (REG_P (old
) && REGNO (old
) >= FIRST_PSEUDO_REGISTER
6789 && reg_equiv_mem
[REGNO (old
)] != 0)
6790 real_old
= reg_equiv_mem
[REGNO (old
)];
6792 if (secondary_reload_class (0, rl
->class, mode
, real_old
) != NO_REGS
)
6794 rtx second_reloadreg
= reloadreg
;
6795 reloadreg
= rld
[secondary_reload
].reg_rtx
;
6797 /* See if RELOADREG is to be used as a scratch register
6798 or as an intermediate register. */
6799 if (rl
->secondary_out_icode
!= CODE_FOR_nothing
)
6801 /* We'd have to add extra code to handle this case. */
6802 gcc_assert (tertiary_reload
< 0);
6804 emit_insn ((GEN_FCN (rl
->secondary_out_icode
)
6805 (real_old
, second_reloadreg
, reloadreg
)));
6810 /* See if we need both a scratch and intermediate reload
6813 enum insn_code tertiary_icode
6814 = rld
[secondary_reload
].secondary_out_icode
;
6816 /* We'd have to add more code for quartary reloads. */
6817 gcc_assert (tertiary_reload
< 0
6818 || rld
[tertiary_reload
].secondary_out_reload
< 0);
6820 if (GET_MODE (reloadreg
) != mode
)
6821 reloadreg
= reload_adjust_reg_for_mode (reloadreg
, mode
);
6823 if (tertiary_icode
!= CODE_FOR_nothing
)
6825 rtx third_reloadreg
= rld
[tertiary_reload
].reg_rtx
;
6828 /* Copy primary reload reg to secondary reload reg.
6829 (Note that these have been swapped above, then
6830 secondary reload reg to OLD using our insn.) */
6832 /* If REAL_OLD is a paradoxical SUBREG, remove it
6833 and try to put the opposite SUBREG on
6835 if (GET_CODE (real_old
) == SUBREG
6836 && (GET_MODE_SIZE (GET_MODE (real_old
))
6837 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (real_old
))))
6838 && 0 != (tem
= gen_lowpart_common
6839 (GET_MODE (SUBREG_REG (real_old
)),
6841 real_old
= SUBREG_REG (real_old
), reloadreg
= tem
;
6843 gen_reload (reloadreg
, second_reloadreg
,
6844 rl
->opnum
, rl
->when_needed
);
6845 emit_insn ((GEN_FCN (tertiary_icode
)
6846 (real_old
, reloadreg
, third_reloadreg
)));
6852 /* Copy between the reload regs here and then to
6855 gen_reload (reloadreg
, second_reloadreg
,
6856 rl
->opnum
, rl
->when_needed
);
6857 if (tertiary_reload
>= 0)
6859 rtx third_reloadreg
= rld
[tertiary_reload
].reg_rtx
;
6861 gen_reload (third_reloadreg
, reloadreg
,
6862 rl
->opnum
, rl
->when_needed
);
6863 reloadreg
= third_reloadreg
;
6870 /* Output the last reload insn. */
6875 /* Don't output the last reload if OLD is not the dest of
6876 INSN and is in the src and is clobbered by INSN. */
6877 if (! flag_expensive_optimizations
6879 || !(set
= single_set (insn
))
6880 || rtx_equal_p (old
, SET_DEST (set
))
6881 || !reg_mentioned_p (old
, SET_SRC (set
))
6882 || !((REGNO (old
) < FIRST_PSEUDO_REGISTER
)
6883 && regno_clobbered_p (REGNO (old
), insn
, rl
->mode
, 0)))
6884 gen_reload (old
, reloadreg
, rl
->opnum
,
6888 /* Look at all insns we emitted, just to be safe. */
6889 for (p
= get_insns (); p
; p
= NEXT_INSN (p
))
6892 rtx pat
= PATTERN (p
);
6894 /* If this output reload doesn't come from a spill reg,
6895 clear any memory of reloaded copies of the pseudo reg.
6896 If this output reload comes from a spill reg,
6897 reg_has_output_reload will make this do nothing. */
6898 note_stores (pat
, forget_old_reloads_1
, NULL
);
6900 if (reg_mentioned_p (rl
->reg_rtx
, pat
))
6902 rtx set
= single_set (insn
);
6903 if (reload_spill_index
[j
] < 0
6905 && SET_SRC (set
) == rl
->reg_rtx
)
6907 int src
= REGNO (SET_SRC (set
));
6909 reload_spill_index
[j
] = src
;
6910 SET_HARD_REG_BIT (reg_is_output_reload
, src
);
6911 if (find_regno_note (insn
, REG_DEAD
, src
))
6912 SET_HARD_REG_BIT (reg_reloaded_died
, src
);
6914 if (REGNO (rl
->reg_rtx
) < FIRST_PSEUDO_REGISTER
)
6916 int s
= rl
->secondary_out_reload
;
6917 set
= single_set (p
);
6918 /* If this reload copies only to the secondary reload
6919 register, the secondary reload does the actual
6921 if (s
>= 0 && set
== NULL_RTX
)
6922 /* We can't tell what function the secondary reload
6923 has and where the actual store to the pseudo is
6924 made; leave new_spill_reg_store alone. */
6927 && SET_SRC (set
) == rl
->reg_rtx
6928 && SET_DEST (set
) == rld
[s
].reg_rtx
)
6930 /* Usually the next instruction will be the
6931 secondary reload insn; if we can confirm
6932 that it is, setting new_spill_reg_store to
6933 that insn will allow an extra optimization. */
6934 rtx s_reg
= rld
[s
].reg_rtx
;
6935 rtx next
= NEXT_INSN (p
);
6936 rld
[s
].out
= rl
->out
;
6937 rld
[s
].out_reg
= rl
->out_reg
;
6938 set
= single_set (next
);
6939 if (set
&& SET_SRC (set
) == s_reg
6940 && ! new_spill_reg_store
[REGNO (s_reg
)])
6942 SET_HARD_REG_BIT (reg_is_output_reload
,
6944 new_spill_reg_store
[REGNO (s_reg
)] = next
;
6948 new_spill_reg_store
[REGNO (rl
->reg_rtx
)] = p
;
6953 if (rl
->when_needed
== RELOAD_OTHER
)
6955 emit_insn (other_output_reload_insns
[rl
->opnum
]);
6956 other_output_reload_insns
[rl
->opnum
] = get_insns ();
6959 output_reload_insns
[rl
->opnum
] = get_insns ();
6961 if (flag_non_call_exceptions
)
6962 copy_eh_notes (insn
, get_insns ());
6967 /* Do input reloading for reload RL, which is for the insn described by CHAIN
6968 and has the number J. */
6970 do_input_reload (struct insn_chain
*chain
, struct reload
*rl
, int j
)
6972 rtx insn
= chain
->insn
;
6973 rtx old
= (rl
->in
&& MEM_P (rl
->in
)
6974 ? rl
->in_reg
: rl
->in
);
6977 /* AUTO_INC reloads need to be handled even if inherited. We got an
6978 AUTO_INC reload if reload_out is set but reload_out_reg isn't. */
6979 && (! reload_inherited
[j
] || (rl
->out
&& ! rl
->out_reg
))
6980 && ! rtx_equal_p (rl
->reg_rtx
, old
)
6981 && rl
->reg_rtx
!= 0)
6982 emit_input_reload_insns (chain
, rld
+ j
, old
, j
);
6984 /* When inheriting a wider reload, we have a MEM in rl->in,
6985 e.g. inheriting a SImode output reload for
6986 (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */
6987 if (optimize
&& reload_inherited
[j
] && rl
->in
6989 && MEM_P (rl
->in_reg
)
6990 && reload_spill_index
[j
] >= 0
6991 && TEST_HARD_REG_BIT (reg_reloaded_valid
, reload_spill_index
[j
]))
6992 rl
->in
= regno_reg_rtx
[reg_reloaded_contents
[reload_spill_index
[j
]]];
6994 /* If we are reloading a register that was recently stored in with an
6995 output-reload, see if we can prove there was
6996 actually no need to store the old value in it. */
6999 /* Only attempt this for input reloads; for RELOAD_OTHER we miss
7000 that there may be multiple uses of the previous output reload.
7001 Restricting to RELOAD_FOR_INPUT is mostly paranoia. */
7002 && rl
->when_needed
== RELOAD_FOR_INPUT
7003 && (reload_inherited
[j
] || reload_override_in
[j
])
7005 && REG_P (rl
->reg_rtx
)
7006 && spill_reg_store
[REGNO (rl
->reg_rtx
)] != 0
7008 /* There doesn't seem to be any reason to restrict this to pseudos
7009 and doing so loses in the case where we are copying from a
7010 register of the wrong class. */
7011 && (REGNO (spill_reg_stored_to
[REGNO (rl
->reg_rtx
)])
7012 >= FIRST_PSEUDO_REGISTER
)
7014 /* The insn might have already some references to stackslots
7015 replaced by MEMs, while reload_out_reg still names the
7017 && (dead_or_set_p (insn
,
7018 spill_reg_stored_to
[REGNO (rl
->reg_rtx
)])
7019 || rtx_equal_p (spill_reg_stored_to
[REGNO (rl
->reg_rtx
)],
7021 delete_output_reload (insn
, j
, REGNO (rl
->reg_rtx
));
7024 /* Do output reloading for reload RL, which is for the insn described by
7025 CHAIN and has the number J.
7026 ??? At some point we need to support handling output reloads of
7027 JUMP_INSNs or insns that set cc0. */
7029 do_output_reload (struct insn_chain
*chain
, struct reload
*rl
, int j
)
7032 rtx insn
= chain
->insn
;
7033 /* If this is an output reload that stores something that is
7034 not loaded in this same reload, see if we can eliminate a previous
7036 rtx pseudo
= rl
->out_reg
;
7041 && ! rtx_equal_p (rl
->in_reg
, pseudo
)
7042 && REGNO (pseudo
) >= FIRST_PSEUDO_REGISTER
7043 && reg_last_reload_reg
[REGNO (pseudo
)])
7045 int pseudo_no
= REGNO (pseudo
);
7046 int last_regno
= REGNO (reg_last_reload_reg
[pseudo_no
]);
7048 /* We don't need to test full validity of last_regno for
7049 inherit here; we only want to know if the store actually
7050 matches the pseudo. */
7051 if (TEST_HARD_REG_BIT (reg_reloaded_valid
, last_regno
)
7052 && reg_reloaded_contents
[last_regno
] == pseudo_no
7053 && spill_reg_store
[last_regno
]
7054 && rtx_equal_p (pseudo
, spill_reg_stored_to
[last_regno
]))
7055 delete_output_reload (insn
, j
, last_regno
);
7060 || rl
->reg_rtx
== old
7061 || rl
->reg_rtx
== 0)
7064 /* An output operand that dies right away does need a reload,
7065 but need not be copied from it. Show the new location in the
7067 if ((REG_P (old
) || GET_CODE (old
) == SCRATCH
)
7068 && (note
= find_reg_note (insn
, REG_UNUSED
, old
)) != 0)
7070 XEXP (note
, 0) = rl
->reg_rtx
;
7073 /* Likewise for a SUBREG of an operand that dies. */
7074 else if (GET_CODE (old
) == SUBREG
7075 && REG_P (SUBREG_REG (old
))
7076 && 0 != (note
= find_reg_note (insn
, REG_UNUSED
,
7079 XEXP (note
, 0) = gen_lowpart_common (GET_MODE (old
),
7083 else if (GET_CODE (old
) == SCRATCH
)
7084 /* If we aren't optimizing, there won't be a REG_UNUSED note,
7085 but we don't want to make an output reload. */
7088 /* If is a JUMP_INSN, we can't support output reloads yet. */
7089 gcc_assert (NONJUMP_INSN_P (insn
));
7091 emit_output_reload_insns (chain
, rld
+ j
, j
);
7094 /* Reload number R reloads from or to a group of hard registers starting at
7095 register REGNO. Return true if it can be treated for inheritance purposes
7096 like a group of reloads, each one reloading a single hard register.
7097 The caller has already checked that the spill register and REGNO use
7098 the same number of registers to store the reload value. */
7101 inherit_piecemeal_p (int r ATTRIBUTE_UNUSED
, int regno ATTRIBUTE_UNUSED
)
7103 #ifdef CANNOT_CHANGE_MODE_CLASS
7104 return (!REG_CANNOT_CHANGE_MODE_P (reload_spill_index
[r
],
7105 GET_MODE (rld
[r
].reg_rtx
),
7106 reg_raw_mode
[reload_spill_index
[r
]])
7107 && !REG_CANNOT_CHANGE_MODE_P (regno
,
7108 GET_MODE (rld
[r
].reg_rtx
),
7109 reg_raw_mode
[regno
]));
7115 /* Output insns to reload values in and out of the chosen reload regs. */
7118 emit_reload_insns (struct insn_chain
*chain
)
7120 rtx insn
= chain
->insn
;
7124 CLEAR_HARD_REG_SET (reg_reloaded_died
);
7126 for (j
= 0; j
< reload_n_operands
; j
++)
7127 input_reload_insns
[j
] = input_address_reload_insns
[j
]
7128 = inpaddr_address_reload_insns
[j
]
7129 = output_reload_insns
[j
] = output_address_reload_insns
[j
]
7130 = outaddr_address_reload_insns
[j
]
7131 = other_output_reload_insns
[j
] = 0;
7132 other_input_address_reload_insns
= 0;
7133 other_input_reload_insns
= 0;
7134 operand_reload_insns
= 0;
7135 other_operand_reload_insns
= 0;
7137 /* Dump reloads into the dump file. */
7140 fprintf (dump_file
, "\nReloads for insn # %d\n", INSN_UID (insn
));
7141 debug_reload_to_stream (dump_file
);
7144 /* Now output the instructions to copy the data into and out of the
7145 reload registers. Do these in the order that the reloads were reported,
7146 since reloads of base and index registers precede reloads of operands
7147 and the operands may need the base and index registers reloaded. */
7149 for (j
= 0; j
< n_reloads
; j
++)
7152 && REGNO (rld
[j
].reg_rtx
) < FIRST_PSEUDO_REGISTER
)
7153 new_spill_reg_store
[REGNO (rld
[j
].reg_rtx
)] = 0;
7155 do_input_reload (chain
, rld
+ j
, j
);
7156 do_output_reload (chain
, rld
+ j
, j
);
7159 /* Now write all the insns we made for reloads in the order expected by
7160 the allocation functions. Prior to the insn being reloaded, we write
7161 the following reloads:
7163 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
7165 RELOAD_OTHER reloads.
7167 For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
7168 by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
7169 RELOAD_FOR_INPUT reload for the operand.
7171 RELOAD_FOR_OPADDR_ADDRS reloads.
7173 RELOAD_FOR_OPERAND_ADDRESS reloads.
7175 After the insn being reloaded, we write the following:
7177 For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
7178 by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
7179 RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
7180 reloads for the operand. The RELOAD_OTHER output reloads are
7181 output in descending order by reload number. */
7183 emit_insn_before (other_input_address_reload_insns
, insn
);
7184 emit_insn_before (other_input_reload_insns
, insn
);
7186 for (j
= 0; j
< reload_n_operands
; j
++)
7188 emit_insn_before (inpaddr_address_reload_insns
[j
], insn
);
7189 emit_insn_before (input_address_reload_insns
[j
], insn
);
7190 emit_insn_before (input_reload_insns
[j
], insn
);
7193 emit_insn_before (other_operand_reload_insns
, insn
);
7194 emit_insn_before (operand_reload_insns
, insn
);
7196 for (j
= 0; j
< reload_n_operands
; j
++)
7198 rtx x
= emit_insn_after (outaddr_address_reload_insns
[j
], insn
);
7199 x
= emit_insn_after (output_address_reload_insns
[j
], x
);
7200 x
= emit_insn_after (output_reload_insns
[j
], x
);
7201 emit_insn_after (other_output_reload_insns
[j
], x
);
7204 /* For all the spill regs newly reloaded in this instruction,
7205 record what they were reloaded from, so subsequent instructions
7206 can inherit the reloads.
7208 Update spill_reg_store for the reloads of this insn.
7209 Copy the elements that were updated in the loop above. */
7211 for (j
= 0; j
< n_reloads
; j
++)
7213 int r
= reload_order
[j
];
7214 int i
= reload_spill_index
[r
];
7216 /* If this is a non-inherited input reload from a pseudo, we must
7217 clear any memory of a previous store to the same pseudo. Only do
7218 something if there will not be an output reload for the pseudo
7220 if (rld
[r
].in_reg
!= 0
7221 && ! (reload_inherited
[r
] || reload_override_in
[r
]))
7223 rtx reg
= rld
[r
].in_reg
;
7225 if (GET_CODE (reg
) == SUBREG
)
7226 reg
= SUBREG_REG (reg
);
7229 && REGNO (reg
) >= FIRST_PSEUDO_REGISTER
7230 && ! reg_has_output_reload
[REGNO (reg
)])
7232 int nregno
= REGNO (reg
);
7234 if (reg_last_reload_reg
[nregno
])
7236 int last_regno
= REGNO (reg_last_reload_reg
[nregno
]);
7238 if (reg_reloaded_contents
[last_regno
] == nregno
)
7239 spill_reg_store
[last_regno
] = 0;
7244 /* I is nonneg if this reload used a register.
7245 If rld[r].reg_rtx is 0, this is an optional reload
7246 that we opted to ignore. */
7248 if (i
>= 0 && rld
[r
].reg_rtx
!= 0)
7250 int nr
= hard_regno_nregs
[i
][GET_MODE (rld
[r
].reg_rtx
)];
7252 int part_reaches_end
= 0;
7253 int all_reaches_end
= 1;
7255 /* For a multi register reload, we need to check if all or part
7256 of the value lives to the end. */
7257 for (k
= 0; k
< nr
; k
++)
7259 if (reload_reg_reaches_end_p (i
+ k
, rld
[r
].opnum
,
7260 rld
[r
].when_needed
))
7261 part_reaches_end
= 1;
7263 all_reaches_end
= 0;
7266 /* Ignore reloads that don't reach the end of the insn in
7268 if (all_reaches_end
)
7270 /* First, clear out memory of what used to be in this spill reg.
7271 If consecutive registers are used, clear them all. */
7273 for (k
= 0; k
< nr
; k
++)
7275 CLEAR_HARD_REG_BIT (reg_reloaded_valid
, i
+ k
);
7276 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered
, i
+ k
);
7279 /* Maybe the spill reg contains a copy of reload_out. */
7281 && (REG_P (rld
[r
].out
)
7285 || REG_P (rld
[r
].out_reg
)))
7287 rtx out
= (REG_P (rld
[r
].out
)
7291 /* AUTO_INC */ : XEXP (rld
[r
].in_reg
, 0));
7292 int nregno
= REGNO (out
);
7293 int nnr
= (nregno
>= FIRST_PSEUDO_REGISTER
? 1
7294 : hard_regno_nregs
[nregno
]
7295 [GET_MODE (rld
[r
].reg_rtx
)]);
7298 spill_reg_store
[i
] = new_spill_reg_store
[i
];
7299 spill_reg_stored_to
[i
] = out
;
7300 reg_last_reload_reg
[nregno
] = rld
[r
].reg_rtx
;
7302 piecemeal
= (nregno
< FIRST_PSEUDO_REGISTER
7304 && inherit_piecemeal_p (r
, nregno
));
7306 /* If NREGNO is a hard register, it may occupy more than
7307 one register. If it does, say what is in the
7308 rest of the registers assuming that both registers
7309 agree on how many words the object takes. If not,
7310 invalidate the subsequent registers. */
7312 if (nregno
< FIRST_PSEUDO_REGISTER
)
7313 for (k
= 1; k
< nnr
; k
++)
7314 reg_last_reload_reg
[nregno
+ k
]
7316 ? regno_reg_rtx
[REGNO (rld
[r
].reg_rtx
) + k
]
7319 /* Now do the inverse operation. */
7320 for (k
= 0; k
< nr
; k
++)
7322 CLEAR_HARD_REG_BIT (reg_reloaded_dead
, i
+ k
);
7323 reg_reloaded_contents
[i
+ k
]
7324 = (nregno
>= FIRST_PSEUDO_REGISTER
|| !piecemeal
7327 reg_reloaded_insn
[i
+ k
] = insn
;
7328 SET_HARD_REG_BIT (reg_reloaded_valid
, i
+ k
);
7329 if (HARD_REGNO_CALL_PART_CLOBBERED (i
+ k
, GET_MODE (out
)))
7330 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered
, i
+ k
);
7334 /* Maybe the spill reg contains a copy of reload_in. Only do
7335 something if there will not be an output reload for
7336 the register being reloaded. */
7337 else if (rld
[r
].out_reg
== 0
7339 && ((REG_P (rld
[r
].in
)
7340 && REGNO (rld
[r
].in
) >= FIRST_PSEUDO_REGISTER
7341 && ! reg_has_output_reload
[REGNO (rld
[r
].in
)])
7342 || (REG_P (rld
[r
].in_reg
)
7343 && ! reg_has_output_reload
[REGNO (rld
[r
].in_reg
)]))
7344 && ! reg_set_p (rld
[r
].reg_rtx
, PATTERN (insn
)))
7351 if (REG_P (rld
[r
].in
)
7352 && REGNO (rld
[r
].in
) >= FIRST_PSEUDO_REGISTER
)
7354 else if (REG_P (rld
[r
].in_reg
))
7357 in
= XEXP (rld
[r
].in_reg
, 0);
7358 nregno
= REGNO (in
);
7360 nnr
= (nregno
>= FIRST_PSEUDO_REGISTER
? 1
7361 : hard_regno_nregs
[nregno
]
7362 [GET_MODE (rld
[r
].reg_rtx
)]);
7364 reg_last_reload_reg
[nregno
] = rld
[r
].reg_rtx
;
7366 piecemeal
= (nregno
< FIRST_PSEUDO_REGISTER
7368 && inherit_piecemeal_p (r
, nregno
));
7370 if (nregno
< FIRST_PSEUDO_REGISTER
)
7371 for (k
= 1; k
< nnr
; k
++)
7372 reg_last_reload_reg
[nregno
+ k
]
7374 ? regno_reg_rtx
[REGNO (rld
[r
].reg_rtx
) + k
]
7377 /* Unless we inherited this reload, show we haven't
7378 recently done a store.
7379 Previous stores of inherited auto_inc expressions
7380 also have to be discarded. */
7381 if (! reload_inherited
[r
]
7382 || (rld
[r
].out
&& ! rld
[r
].out_reg
))
7383 spill_reg_store
[i
] = 0;
7385 for (k
= 0; k
< nr
; k
++)
7387 CLEAR_HARD_REG_BIT (reg_reloaded_dead
, i
+ k
);
7388 reg_reloaded_contents
[i
+ k
]
7389 = (nregno
>= FIRST_PSEUDO_REGISTER
|| !piecemeal
7392 reg_reloaded_insn
[i
+ k
] = insn
;
7393 SET_HARD_REG_BIT (reg_reloaded_valid
, i
+ k
);
7394 if (HARD_REGNO_CALL_PART_CLOBBERED (i
+ k
, GET_MODE (in
)))
7395 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered
, i
+ k
);
7400 /* However, if part of the reload reaches the end, then we must
7401 invalidate the old info for the part that survives to the end. */
7402 else if (part_reaches_end
)
7404 for (k
= 0; k
< nr
; k
++)
7405 if (reload_reg_reaches_end_p (i
+ k
,
7407 rld
[r
].when_needed
))
7408 CLEAR_HARD_REG_BIT (reg_reloaded_valid
, i
+ k
);
7412 /* The following if-statement was #if 0'd in 1.34 (or before...).
7413 It's reenabled in 1.35 because supposedly nothing else
7414 deals with this problem. */
7416 /* If a register gets output-reloaded from a non-spill register,
7417 that invalidates any previous reloaded copy of it.
7418 But forget_old_reloads_1 won't get to see it, because
7419 it thinks only about the original insn. So invalidate it here.
7420 Also do the same thing for RELOAD_OTHER constraints where the
7421 output is discarded. */
7423 && ((rld
[r
].out
!= 0
7424 && (REG_P (rld
[r
].out
)
7425 || (MEM_P (rld
[r
].out
)
7426 && REG_P (rld
[r
].out_reg
))))
7427 || (rld
[r
].out
== 0 && rld
[r
].out_reg
7428 && REG_P (rld
[r
].out_reg
))))
7430 rtx out
= ((rld
[r
].out
&& REG_P (rld
[r
].out
))
7431 ? rld
[r
].out
: rld
[r
].out_reg
);
7432 int nregno
= REGNO (out
);
7433 if (nregno
>= FIRST_PSEUDO_REGISTER
)
7435 rtx src_reg
, store_insn
= NULL_RTX
;
7437 reg_last_reload_reg
[nregno
] = 0;
7439 /* If we can find a hard register that is stored, record
7440 the storing insn so that we may delete this insn with
7441 delete_output_reload. */
7442 src_reg
= rld
[r
].reg_rtx
;
7444 /* If this is an optional reload, try to find the source reg
7445 from an input reload. */
7448 rtx set
= single_set (insn
);
7449 if (set
&& SET_DEST (set
) == rld
[r
].out
)
7453 src_reg
= SET_SRC (set
);
7455 for (k
= 0; k
< n_reloads
; k
++)
7457 if (rld
[k
].in
== src_reg
)
7459 src_reg
= rld
[k
].reg_rtx
;
7466 store_insn
= new_spill_reg_store
[REGNO (src_reg
)];
7467 if (src_reg
&& REG_P (src_reg
)
7468 && REGNO (src_reg
) < FIRST_PSEUDO_REGISTER
)
7470 int src_regno
= REGNO (src_reg
);
7471 int nr
= hard_regno_nregs
[src_regno
][rld
[r
].mode
];
7472 /* The place where to find a death note varies with
7473 PRESERVE_DEATH_INFO_REGNO_P . The condition is not
7474 necessarily checked exactly in the code that moves
7475 notes, so just check both locations. */
7476 rtx note
= find_regno_note (insn
, REG_DEAD
, src_regno
);
7477 if (! note
&& store_insn
)
7478 note
= find_regno_note (store_insn
, REG_DEAD
, src_regno
);
7481 spill_reg_store
[src_regno
+ nr
] = store_insn
;
7482 spill_reg_stored_to
[src_regno
+ nr
] = out
;
7483 reg_reloaded_contents
[src_regno
+ nr
] = nregno
;
7484 reg_reloaded_insn
[src_regno
+ nr
] = store_insn
;
7485 CLEAR_HARD_REG_BIT (reg_reloaded_dead
, src_regno
+ nr
);
7486 SET_HARD_REG_BIT (reg_reloaded_valid
, src_regno
+ nr
);
7487 if (HARD_REGNO_CALL_PART_CLOBBERED (src_regno
+ nr
,
7488 GET_MODE (src_reg
)))
7489 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered
,
7491 SET_HARD_REG_BIT (reg_is_output_reload
, src_regno
+ nr
);
7493 SET_HARD_REG_BIT (reg_reloaded_died
, src_regno
);
7495 CLEAR_HARD_REG_BIT (reg_reloaded_died
, src_regno
);
7497 reg_last_reload_reg
[nregno
] = src_reg
;
7498 /* We have to set reg_has_output_reload here, or else
7499 forget_old_reloads_1 will clear reg_last_reload_reg
7501 reg_has_output_reload
[nregno
] = 1;
7506 int num_regs
= hard_regno_nregs
[nregno
][GET_MODE (out
)];
7508 while (num_regs
-- > 0)
7509 reg_last_reload_reg
[nregno
+ num_regs
] = 0;
7513 IOR_HARD_REG_SET (reg_reloaded_dead
, reg_reloaded_died
);
7516 /* Go through the motions to emit INSN and test if it is strictly valid.
7517 Return the emitted insn if valid, else return NULL. */
7520 emit_insn_if_valid_for_reload (rtx insn
)
7522 rtx last
= get_last_insn ();
7525 insn
= emit_insn (insn
);
7526 code
= recog_memoized (insn
);
7530 extract_insn (insn
);
7531 /* We want constrain operands to treat this insn strictly in its
7532 validity determination, i.e., the way it would after reload has
7534 if (constrain_operands (1))
7538 delete_insns_since (last
);
7542 /* Emit code to perform a reload from IN (which may be a reload register) to
7543 OUT (which may also be a reload register). IN or OUT is from operand
7544 OPNUM with reload type TYPE.
7546 Returns first insn emitted. */
7549 gen_reload (rtx out
, rtx in
, int opnum
, enum reload_type type
)
7551 rtx last
= get_last_insn ();
7554 /* If IN is a paradoxical SUBREG, remove it and try to put the
7555 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
7556 if (GET_CODE (in
) == SUBREG
7557 && (GET_MODE_SIZE (GET_MODE (in
))
7558 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in
))))
7559 && (tem
= gen_lowpart_common (GET_MODE (SUBREG_REG (in
)), out
)) != 0)
7560 in
= SUBREG_REG (in
), out
= tem
;
7561 else if (GET_CODE (out
) == SUBREG
7562 && (GET_MODE_SIZE (GET_MODE (out
))
7563 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out
))))
7564 && (tem
= gen_lowpart_common (GET_MODE (SUBREG_REG (out
)), in
)) != 0)
7565 out
= SUBREG_REG (out
), in
= tem
;
7567 /* How to do this reload can get quite tricky. Normally, we are being
7568 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
7569 register that didn't get a hard register. In that case we can just
7570 call emit_move_insn.
7572 We can also be asked to reload a PLUS that adds a register or a MEM to
7573 another register, constant or MEM. This can occur during frame pointer
7574 elimination and while reloading addresses. This case is handled by
7575 trying to emit a single insn to perform the add. If it is not valid,
7576 we use a two insn sequence.
7578 Or we can be asked to reload an unary operand that was a fragment of
7579 an addressing mode, into a register. If it isn't recognized as-is,
7580 we try making the unop operand and the reload-register the same:
7581 (set reg:X (unop:X expr:Y))
7582 -> (set reg:Y expr:Y) (set reg:X (unop:X reg:Y)).
7584 Finally, we could be called to handle an 'o' constraint by putting
7585 an address into a register. In that case, we first try to do this
7586 with a named pattern of "reload_load_address". If no such pattern
7587 exists, we just emit a SET insn and hope for the best (it will normally
7588 be valid on machines that use 'o').
7590 This entire process is made complex because reload will never
7591 process the insns we generate here and so we must ensure that
7592 they will fit their constraints and also by the fact that parts of
7593 IN might be being reloaded separately and replaced with spill registers.
7594 Because of this, we are, in some sense, just guessing the right approach
7595 here. The one listed above seems to work.
7597 ??? At some point, this whole thing needs to be rethought. */
7599 if (GET_CODE (in
) == PLUS
7600 && (REG_P (XEXP (in
, 0))
7601 || GET_CODE (XEXP (in
, 0)) == SUBREG
7602 || MEM_P (XEXP (in
, 0)))
7603 && (REG_P (XEXP (in
, 1))
7604 || GET_CODE (XEXP (in
, 1)) == SUBREG
7605 || CONSTANT_P (XEXP (in
, 1))
7606 || MEM_P (XEXP (in
, 1))))
7608 /* We need to compute the sum of a register or a MEM and another
7609 register, constant, or MEM, and put it into the reload
7610 register. The best possible way of doing this is if the machine
7611 has a three-operand ADD insn that accepts the required operands.
7613 The simplest approach is to try to generate such an insn and see if it
7614 is recognized and matches its constraints. If so, it can be used.
7616 It might be better not to actually emit the insn unless it is valid,
7617 but we need to pass the insn as an operand to `recog' and
7618 `extract_insn' and it is simpler to emit and then delete the insn if
7619 not valid than to dummy things up. */
7621 rtx op0
, op1
, tem
, insn
;
7624 op0
= find_replacement (&XEXP (in
, 0));
7625 op1
= find_replacement (&XEXP (in
, 1));
7627 /* Since constraint checking is strict, commutativity won't be
7628 checked, so we need to do that here to avoid spurious failure
7629 if the add instruction is two-address and the second operand
7630 of the add is the same as the reload reg, which is frequently
7631 the case. If the insn would be A = B + A, rearrange it so
7632 it will be A = A + B as constrain_operands expects. */
7634 if (REG_P (XEXP (in
, 1))
7635 && REGNO (out
) == REGNO (XEXP (in
, 1)))
7636 tem
= op0
, op0
= op1
, op1
= tem
;
7638 if (op0
!= XEXP (in
, 0) || op1
!= XEXP (in
, 1))
7639 in
= gen_rtx_PLUS (GET_MODE (in
), op0
, op1
);
7641 insn
= emit_insn_if_valid_for_reload (gen_rtx_SET (VOIDmode
, out
, in
));
7645 /* If that failed, we must use a conservative two-insn sequence.
7647 Use a move to copy one operand into the reload register. Prefer
7648 to reload a constant, MEM or pseudo since the move patterns can
7649 handle an arbitrary operand. If OP1 is not a constant, MEM or
7650 pseudo and OP1 is not a valid operand for an add instruction, then
7653 After reloading one of the operands into the reload register, add
7654 the reload register to the output register.
7656 If there is another way to do this for a specific machine, a
7657 DEFINE_PEEPHOLE should be specified that recognizes the sequence
7660 code
= (int) add_optab
->handlers
[(int) GET_MODE (out
)].insn_code
;
7662 if (CONSTANT_P (op1
) || MEM_P (op1
) || GET_CODE (op1
) == SUBREG
7664 && REGNO (op1
) >= FIRST_PSEUDO_REGISTER
)
7665 || (code
!= CODE_FOR_nothing
7666 && ! ((*insn_data
[code
].operand
[2].predicate
)
7667 (op1
, insn_data
[code
].operand
[2].mode
))))
7668 tem
= op0
, op0
= op1
, op1
= tem
;
7670 gen_reload (out
, op0
, opnum
, type
);
7672 /* If OP0 and OP1 are the same, we can use OUT for OP1.
7673 This fixes a problem on the 32K where the stack pointer cannot
7674 be used as an operand of an add insn. */
7676 if (rtx_equal_p (op0
, op1
))
7679 insn
= emit_insn_if_valid_for_reload (gen_add2_insn (out
, op1
));
7682 /* Add a REG_EQUIV note so that find_equiv_reg can find it. */
7684 = gen_rtx_EXPR_LIST (REG_EQUIV
, in
, REG_NOTES (insn
));
7688 /* If that failed, copy the address register to the reload register.
7689 Then add the constant to the reload register. */
7691 gen_reload (out
, op1
, opnum
, type
);
7692 insn
= emit_insn (gen_add2_insn (out
, op0
));
7693 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_EQUIV
, in
, REG_NOTES (insn
));
7696 #ifdef SECONDARY_MEMORY_NEEDED
7697 /* If we need a memory location to do the move, do it that way. */
7698 else if ((REG_P (in
) || GET_CODE (in
) == SUBREG
)
7699 && reg_or_subregno (in
) < FIRST_PSEUDO_REGISTER
7700 && (REG_P (out
) || GET_CODE (out
) == SUBREG
)
7701 && reg_or_subregno (out
) < FIRST_PSEUDO_REGISTER
7702 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (reg_or_subregno (in
)),
7703 REGNO_REG_CLASS (reg_or_subregno (out
)),
7706 /* Get the memory to use and rewrite both registers to its mode. */
7707 rtx loc
= get_secondary_mem (in
, GET_MODE (out
), opnum
, type
);
7709 if (GET_MODE (loc
) != GET_MODE (out
))
7710 out
= gen_rtx_REG (GET_MODE (loc
), REGNO (out
));
7712 if (GET_MODE (loc
) != GET_MODE (in
))
7713 in
= gen_rtx_REG (GET_MODE (loc
), REGNO (in
));
7715 gen_reload (loc
, in
, opnum
, type
);
7716 gen_reload (out
, loc
, opnum
, type
);
7719 else if (REG_P (out
) && UNARY_P (in
))
7726 op1
= find_replacement (&XEXP (in
, 0));
7727 if (op1
!= XEXP (in
, 0))
7728 in
= gen_rtx_fmt_e (GET_CODE (in
), GET_MODE (in
), op1
);
7730 /* First, try a plain SET. */
7731 set
= emit_insn_if_valid_for_reload (gen_rtx_SET (VOIDmode
, out
, in
));
7735 /* If that failed, move the inner operand to the reload
7736 register, and try the same unop with the inner expression
7737 replaced with the reload register. */
7739 if (GET_MODE (op1
) != GET_MODE (out
))
7740 out_moded
= gen_rtx_REG (GET_MODE (op1
), REGNO (out
));
7744 gen_reload (out_moded
, op1
, opnum
, type
);
7747 = gen_rtx_SET (VOIDmode
, out
,
7748 gen_rtx_fmt_e (GET_CODE (in
), GET_MODE (in
),
7750 insn
= emit_insn_if_valid_for_reload (insn
);
7754 = gen_rtx_EXPR_LIST (REG_EQUIV
, in
, REG_NOTES (insn
));
7758 fatal_insn ("Failure trying to reload:", set
);
7760 /* If IN is a simple operand, use gen_move_insn. */
7761 else if (OBJECT_P (in
) || GET_CODE (in
) == SUBREG
)
7762 emit_insn (gen_move_insn (out
, in
));
7764 #ifdef HAVE_reload_load_address
7765 else if (HAVE_reload_load_address
)
7766 emit_insn (gen_reload_load_address (out
, in
));
7769 /* Otherwise, just write (set OUT IN) and hope for the best. */
7771 emit_insn (gen_rtx_SET (VOIDmode
, out
, in
));
7773 /* Return the first insn emitted.
7774 We can not just return get_last_insn, because there may have
7775 been multiple instructions emitted. Also note that gen_move_insn may
7776 emit more than one insn itself, so we can not assume that there is one
7777 insn emitted per emit_insn_before call. */
7779 return last
? NEXT_INSN (last
) : get_insns ();
7782 /* Delete a previously made output-reload whose result we now believe
7783 is not needed. First we double-check.
7785 INSN is the insn now being processed.
7786 LAST_RELOAD_REG is the hard register number for which we want to delete
7787 the last output reload.
7788 J is the reload-number that originally used REG. The caller has made
7789 certain that reload J doesn't use REG any longer for input. */
7792 delete_output_reload (rtx insn
, int j
, int last_reload_reg
)
7794 rtx output_reload_insn
= spill_reg_store
[last_reload_reg
];
7795 rtx reg
= spill_reg_stored_to
[last_reload_reg
];
7798 int n_inherited
= 0;
7802 /* It is possible that this reload has been only used to set another reload
7803 we eliminated earlier and thus deleted this instruction too. */
7804 if (INSN_DELETED_P (output_reload_insn
))
7807 /* Get the raw pseudo-register referred to. */
7809 while (GET_CODE (reg
) == SUBREG
)
7810 reg
= SUBREG_REG (reg
);
7811 substed
= reg_equiv_memory_loc
[REGNO (reg
)];
7813 /* This is unsafe if the operand occurs more often in the current
7814 insn than it is inherited. */
7815 for (k
= n_reloads
- 1; k
>= 0; k
--)
7817 rtx reg2
= rld
[k
].in
;
7820 if (MEM_P (reg2
) || reload_override_in
[k
])
7821 reg2
= rld
[k
].in_reg
;
7823 if (rld
[k
].out
&& ! rld
[k
].out_reg
)
7824 reg2
= XEXP (rld
[k
].in_reg
, 0);
7826 while (GET_CODE (reg2
) == SUBREG
)
7827 reg2
= SUBREG_REG (reg2
);
7828 if (rtx_equal_p (reg2
, reg
))
7830 if (reload_inherited
[k
] || reload_override_in
[k
] || k
== j
)
7833 reg2
= rld
[k
].out_reg
;
7836 while (GET_CODE (reg2
) == SUBREG
)
7837 reg2
= XEXP (reg2
, 0);
7838 if (rtx_equal_p (reg2
, reg
))
7845 n_occurrences
= count_occurrences (PATTERN (insn
), reg
, 0);
7847 n_occurrences
+= count_occurrences (PATTERN (insn
),
7848 eliminate_regs (substed
, 0,
7850 if (n_occurrences
> n_inherited
)
7853 /* If the pseudo-reg we are reloading is no longer referenced
7854 anywhere between the store into it and here,
7855 and we're within the same basic block, then the value can only
7856 pass through the reload reg and end up here.
7857 Otherwise, give up--return. */
7858 for (i1
= NEXT_INSN (output_reload_insn
);
7859 i1
!= insn
; i1
= NEXT_INSN (i1
))
7861 if (NOTE_INSN_BASIC_BLOCK_P (i1
))
7863 if ((NONJUMP_INSN_P (i1
) || CALL_P (i1
))
7864 && reg_mentioned_p (reg
, PATTERN (i1
)))
7866 /* If this is USE in front of INSN, we only have to check that
7867 there are no more references than accounted for by inheritance. */
7868 while (NONJUMP_INSN_P (i1
) && GET_CODE (PATTERN (i1
)) == USE
)
7870 n_occurrences
+= rtx_equal_p (reg
, XEXP (PATTERN (i1
), 0)) != 0;
7871 i1
= NEXT_INSN (i1
);
7873 if (n_occurrences
<= n_inherited
&& i1
== insn
)
7879 /* We will be deleting the insn. Remove the spill reg information. */
7880 for (k
= hard_regno_nregs
[last_reload_reg
][GET_MODE (reg
)]; k
-- > 0; )
7882 spill_reg_store
[last_reload_reg
+ k
] = 0;
7883 spill_reg_stored_to
[last_reload_reg
+ k
] = 0;
7886 /* The caller has already checked that REG dies or is set in INSN.
7887 It has also checked that we are optimizing, and thus some
7888 inaccuracies in the debugging information are acceptable.
7889 So we could just delete output_reload_insn. But in some cases
7890 we can improve the debugging information without sacrificing
7891 optimization - maybe even improving the code: See if the pseudo
7892 reg has been completely replaced with reload regs. If so, delete
7893 the store insn and forget we had a stack slot for the pseudo. */
7894 if (rld
[j
].out
!= rld
[j
].in
7895 && REG_N_DEATHS (REGNO (reg
)) == 1
7896 && REG_N_SETS (REGNO (reg
)) == 1
7897 && REG_BASIC_BLOCK (REGNO (reg
)) >= 0
7898 && find_regno_note (insn
, REG_DEAD
, REGNO (reg
)))
7902 /* We know that it was used only between here and the beginning of
7903 the current basic block. (We also know that the last use before
7904 INSN was the output reload we are thinking of deleting, but never
7905 mind that.) Search that range; see if any ref remains. */
7906 for (i2
= PREV_INSN (insn
); i2
; i2
= PREV_INSN (i2
))
7908 rtx set
= single_set (i2
);
7910 /* Uses which just store in the pseudo don't count,
7911 since if they are the only uses, they are dead. */
7912 if (set
!= 0 && SET_DEST (set
) == reg
)
7917 if ((NONJUMP_INSN_P (i2
) || CALL_P (i2
))
7918 && reg_mentioned_p (reg
, PATTERN (i2
)))
7920 /* Some other ref remains; just delete the output reload we
7922 delete_address_reloads (output_reload_insn
, insn
);
7923 delete_insn (output_reload_insn
);
7928 /* Delete the now-dead stores into this pseudo. Note that this
7929 loop also takes care of deleting output_reload_insn. */
7930 for (i2
= PREV_INSN (insn
); i2
; i2
= PREV_INSN (i2
))
7932 rtx set
= single_set (i2
);
7934 if (set
!= 0 && SET_DEST (set
) == reg
)
7936 delete_address_reloads (i2
, insn
);
7944 /* For the debugging info, say the pseudo lives in this reload reg. */
7945 reg_renumber
[REGNO (reg
)] = REGNO (rld
[j
].reg_rtx
);
7946 alter_reg (REGNO (reg
), -1);
7950 delete_address_reloads (output_reload_insn
, insn
);
7951 delete_insn (output_reload_insn
);
7955 /* We are going to delete DEAD_INSN. Recursively delete loads of
7956 reload registers used in DEAD_INSN that are not used till CURRENT_INSN.
7957 CURRENT_INSN is being reloaded, so we have to check its reloads too. */
7959 delete_address_reloads (rtx dead_insn
, rtx current_insn
)
7961 rtx set
= single_set (dead_insn
);
7962 rtx set2
, dst
, prev
, next
;
7965 rtx dst
= SET_DEST (set
);
7967 delete_address_reloads_1 (dead_insn
, XEXP (dst
, 0), current_insn
);
7969 /* If we deleted the store from a reloaded post_{in,de}c expression,
7970 we can delete the matching adds. */
7971 prev
= PREV_INSN (dead_insn
);
7972 next
= NEXT_INSN (dead_insn
);
7973 if (! prev
|| ! next
)
7975 set
= single_set (next
);
7976 set2
= single_set (prev
);
7978 || GET_CODE (SET_SRC (set
)) != PLUS
|| GET_CODE (SET_SRC (set2
)) != PLUS
7979 || GET_CODE (XEXP (SET_SRC (set
), 1)) != CONST_INT
7980 || GET_CODE (XEXP (SET_SRC (set2
), 1)) != CONST_INT
)
7982 dst
= SET_DEST (set
);
7983 if (! rtx_equal_p (dst
, SET_DEST (set2
))
7984 || ! rtx_equal_p (dst
, XEXP (SET_SRC (set
), 0))
7985 || ! rtx_equal_p (dst
, XEXP (SET_SRC (set2
), 0))
7986 || (INTVAL (XEXP (SET_SRC (set
), 1))
7987 != -INTVAL (XEXP (SET_SRC (set2
), 1))))
7989 delete_related_insns (prev
);
7990 delete_related_insns (next
);
7993 /* Subfunction of delete_address_reloads: process registers found in X. */
7995 delete_address_reloads_1 (rtx dead_insn
, rtx x
, rtx current_insn
)
7997 rtx prev
, set
, dst
, i2
;
7999 enum rtx_code code
= GET_CODE (x
);
8003 const char *fmt
= GET_RTX_FORMAT (code
);
8004 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
8007 delete_address_reloads_1 (dead_insn
, XEXP (x
, i
), current_insn
);
8008 else if (fmt
[i
] == 'E')
8010 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
8011 delete_address_reloads_1 (dead_insn
, XVECEXP (x
, i
, j
),
8018 if (spill_reg_order
[REGNO (x
)] < 0)
8021 /* Scan backwards for the insn that sets x. This might be a way back due
8023 for (prev
= PREV_INSN (dead_insn
); prev
; prev
= PREV_INSN (prev
))
8025 code
= GET_CODE (prev
);
8026 if (code
== CODE_LABEL
|| code
== JUMP_INSN
)
8030 if (reg_set_p (x
, PATTERN (prev
)))
8032 if (reg_referenced_p (x
, PATTERN (prev
)))
8035 if (! prev
|| INSN_UID (prev
) < reload_first_uid
)
8037 /* Check that PREV only sets the reload register. */
8038 set
= single_set (prev
);
8041 dst
= SET_DEST (set
);
8043 || ! rtx_equal_p (dst
, x
))
8045 if (! reg_set_p (dst
, PATTERN (dead_insn
)))
8047 /* Check if DST was used in a later insn -
8048 it might have been inherited. */
8049 for (i2
= NEXT_INSN (dead_insn
); i2
; i2
= NEXT_INSN (i2
))
8055 if (reg_referenced_p (dst
, PATTERN (i2
)))
8057 /* If there is a reference to the register in the current insn,
8058 it might be loaded in a non-inherited reload. If no other
8059 reload uses it, that means the register is set before
8061 if (i2
== current_insn
)
8063 for (j
= n_reloads
- 1; j
>= 0; j
--)
8064 if ((rld
[j
].reg_rtx
== dst
&& reload_inherited
[j
])
8065 || reload_override_in
[j
] == dst
)
8067 for (j
= n_reloads
- 1; j
>= 0; j
--)
8068 if (rld
[j
].in
&& rld
[j
].reg_rtx
== dst
)
8077 /* If DST is still live at CURRENT_INSN, check if it is used for
8078 any reload. Note that even if CURRENT_INSN sets DST, we still
8079 have to check the reloads. */
8080 if (i2
== current_insn
)
8082 for (j
= n_reloads
- 1; j
>= 0; j
--)
8083 if ((rld
[j
].reg_rtx
== dst
&& reload_inherited
[j
])
8084 || reload_override_in
[j
] == dst
)
8086 /* ??? We can't finish the loop here, because dst might be
8087 allocated to a pseudo in this block if no reload in this
8088 block needs any of the classes containing DST - see
8089 spill_hard_reg. There is no easy way to tell this, so we
8090 have to scan till the end of the basic block. */
8092 if (reg_set_p (dst
, PATTERN (i2
)))
8096 delete_address_reloads_1 (prev
, SET_SRC (set
), current_insn
);
8097 reg_reloaded_contents
[REGNO (dst
)] = -1;
8101 /* Output reload-insns to reload VALUE into RELOADREG.
8102 VALUE is an autoincrement or autodecrement RTX whose operand
8103 is a register or memory location;
8104 so reloading involves incrementing that location.
8105 IN is either identical to VALUE, or some cheaper place to reload from.
8107 INC_AMOUNT is the number to increment or decrement by (always positive).
8108 This cannot be deduced from VALUE.
8110 Return the instruction that stores into RELOADREG. */
8113 inc_for_reload (rtx reloadreg
, rtx in
, rtx value
, int inc_amount
)
8115 /* REG or MEM to be copied and incremented. */
8116 rtx incloc
= XEXP (value
, 0);
8117 /* Nonzero if increment after copying. */
8118 int post
= (GET_CODE (value
) == POST_DEC
|| GET_CODE (value
) == POST_INC
);
8124 rtx real_in
= in
== value
? XEXP (in
, 0) : in
;
8126 /* No hard register is equivalent to this register after
8127 inc/dec operation. If REG_LAST_RELOAD_REG were nonzero,
8128 we could inc/dec that register as well (maybe even using it for
8129 the source), but I'm not sure it's worth worrying about. */
8131 reg_last_reload_reg
[REGNO (incloc
)] = 0;
8133 if (GET_CODE (value
) == PRE_DEC
|| GET_CODE (value
) == POST_DEC
)
8134 inc_amount
= -inc_amount
;
8136 inc
= GEN_INT (inc_amount
);
8138 /* If this is post-increment, first copy the location to the reload reg. */
8139 if (post
&& real_in
!= reloadreg
)
8140 emit_insn (gen_move_insn (reloadreg
, real_in
));
8144 /* See if we can directly increment INCLOC. Use a method similar to
8145 that in gen_reload. */
8147 last
= get_last_insn ();
8148 add_insn
= emit_insn (gen_rtx_SET (VOIDmode
, incloc
,
8149 gen_rtx_PLUS (GET_MODE (incloc
),
8152 code
= recog_memoized (add_insn
);
8155 extract_insn (add_insn
);
8156 if (constrain_operands (1))
8158 /* If this is a pre-increment and we have incremented the value
8159 where it lives, copy the incremented value to RELOADREG to
8160 be used as an address. */
8163 emit_insn (gen_move_insn (reloadreg
, incloc
));
8168 delete_insns_since (last
);
8171 /* If couldn't do the increment directly, must increment in RELOADREG.
8172 The way we do this depends on whether this is pre- or post-increment.
8173 For pre-increment, copy INCLOC to the reload register, increment it
8174 there, then save back. */
8178 if (in
!= reloadreg
)
8179 emit_insn (gen_move_insn (reloadreg
, real_in
));
8180 emit_insn (gen_add2_insn (reloadreg
, inc
));
8181 store
= emit_insn (gen_move_insn (incloc
, reloadreg
));
8186 Because this might be a jump insn or a compare, and because RELOADREG
8187 may not be available after the insn in an input reload, we must do
8188 the incrementation before the insn being reloaded for.
8190 We have already copied IN to RELOADREG. Increment the copy in
8191 RELOADREG, save that back, then decrement RELOADREG so it has
8192 the original value. */
8194 emit_insn (gen_add2_insn (reloadreg
, inc
));
8195 store
= emit_insn (gen_move_insn (incloc
, reloadreg
));
8196 emit_insn (gen_add2_insn (reloadreg
, GEN_INT (-inc_amount
)));
8204 add_auto_inc_notes (rtx insn
, rtx x
)
8206 enum rtx_code code
= GET_CODE (x
);
8210 if (code
== MEM
&& auto_inc_p (XEXP (x
, 0)))
8213 = gen_rtx_EXPR_LIST (REG_INC
, XEXP (XEXP (x
, 0), 0), REG_NOTES (insn
));
8217 /* Scan all the operand sub-expressions. */
8218 fmt
= GET_RTX_FORMAT (code
);
8219 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
8222 add_auto_inc_notes (insn
, XEXP (x
, i
));
8223 else if (fmt
[i
] == 'E')
8224 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
8225 add_auto_inc_notes (insn
, XVECEXP (x
, i
, j
));
8230 /* Copy EH notes from an insn to its reloads. */
8232 copy_eh_notes (rtx insn
, rtx x
)
8234 rtx eh_note
= find_reg_note (insn
, REG_EH_REGION
, NULL_RTX
);
8237 for (; x
!= 0; x
= NEXT_INSN (x
))
8239 if (may_trap_p (PATTERN (x
)))
8241 = gen_rtx_EXPR_LIST (REG_EH_REGION
, XEXP (eh_note
, 0),
8247 /* This is used by reload pass, that does emit some instructions after
8248 abnormal calls moving basic block end, but in fact it wants to emit
8249 them on the edge. Looks for abnormal call edges, find backward the
8250 proper call and fix the damage.
8252 Similar handle instructions throwing exceptions internally. */
8254 fixup_abnormal_edges (void)
8256 bool inserted
= false;
8264 /* Look for cases we are interested in - calls or instructions causing
8266 FOR_EACH_EDGE (e
, ei
, bb
->succs
)
8268 if (e
->flags
& EDGE_ABNORMAL_CALL
)
8270 if ((e
->flags
& (EDGE_ABNORMAL
| EDGE_EH
))
8271 == (EDGE_ABNORMAL
| EDGE_EH
))
8274 if (e
&& !CALL_P (BB_END (bb
))
8275 && !can_throw_internal (BB_END (bb
)))
8279 /* Get past the new insns generated. Allow notes, as the insns
8280 may be already deleted. */
8282 while ((NONJUMP_INSN_P (insn
) || NOTE_P (insn
))
8283 && !can_throw_internal (insn
)
8284 && insn
!= BB_HEAD (bb
))
8285 insn
= PREV_INSN (insn
);
8287 if (CALL_P (insn
) || can_throw_internal (insn
))
8291 stop
= NEXT_INSN (BB_END (bb
));
8293 insn
= NEXT_INSN (insn
);
8295 FOR_EACH_EDGE (e
, ei
, bb
->succs
)
8296 if (e
->flags
& EDGE_FALLTHRU
)
8299 while (insn
&& insn
!= stop
)
8301 next
= NEXT_INSN (insn
);
8306 /* Sometimes there's still the return value USE.
8307 If it's placed after a trapping call (i.e. that
8308 call is the last insn anyway), we have no fallthru
8309 edge. Simply delete this use and don't try to insert
8310 on the non-existent edge. */
8311 if (GET_CODE (PATTERN (insn
)) != USE
)
8313 /* We're not deleting it, we're moving it. */
8314 INSN_DELETED_P (insn
) = 0;
8315 PREV_INSN (insn
) = NULL_RTX
;
8316 NEXT_INSN (insn
) = NULL_RTX
;
8318 insert_insn_on_edge (insn
, e
);
8326 /* It may be that we don't find any such trapping insn. In this
8327 case we discovered quite late that the insn that had been
8328 marked as can_throw_internal in fact couldn't trap at all.
8329 So we should in fact delete the EH edges out of the block. */
8331 purge_dead_edges (bb
);
8335 /* We've possibly turned single trapping insn into multiple ones. */
8336 if (flag_non_call_exceptions
)
8339 blocks
= sbitmap_alloc (last_basic_block
);
8340 sbitmap_ones (blocks
);
8341 find_many_sub_basic_blocks (blocks
);
8345 commit_edge_insertions ();
8347 #ifdef ENABLE_CHECKING
8348 /* Verify that we didn't turn one trapping insn into many, and that
8349 we found and corrected all of the problems wrt fixups on the
8351 verify_flow_info ();