1 /* This file contains the definitions and documentation for the
2 Register Transfer Expressions (rtx's) that make up the
3 Register Transfer Language (rtl) used in the Back End of the GNU compiler.
4 Copyright (C) 1987-2017 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 3, or (at your option) any later
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
23 /* Expression definitions and descriptions for all targets are in this file.
24 Some will not be used for some targets.
26 The fields in the cpp macro call "DEF_RTL_EXPR()"
27 are used to create declarations in the C source of the compiler.
31 1. The internal name of the rtx used in the C source.
32 It is a tag in the enumeration "enum rtx_code" defined in "rtl.h".
33 By convention these are in UPPER_CASE.
35 2. The name of the rtx in the external ASCII format read by
36 read_rtx(), and printed by print_rtx().
37 These names are stored in rtx_name[].
38 By convention these are the internal (field 1) names in lower_case.
40 3. The print format, and type of each rtx->u.fld[] (field) in this rtx.
41 These formats are stored in rtx_format[].
42 The meaning of the formats is documented in front of this array in rtl.c
44 4. The class of the rtx. These are stored in rtx_class and are accessed
45 via the GET_RTX_CLASS macro. They are defined as follows:
48 an rtx code that can be used to represent a constant object
51 an rtx code that can be used to represent an object (e.g, REG, MEM)
53 an rtx code for a comparison (e.g, LT, GT)
55 an rtx code for a commutative comparison (e.g, EQ, NE, ORDERED)
57 an rtx code for a unary arithmetic expression (e.g, NEG, NOT)
59 an rtx code for a commutative binary operation (e.g,, PLUS, MULT)
61 an rtx code for a non-bitfield three input operation (IF_THEN_ELSE)
63 an rtx code for a non-commutative binary operation (e.g., MINUS, DIV)
65 an rtx code for a bit-field operation (ZERO_EXTRACT, SIGN_EXTRACT)
67 an rtx code for a machine insn (INSN, JUMP_INSN, CALL_INSN) or
68 data that will be output as assembly pseudo-ops (DEBUG_INSN)
70 an rtx code for something that matches in insns (e.g, MATCH_DUP)
72 an rtx code for autoincrement addressing modes (e.g. POST_DEC)
76 All of the expressions that appear only in machine descriptions,
77 not in RTL used by the compiler itself, are at the end of the file. */
79 /* Unknown, or no such operation; the enumeration constant should have
81 DEF_RTL_EXPR(UNKNOWN, "UnKnown", "*", RTX_EXTRA)
83 /* Used in the cselib routines to describe a value. Objects of this
84 kind are only allocated in cselib.c, in an alloc pool instead of in
85 GC memory. The only operand of a VALUE is a cselib_val.
86 var-tracking requires this to have a distinct integral value from
87 DECL codes in trees. */
88 DEF_RTL_EXPR(VALUE, "value", "0", RTX_OBJ)
90 /* The RTL generated for a DEBUG_EXPR_DECL. It links back to the
91 DEBUG_EXPR_DECL in the first operand. */
92 DEF_RTL_EXPR(DEBUG_EXPR, "debug_expr", "0", RTX_OBJ)
94 /* ---------------------------------------------------------------------
95 Expressions used in constructing lists.
96 --------------------------------------------------------------------- */
98 /* A linked list of expressions. */
99 DEF_RTL_EXPR(EXPR_LIST, "expr_list", "ee", RTX_EXTRA)
101 /* A linked list of instructions.
102 The insns are represented in print by their uids. */
103 DEF_RTL_EXPR(INSN_LIST, "insn_list", "ue", RTX_EXTRA)
105 /* A linked list of integers. */
106 DEF_RTL_EXPR(INT_LIST, "int_list", "ie", RTX_EXTRA)
108 /* SEQUENCE is used in late passes of the compiler to group insns for
109 one reason or another.
111 For example, after delay slot filling, branch instructions with filled
112 delay slots are represented as a SEQUENCE of length 1 + n_delay_slots,
113 with the branch instruction in XEXPVEC(seq, 0, 0) and the instructions
114 occupying the delay slots in the remaining XEXPVEC slots.
116 Another place where a SEQUENCE may appear, is in REG_FRAME_RELATED_EXPR
117 notes, to express complex operations that are not obvious from the insn
118 to which the REG_FRAME_RELATED_EXPR note is attached. In this usage of
119 SEQUENCE, the sequence vector slots do not hold real instructions but
120 only pseudo-instructions that can be translated to DWARF CFA expressions.
122 Some back ends also use SEQUENCE to group insns in bundles.
124 Much of the compiler infrastructure is not prepared to handle SEQUENCE
125 objects. Only passes after pass_free_cfg are expected to handle them. */
126 DEF_RTL_EXPR(SEQUENCE, "sequence", "E", RTX_EXTRA)
128 /* Represents a non-global base address. This is only used in alias.c. */
129 DEF_RTL_EXPR(ADDRESS, "address", "i", RTX_EXTRA)
131 /* ----------------------------------------------------------------------
132 Expression types used for things in the instruction chain.
134 All formats must start with "uu" to handle the chain.
135 Each insn expression holds an rtl instruction and its semantics
136 during back-end processing.
137 See macros in "rtl.h" for the meaning of each rtx->u.fld[].
139 ---------------------------------------------------------------------- */
141 /* An annotation for variable assignment tracking. */
142 DEF_RTL_EXPR(DEBUG_INSN, "debug_insn", "uuBeiie", RTX_INSN)
144 /* An instruction that cannot jump. */
145 DEF_RTL_EXPR(INSN, "insn", "uuBeiie", RTX_INSN)
147 /* An instruction that can possibly jump.
148 Fields ( rtx->u.fld[] ) have exact same meaning as INSN's. */
149 DEF_RTL_EXPR(JUMP_INSN, "jump_insn", "uuBeiie0", RTX_INSN)
151 /* An instruction that can possibly call a subroutine
152 but which will not change which instruction comes next
153 in the current function.
154 Field ( rtx->u.fld[8] ) is CALL_INSN_FUNCTION_USAGE.
155 All other fields ( rtx->u.fld[] ) have exact same meaning as INSN's. */
156 DEF_RTL_EXPR(CALL_INSN, "call_insn", "uuBeiiee", RTX_INSN)
158 /* Placeholder for tablejump JUMP_INSNs. The pattern of this kind
159 of rtx is always either an ADDR_VEC or an ADDR_DIFF_VEC. These
160 placeholders do not appear as real instructions inside a basic
161 block, but are considered active_insn_p instructions for historical
162 reasons, when jump table data was represented with JUMP_INSNs. */
163 DEF_RTL_EXPR(JUMP_TABLE_DATA, "jump_table_data", "uuBe0000", RTX_INSN)
165 /* A marker that indicates that control will not flow through. */
166 DEF_RTL_EXPR(BARRIER, "barrier", "uu00000", RTX_EXTRA)
168 /* Holds a label that is followed by instructions.
170 3: is used in jump.c for the use-count of the label.
171 4: is used in the sh backend.
172 5: is a number that is unique in the entire compilation.
173 6: is the user-given name of the label, if any. */
174 DEF_RTL_EXPR(CODE_LABEL, "code_label", "uuB00is", RTX_EXTRA)
176 /* Say where in the code a source line starts, for symbol table's sake.
178 3: note-specific data
180 5: unique number if insn_note == note_insn_deleted_label. */
181 DEF_RTL_EXPR(NOTE, "note", "uuB0ni", RTX_EXTRA)
183 /* ----------------------------------------------------------------------
184 Top level constituents of INSN, JUMP_INSN and CALL_INSN.
185 ---------------------------------------------------------------------- */
187 /* Conditionally execute code.
188 Operand 0 is the condition that if true, the code is executed.
189 Operand 1 is the code to be executed (typically a SET).
191 Semantics are that there are no side effects if the condition
192 is false. This pattern is created automatically by the if_convert
193 pass run after reload or by target-specific splitters. */
194 DEF_RTL_EXPR(COND_EXEC, "cond_exec", "ee", RTX_EXTRA)
196 /* Several operations to be done in parallel (perhaps under COND_EXEC). */
197 DEF_RTL_EXPR(PARALLEL, "parallel", "E", RTX_EXTRA)
199 /* A string that is passed through to the assembler as input.
200 One can obviously pass comments through by using the
201 assembler comment syntax.
202 These occur in an insn all by themselves as the PATTERN.
203 They also appear inside an ASM_OPERANDS
204 as a convenient way to hold a string. */
205 DEF_RTL_EXPR(ASM_INPUT, "asm_input", "si", RTX_EXTRA)
207 /* An assembler instruction with operands.
208 1st operand is the instruction template.
209 2nd operand is the constraint for the output.
210 3rd operand is the number of the output this expression refers to.
211 When an insn stores more than one value, a separate ASM_OPERANDS
212 is made for each output; this integer distinguishes them.
213 4th is a vector of values of input operands.
214 5th is a vector of modes and constraints for the input operands.
215 Each element is an ASM_INPUT containing a constraint string
216 and whose mode indicates the mode of the input operand.
217 6th is a vector of labels that may be branched to by the asm.
218 7th is the source line number. */
219 DEF_RTL_EXPR(ASM_OPERANDS, "asm_operands", "ssiEEEi", RTX_EXTRA)
221 /* A machine-specific operation.
222 1st operand is a vector of operands being used by the operation so that
223 any needed reloads can be done.
224 2nd operand is a unique value saying which of a number of machine-specific
225 operations is to be performed.
226 (Note that the vector must be the first operand because of the way that
227 genrecog.c record positions within an insn.)
229 UNSPEC can occur all by itself in a PATTERN, as a component of a PARALLEL,
230 or inside an expression.
231 UNSPEC by itself or as a component of a PARALLEL
232 is currently considered not deletable.
234 FIXME: Replace all uses of UNSPEC that appears by itself or as a component
235 of a PARALLEL with USE.
237 DEF_RTL_EXPR(UNSPEC, "unspec", "Ei", RTX_EXTRA)
239 /* Similar, but a volatile operation and one which may trap. */
240 DEF_RTL_EXPR(UNSPEC_VOLATILE, "unspec_volatile", "Ei", RTX_EXTRA)
242 /* ----------------------------------------------------------------------
243 Table jump addresses.
244 ---------------------------------------------------------------------- */
246 /* Vector of addresses, stored as full words.
247 Each element is a LABEL_REF to a CODE_LABEL whose address we want. */
248 DEF_RTL_EXPR(ADDR_VEC, "addr_vec", "E", RTX_EXTRA)
250 /* Vector of address differences X0 - BASE, X1 - BASE, ...
251 First operand is BASE; the vector contains the X's.
252 The machine mode of this rtx says how much space to leave
253 for each difference and is adjusted by branch shortening if
254 CASE_VECTOR_SHORTEN_MODE is defined.
255 The third and fourth operands store the target labels with the
256 minimum and maximum addresses respectively.
257 The fifth operand stores flags for use by branch shortening.
258 Set at the start of shorten_branches:
259 min_align: the minimum alignment for any of the target labels.
260 base_after_vec: true iff BASE is after the ADDR_DIFF_VEC.
261 min_after_vec: true iff minimum addr target label is after the ADDR_DIFF_VEC.
262 max_after_vec: true iff maximum addr target label is after the ADDR_DIFF_VEC.
263 min_after_base: true iff minimum address target label is after BASE.
264 max_after_base: true iff maximum address target label is after BASE.
265 Set by the actual branch shortening process:
266 offset_unsigned: true iff offsets have to be treated as unsigned.
267 scale: scaling that is necessary to make offsets fit into the mode.
269 The third, fourth and fifth operands are only valid when
270 CASE_VECTOR_SHORTEN_MODE is defined, and only in an optimizing
272 DEF_RTL_EXPR(ADDR_DIFF_VEC, "addr_diff_vec", "eEee0", RTX_EXTRA)
274 /* Memory prefetch, with attributes supported on some targets.
275 Operand 1 is the address of the memory to fetch.
276 Operand 2 is 1 for a write access, 0 otherwise.
277 Operand 3 is the level of temporal locality; 0 means there is no
278 temporal locality and 1, 2, and 3 are for increasing levels of temporal
281 The attributes specified by operands 2 and 3 are ignored for targets
282 whose prefetch instructions do not support them. */
283 DEF_RTL_EXPR(PREFETCH, "prefetch", "eee", RTX_EXTRA)
285 /* ----------------------------------------------------------------------
286 At the top level of an instruction (perhaps under PARALLEL).
287 ---------------------------------------------------------------------- */
290 Operand 1 is the location (REG, MEM, PC, CC0 or whatever) assigned to.
291 Operand 2 is the value stored there.
292 ALL assignment must use SET.
293 Instructions that do multiple assignments must use multiple SET,
295 DEF_RTL_EXPR(SET, "set", "ee", RTX_EXTRA)
297 /* Indicate something is used in a way that we don't want to explain.
298 For example, subroutine calls will use the register
299 in which the static chain is passed.
301 USE can not appear as an operand of other rtx except for PARALLEL.
302 USE is not deletable, as it indicates that the operand
303 is used in some unknown way. */
304 DEF_RTL_EXPR(USE, "use", "e", RTX_EXTRA)
306 /* Indicate something is clobbered in a way that we don't want to explain.
307 For example, subroutine calls will clobber some physical registers
308 (the ones that are by convention not saved).
310 CLOBBER can not appear as an operand of other rtx except for PARALLEL.
311 CLOBBER of a hard register appearing by itself (not within PARALLEL)
312 is considered undeletable before reload. */
313 DEF_RTL_EXPR(CLOBBER, "clobber", "e", RTX_EXTRA)
315 /* Call a subroutine.
316 Operand 1 is the address to call.
317 Operand 2 is the number of arguments. */
319 DEF_RTL_EXPR(CALL, "call", "ee", RTX_EXTRA)
321 /* Return from a subroutine. */
323 DEF_RTL_EXPR(RETURN, "return", "", RTX_EXTRA)
325 /* Like RETURN, but truly represents only a function return, while
326 RETURN may represent an insn that also performs other functions
327 of the function epilogue. Like RETURN, this may also occur in
328 conditional jumps. */
329 DEF_RTL_EXPR(SIMPLE_RETURN, "simple_return", "", RTX_EXTRA)
331 /* Special for EH return from subroutine. */
333 DEF_RTL_EXPR(EH_RETURN, "eh_return", "", RTX_EXTRA)
336 Operand 1 is the condition.
337 Operand 2 is the trap code.
338 For an unconditional trap, make the condition (const_int 1). */
339 DEF_RTL_EXPR(TRAP_IF, "trap_if", "ee", RTX_EXTRA)
341 /* ----------------------------------------------------------------------
342 Primitive values for use in expressions.
343 ---------------------------------------------------------------------- */
345 /* numeric integer constant */
346 DEF_RTL_EXPR(CONST_INT, "const_int", "w", RTX_CONST_OBJ)
348 /* numeric integer constant */
349 DEF_RTL_EXPR(CONST_WIDE_INT, "const_wide_int", "", RTX_CONST_OBJ)
351 /* fixed-point constant */
352 DEF_RTL_EXPR(CONST_FIXED, "const_fixed", "www", RTX_CONST_OBJ)
354 /* numeric floating point or integer constant. If the mode is
355 VOIDmode it is an int otherwise it has a floating point mode and a
356 floating point value. Operands hold the value. They are all 'w'
357 and there may be from 2 to 6; see real.h. */
358 DEF_RTL_EXPR(CONST_DOUBLE, "const_double", CONST_DOUBLE_FORMAT, RTX_CONST_OBJ)
360 /* Describes a vector constant. */
361 DEF_RTL_EXPR(CONST_VECTOR, "const_vector", "E", RTX_CONST_OBJ)
363 /* String constant. Used for attributes in machine descriptions and
364 for special cases in DWARF2 debug output. NOT used for source-
365 language string constants. */
366 DEF_RTL_EXPR(CONST_STRING, "const_string", "s", RTX_OBJ)
368 /* This is used to encapsulate an expression whose value is constant
369 (such as the sum of a SYMBOL_REF and a CONST_INT) so that it will be
370 recognized as a constant operand rather than by arithmetic instructions. */
372 DEF_RTL_EXPR(CONST, "const", "e", RTX_CONST_OBJ)
374 /* program counter. Ordinary jumps are represented
375 by a SET whose first operand is (PC). */
376 DEF_RTL_EXPR(PC, "pc", "", RTX_OBJ)
378 /* A register. The "operand" is the register number, accessed with
379 the REGNO macro. If this number is less than FIRST_PSEUDO_REGISTER
380 than a hardware register is being referred to. The second operand
381 points to a reg_attrs structure.
382 This rtx needs to have as many (or more) fields as a MEM, since we
383 can change REG rtx's into MEMs during reload. */
384 DEF_RTL_EXPR(REG, "reg", "r", RTX_OBJ)
386 /* A scratch register. This represents a register used only within a
387 single insn. It will be replaced by a REG during register allocation
388 or reload unless the constraint indicates that the register won't be
389 needed, in which case it can remain a SCRATCH. */
390 DEF_RTL_EXPR(SCRATCH, "scratch", "", RTX_OBJ)
392 /* A reference to a part of another value. The first operand is the
393 complete value and the second is the byte offset of the selected part. */
394 DEF_RTL_EXPR(SUBREG, "subreg", "ei", RTX_EXTRA)
396 /* This one-argument rtx is used for move instructions
397 that are guaranteed to alter only the low part of a destination.
398 Thus, (SET (SUBREG:HI (REG...)) (MEM:HI ...))
399 has an unspecified effect on the high part of REG,
400 but (SET (STRICT_LOW_PART (SUBREG:HI (REG...))) (MEM:HI ...))
401 is guaranteed to alter only the bits of REG that are in HImode.
403 The actual instruction used is probably the same in both cases,
404 but the register constraints may be tighter when STRICT_LOW_PART
407 DEF_RTL_EXPR(STRICT_LOW_PART, "strict_low_part", "e", RTX_EXTRA)
409 /* (CONCAT a b) represents the virtual concatenation of a and b
410 to make a value that has as many bits as a and b put together.
411 This is used for complex values. Normally it appears only
412 in DECL_RTLs and during RTL generation, but not in the insn chain. */
413 DEF_RTL_EXPR(CONCAT, "concat", "ee", RTX_OBJ)
415 /* (CONCATN [a1 a2 ... an]) represents the virtual concatenation of
416 all An to make a value. This is an extension of CONCAT to larger
417 number of components. Like CONCAT, it should not appear in the
418 insn chain. Every element of the CONCATN is the same size. */
419 DEF_RTL_EXPR(CONCATN, "concatn", "E", RTX_OBJ)
421 /* A memory location; operand is the address. The second operand is the
422 alias set to which this MEM belongs. We use `0' instead of `w' for this
423 field so that the field need not be specified in machine descriptions. */
424 DEF_RTL_EXPR(MEM, "mem", "e0", RTX_OBJ)
426 /* Reference to an assembler label in the code for this function.
427 The operand is a CODE_LABEL found in the insn chain. */
428 DEF_RTL_EXPR(LABEL_REF, "label_ref", "u", RTX_CONST_OBJ)
430 /* Reference to a named label:
431 Operand 0: label name
432 Operand 1: tree from which this symbol is derived, or null.
433 This is either a DECL node, or some kind of constant. */
434 DEF_RTL_EXPR(SYMBOL_REF, "symbol_ref", "s0", RTX_CONST_OBJ)
436 /* The condition code register is represented, in our imagination,
437 as a register holding a value that can be compared to zero.
438 In fact, the machine has already compared them and recorded the
439 results; but instructions that look at the condition code
440 pretend to be looking at the entire value and comparing it. */
441 DEF_RTL_EXPR(CC0, "cc0", "", RTX_OBJ)
443 /* ----------------------------------------------------------------------
444 Expressions for operators in an rtl pattern
445 ---------------------------------------------------------------------- */
447 /* if_then_else. This is used in representing ordinary
448 conditional jump instructions.
453 DEF_RTL_EXPR(IF_THEN_ELSE, "if_then_else", "eee", RTX_TERNARY)
455 /* Comparison, produces a condition code result. */
456 DEF_RTL_EXPR(COMPARE, "compare", "ee", RTX_BIN_ARITH)
459 DEF_RTL_EXPR(PLUS, "plus", "ee", RTX_COMM_ARITH)
461 /* Operand 0 minus operand 1. */
462 DEF_RTL_EXPR(MINUS, "minus", "ee", RTX_BIN_ARITH)
464 /* Minus operand 0. */
465 DEF_RTL_EXPR(NEG, "neg", "e", RTX_UNARY)
467 DEF_RTL_EXPR(MULT, "mult", "ee", RTX_COMM_ARITH)
469 /* Multiplication with signed saturation */
470 DEF_RTL_EXPR(SS_MULT, "ss_mult", "ee", RTX_COMM_ARITH)
471 /* Multiplication with unsigned saturation */
472 DEF_RTL_EXPR(US_MULT, "us_mult", "ee", RTX_COMM_ARITH)
474 /* Operand 0 divided by operand 1. */
475 DEF_RTL_EXPR(DIV, "div", "ee", RTX_BIN_ARITH)
476 /* Division with signed saturation */
477 DEF_RTL_EXPR(SS_DIV, "ss_div", "ee", RTX_BIN_ARITH)
478 /* Division with unsigned saturation */
479 DEF_RTL_EXPR(US_DIV, "us_div", "ee", RTX_BIN_ARITH)
481 /* Remainder of operand 0 divided by operand 1. */
482 DEF_RTL_EXPR(MOD, "mod", "ee", RTX_BIN_ARITH)
484 /* Unsigned divide and remainder. */
485 DEF_RTL_EXPR(UDIV, "udiv", "ee", RTX_BIN_ARITH)
486 DEF_RTL_EXPR(UMOD, "umod", "ee", RTX_BIN_ARITH)
488 /* Bitwise operations. */
489 DEF_RTL_EXPR(AND, "and", "ee", RTX_COMM_ARITH)
490 DEF_RTL_EXPR(IOR, "ior", "ee", RTX_COMM_ARITH)
491 DEF_RTL_EXPR(XOR, "xor", "ee", RTX_COMM_ARITH)
492 DEF_RTL_EXPR(NOT, "not", "e", RTX_UNARY)
495 0: value to be shifted.
496 1: number of bits. */
497 DEF_RTL_EXPR(ASHIFT, "ashift", "ee", RTX_BIN_ARITH) /* shift left */
498 DEF_RTL_EXPR(ROTATE, "rotate", "ee", RTX_BIN_ARITH) /* rotate left */
499 DEF_RTL_EXPR(ASHIFTRT, "ashiftrt", "ee", RTX_BIN_ARITH) /* arithmetic shift right */
500 DEF_RTL_EXPR(LSHIFTRT, "lshiftrt", "ee", RTX_BIN_ARITH) /* logical shift right */
501 DEF_RTL_EXPR(ROTATERT, "rotatert", "ee", RTX_BIN_ARITH) /* rotate right */
503 /* Minimum and maximum values of two operands. We need both signed and
504 unsigned forms. (We cannot use MIN for SMIN because it conflicts
505 with a macro of the same name.) The signed variants should be used
506 with floating point. Further, if both operands are zeros, or if either
507 operand is NaN, then it is unspecified which of the two operands is
508 returned as the result. */
510 DEF_RTL_EXPR(SMIN, "smin", "ee", RTX_COMM_ARITH)
511 DEF_RTL_EXPR(SMAX, "smax", "ee", RTX_COMM_ARITH)
512 DEF_RTL_EXPR(UMIN, "umin", "ee", RTX_COMM_ARITH)
513 DEF_RTL_EXPR(UMAX, "umax", "ee", RTX_COMM_ARITH)
515 /* These unary operations are used to represent incrementation
516 and decrementation as they occur in memory addresses.
517 The amount of increment or decrement are not represented
518 because they can be understood from the machine-mode of the
519 containing MEM. These operations exist in only two cases:
520 1. pushes onto the stack.
521 2. created automatically by the auto-inc-dec pass. */
522 DEF_RTL_EXPR(PRE_DEC, "pre_dec", "e", RTX_AUTOINC)
523 DEF_RTL_EXPR(PRE_INC, "pre_inc", "e", RTX_AUTOINC)
524 DEF_RTL_EXPR(POST_DEC, "post_dec", "e", RTX_AUTOINC)
525 DEF_RTL_EXPR(POST_INC, "post_inc", "e", RTX_AUTOINC)
527 /* These binary operations are used to represent generic address
528 side-effects in memory addresses, except for simple incrementation
529 or decrementation which use the above operations. They are
530 created automatically by the life_analysis pass in flow.c.
531 The first operand is a REG which is used as the address.
532 The second operand is an expression that is assigned to the
533 register, either before (PRE_MODIFY) or after (POST_MODIFY)
534 evaluating the address.
535 Currently, the compiler can only handle second operands of the
536 form (plus (reg) (reg)) and (plus (reg) (const_int)), where
537 the first operand of the PLUS has to be the same register as
538 the first operand of the *_MODIFY. */
539 DEF_RTL_EXPR(PRE_MODIFY, "pre_modify", "ee", RTX_AUTOINC)
540 DEF_RTL_EXPR(POST_MODIFY, "post_modify", "ee", RTX_AUTOINC)
542 /* Comparison operations. The ordered comparisons exist in two
543 flavors, signed and unsigned. */
544 DEF_RTL_EXPR(NE, "ne", "ee", RTX_COMM_COMPARE)
545 DEF_RTL_EXPR(EQ, "eq", "ee", RTX_COMM_COMPARE)
546 DEF_RTL_EXPR(GE, "ge", "ee", RTX_COMPARE)
547 DEF_RTL_EXPR(GT, "gt", "ee", RTX_COMPARE)
548 DEF_RTL_EXPR(LE, "le", "ee", RTX_COMPARE)
549 DEF_RTL_EXPR(LT, "lt", "ee", RTX_COMPARE)
550 DEF_RTL_EXPR(GEU, "geu", "ee", RTX_COMPARE)
551 DEF_RTL_EXPR(GTU, "gtu", "ee", RTX_COMPARE)
552 DEF_RTL_EXPR(LEU, "leu", "ee", RTX_COMPARE)
553 DEF_RTL_EXPR(LTU, "ltu", "ee", RTX_COMPARE)
555 /* Additional floating point unordered comparison flavors. */
556 DEF_RTL_EXPR(UNORDERED, "unordered", "ee", RTX_COMM_COMPARE)
557 DEF_RTL_EXPR(ORDERED, "ordered", "ee", RTX_COMM_COMPARE)
559 /* These are equivalent to unordered or ... */
560 DEF_RTL_EXPR(UNEQ, "uneq", "ee", RTX_COMM_COMPARE)
561 DEF_RTL_EXPR(UNGE, "unge", "ee", RTX_COMPARE)
562 DEF_RTL_EXPR(UNGT, "ungt", "ee", RTX_COMPARE)
563 DEF_RTL_EXPR(UNLE, "unle", "ee", RTX_COMPARE)
564 DEF_RTL_EXPR(UNLT, "unlt", "ee", RTX_COMPARE)
566 /* This is an ordered NE, ie !UNEQ, ie false for NaN. */
567 DEF_RTL_EXPR(LTGT, "ltgt", "ee", RTX_COMM_COMPARE)
569 /* Represents the result of sign-extending the sole operand.
570 The machine modes of the operand and of the SIGN_EXTEND expression
571 determine how much sign-extension is going on. */
572 DEF_RTL_EXPR(SIGN_EXTEND, "sign_extend", "e", RTX_UNARY)
574 /* Similar for zero-extension (such as unsigned short to int). */
575 DEF_RTL_EXPR(ZERO_EXTEND, "zero_extend", "e", RTX_UNARY)
577 /* Similar but here the operand has a wider mode. */
578 DEF_RTL_EXPR(TRUNCATE, "truncate", "e", RTX_UNARY)
580 /* Similar for extending floating-point values (such as SFmode to DFmode). */
581 DEF_RTL_EXPR(FLOAT_EXTEND, "float_extend", "e", RTX_UNARY)
582 DEF_RTL_EXPR(FLOAT_TRUNCATE, "float_truncate", "e", RTX_UNARY)
584 /* Conversion of fixed point operand to floating point value. */
585 DEF_RTL_EXPR(FLOAT, "float", "e", RTX_UNARY)
587 /* With fixed-point machine mode:
588 Conversion of floating point operand to fixed point value.
589 Value is defined only when the operand's value is an integer.
590 With floating-point machine mode (and operand with same mode):
591 Operand is rounded toward zero to produce an integer value
592 represented in floating point. */
593 DEF_RTL_EXPR(FIX, "fix", "e", RTX_UNARY)
595 /* Conversion of unsigned fixed point operand to floating point value. */
596 DEF_RTL_EXPR(UNSIGNED_FLOAT, "unsigned_float", "e", RTX_UNARY)
598 /* With fixed-point machine mode:
599 Conversion of floating point operand to *unsigned* fixed point value.
600 Value is defined only when the operand's value is an integer. */
601 DEF_RTL_EXPR(UNSIGNED_FIX, "unsigned_fix", "e", RTX_UNARY)
603 /* Conversions involving fractional fixed-point types without saturation,
605 fractional to fractional (of different precision),
606 signed integer to fractional,
607 fractional to signed integer,
608 floating point to fractional,
609 fractional to floating point.
610 NOTE: fractional can be either signed or unsigned for conversions. */
611 DEF_RTL_EXPR(FRACT_CONVERT, "fract_convert", "e", RTX_UNARY)
613 /* Conversions involving fractional fixed-point types and unsigned integer
614 without saturation, including:
615 unsigned integer to fractional,
616 fractional to unsigned integer.
617 NOTE: fractional can be either signed or unsigned for conversions. */
618 DEF_RTL_EXPR(UNSIGNED_FRACT_CONVERT, "unsigned_fract_convert", "e", RTX_UNARY)
620 /* Conversions involving fractional fixed-point types with saturation,
622 fractional to fractional (of different precision),
623 signed integer to fractional,
624 floating point to fractional.
625 NOTE: fractional can be either signed or unsigned for conversions. */
626 DEF_RTL_EXPR(SAT_FRACT, "sat_fract", "e", RTX_UNARY)
628 /* Conversions involving fractional fixed-point types and unsigned integer
629 with saturation, including:
630 unsigned integer to fractional.
631 NOTE: fractional can be either signed or unsigned for conversions. */
632 DEF_RTL_EXPR(UNSIGNED_SAT_FRACT, "unsigned_sat_fract", "e", RTX_UNARY)
635 DEF_RTL_EXPR(ABS, "abs", "e", RTX_UNARY)
638 DEF_RTL_EXPR(SQRT, "sqrt", "e", RTX_UNARY)
641 DEF_RTL_EXPR(BSWAP, "bswap", "e", RTX_UNARY)
643 /* Find first bit that is set.
644 Value is 1 + number of trailing zeros in the arg.,
646 DEF_RTL_EXPR(FFS, "ffs", "e", RTX_UNARY)
648 /* Count number of leading redundant sign bits (number of leading
649 sign bits minus one). */
650 DEF_RTL_EXPR(CLRSB, "clrsb", "e", RTX_UNARY)
652 /* Count leading zeros. */
653 DEF_RTL_EXPR(CLZ, "clz", "e", RTX_UNARY)
655 /* Count trailing zeros. */
656 DEF_RTL_EXPR(CTZ, "ctz", "e", RTX_UNARY)
658 /* Population count (number of 1 bits). */
659 DEF_RTL_EXPR(POPCOUNT, "popcount", "e", RTX_UNARY)
661 /* Population parity (number of 1 bits modulo 2). */
662 DEF_RTL_EXPR(PARITY, "parity", "e", RTX_UNARY)
664 /* Reference to a signed bit-field of specified size and position.
665 Operand 0 is the memory unit (usually SImode or QImode) which
666 contains the field's first bit. Operand 1 is the width, in bits.
667 Operand 2 is the number of bits in the memory unit before the
668 first bit of this field.
669 If BITS_BIG_ENDIAN is defined, the first bit is the msb and
670 operand 2 counts from the msb of the memory unit.
671 Otherwise, the first bit is the lsb and operand 2 counts from
672 the lsb of the memory unit.
673 This kind of expression can not appear as an lvalue in RTL. */
674 DEF_RTL_EXPR(SIGN_EXTRACT, "sign_extract", "eee", RTX_BITFIELD_OPS)
676 /* Similar for unsigned bit-field.
677 But note! This kind of expression _can_ appear as an lvalue. */
678 DEF_RTL_EXPR(ZERO_EXTRACT, "zero_extract", "eee", RTX_BITFIELD_OPS)
680 /* For RISC machines. These save memory when splitting insns. */
682 /* HIGH are the high-order bits of a constant expression. */
683 DEF_RTL_EXPR(HIGH, "high", "e", RTX_CONST_OBJ)
685 /* LO_SUM is the sum of a register and the low-order bits
686 of a constant expression. */
687 DEF_RTL_EXPR(LO_SUM, "lo_sum", "ee", RTX_OBJ)
689 /* Describes a merge operation between two vector values.
690 Operands 0 and 1 are the vectors to be merged, operand 2 is a bitmask
691 that specifies where the parts of the result are taken from. Set bits
692 indicate operand 0, clear bits indicate operand 1. The parts are defined
693 by the mode of the vectors. */
694 DEF_RTL_EXPR(VEC_MERGE, "vec_merge", "eee", RTX_TERNARY)
696 /* Describes an operation that selects parts of a vector.
697 Operands 0 is the source vector, operand 1 is a PARALLEL that contains
698 a CONST_INT for each of the subparts of the result vector, giving the
699 number of the source subpart that should be stored into it. */
700 DEF_RTL_EXPR(VEC_SELECT, "vec_select", "ee", RTX_BIN_ARITH)
702 /* Describes a vector concat operation. Operands 0 and 1 are the source
703 vectors, the result is a vector that is as long as operands 0 and 1
704 combined and is the concatenation of the two source vectors. */
705 DEF_RTL_EXPR(VEC_CONCAT, "vec_concat", "ee", RTX_BIN_ARITH)
707 /* Describes an operation that converts a small vector into a larger one by
708 duplicating the input values. The output vector mode must have the same
709 submodes as the input vector mode, and the number of output parts must be
710 an integer multiple of the number of input parts. */
711 DEF_RTL_EXPR(VEC_DUPLICATE, "vec_duplicate", "e", RTX_UNARY)
713 /* Creation of a vector in which element I has the value BASE + I * STEP,
714 where BASE is the first operand and STEP is the second. The result
715 must have a vector integer mode. */
716 DEF_RTL_EXPR(VEC_SERIES, "vec_series", "ee", RTX_BIN_ARITH)
718 /* Addition with signed saturation */
719 DEF_RTL_EXPR(SS_PLUS, "ss_plus", "ee", RTX_COMM_ARITH)
721 /* Addition with unsigned saturation */
722 DEF_RTL_EXPR(US_PLUS, "us_plus", "ee", RTX_COMM_ARITH)
724 /* Operand 0 minus operand 1, with signed saturation. */
725 DEF_RTL_EXPR(SS_MINUS, "ss_minus", "ee", RTX_BIN_ARITH)
727 /* Negation with signed saturation. */
728 DEF_RTL_EXPR(SS_NEG, "ss_neg", "e", RTX_UNARY)
729 /* Negation with unsigned saturation. */
730 DEF_RTL_EXPR(US_NEG, "us_neg", "e", RTX_UNARY)
732 /* Absolute value with signed saturation. */
733 DEF_RTL_EXPR(SS_ABS, "ss_abs", "e", RTX_UNARY)
735 /* Shift left with signed saturation. */
736 DEF_RTL_EXPR(SS_ASHIFT, "ss_ashift", "ee", RTX_BIN_ARITH)
738 /* Shift left with unsigned saturation. */
739 DEF_RTL_EXPR(US_ASHIFT, "us_ashift", "ee", RTX_BIN_ARITH)
741 /* Operand 0 minus operand 1, with unsigned saturation. */
742 DEF_RTL_EXPR(US_MINUS, "us_minus", "ee", RTX_BIN_ARITH)
744 /* Signed saturating truncate. */
745 DEF_RTL_EXPR(SS_TRUNCATE, "ss_truncate", "e", RTX_UNARY)
747 /* Unsigned saturating truncate. */
748 DEF_RTL_EXPR(US_TRUNCATE, "us_truncate", "e", RTX_UNARY)
750 /* Floating point multiply/add combined instruction. */
751 DEF_RTL_EXPR(FMA, "fma", "eee", RTX_TERNARY)
753 /* Information about the variable and its location. */
754 DEF_RTL_EXPR(VAR_LOCATION, "var_location", "te", RTX_EXTRA)
756 /* Used in VAR_LOCATION for a pointer to a decl that is no longer
758 DEF_RTL_EXPR(DEBUG_IMPLICIT_PTR, "debug_implicit_ptr", "t", RTX_OBJ)
760 /* Represents value that argument had on function entry. The
761 single argument is the DECL_INCOMING_RTL of the corresponding
763 DEF_RTL_EXPR(ENTRY_VALUE, "entry_value", "0", RTX_OBJ)
765 /* Used in VAR_LOCATION for a reference to a parameter that has
766 been optimized away completely. */
767 DEF_RTL_EXPR(DEBUG_PARAMETER_REF, "debug_parameter_ref", "t", RTX_OBJ)
769 /* All expressions from this point forward appear only in machine
771 #ifdef GENERATOR_FILE
773 /* Pattern-matching operators: */
775 /* Use the function named by the second arg (the string)
776 as a predicate; if matched, store the structure that was matched
777 in the operand table at index specified by the first arg (the integer).
778 If the second arg is the null string, the structure is just stored.
780 A third string argument indicates to the register allocator restrictions
781 on where the operand can be allocated.
783 If the target needs no restriction on any instruction this field should
786 The string is prepended by:
787 '=' to indicate the operand is only written to.
788 '+' to indicate the operand is both read and written to.
790 Each character in the string represents an allocable class for an operand.
791 'g' indicates the operand can be any valid class.
792 'i' indicates the operand can be immediate (in the instruction) data.
793 'r' indicates the operand can be in a register.
794 'm' indicates the operand can be in memory.
795 'o' a subset of the 'm' class. Those memory addressing modes that
796 can be offset at compile time (have a constant added to them).
798 Other characters indicate target dependent operand classes and
799 are described in each target's machine description.
801 For instructions with more than one operand, sets of classes can be
802 separated by a comma to indicate the appropriate multi-operand constraints.
803 There must be a 1 to 1 correspondence between these sets of classes in
804 all operands for an instruction.
806 DEF_RTL_EXPR(MATCH_OPERAND, "match_operand", "iss", RTX_MATCH)
808 /* Match a SCRATCH or a register. When used to generate rtl, a
809 SCRATCH is generated. As for MATCH_OPERAND, the mode specifies
810 the desired mode and the first argument is the operand number.
811 The second argument is the constraint. */
812 DEF_RTL_EXPR(MATCH_SCRATCH, "match_scratch", "is", RTX_MATCH)
814 /* Apply a predicate, AND match recursively the operands of the rtx.
815 Operand 0 is the operand-number, as in match_operand.
816 Operand 1 is a predicate to apply (as a string, a function name).
817 Operand 2 is a vector of expressions, each of which must match
818 one subexpression of the rtx this construct is matching. */
819 DEF_RTL_EXPR(MATCH_OPERATOR, "match_operator", "isE", RTX_MATCH)
821 /* Match a PARALLEL of arbitrary length. The predicate is applied
822 to the PARALLEL and the initial expressions in the PARALLEL are matched.
823 Operand 0 is the operand-number, as in match_operand.
824 Operand 1 is a predicate to apply to the PARALLEL.
825 Operand 2 is a vector of expressions, each of which must match the
826 corresponding element in the PARALLEL. */
827 DEF_RTL_EXPR(MATCH_PARALLEL, "match_parallel", "isE", RTX_MATCH)
829 /* Match only something equal to what is stored in the operand table
830 at the index specified by the argument. Use with MATCH_OPERAND. */
831 DEF_RTL_EXPR(MATCH_DUP, "match_dup", "i", RTX_MATCH)
833 /* Match only something equal to what is stored in the operand table
834 at the index specified by the argument. Use with MATCH_OPERATOR. */
835 DEF_RTL_EXPR(MATCH_OP_DUP, "match_op_dup", "iE", RTX_MATCH)
837 /* Match only something equal to what is stored in the operand table
838 at the index specified by the argument. Use with MATCH_PARALLEL. */
839 DEF_RTL_EXPR(MATCH_PAR_DUP, "match_par_dup", "iE", RTX_MATCH)
841 /* Appears only in define_predicate/define_special_predicate
842 expressions. Evaluates true only if the operand has an RTX code
843 from the set given by the argument (a comma-separated list). If the
844 second argument is present and nonempty, it is a sequence of digits
845 and/or letters which indicates the subexpression to test, using the
846 same syntax as genextract/genrecog's location strings: 0-9 for
847 XEXP (op, n), a-z for XVECEXP (op, 0, n); each character applies to
848 the result of the one before it. */
849 DEF_RTL_EXPR(MATCH_CODE, "match_code", "ss", RTX_MATCH)
851 /* Used to inject a C conditional expression into an .md file. It can
852 appear in a predicate definition or an attribute expression. */
853 DEF_RTL_EXPR(MATCH_TEST, "match_test", "s", RTX_MATCH)
855 /* Insn (and related) definitions. */
857 /* Definition of the pattern for one kind of instruction.
859 0: names this instruction.
860 If the name is the null string, the instruction is in the
861 machine description just to be recognized, and will never be emitted by
862 the tree to rtl expander.
864 2: is a string which is a C expression
865 giving an additional condition for recognizing this pattern.
866 A null string means no extra condition.
867 3: is the action to execute if this pattern is matched.
868 If this assembler code template starts with a * then it is a fragment of
869 C code to run to decide on a template to use. Otherwise, it is the
871 4: optionally, a vector of attributes for this insn.
873 DEF_RTL_EXPR(DEFINE_INSN, "define_insn", "sEsTV", RTX_EXTRA)
875 /* Definition of a peephole optimization.
876 1st operand: vector of insn patterns to match
877 2nd operand: C expression that must be true
878 3rd operand: template or C code to produce assembler output.
879 4: optionally, a vector of attributes for this insn.
881 This form is deprecated; use define_peephole2 instead. */
882 DEF_RTL_EXPR(DEFINE_PEEPHOLE, "define_peephole", "EsTV", RTX_EXTRA)
884 /* Definition of a split operation.
885 1st operand: insn pattern to match
886 2nd operand: C expression that must be true
887 3rd operand: vector of insn patterns to place into a SEQUENCE
888 4th operand: optionally, some C code to execute before generating the
889 insns. This might, for example, create some RTX's and store them in
890 elements of `recog_data.operand' for use by the vector of
892 (`operands' is an alias here for `recog_data.operand'). */
893 DEF_RTL_EXPR(DEFINE_SPLIT, "define_split", "EsES", RTX_EXTRA)
895 /* Definition of an insn and associated split.
896 This is the concatenation, with a few modifications, of a define_insn
897 and a define_split which share the same pattern.
899 0: names this instruction.
900 If the name is the null string, the instruction is in the
901 machine description just to be recognized, and will never be emitted by
902 the tree to rtl expander.
904 2: is a string which is a C expression
905 giving an additional condition for recognizing this pattern.
906 A null string means no extra condition.
907 3: is the action to execute if this pattern is matched.
908 If this assembler code template starts with a * then it is a fragment of
909 C code to run to decide on a template to use. Otherwise, it is the
911 4: C expression that must be true for split. This may start with "&&"
912 in which case the split condition is the logical and of the insn
913 condition and what follows the "&&" of this operand.
914 5: vector of insn patterns to place into a SEQUENCE
915 6: optionally, some C code to execute before generating the
916 insns. This might, for example, create some RTX's and store them in
917 elements of `recog_data.operand' for use by the vector of
919 (`operands' is an alias here for `recog_data.operand').
920 7: optionally, a vector of attributes for this insn. */
921 DEF_RTL_EXPR(DEFINE_INSN_AND_SPLIT, "define_insn_and_split", "sEsTsESV", RTX_EXTRA)
923 /* Definition of an RTL peephole operation.
924 Follows the same arguments as define_split. */
925 DEF_RTL_EXPR(DEFINE_PEEPHOLE2, "define_peephole2", "EsES", RTX_EXTRA)
927 /* Define how to generate multiple insns for a standard insn name.
928 1st operand: the insn name.
929 2nd operand: vector of insn-patterns.
930 Use match_operand to substitute an element of `recog_data.operand'.
931 3rd operand: C expression that must be true for this to be available.
932 This may not test any operands.
933 4th operand: Extra C code to execute before generating the insns.
934 This might, for example, create some RTX's and store them in
935 elements of `recog_data.operand' for use by the vector of
937 (`operands' is an alias here for `recog_data.operand').
938 5th: optionally, a vector of attributes for this expand. */
939 DEF_RTL_EXPR(DEFINE_EXPAND, "define_expand", "sEssV", RTX_EXTRA)
941 /* Define a requirement for delay slots.
942 1st operand: Condition involving insn attributes that, if true,
943 indicates that the insn requires the number of delay slots
945 2nd operand: Vector whose length is the three times the number of delay
947 Each entry gives three conditions, each involving attributes.
948 The first must be true for an insn to occupy that delay slot
949 location. The second is true for all insns that can be
950 annulled if the branch is true and the third is true for all
951 insns that can be annulled if the branch is false.
953 Multiple DEFINE_DELAYs may be present. They indicate differing
954 requirements for delay slots. */
955 DEF_RTL_EXPR(DEFINE_DELAY, "define_delay", "eE", RTX_EXTRA)
957 /* Define attribute computation for `asm' instructions. */
958 DEF_RTL_EXPR(DEFINE_ASM_ATTRIBUTES, "define_asm_attributes", "V", RTX_EXTRA)
960 /* Definition of a conditional execution meta operation. Automatically
961 generates new instances of DEFINE_INSN, selected by having attribute
962 "predicable" true. The new pattern will contain a COND_EXEC and the
963 predicate at top-level.
966 0: The predicate pattern. The top-level form should match a
967 relational operator. Operands should have only one alternative.
968 1: A C expression giving an additional condition for recognizing
969 the generated pattern.
970 2: A template or C code to produce assembler output.
971 3: A vector of attributes to append to the resulting cond_exec insn. */
972 DEF_RTL_EXPR(DEFINE_COND_EXEC, "define_cond_exec", "EssV", RTX_EXTRA)
974 /* Definition of an operand predicate. The difference between
975 DEFINE_PREDICATE and DEFINE_SPECIAL_PREDICATE is that genrecog will
976 not warn about a match_operand with no mode if it has a predicate
977 defined with DEFINE_SPECIAL_PREDICATE.
980 0: The name of the predicate.
981 1: A boolean expression which computes whether or not the predicate
982 matches. This expression can use IOR, AND, NOT, MATCH_OPERAND,
983 MATCH_CODE, and MATCH_TEST. It must be specific enough that genrecog
984 can calculate the set of RTX codes that can possibly match.
985 2: A C function body which must return true for the predicate to match.
986 Optional. Use this when the test is too complicated to fit into a
987 match_test expression. */
988 DEF_RTL_EXPR(DEFINE_PREDICATE, "define_predicate", "ses", RTX_EXTRA)
989 DEF_RTL_EXPR(DEFINE_SPECIAL_PREDICATE, "define_special_predicate", "ses", RTX_EXTRA)
991 /* Definition of a register operand constraint. This simply maps the
992 constraint string to a register class.
995 0: The name of the constraint (often, but not always, a single letter).
996 1: A C expression which evaluates to the appropriate register class for
997 this constraint. If this is not just a constant, it should look only
998 at -m switches and the like.
999 2: A docstring for this constraint, in Texinfo syntax; not currently
1000 used, in future will be incorporated into the manual's list of
1001 machine-specific operand constraints. */
1002 DEF_RTL_EXPR(DEFINE_REGISTER_CONSTRAINT, "define_register_constraint", "sss", RTX_EXTRA)
1004 /* Definition of a non-register operand constraint. These look at the
1005 operand and decide whether it fits the constraint.
1007 DEFINE_CONSTRAINT gets no special treatment if it fails to match.
1008 It is appropriate for constant-only constraints, and most others.
1010 DEFINE_MEMORY_CONSTRAINT tells reload that this constraint can be made
1011 to match, if it doesn't already, by converting the operand to the form
1012 (mem (reg X)) where X is a base register. It is suitable for constraints
1013 that describe a subset of all memory references.
1015 DEFINE_ADDRESS_CONSTRAINT tells reload that this constraint can be made
1016 to match, if it doesn't already, by converting the operand to the form
1017 (reg X) where X is a base register. It is suitable for constraints that
1018 describe a subset of all address references.
1020 When in doubt, use plain DEFINE_CONSTRAINT.
1023 0: The name of the constraint (often, but not always, a single letter).
1024 1: A docstring for this constraint, in Texinfo syntax; not currently
1025 used, in future will be incorporated into the manual's list of
1026 machine-specific operand constraints.
1027 2: A boolean expression which computes whether or not the constraint
1028 matches. It should follow the same rules as a define_predicate
1029 expression, including the bit about specifying the set of RTX codes
1030 that could possibly match. MATCH_TEST subexpressions may make use of
1032 `op' - the RTL object defining the operand.
1033 `mode' - the mode of `op'.
1034 `ival' - INTVAL(op), if op is a CONST_INT.
1035 `hval' - CONST_DOUBLE_HIGH(op), if op is an integer CONST_DOUBLE.
1036 `lval' - CONST_DOUBLE_LOW(op), if op is an integer CONST_DOUBLE.
1037 `rval' - CONST_DOUBLE_REAL_VALUE(op), if op is a floating-point
1039 Do not use ival/hval/lval/rval if op is not the appropriate kind of
1041 DEF_RTL_EXPR(DEFINE_CONSTRAINT, "define_constraint", "sse", RTX_EXTRA)
1042 DEF_RTL_EXPR(DEFINE_MEMORY_CONSTRAINT, "define_memory_constraint", "sse", RTX_EXTRA)
1043 DEF_RTL_EXPR(DEFINE_SPECIAL_MEMORY_CONSTRAINT, "define_special_memory_constraint", "sse", RTX_EXTRA)
1044 DEF_RTL_EXPR(DEFINE_ADDRESS_CONSTRAINT, "define_address_constraint", "sse", RTX_EXTRA)
1047 /* Constructions for CPU pipeline description described by NDFAs. */
1049 /* (define_cpu_unit string [string]) describes cpu functional
1050 units (separated by comma).
1052 1st operand: Names of cpu functional units.
1053 2nd operand: Name of automaton (see comments for DEFINE_AUTOMATON).
1055 All define_reservations, define_cpu_units, and
1056 define_query_cpu_units should have unique names which may not be
1058 DEF_RTL_EXPR(DEFINE_CPU_UNIT, "define_cpu_unit", "sS", RTX_EXTRA)
1060 /* (define_query_cpu_unit string [string]) describes cpu functional
1061 units analogously to define_cpu_unit. The reservation of such
1062 units can be queried for automaton state. */
1063 DEF_RTL_EXPR(DEFINE_QUERY_CPU_UNIT, "define_query_cpu_unit", "sS", RTX_EXTRA)
1065 /* (exclusion_set string string) means that each CPU functional unit
1066 in the first string can not be reserved simultaneously with any
1067 unit whose name is in the second string and vise versa. CPU units
1068 in the string are separated by commas. For example, it is useful
1069 for description CPU with fully pipelined floating point functional
1070 unit which can execute simultaneously only single floating point
1071 insns or only double floating point insns. All CPU functional
1072 units in a set should belong to the same automaton. */
1073 DEF_RTL_EXPR(EXCLUSION_SET, "exclusion_set", "ss", RTX_EXTRA)
1075 /* (presence_set string string) means that each CPU functional unit in
1076 the first string can not be reserved unless at least one of pattern
1077 of units whose names are in the second string is reserved. This is
1078 an asymmetric relation. CPU units or unit patterns in the strings
1079 are separated by commas. Pattern is one unit name or unit names
1080 separated by white-spaces.
1082 For example, it is useful for description that slot1 is reserved
1083 after slot0 reservation for a VLIW processor. We could describe it
1084 by the following construction
1086 (presence_set "slot1" "slot0")
1088 Or slot1 is reserved only after slot0 and unit b0 reservation. In
1089 this case we could write
1091 (presence_set "slot1" "slot0 b0")
1093 All CPU functional units in a set should belong to the same
1095 DEF_RTL_EXPR(PRESENCE_SET, "presence_set", "ss", RTX_EXTRA)
1097 /* (final_presence_set string string) is analogous to `presence_set'.
1098 The difference between them is when checking is done. When an
1099 instruction is issued in given automaton state reflecting all
1100 current and planned unit reservations, the automaton state is
1101 changed. The first state is a source state, the second one is a
1102 result state. Checking for `presence_set' is done on the source
1103 state reservation, checking for `final_presence_set' is done on the
1104 result reservation. This construction is useful to describe a
1105 reservation which is actually two subsequent reservations. For
1108 (presence_set "slot1" "slot0")
1110 the following insn will be never issued (because slot1 requires
1111 slot0 which is absent in the source state).
1113 (define_reservation "insn_and_nop" "slot0 + slot1")
1115 but it can be issued if we use analogous `final_presence_set'. */
1116 DEF_RTL_EXPR(FINAL_PRESENCE_SET, "final_presence_set", "ss", RTX_EXTRA)
1118 /* (absence_set string string) means that each CPU functional unit in
1119 the first string can be reserved only if each pattern of units
1120 whose names are in the second string is not reserved. This is an
1121 asymmetric relation (actually exclusion set is analogous to this
1122 one but it is symmetric). CPU units or unit patterns in the string
1123 are separated by commas. Pattern is one unit name or unit names
1124 separated by white-spaces.
1126 For example, it is useful for description that slot0 can not be
1127 reserved after slot1 or slot2 reservation for a VLIW processor. We
1128 could describe it by the following construction
1130 (absence_set "slot2" "slot0, slot1")
1132 Or slot2 can not be reserved if slot0 and unit b0 are reserved or
1133 slot1 and unit b1 are reserved . In this case we could write
1135 (absence_set "slot2" "slot0 b0, slot1 b1")
1137 All CPU functional units in a set should to belong the same
1139 DEF_RTL_EXPR(ABSENCE_SET, "absence_set", "ss", RTX_EXTRA)
1141 /* (final_absence_set string string) is analogous to `absence_set' but
1142 checking is done on the result (state) reservation. See comments
1143 for `final_presence_set'. */
1144 DEF_RTL_EXPR(FINAL_ABSENCE_SET, "final_absence_set", "ss", RTX_EXTRA)
1146 /* (define_bypass number out_insn_names in_insn_names) names bypass
1147 with given latency (the first number) from insns given by the first
1148 string (see define_insn_reservation) into insns given by the second
1149 string. Insn names in the strings are separated by commas. The
1150 third operand is optional name of function which is additional
1151 guard for the bypass. The function will get the two insns as
1152 parameters. If the function returns zero the bypass will be
1153 ignored for this case. Additional guard is necessary to recognize
1154 complicated bypasses, e.g. when consumer is load address. If there
1155 are more one bypass with the same output and input insns, the
1156 chosen bypass is the first bypass with a guard in description whose
1157 guard function returns nonzero. If there is no such bypass, then
1158 bypass without the guard function is chosen. */
1159 DEF_RTL_EXPR(DEFINE_BYPASS, "define_bypass", "issS", RTX_EXTRA)
1161 /* (define_automaton string) describes names of automata generated and
1162 used for pipeline hazards recognition. The names are separated by
1163 comma. Actually it is possibly to generate the single automaton
1164 but unfortunately it can be very large. If we use more one
1165 automata, the summary size of the automata usually is less than the
1166 single one. The automaton name is used in define_cpu_unit and
1167 define_query_cpu_unit. All automata should have unique names. */
1168 DEF_RTL_EXPR(DEFINE_AUTOMATON, "define_automaton", "s", RTX_EXTRA)
1170 /* (automata_option string) describes option for generation of
1171 automata. Currently there are the following options:
1173 o "no-minimization" which makes no minimization of automata. This
1174 is only worth to do when we are debugging the description and
1175 need to look more accurately at reservations of states.
1177 o "time" which means printing additional time statistics about
1178 generation of automata.
1180 o "v" which means generation of file describing the result
1181 automata. The file has suffix `.dfa' and can be used for the
1182 description verification and debugging.
1184 o "w" which means generation of warning instead of error for
1185 non-critical errors.
1187 o "ndfa" which makes nondeterministic finite state automata.
1189 o "progress" which means output of a progress bar showing how many
1190 states were generated so far for automaton being processed. */
1191 DEF_RTL_EXPR(AUTOMATA_OPTION, "automata_option", "s", RTX_EXTRA)
1193 /* (define_reservation string string) names reservation (the first
1194 string) of cpu functional units (the 2nd string). Sometimes unit
1195 reservations for different insns contain common parts. In such
1196 case, you can describe common part and use its name (the 1st
1197 parameter) in regular expression in define_insn_reservation. All
1198 define_reservations, define_cpu_units, and define_query_cpu_units
1199 should have unique names which may not be "nothing". */
1200 DEF_RTL_EXPR(DEFINE_RESERVATION, "define_reservation", "ss", RTX_EXTRA)
1202 /* (define_insn_reservation name default_latency condition regexpr)
1203 describes reservation of cpu functional units (the 3nd operand) for
1204 instruction which is selected by the condition (the 2nd parameter).
1205 The first parameter is used for output of debugging information.
1206 The reservations are described by a regular expression according
1207 the following syntax:
1209 regexp = regexp "," oneof
1212 oneof = oneof "|" allof
1215 allof = allof "+" repeat
1218 repeat = element "*" number
1221 element = cpu_function_unit_name
1227 1. "," is used for describing start of the next cycle in
1230 2. "|" is used for describing the reservation described by the
1231 first regular expression *or* the reservation described by the
1232 second regular expression *or* etc.
1234 3. "+" is used for describing the reservation described by the
1235 first regular expression *and* the reservation described by the
1236 second regular expression *and* etc.
1238 4. "*" is used for convenience and simply means sequence in
1239 which the regular expression are repeated NUMBER times with
1240 cycle advancing (see ",").
1242 5. cpu functional unit name which means its reservation.
1244 6. reservation name -- see define_reservation.
1246 7. string "nothing" means no units reservation. */
1248 DEF_RTL_EXPR(DEFINE_INSN_RESERVATION, "define_insn_reservation", "sies", RTX_EXTRA)
1250 /* Expressions used for insn attributes. */
1252 /* Definition of an insn attribute.
1253 1st operand: name of the attribute
1254 2nd operand: comma-separated list of possible attribute values
1255 3rd operand: expression for the default value of the attribute. */
1256 DEF_RTL_EXPR(DEFINE_ATTR, "define_attr", "sse", RTX_EXTRA)
1258 /* Definition of an insn attribute that uses an existing enumerated type.
1259 1st operand: name of the attribute
1260 2nd operand: the name of the enumerated type
1261 3rd operand: expression for the default value of the attribute. */
1262 DEF_RTL_EXPR(DEFINE_ENUM_ATTR, "define_enum_attr", "sse", RTX_EXTRA)
1264 /* Marker for the name of an attribute. */
1265 DEF_RTL_EXPR(ATTR, "attr", "s", RTX_EXTRA)
1267 /* For use in the last (optional) operand of DEFINE_INSN or DEFINE_PEEPHOLE and
1268 in DEFINE_ASM_INSN to specify an attribute to assign to insns matching that
1271 (set_attr "name" "value") is equivalent to
1272 (set (attr "name") (const_string "value")) */
1273 DEF_RTL_EXPR(SET_ATTR, "set_attr", "ss", RTX_EXTRA)
1275 /* In the last operand of DEFINE_INSN and DEFINE_PEEPHOLE, this can be used to
1276 specify that attribute values are to be assigned according to the
1277 alternative matched.
1279 The following three expressions are equivalent:
1281 (set (attr "att") (cond [(eq_attrq "alternative" "1") (const_string "a1")
1282 (eq_attrq "alternative" "2") (const_string "a2")]
1283 (const_string "a3")))
1284 (set_attr_alternative "att" [(const_string "a1") (const_string "a2")
1285 (const_string "a3")])
1286 (set_attr "att" "a1,a2,a3")
1288 DEF_RTL_EXPR(SET_ATTR_ALTERNATIVE, "set_attr_alternative", "sE", RTX_EXTRA)
1290 /* A conditional expression true if the value of the specified attribute of
1291 the current insn equals the specified value. The first operand is the
1292 attribute name and the second is the comparison value. */
1293 DEF_RTL_EXPR(EQ_ATTR, "eq_attr", "ss", RTX_EXTRA)
1295 /* A special case of the above representing a set of alternatives. The first
1296 operand is bitmap of the set, the second one is the default value. */
1297 DEF_RTL_EXPR(EQ_ATTR_ALT, "eq_attr_alt", "ii", RTX_EXTRA)
1299 /* A conditional expression which is true if the specified flag is
1300 true for the insn being scheduled in reorg.
1302 genattr.c defines the following flags which can be tested by
1303 (attr_flag "foo") expressions in eligible_for_delay: forward, backward. */
1305 DEF_RTL_EXPR (ATTR_FLAG, "attr_flag", "s", RTX_EXTRA)
1307 /* General conditional. The first operand is a vector composed of pairs of
1308 expressions. The first element of each pair is evaluated, in turn.
1309 The value of the conditional is the second expression of the first pair
1310 whose first expression evaluates nonzero. If none of the expressions is
1311 true, the second operand will be used as the value of the conditional. */
1312 DEF_RTL_EXPR(COND, "cond", "Ee", RTX_EXTRA)
1314 /* Definition of a pattern substitution meta operation on a DEFINE_EXPAND
1315 or a DEFINE_INSN. Automatically generates new instances of DEFINE_INSNs
1316 that match the substitution pattern.
1319 0: The name of the substitition template.
1320 1: Input template to match to see if a substitution is applicable.
1321 2: A C expression giving an additional condition for the generated
1322 new define_expand or define_insn.
1323 3: Output tempalate to generate via substitution.
1325 Within a DEFINE_SUBST template, the meaning of some RTL expressions is
1326 different from their usual interpretation: a MATCH_OPERAND matches any
1327 expression tree with matching machine mode or with VOIDmode. Likewise,
1328 MATCH_OP_DUP and MATCH_DUP match more liberally in a DEFINE_SUBST than
1329 in other RTL expressions. MATCH_OPERATOR matches all common operators
1330 but also UNSPEC, UNSPEC_VOLATILE, and MATCH_OPERATORS from the input
1331 DEFINE_EXPAND or DEFINE_INSN. */
1332 DEF_RTL_EXPR(DEFINE_SUBST, "define_subst", "sEsE", RTX_EXTRA)
1334 /* Substitution attribute to apply a DEFINE_SUBST to a pattern.
1337 0: The name of the subst-attribute.
1338 1: The name of the DEFINE_SUBST to be applied for this attribute.
1339 2: String to substitute for the subst-attribute name in the pattern
1340 name, for the case that the DEFINE_SUBST is not applied (i.e. the
1341 unmodified version of the pattern).
1342 3: String to substitute for the subst-attribute name in the pattern
1343 name, for the case that the DEFINE_SUBST is applied to the patten.
1345 The use of DEFINE_SUBST and DEFINE_SUBST_ATTR is explained in the
1346 GCC internals manual, under "RTL Templates Transformations". */
1347 DEF_RTL_EXPR(DEFINE_SUBST_ATTR, "define_subst_attr", "ssss", RTX_EXTRA)
1349 #endif /* GENERATOR_FILE */
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