1 /* This file contains the definitions and documentation for the
2 Register Transfer Expressions (rtx's) that make up the
3 Register Transfer Language (rtl) used in the Back End of the GNU compiler.
4 Copyright (C) 1987, 1988, 1992, 1994, 1995, 1997, 1998, 1999, 2000, 2004,
5 2005, 2006, 2007, 2008, 2009
6 Free Software Foundation, Inc.
8 This file is part of GCC.
10 GCC is free software; you can redistribute it and/or modify it under
11 the terms of the GNU General Public License as published by the Free
12 Software Foundation; either version 3, or (at your option) any later
15 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
16 WARRANTY; without even the implied warranty of MERCHANTABILITY or
17 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING3. If not see
22 <http://www.gnu.org/licenses/>. */
25 /* Expression definitions and descriptions for all targets are in this file.
26 Some will not be used for some targets.
28 The fields in the cpp macro call "DEF_RTL_EXPR()"
29 are used to create declarations in the C source of the compiler.
33 1. The internal name of the rtx used in the C source.
34 It is a tag in the enumeration "enum rtx_code" defined in "rtl.h".
35 By convention these are in UPPER_CASE.
37 2. The name of the rtx in the external ASCII format read by
38 read_rtx(), and printed by print_rtx().
39 These names are stored in rtx_name[].
40 By convention these are the internal (field 1) names in lower_case.
42 3. The print format, and type of each rtx->u.fld[] (field) in this rtx.
43 These formats are stored in rtx_format[].
44 The meaning of the formats is documented in front of this array in rtl.c
46 4. The class of the rtx. These are stored in rtx_class and are accessed
47 via the GET_RTX_CLASS macro. They are defined as follows:
50 an rtx code that can be used to represent a constant object
53 an rtx code that can be used to represent an object (e.g, REG, MEM)
55 an rtx code for a comparison (e.g, LT, GT)
57 an rtx code for a commutative comparison (e.g, EQ, NE, ORDERED)
59 an rtx code for a unary arithmetic expression (e.g, NEG, NOT)
61 an rtx code for a commutative binary operation (e.g,, PLUS, MULT)
63 an rtx code for a non-bitfield three input operation (IF_THEN_ELSE)
65 an rtx code for a non-commutative binary operation (e.g., MINUS, DIV)
67 an rtx code for a bit-field operation (ZERO_EXTRACT, SIGN_EXTRACT)
69 an rtx code for a machine insn (INSN, JUMP_INSN, CALL_INSN)
71 an rtx code for something that matches in insns (e.g, MATCH_DUP)
73 an rtx code for autoincrement addressing modes (e.g. POST_DEC)
77 All of the expressions that appear only in machine descriptions,
78 not in RTL used by the compiler itself, are at the end of the file. */
80 /* Unknown, or no such operation; the enumeration constant should have
82 DEF_RTL_EXPR(UNKNOWN, "UnKnown", "*", RTX_EXTRA)
84 /* Used in the cselib routines to describe a value. Objects of this
85 kind are only allocated in cselib.c, in an alloc pool instead of in
86 GC memory. The only operand of a VALUE is a cselib_val_struct.
87 var-tracking requires this to have a distinct integral value from
88 DECL codes in trees. */
89 DEF_RTL_EXPR(VALUE, "value", "0", RTX_OBJ)
91 /* ---------------------------------------------------------------------
92 Expressions used in constructing lists.
93 --------------------------------------------------------------------- */
95 /* a linked list of expressions */
96 DEF_RTL_EXPR(EXPR_LIST, "expr_list", "ee", RTX_EXTRA)
98 /* a linked list of instructions.
99 The insns are represented in print by their uids. */
100 DEF_RTL_EXPR(INSN_LIST, "insn_list", "ue", RTX_EXTRA)
102 /* SEQUENCE appears in the result of a `gen_...' function
103 for a DEFINE_EXPAND that wants to make several insns.
104 Its elements are the bodies of the insns that should be made.
105 `emit_insn' takes the SEQUENCE apart and makes separate insns. */
106 DEF_RTL_EXPR(SEQUENCE, "sequence", "E", RTX_EXTRA)
108 /* Refers to the address of its argument. This is only used in alias.c. */
109 DEF_RTL_EXPR(ADDRESS, "address", "e", RTX_MATCH)
111 /* ----------------------------------------------------------------------
112 Expression types used for things in the instruction chain.
114 All formats must start with "iuu" to handle the chain.
115 Each insn expression holds an rtl instruction and its semantics
116 during back-end processing.
117 See macros's in "rtl.h" for the meaning of each rtx->u.fld[].
119 ---------------------------------------------------------------------- */
121 /* An annotation for variable assignment tracking. */
122 DEF_RTL_EXPR(DEBUG_INSN, "debug_insn", "iuuBieie", RTX_INSN)
124 /* An instruction that cannot jump. */
125 DEF_RTL_EXPR(INSN, "insn", "iuuBieie", RTX_INSN)
127 /* An instruction that can possibly jump.
128 Fields ( rtx->u.fld[] ) have exact same meaning as INSN's. */
129 DEF_RTL_EXPR(JUMP_INSN, "jump_insn", "iuuBieie0", RTX_INSN)
131 /* An instruction that can possibly call a subroutine
132 but which will not change which instruction comes next
133 in the current function.
134 Field ( rtx->u.fld[8] ) is CALL_INSN_FUNCTION_USAGE.
135 All other fields ( rtx->u.fld[] ) have exact same meaning as INSN's. */
136 DEF_RTL_EXPR(CALL_INSN, "call_insn", "iuuBieiee", RTX_INSN)
138 /* A marker that indicates that control will not flow through. */
139 DEF_RTL_EXPR(BARRIER, "barrier", "iuu00000", RTX_EXTRA)
141 /* Holds a label that is followed by instructions.
143 4: is used in jump.c for the use-count of the label.
144 5: is used in the sh backend.
145 6: is a number that is unique in the entire compilation.
146 7: is the user-given name of the label, if any. */
147 DEF_RTL_EXPR(CODE_LABEL, "code_label", "iuuB00is", RTX_EXTRA)
149 /* Say where in the code a source line starts, for symbol table's sake.
151 4: note-specific data
153 6: unique number if insn_note == note_insn_deleted_label. */
154 DEF_RTL_EXPR(NOTE, "note", "iuuB0ni", RTX_EXTRA)
156 /* ----------------------------------------------------------------------
157 Top level constituents of INSN, JUMP_INSN and CALL_INSN.
158 ---------------------------------------------------------------------- */
160 /* Conditionally execute code.
161 Operand 0 is the condition that if true, the code is executed.
162 Operand 1 is the code to be executed (typically a SET).
164 Semantics are that there are no side effects if the condition
165 is false. This pattern is created automatically by the if_convert
166 pass run after reload or by target-specific splitters. */
167 DEF_RTL_EXPR(COND_EXEC, "cond_exec", "ee", RTX_EXTRA)
169 /* Several operations to be done in parallel (perhaps under COND_EXEC). */
170 DEF_RTL_EXPR(PARALLEL, "parallel", "E", RTX_EXTRA)
172 /* A string that is passed through to the assembler as input.
173 One can obviously pass comments through by using the
174 assembler comment syntax.
175 These occur in an insn all by themselves as the PATTERN.
176 They also appear inside an ASM_OPERANDS
177 as a convenient way to hold a string. */
178 DEF_RTL_EXPR(ASM_INPUT, "asm_input", "si", RTX_EXTRA)
180 /* An assembler instruction with operands.
181 1st operand is the instruction template.
182 2nd operand is the constraint for the output.
183 3rd operand is the number of the output this expression refers to.
184 When an insn stores more than one value, a separate ASM_OPERANDS
185 is made for each output; this integer distinguishes them.
186 4th is a vector of values of input operands.
187 5th is a vector of modes and constraints for the input operands.
188 Each element is an ASM_INPUT containing a constraint string
189 and whose mode indicates the mode of the input operand.
190 6th is the source line number. */
191 DEF_RTL_EXPR(ASM_OPERANDS, "asm_operands", "ssiEEi", RTX_EXTRA)
193 /* A machine-specific operation.
194 1st operand is a vector of operands being used by the operation so that
195 any needed reloads can be done.
196 2nd operand is a unique value saying which of a number of machine-specific
197 operations is to be performed.
198 (Note that the vector must be the first operand because of the way that
199 genrecog.c record positions within an insn.)
201 UNSPEC can occur all by itself in a PATTERN, as a component of a PARALLEL,
202 or inside an expression.
203 UNSPEC by itself or as a component of a PARALLEL
204 is currently considered not deletable.
206 FIXME: Replace all uses of UNSPEC that appears by itself or as a component
207 of a PARALLEL with USE.
209 DEF_RTL_EXPR(UNSPEC, "unspec", "Ei", RTX_EXTRA)
211 /* Similar, but a volatile operation and one which may trap. */
212 DEF_RTL_EXPR(UNSPEC_VOLATILE, "unspec_volatile", "Ei", RTX_EXTRA)
214 /* Vector of addresses, stored as full words. */
215 /* Each element is a LABEL_REF to a CODE_LABEL whose address we want. */
216 DEF_RTL_EXPR(ADDR_VEC, "addr_vec", "E", RTX_EXTRA)
218 /* Vector of address differences X0 - BASE, X1 - BASE, ...
219 First operand is BASE; the vector contains the X's.
220 The machine mode of this rtx says how much space to leave
221 for each difference and is adjusted by branch shortening if
222 CASE_VECTOR_SHORTEN_MODE is defined.
223 The third and fourth operands store the target labels with the
224 minimum and maximum addresses respectively.
225 The fifth operand stores flags for use by branch shortening.
226 Set at the start of shorten_branches:
227 min_align: the minimum alignment for any of the target labels.
228 base_after_vec: true iff BASE is after the ADDR_DIFF_VEC.
229 min_after_vec: true iff minimum addr target label is after the ADDR_DIFF_VEC.
230 max_after_vec: true iff maximum addr target label is after the ADDR_DIFF_VEC.
231 min_after_base: true iff minimum address target label is after BASE.
232 max_after_base: true iff maximum address target label is after BASE.
233 Set by the actual branch shortening process:
234 offset_unsigned: true iff offsets have to be treated as unsigned.
235 scale: scaling that is necessary to make offsets fit into the mode.
237 The third, fourth and fifth operands are only valid when
238 CASE_VECTOR_SHORTEN_MODE is defined, and only in an optimizing
241 DEF_RTL_EXPR(ADDR_DIFF_VEC, "addr_diff_vec", "eEee0", RTX_EXTRA)
243 /* Memory prefetch, with attributes supported on some targets.
244 Operand 1 is the address of the memory to fetch.
245 Operand 2 is 1 for a write access, 0 otherwise.
246 Operand 3 is the level of temporal locality; 0 means there is no
247 temporal locality and 1, 2, and 3 are for increasing levels of temporal
250 The attributes specified by operands 2 and 3 are ignored for targets
251 whose prefetch instructions do not support them. */
252 DEF_RTL_EXPR(PREFETCH, "prefetch", "eee", RTX_EXTRA)
254 /* ----------------------------------------------------------------------
255 At the top level of an instruction (perhaps under PARALLEL).
256 ---------------------------------------------------------------------- */
259 Operand 1 is the location (REG, MEM, PC, CC0 or whatever) assigned to.
260 Operand 2 is the value stored there.
261 ALL assignment must use SET.
262 Instructions that do multiple assignments must use multiple SET,
264 DEF_RTL_EXPR(SET, "set", "ee", RTX_EXTRA)
266 /* Indicate something is used in a way that we don't want to explain.
267 For example, subroutine calls will use the register
268 in which the static chain is passed.
270 USE can not appear as an operand of other rtx except for PARALLEL.
271 USE is not deletable, as it indicates that the operand
272 is used in some unknown way. */
273 DEF_RTL_EXPR(USE, "use", "e", RTX_EXTRA)
275 /* Indicate something is clobbered in a way that we don't want to explain.
276 For example, subroutine calls will clobber some physical registers
277 (the ones that are by convention not saved).
279 CLOBBER can not appear as an operand of other rtx except for PARALLEL.
280 CLOBBER of a hard register appearing by itself (not within PARALLEL)
281 is considered undeletable before reload. */
282 DEF_RTL_EXPR(CLOBBER, "clobber", "e", RTX_EXTRA)
284 /* Call a subroutine.
285 Operand 1 is the address to call.
286 Operand 2 is the number of arguments. */
288 DEF_RTL_EXPR(CALL, "call", "ee", RTX_EXTRA)
290 /* Return from a subroutine. */
292 DEF_RTL_EXPR(RETURN, "return", "", RTX_EXTRA)
294 /* Special for EH return from subroutine. */
296 DEF_RTL_EXPR(EH_RETURN, "eh_return", "", RTX_EXTRA)
299 Operand 1 is the condition.
300 Operand 2 is the trap code.
301 For an unconditional trap, make the condition (const_int 1). */
302 DEF_RTL_EXPR(TRAP_IF, "trap_if", "ee", RTX_EXTRA)
304 /* ----------------------------------------------------------------------
305 Primitive values for use in expressions.
306 ---------------------------------------------------------------------- */
308 /* numeric integer constant */
309 DEF_RTL_EXPR(CONST_INT, "const_int", "w", RTX_CONST_OBJ)
311 /* fixed-point constant */
312 DEF_RTL_EXPR(CONST_FIXED, "const_fixed", "www", RTX_CONST_OBJ)
314 /* numeric floating point constant.
315 Operands hold the value. They are all 'w' and there may be from 2 to 6;
317 DEF_RTL_EXPR(CONST_DOUBLE, "const_double", CONST_DOUBLE_FORMAT, RTX_CONST_OBJ)
319 /* Describes a vector constant. */
320 DEF_RTL_EXPR(CONST_VECTOR, "const_vector", "E", RTX_CONST_OBJ)
322 /* String constant. Used for attributes in machine descriptions and
323 for special cases in DWARF2 debug output. NOT used for source-
324 language string constants. */
325 DEF_RTL_EXPR(CONST_STRING, "const_string", "s", RTX_OBJ)
327 /* This is used to encapsulate an expression whose value is constant
328 (such as the sum of a SYMBOL_REF and a CONST_INT) so that it will be
329 recognized as a constant operand rather than by arithmetic instructions. */
331 DEF_RTL_EXPR(CONST, "const", "e", RTX_CONST_OBJ)
333 /* program counter. Ordinary jumps are represented
334 by a SET whose first operand is (PC). */
335 DEF_RTL_EXPR(PC, "pc", "", RTX_OBJ)
337 /* A register. The "operand" is the register number, accessed with
338 the REGNO macro. If this number is less than FIRST_PSEUDO_REGISTER
339 than a hardware register is being referred to. The second operand
340 holds the original register number - this will be different for a
341 pseudo register that got turned into a hard register. The third
342 operand points to a reg_attrs structure.
343 This rtx needs to have as many (or more) fields as a MEM, since we
344 can change REG rtx's into MEMs during reload. */
345 DEF_RTL_EXPR(REG, "reg", "i00", RTX_OBJ)
347 /* A scratch register. This represents a register used only within a
348 single insn. It will be turned into a REG during register allocation
349 or reload unless the constraint indicates that the register won't be
350 needed, in which case it can remain a SCRATCH. This code is
351 marked as having one operand so it can be turned into a REG. */
352 DEF_RTL_EXPR(SCRATCH, "scratch", "0", RTX_OBJ)
354 /* A reference to a part of another value. The first operand is the
355 complete value and the second is the byte offset of the selected part. */
356 DEF_RTL_EXPR(SUBREG, "subreg", "ei", RTX_EXTRA)
358 /* This one-argument rtx is used for move instructions
359 that are guaranteed to alter only the low part of a destination.
360 Thus, (SET (SUBREG:HI (REG...)) (MEM:HI ...))
361 has an unspecified effect on the high part of REG,
362 but (SET (STRICT_LOW_PART (SUBREG:HI (REG...))) (MEM:HI ...))
363 is guaranteed to alter only the bits of REG that are in HImode.
365 The actual instruction used is probably the same in both cases,
366 but the register constraints may be tighter when STRICT_LOW_PART
369 DEF_RTL_EXPR(STRICT_LOW_PART, "strict_low_part", "e", RTX_EXTRA)
371 /* (CONCAT a b) represents the virtual concatenation of a and b
372 to make a value that has as many bits as a and b put together.
373 This is used for complex values. Normally it appears only
374 in DECL_RTLs and during RTL generation, but not in the insn chain. */
375 DEF_RTL_EXPR(CONCAT, "concat", "ee", RTX_OBJ)
377 /* (CONCATN [a1 a2 ... an]) represents the virtual concatenation of
378 all An to make a value. This is an extension of CONCAT to larger
379 number of components. Like CONCAT, it should not appear in the
380 insn chain. Every element of the CONCATN is the same size. */
381 DEF_RTL_EXPR(CONCATN, "concatn", "E", RTX_OBJ)
383 /* A memory location; operand is the address. The second operand is the
384 alias set to which this MEM belongs. We use `0' instead of `w' for this
385 field so that the field need not be specified in machine descriptions. */
386 DEF_RTL_EXPR(MEM, "mem", "e0", RTX_OBJ)
388 /* Reference to an assembler label in the code for this function.
389 The operand is a CODE_LABEL found in the insn chain. */
390 DEF_RTL_EXPR(LABEL_REF, "label_ref", "u", RTX_CONST_OBJ)
392 /* Reference to a named label:
393 Operand 0: label name
394 Operand 1: flags (see SYMBOL_FLAG_* in rtl.h)
395 Operand 2: tree from which this symbol is derived, or null.
396 This is either a DECL node, or some kind of constant. */
397 DEF_RTL_EXPR(SYMBOL_REF, "symbol_ref", "s00", RTX_CONST_OBJ)
399 /* The condition code register is represented, in our imagination,
400 as a register holding a value that can be compared to zero.
401 In fact, the machine has already compared them and recorded the
402 results; but instructions that look at the condition code
403 pretend to be looking at the entire value and comparing it. */
404 DEF_RTL_EXPR(CC0, "cc0", "", RTX_OBJ)
406 /* ----------------------------------------------------------------------
407 Expressions for operators in an rtl pattern
408 ---------------------------------------------------------------------- */
410 /* if_then_else. This is used in representing ordinary
411 conditional jump instructions.
416 DEF_RTL_EXPR(IF_THEN_ELSE, "if_then_else", "eee", RTX_TERNARY)
418 /* Comparison, produces a condition code result. */
419 DEF_RTL_EXPR(COMPARE, "compare", "ee", RTX_BIN_ARITH)
422 DEF_RTL_EXPR(PLUS, "plus", "ee", RTX_COMM_ARITH)
424 /* Operand 0 minus operand 1. */
425 DEF_RTL_EXPR(MINUS, "minus", "ee", RTX_BIN_ARITH)
427 /* Minus operand 0. */
428 DEF_RTL_EXPR(NEG, "neg", "e", RTX_UNARY)
430 DEF_RTL_EXPR(MULT, "mult", "ee", RTX_COMM_ARITH)
432 /* Multiplication with signed saturation */
433 DEF_RTL_EXPR(SS_MULT, "ss_mult", "ee", RTX_COMM_ARITH)
434 /* Multiplication with unsigned saturation */
435 DEF_RTL_EXPR(US_MULT, "us_mult", "ee", RTX_COMM_ARITH)
437 /* Operand 0 divided by operand 1. */
438 DEF_RTL_EXPR(DIV, "div", "ee", RTX_BIN_ARITH)
439 /* Division with signed saturation */
440 DEF_RTL_EXPR(SS_DIV, "ss_div", "ee", RTX_BIN_ARITH)
441 /* Division with unsigned saturation */
442 DEF_RTL_EXPR(US_DIV, "us_div", "ee", RTX_BIN_ARITH)
444 /* Remainder of operand 0 divided by operand 1. */
445 DEF_RTL_EXPR(MOD, "mod", "ee", RTX_BIN_ARITH)
447 /* Unsigned divide and remainder. */
448 DEF_RTL_EXPR(UDIV, "udiv", "ee", RTX_BIN_ARITH)
449 DEF_RTL_EXPR(UMOD, "umod", "ee", RTX_BIN_ARITH)
451 /* Bitwise operations. */
452 DEF_RTL_EXPR(AND, "and", "ee", RTX_COMM_ARITH)
453 DEF_RTL_EXPR(IOR, "ior", "ee", RTX_COMM_ARITH)
454 DEF_RTL_EXPR(XOR, "xor", "ee", RTX_COMM_ARITH)
455 DEF_RTL_EXPR(NOT, "not", "e", RTX_UNARY)
458 0: value to be shifted.
459 1: number of bits. */
460 DEF_RTL_EXPR(ASHIFT, "ashift", "ee", RTX_BIN_ARITH) /* shift left */
461 DEF_RTL_EXPR(ROTATE, "rotate", "ee", RTX_BIN_ARITH) /* rotate left */
462 DEF_RTL_EXPR(ASHIFTRT, "ashiftrt", "ee", RTX_BIN_ARITH) /* arithmetic shift right */
463 DEF_RTL_EXPR(LSHIFTRT, "lshiftrt", "ee", RTX_BIN_ARITH) /* logical shift right */
464 DEF_RTL_EXPR(ROTATERT, "rotatert", "ee", RTX_BIN_ARITH) /* rotate right */
466 /* Minimum and maximum values of two operands. We need both signed and
467 unsigned forms. (We cannot use MIN for SMIN because it conflicts
468 with a macro of the same name.) The signed variants should be used
469 with floating point. Further, if both operands are zeros, or if either
470 operand is NaN, then it is unspecified which of the two operands is
471 returned as the result. */
473 DEF_RTL_EXPR(SMIN, "smin", "ee", RTX_COMM_ARITH)
474 DEF_RTL_EXPR(SMAX, "smax", "ee", RTX_COMM_ARITH)
475 DEF_RTL_EXPR(UMIN, "umin", "ee", RTX_COMM_ARITH)
476 DEF_RTL_EXPR(UMAX, "umax", "ee", RTX_COMM_ARITH)
478 /* These unary operations are used to represent incrementation
479 and decrementation as they occur in memory addresses.
480 The amount of increment or decrement are not represented
481 because they can be understood from the machine-mode of the
482 containing MEM. These operations exist in only two cases:
483 1. pushes onto the stack.
484 2. created automatically by the life_analysis pass in flow.c. */
485 DEF_RTL_EXPR(PRE_DEC, "pre_dec", "e", RTX_AUTOINC)
486 DEF_RTL_EXPR(PRE_INC, "pre_inc", "e", RTX_AUTOINC)
487 DEF_RTL_EXPR(POST_DEC, "post_dec", "e", RTX_AUTOINC)
488 DEF_RTL_EXPR(POST_INC, "post_inc", "e", RTX_AUTOINC)
490 /* These binary operations are used to represent generic address
491 side-effects in memory addresses, except for simple incrementation
492 or decrementation which use the above operations. They are
493 created automatically by the life_analysis pass in flow.c.
494 The first operand is a REG which is used as the address.
495 The second operand is an expression that is assigned to the
496 register, either before (PRE_MODIFY) or after (POST_MODIFY)
497 evaluating the address.
498 Currently, the compiler can only handle second operands of the
499 form (plus (reg) (reg)) and (plus (reg) (const_int)), where
500 the first operand of the PLUS has to be the same register as
501 the first operand of the *_MODIFY. */
502 DEF_RTL_EXPR(PRE_MODIFY, "pre_modify", "ee", RTX_AUTOINC)
503 DEF_RTL_EXPR(POST_MODIFY, "post_modify", "ee", RTX_AUTOINC)
505 /* Comparison operations. The ordered comparisons exist in two
506 flavors, signed and unsigned. */
507 DEF_RTL_EXPR(NE, "ne", "ee", RTX_COMM_COMPARE)
508 DEF_RTL_EXPR(EQ, "eq", "ee", RTX_COMM_COMPARE)
509 DEF_RTL_EXPR(GE, "ge", "ee", RTX_COMPARE)
510 DEF_RTL_EXPR(GT, "gt", "ee", RTX_COMPARE)
511 DEF_RTL_EXPR(LE, "le", "ee", RTX_COMPARE)
512 DEF_RTL_EXPR(LT, "lt", "ee", RTX_COMPARE)
513 DEF_RTL_EXPR(GEU, "geu", "ee", RTX_COMPARE)
514 DEF_RTL_EXPR(GTU, "gtu", "ee", RTX_COMPARE)
515 DEF_RTL_EXPR(LEU, "leu", "ee", RTX_COMPARE)
516 DEF_RTL_EXPR(LTU, "ltu", "ee", RTX_COMPARE)
518 /* Additional floating point unordered comparison flavors. */
519 DEF_RTL_EXPR(UNORDERED, "unordered", "ee", RTX_COMM_COMPARE)
520 DEF_RTL_EXPR(ORDERED, "ordered", "ee", RTX_COMM_COMPARE)
522 /* These are equivalent to unordered or ... */
523 DEF_RTL_EXPR(UNEQ, "uneq", "ee", RTX_COMM_COMPARE)
524 DEF_RTL_EXPR(UNGE, "unge", "ee", RTX_COMPARE)
525 DEF_RTL_EXPR(UNGT, "ungt", "ee", RTX_COMPARE)
526 DEF_RTL_EXPR(UNLE, "unle", "ee", RTX_COMPARE)
527 DEF_RTL_EXPR(UNLT, "unlt", "ee", RTX_COMPARE)
529 /* This is an ordered NE, ie !UNEQ, ie false for NaN. */
530 DEF_RTL_EXPR(LTGT, "ltgt", "ee", RTX_COMM_COMPARE)
532 /* Represents the result of sign-extending the sole operand.
533 The machine modes of the operand and of the SIGN_EXTEND expression
534 determine how much sign-extension is going on. */
535 DEF_RTL_EXPR(SIGN_EXTEND, "sign_extend", "e", RTX_UNARY)
537 /* Similar for zero-extension (such as unsigned short to int). */
538 DEF_RTL_EXPR(ZERO_EXTEND, "zero_extend", "e", RTX_UNARY)
540 /* Similar but here the operand has a wider mode. */
541 DEF_RTL_EXPR(TRUNCATE, "truncate", "e", RTX_UNARY)
543 /* Similar for extending floating-point values (such as SFmode to DFmode). */
544 DEF_RTL_EXPR(FLOAT_EXTEND, "float_extend", "e", RTX_UNARY)
545 DEF_RTL_EXPR(FLOAT_TRUNCATE, "float_truncate", "e", RTX_UNARY)
547 /* Conversion of fixed point operand to floating point value. */
548 DEF_RTL_EXPR(FLOAT, "float", "e", RTX_UNARY)
550 /* With fixed-point machine mode:
551 Conversion of floating point operand to fixed point value.
552 Value is defined only when the operand's value is an integer.
553 With floating-point machine mode (and operand with same mode):
554 Operand is rounded toward zero to produce an integer value
555 represented in floating point. */
556 DEF_RTL_EXPR(FIX, "fix", "e", RTX_UNARY)
558 /* Conversion of unsigned fixed point operand to floating point value. */
559 DEF_RTL_EXPR(UNSIGNED_FLOAT, "unsigned_float", "e", RTX_UNARY)
561 /* With fixed-point machine mode:
562 Conversion of floating point operand to *unsigned* fixed point value.
563 Value is defined only when the operand's value is an integer. */
564 DEF_RTL_EXPR(UNSIGNED_FIX, "unsigned_fix", "e", RTX_UNARY)
566 /* Conversions involving fractional fixed-point types without saturation,
568 fractional to fractional (of different precision),
569 signed integer to fractional,
570 fractional to signed integer,
571 floating point to fractional,
572 fractional to floating point.
573 NOTE: fractional can be either signed or unsigned for conversions. */
574 DEF_RTL_EXPR(FRACT_CONVERT, "fract_convert", "e", RTX_UNARY)
576 /* Conversions involving fractional fixed-point types and unsigned integer
577 without saturation, including:
578 unsigned integer to fractional,
579 fractional to unsigned integer.
580 NOTE: fractional can be either signed or unsigned for conversions. */
581 DEF_RTL_EXPR(UNSIGNED_FRACT_CONVERT, "unsigned_fract_convert", "e", RTX_UNARY)
583 /* Conversions involving fractional fixed-point types with saturation,
585 fractional to fractional (of different precision),
586 signed integer to fractional,
587 floating point to fractional.
588 NOTE: fractional can be either signed or unsigned for conversions. */
589 DEF_RTL_EXPR(SAT_FRACT, "sat_fract", "e", RTX_UNARY)
591 /* Conversions involving fractional fixed-point types and unsigned integer
592 with saturation, including:
593 unsigned integer to fractional.
594 NOTE: fractional can be either signed or unsigned for conversions. */
595 DEF_RTL_EXPR(UNSIGNED_SAT_FRACT, "unsigned_sat_fract", "e", RTX_UNARY)
598 DEF_RTL_EXPR(ABS, "abs", "e", RTX_UNARY)
601 DEF_RTL_EXPR(SQRT, "sqrt", "e", RTX_UNARY)
604 DEF_RTL_EXPR(BSWAP, "bswap", "e", RTX_UNARY)
606 /* Find first bit that is set.
607 Value is 1 + number of trailing zeros in the arg.,
609 DEF_RTL_EXPR(FFS, "ffs", "e", RTX_UNARY)
611 /* Count leading zeros. */
612 DEF_RTL_EXPR(CLZ, "clz", "e", RTX_UNARY)
614 /* Count trailing zeros. */
615 DEF_RTL_EXPR(CTZ, "ctz", "e", RTX_UNARY)
617 /* Population count (number of 1 bits). */
618 DEF_RTL_EXPR(POPCOUNT, "popcount", "e", RTX_UNARY)
620 /* Population parity (number of 1 bits modulo 2). */
621 DEF_RTL_EXPR(PARITY, "parity", "e", RTX_UNARY)
623 /* Reference to a signed bit-field of specified size and position.
624 Operand 0 is the memory unit (usually SImode or QImode) which
625 contains the field's first bit. Operand 1 is the width, in bits.
626 Operand 2 is the number of bits in the memory unit before the
627 first bit of this field.
628 If BITS_BIG_ENDIAN is defined, the first bit is the msb and
629 operand 2 counts from the msb of the memory unit.
630 Otherwise, the first bit is the lsb and operand 2 counts from
631 the lsb of the memory unit.
632 This kind of expression can not appear as an lvalue in RTL. */
633 DEF_RTL_EXPR(SIGN_EXTRACT, "sign_extract", "eee", RTX_BITFIELD_OPS)
635 /* Similar for unsigned bit-field.
636 But note! This kind of expression _can_ appear as an lvalue. */
637 DEF_RTL_EXPR(ZERO_EXTRACT, "zero_extract", "eee", RTX_BITFIELD_OPS)
639 /* For RISC machines. These save memory when splitting insns. */
641 /* HIGH are the high-order bits of a constant expression. */
642 DEF_RTL_EXPR(HIGH, "high", "e", RTX_CONST_OBJ)
644 /* LO_SUM is the sum of a register and the low-order bits
645 of a constant expression. */
646 DEF_RTL_EXPR(LO_SUM, "lo_sum", "ee", RTX_OBJ)
648 /* Describes a merge operation between two vector values.
649 Operands 0 and 1 are the vectors to be merged, operand 2 is a bitmask
650 that specifies where the parts of the result are taken from. Set bits
651 indicate operand 0, clear bits indicate operand 1. The parts are defined
652 by the mode of the vectors. */
653 DEF_RTL_EXPR(VEC_MERGE, "vec_merge", "eee", RTX_TERNARY)
655 /* Describes an operation that selects parts of a vector.
656 Operands 0 is the source vector, operand 1 is a PARALLEL that contains
657 a CONST_INT for each of the subparts of the result vector, giving the
658 number of the source subpart that should be stored into it. */
659 DEF_RTL_EXPR(VEC_SELECT, "vec_select", "ee", RTX_BIN_ARITH)
661 /* Describes a vector concat operation. Operands 0 and 1 are the source
662 vectors, the result is a vector that is as long as operands 0 and 1
663 combined and is the concatenation of the two source vectors. */
664 DEF_RTL_EXPR(VEC_CONCAT, "vec_concat", "ee", RTX_BIN_ARITH)
666 /* Describes an operation that converts a small vector into a larger one by
667 duplicating the input values. The output vector mode must have the same
668 submodes as the input vector mode, and the number of output parts must be
669 an integer multiple of the number of input parts. */
670 DEF_RTL_EXPR(VEC_DUPLICATE, "vec_duplicate", "e", RTX_UNARY)
672 /* Addition with signed saturation */
673 DEF_RTL_EXPR(SS_PLUS, "ss_plus", "ee", RTX_COMM_ARITH)
675 /* Addition with unsigned saturation */
676 DEF_RTL_EXPR(US_PLUS, "us_plus", "ee", RTX_COMM_ARITH)
678 /* Operand 0 minus operand 1, with signed saturation. */
679 DEF_RTL_EXPR(SS_MINUS, "ss_minus", "ee", RTX_BIN_ARITH)
681 /* Negation with signed saturation. */
682 DEF_RTL_EXPR(SS_NEG, "ss_neg", "e", RTX_UNARY)
683 /* Negation with unsigned saturation. */
684 DEF_RTL_EXPR(US_NEG, "us_neg", "e", RTX_UNARY)
686 /* Absolute value with signed saturation. */
687 DEF_RTL_EXPR(SS_ABS, "ss_abs", "e", RTX_UNARY)
689 /* Shift left with signed saturation. */
690 DEF_RTL_EXPR(SS_ASHIFT, "ss_ashift", "ee", RTX_BIN_ARITH)
692 /* Shift left with unsigned saturation. */
693 DEF_RTL_EXPR(US_ASHIFT, "us_ashift", "ee", RTX_BIN_ARITH)
695 /* Operand 0 minus operand 1, with unsigned saturation. */
696 DEF_RTL_EXPR(US_MINUS, "us_minus", "ee", RTX_BIN_ARITH)
698 /* Signed saturating truncate. */
699 DEF_RTL_EXPR(SS_TRUNCATE, "ss_truncate", "e", RTX_UNARY)
701 /* Unsigned saturating truncate. */
702 DEF_RTL_EXPR(US_TRUNCATE, "us_truncate", "e", RTX_UNARY)
704 /* Information about the variable and its location. */
705 /* Changed 'te' to 'tei'; the 'i' field is for recording
706 initialization status of variables. */
707 DEF_RTL_EXPR(VAR_LOCATION, "var_location", "tei", RTX_EXTRA)
709 /* All expressions from this point forward appear only in machine
711 #ifdef GENERATOR_FILE
713 /* Include a secondary machine-description file at this point. */
714 DEF_RTL_EXPR(INCLUDE, "include", "s", RTX_EXTRA)
716 /* Pattern-matching operators: */
718 /* Use the function named by the second arg (the string)
719 as a predicate; if matched, store the structure that was matched
720 in the operand table at index specified by the first arg (the integer).
721 If the second arg is the null string, the structure is just stored.
723 A third string argument indicates to the register allocator restrictions
724 on where the operand can be allocated.
726 If the target needs no restriction on any instruction this field should
729 The string is prepended by:
730 '=' to indicate the operand is only written to.
731 '+' to indicate the operand is both read and written to.
733 Each character in the string represents an allocable class for an operand.
734 'g' indicates the operand can be any valid class.
735 'i' indicates the operand can be immediate (in the instruction) data.
736 'r' indicates the operand can be in a register.
737 'm' indicates the operand can be in memory.
738 'o' a subset of the 'm' class. Those memory addressing modes that
739 can be offset at compile time (have a constant added to them).
741 Other characters indicate target dependent operand classes and
742 are described in each target's machine description.
744 For instructions with more than one operand, sets of classes can be
745 separated by a comma to indicate the appropriate multi-operand constraints.
746 There must be a 1 to 1 correspondence between these sets of classes in
747 all operands for an instruction.
749 DEF_RTL_EXPR(MATCH_OPERAND, "match_operand", "iss", RTX_MATCH)
751 /* Match a SCRATCH or a register. When used to generate rtl, a
752 SCRATCH is generated. As for MATCH_OPERAND, the mode specifies
753 the desired mode and the first argument is the operand number.
754 The second argument is the constraint. */
755 DEF_RTL_EXPR(MATCH_SCRATCH, "match_scratch", "is", RTX_MATCH)
757 /* Apply a predicate, AND match recursively the operands of the rtx.
758 Operand 0 is the operand-number, as in match_operand.
759 Operand 1 is a predicate to apply (as a string, a function name).
760 Operand 2 is a vector of expressions, each of which must match
761 one subexpression of the rtx this construct is matching. */
762 DEF_RTL_EXPR(MATCH_OPERATOR, "match_operator", "isE", RTX_MATCH)
764 /* Match a PARALLEL of arbitrary length. The predicate is applied
765 to the PARALLEL and the initial expressions in the PARALLEL are matched.
766 Operand 0 is the operand-number, as in match_operand.
767 Operand 1 is a predicate to apply to the PARALLEL.
768 Operand 2 is a vector of expressions, each of which must match the
769 corresponding element in the PARALLEL. */
770 DEF_RTL_EXPR(MATCH_PARALLEL, "match_parallel", "isE", RTX_MATCH)
772 /* Match only something equal to what is stored in the operand table
773 at the index specified by the argument. Use with MATCH_OPERAND. */
774 DEF_RTL_EXPR(MATCH_DUP, "match_dup", "i", RTX_MATCH)
776 /* Match only something equal to what is stored in the operand table
777 at the index specified by the argument. Use with MATCH_OPERATOR. */
778 DEF_RTL_EXPR(MATCH_OP_DUP, "match_op_dup", "iE", RTX_MATCH)
780 /* Match only something equal to what is stored in the operand table
781 at the index specified by the argument. Use with MATCH_PARALLEL. */
782 DEF_RTL_EXPR(MATCH_PAR_DUP, "match_par_dup", "iE", RTX_MATCH)
784 /* Appears only in define_predicate/define_special_predicate
785 expressions. Evaluates true only if the operand has an RTX code
786 from the set given by the argument (a comma-separated list). If the
787 second argument is present and nonempty, it is a sequence of digits
788 and/or letters which indicates the subexpression to test, using the
789 same syntax as genextract/genrecog's location strings: 0-9 for
790 XEXP (op, n), a-z for XVECEXP (op, 0, n); each character applies to
791 the result of the one before it. */
792 DEF_RTL_EXPR(MATCH_CODE, "match_code", "ss", RTX_MATCH)
794 /* Appears only in define_predicate/define_special_predicate
795 expressions. The argument is a C expression to be injected at this
796 point in the predicate formula. */
797 DEF_RTL_EXPR(MATCH_TEST, "match_test", "s", RTX_MATCH)
799 /* Insn (and related) definitions. */
801 /* Definition of the pattern for one kind of instruction.
803 0: names this instruction.
804 If the name is the null string, the instruction is in the
805 machine description just to be recognized, and will never be emitted by
806 the tree to rtl expander.
808 2: is a string which is a C expression
809 giving an additional condition for recognizing this pattern.
810 A null string means no extra condition.
811 3: is the action to execute if this pattern is matched.
812 If this assembler code template starts with a * then it is a fragment of
813 C code to run to decide on a template to use. Otherwise, it is the
815 4: optionally, a vector of attributes for this insn.
817 DEF_RTL_EXPR(DEFINE_INSN, "define_insn", "sEsTV", RTX_EXTRA)
819 /* Definition of a peephole optimization.
820 1st operand: vector of insn patterns to match
821 2nd operand: C expression that must be true
822 3rd operand: template or C code to produce assembler output.
823 4: optionally, a vector of attributes for this insn.
825 This form is deprecated; use define_peephole2 instead. */
826 DEF_RTL_EXPR(DEFINE_PEEPHOLE, "define_peephole", "EsTV", RTX_EXTRA)
828 /* Definition of a split operation.
829 1st operand: insn pattern to match
830 2nd operand: C expression that must be true
831 3rd operand: vector of insn patterns to place into a SEQUENCE
832 4th operand: optionally, some C code to execute before generating the
833 insns. This might, for example, create some RTX's and store them in
834 elements of `recog_data.operand' for use by the vector of
836 (`operands' is an alias here for `recog_data.operand'). */
837 DEF_RTL_EXPR(DEFINE_SPLIT, "define_split", "EsES", RTX_EXTRA)
839 /* Definition of an insn and associated split.
840 This is the concatenation, with a few modifications, of a define_insn
841 and a define_split which share the same pattern.
843 0: names this instruction.
844 If the name is the null string, the instruction is in the
845 machine description just to be recognized, and will never be emitted by
846 the tree to rtl expander.
848 2: is a string which is a C expression
849 giving an additional condition for recognizing this pattern.
850 A null string means no extra condition.
851 3: is the action to execute if this pattern is matched.
852 If this assembler code template starts with a * then it is a fragment of
853 C code to run to decide on a template to use. Otherwise, it is the
855 4: C expression that must be true for split. This may start with "&&"
856 in which case the split condition is the logical and of the insn
857 condition and what follows the "&&" of this operand.
858 5: vector of insn patterns to place into a SEQUENCE
859 6: optionally, some C code to execute before generating the
860 insns. This might, for example, create some RTX's and store them in
861 elements of `recog_data.operand' for use by the vector of
863 (`operands' is an alias here for `recog_data.operand').
864 7: optionally, a vector of attributes for this insn. */
865 DEF_RTL_EXPR(DEFINE_INSN_AND_SPLIT, "define_insn_and_split", "sEsTsESV", RTX_EXTRA)
867 /* Definition of an RTL peephole operation.
868 Follows the same arguments as define_split. */
869 DEF_RTL_EXPR(DEFINE_PEEPHOLE2, "define_peephole2", "EsES", RTX_EXTRA)
871 /* Define how to generate multiple insns for a standard insn name.
872 1st operand: the insn name.
873 2nd operand: vector of insn-patterns.
874 Use match_operand to substitute an element of `recog_data.operand'.
875 3rd operand: C expression that must be true for this to be available.
876 This may not test any operands.
877 4th operand: Extra C code to execute before generating the insns.
878 This might, for example, create some RTX's and store them in
879 elements of `recog_data.operand' for use by the vector of
881 (`operands' is an alias here for `recog_data.operand'). */
882 DEF_RTL_EXPR(DEFINE_EXPAND, "define_expand", "sEss", RTX_EXTRA)
884 /* Define a requirement for delay slots.
885 1st operand: Condition involving insn attributes that, if true,
886 indicates that the insn requires the number of delay slots
888 2nd operand: Vector whose length is the three times the number of delay
890 Each entry gives three conditions, each involving attributes.
891 The first must be true for an insn to occupy that delay slot
892 location. The second is true for all insns that can be
893 annulled if the branch is true and the third is true for all
894 insns that can be annulled if the branch is false.
896 Multiple DEFINE_DELAYs may be present. They indicate differing
897 requirements for delay slots. */
898 DEF_RTL_EXPR(DEFINE_DELAY, "define_delay", "eE", RTX_EXTRA)
900 /* Define attribute computation for `asm' instructions. */
901 DEF_RTL_EXPR(DEFINE_ASM_ATTRIBUTES, "define_asm_attributes", "V", RTX_EXTRA)
903 /* Definition of a conditional execution meta operation. Automatically
904 generates new instances of DEFINE_INSN, selected by having attribute
905 "predicable" true. The new pattern will contain a COND_EXEC and the
906 predicate at top-level.
909 0: The predicate pattern. The top-level form should match a
910 relational operator. Operands should have only one alternative.
911 1: A C expression giving an additional condition for recognizing
912 the generated pattern.
913 2: A template or C code to produce assembler output. */
914 DEF_RTL_EXPR(DEFINE_COND_EXEC, "define_cond_exec", "Ess", RTX_EXTRA)
916 /* Definition of an operand predicate. The difference between
917 DEFINE_PREDICATE and DEFINE_SPECIAL_PREDICATE is that genrecog will
918 not warn about a match_operand with no mode if it has a predicate
919 defined with DEFINE_SPECIAL_PREDICATE.
922 0: The name of the predicate.
923 1: A boolean expression which computes whether or not the predicate
924 matches. This expression can use IOR, AND, NOT, MATCH_OPERAND,
925 MATCH_CODE, and MATCH_TEST. It must be specific enough that genrecog
926 can calculate the set of RTX codes that can possibly match.
927 2: A C function body which must return true for the predicate to match.
928 Optional. Use this when the test is too complicated to fit into a
929 match_test expression. */
930 DEF_RTL_EXPR(DEFINE_PREDICATE, "define_predicate", "ses", RTX_EXTRA)
931 DEF_RTL_EXPR(DEFINE_SPECIAL_PREDICATE, "define_special_predicate", "ses", RTX_EXTRA)
933 /* Definition of a register operand constraint. This simply maps the
934 constraint string to a register class.
937 0: The name of the constraint (often, but not always, a single letter).
938 1: A C expression which evaluates to the appropriate register class for
939 this constraint. If this is not just a constant, it should look only
940 at -m switches and the like.
941 2: A docstring for this constraint, in Texinfo syntax; not currently
942 used, in future will be incorporated into the manual's list of
943 machine-specific operand constraints. */
944 DEF_RTL_EXPR(DEFINE_REGISTER_CONSTRAINT, "define_register_constraint", "sss", RTX_EXTRA)
946 /* Definition of a non-register operand constraint. These look at the
947 operand and decide whether it fits the constraint.
949 DEFINE_CONSTRAINT gets no special treatment if it fails to match.
950 It is appropriate for constant-only constraints, and most others.
952 DEFINE_MEMORY_CONSTRAINT tells reload that this constraint can be made
953 to match, if it doesn't already, by converting the operand to the form
954 (mem (reg X)) where X is a base register. It is suitable for constraints
955 that describe a subset of all memory references.
957 DEFINE_ADDRESS_CONSTRAINT tells reload that this constraint can be made
958 to match, if it doesn't already, by converting the operand to the form
959 (reg X) where X is a base register. It is suitable for constraints that
960 describe a subset of all address references.
962 When in doubt, use plain DEFINE_CONSTRAINT.
965 0: The name of the constraint (often, but not always, a single letter).
966 1: A docstring for this constraint, in Texinfo syntax; not currently
967 used, in future will be incorporated into the manual's list of
968 machine-specific operand constraints.
969 2: A boolean expression which computes whether or not the constraint
970 matches. It should follow the same rules as a define_predicate
971 expression, including the bit about specifying the set of RTX codes
972 that could possibly match. MATCH_TEST subexpressions may make use of
974 `op' - the RTL object defining the operand.
975 `mode' - the mode of `op'.
976 `ival' - INTVAL(op), if op is a CONST_INT.
977 `hval' - CONST_DOUBLE_HIGH(op), if op is an integer CONST_DOUBLE.
978 `lval' - CONST_DOUBLE_LOW(op), if op is an integer CONST_DOUBLE.
979 `rval' - CONST_DOUBLE_REAL_VALUE(op), if op is a floating-point
981 Do not use ival/hval/lval/rval if op is not the appropriate kind of
983 DEF_RTL_EXPR(DEFINE_CONSTRAINT, "define_constraint", "sse", RTX_EXTRA)
984 DEF_RTL_EXPR(DEFINE_MEMORY_CONSTRAINT, "define_memory_constraint", "sse", RTX_EXTRA)
985 DEF_RTL_EXPR(DEFINE_ADDRESS_CONSTRAINT, "define_address_constraint", "sse", RTX_EXTRA)
988 /* Constructions for CPU pipeline description described by NDFAs. */
990 /* (define_cpu_unit string [string]) describes cpu functional
991 units (separated by comma).
993 1st operand: Names of cpu functional units.
994 2nd operand: Name of automaton (see comments for DEFINE_AUTOMATON).
996 All define_reservations, define_cpu_units, and
997 define_query_cpu_units should have unique names which may not be
999 DEF_RTL_EXPR(DEFINE_CPU_UNIT, "define_cpu_unit", "sS", RTX_EXTRA)
1001 /* (define_query_cpu_unit string [string]) describes cpu functional
1002 units analogously to define_cpu_unit. The reservation of such
1003 units can be queried for automaton state. */
1004 DEF_RTL_EXPR(DEFINE_QUERY_CPU_UNIT, "define_query_cpu_unit", "sS", RTX_EXTRA)
1006 /* (exclusion_set string string) means that each CPU functional unit
1007 in the first string can not be reserved simultaneously with any
1008 unit whose name is in the second string and vise versa. CPU units
1009 in the string are separated by commas. For example, it is useful
1010 for description CPU with fully pipelined floating point functional
1011 unit which can execute simultaneously only single floating point
1012 insns or only double floating point insns. All CPU functional
1013 units in a set should belong to the same automaton. */
1014 DEF_RTL_EXPR(EXCLUSION_SET, "exclusion_set", "ss", RTX_EXTRA)
1016 /* (presence_set string string) means that each CPU functional unit in
1017 the first string can not be reserved unless at least one of pattern
1018 of units whose names are in the second string is reserved. This is
1019 an asymmetric relation. CPU units or unit patterns in the strings
1020 are separated by commas. Pattern is one unit name or unit names
1021 separated by white-spaces.
1023 For example, it is useful for description that slot1 is reserved
1024 after slot0 reservation for a VLIW processor. We could describe it
1025 by the following construction
1027 (presence_set "slot1" "slot0")
1029 Or slot1 is reserved only after slot0 and unit b0 reservation. In
1030 this case we could write
1032 (presence_set "slot1" "slot0 b0")
1034 All CPU functional units in a set should belong to the same
1036 DEF_RTL_EXPR(PRESENCE_SET, "presence_set", "ss", RTX_EXTRA)
1038 /* (final_presence_set string string) is analogous to `presence_set'.
1039 The difference between them is when checking is done. When an
1040 instruction is issued in given automaton state reflecting all
1041 current and planned unit reservations, the automaton state is
1042 changed. The first state is a source state, the second one is a
1043 result state. Checking for `presence_set' is done on the source
1044 state reservation, checking for `final_presence_set' is done on the
1045 result reservation. This construction is useful to describe a
1046 reservation which is actually two subsequent reservations. For
1049 (presence_set "slot1" "slot0")
1051 the following insn will be never issued (because slot1 requires
1052 slot0 which is absent in the source state).
1054 (define_reservation "insn_and_nop" "slot0 + slot1")
1056 but it can be issued if we use analogous `final_presence_set'. */
1057 DEF_RTL_EXPR(FINAL_PRESENCE_SET, "final_presence_set", "ss", RTX_EXTRA)
1059 /* (absence_set string string) means that each CPU functional unit in
1060 the first string can be reserved only if each pattern of units
1061 whose names are in the second string is not reserved. This is an
1062 asymmetric relation (actually exclusion set is analogous to this
1063 one but it is symmetric). CPU units or unit patterns in the string
1064 are separated by commas. Pattern is one unit name or unit names
1065 separated by white-spaces.
1067 For example, it is useful for description that slot0 can not be
1068 reserved after slot1 or slot2 reservation for a VLIW processor. We
1069 could describe it by the following construction
1071 (absence_set "slot2" "slot0, slot1")
1073 Or slot2 can not be reserved if slot0 and unit b0 are reserved or
1074 slot1 and unit b1 are reserved . In this case we could write
1076 (absence_set "slot2" "slot0 b0, slot1 b1")
1078 All CPU functional units in a set should to belong the same
1080 DEF_RTL_EXPR(ABSENCE_SET, "absence_set", "ss", RTX_EXTRA)
1082 /* (final_absence_set string string) is analogous to `absence_set' but
1083 checking is done on the result (state) reservation. See comments
1084 for `final_presence_set'. */
1085 DEF_RTL_EXPR(FINAL_ABSENCE_SET, "final_absence_set", "ss", RTX_EXTRA)
1087 /* (define_bypass number out_insn_names in_insn_names) names bypass
1088 with given latency (the first number) from insns given by the first
1089 string (see define_insn_reservation) into insns given by the second
1090 string. Insn names in the strings are separated by commas. The
1091 third operand is optional name of function which is additional
1092 guard for the bypass. The function will get the two insns as
1093 parameters. If the function returns zero the bypass will be
1094 ignored for this case. Additional guard is necessary to recognize
1095 complicated bypasses, e.g. when consumer is load address. If there
1096 are more one bypass with the same output and input insns, the
1097 chosen bypass is the first bypass with a guard in description whose
1098 guard function returns nonzero. If there is no such bypass, then
1099 bypass without the guard function is chosen. */
1100 DEF_RTL_EXPR(DEFINE_BYPASS, "define_bypass", "issS", RTX_EXTRA)
1102 /* (define_automaton string) describes names of automata generated and
1103 used for pipeline hazards recognition. The names are separated by
1104 comma. Actually it is possibly to generate the single automaton
1105 but unfortunately it can be very large. If we use more one
1106 automata, the summary size of the automata usually is less than the
1107 single one. The automaton name is used in define_cpu_unit and
1108 define_query_cpu_unit. All automata should have unique names. */
1109 DEF_RTL_EXPR(DEFINE_AUTOMATON, "define_automaton", "s", RTX_EXTRA)
1111 /* (automata_option string) describes option for generation of
1112 automata. Currently there are the following options:
1114 o "no-minimization" which makes no minimization of automata. This
1115 is only worth to do when we are debugging the description and
1116 need to look more accurately at reservations of states.
1118 o "time" which means printing additional time statistics about
1119 generation of automata.
1121 o "v" which means generation of file describing the result
1122 automata. The file has suffix `.dfa' and can be used for the
1123 description verification and debugging.
1125 o "w" which means generation of warning instead of error for
1126 non-critical errors.
1128 o "ndfa" which makes nondeterministic finite state automata.
1130 o "progress" which means output of a progress bar showing how many
1131 states were generated so far for automaton being processed. */
1132 DEF_RTL_EXPR(AUTOMATA_OPTION, "automata_option", "s", RTX_EXTRA)
1134 /* (define_reservation string string) names reservation (the first
1135 string) of cpu functional units (the 2nd string). Sometimes unit
1136 reservations for different insns contain common parts. In such
1137 case, you can describe common part and use its name (the 1st
1138 parameter) in regular expression in define_insn_reservation. All
1139 define_reservations, define_cpu_units, and define_query_cpu_units
1140 should have unique names which may not be "nothing". */
1141 DEF_RTL_EXPR(DEFINE_RESERVATION, "define_reservation", "ss", RTX_EXTRA)
1143 /* (define_insn_reservation name default_latency condition regexpr)
1144 describes reservation of cpu functional units (the 3nd operand) for
1145 instruction which is selected by the condition (the 2nd parameter).
1146 The first parameter is used for output of debugging information.
1147 The reservations are described by a regular expression according
1148 the following syntax:
1150 regexp = regexp "," oneof
1153 oneof = oneof "|" allof
1156 allof = allof "+" repeat
1159 repeat = element "*" number
1162 element = cpu_function_unit_name
1168 1. "," is used for describing start of the next cycle in
1171 2. "|" is used for describing the reservation described by the
1172 first regular expression *or* the reservation described by the
1173 second regular expression *or* etc.
1175 3. "+" is used for describing the reservation described by the
1176 first regular expression *and* the reservation described by the
1177 second regular expression *and* etc.
1179 4. "*" is used for convenience and simply means sequence in
1180 which the regular expression are repeated NUMBER times with
1181 cycle advancing (see ",").
1183 5. cpu functional unit name which means its reservation.
1185 6. reservation name -- see define_reservation.
1187 7. string "nothing" means no units reservation. */
1189 DEF_RTL_EXPR(DEFINE_INSN_RESERVATION, "define_insn_reservation", "sies", RTX_EXTRA)
1191 /* Expressions used for insn attributes. */
1193 /* Definition of an insn attribute.
1194 1st operand: name of the attribute
1195 2nd operand: comma-separated list of possible attribute values
1196 3rd operand: expression for the default value of the attribute. */
1197 DEF_RTL_EXPR(DEFINE_ATTR, "define_attr", "sse", RTX_EXTRA)
1199 /* Marker for the name of an attribute. */
1200 DEF_RTL_EXPR(ATTR, "attr", "s", RTX_EXTRA)
1202 /* For use in the last (optional) operand of DEFINE_INSN or DEFINE_PEEPHOLE and
1203 in DEFINE_ASM_INSN to specify an attribute to assign to insns matching that
1206 (set_attr "name" "value") is equivalent to
1207 (set (attr "name") (const_string "value")) */
1208 DEF_RTL_EXPR(SET_ATTR, "set_attr", "ss", RTX_EXTRA)
1210 /* In the last operand of DEFINE_INSN and DEFINE_PEEPHOLE, this can be used to
1211 specify that attribute values are to be assigned according to the
1212 alternative matched.
1214 The following three expressions are equivalent:
1216 (set (attr "att") (cond [(eq_attrq "alternative" "1") (const_string "a1")
1217 (eq_attrq "alternative" "2") (const_string "a2")]
1218 (const_string "a3")))
1219 (set_attr_alternative "att" [(const_string "a1") (const_string "a2")
1220 (const_string "a3")])
1221 (set_attr "att" "a1,a2,a3")
1223 DEF_RTL_EXPR(SET_ATTR_ALTERNATIVE, "set_attr_alternative", "sE", RTX_EXTRA)
1225 /* A conditional expression true if the value of the specified attribute of
1226 the current insn equals the specified value. The first operand is the
1227 attribute name and the second is the comparison value. */
1228 DEF_RTL_EXPR(EQ_ATTR, "eq_attr", "ss", RTX_EXTRA)
1230 /* A special case of the above representing a set of alternatives. The first
1231 operand is bitmap of the set, the second one is the default value. */
1232 DEF_RTL_EXPR(EQ_ATTR_ALT, "eq_attr_alt", "ii", RTX_EXTRA)
1234 /* A conditional expression which is true if the specified flag is
1235 true for the insn being scheduled in reorg.
1237 genattr.c defines the following flags which can be tested by
1238 (attr_flag "foo") expressions in eligible_for_delay.
1240 forward, backward, very_likely, likely, very_unlikely, and unlikely. */
1242 DEF_RTL_EXPR (ATTR_FLAG, "attr_flag", "s", RTX_EXTRA)
1244 /* General conditional. The first operand is a vector composed of pairs of
1245 expressions. The first element of each pair is evaluated, in turn.
1246 The value of the conditional is the second expression of the first pair
1247 whose first expression evaluates nonzero. If none of the expressions is
1248 true, the second operand will be used as the value of the conditional. */
1249 DEF_RTL_EXPR(COND, "cond", "Ee", RTX_EXTRA)
1251 #endif /* GENERATOR_FILE */
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