1 /* This file contains the definitions and documentation for the
2 Register Transfer Expressions (rtx's) that make up the
3 Register Transfer Language (rtl) used in the Back End of the GNU compiler.
4 Copyright (C) 1987-2013 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 3, or (at your option) any later
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
23 /* Expression definitions and descriptions for all targets are in this file.
24 Some will not be used for some targets.
26 The fields in the cpp macro call "DEF_RTL_EXPR()"
27 are used to create declarations in the C source of the compiler.
31 1. The internal name of the rtx used in the C source.
32 It is a tag in the enumeration "enum rtx_code" defined in "rtl.h".
33 By convention these are in UPPER_CASE.
35 2. The name of the rtx in the external ASCII format read by
36 read_rtx(), and printed by print_rtx().
37 These names are stored in rtx_name[].
38 By convention these are the internal (field 1) names in lower_case.
40 3. The print format, and type of each rtx->u.fld[] (field) in this rtx.
41 These formats are stored in rtx_format[].
42 The meaning of the formats is documented in front of this array in rtl.c
44 4. The class of the rtx. These are stored in rtx_class and are accessed
45 via the GET_RTX_CLASS macro. They are defined as follows:
48 an rtx code that can be used to represent a constant object
51 an rtx code that can be used to represent an object (e.g, REG, MEM)
53 an rtx code for a comparison (e.g, LT, GT)
55 an rtx code for a commutative comparison (e.g, EQ, NE, ORDERED)
57 an rtx code for a unary arithmetic expression (e.g, NEG, NOT)
59 an rtx code for a commutative binary operation (e.g,, PLUS, MULT)
61 an rtx code for a non-bitfield three input operation (IF_THEN_ELSE)
63 an rtx code for a non-commutative binary operation (e.g., MINUS, DIV)
65 an rtx code for a bit-field operation (ZERO_EXTRACT, SIGN_EXTRACT)
67 an rtx code for a machine insn (INSN, JUMP_INSN, CALL_INSN) or
68 data that will be output as assembly pseudo-ops (DEBUG_INSN)
70 an rtx code for something that matches in insns (e.g, MATCH_DUP)
72 an rtx code for autoincrement addressing modes (e.g. POST_DEC)
76 All of the expressions that appear only in machine descriptions,
77 not in RTL used by the compiler itself, are at the end of the file. */
79 /* Unknown, or no such operation; the enumeration constant should have
81 DEF_RTL_EXPR(UNKNOWN, "UnKnown", "*", RTX_EXTRA)
83 /* Used in the cselib routines to describe a value. Objects of this
84 kind are only allocated in cselib.c, in an alloc pool instead of in
85 GC memory. The only operand of a VALUE is a cselib_val_struct.
86 var-tracking requires this to have a distinct integral value from
87 DECL codes in trees. */
88 DEF_RTL_EXPR(VALUE, "value", "0", RTX_OBJ)
90 /* The RTL generated for a DEBUG_EXPR_DECL. It links back to the
91 DEBUG_EXPR_DECL in the first operand. */
92 DEF_RTL_EXPR(DEBUG_EXPR, "debug_expr", "0", RTX_OBJ)
94 /* ---------------------------------------------------------------------
95 Expressions used in constructing lists.
96 --------------------------------------------------------------------- */
98 /* a linked list of expressions */
99 DEF_RTL_EXPR(EXPR_LIST, "expr_list", "ee", RTX_EXTRA)
101 /* a linked list of instructions.
102 The insns are represented in print by their uids. */
103 DEF_RTL_EXPR(INSN_LIST, "insn_list", "ue", RTX_EXTRA)
105 /* SEQUENCE appears in the result of a `gen_...' function
106 for a DEFINE_EXPAND that wants to make several insns.
107 Its elements are the bodies of the insns that should be made.
108 `emit_insn' takes the SEQUENCE apart and makes separate insns. */
109 DEF_RTL_EXPR(SEQUENCE, "sequence", "E", RTX_EXTRA)
111 /* Represents a non-global base address. This is only used in alias.c. */
112 DEF_RTL_EXPR(ADDRESS, "address", "i", RTX_EXTRA)
114 /* ----------------------------------------------------------------------
115 Expression types used for things in the instruction chain.
117 All formats must start with "iuu" to handle the chain.
118 Each insn expression holds an rtl instruction and its semantics
119 during back-end processing.
120 See macros's in "rtl.h" for the meaning of each rtx->u.fld[].
122 ---------------------------------------------------------------------- */
124 /* An annotation for variable assignment tracking. */
125 DEF_RTL_EXPR(DEBUG_INSN, "debug_insn", "iuuBeiie", RTX_INSN)
127 /* An instruction that cannot jump. */
128 DEF_RTL_EXPR(INSN, "insn", "iuuBeiie", RTX_INSN)
130 /* An instruction that can possibly jump.
131 Fields ( rtx->u.fld[] ) have exact same meaning as INSN's. */
132 DEF_RTL_EXPR(JUMP_INSN, "jump_insn", "iuuBeiie0", RTX_INSN)
134 /* An instruction that can possibly call a subroutine
135 but which will not change which instruction comes next
136 in the current function.
137 Field ( rtx->u.fld[8] ) is CALL_INSN_FUNCTION_USAGE.
138 All other fields ( rtx->u.fld[] ) have exact same meaning as INSN's. */
139 DEF_RTL_EXPR(CALL_INSN, "call_insn", "iuuBeiiee", RTX_INSN)
141 /* Placeholder for tablejump JUMP_INSNs. The pattern of this kind
142 of rtx is always either an ADDR_VEC or an ADDR_DIFF_VEC. These
143 placeholders do not appear as real instructions inside a basic
144 block, but are considered active_insn_p instructions for historical
145 reasons, when jump table data was represented with JUMP_INSNs. */
146 DEF_RTL_EXPR(JUMP_TABLE_DATA, "jump_table_data", "iuuBe0000", RTX_INSN)
148 /* A marker that indicates that control will not flow through. */
149 DEF_RTL_EXPR(BARRIER, "barrier", "iuu00000", RTX_EXTRA)
151 /* Holds a label that is followed by instructions.
153 4: is used in jump.c for the use-count of the label.
154 5: is used in the sh backend.
155 6: is a number that is unique in the entire compilation.
156 7: is the user-given name of the label, if any. */
157 DEF_RTL_EXPR(CODE_LABEL, "code_label", "iuuB00is", RTX_EXTRA)
159 /* Say where in the code a source line starts, for symbol table's sake.
161 4: note-specific data
163 6: unique number if insn_note == note_insn_deleted_label. */
164 DEF_RTL_EXPR(NOTE, "note", "iuuB0ni", RTX_EXTRA)
166 /* ----------------------------------------------------------------------
167 Top level constituents of INSN, JUMP_INSN and CALL_INSN.
168 ---------------------------------------------------------------------- */
170 /* Conditionally execute code.
171 Operand 0 is the condition that if true, the code is executed.
172 Operand 1 is the code to be executed (typically a SET).
174 Semantics are that there are no side effects if the condition
175 is false. This pattern is created automatically by the if_convert
176 pass run after reload or by target-specific splitters. */
177 DEF_RTL_EXPR(COND_EXEC, "cond_exec", "ee", RTX_EXTRA)
179 /* Several operations to be done in parallel (perhaps under COND_EXEC). */
180 DEF_RTL_EXPR(PARALLEL, "parallel", "E", RTX_EXTRA)
182 /* A string that is passed through to the assembler as input.
183 One can obviously pass comments through by using the
184 assembler comment syntax.
185 These occur in an insn all by themselves as the PATTERN.
186 They also appear inside an ASM_OPERANDS
187 as a convenient way to hold a string. */
188 DEF_RTL_EXPR(ASM_INPUT, "asm_input", "si", RTX_EXTRA)
190 /* An assembler instruction with operands.
191 1st operand is the instruction template.
192 2nd operand is the constraint for the output.
193 3rd operand is the number of the output this expression refers to.
194 When an insn stores more than one value, a separate ASM_OPERANDS
195 is made for each output; this integer distinguishes them.
196 4th is a vector of values of input operands.
197 5th is a vector of modes and constraints for the input operands.
198 Each element is an ASM_INPUT containing a constraint string
199 and whose mode indicates the mode of the input operand.
200 6th is a vector of labels that may be branched to by the asm.
201 7th is the source line number. */
202 DEF_RTL_EXPR(ASM_OPERANDS, "asm_operands", "ssiEEEi", RTX_EXTRA)
204 /* A machine-specific operation.
205 1st operand is a vector of operands being used by the operation so that
206 any needed reloads can be done.
207 2nd operand is a unique value saying which of a number of machine-specific
208 operations is to be performed.
209 (Note that the vector must be the first operand because of the way that
210 genrecog.c record positions within an insn.)
212 UNSPEC can occur all by itself in a PATTERN, as a component of a PARALLEL,
213 or inside an expression.
214 UNSPEC by itself or as a component of a PARALLEL
215 is currently considered not deletable.
217 FIXME: Replace all uses of UNSPEC that appears by itself or as a component
218 of a PARALLEL with USE.
220 DEF_RTL_EXPR(UNSPEC, "unspec", "Ei", RTX_EXTRA)
222 /* Similar, but a volatile operation and one which may trap. */
223 DEF_RTL_EXPR(UNSPEC_VOLATILE, "unspec_volatile", "Ei", RTX_EXTRA)
225 /* ----------------------------------------------------------------------
226 Table jump addresses.
227 ---------------------------------------------------------------------- */
229 /* Vector of addresses, stored as full words.
230 Each element is a LABEL_REF to a CODE_LABEL whose address we want. */
231 DEF_RTL_EXPR(ADDR_VEC, "addr_vec", "E", RTX_EXTRA)
233 /* Vector of address differences X0 - BASE, X1 - BASE, ...
234 First operand is BASE; the vector contains the X's.
235 The machine mode of this rtx says how much space to leave
236 for each difference and is adjusted by branch shortening if
237 CASE_VECTOR_SHORTEN_MODE is defined.
238 The third and fourth operands store the target labels with the
239 minimum and maximum addresses respectively.
240 The fifth operand stores flags for use by branch shortening.
241 Set at the start of shorten_branches:
242 min_align: the minimum alignment for any of the target labels.
243 base_after_vec: true iff BASE is after the ADDR_DIFF_VEC.
244 min_after_vec: true iff minimum addr target label is after the ADDR_DIFF_VEC.
245 max_after_vec: true iff maximum addr target label is after the ADDR_DIFF_VEC.
246 min_after_base: true iff minimum address target label is after BASE.
247 max_after_base: true iff maximum address target label is after BASE.
248 Set by the actual branch shortening process:
249 offset_unsigned: true iff offsets have to be treated as unsigned.
250 scale: scaling that is necessary to make offsets fit into the mode.
252 The third, fourth and fifth operands are only valid when
253 CASE_VECTOR_SHORTEN_MODE is defined, and only in an optimizing
255 DEF_RTL_EXPR(ADDR_DIFF_VEC, "addr_diff_vec", "eEee0", RTX_EXTRA)
257 /* Memory prefetch, with attributes supported on some targets.
258 Operand 1 is the address of the memory to fetch.
259 Operand 2 is 1 for a write access, 0 otherwise.
260 Operand 3 is the level of temporal locality; 0 means there is no
261 temporal locality and 1, 2, and 3 are for increasing levels of temporal
264 The attributes specified by operands 2 and 3 are ignored for targets
265 whose prefetch instructions do not support them. */
266 DEF_RTL_EXPR(PREFETCH, "prefetch", "eee", RTX_EXTRA)
268 /* ----------------------------------------------------------------------
269 At the top level of an instruction (perhaps under PARALLEL).
270 ---------------------------------------------------------------------- */
273 Operand 1 is the location (REG, MEM, PC, CC0 or whatever) assigned to.
274 Operand 2 is the value stored there.
275 ALL assignment must use SET.
276 Instructions that do multiple assignments must use multiple SET,
278 DEF_RTL_EXPR(SET, "set", "ee", RTX_EXTRA)
280 /* Indicate something is used in a way that we don't want to explain.
281 For example, subroutine calls will use the register
282 in which the static chain is passed.
284 USE can not appear as an operand of other rtx except for PARALLEL.
285 USE is not deletable, as it indicates that the operand
286 is used in some unknown way. */
287 DEF_RTL_EXPR(USE, "use", "e", RTX_EXTRA)
289 /* Indicate something is clobbered in a way that we don't want to explain.
290 For example, subroutine calls will clobber some physical registers
291 (the ones that are by convention not saved).
293 CLOBBER can not appear as an operand of other rtx except for PARALLEL.
294 CLOBBER of a hard register appearing by itself (not within PARALLEL)
295 is considered undeletable before reload. */
296 DEF_RTL_EXPR(CLOBBER, "clobber", "e", RTX_EXTRA)
298 /* Call a subroutine.
299 Operand 1 is the address to call.
300 Operand 2 is the number of arguments. */
302 DEF_RTL_EXPR(CALL, "call", "ee", RTX_EXTRA)
304 /* Return from a subroutine. */
306 DEF_RTL_EXPR(RETURN, "return", "", RTX_EXTRA)
308 /* Like RETURN, but truly represents only a function return, while
309 RETURN may represent an insn that also performs other functions
310 of the function epilogue. Like RETURN, this may also occur in
311 conditional jumps. */
312 DEF_RTL_EXPR(SIMPLE_RETURN, "simple_return", "", RTX_EXTRA)
314 /* Special for EH return from subroutine. */
316 DEF_RTL_EXPR(EH_RETURN, "eh_return", "", RTX_EXTRA)
319 Operand 1 is the condition.
320 Operand 2 is the trap code.
321 For an unconditional trap, make the condition (const_int 1). */
322 DEF_RTL_EXPR(TRAP_IF, "trap_if", "ee", RTX_EXTRA)
324 /* ----------------------------------------------------------------------
325 Primitive values for use in expressions.
326 ---------------------------------------------------------------------- */
328 /* numeric integer constant */
329 DEF_RTL_EXPR(CONST_INT, "const_int", "w", RTX_CONST_OBJ)
331 /* fixed-point constant */
332 DEF_RTL_EXPR(CONST_FIXED, "const_fixed", "www", RTX_CONST_OBJ)
334 /* numeric floating point or integer constant. If the mode is
335 VOIDmode it is an int otherwise it has a floating point mode and a
336 floating point value. Operands hold the value. They are all 'w'
337 and there may be from 2 to 6; see real.h. */
338 DEF_RTL_EXPR(CONST_DOUBLE, "const_double", CONST_DOUBLE_FORMAT, RTX_CONST_OBJ)
340 /* Describes a vector constant. */
341 DEF_RTL_EXPR(CONST_VECTOR, "const_vector", "E", RTX_CONST_OBJ)
343 /* String constant. Used for attributes in machine descriptions and
344 for special cases in DWARF2 debug output. NOT used for source-
345 language string constants. */
346 DEF_RTL_EXPR(CONST_STRING, "const_string", "s", RTX_OBJ)
348 /* This is used to encapsulate an expression whose value is constant
349 (such as the sum of a SYMBOL_REF and a CONST_INT) so that it will be
350 recognized as a constant operand rather than by arithmetic instructions. */
352 DEF_RTL_EXPR(CONST, "const", "e", RTX_CONST_OBJ)
354 /* program counter. Ordinary jumps are represented
355 by a SET whose first operand is (PC). */
356 DEF_RTL_EXPR(PC, "pc", "", RTX_OBJ)
358 /* A register. The "operand" is the register number, accessed with
359 the REGNO macro. If this number is less than FIRST_PSEUDO_REGISTER
360 than a hardware register is being referred to. The second operand
361 holds the original register number - this will be different for a
362 pseudo register that got turned into a hard register. The third
363 operand points to a reg_attrs structure.
364 This rtx needs to have as many (or more) fields as a MEM, since we
365 can change REG rtx's into MEMs during reload. */
366 DEF_RTL_EXPR(REG, "reg", "i00", RTX_OBJ)
368 /* A scratch register. This represents a register used only within a
369 single insn. It will be turned into a REG during register allocation
370 or reload unless the constraint indicates that the register won't be
371 needed, in which case it can remain a SCRATCH. This code is
372 marked as having one operand so it can be turned into a REG. */
373 DEF_RTL_EXPR(SCRATCH, "scratch", "0", RTX_OBJ)
375 /* A reference to a part of another value. The first operand is the
376 complete value and the second is the byte offset of the selected part. */
377 DEF_RTL_EXPR(SUBREG, "subreg", "ei", RTX_EXTRA)
379 /* This one-argument rtx is used for move instructions
380 that are guaranteed to alter only the low part of a destination.
381 Thus, (SET (SUBREG:HI (REG...)) (MEM:HI ...))
382 has an unspecified effect on the high part of REG,
383 but (SET (STRICT_LOW_PART (SUBREG:HI (REG...))) (MEM:HI ...))
384 is guaranteed to alter only the bits of REG that are in HImode.
386 The actual instruction used is probably the same in both cases,
387 but the register constraints may be tighter when STRICT_LOW_PART
390 DEF_RTL_EXPR(STRICT_LOW_PART, "strict_low_part", "e", RTX_EXTRA)
392 /* (CONCAT a b) represents the virtual concatenation of a and b
393 to make a value that has as many bits as a and b put together.
394 This is used for complex values. Normally it appears only
395 in DECL_RTLs and during RTL generation, but not in the insn chain. */
396 DEF_RTL_EXPR(CONCAT, "concat", "ee", RTX_OBJ)
398 /* (CONCATN [a1 a2 ... an]) represents the virtual concatenation of
399 all An to make a value. This is an extension of CONCAT to larger
400 number of components. Like CONCAT, it should not appear in the
401 insn chain. Every element of the CONCATN is the same size. */
402 DEF_RTL_EXPR(CONCATN, "concatn", "E", RTX_OBJ)
404 /* A memory location; operand is the address. The second operand is the
405 alias set to which this MEM belongs. We use `0' instead of `w' for this
406 field so that the field need not be specified in machine descriptions. */
407 DEF_RTL_EXPR(MEM, "mem", "e0", RTX_OBJ)
409 /* Reference to an assembler label in the code for this function.
410 The operand is a CODE_LABEL found in the insn chain. */
411 DEF_RTL_EXPR(LABEL_REF, "label_ref", "u", RTX_CONST_OBJ)
413 /* Reference to a named label:
414 Operand 0: label name
415 Operand 1: flags (see SYMBOL_FLAG_* in rtl.h)
416 Operand 2: tree from which this symbol is derived, or null.
417 This is either a DECL node, or some kind of constant. */
418 DEF_RTL_EXPR(SYMBOL_REF, "symbol_ref", "s00", RTX_CONST_OBJ)
420 /* The condition code register is represented, in our imagination,
421 as a register holding a value that can be compared to zero.
422 In fact, the machine has already compared them and recorded the
423 results; but instructions that look at the condition code
424 pretend to be looking at the entire value and comparing it. */
425 DEF_RTL_EXPR(CC0, "cc0", "", RTX_OBJ)
427 /* ----------------------------------------------------------------------
428 Expressions for operators in an rtl pattern
429 ---------------------------------------------------------------------- */
431 /* if_then_else. This is used in representing ordinary
432 conditional jump instructions.
437 DEF_RTL_EXPR(IF_THEN_ELSE, "if_then_else", "eee", RTX_TERNARY)
439 /* Comparison, produces a condition code result. */
440 DEF_RTL_EXPR(COMPARE, "compare", "ee", RTX_BIN_ARITH)
443 DEF_RTL_EXPR(PLUS, "plus", "ee", RTX_COMM_ARITH)
445 /* Operand 0 minus operand 1. */
446 DEF_RTL_EXPR(MINUS, "minus", "ee", RTX_BIN_ARITH)
448 /* Minus operand 0. */
449 DEF_RTL_EXPR(NEG, "neg", "e", RTX_UNARY)
451 DEF_RTL_EXPR(MULT, "mult", "ee", RTX_COMM_ARITH)
453 /* Multiplication with signed saturation */
454 DEF_RTL_EXPR(SS_MULT, "ss_mult", "ee", RTX_COMM_ARITH)
455 /* Multiplication with unsigned saturation */
456 DEF_RTL_EXPR(US_MULT, "us_mult", "ee", RTX_COMM_ARITH)
458 /* Operand 0 divided by operand 1. */
459 DEF_RTL_EXPR(DIV, "div", "ee", RTX_BIN_ARITH)
460 /* Division with signed saturation */
461 DEF_RTL_EXPR(SS_DIV, "ss_div", "ee", RTX_BIN_ARITH)
462 /* Division with unsigned saturation */
463 DEF_RTL_EXPR(US_DIV, "us_div", "ee", RTX_BIN_ARITH)
465 /* Remainder of operand 0 divided by operand 1. */
466 DEF_RTL_EXPR(MOD, "mod", "ee", RTX_BIN_ARITH)
468 /* Unsigned divide and remainder. */
469 DEF_RTL_EXPR(UDIV, "udiv", "ee", RTX_BIN_ARITH)
470 DEF_RTL_EXPR(UMOD, "umod", "ee", RTX_BIN_ARITH)
472 /* Bitwise operations. */
473 DEF_RTL_EXPR(AND, "and", "ee", RTX_COMM_ARITH)
474 DEF_RTL_EXPR(IOR, "ior", "ee", RTX_COMM_ARITH)
475 DEF_RTL_EXPR(XOR, "xor", "ee", RTX_COMM_ARITH)
476 DEF_RTL_EXPR(NOT, "not", "e", RTX_UNARY)
479 0: value to be shifted.
480 1: number of bits. */
481 DEF_RTL_EXPR(ASHIFT, "ashift", "ee", RTX_BIN_ARITH) /* shift left */
482 DEF_RTL_EXPR(ROTATE, "rotate", "ee", RTX_BIN_ARITH) /* rotate left */
483 DEF_RTL_EXPR(ASHIFTRT, "ashiftrt", "ee", RTX_BIN_ARITH) /* arithmetic shift right */
484 DEF_RTL_EXPR(LSHIFTRT, "lshiftrt", "ee", RTX_BIN_ARITH) /* logical shift right */
485 DEF_RTL_EXPR(ROTATERT, "rotatert", "ee", RTX_BIN_ARITH) /* rotate right */
487 /* Minimum and maximum values of two operands. We need both signed and
488 unsigned forms. (We cannot use MIN for SMIN because it conflicts
489 with a macro of the same name.) The signed variants should be used
490 with floating point. Further, if both operands are zeros, or if either
491 operand is NaN, then it is unspecified which of the two operands is
492 returned as the result. */
494 DEF_RTL_EXPR(SMIN, "smin", "ee", RTX_COMM_ARITH)
495 DEF_RTL_EXPR(SMAX, "smax", "ee", RTX_COMM_ARITH)
496 DEF_RTL_EXPR(UMIN, "umin", "ee", RTX_COMM_ARITH)
497 DEF_RTL_EXPR(UMAX, "umax", "ee", RTX_COMM_ARITH)
499 /* These unary operations are used to represent incrementation
500 and decrementation as they occur in memory addresses.
501 The amount of increment or decrement are not represented
502 because they can be understood from the machine-mode of the
503 containing MEM. These operations exist in only two cases:
504 1. pushes onto the stack.
505 2. created automatically by the auto-inc-dec pass. */
506 DEF_RTL_EXPR(PRE_DEC, "pre_dec", "e", RTX_AUTOINC)
507 DEF_RTL_EXPR(PRE_INC, "pre_inc", "e", RTX_AUTOINC)
508 DEF_RTL_EXPR(POST_DEC, "post_dec", "e", RTX_AUTOINC)
509 DEF_RTL_EXPR(POST_INC, "post_inc", "e", RTX_AUTOINC)
511 /* These binary operations are used to represent generic address
512 side-effects in memory addresses, except for simple incrementation
513 or decrementation which use the above operations. They are
514 created automatically by the life_analysis pass in flow.c.
515 The first operand is a REG which is used as the address.
516 The second operand is an expression that is assigned to the
517 register, either before (PRE_MODIFY) or after (POST_MODIFY)
518 evaluating the address.
519 Currently, the compiler can only handle second operands of the
520 form (plus (reg) (reg)) and (plus (reg) (const_int)), where
521 the first operand of the PLUS has to be the same register as
522 the first operand of the *_MODIFY. */
523 DEF_RTL_EXPR(PRE_MODIFY, "pre_modify", "ee", RTX_AUTOINC)
524 DEF_RTL_EXPR(POST_MODIFY, "post_modify", "ee", RTX_AUTOINC)
526 /* Comparison operations. The ordered comparisons exist in two
527 flavors, signed and unsigned. */
528 DEF_RTL_EXPR(NE, "ne", "ee", RTX_COMM_COMPARE)
529 DEF_RTL_EXPR(EQ, "eq", "ee", RTX_COMM_COMPARE)
530 DEF_RTL_EXPR(GE, "ge", "ee", RTX_COMPARE)
531 DEF_RTL_EXPR(GT, "gt", "ee", RTX_COMPARE)
532 DEF_RTL_EXPR(LE, "le", "ee", RTX_COMPARE)
533 DEF_RTL_EXPR(LT, "lt", "ee", RTX_COMPARE)
534 DEF_RTL_EXPR(GEU, "geu", "ee", RTX_COMPARE)
535 DEF_RTL_EXPR(GTU, "gtu", "ee", RTX_COMPARE)
536 DEF_RTL_EXPR(LEU, "leu", "ee", RTX_COMPARE)
537 DEF_RTL_EXPR(LTU, "ltu", "ee", RTX_COMPARE)
539 /* Additional floating point unordered comparison flavors. */
540 DEF_RTL_EXPR(UNORDERED, "unordered", "ee", RTX_COMM_COMPARE)
541 DEF_RTL_EXPR(ORDERED, "ordered", "ee", RTX_COMM_COMPARE)
543 /* These are equivalent to unordered or ... */
544 DEF_RTL_EXPR(UNEQ, "uneq", "ee", RTX_COMM_COMPARE)
545 DEF_RTL_EXPR(UNGE, "unge", "ee", RTX_COMPARE)
546 DEF_RTL_EXPR(UNGT, "ungt", "ee", RTX_COMPARE)
547 DEF_RTL_EXPR(UNLE, "unle", "ee", RTX_COMPARE)
548 DEF_RTL_EXPR(UNLT, "unlt", "ee", RTX_COMPARE)
550 /* This is an ordered NE, ie !UNEQ, ie false for NaN. */
551 DEF_RTL_EXPR(LTGT, "ltgt", "ee", RTX_COMM_COMPARE)
553 /* Represents the result of sign-extending the sole operand.
554 The machine modes of the operand and of the SIGN_EXTEND expression
555 determine how much sign-extension is going on. */
556 DEF_RTL_EXPR(SIGN_EXTEND, "sign_extend", "e", RTX_UNARY)
558 /* Similar for zero-extension (such as unsigned short to int). */
559 DEF_RTL_EXPR(ZERO_EXTEND, "zero_extend", "e", RTX_UNARY)
561 /* Similar but here the operand has a wider mode. */
562 DEF_RTL_EXPR(TRUNCATE, "truncate", "e", RTX_UNARY)
564 /* Similar for extending floating-point values (such as SFmode to DFmode). */
565 DEF_RTL_EXPR(FLOAT_EXTEND, "float_extend", "e", RTX_UNARY)
566 DEF_RTL_EXPR(FLOAT_TRUNCATE, "float_truncate", "e", RTX_UNARY)
568 /* Conversion of fixed point operand to floating point value. */
569 DEF_RTL_EXPR(FLOAT, "float", "e", RTX_UNARY)
571 /* With fixed-point machine mode:
572 Conversion of floating point operand to fixed point value.
573 Value is defined only when the operand's value is an integer.
574 With floating-point machine mode (and operand with same mode):
575 Operand is rounded toward zero to produce an integer value
576 represented in floating point. */
577 DEF_RTL_EXPR(FIX, "fix", "e", RTX_UNARY)
579 /* Conversion of unsigned fixed point operand to floating point value. */
580 DEF_RTL_EXPR(UNSIGNED_FLOAT, "unsigned_float", "e", RTX_UNARY)
582 /* With fixed-point machine mode:
583 Conversion of floating point operand to *unsigned* fixed point value.
584 Value is defined only when the operand's value is an integer. */
585 DEF_RTL_EXPR(UNSIGNED_FIX, "unsigned_fix", "e", RTX_UNARY)
587 /* Conversions involving fractional fixed-point types without saturation,
589 fractional to fractional (of different precision),
590 signed integer to fractional,
591 fractional to signed integer,
592 floating point to fractional,
593 fractional to floating point.
594 NOTE: fractional can be either signed or unsigned for conversions. */
595 DEF_RTL_EXPR(FRACT_CONVERT, "fract_convert", "e", RTX_UNARY)
597 /* Conversions involving fractional fixed-point types and unsigned integer
598 without saturation, including:
599 unsigned integer to fractional,
600 fractional to unsigned integer.
601 NOTE: fractional can be either signed or unsigned for conversions. */
602 DEF_RTL_EXPR(UNSIGNED_FRACT_CONVERT, "unsigned_fract_convert", "e", RTX_UNARY)
604 /* Conversions involving fractional fixed-point types with saturation,
606 fractional to fractional (of different precision),
607 signed integer to fractional,
608 floating point to fractional.
609 NOTE: fractional can be either signed or unsigned for conversions. */
610 DEF_RTL_EXPR(SAT_FRACT, "sat_fract", "e", RTX_UNARY)
612 /* Conversions involving fractional fixed-point types and unsigned integer
613 with saturation, including:
614 unsigned integer to fractional.
615 NOTE: fractional can be either signed or unsigned for conversions. */
616 DEF_RTL_EXPR(UNSIGNED_SAT_FRACT, "unsigned_sat_fract", "e", RTX_UNARY)
619 DEF_RTL_EXPR(ABS, "abs", "e", RTX_UNARY)
622 DEF_RTL_EXPR(SQRT, "sqrt", "e", RTX_UNARY)
625 DEF_RTL_EXPR(BSWAP, "bswap", "e", RTX_UNARY)
627 /* Find first bit that is set.
628 Value is 1 + number of trailing zeros in the arg.,
630 DEF_RTL_EXPR(FFS, "ffs", "e", RTX_UNARY)
632 /* Count number of leading redundant sign bits (number of leading
633 sign bits minus one). */
634 DEF_RTL_EXPR(CLRSB, "clrsb", "e", RTX_UNARY)
636 /* Count leading zeros. */
637 DEF_RTL_EXPR(CLZ, "clz", "e", RTX_UNARY)
639 /* Count trailing zeros. */
640 DEF_RTL_EXPR(CTZ, "ctz", "e", RTX_UNARY)
642 /* Population count (number of 1 bits). */
643 DEF_RTL_EXPR(POPCOUNT, "popcount", "e", RTX_UNARY)
645 /* Population parity (number of 1 bits modulo 2). */
646 DEF_RTL_EXPR(PARITY, "parity", "e", RTX_UNARY)
648 /* Reference to a signed bit-field of specified size and position.
649 Operand 0 is the memory unit (usually SImode or QImode) which
650 contains the field's first bit. Operand 1 is the width, in bits.
651 Operand 2 is the number of bits in the memory unit before the
652 first bit of this field.
653 If BITS_BIG_ENDIAN is defined, the first bit is the msb and
654 operand 2 counts from the msb of the memory unit.
655 Otherwise, the first bit is the lsb and operand 2 counts from
656 the lsb of the memory unit.
657 This kind of expression can not appear as an lvalue in RTL. */
658 DEF_RTL_EXPR(SIGN_EXTRACT, "sign_extract", "eee", RTX_BITFIELD_OPS)
660 /* Similar for unsigned bit-field.
661 But note! This kind of expression _can_ appear as an lvalue. */
662 DEF_RTL_EXPR(ZERO_EXTRACT, "zero_extract", "eee", RTX_BITFIELD_OPS)
664 /* For RISC machines. These save memory when splitting insns. */
666 /* HIGH are the high-order bits of a constant expression. */
667 DEF_RTL_EXPR(HIGH, "high", "e", RTX_CONST_OBJ)
669 /* LO_SUM is the sum of a register and the low-order bits
670 of a constant expression. */
671 DEF_RTL_EXPR(LO_SUM, "lo_sum", "ee", RTX_OBJ)
673 /* Describes a merge operation between two vector values.
674 Operands 0 and 1 are the vectors to be merged, operand 2 is a bitmask
675 that specifies where the parts of the result are taken from. Set bits
676 indicate operand 0, clear bits indicate operand 1. The parts are defined
677 by the mode of the vectors. */
678 DEF_RTL_EXPR(VEC_MERGE, "vec_merge", "eee", RTX_TERNARY)
680 /* Describes an operation that selects parts of a vector.
681 Operands 0 is the source vector, operand 1 is a PARALLEL that contains
682 a CONST_INT for each of the subparts of the result vector, giving the
683 number of the source subpart that should be stored into it. */
684 DEF_RTL_EXPR(VEC_SELECT, "vec_select", "ee", RTX_BIN_ARITH)
686 /* Describes a vector concat operation. Operands 0 and 1 are the source
687 vectors, the result is a vector that is as long as operands 0 and 1
688 combined and is the concatenation of the two source vectors. */
689 DEF_RTL_EXPR(VEC_CONCAT, "vec_concat", "ee", RTX_BIN_ARITH)
691 /* Describes an operation that converts a small vector into a larger one by
692 duplicating the input values. The output vector mode must have the same
693 submodes as the input vector mode, and the number of output parts must be
694 an integer multiple of the number of input parts. */
695 DEF_RTL_EXPR(VEC_DUPLICATE, "vec_duplicate", "e", RTX_UNARY)
697 /* Addition with signed saturation */
698 DEF_RTL_EXPR(SS_PLUS, "ss_plus", "ee", RTX_COMM_ARITH)
700 /* Addition with unsigned saturation */
701 DEF_RTL_EXPR(US_PLUS, "us_plus", "ee", RTX_COMM_ARITH)
703 /* Operand 0 minus operand 1, with signed saturation. */
704 DEF_RTL_EXPR(SS_MINUS, "ss_minus", "ee", RTX_BIN_ARITH)
706 /* Negation with signed saturation. */
707 DEF_RTL_EXPR(SS_NEG, "ss_neg", "e", RTX_UNARY)
708 /* Negation with unsigned saturation. */
709 DEF_RTL_EXPR(US_NEG, "us_neg", "e", RTX_UNARY)
711 /* Absolute value with signed saturation. */
712 DEF_RTL_EXPR(SS_ABS, "ss_abs", "e", RTX_UNARY)
714 /* Shift left with signed saturation. */
715 DEF_RTL_EXPR(SS_ASHIFT, "ss_ashift", "ee", RTX_BIN_ARITH)
717 /* Shift left with unsigned saturation. */
718 DEF_RTL_EXPR(US_ASHIFT, "us_ashift", "ee", RTX_BIN_ARITH)
720 /* Operand 0 minus operand 1, with unsigned saturation. */
721 DEF_RTL_EXPR(US_MINUS, "us_minus", "ee", RTX_BIN_ARITH)
723 /* Signed saturating truncate. */
724 DEF_RTL_EXPR(SS_TRUNCATE, "ss_truncate", "e", RTX_UNARY)
726 /* Unsigned saturating truncate. */
727 DEF_RTL_EXPR(US_TRUNCATE, "us_truncate", "e", RTX_UNARY)
729 /* Floating point multiply/add combined instruction. */
730 DEF_RTL_EXPR(FMA, "fma", "eee", RTX_TERNARY)
732 /* Information about the variable and its location. */
733 /* Changed 'te' to 'tei'; the 'i' field is for recording
734 initialization status of variables. */
735 DEF_RTL_EXPR(VAR_LOCATION, "var_location", "tei", RTX_EXTRA)
737 /* Used in VAR_LOCATION for a pointer to a decl that is no longer
739 DEF_RTL_EXPR(DEBUG_IMPLICIT_PTR, "debug_implicit_ptr", "t", RTX_OBJ)
741 /* Represents value that argument had on function entry. The
742 single argument is the DECL_INCOMING_RTL of the corresponding
744 DEF_RTL_EXPR(ENTRY_VALUE, "entry_value", "0", RTX_OBJ)
746 /* Used in VAR_LOCATION for a reference to a parameter that has
747 been optimized away completely. */
748 DEF_RTL_EXPR(DEBUG_PARAMETER_REF, "debug_parameter_ref", "t", RTX_OBJ)
750 /* All expressions from this point forward appear only in machine
752 #ifdef GENERATOR_FILE
754 /* Pattern-matching operators: */
756 /* Use the function named by the second arg (the string)
757 as a predicate; if matched, store the structure that was matched
758 in the operand table at index specified by the first arg (the integer).
759 If the second arg is the null string, the structure is just stored.
761 A third string argument indicates to the register allocator restrictions
762 on where the operand can be allocated.
764 If the target needs no restriction on any instruction this field should
767 The string is prepended by:
768 '=' to indicate the operand is only written to.
769 '+' to indicate the operand is both read and written to.
771 Each character in the string represents an allocable class for an operand.
772 'g' indicates the operand can be any valid class.
773 'i' indicates the operand can be immediate (in the instruction) data.
774 'r' indicates the operand can be in a register.
775 'm' indicates the operand can be in memory.
776 'o' a subset of the 'm' class. Those memory addressing modes that
777 can be offset at compile time (have a constant added to them).
779 Other characters indicate target dependent operand classes and
780 are described in each target's machine description.
782 For instructions with more than one operand, sets of classes can be
783 separated by a comma to indicate the appropriate multi-operand constraints.
784 There must be a 1 to 1 correspondence between these sets of classes in
785 all operands for an instruction.
787 DEF_RTL_EXPR(MATCH_OPERAND, "match_operand", "iss", RTX_MATCH)
789 /* Match a SCRATCH or a register. When used to generate rtl, a
790 SCRATCH is generated. As for MATCH_OPERAND, the mode specifies
791 the desired mode and the first argument is the operand number.
792 The second argument is the constraint. */
793 DEF_RTL_EXPR(MATCH_SCRATCH, "match_scratch", "is", RTX_MATCH)
795 /* Apply a predicate, AND match recursively the operands of the rtx.
796 Operand 0 is the operand-number, as in match_operand.
797 Operand 1 is a predicate to apply (as a string, a function name).
798 Operand 2 is a vector of expressions, each of which must match
799 one subexpression of the rtx this construct is matching. */
800 DEF_RTL_EXPR(MATCH_OPERATOR, "match_operator", "isE", RTX_MATCH)
802 /* Match a PARALLEL of arbitrary length. The predicate is applied
803 to the PARALLEL and the initial expressions in the PARALLEL are matched.
804 Operand 0 is the operand-number, as in match_operand.
805 Operand 1 is a predicate to apply to the PARALLEL.
806 Operand 2 is a vector of expressions, each of which must match the
807 corresponding element in the PARALLEL. */
808 DEF_RTL_EXPR(MATCH_PARALLEL, "match_parallel", "isE", RTX_MATCH)
810 /* Match only something equal to what is stored in the operand table
811 at the index specified by the argument. Use with MATCH_OPERAND. */
812 DEF_RTL_EXPR(MATCH_DUP, "match_dup", "i", RTX_MATCH)
814 /* Match only something equal to what is stored in the operand table
815 at the index specified by the argument. Use with MATCH_OPERATOR. */
816 DEF_RTL_EXPR(MATCH_OP_DUP, "match_op_dup", "iE", RTX_MATCH)
818 /* Match only something equal to what is stored in the operand table
819 at the index specified by the argument. Use with MATCH_PARALLEL. */
820 DEF_RTL_EXPR(MATCH_PAR_DUP, "match_par_dup", "iE", RTX_MATCH)
822 /* Appears only in define_predicate/define_special_predicate
823 expressions. Evaluates true only if the operand has an RTX code
824 from the set given by the argument (a comma-separated list). If the
825 second argument is present and nonempty, it is a sequence of digits
826 and/or letters which indicates the subexpression to test, using the
827 same syntax as genextract/genrecog's location strings: 0-9 for
828 XEXP (op, n), a-z for XVECEXP (op, 0, n); each character applies to
829 the result of the one before it. */
830 DEF_RTL_EXPR(MATCH_CODE, "match_code", "ss", RTX_MATCH)
832 /* Used to inject a C conditional expression into an .md file. It can
833 appear in a predicate definition or an attribute expression. */
834 DEF_RTL_EXPR(MATCH_TEST, "match_test", "s", RTX_MATCH)
836 /* Insn (and related) definitions. */
838 /* Definition of the pattern for one kind of instruction.
840 0: names this instruction.
841 If the name is the null string, the instruction is in the
842 machine description just to be recognized, and will never be emitted by
843 the tree to rtl expander.
845 2: is a string which is a C expression
846 giving an additional condition for recognizing this pattern.
847 A null string means no extra condition.
848 3: is the action to execute if this pattern is matched.
849 If this assembler code template starts with a * then it is a fragment of
850 C code to run to decide on a template to use. Otherwise, it is the
852 4: optionally, a vector of attributes for this insn.
854 DEF_RTL_EXPR(DEFINE_INSN, "define_insn", "sEsTV", RTX_EXTRA)
856 /* Definition of a peephole optimization.
857 1st operand: vector of insn patterns to match
858 2nd operand: C expression that must be true
859 3rd operand: template or C code to produce assembler output.
860 4: optionally, a vector of attributes for this insn.
862 This form is deprecated; use define_peephole2 instead. */
863 DEF_RTL_EXPR(DEFINE_PEEPHOLE, "define_peephole", "EsTV", RTX_EXTRA)
865 /* Definition of a split operation.
866 1st operand: insn pattern to match
867 2nd operand: C expression that must be true
868 3rd operand: vector of insn patterns to place into a SEQUENCE
869 4th operand: optionally, some C code to execute before generating the
870 insns. This might, for example, create some RTX's and store them in
871 elements of `recog_data.operand' for use by the vector of
873 (`operands' is an alias here for `recog_data.operand'). */
874 DEF_RTL_EXPR(DEFINE_SPLIT, "define_split", "EsES", RTX_EXTRA)
876 /* Definition of an insn and associated split.
877 This is the concatenation, with a few modifications, of a define_insn
878 and a define_split which share the same pattern.
880 0: names this instruction.
881 If the name is the null string, the instruction is in the
882 machine description just to be recognized, and will never be emitted by
883 the tree to rtl expander.
885 2: is a string which is a C expression
886 giving an additional condition for recognizing this pattern.
887 A null string means no extra condition.
888 3: is the action to execute if this pattern is matched.
889 If this assembler code template starts with a * then it is a fragment of
890 C code to run to decide on a template to use. Otherwise, it is the
892 4: C expression that must be true for split. This may start with "&&"
893 in which case the split condition is the logical and of the insn
894 condition and what follows the "&&" of this operand.
895 5: vector of insn patterns to place into a SEQUENCE
896 6: optionally, some C code to execute before generating the
897 insns. This might, for example, create some RTX's and store them in
898 elements of `recog_data.operand' for use by the vector of
900 (`operands' is an alias here for `recog_data.operand').
901 7: optionally, a vector of attributes for this insn. */
902 DEF_RTL_EXPR(DEFINE_INSN_AND_SPLIT, "define_insn_and_split", "sEsTsESV", RTX_EXTRA)
904 /* Definition of an RTL peephole operation.
905 Follows the same arguments as define_split. */
906 DEF_RTL_EXPR(DEFINE_PEEPHOLE2, "define_peephole2", "EsES", RTX_EXTRA)
908 /* Define how to generate multiple insns for a standard insn name.
909 1st operand: the insn name.
910 2nd operand: vector of insn-patterns.
911 Use match_operand to substitute an element of `recog_data.operand'.
912 3rd operand: C expression that must be true for this to be available.
913 This may not test any operands.
914 4th operand: Extra C code to execute before generating the insns.
915 This might, for example, create some RTX's and store them in
916 elements of `recog_data.operand' for use by the vector of
918 (`operands' is an alias here for `recog_data.operand').
919 5th: optionally, a vector of attributes for this expand. */
920 DEF_RTL_EXPR(DEFINE_EXPAND, "define_expand", "sEssV", RTX_EXTRA)
922 /* Define a requirement for delay slots.
923 1st operand: Condition involving insn attributes that, if true,
924 indicates that the insn requires the number of delay slots
926 2nd operand: Vector whose length is the three times the number of delay
928 Each entry gives three conditions, each involving attributes.
929 The first must be true for an insn to occupy that delay slot
930 location. The second is true for all insns that can be
931 annulled if the branch is true and the third is true for all
932 insns that can be annulled if the branch is false.
934 Multiple DEFINE_DELAYs may be present. They indicate differing
935 requirements for delay slots. */
936 DEF_RTL_EXPR(DEFINE_DELAY, "define_delay", "eE", RTX_EXTRA)
938 /* Define attribute computation for `asm' instructions. */
939 DEF_RTL_EXPR(DEFINE_ASM_ATTRIBUTES, "define_asm_attributes", "V", RTX_EXTRA)
941 /* Definition of a conditional execution meta operation. Automatically
942 generates new instances of DEFINE_INSN, selected by having attribute
943 "predicable" true. The new pattern will contain a COND_EXEC and the
944 predicate at top-level.
947 0: The predicate pattern. The top-level form should match a
948 relational operator. Operands should have only one alternative.
949 1: A C expression giving an additional condition for recognizing
950 the generated pattern.
951 2: A template or C code to produce assembler output. */
952 DEF_RTL_EXPR(DEFINE_COND_EXEC, "define_cond_exec", "Ess", RTX_EXTRA)
954 /* Definition of an operand predicate. The difference between
955 DEFINE_PREDICATE and DEFINE_SPECIAL_PREDICATE is that genrecog will
956 not warn about a match_operand with no mode if it has a predicate
957 defined with DEFINE_SPECIAL_PREDICATE.
960 0: The name of the predicate.
961 1: A boolean expression which computes whether or not the predicate
962 matches. This expression can use IOR, AND, NOT, MATCH_OPERAND,
963 MATCH_CODE, and MATCH_TEST. It must be specific enough that genrecog
964 can calculate the set of RTX codes that can possibly match.
965 2: A C function body which must return true for the predicate to match.
966 Optional. Use this when the test is too complicated to fit into a
967 match_test expression. */
968 DEF_RTL_EXPR(DEFINE_PREDICATE, "define_predicate", "ses", RTX_EXTRA)
969 DEF_RTL_EXPR(DEFINE_SPECIAL_PREDICATE, "define_special_predicate", "ses", RTX_EXTRA)
971 /* Definition of a register operand constraint. This simply maps the
972 constraint string to a register class.
975 0: The name of the constraint (often, but not always, a single letter).
976 1: A C expression which evaluates to the appropriate register class for
977 this constraint. If this is not just a constant, it should look only
978 at -m switches and the like.
979 2: A docstring for this constraint, in Texinfo syntax; not currently
980 used, in future will be incorporated into the manual's list of
981 machine-specific operand constraints. */
982 DEF_RTL_EXPR(DEFINE_REGISTER_CONSTRAINT, "define_register_constraint", "sss", RTX_EXTRA)
984 /* Definition of a non-register operand constraint. These look at the
985 operand and decide whether it fits the constraint.
987 DEFINE_CONSTRAINT gets no special treatment if it fails to match.
988 It is appropriate for constant-only constraints, and most others.
990 DEFINE_MEMORY_CONSTRAINT tells reload that this constraint can be made
991 to match, if it doesn't already, by converting the operand to the form
992 (mem (reg X)) where X is a base register. It is suitable for constraints
993 that describe a subset of all memory references.
995 DEFINE_ADDRESS_CONSTRAINT tells reload that this constraint can be made
996 to match, if it doesn't already, by converting the operand to the form
997 (reg X) where X is a base register. It is suitable for constraints that
998 describe a subset of all address references.
1000 When in doubt, use plain DEFINE_CONSTRAINT.
1003 0: The name of the constraint (often, but not always, a single letter).
1004 1: A docstring for this constraint, in Texinfo syntax; not currently
1005 used, in future will be incorporated into the manual's list of
1006 machine-specific operand constraints.
1007 2: A boolean expression which computes whether or not the constraint
1008 matches. It should follow the same rules as a define_predicate
1009 expression, including the bit about specifying the set of RTX codes
1010 that could possibly match. MATCH_TEST subexpressions may make use of
1012 `op' - the RTL object defining the operand.
1013 `mode' - the mode of `op'.
1014 `ival' - INTVAL(op), if op is a CONST_INT.
1015 `hval' - CONST_DOUBLE_HIGH(op), if op is an integer CONST_DOUBLE.
1016 `lval' - CONST_DOUBLE_LOW(op), if op is an integer CONST_DOUBLE.
1017 `rval' - CONST_DOUBLE_REAL_VALUE(op), if op is a floating-point
1019 Do not use ival/hval/lval/rval if op is not the appropriate kind of
1021 DEF_RTL_EXPR(DEFINE_CONSTRAINT, "define_constraint", "sse", RTX_EXTRA)
1022 DEF_RTL_EXPR(DEFINE_MEMORY_CONSTRAINT, "define_memory_constraint", "sse", RTX_EXTRA)
1023 DEF_RTL_EXPR(DEFINE_ADDRESS_CONSTRAINT, "define_address_constraint", "sse", RTX_EXTRA)
1026 /* Constructions for CPU pipeline description described by NDFAs. */
1028 /* (define_cpu_unit string [string]) describes cpu functional
1029 units (separated by comma).
1031 1st operand: Names of cpu functional units.
1032 2nd operand: Name of automaton (see comments for DEFINE_AUTOMATON).
1034 All define_reservations, define_cpu_units, and
1035 define_query_cpu_units should have unique names which may not be
1037 DEF_RTL_EXPR(DEFINE_CPU_UNIT, "define_cpu_unit", "sS", RTX_EXTRA)
1039 /* (define_query_cpu_unit string [string]) describes cpu functional
1040 units analogously to define_cpu_unit. The reservation of such
1041 units can be queried for automaton state. */
1042 DEF_RTL_EXPR(DEFINE_QUERY_CPU_UNIT, "define_query_cpu_unit", "sS", RTX_EXTRA)
1044 /* (exclusion_set string string) means that each CPU functional unit
1045 in the first string can not be reserved simultaneously with any
1046 unit whose name is in the second string and vise versa. CPU units
1047 in the string are separated by commas. For example, it is useful
1048 for description CPU with fully pipelined floating point functional
1049 unit which can execute simultaneously only single floating point
1050 insns or only double floating point insns. All CPU functional
1051 units in a set should belong to the same automaton. */
1052 DEF_RTL_EXPR(EXCLUSION_SET, "exclusion_set", "ss", RTX_EXTRA)
1054 /* (presence_set string string) means that each CPU functional unit in
1055 the first string can not be reserved unless at least one of pattern
1056 of units whose names are in the second string is reserved. This is
1057 an asymmetric relation. CPU units or unit patterns in the strings
1058 are separated by commas. Pattern is one unit name or unit names
1059 separated by white-spaces.
1061 For example, it is useful for description that slot1 is reserved
1062 after slot0 reservation for a VLIW processor. We could describe it
1063 by the following construction
1065 (presence_set "slot1" "slot0")
1067 Or slot1 is reserved only after slot0 and unit b0 reservation. In
1068 this case we could write
1070 (presence_set "slot1" "slot0 b0")
1072 All CPU functional units in a set should belong to the same
1074 DEF_RTL_EXPR(PRESENCE_SET, "presence_set", "ss", RTX_EXTRA)
1076 /* (final_presence_set string string) is analogous to `presence_set'.
1077 The difference between them is when checking is done. When an
1078 instruction is issued in given automaton state reflecting all
1079 current and planned unit reservations, the automaton state is
1080 changed. The first state is a source state, the second one is a
1081 result state. Checking for `presence_set' is done on the source
1082 state reservation, checking for `final_presence_set' is done on the
1083 result reservation. This construction is useful to describe a
1084 reservation which is actually two subsequent reservations. For
1087 (presence_set "slot1" "slot0")
1089 the following insn will be never issued (because slot1 requires
1090 slot0 which is absent in the source state).
1092 (define_reservation "insn_and_nop" "slot0 + slot1")
1094 but it can be issued if we use analogous `final_presence_set'. */
1095 DEF_RTL_EXPR(FINAL_PRESENCE_SET, "final_presence_set", "ss", RTX_EXTRA)
1097 /* (absence_set string string) means that each CPU functional unit in
1098 the first string can be reserved only if each pattern of units
1099 whose names are in the second string is not reserved. This is an
1100 asymmetric relation (actually exclusion set is analogous to this
1101 one but it is symmetric). CPU units or unit patterns in the string
1102 are separated by commas. Pattern is one unit name or unit names
1103 separated by white-spaces.
1105 For example, it is useful for description that slot0 can not be
1106 reserved after slot1 or slot2 reservation for a VLIW processor. We
1107 could describe it by the following construction
1109 (absence_set "slot2" "slot0, slot1")
1111 Or slot2 can not be reserved if slot0 and unit b0 are reserved or
1112 slot1 and unit b1 are reserved . In this case we could write
1114 (absence_set "slot2" "slot0 b0, slot1 b1")
1116 All CPU functional units in a set should to belong the same
1118 DEF_RTL_EXPR(ABSENCE_SET, "absence_set", "ss", RTX_EXTRA)
1120 /* (final_absence_set string string) is analogous to `absence_set' but
1121 checking is done on the result (state) reservation. See comments
1122 for `final_presence_set'. */
1123 DEF_RTL_EXPR(FINAL_ABSENCE_SET, "final_absence_set", "ss", RTX_EXTRA)
1125 /* (define_bypass number out_insn_names in_insn_names) names bypass
1126 with given latency (the first number) from insns given by the first
1127 string (see define_insn_reservation) into insns given by the second
1128 string. Insn names in the strings are separated by commas. The
1129 third operand is optional name of function which is additional
1130 guard for the bypass. The function will get the two insns as
1131 parameters. If the function returns zero the bypass will be
1132 ignored for this case. Additional guard is necessary to recognize
1133 complicated bypasses, e.g. when consumer is load address. If there
1134 are more one bypass with the same output and input insns, the
1135 chosen bypass is the first bypass with a guard in description whose
1136 guard function returns nonzero. If there is no such bypass, then
1137 bypass without the guard function is chosen. */
1138 DEF_RTL_EXPR(DEFINE_BYPASS, "define_bypass", "issS", RTX_EXTRA)
1140 /* (define_automaton string) describes names of automata generated and
1141 used for pipeline hazards recognition. The names are separated by
1142 comma. Actually it is possibly to generate the single automaton
1143 but unfortunately it can be very large. If we use more one
1144 automata, the summary size of the automata usually is less than the
1145 single one. The automaton name is used in define_cpu_unit and
1146 define_query_cpu_unit. All automata should have unique names. */
1147 DEF_RTL_EXPR(DEFINE_AUTOMATON, "define_automaton", "s", RTX_EXTRA)
1149 /* (automata_option string) describes option for generation of
1150 automata. Currently there are the following options:
1152 o "no-minimization" which makes no minimization of automata. This
1153 is only worth to do when we are debugging the description and
1154 need to look more accurately at reservations of states.
1156 o "time" which means printing additional time statistics about
1157 generation of automata.
1159 o "v" which means generation of file describing the result
1160 automata. The file has suffix `.dfa' and can be used for the
1161 description verification and debugging.
1163 o "w" which means generation of warning instead of error for
1164 non-critical errors.
1166 o "ndfa" which makes nondeterministic finite state automata.
1168 o "progress" which means output of a progress bar showing how many
1169 states were generated so far for automaton being processed. */
1170 DEF_RTL_EXPR(AUTOMATA_OPTION, "automata_option", "s", RTX_EXTRA)
1172 /* (define_reservation string string) names reservation (the first
1173 string) of cpu functional units (the 2nd string). Sometimes unit
1174 reservations for different insns contain common parts. In such
1175 case, you can describe common part and use its name (the 1st
1176 parameter) in regular expression in define_insn_reservation. All
1177 define_reservations, define_cpu_units, and define_query_cpu_units
1178 should have unique names which may not be "nothing". */
1179 DEF_RTL_EXPR(DEFINE_RESERVATION, "define_reservation", "ss", RTX_EXTRA)
1181 /* (define_insn_reservation name default_latency condition regexpr)
1182 describes reservation of cpu functional units (the 3nd operand) for
1183 instruction which is selected by the condition (the 2nd parameter).
1184 The first parameter is used for output of debugging information.
1185 The reservations are described by a regular expression according
1186 the following syntax:
1188 regexp = regexp "," oneof
1191 oneof = oneof "|" allof
1194 allof = allof "+" repeat
1197 repeat = element "*" number
1200 element = cpu_function_unit_name
1206 1. "," is used for describing start of the next cycle in
1209 2. "|" is used for describing the reservation described by the
1210 first regular expression *or* the reservation described by the
1211 second regular expression *or* etc.
1213 3. "+" is used for describing the reservation described by the
1214 first regular expression *and* the reservation described by the
1215 second regular expression *and* etc.
1217 4. "*" is used for convenience and simply means sequence in
1218 which the regular expression are repeated NUMBER times with
1219 cycle advancing (see ",").
1221 5. cpu functional unit name which means its reservation.
1223 6. reservation name -- see define_reservation.
1225 7. string "nothing" means no units reservation. */
1227 DEF_RTL_EXPR(DEFINE_INSN_RESERVATION, "define_insn_reservation", "sies", RTX_EXTRA)
1229 /* Expressions used for insn attributes. */
1231 /* Definition of an insn attribute.
1232 1st operand: name of the attribute
1233 2nd operand: comma-separated list of possible attribute values
1234 3rd operand: expression for the default value of the attribute. */
1235 DEF_RTL_EXPR(DEFINE_ATTR, "define_attr", "sse", RTX_EXTRA)
1237 /* Definition of an insn attribute that uses an existing enumerated type.
1238 1st operand: name of the attribute
1239 2nd operand: the name of the enumerated type
1240 3rd operand: expression for the default value of the attribute. */
1241 DEF_RTL_EXPR(DEFINE_ENUM_ATTR, "define_enum_attr", "sse", RTX_EXTRA)
1243 /* Marker for the name of an attribute. */
1244 DEF_RTL_EXPR(ATTR, "attr", "s", RTX_EXTRA)
1246 /* For use in the last (optional) operand of DEFINE_INSN or DEFINE_PEEPHOLE and
1247 in DEFINE_ASM_INSN to specify an attribute to assign to insns matching that
1250 (set_attr "name" "value") is equivalent to
1251 (set (attr "name") (const_string "value")) */
1252 DEF_RTL_EXPR(SET_ATTR, "set_attr", "ss", RTX_EXTRA)
1254 /* In the last operand of DEFINE_INSN and DEFINE_PEEPHOLE, this can be used to
1255 specify that attribute values are to be assigned according to the
1256 alternative matched.
1258 The following three expressions are equivalent:
1260 (set (attr "att") (cond [(eq_attrq "alternative" "1") (const_string "a1")
1261 (eq_attrq "alternative" "2") (const_string "a2")]
1262 (const_string "a3")))
1263 (set_attr_alternative "att" [(const_string "a1") (const_string "a2")
1264 (const_string "a3")])
1265 (set_attr "att" "a1,a2,a3")
1267 DEF_RTL_EXPR(SET_ATTR_ALTERNATIVE, "set_attr_alternative", "sE", RTX_EXTRA)
1269 /* A conditional expression true if the value of the specified attribute of
1270 the current insn equals the specified value. The first operand is the
1271 attribute name and the second is the comparison value. */
1272 DEF_RTL_EXPR(EQ_ATTR, "eq_attr", "ss", RTX_EXTRA)
1274 /* A special case of the above representing a set of alternatives. The first
1275 operand is bitmap of the set, the second one is the default value. */
1276 DEF_RTL_EXPR(EQ_ATTR_ALT, "eq_attr_alt", "ii", RTX_EXTRA)
1278 /* A conditional expression which is true if the specified flag is
1279 true for the insn being scheduled in reorg.
1281 genattr.c defines the following flags which can be tested by
1282 (attr_flag "foo") expressions in eligible_for_delay: forward, backward. */
1284 DEF_RTL_EXPR (ATTR_FLAG, "attr_flag", "s", RTX_EXTRA)
1286 /* General conditional. The first operand is a vector composed of pairs of
1287 expressions. The first element of each pair is evaluated, in turn.
1288 The value of the conditional is the second expression of the first pair
1289 whose first expression evaluates nonzero. If none of the expressions is
1290 true, the second operand will be used as the value of the conditional. */
1291 DEF_RTL_EXPR(COND, "cond", "Ee", RTX_EXTRA)
1293 /* Definition of a pattern substitution meta operation on a DEFINE_EXPAND
1294 or a DEFINE_INSN. Automatically generates new instances of DEFINE_INSNs
1295 that match the substitution pattern.
1298 0: The name of the substitition template.
1299 1: Input template to match to see if a substitution is applicable.
1300 2: A C expression giving an additional condition for the generated
1301 new define_expand or define_insn.
1302 3: Output tempalate to generate via substitution.
1304 Within a DEFINE_SUBST template, the meaning of some RTL expressions is
1305 different from their usual interpretation: a MATCH_OPERAND matches any
1306 expression tree with matching machine mode or with VOIDmode. Likewise,
1307 MATCH_OP_DUP and MATCH_DUP match more liberally in a DEFINE_SUBST than
1308 in other RTL expressions. MATCH_OPERATOR matches all common operators
1309 but also UNSPEC, UNSPEC_VOLATILE, and MATCH_OPERATORS from the input
1310 DEFINE_EXPAND or DEFINE_INSN. */
1311 DEF_RTL_EXPR(DEFINE_SUBST, "define_subst", "sEsE", RTX_EXTRA)
1313 /* Substitution attribute to apply a DEFINE_SUBST to a pattern.
1316 0: The name of the subst-attribute.
1317 1: The name of the DEFINE_SUBST to be applied for this attribute.
1318 2: String to substitute for the subst-attribute name in the pattern
1319 name, for the case that the DEFINE_SUBST is not applied (i.e. the
1320 unmodified version of the pattern).
1321 3: String to substitute for the subst-attribute name in the pattern
1322 name, for the case that the DEFINE_SUBST is applied to the patten.
1324 The use of DEFINE_SUBST and DEFINE_SUBST_ATTR is explained in the
1325 GCC internals manual, under "RTL Templates Transformations". */
1326 DEF_RTL_EXPR(DEFINE_SUBST_ATTR, "define_subst_attr", "ssss", RTX_EXTRA)
1328 #endif /* GENERATOR_FILE */
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