1 /* This file contains the definitions and documentation for the
2 Register Transfer Expressions (rtx's) that make up the
3 Register Transfer Language (rtl) used in the Back End of the GNU compiler.
4 Copyright (C) 1987-2013 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 3, or (at your option) any later
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
23 /* Expression definitions and descriptions for all targets are in this file.
24 Some will not be used for some targets.
26 The fields in the cpp macro call "DEF_RTL_EXPR()"
27 are used to create declarations in the C source of the compiler.
31 1. The internal name of the rtx used in the C source.
32 It is a tag in the enumeration "enum rtx_code" defined in "rtl.h".
33 By convention these are in UPPER_CASE.
35 2. The name of the rtx in the external ASCII format read by
36 read_rtx(), and printed by print_rtx().
37 These names are stored in rtx_name[].
38 By convention these are the internal (field 1) names in lower_case.
40 3. The print format, and type of each rtx->u.fld[] (field) in this rtx.
41 These formats are stored in rtx_format[].
42 The meaning of the formats is documented in front of this array in rtl.c
44 4. The class of the rtx. These are stored in rtx_class and are accessed
45 via the GET_RTX_CLASS macro. They are defined as follows:
48 an rtx code that can be used to represent a constant object
51 an rtx code that can be used to represent an object (e.g, REG, MEM)
53 an rtx code for a comparison (e.g, LT, GT)
55 an rtx code for a commutative comparison (e.g, EQ, NE, ORDERED)
57 an rtx code for a unary arithmetic expression (e.g, NEG, NOT)
59 an rtx code for a commutative binary operation (e.g,, PLUS, MULT)
61 an rtx code for a non-bitfield three input operation (IF_THEN_ELSE)
63 an rtx code for a non-commutative binary operation (e.g., MINUS, DIV)
65 an rtx code for a bit-field operation (ZERO_EXTRACT, SIGN_EXTRACT)
67 an rtx code for a machine insn (INSN, JUMP_INSN, CALL_INSN) or
68 data that will be output as assembly pseudo-ops (DEBUG_INSN)
70 an rtx code for something that matches in insns (e.g, MATCH_DUP)
72 an rtx code for autoincrement addressing modes (e.g. POST_DEC)
76 All of the expressions that appear only in machine descriptions,
77 not in RTL used by the compiler itself, are at the end of the file. */
79 /* Unknown, or no such operation; the enumeration constant should have
81 DEF_RTL_EXPR(UNKNOWN, "UnKnown", "*", RTX_EXTRA)
83 /* Used in the cselib routines to describe a value. Objects of this
84 kind are only allocated in cselib.c, in an alloc pool instead of in
85 GC memory. The only operand of a VALUE is a cselib_val_struct.
86 var-tracking requires this to have a distinct integral value from
87 DECL codes in trees. */
88 DEF_RTL_EXPR(VALUE, "value", "0", RTX_OBJ)
90 /* The RTL generated for a DEBUG_EXPR_DECL. It links back to the
91 DEBUG_EXPR_DECL in the first operand. */
92 DEF_RTL_EXPR(DEBUG_EXPR, "debug_expr", "0", RTX_OBJ)
94 /* ---------------------------------------------------------------------
95 Expressions used in constructing lists.
96 --------------------------------------------------------------------- */
98 /* a linked list of expressions */
99 DEF_RTL_EXPR(EXPR_LIST, "expr_list", "ee", RTX_EXTRA)
101 /* a linked list of instructions.
102 The insns are represented in print by their uids. */
103 DEF_RTL_EXPR(INSN_LIST, "insn_list", "ue", RTX_EXTRA)
105 /* SEQUENCE is used in late passes of the compiler to group insns for
106 one reason or another.
108 For example, after delay slot filling, branch instructions with filled
109 delay slots are represented as a SEQUENCE of length 1 + n_delay_slots,
110 with the branch instruction in XEXPVEC(seq, 0, 0) and the instructions
111 occupying the delay slots in the remaining XEXPVEC slots.
113 Another place where a SEQUENCE may appear, is in REG_FRAME_RELATED_EXPR
114 notes, to express complex operations that are not obvious from the insn
115 to which the REG_FRAME_RELATED_EXPR note is attached. In this usage of
116 SEQUENCE, the sequence vector slots do not hold real instructions but
117 only pseudo-instructions that can be translated to DWARF CFA expressions.
119 Some back ends also use SEQUENCE to group insns in bundles.
121 Much of the compiler infrastructure is not prepared to handle SEQUENCE
122 objects. Only passes after pass_free_cfg are expected to handle them. */
123 DEF_RTL_EXPR(SEQUENCE, "sequence", "E", RTX_EXTRA)
125 /* Represents a non-global base address. This is only used in alias.c. */
126 DEF_RTL_EXPR(ADDRESS, "address", "i", RTX_EXTRA)
128 /* ----------------------------------------------------------------------
129 Expression types used for things in the instruction chain.
131 All formats must start with "iuu" to handle the chain.
132 Each insn expression holds an rtl instruction and its semantics
133 during back-end processing.
134 See macros's in "rtl.h" for the meaning of each rtx->u.fld[].
136 ---------------------------------------------------------------------- */
138 /* An annotation for variable assignment tracking. */
139 DEF_RTL_EXPR(DEBUG_INSN, "debug_insn", "iuuBeiie", RTX_INSN)
141 /* An instruction that cannot jump. */
142 DEF_RTL_EXPR(INSN, "insn", "iuuBeiie", RTX_INSN)
144 /* An instruction that can possibly jump.
145 Fields ( rtx->u.fld[] ) have exact same meaning as INSN's. */
146 DEF_RTL_EXPR(JUMP_INSN, "jump_insn", "iuuBeiie0", RTX_INSN)
148 /* An instruction that can possibly call a subroutine
149 but which will not change which instruction comes next
150 in the current function.
151 Field ( rtx->u.fld[8] ) is CALL_INSN_FUNCTION_USAGE.
152 All other fields ( rtx->u.fld[] ) have exact same meaning as INSN's. */
153 DEF_RTL_EXPR(CALL_INSN, "call_insn", "iuuBeiiee", RTX_INSN)
155 /* Placeholder for tablejump JUMP_INSNs. The pattern of this kind
156 of rtx is always either an ADDR_VEC or an ADDR_DIFF_VEC. These
157 placeholders do not appear as real instructions inside a basic
158 block, but are considered active_insn_p instructions for historical
159 reasons, when jump table data was represented with JUMP_INSNs. */
160 DEF_RTL_EXPR(JUMP_TABLE_DATA, "jump_table_data", "iuuBe0000", RTX_INSN)
162 /* A marker that indicates that control will not flow through. */
163 DEF_RTL_EXPR(BARRIER, "barrier", "iuu00000", RTX_EXTRA)
165 /* Holds a label that is followed by instructions.
167 4: is used in jump.c for the use-count of the label.
168 5: is used in the sh backend.
169 6: is a number that is unique in the entire compilation.
170 7: is the user-given name of the label, if any. */
171 DEF_RTL_EXPR(CODE_LABEL, "code_label", "iuuB00is", RTX_EXTRA)
173 /* Say where in the code a source line starts, for symbol table's sake.
175 4: note-specific data
177 6: unique number if insn_note == note_insn_deleted_label. */
178 DEF_RTL_EXPR(NOTE, "note", "iuuB0ni", RTX_EXTRA)
180 /* ----------------------------------------------------------------------
181 Top level constituents of INSN, JUMP_INSN and CALL_INSN.
182 ---------------------------------------------------------------------- */
184 /* Conditionally execute code.
185 Operand 0 is the condition that if true, the code is executed.
186 Operand 1 is the code to be executed (typically a SET).
188 Semantics are that there are no side effects if the condition
189 is false. This pattern is created automatically by the if_convert
190 pass run after reload or by target-specific splitters. */
191 DEF_RTL_EXPR(COND_EXEC, "cond_exec", "ee", RTX_EXTRA)
193 /* Several operations to be done in parallel (perhaps under COND_EXEC). */
194 DEF_RTL_EXPR(PARALLEL, "parallel", "E", RTX_EXTRA)
196 /* A string that is passed through to the assembler as input.
197 One can obviously pass comments through by using the
198 assembler comment syntax.
199 These occur in an insn all by themselves as the PATTERN.
200 They also appear inside an ASM_OPERANDS
201 as a convenient way to hold a string. */
202 DEF_RTL_EXPR(ASM_INPUT, "asm_input", "si", RTX_EXTRA)
204 /* An assembler instruction with operands.
205 1st operand is the instruction template.
206 2nd operand is the constraint for the output.
207 3rd operand is the number of the output this expression refers to.
208 When an insn stores more than one value, a separate ASM_OPERANDS
209 is made for each output; this integer distinguishes them.
210 4th is a vector of values of input operands.
211 5th is a vector of modes and constraints for the input operands.
212 Each element is an ASM_INPUT containing a constraint string
213 and whose mode indicates the mode of the input operand.
214 6th is a vector of labels that may be branched to by the asm.
215 7th is the source line number. */
216 DEF_RTL_EXPR(ASM_OPERANDS, "asm_operands", "ssiEEEi", RTX_EXTRA)
218 /* A machine-specific operation.
219 1st operand is a vector of operands being used by the operation so that
220 any needed reloads can be done.
221 2nd operand is a unique value saying which of a number of machine-specific
222 operations is to be performed.
223 (Note that the vector must be the first operand because of the way that
224 genrecog.c record positions within an insn.)
226 UNSPEC can occur all by itself in a PATTERN, as a component of a PARALLEL,
227 or inside an expression.
228 UNSPEC by itself or as a component of a PARALLEL
229 is currently considered not deletable.
231 FIXME: Replace all uses of UNSPEC that appears by itself or as a component
232 of a PARALLEL with USE.
234 DEF_RTL_EXPR(UNSPEC, "unspec", "Ei", RTX_EXTRA)
236 /* Similar, but a volatile operation and one which may trap. */
237 DEF_RTL_EXPR(UNSPEC_VOLATILE, "unspec_volatile", "Ei", RTX_EXTRA)
239 /* ----------------------------------------------------------------------
240 Table jump addresses.
241 ---------------------------------------------------------------------- */
243 /* Vector of addresses, stored as full words.
244 Each element is a LABEL_REF to a CODE_LABEL whose address we want. */
245 DEF_RTL_EXPR(ADDR_VEC, "addr_vec", "E", RTX_EXTRA)
247 /* Vector of address differences X0 - BASE, X1 - BASE, ...
248 First operand is BASE; the vector contains the X's.
249 The machine mode of this rtx says how much space to leave
250 for each difference and is adjusted by branch shortening if
251 CASE_VECTOR_SHORTEN_MODE is defined.
252 The third and fourth operands store the target labels with the
253 minimum and maximum addresses respectively.
254 The fifth operand stores flags for use by branch shortening.
255 Set at the start of shorten_branches:
256 min_align: the minimum alignment for any of the target labels.
257 base_after_vec: true iff BASE is after the ADDR_DIFF_VEC.
258 min_after_vec: true iff minimum addr target label is after the ADDR_DIFF_VEC.
259 max_after_vec: true iff maximum addr target label is after the ADDR_DIFF_VEC.
260 min_after_base: true iff minimum address target label is after BASE.
261 max_after_base: true iff maximum address target label is after BASE.
262 Set by the actual branch shortening process:
263 offset_unsigned: true iff offsets have to be treated as unsigned.
264 scale: scaling that is necessary to make offsets fit into the mode.
266 The third, fourth and fifth operands are only valid when
267 CASE_VECTOR_SHORTEN_MODE is defined, and only in an optimizing
269 DEF_RTL_EXPR(ADDR_DIFF_VEC, "addr_diff_vec", "eEee0", RTX_EXTRA)
271 /* Memory prefetch, with attributes supported on some targets.
272 Operand 1 is the address of the memory to fetch.
273 Operand 2 is 1 for a write access, 0 otherwise.
274 Operand 3 is the level of temporal locality; 0 means there is no
275 temporal locality and 1, 2, and 3 are for increasing levels of temporal
278 The attributes specified by operands 2 and 3 are ignored for targets
279 whose prefetch instructions do not support them. */
280 DEF_RTL_EXPR(PREFETCH, "prefetch", "eee", RTX_EXTRA)
282 /* ----------------------------------------------------------------------
283 At the top level of an instruction (perhaps under PARALLEL).
284 ---------------------------------------------------------------------- */
287 Operand 1 is the location (REG, MEM, PC, CC0 or whatever) assigned to.
288 Operand 2 is the value stored there.
289 ALL assignment must use SET.
290 Instructions that do multiple assignments must use multiple SET,
292 DEF_RTL_EXPR(SET, "set", "ee", RTX_EXTRA)
294 /* Indicate something is used in a way that we don't want to explain.
295 For example, subroutine calls will use the register
296 in which the static chain is passed.
298 USE can not appear as an operand of other rtx except for PARALLEL.
299 USE is not deletable, as it indicates that the operand
300 is used in some unknown way. */
301 DEF_RTL_EXPR(USE, "use", "e", RTX_EXTRA)
303 /* Indicate something is clobbered in a way that we don't want to explain.
304 For example, subroutine calls will clobber some physical registers
305 (the ones that are by convention not saved).
307 CLOBBER can not appear as an operand of other rtx except for PARALLEL.
308 CLOBBER of a hard register appearing by itself (not within PARALLEL)
309 is considered undeletable before reload. */
310 DEF_RTL_EXPR(CLOBBER, "clobber", "e", RTX_EXTRA)
312 /* Call a subroutine.
313 Operand 1 is the address to call.
314 Operand 2 is the number of arguments. */
316 DEF_RTL_EXPR(CALL, "call", "ee", RTX_EXTRA)
318 /* Return from a subroutine. */
320 DEF_RTL_EXPR(RETURN, "return", "", RTX_EXTRA)
322 /* Like RETURN, but truly represents only a function return, while
323 RETURN may represent an insn that also performs other functions
324 of the function epilogue. Like RETURN, this may also occur in
325 conditional jumps. */
326 DEF_RTL_EXPR(SIMPLE_RETURN, "simple_return", "", RTX_EXTRA)
328 /* Special for EH return from subroutine. */
330 DEF_RTL_EXPR(EH_RETURN, "eh_return", "", RTX_EXTRA)
333 Operand 1 is the condition.
334 Operand 2 is the trap code.
335 For an unconditional trap, make the condition (const_int 1). */
336 DEF_RTL_EXPR(TRAP_IF, "trap_if", "ee", RTX_EXTRA)
338 /* ----------------------------------------------------------------------
339 Primitive values for use in expressions.
340 ---------------------------------------------------------------------- */
342 /* numeric integer constant */
343 DEF_RTL_EXPR(CONST_INT, "const_int", "w", RTX_CONST_OBJ)
345 /* fixed-point constant */
346 DEF_RTL_EXPR(CONST_FIXED, "const_fixed", "www", RTX_CONST_OBJ)
348 /* numeric floating point or integer constant. If the mode is
349 VOIDmode it is an int otherwise it has a floating point mode and a
350 floating point value. Operands hold the value. They are all 'w'
351 and there may be from 2 to 6; see real.h. */
352 DEF_RTL_EXPR(CONST_DOUBLE, "const_double", CONST_DOUBLE_FORMAT, RTX_CONST_OBJ)
354 /* Describes a vector constant. */
355 DEF_RTL_EXPR(CONST_VECTOR, "const_vector", "E", RTX_CONST_OBJ)
357 /* String constant. Used for attributes in machine descriptions and
358 for special cases in DWARF2 debug output. NOT used for source-
359 language string constants. */
360 DEF_RTL_EXPR(CONST_STRING, "const_string", "s", RTX_OBJ)
362 /* This is used to encapsulate an expression whose value is constant
363 (such as the sum of a SYMBOL_REF and a CONST_INT) so that it will be
364 recognized as a constant operand rather than by arithmetic instructions. */
366 DEF_RTL_EXPR(CONST, "const", "e", RTX_CONST_OBJ)
368 /* program counter. Ordinary jumps are represented
369 by a SET whose first operand is (PC). */
370 DEF_RTL_EXPR(PC, "pc", "", RTX_OBJ)
372 /* A register. The "operand" is the register number, accessed with
373 the REGNO macro. If this number is less than FIRST_PSEUDO_REGISTER
374 than a hardware register is being referred to. The second operand
375 holds the original register number - this will be different for a
376 pseudo register that got turned into a hard register. The third
377 operand points to a reg_attrs structure.
378 This rtx needs to have as many (or more) fields as a MEM, since we
379 can change REG rtx's into MEMs during reload. */
380 DEF_RTL_EXPR(REG, "reg", "i00", RTX_OBJ)
382 /* A scratch register. This represents a register used only within a
383 single insn. It will be turned into a REG during register allocation
384 or reload unless the constraint indicates that the register won't be
385 needed, in which case it can remain a SCRATCH. This code is
386 marked as having one operand so it can be turned into a REG. */
387 DEF_RTL_EXPR(SCRATCH, "scratch", "0", RTX_OBJ)
389 /* A reference to a part of another value. The first operand is the
390 complete value and the second is the byte offset of the selected part. */
391 DEF_RTL_EXPR(SUBREG, "subreg", "ei", RTX_EXTRA)
393 /* This one-argument rtx is used for move instructions
394 that are guaranteed to alter only the low part of a destination.
395 Thus, (SET (SUBREG:HI (REG...)) (MEM:HI ...))
396 has an unspecified effect on the high part of REG,
397 but (SET (STRICT_LOW_PART (SUBREG:HI (REG...))) (MEM:HI ...))
398 is guaranteed to alter only the bits of REG that are in HImode.
400 The actual instruction used is probably the same in both cases,
401 but the register constraints may be tighter when STRICT_LOW_PART
404 DEF_RTL_EXPR(STRICT_LOW_PART, "strict_low_part", "e", RTX_EXTRA)
406 /* (CONCAT a b) represents the virtual concatenation of a and b
407 to make a value that has as many bits as a and b put together.
408 This is used for complex values. Normally it appears only
409 in DECL_RTLs and during RTL generation, but not in the insn chain. */
410 DEF_RTL_EXPR(CONCAT, "concat", "ee", RTX_OBJ)
412 /* (CONCATN [a1 a2 ... an]) represents the virtual concatenation of
413 all An to make a value. This is an extension of CONCAT to larger
414 number of components. Like CONCAT, it should not appear in the
415 insn chain. Every element of the CONCATN is the same size. */
416 DEF_RTL_EXPR(CONCATN, "concatn", "E", RTX_OBJ)
418 /* A memory location; operand is the address. The second operand is the
419 alias set to which this MEM belongs. We use `0' instead of `w' for this
420 field so that the field need not be specified in machine descriptions. */
421 DEF_RTL_EXPR(MEM, "mem", "e0", RTX_OBJ)
423 /* Reference to an assembler label in the code for this function.
424 The operand is a CODE_LABEL found in the insn chain. */
425 DEF_RTL_EXPR(LABEL_REF, "label_ref", "u", RTX_CONST_OBJ)
427 /* Reference to a named label:
428 Operand 0: label name
429 Operand 1: flags (see SYMBOL_FLAG_* in rtl.h)
430 Operand 2: tree from which this symbol is derived, or null.
431 This is either a DECL node, or some kind of constant. */
432 DEF_RTL_EXPR(SYMBOL_REF, "symbol_ref", "s00", RTX_CONST_OBJ)
434 /* The condition code register is represented, in our imagination,
435 as a register holding a value that can be compared to zero.
436 In fact, the machine has already compared them and recorded the
437 results; but instructions that look at the condition code
438 pretend to be looking at the entire value and comparing it. */
439 DEF_RTL_EXPR(CC0, "cc0", "", RTX_OBJ)
441 /* ----------------------------------------------------------------------
442 Expressions for operators in an rtl pattern
443 ---------------------------------------------------------------------- */
445 /* if_then_else. This is used in representing ordinary
446 conditional jump instructions.
451 DEF_RTL_EXPR(IF_THEN_ELSE, "if_then_else", "eee", RTX_TERNARY)
453 /* Comparison, produces a condition code result. */
454 DEF_RTL_EXPR(COMPARE, "compare", "ee", RTX_BIN_ARITH)
457 DEF_RTL_EXPR(PLUS, "plus", "ee", RTX_COMM_ARITH)
459 /* Operand 0 minus operand 1. */
460 DEF_RTL_EXPR(MINUS, "minus", "ee", RTX_BIN_ARITH)
462 /* Minus operand 0. */
463 DEF_RTL_EXPR(NEG, "neg", "e", RTX_UNARY)
465 DEF_RTL_EXPR(MULT, "mult", "ee", RTX_COMM_ARITH)
467 /* Multiplication with signed saturation */
468 DEF_RTL_EXPR(SS_MULT, "ss_mult", "ee", RTX_COMM_ARITH)
469 /* Multiplication with unsigned saturation */
470 DEF_RTL_EXPR(US_MULT, "us_mult", "ee", RTX_COMM_ARITH)
472 /* Operand 0 divided by operand 1. */
473 DEF_RTL_EXPR(DIV, "div", "ee", RTX_BIN_ARITH)
474 /* Division with signed saturation */
475 DEF_RTL_EXPR(SS_DIV, "ss_div", "ee", RTX_BIN_ARITH)
476 /* Division with unsigned saturation */
477 DEF_RTL_EXPR(US_DIV, "us_div", "ee", RTX_BIN_ARITH)
479 /* Remainder of operand 0 divided by operand 1. */
480 DEF_RTL_EXPR(MOD, "mod", "ee", RTX_BIN_ARITH)
482 /* Unsigned divide and remainder. */
483 DEF_RTL_EXPR(UDIV, "udiv", "ee", RTX_BIN_ARITH)
484 DEF_RTL_EXPR(UMOD, "umod", "ee", RTX_BIN_ARITH)
486 /* Bitwise operations. */
487 DEF_RTL_EXPR(AND, "and", "ee", RTX_COMM_ARITH)
488 DEF_RTL_EXPR(IOR, "ior", "ee", RTX_COMM_ARITH)
489 DEF_RTL_EXPR(XOR, "xor", "ee", RTX_COMM_ARITH)
490 DEF_RTL_EXPR(NOT, "not", "e", RTX_UNARY)
493 0: value to be shifted.
494 1: number of bits. */
495 DEF_RTL_EXPR(ASHIFT, "ashift", "ee", RTX_BIN_ARITH) /* shift left */
496 DEF_RTL_EXPR(ROTATE, "rotate", "ee", RTX_BIN_ARITH) /* rotate left */
497 DEF_RTL_EXPR(ASHIFTRT, "ashiftrt", "ee", RTX_BIN_ARITH) /* arithmetic shift right */
498 DEF_RTL_EXPR(LSHIFTRT, "lshiftrt", "ee", RTX_BIN_ARITH) /* logical shift right */
499 DEF_RTL_EXPR(ROTATERT, "rotatert", "ee", RTX_BIN_ARITH) /* rotate right */
501 /* Minimum and maximum values of two operands. We need both signed and
502 unsigned forms. (We cannot use MIN for SMIN because it conflicts
503 with a macro of the same name.) The signed variants should be used
504 with floating point. Further, if both operands are zeros, or if either
505 operand is NaN, then it is unspecified which of the two operands is
506 returned as the result. */
508 DEF_RTL_EXPR(SMIN, "smin", "ee", RTX_COMM_ARITH)
509 DEF_RTL_EXPR(SMAX, "smax", "ee", RTX_COMM_ARITH)
510 DEF_RTL_EXPR(UMIN, "umin", "ee", RTX_COMM_ARITH)
511 DEF_RTL_EXPR(UMAX, "umax", "ee", RTX_COMM_ARITH)
513 /* These unary operations are used to represent incrementation
514 and decrementation as they occur in memory addresses.
515 The amount of increment or decrement are not represented
516 because they can be understood from the machine-mode of the
517 containing MEM. These operations exist in only two cases:
518 1. pushes onto the stack.
519 2. created automatically by the auto-inc-dec pass. */
520 DEF_RTL_EXPR(PRE_DEC, "pre_dec", "e", RTX_AUTOINC)
521 DEF_RTL_EXPR(PRE_INC, "pre_inc", "e", RTX_AUTOINC)
522 DEF_RTL_EXPR(POST_DEC, "post_dec", "e", RTX_AUTOINC)
523 DEF_RTL_EXPR(POST_INC, "post_inc", "e", RTX_AUTOINC)
525 /* These binary operations are used to represent generic address
526 side-effects in memory addresses, except for simple incrementation
527 or decrementation which use the above operations. They are
528 created automatically by the life_analysis pass in flow.c.
529 The first operand is a REG which is used as the address.
530 The second operand is an expression that is assigned to the
531 register, either before (PRE_MODIFY) or after (POST_MODIFY)
532 evaluating the address.
533 Currently, the compiler can only handle second operands of the
534 form (plus (reg) (reg)) and (plus (reg) (const_int)), where
535 the first operand of the PLUS has to be the same register as
536 the first operand of the *_MODIFY. */
537 DEF_RTL_EXPR(PRE_MODIFY, "pre_modify", "ee", RTX_AUTOINC)
538 DEF_RTL_EXPR(POST_MODIFY, "post_modify", "ee", RTX_AUTOINC)
540 /* Comparison operations. The ordered comparisons exist in two
541 flavors, signed and unsigned. */
542 DEF_RTL_EXPR(NE, "ne", "ee", RTX_COMM_COMPARE)
543 DEF_RTL_EXPR(EQ, "eq", "ee", RTX_COMM_COMPARE)
544 DEF_RTL_EXPR(GE, "ge", "ee", RTX_COMPARE)
545 DEF_RTL_EXPR(GT, "gt", "ee", RTX_COMPARE)
546 DEF_RTL_EXPR(LE, "le", "ee", RTX_COMPARE)
547 DEF_RTL_EXPR(LT, "lt", "ee", RTX_COMPARE)
548 DEF_RTL_EXPR(GEU, "geu", "ee", RTX_COMPARE)
549 DEF_RTL_EXPR(GTU, "gtu", "ee", RTX_COMPARE)
550 DEF_RTL_EXPR(LEU, "leu", "ee", RTX_COMPARE)
551 DEF_RTL_EXPR(LTU, "ltu", "ee", RTX_COMPARE)
553 /* Additional floating point unordered comparison flavors. */
554 DEF_RTL_EXPR(UNORDERED, "unordered", "ee", RTX_COMM_COMPARE)
555 DEF_RTL_EXPR(ORDERED, "ordered", "ee", RTX_COMM_COMPARE)
557 /* These are equivalent to unordered or ... */
558 DEF_RTL_EXPR(UNEQ, "uneq", "ee", RTX_COMM_COMPARE)
559 DEF_RTL_EXPR(UNGE, "unge", "ee", RTX_COMPARE)
560 DEF_RTL_EXPR(UNGT, "ungt", "ee", RTX_COMPARE)
561 DEF_RTL_EXPR(UNLE, "unle", "ee", RTX_COMPARE)
562 DEF_RTL_EXPR(UNLT, "unlt", "ee", RTX_COMPARE)
564 /* This is an ordered NE, ie !UNEQ, ie false for NaN. */
565 DEF_RTL_EXPR(LTGT, "ltgt", "ee", RTX_COMM_COMPARE)
567 /* Represents the result of sign-extending the sole operand.
568 The machine modes of the operand and of the SIGN_EXTEND expression
569 determine how much sign-extension is going on. */
570 DEF_RTL_EXPR(SIGN_EXTEND, "sign_extend", "e", RTX_UNARY)
572 /* Similar for zero-extension (such as unsigned short to int). */
573 DEF_RTL_EXPR(ZERO_EXTEND, "zero_extend", "e", RTX_UNARY)
575 /* Similar but here the operand has a wider mode. */
576 DEF_RTL_EXPR(TRUNCATE, "truncate", "e", RTX_UNARY)
578 /* Similar for extending floating-point values (such as SFmode to DFmode). */
579 DEF_RTL_EXPR(FLOAT_EXTEND, "float_extend", "e", RTX_UNARY)
580 DEF_RTL_EXPR(FLOAT_TRUNCATE, "float_truncate", "e", RTX_UNARY)
582 /* Conversion of fixed point operand to floating point value. */
583 DEF_RTL_EXPR(FLOAT, "float", "e", RTX_UNARY)
585 /* With fixed-point machine mode:
586 Conversion of floating point operand to fixed point value.
587 Value is defined only when the operand's value is an integer.
588 With floating-point machine mode (and operand with same mode):
589 Operand is rounded toward zero to produce an integer value
590 represented in floating point. */
591 DEF_RTL_EXPR(FIX, "fix", "e", RTX_UNARY)
593 /* Conversion of unsigned fixed point operand to floating point value. */
594 DEF_RTL_EXPR(UNSIGNED_FLOAT, "unsigned_float", "e", RTX_UNARY)
596 /* With fixed-point machine mode:
597 Conversion of floating point operand to *unsigned* fixed point value.
598 Value is defined only when the operand's value is an integer. */
599 DEF_RTL_EXPR(UNSIGNED_FIX, "unsigned_fix", "e", RTX_UNARY)
601 /* Conversions involving fractional fixed-point types without saturation,
603 fractional to fractional (of different precision),
604 signed integer to fractional,
605 fractional to signed integer,
606 floating point to fractional,
607 fractional to floating point.
608 NOTE: fractional can be either signed or unsigned for conversions. */
609 DEF_RTL_EXPR(FRACT_CONVERT, "fract_convert", "e", RTX_UNARY)
611 /* Conversions involving fractional fixed-point types and unsigned integer
612 without saturation, including:
613 unsigned integer to fractional,
614 fractional to unsigned integer.
615 NOTE: fractional can be either signed or unsigned for conversions. */
616 DEF_RTL_EXPR(UNSIGNED_FRACT_CONVERT, "unsigned_fract_convert", "e", RTX_UNARY)
618 /* Conversions involving fractional fixed-point types with saturation,
620 fractional to fractional (of different precision),
621 signed integer to fractional,
622 floating point to fractional.
623 NOTE: fractional can be either signed or unsigned for conversions. */
624 DEF_RTL_EXPR(SAT_FRACT, "sat_fract", "e", RTX_UNARY)
626 /* Conversions involving fractional fixed-point types and unsigned integer
627 with saturation, including:
628 unsigned integer to fractional.
629 NOTE: fractional can be either signed or unsigned for conversions. */
630 DEF_RTL_EXPR(UNSIGNED_SAT_FRACT, "unsigned_sat_fract", "e", RTX_UNARY)
633 DEF_RTL_EXPR(ABS, "abs", "e", RTX_UNARY)
636 DEF_RTL_EXPR(SQRT, "sqrt", "e", RTX_UNARY)
639 DEF_RTL_EXPR(BSWAP, "bswap", "e", RTX_UNARY)
641 /* Find first bit that is set.
642 Value is 1 + number of trailing zeros in the arg.,
644 DEF_RTL_EXPR(FFS, "ffs", "e", RTX_UNARY)
646 /* Count number of leading redundant sign bits (number of leading
647 sign bits minus one). */
648 DEF_RTL_EXPR(CLRSB, "clrsb", "e", RTX_UNARY)
650 /* Count leading zeros. */
651 DEF_RTL_EXPR(CLZ, "clz", "e", RTX_UNARY)
653 /* Count trailing zeros. */
654 DEF_RTL_EXPR(CTZ, "ctz", "e", RTX_UNARY)
656 /* Population count (number of 1 bits). */
657 DEF_RTL_EXPR(POPCOUNT, "popcount", "e", RTX_UNARY)
659 /* Population parity (number of 1 bits modulo 2). */
660 DEF_RTL_EXPR(PARITY, "parity", "e", RTX_UNARY)
662 /* Reference to a signed bit-field of specified size and position.
663 Operand 0 is the memory unit (usually SImode or QImode) which
664 contains the field's first bit. Operand 1 is the width, in bits.
665 Operand 2 is the number of bits in the memory unit before the
666 first bit of this field.
667 If BITS_BIG_ENDIAN is defined, the first bit is the msb and
668 operand 2 counts from the msb of the memory unit.
669 Otherwise, the first bit is the lsb and operand 2 counts from
670 the lsb of the memory unit.
671 This kind of expression can not appear as an lvalue in RTL. */
672 DEF_RTL_EXPR(SIGN_EXTRACT, "sign_extract", "eee", RTX_BITFIELD_OPS)
674 /* Similar for unsigned bit-field.
675 But note! This kind of expression _can_ appear as an lvalue. */
676 DEF_RTL_EXPR(ZERO_EXTRACT, "zero_extract", "eee", RTX_BITFIELD_OPS)
678 /* For RISC machines. These save memory when splitting insns. */
680 /* HIGH are the high-order bits of a constant expression. */
681 DEF_RTL_EXPR(HIGH, "high", "e", RTX_CONST_OBJ)
683 /* LO_SUM is the sum of a register and the low-order bits
684 of a constant expression. */
685 DEF_RTL_EXPR(LO_SUM, "lo_sum", "ee", RTX_OBJ)
687 /* Describes a merge operation between two vector values.
688 Operands 0 and 1 are the vectors to be merged, operand 2 is a bitmask
689 that specifies where the parts of the result are taken from. Set bits
690 indicate operand 0, clear bits indicate operand 1. The parts are defined
691 by the mode of the vectors. */
692 DEF_RTL_EXPR(VEC_MERGE, "vec_merge", "eee", RTX_TERNARY)
694 /* Describes an operation that selects parts of a vector.
695 Operands 0 is the source vector, operand 1 is a PARALLEL that contains
696 a CONST_INT for each of the subparts of the result vector, giving the
697 number of the source subpart that should be stored into it. */
698 DEF_RTL_EXPR(VEC_SELECT, "vec_select", "ee", RTX_BIN_ARITH)
700 /* Describes a vector concat operation. Operands 0 and 1 are the source
701 vectors, the result is a vector that is as long as operands 0 and 1
702 combined and is the concatenation of the two source vectors. */
703 DEF_RTL_EXPR(VEC_CONCAT, "vec_concat", "ee", RTX_BIN_ARITH)
705 /* Describes an operation that converts a small vector into a larger one by
706 duplicating the input values. The output vector mode must have the same
707 submodes as the input vector mode, and the number of output parts must be
708 an integer multiple of the number of input parts. */
709 DEF_RTL_EXPR(VEC_DUPLICATE, "vec_duplicate", "e", RTX_UNARY)
711 /* Addition with signed saturation */
712 DEF_RTL_EXPR(SS_PLUS, "ss_plus", "ee", RTX_COMM_ARITH)
714 /* Addition with unsigned saturation */
715 DEF_RTL_EXPR(US_PLUS, "us_plus", "ee", RTX_COMM_ARITH)
717 /* Operand 0 minus operand 1, with signed saturation. */
718 DEF_RTL_EXPR(SS_MINUS, "ss_minus", "ee", RTX_BIN_ARITH)
720 /* Negation with signed saturation. */
721 DEF_RTL_EXPR(SS_NEG, "ss_neg", "e", RTX_UNARY)
722 /* Negation with unsigned saturation. */
723 DEF_RTL_EXPR(US_NEG, "us_neg", "e", RTX_UNARY)
725 /* Absolute value with signed saturation. */
726 DEF_RTL_EXPR(SS_ABS, "ss_abs", "e", RTX_UNARY)
728 /* Shift left with signed saturation. */
729 DEF_RTL_EXPR(SS_ASHIFT, "ss_ashift", "ee", RTX_BIN_ARITH)
731 /* Shift left with unsigned saturation. */
732 DEF_RTL_EXPR(US_ASHIFT, "us_ashift", "ee", RTX_BIN_ARITH)
734 /* Operand 0 minus operand 1, with unsigned saturation. */
735 DEF_RTL_EXPR(US_MINUS, "us_minus", "ee", RTX_BIN_ARITH)
737 /* Signed saturating truncate. */
738 DEF_RTL_EXPR(SS_TRUNCATE, "ss_truncate", "e", RTX_UNARY)
740 /* Unsigned saturating truncate. */
741 DEF_RTL_EXPR(US_TRUNCATE, "us_truncate", "e", RTX_UNARY)
743 /* Floating point multiply/add combined instruction. */
744 DEF_RTL_EXPR(FMA, "fma", "eee", RTX_TERNARY)
746 /* Information about the variable and its location. */
747 /* Changed 'te' to 'tei'; the 'i' field is for recording
748 initialization status of variables. */
749 DEF_RTL_EXPR(VAR_LOCATION, "var_location", "tei", RTX_EXTRA)
751 /* Used in VAR_LOCATION for a pointer to a decl that is no longer
753 DEF_RTL_EXPR(DEBUG_IMPLICIT_PTR, "debug_implicit_ptr", "t", RTX_OBJ)
755 /* Represents value that argument had on function entry. The
756 single argument is the DECL_INCOMING_RTL of the corresponding
758 DEF_RTL_EXPR(ENTRY_VALUE, "entry_value", "0", RTX_OBJ)
760 /* Used in VAR_LOCATION for a reference to a parameter that has
761 been optimized away completely. */
762 DEF_RTL_EXPR(DEBUG_PARAMETER_REF, "debug_parameter_ref", "t", RTX_OBJ)
764 /* All expressions from this point forward appear only in machine
766 #ifdef GENERATOR_FILE
768 /* Pattern-matching operators: */
770 /* Use the function named by the second arg (the string)
771 as a predicate; if matched, store the structure that was matched
772 in the operand table at index specified by the first arg (the integer).
773 If the second arg is the null string, the structure is just stored.
775 A third string argument indicates to the register allocator restrictions
776 on where the operand can be allocated.
778 If the target needs no restriction on any instruction this field should
781 The string is prepended by:
782 '=' to indicate the operand is only written to.
783 '+' to indicate the operand is both read and written to.
785 Each character in the string represents an allocable class for an operand.
786 'g' indicates the operand can be any valid class.
787 'i' indicates the operand can be immediate (in the instruction) data.
788 'r' indicates the operand can be in a register.
789 'm' indicates the operand can be in memory.
790 'o' a subset of the 'm' class. Those memory addressing modes that
791 can be offset at compile time (have a constant added to them).
793 Other characters indicate target dependent operand classes and
794 are described in each target's machine description.
796 For instructions with more than one operand, sets of classes can be
797 separated by a comma to indicate the appropriate multi-operand constraints.
798 There must be a 1 to 1 correspondence between these sets of classes in
799 all operands for an instruction.
801 DEF_RTL_EXPR(MATCH_OPERAND, "match_operand", "iss", RTX_MATCH)
803 /* Match a SCRATCH or a register. When used to generate rtl, a
804 SCRATCH is generated. As for MATCH_OPERAND, the mode specifies
805 the desired mode and the first argument is the operand number.
806 The second argument is the constraint. */
807 DEF_RTL_EXPR(MATCH_SCRATCH, "match_scratch", "is", RTX_MATCH)
809 /* Apply a predicate, AND match recursively the operands of the rtx.
810 Operand 0 is the operand-number, as in match_operand.
811 Operand 1 is a predicate to apply (as a string, a function name).
812 Operand 2 is a vector of expressions, each of which must match
813 one subexpression of the rtx this construct is matching. */
814 DEF_RTL_EXPR(MATCH_OPERATOR, "match_operator", "isE", RTX_MATCH)
816 /* Match a PARALLEL of arbitrary length. The predicate is applied
817 to the PARALLEL and the initial expressions in the PARALLEL are matched.
818 Operand 0 is the operand-number, as in match_operand.
819 Operand 1 is a predicate to apply to the PARALLEL.
820 Operand 2 is a vector of expressions, each of which must match the
821 corresponding element in the PARALLEL. */
822 DEF_RTL_EXPR(MATCH_PARALLEL, "match_parallel", "isE", RTX_MATCH)
824 /* Match only something equal to what is stored in the operand table
825 at the index specified by the argument. Use with MATCH_OPERAND. */
826 DEF_RTL_EXPR(MATCH_DUP, "match_dup", "i", RTX_MATCH)
828 /* Match only something equal to what is stored in the operand table
829 at the index specified by the argument. Use with MATCH_OPERATOR. */
830 DEF_RTL_EXPR(MATCH_OP_DUP, "match_op_dup", "iE", RTX_MATCH)
832 /* Match only something equal to what is stored in the operand table
833 at the index specified by the argument. Use with MATCH_PARALLEL. */
834 DEF_RTL_EXPR(MATCH_PAR_DUP, "match_par_dup", "iE", RTX_MATCH)
836 /* Appears only in define_predicate/define_special_predicate
837 expressions. Evaluates true only if the operand has an RTX code
838 from the set given by the argument (a comma-separated list). If the
839 second argument is present and nonempty, it is a sequence of digits
840 and/or letters which indicates the subexpression to test, using the
841 same syntax as genextract/genrecog's location strings: 0-9 for
842 XEXP (op, n), a-z for XVECEXP (op, 0, n); each character applies to
843 the result of the one before it. */
844 DEF_RTL_EXPR(MATCH_CODE, "match_code", "ss", RTX_MATCH)
846 /* Used to inject a C conditional expression into an .md file. It can
847 appear in a predicate definition or an attribute expression. */
848 DEF_RTL_EXPR(MATCH_TEST, "match_test", "s", RTX_MATCH)
850 /* Insn (and related) definitions. */
852 /* Definition of the pattern for one kind of instruction.
854 0: names this instruction.
855 If the name is the null string, the instruction is in the
856 machine description just to be recognized, and will never be emitted by
857 the tree to rtl expander.
859 2: is a string which is a C expression
860 giving an additional condition for recognizing this pattern.
861 A null string means no extra condition.
862 3: is the action to execute if this pattern is matched.
863 If this assembler code template starts with a * then it is a fragment of
864 C code to run to decide on a template to use. Otherwise, it is the
866 4: optionally, a vector of attributes for this insn.
868 DEF_RTL_EXPR(DEFINE_INSN, "define_insn", "sEsTV", RTX_EXTRA)
870 /* Definition of a peephole optimization.
871 1st operand: vector of insn patterns to match
872 2nd operand: C expression that must be true
873 3rd operand: template or C code to produce assembler output.
874 4: optionally, a vector of attributes for this insn.
876 This form is deprecated; use define_peephole2 instead. */
877 DEF_RTL_EXPR(DEFINE_PEEPHOLE, "define_peephole", "EsTV", RTX_EXTRA)
879 /* Definition of a split operation.
880 1st operand: insn pattern to match
881 2nd operand: C expression that must be true
882 3rd operand: vector of insn patterns to place into a SEQUENCE
883 4th operand: optionally, some C code to execute before generating the
884 insns. This might, for example, create some RTX's and store them in
885 elements of `recog_data.operand' for use by the vector of
887 (`operands' is an alias here for `recog_data.operand'). */
888 DEF_RTL_EXPR(DEFINE_SPLIT, "define_split", "EsES", RTX_EXTRA)
890 /* Definition of an insn and associated split.
891 This is the concatenation, with a few modifications, of a define_insn
892 and a define_split which share the same pattern.
894 0: names this instruction.
895 If the name is the null string, the instruction is in the
896 machine description just to be recognized, and will never be emitted by
897 the tree to rtl expander.
899 2: is a string which is a C expression
900 giving an additional condition for recognizing this pattern.
901 A null string means no extra condition.
902 3: is the action to execute if this pattern is matched.
903 If this assembler code template starts with a * then it is a fragment of
904 C code to run to decide on a template to use. Otherwise, it is the
906 4: C expression that must be true for split. This may start with "&&"
907 in which case the split condition is the logical and of the insn
908 condition and what follows the "&&" of this operand.
909 5: vector of insn patterns to place into a SEQUENCE
910 6: optionally, some C code to execute before generating the
911 insns. This might, for example, create some RTX's and store them in
912 elements of `recog_data.operand' for use by the vector of
914 (`operands' is an alias here for `recog_data.operand').
915 7: optionally, a vector of attributes for this insn. */
916 DEF_RTL_EXPR(DEFINE_INSN_AND_SPLIT, "define_insn_and_split", "sEsTsESV", RTX_EXTRA)
918 /* Definition of an RTL peephole operation.
919 Follows the same arguments as define_split. */
920 DEF_RTL_EXPR(DEFINE_PEEPHOLE2, "define_peephole2", "EsES", RTX_EXTRA)
922 /* Define how to generate multiple insns for a standard insn name.
923 1st operand: the insn name.
924 2nd operand: vector of insn-patterns.
925 Use match_operand to substitute an element of `recog_data.operand'.
926 3rd operand: C expression that must be true for this to be available.
927 This may not test any operands.
928 4th operand: Extra C code to execute before generating the insns.
929 This might, for example, create some RTX's and store them in
930 elements of `recog_data.operand' for use by the vector of
932 (`operands' is an alias here for `recog_data.operand').
933 5th: optionally, a vector of attributes for this expand. */
934 DEF_RTL_EXPR(DEFINE_EXPAND, "define_expand", "sEssV", RTX_EXTRA)
936 /* Define a requirement for delay slots.
937 1st operand: Condition involving insn attributes that, if true,
938 indicates that the insn requires the number of delay slots
940 2nd operand: Vector whose length is the three times the number of delay
942 Each entry gives three conditions, each involving attributes.
943 The first must be true for an insn to occupy that delay slot
944 location. The second is true for all insns that can be
945 annulled if the branch is true and the third is true for all
946 insns that can be annulled if the branch is false.
948 Multiple DEFINE_DELAYs may be present. They indicate differing
949 requirements for delay slots. */
950 DEF_RTL_EXPR(DEFINE_DELAY, "define_delay", "eE", RTX_EXTRA)
952 /* Define attribute computation for `asm' instructions. */
953 DEF_RTL_EXPR(DEFINE_ASM_ATTRIBUTES, "define_asm_attributes", "V", RTX_EXTRA)
955 /* Definition of a conditional execution meta operation. Automatically
956 generates new instances of DEFINE_INSN, selected by having attribute
957 "predicable" true. The new pattern will contain a COND_EXEC and the
958 predicate at top-level.
961 0: The predicate pattern. The top-level form should match a
962 relational operator. Operands should have only one alternative.
963 1: A C expression giving an additional condition for recognizing
964 the generated pattern.
965 2: A template or C code to produce assembler output. */
966 DEF_RTL_EXPR(DEFINE_COND_EXEC, "define_cond_exec", "Ess", RTX_EXTRA)
968 /* Definition of an operand predicate. The difference between
969 DEFINE_PREDICATE and DEFINE_SPECIAL_PREDICATE is that genrecog will
970 not warn about a match_operand with no mode if it has a predicate
971 defined with DEFINE_SPECIAL_PREDICATE.
974 0: The name of the predicate.
975 1: A boolean expression which computes whether or not the predicate
976 matches. This expression can use IOR, AND, NOT, MATCH_OPERAND,
977 MATCH_CODE, and MATCH_TEST. It must be specific enough that genrecog
978 can calculate the set of RTX codes that can possibly match.
979 2: A C function body which must return true for the predicate to match.
980 Optional. Use this when the test is too complicated to fit into a
981 match_test expression. */
982 DEF_RTL_EXPR(DEFINE_PREDICATE, "define_predicate", "ses", RTX_EXTRA)
983 DEF_RTL_EXPR(DEFINE_SPECIAL_PREDICATE, "define_special_predicate", "ses", RTX_EXTRA)
985 /* Definition of a register operand constraint. This simply maps the
986 constraint string to a register class.
989 0: The name of the constraint (often, but not always, a single letter).
990 1: A C expression which evaluates to the appropriate register class for
991 this constraint. If this is not just a constant, it should look only
992 at -m switches and the like.
993 2: A docstring for this constraint, in Texinfo syntax; not currently
994 used, in future will be incorporated into the manual's list of
995 machine-specific operand constraints. */
996 DEF_RTL_EXPR(DEFINE_REGISTER_CONSTRAINT, "define_register_constraint", "sss", RTX_EXTRA)
998 /* Definition of a non-register operand constraint. These look at the
999 operand and decide whether it fits the constraint.
1001 DEFINE_CONSTRAINT gets no special treatment if it fails to match.
1002 It is appropriate for constant-only constraints, and most others.
1004 DEFINE_MEMORY_CONSTRAINT tells reload that this constraint can be made
1005 to match, if it doesn't already, by converting the operand to the form
1006 (mem (reg X)) where X is a base register. It is suitable for constraints
1007 that describe a subset of all memory references.
1009 DEFINE_ADDRESS_CONSTRAINT tells reload that this constraint can be made
1010 to match, if it doesn't already, by converting the operand to the form
1011 (reg X) where X is a base register. It is suitable for constraints that
1012 describe a subset of all address references.
1014 When in doubt, use plain DEFINE_CONSTRAINT.
1017 0: The name of the constraint (often, but not always, a single letter).
1018 1: A docstring for this constraint, in Texinfo syntax; not currently
1019 used, in future will be incorporated into the manual's list of
1020 machine-specific operand constraints.
1021 2: A boolean expression which computes whether or not the constraint
1022 matches. It should follow the same rules as a define_predicate
1023 expression, including the bit about specifying the set of RTX codes
1024 that could possibly match. MATCH_TEST subexpressions may make use of
1026 `op' - the RTL object defining the operand.
1027 `mode' - the mode of `op'.
1028 `ival' - INTVAL(op), if op is a CONST_INT.
1029 `hval' - CONST_DOUBLE_HIGH(op), if op is an integer CONST_DOUBLE.
1030 `lval' - CONST_DOUBLE_LOW(op), if op is an integer CONST_DOUBLE.
1031 `rval' - CONST_DOUBLE_REAL_VALUE(op), if op is a floating-point
1033 Do not use ival/hval/lval/rval if op is not the appropriate kind of
1035 DEF_RTL_EXPR(DEFINE_CONSTRAINT, "define_constraint", "sse", RTX_EXTRA)
1036 DEF_RTL_EXPR(DEFINE_MEMORY_CONSTRAINT, "define_memory_constraint", "sse", RTX_EXTRA)
1037 DEF_RTL_EXPR(DEFINE_ADDRESS_CONSTRAINT, "define_address_constraint", "sse", RTX_EXTRA)
1040 /* Constructions for CPU pipeline description described by NDFAs. */
1042 /* (define_cpu_unit string [string]) describes cpu functional
1043 units (separated by comma).
1045 1st operand: Names of cpu functional units.
1046 2nd operand: Name of automaton (see comments for DEFINE_AUTOMATON).
1048 All define_reservations, define_cpu_units, and
1049 define_query_cpu_units should have unique names which may not be
1051 DEF_RTL_EXPR(DEFINE_CPU_UNIT, "define_cpu_unit", "sS", RTX_EXTRA)
1053 /* (define_query_cpu_unit string [string]) describes cpu functional
1054 units analogously to define_cpu_unit. The reservation of such
1055 units can be queried for automaton state. */
1056 DEF_RTL_EXPR(DEFINE_QUERY_CPU_UNIT, "define_query_cpu_unit", "sS", RTX_EXTRA)
1058 /* (exclusion_set string string) means that each CPU functional unit
1059 in the first string can not be reserved simultaneously with any
1060 unit whose name is in the second string and vise versa. CPU units
1061 in the string are separated by commas. For example, it is useful
1062 for description CPU with fully pipelined floating point functional
1063 unit which can execute simultaneously only single floating point
1064 insns or only double floating point insns. All CPU functional
1065 units in a set should belong to the same automaton. */
1066 DEF_RTL_EXPR(EXCLUSION_SET, "exclusion_set", "ss", RTX_EXTRA)
1068 /* (presence_set string string) means that each CPU functional unit in
1069 the first string can not be reserved unless at least one of pattern
1070 of units whose names are in the second string is reserved. This is
1071 an asymmetric relation. CPU units or unit patterns in the strings
1072 are separated by commas. Pattern is one unit name or unit names
1073 separated by white-spaces.
1075 For example, it is useful for description that slot1 is reserved
1076 after slot0 reservation for a VLIW processor. We could describe it
1077 by the following construction
1079 (presence_set "slot1" "slot0")
1081 Or slot1 is reserved only after slot0 and unit b0 reservation. In
1082 this case we could write
1084 (presence_set "slot1" "slot0 b0")
1086 All CPU functional units in a set should belong to the same
1088 DEF_RTL_EXPR(PRESENCE_SET, "presence_set", "ss", RTX_EXTRA)
1090 /* (final_presence_set string string) is analogous to `presence_set'.
1091 The difference between them is when checking is done. When an
1092 instruction is issued in given automaton state reflecting all
1093 current and planned unit reservations, the automaton state is
1094 changed. The first state is a source state, the second one is a
1095 result state. Checking for `presence_set' is done on the source
1096 state reservation, checking for `final_presence_set' is done on the
1097 result reservation. This construction is useful to describe a
1098 reservation which is actually two subsequent reservations. For
1101 (presence_set "slot1" "slot0")
1103 the following insn will be never issued (because slot1 requires
1104 slot0 which is absent in the source state).
1106 (define_reservation "insn_and_nop" "slot0 + slot1")
1108 but it can be issued if we use analogous `final_presence_set'. */
1109 DEF_RTL_EXPR(FINAL_PRESENCE_SET, "final_presence_set", "ss", RTX_EXTRA)
1111 /* (absence_set string string) means that each CPU functional unit in
1112 the first string can be reserved only if each pattern of units
1113 whose names are in the second string is not reserved. This is an
1114 asymmetric relation (actually exclusion set is analogous to this
1115 one but it is symmetric). CPU units or unit patterns in the string
1116 are separated by commas. Pattern is one unit name or unit names
1117 separated by white-spaces.
1119 For example, it is useful for description that slot0 can not be
1120 reserved after slot1 or slot2 reservation for a VLIW processor. We
1121 could describe it by the following construction
1123 (absence_set "slot2" "slot0, slot1")
1125 Or slot2 can not be reserved if slot0 and unit b0 are reserved or
1126 slot1 and unit b1 are reserved . In this case we could write
1128 (absence_set "slot2" "slot0 b0, slot1 b1")
1130 All CPU functional units in a set should to belong the same
1132 DEF_RTL_EXPR(ABSENCE_SET, "absence_set", "ss", RTX_EXTRA)
1134 /* (final_absence_set string string) is analogous to `absence_set' but
1135 checking is done on the result (state) reservation. See comments
1136 for `final_presence_set'. */
1137 DEF_RTL_EXPR(FINAL_ABSENCE_SET, "final_absence_set", "ss", RTX_EXTRA)
1139 /* (define_bypass number out_insn_names in_insn_names) names bypass
1140 with given latency (the first number) from insns given by the first
1141 string (see define_insn_reservation) into insns given by the second
1142 string. Insn names in the strings are separated by commas. The
1143 third operand is optional name of function which is additional
1144 guard for the bypass. The function will get the two insns as
1145 parameters. If the function returns zero the bypass will be
1146 ignored for this case. Additional guard is necessary to recognize
1147 complicated bypasses, e.g. when consumer is load address. If there
1148 are more one bypass with the same output and input insns, the
1149 chosen bypass is the first bypass with a guard in description whose
1150 guard function returns nonzero. If there is no such bypass, then
1151 bypass without the guard function is chosen. */
1152 DEF_RTL_EXPR(DEFINE_BYPASS, "define_bypass", "issS", RTX_EXTRA)
1154 /* (define_automaton string) describes names of automata generated and
1155 used for pipeline hazards recognition. The names are separated by
1156 comma. Actually it is possibly to generate the single automaton
1157 but unfortunately it can be very large. If we use more one
1158 automata, the summary size of the automata usually is less than the
1159 single one. The automaton name is used in define_cpu_unit and
1160 define_query_cpu_unit. All automata should have unique names. */
1161 DEF_RTL_EXPR(DEFINE_AUTOMATON, "define_automaton", "s", RTX_EXTRA)
1163 /* (automata_option string) describes option for generation of
1164 automata. Currently there are the following options:
1166 o "no-minimization" which makes no minimization of automata. This
1167 is only worth to do when we are debugging the description and
1168 need to look more accurately at reservations of states.
1170 o "time" which means printing additional time statistics about
1171 generation of automata.
1173 o "v" which means generation of file describing the result
1174 automata. The file has suffix `.dfa' and can be used for the
1175 description verification and debugging.
1177 o "w" which means generation of warning instead of error for
1178 non-critical errors.
1180 o "ndfa" which makes nondeterministic finite state automata.
1182 o "progress" which means output of a progress bar showing how many
1183 states were generated so far for automaton being processed. */
1184 DEF_RTL_EXPR(AUTOMATA_OPTION, "automata_option", "s", RTX_EXTRA)
1186 /* (define_reservation string string) names reservation (the first
1187 string) of cpu functional units (the 2nd string). Sometimes unit
1188 reservations for different insns contain common parts. In such
1189 case, you can describe common part and use its name (the 1st
1190 parameter) in regular expression in define_insn_reservation. All
1191 define_reservations, define_cpu_units, and define_query_cpu_units
1192 should have unique names which may not be "nothing". */
1193 DEF_RTL_EXPR(DEFINE_RESERVATION, "define_reservation", "ss", RTX_EXTRA)
1195 /* (define_insn_reservation name default_latency condition regexpr)
1196 describes reservation of cpu functional units (the 3nd operand) for
1197 instruction which is selected by the condition (the 2nd parameter).
1198 The first parameter is used for output of debugging information.
1199 The reservations are described by a regular expression according
1200 the following syntax:
1202 regexp = regexp "," oneof
1205 oneof = oneof "|" allof
1208 allof = allof "+" repeat
1211 repeat = element "*" number
1214 element = cpu_function_unit_name
1220 1. "," is used for describing start of the next cycle in
1223 2. "|" is used for describing the reservation described by the
1224 first regular expression *or* the reservation described by the
1225 second regular expression *or* etc.
1227 3. "+" is used for describing the reservation described by the
1228 first regular expression *and* the reservation described by the
1229 second regular expression *and* etc.
1231 4. "*" is used for convenience and simply means sequence in
1232 which the regular expression are repeated NUMBER times with
1233 cycle advancing (see ",").
1235 5. cpu functional unit name which means its reservation.
1237 6. reservation name -- see define_reservation.
1239 7. string "nothing" means no units reservation. */
1241 DEF_RTL_EXPR(DEFINE_INSN_RESERVATION, "define_insn_reservation", "sies", RTX_EXTRA)
1243 /* Expressions used for insn attributes. */
1245 /* Definition of an insn attribute.
1246 1st operand: name of the attribute
1247 2nd operand: comma-separated list of possible attribute values
1248 3rd operand: expression for the default value of the attribute. */
1249 DEF_RTL_EXPR(DEFINE_ATTR, "define_attr", "sse", RTX_EXTRA)
1251 /* Definition of an insn attribute that uses an existing enumerated type.
1252 1st operand: name of the attribute
1253 2nd operand: the name of the enumerated type
1254 3rd operand: expression for the default value of the attribute. */
1255 DEF_RTL_EXPR(DEFINE_ENUM_ATTR, "define_enum_attr", "sse", RTX_EXTRA)
1257 /* Marker for the name of an attribute. */
1258 DEF_RTL_EXPR(ATTR, "attr", "s", RTX_EXTRA)
1260 /* For use in the last (optional) operand of DEFINE_INSN or DEFINE_PEEPHOLE and
1261 in DEFINE_ASM_INSN to specify an attribute to assign to insns matching that
1264 (set_attr "name" "value") is equivalent to
1265 (set (attr "name") (const_string "value")) */
1266 DEF_RTL_EXPR(SET_ATTR, "set_attr", "ss", RTX_EXTRA)
1268 /* In the last operand of DEFINE_INSN and DEFINE_PEEPHOLE, this can be used to
1269 specify that attribute values are to be assigned according to the
1270 alternative matched.
1272 The following three expressions are equivalent:
1274 (set (attr "att") (cond [(eq_attrq "alternative" "1") (const_string "a1")
1275 (eq_attrq "alternative" "2") (const_string "a2")]
1276 (const_string "a3")))
1277 (set_attr_alternative "att" [(const_string "a1") (const_string "a2")
1278 (const_string "a3")])
1279 (set_attr "att" "a1,a2,a3")
1281 DEF_RTL_EXPR(SET_ATTR_ALTERNATIVE, "set_attr_alternative", "sE", RTX_EXTRA)
1283 /* A conditional expression true if the value of the specified attribute of
1284 the current insn equals the specified value. The first operand is the
1285 attribute name and the second is the comparison value. */
1286 DEF_RTL_EXPR(EQ_ATTR, "eq_attr", "ss", RTX_EXTRA)
1288 /* A special case of the above representing a set of alternatives. The first
1289 operand is bitmap of the set, the second one is the default value. */
1290 DEF_RTL_EXPR(EQ_ATTR_ALT, "eq_attr_alt", "ii", RTX_EXTRA)
1292 /* A conditional expression which is true if the specified flag is
1293 true for the insn being scheduled in reorg.
1295 genattr.c defines the following flags which can be tested by
1296 (attr_flag "foo") expressions in eligible_for_delay: forward, backward. */
1298 DEF_RTL_EXPR (ATTR_FLAG, "attr_flag", "s", RTX_EXTRA)
1300 /* General conditional. The first operand is a vector composed of pairs of
1301 expressions. The first element of each pair is evaluated, in turn.
1302 The value of the conditional is the second expression of the first pair
1303 whose first expression evaluates nonzero. If none of the expressions is
1304 true, the second operand will be used as the value of the conditional. */
1305 DEF_RTL_EXPR(COND, "cond", "Ee", RTX_EXTRA)
1307 /* Definition of a pattern substitution meta operation on a DEFINE_EXPAND
1308 or a DEFINE_INSN. Automatically generates new instances of DEFINE_INSNs
1309 that match the substitution pattern.
1312 0: The name of the substitition template.
1313 1: Input template to match to see if a substitution is applicable.
1314 2: A C expression giving an additional condition for the generated
1315 new define_expand or define_insn.
1316 3: Output tempalate to generate via substitution.
1318 Within a DEFINE_SUBST template, the meaning of some RTL expressions is
1319 different from their usual interpretation: a MATCH_OPERAND matches any
1320 expression tree with matching machine mode or with VOIDmode. Likewise,
1321 MATCH_OP_DUP and MATCH_DUP match more liberally in a DEFINE_SUBST than
1322 in other RTL expressions. MATCH_OPERATOR matches all common operators
1323 but also UNSPEC, UNSPEC_VOLATILE, and MATCH_OPERATORS from the input
1324 DEFINE_EXPAND or DEFINE_INSN. */
1325 DEF_RTL_EXPR(DEFINE_SUBST, "define_subst", "sEsE", RTX_EXTRA)
1327 /* Substitution attribute to apply a DEFINE_SUBST to a pattern.
1330 0: The name of the subst-attribute.
1331 1: The name of the DEFINE_SUBST to be applied for this attribute.
1332 2: String to substitute for the subst-attribute name in the pattern
1333 name, for the case that the DEFINE_SUBST is not applied (i.e. the
1334 unmodified version of the pattern).
1335 3: String to substitute for the subst-attribute name in the pattern
1336 name, for the case that the DEFINE_SUBST is applied to the patten.
1338 The use of DEFINE_SUBST and DEFINE_SUBST_ATTR is explained in the
1339 GCC internals manual, under "RTL Templates Transformations". */
1340 DEF_RTL_EXPR(DEFINE_SUBST_ATTR, "define_subst_attr", "ssss", RTX_EXTRA)
1342 #endif /* GENERATOR_FILE */