1 /* This file contains the definitions and documentation for the
2 Register Transfer Expressions (rtx's) that make up the
3 Register Transfer Language (rtl) used in the Back End of the GNU compiler.
4 Copyright (C) 1987, 1988, 1992, 1994, 1995, 1997, 1998, 1999, 2000, 2004,
6 Free Software Foundation, Inc.
8 This file is part of GCC.
10 GCC is free software; you can redistribute it and/or modify it under
11 the terms of the GNU General Public License as published by the Free
12 Software Foundation; either version 2, or (at your option) any later
15 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
16 WARRANTY; without even the implied warranty of MERCHANTABILITY or
17 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING. If not, write to the Free
22 Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
26 /* Expression definitions and descriptions for all targets are in this file.
27 Some will not be used for some targets.
29 The fields in the cpp macro call "DEF_RTL_EXPR()"
30 are used to create declarations in the C source of the compiler.
34 1. The internal name of the rtx used in the C source.
35 It is a tag in the enumeration "enum rtx_code" defined in "rtl.h".
36 By convention these are in UPPER_CASE.
38 2. The name of the rtx in the external ASCII format read by
39 read_rtx(), and printed by print_rtx().
40 These names are stored in rtx_name[].
41 By convention these are the internal (field 1) names in lower_case.
43 3. The print format, and type of each rtx->u.fld[] (field) in this rtx.
44 These formats are stored in rtx_format[].
45 The meaning of the formats is documented in front of this array in rtl.c
47 4. The class of the rtx. These are stored in rtx_class and are accessed
48 via the GET_RTX_CLASS macro. They are defined as follows:
51 an rtx code that can be used to represent a constant object
54 an rtx code that can be used to represent an object (e.g, REG, MEM)
56 an rtx code for a comparison (e.g, LT, GT)
58 an rtx code for a commutative comparison (e.g, EQ, NE, ORDERED)
60 an rtx code for a unary arithmetic expression (e.g, NEG, NOT)
62 an rtx code for a commutative binary operation (e.g,, PLUS, MULT)
64 an rtx code for a non-bitfield three input operation (IF_THEN_ELSE)
66 an rtx code for a non-commutative binary operation (e.g., MINUS, DIV)
68 an rtx code for a bit-field operation (ZERO_EXTRACT, SIGN_EXTRACT)
70 an rtx code for a machine insn (INSN, JUMP_INSN, CALL_INSN)
72 an rtx code for something that matches in insns (e.g, MATCH_DUP)
74 an rtx code for autoincrement addressing modes (e.g. POST_DEC)
78 All of the expressions that appear only in machine descriptions,
79 not in RTL used by the compiler itself, are at the end of the file. */
81 /* Unknown, or no such operation; the enumeration constant should have
83 DEF_RTL_EXPR(UNKNOWN, "UnKnown", "*", RTX_EXTRA)
85 /* ---------------------------------------------------------------------
86 Expressions used in constructing lists.
87 --------------------------------------------------------------------- */
89 /* a linked list of expressions */
90 DEF_RTL_EXPR(EXPR_LIST, "expr_list", "ee", RTX_EXTRA)
92 /* a linked list of instructions.
93 The insns are represented in print by their uids. */
94 DEF_RTL_EXPR(INSN_LIST, "insn_list", "ue", RTX_EXTRA)
96 /* a linked list of dependencies.
97 The insns are represented in print by their uids.
98 Operand 2 is the status of a dependence (see sched-int.h for more). */
99 DEF_RTL_EXPR(DEPS_LIST, "deps_list", "uei", RTX_EXTRA)
101 /* SEQUENCE appears in the result of a `gen_...' function
102 for a DEFINE_EXPAND that wants to make several insns.
103 Its elements are the bodies of the insns that should be made.
104 `emit_insn' takes the SEQUENCE apart and makes separate insns. */
105 DEF_RTL_EXPR(SEQUENCE, "sequence", "E", RTX_EXTRA)
107 /* Refers to the address of its argument. This is only used in alias.c. */
108 DEF_RTL_EXPR(ADDRESS, "address", "e", RTX_MATCH)
110 /* ----------------------------------------------------------------------
111 Expression types used for things in the instruction chain.
113 All formats must start with "iuu" to handle the chain.
114 Each insn expression holds an rtl instruction and its semantics
115 during back-end processing.
116 See macros's in "rtl.h" for the meaning of each rtx->u.fld[].
118 ---------------------------------------------------------------------- */
120 /* An instruction that cannot jump. */
121 DEF_RTL_EXPR(INSN, "insn", "iuuBieiee", RTX_INSN)
123 /* An instruction that can possibly jump.
124 Fields ( rtx->u.fld[] ) have exact same meaning as INSN's. */
125 DEF_RTL_EXPR(JUMP_INSN, "jump_insn", "iuuBieiee0", RTX_INSN)
127 /* An instruction that can possibly call a subroutine
128 but which will not change which instruction comes next
129 in the current function.
130 Field ( rtx->u.fld[9] ) is CALL_INSN_FUNCTION_USAGE.
131 All other fields ( rtx->u.fld[] ) have exact same meaning as INSN's. */
132 DEF_RTL_EXPR(CALL_INSN, "call_insn", "iuuBieieee", RTX_INSN)
134 /* A marker that indicates that control will not flow through. */
135 DEF_RTL_EXPR(BARRIER, "barrier", "iuu000000", RTX_EXTRA)
137 /* Holds a label that is followed by instructions.
139 4: is used in jump.c for the use-count of the label.
140 5: is used in flow.c to point to the chain of label_ref's to this label.
141 6: is a number that is unique in the entire compilation.
142 7: is the user-given name of the label, if any. */
143 DEF_RTL_EXPR(CODE_LABEL, "code_label", "iuuB00is", RTX_EXTRA)
145 #ifdef USE_MAPPED_LOCATION
146 /* Say where in the code a source line starts, for symbol table's sake.
148 4: unused if line number > 0, note-specific data otherwise.
149 5: line number if > 0, enum note_insn otherwise.
150 6: CODE_LABEL_NUMBER if line number == NOTE_INSN_DELETED_LABEL. */
152 /* Say where in the code a source line starts, for symbol table's sake.
154 4: filename, if line number > 0, note-specific data otherwise.
155 5: line number if > 0, enum note_insn otherwise.
156 6: unique number if line number == note_insn_deleted_label. */
158 DEF_RTL_EXPR(NOTE, "note", "iuuB0ni", RTX_EXTRA)
160 /* ----------------------------------------------------------------------
161 Top level constituents of INSN, JUMP_INSN and CALL_INSN.
162 ---------------------------------------------------------------------- */
164 /* Conditionally execute code.
165 Operand 0 is the condition that if true, the code is executed.
166 Operand 1 is the code to be executed (typically a SET).
168 Semantics are that there are no side effects if the condition
169 is false. This pattern is created automatically by the if_convert
170 pass run after reload or by target-specific splitters. */
171 DEF_RTL_EXPR(COND_EXEC, "cond_exec", "ee", RTX_EXTRA)
173 /* Several operations to be done in parallel (perhaps under COND_EXEC). */
174 DEF_RTL_EXPR(PARALLEL, "parallel", "E", RTX_EXTRA)
176 /* A string that is passed through to the assembler as input.
177 One can obviously pass comments through by using the
178 assembler comment syntax.
179 These occur in an insn all by themselves as the PATTERN.
180 They also appear inside an ASM_OPERANDS
181 as a convenient way to hold a string. */
182 DEF_RTL_EXPR(ASM_INPUT, "asm_input", "s", RTX_EXTRA)
184 #ifdef USE_MAPPED_LOCATION
185 /* An assembler instruction with operands.
186 1st operand is the instruction template.
187 2nd operand is the constraint for the output.
188 3rd operand is the number of the output this expression refers to.
189 When an insn stores more than one value, a separate ASM_OPERANDS
190 is made for each output; this integer distinguishes them.
191 4th is a vector of values of input operands.
192 5th is a vector of modes and constraints for the input operands.
193 Each element is an ASM_INPUT containing a constraint string
194 and whose mode indicates the mode of the input operand.
195 6th is the source line number. */
196 DEF_RTL_EXPR(ASM_OPERANDS, "asm_operands", "ssiEEi", RTX_EXTRA)
198 /* An assembler instruction with operands.
199 1st operand is the instruction template.
200 2nd operand is the constraint for the output.
201 3rd operand is the number of the output this expression refers to.
202 When an insn stores more than one value, a separate ASM_OPERANDS
203 is made for each output; this integer distinguishes them.
204 4th is a vector of values of input operands.
205 5th is a vector of modes and constraints for the input operands.
206 Each element is an ASM_INPUT containing a constraint string
207 and whose mode indicates the mode of the input operand.
208 6th is the name of the containing source file.
209 7th is the source line number. */
210 DEF_RTL_EXPR(ASM_OPERANDS, "asm_operands", "ssiEEsi", RTX_EXTRA)
213 /* A machine-specific operation.
214 1st operand is a vector of operands being used by the operation so that
215 any needed reloads can be done.
216 2nd operand is a unique value saying which of a number of machine-specific
217 operations is to be performed.
218 (Note that the vector must be the first operand because of the way that
219 genrecog.c record positions within an insn.)
220 This can occur all by itself in a PATTERN, as a component of a PARALLEL,
221 or inside an expression. */
222 DEF_RTL_EXPR(UNSPEC, "unspec", "Ei", RTX_EXTRA)
224 /* Similar, but a volatile operation and one which may trap. */
225 DEF_RTL_EXPR(UNSPEC_VOLATILE, "unspec_volatile", "Ei", RTX_EXTRA)
227 /* Vector of addresses, stored as full words. */
228 /* Each element is a LABEL_REF to a CODE_LABEL whose address we want. */
229 DEF_RTL_EXPR(ADDR_VEC, "addr_vec", "E", RTX_EXTRA)
231 /* Vector of address differences X0 - BASE, X1 - BASE, ...
232 First operand is BASE; the vector contains the X's.
233 The machine mode of this rtx says how much space to leave
234 for each difference and is adjusted by branch shortening if
235 CASE_VECTOR_SHORTEN_MODE is defined.
236 The third and fourth operands store the target labels with the
237 minimum and maximum addresses respectively.
238 The fifth operand stores flags for use by branch shortening.
239 Set at the start of shorten_branches:
240 min_align: the minimum alignment for any of the target labels.
241 base_after_vec: true iff BASE is after the ADDR_DIFF_VEC.
242 min_after_vec: true iff minimum addr target label is after the ADDR_DIFF_VEC.
243 max_after_vec: true iff maximum addr target label is after the ADDR_DIFF_VEC.
244 min_after_base: true iff minimum address target label is after BASE.
245 max_after_base: true iff maximum address target label is after BASE.
246 Set by the actual branch shortening process:
247 offset_unsigned: true iff offsets have to be treated as unsigned.
248 scale: scaling that is necessary to make offsets fit into the mode.
250 The third, fourth and fifth operands are only valid when
251 CASE_VECTOR_SHORTEN_MODE is defined, and only in an optimizing
254 DEF_RTL_EXPR(ADDR_DIFF_VEC, "addr_diff_vec", "eEee0", RTX_EXTRA)
256 /* Memory prefetch, with attributes supported on some targets.
257 Operand 1 is the address of the memory to fetch.
258 Operand 2 is 1 for a write access, 0 otherwise.
259 Operand 3 is the level of temporal locality; 0 means there is no
260 temporal locality and 1, 2, and 3 are for increasing levels of temporal
263 The attributes specified by operands 2 and 3 are ignored for targets
264 whose prefetch instructions do not support them. */
265 DEF_RTL_EXPR(PREFETCH, "prefetch", "eee", RTX_EXTRA)
267 /* ----------------------------------------------------------------------
268 At the top level of an instruction (perhaps under PARALLEL).
269 ---------------------------------------------------------------------- */
272 Operand 1 is the location (REG, MEM, PC, CC0 or whatever) assigned to.
273 Operand 2 is the value stored there.
274 ALL assignment must use SET.
275 Instructions that do multiple assignments must use multiple SET,
277 DEF_RTL_EXPR(SET, "set", "ee", RTX_EXTRA)
279 /* Indicate something is used in a way that we don't want to explain.
280 For example, subroutine calls will use the register
281 in which the static chain is passed. */
282 DEF_RTL_EXPR(USE, "use", "e", RTX_EXTRA)
284 /* Indicate something is clobbered in a way that we don't want to explain.
285 For example, subroutine calls will clobber some physical registers
286 (the ones that are by convention not saved). */
287 DEF_RTL_EXPR(CLOBBER, "clobber", "e", RTX_EXTRA)
289 /* Call a subroutine.
290 Operand 1 is the address to call.
291 Operand 2 is the number of arguments. */
293 DEF_RTL_EXPR(CALL, "call", "ee", RTX_EXTRA)
295 /* Return from a subroutine. */
297 DEF_RTL_EXPR(RETURN, "return", "", RTX_EXTRA)
300 Operand 1 is the condition.
301 Operand 2 is the trap code.
302 For an unconditional trap, make the condition (const_int 1). */
303 DEF_RTL_EXPR(TRAP_IF, "trap_if", "ee", RTX_EXTRA)
305 /* Placeholder for _Unwind_Resume before we know if a function call
306 or a branch is needed. Operand 1 is the exception region from
307 which control is flowing. */
308 DEF_RTL_EXPR(RESX, "resx", "i", RTX_EXTRA)
310 /* ----------------------------------------------------------------------
311 Primitive values for use in expressions.
312 ---------------------------------------------------------------------- */
314 /* numeric integer constant */
315 DEF_RTL_EXPR(CONST_INT, "const_int", "w", RTX_CONST_OBJ)
317 /* numeric floating point constant.
318 Operands hold the value. They are all 'w' and there may be from 2 to 6;
320 DEF_RTL_EXPR(CONST_DOUBLE, "const_double", CONST_DOUBLE_FORMAT, RTX_CONST_OBJ)
322 /* Describes a vector constant. */
323 DEF_RTL_EXPR(CONST_VECTOR, "const_vector", "E", RTX_CONST_OBJ)
325 /* String constant. Used for attributes in machine descriptions and
326 for special cases in DWARF2 debug output. NOT used for source-
327 language string constants. */
328 DEF_RTL_EXPR(CONST_STRING, "const_string", "s", RTX_OBJ)
330 /* This is used to encapsulate an expression whose value is constant
331 (such as the sum of a SYMBOL_REF and a CONST_INT) so that it will be
332 recognized as a constant operand rather than by arithmetic instructions. */
334 DEF_RTL_EXPR(CONST, "const", "e", RTX_CONST_OBJ)
336 /* program counter. Ordinary jumps are represented
337 by a SET whose first operand is (PC). */
338 DEF_RTL_EXPR(PC, "pc", "", RTX_OBJ)
340 /* Used in the cselib routines to describe a value. Objects of this
341 kind are only allocated in cselib.c, in an alloc pool instead of
342 in GC memory. The only operand of a VALUE is a cselib_val_struct. */
343 DEF_RTL_EXPR(VALUE, "value", "0", RTX_OBJ)
345 /* A register. The "operand" is the register number, accessed with
346 the REGNO macro. If this number is less than FIRST_PSEUDO_REGISTER
347 than a hardware register is being referred to. The second operand
348 holds the original register number - this will be different for a
349 pseudo register that got turned into a hard register. The third
350 operand points to a reg_attrs structure.
351 This rtx needs to have as many (or more) fields as a MEM, since we
352 can change REG rtx's into MEMs during reload. */
353 DEF_RTL_EXPR(REG, "reg", "i00", RTX_OBJ)
355 /* A scratch register. This represents a register used only within a
356 single insn. It will be turned into a REG during register allocation
357 or reload unless the constraint indicates that the register won't be
358 needed, in which case it can remain a SCRATCH. This code is
359 marked as having one operand so it can be turned into a REG. */
360 DEF_RTL_EXPR(SCRATCH, "scratch", "0", RTX_OBJ)
362 /* One word of a multi-word value.
363 The first operand is the complete value; the second says which word.
364 The WORDS_BIG_ENDIAN flag controls whether word number 0
365 (as numbered in a SUBREG) is the most or least significant word.
367 This is also used to refer to a value in a different machine mode.
368 For example, it can be used to refer to a SImode value as if it were
369 Qimode, or vice versa. Then the word number is always 0. */
370 DEF_RTL_EXPR(SUBREG, "subreg", "ei", RTX_EXTRA)
372 /* This one-argument rtx is used for move instructions
373 that are guaranteed to alter only the low part of a destination.
374 Thus, (SET (SUBREG:HI (REG...)) (MEM:HI ...))
375 has an unspecified effect on the high part of REG,
376 but (SET (STRICT_LOW_PART (SUBREG:HI (REG...))) (MEM:HI ...))
377 is guaranteed to alter only the bits of REG that are in HImode.
379 The actual instruction used is probably the same in both cases,
380 but the register constraints may be tighter when STRICT_LOW_PART
383 DEF_RTL_EXPR(STRICT_LOW_PART, "strict_low_part", "e", RTX_EXTRA)
385 /* (CONCAT a b) represents the virtual concatenation of a and b
386 to make a value that has as many bits as a and b put together.
387 This is used for complex values. Normally it appears only
388 in DECL_RTLs and during RTL generation, but not in the insn chain. */
389 DEF_RTL_EXPR(CONCAT, "concat", "ee", RTX_OBJ)
391 /* (CONCATN [a1 a2 ... an]) represents the virtual concatenation of
392 all An to make a value. This is an extension of CONCAT to larger
393 number of components. Like CONCAT, it should not appear in the
394 insn chain. Every element of the CONCATN is the same size. */
395 DEF_RTL_EXPR(CONCATN, "concatn", "E", RTX_OBJ)
397 /* A memory location; operand is the address. The second operand is the
398 alias set to which this MEM belongs. We use `0' instead of `w' for this
399 field so that the field need not be specified in machine descriptions. */
400 DEF_RTL_EXPR(MEM, "mem", "e0", RTX_OBJ)
402 /* Reference to an assembler label in the code for this function.
403 The operand is a CODE_LABEL found in the insn chain. */
404 DEF_RTL_EXPR(LABEL_REF, "label_ref", "u", RTX_CONST_OBJ)
406 /* Reference to a named label:
407 Operand 0: label name
408 Operand 1: flags (see SYMBOL_FLAG_* in rtl.h)
409 Operand 2: tree from which this symbol is derived, or null.
410 This is either a DECL node, or some kind of constant. */
411 DEF_RTL_EXPR(SYMBOL_REF, "symbol_ref", "s00", RTX_CONST_OBJ)
413 /* The condition code register is represented, in our imagination,
414 as a register holding a value that can be compared to zero.
415 In fact, the machine has already compared them and recorded the
416 results; but instructions that look at the condition code
417 pretend to be looking at the entire value and comparing it. */
418 DEF_RTL_EXPR(CC0, "cc0", "", RTX_OBJ)
420 /* ----------------------------------------------------------------------
421 Expressions for operators in an rtl pattern
422 ---------------------------------------------------------------------- */
424 /* if_then_else. This is used in representing ordinary
425 conditional jump instructions.
430 DEF_RTL_EXPR(IF_THEN_ELSE, "if_then_else", "eee", RTX_TERNARY)
432 /* Comparison, produces a condition code result. */
433 DEF_RTL_EXPR(COMPARE, "compare", "ee", RTX_BIN_ARITH)
436 DEF_RTL_EXPR(PLUS, "plus", "ee", RTX_COMM_ARITH)
438 /* Operand 0 minus operand 1. */
439 DEF_RTL_EXPR(MINUS, "minus", "ee", RTX_BIN_ARITH)
441 /* Minus operand 0. */
442 DEF_RTL_EXPR(NEG, "neg", "e", RTX_UNARY)
444 DEF_RTL_EXPR(MULT, "mult", "ee", RTX_COMM_ARITH)
446 /* Operand 0 divided by operand 1. */
447 DEF_RTL_EXPR(DIV, "div", "ee", RTX_BIN_ARITH)
448 /* Remainder of operand 0 divided by operand 1. */
449 DEF_RTL_EXPR(MOD, "mod", "ee", RTX_BIN_ARITH)
451 /* Unsigned divide and remainder. */
452 DEF_RTL_EXPR(UDIV, "udiv", "ee", RTX_BIN_ARITH)
453 DEF_RTL_EXPR(UMOD, "umod", "ee", RTX_BIN_ARITH)
455 /* Bitwise operations. */
456 DEF_RTL_EXPR(AND, "and", "ee", RTX_COMM_ARITH)
457 DEF_RTL_EXPR(IOR, "ior", "ee", RTX_COMM_ARITH)
458 DEF_RTL_EXPR(XOR, "xor", "ee", RTX_COMM_ARITH)
459 DEF_RTL_EXPR(NOT, "not", "e", RTX_UNARY)
462 0: value to be shifted.
463 1: number of bits. */
464 DEF_RTL_EXPR(ASHIFT, "ashift", "ee", RTX_BIN_ARITH) /* shift left */
465 DEF_RTL_EXPR(ROTATE, "rotate", "ee", RTX_BIN_ARITH) /* rotate left */
466 DEF_RTL_EXPR(ASHIFTRT, "ashiftrt", "ee", RTX_BIN_ARITH) /* arithmetic shift right */
467 DEF_RTL_EXPR(LSHIFTRT, "lshiftrt", "ee", RTX_BIN_ARITH) /* logical shift right */
468 DEF_RTL_EXPR(ROTATERT, "rotatert", "ee", RTX_BIN_ARITH) /* rotate right */
470 /* Minimum and maximum values of two operands. We need both signed and
471 unsigned forms. (We cannot use MIN for SMIN because it conflicts
472 with a macro of the same name.) The signed variants should be used
473 with floating point. Further, if both operands are zeros, or if either
474 operand is NaN, then it is unspecified which of the two operands is
475 returned as the result. */
477 DEF_RTL_EXPR(SMIN, "smin", "ee", RTX_COMM_ARITH)
478 DEF_RTL_EXPR(SMAX, "smax", "ee", RTX_COMM_ARITH)
479 DEF_RTL_EXPR(UMIN, "umin", "ee", RTX_COMM_ARITH)
480 DEF_RTL_EXPR(UMAX, "umax", "ee", RTX_COMM_ARITH)
482 /* These unary operations are used to represent incrementation
483 and decrementation as they occur in memory addresses.
484 The amount of increment or decrement are not represented
485 because they can be understood from the machine-mode of the
486 containing MEM. These operations exist in only two cases:
487 1. pushes onto the stack.
488 2. created automatically by the life_analysis pass in flow.c. */
489 DEF_RTL_EXPR(PRE_DEC, "pre_dec", "e", RTX_AUTOINC)
490 DEF_RTL_EXPR(PRE_INC, "pre_inc", "e", RTX_AUTOINC)
491 DEF_RTL_EXPR(POST_DEC, "post_dec", "e", RTX_AUTOINC)
492 DEF_RTL_EXPR(POST_INC, "post_inc", "e", RTX_AUTOINC)
494 /* These binary operations are used to represent generic address
495 side-effects in memory addresses, except for simple incrementation
496 or decrementation which use the above operations. They are
497 created automatically by the life_analysis pass in flow.c.
498 The first operand is a REG which is used as the address.
499 The second operand is an expression that is assigned to the
500 register, either before (PRE_MODIFY) or after (POST_MODIFY)
501 evaluating the address.
502 Currently, the compiler can only handle second operands of the
503 form (plus (reg) (reg)) and (plus (reg) (const_int)), where
504 the first operand of the PLUS has to be the same register as
505 the first operand of the *_MODIFY. */
506 DEF_RTL_EXPR(PRE_MODIFY, "pre_modify", "ee", RTX_AUTOINC)
507 DEF_RTL_EXPR(POST_MODIFY, "post_modify", "ee", RTX_AUTOINC)
509 /* Comparison operations. The ordered comparisons exist in two
510 flavors, signed and unsigned. */
511 DEF_RTL_EXPR(NE, "ne", "ee", RTX_COMM_COMPARE)
512 DEF_RTL_EXPR(EQ, "eq", "ee", RTX_COMM_COMPARE)
513 DEF_RTL_EXPR(GE, "ge", "ee", RTX_COMPARE)
514 DEF_RTL_EXPR(GT, "gt", "ee", RTX_COMPARE)
515 DEF_RTL_EXPR(LE, "le", "ee", RTX_COMPARE)
516 DEF_RTL_EXPR(LT, "lt", "ee", RTX_COMPARE)
517 DEF_RTL_EXPR(GEU, "geu", "ee", RTX_COMPARE)
518 DEF_RTL_EXPR(GTU, "gtu", "ee", RTX_COMPARE)
519 DEF_RTL_EXPR(LEU, "leu", "ee", RTX_COMPARE)
520 DEF_RTL_EXPR(LTU, "ltu", "ee", RTX_COMPARE)
522 /* Additional floating point unordered comparison flavors. */
523 DEF_RTL_EXPR(UNORDERED, "unordered", "ee", RTX_COMM_COMPARE)
524 DEF_RTL_EXPR(ORDERED, "ordered", "ee", RTX_COMM_COMPARE)
526 /* These are equivalent to unordered or ... */
527 DEF_RTL_EXPR(UNEQ, "uneq", "ee", RTX_COMM_COMPARE)
528 DEF_RTL_EXPR(UNGE, "unge", "ee", RTX_COMPARE)
529 DEF_RTL_EXPR(UNGT, "ungt", "ee", RTX_COMPARE)
530 DEF_RTL_EXPR(UNLE, "unle", "ee", RTX_COMPARE)
531 DEF_RTL_EXPR(UNLT, "unlt", "ee", RTX_COMPARE)
533 /* This is an ordered NE, ie !UNEQ, ie false for NaN. */
534 DEF_RTL_EXPR(LTGT, "ltgt", "ee", RTX_COMM_COMPARE)
536 /* Represents the result of sign-extending the sole operand.
537 The machine modes of the operand and of the SIGN_EXTEND expression
538 determine how much sign-extension is going on. */
539 DEF_RTL_EXPR(SIGN_EXTEND, "sign_extend", "e", RTX_UNARY)
541 /* Similar for zero-extension (such as unsigned short to int). */
542 DEF_RTL_EXPR(ZERO_EXTEND, "zero_extend", "e", RTX_UNARY)
544 /* Similar but here the operand has a wider mode. */
545 DEF_RTL_EXPR(TRUNCATE, "truncate", "e", RTX_UNARY)
547 /* Similar for extending floating-point values (such as SFmode to DFmode). */
548 DEF_RTL_EXPR(FLOAT_EXTEND, "float_extend", "e", RTX_UNARY)
549 DEF_RTL_EXPR(FLOAT_TRUNCATE, "float_truncate", "e", RTX_UNARY)
551 /* Conversion of fixed point operand to floating point value. */
552 DEF_RTL_EXPR(FLOAT, "float", "e", RTX_UNARY)
554 /* With fixed-point machine mode:
555 Conversion of floating point operand to fixed point value.
556 Value is defined only when the operand's value is an integer.
557 With floating-point machine mode (and operand with same mode):
558 Operand is rounded toward zero to produce an integer value
559 represented in floating point. */
560 DEF_RTL_EXPR(FIX, "fix", "e", RTX_UNARY)
562 /* Conversion of unsigned fixed point operand to floating point value. */
563 DEF_RTL_EXPR(UNSIGNED_FLOAT, "unsigned_float", "e", RTX_UNARY)
565 /* With fixed-point machine mode:
566 Conversion of floating point operand to *unsigned* fixed point value.
567 Value is defined only when the operand's value is an integer. */
568 DEF_RTL_EXPR(UNSIGNED_FIX, "unsigned_fix", "e", RTX_UNARY)
571 DEF_RTL_EXPR(ABS, "abs", "e", RTX_UNARY)
574 DEF_RTL_EXPR(SQRT, "sqrt", "e", RTX_UNARY)
577 DEF_RTL_EXPR(BSWAP, "bswap", "e", RTX_UNARY)
579 /* Find first bit that is set.
580 Value is 1 + number of trailing zeros in the arg.,
582 DEF_RTL_EXPR(FFS, "ffs", "e", RTX_UNARY)
584 /* Count leading zeros. */
585 DEF_RTL_EXPR(CLZ, "clz", "e", RTX_UNARY)
587 /* Count trailing zeros. */
588 DEF_RTL_EXPR(CTZ, "ctz", "e", RTX_UNARY)
590 /* Population count (number of 1 bits). */
591 DEF_RTL_EXPR(POPCOUNT, "popcount", "e", RTX_UNARY)
593 /* Population parity (number of 1 bits modulo 2). */
594 DEF_RTL_EXPR(PARITY, "parity", "e", RTX_UNARY)
596 /* Reference to a signed bit-field of specified size and position.
597 Operand 0 is the memory unit (usually SImode or QImode) which
598 contains the field's first bit. Operand 1 is the width, in bits.
599 Operand 2 is the number of bits in the memory unit before the
600 first bit of this field.
601 If BITS_BIG_ENDIAN is defined, the first bit is the msb and
602 operand 2 counts from the msb of the memory unit.
603 Otherwise, the first bit is the lsb and operand 2 counts from
604 the lsb of the memory unit.
605 This kind of expression can not appear as an lvalue in RTL. */
606 DEF_RTL_EXPR(SIGN_EXTRACT, "sign_extract", "eee", RTX_BITFIELD_OPS)
608 /* Similar for unsigned bit-field.
609 But note! This kind of expression _can_ appear as an lvalue. */
610 DEF_RTL_EXPR(ZERO_EXTRACT, "zero_extract", "eee", RTX_BITFIELD_OPS)
612 /* For RISC machines. These save memory when splitting insns. */
614 /* HIGH are the high-order bits of a constant expression. */
615 DEF_RTL_EXPR(HIGH, "high", "e", RTX_CONST_OBJ)
617 /* LO_SUM is the sum of a register and the low-order bits
618 of a constant expression. */
619 DEF_RTL_EXPR(LO_SUM, "lo_sum", "ee", RTX_OBJ)
621 /* Describes a merge operation between two vector values.
622 Operands 0 and 1 are the vectors to be merged, operand 2 is a bitmask
623 that specifies where the parts of the result are taken from. Set bits
624 indicate operand 0, clear bits indicate operand 1. The parts are defined
625 by the mode of the vectors. */
626 DEF_RTL_EXPR(VEC_MERGE, "vec_merge", "eee", RTX_TERNARY)
628 /* Describes an operation that selects parts of a vector.
629 Operands 0 is the source vector, operand 1 is a PARALLEL that contains
630 a CONST_INT for each of the subparts of the result vector, giving the
631 number of the source subpart that should be stored into it. */
632 DEF_RTL_EXPR(VEC_SELECT, "vec_select", "ee", RTX_BIN_ARITH)
634 /* Describes a vector concat operation. Operands 0 and 1 are the source
635 vectors, the result is a vector that is as long as operands 0 and 1
636 combined and is the concatenation of the two source vectors. */
637 DEF_RTL_EXPR(VEC_CONCAT, "vec_concat", "ee", RTX_BIN_ARITH)
639 /* Describes an operation that converts a small vector into a larger one by
640 duplicating the input values. The output vector mode must have the same
641 submodes as the input vector mode, and the number of output parts must be
642 an integer multiple of the number of input parts. */
643 DEF_RTL_EXPR(VEC_DUPLICATE, "vec_duplicate", "e", RTX_UNARY)
645 /* Addition with signed saturation */
646 DEF_RTL_EXPR(SS_PLUS, "ss_plus", "ee", RTX_COMM_ARITH)
648 /* Addition with unsigned saturation */
649 DEF_RTL_EXPR(US_PLUS, "us_plus", "ee", RTX_COMM_ARITH)
651 /* Operand 0 minus operand 1, with signed saturation. */
652 DEF_RTL_EXPR(SS_MINUS, "ss_minus", "ee", RTX_BIN_ARITH)
654 /* Negation with signed saturation. */
655 DEF_RTL_EXPR(SS_NEG, "ss_neg", "e", RTX_UNARY)
657 /* Shift left with signed saturation. */
658 DEF_RTL_EXPR(SS_ASHIFT, "ss_ashift", "ee", RTX_BIN_ARITH)
660 /* Operand 0 minus operand 1, with unsigned saturation. */
661 DEF_RTL_EXPR(US_MINUS, "us_minus", "ee", RTX_BIN_ARITH)
663 /* Signed saturating truncate. */
664 DEF_RTL_EXPR(SS_TRUNCATE, "ss_truncate", "e", RTX_UNARY)
666 /* Unsigned saturating truncate. */
667 DEF_RTL_EXPR(US_TRUNCATE, "us_truncate", "e", RTX_UNARY)
669 /* Information about the variable and its location. */
670 DEF_RTL_EXPR(VAR_LOCATION, "var_location", "te", RTX_EXTRA)
672 /* All expressions from this point forward appear only in machine
674 #ifdef GENERATOR_FILE
676 /* Include a secondary machine-description file at this point. */
677 DEF_RTL_EXPR(INCLUDE, "include", "s", RTX_EXTRA)
679 /* Pattern-matching operators: */
681 /* Use the function named by the second arg (the string)
682 as a predicate; if matched, store the structure that was matched
683 in the operand table at index specified by the first arg (the integer).
684 If the second arg is the null string, the structure is just stored.
686 A third string argument indicates to the register allocator restrictions
687 on where the operand can be allocated.
689 If the target needs no restriction on any instruction this field should
692 The string is prepended by:
693 '=' to indicate the operand is only written to.
694 '+' to indicate the operand is both read and written to.
696 Each character in the string represents an allocable class for an operand.
697 'g' indicates the operand can be any valid class.
698 'i' indicates the operand can be immediate (in the instruction) data.
699 'r' indicates the operand can be in a register.
700 'm' indicates the operand can be in memory.
701 'o' a subset of the 'm' class. Those memory addressing modes that
702 can be offset at compile time (have a constant added to them).
704 Other characters indicate target dependent operand classes and
705 are described in each target's machine description.
707 For instructions with more than one operand, sets of classes can be
708 separated by a comma to indicate the appropriate multi-operand constraints.
709 There must be a 1 to 1 correspondence between these sets of classes in
710 all operands for an instruction.
712 DEF_RTL_EXPR(MATCH_OPERAND, "match_operand", "iss", RTX_MATCH)
714 /* Match a SCRATCH or a register. When used to generate rtl, a
715 SCRATCH is generated. As for MATCH_OPERAND, the mode specifies
716 the desired mode and the first argument is the operand number.
717 The second argument is the constraint. */
718 DEF_RTL_EXPR(MATCH_SCRATCH, "match_scratch", "is", RTX_MATCH)
720 /* Apply a predicate, AND match recursively the operands of the rtx.
721 Operand 0 is the operand-number, as in match_operand.
722 Operand 1 is a predicate to apply (as a string, a function name).
723 Operand 2 is a vector of expressions, each of which must match
724 one subexpression of the rtx this construct is matching. */
725 DEF_RTL_EXPR(MATCH_OPERATOR, "match_operator", "isE", RTX_MATCH)
727 /* Match a PARALLEL of arbitrary length. The predicate is applied
728 to the PARALLEL and the initial expressions in the PARALLEL are matched.
729 Operand 0 is the operand-number, as in match_operand.
730 Operand 1 is a predicate to apply to the PARALLEL.
731 Operand 2 is a vector of expressions, each of which must match the
732 corresponding element in the PARALLEL. */
733 DEF_RTL_EXPR(MATCH_PARALLEL, "match_parallel", "isE", RTX_MATCH)
735 /* Match only something equal to what is stored in the operand table
736 at the index specified by the argument. Use with MATCH_OPERAND. */
737 DEF_RTL_EXPR(MATCH_DUP, "match_dup", "i", RTX_MATCH)
739 /* Match only something equal to what is stored in the operand table
740 at the index specified by the argument. Use with MATCH_OPERATOR. */
741 DEF_RTL_EXPR(MATCH_OP_DUP, "match_op_dup", "iE", RTX_MATCH)
743 /* Match only something equal to what is stored in the operand table
744 at the index specified by the argument. Use with MATCH_PARALLEL. */
745 DEF_RTL_EXPR(MATCH_PAR_DUP, "match_par_dup", "iE", RTX_MATCH)
747 /* Appears only in define_predicate/define_special_predicate
748 expressions. Evaluates true only if the operand has an RTX code
749 from the set given by the argument (a comma-separated list). If the
750 second argument is present and nonempty, it is a sequence of digits
751 and/or letters which indicates the subexpression to test, using the
752 same syntax as genextract/genrecog's location strings: 0-9 for
753 XEXP (op, n), a-z for XVECEXP (op, 0, n); each character applies to
754 the result of the one before it. */
755 DEF_RTL_EXPR(MATCH_CODE, "match_code", "ss", RTX_MATCH)
757 /* Appears only in define_predicate/define_special_predicate
758 expressions. The argument is a C expression to be injected at this
759 point in the predicate formula. */
760 DEF_RTL_EXPR(MATCH_TEST, "match_test", "s", RTX_MATCH)
762 /* Insn (and related) definitions. */
764 /* Definition of the pattern for one kind of instruction.
766 0: names this instruction.
767 If the name is the null string, the instruction is in the
768 machine description just to be recognized, and will never be emitted by
769 the tree to rtl expander.
771 2: is a string which is a C expression
772 giving an additional condition for recognizing this pattern.
773 A null string means no extra condition.
774 3: is the action to execute if this pattern is matched.
775 If this assembler code template starts with a * then it is a fragment of
776 C code to run to decide on a template to use. Otherwise, it is the
778 4: optionally, a vector of attributes for this insn.
780 DEF_RTL_EXPR(DEFINE_INSN, "define_insn", "sEsTV", RTX_EXTRA)
782 /* Definition of a peephole optimization.
783 1st operand: vector of insn patterns to match
784 2nd operand: C expression that must be true
785 3rd operand: template or C code to produce assembler output.
786 4: optionally, a vector of attributes for this insn.
788 This form is deprecated; use define_peephole2 instead. */
789 DEF_RTL_EXPR(DEFINE_PEEPHOLE, "define_peephole", "EsTV", RTX_EXTRA)
791 /* Definition of a split operation.
792 1st operand: insn pattern to match
793 2nd operand: C expression that must be true
794 3rd operand: vector of insn patterns to place into a SEQUENCE
795 4th operand: optionally, some C code to execute before generating the
796 insns. This might, for example, create some RTX's and store them in
797 elements of `recog_data.operand' for use by the vector of
799 (`operands' is an alias here for `recog_data.operand'). */
800 DEF_RTL_EXPR(DEFINE_SPLIT, "define_split", "EsES", RTX_EXTRA)
802 /* Definition of an insn and associated split.
803 This is the concatenation, with a few modifications, of a define_insn
804 and a define_split which share the same pattern.
806 0: names this instruction.
807 If the name is the null string, the instruction is in the
808 machine description just to be recognized, and will never be emitted by
809 the tree to rtl expander.
811 2: is a string which is a C expression
812 giving an additional condition for recognizing this pattern.
813 A null string means no extra condition.
814 3: is the action to execute if this pattern is matched.
815 If this assembler code template starts with a * then it is a fragment of
816 C code to run to decide on a template to use. Otherwise, it is the
818 4: C expression that must be true for split. This may start with "&&"
819 in which case the split condition is the logical and of the insn
820 condition and what follows the "&&" of this operand.
821 5: vector of insn patterns to place into a SEQUENCE
822 6: optionally, some C code to execute before generating the
823 insns. This might, for example, create some RTX's and store them in
824 elements of `recog_data.operand' for use by the vector of
826 (`operands' is an alias here for `recog_data.operand').
827 7: optionally, a vector of attributes for this insn. */
828 DEF_RTL_EXPR(DEFINE_INSN_AND_SPLIT, "define_insn_and_split", "sEsTsESV", RTX_EXTRA)
830 /* Definition of an RTL peephole operation.
831 Follows the same arguments as define_split. */
832 DEF_RTL_EXPR(DEFINE_PEEPHOLE2, "define_peephole2", "EsES", RTX_EXTRA)
834 /* Define how to generate multiple insns for a standard insn name.
835 1st operand: the insn name.
836 2nd operand: vector of insn-patterns.
837 Use match_operand to substitute an element of `recog_data.operand'.
838 3rd operand: C expression that must be true for this to be available.
839 This may not test any operands.
840 4th operand: Extra C code to execute before generating the insns.
841 This might, for example, create some RTX's and store them in
842 elements of `recog_data.operand' for use by the vector of
844 (`operands' is an alias here for `recog_data.operand'). */
845 DEF_RTL_EXPR(DEFINE_EXPAND, "define_expand", "sEss", RTX_EXTRA)
847 /* Define a requirement for delay slots.
848 1st operand: Condition involving insn attributes that, if true,
849 indicates that the insn requires the number of delay slots
851 2nd operand: Vector whose length is the three times the number of delay
853 Each entry gives three conditions, each involving attributes.
854 The first must be true for an insn to occupy that delay slot
855 location. The second is true for all insns that can be
856 annulled if the branch is true and the third is true for all
857 insns that can be annulled if the branch is false.
859 Multiple DEFINE_DELAYs may be present. They indicate differing
860 requirements for delay slots. */
861 DEF_RTL_EXPR(DEFINE_DELAY, "define_delay", "eE", RTX_EXTRA)
863 /* Define attribute computation for `asm' instructions. */
864 DEF_RTL_EXPR(DEFINE_ASM_ATTRIBUTES, "define_asm_attributes", "V", RTX_EXTRA)
866 /* Definition of a conditional execution meta operation. Automatically
867 generates new instances of DEFINE_INSN, selected by having attribute
868 "predicable" true. The new pattern will contain a COND_EXEC and the
869 predicate at top-level.
872 0: The predicate pattern. The top-level form should match a
873 relational operator. Operands should have only one alternative.
874 1: A C expression giving an additional condition for recognizing
875 the generated pattern.
876 2: A template or C code to produce assembler output. */
877 DEF_RTL_EXPR(DEFINE_COND_EXEC, "define_cond_exec", "Ess", RTX_EXTRA)
879 /* Definition of an operand predicate. The difference between
880 DEFINE_PREDICATE and DEFINE_SPECIAL_PREDICATE is that genrecog will
881 not warn about a match_operand with no mode if it has a predicate
882 defined with DEFINE_SPECIAL_PREDICATE.
885 0: The name of the predicate.
886 1: A boolean expression which computes whether or not the predicate
887 matches. This expression can use IOR, AND, NOT, MATCH_OPERAND,
888 MATCH_CODE, and MATCH_TEST. It must be specific enough that genrecog
889 can calculate the set of RTX codes that can possibly match.
890 2: A C function body which must return true for the predicate to match.
891 Optional. Use this when the test is too complicated to fit into a
892 match_test expression. */
893 DEF_RTL_EXPR(DEFINE_PREDICATE, "define_predicate", "ses", RTX_EXTRA)
894 DEF_RTL_EXPR(DEFINE_SPECIAL_PREDICATE, "define_special_predicate", "ses", RTX_EXTRA)
896 /* Definition of a register operand constraint. This simply maps the
897 constraint string to a register class.
900 0: The name of the constraint (often, but not always, a single letter).
901 1: A C expression which evaluates to the appropriate register class for
902 this constraint. If this is not just a constant, it should look only
903 at -m switches and the like.
904 2: A docstring for this constraint, in Texinfo syntax; not currently
905 used, in future will be incorporated into the manual's list of
906 machine-specific operand constraints. */
907 DEF_RTL_EXPR(DEFINE_REGISTER_CONSTRAINT, "define_register_constraint", "sss", RTX_EXTRA)
909 /* Definition of a non-register operand constraint. These look at the
910 operand and decide whether it fits the constraint.
912 DEFINE_CONSTRAINT gets no special treatment if it fails to match.
913 It is appropriate for constant-only constraints, and most others.
915 DEFINE_MEMORY_CONSTRAINT tells reload that this constraint can be made
916 to match, if it doesn't already, by converting the operand to the form
917 (mem (reg X)) where X is a base register. It is suitable for constraints
918 that describe a subset of all memory references.
920 DEFINE_ADDRESS_CONSTRAINT tells reload that this constraint can be made
921 to match, if it doesn't already, by converting the operand to the form
922 (reg X) where X is a base register. It is suitable for constraints that
923 describe a subset of all address references.
925 When in doubt, use plain DEFINE_CONSTRAINT.
928 0: The name of the constraint (often, but not always, a single letter).
929 1: A docstring for this constraint, in Texinfo syntax; not currently
930 used, in future will be incorporated into the manual's list of
931 machine-specific operand constraints.
932 2: A boolean expression which computes whether or not the constraint
933 matches. It should follow the same rules as a define_predicate
934 expression, including the bit about specifying the set of RTX codes
935 that could possibly match. MATCH_TEST subexpressions may make use of
937 `op' - the RTL object defining the operand.
938 `mode' - the mode of `op'.
939 `ival' - INTVAL(op), if op is a CONST_INT.
940 `hval' - CONST_DOUBLE_HIGH(op), if op is an integer CONST_DOUBLE.
941 `lval' - CONST_DOUBLE_LOW(op), if op is an integer CONST_DOUBLE.
942 `rval' - CONST_DOUBLE_REAL_VALUE(op), if op is a floating-point
944 Do not use ival/hval/lval/rval if op is not the appropriate kind of
946 DEF_RTL_EXPR(DEFINE_CONSTRAINT, "define_constraint", "sse", RTX_EXTRA)
947 DEF_RTL_EXPR(DEFINE_MEMORY_CONSTRAINT, "define_memory_constraint", "sse", RTX_EXTRA)
948 DEF_RTL_EXPR(DEFINE_ADDRESS_CONSTRAINT, "define_address_constraint", "sse", RTX_EXTRA)
951 /* Constructions for CPU pipeline description described by NDFAs. */
953 /* (define_cpu_unit string [string]) describes cpu functional
954 units (separated by comma).
956 1st operand: Names of cpu functional units.
957 2nd operand: Name of automaton (see comments for DEFINE_AUTOMATON).
959 All define_reservations, define_cpu_units, and
960 define_query_cpu_units should have unique names which may not be
962 DEF_RTL_EXPR(DEFINE_CPU_UNIT, "define_cpu_unit", "sS", RTX_EXTRA)
964 /* (define_query_cpu_unit string [string]) describes cpu functional
965 units analogously to define_cpu_unit. The reservation of such
966 units can be queried for automaton state. */
967 DEF_RTL_EXPR(DEFINE_QUERY_CPU_UNIT, "define_query_cpu_unit", "sS", RTX_EXTRA)
969 /* (exclusion_set string string) means that each CPU functional unit
970 in the first string can not be reserved simultaneously with any
971 unit whose name is in the second string and vise versa. CPU units
972 in the string are separated by commas. For example, it is useful
973 for description CPU with fully pipelined floating point functional
974 unit which can execute simultaneously only single floating point
975 insns or only double floating point insns. All CPU functional
976 units in a set should belong to the same automaton. */
977 DEF_RTL_EXPR(EXCLUSION_SET, "exclusion_set", "ss", RTX_EXTRA)
979 /* (presence_set string string) means that each CPU functional unit in
980 the first string can not be reserved unless at least one of pattern
981 of units whose names are in the second string is reserved. This is
982 an asymmetric relation. CPU units or unit patterns in the strings
983 are separated by commas. Pattern is one unit name or unit names
984 separated by white-spaces.
986 For example, it is useful for description that slot1 is reserved
987 after slot0 reservation for a VLIW processor. We could describe it
988 by the following construction
990 (presence_set "slot1" "slot0")
992 Or slot1 is reserved only after slot0 and unit b0 reservation. In
993 this case we could write
995 (presence_set "slot1" "slot0 b0")
997 All CPU functional units in a set should belong to the same
999 DEF_RTL_EXPR(PRESENCE_SET, "presence_set", "ss", RTX_EXTRA)
1001 /* (final_presence_set string string) is analogous to `presence_set'.
1002 The difference between them is when checking is done. When an
1003 instruction is issued in given automaton state reflecting all
1004 current and planned unit reservations, the automaton state is
1005 changed. The first state is a source state, the second one is a
1006 result state. Checking for `presence_set' is done on the source
1007 state reservation, checking for `final_presence_set' is done on the
1008 result reservation. This construction is useful to describe a
1009 reservation which is actually two subsequent reservations. For
1012 (presence_set "slot1" "slot0")
1014 the following insn will be never issued (because slot1 requires
1015 slot0 which is absent in the source state).
1017 (define_reservation "insn_and_nop" "slot0 + slot1")
1019 but it can be issued if we use analogous `final_presence_set'. */
1020 DEF_RTL_EXPR(FINAL_PRESENCE_SET, "final_presence_set", "ss", RTX_EXTRA)
1022 /* (absence_set string string) means that each CPU functional unit in
1023 the first string can be reserved only if each pattern of units
1024 whose names are in the second string is not reserved. This is an
1025 asymmetric relation (actually exclusion set is analogous to this
1026 one but it is symmetric). CPU units or unit patterns in the string
1027 are separated by commas. Pattern is one unit name or unit names
1028 separated by white-spaces.
1030 For example, it is useful for description that slot0 can not be
1031 reserved after slot1 or slot2 reservation for a VLIW processor. We
1032 could describe it by the following construction
1034 (absence_set "slot2" "slot0, slot1")
1036 Or slot2 can not be reserved if slot0 and unit b0 are reserved or
1037 slot1 and unit b1 are reserved . In this case we could write
1039 (absence_set "slot2" "slot0 b0, slot1 b1")
1041 All CPU functional units in a set should to belong the same
1043 DEF_RTL_EXPR(ABSENCE_SET, "absence_set", "ss", RTX_EXTRA)
1045 /* (final_absence_set string string) is analogous to `absence_set' but
1046 checking is done on the result (state) reservation. See comments
1047 for `final_presence_set'. */
1048 DEF_RTL_EXPR(FINAL_ABSENCE_SET, "final_absence_set", "ss", RTX_EXTRA)
1050 /* (define_bypass number out_insn_names in_insn_names) names bypass
1051 with given latency (the first number) from insns given by the first
1052 string (see define_insn_reservation) into insns given by the second
1053 string. Insn names in the strings are separated by commas. The
1054 third operand is optional name of function which is additional
1055 guard for the bypass. The function will get the two insns as
1056 parameters. If the function returns zero the bypass will be
1057 ignored for this case. Additional guard is necessary to recognize
1058 complicated bypasses, e.g. when consumer is load address. */
1059 DEF_RTL_EXPR(DEFINE_BYPASS, "define_bypass", "issS", RTX_EXTRA)
1061 /* (define_automaton string) describes names of automata generated and
1062 used for pipeline hazards recognition. The names are separated by
1063 comma. Actually it is possibly to generate the single automaton
1064 but unfortunately it can be very large. If we use more one
1065 automata, the summary size of the automata usually is less than the
1066 single one. The automaton name is used in define_cpu_unit and
1067 define_query_cpu_unit. All automata should have unique names. */
1068 DEF_RTL_EXPR(DEFINE_AUTOMATON, "define_automaton", "s", RTX_EXTRA)
1070 /* (automata_option string) describes option for generation of
1071 automata. Currently there are the following options:
1073 o "no-minimization" which makes no minimization of automata. This
1074 is only worth to do when we are debugging the description and
1075 need to look more accurately at reservations of states.
1077 o "time" which means printing additional time statistics about
1078 generation of automata.
1080 o "v" which means generation of file describing the result
1081 automata. The file has suffix `.dfa' and can be used for the
1082 description verification and debugging.
1084 o "w" which means generation of warning instead of error for
1085 non-critical errors.
1087 o "ndfa" which makes nondeterministic finite state automata.
1089 o "progress" which means output of a progress bar showing how many
1090 states were generated so far for automaton being processed. */
1091 DEF_RTL_EXPR(AUTOMATA_OPTION, "automata_option", "s", RTX_EXTRA)
1093 /* (define_reservation string string) names reservation (the first
1094 string) of cpu functional units (the 2nd string). Sometimes unit
1095 reservations for different insns contain common parts. In such
1096 case, you can describe common part and use its name (the 1st
1097 parameter) in regular expression in define_insn_reservation. All
1098 define_reservations, define_cpu_units, and define_query_cpu_units
1099 should have unique names which may not be "nothing". */
1100 DEF_RTL_EXPR(DEFINE_RESERVATION, "define_reservation", "ss", RTX_EXTRA)
1102 /* (define_insn_reservation name default_latency condition regexpr)
1103 describes reservation of cpu functional units (the 3nd operand) for
1104 instruction which is selected by the condition (the 2nd parameter).
1105 The first parameter is used for output of debugging information.
1106 The reservations are described by a regular expression according
1107 the following syntax:
1109 regexp = regexp "," oneof
1112 oneof = oneof "|" allof
1115 allof = allof "+" repeat
1118 repeat = element "*" number
1121 element = cpu_function_unit_name
1127 1. "," is used for describing start of the next cycle in
1130 2. "|" is used for describing the reservation described by the
1131 first regular expression *or* the reservation described by the
1132 second regular expression *or* etc.
1134 3. "+" is used for describing the reservation described by the
1135 first regular expression *and* the reservation described by the
1136 second regular expression *and* etc.
1138 4. "*" is used for convenience and simply means sequence in
1139 which the regular expression are repeated NUMBER times with
1140 cycle advancing (see ",").
1142 5. cpu functional unit name which means its reservation.
1144 6. reservation name -- see define_reservation.
1146 7. string "nothing" means no units reservation. */
1148 DEF_RTL_EXPR(DEFINE_INSN_RESERVATION, "define_insn_reservation", "sies", RTX_EXTRA)
1150 /* Expressions used for insn attributes. */
1152 /* Definition of an insn attribute.
1153 1st operand: name of the attribute
1154 2nd operand: comma-separated list of possible attribute values
1155 3rd operand: expression for the default value of the attribute. */
1156 DEF_RTL_EXPR(DEFINE_ATTR, "define_attr", "sse", RTX_EXTRA)
1158 /* Marker for the name of an attribute. */
1159 DEF_RTL_EXPR(ATTR, "attr", "s", RTX_EXTRA)
1161 /* For use in the last (optional) operand of DEFINE_INSN or DEFINE_PEEPHOLE and
1162 in DEFINE_ASM_INSN to specify an attribute to assign to insns matching that
1165 (set_attr "name" "value") is equivalent to
1166 (set (attr "name") (const_string "value")) */
1167 DEF_RTL_EXPR(SET_ATTR, "set_attr", "ss", RTX_EXTRA)
1169 /* In the last operand of DEFINE_INSN and DEFINE_PEEPHOLE, this can be used to
1170 specify that attribute values are to be assigned according to the
1171 alternative matched.
1173 The following three expressions are equivalent:
1175 (set (attr "att") (cond [(eq_attrq "alternative" "1") (const_string "a1")
1176 (eq_attrq "alternative" "2") (const_string "a2")]
1177 (const_string "a3")))
1178 (set_attr_alternative "att" [(const_string "a1") (const_string "a2")
1179 (const_string "a3")])
1180 (set_attr "att" "a1,a2,a3")
1182 DEF_RTL_EXPR(SET_ATTR_ALTERNATIVE, "set_attr_alternative", "sE", RTX_EXTRA)
1184 /* A conditional expression true if the value of the specified attribute of
1185 the current insn equals the specified value. The first operand is the
1186 attribute name and the second is the comparison value. */
1187 DEF_RTL_EXPR(EQ_ATTR, "eq_attr", "ss", RTX_EXTRA)
1189 /* A special case of the above representing a set of alternatives. The first
1190 operand is bitmap of the set, the second one is the default value. */
1191 DEF_RTL_EXPR(EQ_ATTR_ALT, "eq_attr_alt", "ii", RTX_EXTRA)
1193 /* A conditional expression which is true if the specified flag is
1194 true for the insn being scheduled in reorg.
1196 genattr.c defines the following flags which can be tested by
1197 (attr_flag "foo") expressions in eligible_for_delay.
1199 forward, backward, very_likely, likely, very_unlikely, and unlikely. */
1201 DEF_RTL_EXPR (ATTR_FLAG, "attr_flag", "s", RTX_EXTRA)
1203 /* General conditional. The first operand is a vector composed of pairs of
1204 expressions. The first element of each pair is evaluated, in turn.
1205 The value of the conditional is the second expression of the first pair
1206 whose first expression evaluates nonzero. If none of the expressions is
1207 true, the second operand will be used as the value of the conditional. */
1208 DEF_RTL_EXPR(COND, "cond", "Ee", RTX_EXTRA)
1210 #endif /* GENERATOR_FILE */