1 /* This file contains the definitions and documentation for the
2 Register Transfer Expressions (rtx's) that make up the
3 Register Transfer Language (rtl) used in the Back End of the GNU compiler.
4 Copyright (C) 1987-2014 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 3, or (at your option) any later
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
23 /* Expression definitions and descriptions for all targets are in this file.
24 Some will not be used for some targets.
26 The fields in the cpp macro call "DEF_RTL_EXPR()"
27 are used to create declarations in the C source of the compiler.
31 1. The internal name of the rtx used in the C source.
32 It is a tag in the enumeration "enum rtx_code" defined in "rtl.h".
33 By convention these are in UPPER_CASE.
35 2. The name of the rtx in the external ASCII format read by
36 read_rtx(), and printed by print_rtx().
37 These names are stored in rtx_name[].
38 By convention these are the internal (field 1) names in lower_case.
40 3. The print format, and type of each rtx->u.fld[] (field) in this rtx.
41 These formats are stored in rtx_format[].
42 The meaning of the formats is documented in front of this array in rtl.c
44 4. The class of the rtx. These are stored in rtx_class and are accessed
45 via the GET_RTX_CLASS macro. They are defined as follows:
48 an rtx code that can be used to represent a constant object
51 an rtx code that can be used to represent an object (e.g, REG, MEM)
53 an rtx code for a comparison (e.g, LT, GT)
55 an rtx code for a commutative comparison (e.g, EQ, NE, ORDERED)
57 an rtx code for a unary arithmetic expression (e.g, NEG, NOT)
59 an rtx code for a commutative binary operation (e.g,, PLUS, MULT)
61 an rtx code for a non-bitfield three input operation (IF_THEN_ELSE)
63 an rtx code for a non-commutative binary operation (e.g., MINUS, DIV)
65 an rtx code for a bit-field operation (ZERO_EXTRACT, SIGN_EXTRACT)
67 an rtx code for a machine insn (INSN, JUMP_INSN, CALL_INSN) or
68 data that will be output as assembly pseudo-ops (DEBUG_INSN)
70 an rtx code for something that matches in insns (e.g, MATCH_DUP)
72 an rtx code for autoincrement addressing modes (e.g. POST_DEC)
76 All of the expressions that appear only in machine descriptions,
77 not in RTL used by the compiler itself, are at the end of the file. */
79 /* Unknown, or no such operation; the enumeration constant should have
81 DEF_RTL_EXPR(UNKNOWN, "UnKnown", "*", RTX_EXTRA)
83 /* Used in the cselib routines to describe a value. Objects of this
84 kind are only allocated in cselib.c, in an alloc pool instead of in
85 GC memory. The only operand of a VALUE is a cselib_val.
86 var-tracking requires this to have a distinct integral value from
87 DECL codes in trees. */
88 DEF_RTL_EXPR(VALUE, "value", "0", RTX_OBJ)
90 /* The RTL generated for a DEBUG_EXPR_DECL. It links back to the
91 DEBUG_EXPR_DECL in the first operand. */
92 DEF_RTL_EXPR(DEBUG_EXPR, "debug_expr", "0", RTX_OBJ)
94 /* ---------------------------------------------------------------------
95 Expressions used in constructing lists.
96 --------------------------------------------------------------------- */
98 /* A linked list of expressions. */
99 DEF_RTL_EXPR(EXPR_LIST, "expr_list", "ee", RTX_EXTRA)
101 /* A linked list of instructions.
102 The insns are represented in print by their uids. */
103 DEF_RTL_EXPR(INSN_LIST, "insn_list", "ue", RTX_EXTRA)
105 /* A linked list of integers. */
106 DEF_RTL_EXPR(INT_LIST, "int_list", "ie", RTX_EXTRA)
108 /* SEQUENCE is used in late passes of the compiler to group insns for
109 one reason or another.
111 For example, after delay slot filling, branch instructions with filled
112 delay slots are represented as a SEQUENCE of length 1 + n_delay_slots,
113 with the branch instruction in XEXPVEC(seq, 0, 0) and the instructions
114 occupying the delay slots in the remaining XEXPVEC slots.
116 Another place where a SEQUENCE may appear, is in REG_FRAME_RELATED_EXPR
117 notes, to express complex operations that are not obvious from the insn
118 to which the REG_FRAME_RELATED_EXPR note is attached. In this usage of
119 SEQUENCE, the sequence vector slots do not hold real instructions but
120 only pseudo-instructions that can be translated to DWARF CFA expressions.
122 Some back ends also use SEQUENCE to group insns in bundles.
124 Much of the compiler infrastructure is not prepared to handle SEQUENCE
125 objects. Only passes after pass_free_cfg are expected to handle them. */
126 DEF_RTL_EXPR(SEQUENCE, "sequence", "E", RTX_EXTRA)
128 /* Represents a non-global base address. This is only used in alias.c. */
129 DEF_RTL_EXPR(ADDRESS, "address", "i", RTX_EXTRA)
131 /* ----------------------------------------------------------------------
132 Expression types used for things in the instruction chain.
134 All formats must start with "iuu" to handle the chain.
135 Each insn expression holds an rtl instruction and its semantics
136 during back-end processing.
137 See macros's in "rtl.h" for the meaning of each rtx->u.fld[].
139 ---------------------------------------------------------------------- */
141 /* An annotation for variable assignment tracking. */
142 DEF_RTL_EXPR(DEBUG_INSN, "debug_insn", "uuBeiie", RTX_INSN)
144 /* An instruction that cannot jump. */
145 DEF_RTL_EXPR(INSN, "insn", "uuBeiie", RTX_INSN)
147 /* An instruction that can possibly jump.
148 Fields ( rtx->u.fld[] ) have exact same meaning as INSN's. */
149 DEF_RTL_EXPR(JUMP_INSN, "jump_insn", "uuBeiie0", RTX_INSN)
151 /* An instruction that can possibly call a subroutine
152 but which will not change which instruction comes next
153 in the current function.
154 Field ( rtx->u.fld[8] ) is CALL_INSN_FUNCTION_USAGE.
155 All other fields ( rtx->u.fld[] ) have exact same meaning as INSN's. */
156 DEF_RTL_EXPR(CALL_INSN, "call_insn", "uuBeiiee", RTX_INSN)
158 /* Placeholder for tablejump JUMP_INSNs. The pattern of this kind
159 of rtx is always either an ADDR_VEC or an ADDR_DIFF_VEC. These
160 placeholders do not appear as real instructions inside a basic
161 block, but are considered active_insn_p instructions for historical
162 reasons, when jump table data was represented with JUMP_INSNs. */
163 DEF_RTL_EXPR(JUMP_TABLE_DATA, "jump_table_data", "uuBe0000", RTX_INSN)
165 /* A marker that indicates that control will not flow through. */
166 DEF_RTL_EXPR(BARRIER, "barrier", "uu00000", RTX_EXTRA)
168 /* Holds a label that is followed by instructions.
170 3: is used in jump.c for the use-count of the label.
171 4: is used in the sh backend.
172 5: is a number that is unique in the entire compilation.
173 6: is the user-given name of the label, if any. */
174 DEF_RTL_EXPR(CODE_LABEL, "code_label", "uuB00is", RTX_EXTRA)
176 /* Say where in the code a source line starts, for symbol table's sake.
178 3: note-specific data
180 5: unique number if insn_note == note_insn_deleted_label. */
181 DEF_RTL_EXPR(NOTE, "note", "uuB0ni", RTX_EXTRA)
183 /* ----------------------------------------------------------------------
184 Top level constituents of INSN, JUMP_INSN and CALL_INSN.
185 ---------------------------------------------------------------------- */
187 /* Conditionally execute code.
188 Operand 0 is the condition that if true, the code is executed.
189 Operand 1 is the code to be executed (typically a SET).
191 Semantics are that there are no side effects if the condition
192 is false. This pattern is created automatically by the if_convert
193 pass run after reload or by target-specific splitters. */
194 DEF_RTL_EXPR(COND_EXEC, "cond_exec", "ee", RTX_EXTRA)
196 /* Several operations to be done in parallel (perhaps under COND_EXEC). */
197 DEF_RTL_EXPR(PARALLEL, "parallel", "E", RTX_EXTRA)
199 /* A string that is passed through to the assembler as input.
200 One can obviously pass comments through by using the
201 assembler comment syntax.
202 These occur in an insn all by themselves as the PATTERN.
203 They also appear inside an ASM_OPERANDS
204 as a convenient way to hold a string. */
205 DEF_RTL_EXPR(ASM_INPUT, "asm_input", "si", RTX_EXTRA)
207 /* An assembler instruction with operands.
208 1st operand is the instruction template.
209 2nd operand is the constraint for the output.
210 3rd operand is the number of the output this expression refers to.
211 When an insn stores more than one value, a separate ASM_OPERANDS
212 is made for each output; this integer distinguishes them.
213 4th is a vector of values of input operands.
214 5th is a vector of modes and constraints for the input operands.
215 Each element is an ASM_INPUT containing a constraint string
216 and whose mode indicates the mode of the input operand.
217 6th is a vector of labels that may be branched to by the asm.
218 7th is the source line number. */
219 DEF_RTL_EXPR(ASM_OPERANDS, "asm_operands", "ssiEEEi", RTX_EXTRA)
221 /* A machine-specific operation.
222 1st operand is a vector of operands being used by the operation so that
223 any needed reloads can be done.
224 2nd operand is a unique value saying which of a number of machine-specific
225 operations is to be performed.
226 (Note that the vector must be the first operand because of the way that
227 genrecog.c record positions within an insn.)
229 UNSPEC can occur all by itself in a PATTERN, as a component of a PARALLEL,
230 or inside an expression.
231 UNSPEC by itself or as a component of a PARALLEL
232 is currently considered not deletable.
234 FIXME: Replace all uses of UNSPEC that appears by itself or as a component
235 of a PARALLEL with USE.
237 DEF_RTL_EXPR(UNSPEC, "unspec", "Ei", RTX_EXTRA)
239 /* Similar, but a volatile operation and one which may trap. */
240 DEF_RTL_EXPR(UNSPEC_VOLATILE, "unspec_volatile", "Ei", RTX_EXTRA)
242 /* ----------------------------------------------------------------------
243 Table jump addresses.
244 ---------------------------------------------------------------------- */
246 /* Vector of addresses, stored as full words.
247 Each element is a LABEL_REF to a CODE_LABEL whose address we want. */
248 DEF_RTL_EXPR(ADDR_VEC, "addr_vec", "E", RTX_EXTRA)
250 /* Vector of address differences X0 - BASE, X1 - BASE, ...
251 First operand is BASE; the vector contains the X's.
252 The machine mode of this rtx says how much space to leave
253 for each difference and is adjusted by branch shortening if
254 CASE_VECTOR_SHORTEN_MODE is defined.
255 The third and fourth operands store the target labels with the
256 minimum and maximum addresses respectively.
257 The fifth operand stores flags for use by branch shortening.
258 Set at the start of shorten_branches:
259 min_align: the minimum alignment for any of the target labels.
260 base_after_vec: true iff BASE is after the ADDR_DIFF_VEC.
261 min_after_vec: true iff minimum addr target label is after the ADDR_DIFF_VEC.
262 max_after_vec: true iff maximum addr target label is after the ADDR_DIFF_VEC.
263 min_after_base: true iff minimum address target label is after BASE.
264 max_after_base: true iff maximum address target label is after BASE.
265 Set by the actual branch shortening process:
266 offset_unsigned: true iff offsets have to be treated as unsigned.
267 scale: scaling that is necessary to make offsets fit into the mode.
269 The third, fourth and fifth operands are only valid when
270 CASE_VECTOR_SHORTEN_MODE is defined, and only in an optimizing
272 DEF_RTL_EXPR(ADDR_DIFF_VEC, "addr_diff_vec", "eEee0", RTX_EXTRA)
274 /* Memory prefetch, with attributes supported on some targets.
275 Operand 1 is the address of the memory to fetch.
276 Operand 2 is 1 for a write access, 0 otherwise.
277 Operand 3 is the level of temporal locality; 0 means there is no
278 temporal locality and 1, 2, and 3 are for increasing levels of temporal
281 The attributes specified by operands 2 and 3 are ignored for targets
282 whose prefetch instructions do not support them. */
283 DEF_RTL_EXPR(PREFETCH, "prefetch", "eee", RTX_EXTRA)
285 /* ----------------------------------------------------------------------
286 At the top level of an instruction (perhaps under PARALLEL).
287 ---------------------------------------------------------------------- */
290 Operand 1 is the location (REG, MEM, PC, CC0 or whatever) assigned to.
291 Operand 2 is the value stored there.
292 ALL assignment must use SET.
293 Instructions that do multiple assignments must use multiple SET,
295 DEF_RTL_EXPR(SET, "set", "ee", RTX_EXTRA)
297 /* Indicate something is used in a way that we don't want to explain.
298 For example, subroutine calls will use the register
299 in which the static chain is passed.
301 USE can not appear as an operand of other rtx except for PARALLEL.
302 USE is not deletable, as it indicates that the operand
303 is used in some unknown way. */
304 DEF_RTL_EXPR(USE, "use", "e", RTX_EXTRA)
306 /* Indicate something is clobbered in a way that we don't want to explain.
307 For example, subroutine calls will clobber some physical registers
308 (the ones that are by convention not saved).
310 CLOBBER can not appear as an operand of other rtx except for PARALLEL.
311 CLOBBER of a hard register appearing by itself (not within PARALLEL)
312 is considered undeletable before reload. */
313 DEF_RTL_EXPR(CLOBBER, "clobber", "e", RTX_EXTRA)
315 /* Call a subroutine.
316 Operand 1 is the address to call.
317 Operand 2 is the number of arguments. */
319 DEF_RTL_EXPR(CALL, "call", "ee", RTX_EXTRA)
321 /* Return from a subroutine. */
323 DEF_RTL_EXPR(RETURN, "return", "", RTX_EXTRA)
325 /* Like RETURN, but truly represents only a function return, while
326 RETURN may represent an insn that also performs other functions
327 of the function epilogue. Like RETURN, this may also occur in
328 conditional jumps. */
329 DEF_RTL_EXPR(SIMPLE_RETURN, "simple_return", "", RTX_EXTRA)
331 /* Special for EH return from subroutine. */
333 DEF_RTL_EXPR(EH_RETURN, "eh_return", "", RTX_EXTRA)
336 Operand 1 is the condition.
337 Operand 2 is the trap code.
338 For an unconditional trap, make the condition (const_int 1). */
339 DEF_RTL_EXPR(TRAP_IF, "trap_if", "ee", RTX_EXTRA)
341 /* ----------------------------------------------------------------------
342 Primitive values for use in expressions.
343 ---------------------------------------------------------------------- */
345 /* numeric integer constant */
346 DEF_RTL_EXPR(CONST_INT, "const_int", "w", RTX_CONST_OBJ)
348 /* numeric integer constant */
349 DEF_RTL_EXPR(CONST_WIDE_INT, "const_wide_int", "", RTX_CONST_OBJ)
351 /* fixed-point constant */
352 DEF_RTL_EXPR(CONST_FIXED, "const_fixed", "www", RTX_CONST_OBJ)
354 /* numeric floating point or integer constant. If the mode is
355 VOIDmode it is an int otherwise it has a floating point mode and a
356 floating point value. Operands hold the value. They are all 'w'
357 and there may be from 2 to 6; see real.h. */
358 DEF_RTL_EXPR(CONST_DOUBLE, "const_double", CONST_DOUBLE_FORMAT, RTX_CONST_OBJ)
360 /* Describes a vector constant. */
361 DEF_RTL_EXPR(CONST_VECTOR, "const_vector", "E", RTX_CONST_OBJ)
363 /* String constant. Used for attributes in machine descriptions and
364 for special cases in DWARF2 debug output. NOT used for source-
365 language string constants. */
366 DEF_RTL_EXPR(CONST_STRING, "const_string", "s", RTX_OBJ)
368 /* This is used to encapsulate an expression whose value is constant
369 (such as the sum of a SYMBOL_REF and a CONST_INT) so that it will be
370 recognized as a constant operand rather than by arithmetic instructions. */
372 DEF_RTL_EXPR(CONST, "const", "e", RTX_CONST_OBJ)
374 /* program counter. Ordinary jumps are represented
375 by a SET whose first operand is (PC). */
376 DEF_RTL_EXPR(PC, "pc", "", RTX_OBJ)
378 /* A register. The "operand" is the register number, accessed with
379 the REGNO macro. If this number is less than FIRST_PSEUDO_REGISTER
380 than a hardware register is being referred to. The second operand
381 points to a reg_attrs structure.
382 This rtx needs to have as many (or more) fields as a MEM, since we
383 can change REG rtx's into MEMs during reload. */
384 DEF_RTL_EXPR(REG, "reg", "i0", RTX_OBJ)
386 /* A scratch register. This represents a register used only within a
387 single insn. It will be turned into a REG during register allocation
388 or reload unless the constraint indicates that the register won't be
389 needed, in which case it can remain a SCRATCH. This code is
390 marked as having one operand so it can be turned into a REG. */
391 DEF_RTL_EXPR(SCRATCH, "scratch", "0", RTX_OBJ)
393 /* A reference to a part of another value. The first operand is the
394 complete value and the second is the byte offset of the selected part. */
395 DEF_RTL_EXPR(SUBREG, "subreg", "ei", RTX_EXTRA)
397 /* This one-argument rtx is used for move instructions
398 that are guaranteed to alter only the low part of a destination.
399 Thus, (SET (SUBREG:HI (REG...)) (MEM:HI ...))
400 has an unspecified effect on the high part of REG,
401 but (SET (STRICT_LOW_PART (SUBREG:HI (REG...))) (MEM:HI ...))
402 is guaranteed to alter only the bits of REG that are in HImode.
404 The actual instruction used is probably the same in both cases,
405 but the register constraints may be tighter when STRICT_LOW_PART
408 DEF_RTL_EXPR(STRICT_LOW_PART, "strict_low_part", "e", RTX_EXTRA)
410 /* (CONCAT a b) represents the virtual concatenation of a and b
411 to make a value that has as many bits as a and b put together.
412 This is used for complex values. Normally it appears only
413 in DECL_RTLs and during RTL generation, but not in the insn chain. */
414 DEF_RTL_EXPR(CONCAT, "concat", "ee", RTX_OBJ)
416 /* (CONCATN [a1 a2 ... an]) represents the virtual concatenation of
417 all An to make a value. This is an extension of CONCAT to larger
418 number of components. Like CONCAT, it should not appear in the
419 insn chain. Every element of the CONCATN is the same size. */
420 DEF_RTL_EXPR(CONCATN, "concatn", "E", RTX_OBJ)
422 /* A memory location; operand is the address. The second operand is the
423 alias set to which this MEM belongs. We use `0' instead of `w' for this
424 field so that the field need not be specified in machine descriptions. */
425 DEF_RTL_EXPR(MEM, "mem", "e0", RTX_OBJ)
427 /* Reference to an assembler label in the code for this function.
428 The operand is a CODE_LABEL found in the insn chain. */
429 DEF_RTL_EXPR(LABEL_REF, "label_ref", "u", RTX_CONST_OBJ)
431 /* Reference to a named label:
432 Operand 0: label name
433 Operand 1: flags (see SYMBOL_FLAG_* in rtl.h)
434 Operand 2: tree from which this symbol is derived, or null.
435 This is either a DECL node, or some kind of constant. */
436 DEF_RTL_EXPR(SYMBOL_REF, "symbol_ref", "s00", RTX_CONST_OBJ)
438 /* The condition code register is represented, in our imagination,
439 as a register holding a value that can be compared to zero.
440 In fact, the machine has already compared them and recorded the
441 results; but instructions that look at the condition code
442 pretend to be looking at the entire value and comparing it. */
443 DEF_RTL_EXPR(CC0, "cc0", "", RTX_OBJ)
445 /* ----------------------------------------------------------------------
446 Expressions for operators in an rtl pattern
447 ---------------------------------------------------------------------- */
449 /* if_then_else. This is used in representing ordinary
450 conditional jump instructions.
455 DEF_RTL_EXPR(IF_THEN_ELSE, "if_then_else", "eee", RTX_TERNARY)
457 /* Comparison, produces a condition code result. */
458 DEF_RTL_EXPR(COMPARE, "compare", "ee", RTX_BIN_ARITH)
461 DEF_RTL_EXPR(PLUS, "plus", "ee", RTX_COMM_ARITH)
463 /* Operand 0 minus operand 1. */
464 DEF_RTL_EXPR(MINUS, "minus", "ee", RTX_BIN_ARITH)
466 /* Minus operand 0. */
467 DEF_RTL_EXPR(NEG, "neg", "e", RTX_UNARY)
469 DEF_RTL_EXPR(MULT, "mult", "ee", RTX_COMM_ARITH)
471 /* Multiplication with signed saturation */
472 DEF_RTL_EXPR(SS_MULT, "ss_mult", "ee", RTX_COMM_ARITH)
473 /* Multiplication with unsigned saturation */
474 DEF_RTL_EXPR(US_MULT, "us_mult", "ee", RTX_COMM_ARITH)
476 /* Operand 0 divided by operand 1. */
477 DEF_RTL_EXPR(DIV, "div", "ee", RTX_BIN_ARITH)
478 /* Division with signed saturation */
479 DEF_RTL_EXPR(SS_DIV, "ss_div", "ee", RTX_BIN_ARITH)
480 /* Division with unsigned saturation */
481 DEF_RTL_EXPR(US_DIV, "us_div", "ee", RTX_BIN_ARITH)
483 /* Remainder of operand 0 divided by operand 1. */
484 DEF_RTL_EXPR(MOD, "mod", "ee", RTX_BIN_ARITH)
486 /* Unsigned divide and remainder. */
487 DEF_RTL_EXPR(UDIV, "udiv", "ee", RTX_BIN_ARITH)
488 DEF_RTL_EXPR(UMOD, "umod", "ee", RTX_BIN_ARITH)
490 /* Bitwise operations. */
491 DEF_RTL_EXPR(AND, "and", "ee", RTX_COMM_ARITH)
492 DEF_RTL_EXPR(IOR, "ior", "ee", RTX_COMM_ARITH)
493 DEF_RTL_EXPR(XOR, "xor", "ee", RTX_COMM_ARITH)
494 DEF_RTL_EXPR(NOT, "not", "e", RTX_UNARY)
497 0: value to be shifted.
498 1: number of bits. */
499 DEF_RTL_EXPR(ASHIFT, "ashift", "ee", RTX_BIN_ARITH) /* shift left */
500 DEF_RTL_EXPR(ROTATE, "rotate", "ee", RTX_BIN_ARITH) /* rotate left */
501 DEF_RTL_EXPR(ASHIFTRT, "ashiftrt", "ee", RTX_BIN_ARITH) /* arithmetic shift right */
502 DEF_RTL_EXPR(LSHIFTRT, "lshiftrt", "ee", RTX_BIN_ARITH) /* logical shift right */
503 DEF_RTL_EXPR(ROTATERT, "rotatert", "ee", RTX_BIN_ARITH) /* rotate right */
505 /* Minimum and maximum values of two operands. We need both signed and
506 unsigned forms. (We cannot use MIN for SMIN because it conflicts
507 with a macro of the same name.) The signed variants should be used
508 with floating point. Further, if both operands are zeros, or if either
509 operand is NaN, then it is unspecified which of the two operands is
510 returned as the result. */
512 DEF_RTL_EXPR(SMIN, "smin", "ee", RTX_COMM_ARITH)
513 DEF_RTL_EXPR(SMAX, "smax", "ee", RTX_COMM_ARITH)
514 DEF_RTL_EXPR(UMIN, "umin", "ee", RTX_COMM_ARITH)
515 DEF_RTL_EXPR(UMAX, "umax", "ee", RTX_COMM_ARITH)
517 /* These unary operations are used to represent incrementation
518 and decrementation as they occur in memory addresses.
519 The amount of increment or decrement are not represented
520 because they can be understood from the machine-mode of the
521 containing MEM. These operations exist in only two cases:
522 1. pushes onto the stack.
523 2. created automatically by the auto-inc-dec pass. */
524 DEF_RTL_EXPR(PRE_DEC, "pre_dec", "e", RTX_AUTOINC)
525 DEF_RTL_EXPR(PRE_INC, "pre_inc", "e", RTX_AUTOINC)
526 DEF_RTL_EXPR(POST_DEC, "post_dec", "e", RTX_AUTOINC)
527 DEF_RTL_EXPR(POST_INC, "post_inc", "e", RTX_AUTOINC)
529 /* These binary operations are used to represent generic address
530 side-effects in memory addresses, except for simple incrementation
531 or decrementation which use the above operations. They are
532 created automatically by the life_analysis pass in flow.c.
533 The first operand is a REG which is used as the address.
534 The second operand is an expression that is assigned to the
535 register, either before (PRE_MODIFY) or after (POST_MODIFY)
536 evaluating the address.
537 Currently, the compiler can only handle second operands of the
538 form (plus (reg) (reg)) and (plus (reg) (const_int)), where
539 the first operand of the PLUS has to be the same register as
540 the first operand of the *_MODIFY. */
541 DEF_RTL_EXPR(PRE_MODIFY, "pre_modify", "ee", RTX_AUTOINC)
542 DEF_RTL_EXPR(POST_MODIFY, "post_modify", "ee", RTX_AUTOINC)
544 /* Comparison operations. The ordered comparisons exist in two
545 flavors, signed and unsigned. */
546 DEF_RTL_EXPR(NE, "ne", "ee", RTX_COMM_COMPARE)
547 DEF_RTL_EXPR(EQ, "eq", "ee", RTX_COMM_COMPARE)
548 DEF_RTL_EXPR(GE, "ge", "ee", RTX_COMPARE)
549 DEF_RTL_EXPR(GT, "gt", "ee", RTX_COMPARE)
550 DEF_RTL_EXPR(LE, "le", "ee", RTX_COMPARE)
551 DEF_RTL_EXPR(LT, "lt", "ee", RTX_COMPARE)
552 DEF_RTL_EXPR(GEU, "geu", "ee", RTX_COMPARE)
553 DEF_RTL_EXPR(GTU, "gtu", "ee", RTX_COMPARE)
554 DEF_RTL_EXPR(LEU, "leu", "ee", RTX_COMPARE)
555 DEF_RTL_EXPR(LTU, "ltu", "ee", RTX_COMPARE)
557 /* Additional floating point unordered comparison flavors. */
558 DEF_RTL_EXPR(UNORDERED, "unordered", "ee", RTX_COMM_COMPARE)
559 DEF_RTL_EXPR(ORDERED, "ordered", "ee", RTX_COMM_COMPARE)
561 /* These are equivalent to unordered or ... */
562 DEF_RTL_EXPR(UNEQ, "uneq", "ee", RTX_COMM_COMPARE)
563 DEF_RTL_EXPR(UNGE, "unge", "ee", RTX_COMPARE)
564 DEF_RTL_EXPR(UNGT, "ungt", "ee", RTX_COMPARE)
565 DEF_RTL_EXPR(UNLE, "unle", "ee", RTX_COMPARE)
566 DEF_RTL_EXPR(UNLT, "unlt", "ee", RTX_COMPARE)
568 /* This is an ordered NE, ie !UNEQ, ie false for NaN. */
569 DEF_RTL_EXPR(LTGT, "ltgt", "ee", RTX_COMM_COMPARE)
571 /* Represents the result of sign-extending the sole operand.
572 The machine modes of the operand and of the SIGN_EXTEND expression
573 determine how much sign-extension is going on. */
574 DEF_RTL_EXPR(SIGN_EXTEND, "sign_extend", "e", RTX_UNARY)
576 /* Similar for zero-extension (such as unsigned short to int). */
577 DEF_RTL_EXPR(ZERO_EXTEND, "zero_extend", "e", RTX_UNARY)
579 /* Similar but here the operand has a wider mode. */
580 DEF_RTL_EXPR(TRUNCATE, "truncate", "e", RTX_UNARY)
582 /* Similar for extending floating-point values (such as SFmode to DFmode). */
583 DEF_RTL_EXPR(FLOAT_EXTEND, "float_extend", "e", RTX_UNARY)
584 DEF_RTL_EXPR(FLOAT_TRUNCATE, "float_truncate", "e", RTX_UNARY)
586 /* Conversion of fixed point operand to floating point value. */
587 DEF_RTL_EXPR(FLOAT, "float", "e", RTX_UNARY)
589 /* With fixed-point machine mode:
590 Conversion of floating point operand to fixed point value.
591 Value is defined only when the operand's value is an integer.
592 With floating-point machine mode (and operand with same mode):
593 Operand is rounded toward zero to produce an integer value
594 represented in floating point. */
595 DEF_RTL_EXPR(FIX, "fix", "e", RTX_UNARY)
597 /* Conversion of unsigned fixed point operand to floating point value. */
598 DEF_RTL_EXPR(UNSIGNED_FLOAT, "unsigned_float", "e", RTX_UNARY)
600 /* With fixed-point machine mode:
601 Conversion of floating point operand to *unsigned* fixed point value.
602 Value is defined only when the operand's value is an integer. */
603 DEF_RTL_EXPR(UNSIGNED_FIX, "unsigned_fix", "e", RTX_UNARY)
605 /* Conversions involving fractional fixed-point types without saturation,
607 fractional to fractional (of different precision),
608 signed integer to fractional,
609 fractional to signed integer,
610 floating point to fractional,
611 fractional to floating point.
612 NOTE: fractional can be either signed or unsigned for conversions. */
613 DEF_RTL_EXPR(FRACT_CONVERT, "fract_convert", "e", RTX_UNARY)
615 /* Conversions involving fractional fixed-point types and unsigned integer
616 without saturation, including:
617 unsigned integer to fractional,
618 fractional to unsigned integer.
619 NOTE: fractional can be either signed or unsigned for conversions. */
620 DEF_RTL_EXPR(UNSIGNED_FRACT_CONVERT, "unsigned_fract_convert", "e", RTX_UNARY)
622 /* Conversions involving fractional fixed-point types with saturation,
624 fractional to fractional (of different precision),
625 signed integer to fractional,
626 floating point to fractional.
627 NOTE: fractional can be either signed or unsigned for conversions. */
628 DEF_RTL_EXPR(SAT_FRACT, "sat_fract", "e", RTX_UNARY)
630 /* Conversions involving fractional fixed-point types and unsigned integer
631 with saturation, including:
632 unsigned integer to fractional.
633 NOTE: fractional can be either signed or unsigned for conversions. */
634 DEF_RTL_EXPR(UNSIGNED_SAT_FRACT, "unsigned_sat_fract", "e", RTX_UNARY)
637 DEF_RTL_EXPR(ABS, "abs", "e", RTX_UNARY)
640 DEF_RTL_EXPR(SQRT, "sqrt", "e", RTX_UNARY)
643 DEF_RTL_EXPR(BSWAP, "bswap", "e", RTX_UNARY)
645 /* Find first bit that is set.
646 Value is 1 + number of trailing zeros in the arg.,
648 DEF_RTL_EXPR(FFS, "ffs", "e", RTX_UNARY)
650 /* Count number of leading redundant sign bits (number of leading
651 sign bits minus one). */
652 DEF_RTL_EXPR(CLRSB, "clrsb", "e", RTX_UNARY)
654 /* Count leading zeros. */
655 DEF_RTL_EXPR(CLZ, "clz", "e", RTX_UNARY)
657 /* Count trailing zeros. */
658 DEF_RTL_EXPR(CTZ, "ctz", "e", RTX_UNARY)
660 /* Population count (number of 1 bits). */
661 DEF_RTL_EXPR(POPCOUNT, "popcount", "e", RTX_UNARY)
663 /* Population parity (number of 1 bits modulo 2). */
664 DEF_RTL_EXPR(PARITY, "parity", "e", RTX_UNARY)
666 /* Reference to a signed bit-field of specified size and position.
667 Operand 0 is the memory unit (usually SImode or QImode) which
668 contains the field's first bit. Operand 1 is the width, in bits.
669 Operand 2 is the number of bits in the memory unit before the
670 first bit of this field.
671 If BITS_BIG_ENDIAN is defined, the first bit is the msb and
672 operand 2 counts from the msb of the memory unit.
673 Otherwise, the first bit is the lsb and operand 2 counts from
674 the lsb of the memory unit.
675 This kind of expression can not appear as an lvalue in RTL. */
676 DEF_RTL_EXPR(SIGN_EXTRACT, "sign_extract", "eee", RTX_BITFIELD_OPS)
678 /* Similar for unsigned bit-field.
679 But note! This kind of expression _can_ appear as an lvalue. */
680 DEF_RTL_EXPR(ZERO_EXTRACT, "zero_extract", "eee", RTX_BITFIELD_OPS)
682 /* For RISC machines. These save memory when splitting insns. */
684 /* HIGH are the high-order bits of a constant expression. */
685 DEF_RTL_EXPR(HIGH, "high", "e", RTX_CONST_OBJ)
687 /* LO_SUM is the sum of a register and the low-order bits
688 of a constant expression. */
689 DEF_RTL_EXPR(LO_SUM, "lo_sum", "ee", RTX_OBJ)
691 /* Describes a merge operation between two vector values.
692 Operands 0 and 1 are the vectors to be merged, operand 2 is a bitmask
693 that specifies where the parts of the result are taken from. Set bits
694 indicate operand 0, clear bits indicate operand 1. The parts are defined
695 by the mode of the vectors. */
696 DEF_RTL_EXPR(VEC_MERGE, "vec_merge", "eee", RTX_TERNARY)
698 /* Describes an operation that selects parts of a vector.
699 Operands 0 is the source vector, operand 1 is a PARALLEL that contains
700 a CONST_INT for each of the subparts of the result vector, giving the
701 number of the source subpart that should be stored into it. */
702 DEF_RTL_EXPR(VEC_SELECT, "vec_select", "ee", RTX_BIN_ARITH)
704 /* Describes a vector concat operation. Operands 0 and 1 are the source
705 vectors, the result is a vector that is as long as operands 0 and 1
706 combined and is the concatenation of the two source vectors. */
707 DEF_RTL_EXPR(VEC_CONCAT, "vec_concat", "ee", RTX_BIN_ARITH)
709 /* Describes an operation that converts a small vector into a larger one by
710 duplicating the input values. The output vector mode must have the same
711 submodes as the input vector mode, and the number of output parts must be
712 an integer multiple of the number of input parts. */
713 DEF_RTL_EXPR(VEC_DUPLICATE, "vec_duplicate", "e", RTX_UNARY)
715 /* Addition with signed saturation */
716 DEF_RTL_EXPR(SS_PLUS, "ss_plus", "ee", RTX_COMM_ARITH)
718 /* Addition with unsigned saturation */
719 DEF_RTL_EXPR(US_PLUS, "us_plus", "ee", RTX_COMM_ARITH)
721 /* Operand 0 minus operand 1, with signed saturation. */
722 DEF_RTL_EXPR(SS_MINUS, "ss_minus", "ee", RTX_BIN_ARITH)
724 /* Negation with signed saturation. */
725 DEF_RTL_EXPR(SS_NEG, "ss_neg", "e", RTX_UNARY)
726 /* Negation with unsigned saturation. */
727 DEF_RTL_EXPR(US_NEG, "us_neg", "e", RTX_UNARY)
729 /* Absolute value with signed saturation. */
730 DEF_RTL_EXPR(SS_ABS, "ss_abs", "e", RTX_UNARY)
732 /* Shift left with signed saturation. */
733 DEF_RTL_EXPR(SS_ASHIFT, "ss_ashift", "ee", RTX_BIN_ARITH)
735 /* Shift left with unsigned saturation. */
736 DEF_RTL_EXPR(US_ASHIFT, "us_ashift", "ee", RTX_BIN_ARITH)
738 /* Operand 0 minus operand 1, with unsigned saturation. */
739 DEF_RTL_EXPR(US_MINUS, "us_minus", "ee", RTX_BIN_ARITH)
741 /* Signed saturating truncate. */
742 DEF_RTL_EXPR(SS_TRUNCATE, "ss_truncate", "e", RTX_UNARY)
744 /* Unsigned saturating truncate. */
745 DEF_RTL_EXPR(US_TRUNCATE, "us_truncate", "e", RTX_UNARY)
747 /* Floating point multiply/add combined instruction. */
748 DEF_RTL_EXPR(FMA, "fma", "eee", RTX_TERNARY)
750 /* Information about the variable and its location. */
751 /* Changed 'te' to 'tei'; the 'i' field is for recording
752 initialization status of variables. */
753 DEF_RTL_EXPR(VAR_LOCATION, "var_location", "tei", RTX_EXTRA)
755 /* Used in VAR_LOCATION for a pointer to a decl that is no longer
757 DEF_RTL_EXPR(DEBUG_IMPLICIT_PTR, "debug_implicit_ptr", "t", RTX_OBJ)
759 /* Represents value that argument had on function entry. The
760 single argument is the DECL_INCOMING_RTL of the corresponding
762 DEF_RTL_EXPR(ENTRY_VALUE, "entry_value", "0", RTX_OBJ)
764 /* Used in VAR_LOCATION for a reference to a parameter that has
765 been optimized away completely. */
766 DEF_RTL_EXPR(DEBUG_PARAMETER_REF, "debug_parameter_ref", "t", RTX_OBJ)
768 /* All expressions from this point forward appear only in machine
770 #ifdef GENERATOR_FILE
772 /* Pattern-matching operators: */
774 /* Use the function named by the second arg (the string)
775 as a predicate; if matched, store the structure that was matched
776 in the operand table at index specified by the first arg (the integer).
777 If the second arg is the null string, the structure is just stored.
779 A third string argument indicates to the register allocator restrictions
780 on where the operand can be allocated.
782 If the target needs no restriction on any instruction this field should
785 The string is prepended by:
786 '=' to indicate the operand is only written to.
787 '+' to indicate the operand is both read and written to.
789 Each character in the string represents an allocable class for an operand.
790 'g' indicates the operand can be any valid class.
791 'i' indicates the operand can be immediate (in the instruction) data.
792 'r' indicates the operand can be in a register.
793 'm' indicates the operand can be in memory.
794 'o' a subset of the 'm' class. Those memory addressing modes that
795 can be offset at compile time (have a constant added to them).
797 Other characters indicate target dependent operand classes and
798 are described in each target's machine description.
800 For instructions with more than one operand, sets of classes can be
801 separated by a comma to indicate the appropriate multi-operand constraints.
802 There must be a 1 to 1 correspondence between these sets of classes in
803 all operands for an instruction.
805 DEF_RTL_EXPR(MATCH_OPERAND, "match_operand", "iss", RTX_MATCH)
807 /* Match a SCRATCH or a register. When used to generate rtl, a
808 SCRATCH is generated. As for MATCH_OPERAND, the mode specifies
809 the desired mode and the first argument is the operand number.
810 The second argument is the constraint. */
811 DEF_RTL_EXPR(MATCH_SCRATCH, "match_scratch", "is", RTX_MATCH)
813 /* Apply a predicate, AND match recursively the operands of the rtx.
814 Operand 0 is the operand-number, as in match_operand.
815 Operand 1 is a predicate to apply (as a string, a function name).
816 Operand 2 is a vector of expressions, each of which must match
817 one subexpression of the rtx this construct is matching. */
818 DEF_RTL_EXPR(MATCH_OPERATOR, "match_operator", "isE", RTX_MATCH)
820 /* Match a PARALLEL of arbitrary length. The predicate is applied
821 to the PARALLEL and the initial expressions in the PARALLEL are matched.
822 Operand 0 is the operand-number, as in match_operand.
823 Operand 1 is a predicate to apply to the PARALLEL.
824 Operand 2 is a vector of expressions, each of which must match the
825 corresponding element in the PARALLEL. */
826 DEF_RTL_EXPR(MATCH_PARALLEL, "match_parallel", "isE", RTX_MATCH)
828 /* Match only something equal to what is stored in the operand table
829 at the index specified by the argument. Use with MATCH_OPERAND. */
830 DEF_RTL_EXPR(MATCH_DUP, "match_dup", "i", RTX_MATCH)
832 /* Match only something equal to what is stored in the operand table
833 at the index specified by the argument. Use with MATCH_OPERATOR. */
834 DEF_RTL_EXPR(MATCH_OP_DUP, "match_op_dup", "iE", RTX_MATCH)
836 /* Match only something equal to what is stored in the operand table
837 at the index specified by the argument. Use with MATCH_PARALLEL. */
838 DEF_RTL_EXPR(MATCH_PAR_DUP, "match_par_dup", "iE", RTX_MATCH)
840 /* Appears only in define_predicate/define_special_predicate
841 expressions. Evaluates true only if the operand has an RTX code
842 from the set given by the argument (a comma-separated list). If the
843 second argument is present and nonempty, it is a sequence of digits
844 and/or letters which indicates the subexpression to test, using the
845 same syntax as genextract/genrecog's location strings: 0-9 for
846 XEXP (op, n), a-z for XVECEXP (op, 0, n); each character applies to
847 the result of the one before it. */
848 DEF_RTL_EXPR(MATCH_CODE, "match_code", "ss", RTX_MATCH)
850 /* Used to inject a C conditional expression into an .md file. It can
851 appear in a predicate definition or an attribute expression. */
852 DEF_RTL_EXPR(MATCH_TEST, "match_test", "s", RTX_MATCH)
854 /* Insn (and related) definitions. */
856 /* Definition of the pattern for one kind of instruction.
858 0: names this instruction.
859 If the name is the null string, the instruction is in the
860 machine description just to be recognized, and will never be emitted by
861 the tree to rtl expander.
863 2: is a string which is a C expression
864 giving an additional condition for recognizing this pattern.
865 A null string means no extra condition.
866 3: is the action to execute if this pattern is matched.
867 If this assembler code template starts with a * then it is a fragment of
868 C code to run to decide on a template to use. Otherwise, it is the
870 4: optionally, a vector of attributes for this insn.
872 DEF_RTL_EXPR(DEFINE_INSN, "define_insn", "sEsTV", RTX_EXTRA)
874 /* Definition of a peephole optimization.
875 1st operand: vector of insn patterns to match
876 2nd operand: C expression that must be true
877 3rd operand: template or C code to produce assembler output.
878 4: optionally, a vector of attributes for this insn.
880 This form is deprecated; use define_peephole2 instead. */
881 DEF_RTL_EXPR(DEFINE_PEEPHOLE, "define_peephole", "EsTV", RTX_EXTRA)
883 /* Definition of a split operation.
884 1st operand: insn pattern to match
885 2nd operand: C expression that must be true
886 3rd operand: vector of insn patterns to place into a SEQUENCE
887 4th operand: optionally, some C code to execute before generating the
888 insns. This might, for example, create some RTX's and store them in
889 elements of `recog_data.operand' for use by the vector of
891 (`operands' is an alias here for `recog_data.operand'). */
892 DEF_RTL_EXPR(DEFINE_SPLIT, "define_split", "EsES", RTX_EXTRA)
894 /* Definition of an insn and associated split.
895 This is the concatenation, with a few modifications, of a define_insn
896 and a define_split which share the same pattern.
898 0: names this instruction.
899 If the name is the null string, the instruction is in the
900 machine description just to be recognized, and will never be emitted by
901 the tree to rtl expander.
903 2: is a string which is a C expression
904 giving an additional condition for recognizing this pattern.
905 A null string means no extra condition.
906 3: is the action to execute if this pattern is matched.
907 If this assembler code template starts with a * then it is a fragment of
908 C code to run to decide on a template to use. Otherwise, it is the
910 4: C expression that must be true for split. This may start with "&&"
911 in which case the split condition is the logical and of the insn
912 condition and what follows the "&&" of this operand.
913 5: vector of insn patterns to place into a SEQUENCE
914 6: optionally, some C code to execute before generating the
915 insns. This might, for example, create some RTX's and store them in
916 elements of `recog_data.operand' for use by the vector of
918 (`operands' is an alias here for `recog_data.operand').
919 7: optionally, a vector of attributes for this insn. */
920 DEF_RTL_EXPR(DEFINE_INSN_AND_SPLIT, "define_insn_and_split", "sEsTsESV", RTX_EXTRA)
922 /* Definition of an RTL peephole operation.
923 Follows the same arguments as define_split. */
924 DEF_RTL_EXPR(DEFINE_PEEPHOLE2, "define_peephole2", "EsES", RTX_EXTRA)
926 /* Define how to generate multiple insns for a standard insn name.
927 1st operand: the insn name.
928 2nd operand: vector of insn-patterns.
929 Use match_operand to substitute an element of `recog_data.operand'.
930 3rd operand: C expression that must be true for this to be available.
931 This may not test any operands.
932 4th operand: Extra C code to execute before generating the insns.
933 This might, for example, create some RTX's and store them in
934 elements of `recog_data.operand' for use by the vector of
936 (`operands' is an alias here for `recog_data.operand').
937 5th: optionally, a vector of attributes for this expand. */
938 DEF_RTL_EXPR(DEFINE_EXPAND, "define_expand", "sEssV", RTX_EXTRA)
940 /* Define a requirement for delay slots.
941 1st operand: Condition involving insn attributes that, if true,
942 indicates that the insn requires the number of delay slots
944 2nd operand: Vector whose length is the three times the number of delay
946 Each entry gives three conditions, each involving attributes.
947 The first must be true for an insn to occupy that delay slot
948 location. The second is true for all insns that can be
949 annulled if the branch is true and the third is true for all
950 insns that can be annulled if the branch is false.
952 Multiple DEFINE_DELAYs may be present. They indicate differing
953 requirements for delay slots. */
954 DEF_RTL_EXPR(DEFINE_DELAY, "define_delay", "eE", RTX_EXTRA)
956 /* Define attribute computation for `asm' instructions. */
957 DEF_RTL_EXPR(DEFINE_ASM_ATTRIBUTES, "define_asm_attributes", "V", RTX_EXTRA)
959 /* Definition of a conditional execution meta operation. Automatically
960 generates new instances of DEFINE_INSN, selected by having attribute
961 "predicable" true. The new pattern will contain a COND_EXEC and the
962 predicate at top-level.
965 0: The predicate pattern. The top-level form should match a
966 relational operator. Operands should have only one alternative.
967 1: A C expression giving an additional condition for recognizing
968 the generated pattern.
969 2: A template or C code to produce assembler output.
970 3: A vector of attributes to append to the resulting cond_exec insn. */
971 DEF_RTL_EXPR(DEFINE_COND_EXEC, "define_cond_exec", "EssV", RTX_EXTRA)
973 /* Definition of an operand predicate. The difference between
974 DEFINE_PREDICATE and DEFINE_SPECIAL_PREDICATE is that genrecog will
975 not warn about a match_operand with no mode if it has a predicate
976 defined with DEFINE_SPECIAL_PREDICATE.
979 0: The name of the predicate.
980 1: A boolean expression which computes whether or not the predicate
981 matches. This expression can use IOR, AND, NOT, MATCH_OPERAND,
982 MATCH_CODE, and MATCH_TEST. It must be specific enough that genrecog
983 can calculate the set of RTX codes that can possibly match.
984 2: A C function body which must return true for the predicate to match.
985 Optional. Use this when the test is too complicated to fit into a
986 match_test expression. */
987 DEF_RTL_EXPR(DEFINE_PREDICATE, "define_predicate", "ses", RTX_EXTRA)
988 DEF_RTL_EXPR(DEFINE_SPECIAL_PREDICATE, "define_special_predicate", "ses", RTX_EXTRA)
990 /* Definition of a register operand constraint. This simply maps the
991 constraint string to a register class.
994 0: The name of the constraint (often, but not always, a single letter).
995 1: A C expression which evaluates to the appropriate register class for
996 this constraint. If this is not just a constant, it should look only
997 at -m switches and the like.
998 2: A docstring for this constraint, in Texinfo syntax; not currently
999 used, in future will be incorporated into the manual's list of
1000 machine-specific operand constraints. */
1001 DEF_RTL_EXPR(DEFINE_REGISTER_CONSTRAINT, "define_register_constraint", "sss", RTX_EXTRA)
1003 /* Definition of a non-register operand constraint. These look at the
1004 operand and decide whether it fits the constraint.
1006 DEFINE_CONSTRAINT gets no special treatment if it fails to match.
1007 It is appropriate for constant-only constraints, and most others.
1009 DEFINE_MEMORY_CONSTRAINT tells reload that this constraint can be made
1010 to match, if it doesn't already, by converting the operand to the form
1011 (mem (reg X)) where X is a base register. It is suitable for constraints
1012 that describe a subset of all memory references.
1014 DEFINE_ADDRESS_CONSTRAINT tells reload that this constraint can be made
1015 to match, if it doesn't already, by converting the operand to the form
1016 (reg X) where X is a base register. It is suitable for constraints that
1017 describe a subset of all address references.
1019 When in doubt, use plain DEFINE_CONSTRAINT.
1022 0: The name of the constraint (often, but not always, a single letter).
1023 1: A docstring for this constraint, in Texinfo syntax; not currently
1024 used, in future will be incorporated into the manual's list of
1025 machine-specific operand constraints.
1026 2: A boolean expression which computes whether or not the constraint
1027 matches. It should follow the same rules as a define_predicate
1028 expression, including the bit about specifying the set of RTX codes
1029 that could possibly match. MATCH_TEST subexpressions may make use of
1031 `op' - the RTL object defining the operand.
1032 `mode' - the mode of `op'.
1033 `ival' - INTVAL(op), if op is a CONST_INT.
1034 `hval' - CONST_DOUBLE_HIGH(op), if op is an integer CONST_DOUBLE.
1035 `lval' - CONST_DOUBLE_LOW(op), if op is an integer CONST_DOUBLE.
1036 `rval' - CONST_DOUBLE_REAL_VALUE(op), if op is a floating-point
1038 Do not use ival/hval/lval/rval if op is not the appropriate kind of
1040 DEF_RTL_EXPR(DEFINE_CONSTRAINT, "define_constraint", "sse", RTX_EXTRA)
1041 DEF_RTL_EXPR(DEFINE_MEMORY_CONSTRAINT, "define_memory_constraint", "sse", RTX_EXTRA)
1042 DEF_RTL_EXPR(DEFINE_ADDRESS_CONSTRAINT, "define_address_constraint", "sse", RTX_EXTRA)
1045 /* Constructions for CPU pipeline description described by NDFAs. */
1047 /* (define_cpu_unit string [string]) describes cpu functional
1048 units (separated by comma).
1050 1st operand: Names of cpu functional units.
1051 2nd operand: Name of automaton (see comments for DEFINE_AUTOMATON).
1053 All define_reservations, define_cpu_units, and
1054 define_query_cpu_units should have unique names which may not be
1056 DEF_RTL_EXPR(DEFINE_CPU_UNIT, "define_cpu_unit", "sS", RTX_EXTRA)
1058 /* (define_query_cpu_unit string [string]) describes cpu functional
1059 units analogously to define_cpu_unit. The reservation of such
1060 units can be queried for automaton state. */
1061 DEF_RTL_EXPR(DEFINE_QUERY_CPU_UNIT, "define_query_cpu_unit", "sS", RTX_EXTRA)
1063 /* (exclusion_set string string) means that each CPU functional unit
1064 in the first string can not be reserved simultaneously with any
1065 unit whose name is in the second string and vise versa. CPU units
1066 in the string are separated by commas. For example, it is useful
1067 for description CPU with fully pipelined floating point functional
1068 unit which can execute simultaneously only single floating point
1069 insns or only double floating point insns. All CPU functional
1070 units in a set should belong to the same automaton. */
1071 DEF_RTL_EXPR(EXCLUSION_SET, "exclusion_set", "ss", RTX_EXTRA)
1073 /* (presence_set string string) means that each CPU functional unit in
1074 the first string can not be reserved unless at least one of pattern
1075 of units whose names are in the second string is reserved. This is
1076 an asymmetric relation. CPU units or unit patterns in the strings
1077 are separated by commas. Pattern is one unit name or unit names
1078 separated by white-spaces.
1080 For example, it is useful for description that slot1 is reserved
1081 after slot0 reservation for a VLIW processor. We could describe it
1082 by the following construction
1084 (presence_set "slot1" "slot0")
1086 Or slot1 is reserved only after slot0 and unit b0 reservation. In
1087 this case we could write
1089 (presence_set "slot1" "slot0 b0")
1091 All CPU functional units in a set should belong to the same
1093 DEF_RTL_EXPR(PRESENCE_SET, "presence_set", "ss", RTX_EXTRA)
1095 /* (final_presence_set string string) is analogous to `presence_set'.
1096 The difference between them is when checking is done. When an
1097 instruction is issued in given automaton state reflecting all
1098 current and planned unit reservations, the automaton state is
1099 changed. The first state is a source state, the second one is a
1100 result state. Checking for `presence_set' is done on the source
1101 state reservation, checking for `final_presence_set' is done on the
1102 result reservation. This construction is useful to describe a
1103 reservation which is actually two subsequent reservations. For
1106 (presence_set "slot1" "slot0")
1108 the following insn will be never issued (because slot1 requires
1109 slot0 which is absent in the source state).
1111 (define_reservation "insn_and_nop" "slot0 + slot1")
1113 but it can be issued if we use analogous `final_presence_set'. */
1114 DEF_RTL_EXPR(FINAL_PRESENCE_SET, "final_presence_set", "ss", RTX_EXTRA)
1116 /* (absence_set string string) means that each CPU functional unit in
1117 the first string can be reserved only if each pattern of units
1118 whose names are in the second string is not reserved. This is an
1119 asymmetric relation (actually exclusion set is analogous to this
1120 one but it is symmetric). CPU units or unit patterns in the string
1121 are separated by commas. Pattern is one unit name or unit names
1122 separated by white-spaces.
1124 For example, it is useful for description that slot0 can not be
1125 reserved after slot1 or slot2 reservation for a VLIW processor. We
1126 could describe it by the following construction
1128 (absence_set "slot2" "slot0, slot1")
1130 Or slot2 can not be reserved if slot0 and unit b0 are reserved or
1131 slot1 and unit b1 are reserved . In this case we could write
1133 (absence_set "slot2" "slot0 b0, slot1 b1")
1135 All CPU functional units in a set should to belong the same
1137 DEF_RTL_EXPR(ABSENCE_SET, "absence_set", "ss", RTX_EXTRA)
1139 /* (final_absence_set string string) is analogous to `absence_set' but
1140 checking is done on the result (state) reservation. See comments
1141 for `final_presence_set'. */
1142 DEF_RTL_EXPR(FINAL_ABSENCE_SET, "final_absence_set", "ss", RTX_EXTRA)
1144 /* (define_bypass number out_insn_names in_insn_names) names bypass
1145 with given latency (the first number) from insns given by the first
1146 string (see define_insn_reservation) into insns given by the second
1147 string. Insn names in the strings are separated by commas. The
1148 third operand is optional name of function which is additional
1149 guard for the bypass. The function will get the two insns as
1150 parameters. If the function returns zero the bypass will be
1151 ignored for this case. Additional guard is necessary to recognize
1152 complicated bypasses, e.g. when consumer is load address. If there
1153 are more one bypass with the same output and input insns, the
1154 chosen bypass is the first bypass with a guard in description whose
1155 guard function returns nonzero. If there is no such bypass, then
1156 bypass without the guard function is chosen. */
1157 DEF_RTL_EXPR(DEFINE_BYPASS, "define_bypass", "issS", RTX_EXTRA)
1159 /* (define_automaton string) describes names of automata generated and
1160 used for pipeline hazards recognition. The names are separated by
1161 comma. Actually it is possibly to generate the single automaton
1162 but unfortunately it can be very large. If we use more one
1163 automata, the summary size of the automata usually is less than the
1164 single one. The automaton name is used in define_cpu_unit and
1165 define_query_cpu_unit. All automata should have unique names. */
1166 DEF_RTL_EXPR(DEFINE_AUTOMATON, "define_automaton", "s", RTX_EXTRA)
1168 /* (automata_option string) describes option for generation of
1169 automata. Currently there are the following options:
1171 o "no-minimization" which makes no minimization of automata. This
1172 is only worth to do when we are debugging the description and
1173 need to look more accurately at reservations of states.
1175 o "time" which means printing additional time statistics about
1176 generation of automata.
1178 o "v" which means generation of file describing the result
1179 automata. The file has suffix `.dfa' and can be used for the
1180 description verification and debugging.
1182 o "w" which means generation of warning instead of error for
1183 non-critical errors.
1185 o "ndfa" which makes nondeterministic finite state automata.
1187 o "progress" which means output of a progress bar showing how many
1188 states were generated so far for automaton being processed. */
1189 DEF_RTL_EXPR(AUTOMATA_OPTION, "automata_option", "s", RTX_EXTRA)
1191 /* (define_reservation string string) names reservation (the first
1192 string) of cpu functional units (the 2nd string). Sometimes unit
1193 reservations for different insns contain common parts. In such
1194 case, you can describe common part and use its name (the 1st
1195 parameter) in regular expression in define_insn_reservation. All
1196 define_reservations, define_cpu_units, and define_query_cpu_units
1197 should have unique names which may not be "nothing". */
1198 DEF_RTL_EXPR(DEFINE_RESERVATION, "define_reservation", "ss", RTX_EXTRA)
1200 /* (define_insn_reservation name default_latency condition regexpr)
1201 describes reservation of cpu functional units (the 3nd operand) for
1202 instruction which is selected by the condition (the 2nd parameter).
1203 The first parameter is used for output of debugging information.
1204 The reservations are described by a regular expression according
1205 the following syntax:
1207 regexp = regexp "," oneof
1210 oneof = oneof "|" allof
1213 allof = allof "+" repeat
1216 repeat = element "*" number
1219 element = cpu_function_unit_name
1225 1. "," is used for describing start of the next cycle in
1228 2. "|" is used for describing the reservation described by the
1229 first regular expression *or* the reservation described by the
1230 second regular expression *or* etc.
1232 3. "+" is used for describing the reservation described by the
1233 first regular expression *and* the reservation described by the
1234 second regular expression *and* etc.
1236 4. "*" is used for convenience and simply means sequence in
1237 which the regular expression are repeated NUMBER times with
1238 cycle advancing (see ",").
1240 5. cpu functional unit name which means its reservation.
1242 6. reservation name -- see define_reservation.
1244 7. string "nothing" means no units reservation. */
1246 DEF_RTL_EXPR(DEFINE_INSN_RESERVATION, "define_insn_reservation", "sies", RTX_EXTRA)
1248 /* Expressions used for insn attributes. */
1250 /* Definition of an insn attribute.
1251 1st operand: name of the attribute
1252 2nd operand: comma-separated list of possible attribute values
1253 3rd operand: expression for the default value of the attribute. */
1254 DEF_RTL_EXPR(DEFINE_ATTR, "define_attr", "sse", RTX_EXTRA)
1256 /* Definition of an insn attribute that uses an existing enumerated type.
1257 1st operand: name of the attribute
1258 2nd operand: the name of the enumerated type
1259 3rd operand: expression for the default value of the attribute. */
1260 DEF_RTL_EXPR(DEFINE_ENUM_ATTR, "define_enum_attr", "sse", RTX_EXTRA)
1262 /* Marker for the name of an attribute. */
1263 DEF_RTL_EXPR(ATTR, "attr", "s", RTX_EXTRA)
1265 /* For use in the last (optional) operand of DEFINE_INSN or DEFINE_PEEPHOLE and
1266 in DEFINE_ASM_INSN to specify an attribute to assign to insns matching that
1269 (set_attr "name" "value") is equivalent to
1270 (set (attr "name") (const_string "value")) */
1271 DEF_RTL_EXPR(SET_ATTR, "set_attr", "ss", RTX_EXTRA)
1273 /* In the last operand of DEFINE_INSN and DEFINE_PEEPHOLE, this can be used to
1274 specify that attribute values are to be assigned according to the
1275 alternative matched.
1277 The following three expressions are equivalent:
1279 (set (attr "att") (cond [(eq_attrq "alternative" "1") (const_string "a1")
1280 (eq_attrq "alternative" "2") (const_string "a2")]
1281 (const_string "a3")))
1282 (set_attr_alternative "att" [(const_string "a1") (const_string "a2")
1283 (const_string "a3")])
1284 (set_attr "att" "a1,a2,a3")
1286 DEF_RTL_EXPR(SET_ATTR_ALTERNATIVE, "set_attr_alternative", "sE", RTX_EXTRA)
1288 /* A conditional expression true if the value of the specified attribute of
1289 the current insn equals the specified value. The first operand is the
1290 attribute name and the second is the comparison value. */
1291 DEF_RTL_EXPR(EQ_ATTR, "eq_attr", "ss", RTX_EXTRA)
1293 /* A special case of the above representing a set of alternatives. The first
1294 operand is bitmap of the set, the second one is the default value. */
1295 DEF_RTL_EXPR(EQ_ATTR_ALT, "eq_attr_alt", "ii", RTX_EXTRA)
1297 /* A conditional expression which is true if the specified flag is
1298 true for the insn being scheduled in reorg.
1300 genattr.c defines the following flags which can be tested by
1301 (attr_flag "foo") expressions in eligible_for_delay: forward, backward. */
1303 DEF_RTL_EXPR (ATTR_FLAG, "attr_flag", "s", RTX_EXTRA)
1305 /* General conditional. The first operand is a vector composed of pairs of
1306 expressions. The first element of each pair is evaluated, in turn.
1307 The value of the conditional is the second expression of the first pair
1308 whose first expression evaluates nonzero. If none of the expressions is
1309 true, the second operand will be used as the value of the conditional. */
1310 DEF_RTL_EXPR(COND, "cond", "Ee", RTX_EXTRA)
1312 /* Definition of a pattern substitution meta operation on a DEFINE_EXPAND
1313 or a DEFINE_INSN. Automatically generates new instances of DEFINE_INSNs
1314 that match the substitution pattern.
1317 0: The name of the substitition template.
1318 1: Input template to match to see if a substitution is applicable.
1319 2: A C expression giving an additional condition for the generated
1320 new define_expand or define_insn.
1321 3: Output tempalate to generate via substitution.
1323 Within a DEFINE_SUBST template, the meaning of some RTL expressions is
1324 different from their usual interpretation: a MATCH_OPERAND matches any
1325 expression tree with matching machine mode or with VOIDmode. Likewise,
1326 MATCH_OP_DUP and MATCH_DUP match more liberally in a DEFINE_SUBST than
1327 in other RTL expressions. MATCH_OPERATOR matches all common operators
1328 but also UNSPEC, UNSPEC_VOLATILE, and MATCH_OPERATORS from the input
1329 DEFINE_EXPAND or DEFINE_INSN. */
1330 DEF_RTL_EXPR(DEFINE_SUBST, "define_subst", "sEsE", RTX_EXTRA)
1332 /* Substitution attribute to apply a DEFINE_SUBST to a pattern.
1335 0: The name of the subst-attribute.
1336 1: The name of the DEFINE_SUBST to be applied for this attribute.
1337 2: String to substitute for the subst-attribute name in the pattern
1338 name, for the case that the DEFINE_SUBST is not applied (i.e. the
1339 unmodified version of the pattern).
1340 3: String to substitute for the subst-attribute name in the pattern
1341 name, for the case that the DEFINE_SUBST is applied to the patten.
1343 The use of DEFINE_SUBST and DEFINE_SUBST_ATTR is explained in the
1344 GCC internals manual, under "RTL Templates Transformations". */
1345 DEF_RTL_EXPR(DEFINE_SUBST_ATTR, "define_subst_attr", "ssss", RTX_EXTRA)
1347 #endif /* GENERATOR_FILE */
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