1 /* Analyze RTL for GNU compiler.
2 Copyright (C) 1987-2019 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify it under
7 the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 3, or (at your option) any later
11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
23 #include "coretypes.h"
32 #include "insn-config.h"
34 #include "emit-rtl.h" /* FIXME: Can go away once crtl is moved to rtl.h. */
36 #include "addresses.h"
38 #include "hard-reg-set.h"
40 /* Forward declarations */
41 static void set_of_1 (rtx
, const_rtx
, void *);
42 static bool covers_regno_p (const_rtx
, unsigned int);
43 static bool covers_regno_no_parallel_p (const_rtx
, unsigned int);
44 static int computed_jump_p_1 (const_rtx
);
45 static void parms_set (rtx
, const_rtx
, void *);
47 static unsigned HOST_WIDE_INT
cached_nonzero_bits (const_rtx
, scalar_int_mode
,
48 const_rtx
, machine_mode
,
49 unsigned HOST_WIDE_INT
);
50 static unsigned HOST_WIDE_INT
nonzero_bits1 (const_rtx
, scalar_int_mode
,
51 const_rtx
, machine_mode
,
52 unsigned HOST_WIDE_INT
);
53 static unsigned int cached_num_sign_bit_copies (const_rtx
, scalar_int_mode
,
54 const_rtx
, machine_mode
,
56 static unsigned int num_sign_bit_copies1 (const_rtx
, scalar_int_mode
,
57 const_rtx
, machine_mode
,
60 rtx_subrtx_bound_info rtx_all_subrtx_bounds
[NUM_RTX_CODE
];
61 rtx_subrtx_bound_info rtx_nonconst_subrtx_bounds
[NUM_RTX_CODE
];
63 /* Truncation narrows the mode from SOURCE mode to DESTINATION mode.
64 If TARGET_MODE_REP_EXTENDED (DESTINATION, DESTINATION_REP) is
65 SIGN_EXTEND then while narrowing we also have to enforce the
66 representation and sign-extend the value to mode DESTINATION_REP.
68 If the value is already sign-extended to DESTINATION_REP mode we
69 can just switch to DESTINATION mode on it. For each pair of
70 integral modes SOURCE and DESTINATION, when truncating from SOURCE
71 to DESTINATION, NUM_SIGN_BIT_COPIES_IN_REP[SOURCE][DESTINATION]
72 contains the number of high-order bits in SOURCE that have to be
73 copies of the sign-bit so that we can do this mode-switch to
77 num_sign_bit_copies_in_rep
[MAX_MODE_INT
+ 1][MAX_MODE_INT
+ 1];
79 /* Store X into index I of ARRAY. ARRAY is known to have at least I
80 elements. Return the new base of ARRAY. */
83 typename
T::value_type
*
84 generic_subrtx_iterator
<T
>::add_single_to_queue (array_type
&array
,
86 size_t i
, value_type x
)
88 if (base
== array
.stack
)
95 gcc_checking_assert (i
== LOCAL_ELEMS
);
96 /* A previous iteration might also have moved from the stack to the
97 heap, in which case the heap array will already be big enough. */
98 if (vec_safe_length (array
.heap
) <= i
)
99 vec_safe_grow (array
.heap
, i
+ 1);
100 base
= array
.heap
->address ();
101 memcpy (base
, array
.stack
, sizeof (array
.stack
));
102 base
[LOCAL_ELEMS
] = x
;
105 unsigned int length
= array
.heap
->length ();
108 gcc_checking_assert (base
== array
.heap
->address ());
114 gcc_checking_assert (i
== length
);
115 vec_safe_push (array
.heap
, x
);
116 return array
.heap
->address ();
120 /* Add the subrtxes of X to worklist ARRAY, starting at END. Return the
121 number of elements added to the worklist. */
123 template <typename T
>
125 generic_subrtx_iterator
<T
>::add_subrtxes_to_queue (array_type
&array
,
127 size_t end
, rtx_type x
)
129 enum rtx_code code
= GET_CODE (x
);
130 const char *format
= GET_RTX_FORMAT (code
);
131 size_t orig_end
= end
;
132 if (__builtin_expect (INSN_P (x
), false))
134 /* Put the pattern at the top of the queue, since that's what
135 we're likely to want most. It also allows for the SEQUENCE
137 for (int i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; --i
)
138 if (format
[i
] == 'e')
140 value_type subx
= T::get_value (x
->u
.fld
[i
].rt_rtx
);
141 if (__builtin_expect (end
< LOCAL_ELEMS
, true))
144 base
= add_single_to_queue (array
, base
, end
++, subx
);
148 for (int i
= 0; format
[i
]; ++i
)
149 if (format
[i
] == 'e')
151 value_type subx
= T::get_value (x
->u
.fld
[i
].rt_rtx
);
152 if (__builtin_expect (end
< LOCAL_ELEMS
, true))
155 base
= add_single_to_queue (array
, base
, end
++, subx
);
157 else if (format
[i
] == 'E')
159 unsigned int length
= GET_NUM_ELEM (x
->u
.fld
[i
].rt_rtvec
);
160 rtx
*vec
= x
->u
.fld
[i
].rt_rtvec
->elem
;
161 if (__builtin_expect (end
+ length
<= LOCAL_ELEMS
, true))
162 for (unsigned int j
= 0; j
< length
; j
++)
163 base
[end
++] = T::get_value (vec
[j
]);
165 for (unsigned int j
= 0; j
< length
; j
++)
166 base
= add_single_to_queue (array
, base
, end
++,
167 T::get_value (vec
[j
]));
168 if (code
== SEQUENCE
&& end
== length
)
169 /* If the subrtxes of the sequence fill the entire array then
170 we know that no other parts of a containing insn are queued.
171 The caller is therefore iterating over the sequence as a
172 PATTERN (...), so we also want the patterns of the
174 for (unsigned int j
= 0; j
< length
; j
++)
176 typename
T::rtx_type x
= T::get_rtx (base
[j
]);
178 base
[j
] = T::get_value (PATTERN (x
));
181 return end
- orig_end
;
184 template <typename T
>
186 generic_subrtx_iterator
<T
>::free_array (array_type
&array
)
188 vec_free (array
.heap
);
191 template <typename T
>
192 const size_t generic_subrtx_iterator
<T
>::LOCAL_ELEMS
;
194 template class generic_subrtx_iterator
<const_rtx_accessor
>;
195 template class generic_subrtx_iterator
<rtx_var_accessor
>;
196 template class generic_subrtx_iterator
<rtx_ptr_accessor
>;
198 /* Return 1 if the value of X is unstable
199 (would be different at a different point in the program).
200 The frame pointer, arg pointer, etc. are considered stable
201 (within one function) and so is anything marked `unchanging'. */
204 rtx_unstable_p (const_rtx x
)
206 const RTX_CODE code
= GET_CODE (x
);
213 return !MEM_READONLY_P (x
) || rtx_unstable_p (XEXP (x
, 0));
222 /* As in rtx_varies_p, we have to use the actual rtx, not reg number. */
223 if (x
== frame_pointer_rtx
|| x
== hard_frame_pointer_rtx
224 /* The arg pointer varies if it is not a fixed register. */
225 || (x
== arg_pointer_rtx
&& fixed_regs
[ARG_POINTER_REGNUM
]))
227 /* ??? When call-clobbered, the value is stable modulo the restore
228 that must happen after a call. This currently screws up local-alloc
229 into believing that the restore is not needed. */
230 if (!PIC_OFFSET_TABLE_REG_CALL_CLOBBERED
&& x
== pic_offset_table_rtx
)
235 if (MEM_VOLATILE_P (x
))
244 fmt
= GET_RTX_FORMAT (code
);
245 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
248 if (rtx_unstable_p (XEXP (x
, i
)))
251 else if (fmt
[i
] == 'E')
254 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
255 if (rtx_unstable_p (XVECEXP (x
, i
, j
)))
262 /* Return 1 if X has a value that can vary even between two
263 executions of the program. 0 means X can be compared reliably
264 against certain constants or near-constants.
265 FOR_ALIAS is nonzero if we are called from alias analysis; if it is
266 zero, we are slightly more conservative.
267 The frame pointer and the arg pointer are considered constant. */
270 rtx_varies_p (const_rtx x
, bool for_alias
)
283 return !MEM_READONLY_P (x
) || rtx_varies_p (XEXP (x
, 0), for_alias
);
292 /* Note that we have to test for the actual rtx used for the frame
293 and arg pointers and not just the register number in case we have
294 eliminated the frame and/or arg pointer and are using it
296 if (x
== frame_pointer_rtx
|| x
== hard_frame_pointer_rtx
297 /* The arg pointer varies if it is not a fixed register. */
298 || (x
== arg_pointer_rtx
&& fixed_regs
[ARG_POINTER_REGNUM
]))
300 if (x
== pic_offset_table_rtx
301 /* ??? When call-clobbered, the value is stable modulo the restore
302 that must happen after a call. This currently screws up
303 local-alloc into believing that the restore is not needed, so we
304 must return 0 only if we are called from alias analysis. */
305 && (!PIC_OFFSET_TABLE_REG_CALL_CLOBBERED
|| for_alias
))
310 /* The operand 0 of a LO_SUM is considered constant
311 (in fact it is related specifically to operand 1)
312 during alias analysis. */
313 return (! for_alias
&& rtx_varies_p (XEXP (x
, 0), for_alias
))
314 || rtx_varies_p (XEXP (x
, 1), for_alias
);
317 if (MEM_VOLATILE_P (x
))
326 fmt
= GET_RTX_FORMAT (code
);
327 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
330 if (rtx_varies_p (XEXP (x
, i
), for_alias
))
333 else if (fmt
[i
] == 'E')
336 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
337 if (rtx_varies_p (XVECEXP (x
, i
, j
), for_alias
))
344 /* Compute an approximation for the offset between the register
345 FROM and TO for the current function, as it was at the start
349 get_initial_register_offset (int from
, int to
)
351 static const struct elim_table_t
355 } table
[] = ELIMINABLE_REGS
;
356 poly_int64 offset1
, offset2
;
362 /* It is not safe to call INITIAL_ELIMINATION_OFFSET before the epilogue
363 is completed, but we need to give at least an estimate for the stack
364 pointer based on the frame size. */
365 if (!epilogue_completed
)
367 offset1
= crtl
->outgoing_args_size
+ get_frame_size ();
368 #if !STACK_GROWS_DOWNWARD
371 if (to
== STACK_POINTER_REGNUM
)
373 else if (from
== STACK_POINTER_REGNUM
)
379 for (i
= 0; i
< ARRAY_SIZE (table
); i
++)
380 if (table
[i
].from
== from
)
382 if (table
[i
].to
== to
)
384 INITIAL_ELIMINATION_OFFSET (table
[i
].from
, table
[i
].to
,
388 for (j
= 0; j
< ARRAY_SIZE (table
); j
++)
390 if (table
[j
].to
== to
391 && table
[j
].from
== table
[i
].to
)
393 INITIAL_ELIMINATION_OFFSET (table
[i
].from
, table
[i
].to
,
395 INITIAL_ELIMINATION_OFFSET (table
[j
].from
, table
[j
].to
,
397 return offset1
+ offset2
;
399 if (table
[j
].from
== to
400 && table
[j
].to
== table
[i
].to
)
402 INITIAL_ELIMINATION_OFFSET (table
[i
].from
, table
[i
].to
,
404 INITIAL_ELIMINATION_OFFSET (table
[j
].from
, table
[j
].to
,
406 return offset1
- offset2
;
410 else if (table
[i
].to
== from
)
412 if (table
[i
].from
== to
)
414 INITIAL_ELIMINATION_OFFSET (table
[i
].from
, table
[i
].to
,
418 for (j
= 0; j
< ARRAY_SIZE (table
); j
++)
420 if (table
[j
].to
== to
421 && table
[j
].from
== table
[i
].from
)
423 INITIAL_ELIMINATION_OFFSET (table
[i
].from
, table
[i
].to
,
425 INITIAL_ELIMINATION_OFFSET (table
[j
].from
, table
[j
].to
,
427 return - offset1
+ offset2
;
429 if (table
[j
].from
== to
430 && table
[j
].to
== table
[i
].from
)
432 INITIAL_ELIMINATION_OFFSET (table
[i
].from
, table
[i
].to
,
434 INITIAL_ELIMINATION_OFFSET (table
[j
].from
, table
[j
].to
,
436 return - offset1
- offset2
;
441 /* If the requested register combination was not found,
442 try a different more simple combination. */
443 if (from
== ARG_POINTER_REGNUM
)
444 return get_initial_register_offset (HARD_FRAME_POINTER_REGNUM
, to
);
445 else if (to
== ARG_POINTER_REGNUM
)
446 return get_initial_register_offset (from
, HARD_FRAME_POINTER_REGNUM
);
447 else if (from
== HARD_FRAME_POINTER_REGNUM
)
448 return get_initial_register_offset (FRAME_POINTER_REGNUM
, to
);
449 else if (to
== HARD_FRAME_POINTER_REGNUM
)
450 return get_initial_register_offset (from
, FRAME_POINTER_REGNUM
);
455 /* Return nonzero if the use of X+OFFSET as an address in a MEM with SIZE
456 bytes can cause a trap. MODE is the mode of the MEM (not that of X) and
457 UNALIGNED_MEMS controls whether nonzero is returned for unaligned memory
458 references on strict alignment machines. */
461 rtx_addr_can_trap_p_1 (const_rtx x
, poly_int64 offset
, poly_int64 size
,
462 machine_mode mode
, bool unaligned_mems
)
464 enum rtx_code code
= GET_CODE (x
);
465 gcc_checking_assert (mode
== BLKmode
|| known_size_p (size
));
468 /* The offset must be a multiple of the mode size if we are considering
469 unaligned memory references on strict alignment machines. */
470 if (STRICT_ALIGNMENT
&& unaligned_mems
&& mode
!= BLKmode
)
472 poly_int64 actual_offset
= offset
;
474 #ifdef SPARC_STACK_BOUNDARY_HACK
475 /* ??? The SPARC port may claim a STACK_BOUNDARY higher than
476 the real alignment of %sp. However, when it does this, the
477 alignment of %sp+STACK_POINTER_OFFSET is STACK_BOUNDARY. */
478 if (SPARC_STACK_BOUNDARY_HACK
479 && (x
== stack_pointer_rtx
|| x
== hard_frame_pointer_rtx
))
480 actual_offset
-= STACK_POINTER_OFFSET
;
483 if (!multiple_p (actual_offset
, GET_MODE_SIZE (mode
)))
490 if (SYMBOL_REF_WEAK (x
))
492 if (!CONSTANT_POOL_ADDRESS_P (x
) && !SYMBOL_REF_FUNCTION_P (x
))
495 poly_int64 decl_size
;
497 if (maybe_lt (offset
, 0))
499 if (!known_size_p (size
))
500 return maybe_ne (offset
, 0);
502 /* If the size of the access or of the symbol is unknown,
504 decl
= SYMBOL_REF_DECL (x
);
506 /* Else check that the access is in bounds. TODO: restructure
507 expr_size/tree_expr_size/int_expr_size and just use the latter. */
510 else if (DECL_P (decl
) && DECL_SIZE_UNIT (decl
))
512 if (!poly_int_tree_p (DECL_SIZE_UNIT (decl
), &decl_size
))
515 else if (TREE_CODE (decl
) == STRING_CST
)
516 decl_size
= TREE_STRING_LENGTH (decl
);
517 else if (TYPE_SIZE_UNIT (TREE_TYPE (decl
)))
518 decl_size
= int_size_in_bytes (TREE_TYPE (decl
));
522 return (!known_size_p (decl_size
) || known_eq (decl_size
, 0)
523 ? maybe_ne (offset
, 0)
524 : !known_subrange_p (offset
, size
, 0, decl_size
));
533 /* Stack references are assumed not to trap, but we need to deal with
534 nonsensical offsets. */
535 if (x
== frame_pointer_rtx
|| x
== hard_frame_pointer_rtx
536 || x
== stack_pointer_rtx
537 /* The arg pointer varies if it is not a fixed register. */
538 || (x
== arg_pointer_rtx
&& fixed_regs
[ARG_POINTER_REGNUM
]))
541 poly_int64 red_zone_size
= RED_ZONE_SIZE
;
543 poly_int64 red_zone_size
= 0;
545 poly_int64 stack_boundary
= PREFERRED_STACK_BOUNDARY
/ BITS_PER_UNIT
;
546 poly_int64 low_bound
, high_bound
;
548 if (!known_size_p (size
))
551 if (x
== frame_pointer_rtx
)
553 if (FRAME_GROWS_DOWNWARD
)
555 high_bound
= targetm
.starting_frame_offset ();
556 low_bound
= high_bound
- get_frame_size ();
560 low_bound
= targetm
.starting_frame_offset ();
561 high_bound
= low_bound
+ get_frame_size ();
564 else if (x
== hard_frame_pointer_rtx
)
567 = get_initial_register_offset (STACK_POINTER_REGNUM
,
568 HARD_FRAME_POINTER_REGNUM
);
570 = get_initial_register_offset (ARG_POINTER_REGNUM
,
571 HARD_FRAME_POINTER_REGNUM
);
573 #if STACK_GROWS_DOWNWARD
574 low_bound
= sp_offset
- red_zone_size
- stack_boundary
;
575 high_bound
= ap_offset
576 + FIRST_PARM_OFFSET (current_function_decl
)
577 #if !ARGS_GROW_DOWNWARD
582 high_bound
= sp_offset
+ red_zone_size
+ stack_boundary
;
583 low_bound
= ap_offset
584 + FIRST_PARM_OFFSET (current_function_decl
)
585 #if ARGS_GROW_DOWNWARD
591 else if (x
== stack_pointer_rtx
)
594 = get_initial_register_offset (ARG_POINTER_REGNUM
,
595 STACK_POINTER_REGNUM
);
597 #if STACK_GROWS_DOWNWARD
598 low_bound
= - red_zone_size
- stack_boundary
;
599 high_bound
= ap_offset
600 + FIRST_PARM_OFFSET (current_function_decl
)
601 #if !ARGS_GROW_DOWNWARD
606 high_bound
= red_zone_size
+ stack_boundary
;
607 low_bound
= ap_offset
608 + FIRST_PARM_OFFSET (current_function_decl
)
609 #if ARGS_GROW_DOWNWARD
617 /* We assume that accesses are safe to at least the
619 Examples are varargs and __builtin_return_address. */
620 #if ARGS_GROW_DOWNWARD
621 high_bound
= FIRST_PARM_OFFSET (current_function_decl
)
623 low_bound
= FIRST_PARM_OFFSET (current_function_decl
)
624 - crtl
->args
.size
- stack_boundary
;
626 low_bound
= FIRST_PARM_OFFSET (current_function_decl
)
628 high_bound
= FIRST_PARM_OFFSET (current_function_decl
)
629 + crtl
->args
.size
+ stack_boundary
;
633 if (known_ge (offset
, low_bound
)
634 && known_le (offset
, high_bound
- size
))
638 /* All of the virtual frame registers are stack references. */
639 if (REGNO (x
) >= FIRST_VIRTUAL_REGISTER
640 && REGNO (x
) <= LAST_VIRTUAL_REGISTER
)
645 return rtx_addr_can_trap_p_1 (XEXP (x
, 0), offset
, size
,
646 mode
, unaligned_mems
);
649 /* An address is assumed not to trap if:
650 - it is the pic register plus a const unspec without offset. */
651 if (XEXP (x
, 0) == pic_offset_table_rtx
652 && GET_CODE (XEXP (x
, 1)) == CONST
653 && GET_CODE (XEXP (XEXP (x
, 1), 0)) == UNSPEC
654 && known_eq (offset
, 0))
657 /* - or it is an address that can't trap plus a constant integer. */
658 if (poly_int_rtx_p (XEXP (x
, 1), &const_x1
)
659 && !rtx_addr_can_trap_p_1 (XEXP (x
, 0), offset
+ const_x1
,
660 size
, mode
, unaligned_mems
))
667 return rtx_addr_can_trap_p_1 (XEXP (x
, 1), offset
, size
,
668 mode
, unaligned_mems
);
675 return rtx_addr_can_trap_p_1 (XEXP (x
, 0), offset
, size
,
676 mode
, unaligned_mems
);
682 /* If it isn't one of the case above, it can cause a trap. */
686 /* Return nonzero if the use of X as an address in a MEM can cause a trap. */
689 rtx_addr_can_trap_p (const_rtx x
)
691 return rtx_addr_can_trap_p_1 (x
, 0, -1, BLKmode
, false);
694 /* Return true if X contains a MEM subrtx. */
697 contains_mem_rtx_p (rtx x
)
699 subrtx_iterator::array_type array
;
700 FOR_EACH_SUBRTX (iter
, array
, x
, ALL
)
707 /* Return true if X is an address that is known to not be zero. */
710 nonzero_address_p (const_rtx x
)
712 const enum rtx_code code
= GET_CODE (x
);
717 return flag_delete_null_pointer_checks
&& !SYMBOL_REF_WEAK (x
);
723 /* As in rtx_varies_p, we have to use the actual rtx, not reg number. */
724 if (x
== frame_pointer_rtx
|| x
== hard_frame_pointer_rtx
725 || x
== stack_pointer_rtx
726 || (x
== arg_pointer_rtx
&& fixed_regs
[ARG_POINTER_REGNUM
]))
728 /* All of the virtual frame registers are stack references. */
729 if (REGNO (x
) >= FIRST_VIRTUAL_REGISTER
730 && REGNO (x
) <= LAST_VIRTUAL_REGISTER
)
735 return nonzero_address_p (XEXP (x
, 0));
738 /* Handle PIC references. */
739 if (XEXP (x
, 0) == pic_offset_table_rtx
740 && CONSTANT_P (XEXP (x
, 1)))
745 /* Similar to the above; allow positive offsets. Further, since
746 auto-inc is only allowed in memories, the register must be a
748 if (CONST_INT_P (XEXP (x
, 1))
749 && INTVAL (XEXP (x
, 1)) > 0)
751 return nonzero_address_p (XEXP (x
, 0));
754 /* Similarly. Further, the offset is always positive. */
761 return nonzero_address_p (XEXP (x
, 0));
764 return nonzero_address_p (XEXP (x
, 1));
770 /* If it isn't one of the case above, might be zero. */
774 /* Return 1 if X refers to a memory location whose address
775 cannot be compared reliably with constant addresses,
776 or if X refers to a BLKmode memory object.
777 FOR_ALIAS is nonzero if we are called from alias analysis; if it is
778 zero, we are slightly more conservative. */
781 rtx_addr_varies_p (const_rtx x
, bool for_alias
)
792 return GET_MODE (x
) == BLKmode
|| rtx_varies_p (XEXP (x
, 0), for_alias
);
794 fmt
= GET_RTX_FORMAT (code
);
795 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
798 if (rtx_addr_varies_p (XEXP (x
, i
), for_alias
))
801 else if (fmt
[i
] == 'E')
804 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
805 if (rtx_addr_varies_p (XVECEXP (x
, i
, j
), for_alias
))
811 /* Return the CALL in X if there is one. */
814 get_call_rtx_from (const rtx_insn
*insn
)
816 rtx x
= PATTERN (insn
);
817 if (GET_CODE (x
) == PARALLEL
)
818 x
= XVECEXP (x
, 0, 0);
819 if (GET_CODE (x
) == SET
)
821 if (GET_CODE (x
) == CALL
&& MEM_P (XEXP (x
, 0)))
826 /* Get the declaration of the function called by INSN. */
829 get_call_fndecl (const rtx_insn
*insn
)
833 note
= find_reg_note (insn
, REG_CALL_DECL
, NULL_RTX
);
834 if (note
== NULL_RTX
)
837 datum
= XEXP (note
, 0);
838 if (datum
!= NULL_RTX
)
839 return SYMBOL_REF_DECL (datum
);
844 /* Return the value of the integer term in X, if one is apparent;
846 Only obvious integer terms are detected.
847 This is used in cse.c with the `related_value' field. */
850 get_integer_term (const_rtx x
)
852 if (GET_CODE (x
) == CONST
)
855 if (GET_CODE (x
) == MINUS
856 && CONST_INT_P (XEXP (x
, 1)))
857 return - INTVAL (XEXP (x
, 1));
858 if (GET_CODE (x
) == PLUS
859 && CONST_INT_P (XEXP (x
, 1)))
860 return INTVAL (XEXP (x
, 1));
864 /* If X is a constant, return the value sans apparent integer term;
866 Only obvious integer terms are detected. */
869 get_related_value (const_rtx x
)
871 if (GET_CODE (x
) != CONST
)
874 if (GET_CODE (x
) == PLUS
875 && CONST_INT_P (XEXP (x
, 1)))
877 else if (GET_CODE (x
) == MINUS
878 && CONST_INT_P (XEXP (x
, 1)))
883 /* Return true if SYMBOL is a SYMBOL_REF and OFFSET + SYMBOL points
884 to somewhere in the same object or object_block as SYMBOL. */
887 offset_within_block_p (const_rtx symbol
, HOST_WIDE_INT offset
)
891 if (GET_CODE (symbol
) != SYMBOL_REF
)
899 if (CONSTANT_POOL_ADDRESS_P (symbol
)
900 && offset
< (int) GET_MODE_SIZE (get_pool_mode (symbol
)))
903 decl
= SYMBOL_REF_DECL (symbol
);
904 if (decl
&& offset
< int_size_in_bytes (TREE_TYPE (decl
)))
908 if (SYMBOL_REF_HAS_BLOCK_INFO_P (symbol
)
909 && SYMBOL_REF_BLOCK (symbol
)
910 && SYMBOL_REF_BLOCK_OFFSET (symbol
) >= 0
911 && ((unsigned HOST_WIDE_INT
) offset
+ SYMBOL_REF_BLOCK_OFFSET (symbol
)
912 < (unsigned HOST_WIDE_INT
) SYMBOL_REF_BLOCK (symbol
)->size
))
918 /* Split X into a base and a constant offset, storing them in *BASE_OUT
919 and *OFFSET_OUT respectively. */
922 split_const (rtx x
, rtx
*base_out
, rtx
*offset_out
)
924 if (GET_CODE (x
) == CONST
)
927 if (GET_CODE (x
) == PLUS
&& CONST_INT_P (XEXP (x
, 1)))
929 *base_out
= XEXP (x
, 0);
930 *offset_out
= XEXP (x
, 1);
935 *offset_out
= const0_rtx
;
938 /* Express integer value X as some value Y plus a polynomial offset,
939 where Y is either const0_rtx, X or something within X (as opposed
940 to a new rtx). Return the Y and store the offset in *OFFSET_OUT. */
943 strip_offset (rtx x
, poly_int64_pod
*offset_out
)
945 rtx base
= const0_rtx
;
947 if (GET_CODE (test
) == CONST
)
948 test
= XEXP (test
, 0);
949 if (GET_CODE (test
) == PLUS
)
951 base
= XEXP (test
, 0);
952 test
= XEXP (test
, 1);
954 if (poly_int_rtx_p (test
, offset_out
))
960 /* Return the argument size in REG_ARGS_SIZE note X. */
963 get_args_size (const_rtx x
)
965 gcc_checking_assert (REG_NOTE_KIND (x
) == REG_ARGS_SIZE
);
966 return rtx_to_poly_int64 (XEXP (x
, 0));
969 /* Return the number of places FIND appears within X. If COUNT_DEST is
970 zero, we do not count occurrences inside the destination of a SET. */
973 count_occurrences (const_rtx x
, const_rtx find
, int count_dest
)
977 const char *format_ptr
;
996 count
= count_occurrences (XEXP (x
, 0), find
, count_dest
);
998 count
+= count_occurrences (XEXP (x
, 1), find
, count_dest
);
1002 if (MEM_P (find
) && rtx_equal_p (x
, find
))
1007 if (SET_DEST (x
) == find
&& ! count_dest
)
1008 return count_occurrences (SET_SRC (x
), find
, count_dest
);
1015 format_ptr
= GET_RTX_FORMAT (code
);
1018 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++)
1020 switch (*format_ptr
++)
1023 count
+= count_occurrences (XEXP (x
, i
), find
, count_dest
);
1027 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
1028 count
+= count_occurrences (XVECEXP (x
, i
, j
), find
, count_dest
);
1036 /* Return TRUE if OP is a register or subreg of a register that
1037 holds an unsigned quantity. Otherwise, return FALSE. */
1040 unsigned_reg_p (rtx op
)
1044 && TYPE_UNSIGNED (TREE_TYPE (REG_EXPR (op
))))
1047 if (GET_CODE (op
) == SUBREG
1048 && SUBREG_PROMOTED_SIGN (op
))
1055 /* Nonzero if register REG appears somewhere within IN.
1056 Also works if REG is not a register; in this case it checks
1057 for a subexpression of IN that is Lisp "equal" to REG. */
1060 reg_mentioned_p (const_rtx reg
, const_rtx in
)
1072 if (GET_CODE (in
) == LABEL_REF
)
1073 return reg
== label_ref_label (in
);
1075 code
= GET_CODE (in
);
1079 /* Compare registers by number. */
1081 return REG_P (reg
) && REGNO (in
) == REGNO (reg
);
1083 /* These codes have no constituent expressions
1091 /* These are kept unique for a given value. */
1098 if (GET_CODE (reg
) == code
&& rtx_equal_p (reg
, in
))
1101 fmt
= GET_RTX_FORMAT (code
);
1103 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
1108 for (j
= XVECLEN (in
, i
) - 1; j
>= 0; j
--)
1109 if (reg_mentioned_p (reg
, XVECEXP (in
, i
, j
)))
1112 else if (fmt
[i
] == 'e'
1113 && reg_mentioned_p (reg
, XEXP (in
, i
)))
1119 /* Return 1 if in between BEG and END, exclusive of BEG and END, there is
1120 no CODE_LABEL insn. */
1123 no_labels_between_p (const rtx_insn
*beg
, const rtx_insn
*end
)
1128 for (p
= NEXT_INSN (beg
); p
!= end
; p
= NEXT_INSN (p
))
1134 /* Nonzero if register REG is used in an insn between
1135 FROM_INSN and TO_INSN (exclusive of those two). */
1138 reg_used_between_p (const_rtx reg
, const rtx_insn
*from_insn
,
1139 const rtx_insn
*to_insn
)
1143 if (from_insn
== to_insn
)
1146 for (insn
= NEXT_INSN (from_insn
); insn
!= to_insn
; insn
= NEXT_INSN (insn
))
1147 if (NONDEBUG_INSN_P (insn
)
1148 && (reg_overlap_mentioned_p (reg
, PATTERN (insn
))
1149 || (CALL_P (insn
) && find_reg_fusage (insn
, USE
, reg
))))
1154 /* Nonzero if the old value of X, a register, is referenced in BODY. If X
1155 is entirely replaced by a new value and the only use is as a SET_DEST,
1156 we do not consider it a reference. */
1159 reg_referenced_p (const_rtx x
, const_rtx body
)
1163 switch (GET_CODE (body
))
1166 if (reg_overlap_mentioned_p (x
, SET_SRC (body
)))
1169 /* If the destination is anything other than CC0, PC, a REG or a SUBREG
1170 of a REG that occupies all of the REG, the insn references X if
1171 it is mentioned in the destination. */
1172 if (GET_CODE (SET_DEST (body
)) != CC0
1173 && GET_CODE (SET_DEST (body
)) != PC
1174 && !REG_P (SET_DEST (body
))
1175 && ! (GET_CODE (SET_DEST (body
)) == SUBREG
1176 && REG_P (SUBREG_REG (SET_DEST (body
)))
1177 && !read_modify_subreg_p (SET_DEST (body
)))
1178 && reg_overlap_mentioned_p (x
, SET_DEST (body
)))
1183 for (i
= ASM_OPERANDS_INPUT_LENGTH (body
) - 1; i
>= 0; i
--)
1184 if (reg_overlap_mentioned_p (x
, ASM_OPERANDS_INPUT (body
, i
)))
1191 return reg_overlap_mentioned_p (x
, body
);
1194 return reg_overlap_mentioned_p (x
, TRAP_CONDITION (body
));
1197 return reg_overlap_mentioned_p (x
, XEXP (body
, 0));
1200 case UNSPEC_VOLATILE
:
1201 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; i
--)
1202 if (reg_overlap_mentioned_p (x
, XVECEXP (body
, 0, i
)))
1207 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; i
--)
1208 if (reg_referenced_p (x
, XVECEXP (body
, 0, i
)))
1213 if (MEM_P (XEXP (body
, 0)))
1214 if (reg_overlap_mentioned_p (x
, XEXP (XEXP (body
, 0), 0)))
1219 gcc_assert (REG_P (XEXP (body
, 0)));
1223 if (reg_overlap_mentioned_p (x
, COND_EXEC_TEST (body
)))
1225 return reg_referenced_p (x
, COND_EXEC_CODE (body
));
1232 /* Nonzero if register REG is set or clobbered in an insn between
1233 FROM_INSN and TO_INSN (exclusive of those two). */
1236 reg_set_between_p (const_rtx reg
, const rtx_insn
*from_insn
,
1237 const rtx_insn
*to_insn
)
1239 const rtx_insn
*insn
;
1241 if (from_insn
== to_insn
)
1244 for (insn
= NEXT_INSN (from_insn
); insn
!= to_insn
; insn
= NEXT_INSN (insn
))
1245 if (INSN_P (insn
) && reg_set_p (reg
, insn
))
1250 /* Return true if REG is set or clobbered inside INSN. */
1253 reg_set_p (const_rtx reg
, const_rtx insn
)
1255 /* After delay slot handling, call and branch insns might be in a
1256 sequence. Check all the elements there. */
1257 if (INSN_P (insn
) && GET_CODE (PATTERN (insn
)) == SEQUENCE
)
1259 for (int i
= 0; i
< XVECLEN (PATTERN (insn
), 0); ++i
)
1260 if (reg_set_p (reg
, XVECEXP (PATTERN (insn
), 0, i
)))
1266 /* We can be passed an insn or part of one. If we are passed an insn,
1267 check if a side-effect of the insn clobbers REG. */
1269 && (FIND_REG_INC_NOTE (insn
, reg
)
1272 && REGNO (reg
) < FIRST_PSEUDO_REGISTER
1273 && overlaps_hard_reg_set_p (regs_invalidated_by_call
,
1274 GET_MODE (reg
), REGNO (reg
)))
1276 || find_reg_fusage (insn
, CLOBBER
, reg
)))))
1279 /* There are no REG_INC notes for SP autoinc. */
1280 if (reg
== stack_pointer_rtx
&& INSN_P (insn
))
1282 subrtx_var_iterator::array_type array
;
1283 FOR_EACH_SUBRTX_VAR (iter
, array
, PATTERN (insn
), NONCONST
)
1288 && GET_RTX_CLASS (GET_CODE (XEXP (mem
, 0))) == RTX_AUTOINC
)
1290 if (XEXP (XEXP (mem
, 0), 0) == stack_pointer_rtx
)
1292 iter
.skip_subrtxes ();
1297 return set_of (reg
, insn
) != NULL_RTX
;
1300 /* Similar to reg_set_between_p, but check all registers in X. Return 0
1301 only if none of them are modified between START and END. Return 1 if
1302 X contains a MEM; this routine does use memory aliasing. */
1305 modified_between_p (const_rtx x
, const rtx_insn
*start
, const rtx_insn
*end
)
1307 const enum rtx_code code
= GET_CODE (x
);
1328 if (modified_between_p (XEXP (x
, 0), start
, end
))
1330 if (MEM_READONLY_P (x
))
1332 for (insn
= NEXT_INSN (start
); insn
!= end
; insn
= NEXT_INSN (insn
))
1333 if (memory_modified_in_insn_p (x
, insn
))
1338 return reg_set_between_p (x
, start
, end
);
1344 fmt
= GET_RTX_FORMAT (code
);
1345 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
1347 if (fmt
[i
] == 'e' && modified_between_p (XEXP (x
, i
), start
, end
))
1350 else if (fmt
[i
] == 'E')
1351 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
1352 if (modified_between_p (XVECEXP (x
, i
, j
), start
, end
))
1359 /* Similar to reg_set_p, but check all registers in X. Return 0 only if none
1360 of them are modified in INSN. Return 1 if X contains a MEM; this routine
1361 does use memory aliasing. */
1364 modified_in_p (const_rtx x
, const_rtx insn
)
1366 const enum rtx_code code
= GET_CODE (x
);
1383 if (modified_in_p (XEXP (x
, 0), insn
))
1385 if (MEM_READONLY_P (x
))
1387 if (memory_modified_in_insn_p (x
, insn
))
1392 return reg_set_p (x
, insn
);
1398 fmt
= GET_RTX_FORMAT (code
);
1399 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
1401 if (fmt
[i
] == 'e' && modified_in_p (XEXP (x
, i
), insn
))
1404 else if (fmt
[i
] == 'E')
1405 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
1406 if (modified_in_p (XVECEXP (x
, i
, j
), insn
))
1413 /* Return true if X is a SUBREG and if storing a value to X would
1414 preserve some of its SUBREG_REG. For example, on a normal 32-bit
1415 target, using a SUBREG to store to one half of a DImode REG would
1416 preserve the other half. */
1419 read_modify_subreg_p (const_rtx x
)
1421 if (GET_CODE (x
) != SUBREG
)
1423 poly_uint64 isize
= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
)));
1424 poly_uint64 osize
= GET_MODE_SIZE (GET_MODE (x
));
1425 poly_uint64 regsize
= REGMODE_NATURAL_SIZE (GET_MODE (SUBREG_REG (x
)));
1426 /* The inner and outer modes of a subreg must be ordered, so that we
1427 can tell whether they're paradoxical or partial. */
1428 gcc_checking_assert (ordered_p (isize
, osize
));
1429 return (maybe_gt (isize
, osize
) && maybe_gt (isize
, regsize
));
1432 /* Helper function for set_of. */
1440 set_of_1 (rtx x
, const_rtx pat
, void *data1
)
1442 struct set_of_data
*const data
= (struct set_of_data
*) (data1
);
1443 if (rtx_equal_p (x
, data
->pat
)
1444 || (GET_CODE (pat
) == CLOBBER_HIGH
1445 && REGNO(data
->pat
) == REGNO(XEXP (pat
, 0))
1446 && reg_is_clobbered_by_clobber_high (data
->pat
, XEXP (pat
, 0)))
1447 || (GET_CODE (pat
) != CLOBBER_HIGH
&& !MEM_P (x
)
1448 && reg_overlap_mentioned_p (data
->pat
, x
)))
1452 /* Give an INSN, return a SET or CLOBBER expression that does modify PAT
1453 (either directly or via STRICT_LOW_PART and similar modifiers). */
1455 set_of (const_rtx pat
, const_rtx insn
)
1457 struct set_of_data data
;
1458 data
.found
= NULL_RTX
;
1460 note_pattern_stores (INSN_P (insn
) ? PATTERN (insn
) : insn
, set_of_1
, &data
);
1464 /* Add all hard register in X to *PSET. */
1466 find_all_hard_regs (const_rtx x
, HARD_REG_SET
*pset
)
1468 subrtx_iterator::array_type array
;
1469 FOR_EACH_SUBRTX (iter
, array
, x
, NONCONST
)
1471 const_rtx x
= *iter
;
1472 if (REG_P (x
) && REGNO (x
) < FIRST_PSEUDO_REGISTER
)
1473 add_to_hard_reg_set (pset
, GET_MODE (x
), REGNO (x
));
1477 /* This function, called through note_stores, collects sets and
1478 clobbers of hard registers in a HARD_REG_SET, which is pointed to
1481 record_hard_reg_sets (rtx x
, const_rtx pat ATTRIBUTE_UNUSED
, void *data
)
1483 HARD_REG_SET
*pset
= (HARD_REG_SET
*)data
;
1484 if (REG_P (x
) && HARD_REGISTER_P (x
))
1485 add_to_hard_reg_set (pset
, GET_MODE (x
), REGNO (x
));
1488 /* Examine INSN, and compute the set of hard registers written by it.
1489 Store it in *PSET. Should only be called after reload. */
1491 find_all_hard_reg_sets (const rtx_insn
*insn
, HARD_REG_SET
*pset
, bool implicit
)
1495 CLEAR_HARD_REG_SET (*pset
);
1496 note_stores (insn
, record_hard_reg_sets
, pset
);
1497 if (CALL_P (insn
) && implicit
)
1498 *pset
|= call_used_or_fixed_regs
;
1499 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
1500 if (REG_NOTE_KIND (link
) == REG_INC
)
1501 record_hard_reg_sets (XEXP (link
, 0), NULL
, pset
);
1504 /* Like record_hard_reg_sets, but called through note_uses. */
1506 record_hard_reg_uses (rtx
*px
, void *data
)
1508 find_all_hard_regs (*px
, (HARD_REG_SET
*) data
);
1511 /* Given an INSN, return a SET expression if this insn has only a single SET.
1512 It may also have CLOBBERs, USEs, or SET whose output
1513 will not be used, which we ignore. */
1516 single_set_2 (const rtx_insn
*insn
, const_rtx pat
)
1519 int set_verified
= 1;
1522 if (GET_CODE (pat
) == PARALLEL
)
1524 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
1526 rtx sub
= XVECEXP (pat
, 0, i
);
1527 switch (GET_CODE (sub
))
1535 /* We can consider insns having multiple sets, where all
1536 but one are dead as single set insns. In common case
1537 only single set is present in the pattern so we want
1538 to avoid checking for REG_UNUSED notes unless necessary.
1540 When we reach set first time, we just expect this is
1541 the single set we are looking for and only when more
1542 sets are found in the insn, we check them. */
1545 if (find_reg_note (insn
, REG_UNUSED
, SET_DEST (set
))
1546 && !side_effects_p (set
))
1552 set
= sub
, set_verified
= 0;
1553 else if (!find_reg_note (insn
, REG_UNUSED
, SET_DEST (sub
))
1554 || side_effects_p (sub
))
1566 /* Given an INSN, return nonzero if it has more than one SET, else return
1570 multiple_sets (const_rtx insn
)
1575 /* INSN must be an insn. */
1576 if (! INSN_P (insn
))
1579 /* Only a PARALLEL can have multiple SETs. */
1580 if (GET_CODE (PATTERN (insn
)) == PARALLEL
)
1582 for (i
= 0, found
= 0; i
< XVECLEN (PATTERN (insn
), 0); i
++)
1583 if (GET_CODE (XVECEXP (PATTERN (insn
), 0, i
)) == SET
)
1585 /* If we have already found a SET, then return now. */
1593 /* Either zero or one SET. */
1597 /* Return nonzero if the destination of SET equals the source
1598 and there are no side effects. */
1601 set_noop_p (const_rtx set
)
1603 rtx src
= SET_SRC (set
);
1604 rtx dst
= SET_DEST (set
);
1606 if (dst
== pc_rtx
&& src
== pc_rtx
)
1609 if (MEM_P (dst
) && MEM_P (src
))
1610 return rtx_equal_p (dst
, src
) && !side_effects_p (dst
);
1612 if (GET_CODE (dst
) == ZERO_EXTRACT
)
1613 return rtx_equal_p (XEXP (dst
, 0), src
)
1614 && !BITS_BIG_ENDIAN
&& XEXP (dst
, 2) == const0_rtx
1615 && !side_effects_p (src
);
1617 if (GET_CODE (dst
) == STRICT_LOW_PART
)
1618 dst
= XEXP (dst
, 0);
1620 if (GET_CODE (src
) == SUBREG
&& GET_CODE (dst
) == SUBREG
)
1622 if (maybe_ne (SUBREG_BYTE (src
), SUBREG_BYTE (dst
)))
1624 src
= SUBREG_REG (src
);
1625 dst
= SUBREG_REG (dst
);
1628 /* It is a NOOP if destination overlaps with selected src vector
1630 if (GET_CODE (src
) == VEC_SELECT
1631 && REG_P (XEXP (src
, 0)) && REG_P (dst
)
1632 && HARD_REGISTER_P (XEXP (src
, 0))
1633 && HARD_REGISTER_P (dst
))
1636 rtx par
= XEXP (src
, 1);
1637 rtx src0
= XEXP (src
, 0);
1638 poly_int64 c0
= rtx_to_poly_int64 (XVECEXP (par
, 0, 0));
1639 poly_int64 offset
= GET_MODE_UNIT_SIZE (GET_MODE (src0
)) * c0
;
1641 for (i
= 1; i
< XVECLEN (par
, 0); i
++)
1642 if (maybe_ne (rtx_to_poly_int64 (XVECEXP (par
, 0, i
)), c0
+ i
))
1645 REG_CAN_CHANGE_MODE_P (REGNO (dst
), GET_MODE (src0
), GET_MODE (dst
))
1646 && simplify_subreg_regno (REGNO (src0
), GET_MODE (src0
),
1647 offset
, GET_MODE (dst
)) == (int) REGNO (dst
);
1650 return (REG_P (src
) && REG_P (dst
)
1651 && REGNO (src
) == REGNO (dst
));
1654 /* Return nonzero if an insn consists only of SETs, each of which only sets a
1658 noop_move_p (const rtx_insn
*insn
)
1660 rtx pat
= PATTERN (insn
);
1662 if (INSN_CODE (insn
) == NOOP_MOVE_INSN_CODE
)
1665 /* Insns carrying these notes are useful later on. */
1666 if (find_reg_note (insn
, REG_EQUAL
, NULL_RTX
))
1669 /* Check the code to be executed for COND_EXEC. */
1670 if (GET_CODE (pat
) == COND_EXEC
)
1671 pat
= COND_EXEC_CODE (pat
);
1673 if (GET_CODE (pat
) == SET
&& set_noop_p (pat
))
1676 if (GET_CODE (pat
) == PARALLEL
)
1679 /* If nothing but SETs of registers to themselves,
1680 this insn can also be deleted. */
1681 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
1683 rtx tem
= XVECEXP (pat
, 0, i
);
1685 if (GET_CODE (tem
) == USE
1686 || GET_CODE (tem
) == CLOBBER
1687 || GET_CODE (tem
) == CLOBBER_HIGH
)
1690 if (GET_CODE (tem
) != SET
|| ! set_noop_p (tem
))
1700 /* Return nonzero if register in range [REGNO, ENDREGNO)
1701 appears either explicitly or implicitly in X
1702 other than being stored into.
1704 References contained within the substructure at LOC do not count.
1705 LOC may be zero, meaning don't ignore anything. */
1708 refers_to_regno_p (unsigned int regno
, unsigned int endregno
, const_rtx x
,
1712 unsigned int x_regno
;
1717 /* The contents of a REG_NONNEG note is always zero, so we must come here
1718 upon repeat in case the last REG_NOTE is a REG_NONNEG note. */
1722 code
= GET_CODE (x
);
1727 x_regno
= REGNO (x
);
1729 /* If we modifying the stack, frame, or argument pointer, it will
1730 clobber a virtual register. In fact, we could be more precise,
1731 but it isn't worth it. */
1732 if ((x_regno
== STACK_POINTER_REGNUM
1733 || (FRAME_POINTER_REGNUM
!= ARG_POINTER_REGNUM
1734 && x_regno
== ARG_POINTER_REGNUM
)
1735 || x_regno
== FRAME_POINTER_REGNUM
)
1736 && regno
>= FIRST_VIRTUAL_REGISTER
&& regno
<= LAST_VIRTUAL_REGISTER
)
1739 return endregno
> x_regno
&& regno
< END_REGNO (x
);
1742 /* If this is a SUBREG of a hard reg, we can see exactly which
1743 registers are being modified. Otherwise, handle normally. */
1744 if (REG_P (SUBREG_REG (x
))
1745 && REGNO (SUBREG_REG (x
)) < FIRST_PSEUDO_REGISTER
)
1747 unsigned int inner_regno
= subreg_regno (x
);
1748 unsigned int inner_endregno
1749 = inner_regno
+ (inner_regno
< FIRST_PSEUDO_REGISTER
1750 ? subreg_nregs (x
) : 1);
1752 return endregno
> inner_regno
&& regno
< inner_endregno
;
1758 if (&SET_DEST (x
) != loc
1759 /* Note setting a SUBREG counts as referring to the REG it is in for
1760 a pseudo but not for hard registers since we can
1761 treat each word individually. */
1762 && ((GET_CODE (SET_DEST (x
)) == SUBREG
1763 && loc
!= &SUBREG_REG (SET_DEST (x
))
1764 && REG_P (SUBREG_REG (SET_DEST (x
)))
1765 && REGNO (SUBREG_REG (SET_DEST (x
))) >= FIRST_PSEUDO_REGISTER
1766 && refers_to_regno_p (regno
, endregno
,
1767 SUBREG_REG (SET_DEST (x
)), loc
))
1768 || (!REG_P (SET_DEST (x
))
1769 && refers_to_regno_p (regno
, endregno
, SET_DEST (x
), loc
))))
1772 if (code
== CLOBBER
|| loc
== &SET_SRC (x
))
1781 /* X does not match, so try its subexpressions. */
1783 fmt
= GET_RTX_FORMAT (code
);
1784 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
1786 if (fmt
[i
] == 'e' && loc
!= &XEXP (x
, i
))
1794 if (refers_to_regno_p (regno
, endregno
, XEXP (x
, i
), loc
))
1797 else if (fmt
[i
] == 'E')
1800 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
1801 if (loc
!= &XVECEXP (x
, i
, j
)
1802 && refers_to_regno_p (regno
, endregno
, XVECEXP (x
, i
, j
), loc
))
1809 /* Nonzero if modifying X will affect IN. If X is a register or a SUBREG,
1810 we check if any register number in X conflicts with the relevant register
1811 numbers. If X is a constant, return 0. If X is a MEM, return 1 iff IN
1812 contains a MEM (we don't bother checking for memory addresses that can't
1813 conflict because we expect this to be a rare case. */
1816 reg_overlap_mentioned_p (const_rtx x
, const_rtx in
)
1818 unsigned int regno
, endregno
;
1820 /* If either argument is a constant, then modifying X cannot
1821 affect IN. Here we look at IN, we can profitably combine
1822 CONSTANT_P (x) with the switch statement below. */
1823 if (CONSTANT_P (in
))
1827 switch (GET_CODE (x
))
1830 case STRICT_LOW_PART
:
1833 /* Overly conservative. */
1838 regno
= REGNO (SUBREG_REG (x
));
1839 if (regno
< FIRST_PSEUDO_REGISTER
)
1840 regno
= subreg_regno (x
);
1841 endregno
= regno
+ (regno
< FIRST_PSEUDO_REGISTER
1842 ? subreg_nregs (x
) : 1);
1847 endregno
= END_REGNO (x
);
1849 return refers_to_regno_p (regno
, endregno
, in
, (rtx
*) 0);
1859 fmt
= GET_RTX_FORMAT (GET_CODE (in
));
1860 for (i
= GET_RTX_LENGTH (GET_CODE (in
)) - 1; i
>= 0; i
--)
1863 if (reg_overlap_mentioned_p (x
, XEXP (in
, i
)))
1866 else if (fmt
[i
] == 'E')
1869 for (j
= XVECLEN (in
, i
) - 1; j
>= 0; --j
)
1870 if (reg_overlap_mentioned_p (x
, XVECEXP (in
, i
, j
)))
1880 return reg_mentioned_p (x
, in
);
1886 /* If any register in here refers to it we return true. */
1887 for (i
= XVECLEN (x
, 0) - 1; i
>= 0; i
--)
1888 if (XEXP (XVECEXP (x
, 0, i
), 0) != 0
1889 && reg_overlap_mentioned_p (XEXP (XVECEXP (x
, 0, i
), 0), in
))
1895 gcc_assert (CONSTANT_P (x
));
1900 /* Call FUN on each register or MEM that is stored into or clobbered by X.
1901 (X would be the pattern of an insn). DATA is an arbitrary pointer,
1902 ignored by note_stores, but passed to FUN.
1904 FUN receives three arguments:
1905 1. the REG, MEM, CC0 or PC being stored in or clobbered,
1906 2. the SET or CLOBBER rtx that does the store,
1907 3. the pointer DATA provided to note_stores.
1909 If the item being stored in or clobbered is a SUBREG of a hard register,
1910 the SUBREG will be passed. */
1913 note_pattern_stores (const_rtx x
,
1914 void (*fun
) (rtx
, const_rtx
, void *), void *data
)
1918 if (GET_CODE (x
) == COND_EXEC
)
1919 x
= COND_EXEC_CODE (x
);
1921 if (GET_CODE (x
) == SET
1922 || GET_CODE (x
) == CLOBBER
1923 || GET_CODE (x
) == CLOBBER_HIGH
)
1925 rtx dest
= SET_DEST (x
);
1927 while ((GET_CODE (dest
) == SUBREG
1928 && (!REG_P (SUBREG_REG (dest
))
1929 || REGNO (SUBREG_REG (dest
)) >= FIRST_PSEUDO_REGISTER
))
1930 || GET_CODE (dest
) == ZERO_EXTRACT
1931 || GET_CODE (dest
) == STRICT_LOW_PART
)
1932 dest
= XEXP (dest
, 0);
1934 /* If we have a PARALLEL, SET_DEST is a list of EXPR_LIST expressions,
1935 each of whose first operand is a register. */
1936 if (GET_CODE (dest
) == PARALLEL
)
1938 for (i
= XVECLEN (dest
, 0) - 1; i
>= 0; i
--)
1939 if (XEXP (XVECEXP (dest
, 0, i
), 0) != 0)
1940 (*fun
) (XEXP (XVECEXP (dest
, 0, i
), 0), x
, data
);
1943 (*fun
) (dest
, x
, data
);
1946 else if (GET_CODE (x
) == PARALLEL
)
1947 for (i
= XVECLEN (x
, 0) - 1; i
>= 0; i
--)
1948 note_pattern_stores (XVECEXP (x
, 0, i
), fun
, data
);
1951 /* Same, but for an instruction. If the instruction is a call, include
1952 any CLOBBERs in its CALL_INSN_FUNCTION_USAGE. */
1955 note_stores (const rtx_insn
*insn
,
1956 void (*fun
) (rtx
, const_rtx
, void *), void *data
)
1959 for (rtx link
= CALL_INSN_FUNCTION_USAGE (insn
);
1960 link
; link
= XEXP (link
, 1))
1961 if (GET_CODE (XEXP (link
, 0)) == CLOBBER
)
1962 note_pattern_stores (XEXP (link
, 0), fun
, data
);
1963 note_pattern_stores (PATTERN (insn
), fun
, data
);
1966 /* Like notes_stores, but call FUN for each expression that is being
1967 referenced in PBODY, a pointer to the PATTERN of an insn. We only call
1968 FUN for each expression, not any interior subexpressions. FUN receives a
1969 pointer to the expression and the DATA passed to this function.
1971 Note that this is not quite the same test as that done in reg_referenced_p
1972 since that considers something as being referenced if it is being
1973 partially set, while we do not. */
1976 note_uses (rtx
*pbody
, void (*fun
) (rtx
*, void *), void *data
)
1981 switch (GET_CODE (body
))
1984 (*fun
) (&COND_EXEC_TEST (body
), data
);
1985 note_uses (&COND_EXEC_CODE (body
), fun
, data
);
1989 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; i
--)
1990 note_uses (&XVECEXP (body
, 0, i
), fun
, data
);
1994 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; i
--)
1995 note_uses (&PATTERN (XVECEXP (body
, 0, i
)), fun
, data
);
1999 (*fun
) (&XEXP (body
, 0), data
);
2003 for (i
= ASM_OPERANDS_INPUT_LENGTH (body
) - 1; i
>= 0; i
--)
2004 (*fun
) (&ASM_OPERANDS_INPUT (body
, i
), data
);
2008 (*fun
) (&TRAP_CONDITION (body
), data
);
2012 (*fun
) (&XEXP (body
, 0), data
);
2016 case UNSPEC_VOLATILE
:
2017 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; i
--)
2018 (*fun
) (&XVECEXP (body
, 0, i
), data
);
2022 if (MEM_P (XEXP (body
, 0)))
2023 (*fun
) (&XEXP (XEXP (body
, 0), 0), data
);
2028 rtx dest
= SET_DEST (body
);
2030 /* For sets we replace everything in source plus registers in memory
2031 expression in store and operands of a ZERO_EXTRACT. */
2032 (*fun
) (&SET_SRC (body
), data
);
2034 if (GET_CODE (dest
) == ZERO_EXTRACT
)
2036 (*fun
) (&XEXP (dest
, 1), data
);
2037 (*fun
) (&XEXP (dest
, 2), data
);
2040 while (GET_CODE (dest
) == SUBREG
|| GET_CODE (dest
) == STRICT_LOW_PART
)
2041 dest
= XEXP (dest
, 0);
2044 (*fun
) (&XEXP (dest
, 0), data
);
2049 /* All the other possibilities never store. */
2050 (*fun
) (pbody
, data
);
2055 /* Return nonzero if X's old contents don't survive after INSN.
2056 This will be true if X is (cc0) or if X is a register and
2057 X dies in INSN or because INSN entirely sets X.
2059 "Entirely set" means set directly and not through a SUBREG, or
2060 ZERO_EXTRACT, so no trace of the old contents remains.
2061 Likewise, REG_INC does not count.
2063 REG may be a hard or pseudo reg. Renumbering is not taken into account,
2064 but for this use that makes no difference, since regs don't overlap
2065 during their lifetimes. Therefore, this function may be used
2066 at any time after deaths have been computed.
2068 If REG is a hard reg that occupies multiple machine registers, this
2069 function will only return 1 if each of those registers will be replaced
2073 dead_or_set_p (const rtx_insn
*insn
, const_rtx x
)
2075 unsigned int regno
, end_regno
;
2078 /* Can't use cc0_rtx below since this file is used by genattrtab.c. */
2079 if (GET_CODE (x
) == CC0
)
2082 gcc_assert (REG_P (x
));
2085 end_regno
= END_REGNO (x
);
2086 for (i
= regno
; i
< end_regno
; i
++)
2087 if (! dead_or_set_regno_p (insn
, i
))
2093 /* Return TRUE iff DEST is a register or subreg of a register, is a
2094 complete rather than read-modify-write destination, and contains
2095 register TEST_REGNO. */
2098 covers_regno_no_parallel_p (const_rtx dest
, unsigned int test_regno
)
2100 unsigned int regno
, endregno
;
2102 if (GET_CODE (dest
) == SUBREG
&& !read_modify_subreg_p (dest
))
2103 dest
= SUBREG_REG (dest
);
2108 regno
= REGNO (dest
);
2109 endregno
= END_REGNO (dest
);
2110 return (test_regno
>= regno
&& test_regno
< endregno
);
2113 /* Like covers_regno_no_parallel_p, but also handles PARALLELs where
2114 any member matches the covers_regno_no_parallel_p criteria. */
2117 covers_regno_p (const_rtx dest
, unsigned int test_regno
)
2119 if (GET_CODE (dest
) == PARALLEL
)
2121 /* Some targets place small structures in registers for return
2122 values of functions, and those registers are wrapped in
2123 PARALLELs that we may see as the destination of a SET. */
2126 for (i
= XVECLEN (dest
, 0) - 1; i
>= 0; i
--)
2128 rtx inner
= XEXP (XVECEXP (dest
, 0, i
), 0);
2129 if (inner
!= NULL_RTX
2130 && covers_regno_no_parallel_p (inner
, test_regno
))
2137 return covers_regno_no_parallel_p (dest
, test_regno
);
2140 /* Utility function for dead_or_set_p to check an individual register. */
2143 dead_or_set_regno_p (const rtx_insn
*insn
, unsigned int test_regno
)
2147 /* See if there is a death note for something that includes TEST_REGNO. */
2148 if (find_regno_note (insn
, REG_DEAD
, test_regno
))
2152 && find_regno_fusage (insn
, CLOBBER
, test_regno
))
2155 pattern
= PATTERN (insn
);
2157 /* If a COND_EXEC is not executed, the value survives. */
2158 if (GET_CODE (pattern
) == COND_EXEC
)
2161 if (GET_CODE (pattern
) == SET
|| GET_CODE (pattern
) == CLOBBER
)
2162 return covers_regno_p (SET_DEST (pattern
), test_regno
);
2163 else if (GET_CODE (pattern
) == PARALLEL
)
2167 for (i
= XVECLEN (pattern
, 0) - 1; i
>= 0; i
--)
2169 rtx body
= XVECEXP (pattern
, 0, i
);
2171 if (GET_CODE (body
) == COND_EXEC
)
2172 body
= COND_EXEC_CODE (body
);
2174 if ((GET_CODE (body
) == SET
|| GET_CODE (body
) == CLOBBER
)
2175 && covers_regno_p (SET_DEST (body
), test_regno
))
2183 /* Return the reg-note of kind KIND in insn INSN, if there is one.
2184 If DATUM is nonzero, look for one whose datum is DATUM. */
2187 find_reg_note (const_rtx insn
, enum reg_note kind
, const_rtx datum
)
2191 gcc_checking_assert (insn
);
2193 /* Ignore anything that is not an INSN, JUMP_INSN or CALL_INSN. */
2194 if (! INSN_P (insn
))
2198 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
2199 if (REG_NOTE_KIND (link
) == kind
)
2204 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
2205 if (REG_NOTE_KIND (link
) == kind
&& datum
== XEXP (link
, 0))
2210 /* Return the reg-note of kind KIND in insn INSN which applies to register
2211 number REGNO, if any. Return 0 if there is no such reg-note. Note that
2212 the REGNO of this NOTE need not be REGNO if REGNO is a hard register;
2213 it might be the case that the note overlaps REGNO. */
2216 find_regno_note (const_rtx insn
, enum reg_note kind
, unsigned int regno
)
2220 /* Ignore anything that is not an INSN, JUMP_INSN or CALL_INSN. */
2221 if (! INSN_P (insn
))
2224 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
2225 if (REG_NOTE_KIND (link
) == kind
2226 /* Verify that it is a register, so that scratch and MEM won't cause a
2228 && REG_P (XEXP (link
, 0))
2229 && REGNO (XEXP (link
, 0)) <= regno
2230 && END_REGNO (XEXP (link
, 0)) > regno
)
2235 /* Return a REG_EQUIV or REG_EQUAL note if insn has only a single set and
2239 find_reg_equal_equiv_note (const_rtx insn
)
2246 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
2247 if (REG_NOTE_KIND (link
) == REG_EQUAL
2248 || REG_NOTE_KIND (link
) == REG_EQUIV
)
2250 /* FIXME: We should never have REG_EQUAL/REG_EQUIV notes on
2251 insns that have multiple sets. Checking single_set to
2252 make sure of this is not the proper check, as explained
2253 in the comment in set_unique_reg_note.
2255 This should be changed into an assert. */
2256 if (GET_CODE (PATTERN (insn
)) == PARALLEL
&& multiple_sets (insn
))
2263 /* Check whether INSN is a single_set whose source is known to be
2264 equivalent to a constant. Return that constant if so, otherwise
2268 find_constant_src (const rtx_insn
*insn
)
2272 set
= single_set (insn
);
2275 x
= avoid_constant_pool_reference (SET_SRC (set
));
2280 note
= find_reg_equal_equiv_note (insn
);
2281 if (note
&& CONSTANT_P (XEXP (note
, 0)))
2282 return XEXP (note
, 0);
2287 /* Return true if DATUM, or any overlap of DATUM, of kind CODE is found
2288 in the CALL_INSN_FUNCTION_USAGE information of INSN. */
2291 find_reg_fusage (const_rtx insn
, enum rtx_code code
, const_rtx datum
)
2293 /* If it's not a CALL_INSN, it can't possibly have a
2294 CALL_INSN_FUNCTION_USAGE field, so don't bother checking. */
2304 for (link
= CALL_INSN_FUNCTION_USAGE (insn
);
2306 link
= XEXP (link
, 1))
2307 if (GET_CODE (XEXP (link
, 0)) == code
2308 && rtx_equal_p (datum
, XEXP (XEXP (link
, 0), 0)))
2313 unsigned int regno
= REGNO (datum
);
2315 /* CALL_INSN_FUNCTION_USAGE information cannot contain references
2316 to pseudo registers, so don't bother checking. */
2318 if (regno
< FIRST_PSEUDO_REGISTER
)
2320 unsigned int end_regno
= END_REGNO (datum
);
2323 for (i
= regno
; i
< end_regno
; i
++)
2324 if (find_regno_fusage (insn
, code
, i
))
2332 /* Return true if REGNO, or any overlap of REGNO, of kind CODE is found
2333 in the CALL_INSN_FUNCTION_USAGE information of INSN. */
2336 find_regno_fusage (const_rtx insn
, enum rtx_code code
, unsigned int regno
)
2340 /* CALL_INSN_FUNCTION_USAGE information cannot contain references
2341 to pseudo registers, so don't bother checking. */
2343 if (regno
>= FIRST_PSEUDO_REGISTER
2347 for (link
= CALL_INSN_FUNCTION_USAGE (insn
); link
; link
= XEXP (link
, 1))
2351 if (GET_CODE (op
= XEXP (link
, 0)) == code
2352 && REG_P (reg
= XEXP (op
, 0))
2353 && REGNO (reg
) <= regno
2354 && END_REGNO (reg
) > regno
)
2362 /* Return true if KIND is an integer REG_NOTE. */
2365 int_reg_note_p (enum reg_note kind
)
2367 return kind
== REG_BR_PROB
;
2370 /* Allocate a register note with kind KIND and datum DATUM. LIST is
2371 stored as the pointer to the next register note. */
2374 alloc_reg_note (enum reg_note kind
, rtx datum
, rtx list
)
2378 gcc_checking_assert (!int_reg_note_p (kind
));
2383 case REG_LABEL_TARGET
:
2384 case REG_LABEL_OPERAND
:
2386 /* These types of register notes use an INSN_LIST rather than an
2387 EXPR_LIST, so that copying is done right and dumps look
2389 note
= alloc_INSN_LIST (datum
, list
);
2390 PUT_REG_NOTE_KIND (note
, kind
);
2394 note
= alloc_EXPR_LIST (kind
, datum
, list
);
2401 /* Add register note with kind KIND and datum DATUM to INSN. */
2404 add_reg_note (rtx insn
, enum reg_note kind
, rtx datum
)
2406 REG_NOTES (insn
) = alloc_reg_note (kind
, datum
, REG_NOTES (insn
));
2409 /* Add an integer register note with kind KIND and datum DATUM to INSN. */
2412 add_int_reg_note (rtx_insn
*insn
, enum reg_note kind
, int datum
)
2414 gcc_checking_assert (int_reg_note_p (kind
));
2415 REG_NOTES (insn
) = gen_rtx_INT_LIST ((machine_mode
) kind
,
2416 datum
, REG_NOTES (insn
));
2419 /* Add a REG_ARGS_SIZE note to INSN with value VALUE. */
2422 add_args_size_note (rtx_insn
*insn
, poly_int64 value
)
2424 gcc_checking_assert (!find_reg_note (insn
, REG_ARGS_SIZE
, NULL_RTX
));
2425 add_reg_note (insn
, REG_ARGS_SIZE
, gen_int_mode (value
, Pmode
));
2428 /* Add a register note like NOTE to INSN. */
2431 add_shallow_copy_of_reg_note (rtx_insn
*insn
, rtx note
)
2433 if (GET_CODE (note
) == INT_LIST
)
2434 add_int_reg_note (insn
, REG_NOTE_KIND (note
), XINT (note
, 0));
2436 add_reg_note (insn
, REG_NOTE_KIND (note
), XEXP (note
, 0));
2439 /* Duplicate NOTE and return the copy. */
2441 duplicate_reg_note (rtx note
)
2443 reg_note kind
= REG_NOTE_KIND (note
);
2445 if (GET_CODE (note
) == INT_LIST
)
2446 return gen_rtx_INT_LIST ((machine_mode
) kind
, XINT (note
, 0), NULL_RTX
);
2447 else if (GET_CODE (note
) == EXPR_LIST
)
2448 return alloc_reg_note (kind
, copy_insn_1 (XEXP (note
, 0)), NULL_RTX
);
2450 return alloc_reg_note (kind
, XEXP (note
, 0), NULL_RTX
);
2453 /* Remove register note NOTE from the REG_NOTES of INSN. */
2456 remove_note (rtx_insn
*insn
, const_rtx note
)
2460 if (note
== NULL_RTX
)
2463 if (REG_NOTES (insn
) == note
)
2464 REG_NOTES (insn
) = XEXP (note
, 1);
2466 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
2467 if (XEXP (link
, 1) == note
)
2469 XEXP (link
, 1) = XEXP (note
, 1);
2473 switch (REG_NOTE_KIND (note
))
2477 df_notes_rescan (insn
);
2484 /* Remove REG_EQUAL and/or REG_EQUIV notes if INSN has such notes.
2485 Return true if any note has been removed. */
2488 remove_reg_equal_equiv_notes (rtx_insn
*insn
)
2493 loc
= ®_NOTES (insn
);
2496 enum reg_note kind
= REG_NOTE_KIND (*loc
);
2497 if (kind
== REG_EQUAL
|| kind
== REG_EQUIV
)
2499 *loc
= XEXP (*loc
, 1);
2503 loc
= &XEXP (*loc
, 1);
2508 /* Remove all REG_EQUAL and REG_EQUIV notes referring to REGNO. */
2511 remove_reg_equal_equiv_notes_for_regno (unsigned int regno
)
2518 /* This loop is a little tricky. We cannot just go down the chain because
2519 it is being modified by some actions in the loop. So we just iterate
2520 over the head. We plan to drain the list anyway. */
2521 while ((eq_use
= DF_REG_EQ_USE_CHAIN (regno
)) != NULL
)
2523 rtx_insn
*insn
= DF_REF_INSN (eq_use
);
2524 rtx note
= find_reg_equal_equiv_note (insn
);
2526 /* This assert is generally triggered when someone deletes a REG_EQUAL
2527 or REG_EQUIV note by hacking the list manually rather than calling
2531 remove_note (insn
, note
);
2535 /* Search LISTP (an EXPR_LIST) for an entry whose first operand is NODE and
2536 return 1 if it is found. A simple equality test is used to determine if
2540 in_insn_list_p (const rtx_insn_list
*listp
, const rtx_insn
*node
)
2544 for (x
= listp
; x
; x
= XEXP (x
, 1))
2545 if (node
== XEXP (x
, 0))
2551 /* Search LISTP (an EXPR_LIST) for an entry whose first operand is NODE and
2552 remove that entry from the list if it is found.
2554 A simple equality test is used to determine if NODE matches. */
2557 remove_node_from_expr_list (const_rtx node
, rtx_expr_list
**listp
)
2559 rtx_expr_list
*temp
= *listp
;
2560 rtx_expr_list
*prev
= NULL
;
2564 if (node
== temp
->element ())
2566 /* Splice the node out of the list. */
2568 XEXP (prev
, 1) = temp
->next ();
2570 *listp
= temp
->next ();
2576 temp
= temp
->next ();
2580 /* Search LISTP (an INSN_LIST) for an entry whose first operand is NODE and
2581 remove that entry from the list if it is found.
2583 A simple equality test is used to determine if NODE matches. */
2586 remove_node_from_insn_list (const rtx_insn
*node
, rtx_insn_list
**listp
)
2588 rtx_insn_list
*temp
= *listp
;
2589 rtx_insn_list
*prev
= NULL
;
2593 if (node
== temp
->insn ())
2595 /* Splice the node out of the list. */
2597 XEXP (prev
, 1) = temp
->next ();
2599 *listp
= temp
->next ();
2605 temp
= temp
->next ();
2609 /* Nonzero if X contains any volatile instructions. These are instructions
2610 which may cause unpredictable machine state instructions, and thus no
2611 instructions or register uses should be moved or combined across them.
2612 This includes only volatile asms and UNSPEC_VOLATILE instructions. */
2615 volatile_insn_p (const_rtx x
)
2617 const RTX_CODE code
= GET_CODE (x
);
2635 case UNSPEC_VOLATILE
:
2640 if (MEM_VOLATILE_P (x
))
2647 /* Recursively scan the operands of this expression. */
2650 const char *const fmt
= GET_RTX_FORMAT (code
);
2653 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
2657 if (volatile_insn_p (XEXP (x
, i
)))
2660 else if (fmt
[i
] == 'E')
2663 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
2664 if (volatile_insn_p (XVECEXP (x
, i
, j
)))
2672 /* Nonzero if X contains any volatile memory references
2673 UNSPEC_VOLATILE operations or volatile ASM_OPERANDS expressions. */
2676 volatile_refs_p (const_rtx x
)
2678 const RTX_CODE code
= GET_CODE (x
);
2694 case UNSPEC_VOLATILE
:
2700 if (MEM_VOLATILE_P (x
))
2707 /* Recursively scan the operands of this expression. */
2710 const char *const fmt
= GET_RTX_FORMAT (code
);
2713 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
2717 if (volatile_refs_p (XEXP (x
, i
)))
2720 else if (fmt
[i
] == 'E')
2723 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
2724 if (volatile_refs_p (XVECEXP (x
, i
, j
)))
2732 /* Similar to above, except that it also rejects register pre- and post-
2736 side_effects_p (const_rtx x
)
2738 const RTX_CODE code
= GET_CODE (x
);
2755 /* Reject CLOBBER with a non-VOID mode. These are made by combine.c
2756 when some combination can't be done. If we see one, don't think
2757 that we can simplify the expression. */
2758 return (GET_MODE (x
) != VOIDmode
);
2767 case UNSPEC_VOLATILE
:
2773 if (MEM_VOLATILE_P (x
))
2780 /* Recursively scan the operands of this expression. */
2783 const char *fmt
= GET_RTX_FORMAT (code
);
2786 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
2790 if (side_effects_p (XEXP (x
, i
)))
2793 else if (fmt
[i
] == 'E')
2796 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
2797 if (side_effects_p (XVECEXP (x
, i
, j
)))
2805 /* Return nonzero if evaluating rtx X might cause a trap.
2806 FLAGS controls how to consider MEMs. A nonzero means the context
2807 of the access may have changed from the original, such that the
2808 address may have become invalid. */
2811 may_trap_p_1 (const_rtx x
, unsigned flags
)
2817 /* We make no distinction currently, but this function is part of
2818 the internal target-hooks ABI so we keep the parameter as
2819 "unsigned flags". */
2820 bool code_changed
= flags
!= 0;
2824 code
= GET_CODE (x
);
2827 /* Handle these cases quickly. */
2839 return targetm
.unspec_may_trap_p (x
, flags
);
2841 case UNSPEC_VOLATILE
:
2847 return MEM_VOLATILE_P (x
);
2849 /* Memory ref can trap unless it's a static var or a stack slot. */
2851 /* Recognize specific pattern of stack checking probes. */
2852 if (flag_stack_check
2853 && MEM_VOLATILE_P (x
)
2854 && XEXP (x
, 0) == stack_pointer_rtx
)
2856 if (/* MEM_NOTRAP_P only relates to the actual position of the memory
2857 reference; moving it out of context such as when moving code
2858 when optimizing, might cause its address to become invalid. */
2860 || !MEM_NOTRAP_P (x
))
2862 poly_int64 size
= MEM_SIZE_KNOWN_P (x
) ? MEM_SIZE (x
) : -1;
2863 return rtx_addr_can_trap_p_1 (XEXP (x
, 0), 0, size
,
2864 GET_MODE (x
), code_changed
);
2869 /* Division by a non-constant might trap. */
2874 if (HONOR_SNANS (x
))
2876 if (FLOAT_MODE_P (GET_MODE (x
)))
2877 return flag_trapping_math
;
2878 if (!CONSTANT_P (XEXP (x
, 1)) || (XEXP (x
, 1) == const0_rtx
))
2880 if (GET_CODE (XEXP (x
, 1)) == CONST_VECTOR
)
2882 /* For CONST_VECTOR, return 1 if any element is or might be zero. */
2883 unsigned int n_elts
;
2884 rtx op
= XEXP (x
, 1);
2885 if (!GET_MODE_NUNITS (GET_MODE (op
)).is_constant (&n_elts
))
2887 if (!CONST_VECTOR_DUPLICATE_P (op
))
2889 for (unsigned i
= 0; i
< (unsigned int) XVECLEN (op
, 0); i
++)
2890 if (CONST_VECTOR_ENCODED_ELT (op
, i
) == const0_rtx
)
2894 for (unsigned i
= 0; i
< n_elts
; i
++)
2895 if (CONST_VECTOR_ELT (op
, i
) == const0_rtx
)
2901 /* An EXPR_LIST is used to represent a function call. This
2902 certainly may trap. */
2911 /* Some floating point comparisons may trap. */
2912 if (!flag_trapping_math
)
2914 /* ??? There is no machine independent way to check for tests that trap
2915 when COMPARE is used, though many targets do make this distinction.
2916 For instance, sparc uses CCFPE for compares which generate exceptions
2917 and CCFP for compares which do not generate exceptions. */
2920 /* But often the compare has some CC mode, so check operand
2922 if (HONOR_NANS (XEXP (x
, 0))
2923 || HONOR_NANS (XEXP (x
, 1)))
2929 if (HONOR_SNANS (x
))
2931 /* Often comparison is CC mode, so check operand modes. */
2932 if (HONOR_SNANS (XEXP (x
, 0))
2933 || HONOR_SNANS (XEXP (x
, 1)))
2938 /* Conversion of floating point might trap. */
2939 if (flag_trapping_math
&& HONOR_NANS (XEXP (x
, 0)))
2950 /* These operations don't trap even with floating point. */
2954 /* Any floating arithmetic may trap. */
2955 if (FLOAT_MODE_P (GET_MODE (x
)) && flag_trapping_math
)
2959 fmt
= GET_RTX_FORMAT (code
);
2960 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
2964 if (may_trap_p_1 (XEXP (x
, i
), flags
))
2967 else if (fmt
[i
] == 'E')
2970 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
2971 if (may_trap_p_1 (XVECEXP (x
, i
, j
), flags
))
2978 /* Return nonzero if evaluating rtx X might cause a trap. */
2981 may_trap_p (const_rtx x
)
2983 return may_trap_p_1 (x
, 0);
2986 /* Same as above, but additionally return nonzero if evaluating rtx X might
2987 cause a fault. We define a fault for the purpose of this function as a
2988 erroneous execution condition that cannot be encountered during the normal
2989 execution of a valid program; the typical example is an unaligned memory
2990 access on a strict alignment machine. The compiler guarantees that it
2991 doesn't generate code that will fault from a valid program, but this
2992 guarantee doesn't mean anything for individual instructions. Consider
2993 the following example:
2995 struct S { int d; union { char *cp; int *ip; }; };
2997 int foo(struct S *s)
3005 on a strict alignment machine. In a valid program, foo will never be
3006 invoked on a structure for which d is equal to 1 and the underlying
3007 unique field of the union not aligned on a 4-byte boundary, but the
3008 expression *s->ip might cause a fault if considered individually.
3010 At the RTL level, potentially problematic expressions will almost always
3011 verify may_trap_p; for example, the above dereference can be emitted as
3012 (mem:SI (reg:P)) and this expression is may_trap_p for a generic register.
3013 However, suppose that foo is inlined in a caller that causes s->cp to
3014 point to a local character variable and guarantees that s->d is not set
3015 to 1; foo may have been effectively translated into pseudo-RTL as:
3018 (set (reg:SI) (mem:SI (%fp - 7)))
3020 (set (reg:QI) (mem:QI (%fp - 7)))
3022 Now (mem:SI (%fp - 7)) is considered as not may_trap_p since it is a
3023 memory reference to a stack slot, but it will certainly cause a fault
3024 on a strict alignment machine. */
3027 may_trap_or_fault_p (const_rtx x
)
3029 return may_trap_p_1 (x
, 1);
3032 /* Return nonzero if X contains a comparison that is not either EQ or NE,
3033 i.e., an inequality. */
3036 inequality_comparisons_p (const_rtx x
)
3040 const enum rtx_code code
= GET_CODE (x
);
3068 len
= GET_RTX_LENGTH (code
);
3069 fmt
= GET_RTX_FORMAT (code
);
3071 for (i
= 0; i
< len
; i
++)
3075 if (inequality_comparisons_p (XEXP (x
, i
)))
3078 else if (fmt
[i
] == 'E')
3081 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3082 if (inequality_comparisons_p (XVECEXP (x
, i
, j
)))
3090 /* Replace any occurrence of FROM in X with TO. The function does
3091 not enter into CONST_DOUBLE for the replace.
3093 Note that copying is not done so X must not be shared unless all copies
3096 ALL_REGS is true if we want to replace all REGs equal to FROM, not just
3097 those pointer-equal ones. */
3100 replace_rtx (rtx x
, rtx from
, rtx to
, bool all_regs
)
3108 /* Allow this function to make replacements in EXPR_LISTs. */
3115 && REGNO (x
) == REGNO (from
))
3117 gcc_assert (GET_MODE (x
) == GET_MODE (from
));
3120 else if (GET_CODE (x
) == SUBREG
)
3122 rtx new_rtx
= replace_rtx (SUBREG_REG (x
), from
, to
, all_regs
);
3124 if (CONST_INT_P (new_rtx
))
3126 x
= simplify_subreg (GET_MODE (x
), new_rtx
,
3127 GET_MODE (SUBREG_REG (x
)),
3132 SUBREG_REG (x
) = new_rtx
;
3136 else if (GET_CODE (x
) == ZERO_EXTEND
)
3138 rtx new_rtx
= replace_rtx (XEXP (x
, 0), from
, to
, all_regs
);
3140 if (CONST_INT_P (new_rtx
))
3142 x
= simplify_unary_operation (ZERO_EXTEND
, GET_MODE (x
),
3143 new_rtx
, GET_MODE (XEXP (x
, 0)));
3147 XEXP (x
, 0) = new_rtx
;
3152 fmt
= GET_RTX_FORMAT (GET_CODE (x
));
3153 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
3156 XEXP (x
, i
) = replace_rtx (XEXP (x
, i
), from
, to
, all_regs
);
3157 else if (fmt
[i
] == 'E')
3158 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3159 XVECEXP (x
, i
, j
) = replace_rtx (XVECEXP (x
, i
, j
),
3160 from
, to
, all_regs
);
3166 /* Replace occurrences of the OLD_LABEL in *LOC with NEW_LABEL. Also track
3167 the change in LABEL_NUSES if UPDATE_LABEL_NUSES. */
3170 replace_label (rtx
*loc
, rtx old_label
, rtx new_label
, bool update_label_nuses
)
3172 /* Handle jump tables specially, since ADDR_{DIFF_,}VECs can be long. */
3174 if (JUMP_TABLE_DATA_P (x
))
3177 rtvec vec
= XVEC (x
, GET_CODE (x
) == ADDR_DIFF_VEC
);
3178 int len
= GET_NUM_ELEM (vec
);
3179 for (int i
= 0; i
< len
; ++i
)
3181 rtx ref
= RTVEC_ELT (vec
, i
);
3182 if (XEXP (ref
, 0) == old_label
)
3184 XEXP (ref
, 0) = new_label
;
3185 if (update_label_nuses
)
3187 ++LABEL_NUSES (new_label
);
3188 --LABEL_NUSES (old_label
);
3195 /* If this is a JUMP_INSN, then we also need to fix the JUMP_LABEL
3196 field. This is not handled by the iterator because it doesn't
3197 handle unprinted ('0') fields. */
3198 if (JUMP_P (x
) && JUMP_LABEL (x
) == old_label
)
3199 JUMP_LABEL (x
) = new_label
;
3201 subrtx_ptr_iterator::array_type array
;
3202 FOR_EACH_SUBRTX_PTR (iter
, array
, loc
, ALL
)
3207 if (GET_CODE (x
) == SYMBOL_REF
3208 && CONSTANT_POOL_ADDRESS_P (x
))
3210 rtx c
= get_pool_constant (x
);
3211 if (rtx_referenced_p (old_label
, c
))
3213 /* Create a copy of constant C; replace the label inside
3214 but do not update LABEL_NUSES because uses in constant pool
3216 rtx new_c
= copy_rtx (c
);
3217 replace_label (&new_c
, old_label
, new_label
, false);
3219 /* Add the new constant NEW_C to constant pool and replace
3220 the old reference to constant by new reference. */
3221 rtx new_mem
= force_const_mem (get_pool_mode (x
), new_c
);
3222 *loc
= replace_rtx (x
, x
, XEXP (new_mem
, 0));
3226 if ((GET_CODE (x
) == LABEL_REF
3227 || GET_CODE (x
) == INSN_LIST
)
3228 && XEXP (x
, 0) == old_label
)
3230 XEXP (x
, 0) = new_label
;
3231 if (update_label_nuses
)
3233 ++LABEL_NUSES (new_label
);
3234 --LABEL_NUSES (old_label
);
3242 replace_label_in_insn (rtx_insn
*insn
, rtx_insn
*old_label
,
3243 rtx_insn
*new_label
, bool update_label_nuses
)
3245 rtx insn_as_rtx
= insn
;
3246 replace_label (&insn_as_rtx
, old_label
, new_label
, update_label_nuses
);
3247 gcc_checking_assert (insn_as_rtx
== insn
);
3250 /* Return true if X is referenced in BODY. */
3253 rtx_referenced_p (const_rtx x
, const_rtx body
)
3255 subrtx_iterator::array_type array
;
3256 FOR_EACH_SUBRTX (iter
, array
, body
, ALL
)
3257 if (const_rtx y
= *iter
)
3259 /* Check if a label_ref Y refers to label X. */
3260 if (GET_CODE (y
) == LABEL_REF
3262 && label_ref_label (y
) == x
)
3265 if (rtx_equal_p (x
, y
))
3268 /* If Y is a reference to pool constant traverse the constant. */
3269 if (GET_CODE (y
) == SYMBOL_REF
3270 && CONSTANT_POOL_ADDRESS_P (y
))
3271 iter
.substitute (get_pool_constant (y
));
3276 /* If INSN is a tablejump return true and store the label (before jump table) to
3277 *LABELP and the jump table to *TABLEP. LABELP and TABLEP may be NULL. */
3280 tablejump_p (const rtx_insn
*insn
, rtx_insn
**labelp
,
3281 rtx_jump_table_data
**tablep
)
3286 rtx target
= JUMP_LABEL (insn
);
3287 if (target
== NULL_RTX
|| ANY_RETURN_P (target
))
3290 rtx_insn
*label
= as_a
<rtx_insn
*> (target
);
3291 rtx_insn
*table
= next_insn (label
);
3292 if (table
== NULL_RTX
|| !JUMP_TABLE_DATA_P (table
))
3298 *tablep
= as_a
<rtx_jump_table_data
*> (table
);
3302 /* For INSN known to satisfy tablejump_p, determine if it actually is a
3303 CASESI. Return the insn pattern if so, NULL_RTX otherwise. */
3306 tablejump_casesi_pattern (const rtx_insn
*insn
)
3310 if ((tmp
= single_set (insn
)) != NULL
3311 && SET_DEST (tmp
) == pc_rtx
3312 && GET_CODE (SET_SRC (tmp
)) == IF_THEN_ELSE
3313 && GET_CODE (XEXP (SET_SRC (tmp
), 2)) == LABEL_REF
)
3319 /* A subroutine of computed_jump_p, return 1 if X contains a REG or MEM or
3320 constant that is not in the constant pool and not in the condition
3321 of an IF_THEN_ELSE. */
3324 computed_jump_p_1 (const_rtx x
)
3326 const enum rtx_code code
= GET_CODE (x
);
3343 return ! (GET_CODE (XEXP (x
, 0)) == SYMBOL_REF
3344 && CONSTANT_POOL_ADDRESS_P (XEXP (x
, 0)));
3347 return (computed_jump_p_1 (XEXP (x
, 1))
3348 || computed_jump_p_1 (XEXP (x
, 2)));
3354 fmt
= GET_RTX_FORMAT (code
);
3355 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
3358 && computed_jump_p_1 (XEXP (x
, i
)))
3361 else if (fmt
[i
] == 'E')
3362 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
3363 if (computed_jump_p_1 (XVECEXP (x
, i
, j
)))
3370 /* Return nonzero if INSN is an indirect jump (aka computed jump).
3372 Tablejumps and casesi insns are not considered indirect jumps;
3373 we can recognize them by a (use (label_ref)). */
3376 computed_jump_p (const rtx_insn
*insn
)
3381 rtx pat
= PATTERN (insn
);
3383 /* If we have a JUMP_LABEL set, we're not a computed jump. */
3384 if (JUMP_LABEL (insn
) != NULL
)
3387 if (GET_CODE (pat
) == PARALLEL
)
3389 int len
= XVECLEN (pat
, 0);
3390 int has_use_labelref
= 0;
3392 for (i
= len
- 1; i
>= 0; i
--)
3393 if (GET_CODE (XVECEXP (pat
, 0, i
)) == USE
3394 && (GET_CODE (XEXP (XVECEXP (pat
, 0, i
), 0))
3397 has_use_labelref
= 1;
3401 if (! has_use_labelref
)
3402 for (i
= len
- 1; i
>= 0; i
--)
3403 if (GET_CODE (XVECEXP (pat
, 0, i
)) == SET
3404 && SET_DEST (XVECEXP (pat
, 0, i
)) == pc_rtx
3405 && computed_jump_p_1 (SET_SRC (XVECEXP (pat
, 0, i
))))
3408 else if (GET_CODE (pat
) == SET
3409 && SET_DEST (pat
) == pc_rtx
3410 && computed_jump_p_1 (SET_SRC (pat
)))
3418 /* MEM has a PRE/POST-INC/DEC/MODIFY address X. Extract the operands of
3419 the equivalent add insn and pass the result to FN, using DATA as the
3423 for_each_inc_dec_find_inc_dec (rtx mem
, for_each_inc_dec_fn fn
, void *data
)
3425 rtx x
= XEXP (mem
, 0);
3426 switch (GET_CODE (x
))
3431 poly_int64 size
= GET_MODE_SIZE (GET_MODE (mem
));
3432 rtx r1
= XEXP (x
, 0);
3433 rtx c
= gen_int_mode (size
, GET_MODE (r1
));
3434 return fn (mem
, x
, r1
, r1
, c
, data
);
3440 poly_int64 size
= GET_MODE_SIZE (GET_MODE (mem
));
3441 rtx r1
= XEXP (x
, 0);
3442 rtx c
= gen_int_mode (-size
, GET_MODE (r1
));
3443 return fn (mem
, x
, r1
, r1
, c
, data
);
3449 rtx r1
= XEXP (x
, 0);
3450 rtx add
= XEXP (x
, 1);
3451 return fn (mem
, x
, r1
, add
, NULL
, data
);
3459 /* Traverse *LOC looking for MEMs that have autoinc addresses.
3460 For each such autoinc operation found, call FN, passing it
3461 the innermost enclosing MEM, the operation itself, the RTX modified
3462 by the operation, two RTXs (the second may be NULL) that, once
3463 added, represent the value to be held by the modified RTX
3464 afterwards, and DATA. FN is to return 0 to continue the
3465 traversal or any other value to have it returned to the caller of
3466 for_each_inc_dec. */
3469 for_each_inc_dec (rtx x
,
3470 for_each_inc_dec_fn fn
,
3473 subrtx_var_iterator::array_type array
;
3474 FOR_EACH_SUBRTX_VAR (iter
, array
, x
, NONCONST
)
3479 && GET_RTX_CLASS (GET_CODE (XEXP (mem
, 0))) == RTX_AUTOINC
)
3481 int res
= for_each_inc_dec_find_inc_dec (mem
, fn
, data
);
3484 iter
.skip_subrtxes ();
3491 /* Searches X for any reference to REGNO, returning the rtx of the
3492 reference found if any. Otherwise, returns NULL_RTX. */
3495 regno_use_in (unsigned int regno
, rtx x
)
3501 if (REG_P (x
) && REGNO (x
) == regno
)
3504 fmt
= GET_RTX_FORMAT (GET_CODE (x
));
3505 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
3509 if ((tem
= regno_use_in (regno
, XEXP (x
, i
))))
3512 else if (fmt
[i
] == 'E')
3513 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3514 if ((tem
= regno_use_in (regno
, XVECEXP (x
, i
, j
))))
3521 /* Return a value indicating whether OP, an operand of a commutative
3522 operation, is preferred as the first or second operand. The more
3523 positive the value, the stronger the preference for being the first
3527 commutative_operand_precedence (rtx op
)
3529 enum rtx_code code
= GET_CODE (op
);
3531 /* Constants always become the second operand. Prefer "nice" constants. */
3532 if (code
== CONST_INT
)
3534 if (code
== CONST_WIDE_INT
)
3536 if (code
== CONST_POLY_INT
)
3538 if (code
== CONST_DOUBLE
)
3540 if (code
== CONST_FIXED
)
3542 op
= avoid_constant_pool_reference (op
);
3543 code
= GET_CODE (op
);
3545 switch (GET_RTX_CLASS (code
))
3548 if (code
== CONST_INT
)
3550 if (code
== CONST_WIDE_INT
)
3552 if (code
== CONST_POLY_INT
)
3554 if (code
== CONST_DOUBLE
)
3556 if (code
== CONST_FIXED
)
3561 /* SUBREGs of objects should come second. */
3562 if (code
== SUBREG
&& OBJECT_P (SUBREG_REG (op
)))
3567 /* Complex expressions should be the first, so decrease priority
3568 of objects. Prefer pointer objects over non pointer objects. */
3569 if ((REG_P (op
) && REG_POINTER (op
))
3570 || (MEM_P (op
) && MEM_POINTER (op
)))
3574 case RTX_COMM_ARITH
:
3575 /* Prefer operands that are themselves commutative to be first.
3576 This helps to make things linear. In particular,
3577 (and (and (reg) (reg)) (not (reg))) is canonical. */
3581 /* If only one operand is a binary expression, it will be the first
3582 operand. In particular, (plus (minus (reg) (reg)) (neg (reg)))
3583 is canonical, although it will usually be further simplified. */
3587 /* Then prefer NEG and NOT. */
3588 if (code
== NEG
|| code
== NOT
)
3597 /* Return 1 iff it is necessary to swap operands of commutative operation
3598 in order to canonicalize expression. */
3601 swap_commutative_operands_p (rtx x
, rtx y
)
3603 return (commutative_operand_precedence (x
)
3604 < commutative_operand_precedence (y
));
3607 /* Return 1 if X is an autoincrement side effect and the register is
3608 not the stack pointer. */
3610 auto_inc_p (const_rtx x
)
3612 switch (GET_CODE (x
))
3620 /* There are no REG_INC notes for SP. */
3621 if (XEXP (x
, 0) != stack_pointer_rtx
)
3629 /* Return nonzero if IN contains a piece of rtl that has the address LOC. */
3631 loc_mentioned_in_p (rtx
*loc
, const_rtx in
)
3640 code
= GET_CODE (in
);
3641 fmt
= GET_RTX_FORMAT (code
);
3642 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
3646 if (loc
== &XEXP (in
, i
) || loc_mentioned_in_p (loc
, XEXP (in
, i
)))
3649 else if (fmt
[i
] == 'E')
3650 for (j
= XVECLEN (in
, i
) - 1; j
>= 0; j
--)
3651 if (loc
== &XVECEXP (in
, i
, j
)
3652 || loc_mentioned_in_p (loc
, XVECEXP (in
, i
, j
)))
3658 /* Reinterpret a subreg as a bit extraction from an integer and return
3659 the position of the least significant bit of the extracted value.
3660 In other words, if the extraction were performed as a shift right
3661 and mask, return the number of bits to shift right.
3663 The outer value of the subreg has OUTER_BYTES bytes and starts at
3664 byte offset SUBREG_BYTE within an inner value of INNER_BYTES bytes. */
3667 subreg_size_lsb (poly_uint64 outer_bytes
,
3668 poly_uint64 inner_bytes
,
3669 poly_uint64 subreg_byte
)
3671 poly_uint64 subreg_end
, trailing_bytes
, byte_pos
;
3673 /* A paradoxical subreg begins at bit position 0. */
3674 gcc_checking_assert (ordered_p (outer_bytes
, inner_bytes
));
3675 if (maybe_gt (outer_bytes
, inner_bytes
))
3677 gcc_checking_assert (known_eq (subreg_byte
, 0U));
3681 subreg_end
= subreg_byte
+ outer_bytes
;
3682 trailing_bytes
= inner_bytes
- subreg_end
;
3683 if (WORDS_BIG_ENDIAN
&& BYTES_BIG_ENDIAN
)
3684 byte_pos
= trailing_bytes
;
3685 else if (!WORDS_BIG_ENDIAN
&& !BYTES_BIG_ENDIAN
)
3686 byte_pos
= subreg_byte
;
3689 /* When bytes and words have opposite endianness, we must be able
3690 to split offsets into words and bytes at compile time. */
3691 poly_uint64 leading_word_part
3692 = force_align_down (subreg_byte
, UNITS_PER_WORD
);
3693 poly_uint64 trailing_word_part
3694 = force_align_down (trailing_bytes
, UNITS_PER_WORD
);
3695 /* If the subreg crosses a word boundary ensure that
3696 it also begins and ends on a word boundary. */
3697 gcc_assert (known_le (subreg_end
- leading_word_part
,
3698 (unsigned int) UNITS_PER_WORD
)
3699 || (known_eq (leading_word_part
, subreg_byte
)
3700 && known_eq (trailing_word_part
, trailing_bytes
)));
3701 if (WORDS_BIG_ENDIAN
)
3702 byte_pos
= trailing_word_part
+ (subreg_byte
- leading_word_part
);
3704 byte_pos
= leading_word_part
+ (trailing_bytes
- trailing_word_part
);
3707 return byte_pos
* BITS_PER_UNIT
;
3710 /* Given a subreg X, return the bit offset where the subreg begins
3711 (counting from the least significant bit of the reg). */
3714 subreg_lsb (const_rtx x
)
3716 return subreg_lsb_1 (GET_MODE (x
), GET_MODE (SUBREG_REG (x
)),
3720 /* Return the subreg byte offset for a subreg whose outer value has
3721 OUTER_BYTES bytes, whose inner value has INNER_BYTES bytes, and where
3722 there are LSB_SHIFT *bits* between the lsb of the outer value and the
3723 lsb of the inner value. This is the inverse of the calculation
3724 performed by subreg_lsb_1 (which converts byte offsets to bit shifts). */
3727 subreg_size_offset_from_lsb (poly_uint64 outer_bytes
, poly_uint64 inner_bytes
,
3728 poly_uint64 lsb_shift
)
3730 /* A paradoxical subreg begins at bit position 0. */
3731 gcc_checking_assert (ordered_p (outer_bytes
, inner_bytes
));
3732 if (maybe_gt (outer_bytes
, inner_bytes
))
3734 gcc_checking_assert (known_eq (lsb_shift
, 0U));
3738 poly_uint64 lower_bytes
= exact_div (lsb_shift
, BITS_PER_UNIT
);
3739 poly_uint64 upper_bytes
= inner_bytes
- (lower_bytes
+ outer_bytes
);
3740 if (WORDS_BIG_ENDIAN
&& BYTES_BIG_ENDIAN
)
3742 else if (!WORDS_BIG_ENDIAN
&& !BYTES_BIG_ENDIAN
)
3746 /* When bytes and words have opposite endianness, we must be able
3747 to split offsets into words and bytes at compile time. */
3748 poly_uint64 lower_word_part
= force_align_down (lower_bytes
,
3750 poly_uint64 upper_word_part
= force_align_down (upper_bytes
,
3752 if (WORDS_BIG_ENDIAN
)
3753 return upper_word_part
+ (lower_bytes
- lower_word_part
);
3755 return lower_word_part
+ (upper_bytes
- upper_word_part
);
3759 /* Fill in information about a subreg of a hard register.
3760 xregno - A regno of an inner hard subreg_reg (or what will become one).
3761 xmode - The mode of xregno.
3762 offset - The byte offset.
3763 ymode - The mode of a top level SUBREG (or what may become one).
3764 info - Pointer to structure to fill in.
3766 Rather than considering one particular inner register (and thus one
3767 particular "outer" register) in isolation, this function really uses
3768 XREGNO as a model for a sequence of isomorphic hard registers. Thus the
3769 function does not check whether adding INFO->offset to XREGNO gives
3770 a valid hard register; even if INFO->offset + XREGNO is out of range,
3771 there might be another register of the same type that is in range.
3772 Likewise it doesn't check whether targetm.hard_regno_mode_ok accepts
3773 the new register, since that can depend on things like whether the final
3774 register number is even or odd. Callers that want to check whether
3775 this particular subreg can be replaced by a simple (reg ...) should
3776 use simplify_subreg_regno. */
3779 subreg_get_info (unsigned int xregno
, machine_mode xmode
,
3780 poly_uint64 offset
, machine_mode ymode
,
3781 struct subreg_info
*info
)
3783 unsigned int nregs_xmode
, nregs_ymode
;
3785 gcc_assert (xregno
< FIRST_PSEUDO_REGISTER
);
3787 poly_uint64 xsize
= GET_MODE_SIZE (xmode
);
3788 poly_uint64 ysize
= GET_MODE_SIZE (ymode
);
3790 bool rknown
= false;
3792 /* If the register representation of a non-scalar mode has holes in it,
3793 we expect the scalar units to be concatenated together, with the holes
3794 distributed evenly among the scalar units. Each scalar unit must occupy
3795 at least one register. */
3796 if (HARD_REGNO_NREGS_HAS_PADDING (xregno
, xmode
))
3798 /* As a consequence, we must be dealing with a constant number of
3799 scalars, and thus a constant offset and number of units. */
3800 HOST_WIDE_INT coffset
= offset
.to_constant ();
3801 HOST_WIDE_INT cysize
= ysize
.to_constant ();
3802 nregs_xmode
= HARD_REGNO_NREGS_WITH_PADDING (xregno
, xmode
);
3803 unsigned int nunits
= GET_MODE_NUNITS (xmode
).to_constant ();
3804 scalar_mode xmode_unit
= GET_MODE_INNER (xmode
);
3805 gcc_assert (HARD_REGNO_NREGS_HAS_PADDING (xregno
, xmode_unit
));
3806 gcc_assert (nregs_xmode
3808 * HARD_REGNO_NREGS_WITH_PADDING (xregno
, xmode_unit
)));
3809 gcc_assert (hard_regno_nregs (xregno
, xmode
)
3810 == hard_regno_nregs (xregno
, xmode_unit
) * nunits
);
3812 /* You can only ask for a SUBREG of a value with holes in the middle
3813 if you don't cross the holes. (Such a SUBREG should be done by
3814 picking a different register class, or doing it in memory if
3815 necessary.) An example of a value with holes is XCmode on 32-bit
3816 x86 with -m128bit-long-double; it's represented in 6 32-bit registers,
3817 3 for each part, but in memory it's two 128-bit parts.
3818 Padding is assumed to be at the end (not necessarily the 'high part')
3820 if ((coffset
/ GET_MODE_SIZE (xmode_unit
) + 1 < nunits
)
3821 && (coffset
/ GET_MODE_SIZE (xmode_unit
)
3822 != ((coffset
+ cysize
- 1) / GET_MODE_SIZE (xmode_unit
))))
3824 info
->representable_p
= false;
3829 nregs_xmode
= hard_regno_nregs (xregno
, xmode
);
3831 nregs_ymode
= hard_regno_nregs (xregno
, ymode
);
3833 /* Subreg sizes must be ordered, so that we can tell whether they are
3834 partial, paradoxical or complete. */
3835 gcc_checking_assert (ordered_p (xsize
, ysize
));
3837 /* Paradoxical subregs are otherwise valid. */
3838 if (!rknown
&& known_eq (offset
, 0U) && maybe_gt (ysize
, xsize
))
3840 info
->representable_p
= true;
3841 /* If this is a big endian paradoxical subreg, which uses more
3842 actual hard registers than the original register, we must
3843 return a negative offset so that we find the proper highpart
3846 We assume that the ordering of registers within a multi-register
3847 value has a consistent endianness: if bytes and register words
3848 have different endianness, the hard registers that make up a
3849 multi-register value must be at least word-sized. */
3850 if (REG_WORDS_BIG_ENDIAN
)
3851 info
->offset
= (int) nregs_xmode
- (int) nregs_ymode
;
3854 info
->nregs
= nregs_ymode
;
3858 /* If registers store different numbers of bits in the different
3859 modes, we cannot generally form this subreg. */
3860 poly_uint64 regsize_xmode
, regsize_ymode
;
3861 if (!HARD_REGNO_NREGS_HAS_PADDING (xregno
, xmode
)
3862 && !HARD_REGNO_NREGS_HAS_PADDING (xregno
, ymode
)
3863 && multiple_p (xsize
, nregs_xmode
, ®size_xmode
)
3864 && multiple_p (ysize
, nregs_ymode
, ®size_ymode
))
3867 && ((nregs_ymode
> 1 && maybe_gt (regsize_xmode
, regsize_ymode
))
3868 || (nregs_xmode
> 1 && maybe_gt (regsize_ymode
, regsize_xmode
))))
3870 info
->representable_p
= false;
3871 if (!can_div_away_from_zero_p (ysize
, regsize_xmode
, &info
->nregs
)
3872 || !can_div_trunc_p (offset
, regsize_xmode
, &info
->offset
))
3873 /* Checked by validate_subreg. We must know at compile time
3874 which inner registers are being accessed. */
3878 /* It's not valid to extract a subreg of mode YMODE at OFFSET that
3879 would go outside of XMODE. */
3880 if (!rknown
&& maybe_gt (ysize
+ offset
, xsize
))
3882 info
->representable_p
= false;
3883 info
->nregs
= nregs_ymode
;
3884 if (!can_div_trunc_p (offset
, regsize_xmode
, &info
->offset
))
3885 /* Checked by validate_subreg. We must know at compile time
3886 which inner registers are being accessed. */
3890 /* Quick exit for the simple and common case of extracting whole
3891 subregisters from a multiregister value. */
3892 /* ??? It would be better to integrate this into the code below,
3893 if we can generalize the concept enough and figure out how
3894 odd-sized modes can coexist with the other weird cases we support. */
3895 HOST_WIDE_INT count
;
3897 && WORDS_BIG_ENDIAN
== REG_WORDS_BIG_ENDIAN
3898 && known_eq (regsize_xmode
, regsize_ymode
)
3899 && constant_multiple_p (offset
, regsize_ymode
, &count
))
3901 info
->representable_p
= true;
3902 info
->nregs
= nregs_ymode
;
3903 info
->offset
= count
;
3904 gcc_assert (info
->offset
+ info
->nregs
<= (int) nregs_xmode
);
3909 /* Lowpart subregs are otherwise valid. */
3910 if (!rknown
&& known_eq (offset
, subreg_lowpart_offset (ymode
, xmode
)))
3912 info
->representable_p
= true;
3915 if (known_eq (offset
, 0U) || nregs_xmode
== nregs_ymode
)
3918 info
->nregs
= nregs_ymode
;
3923 /* Set NUM_BLOCKS to the number of independently-representable YMODE
3924 values there are in (reg:XMODE XREGNO). We can view the register
3925 as consisting of this number of independent "blocks", where each
3926 block occupies NREGS_YMODE registers and contains exactly one
3927 representable YMODE value. */
3928 gcc_assert ((nregs_xmode
% nregs_ymode
) == 0);
3929 unsigned int num_blocks
= nregs_xmode
/ nregs_ymode
;
3931 /* Calculate the number of bytes in each block. This must always
3932 be exact, otherwise we don't know how to verify the constraint.
3933 These conditions may be relaxed but subreg_regno_offset would
3934 need to be redesigned. */
3935 poly_uint64 bytes_per_block
= exact_div (xsize
, num_blocks
);
3937 /* Get the number of the first block that contains the subreg and the byte
3938 offset of the subreg from the start of that block. */
3939 unsigned int block_number
;
3940 poly_uint64 subblock_offset
;
3941 if (!can_div_trunc_p (offset
, bytes_per_block
, &block_number
,
3943 /* Checked by validate_subreg. We must know at compile time which
3944 inner registers are being accessed. */
3949 /* Only the lowpart of each block is representable. */
3950 info
->representable_p
3951 = known_eq (subblock_offset
,
3952 subreg_size_lowpart_offset (ysize
, bytes_per_block
));
3956 /* We assume that the ordering of registers within a multi-register
3957 value has a consistent endianness: if bytes and register words
3958 have different endianness, the hard registers that make up a
3959 multi-register value must be at least word-sized. */
3960 if (WORDS_BIG_ENDIAN
!= REG_WORDS_BIG_ENDIAN
)
3961 /* The block number we calculated above followed memory endianness.
3962 Convert it to register endianness by counting back from the end.
3963 (Note that, because of the assumption above, each block must be
3964 at least word-sized.) */
3965 info
->offset
= (num_blocks
- block_number
- 1) * nregs_ymode
;
3967 info
->offset
= block_number
* nregs_ymode
;
3968 info
->nregs
= nregs_ymode
;
3971 /* This function returns the regno offset of a subreg expression.
3972 xregno - A regno of an inner hard subreg_reg (or what will become one).
3973 xmode - The mode of xregno.
3974 offset - The byte offset.
3975 ymode - The mode of a top level SUBREG (or what may become one).
3976 RETURN - The regno offset which would be used. */
3978 subreg_regno_offset (unsigned int xregno
, machine_mode xmode
,
3979 poly_uint64 offset
, machine_mode ymode
)
3981 struct subreg_info info
;
3982 subreg_get_info (xregno
, xmode
, offset
, ymode
, &info
);
3986 /* This function returns true when the offset is representable via
3987 subreg_offset in the given regno.
3988 xregno - A regno of an inner hard subreg_reg (or what will become one).
3989 xmode - The mode of xregno.
3990 offset - The byte offset.
3991 ymode - The mode of a top level SUBREG (or what may become one).
3992 RETURN - Whether the offset is representable. */
3994 subreg_offset_representable_p (unsigned int xregno
, machine_mode xmode
,
3995 poly_uint64 offset
, machine_mode ymode
)
3997 struct subreg_info info
;
3998 subreg_get_info (xregno
, xmode
, offset
, ymode
, &info
);
3999 return info
.representable_p
;
4002 /* Return the number of a YMODE register to which
4004 (subreg:YMODE (reg:XMODE XREGNO) OFFSET)
4006 can be simplified. Return -1 if the subreg can't be simplified.
4008 XREGNO is a hard register number. */
4011 simplify_subreg_regno (unsigned int xregno
, machine_mode xmode
,
4012 poly_uint64 offset
, machine_mode ymode
)
4014 struct subreg_info info
;
4015 unsigned int yregno
;
4017 /* Give the backend a chance to disallow the mode change. */
4018 if (GET_MODE_CLASS (xmode
) != MODE_COMPLEX_INT
4019 && GET_MODE_CLASS (xmode
) != MODE_COMPLEX_FLOAT
4020 && !REG_CAN_CHANGE_MODE_P (xregno
, xmode
, ymode
)
4021 /* We can use mode change in LRA for some transformations. */
4022 && ! lra_in_progress
)
4025 /* We shouldn't simplify stack-related registers. */
4026 if ((!reload_completed
|| frame_pointer_needed
)
4027 && xregno
== FRAME_POINTER_REGNUM
)
4030 if (FRAME_POINTER_REGNUM
!= ARG_POINTER_REGNUM
4031 && xregno
== ARG_POINTER_REGNUM
)
4034 if (xregno
== STACK_POINTER_REGNUM
4035 /* We should convert hard stack register in LRA if it is
4037 && ! lra_in_progress
)
4040 /* Try to get the register offset. */
4041 subreg_get_info (xregno
, xmode
, offset
, ymode
, &info
);
4042 if (!info
.representable_p
)
4045 /* Make sure that the offsetted register value is in range. */
4046 yregno
= xregno
+ info
.offset
;
4047 if (!HARD_REGISTER_NUM_P (yregno
))
4050 /* See whether (reg:YMODE YREGNO) is valid.
4052 ??? We allow invalid registers if (reg:XMODE XREGNO) is also invalid.
4053 This is a kludge to work around how complex FP arguments are passed
4054 on IA-64 and should be fixed. See PR target/49226. */
4055 if (!targetm
.hard_regno_mode_ok (yregno
, ymode
)
4056 && targetm
.hard_regno_mode_ok (xregno
, xmode
))
4059 return (int) yregno
;
4062 /* Return the final regno that a subreg expression refers to. */
4064 subreg_regno (const_rtx x
)
4067 rtx subreg
= SUBREG_REG (x
);
4068 int regno
= REGNO (subreg
);
4070 ret
= regno
+ subreg_regno_offset (regno
,
4078 /* Return the number of registers that a subreg expression refers
4081 subreg_nregs (const_rtx x
)
4083 return subreg_nregs_with_regno (REGNO (SUBREG_REG (x
)), x
);
4086 /* Return the number of registers that a subreg REG with REGNO
4087 expression refers to. This is a copy of the rtlanal.c:subreg_nregs
4088 changed so that the regno can be passed in. */
4091 subreg_nregs_with_regno (unsigned int regno
, const_rtx x
)
4093 struct subreg_info info
;
4094 rtx subreg
= SUBREG_REG (x
);
4096 subreg_get_info (regno
, GET_MODE (subreg
), SUBREG_BYTE (x
), GET_MODE (x
),
4101 struct parms_set_data
4107 /* Helper function for noticing stores to parameter registers. */
4109 parms_set (rtx x
, const_rtx pat ATTRIBUTE_UNUSED
, void *data
)
4111 struct parms_set_data
*const d
= (struct parms_set_data
*) data
;
4112 if (REG_P (x
) && REGNO (x
) < FIRST_PSEUDO_REGISTER
4113 && TEST_HARD_REG_BIT (d
->regs
, REGNO (x
)))
4115 CLEAR_HARD_REG_BIT (d
->regs
, REGNO (x
));
4120 /* Look backward for first parameter to be loaded.
4121 Note that loads of all parameters will not necessarily be
4122 found if CSE has eliminated some of them (e.g., an argument
4123 to the outer function is passed down as a parameter).
4124 Do not skip BOUNDARY. */
4126 find_first_parameter_load (rtx_insn
*call_insn
, rtx_insn
*boundary
)
4128 struct parms_set_data parm
;
4130 rtx_insn
*before
, *first_set
;
4132 /* Since different machines initialize their parameter registers
4133 in different orders, assume nothing. Collect the set of all
4134 parameter registers. */
4135 CLEAR_HARD_REG_SET (parm
.regs
);
4137 for (p
= CALL_INSN_FUNCTION_USAGE (call_insn
); p
; p
= XEXP (p
, 1))
4138 if (GET_CODE (XEXP (p
, 0)) == USE
4139 && REG_P (XEXP (XEXP (p
, 0), 0))
4140 && !STATIC_CHAIN_REG_P (XEXP (XEXP (p
, 0), 0)))
4142 gcc_assert (REGNO (XEXP (XEXP (p
, 0), 0)) < FIRST_PSEUDO_REGISTER
);
4144 /* We only care about registers which can hold function
4146 if (!FUNCTION_ARG_REGNO_P (REGNO (XEXP (XEXP (p
, 0), 0))))
4149 SET_HARD_REG_BIT (parm
.regs
, REGNO (XEXP (XEXP (p
, 0), 0)));
4153 first_set
= call_insn
;
4155 /* Search backward for the first set of a register in this set. */
4156 while (parm
.nregs
&& before
!= boundary
)
4158 before
= PREV_INSN (before
);
4160 /* It is possible that some loads got CSEed from one call to
4161 another. Stop in that case. */
4162 if (CALL_P (before
))
4165 /* Our caller needs either ensure that we will find all sets
4166 (in case code has not been optimized yet), or take care
4167 for possible labels in a way by setting boundary to preceding
4169 if (LABEL_P (before
))
4171 gcc_assert (before
== boundary
);
4175 if (INSN_P (before
))
4177 int nregs_old
= parm
.nregs
;
4178 note_stores (before
, parms_set
, &parm
);
4179 /* If we found something that did not set a parameter reg,
4180 we're done. Do not keep going, as that might result
4181 in hoisting an insn before the setting of a pseudo
4182 that is used by the hoisted insn. */
4183 if (nregs_old
!= parm
.nregs
)
4192 /* Return true if we should avoid inserting code between INSN and preceding
4193 call instruction. */
4196 keep_with_call_p (const rtx_insn
*insn
)
4200 if (INSN_P (insn
) && (set
= single_set (insn
)) != NULL
)
4202 if (REG_P (SET_DEST (set
))
4203 && REGNO (SET_DEST (set
)) < FIRST_PSEUDO_REGISTER
4204 && fixed_regs
[REGNO (SET_DEST (set
))]
4205 && general_operand (SET_SRC (set
), VOIDmode
))
4207 if (REG_P (SET_SRC (set
))
4208 && targetm
.calls
.function_value_regno_p (REGNO (SET_SRC (set
)))
4209 && REG_P (SET_DEST (set
))
4210 && REGNO (SET_DEST (set
)) >= FIRST_PSEUDO_REGISTER
)
4212 /* There may be a stack pop just after the call and before the store
4213 of the return register. Search for the actual store when deciding
4214 if we can break or not. */
4215 if (SET_DEST (set
) == stack_pointer_rtx
)
4217 /* This CONST_CAST is okay because next_nonnote_insn just
4218 returns its argument and we assign it to a const_rtx
4221 = next_nonnote_insn (const_cast<rtx_insn
*> (insn
));
4222 if (i2
&& keep_with_call_p (i2
))
4229 /* Return true if LABEL is a target of JUMP_INSN. This applies only
4230 to non-complex jumps. That is, direct unconditional, conditional,
4231 and tablejumps, but not computed jumps or returns. It also does
4232 not apply to the fallthru case of a conditional jump. */
4235 label_is_jump_target_p (const_rtx label
, const rtx_insn
*jump_insn
)
4237 rtx tmp
= JUMP_LABEL (jump_insn
);
4238 rtx_jump_table_data
*table
;
4243 if (tablejump_p (jump_insn
, NULL
, &table
))
4245 rtvec vec
= table
->get_labels ();
4246 int i
, veclen
= GET_NUM_ELEM (vec
);
4248 for (i
= 0; i
< veclen
; ++i
)
4249 if (XEXP (RTVEC_ELT (vec
, i
), 0) == label
)
4253 if (find_reg_note (jump_insn
, REG_LABEL_TARGET
, label
))
4260 /* Return an estimate of the cost of computing rtx X.
4261 One use is in cse, to decide which expression to keep in the hash table.
4262 Another is in rtl generation, to pick the cheapest way to multiply.
4263 Other uses like the latter are expected in the future.
4265 X appears as operand OPNO in an expression with code OUTER_CODE.
4266 SPEED specifies whether costs optimized for speed or size should
4270 rtx_cost (rtx x
, machine_mode mode
, enum rtx_code outer_code
,
4271 int opno
, bool speed
)
4282 if (GET_MODE (x
) != VOIDmode
)
4283 mode
= GET_MODE (x
);
4285 /* A size N times larger than UNITS_PER_WORD likely needs N times as
4286 many insns, taking N times as long. */
4287 factor
= estimated_poly_value (GET_MODE_SIZE (mode
)) / UNITS_PER_WORD
;
4291 /* Compute the default costs of certain things.
4292 Note that targetm.rtx_costs can override the defaults. */
4294 code
= GET_CODE (x
);
4298 /* Multiplication has time-complexity O(N*N), where N is the
4299 number of units (translated from digits) when using
4300 schoolbook long multiplication. */
4301 total
= factor
* factor
* COSTS_N_INSNS (5);
4307 /* Similarly, complexity for schoolbook long division. */
4308 total
= factor
* factor
* COSTS_N_INSNS (7);
4311 /* Used in combine.c as a marker. */
4315 /* A SET doesn't have a mode, so let's look at the SET_DEST to get
4316 the mode for the factor. */
4317 mode
= GET_MODE (SET_DEST (x
));
4318 factor
= estimated_poly_value (GET_MODE_SIZE (mode
)) / UNITS_PER_WORD
;
4323 total
= factor
* COSTS_N_INSNS (1);
4333 /* If we can't tie these modes, make this expensive. The larger
4334 the mode, the more expensive it is. */
4335 if (!targetm
.modes_tieable_p (mode
, GET_MODE (SUBREG_REG (x
))))
4336 return COSTS_N_INSNS (2 + factor
);
4340 if (targetm
.modes_tieable_p (mode
, GET_MODE (XEXP (x
, 0))))
4347 if (targetm
.rtx_costs (x
, mode
, outer_code
, opno
, &total
, speed
))
4352 /* Sum the costs of the sub-rtx's, plus cost of this operation,
4353 which is already in total. */
4355 fmt
= GET_RTX_FORMAT (code
);
4356 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
4358 total
+= rtx_cost (XEXP (x
, i
), mode
, code
, i
, speed
);
4359 else if (fmt
[i
] == 'E')
4360 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
4361 total
+= rtx_cost (XVECEXP (x
, i
, j
), mode
, code
, i
, speed
);
4366 /* Fill in the structure C with information about both speed and size rtx
4367 costs for X, which is operand OPNO in an expression with code OUTER. */
4370 get_full_rtx_cost (rtx x
, machine_mode mode
, enum rtx_code outer
, int opno
,
4371 struct full_rtx_costs
*c
)
4373 c
->speed
= rtx_cost (x
, mode
, outer
, opno
, true);
4374 c
->size
= rtx_cost (x
, mode
, outer
, opno
, false);
4378 /* Return cost of address expression X.
4379 Expect that X is properly formed address reference.
4381 SPEED parameter specify whether costs optimized for speed or size should
4385 address_cost (rtx x
, machine_mode mode
, addr_space_t as
, bool speed
)
4387 /* We may be asked for cost of various unusual addresses, such as operands
4388 of push instruction. It is not worthwhile to complicate writing
4389 of the target hook by such cases. */
4391 if (!memory_address_addr_space_p (mode
, x
, as
))
4394 return targetm
.address_cost (x
, mode
, as
, speed
);
4397 /* If the target doesn't override, compute the cost as with arithmetic. */
4400 default_address_cost (rtx x
, machine_mode
, addr_space_t
, bool speed
)
4402 return rtx_cost (x
, Pmode
, MEM
, 0, speed
);
4406 unsigned HOST_WIDE_INT
4407 nonzero_bits (const_rtx x
, machine_mode mode
)
4409 if (mode
== VOIDmode
)
4410 mode
= GET_MODE (x
);
4411 scalar_int_mode int_mode
;
4412 if (!is_a
<scalar_int_mode
> (mode
, &int_mode
))
4413 return GET_MODE_MASK (mode
);
4414 return cached_nonzero_bits (x
, int_mode
, NULL_RTX
, VOIDmode
, 0);
4418 num_sign_bit_copies (const_rtx x
, machine_mode mode
)
4420 if (mode
== VOIDmode
)
4421 mode
= GET_MODE (x
);
4422 scalar_int_mode int_mode
;
4423 if (!is_a
<scalar_int_mode
> (mode
, &int_mode
))
4425 return cached_num_sign_bit_copies (x
, int_mode
, NULL_RTX
, VOIDmode
, 0);
4428 /* Return true if nonzero_bits1 might recurse into both operands
4432 nonzero_bits_binary_arith_p (const_rtx x
)
4434 if (!ARITHMETIC_P (x
))
4436 switch (GET_CODE (x
))
4458 /* The function cached_nonzero_bits is a wrapper around nonzero_bits1.
4459 It avoids exponential behavior in nonzero_bits1 when X has
4460 identical subexpressions on the first or the second level. */
4462 static unsigned HOST_WIDE_INT
4463 cached_nonzero_bits (const_rtx x
, scalar_int_mode mode
, const_rtx known_x
,
4464 machine_mode known_mode
,
4465 unsigned HOST_WIDE_INT known_ret
)
4467 if (x
== known_x
&& mode
== known_mode
)
4470 /* Try to find identical subexpressions. If found call
4471 nonzero_bits1 on X with the subexpressions as KNOWN_X and the
4472 precomputed value for the subexpression as KNOWN_RET. */
4474 if (nonzero_bits_binary_arith_p (x
))
4476 rtx x0
= XEXP (x
, 0);
4477 rtx x1
= XEXP (x
, 1);
4479 /* Check the first level. */
4481 return nonzero_bits1 (x
, mode
, x0
, mode
,
4482 cached_nonzero_bits (x0
, mode
, known_x
,
4483 known_mode
, known_ret
));
4485 /* Check the second level. */
4486 if (nonzero_bits_binary_arith_p (x0
)
4487 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
4488 return nonzero_bits1 (x
, mode
, x1
, mode
,
4489 cached_nonzero_bits (x1
, mode
, known_x
,
4490 known_mode
, known_ret
));
4492 if (nonzero_bits_binary_arith_p (x1
)
4493 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
4494 return nonzero_bits1 (x
, mode
, x0
, mode
,
4495 cached_nonzero_bits (x0
, mode
, known_x
,
4496 known_mode
, known_ret
));
4499 return nonzero_bits1 (x
, mode
, known_x
, known_mode
, known_ret
);
4502 /* We let num_sign_bit_copies recur into nonzero_bits as that is useful.
4503 We don't let nonzero_bits recur into num_sign_bit_copies, because that
4504 is less useful. We can't allow both, because that results in exponential
4505 run time recursion. There is a nullstone testcase that triggered
4506 this. This macro avoids accidental uses of num_sign_bit_copies. */
4507 #define cached_num_sign_bit_copies sorry_i_am_preventing_exponential_behavior
4509 /* Given an expression, X, compute which bits in X can be nonzero.
4510 We don't care about bits outside of those defined in MODE.
4512 For most X this is simply GET_MODE_MASK (GET_MODE (X)), but if X is
4513 an arithmetic operation, we can do better. */
4515 static unsigned HOST_WIDE_INT
4516 nonzero_bits1 (const_rtx x
, scalar_int_mode mode
, const_rtx known_x
,
4517 machine_mode known_mode
,
4518 unsigned HOST_WIDE_INT known_ret
)
4520 unsigned HOST_WIDE_INT nonzero
= GET_MODE_MASK (mode
);
4521 unsigned HOST_WIDE_INT inner_nz
;
4522 enum rtx_code code
= GET_CODE (x
);
4523 machine_mode inner_mode
;
4524 unsigned int inner_width
;
4525 scalar_int_mode xmode
;
4527 unsigned int mode_width
= GET_MODE_PRECISION (mode
);
4529 if (CONST_INT_P (x
))
4531 if (SHORT_IMMEDIATES_SIGN_EXTEND
4533 && mode_width
< BITS_PER_WORD
4534 && (UINTVAL (x
) & (HOST_WIDE_INT_1U
<< (mode_width
- 1))) != 0)
4535 return UINTVAL (x
) | (HOST_WIDE_INT_M1U
<< mode_width
);
4540 if (!is_a
<scalar_int_mode
> (GET_MODE (x
), &xmode
))
4542 unsigned int xmode_width
= GET_MODE_PRECISION (xmode
);
4544 /* If X is wider than MODE, use its mode instead. */
4545 if (xmode_width
> mode_width
)
4548 nonzero
= GET_MODE_MASK (mode
);
4549 mode_width
= xmode_width
;
4552 if (mode_width
> HOST_BITS_PER_WIDE_INT
)
4553 /* Our only callers in this case look for single bit values. So
4554 just return the mode mask. Those tests will then be false. */
4557 /* If MODE is wider than X, but both are a single word for both the host
4558 and target machines, we can compute this from which bits of the object
4559 might be nonzero in its own mode, taking into account the fact that, on
4560 CISC machines, accessing an object in a wider mode generally causes the
4561 high-order bits to become undefined, so they are not known to be zero.
4562 We extend this reasoning to RISC machines for operations that might not
4563 operate on the full registers. */
4564 if (mode_width
> xmode_width
4565 && xmode_width
<= BITS_PER_WORD
4566 && xmode_width
<= HOST_BITS_PER_WIDE_INT
4567 && !(WORD_REGISTER_OPERATIONS
&& word_register_operation_p (x
)))
4569 nonzero
&= cached_nonzero_bits (x
, xmode
,
4570 known_x
, known_mode
, known_ret
);
4571 nonzero
|= GET_MODE_MASK (mode
) & ~GET_MODE_MASK (xmode
);
4575 /* Please keep nonzero_bits_binary_arith_p above in sync with
4576 the code in the switch below. */
4580 #if defined(POINTERS_EXTEND_UNSIGNED)
4581 /* If pointers extend unsigned and this is a pointer in Pmode, say that
4582 all the bits above ptr_mode are known to be zero. */
4583 /* As we do not know which address space the pointer is referring to,
4584 we can do this only if the target does not support different pointer
4585 or address modes depending on the address space. */
4586 if (target_default_pointer_address_modes_p ()
4587 && POINTERS_EXTEND_UNSIGNED
4590 && !targetm
.have_ptr_extend ())
4591 nonzero
&= GET_MODE_MASK (ptr_mode
);
4594 /* Include declared information about alignment of pointers. */
4595 /* ??? We don't properly preserve REG_POINTER changes across
4596 pointer-to-integer casts, so we can't trust it except for
4597 things that we know must be pointers. See execute/960116-1.c. */
4598 if ((x
== stack_pointer_rtx
4599 || x
== frame_pointer_rtx
4600 || x
== arg_pointer_rtx
)
4601 && REGNO_POINTER_ALIGN (REGNO (x
)))
4603 unsigned HOST_WIDE_INT alignment
4604 = REGNO_POINTER_ALIGN (REGNO (x
)) / BITS_PER_UNIT
;
4606 #ifdef PUSH_ROUNDING
4607 /* If PUSH_ROUNDING is defined, it is possible for the
4608 stack to be momentarily aligned only to that amount,
4609 so we pick the least alignment. */
4610 if (x
== stack_pointer_rtx
&& PUSH_ARGS
)
4612 poly_uint64 rounded_1
= PUSH_ROUNDING (poly_int64 (1));
4613 alignment
= MIN (known_alignment (rounded_1
), alignment
);
4617 nonzero
&= ~(alignment
- 1);
4621 unsigned HOST_WIDE_INT nonzero_for_hook
= nonzero
;
4622 rtx new_rtx
= rtl_hooks
.reg_nonzero_bits (x
, xmode
, mode
,
4626 nonzero_for_hook
&= cached_nonzero_bits (new_rtx
, mode
, known_x
,
4627 known_mode
, known_ret
);
4629 return nonzero_for_hook
;
4633 /* In many, if not most, RISC machines, reading a byte from memory
4634 zeros the rest of the register. Noticing that fact saves a lot
4635 of extra zero-extends. */
4636 if (load_extend_op (xmode
) == ZERO_EXTEND
)
4637 nonzero
&= GET_MODE_MASK (xmode
);
4641 case UNEQ
: case LTGT
:
4642 case GT
: case GTU
: case UNGT
:
4643 case LT
: case LTU
: case UNLT
:
4644 case GE
: case GEU
: case UNGE
:
4645 case LE
: case LEU
: case UNLE
:
4646 case UNORDERED
: case ORDERED
:
4647 /* If this produces an integer result, we know which bits are set.
4648 Code here used to clear bits outside the mode of X, but that is
4650 /* Mind that MODE is the mode the caller wants to look at this
4651 operation in, and not the actual operation mode. We can wind
4652 up with (subreg:DI (gt:V4HI x y)), and we don't have anything
4653 that describes the results of a vector compare. */
4654 if (GET_MODE_CLASS (xmode
) == MODE_INT
4655 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
4656 nonzero
= STORE_FLAG_VALUE
;
4661 /* Disabled to avoid exponential mutual recursion between nonzero_bits
4662 and num_sign_bit_copies. */
4663 if (num_sign_bit_copies (XEXP (x
, 0), xmode
) == xmode_width
)
4667 if (xmode_width
< mode_width
)
4668 nonzero
|= (GET_MODE_MASK (mode
) & ~GET_MODE_MASK (xmode
));
4673 /* Disabled to avoid exponential mutual recursion between nonzero_bits
4674 and num_sign_bit_copies. */
4675 if (num_sign_bit_copies (XEXP (x
, 0), xmode
) == xmode_width
)
4681 nonzero
&= (cached_nonzero_bits (XEXP (x
, 0), mode
,
4682 known_x
, known_mode
, known_ret
)
4683 & GET_MODE_MASK (mode
));
4687 nonzero
&= cached_nonzero_bits (XEXP (x
, 0), mode
,
4688 known_x
, known_mode
, known_ret
);
4689 if (GET_MODE (XEXP (x
, 0)) != VOIDmode
)
4690 nonzero
&= GET_MODE_MASK (GET_MODE (XEXP (x
, 0)));
4694 /* If the sign bit is known clear, this is the same as ZERO_EXTEND.
4695 Otherwise, show all the bits in the outer mode but not the inner
4697 inner_nz
= cached_nonzero_bits (XEXP (x
, 0), mode
,
4698 known_x
, known_mode
, known_ret
);
4699 if (GET_MODE (XEXP (x
, 0)) != VOIDmode
)
4701 inner_nz
&= GET_MODE_MASK (GET_MODE (XEXP (x
, 0)));
4702 if (val_signbit_known_set_p (GET_MODE (XEXP (x
, 0)), inner_nz
))
4703 inner_nz
|= (GET_MODE_MASK (mode
)
4704 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0))));
4707 nonzero
&= inner_nz
;
4711 nonzero
&= cached_nonzero_bits (XEXP (x
, 0), mode
,
4712 known_x
, known_mode
, known_ret
)
4713 & cached_nonzero_bits (XEXP (x
, 1), mode
,
4714 known_x
, known_mode
, known_ret
);
4718 case UMIN
: case UMAX
: case SMIN
: case SMAX
:
4720 unsigned HOST_WIDE_INT nonzero0
4721 = cached_nonzero_bits (XEXP (x
, 0), mode
,
4722 known_x
, known_mode
, known_ret
);
4724 /* Don't call nonzero_bits for the second time if it cannot change
4726 if ((nonzero
& nonzero0
) != nonzero
)
4728 | cached_nonzero_bits (XEXP (x
, 1), mode
,
4729 known_x
, known_mode
, known_ret
);
4733 case PLUS
: case MINUS
:
4735 case DIV
: case UDIV
:
4736 case MOD
: case UMOD
:
4737 /* We can apply the rules of arithmetic to compute the number of
4738 high- and low-order zero bits of these operations. We start by
4739 computing the width (position of the highest-order nonzero bit)
4740 and the number of low-order zero bits for each value. */
4742 unsigned HOST_WIDE_INT nz0
4743 = cached_nonzero_bits (XEXP (x
, 0), mode
,
4744 known_x
, known_mode
, known_ret
);
4745 unsigned HOST_WIDE_INT nz1
4746 = cached_nonzero_bits (XEXP (x
, 1), mode
,
4747 known_x
, known_mode
, known_ret
);
4748 int sign_index
= xmode_width
- 1;
4749 int width0
= floor_log2 (nz0
) + 1;
4750 int width1
= floor_log2 (nz1
) + 1;
4751 int low0
= ctz_or_zero (nz0
);
4752 int low1
= ctz_or_zero (nz1
);
4753 unsigned HOST_WIDE_INT op0_maybe_minusp
4754 = nz0
& (HOST_WIDE_INT_1U
<< sign_index
);
4755 unsigned HOST_WIDE_INT op1_maybe_minusp
4756 = nz1
& (HOST_WIDE_INT_1U
<< sign_index
);
4757 unsigned int result_width
= mode_width
;
4763 result_width
= MAX (width0
, width1
) + 1;
4764 result_low
= MIN (low0
, low1
);
4767 result_low
= MIN (low0
, low1
);
4770 result_width
= width0
+ width1
;
4771 result_low
= low0
+ low1
;
4776 if (!op0_maybe_minusp
&& !op1_maybe_minusp
)
4777 result_width
= width0
;
4782 result_width
= width0
;
4787 if (!op0_maybe_minusp
&& !op1_maybe_minusp
)
4788 result_width
= MIN (width0
, width1
);
4789 result_low
= MIN (low0
, low1
);
4794 result_width
= MIN (width0
, width1
);
4795 result_low
= MIN (low0
, low1
);
4801 if (result_width
< mode_width
)
4802 nonzero
&= (HOST_WIDE_INT_1U
<< result_width
) - 1;
4805 nonzero
&= ~((HOST_WIDE_INT_1U
<< result_low
) - 1);
4810 if (CONST_INT_P (XEXP (x
, 1))
4811 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
)
4812 nonzero
&= (HOST_WIDE_INT_1U
<< INTVAL (XEXP (x
, 1))) - 1;
4816 /* If this is a SUBREG formed for a promoted variable that has
4817 been zero-extended, we know that at least the high-order bits
4818 are zero, though others might be too. */
4819 if (SUBREG_PROMOTED_VAR_P (x
) && SUBREG_PROMOTED_UNSIGNED_P (x
))
4820 nonzero
= GET_MODE_MASK (xmode
)
4821 & cached_nonzero_bits (SUBREG_REG (x
), xmode
,
4822 known_x
, known_mode
, known_ret
);
4824 /* If the inner mode is a single word for both the host and target
4825 machines, we can compute this from which bits of the inner
4826 object might be nonzero. */
4827 inner_mode
= GET_MODE (SUBREG_REG (x
));
4828 if (GET_MODE_PRECISION (inner_mode
).is_constant (&inner_width
)
4829 && inner_width
<= BITS_PER_WORD
4830 && inner_width
<= HOST_BITS_PER_WIDE_INT
)
4832 nonzero
&= cached_nonzero_bits (SUBREG_REG (x
), mode
,
4833 known_x
, known_mode
, known_ret
);
4835 /* On a typical CISC machine, accessing an object in a wider mode
4836 causes the high-order bits to become undefined. So they are
4837 not known to be zero.
4839 On a typical RISC machine, we only have to worry about the way
4840 loads are extended. Otherwise, if we get a reload for the inner
4841 part, it may be loaded from the stack, and then we may lose all
4842 the zero bits that existed before the store to the stack. */
4844 if ((!WORD_REGISTER_OPERATIONS
4845 || ((extend_op
= load_extend_op (inner_mode
)) == SIGN_EXTEND
4846 ? val_signbit_known_set_p (inner_mode
, nonzero
)
4847 : extend_op
!= ZERO_EXTEND
)
4848 || !MEM_P (SUBREG_REG (x
)))
4849 && xmode_width
> inner_width
)
4851 |= (GET_MODE_MASK (GET_MODE (x
)) & ~GET_MODE_MASK (inner_mode
));
4860 /* The nonzero bits are in two classes: any bits within MODE
4861 that aren't in xmode are always significant. The rest of the
4862 nonzero bits are those that are significant in the operand of
4863 the shift when shifted the appropriate number of bits. This
4864 shows that high-order bits are cleared by the right shift and
4865 low-order bits by left shifts. */
4866 if (CONST_INT_P (XEXP (x
, 1))
4867 && INTVAL (XEXP (x
, 1)) >= 0
4868 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
4869 && INTVAL (XEXP (x
, 1)) < xmode_width
)
4871 int count
= INTVAL (XEXP (x
, 1));
4872 unsigned HOST_WIDE_INT mode_mask
= GET_MODE_MASK (xmode
);
4873 unsigned HOST_WIDE_INT op_nonzero
4874 = cached_nonzero_bits (XEXP (x
, 0), mode
,
4875 known_x
, known_mode
, known_ret
);
4876 unsigned HOST_WIDE_INT inner
= op_nonzero
& mode_mask
;
4877 unsigned HOST_WIDE_INT outer
= 0;
4879 if (mode_width
> xmode_width
)
4880 outer
= (op_nonzero
& nonzero
& ~mode_mask
);
4895 /* If the sign bit may have been nonzero before the shift, we
4896 need to mark all the places it could have been copied to
4897 by the shift as possibly nonzero. */
4898 if (inner
& (HOST_WIDE_INT_1U
<< (xmode_width
- 1 - count
)))
4899 inner
|= (((HOST_WIDE_INT_1U
<< count
) - 1)
4900 << (xmode_width
- count
));
4904 inner
= (inner
<< (count
% xmode_width
)
4905 | (inner
>> (xmode_width
- (count
% xmode_width
))))
4910 inner
= (inner
>> (count
% xmode_width
)
4911 | (inner
<< (xmode_width
- (count
% xmode_width
))))
4919 nonzero
&= (outer
| inner
);
4925 /* This is at most the number of bits in the mode. */
4926 nonzero
= ((unsigned HOST_WIDE_INT
) 2 << (floor_log2 (mode_width
))) - 1;
4930 /* If CLZ has a known value at zero, then the nonzero bits are
4931 that value, plus the number of bits in the mode minus one. */
4932 if (CLZ_DEFINED_VALUE_AT_ZERO (mode
, nonzero
))
4934 |= (HOST_WIDE_INT_1U
<< (floor_log2 (mode_width
))) - 1;
4940 /* If CTZ has a known value at zero, then the nonzero bits are
4941 that value, plus the number of bits in the mode minus one. */
4942 if (CTZ_DEFINED_VALUE_AT_ZERO (mode
, nonzero
))
4944 |= (HOST_WIDE_INT_1U
<< (floor_log2 (mode_width
))) - 1;
4950 /* This is at most the number of bits in the mode minus 1. */
4951 nonzero
= (HOST_WIDE_INT_1U
<< (floor_log2 (mode_width
))) - 1;
4960 unsigned HOST_WIDE_INT nonzero_true
4961 = cached_nonzero_bits (XEXP (x
, 1), mode
,
4962 known_x
, known_mode
, known_ret
);
4964 /* Don't call nonzero_bits for the second time if it cannot change
4966 if ((nonzero
& nonzero_true
) != nonzero
)
4967 nonzero
&= nonzero_true
4968 | cached_nonzero_bits (XEXP (x
, 2), mode
,
4969 known_x
, known_mode
, known_ret
);
4980 /* See the macro definition above. */
4981 #undef cached_num_sign_bit_copies
4984 /* Return true if num_sign_bit_copies1 might recurse into both operands
4988 num_sign_bit_copies_binary_arith_p (const_rtx x
)
4990 if (!ARITHMETIC_P (x
))
4992 switch (GET_CODE (x
))
5010 /* The function cached_num_sign_bit_copies is a wrapper around
5011 num_sign_bit_copies1. It avoids exponential behavior in
5012 num_sign_bit_copies1 when X has identical subexpressions on the
5013 first or the second level. */
5016 cached_num_sign_bit_copies (const_rtx x
, scalar_int_mode mode
,
5017 const_rtx known_x
, machine_mode known_mode
,
5018 unsigned int known_ret
)
5020 if (x
== known_x
&& mode
== known_mode
)
5023 /* Try to find identical subexpressions. If found call
5024 num_sign_bit_copies1 on X with the subexpressions as KNOWN_X and
5025 the precomputed value for the subexpression as KNOWN_RET. */
5027 if (num_sign_bit_copies_binary_arith_p (x
))
5029 rtx x0
= XEXP (x
, 0);
5030 rtx x1
= XEXP (x
, 1);
5032 /* Check the first level. */
5035 num_sign_bit_copies1 (x
, mode
, x0
, mode
,
5036 cached_num_sign_bit_copies (x0
, mode
, known_x
,
5040 /* Check the second level. */
5041 if (num_sign_bit_copies_binary_arith_p (x0
)
5042 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
5044 num_sign_bit_copies1 (x
, mode
, x1
, mode
,
5045 cached_num_sign_bit_copies (x1
, mode
, known_x
,
5049 if (num_sign_bit_copies_binary_arith_p (x1
)
5050 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
5052 num_sign_bit_copies1 (x
, mode
, x0
, mode
,
5053 cached_num_sign_bit_copies (x0
, mode
, known_x
,
5058 return num_sign_bit_copies1 (x
, mode
, known_x
, known_mode
, known_ret
);
5061 /* Return the number of bits at the high-order end of X that are known to
5062 be equal to the sign bit. X will be used in mode MODE. The returned
5063 value will always be between 1 and the number of bits in MODE. */
5066 num_sign_bit_copies1 (const_rtx x
, scalar_int_mode mode
, const_rtx known_x
,
5067 machine_mode known_mode
,
5068 unsigned int known_ret
)
5070 enum rtx_code code
= GET_CODE (x
);
5071 unsigned int bitwidth
= GET_MODE_PRECISION (mode
);
5072 int num0
, num1
, result
;
5073 unsigned HOST_WIDE_INT nonzero
;
5075 if (CONST_INT_P (x
))
5077 /* If the constant is negative, take its 1's complement and remask.
5078 Then see how many zero bits we have. */
5079 nonzero
= UINTVAL (x
) & GET_MODE_MASK (mode
);
5080 if (bitwidth
<= HOST_BITS_PER_WIDE_INT
5081 && (nonzero
& (HOST_WIDE_INT_1U
<< (bitwidth
- 1))) != 0)
5082 nonzero
= (~nonzero
) & GET_MODE_MASK (mode
);
5084 return (nonzero
== 0 ? bitwidth
: bitwidth
- floor_log2 (nonzero
) - 1);
5087 scalar_int_mode xmode
, inner_mode
;
5088 if (!is_a
<scalar_int_mode
> (GET_MODE (x
), &xmode
))
5091 unsigned int xmode_width
= GET_MODE_PRECISION (xmode
);
5093 /* For a smaller mode, just ignore the high bits. */
5094 if (bitwidth
< xmode_width
)
5096 num0
= cached_num_sign_bit_copies (x
, xmode
,
5097 known_x
, known_mode
, known_ret
);
5098 return MAX (1, num0
- (int) (xmode_width
- bitwidth
));
5101 if (bitwidth
> xmode_width
)
5103 /* If this machine does not do all register operations on the entire
5104 register and MODE is wider than the mode of X, we can say nothing
5105 at all about the high-order bits. We extend this reasoning to RISC
5106 machines for operations that might not operate on full registers. */
5107 if (!(WORD_REGISTER_OPERATIONS
&& word_register_operation_p (x
)))
5110 /* Likewise on machines that do, if the mode of the object is smaller
5111 than a word and loads of that size don't sign extend, we can say
5112 nothing about the high order bits. */
5113 if (xmode_width
< BITS_PER_WORD
5114 && load_extend_op (xmode
) != SIGN_EXTEND
)
5118 /* Please keep num_sign_bit_copies_binary_arith_p above in sync with
5119 the code in the switch below. */
5124 #if defined(POINTERS_EXTEND_UNSIGNED)
5125 /* If pointers extend signed and this is a pointer in Pmode, say that
5126 all the bits above ptr_mode are known to be sign bit copies. */
5127 /* As we do not know which address space the pointer is referring to,
5128 we can do this only if the target does not support different pointer
5129 or address modes depending on the address space. */
5130 if (target_default_pointer_address_modes_p ()
5131 && ! POINTERS_EXTEND_UNSIGNED
&& xmode
== Pmode
5132 && mode
== Pmode
&& REG_POINTER (x
)
5133 && !targetm
.have_ptr_extend ())
5134 return GET_MODE_PRECISION (Pmode
) - GET_MODE_PRECISION (ptr_mode
) + 1;
5138 unsigned int copies_for_hook
= 1, copies
= 1;
5139 rtx new_rtx
= rtl_hooks
.reg_num_sign_bit_copies (x
, xmode
, mode
,
5143 copies
= cached_num_sign_bit_copies (new_rtx
, mode
, known_x
,
5144 known_mode
, known_ret
);
5146 if (copies
> 1 || copies_for_hook
> 1)
5147 return MAX (copies
, copies_for_hook
);
5149 /* Else, use nonzero_bits to guess num_sign_bit_copies (see below). */
5154 /* Some RISC machines sign-extend all loads of smaller than a word. */
5155 if (load_extend_op (xmode
) == SIGN_EXTEND
)
5156 return MAX (1, ((int) bitwidth
- (int) xmode_width
+ 1));
5160 /* If this is a SUBREG for a promoted object that is sign-extended
5161 and we are looking at it in a wider mode, we know that at least the
5162 high-order bits are known to be sign bit copies. */
5164 if (SUBREG_PROMOTED_VAR_P (x
) && SUBREG_PROMOTED_SIGNED_P (x
))
5166 num0
= cached_num_sign_bit_copies (SUBREG_REG (x
), mode
,
5167 known_x
, known_mode
, known_ret
);
5168 return MAX ((int) bitwidth
- (int) xmode_width
+ 1, num0
);
5171 if (is_a
<scalar_int_mode
> (GET_MODE (SUBREG_REG (x
)), &inner_mode
))
5173 /* For a smaller object, just ignore the high bits. */
5174 if (bitwidth
<= GET_MODE_PRECISION (inner_mode
))
5176 num0
= cached_num_sign_bit_copies (SUBREG_REG (x
), inner_mode
,
5177 known_x
, known_mode
,
5179 return MAX (1, num0
- (int) (GET_MODE_PRECISION (inner_mode
)
5183 /* For paradoxical SUBREGs on machines where all register operations
5184 affect the entire register, just look inside. Note that we are
5185 passing MODE to the recursive call, so the number of sign bit
5186 copies will remain relative to that mode, not the inner mode.
5188 This works only if loads sign extend. Otherwise, if we get a
5189 reload for the inner part, it may be loaded from the stack, and
5190 then we lose all sign bit copies that existed before the store
5192 if (WORD_REGISTER_OPERATIONS
5193 && load_extend_op (inner_mode
) == SIGN_EXTEND
5194 && paradoxical_subreg_p (x
)
5195 && MEM_P (SUBREG_REG (x
)))
5196 return cached_num_sign_bit_copies (SUBREG_REG (x
), mode
,
5197 known_x
, known_mode
, known_ret
);
5202 if (CONST_INT_P (XEXP (x
, 1)))
5203 return MAX (1, (int) bitwidth
- INTVAL (XEXP (x
, 1)));
5207 if (is_a
<scalar_int_mode
> (GET_MODE (XEXP (x
, 0)), &inner_mode
))
5208 return (bitwidth
- GET_MODE_PRECISION (inner_mode
)
5209 + cached_num_sign_bit_copies (XEXP (x
, 0), inner_mode
,
5210 known_x
, known_mode
, known_ret
));
5214 /* For a smaller object, just ignore the high bits. */
5215 inner_mode
= as_a
<scalar_int_mode
> (GET_MODE (XEXP (x
, 0)));
5216 num0
= cached_num_sign_bit_copies (XEXP (x
, 0), inner_mode
,
5217 known_x
, known_mode
, known_ret
);
5218 return MAX (1, (num0
- (int) (GET_MODE_PRECISION (inner_mode
)
5222 return cached_num_sign_bit_copies (XEXP (x
, 0), mode
,
5223 known_x
, known_mode
, known_ret
);
5225 case ROTATE
: case ROTATERT
:
5226 /* If we are rotating left by a number of bits less than the number
5227 of sign bit copies, we can just subtract that amount from the
5229 if (CONST_INT_P (XEXP (x
, 1))
5230 && INTVAL (XEXP (x
, 1)) >= 0
5231 && INTVAL (XEXP (x
, 1)) < (int) bitwidth
)
5233 num0
= cached_num_sign_bit_copies (XEXP (x
, 0), mode
,
5234 known_x
, known_mode
, known_ret
);
5235 return MAX (1, num0
- (code
== ROTATE
? INTVAL (XEXP (x
, 1))
5236 : (int) bitwidth
- INTVAL (XEXP (x
, 1))));
5241 /* In general, this subtracts one sign bit copy. But if the value
5242 is known to be positive, the number of sign bit copies is the
5243 same as that of the input. Finally, if the input has just one bit
5244 that might be nonzero, all the bits are copies of the sign bit. */
5245 num0
= cached_num_sign_bit_copies (XEXP (x
, 0), mode
,
5246 known_x
, known_mode
, known_ret
);
5247 if (bitwidth
> HOST_BITS_PER_WIDE_INT
)
5248 return num0
> 1 ? num0
- 1 : 1;
5250 nonzero
= nonzero_bits (XEXP (x
, 0), mode
);
5255 && ((HOST_WIDE_INT_1U
<< (bitwidth
- 1)) & nonzero
))
5260 case IOR
: case AND
: case XOR
:
5261 case SMIN
: case SMAX
: case UMIN
: case UMAX
:
5262 /* Logical operations will preserve the number of sign-bit copies.
5263 MIN and MAX operations always return one of the operands. */
5264 num0
= cached_num_sign_bit_copies (XEXP (x
, 0), mode
,
5265 known_x
, known_mode
, known_ret
);
5266 num1
= cached_num_sign_bit_copies (XEXP (x
, 1), mode
,
5267 known_x
, known_mode
, known_ret
);
5269 /* If num1 is clearing some of the top bits then regardless of
5270 the other term, we are guaranteed to have at least that many
5271 high-order zero bits. */
5274 && bitwidth
<= HOST_BITS_PER_WIDE_INT
5275 && CONST_INT_P (XEXP (x
, 1))
5276 && (UINTVAL (XEXP (x
, 1))
5277 & (HOST_WIDE_INT_1U
<< (bitwidth
- 1))) == 0)
5280 /* Similarly for IOR when setting high-order bits. */
5283 && bitwidth
<= HOST_BITS_PER_WIDE_INT
5284 && CONST_INT_P (XEXP (x
, 1))
5285 && (UINTVAL (XEXP (x
, 1))
5286 & (HOST_WIDE_INT_1U
<< (bitwidth
- 1))) != 0)
5289 return MIN (num0
, num1
);
5291 case PLUS
: case MINUS
:
5292 /* For addition and subtraction, we can have a 1-bit carry. However,
5293 if we are subtracting 1 from a positive number, there will not
5294 be such a carry. Furthermore, if the positive number is known to
5295 be 0 or 1, we know the result is either -1 or 0. */
5297 if (code
== PLUS
&& XEXP (x
, 1) == constm1_rtx
5298 && bitwidth
<= HOST_BITS_PER_WIDE_INT
)
5300 nonzero
= nonzero_bits (XEXP (x
, 0), mode
);
5301 if (((HOST_WIDE_INT_1U
<< (bitwidth
- 1)) & nonzero
) == 0)
5302 return (nonzero
== 1 || nonzero
== 0 ? bitwidth
5303 : bitwidth
- floor_log2 (nonzero
) - 1);
5306 num0
= cached_num_sign_bit_copies (XEXP (x
, 0), mode
,
5307 known_x
, known_mode
, known_ret
);
5308 num1
= cached_num_sign_bit_copies (XEXP (x
, 1), mode
,
5309 known_x
, known_mode
, known_ret
);
5310 result
= MAX (1, MIN (num0
, num1
) - 1);
5315 /* The number of bits of the product is the sum of the number of
5316 bits of both terms. However, unless one of the terms if known
5317 to be positive, we must allow for an additional bit since negating
5318 a negative number can remove one sign bit copy. */
5320 num0
= cached_num_sign_bit_copies (XEXP (x
, 0), mode
,
5321 known_x
, known_mode
, known_ret
);
5322 num1
= cached_num_sign_bit_copies (XEXP (x
, 1), mode
,
5323 known_x
, known_mode
, known_ret
);
5325 result
= bitwidth
- (bitwidth
- num0
) - (bitwidth
- num1
);
5327 && (bitwidth
> HOST_BITS_PER_WIDE_INT
5328 || (((nonzero_bits (XEXP (x
, 0), mode
)
5329 & (HOST_WIDE_INT_1U
<< (bitwidth
- 1))) != 0)
5330 && ((nonzero_bits (XEXP (x
, 1), mode
)
5331 & (HOST_WIDE_INT_1U
<< (bitwidth
- 1)))
5335 return MAX (1, result
);
5338 /* The result must be <= the first operand. If the first operand
5339 has the high bit set, we know nothing about the number of sign
5341 if (bitwidth
> HOST_BITS_PER_WIDE_INT
)
5343 else if ((nonzero_bits (XEXP (x
, 0), mode
)
5344 & (HOST_WIDE_INT_1U
<< (bitwidth
- 1))) != 0)
5347 return cached_num_sign_bit_copies (XEXP (x
, 0), mode
,
5348 known_x
, known_mode
, known_ret
);
5351 /* The result must be <= the second operand. If the second operand
5352 has (or just might have) the high bit set, we know nothing about
5353 the number of sign bit copies. */
5354 if (bitwidth
> HOST_BITS_PER_WIDE_INT
)
5356 else if ((nonzero_bits (XEXP (x
, 1), mode
)
5357 & (HOST_WIDE_INT_1U
<< (bitwidth
- 1))) != 0)
5360 return cached_num_sign_bit_copies (XEXP (x
, 1), mode
,
5361 known_x
, known_mode
, known_ret
);
5364 /* Similar to unsigned division, except that we have to worry about
5365 the case where the divisor is negative, in which case we have
5367 result
= cached_num_sign_bit_copies (XEXP (x
, 0), mode
,
5368 known_x
, known_mode
, known_ret
);
5370 && (bitwidth
> HOST_BITS_PER_WIDE_INT
5371 || (nonzero_bits (XEXP (x
, 1), mode
)
5372 & (HOST_WIDE_INT_1U
<< (bitwidth
- 1))) != 0))
5378 result
= cached_num_sign_bit_copies (XEXP (x
, 1), mode
,
5379 known_x
, known_mode
, known_ret
);
5381 && (bitwidth
> HOST_BITS_PER_WIDE_INT
5382 || (nonzero_bits (XEXP (x
, 1), mode
)
5383 & (HOST_WIDE_INT_1U
<< (bitwidth
- 1))) != 0))
5389 /* Shifts by a constant add to the number of bits equal to the
5391 num0
= cached_num_sign_bit_copies (XEXP (x
, 0), mode
,
5392 known_x
, known_mode
, known_ret
);
5393 if (CONST_INT_P (XEXP (x
, 1))
5394 && INTVAL (XEXP (x
, 1)) > 0
5395 && INTVAL (XEXP (x
, 1)) < xmode_width
)
5396 num0
= MIN ((int) bitwidth
, num0
+ INTVAL (XEXP (x
, 1)));
5401 /* Left shifts destroy copies. */
5402 if (!CONST_INT_P (XEXP (x
, 1))
5403 || INTVAL (XEXP (x
, 1)) < 0
5404 || INTVAL (XEXP (x
, 1)) >= (int) bitwidth
5405 || INTVAL (XEXP (x
, 1)) >= xmode_width
)
5408 num0
= cached_num_sign_bit_copies (XEXP (x
, 0), mode
,
5409 known_x
, known_mode
, known_ret
);
5410 return MAX (1, num0
- INTVAL (XEXP (x
, 1)));
5413 num0
= cached_num_sign_bit_copies (XEXP (x
, 1), mode
,
5414 known_x
, known_mode
, known_ret
);
5415 num1
= cached_num_sign_bit_copies (XEXP (x
, 2), mode
,
5416 known_x
, known_mode
, known_ret
);
5417 return MIN (num0
, num1
);
5419 case EQ
: case NE
: case GE
: case GT
: case LE
: case LT
:
5420 case UNEQ
: case LTGT
: case UNGE
: case UNGT
: case UNLE
: case UNLT
:
5421 case GEU
: case GTU
: case LEU
: case LTU
:
5422 case UNORDERED
: case ORDERED
:
5423 /* If the constant is negative, take its 1's complement and remask.
5424 Then see how many zero bits we have. */
5425 nonzero
= STORE_FLAG_VALUE
;
5426 if (bitwidth
<= HOST_BITS_PER_WIDE_INT
5427 && (nonzero
& (HOST_WIDE_INT_1U
<< (bitwidth
- 1))) != 0)
5428 nonzero
= (~nonzero
) & GET_MODE_MASK (mode
);
5430 return (nonzero
== 0 ? bitwidth
: bitwidth
- floor_log2 (nonzero
) - 1);
5436 /* If we haven't been able to figure it out by one of the above rules,
5437 see if some of the high-order bits are known to be zero. If so,
5438 count those bits and return one less than that amount. If we can't
5439 safely compute the mask for this mode, always return BITWIDTH. */
5441 bitwidth
= GET_MODE_PRECISION (mode
);
5442 if (bitwidth
> HOST_BITS_PER_WIDE_INT
)
5445 nonzero
= nonzero_bits (x
, mode
);
5446 return nonzero
& (HOST_WIDE_INT_1U
<< (bitwidth
- 1))
5447 ? 1 : bitwidth
- floor_log2 (nonzero
) - 1;
5450 /* Calculate the rtx_cost of a single instruction pattern. A return value of
5451 zero indicates an instruction pattern without a known cost. */
5454 pattern_cost (rtx pat
, bool speed
)
5459 /* Extract the single set rtx from the instruction pattern. We
5460 can't use single_set since we only have the pattern. We also
5461 consider PARALLELs of a normal set and a single comparison. In
5462 that case we use the cost of the non-comparison SET operation,
5463 which is most-likely to be the real cost of this operation. */
5464 if (GET_CODE (pat
) == SET
)
5466 else if (GET_CODE (pat
) == PARALLEL
)
5469 rtx comparison
= NULL_RTX
;
5471 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
5473 rtx x
= XVECEXP (pat
, 0, i
);
5474 if (GET_CODE (x
) == SET
)
5476 if (GET_CODE (SET_SRC (x
)) == COMPARE
)
5491 if (!set
&& comparison
)
5500 cost
= set_src_cost (SET_SRC (set
), GET_MODE (SET_DEST (set
)), speed
);
5501 return cost
> 0 ? cost
: COSTS_N_INSNS (1);
5504 /* Calculate the cost of a single instruction. A return value of zero
5505 indicates an instruction pattern without a known cost. */
5508 insn_cost (rtx_insn
*insn
, bool speed
)
5510 if (targetm
.insn_cost
)
5511 return targetm
.insn_cost (insn
, speed
);
5513 return pattern_cost (PATTERN (insn
), speed
);
5516 /* Returns estimate on cost of computing SEQ. */
5519 seq_cost (const rtx_insn
*seq
, bool speed
)
5524 for (; seq
; seq
= NEXT_INSN (seq
))
5526 set
= single_set (seq
);
5528 cost
+= set_rtx_cost (set
, speed
);
5529 else if (NONDEBUG_INSN_P (seq
))
5531 int this_cost
= insn_cost (CONST_CAST_RTX_INSN (seq
), speed
);
5542 /* Given an insn INSN and condition COND, return the condition in a
5543 canonical form to simplify testing by callers. Specifically:
5545 (1) The code will always be a comparison operation (EQ, NE, GT, etc.).
5546 (2) Both operands will be machine operands; (cc0) will have been replaced.
5547 (3) If an operand is a constant, it will be the second operand.
5548 (4) (LE x const) will be replaced with (LT x <const+1>) and similarly
5549 for GE, GEU, and LEU.
5551 If the condition cannot be understood, or is an inequality floating-point
5552 comparison which needs to be reversed, 0 will be returned.
5554 If REVERSE is nonzero, then reverse the condition prior to canonizing it.
5556 If EARLIEST is nonzero, it is a pointer to a place where the earliest
5557 insn used in locating the condition was found. If a replacement test
5558 of the condition is desired, it should be placed in front of that
5559 insn and we will be sure that the inputs are still valid.
5561 If WANT_REG is nonzero, we wish the condition to be relative to that
5562 register, if possible. Therefore, do not canonicalize the condition
5563 further. If ALLOW_CC_MODE is nonzero, allow the condition returned
5564 to be a compare to a CC mode register.
5566 If VALID_AT_INSN_P, the condition must be valid at both *EARLIEST
5570 canonicalize_condition (rtx_insn
*insn
, rtx cond
, int reverse
,
5571 rtx_insn
**earliest
,
5572 rtx want_reg
, int allow_cc_mode
, int valid_at_insn_p
)
5575 rtx_insn
*prev
= insn
;
5579 int reverse_code
= 0;
5581 basic_block bb
= BLOCK_FOR_INSN (insn
);
5583 code
= GET_CODE (cond
);
5584 mode
= GET_MODE (cond
);
5585 op0
= XEXP (cond
, 0);
5586 op1
= XEXP (cond
, 1);
5589 code
= reversed_comparison_code (cond
, insn
);
5590 if (code
== UNKNOWN
)
5596 /* If we are comparing a register with zero, see if the register is set
5597 in the previous insn to a COMPARE or a comparison operation. Perform
5598 the same tests as a function of STORE_FLAG_VALUE as find_comparison_args
5601 while ((GET_RTX_CLASS (code
) == RTX_COMPARE
5602 || GET_RTX_CLASS (code
) == RTX_COMM_COMPARE
)
5603 && op1
== CONST0_RTX (GET_MODE (op0
))
5606 /* Set nonzero when we find something of interest. */
5609 /* If comparison with cc0, import actual comparison from compare
5613 if ((prev
= prev_nonnote_insn (prev
)) == 0
5614 || !NONJUMP_INSN_P (prev
)
5615 || (set
= single_set (prev
)) == 0
5616 || SET_DEST (set
) != cc0_rtx
)
5619 op0
= SET_SRC (set
);
5620 op1
= CONST0_RTX (GET_MODE (op0
));
5625 /* If this is a COMPARE, pick up the two things being compared. */
5626 if (GET_CODE (op0
) == COMPARE
)
5628 op1
= XEXP (op0
, 1);
5629 op0
= XEXP (op0
, 0);
5632 else if (!REG_P (op0
))
5635 /* Go back to the previous insn. Stop if it is not an INSN. We also
5636 stop if it isn't a single set or if it has a REG_INC note because
5637 we don't want to bother dealing with it. */
5639 prev
= prev_nonnote_nondebug_insn (prev
);
5642 || !NONJUMP_INSN_P (prev
)
5643 || FIND_REG_INC_NOTE (prev
, NULL_RTX
)
5644 /* In cfglayout mode, there do not have to be labels at the
5645 beginning of a block, or jumps at the end, so the previous
5646 conditions would not stop us when we reach bb boundary. */
5647 || BLOCK_FOR_INSN (prev
) != bb
)
5650 set
= set_of (op0
, prev
);
5653 && (GET_CODE (set
) != SET
5654 || !rtx_equal_p (SET_DEST (set
), op0
)))
5657 /* If this is setting OP0, get what it sets it to if it looks
5661 machine_mode inner_mode
= GET_MODE (SET_DEST (set
));
5662 #ifdef FLOAT_STORE_FLAG_VALUE
5663 REAL_VALUE_TYPE fsfv
;
5666 /* ??? We may not combine comparisons done in a CCmode with
5667 comparisons not done in a CCmode. This is to aid targets
5668 like Alpha that have an IEEE compliant EQ instruction, and
5669 a non-IEEE compliant BEQ instruction. The use of CCmode is
5670 actually artificial, simply to prevent the combination, but
5671 should not affect other platforms.
5673 However, we must allow VOIDmode comparisons to match either
5674 CCmode or non-CCmode comparison, because some ports have
5675 modeless comparisons inside branch patterns.
5677 ??? This mode check should perhaps look more like the mode check
5678 in simplify_comparison in combine. */
5679 if (((GET_MODE_CLASS (mode
) == MODE_CC
)
5680 != (GET_MODE_CLASS (inner_mode
) == MODE_CC
))
5682 && inner_mode
!= VOIDmode
)
5684 if (GET_CODE (SET_SRC (set
)) == COMPARE
5687 && val_signbit_known_set_p (inner_mode
,
5689 #ifdef FLOAT_STORE_FLAG_VALUE
5691 && SCALAR_FLOAT_MODE_P (inner_mode
)
5692 && (fsfv
= FLOAT_STORE_FLAG_VALUE (inner_mode
),
5693 REAL_VALUE_NEGATIVE (fsfv
)))
5696 && COMPARISON_P (SET_SRC (set
))))
5698 else if (((code
== EQ
5700 && val_signbit_known_set_p (inner_mode
,
5702 #ifdef FLOAT_STORE_FLAG_VALUE
5704 && SCALAR_FLOAT_MODE_P (inner_mode
)
5705 && (fsfv
= FLOAT_STORE_FLAG_VALUE (inner_mode
),
5706 REAL_VALUE_NEGATIVE (fsfv
)))
5709 && COMPARISON_P (SET_SRC (set
)))
5714 else if ((code
== EQ
|| code
== NE
)
5715 && GET_CODE (SET_SRC (set
)) == XOR
)
5716 /* Handle sequences like:
5719 ...(eq|ne op0 (const_int 0))...
5723 (eq op0 (const_int 0)) reduces to (eq X Y)
5724 (ne op0 (const_int 0)) reduces to (ne X Y)
5726 This is the form used by MIPS16, for example. */
5732 else if (reg_set_p (op0
, prev
))
5733 /* If this sets OP0, but not directly, we have to give up. */
5738 /* If the caller is expecting the condition to be valid at INSN,
5739 make sure X doesn't change before INSN. */
5740 if (valid_at_insn_p
)
5741 if (modified_in_p (x
, prev
) || modified_between_p (x
, prev
, insn
))
5743 if (COMPARISON_P (x
))
5744 code
= GET_CODE (x
);
5747 code
= reversed_comparison_code (x
, prev
);
5748 if (code
== UNKNOWN
)
5753 op0
= XEXP (x
, 0), op1
= XEXP (x
, 1);
5759 /* If constant is first, put it last. */
5760 if (CONSTANT_P (op0
))
5761 code
= swap_condition (code
), tem
= op0
, op0
= op1
, op1
= tem
;
5763 /* If OP0 is the result of a comparison, we weren't able to find what
5764 was really being compared, so fail. */
5766 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_CC
)
5769 /* Canonicalize any ordered comparison with integers involving equality
5770 if we can do computations in the relevant mode and we do not
5773 scalar_int_mode op0_mode
;
5774 if (CONST_INT_P (op1
)
5775 && is_a
<scalar_int_mode
> (GET_MODE (op0
), &op0_mode
)
5776 && GET_MODE_PRECISION (op0_mode
) <= HOST_BITS_PER_WIDE_INT
)
5778 HOST_WIDE_INT const_val
= INTVAL (op1
);
5779 unsigned HOST_WIDE_INT uconst_val
= const_val
;
5780 unsigned HOST_WIDE_INT max_val
5781 = (unsigned HOST_WIDE_INT
) GET_MODE_MASK (op0_mode
);
5786 if ((unsigned HOST_WIDE_INT
) const_val
!= max_val
>> 1)
5787 code
= LT
, op1
= gen_int_mode (const_val
+ 1, op0_mode
);
5790 /* When cross-compiling, const_val might be sign-extended from
5791 BITS_PER_WORD to HOST_BITS_PER_WIDE_INT */
5793 if ((const_val
& max_val
)
5794 != (HOST_WIDE_INT_1U
<< (GET_MODE_PRECISION (op0_mode
) - 1)))
5795 code
= GT
, op1
= gen_int_mode (const_val
- 1, op0_mode
);
5799 if (uconst_val
< max_val
)
5800 code
= LTU
, op1
= gen_int_mode (uconst_val
+ 1, op0_mode
);
5804 if (uconst_val
!= 0)
5805 code
= GTU
, op1
= gen_int_mode (uconst_val
- 1, op0_mode
);
5813 /* Never return CC0; return zero instead. */
5817 /* We promised to return a comparison. */
5818 rtx ret
= gen_rtx_fmt_ee (code
, VOIDmode
, op0
, op1
);
5819 if (COMPARISON_P (ret
))
5824 /* Given a jump insn JUMP, return the condition that will cause it to branch
5825 to its JUMP_LABEL. If the condition cannot be understood, or is an
5826 inequality floating-point comparison which needs to be reversed, 0 will
5829 If EARLIEST is nonzero, it is a pointer to a place where the earliest
5830 insn used in locating the condition was found. If a replacement test
5831 of the condition is desired, it should be placed in front of that
5832 insn and we will be sure that the inputs are still valid. If EARLIEST
5833 is null, the returned condition will be valid at INSN.
5835 If ALLOW_CC_MODE is nonzero, allow the condition returned to be a
5836 compare CC mode register.
5838 VALID_AT_INSN_P is the same as for canonicalize_condition. */
5841 get_condition (rtx_insn
*jump
, rtx_insn
**earliest
, int allow_cc_mode
,
5842 int valid_at_insn_p
)
5848 /* If this is not a standard conditional jump, we can't parse it. */
5850 || ! any_condjump_p (jump
))
5852 set
= pc_set (jump
);
5854 cond
= XEXP (SET_SRC (set
), 0);
5856 /* If this branches to JUMP_LABEL when the condition is false, reverse
5859 = GET_CODE (XEXP (SET_SRC (set
), 2)) == LABEL_REF
5860 && label_ref_label (XEXP (SET_SRC (set
), 2)) == JUMP_LABEL (jump
);
5862 return canonicalize_condition (jump
, cond
, reverse
, earliest
, NULL_RTX
,
5863 allow_cc_mode
, valid_at_insn_p
);
5866 /* Initialize the table NUM_SIGN_BIT_COPIES_IN_REP based on
5867 TARGET_MODE_REP_EXTENDED.
5869 Note that we assume that the property of
5870 TARGET_MODE_REP_EXTENDED(B, C) is sticky to the integral modes
5871 narrower than mode B. I.e., if A is a mode narrower than B then in
5872 order to be able to operate on it in mode B, mode A needs to
5873 satisfy the requirements set by the representation of mode B. */
5876 init_num_sign_bit_copies_in_rep (void)
5878 opt_scalar_int_mode in_mode_iter
;
5879 scalar_int_mode mode
;
5881 FOR_EACH_MODE_IN_CLASS (in_mode_iter
, MODE_INT
)
5882 FOR_EACH_MODE_UNTIL (mode
, in_mode_iter
.require ())
5884 scalar_int_mode in_mode
= in_mode_iter
.require ();
5887 /* Currently, it is assumed that TARGET_MODE_REP_EXTENDED
5888 extends to the next widest mode. */
5889 gcc_assert (targetm
.mode_rep_extended (mode
, in_mode
) == UNKNOWN
5890 || GET_MODE_WIDER_MODE (mode
).require () == in_mode
);
5892 /* We are in in_mode. Count how many bits outside of mode
5893 have to be copies of the sign-bit. */
5894 FOR_EACH_MODE (i
, mode
, in_mode
)
5896 /* This must always exist (for the last iteration it will be
5898 scalar_int_mode wider
= GET_MODE_WIDER_MODE (i
).require ();
5900 if (targetm
.mode_rep_extended (i
, wider
) == SIGN_EXTEND
5901 /* We can only check sign-bit copies starting from the
5902 top-bit. In order to be able to check the bits we
5903 have already seen we pretend that subsequent bits
5904 have to be sign-bit copies too. */
5905 || num_sign_bit_copies_in_rep
[in_mode
][mode
])
5906 num_sign_bit_copies_in_rep
[in_mode
][mode
]
5907 += GET_MODE_PRECISION (wider
) - GET_MODE_PRECISION (i
);
5912 /* Suppose that truncation from the machine mode of X to MODE is not a
5913 no-op. See if there is anything special about X so that we can
5914 assume it already contains a truncated value of MODE. */
5917 truncated_to_mode (machine_mode mode
, const_rtx x
)
5919 /* This register has already been used in MODE without explicit
5921 if (REG_P (x
) && rtl_hooks
.reg_truncated_to_mode (mode
, x
))
5924 /* See if we already satisfy the requirements of MODE. If yes we
5925 can just switch to MODE. */
5926 if (num_sign_bit_copies_in_rep
[GET_MODE (x
)][mode
]
5927 && (num_sign_bit_copies (x
, GET_MODE (x
))
5928 >= num_sign_bit_copies_in_rep
[GET_MODE (x
)][mode
] + 1))
5934 /* Return true if RTX code CODE has a single sequence of zero or more
5935 "e" operands and no rtvec operands. Initialize its rtx_all_subrtx_bounds
5936 entry in that case. */
5939 setup_reg_subrtx_bounds (unsigned int code
)
5941 const char *format
= GET_RTX_FORMAT ((enum rtx_code
) code
);
5943 for (; format
[i
] != 'e'; ++i
)
5946 /* No subrtxes. Leave start and count as 0. */
5948 if (format
[i
] == 'E' || format
[i
] == 'V')
5952 /* Record the sequence of 'e's. */
5953 rtx_all_subrtx_bounds
[code
].start
= i
;
5956 while (format
[i
] == 'e');
5957 rtx_all_subrtx_bounds
[code
].count
= i
- rtx_all_subrtx_bounds
[code
].start
;
5958 /* rtl-iter.h relies on this. */
5959 gcc_checking_assert (rtx_all_subrtx_bounds
[code
].count
<= 3);
5961 for (; format
[i
]; ++i
)
5962 if (format
[i
] == 'E' || format
[i
] == 'V' || format
[i
] == 'e')
5968 /* Initialize rtx_all_subrtx_bounds. */
5973 for (i
= 0; i
< NUM_RTX_CODE
; i
++)
5975 if (!setup_reg_subrtx_bounds (i
))
5976 rtx_all_subrtx_bounds
[i
].count
= UCHAR_MAX
;
5977 if (GET_RTX_CLASS (i
) != RTX_CONST_OBJ
)
5978 rtx_nonconst_subrtx_bounds
[i
] = rtx_all_subrtx_bounds
[i
];
5981 init_num_sign_bit_copies_in_rep ();
5984 /* Check whether this is a constant pool constant. */
5986 constant_pool_constant_p (rtx x
)
5988 x
= avoid_constant_pool_reference (x
);
5989 return CONST_DOUBLE_P (x
);
5992 /* If M is a bitmask that selects a field of low-order bits within an item but
5993 not the entire word, return the length of the field. Return -1 otherwise.
5994 M is used in machine mode MODE. */
5997 low_bitmask_len (machine_mode mode
, unsigned HOST_WIDE_INT m
)
5999 if (mode
!= VOIDmode
)
6001 if (!HWI_COMPUTABLE_MODE_P (mode
))
6003 m
&= GET_MODE_MASK (mode
);
6006 return exact_log2 (m
+ 1);
6009 /* Return the mode of MEM's address. */
6012 get_address_mode (rtx mem
)
6016 gcc_assert (MEM_P (mem
));
6017 mode
= GET_MODE (XEXP (mem
, 0));
6018 if (mode
!= VOIDmode
)
6019 return as_a
<scalar_int_mode
> (mode
);
6020 return targetm
.addr_space
.address_mode (MEM_ADDR_SPACE (mem
));
6023 /* Split up a CONST_DOUBLE or integer constant rtx
6024 into two rtx's for single words,
6025 storing in *FIRST the word that comes first in memory in the target
6026 and in *SECOND the other.
6028 TODO: This function needs to be rewritten to work on any size
6032 split_double (rtx value
, rtx
*first
, rtx
*second
)
6034 if (CONST_INT_P (value
))
6036 if (HOST_BITS_PER_WIDE_INT
>= (2 * BITS_PER_WORD
))
6038 /* In this case the CONST_INT holds both target words.
6039 Extract the bits from it into two word-sized pieces.
6040 Sign extend each half to HOST_WIDE_INT. */
6041 unsigned HOST_WIDE_INT low
, high
;
6042 unsigned HOST_WIDE_INT mask
, sign_bit
, sign_extend
;
6043 unsigned bits_per_word
= BITS_PER_WORD
;
6045 /* Set sign_bit to the most significant bit of a word. */
6047 sign_bit
<<= bits_per_word
- 1;
6049 /* Set mask so that all bits of the word are set. We could
6050 have used 1 << BITS_PER_WORD instead of basing the
6051 calculation on sign_bit. However, on machines where
6052 HOST_BITS_PER_WIDE_INT == BITS_PER_WORD, it could cause a
6053 compiler warning, even though the code would never be
6055 mask
= sign_bit
<< 1;
6058 /* Set sign_extend as any remaining bits. */
6059 sign_extend
= ~mask
;
6061 /* Pick the lower word and sign-extend it. */
6062 low
= INTVAL (value
);
6067 /* Pick the higher word, shifted to the least significant
6068 bits, and sign-extend it. */
6069 high
= INTVAL (value
);
6070 high
>>= bits_per_word
- 1;
6073 if (high
& sign_bit
)
6074 high
|= sign_extend
;
6076 /* Store the words in the target machine order. */
6077 if (WORDS_BIG_ENDIAN
)
6079 *first
= GEN_INT (high
);
6080 *second
= GEN_INT (low
);
6084 *first
= GEN_INT (low
);
6085 *second
= GEN_INT (high
);
6090 /* The rule for using CONST_INT for a wider mode
6091 is that we regard the value as signed.
6092 So sign-extend it. */
6093 rtx high
= (INTVAL (value
) < 0 ? constm1_rtx
: const0_rtx
);
6094 if (WORDS_BIG_ENDIAN
)
6106 else if (GET_CODE (value
) == CONST_WIDE_INT
)
6108 /* All of this is scary code and needs to be converted to
6109 properly work with any size integer. */
6110 gcc_assert (CONST_WIDE_INT_NUNITS (value
) == 2);
6111 if (WORDS_BIG_ENDIAN
)
6113 *first
= GEN_INT (CONST_WIDE_INT_ELT (value
, 1));
6114 *second
= GEN_INT (CONST_WIDE_INT_ELT (value
, 0));
6118 *first
= GEN_INT (CONST_WIDE_INT_ELT (value
, 0));
6119 *second
= GEN_INT (CONST_WIDE_INT_ELT (value
, 1));
6122 else if (!CONST_DOUBLE_P (value
))
6124 if (WORDS_BIG_ENDIAN
)
6126 *first
= const0_rtx
;
6132 *second
= const0_rtx
;
6135 else if (GET_MODE (value
) == VOIDmode
6136 /* This is the old way we did CONST_DOUBLE integers. */
6137 || GET_MODE_CLASS (GET_MODE (value
)) == MODE_INT
)
6139 /* In an integer, the words are defined as most and least significant.
6140 So order them by the target's convention. */
6141 if (WORDS_BIG_ENDIAN
)
6143 *first
= GEN_INT (CONST_DOUBLE_HIGH (value
));
6144 *second
= GEN_INT (CONST_DOUBLE_LOW (value
));
6148 *first
= GEN_INT (CONST_DOUBLE_LOW (value
));
6149 *second
= GEN_INT (CONST_DOUBLE_HIGH (value
));
6156 /* Note, this converts the REAL_VALUE_TYPE to the target's
6157 format, splits up the floating point double and outputs
6158 exactly 32 bits of it into each of l[0] and l[1] --
6159 not necessarily BITS_PER_WORD bits. */
6160 REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (value
), l
);
6162 /* If 32 bits is an entire word for the target, but not for the host,
6163 then sign-extend on the host so that the number will look the same
6164 way on the host that it would on the target. See for instance
6165 simplify_unary_operation. The #if is needed to avoid compiler
6168 #if HOST_BITS_PER_LONG > 32
6169 if (BITS_PER_WORD
< HOST_BITS_PER_LONG
&& BITS_PER_WORD
== 32)
6171 if (l
[0] & ((long) 1 << 31))
6172 l
[0] |= ((unsigned long) (-1) << 32);
6173 if (l
[1] & ((long) 1 << 31))
6174 l
[1] |= ((unsigned long) (-1) << 32);
6178 *first
= GEN_INT (l
[0]);
6179 *second
= GEN_INT (l
[1]);
6183 /* Return true if X is a sign_extract or zero_extract from the least
6187 lsb_bitfield_op_p (rtx x
)
6189 if (GET_RTX_CLASS (GET_CODE (x
)) == RTX_BITFIELD_OPS
)
6191 machine_mode mode
= GET_MODE (XEXP (x
, 0));
6192 HOST_WIDE_INT len
= INTVAL (XEXP (x
, 1));
6193 HOST_WIDE_INT pos
= INTVAL (XEXP (x
, 2));
6194 poly_int64 remaining_bits
= GET_MODE_PRECISION (mode
) - len
;
6196 return known_eq (pos
, BITS_BIG_ENDIAN
? remaining_bits
: 0);
6201 /* Strip outer address "mutations" from LOC and return a pointer to the
6202 inner value. If OUTER_CODE is nonnull, store the code of the innermost
6203 stripped expression there.
6205 "Mutations" either convert between modes or apply some kind of
6206 extension, truncation or alignment. */
6209 strip_address_mutations (rtx
*loc
, enum rtx_code
*outer_code
)
6213 enum rtx_code code
= GET_CODE (*loc
);
6214 if (GET_RTX_CLASS (code
) == RTX_UNARY
)
6215 /* Things like SIGN_EXTEND, ZERO_EXTEND and TRUNCATE can be
6216 used to convert between pointer sizes. */
6217 loc
= &XEXP (*loc
, 0);
6218 else if (lsb_bitfield_op_p (*loc
))
6219 /* A [SIGN|ZERO]_EXTRACT from the least significant bit effectively
6220 acts as a combined truncation and extension. */
6221 loc
= &XEXP (*loc
, 0);
6222 else if (code
== AND
&& CONST_INT_P (XEXP (*loc
, 1)))
6223 /* (and ... (const_int -X)) is used to align to X bytes. */
6224 loc
= &XEXP (*loc
, 0);
6225 else if (code
== SUBREG
6226 && !OBJECT_P (SUBREG_REG (*loc
))
6227 && subreg_lowpart_p (*loc
))
6228 /* (subreg (operator ...) ...) inside and is used for mode
6230 loc
= &SUBREG_REG (*loc
);
6238 /* Return true if CODE applies some kind of scale. The scaled value is
6239 is the first operand and the scale is the second. */
6242 binary_scale_code_p (enum rtx_code code
)
6244 return (code
== MULT
6246 /* Needed by ARM targets. */
6250 || code
== ROTATERT
);
6253 /* If *INNER can be interpreted as a base, return a pointer to the inner term
6254 (see address_info). Return null otherwise. */
6257 get_base_term (rtx
*inner
)
6259 if (GET_CODE (*inner
) == LO_SUM
)
6260 inner
= strip_address_mutations (&XEXP (*inner
, 0));
6263 || GET_CODE (*inner
) == SUBREG
6264 || GET_CODE (*inner
) == SCRATCH
)
6269 /* If *INNER can be interpreted as an index, return a pointer to the inner term
6270 (see address_info). Return null otherwise. */
6273 get_index_term (rtx
*inner
)
6275 /* At present, only constant scales are allowed. */
6276 if (binary_scale_code_p (GET_CODE (*inner
)) && CONSTANT_P (XEXP (*inner
, 1)))
6277 inner
= strip_address_mutations (&XEXP (*inner
, 0));
6280 || GET_CODE (*inner
) == SUBREG
6281 || GET_CODE (*inner
) == SCRATCH
)
6286 /* Set the segment part of address INFO to LOC, given that INNER is the
6290 set_address_segment (struct address_info
*info
, rtx
*loc
, rtx
*inner
)
6292 gcc_assert (!info
->segment
);
6293 info
->segment
= loc
;
6294 info
->segment_term
= inner
;
6297 /* Set the base part of address INFO to LOC, given that INNER is the
6301 set_address_base (struct address_info
*info
, rtx
*loc
, rtx
*inner
)
6303 gcc_assert (!info
->base
);
6305 info
->base_term
= inner
;
6308 /* Set the index part of address INFO to LOC, given that INNER is the
6312 set_address_index (struct address_info
*info
, rtx
*loc
, rtx
*inner
)
6314 gcc_assert (!info
->index
);
6316 info
->index_term
= inner
;
6319 /* Set the displacement part of address INFO to LOC, given that INNER
6320 is the constant term. */
6323 set_address_disp (struct address_info
*info
, rtx
*loc
, rtx
*inner
)
6325 gcc_assert (!info
->disp
);
6327 info
->disp_term
= inner
;
6330 /* INFO->INNER describes a {PRE,POST}_{INC,DEC} address. Set up the
6331 rest of INFO accordingly. */
6334 decompose_incdec_address (struct address_info
*info
)
6336 info
->autoinc_p
= true;
6338 rtx
*base
= &XEXP (*info
->inner
, 0);
6339 set_address_base (info
, base
, base
);
6340 gcc_checking_assert (info
->base
== info
->base_term
);
6342 /* These addresses are only valid when the size of the addressed
6344 gcc_checking_assert (info
->mode
!= VOIDmode
);
6347 /* INFO->INNER describes a {PRE,POST}_MODIFY address. Set up the rest
6348 of INFO accordingly. */
6351 decompose_automod_address (struct address_info
*info
)
6353 info
->autoinc_p
= true;
6355 rtx
*base
= &XEXP (*info
->inner
, 0);
6356 set_address_base (info
, base
, base
);
6357 gcc_checking_assert (info
->base
== info
->base_term
);
6359 rtx plus
= XEXP (*info
->inner
, 1);
6360 gcc_assert (GET_CODE (plus
) == PLUS
);
6362 info
->base_term2
= &XEXP (plus
, 0);
6363 gcc_checking_assert (rtx_equal_p (*info
->base_term
, *info
->base_term2
));
6365 rtx
*step
= &XEXP (plus
, 1);
6366 rtx
*inner_step
= strip_address_mutations (step
);
6367 if (CONSTANT_P (*inner_step
))
6368 set_address_disp (info
, step
, inner_step
);
6370 set_address_index (info
, step
, inner_step
);
6373 /* Treat *LOC as a tree of PLUS operands and store pointers to the summed
6374 values in [PTR, END). Return a pointer to the end of the used array. */
6377 extract_plus_operands (rtx
*loc
, rtx
**ptr
, rtx
**end
)
6380 if (GET_CODE (x
) == PLUS
)
6382 ptr
= extract_plus_operands (&XEXP (x
, 0), ptr
, end
);
6383 ptr
= extract_plus_operands (&XEXP (x
, 1), ptr
, end
);
6387 gcc_assert (ptr
!= end
);
6393 /* Evaluate the likelihood of X being a base or index value, returning
6394 positive if it is likely to be a base, negative if it is likely to be
6395 an index, and 0 if we can't tell. Make the magnitude of the return
6396 value reflect the amount of confidence we have in the answer.
6398 MODE, AS, OUTER_CODE and INDEX_CODE are as for ok_for_base_p_1. */
6401 baseness (rtx x
, machine_mode mode
, addr_space_t as
,
6402 enum rtx_code outer_code
, enum rtx_code index_code
)
6404 /* Believe *_POINTER unless the address shape requires otherwise. */
6405 if (REG_P (x
) && REG_POINTER (x
))
6407 if (MEM_P (x
) && MEM_POINTER (x
))
6410 if (REG_P (x
) && HARD_REGISTER_P (x
))
6412 /* X is a hard register. If it only fits one of the base
6413 or index classes, choose that interpretation. */
6414 int regno
= REGNO (x
);
6415 bool base_p
= ok_for_base_p_1 (regno
, mode
, as
, outer_code
, index_code
);
6416 bool index_p
= REGNO_OK_FOR_INDEX_P (regno
);
6417 if (base_p
!= index_p
)
6418 return base_p
? 1 : -1;
6423 /* INFO->INNER describes a normal, non-automodified address.
6424 Fill in the rest of INFO accordingly. */
6427 decompose_normal_address (struct address_info
*info
)
6429 /* Treat the address as the sum of up to four values. */
6431 size_t n_ops
= extract_plus_operands (info
->inner
, ops
,
6432 ops
+ ARRAY_SIZE (ops
)) - ops
;
6434 /* If there is more than one component, any base component is in a PLUS. */
6436 info
->base_outer_code
= PLUS
;
6438 /* Try to classify each sum operand now. Leave those that could be
6439 either a base or an index in OPS. */
6442 for (size_t in
= 0; in
< n_ops
; ++in
)
6445 rtx
*inner
= strip_address_mutations (loc
);
6446 if (CONSTANT_P (*inner
))
6447 set_address_disp (info
, loc
, inner
);
6448 else if (GET_CODE (*inner
) == UNSPEC
)
6449 set_address_segment (info
, loc
, inner
);
6452 /* The only other possibilities are a base or an index. */
6453 rtx
*base_term
= get_base_term (inner
);
6454 rtx
*index_term
= get_index_term (inner
);
6455 gcc_assert (base_term
|| index_term
);
6457 set_address_index (info
, loc
, index_term
);
6458 else if (!index_term
)
6459 set_address_base (info
, loc
, base_term
);
6462 gcc_assert (base_term
== index_term
);
6464 inner_ops
[out
] = base_term
;
6470 /* Classify the remaining OPS members as bases and indexes. */
6473 /* If we haven't seen a base or an index yet, assume that this is
6474 the base. If we were confident that another term was the base
6475 or index, treat the remaining operand as the other kind. */
6477 set_address_base (info
, ops
[0], inner_ops
[0]);
6479 set_address_index (info
, ops
[0], inner_ops
[0]);
6483 /* In the event of a tie, assume the base comes first. */
6484 if (baseness (*inner_ops
[0], info
->mode
, info
->as
, PLUS
,
6486 >= baseness (*inner_ops
[1], info
->mode
, info
->as
, PLUS
,
6487 GET_CODE (*ops
[0])))
6489 set_address_base (info
, ops
[0], inner_ops
[0]);
6490 set_address_index (info
, ops
[1], inner_ops
[1]);
6494 set_address_base (info
, ops
[1], inner_ops
[1]);
6495 set_address_index (info
, ops
[0], inner_ops
[0]);
6499 gcc_assert (out
== 0);
6502 /* Describe address *LOC in *INFO. MODE is the mode of the addressed value,
6503 or VOIDmode if not known. AS is the address space associated with LOC.
6504 OUTER_CODE is MEM if *LOC is a MEM address and ADDRESS otherwise. */
6507 decompose_address (struct address_info
*info
, rtx
*loc
, machine_mode mode
,
6508 addr_space_t as
, enum rtx_code outer_code
)
6510 memset (info
, 0, sizeof (*info
));
6513 info
->addr_outer_code
= outer_code
;
6515 info
->inner
= strip_address_mutations (loc
, &outer_code
);
6516 info
->base_outer_code
= outer_code
;
6517 switch (GET_CODE (*info
->inner
))
6523 decompose_incdec_address (info
);
6528 decompose_automod_address (info
);
6532 decompose_normal_address (info
);
6537 /* Describe address operand LOC in INFO. */
6540 decompose_lea_address (struct address_info
*info
, rtx
*loc
)
6542 decompose_address (info
, loc
, VOIDmode
, ADDR_SPACE_GENERIC
, ADDRESS
);
6545 /* Describe the address of MEM X in INFO. */
6548 decompose_mem_address (struct address_info
*info
, rtx x
)
6550 gcc_assert (MEM_P (x
));
6551 decompose_address (info
, &XEXP (x
, 0), GET_MODE (x
),
6552 MEM_ADDR_SPACE (x
), MEM
);
6555 /* Update INFO after a change to the address it describes. */
6558 update_address (struct address_info
*info
)
6560 decompose_address (info
, info
->outer
, info
->mode
, info
->as
,
6561 info
->addr_outer_code
);
6564 /* Return the scale applied to *INFO->INDEX_TERM, or 0 if the index is
6565 more complicated than that. */
6568 get_index_scale (const struct address_info
*info
)
6570 rtx index
= *info
->index
;
6571 if (GET_CODE (index
) == MULT
6572 && CONST_INT_P (XEXP (index
, 1))
6573 && info
->index_term
== &XEXP (index
, 0))
6574 return INTVAL (XEXP (index
, 1));
6576 if (GET_CODE (index
) == ASHIFT
6577 && CONST_INT_P (XEXP (index
, 1))
6578 && info
->index_term
== &XEXP (index
, 0))
6579 return HOST_WIDE_INT_1
<< INTVAL (XEXP (index
, 1));
6581 if (info
->index
== info
->index_term
)
6587 /* Return the "index code" of INFO, in the form required by
6591 get_index_code (const struct address_info
*info
)
6594 return GET_CODE (*info
->index
);
6597 return GET_CODE (*info
->disp
);
6602 /* Return true if RTL X contains a SYMBOL_REF. */
6605 contains_symbol_ref_p (const_rtx x
)
6607 subrtx_iterator::array_type array
;
6608 FOR_EACH_SUBRTX (iter
, array
, x
, ALL
)
6609 if (SYMBOL_REF_P (*iter
))
6615 /* Return true if RTL X contains a SYMBOL_REF or LABEL_REF. */
6618 contains_symbolic_reference_p (const_rtx x
)
6620 subrtx_iterator::array_type array
;
6621 FOR_EACH_SUBRTX (iter
, array
, x
, ALL
)
6622 if (SYMBOL_REF_P (*iter
) || GET_CODE (*iter
) == LABEL_REF
)
6628 /* Return true if RTL X contains a constant pool address. */
6631 contains_constant_pool_address_p (const_rtx x
)
6633 subrtx_iterator::array_type array
;
6634 FOR_EACH_SUBRTX (iter
, array
, x
, ALL
)
6635 if (SYMBOL_REF_P (*iter
) && CONSTANT_POOL_ADDRESS_P (*iter
))
6642 /* Return true if X contains a thread-local symbol. */
6645 tls_referenced_p (const_rtx x
)
6647 if (!targetm
.have_tls
)
6650 subrtx_iterator::array_type array
;
6651 FOR_EACH_SUBRTX (iter
, array
, x
, ALL
)
6652 if (GET_CODE (*iter
) == SYMBOL_REF
&& SYMBOL_REF_TLS_MODEL (*iter
) != 0)
6657 /* Return true if reg REGNO with mode REG_MODE would be clobbered by the
6658 clobber_high operand in CLOBBER_HIGH_OP. */
6661 reg_is_clobbered_by_clobber_high (unsigned int regno
, machine_mode reg_mode
,
6662 const_rtx clobber_high_op
)
6664 unsigned int clobber_regno
= REGNO (clobber_high_op
);
6665 machine_mode clobber_mode
= GET_MODE (clobber_high_op
);
6666 unsigned char regno_nregs
= hard_regno_nregs (regno
, reg_mode
);
6668 /* Clobber high should always span exactly one register. */
6669 gcc_assert (REG_NREGS (clobber_high_op
) == 1);
6671 /* Clobber high needs to match with one of the registers in X. */
6672 if (clobber_regno
< regno
|| clobber_regno
>= regno
+ regno_nregs
)
6675 gcc_assert (reg_mode
!= BLKmode
&& clobber_mode
!= BLKmode
);
6677 if (reg_mode
== VOIDmode
)
6678 return clobber_mode
!= VOIDmode
;
6680 /* Clobber high will clobber if its size might be greater than the size of
6682 return maybe_gt (exact_div (GET_MODE_SIZE (reg_mode
), regno_nregs
),
6683 GET_MODE_SIZE (clobber_mode
));