1 /* Analyze RTL for GNU compiler.
2 Copyright (C) 1987-2015 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify it under
7 the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 3, or (at your option) any later
11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
23 #include "coretypes.h"
31 #include "insn-config.h"
33 #include "emit-rtl.h" /* FIXME: Can go away once crtl is moved to rtl.h. */
35 #include "addresses.h"
38 /* Forward declarations */
39 static void set_of_1 (rtx
, const_rtx
, void *);
40 static bool covers_regno_p (const_rtx
, unsigned int);
41 static bool covers_regno_no_parallel_p (const_rtx
, unsigned int);
42 static int computed_jump_p_1 (const_rtx
);
43 static void parms_set (rtx
, const_rtx
, void *);
45 static unsigned HOST_WIDE_INT
cached_nonzero_bits (const_rtx
, machine_mode
,
46 const_rtx
, machine_mode
,
47 unsigned HOST_WIDE_INT
);
48 static unsigned HOST_WIDE_INT
nonzero_bits1 (const_rtx
, machine_mode
,
49 const_rtx
, machine_mode
,
50 unsigned HOST_WIDE_INT
);
51 static unsigned int cached_num_sign_bit_copies (const_rtx
, machine_mode
, const_rtx
,
54 static unsigned int num_sign_bit_copies1 (const_rtx
, machine_mode
, const_rtx
,
55 machine_mode
, unsigned int);
57 rtx_subrtx_bound_info rtx_all_subrtx_bounds
[NUM_RTX_CODE
];
58 rtx_subrtx_bound_info rtx_nonconst_subrtx_bounds
[NUM_RTX_CODE
];
60 /* Truncation narrows the mode from SOURCE mode to DESTINATION mode.
61 If TARGET_MODE_REP_EXTENDED (DESTINATION, DESTINATION_REP) is
62 SIGN_EXTEND then while narrowing we also have to enforce the
63 representation and sign-extend the value to mode DESTINATION_REP.
65 If the value is already sign-extended to DESTINATION_REP mode we
66 can just switch to DESTINATION mode on it. For each pair of
67 integral modes SOURCE and DESTINATION, when truncating from SOURCE
68 to DESTINATION, NUM_SIGN_BIT_COPIES_IN_REP[SOURCE][DESTINATION]
69 contains the number of high-order bits in SOURCE that have to be
70 copies of the sign-bit so that we can do this mode-switch to
74 num_sign_bit_copies_in_rep
[MAX_MODE_INT
+ 1][MAX_MODE_INT
+ 1];
76 /* Store X into index I of ARRAY. ARRAY is known to have at least I
77 elements. Return the new base of ARRAY. */
80 typename
T::value_type
*
81 generic_subrtx_iterator
<T
>::add_single_to_queue (array_type
&array
,
83 size_t i
, value_type x
)
85 if (base
== array
.stack
)
92 gcc_checking_assert (i
== LOCAL_ELEMS
);
93 /* A previous iteration might also have moved from the stack to the
94 heap, in which case the heap array will already be big enough. */
95 if (vec_safe_length (array
.heap
) <= i
)
96 vec_safe_grow (array
.heap
, i
+ 1);
97 base
= array
.heap
->address ();
98 memcpy (base
, array
.stack
, sizeof (array
.stack
));
99 base
[LOCAL_ELEMS
] = x
;
102 unsigned int length
= array
.heap
->length ();
105 gcc_checking_assert (base
== array
.heap
->address ());
111 gcc_checking_assert (i
== length
);
112 vec_safe_push (array
.heap
, x
);
113 return array
.heap
->address ();
117 /* Add the subrtxes of X to worklist ARRAY, starting at END. Return the
118 number of elements added to the worklist. */
120 template <typename T
>
122 generic_subrtx_iterator
<T
>::add_subrtxes_to_queue (array_type
&array
,
124 size_t end
, rtx_type x
)
126 enum rtx_code code
= GET_CODE (x
);
127 const char *format
= GET_RTX_FORMAT (code
);
128 size_t orig_end
= end
;
129 if (__builtin_expect (INSN_P (x
), false))
131 /* Put the pattern at the top of the queue, since that's what
132 we're likely to want most. It also allows for the SEQUENCE
134 for (int i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; --i
)
135 if (format
[i
] == 'e')
137 value_type subx
= T::get_value (x
->u
.fld
[i
].rt_rtx
);
138 if (__builtin_expect (end
< LOCAL_ELEMS
, true))
141 base
= add_single_to_queue (array
, base
, end
++, subx
);
145 for (int i
= 0; format
[i
]; ++i
)
146 if (format
[i
] == 'e')
148 value_type subx
= T::get_value (x
->u
.fld
[i
].rt_rtx
);
149 if (__builtin_expect (end
< LOCAL_ELEMS
, true))
152 base
= add_single_to_queue (array
, base
, end
++, subx
);
154 else if (format
[i
] == 'E')
156 unsigned int length
= GET_NUM_ELEM (x
->u
.fld
[i
].rt_rtvec
);
157 rtx
*vec
= x
->u
.fld
[i
].rt_rtvec
->elem
;
158 if (__builtin_expect (end
+ length
<= LOCAL_ELEMS
, true))
159 for (unsigned int j
= 0; j
< length
; j
++)
160 base
[end
++] = T::get_value (vec
[j
]);
162 for (unsigned int j
= 0; j
< length
; j
++)
163 base
= add_single_to_queue (array
, base
, end
++,
164 T::get_value (vec
[j
]));
165 if (code
== SEQUENCE
&& end
== length
)
166 /* If the subrtxes of the sequence fill the entire array then
167 we know that no other parts of a containing insn are queued.
168 The caller is therefore iterating over the sequence as a
169 PATTERN (...), so we also want the patterns of the
171 for (unsigned int j
= 0; j
< length
; j
++)
173 typename
T::rtx_type x
= T::get_rtx (base
[j
]);
175 base
[j
] = T::get_value (PATTERN (x
));
178 return end
- orig_end
;
181 template <typename T
>
183 generic_subrtx_iterator
<T
>::free_array (array_type
&array
)
185 vec_free (array
.heap
);
188 template <typename T
>
189 const size_t generic_subrtx_iterator
<T
>::LOCAL_ELEMS
;
191 template class generic_subrtx_iterator
<const_rtx_accessor
>;
192 template class generic_subrtx_iterator
<rtx_var_accessor
>;
193 template class generic_subrtx_iterator
<rtx_ptr_accessor
>;
195 /* Return 1 if the value of X is unstable
196 (would be different at a different point in the program).
197 The frame pointer, arg pointer, etc. are considered stable
198 (within one function) and so is anything marked `unchanging'. */
201 rtx_unstable_p (const_rtx x
)
203 const RTX_CODE code
= GET_CODE (x
);
210 return !MEM_READONLY_P (x
) || rtx_unstable_p (XEXP (x
, 0));
219 /* As in rtx_varies_p, we have to use the actual rtx, not reg number. */
220 if (x
== frame_pointer_rtx
|| x
== hard_frame_pointer_rtx
221 /* The arg pointer varies if it is not a fixed register. */
222 || (x
== arg_pointer_rtx
&& fixed_regs
[ARG_POINTER_REGNUM
]))
224 /* ??? When call-clobbered, the value is stable modulo the restore
225 that must happen after a call. This currently screws up local-alloc
226 into believing that the restore is not needed. */
227 if (!PIC_OFFSET_TABLE_REG_CALL_CLOBBERED
&& x
== pic_offset_table_rtx
)
232 if (MEM_VOLATILE_P (x
))
241 fmt
= GET_RTX_FORMAT (code
);
242 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
245 if (rtx_unstable_p (XEXP (x
, i
)))
248 else if (fmt
[i
] == 'E')
251 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
252 if (rtx_unstable_p (XVECEXP (x
, i
, j
)))
259 /* Return 1 if X has a value that can vary even between two
260 executions of the program. 0 means X can be compared reliably
261 against certain constants or near-constants.
262 FOR_ALIAS is nonzero if we are called from alias analysis; if it is
263 zero, we are slightly more conservative.
264 The frame pointer and the arg pointer are considered constant. */
267 rtx_varies_p (const_rtx x
, bool for_alias
)
280 return !MEM_READONLY_P (x
) || rtx_varies_p (XEXP (x
, 0), for_alias
);
289 /* Note that we have to test for the actual rtx used for the frame
290 and arg pointers and not just the register number in case we have
291 eliminated the frame and/or arg pointer and are using it
293 if (x
== frame_pointer_rtx
|| x
== hard_frame_pointer_rtx
294 /* The arg pointer varies if it is not a fixed register. */
295 || (x
== arg_pointer_rtx
&& fixed_regs
[ARG_POINTER_REGNUM
]))
297 if (x
== pic_offset_table_rtx
298 /* ??? When call-clobbered, the value is stable modulo the restore
299 that must happen after a call. This currently screws up
300 local-alloc into believing that the restore is not needed, so we
301 must return 0 only if we are called from alias analysis. */
302 && (!PIC_OFFSET_TABLE_REG_CALL_CLOBBERED
|| for_alias
))
307 /* The operand 0 of a LO_SUM is considered constant
308 (in fact it is related specifically to operand 1)
309 during alias analysis. */
310 return (! for_alias
&& rtx_varies_p (XEXP (x
, 0), for_alias
))
311 || rtx_varies_p (XEXP (x
, 1), for_alias
);
314 if (MEM_VOLATILE_P (x
))
323 fmt
= GET_RTX_FORMAT (code
);
324 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
327 if (rtx_varies_p (XEXP (x
, i
), for_alias
))
330 else if (fmt
[i
] == 'E')
333 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
334 if (rtx_varies_p (XVECEXP (x
, i
, j
), for_alias
))
341 /* Compute an approximation for the offset between the register
342 FROM and TO for the current function, as it was at the start
346 get_initial_register_offset (int from
, int to
)
348 #ifdef ELIMINABLE_REGS
349 static const struct elim_table_t
353 } table
[] = ELIMINABLE_REGS
;
354 HOST_WIDE_INT offset1
, offset2
;
360 /* It is not safe to call INITIAL_ELIMINATION_OFFSET
361 before the reload pass. We need to give at least
362 an estimation for the resulting frame size. */
363 if (! reload_completed
)
365 offset1
= crtl
->outgoing_args_size
+ get_frame_size ();
366 #if !STACK_GROWS_DOWNWARD
369 if (to
== STACK_POINTER_REGNUM
)
371 else if (from
== STACK_POINTER_REGNUM
)
377 for (i
= 0; i
< ARRAY_SIZE (table
); i
++)
378 if (table
[i
].from
== from
)
380 if (table
[i
].to
== to
)
382 INITIAL_ELIMINATION_OFFSET (table
[i
].from
, table
[i
].to
,
386 for (j
= 0; j
< ARRAY_SIZE (table
); j
++)
388 if (table
[j
].to
== to
389 && table
[j
].from
== table
[i
].to
)
391 INITIAL_ELIMINATION_OFFSET (table
[i
].from
, table
[i
].to
,
393 INITIAL_ELIMINATION_OFFSET (table
[j
].from
, table
[j
].to
,
395 return offset1
+ offset2
;
397 if (table
[j
].from
== to
398 && table
[j
].to
== table
[i
].to
)
400 INITIAL_ELIMINATION_OFFSET (table
[i
].from
, table
[i
].to
,
402 INITIAL_ELIMINATION_OFFSET (table
[j
].from
, table
[j
].to
,
404 return offset1
- offset2
;
408 else if (table
[i
].to
== from
)
410 if (table
[i
].from
== to
)
412 INITIAL_ELIMINATION_OFFSET (table
[i
].from
, table
[i
].to
,
416 for (j
= 0; j
< ARRAY_SIZE (table
); j
++)
418 if (table
[j
].to
== to
419 && table
[j
].from
== table
[i
].from
)
421 INITIAL_ELIMINATION_OFFSET (table
[i
].from
, table
[i
].to
,
423 INITIAL_ELIMINATION_OFFSET (table
[j
].from
, table
[j
].to
,
425 return - offset1
+ offset2
;
427 if (table
[j
].from
== to
428 && table
[j
].to
== table
[i
].from
)
430 INITIAL_ELIMINATION_OFFSET (table
[i
].from
, table
[i
].to
,
432 INITIAL_ELIMINATION_OFFSET (table
[j
].from
, table
[j
].to
,
434 return - offset1
- offset2
;
439 /* If the requested register combination was not found,
440 try a different more simple combination. */
441 if (from
== ARG_POINTER_REGNUM
)
442 return get_initial_register_offset (HARD_FRAME_POINTER_REGNUM
, to
);
443 else if (to
== ARG_POINTER_REGNUM
)
444 return get_initial_register_offset (from
, HARD_FRAME_POINTER_REGNUM
);
445 else if (from
== HARD_FRAME_POINTER_REGNUM
)
446 return get_initial_register_offset (FRAME_POINTER_REGNUM
, to
);
447 else if (to
== HARD_FRAME_POINTER_REGNUM
)
448 return get_initial_register_offset (from
, FRAME_POINTER_REGNUM
);
453 HOST_WIDE_INT offset
;
458 if (reload_completed
)
460 INITIAL_FRAME_POINTER_OFFSET (offset
);
464 offset
= crtl
->outgoing_args_size
+ get_frame_size ();
465 #if !STACK_GROWS_DOWNWARD
470 if (to
== STACK_POINTER_REGNUM
)
472 else if (from
== STACK_POINTER_REGNUM
)
480 /* Return nonzero if the use of X+OFFSET as an address in a MEM with SIZE
481 bytes can cause a trap. MODE is the mode of the MEM (not that of X) and
482 UNALIGNED_MEMS controls whether nonzero is returned for unaligned memory
483 references on strict alignment machines. */
486 rtx_addr_can_trap_p_1 (const_rtx x
, HOST_WIDE_INT offset
, HOST_WIDE_INT size
,
487 machine_mode mode
, bool unaligned_mems
)
489 enum rtx_code code
= GET_CODE (x
);
491 /* The offset must be a multiple of the mode size if we are considering
492 unaligned memory references on strict alignment machines. */
493 if (STRICT_ALIGNMENT
&& unaligned_mems
&& GET_MODE_SIZE (mode
) != 0)
495 HOST_WIDE_INT actual_offset
= offset
;
497 #ifdef SPARC_STACK_BOUNDARY_HACK
498 /* ??? The SPARC port may claim a STACK_BOUNDARY higher than
499 the real alignment of %sp. However, when it does this, the
500 alignment of %sp+STACK_POINTER_OFFSET is STACK_BOUNDARY. */
501 if (SPARC_STACK_BOUNDARY_HACK
502 && (x
== stack_pointer_rtx
|| x
== hard_frame_pointer_rtx
))
503 actual_offset
-= STACK_POINTER_OFFSET
;
506 if (actual_offset
% GET_MODE_SIZE (mode
) != 0)
513 if (SYMBOL_REF_WEAK (x
))
515 if (!CONSTANT_POOL_ADDRESS_P (x
))
518 HOST_WIDE_INT decl_size
;
523 size
= GET_MODE_SIZE (mode
);
527 /* If the size of the access or of the symbol is unknown,
529 decl
= SYMBOL_REF_DECL (x
);
531 /* Else check that the access is in bounds. TODO: restructure
532 expr_size/tree_expr_size/int_expr_size and just use the latter. */
535 else if (DECL_P (decl
) && DECL_SIZE_UNIT (decl
))
536 decl_size
= (tree_fits_shwi_p (DECL_SIZE_UNIT (decl
))
537 ? tree_to_shwi (DECL_SIZE_UNIT (decl
))
539 else if (TREE_CODE (decl
) == STRING_CST
)
540 decl_size
= TREE_STRING_LENGTH (decl
);
541 else if (TYPE_SIZE_UNIT (TREE_TYPE (decl
)))
542 decl_size
= int_size_in_bytes (TREE_TYPE (decl
));
546 return (decl_size
<= 0 ? offset
!= 0 : offset
+ size
> decl_size
);
555 /* Stack references are assumed not to trap, but we need to deal with
556 nonsensical offsets. */
557 if (x
== frame_pointer_rtx
|| x
== hard_frame_pointer_rtx
558 || x
== stack_pointer_rtx
559 /* The arg pointer varies if it is not a fixed register. */
560 || (x
== arg_pointer_rtx
&& fixed_regs
[ARG_POINTER_REGNUM
]))
563 HOST_WIDE_INT red_zone_size
= RED_ZONE_SIZE
;
565 HOST_WIDE_INT red_zone_size
= 0;
567 HOST_WIDE_INT stack_boundary
= PREFERRED_STACK_BOUNDARY
569 HOST_WIDE_INT low_bound
, high_bound
;
572 size
= GET_MODE_SIZE (mode
);
574 if (x
== frame_pointer_rtx
)
576 if (FRAME_GROWS_DOWNWARD
)
578 high_bound
= STARTING_FRAME_OFFSET
;
579 low_bound
= high_bound
- get_frame_size ();
583 low_bound
= STARTING_FRAME_OFFSET
;
584 high_bound
= low_bound
+ get_frame_size ();
587 else if (x
== hard_frame_pointer_rtx
)
589 HOST_WIDE_INT sp_offset
590 = get_initial_register_offset (STACK_POINTER_REGNUM
,
591 HARD_FRAME_POINTER_REGNUM
);
592 HOST_WIDE_INT ap_offset
593 = get_initial_register_offset (ARG_POINTER_REGNUM
,
594 HARD_FRAME_POINTER_REGNUM
);
596 #if STACK_GROWS_DOWNWARD
597 low_bound
= sp_offset
- red_zone_size
- stack_boundary
;
598 high_bound
= ap_offset
599 + FIRST_PARM_OFFSET (current_function_decl
)
600 #if !ARGS_GROW_DOWNWARD
605 high_bound
= sp_offset
+ red_zone_size
+ stack_boundary
;
606 low_bound
= ap_offset
607 + FIRST_PARM_OFFSET (current_function_decl
)
608 #if ARGS_GROW_DOWNWARD
614 else if (x
== stack_pointer_rtx
)
616 HOST_WIDE_INT ap_offset
617 = get_initial_register_offset (ARG_POINTER_REGNUM
,
618 STACK_POINTER_REGNUM
);
620 #if STACK_GROWS_DOWNWARD
621 low_bound
= - red_zone_size
- stack_boundary
;
622 high_bound
= ap_offset
623 + FIRST_PARM_OFFSET (current_function_decl
)
624 #if !ARGS_GROW_DOWNWARD
629 high_bound
= red_zone_size
+ stack_boundary
;
630 low_bound
= ap_offset
631 + FIRST_PARM_OFFSET (current_function_decl
)
632 #if ARGS_GROW_DOWNWARD
640 /* We assume that accesses are safe to at least the
642 Examples are varargs and __builtin_return_address. */
643 #if ARGS_GROW_DOWNWARD
644 high_bound
= FIRST_PARM_OFFSET (current_function_decl
)
646 low_bound
= FIRST_PARM_OFFSET (current_function_decl
)
647 - crtl
->args
.size
- stack_boundary
;
649 low_bound
= FIRST_PARM_OFFSET (current_function_decl
)
651 high_bound
= FIRST_PARM_OFFSET (current_function_decl
)
652 + crtl
->args
.size
+ stack_boundary
;
656 if (offset
>= low_bound
&& offset
<= high_bound
- size
)
660 /* All of the virtual frame registers are stack references. */
661 if (REGNO (x
) >= FIRST_VIRTUAL_REGISTER
662 && REGNO (x
) <= LAST_VIRTUAL_REGISTER
)
667 return rtx_addr_can_trap_p_1 (XEXP (x
, 0), offset
, size
,
668 mode
, unaligned_mems
);
671 /* An address is assumed not to trap if:
672 - it is the pic register plus a constant. */
673 if (XEXP (x
, 0) == pic_offset_table_rtx
&& CONSTANT_P (XEXP (x
, 1)))
676 /* - or it is an address that can't trap plus a constant integer. */
677 if (CONST_INT_P (XEXP (x
, 1))
678 && !rtx_addr_can_trap_p_1 (XEXP (x
, 0), offset
+ INTVAL (XEXP (x
, 1)),
679 size
, mode
, unaligned_mems
))
686 return rtx_addr_can_trap_p_1 (XEXP (x
, 1), offset
, size
,
687 mode
, unaligned_mems
);
694 return rtx_addr_can_trap_p_1 (XEXP (x
, 0), offset
, size
,
695 mode
, unaligned_mems
);
701 /* If it isn't one of the case above, it can cause a trap. */
705 /* Return nonzero if the use of X as an address in a MEM can cause a trap. */
708 rtx_addr_can_trap_p (const_rtx x
)
710 return rtx_addr_can_trap_p_1 (x
, 0, 0, VOIDmode
, false);
713 /* Return true if X is an address that is known to not be zero. */
716 nonzero_address_p (const_rtx x
)
718 const enum rtx_code code
= GET_CODE (x
);
723 return flag_delete_null_pointer_checks
&& !SYMBOL_REF_WEAK (x
);
729 /* As in rtx_varies_p, we have to use the actual rtx, not reg number. */
730 if (x
== frame_pointer_rtx
|| x
== hard_frame_pointer_rtx
731 || x
== stack_pointer_rtx
732 || (x
== arg_pointer_rtx
&& fixed_regs
[ARG_POINTER_REGNUM
]))
734 /* All of the virtual frame registers are stack references. */
735 if (REGNO (x
) >= FIRST_VIRTUAL_REGISTER
736 && REGNO (x
) <= LAST_VIRTUAL_REGISTER
)
741 return nonzero_address_p (XEXP (x
, 0));
744 /* Handle PIC references. */
745 if (XEXP (x
, 0) == pic_offset_table_rtx
746 && CONSTANT_P (XEXP (x
, 1)))
751 /* Similar to the above; allow positive offsets. Further, since
752 auto-inc is only allowed in memories, the register must be a
754 if (CONST_INT_P (XEXP (x
, 1))
755 && INTVAL (XEXP (x
, 1)) > 0)
757 return nonzero_address_p (XEXP (x
, 0));
760 /* Similarly. Further, the offset is always positive. */
767 return nonzero_address_p (XEXP (x
, 0));
770 return nonzero_address_p (XEXP (x
, 1));
776 /* If it isn't one of the case above, might be zero. */
780 /* Return 1 if X refers to a memory location whose address
781 cannot be compared reliably with constant addresses,
782 or if X refers to a BLKmode memory object.
783 FOR_ALIAS is nonzero if we are called from alias analysis; if it is
784 zero, we are slightly more conservative. */
787 rtx_addr_varies_p (const_rtx x
, bool for_alias
)
798 return GET_MODE (x
) == BLKmode
|| rtx_varies_p (XEXP (x
, 0), for_alias
);
800 fmt
= GET_RTX_FORMAT (code
);
801 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
804 if (rtx_addr_varies_p (XEXP (x
, i
), for_alias
))
807 else if (fmt
[i
] == 'E')
810 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
811 if (rtx_addr_varies_p (XVECEXP (x
, i
, j
), for_alias
))
817 /* Return the CALL in X if there is one. */
820 get_call_rtx_from (rtx x
)
824 if (GET_CODE (x
) == PARALLEL
)
825 x
= XVECEXP (x
, 0, 0);
826 if (GET_CODE (x
) == SET
)
828 if (GET_CODE (x
) == CALL
&& MEM_P (XEXP (x
, 0)))
833 /* Return the value of the integer term in X, if one is apparent;
835 Only obvious integer terms are detected.
836 This is used in cse.c with the `related_value' field. */
839 get_integer_term (const_rtx x
)
841 if (GET_CODE (x
) == CONST
)
844 if (GET_CODE (x
) == MINUS
845 && CONST_INT_P (XEXP (x
, 1)))
846 return - INTVAL (XEXP (x
, 1));
847 if (GET_CODE (x
) == PLUS
848 && CONST_INT_P (XEXP (x
, 1)))
849 return INTVAL (XEXP (x
, 1));
853 /* If X is a constant, return the value sans apparent integer term;
855 Only obvious integer terms are detected. */
858 get_related_value (const_rtx x
)
860 if (GET_CODE (x
) != CONST
)
863 if (GET_CODE (x
) == PLUS
864 && CONST_INT_P (XEXP (x
, 1)))
866 else if (GET_CODE (x
) == MINUS
867 && CONST_INT_P (XEXP (x
, 1)))
872 /* Return true if SYMBOL is a SYMBOL_REF and OFFSET + SYMBOL points
873 to somewhere in the same object or object_block as SYMBOL. */
876 offset_within_block_p (const_rtx symbol
, HOST_WIDE_INT offset
)
880 if (GET_CODE (symbol
) != SYMBOL_REF
)
888 if (CONSTANT_POOL_ADDRESS_P (symbol
)
889 && offset
< (int) GET_MODE_SIZE (get_pool_mode (symbol
)))
892 decl
= SYMBOL_REF_DECL (symbol
);
893 if (decl
&& offset
< int_size_in_bytes (TREE_TYPE (decl
)))
897 if (SYMBOL_REF_HAS_BLOCK_INFO_P (symbol
)
898 && SYMBOL_REF_BLOCK (symbol
)
899 && SYMBOL_REF_BLOCK_OFFSET (symbol
) >= 0
900 && ((unsigned HOST_WIDE_INT
) offset
+ SYMBOL_REF_BLOCK_OFFSET (symbol
)
901 < (unsigned HOST_WIDE_INT
) SYMBOL_REF_BLOCK (symbol
)->size
))
907 /* Split X into a base and a constant offset, storing them in *BASE_OUT
908 and *OFFSET_OUT respectively. */
911 split_const (rtx x
, rtx
*base_out
, rtx
*offset_out
)
913 if (GET_CODE (x
) == CONST
)
916 if (GET_CODE (x
) == PLUS
&& CONST_INT_P (XEXP (x
, 1)))
918 *base_out
= XEXP (x
, 0);
919 *offset_out
= XEXP (x
, 1);
924 *offset_out
= const0_rtx
;
927 /* Return the number of places FIND appears within X. If COUNT_DEST is
928 zero, we do not count occurrences inside the destination of a SET. */
931 count_occurrences (const_rtx x
, const_rtx find
, int count_dest
)
935 const char *format_ptr
;
954 count
= count_occurrences (XEXP (x
, 0), find
, count_dest
);
956 count
+= count_occurrences (XEXP (x
, 1), find
, count_dest
);
960 if (MEM_P (find
) && rtx_equal_p (x
, find
))
965 if (SET_DEST (x
) == find
&& ! count_dest
)
966 return count_occurrences (SET_SRC (x
), find
, count_dest
);
973 format_ptr
= GET_RTX_FORMAT (code
);
976 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++)
978 switch (*format_ptr
++)
981 count
+= count_occurrences (XEXP (x
, i
), find
, count_dest
);
985 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
986 count
+= count_occurrences (XVECEXP (x
, i
, j
), find
, count_dest
);
994 /* Return TRUE if OP is a register or subreg of a register that
995 holds an unsigned quantity. Otherwise, return FALSE. */
998 unsigned_reg_p (rtx op
)
1002 && TYPE_UNSIGNED (TREE_TYPE (REG_EXPR (op
))))
1005 if (GET_CODE (op
) == SUBREG
1006 && SUBREG_PROMOTED_SIGN (op
))
1013 /* Nonzero if register REG appears somewhere within IN.
1014 Also works if REG is not a register; in this case it checks
1015 for a subexpression of IN that is Lisp "equal" to REG. */
1018 reg_mentioned_p (const_rtx reg
, const_rtx in
)
1030 if (GET_CODE (in
) == LABEL_REF
)
1031 return reg
== LABEL_REF_LABEL (in
);
1033 code
= GET_CODE (in
);
1037 /* Compare registers by number. */
1039 return REG_P (reg
) && REGNO (in
) == REGNO (reg
);
1041 /* These codes have no constituent expressions
1049 /* These are kept unique for a given value. */
1056 if (GET_CODE (reg
) == code
&& rtx_equal_p (reg
, in
))
1059 fmt
= GET_RTX_FORMAT (code
);
1061 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
1066 for (j
= XVECLEN (in
, i
) - 1; j
>= 0; j
--)
1067 if (reg_mentioned_p (reg
, XVECEXP (in
, i
, j
)))
1070 else if (fmt
[i
] == 'e'
1071 && reg_mentioned_p (reg
, XEXP (in
, i
)))
1077 /* Return 1 if in between BEG and END, exclusive of BEG and END, there is
1078 no CODE_LABEL insn. */
1081 no_labels_between_p (const rtx_insn
*beg
, const rtx_insn
*end
)
1086 for (p
= NEXT_INSN (beg
); p
!= end
; p
= NEXT_INSN (p
))
1092 /* Nonzero if register REG is used in an insn between
1093 FROM_INSN and TO_INSN (exclusive of those two). */
1096 reg_used_between_p (const_rtx reg
, const rtx_insn
*from_insn
,
1097 const rtx_insn
*to_insn
)
1101 if (from_insn
== to_insn
)
1104 for (insn
= NEXT_INSN (from_insn
); insn
!= to_insn
; insn
= NEXT_INSN (insn
))
1105 if (NONDEBUG_INSN_P (insn
)
1106 && (reg_overlap_mentioned_p (reg
, PATTERN (insn
))
1107 || (CALL_P (insn
) && find_reg_fusage (insn
, USE
, reg
))))
1112 /* Nonzero if the old value of X, a register, is referenced in BODY. If X
1113 is entirely replaced by a new value and the only use is as a SET_DEST,
1114 we do not consider it a reference. */
1117 reg_referenced_p (const_rtx x
, const_rtx body
)
1121 switch (GET_CODE (body
))
1124 if (reg_overlap_mentioned_p (x
, SET_SRC (body
)))
1127 /* If the destination is anything other than CC0, PC, a REG or a SUBREG
1128 of a REG that occupies all of the REG, the insn references X if
1129 it is mentioned in the destination. */
1130 if (GET_CODE (SET_DEST (body
)) != CC0
1131 && GET_CODE (SET_DEST (body
)) != PC
1132 && !REG_P (SET_DEST (body
))
1133 && ! (GET_CODE (SET_DEST (body
)) == SUBREG
1134 && REG_P (SUBREG_REG (SET_DEST (body
)))
1135 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (body
))))
1136 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
1137 == ((GET_MODE_SIZE (GET_MODE (SET_DEST (body
)))
1138 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)))
1139 && reg_overlap_mentioned_p (x
, SET_DEST (body
)))
1144 for (i
= ASM_OPERANDS_INPUT_LENGTH (body
) - 1; i
>= 0; i
--)
1145 if (reg_overlap_mentioned_p (x
, ASM_OPERANDS_INPUT (body
, i
)))
1152 return reg_overlap_mentioned_p (x
, body
);
1155 return reg_overlap_mentioned_p (x
, TRAP_CONDITION (body
));
1158 return reg_overlap_mentioned_p (x
, XEXP (body
, 0));
1161 case UNSPEC_VOLATILE
:
1162 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; i
--)
1163 if (reg_overlap_mentioned_p (x
, XVECEXP (body
, 0, i
)))
1168 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; i
--)
1169 if (reg_referenced_p (x
, XVECEXP (body
, 0, i
)))
1174 if (MEM_P (XEXP (body
, 0)))
1175 if (reg_overlap_mentioned_p (x
, XEXP (XEXP (body
, 0), 0)))
1180 if (reg_overlap_mentioned_p (x
, COND_EXEC_TEST (body
)))
1182 return reg_referenced_p (x
, COND_EXEC_CODE (body
));
1189 /* Nonzero if register REG is set or clobbered in an insn between
1190 FROM_INSN and TO_INSN (exclusive of those two). */
1193 reg_set_between_p (const_rtx reg
, const rtx_insn
*from_insn
,
1194 const rtx_insn
*to_insn
)
1196 const rtx_insn
*insn
;
1198 if (from_insn
== to_insn
)
1201 for (insn
= NEXT_INSN (from_insn
); insn
!= to_insn
; insn
= NEXT_INSN (insn
))
1202 if (INSN_P (insn
) && reg_set_p (reg
, insn
))
1207 /* Internals of reg_set_between_p. */
1209 reg_set_p (const_rtx reg
, const_rtx insn
)
1211 /* After delay slot handling, call and branch insns might be in a
1212 sequence. Check all the elements there. */
1213 if (INSN_P (insn
) && GET_CODE (PATTERN (insn
)) == SEQUENCE
)
1215 for (int i
= 0; i
< XVECLEN (PATTERN (insn
), 0); ++i
)
1216 if (reg_set_p (reg
, XVECEXP (PATTERN (insn
), 0, i
)))
1222 /* We can be passed an insn or part of one. If we are passed an insn,
1223 check if a side-effect of the insn clobbers REG. */
1225 && (FIND_REG_INC_NOTE (insn
, reg
)
1228 && REGNO (reg
) < FIRST_PSEUDO_REGISTER
1229 && overlaps_hard_reg_set_p (regs_invalidated_by_call
,
1230 GET_MODE (reg
), REGNO (reg
)))
1232 || find_reg_fusage (insn
, CLOBBER
, reg
)))))
1235 return set_of (reg
, insn
) != NULL_RTX
;
1238 /* Similar to reg_set_between_p, but check all registers in X. Return 0
1239 only if none of them are modified between START and END. Return 1 if
1240 X contains a MEM; this routine does use memory aliasing. */
1243 modified_between_p (const_rtx x
, const rtx_insn
*start
, const rtx_insn
*end
)
1245 const enum rtx_code code
= GET_CODE (x
);
1266 if (modified_between_p (XEXP (x
, 0), start
, end
))
1268 if (MEM_READONLY_P (x
))
1270 for (insn
= NEXT_INSN (start
); insn
!= end
; insn
= NEXT_INSN (insn
))
1271 if (memory_modified_in_insn_p (x
, insn
))
1277 return reg_set_between_p (x
, start
, end
);
1283 fmt
= GET_RTX_FORMAT (code
);
1284 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
1286 if (fmt
[i
] == 'e' && modified_between_p (XEXP (x
, i
), start
, end
))
1289 else if (fmt
[i
] == 'E')
1290 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
1291 if (modified_between_p (XVECEXP (x
, i
, j
), start
, end
))
1298 /* Similar to reg_set_p, but check all registers in X. Return 0 only if none
1299 of them are modified in INSN. Return 1 if X contains a MEM; this routine
1300 does use memory aliasing. */
1303 modified_in_p (const_rtx x
, const_rtx insn
)
1305 const enum rtx_code code
= GET_CODE (x
);
1322 if (modified_in_p (XEXP (x
, 0), insn
))
1324 if (MEM_READONLY_P (x
))
1326 if (memory_modified_in_insn_p (x
, insn
))
1332 return reg_set_p (x
, insn
);
1338 fmt
= GET_RTX_FORMAT (code
);
1339 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
1341 if (fmt
[i
] == 'e' && modified_in_p (XEXP (x
, i
), insn
))
1344 else if (fmt
[i
] == 'E')
1345 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
1346 if (modified_in_p (XVECEXP (x
, i
, j
), insn
))
1353 /* Helper function for set_of. */
1361 set_of_1 (rtx x
, const_rtx pat
, void *data1
)
1363 struct set_of_data
*const data
= (struct set_of_data
*) (data1
);
1364 if (rtx_equal_p (x
, data
->pat
)
1365 || (!MEM_P (x
) && reg_overlap_mentioned_p (data
->pat
, x
)))
1369 /* Give an INSN, return a SET or CLOBBER expression that does modify PAT
1370 (either directly or via STRICT_LOW_PART and similar modifiers). */
1372 set_of (const_rtx pat
, const_rtx insn
)
1374 struct set_of_data data
;
1375 data
.found
= NULL_RTX
;
1377 note_stores (INSN_P (insn
) ? PATTERN (insn
) : insn
, set_of_1
, &data
);
1381 /* Add all hard register in X to *PSET. */
1383 find_all_hard_regs (const_rtx x
, HARD_REG_SET
*pset
)
1385 subrtx_iterator::array_type array
;
1386 FOR_EACH_SUBRTX (iter
, array
, x
, NONCONST
)
1388 const_rtx x
= *iter
;
1389 if (REG_P (x
) && REGNO (x
) < FIRST_PSEUDO_REGISTER
)
1390 add_to_hard_reg_set (pset
, GET_MODE (x
), REGNO (x
));
1394 /* This function, called through note_stores, collects sets and
1395 clobbers of hard registers in a HARD_REG_SET, which is pointed to
1398 record_hard_reg_sets (rtx x
, const_rtx pat ATTRIBUTE_UNUSED
, void *data
)
1400 HARD_REG_SET
*pset
= (HARD_REG_SET
*)data
;
1401 if (REG_P (x
) && HARD_REGISTER_P (x
))
1402 add_to_hard_reg_set (pset
, GET_MODE (x
), REGNO (x
));
1405 /* Examine INSN, and compute the set of hard registers written by it.
1406 Store it in *PSET. Should only be called after reload. */
1408 find_all_hard_reg_sets (const rtx_insn
*insn
, HARD_REG_SET
*pset
, bool implicit
)
1412 CLEAR_HARD_REG_SET (*pset
);
1413 note_stores (PATTERN (insn
), record_hard_reg_sets
, pset
);
1417 IOR_HARD_REG_SET (*pset
, call_used_reg_set
);
1419 for (link
= CALL_INSN_FUNCTION_USAGE (insn
); link
; link
= XEXP (link
, 1))
1420 record_hard_reg_sets (XEXP (link
, 0), NULL
, pset
);
1422 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
1423 if (REG_NOTE_KIND (link
) == REG_INC
)
1424 record_hard_reg_sets (XEXP (link
, 0), NULL
, pset
);
1427 /* Like record_hard_reg_sets, but called through note_uses. */
1429 record_hard_reg_uses (rtx
*px
, void *data
)
1431 find_all_hard_regs (*px
, (HARD_REG_SET
*) data
);
1434 /* Given an INSN, return a SET expression if this insn has only a single SET.
1435 It may also have CLOBBERs, USEs, or SET whose output
1436 will not be used, which we ignore. */
1439 single_set_2 (const rtx_insn
*insn
, const_rtx pat
)
1442 int set_verified
= 1;
1445 if (GET_CODE (pat
) == PARALLEL
)
1447 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
1449 rtx sub
= XVECEXP (pat
, 0, i
);
1450 switch (GET_CODE (sub
))
1457 /* We can consider insns having multiple sets, where all
1458 but one are dead as single set insns. In common case
1459 only single set is present in the pattern so we want
1460 to avoid checking for REG_UNUSED notes unless necessary.
1462 When we reach set first time, we just expect this is
1463 the single set we are looking for and only when more
1464 sets are found in the insn, we check them. */
1467 if (find_reg_note (insn
, REG_UNUSED
, SET_DEST (set
))
1468 && !side_effects_p (set
))
1474 set
= sub
, set_verified
= 0;
1475 else if (!find_reg_note (insn
, REG_UNUSED
, SET_DEST (sub
))
1476 || side_effects_p (sub
))
1488 /* Given an INSN, return nonzero if it has more than one SET, else return
1492 multiple_sets (const_rtx insn
)
1497 /* INSN must be an insn. */
1498 if (! INSN_P (insn
))
1501 /* Only a PARALLEL can have multiple SETs. */
1502 if (GET_CODE (PATTERN (insn
)) == PARALLEL
)
1504 for (i
= 0, found
= 0; i
< XVECLEN (PATTERN (insn
), 0); i
++)
1505 if (GET_CODE (XVECEXP (PATTERN (insn
), 0, i
)) == SET
)
1507 /* If we have already found a SET, then return now. */
1515 /* Either zero or one SET. */
1519 /* Return nonzero if the destination of SET equals the source
1520 and there are no side effects. */
1523 set_noop_p (const_rtx set
)
1525 rtx src
= SET_SRC (set
);
1526 rtx dst
= SET_DEST (set
);
1528 if (dst
== pc_rtx
&& src
== pc_rtx
)
1531 if (MEM_P (dst
) && MEM_P (src
))
1532 return rtx_equal_p (dst
, src
) && !side_effects_p (dst
);
1534 if (GET_CODE (dst
) == ZERO_EXTRACT
)
1535 return rtx_equal_p (XEXP (dst
, 0), src
)
1536 && ! BYTES_BIG_ENDIAN
&& XEXP (dst
, 2) == const0_rtx
1537 && !side_effects_p (src
);
1539 if (GET_CODE (dst
) == STRICT_LOW_PART
)
1540 dst
= XEXP (dst
, 0);
1542 if (GET_CODE (src
) == SUBREG
&& GET_CODE (dst
) == SUBREG
)
1544 if (SUBREG_BYTE (src
) != SUBREG_BYTE (dst
))
1546 src
= SUBREG_REG (src
);
1547 dst
= SUBREG_REG (dst
);
1550 /* It is a NOOP if destination overlaps with selected src vector
1552 if (GET_CODE (src
) == VEC_SELECT
1553 && REG_P (XEXP (src
, 0)) && REG_P (dst
)
1554 && HARD_REGISTER_P (XEXP (src
, 0))
1555 && HARD_REGISTER_P (dst
))
1558 rtx par
= XEXP (src
, 1);
1559 rtx src0
= XEXP (src
, 0);
1560 int c0
= INTVAL (XVECEXP (par
, 0, 0));
1561 HOST_WIDE_INT offset
= GET_MODE_UNIT_SIZE (GET_MODE (src0
)) * c0
;
1563 for (i
= 1; i
< XVECLEN (par
, 0); i
++)
1564 if (INTVAL (XVECEXP (par
, 0, i
)) != c0
+ i
)
1567 simplify_subreg_regno (REGNO (src0
), GET_MODE (src0
),
1568 offset
, GET_MODE (dst
)) == (int) REGNO (dst
);
1571 return (REG_P (src
) && REG_P (dst
)
1572 && REGNO (src
) == REGNO (dst
));
1575 /* Return nonzero if an insn consists only of SETs, each of which only sets a
1579 noop_move_p (const rtx_insn
*insn
)
1581 rtx pat
= PATTERN (insn
);
1583 if (INSN_CODE (insn
) == NOOP_MOVE_INSN_CODE
)
1586 /* Insns carrying these notes are useful later on. */
1587 if (find_reg_note (insn
, REG_EQUAL
, NULL_RTX
))
1590 /* Check the code to be executed for COND_EXEC. */
1591 if (GET_CODE (pat
) == COND_EXEC
)
1592 pat
= COND_EXEC_CODE (pat
);
1594 if (GET_CODE (pat
) == SET
&& set_noop_p (pat
))
1597 if (GET_CODE (pat
) == PARALLEL
)
1600 /* If nothing but SETs of registers to themselves,
1601 this insn can also be deleted. */
1602 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
1604 rtx tem
= XVECEXP (pat
, 0, i
);
1606 if (GET_CODE (tem
) == USE
1607 || GET_CODE (tem
) == CLOBBER
)
1610 if (GET_CODE (tem
) != SET
|| ! set_noop_p (tem
))
1620 /* Return nonzero if register in range [REGNO, ENDREGNO)
1621 appears either explicitly or implicitly in X
1622 other than being stored into.
1624 References contained within the substructure at LOC do not count.
1625 LOC may be zero, meaning don't ignore anything. */
1628 refers_to_regno_p (unsigned int regno
, unsigned int endregno
, const_rtx x
,
1632 unsigned int x_regno
;
1637 /* The contents of a REG_NONNEG note is always zero, so we must come here
1638 upon repeat in case the last REG_NOTE is a REG_NONNEG note. */
1642 code
= GET_CODE (x
);
1647 x_regno
= REGNO (x
);
1649 /* If we modifying the stack, frame, or argument pointer, it will
1650 clobber a virtual register. In fact, we could be more precise,
1651 but it isn't worth it. */
1652 if ((x_regno
== STACK_POINTER_REGNUM
1653 || (FRAME_POINTER_REGNUM
!= ARG_POINTER_REGNUM
1654 && x_regno
== ARG_POINTER_REGNUM
)
1655 || x_regno
== FRAME_POINTER_REGNUM
)
1656 && regno
>= FIRST_VIRTUAL_REGISTER
&& regno
<= LAST_VIRTUAL_REGISTER
)
1659 return endregno
> x_regno
&& regno
< END_REGNO (x
);
1662 /* If this is a SUBREG of a hard reg, we can see exactly which
1663 registers are being modified. Otherwise, handle normally. */
1664 if (REG_P (SUBREG_REG (x
))
1665 && REGNO (SUBREG_REG (x
)) < FIRST_PSEUDO_REGISTER
)
1667 unsigned int inner_regno
= subreg_regno (x
);
1668 unsigned int inner_endregno
1669 = inner_regno
+ (inner_regno
< FIRST_PSEUDO_REGISTER
1670 ? subreg_nregs (x
) : 1);
1672 return endregno
> inner_regno
&& regno
< inner_endregno
;
1678 if (&SET_DEST (x
) != loc
1679 /* Note setting a SUBREG counts as referring to the REG it is in for
1680 a pseudo but not for hard registers since we can
1681 treat each word individually. */
1682 && ((GET_CODE (SET_DEST (x
)) == SUBREG
1683 && loc
!= &SUBREG_REG (SET_DEST (x
))
1684 && REG_P (SUBREG_REG (SET_DEST (x
)))
1685 && REGNO (SUBREG_REG (SET_DEST (x
))) >= FIRST_PSEUDO_REGISTER
1686 && refers_to_regno_p (regno
, endregno
,
1687 SUBREG_REG (SET_DEST (x
)), loc
))
1688 || (!REG_P (SET_DEST (x
))
1689 && refers_to_regno_p (regno
, endregno
, SET_DEST (x
), loc
))))
1692 if (code
== CLOBBER
|| loc
== &SET_SRC (x
))
1701 /* X does not match, so try its subexpressions. */
1703 fmt
= GET_RTX_FORMAT (code
);
1704 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
1706 if (fmt
[i
] == 'e' && loc
!= &XEXP (x
, i
))
1714 if (refers_to_regno_p (regno
, endregno
, XEXP (x
, i
), loc
))
1717 else if (fmt
[i
] == 'E')
1720 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
1721 if (loc
!= &XVECEXP (x
, i
, j
)
1722 && refers_to_regno_p (regno
, endregno
, XVECEXP (x
, i
, j
), loc
))
1729 /* Nonzero if modifying X will affect IN. If X is a register or a SUBREG,
1730 we check if any register number in X conflicts with the relevant register
1731 numbers. If X is a constant, return 0. If X is a MEM, return 1 iff IN
1732 contains a MEM (we don't bother checking for memory addresses that can't
1733 conflict because we expect this to be a rare case. */
1736 reg_overlap_mentioned_p (const_rtx x
, const_rtx in
)
1738 unsigned int regno
, endregno
;
1740 /* If either argument is a constant, then modifying X can not
1741 affect IN. Here we look at IN, we can profitably combine
1742 CONSTANT_P (x) with the switch statement below. */
1743 if (CONSTANT_P (in
))
1747 switch (GET_CODE (x
))
1749 case STRICT_LOW_PART
:
1752 /* Overly conservative. */
1757 regno
= REGNO (SUBREG_REG (x
));
1758 if (regno
< FIRST_PSEUDO_REGISTER
)
1759 regno
= subreg_regno (x
);
1760 endregno
= regno
+ (regno
< FIRST_PSEUDO_REGISTER
1761 ? subreg_nregs (x
) : 1);
1766 endregno
= END_REGNO (x
);
1768 return refers_to_regno_p (regno
, endregno
, in
, (rtx
*) 0);
1778 fmt
= GET_RTX_FORMAT (GET_CODE (in
));
1779 for (i
= GET_RTX_LENGTH (GET_CODE (in
)) - 1; i
>= 0; i
--)
1782 if (reg_overlap_mentioned_p (x
, XEXP (in
, i
)))
1785 else if (fmt
[i
] == 'E')
1788 for (j
= XVECLEN (in
, i
) - 1; j
>= 0; --j
)
1789 if (reg_overlap_mentioned_p (x
, XVECEXP (in
, i
, j
)))
1799 return reg_mentioned_p (x
, in
);
1805 /* If any register in here refers to it we return true. */
1806 for (i
= XVECLEN (x
, 0) - 1; i
>= 0; i
--)
1807 if (XEXP (XVECEXP (x
, 0, i
), 0) != 0
1808 && reg_overlap_mentioned_p (XEXP (XVECEXP (x
, 0, i
), 0), in
))
1814 gcc_assert (CONSTANT_P (x
));
1819 /* Call FUN on each register or MEM that is stored into or clobbered by X.
1820 (X would be the pattern of an insn). DATA is an arbitrary pointer,
1821 ignored by note_stores, but passed to FUN.
1823 FUN receives three arguments:
1824 1. the REG, MEM, CC0 or PC being stored in or clobbered,
1825 2. the SET or CLOBBER rtx that does the store,
1826 3. the pointer DATA provided to note_stores.
1828 If the item being stored in or clobbered is a SUBREG of a hard register,
1829 the SUBREG will be passed. */
1832 note_stores (const_rtx x
, void (*fun
) (rtx
, const_rtx
, void *), void *data
)
1836 if (GET_CODE (x
) == COND_EXEC
)
1837 x
= COND_EXEC_CODE (x
);
1839 if (GET_CODE (x
) == SET
|| GET_CODE (x
) == CLOBBER
)
1841 rtx dest
= SET_DEST (x
);
1843 while ((GET_CODE (dest
) == SUBREG
1844 && (!REG_P (SUBREG_REG (dest
))
1845 || REGNO (SUBREG_REG (dest
)) >= FIRST_PSEUDO_REGISTER
))
1846 || GET_CODE (dest
) == ZERO_EXTRACT
1847 || GET_CODE (dest
) == STRICT_LOW_PART
)
1848 dest
= XEXP (dest
, 0);
1850 /* If we have a PARALLEL, SET_DEST is a list of EXPR_LIST expressions,
1851 each of whose first operand is a register. */
1852 if (GET_CODE (dest
) == PARALLEL
)
1854 for (i
= XVECLEN (dest
, 0) - 1; i
>= 0; i
--)
1855 if (XEXP (XVECEXP (dest
, 0, i
), 0) != 0)
1856 (*fun
) (XEXP (XVECEXP (dest
, 0, i
), 0), x
, data
);
1859 (*fun
) (dest
, x
, data
);
1862 else if (GET_CODE (x
) == PARALLEL
)
1863 for (i
= XVECLEN (x
, 0) - 1; i
>= 0; i
--)
1864 note_stores (XVECEXP (x
, 0, i
), fun
, data
);
1867 /* Like notes_stores, but call FUN for each expression that is being
1868 referenced in PBODY, a pointer to the PATTERN of an insn. We only call
1869 FUN for each expression, not any interior subexpressions. FUN receives a
1870 pointer to the expression and the DATA passed to this function.
1872 Note that this is not quite the same test as that done in reg_referenced_p
1873 since that considers something as being referenced if it is being
1874 partially set, while we do not. */
1877 note_uses (rtx
*pbody
, void (*fun
) (rtx
*, void *), void *data
)
1882 switch (GET_CODE (body
))
1885 (*fun
) (&COND_EXEC_TEST (body
), data
);
1886 note_uses (&COND_EXEC_CODE (body
), fun
, data
);
1890 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; i
--)
1891 note_uses (&XVECEXP (body
, 0, i
), fun
, data
);
1895 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; i
--)
1896 note_uses (&PATTERN (XVECEXP (body
, 0, i
)), fun
, data
);
1900 (*fun
) (&XEXP (body
, 0), data
);
1904 for (i
= ASM_OPERANDS_INPUT_LENGTH (body
) - 1; i
>= 0; i
--)
1905 (*fun
) (&ASM_OPERANDS_INPUT (body
, i
), data
);
1909 (*fun
) (&TRAP_CONDITION (body
), data
);
1913 (*fun
) (&XEXP (body
, 0), data
);
1917 case UNSPEC_VOLATILE
:
1918 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; i
--)
1919 (*fun
) (&XVECEXP (body
, 0, i
), data
);
1923 if (MEM_P (XEXP (body
, 0)))
1924 (*fun
) (&XEXP (XEXP (body
, 0), 0), data
);
1929 rtx dest
= SET_DEST (body
);
1931 /* For sets we replace everything in source plus registers in memory
1932 expression in store and operands of a ZERO_EXTRACT. */
1933 (*fun
) (&SET_SRC (body
), data
);
1935 if (GET_CODE (dest
) == ZERO_EXTRACT
)
1937 (*fun
) (&XEXP (dest
, 1), data
);
1938 (*fun
) (&XEXP (dest
, 2), data
);
1941 while (GET_CODE (dest
) == SUBREG
|| GET_CODE (dest
) == STRICT_LOW_PART
)
1942 dest
= XEXP (dest
, 0);
1945 (*fun
) (&XEXP (dest
, 0), data
);
1950 /* All the other possibilities never store. */
1951 (*fun
) (pbody
, data
);
1956 /* Return nonzero if X's old contents don't survive after INSN.
1957 This will be true if X is (cc0) or if X is a register and
1958 X dies in INSN or because INSN entirely sets X.
1960 "Entirely set" means set directly and not through a SUBREG, or
1961 ZERO_EXTRACT, so no trace of the old contents remains.
1962 Likewise, REG_INC does not count.
1964 REG may be a hard or pseudo reg. Renumbering is not taken into account,
1965 but for this use that makes no difference, since regs don't overlap
1966 during their lifetimes. Therefore, this function may be used
1967 at any time after deaths have been computed.
1969 If REG is a hard reg that occupies multiple machine registers, this
1970 function will only return 1 if each of those registers will be replaced
1974 dead_or_set_p (const_rtx insn
, const_rtx x
)
1976 unsigned int regno
, end_regno
;
1979 /* Can't use cc0_rtx below since this file is used by genattrtab.c. */
1980 if (GET_CODE (x
) == CC0
)
1983 gcc_assert (REG_P (x
));
1986 end_regno
= END_REGNO (x
);
1987 for (i
= regno
; i
< end_regno
; i
++)
1988 if (! dead_or_set_regno_p (insn
, i
))
1994 /* Return TRUE iff DEST is a register or subreg of a register and
1995 doesn't change the number of words of the inner register, and any
1996 part of the register is TEST_REGNO. */
1999 covers_regno_no_parallel_p (const_rtx dest
, unsigned int test_regno
)
2001 unsigned int regno
, endregno
;
2003 if (GET_CODE (dest
) == SUBREG
2004 && (((GET_MODE_SIZE (GET_MODE (dest
))
2005 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
)
2006 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest
)))
2007 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
)))
2008 dest
= SUBREG_REG (dest
);
2013 regno
= REGNO (dest
);
2014 endregno
= END_REGNO (dest
);
2015 return (test_regno
>= regno
&& test_regno
< endregno
);
2018 /* Like covers_regno_no_parallel_p, but also handles PARALLELs where
2019 any member matches the covers_regno_no_parallel_p criteria. */
2022 covers_regno_p (const_rtx dest
, unsigned int test_regno
)
2024 if (GET_CODE (dest
) == PARALLEL
)
2026 /* Some targets place small structures in registers for return
2027 values of functions, and those registers are wrapped in
2028 PARALLELs that we may see as the destination of a SET. */
2031 for (i
= XVECLEN (dest
, 0) - 1; i
>= 0; i
--)
2033 rtx inner
= XEXP (XVECEXP (dest
, 0, i
), 0);
2034 if (inner
!= NULL_RTX
2035 && covers_regno_no_parallel_p (inner
, test_regno
))
2042 return covers_regno_no_parallel_p (dest
, test_regno
);
2045 /* Utility function for dead_or_set_p to check an individual register. */
2048 dead_or_set_regno_p (const_rtx insn
, unsigned int test_regno
)
2052 /* See if there is a death note for something that includes TEST_REGNO. */
2053 if (find_regno_note (insn
, REG_DEAD
, test_regno
))
2057 && find_regno_fusage (insn
, CLOBBER
, test_regno
))
2060 pattern
= PATTERN (insn
);
2062 /* If a COND_EXEC is not executed, the value survives. */
2063 if (GET_CODE (pattern
) == COND_EXEC
)
2066 if (GET_CODE (pattern
) == SET
)
2067 return covers_regno_p (SET_DEST (pattern
), test_regno
);
2068 else if (GET_CODE (pattern
) == PARALLEL
)
2072 for (i
= XVECLEN (pattern
, 0) - 1; i
>= 0; i
--)
2074 rtx body
= XVECEXP (pattern
, 0, i
);
2076 if (GET_CODE (body
) == COND_EXEC
)
2077 body
= COND_EXEC_CODE (body
);
2079 if ((GET_CODE (body
) == SET
|| GET_CODE (body
) == CLOBBER
)
2080 && covers_regno_p (SET_DEST (body
), test_regno
))
2088 /* Return the reg-note of kind KIND in insn INSN, if there is one.
2089 If DATUM is nonzero, look for one whose datum is DATUM. */
2092 find_reg_note (const_rtx insn
, enum reg_note kind
, const_rtx datum
)
2096 gcc_checking_assert (insn
);
2098 /* Ignore anything that is not an INSN, JUMP_INSN or CALL_INSN. */
2099 if (! INSN_P (insn
))
2103 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
2104 if (REG_NOTE_KIND (link
) == kind
)
2109 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
2110 if (REG_NOTE_KIND (link
) == kind
&& datum
== XEXP (link
, 0))
2115 /* Return the reg-note of kind KIND in insn INSN which applies to register
2116 number REGNO, if any. Return 0 if there is no such reg-note. Note that
2117 the REGNO of this NOTE need not be REGNO if REGNO is a hard register;
2118 it might be the case that the note overlaps REGNO. */
2121 find_regno_note (const_rtx insn
, enum reg_note kind
, unsigned int regno
)
2125 /* Ignore anything that is not an INSN, JUMP_INSN or CALL_INSN. */
2126 if (! INSN_P (insn
))
2129 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
2130 if (REG_NOTE_KIND (link
) == kind
2131 /* Verify that it is a register, so that scratch and MEM won't cause a
2133 && REG_P (XEXP (link
, 0))
2134 && REGNO (XEXP (link
, 0)) <= regno
2135 && END_REGNO (XEXP (link
, 0)) > regno
)
2140 /* Return a REG_EQUIV or REG_EQUAL note if insn has only a single set and
2144 find_reg_equal_equiv_note (const_rtx insn
)
2151 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
2152 if (REG_NOTE_KIND (link
) == REG_EQUAL
2153 || REG_NOTE_KIND (link
) == REG_EQUIV
)
2155 /* FIXME: We should never have REG_EQUAL/REG_EQUIV notes on
2156 insns that have multiple sets. Checking single_set to
2157 make sure of this is not the proper check, as explained
2158 in the comment in set_unique_reg_note.
2160 This should be changed into an assert. */
2161 if (GET_CODE (PATTERN (insn
)) == PARALLEL
&& multiple_sets (insn
))
2168 /* Check whether INSN is a single_set whose source is known to be
2169 equivalent to a constant. Return that constant if so, otherwise
2173 find_constant_src (const rtx_insn
*insn
)
2177 set
= single_set (insn
);
2180 x
= avoid_constant_pool_reference (SET_SRC (set
));
2185 note
= find_reg_equal_equiv_note (insn
);
2186 if (note
&& CONSTANT_P (XEXP (note
, 0)))
2187 return XEXP (note
, 0);
2192 /* Return true if DATUM, or any overlap of DATUM, of kind CODE is found
2193 in the CALL_INSN_FUNCTION_USAGE information of INSN. */
2196 find_reg_fusage (const_rtx insn
, enum rtx_code code
, const_rtx datum
)
2198 /* If it's not a CALL_INSN, it can't possibly have a
2199 CALL_INSN_FUNCTION_USAGE field, so don't bother checking. */
2209 for (link
= CALL_INSN_FUNCTION_USAGE (insn
);
2211 link
= XEXP (link
, 1))
2212 if (GET_CODE (XEXP (link
, 0)) == code
2213 && rtx_equal_p (datum
, XEXP (XEXP (link
, 0), 0)))
2218 unsigned int regno
= REGNO (datum
);
2220 /* CALL_INSN_FUNCTION_USAGE information cannot contain references
2221 to pseudo registers, so don't bother checking. */
2223 if (regno
< FIRST_PSEUDO_REGISTER
)
2225 unsigned int end_regno
= END_REGNO (datum
);
2228 for (i
= regno
; i
< end_regno
; i
++)
2229 if (find_regno_fusage (insn
, code
, i
))
2237 /* Return true if REGNO, or any overlap of REGNO, of kind CODE is found
2238 in the CALL_INSN_FUNCTION_USAGE information of INSN. */
2241 find_regno_fusage (const_rtx insn
, enum rtx_code code
, unsigned int regno
)
2245 /* CALL_INSN_FUNCTION_USAGE information cannot contain references
2246 to pseudo registers, so don't bother checking. */
2248 if (regno
>= FIRST_PSEUDO_REGISTER
2252 for (link
= CALL_INSN_FUNCTION_USAGE (insn
); link
; link
= XEXP (link
, 1))
2256 if (GET_CODE (op
= XEXP (link
, 0)) == code
2257 && REG_P (reg
= XEXP (op
, 0))
2258 && REGNO (reg
) <= regno
2259 && END_REGNO (reg
) > regno
)
2267 /* Return true if KIND is an integer REG_NOTE. */
2270 int_reg_note_p (enum reg_note kind
)
2272 return kind
== REG_BR_PROB
;
2275 /* Allocate a register note with kind KIND and datum DATUM. LIST is
2276 stored as the pointer to the next register note. */
2279 alloc_reg_note (enum reg_note kind
, rtx datum
, rtx list
)
2283 gcc_checking_assert (!int_reg_note_p (kind
));
2288 case REG_LABEL_TARGET
:
2289 case REG_LABEL_OPERAND
:
2291 /* These types of register notes use an INSN_LIST rather than an
2292 EXPR_LIST, so that copying is done right and dumps look
2294 note
= alloc_INSN_LIST (datum
, list
);
2295 PUT_REG_NOTE_KIND (note
, kind
);
2299 note
= alloc_EXPR_LIST (kind
, datum
, list
);
2306 /* Add register note with kind KIND and datum DATUM to INSN. */
2309 add_reg_note (rtx insn
, enum reg_note kind
, rtx datum
)
2311 REG_NOTES (insn
) = alloc_reg_note (kind
, datum
, REG_NOTES (insn
));
2314 /* Add an integer register note with kind KIND and datum DATUM to INSN. */
2317 add_int_reg_note (rtx insn
, enum reg_note kind
, int datum
)
2319 gcc_checking_assert (int_reg_note_p (kind
));
2320 REG_NOTES (insn
) = gen_rtx_INT_LIST ((machine_mode
) kind
,
2321 datum
, REG_NOTES (insn
));
2324 /* Add a register note like NOTE to INSN. */
2327 add_shallow_copy_of_reg_note (rtx_insn
*insn
, rtx note
)
2329 if (GET_CODE (note
) == INT_LIST
)
2330 add_int_reg_note (insn
, REG_NOTE_KIND (note
), XINT (note
, 0));
2332 add_reg_note (insn
, REG_NOTE_KIND (note
), XEXP (note
, 0));
2335 /* Remove register note NOTE from the REG_NOTES of INSN. */
2338 remove_note (rtx insn
, const_rtx note
)
2342 if (note
== NULL_RTX
)
2345 if (REG_NOTES (insn
) == note
)
2346 REG_NOTES (insn
) = XEXP (note
, 1);
2348 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
2349 if (XEXP (link
, 1) == note
)
2351 XEXP (link
, 1) = XEXP (note
, 1);
2355 switch (REG_NOTE_KIND (note
))
2359 df_notes_rescan (as_a
<rtx_insn
*> (insn
));
2366 /* Remove REG_EQUAL and/or REG_EQUIV notes if INSN has such notes. */
2369 remove_reg_equal_equiv_notes (rtx_insn
*insn
)
2373 loc
= ®_NOTES (insn
);
2376 enum reg_note kind
= REG_NOTE_KIND (*loc
);
2377 if (kind
== REG_EQUAL
|| kind
== REG_EQUIV
)
2378 *loc
= XEXP (*loc
, 1);
2380 loc
= &XEXP (*loc
, 1);
2384 /* Remove all REG_EQUAL and REG_EQUIV notes referring to REGNO. */
2387 remove_reg_equal_equiv_notes_for_regno (unsigned int regno
)
2394 /* This loop is a little tricky. We cannot just go down the chain because
2395 it is being modified by some actions in the loop. So we just iterate
2396 over the head. We plan to drain the list anyway. */
2397 while ((eq_use
= DF_REG_EQ_USE_CHAIN (regno
)) != NULL
)
2399 rtx_insn
*insn
= DF_REF_INSN (eq_use
);
2400 rtx note
= find_reg_equal_equiv_note (insn
);
2402 /* This assert is generally triggered when someone deletes a REG_EQUAL
2403 or REG_EQUIV note by hacking the list manually rather than calling
2407 remove_note (insn
, note
);
2411 /* Search LISTP (an EXPR_LIST) for an entry whose first operand is NODE and
2412 return 1 if it is found. A simple equality test is used to determine if
2416 in_insn_list_p (const rtx_insn_list
*listp
, const rtx_insn
*node
)
2420 for (x
= listp
; x
; x
= XEXP (x
, 1))
2421 if (node
== XEXP (x
, 0))
2427 /* Search LISTP (an EXPR_LIST) for an entry whose first operand is NODE and
2428 remove that entry from the list if it is found.
2430 A simple equality test is used to determine if NODE matches. */
2433 remove_node_from_expr_list (const_rtx node
, rtx_expr_list
**listp
)
2435 rtx_expr_list
*temp
= *listp
;
2436 rtx_expr_list
*prev
= NULL
;
2440 if (node
== temp
->element ())
2442 /* Splice the node out of the list. */
2444 XEXP (prev
, 1) = temp
->next ();
2446 *listp
= temp
->next ();
2452 temp
= temp
->next ();
2456 /* Search LISTP (an INSN_LIST) for an entry whose first operand is NODE and
2457 remove that entry from the list if it is found.
2459 A simple equality test is used to determine if NODE matches. */
2462 remove_node_from_insn_list (const rtx_insn
*node
, rtx_insn_list
**listp
)
2464 rtx_insn_list
*temp
= *listp
;
2465 rtx_insn_list
*prev
= NULL
;
2469 if (node
== temp
->insn ())
2471 /* Splice the node out of the list. */
2473 XEXP (prev
, 1) = temp
->next ();
2475 *listp
= temp
->next ();
2481 temp
= temp
->next ();
2485 /* Nonzero if X contains any volatile instructions. These are instructions
2486 which may cause unpredictable machine state instructions, and thus no
2487 instructions or register uses should be moved or combined across them.
2488 This includes only volatile asms and UNSPEC_VOLATILE instructions. */
2491 volatile_insn_p (const_rtx x
)
2493 const RTX_CODE code
= GET_CODE (x
);
2511 case UNSPEC_VOLATILE
:
2516 if (MEM_VOLATILE_P (x
))
2523 /* Recursively scan the operands of this expression. */
2526 const char *const fmt
= GET_RTX_FORMAT (code
);
2529 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
2533 if (volatile_insn_p (XEXP (x
, i
)))
2536 else if (fmt
[i
] == 'E')
2539 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
2540 if (volatile_insn_p (XVECEXP (x
, i
, j
)))
2548 /* Nonzero if X contains any volatile memory references
2549 UNSPEC_VOLATILE operations or volatile ASM_OPERANDS expressions. */
2552 volatile_refs_p (const_rtx x
)
2554 const RTX_CODE code
= GET_CODE (x
);
2570 case UNSPEC_VOLATILE
:
2576 if (MEM_VOLATILE_P (x
))
2583 /* Recursively scan the operands of this expression. */
2586 const char *const fmt
= GET_RTX_FORMAT (code
);
2589 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
2593 if (volatile_refs_p (XEXP (x
, i
)))
2596 else if (fmt
[i
] == 'E')
2599 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
2600 if (volatile_refs_p (XVECEXP (x
, i
, j
)))
2608 /* Similar to above, except that it also rejects register pre- and post-
2612 side_effects_p (const_rtx x
)
2614 const RTX_CODE code
= GET_CODE (x
);
2631 /* Reject CLOBBER with a non-VOID mode. These are made by combine.c
2632 when some combination can't be done. If we see one, don't think
2633 that we can simplify the expression. */
2634 return (GET_MODE (x
) != VOIDmode
);
2643 case UNSPEC_VOLATILE
:
2649 if (MEM_VOLATILE_P (x
))
2656 /* Recursively scan the operands of this expression. */
2659 const char *fmt
= GET_RTX_FORMAT (code
);
2662 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
2666 if (side_effects_p (XEXP (x
, i
)))
2669 else if (fmt
[i
] == 'E')
2672 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
2673 if (side_effects_p (XVECEXP (x
, i
, j
)))
2681 /* Return nonzero if evaluating rtx X might cause a trap.
2682 FLAGS controls how to consider MEMs. A nonzero means the context
2683 of the access may have changed from the original, such that the
2684 address may have become invalid. */
2687 may_trap_p_1 (const_rtx x
, unsigned flags
)
2693 /* We make no distinction currently, but this function is part of
2694 the internal target-hooks ABI so we keep the parameter as
2695 "unsigned flags". */
2696 bool code_changed
= flags
!= 0;
2700 code
= GET_CODE (x
);
2703 /* Handle these cases quickly. */
2715 return targetm
.unspec_may_trap_p (x
, flags
);
2717 case UNSPEC_VOLATILE
:
2723 return MEM_VOLATILE_P (x
);
2725 /* Memory ref can trap unless it's a static var or a stack slot. */
2727 /* Recognize specific pattern of stack checking probes. */
2728 if (flag_stack_check
2729 && MEM_VOLATILE_P (x
)
2730 && XEXP (x
, 0) == stack_pointer_rtx
)
2732 if (/* MEM_NOTRAP_P only relates to the actual position of the memory
2733 reference; moving it out of context such as when moving code
2734 when optimizing, might cause its address to become invalid. */
2736 || !MEM_NOTRAP_P (x
))
2738 HOST_WIDE_INT size
= MEM_SIZE_KNOWN_P (x
) ? MEM_SIZE (x
) : 0;
2739 return rtx_addr_can_trap_p_1 (XEXP (x
, 0), 0, size
,
2740 GET_MODE (x
), code_changed
);
2745 /* Division by a non-constant might trap. */
2750 if (HONOR_SNANS (x
))
2752 if (SCALAR_FLOAT_MODE_P (GET_MODE (x
)))
2753 return flag_trapping_math
;
2754 if (!CONSTANT_P (XEXP (x
, 1)) || (XEXP (x
, 1) == const0_rtx
))
2759 /* An EXPR_LIST is used to represent a function call. This
2760 certainly may trap. */
2769 /* Some floating point comparisons may trap. */
2770 if (!flag_trapping_math
)
2772 /* ??? There is no machine independent way to check for tests that trap
2773 when COMPARE is used, though many targets do make this distinction.
2774 For instance, sparc uses CCFPE for compares which generate exceptions
2775 and CCFP for compares which do not generate exceptions. */
2778 /* But often the compare has some CC mode, so check operand
2780 if (HONOR_NANS (XEXP (x
, 0))
2781 || HONOR_NANS (XEXP (x
, 1)))
2787 if (HONOR_SNANS (x
))
2789 /* Often comparison is CC mode, so check operand modes. */
2790 if (HONOR_SNANS (XEXP (x
, 0))
2791 || HONOR_SNANS (XEXP (x
, 1)))
2796 /* Conversion of floating point might trap. */
2797 if (flag_trapping_math
&& HONOR_NANS (XEXP (x
, 0)))
2804 /* These operations don't trap even with floating point. */
2808 /* Any floating arithmetic may trap. */
2809 if (SCALAR_FLOAT_MODE_P (GET_MODE (x
)) && flag_trapping_math
)
2813 fmt
= GET_RTX_FORMAT (code
);
2814 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
2818 if (may_trap_p_1 (XEXP (x
, i
), flags
))
2821 else if (fmt
[i
] == 'E')
2824 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
2825 if (may_trap_p_1 (XVECEXP (x
, i
, j
), flags
))
2832 /* Return nonzero if evaluating rtx X might cause a trap. */
2835 may_trap_p (const_rtx x
)
2837 return may_trap_p_1 (x
, 0);
2840 /* Same as above, but additionally return nonzero if evaluating rtx X might
2841 cause a fault. We define a fault for the purpose of this function as a
2842 erroneous execution condition that cannot be encountered during the normal
2843 execution of a valid program; the typical example is an unaligned memory
2844 access on a strict alignment machine. The compiler guarantees that it
2845 doesn't generate code that will fault from a valid program, but this
2846 guarantee doesn't mean anything for individual instructions. Consider
2847 the following example:
2849 struct S { int d; union { char *cp; int *ip; }; };
2851 int foo(struct S *s)
2859 on a strict alignment machine. In a valid program, foo will never be
2860 invoked on a structure for which d is equal to 1 and the underlying
2861 unique field of the union not aligned on a 4-byte boundary, but the
2862 expression *s->ip might cause a fault if considered individually.
2864 At the RTL level, potentially problematic expressions will almost always
2865 verify may_trap_p; for example, the above dereference can be emitted as
2866 (mem:SI (reg:P)) and this expression is may_trap_p for a generic register.
2867 However, suppose that foo is inlined in a caller that causes s->cp to
2868 point to a local character variable and guarantees that s->d is not set
2869 to 1; foo may have been effectively translated into pseudo-RTL as:
2872 (set (reg:SI) (mem:SI (%fp - 7)))
2874 (set (reg:QI) (mem:QI (%fp - 7)))
2876 Now (mem:SI (%fp - 7)) is considered as not may_trap_p since it is a
2877 memory reference to a stack slot, but it will certainly cause a fault
2878 on a strict alignment machine. */
2881 may_trap_or_fault_p (const_rtx x
)
2883 return may_trap_p_1 (x
, 1);
2886 /* Return nonzero if X contains a comparison that is not either EQ or NE,
2887 i.e., an inequality. */
2890 inequality_comparisons_p (const_rtx x
)
2894 const enum rtx_code code
= GET_CODE (x
);
2922 len
= GET_RTX_LENGTH (code
);
2923 fmt
= GET_RTX_FORMAT (code
);
2925 for (i
= 0; i
< len
; i
++)
2929 if (inequality_comparisons_p (XEXP (x
, i
)))
2932 else if (fmt
[i
] == 'E')
2935 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
2936 if (inequality_comparisons_p (XVECEXP (x
, i
, j
)))
2944 /* Replace any occurrence of FROM in X with TO. The function does
2945 not enter into CONST_DOUBLE for the replace.
2947 Note that copying is not done so X must not be shared unless all copies
2948 are to be modified. */
2951 replace_rtx (rtx x
, rtx from
, rtx to
)
2959 /* Allow this function to make replacements in EXPR_LISTs. */
2963 if (GET_CODE (x
) == SUBREG
)
2965 rtx new_rtx
= replace_rtx (SUBREG_REG (x
), from
, to
);
2967 if (CONST_INT_P (new_rtx
))
2969 x
= simplify_subreg (GET_MODE (x
), new_rtx
,
2970 GET_MODE (SUBREG_REG (x
)),
2975 SUBREG_REG (x
) = new_rtx
;
2979 else if (GET_CODE (x
) == ZERO_EXTEND
)
2981 rtx new_rtx
= replace_rtx (XEXP (x
, 0), from
, to
);
2983 if (CONST_INT_P (new_rtx
))
2985 x
= simplify_unary_operation (ZERO_EXTEND
, GET_MODE (x
),
2986 new_rtx
, GET_MODE (XEXP (x
, 0)));
2990 XEXP (x
, 0) = new_rtx
;
2995 fmt
= GET_RTX_FORMAT (GET_CODE (x
));
2996 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
2999 XEXP (x
, i
) = replace_rtx (XEXP (x
, i
), from
, to
);
3000 else if (fmt
[i
] == 'E')
3001 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3002 XVECEXP (x
, i
, j
) = replace_rtx (XVECEXP (x
, i
, j
), from
, to
);
3008 /* Replace occurrences of the OLD_LABEL in *LOC with NEW_LABEL. Also track
3009 the change in LABEL_NUSES if UPDATE_LABEL_NUSES. */
3012 replace_label (rtx
*loc
, rtx old_label
, rtx new_label
, bool update_label_nuses
)
3014 /* Handle jump tables specially, since ADDR_{DIFF_,}VECs can be long. */
3016 if (JUMP_TABLE_DATA_P (x
))
3019 rtvec vec
= XVEC (x
, GET_CODE (x
) == ADDR_DIFF_VEC
);
3020 int len
= GET_NUM_ELEM (vec
);
3021 for (int i
= 0; i
< len
; ++i
)
3023 rtx ref
= RTVEC_ELT (vec
, i
);
3024 if (XEXP (ref
, 0) == old_label
)
3026 XEXP (ref
, 0) = new_label
;
3027 if (update_label_nuses
)
3029 ++LABEL_NUSES (new_label
);
3030 --LABEL_NUSES (old_label
);
3037 /* If this is a JUMP_INSN, then we also need to fix the JUMP_LABEL
3038 field. This is not handled by the iterator because it doesn't
3039 handle unprinted ('0') fields. */
3040 if (JUMP_P (x
) && JUMP_LABEL (x
) == old_label
)
3041 JUMP_LABEL (x
) = new_label
;
3043 subrtx_ptr_iterator::array_type array
;
3044 FOR_EACH_SUBRTX_PTR (iter
, array
, loc
, ALL
)
3049 if (GET_CODE (x
) == SYMBOL_REF
3050 && CONSTANT_POOL_ADDRESS_P (x
))
3052 rtx c
= get_pool_constant (x
);
3053 if (rtx_referenced_p (old_label
, c
))
3055 /* Create a copy of constant C; replace the label inside
3056 but do not update LABEL_NUSES because uses in constant pool
3058 rtx new_c
= copy_rtx (c
);
3059 replace_label (&new_c
, old_label
, new_label
, false);
3061 /* Add the new constant NEW_C to constant pool and replace
3062 the old reference to constant by new reference. */
3063 rtx new_mem
= force_const_mem (get_pool_mode (x
), new_c
);
3064 *loc
= replace_rtx (x
, x
, XEXP (new_mem
, 0));
3068 if ((GET_CODE (x
) == LABEL_REF
3069 || GET_CODE (x
) == INSN_LIST
)
3070 && XEXP (x
, 0) == old_label
)
3072 XEXP (x
, 0) = new_label
;
3073 if (update_label_nuses
)
3075 ++LABEL_NUSES (new_label
);
3076 --LABEL_NUSES (old_label
);
3084 replace_label_in_insn (rtx_insn
*insn
, rtx old_label
, rtx new_label
,
3085 bool update_label_nuses
)
3087 rtx insn_as_rtx
= insn
;
3088 replace_label (&insn_as_rtx
, old_label
, new_label
, update_label_nuses
);
3089 gcc_checking_assert (insn_as_rtx
== insn
);
3092 /* Return true if X is referenced in BODY. */
3095 rtx_referenced_p (const_rtx x
, const_rtx body
)
3097 subrtx_iterator::array_type array
;
3098 FOR_EACH_SUBRTX (iter
, array
, body
, ALL
)
3099 if (const_rtx y
= *iter
)
3101 /* Check if a label_ref Y refers to label X. */
3102 if (GET_CODE (y
) == LABEL_REF
3104 && LABEL_REF_LABEL (y
) == x
)
3107 if (rtx_equal_p (x
, y
))
3110 /* If Y is a reference to pool constant traverse the constant. */
3111 if (GET_CODE (y
) == SYMBOL_REF
3112 && CONSTANT_POOL_ADDRESS_P (y
))
3113 iter
.substitute (get_pool_constant (y
));
3118 /* If INSN is a tablejump return true and store the label (before jump table) to
3119 *LABELP and the jump table to *TABLEP. LABELP and TABLEP may be NULL. */
3122 tablejump_p (const rtx_insn
*insn
, rtx
*labelp
, rtx_jump_table_data
**tablep
)
3130 label
= JUMP_LABEL (insn
);
3131 if (label
!= NULL_RTX
&& !ANY_RETURN_P (label
)
3132 && (table
= NEXT_INSN (as_a
<rtx_insn
*> (label
))) != NULL_RTX
3133 && JUMP_TABLE_DATA_P (table
))
3138 *tablep
= as_a
<rtx_jump_table_data
*> (table
);
3144 /* A subroutine of computed_jump_p, return 1 if X contains a REG or MEM or
3145 constant that is not in the constant pool and not in the condition
3146 of an IF_THEN_ELSE. */
3149 computed_jump_p_1 (const_rtx x
)
3151 const enum rtx_code code
= GET_CODE (x
);
3168 return ! (GET_CODE (XEXP (x
, 0)) == SYMBOL_REF
3169 && CONSTANT_POOL_ADDRESS_P (XEXP (x
, 0)));
3172 return (computed_jump_p_1 (XEXP (x
, 1))
3173 || computed_jump_p_1 (XEXP (x
, 2)));
3179 fmt
= GET_RTX_FORMAT (code
);
3180 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
3183 && computed_jump_p_1 (XEXP (x
, i
)))
3186 else if (fmt
[i
] == 'E')
3187 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
3188 if (computed_jump_p_1 (XVECEXP (x
, i
, j
)))
3195 /* Return nonzero if INSN is an indirect jump (aka computed jump).
3197 Tablejumps and casesi insns are not considered indirect jumps;
3198 we can recognize them by a (use (label_ref)). */
3201 computed_jump_p (const rtx_insn
*insn
)
3206 rtx pat
= PATTERN (insn
);
3208 /* If we have a JUMP_LABEL set, we're not a computed jump. */
3209 if (JUMP_LABEL (insn
) != NULL
)
3212 if (GET_CODE (pat
) == PARALLEL
)
3214 int len
= XVECLEN (pat
, 0);
3215 int has_use_labelref
= 0;
3217 for (i
= len
- 1; i
>= 0; i
--)
3218 if (GET_CODE (XVECEXP (pat
, 0, i
)) == USE
3219 && (GET_CODE (XEXP (XVECEXP (pat
, 0, i
), 0))
3222 has_use_labelref
= 1;
3226 if (! has_use_labelref
)
3227 for (i
= len
- 1; i
>= 0; i
--)
3228 if (GET_CODE (XVECEXP (pat
, 0, i
)) == SET
3229 && SET_DEST (XVECEXP (pat
, 0, i
)) == pc_rtx
3230 && computed_jump_p_1 (SET_SRC (XVECEXP (pat
, 0, i
))))
3233 else if (GET_CODE (pat
) == SET
3234 && SET_DEST (pat
) == pc_rtx
3235 && computed_jump_p_1 (SET_SRC (pat
)))
3243 /* MEM has a PRE/POST-INC/DEC/MODIFY address X. Extract the operands of
3244 the equivalent add insn and pass the result to FN, using DATA as the
3248 for_each_inc_dec_find_inc_dec (rtx mem
, for_each_inc_dec_fn fn
, void *data
)
3250 rtx x
= XEXP (mem
, 0);
3251 switch (GET_CODE (x
))
3256 int size
= GET_MODE_SIZE (GET_MODE (mem
));
3257 rtx r1
= XEXP (x
, 0);
3258 rtx c
= gen_int_mode (size
, GET_MODE (r1
));
3259 return fn (mem
, x
, r1
, r1
, c
, data
);
3265 int size
= GET_MODE_SIZE (GET_MODE (mem
));
3266 rtx r1
= XEXP (x
, 0);
3267 rtx c
= gen_int_mode (-size
, GET_MODE (r1
));
3268 return fn (mem
, x
, r1
, r1
, c
, data
);
3274 rtx r1
= XEXP (x
, 0);
3275 rtx add
= XEXP (x
, 1);
3276 return fn (mem
, x
, r1
, add
, NULL
, data
);
3284 /* Traverse *LOC looking for MEMs that have autoinc addresses.
3285 For each such autoinc operation found, call FN, passing it
3286 the innermost enclosing MEM, the operation itself, the RTX modified
3287 by the operation, two RTXs (the second may be NULL) that, once
3288 added, represent the value to be held by the modified RTX
3289 afterwards, and DATA. FN is to return 0 to continue the
3290 traversal or any other value to have it returned to the caller of
3291 for_each_inc_dec. */
3294 for_each_inc_dec (rtx x
,
3295 for_each_inc_dec_fn fn
,
3298 subrtx_var_iterator::array_type array
;
3299 FOR_EACH_SUBRTX_VAR (iter
, array
, x
, NONCONST
)
3304 && GET_RTX_CLASS (GET_CODE (XEXP (mem
, 0))) == RTX_AUTOINC
)
3306 int res
= for_each_inc_dec_find_inc_dec (mem
, fn
, data
);
3309 iter
.skip_subrtxes ();
3316 /* Searches X for any reference to REGNO, returning the rtx of the
3317 reference found if any. Otherwise, returns NULL_RTX. */
3320 regno_use_in (unsigned int regno
, rtx x
)
3326 if (REG_P (x
) && REGNO (x
) == regno
)
3329 fmt
= GET_RTX_FORMAT (GET_CODE (x
));
3330 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
3334 if ((tem
= regno_use_in (regno
, XEXP (x
, i
))))
3337 else if (fmt
[i
] == 'E')
3338 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3339 if ((tem
= regno_use_in (regno
, XVECEXP (x
, i
, j
))))
3346 /* Return a value indicating whether OP, an operand of a commutative
3347 operation, is preferred as the first or second operand. The more
3348 positive the value, the stronger the preference for being the first
3352 commutative_operand_precedence (rtx op
)
3354 enum rtx_code code
= GET_CODE (op
);
3356 /* Constants always become the second operand. Prefer "nice" constants. */
3357 if (code
== CONST_INT
)
3359 if (code
== CONST_WIDE_INT
)
3361 if (code
== CONST_DOUBLE
)
3363 if (code
== CONST_FIXED
)
3365 op
= avoid_constant_pool_reference (op
);
3366 code
= GET_CODE (op
);
3368 switch (GET_RTX_CLASS (code
))
3371 if (code
== CONST_INT
)
3373 if (code
== CONST_WIDE_INT
)
3375 if (code
== CONST_DOUBLE
)
3377 if (code
== CONST_FIXED
)
3382 /* SUBREGs of objects should come second. */
3383 if (code
== SUBREG
&& OBJECT_P (SUBREG_REG (op
)))
3388 /* Complex expressions should be the first, so decrease priority
3389 of objects. Prefer pointer objects over non pointer objects. */
3390 if ((REG_P (op
) && REG_POINTER (op
))
3391 || (MEM_P (op
) && MEM_POINTER (op
)))
3395 case RTX_COMM_ARITH
:
3396 /* Prefer operands that are themselves commutative to be first.
3397 This helps to make things linear. In particular,
3398 (and (and (reg) (reg)) (not (reg))) is canonical. */
3402 /* If only one operand is a binary expression, it will be the first
3403 operand. In particular, (plus (minus (reg) (reg)) (neg (reg)))
3404 is canonical, although it will usually be further simplified. */
3408 /* Then prefer NEG and NOT. */
3409 if (code
== NEG
|| code
== NOT
)
3417 /* Return 1 iff it is necessary to swap operands of commutative operation
3418 in order to canonicalize expression. */
3421 swap_commutative_operands_p (rtx x
, rtx y
)
3423 return (commutative_operand_precedence (x
)
3424 < commutative_operand_precedence (y
));
3427 /* Return 1 if X is an autoincrement side effect and the register is
3428 not the stack pointer. */
3430 auto_inc_p (const_rtx x
)
3432 switch (GET_CODE (x
))
3440 /* There are no REG_INC notes for SP. */
3441 if (XEXP (x
, 0) != stack_pointer_rtx
)
3449 /* Return nonzero if IN contains a piece of rtl that has the address LOC. */
3451 loc_mentioned_in_p (rtx
*loc
, const_rtx in
)
3460 code
= GET_CODE (in
);
3461 fmt
= GET_RTX_FORMAT (code
);
3462 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
3466 if (loc
== &XEXP (in
, i
) || loc_mentioned_in_p (loc
, XEXP (in
, i
)))
3469 else if (fmt
[i
] == 'E')
3470 for (j
= XVECLEN (in
, i
) - 1; j
>= 0; j
--)
3471 if (loc
== &XVECEXP (in
, i
, j
)
3472 || loc_mentioned_in_p (loc
, XVECEXP (in
, i
, j
)))
3478 /* Helper function for subreg_lsb. Given a subreg's OUTER_MODE, INNER_MODE,
3479 and SUBREG_BYTE, return the bit offset where the subreg begins
3480 (counting from the least significant bit of the operand). */
3483 subreg_lsb_1 (machine_mode outer_mode
,
3484 machine_mode inner_mode
,
3485 unsigned int subreg_byte
)
3487 unsigned int bitpos
;
3491 /* A paradoxical subreg begins at bit position 0. */
3492 if (GET_MODE_PRECISION (outer_mode
) > GET_MODE_PRECISION (inner_mode
))
3495 if (WORDS_BIG_ENDIAN
!= BYTES_BIG_ENDIAN
)
3496 /* If the subreg crosses a word boundary ensure that
3497 it also begins and ends on a word boundary. */
3498 gcc_assert (!((subreg_byte
% UNITS_PER_WORD
3499 + GET_MODE_SIZE (outer_mode
)) > UNITS_PER_WORD
3500 && (subreg_byte
% UNITS_PER_WORD
3501 || GET_MODE_SIZE (outer_mode
) % UNITS_PER_WORD
)));
3503 if (WORDS_BIG_ENDIAN
)
3504 word
= (GET_MODE_SIZE (inner_mode
)
3505 - (subreg_byte
+ GET_MODE_SIZE (outer_mode
))) / UNITS_PER_WORD
;
3507 word
= subreg_byte
/ UNITS_PER_WORD
;
3508 bitpos
= word
* BITS_PER_WORD
;
3510 if (BYTES_BIG_ENDIAN
)
3511 byte
= (GET_MODE_SIZE (inner_mode
)
3512 - (subreg_byte
+ GET_MODE_SIZE (outer_mode
))) % UNITS_PER_WORD
;
3514 byte
= subreg_byte
% UNITS_PER_WORD
;
3515 bitpos
+= byte
* BITS_PER_UNIT
;
3520 /* Given a subreg X, return the bit offset where the subreg begins
3521 (counting from the least significant bit of the reg). */
3524 subreg_lsb (const_rtx x
)
3526 return subreg_lsb_1 (GET_MODE (x
), GET_MODE (SUBREG_REG (x
)),
3530 /* Fill in information about a subreg of a hard register.
3531 xregno - A regno of an inner hard subreg_reg (or what will become one).
3532 xmode - The mode of xregno.
3533 offset - The byte offset.
3534 ymode - The mode of a top level SUBREG (or what may become one).
3535 info - Pointer to structure to fill in.
3537 Rather than considering one particular inner register (and thus one
3538 particular "outer" register) in isolation, this function really uses
3539 XREGNO as a model for a sequence of isomorphic hard registers. Thus the
3540 function does not check whether adding INFO->offset to XREGNO gives
3541 a valid hard register; even if INFO->offset + XREGNO is out of range,
3542 there might be another register of the same type that is in range.
3543 Likewise it doesn't check whether HARD_REGNO_MODE_OK accepts the new
3544 register, since that can depend on things like whether the final
3545 register number is even or odd. Callers that want to check whether
3546 this particular subreg can be replaced by a simple (reg ...) should
3547 use simplify_subreg_regno. */
3550 subreg_get_info (unsigned int xregno
, machine_mode xmode
,
3551 unsigned int offset
, machine_mode ymode
,
3552 struct subreg_info
*info
)
3554 int nregs_xmode
, nregs_ymode
;
3555 int mode_multiple
, nregs_multiple
;
3556 int offset_adj
, y_offset
, y_offset_adj
;
3557 int regsize_xmode
, regsize_ymode
;
3560 gcc_assert (xregno
< FIRST_PSEUDO_REGISTER
);
3564 /* If there are holes in a non-scalar mode in registers, we expect
3565 that it is made up of its units concatenated together. */
3566 if (HARD_REGNO_NREGS_HAS_PADDING (xregno
, xmode
))
3568 machine_mode xmode_unit
;
3570 nregs_xmode
= HARD_REGNO_NREGS_WITH_PADDING (xregno
, xmode
);
3571 xmode_unit
= GET_MODE_INNER (xmode
);
3572 gcc_assert (HARD_REGNO_NREGS_HAS_PADDING (xregno
, xmode_unit
));
3573 gcc_assert (nregs_xmode
3574 == (GET_MODE_NUNITS (xmode
)
3575 * HARD_REGNO_NREGS_WITH_PADDING (xregno
, xmode_unit
)));
3576 gcc_assert (hard_regno_nregs
[xregno
][xmode
]
3577 == (hard_regno_nregs
[xregno
][xmode_unit
]
3578 * GET_MODE_NUNITS (xmode
)));
3580 /* You can only ask for a SUBREG of a value with holes in the middle
3581 if you don't cross the holes. (Such a SUBREG should be done by
3582 picking a different register class, or doing it in memory if
3583 necessary.) An example of a value with holes is XCmode on 32-bit
3584 x86 with -m128bit-long-double; it's represented in 6 32-bit registers,
3585 3 for each part, but in memory it's two 128-bit parts.
3586 Padding is assumed to be at the end (not necessarily the 'high part')
3588 if ((offset
/ GET_MODE_SIZE (xmode_unit
) + 1
3589 < GET_MODE_NUNITS (xmode
))
3590 && (offset
/ GET_MODE_SIZE (xmode_unit
)
3591 != ((offset
+ GET_MODE_SIZE (ymode
) - 1)
3592 / GET_MODE_SIZE (xmode_unit
))))
3594 info
->representable_p
= false;
3599 nregs_xmode
= hard_regno_nregs
[xregno
][xmode
];
3601 nregs_ymode
= hard_regno_nregs
[xregno
][ymode
];
3603 /* Paradoxical subregs are otherwise valid. */
3606 && GET_MODE_PRECISION (ymode
) > GET_MODE_PRECISION (xmode
))
3608 info
->representable_p
= true;
3609 /* If this is a big endian paradoxical subreg, which uses more
3610 actual hard registers than the original register, we must
3611 return a negative offset so that we find the proper highpart
3613 if (GET_MODE_SIZE (ymode
) > UNITS_PER_WORD
3614 ? REG_WORDS_BIG_ENDIAN
: BYTES_BIG_ENDIAN
)
3615 info
->offset
= nregs_xmode
- nregs_ymode
;
3618 info
->nregs
= nregs_ymode
;
3622 /* If registers store different numbers of bits in the different
3623 modes, we cannot generally form this subreg. */
3624 if (!HARD_REGNO_NREGS_HAS_PADDING (xregno
, xmode
)
3625 && !HARD_REGNO_NREGS_HAS_PADDING (xregno
, ymode
)
3626 && (GET_MODE_SIZE (xmode
) % nregs_xmode
) == 0
3627 && (GET_MODE_SIZE (ymode
) % nregs_ymode
) == 0)
3629 regsize_xmode
= GET_MODE_SIZE (xmode
) / nregs_xmode
;
3630 regsize_ymode
= GET_MODE_SIZE (ymode
) / nregs_ymode
;
3631 if (!rknown
&& regsize_xmode
> regsize_ymode
&& nregs_ymode
> 1)
3633 info
->representable_p
= false;
3635 = (GET_MODE_SIZE (ymode
) + regsize_xmode
- 1) / regsize_xmode
;
3636 info
->offset
= offset
/ regsize_xmode
;
3639 if (!rknown
&& regsize_ymode
> regsize_xmode
&& nregs_xmode
> 1)
3641 info
->representable_p
= false;
3643 = (GET_MODE_SIZE (ymode
) + regsize_xmode
- 1) / regsize_xmode
;
3644 info
->offset
= offset
/ regsize_xmode
;
3647 /* Quick exit for the simple and common case of extracting whole
3648 subregisters from a multiregister value. */
3649 /* ??? It would be better to integrate this into the code below,
3650 if we can generalize the concept enough and figure out how
3651 odd-sized modes can coexist with the other weird cases we support. */
3653 && WORDS_BIG_ENDIAN
== REG_WORDS_BIG_ENDIAN
3654 && regsize_xmode
== regsize_ymode
3655 && (offset
% regsize_ymode
) == 0)
3657 info
->representable_p
= true;
3658 info
->nregs
= nregs_ymode
;
3659 info
->offset
= offset
/ regsize_ymode
;
3660 gcc_assert (info
->offset
+ info
->nregs
<= nregs_xmode
);
3665 /* Lowpart subregs are otherwise valid. */
3666 if (!rknown
&& offset
== subreg_lowpart_offset (ymode
, xmode
))
3668 info
->representable_p
= true;
3671 if (offset
== 0 || nregs_xmode
== nregs_ymode
)
3674 info
->nregs
= nregs_ymode
;
3679 /* This should always pass, otherwise we don't know how to verify
3680 the constraint. These conditions may be relaxed but
3681 subreg_regno_offset would need to be redesigned. */
3682 gcc_assert ((GET_MODE_SIZE (xmode
) % GET_MODE_SIZE (ymode
)) == 0);
3683 gcc_assert ((nregs_xmode
% nregs_ymode
) == 0);
3685 if (WORDS_BIG_ENDIAN
!= REG_WORDS_BIG_ENDIAN
3686 && GET_MODE_SIZE (xmode
) > UNITS_PER_WORD
)
3688 HOST_WIDE_INT xsize
= GET_MODE_SIZE (xmode
);
3689 HOST_WIDE_INT ysize
= GET_MODE_SIZE (ymode
);
3690 HOST_WIDE_INT off_low
= offset
& (ysize
- 1);
3691 HOST_WIDE_INT off_high
= offset
& ~(ysize
- 1);
3692 offset
= (xsize
- ysize
- off_high
) | off_low
;
3694 /* The XMODE value can be seen as a vector of NREGS_XMODE
3695 values. The subreg must represent a lowpart of given field.
3696 Compute what field it is. */
3697 offset_adj
= offset
;
3698 offset_adj
-= subreg_lowpart_offset (ymode
,
3699 mode_for_size (GET_MODE_BITSIZE (xmode
)
3703 /* Size of ymode must not be greater than the size of xmode. */
3704 mode_multiple
= GET_MODE_SIZE (xmode
) / GET_MODE_SIZE (ymode
);
3705 gcc_assert (mode_multiple
!= 0);
3707 y_offset
= offset
/ GET_MODE_SIZE (ymode
);
3708 y_offset_adj
= offset_adj
/ GET_MODE_SIZE (ymode
);
3709 nregs_multiple
= nregs_xmode
/ nregs_ymode
;
3711 gcc_assert ((offset_adj
% GET_MODE_SIZE (ymode
)) == 0);
3712 gcc_assert ((mode_multiple
% nregs_multiple
) == 0);
3716 info
->representable_p
= (!(y_offset_adj
% (mode_multiple
/ nregs_multiple
)));
3719 info
->offset
= (y_offset
/ (mode_multiple
/ nregs_multiple
)) * nregs_ymode
;
3720 info
->nregs
= nregs_ymode
;
3723 /* This function returns the regno offset of a subreg expression.
3724 xregno - A regno of an inner hard subreg_reg (or what will become one).
3725 xmode - The mode of xregno.
3726 offset - The byte offset.
3727 ymode - The mode of a top level SUBREG (or what may become one).
3728 RETURN - The regno offset which would be used. */
3730 subreg_regno_offset (unsigned int xregno
, machine_mode xmode
,
3731 unsigned int offset
, machine_mode ymode
)
3733 struct subreg_info info
;
3734 subreg_get_info (xregno
, xmode
, offset
, ymode
, &info
);
3738 /* This function returns true when the offset is representable via
3739 subreg_offset in the given regno.
3740 xregno - A regno of an inner hard subreg_reg (or what will become one).
3741 xmode - The mode of xregno.
3742 offset - The byte offset.
3743 ymode - The mode of a top level SUBREG (or what may become one).
3744 RETURN - Whether the offset is representable. */
3746 subreg_offset_representable_p (unsigned int xregno
, machine_mode xmode
,
3747 unsigned int offset
, machine_mode ymode
)
3749 struct subreg_info info
;
3750 subreg_get_info (xregno
, xmode
, offset
, ymode
, &info
);
3751 return info
.representable_p
;
3754 /* Return the number of a YMODE register to which
3756 (subreg:YMODE (reg:XMODE XREGNO) OFFSET)
3758 can be simplified. Return -1 if the subreg can't be simplified.
3760 XREGNO is a hard register number. */
3763 simplify_subreg_regno (unsigned int xregno
, machine_mode xmode
,
3764 unsigned int offset
, machine_mode ymode
)
3766 struct subreg_info info
;
3767 unsigned int yregno
;
3769 #ifdef CANNOT_CHANGE_MODE_CLASS
3770 /* Give the backend a chance to disallow the mode change. */
3771 if (GET_MODE_CLASS (xmode
) != MODE_COMPLEX_INT
3772 && GET_MODE_CLASS (xmode
) != MODE_COMPLEX_FLOAT
3773 && REG_CANNOT_CHANGE_MODE_P (xregno
, xmode
, ymode
)
3774 /* We can use mode change in LRA for some transformations. */
3775 && ! lra_in_progress
)
3779 /* We shouldn't simplify stack-related registers. */
3780 if ((!reload_completed
|| frame_pointer_needed
)
3781 && xregno
== FRAME_POINTER_REGNUM
)
3784 if (FRAME_POINTER_REGNUM
!= ARG_POINTER_REGNUM
3785 && xregno
== ARG_POINTER_REGNUM
)
3788 if (xregno
== STACK_POINTER_REGNUM
3789 /* We should convert hard stack register in LRA if it is
3791 && ! lra_in_progress
)
3794 /* Try to get the register offset. */
3795 subreg_get_info (xregno
, xmode
, offset
, ymode
, &info
);
3796 if (!info
.representable_p
)
3799 /* Make sure that the offsetted register value is in range. */
3800 yregno
= xregno
+ info
.offset
;
3801 if (!HARD_REGISTER_NUM_P (yregno
))
3804 /* See whether (reg:YMODE YREGNO) is valid.
3806 ??? We allow invalid registers if (reg:XMODE XREGNO) is also invalid.
3807 This is a kludge to work around how complex FP arguments are passed
3808 on IA-64 and should be fixed. See PR target/49226. */
3809 if (!HARD_REGNO_MODE_OK (yregno
, ymode
)
3810 && HARD_REGNO_MODE_OK (xregno
, xmode
))
3813 return (int) yregno
;
3816 /* Return the final regno that a subreg expression refers to. */
3818 subreg_regno (const_rtx x
)
3821 rtx subreg
= SUBREG_REG (x
);
3822 int regno
= REGNO (subreg
);
3824 ret
= regno
+ subreg_regno_offset (regno
,
3832 /* Return the number of registers that a subreg expression refers
3835 subreg_nregs (const_rtx x
)
3837 return subreg_nregs_with_regno (REGNO (SUBREG_REG (x
)), x
);
3840 /* Return the number of registers that a subreg REG with REGNO
3841 expression refers to. This is a copy of the rtlanal.c:subreg_nregs
3842 changed so that the regno can be passed in. */
3845 subreg_nregs_with_regno (unsigned int regno
, const_rtx x
)
3847 struct subreg_info info
;
3848 rtx subreg
= SUBREG_REG (x
);
3850 subreg_get_info (regno
, GET_MODE (subreg
), SUBREG_BYTE (x
), GET_MODE (x
),
3856 struct parms_set_data
3862 /* Helper function for noticing stores to parameter registers. */
3864 parms_set (rtx x
, const_rtx pat ATTRIBUTE_UNUSED
, void *data
)
3866 struct parms_set_data
*const d
= (struct parms_set_data
*) data
;
3867 if (REG_P (x
) && REGNO (x
) < FIRST_PSEUDO_REGISTER
3868 && TEST_HARD_REG_BIT (d
->regs
, REGNO (x
)))
3870 CLEAR_HARD_REG_BIT (d
->regs
, REGNO (x
));
3875 /* Look backward for first parameter to be loaded.
3876 Note that loads of all parameters will not necessarily be
3877 found if CSE has eliminated some of them (e.g., an argument
3878 to the outer function is passed down as a parameter).
3879 Do not skip BOUNDARY. */
3881 find_first_parameter_load (rtx_insn
*call_insn
, rtx_insn
*boundary
)
3883 struct parms_set_data parm
;
3885 rtx_insn
*before
, *first_set
;
3887 /* Since different machines initialize their parameter registers
3888 in different orders, assume nothing. Collect the set of all
3889 parameter registers. */
3890 CLEAR_HARD_REG_SET (parm
.regs
);
3892 for (p
= CALL_INSN_FUNCTION_USAGE (call_insn
); p
; p
= XEXP (p
, 1))
3893 if (GET_CODE (XEXP (p
, 0)) == USE
3894 && REG_P (XEXP (XEXP (p
, 0), 0)))
3896 gcc_assert (REGNO (XEXP (XEXP (p
, 0), 0)) < FIRST_PSEUDO_REGISTER
);
3898 /* We only care about registers which can hold function
3900 if (!FUNCTION_ARG_REGNO_P (REGNO (XEXP (XEXP (p
, 0), 0))))
3903 SET_HARD_REG_BIT (parm
.regs
, REGNO (XEXP (XEXP (p
, 0), 0)));
3907 first_set
= call_insn
;
3909 /* Search backward for the first set of a register in this set. */
3910 while (parm
.nregs
&& before
!= boundary
)
3912 before
= PREV_INSN (before
);
3914 /* It is possible that some loads got CSEed from one call to
3915 another. Stop in that case. */
3916 if (CALL_P (before
))
3919 /* Our caller needs either ensure that we will find all sets
3920 (in case code has not been optimized yet), or take care
3921 for possible labels in a way by setting boundary to preceding
3923 if (LABEL_P (before
))
3925 gcc_assert (before
== boundary
);
3929 if (INSN_P (before
))
3931 int nregs_old
= parm
.nregs
;
3932 note_stores (PATTERN (before
), parms_set
, &parm
);
3933 /* If we found something that did not set a parameter reg,
3934 we're done. Do not keep going, as that might result
3935 in hoisting an insn before the setting of a pseudo
3936 that is used by the hoisted insn. */
3937 if (nregs_old
!= parm
.nregs
)
3946 /* Return true if we should avoid inserting code between INSN and preceding
3947 call instruction. */
3950 keep_with_call_p (const rtx_insn
*insn
)
3954 if (INSN_P (insn
) && (set
= single_set (insn
)) != NULL
)
3956 if (REG_P (SET_DEST (set
))
3957 && REGNO (SET_DEST (set
)) < FIRST_PSEUDO_REGISTER
3958 && fixed_regs
[REGNO (SET_DEST (set
))]
3959 && general_operand (SET_SRC (set
), VOIDmode
))
3961 if (REG_P (SET_SRC (set
))
3962 && targetm
.calls
.function_value_regno_p (REGNO (SET_SRC (set
)))
3963 && REG_P (SET_DEST (set
))
3964 && REGNO (SET_DEST (set
)) >= FIRST_PSEUDO_REGISTER
)
3966 /* There may be a stack pop just after the call and before the store
3967 of the return register. Search for the actual store when deciding
3968 if we can break or not. */
3969 if (SET_DEST (set
) == stack_pointer_rtx
)
3971 /* This CONST_CAST is okay because next_nonnote_insn just
3972 returns its argument and we assign it to a const_rtx
3975 = next_nonnote_insn (const_cast<rtx_insn
*> (insn
));
3976 if (i2
&& keep_with_call_p (i2
))
3983 /* Return true if LABEL is a target of JUMP_INSN. This applies only
3984 to non-complex jumps. That is, direct unconditional, conditional,
3985 and tablejumps, but not computed jumps or returns. It also does
3986 not apply to the fallthru case of a conditional jump. */
3989 label_is_jump_target_p (const_rtx label
, const rtx_insn
*jump_insn
)
3991 rtx tmp
= JUMP_LABEL (jump_insn
);
3992 rtx_jump_table_data
*table
;
3997 if (tablejump_p (jump_insn
, NULL
, &table
))
3999 rtvec vec
= table
->get_labels ();
4000 int i
, veclen
= GET_NUM_ELEM (vec
);
4002 for (i
= 0; i
< veclen
; ++i
)
4003 if (XEXP (RTVEC_ELT (vec
, i
), 0) == label
)
4007 if (find_reg_note (jump_insn
, REG_LABEL_TARGET
, label
))
4014 /* Return an estimate of the cost of computing rtx X.
4015 One use is in cse, to decide which expression to keep in the hash table.
4016 Another is in rtl generation, to pick the cheapest way to multiply.
4017 Other uses like the latter are expected in the future.
4019 X appears as operand OPNO in an expression with code OUTER_CODE.
4020 SPEED specifies whether costs optimized for speed or size should
4024 rtx_cost (rtx x
, machine_mode mode
, enum rtx_code outer_code
,
4025 int opno
, bool speed
)
4036 if (GET_MODE (x
) != VOIDmode
)
4037 mode
= GET_MODE (x
);
4039 /* A size N times larger than UNITS_PER_WORD likely needs N times as
4040 many insns, taking N times as long. */
4041 factor
= GET_MODE_SIZE (mode
) / UNITS_PER_WORD
;
4045 /* Compute the default costs of certain things.
4046 Note that targetm.rtx_costs can override the defaults. */
4048 code
= GET_CODE (x
);
4052 /* Multiplication has time-complexity O(N*N), where N is the
4053 number of units (translated from digits) when using
4054 schoolbook long multiplication. */
4055 total
= factor
* factor
* COSTS_N_INSNS (5);
4061 /* Similarly, complexity for schoolbook long division. */
4062 total
= factor
* factor
* COSTS_N_INSNS (7);
4065 /* Used in combine.c as a marker. */
4069 /* A SET doesn't have a mode, so let's look at the SET_DEST to get
4070 the mode for the factor. */
4071 mode
= GET_MODE (SET_DEST (x
));
4072 factor
= GET_MODE_SIZE (mode
) / UNITS_PER_WORD
;
4077 total
= factor
* COSTS_N_INSNS (1);
4087 /* If we can't tie these modes, make this expensive. The larger
4088 the mode, the more expensive it is. */
4089 if (! MODES_TIEABLE_P (mode
, GET_MODE (SUBREG_REG (x
))))
4090 return COSTS_N_INSNS (2 + factor
);
4094 if (targetm
.rtx_costs (x
, mode
, outer_code
, opno
, &total
, speed
))
4099 /* Sum the costs of the sub-rtx's, plus cost of this operation,
4100 which is already in total. */
4102 fmt
= GET_RTX_FORMAT (code
);
4103 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
4105 total
+= rtx_cost (XEXP (x
, i
), mode
, code
, i
, speed
);
4106 else if (fmt
[i
] == 'E')
4107 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
4108 total
+= rtx_cost (XVECEXP (x
, i
, j
), mode
, code
, i
, speed
);
4113 /* Fill in the structure C with information about both speed and size rtx
4114 costs for X, which is operand OPNO in an expression with code OUTER. */
4117 get_full_rtx_cost (rtx x
, machine_mode mode
, enum rtx_code outer
, int opno
,
4118 struct full_rtx_costs
*c
)
4120 c
->speed
= rtx_cost (x
, mode
, outer
, opno
, true);
4121 c
->size
= rtx_cost (x
, mode
, outer
, opno
, false);
4125 /* Return cost of address expression X.
4126 Expect that X is properly formed address reference.
4128 SPEED parameter specify whether costs optimized for speed or size should
4132 address_cost (rtx x
, machine_mode mode
, addr_space_t as
, bool speed
)
4134 /* We may be asked for cost of various unusual addresses, such as operands
4135 of push instruction. It is not worthwhile to complicate writing
4136 of the target hook by such cases. */
4138 if (!memory_address_addr_space_p (mode
, x
, as
))
4141 return targetm
.address_cost (x
, mode
, as
, speed
);
4144 /* If the target doesn't override, compute the cost as with arithmetic. */
4147 default_address_cost (rtx x
, machine_mode
, addr_space_t
, bool speed
)
4149 return rtx_cost (x
, Pmode
, MEM
, 0, speed
);
4153 unsigned HOST_WIDE_INT
4154 nonzero_bits (const_rtx x
, machine_mode mode
)
4156 return cached_nonzero_bits (x
, mode
, NULL_RTX
, VOIDmode
, 0);
4160 num_sign_bit_copies (const_rtx x
, machine_mode mode
)
4162 return cached_num_sign_bit_copies (x
, mode
, NULL_RTX
, VOIDmode
, 0);
4165 /* The function cached_nonzero_bits is a wrapper around nonzero_bits1.
4166 It avoids exponential behavior in nonzero_bits1 when X has
4167 identical subexpressions on the first or the second level. */
4169 static unsigned HOST_WIDE_INT
4170 cached_nonzero_bits (const_rtx x
, machine_mode mode
, const_rtx known_x
,
4171 machine_mode known_mode
,
4172 unsigned HOST_WIDE_INT known_ret
)
4174 if (x
== known_x
&& mode
== known_mode
)
4177 /* Try to find identical subexpressions. If found call
4178 nonzero_bits1 on X with the subexpressions as KNOWN_X and the
4179 precomputed value for the subexpression as KNOWN_RET. */
4181 if (ARITHMETIC_P (x
))
4183 rtx x0
= XEXP (x
, 0);
4184 rtx x1
= XEXP (x
, 1);
4186 /* Check the first level. */
4188 return nonzero_bits1 (x
, mode
, x0
, mode
,
4189 cached_nonzero_bits (x0
, mode
, known_x
,
4190 known_mode
, known_ret
));
4192 /* Check the second level. */
4193 if (ARITHMETIC_P (x0
)
4194 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
4195 return nonzero_bits1 (x
, mode
, x1
, mode
,
4196 cached_nonzero_bits (x1
, mode
, known_x
,
4197 known_mode
, known_ret
));
4199 if (ARITHMETIC_P (x1
)
4200 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
4201 return nonzero_bits1 (x
, mode
, x0
, mode
,
4202 cached_nonzero_bits (x0
, mode
, known_x
,
4203 known_mode
, known_ret
));
4206 return nonzero_bits1 (x
, mode
, known_x
, known_mode
, known_ret
);
4209 /* We let num_sign_bit_copies recur into nonzero_bits as that is useful.
4210 We don't let nonzero_bits recur into num_sign_bit_copies, because that
4211 is less useful. We can't allow both, because that results in exponential
4212 run time recursion. There is a nullstone testcase that triggered
4213 this. This macro avoids accidental uses of num_sign_bit_copies. */
4214 #define cached_num_sign_bit_copies sorry_i_am_preventing_exponential_behavior
4216 /* Given an expression, X, compute which bits in X can be nonzero.
4217 We don't care about bits outside of those defined in MODE.
4219 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
4220 an arithmetic operation, we can do better. */
4222 static unsigned HOST_WIDE_INT
4223 nonzero_bits1 (const_rtx x
, machine_mode mode
, const_rtx known_x
,
4224 machine_mode known_mode
,
4225 unsigned HOST_WIDE_INT known_ret
)
4227 unsigned HOST_WIDE_INT nonzero
= GET_MODE_MASK (mode
);
4228 unsigned HOST_WIDE_INT inner_nz
;
4230 machine_mode inner_mode
;
4231 unsigned int mode_width
= GET_MODE_PRECISION (mode
);
4233 /* For floating-point and vector values, assume all bits are needed. */
4234 if (FLOAT_MODE_P (GET_MODE (x
)) || FLOAT_MODE_P (mode
)
4235 || VECTOR_MODE_P (GET_MODE (x
)) || VECTOR_MODE_P (mode
))
4238 /* If X is wider than MODE, use its mode instead. */
4239 if (GET_MODE_PRECISION (GET_MODE (x
)) > mode_width
)
4241 mode
= GET_MODE (x
);
4242 nonzero
= GET_MODE_MASK (mode
);
4243 mode_width
= GET_MODE_PRECISION (mode
);
4246 if (mode_width
> HOST_BITS_PER_WIDE_INT
)
4247 /* Our only callers in this case look for single bit values. So
4248 just return the mode mask. Those tests will then be false. */
4251 /* If MODE is wider than X, but both are a single word for both the host
4252 and target machines, we can compute this from which bits of the
4253 object might be nonzero in its own mode, taking into account the fact
4254 that on many CISC machines, accessing an object in a wider mode
4255 causes the high-order bits to become undefined. So they are
4256 not known to be zero. */
4258 if (!WORD_REGISTER_OPERATIONS
4259 && GET_MODE (x
) != VOIDmode
4260 && GET_MODE (x
) != mode
4261 && GET_MODE_PRECISION (GET_MODE (x
)) <= BITS_PER_WORD
4262 && GET_MODE_PRECISION (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
4263 && GET_MODE_PRECISION (mode
) > GET_MODE_PRECISION (GET_MODE (x
)))
4265 nonzero
&= cached_nonzero_bits (x
, GET_MODE (x
),
4266 known_x
, known_mode
, known_ret
);
4267 nonzero
|= GET_MODE_MASK (mode
) & ~GET_MODE_MASK (GET_MODE (x
));
4271 code
= GET_CODE (x
);
4275 #if defined(POINTERS_EXTEND_UNSIGNED)
4276 /* If pointers extend unsigned and this is a pointer in Pmode, say that
4277 all the bits above ptr_mode are known to be zero. */
4278 /* As we do not know which address space the pointer is referring to,
4279 we can do this only if the target does not support different pointer
4280 or address modes depending on the address space. */
4281 if (target_default_pointer_address_modes_p ()
4282 && POINTERS_EXTEND_UNSIGNED
&& GET_MODE (x
) == Pmode
4284 && !targetm
.have_ptr_extend ())
4285 nonzero
&= GET_MODE_MASK (ptr_mode
);
4288 /* Include declared information about alignment of pointers. */
4289 /* ??? We don't properly preserve REG_POINTER changes across
4290 pointer-to-integer casts, so we can't trust it except for
4291 things that we know must be pointers. See execute/960116-1.c. */
4292 if ((x
== stack_pointer_rtx
4293 || x
== frame_pointer_rtx
4294 || x
== arg_pointer_rtx
)
4295 && REGNO_POINTER_ALIGN (REGNO (x
)))
4297 unsigned HOST_WIDE_INT alignment
4298 = REGNO_POINTER_ALIGN (REGNO (x
)) / BITS_PER_UNIT
;
4300 #ifdef PUSH_ROUNDING
4301 /* If PUSH_ROUNDING is defined, it is possible for the
4302 stack to be momentarily aligned only to that amount,
4303 so we pick the least alignment. */
4304 if (x
== stack_pointer_rtx
&& PUSH_ARGS
)
4305 alignment
= MIN ((unsigned HOST_WIDE_INT
) PUSH_ROUNDING (1),
4309 nonzero
&= ~(alignment
- 1);
4313 unsigned HOST_WIDE_INT nonzero_for_hook
= nonzero
;
4314 rtx new_rtx
= rtl_hooks
.reg_nonzero_bits (x
, mode
, known_x
,
4315 known_mode
, known_ret
,
4319 nonzero_for_hook
&= cached_nonzero_bits (new_rtx
, mode
, known_x
,
4320 known_mode
, known_ret
);
4322 return nonzero_for_hook
;
4326 /* If X is negative in MODE, sign-extend the value. */
4327 if (SHORT_IMMEDIATES_SIGN_EXTEND
&& INTVAL (x
) > 0
4328 && mode_width
< BITS_PER_WORD
4329 && (UINTVAL (x
) & ((unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)))
4331 return UINTVAL (x
) | (HOST_WIDE_INT_M1U
<< mode_width
);
4336 #ifdef LOAD_EXTEND_OP
4337 /* In many, if not most, RISC machines, reading a byte from memory
4338 zeros the rest of the register. Noticing that fact saves a lot
4339 of extra zero-extends. */
4340 if (LOAD_EXTEND_OP (GET_MODE (x
)) == ZERO_EXTEND
)
4341 nonzero
&= GET_MODE_MASK (GET_MODE (x
));
4346 case UNEQ
: case LTGT
:
4347 case GT
: case GTU
: case UNGT
:
4348 case LT
: case LTU
: case UNLT
:
4349 case GE
: case GEU
: case UNGE
:
4350 case LE
: case LEU
: case UNLE
:
4351 case UNORDERED
: case ORDERED
:
4352 /* If this produces an integer result, we know which bits are set.
4353 Code here used to clear bits outside the mode of X, but that is
4355 /* Mind that MODE is the mode the caller wants to look at this
4356 operation in, and not the actual operation mode. We can wind
4357 up with (subreg:DI (gt:V4HI x y)), and we don't have anything
4358 that describes the results of a vector compare. */
4359 if (GET_MODE_CLASS (GET_MODE (x
)) == MODE_INT
4360 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
4361 nonzero
= STORE_FLAG_VALUE
;
4366 /* Disabled to avoid exponential mutual recursion between nonzero_bits
4367 and num_sign_bit_copies. */
4368 if (num_sign_bit_copies (XEXP (x
, 0), GET_MODE (x
))
4369 == GET_MODE_PRECISION (GET_MODE (x
)))
4373 if (GET_MODE_PRECISION (GET_MODE (x
)) < mode_width
)
4374 nonzero
|= (GET_MODE_MASK (mode
) & ~GET_MODE_MASK (GET_MODE (x
)));
4379 /* Disabled to avoid exponential mutual recursion between nonzero_bits
4380 and num_sign_bit_copies. */
4381 if (num_sign_bit_copies (XEXP (x
, 0), GET_MODE (x
))
4382 == GET_MODE_PRECISION (GET_MODE (x
)))
4388 nonzero
&= (cached_nonzero_bits (XEXP (x
, 0), mode
,
4389 known_x
, known_mode
, known_ret
)
4390 & GET_MODE_MASK (mode
));
4394 nonzero
&= cached_nonzero_bits (XEXP (x
, 0), mode
,
4395 known_x
, known_mode
, known_ret
);
4396 if (GET_MODE (XEXP (x
, 0)) != VOIDmode
)
4397 nonzero
&= GET_MODE_MASK (GET_MODE (XEXP (x
, 0)));
4401 /* If the sign bit is known clear, this is the same as ZERO_EXTEND.
4402 Otherwise, show all the bits in the outer mode but not the inner
4404 inner_nz
= cached_nonzero_bits (XEXP (x
, 0), mode
,
4405 known_x
, known_mode
, known_ret
);
4406 if (GET_MODE (XEXP (x
, 0)) != VOIDmode
)
4408 inner_nz
&= GET_MODE_MASK (GET_MODE (XEXP (x
, 0)));
4409 if (val_signbit_known_set_p (GET_MODE (XEXP (x
, 0)), inner_nz
))
4410 inner_nz
|= (GET_MODE_MASK (mode
)
4411 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0))));
4414 nonzero
&= inner_nz
;
4418 nonzero
&= cached_nonzero_bits (XEXP (x
, 0), mode
,
4419 known_x
, known_mode
, known_ret
)
4420 & cached_nonzero_bits (XEXP (x
, 1), mode
,
4421 known_x
, known_mode
, known_ret
);
4425 case UMIN
: case UMAX
: case SMIN
: case SMAX
:
4427 unsigned HOST_WIDE_INT nonzero0
4428 = cached_nonzero_bits (XEXP (x
, 0), mode
,
4429 known_x
, known_mode
, known_ret
);
4431 /* Don't call nonzero_bits for the second time if it cannot change
4433 if ((nonzero
& nonzero0
) != nonzero
)
4435 | cached_nonzero_bits (XEXP (x
, 1), mode
,
4436 known_x
, known_mode
, known_ret
);
4440 case PLUS
: case MINUS
:
4442 case DIV
: case UDIV
:
4443 case MOD
: case UMOD
:
4444 /* We can apply the rules of arithmetic to compute the number of
4445 high- and low-order zero bits of these operations. We start by
4446 computing the width (position of the highest-order nonzero bit)
4447 and the number of low-order zero bits for each value. */
4449 unsigned HOST_WIDE_INT nz0
4450 = cached_nonzero_bits (XEXP (x
, 0), mode
,
4451 known_x
, known_mode
, known_ret
);
4452 unsigned HOST_WIDE_INT nz1
4453 = cached_nonzero_bits (XEXP (x
, 1), mode
,
4454 known_x
, known_mode
, known_ret
);
4455 int sign_index
= GET_MODE_PRECISION (GET_MODE (x
)) - 1;
4456 int width0
= floor_log2 (nz0
) + 1;
4457 int width1
= floor_log2 (nz1
) + 1;
4458 int low0
= floor_log2 (nz0
& -nz0
);
4459 int low1
= floor_log2 (nz1
& -nz1
);
4460 unsigned HOST_WIDE_INT op0_maybe_minusp
4461 = nz0
& ((unsigned HOST_WIDE_INT
) 1 << sign_index
);
4462 unsigned HOST_WIDE_INT op1_maybe_minusp
4463 = nz1
& ((unsigned HOST_WIDE_INT
) 1 << sign_index
);
4464 unsigned int result_width
= mode_width
;
4470 result_width
= MAX (width0
, width1
) + 1;
4471 result_low
= MIN (low0
, low1
);
4474 result_low
= MIN (low0
, low1
);
4477 result_width
= width0
+ width1
;
4478 result_low
= low0
+ low1
;
4483 if (!op0_maybe_minusp
&& !op1_maybe_minusp
)
4484 result_width
= width0
;
4489 result_width
= width0
;
4494 if (!op0_maybe_minusp
&& !op1_maybe_minusp
)
4495 result_width
= MIN (width0
, width1
);
4496 result_low
= MIN (low0
, low1
);
4501 result_width
= MIN (width0
, width1
);
4502 result_low
= MIN (low0
, low1
);
4508 if (result_width
< mode_width
)
4509 nonzero
&= ((unsigned HOST_WIDE_INT
) 1 << result_width
) - 1;
4512 nonzero
&= ~(((unsigned HOST_WIDE_INT
) 1 << result_low
) - 1);
4517 if (CONST_INT_P (XEXP (x
, 1))
4518 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
)
4519 nonzero
&= ((unsigned HOST_WIDE_INT
) 1 << INTVAL (XEXP (x
, 1))) - 1;
4523 /* If this is a SUBREG formed for a promoted variable that has
4524 been zero-extended, we know that at least the high-order bits
4525 are zero, though others might be too. */
4527 if (SUBREG_PROMOTED_VAR_P (x
) && SUBREG_PROMOTED_UNSIGNED_P (x
))
4528 nonzero
= GET_MODE_MASK (GET_MODE (x
))
4529 & cached_nonzero_bits (SUBREG_REG (x
), GET_MODE (x
),
4530 known_x
, known_mode
, known_ret
);
4532 inner_mode
= GET_MODE (SUBREG_REG (x
));
4533 /* If the inner mode is a single word for both the host and target
4534 machines, we can compute this from which bits of the inner
4535 object might be nonzero. */
4536 if (GET_MODE_PRECISION (inner_mode
) <= BITS_PER_WORD
4537 && (GET_MODE_PRECISION (inner_mode
) <= HOST_BITS_PER_WIDE_INT
))
4539 nonzero
&= cached_nonzero_bits (SUBREG_REG (x
), mode
,
4540 known_x
, known_mode
, known_ret
);
4542 #if WORD_REGISTER_OPERATIONS && defined (LOAD_EXTEND_OP)
4543 /* If this is a typical RISC machine, we only have to worry
4544 about the way loads are extended. */
4545 if ((LOAD_EXTEND_OP (inner_mode
) == SIGN_EXTEND
4546 ? val_signbit_known_set_p (inner_mode
, nonzero
)
4547 : LOAD_EXTEND_OP (inner_mode
) != ZERO_EXTEND
)
4548 || !MEM_P (SUBREG_REG (x
)))
4551 /* On many CISC machines, accessing an object in a wider mode
4552 causes the high-order bits to become undefined. So they are
4553 not known to be zero. */
4554 if (GET_MODE_PRECISION (GET_MODE (x
))
4555 > GET_MODE_PRECISION (inner_mode
))
4556 nonzero
|= (GET_MODE_MASK (GET_MODE (x
))
4557 & ~GET_MODE_MASK (inner_mode
));
4566 /* The nonzero bits are in two classes: any bits within MODE
4567 that aren't in GET_MODE (x) are always significant. The rest of the
4568 nonzero bits are those that are significant in the operand of
4569 the shift when shifted the appropriate number of bits. This
4570 shows that high-order bits are cleared by the right shift and
4571 low-order bits by left shifts. */
4572 if (CONST_INT_P (XEXP (x
, 1))
4573 && INTVAL (XEXP (x
, 1)) >= 0
4574 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
4575 && INTVAL (XEXP (x
, 1)) < GET_MODE_PRECISION (GET_MODE (x
)))
4577 machine_mode inner_mode
= GET_MODE (x
);
4578 unsigned int width
= GET_MODE_PRECISION (inner_mode
);
4579 int count
= INTVAL (XEXP (x
, 1));
4580 unsigned HOST_WIDE_INT mode_mask
= GET_MODE_MASK (inner_mode
);
4581 unsigned HOST_WIDE_INT op_nonzero
4582 = cached_nonzero_bits (XEXP (x
, 0), mode
,
4583 known_x
, known_mode
, known_ret
);
4584 unsigned HOST_WIDE_INT inner
= op_nonzero
& mode_mask
;
4585 unsigned HOST_WIDE_INT outer
= 0;
4587 if (mode_width
> width
)
4588 outer
= (op_nonzero
& nonzero
& ~mode_mask
);
4590 if (code
== LSHIFTRT
)
4592 else if (code
== ASHIFTRT
)
4596 /* If the sign bit may have been nonzero before the shift, we
4597 need to mark all the places it could have been copied to
4598 by the shift as possibly nonzero. */
4599 if (inner
& ((unsigned HOST_WIDE_INT
) 1 << (width
- 1 - count
)))
4600 inner
|= (((unsigned HOST_WIDE_INT
) 1 << count
) - 1)
4603 else if (code
== ASHIFT
)
4606 inner
= ((inner
<< (count
% width
)
4607 | (inner
>> (width
- (count
% width
)))) & mode_mask
);
4609 nonzero
&= (outer
| inner
);
4615 /* This is at most the number of bits in the mode. */
4616 nonzero
= ((unsigned HOST_WIDE_INT
) 2 << (floor_log2 (mode_width
))) - 1;
4620 /* If CLZ has a known value at zero, then the nonzero bits are
4621 that value, plus the number of bits in the mode minus one. */
4622 if (CLZ_DEFINED_VALUE_AT_ZERO (mode
, nonzero
))
4624 |= ((unsigned HOST_WIDE_INT
) 1 << (floor_log2 (mode_width
))) - 1;
4630 /* If CTZ has a known value at zero, then the nonzero bits are
4631 that value, plus the number of bits in the mode minus one. */
4632 if (CTZ_DEFINED_VALUE_AT_ZERO (mode
, nonzero
))
4634 |= ((unsigned HOST_WIDE_INT
) 1 << (floor_log2 (mode_width
))) - 1;
4640 /* This is at most the number of bits in the mode minus 1. */
4641 nonzero
= ((unsigned HOST_WIDE_INT
) 1 << (floor_log2 (mode_width
))) - 1;
4650 unsigned HOST_WIDE_INT nonzero_true
4651 = cached_nonzero_bits (XEXP (x
, 1), mode
,
4652 known_x
, known_mode
, known_ret
);
4654 /* Don't call nonzero_bits for the second time if it cannot change
4656 if ((nonzero
& nonzero_true
) != nonzero
)
4657 nonzero
&= nonzero_true
4658 | cached_nonzero_bits (XEXP (x
, 2), mode
,
4659 known_x
, known_mode
, known_ret
);
4670 /* See the macro definition above. */
4671 #undef cached_num_sign_bit_copies
4674 /* The function cached_num_sign_bit_copies is a wrapper around
4675 num_sign_bit_copies1. It avoids exponential behavior in
4676 num_sign_bit_copies1 when X has identical subexpressions on the
4677 first or the second level. */
4680 cached_num_sign_bit_copies (const_rtx x
, machine_mode mode
, const_rtx known_x
,
4681 machine_mode known_mode
,
4682 unsigned int known_ret
)
4684 if (x
== known_x
&& mode
== known_mode
)
4687 /* Try to find identical subexpressions. If found call
4688 num_sign_bit_copies1 on X with the subexpressions as KNOWN_X and
4689 the precomputed value for the subexpression as KNOWN_RET. */
4691 if (ARITHMETIC_P (x
))
4693 rtx x0
= XEXP (x
, 0);
4694 rtx x1
= XEXP (x
, 1);
4696 /* Check the first level. */
4699 num_sign_bit_copies1 (x
, mode
, x0
, mode
,
4700 cached_num_sign_bit_copies (x0
, mode
, known_x
,
4704 /* Check the second level. */
4705 if (ARITHMETIC_P (x0
)
4706 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
4708 num_sign_bit_copies1 (x
, mode
, x1
, mode
,
4709 cached_num_sign_bit_copies (x1
, mode
, known_x
,
4713 if (ARITHMETIC_P (x1
)
4714 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
4716 num_sign_bit_copies1 (x
, mode
, x0
, mode
,
4717 cached_num_sign_bit_copies (x0
, mode
, known_x
,
4722 return num_sign_bit_copies1 (x
, mode
, known_x
, known_mode
, known_ret
);
4725 /* Return the number of bits at the high-order end of X that are known to
4726 be equal to the sign bit. X will be used in mode MODE; if MODE is
4727 VOIDmode, X will be used in its own mode. The returned value will always
4728 be between 1 and the number of bits in MODE. */
4731 num_sign_bit_copies1 (const_rtx x
, machine_mode mode
, const_rtx known_x
,
4732 machine_mode known_mode
,
4733 unsigned int known_ret
)
4735 enum rtx_code code
= GET_CODE (x
);
4736 unsigned int bitwidth
= GET_MODE_PRECISION (mode
);
4737 int num0
, num1
, result
;
4738 unsigned HOST_WIDE_INT nonzero
;
4740 /* If we weren't given a mode, use the mode of X. If the mode is still
4741 VOIDmode, we don't know anything. Likewise if one of the modes is
4744 if (mode
== VOIDmode
)
4745 mode
= GET_MODE (x
);
4747 if (mode
== VOIDmode
|| FLOAT_MODE_P (mode
) || FLOAT_MODE_P (GET_MODE (x
))
4748 || VECTOR_MODE_P (GET_MODE (x
)) || VECTOR_MODE_P (mode
))
4751 /* For a smaller object, just ignore the high bits. */
4752 if (bitwidth
< GET_MODE_PRECISION (GET_MODE (x
)))
4754 num0
= cached_num_sign_bit_copies (x
, GET_MODE (x
),
4755 known_x
, known_mode
, known_ret
);
4757 num0
- (int) (GET_MODE_PRECISION (GET_MODE (x
)) - bitwidth
));
4760 if (GET_MODE (x
) != VOIDmode
&& bitwidth
> GET_MODE_PRECISION (GET_MODE (x
)))
4762 /* If this machine does not do all register operations on the entire
4763 register and MODE is wider than the mode of X, we can say nothing
4764 at all about the high-order bits. */
4765 if (!WORD_REGISTER_OPERATIONS
)
4768 /* Likewise on machines that do, if the mode of the object is smaller
4769 than a word and loads of that size don't sign extend, we can say
4770 nothing about the high order bits. */
4771 if (GET_MODE_PRECISION (GET_MODE (x
)) < BITS_PER_WORD
4772 #ifdef LOAD_EXTEND_OP
4773 && LOAD_EXTEND_OP (GET_MODE (x
)) != SIGN_EXTEND
4783 #if defined(POINTERS_EXTEND_UNSIGNED)
4784 /* If pointers extend signed and this is a pointer in Pmode, say that
4785 all the bits above ptr_mode are known to be sign bit copies. */
4786 /* As we do not know which address space the pointer is referring to,
4787 we can do this only if the target does not support different pointer
4788 or address modes depending on the address space. */
4789 if (target_default_pointer_address_modes_p ()
4790 && ! POINTERS_EXTEND_UNSIGNED
&& GET_MODE (x
) == Pmode
4791 && mode
== Pmode
&& REG_POINTER (x
)
4792 && !targetm
.have_ptr_extend ())
4793 return GET_MODE_PRECISION (Pmode
) - GET_MODE_PRECISION (ptr_mode
) + 1;
4797 unsigned int copies_for_hook
= 1, copies
= 1;
4798 rtx new_rtx
= rtl_hooks
.reg_num_sign_bit_copies (x
, mode
, known_x
,
4799 known_mode
, known_ret
,
4803 copies
= cached_num_sign_bit_copies (new_rtx
, mode
, known_x
,
4804 known_mode
, known_ret
);
4806 if (copies
> 1 || copies_for_hook
> 1)
4807 return MAX (copies
, copies_for_hook
);
4809 /* Else, use nonzero_bits to guess num_sign_bit_copies (see below). */
4814 #ifdef LOAD_EXTEND_OP
4815 /* Some RISC machines sign-extend all loads of smaller than a word. */
4816 if (LOAD_EXTEND_OP (GET_MODE (x
)) == SIGN_EXTEND
)
4817 return MAX (1, ((int) bitwidth
4818 - (int) GET_MODE_PRECISION (GET_MODE (x
)) + 1));
4823 /* If the constant is negative, take its 1's complement and remask.
4824 Then see how many zero bits we have. */
4825 nonzero
= UINTVAL (x
) & GET_MODE_MASK (mode
);
4826 if (bitwidth
<= HOST_BITS_PER_WIDE_INT
4827 && (nonzero
& ((unsigned HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0)
4828 nonzero
= (~nonzero
) & GET_MODE_MASK (mode
);
4830 return (nonzero
== 0 ? bitwidth
: bitwidth
- floor_log2 (nonzero
) - 1);
4833 /* If this is a SUBREG for a promoted object that is sign-extended
4834 and we are looking at it in a wider mode, we know that at least the
4835 high-order bits are known to be sign bit copies. */
4837 if (SUBREG_PROMOTED_VAR_P (x
) && SUBREG_PROMOTED_SIGNED_P (x
))
4839 num0
= cached_num_sign_bit_copies (SUBREG_REG (x
), mode
,
4840 known_x
, known_mode
, known_ret
);
4841 return MAX ((int) bitwidth
4842 - (int) GET_MODE_PRECISION (GET_MODE (x
)) + 1,
4846 /* For a smaller object, just ignore the high bits. */
4847 if (bitwidth
<= GET_MODE_PRECISION (GET_MODE (SUBREG_REG (x
))))
4849 num0
= cached_num_sign_bit_copies (SUBREG_REG (x
), VOIDmode
,
4850 known_x
, known_mode
, known_ret
);
4851 return MAX (1, (num0
4852 - (int) (GET_MODE_PRECISION (GET_MODE (SUBREG_REG (x
)))
4856 #ifdef LOAD_EXTEND_OP
4857 /* For paradoxical SUBREGs on machines where all register operations
4858 affect the entire register, just look inside. Note that we are
4859 passing MODE to the recursive call, so the number of sign bit copies
4860 will remain relative to that mode, not the inner mode. */
4862 /* This works only if loads sign extend. Otherwise, if we get a
4863 reload for the inner part, it may be loaded from the stack, and
4864 then we lose all sign bit copies that existed before the store
4867 if (WORD_REGISTER_OPERATIONS
4868 && paradoxical_subreg_p (x
)
4869 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x
))) == SIGN_EXTEND
4870 && MEM_P (SUBREG_REG (x
)))
4871 return cached_num_sign_bit_copies (SUBREG_REG (x
), mode
,
4872 known_x
, known_mode
, known_ret
);
4877 if (CONST_INT_P (XEXP (x
, 1)))
4878 return MAX (1, (int) bitwidth
- INTVAL (XEXP (x
, 1)));
4882 return (bitwidth
- GET_MODE_PRECISION (GET_MODE (XEXP (x
, 0)))
4883 + cached_num_sign_bit_copies (XEXP (x
, 0), VOIDmode
,
4884 known_x
, known_mode
, known_ret
));
4887 /* For a smaller object, just ignore the high bits. */
4888 num0
= cached_num_sign_bit_copies (XEXP (x
, 0), VOIDmode
,
4889 known_x
, known_mode
, known_ret
);
4890 return MAX (1, (num0
- (int) (GET_MODE_PRECISION (GET_MODE (XEXP (x
, 0)))
4894 return cached_num_sign_bit_copies (XEXP (x
, 0), mode
,
4895 known_x
, known_mode
, known_ret
);
4897 case ROTATE
: case ROTATERT
:
4898 /* If we are rotating left by a number of bits less than the number
4899 of sign bit copies, we can just subtract that amount from the
4901 if (CONST_INT_P (XEXP (x
, 1))
4902 && INTVAL (XEXP (x
, 1)) >= 0
4903 && INTVAL (XEXP (x
, 1)) < (int) bitwidth
)
4905 num0
= cached_num_sign_bit_copies (XEXP (x
, 0), mode
,
4906 known_x
, known_mode
, known_ret
);
4907 return MAX (1, num0
- (code
== ROTATE
? INTVAL (XEXP (x
, 1))
4908 : (int) bitwidth
- INTVAL (XEXP (x
, 1))));
4913 /* In general, this subtracts one sign bit copy. But if the value
4914 is known to be positive, the number of sign bit copies is the
4915 same as that of the input. Finally, if the input has just one bit
4916 that might be nonzero, all the bits are copies of the sign bit. */
4917 num0
= cached_num_sign_bit_copies (XEXP (x
, 0), mode
,
4918 known_x
, known_mode
, known_ret
);
4919 if (bitwidth
> HOST_BITS_PER_WIDE_INT
)
4920 return num0
> 1 ? num0
- 1 : 1;
4922 nonzero
= nonzero_bits (XEXP (x
, 0), mode
);
4927 && (((unsigned HOST_WIDE_INT
) 1 << (bitwidth
- 1)) & nonzero
))
4932 case IOR
: case AND
: case XOR
:
4933 case SMIN
: case SMAX
: case UMIN
: case UMAX
:
4934 /* Logical operations will preserve the number of sign-bit copies.
4935 MIN and MAX operations always return one of the operands. */
4936 num0
= cached_num_sign_bit_copies (XEXP (x
, 0), mode
,
4937 known_x
, known_mode
, known_ret
);
4938 num1
= cached_num_sign_bit_copies (XEXP (x
, 1), mode
,
4939 known_x
, known_mode
, known_ret
);
4941 /* If num1 is clearing some of the top bits then regardless of
4942 the other term, we are guaranteed to have at least that many
4943 high-order zero bits. */
4946 && bitwidth
<= HOST_BITS_PER_WIDE_INT
4947 && CONST_INT_P (XEXP (x
, 1))
4948 && (UINTVAL (XEXP (x
, 1))
4949 & ((unsigned HOST_WIDE_INT
) 1 << (bitwidth
- 1))) == 0)
4952 /* Similarly for IOR when setting high-order bits. */
4955 && bitwidth
<= HOST_BITS_PER_WIDE_INT
4956 && CONST_INT_P (XEXP (x
, 1))
4957 && (UINTVAL (XEXP (x
, 1))
4958 & ((unsigned HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0)
4961 return MIN (num0
, num1
);
4963 case PLUS
: case MINUS
:
4964 /* For addition and subtraction, we can have a 1-bit carry. However,
4965 if we are subtracting 1 from a positive number, there will not
4966 be such a carry. Furthermore, if the positive number is known to
4967 be 0 or 1, we know the result is either -1 or 0. */
4969 if (code
== PLUS
&& XEXP (x
, 1) == constm1_rtx
4970 && bitwidth
<= HOST_BITS_PER_WIDE_INT
)
4972 nonzero
= nonzero_bits (XEXP (x
, 0), mode
);
4973 if ((((unsigned HOST_WIDE_INT
) 1 << (bitwidth
- 1)) & nonzero
) == 0)
4974 return (nonzero
== 1 || nonzero
== 0 ? bitwidth
4975 : bitwidth
- floor_log2 (nonzero
) - 1);
4978 num0
= cached_num_sign_bit_copies (XEXP (x
, 0), mode
,
4979 known_x
, known_mode
, known_ret
);
4980 num1
= cached_num_sign_bit_copies (XEXP (x
, 1), mode
,
4981 known_x
, known_mode
, known_ret
);
4982 result
= MAX (1, MIN (num0
, num1
) - 1);
4987 /* The number of bits of the product is the sum of the number of
4988 bits of both terms. However, unless one of the terms if known
4989 to be positive, we must allow for an additional bit since negating
4990 a negative number can remove one sign bit copy. */
4992 num0
= cached_num_sign_bit_copies (XEXP (x
, 0), mode
,
4993 known_x
, known_mode
, known_ret
);
4994 num1
= cached_num_sign_bit_copies (XEXP (x
, 1), mode
,
4995 known_x
, known_mode
, known_ret
);
4997 result
= bitwidth
- (bitwidth
- num0
) - (bitwidth
- num1
);
4999 && (bitwidth
> HOST_BITS_PER_WIDE_INT
5000 || (((nonzero_bits (XEXP (x
, 0), mode
)
5001 & ((unsigned HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0)
5002 && ((nonzero_bits (XEXP (x
, 1), mode
)
5003 & ((unsigned HOST_WIDE_INT
) 1 << (bitwidth
- 1)))
5007 return MAX (1, result
);
5010 /* The result must be <= the first operand. If the first operand
5011 has the high bit set, we know nothing about the number of sign
5013 if (bitwidth
> HOST_BITS_PER_WIDE_INT
)
5015 else if ((nonzero_bits (XEXP (x
, 0), mode
)
5016 & ((unsigned HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0)
5019 return cached_num_sign_bit_copies (XEXP (x
, 0), mode
,
5020 known_x
, known_mode
, known_ret
);
5023 /* The result must be <= the second operand. If the second operand
5024 has (or just might have) the high bit set, we know nothing about
5025 the number of sign bit copies. */
5026 if (bitwidth
> HOST_BITS_PER_WIDE_INT
)
5028 else if ((nonzero_bits (XEXP (x
, 1), mode
)
5029 & ((unsigned HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0)
5032 return cached_num_sign_bit_copies (XEXP (x
, 1), mode
,
5033 known_x
, known_mode
, known_ret
);
5036 /* Similar to unsigned division, except that we have to worry about
5037 the case where the divisor is negative, in which case we have
5039 result
= cached_num_sign_bit_copies (XEXP (x
, 0), mode
,
5040 known_x
, known_mode
, known_ret
);
5042 && (bitwidth
> HOST_BITS_PER_WIDE_INT
5043 || (nonzero_bits (XEXP (x
, 1), mode
)
5044 & ((unsigned HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0))
5050 result
= cached_num_sign_bit_copies (XEXP (x
, 1), mode
,
5051 known_x
, known_mode
, known_ret
);
5053 && (bitwidth
> HOST_BITS_PER_WIDE_INT
5054 || (nonzero_bits (XEXP (x
, 1), mode
)
5055 & ((unsigned HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0))
5061 /* Shifts by a constant add to the number of bits equal to the
5063 num0
= cached_num_sign_bit_copies (XEXP (x
, 0), mode
,
5064 known_x
, known_mode
, known_ret
);
5065 if (CONST_INT_P (XEXP (x
, 1))
5066 && INTVAL (XEXP (x
, 1)) > 0
5067 && INTVAL (XEXP (x
, 1)) < GET_MODE_PRECISION (GET_MODE (x
)))
5068 num0
= MIN ((int) bitwidth
, num0
+ INTVAL (XEXP (x
, 1)));
5073 /* Left shifts destroy copies. */
5074 if (!CONST_INT_P (XEXP (x
, 1))
5075 || INTVAL (XEXP (x
, 1)) < 0
5076 || INTVAL (XEXP (x
, 1)) >= (int) bitwidth
5077 || INTVAL (XEXP (x
, 1)) >= GET_MODE_PRECISION (GET_MODE (x
)))
5080 num0
= cached_num_sign_bit_copies (XEXP (x
, 0), mode
,
5081 known_x
, known_mode
, known_ret
);
5082 return MAX (1, num0
- INTVAL (XEXP (x
, 1)));
5085 num0
= cached_num_sign_bit_copies (XEXP (x
, 1), mode
,
5086 known_x
, known_mode
, known_ret
);
5087 num1
= cached_num_sign_bit_copies (XEXP (x
, 2), mode
,
5088 known_x
, known_mode
, known_ret
);
5089 return MIN (num0
, num1
);
5091 case EQ
: case NE
: case GE
: case GT
: case LE
: case LT
:
5092 case UNEQ
: case LTGT
: case UNGE
: case UNGT
: case UNLE
: case UNLT
:
5093 case GEU
: case GTU
: case LEU
: case LTU
:
5094 case UNORDERED
: case ORDERED
:
5095 /* If the constant is negative, take its 1's complement and remask.
5096 Then see how many zero bits we have. */
5097 nonzero
= STORE_FLAG_VALUE
;
5098 if (bitwidth
<= HOST_BITS_PER_WIDE_INT
5099 && (nonzero
& ((unsigned HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0)
5100 nonzero
= (~nonzero
) & GET_MODE_MASK (mode
);
5102 return (nonzero
== 0 ? bitwidth
: bitwidth
- floor_log2 (nonzero
) - 1);
5108 /* If we haven't been able to figure it out by one of the above rules,
5109 see if some of the high-order bits are known to be zero. If so,
5110 count those bits and return one less than that amount. If we can't
5111 safely compute the mask for this mode, always return BITWIDTH. */
5113 bitwidth
= GET_MODE_PRECISION (mode
);
5114 if (bitwidth
> HOST_BITS_PER_WIDE_INT
)
5117 nonzero
= nonzero_bits (x
, mode
);
5118 return nonzero
& ((unsigned HOST_WIDE_INT
) 1 << (bitwidth
- 1))
5119 ? 1 : bitwidth
- floor_log2 (nonzero
) - 1;
5122 /* Calculate the rtx_cost of a single instruction. A return value of
5123 zero indicates an instruction pattern without a known cost. */
5126 insn_rtx_cost (rtx pat
, bool speed
)
5131 /* Extract the single set rtx from the instruction pattern.
5132 We can't use single_set since we only have the pattern. */
5133 if (GET_CODE (pat
) == SET
)
5135 else if (GET_CODE (pat
) == PARALLEL
)
5138 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
5140 rtx x
= XVECEXP (pat
, 0, i
);
5141 if (GET_CODE (x
) == SET
)
5154 cost
= set_src_cost (SET_SRC (set
), GET_MODE (SET_DEST (set
)), speed
);
5155 return cost
> 0 ? cost
: COSTS_N_INSNS (1);
5158 /* Returns estimate on cost of computing SEQ. */
5161 seq_cost (const rtx_insn
*seq
, bool speed
)
5166 for (; seq
; seq
= NEXT_INSN (seq
))
5168 set
= single_set (seq
);
5170 cost
+= set_rtx_cost (set
, speed
);
5178 /* Given an insn INSN and condition COND, return the condition in a
5179 canonical form to simplify testing by callers. Specifically:
5181 (1) The code will always be a comparison operation (EQ, NE, GT, etc.).
5182 (2) Both operands will be machine operands; (cc0) will have been replaced.
5183 (3) If an operand is a constant, it will be the second operand.
5184 (4) (LE x const) will be replaced with (LT x <const+1>) and similarly
5185 for GE, GEU, and LEU.
5187 If the condition cannot be understood, or is an inequality floating-point
5188 comparison which needs to be reversed, 0 will be returned.
5190 If REVERSE is nonzero, then reverse the condition prior to canonizing it.
5192 If EARLIEST is nonzero, it is a pointer to a place where the earliest
5193 insn used in locating the condition was found. If a replacement test
5194 of the condition is desired, it should be placed in front of that
5195 insn and we will be sure that the inputs are still valid.
5197 If WANT_REG is nonzero, we wish the condition to be relative to that
5198 register, if possible. Therefore, do not canonicalize the condition
5199 further. If ALLOW_CC_MODE is nonzero, allow the condition returned
5200 to be a compare to a CC mode register.
5202 If VALID_AT_INSN_P, the condition must be valid at both *EARLIEST
5206 canonicalize_condition (rtx_insn
*insn
, rtx cond
, int reverse
,
5207 rtx_insn
**earliest
,
5208 rtx want_reg
, int allow_cc_mode
, int valid_at_insn_p
)
5211 rtx_insn
*prev
= insn
;
5215 int reverse_code
= 0;
5217 basic_block bb
= BLOCK_FOR_INSN (insn
);
5219 code
= GET_CODE (cond
);
5220 mode
= GET_MODE (cond
);
5221 op0
= XEXP (cond
, 0);
5222 op1
= XEXP (cond
, 1);
5225 code
= reversed_comparison_code (cond
, insn
);
5226 if (code
== UNKNOWN
)
5232 /* If we are comparing a register with zero, see if the register is set
5233 in the previous insn to a COMPARE or a comparison operation. Perform
5234 the same tests as a function of STORE_FLAG_VALUE as find_comparison_args
5237 while ((GET_RTX_CLASS (code
) == RTX_COMPARE
5238 || GET_RTX_CLASS (code
) == RTX_COMM_COMPARE
)
5239 && op1
== CONST0_RTX (GET_MODE (op0
))
5242 /* Set nonzero when we find something of interest. */
5245 /* If comparison with cc0, import actual comparison from compare
5249 if ((prev
= prev_nonnote_insn (prev
)) == 0
5250 || !NONJUMP_INSN_P (prev
)
5251 || (set
= single_set (prev
)) == 0
5252 || SET_DEST (set
) != cc0_rtx
)
5255 op0
= SET_SRC (set
);
5256 op1
= CONST0_RTX (GET_MODE (op0
));
5261 /* If this is a COMPARE, pick up the two things being compared. */
5262 if (GET_CODE (op0
) == COMPARE
)
5264 op1
= XEXP (op0
, 1);
5265 op0
= XEXP (op0
, 0);
5268 else if (!REG_P (op0
))
5271 /* Go back to the previous insn. Stop if it is not an INSN. We also
5272 stop if it isn't a single set or if it has a REG_INC note because
5273 we don't want to bother dealing with it. */
5275 prev
= prev_nonnote_nondebug_insn (prev
);
5278 || !NONJUMP_INSN_P (prev
)
5279 || FIND_REG_INC_NOTE (prev
, NULL_RTX
)
5280 /* In cfglayout mode, there do not have to be labels at the
5281 beginning of a block, or jumps at the end, so the previous
5282 conditions would not stop us when we reach bb boundary. */
5283 || BLOCK_FOR_INSN (prev
) != bb
)
5286 set
= set_of (op0
, prev
);
5289 && (GET_CODE (set
) != SET
5290 || !rtx_equal_p (SET_DEST (set
), op0
)))
5293 /* If this is setting OP0, get what it sets it to if it looks
5297 machine_mode inner_mode
= GET_MODE (SET_DEST (set
));
5298 #ifdef FLOAT_STORE_FLAG_VALUE
5299 REAL_VALUE_TYPE fsfv
;
5302 /* ??? We may not combine comparisons done in a CCmode with
5303 comparisons not done in a CCmode. This is to aid targets
5304 like Alpha that have an IEEE compliant EQ instruction, and
5305 a non-IEEE compliant BEQ instruction. The use of CCmode is
5306 actually artificial, simply to prevent the combination, but
5307 should not affect other platforms.
5309 However, we must allow VOIDmode comparisons to match either
5310 CCmode or non-CCmode comparison, because some ports have
5311 modeless comparisons inside branch patterns.
5313 ??? This mode check should perhaps look more like the mode check
5314 in simplify_comparison in combine. */
5315 if (((GET_MODE_CLASS (mode
) == MODE_CC
)
5316 != (GET_MODE_CLASS (inner_mode
) == MODE_CC
))
5318 && inner_mode
!= VOIDmode
)
5320 if (GET_CODE (SET_SRC (set
)) == COMPARE
5323 && val_signbit_known_set_p (inner_mode
,
5325 #ifdef FLOAT_STORE_FLAG_VALUE
5327 && SCALAR_FLOAT_MODE_P (inner_mode
)
5328 && (fsfv
= FLOAT_STORE_FLAG_VALUE (inner_mode
),
5329 REAL_VALUE_NEGATIVE (fsfv
)))
5332 && COMPARISON_P (SET_SRC (set
))))
5334 else if (((code
== EQ
5336 && val_signbit_known_set_p (inner_mode
,
5338 #ifdef FLOAT_STORE_FLAG_VALUE
5340 && SCALAR_FLOAT_MODE_P (inner_mode
)
5341 && (fsfv
= FLOAT_STORE_FLAG_VALUE (inner_mode
),
5342 REAL_VALUE_NEGATIVE (fsfv
)))
5345 && COMPARISON_P (SET_SRC (set
)))
5350 else if ((code
== EQ
|| code
== NE
)
5351 && GET_CODE (SET_SRC (set
)) == XOR
)
5352 /* Handle sequences like:
5355 ...(eq|ne op0 (const_int 0))...
5359 (eq op0 (const_int 0)) reduces to (eq X Y)
5360 (ne op0 (const_int 0)) reduces to (ne X Y)
5362 This is the form used by MIPS16, for example. */
5368 else if (reg_set_p (op0
, prev
))
5369 /* If this sets OP0, but not directly, we have to give up. */
5374 /* If the caller is expecting the condition to be valid at INSN,
5375 make sure X doesn't change before INSN. */
5376 if (valid_at_insn_p
)
5377 if (modified_in_p (x
, prev
) || modified_between_p (x
, prev
, insn
))
5379 if (COMPARISON_P (x
))
5380 code
= GET_CODE (x
);
5383 code
= reversed_comparison_code (x
, prev
);
5384 if (code
== UNKNOWN
)
5389 op0
= XEXP (x
, 0), op1
= XEXP (x
, 1);
5395 /* If constant is first, put it last. */
5396 if (CONSTANT_P (op0
))
5397 code
= swap_condition (code
), tem
= op0
, op0
= op1
, op1
= tem
;
5399 /* If OP0 is the result of a comparison, we weren't able to find what
5400 was really being compared, so fail. */
5402 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_CC
)
5405 /* Canonicalize any ordered comparison with integers involving equality
5406 if we can do computations in the relevant mode and we do not
5409 if (GET_MODE_CLASS (GET_MODE (op0
)) != MODE_CC
5410 && CONST_INT_P (op1
)
5411 && GET_MODE (op0
) != VOIDmode
5412 && GET_MODE_PRECISION (GET_MODE (op0
)) <= HOST_BITS_PER_WIDE_INT
)
5414 HOST_WIDE_INT const_val
= INTVAL (op1
);
5415 unsigned HOST_WIDE_INT uconst_val
= const_val
;
5416 unsigned HOST_WIDE_INT max_val
5417 = (unsigned HOST_WIDE_INT
) GET_MODE_MASK (GET_MODE (op0
));
5422 if ((unsigned HOST_WIDE_INT
) const_val
!= max_val
>> 1)
5423 code
= LT
, op1
= gen_int_mode (const_val
+ 1, GET_MODE (op0
));
5426 /* When cross-compiling, const_val might be sign-extended from
5427 BITS_PER_WORD to HOST_BITS_PER_WIDE_INT */
5429 if ((const_val
& max_val
)
5430 != ((unsigned HOST_WIDE_INT
) 1
5431 << (GET_MODE_PRECISION (GET_MODE (op0
)) - 1)))
5432 code
= GT
, op1
= gen_int_mode (const_val
- 1, GET_MODE (op0
));
5436 if (uconst_val
< max_val
)
5437 code
= LTU
, op1
= gen_int_mode (uconst_val
+ 1, GET_MODE (op0
));
5441 if (uconst_val
!= 0)
5442 code
= GTU
, op1
= gen_int_mode (uconst_val
- 1, GET_MODE (op0
));
5450 /* Never return CC0; return zero instead. */
5454 return gen_rtx_fmt_ee (code
, VOIDmode
, op0
, op1
);
5457 /* Given a jump insn JUMP, return the condition that will cause it to branch
5458 to its JUMP_LABEL. If the condition cannot be understood, or is an
5459 inequality floating-point comparison which needs to be reversed, 0 will
5462 If EARLIEST is nonzero, it is a pointer to a place where the earliest
5463 insn used in locating the condition was found. If a replacement test
5464 of the condition is desired, it should be placed in front of that
5465 insn and we will be sure that the inputs are still valid. If EARLIEST
5466 is null, the returned condition will be valid at INSN.
5468 If ALLOW_CC_MODE is nonzero, allow the condition returned to be a
5469 compare CC mode register.
5471 VALID_AT_INSN_P is the same as for canonicalize_condition. */
5474 get_condition (rtx_insn
*jump
, rtx_insn
**earliest
, int allow_cc_mode
,
5475 int valid_at_insn_p
)
5481 /* If this is not a standard conditional jump, we can't parse it. */
5483 || ! any_condjump_p (jump
))
5485 set
= pc_set (jump
);
5487 cond
= XEXP (SET_SRC (set
), 0);
5489 /* If this branches to JUMP_LABEL when the condition is false, reverse
5492 = GET_CODE (XEXP (SET_SRC (set
), 2)) == LABEL_REF
5493 && LABEL_REF_LABEL (XEXP (SET_SRC (set
), 2)) == JUMP_LABEL (jump
);
5495 return canonicalize_condition (jump
, cond
, reverse
, earliest
, NULL_RTX
,
5496 allow_cc_mode
, valid_at_insn_p
);
5499 /* Initialize the table NUM_SIGN_BIT_COPIES_IN_REP based on
5500 TARGET_MODE_REP_EXTENDED.
5502 Note that we assume that the property of
5503 TARGET_MODE_REP_EXTENDED(B, C) is sticky to the integral modes
5504 narrower than mode B. I.e., if A is a mode narrower than B then in
5505 order to be able to operate on it in mode B, mode A needs to
5506 satisfy the requirements set by the representation of mode B. */
5509 init_num_sign_bit_copies_in_rep (void)
5511 machine_mode mode
, in_mode
;
5513 for (in_mode
= GET_CLASS_NARROWEST_MODE (MODE_INT
); in_mode
!= VOIDmode
;
5514 in_mode
= GET_MODE_WIDER_MODE (mode
))
5515 for (mode
= GET_CLASS_NARROWEST_MODE (MODE_INT
); mode
!= in_mode
;
5516 mode
= GET_MODE_WIDER_MODE (mode
))
5520 /* Currently, it is assumed that TARGET_MODE_REP_EXTENDED
5521 extends to the next widest mode. */
5522 gcc_assert (targetm
.mode_rep_extended (mode
, in_mode
) == UNKNOWN
5523 || GET_MODE_WIDER_MODE (mode
) == in_mode
);
5525 /* We are in in_mode. Count how many bits outside of mode
5526 have to be copies of the sign-bit. */
5527 for (i
= mode
; i
!= in_mode
; i
= GET_MODE_WIDER_MODE (i
))
5529 machine_mode wider
= GET_MODE_WIDER_MODE (i
);
5531 if (targetm
.mode_rep_extended (i
, wider
) == SIGN_EXTEND
5532 /* We can only check sign-bit copies starting from the
5533 top-bit. In order to be able to check the bits we
5534 have already seen we pretend that subsequent bits
5535 have to be sign-bit copies too. */
5536 || num_sign_bit_copies_in_rep
[in_mode
][mode
])
5537 num_sign_bit_copies_in_rep
[in_mode
][mode
]
5538 += GET_MODE_PRECISION (wider
) - GET_MODE_PRECISION (i
);
5543 /* Suppose that truncation from the machine mode of X to MODE is not a
5544 no-op. See if there is anything special about X so that we can
5545 assume it already contains a truncated value of MODE. */
5548 truncated_to_mode (machine_mode mode
, const_rtx x
)
5550 /* This register has already been used in MODE without explicit
5552 if (REG_P (x
) && rtl_hooks
.reg_truncated_to_mode (mode
, x
))
5555 /* See if we already satisfy the requirements of MODE. If yes we
5556 can just switch to MODE. */
5557 if (num_sign_bit_copies_in_rep
[GET_MODE (x
)][mode
]
5558 && (num_sign_bit_copies (x
, GET_MODE (x
))
5559 >= num_sign_bit_copies_in_rep
[GET_MODE (x
)][mode
] + 1))
5565 /* Return true if RTX code CODE has a single sequence of zero or more
5566 "e" operands and no rtvec operands. Initialize its rtx_all_subrtx_bounds
5567 entry in that case. */
5570 setup_reg_subrtx_bounds (unsigned int code
)
5572 const char *format
= GET_RTX_FORMAT ((enum rtx_code
) code
);
5574 for (; format
[i
] != 'e'; ++i
)
5577 /* No subrtxes. Leave start and count as 0. */
5579 if (format
[i
] == 'E' || format
[i
] == 'V')
5583 /* Record the sequence of 'e's. */
5584 rtx_all_subrtx_bounds
[code
].start
= i
;
5587 while (format
[i
] == 'e');
5588 rtx_all_subrtx_bounds
[code
].count
= i
- rtx_all_subrtx_bounds
[code
].start
;
5589 /* rtl-iter.h relies on this. */
5590 gcc_checking_assert (rtx_all_subrtx_bounds
[code
].count
<= 3);
5592 for (; format
[i
]; ++i
)
5593 if (format
[i
] == 'E' || format
[i
] == 'V' || format
[i
] == 'e')
5599 /* Initialize rtx_all_subrtx_bounds. */
5604 for (i
= 0; i
< NUM_RTX_CODE
; i
++)
5606 if (!setup_reg_subrtx_bounds (i
))
5607 rtx_all_subrtx_bounds
[i
].count
= UCHAR_MAX
;
5608 if (GET_RTX_CLASS (i
) != RTX_CONST_OBJ
)
5609 rtx_nonconst_subrtx_bounds
[i
] = rtx_all_subrtx_bounds
[i
];
5612 init_num_sign_bit_copies_in_rep ();
5615 /* Check whether this is a constant pool constant. */
5617 constant_pool_constant_p (rtx x
)
5619 x
= avoid_constant_pool_reference (x
);
5620 return CONST_DOUBLE_P (x
);
5623 /* If M is a bitmask that selects a field of low-order bits within an item but
5624 not the entire word, return the length of the field. Return -1 otherwise.
5625 M is used in machine mode MODE. */
5628 low_bitmask_len (machine_mode mode
, unsigned HOST_WIDE_INT m
)
5630 if (mode
!= VOIDmode
)
5632 if (GET_MODE_PRECISION (mode
) > HOST_BITS_PER_WIDE_INT
)
5634 m
&= GET_MODE_MASK (mode
);
5637 return exact_log2 (m
+ 1);
5640 /* Return the mode of MEM's address. */
5643 get_address_mode (rtx mem
)
5647 gcc_assert (MEM_P (mem
));
5648 mode
= GET_MODE (XEXP (mem
, 0));
5649 if (mode
!= VOIDmode
)
5651 return targetm
.addr_space
.address_mode (MEM_ADDR_SPACE (mem
));
5654 /* Split up a CONST_DOUBLE or integer constant rtx
5655 into two rtx's for single words,
5656 storing in *FIRST the word that comes first in memory in the target
5657 and in *SECOND the other.
5659 TODO: This function needs to be rewritten to work on any size
5663 split_double (rtx value
, rtx
*first
, rtx
*second
)
5665 if (CONST_INT_P (value
))
5667 if (HOST_BITS_PER_WIDE_INT
>= (2 * BITS_PER_WORD
))
5669 /* In this case the CONST_INT holds both target words.
5670 Extract the bits from it into two word-sized pieces.
5671 Sign extend each half to HOST_WIDE_INT. */
5672 unsigned HOST_WIDE_INT low
, high
;
5673 unsigned HOST_WIDE_INT mask
, sign_bit
, sign_extend
;
5674 unsigned bits_per_word
= BITS_PER_WORD
;
5676 /* Set sign_bit to the most significant bit of a word. */
5678 sign_bit
<<= bits_per_word
- 1;
5680 /* Set mask so that all bits of the word are set. We could
5681 have used 1 << BITS_PER_WORD instead of basing the
5682 calculation on sign_bit. However, on machines where
5683 HOST_BITS_PER_WIDE_INT == BITS_PER_WORD, it could cause a
5684 compiler warning, even though the code would never be
5686 mask
= sign_bit
<< 1;
5689 /* Set sign_extend as any remaining bits. */
5690 sign_extend
= ~mask
;
5692 /* Pick the lower word and sign-extend it. */
5693 low
= INTVAL (value
);
5698 /* Pick the higher word, shifted to the least significant
5699 bits, and sign-extend it. */
5700 high
= INTVAL (value
);
5701 high
>>= bits_per_word
- 1;
5704 if (high
& sign_bit
)
5705 high
|= sign_extend
;
5707 /* Store the words in the target machine order. */
5708 if (WORDS_BIG_ENDIAN
)
5710 *first
= GEN_INT (high
);
5711 *second
= GEN_INT (low
);
5715 *first
= GEN_INT (low
);
5716 *second
= GEN_INT (high
);
5721 /* The rule for using CONST_INT for a wider mode
5722 is that we regard the value as signed.
5723 So sign-extend it. */
5724 rtx high
= (INTVAL (value
) < 0 ? constm1_rtx
: const0_rtx
);
5725 if (WORDS_BIG_ENDIAN
)
5737 else if (GET_CODE (value
) == CONST_WIDE_INT
)
5739 /* All of this is scary code and needs to be converted to
5740 properly work with any size integer. */
5741 gcc_assert (CONST_WIDE_INT_NUNITS (value
) == 2);
5742 if (WORDS_BIG_ENDIAN
)
5744 *first
= GEN_INT (CONST_WIDE_INT_ELT (value
, 1));
5745 *second
= GEN_INT (CONST_WIDE_INT_ELT (value
, 0));
5749 *first
= GEN_INT (CONST_WIDE_INT_ELT (value
, 0));
5750 *second
= GEN_INT (CONST_WIDE_INT_ELT (value
, 1));
5753 else if (!CONST_DOUBLE_P (value
))
5755 if (WORDS_BIG_ENDIAN
)
5757 *first
= const0_rtx
;
5763 *second
= const0_rtx
;
5766 else if (GET_MODE (value
) == VOIDmode
5767 /* This is the old way we did CONST_DOUBLE integers. */
5768 || GET_MODE_CLASS (GET_MODE (value
)) == MODE_INT
)
5770 /* In an integer, the words are defined as most and least significant.
5771 So order them by the target's convention. */
5772 if (WORDS_BIG_ENDIAN
)
5774 *first
= GEN_INT (CONST_DOUBLE_HIGH (value
));
5775 *second
= GEN_INT (CONST_DOUBLE_LOW (value
));
5779 *first
= GEN_INT (CONST_DOUBLE_LOW (value
));
5780 *second
= GEN_INT (CONST_DOUBLE_HIGH (value
));
5787 /* Note, this converts the REAL_VALUE_TYPE to the target's
5788 format, splits up the floating point double and outputs
5789 exactly 32 bits of it into each of l[0] and l[1] --
5790 not necessarily BITS_PER_WORD bits. */
5791 REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (value
), l
);
5793 /* If 32 bits is an entire word for the target, but not for the host,
5794 then sign-extend on the host so that the number will look the same
5795 way on the host that it would on the target. See for instance
5796 simplify_unary_operation. The #if is needed to avoid compiler
5799 #if HOST_BITS_PER_LONG > 32
5800 if (BITS_PER_WORD
< HOST_BITS_PER_LONG
&& BITS_PER_WORD
== 32)
5802 if (l
[0] & ((long) 1 << 31))
5803 l
[0] |= ((unsigned long) (-1) << 32);
5804 if (l
[1] & ((long) 1 << 31))
5805 l
[1] |= ((unsigned long) (-1) << 32);
5809 *first
= GEN_INT (l
[0]);
5810 *second
= GEN_INT (l
[1]);
5814 /* Return true if X is a sign_extract or zero_extract from the least
5818 lsb_bitfield_op_p (rtx x
)
5820 if (GET_RTX_CLASS (GET_CODE (x
)) == RTX_BITFIELD_OPS
)
5822 machine_mode mode
= GET_MODE (XEXP (x
, 0));
5823 HOST_WIDE_INT len
= INTVAL (XEXP (x
, 1));
5824 HOST_WIDE_INT pos
= INTVAL (XEXP (x
, 2));
5826 return (pos
== (BITS_BIG_ENDIAN
? GET_MODE_PRECISION (mode
) - len
: 0));
5831 /* Strip outer address "mutations" from LOC and return a pointer to the
5832 inner value. If OUTER_CODE is nonnull, store the code of the innermost
5833 stripped expression there.
5835 "Mutations" either convert between modes or apply some kind of
5836 extension, truncation or alignment. */
5839 strip_address_mutations (rtx
*loc
, enum rtx_code
*outer_code
)
5843 enum rtx_code code
= GET_CODE (*loc
);
5844 if (GET_RTX_CLASS (code
) == RTX_UNARY
)
5845 /* Things like SIGN_EXTEND, ZERO_EXTEND and TRUNCATE can be
5846 used to convert between pointer sizes. */
5847 loc
= &XEXP (*loc
, 0);
5848 else if (lsb_bitfield_op_p (*loc
))
5849 /* A [SIGN|ZERO]_EXTRACT from the least significant bit effectively
5850 acts as a combined truncation and extension. */
5851 loc
= &XEXP (*loc
, 0);
5852 else if (code
== AND
&& CONST_INT_P (XEXP (*loc
, 1)))
5853 /* (and ... (const_int -X)) is used to align to X bytes. */
5854 loc
= &XEXP (*loc
, 0);
5855 else if (code
== SUBREG
5856 && !OBJECT_P (SUBREG_REG (*loc
))
5857 && subreg_lowpart_p (*loc
))
5858 /* (subreg (operator ...) ...) inside and is used for mode
5860 loc
= &SUBREG_REG (*loc
);
5868 /* Return true if CODE applies some kind of scale. The scaled value is
5869 is the first operand and the scale is the second. */
5872 binary_scale_code_p (enum rtx_code code
)
5874 return (code
== MULT
5876 /* Needed by ARM targets. */
5880 || code
== ROTATERT
);
5883 /* If *INNER can be interpreted as a base, return a pointer to the inner term
5884 (see address_info). Return null otherwise. */
5887 get_base_term (rtx
*inner
)
5889 if (GET_CODE (*inner
) == LO_SUM
)
5890 inner
= strip_address_mutations (&XEXP (*inner
, 0));
5893 || GET_CODE (*inner
) == SUBREG
5894 || GET_CODE (*inner
) == SCRATCH
)
5899 /* If *INNER can be interpreted as an index, return a pointer to the inner term
5900 (see address_info). Return null otherwise. */
5903 get_index_term (rtx
*inner
)
5905 /* At present, only constant scales are allowed. */
5906 if (binary_scale_code_p (GET_CODE (*inner
)) && CONSTANT_P (XEXP (*inner
, 1)))
5907 inner
= strip_address_mutations (&XEXP (*inner
, 0));
5910 || GET_CODE (*inner
) == SUBREG
5911 || GET_CODE (*inner
) == SCRATCH
)
5916 /* Set the segment part of address INFO to LOC, given that INNER is the
5920 set_address_segment (struct address_info
*info
, rtx
*loc
, rtx
*inner
)
5922 gcc_assert (!info
->segment
);
5923 info
->segment
= loc
;
5924 info
->segment_term
= inner
;
5927 /* Set the base part of address INFO to LOC, given that INNER is the
5931 set_address_base (struct address_info
*info
, rtx
*loc
, rtx
*inner
)
5933 gcc_assert (!info
->base
);
5935 info
->base_term
= inner
;
5938 /* Set the index part of address INFO to LOC, given that INNER is the
5942 set_address_index (struct address_info
*info
, rtx
*loc
, rtx
*inner
)
5944 gcc_assert (!info
->index
);
5946 info
->index_term
= inner
;
5949 /* Set the displacement part of address INFO to LOC, given that INNER
5950 is the constant term. */
5953 set_address_disp (struct address_info
*info
, rtx
*loc
, rtx
*inner
)
5955 gcc_assert (!info
->disp
);
5957 info
->disp_term
= inner
;
5960 /* INFO->INNER describes a {PRE,POST}_{INC,DEC} address. Set up the
5961 rest of INFO accordingly. */
5964 decompose_incdec_address (struct address_info
*info
)
5966 info
->autoinc_p
= true;
5968 rtx
*base
= &XEXP (*info
->inner
, 0);
5969 set_address_base (info
, base
, base
);
5970 gcc_checking_assert (info
->base
== info
->base_term
);
5972 /* These addresses are only valid when the size of the addressed
5974 gcc_checking_assert (info
->mode
!= VOIDmode
);
5977 /* INFO->INNER describes a {PRE,POST}_MODIFY address. Set up the rest
5978 of INFO accordingly. */
5981 decompose_automod_address (struct address_info
*info
)
5983 info
->autoinc_p
= true;
5985 rtx
*base
= &XEXP (*info
->inner
, 0);
5986 set_address_base (info
, base
, base
);
5987 gcc_checking_assert (info
->base
== info
->base_term
);
5989 rtx plus
= XEXP (*info
->inner
, 1);
5990 gcc_assert (GET_CODE (plus
) == PLUS
);
5992 info
->base_term2
= &XEXP (plus
, 0);
5993 gcc_checking_assert (rtx_equal_p (*info
->base_term
, *info
->base_term2
));
5995 rtx
*step
= &XEXP (plus
, 1);
5996 rtx
*inner_step
= strip_address_mutations (step
);
5997 if (CONSTANT_P (*inner_step
))
5998 set_address_disp (info
, step
, inner_step
);
6000 set_address_index (info
, step
, inner_step
);
6003 /* Treat *LOC as a tree of PLUS operands and store pointers to the summed
6004 values in [PTR, END). Return a pointer to the end of the used array. */
6007 extract_plus_operands (rtx
*loc
, rtx
**ptr
, rtx
**end
)
6010 if (GET_CODE (x
) == PLUS
)
6012 ptr
= extract_plus_operands (&XEXP (x
, 0), ptr
, end
);
6013 ptr
= extract_plus_operands (&XEXP (x
, 1), ptr
, end
);
6017 gcc_assert (ptr
!= end
);
6023 /* Evaluate the likelihood of X being a base or index value, returning
6024 positive if it is likely to be a base, negative if it is likely to be
6025 an index, and 0 if we can't tell. Make the magnitude of the return
6026 value reflect the amount of confidence we have in the answer.
6028 MODE, AS, OUTER_CODE and INDEX_CODE are as for ok_for_base_p_1. */
6031 baseness (rtx x
, machine_mode mode
, addr_space_t as
,
6032 enum rtx_code outer_code
, enum rtx_code index_code
)
6034 /* Believe *_POINTER unless the address shape requires otherwise. */
6035 if (REG_P (x
) && REG_POINTER (x
))
6037 if (MEM_P (x
) && MEM_POINTER (x
))
6040 if (REG_P (x
) && HARD_REGISTER_P (x
))
6042 /* X is a hard register. If it only fits one of the base
6043 or index classes, choose that interpretation. */
6044 int regno
= REGNO (x
);
6045 bool base_p
= ok_for_base_p_1 (regno
, mode
, as
, outer_code
, index_code
);
6046 bool index_p
= REGNO_OK_FOR_INDEX_P (regno
);
6047 if (base_p
!= index_p
)
6048 return base_p
? 1 : -1;
6053 /* INFO->INNER describes a normal, non-automodified address.
6054 Fill in the rest of INFO accordingly. */
6057 decompose_normal_address (struct address_info
*info
)
6059 /* Treat the address as the sum of up to four values. */
6061 size_t n_ops
= extract_plus_operands (info
->inner
, ops
,
6062 ops
+ ARRAY_SIZE (ops
)) - ops
;
6064 /* If there is more than one component, any base component is in a PLUS. */
6066 info
->base_outer_code
= PLUS
;
6068 /* Try to classify each sum operand now. Leave those that could be
6069 either a base or an index in OPS. */
6072 for (size_t in
= 0; in
< n_ops
; ++in
)
6075 rtx
*inner
= strip_address_mutations (loc
);
6076 if (CONSTANT_P (*inner
))
6077 set_address_disp (info
, loc
, inner
);
6078 else if (GET_CODE (*inner
) == UNSPEC
)
6079 set_address_segment (info
, loc
, inner
);
6082 /* The only other possibilities are a base or an index. */
6083 rtx
*base_term
= get_base_term (inner
);
6084 rtx
*index_term
= get_index_term (inner
);
6085 gcc_assert (base_term
|| index_term
);
6087 set_address_index (info
, loc
, index_term
);
6088 else if (!index_term
)
6089 set_address_base (info
, loc
, base_term
);
6092 gcc_assert (base_term
== index_term
);
6094 inner_ops
[out
] = base_term
;
6100 /* Classify the remaining OPS members as bases and indexes. */
6103 /* If we haven't seen a base or an index yet, assume that this is
6104 the base. If we were confident that another term was the base
6105 or index, treat the remaining operand as the other kind. */
6107 set_address_base (info
, ops
[0], inner_ops
[0]);
6109 set_address_index (info
, ops
[0], inner_ops
[0]);
6113 /* In the event of a tie, assume the base comes first. */
6114 if (baseness (*inner_ops
[0], info
->mode
, info
->as
, PLUS
,
6116 >= baseness (*inner_ops
[1], info
->mode
, info
->as
, PLUS
,
6117 GET_CODE (*ops
[0])))
6119 set_address_base (info
, ops
[0], inner_ops
[0]);
6120 set_address_index (info
, ops
[1], inner_ops
[1]);
6124 set_address_base (info
, ops
[1], inner_ops
[1]);
6125 set_address_index (info
, ops
[0], inner_ops
[0]);
6129 gcc_assert (out
== 0);
6132 /* Describe address *LOC in *INFO. MODE is the mode of the addressed value,
6133 or VOIDmode if not known. AS is the address space associated with LOC.
6134 OUTER_CODE is MEM if *LOC is a MEM address and ADDRESS otherwise. */
6137 decompose_address (struct address_info
*info
, rtx
*loc
, machine_mode mode
,
6138 addr_space_t as
, enum rtx_code outer_code
)
6140 memset (info
, 0, sizeof (*info
));
6143 info
->addr_outer_code
= outer_code
;
6145 info
->inner
= strip_address_mutations (loc
, &outer_code
);
6146 info
->base_outer_code
= outer_code
;
6147 switch (GET_CODE (*info
->inner
))
6153 decompose_incdec_address (info
);
6158 decompose_automod_address (info
);
6162 decompose_normal_address (info
);
6167 /* Describe address operand LOC in INFO. */
6170 decompose_lea_address (struct address_info
*info
, rtx
*loc
)
6172 decompose_address (info
, loc
, VOIDmode
, ADDR_SPACE_GENERIC
, ADDRESS
);
6175 /* Describe the address of MEM X in INFO. */
6178 decompose_mem_address (struct address_info
*info
, rtx x
)
6180 gcc_assert (MEM_P (x
));
6181 decompose_address (info
, &XEXP (x
, 0), GET_MODE (x
),
6182 MEM_ADDR_SPACE (x
), MEM
);
6185 /* Update INFO after a change to the address it describes. */
6188 update_address (struct address_info
*info
)
6190 decompose_address (info
, info
->outer
, info
->mode
, info
->as
,
6191 info
->addr_outer_code
);
6194 /* Return the scale applied to *INFO->INDEX_TERM, or 0 if the index is
6195 more complicated than that. */
6198 get_index_scale (const struct address_info
*info
)
6200 rtx index
= *info
->index
;
6201 if (GET_CODE (index
) == MULT
6202 && CONST_INT_P (XEXP (index
, 1))
6203 && info
->index_term
== &XEXP (index
, 0))
6204 return INTVAL (XEXP (index
, 1));
6206 if (GET_CODE (index
) == ASHIFT
6207 && CONST_INT_P (XEXP (index
, 1))
6208 && info
->index_term
== &XEXP (index
, 0))
6209 return (HOST_WIDE_INT
) 1 << INTVAL (XEXP (index
, 1));
6211 if (info
->index
== info
->index_term
)
6217 /* Return the "index code" of INFO, in the form required by
6221 get_index_code (const struct address_info
*info
)
6224 return GET_CODE (*info
->index
);
6227 return GET_CODE (*info
->disp
);
6232 /* Return true if X contains a thread-local symbol. */
6235 tls_referenced_p (const_rtx x
)
6237 if (!targetm
.have_tls
)
6240 subrtx_iterator::array_type array
;
6241 FOR_EACH_SUBRTX (iter
, array
, x
, ALL
)
6242 if (GET_CODE (*iter
) == SYMBOL_REF
&& SYMBOL_REF_TLS_MODEL (*iter
) != 0)