1 /* Analyze RTL for GNU compiler.
2 Copyright (C) 1987-2016 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify it under
7 the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 3, or (at your option) any later
11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
23 #include "coretypes.h"
31 #include "insn-config.h"
33 #include "emit-rtl.h" /* FIXME: Can go away once crtl is moved to rtl.h. */
35 #include "addresses.h"
38 /* Forward declarations */
39 static void set_of_1 (rtx
, const_rtx
, void *);
40 static bool covers_regno_p (const_rtx
, unsigned int);
41 static bool covers_regno_no_parallel_p (const_rtx
, unsigned int);
42 static int computed_jump_p_1 (const_rtx
);
43 static void parms_set (rtx
, const_rtx
, void *);
45 static unsigned HOST_WIDE_INT
cached_nonzero_bits (const_rtx
, machine_mode
,
46 const_rtx
, machine_mode
,
47 unsigned HOST_WIDE_INT
);
48 static unsigned HOST_WIDE_INT
nonzero_bits1 (const_rtx
, machine_mode
,
49 const_rtx
, machine_mode
,
50 unsigned HOST_WIDE_INT
);
51 static unsigned int cached_num_sign_bit_copies (const_rtx
, machine_mode
, const_rtx
,
54 static unsigned int num_sign_bit_copies1 (const_rtx
, machine_mode
, const_rtx
,
55 machine_mode
, unsigned int);
57 rtx_subrtx_bound_info rtx_all_subrtx_bounds
[NUM_RTX_CODE
];
58 rtx_subrtx_bound_info rtx_nonconst_subrtx_bounds
[NUM_RTX_CODE
];
60 /* Truncation narrows the mode from SOURCE mode to DESTINATION mode.
61 If TARGET_MODE_REP_EXTENDED (DESTINATION, DESTINATION_REP) is
62 SIGN_EXTEND then while narrowing we also have to enforce the
63 representation and sign-extend the value to mode DESTINATION_REP.
65 If the value is already sign-extended to DESTINATION_REP mode we
66 can just switch to DESTINATION mode on it. For each pair of
67 integral modes SOURCE and DESTINATION, when truncating from SOURCE
68 to DESTINATION, NUM_SIGN_BIT_COPIES_IN_REP[SOURCE][DESTINATION]
69 contains the number of high-order bits in SOURCE that have to be
70 copies of the sign-bit so that we can do this mode-switch to
74 num_sign_bit_copies_in_rep
[MAX_MODE_INT
+ 1][MAX_MODE_INT
+ 1];
76 /* Store X into index I of ARRAY. ARRAY is known to have at least I
77 elements. Return the new base of ARRAY. */
80 typename
T::value_type
*
81 generic_subrtx_iterator
<T
>::add_single_to_queue (array_type
&array
,
83 size_t i
, value_type x
)
85 if (base
== array
.stack
)
92 gcc_checking_assert (i
== LOCAL_ELEMS
);
93 /* A previous iteration might also have moved from the stack to the
94 heap, in which case the heap array will already be big enough. */
95 if (vec_safe_length (array
.heap
) <= i
)
96 vec_safe_grow (array
.heap
, i
+ 1);
97 base
= array
.heap
->address ();
98 memcpy (base
, array
.stack
, sizeof (array
.stack
));
99 base
[LOCAL_ELEMS
] = x
;
102 unsigned int length
= array
.heap
->length ();
105 gcc_checking_assert (base
== array
.heap
->address ());
111 gcc_checking_assert (i
== length
);
112 vec_safe_push (array
.heap
, x
);
113 return array
.heap
->address ();
117 /* Add the subrtxes of X to worklist ARRAY, starting at END. Return the
118 number of elements added to the worklist. */
120 template <typename T
>
122 generic_subrtx_iterator
<T
>::add_subrtxes_to_queue (array_type
&array
,
124 size_t end
, rtx_type x
)
126 enum rtx_code code
= GET_CODE (x
);
127 const char *format
= GET_RTX_FORMAT (code
);
128 size_t orig_end
= end
;
129 if (__builtin_expect (INSN_P (x
), false))
131 /* Put the pattern at the top of the queue, since that's what
132 we're likely to want most. It also allows for the SEQUENCE
134 for (int i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; --i
)
135 if (format
[i
] == 'e')
137 value_type subx
= T::get_value (x
->u
.fld
[i
].rt_rtx
);
138 if (__builtin_expect (end
< LOCAL_ELEMS
, true))
141 base
= add_single_to_queue (array
, base
, end
++, subx
);
145 for (int i
= 0; format
[i
]; ++i
)
146 if (format
[i
] == 'e')
148 value_type subx
= T::get_value (x
->u
.fld
[i
].rt_rtx
);
149 if (__builtin_expect (end
< LOCAL_ELEMS
, true))
152 base
= add_single_to_queue (array
, base
, end
++, subx
);
154 else if (format
[i
] == 'E')
156 unsigned int length
= GET_NUM_ELEM (x
->u
.fld
[i
].rt_rtvec
);
157 rtx
*vec
= x
->u
.fld
[i
].rt_rtvec
->elem
;
158 if (__builtin_expect (end
+ length
<= LOCAL_ELEMS
, true))
159 for (unsigned int j
= 0; j
< length
; j
++)
160 base
[end
++] = T::get_value (vec
[j
]);
162 for (unsigned int j
= 0; j
< length
; j
++)
163 base
= add_single_to_queue (array
, base
, end
++,
164 T::get_value (vec
[j
]));
165 if (code
== SEQUENCE
&& end
== length
)
166 /* If the subrtxes of the sequence fill the entire array then
167 we know that no other parts of a containing insn are queued.
168 The caller is therefore iterating over the sequence as a
169 PATTERN (...), so we also want the patterns of the
171 for (unsigned int j
= 0; j
< length
; j
++)
173 typename
T::rtx_type x
= T::get_rtx (base
[j
]);
175 base
[j
] = T::get_value (PATTERN (x
));
178 return end
- orig_end
;
181 template <typename T
>
183 generic_subrtx_iterator
<T
>::free_array (array_type
&array
)
185 vec_free (array
.heap
);
188 template <typename T
>
189 const size_t generic_subrtx_iterator
<T
>::LOCAL_ELEMS
;
191 template class generic_subrtx_iterator
<const_rtx_accessor
>;
192 template class generic_subrtx_iterator
<rtx_var_accessor
>;
193 template class generic_subrtx_iterator
<rtx_ptr_accessor
>;
195 /* Return 1 if the value of X is unstable
196 (would be different at a different point in the program).
197 The frame pointer, arg pointer, etc. are considered stable
198 (within one function) and so is anything marked `unchanging'. */
201 rtx_unstable_p (const_rtx x
)
203 const RTX_CODE code
= GET_CODE (x
);
210 return !MEM_READONLY_P (x
) || rtx_unstable_p (XEXP (x
, 0));
219 /* As in rtx_varies_p, we have to use the actual rtx, not reg number. */
220 if (x
== frame_pointer_rtx
|| x
== hard_frame_pointer_rtx
221 /* The arg pointer varies if it is not a fixed register. */
222 || (x
== arg_pointer_rtx
&& fixed_regs
[ARG_POINTER_REGNUM
]))
224 /* ??? When call-clobbered, the value is stable modulo the restore
225 that must happen after a call. This currently screws up local-alloc
226 into believing that the restore is not needed. */
227 if (!PIC_OFFSET_TABLE_REG_CALL_CLOBBERED
&& x
== pic_offset_table_rtx
)
232 if (MEM_VOLATILE_P (x
))
241 fmt
= GET_RTX_FORMAT (code
);
242 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
245 if (rtx_unstable_p (XEXP (x
, i
)))
248 else if (fmt
[i
] == 'E')
251 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
252 if (rtx_unstable_p (XVECEXP (x
, i
, j
)))
259 /* Return 1 if X has a value that can vary even between two
260 executions of the program. 0 means X can be compared reliably
261 against certain constants or near-constants.
262 FOR_ALIAS is nonzero if we are called from alias analysis; if it is
263 zero, we are slightly more conservative.
264 The frame pointer and the arg pointer are considered constant. */
267 rtx_varies_p (const_rtx x
, bool for_alias
)
280 return !MEM_READONLY_P (x
) || rtx_varies_p (XEXP (x
, 0), for_alias
);
289 /* Note that we have to test for the actual rtx used for the frame
290 and arg pointers and not just the register number in case we have
291 eliminated the frame and/or arg pointer and are using it
293 if (x
== frame_pointer_rtx
|| x
== hard_frame_pointer_rtx
294 /* The arg pointer varies if it is not a fixed register. */
295 || (x
== arg_pointer_rtx
&& fixed_regs
[ARG_POINTER_REGNUM
]))
297 if (x
== pic_offset_table_rtx
298 /* ??? When call-clobbered, the value is stable modulo the restore
299 that must happen after a call. This currently screws up
300 local-alloc into believing that the restore is not needed, so we
301 must return 0 only if we are called from alias analysis. */
302 && (!PIC_OFFSET_TABLE_REG_CALL_CLOBBERED
|| for_alias
))
307 /* The operand 0 of a LO_SUM is considered constant
308 (in fact it is related specifically to operand 1)
309 during alias analysis. */
310 return (! for_alias
&& rtx_varies_p (XEXP (x
, 0), for_alias
))
311 || rtx_varies_p (XEXP (x
, 1), for_alias
);
314 if (MEM_VOLATILE_P (x
))
323 fmt
= GET_RTX_FORMAT (code
);
324 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
327 if (rtx_varies_p (XEXP (x
, i
), for_alias
))
330 else if (fmt
[i
] == 'E')
333 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
334 if (rtx_varies_p (XVECEXP (x
, i
, j
), for_alias
))
341 /* Compute an approximation for the offset between the register
342 FROM and TO for the current function, as it was at the start
346 get_initial_register_offset (int from
, int to
)
348 #ifdef ELIMINABLE_REGS
349 static const struct elim_table_t
353 } table
[] = ELIMINABLE_REGS
;
354 HOST_WIDE_INT offset1
, offset2
;
360 /* It is not safe to call INITIAL_ELIMINATION_OFFSET
361 before the reload pass. We need to give at least
362 an estimation for the resulting frame size. */
363 if (! reload_completed
)
365 offset1
= crtl
->outgoing_args_size
+ get_frame_size ();
366 #if !STACK_GROWS_DOWNWARD
369 if (to
== STACK_POINTER_REGNUM
)
371 else if (from
== STACK_POINTER_REGNUM
)
377 for (i
= 0; i
< ARRAY_SIZE (table
); i
++)
378 if (table
[i
].from
== from
)
380 if (table
[i
].to
== to
)
382 INITIAL_ELIMINATION_OFFSET (table
[i
].from
, table
[i
].to
,
386 for (j
= 0; j
< ARRAY_SIZE (table
); j
++)
388 if (table
[j
].to
== to
389 && table
[j
].from
== table
[i
].to
)
391 INITIAL_ELIMINATION_OFFSET (table
[i
].from
, table
[i
].to
,
393 INITIAL_ELIMINATION_OFFSET (table
[j
].from
, table
[j
].to
,
395 return offset1
+ offset2
;
397 if (table
[j
].from
== to
398 && table
[j
].to
== table
[i
].to
)
400 INITIAL_ELIMINATION_OFFSET (table
[i
].from
, table
[i
].to
,
402 INITIAL_ELIMINATION_OFFSET (table
[j
].from
, table
[j
].to
,
404 return offset1
- offset2
;
408 else if (table
[i
].to
== from
)
410 if (table
[i
].from
== to
)
412 INITIAL_ELIMINATION_OFFSET (table
[i
].from
, table
[i
].to
,
416 for (j
= 0; j
< ARRAY_SIZE (table
); j
++)
418 if (table
[j
].to
== to
419 && table
[j
].from
== table
[i
].from
)
421 INITIAL_ELIMINATION_OFFSET (table
[i
].from
, table
[i
].to
,
423 INITIAL_ELIMINATION_OFFSET (table
[j
].from
, table
[j
].to
,
425 return - offset1
+ offset2
;
427 if (table
[j
].from
== to
428 && table
[j
].to
== table
[i
].from
)
430 INITIAL_ELIMINATION_OFFSET (table
[i
].from
, table
[i
].to
,
432 INITIAL_ELIMINATION_OFFSET (table
[j
].from
, table
[j
].to
,
434 return - offset1
- offset2
;
439 /* If the requested register combination was not found,
440 try a different more simple combination. */
441 if (from
== ARG_POINTER_REGNUM
)
442 return get_initial_register_offset (HARD_FRAME_POINTER_REGNUM
, to
);
443 else if (to
== ARG_POINTER_REGNUM
)
444 return get_initial_register_offset (from
, HARD_FRAME_POINTER_REGNUM
);
445 else if (from
== HARD_FRAME_POINTER_REGNUM
)
446 return get_initial_register_offset (FRAME_POINTER_REGNUM
, to
);
447 else if (to
== HARD_FRAME_POINTER_REGNUM
)
448 return get_initial_register_offset (from
, FRAME_POINTER_REGNUM
);
453 HOST_WIDE_INT offset
;
458 if (reload_completed
)
460 INITIAL_FRAME_POINTER_OFFSET (offset
);
464 offset
= crtl
->outgoing_args_size
+ get_frame_size ();
465 #if !STACK_GROWS_DOWNWARD
470 if (to
== STACK_POINTER_REGNUM
)
472 else if (from
== STACK_POINTER_REGNUM
)
480 /* Return nonzero if the use of X+OFFSET as an address in a MEM with SIZE
481 bytes can cause a trap. MODE is the mode of the MEM (not that of X) and
482 UNALIGNED_MEMS controls whether nonzero is returned for unaligned memory
483 references on strict alignment machines. */
486 rtx_addr_can_trap_p_1 (const_rtx x
, HOST_WIDE_INT offset
, HOST_WIDE_INT size
,
487 machine_mode mode
, bool unaligned_mems
)
489 enum rtx_code code
= GET_CODE (x
);
491 /* The offset must be a multiple of the mode size if we are considering
492 unaligned memory references on strict alignment machines. */
493 if (STRICT_ALIGNMENT
&& unaligned_mems
&& GET_MODE_SIZE (mode
) != 0)
495 HOST_WIDE_INT actual_offset
= offset
;
497 #ifdef SPARC_STACK_BOUNDARY_HACK
498 /* ??? The SPARC port may claim a STACK_BOUNDARY higher than
499 the real alignment of %sp. However, when it does this, the
500 alignment of %sp+STACK_POINTER_OFFSET is STACK_BOUNDARY. */
501 if (SPARC_STACK_BOUNDARY_HACK
502 && (x
== stack_pointer_rtx
|| x
== hard_frame_pointer_rtx
))
503 actual_offset
-= STACK_POINTER_OFFSET
;
506 if (actual_offset
% GET_MODE_SIZE (mode
) != 0)
513 if (SYMBOL_REF_WEAK (x
))
515 if (!CONSTANT_POOL_ADDRESS_P (x
))
518 HOST_WIDE_INT decl_size
;
523 size
= GET_MODE_SIZE (mode
);
527 /* If the size of the access or of the symbol is unknown,
529 decl
= SYMBOL_REF_DECL (x
);
531 /* Else check that the access is in bounds. TODO: restructure
532 expr_size/tree_expr_size/int_expr_size and just use the latter. */
535 else if (DECL_P (decl
) && DECL_SIZE_UNIT (decl
))
536 decl_size
= (tree_fits_shwi_p (DECL_SIZE_UNIT (decl
))
537 ? tree_to_shwi (DECL_SIZE_UNIT (decl
))
539 else if (TREE_CODE (decl
) == STRING_CST
)
540 decl_size
= TREE_STRING_LENGTH (decl
);
541 else if (TYPE_SIZE_UNIT (TREE_TYPE (decl
)))
542 decl_size
= int_size_in_bytes (TREE_TYPE (decl
));
546 return (decl_size
<= 0 ? offset
!= 0 : offset
+ size
> decl_size
);
555 /* Stack references are assumed not to trap, but we need to deal with
556 nonsensical offsets. */
557 if (x
== frame_pointer_rtx
|| x
== hard_frame_pointer_rtx
558 || x
== stack_pointer_rtx
559 /* The arg pointer varies if it is not a fixed register. */
560 || (x
== arg_pointer_rtx
&& fixed_regs
[ARG_POINTER_REGNUM
]))
563 HOST_WIDE_INT red_zone_size
= RED_ZONE_SIZE
;
565 HOST_WIDE_INT red_zone_size
= 0;
567 HOST_WIDE_INT stack_boundary
= PREFERRED_STACK_BOUNDARY
569 HOST_WIDE_INT low_bound
, high_bound
;
572 size
= GET_MODE_SIZE (mode
);
574 if (x
== frame_pointer_rtx
)
576 if (FRAME_GROWS_DOWNWARD
)
578 high_bound
= STARTING_FRAME_OFFSET
;
579 low_bound
= high_bound
- get_frame_size ();
583 low_bound
= STARTING_FRAME_OFFSET
;
584 high_bound
= low_bound
+ get_frame_size ();
587 else if (x
== hard_frame_pointer_rtx
)
589 HOST_WIDE_INT sp_offset
590 = get_initial_register_offset (STACK_POINTER_REGNUM
,
591 HARD_FRAME_POINTER_REGNUM
);
592 HOST_WIDE_INT ap_offset
593 = get_initial_register_offset (ARG_POINTER_REGNUM
,
594 HARD_FRAME_POINTER_REGNUM
);
596 #if STACK_GROWS_DOWNWARD
597 low_bound
= sp_offset
- red_zone_size
- stack_boundary
;
598 high_bound
= ap_offset
599 + FIRST_PARM_OFFSET (current_function_decl
)
600 #if !ARGS_GROW_DOWNWARD
605 high_bound
= sp_offset
+ red_zone_size
+ stack_boundary
;
606 low_bound
= ap_offset
607 + FIRST_PARM_OFFSET (current_function_decl
)
608 #if ARGS_GROW_DOWNWARD
614 else if (x
== stack_pointer_rtx
)
616 HOST_WIDE_INT ap_offset
617 = get_initial_register_offset (ARG_POINTER_REGNUM
,
618 STACK_POINTER_REGNUM
);
620 #if STACK_GROWS_DOWNWARD
621 low_bound
= - red_zone_size
- stack_boundary
;
622 high_bound
= ap_offset
623 + FIRST_PARM_OFFSET (current_function_decl
)
624 #if !ARGS_GROW_DOWNWARD
629 high_bound
= red_zone_size
+ stack_boundary
;
630 low_bound
= ap_offset
631 + FIRST_PARM_OFFSET (current_function_decl
)
632 #if ARGS_GROW_DOWNWARD
640 /* We assume that accesses are safe to at least the
642 Examples are varargs and __builtin_return_address. */
643 #if ARGS_GROW_DOWNWARD
644 high_bound
= FIRST_PARM_OFFSET (current_function_decl
)
646 low_bound
= FIRST_PARM_OFFSET (current_function_decl
)
647 - crtl
->args
.size
- stack_boundary
;
649 low_bound
= FIRST_PARM_OFFSET (current_function_decl
)
651 high_bound
= FIRST_PARM_OFFSET (current_function_decl
)
652 + crtl
->args
.size
+ stack_boundary
;
656 if (offset
>= low_bound
&& offset
<= high_bound
- size
)
660 /* All of the virtual frame registers are stack references. */
661 if (REGNO (x
) >= FIRST_VIRTUAL_REGISTER
662 && REGNO (x
) <= LAST_VIRTUAL_REGISTER
)
667 return rtx_addr_can_trap_p_1 (XEXP (x
, 0), offset
, size
,
668 mode
, unaligned_mems
);
671 /* An address is assumed not to trap if:
672 - it is the pic register plus a constant. */
673 if (XEXP (x
, 0) == pic_offset_table_rtx
&& CONSTANT_P (XEXP (x
, 1)))
676 /* - or it is an address that can't trap plus a constant integer. */
677 if (CONST_INT_P (XEXP (x
, 1))
678 && !rtx_addr_can_trap_p_1 (XEXP (x
, 0), offset
+ INTVAL (XEXP (x
, 1)),
679 size
, mode
, unaligned_mems
))
686 return rtx_addr_can_trap_p_1 (XEXP (x
, 1), offset
, size
,
687 mode
, unaligned_mems
);
694 return rtx_addr_can_trap_p_1 (XEXP (x
, 0), offset
, size
,
695 mode
, unaligned_mems
);
701 /* If it isn't one of the case above, it can cause a trap. */
705 /* Return nonzero if the use of X as an address in a MEM can cause a trap. */
708 rtx_addr_can_trap_p (const_rtx x
)
710 return rtx_addr_can_trap_p_1 (x
, 0, 0, VOIDmode
, false);
713 /* Return true if X is an address that is known to not be zero. */
716 nonzero_address_p (const_rtx x
)
718 const enum rtx_code code
= GET_CODE (x
);
723 return flag_delete_null_pointer_checks
&& !SYMBOL_REF_WEAK (x
);
729 /* As in rtx_varies_p, we have to use the actual rtx, not reg number. */
730 if (x
== frame_pointer_rtx
|| x
== hard_frame_pointer_rtx
731 || x
== stack_pointer_rtx
732 || (x
== arg_pointer_rtx
&& fixed_regs
[ARG_POINTER_REGNUM
]))
734 /* All of the virtual frame registers are stack references. */
735 if (REGNO (x
) >= FIRST_VIRTUAL_REGISTER
736 && REGNO (x
) <= LAST_VIRTUAL_REGISTER
)
741 return nonzero_address_p (XEXP (x
, 0));
744 /* Handle PIC references. */
745 if (XEXP (x
, 0) == pic_offset_table_rtx
746 && CONSTANT_P (XEXP (x
, 1)))
751 /* Similar to the above; allow positive offsets. Further, since
752 auto-inc is only allowed in memories, the register must be a
754 if (CONST_INT_P (XEXP (x
, 1))
755 && INTVAL (XEXP (x
, 1)) > 0)
757 return nonzero_address_p (XEXP (x
, 0));
760 /* Similarly. Further, the offset is always positive. */
767 return nonzero_address_p (XEXP (x
, 0));
770 return nonzero_address_p (XEXP (x
, 1));
776 /* If it isn't one of the case above, might be zero. */
780 /* Return 1 if X refers to a memory location whose address
781 cannot be compared reliably with constant addresses,
782 or if X refers to a BLKmode memory object.
783 FOR_ALIAS is nonzero if we are called from alias analysis; if it is
784 zero, we are slightly more conservative. */
787 rtx_addr_varies_p (const_rtx x
, bool for_alias
)
798 return GET_MODE (x
) == BLKmode
|| rtx_varies_p (XEXP (x
, 0), for_alias
);
800 fmt
= GET_RTX_FORMAT (code
);
801 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
804 if (rtx_addr_varies_p (XEXP (x
, i
), for_alias
))
807 else if (fmt
[i
] == 'E')
810 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
811 if (rtx_addr_varies_p (XVECEXP (x
, i
, j
), for_alias
))
817 /* Return the CALL in X if there is one. */
820 get_call_rtx_from (rtx x
)
824 if (GET_CODE (x
) == PARALLEL
)
825 x
= XVECEXP (x
, 0, 0);
826 if (GET_CODE (x
) == SET
)
828 if (GET_CODE (x
) == CALL
&& MEM_P (XEXP (x
, 0)))
833 /* Return the value of the integer term in X, if one is apparent;
835 Only obvious integer terms are detected.
836 This is used in cse.c with the `related_value' field. */
839 get_integer_term (const_rtx x
)
841 if (GET_CODE (x
) == CONST
)
844 if (GET_CODE (x
) == MINUS
845 && CONST_INT_P (XEXP (x
, 1)))
846 return - INTVAL (XEXP (x
, 1));
847 if (GET_CODE (x
) == PLUS
848 && CONST_INT_P (XEXP (x
, 1)))
849 return INTVAL (XEXP (x
, 1));
853 /* If X is a constant, return the value sans apparent integer term;
855 Only obvious integer terms are detected. */
858 get_related_value (const_rtx x
)
860 if (GET_CODE (x
) != CONST
)
863 if (GET_CODE (x
) == PLUS
864 && CONST_INT_P (XEXP (x
, 1)))
866 else if (GET_CODE (x
) == MINUS
867 && CONST_INT_P (XEXP (x
, 1)))
872 /* Return true if SYMBOL is a SYMBOL_REF and OFFSET + SYMBOL points
873 to somewhere in the same object or object_block as SYMBOL. */
876 offset_within_block_p (const_rtx symbol
, HOST_WIDE_INT offset
)
880 if (GET_CODE (symbol
) != SYMBOL_REF
)
888 if (CONSTANT_POOL_ADDRESS_P (symbol
)
889 && offset
< (int) GET_MODE_SIZE (get_pool_mode (symbol
)))
892 decl
= SYMBOL_REF_DECL (symbol
);
893 if (decl
&& offset
< int_size_in_bytes (TREE_TYPE (decl
)))
897 if (SYMBOL_REF_HAS_BLOCK_INFO_P (symbol
)
898 && SYMBOL_REF_BLOCK (symbol
)
899 && SYMBOL_REF_BLOCK_OFFSET (symbol
) >= 0
900 && ((unsigned HOST_WIDE_INT
) offset
+ SYMBOL_REF_BLOCK_OFFSET (symbol
)
901 < (unsigned HOST_WIDE_INT
) SYMBOL_REF_BLOCK (symbol
)->size
))
907 /* Split X into a base and a constant offset, storing them in *BASE_OUT
908 and *OFFSET_OUT respectively. */
911 split_const (rtx x
, rtx
*base_out
, rtx
*offset_out
)
913 if (GET_CODE (x
) == CONST
)
916 if (GET_CODE (x
) == PLUS
&& CONST_INT_P (XEXP (x
, 1)))
918 *base_out
= XEXP (x
, 0);
919 *offset_out
= XEXP (x
, 1);
924 *offset_out
= const0_rtx
;
927 /* Return the number of places FIND appears within X. If COUNT_DEST is
928 zero, we do not count occurrences inside the destination of a SET. */
931 count_occurrences (const_rtx x
, const_rtx find
, int count_dest
)
935 const char *format_ptr
;
954 count
= count_occurrences (XEXP (x
, 0), find
, count_dest
);
956 count
+= count_occurrences (XEXP (x
, 1), find
, count_dest
);
960 if (MEM_P (find
) && rtx_equal_p (x
, find
))
965 if (SET_DEST (x
) == find
&& ! count_dest
)
966 return count_occurrences (SET_SRC (x
), find
, count_dest
);
973 format_ptr
= GET_RTX_FORMAT (code
);
976 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++)
978 switch (*format_ptr
++)
981 count
+= count_occurrences (XEXP (x
, i
), find
, count_dest
);
985 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
986 count
+= count_occurrences (XVECEXP (x
, i
, j
), find
, count_dest
);
994 /* Return TRUE if OP is a register or subreg of a register that
995 holds an unsigned quantity. Otherwise, return FALSE. */
998 unsigned_reg_p (rtx op
)
1002 && TYPE_UNSIGNED (TREE_TYPE (REG_EXPR (op
))))
1005 if (GET_CODE (op
) == SUBREG
1006 && SUBREG_PROMOTED_SIGN (op
))
1013 /* Nonzero if register REG appears somewhere within IN.
1014 Also works if REG is not a register; in this case it checks
1015 for a subexpression of IN that is Lisp "equal" to REG. */
1018 reg_mentioned_p (const_rtx reg
, const_rtx in
)
1030 if (GET_CODE (in
) == LABEL_REF
)
1031 return reg
== LABEL_REF_LABEL (in
);
1033 code
= GET_CODE (in
);
1037 /* Compare registers by number. */
1039 return REG_P (reg
) && REGNO (in
) == REGNO (reg
);
1041 /* These codes have no constituent expressions
1049 /* These are kept unique for a given value. */
1056 if (GET_CODE (reg
) == code
&& rtx_equal_p (reg
, in
))
1059 fmt
= GET_RTX_FORMAT (code
);
1061 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
1066 for (j
= XVECLEN (in
, i
) - 1; j
>= 0; j
--)
1067 if (reg_mentioned_p (reg
, XVECEXP (in
, i
, j
)))
1070 else if (fmt
[i
] == 'e'
1071 && reg_mentioned_p (reg
, XEXP (in
, i
)))
1077 /* Return 1 if in between BEG and END, exclusive of BEG and END, there is
1078 no CODE_LABEL insn. */
1081 no_labels_between_p (const rtx_insn
*beg
, const rtx_insn
*end
)
1086 for (p
= NEXT_INSN (beg
); p
!= end
; p
= NEXT_INSN (p
))
1092 /* Nonzero if register REG is used in an insn between
1093 FROM_INSN and TO_INSN (exclusive of those two). */
1096 reg_used_between_p (const_rtx reg
, const rtx_insn
*from_insn
,
1097 const rtx_insn
*to_insn
)
1101 if (from_insn
== to_insn
)
1104 for (insn
= NEXT_INSN (from_insn
); insn
!= to_insn
; insn
= NEXT_INSN (insn
))
1105 if (NONDEBUG_INSN_P (insn
)
1106 && (reg_overlap_mentioned_p (reg
, PATTERN (insn
))
1107 || (CALL_P (insn
) && find_reg_fusage (insn
, USE
, reg
))))
1112 /* Nonzero if the old value of X, a register, is referenced in BODY. If X
1113 is entirely replaced by a new value and the only use is as a SET_DEST,
1114 we do not consider it a reference. */
1117 reg_referenced_p (const_rtx x
, const_rtx body
)
1121 switch (GET_CODE (body
))
1124 if (reg_overlap_mentioned_p (x
, SET_SRC (body
)))
1127 /* If the destination is anything other than CC0, PC, a REG or a SUBREG
1128 of a REG that occupies all of the REG, the insn references X if
1129 it is mentioned in the destination. */
1130 if (GET_CODE (SET_DEST (body
)) != CC0
1131 && GET_CODE (SET_DEST (body
)) != PC
1132 && !REG_P (SET_DEST (body
))
1133 && ! (GET_CODE (SET_DEST (body
)) == SUBREG
1134 && REG_P (SUBREG_REG (SET_DEST (body
)))
1135 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (body
))))
1136 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
1137 == ((GET_MODE_SIZE (GET_MODE (SET_DEST (body
)))
1138 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)))
1139 && reg_overlap_mentioned_p (x
, SET_DEST (body
)))
1144 for (i
= ASM_OPERANDS_INPUT_LENGTH (body
) - 1; i
>= 0; i
--)
1145 if (reg_overlap_mentioned_p (x
, ASM_OPERANDS_INPUT (body
, i
)))
1152 return reg_overlap_mentioned_p (x
, body
);
1155 return reg_overlap_mentioned_p (x
, TRAP_CONDITION (body
));
1158 return reg_overlap_mentioned_p (x
, XEXP (body
, 0));
1161 case UNSPEC_VOLATILE
:
1162 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; i
--)
1163 if (reg_overlap_mentioned_p (x
, XVECEXP (body
, 0, i
)))
1168 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; i
--)
1169 if (reg_referenced_p (x
, XVECEXP (body
, 0, i
)))
1174 if (MEM_P (XEXP (body
, 0)))
1175 if (reg_overlap_mentioned_p (x
, XEXP (XEXP (body
, 0), 0)))
1180 if (reg_overlap_mentioned_p (x
, COND_EXEC_TEST (body
)))
1182 return reg_referenced_p (x
, COND_EXEC_CODE (body
));
1189 /* Nonzero if register REG is set or clobbered in an insn between
1190 FROM_INSN and TO_INSN (exclusive of those two). */
1193 reg_set_between_p (const_rtx reg
, const rtx_insn
*from_insn
,
1194 const rtx_insn
*to_insn
)
1196 const rtx_insn
*insn
;
1198 if (from_insn
== to_insn
)
1201 for (insn
= NEXT_INSN (from_insn
); insn
!= to_insn
; insn
= NEXT_INSN (insn
))
1202 if (INSN_P (insn
) && reg_set_p (reg
, insn
))
1207 /* Return true if REG is set or clobbered inside INSN. */
1210 reg_set_p (const_rtx reg
, const_rtx insn
)
1212 /* After delay slot handling, call and branch insns might be in a
1213 sequence. Check all the elements there. */
1214 if (INSN_P (insn
) && GET_CODE (PATTERN (insn
)) == SEQUENCE
)
1216 for (int i
= 0; i
< XVECLEN (PATTERN (insn
), 0); ++i
)
1217 if (reg_set_p (reg
, XVECEXP (PATTERN (insn
), 0, i
)))
1223 /* We can be passed an insn or part of one. If we are passed an insn,
1224 check if a side-effect of the insn clobbers REG. */
1226 && (FIND_REG_INC_NOTE (insn
, reg
)
1229 && REGNO (reg
) < FIRST_PSEUDO_REGISTER
1230 && overlaps_hard_reg_set_p (regs_invalidated_by_call
,
1231 GET_MODE (reg
), REGNO (reg
)))
1233 || find_reg_fusage (insn
, CLOBBER
, reg
)))))
1236 return set_of (reg
, insn
) != NULL_RTX
;
1239 /* Similar to reg_set_between_p, but check all registers in X. Return 0
1240 only if none of them are modified between START and END. Return 1 if
1241 X contains a MEM; this routine does use memory aliasing. */
1244 modified_between_p (const_rtx x
, const rtx_insn
*start
, const rtx_insn
*end
)
1246 const enum rtx_code code
= GET_CODE (x
);
1267 if (modified_between_p (XEXP (x
, 0), start
, end
))
1269 if (MEM_READONLY_P (x
))
1271 for (insn
= NEXT_INSN (start
); insn
!= end
; insn
= NEXT_INSN (insn
))
1272 if (memory_modified_in_insn_p (x
, insn
))
1278 return reg_set_between_p (x
, start
, end
);
1284 fmt
= GET_RTX_FORMAT (code
);
1285 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
1287 if (fmt
[i
] == 'e' && modified_between_p (XEXP (x
, i
), start
, end
))
1290 else if (fmt
[i
] == 'E')
1291 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
1292 if (modified_between_p (XVECEXP (x
, i
, j
), start
, end
))
1299 /* Similar to reg_set_p, but check all registers in X. Return 0 only if none
1300 of them are modified in INSN. Return 1 if X contains a MEM; this routine
1301 does use memory aliasing. */
1304 modified_in_p (const_rtx x
, const_rtx insn
)
1306 const enum rtx_code code
= GET_CODE (x
);
1323 if (modified_in_p (XEXP (x
, 0), insn
))
1325 if (MEM_READONLY_P (x
))
1327 if (memory_modified_in_insn_p (x
, insn
))
1333 return reg_set_p (x
, insn
);
1339 fmt
= GET_RTX_FORMAT (code
);
1340 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
1342 if (fmt
[i
] == 'e' && modified_in_p (XEXP (x
, i
), insn
))
1345 else if (fmt
[i
] == 'E')
1346 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
1347 if (modified_in_p (XVECEXP (x
, i
, j
), insn
))
1354 /* Helper function for set_of. */
1362 set_of_1 (rtx x
, const_rtx pat
, void *data1
)
1364 struct set_of_data
*const data
= (struct set_of_data
*) (data1
);
1365 if (rtx_equal_p (x
, data
->pat
)
1366 || (!MEM_P (x
) && reg_overlap_mentioned_p (data
->pat
, x
)))
1370 /* Give an INSN, return a SET or CLOBBER expression that does modify PAT
1371 (either directly or via STRICT_LOW_PART and similar modifiers). */
1373 set_of (const_rtx pat
, const_rtx insn
)
1375 struct set_of_data data
;
1376 data
.found
= NULL_RTX
;
1378 note_stores (INSN_P (insn
) ? PATTERN (insn
) : insn
, set_of_1
, &data
);
1382 /* Add all hard register in X to *PSET. */
1384 find_all_hard_regs (const_rtx x
, HARD_REG_SET
*pset
)
1386 subrtx_iterator::array_type array
;
1387 FOR_EACH_SUBRTX (iter
, array
, x
, NONCONST
)
1389 const_rtx x
= *iter
;
1390 if (REG_P (x
) && REGNO (x
) < FIRST_PSEUDO_REGISTER
)
1391 add_to_hard_reg_set (pset
, GET_MODE (x
), REGNO (x
));
1395 /* This function, called through note_stores, collects sets and
1396 clobbers of hard registers in a HARD_REG_SET, which is pointed to
1399 record_hard_reg_sets (rtx x
, const_rtx pat ATTRIBUTE_UNUSED
, void *data
)
1401 HARD_REG_SET
*pset
= (HARD_REG_SET
*)data
;
1402 if (REG_P (x
) && HARD_REGISTER_P (x
))
1403 add_to_hard_reg_set (pset
, GET_MODE (x
), REGNO (x
));
1406 /* Examine INSN, and compute the set of hard registers written by it.
1407 Store it in *PSET. Should only be called after reload. */
1409 find_all_hard_reg_sets (const rtx_insn
*insn
, HARD_REG_SET
*pset
, bool implicit
)
1413 CLEAR_HARD_REG_SET (*pset
);
1414 note_stores (PATTERN (insn
), record_hard_reg_sets
, pset
);
1418 IOR_HARD_REG_SET (*pset
, call_used_reg_set
);
1420 for (link
= CALL_INSN_FUNCTION_USAGE (insn
); link
; link
= XEXP (link
, 1))
1421 record_hard_reg_sets (XEXP (link
, 0), NULL
, pset
);
1423 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
1424 if (REG_NOTE_KIND (link
) == REG_INC
)
1425 record_hard_reg_sets (XEXP (link
, 0), NULL
, pset
);
1428 /* Like record_hard_reg_sets, but called through note_uses. */
1430 record_hard_reg_uses (rtx
*px
, void *data
)
1432 find_all_hard_regs (*px
, (HARD_REG_SET
*) data
);
1435 /* Given an INSN, return a SET expression if this insn has only a single SET.
1436 It may also have CLOBBERs, USEs, or SET whose output
1437 will not be used, which we ignore. */
1440 single_set_2 (const rtx_insn
*insn
, const_rtx pat
)
1443 int set_verified
= 1;
1446 if (GET_CODE (pat
) == PARALLEL
)
1448 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
1450 rtx sub
= XVECEXP (pat
, 0, i
);
1451 switch (GET_CODE (sub
))
1458 /* We can consider insns having multiple sets, where all
1459 but one are dead as single set insns. In common case
1460 only single set is present in the pattern so we want
1461 to avoid checking for REG_UNUSED notes unless necessary.
1463 When we reach set first time, we just expect this is
1464 the single set we are looking for and only when more
1465 sets are found in the insn, we check them. */
1468 if (find_reg_note (insn
, REG_UNUSED
, SET_DEST (set
))
1469 && !side_effects_p (set
))
1475 set
= sub
, set_verified
= 0;
1476 else if (!find_reg_note (insn
, REG_UNUSED
, SET_DEST (sub
))
1477 || side_effects_p (sub
))
1489 /* Given an INSN, return nonzero if it has more than one SET, else return
1493 multiple_sets (const_rtx insn
)
1498 /* INSN must be an insn. */
1499 if (! INSN_P (insn
))
1502 /* Only a PARALLEL can have multiple SETs. */
1503 if (GET_CODE (PATTERN (insn
)) == PARALLEL
)
1505 for (i
= 0, found
= 0; i
< XVECLEN (PATTERN (insn
), 0); i
++)
1506 if (GET_CODE (XVECEXP (PATTERN (insn
), 0, i
)) == SET
)
1508 /* If we have already found a SET, then return now. */
1516 /* Either zero or one SET. */
1520 /* Return nonzero if the destination of SET equals the source
1521 and there are no side effects. */
1524 set_noop_p (const_rtx set
)
1526 rtx src
= SET_SRC (set
);
1527 rtx dst
= SET_DEST (set
);
1529 if (dst
== pc_rtx
&& src
== pc_rtx
)
1532 if (MEM_P (dst
) && MEM_P (src
))
1533 return rtx_equal_p (dst
, src
) && !side_effects_p (dst
);
1535 if (GET_CODE (dst
) == ZERO_EXTRACT
)
1536 return rtx_equal_p (XEXP (dst
, 0), src
)
1537 && !BITS_BIG_ENDIAN
&& XEXP (dst
, 2) == const0_rtx
1538 && !side_effects_p (src
);
1540 if (GET_CODE (dst
) == STRICT_LOW_PART
)
1541 dst
= XEXP (dst
, 0);
1543 if (GET_CODE (src
) == SUBREG
&& GET_CODE (dst
) == SUBREG
)
1545 if (SUBREG_BYTE (src
) != SUBREG_BYTE (dst
))
1547 src
= SUBREG_REG (src
);
1548 dst
= SUBREG_REG (dst
);
1551 /* It is a NOOP if destination overlaps with selected src vector
1553 if (GET_CODE (src
) == VEC_SELECT
1554 && REG_P (XEXP (src
, 0)) && REG_P (dst
)
1555 && HARD_REGISTER_P (XEXP (src
, 0))
1556 && HARD_REGISTER_P (dst
))
1559 rtx par
= XEXP (src
, 1);
1560 rtx src0
= XEXP (src
, 0);
1561 int c0
= INTVAL (XVECEXP (par
, 0, 0));
1562 HOST_WIDE_INT offset
= GET_MODE_UNIT_SIZE (GET_MODE (src0
)) * c0
;
1564 for (i
= 1; i
< XVECLEN (par
, 0); i
++)
1565 if (INTVAL (XVECEXP (par
, 0, i
)) != c0
+ i
)
1568 simplify_subreg_regno (REGNO (src0
), GET_MODE (src0
),
1569 offset
, GET_MODE (dst
)) == (int) REGNO (dst
);
1572 return (REG_P (src
) && REG_P (dst
)
1573 && REGNO (src
) == REGNO (dst
));
1576 /* Return nonzero if an insn consists only of SETs, each of which only sets a
1580 noop_move_p (const rtx_insn
*insn
)
1582 rtx pat
= PATTERN (insn
);
1584 if (INSN_CODE (insn
) == NOOP_MOVE_INSN_CODE
)
1587 /* Insns carrying these notes are useful later on. */
1588 if (find_reg_note (insn
, REG_EQUAL
, NULL_RTX
))
1591 /* Check the code to be executed for COND_EXEC. */
1592 if (GET_CODE (pat
) == COND_EXEC
)
1593 pat
= COND_EXEC_CODE (pat
);
1595 if (GET_CODE (pat
) == SET
&& set_noop_p (pat
))
1598 if (GET_CODE (pat
) == PARALLEL
)
1601 /* If nothing but SETs of registers to themselves,
1602 this insn can also be deleted. */
1603 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
1605 rtx tem
= XVECEXP (pat
, 0, i
);
1607 if (GET_CODE (tem
) == USE
1608 || GET_CODE (tem
) == CLOBBER
)
1611 if (GET_CODE (tem
) != SET
|| ! set_noop_p (tem
))
1621 /* Return nonzero if register in range [REGNO, ENDREGNO)
1622 appears either explicitly or implicitly in X
1623 other than being stored into.
1625 References contained within the substructure at LOC do not count.
1626 LOC may be zero, meaning don't ignore anything. */
1629 refers_to_regno_p (unsigned int regno
, unsigned int endregno
, const_rtx x
,
1633 unsigned int x_regno
;
1638 /* The contents of a REG_NONNEG note is always zero, so we must come here
1639 upon repeat in case the last REG_NOTE is a REG_NONNEG note. */
1643 code
= GET_CODE (x
);
1648 x_regno
= REGNO (x
);
1650 /* If we modifying the stack, frame, or argument pointer, it will
1651 clobber a virtual register. In fact, we could be more precise,
1652 but it isn't worth it. */
1653 if ((x_regno
== STACK_POINTER_REGNUM
1654 || (FRAME_POINTER_REGNUM
!= ARG_POINTER_REGNUM
1655 && x_regno
== ARG_POINTER_REGNUM
)
1656 || x_regno
== FRAME_POINTER_REGNUM
)
1657 && regno
>= FIRST_VIRTUAL_REGISTER
&& regno
<= LAST_VIRTUAL_REGISTER
)
1660 return endregno
> x_regno
&& regno
< END_REGNO (x
);
1663 /* If this is a SUBREG of a hard reg, we can see exactly which
1664 registers are being modified. Otherwise, handle normally. */
1665 if (REG_P (SUBREG_REG (x
))
1666 && REGNO (SUBREG_REG (x
)) < FIRST_PSEUDO_REGISTER
)
1668 unsigned int inner_regno
= subreg_regno (x
);
1669 unsigned int inner_endregno
1670 = inner_regno
+ (inner_regno
< FIRST_PSEUDO_REGISTER
1671 ? subreg_nregs (x
) : 1);
1673 return endregno
> inner_regno
&& regno
< inner_endregno
;
1679 if (&SET_DEST (x
) != loc
1680 /* Note setting a SUBREG counts as referring to the REG it is in for
1681 a pseudo but not for hard registers since we can
1682 treat each word individually. */
1683 && ((GET_CODE (SET_DEST (x
)) == SUBREG
1684 && loc
!= &SUBREG_REG (SET_DEST (x
))
1685 && REG_P (SUBREG_REG (SET_DEST (x
)))
1686 && REGNO (SUBREG_REG (SET_DEST (x
))) >= FIRST_PSEUDO_REGISTER
1687 && refers_to_regno_p (regno
, endregno
,
1688 SUBREG_REG (SET_DEST (x
)), loc
))
1689 || (!REG_P (SET_DEST (x
))
1690 && refers_to_regno_p (regno
, endregno
, SET_DEST (x
), loc
))))
1693 if (code
== CLOBBER
|| loc
== &SET_SRC (x
))
1702 /* X does not match, so try its subexpressions. */
1704 fmt
= GET_RTX_FORMAT (code
);
1705 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
1707 if (fmt
[i
] == 'e' && loc
!= &XEXP (x
, i
))
1715 if (refers_to_regno_p (regno
, endregno
, XEXP (x
, i
), loc
))
1718 else if (fmt
[i
] == 'E')
1721 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
1722 if (loc
!= &XVECEXP (x
, i
, j
)
1723 && refers_to_regno_p (regno
, endregno
, XVECEXP (x
, i
, j
), loc
))
1730 /* Nonzero if modifying X will affect IN. If X is a register or a SUBREG,
1731 we check if any register number in X conflicts with the relevant register
1732 numbers. If X is a constant, return 0. If X is a MEM, return 1 iff IN
1733 contains a MEM (we don't bother checking for memory addresses that can't
1734 conflict because we expect this to be a rare case. */
1737 reg_overlap_mentioned_p (const_rtx x
, const_rtx in
)
1739 unsigned int regno
, endregno
;
1741 /* If either argument is a constant, then modifying X can not
1742 affect IN. Here we look at IN, we can profitably combine
1743 CONSTANT_P (x) with the switch statement below. */
1744 if (CONSTANT_P (in
))
1748 switch (GET_CODE (x
))
1750 case STRICT_LOW_PART
:
1753 /* Overly conservative. */
1758 regno
= REGNO (SUBREG_REG (x
));
1759 if (regno
< FIRST_PSEUDO_REGISTER
)
1760 regno
= subreg_regno (x
);
1761 endregno
= regno
+ (regno
< FIRST_PSEUDO_REGISTER
1762 ? subreg_nregs (x
) : 1);
1767 endregno
= END_REGNO (x
);
1769 return refers_to_regno_p (regno
, endregno
, in
, (rtx
*) 0);
1779 fmt
= GET_RTX_FORMAT (GET_CODE (in
));
1780 for (i
= GET_RTX_LENGTH (GET_CODE (in
)) - 1; i
>= 0; i
--)
1783 if (reg_overlap_mentioned_p (x
, XEXP (in
, i
)))
1786 else if (fmt
[i
] == 'E')
1789 for (j
= XVECLEN (in
, i
) - 1; j
>= 0; --j
)
1790 if (reg_overlap_mentioned_p (x
, XVECEXP (in
, i
, j
)))
1800 return reg_mentioned_p (x
, in
);
1806 /* If any register in here refers to it we return true. */
1807 for (i
= XVECLEN (x
, 0) - 1; i
>= 0; i
--)
1808 if (XEXP (XVECEXP (x
, 0, i
), 0) != 0
1809 && reg_overlap_mentioned_p (XEXP (XVECEXP (x
, 0, i
), 0), in
))
1815 gcc_assert (CONSTANT_P (x
));
1820 /* Call FUN on each register or MEM that is stored into or clobbered by X.
1821 (X would be the pattern of an insn). DATA is an arbitrary pointer,
1822 ignored by note_stores, but passed to FUN.
1824 FUN receives three arguments:
1825 1. the REG, MEM, CC0 or PC being stored in or clobbered,
1826 2. the SET or CLOBBER rtx that does the store,
1827 3. the pointer DATA provided to note_stores.
1829 If the item being stored in or clobbered is a SUBREG of a hard register,
1830 the SUBREG will be passed. */
1833 note_stores (const_rtx x
, void (*fun
) (rtx
, const_rtx
, void *), void *data
)
1837 if (GET_CODE (x
) == COND_EXEC
)
1838 x
= COND_EXEC_CODE (x
);
1840 if (GET_CODE (x
) == SET
|| GET_CODE (x
) == CLOBBER
)
1842 rtx dest
= SET_DEST (x
);
1844 while ((GET_CODE (dest
) == SUBREG
1845 && (!REG_P (SUBREG_REG (dest
))
1846 || REGNO (SUBREG_REG (dest
)) >= FIRST_PSEUDO_REGISTER
))
1847 || GET_CODE (dest
) == ZERO_EXTRACT
1848 || GET_CODE (dest
) == STRICT_LOW_PART
)
1849 dest
= XEXP (dest
, 0);
1851 /* If we have a PARALLEL, SET_DEST is a list of EXPR_LIST expressions,
1852 each of whose first operand is a register. */
1853 if (GET_CODE (dest
) == PARALLEL
)
1855 for (i
= XVECLEN (dest
, 0) - 1; i
>= 0; i
--)
1856 if (XEXP (XVECEXP (dest
, 0, i
), 0) != 0)
1857 (*fun
) (XEXP (XVECEXP (dest
, 0, i
), 0), x
, data
);
1860 (*fun
) (dest
, x
, data
);
1863 else if (GET_CODE (x
) == PARALLEL
)
1864 for (i
= XVECLEN (x
, 0) - 1; i
>= 0; i
--)
1865 note_stores (XVECEXP (x
, 0, i
), fun
, data
);
1868 /* Like notes_stores, but call FUN for each expression that is being
1869 referenced in PBODY, a pointer to the PATTERN of an insn. We only call
1870 FUN for each expression, not any interior subexpressions. FUN receives a
1871 pointer to the expression and the DATA passed to this function.
1873 Note that this is not quite the same test as that done in reg_referenced_p
1874 since that considers something as being referenced if it is being
1875 partially set, while we do not. */
1878 note_uses (rtx
*pbody
, void (*fun
) (rtx
*, void *), void *data
)
1883 switch (GET_CODE (body
))
1886 (*fun
) (&COND_EXEC_TEST (body
), data
);
1887 note_uses (&COND_EXEC_CODE (body
), fun
, data
);
1891 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; i
--)
1892 note_uses (&XVECEXP (body
, 0, i
), fun
, data
);
1896 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; i
--)
1897 note_uses (&PATTERN (XVECEXP (body
, 0, i
)), fun
, data
);
1901 (*fun
) (&XEXP (body
, 0), data
);
1905 for (i
= ASM_OPERANDS_INPUT_LENGTH (body
) - 1; i
>= 0; i
--)
1906 (*fun
) (&ASM_OPERANDS_INPUT (body
, i
), data
);
1910 (*fun
) (&TRAP_CONDITION (body
), data
);
1914 (*fun
) (&XEXP (body
, 0), data
);
1918 case UNSPEC_VOLATILE
:
1919 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; i
--)
1920 (*fun
) (&XVECEXP (body
, 0, i
), data
);
1924 if (MEM_P (XEXP (body
, 0)))
1925 (*fun
) (&XEXP (XEXP (body
, 0), 0), data
);
1930 rtx dest
= SET_DEST (body
);
1932 /* For sets we replace everything in source plus registers in memory
1933 expression in store and operands of a ZERO_EXTRACT. */
1934 (*fun
) (&SET_SRC (body
), data
);
1936 if (GET_CODE (dest
) == ZERO_EXTRACT
)
1938 (*fun
) (&XEXP (dest
, 1), data
);
1939 (*fun
) (&XEXP (dest
, 2), data
);
1942 while (GET_CODE (dest
) == SUBREG
|| GET_CODE (dest
) == STRICT_LOW_PART
)
1943 dest
= XEXP (dest
, 0);
1946 (*fun
) (&XEXP (dest
, 0), data
);
1951 /* All the other possibilities never store. */
1952 (*fun
) (pbody
, data
);
1957 /* Return nonzero if X's old contents don't survive after INSN.
1958 This will be true if X is (cc0) or if X is a register and
1959 X dies in INSN or because INSN entirely sets X.
1961 "Entirely set" means set directly and not through a SUBREG, or
1962 ZERO_EXTRACT, so no trace of the old contents remains.
1963 Likewise, REG_INC does not count.
1965 REG may be a hard or pseudo reg. Renumbering is not taken into account,
1966 but for this use that makes no difference, since regs don't overlap
1967 during their lifetimes. Therefore, this function may be used
1968 at any time after deaths have been computed.
1970 If REG is a hard reg that occupies multiple machine registers, this
1971 function will only return 1 if each of those registers will be replaced
1975 dead_or_set_p (const_rtx insn
, const_rtx x
)
1977 unsigned int regno
, end_regno
;
1980 /* Can't use cc0_rtx below since this file is used by genattrtab.c. */
1981 if (GET_CODE (x
) == CC0
)
1984 gcc_assert (REG_P (x
));
1987 end_regno
= END_REGNO (x
);
1988 for (i
= regno
; i
< end_regno
; i
++)
1989 if (! dead_or_set_regno_p (insn
, i
))
1995 /* Return TRUE iff DEST is a register or subreg of a register and
1996 doesn't change the number of words of the inner register, and any
1997 part of the register is TEST_REGNO. */
2000 covers_regno_no_parallel_p (const_rtx dest
, unsigned int test_regno
)
2002 unsigned int regno
, endregno
;
2004 if (GET_CODE (dest
) == SUBREG
2005 && (((GET_MODE_SIZE (GET_MODE (dest
))
2006 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
)
2007 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest
)))
2008 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
)))
2009 dest
= SUBREG_REG (dest
);
2014 regno
= REGNO (dest
);
2015 endregno
= END_REGNO (dest
);
2016 return (test_regno
>= regno
&& test_regno
< endregno
);
2019 /* Like covers_regno_no_parallel_p, but also handles PARALLELs where
2020 any member matches the covers_regno_no_parallel_p criteria. */
2023 covers_regno_p (const_rtx dest
, unsigned int test_regno
)
2025 if (GET_CODE (dest
) == PARALLEL
)
2027 /* Some targets place small structures in registers for return
2028 values of functions, and those registers are wrapped in
2029 PARALLELs that we may see as the destination of a SET. */
2032 for (i
= XVECLEN (dest
, 0) - 1; i
>= 0; i
--)
2034 rtx inner
= XEXP (XVECEXP (dest
, 0, i
), 0);
2035 if (inner
!= NULL_RTX
2036 && covers_regno_no_parallel_p (inner
, test_regno
))
2043 return covers_regno_no_parallel_p (dest
, test_regno
);
2046 /* Utility function for dead_or_set_p to check an individual register. */
2049 dead_or_set_regno_p (const_rtx insn
, unsigned int test_regno
)
2053 /* See if there is a death note for something that includes TEST_REGNO. */
2054 if (find_regno_note (insn
, REG_DEAD
, test_regno
))
2058 && find_regno_fusage (insn
, CLOBBER
, test_regno
))
2061 pattern
= PATTERN (insn
);
2063 /* If a COND_EXEC is not executed, the value survives. */
2064 if (GET_CODE (pattern
) == COND_EXEC
)
2067 if (GET_CODE (pattern
) == SET
)
2068 return covers_regno_p (SET_DEST (pattern
), test_regno
);
2069 else if (GET_CODE (pattern
) == PARALLEL
)
2073 for (i
= XVECLEN (pattern
, 0) - 1; i
>= 0; i
--)
2075 rtx body
= XVECEXP (pattern
, 0, i
);
2077 if (GET_CODE (body
) == COND_EXEC
)
2078 body
= COND_EXEC_CODE (body
);
2080 if ((GET_CODE (body
) == SET
|| GET_CODE (body
) == CLOBBER
)
2081 && covers_regno_p (SET_DEST (body
), test_regno
))
2089 /* Return the reg-note of kind KIND in insn INSN, if there is one.
2090 If DATUM is nonzero, look for one whose datum is DATUM. */
2093 find_reg_note (const_rtx insn
, enum reg_note kind
, const_rtx datum
)
2097 gcc_checking_assert (insn
);
2099 /* Ignore anything that is not an INSN, JUMP_INSN or CALL_INSN. */
2100 if (! INSN_P (insn
))
2104 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
2105 if (REG_NOTE_KIND (link
) == kind
)
2110 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
2111 if (REG_NOTE_KIND (link
) == kind
&& datum
== XEXP (link
, 0))
2116 /* Return the reg-note of kind KIND in insn INSN which applies to register
2117 number REGNO, if any. Return 0 if there is no such reg-note. Note that
2118 the REGNO of this NOTE need not be REGNO if REGNO is a hard register;
2119 it might be the case that the note overlaps REGNO. */
2122 find_regno_note (const_rtx insn
, enum reg_note kind
, unsigned int regno
)
2126 /* Ignore anything that is not an INSN, JUMP_INSN or CALL_INSN. */
2127 if (! INSN_P (insn
))
2130 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
2131 if (REG_NOTE_KIND (link
) == kind
2132 /* Verify that it is a register, so that scratch and MEM won't cause a
2134 && REG_P (XEXP (link
, 0))
2135 && REGNO (XEXP (link
, 0)) <= regno
2136 && END_REGNO (XEXP (link
, 0)) > regno
)
2141 /* Return a REG_EQUIV or REG_EQUAL note if insn has only a single set and
2145 find_reg_equal_equiv_note (const_rtx insn
)
2152 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
2153 if (REG_NOTE_KIND (link
) == REG_EQUAL
2154 || REG_NOTE_KIND (link
) == REG_EQUIV
)
2156 /* FIXME: We should never have REG_EQUAL/REG_EQUIV notes on
2157 insns that have multiple sets. Checking single_set to
2158 make sure of this is not the proper check, as explained
2159 in the comment in set_unique_reg_note.
2161 This should be changed into an assert. */
2162 if (GET_CODE (PATTERN (insn
)) == PARALLEL
&& multiple_sets (insn
))
2169 /* Check whether INSN is a single_set whose source is known to be
2170 equivalent to a constant. Return that constant if so, otherwise
2174 find_constant_src (const rtx_insn
*insn
)
2178 set
= single_set (insn
);
2181 x
= avoid_constant_pool_reference (SET_SRC (set
));
2186 note
= find_reg_equal_equiv_note (insn
);
2187 if (note
&& CONSTANT_P (XEXP (note
, 0)))
2188 return XEXP (note
, 0);
2193 /* Return true if DATUM, or any overlap of DATUM, of kind CODE is found
2194 in the CALL_INSN_FUNCTION_USAGE information of INSN. */
2197 find_reg_fusage (const_rtx insn
, enum rtx_code code
, const_rtx datum
)
2199 /* If it's not a CALL_INSN, it can't possibly have a
2200 CALL_INSN_FUNCTION_USAGE field, so don't bother checking. */
2210 for (link
= CALL_INSN_FUNCTION_USAGE (insn
);
2212 link
= XEXP (link
, 1))
2213 if (GET_CODE (XEXP (link
, 0)) == code
2214 && rtx_equal_p (datum
, XEXP (XEXP (link
, 0), 0)))
2219 unsigned int regno
= REGNO (datum
);
2221 /* CALL_INSN_FUNCTION_USAGE information cannot contain references
2222 to pseudo registers, so don't bother checking. */
2224 if (regno
< FIRST_PSEUDO_REGISTER
)
2226 unsigned int end_regno
= END_REGNO (datum
);
2229 for (i
= regno
; i
< end_regno
; i
++)
2230 if (find_regno_fusage (insn
, code
, i
))
2238 /* Return true if REGNO, or any overlap of REGNO, of kind CODE is found
2239 in the CALL_INSN_FUNCTION_USAGE information of INSN. */
2242 find_regno_fusage (const_rtx insn
, enum rtx_code code
, unsigned int regno
)
2246 /* CALL_INSN_FUNCTION_USAGE information cannot contain references
2247 to pseudo registers, so don't bother checking. */
2249 if (regno
>= FIRST_PSEUDO_REGISTER
2253 for (link
= CALL_INSN_FUNCTION_USAGE (insn
); link
; link
= XEXP (link
, 1))
2257 if (GET_CODE (op
= XEXP (link
, 0)) == code
2258 && REG_P (reg
= XEXP (op
, 0))
2259 && REGNO (reg
) <= regno
2260 && END_REGNO (reg
) > regno
)
2268 /* Return true if KIND is an integer REG_NOTE. */
2271 int_reg_note_p (enum reg_note kind
)
2273 return kind
== REG_BR_PROB
;
2276 /* Allocate a register note with kind KIND and datum DATUM. LIST is
2277 stored as the pointer to the next register note. */
2280 alloc_reg_note (enum reg_note kind
, rtx datum
, rtx list
)
2284 gcc_checking_assert (!int_reg_note_p (kind
));
2289 case REG_LABEL_TARGET
:
2290 case REG_LABEL_OPERAND
:
2292 /* These types of register notes use an INSN_LIST rather than an
2293 EXPR_LIST, so that copying is done right and dumps look
2295 note
= alloc_INSN_LIST (datum
, list
);
2296 PUT_REG_NOTE_KIND (note
, kind
);
2300 note
= alloc_EXPR_LIST (kind
, datum
, list
);
2307 /* Add register note with kind KIND and datum DATUM to INSN. */
2310 add_reg_note (rtx insn
, enum reg_note kind
, rtx datum
)
2312 REG_NOTES (insn
) = alloc_reg_note (kind
, datum
, REG_NOTES (insn
));
2315 /* Add an integer register note with kind KIND and datum DATUM to INSN. */
2318 add_int_reg_note (rtx insn
, enum reg_note kind
, int datum
)
2320 gcc_checking_assert (int_reg_note_p (kind
));
2321 REG_NOTES (insn
) = gen_rtx_INT_LIST ((machine_mode
) kind
,
2322 datum
, REG_NOTES (insn
));
2325 /* Add a register note like NOTE to INSN. */
2328 add_shallow_copy_of_reg_note (rtx_insn
*insn
, rtx note
)
2330 if (GET_CODE (note
) == INT_LIST
)
2331 add_int_reg_note (insn
, REG_NOTE_KIND (note
), XINT (note
, 0));
2333 add_reg_note (insn
, REG_NOTE_KIND (note
), XEXP (note
, 0));
2336 /* Remove register note NOTE from the REG_NOTES of INSN. */
2339 remove_note (rtx insn
, const_rtx note
)
2343 if (note
== NULL_RTX
)
2346 if (REG_NOTES (insn
) == note
)
2347 REG_NOTES (insn
) = XEXP (note
, 1);
2349 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
2350 if (XEXP (link
, 1) == note
)
2352 XEXP (link
, 1) = XEXP (note
, 1);
2356 switch (REG_NOTE_KIND (note
))
2360 df_notes_rescan (as_a
<rtx_insn
*> (insn
));
2367 /* Remove REG_EQUAL and/or REG_EQUIV notes if INSN has such notes. */
2370 remove_reg_equal_equiv_notes (rtx_insn
*insn
)
2374 loc
= ®_NOTES (insn
);
2377 enum reg_note kind
= REG_NOTE_KIND (*loc
);
2378 if (kind
== REG_EQUAL
|| kind
== REG_EQUIV
)
2379 *loc
= XEXP (*loc
, 1);
2381 loc
= &XEXP (*loc
, 1);
2385 /* Remove all REG_EQUAL and REG_EQUIV notes referring to REGNO. */
2388 remove_reg_equal_equiv_notes_for_regno (unsigned int regno
)
2395 /* This loop is a little tricky. We cannot just go down the chain because
2396 it is being modified by some actions in the loop. So we just iterate
2397 over the head. We plan to drain the list anyway. */
2398 while ((eq_use
= DF_REG_EQ_USE_CHAIN (regno
)) != NULL
)
2400 rtx_insn
*insn
= DF_REF_INSN (eq_use
);
2401 rtx note
= find_reg_equal_equiv_note (insn
);
2403 /* This assert is generally triggered when someone deletes a REG_EQUAL
2404 or REG_EQUIV note by hacking the list manually rather than calling
2408 remove_note (insn
, note
);
2412 /* Search LISTP (an EXPR_LIST) for an entry whose first operand is NODE and
2413 return 1 if it is found. A simple equality test is used to determine if
2417 in_insn_list_p (const rtx_insn_list
*listp
, const rtx_insn
*node
)
2421 for (x
= listp
; x
; x
= XEXP (x
, 1))
2422 if (node
== XEXP (x
, 0))
2428 /* Search LISTP (an EXPR_LIST) for an entry whose first operand is NODE and
2429 remove that entry from the list if it is found.
2431 A simple equality test is used to determine if NODE matches. */
2434 remove_node_from_expr_list (const_rtx node
, rtx_expr_list
**listp
)
2436 rtx_expr_list
*temp
= *listp
;
2437 rtx_expr_list
*prev
= NULL
;
2441 if (node
== temp
->element ())
2443 /* Splice the node out of the list. */
2445 XEXP (prev
, 1) = temp
->next ();
2447 *listp
= temp
->next ();
2453 temp
= temp
->next ();
2457 /* Search LISTP (an INSN_LIST) for an entry whose first operand is NODE and
2458 remove that entry from the list if it is found.
2460 A simple equality test is used to determine if NODE matches. */
2463 remove_node_from_insn_list (const rtx_insn
*node
, rtx_insn_list
**listp
)
2465 rtx_insn_list
*temp
= *listp
;
2466 rtx_insn_list
*prev
= NULL
;
2470 if (node
== temp
->insn ())
2472 /* Splice the node out of the list. */
2474 XEXP (prev
, 1) = temp
->next ();
2476 *listp
= temp
->next ();
2482 temp
= temp
->next ();
2486 /* Nonzero if X contains any volatile instructions. These are instructions
2487 which may cause unpredictable machine state instructions, and thus no
2488 instructions or register uses should be moved or combined across them.
2489 This includes only volatile asms and UNSPEC_VOLATILE instructions. */
2492 volatile_insn_p (const_rtx x
)
2494 const RTX_CODE code
= GET_CODE (x
);
2512 case UNSPEC_VOLATILE
:
2517 if (MEM_VOLATILE_P (x
))
2524 /* Recursively scan the operands of this expression. */
2527 const char *const fmt
= GET_RTX_FORMAT (code
);
2530 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
2534 if (volatile_insn_p (XEXP (x
, i
)))
2537 else if (fmt
[i
] == 'E')
2540 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
2541 if (volatile_insn_p (XVECEXP (x
, i
, j
)))
2549 /* Nonzero if X contains any volatile memory references
2550 UNSPEC_VOLATILE operations or volatile ASM_OPERANDS expressions. */
2553 volatile_refs_p (const_rtx x
)
2555 const RTX_CODE code
= GET_CODE (x
);
2571 case UNSPEC_VOLATILE
:
2577 if (MEM_VOLATILE_P (x
))
2584 /* Recursively scan the operands of this expression. */
2587 const char *const fmt
= GET_RTX_FORMAT (code
);
2590 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
2594 if (volatile_refs_p (XEXP (x
, i
)))
2597 else if (fmt
[i
] == 'E')
2600 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
2601 if (volatile_refs_p (XVECEXP (x
, i
, j
)))
2609 /* Similar to above, except that it also rejects register pre- and post-
2613 side_effects_p (const_rtx x
)
2615 const RTX_CODE code
= GET_CODE (x
);
2632 /* Reject CLOBBER with a non-VOID mode. These are made by combine.c
2633 when some combination can't be done. If we see one, don't think
2634 that we can simplify the expression. */
2635 return (GET_MODE (x
) != VOIDmode
);
2644 case UNSPEC_VOLATILE
:
2650 if (MEM_VOLATILE_P (x
))
2657 /* Recursively scan the operands of this expression. */
2660 const char *fmt
= GET_RTX_FORMAT (code
);
2663 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
2667 if (side_effects_p (XEXP (x
, i
)))
2670 else if (fmt
[i
] == 'E')
2673 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
2674 if (side_effects_p (XVECEXP (x
, i
, j
)))
2682 /* Return nonzero if evaluating rtx X might cause a trap.
2683 FLAGS controls how to consider MEMs. A nonzero means the context
2684 of the access may have changed from the original, such that the
2685 address may have become invalid. */
2688 may_trap_p_1 (const_rtx x
, unsigned flags
)
2694 /* We make no distinction currently, but this function is part of
2695 the internal target-hooks ABI so we keep the parameter as
2696 "unsigned flags". */
2697 bool code_changed
= flags
!= 0;
2701 code
= GET_CODE (x
);
2704 /* Handle these cases quickly. */
2716 return targetm
.unspec_may_trap_p (x
, flags
);
2718 case UNSPEC_VOLATILE
:
2724 return MEM_VOLATILE_P (x
);
2726 /* Memory ref can trap unless it's a static var or a stack slot. */
2728 /* Recognize specific pattern of stack checking probes. */
2729 if (flag_stack_check
2730 && MEM_VOLATILE_P (x
)
2731 && XEXP (x
, 0) == stack_pointer_rtx
)
2733 if (/* MEM_NOTRAP_P only relates to the actual position of the memory
2734 reference; moving it out of context such as when moving code
2735 when optimizing, might cause its address to become invalid. */
2737 || !MEM_NOTRAP_P (x
))
2739 HOST_WIDE_INT size
= MEM_SIZE_KNOWN_P (x
) ? MEM_SIZE (x
) : 0;
2740 return rtx_addr_can_trap_p_1 (XEXP (x
, 0), 0, size
,
2741 GET_MODE (x
), code_changed
);
2746 /* Division by a non-constant might trap. */
2751 if (HONOR_SNANS (x
))
2753 if (SCALAR_FLOAT_MODE_P (GET_MODE (x
)))
2754 return flag_trapping_math
;
2755 if (!CONSTANT_P (XEXP (x
, 1)) || (XEXP (x
, 1) == const0_rtx
))
2760 /* An EXPR_LIST is used to represent a function call. This
2761 certainly may trap. */
2770 /* Some floating point comparisons may trap. */
2771 if (!flag_trapping_math
)
2773 /* ??? There is no machine independent way to check for tests that trap
2774 when COMPARE is used, though many targets do make this distinction.
2775 For instance, sparc uses CCFPE for compares which generate exceptions
2776 and CCFP for compares which do not generate exceptions. */
2779 /* But often the compare has some CC mode, so check operand
2781 if (HONOR_NANS (XEXP (x
, 0))
2782 || HONOR_NANS (XEXP (x
, 1)))
2788 if (HONOR_SNANS (x
))
2790 /* Often comparison is CC mode, so check operand modes. */
2791 if (HONOR_SNANS (XEXP (x
, 0))
2792 || HONOR_SNANS (XEXP (x
, 1)))
2797 /* Conversion of floating point might trap. */
2798 if (flag_trapping_math
&& HONOR_NANS (XEXP (x
, 0)))
2805 /* These operations don't trap even with floating point. */
2809 /* Any floating arithmetic may trap. */
2810 if (SCALAR_FLOAT_MODE_P (GET_MODE (x
)) && flag_trapping_math
)
2814 fmt
= GET_RTX_FORMAT (code
);
2815 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
2819 if (may_trap_p_1 (XEXP (x
, i
), flags
))
2822 else if (fmt
[i
] == 'E')
2825 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
2826 if (may_trap_p_1 (XVECEXP (x
, i
, j
), flags
))
2833 /* Return nonzero if evaluating rtx X might cause a trap. */
2836 may_trap_p (const_rtx x
)
2838 return may_trap_p_1 (x
, 0);
2841 /* Same as above, but additionally return nonzero if evaluating rtx X might
2842 cause a fault. We define a fault for the purpose of this function as a
2843 erroneous execution condition that cannot be encountered during the normal
2844 execution of a valid program; the typical example is an unaligned memory
2845 access on a strict alignment machine. The compiler guarantees that it
2846 doesn't generate code that will fault from a valid program, but this
2847 guarantee doesn't mean anything for individual instructions. Consider
2848 the following example:
2850 struct S { int d; union { char *cp; int *ip; }; };
2852 int foo(struct S *s)
2860 on a strict alignment machine. In a valid program, foo will never be
2861 invoked on a structure for which d is equal to 1 and the underlying
2862 unique field of the union not aligned on a 4-byte boundary, but the
2863 expression *s->ip might cause a fault if considered individually.
2865 At the RTL level, potentially problematic expressions will almost always
2866 verify may_trap_p; for example, the above dereference can be emitted as
2867 (mem:SI (reg:P)) and this expression is may_trap_p for a generic register.
2868 However, suppose that foo is inlined in a caller that causes s->cp to
2869 point to a local character variable and guarantees that s->d is not set
2870 to 1; foo may have been effectively translated into pseudo-RTL as:
2873 (set (reg:SI) (mem:SI (%fp - 7)))
2875 (set (reg:QI) (mem:QI (%fp - 7)))
2877 Now (mem:SI (%fp - 7)) is considered as not may_trap_p since it is a
2878 memory reference to a stack slot, but it will certainly cause a fault
2879 on a strict alignment machine. */
2882 may_trap_or_fault_p (const_rtx x
)
2884 return may_trap_p_1 (x
, 1);
2887 /* Return nonzero if X contains a comparison that is not either EQ or NE,
2888 i.e., an inequality. */
2891 inequality_comparisons_p (const_rtx x
)
2895 const enum rtx_code code
= GET_CODE (x
);
2923 len
= GET_RTX_LENGTH (code
);
2924 fmt
= GET_RTX_FORMAT (code
);
2926 for (i
= 0; i
< len
; i
++)
2930 if (inequality_comparisons_p (XEXP (x
, i
)))
2933 else if (fmt
[i
] == 'E')
2936 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
2937 if (inequality_comparisons_p (XVECEXP (x
, i
, j
)))
2945 /* Replace any occurrence of FROM in X with TO. The function does
2946 not enter into CONST_DOUBLE for the replace.
2948 Note that copying is not done so X must not be shared unless all copies
2949 are to be modified. */
2952 replace_rtx (rtx x
, rtx from
, rtx to
)
2960 /* Allow this function to make replacements in EXPR_LISTs. */
2964 if (GET_CODE (x
) == REG
)
2966 if (GET_CODE (from
) == REG
2967 && REGNO (x
) == REGNO (from
))
2969 gcc_assert (GET_MODE (x
) == GET_MODE (from
));
2973 else if (GET_CODE (x
) == SUBREG
)
2975 rtx new_rtx
= replace_rtx (SUBREG_REG (x
), from
, to
);
2977 if (CONST_INT_P (new_rtx
))
2979 x
= simplify_subreg (GET_MODE (x
), new_rtx
,
2980 GET_MODE (SUBREG_REG (x
)),
2985 SUBREG_REG (x
) = new_rtx
;
2989 else if (GET_CODE (x
) == ZERO_EXTEND
)
2991 rtx new_rtx
= replace_rtx (XEXP (x
, 0), from
, to
);
2993 if (CONST_INT_P (new_rtx
))
2995 x
= simplify_unary_operation (ZERO_EXTEND
, GET_MODE (x
),
2996 new_rtx
, GET_MODE (XEXP (x
, 0)));
3000 XEXP (x
, 0) = new_rtx
;
3005 fmt
= GET_RTX_FORMAT (GET_CODE (x
));
3006 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
3009 XEXP (x
, i
) = replace_rtx (XEXP (x
, i
), from
, to
);
3010 else if (fmt
[i
] == 'E')
3011 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3012 XVECEXP (x
, i
, j
) = replace_rtx (XVECEXP (x
, i
, j
), from
, to
);
3018 /* Replace occurrences of the OLD_LABEL in *LOC with NEW_LABEL. Also track
3019 the change in LABEL_NUSES if UPDATE_LABEL_NUSES. */
3022 replace_label (rtx
*loc
, rtx old_label
, rtx new_label
, bool update_label_nuses
)
3024 /* Handle jump tables specially, since ADDR_{DIFF_,}VECs can be long. */
3026 if (JUMP_TABLE_DATA_P (x
))
3029 rtvec vec
= XVEC (x
, GET_CODE (x
) == ADDR_DIFF_VEC
);
3030 int len
= GET_NUM_ELEM (vec
);
3031 for (int i
= 0; i
< len
; ++i
)
3033 rtx ref
= RTVEC_ELT (vec
, i
);
3034 if (XEXP (ref
, 0) == old_label
)
3036 XEXP (ref
, 0) = new_label
;
3037 if (update_label_nuses
)
3039 ++LABEL_NUSES (new_label
);
3040 --LABEL_NUSES (old_label
);
3047 /* If this is a JUMP_INSN, then we also need to fix the JUMP_LABEL
3048 field. This is not handled by the iterator because it doesn't
3049 handle unprinted ('0') fields. */
3050 if (JUMP_P (x
) && JUMP_LABEL (x
) == old_label
)
3051 JUMP_LABEL (x
) = new_label
;
3053 subrtx_ptr_iterator::array_type array
;
3054 FOR_EACH_SUBRTX_PTR (iter
, array
, loc
, ALL
)
3059 if (GET_CODE (x
) == SYMBOL_REF
3060 && CONSTANT_POOL_ADDRESS_P (x
))
3062 rtx c
= get_pool_constant (x
);
3063 if (rtx_referenced_p (old_label
, c
))
3065 /* Create a copy of constant C; replace the label inside
3066 but do not update LABEL_NUSES because uses in constant pool
3068 rtx new_c
= copy_rtx (c
);
3069 replace_label (&new_c
, old_label
, new_label
, false);
3071 /* Add the new constant NEW_C to constant pool and replace
3072 the old reference to constant by new reference. */
3073 rtx new_mem
= force_const_mem (get_pool_mode (x
), new_c
);
3074 *loc
= replace_rtx (x
, x
, XEXP (new_mem
, 0));
3078 if ((GET_CODE (x
) == LABEL_REF
3079 || GET_CODE (x
) == INSN_LIST
)
3080 && XEXP (x
, 0) == old_label
)
3082 XEXP (x
, 0) = new_label
;
3083 if (update_label_nuses
)
3085 ++LABEL_NUSES (new_label
);
3086 --LABEL_NUSES (old_label
);
3094 replace_label_in_insn (rtx_insn
*insn
, rtx old_label
, rtx new_label
,
3095 bool update_label_nuses
)
3097 rtx insn_as_rtx
= insn
;
3098 replace_label (&insn_as_rtx
, old_label
, new_label
, update_label_nuses
);
3099 gcc_checking_assert (insn_as_rtx
== insn
);
3102 /* Return true if X is referenced in BODY. */
3105 rtx_referenced_p (const_rtx x
, const_rtx body
)
3107 subrtx_iterator::array_type array
;
3108 FOR_EACH_SUBRTX (iter
, array
, body
, ALL
)
3109 if (const_rtx y
= *iter
)
3111 /* Check if a label_ref Y refers to label X. */
3112 if (GET_CODE (y
) == LABEL_REF
3114 && LABEL_REF_LABEL (y
) == x
)
3117 if (rtx_equal_p (x
, y
))
3120 /* If Y is a reference to pool constant traverse the constant. */
3121 if (GET_CODE (y
) == SYMBOL_REF
3122 && CONSTANT_POOL_ADDRESS_P (y
))
3123 iter
.substitute (get_pool_constant (y
));
3128 /* If INSN is a tablejump return true and store the label (before jump table) to
3129 *LABELP and the jump table to *TABLEP. LABELP and TABLEP may be NULL. */
3132 tablejump_p (const rtx_insn
*insn
, rtx
*labelp
, rtx_jump_table_data
**tablep
)
3140 label
= JUMP_LABEL (insn
);
3141 if (label
!= NULL_RTX
&& !ANY_RETURN_P (label
)
3142 && (table
= NEXT_INSN (as_a
<rtx_insn
*> (label
))) != NULL_RTX
3143 && JUMP_TABLE_DATA_P (table
))
3148 *tablep
= as_a
<rtx_jump_table_data
*> (table
);
3154 /* A subroutine of computed_jump_p, return 1 if X contains a REG or MEM or
3155 constant that is not in the constant pool and not in the condition
3156 of an IF_THEN_ELSE. */
3159 computed_jump_p_1 (const_rtx x
)
3161 const enum rtx_code code
= GET_CODE (x
);
3178 return ! (GET_CODE (XEXP (x
, 0)) == SYMBOL_REF
3179 && CONSTANT_POOL_ADDRESS_P (XEXP (x
, 0)));
3182 return (computed_jump_p_1 (XEXP (x
, 1))
3183 || computed_jump_p_1 (XEXP (x
, 2)));
3189 fmt
= GET_RTX_FORMAT (code
);
3190 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
3193 && computed_jump_p_1 (XEXP (x
, i
)))
3196 else if (fmt
[i
] == 'E')
3197 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
3198 if (computed_jump_p_1 (XVECEXP (x
, i
, j
)))
3205 /* Return nonzero if INSN is an indirect jump (aka computed jump).
3207 Tablejumps and casesi insns are not considered indirect jumps;
3208 we can recognize them by a (use (label_ref)). */
3211 computed_jump_p (const rtx_insn
*insn
)
3216 rtx pat
= PATTERN (insn
);
3218 /* If we have a JUMP_LABEL set, we're not a computed jump. */
3219 if (JUMP_LABEL (insn
) != NULL
)
3222 if (GET_CODE (pat
) == PARALLEL
)
3224 int len
= XVECLEN (pat
, 0);
3225 int has_use_labelref
= 0;
3227 for (i
= len
- 1; i
>= 0; i
--)
3228 if (GET_CODE (XVECEXP (pat
, 0, i
)) == USE
3229 && (GET_CODE (XEXP (XVECEXP (pat
, 0, i
), 0))
3232 has_use_labelref
= 1;
3236 if (! has_use_labelref
)
3237 for (i
= len
- 1; i
>= 0; i
--)
3238 if (GET_CODE (XVECEXP (pat
, 0, i
)) == SET
3239 && SET_DEST (XVECEXP (pat
, 0, i
)) == pc_rtx
3240 && computed_jump_p_1 (SET_SRC (XVECEXP (pat
, 0, i
))))
3243 else if (GET_CODE (pat
) == SET
3244 && SET_DEST (pat
) == pc_rtx
3245 && computed_jump_p_1 (SET_SRC (pat
)))
3253 /* MEM has a PRE/POST-INC/DEC/MODIFY address X. Extract the operands of
3254 the equivalent add insn and pass the result to FN, using DATA as the
3258 for_each_inc_dec_find_inc_dec (rtx mem
, for_each_inc_dec_fn fn
, void *data
)
3260 rtx x
= XEXP (mem
, 0);
3261 switch (GET_CODE (x
))
3266 int size
= GET_MODE_SIZE (GET_MODE (mem
));
3267 rtx r1
= XEXP (x
, 0);
3268 rtx c
= gen_int_mode (size
, GET_MODE (r1
));
3269 return fn (mem
, x
, r1
, r1
, c
, data
);
3275 int size
= GET_MODE_SIZE (GET_MODE (mem
));
3276 rtx r1
= XEXP (x
, 0);
3277 rtx c
= gen_int_mode (-size
, GET_MODE (r1
));
3278 return fn (mem
, x
, r1
, r1
, c
, data
);
3284 rtx r1
= XEXP (x
, 0);
3285 rtx add
= XEXP (x
, 1);
3286 return fn (mem
, x
, r1
, add
, NULL
, data
);
3294 /* Traverse *LOC looking for MEMs that have autoinc addresses.
3295 For each such autoinc operation found, call FN, passing it
3296 the innermost enclosing MEM, the operation itself, the RTX modified
3297 by the operation, two RTXs (the second may be NULL) that, once
3298 added, represent the value to be held by the modified RTX
3299 afterwards, and DATA. FN is to return 0 to continue the
3300 traversal or any other value to have it returned to the caller of
3301 for_each_inc_dec. */
3304 for_each_inc_dec (rtx x
,
3305 for_each_inc_dec_fn fn
,
3308 subrtx_var_iterator::array_type array
;
3309 FOR_EACH_SUBRTX_VAR (iter
, array
, x
, NONCONST
)
3314 && GET_RTX_CLASS (GET_CODE (XEXP (mem
, 0))) == RTX_AUTOINC
)
3316 int res
= for_each_inc_dec_find_inc_dec (mem
, fn
, data
);
3319 iter
.skip_subrtxes ();
3326 /* Searches X for any reference to REGNO, returning the rtx of the
3327 reference found if any. Otherwise, returns NULL_RTX. */
3330 regno_use_in (unsigned int regno
, rtx x
)
3336 if (REG_P (x
) && REGNO (x
) == regno
)
3339 fmt
= GET_RTX_FORMAT (GET_CODE (x
));
3340 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
3344 if ((tem
= regno_use_in (regno
, XEXP (x
, i
))))
3347 else if (fmt
[i
] == 'E')
3348 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3349 if ((tem
= regno_use_in (regno
, XVECEXP (x
, i
, j
))))
3356 /* Return a value indicating whether OP, an operand of a commutative
3357 operation, is preferred as the first or second operand. The more
3358 positive the value, the stronger the preference for being the first
3362 commutative_operand_precedence (rtx op
)
3364 enum rtx_code code
= GET_CODE (op
);
3366 /* Constants always become the second operand. Prefer "nice" constants. */
3367 if (code
== CONST_INT
)
3369 if (code
== CONST_WIDE_INT
)
3371 if (code
== CONST_DOUBLE
)
3373 if (code
== CONST_FIXED
)
3375 op
= avoid_constant_pool_reference (op
);
3376 code
= GET_CODE (op
);
3378 switch (GET_RTX_CLASS (code
))
3381 if (code
== CONST_INT
)
3383 if (code
== CONST_WIDE_INT
)
3385 if (code
== CONST_DOUBLE
)
3387 if (code
== CONST_FIXED
)
3392 /* SUBREGs of objects should come second. */
3393 if (code
== SUBREG
&& OBJECT_P (SUBREG_REG (op
)))
3398 /* Complex expressions should be the first, so decrease priority
3399 of objects. Prefer pointer objects over non pointer objects. */
3400 if ((REG_P (op
) && REG_POINTER (op
))
3401 || (MEM_P (op
) && MEM_POINTER (op
)))
3405 case RTX_COMM_ARITH
:
3406 /* Prefer operands that are themselves commutative to be first.
3407 This helps to make things linear. In particular,
3408 (and (and (reg) (reg)) (not (reg))) is canonical. */
3412 /* If only one operand is a binary expression, it will be the first
3413 operand. In particular, (plus (minus (reg) (reg)) (neg (reg)))
3414 is canonical, although it will usually be further simplified. */
3418 /* Then prefer NEG and NOT. */
3419 if (code
== NEG
|| code
== NOT
)
3427 /* Return 1 iff it is necessary to swap operands of commutative operation
3428 in order to canonicalize expression. */
3431 swap_commutative_operands_p (rtx x
, rtx y
)
3433 return (commutative_operand_precedence (x
)
3434 < commutative_operand_precedence (y
));
3437 /* Return 1 if X is an autoincrement side effect and the register is
3438 not the stack pointer. */
3440 auto_inc_p (const_rtx x
)
3442 switch (GET_CODE (x
))
3450 /* There are no REG_INC notes for SP. */
3451 if (XEXP (x
, 0) != stack_pointer_rtx
)
3459 /* Return nonzero if IN contains a piece of rtl that has the address LOC. */
3461 loc_mentioned_in_p (rtx
*loc
, const_rtx in
)
3470 code
= GET_CODE (in
);
3471 fmt
= GET_RTX_FORMAT (code
);
3472 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
3476 if (loc
== &XEXP (in
, i
) || loc_mentioned_in_p (loc
, XEXP (in
, i
)))
3479 else if (fmt
[i
] == 'E')
3480 for (j
= XVECLEN (in
, i
) - 1; j
>= 0; j
--)
3481 if (loc
== &XVECEXP (in
, i
, j
)
3482 || loc_mentioned_in_p (loc
, XVECEXP (in
, i
, j
)))
3488 /* Helper function for subreg_lsb. Given a subreg's OUTER_MODE, INNER_MODE,
3489 and SUBREG_BYTE, return the bit offset where the subreg begins
3490 (counting from the least significant bit of the operand). */
3493 subreg_lsb_1 (machine_mode outer_mode
,
3494 machine_mode inner_mode
,
3495 unsigned int subreg_byte
)
3497 unsigned int bitpos
;
3501 /* A paradoxical subreg begins at bit position 0. */
3502 if (GET_MODE_PRECISION (outer_mode
) > GET_MODE_PRECISION (inner_mode
))
3505 if (WORDS_BIG_ENDIAN
!= BYTES_BIG_ENDIAN
)
3506 /* If the subreg crosses a word boundary ensure that
3507 it also begins and ends on a word boundary. */
3508 gcc_assert (!((subreg_byte
% UNITS_PER_WORD
3509 + GET_MODE_SIZE (outer_mode
)) > UNITS_PER_WORD
3510 && (subreg_byte
% UNITS_PER_WORD
3511 || GET_MODE_SIZE (outer_mode
) % UNITS_PER_WORD
)));
3513 if (WORDS_BIG_ENDIAN
)
3514 word
= (GET_MODE_SIZE (inner_mode
)
3515 - (subreg_byte
+ GET_MODE_SIZE (outer_mode
))) / UNITS_PER_WORD
;
3517 word
= subreg_byte
/ UNITS_PER_WORD
;
3518 bitpos
= word
* BITS_PER_WORD
;
3520 if (BYTES_BIG_ENDIAN
)
3521 byte
= (GET_MODE_SIZE (inner_mode
)
3522 - (subreg_byte
+ GET_MODE_SIZE (outer_mode
))) % UNITS_PER_WORD
;
3524 byte
= subreg_byte
% UNITS_PER_WORD
;
3525 bitpos
+= byte
* BITS_PER_UNIT
;
3530 /* Given a subreg X, return the bit offset where the subreg begins
3531 (counting from the least significant bit of the reg). */
3534 subreg_lsb (const_rtx x
)
3536 return subreg_lsb_1 (GET_MODE (x
), GET_MODE (SUBREG_REG (x
)),
3540 /* Fill in information about a subreg of a hard register.
3541 xregno - A regno of an inner hard subreg_reg (or what will become one).
3542 xmode - The mode of xregno.
3543 offset - The byte offset.
3544 ymode - The mode of a top level SUBREG (or what may become one).
3545 info - Pointer to structure to fill in.
3547 Rather than considering one particular inner register (and thus one
3548 particular "outer" register) in isolation, this function really uses
3549 XREGNO as a model for a sequence of isomorphic hard registers. Thus the
3550 function does not check whether adding INFO->offset to XREGNO gives
3551 a valid hard register; even if INFO->offset + XREGNO is out of range,
3552 there might be another register of the same type that is in range.
3553 Likewise it doesn't check whether HARD_REGNO_MODE_OK accepts the new
3554 register, since that can depend on things like whether the final
3555 register number is even or odd. Callers that want to check whether
3556 this particular subreg can be replaced by a simple (reg ...) should
3557 use simplify_subreg_regno. */
3560 subreg_get_info (unsigned int xregno
, machine_mode xmode
,
3561 unsigned int offset
, machine_mode ymode
,
3562 struct subreg_info
*info
)
3564 int nregs_xmode
, nregs_ymode
;
3565 int mode_multiple
, nregs_multiple
;
3566 int offset_adj
, y_offset
, y_offset_adj
;
3567 int regsize_xmode
, regsize_ymode
;
3570 gcc_assert (xregno
< FIRST_PSEUDO_REGISTER
);
3574 /* If there are holes in a non-scalar mode in registers, we expect
3575 that it is made up of its units concatenated together. */
3576 if (HARD_REGNO_NREGS_HAS_PADDING (xregno
, xmode
))
3578 machine_mode xmode_unit
;
3580 nregs_xmode
= HARD_REGNO_NREGS_WITH_PADDING (xregno
, xmode
);
3581 xmode_unit
= GET_MODE_INNER (xmode
);
3582 gcc_assert (HARD_REGNO_NREGS_HAS_PADDING (xregno
, xmode_unit
));
3583 gcc_assert (nregs_xmode
3584 == (GET_MODE_NUNITS (xmode
)
3585 * HARD_REGNO_NREGS_WITH_PADDING (xregno
, xmode_unit
)));
3586 gcc_assert (hard_regno_nregs
[xregno
][xmode
]
3587 == (hard_regno_nregs
[xregno
][xmode_unit
]
3588 * GET_MODE_NUNITS (xmode
)));
3590 /* You can only ask for a SUBREG of a value with holes in the middle
3591 if you don't cross the holes. (Such a SUBREG should be done by
3592 picking a different register class, or doing it in memory if
3593 necessary.) An example of a value with holes is XCmode on 32-bit
3594 x86 with -m128bit-long-double; it's represented in 6 32-bit registers,
3595 3 for each part, but in memory it's two 128-bit parts.
3596 Padding is assumed to be at the end (not necessarily the 'high part')
3598 if ((offset
/ GET_MODE_SIZE (xmode_unit
) + 1
3599 < GET_MODE_NUNITS (xmode
))
3600 && (offset
/ GET_MODE_SIZE (xmode_unit
)
3601 != ((offset
+ GET_MODE_SIZE (ymode
) - 1)
3602 / GET_MODE_SIZE (xmode_unit
))))
3604 info
->representable_p
= false;
3609 nregs_xmode
= hard_regno_nregs
[xregno
][xmode
];
3611 nregs_ymode
= hard_regno_nregs
[xregno
][ymode
];
3613 /* Paradoxical subregs are otherwise valid. */
3616 && GET_MODE_PRECISION (ymode
) > GET_MODE_PRECISION (xmode
))
3618 info
->representable_p
= true;
3619 /* If this is a big endian paradoxical subreg, which uses more
3620 actual hard registers than the original register, we must
3621 return a negative offset so that we find the proper highpart
3623 if (GET_MODE_SIZE (ymode
) > UNITS_PER_WORD
3624 ? REG_WORDS_BIG_ENDIAN
: BYTES_BIG_ENDIAN
)
3625 info
->offset
= nregs_xmode
- nregs_ymode
;
3628 info
->nregs
= nregs_ymode
;
3632 /* If registers store different numbers of bits in the different
3633 modes, we cannot generally form this subreg. */
3634 if (!HARD_REGNO_NREGS_HAS_PADDING (xregno
, xmode
)
3635 && !HARD_REGNO_NREGS_HAS_PADDING (xregno
, ymode
)
3636 && (GET_MODE_SIZE (xmode
) % nregs_xmode
) == 0
3637 && (GET_MODE_SIZE (ymode
) % nregs_ymode
) == 0)
3639 regsize_xmode
= GET_MODE_SIZE (xmode
) / nregs_xmode
;
3640 regsize_ymode
= GET_MODE_SIZE (ymode
) / nregs_ymode
;
3641 if (!rknown
&& regsize_xmode
> regsize_ymode
&& nregs_ymode
> 1)
3643 info
->representable_p
= false;
3645 = (GET_MODE_SIZE (ymode
) + regsize_xmode
- 1) / regsize_xmode
;
3646 info
->offset
= offset
/ regsize_xmode
;
3649 if (!rknown
&& regsize_ymode
> regsize_xmode
&& nregs_xmode
> 1)
3651 info
->representable_p
= false;
3653 = (GET_MODE_SIZE (ymode
) + regsize_xmode
- 1) / regsize_xmode
;
3654 info
->offset
= offset
/ regsize_xmode
;
3657 /* Quick exit for the simple and common case of extracting whole
3658 subregisters from a multiregister value. */
3659 /* ??? It would be better to integrate this into the code below,
3660 if we can generalize the concept enough and figure out how
3661 odd-sized modes can coexist with the other weird cases we support. */
3663 && WORDS_BIG_ENDIAN
== REG_WORDS_BIG_ENDIAN
3664 && regsize_xmode
== regsize_ymode
3665 && (offset
% regsize_ymode
) == 0)
3667 info
->representable_p
= true;
3668 info
->nregs
= nregs_ymode
;
3669 info
->offset
= offset
/ regsize_ymode
;
3670 gcc_assert (info
->offset
+ info
->nregs
<= nregs_xmode
);
3675 /* Lowpart subregs are otherwise valid. */
3676 if (!rknown
&& offset
== subreg_lowpart_offset (ymode
, xmode
))
3678 info
->representable_p
= true;
3681 if (offset
== 0 || nregs_xmode
== nregs_ymode
)
3684 info
->nregs
= nregs_ymode
;
3689 /* This should always pass, otherwise we don't know how to verify
3690 the constraint. These conditions may be relaxed but
3691 subreg_regno_offset would need to be redesigned. */
3692 gcc_assert ((GET_MODE_SIZE (xmode
) % GET_MODE_SIZE (ymode
)) == 0);
3693 gcc_assert ((nregs_xmode
% nregs_ymode
) == 0);
3695 if (WORDS_BIG_ENDIAN
!= REG_WORDS_BIG_ENDIAN
3696 && GET_MODE_SIZE (xmode
) > UNITS_PER_WORD
)
3698 HOST_WIDE_INT xsize
= GET_MODE_SIZE (xmode
);
3699 HOST_WIDE_INT ysize
= GET_MODE_SIZE (ymode
);
3700 HOST_WIDE_INT off_low
= offset
& (ysize
- 1);
3701 HOST_WIDE_INT off_high
= offset
& ~(ysize
- 1);
3702 offset
= (xsize
- ysize
- off_high
) | off_low
;
3704 /* The XMODE value can be seen as a vector of NREGS_XMODE
3705 values. The subreg must represent a lowpart of given field.
3706 Compute what field it is. */
3707 offset_adj
= offset
;
3708 offset_adj
-= subreg_lowpart_offset (ymode
,
3709 mode_for_size (GET_MODE_BITSIZE (xmode
)
3713 /* Size of ymode must not be greater than the size of xmode. */
3714 mode_multiple
= GET_MODE_SIZE (xmode
) / GET_MODE_SIZE (ymode
);
3715 gcc_assert (mode_multiple
!= 0);
3717 y_offset
= offset
/ GET_MODE_SIZE (ymode
);
3718 y_offset_adj
= offset_adj
/ GET_MODE_SIZE (ymode
);
3719 nregs_multiple
= nregs_xmode
/ nregs_ymode
;
3721 gcc_assert ((offset_adj
% GET_MODE_SIZE (ymode
)) == 0);
3722 gcc_assert ((mode_multiple
% nregs_multiple
) == 0);
3726 info
->representable_p
= (!(y_offset_adj
% (mode_multiple
/ nregs_multiple
)));
3729 info
->offset
= (y_offset
/ (mode_multiple
/ nregs_multiple
)) * nregs_ymode
;
3730 info
->nregs
= nregs_ymode
;
3733 /* This function returns the regno offset of a subreg expression.
3734 xregno - A regno of an inner hard subreg_reg (or what will become one).
3735 xmode - The mode of xregno.
3736 offset - The byte offset.
3737 ymode - The mode of a top level SUBREG (or what may become one).
3738 RETURN - The regno offset which would be used. */
3740 subreg_regno_offset (unsigned int xregno
, machine_mode xmode
,
3741 unsigned int offset
, machine_mode ymode
)
3743 struct subreg_info info
;
3744 subreg_get_info (xregno
, xmode
, offset
, ymode
, &info
);
3748 /* This function returns true when the offset is representable via
3749 subreg_offset in the given regno.
3750 xregno - A regno of an inner hard subreg_reg (or what will become one).
3751 xmode - The mode of xregno.
3752 offset - The byte offset.
3753 ymode - The mode of a top level SUBREG (or what may become one).
3754 RETURN - Whether the offset is representable. */
3756 subreg_offset_representable_p (unsigned int xregno
, machine_mode xmode
,
3757 unsigned int offset
, machine_mode ymode
)
3759 struct subreg_info info
;
3760 subreg_get_info (xregno
, xmode
, offset
, ymode
, &info
);
3761 return info
.representable_p
;
3764 /* Return the number of a YMODE register to which
3766 (subreg:YMODE (reg:XMODE XREGNO) OFFSET)
3768 can be simplified. Return -1 if the subreg can't be simplified.
3770 XREGNO is a hard register number. */
3773 simplify_subreg_regno (unsigned int xregno
, machine_mode xmode
,
3774 unsigned int offset
, machine_mode ymode
)
3776 struct subreg_info info
;
3777 unsigned int yregno
;
3779 #ifdef CANNOT_CHANGE_MODE_CLASS
3780 /* Give the backend a chance to disallow the mode change. */
3781 if (GET_MODE_CLASS (xmode
) != MODE_COMPLEX_INT
3782 && GET_MODE_CLASS (xmode
) != MODE_COMPLEX_FLOAT
3783 && REG_CANNOT_CHANGE_MODE_P (xregno
, xmode
, ymode
)
3784 /* We can use mode change in LRA for some transformations. */
3785 && ! lra_in_progress
)
3789 /* We shouldn't simplify stack-related registers. */
3790 if ((!reload_completed
|| frame_pointer_needed
)
3791 && xregno
== FRAME_POINTER_REGNUM
)
3794 if (FRAME_POINTER_REGNUM
!= ARG_POINTER_REGNUM
3795 && xregno
== ARG_POINTER_REGNUM
)
3798 if (xregno
== STACK_POINTER_REGNUM
3799 /* We should convert hard stack register in LRA if it is
3801 && ! lra_in_progress
)
3804 /* Try to get the register offset. */
3805 subreg_get_info (xregno
, xmode
, offset
, ymode
, &info
);
3806 if (!info
.representable_p
)
3809 /* Make sure that the offsetted register value is in range. */
3810 yregno
= xregno
+ info
.offset
;
3811 if (!HARD_REGISTER_NUM_P (yregno
))
3814 /* See whether (reg:YMODE YREGNO) is valid.
3816 ??? We allow invalid registers if (reg:XMODE XREGNO) is also invalid.
3817 This is a kludge to work around how complex FP arguments are passed
3818 on IA-64 and should be fixed. See PR target/49226. */
3819 if (!HARD_REGNO_MODE_OK (yregno
, ymode
)
3820 && HARD_REGNO_MODE_OK (xregno
, xmode
))
3823 return (int) yregno
;
3826 /* Return the final regno that a subreg expression refers to. */
3828 subreg_regno (const_rtx x
)
3831 rtx subreg
= SUBREG_REG (x
);
3832 int regno
= REGNO (subreg
);
3834 ret
= regno
+ subreg_regno_offset (regno
,
3842 /* Return the number of registers that a subreg expression refers
3845 subreg_nregs (const_rtx x
)
3847 return subreg_nregs_with_regno (REGNO (SUBREG_REG (x
)), x
);
3850 /* Return the number of registers that a subreg REG with REGNO
3851 expression refers to. This is a copy of the rtlanal.c:subreg_nregs
3852 changed so that the regno can be passed in. */
3855 subreg_nregs_with_regno (unsigned int regno
, const_rtx x
)
3857 struct subreg_info info
;
3858 rtx subreg
= SUBREG_REG (x
);
3860 subreg_get_info (regno
, GET_MODE (subreg
), SUBREG_BYTE (x
), GET_MODE (x
),
3866 struct parms_set_data
3872 /* Helper function for noticing stores to parameter registers. */
3874 parms_set (rtx x
, const_rtx pat ATTRIBUTE_UNUSED
, void *data
)
3876 struct parms_set_data
*const d
= (struct parms_set_data
*) data
;
3877 if (REG_P (x
) && REGNO (x
) < FIRST_PSEUDO_REGISTER
3878 && TEST_HARD_REG_BIT (d
->regs
, REGNO (x
)))
3880 CLEAR_HARD_REG_BIT (d
->regs
, REGNO (x
));
3885 /* Look backward for first parameter to be loaded.
3886 Note that loads of all parameters will not necessarily be
3887 found if CSE has eliminated some of them (e.g., an argument
3888 to the outer function is passed down as a parameter).
3889 Do not skip BOUNDARY. */
3891 find_first_parameter_load (rtx_insn
*call_insn
, rtx_insn
*boundary
)
3893 struct parms_set_data parm
;
3895 rtx_insn
*before
, *first_set
;
3897 /* Since different machines initialize their parameter registers
3898 in different orders, assume nothing. Collect the set of all
3899 parameter registers. */
3900 CLEAR_HARD_REG_SET (parm
.regs
);
3902 for (p
= CALL_INSN_FUNCTION_USAGE (call_insn
); p
; p
= XEXP (p
, 1))
3903 if (GET_CODE (XEXP (p
, 0)) == USE
3904 && REG_P (XEXP (XEXP (p
, 0), 0)))
3906 gcc_assert (REGNO (XEXP (XEXP (p
, 0), 0)) < FIRST_PSEUDO_REGISTER
);
3908 /* We only care about registers which can hold function
3910 if (!FUNCTION_ARG_REGNO_P (REGNO (XEXP (XEXP (p
, 0), 0))))
3913 SET_HARD_REG_BIT (parm
.regs
, REGNO (XEXP (XEXP (p
, 0), 0)));
3917 first_set
= call_insn
;
3919 /* Search backward for the first set of a register in this set. */
3920 while (parm
.nregs
&& before
!= boundary
)
3922 before
= PREV_INSN (before
);
3924 /* It is possible that some loads got CSEed from one call to
3925 another. Stop in that case. */
3926 if (CALL_P (before
))
3929 /* Our caller needs either ensure that we will find all sets
3930 (in case code has not been optimized yet), or take care
3931 for possible labels in a way by setting boundary to preceding
3933 if (LABEL_P (before
))
3935 gcc_assert (before
== boundary
);
3939 if (INSN_P (before
))
3941 int nregs_old
= parm
.nregs
;
3942 note_stores (PATTERN (before
), parms_set
, &parm
);
3943 /* If we found something that did not set a parameter reg,
3944 we're done. Do not keep going, as that might result
3945 in hoisting an insn before the setting of a pseudo
3946 that is used by the hoisted insn. */
3947 if (nregs_old
!= parm
.nregs
)
3956 /* Return true if we should avoid inserting code between INSN and preceding
3957 call instruction. */
3960 keep_with_call_p (const rtx_insn
*insn
)
3964 if (INSN_P (insn
) && (set
= single_set (insn
)) != NULL
)
3966 if (REG_P (SET_DEST (set
))
3967 && REGNO (SET_DEST (set
)) < FIRST_PSEUDO_REGISTER
3968 && fixed_regs
[REGNO (SET_DEST (set
))]
3969 && general_operand (SET_SRC (set
), VOIDmode
))
3971 if (REG_P (SET_SRC (set
))
3972 && targetm
.calls
.function_value_regno_p (REGNO (SET_SRC (set
)))
3973 && REG_P (SET_DEST (set
))
3974 && REGNO (SET_DEST (set
)) >= FIRST_PSEUDO_REGISTER
)
3976 /* There may be a stack pop just after the call and before the store
3977 of the return register. Search for the actual store when deciding
3978 if we can break or not. */
3979 if (SET_DEST (set
) == stack_pointer_rtx
)
3981 /* This CONST_CAST is okay because next_nonnote_insn just
3982 returns its argument and we assign it to a const_rtx
3985 = next_nonnote_insn (const_cast<rtx_insn
*> (insn
));
3986 if (i2
&& keep_with_call_p (i2
))
3993 /* Return true if LABEL is a target of JUMP_INSN. This applies only
3994 to non-complex jumps. That is, direct unconditional, conditional,
3995 and tablejumps, but not computed jumps or returns. It also does
3996 not apply to the fallthru case of a conditional jump. */
3999 label_is_jump_target_p (const_rtx label
, const rtx_insn
*jump_insn
)
4001 rtx tmp
= JUMP_LABEL (jump_insn
);
4002 rtx_jump_table_data
*table
;
4007 if (tablejump_p (jump_insn
, NULL
, &table
))
4009 rtvec vec
= table
->get_labels ();
4010 int i
, veclen
= GET_NUM_ELEM (vec
);
4012 for (i
= 0; i
< veclen
; ++i
)
4013 if (XEXP (RTVEC_ELT (vec
, i
), 0) == label
)
4017 if (find_reg_note (jump_insn
, REG_LABEL_TARGET
, label
))
4024 /* Return an estimate of the cost of computing rtx X.
4025 One use is in cse, to decide which expression to keep in the hash table.
4026 Another is in rtl generation, to pick the cheapest way to multiply.
4027 Other uses like the latter are expected in the future.
4029 X appears as operand OPNO in an expression with code OUTER_CODE.
4030 SPEED specifies whether costs optimized for speed or size should
4034 rtx_cost (rtx x
, machine_mode mode
, enum rtx_code outer_code
,
4035 int opno
, bool speed
)
4046 if (GET_MODE (x
) != VOIDmode
)
4047 mode
= GET_MODE (x
);
4049 /* A size N times larger than UNITS_PER_WORD likely needs N times as
4050 many insns, taking N times as long. */
4051 factor
= GET_MODE_SIZE (mode
) / UNITS_PER_WORD
;
4055 /* Compute the default costs of certain things.
4056 Note that targetm.rtx_costs can override the defaults. */
4058 code
= GET_CODE (x
);
4062 /* Multiplication has time-complexity O(N*N), where N is the
4063 number of units (translated from digits) when using
4064 schoolbook long multiplication. */
4065 total
= factor
* factor
* COSTS_N_INSNS (5);
4071 /* Similarly, complexity for schoolbook long division. */
4072 total
= factor
* factor
* COSTS_N_INSNS (7);
4075 /* Used in combine.c as a marker. */
4079 /* A SET doesn't have a mode, so let's look at the SET_DEST to get
4080 the mode for the factor. */
4081 mode
= GET_MODE (SET_DEST (x
));
4082 factor
= GET_MODE_SIZE (mode
) / UNITS_PER_WORD
;
4087 total
= factor
* COSTS_N_INSNS (1);
4097 /* If we can't tie these modes, make this expensive. The larger
4098 the mode, the more expensive it is. */
4099 if (! MODES_TIEABLE_P (mode
, GET_MODE (SUBREG_REG (x
))))
4100 return COSTS_N_INSNS (2 + factor
);
4104 if (targetm
.rtx_costs (x
, mode
, outer_code
, opno
, &total
, speed
))
4109 /* Sum the costs of the sub-rtx's, plus cost of this operation,
4110 which is already in total. */
4112 fmt
= GET_RTX_FORMAT (code
);
4113 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
4115 total
+= rtx_cost (XEXP (x
, i
), mode
, code
, i
, speed
);
4116 else if (fmt
[i
] == 'E')
4117 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
4118 total
+= rtx_cost (XVECEXP (x
, i
, j
), mode
, code
, i
, speed
);
4123 /* Fill in the structure C with information about both speed and size rtx
4124 costs for X, which is operand OPNO in an expression with code OUTER. */
4127 get_full_rtx_cost (rtx x
, machine_mode mode
, enum rtx_code outer
, int opno
,
4128 struct full_rtx_costs
*c
)
4130 c
->speed
= rtx_cost (x
, mode
, outer
, opno
, true);
4131 c
->size
= rtx_cost (x
, mode
, outer
, opno
, false);
4135 /* Return cost of address expression X.
4136 Expect that X is properly formed address reference.
4138 SPEED parameter specify whether costs optimized for speed or size should
4142 address_cost (rtx x
, machine_mode mode
, addr_space_t as
, bool speed
)
4144 /* We may be asked for cost of various unusual addresses, such as operands
4145 of push instruction. It is not worthwhile to complicate writing
4146 of the target hook by such cases. */
4148 if (!memory_address_addr_space_p (mode
, x
, as
))
4151 return targetm
.address_cost (x
, mode
, as
, speed
);
4154 /* If the target doesn't override, compute the cost as with arithmetic. */
4157 default_address_cost (rtx x
, machine_mode
, addr_space_t
, bool speed
)
4159 return rtx_cost (x
, Pmode
, MEM
, 0, speed
);
4163 unsigned HOST_WIDE_INT
4164 nonzero_bits (const_rtx x
, machine_mode mode
)
4166 return cached_nonzero_bits (x
, mode
, NULL_RTX
, VOIDmode
, 0);
4170 num_sign_bit_copies (const_rtx x
, machine_mode mode
)
4172 return cached_num_sign_bit_copies (x
, mode
, NULL_RTX
, VOIDmode
, 0);
4175 /* Return true if nonzero_bits1 might recurse into both operands
4179 nonzero_bits_binary_arith_p (const_rtx x
)
4181 if (!ARITHMETIC_P (x
))
4183 switch (GET_CODE (x
))
4205 /* The function cached_nonzero_bits is a wrapper around nonzero_bits1.
4206 It avoids exponential behavior in nonzero_bits1 when X has
4207 identical subexpressions on the first or the second level. */
4209 static unsigned HOST_WIDE_INT
4210 cached_nonzero_bits (const_rtx x
, machine_mode mode
, const_rtx known_x
,
4211 machine_mode known_mode
,
4212 unsigned HOST_WIDE_INT known_ret
)
4214 if (x
== known_x
&& mode
== known_mode
)
4217 /* Try to find identical subexpressions. If found call
4218 nonzero_bits1 on X with the subexpressions as KNOWN_X and the
4219 precomputed value for the subexpression as KNOWN_RET. */
4221 if (nonzero_bits_binary_arith_p (x
))
4223 rtx x0
= XEXP (x
, 0);
4224 rtx x1
= XEXP (x
, 1);
4226 /* Check the first level. */
4228 return nonzero_bits1 (x
, mode
, x0
, mode
,
4229 cached_nonzero_bits (x0
, mode
, known_x
,
4230 known_mode
, known_ret
));
4232 /* Check the second level. */
4233 if (nonzero_bits_binary_arith_p (x0
)
4234 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
4235 return nonzero_bits1 (x
, mode
, x1
, mode
,
4236 cached_nonzero_bits (x1
, mode
, known_x
,
4237 known_mode
, known_ret
));
4239 if (nonzero_bits_binary_arith_p (x1
)
4240 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
4241 return nonzero_bits1 (x
, mode
, x0
, mode
,
4242 cached_nonzero_bits (x0
, mode
, known_x
,
4243 known_mode
, known_ret
));
4246 return nonzero_bits1 (x
, mode
, known_x
, known_mode
, known_ret
);
4249 /* We let num_sign_bit_copies recur into nonzero_bits as that is useful.
4250 We don't let nonzero_bits recur into num_sign_bit_copies, because that
4251 is less useful. We can't allow both, because that results in exponential
4252 run time recursion. There is a nullstone testcase that triggered
4253 this. This macro avoids accidental uses of num_sign_bit_copies. */
4254 #define cached_num_sign_bit_copies sorry_i_am_preventing_exponential_behavior
4256 /* Given an expression, X, compute which bits in X can be nonzero.
4257 We don't care about bits outside of those defined in MODE.
4259 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
4260 an arithmetic operation, we can do better. */
4262 static unsigned HOST_WIDE_INT
4263 nonzero_bits1 (const_rtx x
, machine_mode mode
, const_rtx known_x
,
4264 machine_mode known_mode
,
4265 unsigned HOST_WIDE_INT known_ret
)
4267 unsigned HOST_WIDE_INT nonzero
= GET_MODE_MASK (mode
);
4268 unsigned HOST_WIDE_INT inner_nz
;
4270 machine_mode inner_mode
;
4271 unsigned int mode_width
= GET_MODE_PRECISION (mode
);
4273 /* For floating-point and vector values, assume all bits are needed. */
4274 if (FLOAT_MODE_P (GET_MODE (x
)) || FLOAT_MODE_P (mode
)
4275 || VECTOR_MODE_P (GET_MODE (x
)) || VECTOR_MODE_P (mode
))
4278 /* If X is wider than MODE, use its mode instead. */
4279 if (GET_MODE_PRECISION (GET_MODE (x
)) > mode_width
)
4281 mode
= GET_MODE (x
);
4282 nonzero
= GET_MODE_MASK (mode
);
4283 mode_width
= GET_MODE_PRECISION (mode
);
4286 if (mode_width
> HOST_BITS_PER_WIDE_INT
)
4287 /* Our only callers in this case look for single bit values. So
4288 just return the mode mask. Those tests will then be false. */
4291 /* If MODE is wider than X, but both are a single word for both the host
4292 and target machines, we can compute this from which bits of the
4293 object might be nonzero in its own mode, taking into account the fact
4294 that on many CISC machines, accessing an object in a wider mode
4295 causes the high-order bits to become undefined. So they are
4296 not known to be zero. */
4298 if (!WORD_REGISTER_OPERATIONS
4299 && GET_MODE (x
) != VOIDmode
4300 && GET_MODE (x
) != mode
4301 && GET_MODE_PRECISION (GET_MODE (x
)) <= BITS_PER_WORD
4302 && GET_MODE_PRECISION (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
4303 && GET_MODE_PRECISION (mode
) > GET_MODE_PRECISION (GET_MODE (x
)))
4305 nonzero
&= cached_nonzero_bits (x
, GET_MODE (x
),
4306 known_x
, known_mode
, known_ret
);
4307 nonzero
|= GET_MODE_MASK (mode
) & ~GET_MODE_MASK (GET_MODE (x
));
4311 /* Please keep nonzero_bits_binary_arith_p above in sync with
4312 the code in the switch below. */
4313 code
= GET_CODE (x
);
4317 #if defined(POINTERS_EXTEND_UNSIGNED)
4318 /* If pointers extend unsigned and this is a pointer in Pmode, say that
4319 all the bits above ptr_mode are known to be zero. */
4320 /* As we do not know which address space the pointer is referring to,
4321 we can do this only if the target does not support different pointer
4322 or address modes depending on the address space. */
4323 if (target_default_pointer_address_modes_p ()
4324 && POINTERS_EXTEND_UNSIGNED
&& GET_MODE (x
) == Pmode
4326 && !targetm
.have_ptr_extend ())
4327 nonzero
&= GET_MODE_MASK (ptr_mode
);
4330 /* Include declared information about alignment of pointers. */
4331 /* ??? We don't properly preserve REG_POINTER changes across
4332 pointer-to-integer casts, so we can't trust it except for
4333 things that we know must be pointers. See execute/960116-1.c. */
4334 if ((x
== stack_pointer_rtx
4335 || x
== frame_pointer_rtx
4336 || x
== arg_pointer_rtx
)
4337 && REGNO_POINTER_ALIGN (REGNO (x
)))
4339 unsigned HOST_WIDE_INT alignment
4340 = REGNO_POINTER_ALIGN (REGNO (x
)) / BITS_PER_UNIT
;
4342 #ifdef PUSH_ROUNDING
4343 /* If PUSH_ROUNDING is defined, it is possible for the
4344 stack to be momentarily aligned only to that amount,
4345 so we pick the least alignment. */
4346 if (x
== stack_pointer_rtx
&& PUSH_ARGS
)
4347 alignment
= MIN ((unsigned HOST_WIDE_INT
) PUSH_ROUNDING (1),
4351 nonzero
&= ~(alignment
- 1);
4355 unsigned HOST_WIDE_INT nonzero_for_hook
= nonzero
;
4356 rtx new_rtx
= rtl_hooks
.reg_nonzero_bits (x
, mode
, known_x
,
4357 known_mode
, known_ret
,
4361 nonzero_for_hook
&= cached_nonzero_bits (new_rtx
, mode
, known_x
,
4362 known_mode
, known_ret
);
4364 return nonzero_for_hook
;
4368 /* If X is negative in MODE, sign-extend the value. */
4369 if (SHORT_IMMEDIATES_SIGN_EXTEND
&& INTVAL (x
) > 0
4370 && mode_width
< BITS_PER_WORD
4371 && (UINTVAL (x
) & ((unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)))
4373 return UINTVAL (x
) | (HOST_WIDE_INT_M1U
<< mode_width
);
4378 #ifdef LOAD_EXTEND_OP
4379 /* In many, if not most, RISC machines, reading a byte from memory
4380 zeros the rest of the register. Noticing that fact saves a lot
4381 of extra zero-extends. */
4382 if (LOAD_EXTEND_OP (GET_MODE (x
)) == ZERO_EXTEND
)
4383 nonzero
&= GET_MODE_MASK (GET_MODE (x
));
4388 case UNEQ
: case LTGT
:
4389 case GT
: case GTU
: case UNGT
:
4390 case LT
: case LTU
: case UNLT
:
4391 case GE
: case GEU
: case UNGE
:
4392 case LE
: case LEU
: case UNLE
:
4393 case UNORDERED
: case ORDERED
:
4394 /* If this produces an integer result, we know which bits are set.
4395 Code here used to clear bits outside the mode of X, but that is
4397 /* Mind that MODE is the mode the caller wants to look at this
4398 operation in, and not the actual operation mode. We can wind
4399 up with (subreg:DI (gt:V4HI x y)), and we don't have anything
4400 that describes the results of a vector compare. */
4401 if (GET_MODE_CLASS (GET_MODE (x
)) == MODE_INT
4402 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
4403 nonzero
= STORE_FLAG_VALUE
;
4408 /* Disabled to avoid exponential mutual recursion between nonzero_bits
4409 and num_sign_bit_copies. */
4410 if (num_sign_bit_copies (XEXP (x
, 0), GET_MODE (x
))
4411 == GET_MODE_PRECISION (GET_MODE (x
)))
4415 if (GET_MODE_PRECISION (GET_MODE (x
)) < mode_width
)
4416 nonzero
|= (GET_MODE_MASK (mode
) & ~GET_MODE_MASK (GET_MODE (x
)));
4421 /* Disabled to avoid exponential mutual recursion between nonzero_bits
4422 and num_sign_bit_copies. */
4423 if (num_sign_bit_copies (XEXP (x
, 0), GET_MODE (x
))
4424 == GET_MODE_PRECISION (GET_MODE (x
)))
4430 nonzero
&= (cached_nonzero_bits (XEXP (x
, 0), mode
,
4431 known_x
, known_mode
, known_ret
)
4432 & GET_MODE_MASK (mode
));
4436 nonzero
&= cached_nonzero_bits (XEXP (x
, 0), mode
,
4437 known_x
, known_mode
, known_ret
);
4438 if (GET_MODE (XEXP (x
, 0)) != VOIDmode
)
4439 nonzero
&= GET_MODE_MASK (GET_MODE (XEXP (x
, 0)));
4443 /* If the sign bit is known clear, this is the same as ZERO_EXTEND.
4444 Otherwise, show all the bits in the outer mode but not the inner
4446 inner_nz
= cached_nonzero_bits (XEXP (x
, 0), mode
,
4447 known_x
, known_mode
, known_ret
);
4448 if (GET_MODE (XEXP (x
, 0)) != VOIDmode
)
4450 inner_nz
&= GET_MODE_MASK (GET_MODE (XEXP (x
, 0)));
4451 if (val_signbit_known_set_p (GET_MODE (XEXP (x
, 0)), inner_nz
))
4452 inner_nz
|= (GET_MODE_MASK (mode
)
4453 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0))));
4456 nonzero
&= inner_nz
;
4460 nonzero
&= cached_nonzero_bits (XEXP (x
, 0), mode
,
4461 known_x
, known_mode
, known_ret
)
4462 & cached_nonzero_bits (XEXP (x
, 1), mode
,
4463 known_x
, known_mode
, known_ret
);
4467 case UMIN
: case UMAX
: case SMIN
: case SMAX
:
4469 unsigned HOST_WIDE_INT nonzero0
4470 = cached_nonzero_bits (XEXP (x
, 0), mode
,
4471 known_x
, known_mode
, known_ret
);
4473 /* Don't call nonzero_bits for the second time if it cannot change
4475 if ((nonzero
& nonzero0
) != nonzero
)
4477 | cached_nonzero_bits (XEXP (x
, 1), mode
,
4478 known_x
, known_mode
, known_ret
);
4482 case PLUS
: case MINUS
:
4484 case DIV
: case UDIV
:
4485 case MOD
: case UMOD
:
4486 /* We can apply the rules of arithmetic to compute the number of
4487 high- and low-order zero bits of these operations. We start by
4488 computing the width (position of the highest-order nonzero bit)
4489 and the number of low-order zero bits for each value. */
4491 unsigned HOST_WIDE_INT nz0
4492 = cached_nonzero_bits (XEXP (x
, 0), mode
,
4493 known_x
, known_mode
, known_ret
);
4494 unsigned HOST_WIDE_INT nz1
4495 = cached_nonzero_bits (XEXP (x
, 1), mode
,
4496 known_x
, known_mode
, known_ret
);
4497 int sign_index
= GET_MODE_PRECISION (GET_MODE (x
)) - 1;
4498 int width0
= floor_log2 (nz0
) + 1;
4499 int width1
= floor_log2 (nz1
) + 1;
4500 int low0
= floor_log2 (nz0
& -nz0
);
4501 int low1
= floor_log2 (nz1
& -nz1
);
4502 unsigned HOST_WIDE_INT op0_maybe_minusp
4503 = nz0
& ((unsigned HOST_WIDE_INT
) 1 << sign_index
);
4504 unsigned HOST_WIDE_INT op1_maybe_minusp
4505 = nz1
& ((unsigned HOST_WIDE_INT
) 1 << sign_index
);
4506 unsigned int result_width
= mode_width
;
4512 result_width
= MAX (width0
, width1
) + 1;
4513 result_low
= MIN (low0
, low1
);
4516 result_low
= MIN (low0
, low1
);
4519 result_width
= width0
+ width1
;
4520 result_low
= low0
+ low1
;
4525 if (!op0_maybe_minusp
&& !op1_maybe_minusp
)
4526 result_width
= width0
;
4531 result_width
= width0
;
4536 if (!op0_maybe_minusp
&& !op1_maybe_minusp
)
4537 result_width
= MIN (width0
, width1
);
4538 result_low
= MIN (low0
, low1
);
4543 result_width
= MIN (width0
, width1
);
4544 result_low
= MIN (low0
, low1
);
4550 if (result_width
< mode_width
)
4551 nonzero
&= ((unsigned HOST_WIDE_INT
) 1 << result_width
) - 1;
4554 nonzero
&= ~(((unsigned HOST_WIDE_INT
) 1 << result_low
) - 1);
4559 if (CONST_INT_P (XEXP (x
, 1))
4560 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
)
4561 nonzero
&= ((unsigned HOST_WIDE_INT
) 1 << INTVAL (XEXP (x
, 1))) - 1;
4565 /* If this is a SUBREG formed for a promoted variable that has
4566 been zero-extended, we know that at least the high-order bits
4567 are zero, though others might be too. */
4569 if (SUBREG_PROMOTED_VAR_P (x
) && SUBREG_PROMOTED_UNSIGNED_P (x
))
4570 nonzero
= GET_MODE_MASK (GET_MODE (x
))
4571 & cached_nonzero_bits (SUBREG_REG (x
), GET_MODE (x
),
4572 known_x
, known_mode
, known_ret
);
4574 inner_mode
= GET_MODE (SUBREG_REG (x
));
4575 /* If the inner mode is a single word for both the host and target
4576 machines, we can compute this from which bits of the inner
4577 object might be nonzero. */
4578 if (GET_MODE_PRECISION (inner_mode
) <= BITS_PER_WORD
4579 && (GET_MODE_PRECISION (inner_mode
) <= HOST_BITS_PER_WIDE_INT
))
4581 nonzero
&= cached_nonzero_bits (SUBREG_REG (x
), mode
,
4582 known_x
, known_mode
, known_ret
);
4584 #if WORD_REGISTER_OPERATIONS && defined (LOAD_EXTEND_OP)
4585 /* If this is a typical RISC machine, we only have to worry
4586 about the way loads are extended. */
4587 if ((LOAD_EXTEND_OP (inner_mode
) == SIGN_EXTEND
4588 ? val_signbit_known_set_p (inner_mode
, nonzero
)
4589 : LOAD_EXTEND_OP (inner_mode
) != ZERO_EXTEND
)
4590 || !MEM_P (SUBREG_REG (x
)))
4593 /* On many CISC machines, accessing an object in a wider mode
4594 causes the high-order bits to become undefined. So they are
4595 not known to be zero. */
4596 if (GET_MODE_PRECISION (GET_MODE (x
))
4597 > GET_MODE_PRECISION (inner_mode
))
4598 nonzero
|= (GET_MODE_MASK (GET_MODE (x
))
4599 & ~GET_MODE_MASK (inner_mode
));
4608 /* The nonzero bits are in two classes: any bits within MODE
4609 that aren't in GET_MODE (x) are always significant. The rest of the
4610 nonzero bits are those that are significant in the operand of
4611 the shift when shifted the appropriate number of bits. This
4612 shows that high-order bits are cleared by the right shift and
4613 low-order bits by left shifts. */
4614 if (CONST_INT_P (XEXP (x
, 1))
4615 && INTVAL (XEXP (x
, 1)) >= 0
4616 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
4617 && INTVAL (XEXP (x
, 1)) < GET_MODE_PRECISION (GET_MODE (x
)))
4619 machine_mode inner_mode
= GET_MODE (x
);
4620 unsigned int width
= GET_MODE_PRECISION (inner_mode
);
4621 int count
= INTVAL (XEXP (x
, 1));
4622 unsigned HOST_WIDE_INT mode_mask
= GET_MODE_MASK (inner_mode
);
4623 unsigned HOST_WIDE_INT op_nonzero
4624 = cached_nonzero_bits (XEXP (x
, 0), mode
,
4625 known_x
, known_mode
, known_ret
);
4626 unsigned HOST_WIDE_INT inner
= op_nonzero
& mode_mask
;
4627 unsigned HOST_WIDE_INT outer
= 0;
4629 if (mode_width
> width
)
4630 outer
= (op_nonzero
& nonzero
& ~mode_mask
);
4632 if (code
== LSHIFTRT
)
4634 else if (code
== ASHIFTRT
)
4638 /* If the sign bit may have been nonzero before the shift, we
4639 need to mark all the places it could have been copied to
4640 by the shift as possibly nonzero. */
4641 if (inner
& ((unsigned HOST_WIDE_INT
) 1 << (width
- 1 - count
)))
4642 inner
|= (((unsigned HOST_WIDE_INT
) 1 << count
) - 1)
4645 else if (code
== ASHIFT
)
4648 inner
= ((inner
<< (count
% width
)
4649 | (inner
>> (width
- (count
% width
)))) & mode_mask
);
4651 nonzero
&= (outer
| inner
);
4657 /* This is at most the number of bits in the mode. */
4658 nonzero
= ((unsigned HOST_WIDE_INT
) 2 << (floor_log2 (mode_width
))) - 1;
4662 /* If CLZ has a known value at zero, then the nonzero bits are
4663 that value, plus the number of bits in the mode minus one. */
4664 if (CLZ_DEFINED_VALUE_AT_ZERO (mode
, nonzero
))
4666 |= ((unsigned HOST_WIDE_INT
) 1 << (floor_log2 (mode_width
))) - 1;
4672 /* If CTZ has a known value at zero, then the nonzero bits are
4673 that value, plus the number of bits in the mode minus one. */
4674 if (CTZ_DEFINED_VALUE_AT_ZERO (mode
, nonzero
))
4676 |= ((unsigned HOST_WIDE_INT
) 1 << (floor_log2 (mode_width
))) - 1;
4682 /* This is at most the number of bits in the mode minus 1. */
4683 nonzero
= ((unsigned HOST_WIDE_INT
) 1 << (floor_log2 (mode_width
))) - 1;
4692 unsigned HOST_WIDE_INT nonzero_true
4693 = cached_nonzero_bits (XEXP (x
, 1), mode
,
4694 known_x
, known_mode
, known_ret
);
4696 /* Don't call nonzero_bits for the second time if it cannot change
4698 if ((nonzero
& nonzero_true
) != nonzero
)
4699 nonzero
&= nonzero_true
4700 | cached_nonzero_bits (XEXP (x
, 2), mode
,
4701 known_x
, known_mode
, known_ret
);
4712 /* See the macro definition above. */
4713 #undef cached_num_sign_bit_copies
4716 /* Return true if num_sign_bit_copies1 might recurse into both operands
4720 num_sign_bit_copies_binary_arith_p (const_rtx x
)
4722 if (!ARITHMETIC_P (x
))
4724 switch (GET_CODE (x
))
4742 /* The function cached_num_sign_bit_copies is a wrapper around
4743 num_sign_bit_copies1. It avoids exponential behavior in
4744 num_sign_bit_copies1 when X has identical subexpressions on the
4745 first or the second level. */
4748 cached_num_sign_bit_copies (const_rtx x
, machine_mode mode
, const_rtx known_x
,
4749 machine_mode known_mode
,
4750 unsigned int known_ret
)
4752 if (x
== known_x
&& mode
== known_mode
)
4755 /* Try to find identical subexpressions. If found call
4756 num_sign_bit_copies1 on X with the subexpressions as KNOWN_X and
4757 the precomputed value for the subexpression as KNOWN_RET. */
4759 if (num_sign_bit_copies_binary_arith_p (x
))
4761 rtx x0
= XEXP (x
, 0);
4762 rtx x1
= XEXP (x
, 1);
4764 /* Check the first level. */
4767 num_sign_bit_copies1 (x
, mode
, x0
, mode
,
4768 cached_num_sign_bit_copies (x0
, mode
, known_x
,
4772 /* Check the second level. */
4773 if (num_sign_bit_copies_binary_arith_p (x0
)
4774 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
4776 num_sign_bit_copies1 (x
, mode
, x1
, mode
,
4777 cached_num_sign_bit_copies (x1
, mode
, known_x
,
4781 if (num_sign_bit_copies_binary_arith_p (x1
)
4782 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
4784 num_sign_bit_copies1 (x
, mode
, x0
, mode
,
4785 cached_num_sign_bit_copies (x0
, mode
, known_x
,
4790 return num_sign_bit_copies1 (x
, mode
, known_x
, known_mode
, known_ret
);
4793 /* Return the number of bits at the high-order end of X that are known to
4794 be equal to the sign bit. X will be used in mode MODE; if MODE is
4795 VOIDmode, X will be used in its own mode. The returned value will always
4796 be between 1 and the number of bits in MODE. */
4799 num_sign_bit_copies1 (const_rtx x
, machine_mode mode
, const_rtx known_x
,
4800 machine_mode known_mode
,
4801 unsigned int known_ret
)
4803 enum rtx_code code
= GET_CODE (x
);
4804 unsigned int bitwidth
= GET_MODE_PRECISION (mode
);
4805 int num0
, num1
, result
;
4806 unsigned HOST_WIDE_INT nonzero
;
4808 /* If we weren't given a mode, use the mode of X. If the mode is still
4809 VOIDmode, we don't know anything. Likewise if one of the modes is
4812 if (mode
== VOIDmode
)
4813 mode
= GET_MODE (x
);
4815 if (mode
== VOIDmode
|| FLOAT_MODE_P (mode
) || FLOAT_MODE_P (GET_MODE (x
))
4816 || VECTOR_MODE_P (GET_MODE (x
)) || VECTOR_MODE_P (mode
))
4819 /* For a smaller object, just ignore the high bits. */
4820 if (bitwidth
< GET_MODE_PRECISION (GET_MODE (x
)))
4822 num0
= cached_num_sign_bit_copies (x
, GET_MODE (x
),
4823 known_x
, known_mode
, known_ret
);
4825 num0
- (int) (GET_MODE_PRECISION (GET_MODE (x
)) - bitwidth
));
4828 if (GET_MODE (x
) != VOIDmode
&& bitwidth
> GET_MODE_PRECISION (GET_MODE (x
)))
4830 /* If this machine does not do all register operations on the entire
4831 register and MODE is wider than the mode of X, we can say nothing
4832 at all about the high-order bits. */
4833 if (!WORD_REGISTER_OPERATIONS
)
4836 /* Likewise on machines that do, if the mode of the object is smaller
4837 than a word and loads of that size don't sign extend, we can say
4838 nothing about the high order bits. */
4839 if (GET_MODE_PRECISION (GET_MODE (x
)) < BITS_PER_WORD
4840 #ifdef LOAD_EXTEND_OP
4841 && LOAD_EXTEND_OP (GET_MODE (x
)) != SIGN_EXTEND
4847 /* Please keep num_sign_bit_copies_binary_arith_p above in sync with
4848 the code in the switch below. */
4853 #if defined(POINTERS_EXTEND_UNSIGNED)
4854 /* If pointers extend signed and this is a pointer in Pmode, say that
4855 all the bits above ptr_mode are known to be sign bit copies. */
4856 /* As we do not know which address space the pointer is referring to,
4857 we can do this only if the target does not support different pointer
4858 or address modes depending on the address space. */
4859 if (target_default_pointer_address_modes_p ()
4860 && ! POINTERS_EXTEND_UNSIGNED
&& GET_MODE (x
) == Pmode
4861 && mode
== Pmode
&& REG_POINTER (x
)
4862 && !targetm
.have_ptr_extend ())
4863 return GET_MODE_PRECISION (Pmode
) - GET_MODE_PRECISION (ptr_mode
) + 1;
4867 unsigned int copies_for_hook
= 1, copies
= 1;
4868 rtx new_rtx
= rtl_hooks
.reg_num_sign_bit_copies (x
, mode
, known_x
,
4869 known_mode
, known_ret
,
4873 copies
= cached_num_sign_bit_copies (new_rtx
, mode
, known_x
,
4874 known_mode
, known_ret
);
4876 if (copies
> 1 || copies_for_hook
> 1)
4877 return MAX (copies
, copies_for_hook
);
4879 /* Else, use nonzero_bits to guess num_sign_bit_copies (see below). */
4884 #ifdef LOAD_EXTEND_OP
4885 /* Some RISC machines sign-extend all loads of smaller than a word. */
4886 if (LOAD_EXTEND_OP (GET_MODE (x
)) == SIGN_EXTEND
)
4887 return MAX (1, ((int) bitwidth
4888 - (int) GET_MODE_PRECISION (GET_MODE (x
)) + 1));
4893 /* If the constant is negative, take its 1's complement and remask.
4894 Then see how many zero bits we have. */
4895 nonzero
= UINTVAL (x
) & GET_MODE_MASK (mode
);
4896 if (bitwidth
<= HOST_BITS_PER_WIDE_INT
4897 && (nonzero
& ((unsigned HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0)
4898 nonzero
= (~nonzero
) & GET_MODE_MASK (mode
);
4900 return (nonzero
== 0 ? bitwidth
: bitwidth
- floor_log2 (nonzero
) - 1);
4903 /* If this is a SUBREG for a promoted object that is sign-extended
4904 and we are looking at it in a wider mode, we know that at least the
4905 high-order bits are known to be sign bit copies. */
4907 if (SUBREG_PROMOTED_VAR_P (x
) && SUBREG_PROMOTED_SIGNED_P (x
))
4909 num0
= cached_num_sign_bit_copies (SUBREG_REG (x
), mode
,
4910 known_x
, known_mode
, known_ret
);
4911 return MAX ((int) bitwidth
4912 - (int) GET_MODE_PRECISION (GET_MODE (x
)) + 1,
4916 /* For a smaller object, just ignore the high bits. */
4917 if (bitwidth
<= GET_MODE_PRECISION (GET_MODE (SUBREG_REG (x
))))
4919 num0
= cached_num_sign_bit_copies (SUBREG_REG (x
), VOIDmode
,
4920 known_x
, known_mode
, known_ret
);
4921 return MAX (1, (num0
4922 - (int) (GET_MODE_PRECISION (GET_MODE (SUBREG_REG (x
)))
4926 #ifdef LOAD_EXTEND_OP
4927 /* For paradoxical SUBREGs on machines where all register operations
4928 affect the entire register, just look inside. Note that we are
4929 passing MODE to the recursive call, so the number of sign bit copies
4930 will remain relative to that mode, not the inner mode. */
4932 /* This works only if loads sign extend. Otherwise, if we get a
4933 reload for the inner part, it may be loaded from the stack, and
4934 then we lose all sign bit copies that existed before the store
4937 if (WORD_REGISTER_OPERATIONS
4938 && paradoxical_subreg_p (x
)
4939 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x
))) == SIGN_EXTEND
4940 && MEM_P (SUBREG_REG (x
)))
4941 return cached_num_sign_bit_copies (SUBREG_REG (x
), mode
,
4942 known_x
, known_mode
, known_ret
);
4947 if (CONST_INT_P (XEXP (x
, 1)))
4948 return MAX (1, (int) bitwidth
- INTVAL (XEXP (x
, 1)));
4952 return (bitwidth
- GET_MODE_PRECISION (GET_MODE (XEXP (x
, 0)))
4953 + cached_num_sign_bit_copies (XEXP (x
, 0), VOIDmode
,
4954 known_x
, known_mode
, known_ret
));
4957 /* For a smaller object, just ignore the high bits. */
4958 num0
= cached_num_sign_bit_copies (XEXP (x
, 0), VOIDmode
,
4959 known_x
, known_mode
, known_ret
);
4960 return MAX (1, (num0
- (int) (GET_MODE_PRECISION (GET_MODE (XEXP (x
, 0)))
4964 return cached_num_sign_bit_copies (XEXP (x
, 0), mode
,
4965 known_x
, known_mode
, known_ret
);
4967 case ROTATE
: case ROTATERT
:
4968 /* If we are rotating left by a number of bits less than the number
4969 of sign bit copies, we can just subtract that amount from the
4971 if (CONST_INT_P (XEXP (x
, 1))
4972 && INTVAL (XEXP (x
, 1)) >= 0
4973 && INTVAL (XEXP (x
, 1)) < (int) bitwidth
)
4975 num0
= cached_num_sign_bit_copies (XEXP (x
, 0), mode
,
4976 known_x
, known_mode
, known_ret
);
4977 return MAX (1, num0
- (code
== ROTATE
? INTVAL (XEXP (x
, 1))
4978 : (int) bitwidth
- INTVAL (XEXP (x
, 1))));
4983 /* In general, this subtracts one sign bit copy. But if the value
4984 is known to be positive, the number of sign bit copies is the
4985 same as that of the input. Finally, if the input has just one bit
4986 that might be nonzero, all the bits are copies of the sign bit. */
4987 num0
= cached_num_sign_bit_copies (XEXP (x
, 0), mode
,
4988 known_x
, known_mode
, known_ret
);
4989 if (bitwidth
> HOST_BITS_PER_WIDE_INT
)
4990 return num0
> 1 ? num0
- 1 : 1;
4992 nonzero
= nonzero_bits (XEXP (x
, 0), mode
);
4997 && (((unsigned HOST_WIDE_INT
) 1 << (bitwidth
- 1)) & nonzero
))
5002 case IOR
: case AND
: case XOR
:
5003 case SMIN
: case SMAX
: case UMIN
: case UMAX
:
5004 /* Logical operations will preserve the number of sign-bit copies.
5005 MIN and MAX operations always return one of the operands. */
5006 num0
= cached_num_sign_bit_copies (XEXP (x
, 0), mode
,
5007 known_x
, known_mode
, known_ret
);
5008 num1
= cached_num_sign_bit_copies (XEXP (x
, 1), mode
,
5009 known_x
, known_mode
, known_ret
);
5011 /* If num1 is clearing some of the top bits then regardless of
5012 the other term, we are guaranteed to have at least that many
5013 high-order zero bits. */
5016 && bitwidth
<= HOST_BITS_PER_WIDE_INT
5017 && CONST_INT_P (XEXP (x
, 1))
5018 && (UINTVAL (XEXP (x
, 1))
5019 & ((unsigned HOST_WIDE_INT
) 1 << (bitwidth
- 1))) == 0)
5022 /* Similarly for IOR when setting high-order bits. */
5025 && bitwidth
<= HOST_BITS_PER_WIDE_INT
5026 && CONST_INT_P (XEXP (x
, 1))
5027 && (UINTVAL (XEXP (x
, 1))
5028 & ((unsigned HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0)
5031 return MIN (num0
, num1
);
5033 case PLUS
: case MINUS
:
5034 /* For addition and subtraction, we can have a 1-bit carry. However,
5035 if we are subtracting 1 from a positive number, there will not
5036 be such a carry. Furthermore, if the positive number is known to
5037 be 0 or 1, we know the result is either -1 or 0. */
5039 if (code
== PLUS
&& XEXP (x
, 1) == constm1_rtx
5040 && bitwidth
<= HOST_BITS_PER_WIDE_INT
)
5042 nonzero
= nonzero_bits (XEXP (x
, 0), mode
);
5043 if ((((unsigned HOST_WIDE_INT
) 1 << (bitwidth
- 1)) & nonzero
) == 0)
5044 return (nonzero
== 1 || nonzero
== 0 ? bitwidth
5045 : bitwidth
- floor_log2 (nonzero
) - 1);
5048 num0
= cached_num_sign_bit_copies (XEXP (x
, 0), mode
,
5049 known_x
, known_mode
, known_ret
);
5050 num1
= cached_num_sign_bit_copies (XEXP (x
, 1), mode
,
5051 known_x
, known_mode
, known_ret
);
5052 result
= MAX (1, MIN (num0
, num1
) - 1);
5057 /* The number of bits of the product is the sum of the number of
5058 bits of both terms. However, unless one of the terms if known
5059 to be positive, we must allow for an additional bit since negating
5060 a negative number can remove one sign bit copy. */
5062 num0
= cached_num_sign_bit_copies (XEXP (x
, 0), mode
,
5063 known_x
, known_mode
, known_ret
);
5064 num1
= cached_num_sign_bit_copies (XEXP (x
, 1), mode
,
5065 known_x
, known_mode
, known_ret
);
5067 result
= bitwidth
- (bitwidth
- num0
) - (bitwidth
- num1
);
5069 && (bitwidth
> HOST_BITS_PER_WIDE_INT
5070 || (((nonzero_bits (XEXP (x
, 0), mode
)
5071 & ((unsigned HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0)
5072 && ((nonzero_bits (XEXP (x
, 1), mode
)
5073 & ((unsigned HOST_WIDE_INT
) 1 << (bitwidth
- 1)))
5077 return MAX (1, result
);
5080 /* The result must be <= the first operand. If the first operand
5081 has the high bit set, we know nothing about the number of sign
5083 if (bitwidth
> HOST_BITS_PER_WIDE_INT
)
5085 else if ((nonzero_bits (XEXP (x
, 0), mode
)
5086 & ((unsigned HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0)
5089 return cached_num_sign_bit_copies (XEXP (x
, 0), mode
,
5090 known_x
, known_mode
, known_ret
);
5093 /* The result must be <= the second operand. If the second operand
5094 has (or just might have) the high bit set, we know nothing about
5095 the number of sign bit copies. */
5096 if (bitwidth
> HOST_BITS_PER_WIDE_INT
)
5098 else if ((nonzero_bits (XEXP (x
, 1), mode
)
5099 & ((unsigned HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0)
5102 return cached_num_sign_bit_copies (XEXP (x
, 1), mode
,
5103 known_x
, known_mode
, known_ret
);
5106 /* Similar to unsigned division, except that we have to worry about
5107 the case where the divisor is negative, in which case we have
5109 result
= cached_num_sign_bit_copies (XEXP (x
, 0), mode
,
5110 known_x
, known_mode
, known_ret
);
5112 && (bitwidth
> HOST_BITS_PER_WIDE_INT
5113 || (nonzero_bits (XEXP (x
, 1), mode
)
5114 & ((unsigned HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0))
5120 result
= cached_num_sign_bit_copies (XEXP (x
, 1), mode
,
5121 known_x
, known_mode
, known_ret
);
5123 && (bitwidth
> HOST_BITS_PER_WIDE_INT
5124 || (nonzero_bits (XEXP (x
, 1), mode
)
5125 & ((unsigned HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0))
5131 /* Shifts by a constant add to the number of bits equal to the
5133 num0
= cached_num_sign_bit_copies (XEXP (x
, 0), mode
,
5134 known_x
, known_mode
, known_ret
);
5135 if (CONST_INT_P (XEXP (x
, 1))
5136 && INTVAL (XEXP (x
, 1)) > 0
5137 && INTVAL (XEXP (x
, 1)) < GET_MODE_PRECISION (GET_MODE (x
)))
5138 num0
= MIN ((int) bitwidth
, num0
+ INTVAL (XEXP (x
, 1)));
5143 /* Left shifts destroy copies. */
5144 if (!CONST_INT_P (XEXP (x
, 1))
5145 || INTVAL (XEXP (x
, 1)) < 0
5146 || INTVAL (XEXP (x
, 1)) >= (int) bitwidth
5147 || INTVAL (XEXP (x
, 1)) >= GET_MODE_PRECISION (GET_MODE (x
)))
5150 num0
= cached_num_sign_bit_copies (XEXP (x
, 0), mode
,
5151 known_x
, known_mode
, known_ret
);
5152 return MAX (1, num0
- INTVAL (XEXP (x
, 1)));
5155 num0
= cached_num_sign_bit_copies (XEXP (x
, 1), mode
,
5156 known_x
, known_mode
, known_ret
);
5157 num1
= cached_num_sign_bit_copies (XEXP (x
, 2), mode
,
5158 known_x
, known_mode
, known_ret
);
5159 return MIN (num0
, num1
);
5161 case EQ
: case NE
: case GE
: case GT
: case LE
: case LT
:
5162 case UNEQ
: case LTGT
: case UNGE
: case UNGT
: case UNLE
: case UNLT
:
5163 case GEU
: case GTU
: case LEU
: case LTU
:
5164 case UNORDERED
: case ORDERED
:
5165 /* If the constant is negative, take its 1's complement and remask.
5166 Then see how many zero bits we have. */
5167 nonzero
= STORE_FLAG_VALUE
;
5168 if (bitwidth
<= HOST_BITS_PER_WIDE_INT
5169 && (nonzero
& ((unsigned HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0)
5170 nonzero
= (~nonzero
) & GET_MODE_MASK (mode
);
5172 return (nonzero
== 0 ? bitwidth
: bitwidth
- floor_log2 (nonzero
) - 1);
5178 /* If we haven't been able to figure it out by one of the above rules,
5179 see if some of the high-order bits are known to be zero. If so,
5180 count those bits and return one less than that amount. If we can't
5181 safely compute the mask for this mode, always return BITWIDTH. */
5183 bitwidth
= GET_MODE_PRECISION (mode
);
5184 if (bitwidth
> HOST_BITS_PER_WIDE_INT
)
5187 nonzero
= nonzero_bits (x
, mode
);
5188 return nonzero
& ((unsigned HOST_WIDE_INT
) 1 << (bitwidth
- 1))
5189 ? 1 : bitwidth
- floor_log2 (nonzero
) - 1;
5192 /* Calculate the rtx_cost of a single instruction. A return value of
5193 zero indicates an instruction pattern without a known cost. */
5196 insn_rtx_cost (rtx pat
, bool speed
)
5201 /* Extract the single set rtx from the instruction pattern.
5202 We can't use single_set since we only have the pattern. */
5203 if (GET_CODE (pat
) == SET
)
5205 else if (GET_CODE (pat
) == PARALLEL
)
5208 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
5210 rtx x
= XVECEXP (pat
, 0, i
);
5211 if (GET_CODE (x
) == SET
)
5224 cost
= set_src_cost (SET_SRC (set
), GET_MODE (SET_DEST (set
)), speed
);
5225 return cost
> 0 ? cost
: COSTS_N_INSNS (1);
5228 /* Returns estimate on cost of computing SEQ. */
5231 seq_cost (const rtx_insn
*seq
, bool speed
)
5236 for (; seq
; seq
= NEXT_INSN (seq
))
5238 set
= single_set (seq
);
5240 cost
+= set_rtx_cost (set
, speed
);
5248 /* Given an insn INSN and condition COND, return the condition in a
5249 canonical form to simplify testing by callers. Specifically:
5251 (1) The code will always be a comparison operation (EQ, NE, GT, etc.).
5252 (2) Both operands will be machine operands; (cc0) will have been replaced.
5253 (3) If an operand is a constant, it will be the second operand.
5254 (4) (LE x const) will be replaced with (LT x <const+1>) and similarly
5255 for GE, GEU, and LEU.
5257 If the condition cannot be understood, or is an inequality floating-point
5258 comparison which needs to be reversed, 0 will be returned.
5260 If REVERSE is nonzero, then reverse the condition prior to canonizing it.
5262 If EARLIEST is nonzero, it is a pointer to a place where the earliest
5263 insn used in locating the condition was found. If a replacement test
5264 of the condition is desired, it should be placed in front of that
5265 insn and we will be sure that the inputs are still valid.
5267 If WANT_REG is nonzero, we wish the condition to be relative to that
5268 register, if possible. Therefore, do not canonicalize the condition
5269 further. If ALLOW_CC_MODE is nonzero, allow the condition returned
5270 to be a compare to a CC mode register.
5272 If VALID_AT_INSN_P, the condition must be valid at both *EARLIEST
5276 canonicalize_condition (rtx_insn
*insn
, rtx cond
, int reverse
,
5277 rtx_insn
**earliest
,
5278 rtx want_reg
, int allow_cc_mode
, int valid_at_insn_p
)
5281 rtx_insn
*prev
= insn
;
5285 int reverse_code
= 0;
5287 basic_block bb
= BLOCK_FOR_INSN (insn
);
5289 code
= GET_CODE (cond
);
5290 mode
= GET_MODE (cond
);
5291 op0
= XEXP (cond
, 0);
5292 op1
= XEXP (cond
, 1);
5295 code
= reversed_comparison_code (cond
, insn
);
5296 if (code
== UNKNOWN
)
5302 /* If we are comparing a register with zero, see if the register is set
5303 in the previous insn to a COMPARE or a comparison operation. Perform
5304 the same tests as a function of STORE_FLAG_VALUE as find_comparison_args
5307 while ((GET_RTX_CLASS (code
) == RTX_COMPARE
5308 || GET_RTX_CLASS (code
) == RTX_COMM_COMPARE
)
5309 && op1
== CONST0_RTX (GET_MODE (op0
))
5312 /* Set nonzero when we find something of interest. */
5315 /* If comparison with cc0, import actual comparison from compare
5319 if ((prev
= prev_nonnote_insn (prev
)) == 0
5320 || !NONJUMP_INSN_P (prev
)
5321 || (set
= single_set (prev
)) == 0
5322 || SET_DEST (set
) != cc0_rtx
)
5325 op0
= SET_SRC (set
);
5326 op1
= CONST0_RTX (GET_MODE (op0
));
5331 /* If this is a COMPARE, pick up the two things being compared. */
5332 if (GET_CODE (op0
) == COMPARE
)
5334 op1
= XEXP (op0
, 1);
5335 op0
= XEXP (op0
, 0);
5338 else if (!REG_P (op0
))
5341 /* Go back to the previous insn. Stop if it is not an INSN. We also
5342 stop if it isn't a single set or if it has a REG_INC note because
5343 we don't want to bother dealing with it. */
5345 prev
= prev_nonnote_nondebug_insn (prev
);
5348 || !NONJUMP_INSN_P (prev
)
5349 || FIND_REG_INC_NOTE (prev
, NULL_RTX
)
5350 /* In cfglayout mode, there do not have to be labels at the
5351 beginning of a block, or jumps at the end, so the previous
5352 conditions would not stop us when we reach bb boundary. */
5353 || BLOCK_FOR_INSN (prev
) != bb
)
5356 set
= set_of (op0
, prev
);
5359 && (GET_CODE (set
) != SET
5360 || !rtx_equal_p (SET_DEST (set
), op0
)))
5363 /* If this is setting OP0, get what it sets it to if it looks
5367 machine_mode inner_mode
= GET_MODE (SET_DEST (set
));
5368 #ifdef FLOAT_STORE_FLAG_VALUE
5369 REAL_VALUE_TYPE fsfv
;
5372 /* ??? We may not combine comparisons done in a CCmode with
5373 comparisons not done in a CCmode. This is to aid targets
5374 like Alpha that have an IEEE compliant EQ instruction, and
5375 a non-IEEE compliant BEQ instruction. The use of CCmode is
5376 actually artificial, simply to prevent the combination, but
5377 should not affect other platforms.
5379 However, we must allow VOIDmode comparisons to match either
5380 CCmode or non-CCmode comparison, because some ports have
5381 modeless comparisons inside branch patterns.
5383 ??? This mode check should perhaps look more like the mode check
5384 in simplify_comparison in combine. */
5385 if (((GET_MODE_CLASS (mode
) == MODE_CC
)
5386 != (GET_MODE_CLASS (inner_mode
) == MODE_CC
))
5388 && inner_mode
!= VOIDmode
)
5390 if (GET_CODE (SET_SRC (set
)) == COMPARE
5393 && val_signbit_known_set_p (inner_mode
,
5395 #ifdef FLOAT_STORE_FLAG_VALUE
5397 && SCALAR_FLOAT_MODE_P (inner_mode
)
5398 && (fsfv
= FLOAT_STORE_FLAG_VALUE (inner_mode
),
5399 REAL_VALUE_NEGATIVE (fsfv
)))
5402 && COMPARISON_P (SET_SRC (set
))))
5404 else if (((code
== EQ
5406 && val_signbit_known_set_p (inner_mode
,
5408 #ifdef FLOAT_STORE_FLAG_VALUE
5410 && SCALAR_FLOAT_MODE_P (inner_mode
)
5411 && (fsfv
= FLOAT_STORE_FLAG_VALUE (inner_mode
),
5412 REAL_VALUE_NEGATIVE (fsfv
)))
5415 && COMPARISON_P (SET_SRC (set
)))
5420 else if ((code
== EQ
|| code
== NE
)
5421 && GET_CODE (SET_SRC (set
)) == XOR
)
5422 /* Handle sequences like:
5425 ...(eq|ne op0 (const_int 0))...
5429 (eq op0 (const_int 0)) reduces to (eq X Y)
5430 (ne op0 (const_int 0)) reduces to (ne X Y)
5432 This is the form used by MIPS16, for example. */
5438 else if (reg_set_p (op0
, prev
))
5439 /* If this sets OP0, but not directly, we have to give up. */
5444 /* If the caller is expecting the condition to be valid at INSN,
5445 make sure X doesn't change before INSN. */
5446 if (valid_at_insn_p
)
5447 if (modified_in_p (x
, prev
) || modified_between_p (x
, prev
, insn
))
5449 if (COMPARISON_P (x
))
5450 code
= GET_CODE (x
);
5453 code
= reversed_comparison_code (x
, prev
);
5454 if (code
== UNKNOWN
)
5459 op0
= XEXP (x
, 0), op1
= XEXP (x
, 1);
5465 /* If constant is first, put it last. */
5466 if (CONSTANT_P (op0
))
5467 code
= swap_condition (code
), tem
= op0
, op0
= op1
, op1
= tem
;
5469 /* If OP0 is the result of a comparison, we weren't able to find what
5470 was really being compared, so fail. */
5472 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_CC
)
5475 /* Canonicalize any ordered comparison with integers involving equality
5476 if we can do computations in the relevant mode and we do not
5479 if (GET_MODE_CLASS (GET_MODE (op0
)) != MODE_CC
5480 && CONST_INT_P (op1
)
5481 && GET_MODE (op0
) != VOIDmode
5482 && GET_MODE_PRECISION (GET_MODE (op0
)) <= HOST_BITS_PER_WIDE_INT
)
5484 HOST_WIDE_INT const_val
= INTVAL (op1
);
5485 unsigned HOST_WIDE_INT uconst_val
= const_val
;
5486 unsigned HOST_WIDE_INT max_val
5487 = (unsigned HOST_WIDE_INT
) GET_MODE_MASK (GET_MODE (op0
));
5492 if ((unsigned HOST_WIDE_INT
) const_val
!= max_val
>> 1)
5493 code
= LT
, op1
= gen_int_mode (const_val
+ 1, GET_MODE (op0
));
5496 /* When cross-compiling, const_val might be sign-extended from
5497 BITS_PER_WORD to HOST_BITS_PER_WIDE_INT */
5499 if ((const_val
& max_val
)
5500 != ((unsigned HOST_WIDE_INT
) 1
5501 << (GET_MODE_PRECISION (GET_MODE (op0
)) - 1)))
5502 code
= GT
, op1
= gen_int_mode (const_val
- 1, GET_MODE (op0
));
5506 if (uconst_val
< max_val
)
5507 code
= LTU
, op1
= gen_int_mode (uconst_val
+ 1, GET_MODE (op0
));
5511 if (uconst_val
!= 0)
5512 code
= GTU
, op1
= gen_int_mode (uconst_val
- 1, GET_MODE (op0
));
5520 /* Never return CC0; return zero instead. */
5524 return gen_rtx_fmt_ee (code
, VOIDmode
, op0
, op1
);
5527 /* Given a jump insn JUMP, return the condition that will cause it to branch
5528 to its JUMP_LABEL. If the condition cannot be understood, or is an
5529 inequality floating-point comparison which needs to be reversed, 0 will
5532 If EARLIEST is nonzero, it is a pointer to a place where the earliest
5533 insn used in locating the condition was found. If a replacement test
5534 of the condition is desired, it should be placed in front of that
5535 insn and we will be sure that the inputs are still valid. If EARLIEST
5536 is null, the returned condition will be valid at INSN.
5538 If ALLOW_CC_MODE is nonzero, allow the condition returned to be a
5539 compare CC mode register.
5541 VALID_AT_INSN_P is the same as for canonicalize_condition. */
5544 get_condition (rtx_insn
*jump
, rtx_insn
**earliest
, int allow_cc_mode
,
5545 int valid_at_insn_p
)
5551 /* If this is not a standard conditional jump, we can't parse it. */
5553 || ! any_condjump_p (jump
))
5555 set
= pc_set (jump
);
5557 cond
= XEXP (SET_SRC (set
), 0);
5559 /* If this branches to JUMP_LABEL when the condition is false, reverse
5562 = GET_CODE (XEXP (SET_SRC (set
), 2)) == LABEL_REF
5563 && LABEL_REF_LABEL (XEXP (SET_SRC (set
), 2)) == JUMP_LABEL (jump
);
5565 return canonicalize_condition (jump
, cond
, reverse
, earliest
, NULL_RTX
,
5566 allow_cc_mode
, valid_at_insn_p
);
5569 /* Initialize the table NUM_SIGN_BIT_COPIES_IN_REP based on
5570 TARGET_MODE_REP_EXTENDED.
5572 Note that we assume that the property of
5573 TARGET_MODE_REP_EXTENDED(B, C) is sticky to the integral modes
5574 narrower than mode B. I.e., if A is a mode narrower than B then in
5575 order to be able to operate on it in mode B, mode A needs to
5576 satisfy the requirements set by the representation of mode B. */
5579 init_num_sign_bit_copies_in_rep (void)
5581 machine_mode mode
, in_mode
;
5583 for (in_mode
= GET_CLASS_NARROWEST_MODE (MODE_INT
); in_mode
!= VOIDmode
;
5584 in_mode
= GET_MODE_WIDER_MODE (mode
))
5585 for (mode
= GET_CLASS_NARROWEST_MODE (MODE_INT
); mode
!= in_mode
;
5586 mode
= GET_MODE_WIDER_MODE (mode
))
5590 /* Currently, it is assumed that TARGET_MODE_REP_EXTENDED
5591 extends to the next widest mode. */
5592 gcc_assert (targetm
.mode_rep_extended (mode
, in_mode
) == UNKNOWN
5593 || GET_MODE_WIDER_MODE (mode
) == in_mode
);
5595 /* We are in in_mode. Count how many bits outside of mode
5596 have to be copies of the sign-bit. */
5597 for (i
= mode
; i
!= in_mode
; i
= GET_MODE_WIDER_MODE (i
))
5599 machine_mode wider
= GET_MODE_WIDER_MODE (i
);
5601 if (targetm
.mode_rep_extended (i
, wider
) == SIGN_EXTEND
5602 /* We can only check sign-bit copies starting from the
5603 top-bit. In order to be able to check the bits we
5604 have already seen we pretend that subsequent bits
5605 have to be sign-bit copies too. */
5606 || num_sign_bit_copies_in_rep
[in_mode
][mode
])
5607 num_sign_bit_copies_in_rep
[in_mode
][mode
]
5608 += GET_MODE_PRECISION (wider
) - GET_MODE_PRECISION (i
);
5613 /* Suppose that truncation from the machine mode of X to MODE is not a
5614 no-op. See if there is anything special about X so that we can
5615 assume it already contains a truncated value of MODE. */
5618 truncated_to_mode (machine_mode mode
, const_rtx x
)
5620 /* This register has already been used in MODE without explicit
5622 if (REG_P (x
) && rtl_hooks
.reg_truncated_to_mode (mode
, x
))
5625 /* See if we already satisfy the requirements of MODE. If yes we
5626 can just switch to MODE. */
5627 if (num_sign_bit_copies_in_rep
[GET_MODE (x
)][mode
]
5628 && (num_sign_bit_copies (x
, GET_MODE (x
))
5629 >= num_sign_bit_copies_in_rep
[GET_MODE (x
)][mode
] + 1))
5635 /* Return true if RTX code CODE has a single sequence of zero or more
5636 "e" operands and no rtvec operands. Initialize its rtx_all_subrtx_bounds
5637 entry in that case. */
5640 setup_reg_subrtx_bounds (unsigned int code
)
5642 const char *format
= GET_RTX_FORMAT ((enum rtx_code
) code
);
5644 for (; format
[i
] != 'e'; ++i
)
5647 /* No subrtxes. Leave start and count as 0. */
5649 if (format
[i
] == 'E' || format
[i
] == 'V')
5653 /* Record the sequence of 'e's. */
5654 rtx_all_subrtx_bounds
[code
].start
= i
;
5657 while (format
[i
] == 'e');
5658 rtx_all_subrtx_bounds
[code
].count
= i
- rtx_all_subrtx_bounds
[code
].start
;
5659 /* rtl-iter.h relies on this. */
5660 gcc_checking_assert (rtx_all_subrtx_bounds
[code
].count
<= 3);
5662 for (; format
[i
]; ++i
)
5663 if (format
[i
] == 'E' || format
[i
] == 'V' || format
[i
] == 'e')
5669 /* Initialize rtx_all_subrtx_bounds. */
5674 for (i
= 0; i
< NUM_RTX_CODE
; i
++)
5676 if (!setup_reg_subrtx_bounds (i
))
5677 rtx_all_subrtx_bounds
[i
].count
= UCHAR_MAX
;
5678 if (GET_RTX_CLASS (i
) != RTX_CONST_OBJ
)
5679 rtx_nonconst_subrtx_bounds
[i
] = rtx_all_subrtx_bounds
[i
];
5682 init_num_sign_bit_copies_in_rep ();
5685 /* Check whether this is a constant pool constant. */
5687 constant_pool_constant_p (rtx x
)
5689 x
= avoid_constant_pool_reference (x
);
5690 return CONST_DOUBLE_P (x
);
5693 /* If M is a bitmask that selects a field of low-order bits within an item but
5694 not the entire word, return the length of the field. Return -1 otherwise.
5695 M is used in machine mode MODE. */
5698 low_bitmask_len (machine_mode mode
, unsigned HOST_WIDE_INT m
)
5700 if (mode
!= VOIDmode
)
5702 if (GET_MODE_PRECISION (mode
) > HOST_BITS_PER_WIDE_INT
)
5704 m
&= GET_MODE_MASK (mode
);
5707 return exact_log2 (m
+ 1);
5710 /* Return the mode of MEM's address. */
5713 get_address_mode (rtx mem
)
5717 gcc_assert (MEM_P (mem
));
5718 mode
= GET_MODE (XEXP (mem
, 0));
5719 if (mode
!= VOIDmode
)
5721 return targetm
.addr_space
.address_mode (MEM_ADDR_SPACE (mem
));
5724 /* Split up a CONST_DOUBLE or integer constant rtx
5725 into two rtx's for single words,
5726 storing in *FIRST the word that comes first in memory in the target
5727 and in *SECOND the other.
5729 TODO: This function needs to be rewritten to work on any size
5733 split_double (rtx value
, rtx
*first
, rtx
*second
)
5735 if (CONST_INT_P (value
))
5737 if (HOST_BITS_PER_WIDE_INT
>= (2 * BITS_PER_WORD
))
5739 /* In this case the CONST_INT holds both target words.
5740 Extract the bits from it into two word-sized pieces.
5741 Sign extend each half to HOST_WIDE_INT. */
5742 unsigned HOST_WIDE_INT low
, high
;
5743 unsigned HOST_WIDE_INT mask
, sign_bit
, sign_extend
;
5744 unsigned bits_per_word
= BITS_PER_WORD
;
5746 /* Set sign_bit to the most significant bit of a word. */
5748 sign_bit
<<= bits_per_word
- 1;
5750 /* Set mask so that all bits of the word are set. We could
5751 have used 1 << BITS_PER_WORD instead of basing the
5752 calculation on sign_bit. However, on machines where
5753 HOST_BITS_PER_WIDE_INT == BITS_PER_WORD, it could cause a
5754 compiler warning, even though the code would never be
5756 mask
= sign_bit
<< 1;
5759 /* Set sign_extend as any remaining bits. */
5760 sign_extend
= ~mask
;
5762 /* Pick the lower word and sign-extend it. */
5763 low
= INTVAL (value
);
5768 /* Pick the higher word, shifted to the least significant
5769 bits, and sign-extend it. */
5770 high
= INTVAL (value
);
5771 high
>>= bits_per_word
- 1;
5774 if (high
& sign_bit
)
5775 high
|= sign_extend
;
5777 /* Store the words in the target machine order. */
5778 if (WORDS_BIG_ENDIAN
)
5780 *first
= GEN_INT (high
);
5781 *second
= GEN_INT (low
);
5785 *first
= GEN_INT (low
);
5786 *second
= GEN_INT (high
);
5791 /* The rule for using CONST_INT for a wider mode
5792 is that we regard the value as signed.
5793 So sign-extend it. */
5794 rtx high
= (INTVAL (value
) < 0 ? constm1_rtx
: const0_rtx
);
5795 if (WORDS_BIG_ENDIAN
)
5807 else if (GET_CODE (value
) == CONST_WIDE_INT
)
5809 /* All of this is scary code and needs to be converted to
5810 properly work with any size integer. */
5811 gcc_assert (CONST_WIDE_INT_NUNITS (value
) == 2);
5812 if (WORDS_BIG_ENDIAN
)
5814 *first
= GEN_INT (CONST_WIDE_INT_ELT (value
, 1));
5815 *second
= GEN_INT (CONST_WIDE_INT_ELT (value
, 0));
5819 *first
= GEN_INT (CONST_WIDE_INT_ELT (value
, 0));
5820 *second
= GEN_INT (CONST_WIDE_INT_ELT (value
, 1));
5823 else if (!CONST_DOUBLE_P (value
))
5825 if (WORDS_BIG_ENDIAN
)
5827 *first
= const0_rtx
;
5833 *second
= const0_rtx
;
5836 else if (GET_MODE (value
) == VOIDmode
5837 /* This is the old way we did CONST_DOUBLE integers. */
5838 || GET_MODE_CLASS (GET_MODE (value
)) == MODE_INT
)
5840 /* In an integer, the words are defined as most and least significant.
5841 So order them by the target's convention. */
5842 if (WORDS_BIG_ENDIAN
)
5844 *first
= GEN_INT (CONST_DOUBLE_HIGH (value
));
5845 *second
= GEN_INT (CONST_DOUBLE_LOW (value
));
5849 *first
= GEN_INT (CONST_DOUBLE_LOW (value
));
5850 *second
= GEN_INT (CONST_DOUBLE_HIGH (value
));
5857 /* Note, this converts the REAL_VALUE_TYPE to the target's
5858 format, splits up the floating point double and outputs
5859 exactly 32 bits of it into each of l[0] and l[1] --
5860 not necessarily BITS_PER_WORD bits. */
5861 REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (value
), l
);
5863 /* If 32 bits is an entire word for the target, but not for the host,
5864 then sign-extend on the host so that the number will look the same
5865 way on the host that it would on the target. See for instance
5866 simplify_unary_operation. The #if is needed to avoid compiler
5869 #if HOST_BITS_PER_LONG > 32
5870 if (BITS_PER_WORD
< HOST_BITS_PER_LONG
&& BITS_PER_WORD
== 32)
5872 if (l
[0] & ((long) 1 << 31))
5873 l
[0] |= ((unsigned long) (-1) << 32);
5874 if (l
[1] & ((long) 1 << 31))
5875 l
[1] |= ((unsigned long) (-1) << 32);
5879 *first
= GEN_INT (l
[0]);
5880 *second
= GEN_INT (l
[1]);
5884 /* Return true if X is a sign_extract or zero_extract from the least
5888 lsb_bitfield_op_p (rtx x
)
5890 if (GET_RTX_CLASS (GET_CODE (x
)) == RTX_BITFIELD_OPS
)
5892 machine_mode mode
= GET_MODE (XEXP (x
, 0));
5893 HOST_WIDE_INT len
= INTVAL (XEXP (x
, 1));
5894 HOST_WIDE_INT pos
= INTVAL (XEXP (x
, 2));
5896 return (pos
== (BITS_BIG_ENDIAN
? GET_MODE_PRECISION (mode
) - len
: 0));
5901 /* Strip outer address "mutations" from LOC and return a pointer to the
5902 inner value. If OUTER_CODE is nonnull, store the code of the innermost
5903 stripped expression there.
5905 "Mutations" either convert between modes or apply some kind of
5906 extension, truncation or alignment. */
5909 strip_address_mutations (rtx
*loc
, enum rtx_code
*outer_code
)
5913 enum rtx_code code
= GET_CODE (*loc
);
5914 if (GET_RTX_CLASS (code
) == RTX_UNARY
)
5915 /* Things like SIGN_EXTEND, ZERO_EXTEND and TRUNCATE can be
5916 used to convert between pointer sizes. */
5917 loc
= &XEXP (*loc
, 0);
5918 else if (lsb_bitfield_op_p (*loc
))
5919 /* A [SIGN|ZERO]_EXTRACT from the least significant bit effectively
5920 acts as a combined truncation and extension. */
5921 loc
= &XEXP (*loc
, 0);
5922 else if (code
== AND
&& CONST_INT_P (XEXP (*loc
, 1)))
5923 /* (and ... (const_int -X)) is used to align to X bytes. */
5924 loc
= &XEXP (*loc
, 0);
5925 else if (code
== SUBREG
5926 && !OBJECT_P (SUBREG_REG (*loc
))
5927 && subreg_lowpart_p (*loc
))
5928 /* (subreg (operator ...) ...) inside and is used for mode
5930 loc
= &SUBREG_REG (*loc
);
5938 /* Return true if CODE applies some kind of scale. The scaled value is
5939 is the first operand and the scale is the second. */
5942 binary_scale_code_p (enum rtx_code code
)
5944 return (code
== MULT
5946 /* Needed by ARM targets. */
5950 || code
== ROTATERT
);
5953 /* If *INNER can be interpreted as a base, return a pointer to the inner term
5954 (see address_info). Return null otherwise. */
5957 get_base_term (rtx
*inner
)
5959 if (GET_CODE (*inner
) == LO_SUM
)
5960 inner
= strip_address_mutations (&XEXP (*inner
, 0));
5963 || GET_CODE (*inner
) == SUBREG
5964 || GET_CODE (*inner
) == SCRATCH
)
5969 /* If *INNER can be interpreted as an index, return a pointer to the inner term
5970 (see address_info). Return null otherwise. */
5973 get_index_term (rtx
*inner
)
5975 /* At present, only constant scales are allowed. */
5976 if (binary_scale_code_p (GET_CODE (*inner
)) && CONSTANT_P (XEXP (*inner
, 1)))
5977 inner
= strip_address_mutations (&XEXP (*inner
, 0));
5980 || GET_CODE (*inner
) == SUBREG
5981 || GET_CODE (*inner
) == SCRATCH
)
5986 /* Set the segment part of address INFO to LOC, given that INNER is the
5990 set_address_segment (struct address_info
*info
, rtx
*loc
, rtx
*inner
)
5992 gcc_assert (!info
->segment
);
5993 info
->segment
= loc
;
5994 info
->segment_term
= inner
;
5997 /* Set the base part of address INFO to LOC, given that INNER is the
6001 set_address_base (struct address_info
*info
, rtx
*loc
, rtx
*inner
)
6003 gcc_assert (!info
->base
);
6005 info
->base_term
= inner
;
6008 /* Set the index part of address INFO to LOC, given that INNER is the
6012 set_address_index (struct address_info
*info
, rtx
*loc
, rtx
*inner
)
6014 gcc_assert (!info
->index
);
6016 info
->index_term
= inner
;
6019 /* Set the displacement part of address INFO to LOC, given that INNER
6020 is the constant term. */
6023 set_address_disp (struct address_info
*info
, rtx
*loc
, rtx
*inner
)
6025 gcc_assert (!info
->disp
);
6027 info
->disp_term
= inner
;
6030 /* INFO->INNER describes a {PRE,POST}_{INC,DEC} address. Set up the
6031 rest of INFO accordingly. */
6034 decompose_incdec_address (struct address_info
*info
)
6036 info
->autoinc_p
= true;
6038 rtx
*base
= &XEXP (*info
->inner
, 0);
6039 set_address_base (info
, base
, base
);
6040 gcc_checking_assert (info
->base
== info
->base_term
);
6042 /* These addresses are only valid when the size of the addressed
6044 gcc_checking_assert (info
->mode
!= VOIDmode
);
6047 /* INFO->INNER describes a {PRE,POST}_MODIFY address. Set up the rest
6048 of INFO accordingly. */
6051 decompose_automod_address (struct address_info
*info
)
6053 info
->autoinc_p
= true;
6055 rtx
*base
= &XEXP (*info
->inner
, 0);
6056 set_address_base (info
, base
, base
);
6057 gcc_checking_assert (info
->base
== info
->base_term
);
6059 rtx plus
= XEXP (*info
->inner
, 1);
6060 gcc_assert (GET_CODE (plus
) == PLUS
);
6062 info
->base_term2
= &XEXP (plus
, 0);
6063 gcc_checking_assert (rtx_equal_p (*info
->base_term
, *info
->base_term2
));
6065 rtx
*step
= &XEXP (plus
, 1);
6066 rtx
*inner_step
= strip_address_mutations (step
);
6067 if (CONSTANT_P (*inner_step
))
6068 set_address_disp (info
, step
, inner_step
);
6070 set_address_index (info
, step
, inner_step
);
6073 /* Treat *LOC as a tree of PLUS operands and store pointers to the summed
6074 values in [PTR, END). Return a pointer to the end of the used array. */
6077 extract_plus_operands (rtx
*loc
, rtx
**ptr
, rtx
**end
)
6080 if (GET_CODE (x
) == PLUS
)
6082 ptr
= extract_plus_operands (&XEXP (x
, 0), ptr
, end
);
6083 ptr
= extract_plus_operands (&XEXP (x
, 1), ptr
, end
);
6087 gcc_assert (ptr
!= end
);
6093 /* Evaluate the likelihood of X being a base or index value, returning
6094 positive if it is likely to be a base, negative if it is likely to be
6095 an index, and 0 if we can't tell. Make the magnitude of the return
6096 value reflect the amount of confidence we have in the answer.
6098 MODE, AS, OUTER_CODE and INDEX_CODE are as for ok_for_base_p_1. */
6101 baseness (rtx x
, machine_mode mode
, addr_space_t as
,
6102 enum rtx_code outer_code
, enum rtx_code index_code
)
6104 /* Believe *_POINTER unless the address shape requires otherwise. */
6105 if (REG_P (x
) && REG_POINTER (x
))
6107 if (MEM_P (x
) && MEM_POINTER (x
))
6110 if (REG_P (x
) && HARD_REGISTER_P (x
))
6112 /* X is a hard register. If it only fits one of the base
6113 or index classes, choose that interpretation. */
6114 int regno
= REGNO (x
);
6115 bool base_p
= ok_for_base_p_1 (regno
, mode
, as
, outer_code
, index_code
);
6116 bool index_p
= REGNO_OK_FOR_INDEX_P (regno
);
6117 if (base_p
!= index_p
)
6118 return base_p
? 1 : -1;
6123 /* INFO->INNER describes a normal, non-automodified address.
6124 Fill in the rest of INFO accordingly. */
6127 decompose_normal_address (struct address_info
*info
)
6129 /* Treat the address as the sum of up to four values. */
6131 size_t n_ops
= extract_plus_operands (info
->inner
, ops
,
6132 ops
+ ARRAY_SIZE (ops
)) - ops
;
6134 /* If there is more than one component, any base component is in a PLUS. */
6136 info
->base_outer_code
= PLUS
;
6138 /* Try to classify each sum operand now. Leave those that could be
6139 either a base or an index in OPS. */
6142 for (size_t in
= 0; in
< n_ops
; ++in
)
6145 rtx
*inner
= strip_address_mutations (loc
);
6146 if (CONSTANT_P (*inner
))
6147 set_address_disp (info
, loc
, inner
);
6148 else if (GET_CODE (*inner
) == UNSPEC
)
6149 set_address_segment (info
, loc
, inner
);
6152 /* The only other possibilities are a base or an index. */
6153 rtx
*base_term
= get_base_term (inner
);
6154 rtx
*index_term
= get_index_term (inner
);
6155 gcc_assert (base_term
|| index_term
);
6157 set_address_index (info
, loc
, index_term
);
6158 else if (!index_term
)
6159 set_address_base (info
, loc
, base_term
);
6162 gcc_assert (base_term
== index_term
);
6164 inner_ops
[out
] = base_term
;
6170 /* Classify the remaining OPS members as bases and indexes. */
6173 /* If we haven't seen a base or an index yet, assume that this is
6174 the base. If we were confident that another term was the base
6175 or index, treat the remaining operand as the other kind. */
6177 set_address_base (info
, ops
[0], inner_ops
[0]);
6179 set_address_index (info
, ops
[0], inner_ops
[0]);
6183 /* In the event of a tie, assume the base comes first. */
6184 if (baseness (*inner_ops
[0], info
->mode
, info
->as
, PLUS
,
6186 >= baseness (*inner_ops
[1], info
->mode
, info
->as
, PLUS
,
6187 GET_CODE (*ops
[0])))
6189 set_address_base (info
, ops
[0], inner_ops
[0]);
6190 set_address_index (info
, ops
[1], inner_ops
[1]);
6194 set_address_base (info
, ops
[1], inner_ops
[1]);
6195 set_address_index (info
, ops
[0], inner_ops
[0]);
6199 gcc_assert (out
== 0);
6202 /* Describe address *LOC in *INFO. MODE is the mode of the addressed value,
6203 or VOIDmode if not known. AS is the address space associated with LOC.
6204 OUTER_CODE is MEM if *LOC is a MEM address and ADDRESS otherwise. */
6207 decompose_address (struct address_info
*info
, rtx
*loc
, machine_mode mode
,
6208 addr_space_t as
, enum rtx_code outer_code
)
6210 memset (info
, 0, sizeof (*info
));
6213 info
->addr_outer_code
= outer_code
;
6215 info
->inner
= strip_address_mutations (loc
, &outer_code
);
6216 info
->base_outer_code
= outer_code
;
6217 switch (GET_CODE (*info
->inner
))
6223 decompose_incdec_address (info
);
6228 decompose_automod_address (info
);
6232 decompose_normal_address (info
);
6237 /* Describe address operand LOC in INFO. */
6240 decompose_lea_address (struct address_info
*info
, rtx
*loc
)
6242 decompose_address (info
, loc
, VOIDmode
, ADDR_SPACE_GENERIC
, ADDRESS
);
6245 /* Describe the address of MEM X in INFO. */
6248 decompose_mem_address (struct address_info
*info
, rtx x
)
6250 gcc_assert (MEM_P (x
));
6251 decompose_address (info
, &XEXP (x
, 0), GET_MODE (x
),
6252 MEM_ADDR_SPACE (x
), MEM
);
6255 /* Update INFO after a change to the address it describes. */
6258 update_address (struct address_info
*info
)
6260 decompose_address (info
, info
->outer
, info
->mode
, info
->as
,
6261 info
->addr_outer_code
);
6264 /* Return the scale applied to *INFO->INDEX_TERM, or 0 if the index is
6265 more complicated than that. */
6268 get_index_scale (const struct address_info
*info
)
6270 rtx index
= *info
->index
;
6271 if (GET_CODE (index
) == MULT
6272 && CONST_INT_P (XEXP (index
, 1))
6273 && info
->index_term
== &XEXP (index
, 0))
6274 return INTVAL (XEXP (index
, 1));
6276 if (GET_CODE (index
) == ASHIFT
6277 && CONST_INT_P (XEXP (index
, 1))
6278 && info
->index_term
== &XEXP (index
, 0))
6279 return (HOST_WIDE_INT
) 1 << INTVAL (XEXP (index
, 1));
6281 if (info
->index
== info
->index_term
)
6287 /* Return the "index code" of INFO, in the form required by
6291 get_index_code (const struct address_info
*info
)
6294 return GET_CODE (*info
->index
);
6297 return GET_CODE (*info
->disp
);
6302 /* Return true if RTL X contains a SYMBOL_REF. */
6305 contains_symbol_ref_p (const_rtx x
)
6307 subrtx_iterator::array_type array
;
6308 FOR_EACH_SUBRTX (iter
, array
, x
, ALL
)
6309 if (SYMBOL_REF_P (*iter
))
6315 /* Return true if RTL X contains a SYMBOL_REF or LABEL_REF. */
6318 contains_symbolic_reference_p (const_rtx x
)
6320 subrtx_iterator::array_type array
;
6321 FOR_EACH_SUBRTX (iter
, array
, x
, ALL
)
6322 if (SYMBOL_REF_P (*iter
) || GET_CODE (*iter
) == LABEL_REF
)
6328 /* Return true if X contains a thread-local symbol. */
6331 tls_referenced_p (const_rtx x
)
6333 if (!targetm
.have_tls
)
6336 subrtx_iterator::array_type array
;
6337 FOR_EACH_SUBRTX (iter
, array
, x
, ALL
)
6338 if (GET_CODE (*iter
) == SYMBOL_REF
&& SYMBOL_REF_TLS_MODEL (*iter
) != 0)