1 /* Instruction scheduling pass. Selective scheduler and pipeliner.
2 Copyright (C) 2006, 2007, 2008, 2009, 2010 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify it under
7 the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 3, or (at your option) any later
11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
22 #include "coretypes.h"
27 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "insn-attr.h"
40 #include "tree-pass.h"
41 #include "sched-int.h"
45 #include "langhooks.h"
46 #include "rtlhooks-def.h"
50 #ifdef INSN_SCHEDULING
51 #include "sel-sched-ir.h"
52 #include "sel-sched-dump.h"
53 #include "sel-sched.h"
56 /* Implementation of selective scheduling approach.
57 The below implementation follows the original approach with the following
60 o the scheduler works after register allocation (but can be also tuned
62 o some instructions are not copied or register renamed;
63 o conditional jumps are not moved with code duplication;
64 o several jumps in one parallel group are not supported;
65 o when pipelining outer loops, code motion through inner loops
67 o control and data speculation are supported;
68 o some improvements for better compile time/performance were made.
73 A vinsn, or virtual insn, is an insn with additional data characterizing
74 insn pattern, such as LHS, RHS, register sets used/set/clobbered, etc.
75 Vinsns also act as smart pointers to save memory by reusing them in
76 different expressions. A vinsn is described by vinsn_t type.
78 An expression is a vinsn with additional data characterizing its properties
79 at some point in the control flow graph. The data may be its usefulness,
80 priority, speculative status, whether it was renamed/subsituted, etc.
81 An expression is described by expr_t type.
83 Availability set (av_set) is a set of expressions at a given control flow
84 point. It is represented as av_set_t. The expressions in av sets are kept
85 sorted in the terms of expr_greater_p function. It allows to truncate
86 the set while leaving the best expressions.
88 A fence is a point through which code motion is prohibited. On each step,
89 we gather a parallel group of insns at a fence. It is possible to have
90 multiple fences. A fence is represented via fence_t.
92 A boundary is the border between the fence group and the rest of the code.
93 Currently, we never have more than one boundary per fence, as we finalize
94 the fence group when a jump is scheduled. A boundary is represented
100 The scheduler finds regions to schedule, schedules each one, and finalizes.
101 The regions are formed starting from innermost loops, so that when the inner
102 loop is pipelined, its prologue can be scheduled together with yet unprocessed
103 outer loop. The rest of acyclic regions are found using extend_rgns:
104 the blocks that are not yet allocated to any regions are traversed in top-down
105 order, and a block is added to a region to which all its predecessors belong;
106 otherwise, the block starts its own region.
108 The main scheduling loop (sel_sched_region_2) consists of just
109 scheduling on each fence and updating fences. For each fence,
110 we fill a parallel group of insns (fill_insns) until some insns can be added.
111 First, we compute available exprs (av-set) at the boundary of the current
112 group. Second, we choose the best expression from it. If the stall is
113 required to schedule any of the expressions, we advance the current cycle
114 appropriately. So, the final group does not exactly correspond to a VLIW
115 word. Third, we move the chosen expression to the boundary (move_op)
116 and update the intermediate av sets and liveness sets. We quit fill_insns
117 when either no insns left for scheduling or we have scheduled enough insns
118 so we feel like advancing a scheduling point.
120 Computing available expressions
121 ===============================
123 The computation (compute_av_set) is a bottom-up traversal. At each insn,
124 we're moving the union of its successors' sets through it via
125 moveup_expr_set. The dependent expressions are removed. Local
126 transformations (substitution, speculation) are applied to move more
127 exprs. Then the expr corresponding to the current insn is added.
128 The result is saved on each basic block header.
130 When traversing the CFG, we're moving down for no more than max_ws insns.
131 Also, we do not move down to ineligible successors (is_ineligible_successor),
132 which include moving along a back-edge, moving to already scheduled code,
133 and moving to another fence. The first two restrictions are lifted during
134 pipelining, which allows us to move insns along a back-edge. We always have
135 an acyclic region for scheduling because we forbid motion through fences.
137 Choosing the best expression
138 ============================
140 We sort the final availability set via sel_rank_for_schedule, then we remove
141 expressions which are not yet ready (tick_check_p) or which dest registers
142 cannot be used. For some of them, we choose another register via
143 find_best_reg. To do this, we run find_used_regs to calculate the set of
144 registers which cannot be used. The find_used_regs function performs
145 a traversal of code motion paths for an expr. We consider for renaming
146 only registers which are from the same regclass as the original one and
147 using which does not interfere with any live ranges. Finally, we convert
148 the resulting set to the ready list format and use max_issue and reorder*
149 hooks similarly to the Haifa scheduler.
151 Scheduling the best expression
152 ==============================
154 We run the move_op routine to perform the same type of code motion paths
155 traversal as in find_used_regs. (These are working via the same driver,
156 code_motion_path_driver.) When moving down the CFG, we look for original
157 instruction that gave birth to a chosen expression. We undo
158 the transformations performed on an expression via the history saved in it.
159 When found, we remove the instruction or leave a reg-reg copy/speculation
160 check if needed. On a way up, we insert bookkeeping copies at each join
161 point. If a copy is not needed, it will be removed later during this
162 traversal. We update the saved av sets and liveness sets on the way up, too.
164 Finalizing the schedule
165 =======================
167 When pipelining, we reschedule the blocks from which insns were pipelined
168 to get a tighter schedule. On Itanium, we also perform bundling via
169 the same routine from ia64.c.
171 Dependence analysis changes
172 ===========================
174 We augmented the sched-deps.c with hooks that get called when a particular
175 dependence is found in a particular part of an insn. Using these hooks, we
176 can do several actions such as: determine whether an insn can be moved through
177 another (has_dependence_p, moveup_expr); find out whether an insn can be
178 scheduled on the current cycle (tick_check_p); find out registers that
179 are set/used/clobbered by an insn and find out all the strange stuff that
180 restrict its movement, like SCHED_GROUP_P or CANT_MOVE (done in
181 init_global_and_expr_for_insn).
183 Initialization changes
184 ======================
186 There are parts of haifa-sched.c, sched-deps.c, and sched-rgn.c that are
187 reused in all of the schedulers. We have split up the initialization of data
188 of such parts into different functions prefixed with scheduler type and
189 postfixed with the type of data initialized: {,sel_,haifa_}sched_{init,finish},
190 sched_rgn_init/finish, sched_deps_init/finish, sched_init_{luids/bbs}, etc.
191 The same splitting is done with current_sched_info structure:
192 dependence-related parts are in sched_deps_info, common part is in
193 common_sched_info, and haifa/sel/etc part is in current_sched_info.
198 As we now have multiple-point scheduling, this would not work with backends
199 which save some of the scheduler state to use it in the target hooks.
200 For this purpose, we introduce a concept of target contexts, which
201 encapsulate such information. The backend should implement simple routines
202 of allocating/freeing/setting such a context. The scheduler calls these
203 as target hooks and handles the target context as an opaque pointer (similar
204 to the DFA state type, state_t).
209 As the correct data dependence graph is not supported during scheduling (which
210 is to be changed in mid-term), we cache as much of the dependence analysis
211 results as possible to avoid reanalyzing. This includes: bitmap caches on
212 each insn in stream of the region saying yes/no for a query with a pair of
213 UIDs; hashtables with the previously done transformations on each insn in
214 stream; a vector keeping a history of transformations on each expr.
216 Also, we try to minimize the dependence context used on each fence to check
217 whether the given expression is ready for scheduling by removing from it
218 insns that are definitely completed the execution. The results of
219 tick_check_p checks are also cached in a vector on each fence.
221 We keep a valid liveness set on each insn in a region to avoid the high
222 cost of recomputation on large basic blocks.
224 Finally, we try to minimize the number of needed updates to the availability
225 sets. The updates happen in two cases: when fill_insns terminates,
226 we advance all fences and increase the stage number to show that the region
227 has changed and the sets are to be recomputed; and when the next iteration
228 of a loop in fill_insns happens (but this one reuses the saved av sets
229 on bb headers.) Thus, we try to break the fill_insns loop only when
230 "significant" number of insns from the current scheduling window was
231 scheduled. This should be made a target param.
234 TODO: correctly support the data dependence graph at all stages and get rid
235 of all caches. This should speed up the scheduler.
236 TODO: implement moving cond jumps with bookkeeping copies on both targets.
237 TODO: tune the scheduler before RA so it does not create too much pseudos.
241 S.-M. Moon and K. Ebcioglu. Parallelizing nonnumerical code with
242 selective scheduling and software pipelining.
243 ACM TOPLAS, Vol 19, No. 6, pages 853--898, Nov. 1997.
245 Andrey Belevantsev, Maxim Kuvyrkov, Vladimir Makarov, Dmitry Melnik,
246 and Dmitry Zhurikhin. An interblock VLIW-targeted instruction scheduler
247 for GCC. In Proceedings of GCC Developers' Summit 2006.
249 Arutyun Avetisyan, Andrey Belevantsev, and Dmitry Melnik. GCC Instruction
250 Scheduler and Software Pipeliner on the Itanium Platform. EPIC-7 Workshop.
251 http://rogue.colorado.edu/EPIC7/.
255 /* True when pipelining is enabled. */
258 /* True if bookkeeping is enabled. */
261 /* Maximum number of insns that are eligible for renaming. */
262 int max_insns_to_rename
;
265 /* Definitions of local types and macros. */
267 /* Represents possible outcomes of moving an expression through an insn. */
268 enum MOVEUP_EXPR_CODE
270 /* The expression is not changed. */
273 /* Not changed, but requires a new destination register. */
276 /* Cannot be moved. */
279 /* Changed (substituted or speculated). */
283 /* The container to be passed into rtx search & replace functions. */
284 struct rtx_search_arg
286 /* What we are searching for. */
289 /* The occurence counter. */
293 typedef struct rtx_search_arg
*rtx_search_arg_p
;
295 /* This struct contains precomputed hard reg sets that are needed when
296 computing registers available for renaming. */
297 struct hard_regs_data
299 /* For every mode, this stores registers available for use with
301 HARD_REG_SET regs_for_mode
[NUM_MACHINE_MODES
];
303 /* True when regs_for_mode[mode] is initialized. */
304 bool regs_for_mode_ok
[NUM_MACHINE_MODES
];
306 /* For every register, it has regs that are ok to rename into it.
307 The register in question is always set. If not, this means
308 that the whole set is not computed yet. */
309 HARD_REG_SET regs_for_rename
[FIRST_PSEUDO_REGISTER
];
311 /* For every mode, this stores registers not available due to
313 HARD_REG_SET regs_for_call_clobbered
[NUM_MACHINE_MODES
];
315 /* All registers that are used or call used. */
316 HARD_REG_SET regs_ever_used
;
319 /* Stack registers. */
320 HARD_REG_SET stack_regs
;
324 /* Holds the results of computation of available for renaming and
325 unavailable hard registers. */
328 /* These are unavailable due to calls crossing, globalness, etc. */
329 HARD_REG_SET unavailable_hard_regs
;
331 /* These are *available* for renaming. */
332 HARD_REG_SET available_for_renaming
;
334 /* Whether this code motion path crosses a call. */
338 /* A global structure that contains the needed information about harg
340 static struct hard_regs_data sel_hrd
;
343 /* This structure holds local data used in code_motion_path_driver hooks on
344 the same or adjacent levels of recursion. Here we keep those parameters
345 that are not used in code_motion_path_driver routine itself, but only in
346 its hooks. Moreover, all parameters that can be modified in hooks are
347 in this structure, so all other parameters passed explicitly to hooks are
349 struct cmpd_local_params
351 /* Local params used in move_op_* functions. */
353 /* Edges for bookkeeping generation. */
356 /* C_EXPR merged from all successors and locally allocated temporary C_EXPR. */
357 expr_t c_expr_merged
, c_expr_local
;
359 /* Local params used in fur_* functions. */
360 /* Copy of the ORIGINAL_INSN list, stores the original insns already
361 found before entering the current level of code_motion_path_driver. */
362 def_list_t old_original_insns
;
364 /* Local params used in move_op_* functions. */
365 /* True when we have removed last insn in the block which was
366 also a boundary. Do not update anything or create bookkeeping copies. */
367 BOOL_BITFIELD removed_last_insn
: 1;
370 /* Stores the static parameters for move_op_* calls. */
371 struct moveop_static_params
373 /* Destination register. */
376 /* Current C_EXPR. */
379 /* An UID of expr_vliw which is to be moved up. If we find other exprs,
380 they are to be removed. */
383 #ifdef ENABLE_CHECKING
384 /* This is initialized to the insn on which the driver stopped its traversal. */
388 /* True if we scheduled an insn with different register. */
392 /* Stores the static parameters for fur_* calls. */
393 struct fur_static_params
395 /* Set of registers unavailable on the code motion path. */
398 /* Pointer to the list of original insns definitions. */
399 def_list_t
*original_insns
;
401 /* True if a code motion path contains a CALL insn. */
405 typedef struct fur_static_params
*fur_static_params_p
;
406 typedef struct cmpd_local_params
*cmpd_local_params_p
;
407 typedef struct moveop_static_params
*moveop_static_params_p
;
409 /* Set of hooks and parameters that determine behaviour specific to
410 move_op or find_used_regs functions. */
411 struct code_motion_path_driver_info_def
413 /* Called on enter to the basic block. */
414 int (*on_enter
) (insn_t
, cmpd_local_params_p
, void *, bool);
416 /* Called when original expr is found. */
417 void (*orig_expr_found
) (insn_t
, expr_t
, cmpd_local_params_p
, void *);
419 /* Called while descending current basic block if current insn is not
420 the original EXPR we're searching for. */
421 bool (*orig_expr_not_found
) (insn_t
, av_set_t
, void *);
423 /* Function to merge C_EXPRes from different successors. */
424 void (*merge_succs
) (insn_t
, insn_t
, int, cmpd_local_params_p
, void *);
426 /* Function to finalize merge from different successors and possibly
427 deallocate temporary data structures used for merging. */
428 void (*after_merge_succs
) (cmpd_local_params_p
, void *);
430 /* Called on the backward stage of recursion to do moveup_expr.
431 Used only with move_op_*. */
432 void (*ascend
) (insn_t
, void *);
434 /* Called on the ascending pass, before returning from the current basic
435 block or from the whole traversal. */
436 void (*at_first_insn
) (insn_t
, cmpd_local_params_p
, void *);
438 /* When processing successors in move_op we need only descend into
439 SUCCS_NORMAL successors, while in find_used_regs we need SUCCS_ALL. */
442 /* The routine name to print in dumps ("move_op" of "find_used_regs"). */
443 const char *routine_name
;
446 /* Global pointer to current hooks, either points to MOVE_OP_HOOKS or
448 struct code_motion_path_driver_info_def
*code_motion_path_driver_info
;
450 /* Set of hooks for performing move_op and find_used_regs routines with
451 code_motion_path_driver. */
452 extern struct code_motion_path_driver_info_def move_op_hooks
, fur_hooks
;
454 /* True if/when we want to emulate Haifa scheduler in the common code.
455 This is used in sched_rgn_local_init and in various places in
457 int sched_emulate_haifa_p
;
459 /* GLOBAL_LEVEL is used to discard information stored in basic block headers
460 av_sets. Av_set of bb header is valid if its (bb header's) level is equal
461 to GLOBAL_LEVEL. And invalid if lesser. This is primarily used to advance
462 scheduling window. */
465 /* Current fences. */
468 /* True when separable insns should be scheduled as RHSes. */
469 static bool enable_schedule_as_rhs_p
;
471 /* Used in verify_target_availability to assert that target reg is reported
472 unavailabile by both TARGET_UNAVAILABLE and find_used_regs only if
473 we haven't scheduled anything on the previous fence.
474 if scheduled_something_on_previous_fence is true, TARGET_UNAVAILABLE can
475 have more conservative value than the one returned by the
476 find_used_regs, thus we shouldn't assert that these values are equal. */
477 static bool scheduled_something_on_previous_fence
;
479 /* All newly emitted insns will have their uids greater than this value. */
480 static int first_emitted_uid
;
482 /* Set of basic blocks that are forced to start new ebbs. This is a subset
483 of all the ebb heads. */
484 static bitmap_head _forced_ebb_heads
;
485 bitmap_head
*forced_ebb_heads
= &_forced_ebb_heads
;
487 /* Blocks that need to be rescheduled after pipelining. */
488 bitmap blocks_to_reschedule
= NULL
;
490 /* True when the first lv set should be ignored when updating liveness. */
491 static bool ignore_first
= false;
493 /* Number of insns max_issue has initialized data structures for. */
494 static int max_issue_size
= 0;
496 /* Whether we can issue more instructions. */
497 static int can_issue_more
;
499 /* Maximum software lookahead window size, reduced when rescheduling after
503 /* Number of insns scheduled in current region. */
504 static int num_insns_scheduled
;
506 /* A vector of expressions is used to be able to sort them. */
508 DEF_VEC_ALLOC_P(expr_t
,heap
);
509 static VEC(expr_t
, heap
) *vec_av_set
= NULL
;
511 /* A vector of vinsns is used to hold temporary lists of vinsns. */
513 DEF_VEC_ALLOC_P(vinsn_t
,heap
);
514 typedef VEC(vinsn_t
, heap
) *vinsn_vec_t
;
516 /* This vector has the exprs which may still present in av_sets, but actually
517 can't be moved up due to bookkeeping created during code motion to another
518 fence. See comment near the call to update_and_record_unavailable_insns
519 for the detailed explanations. */
520 static vinsn_vec_t vec_bookkeeping_blocked_vinsns
= NULL
;
522 /* This vector has vinsns which are scheduled with renaming on the first fence
523 and then seen on the second. For expressions with such vinsns, target
524 availability information may be wrong. */
525 static vinsn_vec_t vec_target_unavailable_vinsns
= NULL
;
527 /* Vector to store temporary nops inserted in move_op to prevent removal
530 DEF_VEC_ALLOC_P(insn_t
,heap
);
531 static VEC(insn_t
, heap
) *vec_temp_moveop_nops
= NULL
;
533 /* These bitmaps record original instructions scheduled on the current
534 iteration and bookkeeping copies created by them. */
535 static bitmap current_originators
= NULL
;
536 static bitmap current_copies
= NULL
;
538 /* This bitmap marks the blocks visited by code_motion_path_driver so we don't
539 visit them afterwards. */
540 static bitmap code_motion_visited_blocks
= NULL
;
542 /* Variables to accumulate different statistics. */
544 /* The number of bookkeeping copies created. */
545 static int stat_bookkeeping_copies
;
547 /* The number of insns that required bookkeeiping for their scheduling. */
548 static int stat_insns_needed_bookkeeping
;
550 /* The number of insns that got renamed. */
551 static int stat_renamed_scheduled
;
553 /* The number of substitutions made during scheduling. */
554 static int stat_substitutions_total
;
557 /* Forward declarations of static functions. */
558 static bool rtx_ok_for_substitution_p (rtx
, rtx
);
559 static int sel_rank_for_schedule (const void *, const void *);
560 static av_set_t
find_sequential_best_exprs (bnd_t
, expr_t
, bool);
561 static basic_block
find_block_for_bookkeeping (edge e1
, edge e2
, bool lax
);
563 static rtx
get_dest_from_orig_ops (av_set_t
);
564 static basic_block
generate_bookkeeping_insn (expr_t
, edge
, edge
);
565 static bool find_used_regs (insn_t
, av_set_t
, regset
, struct reg_rename
*,
567 static bool move_op (insn_t
, av_set_t
, expr_t
, rtx
, expr_t
, bool*);
568 static int code_motion_path_driver (insn_t
, av_set_t
, ilist_t
,
569 cmpd_local_params_p
, void *);
570 static void sel_sched_region_1 (void);
571 static void sel_sched_region_2 (int);
572 static av_set_t
compute_av_set_inside_bb (insn_t
, ilist_t
, int, bool);
574 static void debug_state (state_t
);
577 /* Functions that work with fences. */
579 /* Advance one cycle on FENCE. */
581 advance_one_cycle (fence_t fence
)
587 advance_state (FENCE_STATE (fence
));
588 cycle
= ++FENCE_CYCLE (fence
);
589 FENCE_ISSUED_INSNS (fence
) = 0;
590 FENCE_STARTS_CYCLE_P (fence
) = 1;
591 can_issue_more
= issue_rate
;
592 FENCE_ISSUE_MORE (fence
) = can_issue_more
;
594 for (i
= 0; VEC_iterate (rtx
, FENCE_EXECUTING_INSNS (fence
), i
, insn
); )
596 if (INSN_READY_CYCLE (insn
) < cycle
)
598 remove_from_deps (FENCE_DC (fence
), insn
);
599 VEC_unordered_remove (rtx
, FENCE_EXECUTING_INSNS (fence
), i
);
604 if (sched_verbose
>= 2)
606 sel_print ("Finished a cycle. Current cycle = %d\n", FENCE_CYCLE (fence
));
607 debug_state (FENCE_STATE (fence
));
611 /* Returns true when SUCC in a fallthru bb of INSN, possibly
612 skipping empty basic blocks. */
614 in_fallthru_bb_p (rtx insn
, rtx succ
)
616 basic_block bb
= BLOCK_FOR_INSN (insn
);
618 if (bb
== BLOCK_FOR_INSN (succ
))
621 if (find_fallthru_edge (bb
))
622 bb
= find_fallthru_edge (bb
)->dest
;
626 while (sel_bb_empty_p (bb
))
629 return bb
== BLOCK_FOR_INSN (succ
);
632 /* Construct successor fences from OLD_FENCEs and put them in NEW_FENCES.
633 When a successor will continue a ebb, transfer all parameters of a fence
634 to the new fence. ORIG_MAX_SEQNO is the maximal seqno before this round
635 of scheduling helping to distinguish between the old and the new code. */
637 extract_new_fences_from (flist_t old_fences
, flist_tail_t new_fences
,
640 bool was_here_p
= false;
641 insn_t insn
= NULL_RTX
;
645 fence_t fence
= FLIST_FENCE (old_fences
);
648 /* Get the only element of FENCE_BNDS (fence). */
649 FOR_EACH_INSN (insn
, ii
, FENCE_BNDS (fence
))
651 gcc_assert (!was_here_p
);
654 gcc_assert (was_here_p
&& insn
!= NULL_RTX
);
656 /* When in the "middle" of the block, just move this fence
658 bb
= BLOCK_FOR_INSN (insn
);
659 if (! sel_bb_end_p (insn
)
660 || (single_succ_p (bb
)
661 && single_pred_p (single_succ (bb
))))
665 succ
= (sel_bb_end_p (insn
)
666 ? sel_bb_head (single_succ (bb
))
669 if (INSN_SEQNO (succ
) > 0
670 && INSN_SEQNO (succ
) <= orig_max_seqno
671 && INSN_SCHED_TIMES (succ
) <= 0)
673 FENCE_INSN (fence
) = succ
;
674 move_fence_to_fences (old_fences
, new_fences
);
676 if (sched_verbose
>= 1)
677 sel_print ("Fence %d continues as %d[%d] (state continue)\n",
678 INSN_UID (insn
), INSN_UID (succ
), BLOCK_NUM (succ
));
683 /* Otherwise copy fence's structures to (possibly) multiple successors. */
684 FOR_EACH_SUCC_1 (succ
, si
, insn
, SUCCS_NORMAL
| SUCCS_SKIP_TO_LOOP_EXITS
)
686 int seqno
= INSN_SEQNO (succ
);
688 if (0 < seqno
&& seqno
<= orig_max_seqno
689 && (pipelining_p
|| INSN_SCHED_TIMES (succ
) <= 0))
691 bool b
= (in_same_ebb_p (insn
, succ
)
692 || in_fallthru_bb_p (insn
, succ
));
694 if (sched_verbose
>= 1)
695 sel_print ("Fence %d continues as %d[%d] (state %s)\n",
696 INSN_UID (insn
), INSN_UID (succ
),
697 BLOCK_NUM (succ
), b
? "continue" : "reset");
700 add_dirty_fence_to_fences (new_fences
, succ
, fence
);
703 /* Mark block of the SUCC as head of the new ebb. */
704 bitmap_set_bit (forced_ebb_heads
, BLOCK_NUM (succ
));
705 add_clean_fence_to_fences (new_fences
, succ
, fence
);
712 /* Functions to support substitution. */
714 /* Returns whether INSN with dependence status DS is eligible for
715 substitution, i.e. it's a copy operation x := y, and RHS that is
716 moved up through this insn should be substituted. */
718 can_substitute_through_p (insn_t insn
, ds_t ds
)
720 /* We can substitute only true dependencies. */
721 if ((ds
& DEP_OUTPUT
)
724 || ! INSN_LHS (insn
))
727 /* Now we just need to make sure the INSN_RHS consists of only one
729 if (REG_P (INSN_LHS (insn
))
730 && REG_P (INSN_RHS (insn
)))
735 /* Substitute all occurences of INSN's destination in EXPR' vinsn with INSN's
736 source (if INSN is eligible for substitution). Returns TRUE if
737 substitution was actually performed, FALSE otherwise. Substitution might
738 be not performed because it's either EXPR' vinsn doesn't contain INSN's
739 destination or the resulting insn is invalid for the target machine.
740 When UNDO is true, perform unsubstitution instead (the difference is in
741 the part of rtx on which validate_replace_rtx is called). */
743 substitute_reg_in_expr (expr_t expr
, insn_t insn
, bool undo
)
747 vinsn_t
*vi
= &EXPR_VINSN (expr
);
748 bool has_rhs
= VINSN_RHS (*vi
) != NULL
;
751 /* Do not try to replace in SET_DEST. Although we'll choose new
752 register for the RHS, we don't want to change RHS' original reg.
753 If the insn is not SET, we may still be able to substitute something
754 in it, and if we're here (don't have deps), it doesn't write INSN's
758 : &PATTERN (VINSN_INSN_RTX (*vi
)));
759 old
= undo
? INSN_RHS (insn
) : INSN_LHS (insn
);
761 /* Substitute if INSN has a form of x:=y and LHS(INSN) occurs in *VI. */
762 if (rtx_ok_for_substitution_p (old
, *where
))
767 /* We should copy these rtxes before substitution. */
768 new_rtx
= copy_rtx (undo
? INSN_LHS (insn
) : INSN_RHS (insn
));
769 new_insn
= create_copy_of_insn_rtx (VINSN_INSN_RTX (*vi
));
771 /* Where we'll replace.
772 WHERE_REPLACE should point inside NEW_INSN, so INSN_RHS couldn't be
773 used instead of SET_SRC. */
774 where_replace
= (has_rhs
775 ? &SET_SRC (PATTERN (new_insn
))
776 : &PATTERN (new_insn
));
779 = validate_replace_rtx_part_nosimplify (old
, new_rtx
, where_replace
,
782 /* ??? Actually, constrain_operands result depends upon choice of
783 destination register. E.g. if we allow single register to be an rhs,
784 and if we try to move dx=ax(as rhs) through ax=dx, we'll result
785 in invalid insn dx=dx, so we'll loose this rhs here.
786 Just can't come up with significant testcase for this, so just
787 leaving it for now. */
790 change_vinsn_in_expr (expr
,
791 create_vinsn_from_insn_rtx (new_insn
, false));
793 /* Do not allow clobbering the address register of speculative
795 if ((EXPR_SPEC_DONE_DS (expr
) & SPECULATIVE
)
796 && bitmap_bit_p (VINSN_REG_USES (EXPR_VINSN (expr
)),
797 expr_dest_regno (expr
)))
798 EXPR_TARGET_AVAILABLE (expr
) = false;
809 /* Helper function for count_occurences_equiv. */
811 count_occurrences_1 (rtx
*cur_rtx
, void *arg
)
813 rtx_search_arg_p p
= (rtx_search_arg_p
) arg
;
815 /* The last param FOR_GCSE is true, because otherwise it performs excessive
819 for the last insn it presumes r33 equivalent to r8, so it changes it to
820 r33. Actually, there's no change, but it spoils debugging. */
821 if (exp_equiv_p (*cur_rtx
, p
->x
, 0, true))
823 /* Bail out if we occupy more than one register. */
825 && HARD_REGISTER_P (*cur_rtx
)
826 && hard_regno_nregs
[REGNO(*cur_rtx
)][GET_MODE (*cur_rtx
)] > 1)
834 /* Do not traverse subexprs. */
838 if (GET_CODE (*cur_rtx
) == SUBREG
840 && REGNO (SUBREG_REG (*cur_rtx
)) == REGNO (p
->x
))
842 /* ??? Do not support substituting regs inside subregs. In that case,
843 simplify_subreg will be called by validate_replace_rtx, and
844 unsubstitution will fail later. */
849 /* Continue search. */
853 /* Return the number of places WHAT appears within WHERE.
854 Bail out when we found a reference occupying several hard registers. */
856 count_occurrences_equiv (rtx what
, rtx where
)
858 struct rtx_search_arg arg
;
863 for_each_rtx (&where
, &count_occurrences_1
, (void *) &arg
);
868 /* Returns TRUE if WHAT is found in WHERE rtx tree. */
870 rtx_ok_for_substitution_p (rtx what
, rtx where
)
872 return (count_occurrences_equiv (what
, where
) > 0);
876 /* Functions to support register renaming. */
878 /* Substitute VI's set source with REGNO. Returns newly created pattern
879 that has REGNO as its source. */
881 create_insn_rtx_with_rhs (vinsn_t vi
, rtx rhs_rtx
)
887 lhs_rtx
= copy_rtx (VINSN_LHS (vi
));
889 pattern
= gen_rtx_SET (VOIDmode
, lhs_rtx
, rhs_rtx
);
890 insn_rtx
= create_insn_rtx_from_pattern (pattern
, NULL_RTX
);
895 /* Returns whether INSN's src can be replaced with register number
896 NEW_SRC_REG. E.g. the following insn is valid for i386:
898 (insn:HI 2205 6585 2207 727 ../../gcc/libiberty/regex.c:3337
899 (set (mem/s:QI (plus:SI (plus:SI (reg/f:SI 7 sp)
900 (reg:SI 0 ax [orig:770 c1 ] [770]))
901 (const_int 288 [0x120])) [0 str S1 A8])
902 (const_int 0 [0x0])) 43 {*movqi_1} (nil)
905 But if we change (const_int 0 [0x0]) to (reg:QI 4 si), it will be invalid
906 because of operand constraints:
908 (define_insn "*movqi_1"
909 [(set (match_operand:QI 0 "nonimmediate_operand" "=q,q ,q ,r,r ,?r,m")
910 (match_operand:QI 1 "general_operand" " q,qn,qm,q,rn,qm,qn")
913 So do constrain_operands here, before choosing NEW_SRC_REG as best
917 replace_src_with_reg_ok_p (insn_t insn
, rtx new_src_reg
)
919 vinsn_t vi
= INSN_VINSN (insn
);
920 enum machine_mode mode
;
924 gcc_assert (VINSN_SEPARABLE_P (vi
));
926 get_dest_and_mode (insn
, &dst_loc
, &mode
);
927 gcc_assert (mode
== GET_MODE (new_src_reg
));
929 if (REG_P (dst_loc
) && REGNO (new_src_reg
) == REGNO (dst_loc
))
932 /* See whether SET_SRC can be replaced with this register. */
933 validate_change (insn
, &SET_SRC (PATTERN (insn
)), new_src_reg
, 1);
934 res
= verify_changes (0);
940 /* Returns whether INSN still be valid after replacing it's DEST with
943 replace_dest_with_reg_ok_p (insn_t insn
, rtx new_reg
)
945 vinsn_t vi
= INSN_VINSN (insn
);
948 /* We should deal here only with separable insns. */
949 gcc_assert (VINSN_SEPARABLE_P (vi
));
950 gcc_assert (GET_MODE (VINSN_LHS (vi
)) == GET_MODE (new_reg
));
952 /* See whether SET_DEST can be replaced with this register. */
953 validate_change (insn
, &SET_DEST (PATTERN (insn
)), new_reg
, 1);
954 res
= verify_changes (0);
960 /* Create a pattern with rhs of VI and lhs of LHS_RTX. */
962 create_insn_rtx_with_lhs (vinsn_t vi
, rtx lhs_rtx
)
968 rhs_rtx
= copy_rtx (VINSN_RHS (vi
));
970 pattern
= gen_rtx_SET (VOIDmode
, lhs_rtx
, rhs_rtx
);
971 insn_rtx
= create_insn_rtx_from_pattern (pattern
, NULL_RTX
);
976 /* Substitute lhs in the given expression EXPR for the register with number
977 NEW_REGNO. SET_DEST may be arbitrary rtx, not only register. */
979 replace_dest_with_reg_in_expr (expr_t expr
, rtx new_reg
)
984 insn_rtx
= create_insn_rtx_with_lhs (EXPR_VINSN (expr
), new_reg
);
985 vinsn
= create_vinsn_from_insn_rtx (insn_rtx
, false);
987 change_vinsn_in_expr (expr
, vinsn
);
988 EXPR_WAS_RENAMED (expr
) = 1;
989 EXPR_TARGET_AVAILABLE (expr
) = 1;
992 /* Returns whether VI writes either one of the USED_REGS registers or,
993 if a register is a hard one, one of the UNAVAILABLE_HARD_REGS registers. */
995 vinsn_writes_one_of_regs_p (vinsn_t vi
, regset used_regs
,
996 HARD_REG_SET unavailable_hard_regs
)
999 reg_set_iterator rsi
;
1001 EXECUTE_IF_SET_IN_REG_SET (VINSN_REG_SETS (vi
), 0, regno
, rsi
)
1003 if (REGNO_REG_SET_P (used_regs
, regno
))
1005 if (HARD_REGISTER_NUM_P (regno
)
1006 && TEST_HARD_REG_BIT (unavailable_hard_regs
, regno
))
1010 EXECUTE_IF_SET_IN_REG_SET (VINSN_REG_CLOBBERS (vi
), 0, regno
, rsi
)
1012 if (REGNO_REG_SET_P (used_regs
, regno
))
1014 if (HARD_REGISTER_NUM_P (regno
)
1015 && TEST_HARD_REG_BIT (unavailable_hard_regs
, regno
))
1022 /* Returns register class of the output register in INSN.
1023 Returns NO_REGS for call insns because some targets have constraints on
1024 destination register of a call insn.
1026 Code adopted from regrename.c::build_def_use. */
1027 static enum reg_class
1028 get_reg_class (rtx insn
)
1032 extract_insn (insn
);
1033 if (! constrain_operands (1))
1034 fatal_insn_not_found (insn
);
1035 preprocess_constraints ();
1036 alt
= which_alternative
;
1037 n_ops
= recog_data
.n_operands
;
1039 for (i
= 0; i
< n_ops
; ++i
)
1041 int matches
= recog_op_alt
[i
][alt
].matches
;
1043 recog_op_alt
[i
][alt
].cl
= recog_op_alt
[matches
][alt
].cl
;
1046 if (asm_noperands (PATTERN (insn
)) > 0)
1048 for (i
= 0; i
< n_ops
; i
++)
1049 if (recog_data
.operand_type
[i
] == OP_OUT
)
1051 rtx
*loc
= recog_data
.operand_loc
[i
];
1053 enum reg_class cl
= recog_op_alt
[i
][alt
].cl
;
1056 && REGNO (op
) == ORIGINAL_REGNO (op
))
1062 else if (!CALL_P (insn
))
1064 for (i
= 0; i
< n_ops
+ recog_data
.n_dups
; i
++)
1066 int opn
= i
< n_ops
? i
: recog_data
.dup_num
[i
- n_ops
];
1067 enum reg_class cl
= recog_op_alt
[opn
][alt
].cl
;
1069 if (recog_data
.operand_type
[opn
] == OP_OUT
||
1070 recog_data
.operand_type
[opn
] == OP_INOUT
)
1076 (insn (set (reg:CCZ 17 flags) (compare:CCZ ...)))
1077 may result in returning NO_REGS, cause flags is written implicitly through
1078 CMP insn, which has no OP_OUT | OP_INOUT operands. */
1082 #ifdef HARD_REGNO_RENAME_OK
1083 /* Calculate HARD_REGNO_RENAME_OK data for REGNO. */
1085 init_hard_regno_rename (int regno
)
1089 SET_HARD_REG_BIT (sel_hrd
.regs_for_rename
[regno
], regno
);
1091 for (cur_reg
= 0; cur_reg
< FIRST_PSEUDO_REGISTER
; cur_reg
++)
1093 /* We are not interested in renaming in other regs. */
1094 if (!TEST_HARD_REG_BIT (sel_hrd
.regs_ever_used
, cur_reg
))
1097 if (HARD_REGNO_RENAME_OK (regno
, cur_reg
))
1098 SET_HARD_REG_BIT (sel_hrd
.regs_for_rename
[regno
], cur_reg
);
1103 /* A wrapper around HARD_REGNO_RENAME_OK that will look into the hard regs
1106 sel_hard_regno_rename_ok (int from ATTRIBUTE_UNUSED
, int to ATTRIBUTE_UNUSED
)
1108 #ifdef HARD_REGNO_RENAME_OK
1109 /* Check whether this is all calculated. */
1110 if (TEST_HARD_REG_BIT (sel_hrd
.regs_for_rename
[from
], from
))
1111 return TEST_HARD_REG_BIT (sel_hrd
.regs_for_rename
[from
], to
);
1113 init_hard_regno_rename (from
);
1115 return TEST_HARD_REG_BIT (sel_hrd
.regs_for_rename
[from
], to
);
1121 /* Calculate set of registers that are capable of holding MODE. */
1123 init_regs_for_mode (enum machine_mode mode
)
1127 CLEAR_HARD_REG_SET (sel_hrd
.regs_for_mode
[mode
]);
1128 CLEAR_HARD_REG_SET (sel_hrd
.regs_for_call_clobbered
[mode
]);
1130 for (cur_reg
= 0; cur_reg
< FIRST_PSEUDO_REGISTER
; cur_reg
++)
1132 int nregs
= hard_regno_nregs
[cur_reg
][mode
];
1135 for (i
= nregs
- 1; i
>= 0; --i
)
1136 if (fixed_regs
[cur_reg
+ i
]
1137 || global_regs
[cur_reg
+ i
]
1138 /* Can't use regs which aren't saved by
1140 || !TEST_HARD_REG_BIT (sel_hrd
.regs_ever_used
, cur_reg
+ i
)
1141 #ifdef LEAF_REGISTERS
1142 /* We can't use a non-leaf register if we're in a
1144 || (current_function_is_leaf
1145 && !LEAF_REGISTERS
[cur_reg
+ i
])
1153 /* See whether it accepts all modes that occur in
1155 if (! HARD_REGNO_MODE_OK (cur_reg
, mode
))
1158 if (HARD_REGNO_CALL_PART_CLOBBERED (cur_reg
, mode
))
1159 SET_HARD_REG_BIT (sel_hrd
.regs_for_call_clobbered
[mode
],
1162 /* If the CUR_REG passed all the checks above,
1164 SET_HARD_REG_BIT (sel_hrd
.regs_for_mode
[mode
], cur_reg
);
1167 sel_hrd
.regs_for_mode_ok
[mode
] = true;
1170 /* Init all register sets gathered in HRD. */
1172 init_hard_regs_data (void)
1177 CLEAR_HARD_REG_SET (sel_hrd
.regs_ever_used
);
1178 for (cur_reg
= 0; cur_reg
< FIRST_PSEUDO_REGISTER
; cur_reg
++)
1179 if (df_regs_ever_live_p (cur_reg
) || call_used_regs
[cur_reg
])
1180 SET_HARD_REG_BIT (sel_hrd
.regs_ever_used
, cur_reg
);
1182 /* Initialize registers that are valid based on mode when this is
1184 for (cur_mode
= 0; cur_mode
< NUM_MACHINE_MODES
; cur_mode
++)
1185 sel_hrd
.regs_for_mode_ok
[cur_mode
] = false;
1187 /* Mark that all HARD_REGNO_RENAME_OK is not calculated. */
1188 for (cur_reg
= 0; cur_reg
< FIRST_PSEUDO_REGISTER
; cur_reg
++)
1189 CLEAR_HARD_REG_SET (sel_hrd
.regs_for_rename
[cur_reg
]);
1192 CLEAR_HARD_REG_SET (sel_hrd
.stack_regs
);
1194 for (cur_reg
= FIRST_STACK_REG
; cur_reg
<= LAST_STACK_REG
; cur_reg
++)
1195 SET_HARD_REG_BIT (sel_hrd
.stack_regs
, cur_reg
);
1199 /* Mark hardware regs in REG_RENAME_P that are not suitable
1200 for renaming rhs in INSN due to hardware restrictions (register class,
1201 modes compatibility etc). This doesn't affect original insn's dest reg,
1202 if it isn't in USED_REGS. DEF is a definition insn of rhs for which the
1203 destination register is sought. LHS (DEF->ORIG_INSN) may be REG or MEM.
1204 Registers that are in used_regs are always marked in
1205 unavailable_hard_regs as well. */
1208 mark_unavailable_hard_regs (def_t def
, struct reg_rename
*reg_rename_p
,
1209 regset used_regs ATTRIBUTE_UNUSED
)
1211 enum machine_mode mode
;
1212 enum reg_class cl
= NO_REGS
;
1214 unsigned cur_reg
, regno
;
1215 hard_reg_set_iterator hrsi
;
1217 gcc_assert (GET_CODE (PATTERN (def
->orig_insn
)) == SET
);
1218 gcc_assert (reg_rename_p
);
1220 orig_dest
= SET_DEST (PATTERN (def
->orig_insn
));
1222 /* We have decided not to rename 'mem = something;' insns, as 'something'
1223 is usually a register. */
1224 if (!REG_P (orig_dest
))
1227 regno
= REGNO (orig_dest
);
1229 /* If before reload, don't try to work with pseudos. */
1230 if (!reload_completed
&& !HARD_REGISTER_NUM_P (regno
))
1233 if (reload_completed
)
1234 cl
= get_reg_class (def
->orig_insn
);
1236 /* Stop if the original register is one of the fixed_regs, global_regs or
1237 frame pointer, or we could not discover its class. */
1238 if (fixed_regs
[regno
]
1239 || global_regs
[regno
]
1240 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
1241 || (frame_pointer_needed
&& regno
== HARD_FRAME_POINTER_REGNUM
)
1243 || (frame_pointer_needed
&& regno
== FRAME_POINTER_REGNUM
)
1245 || (reload_completed
&& cl
== NO_REGS
))
1247 SET_HARD_REG_SET (reg_rename_p
->unavailable_hard_regs
);
1249 /* Give a chance for original register, if it isn't in used_regs. */
1250 if (!def
->crosses_call
)
1251 CLEAR_HARD_REG_BIT (reg_rename_p
->unavailable_hard_regs
, regno
);
1256 /* If something allocated on stack in this function, mark frame pointer
1257 register unavailable, considering also modes.
1258 FIXME: it is enough to do this once per all original defs. */
1259 if (frame_pointer_needed
)
1263 for (i
= hard_regno_nregs
[FRAME_POINTER_REGNUM
][Pmode
]; i
--;)
1264 SET_HARD_REG_BIT (reg_rename_p
->unavailable_hard_regs
,
1265 FRAME_POINTER_REGNUM
+ i
);
1267 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
1268 for (i
= hard_regno_nregs
[HARD_FRAME_POINTER_REGNUM
][Pmode
]; i
--;)
1269 SET_HARD_REG_BIT (reg_rename_p
->unavailable_hard_regs
,
1270 HARD_FRAME_POINTER_REGNUM
+ i
);
1275 /* For the stack registers the presence of FIRST_STACK_REG in USED_REGS
1276 is equivalent to as if all stack regs were in this set.
1277 I.e. no stack register can be renamed, and even if it's an original
1278 register here we make sure it won't be lifted over it's previous def
1279 (it's previous def will appear as if it's a FIRST_STACK_REG def.
1280 The HARD_REGNO_RENAME_OK covers other cases in condition below. */
1281 if (IN_RANGE (REGNO (orig_dest
), FIRST_STACK_REG
, LAST_STACK_REG
)
1282 && REGNO_REG_SET_P (used_regs
, FIRST_STACK_REG
))
1283 IOR_HARD_REG_SET (reg_rename_p
->unavailable_hard_regs
,
1284 sel_hrd
.stack_regs
);
1287 /* If there's a call on this path, make regs from call_used_reg_set
1289 if (def
->crosses_call
)
1290 IOR_HARD_REG_SET (reg_rename_p
->unavailable_hard_regs
,
1293 /* Stop here before reload: we need FRAME_REGS, STACK_REGS, and crosses_call,
1294 but not register classes. */
1295 if (!reload_completed
)
1298 /* Leave regs as 'available' only from the current
1300 COPY_HARD_REG_SET (reg_rename_p
->available_for_renaming
,
1301 reg_class_contents
[cl
]);
1303 mode
= GET_MODE (orig_dest
);
1305 /* Leave only registers available for this mode. */
1306 if (!sel_hrd
.regs_for_mode_ok
[mode
])
1307 init_regs_for_mode (mode
);
1308 AND_HARD_REG_SET (reg_rename_p
->available_for_renaming
,
1309 sel_hrd
.regs_for_mode
[mode
]);
1311 /* Exclude registers that are partially call clobbered. */
1312 if (def
->crosses_call
1313 && ! HARD_REGNO_CALL_PART_CLOBBERED (regno
, mode
))
1314 AND_COMPL_HARD_REG_SET (reg_rename_p
->available_for_renaming
,
1315 sel_hrd
.regs_for_call_clobbered
[mode
]);
1317 /* Leave only those that are ok to rename. */
1318 EXECUTE_IF_SET_IN_HARD_REG_SET (reg_rename_p
->available_for_renaming
,
1324 nregs
= hard_regno_nregs
[cur_reg
][mode
];
1325 gcc_assert (nregs
> 0);
1327 for (i
= nregs
- 1; i
>= 0; --i
)
1328 if (! sel_hard_regno_rename_ok (regno
+ i
, cur_reg
+ i
))
1332 CLEAR_HARD_REG_BIT (reg_rename_p
->available_for_renaming
,
1336 AND_COMPL_HARD_REG_SET (reg_rename_p
->available_for_renaming
,
1337 reg_rename_p
->unavailable_hard_regs
);
1339 /* Regno is always ok from the renaming part of view, but it really
1340 could be in *unavailable_hard_regs already, so set it here instead
1342 SET_HARD_REG_BIT (reg_rename_p
->available_for_renaming
, regno
);
1345 /* reg_rename_tick[REG1] > reg_rename_tick[REG2] if REG1 was chosen as the
1346 best register more recently than REG2. */
1347 static int reg_rename_tick
[FIRST_PSEUDO_REGISTER
];
1349 /* Indicates the number of times renaming happened before the current one. */
1350 static int reg_rename_this_tick
;
1352 /* Choose the register among free, that is suitable for storing
1355 ORIGINAL_INSNS is the list of insns where the operation (rhs)
1356 originally appears. There could be multiple original operations
1357 for single rhs since we moving it up and merging along different
1360 Some code is adapted from regrename.c (regrename_optimize).
1361 If original register is available, function returns it.
1362 Otherwise it performs the checks, so the new register should
1363 comply with the following:
1364 - it should not violate any live ranges (such registers are in
1365 REG_RENAME_P->available_for_renaming set);
1366 - it should not be in the HARD_REGS_USED regset;
1367 - it should be in the class compatible with original uses;
1368 - it should not be clobbered through reference with different mode;
1369 - if we're in the leaf function, then the new register should
1370 not be in the LEAF_REGISTERS;
1373 If several registers meet the conditions, the register with smallest
1374 tick is returned to achieve more even register allocation.
1376 If original register seems to be ok, we set *IS_ORIG_REG_P_PTR to true.
1378 If no register satisfies the above conditions, NULL_RTX is returned. */
1380 choose_best_reg_1 (HARD_REG_SET hard_regs_used
,
1381 struct reg_rename
*reg_rename_p
,
1382 def_list_t original_insns
, bool *is_orig_reg_p_ptr
)
1386 enum machine_mode mode
= VOIDmode
;
1387 unsigned regno
, i
, n
;
1388 hard_reg_set_iterator hrsi
;
1389 def_list_iterator di
;
1392 /* If original register is available, return it. */
1393 *is_orig_reg_p_ptr
= true;
1395 FOR_EACH_DEF (def
, di
, original_insns
)
1397 rtx orig_dest
= SET_DEST (PATTERN (def
->orig_insn
));
1399 gcc_assert (REG_P (orig_dest
));
1401 /* Check that all original operations have the same mode.
1402 This is done for the next loop; if we'd return from this
1403 loop, we'd check only part of them, but in this case
1404 it doesn't matter. */
1405 if (mode
== VOIDmode
)
1406 mode
= GET_MODE (orig_dest
);
1407 gcc_assert (mode
== GET_MODE (orig_dest
));
1409 regno
= REGNO (orig_dest
);
1410 for (i
= 0, n
= hard_regno_nregs
[regno
][mode
]; i
< n
; i
++)
1411 if (TEST_HARD_REG_BIT (hard_regs_used
, regno
+ i
))
1414 /* All hard registers are available. */
1417 gcc_assert (mode
!= VOIDmode
);
1419 /* Hard registers should not be shared. */
1420 return gen_rtx_REG (mode
, regno
);
1424 *is_orig_reg_p_ptr
= false;
1427 /* Among all available regs choose the register that was
1428 allocated earliest. */
1429 EXECUTE_IF_SET_IN_HARD_REG_SET (reg_rename_p
->available_for_renaming
,
1431 if (! TEST_HARD_REG_BIT (hard_regs_used
, cur_reg
))
1433 /* Check that all hard regs for mode are available. */
1434 for (i
= 1, n
= hard_regno_nregs
[cur_reg
][mode
]; i
< n
; i
++)
1435 if (TEST_HARD_REG_BIT (hard_regs_used
, cur_reg
+ i
)
1436 || !TEST_HARD_REG_BIT (reg_rename_p
->available_for_renaming
,
1443 /* All hard registers are available. */
1444 if (best_new_reg
< 0
1445 || reg_rename_tick
[cur_reg
] < reg_rename_tick
[best_new_reg
])
1447 best_new_reg
= cur_reg
;
1449 /* Return immediately when we know there's no better reg. */
1450 if (! reg_rename_tick
[best_new_reg
])
1455 if (best_new_reg
>= 0)
1457 /* Use the check from the above loop. */
1458 gcc_assert (mode
!= VOIDmode
);
1459 return gen_rtx_REG (mode
, best_new_reg
);
1465 /* A wrapper around choose_best_reg_1 () to verify that we make correct
1466 assumptions about available registers in the function. */
1468 choose_best_reg (HARD_REG_SET hard_regs_used
, struct reg_rename
*reg_rename_p
,
1469 def_list_t original_insns
, bool *is_orig_reg_p_ptr
)
1471 rtx best_reg
= choose_best_reg_1 (hard_regs_used
, reg_rename_p
,
1472 original_insns
, is_orig_reg_p_ptr
);
1474 /* FIXME loop over hard_regno_nregs here. */
1475 gcc_assert (best_reg
== NULL_RTX
1476 || TEST_HARD_REG_BIT (sel_hrd
.regs_ever_used
, REGNO (best_reg
)));
1481 /* Choose the pseudo register for storing rhs value. As this is supposed
1482 to work before reload, we return either the original register or make
1483 the new one. The parameters are the same that in choose_nest_reg_1
1484 functions, except that USED_REGS may contain pseudos.
1485 If we work with hard regs, check also REG_RENAME_P->UNAVAILABLE_HARD_REGS.
1487 TODO: take into account register pressure while doing this. Up to this
1488 moment, this function would never return NULL for pseudos, but we should
1489 not rely on this. */
1491 choose_best_pseudo_reg (regset used_regs
,
1492 struct reg_rename
*reg_rename_p
,
1493 def_list_t original_insns
, bool *is_orig_reg_p_ptr
)
1495 def_list_iterator i
;
1497 enum machine_mode mode
= VOIDmode
;
1498 bool bad_hard_regs
= false;
1500 /* We should not use this after reload. */
1501 gcc_assert (!reload_completed
);
1503 /* If original register is available, return it. */
1504 *is_orig_reg_p_ptr
= true;
1506 FOR_EACH_DEF (def
, i
, original_insns
)
1508 rtx dest
= SET_DEST (PATTERN (def
->orig_insn
));
1511 gcc_assert (REG_P (dest
));
1513 /* Check that all original operations have the same mode. */
1514 if (mode
== VOIDmode
)
1515 mode
= GET_MODE (dest
);
1517 gcc_assert (mode
== GET_MODE (dest
));
1518 orig_regno
= REGNO (dest
);
1520 if (!REGNO_REG_SET_P (used_regs
, orig_regno
))
1522 if (orig_regno
< FIRST_PSEUDO_REGISTER
)
1524 gcc_assert (df_regs_ever_live_p (orig_regno
));
1526 /* For hard registers, we have to check hardware imposed
1527 limitations (frame/stack registers, calls crossed). */
1528 if (!TEST_HARD_REG_BIT (reg_rename_p
->unavailable_hard_regs
,
1531 /* Don't let register cross a call if it doesn't already
1532 cross one. This condition is written in accordance with
1533 that in sched-deps.c sched_analyze_reg(). */
1534 if (!reg_rename_p
->crosses_call
1535 || REG_N_CALLS_CROSSED (orig_regno
) > 0)
1536 return gen_rtx_REG (mode
, orig_regno
);
1539 bad_hard_regs
= true;
1546 *is_orig_reg_p_ptr
= false;
1548 /* We had some original hard registers that couldn't be used.
1549 Those were likely special. Don't try to create a pseudo. */
1553 /* We haven't found a register from original operations. Get a new one.
1554 FIXME: control register pressure somehow. */
1556 rtx new_reg
= gen_reg_rtx (mode
);
1558 gcc_assert (mode
!= VOIDmode
);
1560 max_regno
= max_reg_num ();
1561 maybe_extend_reg_info_p ();
1562 REG_N_CALLS_CROSSED (REGNO (new_reg
)) = reg_rename_p
->crosses_call
? 1 : 0;
1568 /* True when target of EXPR is available due to EXPR_TARGET_AVAILABLE,
1569 USED_REGS and REG_RENAME_P->UNAVAILABLE_HARD_REGS. */
1571 verify_target_availability (expr_t expr
, regset used_regs
,
1572 struct reg_rename
*reg_rename_p
)
1574 unsigned n
, i
, regno
;
1575 enum machine_mode mode
;
1576 bool target_available
, live_available
, hard_available
;
1578 if (!REG_P (EXPR_LHS (expr
)) || EXPR_TARGET_AVAILABLE (expr
) < 0)
1581 regno
= expr_dest_regno (expr
);
1582 mode
= GET_MODE (EXPR_LHS (expr
));
1583 target_available
= EXPR_TARGET_AVAILABLE (expr
) == 1;
1584 n
= reload_completed
? hard_regno_nregs
[regno
][mode
] : 1;
1586 live_available
= hard_available
= true;
1587 for (i
= 0; i
< n
; i
++)
1589 if (bitmap_bit_p (used_regs
, regno
+ i
))
1590 live_available
= false;
1591 if (TEST_HARD_REG_BIT (reg_rename_p
->unavailable_hard_regs
, regno
+ i
))
1592 hard_available
= false;
1595 /* When target is not available, it may be due to hard register
1596 restrictions, e.g. crosses calls, so we check hard_available too. */
1597 if (target_available
)
1598 gcc_assert (live_available
);
1600 /* Check only if we haven't scheduled something on the previous fence,
1601 cause due to MAX_SOFTWARE_LOOKAHEAD_WINDOW_SIZE issues
1602 and having more than one fence, we may end having targ_un in a block
1603 in which successors target register is actually available.
1605 The last condition handles the case when a dependence from a call insn
1606 was created in sched-deps.c for insns with destination registers that
1607 never crossed a call before, but do cross one after our code motion.
1609 FIXME: in the latter case, we just uselessly called find_used_regs,
1610 because we can't move this expression with any other register
1612 gcc_assert (scheduled_something_on_previous_fence
|| !live_available
1614 || (!reload_completed
&& reg_rename_p
->crosses_call
1615 && REG_N_CALLS_CROSSED (regno
) == 0));
1618 /* Collect unavailable registers due to liveness for EXPR from BNDS
1619 into USED_REGS. Save additional information about available
1620 registers and unavailable due to hardware restriction registers
1621 into REG_RENAME_P structure. Save original insns into ORIGINAL_INSNS
1624 collect_unavailable_regs_from_bnds (expr_t expr
, blist_t bnds
, regset used_regs
,
1625 struct reg_rename
*reg_rename_p
,
1626 def_list_t
*original_insns
)
1628 for (; bnds
; bnds
= BLIST_NEXT (bnds
))
1631 av_set_t orig_ops
= NULL
;
1632 bnd_t bnd
= BLIST_BND (bnds
);
1634 /* If the chosen best expr doesn't belong to current boundary,
1636 if (!av_set_is_in_p (BND_AV1 (bnd
), EXPR_VINSN (expr
)))
1639 /* Put in ORIG_OPS all exprs from this boundary that became
1641 orig_ops
= find_sequential_best_exprs (bnd
, expr
, false);
1643 /* Compute used regs and OR it into the USED_REGS. */
1644 res
= find_used_regs (BND_TO (bnd
), orig_ops
, used_regs
,
1645 reg_rename_p
, original_insns
);
1647 /* FIXME: the assert is true until we'd have several boundaries. */
1649 av_set_clear (&orig_ops
);
1653 /* Return TRUE if it is possible to replace LHSes of ORIG_INSNS with BEST_REG.
1654 If BEST_REG is valid, replace LHS of EXPR with it. */
1656 try_replace_dest_reg (ilist_t orig_insns
, rtx best_reg
, expr_t expr
)
1658 /* Try whether we'll be able to generate the insn
1659 'dest := best_reg' at the place of the original operation. */
1660 for (; orig_insns
; orig_insns
= ILIST_NEXT (orig_insns
))
1662 insn_t orig_insn
= DEF_LIST_DEF (orig_insns
)->orig_insn
;
1664 gcc_assert (EXPR_SEPARABLE_P (INSN_EXPR (orig_insn
)));
1666 if (REGNO (best_reg
) != REGNO (INSN_LHS (orig_insn
))
1667 && (! replace_src_with_reg_ok_p (orig_insn
, best_reg
)
1668 || ! replace_dest_with_reg_ok_p (orig_insn
, best_reg
)))
1672 /* Make sure that EXPR has the right destination
1674 if (expr_dest_regno (expr
) != REGNO (best_reg
))
1675 replace_dest_with_reg_in_expr (expr
, best_reg
);
1677 EXPR_TARGET_AVAILABLE (expr
) = 1;
1682 /* Select and assign best register to EXPR searching from BNDS.
1683 Set *IS_ORIG_REG_P to TRUE if original register was selected.
1684 Return FALSE if no register can be chosen, which could happen when:
1685 * EXPR_SEPARABLE_P is true but we were unable to find suitable register;
1686 * EXPR_SEPARABLE_P is false but the insn sets/clobbers one of the registers
1687 that are used on the moving path. */
1689 find_best_reg_for_expr (expr_t expr
, blist_t bnds
, bool *is_orig_reg_p
)
1691 static struct reg_rename reg_rename_data
;
1694 def_list_t original_insns
= NULL
;
1697 *is_orig_reg_p
= false;
1699 /* Don't bother to do anything if this insn doesn't set any registers. */
1700 if (bitmap_empty_p (VINSN_REG_SETS (EXPR_VINSN (expr
)))
1701 && bitmap_empty_p (VINSN_REG_CLOBBERS (EXPR_VINSN (expr
))))
1704 used_regs
= get_clear_regset_from_pool ();
1705 CLEAR_HARD_REG_SET (reg_rename_data
.unavailable_hard_regs
);
1707 collect_unavailable_regs_from_bnds (expr
, bnds
, used_regs
, ®_rename_data
,
1710 #ifdef ENABLE_CHECKING
1711 /* If after reload, make sure we're working with hard regs here. */
1712 if (reload_completed
)
1714 reg_set_iterator rsi
;
1717 EXECUTE_IF_SET_IN_REG_SET (used_regs
, FIRST_PSEUDO_REGISTER
, i
, rsi
)
1722 if (EXPR_SEPARABLE_P (expr
))
1724 rtx best_reg
= NULL_RTX
;
1725 /* Check that we have computed availability of a target register
1727 verify_target_availability (expr
, used_regs
, ®_rename_data
);
1729 /* Turn everything in hard regs after reload. */
1730 if (reload_completed
)
1732 HARD_REG_SET hard_regs_used
;
1733 REG_SET_TO_HARD_REG_SET (hard_regs_used
, used_regs
);
1735 /* Join hard registers unavailable due to register class
1736 restrictions and live range intersection. */
1737 IOR_HARD_REG_SET (hard_regs_used
,
1738 reg_rename_data
.unavailable_hard_regs
);
1740 best_reg
= choose_best_reg (hard_regs_used
, ®_rename_data
,
1741 original_insns
, is_orig_reg_p
);
1744 best_reg
= choose_best_pseudo_reg (used_regs
, ®_rename_data
,
1745 original_insns
, is_orig_reg_p
);
1749 else if (*is_orig_reg_p
)
1751 /* In case of unification BEST_REG may be different from EXPR's LHS
1752 when EXPR's LHS is unavailable, and there is another LHS among
1754 reg_ok
= try_replace_dest_reg (original_insns
, best_reg
, expr
);
1758 /* Forbid renaming of low-cost insns. */
1759 if (sel_vinsn_cost (EXPR_VINSN (expr
)) < 2)
1762 reg_ok
= try_replace_dest_reg (original_insns
, best_reg
, expr
);
1767 /* If !EXPR_SCHEDULE_AS_RHS (EXPR), just make sure INSN doesn't set
1768 any of the HARD_REGS_USED set. */
1769 if (vinsn_writes_one_of_regs_p (EXPR_VINSN (expr
), used_regs
,
1770 reg_rename_data
.unavailable_hard_regs
))
1773 gcc_assert (EXPR_TARGET_AVAILABLE (expr
) <= 0);
1778 gcc_assert (EXPR_TARGET_AVAILABLE (expr
) != 0);
1782 ilist_clear (&original_insns
);
1783 return_regset_to_pool (used_regs
);
1789 /* Return true if dependence described by DS can be overcomed. */
1791 can_speculate_dep_p (ds_t ds
)
1793 if (spec_info
== NULL
)
1796 /* Leave only speculative data. */
1803 /* FIXME: make sched-deps.c produce only those non-hard dependencies,
1804 that we can overcome. */
1805 ds_t spec_mask
= spec_info
->mask
;
1807 if ((ds
& spec_mask
) != ds
)
1811 if (ds_weak (ds
) < spec_info
->data_weakness_cutoff
)
1817 /* Get a speculation check instruction.
1818 C_EXPR is a speculative expression,
1819 CHECK_DS describes speculations that should be checked,
1820 ORIG_INSN is the original non-speculative insn in the stream. */
1822 create_speculation_check (expr_t c_expr
, ds_t check_ds
, insn_t orig_insn
)
1827 basic_block recovery_block
;
1830 /* Create a recovery block if target is going to emit branchy check, or if
1831 ORIG_INSN was speculative already. */
1832 if (targetm
.sched
.needs_block_p (check_ds
)
1833 || EXPR_SPEC_DONE_DS (INSN_EXPR (orig_insn
)) != 0)
1835 recovery_block
= sel_create_recovery_block (orig_insn
);
1836 label
= BB_HEAD (recovery_block
);
1840 recovery_block
= NULL
;
1844 /* Get pattern of the check. */
1845 check_pattern
= targetm
.sched
.gen_spec_check (EXPR_INSN_RTX (c_expr
), label
,
1848 gcc_assert (check_pattern
!= NULL
);
1851 insn_rtx
= create_insn_rtx_from_pattern (check_pattern
, label
);
1853 insn
= sel_gen_insn_from_rtx_after (insn_rtx
, INSN_EXPR (orig_insn
),
1854 INSN_SEQNO (orig_insn
), orig_insn
);
1856 /* Make check to be non-speculative. */
1857 EXPR_SPEC_DONE_DS (INSN_EXPR (insn
)) = 0;
1858 INSN_SPEC_CHECKED_DS (insn
) = check_ds
;
1860 /* Decrease priority of check by difference of load/check instruction
1862 EXPR_PRIORITY (INSN_EXPR (insn
)) -= (sel_vinsn_cost (INSN_VINSN (orig_insn
))
1863 - sel_vinsn_cost (INSN_VINSN (insn
)));
1865 /* Emit copy of original insn (though with replaced target register,
1866 if needed) to the recovery block. */
1867 if (recovery_block
!= NULL
)
1871 twin_rtx
= copy_rtx (PATTERN (EXPR_INSN_RTX (c_expr
)));
1872 twin_rtx
= create_insn_rtx_from_pattern (twin_rtx
, NULL_RTX
);
1873 sel_gen_recovery_insn_from_rtx_after (twin_rtx
,
1874 INSN_EXPR (orig_insn
),
1876 bb_note (recovery_block
));
1879 /* If we've generated a data speculation check, make sure
1880 that all the bookkeeping instruction we'll create during
1881 this move_op () will allocate an ALAT entry so that the
1883 In case of control speculation we must convert C_EXPR to control
1884 speculative mode, because failing to do so will bring us an exception
1885 thrown by the non-control-speculative load. */
1886 check_ds
= ds_get_max_dep_weak (check_ds
);
1887 speculate_expr (c_expr
, check_ds
);
1892 /* True when INSN is a "regN = regN" copy. */
1894 identical_copy_p (rtx insn
)
1898 pat
= PATTERN (insn
);
1900 if (GET_CODE (pat
) != SET
)
1903 lhs
= SET_DEST (pat
);
1907 rhs
= SET_SRC (pat
);
1911 return REGNO (lhs
) == REGNO (rhs
);
1914 /* Undo all transformations on *AV_PTR that were done when
1915 moving through INSN. */
1917 undo_transformations (av_set_t
*av_ptr
, rtx insn
)
1919 av_set_iterator av_iter
;
1921 av_set_t new_set
= NULL
;
1923 /* First, kill any EXPR that uses registers set by an insn. This is
1924 required for correctness. */
1925 FOR_EACH_EXPR_1 (expr
, av_iter
, av_ptr
)
1926 if (!sched_insns_conditions_mutex_p (insn
, EXPR_INSN_RTX (expr
))
1927 && bitmap_intersect_p (INSN_REG_SETS (insn
),
1928 VINSN_REG_USES (EXPR_VINSN (expr
)))
1929 /* When an insn looks like 'r1 = r1', we could substitute through
1930 it, but the above condition will still hold. This happened with
1931 gcc.c-torture/execute/961125-1.c. */
1932 && !identical_copy_p (insn
))
1934 if (sched_verbose
>= 6)
1935 sel_print ("Expr %d removed due to use/set conflict\n",
1936 INSN_UID (EXPR_INSN_RTX (expr
)));
1937 av_set_iter_remove (&av_iter
);
1940 /* Undo transformations looking at the history vector. */
1941 FOR_EACH_EXPR (expr
, av_iter
, *av_ptr
)
1943 int index
= find_in_history_vect (EXPR_HISTORY_OF_CHANGES (expr
),
1944 insn
, EXPR_VINSN (expr
), true);
1948 expr_history_def
*phist
;
1950 phist
= VEC_index (expr_history_def
,
1951 EXPR_HISTORY_OF_CHANGES (expr
),
1954 switch (phist
->type
)
1956 case TRANS_SPECULATION
:
1958 ds_t old_ds
, new_ds
;
1960 /* Compute the difference between old and new speculative
1961 statuses: that's what we need to check.
1962 Earlier we used to assert that the status will really
1963 change. This no longer works because only the probability
1964 bits in the status may have changed during compute_av_set,
1965 and in the case of merging different probabilities of the
1966 same speculative status along different paths we do not
1967 record this in the history vector. */
1968 old_ds
= phist
->spec_ds
;
1969 new_ds
= EXPR_SPEC_DONE_DS (expr
);
1971 old_ds
&= SPECULATIVE
;
1972 new_ds
&= SPECULATIVE
;
1975 EXPR_SPEC_TO_CHECK_DS (expr
) |= new_ds
;
1978 case TRANS_SUBSTITUTION
:
1980 expr_def _tmp_expr
, *tmp_expr
= &_tmp_expr
;
1984 new_vi
= phist
->old_expr_vinsn
;
1986 gcc_assert (VINSN_SEPARABLE_P (new_vi
)
1987 == EXPR_SEPARABLE_P (expr
));
1988 copy_expr (tmp_expr
, expr
);
1990 if (vinsn_equal_p (phist
->new_expr_vinsn
,
1991 EXPR_VINSN (tmp_expr
)))
1992 change_vinsn_in_expr (tmp_expr
, new_vi
);
1994 /* This happens when we're unsubstituting on a bookkeeping
1995 copy, which was in turn substituted. The history is wrong
1996 in this case. Do it the hard way. */
1997 add
= substitute_reg_in_expr (tmp_expr
, insn
, true);
1999 av_set_add (&new_set
, tmp_expr
);
2000 clear_expr (tmp_expr
);
2010 av_set_union_and_clear (av_ptr
, &new_set
, NULL
);
2014 /* Moveup_* helpers for code motion and computing av sets. */
2016 /* Propagates EXPR inside an insn group through THROUGH_INSN.
2017 The difference from the below function is that only substitution is
2019 static enum MOVEUP_EXPR_CODE
2020 moveup_expr_inside_insn_group (expr_t expr
, insn_t through_insn
)
2022 vinsn_t vi
= EXPR_VINSN (expr
);
2026 /* Do this only inside insn group. */
2027 gcc_assert (INSN_SCHED_CYCLE (through_insn
) > 0);
2029 full_ds
= has_dependence_p (expr
, through_insn
, &has_dep_p
);
2031 return MOVEUP_EXPR_SAME
;
2033 /* Substitution is the possible choice in this case. */
2034 if (has_dep_p
[DEPS_IN_RHS
])
2036 /* Can't substitute UNIQUE VINSNs. */
2037 gcc_assert (!VINSN_UNIQUE_P (vi
));
2039 if (can_substitute_through_p (through_insn
,
2040 has_dep_p
[DEPS_IN_RHS
])
2041 && substitute_reg_in_expr (expr
, through_insn
, false))
2043 EXPR_WAS_SUBSTITUTED (expr
) = true;
2044 return MOVEUP_EXPR_CHANGED
;
2047 /* Don't care about this, as even true dependencies may be allowed
2048 in an insn group. */
2049 return MOVEUP_EXPR_SAME
;
2052 /* This can catch output dependencies in COND_EXECs. */
2053 if (has_dep_p
[DEPS_IN_INSN
])
2054 return MOVEUP_EXPR_NULL
;
2056 /* This is either an output or an anti dependence, which usually have
2057 a zero latency. Allow this here, if we'd be wrong, tick_check_p
2059 gcc_assert (has_dep_p
[DEPS_IN_LHS
]);
2060 return MOVEUP_EXPR_AS_RHS
;
2063 /* True when a trapping EXPR cannot be moved through THROUGH_INSN. */
2064 #define CANT_MOVE_TRAPPING(expr, through_insn) \
2065 (VINSN_MAY_TRAP_P (EXPR_VINSN (expr)) \
2066 && !sel_insn_has_single_succ_p ((through_insn), SUCCS_ALL) \
2067 && !sel_insn_is_speculation_check (through_insn))
2069 /* True when a conflict on a target register was found during moveup_expr. */
2070 static bool was_target_conflict
= false;
2072 /* Return true when moving a debug INSN across THROUGH_INSN will
2073 create a bookkeeping block. We don't want to create such blocks,
2074 for they would cause codegen differences between compilations with
2075 and without debug info. */
2078 moving_insn_creates_bookkeeping_block_p (insn_t insn
,
2079 insn_t through_insn
)
2081 basic_block bbi
, bbt
;
2083 edge_iterator ei1
, ei2
;
2085 if (!bookkeeping_can_be_created_if_moved_through_p (through_insn
))
2087 if (sched_verbose
>= 9)
2088 sel_print ("no bookkeeping required: ");
2092 bbi
= BLOCK_FOR_INSN (insn
);
2094 if (EDGE_COUNT (bbi
->preds
) == 1)
2096 if (sched_verbose
>= 9)
2097 sel_print ("only one pred edge: ");
2101 bbt
= BLOCK_FOR_INSN (through_insn
);
2103 FOR_EACH_EDGE (e1
, ei1
, bbt
->succs
)
2105 FOR_EACH_EDGE (e2
, ei2
, bbi
->preds
)
2107 if (find_block_for_bookkeeping (e1
, e2
, TRUE
))
2109 if (sched_verbose
>= 9)
2110 sel_print ("found existing block: ");
2116 if (sched_verbose
>= 9)
2117 sel_print ("would create bookkeeping block: ");
2122 /* Modifies EXPR so it can be moved through the THROUGH_INSN,
2123 performing necessary transformations. Record the type of transformation
2124 made in PTRANS_TYPE, when it is not NULL. When INSIDE_INSN_GROUP,
2125 permit all dependencies except true ones, and try to remove those
2126 too via forward substitution. All cases when a non-eliminable
2127 non-zero cost dependency exists inside an insn group will be fixed
2128 in tick_check_p instead. */
2129 static enum MOVEUP_EXPR_CODE
2130 moveup_expr (expr_t expr
, insn_t through_insn
, bool inside_insn_group
,
2131 enum local_trans_type
*ptrans_type
)
2133 vinsn_t vi
= EXPR_VINSN (expr
);
2134 insn_t insn
= VINSN_INSN_RTX (vi
);
2135 bool was_changed
= false;
2136 bool as_rhs
= false;
2140 /* When inside_insn_group, delegate to the helper. */
2141 if (inside_insn_group
)
2142 return moveup_expr_inside_insn_group (expr
, through_insn
);
2144 /* Deal with unique insns and control dependencies. */
2145 if (VINSN_UNIQUE_P (vi
))
2147 /* We can move jumps without side-effects or jumps that are
2148 mutually exclusive with instruction THROUGH_INSN (all in cases
2149 dependencies allow to do so and jump is not speculative). */
2150 if (control_flow_insn_p (insn
))
2152 basic_block fallthru_bb
;
2154 /* Do not move checks and do not move jumps through other
2156 if (control_flow_insn_p (through_insn
)
2157 || sel_insn_is_speculation_check (insn
))
2158 return MOVEUP_EXPR_NULL
;
2160 /* Don't move jumps through CFG joins. */
2161 if (bookkeeping_can_be_created_if_moved_through_p (through_insn
))
2162 return MOVEUP_EXPR_NULL
;
2164 /* The jump should have a clear fallthru block, and
2165 this block should be in the current region. */
2166 if ((fallthru_bb
= fallthru_bb_of_jump (insn
)) == NULL
2167 || ! in_current_region_p (fallthru_bb
))
2168 return MOVEUP_EXPR_NULL
;
2170 /* And it should be mutually exclusive with through_insn, or
2171 be an unconditional jump. */
2172 if (! any_uncondjump_p (insn
)
2173 && ! sched_insns_conditions_mutex_p (insn
, through_insn
)
2174 && ! DEBUG_INSN_P (through_insn
))
2175 return MOVEUP_EXPR_NULL
;
2178 /* Don't move what we can't move. */
2179 if (EXPR_CANT_MOVE (expr
)
2180 && BLOCK_FOR_INSN (through_insn
) != BLOCK_FOR_INSN (insn
))
2181 return MOVEUP_EXPR_NULL
;
2183 /* Don't move SCHED_GROUP instruction through anything.
2184 If we don't force this, then it will be possible to start
2185 scheduling a sched_group before all its dependencies are
2187 ??? Haifa deals with this issue by delaying the SCHED_GROUP
2188 as late as possible through rank_for_schedule. */
2189 if (SCHED_GROUP_P (insn
))
2190 return MOVEUP_EXPR_NULL
;
2193 gcc_assert (!control_flow_insn_p (insn
));
2195 /* Don't move debug insns if this would require bookkeeping. */
2196 if (DEBUG_INSN_P (insn
)
2197 && BLOCK_FOR_INSN (through_insn
) != BLOCK_FOR_INSN (insn
)
2198 && moving_insn_creates_bookkeeping_block_p (insn
, through_insn
))
2199 return MOVEUP_EXPR_NULL
;
2201 /* Deal with data dependencies. */
2202 was_target_conflict
= false;
2203 full_ds
= has_dependence_p (expr
, through_insn
, &has_dep_p
);
2206 if (!CANT_MOVE_TRAPPING (expr
, through_insn
))
2207 return MOVEUP_EXPR_SAME
;
2211 /* We can move UNIQUE insn up only as a whole and unchanged,
2212 so it shouldn't have any dependencies. */
2213 if (VINSN_UNIQUE_P (vi
))
2214 return MOVEUP_EXPR_NULL
;
2217 if (full_ds
!= 0 && can_speculate_dep_p (full_ds
))
2221 res
= speculate_expr (expr
, full_ds
);
2224 /* Speculation was successful. */
2226 was_changed
= (res
> 0);
2228 was_target_conflict
= true;
2230 *ptrans_type
= TRANS_SPECULATION
;
2231 sel_clear_has_dependence ();
2235 if (has_dep_p
[DEPS_IN_INSN
])
2236 /* We have some dependency that cannot be discarded. */
2237 return MOVEUP_EXPR_NULL
;
2239 if (has_dep_p
[DEPS_IN_LHS
])
2241 /* Only separable insns can be moved up with the new register.
2242 Anyways, we should mark that the original register is
2244 if (!enable_schedule_as_rhs_p
|| !EXPR_SEPARABLE_P (expr
))
2245 return MOVEUP_EXPR_NULL
;
2247 EXPR_TARGET_AVAILABLE (expr
) = false;
2248 was_target_conflict
= true;
2252 /* At this point we have either separable insns, that will be lifted
2253 up only as RHSes, or non-separable insns with no dependency in lhs.
2254 If dependency is in RHS, then try to perform substitution and move up
2261 In Ex.1 y*2 can be substituted for x*2 and the whole operation can be
2262 moved above y=x assignment as z=x*2.
2264 In Ex.2 y*2 also can be substituted for x*2, but only the right hand
2265 side can be moved because of the output dependency. The operation was
2266 cropped to its rhs above. */
2267 if (has_dep_p
[DEPS_IN_RHS
])
2269 ds_t
*rhs_dsp
= &has_dep_p
[DEPS_IN_RHS
];
2271 /* Can't substitute UNIQUE VINSNs. */
2272 gcc_assert (!VINSN_UNIQUE_P (vi
));
2274 if (can_speculate_dep_p (*rhs_dsp
))
2278 res
= speculate_expr (expr
, *rhs_dsp
);
2281 /* Speculation was successful. */
2283 was_changed
= (res
> 0);
2285 was_target_conflict
= true;
2287 *ptrans_type
= TRANS_SPECULATION
;
2290 return MOVEUP_EXPR_NULL
;
2292 else if (can_substitute_through_p (through_insn
,
2294 && substitute_reg_in_expr (expr
, through_insn
, false))
2296 /* ??? We cannot perform substitution AND speculation on the same
2298 gcc_assert (!was_changed
);
2301 *ptrans_type
= TRANS_SUBSTITUTION
;
2302 EXPR_WAS_SUBSTITUTED (expr
) = true;
2305 return MOVEUP_EXPR_NULL
;
2308 /* Don't move trapping insns through jumps.
2309 This check should be at the end to give a chance to control speculation
2310 to perform its duties. */
2311 if (CANT_MOVE_TRAPPING (expr
, through_insn
))
2312 return MOVEUP_EXPR_NULL
;
2315 ? MOVEUP_EXPR_CHANGED
2317 ? MOVEUP_EXPR_AS_RHS
2318 : MOVEUP_EXPR_SAME
));
2321 /* Try to look at bitmap caches for EXPR and INSN pair, return true
2322 if successful. When INSIDE_INSN_GROUP, also try ignore dependencies
2323 that can exist within a parallel group. Write to RES the resulting
2324 code for moveup_expr. */
2326 try_bitmap_cache (expr_t expr
, insn_t insn
,
2327 bool inside_insn_group
,
2328 enum MOVEUP_EXPR_CODE
*res
)
2330 int expr_uid
= INSN_UID (EXPR_INSN_RTX (expr
));
2332 /* First check whether we've analyzed this situation already. */
2333 if (bitmap_bit_p (INSN_ANALYZED_DEPS (insn
), expr_uid
))
2335 if (bitmap_bit_p (INSN_FOUND_DEPS (insn
), expr_uid
))
2337 if (sched_verbose
>= 6)
2338 sel_print ("removed (cached)\n");
2339 *res
= MOVEUP_EXPR_NULL
;
2344 if (sched_verbose
>= 6)
2345 sel_print ("unchanged (cached)\n");
2346 *res
= MOVEUP_EXPR_SAME
;
2350 else if (bitmap_bit_p (INSN_FOUND_DEPS (insn
), expr_uid
))
2352 if (inside_insn_group
)
2354 if (sched_verbose
>= 6)
2355 sel_print ("unchanged (as RHS, cached, inside insn group)\n");
2356 *res
= MOVEUP_EXPR_SAME
;
2361 EXPR_TARGET_AVAILABLE (expr
) = false;
2363 /* This is the only case when propagation result can change over time,
2364 as we can dynamically switch off scheduling as RHS. In this case,
2365 just check the flag to reach the correct decision. */
2366 if (enable_schedule_as_rhs_p
)
2368 if (sched_verbose
>= 6)
2369 sel_print ("unchanged (as RHS, cached)\n");
2370 *res
= MOVEUP_EXPR_AS_RHS
;
2375 if (sched_verbose
>= 6)
2376 sel_print ("removed (cached as RHS, but renaming"
2377 " is now disabled)\n");
2378 *res
= MOVEUP_EXPR_NULL
;
2386 /* Try to look at bitmap caches for EXPR and INSN pair, return true
2387 if successful. Write to RES the resulting code for moveup_expr. */
2389 try_transformation_cache (expr_t expr
, insn_t insn
,
2390 enum MOVEUP_EXPR_CODE
*res
)
2392 struct transformed_insns
*pti
2393 = (struct transformed_insns
*)
2394 htab_find_with_hash (INSN_TRANSFORMED_INSNS (insn
),
2396 VINSN_HASH_RTX (EXPR_VINSN (expr
)));
2399 /* This EXPR was already moved through this insn and was
2400 changed as a result. Fetch the proper data from
2402 insert_in_history_vect (&EXPR_HISTORY_OF_CHANGES (expr
),
2403 INSN_UID (insn
), pti
->type
,
2404 pti
->vinsn_old
, pti
->vinsn_new
,
2405 EXPR_SPEC_DONE_DS (expr
));
2407 if (INSN_IN_STREAM_P (VINSN_INSN_RTX (pti
->vinsn_new
)))
2408 pti
->vinsn_new
= vinsn_copy (pti
->vinsn_new
, true);
2409 change_vinsn_in_expr (expr
, pti
->vinsn_new
);
2410 if (pti
->was_target_conflict
)
2411 EXPR_TARGET_AVAILABLE (expr
) = false;
2412 if (pti
->type
== TRANS_SPECULATION
)
2414 EXPR_SPEC_DONE_DS (expr
) = pti
->ds
;
2415 EXPR_NEEDS_SPEC_CHECK_P (expr
) |= pti
->needs_check
;
2418 if (sched_verbose
>= 6)
2420 sel_print ("changed (cached): ");
2425 *res
= MOVEUP_EXPR_CHANGED
;
2432 /* Update bitmap caches on INSN with result RES of propagating EXPR. */
2434 update_bitmap_cache (expr_t expr
, insn_t insn
, bool inside_insn_group
,
2435 enum MOVEUP_EXPR_CODE res
)
2437 int expr_uid
= INSN_UID (EXPR_INSN_RTX (expr
));
2439 /* Do not cache result of propagating jumps through an insn group,
2440 as it is always true, which is not useful outside the group. */
2441 if (inside_insn_group
)
2444 if (res
== MOVEUP_EXPR_NULL
)
2446 bitmap_set_bit (INSN_ANALYZED_DEPS (insn
), expr_uid
);
2447 bitmap_set_bit (INSN_FOUND_DEPS (insn
), expr_uid
);
2449 else if (res
== MOVEUP_EXPR_SAME
)
2451 bitmap_set_bit (INSN_ANALYZED_DEPS (insn
), expr_uid
);
2452 bitmap_clear_bit (INSN_FOUND_DEPS (insn
), expr_uid
);
2454 else if (res
== MOVEUP_EXPR_AS_RHS
)
2456 bitmap_clear_bit (INSN_ANALYZED_DEPS (insn
), expr_uid
);
2457 bitmap_set_bit (INSN_FOUND_DEPS (insn
), expr_uid
);
2463 /* Update hashtable on INSN with changed EXPR, old EXPR_OLD_VINSN
2464 and transformation type TRANS_TYPE. */
2466 update_transformation_cache (expr_t expr
, insn_t insn
,
2467 bool inside_insn_group
,
2468 enum local_trans_type trans_type
,
2469 vinsn_t expr_old_vinsn
)
2471 struct transformed_insns
*pti
;
2473 if (inside_insn_group
)
2476 pti
= XNEW (struct transformed_insns
);
2477 pti
->vinsn_old
= expr_old_vinsn
;
2478 pti
->vinsn_new
= EXPR_VINSN (expr
);
2479 pti
->type
= trans_type
;
2480 pti
->was_target_conflict
= was_target_conflict
;
2481 pti
->ds
= EXPR_SPEC_DONE_DS (expr
);
2482 pti
->needs_check
= EXPR_NEEDS_SPEC_CHECK_P (expr
);
2483 vinsn_attach (pti
->vinsn_old
);
2484 vinsn_attach (pti
->vinsn_new
);
2485 *((struct transformed_insns
**)
2486 htab_find_slot_with_hash (INSN_TRANSFORMED_INSNS (insn
),
2487 pti
, VINSN_HASH_RTX (expr_old_vinsn
),
2491 /* Same as moveup_expr, but first looks up the result of
2492 transformation in caches. */
2493 static enum MOVEUP_EXPR_CODE
2494 moveup_expr_cached (expr_t expr
, insn_t insn
, bool inside_insn_group
)
2496 enum MOVEUP_EXPR_CODE res
;
2497 bool got_answer
= false;
2499 if (sched_verbose
>= 6)
2501 sel_print ("Moving ");
2503 sel_print (" through %d: ", INSN_UID (insn
));
2506 if (DEBUG_INSN_P (EXPR_INSN_RTX (expr
))
2507 && (sel_bb_head (BLOCK_FOR_INSN (EXPR_INSN_RTX (expr
)))
2508 == EXPR_INSN_RTX (expr
)))
2509 /* Don't use cached information for debug insns that are heads of
2511 else if (try_bitmap_cache (expr
, insn
, inside_insn_group
, &res
))
2512 /* When inside insn group, we do not want remove stores conflicting
2513 with previosly issued loads. */
2514 got_answer
= ! inside_insn_group
|| res
!= MOVEUP_EXPR_NULL
;
2515 else if (try_transformation_cache (expr
, insn
, &res
))
2520 /* Invoke moveup_expr and record the results. */
2521 vinsn_t expr_old_vinsn
= EXPR_VINSN (expr
);
2522 ds_t expr_old_spec_ds
= EXPR_SPEC_DONE_DS (expr
);
2523 int expr_uid
= INSN_UID (VINSN_INSN_RTX (expr_old_vinsn
));
2524 bool unique_p
= VINSN_UNIQUE_P (expr_old_vinsn
);
2525 enum local_trans_type trans_type
= TRANS_SUBSTITUTION
;
2527 /* ??? Invent something better than this. We can't allow old_vinsn
2528 to go, we need it for the history vector. */
2529 vinsn_attach (expr_old_vinsn
);
2531 res
= moveup_expr (expr
, insn
, inside_insn_group
,
2535 case MOVEUP_EXPR_NULL
:
2536 update_bitmap_cache (expr
, insn
, inside_insn_group
, res
);
2537 if (sched_verbose
>= 6)
2538 sel_print ("removed\n");
2541 case MOVEUP_EXPR_SAME
:
2542 update_bitmap_cache (expr
, insn
, inside_insn_group
, res
);
2543 if (sched_verbose
>= 6)
2544 sel_print ("unchanged\n");
2547 case MOVEUP_EXPR_AS_RHS
:
2548 gcc_assert (!unique_p
|| inside_insn_group
);
2549 update_bitmap_cache (expr
, insn
, inside_insn_group
, res
);
2550 if (sched_verbose
>= 6)
2551 sel_print ("unchanged (as RHS)\n");
2554 case MOVEUP_EXPR_CHANGED
:
2555 gcc_assert (INSN_UID (EXPR_INSN_RTX (expr
)) != expr_uid
2556 || EXPR_SPEC_DONE_DS (expr
) != expr_old_spec_ds
);
2557 insert_in_history_vect (&EXPR_HISTORY_OF_CHANGES (expr
),
2558 INSN_UID (insn
), trans_type
,
2559 expr_old_vinsn
, EXPR_VINSN (expr
),
2561 update_transformation_cache (expr
, insn
, inside_insn_group
,
2562 trans_type
, expr_old_vinsn
);
2563 if (sched_verbose
>= 6)
2565 sel_print ("changed: ");
2574 vinsn_detach (expr_old_vinsn
);
2580 /* Moves an av set AVP up through INSN, performing necessary
2583 moveup_set_expr (av_set_t
*avp
, insn_t insn
, bool inside_insn_group
)
2588 FOR_EACH_EXPR_1 (expr
, i
, avp
)
2591 switch (moveup_expr_cached (expr
, insn
, inside_insn_group
))
2593 case MOVEUP_EXPR_SAME
:
2594 case MOVEUP_EXPR_AS_RHS
:
2597 case MOVEUP_EXPR_NULL
:
2598 av_set_iter_remove (&i
);
2601 case MOVEUP_EXPR_CHANGED
:
2602 expr
= merge_with_other_exprs (avp
, &i
, expr
);
2611 /* Moves AVP set along PATH. */
2613 moveup_set_inside_insn_group (av_set_t
*avp
, ilist_t path
)
2617 if (sched_verbose
>= 6)
2618 sel_print ("Moving expressions up in the insn group...\n");
2621 last_cycle
= INSN_SCHED_CYCLE (ILIST_INSN (path
));
2623 && INSN_SCHED_CYCLE (ILIST_INSN (path
)) == last_cycle
)
2625 moveup_set_expr (avp
, ILIST_INSN (path
), true);
2626 path
= ILIST_NEXT (path
);
2630 /* Returns true if after moving EXPR along PATH it equals to EXPR_VLIW. */
2632 equal_after_moveup_path_p (expr_t expr
, ilist_t path
, expr_t expr_vliw
)
2634 expr_def _tmp
, *tmp
= &_tmp
;
2638 copy_expr_onside (tmp
, expr
);
2639 last_cycle
= path
? INSN_SCHED_CYCLE (ILIST_INSN (path
)) : 0;
2642 && INSN_SCHED_CYCLE (ILIST_INSN (path
)) == last_cycle
)
2644 res
= (moveup_expr_cached (tmp
, ILIST_INSN (path
), true)
2645 != MOVEUP_EXPR_NULL
);
2646 path
= ILIST_NEXT (path
);
2651 vinsn_t tmp_vinsn
= EXPR_VINSN (tmp
);
2652 vinsn_t expr_vliw_vinsn
= EXPR_VINSN (expr_vliw
);
2654 if (tmp_vinsn
!= expr_vliw_vinsn
)
2655 res
= vinsn_equal_p (tmp_vinsn
, expr_vliw_vinsn
);
2663 /* Functions that compute av and lv sets. */
2665 /* Returns true if INSN is not a downward continuation of the given path P in
2666 the current stage. */
2668 is_ineligible_successor (insn_t insn
, ilist_t p
)
2672 /* Check if insn is not deleted. */
2673 if (PREV_INSN (insn
) && NEXT_INSN (PREV_INSN (insn
)) != insn
)
2675 else if (NEXT_INSN (insn
) && PREV_INSN (NEXT_INSN (insn
)) != insn
)
2678 /* If it's the first insn visited, then the successor is ok. */
2682 prev_insn
= ILIST_INSN (p
);
2684 if (/* a backward edge. */
2685 INSN_SEQNO (insn
) < INSN_SEQNO (prev_insn
)
2686 /* is already visited. */
2687 || (INSN_SEQNO (insn
) == INSN_SEQNO (prev_insn
)
2688 && (ilist_is_in_p (p
, insn
)
2689 /* We can reach another fence here and still seqno of insn
2690 would be equal to seqno of prev_insn. This is possible
2691 when prev_insn is a previously created bookkeeping copy.
2692 In that case it'd get a seqno of insn. Thus, check here
2693 whether insn is in current fence too. */
2694 || IN_CURRENT_FENCE_P (insn
)))
2695 /* Was already scheduled on this round. */
2696 || (INSN_SEQNO (insn
) > INSN_SEQNO (prev_insn
)
2697 && IN_CURRENT_FENCE_P (insn
))
2698 /* An insn from another fence could also be
2699 scheduled earlier even if this insn is not in
2700 a fence list right now. Check INSN_SCHED_CYCLE instead. */
2702 && INSN_SCHED_TIMES (insn
) > 0))
2708 /* Computes the av_set below the last bb insn INSN, doing all the 'dirty work'
2709 of handling multiple successors and properly merging its av_sets. P is
2710 the current path traversed. WS is the size of lookahead window.
2711 Return the av set computed. */
2713 compute_av_set_at_bb_end (insn_t insn
, ilist_t p
, int ws
)
2715 struct succs_info
*sinfo
;
2716 av_set_t expr_in_all_succ_branches
= NULL
;
2718 insn_t succ
, zero_succ
= NULL
;
2719 av_set_t av1
= NULL
;
2721 gcc_assert (sel_bb_end_p (insn
));
2723 /* Find different kind of successors needed for correct computing of
2724 SPEC and TARGET_AVAILABLE attributes. */
2725 sinfo
= compute_succs_info (insn
, SUCCS_NORMAL
);
2728 if (sched_verbose
>= 6)
2730 sel_print ("successors of bb end (%d): ", INSN_UID (insn
));
2731 dump_insn_vector (sinfo
->succs_ok
);
2733 if (sinfo
->succs_ok_n
!= sinfo
->all_succs_n
)
2734 sel_print ("real successors num: %d\n", sinfo
->all_succs_n
);
2737 /* Add insn to to the tail of current path. */
2738 ilist_add (&p
, insn
);
2740 for (is
= 0; VEC_iterate (rtx
, sinfo
->succs_ok
, is
, succ
); is
++)
2744 /* We will edit SUCC_SET and EXPR_SPEC field of its elements. */
2745 succ_set
= compute_av_set_inside_bb (succ
, p
, ws
, true);
2747 av_set_split_usefulness (succ_set
,
2748 VEC_index (int, sinfo
->probs_ok
, is
),
2751 if (sinfo
->all_succs_n
> 1)
2753 /* Find EXPR'es that came from *all* successors and save them
2754 into expr_in_all_succ_branches. This set will be used later
2755 for calculating speculation attributes of EXPR'es. */
2758 expr_in_all_succ_branches
= av_set_copy (succ_set
);
2760 /* Remember the first successor for later. */
2768 FOR_EACH_EXPR_1 (expr
, i
, &expr_in_all_succ_branches
)
2769 if (!av_set_is_in_p (succ_set
, EXPR_VINSN (expr
)))
2770 av_set_iter_remove (&i
);
2774 /* Union the av_sets. Check liveness restrictions on target registers
2775 in special case of two successors. */
2776 if (sinfo
->succs_ok_n
== 2 && is
== 1)
2778 basic_block bb0
= BLOCK_FOR_INSN (zero_succ
);
2779 basic_block bb1
= BLOCK_FOR_INSN (succ
);
2781 gcc_assert (BB_LV_SET_VALID_P (bb0
) && BB_LV_SET_VALID_P (bb1
));
2782 av_set_union_and_live (&av1
, &succ_set
,
2788 av_set_union_and_clear (&av1
, &succ_set
, insn
);
2791 /* Check liveness restrictions via hard way when there are more than
2793 if (sinfo
->succs_ok_n
> 2)
2794 for (is
= 0; VEC_iterate (rtx
, sinfo
->succs_ok
, is
, succ
); is
++)
2796 basic_block succ_bb
= BLOCK_FOR_INSN (succ
);
2798 gcc_assert (BB_LV_SET_VALID_P (succ_bb
));
2799 mark_unavailable_targets (av1
, BB_AV_SET (succ_bb
),
2800 BB_LV_SET (succ_bb
));
2803 /* Finally, check liveness restrictions on paths leaving the region. */
2804 if (sinfo
->all_succs_n
> sinfo
->succs_ok_n
)
2805 for (is
= 0; VEC_iterate (rtx
, sinfo
->succs_other
, is
, succ
); is
++)
2806 mark_unavailable_targets
2807 (av1
, NULL
, BB_LV_SET (BLOCK_FOR_INSN (succ
)));
2809 if (sinfo
->all_succs_n
> 1)
2814 /* Increase the spec attribute of all EXPR'es that didn't come
2815 from all successors. */
2816 FOR_EACH_EXPR (expr
, i
, av1
)
2817 if (!av_set_is_in_p (expr_in_all_succ_branches
, EXPR_VINSN (expr
)))
2820 av_set_clear (&expr_in_all_succ_branches
);
2822 /* Do not move conditional branches through other
2823 conditional branches. So, remove all conditional
2824 branches from av_set if current operator is a conditional
2826 av_set_substract_cond_branches (&av1
);
2830 free_succs_info (sinfo
);
2832 if (sched_verbose
>= 6)
2834 sel_print ("av_succs (%d): ", INSN_UID (insn
));
2842 /* This function computes av_set for the FIRST_INSN by dragging valid
2843 av_set through all basic block insns either from the end of basic block
2844 (computed using compute_av_set_at_bb_end) or from the insn on which
2845 MAX_WS was exceeded. It uses compute_av_set_at_bb_end to compute av_set
2846 below the basic block and handling conditional branches.
2847 FIRST_INSN - the basic block head, P - path consisting of the insns
2848 traversed on the way to the FIRST_INSN (the path is sparse, only bb heads
2849 and bb ends are added to the path), WS - current window size,
2850 NEED_COPY_P - true if we'll make a copy of av_set before returning it. */
2852 compute_av_set_inside_bb (insn_t first_insn
, ilist_t p
, int ws
,
2857 insn_t bb_end
= sel_bb_end (BLOCK_FOR_INSN (first_insn
));
2858 insn_t after_bb_end
= NEXT_INSN (bb_end
);
2861 basic_block cur_bb
= BLOCK_FOR_INSN (first_insn
);
2863 /* Return NULL if insn is not on the legitimate downward path. */
2864 if (is_ineligible_successor (first_insn
, p
))
2866 if (sched_verbose
>= 6)
2867 sel_print ("Insn %d is ineligible_successor\n", INSN_UID (first_insn
));
2872 /* If insn already has valid av(insn) computed, just return it. */
2873 if (AV_SET_VALID_P (first_insn
))
2877 if (sel_bb_head_p (first_insn
))
2878 av_set
= BB_AV_SET (BLOCK_FOR_INSN (first_insn
));
2882 if (sched_verbose
>= 6)
2884 sel_print ("Insn %d has a valid av set: ", INSN_UID (first_insn
));
2885 dump_av_set (av_set
);
2889 return need_copy_p
? av_set_copy (av_set
) : av_set
;
2892 ilist_add (&p
, first_insn
);
2894 /* As the result after this loop have completed, in LAST_INSN we'll
2895 have the insn which has valid av_set to start backward computation
2896 from: it either will be NULL because on it the window size was exceeded
2897 or other valid av_set as returned by compute_av_set for the last insn
2898 of the basic block. */
2899 for (last_insn
= first_insn
; last_insn
!= after_bb_end
;
2900 last_insn
= NEXT_INSN (last_insn
))
2902 /* We may encounter valid av_set not only on bb_head, but also on
2903 those insns on which previously MAX_WS was exceeded. */
2904 if (AV_SET_VALID_P (last_insn
))
2906 if (sched_verbose
>= 6)
2907 sel_print ("Insn %d has a valid empty av set\n", INSN_UID (last_insn
));
2911 /* The special case: the last insn of the BB may be an
2912 ineligible_successor due to its SEQ_NO that was set on
2913 it as a bookkeeping. */
2914 if (last_insn
!= first_insn
2915 && is_ineligible_successor (last_insn
, p
))
2917 if (sched_verbose
>= 6)
2918 sel_print ("Insn %d is ineligible_successor\n", INSN_UID (last_insn
));
2922 if (DEBUG_INSN_P (last_insn
))
2925 if (end_ws
> max_ws
)
2927 /* We can reach max lookahead size at bb_header, so clean av_set
2929 INSN_WS_LEVEL (last_insn
) = global_level
;
2931 if (sched_verbose
>= 6)
2932 sel_print ("Insn %d is beyond the software lookahead window size\n",
2933 INSN_UID (last_insn
));
2940 /* Get the valid av_set into AV above the LAST_INSN to start backward
2941 computation from. It either will be empty av_set or av_set computed from
2942 the successors on the last insn of the current bb. */
2943 if (last_insn
!= after_bb_end
)
2947 /* This is needed only to obtain av_sets that are identical to
2948 those computed by the old compute_av_set version. */
2949 if (last_insn
== first_insn
&& !INSN_NOP_P (last_insn
))
2950 av_set_add (&av
, INSN_EXPR (last_insn
));
2953 /* END_WS is always already increased by 1 if LAST_INSN == AFTER_BB_END. */
2954 av
= compute_av_set_at_bb_end (bb_end
, p
, end_ws
);
2956 /* Compute av_set in AV starting from below the LAST_INSN up to
2957 location above the FIRST_INSN. */
2958 for (cur_insn
= PREV_INSN (last_insn
); cur_insn
!= PREV_INSN (first_insn
);
2959 cur_insn
= PREV_INSN (cur_insn
))
2960 if (!INSN_NOP_P (cur_insn
))
2964 moveup_set_expr (&av
, cur_insn
, false);
2966 /* If the expression for CUR_INSN is already in the set,
2967 replace it by the new one. */
2968 expr
= av_set_lookup (av
, INSN_VINSN (cur_insn
));
2972 copy_expr (expr
, INSN_EXPR (cur_insn
));
2975 av_set_add (&av
, INSN_EXPR (cur_insn
));
2978 /* Clear stale bb_av_set. */
2979 if (sel_bb_head_p (first_insn
))
2981 av_set_clear (&BB_AV_SET (cur_bb
));
2982 BB_AV_SET (cur_bb
) = need_copy_p
? av_set_copy (av
) : av
;
2983 BB_AV_LEVEL (cur_bb
) = global_level
;
2986 if (sched_verbose
>= 6)
2988 sel_print ("Computed av set for insn %d: ", INSN_UID (first_insn
));
2997 /* Compute av set before INSN.
2998 INSN - the current operation (actual rtx INSN)
2999 P - the current path, which is list of insns visited so far
3000 WS - software lookahead window size.
3001 UNIQUE_P - TRUE, if returned av_set will be changed, hence
3002 if we want to save computed av_set in s_i_d, we should make a copy of it.
3004 In the resulting set we will have only expressions that don't have delay
3005 stalls and nonsubstitutable dependences. */
3007 compute_av_set (insn_t insn
, ilist_t p
, int ws
, bool unique_p
)
3009 return compute_av_set_inside_bb (insn
, p
, ws
, unique_p
);
3012 /* Propagate a liveness set LV through INSN. */
3014 propagate_lv_set (regset lv
, insn_t insn
)
3016 gcc_assert (INSN_P (insn
));
3018 if (INSN_NOP_P (insn
))
3021 df_simulate_one_insn_backwards (BLOCK_FOR_INSN (insn
), insn
, lv
);
3024 /* Return livness set at the end of BB. */
3026 compute_live_after_bb (basic_block bb
)
3030 regset lv
= get_clear_regset_from_pool ();
3032 gcc_assert (!ignore_first
);
3034 FOR_EACH_EDGE (e
, ei
, bb
->succs
)
3035 if (sel_bb_empty_p (e
->dest
))
3037 if (! BB_LV_SET_VALID_P (e
->dest
))
3040 gcc_assert (BB_LV_SET (e
->dest
) == NULL
);
3041 BB_LV_SET (e
->dest
) = compute_live_after_bb (e
->dest
);
3042 BB_LV_SET_VALID_P (e
->dest
) = true;
3044 IOR_REG_SET (lv
, BB_LV_SET (e
->dest
));
3047 IOR_REG_SET (lv
, compute_live (sel_bb_head (e
->dest
)));
3052 /* Compute the set of all live registers at the point before INSN and save
3053 it at INSN if INSN is bb header. */
3055 compute_live (insn_t insn
)
3057 basic_block bb
= BLOCK_FOR_INSN (insn
);
3061 /* Return the valid set if we're already on it. */
3066 if (sel_bb_head_p (insn
) && BB_LV_SET_VALID_P (bb
))
3067 src
= BB_LV_SET (bb
);
3070 gcc_assert (in_current_region_p (bb
));
3071 if (INSN_LIVE_VALID_P (insn
))
3072 src
= INSN_LIVE (insn
);
3077 lv
= get_regset_from_pool ();
3078 COPY_REG_SET (lv
, src
);
3080 if (sel_bb_head_p (insn
) && ! BB_LV_SET_VALID_P (bb
))
3082 COPY_REG_SET (BB_LV_SET (bb
), lv
);
3083 BB_LV_SET_VALID_P (bb
) = true;
3086 return_regset_to_pool (lv
);
3091 /* We've skipped the wrong lv_set. Don't skip the right one. */
3092 ignore_first
= false;
3093 gcc_assert (in_current_region_p (bb
));
3095 /* Find a valid LV set in this block or below, if needed.
3096 Start searching from the next insn: either ignore_first is true, or
3097 INSN doesn't have a correct live set. */
3098 temp
= NEXT_INSN (insn
);
3099 final
= NEXT_INSN (BB_END (bb
));
3100 while (temp
!= final
&& ! INSN_LIVE_VALID_P (temp
))
3101 temp
= NEXT_INSN (temp
);
3104 lv
= compute_live_after_bb (bb
);
3105 temp
= PREV_INSN (temp
);
3109 lv
= get_regset_from_pool ();
3110 COPY_REG_SET (lv
, INSN_LIVE (temp
));
3113 /* Put correct lv sets on the insns which have bad sets. */
3114 final
= PREV_INSN (insn
);
3115 while (temp
!= final
)
3117 propagate_lv_set (lv
, temp
);
3118 COPY_REG_SET (INSN_LIVE (temp
), lv
);
3119 INSN_LIVE_VALID_P (temp
) = true;
3120 temp
= PREV_INSN (temp
);
3123 /* Also put it in a BB. */
3124 if (sel_bb_head_p (insn
))
3126 basic_block bb
= BLOCK_FOR_INSN (insn
);
3128 COPY_REG_SET (BB_LV_SET (bb
), lv
);
3129 BB_LV_SET_VALID_P (bb
) = true;
3132 /* We return LV to the pool, but will not clear it there. Thus we can
3133 legimatelly use LV till the next use of regset_pool_get (). */
3134 return_regset_to_pool (lv
);
3138 /* Update liveness sets for INSN. */
3140 update_liveness_on_insn (rtx insn
)
3142 ignore_first
= true;
3143 compute_live (insn
);
3146 /* Compute liveness below INSN and write it into REGS. */
3148 compute_live_below_insn (rtx insn
, regset regs
)
3153 FOR_EACH_SUCC_1 (succ
, si
, insn
, SUCCS_ALL
)
3154 IOR_REG_SET (regs
, compute_live (succ
));
3157 /* Update the data gathered in av and lv sets starting from INSN. */
3159 update_data_sets (rtx insn
)
3161 update_liveness_on_insn (insn
);
3162 if (sel_bb_head_p (insn
))
3164 gcc_assert (AV_LEVEL (insn
) != 0);
3165 BB_AV_LEVEL (BLOCK_FOR_INSN (insn
)) = -1;
3166 compute_av_set (insn
, NULL
, 0, 0);
3171 /* Helper for move_op () and find_used_regs ().
3172 Return speculation type for which a check should be created on the place
3173 of INSN. EXPR is one of the original ops we are searching for. */
3175 get_spec_check_type_for_insn (insn_t insn
, expr_t expr
)
3178 ds_t already_checked_ds
= EXPR_SPEC_DONE_DS (INSN_EXPR (insn
));
3180 to_check_ds
= EXPR_SPEC_TO_CHECK_DS (expr
);
3182 if (targetm
.sched
.get_insn_checked_ds
)
3183 already_checked_ds
|= targetm
.sched
.get_insn_checked_ds (insn
);
3185 if (spec_info
!= NULL
3186 && (spec_info
->flags
& SEL_SCHED_SPEC_DONT_CHECK_CONTROL
))
3187 already_checked_ds
|= BEGIN_CONTROL
;
3189 already_checked_ds
= ds_get_speculation_types (already_checked_ds
);
3191 to_check_ds
&= ~already_checked_ds
;
3196 /* Find the set of registers that are unavailable for storing expres
3197 while moving ORIG_OPS up on the path starting from INSN due to
3198 liveness (USED_REGS) or hardware restrictions (REG_RENAME_P).
3200 All the original operations found during the traversal are saved in the
3201 ORIGINAL_INSNS list.
3203 REG_RENAME_P denotes the set of hardware registers that
3204 can not be used with renaming due to the register class restrictions,
3205 mode restrictions and other (the register we'll choose should be
3206 compatible class with the original uses, shouldn't be in call_used_regs,
3207 should be HARD_REGNO_RENAME_OK etc).
3209 Returns TRUE if we've found all original insns, FALSE otherwise.
3211 This function utilizes code_motion_path_driver (formerly find_used_regs_1)
3212 to traverse the code motion paths. This helper function finds registers
3213 that are not available for storing expres while moving ORIG_OPS up on the
3214 path starting from INSN. A register considered as used on the moving path,
3215 if one of the following conditions is not satisfied:
3217 (1) a register not set or read on any path from xi to an instance of
3218 the original operation,
3219 (2) not among the live registers of the point immediately following the
3220 first original operation on a given downward path, except for the
3221 original target register of the operation,
3222 (3) not live on the other path of any conditional branch that is passed
3223 by the operation, in case original operations are not present on
3224 both paths of the conditional branch.
3226 All the original operations found during the traversal are saved in the
3227 ORIGINAL_INSNS list.
3229 REG_RENAME_P->CROSSES_CALL is true, if there is a call insn on the path
3230 from INSN to original insn. In this case CALL_USED_REG_SET will be added
3231 to unavailable hard regs at the point original operation is found. */
3234 find_used_regs (insn_t insn
, av_set_t orig_ops
, regset used_regs
,
3235 struct reg_rename
*reg_rename_p
, def_list_t
*original_insns
)
3237 def_list_iterator i
;
3240 bool needs_spec_check_p
= false;
3242 av_set_iterator expr_iter
;
3243 struct fur_static_params sparams
;
3244 struct cmpd_local_params lparams
;
3246 /* We haven't visited any blocks yet. */
3247 bitmap_clear (code_motion_visited_blocks
);
3249 /* Init parameters for code_motion_path_driver. */
3250 sparams
.crosses_call
= false;
3251 sparams
.original_insns
= original_insns
;
3252 sparams
.used_regs
= used_regs
;
3254 /* Set the appropriate hooks and data. */
3255 code_motion_path_driver_info
= &fur_hooks
;
3257 res
= code_motion_path_driver (insn
, orig_ops
, NULL
, &lparams
, &sparams
);
3259 reg_rename_p
->crosses_call
|= sparams
.crosses_call
;
3261 gcc_assert (res
== 1);
3262 gcc_assert (original_insns
&& *original_insns
);
3264 /* ??? We calculate whether an expression needs a check when computing
3265 av sets. This information is not as precise as it could be due to
3266 merging this bit in merge_expr. We can do better in find_used_regs,
3267 but we want to avoid multiple traversals of the same code motion
3269 FOR_EACH_EXPR (expr
, expr_iter
, orig_ops
)
3270 needs_spec_check_p
|= EXPR_NEEDS_SPEC_CHECK_P (expr
);
3272 /* Mark hardware regs in REG_RENAME_P that are not suitable
3273 for renaming expr in INSN due to hardware restrictions (register class,
3274 modes compatibility etc). */
3275 FOR_EACH_DEF (def
, i
, *original_insns
)
3277 vinsn_t vinsn
= INSN_VINSN (def
->orig_insn
);
3279 if (VINSN_SEPARABLE_P (vinsn
))
3280 mark_unavailable_hard_regs (def
, reg_rename_p
, used_regs
);
3282 /* Do not allow clobbering of ld.[sa] address in case some of the
3283 original operations need a check. */
3284 if (needs_spec_check_p
)
3285 IOR_REG_SET (used_regs
, VINSN_REG_USES (vinsn
));
3292 /* Functions to choose the best insn from available ones. */
3294 /* Adjusts the priority for EXPR using the backend *_adjust_priority hook. */
3296 sel_target_adjust_priority (expr_t expr
)
3298 int priority
= EXPR_PRIORITY (expr
);
3301 if (targetm
.sched
.adjust_priority
)
3302 new_priority
= targetm
.sched
.adjust_priority (EXPR_INSN_RTX (expr
), priority
);
3304 new_priority
= priority
;
3306 /* If the priority has changed, adjust EXPR_PRIORITY_ADJ accordingly. */
3307 EXPR_PRIORITY_ADJ (expr
) = new_priority
- EXPR_PRIORITY (expr
);
3309 gcc_assert (EXPR_PRIORITY_ADJ (expr
) >= 0);
3311 if (sched_verbose
>= 4)
3312 sel_print ("sel_target_adjust_priority: insn %d, %d+%d = %d.\n",
3313 INSN_UID (EXPR_INSN_RTX (expr
)), EXPR_PRIORITY (expr
),
3314 EXPR_PRIORITY_ADJ (expr
), new_priority
);
3316 return new_priority
;
3319 /* Rank two available exprs for schedule. Never return 0 here. */
3321 sel_rank_for_schedule (const void *x
, const void *y
)
3323 expr_t tmp
= *(const expr_t
*) y
;
3324 expr_t tmp2
= *(const expr_t
*) x
;
3325 insn_t tmp_insn
, tmp2_insn
;
3326 vinsn_t tmp_vinsn
, tmp2_vinsn
;
3329 tmp_vinsn
= EXPR_VINSN (tmp
);
3330 tmp2_vinsn
= EXPR_VINSN (tmp2
);
3331 tmp_insn
= EXPR_INSN_RTX (tmp
);
3332 tmp2_insn
= EXPR_INSN_RTX (tmp2
);
3334 /* Schedule debug insns as early as possible. */
3335 if (DEBUG_INSN_P (tmp_insn
) && !DEBUG_INSN_P (tmp2_insn
))
3337 else if (DEBUG_INSN_P (tmp2_insn
))
3340 /* Prefer SCHED_GROUP_P insns to any others. */
3341 if (SCHED_GROUP_P (tmp_insn
) != SCHED_GROUP_P (tmp2_insn
))
3343 if (VINSN_UNIQUE_P (tmp_vinsn
) && VINSN_UNIQUE_P (tmp2_vinsn
))
3344 return SCHED_GROUP_P (tmp2_insn
) ? 1 : -1;
3346 /* Now uniqueness means SCHED_GROUP_P is set, because schedule groups
3347 cannot be cloned. */
3348 if (VINSN_UNIQUE_P (tmp2_vinsn
))
3353 /* Discourage scheduling of speculative checks. */
3354 val
= (sel_insn_is_speculation_check (tmp_insn
)
3355 - sel_insn_is_speculation_check (tmp2_insn
));
3359 /* Prefer not scheduled insn over scheduled one. */
3360 if (EXPR_SCHED_TIMES (tmp
) > 0 || EXPR_SCHED_TIMES (tmp2
) > 0)
3362 val
= EXPR_SCHED_TIMES (tmp
) - EXPR_SCHED_TIMES (tmp2
);
3367 /* Prefer jump over non-jump instruction. */
3368 if (control_flow_insn_p (tmp_insn
) && !control_flow_insn_p (tmp2_insn
))
3370 else if (control_flow_insn_p (tmp2_insn
) && !control_flow_insn_p (tmp_insn
))
3373 /* Prefer an expr with greater priority. */
3374 if (EXPR_USEFULNESS (tmp
) != 0 && EXPR_USEFULNESS (tmp2
) != 0)
3376 int p2
= EXPR_PRIORITY (tmp2
) + EXPR_PRIORITY_ADJ (tmp2
),
3377 p1
= EXPR_PRIORITY (tmp
) + EXPR_PRIORITY_ADJ (tmp
);
3379 val
= p2
* EXPR_USEFULNESS (tmp2
) - p1
* EXPR_USEFULNESS (tmp
);
3382 val
= EXPR_PRIORITY (tmp2
) - EXPR_PRIORITY (tmp
)
3383 + EXPR_PRIORITY_ADJ (tmp2
) - EXPR_PRIORITY_ADJ (tmp
);
3387 if (spec_info
!= NULL
&& spec_info
->mask
!= 0)
3388 /* This code was taken from haifa-sched.c: rank_for_schedule (). */
3394 ds1
= EXPR_SPEC_DONE_DS (tmp
);
3396 dw1
= ds_weak (ds1
);
3400 ds2
= EXPR_SPEC_DONE_DS (tmp2
);
3402 dw2
= ds_weak (ds2
);
3407 if (dw
> (NO_DEP_WEAK
/ 8) || dw
< -(NO_DEP_WEAK
/ 8))
3411 /* Prefer an old insn to a bookkeeping insn. */
3412 if (INSN_UID (tmp_insn
) < first_emitted_uid
3413 && INSN_UID (tmp2_insn
) >= first_emitted_uid
)
3415 if (INSN_UID (tmp_insn
) >= first_emitted_uid
3416 && INSN_UID (tmp2_insn
) < first_emitted_uid
)
3419 /* Prefer an insn with smaller UID, as a last resort.
3420 We can't safely use INSN_LUID as it is defined only for those insns
3421 that are in the stream. */
3422 return INSN_UID (tmp_insn
) - INSN_UID (tmp2_insn
);
3425 /* Filter out expressions from av set pointed to by AV_PTR
3426 that are pipelined too many times. */
3428 process_pipelined_exprs (av_set_t
*av_ptr
)
3433 /* Don't pipeline already pipelined code as that would increase
3434 number of unnecessary register moves. */
3435 FOR_EACH_EXPR_1 (expr
, si
, av_ptr
)
3437 if (EXPR_SCHED_TIMES (expr
)
3438 >= PARAM_VALUE (PARAM_SELSCHED_MAX_SCHED_TIMES
))
3439 av_set_iter_remove (&si
);
3443 /* Filter speculative insns from AV_PTR if we don't want them. */
3445 process_spec_exprs (av_set_t
*av_ptr
)
3447 bool try_data_p
= true;
3448 bool try_control_p
= true;
3452 if (spec_info
== NULL
)
3455 /* Scan *AV_PTR to find out if we want to consider speculative
3456 instructions for scheduling. */
3457 FOR_EACH_EXPR_1 (expr
, si
, av_ptr
)
3461 ds
= EXPR_SPEC_DONE_DS (expr
);
3463 /* The probability of a success is too low - don't speculate. */
3464 if ((ds
& SPECULATIVE
)
3465 && (ds_weak (ds
) < spec_info
->data_weakness_cutoff
3466 || EXPR_USEFULNESS (expr
) < spec_info
->control_weakness_cutoff
3467 || (pipelining_p
&& false
3469 && (ds
& CONTROL_SPEC
))))
3471 av_set_iter_remove (&si
);
3475 if ((spec_info
->flags
& PREFER_NON_DATA_SPEC
)
3476 && !(ds
& BEGIN_DATA
))
3479 if ((spec_info
->flags
& PREFER_NON_CONTROL_SPEC
)
3480 && !(ds
& BEGIN_CONTROL
))
3481 try_control_p
= false;
3484 FOR_EACH_EXPR_1 (expr
, si
, av_ptr
)
3488 ds
= EXPR_SPEC_DONE_DS (expr
);
3490 if (ds
& SPECULATIVE
)
3492 if ((ds
& BEGIN_DATA
) && !try_data_p
)
3493 /* We don't want any data speculative instructions right
3495 av_set_iter_remove (&si
);
3497 if ((ds
& BEGIN_CONTROL
) && !try_control_p
)
3498 /* We don't want any control speculative instructions right
3500 av_set_iter_remove (&si
);
3505 /* Search for any use-like insns in AV_PTR and decide on scheduling
3506 them. Return one when found, and NULL otherwise.
3507 Note that we check here whether a USE could be scheduled to avoid
3508 an infinite loop later. */
3510 process_use_exprs (av_set_t
*av_ptr
)
3514 bool uses_present_p
= false;
3515 bool try_uses_p
= true;
3517 FOR_EACH_EXPR_1 (expr
, si
, av_ptr
)
3519 /* This will also initialize INSN_CODE for later use. */
3520 if (recog_memoized (EXPR_INSN_RTX (expr
)) < 0)
3522 /* If we have a USE in *AV_PTR that was not scheduled yet,
3523 do so because it will do good only. */
3524 if (EXPR_SCHED_TIMES (expr
) <= 0)
3526 if (EXPR_TARGET_AVAILABLE (expr
) == 1)
3529 av_set_iter_remove (&si
);
3533 gcc_assert (pipelining_p
);
3535 uses_present_p
= true;
3544 /* If we don't want to schedule any USEs right now and we have some
3545 in *AV_PTR, remove them, else just return the first one found. */
3548 FOR_EACH_EXPR_1 (expr
, si
, av_ptr
)
3549 if (INSN_CODE (EXPR_INSN_RTX (expr
)) < 0)
3550 av_set_iter_remove (&si
);
3554 FOR_EACH_EXPR_1 (expr
, si
, av_ptr
)
3556 gcc_assert (INSN_CODE (EXPR_INSN_RTX (expr
)) < 0);
3558 if (EXPR_TARGET_AVAILABLE (expr
) == 1)
3561 av_set_iter_remove (&si
);
3569 /* Lookup EXPR in VINSN_VEC and return TRUE if found. */
3571 vinsn_vec_has_expr_p (vinsn_vec_t vinsn_vec
, expr_t expr
)
3576 for (n
= 0; VEC_iterate (vinsn_t
, vinsn_vec
, n
, vinsn
); n
++)
3577 if (VINSN_SEPARABLE_P (vinsn
))
3579 if (vinsn_equal_p (vinsn
, EXPR_VINSN (expr
)))
3584 /* For non-separable instructions, the blocking insn can have
3585 another pattern due to substitution, and we can't choose
3586 different register as in the above case. Check all registers
3587 being written instead. */
3588 if (bitmap_intersect_p (VINSN_REG_SETS (vinsn
),
3589 VINSN_REG_SETS (EXPR_VINSN (expr
))))
3596 #ifdef ENABLE_CHECKING
3597 /* Return true if either of expressions from ORIG_OPS can be blocked
3598 by previously created bookkeeping code. STATIC_PARAMS points to static
3599 parameters of move_op. */
3601 av_set_could_be_blocked_by_bookkeeping_p (av_set_t orig_ops
, void *static_params
)
3604 av_set_iterator iter
;
3605 moveop_static_params_p sparams
;
3607 /* This checks that expressions in ORIG_OPS are not blocked by bookkeeping
3608 created while scheduling on another fence. */
3609 FOR_EACH_EXPR (expr
, iter
, orig_ops
)
3610 if (vinsn_vec_has_expr_p (vec_bookkeeping_blocked_vinsns
, expr
))
3613 gcc_assert (code_motion_path_driver_info
== &move_op_hooks
);
3614 sparams
= (moveop_static_params_p
) static_params
;
3616 /* Expressions can be also blocked by bookkeeping created during current
3618 if (bitmap_bit_p (current_copies
, INSN_UID (sparams
->failed_insn
)))
3619 FOR_EACH_EXPR (expr
, iter
, orig_ops
)
3620 if (moveup_expr_cached (expr
, sparams
->failed_insn
, false) != MOVEUP_EXPR_NULL
)
3623 /* Expressions in ORIG_OPS may have wrong destination register due to
3624 renaming. Check with the right register instead. */
3625 if (sparams
->dest
&& REG_P (sparams
->dest
))
3627 unsigned regno
= REGNO (sparams
->dest
);
3628 vinsn_t failed_vinsn
= INSN_VINSN (sparams
->failed_insn
);
3630 if (bitmap_bit_p (VINSN_REG_SETS (failed_vinsn
), regno
)
3631 || bitmap_bit_p (VINSN_REG_USES (failed_vinsn
), regno
)
3632 || bitmap_bit_p (VINSN_REG_CLOBBERS (failed_vinsn
), regno
))
3640 /* Clear VINSN_VEC and detach vinsns. */
3642 vinsn_vec_clear (vinsn_vec_t
*vinsn_vec
)
3644 unsigned len
= VEC_length (vinsn_t
, *vinsn_vec
);
3650 for (n
= 0; VEC_iterate (vinsn_t
, *vinsn_vec
, n
, vinsn
); n
++)
3651 vinsn_detach (vinsn
);
3652 VEC_block_remove (vinsn_t
, *vinsn_vec
, 0, len
);
3656 /* Add the vinsn of EXPR to the VINSN_VEC. */
3658 vinsn_vec_add (vinsn_vec_t
*vinsn_vec
, expr_t expr
)
3660 vinsn_attach (EXPR_VINSN (expr
));
3661 VEC_safe_push (vinsn_t
, heap
, *vinsn_vec
, EXPR_VINSN (expr
));
3664 /* Free the vector representing blocked expressions. */
3666 vinsn_vec_free (vinsn_vec_t
*vinsn_vec
)
3669 VEC_free (vinsn_t
, heap
, *vinsn_vec
);
3672 /* Increase EXPR_PRIORITY_ADJ for INSN by AMOUNT. */
3674 void sel_add_to_insn_priority (rtx insn
, int amount
)
3676 EXPR_PRIORITY_ADJ (INSN_EXPR (insn
)) += amount
;
3678 if (sched_verbose
>= 2)
3679 sel_print ("sel_add_to_insn_priority: insn %d, by %d (now %d+%d).\n",
3680 INSN_UID (insn
), amount
, EXPR_PRIORITY (INSN_EXPR (insn
)),
3681 EXPR_PRIORITY_ADJ (INSN_EXPR (insn
)));
3684 /* Turn AV into a vector, filter inappropriate insns and sort it. Return
3685 true if there is something to schedule. BNDS and FENCE are current
3686 boundaries and fence, respectively. If we need to stall for some cycles
3687 before an expr from AV would become available, write this number to
3690 fill_vec_av_set (av_set_t av
, blist_t bnds
, fence_t fence
,
3695 int sched_next_worked
= 0, stalled
, n
;
3696 static int av_max_prio
, est_ticks_till_branch
;
3697 int min_need_stall
= -1;
3698 deps_t dc
= BND_DC (BLIST_BND (bnds
));
3700 /* Bail out early when the ready list contained only USEs/CLOBBERs that are
3701 already scheduled. */
3705 /* Empty vector from the previous stuff. */
3706 if (VEC_length (expr_t
, vec_av_set
) > 0)
3707 VEC_block_remove (expr_t
, vec_av_set
, 0, VEC_length (expr_t
, vec_av_set
));
3709 /* Turn the set into a vector for sorting and call sel_target_adjust_priority
3711 gcc_assert (VEC_empty (expr_t
, vec_av_set
));
3712 FOR_EACH_EXPR (expr
, si
, av
)
3714 VEC_safe_push (expr_t
, heap
, vec_av_set
, expr
);
3716 gcc_assert (EXPR_PRIORITY_ADJ (expr
) == 0 || *pneed_stall
);
3718 /* Adjust priority using target backend hook. */
3719 sel_target_adjust_priority (expr
);
3722 /* Sort the vector. */
3723 qsort (VEC_address (expr_t
, vec_av_set
), VEC_length (expr_t
, vec_av_set
),
3724 sizeof (expr_t
), sel_rank_for_schedule
);
3726 /* We record maximal priority of insns in av set for current instruction
3728 if (FENCE_STARTS_CYCLE_P (fence
))
3729 av_max_prio
= est_ticks_till_branch
= INT_MIN
;
3731 /* Filter out inappropriate expressions. Loop's direction is reversed to
3732 visit "best" instructions first. We assume that VEC_unordered_remove
3733 moves last element in place of one being deleted. */
3734 for (n
= VEC_length (expr_t
, vec_av_set
) - 1, stalled
= 0; n
>= 0; n
--)
3736 expr_t expr
= VEC_index (expr_t
, vec_av_set
, n
);
3737 insn_t insn
= EXPR_INSN_RTX (expr
);
3738 char target_available
;
3739 bool is_orig_reg_p
= true;
3740 int need_cycles
, new_prio
;
3742 /* Don't allow any insns other than from SCHED_GROUP if we have one. */
3743 if (FENCE_SCHED_NEXT (fence
) && insn
!= FENCE_SCHED_NEXT (fence
))
3745 VEC_unordered_remove (expr_t
, vec_av_set
, n
);
3749 /* Set number of sched_next insns (just in case there
3750 could be several). */
3751 if (FENCE_SCHED_NEXT (fence
))
3752 sched_next_worked
++;
3754 /* Check all liveness requirements and try renaming.
3755 FIXME: try to minimize calls to this. */
3756 target_available
= EXPR_TARGET_AVAILABLE (expr
);
3758 /* If insn was already scheduled on the current fence,
3759 set TARGET_AVAILABLE to -1 no matter what expr's attribute says. */
3760 if (vinsn_vec_has_expr_p (vec_target_unavailable_vinsns
, expr
))
3761 target_available
= -1;
3763 /* If the availability of the EXPR is invalidated by the insertion of
3764 bookkeeping earlier, make sure that we won't choose this expr for
3765 scheduling if it's not separable, and if it is separable, then
3766 we have to recompute the set of available registers for it. */
3767 if (vinsn_vec_has_expr_p (vec_bookkeeping_blocked_vinsns
, expr
))
3769 VEC_unordered_remove (expr_t
, vec_av_set
, n
);
3770 if (sched_verbose
>= 4)
3771 sel_print ("Expr %d is blocked by bookkeeping inserted earlier\n",
3776 if (target_available
== true)
3778 /* Do nothing -- we can use an existing register. */
3779 is_orig_reg_p
= EXPR_SEPARABLE_P (expr
);
3781 else if (/* Non-separable instruction will never
3782 get another register. */
3783 (target_available
== false
3784 && !EXPR_SEPARABLE_P (expr
))
3785 /* Don't try to find a register for low-priority expression. */
3786 || (int) VEC_length (expr_t
, vec_av_set
) - 1 - n
>= max_insns_to_rename
3787 /* ??? FIXME: Don't try to rename data speculation. */
3788 || (EXPR_SPEC_DONE_DS (expr
) & BEGIN_DATA
)
3789 || ! find_best_reg_for_expr (expr
, bnds
, &is_orig_reg_p
))
3791 VEC_unordered_remove (expr_t
, vec_av_set
, n
);
3792 if (sched_verbose
>= 4)
3793 sel_print ("Expr %d has no suitable target register\n",
3798 /* Filter expressions that need to be renamed or speculated when
3799 pipelining, because compensating register copies or speculation
3800 checks are likely to be placed near the beginning of the loop,
3802 if (pipelining_p
&& EXPR_ORIG_SCHED_CYCLE (expr
) > 0
3803 && (!is_orig_reg_p
|| EXPR_SPEC_DONE_DS (expr
) != 0))
3805 /* Estimation of number of cycles until loop branch for
3806 renaming/speculation to be successful. */
3807 int need_n_ticks_till_branch
= sel_vinsn_cost (EXPR_VINSN (expr
));
3809 if ((int) current_loop_nest
->ninsns
< 9)
3811 VEC_unordered_remove (expr_t
, vec_av_set
, n
);
3812 if (sched_verbose
>= 4)
3813 sel_print ("Pipelining expr %d will likely cause stall\n",
3818 if ((int) current_loop_nest
->ninsns
- num_insns_scheduled
3819 < need_n_ticks_till_branch
* issue_rate
/ 2
3820 && est_ticks_till_branch
< need_n_ticks_till_branch
)
3822 VEC_unordered_remove (expr_t
, vec_av_set
, n
);
3823 if (sched_verbose
>= 4)
3824 sel_print ("Pipelining expr %d will likely cause stall\n",
3830 /* We want to schedule speculation checks as late as possible. Discard
3831 them from av set if there are instructions with higher priority. */
3832 if (sel_insn_is_speculation_check (insn
)
3833 && EXPR_PRIORITY (expr
) < av_max_prio
)
3836 min_need_stall
= min_need_stall
< 0 ? 1 : MIN (min_need_stall
, 1);
3837 VEC_unordered_remove (expr_t
, vec_av_set
, n
);
3838 if (sched_verbose
>= 4)
3839 sel_print ("Delaying speculation check %d until its first use\n",
3844 /* Ignore EXPRs available from pipelining to update AV_MAX_PRIO. */
3845 if (EXPR_ORIG_SCHED_CYCLE (expr
) <= 0)
3846 av_max_prio
= MAX (av_max_prio
, EXPR_PRIORITY (expr
));
3848 /* Don't allow any insns whose data is not yet ready.
3849 Check first whether we've already tried them and failed. */
3850 if (INSN_UID (insn
) < FENCE_READY_TICKS_SIZE (fence
))
3852 need_cycles
= (FENCE_READY_TICKS (fence
)[INSN_UID (insn
)]
3853 - FENCE_CYCLE (fence
));
3854 if (EXPR_ORIG_SCHED_CYCLE (expr
) <= 0)
3855 est_ticks_till_branch
= MAX (est_ticks_till_branch
,
3856 EXPR_PRIORITY (expr
) + need_cycles
);
3858 if (need_cycles
> 0)
3861 min_need_stall
= (min_need_stall
< 0
3863 : MIN (min_need_stall
, need_cycles
));
3864 VEC_unordered_remove (expr_t
, vec_av_set
, n
);
3866 if (sched_verbose
>= 4)
3867 sel_print ("Expr %d is not ready until cycle %d (cached)\n",
3869 FENCE_READY_TICKS (fence
)[INSN_UID (insn
)]);
3874 /* Now resort to dependence analysis to find whether EXPR might be
3875 stalled due to dependencies from FENCE's context. */
3876 need_cycles
= tick_check_p (expr
, dc
, fence
);
3877 new_prio
= EXPR_PRIORITY (expr
) + EXPR_PRIORITY_ADJ (expr
) + need_cycles
;
3879 if (EXPR_ORIG_SCHED_CYCLE (expr
) <= 0)
3880 est_ticks_till_branch
= MAX (est_ticks_till_branch
,
3883 if (need_cycles
> 0)
3885 if (INSN_UID (insn
) >= FENCE_READY_TICKS_SIZE (fence
))
3887 int new_size
= INSN_UID (insn
) * 3 / 2;
3889 FENCE_READY_TICKS (fence
)
3890 = (int *) xrecalloc (FENCE_READY_TICKS (fence
),
3891 new_size
, FENCE_READY_TICKS_SIZE (fence
),
3894 FENCE_READY_TICKS (fence
)[INSN_UID (insn
)]
3895 = FENCE_CYCLE (fence
) + need_cycles
;
3898 min_need_stall
= (min_need_stall
< 0
3900 : MIN (min_need_stall
, need_cycles
));
3902 VEC_unordered_remove (expr_t
, vec_av_set
, n
);
3904 if (sched_verbose
>= 4)
3905 sel_print ("Expr %d is not ready yet until cycle %d\n",
3907 FENCE_READY_TICKS (fence
)[INSN_UID (insn
)]);
3911 if (sched_verbose
>= 4)
3912 sel_print ("Expr %d is ok\n", INSN_UID (insn
));
3916 /* Clear SCHED_NEXT. */
3917 if (FENCE_SCHED_NEXT (fence
))
3919 gcc_assert (sched_next_worked
== 1);
3920 FENCE_SCHED_NEXT (fence
) = NULL_RTX
;
3923 /* No need to stall if this variable was not initialized. */
3924 if (min_need_stall
< 0)
3927 if (VEC_empty (expr_t
, vec_av_set
))
3929 /* We need to set *pneed_stall here, because later we skip this code
3930 when ready list is empty. */
3931 *pneed_stall
= min_need_stall
;
3935 gcc_assert (min_need_stall
== 0);
3937 /* Sort the vector. */
3938 qsort (VEC_address (expr_t
, vec_av_set
), VEC_length (expr_t
, vec_av_set
),
3939 sizeof (expr_t
), sel_rank_for_schedule
);
3941 if (sched_verbose
>= 4)
3943 sel_print ("Total ready exprs: %d, stalled: %d\n",
3944 VEC_length (expr_t
, vec_av_set
), stalled
);
3945 sel_print ("Sorted av set (%d): ", VEC_length (expr_t
, vec_av_set
));
3946 for (n
= 0; VEC_iterate (expr_t
, vec_av_set
, n
, expr
); n
++)
3955 /* Convert a vectored and sorted av set to the ready list that
3956 the rest of the backend wants to see. */
3958 convert_vec_av_set_to_ready (void)
3963 /* Allocate and fill the ready list from the sorted vector. */
3964 ready
.n_ready
= VEC_length (expr_t
, vec_av_set
);
3965 ready
.first
= ready
.n_ready
- 1;
3967 gcc_assert (ready
.n_ready
> 0);
3969 if (ready
.n_ready
> max_issue_size
)
3971 max_issue_size
= ready
.n_ready
;
3972 sched_extend_ready_list (ready
.n_ready
);
3975 for (n
= 0; VEC_iterate (expr_t
, vec_av_set
, n
, expr
); n
++)
3977 vinsn_t vi
= EXPR_VINSN (expr
);
3978 insn_t insn
= VINSN_INSN_RTX (vi
);
3981 ready
.vec
[n
] = insn
;
3985 /* Initialize ready list from *AV_PTR for the max_issue () call.
3986 If any unrecognizable insn found in *AV_PTR, return it (and skip
3987 max_issue). BND and FENCE are current boundary and fence,
3988 respectively. If we need to stall for some cycles before an expr
3989 from *AV_PTR would become available, write this number to *PNEED_STALL. */
3991 fill_ready_list (av_set_t
*av_ptr
, blist_t bnds
, fence_t fence
,
3996 /* We do not support multiple boundaries per fence. */
3997 gcc_assert (BLIST_NEXT (bnds
) == NULL
);
3999 /* Process expressions required special handling, i.e. pipelined,
4000 speculative and recog() < 0 expressions first. */
4001 process_pipelined_exprs (av_ptr
);
4002 process_spec_exprs (av_ptr
);
4004 /* A USE could be scheduled immediately. */
4005 expr
= process_use_exprs (av_ptr
);
4012 /* Turn the av set to a vector for sorting. */
4013 if (! fill_vec_av_set (*av_ptr
, bnds
, fence
, pneed_stall
))
4019 /* Build the final ready list. */
4020 convert_vec_av_set_to_ready ();
4024 /* Wrapper for dfa_new_cycle (). Returns TRUE if cycle was advanced. */
4026 sel_dfa_new_cycle (insn_t insn
, fence_t fence
)
4028 int last_scheduled_cycle
= FENCE_LAST_SCHEDULED_INSN (fence
)
4029 ? INSN_SCHED_CYCLE (FENCE_LAST_SCHEDULED_INSN (fence
))
4030 : FENCE_CYCLE (fence
) - 1;
4034 if (!targetm
.sched
.dfa_new_cycle
)
4037 memcpy (curr_state
, FENCE_STATE (fence
), dfa_state_size
);
4039 while (!sort_p
&& targetm
.sched
.dfa_new_cycle (sched_dump
, sched_verbose
,
4040 insn
, last_scheduled_cycle
,
4041 FENCE_CYCLE (fence
), &sort_p
))
4043 memcpy (FENCE_STATE (fence
), curr_state
, dfa_state_size
);
4044 advance_one_cycle (fence
);
4045 memcpy (curr_state
, FENCE_STATE (fence
), dfa_state_size
);
4052 /* Invoke reorder* target hooks on the ready list. Return the number of insns
4053 we can issue. FENCE is the current fence. */
4055 invoke_reorder_hooks (fence_t fence
)
4058 bool ran_hook
= false;
4060 /* Call the reorder hook at the beginning of the cycle, and call
4061 the reorder2 hook in the middle of the cycle. */
4062 if (FENCE_ISSUED_INSNS (fence
) == 0)
4064 if (targetm
.sched
.reorder
4065 && !SCHED_GROUP_P (ready_element (&ready
, 0))
4066 && ready
.n_ready
> 1)
4068 /* Don't give reorder the most prioritized insn as it can break
4074 = targetm
.sched
.reorder (sched_dump
, sched_verbose
,
4075 ready_lastpos (&ready
),
4076 &ready
.n_ready
, FENCE_CYCLE (fence
));
4084 /* Initialize can_issue_more for variable_issue. */
4085 issue_more
= issue_rate
;
4087 else if (targetm
.sched
.reorder2
4088 && !SCHED_GROUP_P (ready_element (&ready
, 0)))
4090 if (ready
.n_ready
== 1)
4092 targetm
.sched
.reorder2 (sched_dump
, sched_verbose
,
4093 ready_lastpos (&ready
),
4094 &ready
.n_ready
, FENCE_CYCLE (fence
));
4101 targetm
.sched
.reorder2 (sched_dump
, sched_verbose
,
4103 ? ready_lastpos (&ready
) : NULL
,
4104 &ready
.n_ready
, FENCE_CYCLE (fence
));
4113 issue_more
= FENCE_ISSUE_MORE (fence
);
4115 /* Ensure that ready list and vec_av_set are in line with each other,
4116 i.e. vec_av_set[i] == ready_element (&ready, i). */
4117 if (issue_more
&& ran_hook
)
4120 rtx
*arr
= ready
.vec
;
4121 expr_t
*vec
= VEC_address (expr_t
, vec_av_set
);
4123 for (i
= 0, n
= ready
.n_ready
; i
< n
; i
++)
4124 if (EXPR_INSN_RTX (vec
[i
]) != arr
[i
])
4128 for (j
= i
; j
< n
; j
++)
4129 if (EXPR_INSN_RTX (vec
[j
]) == arr
[i
])
4142 /* Return an EXPR correponding to INDEX element of ready list, if
4143 FOLLOW_READY_ELEMENT is true (i.e., an expr of
4144 ready_element (&ready, INDEX) will be returned), and to INDEX element of
4145 ready.vec otherwise. */
4146 static inline expr_t
4147 find_expr_for_ready (int index
, bool follow_ready_element
)
4152 real_index
= follow_ready_element
? ready
.first
- index
: index
;
4154 expr
= VEC_index (expr_t
, vec_av_set
, real_index
);
4155 gcc_assert (ready
.vec
[real_index
] == EXPR_INSN_RTX (expr
));
4160 /* Calculate insns worth trying via lookahead_guard hook. Return a number
4161 of such insns found. */
4163 invoke_dfa_lookahead_guard (void)
4167 = targetm
.sched
.first_cycle_multipass_dfa_lookahead_guard
!= NULL
;
4169 if (sched_verbose
>= 2)
4170 sel_print ("ready after reorder: ");
4172 for (i
= 0, n
= 0; i
< ready
.n_ready
; i
++)
4178 /* In this loop insn is Ith element of the ready list given by
4179 ready_element, not Ith element of ready.vec. */
4180 insn
= ready_element (&ready
, i
);
4182 if (! have_hook
|| i
== 0)
4185 r
= !targetm
.sched
.first_cycle_multipass_dfa_lookahead_guard (insn
);
4187 gcc_assert (INSN_CODE (insn
) >= 0);
4189 /* Only insns with ready_try = 0 can get here
4190 from fill_ready_list. */
4191 gcc_assert (ready_try
[i
] == 0);
4196 expr
= find_expr_for_ready (i
, true);
4198 if (sched_verbose
>= 2)
4200 dump_vinsn (EXPR_VINSN (expr
));
4201 sel_print (":%d; ", ready_try
[i
]);
4205 if (sched_verbose
>= 2)
4210 /* Calculate the number of privileged insns and return it. */
4212 calculate_privileged_insns (void)
4214 expr_t cur_expr
, min_spec_expr
= NULL
;
4215 int privileged_n
= 0, i
;
4217 for (i
= 0; i
< ready
.n_ready
; i
++)
4222 if (! min_spec_expr
)
4223 min_spec_expr
= find_expr_for_ready (i
, true);
4225 cur_expr
= find_expr_for_ready (i
, true);
4227 if (EXPR_SPEC (cur_expr
) > EXPR_SPEC (min_spec_expr
))
4233 if (i
== ready
.n_ready
)
4236 if (sched_verbose
>= 2)
4237 sel_print ("privileged_n: %d insns with SPEC %d\n",
4238 privileged_n
, privileged_n
? EXPR_SPEC (min_spec_expr
) : -1);
4239 return privileged_n
;
4242 /* Call the rest of the hooks after the choice was made. Return
4243 the number of insns that still can be issued given that the current
4244 number is ISSUE_MORE. FENCE and BEST_INSN are the current fence
4245 and the insn chosen for scheduling, respectively. */
4247 invoke_aftermath_hooks (fence_t fence
, rtx best_insn
, int issue_more
)
4249 gcc_assert (INSN_P (best_insn
));
4251 /* First, call dfa_new_cycle, and then variable_issue, if available. */
4252 sel_dfa_new_cycle (best_insn
, fence
);
4254 if (targetm
.sched
.variable_issue
)
4256 memcpy (curr_state
, FENCE_STATE (fence
), dfa_state_size
);
4258 targetm
.sched
.variable_issue (sched_dump
, sched_verbose
, best_insn
,
4260 memcpy (FENCE_STATE (fence
), curr_state
, dfa_state_size
);
4262 else if (GET_CODE (PATTERN (best_insn
)) != USE
4263 && GET_CODE (PATTERN (best_insn
)) != CLOBBER
)
4269 /* Estimate the cost of issuing INSN on DFA state STATE. */
4271 estimate_insn_cost (rtx insn
, state_t state
)
4273 static state_t temp
= NULL
;
4277 temp
= xmalloc (dfa_state_size
);
4279 memcpy (temp
, state
, dfa_state_size
);
4280 cost
= state_transition (temp
, insn
);
4289 /* Return the cost of issuing EXPR on the FENCE as estimated by DFA.
4290 This function properly handles ASMs, USEs etc. */
4292 get_expr_cost (expr_t expr
, fence_t fence
)
4294 rtx insn
= EXPR_INSN_RTX (expr
);
4296 if (recog_memoized (insn
) < 0)
4298 if (!FENCE_STARTS_CYCLE_P (fence
)
4299 && INSN_ASM_P (insn
))
4300 /* This is asm insn which is tryed to be issued on the
4301 cycle not first. Issue it on the next cycle. */
4304 /* A USE insn, or something else we don't need to
4305 understand. We can't pass these directly to
4306 state_transition because it will trigger a
4307 fatal error for unrecognizable insns. */
4311 return estimate_insn_cost (insn
, FENCE_STATE (fence
));
4314 /* Find the best insn for scheduling, either via max_issue or just take
4315 the most prioritized available. */
4317 choose_best_insn (fence_t fence
, int privileged_n
, int *index
)
4321 if (dfa_lookahead
> 0)
4323 cycle_issued_insns
= FENCE_ISSUED_INSNS (fence
);
4324 can_issue
= max_issue (&ready
, privileged_n
,
4325 FENCE_STATE (fence
), index
);
4326 if (sched_verbose
>= 2)
4327 sel_print ("max_issue: we can issue %d insns, already did %d insns\n",
4328 can_issue
, FENCE_ISSUED_INSNS (fence
));
4332 /* We can't use max_issue; just return the first available element. */
4335 for (i
= 0; i
< ready
.n_ready
; i
++)
4337 expr_t expr
= find_expr_for_ready (i
, true);
4339 if (get_expr_cost (expr
, fence
) < 1)
4341 can_issue
= can_issue_more
;
4344 if (sched_verbose
>= 2)
4345 sel_print ("using %dth insn from the ready list\n", i
+ 1);
4351 if (i
== ready
.n_ready
)
4361 /* Choose the best expr from *AV_VLIW_PTR and a suitable register for it.
4362 BNDS and FENCE are current boundaries and scheduling fence respectively.
4363 Return the expr found and NULL if nothing can be issued atm.
4364 Write to PNEED_STALL the number of cycles to stall if no expr was found. */
4366 find_best_expr (av_set_t
*av_vliw_ptr
, blist_t bnds
, fence_t fence
,
4371 /* Choose the best insn for scheduling via:
4372 1) sorting the ready list based on priority;
4373 2) calling the reorder hook;
4374 3) calling max_issue. */
4375 best
= fill_ready_list (av_vliw_ptr
, bnds
, fence
, pneed_stall
);
4376 if (best
== NULL
&& ready
.n_ready
> 0)
4378 int privileged_n
, index
;
4380 can_issue_more
= invoke_reorder_hooks (fence
);
4381 if (can_issue_more
> 0)
4383 /* Try choosing the best insn until we find one that is could be
4384 scheduled due to liveness restrictions on its destination register.
4385 In the future, we'd like to choose once and then just probe insns
4386 in the order of their priority. */
4387 invoke_dfa_lookahead_guard ();
4388 privileged_n
= calculate_privileged_insns ();
4389 can_issue_more
= choose_best_insn (fence
, privileged_n
, &index
);
4391 best
= find_expr_for_ready (index
, true);
4393 /* We had some available insns, so if we can't issue them,
4395 if (can_issue_more
== 0)
4404 can_issue_more
= invoke_aftermath_hooks (fence
, EXPR_INSN_RTX (best
),
4406 if (can_issue_more
== 0)
4410 if (sched_verbose
>= 2)
4414 sel_print ("Best expression (vliw form): ");
4416 sel_print ("; cycle %d\n", FENCE_CYCLE (fence
));
4419 sel_print ("No best expr found!\n");
4426 /* Functions that implement the core of the scheduler. */
4429 /* Emit an instruction from EXPR with SEQNO and VINSN after
4432 emit_insn_from_expr_after (expr_t expr
, vinsn_t vinsn
, int seqno
,
4433 insn_t place_to_insert
)
4435 /* This assert fails when we have identical instructions
4436 one of which dominates the other. In this case move_op ()
4437 finds the first instruction and doesn't search for second one.
4438 The solution would be to compute av_set after the first found
4439 insn and, if insn present in that set, continue searching.
4440 For now we workaround this issue in move_op. */
4441 gcc_assert (!INSN_IN_STREAM_P (EXPR_INSN_RTX (expr
)));
4443 if (EXPR_WAS_RENAMED (expr
))
4445 unsigned regno
= expr_dest_regno (expr
);
4447 if (HARD_REGISTER_NUM_P (regno
))
4449 df_set_regs_ever_live (regno
, true);
4450 reg_rename_tick
[regno
] = ++reg_rename_this_tick
;
4454 return sel_gen_insn_from_expr_after (expr
, vinsn
, seqno
,
4458 /* Return TRUE if BB can hold bookkeeping code. */
4460 block_valid_for_bookkeeping_p (basic_block bb
)
4462 insn_t bb_end
= BB_END (bb
);
4464 if (!in_current_region_p (bb
) || EDGE_COUNT (bb
->succs
) > 1)
4467 if (INSN_P (bb_end
))
4469 if (INSN_SCHED_TIMES (bb_end
) > 0)
4473 gcc_assert (NOTE_INSN_BASIC_BLOCK_P (bb_end
));
4478 /* Attempt to find a block that can hold bookkeeping code for path(s) incoming
4479 into E2->dest, except from E1->src (there may be a sequence of empty basic
4480 blocks between E1->src and E2->dest). Return found block, or NULL if new
4481 one must be created. If LAX holds, don't assume there is a simple path
4482 from E1->src to E2->dest. */
4484 find_block_for_bookkeeping (edge e1
, edge e2
, bool lax
)
4486 basic_block candidate_block
= NULL
;
4489 /* Loop over edges from E1 to E2, inclusive. */
4490 for (e
= e1
; !lax
|| e
->dest
!= EXIT_BLOCK_PTR
; e
= EDGE_SUCC (e
->dest
, 0))
4492 if (EDGE_COUNT (e
->dest
->preds
) == 2)
4494 if (candidate_block
== NULL
)
4495 candidate_block
= (EDGE_PRED (e
->dest
, 0) == e
4496 ? EDGE_PRED (e
->dest
, 1)->src
4497 : EDGE_PRED (e
->dest
, 0)->src
);
4499 /* Found additional edge leading to path from e1 to e2
4503 else if (EDGE_COUNT (e
->dest
->preds
) > 2)
4504 /* Several edges leading to path from e1 to e2 from aside. */
4508 return ((!lax
|| candidate_block
)
4509 && block_valid_for_bookkeeping_p (candidate_block
)
4513 if (lax
&& EDGE_COUNT (e
->dest
->succs
) != 1)
4523 /* Create new basic block for bookkeeping code for path(s) incoming into
4524 E2->dest, except from E1->src. Return created block. */
4526 create_block_for_bookkeeping (edge e1
, edge e2
)
4528 basic_block new_bb
, bb
= e2
->dest
;
4530 /* Check that we don't spoil the loop structure. */
4531 if (current_loop_nest
)
4533 basic_block latch
= current_loop_nest
->latch
;
4535 /* We do not split header. */
4536 gcc_assert (e2
->dest
!= current_loop_nest
->header
);
4538 /* We do not redirect the only edge to the latch block. */
4539 gcc_assert (e1
->dest
!= latch
4540 || !single_pred_p (latch
)
4541 || e1
!= single_pred_edge (latch
));
4544 /* Split BB to insert BOOK_INSN there. */
4545 new_bb
= sched_split_block (bb
, NULL
);
4547 /* Move note_list from the upper bb. */
4548 gcc_assert (BB_NOTE_LIST (new_bb
) == NULL_RTX
);
4549 BB_NOTE_LIST (new_bb
) = BB_NOTE_LIST (bb
);
4550 BB_NOTE_LIST (bb
) = NULL_RTX
;
4552 gcc_assert (e2
->dest
== bb
);
4554 /* Skip block for bookkeeping copy when leaving E1->src. */
4555 if (e1
->flags
& EDGE_FALLTHRU
)
4556 sel_redirect_edge_and_branch_force (e1
, new_bb
);
4558 sel_redirect_edge_and_branch (e1
, new_bb
);
4560 gcc_assert (e1
->dest
== new_bb
);
4561 gcc_assert (sel_bb_empty_p (bb
));
4563 /* To keep basic block numbers in sync between debug and non-debug
4564 compilations, we have to rotate blocks here. Consider that we
4565 started from (a,b)->d, (c,d)->e, and d contained only debug
4566 insns. It would have been removed before if the debug insns
4567 weren't there, so we'd have split e rather than d. So what we do
4568 now is to swap the block numbers of new_bb and
4569 single_succ(new_bb) == e, so that the insns that were in e before
4570 get the new block number. */
4572 if (MAY_HAVE_DEBUG_INSNS
)
4575 insn_t insn
= sel_bb_head (new_bb
);
4578 if (DEBUG_INSN_P (insn
)
4579 && single_succ_p (new_bb
)
4580 && (succ
= single_succ (new_bb
))
4581 && succ
!= EXIT_BLOCK_PTR
4582 && DEBUG_INSN_P ((last
= sel_bb_end (new_bb
))))
4584 while (insn
!= last
&& (DEBUG_INSN_P (insn
) || NOTE_P (insn
)))
4585 insn
= NEXT_INSN (insn
);
4589 sel_global_bb_info_def gbi
;
4590 sel_region_bb_info_def rbi
;
4593 if (sched_verbose
>= 2)
4594 sel_print ("Swapping block ids %i and %i\n",
4595 new_bb
->index
, succ
->index
);
4598 new_bb
->index
= succ
->index
;
4601 SET_BASIC_BLOCK (new_bb
->index
, new_bb
);
4602 SET_BASIC_BLOCK (succ
->index
, succ
);
4604 memcpy (&gbi
, SEL_GLOBAL_BB_INFO (new_bb
), sizeof (gbi
));
4605 memcpy (SEL_GLOBAL_BB_INFO (new_bb
), SEL_GLOBAL_BB_INFO (succ
),
4607 memcpy (SEL_GLOBAL_BB_INFO (succ
), &gbi
, sizeof (gbi
));
4609 memcpy (&rbi
, SEL_REGION_BB_INFO (new_bb
), sizeof (rbi
));
4610 memcpy (SEL_REGION_BB_INFO (new_bb
), SEL_REGION_BB_INFO (succ
),
4612 memcpy (SEL_REGION_BB_INFO (succ
), &rbi
, sizeof (rbi
));
4614 i
= BLOCK_TO_BB (new_bb
->index
);
4615 BLOCK_TO_BB (new_bb
->index
) = BLOCK_TO_BB (succ
->index
);
4616 BLOCK_TO_BB (succ
->index
) = i
;
4618 i
= CONTAINING_RGN (new_bb
->index
);
4619 CONTAINING_RGN (new_bb
->index
) = CONTAINING_RGN (succ
->index
);
4620 CONTAINING_RGN (succ
->index
) = i
;
4622 for (i
= 0; i
< current_nr_blocks
; i
++)
4623 if (BB_TO_BLOCK (i
) == succ
->index
)
4624 BB_TO_BLOCK (i
) = new_bb
->index
;
4625 else if (BB_TO_BLOCK (i
) == new_bb
->index
)
4626 BB_TO_BLOCK (i
) = succ
->index
;
4628 FOR_BB_INSNS (new_bb
, insn
)
4630 EXPR_ORIG_BB_INDEX (INSN_EXPR (insn
)) = new_bb
->index
;
4632 FOR_BB_INSNS (succ
, insn
)
4634 EXPR_ORIG_BB_INDEX (INSN_EXPR (insn
)) = succ
->index
;
4636 if (bitmap_bit_p (code_motion_visited_blocks
, new_bb
->index
))
4638 bitmap_set_bit (code_motion_visited_blocks
, succ
->index
);
4639 bitmap_clear_bit (code_motion_visited_blocks
, new_bb
->index
);
4642 gcc_assert (LABEL_P (BB_HEAD (new_bb
))
4643 && LABEL_P (BB_HEAD (succ
)));
4645 if (sched_verbose
>= 4)
4646 sel_print ("Swapping code labels %i and %i\n",
4647 CODE_LABEL_NUMBER (BB_HEAD (new_bb
)),
4648 CODE_LABEL_NUMBER (BB_HEAD (succ
)));
4650 i
= CODE_LABEL_NUMBER (BB_HEAD (new_bb
));
4651 CODE_LABEL_NUMBER (BB_HEAD (new_bb
))
4652 = CODE_LABEL_NUMBER (BB_HEAD (succ
));
4653 CODE_LABEL_NUMBER (BB_HEAD (succ
)) = i
;
4661 /* Return insn after which we must insert bookkeeping code for path(s) incoming
4662 into E2->dest, except from E1->src. */
4664 find_place_for_bookkeeping (edge e1
, edge e2
)
4666 insn_t place_to_insert
;
4667 /* Find a basic block that can hold bookkeeping. If it can be found, do not
4668 create new basic block, but insert bookkeeping there. */
4669 basic_block book_block
= find_block_for_bookkeeping (e1
, e2
, FALSE
);
4673 place_to_insert
= BB_END (book_block
);
4675 /* Don't use a block containing only debug insns for
4676 bookkeeping, this causes scheduling differences between debug
4677 and non-debug compilations, for the block would have been
4679 if (DEBUG_INSN_P (place_to_insert
))
4681 rtx insn
= sel_bb_head (book_block
);
4683 while (insn
!= place_to_insert
&&
4684 (DEBUG_INSN_P (insn
) || NOTE_P (insn
)))
4685 insn
= NEXT_INSN (insn
);
4687 if (insn
== place_to_insert
)
4694 book_block
= create_block_for_bookkeeping (e1
, e2
);
4695 place_to_insert
= BB_END (book_block
);
4696 if (sched_verbose
>= 9)
4697 sel_print ("New block is %i, split from bookkeeping block %i\n",
4698 EDGE_SUCC (book_block
, 0)->dest
->index
, book_block
->index
);
4702 if (sched_verbose
>= 9)
4703 sel_print ("Pre-existing bookkeeping block is %i\n", book_block
->index
);
4706 /* If basic block ends with a jump, insert bookkeeping code right before it. */
4707 if (INSN_P (place_to_insert
) && control_flow_insn_p (place_to_insert
))
4708 place_to_insert
= PREV_INSN (place_to_insert
);
4710 return place_to_insert
;
4713 /* Find a proper seqno for bookkeeing insn inserted at PLACE_TO_INSERT
4716 find_seqno_for_bookkeeping (insn_t place_to_insert
, insn_t join_point
)
4721 /* Check if we are about to insert bookkeeping copy before a jump, and use
4722 jump's seqno for the copy; otherwise, use JOIN_POINT's seqno. */
4723 next
= NEXT_INSN (place_to_insert
);
4726 && BLOCK_FOR_INSN (next
) == BLOCK_FOR_INSN (place_to_insert
))
4728 gcc_assert (INSN_SCHED_TIMES (next
) == 0);
4729 seqno
= INSN_SEQNO (next
);
4731 else if (INSN_SEQNO (join_point
) > 0)
4732 seqno
= INSN_SEQNO (join_point
);
4735 seqno
= get_seqno_by_preds (place_to_insert
);
4737 /* Sometimes the fences can move in such a way that there will be
4738 no instructions with positive seqno around this bookkeeping.
4739 This means that there will be no way to get to it by a regular
4740 fence movement. Never mind because we pick up such pieces for
4741 rescheduling anyways, so any positive value will do for now. */
4744 gcc_assert (pipelining_p
);
4749 gcc_assert (seqno
> 0);
4753 /* Insert bookkeeping copy of C_EXPS's insn after PLACE_TO_INSERT, assigning
4754 NEW_SEQNO to it. Return created insn. */
4756 emit_bookkeeping_insn (insn_t place_to_insert
, expr_t c_expr
, int new_seqno
)
4758 rtx new_insn_rtx
= create_copy_of_insn_rtx (EXPR_INSN_RTX (c_expr
));
4761 = create_vinsn_from_insn_rtx (new_insn_rtx
,
4762 VINSN_UNIQUE_P (EXPR_VINSN (c_expr
)));
4764 insn_t new_insn
= emit_insn_from_expr_after (c_expr
, new_vinsn
, new_seqno
,
4767 INSN_SCHED_TIMES (new_insn
) = 0;
4768 bitmap_set_bit (current_copies
, INSN_UID (new_insn
));
4773 /* Generate a bookkeeping copy of C_EXPR's insn for path(s) incoming into to
4774 E2->dest, except from E1->src (there may be a sequence of empty blocks
4775 between E1->src and E2->dest). Return block containing the copy.
4776 All scheduler data is initialized for the newly created insn. */
4778 generate_bookkeeping_insn (expr_t c_expr
, edge e1
, edge e2
)
4780 insn_t join_point
, place_to_insert
, new_insn
;
4782 bool need_to_exchange_data_sets
;
4784 if (sched_verbose
>= 4)
4785 sel_print ("Generating bookkeeping insn (%d->%d)\n", e1
->src
->index
,
4788 join_point
= sel_bb_head (e2
->dest
);
4789 place_to_insert
= find_place_for_bookkeeping (e1
, e2
);
4790 if (!place_to_insert
)
4792 new_seqno
= find_seqno_for_bookkeeping (place_to_insert
, join_point
);
4793 need_to_exchange_data_sets
4794 = sel_bb_empty_p (BLOCK_FOR_INSN (place_to_insert
));
4796 new_insn
= emit_bookkeeping_insn (place_to_insert
, c_expr
, new_seqno
);
4798 /* When inserting bookkeeping insn in new block, av sets should be
4799 following: old basic block (that now holds bookkeeping) data sets are
4800 the same as was before generation of bookkeeping, and new basic block
4801 (that now hold all other insns of old basic block) data sets are
4802 invalid. So exchange data sets for these basic blocks as sel_split_block
4803 mistakenly exchanges them in this case. Cannot do it earlier because
4804 when single instruction is added to new basic block it should hold NULL
4806 if (need_to_exchange_data_sets
)
4807 exchange_data_sets (BLOCK_FOR_INSN (new_insn
),
4808 BLOCK_FOR_INSN (join_point
));
4810 stat_bookkeeping_copies
++;
4811 return BLOCK_FOR_INSN (new_insn
);
4814 /* Remove from AV_PTR all insns that may need bookkeeping when scheduling
4815 on FENCE, but we are unable to copy them. */
4817 remove_insns_that_need_bookkeeping (fence_t fence
, av_set_t
*av_ptr
)
4822 /* An expression does not need bookkeeping if it is available on all paths
4823 from current block to original block and current block dominates
4824 original block. We check availability on all paths by examining
4825 EXPR_SPEC; this is not equivalent, because it may be positive even
4826 if expr is available on all paths (but if expr is not available on
4827 any path, EXPR_SPEC will be positive). */
4829 FOR_EACH_EXPR_1 (expr
, i
, av_ptr
)
4831 if (!control_flow_insn_p (EXPR_INSN_RTX (expr
))
4832 && (!bookkeeping_p
|| VINSN_UNIQUE_P (EXPR_VINSN (expr
)))
4833 && (EXPR_SPEC (expr
)
4834 || !EXPR_ORIG_BB_INDEX (expr
)
4835 || !dominated_by_p (CDI_DOMINATORS
,
4836 BASIC_BLOCK (EXPR_ORIG_BB_INDEX (expr
)),
4837 BLOCK_FOR_INSN (FENCE_INSN (fence
)))))
4839 if (sched_verbose
>= 4)
4840 sel_print ("Expr %d removed because it would need bookkeeping, which "
4841 "cannot be created\n", INSN_UID (EXPR_INSN_RTX (expr
)));
4842 av_set_iter_remove (&i
);
4847 /* Moving conditional jump through some instructions.
4851 ... <- current scheduling point
4852 NOTE BASIC BLOCK: <- bb header
4853 (p8) add r14=r14+0x9;;
4859 We can schedule jump one cycle earlier, than mov, because they cannot be
4860 executed together as their predicates are mutually exclusive.
4862 This is done in this way: first, new fallthrough basic block is created
4863 after jump (it is always can be done, because there already should be a
4864 fallthrough block, where control flow goes in case of predicate being true -
4865 in our example; otherwise there should be a dependence between those
4866 instructions and jump and we cannot schedule jump right now);
4867 next, all instructions between jump and current scheduling point are moved
4868 to this new block. And the result is this:
4871 (!p8) jump L1 <- current scheduling point
4872 NOTE BASIC BLOCK: <- bb header
4873 (p8) add r14=r14+0x9;;
4879 move_cond_jump (rtx insn
, bnd_t bnd
)
4882 basic_block block_from
, block_next
, block_new
;
4883 rtx next
, prev
, link
;
4885 /* BLOCK_FROM holds basic block of the jump. */
4886 block_from
= BLOCK_FOR_INSN (insn
);
4888 /* Moving of jump should not cross any other jumps or
4889 beginnings of new basic blocks. */
4890 gcc_assert (block_from
== BLOCK_FOR_INSN (BND_TO (bnd
)));
4892 /* Jump is moved to the boundary. */
4893 prev
= BND_TO (bnd
);
4894 next
= PREV_INSN (insn
);
4895 BND_TO (bnd
) = insn
;
4897 ft_edge
= find_fallthru_edge (block_from
);
4898 block_next
= ft_edge
->dest
;
4899 /* There must be a fallthrough block (or where should go
4900 control flow in case of false jump predicate otherwise?). */
4901 gcc_assert (block_next
);
4903 /* Create new empty basic block after source block. */
4904 block_new
= sel_split_edge (ft_edge
);
4905 gcc_assert (block_new
->next_bb
== block_next
4906 && block_from
->next_bb
== block_new
);
4908 gcc_assert (BB_END (block_from
) == insn
);
4910 /* Move all instructions except INSN from BLOCK_FROM to
4912 for (link
= prev
; link
!= insn
; link
= NEXT_INSN (link
))
4914 EXPR_ORIG_BB_INDEX (INSN_EXPR (link
)) = block_new
->index
;
4915 df_insn_change_bb (link
, block_new
);
4918 /* Set correct basic block and instructions properties. */
4919 BB_END (block_new
) = PREV_INSN (insn
);
4921 NEXT_INSN (PREV_INSN (prev
)) = insn
;
4922 PREV_INSN (insn
) = PREV_INSN (prev
);
4924 /* Assert there is no jump to BLOCK_NEW, only fallthrough edge. */
4925 gcc_assert (NOTE_INSN_BASIC_BLOCK_P (BB_HEAD (block_new
)));
4926 PREV_INSN (prev
) = BB_HEAD (block_new
);
4927 NEXT_INSN (next
) = NEXT_INSN (BB_HEAD (block_new
));
4928 NEXT_INSN (BB_HEAD (block_new
)) = prev
;
4929 PREV_INSN (NEXT_INSN (next
)) = next
;
4931 gcc_assert (!sel_bb_empty_p (block_from
)
4932 && !sel_bb_empty_p (block_new
));
4934 /* Update data sets for BLOCK_NEW to represent that INSN and
4935 instructions from the other branch of INSN is no longer
4936 available at BLOCK_NEW. */
4937 BB_AV_LEVEL (block_new
) = global_level
;
4938 gcc_assert (BB_LV_SET (block_new
) == NULL
);
4939 BB_LV_SET (block_new
) = get_clear_regset_from_pool ();
4940 update_data_sets (sel_bb_head (block_new
));
4942 /* INSN is a new basic block header - so prepare its data
4943 structures and update availability and liveness sets. */
4944 update_data_sets (insn
);
4946 if (sched_verbose
>= 4)
4947 sel_print ("Moving jump %d\n", INSN_UID (insn
));
4950 /* Remove nops generated during move_op for preventing removal of empty
4953 remove_temp_moveop_nops (bool full_tidying
)
4958 for (i
= 0; VEC_iterate (insn_t
, vec_temp_moveop_nops
, i
, insn
); i
++)
4960 gcc_assert (INSN_NOP_P (insn
));
4961 return_nop_to_pool (insn
, full_tidying
);
4964 /* Empty the vector. */
4965 if (VEC_length (insn_t
, vec_temp_moveop_nops
) > 0)
4966 VEC_block_remove (insn_t
, vec_temp_moveop_nops
, 0,
4967 VEC_length (insn_t
, vec_temp_moveop_nops
));
4970 /* Records the maximal UID before moving up an instruction. Used for
4971 distinguishing between bookkeeping copies and original insns. */
4972 static int max_uid_before_move_op
= 0;
4974 /* Remove from AV_VLIW_P all instructions but next when debug counter
4975 tells us so. Next instruction is fetched from BNDS. */
4977 remove_insns_for_debug (blist_t bnds
, av_set_t
*av_vliw_p
)
4979 if (! dbg_cnt (sel_sched_insn_cnt
))
4980 /* Leave only the next insn in av_vliw. */
4982 av_set_iterator av_it
;
4984 bnd_t bnd
= BLIST_BND (bnds
);
4985 insn_t next
= BND_TO (bnd
);
4987 gcc_assert (BLIST_NEXT (bnds
) == NULL
);
4989 FOR_EACH_EXPR_1 (expr
, av_it
, av_vliw_p
)
4990 if (EXPR_INSN_RTX (expr
) != next
)
4991 av_set_iter_remove (&av_it
);
4995 /* Compute available instructions on BNDS. FENCE is the current fence. Write
4996 the computed set to *AV_VLIW_P. */
4998 compute_av_set_on_boundaries (fence_t fence
, blist_t bnds
, av_set_t
*av_vliw_p
)
5000 if (sched_verbose
>= 2)
5002 sel_print ("Boundaries: ");
5007 for (; bnds
; bnds
= BLIST_NEXT (bnds
))
5009 bnd_t bnd
= BLIST_BND (bnds
);
5011 insn_t bnd_to
= BND_TO (bnd
);
5013 /* Rewind BND->TO to the basic block header in case some bookkeeping
5014 instructions were inserted before BND->TO and it needs to be
5016 if (sel_bb_head_p (bnd_to
))
5017 gcc_assert (INSN_SCHED_TIMES (bnd_to
) == 0);
5019 while (INSN_SCHED_TIMES (PREV_INSN (bnd_to
)) == 0)
5021 bnd_to
= PREV_INSN (bnd_to
);
5022 if (sel_bb_head_p (bnd_to
))
5026 if (BND_TO (bnd
) != bnd_to
)
5028 gcc_assert (FENCE_INSN (fence
) == BND_TO (bnd
));
5029 FENCE_INSN (fence
) = bnd_to
;
5030 BND_TO (bnd
) = bnd_to
;
5033 av_set_clear (&BND_AV (bnd
));
5034 BND_AV (bnd
) = compute_av_set (BND_TO (bnd
), NULL
, 0, true);
5036 av_set_clear (&BND_AV1 (bnd
));
5037 BND_AV1 (bnd
) = av_set_copy (BND_AV (bnd
));
5039 moveup_set_inside_insn_group (&BND_AV1 (bnd
), NULL
);
5041 av1_copy
= av_set_copy (BND_AV1 (bnd
));
5042 av_set_union_and_clear (av_vliw_p
, &av1_copy
, NULL
);
5045 if (sched_verbose
>= 2)
5047 sel_print ("Available exprs (vliw form): ");
5048 dump_av_set (*av_vliw_p
);
5053 /* Calculate the sequential av set on BND corresponding to the EXPR_VLIW
5054 expression. When FOR_MOVEOP is true, also replace the register of
5055 expressions found with the register from EXPR_VLIW. */
5057 find_sequential_best_exprs (bnd_t bnd
, expr_t expr_vliw
, bool for_moveop
)
5059 av_set_t expr_seq
= NULL
;
5063 FOR_EACH_EXPR (expr
, i
, BND_AV (bnd
))
5065 if (equal_after_moveup_path_p (expr
, NULL
, expr_vliw
))
5069 /* The sequential expression has the right form to pass
5070 to move_op except when renaming happened. Put the
5071 correct register in EXPR then. */
5072 if (EXPR_SEPARABLE_P (expr
) && REG_P (EXPR_LHS (expr
)))
5074 if (expr_dest_regno (expr
) != expr_dest_regno (expr_vliw
))
5076 replace_dest_with_reg_in_expr (expr
, EXPR_LHS (expr_vliw
));
5077 stat_renamed_scheduled
++;
5079 /* Also put the correct TARGET_AVAILABLE bit on the expr.
5080 This is needed when renaming came up with original
5082 else if (EXPR_TARGET_AVAILABLE (expr
)
5083 != EXPR_TARGET_AVAILABLE (expr_vliw
))
5085 gcc_assert (EXPR_TARGET_AVAILABLE (expr_vliw
) == 1);
5086 EXPR_TARGET_AVAILABLE (expr
) = 1;
5089 if (EXPR_WAS_SUBSTITUTED (expr
))
5090 stat_substitutions_total
++;
5093 av_set_add (&expr_seq
, expr
);
5095 /* With substitution inside insn group, it is possible
5096 that more than one expression in expr_seq will correspond
5097 to expr_vliw. In this case, choose one as the attempt to
5098 move both leads to miscompiles. */
5103 if (for_moveop
&& sched_verbose
>= 2)
5105 sel_print ("Best expression(s) (sequential form): ");
5106 dump_av_set (expr_seq
);
5114 /* Move nop to previous block. */
5115 static void ATTRIBUTE_UNUSED
5116 move_nop_to_previous_block (insn_t nop
, basic_block prev_bb
)
5118 insn_t prev_insn
, next_insn
, note
;
5120 gcc_assert (sel_bb_head_p (nop
)
5121 && prev_bb
== BLOCK_FOR_INSN (nop
)->prev_bb
);
5122 note
= bb_note (BLOCK_FOR_INSN (nop
));
5123 prev_insn
= sel_bb_end (prev_bb
);
5124 next_insn
= NEXT_INSN (nop
);
5125 gcc_assert (prev_insn
!= NULL_RTX
5126 && PREV_INSN (note
) == prev_insn
);
5128 NEXT_INSN (prev_insn
) = nop
;
5129 PREV_INSN (nop
) = prev_insn
;
5131 PREV_INSN (note
) = nop
;
5132 NEXT_INSN (note
) = next_insn
;
5134 NEXT_INSN (nop
) = note
;
5135 PREV_INSN (next_insn
) = note
;
5137 BB_END (prev_bb
) = nop
;
5138 BLOCK_FOR_INSN (nop
) = prev_bb
;
5141 /* Prepare a place to insert the chosen expression on BND. */
5143 prepare_place_to_insert (bnd_t bnd
)
5145 insn_t place_to_insert
;
5147 /* Init place_to_insert before calling move_op, as the later
5148 can possibly remove BND_TO (bnd). */
5149 if (/* If this is not the first insn scheduled. */
5152 /* Add it after last scheduled. */
5153 place_to_insert
= ILIST_INSN (BND_PTR (bnd
));
5154 if (DEBUG_INSN_P (place_to_insert
))
5156 ilist_t l
= BND_PTR (bnd
);
5157 while ((l
= ILIST_NEXT (l
)) &&
5158 DEBUG_INSN_P (ILIST_INSN (l
)))
5161 place_to_insert
= NULL
;
5165 place_to_insert
= NULL
;
5167 if (!place_to_insert
)
5169 /* Add it before BND_TO. The difference is in the
5170 basic block, where INSN will be added. */
5171 place_to_insert
= get_nop_from_pool (BND_TO (bnd
));
5172 gcc_assert (BLOCK_FOR_INSN (place_to_insert
)
5173 == BLOCK_FOR_INSN (BND_TO (bnd
)));
5176 return place_to_insert
;
5179 /* Find original instructions for EXPR_SEQ and move it to BND boundary.
5180 Return the expression to emit in C_EXPR. */
5182 move_exprs_to_boundary (bnd_t bnd
, expr_t expr_vliw
,
5183 av_set_t expr_seq
, expr_t c_expr
)
5185 bool b
, should_move
;
5188 int n_bookkeeping_copies_before_moveop
;
5190 /* Make a move. This call will remove the original operation,
5191 insert all necessary bookkeeping instructions and update the
5192 data sets. After that all we have to do is add the operation
5193 at before BND_TO (BND). */
5194 n_bookkeeping_copies_before_moveop
= stat_bookkeeping_copies
;
5195 max_uid_before_move_op
= get_max_uid ();
5196 bitmap_clear (current_copies
);
5197 bitmap_clear (current_originators
);
5199 b
= move_op (BND_TO (bnd
), expr_seq
, expr_vliw
,
5200 get_dest_from_orig_ops (expr_seq
), c_expr
, &should_move
);
5202 /* We should be able to find the expression we've chosen for
5206 if (stat_bookkeeping_copies
> n_bookkeeping_copies_before_moveop
)
5207 stat_insns_needed_bookkeeping
++;
5209 EXECUTE_IF_SET_IN_BITMAP (current_copies
, 0, book_uid
, bi
)
5214 /* We allocate these bitmaps lazily. */
5215 if (! INSN_ORIGINATORS_BY_UID (book_uid
))
5216 INSN_ORIGINATORS_BY_UID (book_uid
) = BITMAP_ALLOC (NULL
);
5218 bitmap_copy (INSN_ORIGINATORS_BY_UID (book_uid
),
5219 current_originators
);
5221 /* Transitively add all originators' originators. */
5222 EXECUTE_IF_SET_IN_BITMAP (current_originators
, 0, uid
, bi
)
5223 if (INSN_ORIGINATORS_BY_UID (uid
))
5224 bitmap_ior_into (INSN_ORIGINATORS_BY_UID (book_uid
),
5225 INSN_ORIGINATORS_BY_UID (uid
));
5232 /* Debug a DFA state as an array of bytes. */
5234 debug_state (state_t state
)
5237 unsigned int i
, size
= dfa_state_size
;
5239 sel_print ("state (%u):", size
);
5240 for (i
= 0, p
= (unsigned char *) state
; i
< size
; i
++)
5241 sel_print (" %d", p
[i
]);
5245 /* Advance state on FENCE with INSN. Return true if INSN is
5246 an ASM, and we should advance state once more. */
5248 advance_state_on_fence (fence_t fence
, insn_t insn
)
5252 if (recog_memoized (insn
) >= 0)
5255 state_t temp_state
= alloca (dfa_state_size
);
5257 gcc_assert (!INSN_ASM_P (insn
));
5260 memcpy (temp_state
, FENCE_STATE (fence
), dfa_state_size
);
5261 res
= state_transition (FENCE_STATE (fence
), insn
);
5262 gcc_assert (res
< 0);
5264 if (memcmp (temp_state
, FENCE_STATE (fence
), dfa_state_size
))
5266 FENCE_ISSUED_INSNS (fence
)++;
5268 /* We should never issue more than issue_rate insns. */
5269 if (FENCE_ISSUED_INSNS (fence
) > issue_rate
)
5275 /* This could be an ASM insn which we'd like to schedule
5276 on the next cycle. */
5277 asm_p
= INSN_ASM_P (insn
);
5278 if (!FENCE_STARTS_CYCLE_P (fence
) && asm_p
)
5279 advance_one_cycle (fence
);
5282 if (sched_verbose
>= 2)
5283 debug_state (FENCE_STATE (fence
));
5284 if (!DEBUG_INSN_P (insn
))
5285 FENCE_STARTS_CYCLE_P (fence
) = 0;
5286 FENCE_ISSUE_MORE (fence
) = can_issue_more
;
5290 /* Update FENCE on which INSN was scheduled and this INSN, too. NEED_STALL
5291 is nonzero if we need to stall after issuing INSN. */
5293 update_fence_and_insn (fence_t fence
, insn_t insn
, int need_stall
)
5297 /* First, reflect that something is scheduled on this fence. */
5298 asm_p
= advance_state_on_fence (fence
, insn
);
5299 FENCE_LAST_SCHEDULED_INSN (fence
) = insn
;
5300 VEC_safe_push (rtx
, gc
, FENCE_EXECUTING_INSNS (fence
), insn
);
5301 if (SCHED_GROUP_P (insn
))
5303 FENCE_SCHED_NEXT (fence
) = INSN_SCHED_NEXT (insn
);
5304 SCHED_GROUP_P (insn
) = 0;
5307 FENCE_SCHED_NEXT (fence
) = NULL_RTX
;
5308 if (INSN_UID (insn
) < FENCE_READY_TICKS_SIZE (fence
))
5309 FENCE_READY_TICKS (fence
) [INSN_UID (insn
)] = 0;
5311 /* Set instruction scheduling info. This will be used in bundling,
5312 pipelining, tick computations etc. */
5313 ++INSN_SCHED_TIMES (insn
);
5314 EXPR_TARGET_AVAILABLE (INSN_EXPR (insn
)) = true;
5315 EXPR_ORIG_SCHED_CYCLE (INSN_EXPR (insn
)) = FENCE_CYCLE (fence
);
5316 INSN_AFTER_STALL_P (insn
) = FENCE_AFTER_STALL_P (fence
);
5317 INSN_SCHED_CYCLE (insn
) = FENCE_CYCLE (fence
);
5319 /* This does not account for adjust_cost hooks, just add the biggest
5320 constant the hook may add to the latency. TODO: make this
5321 a target dependent constant. */
5322 INSN_READY_CYCLE (insn
)
5323 = INSN_SCHED_CYCLE (insn
) + (INSN_CODE (insn
) < 0
5325 : maximal_insn_latency (insn
) + 1);
5327 /* Change these fields last, as they're used above. */
5328 FENCE_AFTER_STALL_P (fence
) = 0;
5329 if (asm_p
|| need_stall
)
5330 advance_one_cycle (fence
);
5332 /* Indicate that we've scheduled something on this fence. */
5333 FENCE_SCHEDULED_P (fence
) = true;
5334 scheduled_something_on_previous_fence
= true;
5336 /* Print debug information when insn's fields are updated. */
5337 if (sched_verbose
>= 2)
5339 sel_print ("Scheduling insn: ");
5340 dump_insn_1 (insn
, 1);
5345 /* Update boundary BND (and, if needed, FENCE) with INSN, remove the
5346 old boundary from BNDSP, add new boundaries to BNDS_TAIL_P and
5349 update_boundaries (fence_t fence
, bnd_t bnd
, insn_t insn
, blist_t
*bndsp
,
5350 blist_t
*bnds_tailp
)
5355 advance_deps_context (BND_DC (bnd
), insn
);
5356 FOR_EACH_SUCC_1 (succ
, si
, insn
,
5357 SUCCS_NORMAL
| SUCCS_SKIP_TO_LOOP_EXITS
)
5359 ilist_t ptr
= ilist_copy (BND_PTR (bnd
));
5361 ilist_add (&ptr
, insn
);
5363 if (DEBUG_INSN_P (insn
) && sel_bb_end_p (insn
)
5364 && is_ineligible_successor (succ
, ptr
))
5370 if (FENCE_INSN (fence
) == insn
&& !sel_bb_end_p (insn
))
5372 if (sched_verbose
>= 9)
5373 sel_print ("Updating fence insn from %i to %i\n",
5374 INSN_UID (insn
), INSN_UID (succ
));
5375 FENCE_INSN (fence
) = succ
;
5377 blist_add (bnds_tailp
, succ
, ptr
, BND_DC (bnd
));
5378 bnds_tailp
= &BLIST_NEXT (*bnds_tailp
);
5381 blist_remove (bndsp
);
5385 /* Schedule EXPR_VLIW on BND. Return the insn emitted. */
5387 schedule_expr_on_boundary (bnd_t bnd
, expr_t expr_vliw
, int seqno
)
5390 expr_t c_expr
= XALLOCA (expr_def
);
5391 insn_t place_to_insert
;
5395 expr_seq
= find_sequential_best_exprs (bnd
, expr_vliw
, true);
5397 /* In case of scheduling a jump skipping some other instructions,
5398 prepare CFG. After this, jump is at the boundary and can be
5399 scheduled as usual insn by MOVE_OP. */
5400 if (vinsn_cond_branch_p (EXPR_VINSN (expr_vliw
)))
5402 insn
= EXPR_INSN_RTX (expr_vliw
);
5404 /* Speculative jumps are not handled. */
5405 if (insn
!= BND_TO (bnd
)
5406 && !sel_insn_is_speculation_check (insn
))
5407 move_cond_jump (insn
, bnd
);
5410 /* Find a place for C_EXPR to schedule. */
5411 place_to_insert
= prepare_place_to_insert (bnd
);
5412 should_move
= move_exprs_to_boundary (bnd
, expr_vliw
, expr_seq
, c_expr
);
5413 clear_expr (c_expr
);
5415 /* Add the instruction. The corner case to care about is when
5416 the expr_seq set has more than one expr, and we chose the one that
5417 is not equal to expr_vliw. Then expr_vliw may be insn in stream, and
5418 we can't use it. Generate the new vinsn. */
5419 if (INSN_IN_STREAM_P (EXPR_INSN_RTX (expr_vliw
)))
5423 vinsn_new
= vinsn_copy (EXPR_VINSN (expr_vliw
), false);
5424 change_vinsn_in_expr (expr_vliw
, vinsn_new
);
5425 should_move
= false;
5428 insn
= sel_move_insn (expr_vliw
, seqno
, place_to_insert
);
5430 insn
= emit_insn_from_expr_after (expr_vliw
, NULL
, seqno
,
5433 /* Return the nops generated for preserving of data sets back
5435 if (INSN_NOP_P (place_to_insert
))
5436 return_nop_to_pool (place_to_insert
, !DEBUG_INSN_P (insn
));
5437 remove_temp_moveop_nops (!DEBUG_INSN_P (insn
));
5439 av_set_clear (&expr_seq
);
5441 /* Save the expression scheduled so to reset target availability if we'll
5442 meet it later on the same fence. */
5443 if (EXPR_WAS_RENAMED (expr_vliw
))
5444 vinsn_vec_add (&vec_target_unavailable_vinsns
, INSN_EXPR (insn
));
5446 /* Check that the recent movement didn't destroyed loop
5448 gcc_assert (!pipelining_p
5449 || current_loop_nest
== NULL
5450 || loop_latch_edge (current_loop_nest
));
5454 /* Stall for N cycles on FENCE. */
5456 stall_for_cycles (fence_t fence
, int n
)
5460 could_more
= n
> 1 || FENCE_ISSUED_INSNS (fence
) < issue_rate
;
5462 advance_one_cycle (fence
);
5464 FENCE_AFTER_STALL_P (fence
) = 1;
5467 /* Gather a parallel group of insns at FENCE and assign their seqno
5468 to SEQNO. All scheduled insns are gathered in SCHEDULED_INSNS_TAILPP
5469 list for later recalculation of seqnos. */
5471 fill_insns (fence_t fence
, int seqno
, ilist_t
**scheduled_insns_tailpp
)
5473 blist_t bnds
= NULL
, *bnds_tailp
;
5474 av_set_t av_vliw
= NULL
;
5475 insn_t insn
= FENCE_INSN (fence
);
5477 if (sched_verbose
>= 2)
5478 sel_print ("Starting fill_insns for insn %d, cycle %d\n",
5479 INSN_UID (insn
), FENCE_CYCLE (fence
));
5481 blist_add (&bnds
, insn
, NULL
, FENCE_DC (fence
));
5482 bnds_tailp
= &BLIST_NEXT (bnds
);
5483 set_target_context (FENCE_TC (fence
));
5484 can_issue_more
= FENCE_ISSUE_MORE (fence
);
5485 target_bb
= INSN_BB (insn
);
5487 /* Do while we can add any operation to the current group. */
5490 blist_t
*bnds_tailp1
, *bndsp
;
5493 int was_stall
= 0, scheduled_insns
= 0, stall_iterations
= 0;
5494 int max_insns
= pipelining_p
? issue_rate
: 2 * issue_rate
;
5495 int max_stall
= pipelining_p
? 1 : 3;
5496 bool last_insn_was_debug
= false;
5497 bool was_debug_bb_end_p
= false;
5499 compute_av_set_on_boundaries (fence
, bnds
, &av_vliw
);
5500 remove_insns_that_need_bookkeeping (fence
, &av_vliw
);
5501 remove_insns_for_debug (bnds
, &av_vliw
);
5503 /* Return early if we have nothing to schedule. */
5504 if (av_vliw
== NULL
)
5507 /* Choose the best expression and, if needed, destination register
5511 expr_vliw
= find_best_expr (&av_vliw
, bnds
, fence
, &need_stall
);
5512 if (!expr_vliw
&& need_stall
)
5514 /* All expressions required a stall. Do not recompute av sets
5515 as we'll get the same answer (modulo the insns between
5516 the fence and its boundary, which will not be available for
5518 gcc_assert (! expr_vliw
&& stall_iterations
< 2);
5520 /* If we are going to stall for too long, break to recompute av
5521 sets and bring more insns for pipelining. */
5522 if (need_stall
<= 3)
5523 stall_for_cycles (fence
, need_stall
);
5526 stall_for_cycles (fence
, 1);
5531 while (! expr_vliw
&& need_stall
);
5533 /* Now either we've selected expr_vliw or we have nothing to schedule. */
5536 av_set_clear (&av_vliw
);
5541 bnds_tailp1
= bnds_tailp
;
5544 /* This code will be executed only once until we'd have several
5545 boundaries per fence. */
5547 bnd_t bnd
= BLIST_BND (*bndsp
);
5549 if (!av_set_is_in_p (BND_AV1 (bnd
), EXPR_VINSN (expr_vliw
)))
5551 bndsp
= &BLIST_NEXT (*bndsp
);
5555 insn
= schedule_expr_on_boundary (bnd
, expr_vliw
, seqno
);
5556 last_insn_was_debug
= DEBUG_INSN_P (insn
);
5557 if (last_insn_was_debug
)
5558 was_debug_bb_end_p
= (insn
== BND_TO (bnd
) && sel_bb_end_p (insn
));
5559 update_fence_and_insn (fence
, insn
, need_stall
);
5560 bnds_tailp
= update_boundaries (fence
, bnd
, insn
, bndsp
, bnds_tailp
);
5562 /* Add insn to the list of scheduled on this cycle instructions. */
5563 ilist_add (*scheduled_insns_tailpp
, insn
);
5564 *scheduled_insns_tailpp
= &ILIST_NEXT (**scheduled_insns_tailpp
);
5566 while (*bndsp
!= *bnds_tailp1
);
5568 av_set_clear (&av_vliw
);
5569 if (!last_insn_was_debug
)
5572 /* We currently support information about candidate blocks only for
5573 one 'target_bb' block. Hence we can't schedule after jump insn,
5574 as this will bring two boundaries and, hence, necessity to handle
5575 information for two or more blocks concurrently. */
5576 if ((last_insn_was_debug
? was_debug_bb_end_p
: sel_bb_end_p (insn
))
5578 && (was_stall
>= max_stall
5579 || scheduled_insns
>= max_insns
)))
5584 gcc_assert (!FENCE_BNDS (fence
));
5586 /* Update boundaries of the FENCE. */
5589 ilist_t ptr
= BND_PTR (BLIST_BND (bnds
));
5593 insn
= ILIST_INSN (ptr
);
5595 if (!ilist_is_in_p (FENCE_BNDS (fence
), insn
))
5596 ilist_add (&FENCE_BNDS (fence
), insn
);
5599 blist_remove (&bnds
);
5602 /* Update target context on the fence. */
5603 reset_target_context (FENCE_TC (fence
), false);
5606 /* All exprs in ORIG_OPS must have the same destination register or memory.
5607 Return that destination. */
5609 get_dest_from_orig_ops (av_set_t orig_ops
)
5611 rtx dest
= NULL_RTX
;
5612 av_set_iterator av_it
;
5614 bool first_p
= true;
5616 FOR_EACH_EXPR (expr
, av_it
, orig_ops
)
5618 rtx x
= EXPR_LHS (expr
);
5626 gcc_assert (dest
== x
5627 || (dest
!= NULL_RTX
&& x
!= NULL_RTX
5628 && rtx_equal_p (dest
, x
)));
5634 /* Update data sets for the bookkeeping block and record those expressions
5635 which become no longer available after inserting this bookkeeping. */
5637 update_and_record_unavailable_insns (basic_block book_block
)
5640 av_set_t old_av_set
= NULL
;
5642 rtx bb_end
= sel_bb_end (book_block
);
5644 /* First, get correct liveness in the bookkeeping block. The problem is
5645 the range between the bookeeping insn and the end of block. */
5646 update_liveness_on_insn (bb_end
);
5647 if (control_flow_insn_p (bb_end
))
5648 update_liveness_on_insn (PREV_INSN (bb_end
));
5650 /* If there's valid av_set on BOOK_BLOCK, then there might exist another
5651 fence above, where we may choose to schedule an insn which is
5652 actually blocked from moving up with the bookkeeping we create here. */
5653 if (AV_SET_VALID_P (sel_bb_head (book_block
)))
5655 old_av_set
= av_set_copy (BB_AV_SET (book_block
));
5656 update_data_sets (sel_bb_head (book_block
));
5658 /* Traverse all the expressions in the old av_set and check whether
5659 CUR_EXPR is in new AV_SET. */
5660 FOR_EACH_EXPR (cur_expr
, i
, old_av_set
)
5662 expr_t new_expr
= av_set_lookup (BB_AV_SET (book_block
),
5663 EXPR_VINSN (cur_expr
));
5666 /* In this case, we can just turn off the E_T_A bit, but we can't
5667 represent this information with the current vector. */
5668 || EXPR_TARGET_AVAILABLE (new_expr
)
5669 != EXPR_TARGET_AVAILABLE (cur_expr
))
5670 /* Unfortunately, the below code could be also fired up on
5672 FIXME: add an example of how this could happen. */
5673 vinsn_vec_add (&vec_bookkeeping_blocked_vinsns
, cur_expr
);
5676 av_set_clear (&old_av_set
);
5680 /* The main effect of this function is that sparams->c_expr is merged
5681 with (or copied to) lparams->c_expr_merged. If there's only one successor,
5682 we avoid merging anything by copying sparams->c_expr to lparams->c_expr_merged.
5683 lparams->c_expr_merged is copied back to sparams->c_expr after all
5684 successors has been traversed. lparams->c_expr_local is an expr allocated
5685 on stack in the caller function, and is used if there is more than one
5688 SUCC is one of the SUCCS_NORMAL successors of INSN,
5689 MOVEOP_DRV_CALL_RES is the result of call code_motion_path_driver on succ,
5690 LPARAMS and STATIC_PARAMS contain the parameters described above. */
5692 move_op_merge_succs (insn_t insn ATTRIBUTE_UNUSED
,
5693 insn_t succ ATTRIBUTE_UNUSED
,
5694 int moveop_drv_call_res
,
5695 cmpd_local_params_p lparams
, void *static_params
)
5697 moveop_static_params_p sparams
= (moveop_static_params_p
) static_params
;
5699 /* Nothing to do, if original expr wasn't found below. */
5700 if (moveop_drv_call_res
!= 1)
5703 /* If this is a first successor. */
5704 if (!lparams
->c_expr_merged
)
5706 lparams
->c_expr_merged
= sparams
->c_expr
;
5707 sparams
->c_expr
= lparams
->c_expr_local
;
5711 /* We must merge all found expressions to get reasonable
5712 EXPR_SPEC_DONE_DS for the resulting insn. If we don't
5713 do so then we can first find the expr with epsilon
5714 speculation success probability and only then with the
5715 good probability. As a result the insn will get epsilon
5716 probability and will never be scheduled because of
5717 weakness_cutoff in find_best_expr.
5719 We call merge_expr_data here instead of merge_expr
5720 because due to speculation C_EXPR and X may have the
5721 same insns with different speculation types. And as of
5722 now such insns are considered non-equal.
5724 However, EXPR_SCHED_TIMES is different -- we must get
5725 SCHED_TIMES from a real insn, not a bookkeeping copy.
5726 We force this here. Instead, we may consider merging
5727 SCHED_TIMES to the maximum instead of minimum in the
5729 int old_times
= EXPR_SCHED_TIMES (lparams
->c_expr_merged
);
5731 merge_expr_data (lparams
->c_expr_merged
, sparams
->c_expr
, NULL
);
5732 if (EXPR_SCHED_TIMES (sparams
->c_expr
) == 0)
5733 EXPR_SCHED_TIMES (lparams
->c_expr_merged
) = old_times
;
5735 clear_expr (sparams
->c_expr
);
5739 /* Add used regs for the successor SUCC into SPARAMS->USED_REGS.
5741 SUCC is one of the SUCCS_NORMAL successors of INSN,
5742 MOVEOP_DRV_CALL_RES is the result of call code_motion_path_driver on succ or 0,
5743 if SUCC is one of SUCCS_BACK or SUCCS_OUT.
5744 STATIC_PARAMS contain USED_REGS set. */
5746 fur_merge_succs (insn_t insn ATTRIBUTE_UNUSED
, insn_t succ
,
5747 int moveop_drv_call_res
,
5748 cmpd_local_params_p lparams ATTRIBUTE_UNUSED
,
5749 void *static_params
)
5752 fur_static_params_p sparams
= (fur_static_params_p
) static_params
;
5754 /* Here we compute live regsets only for branches that do not lie
5755 on the code motion paths. These branches correspond to value
5756 MOVEOP_DRV_CALL_RES==0 and include SUCCS_BACK and SUCCS_OUT, though
5757 for such branches code_motion_path_driver is not called. */
5758 if (moveop_drv_call_res
!= 0)
5761 /* Mark all registers that do not meet the following condition:
5762 (3) not live on the other path of any conditional branch
5763 that is passed by the operation, in case original
5764 operations are not present on both paths of the
5765 conditional branch. */
5766 succ_live
= compute_live (succ
);
5767 IOR_REG_SET (sparams
->used_regs
, succ_live
);
5770 /* This function is called after the last successor. Copies LP->C_EXPR_MERGED
5773 move_op_after_merge_succs (cmpd_local_params_p lp
, void *sparams
)
5775 moveop_static_params_p sp
= (moveop_static_params_p
) sparams
;
5777 sp
->c_expr
= lp
->c_expr_merged
;
5780 /* Track bookkeeping copies created, insns scheduled, and blocks for
5781 rescheduling when INSN is found by move_op. */
5783 track_scheduled_insns_and_blocks (rtx insn
)
5785 /* Even if this insn can be a copy that will be removed during current move_op,
5786 we still need to count it as an originator. */
5787 bitmap_set_bit (current_originators
, INSN_UID (insn
));
5789 if (!bitmap_bit_p (current_copies
, INSN_UID (insn
)))
5791 /* Note that original block needs to be rescheduled, as we pulled an
5792 instruction out of it. */
5793 if (INSN_SCHED_TIMES (insn
) > 0)
5794 bitmap_set_bit (blocks_to_reschedule
, BLOCK_FOR_INSN (insn
)->index
);
5795 else if (INSN_UID (insn
) < first_emitted_uid
&& !DEBUG_INSN_P (insn
))
5796 num_insns_scheduled
++;
5799 bitmap_clear_bit (current_copies
, INSN_UID (insn
));
5801 /* For instructions we must immediately remove insn from the
5802 stream, so subsequent update_data_sets () won't include this
5804 For expr we must make insn look like "INSN_REG (insn) := c_expr". */
5805 if (INSN_UID (insn
) > max_uid_before_move_op
)
5806 stat_bookkeeping_copies
--;
5809 /* Emit a register-register copy for INSN if needed. Return true if
5810 emitted one. PARAMS is the move_op static parameters. */
5812 maybe_emit_renaming_copy (rtx insn
,
5813 moveop_static_params_p params
)
5815 bool insn_emitted
= false;
5818 /* Bail out early when expression can not be renamed at all. */
5819 if (!EXPR_SEPARABLE_P (params
->c_expr
))
5822 cur_reg
= expr_dest_reg (params
->c_expr
);
5823 gcc_assert (cur_reg
&& params
->dest
&& REG_P (params
->dest
));
5825 /* If original operation has expr and the register chosen for
5826 that expr is not original operation's dest reg, substitute
5827 operation's right hand side with the register chosen. */
5828 if (REGNO (params
->dest
) != REGNO (cur_reg
))
5830 insn_t reg_move_insn
, reg_move_insn_rtx
;
5832 reg_move_insn_rtx
= create_insn_rtx_with_rhs (INSN_VINSN (insn
),
5834 reg_move_insn
= sel_gen_insn_from_rtx_after (reg_move_insn_rtx
,
5838 EXPR_SPEC_DONE_DS (INSN_EXPR (reg_move_insn
)) = 0;
5839 replace_dest_with_reg_in_expr (params
->c_expr
, params
->dest
);
5841 insn_emitted
= true;
5842 params
->was_renamed
= true;
5845 return insn_emitted
;
5848 /* Emit a speculative check for INSN speculated as EXPR if needed.
5849 Return true if we've emitted one. PARAMS is the move_op static
5852 maybe_emit_speculative_check (rtx insn
, expr_t expr
,
5853 moveop_static_params_p params
)
5855 bool insn_emitted
= false;
5859 check_ds
= get_spec_check_type_for_insn (insn
, expr
);
5862 /* A speculation check should be inserted. */
5863 x
= create_speculation_check (params
->c_expr
, check_ds
, insn
);
5864 insn_emitted
= true;
5868 EXPR_SPEC_DONE_DS (INSN_EXPR (insn
)) = 0;
5872 gcc_assert (EXPR_SPEC_DONE_DS (INSN_EXPR (x
)) == 0
5873 && EXPR_SPEC_TO_CHECK_DS (INSN_EXPR (x
)) == 0);
5874 return insn_emitted
;
5877 /* Handle transformations that leave an insn in place of original
5878 insn such as renaming/speculation. Return true if one of such
5879 transformations actually happened, and we have emitted this insn. */
5881 handle_emitting_transformations (rtx insn
, expr_t expr
,
5882 moveop_static_params_p params
)
5884 bool insn_emitted
= false;
5886 insn_emitted
= maybe_emit_renaming_copy (insn
, params
);
5887 insn_emitted
|= maybe_emit_speculative_check (insn
, expr
, params
);
5889 return insn_emitted
;
5892 /* If INSN is the only insn in the basic block (not counting JUMP,
5893 which may be a jump to next insn, and DEBUG_INSNs), we want to
5894 leave a NOP there till the return to fill_insns. */
5897 need_nop_to_preserve_insn_bb (rtx insn
)
5899 insn_t bb_head
, bb_end
, bb_next
, in_next
;
5900 basic_block bb
= BLOCK_FOR_INSN (insn
);
5902 bb_head
= sel_bb_head (bb
);
5903 bb_end
= sel_bb_end (bb
);
5905 if (bb_head
== bb_end
)
5908 while (bb_head
!= bb_end
&& DEBUG_INSN_P (bb_head
))
5909 bb_head
= NEXT_INSN (bb_head
);
5911 if (bb_head
== bb_end
)
5914 while (bb_head
!= bb_end
&& DEBUG_INSN_P (bb_end
))
5915 bb_end
= PREV_INSN (bb_end
);
5917 if (bb_head
== bb_end
)
5920 bb_next
= NEXT_INSN (bb_head
);
5921 while (bb_next
!= bb_end
&& DEBUG_INSN_P (bb_next
))
5922 bb_next
= NEXT_INSN (bb_next
);
5924 if (bb_next
== bb_end
&& JUMP_P (bb_end
))
5927 in_next
= NEXT_INSN (insn
);
5928 while (DEBUG_INSN_P (in_next
))
5929 in_next
= NEXT_INSN (in_next
);
5931 if (IN_CURRENT_FENCE_P (in_next
))
5937 /* Remove INSN from stream. When ONLY_DISCONNECT is true, its data
5938 is not removed but reused when INSN is re-emitted. */
5940 remove_insn_from_stream (rtx insn
, bool only_disconnect
)
5942 /* If there's only one insn in the BB, make sure that a nop is
5943 inserted into it, so the basic block won't disappear when we'll
5944 delete INSN below with sel_remove_insn. It should also survive
5945 till the return to fill_insns. */
5946 if (need_nop_to_preserve_insn_bb (insn
))
5948 insn_t nop
= get_nop_from_pool (insn
);
5949 gcc_assert (INSN_NOP_P (nop
));
5950 VEC_safe_push (insn_t
, heap
, vec_temp_moveop_nops
, nop
);
5953 sel_remove_insn (insn
, only_disconnect
, false);
5956 /* This function is called when original expr is found.
5957 INSN - current insn traversed, EXPR - the corresponding expr found.
5958 LPARAMS is the local parameters of code modion driver, STATIC_PARAMS
5959 is static parameters of move_op. */
5961 move_op_orig_expr_found (insn_t insn
, expr_t expr
,
5962 cmpd_local_params_p lparams ATTRIBUTE_UNUSED
,
5963 void *static_params
)
5965 bool only_disconnect
, insn_emitted
;
5966 moveop_static_params_p params
= (moveop_static_params_p
) static_params
;
5968 copy_expr_onside (params
->c_expr
, INSN_EXPR (insn
));
5969 track_scheduled_insns_and_blocks (insn
);
5970 insn_emitted
= handle_emitting_transformations (insn
, expr
, params
);
5971 only_disconnect
= (params
->uid
== INSN_UID (insn
)
5972 && ! insn_emitted
&& ! EXPR_WAS_CHANGED (expr
));
5974 /* Mark that we've disconnected an insn. */
5975 if (only_disconnect
)
5977 remove_insn_from_stream (insn
, only_disconnect
);
5980 /* The function is called when original expr is found.
5981 INSN - current insn traversed, EXPR - the corresponding expr found,
5982 crosses_call and original_insns in STATIC_PARAMS are updated. */
5984 fur_orig_expr_found (insn_t insn
, expr_t expr ATTRIBUTE_UNUSED
,
5985 cmpd_local_params_p lparams ATTRIBUTE_UNUSED
,
5986 void *static_params
)
5988 fur_static_params_p params
= (fur_static_params_p
) static_params
;
5992 params
->crosses_call
= true;
5994 def_list_add (params
->original_insns
, insn
, params
->crosses_call
);
5996 /* Mark the registers that do not meet the following condition:
5997 (2) not among the live registers of the point
5998 immediately following the first original operation on
5999 a given downward path, except for the original target
6000 register of the operation. */
6001 tmp
= get_clear_regset_from_pool ();
6002 compute_live_below_insn (insn
, tmp
);
6003 AND_COMPL_REG_SET (tmp
, INSN_REG_SETS (insn
));
6004 AND_COMPL_REG_SET (tmp
, INSN_REG_CLOBBERS (insn
));
6005 IOR_REG_SET (params
->used_regs
, tmp
);
6006 return_regset_to_pool (tmp
);
6008 /* (*1) We need to add to USED_REGS registers that are read by
6009 INSN's lhs. This may lead to choosing wrong src register.
6010 E.g. (scheduling const expr enabled):
6012 429: ax=0x0 <- Can't use AX for this expr (0x0)
6019 /* FIXME: see comment above and enable MEM_P
6020 in vinsn_separable_p. */
6021 gcc_assert (!VINSN_SEPARABLE_P (INSN_VINSN (insn
))
6022 || !MEM_P (INSN_LHS (insn
)));
6025 /* This function is called on the ascending pass, before returning from
6026 current basic block. */
6028 move_op_at_first_insn (insn_t insn
, cmpd_local_params_p lparams
,
6029 void *static_params
)
6031 moveop_static_params_p sparams
= (moveop_static_params_p
) static_params
;
6032 basic_block book_block
= NULL
;
6034 /* When we have removed the boundary insn for scheduling, which also
6035 happened to be the end insn in its bb, we don't need to update sets. */
6036 if (!lparams
->removed_last_insn
6038 && sel_bb_head_p (insn
))
6040 /* We should generate bookkeeping code only if we are not at the
6041 top level of the move_op. */
6042 if (sel_num_cfg_preds_gt_1 (insn
))
6043 book_block
= generate_bookkeeping_insn (sparams
->c_expr
,
6044 lparams
->e1
, lparams
->e2
);
6045 /* Update data sets for the current insn. */
6046 update_data_sets (insn
);
6049 /* If bookkeeping code was inserted, we need to update av sets of basic
6050 block that received bookkeeping. After generation of bookkeeping insn,
6051 bookkeeping block does not contain valid av set because we are not following
6052 the original algorithm in every detail with regards to e.g. renaming
6053 simple reg-reg copies. Consider example:
6055 bookkeeping block scheduling fence
6065 We try to schedule insn "r1 := r3" on the current
6066 scheduling fence. Also, note that av set of bookkeeping block
6067 contain both insns "r1 := r2" and "r1 := r3". When the insn has
6068 been scheduled, the CFG is as follows:
6071 bookkeeping block scheduling fence
6081 Here, insn "r1 := r3" was scheduled at the current scheduling point
6082 and bookkeeping code was generated at the bookeeping block. This
6083 way insn "r1 := r2" is no longer available as a whole instruction
6084 (but only as expr) ahead of insn "r1 := r3" in bookkeeping block.
6085 This situation is handled by calling update_data_sets.
6087 Since update_data_sets is called only on the bookkeeping block, and
6088 it also may have predecessors with av_sets, containing instructions that
6089 are no longer available, we save all such expressions that become
6090 unavailable during data sets update on the bookkeeping block in
6091 VEC_BOOKKEEPING_BLOCKED_VINSNS. Later we avoid selecting such
6092 expressions for scheduling. This allows us to avoid recomputation of
6093 av_sets outside the code motion path. */
6096 update_and_record_unavailable_insns (book_block
);
6098 /* If INSN was previously marked for deletion, it's time to do it. */
6099 if (lparams
->removed_last_insn
)
6100 insn
= PREV_INSN (insn
);
6102 /* Do not tidy control flow at the topmost moveop, as we can erroneously
6103 kill a block with a single nop in which the insn should be emitted. */
6105 tidy_control_flow (BLOCK_FOR_INSN (insn
), true);
6108 /* This function is called on the ascending pass, before returning from the
6109 current basic block. */
6111 fur_at_first_insn (insn_t insn
,
6112 cmpd_local_params_p lparams ATTRIBUTE_UNUSED
,
6113 void *static_params ATTRIBUTE_UNUSED
)
6115 gcc_assert (!sel_bb_head_p (insn
) || AV_SET_VALID_P (insn
)
6116 || AV_LEVEL (insn
) == -1);
6119 /* Called on the backward stage of recursion to call moveup_expr for insn
6120 and sparams->c_expr. */
6122 move_op_ascend (insn_t insn
, void *static_params
)
6124 enum MOVEUP_EXPR_CODE res
;
6125 moveop_static_params_p sparams
= (moveop_static_params_p
) static_params
;
6127 if (! INSN_NOP_P (insn
))
6129 res
= moveup_expr_cached (sparams
->c_expr
, insn
, false);
6130 gcc_assert (res
!= MOVEUP_EXPR_NULL
);
6133 /* Update liveness for this insn as it was invalidated. */
6134 update_liveness_on_insn (insn
);
6137 /* This function is called on enter to the basic block.
6138 Returns TRUE if this block already have been visited and
6139 code_motion_path_driver should return 1, FALSE otherwise. */
6141 fur_on_enter (insn_t insn ATTRIBUTE_UNUSED
, cmpd_local_params_p local_params
,
6142 void *static_params
, bool visited_p
)
6144 fur_static_params_p sparams
= (fur_static_params_p
) static_params
;
6148 /* If we have found something below this block, there should be at
6149 least one insn in ORIGINAL_INSNS. */
6150 gcc_assert (*sparams
->original_insns
);
6152 /* Adjust CROSSES_CALL, since we may have come to this block along
6154 DEF_LIST_DEF (*sparams
->original_insns
)->crosses_call
6155 |= sparams
->crosses_call
;
6158 local_params
->old_original_insns
= *sparams
->original_insns
;
6163 /* Same as above but for move_op. */
6165 move_op_on_enter (insn_t insn ATTRIBUTE_UNUSED
,
6166 cmpd_local_params_p local_params ATTRIBUTE_UNUSED
,
6167 void *static_params ATTRIBUTE_UNUSED
, bool visited_p
)
6174 /* This function is called while descending current basic block if current
6175 insn is not the original EXPR we're searching for.
6177 Return value: FALSE, if code_motion_path_driver should perform a local
6178 cleanup and return 0 itself;
6179 TRUE, if code_motion_path_driver should continue. */
6181 move_op_orig_expr_not_found (insn_t insn
, av_set_t orig_ops ATTRIBUTE_UNUSED
,
6182 void *static_params
)
6184 moveop_static_params_p sparams
= (moveop_static_params_p
) static_params
;
6186 #ifdef ENABLE_CHECKING
6187 sparams
->failed_insn
= insn
;
6190 /* If we're scheduling separate expr, in order to generate correct code
6191 we need to stop the search at bookkeeping code generated with the
6192 same destination register or memory. */
6193 if (lhs_of_insn_equals_to_dest_p (insn
, sparams
->dest
))
6198 /* This function is called while descending current basic block if current
6199 insn is not the original EXPR we're searching for.
6201 Return value: TRUE (code_motion_path_driver should continue). */
6203 fur_orig_expr_not_found (insn_t insn
, av_set_t orig_ops
, void *static_params
)
6207 av_set_iterator avi
;
6208 fur_static_params_p sparams
= (fur_static_params_p
) static_params
;
6211 sparams
->crosses_call
= true;
6212 else if (DEBUG_INSN_P (insn
))
6215 /* If current insn we are looking at cannot be executed together
6216 with original insn, then we can skip it safely.
6218 Example: ORIG_OPS = { (p6) r14 = sign_extend (r15); }
6219 INSN = (!p6) r14 = r14 + 1;
6221 Here we can schedule ORIG_OP with lhs = r14, though only
6222 looking at the set of used and set registers of INSN we must
6223 forbid it. So, add set/used in INSN registers to the
6224 untouchable set only if there is an insn in ORIG_OPS that can
6227 FOR_EACH_EXPR (r
, avi
, orig_ops
)
6228 if (!sched_insns_conditions_mutex_p (insn
, EXPR_INSN_RTX (r
)))
6234 /* Mark all registers that do not meet the following condition:
6235 (1) Not set or read on any path from xi to an instance of the
6236 original operation. */
6239 IOR_REG_SET (sparams
->used_regs
, INSN_REG_SETS (insn
));
6240 IOR_REG_SET (sparams
->used_regs
, INSN_REG_USES (insn
));
6241 IOR_REG_SET (sparams
->used_regs
, INSN_REG_CLOBBERS (insn
));
6247 /* Hooks and data to perform move_op operations with code_motion_path_driver. */
6248 struct code_motion_path_driver_info_def move_op_hooks
= {
6250 move_op_orig_expr_found
,
6251 move_op_orig_expr_not_found
,
6252 move_op_merge_succs
,
6253 move_op_after_merge_succs
,
6255 move_op_at_first_insn
,
6260 /* Hooks and data to perform find_used_regs operations
6261 with code_motion_path_driver. */
6262 struct code_motion_path_driver_info_def fur_hooks
= {
6264 fur_orig_expr_found
,
6265 fur_orig_expr_not_found
,
6267 NULL
, /* fur_after_merge_succs */
6268 NULL
, /* fur_ascend */
6274 /* Traverse all successors of INSN. For each successor that is SUCCS_NORMAL
6275 code_motion_path_driver is called recursively. Original operation
6276 was found at least on one path that is starting with one of INSN's
6277 successors (this fact is asserted). ORIG_OPS is expressions we're looking
6278 for, PATH is the path we've traversed, STATIC_PARAMS is the parameters
6279 of either move_op or find_used_regs depending on the caller.
6281 Return 0 if we haven't found expression, 1 if we found it, -1 if we don't
6282 know for sure at this point. */
6284 code_motion_process_successors (insn_t insn
, av_set_t orig_ops
,
6285 ilist_t path
, void *static_params
)
6288 succ_iterator succ_i
;
6294 struct cmpd_local_params lparams
;
6297 lparams
.c_expr_local
= &_x
;
6298 lparams
.c_expr_merged
= NULL
;
6300 /* We need to process only NORMAL succs for move_op, and collect live
6301 registers from ALL branches (including those leading out of the
6302 region) for find_used_regs.
6304 In move_op, there can be a case when insn's bb number has changed
6305 due to created bookkeeping. This happens very rare, as we need to
6306 move expression from the beginning to the end of the same block.
6307 Rescan successors in this case. */
6310 bb
= BLOCK_FOR_INSN (insn
);
6311 old_index
= bb
->index
;
6312 old_succs
= EDGE_COUNT (bb
->succs
);
6314 FOR_EACH_SUCC_1 (succ
, succ_i
, insn
, code_motion_path_driver_info
->succ_flags
)
6318 lparams
.e1
= succ_i
.e1
;
6319 lparams
.e2
= succ_i
.e2
;
6321 /* Go deep into recursion only for NORMAL edges (non-backedges within the
6323 if (succ_i
.current_flags
== SUCCS_NORMAL
)
6324 b
= code_motion_path_driver (succ
, orig_ops
, path
, &lparams
,
6329 /* Merge c_expres found or unify live register sets from different
6331 code_motion_path_driver_info
->merge_succs (insn
, succ
, b
, &lparams
,
6335 else if (b
== -1 && res
!= 1)
6338 /* We have simplified the control flow below this point. In this case,
6339 the iterator becomes invalid. We need to try again. */
6340 if (BLOCK_FOR_INSN (insn
)->index
!= old_index
6341 || EDGE_COUNT (bb
->succs
) != old_succs
)
6345 #ifdef ENABLE_CHECKING
6346 /* Here, RES==1 if original expr was found at least for one of the
6347 successors. After the loop, RES may happen to have zero value
6348 only if at some point the expr searched is present in av_set, but is
6349 not found below. In most cases, this situation is an error.
6350 The exception is when the original operation is blocked by
6351 bookkeeping generated for another fence or for another path in current
6353 gcc_assert (res
== 1
6355 && av_set_could_be_blocked_by_bookkeeping_p (orig_ops
,
6360 /* Merge data, clean up, etc. */
6361 if (res
!= -1 && code_motion_path_driver_info
->after_merge_succs
)
6362 code_motion_path_driver_info
->after_merge_succs (&lparams
, static_params
);
6368 /* Perform a cleanup when the driver is about to terminate. ORIG_OPS_P
6369 is the pointer to the av set with expressions we were looking for,
6370 PATH_P is the pointer to the traversed path. */
6372 code_motion_path_driver_cleanup (av_set_t
*orig_ops_p
, ilist_t
*path_p
)
6374 ilist_remove (path_p
);
6375 av_set_clear (orig_ops_p
);
6378 /* The driver function that implements move_op or find_used_regs
6379 functionality dependent whether code_motion_path_driver_INFO is set to
6380 &MOVE_OP_HOOKS or &FUR_HOOKS. This function implements the common parts
6381 of code (CFG traversal etc) that are shared among both functions. INSN
6382 is the insn we're starting the search from, ORIG_OPS are the expressions
6383 we're searching for, PATH is traversed path, LOCAL_PARAMS_IN are local
6384 parameters of the driver, and STATIC_PARAMS are static parameters of
6387 Returns whether original instructions were found. Note that top-level
6388 code_motion_path_driver always returns true. */
6390 code_motion_path_driver (insn_t insn
, av_set_t orig_ops
, ilist_t path
,
6391 cmpd_local_params_p local_params_in
,
6392 void *static_params
)
6395 basic_block bb
= BLOCK_FOR_INSN (insn
);
6396 insn_t first_insn
, bb_tail
, before_first
;
6397 bool removed_last_insn
= false;
6399 if (sched_verbose
>= 6)
6401 sel_print ("%s (", code_motion_path_driver_info
->routine_name
);
6404 dump_av_set (orig_ops
);
6408 gcc_assert (orig_ops
);
6410 /* If no original operations exist below this insn, return immediately. */
6411 if (is_ineligible_successor (insn
, path
))
6413 if (sched_verbose
>= 6)
6414 sel_print ("Insn %d is ineligible successor\n", INSN_UID (insn
));
6418 /* The block can have invalid av set, in which case it was created earlier
6419 during move_op. Return immediately. */
6420 if (sel_bb_head_p (insn
))
6422 if (! AV_SET_VALID_P (insn
))
6424 if (sched_verbose
>= 6)
6425 sel_print ("Returned from block %d as it had invalid av set\n",
6430 if (bitmap_bit_p (code_motion_visited_blocks
, bb
->index
))
6432 /* We have already found an original operation on this branch, do not
6433 go any further and just return TRUE here. If we don't stop here,
6434 function can have exponential behaviour even on the small code
6435 with many different paths (e.g. with data speculation and
6436 recovery blocks). */
6437 if (sched_verbose
>= 6)
6438 sel_print ("Block %d already visited in this traversal\n", bb
->index
);
6439 if (code_motion_path_driver_info
->on_enter
)
6440 return code_motion_path_driver_info
->on_enter (insn
,
6447 if (code_motion_path_driver_info
->on_enter
)
6448 code_motion_path_driver_info
->on_enter (insn
, local_params_in
,
6449 static_params
, false);
6450 orig_ops
= av_set_copy (orig_ops
);
6452 /* Filter the orig_ops set. */
6453 if (AV_SET_VALID_P (insn
))
6454 av_set_intersect (&orig_ops
, AV_SET (insn
));
6456 /* If no more original ops, return immediately. */
6459 if (sched_verbose
>= 6)
6460 sel_print ("No intersection with av set of block %d\n", bb
->index
);
6464 /* For non-speculative insns we have to leave only one form of the
6465 original operation, because if we don't, we may end up with
6466 different C_EXPRes and, consequently, with bookkeepings for different
6467 expression forms along the same code motion path. That may lead to
6468 generation of incorrect code. So for each code motion we stick to
6469 the single form of the instruction, except for speculative insns
6470 which we need to keep in different forms with all speculation
6472 av_set_leave_one_nonspec (&orig_ops
);
6474 /* It is not possible that all ORIG_OPS are filtered out. */
6475 gcc_assert (orig_ops
);
6477 /* It is enough to place only heads and tails of visited basic blocks into
6479 ilist_add (&path
, insn
);
6481 bb_tail
= sel_bb_end (bb
);
6483 /* Descend the basic block in search of the original expr; this part
6484 corresponds to the part of the original move_op procedure executed
6485 before the recursive call. */
6488 /* Look at the insn and decide if it could be an ancestor of currently
6489 scheduling operation. If it is so, then the insn "dest = op" could
6490 either be replaced with "dest = reg", because REG now holds the result
6491 of OP, or just removed, if we've scheduled the insn as a whole.
6493 If this insn doesn't contain currently scheduling OP, then proceed
6494 with searching and look at its successors. Operations we're searching
6495 for could have changed when moving up through this insn via
6496 substituting. In this case, perform unsubstitution on them first.
6498 When traversing the DAG below this insn is finished, insert
6499 bookkeeping code, if the insn is a joint point, and remove
6502 expr
= av_set_lookup (orig_ops
, INSN_VINSN (insn
));
6505 insn_t last_insn
= PREV_INSN (insn
);
6507 /* We have found the original operation. */
6508 if (sched_verbose
>= 6)
6509 sel_print ("Found original operation at insn %d\n", INSN_UID (insn
));
6511 code_motion_path_driver_info
->orig_expr_found
6512 (insn
, expr
, local_params_in
, static_params
);
6514 /* Step back, so on the way back we'll start traversing from the
6515 previous insn (or we'll see that it's bb_note and skip that
6517 if (insn
== first_insn
)
6519 first_insn
= NEXT_INSN (last_insn
);
6520 removed_last_insn
= sel_bb_end_p (last_insn
);
6527 /* We haven't found the original expr, continue descending the basic
6529 if (code_motion_path_driver_info
->orig_expr_not_found
6530 (insn
, orig_ops
, static_params
))
6532 /* Av set ops could have been changed when moving through this
6533 insn. To find them below it, we have to un-substitute them. */
6534 undo_transformations (&orig_ops
, insn
);
6538 /* Clean up and return, if the hook tells us to do so. It may
6539 happen if we've encountered the previously created
6541 code_motion_path_driver_cleanup (&orig_ops
, &path
);
6545 gcc_assert (orig_ops
);
6548 /* Stop at insn if we got to the end of BB. */
6549 if (insn
== bb_tail
)
6552 insn
= NEXT_INSN (insn
);
6555 /* Here INSN either points to the insn before the original insn (may be
6556 bb_note, if original insn was a bb_head) or to the bb_end. */
6561 gcc_assert (insn
== sel_bb_end (bb
));
6563 /* Add bb tail to PATH (but it doesn't make any sense if it's a bb_head -
6564 it's already in PATH then). */
6565 if (insn
!= first_insn
)
6566 ilist_add (&path
, insn
);
6568 /* Process_successors should be able to find at least one
6569 successor for which code_motion_path_driver returns TRUE. */
6570 res
= code_motion_process_successors (insn
, orig_ops
,
6571 path
, static_params
);
6573 /* Remove bb tail from path. */
6574 if (insn
!= first_insn
)
6575 ilist_remove (&path
);
6579 /* This is the case when one of the original expr is no longer available
6580 due to bookkeeping created on this branch with the same register.
6581 In the original algorithm, which doesn't have update_data_sets call
6582 on a bookkeeping block, it would simply result in returning
6583 FALSE when we've encountered a previously generated bookkeeping
6584 insn in moveop_orig_expr_not_found. */
6585 code_motion_path_driver_cleanup (&orig_ops
, &path
);
6590 /* Don't need it any more. */
6591 av_set_clear (&orig_ops
);
6593 /* Backward pass: now, when we have C_EXPR computed, we'll drag it to
6594 the beginning of the basic block. */
6595 before_first
= PREV_INSN (first_insn
);
6596 while (insn
!= before_first
)
6598 if (code_motion_path_driver_info
->ascend
)
6599 code_motion_path_driver_info
->ascend (insn
, static_params
);
6601 insn
= PREV_INSN (insn
);
6604 /* Now we're at the bb head. */
6606 ilist_remove (&path
);
6607 local_params_in
->removed_last_insn
= removed_last_insn
;
6608 code_motion_path_driver_info
->at_first_insn (insn
, local_params_in
, static_params
);
6610 /* This should be the very last operation as at bb head we could change
6611 the numbering by creating bookkeeping blocks. */
6612 if (removed_last_insn
)
6613 insn
= PREV_INSN (insn
);
6614 bitmap_set_bit (code_motion_visited_blocks
, BLOCK_FOR_INSN (insn
)->index
);
6618 /* Move up the operations from ORIG_OPS set traversing the dag starting
6619 from INSN. PATH represents the edges traversed so far.
6620 DEST is the register chosen for scheduling the current expr. Insert
6621 bookkeeping code in the join points. EXPR_VLIW is the chosen expression,
6622 C_EXPR is how it looks like at the given cfg point.
6623 Set *SHOULD_MOVE to indicate whether we have only disconnected
6624 one of the insns found.
6626 Returns whether original instructions were found, which is asserted
6627 to be true in the caller. */
6629 move_op (insn_t insn
, av_set_t orig_ops
, expr_t expr_vliw
,
6630 rtx dest
, expr_t c_expr
, bool *should_move
)
6632 struct moveop_static_params sparams
;
6633 struct cmpd_local_params lparams
;
6636 /* Init params for code_motion_path_driver. */
6637 sparams
.dest
= dest
;
6638 sparams
.c_expr
= c_expr
;
6639 sparams
.uid
= INSN_UID (EXPR_INSN_RTX (expr_vliw
));
6640 #ifdef ENABLE_CHECKING
6641 sparams
.failed_insn
= NULL
;
6643 sparams
.was_renamed
= false;
6646 /* We haven't visited any blocks yet. */
6647 bitmap_clear (code_motion_visited_blocks
);
6649 /* Set appropriate hooks and data. */
6650 code_motion_path_driver_info
= &move_op_hooks
;
6651 res
= code_motion_path_driver (insn
, orig_ops
, NULL
, &lparams
, &sparams
);
6653 if (sparams
.was_renamed
)
6654 EXPR_WAS_RENAMED (expr_vliw
) = true;
6656 *should_move
= (sparams
.uid
== -1);
6662 /* Functions that work with regions. */
6664 /* Current number of seqno used in init_seqno and init_seqno_1. */
6665 static int cur_seqno
;
6667 /* A helper for init_seqno. Traverse the region starting from BB and
6668 compute seqnos for visited insns, marking visited bbs in VISITED_BBS.
6669 Clear visited blocks from BLOCKS_TO_RESCHEDULE. */
6671 init_seqno_1 (basic_block bb
, sbitmap visited_bbs
, bitmap blocks_to_reschedule
)
6673 int bbi
= BLOCK_TO_BB (bb
->index
);
6674 insn_t insn
, note
= bb_note (bb
);
6678 SET_BIT (visited_bbs
, bbi
);
6679 if (blocks_to_reschedule
)
6680 bitmap_clear_bit (blocks_to_reschedule
, bb
->index
);
6682 FOR_EACH_SUCC_1 (succ_insn
, si
, BB_END (bb
),
6683 SUCCS_NORMAL
| SUCCS_SKIP_TO_LOOP_EXITS
)
6685 basic_block succ
= BLOCK_FOR_INSN (succ_insn
);
6686 int succ_bbi
= BLOCK_TO_BB (succ
->index
);
6688 gcc_assert (in_current_region_p (succ
));
6690 if (!TEST_BIT (visited_bbs
, succ_bbi
))
6692 gcc_assert (succ_bbi
> bbi
);
6694 init_seqno_1 (succ
, visited_bbs
, blocks_to_reschedule
);
6698 for (insn
= BB_END (bb
); insn
!= note
; insn
= PREV_INSN (insn
))
6699 INSN_SEQNO (insn
) = cur_seqno
--;
6702 /* Initialize seqnos for the current region. NUMBER_OF_INSNS is the number
6703 of instructions in the region, BLOCKS_TO_RESCHEDULE contains blocks on
6704 which we're rescheduling when pipelining, FROM is the block where
6705 traversing region begins (it may not be the head of the region when
6706 pipelining, but the head of the loop instead).
6708 Returns the maximal seqno found. */
6710 init_seqno (int number_of_insns
, bitmap blocks_to_reschedule
, basic_block from
)
6712 sbitmap visited_bbs
;
6716 visited_bbs
= sbitmap_alloc (current_nr_blocks
);
6718 if (blocks_to_reschedule
)
6720 sbitmap_ones (visited_bbs
);
6721 EXECUTE_IF_SET_IN_BITMAP (blocks_to_reschedule
, 0, bbi
, bi
)
6723 gcc_assert (BLOCK_TO_BB (bbi
) < current_nr_blocks
);
6724 RESET_BIT (visited_bbs
, BLOCK_TO_BB (bbi
));
6729 sbitmap_zero (visited_bbs
);
6730 from
= EBB_FIRST_BB (0);
6733 cur_seqno
= number_of_insns
> 0 ? number_of_insns
: sched_max_luid
- 1;
6734 init_seqno_1 (from
, visited_bbs
, blocks_to_reschedule
);
6735 gcc_assert (cur_seqno
== 0 || number_of_insns
== 0);
6737 sbitmap_free (visited_bbs
);
6738 return sched_max_luid
- 1;
6741 /* Initialize scheduling parameters for current region. */
6743 sel_setup_region_sched_flags (void)
6745 enable_schedule_as_rhs_p
= 1;
6747 pipelining_p
= (bookkeeping_p
6748 && (flag_sel_sched_pipelining
!= 0)
6749 && current_loop_nest
!= NULL
);
6750 max_insns_to_rename
= PARAM_VALUE (PARAM_SELSCHED_INSNS_TO_RENAME
);
6754 /* Return true if all basic blocks of current region are empty. */
6756 current_region_empty_p (void)
6759 for (i
= 0; i
< current_nr_blocks
; i
++)
6760 if (! sel_bb_empty_p (BASIC_BLOCK (BB_TO_BLOCK (i
))))
6766 /* Prepare and verify loop nest for pipelining. */
6768 setup_current_loop_nest (int rgn
)
6770 current_loop_nest
= get_loop_nest_for_rgn (rgn
);
6772 if (!current_loop_nest
)
6775 /* If this loop has any saved loop preheaders from nested loops,
6776 add these basic blocks to the current region. */
6777 sel_add_loop_preheaders ();
6779 /* Check that we're starting with a valid information. */
6780 gcc_assert (loop_latch_edge (current_loop_nest
));
6781 gcc_assert (LOOP_MARKED_FOR_PIPELINING_P (current_loop_nest
));
6784 /* Compute instruction priorities for current region. */
6786 sel_compute_priorities (int rgn
)
6788 sched_rgn_compute_dependencies (rgn
);
6790 /* Compute insn priorities in haifa style. Then free haifa style
6791 dependencies that we've calculated for this. */
6792 compute_priorities ();
6794 if (sched_verbose
>= 5)
6795 debug_rgn_dependencies (0);
6800 /* Init scheduling data for RGN. Returns true when this region should not
6803 sel_region_init (int rgn
)
6808 rgn_setup_region (rgn
);
6810 /* Even if sched_is_disabled_for_current_region_p() is true, we still
6811 do region initialization here so the region can be bundled correctly,
6812 but we'll skip the scheduling in sel_sched_region (). */
6813 if (current_region_empty_p ())
6816 if (flag_sel_sched_pipelining
)
6817 setup_current_loop_nest (rgn
);
6819 sel_setup_region_sched_flags ();
6821 bbs
= VEC_alloc (basic_block
, heap
, current_nr_blocks
);
6823 for (i
= 0; i
< current_nr_blocks
; i
++)
6824 VEC_quick_push (basic_block
, bbs
, BASIC_BLOCK (BB_TO_BLOCK (i
)));
6826 sel_init_bbs (bbs
, NULL
);
6828 /* Initialize luids and dependence analysis which both sel-sched and haifa
6830 sched_init_luids (bbs
, NULL
, NULL
, NULL
);
6831 sched_deps_init (false);
6833 /* Initialize haifa data. */
6834 rgn_setup_sched_infos ();
6835 sel_set_sched_flags ();
6836 haifa_init_h_i_d (bbs
, NULL
, NULL
, NULL
);
6838 sel_compute_priorities (rgn
);
6839 init_deps_global ();
6841 /* Main initialization. */
6842 sel_setup_sched_infos ();
6843 sel_init_global_and_expr (bbs
);
6845 VEC_free (basic_block
, heap
, bbs
);
6847 blocks_to_reschedule
= BITMAP_ALLOC (NULL
);
6849 /* Init correct liveness sets on each instruction of a single-block loop.
6850 This is the only situation when we can't update liveness when calling
6851 compute_live for the first insn of the loop. */
6852 if (current_loop_nest
)
6854 int header
= (sel_is_loop_preheader_p (BASIC_BLOCK (BB_TO_BLOCK (0)))
6858 if (current_nr_blocks
== header
+ 1)
6859 update_liveness_on_insn
6860 (sel_bb_head (BASIC_BLOCK (BB_TO_BLOCK (header
))));
6863 /* Set hooks so that no newly generated insn will go out unnoticed. */
6864 sel_register_cfg_hooks ();
6866 /* !!! We call target.sched.init () for the whole region, but we invoke
6867 targetm.sched.finish () for every ebb. */
6868 if (targetm
.sched
.init
)
6869 /* None of the arguments are actually used in any target. */
6870 targetm
.sched
.init (sched_dump
, sched_verbose
, -1);
6872 first_emitted_uid
= get_max_uid () + 1;
6873 preheader_removed
= false;
6875 /* Reset register allocation ticks array. */
6876 memset (reg_rename_tick
, 0, sizeof reg_rename_tick
);
6877 reg_rename_this_tick
= 0;
6879 bitmap_initialize (forced_ebb_heads
, 0);
6880 bitmap_clear (forced_ebb_heads
);
6883 current_copies
= BITMAP_ALLOC (NULL
);
6884 current_originators
= BITMAP_ALLOC (NULL
);
6885 code_motion_visited_blocks
= BITMAP_ALLOC (NULL
);
6890 /* Simplify insns after the scheduling. */
6892 simplify_changed_insns (void)
6896 for (i
= 0; i
< current_nr_blocks
; i
++)
6898 basic_block bb
= BASIC_BLOCK (BB_TO_BLOCK (i
));
6901 FOR_BB_INSNS (bb
, insn
)
6904 expr_t expr
= INSN_EXPR (insn
);
6906 if (EXPR_WAS_SUBSTITUTED (expr
))
6907 validate_simplify_insn (insn
);
6912 /* Find boundaries of the EBB starting from basic block BB, marking blocks of
6913 this EBB in SCHEDULED_BLOCKS and appropriately filling in HEAD, TAIL,
6914 PREV_HEAD, and NEXT_TAIL fields of CURRENT_SCHED_INFO structure. */
6916 find_ebb_boundaries (basic_block bb
, bitmap scheduled_blocks
)
6919 basic_block bb1
= bb
;
6920 if (sched_verbose
>= 2)
6921 sel_print ("Finishing schedule in bbs: ");
6925 bitmap_set_bit (scheduled_blocks
, BLOCK_TO_BB (bb1
->index
));
6927 if (sched_verbose
>= 2)
6928 sel_print ("%d; ", bb1
->index
);
6930 while (!bb_ends_ebb_p (bb1
) && (bb1
= bb_next_bb (bb1
)));
6932 if (sched_verbose
>= 2)
6935 get_ebb_head_tail (bb
, bb1
, &head
, &tail
);
6937 current_sched_info
->head
= head
;
6938 current_sched_info
->tail
= tail
;
6939 current_sched_info
->prev_head
= PREV_INSN (head
);
6940 current_sched_info
->next_tail
= NEXT_INSN (tail
);
6943 /* Regenerate INSN_SCHED_CYCLEs for insns of current EBB. */
6945 reset_sched_cycles_in_current_ebb (void)
6948 int haifa_last_clock
= -1;
6949 int haifa_clock
= 0;
6952 if (targetm
.sched
.init
)
6954 /* None of the arguments are actually used in any target.
6955 NB: We should have md_reset () hook for cases like this. */
6956 targetm
.sched
.init (sched_dump
, sched_verbose
, -1);
6959 state_reset (curr_state
);
6960 advance_state (curr_state
);
6962 for (insn
= current_sched_info
->head
;
6963 insn
!= current_sched_info
->next_tail
;
6964 insn
= NEXT_INSN (insn
))
6966 int cost
, haifa_cost
;
6968 bool asm_p
, real_insn
, after_stall
;
6975 real_insn
= recog_memoized (insn
) >= 0;
6976 clock
= INSN_SCHED_CYCLE (insn
);
6978 cost
= clock
- last_clock
;
6980 /* Initialize HAIFA_COST. */
6983 asm_p
= INSN_ASM_P (insn
);
6986 /* This is asm insn which *had* to be scheduled first
6990 /* This is a use/clobber insn. It should not change
6995 haifa_cost
= estimate_insn_cost (insn
, curr_state
);
6997 /* Stall for whatever cycles we've stalled before. */
6999 if (INSN_AFTER_STALL_P (insn
) && cost
> haifa_cost
)
7009 while (haifa_cost
--)
7011 advance_state (curr_state
);
7014 if (sched_verbose
>= 2)
7016 sel_print ("advance_state (state_transition)\n");
7017 debug_state (curr_state
);
7020 /* The DFA may report that e.g. insn requires 2 cycles to be
7021 issued, but on the next cycle it says that insn is ready
7022 to go. Check this here. */
7026 && estimate_insn_cost (insn
, curr_state
) == 0)
7033 gcc_assert (haifa_cost
== 0);
7035 if (sched_verbose
>= 2)
7036 sel_print ("Haifa cost for insn %d: %d\n", INSN_UID (insn
), haifa_cost
);
7038 if (targetm
.sched
.dfa_new_cycle
)
7039 while (targetm
.sched
.dfa_new_cycle (sched_dump
, sched_verbose
, insn
,
7040 haifa_last_clock
, haifa_clock
,
7043 advance_state (curr_state
);
7045 if (sched_verbose
>= 2)
7047 sel_print ("advance_state (dfa_new_cycle)\n");
7048 debug_state (curr_state
);
7054 cost
= state_transition (curr_state
, insn
);
7056 if (sched_verbose
>= 2)
7057 debug_state (curr_state
);
7059 gcc_assert (cost
< 0);
7062 if (targetm
.sched
.variable_issue
)
7063 targetm
.sched
.variable_issue (sched_dump
, sched_verbose
, insn
, 0);
7065 INSN_SCHED_CYCLE (insn
) = haifa_clock
;
7068 haifa_last_clock
= haifa_clock
;
7072 /* Put TImode markers on insns starting a new issue group. */
7076 int last_clock
= -1;
7079 for (insn
= current_sched_info
->head
; insn
!= current_sched_info
->next_tail
;
7080 insn
= NEXT_INSN (insn
))
7087 clock
= INSN_SCHED_CYCLE (insn
);
7088 cost
= (last_clock
== -1) ? 1 : clock
- last_clock
;
7090 gcc_assert (cost
>= 0);
7093 && GET_CODE (PATTERN (insn
)) != USE
7094 && GET_CODE (PATTERN (insn
)) != CLOBBER
)
7096 if (reload_completed
&& cost
> 0)
7097 PUT_MODE (insn
, TImode
);
7102 if (sched_verbose
>= 2)
7103 sel_print ("Cost for insn %d is %d\n", INSN_UID (insn
), cost
);
7107 /* Perform MD_FINISH on EBBs comprising current region. When
7108 RESET_SCHED_CYCLES_P is true, run a pass emulating the scheduler
7109 to produce correct sched cycles on insns. */
7111 sel_region_target_finish (bool reset_sched_cycles_p
)
7114 bitmap scheduled_blocks
= BITMAP_ALLOC (NULL
);
7116 for (i
= 0; i
< current_nr_blocks
; i
++)
7118 if (bitmap_bit_p (scheduled_blocks
, i
))
7121 /* While pipelining outer loops, skip bundling for loop
7122 preheaders. Those will be rescheduled in the outer loop. */
7123 if (sel_is_loop_preheader_p (EBB_FIRST_BB (i
)))
7126 find_ebb_boundaries (EBB_FIRST_BB (i
), scheduled_blocks
);
7128 if (no_real_insns_p (current_sched_info
->head
, current_sched_info
->tail
))
7131 if (reset_sched_cycles_p
)
7132 reset_sched_cycles_in_current_ebb ();
7134 if (targetm
.sched
.init
)
7135 targetm
.sched
.init (sched_dump
, sched_verbose
, -1);
7139 if (targetm
.sched
.finish
)
7141 targetm
.sched
.finish (sched_dump
, sched_verbose
);
7143 /* Extend luids so that insns generated by the target will
7145 sched_init_luids (NULL
, NULL
, NULL
, NULL
);
7149 BITMAP_FREE (scheduled_blocks
);
7152 /* Free the scheduling data for the current region. When RESET_SCHED_CYCLES_P
7153 is true, make an additional pass emulating scheduler to get correct insn
7154 cycles for md_finish calls. */
7156 sel_region_finish (bool reset_sched_cycles_p
)
7158 simplify_changed_insns ();
7159 sched_finish_ready_list ();
7162 /* Free the vectors. */
7164 VEC_free (expr_t
, heap
, vec_av_set
);
7165 BITMAP_FREE (current_copies
);
7166 BITMAP_FREE (current_originators
);
7167 BITMAP_FREE (code_motion_visited_blocks
);
7168 vinsn_vec_free (&vec_bookkeeping_blocked_vinsns
);
7169 vinsn_vec_free (&vec_target_unavailable_vinsns
);
7171 /* If LV_SET of the region head should be updated, do it now because
7172 there will be no other chance. */
7177 FOR_EACH_SUCC_1 (insn
, si
, bb_note (EBB_FIRST_BB (0)),
7178 SUCCS_NORMAL
| SUCCS_SKIP_TO_LOOP_EXITS
)
7180 basic_block bb
= BLOCK_FOR_INSN (insn
);
7182 if (!BB_LV_SET_VALID_P (bb
))
7183 compute_live (insn
);
7187 /* Emulate the Haifa scheduler for bundling. */
7188 if (reload_completed
)
7189 sel_region_target_finish (reset_sched_cycles_p
);
7191 sel_finish_global_and_expr ();
7193 bitmap_clear (forced_ebb_heads
);
7197 finish_deps_global ();
7198 sched_finish_luids ();
7201 BITMAP_FREE (blocks_to_reschedule
);
7203 sel_unregister_cfg_hooks ();
7209 /* Functions that implement the scheduler driver. */
7211 /* Schedule a parallel instruction group on each of FENCES. MAX_SEQNO
7212 is the current maximum seqno. SCHEDULED_INSNS_TAILPP is the list
7213 of insns scheduled -- these would be postprocessed later. */
7215 schedule_on_fences (flist_t fences
, int max_seqno
,
7216 ilist_t
**scheduled_insns_tailpp
)
7218 flist_t old_fences
= fences
;
7220 if (sched_verbose
>= 1)
7222 sel_print ("\nScheduling on fences: ");
7223 dump_flist (fences
);
7227 scheduled_something_on_previous_fence
= false;
7228 for (; fences
; fences
= FLIST_NEXT (fences
))
7230 fence_t fence
= NULL
;
7233 bool first_p
= true;
7235 /* Choose the next fence group to schedule.
7236 The fact that insn can be scheduled only once
7237 on the cycle is guaranteed by two properties:
7238 1. seqnos of parallel groups decrease with each iteration.
7239 2. If is_ineligible_successor () sees the larger seqno, it
7240 checks if candidate insn is_in_current_fence_p (). */
7241 for (fences2
= old_fences
; fences2
; fences2
= FLIST_NEXT (fences2
))
7243 fence_t f
= FLIST_FENCE (fences2
);
7245 if (!FENCE_PROCESSED_P (f
))
7247 int i
= INSN_SEQNO (FENCE_INSN (f
));
7249 if (first_p
|| i
> seqno
)
7256 /* ??? Seqnos of different groups should be different. */
7257 gcc_assert (1 || i
!= seqno
);
7263 /* As FENCE is nonnull, SEQNO is initialized. */
7264 seqno
-= max_seqno
+ 1;
7265 fill_insns (fence
, seqno
, scheduled_insns_tailpp
);
7266 FENCE_PROCESSED_P (fence
) = true;
7269 /* All av_sets are invalidated by GLOBAL_LEVEL increase, thus we
7270 don't need to keep bookkeeping-invalidated and target-unavailable
7272 vinsn_vec_clear (&vec_bookkeeping_blocked_vinsns
);
7273 vinsn_vec_clear (&vec_target_unavailable_vinsns
);
7276 /* Calculate MIN_SEQNO and MAX_SEQNO. */
7278 find_min_max_seqno (flist_t fences
, int *min_seqno
, int *max_seqno
)
7280 *min_seqno
= *max_seqno
= INSN_SEQNO (FENCE_INSN (FLIST_FENCE (fences
)));
7282 /* The first element is already processed. */
7283 while ((fences
= FLIST_NEXT (fences
)))
7285 int seqno
= INSN_SEQNO (FENCE_INSN (FLIST_FENCE (fences
)));
7287 if (*min_seqno
> seqno
)
7289 else if (*max_seqno
< seqno
)
7294 /* Calculate new fences from FENCES. */
7296 calculate_new_fences (flist_t fences
, int orig_max_seqno
)
7298 flist_t old_fences
= fences
;
7299 struct flist_tail_def _new_fences
, *new_fences
= &_new_fences
;
7301 flist_tail_init (new_fences
);
7302 for (; fences
; fences
= FLIST_NEXT (fences
))
7304 fence_t fence
= FLIST_FENCE (fences
);
7307 if (!FENCE_BNDS (fence
))
7309 /* This fence doesn't have any successors. */
7310 if (!FENCE_SCHEDULED_P (fence
))
7312 /* Nothing was scheduled on this fence. */
7315 insn
= FENCE_INSN (fence
);
7316 seqno
= INSN_SEQNO (insn
);
7317 gcc_assert (seqno
> 0 && seqno
<= orig_max_seqno
);
7319 if (sched_verbose
>= 1)
7320 sel_print ("Fence %d[%d] has not changed\n",
7323 move_fence_to_fences (fences
, new_fences
);
7327 extract_new_fences_from (fences
, new_fences
, orig_max_seqno
);
7330 flist_clear (&old_fences
);
7331 return FLIST_TAIL_HEAD (new_fences
);
7334 /* Update seqnos of insns given by PSCHEDULED_INSNS. MIN_SEQNO and MAX_SEQNO
7335 are the miminum and maximum seqnos of the group, HIGHEST_SEQNO_IN_USE is
7336 the highest seqno used in a region. Return the updated highest seqno. */
7338 update_seqnos_and_stage (int min_seqno
, int max_seqno
,
7339 int highest_seqno_in_use
,
7340 ilist_t
*pscheduled_insns
)
7346 /* Actually, new_hs is the seqno of the instruction, that was
7347 scheduled first (i.e. it is the first one in SCHEDULED_INSNS). */
7348 if (*pscheduled_insns
)
7350 new_hs
= (INSN_SEQNO (ILIST_INSN (*pscheduled_insns
))
7351 + highest_seqno_in_use
+ max_seqno
- min_seqno
+ 2);
7352 gcc_assert (new_hs
> highest_seqno_in_use
);
7355 new_hs
= highest_seqno_in_use
;
7357 FOR_EACH_INSN (insn
, ii
, *pscheduled_insns
)
7359 gcc_assert (INSN_SEQNO (insn
) < 0);
7360 INSN_SEQNO (insn
) += highest_seqno_in_use
+ max_seqno
- min_seqno
+ 2;
7361 gcc_assert (INSN_SEQNO (insn
) <= new_hs
);
7363 /* When not pipelining, purge unneeded insn info on the scheduled insns.
7364 For example, having reg_last array of INSN_DEPS_CONTEXT in memory may
7365 require > 1GB of memory e.g. on limit-fnargs.c. */
7367 free_data_for_scheduled_insn (insn
);
7370 ilist_clear (pscheduled_insns
);
7376 /* The main driver for scheduling a region. This function is responsible
7377 for correct propagation of fences (i.e. scheduling points) and creating
7378 a group of parallel insns at each of them. It also supports
7379 pipelining. ORIG_MAX_SEQNO is the maximal seqno before this pass
7382 sel_sched_region_2 (int orig_max_seqno
)
7384 int highest_seqno_in_use
= orig_max_seqno
;
7386 stat_bookkeeping_copies
= 0;
7387 stat_insns_needed_bookkeeping
= 0;
7388 stat_renamed_scheduled
= 0;
7389 stat_substitutions_total
= 0;
7390 num_insns_scheduled
= 0;
7394 int min_seqno
, max_seqno
;
7395 ilist_t scheduled_insns
= NULL
;
7396 ilist_t
*scheduled_insns_tailp
= &scheduled_insns
;
7398 find_min_max_seqno (fences
, &min_seqno
, &max_seqno
);
7399 schedule_on_fences (fences
, max_seqno
, &scheduled_insns_tailp
);
7400 fences
= calculate_new_fences (fences
, orig_max_seqno
);
7401 highest_seqno_in_use
= update_seqnos_and_stage (min_seqno
, max_seqno
,
7402 highest_seqno_in_use
,
7406 if (sched_verbose
>= 1)
7407 sel_print ("Scheduled %d bookkeeping copies, %d insns needed "
7408 "bookkeeping, %d insns renamed, %d insns substituted\n",
7409 stat_bookkeeping_copies
,
7410 stat_insns_needed_bookkeeping
,
7411 stat_renamed_scheduled
,
7412 stat_substitutions_total
);
7415 /* Schedule a region. When pipelining, search for possibly never scheduled
7416 bookkeeping code and schedule it. Reschedule pipelined code without
7417 pipelining after. */
7419 sel_sched_region_1 (void)
7421 int number_of_insns
;
7424 /* Remove empty blocks that might be in the region from the beginning.
7425 We need to do save sched_max_luid before that, as it actually shows
7426 the number of insns in the region, and purge_empty_blocks can
7428 number_of_insns
= sched_max_luid
- 1;
7429 purge_empty_blocks ();
7431 orig_max_seqno
= init_seqno (number_of_insns
, NULL
, NULL
);
7432 gcc_assert (orig_max_seqno
>= 1);
7434 /* When pipelining outer loops, create fences on the loop header,
7437 if (current_loop_nest
)
7438 init_fences (BB_END (EBB_FIRST_BB (0)));
7440 init_fences (bb_note (EBB_FIRST_BB (0)));
7443 sel_sched_region_2 (orig_max_seqno
);
7445 gcc_assert (fences
== NULL
);
7451 struct flist_tail_def _new_fences
;
7452 flist_tail_t new_fences
= &_new_fences
;
7455 pipelining_p
= false;
7456 max_ws
= MIN (max_ws
, issue_rate
* 3 / 2);
7457 bookkeeping_p
= false;
7458 enable_schedule_as_rhs_p
= false;
7460 /* Schedule newly created code, that has not been scheduled yet. */
7467 for (i
= 0; i
< current_nr_blocks
; i
++)
7469 basic_block bb
= EBB_FIRST_BB (i
);
7471 if (sel_bb_empty_p (bb
))
7473 bitmap_clear_bit (blocks_to_reschedule
, bb
->index
);
7477 if (bitmap_bit_p (blocks_to_reschedule
, bb
->index
))
7479 clear_outdated_rtx_info (bb
);
7480 if (sel_insn_is_speculation_check (BB_END (bb
))
7481 && JUMP_P (BB_END (bb
)))
7482 bitmap_set_bit (blocks_to_reschedule
,
7483 BRANCH_EDGE (bb
)->dest
->index
);
7485 else if (INSN_SCHED_TIMES (sel_bb_head (bb
)) <= 0)
7486 bitmap_set_bit (blocks_to_reschedule
, bb
->index
);
7489 for (i
= 0; i
< current_nr_blocks
; i
++)
7491 bb
= EBB_FIRST_BB (i
);
7493 /* While pipelining outer loops, skip bundling for loop
7494 preheaders. Those will be rescheduled in the outer
7496 if (sel_is_loop_preheader_p (bb
))
7498 clear_outdated_rtx_info (bb
);
7502 if (bitmap_bit_p (blocks_to_reschedule
, bb
->index
))
7504 flist_tail_init (new_fences
);
7506 orig_max_seqno
= init_seqno (0, blocks_to_reschedule
, bb
);
7508 /* Mark BB as head of the new ebb. */
7509 bitmap_set_bit (forced_ebb_heads
, bb
->index
);
7511 bitmap_clear_bit (blocks_to_reschedule
, bb
->index
);
7513 gcc_assert (fences
== NULL
);
7515 init_fences (bb_note (bb
));
7517 sel_sched_region_2 (orig_max_seqno
);
7527 /* Schedule the RGN region. */
7529 sel_sched_region (int rgn
)
7532 bool reset_sched_cycles_p
;
7534 if (sel_region_init (rgn
))
7537 if (sched_verbose
>= 1)
7538 sel_print ("Scheduling region %d\n", rgn
);
7540 schedule_p
= (!sched_is_disabled_for_current_region_p ()
7541 && dbg_cnt (sel_sched_region_cnt
));
7542 reset_sched_cycles_p
= pipelining_p
;
7544 sel_sched_region_1 ();
7546 /* Force initialization of INSN_SCHED_CYCLEs for correct bundling. */
7547 reset_sched_cycles_p
= true;
7549 sel_region_finish (reset_sched_cycles_p
);
7552 /* Perform global init for the scheduler. */
7554 sel_global_init (void)
7556 calculate_dominance_info (CDI_DOMINATORS
);
7557 alloc_sched_pools ();
7559 /* Setup the infos for sched_init. */
7560 sel_setup_sched_infos ();
7561 setup_sched_dump ();
7563 sched_rgn_init (false);
7567 /* Reset AFTER_RECOVERY if it has been set by the 1st scheduler pass. */
7569 can_issue_more
= issue_rate
;
7571 sched_extend_target ();
7572 sched_deps_init (true);
7573 setup_nop_and_exit_insns ();
7574 sel_extend_global_bb_info ();
7576 init_hard_regs_data ();
7579 /* Free the global data of the scheduler. */
7581 sel_global_finish (void)
7583 free_bb_note_pool ();
7585 sel_finish_global_bb_info ();
7587 free_regset_pool ();
7588 free_nop_and_exit_insns ();
7590 sched_rgn_finish ();
7591 sched_deps_finish ();
7595 sel_finish_pipelining ();
7597 free_sched_pools ();
7598 free_dominance_info (CDI_DOMINATORS
);
7601 /* Return true when we need to skip selective scheduling. Used for debugging. */
7603 maybe_skip_selective_scheduling (void)
7605 return ! dbg_cnt (sel_sched_cnt
);
7608 /* The entry point. */
7610 run_selective_scheduling (void)
7614 if (n_basic_blocks
== NUM_FIXED_BLOCKS
)
7619 for (rgn
= 0; rgn
< nr_regions
; rgn
++)
7620 sel_sched_region (rgn
);
7622 sel_global_finish ();