1 /* Instruction scheduling pass. Selective scheduler and pipeliner.
2 Copyright (C) 2006-2019 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify it under
7 the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 3, or (at your option) any later
11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
22 #include "coretypes.h"
31 #include "cfgcleanup.h"
32 #include "insn-config.h"
33 #include "insn-attr.h"
36 #include "sched-int.h"
37 #include "rtlhooks-def.h"
42 #ifdef INSN_SCHEDULING
45 #include "sel-sched-ir.h"
46 #include "sel-sched-dump.h"
47 #include "sel-sched.h"
50 /* Implementation of selective scheduling approach.
51 The below implementation follows the original approach with the following
54 o the scheduler works after register allocation (but can be also tuned
56 o some instructions are not copied or register renamed;
57 o conditional jumps are not moved with code duplication;
58 o several jumps in one parallel group are not supported;
59 o when pipelining outer loops, code motion through inner loops
61 o control and data speculation are supported;
62 o some improvements for better compile time/performance were made.
67 A vinsn, or virtual insn, is an insn with additional data characterizing
68 insn pattern, such as LHS, RHS, register sets used/set/clobbered, etc.
69 Vinsns also act as smart pointers to save memory by reusing them in
70 different expressions. A vinsn is described by vinsn_t type.
72 An expression is a vinsn with additional data characterizing its properties
73 at some point in the control flow graph. The data may be its usefulness,
74 priority, speculative status, whether it was renamed/subsituted, etc.
75 An expression is described by expr_t type.
77 Availability set (av_set) is a set of expressions at a given control flow
78 point. It is represented as av_set_t. The expressions in av sets are kept
79 sorted in the terms of expr_greater_p function. It allows to truncate
80 the set while leaving the best expressions.
82 A fence is a point through which code motion is prohibited. On each step,
83 we gather a parallel group of insns at a fence. It is possible to have
84 multiple fences. A fence is represented via fence_t.
86 A boundary is the border between the fence group and the rest of the code.
87 Currently, we never have more than one boundary per fence, as we finalize
88 the fence group when a jump is scheduled. A boundary is represented
94 The scheduler finds regions to schedule, schedules each one, and finalizes.
95 The regions are formed starting from innermost loops, so that when the inner
96 loop is pipelined, its prologue can be scheduled together with yet unprocessed
97 outer loop. The rest of acyclic regions are found using extend_rgns:
98 the blocks that are not yet allocated to any regions are traversed in top-down
99 order, and a block is added to a region to which all its predecessors belong;
100 otherwise, the block starts its own region.
102 The main scheduling loop (sel_sched_region_2) consists of just
103 scheduling on each fence and updating fences. For each fence,
104 we fill a parallel group of insns (fill_insns) until some insns can be added.
105 First, we compute available exprs (av-set) at the boundary of the current
106 group. Second, we choose the best expression from it. If the stall is
107 required to schedule any of the expressions, we advance the current cycle
108 appropriately. So, the final group does not exactly correspond to a VLIW
109 word. Third, we move the chosen expression to the boundary (move_op)
110 and update the intermediate av sets and liveness sets. We quit fill_insns
111 when either no insns left for scheduling or we have scheduled enough insns
112 so we feel like advancing a scheduling point.
114 Computing available expressions
115 ===============================
117 The computation (compute_av_set) is a bottom-up traversal. At each insn,
118 we're moving the union of its successors' sets through it via
119 moveup_expr_set. The dependent expressions are removed. Local
120 transformations (substitution, speculation) are applied to move more
121 exprs. Then the expr corresponding to the current insn is added.
122 The result is saved on each basic block header.
124 When traversing the CFG, we're moving down for no more than max_ws insns.
125 Also, we do not move down to ineligible successors (is_ineligible_successor),
126 which include moving along a back-edge, moving to already scheduled code,
127 and moving to another fence. The first two restrictions are lifted during
128 pipelining, which allows us to move insns along a back-edge. We always have
129 an acyclic region for scheduling because we forbid motion through fences.
131 Choosing the best expression
132 ============================
134 We sort the final availability set via sel_rank_for_schedule, then we remove
135 expressions which are not yet ready (tick_check_p) or which dest registers
136 cannot be used. For some of them, we choose another register via
137 find_best_reg. To do this, we run find_used_regs to calculate the set of
138 registers which cannot be used. The find_used_regs function performs
139 a traversal of code motion paths for an expr. We consider for renaming
140 only registers which are from the same regclass as the original one and
141 using which does not interfere with any live ranges. Finally, we convert
142 the resulting set to the ready list format and use max_issue and reorder*
143 hooks similarly to the Haifa scheduler.
145 Scheduling the best expression
146 ==============================
148 We run the move_op routine to perform the same type of code motion paths
149 traversal as in find_used_regs. (These are working via the same driver,
150 code_motion_path_driver.) When moving down the CFG, we look for original
151 instruction that gave birth to a chosen expression. We undo
152 the transformations performed on an expression via the history saved in it.
153 When found, we remove the instruction or leave a reg-reg copy/speculation
154 check if needed. On a way up, we insert bookkeeping copies at each join
155 point. If a copy is not needed, it will be removed later during this
156 traversal. We update the saved av sets and liveness sets on the way up, too.
158 Finalizing the schedule
159 =======================
161 When pipelining, we reschedule the blocks from which insns were pipelined
162 to get a tighter schedule. On Itanium, we also perform bundling via
163 the same routine from ia64.c.
165 Dependence analysis changes
166 ===========================
168 We augmented the sched-deps.c with hooks that get called when a particular
169 dependence is found in a particular part of an insn. Using these hooks, we
170 can do several actions such as: determine whether an insn can be moved through
171 another (has_dependence_p, moveup_expr); find out whether an insn can be
172 scheduled on the current cycle (tick_check_p); find out registers that
173 are set/used/clobbered by an insn and find out all the strange stuff that
174 restrict its movement, like SCHED_GROUP_P or CANT_MOVE (done in
175 init_global_and_expr_for_insn).
177 Initialization changes
178 ======================
180 There are parts of haifa-sched.c, sched-deps.c, and sched-rgn.c that are
181 reused in all of the schedulers. We have split up the initialization of data
182 of such parts into different functions prefixed with scheduler type and
183 postfixed with the type of data initialized: {,sel_,haifa_}sched_{init,finish},
184 sched_rgn_init/finish, sched_deps_init/finish, sched_init_{luids/bbs}, etc.
185 The same splitting is done with current_sched_info structure:
186 dependence-related parts are in sched_deps_info, common part is in
187 common_sched_info, and haifa/sel/etc part is in current_sched_info.
192 As we now have multiple-point scheduling, this would not work with backends
193 which save some of the scheduler state to use it in the target hooks.
194 For this purpose, we introduce a concept of target contexts, which
195 encapsulate such information. The backend should implement simple routines
196 of allocating/freeing/setting such a context. The scheduler calls these
197 as target hooks and handles the target context as an opaque pointer (similar
198 to the DFA state type, state_t).
203 As the correct data dependence graph is not supported during scheduling (which
204 is to be changed in mid-term), we cache as much of the dependence analysis
205 results as possible to avoid reanalyzing. This includes: bitmap caches on
206 each insn in stream of the region saying yes/no for a query with a pair of
207 UIDs; hashtables with the previously done transformations on each insn in
208 stream; a vector keeping a history of transformations on each expr.
210 Also, we try to minimize the dependence context used on each fence to check
211 whether the given expression is ready for scheduling by removing from it
212 insns that are definitely completed the execution. The results of
213 tick_check_p checks are also cached in a vector on each fence.
215 We keep a valid liveness set on each insn in a region to avoid the high
216 cost of recomputation on large basic blocks.
218 Finally, we try to minimize the number of needed updates to the availability
219 sets. The updates happen in two cases: when fill_insns terminates,
220 we advance all fences and increase the stage number to show that the region
221 has changed and the sets are to be recomputed; and when the next iteration
222 of a loop in fill_insns happens (but this one reuses the saved av sets
223 on bb headers.) Thus, we try to break the fill_insns loop only when
224 "significant" number of insns from the current scheduling window was
225 scheduled. This should be made a target param.
228 TODO: correctly support the data dependence graph at all stages and get rid
229 of all caches. This should speed up the scheduler.
230 TODO: implement moving cond jumps with bookkeeping copies on both targets.
231 TODO: tune the scheduler before RA so it does not create too much pseudos.
235 S.-M. Moon and K. Ebcioglu. Parallelizing nonnumerical code with
236 selective scheduling and software pipelining.
237 ACM TOPLAS, Vol 19, No. 6, pages 853--898, Nov. 1997.
239 Andrey Belevantsev, Maxim Kuvyrkov, Vladimir Makarov, Dmitry Melnik,
240 and Dmitry Zhurikhin. An interblock VLIW-targeted instruction scheduler
241 for GCC. In Proceedings of GCC Developers' Summit 2006.
243 Arutyun Avetisyan, Andrey Belevantsev, and Dmitry Melnik. GCC Instruction
244 Scheduler and Software Pipeliner on the Itanium Platform. EPIC-7 Workshop.
245 http://rogue.colorado.edu/EPIC7/.
249 /* True when pipelining is enabled. */
252 /* True if bookkeeping is enabled. */
255 /* Maximum number of insns that are eligible for renaming. */
256 int max_insns_to_rename
;
259 /* Definitions of local types and macros. */
261 /* Represents possible outcomes of moving an expression through an insn. */
262 enum MOVEUP_EXPR_CODE
264 /* The expression is not changed. */
267 /* Not changed, but requires a new destination register. */
270 /* Cannot be moved. */
273 /* Changed (substituted or speculated). */
277 /* The container to be passed into rtx search & replace functions. */
278 struct rtx_search_arg
280 /* What we are searching for. */
283 /* The occurrence counter. */
287 typedef struct rtx_search_arg
*rtx_search_arg_p
;
289 /* This struct contains precomputed hard reg sets that are needed when
290 computing registers available for renaming. */
291 struct hard_regs_data
293 /* For every mode, this stores registers available for use with
295 HARD_REG_SET regs_for_mode
[NUM_MACHINE_MODES
];
297 /* True when regs_for_mode[mode] is initialized. */
298 bool regs_for_mode_ok
[NUM_MACHINE_MODES
];
300 /* For every register, it has regs that are ok to rename into it.
301 The register in question is always set. If not, this means
302 that the whole set is not computed yet. */
303 HARD_REG_SET regs_for_rename
[FIRST_PSEUDO_REGISTER
];
305 /* For every mode, this stores registers not available due to
307 HARD_REG_SET regs_for_call_clobbered
[NUM_MACHINE_MODES
];
309 /* All registers that are used or call used. */
310 HARD_REG_SET regs_ever_used
;
313 /* Stack registers. */
314 HARD_REG_SET stack_regs
;
318 /* Holds the results of computation of available for renaming and
319 unavailable hard registers. */
322 /* These are unavailable due to calls crossing, globalness, etc. */
323 HARD_REG_SET unavailable_hard_regs
;
325 /* These are *available* for renaming. */
326 HARD_REG_SET available_for_renaming
;
328 /* Whether this code motion path crosses a call. */
332 /* A global structure that contains the needed information about harg
334 static struct hard_regs_data sel_hrd
;
337 /* This structure holds local data used in code_motion_path_driver hooks on
338 the same or adjacent levels of recursion. Here we keep those parameters
339 that are not used in code_motion_path_driver routine itself, but only in
340 its hooks. Moreover, all parameters that can be modified in hooks are
341 in this structure, so all other parameters passed explicitly to hooks are
343 struct cmpd_local_params
345 /* Local params used in move_op_* functions. */
347 /* Edges for bookkeeping generation. */
350 /* C_EXPR merged from all successors and locally allocated temporary C_EXPR. */
351 expr_t c_expr_merged
, c_expr_local
;
353 /* Local params used in fur_* functions. */
354 /* Copy of the ORIGINAL_INSN list, stores the original insns already
355 found before entering the current level of code_motion_path_driver. */
356 def_list_t old_original_insns
;
358 /* Local params used in move_op_* functions. */
359 /* True when we have removed last insn in the block which was
360 also a boundary. Do not update anything or create bookkeeping copies. */
361 BOOL_BITFIELD removed_last_insn
: 1;
364 /* Stores the static parameters for move_op_* calls. */
365 struct moveop_static_params
367 /* Destination register. */
370 /* Current C_EXPR. */
373 /* An UID of expr_vliw which is to be moved up. If we find other exprs,
374 they are to be removed. */
377 /* This is initialized to the insn on which the driver stopped its traversal. */
380 /* True if we scheduled an insn with different register. */
384 /* Stores the static parameters for fur_* calls. */
385 struct fur_static_params
387 /* Set of registers unavailable on the code motion path. */
390 /* Pointer to the list of original insns definitions. */
391 def_list_t
*original_insns
;
393 /* True if a code motion path contains a CALL insn. */
397 typedef struct fur_static_params
*fur_static_params_p
;
398 typedef struct cmpd_local_params
*cmpd_local_params_p
;
399 typedef struct moveop_static_params
*moveop_static_params_p
;
401 /* Set of hooks and parameters that determine behavior specific to
402 move_op or find_used_regs functions. */
403 struct code_motion_path_driver_info_def
405 /* Called on enter to the basic block. */
406 int (*on_enter
) (insn_t
, cmpd_local_params_p
, void *, bool);
408 /* Called when original expr is found. */
409 void (*orig_expr_found
) (insn_t
, expr_t
, cmpd_local_params_p
, void *);
411 /* Called while descending current basic block if current insn is not
412 the original EXPR we're searching for. */
413 bool (*orig_expr_not_found
) (insn_t
, av_set_t
, void *);
415 /* Function to merge C_EXPRes from different successors. */
416 void (*merge_succs
) (insn_t
, insn_t
, int, cmpd_local_params_p
, void *);
418 /* Function to finalize merge from different successors and possibly
419 deallocate temporary data structures used for merging. */
420 void (*after_merge_succs
) (cmpd_local_params_p
, void *);
422 /* Called on the backward stage of recursion to do moveup_expr.
423 Used only with move_op_*. */
424 void (*ascend
) (insn_t
, void *);
426 /* Called on the ascending pass, before returning from the current basic
427 block or from the whole traversal. */
428 void (*at_first_insn
) (insn_t
, cmpd_local_params_p
, void *);
430 /* When processing successors in move_op we need only descend into
431 SUCCS_NORMAL successors, while in find_used_regs we need SUCCS_ALL. */
434 /* The routine name to print in dumps ("move_op" of "find_used_regs"). */
435 const char *routine_name
;
438 /* Global pointer to current hooks, either points to MOVE_OP_HOOKS or
440 struct code_motion_path_driver_info_def
*code_motion_path_driver_info
;
442 /* Set of hooks for performing move_op and find_used_regs routines with
443 code_motion_path_driver. */
444 extern struct code_motion_path_driver_info_def move_op_hooks
, fur_hooks
;
446 /* True if/when we want to emulate Haifa scheduler in the common code.
447 This is used in sched_rgn_local_init and in various places in
449 int sched_emulate_haifa_p
;
451 /* GLOBAL_LEVEL is used to discard information stored in basic block headers
452 av_sets. Av_set of bb header is valid if its (bb header's) level is equal
453 to GLOBAL_LEVEL. And invalid if lesser. This is primarily used to advance
454 scheduling window. */
457 /* Current fences. */
460 /* True when separable insns should be scheduled as RHSes. */
461 static bool enable_schedule_as_rhs_p
;
463 /* Used in verify_target_availability to assert that target reg is reported
464 unavailabile by both TARGET_UNAVAILABLE and find_used_regs only if
465 we haven't scheduled anything on the previous fence.
466 if scheduled_something_on_previous_fence is true, TARGET_UNAVAILABLE can
467 have more conservative value than the one returned by the
468 find_used_regs, thus we shouldn't assert that these values are equal. */
469 static bool scheduled_something_on_previous_fence
;
471 /* All newly emitted insns will have their uids greater than this value. */
472 static int first_emitted_uid
;
474 /* Set of basic blocks that are forced to start new ebbs. This is a subset
475 of all the ebb heads. */
476 bitmap forced_ebb_heads
;
478 /* Blocks that need to be rescheduled after pipelining. */
479 bitmap blocks_to_reschedule
= NULL
;
481 /* True when the first lv set should be ignored when updating liveness. */
482 static bool ignore_first
= false;
484 /* Number of insns max_issue has initialized data structures for. */
485 static int max_issue_size
= 0;
487 /* Whether we can issue more instructions. */
488 static int can_issue_more
;
490 /* Maximum software lookahead window size, reduced when rescheduling after
494 /* Number of insns scheduled in current region. */
495 static int num_insns_scheduled
;
497 /* A vector of expressions is used to be able to sort them. */
498 static vec
<expr_t
> vec_av_set
;
500 /* A vector of vinsns is used to hold temporary lists of vinsns. */
501 typedef vec
<vinsn_t
> vinsn_vec_t
;
503 /* This vector has the exprs which may still present in av_sets, but actually
504 can't be moved up due to bookkeeping created during code motion to another
505 fence. See comment near the call to update_and_record_unavailable_insns
506 for the detailed explanations. */
507 static vinsn_vec_t vec_bookkeeping_blocked_vinsns
= vinsn_vec_t ();
509 /* This vector has vinsns which are scheduled with renaming on the first fence
510 and then seen on the second. For expressions with such vinsns, target
511 availability information may be wrong. */
512 static vinsn_vec_t vec_target_unavailable_vinsns
= vinsn_vec_t ();
514 /* Vector to store temporary nops inserted in move_op to prevent removal
516 static vec
<insn_t
> vec_temp_moveop_nops
;
518 /* These bitmaps record original instructions scheduled on the current
519 iteration and bookkeeping copies created by them. */
520 static bitmap current_originators
= NULL
;
521 static bitmap current_copies
= NULL
;
523 /* This bitmap marks the blocks visited by code_motion_path_driver so we don't
524 visit them afterwards. */
525 static bitmap code_motion_visited_blocks
= NULL
;
527 /* Variables to accumulate different statistics. */
529 /* The number of bookkeeping copies created. */
530 static int stat_bookkeeping_copies
;
532 /* The number of insns that required bookkeeiping for their scheduling. */
533 static int stat_insns_needed_bookkeeping
;
535 /* The number of insns that got renamed. */
536 static int stat_renamed_scheduled
;
538 /* The number of substitutions made during scheduling. */
539 static int stat_substitutions_total
;
542 /* Forward declarations of static functions. */
543 static bool rtx_ok_for_substitution_p (rtx
, rtx
);
544 static int sel_rank_for_schedule (const void *, const void *);
545 static av_set_t
find_sequential_best_exprs (bnd_t
, expr_t
, bool);
546 static basic_block
find_block_for_bookkeeping (edge e1
, edge e2
, bool lax
);
548 static rtx
get_dest_from_orig_ops (av_set_t
);
549 static basic_block
generate_bookkeeping_insn (expr_t
, edge
, edge
);
550 static bool find_used_regs (insn_t
, av_set_t
, regset
, struct reg_rename
*,
552 static bool move_op (insn_t
, av_set_t
, expr_t
, rtx
, expr_t
, bool*);
553 static int code_motion_path_driver (insn_t
, av_set_t
, ilist_t
,
554 cmpd_local_params_p
, void *);
555 static void sel_sched_region_1 (void);
556 static void sel_sched_region_2 (int);
557 static av_set_t
compute_av_set_inside_bb (insn_t
, ilist_t
, int, bool);
559 static void debug_state (state_t
);
562 /* Functions that work with fences. */
564 /* Advance one cycle on FENCE. */
566 advance_one_cycle (fence_t fence
)
572 advance_state (FENCE_STATE (fence
));
573 cycle
= ++FENCE_CYCLE (fence
);
574 FENCE_ISSUED_INSNS (fence
) = 0;
575 FENCE_STARTS_CYCLE_P (fence
) = 1;
576 can_issue_more
= issue_rate
;
577 FENCE_ISSUE_MORE (fence
) = can_issue_more
;
579 for (i
= 0; vec_safe_iterate (FENCE_EXECUTING_INSNS (fence
), i
, &insn
); )
581 if (INSN_READY_CYCLE (insn
) < cycle
)
583 remove_from_deps (FENCE_DC (fence
), insn
);
584 FENCE_EXECUTING_INSNS (fence
)->unordered_remove (i
);
589 if (sched_verbose
>= 2)
591 sel_print ("Finished a cycle. Current cycle = %d\n", FENCE_CYCLE (fence
));
592 debug_state (FENCE_STATE (fence
));
596 /* Returns true when SUCC in a fallthru bb of INSN, possibly
597 skipping empty basic blocks. */
599 in_fallthru_bb_p (rtx_insn
*insn
, rtx succ
)
601 basic_block bb
= BLOCK_FOR_INSN (insn
);
604 if (bb
== BLOCK_FOR_INSN (succ
))
607 e
= find_fallthru_edge_from (bb
);
613 while (sel_bb_empty_p (bb
))
616 return bb
== BLOCK_FOR_INSN (succ
);
619 /* Construct successor fences from OLD_FENCEs and put them in NEW_FENCES.
620 When a successor will continue a ebb, transfer all parameters of a fence
621 to the new fence. ORIG_MAX_SEQNO is the maximal seqno before this round
622 of scheduling helping to distinguish between the old and the new code. */
624 extract_new_fences_from (flist_t old_fences
, flist_tail_t new_fences
,
627 bool was_here_p
= false;
632 fence_t fence
= FLIST_FENCE (old_fences
);
635 /* Get the only element of FENCE_BNDS (fence). */
636 FOR_EACH_INSN (insn
, ii
, FENCE_BNDS (fence
))
638 gcc_assert (!was_here_p
);
641 gcc_assert (was_here_p
&& insn
!= NULL_RTX
);
643 /* When in the "middle" of the block, just move this fence
645 bb
= BLOCK_FOR_INSN (insn
);
646 if (! sel_bb_end_p (insn
)
647 || (single_succ_p (bb
)
648 && single_pred_p (single_succ (bb
))))
652 succ
= (sel_bb_end_p (insn
)
653 ? sel_bb_head (single_succ (bb
))
656 if (INSN_SEQNO (succ
) > 0
657 && INSN_SEQNO (succ
) <= orig_max_seqno
658 && INSN_SCHED_TIMES (succ
) <= 0)
660 FENCE_INSN (fence
) = succ
;
661 move_fence_to_fences (old_fences
, new_fences
);
663 if (sched_verbose
>= 1)
664 sel_print ("Fence %d continues as %d[%d] (state continue)\n",
665 INSN_UID (insn
), INSN_UID (succ
), BLOCK_NUM (succ
));
670 /* Otherwise copy fence's structures to (possibly) multiple successors. */
671 FOR_EACH_SUCC_1 (succ
, si
, insn
, SUCCS_NORMAL
| SUCCS_SKIP_TO_LOOP_EXITS
)
673 int seqno
= INSN_SEQNO (succ
);
675 if (seqno
> 0 && seqno
<= orig_max_seqno
676 && (pipelining_p
|| INSN_SCHED_TIMES (succ
) <= 0))
678 bool b
= (in_same_ebb_p (insn
, succ
)
679 || in_fallthru_bb_p (insn
, succ
));
681 if (sched_verbose
>= 1)
682 sel_print ("Fence %d continues as %d[%d] (state %s)\n",
683 INSN_UID (insn
), INSN_UID (succ
),
684 BLOCK_NUM (succ
), b
? "continue" : "reset");
687 add_dirty_fence_to_fences (new_fences
, succ
, fence
);
690 /* Mark block of the SUCC as head of the new ebb. */
691 bitmap_set_bit (forced_ebb_heads
, BLOCK_NUM (succ
));
692 add_clean_fence_to_fences (new_fences
, succ
, fence
);
699 /* Functions to support substitution. */
701 /* Returns whether INSN with dependence status DS is eligible for
702 substitution, i.e. it's a copy operation x := y, and RHS that is
703 moved up through this insn should be substituted. */
705 can_substitute_through_p (insn_t insn
, ds_t ds
)
707 /* We can substitute only true dependencies. */
708 if ((ds
& DEP_OUTPUT
)
711 || ! INSN_LHS (insn
))
714 /* Now we just need to make sure the INSN_RHS consists of only one
716 if (REG_P (INSN_LHS (insn
))
717 && REG_P (INSN_RHS (insn
)))
722 /* Substitute all occurrences of INSN's destination in EXPR' vinsn with INSN's
723 source (if INSN is eligible for substitution). Returns TRUE if
724 substitution was actually performed, FALSE otherwise. Substitution might
725 be not performed because it's either EXPR' vinsn doesn't contain INSN's
726 destination or the resulting insn is invalid for the target machine.
727 When UNDO is true, perform unsubstitution instead (the difference is in
728 the part of rtx on which validate_replace_rtx is called). */
730 substitute_reg_in_expr (expr_t expr
, insn_t insn
, bool undo
)
734 vinsn_t
*vi
= &EXPR_VINSN (expr
);
735 bool has_rhs
= VINSN_RHS (*vi
) != NULL
;
738 /* Do not try to replace in SET_DEST. Although we'll choose new
739 register for the RHS, we don't want to change RHS' original reg.
740 If the insn is not SET, we may still be able to substitute something
741 in it, and if we're here (don't have deps), it doesn't write INSN's
745 : &PATTERN (VINSN_INSN_RTX (*vi
)));
746 old
= undo
? INSN_RHS (insn
) : INSN_LHS (insn
);
748 /* Substitute if INSN has a form of x:=y and LHS(INSN) occurs in *VI. */
749 if (rtx_ok_for_substitution_p (old
, *where
))
754 /* We should copy these rtxes before substitution. */
755 new_rtx
= copy_rtx (undo
? INSN_LHS (insn
) : INSN_RHS (insn
));
756 new_insn
= create_copy_of_insn_rtx (VINSN_INSN_RTX (*vi
));
758 /* Where we'll replace.
759 WHERE_REPLACE should point inside NEW_INSN, so INSN_RHS couldn't be
760 used instead of SET_SRC. */
761 where_replace
= (has_rhs
762 ? &SET_SRC (PATTERN (new_insn
))
763 : &PATTERN (new_insn
));
766 = validate_replace_rtx_part_nosimplify (old
, new_rtx
, where_replace
,
769 /* ??? Actually, constrain_operands result depends upon choice of
770 destination register. E.g. if we allow single register to be an rhs,
771 and if we try to move dx=ax(as rhs) through ax=dx, we'll result
772 in invalid insn dx=dx, so we'll loose this rhs here.
773 Just can't come up with significant testcase for this, so just
774 leaving it for now. */
777 change_vinsn_in_expr (expr
,
778 create_vinsn_from_insn_rtx (new_insn
, false));
780 /* Do not allow clobbering the address register of speculative
782 if ((EXPR_SPEC_DONE_DS (expr
) & SPECULATIVE
)
783 && register_unavailable_p (VINSN_REG_USES (EXPR_VINSN (expr
)),
784 expr_dest_reg (expr
)))
785 EXPR_TARGET_AVAILABLE (expr
) = false;
796 /* Return the number of places WHAT appears within WHERE.
797 Bail out when we found a reference occupying several hard registers. */
799 count_occurrences_equiv (const_rtx what
, const_rtx where
)
802 subrtx_iterator::array_type array
;
803 FOR_EACH_SUBRTX (iter
, array
, where
, NONCONST
)
806 if (REG_P (x
) && REGNO (x
) == REGNO (what
))
808 /* Bail out if mode is different or more than one register is
810 if (GET_MODE (x
) != GET_MODE (what
) || REG_NREGS (x
) > 1)
814 else if (GET_CODE (x
) == SUBREG
815 && (!REG_P (SUBREG_REG (x
))
816 || REGNO (SUBREG_REG (x
)) == REGNO (what
)))
817 /* ??? Do not support substituting regs inside subregs. In that case,
818 simplify_subreg will be called by validate_replace_rtx, and
819 unsubstitution will fail later. */
825 /* Returns TRUE if WHAT is found in WHERE rtx tree. */
827 rtx_ok_for_substitution_p (rtx what
, rtx where
)
829 return (count_occurrences_equiv (what
, where
) > 0);
833 /* Functions to support register renaming. */
835 /* Substitute VI's set source with REGNO. Returns newly created pattern
836 that has REGNO as its source. */
838 create_insn_rtx_with_rhs (vinsn_t vi
, rtx rhs_rtx
)
844 lhs_rtx
= copy_rtx (VINSN_LHS (vi
));
846 pattern
= gen_rtx_SET (lhs_rtx
, rhs_rtx
);
847 insn_rtx
= create_insn_rtx_from_pattern (pattern
, NULL_RTX
);
852 /* Returns whether INSN's src can be replaced with register number
853 NEW_SRC_REG. E.g. the following insn is valid for i386:
855 (insn:HI 2205 6585 2207 727 ../../gcc/libiberty/regex.c:3337
856 (set (mem/s:QI (plus:SI (plus:SI (reg/f:SI 7 sp)
857 (reg:SI 0 ax [orig:770 c1 ] [770]))
858 (const_int 288 [0x120])) [0 str S1 A8])
859 (const_int 0 [0x0])) 43 {*movqi_1} (nil)
862 But if we change (const_int 0 [0x0]) to (reg:QI 4 si), it will be invalid
863 because of operand constraints:
865 (define_insn "*movqi_1"
866 [(set (match_operand:QI 0 "nonimmediate_operand" "=q,q ,q ,r,r ,?r,m")
867 (match_operand:QI 1 "general_operand" " q,qn,qm,q,rn,qm,qn")
870 So do constrain_operands here, before choosing NEW_SRC_REG as best
874 replace_src_with_reg_ok_p (insn_t insn
, rtx new_src_reg
)
876 vinsn_t vi
= INSN_VINSN (insn
);
881 gcc_assert (VINSN_SEPARABLE_P (vi
));
883 get_dest_and_mode (insn
, &dst_loc
, &mode
);
884 gcc_assert (mode
== GET_MODE (new_src_reg
));
886 if (REG_P (dst_loc
) && REGNO (new_src_reg
) == REGNO (dst_loc
))
889 /* See whether SET_SRC can be replaced with this register. */
890 validate_change (insn
, &SET_SRC (PATTERN (insn
)), new_src_reg
, 1);
891 res
= verify_changes (0);
897 /* Returns whether INSN still be valid after replacing it's DEST with
900 replace_dest_with_reg_ok_p (insn_t insn
, rtx new_reg
)
902 vinsn_t vi
= INSN_VINSN (insn
);
905 /* We should deal here only with separable insns. */
906 gcc_assert (VINSN_SEPARABLE_P (vi
));
907 gcc_assert (GET_MODE (VINSN_LHS (vi
)) == GET_MODE (new_reg
));
909 /* See whether SET_DEST can be replaced with this register. */
910 validate_change (insn
, &SET_DEST (PATTERN (insn
)), new_reg
, 1);
911 res
= verify_changes (0);
917 /* Create a pattern with rhs of VI and lhs of LHS_RTX. */
919 create_insn_rtx_with_lhs (vinsn_t vi
, rtx lhs_rtx
)
925 rhs_rtx
= copy_rtx (VINSN_RHS (vi
));
927 pattern
= gen_rtx_SET (lhs_rtx
, rhs_rtx
);
928 insn_rtx
= create_insn_rtx_from_pattern (pattern
, NULL_RTX
);
933 /* Substitute lhs in the given expression EXPR for the register with number
934 NEW_REGNO. SET_DEST may be arbitrary rtx, not only register. */
936 replace_dest_with_reg_in_expr (expr_t expr
, rtx new_reg
)
941 insn_rtx
= create_insn_rtx_with_lhs (EXPR_VINSN (expr
), new_reg
);
942 vinsn
= create_vinsn_from_insn_rtx (insn_rtx
, false);
944 change_vinsn_in_expr (expr
, vinsn
);
945 EXPR_WAS_RENAMED (expr
) = 1;
946 EXPR_TARGET_AVAILABLE (expr
) = 1;
949 /* Returns whether VI writes either one of the USED_REGS registers or,
950 if a register is a hard one, one of the UNAVAILABLE_HARD_REGS registers. */
952 vinsn_writes_one_of_regs_p (vinsn_t vi
, regset used_regs
,
953 HARD_REG_SET unavailable_hard_regs
)
956 reg_set_iterator rsi
;
958 EXECUTE_IF_SET_IN_REG_SET (VINSN_REG_SETS (vi
), 0, regno
, rsi
)
960 if (REGNO_REG_SET_P (used_regs
, regno
))
962 if (HARD_REGISTER_NUM_P (regno
)
963 && TEST_HARD_REG_BIT (unavailable_hard_regs
, regno
))
967 EXECUTE_IF_SET_IN_REG_SET (VINSN_REG_CLOBBERS (vi
), 0, regno
, rsi
)
969 if (REGNO_REG_SET_P (used_regs
, regno
))
971 if (HARD_REGISTER_NUM_P (regno
)
972 && TEST_HARD_REG_BIT (unavailable_hard_regs
, regno
))
979 /* Returns register class of the output register in INSN.
980 Returns NO_REGS for call insns because some targets have constraints on
981 destination register of a call insn.
983 Code adopted from regrename.c::build_def_use. */
984 static enum reg_class
985 get_reg_class (rtx_insn
*insn
)
989 extract_constrain_insn (insn
);
990 preprocess_constraints (insn
);
991 n_ops
= recog_data
.n_operands
;
993 const operand_alternative
*op_alt
= which_op_alt ();
994 if (asm_noperands (PATTERN (insn
)) > 0)
996 for (i
= 0; i
< n_ops
; i
++)
997 if (recog_data
.operand_type
[i
] == OP_OUT
)
999 rtx
*loc
= recog_data
.operand_loc
[i
];
1001 enum reg_class cl
= alternative_class (op_alt
, i
);
1004 && REGNO (op
) == ORIGINAL_REGNO (op
))
1010 else if (!CALL_P (insn
))
1012 for (i
= 0; i
< n_ops
+ recog_data
.n_dups
; i
++)
1014 int opn
= i
< n_ops
? i
: recog_data
.dup_num
[i
- n_ops
];
1015 enum reg_class cl
= alternative_class (op_alt
, opn
);
1017 if (recog_data
.operand_type
[opn
] == OP_OUT
||
1018 recog_data
.operand_type
[opn
] == OP_INOUT
)
1024 (insn (set (reg:CCZ 17 flags) (compare:CCZ ...)))
1025 may result in returning NO_REGS, cause flags is written implicitly through
1026 CMP insn, which has no OP_OUT | OP_INOUT operands. */
1030 /* Calculate HARD_REGNO_RENAME_OK data for REGNO. */
1032 init_hard_regno_rename (int regno
)
1036 SET_HARD_REG_BIT (sel_hrd
.regs_for_rename
[regno
], regno
);
1038 for (cur_reg
= 0; cur_reg
< FIRST_PSEUDO_REGISTER
; cur_reg
++)
1040 /* We are not interested in renaming in other regs. */
1041 if (!TEST_HARD_REG_BIT (sel_hrd
.regs_ever_used
, cur_reg
))
1044 if (HARD_REGNO_RENAME_OK (regno
, cur_reg
))
1045 SET_HARD_REG_BIT (sel_hrd
.regs_for_rename
[regno
], cur_reg
);
1049 /* A wrapper around HARD_REGNO_RENAME_OK that will look into the hard regs
1052 sel_hard_regno_rename_ok (int from ATTRIBUTE_UNUSED
, int to ATTRIBUTE_UNUSED
)
1054 /* Check whether this is all calculated. */
1055 if (TEST_HARD_REG_BIT (sel_hrd
.regs_for_rename
[from
], from
))
1056 return TEST_HARD_REG_BIT (sel_hrd
.regs_for_rename
[from
], to
);
1058 init_hard_regno_rename (from
);
1060 return TEST_HARD_REG_BIT (sel_hrd
.regs_for_rename
[from
], to
);
1063 /* Calculate set of registers that are capable of holding MODE. */
1065 init_regs_for_mode (machine_mode mode
)
1069 CLEAR_HARD_REG_SET (sel_hrd
.regs_for_mode
[mode
]);
1070 CLEAR_HARD_REG_SET (sel_hrd
.regs_for_call_clobbered
[mode
]);
1072 for (cur_reg
= 0; cur_reg
< FIRST_PSEUDO_REGISTER
; cur_reg
++)
1077 /* See whether it accepts all modes that occur in
1079 if (!targetm
.hard_regno_mode_ok (cur_reg
, mode
))
1082 nregs
= hard_regno_nregs (cur_reg
, mode
);
1084 for (i
= nregs
- 1; i
>= 0; --i
)
1085 if (fixed_regs
[cur_reg
+ i
]
1086 || global_regs
[cur_reg
+ i
]
1087 /* Can't use regs which aren't saved by
1089 || !TEST_HARD_REG_BIT (sel_hrd
.regs_ever_used
, cur_reg
+ i
)
1090 /* Can't use regs with non-null REG_BASE_VALUE, because adjusting
1091 it affects aliasing globally and invalidates all AV sets. */
1092 || get_reg_base_value (cur_reg
+ i
)
1093 #ifdef LEAF_REGISTERS
1094 /* We can't use a non-leaf register if we're in a
1097 && !LEAF_REGISTERS
[cur_reg
+ i
])
1105 if (targetm
.hard_regno_call_part_clobbered (NULL
, cur_reg
, mode
))
1106 SET_HARD_REG_BIT (sel_hrd
.regs_for_call_clobbered
[mode
],
1109 /* If the CUR_REG passed all the checks above,
1111 SET_HARD_REG_BIT (sel_hrd
.regs_for_mode
[mode
], cur_reg
);
1114 sel_hrd
.regs_for_mode_ok
[mode
] = true;
1117 /* Init all register sets gathered in HRD. */
1119 init_hard_regs_data (void)
1124 CLEAR_HARD_REG_SET (sel_hrd
.regs_ever_used
);
1125 for (cur_reg
= 0; cur_reg
< FIRST_PSEUDO_REGISTER
; cur_reg
++)
1126 if (df_regs_ever_live_p (cur_reg
) || call_used_regs
[cur_reg
])
1127 SET_HARD_REG_BIT (sel_hrd
.regs_ever_used
, cur_reg
);
1129 /* Initialize registers that are valid based on mode when this is
1131 for (cur_mode
= 0; cur_mode
< NUM_MACHINE_MODES
; cur_mode
++)
1132 sel_hrd
.regs_for_mode_ok
[cur_mode
] = false;
1134 /* Mark that all HARD_REGNO_RENAME_OK is not calculated. */
1135 for (cur_reg
= 0; cur_reg
< FIRST_PSEUDO_REGISTER
; cur_reg
++)
1136 CLEAR_HARD_REG_SET (sel_hrd
.regs_for_rename
[cur_reg
]);
1139 CLEAR_HARD_REG_SET (sel_hrd
.stack_regs
);
1141 for (cur_reg
= FIRST_STACK_REG
; cur_reg
<= LAST_STACK_REG
; cur_reg
++)
1142 SET_HARD_REG_BIT (sel_hrd
.stack_regs
, cur_reg
);
1146 /* Mark hardware regs in REG_RENAME_P that are not suitable
1147 for renaming rhs in INSN due to hardware restrictions (register class,
1148 modes compatibility etc). This doesn't affect original insn's dest reg,
1149 if it isn't in USED_REGS. DEF is a definition insn of rhs for which the
1150 destination register is sought. LHS (DEF->ORIG_INSN) may be REG or MEM.
1151 Registers that are in used_regs are always marked in
1152 unavailable_hard_regs as well. */
1155 mark_unavailable_hard_regs (def_t def
, struct reg_rename
*reg_rename_p
,
1156 regset used_regs ATTRIBUTE_UNUSED
)
1159 enum reg_class cl
= NO_REGS
;
1161 unsigned cur_reg
, regno
;
1162 hard_reg_set_iterator hrsi
;
1164 gcc_assert (GET_CODE (PATTERN (def
->orig_insn
)) == SET
);
1165 gcc_assert (reg_rename_p
);
1167 orig_dest
= SET_DEST (PATTERN (def
->orig_insn
));
1169 /* We have decided not to rename 'mem = something;' insns, as 'something'
1170 is usually a register. */
1171 if (!REG_P (orig_dest
))
1174 regno
= REGNO (orig_dest
);
1176 /* If before reload, don't try to work with pseudos. */
1177 if (!reload_completed
&& !HARD_REGISTER_NUM_P (regno
))
1180 if (reload_completed
)
1181 cl
= get_reg_class (def
->orig_insn
);
1183 /* Stop if the original register is one of the fixed_regs, global_regs or
1184 frame pointer, or we could not discover its class. */
1185 if (fixed_regs
[regno
]
1186 || global_regs
[regno
]
1187 || (!HARD_FRAME_POINTER_IS_FRAME_POINTER
&& frame_pointer_needed
1188 && regno
== HARD_FRAME_POINTER_REGNUM
)
1189 || (HARD_FRAME_POINTER_IS_FRAME_POINTER
&& frame_pointer_needed
1190 && regno
== FRAME_POINTER_REGNUM
)
1191 || (reload_completed
&& cl
== NO_REGS
))
1193 SET_HARD_REG_SET (reg_rename_p
->unavailable_hard_regs
);
1195 /* Give a chance for original register, if it isn't in used_regs. */
1196 if (!def
->crosses_call
)
1197 CLEAR_HARD_REG_BIT (reg_rename_p
->unavailable_hard_regs
, regno
);
1202 /* If something allocated on stack in this function, mark frame pointer
1203 register unavailable, considering also modes.
1204 FIXME: it is enough to do this once per all original defs. */
1205 if (frame_pointer_needed
)
1207 add_to_hard_reg_set (®_rename_p
->unavailable_hard_regs
,
1208 Pmode
, FRAME_POINTER_REGNUM
);
1210 if (!HARD_FRAME_POINTER_IS_FRAME_POINTER
)
1211 add_to_hard_reg_set (®_rename_p
->unavailable_hard_regs
,
1212 Pmode
, HARD_FRAME_POINTER_REGNUM
);
1216 /* For the stack registers the presence of FIRST_STACK_REG in USED_REGS
1217 is equivalent to as if all stack regs were in this set.
1218 I.e. no stack register can be renamed, and even if it's an original
1219 register here we make sure it won't be lifted over it's previous def
1220 (it's previous def will appear as if it's a FIRST_STACK_REG def.
1221 The HARD_REGNO_RENAME_OK covers other cases in condition below. */
1222 if (IN_RANGE (REGNO (orig_dest
), FIRST_STACK_REG
, LAST_STACK_REG
)
1223 && REGNO_REG_SET_P (used_regs
, FIRST_STACK_REG
))
1224 IOR_HARD_REG_SET (reg_rename_p
->unavailable_hard_regs
,
1225 sel_hrd
.stack_regs
);
1228 /* If there's a call on this path, make regs from call_used_reg_set
1230 if (def
->crosses_call
)
1231 IOR_HARD_REG_SET (reg_rename_p
->unavailable_hard_regs
,
1234 /* Stop here before reload: we need FRAME_REGS, STACK_REGS, and crosses_call,
1235 but not register classes. */
1236 if (!reload_completed
)
1239 /* Leave regs as 'available' only from the current
1241 reg_rename_p
->available_for_renaming
= reg_class_contents
[cl
];
1243 mode
= GET_MODE (orig_dest
);
1245 /* Leave only registers available for this mode. */
1246 if (!sel_hrd
.regs_for_mode_ok
[mode
])
1247 init_regs_for_mode (mode
);
1248 AND_HARD_REG_SET (reg_rename_p
->available_for_renaming
,
1249 sel_hrd
.regs_for_mode
[mode
]);
1251 /* Exclude registers that are partially call clobbered. */
1252 if (def
->crosses_call
1253 && !targetm
.hard_regno_call_part_clobbered (NULL
, regno
, mode
))
1254 AND_COMPL_HARD_REG_SET (reg_rename_p
->available_for_renaming
,
1255 sel_hrd
.regs_for_call_clobbered
[mode
]);
1257 /* Leave only those that are ok to rename. */
1258 EXECUTE_IF_SET_IN_HARD_REG_SET (reg_rename_p
->available_for_renaming
,
1264 nregs
= hard_regno_nregs (cur_reg
, mode
);
1265 gcc_assert (nregs
> 0);
1267 for (i
= nregs
- 1; i
>= 0; --i
)
1268 if (! sel_hard_regno_rename_ok (regno
+ i
, cur_reg
+ i
))
1272 CLEAR_HARD_REG_BIT (reg_rename_p
->available_for_renaming
,
1276 AND_COMPL_HARD_REG_SET (reg_rename_p
->available_for_renaming
,
1277 reg_rename_p
->unavailable_hard_regs
);
1279 /* Regno is always ok from the renaming part of view, but it really
1280 could be in *unavailable_hard_regs already, so set it here instead
1282 SET_HARD_REG_BIT (reg_rename_p
->available_for_renaming
, regno
);
1285 /* reg_rename_tick[REG1] > reg_rename_tick[REG2] if REG1 was chosen as the
1286 best register more recently than REG2. */
1287 static int reg_rename_tick
[FIRST_PSEUDO_REGISTER
];
1289 /* Indicates the number of times renaming happened before the current one. */
1290 static int reg_rename_this_tick
;
1292 /* Choose the register among free, that is suitable for storing
1295 ORIGINAL_INSNS is the list of insns where the operation (rhs)
1296 originally appears. There could be multiple original operations
1297 for single rhs since we moving it up and merging along different
1300 Some code is adapted from regrename.c (regrename_optimize).
1301 If original register is available, function returns it.
1302 Otherwise it performs the checks, so the new register should
1303 comply with the following:
1304 - it should not violate any live ranges (such registers are in
1305 REG_RENAME_P->available_for_renaming set);
1306 - it should not be in the HARD_REGS_USED regset;
1307 - it should be in the class compatible with original uses;
1308 - it should not be clobbered through reference with different mode;
1309 - if we're in the leaf function, then the new register should
1310 not be in the LEAF_REGISTERS;
1313 If several registers meet the conditions, the register with smallest
1314 tick is returned to achieve more even register allocation.
1316 If original register seems to be ok, we set *IS_ORIG_REG_P_PTR to true.
1318 If no register satisfies the above conditions, NULL_RTX is returned. */
1320 choose_best_reg_1 (HARD_REG_SET hard_regs_used
,
1321 struct reg_rename
*reg_rename_p
,
1322 def_list_t original_insns
, bool *is_orig_reg_p_ptr
)
1326 machine_mode mode
= VOIDmode
;
1327 unsigned regno
, i
, n
;
1328 hard_reg_set_iterator hrsi
;
1329 def_list_iterator di
;
1332 /* If original register is available, return it. */
1333 *is_orig_reg_p_ptr
= true;
1335 FOR_EACH_DEF (def
, di
, original_insns
)
1337 rtx orig_dest
= SET_DEST (PATTERN (def
->orig_insn
));
1339 gcc_assert (REG_P (orig_dest
));
1341 /* Check that all original operations have the same mode.
1342 This is done for the next loop; if we'd return from this
1343 loop, we'd check only part of them, but in this case
1344 it doesn't matter. */
1345 if (mode
== VOIDmode
)
1346 mode
= GET_MODE (orig_dest
);
1347 gcc_assert (mode
== GET_MODE (orig_dest
));
1349 regno
= REGNO (orig_dest
);
1350 for (i
= 0, n
= REG_NREGS (orig_dest
); i
< n
; i
++)
1351 if (TEST_HARD_REG_BIT (hard_regs_used
, regno
+ i
))
1354 /* All hard registers are available. */
1357 gcc_assert (mode
!= VOIDmode
);
1359 /* Hard registers should not be shared. */
1360 return gen_rtx_REG (mode
, regno
);
1364 *is_orig_reg_p_ptr
= false;
1367 /* Among all available regs choose the register that was
1368 allocated earliest. */
1369 EXECUTE_IF_SET_IN_HARD_REG_SET (reg_rename_p
->available_for_renaming
,
1371 if (! TEST_HARD_REG_BIT (hard_regs_used
, cur_reg
))
1373 /* Check that all hard regs for mode are available. */
1374 for (i
= 1, n
= hard_regno_nregs (cur_reg
, mode
); i
< n
; i
++)
1375 if (TEST_HARD_REG_BIT (hard_regs_used
, cur_reg
+ i
)
1376 || !TEST_HARD_REG_BIT (reg_rename_p
->available_for_renaming
,
1383 /* All hard registers are available. */
1384 if (best_new_reg
< 0
1385 || reg_rename_tick
[cur_reg
] < reg_rename_tick
[best_new_reg
])
1387 best_new_reg
= cur_reg
;
1389 /* Return immediately when we know there's no better reg. */
1390 if (! reg_rename_tick
[best_new_reg
])
1395 if (best_new_reg
>= 0)
1397 /* Use the check from the above loop. */
1398 gcc_assert (mode
!= VOIDmode
);
1399 return gen_rtx_REG (mode
, best_new_reg
);
1405 /* A wrapper around choose_best_reg_1 () to verify that we make correct
1406 assumptions about available registers in the function. */
1408 choose_best_reg (HARD_REG_SET hard_regs_used
, struct reg_rename
*reg_rename_p
,
1409 def_list_t original_insns
, bool *is_orig_reg_p_ptr
)
1411 rtx best_reg
= choose_best_reg_1 (hard_regs_used
, reg_rename_p
,
1412 original_insns
, is_orig_reg_p_ptr
);
1414 /* FIXME loop over hard_regno_nregs here. */
1415 gcc_assert (best_reg
== NULL_RTX
1416 || TEST_HARD_REG_BIT (sel_hrd
.regs_ever_used
, REGNO (best_reg
)));
1421 /* Choose the pseudo register for storing rhs value. As this is supposed
1422 to work before reload, we return either the original register or make
1423 the new one. The parameters are the same that in choose_nest_reg_1
1424 functions, except that USED_REGS may contain pseudos.
1425 If we work with hard regs, check also REG_RENAME_P->UNAVAILABLE_HARD_REGS.
1427 TODO: take into account register pressure while doing this. Up to this
1428 moment, this function would never return NULL for pseudos, but we should
1429 not rely on this. */
1431 choose_best_pseudo_reg (regset used_regs
,
1432 struct reg_rename
*reg_rename_p
,
1433 def_list_t original_insns
, bool *is_orig_reg_p_ptr
)
1435 def_list_iterator i
;
1437 machine_mode mode
= VOIDmode
;
1438 bool bad_hard_regs
= false;
1440 /* We should not use this after reload. */
1441 gcc_assert (!reload_completed
);
1443 /* If original register is available, return it. */
1444 *is_orig_reg_p_ptr
= true;
1446 FOR_EACH_DEF (def
, i
, original_insns
)
1448 rtx dest
= SET_DEST (PATTERN (def
->orig_insn
));
1451 gcc_assert (REG_P (dest
));
1453 /* Check that all original operations have the same mode. */
1454 if (mode
== VOIDmode
)
1455 mode
= GET_MODE (dest
);
1457 gcc_assert (mode
== GET_MODE (dest
));
1458 orig_regno
= REGNO (dest
);
1460 /* Check that nothing in used_regs intersects with orig_regno. When
1461 we have a hard reg here, still loop over hard_regno_nregs. */
1462 if (HARD_REGISTER_NUM_P (orig_regno
))
1465 for (j
= 0, n
= REG_NREGS (dest
); j
< n
; j
++)
1466 if (REGNO_REG_SET_P (used_regs
, orig_regno
+ j
))
1473 if (REGNO_REG_SET_P (used_regs
, orig_regno
))
1476 if (HARD_REGISTER_NUM_P (orig_regno
))
1478 gcc_assert (df_regs_ever_live_p (orig_regno
));
1480 /* For hard registers, we have to check hardware imposed
1481 limitations (frame/stack registers, calls crossed). */
1482 if (!TEST_HARD_REG_BIT (reg_rename_p
->unavailable_hard_regs
,
1485 /* Don't let register cross a call if it doesn't already
1486 cross one. This condition is written in accordance with
1487 that in sched-deps.c sched_analyze_reg(). */
1488 if (!reg_rename_p
->crosses_call
1489 || REG_N_CALLS_CROSSED (orig_regno
) > 0)
1490 return gen_rtx_REG (mode
, orig_regno
);
1493 bad_hard_regs
= true;
1499 *is_orig_reg_p_ptr
= false;
1501 /* We had some original hard registers that couldn't be used.
1502 Those were likely special. Don't try to create a pseudo. */
1506 /* We haven't found a register from original operations. Get a new one.
1507 FIXME: control register pressure somehow. */
1509 rtx new_reg
= gen_reg_rtx (mode
);
1511 gcc_assert (mode
!= VOIDmode
);
1513 max_regno
= max_reg_num ();
1514 maybe_extend_reg_info_p ();
1515 REG_N_CALLS_CROSSED (REGNO (new_reg
)) = reg_rename_p
->crosses_call
? 1 : 0;
1521 /* True when target of EXPR is available due to EXPR_TARGET_AVAILABLE,
1522 USED_REGS and REG_RENAME_P->UNAVAILABLE_HARD_REGS. */
1524 verify_target_availability (expr_t expr
, regset used_regs
,
1525 struct reg_rename
*reg_rename_p
)
1527 unsigned n
, i
, regno
;
1529 bool target_available
, live_available
, hard_available
;
1531 if (!REG_P (EXPR_LHS (expr
)) || EXPR_TARGET_AVAILABLE (expr
) < 0)
1534 regno
= expr_dest_regno (expr
);
1535 mode
= GET_MODE (EXPR_LHS (expr
));
1536 target_available
= EXPR_TARGET_AVAILABLE (expr
) == 1;
1537 n
= HARD_REGISTER_NUM_P (regno
) ? hard_regno_nregs (regno
, mode
) : 1;
1539 live_available
= hard_available
= true;
1540 for (i
= 0; i
< n
; i
++)
1542 if (bitmap_bit_p (used_regs
, regno
+ i
))
1543 live_available
= false;
1544 if (TEST_HARD_REG_BIT (reg_rename_p
->unavailable_hard_regs
, regno
+ i
))
1545 hard_available
= false;
1548 /* When target is not available, it may be due to hard register
1549 restrictions, e.g. crosses calls, so we check hard_available too. */
1550 if (target_available
)
1551 gcc_assert (live_available
);
1553 /* Check only if we haven't scheduled something on the previous fence,
1554 cause due to MAX_SOFTWARE_LOOKAHEAD_WINDOW_SIZE issues
1555 and having more than one fence, we may end having targ_un in a block
1556 in which successors target register is actually available.
1558 The last condition handles the case when a dependence from a call insn
1559 was created in sched-deps.c for insns with destination registers that
1560 never crossed a call before, but do cross one after our code motion.
1562 FIXME: in the latter case, we just uselessly called find_used_regs,
1563 because we can't move this expression with any other register
1565 gcc_assert (scheduled_something_on_previous_fence
|| !live_available
1567 || (!reload_completed
&& reg_rename_p
->crosses_call
1568 && REG_N_CALLS_CROSSED (regno
) == 0));
1571 /* Collect unavailable registers due to liveness for EXPR from BNDS
1572 into USED_REGS. Save additional information about available
1573 registers and unavailable due to hardware restriction registers
1574 into REG_RENAME_P structure. Save original insns into ORIGINAL_INSNS
1577 collect_unavailable_regs_from_bnds (expr_t expr
, blist_t bnds
, regset used_regs
,
1578 struct reg_rename
*reg_rename_p
,
1579 def_list_t
*original_insns
)
1581 for (; bnds
; bnds
= BLIST_NEXT (bnds
))
1584 av_set_t orig_ops
= NULL
;
1585 bnd_t bnd
= BLIST_BND (bnds
);
1587 /* If the chosen best expr doesn't belong to current boundary,
1589 if (!av_set_is_in_p (BND_AV1 (bnd
), EXPR_VINSN (expr
)))
1592 /* Put in ORIG_OPS all exprs from this boundary that became
1594 orig_ops
= find_sequential_best_exprs (bnd
, expr
, false);
1596 /* Compute used regs and OR it into the USED_REGS. */
1597 res
= find_used_regs (BND_TO (bnd
), orig_ops
, used_regs
,
1598 reg_rename_p
, original_insns
);
1600 /* FIXME: the assert is true until we'd have several boundaries. */
1602 av_set_clear (&orig_ops
);
1606 /* Return TRUE if it is possible to replace LHSes of ORIG_INSNS with BEST_REG.
1607 If BEST_REG is valid, replace LHS of EXPR with it. */
1609 try_replace_dest_reg (ilist_t orig_insns
, rtx best_reg
, expr_t expr
)
1611 /* Try whether we'll be able to generate the insn
1612 'dest := best_reg' at the place of the original operation. */
1613 for (; orig_insns
; orig_insns
= ILIST_NEXT (orig_insns
))
1615 insn_t orig_insn
= DEF_LIST_DEF (orig_insns
)->orig_insn
;
1617 gcc_assert (EXPR_SEPARABLE_P (INSN_EXPR (orig_insn
)));
1619 if (REGNO (best_reg
) != REGNO (INSN_LHS (orig_insn
))
1620 && (! replace_src_with_reg_ok_p (orig_insn
, best_reg
)
1621 || ! replace_dest_with_reg_ok_p (orig_insn
, best_reg
)))
1625 /* Make sure that EXPR has the right destination
1627 if (expr_dest_regno (expr
) != REGNO (best_reg
))
1628 replace_dest_with_reg_in_expr (expr
, best_reg
);
1630 EXPR_TARGET_AVAILABLE (expr
) = 1;
1635 /* Select and assign best register to EXPR searching from BNDS.
1636 Set *IS_ORIG_REG_P to TRUE if original register was selected.
1637 Return FALSE if no register can be chosen, which could happen when:
1638 * EXPR_SEPARABLE_P is true but we were unable to find suitable register;
1639 * EXPR_SEPARABLE_P is false but the insn sets/clobbers one of the registers
1640 that are used on the moving path. */
1642 find_best_reg_for_expr (expr_t expr
, blist_t bnds
, bool *is_orig_reg_p
)
1644 static struct reg_rename reg_rename_data
;
1647 def_list_t original_insns
= NULL
;
1650 *is_orig_reg_p
= false;
1652 /* Don't bother to do anything if this insn doesn't set any registers. */
1653 if (bitmap_empty_p (VINSN_REG_SETS (EXPR_VINSN (expr
)))
1654 && bitmap_empty_p (VINSN_REG_CLOBBERS (EXPR_VINSN (expr
))))
1657 used_regs
= get_clear_regset_from_pool ();
1658 CLEAR_HARD_REG_SET (reg_rename_data
.unavailable_hard_regs
);
1660 collect_unavailable_regs_from_bnds (expr
, bnds
, used_regs
, ®_rename_data
,
1663 /* If after reload, make sure we're working with hard regs here. */
1664 if (flag_checking
&& reload_completed
)
1666 reg_set_iterator rsi
;
1669 EXECUTE_IF_SET_IN_REG_SET (used_regs
, FIRST_PSEUDO_REGISTER
, i
, rsi
)
1673 if (EXPR_SEPARABLE_P (expr
))
1675 rtx best_reg
= NULL_RTX
;
1676 /* Check that we have computed availability of a target register
1678 verify_target_availability (expr
, used_regs
, ®_rename_data
);
1680 /* Turn everything in hard regs after reload. */
1681 if (reload_completed
)
1683 HARD_REG_SET hard_regs_used
;
1684 REG_SET_TO_HARD_REG_SET (hard_regs_used
, used_regs
);
1686 /* Join hard registers unavailable due to register class
1687 restrictions and live range intersection. */
1688 IOR_HARD_REG_SET (hard_regs_used
,
1689 reg_rename_data
.unavailable_hard_regs
);
1691 best_reg
= choose_best_reg (hard_regs_used
, ®_rename_data
,
1692 original_insns
, is_orig_reg_p
);
1695 best_reg
= choose_best_pseudo_reg (used_regs
, ®_rename_data
,
1696 original_insns
, is_orig_reg_p
);
1700 else if (*is_orig_reg_p
)
1702 /* In case of unification BEST_REG may be different from EXPR's LHS
1703 when EXPR's LHS is unavailable, and there is another LHS among
1705 reg_ok
= try_replace_dest_reg (original_insns
, best_reg
, expr
);
1709 /* Forbid renaming of low-cost insns. */
1710 if (sel_vinsn_cost (EXPR_VINSN (expr
)) < 2)
1713 reg_ok
= try_replace_dest_reg (original_insns
, best_reg
, expr
);
1718 /* If !EXPR_SCHEDULE_AS_RHS (EXPR), just make sure INSN doesn't set
1719 any of the HARD_REGS_USED set. */
1720 if (vinsn_writes_one_of_regs_p (EXPR_VINSN (expr
), used_regs
,
1721 reg_rename_data
.unavailable_hard_regs
))
1724 gcc_assert (EXPR_TARGET_AVAILABLE (expr
) <= 0);
1729 gcc_assert (EXPR_TARGET_AVAILABLE (expr
) != 0);
1733 ilist_clear (&original_insns
);
1734 return_regset_to_pool (used_regs
);
1740 /* Return true if dependence described by DS can be overcomed. */
1742 can_speculate_dep_p (ds_t ds
)
1744 if (spec_info
== NULL
)
1747 /* Leave only speculative data. */
1754 /* FIXME: make sched-deps.c produce only those non-hard dependencies,
1755 that we can overcome. */
1756 ds_t spec_mask
= spec_info
->mask
;
1758 if ((ds
& spec_mask
) != ds
)
1762 if (ds_weak (ds
) < spec_info
->data_weakness_cutoff
)
1768 /* Get a speculation check instruction.
1769 C_EXPR is a speculative expression,
1770 CHECK_DS describes speculations that should be checked,
1771 ORIG_INSN is the original non-speculative insn in the stream. */
1773 create_speculation_check (expr_t c_expr
, ds_t check_ds
, insn_t orig_insn
)
1778 basic_block recovery_block
;
1781 /* Create a recovery block if target is going to emit branchy check, or if
1782 ORIG_INSN was speculative already. */
1783 if (targetm
.sched
.needs_block_p (check_ds
)
1784 || EXPR_SPEC_DONE_DS (INSN_EXPR (orig_insn
)) != 0)
1786 recovery_block
= sel_create_recovery_block (orig_insn
);
1787 label
= BB_HEAD (recovery_block
);
1791 recovery_block
= NULL
;
1795 /* Get pattern of the check. */
1796 check_pattern
= targetm
.sched
.gen_spec_check (EXPR_INSN_RTX (c_expr
), label
,
1799 gcc_assert (check_pattern
!= NULL
);
1802 insn_rtx
= create_insn_rtx_from_pattern (check_pattern
, label
);
1804 insn
= sel_gen_insn_from_rtx_after (insn_rtx
, INSN_EXPR (orig_insn
),
1805 INSN_SEQNO (orig_insn
), orig_insn
);
1807 /* Make check to be non-speculative. */
1808 EXPR_SPEC_DONE_DS (INSN_EXPR (insn
)) = 0;
1809 INSN_SPEC_CHECKED_DS (insn
) = check_ds
;
1811 /* Decrease priority of check by difference of load/check instruction
1813 EXPR_PRIORITY (INSN_EXPR (insn
)) -= (sel_vinsn_cost (INSN_VINSN (orig_insn
))
1814 - sel_vinsn_cost (INSN_VINSN (insn
)));
1816 /* Emit copy of original insn (though with replaced target register,
1817 if needed) to the recovery block. */
1818 if (recovery_block
!= NULL
)
1822 twin_rtx
= copy_rtx (PATTERN (EXPR_INSN_RTX (c_expr
)));
1823 twin_rtx
= create_insn_rtx_from_pattern (twin_rtx
, NULL_RTX
);
1824 sel_gen_recovery_insn_from_rtx_after (twin_rtx
,
1825 INSN_EXPR (orig_insn
),
1827 bb_note (recovery_block
));
1830 /* If we've generated a data speculation check, make sure
1831 that all the bookkeeping instruction we'll create during
1832 this move_op () will allocate an ALAT entry so that the
1834 In case of control speculation we must convert C_EXPR to control
1835 speculative mode, because failing to do so will bring us an exception
1836 thrown by the non-control-speculative load. */
1837 check_ds
= ds_get_max_dep_weak (check_ds
);
1838 speculate_expr (c_expr
, check_ds
);
1843 /* True when INSN is a "regN = regN" copy. */
1845 identical_copy_p (rtx_insn
*insn
)
1849 pat
= PATTERN (insn
);
1851 if (GET_CODE (pat
) != SET
)
1854 lhs
= SET_DEST (pat
);
1858 rhs
= SET_SRC (pat
);
1862 return REGNO (lhs
) == REGNO (rhs
);
1865 /* Undo all transformations on *AV_PTR that were done when
1866 moving through INSN. */
1868 undo_transformations (av_set_t
*av_ptr
, rtx_insn
*insn
)
1870 av_set_iterator av_iter
;
1872 av_set_t new_set
= NULL
;
1874 /* First, kill any EXPR that uses registers set by an insn. This is
1875 required for correctness. */
1876 FOR_EACH_EXPR_1 (expr
, av_iter
, av_ptr
)
1877 if (!sched_insns_conditions_mutex_p (insn
, EXPR_INSN_RTX (expr
))
1878 && bitmap_intersect_p (INSN_REG_SETS (insn
),
1879 VINSN_REG_USES (EXPR_VINSN (expr
)))
1880 /* When an insn looks like 'r1 = r1', we could substitute through
1881 it, but the above condition will still hold. This happened with
1882 gcc.c-torture/execute/961125-1.c. */
1883 && !identical_copy_p (insn
))
1885 if (sched_verbose
>= 6)
1886 sel_print ("Expr %d removed due to use/set conflict\n",
1887 INSN_UID (EXPR_INSN_RTX (expr
)));
1888 av_set_iter_remove (&av_iter
);
1891 /* Undo transformations looking at the history vector. */
1892 FOR_EACH_EXPR (expr
, av_iter
, *av_ptr
)
1894 int index
= find_in_history_vect (EXPR_HISTORY_OF_CHANGES (expr
),
1895 insn
, EXPR_VINSN (expr
), true);
1899 expr_history_def
*phist
;
1901 phist
= &EXPR_HISTORY_OF_CHANGES (expr
)[index
];
1903 switch (phist
->type
)
1905 case TRANS_SPECULATION
:
1907 ds_t old_ds
, new_ds
;
1909 /* Compute the difference between old and new speculative
1910 statuses: that's what we need to check.
1911 Earlier we used to assert that the status will really
1912 change. This no longer works because only the probability
1913 bits in the status may have changed during compute_av_set,
1914 and in the case of merging different probabilities of the
1915 same speculative status along different paths we do not
1916 record this in the history vector. */
1917 old_ds
= phist
->spec_ds
;
1918 new_ds
= EXPR_SPEC_DONE_DS (expr
);
1920 old_ds
&= SPECULATIVE
;
1921 new_ds
&= SPECULATIVE
;
1924 EXPR_SPEC_TO_CHECK_DS (expr
) |= new_ds
;
1927 case TRANS_SUBSTITUTION
:
1929 expr_def _tmp_expr
, *tmp_expr
= &_tmp_expr
;
1933 new_vi
= phist
->old_expr_vinsn
;
1935 gcc_assert (VINSN_SEPARABLE_P (new_vi
)
1936 == EXPR_SEPARABLE_P (expr
));
1937 copy_expr (tmp_expr
, expr
);
1939 if (vinsn_equal_p (phist
->new_expr_vinsn
,
1940 EXPR_VINSN (tmp_expr
)))
1941 change_vinsn_in_expr (tmp_expr
, new_vi
);
1943 /* This happens when we're unsubstituting on a bookkeeping
1944 copy, which was in turn substituted. The history is wrong
1945 in this case. Do it the hard way. */
1946 add
= substitute_reg_in_expr (tmp_expr
, insn
, true);
1948 av_set_add (&new_set
, tmp_expr
);
1949 clear_expr (tmp_expr
);
1959 av_set_union_and_clear (av_ptr
, &new_set
, NULL
);
1963 /* Moveup_* helpers for code motion and computing av sets. */
1965 /* Propagates EXPR inside an insn group through THROUGH_INSN.
1966 The difference from the below function is that only substitution is
1968 static enum MOVEUP_EXPR_CODE
1969 moveup_expr_inside_insn_group (expr_t expr
, insn_t through_insn
)
1971 vinsn_t vi
= EXPR_VINSN (expr
);
1975 /* Do this only inside insn group. */
1976 gcc_assert (INSN_SCHED_CYCLE (through_insn
) > 0);
1978 full_ds
= has_dependence_p (expr
, through_insn
, &has_dep_p
);
1980 return MOVEUP_EXPR_SAME
;
1982 /* Substitution is the possible choice in this case. */
1983 if (has_dep_p
[DEPS_IN_RHS
])
1985 /* Can't substitute UNIQUE VINSNs. */
1986 gcc_assert (!VINSN_UNIQUE_P (vi
));
1988 if (can_substitute_through_p (through_insn
,
1989 has_dep_p
[DEPS_IN_RHS
])
1990 && substitute_reg_in_expr (expr
, through_insn
, false))
1992 EXPR_WAS_SUBSTITUTED (expr
) = true;
1993 return MOVEUP_EXPR_CHANGED
;
1996 /* Don't care about this, as even true dependencies may be allowed
1997 in an insn group. */
1998 return MOVEUP_EXPR_SAME
;
2001 /* This can catch output dependencies in COND_EXECs. */
2002 if (has_dep_p
[DEPS_IN_INSN
])
2003 return MOVEUP_EXPR_NULL
;
2005 /* This is either an output or an anti dependence, which usually have
2006 a zero latency. Allow this here, if we'd be wrong, tick_check_p
2008 gcc_assert (has_dep_p
[DEPS_IN_LHS
]);
2009 return MOVEUP_EXPR_AS_RHS
;
2012 /* True when a trapping EXPR cannot be moved through THROUGH_INSN. */
2013 #define CANT_MOVE_TRAPPING(expr, through_insn) \
2014 (VINSN_MAY_TRAP_P (EXPR_VINSN (expr)) \
2015 && !sel_insn_has_single_succ_p ((through_insn), SUCCS_ALL) \
2016 && !sel_insn_is_speculation_check (through_insn))
2018 /* True when a conflict on a target register was found during moveup_expr. */
2019 static bool was_target_conflict
= false;
2021 /* Return true when moving a debug INSN across THROUGH_INSN will
2022 create a bookkeeping block. We don't want to create such blocks,
2023 for they would cause codegen differences between compilations with
2024 and without debug info. */
2027 moving_insn_creates_bookkeeping_block_p (insn_t insn
,
2028 insn_t through_insn
)
2030 basic_block bbi
, bbt
;
2032 edge_iterator ei1
, ei2
;
2034 if (!bookkeeping_can_be_created_if_moved_through_p (through_insn
))
2036 if (sched_verbose
>= 9)
2037 sel_print ("no bookkeeping required: ");
2041 bbi
= BLOCK_FOR_INSN (insn
);
2043 if (EDGE_COUNT (bbi
->preds
) == 1)
2045 if (sched_verbose
>= 9)
2046 sel_print ("only one pred edge: ");
2050 bbt
= BLOCK_FOR_INSN (through_insn
);
2052 FOR_EACH_EDGE (e1
, ei1
, bbt
->succs
)
2054 FOR_EACH_EDGE (e2
, ei2
, bbi
->preds
)
2056 if (find_block_for_bookkeeping (e1
, e2
, TRUE
))
2058 if (sched_verbose
>= 9)
2059 sel_print ("found existing block: ");
2065 if (sched_verbose
>= 9)
2066 sel_print ("would create bookkeeping block: ");
2071 /* Return true when the conflict with newly created implicit clobbers
2072 between EXPR and THROUGH_INSN is found because of renaming. */
2074 implicit_clobber_conflict_p (insn_t through_insn
, expr_t expr
)
2079 hard_reg_set_iterator hrsi
;
2083 /* Make a new pseudo register. */
2084 reg
= gen_reg_rtx (GET_MODE (EXPR_LHS (expr
)));
2085 max_regno
= max_reg_num ();
2086 maybe_extend_reg_info_p ();
2088 /* Validate a change and bail out early. */
2089 insn
= EXPR_INSN_RTX (expr
);
2090 validate_change (insn
, &SET_DEST (PATTERN (insn
)), reg
, true);
2091 valid
= verify_changes (0);
2095 if (sched_verbose
>= 6)
2096 sel_print ("implicit clobbers failed validation, ");
2100 /* Make a new insn with it. */
2101 rhs
= copy_rtx (VINSN_RHS (EXPR_VINSN (expr
)));
2102 pat
= gen_rtx_SET (reg
, rhs
);
2104 insn
= emit_insn (pat
);
2107 /* Calculate implicit clobbers. */
2108 extract_insn (insn
);
2109 preprocess_constraints (insn
);
2110 alternative_mask prefrred
= get_preferred_alternatives (insn
);
2111 ira_implicitly_set_insn_hard_regs (&temp
, prefrred
);
2112 AND_COMPL_HARD_REG_SET (temp
, ira_no_alloc_regs
);
2114 /* If any implicit clobber registers intersect with regular ones in
2115 through_insn, we have a dependency and thus bail out. */
2116 EXECUTE_IF_SET_IN_HARD_REG_SET (temp
, 0, regno
, hrsi
)
2118 vinsn_t vi
= INSN_VINSN (through_insn
);
2119 if (bitmap_bit_p (VINSN_REG_SETS (vi
), regno
)
2120 || bitmap_bit_p (VINSN_REG_CLOBBERS (vi
), regno
)
2121 || bitmap_bit_p (VINSN_REG_USES (vi
), regno
))
2128 /* Modifies EXPR so it can be moved through the THROUGH_INSN,
2129 performing necessary transformations. Record the type of transformation
2130 made in PTRANS_TYPE, when it is not NULL. When INSIDE_INSN_GROUP,
2131 permit all dependencies except true ones, and try to remove those
2132 too via forward substitution. All cases when a non-eliminable
2133 non-zero cost dependency exists inside an insn group will be fixed
2134 in tick_check_p instead. */
2135 static enum MOVEUP_EXPR_CODE
2136 moveup_expr (expr_t expr
, insn_t through_insn
, bool inside_insn_group
,
2137 enum local_trans_type
*ptrans_type
)
2139 vinsn_t vi
= EXPR_VINSN (expr
);
2140 insn_t insn
= VINSN_INSN_RTX (vi
);
2141 bool was_changed
= false;
2142 bool as_rhs
= false;
2146 /* ??? We use dependencies of non-debug insns on debug insns to
2147 indicate that the debug insns need to be reset if the non-debug
2148 insn is pulled ahead of it. It's hard to figure out how to
2149 introduce such a notion in sel-sched, but it already fails to
2150 support debug insns in other ways, so we just go ahead and
2151 let the deug insns go corrupt for now. */
2152 if (DEBUG_INSN_P (through_insn
) && !DEBUG_INSN_P (insn
))
2153 return MOVEUP_EXPR_SAME
;
2155 /* When inside_insn_group, delegate to the helper. */
2156 if (inside_insn_group
)
2157 return moveup_expr_inside_insn_group (expr
, through_insn
);
2159 /* Deal with unique insns and control dependencies. */
2160 if (VINSN_UNIQUE_P (vi
))
2162 /* We can move jumps without side-effects or jumps that are
2163 mutually exclusive with instruction THROUGH_INSN (all in cases
2164 dependencies allow to do so and jump is not speculative). */
2165 if (control_flow_insn_p (insn
))
2167 basic_block fallthru_bb
;
2169 /* Do not move checks and do not move jumps through other
2171 if (control_flow_insn_p (through_insn
)
2172 || sel_insn_is_speculation_check (insn
))
2173 return MOVEUP_EXPR_NULL
;
2175 /* Don't move jumps through CFG joins. */
2176 if (bookkeeping_can_be_created_if_moved_through_p (through_insn
))
2177 return MOVEUP_EXPR_NULL
;
2179 /* The jump should have a clear fallthru block, and
2180 this block should be in the current region. */
2181 if ((fallthru_bb
= fallthru_bb_of_jump (insn
)) == NULL
2182 || ! in_current_region_p (fallthru_bb
))
2183 return MOVEUP_EXPR_NULL
;
2185 /* And it should be mutually exclusive with through_insn. */
2186 if (! sched_insns_conditions_mutex_p (insn
, through_insn
)
2187 && ! DEBUG_INSN_P (through_insn
))
2188 return MOVEUP_EXPR_NULL
;
2191 /* Don't move what we can't move. */
2192 if (EXPR_CANT_MOVE (expr
)
2193 && BLOCK_FOR_INSN (through_insn
) != BLOCK_FOR_INSN (insn
))
2194 return MOVEUP_EXPR_NULL
;
2196 /* Don't move SCHED_GROUP instruction through anything.
2197 If we don't force this, then it will be possible to start
2198 scheduling a sched_group before all its dependencies are
2200 ??? Haifa deals with this issue by delaying the SCHED_GROUP
2201 as late as possible through rank_for_schedule. */
2202 if (SCHED_GROUP_P (insn
))
2203 return MOVEUP_EXPR_NULL
;
2206 gcc_assert (!control_flow_insn_p (insn
));
2208 /* Don't move debug insns if this would require bookkeeping. */
2209 if (DEBUG_INSN_P (insn
)
2210 && BLOCK_FOR_INSN (through_insn
) != BLOCK_FOR_INSN (insn
)
2211 && moving_insn_creates_bookkeeping_block_p (insn
, through_insn
))
2212 return MOVEUP_EXPR_NULL
;
2214 /* Deal with data dependencies. */
2215 was_target_conflict
= false;
2216 full_ds
= has_dependence_p (expr
, through_insn
, &has_dep_p
);
2219 if (!CANT_MOVE_TRAPPING (expr
, through_insn
))
2220 return MOVEUP_EXPR_SAME
;
2224 /* We can move UNIQUE insn up only as a whole and unchanged,
2225 so it shouldn't have any dependencies. */
2226 if (VINSN_UNIQUE_P (vi
))
2227 return MOVEUP_EXPR_NULL
;
2230 if (full_ds
!= 0 && can_speculate_dep_p (full_ds
))
2234 res
= speculate_expr (expr
, full_ds
);
2237 /* Speculation was successful. */
2239 was_changed
= (res
> 0);
2241 was_target_conflict
= true;
2243 *ptrans_type
= TRANS_SPECULATION
;
2244 sel_clear_has_dependence ();
2248 if (has_dep_p
[DEPS_IN_INSN
])
2249 /* We have some dependency that cannot be discarded. */
2250 return MOVEUP_EXPR_NULL
;
2252 if (has_dep_p
[DEPS_IN_LHS
])
2254 /* Only separable insns can be moved up with the new register.
2255 Anyways, we should mark that the original register is
2257 if (!enable_schedule_as_rhs_p
|| !EXPR_SEPARABLE_P (expr
))
2258 return MOVEUP_EXPR_NULL
;
2260 /* When renaming a hard register to a pseudo before reload, extra
2261 dependencies can occur from the implicit clobbers of the insn.
2262 Filter out such cases here. */
2263 if (!reload_completed
&& REG_P (EXPR_LHS (expr
))
2264 && HARD_REGISTER_P (EXPR_LHS (expr
))
2265 && implicit_clobber_conflict_p (through_insn
, expr
))
2267 if (sched_verbose
>= 6)
2268 sel_print ("implicit clobbers conflict detected, ");
2269 return MOVEUP_EXPR_NULL
;
2271 EXPR_TARGET_AVAILABLE (expr
) = false;
2272 was_target_conflict
= true;
2276 /* At this point we have either separable insns, that will be lifted
2277 up only as RHSes, or non-separable insns with no dependency in lhs.
2278 If dependency is in RHS, then try to perform substitution and move up
2285 In Ex.1 y*2 can be substituted for x*2 and the whole operation can be
2286 moved above y=x assignment as z=x*2.
2288 In Ex.2 y*2 also can be substituted for x*2, but only the right hand
2289 side can be moved because of the output dependency. The operation was
2290 cropped to its rhs above. */
2291 if (has_dep_p
[DEPS_IN_RHS
])
2293 ds_t
*rhs_dsp
= &has_dep_p
[DEPS_IN_RHS
];
2295 /* Can't substitute UNIQUE VINSNs. */
2296 gcc_assert (!VINSN_UNIQUE_P (vi
));
2298 if (can_speculate_dep_p (*rhs_dsp
))
2302 res
= speculate_expr (expr
, *rhs_dsp
);
2305 /* Speculation was successful. */
2307 was_changed
= (res
> 0);
2309 was_target_conflict
= true;
2311 *ptrans_type
= TRANS_SPECULATION
;
2314 return MOVEUP_EXPR_NULL
;
2316 else if (can_substitute_through_p (through_insn
,
2318 && substitute_reg_in_expr (expr
, through_insn
, false))
2320 /* ??? We cannot perform substitution AND speculation on the same
2322 gcc_assert (!was_changed
);
2325 *ptrans_type
= TRANS_SUBSTITUTION
;
2326 EXPR_WAS_SUBSTITUTED (expr
) = true;
2329 return MOVEUP_EXPR_NULL
;
2332 /* Don't move trapping insns through jumps.
2333 This check should be at the end to give a chance to control speculation
2334 to perform its duties. */
2335 if (CANT_MOVE_TRAPPING (expr
, through_insn
))
2336 return MOVEUP_EXPR_NULL
;
2339 ? MOVEUP_EXPR_CHANGED
2341 ? MOVEUP_EXPR_AS_RHS
2342 : MOVEUP_EXPR_SAME
));
2345 /* Try to look at bitmap caches for EXPR and INSN pair, return true
2346 if successful. When INSIDE_INSN_GROUP, also try ignore dependencies
2347 that can exist within a parallel group. Write to RES the resulting
2348 code for moveup_expr. */
2350 try_bitmap_cache (expr_t expr
, insn_t insn
,
2351 bool inside_insn_group
,
2352 enum MOVEUP_EXPR_CODE
*res
)
2354 int expr_uid
= INSN_UID (EXPR_INSN_RTX (expr
));
2356 /* First check whether we've analyzed this situation already. */
2357 if (bitmap_bit_p (INSN_ANALYZED_DEPS (insn
), expr_uid
))
2359 if (bitmap_bit_p (INSN_FOUND_DEPS (insn
), expr_uid
))
2361 if (sched_verbose
>= 6)
2362 sel_print ("removed (cached)\n");
2363 *res
= MOVEUP_EXPR_NULL
;
2368 if (sched_verbose
>= 6)
2369 sel_print ("unchanged (cached)\n");
2370 *res
= MOVEUP_EXPR_SAME
;
2374 else if (bitmap_bit_p (INSN_FOUND_DEPS (insn
), expr_uid
))
2376 if (inside_insn_group
)
2378 if (sched_verbose
>= 6)
2379 sel_print ("unchanged (as RHS, cached, inside insn group)\n");
2380 *res
= MOVEUP_EXPR_SAME
;
2385 EXPR_TARGET_AVAILABLE (expr
) = false;
2387 /* This is the only case when propagation result can change over time,
2388 as we can dynamically switch off scheduling as RHS. In this case,
2389 just check the flag to reach the correct decision. */
2390 if (enable_schedule_as_rhs_p
)
2392 if (sched_verbose
>= 6)
2393 sel_print ("unchanged (as RHS, cached)\n");
2394 *res
= MOVEUP_EXPR_AS_RHS
;
2399 if (sched_verbose
>= 6)
2400 sel_print ("removed (cached as RHS, but renaming"
2401 " is now disabled)\n");
2402 *res
= MOVEUP_EXPR_NULL
;
2410 /* Try to look at bitmap caches for EXPR and INSN pair, return true
2411 if successful. Write to RES the resulting code for moveup_expr. */
2413 try_transformation_cache (expr_t expr
, insn_t insn
,
2414 enum MOVEUP_EXPR_CODE
*res
)
2416 struct transformed_insns
*pti
2417 = (struct transformed_insns
*)
2418 htab_find_with_hash (INSN_TRANSFORMED_INSNS (insn
),
2420 VINSN_HASH_RTX (EXPR_VINSN (expr
)));
2423 /* This EXPR was already moved through this insn and was
2424 changed as a result. Fetch the proper data from
2426 insert_in_history_vect (&EXPR_HISTORY_OF_CHANGES (expr
),
2427 INSN_UID (insn
), pti
->type
,
2428 pti
->vinsn_old
, pti
->vinsn_new
,
2429 EXPR_SPEC_DONE_DS (expr
));
2431 if (INSN_IN_STREAM_P (VINSN_INSN_RTX (pti
->vinsn_new
)))
2432 pti
->vinsn_new
= vinsn_copy (pti
->vinsn_new
, true);
2433 change_vinsn_in_expr (expr
, pti
->vinsn_new
);
2434 if (pti
->was_target_conflict
)
2435 EXPR_TARGET_AVAILABLE (expr
) = false;
2436 if (pti
->type
== TRANS_SPECULATION
)
2438 EXPR_SPEC_DONE_DS (expr
) = pti
->ds
;
2439 EXPR_NEEDS_SPEC_CHECK_P (expr
) |= pti
->needs_check
;
2442 if (sched_verbose
>= 6)
2444 sel_print ("changed (cached): ");
2449 *res
= MOVEUP_EXPR_CHANGED
;
2456 /* Update bitmap caches on INSN with result RES of propagating EXPR. */
2458 update_bitmap_cache (expr_t expr
, insn_t insn
, bool inside_insn_group
,
2459 enum MOVEUP_EXPR_CODE res
)
2461 int expr_uid
= INSN_UID (EXPR_INSN_RTX (expr
));
2463 /* Do not cache result of propagating jumps through an insn group,
2464 as it is always true, which is not useful outside the group. */
2465 if (inside_insn_group
)
2468 if (res
== MOVEUP_EXPR_NULL
)
2470 bitmap_set_bit (INSN_ANALYZED_DEPS (insn
), expr_uid
);
2471 bitmap_set_bit (INSN_FOUND_DEPS (insn
), expr_uid
);
2473 else if (res
== MOVEUP_EXPR_SAME
)
2475 bitmap_set_bit (INSN_ANALYZED_DEPS (insn
), expr_uid
);
2476 bitmap_clear_bit (INSN_FOUND_DEPS (insn
), expr_uid
);
2478 else if (res
== MOVEUP_EXPR_AS_RHS
)
2480 bitmap_clear_bit (INSN_ANALYZED_DEPS (insn
), expr_uid
);
2481 bitmap_set_bit (INSN_FOUND_DEPS (insn
), expr_uid
);
2487 /* Update hashtable on INSN with changed EXPR, old EXPR_OLD_VINSN
2488 and transformation type TRANS_TYPE. */
2490 update_transformation_cache (expr_t expr
, insn_t insn
,
2491 bool inside_insn_group
,
2492 enum local_trans_type trans_type
,
2493 vinsn_t expr_old_vinsn
)
2495 struct transformed_insns
*pti
;
2497 if (inside_insn_group
)
2500 pti
= XNEW (struct transformed_insns
);
2501 pti
->vinsn_old
= expr_old_vinsn
;
2502 pti
->vinsn_new
= EXPR_VINSN (expr
);
2503 pti
->type
= trans_type
;
2504 pti
->was_target_conflict
= was_target_conflict
;
2505 pti
->ds
= EXPR_SPEC_DONE_DS (expr
);
2506 pti
->needs_check
= EXPR_NEEDS_SPEC_CHECK_P (expr
);
2507 vinsn_attach (pti
->vinsn_old
);
2508 vinsn_attach (pti
->vinsn_new
);
2509 *((struct transformed_insns
**)
2510 htab_find_slot_with_hash (INSN_TRANSFORMED_INSNS (insn
),
2511 pti
, VINSN_HASH_RTX (expr_old_vinsn
),
2515 /* Same as moveup_expr, but first looks up the result of
2516 transformation in caches. */
2517 static enum MOVEUP_EXPR_CODE
2518 moveup_expr_cached (expr_t expr
, insn_t insn
, bool inside_insn_group
)
2520 enum MOVEUP_EXPR_CODE res
;
2521 bool got_answer
= false;
2523 if (sched_verbose
>= 6)
2525 sel_print ("Moving ");
2527 sel_print (" through %d: ", INSN_UID (insn
));
2530 if (DEBUG_INSN_P (EXPR_INSN_RTX (expr
))
2531 && BLOCK_FOR_INSN (EXPR_INSN_RTX (expr
))
2532 && (sel_bb_head (BLOCK_FOR_INSN (EXPR_INSN_RTX (expr
)))
2533 == EXPR_INSN_RTX (expr
)))
2534 /* Don't use cached information for debug insns that are heads of
2536 else if (try_bitmap_cache (expr
, insn
, inside_insn_group
, &res
))
2537 /* When inside insn group, we do not want remove stores conflicting
2538 with previosly issued loads. */
2539 got_answer
= ! inside_insn_group
|| res
!= MOVEUP_EXPR_NULL
;
2540 else if (try_transformation_cache (expr
, insn
, &res
))
2545 /* Invoke moveup_expr and record the results. */
2546 vinsn_t expr_old_vinsn
= EXPR_VINSN (expr
);
2547 ds_t expr_old_spec_ds
= EXPR_SPEC_DONE_DS (expr
);
2548 int expr_uid
= INSN_UID (VINSN_INSN_RTX (expr_old_vinsn
));
2549 bool unique_p
= VINSN_UNIQUE_P (expr_old_vinsn
);
2550 enum local_trans_type trans_type
= TRANS_SUBSTITUTION
;
2552 /* ??? Invent something better than this. We can't allow old_vinsn
2553 to go, we need it for the history vector. */
2554 vinsn_attach (expr_old_vinsn
);
2556 res
= moveup_expr (expr
, insn
, inside_insn_group
,
2560 case MOVEUP_EXPR_NULL
:
2561 update_bitmap_cache (expr
, insn
, inside_insn_group
, res
);
2562 if (sched_verbose
>= 6)
2563 sel_print ("removed\n");
2566 case MOVEUP_EXPR_SAME
:
2567 update_bitmap_cache (expr
, insn
, inside_insn_group
, res
);
2568 if (sched_verbose
>= 6)
2569 sel_print ("unchanged\n");
2572 case MOVEUP_EXPR_AS_RHS
:
2573 gcc_assert (!unique_p
|| inside_insn_group
);
2574 update_bitmap_cache (expr
, insn
, inside_insn_group
, res
);
2575 if (sched_verbose
>= 6)
2576 sel_print ("unchanged (as RHS)\n");
2579 case MOVEUP_EXPR_CHANGED
:
2580 gcc_assert (INSN_UID (EXPR_INSN_RTX (expr
)) != expr_uid
2581 || EXPR_SPEC_DONE_DS (expr
) != expr_old_spec_ds
);
2582 insert_in_history_vect (&EXPR_HISTORY_OF_CHANGES (expr
),
2583 INSN_UID (insn
), trans_type
,
2584 expr_old_vinsn
, EXPR_VINSN (expr
),
2586 update_transformation_cache (expr
, insn
, inside_insn_group
,
2587 trans_type
, expr_old_vinsn
);
2588 if (sched_verbose
>= 6)
2590 sel_print ("changed: ");
2599 vinsn_detach (expr_old_vinsn
);
2605 /* Moves an av set AVP up through INSN, performing necessary
2608 moveup_set_expr (av_set_t
*avp
, insn_t insn
, bool inside_insn_group
)
2613 FOR_EACH_EXPR_1 (expr
, i
, avp
)
2616 switch (moveup_expr_cached (expr
, insn
, inside_insn_group
))
2618 case MOVEUP_EXPR_SAME
:
2619 case MOVEUP_EXPR_AS_RHS
:
2622 case MOVEUP_EXPR_NULL
:
2623 av_set_iter_remove (&i
);
2626 case MOVEUP_EXPR_CHANGED
:
2627 expr
= merge_with_other_exprs (avp
, &i
, expr
);
2636 /* Moves AVP set along PATH. */
2638 moveup_set_inside_insn_group (av_set_t
*avp
, ilist_t path
)
2642 if (sched_verbose
>= 6)
2643 sel_print ("Moving expressions up in the insn group...\n");
2646 last_cycle
= INSN_SCHED_CYCLE (ILIST_INSN (path
));
2648 && INSN_SCHED_CYCLE (ILIST_INSN (path
)) == last_cycle
)
2650 moveup_set_expr (avp
, ILIST_INSN (path
), true);
2651 path
= ILIST_NEXT (path
);
2655 /* Returns true if after moving EXPR along PATH it equals to EXPR_VLIW. */
2657 equal_after_moveup_path_p (expr_t expr
, ilist_t path
, expr_t expr_vliw
)
2659 expr_def _tmp
, *tmp
= &_tmp
;
2663 copy_expr_onside (tmp
, expr
);
2664 last_cycle
= path
? INSN_SCHED_CYCLE (ILIST_INSN (path
)) : 0;
2667 && INSN_SCHED_CYCLE (ILIST_INSN (path
)) == last_cycle
)
2669 res
= (moveup_expr_cached (tmp
, ILIST_INSN (path
), true)
2670 != MOVEUP_EXPR_NULL
);
2671 path
= ILIST_NEXT (path
);
2676 vinsn_t tmp_vinsn
= EXPR_VINSN (tmp
);
2677 vinsn_t expr_vliw_vinsn
= EXPR_VINSN (expr_vliw
);
2679 if (tmp_vinsn
!= expr_vliw_vinsn
)
2680 res
= vinsn_equal_p (tmp_vinsn
, expr_vliw_vinsn
);
2688 /* Functions that compute av and lv sets. */
2690 /* Returns true if INSN is not a downward continuation of the given path P in
2691 the current stage. */
2693 is_ineligible_successor (insn_t insn
, ilist_t p
)
2697 /* Check if insn is not deleted. */
2698 if (PREV_INSN (insn
) && NEXT_INSN (PREV_INSN (insn
)) != insn
)
2700 else if (NEXT_INSN (insn
) && PREV_INSN (NEXT_INSN (insn
)) != insn
)
2703 /* If it's the first insn visited, then the successor is ok. */
2707 prev_insn
= ILIST_INSN (p
);
2709 if (/* a backward edge. */
2710 INSN_SEQNO (insn
) < INSN_SEQNO (prev_insn
)
2711 /* is already visited. */
2712 || (INSN_SEQNO (insn
) == INSN_SEQNO (prev_insn
)
2713 && (ilist_is_in_p (p
, insn
)
2714 /* We can reach another fence here and still seqno of insn
2715 would be equal to seqno of prev_insn. This is possible
2716 when prev_insn is a previously created bookkeeping copy.
2717 In that case it'd get a seqno of insn. Thus, check here
2718 whether insn is in current fence too. */
2719 || IN_CURRENT_FENCE_P (insn
)))
2720 /* Was already scheduled on this round. */
2721 || (INSN_SEQNO (insn
) > INSN_SEQNO (prev_insn
)
2722 && IN_CURRENT_FENCE_P (insn
))
2723 /* An insn from another fence could also be
2724 scheduled earlier even if this insn is not in
2725 a fence list right now. Check INSN_SCHED_CYCLE instead. */
2727 && INSN_SCHED_TIMES (insn
) > 0))
2733 /* Computes the av_set below the last bb insn INSN, doing all the 'dirty work'
2734 of handling multiple successors and properly merging its av_sets. P is
2735 the current path traversed. WS is the size of lookahead window.
2736 Return the av set computed. */
2738 compute_av_set_at_bb_end (insn_t insn
, ilist_t p
, int ws
)
2740 struct succs_info
*sinfo
;
2741 av_set_t expr_in_all_succ_branches
= NULL
;
2743 insn_t succ
, zero_succ
= NULL
;
2744 av_set_t av1
= NULL
;
2746 gcc_assert (sel_bb_end_p (insn
));
2748 /* Find different kind of successors needed for correct computing of
2749 SPEC and TARGET_AVAILABLE attributes. */
2750 sinfo
= compute_succs_info (insn
, SUCCS_NORMAL
);
2753 if (sched_verbose
>= 6)
2755 sel_print ("successors of bb end (%d): ", INSN_UID (insn
));
2756 dump_insn_vector (sinfo
->succs_ok
);
2758 if (sinfo
->succs_ok_n
!= sinfo
->all_succs_n
)
2759 sel_print ("real successors num: %d\n", sinfo
->all_succs_n
);
2762 /* Add insn to the tail of current path. */
2763 ilist_add (&p
, insn
);
2765 FOR_EACH_VEC_ELT (sinfo
->succs_ok
, is
, succ
)
2769 /* We will edit SUCC_SET and EXPR_SPEC field of its elements. */
2770 succ_set
= compute_av_set_inside_bb (succ
, p
, ws
, true);
2772 av_set_split_usefulness (succ_set
,
2773 sinfo
->probs_ok
[is
],
2776 if (sinfo
->all_succs_n
> 1)
2778 /* Find EXPR'es that came from *all* successors and save them
2779 into expr_in_all_succ_branches. This set will be used later
2780 for calculating speculation attributes of EXPR'es. */
2783 expr_in_all_succ_branches
= av_set_copy (succ_set
);
2785 /* Remember the first successor for later. */
2793 FOR_EACH_EXPR_1 (expr
, i
, &expr_in_all_succ_branches
)
2794 if (!av_set_is_in_p (succ_set
, EXPR_VINSN (expr
)))
2795 av_set_iter_remove (&i
);
2799 /* Union the av_sets. Check liveness restrictions on target registers
2800 in special case of two successors. */
2801 if (sinfo
->succs_ok_n
== 2 && is
== 1)
2803 basic_block bb0
= BLOCK_FOR_INSN (zero_succ
);
2804 basic_block bb1
= BLOCK_FOR_INSN (succ
);
2806 gcc_assert (BB_LV_SET_VALID_P (bb0
) && BB_LV_SET_VALID_P (bb1
));
2807 av_set_union_and_live (&av1
, &succ_set
,
2813 av_set_union_and_clear (&av1
, &succ_set
, insn
);
2816 /* Check liveness restrictions via hard way when there are more than
2818 if (sinfo
->succs_ok_n
> 2)
2819 FOR_EACH_VEC_ELT (sinfo
->succs_ok
, is
, succ
)
2821 basic_block succ_bb
= BLOCK_FOR_INSN (succ
);
2822 av_set_t av_succ
= (is_ineligible_successor (succ
, p
)
2824 : BB_AV_SET (succ_bb
));
2826 gcc_assert (BB_LV_SET_VALID_P (succ_bb
));
2827 mark_unavailable_targets (av1
, av_succ
, BB_LV_SET (succ_bb
));
2830 /* Finally, check liveness restrictions on paths leaving the region. */
2831 if (sinfo
->all_succs_n
> sinfo
->succs_ok_n
)
2832 FOR_EACH_VEC_ELT (sinfo
->succs_other
, is
, succ
)
2833 mark_unavailable_targets
2834 (av1
, NULL
, BB_LV_SET (BLOCK_FOR_INSN (succ
)));
2836 if (sinfo
->all_succs_n
> 1)
2841 /* Increase the spec attribute of all EXPR'es that didn't come
2842 from all successors. */
2843 FOR_EACH_EXPR (expr
, i
, av1
)
2844 if (!av_set_is_in_p (expr_in_all_succ_branches
, EXPR_VINSN (expr
)))
2847 av_set_clear (&expr_in_all_succ_branches
);
2849 /* Do not move conditional branches through other
2850 conditional branches. So, remove all conditional
2851 branches from av_set if current operator is a conditional
2853 av_set_substract_cond_branches (&av1
);
2857 free_succs_info (sinfo
);
2859 if (sched_verbose
>= 6)
2861 sel_print ("av_succs (%d): ", INSN_UID (insn
));
2869 /* This function computes av_set for the FIRST_INSN by dragging valid
2870 av_set through all basic block insns either from the end of basic block
2871 (computed using compute_av_set_at_bb_end) or from the insn on which
2872 MAX_WS was exceeded. It uses compute_av_set_at_bb_end to compute av_set
2873 below the basic block and handling conditional branches.
2874 FIRST_INSN - the basic block head, P - path consisting of the insns
2875 traversed on the way to the FIRST_INSN (the path is sparse, only bb heads
2876 and bb ends are added to the path), WS - current window size,
2877 NEED_COPY_P - true if we'll make a copy of av_set before returning it. */
2879 compute_av_set_inside_bb (insn_t first_insn
, ilist_t p
, int ws
,
2884 insn_t bb_end
= sel_bb_end (BLOCK_FOR_INSN (first_insn
));
2885 insn_t after_bb_end
= NEXT_INSN (bb_end
);
2888 basic_block cur_bb
= BLOCK_FOR_INSN (first_insn
);
2890 /* Return NULL if insn is not on the legitimate downward path. */
2891 if (is_ineligible_successor (first_insn
, p
))
2893 if (sched_verbose
>= 6)
2894 sel_print ("Insn %d is ineligible_successor\n", INSN_UID (first_insn
));
2899 /* If insn already has valid av(insn) computed, just return it. */
2900 if (AV_SET_VALID_P (first_insn
))
2904 if (sel_bb_head_p (first_insn
))
2905 av_set
= BB_AV_SET (BLOCK_FOR_INSN (first_insn
));
2909 if (sched_verbose
>= 6)
2911 sel_print ("Insn %d has a valid av set: ", INSN_UID (first_insn
));
2912 dump_av_set (av_set
);
2916 return need_copy_p
? av_set_copy (av_set
) : av_set
;
2919 ilist_add (&p
, first_insn
);
2921 /* As the result after this loop have completed, in LAST_INSN we'll
2922 have the insn which has valid av_set to start backward computation
2923 from: it either will be NULL because on it the window size was exceeded
2924 or other valid av_set as returned by compute_av_set for the last insn
2925 of the basic block. */
2926 for (last_insn
= first_insn
; last_insn
!= after_bb_end
;
2927 last_insn
= NEXT_INSN (last_insn
))
2929 /* We may encounter valid av_set not only on bb_head, but also on
2930 those insns on which previously MAX_WS was exceeded. */
2931 if (AV_SET_VALID_P (last_insn
))
2933 if (sched_verbose
>= 6)
2934 sel_print ("Insn %d has a valid empty av set\n", INSN_UID (last_insn
));
2938 /* The special case: the last insn of the BB may be an
2939 ineligible_successor due to its SEQ_NO that was set on
2940 it as a bookkeeping. */
2941 if (last_insn
!= first_insn
2942 && is_ineligible_successor (last_insn
, p
))
2944 if (sched_verbose
>= 6)
2945 sel_print ("Insn %d is ineligible_successor\n", INSN_UID (last_insn
));
2949 if (DEBUG_INSN_P (last_insn
))
2952 if (end_ws
> max_ws
)
2954 /* We can reach max lookahead size at bb_header, so clean av_set
2956 INSN_WS_LEVEL (last_insn
) = global_level
;
2958 if (sched_verbose
>= 6)
2959 sel_print ("Insn %d is beyond the software lookahead window size\n",
2960 INSN_UID (last_insn
));
2967 /* Get the valid av_set into AV above the LAST_INSN to start backward
2968 computation from. It either will be empty av_set or av_set computed from
2969 the successors on the last insn of the current bb. */
2970 if (last_insn
!= after_bb_end
)
2974 /* This is needed only to obtain av_sets that are identical to
2975 those computed by the old compute_av_set version. */
2976 if (last_insn
== first_insn
&& !INSN_NOP_P (last_insn
))
2977 av_set_add (&av
, INSN_EXPR (last_insn
));
2980 /* END_WS is always already increased by 1 if LAST_INSN == AFTER_BB_END. */
2981 av
= compute_av_set_at_bb_end (bb_end
, p
, end_ws
);
2983 /* Compute av_set in AV starting from below the LAST_INSN up to
2984 location above the FIRST_INSN. */
2985 for (cur_insn
= PREV_INSN (last_insn
); cur_insn
!= PREV_INSN (first_insn
);
2986 cur_insn
= PREV_INSN (cur_insn
))
2987 if (!INSN_NOP_P (cur_insn
))
2991 moveup_set_expr (&av
, cur_insn
, false);
2993 /* If the expression for CUR_INSN is already in the set,
2994 replace it by the new one. */
2995 expr
= av_set_lookup (av
, INSN_VINSN (cur_insn
));
2999 copy_expr (expr
, INSN_EXPR (cur_insn
));
3002 av_set_add (&av
, INSN_EXPR (cur_insn
));
3005 /* Clear stale bb_av_set. */
3006 if (sel_bb_head_p (first_insn
))
3008 av_set_clear (&BB_AV_SET (cur_bb
));
3009 BB_AV_SET (cur_bb
) = need_copy_p
? av_set_copy (av
) : av
;
3010 BB_AV_LEVEL (cur_bb
) = global_level
;
3013 if (sched_verbose
>= 6)
3015 sel_print ("Computed av set for insn %d: ", INSN_UID (first_insn
));
3024 /* Compute av set before INSN.
3025 INSN - the current operation (actual rtx INSN)
3026 P - the current path, which is list of insns visited so far
3027 WS - software lookahead window size.
3028 UNIQUE_P - TRUE, if returned av_set will be changed, hence
3029 if we want to save computed av_set in s_i_d, we should make a copy of it.
3031 In the resulting set we will have only expressions that don't have delay
3032 stalls and nonsubstitutable dependences. */
3034 compute_av_set (insn_t insn
, ilist_t p
, int ws
, bool unique_p
)
3036 return compute_av_set_inside_bb (insn
, p
, ws
, unique_p
);
3039 /* Propagate a liveness set LV through INSN. */
3041 propagate_lv_set (regset lv
, insn_t insn
)
3043 gcc_assert (INSN_P (insn
));
3045 if (INSN_NOP_P (insn
))
3048 df_simulate_one_insn_backwards (BLOCK_FOR_INSN (insn
), insn
, lv
);
3051 /* Return livness set at the end of BB. */
3053 compute_live_after_bb (basic_block bb
)
3057 regset lv
= get_clear_regset_from_pool ();
3059 gcc_assert (!ignore_first
);
3061 FOR_EACH_EDGE (e
, ei
, bb
->succs
)
3062 if (sel_bb_empty_p (e
->dest
))
3064 if (! BB_LV_SET_VALID_P (e
->dest
))
3067 gcc_assert (BB_LV_SET (e
->dest
) == NULL
);
3068 BB_LV_SET (e
->dest
) = compute_live_after_bb (e
->dest
);
3069 BB_LV_SET_VALID_P (e
->dest
) = true;
3071 IOR_REG_SET (lv
, BB_LV_SET (e
->dest
));
3074 IOR_REG_SET (lv
, compute_live (sel_bb_head (e
->dest
)));
3079 /* Compute the set of all live registers at the point before INSN and save
3080 it at INSN if INSN is bb header. */
3082 compute_live (insn_t insn
)
3084 basic_block bb
= BLOCK_FOR_INSN (insn
);
3088 /* Return the valid set if we're already on it. */
3093 if (sel_bb_head_p (insn
) && BB_LV_SET_VALID_P (bb
))
3094 src
= BB_LV_SET (bb
);
3097 gcc_assert (in_current_region_p (bb
));
3098 if (INSN_LIVE_VALID_P (insn
))
3099 src
= INSN_LIVE (insn
);
3104 lv
= get_regset_from_pool ();
3105 COPY_REG_SET (lv
, src
);
3107 if (sel_bb_head_p (insn
) && ! BB_LV_SET_VALID_P (bb
))
3109 COPY_REG_SET (BB_LV_SET (bb
), lv
);
3110 BB_LV_SET_VALID_P (bb
) = true;
3113 return_regset_to_pool (lv
);
3118 /* We've skipped the wrong lv_set. Don't skip the right one. */
3119 ignore_first
= false;
3120 gcc_assert (in_current_region_p (bb
));
3122 /* Find a valid LV set in this block or below, if needed.
3123 Start searching from the next insn: either ignore_first is true, or
3124 INSN doesn't have a correct live set. */
3125 temp
= NEXT_INSN (insn
);
3126 final
= NEXT_INSN (BB_END (bb
));
3127 while (temp
!= final
&& ! INSN_LIVE_VALID_P (temp
))
3128 temp
= NEXT_INSN (temp
);
3131 lv
= compute_live_after_bb (bb
);
3132 temp
= PREV_INSN (temp
);
3136 lv
= get_regset_from_pool ();
3137 COPY_REG_SET (lv
, INSN_LIVE (temp
));
3140 /* Put correct lv sets on the insns which have bad sets. */
3141 final
= PREV_INSN (insn
);
3142 while (temp
!= final
)
3144 propagate_lv_set (lv
, temp
);
3145 COPY_REG_SET (INSN_LIVE (temp
), lv
);
3146 INSN_LIVE_VALID_P (temp
) = true;
3147 temp
= PREV_INSN (temp
);
3150 /* Also put it in a BB. */
3151 if (sel_bb_head_p (insn
))
3153 basic_block bb
= BLOCK_FOR_INSN (insn
);
3155 COPY_REG_SET (BB_LV_SET (bb
), lv
);
3156 BB_LV_SET_VALID_P (bb
) = true;
3159 /* We return LV to the pool, but will not clear it there. Thus we can
3160 legimatelly use LV till the next use of regset_pool_get (). */
3161 return_regset_to_pool (lv
);
3165 /* Update liveness sets for INSN. */
3167 update_liveness_on_insn (rtx_insn
*insn
)
3169 ignore_first
= true;
3170 compute_live (insn
);
3173 /* Compute liveness below INSN and write it into REGS. */
3175 compute_live_below_insn (rtx_insn
*insn
, regset regs
)
3180 FOR_EACH_SUCC_1 (succ
, si
, insn
, SUCCS_ALL
)
3181 IOR_REG_SET (regs
, compute_live (succ
));
3184 /* Update the data gathered in av and lv sets starting from INSN. */
3186 update_data_sets (rtx_insn
*insn
)
3188 update_liveness_on_insn (insn
);
3189 if (sel_bb_head_p (insn
))
3191 gcc_assert (AV_LEVEL (insn
) != 0);
3192 BB_AV_LEVEL (BLOCK_FOR_INSN (insn
)) = -1;
3193 compute_av_set (insn
, NULL
, 0, 0);
3198 /* Helper for move_op () and find_used_regs ().
3199 Return speculation type for which a check should be created on the place
3200 of INSN. EXPR is one of the original ops we are searching for. */
3202 get_spec_check_type_for_insn (insn_t insn
, expr_t expr
)
3205 ds_t already_checked_ds
= EXPR_SPEC_DONE_DS (INSN_EXPR (insn
));
3207 to_check_ds
= EXPR_SPEC_TO_CHECK_DS (expr
);
3209 if (targetm
.sched
.get_insn_checked_ds
)
3210 already_checked_ds
|= targetm
.sched
.get_insn_checked_ds (insn
);
3212 if (spec_info
!= NULL
3213 && (spec_info
->flags
& SEL_SCHED_SPEC_DONT_CHECK_CONTROL
))
3214 already_checked_ds
|= BEGIN_CONTROL
;
3216 already_checked_ds
= ds_get_speculation_types (already_checked_ds
);
3218 to_check_ds
&= ~already_checked_ds
;
3223 /* Find the set of registers that are unavailable for storing expres
3224 while moving ORIG_OPS up on the path starting from INSN due to
3225 liveness (USED_REGS) or hardware restrictions (REG_RENAME_P).
3227 All the original operations found during the traversal are saved in the
3228 ORIGINAL_INSNS list.
3230 REG_RENAME_P denotes the set of hardware registers that
3231 cannot be used with renaming due to the register class restrictions,
3232 mode restrictions and other (the register we'll choose should be
3233 compatible class with the original uses, shouldn't be in call_used_regs,
3234 should be HARD_REGNO_RENAME_OK etc).
3236 Returns TRUE if we've found all original insns, FALSE otherwise.
3238 This function utilizes code_motion_path_driver (formerly find_used_regs_1)
3239 to traverse the code motion paths. This helper function finds registers
3240 that are not available for storing expres while moving ORIG_OPS up on the
3241 path starting from INSN. A register considered as used on the moving path,
3242 if one of the following conditions is not satisfied:
3244 (1) a register not set or read on any path from xi to an instance of
3245 the original operation,
3246 (2) not among the live registers of the point immediately following the
3247 first original operation on a given downward path, except for the
3248 original target register of the operation,
3249 (3) not live on the other path of any conditional branch that is passed
3250 by the operation, in case original operations are not present on
3251 both paths of the conditional branch.
3253 All the original operations found during the traversal are saved in the
3254 ORIGINAL_INSNS list.
3256 REG_RENAME_P->CROSSES_CALL is true, if there is a call insn on the path
3257 from INSN to original insn. In this case CALL_USED_REG_SET will be added
3258 to unavailable hard regs at the point original operation is found. */
3261 find_used_regs (insn_t insn
, av_set_t orig_ops
, regset used_regs
,
3262 struct reg_rename
*reg_rename_p
, def_list_t
*original_insns
)
3264 def_list_iterator i
;
3267 bool needs_spec_check_p
= false;
3269 av_set_iterator expr_iter
;
3270 struct fur_static_params sparams
;
3271 struct cmpd_local_params lparams
;
3273 /* We haven't visited any blocks yet. */
3274 bitmap_clear (code_motion_visited_blocks
);
3276 /* Init parameters for code_motion_path_driver. */
3277 sparams
.crosses_call
= false;
3278 sparams
.original_insns
= original_insns
;
3279 sparams
.used_regs
= used_regs
;
3281 /* Set the appropriate hooks and data. */
3282 code_motion_path_driver_info
= &fur_hooks
;
3284 res
= code_motion_path_driver (insn
, orig_ops
, NULL
, &lparams
, &sparams
);
3286 reg_rename_p
->crosses_call
|= sparams
.crosses_call
;
3288 gcc_assert (res
== 1);
3289 gcc_assert (original_insns
&& *original_insns
);
3291 /* ??? We calculate whether an expression needs a check when computing
3292 av sets. This information is not as precise as it could be due to
3293 merging this bit in merge_expr. We can do better in find_used_regs,
3294 but we want to avoid multiple traversals of the same code motion
3296 FOR_EACH_EXPR (expr
, expr_iter
, orig_ops
)
3297 needs_spec_check_p
|= EXPR_NEEDS_SPEC_CHECK_P (expr
);
3299 /* Mark hardware regs in REG_RENAME_P that are not suitable
3300 for renaming expr in INSN due to hardware restrictions (register class,
3301 modes compatibility etc). */
3302 FOR_EACH_DEF (def
, i
, *original_insns
)
3304 vinsn_t vinsn
= INSN_VINSN (def
->orig_insn
);
3306 if (VINSN_SEPARABLE_P (vinsn
))
3307 mark_unavailable_hard_regs (def
, reg_rename_p
, used_regs
);
3309 /* Do not allow clobbering of ld.[sa] address in case some of the
3310 original operations need a check. */
3311 if (needs_spec_check_p
)
3312 IOR_REG_SET (used_regs
, VINSN_REG_USES (vinsn
));
3319 /* Functions to choose the best insn from available ones. */
3321 /* Adjusts the priority for EXPR using the backend *_adjust_priority hook. */
3323 sel_target_adjust_priority (expr_t expr
)
3325 int priority
= EXPR_PRIORITY (expr
);
3328 if (targetm
.sched
.adjust_priority
)
3329 new_priority
= targetm
.sched
.adjust_priority (EXPR_INSN_RTX (expr
), priority
);
3331 new_priority
= priority
;
3333 /* If the priority has changed, adjust EXPR_PRIORITY_ADJ accordingly. */
3334 EXPR_PRIORITY_ADJ (expr
) = new_priority
- EXPR_PRIORITY (expr
);
3336 if (sched_verbose
>= 4)
3337 sel_print ("sel_target_adjust_priority: insn %d, %d+%d = %d.\n",
3338 INSN_UID (EXPR_INSN_RTX (expr
)), EXPR_PRIORITY (expr
),
3339 EXPR_PRIORITY_ADJ (expr
), new_priority
);
3341 return new_priority
;
3344 /* Rank two available exprs for schedule. Never return 0 here. */
3346 sel_rank_for_schedule (const void *x
, const void *y
)
3348 expr_t tmp
= *(const expr_t
*) y
;
3349 expr_t tmp2
= *(const expr_t
*) x
;
3350 insn_t tmp_insn
, tmp2_insn
;
3351 vinsn_t tmp_vinsn
, tmp2_vinsn
;
3354 tmp_vinsn
= EXPR_VINSN (tmp
);
3355 tmp2_vinsn
= EXPR_VINSN (tmp2
);
3356 tmp_insn
= EXPR_INSN_RTX (tmp
);
3357 tmp2_insn
= EXPR_INSN_RTX (tmp2
);
3359 /* Schedule debug insns as early as possible. */
3360 if (DEBUG_INSN_P (tmp_insn
) && !DEBUG_INSN_P (tmp2_insn
))
3362 else if (DEBUG_INSN_P (tmp2_insn
))
3365 /* Prefer SCHED_GROUP_P insns to any others. */
3366 if (SCHED_GROUP_P (tmp_insn
) != SCHED_GROUP_P (tmp2_insn
))
3368 if (VINSN_UNIQUE_P (tmp_vinsn
) && VINSN_UNIQUE_P (tmp2_vinsn
))
3369 return SCHED_GROUP_P (tmp2_insn
) ? 1 : -1;
3371 /* Now uniqueness means SCHED_GROUP_P is set, because schedule groups
3372 cannot be cloned. */
3373 if (VINSN_UNIQUE_P (tmp2_vinsn
))
3378 /* Discourage scheduling of speculative checks. */
3379 val
= (sel_insn_is_speculation_check (tmp_insn
)
3380 - sel_insn_is_speculation_check (tmp2_insn
));
3384 /* Prefer not scheduled insn over scheduled one. */
3385 if (EXPR_SCHED_TIMES (tmp
) > 0 || EXPR_SCHED_TIMES (tmp2
) > 0)
3387 val
= EXPR_SCHED_TIMES (tmp
) - EXPR_SCHED_TIMES (tmp2
);
3392 /* Prefer jump over non-jump instruction. */
3393 if (control_flow_insn_p (tmp_insn
) && !control_flow_insn_p (tmp2_insn
))
3395 else if (control_flow_insn_p (tmp2_insn
) && !control_flow_insn_p (tmp_insn
))
3398 /* Prefer an expr with non-zero usefulness. */
3399 int u1
= EXPR_USEFULNESS (tmp
), u2
= EXPR_USEFULNESS (tmp2
);
3411 /* Prefer an expr with greater priority. */
3412 val
= (u2
* (EXPR_PRIORITY (tmp2
) + EXPR_PRIORITY_ADJ (tmp2
))
3413 - u1
* (EXPR_PRIORITY (tmp
) + EXPR_PRIORITY_ADJ (tmp
)));
3417 if (spec_info
!= NULL
&& spec_info
->mask
!= 0)
3418 /* This code was taken from haifa-sched.c: rank_for_schedule (). */
3424 ds1
= EXPR_SPEC_DONE_DS (tmp
);
3426 dw1
= ds_weak (ds1
);
3430 ds2
= EXPR_SPEC_DONE_DS (tmp2
);
3432 dw2
= ds_weak (ds2
);
3437 if (dw
> (NO_DEP_WEAK
/ 8) || dw
< -(NO_DEP_WEAK
/ 8))
3441 /* Prefer an old insn to a bookkeeping insn. */
3442 if (INSN_UID (tmp_insn
) < first_emitted_uid
3443 && INSN_UID (tmp2_insn
) >= first_emitted_uid
)
3445 if (INSN_UID (tmp_insn
) >= first_emitted_uid
3446 && INSN_UID (tmp2_insn
) < first_emitted_uid
)
3449 /* Prefer an insn with smaller UID, as a last resort.
3450 We can't safely use INSN_LUID as it is defined only for those insns
3451 that are in the stream. */
3452 return INSN_UID (tmp_insn
) - INSN_UID (tmp2_insn
);
3455 /* Filter out expressions from av set pointed to by AV_PTR
3456 that are pipelined too many times. */
3458 process_pipelined_exprs (av_set_t
*av_ptr
)
3463 /* Don't pipeline already pipelined code as that would increase
3464 number of unnecessary register moves. */
3465 FOR_EACH_EXPR_1 (expr
, si
, av_ptr
)
3467 if (EXPR_SCHED_TIMES (expr
)
3468 >= PARAM_VALUE (PARAM_SELSCHED_MAX_SCHED_TIMES
))
3469 av_set_iter_remove (&si
);
3473 /* Filter speculative insns from AV_PTR if we don't want them. */
3475 process_spec_exprs (av_set_t
*av_ptr
)
3480 if (spec_info
== NULL
)
3483 /* Scan *AV_PTR to find out if we want to consider speculative
3484 instructions for scheduling. */
3485 FOR_EACH_EXPR_1 (expr
, si
, av_ptr
)
3489 ds
= EXPR_SPEC_DONE_DS (expr
);
3491 /* The probability of a success is too low - don't speculate. */
3492 if ((ds
& SPECULATIVE
)
3493 && (ds_weak (ds
) < spec_info
->data_weakness_cutoff
3494 || EXPR_USEFULNESS (expr
) < spec_info
->control_weakness_cutoff
3495 || (pipelining_p
&& false
3497 && (ds
& CONTROL_SPEC
))))
3499 av_set_iter_remove (&si
);
3505 /* Search for any use-like insns in AV_PTR and decide on scheduling
3506 them. Return one when found, and NULL otherwise.
3507 Note that we check here whether a USE could be scheduled to avoid
3508 an infinite loop later. */
3510 process_use_exprs (av_set_t
*av_ptr
)
3514 bool uses_present_p
= false;
3515 bool try_uses_p
= true;
3517 FOR_EACH_EXPR_1 (expr
, si
, av_ptr
)
3519 /* This will also initialize INSN_CODE for later use. */
3520 if (recog_memoized (EXPR_INSN_RTX (expr
)) < 0)
3522 /* If we have a USE in *AV_PTR that was not scheduled yet,
3523 do so because it will do good only. */
3524 if (EXPR_SCHED_TIMES (expr
) <= 0)
3526 if (EXPR_TARGET_AVAILABLE (expr
) == 1)
3529 av_set_iter_remove (&si
);
3533 gcc_assert (pipelining_p
);
3535 uses_present_p
= true;
3544 /* If we don't want to schedule any USEs right now and we have some
3545 in *AV_PTR, remove them, else just return the first one found. */
3548 FOR_EACH_EXPR_1 (expr
, si
, av_ptr
)
3549 if (INSN_CODE (EXPR_INSN_RTX (expr
)) < 0)
3550 av_set_iter_remove (&si
);
3554 FOR_EACH_EXPR_1 (expr
, si
, av_ptr
)
3556 gcc_assert (INSN_CODE (EXPR_INSN_RTX (expr
)) < 0);
3558 if (EXPR_TARGET_AVAILABLE (expr
) == 1)
3561 av_set_iter_remove (&si
);
3569 /* Lookup EXPR in VINSN_VEC and return TRUE if found. Also check patterns from
3570 EXPR's history of changes. */
3572 vinsn_vec_has_expr_p (vinsn_vec_t vinsn_vec
, expr_t expr
)
3574 vinsn_t vinsn
, expr_vinsn
;
3578 /* Start with checking expr itself and then proceed with all the old forms
3579 of expr taken from its history vector. */
3580 for (i
= 0, expr_vinsn
= EXPR_VINSN (expr
);
3582 expr_vinsn
= (i
< EXPR_HISTORY_OF_CHANGES (expr
).length ()
3583 ? EXPR_HISTORY_OF_CHANGES (expr
)[i
++].old_expr_vinsn
3585 FOR_EACH_VEC_ELT (vinsn_vec
, n
, vinsn
)
3586 if (VINSN_SEPARABLE_P (vinsn
))
3588 if (vinsn_equal_p (vinsn
, expr_vinsn
))
3593 /* For non-separable instructions, the blocking insn can have
3594 another pattern due to substitution, and we can't choose
3595 different register as in the above case. Check all registers
3596 being written instead. */
3597 if (bitmap_intersect_p (VINSN_REG_SETS (vinsn
),
3598 VINSN_REG_SETS (expr_vinsn
)))
3605 /* Return true if either of expressions from ORIG_OPS can be blocked
3606 by previously created bookkeeping code. STATIC_PARAMS points to static
3607 parameters of move_op. */
3609 av_set_could_be_blocked_by_bookkeeping_p (av_set_t orig_ops
, void *static_params
)
3612 av_set_iterator iter
;
3613 moveop_static_params_p sparams
;
3615 /* This checks that expressions in ORIG_OPS are not blocked by bookkeeping
3616 created while scheduling on another fence. */
3617 FOR_EACH_EXPR (expr
, iter
, orig_ops
)
3618 if (vinsn_vec_has_expr_p (vec_bookkeeping_blocked_vinsns
, expr
))
3621 gcc_assert (code_motion_path_driver_info
== &move_op_hooks
);
3622 sparams
= (moveop_static_params_p
) static_params
;
3624 /* Expressions can be also blocked by bookkeeping created during current
3626 if (bitmap_bit_p (current_copies
, INSN_UID (sparams
->failed_insn
)))
3627 FOR_EACH_EXPR (expr
, iter
, orig_ops
)
3628 if (moveup_expr_cached (expr
, sparams
->failed_insn
, false) != MOVEUP_EXPR_NULL
)
3631 /* Expressions in ORIG_OPS may have wrong destination register due to
3632 renaming. Check with the right register instead. */
3633 if (sparams
->dest
&& REG_P (sparams
->dest
))
3635 rtx reg
= sparams
->dest
;
3636 vinsn_t failed_vinsn
= INSN_VINSN (sparams
->failed_insn
);
3638 if (register_unavailable_p (VINSN_REG_SETS (failed_vinsn
), reg
)
3639 || register_unavailable_p (VINSN_REG_USES (failed_vinsn
), reg
)
3640 || register_unavailable_p (VINSN_REG_CLOBBERS (failed_vinsn
), reg
))
3647 /* Clear VINSN_VEC and detach vinsns. */
3649 vinsn_vec_clear (vinsn_vec_t
*vinsn_vec
)
3651 unsigned len
= vinsn_vec
->length ();
3657 FOR_EACH_VEC_ELT (*vinsn_vec
, n
, vinsn
)
3658 vinsn_detach (vinsn
);
3659 vinsn_vec
->block_remove (0, len
);
3663 /* Add the vinsn of EXPR to the VINSN_VEC. */
3665 vinsn_vec_add (vinsn_vec_t
*vinsn_vec
, expr_t expr
)
3667 vinsn_attach (EXPR_VINSN (expr
));
3668 vinsn_vec
->safe_push (EXPR_VINSN (expr
));
3671 /* Free the vector representing blocked expressions. */
3673 vinsn_vec_free (vinsn_vec_t
&vinsn_vec
)
3675 vinsn_vec
.release ();
3678 /* Increase EXPR_PRIORITY_ADJ for INSN by AMOUNT. */
3680 void sel_add_to_insn_priority (rtx insn
, int amount
)
3682 EXPR_PRIORITY_ADJ (INSN_EXPR (insn
)) += amount
;
3684 if (sched_verbose
>= 2)
3685 sel_print ("sel_add_to_insn_priority: insn %d, by %d (now %d+%d).\n",
3686 INSN_UID (insn
), amount
, EXPR_PRIORITY (INSN_EXPR (insn
)),
3687 EXPR_PRIORITY_ADJ (INSN_EXPR (insn
)));
3690 /* Turn AV into a vector, filter inappropriate insns and sort it. Return
3691 true if there is something to schedule. BNDS and FENCE are current
3692 boundaries and fence, respectively. If we need to stall for some cycles
3693 before an expr from AV would become available, write this number to
3696 fill_vec_av_set (av_set_t av
, blist_t bnds
, fence_t fence
,
3701 int sched_next_worked
= 0, stalled
, n
;
3702 static int av_max_prio
, est_ticks_till_branch
;
3703 int min_need_stall
= -1;
3704 deps_t dc
= BND_DC (BLIST_BND (bnds
));
3706 /* Bail out early when the ready list contained only USEs/CLOBBERs that are
3707 already scheduled. */
3711 /* Empty vector from the previous stuff. */
3712 if (vec_av_set
.length () > 0)
3713 vec_av_set
.block_remove (0, vec_av_set
.length ());
3715 /* Turn the set into a vector for sorting and call sel_target_adjust_priority
3717 gcc_assert (vec_av_set
.is_empty ());
3718 FOR_EACH_EXPR (expr
, si
, av
)
3720 vec_av_set
.safe_push (expr
);
3722 gcc_assert (EXPR_PRIORITY_ADJ (expr
) == 0 || *pneed_stall
);
3724 /* Adjust priority using target backend hook. */
3725 sel_target_adjust_priority (expr
);
3728 /* Sort the vector. */
3729 vec_av_set
.qsort (sel_rank_for_schedule
);
3731 /* We record maximal priority of insns in av set for current instruction
3733 if (FENCE_STARTS_CYCLE_P (fence
))
3734 av_max_prio
= est_ticks_till_branch
= INT_MIN
;
3736 /* Filter out inappropriate expressions. Loop's direction is reversed to
3737 visit "best" instructions first. We assume that vec::unordered_remove
3738 moves last element in place of one being deleted. */
3739 for (n
= vec_av_set
.length () - 1, stalled
= 0; n
>= 0; n
--)
3741 expr_t expr
= vec_av_set
[n
];
3742 insn_t insn
= EXPR_INSN_RTX (expr
);
3743 signed char target_available
;
3744 bool is_orig_reg_p
= true;
3745 int need_cycles
, new_prio
;
3746 bool fence_insn_p
= INSN_UID (insn
) == INSN_UID (FENCE_INSN (fence
));
3748 /* Don't allow any insns other than from SCHED_GROUP if we have one. */
3749 if (FENCE_SCHED_NEXT (fence
) && insn
!= FENCE_SCHED_NEXT (fence
))
3751 vec_av_set
.unordered_remove (n
);
3755 /* Set number of sched_next insns (just in case there
3756 could be several). */
3757 if (FENCE_SCHED_NEXT (fence
))
3758 sched_next_worked
++;
3760 /* Check all liveness requirements and try renaming.
3761 FIXME: try to minimize calls to this. */
3762 target_available
= EXPR_TARGET_AVAILABLE (expr
);
3764 /* If insn was already scheduled on the current fence,
3765 set TARGET_AVAILABLE to -1 no matter what expr's attribute says. */
3766 if (vinsn_vec_has_expr_p (vec_target_unavailable_vinsns
, expr
)
3768 target_available
= -1;
3770 /* If the availability of the EXPR is invalidated by the insertion of
3771 bookkeeping earlier, make sure that we won't choose this expr for
3772 scheduling if it's not separable, and if it is separable, then
3773 we have to recompute the set of available registers for it. */
3774 if (vinsn_vec_has_expr_p (vec_bookkeeping_blocked_vinsns
, expr
))
3776 vec_av_set
.unordered_remove (n
);
3777 if (sched_verbose
>= 4)
3778 sel_print ("Expr %d is blocked by bookkeeping inserted earlier\n",
3783 if (target_available
== true)
3785 /* Do nothing -- we can use an existing register. */
3786 is_orig_reg_p
= EXPR_SEPARABLE_P (expr
);
3788 else if (/* Non-separable instruction will never
3789 get another register. */
3790 (target_available
== false
3791 && !EXPR_SEPARABLE_P (expr
))
3792 /* Don't try to find a register for low-priority expression. */
3793 || (int) vec_av_set
.length () - 1 - n
>= max_insns_to_rename
3794 /* ??? FIXME: Don't try to rename data speculation. */
3795 || (EXPR_SPEC_DONE_DS (expr
) & BEGIN_DATA
)
3796 || ! find_best_reg_for_expr (expr
, bnds
, &is_orig_reg_p
))
3798 vec_av_set
.unordered_remove (n
);
3799 if (sched_verbose
>= 4)
3800 sel_print ("Expr %d has no suitable target register\n",
3803 /* A fence insn should not get here. */
3804 gcc_assert (!fence_insn_p
);
3808 /* At this point a fence insn should always be available. */
3809 gcc_assert (!fence_insn_p
3810 || INSN_UID (FENCE_INSN (fence
)) == INSN_UID (EXPR_INSN_RTX (expr
)));
3812 /* Filter expressions that need to be renamed or speculated when
3813 pipelining, because compensating register copies or speculation
3814 checks are likely to be placed near the beginning of the loop,
3816 if (pipelining_p
&& EXPR_ORIG_SCHED_CYCLE (expr
) > 0
3817 && (!is_orig_reg_p
|| EXPR_SPEC_DONE_DS (expr
) != 0))
3819 /* Estimation of number of cycles until loop branch for
3820 renaming/speculation to be successful. */
3821 int need_n_ticks_till_branch
= sel_vinsn_cost (EXPR_VINSN (expr
));
3823 if ((int) current_loop_nest
->ninsns
< 9)
3825 vec_av_set
.unordered_remove (n
);
3826 if (sched_verbose
>= 4)
3827 sel_print ("Pipelining expr %d will likely cause stall\n",
3832 if ((int) current_loop_nest
->ninsns
- num_insns_scheduled
3833 < need_n_ticks_till_branch
* issue_rate
/ 2
3834 && est_ticks_till_branch
< need_n_ticks_till_branch
)
3836 vec_av_set
.unordered_remove (n
);
3837 if (sched_verbose
>= 4)
3838 sel_print ("Pipelining expr %d will likely cause stall\n",
3844 /* We want to schedule speculation checks as late as possible. Discard
3845 them from av set if there are instructions with higher priority. */
3846 if (sel_insn_is_speculation_check (insn
)
3847 && EXPR_PRIORITY (expr
) < av_max_prio
)
3850 min_need_stall
= min_need_stall
< 0 ? 1 : MIN (min_need_stall
, 1);
3851 vec_av_set
.unordered_remove (n
);
3852 if (sched_verbose
>= 4)
3853 sel_print ("Delaying speculation check %d until its first use\n",
3858 /* Ignore EXPRs available from pipelining to update AV_MAX_PRIO. */
3859 if (EXPR_ORIG_SCHED_CYCLE (expr
) <= 0)
3860 av_max_prio
= MAX (av_max_prio
, EXPR_PRIORITY (expr
));
3862 /* Don't allow any insns whose data is not yet ready.
3863 Check first whether we've already tried them and failed. */
3864 if (INSN_UID (insn
) < FENCE_READY_TICKS_SIZE (fence
))
3866 need_cycles
= (FENCE_READY_TICKS (fence
)[INSN_UID (insn
)]
3867 - FENCE_CYCLE (fence
));
3868 if (EXPR_ORIG_SCHED_CYCLE (expr
) <= 0)
3869 est_ticks_till_branch
= MAX (est_ticks_till_branch
,
3870 EXPR_PRIORITY (expr
) + need_cycles
);
3872 if (need_cycles
> 0)
3875 min_need_stall
= (min_need_stall
< 0
3877 : MIN (min_need_stall
, need_cycles
));
3878 vec_av_set
.unordered_remove (n
);
3880 if (sched_verbose
>= 4)
3881 sel_print ("Expr %d is not ready until cycle %d (cached)\n",
3883 FENCE_READY_TICKS (fence
)[INSN_UID (insn
)]);
3888 /* Now resort to dependence analysis to find whether EXPR might be
3889 stalled due to dependencies from FENCE's context. */
3890 need_cycles
= tick_check_p (expr
, dc
, fence
);
3891 new_prio
= EXPR_PRIORITY (expr
) + EXPR_PRIORITY_ADJ (expr
) + need_cycles
;
3893 if (EXPR_ORIG_SCHED_CYCLE (expr
) <= 0)
3894 est_ticks_till_branch
= MAX (est_ticks_till_branch
,
3897 if (need_cycles
> 0)
3899 if (INSN_UID (insn
) >= FENCE_READY_TICKS_SIZE (fence
))
3901 int new_size
= INSN_UID (insn
) * 3 / 2;
3903 FENCE_READY_TICKS (fence
)
3904 = (int *) xrecalloc (FENCE_READY_TICKS (fence
),
3905 new_size
, FENCE_READY_TICKS_SIZE (fence
),
3908 FENCE_READY_TICKS (fence
)[INSN_UID (insn
)]
3909 = FENCE_CYCLE (fence
) + need_cycles
;
3912 min_need_stall
= (min_need_stall
< 0
3914 : MIN (min_need_stall
, need_cycles
));
3916 vec_av_set
.unordered_remove (n
);
3918 if (sched_verbose
>= 4)
3919 sel_print ("Expr %d is not ready yet until cycle %d\n",
3921 FENCE_READY_TICKS (fence
)[INSN_UID (insn
)]);
3925 if (sched_verbose
>= 4)
3926 sel_print ("Expr %d is ok\n", INSN_UID (insn
));
3930 /* Clear SCHED_NEXT. */
3931 if (FENCE_SCHED_NEXT (fence
))
3933 gcc_assert (sched_next_worked
== 1);
3934 FENCE_SCHED_NEXT (fence
) = NULL
;
3937 /* No need to stall if this variable was not initialized. */
3938 if (min_need_stall
< 0)
3941 if (vec_av_set
.is_empty ())
3943 /* We need to set *pneed_stall here, because later we skip this code
3944 when ready list is empty. */
3945 *pneed_stall
= min_need_stall
;
3949 gcc_assert (min_need_stall
== 0);
3951 /* Sort the vector. */
3952 vec_av_set
.qsort (sel_rank_for_schedule
);
3954 if (sched_verbose
>= 4)
3956 sel_print ("Total ready exprs: %d, stalled: %d\n",
3957 vec_av_set
.length (), stalled
);
3958 sel_print ("Sorted av set (%d): ", vec_av_set
.length ());
3959 FOR_EACH_VEC_ELT (vec_av_set
, n
, expr
)
3968 /* Convert a vectored and sorted av set to the ready list that
3969 the rest of the backend wants to see. */
3971 convert_vec_av_set_to_ready (void)
3976 /* Allocate and fill the ready list from the sorted vector. */
3977 ready
.n_ready
= vec_av_set
.length ();
3978 ready
.first
= ready
.n_ready
- 1;
3980 gcc_assert (ready
.n_ready
> 0);
3982 if (ready
.n_ready
> max_issue_size
)
3984 max_issue_size
= ready
.n_ready
;
3985 sched_extend_ready_list (ready
.n_ready
);
3988 FOR_EACH_VEC_ELT (vec_av_set
, n
, expr
)
3990 vinsn_t vi
= EXPR_VINSN (expr
);
3991 insn_t insn
= VINSN_INSN_RTX (vi
);
3994 ready
.vec
[n
] = insn
;
3998 /* Initialize ready list from *AV_PTR for the max_issue () call.
3999 If any unrecognizable insn found in *AV_PTR, return it (and skip
4000 max_issue). BND and FENCE are current boundary and fence,
4001 respectively. If we need to stall for some cycles before an expr
4002 from *AV_PTR would become available, write this number to *PNEED_STALL. */
4004 fill_ready_list (av_set_t
*av_ptr
, blist_t bnds
, fence_t fence
,
4009 /* We do not support multiple boundaries per fence. */
4010 gcc_assert (BLIST_NEXT (bnds
) == NULL
);
4012 /* Process expressions required special handling, i.e. pipelined,
4013 speculative and recog() < 0 expressions first. */
4014 process_pipelined_exprs (av_ptr
);
4015 process_spec_exprs (av_ptr
);
4017 /* A USE could be scheduled immediately. */
4018 expr
= process_use_exprs (av_ptr
);
4025 /* Turn the av set to a vector for sorting. */
4026 if (! fill_vec_av_set (*av_ptr
, bnds
, fence
, pneed_stall
))
4032 /* Build the final ready list. */
4033 convert_vec_av_set_to_ready ();
4037 /* Wrapper for dfa_new_cycle (). Returns TRUE if cycle was advanced. */
4039 sel_dfa_new_cycle (insn_t insn
, fence_t fence
)
4041 int last_scheduled_cycle
= FENCE_LAST_SCHEDULED_INSN (fence
)
4042 ? INSN_SCHED_CYCLE (FENCE_LAST_SCHEDULED_INSN (fence
))
4043 : FENCE_CYCLE (fence
) - 1;
4047 if (!targetm
.sched
.dfa_new_cycle
)
4050 memcpy (curr_state
, FENCE_STATE (fence
), dfa_state_size
);
4052 while (!sort_p
&& targetm
.sched
.dfa_new_cycle (sched_dump
, sched_verbose
,
4053 insn
, last_scheduled_cycle
,
4054 FENCE_CYCLE (fence
), &sort_p
))
4056 memcpy (FENCE_STATE (fence
), curr_state
, dfa_state_size
);
4057 advance_one_cycle (fence
);
4058 memcpy (curr_state
, FENCE_STATE (fence
), dfa_state_size
);
4065 /* Invoke reorder* target hooks on the ready list. Return the number of insns
4066 we can issue. FENCE is the current fence. */
4068 invoke_reorder_hooks (fence_t fence
)
4071 bool ran_hook
= false;
4073 /* Call the reorder hook at the beginning of the cycle, and call
4074 the reorder2 hook in the middle of the cycle. */
4075 if (FENCE_ISSUED_INSNS (fence
) == 0)
4077 if (targetm
.sched
.reorder
4078 && !SCHED_GROUP_P (ready_element (&ready
, 0))
4079 && ready
.n_ready
> 1)
4081 /* Don't give reorder the most prioritized insn as it can break
4087 = targetm
.sched
.reorder (sched_dump
, sched_verbose
,
4088 ready_lastpos (&ready
),
4089 &ready
.n_ready
, FENCE_CYCLE (fence
));
4097 /* Initialize can_issue_more for variable_issue. */
4098 issue_more
= issue_rate
;
4100 else if (targetm
.sched
.reorder2
4101 && !SCHED_GROUP_P (ready_element (&ready
, 0)))
4103 if (ready
.n_ready
== 1)
4105 targetm
.sched
.reorder2 (sched_dump
, sched_verbose
,
4106 ready_lastpos (&ready
),
4107 &ready
.n_ready
, FENCE_CYCLE (fence
));
4114 targetm
.sched
.reorder2 (sched_dump
, sched_verbose
,
4116 ? ready_lastpos (&ready
) : NULL
,
4117 &ready
.n_ready
, FENCE_CYCLE (fence
));
4126 issue_more
= FENCE_ISSUE_MORE (fence
);
4128 /* Ensure that ready list and vec_av_set are in line with each other,
4129 i.e. vec_av_set[i] == ready_element (&ready, i). */
4130 if (issue_more
&& ran_hook
)
4133 rtx_insn
**arr
= ready
.vec
;
4134 expr_t
*vec
= vec_av_set
.address ();
4136 for (i
= 0, n
= ready
.n_ready
; i
< n
; i
++)
4137 if (EXPR_INSN_RTX (vec
[i
]) != arr
[i
])
4139 for (j
= i
; j
< n
; j
++)
4140 if (EXPR_INSN_RTX (vec
[j
]) == arr
[i
])
4144 std::swap (vec
[i
], vec
[j
]);
4151 /* Return an EXPR corresponding to INDEX element of ready list, if
4152 FOLLOW_READY_ELEMENT is true (i.e., an expr of
4153 ready_element (&ready, INDEX) will be returned), and to INDEX element of
4154 ready.vec otherwise. */
4155 static inline expr_t
4156 find_expr_for_ready (int index
, bool follow_ready_element
)
4161 real_index
= follow_ready_element
? ready
.first
- index
: index
;
4163 expr
= vec_av_set
[real_index
];
4164 gcc_assert (ready
.vec
[real_index
] == EXPR_INSN_RTX (expr
));
4169 /* Calculate insns worth trying via lookahead_guard hook. Return a number
4170 of such insns found. */
4172 invoke_dfa_lookahead_guard (void)
4176 = targetm
.sched
.first_cycle_multipass_dfa_lookahead_guard
!= NULL
;
4178 if (sched_verbose
>= 2)
4179 sel_print ("ready after reorder: ");
4181 for (i
= 0, n
= 0; i
< ready
.n_ready
; i
++)
4187 /* In this loop insn is Ith element of the ready list given by
4188 ready_element, not Ith element of ready.vec. */
4189 insn
= ready_element (&ready
, i
);
4191 if (! have_hook
|| i
== 0)
4194 r
= targetm
.sched
.first_cycle_multipass_dfa_lookahead_guard (insn
, i
);
4196 gcc_assert (INSN_CODE (insn
) >= 0);
4198 /* Only insns with ready_try = 0 can get here
4199 from fill_ready_list. */
4200 gcc_assert (ready_try
[i
] == 0);
4205 expr
= find_expr_for_ready (i
, true);
4207 if (sched_verbose
>= 2)
4209 dump_vinsn (EXPR_VINSN (expr
));
4210 sel_print (":%d; ", ready_try
[i
]);
4214 if (sched_verbose
>= 2)
4219 /* Calculate the number of privileged insns and return it. */
4221 calculate_privileged_insns (void)
4223 expr_t cur_expr
, min_spec_expr
= NULL
;
4224 int privileged_n
= 0, i
;
4226 for (i
= 0; i
< ready
.n_ready
; i
++)
4231 if (! min_spec_expr
)
4232 min_spec_expr
= find_expr_for_ready (i
, true);
4234 cur_expr
= find_expr_for_ready (i
, true);
4236 if (EXPR_SPEC (cur_expr
) > EXPR_SPEC (min_spec_expr
))
4242 if (i
== ready
.n_ready
)
4245 if (sched_verbose
>= 2)
4246 sel_print ("privileged_n: %d insns with SPEC %d\n",
4247 privileged_n
, privileged_n
? EXPR_SPEC (min_spec_expr
) : -1);
4248 return privileged_n
;
4251 /* Call the rest of the hooks after the choice was made. Return
4252 the number of insns that still can be issued given that the current
4253 number is ISSUE_MORE. FENCE and BEST_INSN are the current fence
4254 and the insn chosen for scheduling, respectively. */
4256 invoke_aftermath_hooks (fence_t fence
, rtx_insn
*best_insn
, int issue_more
)
4258 gcc_assert (INSN_P (best_insn
));
4260 /* First, call dfa_new_cycle, and then variable_issue, if available. */
4261 sel_dfa_new_cycle (best_insn
, fence
);
4263 if (targetm
.sched
.variable_issue
)
4265 memcpy (curr_state
, FENCE_STATE (fence
), dfa_state_size
);
4267 targetm
.sched
.variable_issue (sched_dump
, sched_verbose
, best_insn
,
4269 memcpy (FENCE_STATE (fence
), curr_state
, dfa_state_size
);
4271 else if (!DEBUG_INSN_P (best_insn
)
4272 && GET_CODE (PATTERN (best_insn
)) != USE
4273 && GET_CODE (PATTERN (best_insn
)) != CLOBBER
)
4279 /* Estimate the cost of issuing INSN on DFA state STATE. */
4281 estimate_insn_cost (rtx_insn
*insn
, state_t state
)
4283 static state_t temp
= NULL
;
4287 temp
= xmalloc (dfa_state_size
);
4289 memcpy (temp
, state
, dfa_state_size
);
4290 cost
= state_transition (temp
, insn
);
4299 /* Return the cost of issuing EXPR on the FENCE as estimated by DFA.
4300 This function properly handles ASMs, USEs etc. */
4302 get_expr_cost (expr_t expr
, fence_t fence
)
4304 rtx_insn
*insn
= EXPR_INSN_RTX (expr
);
4306 if (recog_memoized (insn
) < 0)
4308 if (!FENCE_STARTS_CYCLE_P (fence
)
4309 && INSN_ASM_P (insn
))
4310 /* This is asm insn which is tryed to be issued on the
4311 cycle not first. Issue it on the next cycle. */
4314 /* A USE insn, or something else we don't need to
4315 understand. We can't pass these directly to
4316 state_transition because it will trigger a
4317 fatal error for unrecognizable insns. */
4321 return estimate_insn_cost (insn
, FENCE_STATE (fence
));
4324 /* Find the best insn for scheduling, either via max_issue or just take
4325 the most prioritized available. */
4327 choose_best_insn (fence_t fence
, int privileged_n
, int *index
)
4331 if (dfa_lookahead
> 0)
4333 cycle_issued_insns
= FENCE_ISSUED_INSNS (fence
);
4334 /* TODO: pass equivalent of first_cycle_insn_p to max_issue (). */
4335 can_issue
= max_issue (&ready
, privileged_n
,
4336 FENCE_STATE (fence
), true, index
);
4337 if (sched_verbose
>= 2)
4338 sel_print ("max_issue: we can issue %d insns, already did %d insns\n",
4339 can_issue
, FENCE_ISSUED_INSNS (fence
));
4343 /* We can't use max_issue; just return the first available element. */
4346 for (i
= 0; i
< ready
.n_ready
; i
++)
4348 expr_t expr
= find_expr_for_ready (i
, true);
4350 if (get_expr_cost (expr
, fence
) < 1)
4352 can_issue
= can_issue_more
;
4355 if (sched_verbose
>= 2)
4356 sel_print ("using %dth insn from the ready list\n", i
+ 1);
4362 if (i
== ready
.n_ready
)
4372 /* Choose the best expr from *AV_VLIW_PTR and a suitable register for it.
4373 BNDS and FENCE are current boundaries and scheduling fence respectively.
4374 Return the expr found and NULL if nothing can be issued atm.
4375 Write to PNEED_STALL the number of cycles to stall if no expr was found. */
4377 find_best_expr (av_set_t
*av_vliw_ptr
, blist_t bnds
, fence_t fence
,
4382 /* Choose the best insn for scheduling via:
4383 1) sorting the ready list based on priority;
4384 2) calling the reorder hook;
4385 3) calling max_issue. */
4386 best
= fill_ready_list (av_vliw_ptr
, bnds
, fence
, pneed_stall
);
4387 if (best
== NULL
&& ready
.n_ready
> 0)
4389 int privileged_n
, index
;
4391 can_issue_more
= invoke_reorder_hooks (fence
);
4392 if (can_issue_more
> 0)
4394 /* Try choosing the best insn until we find one that is could be
4395 scheduled due to liveness restrictions on its destination register.
4396 In the future, we'd like to choose once and then just probe insns
4397 in the order of their priority. */
4398 invoke_dfa_lookahead_guard ();
4399 privileged_n
= calculate_privileged_insns ();
4400 can_issue_more
= choose_best_insn (fence
, privileged_n
, &index
);
4402 best
= find_expr_for_ready (index
, true);
4404 /* We had some available insns, so if we can't issue them,
4406 if (can_issue_more
== 0)
4415 can_issue_more
= invoke_aftermath_hooks (fence
, EXPR_INSN_RTX (best
),
4417 if (targetm
.sched
.variable_issue
4418 && can_issue_more
== 0)
4422 if (sched_verbose
>= 2)
4426 sel_print ("Best expression (vliw form): ");
4428 sel_print ("; cycle %d\n", FENCE_CYCLE (fence
));
4431 sel_print ("No best expr found!\n");
4438 /* Functions that implement the core of the scheduler. */
4441 /* Emit an instruction from EXPR with SEQNO and VINSN after
4444 emit_insn_from_expr_after (expr_t expr
, vinsn_t vinsn
, int seqno
,
4445 insn_t place_to_insert
)
4447 /* This assert fails when we have identical instructions
4448 one of which dominates the other. In this case move_op ()
4449 finds the first instruction and doesn't search for second one.
4450 The solution would be to compute av_set after the first found
4451 insn and, if insn present in that set, continue searching.
4452 For now we workaround this issue in move_op. */
4453 gcc_assert (!INSN_IN_STREAM_P (EXPR_INSN_RTX (expr
)));
4455 if (EXPR_WAS_RENAMED (expr
))
4457 unsigned regno
= expr_dest_regno (expr
);
4459 if (HARD_REGISTER_NUM_P (regno
))
4461 df_set_regs_ever_live (regno
, true);
4462 reg_rename_tick
[regno
] = ++reg_rename_this_tick
;
4466 return sel_gen_insn_from_expr_after (expr
, vinsn
, seqno
,
4470 /* Return TRUE if BB can hold bookkeeping code. */
4472 block_valid_for_bookkeeping_p (basic_block bb
)
4474 insn_t bb_end
= BB_END (bb
);
4476 if (!in_current_region_p (bb
) || EDGE_COUNT (bb
->succs
) > 1)
4479 if (INSN_P (bb_end
))
4481 if (INSN_SCHED_TIMES (bb_end
) > 0)
4485 gcc_assert (NOTE_INSN_BASIC_BLOCK_P (bb_end
));
4490 /* Attempt to find a block that can hold bookkeeping code for path(s) incoming
4491 into E2->dest, except from E1->src (there may be a sequence of empty basic
4492 blocks between E1->src and E2->dest). Return found block, or NULL if new
4493 one must be created. If LAX holds, don't assume there is a simple path
4494 from E1->src to E2->dest. */
4496 find_block_for_bookkeeping (edge e1
, edge e2
, bool lax
)
4498 basic_block candidate_block
= NULL
;
4501 /* Loop over edges from E1 to E2, inclusive. */
4502 for (e
= e1
; !lax
|| e
->dest
!= EXIT_BLOCK_PTR_FOR_FN (cfun
); e
=
4503 EDGE_SUCC (e
->dest
, 0))
4505 if (EDGE_COUNT (e
->dest
->preds
) == 2)
4507 if (candidate_block
== NULL
)
4508 candidate_block
= (EDGE_PRED (e
->dest
, 0) == e
4509 ? EDGE_PRED (e
->dest
, 1)->src
4510 : EDGE_PRED (e
->dest
, 0)->src
);
4512 /* Found additional edge leading to path from e1 to e2
4516 else if (EDGE_COUNT (e
->dest
->preds
) > 2)
4517 /* Several edges leading to path from e1 to e2 from aside. */
4521 return ((!lax
|| candidate_block
)
4522 && block_valid_for_bookkeeping_p (candidate_block
)
4526 if (lax
&& EDGE_COUNT (e
->dest
->succs
) != 1)
4536 /* Create new basic block for bookkeeping code for path(s) incoming into
4537 E2->dest, except from E1->src. Return created block. */
4539 create_block_for_bookkeeping (edge e1
, edge e2
)
4541 basic_block new_bb
, bb
= e2
->dest
;
4543 /* Check that we don't spoil the loop structure. */
4544 if (current_loop_nest
)
4546 basic_block latch
= current_loop_nest
->latch
;
4548 /* We do not split header. */
4549 gcc_assert (e2
->dest
!= current_loop_nest
->header
);
4551 /* We do not redirect the only edge to the latch block. */
4552 gcc_assert (e1
->dest
!= latch
4553 || !single_pred_p (latch
)
4554 || e1
!= single_pred_edge (latch
));
4557 /* Split BB to insert BOOK_INSN there. */
4558 new_bb
= sched_split_block (bb
, NULL
);
4560 /* Move note_list from the upper bb. */
4561 gcc_assert (BB_NOTE_LIST (new_bb
) == NULL_RTX
);
4562 BB_NOTE_LIST (new_bb
) = BB_NOTE_LIST (bb
);
4563 BB_NOTE_LIST (bb
) = NULL
;
4565 gcc_assert (e2
->dest
== bb
);
4567 /* Skip block for bookkeeping copy when leaving E1->src. */
4568 if (e1
->flags
& EDGE_FALLTHRU
)
4569 sel_redirect_edge_and_branch_force (e1
, new_bb
);
4571 sel_redirect_edge_and_branch (e1
, new_bb
);
4573 gcc_assert (e1
->dest
== new_bb
);
4574 gcc_assert (sel_bb_empty_p (bb
));
4576 /* To keep basic block numbers in sync between debug and non-debug
4577 compilations, we have to rotate blocks here. Consider that we
4578 started from (a,b)->d, (c,d)->e, and d contained only debug
4579 insns. It would have been removed before if the debug insns
4580 weren't there, so we'd have split e rather than d. So what we do
4581 now is to swap the block numbers of new_bb and
4582 single_succ(new_bb) == e, so that the insns that were in e before
4583 get the new block number. */
4585 if (MAY_HAVE_DEBUG_INSNS
)
4588 insn_t insn
= sel_bb_head (new_bb
);
4591 if (DEBUG_INSN_P (insn
)
4592 && single_succ_p (new_bb
)
4593 && (succ
= single_succ (new_bb
))
4594 && succ
!= EXIT_BLOCK_PTR_FOR_FN (cfun
)
4595 && DEBUG_INSN_P ((last
= sel_bb_end (new_bb
))))
4597 while (insn
!= last
&& (DEBUG_INSN_P (insn
) || NOTE_P (insn
)))
4598 insn
= NEXT_INSN (insn
);
4602 sel_global_bb_info_def gbi
;
4603 sel_region_bb_info_def rbi
;
4605 if (sched_verbose
>= 2)
4606 sel_print ("Swapping block ids %i and %i\n",
4607 new_bb
->index
, succ
->index
);
4609 std::swap (new_bb
->index
, succ
->index
);
4611 SET_BASIC_BLOCK_FOR_FN (cfun
, new_bb
->index
, new_bb
);
4612 SET_BASIC_BLOCK_FOR_FN (cfun
, succ
->index
, succ
);
4614 memcpy (&gbi
, SEL_GLOBAL_BB_INFO (new_bb
), sizeof (gbi
));
4615 memcpy (SEL_GLOBAL_BB_INFO (new_bb
), SEL_GLOBAL_BB_INFO (succ
),
4617 memcpy (SEL_GLOBAL_BB_INFO (succ
), &gbi
, sizeof (gbi
));
4619 memcpy (&rbi
, SEL_REGION_BB_INFO (new_bb
), sizeof (rbi
));
4620 memcpy (SEL_REGION_BB_INFO (new_bb
), SEL_REGION_BB_INFO (succ
),
4622 memcpy (SEL_REGION_BB_INFO (succ
), &rbi
, sizeof (rbi
));
4624 std::swap (BLOCK_TO_BB (new_bb
->index
),
4625 BLOCK_TO_BB (succ
->index
));
4627 std::swap (CONTAINING_RGN (new_bb
->index
),
4628 CONTAINING_RGN (succ
->index
));
4630 for (int i
= 0; i
< current_nr_blocks
; i
++)
4631 if (BB_TO_BLOCK (i
) == succ
->index
)
4632 BB_TO_BLOCK (i
) = new_bb
->index
;
4633 else if (BB_TO_BLOCK (i
) == new_bb
->index
)
4634 BB_TO_BLOCK (i
) = succ
->index
;
4636 FOR_BB_INSNS (new_bb
, insn
)
4638 EXPR_ORIG_BB_INDEX (INSN_EXPR (insn
)) = new_bb
->index
;
4640 FOR_BB_INSNS (succ
, insn
)
4642 EXPR_ORIG_BB_INDEX (INSN_EXPR (insn
)) = succ
->index
;
4644 if (bitmap_clear_bit (code_motion_visited_blocks
, new_bb
->index
))
4645 bitmap_set_bit (code_motion_visited_blocks
, succ
->index
);
4647 gcc_assert (LABEL_P (BB_HEAD (new_bb
))
4648 && LABEL_P (BB_HEAD (succ
)));
4650 if (sched_verbose
>= 4)
4651 sel_print ("Swapping code labels %i and %i\n",
4652 CODE_LABEL_NUMBER (BB_HEAD (new_bb
)),
4653 CODE_LABEL_NUMBER (BB_HEAD (succ
)));
4655 std::swap (CODE_LABEL_NUMBER (BB_HEAD (new_bb
)),
4656 CODE_LABEL_NUMBER (BB_HEAD (succ
)));
4664 /* Return insn after which we must insert bookkeeping code for path(s) incoming
4665 into E2->dest, except from E1->src. If the returned insn immediately
4666 precedes a fence, assign that fence to *FENCE_TO_REWIND. */
4668 find_place_for_bookkeeping (edge e1
, edge e2
, fence_t
*fence_to_rewind
)
4670 insn_t place_to_insert
;
4671 /* Find a basic block that can hold bookkeeping. If it can be found, do not
4672 create new basic block, but insert bookkeeping there. */
4673 basic_block book_block
= find_block_for_bookkeeping (e1
, e2
, FALSE
);
4677 place_to_insert
= BB_END (book_block
);
4679 /* Don't use a block containing only debug insns for
4680 bookkeeping, this causes scheduling differences between debug
4681 and non-debug compilations, for the block would have been
4683 if (DEBUG_INSN_P (place_to_insert
))
4685 rtx_insn
*insn
= sel_bb_head (book_block
);
4687 while (insn
!= place_to_insert
&&
4688 (DEBUG_INSN_P (insn
) || NOTE_P (insn
)))
4689 insn
= NEXT_INSN (insn
);
4691 if (insn
== place_to_insert
)
4698 book_block
= create_block_for_bookkeeping (e1
, e2
);
4699 place_to_insert
= BB_END (book_block
);
4700 if (sched_verbose
>= 9)
4701 sel_print ("New block is %i, split from bookkeeping block %i\n",
4702 EDGE_SUCC (book_block
, 0)->dest
->index
, book_block
->index
);
4706 if (sched_verbose
>= 9)
4707 sel_print ("Pre-existing bookkeeping block is %i\n", book_block
->index
);
4710 *fence_to_rewind
= NULL
;
4711 /* If basic block ends with a jump, insert bookkeeping code right before it.
4712 Notice if we are crossing a fence when taking PREV_INSN. */
4713 if (INSN_P (place_to_insert
) && control_flow_insn_p (place_to_insert
))
4715 *fence_to_rewind
= flist_lookup (fences
, place_to_insert
);
4716 place_to_insert
= PREV_INSN (place_to_insert
);
4719 return place_to_insert
;
4722 /* Find a proper seqno for bookkeeing insn inserted at PLACE_TO_INSERT
4725 find_seqno_for_bookkeeping (insn_t place_to_insert
, insn_t join_point
)
4729 /* Check if we are about to insert bookkeeping copy before a jump, and use
4730 jump's seqno for the copy; otherwise, use JOIN_POINT's seqno. */
4731 rtx_insn
*next
= NEXT_INSN (place_to_insert
);
4734 && BLOCK_FOR_INSN (next
) == BLOCK_FOR_INSN (place_to_insert
))
4736 gcc_assert (INSN_SCHED_TIMES (next
) == 0);
4737 seqno
= INSN_SEQNO (next
);
4739 else if (INSN_SEQNO (join_point
) > 0)
4740 seqno
= INSN_SEQNO (join_point
);
4743 seqno
= get_seqno_by_preds (place_to_insert
);
4745 /* Sometimes the fences can move in such a way that there will be
4746 no instructions with positive seqno around this bookkeeping.
4747 This means that there will be no way to get to it by a regular
4748 fence movement. Never mind because we pick up such pieces for
4749 rescheduling anyways, so any positive value will do for now. */
4752 gcc_assert (pipelining_p
);
4757 gcc_assert (seqno
> 0);
4761 /* Insert bookkeeping copy of C_EXPS's insn after PLACE_TO_INSERT, assigning
4762 NEW_SEQNO to it. Return created insn. */
4764 emit_bookkeeping_insn (insn_t place_to_insert
, expr_t c_expr
, int new_seqno
)
4766 rtx_insn
*new_insn_rtx
= create_copy_of_insn_rtx (EXPR_INSN_RTX (c_expr
));
4769 = create_vinsn_from_insn_rtx (new_insn_rtx
,
4770 VINSN_UNIQUE_P (EXPR_VINSN (c_expr
)));
4772 insn_t new_insn
= emit_insn_from_expr_after (c_expr
, new_vinsn
, new_seqno
,
4775 INSN_SCHED_TIMES (new_insn
) = 0;
4776 bitmap_set_bit (current_copies
, INSN_UID (new_insn
));
4781 /* Generate a bookkeeping copy of C_EXPR's insn for path(s) incoming into to
4782 E2->dest, except from E1->src (there may be a sequence of empty blocks
4783 between E1->src and E2->dest). Return block containing the copy.
4784 All scheduler data is initialized for the newly created insn. */
4786 generate_bookkeeping_insn (expr_t c_expr
, edge e1
, edge e2
)
4788 insn_t join_point
, place_to_insert
, new_insn
;
4790 bool need_to_exchange_data_sets
;
4791 fence_t fence_to_rewind
;
4793 if (sched_verbose
>= 4)
4794 sel_print ("Generating bookkeeping insn (%d->%d)\n", e1
->src
->index
,
4797 join_point
= sel_bb_head (e2
->dest
);
4798 place_to_insert
= find_place_for_bookkeeping (e1
, e2
, &fence_to_rewind
);
4799 new_seqno
= find_seqno_for_bookkeeping (place_to_insert
, join_point
);
4800 need_to_exchange_data_sets
4801 = sel_bb_empty_p (BLOCK_FOR_INSN (place_to_insert
));
4803 new_insn
= emit_bookkeeping_insn (place_to_insert
, c_expr
, new_seqno
);
4805 if (fence_to_rewind
)
4806 FENCE_INSN (fence_to_rewind
) = new_insn
;
4808 /* When inserting bookkeeping insn in new block, av sets should be
4809 following: old basic block (that now holds bookkeeping) data sets are
4810 the same as was before generation of bookkeeping, and new basic block
4811 (that now hold all other insns of old basic block) data sets are
4812 invalid. So exchange data sets for these basic blocks as sel_split_block
4813 mistakenly exchanges them in this case. Cannot do it earlier because
4814 when single instruction is added to new basic block it should hold NULL
4816 if (need_to_exchange_data_sets
)
4817 exchange_data_sets (BLOCK_FOR_INSN (new_insn
),
4818 BLOCK_FOR_INSN (join_point
));
4820 stat_bookkeeping_copies
++;
4821 return BLOCK_FOR_INSN (new_insn
);
4824 /* Remove from AV_PTR all insns that may need bookkeeping when scheduling
4825 on FENCE, but we are unable to copy them. */
4827 remove_insns_that_need_bookkeeping (fence_t fence
, av_set_t
*av_ptr
)
4832 /* An expression does not need bookkeeping if it is available on all paths
4833 from current block to original block and current block dominates
4834 original block. We check availability on all paths by examining
4835 EXPR_SPEC; this is not equivalent, because it may be positive even
4836 if expr is available on all paths (but if expr is not available on
4837 any path, EXPR_SPEC will be positive). */
4839 FOR_EACH_EXPR_1 (expr
, i
, av_ptr
)
4841 if (!control_flow_insn_p (EXPR_INSN_RTX (expr
))
4842 && (!bookkeeping_p
|| VINSN_UNIQUE_P (EXPR_VINSN (expr
)))
4843 && (EXPR_SPEC (expr
)
4844 || !EXPR_ORIG_BB_INDEX (expr
)
4845 || !dominated_by_p (CDI_DOMINATORS
,
4846 BASIC_BLOCK_FOR_FN (cfun
,
4847 EXPR_ORIG_BB_INDEX (expr
)),
4848 BLOCK_FOR_INSN (FENCE_INSN (fence
)))))
4850 if (sched_verbose
>= 4)
4851 sel_print ("Expr %d removed because it would need bookkeeping, which "
4852 "cannot be created\n", INSN_UID (EXPR_INSN_RTX (expr
)));
4853 av_set_iter_remove (&i
);
4858 /* Moving conditional jump through some instructions.
4862 ... <- current scheduling point
4863 NOTE BASIC BLOCK: <- bb header
4864 (p8) add r14=r14+0x9;;
4870 We can schedule jump one cycle earlier, than mov, because they cannot be
4871 executed together as their predicates are mutually exclusive.
4873 This is done in this way: first, new fallthrough basic block is created
4874 after jump (it is always can be done, because there already should be a
4875 fallthrough block, where control flow goes in case of predicate being true -
4876 in our example; otherwise there should be a dependence between those
4877 instructions and jump and we cannot schedule jump right now);
4878 next, all instructions between jump and current scheduling point are moved
4879 to this new block. And the result is this:
4882 (!p8) jump L1 <- current scheduling point
4883 NOTE BASIC BLOCK: <- bb header
4884 (p8) add r14=r14+0x9;;
4890 move_cond_jump (rtx_insn
*insn
, bnd_t bnd
)
4893 basic_block block_from
, block_next
, block_new
, block_bnd
, bb
;
4894 rtx_insn
*next
, *prev
, *link
, *head
;
4896 block_from
= BLOCK_FOR_INSN (insn
);
4897 block_bnd
= BLOCK_FOR_INSN (BND_TO (bnd
));
4898 prev
= BND_TO (bnd
);
4900 /* Moving of jump should not cross any other jumps or beginnings of new
4901 basic blocks. The only exception is when we move a jump through
4902 mutually exclusive insns along fallthru edges. */
4903 if (flag_checking
&& block_from
!= block_bnd
)
4906 for (link
= PREV_INSN (insn
); link
!= PREV_INSN (prev
);
4907 link
= PREV_INSN (link
))
4910 gcc_assert (sched_insns_conditions_mutex_p (insn
, link
));
4911 if (BLOCK_FOR_INSN (link
) && BLOCK_FOR_INSN (link
) != bb
)
4913 gcc_assert (single_pred (bb
) == BLOCK_FOR_INSN (link
));
4914 bb
= BLOCK_FOR_INSN (link
);
4919 /* Jump is moved to the boundary. */
4920 next
= PREV_INSN (insn
);
4921 BND_TO (bnd
) = insn
;
4923 ft_edge
= find_fallthru_edge_from (block_from
);
4924 block_next
= ft_edge
->dest
;
4925 /* There must be a fallthrough block (or where should go
4926 control flow in case of false jump predicate otherwise?). */
4927 gcc_assert (block_next
);
4929 /* Create new empty basic block after source block. */
4930 block_new
= sel_split_edge (ft_edge
);
4931 gcc_assert (block_new
->next_bb
== block_next
4932 && block_from
->next_bb
== block_new
);
4934 /* Move all instructions except INSN to BLOCK_NEW. */
4936 head
= BB_HEAD (block_new
);
4937 while (bb
!= block_from
->next_bb
)
4939 rtx_insn
*from
, *to
;
4940 from
= bb
== block_bnd
? prev
: sel_bb_head (bb
);
4941 to
= bb
== block_from
? next
: sel_bb_end (bb
);
4943 /* The jump being moved can be the first insn in the block.
4944 In this case we don't have to move anything in this block. */
4945 if (NEXT_INSN (to
) != from
)
4947 reorder_insns (from
, to
, head
);
4949 for (link
= to
; link
!= head
; link
= PREV_INSN (link
))
4950 EXPR_ORIG_BB_INDEX (INSN_EXPR (link
)) = block_new
->index
;
4954 /* Cleanup possibly empty blocks left. */
4955 block_next
= bb
->next_bb
;
4956 if (bb
!= block_from
)
4957 tidy_control_flow (bb
, false);
4961 /* Assert there is no jump to BLOCK_NEW, only fallthrough edge. */
4962 gcc_assert (NOTE_INSN_BASIC_BLOCK_P (BB_HEAD (block_new
)));
4964 gcc_assert (!sel_bb_empty_p (block_from
)
4965 && !sel_bb_empty_p (block_new
));
4967 /* Update data sets for BLOCK_NEW to represent that INSN and
4968 instructions from the other branch of INSN is no longer
4969 available at BLOCK_NEW. */
4970 BB_AV_LEVEL (block_new
) = global_level
;
4971 gcc_assert (BB_LV_SET (block_new
) == NULL
);
4972 BB_LV_SET (block_new
) = get_clear_regset_from_pool ();
4973 update_data_sets (sel_bb_head (block_new
));
4975 /* INSN is a new basic block header - so prepare its data
4976 structures and update availability and liveness sets. */
4977 update_data_sets (insn
);
4979 if (sched_verbose
>= 4)
4980 sel_print ("Moving jump %d\n", INSN_UID (insn
));
4983 /* Remove nops generated during move_op for preventing removal of empty
4986 remove_temp_moveop_nops (bool full_tidying
)
4991 FOR_EACH_VEC_ELT (vec_temp_moveop_nops
, i
, insn
)
4993 gcc_assert (INSN_NOP_P (insn
));
4994 return_nop_to_pool (insn
, full_tidying
);
4997 /* Empty the vector. */
4998 if (vec_temp_moveop_nops
.length () > 0)
4999 vec_temp_moveop_nops
.block_remove (0, vec_temp_moveop_nops
.length ());
5002 /* Records the maximal UID before moving up an instruction. Used for
5003 distinguishing between bookkeeping copies and original insns. */
5004 static int max_uid_before_move_op
= 0;
5006 /* When true, we're always scheduling next insn on the already scheduled code
5007 to get the right insn data for the following bundling or other passes. */
5008 static int force_next_insn
= 0;
5010 /* Remove from AV_VLIW_P all instructions but next when debug counter
5011 tells us so. Next instruction is fetched from BNDS. */
5013 remove_insns_for_debug (blist_t bnds
, av_set_t
*av_vliw_p
)
5015 if (! dbg_cnt (sel_sched_insn_cnt
) || force_next_insn
)
5016 /* Leave only the next insn in av_vliw. */
5018 av_set_iterator av_it
;
5020 bnd_t bnd
= BLIST_BND (bnds
);
5021 insn_t next
= BND_TO (bnd
);
5023 gcc_assert (BLIST_NEXT (bnds
) == NULL
);
5025 FOR_EACH_EXPR_1 (expr
, av_it
, av_vliw_p
)
5026 if (EXPR_INSN_RTX (expr
) != next
)
5027 av_set_iter_remove (&av_it
);
5031 /* Compute available instructions on BNDS. FENCE is the current fence. Write
5032 the computed set to *AV_VLIW_P. */
5034 compute_av_set_on_boundaries (fence_t fence
, blist_t bnds
, av_set_t
*av_vliw_p
)
5036 if (sched_verbose
>= 2)
5038 sel_print ("Boundaries: ");
5043 for (; bnds
; bnds
= BLIST_NEXT (bnds
))
5045 bnd_t bnd
= BLIST_BND (bnds
);
5047 insn_t bnd_to
= BND_TO (bnd
);
5049 /* Rewind BND->TO to the basic block header in case some bookkeeping
5050 instructions were inserted before BND->TO and it needs to be
5052 if (sel_bb_head_p (bnd_to
))
5053 gcc_assert (INSN_SCHED_TIMES (bnd_to
) == 0);
5055 while (INSN_SCHED_TIMES (PREV_INSN (bnd_to
)) == 0)
5057 bnd_to
= PREV_INSN (bnd_to
);
5058 if (sel_bb_head_p (bnd_to
))
5062 if (BND_TO (bnd
) != bnd_to
)
5064 gcc_assert (FENCE_INSN (fence
) == BND_TO (bnd
));
5065 FENCE_INSN (fence
) = bnd_to
;
5066 BND_TO (bnd
) = bnd_to
;
5069 av_set_clear (&BND_AV (bnd
));
5070 BND_AV (bnd
) = compute_av_set (BND_TO (bnd
), NULL
, 0, true);
5072 av_set_clear (&BND_AV1 (bnd
));
5073 BND_AV1 (bnd
) = av_set_copy (BND_AV (bnd
));
5075 moveup_set_inside_insn_group (&BND_AV1 (bnd
), NULL
);
5077 av1_copy
= av_set_copy (BND_AV1 (bnd
));
5078 av_set_union_and_clear (av_vliw_p
, &av1_copy
, NULL
);
5081 if (sched_verbose
>= 2)
5083 sel_print ("Available exprs (vliw form): ");
5084 dump_av_set (*av_vliw_p
);
5089 /* Calculate the sequential av set on BND corresponding to the EXPR_VLIW
5090 expression. When FOR_MOVEOP is true, also replace the register of
5091 expressions found with the register from EXPR_VLIW. */
5093 find_sequential_best_exprs (bnd_t bnd
, expr_t expr_vliw
, bool for_moveop
)
5095 av_set_t expr_seq
= NULL
;
5099 FOR_EACH_EXPR (expr
, i
, BND_AV (bnd
))
5101 if (equal_after_moveup_path_p (expr
, NULL
, expr_vliw
))
5105 /* The sequential expression has the right form to pass
5106 to move_op except when renaming happened. Put the
5107 correct register in EXPR then. */
5108 if (EXPR_SEPARABLE_P (expr
) && REG_P (EXPR_LHS (expr
)))
5110 if (expr_dest_regno (expr
) != expr_dest_regno (expr_vliw
))
5112 replace_dest_with_reg_in_expr (expr
, EXPR_LHS (expr_vliw
));
5113 stat_renamed_scheduled
++;
5115 /* Also put the correct TARGET_AVAILABLE bit on the expr.
5116 This is needed when renaming came up with original
5118 else if (EXPR_TARGET_AVAILABLE (expr
)
5119 != EXPR_TARGET_AVAILABLE (expr_vliw
))
5121 gcc_assert (EXPR_TARGET_AVAILABLE (expr_vliw
) == 1);
5122 EXPR_TARGET_AVAILABLE (expr
) = 1;
5125 if (EXPR_WAS_SUBSTITUTED (expr
))
5126 stat_substitutions_total
++;
5129 av_set_add (&expr_seq
, expr
);
5131 /* With substitution inside insn group, it is possible
5132 that more than one expression in expr_seq will correspond
5133 to expr_vliw. In this case, choose one as the attempt to
5134 move both leads to miscompiles. */
5139 if (for_moveop
&& sched_verbose
>= 2)
5141 sel_print ("Best expression(s) (sequential form): ");
5142 dump_av_set (expr_seq
);
5150 /* Move nop to previous block. */
5151 static void ATTRIBUTE_UNUSED
5152 move_nop_to_previous_block (insn_t nop
, basic_block prev_bb
)
5154 insn_t prev_insn
, next_insn
;
5156 gcc_assert (sel_bb_head_p (nop
)
5157 && prev_bb
== BLOCK_FOR_INSN (nop
)->prev_bb
);
5158 rtx_note
*note
= bb_note (BLOCK_FOR_INSN (nop
));
5159 prev_insn
= sel_bb_end (prev_bb
);
5160 next_insn
= NEXT_INSN (nop
);
5161 gcc_assert (prev_insn
!= NULL_RTX
5162 && PREV_INSN (note
) == prev_insn
);
5164 SET_NEXT_INSN (prev_insn
) = nop
;
5165 SET_PREV_INSN (nop
) = prev_insn
;
5167 SET_PREV_INSN (note
) = nop
;
5168 SET_NEXT_INSN (note
) = next_insn
;
5170 SET_NEXT_INSN (nop
) = note
;
5171 SET_PREV_INSN (next_insn
) = note
;
5173 BB_END (prev_bb
) = nop
;
5174 BLOCK_FOR_INSN (nop
) = prev_bb
;
5177 /* Prepare a place to insert the chosen expression on BND. */
5179 prepare_place_to_insert (bnd_t bnd
)
5181 insn_t place_to_insert
;
5183 /* Init place_to_insert before calling move_op, as the later
5184 can possibly remove BND_TO (bnd). */
5185 if (/* If this is not the first insn scheduled. */
5188 /* Add it after last scheduled. */
5189 place_to_insert
= ILIST_INSN (BND_PTR (bnd
));
5190 if (DEBUG_INSN_P (place_to_insert
))
5192 ilist_t l
= BND_PTR (bnd
);
5193 while ((l
= ILIST_NEXT (l
)) &&
5194 DEBUG_INSN_P (ILIST_INSN (l
)))
5197 place_to_insert
= NULL
;
5201 place_to_insert
= NULL
;
5203 if (!place_to_insert
)
5205 /* Add it before BND_TO. The difference is in the
5206 basic block, where INSN will be added. */
5207 place_to_insert
= get_nop_from_pool (BND_TO (bnd
));
5208 gcc_assert (BLOCK_FOR_INSN (place_to_insert
)
5209 == BLOCK_FOR_INSN (BND_TO (bnd
)));
5212 return place_to_insert
;
5215 /* Find original instructions for EXPR_SEQ and move it to BND boundary.
5216 Return the expression to emit in C_EXPR. */
5218 move_exprs_to_boundary (bnd_t bnd
, expr_t expr_vliw
,
5219 av_set_t expr_seq
, expr_t c_expr
)
5221 bool b
, should_move
;
5224 int n_bookkeeping_copies_before_moveop
;
5226 /* Make a move. This call will remove the original operation,
5227 insert all necessary bookkeeping instructions and update the
5228 data sets. After that all we have to do is add the operation
5229 at before BND_TO (BND). */
5230 n_bookkeeping_copies_before_moveop
= stat_bookkeeping_copies
;
5231 max_uid_before_move_op
= get_max_uid ();
5232 bitmap_clear (current_copies
);
5233 bitmap_clear (current_originators
);
5235 b
= move_op (BND_TO (bnd
), expr_seq
, expr_vliw
,
5236 get_dest_from_orig_ops (expr_seq
), c_expr
, &should_move
);
5238 /* We should be able to find the expression we've chosen for
5242 if (stat_bookkeeping_copies
> n_bookkeeping_copies_before_moveop
)
5243 stat_insns_needed_bookkeeping
++;
5245 EXECUTE_IF_SET_IN_BITMAP (current_copies
, 0, book_uid
, bi
)
5250 /* We allocate these bitmaps lazily. */
5251 if (! INSN_ORIGINATORS_BY_UID (book_uid
))
5252 INSN_ORIGINATORS_BY_UID (book_uid
) = BITMAP_ALLOC (NULL
);
5254 bitmap_copy (INSN_ORIGINATORS_BY_UID (book_uid
),
5255 current_originators
);
5257 /* Transitively add all originators' originators. */
5258 EXECUTE_IF_SET_IN_BITMAP (current_originators
, 0, uid
, bi
)
5259 if (INSN_ORIGINATORS_BY_UID (uid
))
5260 bitmap_ior_into (INSN_ORIGINATORS_BY_UID (book_uid
),
5261 INSN_ORIGINATORS_BY_UID (uid
));
5268 /* Debug a DFA state as an array of bytes. */
5270 debug_state (state_t state
)
5273 unsigned int i
, size
= dfa_state_size
;
5275 sel_print ("state (%u):", size
);
5276 for (i
= 0, p
= (unsigned char *) state
; i
< size
; i
++)
5277 sel_print (" %d", p
[i
]);
5281 /* Advance state on FENCE with INSN. Return true if INSN is
5282 an ASM, and we should advance state once more. */
5284 advance_state_on_fence (fence_t fence
, insn_t insn
)
5288 if (recog_memoized (insn
) >= 0)
5291 state_t temp_state
= alloca (dfa_state_size
);
5293 gcc_assert (!INSN_ASM_P (insn
));
5296 memcpy (temp_state
, FENCE_STATE (fence
), dfa_state_size
);
5297 res
= state_transition (FENCE_STATE (fence
), insn
);
5298 gcc_assert (res
< 0);
5300 if (memcmp (temp_state
, FENCE_STATE (fence
), dfa_state_size
))
5302 FENCE_ISSUED_INSNS (fence
)++;
5304 /* We should never issue more than issue_rate insns. */
5305 if (FENCE_ISSUED_INSNS (fence
) > issue_rate
)
5311 /* This could be an ASM insn which we'd like to schedule
5312 on the next cycle. */
5313 asm_p
= INSN_ASM_P (insn
);
5314 if (!FENCE_STARTS_CYCLE_P (fence
) && asm_p
)
5315 advance_one_cycle (fence
);
5318 if (sched_verbose
>= 2)
5319 debug_state (FENCE_STATE (fence
));
5320 if (!DEBUG_INSN_P (insn
))
5321 FENCE_STARTS_CYCLE_P (fence
) = 0;
5322 FENCE_ISSUE_MORE (fence
) = can_issue_more
;
5326 /* Update FENCE on which INSN was scheduled and this INSN, too. NEED_STALL
5327 is nonzero if we need to stall after issuing INSN. */
5329 update_fence_and_insn (fence_t fence
, insn_t insn
, int need_stall
)
5333 /* First, reflect that something is scheduled on this fence. */
5334 asm_p
= advance_state_on_fence (fence
, insn
);
5335 FENCE_LAST_SCHEDULED_INSN (fence
) = insn
;
5336 vec_safe_push (FENCE_EXECUTING_INSNS (fence
), insn
);
5337 if (SCHED_GROUP_P (insn
))
5339 FENCE_SCHED_NEXT (fence
) = INSN_SCHED_NEXT (insn
);
5340 SCHED_GROUP_P (insn
) = 0;
5343 FENCE_SCHED_NEXT (fence
) = NULL
;
5344 if (INSN_UID (insn
) < FENCE_READY_TICKS_SIZE (fence
))
5345 FENCE_READY_TICKS (fence
) [INSN_UID (insn
)] = 0;
5347 /* Set instruction scheduling info. This will be used in bundling,
5348 pipelining, tick computations etc. */
5349 ++INSN_SCHED_TIMES (insn
);
5350 EXPR_TARGET_AVAILABLE (INSN_EXPR (insn
)) = true;
5351 EXPR_ORIG_SCHED_CYCLE (INSN_EXPR (insn
)) = FENCE_CYCLE (fence
);
5352 INSN_AFTER_STALL_P (insn
) = FENCE_AFTER_STALL_P (fence
);
5353 INSN_SCHED_CYCLE (insn
) = FENCE_CYCLE (fence
);
5355 /* This does not account for adjust_cost hooks, just add the biggest
5356 constant the hook may add to the latency. TODO: make this
5357 a target dependent constant. */
5358 INSN_READY_CYCLE (insn
)
5359 = INSN_SCHED_CYCLE (insn
) + (INSN_CODE (insn
) < 0
5361 : maximal_insn_latency (insn
) + 1);
5363 /* Change these fields last, as they're used above. */
5364 FENCE_AFTER_STALL_P (fence
) = 0;
5365 if (asm_p
|| need_stall
)
5366 advance_one_cycle (fence
);
5368 /* Indicate that we've scheduled something on this fence. */
5369 FENCE_SCHEDULED_P (fence
) = true;
5370 scheduled_something_on_previous_fence
= true;
5372 /* Print debug information when insn's fields are updated. */
5373 if (sched_verbose
>= 2)
5375 sel_print ("Scheduling insn: ");
5376 dump_insn_1 (insn
, 1);
5381 /* Update boundary BND (and, if needed, FENCE) with INSN, remove the
5382 old boundary from BNDSP, add new boundaries to BNDS_TAIL_P and
5385 update_boundaries (fence_t fence
, bnd_t bnd
, insn_t insn
, blist_t
*bndsp
,
5386 blist_t
*bnds_tailp
)
5391 advance_deps_context (BND_DC (bnd
), insn
);
5392 FOR_EACH_SUCC_1 (succ
, si
, insn
,
5393 SUCCS_NORMAL
| SUCCS_SKIP_TO_LOOP_EXITS
)
5395 ilist_t ptr
= ilist_copy (BND_PTR (bnd
));
5397 ilist_add (&ptr
, insn
);
5399 if (DEBUG_INSN_P (insn
) && sel_bb_end_p (insn
)
5400 && is_ineligible_successor (succ
, ptr
))
5406 if (FENCE_INSN (fence
) == insn
&& !sel_bb_end_p (insn
))
5408 if (sched_verbose
>= 9)
5409 sel_print ("Updating fence insn from %i to %i\n",
5410 INSN_UID (insn
), INSN_UID (succ
));
5411 FENCE_INSN (fence
) = succ
;
5413 blist_add (bnds_tailp
, succ
, ptr
, BND_DC (bnd
));
5414 bnds_tailp
= &BLIST_NEXT (*bnds_tailp
);
5417 blist_remove (bndsp
);
5421 /* Schedule EXPR_VLIW on BND. Return the insn emitted. */
5423 schedule_expr_on_boundary (bnd_t bnd
, expr_t expr_vliw
, int seqno
)
5426 expr_t c_expr
= XALLOCA (expr_def
);
5427 insn_t place_to_insert
;
5431 expr_seq
= find_sequential_best_exprs (bnd
, expr_vliw
, true);
5433 /* In case of scheduling a jump skipping some other instructions,
5434 prepare CFG. After this, jump is at the boundary and can be
5435 scheduled as usual insn by MOVE_OP. */
5436 if (vinsn_cond_branch_p (EXPR_VINSN (expr_vliw
)))
5438 insn
= EXPR_INSN_RTX (expr_vliw
);
5440 /* Speculative jumps are not handled. */
5441 if (insn
!= BND_TO (bnd
)
5442 && !sel_insn_is_speculation_check (insn
))
5443 move_cond_jump (insn
, bnd
);
5446 /* Find a place for C_EXPR to schedule. */
5447 place_to_insert
= prepare_place_to_insert (bnd
);
5448 should_move
= move_exprs_to_boundary (bnd
, expr_vliw
, expr_seq
, c_expr
);
5449 clear_expr (c_expr
);
5451 /* Add the instruction. The corner case to care about is when
5452 the expr_seq set has more than one expr, and we chose the one that
5453 is not equal to expr_vliw. Then expr_vliw may be insn in stream, and
5454 we can't use it. Generate the new vinsn. */
5455 if (INSN_IN_STREAM_P (EXPR_INSN_RTX (expr_vliw
)))
5459 vinsn_new
= vinsn_copy (EXPR_VINSN (expr_vliw
), false);
5460 change_vinsn_in_expr (expr_vliw
, vinsn_new
);
5461 should_move
= false;
5464 insn
= sel_move_insn (expr_vliw
, seqno
, place_to_insert
);
5466 insn
= emit_insn_from_expr_after (expr_vliw
, NULL
, seqno
,
5469 /* Return the nops generated for preserving of data sets back
5471 if (INSN_NOP_P (place_to_insert
))
5472 return_nop_to_pool (place_to_insert
, !DEBUG_INSN_P (insn
));
5473 remove_temp_moveop_nops (!DEBUG_INSN_P (insn
));
5475 av_set_clear (&expr_seq
);
5477 /* Save the expression scheduled so to reset target availability if we'll
5478 meet it later on the same fence. */
5479 if (EXPR_WAS_RENAMED (expr_vliw
))
5480 vinsn_vec_add (&vec_target_unavailable_vinsns
, INSN_EXPR (insn
));
5482 /* Check that the recent movement didn't destroyed loop
5484 gcc_assert (!pipelining_p
5485 || current_loop_nest
== NULL
5486 || loop_latch_edge (current_loop_nest
));
5490 /* Stall for N cycles on FENCE. */
5492 stall_for_cycles (fence_t fence
, int n
)
5496 could_more
= n
> 1 || FENCE_ISSUED_INSNS (fence
) < issue_rate
;
5498 advance_one_cycle (fence
);
5500 FENCE_AFTER_STALL_P (fence
) = 1;
5503 /* Gather a parallel group of insns at FENCE and assign their seqno
5504 to SEQNO. All scheduled insns are gathered in SCHEDULED_INSNS_TAILPP
5505 list for later recalculation of seqnos. */
5507 fill_insns (fence_t fence
, int seqno
, ilist_t
**scheduled_insns_tailpp
)
5509 blist_t bnds
= NULL
, *bnds_tailp
;
5510 av_set_t av_vliw
= NULL
;
5511 insn_t insn
= FENCE_INSN (fence
);
5513 if (sched_verbose
>= 2)
5514 sel_print ("Starting fill_insns for insn %d, cycle %d\n",
5515 INSN_UID (insn
), FENCE_CYCLE (fence
));
5517 blist_add (&bnds
, insn
, NULL
, FENCE_DC (fence
));
5518 bnds_tailp
= &BLIST_NEXT (bnds
);
5519 set_target_context (FENCE_TC (fence
));
5520 can_issue_more
= FENCE_ISSUE_MORE (fence
);
5521 target_bb
= INSN_BB (insn
);
5523 /* Do while we can add any operation to the current group. */
5526 blist_t
*bnds_tailp1
, *bndsp
;
5528 int need_stall
= false;
5529 int was_stall
= 0, scheduled_insns
= 0;
5530 int max_insns
= pipelining_p
? issue_rate
: 2 * issue_rate
;
5531 int max_stall
= pipelining_p
? 1 : 3;
5532 bool last_insn_was_debug
= false;
5533 bool was_debug_bb_end_p
= false;
5535 compute_av_set_on_boundaries (fence
, bnds
, &av_vliw
);
5536 remove_insns_that_need_bookkeeping (fence
, &av_vliw
);
5537 remove_insns_for_debug (bnds
, &av_vliw
);
5539 /* Return early if we have nothing to schedule. */
5540 if (av_vliw
== NULL
)
5543 /* Choose the best expression and, if needed, destination register
5547 expr_vliw
= find_best_expr (&av_vliw
, bnds
, fence
, &need_stall
);
5548 if (! expr_vliw
&& need_stall
)
5550 /* All expressions required a stall. Do not recompute av sets
5551 as we'll get the same answer (modulo the insns between
5552 the fence and its boundary, which will not be available for
5554 If we are going to stall for too long, break to recompute av
5555 sets and bring more insns for pipelining. */
5557 if (need_stall
<= 3)
5558 stall_for_cycles (fence
, need_stall
);
5561 stall_for_cycles (fence
, 1);
5566 while (! expr_vliw
&& need_stall
);
5568 /* Now either we've selected expr_vliw or we have nothing to schedule. */
5571 av_set_clear (&av_vliw
);
5576 bnds_tailp1
= bnds_tailp
;
5579 /* This code will be executed only once until we'd have several
5580 boundaries per fence. */
5582 bnd_t bnd
= BLIST_BND (*bndsp
);
5584 if (!av_set_is_in_p (BND_AV1 (bnd
), EXPR_VINSN (expr_vliw
)))
5586 bndsp
= &BLIST_NEXT (*bndsp
);
5590 insn
= schedule_expr_on_boundary (bnd
, expr_vliw
, seqno
);
5591 last_insn_was_debug
= DEBUG_INSN_P (insn
);
5592 if (last_insn_was_debug
)
5593 was_debug_bb_end_p
= (insn
== BND_TO (bnd
) && sel_bb_end_p (insn
));
5594 update_fence_and_insn (fence
, insn
, need_stall
);
5595 bnds_tailp
= update_boundaries (fence
, bnd
, insn
, bndsp
, bnds_tailp
);
5597 /* Add insn to the list of scheduled on this cycle instructions. */
5598 ilist_add (*scheduled_insns_tailpp
, insn
);
5599 *scheduled_insns_tailpp
= &ILIST_NEXT (**scheduled_insns_tailpp
);
5601 while (*bndsp
!= *bnds_tailp1
);
5603 av_set_clear (&av_vliw
);
5604 if (!last_insn_was_debug
)
5607 /* We currently support information about candidate blocks only for
5608 one 'target_bb' block. Hence we can't schedule after jump insn,
5609 as this will bring two boundaries and, hence, necessity to handle
5610 information for two or more blocks concurrently. */
5611 if ((last_insn_was_debug
? was_debug_bb_end_p
: sel_bb_end_p (insn
))
5613 && (was_stall
>= max_stall
5614 || scheduled_insns
>= max_insns
)))
5619 gcc_assert (!FENCE_BNDS (fence
));
5621 /* Update boundaries of the FENCE. */
5624 ilist_t ptr
= BND_PTR (BLIST_BND (bnds
));
5628 insn
= ILIST_INSN (ptr
);
5630 if (!ilist_is_in_p (FENCE_BNDS (fence
), insn
))
5631 ilist_add (&FENCE_BNDS (fence
), insn
);
5634 blist_remove (&bnds
);
5637 /* Update target context on the fence. */
5638 reset_target_context (FENCE_TC (fence
), false);
5641 /* All exprs in ORIG_OPS must have the same destination register or memory.
5642 Return that destination. */
5644 get_dest_from_orig_ops (av_set_t orig_ops
)
5646 rtx dest
= NULL_RTX
;
5647 av_set_iterator av_it
;
5649 bool first_p
= true;
5651 FOR_EACH_EXPR (expr
, av_it
, orig_ops
)
5653 rtx x
= EXPR_LHS (expr
);
5661 gcc_assert (dest
== x
5662 || (dest
!= NULL_RTX
&& x
!= NULL_RTX
5663 && rtx_equal_p (dest
, x
)));
5669 /* Update data sets for the bookkeeping block and record those expressions
5670 which become no longer available after inserting this bookkeeping. */
5672 update_and_record_unavailable_insns (basic_block book_block
)
5675 av_set_t old_av_set
= NULL
;
5677 rtx_insn
*bb_end
= sel_bb_end (book_block
);
5679 /* First, get correct liveness in the bookkeeping block. The problem is
5680 the range between the bookeeping insn and the end of block. */
5681 update_liveness_on_insn (bb_end
);
5682 if (control_flow_insn_p (bb_end
))
5683 update_liveness_on_insn (PREV_INSN (bb_end
));
5685 /* If there's valid av_set on BOOK_BLOCK, then there might exist another
5686 fence above, where we may choose to schedule an insn which is
5687 actually blocked from moving up with the bookkeeping we create here. */
5688 if (AV_SET_VALID_P (sel_bb_head (book_block
)))
5690 old_av_set
= av_set_copy (BB_AV_SET (book_block
));
5691 update_data_sets (sel_bb_head (book_block
));
5693 /* Traverse all the expressions in the old av_set and check whether
5694 CUR_EXPR is in new AV_SET. */
5695 FOR_EACH_EXPR (cur_expr
, i
, old_av_set
)
5697 expr_t new_expr
= av_set_lookup (BB_AV_SET (book_block
),
5698 EXPR_VINSN (cur_expr
));
5701 /* In this case, we can just turn off the E_T_A bit, but we can't
5702 represent this information with the current vector. */
5703 || EXPR_TARGET_AVAILABLE (new_expr
)
5704 != EXPR_TARGET_AVAILABLE (cur_expr
))
5705 /* Unfortunately, the below code could be also fired up on
5706 separable insns, e.g. when moving insns through the new
5707 speculation check as in PR 53701. */
5708 vinsn_vec_add (&vec_bookkeeping_blocked_vinsns
, cur_expr
);
5711 av_set_clear (&old_av_set
);
5715 /* The main effect of this function is that sparams->c_expr is merged
5716 with (or copied to) lparams->c_expr_merged. If there's only one successor,
5717 we avoid merging anything by copying sparams->c_expr to lparams->c_expr_merged.
5718 lparams->c_expr_merged is copied back to sparams->c_expr after all
5719 successors has been traversed. lparams->c_expr_local is an expr allocated
5720 on stack in the caller function, and is used if there is more than one
5723 SUCC is one of the SUCCS_NORMAL successors of INSN,
5724 MOVEOP_DRV_CALL_RES is the result of call code_motion_path_driver on succ,
5725 LPARAMS and STATIC_PARAMS contain the parameters described above. */
5727 move_op_merge_succs (insn_t insn ATTRIBUTE_UNUSED
,
5728 insn_t succ ATTRIBUTE_UNUSED
,
5729 int moveop_drv_call_res
,
5730 cmpd_local_params_p lparams
, void *static_params
)
5732 moveop_static_params_p sparams
= (moveop_static_params_p
) static_params
;
5734 /* Nothing to do, if original expr wasn't found below. */
5735 if (moveop_drv_call_res
!= 1)
5738 /* If this is a first successor. */
5739 if (!lparams
->c_expr_merged
)
5741 lparams
->c_expr_merged
= sparams
->c_expr
;
5742 sparams
->c_expr
= lparams
->c_expr_local
;
5746 /* We must merge all found expressions to get reasonable
5747 EXPR_SPEC_DONE_DS for the resulting insn. If we don't
5748 do so then we can first find the expr with epsilon
5749 speculation success probability and only then with the
5750 good probability. As a result the insn will get epsilon
5751 probability and will never be scheduled because of
5752 weakness_cutoff in find_best_expr.
5754 We call merge_expr_data here instead of merge_expr
5755 because due to speculation C_EXPR and X may have the
5756 same insns with different speculation types. And as of
5757 now such insns are considered non-equal.
5759 However, EXPR_SCHED_TIMES is different -- we must get
5760 SCHED_TIMES from a real insn, not a bookkeeping copy.
5761 We force this here. Instead, we may consider merging
5762 SCHED_TIMES to the maximum instead of minimum in the
5764 int old_times
= EXPR_SCHED_TIMES (lparams
->c_expr_merged
);
5766 merge_expr_data (lparams
->c_expr_merged
, sparams
->c_expr
, NULL
);
5767 if (EXPR_SCHED_TIMES (sparams
->c_expr
) == 0)
5768 EXPR_SCHED_TIMES (lparams
->c_expr_merged
) = old_times
;
5770 clear_expr (sparams
->c_expr
);
5774 /* Add used regs for the successor SUCC into SPARAMS->USED_REGS.
5776 SUCC is one of the SUCCS_NORMAL successors of INSN,
5777 MOVEOP_DRV_CALL_RES is the result of call code_motion_path_driver on succ or 0,
5778 if SUCC is one of SUCCS_BACK or SUCCS_OUT.
5779 STATIC_PARAMS contain USED_REGS set. */
5781 fur_merge_succs (insn_t insn ATTRIBUTE_UNUSED
, insn_t succ
,
5782 int moveop_drv_call_res
,
5783 cmpd_local_params_p lparams ATTRIBUTE_UNUSED
,
5784 void *static_params
)
5787 fur_static_params_p sparams
= (fur_static_params_p
) static_params
;
5789 /* Here we compute live regsets only for branches that do not lie
5790 on the code motion paths. These branches correspond to value
5791 MOVEOP_DRV_CALL_RES==0 and include SUCCS_BACK and SUCCS_OUT, though
5792 for such branches code_motion_path_driver is not called. */
5793 if (moveop_drv_call_res
!= 0)
5796 /* Mark all registers that do not meet the following condition:
5797 (3) not live on the other path of any conditional branch
5798 that is passed by the operation, in case original
5799 operations are not present on both paths of the
5800 conditional branch. */
5801 succ_live
= compute_live (succ
);
5802 IOR_REG_SET (sparams
->used_regs
, succ_live
);
5805 /* This function is called after the last successor. Copies LP->C_EXPR_MERGED
5808 move_op_after_merge_succs (cmpd_local_params_p lp
, void *sparams
)
5810 moveop_static_params_p sp
= (moveop_static_params_p
) sparams
;
5812 sp
->c_expr
= lp
->c_expr_merged
;
5815 /* Track bookkeeping copies created, insns scheduled, and blocks for
5816 rescheduling when INSN is found by move_op. */
5818 track_scheduled_insns_and_blocks (rtx_insn
*insn
)
5820 /* Even if this insn can be a copy that will be removed during current move_op,
5821 we still need to count it as an originator. */
5822 bitmap_set_bit (current_originators
, INSN_UID (insn
));
5824 if (!bitmap_clear_bit (current_copies
, INSN_UID (insn
)))
5826 /* Note that original block needs to be rescheduled, as we pulled an
5827 instruction out of it. */
5828 if (INSN_SCHED_TIMES (insn
) > 0)
5829 bitmap_set_bit (blocks_to_reschedule
, BLOCK_FOR_INSN (insn
)->index
);
5830 else if (INSN_UID (insn
) < first_emitted_uid
&& !DEBUG_INSN_P (insn
))
5831 num_insns_scheduled
++;
5834 /* For instructions we must immediately remove insn from the
5835 stream, so subsequent update_data_sets () won't include this
5837 For expr we must make insn look like "INSN_REG (insn) := c_expr". */
5838 if (INSN_UID (insn
) > max_uid_before_move_op
)
5839 stat_bookkeeping_copies
--;
5842 /* Emit a register-register copy for INSN if needed. Return true if
5843 emitted one. PARAMS is the move_op static parameters. */
5845 maybe_emit_renaming_copy (rtx_insn
*insn
,
5846 moveop_static_params_p params
)
5848 bool insn_emitted
= false;
5851 /* Bail out early when expression cannot be renamed at all. */
5852 if (!EXPR_SEPARABLE_P (params
->c_expr
))
5855 cur_reg
= expr_dest_reg (params
->c_expr
);
5856 gcc_assert (cur_reg
&& params
->dest
&& REG_P (params
->dest
));
5858 /* If original operation has expr and the register chosen for
5859 that expr is not original operation's dest reg, substitute
5860 operation's right hand side with the register chosen. */
5861 if (REGNO (params
->dest
) != REGNO (cur_reg
))
5863 insn_t reg_move_insn
, reg_move_insn_rtx
;
5865 reg_move_insn_rtx
= create_insn_rtx_with_rhs (INSN_VINSN (insn
),
5867 reg_move_insn
= sel_gen_insn_from_rtx_after (reg_move_insn_rtx
,
5871 EXPR_SPEC_DONE_DS (INSN_EXPR (reg_move_insn
)) = 0;
5872 replace_dest_with_reg_in_expr (params
->c_expr
, params
->dest
);
5874 insn_emitted
= true;
5875 params
->was_renamed
= true;
5878 return insn_emitted
;
5881 /* Emit a speculative check for INSN speculated as EXPR if needed.
5882 Return true if we've emitted one. PARAMS is the move_op static
5885 maybe_emit_speculative_check (rtx_insn
*insn
, expr_t expr
,
5886 moveop_static_params_p params
)
5888 bool insn_emitted
= false;
5892 check_ds
= get_spec_check_type_for_insn (insn
, expr
);
5895 /* A speculation check should be inserted. */
5896 x
= create_speculation_check (params
->c_expr
, check_ds
, insn
);
5897 insn_emitted
= true;
5901 EXPR_SPEC_DONE_DS (INSN_EXPR (insn
)) = 0;
5905 gcc_assert (EXPR_SPEC_DONE_DS (INSN_EXPR (x
)) == 0
5906 && EXPR_SPEC_TO_CHECK_DS (INSN_EXPR (x
)) == 0);
5907 return insn_emitted
;
5910 /* Handle transformations that leave an insn in place of original
5911 insn such as renaming/speculation. Return true if one of such
5912 transformations actually happened, and we have emitted this insn. */
5914 handle_emitting_transformations (rtx_insn
*insn
, expr_t expr
,
5915 moveop_static_params_p params
)
5917 bool insn_emitted
= false;
5919 insn_emitted
= maybe_emit_renaming_copy (insn
, params
);
5920 insn_emitted
|= maybe_emit_speculative_check (insn
, expr
, params
);
5922 return insn_emitted
;
5925 /* If INSN is the only insn in the basic block (not counting JUMP,
5926 which may be a jump to next insn, and DEBUG_INSNs), we want to
5927 leave a NOP there till the return to fill_insns. */
5930 need_nop_to_preserve_insn_bb (rtx_insn
*insn
)
5932 insn_t bb_head
, bb_end
, bb_next
, in_next
;
5933 basic_block bb
= BLOCK_FOR_INSN (insn
);
5935 bb_head
= sel_bb_head (bb
);
5936 bb_end
= sel_bb_end (bb
);
5938 if (bb_head
== bb_end
)
5941 while (bb_head
!= bb_end
&& DEBUG_INSN_P (bb_head
))
5942 bb_head
= NEXT_INSN (bb_head
);
5944 if (bb_head
== bb_end
)
5947 while (bb_head
!= bb_end
&& DEBUG_INSN_P (bb_end
))
5948 bb_end
= PREV_INSN (bb_end
);
5950 if (bb_head
== bb_end
)
5953 bb_next
= NEXT_INSN (bb_head
);
5954 while (bb_next
!= bb_end
&& DEBUG_INSN_P (bb_next
))
5955 bb_next
= NEXT_INSN (bb_next
);
5957 if (bb_next
== bb_end
&& JUMP_P (bb_end
))
5960 in_next
= NEXT_INSN (insn
);
5961 while (DEBUG_INSN_P (in_next
))
5962 in_next
= NEXT_INSN (in_next
);
5964 if (IN_CURRENT_FENCE_P (in_next
))
5970 /* Remove INSN from stream. When ONLY_DISCONNECT is true, its data
5971 is not removed but reused when INSN is re-emitted. */
5973 remove_insn_from_stream (rtx_insn
*insn
, bool only_disconnect
)
5975 /* If there's only one insn in the BB, make sure that a nop is
5976 inserted into it, so the basic block won't disappear when we'll
5977 delete INSN below with sel_remove_insn. It should also survive
5978 till the return to fill_insns. */
5979 if (need_nop_to_preserve_insn_bb (insn
))
5981 insn_t nop
= get_nop_from_pool (insn
);
5982 gcc_assert (INSN_NOP_P (nop
));
5983 vec_temp_moveop_nops
.safe_push (nop
);
5986 sel_remove_insn (insn
, only_disconnect
, false);
5989 /* This function is called when original expr is found.
5990 INSN - current insn traversed, EXPR - the corresponding expr found.
5991 LPARAMS is the local parameters of code modion driver, STATIC_PARAMS
5992 is static parameters of move_op. */
5994 move_op_orig_expr_found (insn_t insn
, expr_t expr
,
5995 cmpd_local_params_p lparams ATTRIBUTE_UNUSED
,
5996 void *static_params
)
5998 bool only_disconnect
;
5999 moveop_static_params_p params
= (moveop_static_params_p
) static_params
;
6001 copy_expr_onside (params
->c_expr
, INSN_EXPR (insn
));
6002 track_scheduled_insns_and_blocks (insn
);
6003 handle_emitting_transformations (insn
, expr
, params
);
6004 only_disconnect
= params
->uid
== INSN_UID (insn
);
6006 /* Mark that we've disconnected an insn. */
6007 if (only_disconnect
)
6009 remove_insn_from_stream (insn
, only_disconnect
);
6012 /* The function is called when original expr is found.
6013 INSN - current insn traversed, EXPR - the corresponding expr found,
6014 crosses_call and original_insns in STATIC_PARAMS are updated. */
6016 fur_orig_expr_found (insn_t insn
, expr_t expr ATTRIBUTE_UNUSED
,
6017 cmpd_local_params_p lparams ATTRIBUTE_UNUSED
,
6018 void *static_params
)
6020 fur_static_params_p params
= (fur_static_params_p
) static_params
;
6024 params
->crosses_call
= true;
6026 def_list_add (params
->original_insns
, insn
, params
->crosses_call
);
6028 /* Mark the registers that do not meet the following condition:
6029 (2) not among the live registers of the point
6030 immediately following the first original operation on
6031 a given downward path, except for the original target
6032 register of the operation. */
6033 tmp
= get_clear_regset_from_pool ();
6034 compute_live_below_insn (insn
, tmp
);
6035 AND_COMPL_REG_SET (tmp
, INSN_REG_SETS (insn
));
6036 AND_COMPL_REG_SET (tmp
, INSN_REG_CLOBBERS (insn
));
6037 IOR_REG_SET (params
->used_regs
, tmp
);
6038 return_regset_to_pool (tmp
);
6040 /* (*1) We need to add to USED_REGS registers that are read by
6041 INSN's lhs. This may lead to choosing wrong src register.
6042 E.g. (scheduling const expr enabled):
6044 429: ax=0x0 <- Can't use AX for this expr (0x0)
6051 /* FIXME: see comment above and enable MEM_P
6052 in vinsn_separable_p. */
6053 gcc_assert (!VINSN_SEPARABLE_P (INSN_VINSN (insn
))
6054 || !MEM_P (INSN_LHS (insn
)));
6057 /* This function is called on the ascending pass, before returning from
6058 current basic block. */
6060 move_op_at_first_insn (insn_t insn
, cmpd_local_params_p lparams
,
6061 void *static_params
)
6063 moveop_static_params_p sparams
= (moveop_static_params_p
) static_params
;
6064 basic_block book_block
= NULL
;
6066 /* When we have removed the boundary insn for scheduling, which also
6067 happened to be the end insn in its bb, we don't need to update sets. */
6068 if (!lparams
->removed_last_insn
6070 && sel_bb_head_p (insn
))
6072 /* We should generate bookkeeping code only if we are not at the
6073 top level of the move_op. */
6074 if (sel_num_cfg_preds_gt_1 (insn
))
6075 book_block
= generate_bookkeeping_insn (sparams
->c_expr
,
6076 lparams
->e1
, lparams
->e2
);
6077 /* Update data sets for the current insn. */
6078 update_data_sets (insn
);
6081 /* If bookkeeping code was inserted, we need to update av sets of basic
6082 block that received bookkeeping. After generation of bookkeeping insn,
6083 bookkeeping block does not contain valid av set because we are not following
6084 the original algorithm in every detail with regards to e.g. renaming
6085 simple reg-reg copies. Consider example:
6087 bookkeeping block scheduling fence
6097 We try to schedule insn "r1 := r3" on the current
6098 scheduling fence. Also, note that av set of bookkeeping block
6099 contain both insns "r1 := r2" and "r1 := r3". When the insn has
6100 been scheduled, the CFG is as follows:
6103 bookkeeping block scheduling fence
6113 Here, insn "r1 := r3" was scheduled at the current scheduling point
6114 and bookkeeping code was generated at the bookeeping block. This
6115 way insn "r1 := r2" is no longer available as a whole instruction
6116 (but only as expr) ahead of insn "r1 := r3" in bookkeeping block.
6117 This situation is handled by calling update_data_sets.
6119 Since update_data_sets is called only on the bookkeeping block, and
6120 it also may have predecessors with av_sets, containing instructions that
6121 are no longer available, we save all such expressions that become
6122 unavailable during data sets update on the bookkeeping block in
6123 VEC_BOOKKEEPING_BLOCKED_VINSNS. Later we avoid selecting such
6124 expressions for scheduling. This allows us to avoid recomputation of
6125 av_sets outside the code motion path. */
6128 update_and_record_unavailable_insns (book_block
);
6130 /* If INSN was previously marked for deletion, it's time to do it. */
6131 if (lparams
->removed_last_insn
)
6132 insn
= PREV_INSN (insn
);
6134 /* Do not tidy control flow at the topmost moveop, as we can erroneously
6135 kill a block with a single nop in which the insn should be emitted. */
6137 tidy_control_flow (BLOCK_FOR_INSN (insn
), true);
6140 /* This function is called on the ascending pass, before returning from the
6141 current basic block. */
6143 fur_at_first_insn (insn_t insn
,
6144 cmpd_local_params_p lparams ATTRIBUTE_UNUSED
,
6145 void *static_params ATTRIBUTE_UNUSED
)
6147 gcc_assert (!sel_bb_head_p (insn
) || AV_SET_VALID_P (insn
)
6148 || AV_LEVEL (insn
) == -1);
6151 /* Called on the backward stage of recursion to call moveup_expr for insn
6152 and sparams->c_expr. */
6154 move_op_ascend (insn_t insn
, void *static_params
)
6156 enum MOVEUP_EXPR_CODE res
;
6157 moveop_static_params_p sparams
= (moveop_static_params_p
) static_params
;
6159 if (! INSN_NOP_P (insn
))
6161 res
= moveup_expr_cached (sparams
->c_expr
, insn
, false);
6162 gcc_assert (res
!= MOVEUP_EXPR_NULL
);
6165 /* Update liveness for this insn as it was invalidated. */
6166 update_liveness_on_insn (insn
);
6169 /* This function is called on enter to the basic block.
6170 Returns TRUE if this block already have been visited and
6171 code_motion_path_driver should return 1, FALSE otherwise. */
6173 fur_on_enter (insn_t insn ATTRIBUTE_UNUSED
, cmpd_local_params_p local_params
,
6174 void *static_params
, bool visited_p
)
6176 fur_static_params_p sparams
= (fur_static_params_p
) static_params
;
6180 /* If we have found something below this block, there should be at
6181 least one insn in ORIGINAL_INSNS. */
6182 gcc_assert (*sparams
->original_insns
);
6184 /* Adjust CROSSES_CALL, since we may have come to this block along
6186 DEF_LIST_DEF (*sparams
->original_insns
)->crosses_call
6187 |= sparams
->crosses_call
;
6190 local_params
->old_original_insns
= *sparams
->original_insns
;
6195 /* Same as above but for move_op. */
6197 move_op_on_enter (insn_t insn ATTRIBUTE_UNUSED
,
6198 cmpd_local_params_p local_params ATTRIBUTE_UNUSED
,
6199 void *static_params ATTRIBUTE_UNUSED
, bool visited_p
)
6206 /* This function is called while descending current basic block if current
6207 insn is not the original EXPR we're searching for.
6209 Return value: FALSE, if code_motion_path_driver should perform a local
6210 cleanup and return 0 itself;
6211 TRUE, if code_motion_path_driver should continue. */
6213 move_op_orig_expr_not_found (insn_t insn
, av_set_t orig_ops ATTRIBUTE_UNUSED
,
6214 void *static_params
)
6216 moveop_static_params_p sparams
= (moveop_static_params_p
) static_params
;
6218 sparams
->failed_insn
= insn
;
6220 /* If we're scheduling separate expr, in order to generate correct code
6221 we need to stop the search at bookkeeping code generated with the
6222 same destination register or memory. */
6223 if (lhs_of_insn_equals_to_dest_p (insn
, sparams
->dest
))
6228 /* This function is called while descending current basic block if current
6229 insn is not the original EXPR we're searching for.
6231 Return value: TRUE (code_motion_path_driver should continue). */
6233 fur_orig_expr_not_found (insn_t insn
, av_set_t orig_ops
, void *static_params
)
6237 av_set_iterator avi
;
6238 fur_static_params_p sparams
= (fur_static_params_p
) static_params
;
6241 sparams
->crosses_call
= true;
6242 else if (DEBUG_INSN_P (insn
))
6245 /* If current insn we are looking at cannot be executed together
6246 with original insn, then we can skip it safely.
6248 Example: ORIG_OPS = { (p6) r14 = sign_extend (r15); }
6249 INSN = (!p6) r14 = r14 + 1;
6251 Here we can schedule ORIG_OP with lhs = r14, though only
6252 looking at the set of used and set registers of INSN we must
6253 forbid it. So, add set/used in INSN registers to the
6254 untouchable set only if there is an insn in ORIG_OPS that can
6257 FOR_EACH_EXPR (r
, avi
, orig_ops
)
6258 if (!sched_insns_conditions_mutex_p (insn
, EXPR_INSN_RTX (r
)))
6264 /* Mark all registers that do not meet the following condition:
6265 (1) Not set or read on any path from xi to an instance of the
6266 original operation. */
6269 IOR_REG_SET (sparams
->used_regs
, INSN_REG_SETS (insn
));
6270 IOR_REG_SET (sparams
->used_regs
, INSN_REG_USES (insn
));
6271 IOR_REG_SET (sparams
->used_regs
, INSN_REG_CLOBBERS (insn
));
6277 /* Hooks and data to perform move_op operations with code_motion_path_driver. */
6278 struct code_motion_path_driver_info_def move_op_hooks
= {
6280 move_op_orig_expr_found
,
6281 move_op_orig_expr_not_found
,
6282 move_op_merge_succs
,
6283 move_op_after_merge_succs
,
6285 move_op_at_first_insn
,
6290 /* Hooks and data to perform find_used_regs operations
6291 with code_motion_path_driver. */
6292 struct code_motion_path_driver_info_def fur_hooks
= {
6294 fur_orig_expr_found
,
6295 fur_orig_expr_not_found
,
6297 NULL
, /* fur_after_merge_succs */
6298 NULL
, /* fur_ascend */
6304 /* Traverse all successors of INSN. For each successor that is SUCCS_NORMAL
6305 code_motion_path_driver is called recursively. Original operation
6306 was found at least on one path that is starting with one of INSN's
6307 successors (this fact is asserted). ORIG_OPS is expressions we're looking
6308 for, PATH is the path we've traversed, STATIC_PARAMS is the parameters
6309 of either move_op or find_used_regs depending on the caller.
6311 Return 0 if we haven't found expression, 1 if we found it, -1 if we don't
6312 know for sure at this point. */
6314 code_motion_process_successors (insn_t insn
, av_set_t orig_ops
,
6315 ilist_t path
, void *static_params
)
6318 succ_iterator succ_i
;
6324 struct cmpd_local_params lparams
;
6327 lparams
.c_expr_local
= &_x
;
6328 lparams
.c_expr_merged
= NULL
;
6330 /* We need to process only NORMAL succs for move_op, and collect live
6331 registers from ALL branches (including those leading out of the
6332 region) for find_used_regs.
6334 In move_op, there can be a case when insn's bb number has changed
6335 due to created bookkeeping. This happens very rare, as we need to
6336 move expression from the beginning to the end of the same block.
6337 Rescan successors in this case. */
6340 bb
= BLOCK_FOR_INSN (insn
);
6341 old_index
= bb
->index
;
6342 old_succs
= EDGE_COUNT (bb
->succs
);
6344 FOR_EACH_SUCC_1 (succ
, succ_i
, insn
, code_motion_path_driver_info
->succ_flags
)
6348 lparams
.e1
= succ_i
.e1
;
6349 lparams
.e2
= succ_i
.e2
;
6351 /* Go deep into recursion only for NORMAL edges (non-backedges within the
6353 if (succ_i
.current_flags
== SUCCS_NORMAL
)
6354 b
= code_motion_path_driver (succ
, orig_ops
, path
, &lparams
,
6359 /* Merge c_expres found or unify live register sets from different
6361 code_motion_path_driver_info
->merge_succs (insn
, succ
, b
, &lparams
,
6365 else if (b
== -1 && res
!= 1)
6368 /* We have simplified the control flow below this point. In this case,
6369 the iterator becomes invalid. We need to try again.
6370 If we have removed the insn itself, it could be only an
6371 unconditional jump. Thus, do not rescan but break immediately --
6372 we have already visited the only successor block. */
6373 if (!BLOCK_FOR_INSN (insn
))
6375 if (sched_verbose
>= 6)
6376 sel_print ("Not doing rescan: already visited the only successor"
6377 " of block %d\n", old_index
);
6380 if (BLOCK_FOR_INSN (insn
)->index
!= old_index
6381 || EDGE_COUNT (bb
->succs
) != old_succs
)
6383 if (sched_verbose
>= 6)
6384 sel_print ("Rescan: CFG was simplified below insn %d, block %d\n",
6385 INSN_UID (insn
), BLOCK_FOR_INSN (insn
)->index
);
6386 insn
= sel_bb_end (BLOCK_FOR_INSN (insn
));
6391 /* Here, RES==1 if original expr was found at least for one of the
6392 successors. After the loop, RES may happen to have zero value
6393 only if at some point the expr searched is present in av_set, but is
6394 not found below. In most cases, this situation is an error.
6395 The exception is when the original operation is blocked by
6396 bookkeeping generated for another fence or for another path in current
6398 gcc_checking_assert (res
== 1
6400 && av_set_could_be_blocked_by_bookkeeping_p (orig_ops
, static_params
))
6403 /* Merge data, clean up, etc. */
6404 if (res
!= -1 && code_motion_path_driver_info
->after_merge_succs
)
6405 code_motion_path_driver_info
->after_merge_succs (&lparams
, static_params
);
6411 /* Perform a cleanup when the driver is about to terminate. ORIG_OPS_P
6412 is the pointer to the av set with expressions we were looking for,
6413 PATH_P is the pointer to the traversed path. */
6415 code_motion_path_driver_cleanup (av_set_t
*orig_ops_p
, ilist_t
*path_p
)
6417 ilist_remove (path_p
);
6418 av_set_clear (orig_ops_p
);
6421 /* The driver function that implements move_op or find_used_regs
6422 functionality dependent whether code_motion_path_driver_INFO is set to
6423 &MOVE_OP_HOOKS or &FUR_HOOKS. This function implements the common parts
6424 of code (CFG traversal etc) that are shared among both functions. INSN
6425 is the insn we're starting the search from, ORIG_OPS are the expressions
6426 we're searching for, PATH is traversed path, LOCAL_PARAMS_IN are local
6427 parameters of the driver, and STATIC_PARAMS are static parameters of
6430 Returns whether original instructions were found. Note that top-level
6431 code_motion_path_driver always returns true. */
6433 code_motion_path_driver (insn_t insn
, av_set_t orig_ops
, ilist_t path
,
6434 cmpd_local_params_p local_params_in
,
6435 void *static_params
)
6438 basic_block bb
= BLOCK_FOR_INSN (insn
);
6439 insn_t first_insn
, original_insn
, bb_tail
, before_first
;
6440 bool removed_last_insn
= false;
6442 if (sched_verbose
>= 6)
6444 sel_print ("%s (", code_motion_path_driver_info
->routine_name
);
6447 dump_av_set (orig_ops
);
6451 gcc_assert (orig_ops
);
6453 /* If no original operations exist below this insn, return immediately. */
6454 if (is_ineligible_successor (insn
, path
))
6456 if (sched_verbose
>= 6)
6457 sel_print ("Insn %d is ineligible successor\n", INSN_UID (insn
));
6461 /* The block can have invalid av set, in which case it was created earlier
6462 during move_op. Return immediately. */
6463 if (sel_bb_head_p (insn
))
6465 if (! AV_SET_VALID_P (insn
))
6467 if (sched_verbose
>= 6)
6468 sel_print ("Returned from block %d as it had invalid av set\n",
6473 if (bitmap_bit_p (code_motion_visited_blocks
, bb
->index
))
6475 /* We have already found an original operation on this branch, do not
6476 go any further and just return TRUE here. If we don't stop here,
6477 function can have exponential behavior even on the small code
6478 with many different paths (e.g. with data speculation and
6479 recovery blocks). */
6480 if (sched_verbose
>= 6)
6481 sel_print ("Block %d already visited in this traversal\n", bb
->index
);
6482 if (code_motion_path_driver_info
->on_enter
)
6483 return code_motion_path_driver_info
->on_enter (insn
,
6490 if (code_motion_path_driver_info
->on_enter
)
6491 code_motion_path_driver_info
->on_enter (insn
, local_params_in
,
6492 static_params
, false);
6493 orig_ops
= av_set_copy (orig_ops
);
6495 /* Filter the orig_ops set. */
6496 if (AV_SET_VALID_P (insn
))
6497 av_set_code_motion_filter (&orig_ops
, AV_SET (insn
));
6499 /* If no more original ops, return immediately. */
6502 if (sched_verbose
>= 6)
6503 sel_print ("No intersection with av set of block %d\n", bb
->index
);
6507 /* For non-speculative insns we have to leave only one form of the
6508 original operation, because if we don't, we may end up with
6509 different C_EXPRes and, consequently, with bookkeepings for different
6510 expression forms along the same code motion path. That may lead to
6511 generation of incorrect code. So for each code motion we stick to
6512 the single form of the instruction, except for speculative insns
6513 which we need to keep in different forms with all speculation
6515 av_set_leave_one_nonspec (&orig_ops
);
6517 /* It is not possible that all ORIG_OPS are filtered out. */
6518 gcc_assert (orig_ops
);
6520 /* It is enough to place only heads and tails of visited basic blocks into
6522 ilist_add (&path
, insn
);
6523 first_insn
= original_insn
= insn
;
6524 bb_tail
= sel_bb_end (bb
);
6526 /* Descend the basic block in search of the original expr; this part
6527 corresponds to the part of the original move_op procedure executed
6528 before the recursive call. */
6531 /* Look at the insn and decide if it could be an ancestor of currently
6532 scheduling operation. If it is so, then the insn "dest = op" could
6533 either be replaced with "dest = reg", because REG now holds the result
6534 of OP, or just removed, if we've scheduled the insn as a whole.
6536 If this insn doesn't contain currently scheduling OP, then proceed
6537 with searching and look at its successors. Operations we're searching
6538 for could have changed when moving up through this insn via
6539 substituting. In this case, perform unsubstitution on them first.
6541 When traversing the DAG below this insn is finished, insert
6542 bookkeeping code, if the insn is a joint point, and remove
6545 expr
= av_set_lookup (orig_ops
, INSN_VINSN (insn
));
6548 insn_t last_insn
= PREV_INSN (insn
);
6550 /* We have found the original operation. */
6551 if (sched_verbose
>= 6)
6552 sel_print ("Found original operation at insn %d\n", INSN_UID (insn
));
6554 code_motion_path_driver_info
->orig_expr_found
6555 (insn
, expr
, local_params_in
, static_params
);
6557 /* Step back, so on the way back we'll start traversing from the
6558 previous insn (or we'll see that it's bb_note and skip that
6560 if (insn
== first_insn
)
6562 first_insn
= NEXT_INSN (last_insn
);
6563 removed_last_insn
= sel_bb_end_p (last_insn
);
6570 /* We haven't found the original expr, continue descending the basic
6572 if (code_motion_path_driver_info
->orig_expr_not_found
6573 (insn
, orig_ops
, static_params
))
6575 /* Av set ops could have been changed when moving through this
6576 insn. To find them below it, we have to un-substitute them. */
6577 undo_transformations (&orig_ops
, insn
);
6581 /* Clean up and return, if the hook tells us to do so. It may
6582 happen if we've encountered the previously created
6584 code_motion_path_driver_cleanup (&orig_ops
, &path
);
6588 gcc_assert (orig_ops
);
6591 /* Stop at insn if we got to the end of BB. */
6592 if (insn
== bb_tail
)
6595 insn
= NEXT_INSN (insn
);
6598 /* Here INSN either points to the insn before the original insn (may be
6599 bb_note, if original insn was a bb_head) or to the bb_end. */
6603 rtx_insn
*last_insn
= PREV_INSN (insn
);
6606 gcc_assert (insn
== sel_bb_end (bb
));
6608 /* Add bb tail to PATH (but it doesn't make any sense if it's a bb_head -
6609 it's already in PATH then). */
6610 if (insn
!= first_insn
)
6612 ilist_add (&path
, insn
);
6613 added_to_path
= true;
6616 added_to_path
= false;
6618 /* Process_successors should be able to find at least one
6619 successor for which code_motion_path_driver returns TRUE. */
6620 res
= code_motion_process_successors (insn
, orig_ops
,
6621 path
, static_params
);
6623 /* Jump in the end of basic block could have been removed or replaced
6624 during code_motion_process_successors, so recompute insn as the
6626 if (NEXT_INSN (last_insn
) != insn
)
6628 insn
= sel_bb_end (bb
);
6629 first_insn
= sel_bb_head (bb
);
6630 if (first_insn
!= original_insn
)
6631 first_insn
= original_insn
;
6634 /* Remove bb tail from path. */
6636 ilist_remove (&path
);
6640 /* This is the case when one of the original expr is no longer available
6641 due to bookkeeping created on this branch with the same register.
6642 In the original algorithm, which doesn't have update_data_sets call
6643 on a bookkeeping block, it would simply result in returning
6644 FALSE when we've encountered a previously generated bookkeeping
6645 insn in moveop_orig_expr_not_found. */
6646 code_motion_path_driver_cleanup (&orig_ops
, &path
);
6651 /* Don't need it any more. */
6652 av_set_clear (&orig_ops
);
6654 /* Backward pass: now, when we have C_EXPR computed, we'll drag it to
6655 the beginning of the basic block. */
6656 before_first
= PREV_INSN (first_insn
);
6657 while (insn
!= before_first
)
6659 if (code_motion_path_driver_info
->ascend
)
6660 code_motion_path_driver_info
->ascend (insn
, static_params
);
6662 insn
= PREV_INSN (insn
);
6665 /* Now we're at the bb head. */
6667 ilist_remove (&path
);
6668 local_params_in
->removed_last_insn
= removed_last_insn
;
6669 code_motion_path_driver_info
->at_first_insn (insn
, local_params_in
, static_params
);
6671 /* This should be the very last operation as at bb head we could change
6672 the numbering by creating bookkeeping blocks. */
6673 if (removed_last_insn
)
6674 insn
= PREV_INSN (insn
);
6676 /* If we have simplified the control flow and removed the first jump insn,
6677 there's no point in marking this block in the visited blocks bitmap. */
6678 if (BLOCK_FOR_INSN (insn
))
6679 bitmap_set_bit (code_motion_visited_blocks
, BLOCK_FOR_INSN (insn
)->index
);
6683 /* Move up the operations from ORIG_OPS set traversing the dag starting
6684 from INSN. PATH represents the edges traversed so far.
6685 DEST is the register chosen for scheduling the current expr. Insert
6686 bookkeeping code in the join points. EXPR_VLIW is the chosen expression,
6687 C_EXPR is how it looks like at the given cfg point.
6688 Set *SHOULD_MOVE to indicate whether we have only disconnected
6689 one of the insns found.
6691 Returns whether original instructions were found, which is asserted
6692 to be true in the caller. */
6694 move_op (insn_t insn
, av_set_t orig_ops
, expr_t expr_vliw
,
6695 rtx dest
, expr_t c_expr
, bool *should_move
)
6697 struct moveop_static_params sparams
;
6698 struct cmpd_local_params lparams
;
6701 /* Init params for code_motion_path_driver. */
6702 sparams
.dest
= dest
;
6703 sparams
.c_expr
= c_expr
;
6704 sparams
.uid
= INSN_UID (EXPR_INSN_RTX (expr_vliw
));
6705 sparams
.failed_insn
= NULL
;
6706 sparams
.was_renamed
= false;
6709 /* We haven't visited any blocks yet. */
6710 bitmap_clear (code_motion_visited_blocks
);
6712 /* Set appropriate hooks and data. */
6713 code_motion_path_driver_info
= &move_op_hooks
;
6714 res
= code_motion_path_driver (insn
, orig_ops
, NULL
, &lparams
, &sparams
);
6716 gcc_assert (res
!= -1);
6718 if (sparams
.was_renamed
)
6719 EXPR_WAS_RENAMED (expr_vliw
) = true;
6721 *should_move
= (sparams
.uid
== -1);
6727 /* Functions that work with regions. */
6729 /* Current number of seqno used in init_seqno and init_seqno_1. */
6730 static int cur_seqno
;
6732 /* A helper for init_seqno. Traverse the region starting from BB and
6733 compute seqnos for visited insns, marking visited bbs in VISITED_BBS.
6734 Clear visited blocks from BLOCKS_TO_RESCHEDULE. */
6736 init_seqno_1 (basic_block bb
, sbitmap visited_bbs
, bitmap blocks_to_reschedule
)
6738 int bbi
= BLOCK_TO_BB (bb
->index
);
6743 rtx_note
*note
= bb_note (bb
);
6744 bitmap_set_bit (visited_bbs
, bbi
);
6745 if (blocks_to_reschedule
)
6746 bitmap_clear_bit (blocks_to_reschedule
, bb
->index
);
6748 FOR_EACH_SUCC_1 (succ_insn
, si
, BB_END (bb
),
6749 SUCCS_NORMAL
| SUCCS_SKIP_TO_LOOP_EXITS
)
6751 basic_block succ
= BLOCK_FOR_INSN (succ_insn
);
6752 int succ_bbi
= BLOCK_TO_BB (succ
->index
);
6754 gcc_assert (in_current_region_p (succ
));
6756 if (!bitmap_bit_p (visited_bbs
, succ_bbi
))
6758 gcc_assert (succ_bbi
> bbi
);
6760 init_seqno_1 (succ
, visited_bbs
, blocks_to_reschedule
);
6762 else if (blocks_to_reschedule
)
6763 bitmap_set_bit (forced_ebb_heads
, succ
->index
);
6766 for (insn
= BB_END (bb
); insn
!= note
; insn
= PREV_INSN (insn
))
6767 INSN_SEQNO (insn
) = cur_seqno
--;
6770 /* Initialize seqnos for the current region. BLOCKS_TO_RESCHEDULE contains
6771 blocks on which we're rescheduling when pipelining, FROM is the block where
6772 traversing region begins (it may not be the head of the region when
6773 pipelining, but the head of the loop instead).
6775 Returns the maximal seqno found. */
6777 init_seqno (bitmap blocks_to_reschedule
, basic_block from
)
6782 auto_sbitmap
visited_bbs (current_nr_blocks
);
6784 if (blocks_to_reschedule
)
6786 bitmap_ones (visited_bbs
);
6787 EXECUTE_IF_SET_IN_BITMAP (blocks_to_reschedule
, 0, bbi
, bi
)
6789 gcc_assert (BLOCK_TO_BB (bbi
) < current_nr_blocks
);
6790 bitmap_clear_bit (visited_bbs
, BLOCK_TO_BB (bbi
));
6795 bitmap_clear (visited_bbs
);
6796 from
= EBB_FIRST_BB (0);
6799 cur_seqno
= sched_max_luid
- 1;
6800 init_seqno_1 (from
, visited_bbs
, blocks_to_reschedule
);
6802 /* cur_seqno may be positive if the number of instructions is less than
6803 sched_max_luid - 1 (when rescheduling or if some instructions have been
6804 removed by the call to purge_empty_blocks in sel_sched_region_1). */
6805 gcc_assert (cur_seqno
>= 0);
6807 return sched_max_luid
- 1;
6810 /* Initialize scheduling parameters for current region. */
6812 sel_setup_region_sched_flags (void)
6814 enable_schedule_as_rhs_p
= 1;
6816 pipelining_p
= (bookkeeping_p
6817 && (flag_sel_sched_pipelining
!= 0)
6818 && current_loop_nest
!= NULL
6819 && loop_has_exit_edges (current_loop_nest
));
6820 max_insns_to_rename
= PARAM_VALUE (PARAM_SELSCHED_INSNS_TO_RENAME
);
6824 /* Return true if all basic blocks of current region are empty. */
6826 current_region_empty_p (void)
6829 for (i
= 0; i
< current_nr_blocks
; i
++)
6830 if (! sel_bb_empty_p (BASIC_BLOCK_FOR_FN (cfun
, BB_TO_BLOCK (i
))))
6836 /* Prepare and verify loop nest for pipelining. */
6838 setup_current_loop_nest (int rgn
, bb_vec_t
*bbs
)
6840 current_loop_nest
= get_loop_nest_for_rgn (rgn
);
6842 if (!current_loop_nest
)
6845 /* If this loop has any saved loop preheaders from nested loops,
6846 add these basic blocks to the current region. */
6847 sel_add_loop_preheaders (bbs
);
6849 /* Check that we're starting with a valid information. */
6850 gcc_assert (loop_latch_edge (current_loop_nest
));
6851 gcc_assert (LOOP_MARKED_FOR_PIPELINING_P (current_loop_nest
));
6854 /* Compute instruction priorities for current region. */
6856 sel_compute_priorities (int rgn
)
6858 sched_rgn_compute_dependencies (rgn
);
6860 /* Compute insn priorities in haifa style. Then free haifa style
6861 dependencies that we've calculated for this. */
6862 compute_priorities ();
6864 if (sched_verbose
>= 5)
6865 debug_rgn_dependencies (0);
6870 /* Init scheduling data for RGN. Returns true when this region should not
6873 sel_region_init (int rgn
)
6878 rgn_setup_region (rgn
);
6880 /* Even if sched_is_disabled_for_current_region_p() is true, we still
6881 do region initialization here so the region can be bundled correctly,
6882 but we'll skip the scheduling in sel_sched_region (). */
6883 if (current_region_empty_p ())
6886 bbs
.create (current_nr_blocks
);
6888 for (i
= 0; i
< current_nr_blocks
; i
++)
6889 bbs
.quick_push (BASIC_BLOCK_FOR_FN (cfun
, BB_TO_BLOCK (i
)));
6893 if (flag_sel_sched_pipelining
)
6894 setup_current_loop_nest (rgn
, &bbs
);
6896 sel_setup_region_sched_flags ();
6898 /* Initialize luids and dependence analysis which both sel-sched and haifa
6900 sched_init_luids (bbs
);
6901 sched_deps_init (false);
6903 /* Initialize haifa data. */
6904 rgn_setup_sched_infos ();
6905 sel_set_sched_flags ();
6906 haifa_init_h_i_d (bbs
);
6908 sel_compute_priorities (rgn
);
6909 init_deps_global ();
6911 /* Main initialization. */
6912 sel_setup_sched_infos ();
6913 sel_init_global_and_expr (bbs
);
6917 blocks_to_reschedule
= BITMAP_ALLOC (NULL
);
6919 /* Init correct liveness sets on each instruction of a single-block loop.
6920 This is the only situation when we can't update liveness when calling
6921 compute_live for the first insn of the loop. */
6922 if (current_loop_nest
)
6925 (sel_is_loop_preheader_p (BASIC_BLOCK_FOR_FN (cfun
, BB_TO_BLOCK (0)))
6929 if (current_nr_blocks
== header
+ 1)
6930 update_liveness_on_insn
6931 (sel_bb_head (BASIC_BLOCK_FOR_FN (cfun
, BB_TO_BLOCK (header
))));
6934 /* Set hooks so that no newly generated insn will go out unnoticed. */
6935 sel_register_cfg_hooks ();
6937 /* !!! We call target.sched.init () for the whole region, but we invoke
6938 targetm.sched.finish () for every ebb. */
6939 if (targetm
.sched
.init
)
6940 /* None of the arguments are actually used in any target. */
6941 targetm
.sched
.init (sched_dump
, sched_verbose
, -1);
6943 first_emitted_uid
= get_max_uid () + 1;
6944 preheader_removed
= false;
6946 /* Reset register allocation ticks array. */
6947 memset (reg_rename_tick
, 0, sizeof reg_rename_tick
);
6948 reg_rename_this_tick
= 0;
6950 forced_ebb_heads
= BITMAP_ALLOC (NULL
);
6953 current_copies
= BITMAP_ALLOC (NULL
);
6954 current_originators
= BITMAP_ALLOC (NULL
);
6955 code_motion_visited_blocks
= BITMAP_ALLOC (NULL
);
6960 /* Simplify insns after the scheduling. */
6962 simplify_changed_insns (void)
6966 for (i
= 0; i
< current_nr_blocks
; i
++)
6968 basic_block bb
= BASIC_BLOCK_FOR_FN (cfun
, BB_TO_BLOCK (i
));
6971 FOR_BB_INSNS (bb
, insn
)
6974 expr_t expr
= INSN_EXPR (insn
);
6976 if (EXPR_WAS_SUBSTITUTED (expr
))
6977 validate_simplify_insn (insn
);
6982 /* Find boundaries of the EBB starting from basic block BB, marking blocks of
6983 this EBB in SCHEDULED_BLOCKS and appropriately filling in HEAD, TAIL,
6984 PREV_HEAD, and NEXT_TAIL fields of CURRENT_SCHED_INFO structure. */
6986 find_ebb_boundaries (basic_block bb
, bitmap scheduled_blocks
)
6988 rtx_insn
*head
, *tail
;
6989 basic_block bb1
= bb
;
6990 if (sched_verbose
>= 2)
6991 sel_print ("Finishing schedule in bbs: ");
6995 bitmap_set_bit (scheduled_blocks
, BLOCK_TO_BB (bb1
->index
));
6997 if (sched_verbose
>= 2)
6998 sel_print ("%d; ", bb1
->index
);
7000 while (!bb_ends_ebb_p (bb1
) && (bb1
= bb_next_bb (bb1
)));
7002 if (sched_verbose
>= 2)
7005 get_ebb_head_tail (bb
, bb1
, &head
, &tail
);
7007 current_sched_info
->head
= head
;
7008 current_sched_info
->tail
= tail
;
7009 current_sched_info
->prev_head
= PREV_INSN (head
);
7010 current_sched_info
->next_tail
= NEXT_INSN (tail
);
7013 /* Regenerate INSN_SCHED_CYCLEs for insns of current EBB. */
7015 reset_sched_cycles_in_current_ebb (void)
7018 int haifa_last_clock
= -1;
7019 int haifa_clock
= 0;
7020 int issued_insns
= 0;
7023 if (targetm
.sched
.init
)
7025 /* None of the arguments are actually used in any target.
7026 NB: We should have md_reset () hook for cases like this. */
7027 targetm
.sched
.init (sched_dump
, sched_verbose
, -1);
7030 state_reset (curr_state
);
7031 advance_state (curr_state
);
7033 for (insn
= current_sched_info
->head
;
7034 insn
!= current_sched_info
->next_tail
;
7035 insn
= NEXT_INSN (insn
))
7037 int cost
, haifa_cost
;
7039 bool asm_p
, real_insn
, after_stall
, all_issued
;
7046 real_insn
= recog_memoized (insn
) >= 0;
7047 clock
= INSN_SCHED_CYCLE (insn
);
7049 cost
= clock
- last_clock
;
7051 /* Initialize HAIFA_COST. */
7054 asm_p
= INSN_ASM_P (insn
);
7057 /* This is asm insn which *had* to be scheduled first
7061 /* This is a use/clobber insn. It should not change
7066 haifa_cost
= estimate_insn_cost (insn
, curr_state
);
7068 /* Stall for whatever cycles we've stalled before. */
7070 if (INSN_AFTER_STALL_P (insn
) && cost
> haifa_cost
)
7075 all_issued
= issued_insns
== issue_rate
;
7076 if (haifa_cost
== 0 && all_issued
)
7082 while (haifa_cost
--)
7084 advance_state (curr_state
);
7088 if (sched_verbose
>= 2)
7090 sel_print ("advance_state (state_transition)\n");
7091 debug_state (curr_state
);
7094 /* The DFA may report that e.g. insn requires 2 cycles to be
7095 issued, but on the next cycle it says that insn is ready
7096 to go. Check this here. */
7100 && estimate_insn_cost (insn
, curr_state
) == 0)
7103 /* When the data dependency stall is longer than the DFA stall,
7104 and when we have issued exactly issue_rate insns and stalled,
7105 it could be that after this longer stall the insn will again
7106 become unavailable to the DFA restrictions. Looks strange
7107 but happens e.g. on x86-64. So recheck DFA on the last
7109 if ((after_stall
|| all_issued
)
7112 haifa_cost
= estimate_insn_cost (insn
, curr_state
);
7116 if (sched_verbose
>= 2)
7117 sel_print ("haifa clock: %d\n", haifa_clock
);
7120 gcc_assert (haifa_cost
== 0);
7122 if (sched_verbose
>= 2)
7123 sel_print ("Haifa cost for insn %d: %d\n", INSN_UID (insn
), haifa_cost
);
7125 if (targetm
.sched
.dfa_new_cycle
)
7126 while (targetm
.sched
.dfa_new_cycle (sched_dump
, sched_verbose
, insn
,
7127 haifa_last_clock
, haifa_clock
,
7130 advance_state (curr_state
);
7133 if (sched_verbose
>= 2)
7135 sel_print ("advance_state (dfa_new_cycle)\n");
7136 debug_state (curr_state
);
7137 sel_print ("haifa clock: %d\n", haifa_clock
+ 1);
7143 static state_t temp
= NULL
;
7146 temp
= xmalloc (dfa_state_size
);
7147 memcpy (temp
, curr_state
, dfa_state_size
);
7149 cost
= state_transition (curr_state
, insn
);
7150 if (memcmp (temp
, curr_state
, dfa_state_size
))
7153 if (sched_verbose
>= 2)
7155 sel_print ("scheduled insn %d, clock %d\n", INSN_UID (insn
),
7157 debug_state (curr_state
);
7159 gcc_assert (cost
< 0);
7162 if (targetm
.sched
.variable_issue
)
7163 targetm
.sched
.variable_issue (sched_dump
, sched_verbose
, insn
, 0);
7165 INSN_SCHED_CYCLE (insn
) = haifa_clock
;
7168 haifa_last_clock
= haifa_clock
;
7172 /* Put TImode markers on insns starting a new issue group. */
7176 int last_clock
= -1;
7179 for (insn
= current_sched_info
->head
; insn
!= current_sched_info
->next_tail
;
7180 insn
= NEXT_INSN (insn
))
7187 clock
= INSN_SCHED_CYCLE (insn
);
7188 cost
= (last_clock
== -1) ? 1 : clock
- last_clock
;
7190 gcc_assert (cost
>= 0);
7193 && GET_CODE (PATTERN (insn
)) != USE
7194 && GET_CODE (PATTERN (insn
)) != CLOBBER
)
7196 if (reload_completed
&& cost
> 0)
7197 PUT_MODE (insn
, TImode
);
7202 if (sched_verbose
>= 2)
7203 sel_print ("Cost for insn %d is %d\n", INSN_UID (insn
), cost
);
7207 /* Perform MD_FINISH on EBBs comprising current region. When
7208 RESET_SCHED_CYCLES_P is true, run a pass emulating the scheduler
7209 to produce correct sched cycles on insns. */
7211 sel_region_target_finish (bool reset_sched_cycles_p
)
7214 bitmap scheduled_blocks
= BITMAP_ALLOC (NULL
);
7216 for (i
= 0; i
< current_nr_blocks
; i
++)
7218 if (bitmap_bit_p (scheduled_blocks
, i
))
7221 /* While pipelining outer loops, skip bundling for loop
7222 preheaders. Those will be rescheduled in the outer loop. */
7223 if (sel_is_loop_preheader_p (EBB_FIRST_BB (i
)))
7226 find_ebb_boundaries (EBB_FIRST_BB (i
), scheduled_blocks
);
7228 if (no_real_insns_p (current_sched_info
->head
, current_sched_info
->tail
))
7231 if (reset_sched_cycles_p
)
7232 reset_sched_cycles_in_current_ebb ();
7234 if (targetm
.sched
.init
)
7235 targetm
.sched
.init (sched_dump
, sched_verbose
, -1);
7239 if (targetm
.sched
.finish
)
7241 targetm
.sched
.finish (sched_dump
, sched_verbose
);
7243 /* Extend luids so that insns generated by the target will
7245 sched_extend_luids ();
7249 BITMAP_FREE (scheduled_blocks
);
7252 /* Free the scheduling data for the current region. When RESET_SCHED_CYCLES_P
7253 is true, make an additional pass emulating scheduler to get correct insn
7254 cycles for md_finish calls. */
7256 sel_region_finish (bool reset_sched_cycles_p
)
7258 simplify_changed_insns ();
7259 sched_finish_ready_list ();
7262 /* Free the vectors. */
7263 vec_av_set
.release ();
7264 BITMAP_FREE (current_copies
);
7265 BITMAP_FREE (current_originators
);
7266 BITMAP_FREE (code_motion_visited_blocks
);
7267 vinsn_vec_free (vec_bookkeeping_blocked_vinsns
);
7268 vinsn_vec_free (vec_target_unavailable_vinsns
);
7270 /* If LV_SET of the region head should be updated, do it now because
7271 there will be no other chance. */
7276 FOR_EACH_SUCC_1 (insn
, si
, bb_note (EBB_FIRST_BB (0)),
7277 SUCCS_NORMAL
| SUCCS_SKIP_TO_LOOP_EXITS
)
7279 basic_block bb
= BLOCK_FOR_INSN (insn
);
7281 if (!BB_LV_SET_VALID_P (bb
))
7282 compute_live (insn
);
7286 /* Emulate the Haifa scheduler for bundling. */
7287 if (reload_completed
)
7288 sel_region_target_finish (reset_sched_cycles_p
);
7290 sel_finish_global_and_expr ();
7292 BITMAP_FREE (forced_ebb_heads
);
7296 finish_deps_global ();
7297 sched_finish_luids ();
7301 BITMAP_FREE (blocks_to_reschedule
);
7303 sel_unregister_cfg_hooks ();
7309 /* Functions that implement the scheduler driver. */
7311 /* Schedule a parallel instruction group on each of FENCES. MAX_SEQNO
7312 is the current maximum seqno. SCHEDULED_INSNS_TAILPP is the list
7313 of insns scheduled -- these would be postprocessed later. */
7315 schedule_on_fences (flist_t fences
, int max_seqno
,
7316 ilist_t
**scheduled_insns_tailpp
)
7318 flist_t old_fences
= fences
;
7320 if (sched_verbose
>= 1)
7322 sel_print ("\nScheduling on fences: ");
7323 dump_flist (fences
);
7327 scheduled_something_on_previous_fence
= false;
7328 for (; fences
; fences
= FLIST_NEXT (fences
))
7330 fence_t fence
= NULL
;
7333 bool first_p
= true;
7335 /* Choose the next fence group to schedule.
7336 The fact that insn can be scheduled only once
7337 on the cycle is guaranteed by two properties:
7338 1. seqnos of parallel groups decrease with each iteration.
7339 2. If is_ineligible_successor () sees the larger seqno, it
7340 checks if candidate insn is_in_current_fence_p (). */
7341 for (fences2
= old_fences
; fences2
; fences2
= FLIST_NEXT (fences2
))
7343 fence_t f
= FLIST_FENCE (fences2
);
7345 if (!FENCE_PROCESSED_P (f
))
7347 int i
= INSN_SEQNO (FENCE_INSN (f
));
7349 if (first_p
|| i
> seqno
)
7356 /* ??? Seqnos of different groups should be different. */
7357 gcc_assert (1 || i
!= seqno
);
7363 /* As FENCE is nonnull, SEQNO is initialized. */
7364 seqno
-= max_seqno
+ 1;
7365 fill_insns (fence
, seqno
, scheduled_insns_tailpp
);
7366 FENCE_PROCESSED_P (fence
) = true;
7369 /* All av_sets are invalidated by GLOBAL_LEVEL increase, thus we
7370 don't need to keep bookkeeping-invalidated and target-unavailable
7372 vinsn_vec_clear (&vec_bookkeeping_blocked_vinsns
);
7373 vinsn_vec_clear (&vec_target_unavailable_vinsns
);
7376 /* Calculate MIN_SEQNO and MAX_SEQNO. */
7378 find_min_max_seqno (flist_t fences
, int *min_seqno
, int *max_seqno
)
7380 *min_seqno
= *max_seqno
= INSN_SEQNO (FENCE_INSN (FLIST_FENCE (fences
)));
7382 /* The first element is already processed. */
7383 while ((fences
= FLIST_NEXT (fences
)))
7385 int seqno
= INSN_SEQNO (FENCE_INSN (FLIST_FENCE (fences
)));
7387 if (*min_seqno
> seqno
)
7389 else if (*max_seqno
< seqno
)
7394 /* Calculate new fences from FENCES. Write the current time to PTIME. */
7396 calculate_new_fences (flist_t fences
, int orig_max_seqno
, int *ptime
)
7398 flist_t old_fences
= fences
;
7399 struct flist_tail_def _new_fences
, *new_fences
= &_new_fences
;
7402 flist_tail_init (new_fences
);
7403 for (; fences
; fences
= FLIST_NEXT (fences
))
7405 fence_t fence
= FLIST_FENCE (fences
);
7408 if (!FENCE_BNDS (fence
))
7410 /* This fence doesn't have any successors. */
7411 if (!FENCE_SCHEDULED_P (fence
))
7413 /* Nothing was scheduled on this fence. */
7416 insn
= FENCE_INSN (fence
);
7417 seqno
= INSN_SEQNO (insn
);
7418 gcc_assert (seqno
> 0 && seqno
<= orig_max_seqno
);
7420 if (sched_verbose
>= 1)
7421 sel_print ("Fence %d[%d] has not changed\n",
7424 move_fence_to_fences (fences
, new_fences
);
7428 extract_new_fences_from (fences
, new_fences
, orig_max_seqno
);
7429 max_time
= MAX (max_time
, FENCE_CYCLE (fence
));
7432 flist_clear (&old_fences
);
7434 return FLIST_TAIL_HEAD (new_fences
);
7437 /* Update seqnos of insns given by PSCHEDULED_INSNS. MIN_SEQNO and MAX_SEQNO
7438 are the miminum and maximum seqnos of the group, HIGHEST_SEQNO_IN_USE is
7439 the highest seqno used in a region. Return the updated highest seqno. */
7441 update_seqnos_and_stage (int min_seqno
, int max_seqno
,
7442 int highest_seqno_in_use
,
7443 ilist_t
*pscheduled_insns
)
7449 /* Actually, new_hs is the seqno of the instruction, that was
7450 scheduled first (i.e. it is the first one in SCHEDULED_INSNS). */
7451 if (*pscheduled_insns
)
7453 new_hs
= (INSN_SEQNO (ILIST_INSN (*pscheduled_insns
))
7454 + highest_seqno_in_use
+ max_seqno
- min_seqno
+ 2);
7455 gcc_assert (new_hs
> highest_seqno_in_use
);
7458 new_hs
= highest_seqno_in_use
;
7460 FOR_EACH_INSN (insn
, ii
, *pscheduled_insns
)
7462 gcc_assert (INSN_SEQNO (insn
) < 0);
7463 INSN_SEQNO (insn
) += highest_seqno_in_use
+ max_seqno
- min_seqno
+ 2;
7464 gcc_assert (INSN_SEQNO (insn
) <= new_hs
);
7466 /* When not pipelining, purge unneeded insn info on the scheduled insns.
7467 For example, having reg_last array of INSN_DEPS_CONTEXT in memory may
7468 require > 1GB of memory e.g. on limit-fnargs.c. */
7470 free_data_for_scheduled_insn (insn
);
7473 ilist_clear (pscheduled_insns
);
7479 /* The main driver for scheduling a region. This function is responsible
7480 for correct propagation of fences (i.e. scheduling points) and creating
7481 a group of parallel insns at each of them. It also supports
7482 pipelining. ORIG_MAX_SEQNO is the maximal seqno before this pass
7485 sel_sched_region_2 (int orig_max_seqno
)
7487 int highest_seqno_in_use
= orig_max_seqno
;
7490 stat_bookkeeping_copies
= 0;
7491 stat_insns_needed_bookkeeping
= 0;
7492 stat_renamed_scheduled
= 0;
7493 stat_substitutions_total
= 0;
7494 num_insns_scheduled
= 0;
7498 int min_seqno
, max_seqno
;
7499 ilist_t scheduled_insns
= NULL
;
7500 ilist_t
*scheduled_insns_tailp
= &scheduled_insns
;
7502 find_min_max_seqno (fences
, &min_seqno
, &max_seqno
);
7503 schedule_on_fences (fences
, max_seqno
, &scheduled_insns_tailp
);
7504 fences
= calculate_new_fences (fences
, orig_max_seqno
, &max_time
);
7505 highest_seqno_in_use
= update_seqnos_and_stage (min_seqno
, max_seqno
,
7506 highest_seqno_in_use
,
7510 if (sched_verbose
>= 1)
7512 sel_print ("Total scheduling time: %d cycles\n", max_time
);
7513 sel_print ("Scheduled %d bookkeeping copies, %d insns needed "
7514 "bookkeeping, %d insns renamed, %d insns substituted\n",
7515 stat_bookkeeping_copies
,
7516 stat_insns_needed_bookkeeping
,
7517 stat_renamed_scheduled
,
7518 stat_substitutions_total
);
7522 /* Schedule a region. When pipelining, search for possibly never scheduled
7523 bookkeeping code and schedule it. Reschedule pipelined code without
7524 pipelining after. */
7526 sel_sched_region_1 (void)
7530 /* Remove empty blocks that might be in the region from the beginning. */
7531 purge_empty_blocks ();
7533 orig_max_seqno
= init_seqno (NULL
, NULL
);
7534 gcc_assert (orig_max_seqno
>= 1);
7536 /* When pipelining outer loops, create fences on the loop header,
7539 if (current_loop_nest
)
7540 init_fences (BB_END (EBB_FIRST_BB (0)));
7542 init_fences (bb_note (EBB_FIRST_BB (0)));
7545 sel_sched_region_2 (orig_max_seqno
);
7547 gcc_assert (fences
== NULL
);
7553 struct flist_tail_def _new_fences
;
7554 flist_tail_t new_fences
= &_new_fences
;
7557 pipelining_p
= false;
7558 max_ws
= MIN (max_ws
, issue_rate
* 3 / 2);
7559 bookkeeping_p
= false;
7560 enable_schedule_as_rhs_p
= false;
7562 /* Schedule newly created code, that has not been scheduled yet. */
7569 for (i
= 0; i
< current_nr_blocks
; i
++)
7571 basic_block bb
= EBB_FIRST_BB (i
);
7573 if (bitmap_bit_p (blocks_to_reschedule
, bb
->index
))
7575 if (! bb_ends_ebb_p (bb
))
7576 bitmap_set_bit (blocks_to_reschedule
, bb_next_bb (bb
)->index
);
7577 if (sel_bb_empty_p (bb
))
7579 bitmap_clear_bit (blocks_to_reschedule
, bb
->index
);
7582 clear_outdated_rtx_info (bb
);
7583 if (sel_insn_is_speculation_check (BB_END (bb
))
7584 && JUMP_P (BB_END (bb
)))
7585 bitmap_set_bit (blocks_to_reschedule
,
7586 BRANCH_EDGE (bb
)->dest
->index
);
7588 else if (! sel_bb_empty_p (bb
)
7589 && INSN_SCHED_TIMES (sel_bb_head (bb
)) <= 0)
7590 bitmap_set_bit (blocks_to_reschedule
, bb
->index
);
7593 for (i
= 0; i
< current_nr_blocks
; i
++)
7595 bb
= EBB_FIRST_BB (i
);
7597 /* While pipelining outer loops, skip bundling for loop
7598 preheaders. Those will be rescheduled in the outer
7600 if (sel_is_loop_preheader_p (bb
))
7602 clear_outdated_rtx_info (bb
);
7606 if (bitmap_bit_p (blocks_to_reschedule
, bb
->index
))
7608 flist_tail_init (new_fences
);
7610 orig_max_seqno
= init_seqno (blocks_to_reschedule
, bb
);
7612 /* Mark BB as head of the new ebb. */
7613 bitmap_set_bit (forced_ebb_heads
, bb
->index
);
7615 gcc_assert (fences
== NULL
);
7617 init_fences (bb_note (bb
));
7619 sel_sched_region_2 (orig_max_seqno
);
7629 /* Schedule the RGN region. */
7631 sel_sched_region (int rgn
)
7634 bool reset_sched_cycles_p
;
7636 if (sel_region_init (rgn
))
7639 if (sched_verbose
>= 1)
7640 sel_print ("Scheduling region %d\n", rgn
);
7642 schedule_p
= (!sched_is_disabled_for_current_region_p ()
7643 && dbg_cnt (sel_sched_region_cnt
));
7644 reset_sched_cycles_p
= pipelining_p
;
7646 sel_sched_region_1 ();
7649 /* Schedule always selecting the next insn to make the correct data
7650 for bundling or other later passes. */
7651 pipelining_p
= false;
7652 reset_sched_cycles_p
= false;
7653 force_next_insn
= 1;
7654 sel_sched_region_1 ();
7655 force_next_insn
= 0;
7657 sel_region_finish (reset_sched_cycles_p
);
7660 /* Perform global init for the scheduler. */
7662 sel_global_init (void)
7664 /* Remove empty blocks: their presence can break assumptions elsewhere,
7665 e.g. the logic to invoke update_liveness_on_insn in sel_region_init. */
7668 calculate_dominance_info (CDI_DOMINATORS
);
7669 alloc_sched_pools ();
7671 /* Setup the infos for sched_init. */
7672 sel_setup_sched_infos ();
7673 setup_sched_dump ();
7675 sched_rgn_init (false);
7679 /* Reset AFTER_RECOVERY if it has been set by the 1st scheduler pass. */
7681 can_issue_more
= issue_rate
;
7683 sched_extend_target ();
7684 sched_deps_init (true);
7685 setup_nop_and_exit_insns ();
7686 sel_extend_global_bb_info ();
7688 init_hard_regs_data ();
7691 /* Free the global data of the scheduler. */
7693 sel_global_finish (void)
7695 free_bb_note_pool ();
7697 sel_finish_global_bb_info ();
7699 free_regset_pool ();
7700 free_nop_and_exit_insns ();
7702 sched_rgn_finish ();
7703 sched_deps_finish ();
7707 sel_finish_pipelining ();
7709 free_sched_pools ();
7710 free_dominance_info (CDI_DOMINATORS
);
7713 /* Return true when we need to skip selective scheduling. Used for debugging. */
7715 maybe_skip_selective_scheduling (void)
7717 return ! dbg_cnt (sel_sched_cnt
);
7720 /* The entry point. */
7722 run_selective_scheduling (void)
7726 if (n_basic_blocks_for_fn (cfun
) == NUM_FIXED_BLOCKS
)
7731 for (rgn
= 0; rgn
< nr_regions
; rgn
++)
7732 sel_sched_region (rgn
);
7734 sel_global_finish ();