1 /* Instruction scheduling pass. Selective scheduler and pipeliner.
2 Copyright (C) 2006, 2007, 2008, 2009, 2010, 2011
3 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 3, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
23 #include "coretypes.h"
25 #include "rtl-error.h"
27 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "insn-attr.h"
39 #include "tree-pass.h"
40 #include "sched-int.h"
44 #include "langhooks.h"
45 #include "rtlhooks-def.h"
49 #ifdef INSN_SCHEDULING
50 #include "sel-sched-ir.h"
51 #include "sel-sched-dump.h"
52 #include "sel-sched.h"
55 /* Implementation of selective scheduling approach.
56 The below implementation follows the original approach with the following
59 o the scheduler works after register allocation (but can be also tuned
61 o some instructions are not copied or register renamed;
62 o conditional jumps are not moved with code duplication;
63 o several jumps in one parallel group are not supported;
64 o when pipelining outer loops, code motion through inner loops
66 o control and data speculation are supported;
67 o some improvements for better compile time/performance were made.
72 A vinsn, or virtual insn, is an insn with additional data characterizing
73 insn pattern, such as LHS, RHS, register sets used/set/clobbered, etc.
74 Vinsns also act as smart pointers to save memory by reusing them in
75 different expressions. A vinsn is described by vinsn_t type.
77 An expression is a vinsn with additional data characterizing its properties
78 at some point in the control flow graph. The data may be its usefulness,
79 priority, speculative status, whether it was renamed/subsituted, etc.
80 An expression is described by expr_t type.
82 Availability set (av_set) is a set of expressions at a given control flow
83 point. It is represented as av_set_t. The expressions in av sets are kept
84 sorted in the terms of expr_greater_p function. It allows to truncate
85 the set while leaving the best expressions.
87 A fence is a point through which code motion is prohibited. On each step,
88 we gather a parallel group of insns at a fence. It is possible to have
89 multiple fences. A fence is represented via fence_t.
91 A boundary is the border between the fence group and the rest of the code.
92 Currently, we never have more than one boundary per fence, as we finalize
93 the fence group when a jump is scheduled. A boundary is represented
99 The scheduler finds regions to schedule, schedules each one, and finalizes.
100 The regions are formed starting from innermost loops, so that when the inner
101 loop is pipelined, its prologue can be scheduled together with yet unprocessed
102 outer loop. The rest of acyclic regions are found using extend_rgns:
103 the blocks that are not yet allocated to any regions are traversed in top-down
104 order, and a block is added to a region to which all its predecessors belong;
105 otherwise, the block starts its own region.
107 The main scheduling loop (sel_sched_region_2) consists of just
108 scheduling on each fence and updating fences. For each fence,
109 we fill a parallel group of insns (fill_insns) until some insns can be added.
110 First, we compute available exprs (av-set) at the boundary of the current
111 group. Second, we choose the best expression from it. If the stall is
112 required to schedule any of the expressions, we advance the current cycle
113 appropriately. So, the final group does not exactly correspond to a VLIW
114 word. Third, we move the chosen expression to the boundary (move_op)
115 and update the intermediate av sets and liveness sets. We quit fill_insns
116 when either no insns left for scheduling or we have scheduled enough insns
117 so we feel like advancing a scheduling point.
119 Computing available expressions
120 ===============================
122 The computation (compute_av_set) is a bottom-up traversal. At each insn,
123 we're moving the union of its successors' sets through it via
124 moveup_expr_set. The dependent expressions are removed. Local
125 transformations (substitution, speculation) are applied to move more
126 exprs. Then the expr corresponding to the current insn is added.
127 The result is saved on each basic block header.
129 When traversing the CFG, we're moving down for no more than max_ws insns.
130 Also, we do not move down to ineligible successors (is_ineligible_successor),
131 which include moving along a back-edge, moving to already scheduled code,
132 and moving to another fence. The first two restrictions are lifted during
133 pipelining, which allows us to move insns along a back-edge. We always have
134 an acyclic region for scheduling because we forbid motion through fences.
136 Choosing the best expression
137 ============================
139 We sort the final availability set via sel_rank_for_schedule, then we remove
140 expressions which are not yet ready (tick_check_p) or which dest registers
141 cannot be used. For some of them, we choose another register via
142 find_best_reg. To do this, we run find_used_regs to calculate the set of
143 registers which cannot be used. The find_used_regs function performs
144 a traversal of code motion paths for an expr. We consider for renaming
145 only registers which are from the same regclass as the original one and
146 using which does not interfere with any live ranges. Finally, we convert
147 the resulting set to the ready list format and use max_issue and reorder*
148 hooks similarly to the Haifa scheduler.
150 Scheduling the best expression
151 ==============================
153 We run the move_op routine to perform the same type of code motion paths
154 traversal as in find_used_regs. (These are working via the same driver,
155 code_motion_path_driver.) When moving down the CFG, we look for original
156 instruction that gave birth to a chosen expression. We undo
157 the transformations performed on an expression via the history saved in it.
158 When found, we remove the instruction or leave a reg-reg copy/speculation
159 check if needed. On a way up, we insert bookkeeping copies at each join
160 point. If a copy is not needed, it will be removed later during this
161 traversal. We update the saved av sets and liveness sets on the way up, too.
163 Finalizing the schedule
164 =======================
166 When pipelining, we reschedule the blocks from which insns were pipelined
167 to get a tighter schedule. On Itanium, we also perform bundling via
168 the same routine from ia64.c.
170 Dependence analysis changes
171 ===========================
173 We augmented the sched-deps.c with hooks that get called when a particular
174 dependence is found in a particular part of an insn. Using these hooks, we
175 can do several actions such as: determine whether an insn can be moved through
176 another (has_dependence_p, moveup_expr); find out whether an insn can be
177 scheduled on the current cycle (tick_check_p); find out registers that
178 are set/used/clobbered by an insn and find out all the strange stuff that
179 restrict its movement, like SCHED_GROUP_P or CANT_MOVE (done in
180 init_global_and_expr_for_insn).
182 Initialization changes
183 ======================
185 There are parts of haifa-sched.c, sched-deps.c, and sched-rgn.c that are
186 reused in all of the schedulers. We have split up the initialization of data
187 of such parts into different functions prefixed with scheduler type and
188 postfixed with the type of data initialized: {,sel_,haifa_}sched_{init,finish},
189 sched_rgn_init/finish, sched_deps_init/finish, sched_init_{luids/bbs}, etc.
190 The same splitting is done with current_sched_info structure:
191 dependence-related parts are in sched_deps_info, common part is in
192 common_sched_info, and haifa/sel/etc part is in current_sched_info.
197 As we now have multiple-point scheduling, this would not work with backends
198 which save some of the scheduler state to use it in the target hooks.
199 For this purpose, we introduce a concept of target contexts, which
200 encapsulate such information. The backend should implement simple routines
201 of allocating/freeing/setting such a context. The scheduler calls these
202 as target hooks and handles the target context as an opaque pointer (similar
203 to the DFA state type, state_t).
208 As the correct data dependence graph is not supported during scheduling (which
209 is to be changed in mid-term), we cache as much of the dependence analysis
210 results as possible to avoid reanalyzing. This includes: bitmap caches on
211 each insn in stream of the region saying yes/no for a query with a pair of
212 UIDs; hashtables with the previously done transformations on each insn in
213 stream; a vector keeping a history of transformations on each expr.
215 Also, we try to minimize the dependence context used on each fence to check
216 whether the given expression is ready for scheduling by removing from it
217 insns that are definitely completed the execution. The results of
218 tick_check_p checks are also cached in a vector on each fence.
220 We keep a valid liveness set on each insn in a region to avoid the high
221 cost of recomputation on large basic blocks.
223 Finally, we try to minimize the number of needed updates to the availability
224 sets. The updates happen in two cases: when fill_insns terminates,
225 we advance all fences and increase the stage number to show that the region
226 has changed and the sets are to be recomputed; and when the next iteration
227 of a loop in fill_insns happens (but this one reuses the saved av sets
228 on bb headers.) Thus, we try to break the fill_insns loop only when
229 "significant" number of insns from the current scheduling window was
230 scheduled. This should be made a target param.
233 TODO: correctly support the data dependence graph at all stages and get rid
234 of all caches. This should speed up the scheduler.
235 TODO: implement moving cond jumps with bookkeeping copies on both targets.
236 TODO: tune the scheduler before RA so it does not create too much pseudos.
240 S.-M. Moon and K. Ebcioglu. Parallelizing nonnumerical code with
241 selective scheduling and software pipelining.
242 ACM TOPLAS, Vol 19, No. 6, pages 853--898, Nov. 1997.
244 Andrey Belevantsev, Maxim Kuvyrkov, Vladimir Makarov, Dmitry Melnik,
245 and Dmitry Zhurikhin. An interblock VLIW-targeted instruction scheduler
246 for GCC. In Proceedings of GCC Developers' Summit 2006.
248 Arutyun Avetisyan, Andrey Belevantsev, and Dmitry Melnik. GCC Instruction
249 Scheduler and Software Pipeliner on the Itanium Platform. EPIC-7 Workshop.
250 http://rogue.colorado.edu/EPIC7/.
254 /* True when pipelining is enabled. */
257 /* True if bookkeeping is enabled. */
260 /* Maximum number of insns that are eligible for renaming. */
261 int max_insns_to_rename
;
264 /* Definitions of local types and macros. */
266 /* Represents possible outcomes of moving an expression through an insn. */
267 enum MOVEUP_EXPR_CODE
269 /* The expression is not changed. */
272 /* Not changed, but requires a new destination register. */
275 /* Cannot be moved. */
278 /* Changed (substituted or speculated). */
282 /* The container to be passed into rtx search & replace functions. */
283 struct rtx_search_arg
285 /* What we are searching for. */
288 /* The occurence counter. */
292 typedef struct rtx_search_arg
*rtx_search_arg_p
;
294 /* This struct contains precomputed hard reg sets that are needed when
295 computing registers available for renaming. */
296 struct hard_regs_data
298 /* For every mode, this stores registers available for use with
300 HARD_REG_SET regs_for_mode
[NUM_MACHINE_MODES
];
302 /* True when regs_for_mode[mode] is initialized. */
303 bool regs_for_mode_ok
[NUM_MACHINE_MODES
];
305 /* For every register, it has regs that are ok to rename into it.
306 The register in question is always set. If not, this means
307 that the whole set is not computed yet. */
308 HARD_REG_SET regs_for_rename
[FIRST_PSEUDO_REGISTER
];
310 /* For every mode, this stores registers not available due to
312 HARD_REG_SET regs_for_call_clobbered
[NUM_MACHINE_MODES
];
314 /* All registers that are used or call used. */
315 HARD_REG_SET regs_ever_used
;
318 /* Stack registers. */
319 HARD_REG_SET stack_regs
;
323 /* Holds the results of computation of available for renaming and
324 unavailable hard registers. */
327 /* These are unavailable due to calls crossing, globalness, etc. */
328 HARD_REG_SET unavailable_hard_regs
;
330 /* These are *available* for renaming. */
331 HARD_REG_SET available_for_renaming
;
333 /* Whether this code motion path crosses a call. */
337 /* A global structure that contains the needed information about harg
339 static struct hard_regs_data sel_hrd
;
342 /* This structure holds local data used in code_motion_path_driver hooks on
343 the same or adjacent levels of recursion. Here we keep those parameters
344 that are not used in code_motion_path_driver routine itself, but only in
345 its hooks. Moreover, all parameters that can be modified in hooks are
346 in this structure, so all other parameters passed explicitly to hooks are
348 struct cmpd_local_params
350 /* Local params used in move_op_* functions. */
352 /* Edges for bookkeeping generation. */
355 /* C_EXPR merged from all successors and locally allocated temporary C_EXPR. */
356 expr_t c_expr_merged
, c_expr_local
;
358 /* Local params used in fur_* functions. */
359 /* Copy of the ORIGINAL_INSN list, stores the original insns already
360 found before entering the current level of code_motion_path_driver. */
361 def_list_t old_original_insns
;
363 /* Local params used in move_op_* functions. */
364 /* True when we have removed last insn in the block which was
365 also a boundary. Do not update anything or create bookkeeping copies. */
366 BOOL_BITFIELD removed_last_insn
: 1;
369 /* Stores the static parameters for move_op_* calls. */
370 struct moveop_static_params
372 /* Destination register. */
375 /* Current C_EXPR. */
378 /* An UID of expr_vliw which is to be moved up. If we find other exprs,
379 they are to be removed. */
382 #ifdef ENABLE_CHECKING
383 /* This is initialized to the insn on which the driver stopped its traversal. */
387 /* True if we scheduled an insn with different register. */
391 /* Stores the static parameters for fur_* calls. */
392 struct fur_static_params
394 /* Set of registers unavailable on the code motion path. */
397 /* Pointer to the list of original insns definitions. */
398 def_list_t
*original_insns
;
400 /* True if a code motion path contains a CALL insn. */
404 typedef struct fur_static_params
*fur_static_params_p
;
405 typedef struct cmpd_local_params
*cmpd_local_params_p
;
406 typedef struct moveop_static_params
*moveop_static_params_p
;
408 /* Set of hooks and parameters that determine behaviour specific to
409 move_op or find_used_regs functions. */
410 struct code_motion_path_driver_info_def
412 /* Called on enter to the basic block. */
413 int (*on_enter
) (insn_t
, cmpd_local_params_p
, void *, bool);
415 /* Called when original expr is found. */
416 void (*orig_expr_found
) (insn_t
, expr_t
, cmpd_local_params_p
, void *);
418 /* Called while descending current basic block if current insn is not
419 the original EXPR we're searching for. */
420 bool (*orig_expr_not_found
) (insn_t
, av_set_t
, void *);
422 /* Function to merge C_EXPRes from different successors. */
423 void (*merge_succs
) (insn_t
, insn_t
, int, cmpd_local_params_p
, void *);
425 /* Function to finalize merge from different successors and possibly
426 deallocate temporary data structures used for merging. */
427 void (*after_merge_succs
) (cmpd_local_params_p
, void *);
429 /* Called on the backward stage of recursion to do moveup_expr.
430 Used only with move_op_*. */
431 void (*ascend
) (insn_t
, void *);
433 /* Called on the ascending pass, before returning from the current basic
434 block or from the whole traversal. */
435 void (*at_first_insn
) (insn_t
, cmpd_local_params_p
, void *);
437 /* When processing successors in move_op we need only descend into
438 SUCCS_NORMAL successors, while in find_used_regs we need SUCCS_ALL. */
441 /* The routine name to print in dumps ("move_op" of "find_used_regs"). */
442 const char *routine_name
;
445 /* Global pointer to current hooks, either points to MOVE_OP_HOOKS or
447 struct code_motion_path_driver_info_def
*code_motion_path_driver_info
;
449 /* Set of hooks for performing move_op and find_used_regs routines with
450 code_motion_path_driver. */
451 extern struct code_motion_path_driver_info_def move_op_hooks
, fur_hooks
;
453 /* True if/when we want to emulate Haifa scheduler in the common code.
454 This is used in sched_rgn_local_init and in various places in
456 int sched_emulate_haifa_p
;
458 /* GLOBAL_LEVEL is used to discard information stored in basic block headers
459 av_sets. Av_set of bb header is valid if its (bb header's) level is equal
460 to GLOBAL_LEVEL. And invalid if lesser. This is primarily used to advance
461 scheduling window. */
464 /* Current fences. */
467 /* True when separable insns should be scheduled as RHSes. */
468 static bool enable_schedule_as_rhs_p
;
470 /* Used in verify_target_availability to assert that target reg is reported
471 unavailabile by both TARGET_UNAVAILABLE and find_used_regs only if
472 we haven't scheduled anything on the previous fence.
473 if scheduled_something_on_previous_fence is true, TARGET_UNAVAILABLE can
474 have more conservative value than the one returned by the
475 find_used_regs, thus we shouldn't assert that these values are equal. */
476 static bool scheduled_something_on_previous_fence
;
478 /* All newly emitted insns will have their uids greater than this value. */
479 static int first_emitted_uid
;
481 /* Set of basic blocks that are forced to start new ebbs. This is a subset
482 of all the ebb heads. */
483 static bitmap_head _forced_ebb_heads
;
484 bitmap_head
*forced_ebb_heads
= &_forced_ebb_heads
;
486 /* Blocks that need to be rescheduled after pipelining. */
487 bitmap blocks_to_reschedule
= NULL
;
489 /* True when the first lv set should be ignored when updating liveness. */
490 static bool ignore_first
= false;
492 /* Number of insns max_issue has initialized data structures for. */
493 static int max_issue_size
= 0;
495 /* Whether we can issue more instructions. */
496 static int can_issue_more
;
498 /* Maximum software lookahead window size, reduced when rescheduling after
502 /* Number of insns scheduled in current region. */
503 static int num_insns_scheduled
;
505 /* A vector of expressions is used to be able to sort them. */
507 DEF_VEC_ALLOC_P(expr_t
,heap
);
508 static VEC(expr_t
, heap
) *vec_av_set
= NULL
;
510 /* A vector of vinsns is used to hold temporary lists of vinsns. */
512 DEF_VEC_ALLOC_P(vinsn_t
,heap
);
513 typedef VEC(vinsn_t
, heap
) *vinsn_vec_t
;
515 /* This vector has the exprs which may still present in av_sets, but actually
516 can't be moved up due to bookkeeping created during code motion to another
517 fence. See comment near the call to update_and_record_unavailable_insns
518 for the detailed explanations. */
519 static vinsn_vec_t vec_bookkeeping_blocked_vinsns
= NULL
;
521 /* This vector has vinsns which are scheduled with renaming on the first fence
522 and then seen on the second. For expressions with such vinsns, target
523 availability information may be wrong. */
524 static vinsn_vec_t vec_target_unavailable_vinsns
= NULL
;
526 /* Vector to store temporary nops inserted in move_op to prevent removal
529 DEF_VEC_ALLOC_P(insn_t
,heap
);
530 static VEC(insn_t
, heap
) *vec_temp_moveop_nops
= NULL
;
532 /* These bitmaps record original instructions scheduled on the current
533 iteration and bookkeeping copies created by them. */
534 static bitmap current_originators
= NULL
;
535 static bitmap current_copies
= NULL
;
537 /* This bitmap marks the blocks visited by code_motion_path_driver so we don't
538 visit them afterwards. */
539 static bitmap code_motion_visited_blocks
= NULL
;
541 /* Variables to accumulate different statistics. */
543 /* The number of bookkeeping copies created. */
544 static int stat_bookkeeping_copies
;
546 /* The number of insns that required bookkeeiping for their scheduling. */
547 static int stat_insns_needed_bookkeeping
;
549 /* The number of insns that got renamed. */
550 static int stat_renamed_scheduled
;
552 /* The number of substitutions made during scheduling. */
553 static int stat_substitutions_total
;
556 /* Forward declarations of static functions. */
557 static bool rtx_ok_for_substitution_p (rtx
, rtx
);
558 static int sel_rank_for_schedule (const void *, const void *);
559 static av_set_t
find_sequential_best_exprs (bnd_t
, expr_t
, bool);
560 static basic_block
find_block_for_bookkeeping (edge e1
, edge e2
, bool lax
);
562 static rtx
get_dest_from_orig_ops (av_set_t
);
563 static basic_block
generate_bookkeeping_insn (expr_t
, edge
, edge
);
564 static bool find_used_regs (insn_t
, av_set_t
, regset
, struct reg_rename
*,
566 static bool move_op (insn_t
, av_set_t
, expr_t
, rtx
, expr_t
, bool*);
567 static int code_motion_path_driver (insn_t
, av_set_t
, ilist_t
,
568 cmpd_local_params_p
, void *);
569 static void sel_sched_region_1 (void);
570 static void sel_sched_region_2 (int);
571 static av_set_t
compute_av_set_inside_bb (insn_t
, ilist_t
, int, bool);
573 static void debug_state (state_t
);
576 /* Functions that work with fences. */
578 /* Advance one cycle on FENCE. */
580 advance_one_cycle (fence_t fence
)
586 advance_state (FENCE_STATE (fence
));
587 cycle
= ++FENCE_CYCLE (fence
);
588 FENCE_ISSUED_INSNS (fence
) = 0;
589 FENCE_STARTS_CYCLE_P (fence
) = 1;
590 can_issue_more
= issue_rate
;
591 FENCE_ISSUE_MORE (fence
) = can_issue_more
;
593 for (i
= 0; VEC_iterate (rtx
, FENCE_EXECUTING_INSNS (fence
), i
, insn
); )
595 if (INSN_READY_CYCLE (insn
) < cycle
)
597 remove_from_deps (FENCE_DC (fence
), insn
);
598 VEC_unordered_remove (rtx
, FENCE_EXECUTING_INSNS (fence
), i
);
603 if (sched_verbose
>= 2)
605 sel_print ("Finished a cycle. Current cycle = %d\n", FENCE_CYCLE (fence
));
606 debug_state (FENCE_STATE (fence
));
610 /* Returns true when SUCC in a fallthru bb of INSN, possibly
611 skipping empty basic blocks. */
613 in_fallthru_bb_p (rtx insn
, rtx succ
)
615 basic_block bb
= BLOCK_FOR_INSN (insn
);
618 if (bb
== BLOCK_FOR_INSN (succ
))
621 e
= find_fallthru_edge_from (bb
);
627 while (sel_bb_empty_p (bb
))
630 return bb
== BLOCK_FOR_INSN (succ
);
633 /* Construct successor fences from OLD_FENCEs and put them in NEW_FENCES.
634 When a successor will continue a ebb, transfer all parameters of a fence
635 to the new fence. ORIG_MAX_SEQNO is the maximal seqno before this round
636 of scheduling helping to distinguish between the old and the new code. */
638 extract_new_fences_from (flist_t old_fences
, flist_tail_t new_fences
,
641 bool was_here_p
= false;
642 insn_t insn
= NULL_RTX
;
646 fence_t fence
= FLIST_FENCE (old_fences
);
649 /* Get the only element of FENCE_BNDS (fence). */
650 FOR_EACH_INSN (insn
, ii
, FENCE_BNDS (fence
))
652 gcc_assert (!was_here_p
);
655 gcc_assert (was_here_p
&& insn
!= NULL_RTX
);
657 /* When in the "middle" of the block, just move this fence
659 bb
= BLOCK_FOR_INSN (insn
);
660 if (! sel_bb_end_p (insn
)
661 || (single_succ_p (bb
)
662 && single_pred_p (single_succ (bb
))))
666 succ
= (sel_bb_end_p (insn
)
667 ? sel_bb_head (single_succ (bb
))
670 if (INSN_SEQNO (succ
) > 0
671 && INSN_SEQNO (succ
) <= orig_max_seqno
672 && INSN_SCHED_TIMES (succ
) <= 0)
674 FENCE_INSN (fence
) = succ
;
675 move_fence_to_fences (old_fences
, new_fences
);
677 if (sched_verbose
>= 1)
678 sel_print ("Fence %d continues as %d[%d] (state continue)\n",
679 INSN_UID (insn
), INSN_UID (succ
), BLOCK_NUM (succ
));
684 /* Otherwise copy fence's structures to (possibly) multiple successors. */
685 FOR_EACH_SUCC_1 (succ
, si
, insn
, SUCCS_NORMAL
| SUCCS_SKIP_TO_LOOP_EXITS
)
687 int seqno
= INSN_SEQNO (succ
);
689 if (0 < seqno
&& seqno
<= orig_max_seqno
690 && (pipelining_p
|| INSN_SCHED_TIMES (succ
) <= 0))
692 bool b
= (in_same_ebb_p (insn
, succ
)
693 || in_fallthru_bb_p (insn
, succ
));
695 if (sched_verbose
>= 1)
696 sel_print ("Fence %d continues as %d[%d] (state %s)\n",
697 INSN_UID (insn
), INSN_UID (succ
),
698 BLOCK_NUM (succ
), b
? "continue" : "reset");
701 add_dirty_fence_to_fences (new_fences
, succ
, fence
);
704 /* Mark block of the SUCC as head of the new ebb. */
705 bitmap_set_bit (forced_ebb_heads
, BLOCK_NUM (succ
));
706 add_clean_fence_to_fences (new_fences
, succ
, fence
);
713 /* Functions to support substitution. */
715 /* Returns whether INSN with dependence status DS is eligible for
716 substitution, i.e. it's a copy operation x := y, and RHS that is
717 moved up through this insn should be substituted. */
719 can_substitute_through_p (insn_t insn
, ds_t ds
)
721 /* We can substitute only true dependencies. */
722 if ((ds
& DEP_OUTPUT
)
725 || ! INSN_LHS (insn
))
728 /* Now we just need to make sure the INSN_RHS consists of only one
730 if (REG_P (INSN_LHS (insn
))
731 && REG_P (INSN_RHS (insn
)))
736 /* Substitute all occurences of INSN's destination in EXPR' vinsn with INSN's
737 source (if INSN is eligible for substitution). Returns TRUE if
738 substitution was actually performed, FALSE otherwise. Substitution might
739 be not performed because it's either EXPR' vinsn doesn't contain INSN's
740 destination or the resulting insn is invalid for the target machine.
741 When UNDO is true, perform unsubstitution instead (the difference is in
742 the part of rtx on which validate_replace_rtx is called). */
744 substitute_reg_in_expr (expr_t expr
, insn_t insn
, bool undo
)
748 vinsn_t
*vi
= &EXPR_VINSN (expr
);
749 bool has_rhs
= VINSN_RHS (*vi
) != NULL
;
752 /* Do not try to replace in SET_DEST. Although we'll choose new
753 register for the RHS, we don't want to change RHS' original reg.
754 If the insn is not SET, we may still be able to substitute something
755 in it, and if we're here (don't have deps), it doesn't write INSN's
759 : &PATTERN (VINSN_INSN_RTX (*vi
)));
760 old
= undo
? INSN_RHS (insn
) : INSN_LHS (insn
);
762 /* Substitute if INSN has a form of x:=y and LHS(INSN) occurs in *VI. */
763 if (rtx_ok_for_substitution_p (old
, *where
))
768 /* We should copy these rtxes before substitution. */
769 new_rtx
= copy_rtx (undo
? INSN_LHS (insn
) : INSN_RHS (insn
));
770 new_insn
= create_copy_of_insn_rtx (VINSN_INSN_RTX (*vi
));
772 /* Where we'll replace.
773 WHERE_REPLACE should point inside NEW_INSN, so INSN_RHS couldn't be
774 used instead of SET_SRC. */
775 where_replace
= (has_rhs
776 ? &SET_SRC (PATTERN (new_insn
))
777 : &PATTERN (new_insn
));
780 = validate_replace_rtx_part_nosimplify (old
, new_rtx
, where_replace
,
783 /* ??? Actually, constrain_operands result depends upon choice of
784 destination register. E.g. if we allow single register to be an rhs,
785 and if we try to move dx=ax(as rhs) through ax=dx, we'll result
786 in invalid insn dx=dx, so we'll loose this rhs here.
787 Just can't come up with significant testcase for this, so just
788 leaving it for now. */
791 change_vinsn_in_expr (expr
,
792 create_vinsn_from_insn_rtx (new_insn
, false));
794 /* Do not allow clobbering the address register of speculative
796 if ((EXPR_SPEC_DONE_DS (expr
) & SPECULATIVE
)
797 && bitmap_bit_p (VINSN_REG_USES (EXPR_VINSN (expr
)),
798 expr_dest_regno (expr
)))
799 EXPR_TARGET_AVAILABLE (expr
) = false;
810 /* Helper function for count_occurences_equiv. */
812 count_occurrences_1 (rtx
*cur_rtx
, void *arg
)
814 rtx_search_arg_p p
= (rtx_search_arg_p
) arg
;
816 /* The last param FOR_GCSE is true, because otherwise it performs excessive
820 for the last insn it presumes r33 equivalent to r8, so it changes it to
821 r33. Actually, there's no change, but it spoils debugging. */
822 if (exp_equiv_p (*cur_rtx
, p
->x
, 0, true))
824 /* Bail out if we occupy more than one register. */
826 && HARD_REGISTER_P (*cur_rtx
)
827 && hard_regno_nregs
[REGNO(*cur_rtx
)][GET_MODE (*cur_rtx
)] > 1)
835 /* Do not traverse subexprs. */
839 if (GET_CODE (*cur_rtx
) == SUBREG
841 && (!REG_P (SUBREG_REG (*cur_rtx
))
842 || REGNO (SUBREG_REG (*cur_rtx
)) == REGNO (p
->x
)))
844 /* ??? Do not support substituting regs inside subregs. In that case,
845 simplify_subreg will be called by validate_replace_rtx, and
846 unsubstitution will fail later. */
851 /* Continue search. */
855 /* Return the number of places WHAT appears within WHERE.
856 Bail out when we found a reference occupying several hard registers. */
858 count_occurrences_equiv (rtx what
, rtx where
)
860 struct rtx_search_arg arg
;
865 for_each_rtx (&where
, &count_occurrences_1
, (void *) &arg
);
870 /* Returns TRUE if WHAT is found in WHERE rtx tree. */
872 rtx_ok_for_substitution_p (rtx what
, rtx where
)
874 return (count_occurrences_equiv (what
, where
) > 0);
878 /* Functions to support register renaming. */
880 /* Substitute VI's set source with REGNO. Returns newly created pattern
881 that has REGNO as its source. */
883 create_insn_rtx_with_rhs (vinsn_t vi
, rtx rhs_rtx
)
889 lhs_rtx
= copy_rtx (VINSN_LHS (vi
));
891 pattern
= gen_rtx_SET (VOIDmode
, lhs_rtx
, rhs_rtx
);
892 insn_rtx
= create_insn_rtx_from_pattern (pattern
, NULL_RTX
);
897 /* Returns whether INSN's src can be replaced with register number
898 NEW_SRC_REG. E.g. the following insn is valid for i386:
900 (insn:HI 2205 6585 2207 727 ../../gcc/libiberty/regex.c:3337
901 (set (mem/s:QI (plus:SI (plus:SI (reg/f:SI 7 sp)
902 (reg:SI 0 ax [orig:770 c1 ] [770]))
903 (const_int 288 [0x120])) [0 str S1 A8])
904 (const_int 0 [0x0])) 43 {*movqi_1} (nil)
907 But if we change (const_int 0 [0x0]) to (reg:QI 4 si), it will be invalid
908 because of operand constraints:
910 (define_insn "*movqi_1"
911 [(set (match_operand:QI 0 "nonimmediate_operand" "=q,q ,q ,r,r ,?r,m")
912 (match_operand:QI 1 "general_operand" " q,qn,qm,q,rn,qm,qn")
915 So do constrain_operands here, before choosing NEW_SRC_REG as best
919 replace_src_with_reg_ok_p (insn_t insn
, rtx new_src_reg
)
921 vinsn_t vi
= INSN_VINSN (insn
);
922 enum machine_mode mode
;
926 gcc_assert (VINSN_SEPARABLE_P (vi
));
928 get_dest_and_mode (insn
, &dst_loc
, &mode
);
929 gcc_assert (mode
== GET_MODE (new_src_reg
));
931 if (REG_P (dst_loc
) && REGNO (new_src_reg
) == REGNO (dst_loc
))
934 /* See whether SET_SRC can be replaced with this register. */
935 validate_change (insn
, &SET_SRC (PATTERN (insn
)), new_src_reg
, 1);
936 res
= verify_changes (0);
942 /* Returns whether INSN still be valid after replacing it's DEST with
945 replace_dest_with_reg_ok_p (insn_t insn
, rtx new_reg
)
947 vinsn_t vi
= INSN_VINSN (insn
);
950 /* We should deal here only with separable insns. */
951 gcc_assert (VINSN_SEPARABLE_P (vi
));
952 gcc_assert (GET_MODE (VINSN_LHS (vi
)) == GET_MODE (new_reg
));
954 /* See whether SET_DEST can be replaced with this register. */
955 validate_change (insn
, &SET_DEST (PATTERN (insn
)), new_reg
, 1);
956 res
= verify_changes (0);
962 /* Create a pattern with rhs of VI and lhs of LHS_RTX. */
964 create_insn_rtx_with_lhs (vinsn_t vi
, rtx lhs_rtx
)
970 rhs_rtx
= copy_rtx (VINSN_RHS (vi
));
972 pattern
= gen_rtx_SET (VOIDmode
, lhs_rtx
, rhs_rtx
);
973 insn_rtx
= create_insn_rtx_from_pattern (pattern
, NULL_RTX
);
978 /* Substitute lhs in the given expression EXPR for the register with number
979 NEW_REGNO. SET_DEST may be arbitrary rtx, not only register. */
981 replace_dest_with_reg_in_expr (expr_t expr
, rtx new_reg
)
986 insn_rtx
= create_insn_rtx_with_lhs (EXPR_VINSN (expr
), new_reg
);
987 vinsn
= create_vinsn_from_insn_rtx (insn_rtx
, false);
989 change_vinsn_in_expr (expr
, vinsn
);
990 EXPR_WAS_RENAMED (expr
) = 1;
991 EXPR_TARGET_AVAILABLE (expr
) = 1;
994 /* Returns whether VI writes either one of the USED_REGS registers or,
995 if a register is a hard one, one of the UNAVAILABLE_HARD_REGS registers. */
997 vinsn_writes_one_of_regs_p (vinsn_t vi
, regset used_regs
,
998 HARD_REG_SET unavailable_hard_regs
)
1001 reg_set_iterator rsi
;
1003 EXECUTE_IF_SET_IN_REG_SET (VINSN_REG_SETS (vi
), 0, regno
, rsi
)
1005 if (REGNO_REG_SET_P (used_regs
, regno
))
1007 if (HARD_REGISTER_NUM_P (regno
)
1008 && TEST_HARD_REG_BIT (unavailable_hard_regs
, regno
))
1012 EXECUTE_IF_SET_IN_REG_SET (VINSN_REG_CLOBBERS (vi
), 0, regno
, rsi
)
1014 if (REGNO_REG_SET_P (used_regs
, regno
))
1016 if (HARD_REGISTER_NUM_P (regno
)
1017 && TEST_HARD_REG_BIT (unavailable_hard_regs
, regno
))
1024 /* Returns register class of the output register in INSN.
1025 Returns NO_REGS for call insns because some targets have constraints on
1026 destination register of a call insn.
1028 Code adopted from regrename.c::build_def_use. */
1029 static enum reg_class
1030 get_reg_class (rtx insn
)
1034 extract_insn (insn
);
1035 if (! constrain_operands (1))
1036 fatal_insn_not_found (insn
);
1037 preprocess_constraints ();
1038 alt
= which_alternative
;
1039 n_ops
= recog_data
.n_operands
;
1041 for (i
= 0; i
< n_ops
; ++i
)
1043 int matches
= recog_op_alt
[i
][alt
].matches
;
1045 recog_op_alt
[i
][alt
].cl
= recog_op_alt
[matches
][alt
].cl
;
1048 if (asm_noperands (PATTERN (insn
)) > 0)
1050 for (i
= 0; i
< n_ops
; i
++)
1051 if (recog_data
.operand_type
[i
] == OP_OUT
)
1053 rtx
*loc
= recog_data
.operand_loc
[i
];
1055 enum reg_class cl
= recog_op_alt
[i
][alt
].cl
;
1058 && REGNO (op
) == ORIGINAL_REGNO (op
))
1064 else if (!CALL_P (insn
))
1066 for (i
= 0; i
< n_ops
+ recog_data
.n_dups
; i
++)
1068 int opn
= i
< n_ops
? i
: recog_data
.dup_num
[i
- n_ops
];
1069 enum reg_class cl
= recog_op_alt
[opn
][alt
].cl
;
1071 if (recog_data
.operand_type
[opn
] == OP_OUT
||
1072 recog_data
.operand_type
[opn
] == OP_INOUT
)
1078 (insn (set (reg:CCZ 17 flags) (compare:CCZ ...)))
1079 may result in returning NO_REGS, cause flags is written implicitly through
1080 CMP insn, which has no OP_OUT | OP_INOUT operands. */
1084 #ifdef HARD_REGNO_RENAME_OK
1085 /* Calculate HARD_REGNO_RENAME_OK data for REGNO. */
1087 init_hard_regno_rename (int regno
)
1091 SET_HARD_REG_BIT (sel_hrd
.regs_for_rename
[regno
], regno
);
1093 for (cur_reg
= 0; cur_reg
< FIRST_PSEUDO_REGISTER
; cur_reg
++)
1095 /* We are not interested in renaming in other regs. */
1096 if (!TEST_HARD_REG_BIT (sel_hrd
.regs_ever_used
, cur_reg
))
1099 if (HARD_REGNO_RENAME_OK (regno
, cur_reg
))
1100 SET_HARD_REG_BIT (sel_hrd
.regs_for_rename
[regno
], cur_reg
);
1105 /* A wrapper around HARD_REGNO_RENAME_OK that will look into the hard regs
1108 sel_hard_regno_rename_ok (int from ATTRIBUTE_UNUSED
, int to ATTRIBUTE_UNUSED
)
1110 #ifdef HARD_REGNO_RENAME_OK
1111 /* Check whether this is all calculated. */
1112 if (TEST_HARD_REG_BIT (sel_hrd
.regs_for_rename
[from
], from
))
1113 return TEST_HARD_REG_BIT (sel_hrd
.regs_for_rename
[from
], to
);
1115 init_hard_regno_rename (from
);
1117 return TEST_HARD_REG_BIT (sel_hrd
.regs_for_rename
[from
], to
);
1123 /* Calculate set of registers that are capable of holding MODE. */
1125 init_regs_for_mode (enum machine_mode mode
)
1129 CLEAR_HARD_REG_SET (sel_hrd
.regs_for_mode
[mode
]);
1130 CLEAR_HARD_REG_SET (sel_hrd
.regs_for_call_clobbered
[mode
]);
1132 for (cur_reg
= 0; cur_reg
< FIRST_PSEUDO_REGISTER
; cur_reg
++)
1134 int nregs
= hard_regno_nregs
[cur_reg
][mode
];
1137 for (i
= nregs
- 1; i
>= 0; --i
)
1138 if (fixed_regs
[cur_reg
+ i
]
1139 || global_regs
[cur_reg
+ i
]
1140 /* Can't use regs which aren't saved by
1142 || !TEST_HARD_REG_BIT (sel_hrd
.regs_ever_used
, cur_reg
+ i
)
1143 /* Can't use regs with non-null REG_BASE_VALUE, because adjusting
1144 it affects aliasing globally and invalidates all AV sets. */
1145 || get_reg_base_value (cur_reg
+ i
)
1146 #ifdef LEAF_REGISTERS
1147 /* We can't use a non-leaf register if we're in a
1149 || (current_function_is_leaf
1150 && !LEAF_REGISTERS
[cur_reg
+ i
])
1158 /* See whether it accepts all modes that occur in
1160 if (! HARD_REGNO_MODE_OK (cur_reg
, mode
))
1163 if (HARD_REGNO_CALL_PART_CLOBBERED (cur_reg
, mode
))
1164 SET_HARD_REG_BIT (sel_hrd
.regs_for_call_clobbered
[mode
],
1167 /* If the CUR_REG passed all the checks above,
1169 SET_HARD_REG_BIT (sel_hrd
.regs_for_mode
[mode
], cur_reg
);
1172 sel_hrd
.regs_for_mode_ok
[mode
] = true;
1175 /* Init all register sets gathered in HRD. */
1177 init_hard_regs_data (void)
1182 CLEAR_HARD_REG_SET (sel_hrd
.regs_ever_used
);
1183 for (cur_reg
= 0; cur_reg
< FIRST_PSEUDO_REGISTER
; cur_reg
++)
1184 if (df_regs_ever_live_p (cur_reg
) || call_used_regs
[cur_reg
])
1185 SET_HARD_REG_BIT (sel_hrd
.regs_ever_used
, cur_reg
);
1187 /* Initialize registers that are valid based on mode when this is
1189 for (cur_mode
= 0; cur_mode
< NUM_MACHINE_MODES
; cur_mode
++)
1190 sel_hrd
.regs_for_mode_ok
[cur_mode
] = false;
1192 /* Mark that all HARD_REGNO_RENAME_OK is not calculated. */
1193 for (cur_reg
= 0; cur_reg
< FIRST_PSEUDO_REGISTER
; cur_reg
++)
1194 CLEAR_HARD_REG_SET (sel_hrd
.regs_for_rename
[cur_reg
]);
1197 CLEAR_HARD_REG_SET (sel_hrd
.stack_regs
);
1199 for (cur_reg
= FIRST_STACK_REG
; cur_reg
<= LAST_STACK_REG
; cur_reg
++)
1200 SET_HARD_REG_BIT (sel_hrd
.stack_regs
, cur_reg
);
1204 /* Mark hardware regs in REG_RENAME_P that are not suitable
1205 for renaming rhs in INSN due to hardware restrictions (register class,
1206 modes compatibility etc). This doesn't affect original insn's dest reg,
1207 if it isn't in USED_REGS. DEF is a definition insn of rhs for which the
1208 destination register is sought. LHS (DEF->ORIG_INSN) may be REG or MEM.
1209 Registers that are in used_regs are always marked in
1210 unavailable_hard_regs as well. */
1213 mark_unavailable_hard_regs (def_t def
, struct reg_rename
*reg_rename_p
,
1214 regset used_regs ATTRIBUTE_UNUSED
)
1216 enum machine_mode mode
;
1217 enum reg_class cl
= NO_REGS
;
1219 unsigned cur_reg
, regno
;
1220 hard_reg_set_iterator hrsi
;
1222 gcc_assert (GET_CODE (PATTERN (def
->orig_insn
)) == SET
);
1223 gcc_assert (reg_rename_p
);
1225 orig_dest
= SET_DEST (PATTERN (def
->orig_insn
));
1227 /* We have decided not to rename 'mem = something;' insns, as 'something'
1228 is usually a register. */
1229 if (!REG_P (orig_dest
))
1232 regno
= REGNO (orig_dest
);
1234 /* If before reload, don't try to work with pseudos. */
1235 if (!reload_completed
&& !HARD_REGISTER_NUM_P (regno
))
1238 if (reload_completed
)
1239 cl
= get_reg_class (def
->orig_insn
);
1241 /* Stop if the original register is one of the fixed_regs, global_regs or
1242 frame pointer, or we could not discover its class. */
1243 if (fixed_regs
[regno
]
1244 || global_regs
[regno
]
1245 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
1246 || (frame_pointer_needed
&& regno
== HARD_FRAME_POINTER_REGNUM
)
1248 || (frame_pointer_needed
&& regno
== FRAME_POINTER_REGNUM
)
1250 || (reload_completed
&& cl
== NO_REGS
))
1252 SET_HARD_REG_SET (reg_rename_p
->unavailable_hard_regs
);
1254 /* Give a chance for original register, if it isn't in used_regs. */
1255 if (!def
->crosses_call
)
1256 CLEAR_HARD_REG_BIT (reg_rename_p
->unavailable_hard_regs
, regno
);
1261 /* If something allocated on stack in this function, mark frame pointer
1262 register unavailable, considering also modes.
1263 FIXME: it is enough to do this once per all original defs. */
1264 if (frame_pointer_needed
)
1266 add_to_hard_reg_set (®_rename_p
->unavailable_hard_regs
,
1267 Pmode
, FRAME_POINTER_REGNUM
);
1269 if (!HARD_FRAME_POINTER_IS_FRAME_POINTER
)
1270 add_to_hard_reg_set (®_rename_p
->unavailable_hard_regs
,
1271 Pmode
, HARD_FRAME_POINTER_IS_FRAME_POINTER
);
1275 /* For the stack registers the presence of FIRST_STACK_REG in USED_REGS
1276 is equivalent to as if all stack regs were in this set.
1277 I.e. no stack register can be renamed, and even if it's an original
1278 register here we make sure it won't be lifted over it's previous def
1279 (it's previous def will appear as if it's a FIRST_STACK_REG def.
1280 The HARD_REGNO_RENAME_OK covers other cases in condition below. */
1281 if (IN_RANGE (REGNO (orig_dest
), FIRST_STACK_REG
, LAST_STACK_REG
)
1282 && REGNO_REG_SET_P (used_regs
, FIRST_STACK_REG
))
1283 IOR_HARD_REG_SET (reg_rename_p
->unavailable_hard_regs
,
1284 sel_hrd
.stack_regs
);
1287 /* If there's a call on this path, make regs from call_used_reg_set
1289 if (def
->crosses_call
)
1290 IOR_HARD_REG_SET (reg_rename_p
->unavailable_hard_regs
,
1293 /* Stop here before reload: we need FRAME_REGS, STACK_REGS, and crosses_call,
1294 but not register classes. */
1295 if (!reload_completed
)
1298 /* Leave regs as 'available' only from the current
1300 COPY_HARD_REG_SET (reg_rename_p
->available_for_renaming
,
1301 reg_class_contents
[cl
]);
1303 mode
= GET_MODE (orig_dest
);
1305 /* Leave only registers available for this mode. */
1306 if (!sel_hrd
.regs_for_mode_ok
[mode
])
1307 init_regs_for_mode (mode
);
1308 AND_HARD_REG_SET (reg_rename_p
->available_for_renaming
,
1309 sel_hrd
.regs_for_mode
[mode
]);
1311 /* Exclude registers that are partially call clobbered. */
1312 if (def
->crosses_call
1313 && ! HARD_REGNO_CALL_PART_CLOBBERED (regno
, mode
))
1314 AND_COMPL_HARD_REG_SET (reg_rename_p
->available_for_renaming
,
1315 sel_hrd
.regs_for_call_clobbered
[mode
]);
1317 /* Leave only those that are ok to rename. */
1318 EXECUTE_IF_SET_IN_HARD_REG_SET (reg_rename_p
->available_for_renaming
,
1324 nregs
= hard_regno_nregs
[cur_reg
][mode
];
1325 gcc_assert (nregs
> 0);
1327 for (i
= nregs
- 1; i
>= 0; --i
)
1328 if (! sel_hard_regno_rename_ok (regno
+ i
, cur_reg
+ i
))
1332 CLEAR_HARD_REG_BIT (reg_rename_p
->available_for_renaming
,
1336 AND_COMPL_HARD_REG_SET (reg_rename_p
->available_for_renaming
,
1337 reg_rename_p
->unavailable_hard_regs
);
1339 /* Regno is always ok from the renaming part of view, but it really
1340 could be in *unavailable_hard_regs already, so set it here instead
1342 SET_HARD_REG_BIT (reg_rename_p
->available_for_renaming
, regno
);
1345 /* reg_rename_tick[REG1] > reg_rename_tick[REG2] if REG1 was chosen as the
1346 best register more recently than REG2. */
1347 static int reg_rename_tick
[FIRST_PSEUDO_REGISTER
];
1349 /* Indicates the number of times renaming happened before the current one. */
1350 static int reg_rename_this_tick
;
1352 /* Choose the register among free, that is suitable for storing
1355 ORIGINAL_INSNS is the list of insns where the operation (rhs)
1356 originally appears. There could be multiple original operations
1357 for single rhs since we moving it up and merging along different
1360 Some code is adapted from regrename.c (regrename_optimize).
1361 If original register is available, function returns it.
1362 Otherwise it performs the checks, so the new register should
1363 comply with the following:
1364 - it should not violate any live ranges (such registers are in
1365 REG_RENAME_P->available_for_renaming set);
1366 - it should not be in the HARD_REGS_USED regset;
1367 - it should be in the class compatible with original uses;
1368 - it should not be clobbered through reference with different mode;
1369 - if we're in the leaf function, then the new register should
1370 not be in the LEAF_REGISTERS;
1373 If several registers meet the conditions, the register with smallest
1374 tick is returned to achieve more even register allocation.
1376 If original register seems to be ok, we set *IS_ORIG_REG_P_PTR to true.
1378 If no register satisfies the above conditions, NULL_RTX is returned. */
1380 choose_best_reg_1 (HARD_REG_SET hard_regs_used
,
1381 struct reg_rename
*reg_rename_p
,
1382 def_list_t original_insns
, bool *is_orig_reg_p_ptr
)
1386 enum machine_mode mode
= VOIDmode
;
1387 unsigned regno
, i
, n
;
1388 hard_reg_set_iterator hrsi
;
1389 def_list_iterator di
;
1392 /* If original register is available, return it. */
1393 *is_orig_reg_p_ptr
= true;
1395 FOR_EACH_DEF (def
, di
, original_insns
)
1397 rtx orig_dest
= SET_DEST (PATTERN (def
->orig_insn
));
1399 gcc_assert (REG_P (orig_dest
));
1401 /* Check that all original operations have the same mode.
1402 This is done for the next loop; if we'd return from this
1403 loop, we'd check only part of them, but in this case
1404 it doesn't matter. */
1405 if (mode
== VOIDmode
)
1406 mode
= GET_MODE (orig_dest
);
1407 gcc_assert (mode
== GET_MODE (orig_dest
));
1409 regno
= REGNO (orig_dest
);
1410 for (i
= 0, n
= hard_regno_nregs
[regno
][mode
]; i
< n
; i
++)
1411 if (TEST_HARD_REG_BIT (hard_regs_used
, regno
+ i
))
1414 /* All hard registers are available. */
1417 gcc_assert (mode
!= VOIDmode
);
1419 /* Hard registers should not be shared. */
1420 return gen_rtx_REG (mode
, regno
);
1424 *is_orig_reg_p_ptr
= false;
1427 /* Among all available regs choose the register that was
1428 allocated earliest. */
1429 EXECUTE_IF_SET_IN_HARD_REG_SET (reg_rename_p
->available_for_renaming
,
1431 if (! TEST_HARD_REG_BIT (hard_regs_used
, cur_reg
))
1433 /* Check that all hard regs for mode are available. */
1434 for (i
= 1, n
= hard_regno_nregs
[cur_reg
][mode
]; i
< n
; i
++)
1435 if (TEST_HARD_REG_BIT (hard_regs_used
, cur_reg
+ i
)
1436 || !TEST_HARD_REG_BIT (reg_rename_p
->available_for_renaming
,
1443 /* All hard registers are available. */
1444 if (best_new_reg
< 0
1445 || reg_rename_tick
[cur_reg
] < reg_rename_tick
[best_new_reg
])
1447 best_new_reg
= cur_reg
;
1449 /* Return immediately when we know there's no better reg. */
1450 if (! reg_rename_tick
[best_new_reg
])
1455 if (best_new_reg
>= 0)
1457 /* Use the check from the above loop. */
1458 gcc_assert (mode
!= VOIDmode
);
1459 return gen_rtx_REG (mode
, best_new_reg
);
1465 /* A wrapper around choose_best_reg_1 () to verify that we make correct
1466 assumptions about available registers in the function. */
1468 choose_best_reg (HARD_REG_SET hard_regs_used
, struct reg_rename
*reg_rename_p
,
1469 def_list_t original_insns
, bool *is_orig_reg_p_ptr
)
1471 rtx best_reg
= choose_best_reg_1 (hard_regs_used
, reg_rename_p
,
1472 original_insns
, is_orig_reg_p_ptr
);
1474 /* FIXME loop over hard_regno_nregs here. */
1475 gcc_assert (best_reg
== NULL_RTX
1476 || TEST_HARD_REG_BIT (sel_hrd
.regs_ever_used
, REGNO (best_reg
)));
1481 /* Choose the pseudo register for storing rhs value. As this is supposed
1482 to work before reload, we return either the original register or make
1483 the new one. The parameters are the same that in choose_nest_reg_1
1484 functions, except that USED_REGS may contain pseudos.
1485 If we work with hard regs, check also REG_RENAME_P->UNAVAILABLE_HARD_REGS.
1487 TODO: take into account register pressure while doing this. Up to this
1488 moment, this function would never return NULL for pseudos, but we should
1489 not rely on this. */
1491 choose_best_pseudo_reg (regset used_regs
,
1492 struct reg_rename
*reg_rename_p
,
1493 def_list_t original_insns
, bool *is_orig_reg_p_ptr
)
1495 def_list_iterator i
;
1497 enum machine_mode mode
= VOIDmode
;
1498 bool bad_hard_regs
= false;
1500 /* We should not use this after reload. */
1501 gcc_assert (!reload_completed
);
1503 /* If original register is available, return it. */
1504 *is_orig_reg_p_ptr
= true;
1506 FOR_EACH_DEF (def
, i
, original_insns
)
1508 rtx dest
= SET_DEST (PATTERN (def
->orig_insn
));
1511 gcc_assert (REG_P (dest
));
1513 /* Check that all original operations have the same mode. */
1514 if (mode
== VOIDmode
)
1515 mode
= GET_MODE (dest
);
1517 gcc_assert (mode
== GET_MODE (dest
));
1518 orig_regno
= REGNO (dest
);
1520 if (!REGNO_REG_SET_P (used_regs
, orig_regno
))
1522 if (orig_regno
< FIRST_PSEUDO_REGISTER
)
1524 gcc_assert (df_regs_ever_live_p (orig_regno
));
1526 /* For hard registers, we have to check hardware imposed
1527 limitations (frame/stack registers, calls crossed). */
1528 if (!TEST_HARD_REG_BIT (reg_rename_p
->unavailable_hard_regs
,
1531 /* Don't let register cross a call if it doesn't already
1532 cross one. This condition is written in accordance with
1533 that in sched-deps.c sched_analyze_reg(). */
1534 if (!reg_rename_p
->crosses_call
1535 || REG_N_CALLS_CROSSED (orig_regno
) > 0)
1536 return gen_rtx_REG (mode
, orig_regno
);
1539 bad_hard_regs
= true;
1546 *is_orig_reg_p_ptr
= false;
1548 /* We had some original hard registers that couldn't be used.
1549 Those were likely special. Don't try to create a pseudo. */
1553 /* We haven't found a register from original operations. Get a new one.
1554 FIXME: control register pressure somehow. */
1556 rtx new_reg
= gen_reg_rtx (mode
);
1558 gcc_assert (mode
!= VOIDmode
);
1560 max_regno
= max_reg_num ();
1561 maybe_extend_reg_info_p ();
1562 REG_N_CALLS_CROSSED (REGNO (new_reg
)) = reg_rename_p
->crosses_call
? 1 : 0;
1568 /* True when target of EXPR is available due to EXPR_TARGET_AVAILABLE,
1569 USED_REGS and REG_RENAME_P->UNAVAILABLE_HARD_REGS. */
1571 verify_target_availability (expr_t expr
, regset used_regs
,
1572 struct reg_rename
*reg_rename_p
)
1574 unsigned n
, i
, regno
;
1575 enum machine_mode mode
;
1576 bool target_available
, live_available
, hard_available
;
1578 if (!REG_P (EXPR_LHS (expr
)) || EXPR_TARGET_AVAILABLE (expr
) < 0)
1581 regno
= expr_dest_regno (expr
);
1582 mode
= GET_MODE (EXPR_LHS (expr
));
1583 target_available
= EXPR_TARGET_AVAILABLE (expr
) == 1;
1584 n
= HARD_REGISTER_NUM_P (regno
) ? hard_regno_nregs
[regno
][mode
] : 1;
1586 live_available
= hard_available
= true;
1587 for (i
= 0; i
< n
; i
++)
1589 if (bitmap_bit_p (used_regs
, regno
+ i
))
1590 live_available
= false;
1591 if (TEST_HARD_REG_BIT (reg_rename_p
->unavailable_hard_regs
, regno
+ i
))
1592 hard_available
= false;
1595 /* When target is not available, it may be due to hard register
1596 restrictions, e.g. crosses calls, so we check hard_available too. */
1597 if (target_available
)
1598 gcc_assert (live_available
);
1600 /* Check only if we haven't scheduled something on the previous fence,
1601 cause due to MAX_SOFTWARE_LOOKAHEAD_WINDOW_SIZE issues
1602 and having more than one fence, we may end having targ_un in a block
1603 in which successors target register is actually available.
1605 The last condition handles the case when a dependence from a call insn
1606 was created in sched-deps.c for insns with destination registers that
1607 never crossed a call before, but do cross one after our code motion.
1609 FIXME: in the latter case, we just uselessly called find_used_regs,
1610 because we can't move this expression with any other register
1612 gcc_assert (scheduled_something_on_previous_fence
|| !live_available
1614 || (!reload_completed
&& reg_rename_p
->crosses_call
1615 && REG_N_CALLS_CROSSED (regno
) == 0));
1618 /* Collect unavailable registers due to liveness for EXPR from BNDS
1619 into USED_REGS. Save additional information about available
1620 registers and unavailable due to hardware restriction registers
1621 into REG_RENAME_P structure. Save original insns into ORIGINAL_INSNS
1624 collect_unavailable_regs_from_bnds (expr_t expr
, blist_t bnds
, regset used_regs
,
1625 struct reg_rename
*reg_rename_p
,
1626 def_list_t
*original_insns
)
1628 for (; bnds
; bnds
= BLIST_NEXT (bnds
))
1631 av_set_t orig_ops
= NULL
;
1632 bnd_t bnd
= BLIST_BND (bnds
);
1634 /* If the chosen best expr doesn't belong to current boundary,
1636 if (!av_set_is_in_p (BND_AV1 (bnd
), EXPR_VINSN (expr
)))
1639 /* Put in ORIG_OPS all exprs from this boundary that became
1641 orig_ops
= find_sequential_best_exprs (bnd
, expr
, false);
1643 /* Compute used regs and OR it into the USED_REGS. */
1644 res
= find_used_regs (BND_TO (bnd
), orig_ops
, used_regs
,
1645 reg_rename_p
, original_insns
);
1647 /* FIXME: the assert is true until we'd have several boundaries. */
1649 av_set_clear (&orig_ops
);
1653 /* Return TRUE if it is possible to replace LHSes of ORIG_INSNS with BEST_REG.
1654 If BEST_REG is valid, replace LHS of EXPR with it. */
1656 try_replace_dest_reg (ilist_t orig_insns
, rtx best_reg
, expr_t expr
)
1658 /* Try whether we'll be able to generate the insn
1659 'dest := best_reg' at the place of the original operation. */
1660 for (; orig_insns
; orig_insns
= ILIST_NEXT (orig_insns
))
1662 insn_t orig_insn
= DEF_LIST_DEF (orig_insns
)->orig_insn
;
1664 gcc_assert (EXPR_SEPARABLE_P (INSN_EXPR (orig_insn
)));
1666 if (REGNO (best_reg
) != REGNO (INSN_LHS (orig_insn
))
1667 && (! replace_src_with_reg_ok_p (orig_insn
, best_reg
)
1668 || ! replace_dest_with_reg_ok_p (orig_insn
, best_reg
)))
1672 /* Make sure that EXPR has the right destination
1674 if (expr_dest_regno (expr
) != REGNO (best_reg
))
1675 replace_dest_with_reg_in_expr (expr
, best_reg
);
1677 EXPR_TARGET_AVAILABLE (expr
) = 1;
1682 /* Select and assign best register to EXPR searching from BNDS.
1683 Set *IS_ORIG_REG_P to TRUE if original register was selected.
1684 Return FALSE if no register can be chosen, which could happen when:
1685 * EXPR_SEPARABLE_P is true but we were unable to find suitable register;
1686 * EXPR_SEPARABLE_P is false but the insn sets/clobbers one of the registers
1687 that are used on the moving path. */
1689 find_best_reg_for_expr (expr_t expr
, blist_t bnds
, bool *is_orig_reg_p
)
1691 static struct reg_rename reg_rename_data
;
1694 def_list_t original_insns
= NULL
;
1697 *is_orig_reg_p
= false;
1699 /* Don't bother to do anything if this insn doesn't set any registers. */
1700 if (bitmap_empty_p (VINSN_REG_SETS (EXPR_VINSN (expr
)))
1701 && bitmap_empty_p (VINSN_REG_CLOBBERS (EXPR_VINSN (expr
))))
1704 used_regs
= get_clear_regset_from_pool ();
1705 CLEAR_HARD_REG_SET (reg_rename_data
.unavailable_hard_regs
);
1707 collect_unavailable_regs_from_bnds (expr
, bnds
, used_regs
, ®_rename_data
,
1710 #ifdef ENABLE_CHECKING
1711 /* If after reload, make sure we're working with hard regs here. */
1712 if (reload_completed
)
1714 reg_set_iterator rsi
;
1717 EXECUTE_IF_SET_IN_REG_SET (used_regs
, FIRST_PSEUDO_REGISTER
, i
, rsi
)
1722 if (EXPR_SEPARABLE_P (expr
))
1724 rtx best_reg
= NULL_RTX
;
1725 /* Check that we have computed availability of a target register
1727 verify_target_availability (expr
, used_regs
, ®_rename_data
);
1729 /* Turn everything in hard regs after reload. */
1730 if (reload_completed
)
1732 HARD_REG_SET hard_regs_used
;
1733 REG_SET_TO_HARD_REG_SET (hard_regs_used
, used_regs
);
1735 /* Join hard registers unavailable due to register class
1736 restrictions and live range intersection. */
1737 IOR_HARD_REG_SET (hard_regs_used
,
1738 reg_rename_data
.unavailable_hard_regs
);
1740 best_reg
= choose_best_reg (hard_regs_used
, ®_rename_data
,
1741 original_insns
, is_orig_reg_p
);
1744 best_reg
= choose_best_pseudo_reg (used_regs
, ®_rename_data
,
1745 original_insns
, is_orig_reg_p
);
1749 else if (*is_orig_reg_p
)
1751 /* In case of unification BEST_REG may be different from EXPR's LHS
1752 when EXPR's LHS is unavailable, and there is another LHS among
1754 reg_ok
= try_replace_dest_reg (original_insns
, best_reg
, expr
);
1758 /* Forbid renaming of low-cost insns. */
1759 if (sel_vinsn_cost (EXPR_VINSN (expr
)) < 2)
1762 reg_ok
= try_replace_dest_reg (original_insns
, best_reg
, expr
);
1767 /* If !EXPR_SCHEDULE_AS_RHS (EXPR), just make sure INSN doesn't set
1768 any of the HARD_REGS_USED set. */
1769 if (vinsn_writes_one_of_regs_p (EXPR_VINSN (expr
), used_regs
,
1770 reg_rename_data
.unavailable_hard_regs
))
1773 gcc_assert (EXPR_TARGET_AVAILABLE (expr
) <= 0);
1778 gcc_assert (EXPR_TARGET_AVAILABLE (expr
) != 0);
1782 ilist_clear (&original_insns
);
1783 return_regset_to_pool (used_regs
);
1789 /* Return true if dependence described by DS can be overcomed. */
1791 can_speculate_dep_p (ds_t ds
)
1793 if (spec_info
== NULL
)
1796 /* Leave only speculative data. */
1803 /* FIXME: make sched-deps.c produce only those non-hard dependencies,
1804 that we can overcome. */
1805 ds_t spec_mask
= spec_info
->mask
;
1807 if ((ds
& spec_mask
) != ds
)
1811 if (ds_weak (ds
) < spec_info
->data_weakness_cutoff
)
1817 /* Get a speculation check instruction.
1818 C_EXPR is a speculative expression,
1819 CHECK_DS describes speculations that should be checked,
1820 ORIG_INSN is the original non-speculative insn in the stream. */
1822 create_speculation_check (expr_t c_expr
, ds_t check_ds
, insn_t orig_insn
)
1827 basic_block recovery_block
;
1830 /* Create a recovery block if target is going to emit branchy check, or if
1831 ORIG_INSN was speculative already. */
1832 if (targetm
.sched
.needs_block_p (check_ds
)
1833 || EXPR_SPEC_DONE_DS (INSN_EXPR (orig_insn
)) != 0)
1835 recovery_block
= sel_create_recovery_block (orig_insn
);
1836 label
= BB_HEAD (recovery_block
);
1840 recovery_block
= NULL
;
1844 /* Get pattern of the check. */
1845 check_pattern
= targetm
.sched
.gen_spec_check (EXPR_INSN_RTX (c_expr
), label
,
1848 gcc_assert (check_pattern
!= NULL
);
1851 insn_rtx
= create_insn_rtx_from_pattern (check_pattern
, label
);
1853 insn
= sel_gen_insn_from_rtx_after (insn_rtx
, INSN_EXPR (orig_insn
),
1854 INSN_SEQNO (orig_insn
), orig_insn
);
1856 /* Make check to be non-speculative. */
1857 EXPR_SPEC_DONE_DS (INSN_EXPR (insn
)) = 0;
1858 INSN_SPEC_CHECKED_DS (insn
) = check_ds
;
1860 /* Decrease priority of check by difference of load/check instruction
1862 EXPR_PRIORITY (INSN_EXPR (insn
)) -= (sel_vinsn_cost (INSN_VINSN (orig_insn
))
1863 - sel_vinsn_cost (INSN_VINSN (insn
)));
1865 /* Emit copy of original insn (though with replaced target register,
1866 if needed) to the recovery block. */
1867 if (recovery_block
!= NULL
)
1871 twin_rtx
= copy_rtx (PATTERN (EXPR_INSN_RTX (c_expr
)));
1872 twin_rtx
= create_insn_rtx_from_pattern (twin_rtx
, NULL_RTX
);
1873 sel_gen_recovery_insn_from_rtx_after (twin_rtx
,
1874 INSN_EXPR (orig_insn
),
1876 bb_note (recovery_block
));
1879 /* If we've generated a data speculation check, make sure
1880 that all the bookkeeping instruction we'll create during
1881 this move_op () will allocate an ALAT entry so that the
1883 In case of control speculation we must convert C_EXPR to control
1884 speculative mode, because failing to do so will bring us an exception
1885 thrown by the non-control-speculative load. */
1886 check_ds
= ds_get_max_dep_weak (check_ds
);
1887 speculate_expr (c_expr
, check_ds
);
1892 /* True when INSN is a "regN = regN" copy. */
1894 identical_copy_p (rtx insn
)
1898 pat
= PATTERN (insn
);
1900 if (GET_CODE (pat
) != SET
)
1903 lhs
= SET_DEST (pat
);
1907 rhs
= SET_SRC (pat
);
1911 return REGNO (lhs
) == REGNO (rhs
);
1914 /* Undo all transformations on *AV_PTR that were done when
1915 moving through INSN. */
1917 undo_transformations (av_set_t
*av_ptr
, rtx insn
)
1919 av_set_iterator av_iter
;
1921 av_set_t new_set
= NULL
;
1923 /* First, kill any EXPR that uses registers set by an insn. This is
1924 required for correctness. */
1925 FOR_EACH_EXPR_1 (expr
, av_iter
, av_ptr
)
1926 if (!sched_insns_conditions_mutex_p (insn
, EXPR_INSN_RTX (expr
))
1927 && bitmap_intersect_p (INSN_REG_SETS (insn
),
1928 VINSN_REG_USES (EXPR_VINSN (expr
)))
1929 /* When an insn looks like 'r1 = r1', we could substitute through
1930 it, but the above condition will still hold. This happened with
1931 gcc.c-torture/execute/961125-1.c. */
1932 && !identical_copy_p (insn
))
1934 if (sched_verbose
>= 6)
1935 sel_print ("Expr %d removed due to use/set conflict\n",
1936 INSN_UID (EXPR_INSN_RTX (expr
)));
1937 av_set_iter_remove (&av_iter
);
1940 /* Undo transformations looking at the history vector. */
1941 FOR_EACH_EXPR (expr
, av_iter
, *av_ptr
)
1943 int index
= find_in_history_vect (EXPR_HISTORY_OF_CHANGES (expr
),
1944 insn
, EXPR_VINSN (expr
), true);
1948 expr_history_def
*phist
;
1950 phist
= VEC_index (expr_history_def
,
1951 EXPR_HISTORY_OF_CHANGES (expr
),
1954 switch (phist
->type
)
1956 case TRANS_SPECULATION
:
1958 ds_t old_ds
, new_ds
;
1960 /* Compute the difference between old and new speculative
1961 statuses: that's what we need to check.
1962 Earlier we used to assert that the status will really
1963 change. This no longer works because only the probability
1964 bits in the status may have changed during compute_av_set,
1965 and in the case of merging different probabilities of the
1966 same speculative status along different paths we do not
1967 record this in the history vector. */
1968 old_ds
= phist
->spec_ds
;
1969 new_ds
= EXPR_SPEC_DONE_DS (expr
);
1971 old_ds
&= SPECULATIVE
;
1972 new_ds
&= SPECULATIVE
;
1975 EXPR_SPEC_TO_CHECK_DS (expr
) |= new_ds
;
1978 case TRANS_SUBSTITUTION
:
1980 expr_def _tmp_expr
, *tmp_expr
= &_tmp_expr
;
1984 new_vi
= phist
->old_expr_vinsn
;
1986 gcc_assert (VINSN_SEPARABLE_P (new_vi
)
1987 == EXPR_SEPARABLE_P (expr
));
1988 copy_expr (tmp_expr
, expr
);
1990 if (vinsn_equal_p (phist
->new_expr_vinsn
,
1991 EXPR_VINSN (tmp_expr
)))
1992 change_vinsn_in_expr (tmp_expr
, new_vi
);
1994 /* This happens when we're unsubstituting on a bookkeeping
1995 copy, which was in turn substituted. The history is wrong
1996 in this case. Do it the hard way. */
1997 add
= substitute_reg_in_expr (tmp_expr
, insn
, true);
1999 av_set_add (&new_set
, tmp_expr
);
2000 clear_expr (tmp_expr
);
2010 av_set_union_and_clear (av_ptr
, &new_set
, NULL
);
2014 /* Moveup_* helpers for code motion and computing av sets. */
2016 /* Propagates EXPR inside an insn group through THROUGH_INSN.
2017 The difference from the below function is that only substitution is
2019 static enum MOVEUP_EXPR_CODE
2020 moveup_expr_inside_insn_group (expr_t expr
, insn_t through_insn
)
2022 vinsn_t vi
= EXPR_VINSN (expr
);
2026 /* Do this only inside insn group. */
2027 gcc_assert (INSN_SCHED_CYCLE (through_insn
) > 0);
2029 full_ds
= has_dependence_p (expr
, through_insn
, &has_dep_p
);
2031 return MOVEUP_EXPR_SAME
;
2033 /* Substitution is the possible choice in this case. */
2034 if (has_dep_p
[DEPS_IN_RHS
])
2036 /* Can't substitute UNIQUE VINSNs. */
2037 gcc_assert (!VINSN_UNIQUE_P (vi
));
2039 if (can_substitute_through_p (through_insn
,
2040 has_dep_p
[DEPS_IN_RHS
])
2041 && substitute_reg_in_expr (expr
, through_insn
, false))
2043 EXPR_WAS_SUBSTITUTED (expr
) = true;
2044 return MOVEUP_EXPR_CHANGED
;
2047 /* Don't care about this, as even true dependencies may be allowed
2048 in an insn group. */
2049 return MOVEUP_EXPR_SAME
;
2052 /* This can catch output dependencies in COND_EXECs. */
2053 if (has_dep_p
[DEPS_IN_INSN
])
2054 return MOVEUP_EXPR_NULL
;
2056 /* This is either an output or an anti dependence, which usually have
2057 a zero latency. Allow this here, if we'd be wrong, tick_check_p
2059 gcc_assert (has_dep_p
[DEPS_IN_LHS
]);
2060 return MOVEUP_EXPR_AS_RHS
;
2063 /* True when a trapping EXPR cannot be moved through THROUGH_INSN. */
2064 #define CANT_MOVE_TRAPPING(expr, through_insn) \
2065 (VINSN_MAY_TRAP_P (EXPR_VINSN (expr)) \
2066 && !sel_insn_has_single_succ_p ((through_insn), SUCCS_ALL) \
2067 && !sel_insn_is_speculation_check (through_insn))
2069 /* True when a conflict on a target register was found during moveup_expr. */
2070 static bool was_target_conflict
= false;
2072 /* Return true when moving a debug INSN across THROUGH_INSN will
2073 create a bookkeeping block. We don't want to create such blocks,
2074 for they would cause codegen differences between compilations with
2075 and without debug info. */
2078 moving_insn_creates_bookkeeping_block_p (insn_t insn
,
2079 insn_t through_insn
)
2081 basic_block bbi
, bbt
;
2083 edge_iterator ei1
, ei2
;
2085 if (!bookkeeping_can_be_created_if_moved_through_p (through_insn
))
2087 if (sched_verbose
>= 9)
2088 sel_print ("no bookkeeping required: ");
2092 bbi
= BLOCK_FOR_INSN (insn
);
2094 if (EDGE_COUNT (bbi
->preds
) == 1)
2096 if (sched_verbose
>= 9)
2097 sel_print ("only one pred edge: ");
2101 bbt
= BLOCK_FOR_INSN (through_insn
);
2103 FOR_EACH_EDGE (e1
, ei1
, bbt
->succs
)
2105 FOR_EACH_EDGE (e2
, ei2
, bbi
->preds
)
2107 if (find_block_for_bookkeeping (e1
, e2
, TRUE
))
2109 if (sched_verbose
>= 9)
2110 sel_print ("found existing block: ");
2116 if (sched_verbose
>= 9)
2117 sel_print ("would create bookkeeping block: ");
2122 /* Modifies EXPR so it can be moved through the THROUGH_INSN,
2123 performing necessary transformations. Record the type of transformation
2124 made in PTRANS_TYPE, when it is not NULL. When INSIDE_INSN_GROUP,
2125 permit all dependencies except true ones, and try to remove those
2126 too via forward substitution. All cases when a non-eliminable
2127 non-zero cost dependency exists inside an insn group will be fixed
2128 in tick_check_p instead. */
2129 static enum MOVEUP_EXPR_CODE
2130 moveup_expr (expr_t expr
, insn_t through_insn
, bool inside_insn_group
,
2131 enum local_trans_type
*ptrans_type
)
2133 vinsn_t vi
= EXPR_VINSN (expr
);
2134 insn_t insn
= VINSN_INSN_RTX (vi
);
2135 bool was_changed
= false;
2136 bool as_rhs
= false;
2140 /* ??? We use dependencies of non-debug insns on debug insns to
2141 indicate that the debug insns need to be reset if the non-debug
2142 insn is pulled ahead of it. It's hard to figure out how to
2143 introduce such a notion in sel-sched, but it already fails to
2144 support debug insns in other ways, so we just go ahead and
2145 let the deug insns go corrupt for now. */
2146 if (DEBUG_INSN_P (through_insn
) && !DEBUG_INSN_P (insn
))
2147 return MOVEUP_EXPR_SAME
;
2149 /* When inside_insn_group, delegate to the helper. */
2150 if (inside_insn_group
)
2151 return moveup_expr_inside_insn_group (expr
, through_insn
);
2153 /* Deal with unique insns and control dependencies. */
2154 if (VINSN_UNIQUE_P (vi
))
2156 /* We can move jumps without side-effects or jumps that are
2157 mutually exclusive with instruction THROUGH_INSN (all in cases
2158 dependencies allow to do so and jump is not speculative). */
2159 if (control_flow_insn_p (insn
))
2161 basic_block fallthru_bb
;
2163 /* Do not move checks and do not move jumps through other
2165 if (control_flow_insn_p (through_insn
)
2166 || sel_insn_is_speculation_check (insn
))
2167 return MOVEUP_EXPR_NULL
;
2169 /* Don't move jumps through CFG joins. */
2170 if (bookkeeping_can_be_created_if_moved_through_p (through_insn
))
2171 return MOVEUP_EXPR_NULL
;
2173 /* The jump should have a clear fallthru block, and
2174 this block should be in the current region. */
2175 if ((fallthru_bb
= fallthru_bb_of_jump (insn
)) == NULL
2176 || ! in_current_region_p (fallthru_bb
))
2177 return MOVEUP_EXPR_NULL
;
2179 /* And it should be mutually exclusive with through_insn. */
2180 if (! sched_insns_conditions_mutex_p (insn
, through_insn
)
2181 && ! DEBUG_INSN_P (through_insn
))
2182 return MOVEUP_EXPR_NULL
;
2185 /* Don't move what we can't move. */
2186 if (EXPR_CANT_MOVE (expr
)
2187 && BLOCK_FOR_INSN (through_insn
) != BLOCK_FOR_INSN (insn
))
2188 return MOVEUP_EXPR_NULL
;
2190 /* Don't move SCHED_GROUP instruction through anything.
2191 If we don't force this, then it will be possible to start
2192 scheduling a sched_group before all its dependencies are
2194 ??? Haifa deals with this issue by delaying the SCHED_GROUP
2195 as late as possible through rank_for_schedule. */
2196 if (SCHED_GROUP_P (insn
))
2197 return MOVEUP_EXPR_NULL
;
2200 gcc_assert (!control_flow_insn_p (insn
));
2202 /* Don't move debug insns if this would require bookkeeping. */
2203 if (DEBUG_INSN_P (insn
)
2204 && BLOCK_FOR_INSN (through_insn
) != BLOCK_FOR_INSN (insn
)
2205 && moving_insn_creates_bookkeeping_block_p (insn
, through_insn
))
2206 return MOVEUP_EXPR_NULL
;
2208 /* Deal with data dependencies. */
2209 was_target_conflict
= false;
2210 full_ds
= has_dependence_p (expr
, through_insn
, &has_dep_p
);
2213 if (!CANT_MOVE_TRAPPING (expr
, through_insn
))
2214 return MOVEUP_EXPR_SAME
;
2218 /* We can move UNIQUE insn up only as a whole and unchanged,
2219 so it shouldn't have any dependencies. */
2220 if (VINSN_UNIQUE_P (vi
))
2221 return MOVEUP_EXPR_NULL
;
2224 if (full_ds
!= 0 && can_speculate_dep_p (full_ds
))
2228 res
= speculate_expr (expr
, full_ds
);
2231 /* Speculation was successful. */
2233 was_changed
= (res
> 0);
2235 was_target_conflict
= true;
2237 *ptrans_type
= TRANS_SPECULATION
;
2238 sel_clear_has_dependence ();
2242 if (has_dep_p
[DEPS_IN_INSN
])
2243 /* We have some dependency that cannot be discarded. */
2244 return MOVEUP_EXPR_NULL
;
2246 if (has_dep_p
[DEPS_IN_LHS
])
2248 /* Only separable insns can be moved up with the new register.
2249 Anyways, we should mark that the original register is
2251 if (!enable_schedule_as_rhs_p
|| !EXPR_SEPARABLE_P (expr
))
2252 return MOVEUP_EXPR_NULL
;
2254 EXPR_TARGET_AVAILABLE (expr
) = false;
2255 was_target_conflict
= true;
2259 /* At this point we have either separable insns, that will be lifted
2260 up only as RHSes, or non-separable insns with no dependency in lhs.
2261 If dependency is in RHS, then try to perform substitution and move up
2268 In Ex.1 y*2 can be substituted for x*2 and the whole operation can be
2269 moved above y=x assignment as z=x*2.
2271 In Ex.2 y*2 also can be substituted for x*2, but only the right hand
2272 side can be moved because of the output dependency. The operation was
2273 cropped to its rhs above. */
2274 if (has_dep_p
[DEPS_IN_RHS
])
2276 ds_t
*rhs_dsp
= &has_dep_p
[DEPS_IN_RHS
];
2278 /* Can't substitute UNIQUE VINSNs. */
2279 gcc_assert (!VINSN_UNIQUE_P (vi
));
2281 if (can_speculate_dep_p (*rhs_dsp
))
2285 res
= speculate_expr (expr
, *rhs_dsp
);
2288 /* Speculation was successful. */
2290 was_changed
= (res
> 0);
2292 was_target_conflict
= true;
2294 *ptrans_type
= TRANS_SPECULATION
;
2297 return MOVEUP_EXPR_NULL
;
2299 else if (can_substitute_through_p (through_insn
,
2301 && substitute_reg_in_expr (expr
, through_insn
, false))
2303 /* ??? We cannot perform substitution AND speculation on the same
2305 gcc_assert (!was_changed
);
2308 *ptrans_type
= TRANS_SUBSTITUTION
;
2309 EXPR_WAS_SUBSTITUTED (expr
) = true;
2312 return MOVEUP_EXPR_NULL
;
2315 /* Don't move trapping insns through jumps.
2316 This check should be at the end to give a chance to control speculation
2317 to perform its duties. */
2318 if (CANT_MOVE_TRAPPING (expr
, through_insn
))
2319 return MOVEUP_EXPR_NULL
;
2322 ? MOVEUP_EXPR_CHANGED
2324 ? MOVEUP_EXPR_AS_RHS
2325 : MOVEUP_EXPR_SAME
));
2328 /* Try to look at bitmap caches for EXPR and INSN pair, return true
2329 if successful. When INSIDE_INSN_GROUP, also try ignore dependencies
2330 that can exist within a parallel group. Write to RES the resulting
2331 code for moveup_expr. */
2333 try_bitmap_cache (expr_t expr
, insn_t insn
,
2334 bool inside_insn_group
,
2335 enum MOVEUP_EXPR_CODE
*res
)
2337 int expr_uid
= INSN_UID (EXPR_INSN_RTX (expr
));
2339 /* First check whether we've analyzed this situation already. */
2340 if (bitmap_bit_p (INSN_ANALYZED_DEPS (insn
), expr_uid
))
2342 if (bitmap_bit_p (INSN_FOUND_DEPS (insn
), expr_uid
))
2344 if (sched_verbose
>= 6)
2345 sel_print ("removed (cached)\n");
2346 *res
= MOVEUP_EXPR_NULL
;
2351 if (sched_verbose
>= 6)
2352 sel_print ("unchanged (cached)\n");
2353 *res
= MOVEUP_EXPR_SAME
;
2357 else if (bitmap_bit_p (INSN_FOUND_DEPS (insn
), expr_uid
))
2359 if (inside_insn_group
)
2361 if (sched_verbose
>= 6)
2362 sel_print ("unchanged (as RHS, cached, inside insn group)\n");
2363 *res
= MOVEUP_EXPR_SAME
;
2368 EXPR_TARGET_AVAILABLE (expr
) = false;
2370 /* This is the only case when propagation result can change over time,
2371 as we can dynamically switch off scheduling as RHS. In this case,
2372 just check the flag to reach the correct decision. */
2373 if (enable_schedule_as_rhs_p
)
2375 if (sched_verbose
>= 6)
2376 sel_print ("unchanged (as RHS, cached)\n");
2377 *res
= MOVEUP_EXPR_AS_RHS
;
2382 if (sched_verbose
>= 6)
2383 sel_print ("removed (cached as RHS, but renaming"
2384 " is now disabled)\n");
2385 *res
= MOVEUP_EXPR_NULL
;
2393 /* Try to look at bitmap caches for EXPR and INSN pair, return true
2394 if successful. Write to RES the resulting code for moveup_expr. */
2396 try_transformation_cache (expr_t expr
, insn_t insn
,
2397 enum MOVEUP_EXPR_CODE
*res
)
2399 struct transformed_insns
*pti
2400 = (struct transformed_insns
*)
2401 htab_find_with_hash (INSN_TRANSFORMED_INSNS (insn
),
2403 VINSN_HASH_RTX (EXPR_VINSN (expr
)));
2406 /* This EXPR was already moved through this insn and was
2407 changed as a result. Fetch the proper data from
2409 insert_in_history_vect (&EXPR_HISTORY_OF_CHANGES (expr
),
2410 INSN_UID (insn
), pti
->type
,
2411 pti
->vinsn_old
, pti
->vinsn_new
,
2412 EXPR_SPEC_DONE_DS (expr
));
2414 if (INSN_IN_STREAM_P (VINSN_INSN_RTX (pti
->vinsn_new
)))
2415 pti
->vinsn_new
= vinsn_copy (pti
->vinsn_new
, true);
2416 change_vinsn_in_expr (expr
, pti
->vinsn_new
);
2417 if (pti
->was_target_conflict
)
2418 EXPR_TARGET_AVAILABLE (expr
) = false;
2419 if (pti
->type
== TRANS_SPECULATION
)
2421 EXPR_SPEC_DONE_DS (expr
) = pti
->ds
;
2422 EXPR_NEEDS_SPEC_CHECK_P (expr
) |= pti
->needs_check
;
2425 if (sched_verbose
>= 6)
2427 sel_print ("changed (cached): ");
2432 *res
= MOVEUP_EXPR_CHANGED
;
2439 /* Update bitmap caches on INSN with result RES of propagating EXPR. */
2441 update_bitmap_cache (expr_t expr
, insn_t insn
, bool inside_insn_group
,
2442 enum MOVEUP_EXPR_CODE res
)
2444 int expr_uid
= INSN_UID (EXPR_INSN_RTX (expr
));
2446 /* Do not cache result of propagating jumps through an insn group,
2447 as it is always true, which is not useful outside the group. */
2448 if (inside_insn_group
)
2451 if (res
== MOVEUP_EXPR_NULL
)
2453 bitmap_set_bit (INSN_ANALYZED_DEPS (insn
), expr_uid
);
2454 bitmap_set_bit (INSN_FOUND_DEPS (insn
), expr_uid
);
2456 else if (res
== MOVEUP_EXPR_SAME
)
2458 bitmap_set_bit (INSN_ANALYZED_DEPS (insn
), expr_uid
);
2459 bitmap_clear_bit (INSN_FOUND_DEPS (insn
), expr_uid
);
2461 else if (res
== MOVEUP_EXPR_AS_RHS
)
2463 bitmap_clear_bit (INSN_ANALYZED_DEPS (insn
), expr_uid
);
2464 bitmap_set_bit (INSN_FOUND_DEPS (insn
), expr_uid
);
2470 /* Update hashtable on INSN with changed EXPR, old EXPR_OLD_VINSN
2471 and transformation type TRANS_TYPE. */
2473 update_transformation_cache (expr_t expr
, insn_t insn
,
2474 bool inside_insn_group
,
2475 enum local_trans_type trans_type
,
2476 vinsn_t expr_old_vinsn
)
2478 struct transformed_insns
*pti
;
2480 if (inside_insn_group
)
2483 pti
= XNEW (struct transformed_insns
);
2484 pti
->vinsn_old
= expr_old_vinsn
;
2485 pti
->vinsn_new
= EXPR_VINSN (expr
);
2486 pti
->type
= trans_type
;
2487 pti
->was_target_conflict
= was_target_conflict
;
2488 pti
->ds
= EXPR_SPEC_DONE_DS (expr
);
2489 pti
->needs_check
= EXPR_NEEDS_SPEC_CHECK_P (expr
);
2490 vinsn_attach (pti
->vinsn_old
);
2491 vinsn_attach (pti
->vinsn_new
);
2492 *((struct transformed_insns
**)
2493 htab_find_slot_with_hash (INSN_TRANSFORMED_INSNS (insn
),
2494 pti
, VINSN_HASH_RTX (expr_old_vinsn
),
2498 /* Same as moveup_expr, but first looks up the result of
2499 transformation in caches. */
2500 static enum MOVEUP_EXPR_CODE
2501 moveup_expr_cached (expr_t expr
, insn_t insn
, bool inside_insn_group
)
2503 enum MOVEUP_EXPR_CODE res
;
2504 bool got_answer
= false;
2506 if (sched_verbose
>= 6)
2508 sel_print ("Moving ");
2510 sel_print (" through %d: ", INSN_UID (insn
));
2513 if (DEBUG_INSN_P (EXPR_INSN_RTX (expr
))
2514 && (sel_bb_head (BLOCK_FOR_INSN (EXPR_INSN_RTX (expr
)))
2515 == EXPR_INSN_RTX (expr
)))
2516 /* Don't use cached information for debug insns that are heads of
2518 else if (try_bitmap_cache (expr
, insn
, inside_insn_group
, &res
))
2519 /* When inside insn group, we do not want remove stores conflicting
2520 with previosly issued loads. */
2521 got_answer
= ! inside_insn_group
|| res
!= MOVEUP_EXPR_NULL
;
2522 else if (try_transformation_cache (expr
, insn
, &res
))
2527 /* Invoke moveup_expr and record the results. */
2528 vinsn_t expr_old_vinsn
= EXPR_VINSN (expr
);
2529 ds_t expr_old_spec_ds
= EXPR_SPEC_DONE_DS (expr
);
2530 int expr_uid
= INSN_UID (VINSN_INSN_RTX (expr_old_vinsn
));
2531 bool unique_p
= VINSN_UNIQUE_P (expr_old_vinsn
);
2532 enum local_trans_type trans_type
= TRANS_SUBSTITUTION
;
2534 /* ??? Invent something better than this. We can't allow old_vinsn
2535 to go, we need it for the history vector. */
2536 vinsn_attach (expr_old_vinsn
);
2538 res
= moveup_expr (expr
, insn
, inside_insn_group
,
2542 case MOVEUP_EXPR_NULL
:
2543 update_bitmap_cache (expr
, insn
, inside_insn_group
, res
);
2544 if (sched_verbose
>= 6)
2545 sel_print ("removed\n");
2548 case MOVEUP_EXPR_SAME
:
2549 update_bitmap_cache (expr
, insn
, inside_insn_group
, res
);
2550 if (sched_verbose
>= 6)
2551 sel_print ("unchanged\n");
2554 case MOVEUP_EXPR_AS_RHS
:
2555 gcc_assert (!unique_p
|| inside_insn_group
);
2556 update_bitmap_cache (expr
, insn
, inside_insn_group
, res
);
2557 if (sched_verbose
>= 6)
2558 sel_print ("unchanged (as RHS)\n");
2561 case MOVEUP_EXPR_CHANGED
:
2562 gcc_assert (INSN_UID (EXPR_INSN_RTX (expr
)) != expr_uid
2563 || EXPR_SPEC_DONE_DS (expr
) != expr_old_spec_ds
);
2564 insert_in_history_vect (&EXPR_HISTORY_OF_CHANGES (expr
),
2565 INSN_UID (insn
), trans_type
,
2566 expr_old_vinsn
, EXPR_VINSN (expr
),
2568 update_transformation_cache (expr
, insn
, inside_insn_group
,
2569 trans_type
, expr_old_vinsn
);
2570 if (sched_verbose
>= 6)
2572 sel_print ("changed: ");
2581 vinsn_detach (expr_old_vinsn
);
2587 /* Moves an av set AVP up through INSN, performing necessary
2590 moveup_set_expr (av_set_t
*avp
, insn_t insn
, bool inside_insn_group
)
2595 FOR_EACH_EXPR_1 (expr
, i
, avp
)
2598 switch (moveup_expr_cached (expr
, insn
, inside_insn_group
))
2600 case MOVEUP_EXPR_SAME
:
2601 case MOVEUP_EXPR_AS_RHS
:
2604 case MOVEUP_EXPR_NULL
:
2605 av_set_iter_remove (&i
);
2608 case MOVEUP_EXPR_CHANGED
:
2609 expr
= merge_with_other_exprs (avp
, &i
, expr
);
2618 /* Moves AVP set along PATH. */
2620 moveup_set_inside_insn_group (av_set_t
*avp
, ilist_t path
)
2624 if (sched_verbose
>= 6)
2625 sel_print ("Moving expressions up in the insn group...\n");
2628 last_cycle
= INSN_SCHED_CYCLE (ILIST_INSN (path
));
2630 && INSN_SCHED_CYCLE (ILIST_INSN (path
)) == last_cycle
)
2632 moveup_set_expr (avp
, ILIST_INSN (path
), true);
2633 path
= ILIST_NEXT (path
);
2637 /* Returns true if after moving EXPR along PATH it equals to EXPR_VLIW. */
2639 equal_after_moveup_path_p (expr_t expr
, ilist_t path
, expr_t expr_vliw
)
2641 expr_def _tmp
, *tmp
= &_tmp
;
2645 copy_expr_onside (tmp
, expr
);
2646 last_cycle
= path
? INSN_SCHED_CYCLE (ILIST_INSN (path
)) : 0;
2649 && INSN_SCHED_CYCLE (ILIST_INSN (path
)) == last_cycle
)
2651 res
= (moveup_expr_cached (tmp
, ILIST_INSN (path
), true)
2652 != MOVEUP_EXPR_NULL
);
2653 path
= ILIST_NEXT (path
);
2658 vinsn_t tmp_vinsn
= EXPR_VINSN (tmp
);
2659 vinsn_t expr_vliw_vinsn
= EXPR_VINSN (expr_vliw
);
2661 if (tmp_vinsn
!= expr_vliw_vinsn
)
2662 res
= vinsn_equal_p (tmp_vinsn
, expr_vliw_vinsn
);
2670 /* Functions that compute av and lv sets. */
2672 /* Returns true if INSN is not a downward continuation of the given path P in
2673 the current stage. */
2675 is_ineligible_successor (insn_t insn
, ilist_t p
)
2679 /* Check if insn is not deleted. */
2680 if (PREV_INSN (insn
) && NEXT_INSN (PREV_INSN (insn
)) != insn
)
2682 else if (NEXT_INSN (insn
) && PREV_INSN (NEXT_INSN (insn
)) != insn
)
2685 /* If it's the first insn visited, then the successor is ok. */
2689 prev_insn
= ILIST_INSN (p
);
2691 if (/* a backward edge. */
2692 INSN_SEQNO (insn
) < INSN_SEQNO (prev_insn
)
2693 /* is already visited. */
2694 || (INSN_SEQNO (insn
) == INSN_SEQNO (prev_insn
)
2695 && (ilist_is_in_p (p
, insn
)
2696 /* We can reach another fence here and still seqno of insn
2697 would be equal to seqno of prev_insn. This is possible
2698 when prev_insn is a previously created bookkeeping copy.
2699 In that case it'd get a seqno of insn. Thus, check here
2700 whether insn is in current fence too. */
2701 || IN_CURRENT_FENCE_P (insn
)))
2702 /* Was already scheduled on this round. */
2703 || (INSN_SEQNO (insn
) > INSN_SEQNO (prev_insn
)
2704 && IN_CURRENT_FENCE_P (insn
))
2705 /* An insn from another fence could also be
2706 scheduled earlier even if this insn is not in
2707 a fence list right now. Check INSN_SCHED_CYCLE instead. */
2709 && INSN_SCHED_TIMES (insn
) > 0))
2715 /* Computes the av_set below the last bb insn INSN, doing all the 'dirty work'
2716 of handling multiple successors and properly merging its av_sets. P is
2717 the current path traversed. WS is the size of lookahead window.
2718 Return the av set computed. */
2720 compute_av_set_at_bb_end (insn_t insn
, ilist_t p
, int ws
)
2722 struct succs_info
*sinfo
;
2723 av_set_t expr_in_all_succ_branches
= NULL
;
2725 insn_t succ
, zero_succ
= NULL
;
2726 av_set_t av1
= NULL
;
2728 gcc_assert (sel_bb_end_p (insn
));
2730 /* Find different kind of successors needed for correct computing of
2731 SPEC and TARGET_AVAILABLE attributes. */
2732 sinfo
= compute_succs_info (insn
, SUCCS_NORMAL
);
2735 if (sched_verbose
>= 6)
2737 sel_print ("successors of bb end (%d): ", INSN_UID (insn
));
2738 dump_insn_vector (sinfo
->succs_ok
);
2740 if (sinfo
->succs_ok_n
!= sinfo
->all_succs_n
)
2741 sel_print ("real successors num: %d\n", sinfo
->all_succs_n
);
2744 /* Add insn to the tail of current path. */
2745 ilist_add (&p
, insn
);
2747 FOR_EACH_VEC_ELT (rtx
, sinfo
->succs_ok
, is
, succ
)
2751 /* We will edit SUCC_SET and EXPR_SPEC field of its elements. */
2752 succ_set
= compute_av_set_inside_bb (succ
, p
, ws
, true);
2754 av_set_split_usefulness (succ_set
,
2755 VEC_index (int, sinfo
->probs_ok
, is
),
2758 if (sinfo
->all_succs_n
> 1)
2760 /* Find EXPR'es that came from *all* successors and save them
2761 into expr_in_all_succ_branches. This set will be used later
2762 for calculating speculation attributes of EXPR'es. */
2765 expr_in_all_succ_branches
= av_set_copy (succ_set
);
2767 /* Remember the first successor for later. */
2775 FOR_EACH_EXPR_1 (expr
, i
, &expr_in_all_succ_branches
)
2776 if (!av_set_is_in_p (succ_set
, EXPR_VINSN (expr
)))
2777 av_set_iter_remove (&i
);
2781 /* Union the av_sets. Check liveness restrictions on target registers
2782 in special case of two successors. */
2783 if (sinfo
->succs_ok_n
== 2 && is
== 1)
2785 basic_block bb0
= BLOCK_FOR_INSN (zero_succ
);
2786 basic_block bb1
= BLOCK_FOR_INSN (succ
);
2788 gcc_assert (BB_LV_SET_VALID_P (bb0
) && BB_LV_SET_VALID_P (bb1
));
2789 av_set_union_and_live (&av1
, &succ_set
,
2795 av_set_union_and_clear (&av1
, &succ_set
, insn
);
2798 /* Check liveness restrictions via hard way when there are more than
2800 if (sinfo
->succs_ok_n
> 2)
2801 FOR_EACH_VEC_ELT (rtx
, sinfo
->succs_ok
, is
, succ
)
2803 basic_block succ_bb
= BLOCK_FOR_INSN (succ
);
2805 gcc_assert (BB_LV_SET_VALID_P (succ_bb
));
2806 mark_unavailable_targets (av1
, BB_AV_SET (succ_bb
),
2807 BB_LV_SET (succ_bb
));
2810 /* Finally, check liveness restrictions on paths leaving the region. */
2811 if (sinfo
->all_succs_n
> sinfo
->succs_ok_n
)
2812 FOR_EACH_VEC_ELT (rtx
, sinfo
->succs_other
, is
, succ
)
2813 mark_unavailable_targets
2814 (av1
, NULL
, BB_LV_SET (BLOCK_FOR_INSN (succ
)));
2816 if (sinfo
->all_succs_n
> 1)
2821 /* Increase the spec attribute of all EXPR'es that didn't come
2822 from all successors. */
2823 FOR_EACH_EXPR (expr
, i
, av1
)
2824 if (!av_set_is_in_p (expr_in_all_succ_branches
, EXPR_VINSN (expr
)))
2827 av_set_clear (&expr_in_all_succ_branches
);
2829 /* Do not move conditional branches through other
2830 conditional branches. So, remove all conditional
2831 branches from av_set if current operator is a conditional
2833 av_set_substract_cond_branches (&av1
);
2837 free_succs_info (sinfo
);
2839 if (sched_verbose
>= 6)
2841 sel_print ("av_succs (%d): ", INSN_UID (insn
));
2849 /* This function computes av_set for the FIRST_INSN by dragging valid
2850 av_set through all basic block insns either from the end of basic block
2851 (computed using compute_av_set_at_bb_end) or from the insn on which
2852 MAX_WS was exceeded. It uses compute_av_set_at_bb_end to compute av_set
2853 below the basic block and handling conditional branches.
2854 FIRST_INSN - the basic block head, P - path consisting of the insns
2855 traversed on the way to the FIRST_INSN (the path is sparse, only bb heads
2856 and bb ends are added to the path), WS - current window size,
2857 NEED_COPY_P - true if we'll make a copy of av_set before returning it. */
2859 compute_av_set_inside_bb (insn_t first_insn
, ilist_t p
, int ws
,
2864 insn_t bb_end
= sel_bb_end (BLOCK_FOR_INSN (first_insn
));
2865 insn_t after_bb_end
= NEXT_INSN (bb_end
);
2868 basic_block cur_bb
= BLOCK_FOR_INSN (first_insn
);
2870 /* Return NULL if insn is not on the legitimate downward path. */
2871 if (is_ineligible_successor (first_insn
, p
))
2873 if (sched_verbose
>= 6)
2874 sel_print ("Insn %d is ineligible_successor\n", INSN_UID (first_insn
));
2879 /* If insn already has valid av(insn) computed, just return it. */
2880 if (AV_SET_VALID_P (first_insn
))
2884 if (sel_bb_head_p (first_insn
))
2885 av_set
= BB_AV_SET (BLOCK_FOR_INSN (first_insn
));
2889 if (sched_verbose
>= 6)
2891 sel_print ("Insn %d has a valid av set: ", INSN_UID (first_insn
));
2892 dump_av_set (av_set
);
2896 return need_copy_p
? av_set_copy (av_set
) : av_set
;
2899 ilist_add (&p
, first_insn
);
2901 /* As the result after this loop have completed, in LAST_INSN we'll
2902 have the insn which has valid av_set to start backward computation
2903 from: it either will be NULL because on it the window size was exceeded
2904 or other valid av_set as returned by compute_av_set for the last insn
2905 of the basic block. */
2906 for (last_insn
= first_insn
; last_insn
!= after_bb_end
;
2907 last_insn
= NEXT_INSN (last_insn
))
2909 /* We may encounter valid av_set not only on bb_head, but also on
2910 those insns on which previously MAX_WS was exceeded. */
2911 if (AV_SET_VALID_P (last_insn
))
2913 if (sched_verbose
>= 6)
2914 sel_print ("Insn %d has a valid empty av set\n", INSN_UID (last_insn
));
2918 /* The special case: the last insn of the BB may be an
2919 ineligible_successor due to its SEQ_NO that was set on
2920 it as a bookkeeping. */
2921 if (last_insn
!= first_insn
2922 && is_ineligible_successor (last_insn
, p
))
2924 if (sched_verbose
>= 6)
2925 sel_print ("Insn %d is ineligible_successor\n", INSN_UID (last_insn
));
2929 if (DEBUG_INSN_P (last_insn
))
2932 if (end_ws
> max_ws
)
2934 /* We can reach max lookahead size at bb_header, so clean av_set
2936 INSN_WS_LEVEL (last_insn
) = global_level
;
2938 if (sched_verbose
>= 6)
2939 sel_print ("Insn %d is beyond the software lookahead window size\n",
2940 INSN_UID (last_insn
));
2947 /* Get the valid av_set into AV above the LAST_INSN to start backward
2948 computation from. It either will be empty av_set or av_set computed from
2949 the successors on the last insn of the current bb. */
2950 if (last_insn
!= after_bb_end
)
2954 /* This is needed only to obtain av_sets that are identical to
2955 those computed by the old compute_av_set version. */
2956 if (last_insn
== first_insn
&& !INSN_NOP_P (last_insn
))
2957 av_set_add (&av
, INSN_EXPR (last_insn
));
2960 /* END_WS is always already increased by 1 if LAST_INSN == AFTER_BB_END. */
2961 av
= compute_av_set_at_bb_end (bb_end
, p
, end_ws
);
2963 /* Compute av_set in AV starting from below the LAST_INSN up to
2964 location above the FIRST_INSN. */
2965 for (cur_insn
= PREV_INSN (last_insn
); cur_insn
!= PREV_INSN (first_insn
);
2966 cur_insn
= PREV_INSN (cur_insn
))
2967 if (!INSN_NOP_P (cur_insn
))
2971 moveup_set_expr (&av
, cur_insn
, false);
2973 /* If the expression for CUR_INSN is already in the set,
2974 replace it by the new one. */
2975 expr
= av_set_lookup (av
, INSN_VINSN (cur_insn
));
2979 copy_expr (expr
, INSN_EXPR (cur_insn
));
2982 av_set_add (&av
, INSN_EXPR (cur_insn
));
2985 /* Clear stale bb_av_set. */
2986 if (sel_bb_head_p (first_insn
))
2988 av_set_clear (&BB_AV_SET (cur_bb
));
2989 BB_AV_SET (cur_bb
) = need_copy_p
? av_set_copy (av
) : av
;
2990 BB_AV_LEVEL (cur_bb
) = global_level
;
2993 if (sched_verbose
>= 6)
2995 sel_print ("Computed av set for insn %d: ", INSN_UID (first_insn
));
3004 /* Compute av set before INSN.
3005 INSN - the current operation (actual rtx INSN)
3006 P - the current path, which is list of insns visited so far
3007 WS - software lookahead window size.
3008 UNIQUE_P - TRUE, if returned av_set will be changed, hence
3009 if we want to save computed av_set in s_i_d, we should make a copy of it.
3011 In the resulting set we will have only expressions that don't have delay
3012 stalls and nonsubstitutable dependences. */
3014 compute_av_set (insn_t insn
, ilist_t p
, int ws
, bool unique_p
)
3016 return compute_av_set_inside_bb (insn
, p
, ws
, unique_p
);
3019 /* Propagate a liveness set LV through INSN. */
3021 propagate_lv_set (regset lv
, insn_t insn
)
3023 gcc_assert (INSN_P (insn
));
3025 if (INSN_NOP_P (insn
))
3028 df_simulate_one_insn_backwards (BLOCK_FOR_INSN (insn
), insn
, lv
);
3031 /* Return livness set at the end of BB. */
3033 compute_live_after_bb (basic_block bb
)
3037 regset lv
= get_clear_regset_from_pool ();
3039 gcc_assert (!ignore_first
);
3041 FOR_EACH_EDGE (e
, ei
, bb
->succs
)
3042 if (sel_bb_empty_p (e
->dest
))
3044 if (! BB_LV_SET_VALID_P (e
->dest
))
3047 gcc_assert (BB_LV_SET (e
->dest
) == NULL
);
3048 BB_LV_SET (e
->dest
) = compute_live_after_bb (e
->dest
);
3049 BB_LV_SET_VALID_P (e
->dest
) = true;
3051 IOR_REG_SET (lv
, BB_LV_SET (e
->dest
));
3054 IOR_REG_SET (lv
, compute_live (sel_bb_head (e
->dest
)));
3059 /* Compute the set of all live registers at the point before INSN and save
3060 it at INSN if INSN is bb header. */
3062 compute_live (insn_t insn
)
3064 basic_block bb
= BLOCK_FOR_INSN (insn
);
3068 /* Return the valid set if we're already on it. */
3073 if (sel_bb_head_p (insn
) && BB_LV_SET_VALID_P (bb
))
3074 src
= BB_LV_SET (bb
);
3077 gcc_assert (in_current_region_p (bb
));
3078 if (INSN_LIVE_VALID_P (insn
))
3079 src
= INSN_LIVE (insn
);
3084 lv
= get_regset_from_pool ();
3085 COPY_REG_SET (lv
, src
);
3087 if (sel_bb_head_p (insn
) && ! BB_LV_SET_VALID_P (bb
))
3089 COPY_REG_SET (BB_LV_SET (bb
), lv
);
3090 BB_LV_SET_VALID_P (bb
) = true;
3093 return_regset_to_pool (lv
);
3098 /* We've skipped the wrong lv_set. Don't skip the right one. */
3099 ignore_first
= false;
3100 gcc_assert (in_current_region_p (bb
));
3102 /* Find a valid LV set in this block or below, if needed.
3103 Start searching from the next insn: either ignore_first is true, or
3104 INSN doesn't have a correct live set. */
3105 temp
= NEXT_INSN (insn
);
3106 final
= NEXT_INSN (BB_END (bb
));
3107 while (temp
!= final
&& ! INSN_LIVE_VALID_P (temp
))
3108 temp
= NEXT_INSN (temp
);
3111 lv
= compute_live_after_bb (bb
);
3112 temp
= PREV_INSN (temp
);
3116 lv
= get_regset_from_pool ();
3117 COPY_REG_SET (lv
, INSN_LIVE (temp
));
3120 /* Put correct lv sets on the insns which have bad sets. */
3121 final
= PREV_INSN (insn
);
3122 while (temp
!= final
)
3124 propagate_lv_set (lv
, temp
);
3125 COPY_REG_SET (INSN_LIVE (temp
), lv
);
3126 INSN_LIVE_VALID_P (temp
) = true;
3127 temp
= PREV_INSN (temp
);
3130 /* Also put it in a BB. */
3131 if (sel_bb_head_p (insn
))
3133 basic_block bb
= BLOCK_FOR_INSN (insn
);
3135 COPY_REG_SET (BB_LV_SET (bb
), lv
);
3136 BB_LV_SET_VALID_P (bb
) = true;
3139 /* We return LV to the pool, but will not clear it there. Thus we can
3140 legimatelly use LV till the next use of regset_pool_get (). */
3141 return_regset_to_pool (lv
);
3145 /* Update liveness sets for INSN. */
3147 update_liveness_on_insn (rtx insn
)
3149 ignore_first
= true;
3150 compute_live (insn
);
3153 /* Compute liveness below INSN and write it into REGS. */
3155 compute_live_below_insn (rtx insn
, regset regs
)
3160 FOR_EACH_SUCC_1 (succ
, si
, insn
, SUCCS_ALL
)
3161 IOR_REG_SET (regs
, compute_live (succ
));
3164 /* Update the data gathered in av and lv sets starting from INSN. */
3166 update_data_sets (rtx insn
)
3168 update_liveness_on_insn (insn
);
3169 if (sel_bb_head_p (insn
))
3171 gcc_assert (AV_LEVEL (insn
) != 0);
3172 BB_AV_LEVEL (BLOCK_FOR_INSN (insn
)) = -1;
3173 compute_av_set (insn
, NULL
, 0, 0);
3178 /* Helper for move_op () and find_used_regs ().
3179 Return speculation type for which a check should be created on the place
3180 of INSN. EXPR is one of the original ops we are searching for. */
3182 get_spec_check_type_for_insn (insn_t insn
, expr_t expr
)
3185 ds_t already_checked_ds
= EXPR_SPEC_DONE_DS (INSN_EXPR (insn
));
3187 to_check_ds
= EXPR_SPEC_TO_CHECK_DS (expr
);
3189 if (targetm
.sched
.get_insn_checked_ds
)
3190 already_checked_ds
|= targetm
.sched
.get_insn_checked_ds (insn
);
3192 if (spec_info
!= NULL
3193 && (spec_info
->flags
& SEL_SCHED_SPEC_DONT_CHECK_CONTROL
))
3194 already_checked_ds
|= BEGIN_CONTROL
;
3196 already_checked_ds
= ds_get_speculation_types (already_checked_ds
);
3198 to_check_ds
&= ~already_checked_ds
;
3203 /* Find the set of registers that are unavailable for storing expres
3204 while moving ORIG_OPS up on the path starting from INSN due to
3205 liveness (USED_REGS) or hardware restrictions (REG_RENAME_P).
3207 All the original operations found during the traversal are saved in the
3208 ORIGINAL_INSNS list.
3210 REG_RENAME_P denotes the set of hardware registers that
3211 can not be used with renaming due to the register class restrictions,
3212 mode restrictions and other (the register we'll choose should be
3213 compatible class with the original uses, shouldn't be in call_used_regs,
3214 should be HARD_REGNO_RENAME_OK etc).
3216 Returns TRUE if we've found all original insns, FALSE otherwise.
3218 This function utilizes code_motion_path_driver (formerly find_used_regs_1)
3219 to traverse the code motion paths. This helper function finds registers
3220 that are not available for storing expres while moving ORIG_OPS up on the
3221 path starting from INSN. A register considered as used on the moving path,
3222 if one of the following conditions is not satisfied:
3224 (1) a register not set or read on any path from xi to an instance of
3225 the original operation,
3226 (2) not among the live registers of the point immediately following the
3227 first original operation on a given downward path, except for the
3228 original target register of the operation,
3229 (3) not live on the other path of any conditional branch that is passed
3230 by the operation, in case original operations are not present on
3231 both paths of the conditional branch.
3233 All the original operations found during the traversal are saved in the
3234 ORIGINAL_INSNS list.
3236 REG_RENAME_P->CROSSES_CALL is true, if there is a call insn on the path
3237 from INSN to original insn. In this case CALL_USED_REG_SET will be added
3238 to unavailable hard regs at the point original operation is found. */
3241 find_used_regs (insn_t insn
, av_set_t orig_ops
, regset used_regs
,
3242 struct reg_rename
*reg_rename_p
, def_list_t
*original_insns
)
3244 def_list_iterator i
;
3247 bool needs_spec_check_p
= false;
3249 av_set_iterator expr_iter
;
3250 struct fur_static_params sparams
;
3251 struct cmpd_local_params lparams
;
3253 /* We haven't visited any blocks yet. */
3254 bitmap_clear (code_motion_visited_blocks
);
3256 /* Init parameters for code_motion_path_driver. */
3257 sparams
.crosses_call
= false;
3258 sparams
.original_insns
= original_insns
;
3259 sparams
.used_regs
= used_regs
;
3261 /* Set the appropriate hooks and data. */
3262 code_motion_path_driver_info
= &fur_hooks
;
3264 res
= code_motion_path_driver (insn
, orig_ops
, NULL
, &lparams
, &sparams
);
3266 reg_rename_p
->crosses_call
|= sparams
.crosses_call
;
3268 gcc_assert (res
== 1);
3269 gcc_assert (original_insns
&& *original_insns
);
3271 /* ??? We calculate whether an expression needs a check when computing
3272 av sets. This information is not as precise as it could be due to
3273 merging this bit in merge_expr. We can do better in find_used_regs,
3274 but we want to avoid multiple traversals of the same code motion
3276 FOR_EACH_EXPR (expr
, expr_iter
, orig_ops
)
3277 needs_spec_check_p
|= EXPR_NEEDS_SPEC_CHECK_P (expr
);
3279 /* Mark hardware regs in REG_RENAME_P that are not suitable
3280 for renaming expr in INSN due to hardware restrictions (register class,
3281 modes compatibility etc). */
3282 FOR_EACH_DEF (def
, i
, *original_insns
)
3284 vinsn_t vinsn
= INSN_VINSN (def
->orig_insn
);
3286 if (VINSN_SEPARABLE_P (vinsn
))
3287 mark_unavailable_hard_regs (def
, reg_rename_p
, used_regs
);
3289 /* Do not allow clobbering of ld.[sa] address in case some of the
3290 original operations need a check. */
3291 if (needs_spec_check_p
)
3292 IOR_REG_SET (used_regs
, VINSN_REG_USES (vinsn
));
3299 /* Functions to choose the best insn from available ones. */
3301 /* Adjusts the priority for EXPR using the backend *_adjust_priority hook. */
3303 sel_target_adjust_priority (expr_t expr
)
3305 int priority
= EXPR_PRIORITY (expr
);
3308 if (targetm
.sched
.adjust_priority
)
3309 new_priority
= targetm
.sched
.adjust_priority (EXPR_INSN_RTX (expr
), priority
);
3311 new_priority
= priority
;
3313 /* If the priority has changed, adjust EXPR_PRIORITY_ADJ accordingly. */
3314 EXPR_PRIORITY_ADJ (expr
) = new_priority
- EXPR_PRIORITY (expr
);
3316 gcc_assert (EXPR_PRIORITY_ADJ (expr
) >= 0);
3318 if (sched_verbose
>= 4)
3319 sel_print ("sel_target_adjust_priority: insn %d, %d+%d = %d.\n",
3320 INSN_UID (EXPR_INSN_RTX (expr
)), EXPR_PRIORITY (expr
),
3321 EXPR_PRIORITY_ADJ (expr
), new_priority
);
3323 return new_priority
;
3326 /* Rank two available exprs for schedule. Never return 0 here. */
3328 sel_rank_for_schedule (const void *x
, const void *y
)
3330 expr_t tmp
= *(const expr_t
*) y
;
3331 expr_t tmp2
= *(const expr_t
*) x
;
3332 insn_t tmp_insn
, tmp2_insn
;
3333 vinsn_t tmp_vinsn
, tmp2_vinsn
;
3336 tmp_vinsn
= EXPR_VINSN (tmp
);
3337 tmp2_vinsn
= EXPR_VINSN (tmp2
);
3338 tmp_insn
= EXPR_INSN_RTX (tmp
);
3339 tmp2_insn
= EXPR_INSN_RTX (tmp2
);
3341 /* Schedule debug insns as early as possible. */
3342 if (DEBUG_INSN_P (tmp_insn
) && !DEBUG_INSN_P (tmp2_insn
))
3344 else if (DEBUG_INSN_P (tmp2_insn
))
3347 /* Prefer SCHED_GROUP_P insns to any others. */
3348 if (SCHED_GROUP_P (tmp_insn
) != SCHED_GROUP_P (tmp2_insn
))
3350 if (VINSN_UNIQUE_P (tmp_vinsn
) && VINSN_UNIQUE_P (tmp2_vinsn
))
3351 return SCHED_GROUP_P (tmp2_insn
) ? 1 : -1;
3353 /* Now uniqueness means SCHED_GROUP_P is set, because schedule groups
3354 cannot be cloned. */
3355 if (VINSN_UNIQUE_P (tmp2_vinsn
))
3360 /* Discourage scheduling of speculative checks. */
3361 val
= (sel_insn_is_speculation_check (tmp_insn
)
3362 - sel_insn_is_speculation_check (tmp2_insn
));
3366 /* Prefer not scheduled insn over scheduled one. */
3367 if (EXPR_SCHED_TIMES (tmp
) > 0 || EXPR_SCHED_TIMES (tmp2
) > 0)
3369 val
= EXPR_SCHED_TIMES (tmp
) - EXPR_SCHED_TIMES (tmp2
);
3374 /* Prefer jump over non-jump instruction. */
3375 if (control_flow_insn_p (tmp_insn
) && !control_flow_insn_p (tmp2_insn
))
3377 else if (control_flow_insn_p (tmp2_insn
) && !control_flow_insn_p (tmp_insn
))
3380 /* Prefer an expr with greater priority. */
3381 if (EXPR_USEFULNESS (tmp
) != 0 && EXPR_USEFULNESS (tmp2
) != 0)
3383 int p2
= EXPR_PRIORITY (tmp2
) + EXPR_PRIORITY_ADJ (tmp2
),
3384 p1
= EXPR_PRIORITY (tmp
) + EXPR_PRIORITY_ADJ (tmp
);
3386 val
= p2
* EXPR_USEFULNESS (tmp2
) - p1
* EXPR_USEFULNESS (tmp
);
3389 val
= EXPR_PRIORITY (tmp2
) - EXPR_PRIORITY (tmp
)
3390 + EXPR_PRIORITY_ADJ (tmp2
) - EXPR_PRIORITY_ADJ (tmp
);
3394 if (spec_info
!= NULL
&& spec_info
->mask
!= 0)
3395 /* This code was taken from haifa-sched.c: rank_for_schedule (). */
3401 ds1
= EXPR_SPEC_DONE_DS (tmp
);
3403 dw1
= ds_weak (ds1
);
3407 ds2
= EXPR_SPEC_DONE_DS (tmp2
);
3409 dw2
= ds_weak (ds2
);
3414 if (dw
> (NO_DEP_WEAK
/ 8) || dw
< -(NO_DEP_WEAK
/ 8))
3418 /* Prefer an old insn to a bookkeeping insn. */
3419 if (INSN_UID (tmp_insn
) < first_emitted_uid
3420 && INSN_UID (tmp2_insn
) >= first_emitted_uid
)
3422 if (INSN_UID (tmp_insn
) >= first_emitted_uid
3423 && INSN_UID (tmp2_insn
) < first_emitted_uid
)
3426 /* Prefer an insn with smaller UID, as a last resort.
3427 We can't safely use INSN_LUID as it is defined only for those insns
3428 that are in the stream. */
3429 return INSN_UID (tmp_insn
) - INSN_UID (tmp2_insn
);
3432 /* Filter out expressions from av set pointed to by AV_PTR
3433 that are pipelined too many times. */
3435 process_pipelined_exprs (av_set_t
*av_ptr
)
3440 /* Don't pipeline already pipelined code as that would increase
3441 number of unnecessary register moves. */
3442 FOR_EACH_EXPR_1 (expr
, si
, av_ptr
)
3444 if (EXPR_SCHED_TIMES (expr
)
3445 >= PARAM_VALUE (PARAM_SELSCHED_MAX_SCHED_TIMES
))
3446 av_set_iter_remove (&si
);
3450 /* Filter speculative insns from AV_PTR if we don't want them. */
3452 process_spec_exprs (av_set_t
*av_ptr
)
3454 bool try_data_p
= true;
3455 bool try_control_p
= true;
3459 if (spec_info
== NULL
)
3462 /* Scan *AV_PTR to find out if we want to consider speculative
3463 instructions for scheduling. */
3464 FOR_EACH_EXPR_1 (expr
, si
, av_ptr
)
3468 ds
= EXPR_SPEC_DONE_DS (expr
);
3470 /* The probability of a success is too low - don't speculate. */
3471 if ((ds
& SPECULATIVE
)
3472 && (ds_weak (ds
) < spec_info
->data_weakness_cutoff
3473 || EXPR_USEFULNESS (expr
) < spec_info
->control_weakness_cutoff
3474 || (pipelining_p
&& false
3476 && (ds
& CONTROL_SPEC
))))
3478 av_set_iter_remove (&si
);
3482 if ((spec_info
->flags
& PREFER_NON_DATA_SPEC
)
3483 && !(ds
& BEGIN_DATA
))
3486 if ((spec_info
->flags
& PREFER_NON_CONTROL_SPEC
)
3487 && !(ds
& BEGIN_CONTROL
))
3488 try_control_p
= false;
3491 FOR_EACH_EXPR_1 (expr
, si
, av_ptr
)
3495 ds
= EXPR_SPEC_DONE_DS (expr
);
3497 if (ds
& SPECULATIVE
)
3499 if ((ds
& BEGIN_DATA
) && !try_data_p
)
3500 /* We don't want any data speculative instructions right
3502 av_set_iter_remove (&si
);
3504 if ((ds
& BEGIN_CONTROL
) && !try_control_p
)
3505 /* We don't want any control speculative instructions right
3507 av_set_iter_remove (&si
);
3512 /* Search for any use-like insns in AV_PTR and decide on scheduling
3513 them. Return one when found, and NULL otherwise.
3514 Note that we check here whether a USE could be scheduled to avoid
3515 an infinite loop later. */
3517 process_use_exprs (av_set_t
*av_ptr
)
3521 bool uses_present_p
= false;
3522 bool try_uses_p
= true;
3524 FOR_EACH_EXPR_1 (expr
, si
, av_ptr
)
3526 /* This will also initialize INSN_CODE for later use. */
3527 if (recog_memoized (EXPR_INSN_RTX (expr
)) < 0)
3529 /* If we have a USE in *AV_PTR that was not scheduled yet,
3530 do so because it will do good only. */
3531 if (EXPR_SCHED_TIMES (expr
) <= 0)
3533 if (EXPR_TARGET_AVAILABLE (expr
) == 1)
3536 av_set_iter_remove (&si
);
3540 gcc_assert (pipelining_p
);
3542 uses_present_p
= true;
3551 /* If we don't want to schedule any USEs right now and we have some
3552 in *AV_PTR, remove them, else just return the first one found. */
3555 FOR_EACH_EXPR_1 (expr
, si
, av_ptr
)
3556 if (INSN_CODE (EXPR_INSN_RTX (expr
)) < 0)
3557 av_set_iter_remove (&si
);
3561 FOR_EACH_EXPR_1 (expr
, si
, av_ptr
)
3563 gcc_assert (INSN_CODE (EXPR_INSN_RTX (expr
)) < 0);
3565 if (EXPR_TARGET_AVAILABLE (expr
) == 1)
3568 av_set_iter_remove (&si
);
3576 /* Lookup EXPR in VINSN_VEC and return TRUE if found. */
3578 vinsn_vec_has_expr_p (vinsn_vec_t vinsn_vec
, expr_t expr
)
3583 FOR_EACH_VEC_ELT (vinsn_t
, vinsn_vec
, n
, vinsn
)
3584 if (VINSN_SEPARABLE_P (vinsn
))
3586 if (vinsn_equal_p (vinsn
, EXPR_VINSN (expr
)))
3591 /* For non-separable instructions, the blocking insn can have
3592 another pattern due to substitution, and we can't choose
3593 different register as in the above case. Check all registers
3594 being written instead. */
3595 if (bitmap_intersect_p (VINSN_REG_SETS (vinsn
),
3596 VINSN_REG_SETS (EXPR_VINSN (expr
))))
3603 #ifdef ENABLE_CHECKING
3604 /* Return true if either of expressions from ORIG_OPS can be blocked
3605 by previously created bookkeeping code. STATIC_PARAMS points to static
3606 parameters of move_op. */
3608 av_set_could_be_blocked_by_bookkeeping_p (av_set_t orig_ops
, void *static_params
)
3611 av_set_iterator iter
;
3612 moveop_static_params_p sparams
;
3614 /* This checks that expressions in ORIG_OPS are not blocked by bookkeeping
3615 created while scheduling on another fence. */
3616 FOR_EACH_EXPR (expr
, iter
, orig_ops
)
3617 if (vinsn_vec_has_expr_p (vec_bookkeeping_blocked_vinsns
, expr
))
3620 gcc_assert (code_motion_path_driver_info
== &move_op_hooks
);
3621 sparams
= (moveop_static_params_p
) static_params
;
3623 /* Expressions can be also blocked by bookkeeping created during current
3625 if (bitmap_bit_p (current_copies
, INSN_UID (sparams
->failed_insn
)))
3626 FOR_EACH_EXPR (expr
, iter
, orig_ops
)
3627 if (moveup_expr_cached (expr
, sparams
->failed_insn
, false) != MOVEUP_EXPR_NULL
)
3630 /* Expressions in ORIG_OPS may have wrong destination register due to
3631 renaming. Check with the right register instead. */
3632 if (sparams
->dest
&& REG_P (sparams
->dest
))
3634 unsigned regno
= REGNO (sparams
->dest
);
3635 vinsn_t failed_vinsn
= INSN_VINSN (sparams
->failed_insn
);
3637 if (bitmap_bit_p (VINSN_REG_SETS (failed_vinsn
), regno
)
3638 || bitmap_bit_p (VINSN_REG_USES (failed_vinsn
), regno
)
3639 || bitmap_bit_p (VINSN_REG_CLOBBERS (failed_vinsn
), regno
))
3647 /* Clear VINSN_VEC and detach vinsns. */
3649 vinsn_vec_clear (vinsn_vec_t
*vinsn_vec
)
3651 unsigned len
= VEC_length (vinsn_t
, *vinsn_vec
);
3657 FOR_EACH_VEC_ELT (vinsn_t
, *vinsn_vec
, n
, vinsn
)
3658 vinsn_detach (vinsn
);
3659 VEC_block_remove (vinsn_t
, *vinsn_vec
, 0, len
);
3663 /* Add the vinsn of EXPR to the VINSN_VEC. */
3665 vinsn_vec_add (vinsn_vec_t
*vinsn_vec
, expr_t expr
)
3667 vinsn_attach (EXPR_VINSN (expr
));
3668 VEC_safe_push (vinsn_t
, heap
, *vinsn_vec
, EXPR_VINSN (expr
));
3671 /* Free the vector representing blocked expressions. */
3673 vinsn_vec_free (vinsn_vec_t
*vinsn_vec
)
3676 VEC_free (vinsn_t
, heap
, *vinsn_vec
);
3679 /* Increase EXPR_PRIORITY_ADJ for INSN by AMOUNT. */
3681 void sel_add_to_insn_priority (rtx insn
, int amount
)
3683 EXPR_PRIORITY_ADJ (INSN_EXPR (insn
)) += amount
;
3685 if (sched_verbose
>= 2)
3686 sel_print ("sel_add_to_insn_priority: insn %d, by %d (now %d+%d).\n",
3687 INSN_UID (insn
), amount
, EXPR_PRIORITY (INSN_EXPR (insn
)),
3688 EXPR_PRIORITY_ADJ (INSN_EXPR (insn
)));
3691 /* Turn AV into a vector, filter inappropriate insns and sort it. Return
3692 true if there is something to schedule. BNDS and FENCE are current
3693 boundaries and fence, respectively. If we need to stall for some cycles
3694 before an expr from AV would become available, write this number to
3697 fill_vec_av_set (av_set_t av
, blist_t bnds
, fence_t fence
,
3702 int sched_next_worked
= 0, stalled
, n
;
3703 static int av_max_prio
, est_ticks_till_branch
;
3704 int min_need_stall
= -1;
3705 deps_t dc
= BND_DC (BLIST_BND (bnds
));
3707 /* Bail out early when the ready list contained only USEs/CLOBBERs that are
3708 already scheduled. */
3712 /* Empty vector from the previous stuff. */
3713 if (VEC_length (expr_t
, vec_av_set
) > 0)
3714 VEC_block_remove (expr_t
, vec_av_set
, 0, VEC_length (expr_t
, vec_av_set
));
3716 /* Turn the set into a vector for sorting and call sel_target_adjust_priority
3718 gcc_assert (VEC_empty (expr_t
, vec_av_set
));
3719 FOR_EACH_EXPR (expr
, si
, av
)
3721 VEC_safe_push (expr_t
, heap
, vec_av_set
, expr
);
3723 gcc_assert (EXPR_PRIORITY_ADJ (expr
) == 0 || *pneed_stall
);
3725 /* Adjust priority using target backend hook. */
3726 sel_target_adjust_priority (expr
);
3729 /* Sort the vector. */
3730 VEC_qsort (expr_t
, vec_av_set
, sel_rank_for_schedule
);
3732 /* We record maximal priority of insns in av set for current instruction
3734 if (FENCE_STARTS_CYCLE_P (fence
))
3735 av_max_prio
= est_ticks_till_branch
= INT_MIN
;
3737 /* Filter out inappropriate expressions. Loop's direction is reversed to
3738 visit "best" instructions first. We assume that VEC_unordered_remove
3739 moves last element in place of one being deleted. */
3740 for (n
= VEC_length (expr_t
, vec_av_set
) - 1, stalled
= 0; n
>= 0; n
--)
3742 expr_t expr
= VEC_index (expr_t
, vec_av_set
, n
);
3743 insn_t insn
= EXPR_INSN_RTX (expr
);
3744 signed char target_available
;
3745 bool is_orig_reg_p
= true;
3746 int need_cycles
, new_prio
;
3748 /* Don't allow any insns other than from SCHED_GROUP if we have one. */
3749 if (FENCE_SCHED_NEXT (fence
) && insn
!= FENCE_SCHED_NEXT (fence
))
3751 VEC_unordered_remove (expr_t
, vec_av_set
, n
);
3755 /* Set number of sched_next insns (just in case there
3756 could be several). */
3757 if (FENCE_SCHED_NEXT (fence
))
3758 sched_next_worked
++;
3760 /* Check all liveness requirements and try renaming.
3761 FIXME: try to minimize calls to this. */
3762 target_available
= EXPR_TARGET_AVAILABLE (expr
);
3764 /* If insn was already scheduled on the current fence,
3765 set TARGET_AVAILABLE to -1 no matter what expr's attribute says. */
3766 if (vinsn_vec_has_expr_p (vec_target_unavailable_vinsns
, expr
))
3767 target_available
= -1;
3769 /* If the availability of the EXPR is invalidated by the insertion of
3770 bookkeeping earlier, make sure that we won't choose this expr for
3771 scheduling if it's not separable, and if it is separable, then
3772 we have to recompute the set of available registers for it. */
3773 if (vinsn_vec_has_expr_p (vec_bookkeeping_blocked_vinsns
, expr
))
3775 VEC_unordered_remove (expr_t
, vec_av_set
, n
);
3776 if (sched_verbose
>= 4)
3777 sel_print ("Expr %d is blocked by bookkeeping inserted earlier\n",
3782 if (target_available
== true)
3784 /* Do nothing -- we can use an existing register. */
3785 is_orig_reg_p
= EXPR_SEPARABLE_P (expr
);
3787 else if (/* Non-separable instruction will never
3788 get another register. */
3789 (target_available
== false
3790 && !EXPR_SEPARABLE_P (expr
))
3791 /* Don't try to find a register for low-priority expression. */
3792 || (int) VEC_length (expr_t
, vec_av_set
) - 1 - n
>= max_insns_to_rename
3793 /* ??? FIXME: Don't try to rename data speculation. */
3794 || (EXPR_SPEC_DONE_DS (expr
) & BEGIN_DATA
)
3795 || ! find_best_reg_for_expr (expr
, bnds
, &is_orig_reg_p
))
3797 VEC_unordered_remove (expr_t
, vec_av_set
, n
);
3798 if (sched_verbose
>= 4)
3799 sel_print ("Expr %d has no suitable target register\n",
3804 /* Filter expressions that need to be renamed or speculated when
3805 pipelining, because compensating register copies or speculation
3806 checks are likely to be placed near the beginning of the loop,
3808 if (pipelining_p
&& EXPR_ORIG_SCHED_CYCLE (expr
) > 0
3809 && (!is_orig_reg_p
|| EXPR_SPEC_DONE_DS (expr
) != 0))
3811 /* Estimation of number of cycles until loop branch for
3812 renaming/speculation to be successful. */
3813 int need_n_ticks_till_branch
= sel_vinsn_cost (EXPR_VINSN (expr
));
3815 if ((int) current_loop_nest
->ninsns
< 9)
3817 VEC_unordered_remove (expr_t
, vec_av_set
, n
);
3818 if (sched_verbose
>= 4)
3819 sel_print ("Pipelining expr %d will likely cause stall\n",
3824 if ((int) current_loop_nest
->ninsns
- num_insns_scheduled
3825 < need_n_ticks_till_branch
* issue_rate
/ 2
3826 && est_ticks_till_branch
< need_n_ticks_till_branch
)
3828 VEC_unordered_remove (expr_t
, vec_av_set
, n
);
3829 if (sched_verbose
>= 4)
3830 sel_print ("Pipelining expr %d will likely cause stall\n",
3836 /* We want to schedule speculation checks as late as possible. Discard
3837 them from av set if there are instructions with higher priority. */
3838 if (sel_insn_is_speculation_check (insn
)
3839 && EXPR_PRIORITY (expr
) < av_max_prio
)
3842 min_need_stall
= min_need_stall
< 0 ? 1 : MIN (min_need_stall
, 1);
3843 VEC_unordered_remove (expr_t
, vec_av_set
, n
);
3844 if (sched_verbose
>= 4)
3845 sel_print ("Delaying speculation check %d until its first use\n",
3850 /* Ignore EXPRs available from pipelining to update AV_MAX_PRIO. */
3851 if (EXPR_ORIG_SCHED_CYCLE (expr
) <= 0)
3852 av_max_prio
= MAX (av_max_prio
, EXPR_PRIORITY (expr
));
3854 /* Don't allow any insns whose data is not yet ready.
3855 Check first whether we've already tried them and failed. */
3856 if (INSN_UID (insn
) < FENCE_READY_TICKS_SIZE (fence
))
3858 need_cycles
= (FENCE_READY_TICKS (fence
)[INSN_UID (insn
)]
3859 - FENCE_CYCLE (fence
));
3860 if (EXPR_ORIG_SCHED_CYCLE (expr
) <= 0)
3861 est_ticks_till_branch
= MAX (est_ticks_till_branch
,
3862 EXPR_PRIORITY (expr
) + need_cycles
);
3864 if (need_cycles
> 0)
3867 min_need_stall
= (min_need_stall
< 0
3869 : MIN (min_need_stall
, need_cycles
));
3870 VEC_unordered_remove (expr_t
, vec_av_set
, n
);
3872 if (sched_verbose
>= 4)
3873 sel_print ("Expr %d is not ready until cycle %d (cached)\n",
3875 FENCE_READY_TICKS (fence
)[INSN_UID (insn
)]);
3880 /* Now resort to dependence analysis to find whether EXPR might be
3881 stalled due to dependencies from FENCE's context. */
3882 need_cycles
= tick_check_p (expr
, dc
, fence
);
3883 new_prio
= EXPR_PRIORITY (expr
) + EXPR_PRIORITY_ADJ (expr
) + need_cycles
;
3885 if (EXPR_ORIG_SCHED_CYCLE (expr
) <= 0)
3886 est_ticks_till_branch
= MAX (est_ticks_till_branch
,
3889 if (need_cycles
> 0)
3891 if (INSN_UID (insn
) >= FENCE_READY_TICKS_SIZE (fence
))
3893 int new_size
= INSN_UID (insn
) * 3 / 2;
3895 FENCE_READY_TICKS (fence
)
3896 = (int *) xrecalloc (FENCE_READY_TICKS (fence
),
3897 new_size
, FENCE_READY_TICKS_SIZE (fence
),
3900 FENCE_READY_TICKS (fence
)[INSN_UID (insn
)]
3901 = FENCE_CYCLE (fence
) + need_cycles
;
3904 min_need_stall
= (min_need_stall
< 0
3906 : MIN (min_need_stall
, need_cycles
));
3908 VEC_unordered_remove (expr_t
, vec_av_set
, n
);
3910 if (sched_verbose
>= 4)
3911 sel_print ("Expr %d is not ready yet until cycle %d\n",
3913 FENCE_READY_TICKS (fence
)[INSN_UID (insn
)]);
3917 if (sched_verbose
>= 4)
3918 sel_print ("Expr %d is ok\n", INSN_UID (insn
));
3922 /* Clear SCHED_NEXT. */
3923 if (FENCE_SCHED_NEXT (fence
))
3925 gcc_assert (sched_next_worked
== 1);
3926 FENCE_SCHED_NEXT (fence
) = NULL_RTX
;
3929 /* No need to stall if this variable was not initialized. */
3930 if (min_need_stall
< 0)
3933 if (VEC_empty (expr_t
, vec_av_set
))
3935 /* We need to set *pneed_stall here, because later we skip this code
3936 when ready list is empty. */
3937 *pneed_stall
= min_need_stall
;
3941 gcc_assert (min_need_stall
== 0);
3943 /* Sort the vector. */
3944 VEC_qsort (expr_t
, vec_av_set
, sel_rank_for_schedule
);
3946 if (sched_verbose
>= 4)
3948 sel_print ("Total ready exprs: %d, stalled: %d\n",
3949 VEC_length (expr_t
, vec_av_set
), stalled
);
3950 sel_print ("Sorted av set (%d): ", VEC_length (expr_t
, vec_av_set
));
3951 FOR_EACH_VEC_ELT (expr_t
, vec_av_set
, n
, expr
)
3960 /* Convert a vectored and sorted av set to the ready list that
3961 the rest of the backend wants to see. */
3963 convert_vec_av_set_to_ready (void)
3968 /* Allocate and fill the ready list from the sorted vector. */
3969 ready
.n_ready
= VEC_length (expr_t
, vec_av_set
);
3970 ready
.first
= ready
.n_ready
- 1;
3972 gcc_assert (ready
.n_ready
> 0);
3974 if (ready
.n_ready
> max_issue_size
)
3976 max_issue_size
= ready
.n_ready
;
3977 sched_extend_ready_list (ready
.n_ready
);
3980 FOR_EACH_VEC_ELT (expr_t
, vec_av_set
, n
, expr
)
3982 vinsn_t vi
= EXPR_VINSN (expr
);
3983 insn_t insn
= VINSN_INSN_RTX (vi
);
3986 ready
.vec
[n
] = insn
;
3990 /* Initialize ready list from *AV_PTR for the max_issue () call.
3991 If any unrecognizable insn found in *AV_PTR, return it (and skip
3992 max_issue). BND and FENCE are current boundary and fence,
3993 respectively. If we need to stall for some cycles before an expr
3994 from *AV_PTR would become available, write this number to *PNEED_STALL. */
3996 fill_ready_list (av_set_t
*av_ptr
, blist_t bnds
, fence_t fence
,
4001 /* We do not support multiple boundaries per fence. */
4002 gcc_assert (BLIST_NEXT (bnds
) == NULL
);
4004 /* Process expressions required special handling, i.e. pipelined,
4005 speculative and recog() < 0 expressions first. */
4006 process_pipelined_exprs (av_ptr
);
4007 process_spec_exprs (av_ptr
);
4009 /* A USE could be scheduled immediately. */
4010 expr
= process_use_exprs (av_ptr
);
4017 /* Turn the av set to a vector for sorting. */
4018 if (! fill_vec_av_set (*av_ptr
, bnds
, fence
, pneed_stall
))
4024 /* Build the final ready list. */
4025 convert_vec_av_set_to_ready ();
4029 /* Wrapper for dfa_new_cycle (). Returns TRUE if cycle was advanced. */
4031 sel_dfa_new_cycle (insn_t insn
, fence_t fence
)
4033 int last_scheduled_cycle
= FENCE_LAST_SCHEDULED_INSN (fence
)
4034 ? INSN_SCHED_CYCLE (FENCE_LAST_SCHEDULED_INSN (fence
))
4035 : FENCE_CYCLE (fence
) - 1;
4039 if (!targetm
.sched
.dfa_new_cycle
)
4042 memcpy (curr_state
, FENCE_STATE (fence
), dfa_state_size
);
4044 while (!sort_p
&& targetm
.sched
.dfa_new_cycle (sched_dump
, sched_verbose
,
4045 insn
, last_scheduled_cycle
,
4046 FENCE_CYCLE (fence
), &sort_p
))
4048 memcpy (FENCE_STATE (fence
), curr_state
, dfa_state_size
);
4049 advance_one_cycle (fence
);
4050 memcpy (curr_state
, FENCE_STATE (fence
), dfa_state_size
);
4057 /* Invoke reorder* target hooks on the ready list. Return the number of insns
4058 we can issue. FENCE is the current fence. */
4060 invoke_reorder_hooks (fence_t fence
)
4063 bool ran_hook
= false;
4065 /* Call the reorder hook at the beginning of the cycle, and call
4066 the reorder2 hook in the middle of the cycle. */
4067 if (FENCE_ISSUED_INSNS (fence
) == 0)
4069 if (targetm
.sched
.reorder
4070 && !SCHED_GROUP_P (ready_element (&ready
, 0))
4071 && ready
.n_ready
> 1)
4073 /* Don't give reorder the most prioritized insn as it can break
4079 = targetm
.sched
.reorder (sched_dump
, sched_verbose
,
4080 ready_lastpos (&ready
),
4081 &ready
.n_ready
, FENCE_CYCLE (fence
));
4089 /* Initialize can_issue_more for variable_issue. */
4090 issue_more
= issue_rate
;
4092 else if (targetm
.sched
.reorder2
4093 && !SCHED_GROUP_P (ready_element (&ready
, 0)))
4095 if (ready
.n_ready
== 1)
4097 targetm
.sched
.reorder2 (sched_dump
, sched_verbose
,
4098 ready_lastpos (&ready
),
4099 &ready
.n_ready
, FENCE_CYCLE (fence
));
4106 targetm
.sched
.reorder2 (sched_dump
, sched_verbose
,
4108 ? ready_lastpos (&ready
) : NULL
,
4109 &ready
.n_ready
, FENCE_CYCLE (fence
));
4118 issue_more
= FENCE_ISSUE_MORE (fence
);
4120 /* Ensure that ready list and vec_av_set are in line with each other,
4121 i.e. vec_av_set[i] == ready_element (&ready, i). */
4122 if (issue_more
&& ran_hook
)
4125 rtx
*arr
= ready
.vec
;
4126 expr_t
*vec
= VEC_address (expr_t
, vec_av_set
);
4128 for (i
= 0, n
= ready
.n_ready
; i
< n
; i
++)
4129 if (EXPR_INSN_RTX (vec
[i
]) != arr
[i
])
4133 for (j
= i
; j
< n
; j
++)
4134 if (EXPR_INSN_RTX (vec
[j
]) == arr
[i
])
4147 /* Return an EXPR correponding to INDEX element of ready list, if
4148 FOLLOW_READY_ELEMENT is true (i.e., an expr of
4149 ready_element (&ready, INDEX) will be returned), and to INDEX element of
4150 ready.vec otherwise. */
4151 static inline expr_t
4152 find_expr_for_ready (int index
, bool follow_ready_element
)
4157 real_index
= follow_ready_element
? ready
.first
- index
: index
;
4159 expr
= VEC_index (expr_t
, vec_av_set
, real_index
);
4160 gcc_assert (ready
.vec
[real_index
] == EXPR_INSN_RTX (expr
));
4165 /* Calculate insns worth trying via lookahead_guard hook. Return a number
4166 of such insns found. */
4168 invoke_dfa_lookahead_guard (void)
4172 = targetm
.sched
.first_cycle_multipass_dfa_lookahead_guard
!= NULL
;
4174 if (sched_verbose
>= 2)
4175 sel_print ("ready after reorder: ");
4177 for (i
= 0, n
= 0; i
< ready
.n_ready
; i
++)
4183 /* In this loop insn is Ith element of the ready list given by
4184 ready_element, not Ith element of ready.vec. */
4185 insn
= ready_element (&ready
, i
);
4187 if (! have_hook
|| i
== 0)
4190 r
= !targetm
.sched
.first_cycle_multipass_dfa_lookahead_guard (insn
);
4192 gcc_assert (INSN_CODE (insn
) >= 0);
4194 /* Only insns with ready_try = 0 can get here
4195 from fill_ready_list. */
4196 gcc_assert (ready_try
[i
] == 0);
4201 expr
= find_expr_for_ready (i
, true);
4203 if (sched_verbose
>= 2)
4205 dump_vinsn (EXPR_VINSN (expr
));
4206 sel_print (":%d; ", ready_try
[i
]);
4210 if (sched_verbose
>= 2)
4215 /* Calculate the number of privileged insns and return it. */
4217 calculate_privileged_insns (void)
4219 expr_t cur_expr
, min_spec_expr
= NULL
;
4220 int privileged_n
= 0, i
;
4222 for (i
= 0; i
< ready
.n_ready
; i
++)
4227 if (! min_spec_expr
)
4228 min_spec_expr
= find_expr_for_ready (i
, true);
4230 cur_expr
= find_expr_for_ready (i
, true);
4232 if (EXPR_SPEC (cur_expr
) > EXPR_SPEC (min_spec_expr
))
4238 if (i
== ready
.n_ready
)
4241 if (sched_verbose
>= 2)
4242 sel_print ("privileged_n: %d insns with SPEC %d\n",
4243 privileged_n
, privileged_n
? EXPR_SPEC (min_spec_expr
) : -1);
4244 return privileged_n
;
4247 /* Call the rest of the hooks after the choice was made. Return
4248 the number of insns that still can be issued given that the current
4249 number is ISSUE_MORE. FENCE and BEST_INSN are the current fence
4250 and the insn chosen for scheduling, respectively. */
4252 invoke_aftermath_hooks (fence_t fence
, rtx best_insn
, int issue_more
)
4254 gcc_assert (INSN_P (best_insn
));
4256 /* First, call dfa_new_cycle, and then variable_issue, if available. */
4257 sel_dfa_new_cycle (best_insn
, fence
);
4259 if (targetm
.sched
.variable_issue
)
4261 memcpy (curr_state
, FENCE_STATE (fence
), dfa_state_size
);
4263 targetm
.sched
.variable_issue (sched_dump
, sched_verbose
, best_insn
,
4265 memcpy (FENCE_STATE (fence
), curr_state
, dfa_state_size
);
4267 else if (GET_CODE (PATTERN (best_insn
)) != USE
4268 && GET_CODE (PATTERN (best_insn
)) != CLOBBER
)
4274 /* Estimate the cost of issuing INSN on DFA state STATE. */
4276 estimate_insn_cost (rtx insn
, state_t state
)
4278 static state_t temp
= NULL
;
4282 temp
= xmalloc (dfa_state_size
);
4284 memcpy (temp
, state
, dfa_state_size
);
4285 cost
= state_transition (temp
, insn
);
4294 /* Return the cost of issuing EXPR on the FENCE as estimated by DFA.
4295 This function properly handles ASMs, USEs etc. */
4297 get_expr_cost (expr_t expr
, fence_t fence
)
4299 rtx insn
= EXPR_INSN_RTX (expr
);
4301 if (recog_memoized (insn
) < 0)
4303 if (!FENCE_STARTS_CYCLE_P (fence
)
4304 && INSN_ASM_P (insn
))
4305 /* This is asm insn which is tryed to be issued on the
4306 cycle not first. Issue it on the next cycle. */
4309 /* A USE insn, or something else we don't need to
4310 understand. We can't pass these directly to
4311 state_transition because it will trigger a
4312 fatal error for unrecognizable insns. */
4316 return estimate_insn_cost (insn
, FENCE_STATE (fence
));
4319 /* Find the best insn for scheduling, either via max_issue or just take
4320 the most prioritized available. */
4322 choose_best_insn (fence_t fence
, int privileged_n
, int *index
)
4326 if (dfa_lookahead
> 0)
4328 cycle_issued_insns
= FENCE_ISSUED_INSNS (fence
);
4329 /* TODO: pass equivalent of first_cycle_insn_p to max_issue (). */
4330 can_issue
= max_issue (&ready
, privileged_n
,
4331 FENCE_STATE (fence
), true, index
);
4332 if (sched_verbose
>= 2)
4333 sel_print ("max_issue: we can issue %d insns, already did %d insns\n",
4334 can_issue
, FENCE_ISSUED_INSNS (fence
));
4338 /* We can't use max_issue; just return the first available element. */
4341 for (i
= 0; i
< ready
.n_ready
; i
++)
4343 expr_t expr
= find_expr_for_ready (i
, true);
4345 if (get_expr_cost (expr
, fence
) < 1)
4347 can_issue
= can_issue_more
;
4350 if (sched_verbose
>= 2)
4351 sel_print ("using %dth insn from the ready list\n", i
+ 1);
4357 if (i
== ready
.n_ready
)
4367 /* Choose the best expr from *AV_VLIW_PTR and a suitable register for it.
4368 BNDS and FENCE are current boundaries and scheduling fence respectively.
4369 Return the expr found and NULL if nothing can be issued atm.
4370 Write to PNEED_STALL the number of cycles to stall if no expr was found. */
4372 find_best_expr (av_set_t
*av_vliw_ptr
, blist_t bnds
, fence_t fence
,
4377 /* Choose the best insn for scheduling via:
4378 1) sorting the ready list based on priority;
4379 2) calling the reorder hook;
4380 3) calling max_issue. */
4381 best
= fill_ready_list (av_vliw_ptr
, bnds
, fence
, pneed_stall
);
4382 if (best
== NULL
&& ready
.n_ready
> 0)
4384 int privileged_n
, index
;
4386 can_issue_more
= invoke_reorder_hooks (fence
);
4387 if (can_issue_more
> 0)
4389 /* Try choosing the best insn until we find one that is could be
4390 scheduled due to liveness restrictions on its destination register.
4391 In the future, we'd like to choose once and then just probe insns
4392 in the order of their priority. */
4393 invoke_dfa_lookahead_guard ();
4394 privileged_n
= calculate_privileged_insns ();
4395 can_issue_more
= choose_best_insn (fence
, privileged_n
, &index
);
4397 best
= find_expr_for_ready (index
, true);
4399 /* We had some available insns, so if we can't issue them,
4401 if (can_issue_more
== 0)
4410 can_issue_more
= invoke_aftermath_hooks (fence
, EXPR_INSN_RTX (best
),
4412 if (targetm
.sched
.variable_issue
4413 && can_issue_more
== 0)
4417 if (sched_verbose
>= 2)
4421 sel_print ("Best expression (vliw form): ");
4423 sel_print ("; cycle %d\n", FENCE_CYCLE (fence
));
4426 sel_print ("No best expr found!\n");
4433 /* Functions that implement the core of the scheduler. */
4436 /* Emit an instruction from EXPR with SEQNO and VINSN after
4439 emit_insn_from_expr_after (expr_t expr
, vinsn_t vinsn
, int seqno
,
4440 insn_t place_to_insert
)
4442 /* This assert fails when we have identical instructions
4443 one of which dominates the other. In this case move_op ()
4444 finds the first instruction and doesn't search for second one.
4445 The solution would be to compute av_set after the first found
4446 insn and, if insn present in that set, continue searching.
4447 For now we workaround this issue in move_op. */
4448 gcc_assert (!INSN_IN_STREAM_P (EXPR_INSN_RTX (expr
)));
4450 if (EXPR_WAS_RENAMED (expr
))
4452 unsigned regno
= expr_dest_regno (expr
);
4454 if (HARD_REGISTER_NUM_P (regno
))
4456 df_set_regs_ever_live (regno
, true);
4457 reg_rename_tick
[regno
] = ++reg_rename_this_tick
;
4461 return sel_gen_insn_from_expr_after (expr
, vinsn
, seqno
,
4465 /* Return TRUE if BB can hold bookkeeping code. */
4467 block_valid_for_bookkeeping_p (basic_block bb
)
4469 insn_t bb_end
= BB_END (bb
);
4471 if (!in_current_region_p (bb
) || EDGE_COUNT (bb
->succs
) > 1)
4474 if (INSN_P (bb_end
))
4476 if (INSN_SCHED_TIMES (bb_end
) > 0)
4480 gcc_assert (NOTE_INSN_BASIC_BLOCK_P (bb_end
));
4485 /* Attempt to find a block that can hold bookkeeping code for path(s) incoming
4486 into E2->dest, except from E1->src (there may be a sequence of empty basic
4487 blocks between E1->src and E2->dest). Return found block, or NULL if new
4488 one must be created. If LAX holds, don't assume there is a simple path
4489 from E1->src to E2->dest. */
4491 find_block_for_bookkeeping (edge e1
, edge e2
, bool lax
)
4493 basic_block candidate_block
= NULL
;
4496 /* Loop over edges from E1 to E2, inclusive. */
4497 for (e
= e1
; !lax
|| e
->dest
!= EXIT_BLOCK_PTR
; e
= EDGE_SUCC (e
->dest
, 0))
4499 if (EDGE_COUNT (e
->dest
->preds
) == 2)
4501 if (candidate_block
== NULL
)
4502 candidate_block
= (EDGE_PRED (e
->dest
, 0) == e
4503 ? EDGE_PRED (e
->dest
, 1)->src
4504 : EDGE_PRED (e
->dest
, 0)->src
);
4506 /* Found additional edge leading to path from e1 to e2
4510 else if (EDGE_COUNT (e
->dest
->preds
) > 2)
4511 /* Several edges leading to path from e1 to e2 from aside. */
4515 return ((!lax
|| candidate_block
)
4516 && block_valid_for_bookkeeping_p (candidate_block
)
4520 if (lax
&& EDGE_COUNT (e
->dest
->succs
) != 1)
4530 /* Create new basic block for bookkeeping code for path(s) incoming into
4531 E2->dest, except from E1->src. Return created block. */
4533 create_block_for_bookkeeping (edge e1
, edge e2
)
4535 basic_block new_bb
, bb
= e2
->dest
;
4537 /* Check that we don't spoil the loop structure. */
4538 if (current_loop_nest
)
4540 basic_block latch
= current_loop_nest
->latch
;
4542 /* We do not split header. */
4543 gcc_assert (e2
->dest
!= current_loop_nest
->header
);
4545 /* We do not redirect the only edge to the latch block. */
4546 gcc_assert (e1
->dest
!= latch
4547 || !single_pred_p (latch
)
4548 || e1
!= single_pred_edge (latch
));
4551 /* Split BB to insert BOOK_INSN there. */
4552 new_bb
= sched_split_block (bb
, NULL
);
4554 /* Move note_list from the upper bb. */
4555 gcc_assert (BB_NOTE_LIST (new_bb
) == NULL_RTX
);
4556 BB_NOTE_LIST (new_bb
) = BB_NOTE_LIST (bb
);
4557 BB_NOTE_LIST (bb
) = NULL_RTX
;
4559 gcc_assert (e2
->dest
== bb
);
4561 /* Skip block for bookkeeping copy when leaving E1->src. */
4562 if (e1
->flags
& EDGE_FALLTHRU
)
4563 sel_redirect_edge_and_branch_force (e1
, new_bb
);
4565 sel_redirect_edge_and_branch (e1
, new_bb
);
4567 gcc_assert (e1
->dest
== new_bb
);
4568 gcc_assert (sel_bb_empty_p (bb
));
4570 /* To keep basic block numbers in sync between debug and non-debug
4571 compilations, we have to rotate blocks here. Consider that we
4572 started from (a,b)->d, (c,d)->e, and d contained only debug
4573 insns. It would have been removed before if the debug insns
4574 weren't there, so we'd have split e rather than d. So what we do
4575 now is to swap the block numbers of new_bb and
4576 single_succ(new_bb) == e, so that the insns that were in e before
4577 get the new block number. */
4579 if (MAY_HAVE_DEBUG_INSNS
)
4582 insn_t insn
= sel_bb_head (new_bb
);
4585 if (DEBUG_INSN_P (insn
)
4586 && single_succ_p (new_bb
)
4587 && (succ
= single_succ (new_bb
))
4588 && succ
!= EXIT_BLOCK_PTR
4589 && DEBUG_INSN_P ((last
= sel_bb_end (new_bb
))))
4591 while (insn
!= last
&& (DEBUG_INSN_P (insn
) || NOTE_P (insn
)))
4592 insn
= NEXT_INSN (insn
);
4596 sel_global_bb_info_def gbi
;
4597 sel_region_bb_info_def rbi
;
4600 if (sched_verbose
>= 2)
4601 sel_print ("Swapping block ids %i and %i\n",
4602 new_bb
->index
, succ
->index
);
4605 new_bb
->index
= succ
->index
;
4608 SET_BASIC_BLOCK (new_bb
->index
, new_bb
);
4609 SET_BASIC_BLOCK (succ
->index
, succ
);
4611 memcpy (&gbi
, SEL_GLOBAL_BB_INFO (new_bb
), sizeof (gbi
));
4612 memcpy (SEL_GLOBAL_BB_INFO (new_bb
), SEL_GLOBAL_BB_INFO (succ
),
4614 memcpy (SEL_GLOBAL_BB_INFO (succ
), &gbi
, sizeof (gbi
));
4616 memcpy (&rbi
, SEL_REGION_BB_INFO (new_bb
), sizeof (rbi
));
4617 memcpy (SEL_REGION_BB_INFO (new_bb
), SEL_REGION_BB_INFO (succ
),
4619 memcpy (SEL_REGION_BB_INFO (succ
), &rbi
, sizeof (rbi
));
4621 i
= BLOCK_TO_BB (new_bb
->index
);
4622 BLOCK_TO_BB (new_bb
->index
) = BLOCK_TO_BB (succ
->index
);
4623 BLOCK_TO_BB (succ
->index
) = i
;
4625 i
= CONTAINING_RGN (new_bb
->index
);
4626 CONTAINING_RGN (new_bb
->index
) = CONTAINING_RGN (succ
->index
);
4627 CONTAINING_RGN (succ
->index
) = i
;
4629 for (i
= 0; i
< current_nr_blocks
; i
++)
4630 if (BB_TO_BLOCK (i
) == succ
->index
)
4631 BB_TO_BLOCK (i
) = new_bb
->index
;
4632 else if (BB_TO_BLOCK (i
) == new_bb
->index
)
4633 BB_TO_BLOCK (i
) = succ
->index
;
4635 FOR_BB_INSNS (new_bb
, insn
)
4637 EXPR_ORIG_BB_INDEX (INSN_EXPR (insn
)) = new_bb
->index
;
4639 FOR_BB_INSNS (succ
, insn
)
4641 EXPR_ORIG_BB_INDEX (INSN_EXPR (insn
)) = succ
->index
;
4643 if (bitmap_clear_bit (code_motion_visited_blocks
, new_bb
->index
))
4644 bitmap_set_bit (code_motion_visited_blocks
, succ
->index
);
4646 gcc_assert (LABEL_P (BB_HEAD (new_bb
))
4647 && LABEL_P (BB_HEAD (succ
)));
4649 if (sched_verbose
>= 4)
4650 sel_print ("Swapping code labels %i and %i\n",
4651 CODE_LABEL_NUMBER (BB_HEAD (new_bb
)),
4652 CODE_LABEL_NUMBER (BB_HEAD (succ
)));
4654 i
= CODE_LABEL_NUMBER (BB_HEAD (new_bb
));
4655 CODE_LABEL_NUMBER (BB_HEAD (new_bb
))
4656 = CODE_LABEL_NUMBER (BB_HEAD (succ
));
4657 CODE_LABEL_NUMBER (BB_HEAD (succ
)) = i
;
4665 /* Return insn after which we must insert bookkeeping code for path(s) incoming
4666 into E2->dest, except from E1->src. If the returned insn immediately
4667 precedes a fence, assign that fence to *FENCE_TO_REWIND. */
4669 find_place_for_bookkeeping (edge e1
, edge e2
, fence_t
*fence_to_rewind
)
4671 insn_t place_to_insert
;
4672 /* Find a basic block that can hold bookkeeping. If it can be found, do not
4673 create new basic block, but insert bookkeeping there. */
4674 basic_block book_block
= find_block_for_bookkeeping (e1
, e2
, FALSE
);
4678 place_to_insert
= BB_END (book_block
);
4680 /* Don't use a block containing only debug insns for
4681 bookkeeping, this causes scheduling differences between debug
4682 and non-debug compilations, for the block would have been
4684 if (DEBUG_INSN_P (place_to_insert
))
4686 rtx insn
= sel_bb_head (book_block
);
4688 while (insn
!= place_to_insert
&&
4689 (DEBUG_INSN_P (insn
) || NOTE_P (insn
)))
4690 insn
= NEXT_INSN (insn
);
4692 if (insn
== place_to_insert
)
4699 book_block
= create_block_for_bookkeeping (e1
, e2
);
4700 place_to_insert
= BB_END (book_block
);
4701 if (sched_verbose
>= 9)
4702 sel_print ("New block is %i, split from bookkeeping block %i\n",
4703 EDGE_SUCC (book_block
, 0)->dest
->index
, book_block
->index
);
4707 if (sched_verbose
>= 9)
4708 sel_print ("Pre-existing bookkeeping block is %i\n", book_block
->index
);
4711 *fence_to_rewind
= NULL
;
4712 /* If basic block ends with a jump, insert bookkeeping code right before it.
4713 Notice if we are crossing a fence when taking PREV_INSN. */
4714 if (INSN_P (place_to_insert
) && control_flow_insn_p (place_to_insert
))
4716 *fence_to_rewind
= flist_lookup (fences
, place_to_insert
);
4717 place_to_insert
= PREV_INSN (place_to_insert
);
4720 return place_to_insert
;
4723 /* Find a proper seqno for bookkeeing insn inserted at PLACE_TO_INSERT
4726 find_seqno_for_bookkeeping (insn_t place_to_insert
, insn_t join_point
)
4731 /* Check if we are about to insert bookkeeping copy before a jump, and use
4732 jump's seqno for the copy; otherwise, use JOIN_POINT's seqno. */
4733 next
= NEXT_INSN (place_to_insert
);
4736 && BLOCK_FOR_INSN (next
) == BLOCK_FOR_INSN (place_to_insert
))
4738 gcc_assert (INSN_SCHED_TIMES (next
) == 0);
4739 seqno
= INSN_SEQNO (next
);
4741 else if (INSN_SEQNO (join_point
) > 0)
4742 seqno
= INSN_SEQNO (join_point
);
4745 seqno
= get_seqno_by_preds (place_to_insert
);
4747 /* Sometimes the fences can move in such a way that there will be
4748 no instructions with positive seqno around this bookkeeping.
4749 This means that there will be no way to get to it by a regular
4750 fence movement. Never mind because we pick up such pieces for
4751 rescheduling anyways, so any positive value will do for now. */
4754 gcc_assert (pipelining_p
);
4759 gcc_assert (seqno
> 0);
4763 /* Insert bookkeeping copy of C_EXPS's insn after PLACE_TO_INSERT, assigning
4764 NEW_SEQNO to it. Return created insn. */
4766 emit_bookkeeping_insn (insn_t place_to_insert
, expr_t c_expr
, int new_seqno
)
4768 rtx new_insn_rtx
= create_copy_of_insn_rtx (EXPR_INSN_RTX (c_expr
));
4771 = create_vinsn_from_insn_rtx (new_insn_rtx
,
4772 VINSN_UNIQUE_P (EXPR_VINSN (c_expr
)));
4774 insn_t new_insn
= emit_insn_from_expr_after (c_expr
, new_vinsn
, new_seqno
,
4777 INSN_SCHED_TIMES (new_insn
) = 0;
4778 bitmap_set_bit (current_copies
, INSN_UID (new_insn
));
4783 /* Generate a bookkeeping copy of C_EXPR's insn for path(s) incoming into to
4784 E2->dest, except from E1->src (there may be a sequence of empty blocks
4785 between E1->src and E2->dest). Return block containing the copy.
4786 All scheduler data is initialized for the newly created insn. */
4788 generate_bookkeeping_insn (expr_t c_expr
, edge e1
, edge e2
)
4790 insn_t join_point
, place_to_insert
, new_insn
;
4792 bool need_to_exchange_data_sets
;
4793 fence_t fence_to_rewind
;
4795 if (sched_verbose
>= 4)
4796 sel_print ("Generating bookkeeping insn (%d->%d)\n", e1
->src
->index
,
4799 join_point
= sel_bb_head (e2
->dest
);
4800 place_to_insert
= find_place_for_bookkeeping (e1
, e2
, &fence_to_rewind
);
4801 new_seqno
= find_seqno_for_bookkeeping (place_to_insert
, join_point
);
4802 need_to_exchange_data_sets
4803 = sel_bb_empty_p (BLOCK_FOR_INSN (place_to_insert
));
4805 new_insn
= emit_bookkeeping_insn (place_to_insert
, c_expr
, new_seqno
);
4807 if (fence_to_rewind
)
4808 FENCE_INSN (fence_to_rewind
) = new_insn
;
4810 /* When inserting bookkeeping insn in new block, av sets should be
4811 following: old basic block (that now holds bookkeeping) data sets are
4812 the same as was before generation of bookkeeping, and new basic block
4813 (that now hold all other insns of old basic block) data sets are
4814 invalid. So exchange data sets for these basic blocks as sel_split_block
4815 mistakenly exchanges them in this case. Cannot do it earlier because
4816 when single instruction is added to new basic block it should hold NULL
4818 if (need_to_exchange_data_sets
)
4819 exchange_data_sets (BLOCK_FOR_INSN (new_insn
),
4820 BLOCK_FOR_INSN (join_point
));
4822 stat_bookkeeping_copies
++;
4823 return BLOCK_FOR_INSN (new_insn
);
4826 /* Remove from AV_PTR all insns that may need bookkeeping when scheduling
4827 on FENCE, but we are unable to copy them. */
4829 remove_insns_that_need_bookkeeping (fence_t fence
, av_set_t
*av_ptr
)
4834 /* An expression does not need bookkeeping if it is available on all paths
4835 from current block to original block and current block dominates
4836 original block. We check availability on all paths by examining
4837 EXPR_SPEC; this is not equivalent, because it may be positive even
4838 if expr is available on all paths (but if expr is not available on
4839 any path, EXPR_SPEC will be positive). */
4841 FOR_EACH_EXPR_1 (expr
, i
, av_ptr
)
4843 if (!control_flow_insn_p (EXPR_INSN_RTX (expr
))
4844 && (!bookkeeping_p
|| VINSN_UNIQUE_P (EXPR_VINSN (expr
)))
4845 && (EXPR_SPEC (expr
)
4846 || !EXPR_ORIG_BB_INDEX (expr
)
4847 || !dominated_by_p (CDI_DOMINATORS
,
4848 BASIC_BLOCK (EXPR_ORIG_BB_INDEX (expr
)),
4849 BLOCK_FOR_INSN (FENCE_INSN (fence
)))))
4851 if (sched_verbose
>= 4)
4852 sel_print ("Expr %d removed because it would need bookkeeping, which "
4853 "cannot be created\n", INSN_UID (EXPR_INSN_RTX (expr
)));
4854 av_set_iter_remove (&i
);
4859 /* Moving conditional jump through some instructions.
4863 ... <- current scheduling point
4864 NOTE BASIC BLOCK: <- bb header
4865 (p8) add r14=r14+0x9;;
4871 We can schedule jump one cycle earlier, than mov, because they cannot be
4872 executed together as their predicates are mutually exclusive.
4874 This is done in this way: first, new fallthrough basic block is created
4875 after jump (it is always can be done, because there already should be a
4876 fallthrough block, where control flow goes in case of predicate being true -
4877 in our example; otherwise there should be a dependence between those
4878 instructions and jump and we cannot schedule jump right now);
4879 next, all instructions between jump and current scheduling point are moved
4880 to this new block. And the result is this:
4883 (!p8) jump L1 <- current scheduling point
4884 NOTE BASIC BLOCK: <- bb header
4885 (p8) add r14=r14+0x9;;
4891 move_cond_jump (rtx insn
, bnd_t bnd
)
4894 basic_block block_from
, block_next
, block_new
, block_bnd
, bb
;
4895 rtx next
, prev
, link
, head
;
4897 block_from
= BLOCK_FOR_INSN (insn
);
4898 block_bnd
= BLOCK_FOR_INSN (BND_TO (bnd
));
4899 prev
= BND_TO (bnd
);
4901 #ifdef ENABLE_CHECKING
4902 /* Moving of jump should not cross any other jumps or beginnings of new
4903 basic blocks. The only exception is when we move a jump through
4904 mutually exclusive insns along fallthru edges. */
4905 if (block_from
!= block_bnd
)
4908 for (link
= PREV_INSN (insn
); link
!= PREV_INSN (prev
);
4909 link
= PREV_INSN (link
))
4912 gcc_assert (sched_insns_conditions_mutex_p (insn
, link
));
4913 if (BLOCK_FOR_INSN (link
) && BLOCK_FOR_INSN (link
) != bb
)
4915 gcc_assert (single_pred (bb
) == BLOCK_FOR_INSN (link
));
4916 bb
= BLOCK_FOR_INSN (link
);
4922 /* Jump is moved to the boundary. */
4923 next
= PREV_INSN (insn
);
4924 BND_TO (bnd
) = insn
;
4926 ft_edge
= find_fallthru_edge_from (block_from
);
4927 block_next
= ft_edge
->dest
;
4928 /* There must be a fallthrough block (or where should go
4929 control flow in case of false jump predicate otherwise?). */
4930 gcc_assert (block_next
);
4932 /* Create new empty basic block after source block. */
4933 block_new
= sel_split_edge (ft_edge
);
4934 gcc_assert (block_new
->next_bb
== block_next
4935 && block_from
->next_bb
== block_new
);
4937 /* Move all instructions except INSN to BLOCK_NEW. */
4939 head
= BB_HEAD (block_new
);
4940 while (bb
!= block_from
->next_bb
)
4943 from
= bb
== block_bnd
? prev
: sel_bb_head (bb
);
4944 to
= bb
== block_from
? next
: sel_bb_end (bb
);
4946 /* The jump being moved can be the first insn in the block.
4947 In this case we don't have to move anything in this block. */
4948 if (NEXT_INSN (to
) != from
)
4950 reorder_insns (from
, to
, head
);
4952 for (link
= to
; link
!= head
; link
= PREV_INSN (link
))
4953 EXPR_ORIG_BB_INDEX (INSN_EXPR (link
)) = block_new
->index
;
4957 /* Cleanup possibly empty blocks left. */
4958 block_next
= bb
->next_bb
;
4959 if (bb
!= block_from
)
4960 tidy_control_flow (bb
, false);
4964 /* Assert there is no jump to BLOCK_NEW, only fallthrough edge. */
4965 gcc_assert (NOTE_INSN_BASIC_BLOCK_P (BB_HEAD (block_new
)));
4967 gcc_assert (!sel_bb_empty_p (block_from
)
4968 && !sel_bb_empty_p (block_new
));
4970 /* Update data sets for BLOCK_NEW to represent that INSN and
4971 instructions from the other branch of INSN is no longer
4972 available at BLOCK_NEW. */
4973 BB_AV_LEVEL (block_new
) = global_level
;
4974 gcc_assert (BB_LV_SET (block_new
) == NULL
);
4975 BB_LV_SET (block_new
) = get_clear_regset_from_pool ();
4976 update_data_sets (sel_bb_head (block_new
));
4978 /* INSN is a new basic block header - so prepare its data
4979 structures and update availability and liveness sets. */
4980 update_data_sets (insn
);
4982 if (sched_verbose
>= 4)
4983 sel_print ("Moving jump %d\n", INSN_UID (insn
));
4986 /* Remove nops generated during move_op for preventing removal of empty
4989 remove_temp_moveop_nops (bool full_tidying
)
4994 FOR_EACH_VEC_ELT (insn_t
, vec_temp_moveop_nops
, i
, insn
)
4996 gcc_assert (INSN_NOP_P (insn
));
4997 return_nop_to_pool (insn
, full_tidying
);
5000 /* Empty the vector. */
5001 if (VEC_length (insn_t
, vec_temp_moveop_nops
) > 0)
5002 VEC_block_remove (insn_t
, vec_temp_moveop_nops
, 0,
5003 VEC_length (insn_t
, vec_temp_moveop_nops
));
5006 /* Records the maximal UID before moving up an instruction. Used for
5007 distinguishing between bookkeeping copies and original insns. */
5008 static int max_uid_before_move_op
= 0;
5010 /* Remove from AV_VLIW_P all instructions but next when debug counter
5011 tells us so. Next instruction is fetched from BNDS. */
5013 remove_insns_for_debug (blist_t bnds
, av_set_t
*av_vliw_p
)
5015 if (! dbg_cnt (sel_sched_insn_cnt
))
5016 /* Leave only the next insn in av_vliw. */
5018 av_set_iterator av_it
;
5020 bnd_t bnd
= BLIST_BND (bnds
);
5021 insn_t next
= BND_TO (bnd
);
5023 gcc_assert (BLIST_NEXT (bnds
) == NULL
);
5025 FOR_EACH_EXPR_1 (expr
, av_it
, av_vliw_p
)
5026 if (EXPR_INSN_RTX (expr
) != next
)
5027 av_set_iter_remove (&av_it
);
5031 /* Compute available instructions on BNDS. FENCE is the current fence. Write
5032 the computed set to *AV_VLIW_P. */
5034 compute_av_set_on_boundaries (fence_t fence
, blist_t bnds
, av_set_t
*av_vliw_p
)
5036 if (sched_verbose
>= 2)
5038 sel_print ("Boundaries: ");
5043 for (; bnds
; bnds
= BLIST_NEXT (bnds
))
5045 bnd_t bnd
= BLIST_BND (bnds
);
5047 insn_t bnd_to
= BND_TO (bnd
);
5049 /* Rewind BND->TO to the basic block header in case some bookkeeping
5050 instructions were inserted before BND->TO and it needs to be
5052 if (sel_bb_head_p (bnd_to
))
5053 gcc_assert (INSN_SCHED_TIMES (bnd_to
) == 0);
5055 while (INSN_SCHED_TIMES (PREV_INSN (bnd_to
)) == 0)
5057 bnd_to
= PREV_INSN (bnd_to
);
5058 if (sel_bb_head_p (bnd_to
))
5062 if (BND_TO (bnd
) != bnd_to
)
5064 gcc_assert (FENCE_INSN (fence
) == BND_TO (bnd
));
5065 FENCE_INSN (fence
) = bnd_to
;
5066 BND_TO (bnd
) = bnd_to
;
5069 av_set_clear (&BND_AV (bnd
));
5070 BND_AV (bnd
) = compute_av_set (BND_TO (bnd
), NULL
, 0, true);
5072 av_set_clear (&BND_AV1 (bnd
));
5073 BND_AV1 (bnd
) = av_set_copy (BND_AV (bnd
));
5075 moveup_set_inside_insn_group (&BND_AV1 (bnd
), NULL
);
5077 av1_copy
= av_set_copy (BND_AV1 (bnd
));
5078 av_set_union_and_clear (av_vliw_p
, &av1_copy
, NULL
);
5081 if (sched_verbose
>= 2)
5083 sel_print ("Available exprs (vliw form): ");
5084 dump_av_set (*av_vliw_p
);
5089 /* Calculate the sequential av set on BND corresponding to the EXPR_VLIW
5090 expression. When FOR_MOVEOP is true, also replace the register of
5091 expressions found with the register from EXPR_VLIW. */
5093 find_sequential_best_exprs (bnd_t bnd
, expr_t expr_vliw
, bool for_moveop
)
5095 av_set_t expr_seq
= NULL
;
5099 FOR_EACH_EXPR (expr
, i
, BND_AV (bnd
))
5101 if (equal_after_moveup_path_p (expr
, NULL
, expr_vliw
))
5105 /* The sequential expression has the right form to pass
5106 to move_op except when renaming happened. Put the
5107 correct register in EXPR then. */
5108 if (EXPR_SEPARABLE_P (expr
) && REG_P (EXPR_LHS (expr
)))
5110 if (expr_dest_regno (expr
) != expr_dest_regno (expr_vliw
))
5112 replace_dest_with_reg_in_expr (expr
, EXPR_LHS (expr_vliw
));
5113 stat_renamed_scheduled
++;
5115 /* Also put the correct TARGET_AVAILABLE bit on the expr.
5116 This is needed when renaming came up with original
5118 else if (EXPR_TARGET_AVAILABLE (expr
)
5119 != EXPR_TARGET_AVAILABLE (expr_vliw
))
5121 gcc_assert (EXPR_TARGET_AVAILABLE (expr_vliw
) == 1);
5122 EXPR_TARGET_AVAILABLE (expr
) = 1;
5125 if (EXPR_WAS_SUBSTITUTED (expr
))
5126 stat_substitutions_total
++;
5129 av_set_add (&expr_seq
, expr
);
5131 /* With substitution inside insn group, it is possible
5132 that more than one expression in expr_seq will correspond
5133 to expr_vliw. In this case, choose one as the attempt to
5134 move both leads to miscompiles. */
5139 if (for_moveop
&& sched_verbose
>= 2)
5141 sel_print ("Best expression(s) (sequential form): ");
5142 dump_av_set (expr_seq
);
5150 /* Move nop to previous block. */
5151 static void ATTRIBUTE_UNUSED
5152 move_nop_to_previous_block (insn_t nop
, basic_block prev_bb
)
5154 insn_t prev_insn
, next_insn
, note
;
5156 gcc_assert (sel_bb_head_p (nop
)
5157 && prev_bb
== BLOCK_FOR_INSN (nop
)->prev_bb
);
5158 note
= bb_note (BLOCK_FOR_INSN (nop
));
5159 prev_insn
= sel_bb_end (prev_bb
);
5160 next_insn
= NEXT_INSN (nop
);
5161 gcc_assert (prev_insn
!= NULL_RTX
5162 && PREV_INSN (note
) == prev_insn
);
5164 NEXT_INSN (prev_insn
) = nop
;
5165 PREV_INSN (nop
) = prev_insn
;
5167 PREV_INSN (note
) = nop
;
5168 NEXT_INSN (note
) = next_insn
;
5170 NEXT_INSN (nop
) = note
;
5171 PREV_INSN (next_insn
) = note
;
5173 BB_END (prev_bb
) = nop
;
5174 BLOCK_FOR_INSN (nop
) = prev_bb
;
5177 /* Prepare a place to insert the chosen expression on BND. */
5179 prepare_place_to_insert (bnd_t bnd
)
5181 insn_t place_to_insert
;
5183 /* Init place_to_insert before calling move_op, as the later
5184 can possibly remove BND_TO (bnd). */
5185 if (/* If this is not the first insn scheduled. */
5188 /* Add it after last scheduled. */
5189 place_to_insert
= ILIST_INSN (BND_PTR (bnd
));
5190 if (DEBUG_INSN_P (place_to_insert
))
5192 ilist_t l
= BND_PTR (bnd
);
5193 while ((l
= ILIST_NEXT (l
)) &&
5194 DEBUG_INSN_P (ILIST_INSN (l
)))
5197 place_to_insert
= NULL
;
5201 place_to_insert
= NULL
;
5203 if (!place_to_insert
)
5205 /* Add it before BND_TO. The difference is in the
5206 basic block, where INSN will be added. */
5207 place_to_insert
= get_nop_from_pool (BND_TO (bnd
));
5208 gcc_assert (BLOCK_FOR_INSN (place_to_insert
)
5209 == BLOCK_FOR_INSN (BND_TO (bnd
)));
5212 return place_to_insert
;
5215 /* Find original instructions for EXPR_SEQ and move it to BND boundary.
5216 Return the expression to emit in C_EXPR. */
5218 move_exprs_to_boundary (bnd_t bnd
, expr_t expr_vliw
,
5219 av_set_t expr_seq
, expr_t c_expr
)
5221 bool b
, should_move
;
5224 int n_bookkeeping_copies_before_moveop
;
5226 /* Make a move. This call will remove the original operation,
5227 insert all necessary bookkeeping instructions and update the
5228 data sets. After that all we have to do is add the operation
5229 at before BND_TO (BND). */
5230 n_bookkeeping_copies_before_moveop
= stat_bookkeeping_copies
;
5231 max_uid_before_move_op
= get_max_uid ();
5232 bitmap_clear (current_copies
);
5233 bitmap_clear (current_originators
);
5235 b
= move_op (BND_TO (bnd
), expr_seq
, expr_vliw
,
5236 get_dest_from_orig_ops (expr_seq
), c_expr
, &should_move
);
5238 /* We should be able to find the expression we've chosen for
5242 if (stat_bookkeeping_copies
> n_bookkeeping_copies_before_moveop
)
5243 stat_insns_needed_bookkeeping
++;
5245 EXECUTE_IF_SET_IN_BITMAP (current_copies
, 0, book_uid
, bi
)
5250 /* We allocate these bitmaps lazily. */
5251 if (! INSN_ORIGINATORS_BY_UID (book_uid
))
5252 INSN_ORIGINATORS_BY_UID (book_uid
) = BITMAP_ALLOC (NULL
);
5254 bitmap_copy (INSN_ORIGINATORS_BY_UID (book_uid
),
5255 current_originators
);
5257 /* Transitively add all originators' originators. */
5258 EXECUTE_IF_SET_IN_BITMAP (current_originators
, 0, uid
, bi
)
5259 if (INSN_ORIGINATORS_BY_UID (uid
))
5260 bitmap_ior_into (INSN_ORIGINATORS_BY_UID (book_uid
),
5261 INSN_ORIGINATORS_BY_UID (uid
));
5268 /* Debug a DFA state as an array of bytes. */
5270 debug_state (state_t state
)
5273 unsigned int i
, size
= dfa_state_size
;
5275 sel_print ("state (%u):", size
);
5276 for (i
= 0, p
= (unsigned char *) state
; i
< size
; i
++)
5277 sel_print (" %d", p
[i
]);
5281 /* Advance state on FENCE with INSN. Return true if INSN is
5282 an ASM, and we should advance state once more. */
5284 advance_state_on_fence (fence_t fence
, insn_t insn
)
5288 if (recog_memoized (insn
) >= 0)
5291 state_t temp_state
= alloca (dfa_state_size
);
5293 gcc_assert (!INSN_ASM_P (insn
));
5296 memcpy (temp_state
, FENCE_STATE (fence
), dfa_state_size
);
5297 res
= state_transition (FENCE_STATE (fence
), insn
);
5298 gcc_assert (res
< 0);
5300 if (memcmp (temp_state
, FENCE_STATE (fence
), dfa_state_size
))
5302 FENCE_ISSUED_INSNS (fence
)++;
5304 /* We should never issue more than issue_rate insns. */
5305 if (FENCE_ISSUED_INSNS (fence
) > issue_rate
)
5311 /* This could be an ASM insn which we'd like to schedule
5312 on the next cycle. */
5313 asm_p
= INSN_ASM_P (insn
);
5314 if (!FENCE_STARTS_CYCLE_P (fence
) && asm_p
)
5315 advance_one_cycle (fence
);
5318 if (sched_verbose
>= 2)
5319 debug_state (FENCE_STATE (fence
));
5320 if (!DEBUG_INSN_P (insn
))
5321 FENCE_STARTS_CYCLE_P (fence
) = 0;
5322 FENCE_ISSUE_MORE (fence
) = can_issue_more
;
5326 /* Update FENCE on which INSN was scheduled and this INSN, too. NEED_STALL
5327 is nonzero if we need to stall after issuing INSN. */
5329 update_fence_and_insn (fence_t fence
, insn_t insn
, int need_stall
)
5333 /* First, reflect that something is scheduled on this fence. */
5334 asm_p
= advance_state_on_fence (fence
, insn
);
5335 FENCE_LAST_SCHEDULED_INSN (fence
) = insn
;
5336 VEC_safe_push (rtx
, gc
, FENCE_EXECUTING_INSNS (fence
), insn
);
5337 if (SCHED_GROUP_P (insn
))
5339 FENCE_SCHED_NEXT (fence
) = INSN_SCHED_NEXT (insn
);
5340 SCHED_GROUP_P (insn
) = 0;
5343 FENCE_SCHED_NEXT (fence
) = NULL_RTX
;
5344 if (INSN_UID (insn
) < FENCE_READY_TICKS_SIZE (fence
))
5345 FENCE_READY_TICKS (fence
) [INSN_UID (insn
)] = 0;
5347 /* Set instruction scheduling info. This will be used in bundling,
5348 pipelining, tick computations etc. */
5349 ++INSN_SCHED_TIMES (insn
);
5350 EXPR_TARGET_AVAILABLE (INSN_EXPR (insn
)) = true;
5351 EXPR_ORIG_SCHED_CYCLE (INSN_EXPR (insn
)) = FENCE_CYCLE (fence
);
5352 INSN_AFTER_STALL_P (insn
) = FENCE_AFTER_STALL_P (fence
);
5353 INSN_SCHED_CYCLE (insn
) = FENCE_CYCLE (fence
);
5355 /* This does not account for adjust_cost hooks, just add the biggest
5356 constant the hook may add to the latency. TODO: make this
5357 a target dependent constant. */
5358 INSN_READY_CYCLE (insn
)
5359 = INSN_SCHED_CYCLE (insn
) + (INSN_CODE (insn
) < 0
5361 : maximal_insn_latency (insn
) + 1);
5363 /* Change these fields last, as they're used above. */
5364 FENCE_AFTER_STALL_P (fence
) = 0;
5365 if (asm_p
|| need_stall
)
5366 advance_one_cycle (fence
);
5368 /* Indicate that we've scheduled something on this fence. */
5369 FENCE_SCHEDULED_P (fence
) = true;
5370 scheduled_something_on_previous_fence
= true;
5372 /* Print debug information when insn's fields are updated. */
5373 if (sched_verbose
>= 2)
5375 sel_print ("Scheduling insn: ");
5376 dump_insn_1 (insn
, 1);
5381 /* Update boundary BND (and, if needed, FENCE) with INSN, remove the
5382 old boundary from BNDSP, add new boundaries to BNDS_TAIL_P and
5385 update_boundaries (fence_t fence
, bnd_t bnd
, insn_t insn
, blist_t
*bndsp
,
5386 blist_t
*bnds_tailp
)
5391 advance_deps_context (BND_DC (bnd
), insn
);
5392 FOR_EACH_SUCC_1 (succ
, si
, insn
,
5393 SUCCS_NORMAL
| SUCCS_SKIP_TO_LOOP_EXITS
)
5395 ilist_t ptr
= ilist_copy (BND_PTR (bnd
));
5397 ilist_add (&ptr
, insn
);
5399 if (DEBUG_INSN_P (insn
) && sel_bb_end_p (insn
)
5400 && is_ineligible_successor (succ
, ptr
))
5406 if (FENCE_INSN (fence
) == insn
&& !sel_bb_end_p (insn
))
5408 if (sched_verbose
>= 9)
5409 sel_print ("Updating fence insn from %i to %i\n",
5410 INSN_UID (insn
), INSN_UID (succ
));
5411 FENCE_INSN (fence
) = succ
;
5413 blist_add (bnds_tailp
, succ
, ptr
, BND_DC (bnd
));
5414 bnds_tailp
= &BLIST_NEXT (*bnds_tailp
);
5417 blist_remove (bndsp
);
5421 /* Schedule EXPR_VLIW on BND. Return the insn emitted. */
5423 schedule_expr_on_boundary (bnd_t bnd
, expr_t expr_vliw
, int seqno
)
5426 expr_t c_expr
= XALLOCA (expr_def
);
5427 insn_t place_to_insert
;
5431 expr_seq
= find_sequential_best_exprs (bnd
, expr_vliw
, true);
5433 /* In case of scheduling a jump skipping some other instructions,
5434 prepare CFG. After this, jump is at the boundary and can be
5435 scheduled as usual insn by MOVE_OP. */
5436 if (vinsn_cond_branch_p (EXPR_VINSN (expr_vliw
)))
5438 insn
= EXPR_INSN_RTX (expr_vliw
);
5440 /* Speculative jumps are not handled. */
5441 if (insn
!= BND_TO (bnd
)
5442 && !sel_insn_is_speculation_check (insn
))
5443 move_cond_jump (insn
, bnd
);
5446 /* Find a place for C_EXPR to schedule. */
5447 place_to_insert
= prepare_place_to_insert (bnd
);
5448 should_move
= move_exprs_to_boundary (bnd
, expr_vliw
, expr_seq
, c_expr
);
5449 clear_expr (c_expr
);
5451 /* Add the instruction. The corner case to care about is when
5452 the expr_seq set has more than one expr, and we chose the one that
5453 is not equal to expr_vliw. Then expr_vliw may be insn in stream, and
5454 we can't use it. Generate the new vinsn. */
5455 if (INSN_IN_STREAM_P (EXPR_INSN_RTX (expr_vliw
)))
5459 vinsn_new
= vinsn_copy (EXPR_VINSN (expr_vliw
), false);
5460 change_vinsn_in_expr (expr_vliw
, vinsn_new
);
5461 should_move
= false;
5464 insn
= sel_move_insn (expr_vliw
, seqno
, place_to_insert
);
5466 insn
= emit_insn_from_expr_after (expr_vliw
, NULL
, seqno
,
5469 /* Return the nops generated for preserving of data sets back
5471 if (INSN_NOP_P (place_to_insert
))
5472 return_nop_to_pool (place_to_insert
, !DEBUG_INSN_P (insn
));
5473 remove_temp_moveop_nops (!DEBUG_INSN_P (insn
));
5475 av_set_clear (&expr_seq
);
5477 /* Save the expression scheduled so to reset target availability if we'll
5478 meet it later on the same fence. */
5479 if (EXPR_WAS_RENAMED (expr_vliw
))
5480 vinsn_vec_add (&vec_target_unavailable_vinsns
, INSN_EXPR (insn
));
5482 /* Check that the recent movement didn't destroyed loop
5484 gcc_assert (!pipelining_p
5485 || current_loop_nest
== NULL
5486 || loop_latch_edge (current_loop_nest
));
5490 /* Stall for N cycles on FENCE. */
5492 stall_for_cycles (fence_t fence
, int n
)
5496 could_more
= n
> 1 || FENCE_ISSUED_INSNS (fence
) < issue_rate
;
5498 advance_one_cycle (fence
);
5500 FENCE_AFTER_STALL_P (fence
) = 1;
5503 /* Gather a parallel group of insns at FENCE and assign their seqno
5504 to SEQNO. All scheduled insns are gathered in SCHEDULED_INSNS_TAILPP
5505 list for later recalculation of seqnos. */
5507 fill_insns (fence_t fence
, int seqno
, ilist_t
**scheduled_insns_tailpp
)
5509 blist_t bnds
= NULL
, *bnds_tailp
;
5510 av_set_t av_vliw
= NULL
;
5511 insn_t insn
= FENCE_INSN (fence
);
5513 if (sched_verbose
>= 2)
5514 sel_print ("Starting fill_insns for insn %d, cycle %d\n",
5515 INSN_UID (insn
), FENCE_CYCLE (fence
));
5517 blist_add (&bnds
, insn
, NULL
, FENCE_DC (fence
));
5518 bnds_tailp
= &BLIST_NEXT (bnds
);
5519 set_target_context (FENCE_TC (fence
));
5520 can_issue_more
= FENCE_ISSUE_MORE (fence
);
5521 target_bb
= INSN_BB (insn
);
5523 /* Do while we can add any operation to the current group. */
5526 blist_t
*bnds_tailp1
, *bndsp
;
5528 int need_stall
= false;
5529 int was_stall
= 0, scheduled_insns
= 0;
5530 int max_insns
= pipelining_p
? issue_rate
: 2 * issue_rate
;
5531 int max_stall
= pipelining_p
? 1 : 3;
5532 bool last_insn_was_debug
= false;
5533 bool was_debug_bb_end_p
= false;
5535 compute_av_set_on_boundaries (fence
, bnds
, &av_vliw
);
5536 remove_insns_that_need_bookkeeping (fence
, &av_vliw
);
5537 remove_insns_for_debug (bnds
, &av_vliw
);
5539 /* Return early if we have nothing to schedule. */
5540 if (av_vliw
== NULL
)
5543 /* Choose the best expression and, if needed, destination register
5547 expr_vliw
= find_best_expr (&av_vliw
, bnds
, fence
, &need_stall
);
5548 if (! expr_vliw
&& need_stall
)
5550 /* All expressions required a stall. Do not recompute av sets
5551 as we'll get the same answer (modulo the insns between
5552 the fence and its boundary, which will not be available for
5554 If we are going to stall for too long, break to recompute av
5555 sets and bring more insns for pipelining. */
5557 if (need_stall
<= 3)
5558 stall_for_cycles (fence
, need_stall
);
5561 stall_for_cycles (fence
, 1);
5566 while (! expr_vliw
&& need_stall
);
5568 /* Now either we've selected expr_vliw or we have nothing to schedule. */
5571 av_set_clear (&av_vliw
);
5576 bnds_tailp1
= bnds_tailp
;
5579 /* This code will be executed only once until we'd have several
5580 boundaries per fence. */
5582 bnd_t bnd
= BLIST_BND (*bndsp
);
5584 if (!av_set_is_in_p (BND_AV1 (bnd
), EXPR_VINSN (expr_vliw
)))
5586 bndsp
= &BLIST_NEXT (*bndsp
);
5590 insn
= schedule_expr_on_boundary (bnd
, expr_vliw
, seqno
);
5591 last_insn_was_debug
= DEBUG_INSN_P (insn
);
5592 if (last_insn_was_debug
)
5593 was_debug_bb_end_p
= (insn
== BND_TO (bnd
) && sel_bb_end_p (insn
));
5594 update_fence_and_insn (fence
, insn
, need_stall
);
5595 bnds_tailp
= update_boundaries (fence
, bnd
, insn
, bndsp
, bnds_tailp
);
5597 /* Add insn to the list of scheduled on this cycle instructions. */
5598 ilist_add (*scheduled_insns_tailpp
, insn
);
5599 *scheduled_insns_tailpp
= &ILIST_NEXT (**scheduled_insns_tailpp
);
5601 while (*bndsp
!= *bnds_tailp1
);
5603 av_set_clear (&av_vliw
);
5604 if (!last_insn_was_debug
)
5607 /* We currently support information about candidate blocks only for
5608 one 'target_bb' block. Hence we can't schedule after jump insn,
5609 as this will bring two boundaries and, hence, necessity to handle
5610 information for two or more blocks concurrently. */
5611 if ((last_insn_was_debug
? was_debug_bb_end_p
: sel_bb_end_p (insn
))
5613 && (was_stall
>= max_stall
5614 || scheduled_insns
>= max_insns
)))
5619 gcc_assert (!FENCE_BNDS (fence
));
5621 /* Update boundaries of the FENCE. */
5624 ilist_t ptr
= BND_PTR (BLIST_BND (bnds
));
5628 insn
= ILIST_INSN (ptr
);
5630 if (!ilist_is_in_p (FENCE_BNDS (fence
), insn
))
5631 ilist_add (&FENCE_BNDS (fence
), insn
);
5634 blist_remove (&bnds
);
5637 /* Update target context on the fence. */
5638 reset_target_context (FENCE_TC (fence
), false);
5641 /* All exprs in ORIG_OPS must have the same destination register or memory.
5642 Return that destination. */
5644 get_dest_from_orig_ops (av_set_t orig_ops
)
5646 rtx dest
= NULL_RTX
;
5647 av_set_iterator av_it
;
5649 bool first_p
= true;
5651 FOR_EACH_EXPR (expr
, av_it
, orig_ops
)
5653 rtx x
= EXPR_LHS (expr
);
5661 gcc_assert (dest
== x
5662 || (dest
!= NULL_RTX
&& x
!= NULL_RTX
5663 && rtx_equal_p (dest
, x
)));
5669 /* Update data sets for the bookkeeping block and record those expressions
5670 which become no longer available after inserting this bookkeeping. */
5672 update_and_record_unavailable_insns (basic_block book_block
)
5675 av_set_t old_av_set
= NULL
;
5677 rtx bb_end
= sel_bb_end (book_block
);
5679 /* First, get correct liveness in the bookkeeping block. The problem is
5680 the range between the bookeeping insn and the end of block. */
5681 update_liveness_on_insn (bb_end
);
5682 if (control_flow_insn_p (bb_end
))
5683 update_liveness_on_insn (PREV_INSN (bb_end
));
5685 /* If there's valid av_set on BOOK_BLOCK, then there might exist another
5686 fence above, where we may choose to schedule an insn which is
5687 actually blocked from moving up with the bookkeeping we create here. */
5688 if (AV_SET_VALID_P (sel_bb_head (book_block
)))
5690 old_av_set
= av_set_copy (BB_AV_SET (book_block
));
5691 update_data_sets (sel_bb_head (book_block
));
5693 /* Traverse all the expressions in the old av_set and check whether
5694 CUR_EXPR is in new AV_SET. */
5695 FOR_EACH_EXPR (cur_expr
, i
, old_av_set
)
5697 expr_t new_expr
= av_set_lookup (BB_AV_SET (book_block
),
5698 EXPR_VINSN (cur_expr
));
5701 /* In this case, we can just turn off the E_T_A bit, but we can't
5702 represent this information with the current vector. */
5703 || EXPR_TARGET_AVAILABLE (new_expr
)
5704 != EXPR_TARGET_AVAILABLE (cur_expr
))
5705 /* Unfortunately, the below code could be also fired up on
5707 FIXME: add an example of how this could happen. */
5708 vinsn_vec_add (&vec_bookkeeping_blocked_vinsns
, cur_expr
);
5711 av_set_clear (&old_av_set
);
5715 /* The main effect of this function is that sparams->c_expr is merged
5716 with (or copied to) lparams->c_expr_merged. If there's only one successor,
5717 we avoid merging anything by copying sparams->c_expr to lparams->c_expr_merged.
5718 lparams->c_expr_merged is copied back to sparams->c_expr after all
5719 successors has been traversed. lparams->c_expr_local is an expr allocated
5720 on stack in the caller function, and is used if there is more than one
5723 SUCC is one of the SUCCS_NORMAL successors of INSN,
5724 MOVEOP_DRV_CALL_RES is the result of call code_motion_path_driver on succ,
5725 LPARAMS and STATIC_PARAMS contain the parameters described above. */
5727 move_op_merge_succs (insn_t insn ATTRIBUTE_UNUSED
,
5728 insn_t succ ATTRIBUTE_UNUSED
,
5729 int moveop_drv_call_res
,
5730 cmpd_local_params_p lparams
, void *static_params
)
5732 moveop_static_params_p sparams
= (moveop_static_params_p
) static_params
;
5734 /* Nothing to do, if original expr wasn't found below. */
5735 if (moveop_drv_call_res
!= 1)
5738 /* If this is a first successor. */
5739 if (!lparams
->c_expr_merged
)
5741 lparams
->c_expr_merged
= sparams
->c_expr
;
5742 sparams
->c_expr
= lparams
->c_expr_local
;
5746 /* We must merge all found expressions to get reasonable
5747 EXPR_SPEC_DONE_DS for the resulting insn. If we don't
5748 do so then we can first find the expr with epsilon
5749 speculation success probability and only then with the
5750 good probability. As a result the insn will get epsilon
5751 probability and will never be scheduled because of
5752 weakness_cutoff in find_best_expr.
5754 We call merge_expr_data here instead of merge_expr
5755 because due to speculation C_EXPR and X may have the
5756 same insns with different speculation types. And as of
5757 now such insns are considered non-equal.
5759 However, EXPR_SCHED_TIMES is different -- we must get
5760 SCHED_TIMES from a real insn, not a bookkeeping copy.
5761 We force this here. Instead, we may consider merging
5762 SCHED_TIMES to the maximum instead of minimum in the
5764 int old_times
= EXPR_SCHED_TIMES (lparams
->c_expr_merged
);
5766 merge_expr_data (lparams
->c_expr_merged
, sparams
->c_expr
, NULL
);
5767 if (EXPR_SCHED_TIMES (sparams
->c_expr
) == 0)
5768 EXPR_SCHED_TIMES (lparams
->c_expr_merged
) = old_times
;
5770 clear_expr (sparams
->c_expr
);
5774 /* Add used regs for the successor SUCC into SPARAMS->USED_REGS.
5776 SUCC is one of the SUCCS_NORMAL successors of INSN,
5777 MOVEOP_DRV_CALL_RES is the result of call code_motion_path_driver on succ or 0,
5778 if SUCC is one of SUCCS_BACK or SUCCS_OUT.
5779 STATIC_PARAMS contain USED_REGS set. */
5781 fur_merge_succs (insn_t insn ATTRIBUTE_UNUSED
, insn_t succ
,
5782 int moveop_drv_call_res
,
5783 cmpd_local_params_p lparams ATTRIBUTE_UNUSED
,
5784 void *static_params
)
5787 fur_static_params_p sparams
= (fur_static_params_p
) static_params
;
5789 /* Here we compute live regsets only for branches that do not lie
5790 on the code motion paths. These branches correspond to value
5791 MOVEOP_DRV_CALL_RES==0 and include SUCCS_BACK and SUCCS_OUT, though
5792 for such branches code_motion_path_driver is not called. */
5793 if (moveop_drv_call_res
!= 0)
5796 /* Mark all registers that do not meet the following condition:
5797 (3) not live on the other path of any conditional branch
5798 that is passed by the operation, in case original
5799 operations are not present on both paths of the
5800 conditional branch. */
5801 succ_live
= compute_live (succ
);
5802 IOR_REG_SET (sparams
->used_regs
, succ_live
);
5805 /* This function is called after the last successor. Copies LP->C_EXPR_MERGED
5808 move_op_after_merge_succs (cmpd_local_params_p lp
, void *sparams
)
5810 moveop_static_params_p sp
= (moveop_static_params_p
) sparams
;
5812 sp
->c_expr
= lp
->c_expr_merged
;
5815 /* Track bookkeeping copies created, insns scheduled, and blocks for
5816 rescheduling when INSN is found by move_op. */
5818 track_scheduled_insns_and_blocks (rtx insn
)
5820 /* Even if this insn can be a copy that will be removed during current move_op,
5821 we still need to count it as an originator. */
5822 bitmap_set_bit (current_originators
, INSN_UID (insn
));
5824 if (!bitmap_clear_bit (current_copies
, INSN_UID (insn
)))
5826 /* Note that original block needs to be rescheduled, as we pulled an
5827 instruction out of it. */
5828 if (INSN_SCHED_TIMES (insn
) > 0)
5829 bitmap_set_bit (blocks_to_reschedule
, BLOCK_FOR_INSN (insn
)->index
);
5830 else if (INSN_UID (insn
) < first_emitted_uid
&& !DEBUG_INSN_P (insn
))
5831 num_insns_scheduled
++;
5834 /* For instructions we must immediately remove insn from the
5835 stream, so subsequent update_data_sets () won't include this
5837 For expr we must make insn look like "INSN_REG (insn) := c_expr". */
5838 if (INSN_UID (insn
) > max_uid_before_move_op
)
5839 stat_bookkeeping_copies
--;
5842 /* Emit a register-register copy for INSN if needed. Return true if
5843 emitted one. PARAMS is the move_op static parameters. */
5845 maybe_emit_renaming_copy (rtx insn
,
5846 moveop_static_params_p params
)
5848 bool insn_emitted
= false;
5851 /* Bail out early when expression can not be renamed at all. */
5852 if (!EXPR_SEPARABLE_P (params
->c_expr
))
5855 cur_reg
= expr_dest_reg (params
->c_expr
);
5856 gcc_assert (cur_reg
&& params
->dest
&& REG_P (params
->dest
));
5858 /* If original operation has expr and the register chosen for
5859 that expr is not original operation's dest reg, substitute
5860 operation's right hand side with the register chosen. */
5861 if (REGNO (params
->dest
) != REGNO (cur_reg
))
5863 insn_t reg_move_insn
, reg_move_insn_rtx
;
5865 reg_move_insn_rtx
= create_insn_rtx_with_rhs (INSN_VINSN (insn
),
5867 reg_move_insn
= sel_gen_insn_from_rtx_after (reg_move_insn_rtx
,
5871 EXPR_SPEC_DONE_DS (INSN_EXPR (reg_move_insn
)) = 0;
5872 replace_dest_with_reg_in_expr (params
->c_expr
, params
->dest
);
5874 insn_emitted
= true;
5875 params
->was_renamed
= true;
5878 return insn_emitted
;
5881 /* Emit a speculative check for INSN speculated as EXPR if needed.
5882 Return true if we've emitted one. PARAMS is the move_op static
5885 maybe_emit_speculative_check (rtx insn
, expr_t expr
,
5886 moveop_static_params_p params
)
5888 bool insn_emitted
= false;
5892 check_ds
= get_spec_check_type_for_insn (insn
, expr
);
5895 /* A speculation check should be inserted. */
5896 x
= create_speculation_check (params
->c_expr
, check_ds
, insn
);
5897 insn_emitted
= true;
5901 EXPR_SPEC_DONE_DS (INSN_EXPR (insn
)) = 0;
5905 gcc_assert (EXPR_SPEC_DONE_DS (INSN_EXPR (x
)) == 0
5906 && EXPR_SPEC_TO_CHECK_DS (INSN_EXPR (x
)) == 0);
5907 return insn_emitted
;
5910 /* Handle transformations that leave an insn in place of original
5911 insn such as renaming/speculation. Return true if one of such
5912 transformations actually happened, and we have emitted this insn. */
5914 handle_emitting_transformations (rtx insn
, expr_t expr
,
5915 moveop_static_params_p params
)
5917 bool insn_emitted
= false;
5919 insn_emitted
= maybe_emit_renaming_copy (insn
, params
);
5920 insn_emitted
|= maybe_emit_speculative_check (insn
, expr
, params
);
5922 return insn_emitted
;
5925 /* If INSN is the only insn in the basic block (not counting JUMP,
5926 which may be a jump to next insn, and DEBUG_INSNs), we want to
5927 leave a NOP there till the return to fill_insns. */
5930 need_nop_to_preserve_insn_bb (rtx insn
)
5932 insn_t bb_head
, bb_end
, bb_next
, in_next
;
5933 basic_block bb
= BLOCK_FOR_INSN (insn
);
5935 bb_head
= sel_bb_head (bb
);
5936 bb_end
= sel_bb_end (bb
);
5938 if (bb_head
== bb_end
)
5941 while (bb_head
!= bb_end
&& DEBUG_INSN_P (bb_head
))
5942 bb_head
= NEXT_INSN (bb_head
);
5944 if (bb_head
== bb_end
)
5947 while (bb_head
!= bb_end
&& DEBUG_INSN_P (bb_end
))
5948 bb_end
= PREV_INSN (bb_end
);
5950 if (bb_head
== bb_end
)
5953 bb_next
= NEXT_INSN (bb_head
);
5954 while (bb_next
!= bb_end
&& DEBUG_INSN_P (bb_next
))
5955 bb_next
= NEXT_INSN (bb_next
);
5957 if (bb_next
== bb_end
&& JUMP_P (bb_end
))
5960 in_next
= NEXT_INSN (insn
);
5961 while (DEBUG_INSN_P (in_next
))
5962 in_next
= NEXT_INSN (in_next
);
5964 if (IN_CURRENT_FENCE_P (in_next
))
5970 /* Remove INSN from stream. When ONLY_DISCONNECT is true, its data
5971 is not removed but reused when INSN is re-emitted. */
5973 remove_insn_from_stream (rtx insn
, bool only_disconnect
)
5975 /* If there's only one insn in the BB, make sure that a nop is
5976 inserted into it, so the basic block won't disappear when we'll
5977 delete INSN below with sel_remove_insn. It should also survive
5978 till the return to fill_insns. */
5979 if (need_nop_to_preserve_insn_bb (insn
))
5981 insn_t nop
= get_nop_from_pool (insn
);
5982 gcc_assert (INSN_NOP_P (nop
));
5983 VEC_safe_push (insn_t
, heap
, vec_temp_moveop_nops
, nop
);
5986 sel_remove_insn (insn
, only_disconnect
, false);
5989 /* This function is called when original expr is found.
5990 INSN - current insn traversed, EXPR - the corresponding expr found.
5991 LPARAMS is the local parameters of code modion driver, STATIC_PARAMS
5992 is static parameters of move_op. */
5994 move_op_orig_expr_found (insn_t insn
, expr_t expr
,
5995 cmpd_local_params_p lparams ATTRIBUTE_UNUSED
,
5996 void *static_params
)
5998 bool only_disconnect
, insn_emitted
;
5999 moveop_static_params_p params
= (moveop_static_params_p
) static_params
;
6001 copy_expr_onside (params
->c_expr
, INSN_EXPR (insn
));
6002 track_scheduled_insns_and_blocks (insn
);
6003 insn_emitted
= handle_emitting_transformations (insn
, expr
, params
);
6004 only_disconnect
= (params
->uid
== INSN_UID (insn
)
6005 && ! insn_emitted
&& ! EXPR_WAS_CHANGED (expr
));
6007 /* Mark that we've disconnected an insn. */
6008 if (only_disconnect
)
6010 remove_insn_from_stream (insn
, only_disconnect
);
6013 /* The function is called when original expr is found.
6014 INSN - current insn traversed, EXPR - the corresponding expr found,
6015 crosses_call and original_insns in STATIC_PARAMS are updated. */
6017 fur_orig_expr_found (insn_t insn
, expr_t expr ATTRIBUTE_UNUSED
,
6018 cmpd_local_params_p lparams ATTRIBUTE_UNUSED
,
6019 void *static_params
)
6021 fur_static_params_p params
= (fur_static_params_p
) static_params
;
6025 params
->crosses_call
= true;
6027 def_list_add (params
->original_insns
, insn
, params
->crosses_call
);
6029 /* Mark the registers that do not meet the following condition:
6030 (2) not among the live registers of the point
6031 immediately following the first original operation on
6032 a given downward path, except for the original target
6033 register of the operation. */
6034 tmp
= get_clear_regset_from_pool ();
6035 compute_live_below_insn (insn
, tmp
);
6036 AND_COMPL_REG_SET (tmp
, INSN_REG_SETS (insn
));
6037 AND_COMPL_REG_SET (tmp
, INSN_REG_CLOBBERS (insn
));
6038 IOR_REG_SET (params
->used_regs
, tmp
);
6039 return_regset_to_pool (tmp
);
6041 /* (*1) We need to add to USED_REGS registers that are read by
6042 INSN's lhs. This may lead to choosing wrong src register.
6043 E.g. (scheduling const expr enabled):
6045 429: ax=0x0 <- Can't use AX for this expr (0x0)
6052 /* FIXME: see comment above and enable MEM_P
6053 in vinsn_separable_p. */
6054 gcc_assert (!VINSN_SEPARABLE_P (INSN_VINSN (insn
))
6055 || !MEM_P (INSN_LHS (insn
)));
6058 /* This function is called on the ascending pass, before returning from
6059 current basic block. */
6061 move_op_at_first_insn (insn_t insn
, cmpd_local_params_p lparams
,
6062 void *static_params
)
6064 moveop_static_params_p sparams
= (moveop_static_params_p
) static_params
;
6065 basic_block book_block
= NULL
;
6067 /* When we have removed the boundary insn for scheduling, which also
6068 happened to be the end insn in its bb, we don't need to update sets. */
6069 if (!lparams
->removed_last_insn
6071 && sel_bb_head_p (insn
))
6073 /* We should generate bookkeeping code only if we are not at the
6074 top level of the move_op. */
6075 if (sel_num_cfg_preds_gt_1 (insn
))
6076 book_block
= generate_bookkeeping_insn (sparams
->c_expr
,
6077 lparams
->e1
, lparams
->e2
);
6078 /* Update data sets for the current insn. */
6079 update_data_sets (insn
);
6082 /* If bookkeeping code was inserted, we need to update av sets of basic
6083 block that received bookkeeping. After generation of bookkeeping insn,
6084 bookkeeping block does not contain valid av set because we are not following
6085 the original algorithm in every detail with regards to e.g. renaming
6086 simple reg-reg copies. Consider example:
6088 bookkeeping block scheduling fence
6098 We try to schedule insn "r1 := r3" on the current
6099 scheduling fence. Also, note that av set of bookkeeping block
6100 contain both insns "r1 := r2" and "r1 := r3". When the insn has
6101 been scheduled, the CFG is as follows:
6104 bookkeeping block scheduling fence
6114 Here, insn "r1 := r3" was scheduled at the current scheduling point
6115 and bookkeeping code was generated at the bookeeping block. This
6116 way insn "r1 := r2" is no longer available as a whole instruction
6117 (but only as expr) ahead of insn "r1 := r3" in bookkeeping block.
6118 This situation is handled by calling update_data_sets.
6120 Since update_data_sets is called only on the bookkeeping block, and
6121 it also may have predecessors with av_sets, containing instructions that
6122 are no longer available, we save all such expressions that become
6123 unavailable during data sets update on the bookkeeping block in
6124 VEC_BOOKKEEPING_BLOCKED_VINSNS. Later we avoid selecting such
6125 expressions for scheduling. This allows us to avoid recomputation of
6126 av_sets outside the code motion path. */
6129 update_and_record_unavailable_insns (book_block
);
6131 /* If INSN was previously marked for deletion, it's time to do it. */
6132 if (lparams
->removed_last_insn
)
6133 insn
= PREV_INSN (insn
);
6135 /* Do not tidy control flow at the topmost moveop, as we can erroneously
6136 kill a block with a single nop in which the insn should be emitted. */
6138 tidy_control_flow (BLOCK_FOR_INSN (insn
), true);
6141 /* This function is called on the ascending pass, before returning from the
6142 current basic block. */
6144 fur_at_first_insn (insn_t insn
,
6145 cmpd_local_params_p lparams ATTRIBUTE_UNUSED
,
6146 void *static_params ATTRIBUTE_UNUSED
)
6148 gcc_assert (!sel_bb_head_p (insn
) || AV_SET_VALID_P (insn
)
6149 || AV_LEVEL (insn
) == -1);
6152 /* Called on the backward stage of recursion to call moveup_expr for insn
6153 and sparams->c_expr. */
6155 move_op_ascend (insn_t insn
, void *static_params
)
6157 enum MOVEUP_EXPR_CODE res
;
6158 moveop_static_params_p sparams
= (moveop_static_params_p
) static_params
;
6160 if (! INSN_NOP_P (insn
))
6162 res
= moveup_expr_cached (sparams
->c_expr
, insn
, false);
6163 gcc_assert (res
!= MOVEUP_EXPR_NULL
);
6166 /* Update liveness for this insn as it was invalidated. */
6167 update_liveness_on_insn (insn
);
6170 /* This function is called on enter to the basic block.
6171 Returns TRUE if this block already have been visited and
6172 code_motion_path_driver should return 1, FALSE otherwise. */
6174 fur_on_enter (insn_t insn ATTRIBUTE_UNUSED
, cmpd_local_params_p local_params
,
6175 void *static_params
, bool visited_p
)
6177 fur_static_params_p sparams
= (fur_static_params_p
) static_params
;
6181 /* If we have found something below this block, there should be at
6182 least one insn in ORIGINAL_INSNS. */
6183 gcc_assert (*sparams
->original_insns
);
6185 /* Adjust CROSSES_CALL, since we may have come to this block along
6187 DEF_LIST_DEF (*sparams
->original_insns
)->crosses_call
6188 |= sparams
->crosses_call
;
6191 local_params
->old_original_insns
= *sparams
->original_insns
;
6196 /* Same as above but for move_op. */
6198 move_op_on_enter (insn_t insn ATTRIBUTE_UNUSED
,
6199 cmpd_local_params_p local_params ATTRIBUTE_UNUSED
,
6200 void *static_params ATTRIBUTE_UNUSED
, bool visited_p
)
6207 /* This function is called while descending current basic block if current
6208 insn is not the original EXPR we're searching for.
6210 Return value: FALSE, if code_motion_path_driver should perform a local
6211 cleanup and return 0 itself;
6212 TRUE, if code_motion_path_driver should continue. */
6214 move_op_orig_expr_not_found (insn_t insn
, av_set_t orig_ops ATTRIBUTE_UNUSED
,
6215 void *static_params
)
6217 moveop_static_params_p sparams
= (moveop_static_params_p
) static_params
;
6219 #ifdef ENABLE_CHECKING
6220 sparams
->failed_insn
= insn
;
6223 /* If we're scheduling separate expr, in order to generate correct code
6224 we need to stop the search at bookkeeping code generated with the
6225 same destination register or memory. */
6226 if (lhs_of_insn_equals_to_dest_p (insn
, sparams
->dest
))
6231 /* This function is called while descending current basic block if current
6232 insn is not the original EXPR we're searching for.
6234 Return value: TRUE (code_motion_path_driver should continue). */
6236 fur_orig_expr_not_found (insn_t insn
, av_set_t orig_ops
, void *static_params
)
6240 av_set_iterator avi
;
6241 fur_static_params_p sparams
= (fur_static_params_p
) static_params
;
6244 sparams
->crosses_call
= true;
6245 else if (DEBUG_INSN_P (insn
))
6248 /* If current insn we are looking at cannot be executed together
6249 with original insn, then we can skip it safely.
6251 Example: ORIG_OPS = { (p6) r14 = sign_extend (r15); }
6252 INSN = (!p6) r14 = r14 + 1;
6254 Here we can schedule ORIG_OP with lhs = r14, though only
6255 looking at the set of used and set registers of INSN we must
6256 forbid it. So, add set/used in INSN registers to the
6257 untouchable set only if there is an insn in ORIG_OPS that can
6260 FOR_EACH_EXPR (r
, avi
, orig_ops
)
6261 if (!sched_insns_conditions_mutex_p (insn
, EXPR_INSN_RTX (r
)))
6267 /* Mark all registers that do not meet the following condition:
6268 (1) Not set or read on any path from xi to an instance of the
6269 original operation. */
6272 IOR_REG_SET (sparams
->used_regs
, INSN_REG_SETS (insn
));
6273 IOR_REG_SET (sparams
->used_regs
, INSN_REG_USES (insn
));
6274 IOR_REG_SET (sparams
->used_regs
, INSN_REG_CLOBBERS (insn
));
6280 /* Hooks and data to perform move_op operations with code_motion_path_driver. */
6281 struct code_motion_path_driver_info_def move_op_hooks
= {
6283 move_op_orig_expr_found
,
6284 move_op_orig_expr_not_found
,
6285 move_op_merge_succs
,
6286 move_op_after_merge_succs
,
6288 move_op_at_first_insn
,
6293 /* Hooks and data to perform find_used_regs operations
6294 with code_motion_path_driver. */
6295 struct code_motion_path_driver_info_def fur_hooks
= {
6297 fur_orig_expr_found
,
6298 fur_orig_expr_not_found
,
6300 NULL
, /* fur_after_merge_succs */
6301 NULL
, /* fur_ascend */
6307 /* Traverse all successors of INSN. For each successor that is SUCCS_NORMAL
6308 code_motion_path_driver is called recursively. Original operation
6309 was found at least on one path that is starting with one of INSN's
6310 successors (this fact is asserted). ORIG_OPS is expressions we're looking
6311 for, PATH is the path we've traversed, STATIC_PARAMS is the parameters
6312 of either move_op or find_used_regs depending on the caller.
6314 Return 0 if we haven't found expression, 1 if we found it, -1 if we don't
6315 know for sure at this point. */
6317 code_motion_process_successors (insn_t insn
, av_set_t orig_ops
,
6318 ilist_t path
, void *static_params
)
6321 succ_iterator succ_i
;
6327 struct cmpd_local_params lparams
;
6330 lparams
.c_expr_local
= &_x
;
6331 lparams
.c_expr_merged
= NULL
;
6333 /* We need to process only NORMAL succs for move_op, and collect live
6334 registers from ALL branches (including those leading out of the
6335 region) for find_used_regs.
6337 In move_op, there can be a case when insn's bb number has changed
6338 due to created bookkeeping. This happens very rare, as we need to
6339 move expression from the beginning to the end of the same block.
6340 Rescan successors in this case. */
6343 bb
= BLOCK_FOR_INSN (insn
);
6344 old_index
= bb
->index
;
6345 old_succs
= EDGE_COUNT (bb
->succs
);
6347 FOR_EACH_SUCC_1 (succ
, succ_i
, insn
, code_motion_path_driver_info
->succ_flags
)
6351 lparams
.e1
= succ_i
.e1
;
6352 lparams
.e2
= succ_i
.e2
;
6354 /* Go deep into recursion only for NORMAL edges (non-backedges within the
6356 if (succ_i
.current_flags
== SUCCS_NORMAL
)
6357 b
= code_motion_path_driver (succ
, orig_ops
, path
, &lparams
,
6362 /* Merge c_expres found or unify live register sets from different
6364 code_motion_path_driver_info
->merge_succs (insn
, succ
, b
, &lparams
,
6368 else if (b
== -1 && res
!= 1)
6371 /* We have simplified the control flow below this point. In this case,
6372 the iterator becomes invalid. We need to try again. */
6373 if (BLOCK_FOR_INSN (insn
)->index
!= old_index
6374 || EDGE_COUNT (bb
->succs
) != old_succs
)
6376 insn
= sel_bb_end (BLOCK_FOR_INSN (insn
));
6381 #ifdef ENABLE_CHECKING
6382 /* Here, RES==1 if original expr was found at least for one of the
6383 successors. After the loop, RES may happen to have zero value
6384 only if at some point the expr searched is present in av_set, but is
6385 not found below. In most cases, this situation is an error.
6386 The exception is when the original operation is blocked by
6387 bookkeeping generated for another fence or for another path in current
6389 gcc_assert (res
== 1
6391 && av_set_could_be_blocked_by_bookkeeping_p (orig_ops
,
6396 /* Merge data, clean up, etc. */
6397 if (res
!= -1 && code_motion_path_driver_info
->after_merge_succs
)
6398 code_motion_path_driver_info
->after_merge_succs (&lparams
, static_params
);
6404 /* Perform a cleanup when the driver is about to terminate. ORIG_OPS_P
6405 is the pointer to the av set with expressions we were looking for,
6406 PATH_P is the pointer to the traversed path. */
6408 code_motion_path_driver_cleanup (av_set_t
*orig_ops_p
, ilist_t
*path_p
)
6410 ilist_remove (path_p
);
6411 av_set_clear (orig_ops_p
);
6414 /* The driver function that implements move_op or find_used_regs
6415 functionality dependent whether code_motion_path_driver_INFO is set to
6416 &MOVE_OP_HOOKS or &FUR_HOOKS. This function implements the common parts
6417 of code (CFG traversal etc) that are shared among both functions. INSN
6418 is the insn we're starting the search from, ORIG_OPS are the expressions
6419 we're searching for, PATH is traversed path, LOCAL_PARAMS_IN are local
6420 parameters of the driver, and STATIC_PARAMS are static parameters of
6423 Returns whether original instructions were found. Note that top-level
6424 code_motion_path_driver always returns true. */
6426 code_motion_path_driver (insn_t insn
, av_set_t orig_ops
, ilist_t path
,
6427 cmpd_local_params_p local_params_in
,
6428 void *static_params
)
6431 basic_block bb
= BLOCK_FOR_INSN (insn
);
6432 insn_t first_insn
, bb_tail
, before_first
;
6433 bool removed_last_insn
= false;
6435 if (sched_verbose
>= 6)
6437 sel_print ("%s (", code_motion_path_driver_info
->routine_name
);
6440 dump_av_set (orig_ops
);
6444 gcc_assert (orig_ops
);
6446 /* If no original operations exist below this insn, return immediately. */
6447 if (is_ineligible_successor (insn
, path
))
6449 if (sched_verbose
>= 6)
6450 sel_print ("Insn %d is ineligible successor\n", INSN_UID (insn
));
6454 /* The block can have invalid av set, in which case it was created earlier
6455 during move_op. Return immediately. */
6456 if (sel_bb_head_p (insn
))
6458 if (! AV_SET_VALID_P (insn
))
6460 if (sched_verbose
>= 6)
6461 sel_print ("Returned from block %d as it had invalid av set\n",
6466 if (bitmap_bit_p (code_motion_visited_blocks
, bb
->index
))
6468 /* We have already found an original operation on this branch, do not
6469 go any further and just return TRUE here. If we don't stop here,
6470 function can have exponential behaviour even on the small code
6471 with many different paths (e.g. with data speculation and
6472 recovery blocks). */
6473 if (sched_verbose
>= 6)
6474 sel_print ("Block %d already visited in this traversal\n", bb
->index
);
6475 if (code_motion_path_driver_info
->on_enter
)
6476 return code_motion_path_driver_info
->on_enter (insn
,
6483 if (code_motion_path_driver_info
->on_enter
)
6484 code_motion_path_driver_info
->on_enter (insn
, local_params_in
,
6485 static_params
, false);
6486 orig_ops
= av_set_copy (orig_ops
);
6488 /* Filter the orig_ops set. */
6489 if (AV_SET_VALID_P (insn
))
6490 av_set_code_motion_filter (&orig_ops
, AV_SET (insn
));
6492 /* If no more original ops, return immediately. */
6495 if (sched_verbose
>= 6)
6496 sel_print ("No intersection with av set of block %d\n", bb
->index
);
6500 /* For non-speculative insns we have to leave only one form of the
6501 original operation, because if we don't, we may end up with
6502 different C_EXPRes and, consequently, with bookkeepings for different
6503 expression forms along the same code motion path. That may lead to
6504 generation of incorrect code. So for each code motion we stick to
6505 the single form of the instruction, except for speculative insns
6506 which we need to keep in different forms with all speculation
6508 av_set_leave_one_nonspec (&orig_ops
);
6510 /* It is not possible that all ORIG_OPS are filtered out. */
6511 gcc_assert (orig_ops
);
6513 /* It is enough to place only heads and tails of visited basic blocks into
6515 ilist_add (&path
, insn
);
6517 bb_tail
= sel_bb_end (bb
);
6519 /* Descend the basic block in search of the original expr; this part
6520 corresponds to the part of the original move_op procedure executed
6521 before the recursive call. */
6524 /* Look at the insn and decide if it could be an ancestor of currently
6525 scheduling operation. If it is so, then the insn "dest = op" could
6526 either be replaced with "dest = reg", because REG now holds the result
6527 of OP, or just removed, if we've scheduled the insn as a whole.
6529 If this insn doesn't contain currently scheduling OP, then proceed
6530 with searching and look at its successors. Operations we're searching
6531 for could have changed when moving up through this insn via
6532 substituting. In this case, perform unsubstitution on them first.
6534 When traversing the DAG below this insn is finished, insert
6535 bookkeeping code, if the insn is a joint point, and remove
6538 expr
= av_set_lookup (orig_ops
, INSN_VINSN (insn
));
6541 insn_t last_insn
= PREV_INSN (insn
);
6543 /* We have found the original operation. */
6544 if (sched_verbose
>= 6)
6545 sel_print ("Found original operation at insn %d\n", INSN_UID (insn
));
6547 code_motion_path_driver_info
->orig_expr_found
6548 (insn
, expr
, local_params_in
, static_params
);
6550 /* Step back, so on the way back we'll start traversing from the
6551 previous insn (or we'll see that it's bb_note and skip that
6553 if (insn
== first_insn
)
6555 first_insn
= NEXT_INSN (last_insn
);
6556 removed_last_insn
= sel_bb_end_p (last_insn
);
6563 /* We haven't found the original expr, continue descending the basic
6565 if (code_motion_path_driver_info
->orig_expr_not_found
6566 (insn
, orig_ops
, static_params
))
6568 /* Av set ops could have been changed when moving through this
6569 insn. To find them below it, we have to un-substitute them. */
6570 undo_transformations (&orig_ops
, insn
);
6574 /* Clean up and return, if the hook tells us to do so. It may
6575 happen if we've encountered the previously created
6577 code_motion_path_driver_cleanup (&orig_ops
, &path
);
6581 gcc_assert (orig_ops
);
6584 /* Stop at insn if we got to the end of BB. */
6585 if (insn
== bb_tail
)
6588 insn
= NEXT_INSN (insn
);
6591 /* Here INSN either points to the insn before the original insn (may be
6592 bb_note, if original insn was a bb_head) or to the bb_end. */
6596 rtx last_insn
= PREV_INSN (insn
);
6599 gcc_assert (insn
== sel_bb_end (bb
));
6601 /* Add bb tail to PATH (but it doesn't make any sense if it's a bb_head -
6602 it's already in PATH then). */
6603 if (insn
!= first_insn
)
6605 ilist_add (&path
, insn
);
6606 added_to_path
= true;
6609 added_to_path
= false;
6611 /* Process_successors should be able to find at least one
6612 successor for which code_motion_path_driver returns TRUE. */
6613 res
= code_motion_process_successors (insn
, orig_ops
,
6614 path
, static_params
);
6616 /* Jump in the end of basic block could have been removed or replaced
6617 during code_motion_process_successors, so recompute insn as the
6619 if (NEXT_INSN (last_insn
) != insn
)
6621 insn
= sel_bb_end (bb
);
6622 first_insn
= sel_bb_head (bb
);
6625 /* Remove bb tail from path. */
6627 ilist_remove (&path
);
6631 /* This is the case when one of the original expr is no longer available
6632 due to bookkeeping created on this branch with the same register.
6633 In the original algorithm, which doesn't have update_data_sets call
6634 on a bookkeeping block, it would simply result in returning
6635 FALSE when we've encountered a previously generated bookkeeping
6636 insn in moveop_orig_expr_not_found. */
6637 code_motion_path_driver_cleanup (&orig_ops
, &path
);
6642 /* Don't need it any more. */
6643 av_set_clear (&orig_ops
);
6645 /* Backward pass: now, when we have C_EXPR computed, we'll drag it to
6646 the beginning of the basic block. */
6647 before_first
= PREV_INSN (first_insn
);
6648 while (insn
!= before_first
)
6650 if (code_motion_path_driver_info
->ascend
)
6651 code_motion_path_driver_info
->ascend (insn
, static_params
);
6653 insn
= PREV_INSN (insn
);
6656 /* Now we're at the bb head. */
6658 ilist_remove (&path
);
6659 local_params_in
->removed_last_insn
= removed_last_insn
;
6660 code_motion_path_driver_info
->at_first_insn (insn
, local_params_in
, static_params
);
6662 /* This should be the very last operation as at bb head we could change
6663 the numbering by creating bookkeeping blocks. */
6664 if (removed_last_insn
)
6665 insn
= PREV_INSN (insn
);
6666 bitmap_set_bit (code_motion_visited_blocks
, BLOCK_FOR_INSN (insn
)->index
);
6670 /* Move up the operations from ORIG_OPS set traversing the dag starting
6671 from INSN. PATH represents the edges traversed so far.
6672 DEST is the register chosen for scheduling the current expr. Insert
6673 bookkeeping code in the join points. EXPR_VLIW is the chosen expression,
6674 C_EXPR is how it looks like at the given cfg point.
6675 Set *SHOULD_MOVE to indicate whether we have only disconnected
6676 one of the insns found.
6678 Returns whether original instructions were found, which is asserted
6679 to be true in the caller. */
6681 move_op (insn_t insn
, av_set_t orig_ops
, expr_t expr_vliw
,
6682 rtx dest
, expr_t c_expr
, bool *should_move
)
6684 struct moveop_static_params sparams
;
6685 struct cmpd_local_params lparams
;
6688 /* Init params for code_motion_path_driver. */
6689 sparams
.dest
= dest
;
6690 sparams
.c_expr
= c_expr
;
6691 sparams
.uid
= INSN_UID (EXPR_INSN_RTX (expr_vliw
));
6692 #ifdef ENABLE_CHECKING
6693 sparams
.failed_insn
= NULL
;
6695 sparams
.was_renamed
= false;
6698 /* We haven't visited any blocks yet. */
6699 bitmap_clear (code_motion_visited_blocks
);
6701 /* Set appropriate hooks and data. */
6702 code_motion_path_driver_info
= &move_op_hooks
;
6703 res
= code_motion_path_driver (insn
, orig_ops
, NULL
, &lparams
, &sparams
);
6705 gcc_assert (res
!= -1);
6707 if (sparams
.was_renamed
)
6708 EXPR_WAS_RENAMED (expr_vliw
) = true;
6710 *should_move
= (sparams
.uid
== -1);
6716 /* Functions that work with regions. */
6718 /* Current number of seqno used in init_seqno and init_seqno_1. */
6719 static int cur_seqno
;
6721 /* A helper for init_seqno. Traverse the region starting from BB and
6722 compute seqnos for visited insns, marking visited bbs in VISITED_BBS.
6723 Clear visited blocks from BLOCKS_TO_RESCHEDULE. */
6725 init_seqno_1 (basic_block bb
, sbitmap visited_bbs
, bitmap blocks_to_reschedule
)
6727 int bbi
= BLOCK_TO_BB (bb
->index
);
6728 insn_t insn
, note
= bb_note (bb
);
6732 SET_BIT (visited_bbs
, bbi
);
6733 if (blocks_to_reschedule
)
6734 bitmap_clear_bit (blocks_to_reschedule
, bb
->index
);
6736 FOR_EACH_SUCC_1 (succ_insn
, si
, BB_END (bb
),
6737 SUCCS_NORMAL
| SUCCS_SKIP_TO_LOOP_EXITS
)
6739 basic_block succ
= BLOCK_FOR_INSN (succ_insn
);
6740 int succ_bbi
= BLOCK_TO_BB (succ
->index
);
6742 gcc_assert (in_current_region_p (succ
));
6744 if (!TEST_BIT (visited_bbs
, succ_bbi
))
6746 gcc_assert (succ_bbi
> bbi
);
6748 init_seqno_1 (succ
, visited_bbs
, blocks_to_reschedule
);
6750 else if (blocks_to_reschedule
)
6751 bitmap_set_bit (forced_ebb_heads
, succ
->index
);
6754 for (insn
= BB_END (bb
); insn
!= note
; insn
= PREV_INSN (insn
))
6755 INSN_SEQNO (insn
) = cur_seqno
--;
6758 /* Initialize seqnos for the current region. BLOCKS_TO_RESCHEDULE contains
6759 blocks on which we're rescheduling when pipelining, FROM is the block where
6760 traversing region begins (it may not be the head of the region when
6761 pipelining, but the head of the loop instead).
6763 Returns the maximal seqno found. */
6765 init_seqno (bitmap blocks_to_reschedule
, basic_block from
)
6767 sbitmap visited_bbs
;
6771 visited_bbs
= sbitmap_alloc (current_nr_blocks
);
6773 if (blocks_to_reschedule
)
6775 sbitmap_ones (visited_bbs
);
6776 EXECUTE_IF_SET_IN_BITMAP (blocks_to_reschedule
, 0, bbi
, bi
)
6778 gcc_assert (BLOCK_TO_BB (bbi
) < current_nr_blocks
);
6779 RESET_BIT (visited_bbs
, BLOCK_TO_BB (bbi
));
6784 sbitmap_zero (visited_bbs
);
6785 from
= EBB_FIRST_BB (0);
6788 cur_seqno
= sched_max_luid
- 1;
6789 init_seqno_1 (from
, visited_bbs
, blocks_to_reschedule
);
6791 /* cur_seqno may be positive if the number of instructions is less than
6792 sched_max_luid - 1 (when rescheduling or if some instructions have been
6793 removed by the call to purge_empty_blocks in sel_sched_region_1). */
6794 gcc_assert (cur_seqno
>= 0);
6796 sbitmap_free (visited_bbs
);
6797 return sched_max_luid
- 1;
6800 /* Initialize scheduling parameters for current region. */
6802 sel_setup_region_sched_flags (void)
6804 enable_schedule_as_rhs_p
= 1;
6806 pipelining_p
= (bookkeeping_p
6807 && (flag_sel_sched_pipelining
!= 0)
6808 && current_loop_nest
!= NULL
6809 && loop_has_exit_edges (current_loop_nest
));
6810 max_insns_to_rename
= PARAM_VALUE (PARAM_SELSCHED_INSNS_TO_RENAME
);
6814 /* Return true if all basic blocks of current region are empty. */
6816 current_region_empty_p (void)
6819 for (i
= 0; i
< current_nr_blocks
; i
++)
6820 if (! sel_bb_empty_p (BASIC_BLOCK (BB_TO_BLOCK (i
))))
6826 /* Prepare and verify loop nest for pipelining. */
6828 setup_current_loop_nest (int rgn
, bb_vec_t
*bbs
)
6830 current_loop_nest
= get_loop_nest_for_rgn (rgn
);
6832 if (!current_loop_nest
)
6835 /* If this loop has any saved loop preheaders from nested loops,
6836 add these basic blocks to the current region. */
6837 sel_add_loop_preheaders (bbs
);
6839 /* Check that we're starting with a valid information. */
6840 gcc_assert (loop_latch_edge (current_loop_nest
));
6841 gcc_assert (LOOP_MARKED_FOR_PIPELINING_P (current_loop_nest
));
6844 /* Compute instruction priorities for current region. */
6846 sel_compute_priorities (int rgn
)
6848 sched_rgn_compute_dependencies (rgn
);
6850 /* Compute insn priorities in haifa style. Then free haifa style
6851 dependencies that we've calculated for this. */
6852 compute_priorities ();
6854 if (sched_verbose
>= 5)
6855 debug_rgn_dependencies (0);
6860 /* Init scheduling data for RGN. Returns true when this region should not
6863 sel_region_init (int rgn
)
6868 rgn_setup_region (rgn
);
6870 /* Even if sched_is_disabled_for_current_region_p() is true, we still
6871 do region initialization here so the region can be bundled correctly,
6872 but we'll skip the scheduling in sel_sched_region (). */
6873 if (current_region_empty_p ())
6876 bbs
= VEC_alloc (basic_block
, heap
, current_nr_blocks
);
6878 for (i
= 0; i
< current_nr_blocks
; i
++)
6879 VEC_quick_push (basic_block
, bbs
, BASIC_BLOCK (BB_TO_BLOCK (i
)));
6883 if (flag_sel_sched_pipelining
)
6884 setup_current_loop_nest (rgn
, &bbs
);
6886 sel_setup_region_sched_flags ();
6888 /* Initialize luids and dependence analysis which both sel-sched and haifa
6890 sched_init_luids (bbs
);
6891 sched_deps_init (false);
6893 /* Initialize haifa data. */
6894 rgn_setup_sched_infos ();
6895 sel_set_sched_flags ();
6896 haifa_init_h_i_d (bbs
);
6898 sel_compute_priorities (rgn
);
6899 init_deps_global ();
6901 /* Main initialization. */
6902 sel_setup_sched_infos ();
6903 sel_init_global_and_expr (bbs
);
6905 VEC_free (basic_block
, heap
, bbs
);
6907 blocks_to_reschedule
= BITMAP_ALLOC (NULL
);
6909 /* Init correct liveness sets on each instruction of a single-block loop.
6910 This is the only situation when we can't update liveness when calling
6911 compute_live for the first insn of the loop. */
6912 if (current_loop_nest
)
6914 int header
= (sel_is_loop_preheader_p (BASIC_BLOCK (BB_TO_BLOCK (0)))
6918 if (current_nr_blocks
== header
+ 1)
6919 update_liveness_on_insn
6920 (sel_bb_head (BASIC_BLOCK (BB_TO_BLOCK (header
))));
6923 /* Set hooks so that no newly generated insn will go out unnoticed. */
6924 sel_register_cfg_hooks ();
6926 /* !!! We call target.sched.init () for the whole region, but we invoke
6927 targetm.sched.finish () for every ebb. */
6928 if (targetm
.sched
.init
)
6929 /* None of the arguments are actually used in any target. */
6930 targetm
.sched
.init (sched_dump
, sched_verbose
, -1);
6932 first_emitted_uid
= get_max_uid () + 1;
6933 preheader_removed
= false;
6935 /* Reset register allocation ticks array. */
6936 memset (reg_rename_tick
, 0, sizeof reg_rename_tick
);
6937 reg_rename_this_tick
= 0;
6939 bitmap_initialize (forced_ebb_heads
, 0);
6940 bitmap_clear (forced_ebb_heads
);
6943 current_copies
= BITMAP_ALLOC (NULL
);
6944 current_originators
= BITMAP_ALLOC (NULL
);
6945 code_motion_visited_blocks
= BITMAP_ALLOC (NULL
);
6950 /* Simplify insns after the scheduling. */
6952 simplify_changed_insns (void)
6956 for (i
= 0; i
< current_nr_blocks
; i
++)
6958 basic_block bb
= BASIC_BLOCK (BB_TO_BLOCK (i
));
6961 FOR_BB_INSNS (bb
, insn
)
6964 expr_t expr
= INSN_EXPR (insn
);
6966 if (EXPR_WAS_SUBSTITUTED (expr
))
6967 validate_simplify_insn (insn
);
6972 /* Find boundaries of the EBB starting from basic block BB, marking blocks of
6973 this EBB in SCHEDULED_BLOCKS and appropriately filling in HEAD, TAIL,
6974 PREV_HEAD, and NEXT_TAIL fields of CURRENT_SCHED_INFO structure. */
6976 find_ebb_boundaries (basic_block bb
, bitmap scheduled_blocks
)
6979 basic_block bb1
= bb
;
6980 if (sched_verbose
>= 2)
6981 sel_print ("Finishing schedule in bbs: ");
6985 bitmap_set_bit (scheduled_blocks
, BLOCK_TO_BB (bb1
->index
));
6987 if (sched_verbose
>= 2)
6988 sel_print ("%d; ", bb1
->index
);
6990 while (!bb_ends_ebb_p (bb1
) && (bb1
= bb_next_bb (bb1
)));
6992 if (sched_verbose
>= 2)
6995 get_ebb_head_tail (bb
, bb1
, &head
, &tail
);
6997 current_sched_info
->head
= head
;
6998 current_sched_info
->tail
= tail
;
6999 current_sched_info
->prev_head
= PREV_INSN (head
);
7000 current_sched_info
->next_tail
= NEXT_INSN (tail
);
7003 /* Regenerate INSN_SCHED_CYCLEs for insns of current EBB. */
7005 reset_sched_cycles_in_current_ebb (void)
7008 int haifa_last_clock
= -1;
7009 int haifa_clock
= 0;
7010 int issued_insns
= 0;
7013 if (targetm
.sched
.init
)
7015 /* None of the arguments are actually used in any target.
7016 NB: We should have md_reset () hook for cases like this. */
7017 targetm
.sched
.init (sched_dump
, sched_verbose
, -1);
7020 state_reset (curr_state
);
7021 advance_state (curr_state
);
7023 for (insn
= current_sched_info
->head
;
7024 insn
!= current_sched_info
->next_tail
;
7025 insn
= NEXT_INSN (insn
))
7027 int cost
, haifa_cost
;
7029 bool asm_p
, real_insn
, after_stall
, all_issued
;
7036 real_insn
= recog_memoized (insn
) >= 0;
7037 clock
= INSN_SCHED_CYCLE (insn
);
7039 cost
= clock
- last_clock
;
7041 /* Initialize HAIFA_COST. */
7044 asm_p
= INSN_ASM_P (insn
);
7047 /* This is asm insn which *had* to be scheduled first
7051 /* This is a use/clobber insn. It should not change
7056 haifa_cost
= estimate_insn_cost (insn
, curr_state
);
7058 /* Stall for whatever cycles we've stalled before. */
7060 if (INSN_AFTER_STALL_P (insn
) && cost
> haifa_cost
)
7065 all_issued
= issued_insns
== issue_rate
;
7066 if (haifa_cost
== 0 && all_issued
)
7072 while (haifa_cost
--)
7074 advance_state (curr_state
);
7078 if (sched_verbose
>= 2)
7080 sel_print ("advance_state (state_transition)\n");
7081 debug_state (curr_state
);
7084 /* The DFA may report that e.g. insn requires 2 cycles to be
7085 issued, but on the next cycle it says that insn is ready
7086 to go. Check this here. */
7090 && estimate_insn_cost (insn
, curr_state
) == 0)
7093 /* When the data dependency stall is longer than the DFA stall,
7094 and when we have issued exactly issue_rate insns and stalled,
7095 it could be that after this longer stall the insn will again
7096 become unavailable to the DFA restrictions. Looks strange
7097 but happens e.g. on x86-64. So recheck DFA on the last
7099 if ((after_stall
|| all_issued
)
7102 haifa_cost
= estimate_insn_cost (insn
, curr_state
);
7106 if (sched_verbose
>= 2)
7107 sel_print ("haifa clock: %d\n", haifa_clock
);
7110 gcc_assert (haifa_cost
== 0);
7112 if (sched_verbose
>= 2)
7113 sel_print ("Haifa cost for insn %d: %d\n", INSN_UID (insn
), haifa_cost
);
7115 if (targetm
.sched
.dfa_new_cycle
)
7116 while (targetm
.sched
.dfa_new_cycle (sched_dump
, sched_verbose
, insn
,
7117 haifa_last_clock
, haifa_clock
,
7120 advance_state (curr_state
);
7123 if (sched_verbose
>= 2)
7125 sel_print ("advance_state (dfa_new_cycle)\n");
7126 debug_state (curr_state
);
7127 sel_print ("haifa clock: %d\n", haifa_clock
+ 1);
7133 cost
= state_transition (curr_state
, insn
);
7136 if (sched_verbose
>= 2)
7138 sel_print ("scheduled insn %d, clock %d\n", INSN_UID (insn
),
7140 debug_state (curr_state
);
7142 gcc_assert (cost
< 0);
7145 if (targetm
.sched
.variable_issue
)
7146 targetm
.sched
.variable_issue (sched_dump
, sched_verbose
, insn
, 0);
7148 INSN_SCHED_CYCLE (insn
) = haifa_clock
;
7151 haifa_last_clock
= haifa_clock
;
7155 /* Put TImode markers on insns starting a new issue group. */
7159 int last_clock
= -1;
7162 for (insn
= current_sched_info
->head
; insn
!= current_sched_info
->next_tail
;
7163 insn
= NEXT_INSN (insn
))
7170 clock
= INSN_SCHED_CYCLE (insn
);
7171 cost
= (last_clock
== -1) ? 1 : clock
- last_clock
;
7173 gcc_assert (cost
>= 0);
7176 && GET_CODE (PATTERN (insn
)) != USE
7177 && GET_CODE (PATTERN (insn
)) != CLOBBER
)
7179 if (reload_completed
&& cost
> 0)
7180 PUT_MODE (insn
, TImode
);
7185 if (sched_verbose
>= 2)
7186 sel_print ("Cost for insn %d is %d\n", INSN_UID (insn
), cost
);
7190 /* Perform MD_FINISH on EBBs comprising current region. When
7191 RESET_SCHED_CYCLES_P is true, run a pass emulating the scheduler
7192 to produce correct sched cycles on insns. */
7194 sel_region_target_finish (bool reset_sched_cycles_p
)
7197 bitmap scheduled_blocks
= BITMAP_ALLOC (NULL
);
7199 for (i
= 0; i
< current_nr_blocks
; i
++)
7201 if (bitmap_bit_p (scheduled_blocks
, i
))
7204 /* While pipelining outer loops, skip bundling for loop
7205 preheaders. Those will be rescheduled in the outer loop. */
7206 if (sel_is_loop_preheader_p (EBB_FIRST_BB (i
)))
7209 find_ebb_boundaries (EBB_FIRST_BB (i
), scheduled_blocks
);
7211 if (no_real_insns_p (current_sched_info
->head
, current_sched_info
->tail
))
7214 if (reset_sched_cycles_p
)
7215 reset_sched_cycles_in_current_ebb ();
7217 if (targetm
.sched
.init
)
7218 targetm
.sched
.init (sched_dump
, sched_verbose
, -1);
7222 if (targetm
.sched
.finish
)
7224 targetm
.sched
.finish (sched_dump
, sched_verbose
);
7226 /* Extend luids so that insns generated by the target will
7228 sched_extend_luids ();
7232 BITMAP_FREE (scheduled_blocks
);
7235 /* Free the scheduling data for the current region. When RESET_SCHED_CYCLES_P
7236 is true, make an additional pass emulating scheduler to get correct insn
7237 cycles for md_finish calls. */
7239 sel_region_finish (bool reset_sched_cycles_p
)
7241 simplify_changed_insns ();
7242 sched_finish_ready_list ();
7245 /* Free the vectors. */
7247 VEC_free (expr_t
, heap
, vec_av_set
);
7248 BITMAP_FREE (current_copies
);
7249 BITMAP_FREE (current_originators
);
7250 BITMAP_FREE (code_motion_visited_blocks
);
7251 vinsn_vec_free (&vec_bookkeeping_blocked_vinsns
);
7252 vinsn_vec_free (&vec_target_unavailable_vinsns
);
7254 /* If LV_SET of the region head should be updated, do it now because
7255 there will be no other chance. */
7260 FOR_EACH_SUCC_1 (insn
, si
, bb_note (EBB_FIRST_BB (0)),
7261 SUCCS_NORMAL
| SUCCS_SKIP_TO_LOOP_EXITS
)
7263 basic_block bb
= BLOCK_FOR_INSN (insn
);
7265 if (!BB_LV_SET_VALID_P (bb
))
7266 compute_live (insn
);
7270 /* Emulate the Haifa scheduler for bundling. */
7271 if (reload_completed
)
7272 sel_region_target_finish (reset_sched_cycles_p
);
7274 sel_finish_global_and_expr ();
7276 bitmap_clear (forced_ebb_heads
);
7280 finish_deps_global ();
7281 sched_finish_luids ();
7282 VEC_free (haifa_deps_insn_data_def
, heap
, h_d_i_d
);
7285 BITMAP_FREE (blocks_to_reschedule
);
7287 sel_unregister_cfg_hooks ();
7293 /* Functions that implement the scheduler driver. */
7295 /* Schedule a parallel instruction group on each of FENCES. MAX_SEQNO
7296 is the current maximum seqno. SCHEDULED_INSNS_TAILPP is the list
7297 of insns scheduled -- these would be postprocessed later. */
7299 schedule_on_fences (flist_t fences
, int max_seqno
,
7300 ilist_t
**scheduled_insns_tailpp
)
7302 flist_t old_fences
= fences
;
7304 if (sched_verbose
>= 1)
7306 sel_print ("\nScheduling on fences: ");
7307 dump_flist (fences
);
7311 scheduled_something_on_previous_fence
= false;
7312 for (; fences
; fences
= FLIST_NEXT (fences
))
7314 fence_t fence
= NULL
;
7317 bool first_p
= true;
7319 /* Choose the next fence group to schedule.
7320 The fact that insn can be scheduled only once
7321 on the cycle is guaranteed by two properties:
7322 1. seqnos of parallel groups decrease with each iteration.
7323 2. If is_ineligible_successor () sees the larger seqno, it
7324 checks if candidate insn is_in_current_fence_p (). */
7325 for (fences2
= old_fences
; fences2
; fences2
= FLIST_NEXT (fences2
))
7327 fence_t f
= FLIST_FENCE (fences2
);
7329 if (!FENCE_PROCESSED_P (f
))
7331 int i
= INSN_SEQNO (FENCE_INSN (f
));
7333 if (first_p
|| i
> seqno
)
7340 /* ??? Seqnos of different groups should be different. */
7341 gcc_assert (1 || i
!= seqno
);
7347 /* As FENCE is nonnull, SEQNO is initialized. */
7348 seqno
-= max_seqno
+ 1;
7349 fill_insns (fence
, seqno
, scheduled_insns_tailpp
);
7350 FENCE_PROCESSED_P (fence
) = true;
7353 /* All av_sets are invalidated by GLOBAL_LEVEL increase, thus we
7354 don't need to keep bookkeeping-invalidated and target-unavailable
7356 vinsn_vec_clear (&vec_bookkeeping_blocked_vinsns
);
7357 vinsn_vec_clear (&vec_target_unavailable_vinsns
);
7360 /* Calculate MIN_SEQNO and MAX_SEQNO. */
7362 find_min_max_seqno (flist_t fences
, int *min_seqno
, int *max_seqno
)
7364 *min_seqno
= *max_seqno
= INSN_SEQNO (FENCE_INSN (FLIST_FENCE (fences
)));
7366 /* The first element is already processed. */
7367 while ((fences
= FLIST_NEXT (fences
)))
7369 int seqno
= INSN_SEQNO (FENCE_INSN (FLIST_FENCE (fences
)));
7371 if (*min_seqno
> seqno
)
7373 else if (*max_seqno
< seqno
)
7378 /* Calculate new fences from FENCES. */
7380 calculate_new_fences (flist_t fences
, int orig_max_seqno
)
7382 flist_t old_fences
= fences
;
7383 struct flist_tail_def _new_fences
, *new_fences
= &_new_fences
;
7385 flist_tail_init (new_fences
);
7386 for (; fences
; fences
= FLIST_NEXT (fences
))
7388 fence_t fence
= FLIST_FENCE (fences
);
7391 if (!FENCE_BNDS (fence
))
7393 /* This fence doesn't have any successors. */
7394 if (!FENCE_SCHEDULED_P (fence
))
7396 /* Nothing was scheduled on this fence. */
7399 insn
= FENCE_INSN (fence
);
7400 seqno
= INSN_SEQNO (insn
);
7401 gcc_assert (seqno
> 0 && seqno
<= orig_max_seqno
);
7403 if (sched_verbose
>= 1)
7404 sel_print ("Fence %d[%d] has not changed\n",
7407 move_fence_to_fences (fences
, new_fences
);
7411 extract_new_fences_from (fences
, new_fences
, orig_max_seqno
);
7414 flist_clear (&old_fences
);
7415 return FLIST_TAIL_HEAD (new_fences
);
7418 /* Update seqnos of insns given by PSCHEDULED_INSNS. MIN_SEQNO and MAX_SEQNO
7419 are the miminum and maximum seqnos of the group, HIGHEST_SEQNO_IN_USE is
7420 the highest seqno used in a region. Return the updated highest seqno. */
7422 update_seqnos_and_stage (int min_seqno
, int max_seqno
,
7423 int highest_seqno_in_use
,
7424 ilist_t
*pscheduled_insns
)
7430 /* Actually, new_hs is the seqno of the instruction, that was
7431 scheduled first (i.e. it is the first one in SCHEDULED_INSNS). */
7432 if (*pscheduled_insns
)
7434 new_hs
= (INSN_SEQNO (ILIST_INSN (*pscheduled_insns
))
7435 + highest_seqno_in_use
+ max_seqno
- min_seqno
+ 2);
7436 gcc_assert (new_hs
> highest_seqno_in_use
);
7439 new_hs
= highest_seqno_in_use
;
7441 FOR_EACH_INSN (insn
, ii
, *pscheduled_insns
)
7443 gcc_assert (INSN_SEQNO (insn
) < 0);
7444 INSN_SEQNO (insn
) += highest_seqno_in_use
+ max_seqno
- min_seqno
+ 2;
7445 gcc_assert (INSN_SEQNO (insn
) <= new_hs
);
7447 /* When not pipelining, purge unneeded insn info on the scheduled insns.
7448 For example, having reg_last array of INSN_DEPS_CONTEXT in memory may
7449 require > 1GB of memory e.g. on limit-fnargs.c. */
7451 free_data_for_scheduled_insn (insn
);
7454 ilist_clear (pscheduled_insns
);
7460 /* The main driver for scheduling a region. This function is responsible
7461 for correct propagation of fences (i.e. scheduling points) and creating
7462 a group of parallel insns at each of them. It also supports
7463 pipelining. ORIG_MAX_SEQNO is the maximal seqno before this pass
7466 sel_sched_region_2 (int orig_max_seqno
)
7468 int highest_seqno_in_use
= orig_max_seqno
;
7470 stat_bookkeeping_copies
= 0;
7471 stat_insns_needed_bookkeeping
= 0;
7472 stat_renamed_scheduled
= 0;
7473 stat_substitutions_total
= 0;
7474 num_insns_scheduled
= 0;
7478 int min_seqno
, max_seqno
;
7479 ilist_t scheduled_insns
= NULL
;
7480 ilist_t
*scheduled_insns_tailp
= &scheduled_insns
;
7482 find_min_max_seqno (fences
, &min_seqno
, &max_seqno
);
7483 schedule_on_fences (fences
, max_seqno
, &scheduled_insns_tailp
);
7484 fences
= calculate_new_fences (fences
, orig_max_seqno
);
7485 highest_seqno_in_use
= update_seqnos_and_stage (min_seqno
, max_seqno
,
7486 highest_seqno_in_use
,
7490 if (sched_verbose
>= 1)
7491 sel_print ("Scheduled %d bookkeeping copies, %d insns needed "
7492 "bookkeeping, %d insns renamed, %d insns substituted\n",
7493 stat_bookkeeping_copies
,
7494 stat_insns_needed_bookkeeping
,
7495 stat_renamed_scheduled
,
7496 stat_substitutions_total
);
7499 /* Schedule a region. When pipelining, search for possibly never scheduled
7500 bookkeeping code and schedule it. Reschedule pipelined code without
7501 pipelining after. */
7503 sel_sched_region_1 (void)
7507 /* Remove empty blocks that might be in the region from the beginning. */
7508 purge_empty_blocks ();
7510 orig_max_seqno
= init_seqno (NULL
, NULL
);
7511 gcc_assert (orig_max_seqno
>= 1);
7513 /* When pipelining outer loops, create fences on the loop header,
7516 if (current_loop_nest
)
7517 init_fences (BB_END (EBB_FIRST_BB (0)));
7519 init_fences (bb_note (EBB_FIRST_BB (0)));
7522 sel_sched_region_2 (orig_max_seqno
);
7524 gcc_assert (fences
== NULL
);
7530 struct flist_tail_def _new_fences
;
7531 flist_tail_t new_fences
= &_new_fences
;
7534 pipelining_p
= false;
7535 max_ws
= MIN (max_ws
, issue_rate
* 3 / 2);
7536 bookkeeping_p
= false;
7537 enable_schedule_as_rhs_p
= false;
7539 /* Schedule newly created code, that has not been scheduled yet. */
7546 for (i
= 0; i
< current_nr_blocks
; i
++)
7548 basic_block bb
= EBB_FIRST_BB (i
);
7550 if (bitmap_bit_p (blocks_to_reschedule
, bb
->index
))
7552 if (! bb_ends_ebb_p (bb
))
7553 bitmap_set_bit (blocks_to_reschedule
, bb_next_bb (bb
)->index
);
7554 if (sel_bb_empty_p (bb
))
7556 bitmap_clear_bit (blocks_to_reschedule
, bb
->index
);
7559 clear_outdated_rtx_info (bb
);
7560 if (sel_insn_is_speculation_check (BB_END (bb
))
7561 && JUMP_P (BB_END (bb
)))
7562 bitmap_set_bit (blocks_to_reschedule
,
7563 BRANCH_EDGE (bb
)->dest
->index
);
7565 else if (! sel_bb_empty_p (bb
)
7566 && INSN_SCHED_TIMES (sel_bb_head (bb
)) <= 0)
7567 bitmap_set_bit (blocks_to_reschedule
, bb
->index
);
7570 for (i
= 0; i
< current_nr_blocks
; i
++)
7572 bb
= EBB_FIRST_BB (i
);
7574 /* While pipelining outer loops, skip bundling for loop
7575 preheaders. Those will be rescheduled in the outer
7577 if (sel_is_loop_preheader_p (bb
))
7579 clear_outdated_rtx_info (bb
);
7583 if (bitmap_bit_p (blocks_to_reschedule
, bb
->index
))
7585 flist_tail_init (new_fences
);
7587 orig_max_seqno
= init_seqno (blocks_to_reschedule
, bb
);
7589 /* Mark BB as head of the new ebb. */
7590 bitmap_set_bit (forced_ebb_heads
, bb
->index
);
7592 gcc_assert (fences
== NULL
);
7594 init_fences (bb_note (bb
));
7596 sel_sched_region_2 (orig_max_seqno
);
7606 /* Schedule the RGN region. */
7608 sel_sched_region (int rgn
)
7611 bool reset_sched_cycles_p
;
7613 if (sel_region_init (rgn
))
7616 if (sched_verbose
>= 1)
7617 sel_print ("Scheduling region %d\n", rgn
);
7619 schedule_p
= (!sched_is_disabled_for_current_region_p ()
7620 && dbg_cnt (sel_sched_region_cnt
));
7621 reset_sched_cycles_p
= pipelining_p
;
7623 sel_sched_region_1 ();
7625 /* Force initialization of INSN_SCHED_CYCLEs for correct bundling. */
7626 reset_sched_cycles_p
= true;
7628 sel_region_finish (reset_sched_cycles_p
);
7631 /* Perform global init for the scheduler. */
7633 sel_global_init (void)
7635 calculate_dominance_info (CDI_DOMINATORS
);
7636 alloc_sched_pools ();
7638 /* Setup the infos for sched_init. */
7639 sel_setup_sched_infos ();
7640 setup_sched_dump ();
7642 sched_rgn_init (false);
7646 /* Reset AFTER_RECOVERY if it has been set by the 1st scheduler pass. */
7648 can_issue_more
= issue_rate
;
7650 sched_extend_target ();
7651 sched_deps_init (true);
7652 setup_nop_and_exit_insns ();
7653 sel_extend_global_bb_info ();
7655 init_hard_regs_data ();
7658 /* Free the global data of the scheduler. */
7660 sel_global_finish (void)
7662 free_bb_note_pool ();
7664 sel_finish_global_bb_info ();
7666 free_regset_pool ();
7667 free_nop_and_exit_insns ();
7669 sched_rgn_finish ();
7670 sched_deps_finish ();
7674 sel_finish_pipelining ();
7676 free_sched_pools ();
7677 free_dominance_info (CDI_DOMINATORS
);
7680 /* Return true when we need to skip selective scheduling. Used for debugging. */
7682 maybe_skip_selective_scheduling (void)
7684 return ! dbg_cnt (sel_sched_cnt
);
7687 /* The entry point. */
7689 run_selective_scheduling (void)
7693 if (n_basic_blocks
== NUM_FIXED_BLOCKS
)
7698 for (rgn
= 0; rgn
< nr_regions
; rgn
++)
7699 sel_sched_region (rgn
);
7701 sel_global_finish ();