1 /* Instruction scheduling pass. Selective scheduler and pipeliner.
2 Copyright (C) 2006, 2007, 2008, 2009, 2010 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify it under
7 the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 3, or (at your option) any later
11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
22 #include "coretypes.h"
24 #include "rtl-error.h"
26 #include "hard-reg-set.h"
30 #include "insn-config.h"
31 #include "insn-attr.h"
38 #include "tree-pass.h"
39 #include "sched-int.h"
43 #include "langhooks.h"
44 #include "rtlhooks-def.h"
48 #ifdef INSN_SCHEDULING
49 #include "sel-sched-ir.h"
50 #include "sel-sched-dump.h"
51 #include "sel-sched.h"
54 /* Implementation of selective scheduling approach.
55 The below implementation follows the original approach with the following
58 o the scheduler works after register allocation (but can be also tuned
60 o some instructions are not copied or register renamed;
61 o conditional jumps are not moved with code duplication;
62 o several jumps in one parallel group are not supported;
63 o when pipelining outer loops, code motion through inner loops
65 o control and data speculation are supported;
66 o some improvements for better compile time/performance were made.
71 A vinsn, or virtual insn, is an insn with additional data characterizing
72 insn pattern, such as LHS, RHS, register sets used/set/clobbered, etc.
73 Vinsns also act as smart pointers to save memory by reusing them in
74 different expressions. A vinsn is described by vinsn_t type.
76 An expression is a vinsn with additional data characterizing its properties
77 at some point in the control flow graph. The data may be its usefulness,
78 priority, speculative status, whether it was renamed/subsituted, etc.
79 An expression is described by expr_t type.
81 Availability set (av_set) is a set of expressions at a given control flow
82 point. It is represented as av_set_t. The expressions in av sets are kept
83 sorted in the terms of expr_greater_p function. It allows to truncate
84 the set while leaving the best expressions.
86 A fence is a point through which code motion is prohibited. On each step,
87 we gather a parallel group of insns at a fence. It is possible to have
88 multiple fences. A fence is represented via fence_t.
90 A boundary is the border between the fence group and the rest of the code.
91 Currently, we never have more than one boundary per fence, as we finalize
92 the fence group when a jump is scheduled. A boundary is represented
98 The scheduler finds regions to schedule, schedules each one, and finalizes.
99 The regions are formed starting from innermost loops, so that when the inner
100 loop is pipelined, its prologue can be scheduled together with yet unprocessed
101 outer loop. The rest of acyclic regions are found using extend_rgns:
102 the blocks that are not yet allocated to any regions are traversed in top-down
103 order, and a block is added to a region to which all its predecessors belong;
104 otherwise, the block starts its own region.
106 The main scheduling loop (sel_sched_region_2) consists of just
107 scheduling on each fence and updating fences. For each fence,
108 we fill a parallel group of insns (fill_insns) until some insns can be added.
109 First, we compute available exprs (av-set) at the boundary of the current
110 group. Second, we choose the best expression from it. If the stall is
111 required to schedule any of the expressions, we advance the current cycle
112 appropriately. So, the final group does not exactly correspond to a VLIW
113 word. Third, we move the chosen expression to the boundary (move_op)
114 and update the intermediate av sets and liveness sets. We quit fill_insns
115 when either no insns left for scheduling or we have scheduled enough insns
116 so we feel like advancing a scheduling point.
118 Computing available expressions
119 ===============================
121 The computation (compute_av_set) is a bottom-up traversal. At each insn,
122 we're moving the union of its successors' sets through it via
123 moveup_expr_set. The dependent expressions are removed. Local
124 transformations (substitution, speculation) are applied to move more
125 exprs. Then the expr corresponding to the current insn is added.
126 The result is saved on each basic block header.
128 When traversing the CFG, we're moving down for no more than max_ws insns.
129 Also, we do not move down to ineligible successors (is_ineligible_successor),
130 which include moving along a back-edge, moving to already scheduled code,
131 and moving to another fence. The first two restrictions are lifted during
132 pipelining, which allows us to move insns along a back-edge. We always have
133 an acyclic region for scheduling because we forbid motion through fences.
135 Choosing the best expression
136 ============================
138 We sort the final availability set via sel_rank_for_schedule, then we remove
139 expressions which are not yet ready (tick_check_p) or which dest registers
140 cannot be used. For some of them, we choose another register via
141 find_best_reg. To do this, we run find_used_regs to calculate the set of
142 registers which cannot be used. The find_used_regs function performs
143 a traversal of code motion paths for an expr. We consider for renaming
144 only registers which are from the same regclass as the original one and
145 using which does not interfere with any live ranges. Finally, we convert
146 the resulting set to the ready list format and use max_issue and reorder*
147 hooks similarly to the Haifa scheduler.
149 Scheduling the best expression
150 ==============================
152 We run the move_op routine to perform the same type of code motion paths
153 traversal as in find_used_regs. (These are working via the same driver,
154 code_motion_path_driver.) When moving down the CFG, we look for original
155 instruction that gave birth to a chosen expression. We undo
156 the transformations performed on an expression via the history saved in it.
157 When found, we remove the instruction or leave a reg-reg copy/speculation
158 check if needed. On a way up, we insert bookkeeping copies at each join
159 point. If a copy is not needed, it will be removed later during this
160 traversal. We update the saved av sets and liveness sets on the way up, too.
162 Finalizing the schedule
163 =======================
165 When pipelining, we reschedule the blocks from which insns were pipelined
166 to get a tighter schedule. On Itanium, we also perform bundling via
167 the same routine from ia64.c.
169 Dependence analysis changes
170 ===========================
172 We augmented the sched-deps.c with hooks that get called when a particular
173 dependence is found in a particular part of an insn. Using these hooks, we
174 can do several actions such as: determine whether an insn can be moved through
175 another (has_dependence_p, moveup_expr); find out whether an insn can be
176 scheduled on the current cycle (tick_check_p); find out registers that
177 are set/used/clobbered by an insn and find out all the strange stuff that
178 restrict its movement, like SCHED_GROUP_P or CANT_MOVE (done in
179 init_global_and_expr_for_insn).
181 Initialization changes
182 ======================
184 There are parts of haifa-sched.c, sched-deps.c, and sched-rgn.c that are
185 reused in all of the schedulers. We have split up the initialization of data
186 of such parts into different functions prefixed with scheduler type and
187 postfixed with the type of data initialized: {,sel_,haifa_}sched_{init,finish},
188 sched_rgn_init/finish, sched_deps_init/finish, sched_init_{luids/bbs}, etc.
189 The same splitting is done with current_sched_info structure:
190 dependence-related parts are in sched_deps_info, common part is in
191 common_sched_info, and haifa/sel/etc part is in current_sched_info.
196 As we now have multiple-point scheduling, this would not work with backends
197 which save some of the scheduler state to use it in the target hooks.
198 For this purpose, we introduce a concept of target contexts, which
199 encapsulate such information. The backend should implement simple routines
200 of allocating/freeing/setting such a context. The scheduler calls these
201 as target hooks and handles the target context as an opaque pointer (similar
202 to the DFA state type, state_t).
207 As the correct data dependence graph is not supported during scheduling (which
208 is to be changed in mid-term), we cache as much of the dependence analysis
209 results as possible to avoid reanalyzing. This includes: bitmap caches on
210 each insn in stream of the region saying yes/no for a query with a pair of
211 UIDs; hashtables with the previously done transformations on each insn in
212 stream; a vector keeping a history of transformations on each expr.
214 Also, we try to minimize the dependence context used on each fence to check
215 whether the given expression is ready for scheduling by removing from it
216 insns that are definitely completed the execution. The results of
217 tick_check_p checks are also cached in a vector on each fence.
219 We keep a valid liveness set on each insn in a region to avoid the high
220 cost of recomputation on large basic blocks.
222 Finally, we try to minimize the number of needed updates to the availability
223 sets. The updates happen in two cases: when fill_insns terminates,
224 we advance all fences and increase the stage number to show that the region
225 has changed and the sets are to be recomputed; and when the next iteration
226 of a loop in fill_insns happens (but this one reuses the saved av sets
227 on bb headers.) Thus, we try to break the fill_insns loop only when
228 "significant" number of insns from the current scheduling window was
229 scheduled. This should be made a target param.
232 TODO: correctly support the data dependence graph at all stages and get rid
233 of all caches. This should speed up the scheduler.
234 TODO: implement moving cond jumps with bookkeeping copies on both targets.
235 TODO: tune the scheduler before RA so it does not create too much pseudos.
239 S.-M. Moon and K. Ebcioglu. Parallelizing nonnumerical code with
240 selective scheduling and software pipelining.
241 ACM TOPLAS, Vol 19, No. 6, pages 853--898, Nov. 1997.
243 Andrey Belevantsev, Maxim Kuvyrkov, Vladimir Makarov, Dmitry Melnik,
244 and Dmitry Zhurikhin. An interblock VLIW-targeted instruction scheduler
245 for GCC. In Proceedings of GCC Developers' Summit 2006.
247 Arutyun Avetisyan, Andrey Belevantsev, and Dmitry Melnik. GCC Instruction
248 Scheduler and Software Pipeliner on the Itanium Platform. EPIC-7 Workshop.
249 http://rogue.colorado.edu/EPIC7/.
253 /* True when pipelining is enabled. */
256 /* True if bookkeeping is enabled. */
259 /* Maximum number of insns that are eligible for renaming. */
260 int max_insns_to_rename
;
263 /* Definitions of local types and macros. */
265 /* Represents possible outcomes of moving an expression through an insn. */
266 enum MOVEUP_EXPR_CODE
268 /* The expression is not changed. */
271 /* Not changed, but requires a new destination register. */
274 /* Cannot be moved. */
277 /* Changed (substituted or speculated). */
281 /* The container to be passed into rtx search & replace functions. */
282 struct rtx_search_arg
284 /* What we are searching for. */
287 /* The occurence counter. */
291 typedef struct rtx_search_arg
*rtx_search_arg_p
;
293 /* This struct contains precomputed hard reg sets that are needed when
294 computing registers available for renaming. */
295 struct hard_regs_data
297 /* For every mode, this stores registers available for use with
299 HARD_REG_SET regs_for_mode
[NUM_MACHINE_MODES
];
301 /* True when regs_for_mode[mode] is initialized. */
302 bool regs_for_mode_ok
[NUM_MACHINE_MODES
];
304 /* For every register, it has regs that are ok to rename into it.
305 The register in question is always set. If not, this means
306 that the whole set is not computed yet. */
307 HARD_REG_SET regs_for_rename
[FIRST_PSEUDO_REGISTER
];
309 /* For every mode, this stores registers not available due to
311 HARD_REG_SET regs_for_call_clobbered
[NUM_MACHINE_MODES
];
313 /* All registers that are used or call used. */
314 HARD_REG_SET regs_ever_used
;
317 /* Stack registers. */
318 HARD_REG_SET stack_regs
;
322 /* Holds the results of computation of available for renaming and
323 unavailable hard registers. */
326 /* These are unavailable due to calls crossing, globalness, etc. */
327 HARD_REG_SET unavailable_hard_regs
;
329 /* These are *available* for renaming. */
330 HARD_REG_SET available_for_renaming
;
332 /* Whether this code motion path crosses a call. */
336 /* A global structure that contains the needed information about harg
338 static struct hard_regs_data sel_hrd
;
341 /* This structure holds local data used in code_motion_path_driver hooks on
342 the same or adjacent levels of recursion. Here we keep those parameters
343 that are not used in code_motion_path_driver routine itself, but only in
344 its hooks. Moreover, all parameters that can be modified in hooks are
345 in this structure, so all other parameters passed explicitly to hooks are
347 struct cmpd_local_params
349 /* Local params used in move_op_* functions. */
351 /* Edges for bookkeeping generation. */
354 /* C_EXPR merged from all successors and locally allocated temporary C_EXPR. */
355 expr_t c_expr_merged
, c_expr_local
;
357 /* Local params used in fur_* functions. */
358 /* Copy of the ORIGINAL_INSN list, stores the original insns already
359 found before entering the current level of code_motion_path_driver. */
360 def_list_t old_original_insns
;
362 /* Local params used in move_op_* functions. */
363 /* True when we have removed last insn in the block which was
364 also a boundary. Do not update anything or create bookkeeping copies. */
365 BOOL_BITFIELD removed_last_insn
: 1;
368 /* Stores the static parameters for move_op_* calls. */
369 struct moveop_static_params
371 /* Destination register. */
374 /* Current C_EXPR. */
377 /* An UID of expr_vliw which is to be moved up. If we find other exprs,
378 they are to be removed. */
381 #ifdef ENABLE_CHECKING
382 /* This is initialized to the insn on which the driver stopped its traversal. */
386 /* True if we scheduled an insn with different register. */
390 /* Stores the static parameters for fur_* calls. */
391 struct fur_static_params
393 /* Set of registers unavailable on the code motion path. */
396 /* Pointer to the list of original insns definitions. */
397 def_list_t
*original_insns
;
399 /* True if a code motion path contains a CALL insn. */
403 typedef struct fur_static_params
*fur_static_params_p
;
404 typedef struct cmpd_local_params
*cmpd_local_params_p
;
405 typedef struct moveop_static_params
*moveop_static_params_p
;
407 /* Set of hooks and parameters that determine behaviour specific to
408 move_op or find_used_regs functions. */
409 struct code_motion_path_driver_info_def
411 /* Called on enter to the basic block. */
412 int (*on_enter
) (insn_t
, cmpd_local_params_p
, void *, bool);
414 /* Called when original expr is found. */
415 void (*orig_expr_found
) (insn_t
, expr_t
, cmpd_local_params_p
, void *);
417 /* Called while descending current basic block if current insn is not
418 the original EXPR we're searching for. */
419 bool (*orig_expr_not_found
) (insn_t
, av_set_t
, void *);
421 /* Function to merge C_EXPRes from different successors. */
422 void (*merge_succs
) (insn_t
, insn_t
, int, cmpd_local_params_p
, void *);
424 /* Function to finalize merge from different successors and possibly
425 deallocate temporary data structures used for merging. */
426 void (*after_merge_succs
) (cmpd_local_params_p
, void *);
428 /* Called on the backward stage of recursion to do moveup_expr.
429 Used only with move_op_*. */
430 void (*ascend
) (insn_t
, void *);
432 /* Called on the ascending pass, before returning from the current basic
433 block or from the whole traversal. */
434 void (*at_first_insn
) (insn_t
, cmpd_local_params_p
, void *);
436 /* When processing successors in move_op we need only descend into
437 SUCCS_NORMAL successors, while in find_used_regs we need SUCCS_ALL. */
440 /* The routine name to print in dumps ("move_op" of "find_used_regs"). */
441 const char *routine_name
;
444 /* Global pointer to current hooks, either points to MOVE_OP_HOOKS or
446 struct code_motion_path_driver_info_def
*code_motion_path_driver_info
;
448 /* Set of hooks for performing move_op and find_used_regs routines with
449 code_motion_path_driver. */
450 extern struct code_motion_path_driver_info_def move_op_hooks
, fur_hooks
;
452 /* True if/when we want to emulate Haifa scheduler in the common code.
453 This is used in sched_rgn_local_init and in various places in
455 int sched_emulate_haifa_p
;
457 /* GLOBAL_LEVEL is used to discard information stored in basic block headers
458 av_sets. Av_set of bb header is valid if its (bb header's) level is equal
459 to GLOBAL_LEVEL. And invalid if lesser. This is primarily used to advance
460 scheduling window. */
463 /* Current fences. */
466 /* True when separable insns should be scheduled as RHSes. */
467 static bool enable_schedule_as_rhs_p
;
469 /* Used in verify_target_availability to assert that target reg is reported
470 unavailabile by both TARGET_UNAVAILABLE and find_used_regs only if
471 we haven't scheduled anything on the previous fence.
472 if scheduled_something_on_previous_fence is true, TARGET_UNAVAILABLE can
473 have more conservative value than the one returned by the
474 find_used_regs, thus we shouldn't assert that these values are equal. */
475 static bool scheduled_something_on_previous_fence
;
477 /* All newly emitted insns will have their uids greater than this value. */
478 static int first_emitted_uid
;
480 /* Set of basic blocks that are forced to start new ebbs. This is a subset
481 of all the ebb heads. */
482 static bitmap_head _forced_ebb_heads
;
483 bitmap_head
*forced_ebb_heads
= &_forced_ebb_heads
;
485 /* Blocks that need to be rescheduled after pipelining. */
486 bitmap blocks_to_reschedule
= NULL
;
488 /* True when the first lv set should be ignored when updating liveness. */
489 static bool ignore_first
= false;
491 /* Number of insns max_issue has initialized data structures for. */
492 static int max_issue_size
= 0;
494 /* Whether we can issue more instructions. */
495 static int can_issue_more
;
497 /* Maximum software lookahead window size, reduced when rescheduling after
501 /* Number of insns scheduled in current region. */
502 static int num_insns_scheduled
;
504 /* A vector of expressions is used to be able to sort them. */
506 DEF_VEC_ALLOC_P(expr_t
,heap
);
507 static VEC(expr_t
, heap
) *vec_av_set
= NULL
;
509 /* A vector of vinsns is used to hold temporary lists of vinsns. */
511 DEF_VEC_ALLOC_P(vinsn_t
,heap
);
512 typedef VEC(vinsn_t
, heap
) *vinsn_vec_t
;
514 /* This vector has the exprs which may still present in av_sets, but actually
515 can't be moved up due to bookkeeping created during code motion to another
516 fence. See comment near the call to update_and_record_unavailable_insns
517 for the detailed explanations. */
518 static vinsn_vec_t vec_bookkeeping_blocked_vinsns
= NULL
;
520 /* This vector has vinsns which are scheduled with renaming on the first fence
521 and then seen on the second. For expressions with such vinsns, target
522 availability information may be wrong. */
523 static vinsn_vec_t vec_target_unavailable_vinsns
= NULL
;
525 /* Vector to store temporary nops inserted in move_op to prevent removal
528 DEF_VEC_ALLOC_P(insn_t
,heap
);
529 static VEC(insn_t
, heap
) *vec_temp_moveop_nops
= NULL
;
531 /* These bitmaps record original instructions scheduled on the current
532 iteration and bookkeeping copies created by them. */
533 static bitmap current_originators
= NULL
;
534 static bitmap current_copies
= NULL
;
536 /* This bitmap marks the blocks visited by code_motion_path_driver so we don't
537 visit them afterwards. */
538 static bitmap code_motion_visited_blocks
= NULL
;
540 /* Variables to accumulate different statistics. */
542 /* The number of bookkeeping copies created. */
543 static int stat_bookkeeping_copies
;
545 /* The number of insns that required bookkeeiping for their scheduling. */
546 static int stat_insns_needed_bookkeeping
;
548 /* The number of insns that got renamed. */
549 static int stat_renamed_scheduled
;
551 /* The number of substitutions made during scheduling. */
552 static int stat_substitutions_total
;
555 /* Forward declarations of static functions. */
556 static bool rtx_ok_for_substitution_p (rtx
, rtx
);
557 static int sel_rank_for_schedule (const void *, const void *);
558 static av_set_t
find_sequential_best_exprs (bnd_t
, expr_t
, bool);
559 static basic_block
find_block_for_bookkeeping (edge e1
, edge e2
, bool lax
);
561 static rtx
get_dest_from_orig_ops (av_set_t
);
562 static basic_block
generate_bookkeeping_insn (expr_t
, edge
, edge
);
563 static bool find_used_regs (insn_t
, av_set_t
, regset
, struct reg_rename
*,
565 static bool move_op (insn_t
, av_set_t
, expr_t
, rtx
, expr_t
, bool*);
566 static int code_motion_path_driver (insn_t
, av_set_t
, ilist_t
,
567 cmpd_local_params_p
, void *);
568 static void sel_sched_region_1 (void);
569 static void sel_sched_region_2 (int);
570 static av_set_t
compute_av_set_inside_bb (insn_t
, ilist_t
, int, bool);
572 static void debug_state (state_t
);
575 /* Functions that work with fences. */
577 /* Advance one cycle on FENCE. */
579 advance_one_cycle (fence_t fence
)
585 advance_state (FENCE_STATE (fence
));
586 cycle
= ++FENCE_CYCLE (fence
);
587 FENCE_ISSUED_INSNS (fence
) = 0;
588 FENCE_STARTS_CYCLE_P (fence
) = 1;
589 can_issue_more
= issue_rate
;
590 FENCE_ISSUE_MORE (fence
) = can_issue_more
;
592 for (i
= 0; VEC_iterate (rtx
, FENCE_EXECUTING_INSNS (fence
), i
, insn
); )
594 if (INSN_READY_CYCLE (insn
) < cycle
)
596 remove_from_deps (FENCE_DC (fence
), insn
);
597 VEC_unordered_remove (rtx
, FENCE_EXECUTING_INSNS (fence
), i
);
602 if (sched_verbose
>= 2)
604 sel_print ("Finished a cycle. Current cycle = %d\n", FENCE_CYCLE (fence
));
605 debug_state (FENCE_STATE (fence
));
609 /* Returns true when SUCC in a fallthru bb of INSN, possibly
610 skipping empty basic blocks. */
612 in_fallthru_bb_p (rtx insn
, rtx succ
)
614 basic_block bb
= BLOCK_FOR_INSN (insn
);
616 if (bb
== BLOCK_FOR_INSN (succ
))
619 if (find_fallthru_edge (bb
))
620 bb
= find_fallthru_edge (bb
)->dest
;
624 while (sel_bb_empty_p (bb
))
627 return bb
== BLOCK_FOR_INSN (succ
);
630 /* Construct successor fences from OLD_FENCEs and put them in NEW_FENCES.
631 When a successor will continue a ebb, transfer all parameters of a fence
632 to the new fence. ORIG_MAX_SEQNO is the maximal seqno before this round
633 of scheduling helping to distinguish between the old and the new code. */
635 extract_new_fences_from (flist_t old_fences
, flist_tail_t new_fences
,
638 bool was_here_p
= false;
639 insn_t insn
= NULL_RTX
;
643 fence_t fence
= FLIST_FENCE (old_fences
);
646 /* Get the only element of FENCE_BNDS (fence). */
647 FOR_EACH_INSN (insn
, ii
, FENCE_BNDS (fence
))
649 gcc_assert (!was_here_p
);
652 gcc_assert (was_here_p
&& insn
!= NULL_RTX
);
654 /* When in the "middle" of the block, just move this fence
656 bb
= BLOCK_FOR_INSN (insn
);
657 if (! sel_bb_end_p (insn
)
658 || (single_succ_p (bb
)
659 && single_pred_p (single_succ (bb
))))
663 succ
= (sel_bb_end_p (insn
)
664 ? sel_bb_head (single_succ (bb
))
667 if (INSN_SEQNO (succ
) > 0
668 && INSN_SEQNO (succ
) <= orig_max_seqno
669 && INSN_SCHED_TIMES (succ
) <= 0)
671 FENCE_INSN (fence
) = succ
;
672 move_fence_to_fences (old_fences
, new_fences
);
674 if (sched_verbose
>= 1)
675 sel_print ("Fence %d continues as %d[%d] (state continue)\n",
676 INSN_UID (insn
), INSN_UID (succ
), BLOCK_NUM (succ
));
681 /* Otherwise copy fence's structures to (possibly) multiple successors. */
682 FOR_EACH_SUCC_1 (succ
, si
, insn
, SUCCS_NORMAL
| SUCCS_SKIP_TO_LOOP_EXITS
)
684 int seqno
= INSN_SEQNO (succ
);
686 if (0 < seqno
&& seqno
<= orig_max_seqno
687 && (pipelining_p
|| INSN_SCHED_TIMES (succ
) <= 0))
689 bool b
= (in_same_ebb_p (insn
, succ
)
690 || in_fallthru_bb_p (insn
, succ
));
692 if (sched_verbose
>= 1)
693 sel_print ("Fence %d continues as %d[%d] (state %s)\n",
694 INSN_UID (insn
), INSN_UID (succ
),
695 BLOCK_NUM (succ
), b
? "continue" : "reset");
698 add_dirty_fence_to_fences (new_fences
, succ
, fence
);
701 /* Mark block of the SUCC as head of the new ebb. */
702 bitmap_set_bit (forced_ebb_heads
, BLOCK_NUM (succ
));
703 add_clean_fence_to_fences (new_fences
, succ
, fence
);
710 /* Functions to support substitution. */
712 /* Returns whether INSN with dependence status DS is eligible for
713 substitution, i.e. it's a copy operation x := y, and RHS that is
714 moved up through this insn should be substituted. */
716 can_substitute_through_p (insn_t insn
, ds_t ds
)
718 /* We can substitute only true dependencies. */
719 if ((ds
& DEP_OUTPUT
)
722 || ! INSN_LHS (insn
))
725 /* Now we just need to make sure the INSN_RHS consists of only one
727 if (REG_P (INSN_LHS (insn
))
728 && REG_P (INSN_RHS (insn
)))
733 /* Substitute all occurences of INSN's destination in EXPR' vinsn with INSN's
734 source (if INSN is eligible for substitution). Returns TRUE if
735 substitution was actually performed, FALSE otherwise. Substitution might
736 be not performed because it's either EXPR' vinsn doesn't contain INSN's
737 destination or the resulting insn is invalid for the target machine.
738 When UNDO is true, perform unsubstitution instead (the difference is in
739 the part of rtx on which validate_replace_rtx is called). */
741 substitute_reg_in_expr (expr_t expr
, insn_t insn
, bool undo
)
745 vinsn_t
*vi
= &EXPR_VINSN (expr
);
746 bool has_rhs
= VINSN_RHS (*vi
) != NULL
;
749 /* Do not try to replace in SET_DEST. Although we'll choose new
750 register for the RHS, we don't want to change RHS' original reg.
751 If the insn is not SET, we may still be able to substitute something
752 in it, and if we're here (don't have deps), it doesn't write INSN's
756 : &PATTERN (VINSN_INSN_RTX (*vi
)));
757 old
= undo
? INSN_RHS (insn
) : INSN_LHS (insn
);
759 /* Substitute if INSN has a form of x:=y and LHS(INSN) occurs in *VI. */
760 if (rtx_ok_for_substitution_p (old
, *where
))
765 /* We should copy these rtxes before substitution. */
766 new_rtx
= copy_rtx (undo
? INSN_LHS (insn
) : INSN_RHS (insn
));
767 new_insn
= create_copy_of_insn_rtx (VINSN_INSN_RTX (*vi
));
769 /* Where we'll replace.
770 WHERE_REPLACE should point inside NEW_INSN, so INSN_RHS couldn't be
771 used instead of SET_SRC. */
772 where_replace
= (has_rhs
773 ? &SET_SRC (PATTERN (new_insn
))
774 : &PATTERN (new_insn
));
777 = validate_replace_rtx_part_nosimplify (old
, new_rtx
, where_replace
,
780 /* ??? Actually, constrain_operands result depends upon choice of
781 destination register. E.g. if we allow single register to be an rhs,
782 and if we try to move dx=ax(as rhs) through ax=dx, we'll result
783 in invalid insn dx=dx, so we'll loose this rhs here.
784 Just can't come up with significant testcase for this, so just
785 leaving it for now. */
788 change_vinsn_in_expr (expr
,
789 create_vinsn_from_insn_rtx (new_insn
, false));
791 /* Do not allow clobbering the address register of speculative
793 if ((EXPR_SPEC_DONE_DS (expr
) & SPECULATIVE
)
794 && bitmap_bit_p (VINSN_REG_USES (EXPR_VINSN (expr
)),
795 expr_dest_regno (expr
)))
796 EXPR_TARGET_AVAILABLE (expr
) = false;
807 /* Helper function for count_occurences_equiv. */
809 count_occurrences_1 (rtx
*cur_rtx
, void *arg
)
811 rtx_search_arg_p p
= (rtx_search_arg_p
) arg
;
813 /* The last param FOR_GCSE is true, because otherwise it performs excessive
817 for the last insn it presumes r33 equivalent to r8, so it changes it to
818 r33. Actually, there's no change, but it spoils debugging. */
819 if (exp_equiv_p (*cur_rtx
, p
->x
, 0, true))
821 /* Bail out if we occupy more than one register. */
823 && HARD_REGISTER_P (*cur_rtx
)
824 && hard_regno_nregs
[REGNO(*cur_rtx
)][GET_MODE (*cur_rtx
)] > 1)
832 /* Do not traverse subexprs. */
836 if (GET_CODE (*cur_rtx
) == SUBREG
838 && (!REG_P (SUBREG_REG (*cur_rtx
))
839 || REGNO (SUBREG_REG (*cur_rtx
)) == REGNO (p
->x
)))
841 /* ??? Do not support substituting regs inside subregs. In that case,
842 simplify_subreg will be called by validate_replace_rtx, and
843 unsubstitution will fail later. */
848 /* Continue search. */
852 /* Return the number of places WHAT appears within WHERE.
853 Bail out when we found a reference occupying several hard registers. */
855 count_occurrences_equiv (rtx what
, rtx where
)
857 struct rtx_search_arg arg
;
862 for_each_rtx (&where
, &count_occurrences_1
, (void *) &arg
);
867 /* Returns TRUE if WHAT is found in WHERE rtx tree. */
869 rtx_ok_for_substitution_p (rtx what
, rtx where
)
871 return (count_occurrences_equiv (what
, where
) > 0);
875 /* Functions to support register renaming. */
877 /* Substitute VI's set source with REGNO. Returns newly created pattern
878 that has REGNO as its source. */
880 create_insn_rtx_with_rhs (vinsn_t vi
, rtx rhs_rtx
)
886 lhs_rtx
= copy_rtx (VINSN_LHS (vi
));
888 pattern
= gen_rtx_SET (VOIDmode
, lhs_rtx
, rhs_rtx
);
889 insn_rtx
= create_insn_rtx_from_pattern (pattern
, NULL_RTX
);
894 /* Returns whether INSN's src can be replaced with register number
895 NEW_SRC_REG. E.g. the following insn is valid for i386:
897 (insn:HI 2205 6585 2207 727 ../../gcc/libiberty/regex.c:3337
898 (set (mem/s:QI (plus:SI (plus:SI (reg/f:SI 7 sp)
899 (reg:SI 0 ax [orig:770 c1 ] [770]))
900 (const_int 288 [0x120])) [0 str S1 A8])
901 (const_int 0 [0x0])) 43 {*movqi_1} (nil)
904 But if we change (const_int 0 [0x0]) to (reg:QI 4 si), it will be invalid
905 because of operand constraints:
907 (define_insn "*movqi_1"
908 [(set (match_operand:QI 0 "nonimmediate_operand" "=q,q ,q ,r,r ,?r,m")
909 (match_operand:QI 1 "general_operand" " q,qn,qm,q,rn,qm,qn")
912 So do constrain_operands here, before choosing NEW_SRC_REG as best
916 replace_src_with_reg_ok_p (insn_t insn
, rtx new_src_reg
)
918 vinsn_t vi
= INSN_VINSN (insn
);
919 enum machine_mode mode
;
923 gcc_assert (VINSN_SEPARABLE_P (vi
));
925 get_dest_and_mode (insn
, &dst_loc
, &mode
);
926 gcc_assert (mode
== GET_MODE (new_src_reg
));
928 if (REG_P (dst_loc
) && REGNO (new_src_reg
) == REGNO (dst_loc
))
931 /* See whether SET_SRC can be replaced with this register. */
932 validate_change (insn
, &SET_SRC (PATTERN (insn
)), new_src_reg
, 1);
933 res
= verify_changes (0);
939 /* Returns whether INSN still be valid after replacing it's DEST with
942 replace_dest_with_reg_ok_p (insn_t insn
, rtx new_reg
)
944 vinsn_t vi
= INSN_VINSN (insn
);
947 /* We should deal here only with separable insns. */
948 gcc_assert (VINSN_SEPARABLE_P (vi
));
949 gcc_assert (GET_MODE (VINSN_LHS (vi
)) == GET_MODE (new_reg
));
951 /* See whether SET_DEST can be replaced with this register. */
952 validate_change (insn
, &SET_DEST (PATTERN (insn
)), new_reg
, 1);
953 res
= verify_changes (0);
959 /* Create a pattern with rhs of VI and lhs of LHS_RTX. */
961 create_insn_rtx_with_lhs (vinsn_t vi
, rtx lhs_rtx
)
967 rhs_rtx
= copy_rtx (VINSN_RHS (vi
));
969 pattern
= gen_rtx_SET (VOIDmode
, lhs_rtx
, rhs_rtx
);
970 insn_rtx
= create_insn_rtx_from_pattern (pattern
, NULL_RTX
);
975 /* Substitute lhs in the given expression EXPR for the register with number
976 NEW_REGNO. SET_DEST may be arbitrary rtx, not only register. */
978 replace_dest_with_reg_in_expr (expr_t expr
, rtx new_reg
)
983 insn_rtx
= create_insn_rtx_with_lhs (EXPR_VINSN (expr
), new_reg
);
984 vinsn
= create_vinsn_from_insn_rtx (insn_rtx
, false);
986 change_vinsn_in_expr (expr
, vinsn
);
987 EXPR_WAS_RENAMED (expr
) = 1;
988 EXPR_TARGET_AVAILABLE (expr
) = 1;
991 /* Returns whether VI writes either one of the USED_REGS registers or,
992 if a register is a hard one, one of the UNAVAILABLE_HARD_REGS registers. */
994 vinsn_writes_one_of_regs_p (vinsn_t vi
, regset used_regs
,
995 HARD_REG_SET unavailable_hard_regs
)
998 reg_set_iterator rsi
;
1000 EXECUTE_IF_SET_IN_REG_SET (VINSN_REG_SETS (vi
), 0, regno
, rsi
)
1002 if (REGNO_REG_SET_P (used_regs
, regno
))
1004 if (HARD_REGISTER_NUM_P (regno
)
1005 && TEST_HARD_REG_BIT (unavailable_hard_regs
, regno
))
1009 EXECUTE_IF_SET_IN_REG_SET (VINSN_REG_CLOBBERS (vi
), 0, regno
, rsi
)
1011 if (REGNO_REG_SET_P (used_regs
, regno
))
1013 if (HARD_REGISTER_NUM_P (regno
)
1014 && TEST_HARD_REG_BIT (unavailable_hard_regs
, regno
))
1021 /* Returns register class of the output register in INSN.
1022 Returns NO_REGS for call insns because some targets have constraints on
1023 destination register of a call insn.
1025 Code adopted from regrename.c::build_def_use. */
1026 static enum reg_class
1027 get_reg_class (rtx insn
)
1031 extract_insn (insn
);
1032 if (! constrain_operands (1))
1033 fatal_insn_not_found (insn
);
1034 preprocess_constraints ();
1035 alt
= which_alternative
;
1036 n_ops
= recog_data
.n_operands
;
1038 for (i
= 0; i
< n_ops
; ++i
)
1040 int matches
= recog_op_alt
[i
][alt
].matches
;
1042 recog_op_alt
[i
][alt
].cl
= recog_op_alt
[matches
][alt
].cl
;
1045 if (asm_noperands (PATTERN (insn
)) > 0)
1047 for (i
= 0; i
< n_ops
; i
++)
1048 if (recog_data
.operand_type
[i
] == OP_OUT
)
1050 rtx
*loc
= recog_data
.operand_loc
[i
];
1052 enum reg_class cl
= recog_op_alt
[i
][alt
].cl
;
1055 && REGNO (op
) == ORIGINAL_REGNO (op
))
1061 else if (!CALL_P (insn
))
1063 for (i
= 0; i
< n_ops
+ recog_data
.n_dups
; i
++)
1065 int opn
= i
< n_ops
? i
: recog_data
.dup_num
[i
- n_ops
];
1066 enum reg_class cl
= recog_op_alt
[opn
][alt
].cl
;
1068 if (recog_data
.operand_type
[opn
] == OP_OUT
||
1069 recog_data
.operand_type
[opn
] == OP_INOUT
)
1075 (insn (set (reg:CCZ 17 flags) (compare:CCZ ...)))
1076 may result in returning NO_REGS, cause flags is written implicitly through
1077 CMP insn, which has no OP_OUT | OP_INOUT operands. */
1081 #ifdef HARD_REGNO_RENAME_OK
1082 /* Calculate HARD_REGNO_RENAME_OK data for REGNO. */
1084 init_hard_regno_rename (int regno
)
1088 SET_HARD_REG_BIT (sel_hrd
.regs_for_rename
[regno
], regno
);
1090 for (cur_reg
= 0; cur_reg
< FIRST_PSEUDO_REGISTER
; cur_reg
++)
1092 /* We are not interested in renaming in other regs. */
1093 if (!TEST_HARD_REG_BIT (sel_hrd
.regs_ever_used
, cur_reg
))
1096 if (HARD_REGNO_RENAME_OK (regno
, cur_reg
))
1097 SET_HARD_REG_BIT (sel_hrd
.regs_for_rename
[regno
], cur_reg
);
1102 /* A wrapper around HARD_REGNO_RENAME_OK that will look into the hard regs
1105 sel_hard_regno_rename_ok (int from ATTRIBUTE_UNUSED
, int to ATTRIBUTE_UNUSED
)
1107 #ifdef HARD_REGNO_RENAME_OK
1108 /* Check whether this is all calculated. */
1109 if (TEST_HARD_REG_BIT (sel_hrd
.regs_for_rename
[from
], from
))
1110 return TEST_HARD_REG_BIT (sel_hrd
.regs_for_rename
[from
], to
);
1112 init_hard_regno_rename (from
);
1114 return TEST_HARD_REG_BIT (sel_hrd
.regs_for_rename
[from
], to
);
1120 /* Calculate set of registers that are capable of holding MODE. */
1122 init_regs_for_mode (enum machine_mode mode
)
1126 CLEAR_HARD_REG_SET (sel_hrd
.regs_for_mode
[mode
]);
1127 CLEAR_HARD_REG_SET (sel_hrd
.regs_for_call_clobbered
[mode
]);
1129 for (cur_reg
= 0; cur_reg
< FIRST_PSEUDO_REGISTER
; cur_reg
++)
1131 int nregs
= hard_regno_nregs
[cur_reg
][mode
];
1134 for (i
= nregs
- 1; i
>= 0; --i
)
1135 if (fixed_regs
[cur_reg
+ i
]
1136 || global_regs
[cur_reg
+ i
]
1137 /* Can't use regs which aren't saved by
1139 || !TEST_HARD_REG_BIT (sel_hrd
.regs_ever_used
, cur_reg
+ i
)
1140 #ifdef LEAF_REGISTERS
1141 /* We can't use a non-leaf register if we're in a
1143 || (current_function_is_leaf
1144 && !LEAF_REGISTERS
[cur_reg
+ i
])
1152 /* See whether it accepts all modes that occur in
1154 if (! HARD_REGNO_MODE_OK (cur_reg
, mode
))
1157 if (HARD_REGNO_CALL_PART_CLOBBERED (cur_reg
, mode
))
1158 SET_HARD_REG_BIT (sel_hrd
.regs_for_call_clobbered
[mode
],
1161 /* If the CUR_REG passed all the checks above,
1163 SET_HARD_REG_BIT (sel_hrd
.regs_for_mode
[mode
], cur_reg
);
1166 sel_hrd
.regs_for_mode_ok
[mode
] = true;
1169 /* Init all register sets gathered in HRD. */
1171 init_hard_regs_data (void)
1176 CLEAR_HARD_REG_SET (sel_hrd
.regs_ever_used
);
1177 for (cur_reg
= 0; cur_reg
< FIRST_PSEUDO_REGISTER
; cur_reg
++)
1178 if (df_regs_ever_live_p (cur_reg
) || call_used_regs
[cur_reg
])
1179 SET_HARD_REG_BIT (sel_hrd
.regs_ever_used
, cur_reg
);
1181 /* Initialize registers that are valid based on mode when this is
1183 for (cur_mode
= 0; cur_mode
< NUM_MACHINE_MODES
; cur_mode
++)
1184 sel_hrd
.regs_for_mode_ok
[cur_mode
] = false;
1186 /* Mark that all HARD_REGNO_RENAME_OK is not calculated. */
1187 for (cur_reg
= 0; cur_reg
< FIRST_PSEUDO_REGISTER
; cur_reg
++)
1188 CLEAR_HARD_REG_SET (sel_hrd
.regs_for_rename
[cur_reg
]);
1191 CLEAR_HARD_REG_SET (sel_hrd
.stack_regs
);
1193 for (cur_reg
= FIRST_STACK_REG
; cur_reg
<= LAST_STACK_REG
; cur_reg
++)
1194 SET_HARD_REG_BIT (sel_hrd
.stack_regs
, cur_reg
);
1198 /* Mark hardware regs in REG_RENAME_P that are not suitable
1199 for renaming rhs in INSN due to hardware restrictions (register class,
1200 modes compatibility etc). This doesn't affect original insn's dest reg,
1201 if it isn't in USED_REGS. DEF is a definition insn of rhs for which the
1202 destination register is sought. LHS (DEF->ORIG_INSN) may be REG or MEM.
1203 Registers that are in used_regs are always marked in
1204 unavailable_hard_regs as well. */
1207 mark_unavailable_hard_regs (def_t def
, struct reg_rename
*reg_rename_p
,
1208 regset used_regs ATTRIBUTE_UNUSED
)
1210 enum machine_mode mode
;
1211 enum reg_class cl
= NO_REGS
;
1213 unsigned cur_reg
, regno
;
1214 hard_reg_set_iterator hrsi
;
1216 gcc_assert (GET_CODE (PATTERN (def
->orig_insn
)) == SET
);
1217 gcc_assert (reg_rename_p
);
1219 orig_dest
= SET_DEST (PATTERN (def
->orig_insn
));
1221 /* We have decided not to rename 'mem = something;' insns, as 'something'
1222 is usually a register. */
1223 if (!REG_P (orig_dest
))
1226 regno
= REGNO (orig_dest
);
1228 /* If before reload, don't try to work with pseudos. */
1229 if (!reload_completed
&& !HARD_REGISTER_NUM_P (regno
))
1232 if (reload_completed
)
1233 cl
= get_reg_class (def
->orig_insn
);
1235 /* Stop if the original register is one of the fixed_regs, global_regs or
1236 frame pointer, or we could not discover its class. */
1237 if (fixed_regs
[regno
]
1238 || global_regs
[regno
]
1239 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
1240 || (frame_pointer_needed
&& regno
== HARD_FRAME_POINTER_REGNUM
)
1242 || (frame_pointer_needed
&& regno
== FRAME_POINTER_REGNUM
)
1244 || (reload_completed
&& cl
== NO_REGS
))
1246 SET_HARD_REG_SET (reg_rename_p
->unavailable_hard_regs
);
1248 /* Give a chance for original register, if it isn't in used_regs. */
1249 if (!def
->crosses_call
)
1250 CLEAR_HARD_REG_BIT (reg_rename_p
->unavailable_hard_regs
, regno
);
1255 /* If something allocated on stack in this function, mark frame pointer
1256 register unavailable, considering also modes.
1257 FIXME: it is enough to do this once per all original defs. */
1258 if (frame_pointer_needed
)
1262 for (i
= hard_regno_nregs
[FRAME_POINTER_REGNUM
][Pmode
]; i
--;)
1263 SET_HARD_REG_BIT (reg_rename_p
->unavailable_hard_regs
,
1264 FRAME_POINTER_REGNUM
+ i
);
1266 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
1267 for (i
= hard_regno_nregs
[HARD_FRAME_POINTER_REGNUM
][Pmode
]; i
--;)
1268 SET_HARD_REG_BIT (reg_rename_p
->unavailable_hard_regs
,
1269 HARD_FRAME_POINTER_REGNUM
+ i
);
1274 /* For the stack registers the presence of FIRST_STACK_REG in USED_REGS
1275 is equivalent to as if all stack regs were in this set.
1276 I.e. no stack register can be renamed, and even if it's an original
1277 register here we make sure it won't be lifted over it's previous def
1278 (it's previous def will appear as if it's a FIRST_STACK_REG def.
1279 The HARD_REGNO_RENAME_OK covers other cases in condition below. */
1280 if (IN_RANGE (REGNO (orig_dest
), FIRST_STACK_REG
, LAST_STACK_REG
)
1281 && REGNO_REG_SET_P (used_regs
, FIRST_STACK_REG
))
1282 IOR_HARD_REG_SET (reg_rename_p
->unavailable_hard_regs
,
1283 sel_hrd
.stack_regs
);
1286 /* If there's a call on this path, make regs from call_used_reg_set
1288 if (def
->crosses_call
)
1289 IOR_HARD_REG_SET (reg_rename_p
->unavailable_hard_regs
,
1292 /* Stop here before reload: we need FRAME_REGS, STACK_REGS, and crosses_call,
1293 but not register classes. */
1294 if (!reload_completed
)
1297 /* Leave regs as 'available' only from the current
1299 COPY_HARD_REG_SET (reg_rename_p
->available_for_renaming
,
1300 reg_class_contents
[cl
]);
1302 mode
= GET_MODE (orig_dest
);
1304 /* Leave only registers available for this mode. */
1305 if (!sel_hrd
.regs_for_mode_ok
[mode
])
1306 init_regs_for_mode (mode
);
1307 AND_HARD_REG_SET (reg_rename_p
->available_for_renaming
,
1308 sel_hrd
.regs_for_mode
[mode
]);
1310 /* Exclude registers that are partially call clobbered. */
1311 if (def
->crosses_call
1312 && ! HARD_REGNO_CALL_PART_CLOBBERED (regno
, mode
))
1313 AND_COMPL_HARD_REG_SET (reg_rename_p
->available_for_renaming
,
1314 sel_hrd
.regs_for_call_clobbered
[mode
]);
1316 /* Leave only those that are ok to rename. */
1317 EXECUTE_IF_SET_IN_HARD_REG_SET (reg_rename_p
->available_for_renaming
,
1323 nregs
= hard_regno_nregs
[cur_reg
][mode
];
1324 gcc_assert (nregs
> 0);
1326 for (i
= nregs
- 1; i
>= 0; --i
)
1327 if (! sel_hard_regno_rename_ok (regno
+ i
, cur_reg
+ i
))
1331 CLEAR_HARD_REG_BIT (reg_rename_p
->available_for_renaming
,
1335 AND_COMPL_HARD_REG_SET (reg_rename_p
->available_for_renaming
,
1336 reg_rename_p
->unavailable_hard_regs
);
1338 /* Regno is always ok from the renaming part of view, but it really
1339 could be in *unavailable_hard_regs already, so set it here instead
1341 SET_HARD_REG_BIT (reg_rename_p
->available_for_renaming
, regno
);
1344 /* reg_rename_tick[REG1] > reg_rename_tick[REG2] if REG1 was chosen as the
1345 best register more recently than REG2. */
1346 static int reg_rename_tick
[FIRST_PSEUDO_REGISTER
];
1348 /* Indicates the number of times renaming happened before the current one. */
1349 static int reg_rename_this_tick
;
1351 /* Choose the register among free, that is suitable for storing
1354 ORIGINAL_INSNS is the list of insns where the operation (rhs)
1355 originally appears. There could be multiple original operations
1356 for single rhs since we moving it up and merging along different
1359 Some code is adapted from regrename.c (regrename_optimize).
1360 If original register is available, function returns it.
1361 Otherwise it performs the checks, so the new register should
1362 comply with the following:
1363 - it should not violate any live ranges (such registers are in
1364 REG_RENAME_P->available_for_renaming set);
1365 - it should not be in the HARD_REGS_USED regset;
1366 - it should be in the class compatible with original uses;
1367 - it should not be clobbered through reference with different mode;
1368 - if we're in the leaf function, then the new register should
1369 not be in the LEAF_REGISTERS;
1372 If several registers meet the conditions, the register with smallest
1373 tick is returned to achieve more even register allocation.
1375 If original register seems to be ok, we set *IS_ORIG_REG_P_PTR to true.
1377 If no register satisfies the above conditions, NULL_RTX is returned. */
1379 choose_best_reg_1 (HARD_REG_SET hard_regs_used
,
1380 struct reg_rename
*reg_rename_p
,
1381 def_list_t original_insns
, bool *is_orig_reg_p_ptr
)
1385 enum machine_mode mode
= VOIDmode
;
1386 unsigned regno
, i
, n
;
1387 hard_reg_set_iterator hrsi
;
1388 def_list_iterator di
;
1391 /* If original register is available, return it. */
1392 *is_orig_reg_p_ptr
= true;
1394 FOR_EACH_DEF (def
, di
, original_insns
)
1396 rtx orig_dest
= SET_DEST (PATTERN (def
->orig_insn
));
1398 gcc_assert (REG_P (orig_dest
));
1400 /* Check that all original operations have the same mode.
1401 This is done for the next loop; if we'd return from this
1402 loop, we'd check only part of them, but in this case
1403 it doesn't matter. */
1404 if (mode
== VOIDmode
)
1405 mode
= GET_MODE (orig_dest
);
1406 gcc_assert (mode
== GET_MODE (orig_dest
));
1408 regno
= REGNO (orig_dest
);
1409 for (i
= 0, n
= hard_regno_nregs
[regno
][mode
]; i
< n
; i
++)
1410 if (TEST_HARD_REG_BIT (hard_regs_used
, regno
+ i
))
1413 /* All hard registers are available. */
1416 gcc_assert (mode
!= VOIDmode
);
1418 /* Hard registers should not be shared. */
1419 return gen_rtx_REG (mode
, regno
);
1423 *is_orig_reg_p_ptr
= false;
1426 /* Among all available regs choose the register that was
1427 allocated earliest. */
1428 EXECUTE_IF_SET_IN_HARD_REG_SET (reg_rename_p
->available_for_renaming
,
1430 if (! TEST_HARD_REG_BIT (hard_regs_used
, cur_reg
))
1432 /* Check that all hard regs for mode are available. */
1433 for (i
= 1, n
= hard_regno_nregs
[cur_reg
][mode
]; i
< n
; i
++)
1434 if (TEST_HARD_REG_BIT (hard_regs_used
, cur_reg
+ i
)
1435 || !TEST_HARD_REG_BIT (reg_rename_p
->available_for_renaming
,
1442 /* All hard registers are available. */
1443 if (best_new_reg
< 0
1444 || reg_rename_tick
[cur_reg
] < reg_rename_tick
[best_new_reg
])
1446 best_new_reg
= cur_reg
;
1448 /* Return immediately when we know there's no better reg. */
1449 if (! reg_rename_tick
[best_new_reg
])
1454 if (best_new_reg
>= 0)
1456 /* Use the check from the above loop. */
1457 gcc_assert (mode
!= VOIDmode
);
1458 return gen_rtx_REG (mode
, best_new_reg
);
1464 /* A wrapper around choose_best_reg_1 () to verify that we make correct
1465 assumptions about available registers in the function. */
1467 choose_best_reg (HARD_REG_SET hard_regs_used
, struct reg_rename
*reg_rename_p
,
1468 def_list_t original_insns
, bool *is_orig_reg_p_ptr
)
1470 rtx best_reg
= choose_best_reg_1 (hard_regs_used
, reg_rename_p
,
1471 original_insns
, is_orig_reg_p_ptr
);
1473 /* FIXME loop over hard_regno_nregs here. */
1474 gcc_assert (best_reg
== NULL_RTX
1475 || TEST_HARD_REG_BIT (sel_hrd
.regs_ever_used
, REGNO (best_reg
)));
1480 /* Choose the pseudo register for storing rhs value. As this is supposed
1481 to work before reload, we return either the original register or make
1482 the new one. The parameters are the same that in choose_nest_reg_1
1483 functions, except that USED_REGS may contain pseudos.
1484 If we work with hard regs, check also REG_RENAME_P->UNAVAILABLE_HARD_REGS.
1486 TODO: take into account register pressure while doing this. Up to this
1487 moment, this function would never return NULL for pseudos, but we should
1488 not rely on this. */
1490 choose_best_pseudo_reg (regset used_regs
,
1491 struct reg_rename
*reg_rename_p
,
1492 def_list_t original_insns
, bool *is_orig_reg_p_ptr
)
1494 def_list_iterator i
;
1496 enum machine_mode mode
= VOIDmode
;
1497 bool bad_hard_regs
= false;
1499 /* We should not use this after reload. */
1500 gcc_assert (!reload_completed
);
1502 /* If original register is available, return it. */
1503 *is_orig_reg_p_ptr
= true;
1505 FOR_EACH_DEF (def
, i
, original_insns
)
1507 rtx dest
= SET_DEST (PATTERN (def
->orig_insn
));
1510 gcc_assert (REG_P (dest
));
1512 /* Check that all original operations have the same mode. */
1513 if (mode
== VOIDmode
)
1514 mode
= GET_MODE (dest
);
1516 gcc_assert (mode
== GET_MODE (dest
));
1517 orig_regno
= REGNO (dest
);
1519 if (!REGNO_REG_SET_P (used_regs
, orig_regno
))
1521 if (orig_regno
< FIRST_PSEUDO_REGISTER
)
1523 gcc_assert (df_regs_ever_live_p (orig_regno
));
1525 /* For hard registers, we have to check hardware imposed
1526 limitations (frame/stack registers, calls crossed). */
1527 if (!TEST_HARD_REG_BIT (reg_rename_p
->unavailable_hard_regs
,
1530 /* Don't let register cross a call if it doesn't already
1531 cross one. This condition is written in accordance with
1532 that in sched-deps.c sched_analyze_reg(). */
1533 if (!reg_rename_p
->crosses_call
1534 || REG_N_CALLS_CROSSED (orig_regno
) > 0)
1535 return gen_rtx_REG (mode
, orig_regno
);
1538 bad_hard_regs
= true;
1545 *is_orig_reg_p_ptr
= false;
1547 /* We had some original hard registers that couldn't be used.
1548 Those were likely special. Don't try to create a pseudo. */
1552 /* We haven't found a register from original operations. Get a new one.
1553 FIXME: control register pressure somehow. */
1555 rtx new_reg
= gen_reg_rtx (mode
);
1557 gcc_assert (mode
!= VOIDmode
);
1559 max_regno
= max_reg_num ();
1560 maybe_extend_reg_info_p ();
1561 REG_N_CALLS_CROSSED (REGNO (new_reg
)) = reg_rename_p
->crosses_call
? 1 : 0;
1567 /* True when target of EXPR is available due to EXPR_TARGET_AVAILABLE,
1568 USED_REGS and REG_RENAME_P->UNAVAILABLE_HARD_REGS. */
1570 verify_target_availability (expr_t expr
, regset used_regs
,
1571 struct reg_rename
*reg_rename_p
)
1573 unsigned n
, i
, regno
;
1574 enum machine_mode mode
;
1575 bool target_available
, live_available
, hard_available
;
1577 if (!REG_P (EXPR_LHS (expr
)) || EXPR_TARGET_AVAILABLE (expr
) < 0)
1580 regno
= expr_dest_regno (expr
);
1581 mode
= GET_MODE (EXPR_LHS (expr
));
1582 target_available
= EXPR_TARGET_AVAILABLE (expr
) == 1;
1583 n
= reload_completed
? hard_regno_nregs
[regno
][mode
] : 1;
1585 live_available
= hard_available
= true;
1586 for (i
= 0; i
< n
; i
++)
1588 if (bitmap_bit_p (used_regs
, regno
+ i
))
1589 live_available
= false;
1590 if (TEST_HARD_REG_BIT (reg_rename_p
->unavailable_hard_regs
, regno
+ i
))
1591 hard_available
= false;
1594 /* When target is not available, it may be due to hard register
1595 restrictions, e.g. crosses calls, so we check hard_available too. */
1596 if (target_available
)
1597 gcc_assert (live_available
);
1599 /* Check only if we haven't scheduled something on the previous fence,
1600 cause due to MAX_SOFTWARE_LOOKAHEAD_WINDOW_SIZE issues
1601 and having more than one fence, we may end having targ_un in a block
1602 in which successors target register is actually available.
1604 The last condition handles the case when a dependence from a call insn
1605 was created in sched-deps.c for insns with destination registers that
1606 never crossed a call before, but do cross one after our code motion.
1608 FIXME: in the latter case, we just uselessly called find_used_regs,
1609 because we can't move this expression with any other register
1611 gcc_assert (scheduled_something_on_previous_fence
|| !live_available
1613 || (!reload_completed
&& reg_rename_p
->crosses_call
1614 && REG_N_CALLS_CROSSED (regno
) == 0));
1617 /* Collect unavailable registers due to liveness for EXPR from BNDS
1618 into USED_REGS. Save additional information about available
1619 registers and unavailable due to hardware restriction registers
1620 into REG_RENAME_P structure. Save original insns into ORIGINAL_INSNS
1623 collect_unavailable_regs_from_bnds (expr_t expr
, blist_t bnds
, regset used_regs
,
1624 struct reg_rename
*reg_rename_p
,
1625 def_list_t
*original_insns
)
1627 for (; bnds
; bnds
= BLIST_NEXT (bnds
))
1630 av_set_t orig_ops
= NULL
;
1631 bnd_t bnd
= BLIST_BND (bnds
);
1633 /* If the chosen best expr doesn't belong to current boundary,
1635 if (!av_set_is_in_p (BND_AV1 (bnd
), EXPR_VINSN (expr
)))
1638 /* Put in ORIG_OPS all exprs from this boundary that became
1640 orig_ops
= find_sequential_best_exprs (bnd
, expr
, false);
1642 /* Compute used regs and OR it into the USED_REGS. */
1643 res
= find_used_regs (BND_TO (bnd
), orig_ops
, used_regs
,
1644 reg_rename_p
, original_insns
);
1646 /* FIXME: the assert is true until we'd have several boundaries. */
1648 av_set_clear (&orig_ops
);
1652 /* Return TRUE if it is possible to replace LHSes of ORIG_INSNS with BEST_REG.
1653 If BEST_REG is valid, replace LHS of EXPR with it. */
1655 try_replace_dest_reg (ilist_t orig_insns
, rtx best_reg
, expr_t expr
)
1657 /* Try whether we'll be able to generate the insn
1658 'dest := best_reg' at the place of the original operation. */
1659 for (; orig_insns
; orig_insns
= ILIST_NEXT (orig_insns
))
1661 insn_t orig_insn
= DEF_LIST_DEF (orig_insns
)->orig_insn
;
1663 gcc_assert (EXPR_SEPARABLE_P (INSN_EXPR (orig_insn
)));
1665 if (REGNO (best_reg
) != REGNO (INSN_LHS (orig_insn
))
1666 && (! replace_src_with_reg_ok_p (orig_insn
, best_reg
)
1667 || ! replace_dest_with_reg_ok_p (orig_insn
, best_reg
)))
1671 /* Make sure that EXPR has the right destination
1673 if (expr_dest_regno (expr
) != REGNO (best_reg
))
1674 replace_dest_with_reg_in_expr (expr
, best_reg
);
1676 EXPR_TARGET_AVAILABLE (expr
) = 1;
1681 /* Select and assign best register to EXPR searching from BNDS.
1682 Set *IS_ORIG_REG_P to TRUE if original register was selected.
1683 Return FALSE if no register can be chosen, which could happen when:
1684 * EXPR_SEPARABLE_P is true but we were unable to find suitable register;
1685 * EXPR_SEPARABLE_P is false but the insn sets/clobbers one of the registers
1686 that are used on the moving path. */
1688 find_best_reg_for_expr (expr_t expr
, blist_t bnds
, bool *is_orig_reg_p
)
1690 static struct reg_rename reg_rename_data
;
1693 def_list_t original_insns
= NULL
;
1696 *is_orig_reg_p
= false;
1698 /* Don't bother to do anything if this insn doesn't set any registers. */
1699 if (bitmap_empty_p (VINSN_REG_SETS (EXPR_VINSN (expr
)))
1700 && bitmap_empty_p (VINSN_REG_CLOBBERS (EXPR_VINSN (expr
))))
1703 used_regs
= get_clear_regset_from_pool ();
1704 CLEAR_HARD_REG_SET (reg_rename_data
.unavailable_hard_regs
);
1706 collect_unavailable_regs_from_bnds (expr
, bnds
, used_regs
, ®_rename_data
,
1709 #ifdef ENABLE_CHECKING
1710 /* If after reload, make sure we're working with hard regs here. */
1711 if (reload_completed
)
1713 reg_set_iterator rsi
;
1716 EXECUTE_IF_SET_IN_REG_SET (used_regs
, FIRST_PSEUDO_REGISTER
, i
, rsi
)
1721 if (EXPR_SEPARABLE_P (expr
))
1723 rtx best_reg
= NULL_RTX
;
1724 /* Check that we have computed availability of a target register
1726 verify_target_availability (expr
, used_regs
, ®_rename_data
);
1728 /* Turn everything in hard regs after reload. */
1729 if (reload_completed
)
1731 HARD_REG_SET hard_regs_used
;
1732 REG_SET_TO_HARD_REG_SET (hard_regs_used
, used_regs
);
1734 /* Join hard registers unavailable due to register class
1735 restrictions and live range intersection. */
1736 IOR_HARD_REG_SET (hard_regs_used
,
1737 reg_rename_data
.unavailable_hard_regs
);
1739 best_reg
= choose_best_reg (hard_regs_used
, ®_rename_data
,
1740 original_insns
, is_orig_reg_p
);
1743 best_reg
= choose_best_pseudo_reg (used_regs
, ®_rename_data
,
1744 original_insns
, is_orig_reg_p
);
1748 else if (*is_orig_reg_p
)
1750 /* In case of unification BEST_REG may be different from EXPR's LHS
1751 when EXPR's LHS is unavailable, and there is another LHS among
1753 reg_ok
= try_replace_dest_reg (original_insns
, best_reg
, expr
);
1757 /* Forbid renaming of low-cost insns. */
1758 if (sel_vinsn_cost (EXPR_VINSN (expr
)) < 2)
1761 reg_ok
= try_replace_dest_reg (original_insns
, best_reg
, expr
);
1766 /* If !EXPR_SCHEDULE_AS_RHS (EXPR), just make sure INSN doesn't set
1767 any of the HARD_REGS_USED set. */
1768 if (vinsn_writes_one_of_regs_p (EXPR_VINSN (expr
), used_regs
,
1769 reg_rename_data
.unavailable_hard_regs
))
1772 gcc_assert (EXPR_TARGET_AVAILABLE (expr
) <= 0);
1777 gcc_assert (EXPR_TARGET_AVAILABLE (expr
) != 0);
1781 ilist_clear (&original_insns
);
1782 return_regset_to_pool (used_regs
);
1788 /* Return true if dependence described by DS can be overcomed. */
1790 can_speculate_dep_p (ds_t ds
)
1792 if (spec_info
== NULL
)
1795 /* Leave only speculative data. */
1802 /* FIXME: make sched-deps.c produce only those non-hard dependencies,
1803 that we can overcome. */
1804 ds_t spec_mask
= spec_info
->mask
;
1806 if ((ds
& spec_mask
) != ds
)
1810 if (ds_weak (ds
) < spec_info
->data_weakness_cutoff
)
1816 /* Get a speculation check instruction.
1817 C_EXPR is a speculative expression,
1818 CHECK_DS describes speculations that should be checked,
1819 ORIG_INSN is the original non-speculative insn in the stream. */
1821 create_speculation_check (expr_t c_expr
, ds_t check_ds
, insn_t orig_insn
)
1826 basic_block recovery_block
;
1829 /* Create a recovery block if target is going to emit branchy check, or if
1830 ORIG_INSN was speculative already. */
1831 if (targetm
.sched
.needs_block_p (check_ds
)
1832 || EXPR_SPEC_DONE_DS (INSN_EXPR (orig_insn
)) != 0)
1834 recovery_block
= sel_create_recovery_block (orig_insn
);
1835 label
= BB_HEAD (recovery_block
);
1839 recovery_block
= NULL
;
1843 /* Get pattern of the check. */
1844 check_pattern
= targetm
.sched
.gen_spec_check (EXPR_INSN_RTX (c_expr
), label
,
1847 gcc_assert (check_pattern
!= NULL
);
1850 insn_rtx
= create_insn_rtx_from_pattern (check_pattern
, label
);
1852 insn
= sel_gen_insn_from_rtx_after (insn_rtx
, INSN_EXPR (orig_insn
),
1853 INSN_SEQNO (orig_insn
), orig_insn
);
1855 /* Make check to be non-speculative. */
1856 EXPR_SPEC_DONE_DS (INSN_EXPR (insn
)) = 0;
1857 INSN_SPEC_CHECKED_DS (insn
) = check_ds
;
1859 /* Decrease priority of check by difference of load/check instruction
1861 EXPR_PRIORITY (INSN_EXPR (insn
)) -= (sel_vinsn_cost (INSN_VINSN (orig_insn
))
1862 - sel_vinsn_cost (INSN_VINSN (insn
)));
1864 /* Emit copy of original insn (though with replaced target register,
1865 if needed) to the recovery block. */
1866 if (recovery_block
!= NULL
)
1870 twin_rtx
= copy_rtx (PATTERN (EXPR_INSN_RTX (c_expr
)));
1871 twin_rtx
= create_insn_rtx_from_pattern (twin_rtx
, NULL_RTX
);
1872 sel_gen_recovery_insn_from_rtx_after (twin_rtx
,
1873 INSN_EXPR (orig_insn
),
1875 bb_note (recovery_block
));
1878 /* If we've generated a data speculation check, make sure
1879 that all the bookkeeping instruction we'll create during
1880 this move_op () will allocate an ALAT entry so that the
1882 In case of control speculation we must convert C_EXPR to control
1883 speculative mode, because failing to do so will bring us an exception
1884 thrown by the non-control-speculative load. */
1885 check_ds
= ds_get_max_dep_weak (check_ds
);
1886 speculate_expr (c_expr
, check_ds
);
1891 /* True when INSN is a "regN = regN" copy. */
1893 identical_copy_p (rtx insn
)
1897 pat
= PATTERN (insn
);
1899 if (GET_CODE (pat
) != SET
)
1902 lhs
= SET_DEST (pat
);
1906 rhs
= SET_SRC (pat
);
1910 return REGNO (lhs
) == REGNO (rhs
);
1913 /* Undo all transformations on *AV_PTR that were done when
1914 moving through INSN. */
1916 undo_transformations (av_set_t
*av_ptr
, rtx insn
)
1918 av_set_iterator av_iter
;
1920 av_set_t new_set
= NULL
;
1922 /* First, kill any EXPR that uses registers set by an insn. This is
1923 required for correctness. */
1924 FOR_EACH_EXPR_1 (expr
, av_iter
, av_ptr
)
1925 if (!sched_insns_conditions_mutex_p (insn
, EXPR_INSN_RTX (expr
))
1926 && bitmap_intersect_p (INSN_REG_SETS (insn
),
1927 VINSN_REG_USES (EXPR_VINSN (expr
)))
1928 /* When an insn looks like 'r1 = r1', we could substitute through
1929 it, but the above condition will still hold. This happened with
1930 gcc.c-torture/execute/961125-1.c. */
1931 && !identical_copy_p (insn
))
1933 if (sched_verbose
>= 6)
1934 sel_print ("Expr %d removed due to use/set conflict\n",
1935 INSN_UID (EXPR_INSN_RTX (expr
)));
1936 av_set_iter_remove (&av_iter
);
1939 /* Undo transformations looking at the history vector. */
1940 FOR_EACH_EXPR (expr
, av_iter
, *av_ptr
)
1942 int index
= find_in_history_vect (EXPR_HISTORY_OF_CHANGES (expr
),
1943 insn
, EXPR_VINSN (expr
), true);
1947 expr_history_def
*phist
;
1949 phist
= VEC_index (expr_history_def
,
1950 EXPR_HISTORY_OF_CHANGES (expr
),
1953 switch (phist
->type
)
1955 case TRANS_SPECULATION
:
1957 ds_t old_ds
, new_ds
;
1959 /* Compute the difference between old and new speculative
1960 statuses: that's what we need to check.
1961 Earlier we used to assert that the status will really
1962 change. This no longer works because only the probability
1963 bits in the status may have changed during compute_av_set,
1964 and in the case of merging different probabilities of the
1965 same speculative status along different paths we do not
1966 record this in the history vector. */
1967 old_ds
= phist
->spec_ds
;
1968 new_ds
= EXPR_SPEC_DONE_DS (expr
);
1970 old_ds
&= SPECULATIVE
;
1971 new_ds
&= SPECULATIVE
;
1974 EXPR_SPEC_TO_CHECK_DS (expr
) |= new_ds
;
1977 case TRANS_SUBSTITUTION
:
1979 expr_def _tmp_expr
, *tmp_expr
= &_tmp_expr
;
1983 new_vi
= phist
->old_expr_vinsn
;
1985 gcc_assert (VINSN_SEPARABLE_P (new_vi
)
1986 == EXPR_SEPARABLE_P (expr
));
1987 copy_expr (tmp_expr
, expr
);
1989 if (vinsn_equal_p (phist
->new_expr_vinsn
,
1990 EXPR_VINSN (tmp_expr
)))
1991 change_vinsn_in_expr (tmp_expr
, new_vi
);
1993 /* This happens when we're unsubstituting on a bookkeeping
1994 copy, which was in turn substituted. The history is wrong
1995 in this case. Do it the hard way. */
1996 add
= substitute_reg_in_expr (tmp_expr
, insn
, true);
1998 av_set_add (&new_set
, tmp_expr
);
1999 clear_expr (tmp_expr
);
2009 av_set_union_and_clear (av_ptr
, &new_set
, NULL
);
2013 /* Moveup_* helpers for code motion and computing av sets. */
2015 /* Propagates EXPR inside an insn group through THROUGH_INSN.
2016 The difference from the below function is that only substitution is
2018 static enum MOVEUP_EXPR_CODE
2019 moveup_expr_inside_insn_group (expr_t expr
, insn_t through_insn
)
2021 vinsn_t vi
= EXPR_VINSN (expr
);
2025 /* Do this only inside insn group. */
2026 gcc_assert (INSN_SCHED_CYCLE (through_insn
) > 0);
2028 full_ds
= has_dependence_p (expr
, through_insn
, &has_dep_p
);
2030 return MOVEUP_EXPR_SAME
;
2032 /* Substitution is the possible choice in this case. */
2033 if (has_dep_p
[DEPS_IN_RHS
])
2035 /* Can't substitute UNIQUE VINSNs. */
2036 gcc_assert (!VINSN_UNIQUE_P (vi
));
2038 if (can_substitute_through_p (through_insn
,
2039 has_dep_p
[DEPS_IN_RHS
])
2040 && substitute_reg_in_expr (expr
, through_insn
, false))
2042 EXPR_WAS_SUBSTITUTED (expr
) = true;
2043 return MOVEUP_EXPR_CHANGED
;
2046 /* Don't care about this, as even true dependencies may be allowed
2047 in an insn group. */
2048 return MOVEUP_EXPR_SAME
;
2051 /* This can catch output dependencies in COND_EXECs. */
2052 if (has_dep_p
[DEPS_IN_INSN
])
2053 return MOVEUP_EXPR_NULL
;
2055 /* This is either an output or an anti dependence, which usually have
2056 a zero latency. Allow this here, if we'd be wrong, tick_check_p
2058 gcc_assert (has_dep_p
[DEPS_IN_LHS
]);
2059 return MOVEUP_EXPR_AS_RHS
;
2062 /* True when a trapping EXPR cannot be moved through THROUGH_INSN. */
2063 #define CANT_MOVE_TRAPPING(expr, through_insn) \
2064 (VINSN_MAY_TRAP_P (EXPR_VINSN (expr)) \
2065 && !sel_insn_has_single_succ_p ((through_insn), SUCCS_ALL) \
2066 && !sel_insn_is_speculation_check (through_insn))
2068 /* True when a conflict on a target register was found during moveup_expr. */
2069 static bool was_target_conflict
= false;
2071 /* Return true when moving a debug INSN across THROUGH_INSN will
2072 create a bookkeeping block. We don't want to create such blocks,
2073 for they would cause codegen differences between compilations with
2074 and without debug info. */
2077 moving_insn_creates_bookkeeping_block_p (insn_t insn
,
2078 insn_t through_insn
)
2080 basic_block bbi
, bbt
;
2082 edge_iterator ei1
, ei2
;
2084 if (!bookkeeping_can_be_created_if_moved_through_p (through_insn
))
2086 if (sched_verbose
>= 9)
2087 sel_print ("no bookkeeping required: ");
2091 bbi
= BLOCK_FOR_INSN (insn
);
2093 if (EDGE_COUNT (bbi
->preds
) == 1)
2095 if (sched_verbose
>= 9)
2096 sel_print ("only one pred edge: ");
2100 bbt
= BLOCK_FOR_INSN (through_insn
);
2102 FOR_EACH_EDGE (e1
, ei1
, bbt
->succs
)
2104 FOR_EACH_EDGE (e2
, ei2
, bbi
->preds
)
2106 if (find_block_for_bookkeeping (e1
, e2
, TRUE
))
2108 if (sched_verbose
>= 9)
2109 sel_print ("found existing block: ");
2115 if (sched_verbose
>= 9)
2116 sel_print ("would create bookkeeping block: ");
2121 /* Modifies EXPR so it can be moved through the THROUGH_INSN,
2122 performing necessary transformations. Record the type of transformation
2123 made in PTRANS_TYPE, when it is not NULL. When INSIDE_INSN_GROUP,
2124 permit all dependencies except true ones, and try to remove those
2125 too via forward substitution. All cases when a non-eliminable
2126 non-zero cost dependency exists inside an insn group will be fixed
2127 in tick_check_p instead. */
2128 static enum MOVEUP_EXPR_CODE
2129 moveup_expr (expr_t expr
, insn_t through_insn
, bool inside_insn_group
,
2130 enum local_trans_type
*ptrans_type
)
2132 vinsn_t vi
= EXPR_VINSN (expr
);
2133 insn_t insn
= VINSN_INSN_RTX (vi
);
2134 bool was_changed
= false;
2135 bool as_rhs
= false;
2139 /* When inside_insn_group, delegate to the helper. */
2140 if (inside_insn_group
)
2141 return moveup_expr_inside_insn_group (expr
, through_insn
);
2143 /* Deal with unique insns and control dependencies. */
2144 if (VINSN_UNIQUE_P (vi
))
2146 /* We can move jumps without side-effects or jumps that are
2147 mutually exclusive with instruction THROUGH_INSN (all in cases
2148 dependencies allow to do so and jump is not speculative). */
2149 if (control_flow_insn_p (insn
))
2151 basic_block fallthru_bb
;
2153 /* Do not move checks and do not move jumps through other
2155 if (control_flow_insn_p (through_insn
)
2156 || sel_insn_is_speculation_check (insn
))
2157 return MOVEUP_EXPR_NULL
;
2159 /* Don't move jumps through CFG joins. */
2160 if (bookkeeping_can_be_created_if_moved_through_p (through_insn
))
2161 return MOVEUP_EXPR_NULL
;
2163 /* The jump should have a clear fallthru block, and
2164 this block should be in the current region. */
2165 if ((fallthru_bb
= fallthru_bb_of_jump (insn
)) == NULL
2166 || ! in_current_region_p (fallthru_bb
))
2167 return MOVEUP_EXPR_NULL
;
2169 /* And it should be mutually exclusive with through_insn, or
2170 be an unconditional jump. */
2171 if (! any_uncondjump_p (insn
)
2172 && ! sched_insns_conditions_mutex_p (insn
, through_insn
)
2173 && ! DEBUG_INSN_P (through_insn
))
2174 return MOVEUP_EXPR_NULL
;
2177 /* Don't move what we can't move. */
2178 if (EXPR_CANT_MOVE (expr
)
2179 && BLOCK_FOR_INSN (through_insn
) != BLOCK_FOR_INSN (insn
))
2180 return MOVEUP_EXPR_NULL
;
2182 /* Don't move SCHED_GROUP instruction through anything.
2183 If we don't force this, then it will be possible to start
2184 scheduling a sched_group before all its dependencies are
2186 ??? Haifa deals with this issue by delaying the SCHED_GROUP
2187 as late as possible through rank_for_schedule. */
2188 if (SCHED_GROUP_P (insn
))
2189 return MOVEUP_EXPR_NULL
;
2192 gcc_assert (!control_flow_insn_p (insn
));
2194 /* Don't move debug insns if this would require bookkeeping. */
2195 if (DEBUG_INSN_P (insn
)
2196 && BLOCK_FOR_INSN (through_insn
) != BLOCK_FOR_INSN (insn
)
2197 && moving_insn_creates_bookkeeping_block_p (insn
, through_insn
))
2198 return MOVEUP_EXPR_NULL
;
2200 /* Deal with data dependencies. */
2201 was_target_conflict
= false;
2202 full_ds
= has_dependence_p (expr
, through_insn
, &has_dep_p
);
2205 if (!CANT_MOVE_TRAPPING (expr
, through_insn
))
2206 return MOVEUP_EXPR_SAME
;
2210 /* We can move UNIQUE insn up only as a whole and unchanged,
2211 so it shouldn't have any dependencies. */
2212 if (VINSN_UNIQUE_P (vi
))
2213 return MOVEUP_EXPR_NULL
;
2216 if (full_ds
!= 0 && can_speculate_dep_p (full_ds
))
2220 res
= speculate_expr (expr
, full_ds
);
2223 /* Speculation was successful. */
2225 was_changed
= (res
> 0);
2227 was_target_conflict
= true;
2229 *ptrans_type
= TRANS_SPECULATION
;
2230 sel_clear_has_dependence ();
2234 if (has_dep_p
[DEPS_IN_INSN
])
2235 /* We have some dependency that cannot be discarded. */
2236 return MOVEUP_EXPR_NULL
;
2238 if (has_dep_p
[DEPS_IN_LHS
])
2240 /* Only separable insns can be moved up with the new register.
2241 Anyways, we should mark that the original register is
2243 if (!enable_schedule_as_rhs_p
|| !EXPR_SEPARABLE_P (expr
))
2244 return MOVEUP_EXPR_NULL
;
2246 EXPR_TARGET_AVAILABLE (expr
) = false;
2247 was_target_conflict
= true;
2251 /* At this point we have either separable insns, that will be lifted
2252 up only as RHSes, or non-separable insns with no dependency in lhs.
2253 If dependency is in RHS, then try to perform substitution and move up
2260 In Ex.1 y*2 can be substituted for x*2 and the whole operation can be
2261 moved above y=x assignment as z=x*2.
2263 In Ex.2 y*2 also can be substituted for x*2, but only the right hand
2264 side can be moved because of the output dependency. The operation was
2265 cropped to its rhs above. */
2266 if (has_dep_p
[DEPS_IN_RHS
])
2268 ds_t
*rhs_dsp
= &has_dep_p
[DEPS_IN_RHS
];
2270 /* Can't substitute UNIQUE VINSNs. */
2271 gcc_assert (!VINSN_UNIQUE_P (vi
));
2273 if (can_speculate_dep_p (*rhs_dsp
))
2277 res
= speculate_expr (expr
, *rhs_dsp
);
2280 /* Speculation was successful. */
2282 was_changed
= (res
> 0);
2284 was_target_conflict
= true;
2286 *ptrans_type
= TRANS_SPECULATION
;
2289 return MOVEUP_EXPR_NULL
;
2291 else if (can_substitute_through_p (through_insn
,
2293 && substitute_reg_in_expr (expr
, through_insn
, false))
2295 /* ??? We cannot perform substitution AND speculation on the same
2297 gcc_assert (!was_changed
);
2300 *ptrans_type
= TRANS_SUBSTITUTION
;
2301 EXPR_WAS_SUBSTITUTED (expr
) = true;
2304 return MOVEUP_EXPR_NULL
;
2307 /* Don't move trapping insns through jumps.
2308 This check should be at the end to give a chance to control speculation
2309 to perform its duties. */
2310 if (CANT_MOVE_TRAPPING (expr
, through_insn
))
2311 return MOVEUP_EXPR_NULL
;
2314 ? MOVEUP_EXPR_CHANGED
2316 ? MOVEUP_EXPR_AS_RHS
2317 : MOVEUP_EXPR_SAME
));
2320 /* Try to look at bitmap caches for EXPR and INSN pair, return true
2321 if successful. When INSIDE_INSN_GROUP, also try ignore dependencies
2322 that can exist within a parallel group. Write to RES the resulting
2323 code for moveup_expr. */
2325 try_bitmap_cache (expr_t expr
, insn_t insn
,
2326 bool inside_insn_group
,
2327 enum MOVEUP_EXPR_CODE
*res
)
2329 int expr_uid
= INSN_UID (EXPR_INSN_RTX (expr
));
2331 /* First check whether we've analyzed this situation already. */
2332 if (bitmap_bit_p (INSN_ANALYZED_DEPS (insn
), expr_uid
))
2334 if (bitmap_bit_p (INSN_FOUND_DEPS (insn
), expr_uid
))
2336 if (sched_verbose
>= 6)
2337 sel_print ("removed (cached)\n");
2338 *res
= MOVEUP_EXPR_NULL
;
2343 if (sched_verbose
>= 6)
2344 sel_print ("unchanged (cached)\n");
2345 *res
= MOVEUP_EXPR_SAME
;
2349 else if (bitmap_bit_p (INSN_FOUND_DEPS (insn
), expr_uid
))
2351 if (inside_insn_group
)
2353 if (sched_verbose
>= 6)
2354 sel_print ("unchanged (as RHS, cached, inside insn group)\n");
2355 *res
= MOVEUP_EXPR_SAME
;
2360 EXPR_TARGET_AVAILABLE (expr
) = false;
2362 /* This is the only case when propagation result can change over time,
2363 as we can dynamically switch off scheduling as RHS. In this case,
2364 just check the flag to reach the correct decision. */
2365 if (enable_schedule_as_rhs_p
)
2367 if (sched_verbose
>= 6)
2368 sel_print ("unchanged (as RHS, cached)\n");
2369 *res
= MOVEUP_EXPR_AS_RHS
;
2374 if (sched_verbose
>= 6)
2375 sel_print ("removed (cached as RHS, but renaming"
2376 " is now disabled)\n");
2377 *res
= MOVEUP_EXPR_NULL
;
2385 /* Try to look at bitmap caches for EXPR and INSN pair, return true
2386 if successful. Write to RES the resulting code for moveup_expr. */
2388 try_transformation_cache (expr_t expr
, insn_t insn
,
2389 enum MOVEUP_EXPR_CODE
*res
)
2391 struct transformed_insns
*pti
2392 = (struct transformed_insns
*)
2393 htab_find_with_hash (INSN_TRANSFORMED_INSNS (insn
),
2395 VINSN_HASH_RTX (EXPR_VINSN (expr
)));
2398 /* This EXPR was already moved through this insn and was
2399 changed as a result. Fetch the proper data from
2401 insert_in_history_vect (&EXPR_HISTORY_OF_CHANGES (expr
),
2402 INSN_UID (insn
), pti
->type
,
2403 pti
->vinsn_old
, pti
->vinsn_new
,
2404 EXPR_SPEC_DONE_DS (expr
));
2406 if (INSN_IN_STREAM_P (VINSN_INSN_RTX (pti
->vinsn_new
)))
2407 pti
->vinsn_new
= vinsn_copy (pti
->vinsn_new
, true);
2408 change_vinsn_in_expr (expr
, pti
->vinsn_new
);
2409 if (pti
->was_target_conflict
)
2410 EXPR_TARGET_AVAILABLE (expr
) = false;
2411 if (pti
->type
== TRANS_SPECULATION
)
2413 EXPR_SPEC_DONE_DS (expr
) = pti
->ds
;
2414 EXPR_NEEDS_SPEC_CHECK_P (expr
) |= pti
->needs_check
;
2417 if (sched_verbose
>= 6)
2419 sel_print ("changed (cached): ");
2424 *res
= MOVEUP_EXPR_CHANGED
;
2431 /* Update bitmap caches on INSN with result RES of propagating EXPR. */
2433 update_bitmap_cache (expr_t expr
, insn_t insn
, bool inside_insn_group
,
2434 enum MOVEUP_EXPR_CODE res
)
2436 int expr_uid
= INSN_UID (EXPR_INSN_RTX (expr
));
2438 /* Do not cache result of propagating jumps through an insn group,
2439 as it is always true, which is not useful outside the group. */
2440 if (inside_insn_group
)
2443 if (res
== MOVEUP_EXPR_NULL
)
2445 bitmap_set_bit (INSN_ANALYZED_DEPS (insn
), expr_uid
);
2446 bitmap_set_bit (INSN_FOUND_DEPS (insn
), expr_uid
);
2448 else if (res
== MOVEUP_EXPR_SAME
)
2450 bitmap_set_bit (INSN_ANALYZED_DEPS (insn
), expr_uid
);
2451 bitmap_clear_bit (INSN_FOUND_DEPS (insn
), expr_uid
);
2453 else if (res
== MOVEUP_EXPR_AS_RHS
)
2455 bitmap_clear_bit (INSN_ANALYZED_DEPS (insn
), expr_uid
);
2456 bitmap_set_bit (INSN_FOUND_DEPS (insn
), expr_uid
);
2462 /* Update hashtable on INSN with changed EXPR, old EXPR_OLD_VINSN
2463 and transformation type TRANS_TYPE. */
2465 update_transformation_cache (expr_t expr
, insn_t insn
,
2466 bool inside_insn_group
,
2467 enum local_trans_type trans_type
,
2468 vinsn_t expr_old_vinsn
)
2470 struct transformed_insns
*pti
;
2472 if (inside_insn_group
)
2475 pti
= XNEW (struct transformed_insns
);
2476 pti
->vinsn_old
= expr_old_vinsn
;
2477 pti
->vinsn_new
= EXPR_VINSN (expr
);
2478 pti
->type
= trans_type
;
2479 pti
->was_target_conflict
= was_target_conflict
;
2480 pti
->ds
= EXPR_SPEC_DONE_DS (expr
);
2481 pti
->needs_check
= EXPR_NEEDS_SPEC_CHECK_P (expr
);
2482 vinsn_attach (pti
->vinsn_old
);
2483 vinsn_attach (pti
->vinsn_new
);
2484 *((struct transformed_insns
**)
2485 htab_find_slot_with_hash (INSN_TRANSFORMED_INSNS (insn
),
2486 pti
, VINSN_HASH_RTX (expr_old_vinsn
),
2490 /* Same as moveup_expr, but first looks up the result of
2491 transformation in caches. */
2492 static enum MOVEUP_EXPR_CODE
2493 moveup_expr_cached (expr_t expr
, insn_t insn
, bool inside_insn_group
)
2495 enum MOVEUP_EXPR_CODE res
;
2496 bool got_answer
= false;
2498 if (sched_verbose
>= 6)
2500 sel_print ("Moving ");
2502 sel_print (" through %d: ", INSN_UID (insn
));
2505 if (DEBUG_INSN_P (EXPR_INSN_RTX (expr
))
2506 && (sel_bb_head (BLOCK_FOR_INSN (EXPR_INSN_RTX (expr
)))
2507 == EXPR_INSN_RTX (expr
)))
2508 /* Don't use cached information for debug insns that are heads of
2510 else if (try_bitmap_cache (expr
, insn
, inside_insn_group
, &res
))
2511 /* When inside insn group, we do not want remove stores conflicting
2512 with previosly issued loads. */
2513 got_answer
= ! inside_insn_group
|| res
!= MOVEUP_EXPR_NULL
;
2514 else if (try_transformation_cache (expr
, insn
, &res
))
2519 /* Invoke moveup_expr and record the results. */
2520 vinsn_t expr_old_vinsn
= EXPR_VINSN (expr
);
2521 ds_t expr_old_spec_ds
= EXPR_SPEC_DONE_DS (expr
);
2522 int expr_uid
= INSN_UID (VINSN_INSN_RTX (expr_old_vinsn
));
2523 bool unique_p
= VINSN_UNIQUE_P (expr_old_vinsn
);
2524 enum local_trans_type trans_type
= TRANS_SUBSTITUTION
;
2526 /* ??? Invent something better than this. We can't allow old_vinsn
2527 to go, we need it for the history vector. */
2528 vinsn_attach (expr_old_vinsn
);
2530 res
= moveup_expr (expr
, insn
, inside_insn_group
,
2534 case MOVEUP_EXPR_NULL
:
2535 update_bitmap_cache (expr
, insn
, inside_insn_group
, res
);
2536 if (sched_verbose
>= 6)
2537 sel_print ("removed\n");
2540 case MOVEUP_EXPR_SAME
:
2541 update_bitmap_cache (expr
, insn
, inside_insn_group
, res
);
2542 if (sched_verbose
>= 6)
2543 sel_print ("unchanged\n");
2546 case MOVEUP_EXPR_AS_RHS
:
2547 gcc_assert (!unique_p
|| inside_insn_group
);
2548 update_bitmap_cache (expr
, insn
, inside_insn_group
, res
);
2549 if (sched_verbose
>= 6)
2550 sel_print ("unchanged (as RHS)\n");
2553 case MOVEUP_EXPR_CHANGED
:
2554 gcc_assert (INSN_UID (EXPR_INSN_RTX (expr
)) != expr_uid
2555 || EXPR_SPEC_DONE_DS (expr
) != expr_old_spec_ds
);
2556 insert_in_history_vect (&EXPR_HISTORY_OF_CHANGES (expr
),
2557 INSN_UID (insn
), trans_type
,
2558 expr_old_vinsn
, EXPR_VINSN (expr
),
2560 update_transformation_cache (expr
, insn
, inside_insn_group
,
2561 trans_type
, expr_old_vinsn
);
2562 if (sched_verbose
>= 6)
2564 sel_print ("changed: ");
2573 vinsn_detach (expr_old_vinsn
);
2579 /* Moves an av set AVP up through INSN, performing necessary
2582 moveup_set_expr (av_set_t
*avp
, insn_t insn
, bool inside_insn_group
)
2587 FOR_EACH_EXPR_1 (expr
, i
, avp
)
2590 switch (moveup_expr_cached (expr
, insn
, inside_insn_group
))
2592 case MOVEUP_EXPR_SAME
:
2593 case MOVEUP_EXPR_AS_RHS
:
2596 case MOVEUP_EXPR_NULL
:
2597 av_set_iter_remove (&i
);
2600 case MOVEUP_EXPR_CHANGED
:
2601 expr
= merge_with_other_exprs (avp
, &i
, expr
);
2610 /* Moves AVP set along PATH. */
2612 moveup_set_inside_insn_group (av_set_t
*avp
, ilist_t path
)
2616 if (sched_verbose
>= 6)
2617 sel_print ("Moving expressions up in the insn group...\n");
2620 last_cycle
= INSN_SCHED_CYCLE (ILIST_INSN (path
));
2622 && INSN_SCHED_CYCLE (ILIST_INSN (path
)) == last_cycle
)
2624 moveup_set_expr (avp
, ILIST_INSN (path
), true);
2625 path
= ILIST_NEXT (path
);
2629 /* Returns true if after moving EXPR along PATH it equals to EXPR_VLIW. */
2631 equal_after_moveup_path_p (expr_t expr
, ilist_t path
, expr_t expr_vliw
)
2633 expr_def _tmp
, *tmp
= &_tmp
;
2637 copy_expr_onside (tmp
, expr
);
2638 last_cycle
= path
? INSN_SCHED_CYCLE (ILIST_INSN (path
)) : 0;
2641 && INSN_SCHED_CYCLE (ILIST_INSN (path
)) == last_cycle
)
2643 res
= (moveup_expr_cached (tmp
, ILIST_INSN (path
), true)
2644 != MOVEUP_EXPR_NULL
);
2645 path
= ILIST_NEXT (path
);
2650 vinsn_t tmp_vinsn
= EXPR_VINSN (tmp
);
2651 vinsn_t expr_vliw_vinsn
= EXPR_VINSN (expr_vliw
);
2653 if (tmp_vinsn
!= expr_vliw_vinsn
)
2654 res
= vinsn_equal_p (tmp_vinsn
, expr_vliw_vinsn
);
2662 /* Functions that compute av and lv sets. */
2664 /* Returns true if INSN is not a downward continuation of the given path P in
2665 the current stage. */
2667 is_ineligible_successor (insn_t insn
, ilist_t p
)
2671 /* Check if insn is not deleted. */
2672 if (PREV_INSN (insn
) && NEXT_INSN (PREV_INSN (insn
)) != insn
)
2674 else if (NEXT_INSN (insn
) && PREV_INSN (NEXT_INSN (insn
)) != insn
)
2677 /* If it's the first insn visited, then the successor is ok. */
2681 prev_insn
= ILIST_INSN (p
);
2683 if (/* a backward edge. */
2684 INSN_SEQNO (insn
) < INSN_SEQNO (prev_insn
)
2685 /* is already visited. */
2686 || (INSN_SEQNO (insn
) == INSN_SEQNO (prev_insn
)
2687 && (ilist_is_in_p (p
, insn
)
2688 /* We can reach another fence here and still seqno of insn
2689 would be equal to seqno of prev_insn. This is possible
2690 when prev_insn is a previously created bookkeeping copy.
2691 In that case it'd get a seqno of insn. Thus, check here
2692 whether insn is in current fence too. */
2693 || IN_CURRENT_FENCE_P (insn
)))
2694 /* Was already scheduled on this round. */
2695 || (INSN_SEQNO (insn
) > INSN_SEQNO (prev_insn
)
2696 && IN_CURRENT_FENCE_P (insn
))
2697 /* An insn from another fence could also be
2698 scheduled earlier even if this insn is not in
2699 a fence list right now. Check INSN_SCHED_CYCLE instead. */
2701 && INSN_SCHED_TIMES (insn
) > 0))
2707 /* Computes the av_set below the last bb insn INSN, doing all the 'dirty work'
2708 of handling multiple successors and properly merging its av_sets. P is
2709 the current path traversed. WS is the size of lookahead window.
2710 Return the av set computed. */
2712 compute_av_set_at_bb_end (insn_t insn
, ilist_t p
, int ws
)
2714 struct succs_info
*sinfo
;
2715 av_set_t expr_in_all_succ_branches
= NULL
;
2717 insn_t succ
, zero_succ
= NULL
;
2718 av_set_t av1
= NULL
;
2720 gcc_assert (sel_bb_end_p (insn
));
2722 /* Find different kind of successors needed for correct computing of
2723 SPEC and TARGET_AVAILABLE attributes. */
2724 sinfo
= compute_succs_info (insn
, SUCCS_NORMAL
);
2727 if (sched_verbose
>= 6)
2729 sel_print ("successors of bb end (%d): ", INSN_UID (insn
));
2730 dump_insn_vector (sinfo
->succs_ok
);
2732 if (sinfo
->succs_ok_n
!= sinfo
->all_succs_n
)
2733 sel_print ("real successors num: %d\n", sinfo
->all_succs_n
);
2736 /* Add insn to to the tail of current path. */
2737 ilist_add (&p
, insn
);
2739 FOR_EACH_VEC_ELT (rtx
, sinfo
->succs_ok
, is
, succ
)
2743 /* We will edit SUCC_SET and EXPR_SPEC field of its elements. */
2744 succ_set
= compute_av_set_inside_bb (succ
, p
, ws
, true);
2746 av_set_split_usefulness (succ_set
,
2747 VEC_index (int, sinfo
->probs_ok
, is
),
2750 if (sinfo
->all_succs_n
> 1)
2752 /* Find EXPR'es that came from *all* successors and save them
2753 into expr_in_all_succ_branches. This set will be used later
2754 for calculating speculation attributes of EXPR'es. */
2757 expr_in_all_succ_branches
= av_set_copy (succ_set
);
2759 /* Remember the first successor for later. */
2767 FOR_EACH_EXPR_1 (expr
, i
, &expr_in_all_succ_branches
)
2768 if (!av_set_is_in_p (succ_set
, EXPR_VINSN (expr
)))
2769 av_set_iter_remove (&i
);
2773 /* Union the av_sets. Check liveness restrictions on target registers
2774 in special case of two successors. */
2775 if (sinfo
->succs_ok_n
== 2 && is
== 1)
2777 basic_block bb0
= BLOCK_FOR_INSN (zero_succ
);
2778 basic_block bb1
= BLOCK_FOR_INSN (succ
);
2780 gcc_assert (BB_LV_SET_VALID_P (bb0
) && BB_LV_SET_VALID_P (bb1
));
2781 av_set_union_and_live (&av1
, &succ_set
,
2787 av_set_union_and_clear (&av1
, &succ_set
, insn
);
2790 /* Check liveness restrictions via hard way when there are more than
2792 if (sinfo
->succs_ok_n
> 2)
2793 FOR_EACH_VEC_ELT (rtx
, sinfo
->succs_ok
, is
, succ
)
2795 basic_block succ_bb
= BLOCK_FOR_INSN (succ
);
2797 gcc_assert (BB_LV_SET_VALID_P (succ_bb
));
2798 mark_unavailable_targets (av1
, BB_AV_SET (succ_bb
),
2799 BB_LV_SET (succ_bb
));
2802 /* Finally, check liveness restrictions on paths leaving the region. */
2803 if (sinfo
->all_succs_n
> sinfo
->succs_ok_n
)
2804 FOR_EACH_VEC_ELT (rtx
, sinfo
->succs_other
, is
, succ
)
2805 mark_unavailable_targets
2806 (av1
, NULL
, BB_LV_SET (BLOCK_FOR_INSN (succ
)));
2808 if (sinfo
->all_succs_n
> 1)
2813 /* Increase the spec attribute of all EXPR'es that didn't come
2814 from all successors. */
2815 FOR_EACH_EXPR (expr
, i
, av1
)
2816 if (!av_set_is_in_p (expr_in_all_succ_branches
, EXPR_VINSN (expr
)))
2819 av_set_clear (&expr_in_all_succ_branches
);
2821 /* Do not move conditional branches through other
2822 conditional branches. So, remove all conditional
2823 branches from av_set if current operator is a conditional
2825 av_set_substract_cond_branches (&av1
);
2829 free_succs_info (sinfo
);
2831 if (sched_verbose
>= 6)
2833 sel_print ("av_succs (%d): ", INSN_UID (insn
));
2841 /* This function computes av_set for the FIRST_INSN by dragging valid
2842 av_set through all basic block insns either from the end of basic block
2843 (computed using compute_av_set_at_bb_end) or from the insn on which
2844 MAX_WS was exceeded. It uses compute_av_set_at_bb_end to compute av_set
2845 below the basic block and handling conditional branches.
2846 FIRST_INSN - the basic block head, P - path consisting of the insns
2847 traversed on the way to the FIRST_INSN (the path is sparse, only bb heads
2848 and bb ends are added to the path), WS - current window size,
2849 NEED_COPY_P - true if we'll make a copy of av_set before returning it. */
2851 compute_av_set_inside_bb (insn_t first_insn
, ilist_t p
, int ws
,
2856 insn_t bb_end
= sel_bb_end (BLOCK_FOR_INSN (first_insn
));
2857 insn_t after_bb_end
= NEXT_INSN (bb_end
);
2860 basic_block cur_bb
= BLOCK_FOR_INSN (first_insn
);
2862 /* Return NULL if insn is not on the legitimate downward path. */
2863 if (is_ineligible_successor (first_insn
, p
))
2865 if (sched_verbose
>= 6)
2866 sel_print ("Insn %d is ineligible_successor\n", INSN_UID (first_insn
));
2871 /* If insn already has valid av(insn) computed, just return it. */
2872 if (AV_SET_VALID_P (first_insn
))
2876 if (sel_bb_head_p (first_insn
))
2877 av_set
= BB_AV_SET (BLOCK_FOR_INSN (first_insn
));
2881 if (sched_verbose
>= 6)
2883 sel_print ("Insn %d has a valid av set: ", INSN_UID (first_insn
));
2884 dump_av_set (av_set
);
2888 return need_copy_p
? av_set_copy (av_set
) : av_set
;
2891 ilist_add (&p
, first_insn
);
2893 /* As the result after this loop have completed, in LAST_INSN we'll
2894 have the insn which has valid av_set to start backward computation
2895 from: it either will be NULL because on it the window size was exceeded
2896 or other valid av_set as returned by compute_av_set for the last insn
2897 of the basic block. */
2898 for (last_insn
= first_insn
; last_insn
!= after_bb_end
;
2899 last_insn
= NEXT_INSN (last_insn
))
2901 /* We may encounter valid av_set not only on bb_head, but also on
2902 those insns on which previously MAX_WS was exceeded. */
2903 if (AV_SET_VALID_P (last_insn
))
2905 if (sched_verbose
>= 6)
2906 sel_print ("Insn %d has a valid empty av set\n", INSN_UID (last_insn
));
2910 /* The special case: the last insn of the BB may be an
2911 ineligible_successor due to its SEQ_NO that was set on
2912 it as a bookkeeping. */
2913 if (last_insn
!= first_insn
2914 && is_ineligible_successor (last_insn
, p
))
2916 if (sched_verbose
>= 6)
2917 sel_print ("Insn %d is ineligible_successor\n", INSN_UID (last_insn
));
2921 if (DEBUG_INSN_P (last_insn
))
2924 if (end_ws
> max_ws
)
2926 /* We can reach max lookahead size at bb_header, so clean av_set
2928 INSN_WS_LEVEL (last_insn
) = global_level
;
2930 if (sched_verbose
>= 6)
2931 sel_print ("Insn %d is beyond the software lookahead window size\n",
2932 INSN_UID (last_insn
));
2939 /* Get the valid av_set into AV above the LAST_INSN to start backward
2940 computation from. It either will be empty av_set or av_set computed from
2941 the successors on the last insn of the current bb. */
2942 if (last_insn
!= after_bb_end
)
2946 /* This is needed only to obtain av_sets that are identical to
2947 those computed by the old compute_av_set version. */
2948 if (last_insn
== first_insn
&& !INSN_NOP_P (last_insn
))
2949 av_set_add (&av
, INSN_EXPR (last_insn
));
2952 /* END_WS is always already increased by 1 if LAST_INSN == AFTER_BB_END. */
2953 av
= compute_av_set_at_bb_end (bb_end
, p
, end_ws
);
2955 /* Compute av_set in AV starting from below the LAST_INSN up to
2956 location above the FIRST_INSN. */
2957 for (cur_insn
= PREV_INSN (last_insn
); cur_insn
!= PREV_INSN (first_insn
);
2958 cur_insn
= PREV_INSN (cur_insn
))
2959 if (!INSN_NOP_P (cur_insn
))
2963 moveup_set_expr (&av
, cur_insn
, false);
2965 /* If the expression for CUR_INSN is already in the set,
2966 replace it by the new one. */
2967 expr
= av_set_lookup (av
, INSN_VINSN (cur_insn
));
2971 copy_expr (expr
, INSN_EXPR (cur_insn
));
2974 av_set_add (&av
, INSN_EXPR (cur_insn
));
2977 /* Clear stale bb_av_set. */
2978 if (sel_bb_head_p (first_insn
))
2980 av_set_clear (&BB_AV_SET (cur_bb
));
2981 BB_AV_SET (cur_bb
) = need_copy_p
? av_set_copy (av
) : av
;
2982 BB_AV_LEVEL (cur_bb
) = global_level
;
2985 if (sched_verbose
>= 6)
2987 sel_print ("Computed av set for insn %d: ", INSN_UID (first_insn
));
2996 /* Compute av set before INSN.
2997 INSN - the current operation (actual rtx INSN)
2998 P - the current path, which is list of insns visited so far
2999 WS - software lookahead window size.
3000 UNIQUE_P - TRUE, if returned av_set will be changed, hence
3001 if we want to save computed av_set in s_i_d, we should make a copy of it.
3003 In the resulting set we will have only expressions that don't have delay
3004 stalls and nonsubstitutable dependences. */
3006 compute_av_set (insn_t insn
, ilist_t p
, int ws
, bool unique_p
)
3008 return compute_av_set_inside_bb (insn
, p
, ws
, unique_p
);
3011 /* Propagate a liveness set LV through INSN. */
3013 propagate_lv_set (regset lv
, insn_t insn
)
3015 gcc_assert (INSN_P (insn
));
3017 if (INSN_NOP_P (insn
))
3020 df_simulate_one_insn_backwards (BLOCK_FOR_INSN (insn
), insn
, lv
);
3023 /* Return livness set at the end of BB. */
3025 compute_live_after_bb (basic_block bb
)
3029 regset lv
= get_clear_regset_from_pool ();
3031 gcc_assert (!ignore_first
);
3033 FOR_EACH_EDGE (e
, ei
, bb
->succs
)
3034 if (sel_bb_empty_p (e
->dest
))
3036 if (! BB_LV_SET_VALID_P (e
->dest
))
3039 gcc_assert (BB_LV_SET (e
->dest
) == NULL
);
3040 BB_LV_SET (e
->dest
) = compute_live_after_bb (e
->dest
);
3041 BB_LV_SET_VALID_P (e
->dest
) = true;
3043 IOR_REG_SET (lv
, BB_LV_SET (e
->dest
));
3046 IOR_REG_SET (lv
, compute_live (sel_bb_head (e
->dest
)));
3051 /* Compute the set of all live registers at the point before INSN and save
3052 it at INSN if INSN is bb header. */
3054 compute_live (insn_t insn
)
3056 basic_block bb
= BLOCK_FOR_INSN (insn
);
3060 /* Return the valid set if we're already on it. */
3065 if (sel_bb_head_p (insn
) && BB_LV_SET_VALID_P (bb
))
3066 src
= BB_LV_SET (bb
);
3069 gcc_assert (in_current_region_p (bb
));
3070 if (INSN_LIVE_VALID_P (insn
))
3071 src
= INSN_LIVE (insn
);
3076 lv
= get_regset_from_pool ();
3077 COPY_REG_SET (lv
, src
);
3079 if (sel_bb_head_p (insn
) && ! BB_LV_SET_VALID_P (bb
))
3081 COPY_REG_SET (BB_LV_SET (bb
), lv
);
3082 BB_LV_SET_VALID_P (bb
) = true;
3085 return_regset_to_pool (lv
);
3090 /* We've skipped the wrong lv_set. Don't skip the right one. */
3091 ignore_first
= false;
3092 gcc_assert (in_current_region_p (bb
));
3094 /* Find a valid LV set in this block or below, if needed.
3095 Start searching from the next insn: either ignore_first is true, or
3096 INSN doesn't have a correct live set. */
3097 temp
= NEXT_INSN (insn
);
3098 final
= NEXT_INSN (BB_END (bb
));
3099 while (temp
!= final
&& ! INSN_LIVE_VALID_P (temp
))
3100 temp
= NEXT_INSN (temp
);
3103 lv
= compute_live_after_bb (bb
);
3104 temp
= PREV_INSN (temp
);
3108 lv
= get_regset_from_pool ();
3109 COPY_REG_SET (lv
, INSN_LIVE (temp
));
3112 /* Put correct lv sets on the insns which have bad sets. */
3113 final
= PREV_INSN (insn
);
3114 while (temp
!= final
)
3116 propagate_lv_set (lv
, temp
);
3117 COPY_REG_SET (INSN_LIVE (temp
), lv
);
3118 INSN_LIVE_VALID_P (temp
) = true;
3119 temp
= PREV_INSN (temp
);
3122 /* Also put it in a BB. */
3123 if (sel_bb_head_p (insn
))
3125 basic_block bb
= BLOCK_FOR_INSN (insn
);
3127 COPY_REG_SET (BB_LV_SET (bb
), lv
);
3128 BB_LV_SET_VALID_P (bb
) = true;
3131 /* We return LV to the pool, but will not clear it there. Thus we can
3132 legimatelly use LV till the next use of regset_pool_get (). */
3133 return_regset_to_pool (lv
);
3137 /* Update liveness sets for INSN. */
3139 update_liveness_on_insn (rtx insn
)
3141 ignore_first
= true;
3142 compute_live (insn
);
3145 /* Compute liveness below INSN and write it into REGS. */
3147 compute_live_below_insn (rtx insn
, regset regs
)
3152 FOR_EACH_SUCC_1 (succ
, si
, insn
, SUCCS_ALL
)
3153 IOR_REG_SET (regs
, compute_live (succ
));
3156 /* Update the data gathered in av and lv sets starting from INSN. */
3158 update_data_sets (rtx insn
)
3160 update_liveness_on_insn (insn
);
3161 if (sel_bb_head_p (insn
))
3163 gcc_assert (AV_LEVEL (insn
) != 0);
3164 BB_AV_LEVEL (BLOCK_FOR_INSN (insn
)) = -1;
3165 compute_av_set (insn
, NULL
, 0, 0);
3170 /* Helper for move_op () and find_used_regs ().
3171 Return speculation type for which a check should be created on the place
3172 of INSN. EXPR is one of the original ops we are searching for. */
3174 get_spec_check_type_for_insn (insn_t insn
, expr_t expr
)
3177 ds_t already_checked_ds
= EXPR_SPEC_DONE_DS (INSN_EXPR (insn
));
3179 to_check_ds
= EXPR_SPEC_TO_CHECK_DS (expr
);
3181 if (targetm
.sched
.get_insn_checked_ds
)
3182 already_checked_ds
|= targetm
.sched
.get_insn_checked_ds (insn
);
3184 if (spec_info
!= NULL
3185 && (spec_info
->flags
& SEL_SCHED_SPEC_DONT_CHECK_CONTROL
))
3186 already_checked_ds
|= BEGIN_CONTROL
;
3188 already_checked_ds
= ds_get_speculation_types (already_checked_ds
);
3190 to_check_ds
&= ~already_checked_ds
;
3195 /* Find the set of registers that are unavailable for storing expres
3196 while moving ORIG_OPS up on the path starting from INSN due to
3197 liveness (USED_REGS) or hardware restrictions (REG_RENAME_P).
3199 All the original operations found during the traversal are saved in the
3200 ORIGINAL_INSNS list.
3202 REG_RENAME_P denotes the set of hardware registers that
3203 can not be used with renaming due to the register class restrictions,
3204 mode restrictions and other (the register we'll choose should be
3205 compatible class with the original uses, shouldn't be in call_used_regs,
3206 should be HARD_REGNO_RENAME_OK etc).
3208 Returns TRUE if we've found all original insns, FALSE otherwise.
3210 This function utilizes code_motion_path_driver (formerly find_used_regs_1)
3211 to traverse the code motion paths. This helper function finds registers
3212 that are not available for storing expres while moving ORIG_OPS up on the
3213 path starting from INSN. A register considered as used on the moving path,
3214 if one of the following conditions is not satisfied:
3216 (1) a register not set or read on any path from xi to an instance of
3217 the original operation,
3218 (2) not among the live registers of the point immediately following the
3219 first original operation on a given downward path, except for the
3220 original target register of the operation,
3221 (3) not live on the other path of any conditional branch that is passed
3222 by the operation, in case original operations are not present on
3223 both paths of the conditional branch.
3225 All the original operations found during the traversal are saved in the
3226 ORIGINAL_INSNS list.
3228 REG_RENAME_P->CROSSES_CALL is true, if there is a call insn on the path
3229 from INSN to original insn. In this case CALL_USED_REG_SET will be added
3230 to unavailable hard regs at the point original operation is found. */
3233 find_used_regs (insn_t insn
, av_set_t orig_ops
, regset used_regs
,
3234 struct reg_rename
*reg_rename_p
, def_list_t
*original_insns
)
3236 def_list_iterator i
;
3239 bool needs_spec_check_p
= false;
3241 av_set_iterator expr_iter
;
3242 struct fur_static_params sparams
;
3243 struct cmpd_local_params lparams
;
3245 /* We haven't visited any blocks yet. */
3246 bitmap_clear (code_motion_visited_blocks
);
3248 /* Init parameters for code_motion_path_driver. */
3249 sparams
.crosses_call
= false;
3250 sparams
.original_insns
= original_insns
;
3251 sparams
.used_regs
= used_regs
;
3253 /* Set the appropriate hooks and data. */
3254 code_motion_path_driver_info
= &fur_hooks
;
3256 res
= code_motion_path_driver (insn
, orig_ops
, NULL
, &lparams
, &sparams
);
3258 reg_rename_p
->crosses_call
|= sparams
.crosses_call
;
3260 gcc_assert (res
== 1);
3261 gcc_assert (original_insns
&& *original_insns
);
3263 /* ??? We calculate whether an expression needs a check when computing
3264 av sets. This information is not as precise as it could be due to
3265 merging this bit in merge_expr. We can do better in find_used_regs,
3266 but we want to avoid multiple traversals of the same code motion
3268 FOR_EACH_EXPR (expr
, expr_iter
, orig_ops
)
3269 needs_spec_check_p
|= EXPR_NEEDS_SPEC_CHECK_P (expr
);
3271 /* Mark hardware regs in REG_RENAME_P that are not suitable
3272 for renaming expr in INSN due to hardware restrictions (register class,
3273 modes compatibility etc). */
3274 FOR_EACH_DEF (def
, i
, *original_insns
)
3276 vinsn_t vinsn
= INSN_VINSN (def
->orig_insn
);
3278 if (VINSN_SEPARABLE_P (vinsn
))
3279 mark_unavailable_hard_regs (def
, reg_rename_p
, used_regs
);
3281 /* Do not allow clobbering of ld.[sa] address in case some of the
3282 original operations need a check. */
3283 if (needs_spec_check_p
)
3284 IOR_REG_SET (used_regs
, VINSN_REG_USES (vinsn
));
3291 /* Functions to choose the best insn from available ones. */
3293 /* Adjusts the priority for EXPR using the backend *_adjust_priority hook. */
3295 sel_target_adjust_priority (expr_t expr
)
3297 int priority
= EXPR_PRIORITY (expr
);
3300 if (targetm
.sched
.adjust_priority
)
3301 new_priority
= targetm
.sched
.adjust_priority (EXPR_INSN_RTX (expr
), priority
);
3303 new_priority
= priority
;
3305 /* If the priority has changed, adjust EXPR_PRIORITY_ADJ accordingly. */
3306 EXPR_PRIORITY_ADJ (expr
) = new_priority
- EXPR_PRIORITY (expr
);
3308 gcc_assert (EXPR_PRIORITY_ADJ (expr
) >= 0);
3310 if (sched_verbose
>= 4)
3311 sel_print ("sel_target_adjust_priority: insn %d, %d+%d = %d.\n",
3312 INSN_UID (EXPR_INSN_RTX (expr
)), EXPR_PRIORITY (expr
),
3313 EXPR_PRIORITY_ADJ (expr
), new_priority
);
3315 return new_priority
;
3318 /* Rank two available exprs for schedule. Never return 0 here. */
3320 sel_rank_for_schedule (const void *x
, const void *y
)
3322 expr_t tmp
= *(const expr_t
*) y
;
3323 expr_t tmp2
= *(const expr_t
*) x
;
3324 insn_t tmp_insn
, tmp2_insn
;
3325 vinsn_t tmp_vinsn
, tmp2_vinsn
;
3328 tmp_vinsn
= EXPR_VINSN (tmp
);
3329 tmp2_vinsn
= EXPR_VINSN (tmp2
);
3330 tmp_insn
= EXPR_INSN_RTX (tmp
);
3331 tmp2_insn
= EXPR_INSN_RTX (tmp2
);
3333 /* Schedule debug insns as early as possible. */
3334 if (DEBUG_INSN_P (tmp_insn
) && !DEBUG_INSN_P (tmp2_insn
))
3336 else if (DEBUG_INSN_P (tmp2_insn
))
3339 /* Prefer SCHED_GROUP_P insns to any others. */
3340 if (SCHED_GROUP_P (tmp_insn
) != SCHED_GROUP_P (tmp2_insn
))
3342 if (VINSN_UNIQUE_P (tmp_vinsn
) && VINSN_UNIQUE_P (tmp2_vinsn
))
3343 return SCHED_GROUP_P (tmp2_insn
) ? 1 : -1;
3345 /* Now uniqueness means SCHED_GROUP_P is set, because schedule groups
3346 cannot be cloned. */
3347 if (VINSN_UNIQUE_P (tmp2_vinsn
))
3352 /* Discourage scheduling of speculative checks. */
3353 val
= (sel_insn_is_speculation_check (tmp_insn
)
3354 - sel_insn_is_speculation_check (tmp2_insn
));
3358 /* Prefer not scheduled insn over scheduled one. */
3359 if (EXPR_SCHED_TIMES (tmp
) > 0 || EXPR_SCHED_TIMES (tmp2
) > 0)
3361 val
= EXPR_SCHED_TIMES (tmp
) - EXPR_SCHED_TIMES (tmp2
);
3366 /* Prefer jump over non-jump instruction. */
3367 if (control_flow_insn_p (tmp_insn
) && !control_flow_insn_p (tmp2_insn
))
3369 else if (control_flow_insn_p (tmp2_insn
) && !control_flow_insn_p (tmp_insn
))
3372 /* Prefer an expr with greater priority. */
3373 if (EXPR_USEFULNESS (tmp
) != 0 && EXPR_USEFULNESS (tmp2
) != 0)
3375 int p2
= EXPR_PRIORITY (tmp2
) + EXPR_PRIORITY_ADJ (tmp2
),
3376 p1
= EXPR_PRIORITY (tmp
) + EXPR_PRIORITY_ADJ (tmp
);
3378 val
= p2
* EXPR_USEFULNESS (tmp2
) - p1
* EXPR_USEFULNESS (tmp
);
3381 val
= EXPR_PRIORITY (tmp2
) - EXPR_PRIORITY (tmp
)
3382 + EXPR_PRIORITY_ADJ (tmp2
) - EXPR_PRIORITY_ADJ (tmp
);
3386 if (spec_info
!= NULL
&& spec_info
->mask
!= 0)
3387 /* This code was taken from haifa-sched.c: rank_for_schedule (). */
3393 ds1
= EXPR_SPEC_DONE_DS (tmp
);
3395 dw1
= ds_weak (ds1
);
3399 ds2
= EXPR_SPEC_DONE_DS (tmp2
);
3401 dw2
= ds_weak (ds2
);
3406 if (dw
> (NO_DEP_WEAK
/ 8) || dw
< -(NO_DEP_WEAK
/ 8))
3410 /* Prefer an old insn to a bookkeeping insn. */
3411 if (INSN_UID (tmp_insn
) < first_emitted_uid
3412 && INSN_UID (tmp2_insn
) >= first_emitted_uid
)
3414 if (INSN_UID (tmp_insn
) >= first_emitted_uid
3415 && INSN_UID (tmp2_insn
) < first_emitted_uid
)
3418 /* Prefer an insn with smaller UID, as a last resort.
3419 We can't safely use INSN_LUID as it is defined only for those insns
3420 that are in the stream. */
3421 return INSN_UID (tmp_insn
) - INSN_UID (tmp2_insn
);
3424 /* Filter out expressions from av set pointed to by AV_PTR
3425 that are pipelined too many times. */
3427 process_pipelined_exprs (av_set_t
*av_ptr
)
3432 /* Don't pipeline already pipelined code as that would increase
3433 number of unnecessary register moves. */
3434 FOR_EACH_EXPR_1 (expr
, si
, av_ptr
)
3436 if (EXPR_SCHED_TIMES (expr
)
3437 >= PARAM_VALUE (PARAM_SELSCHED_MAX_SCHED_TIMES
))
3438 av_set_iter_remove (&si
);
3442 /* Filter speculative insns from AV_PTR if we don't want them. */
3444 process_spec_exprs (av_set_t
*av_ptr
)
3446 bool try_data_p
= true;
3447 bool try_control_p
= true;
3451 if (spec_info
== NULL
)
3454 /* Scan *AV_PTR to find out if we want to consider speculative
3455 instructions for scheduling. */
3456 FOR_EACH_EXPR_1 (expr
, si
, av_ptr
)
3460 ds
= EXPR_SPEC_DONE_DS (expr
);
3462 /* The probability of a success is too low - don't speculate. */
3463 if ((ds
& SPECULATIVE
)
3464 && (ds_weak (ds
) < spec_info
->data_weakness_cutoff
3465 || EXPR_USEFULNESS (expr
) < spec_info
->control_weakness_cutoff
3466 || (pipelining_p
&& false
3468 && (ds
& CONTROL_SPEC
))))
3470 av_set_iter_remove (&si
);
3474 if ((spec_info
->flags
& PREFER_NON_DATA_SPEC
)
3475 && !(ds
& BEGIN_DATA
))
3478 if ((spec_info
->flags
& PREFER_NON_CONTROL_SPEC
)
3479 && !(ds
& BEGIN_CONTROL
))
3480 try_control_p
= false;
3483 FOR_EACH_EXPR_1 (expr
, si
, av_ptr
)
3487 ds
= EXPR_SPEC_DONE_DS (expr
);
3489 if (ds
& SPECULATIVE
)
3491 if ((ds
& BEGIN_DATA
) && !try_data_p
)
3492 /* We don't want any data speculative instructions right
3494 av_set_iter_remove (&si
);
3496 if ((ds
& BEGIN_CONTROL
) && !try_control_p
)
3497 /* We don't want any control speculative instructions right
3499 av_set_iter_remove (&si
);
3504 /* Search for any use-like insns in AV_PTR and decide on scheduling
3505 them. Return one when found, and NULL otherwise.
3506 Note that we check here whether a USE could be scheduled to avoid
3507 an infinite loop later. */
3509 process_use_exprs (av_set_t
*av_ptr
)
3513 bool uses_present_p
= false;
3514 bool try_uses_p
= true;
3516 FOR_EACH_EXPR_1 (expr
, si
, av_ptr
)
3518 /* This will also initialize INSN_CODE for later use. */
3519 if (recog_memoized (EXPR_INSN_RTX (expr
)) < 0)
3521 /* If we have a USE in *AV_PTR that was not scheduled yet,
3522 do so because it will do good only. */
3523 if (EXPR_SCHED_TIMES (expr
) <= 0)
3525 if (EXPR_TARGET_AVAILABLE (expr
) == 1)
3528 av_set_iter_remove (&si
);
3532 gcc_assert (pipelining_p
);
3534 uses_present_p
= true;
3543 /* If we don't want to schedule any USEs right now and we have some
3544 in *AV_PTR, remove them, else just return the first one found. */
3547 FOR_EACH_EXPR_1 (expr
, si
, av_ptr
)
3548 if (INSN_CODE (EXPR_INSN_RTX (expr
)) < 0)
3549 av_set_iter_remove (&si
);
3553 FOR_EACH_EXPR_1 (expr
, si
, av_ptr
)
3555 gcc_assert (INSN_CODE (EXPR_INSN_RTX (expr
)) < 0);
3557 if (EXPR_TARGET_AVAILABLE (expr
) == 1)
3560 av_set_iter_remove (&si
);
3568 /* Lookup EXPR in VINSN_VEC and return TRUE if found. */
3570 vinsn_vec_has_expr_p (vinsn_vec_t vinsn_vec
, expr_t expr
)
3575 FOR_EACH_VEC_ELT (vinsn_t
, vinsn_vec
, n
, vinsn
)
3576 if (VINSN_SEPARABLE_P (vinsn
))
3578 if (vinsn_equal_p (vinsn
, EXPR_VINSN (expr
)))
3583 /* For non-separable instructions, the blocking insn can have
3584 another pattern due to substitution, and we can't choose
3585 different register as in the above case. Check all registers
3586 being written instead. */
3587 if (bitmap_intersect_p (VINSN_REG_SETS (vinsn
),
3588 VINSN_REG_SETS (EXPR_VINSN (expr
))))
3595 #ifdef ENABLE_CHECKING
3596 /* Return true if either of expressions from ORIG_OPS can be blocked
3597 by previously created bookkeeping code. STATIC_PARAMS points to static
3598 parameters of move_op. */
3600 av_set_could_be_blocked_by_bookkeeping_p (av_set_t orig_ops
, void *static_params
)
3603 av_set_iterator iter
;
3604 moveop_static_params_p sparams
;
3606 /* This checks that expressions in ORIG_OPS are not blocked by bookkeeping
3607 created while scheduling on another fence. */
3608 FOR_EACH_EXPR (expr
, iter
, orig_ops
)
3609 if (vinsn_vec_has_expr_p (vec_bookkeeping_blocked_vinsns
, expr
))
3612 gcc_assert (code_motion_path_driver_info
== &move_op_hooks
);
3613 sparams
= (moveop_static_params_p
) static_params
;
3615 /* Expressions can be also blocked by bookkeeping created during current
3617 if (bitmap_bit_p (current_copies
, INSN_UID (sparams
->failed_insn
)))
3618 FOR_EACH_EXPR (expr
, iter
, orig_ops
)
3619 if (moveup_expr_cached (expr
, sparams
->failed_insn
, false) != MOVEUP_EXPR_NULL
)
3622 /* Expressions in ORIG_OPS may have wrong destination register due to
3623 renaming. Check with the right register instead. */
3624 if (sparams
->dest
&& REG_P (sparams
->dest
))
3626 unsigned regno
= REGNO (sparams
->dest
);
3627 vinsn_t failed_vinsn
= INSN_VINSN (sparams
->failed_insn
);
3629 if (bitmap_bit_p (VINSN_REG_SETS (failed_vinsn
), regno
)
3630 || bitmap_bit_p (VINSN_REG_USES (failed_vinsn
), regno
)
3631 || bitmap_bit_p (VINSN_REG_CLOBBERS (failed_vinsn
), regno
))
3639 /* Clear VINSN_VEC and detach vinsns. */
3641 vinsn_vec_clear (vinsn_vec_t
*vinsn_vec
)
3643 unsigned len
= VEC_length (vinsn_t
, *vinsn_vec
);
3649 FOR_EACH_VEC_ELT (vinsn_t
, *vinsn_vec
, n
, vinsn
)
3650 vinsn_detach (vinsn
);
3651 VEC_block_remove (vinsn_t
, *vinsn_vec
, 0, len
);
3655 /* Add the vinsn of EXPR to the VINSN_VEC. */
3657 vinsn_vec_add (vinsn_vec_t
*vinsn_vec
, expr_t expr
)
3659 vinsn_attach (EXPR_VINSN (expr
));
3660 VEC_safe_push (vinsn_t
, heap
, *vinsn_vec
, EXPR_VINSN (expr
));
3663 /* Free the vector representing blocked expressions. */
3665 vinsn_vec_free (vinsn_vec_t
*vinsn_vec
)
3668 VEC_free (vinsn_t
, heap
, *vinsn_vec
);
3671 /* Increase EXPR_PRIORITY_ADJ for INSN by AMOUNT. */
3673 void sel_add_to_insn_priority (rtx insn
, int amount
)
3675 EXPR_PRIORITY_ADJ (INSN_EXPR (insn
)) += amount
;
3677 if (sched_verbose
>= 2)
3678 sel_print ("sel_add_to_insn_priority: insn %d, by %d (now %d+%d).\n",
3679 INSN_UID (insn
), amount
, EXPR_PRIORITY (INSN_EXPR (insn
)),
3680 EXPR_PRIORITY_ADJ (INSN_EXPR (insn
)));
3683 /* Turn AV into a vector, filter inappropriate insns and sort it. Return
3684 true if there is something to schedule. BNDS and FENCE are current
3685 boundaries and fence, respectively. If we need to stall for some cycles
3686 before an expr from AV would become available, write this number to
3689 fill_vec_av_set (av_set_t av
, blist_t bnds
, fence_t fence
,
3694 int sched_next_worked
= 0, stalled
, n
;
3695 static int av_max_prio
, est_ticks_till_branch
;
3696 int min_need_stall
= -1;
3697 deps_t dc
= BND_DC (BLIST_BND (bnds
));
3699 /* Bail out early when the ready list contained only USEs/CLOBBERs that are
3700 already scheduled. */
3704 /* Empty vector from the previous stuff. */
3705 if (VEC_length (expr_t
, vec_av_set
) > 0)
3706 VEC_block_remove (expr_t
, vec_av_set
, 0, VEC_length (expr_t
, vec_av_set
));
3708 /* Turn the set into a vector for sorting and call sel_target_adjust_priority
3710 gcc_assert (VEC_empty (expr_t
, vec_av_set
));
3711 FOR_EACH_EXPR (expr
, si
, av
)
3713 VEC_safe_push (expr_t
, heap
, vec_av_set
, expr
);
3715 gcc_assert (EXPR_PRIORITY_ADJ (expr
) == 0 || *pneed_stall
);
3717 /* Adjust priority using target backend hook. */
3718 sel_target_adjust_priority (expr
);
3721 /* Sort the vector. */
3722 qsort (VEC_address (expr_t
, vec_av_set
), VEC_length (expr_t
, vec_av_set
),
3723 sizeof (expr_t
), sel_rank_for_schedule
);
3725 /* We record maximal priority of insns in av set for current instruction
3727 if (FENCE_STARTS_CYCLE_P (fence
))
3728 av_max_prio
= est_ticks_till_branch
= INT_MIN
;
3730 /* Filter out inappropriate expressions. Loop's direction is reversed to
3731 visit "best" instructions first. We assume that VEC_unordered_remove
3732 moves last element in place of one being deleted. */
3733 for (n
= VEC_length (expr_t
, vec_av_set
) - 1, stalled
= 0; n
>= 0; n
--)
3735 expr_t expr
= VEC_index (expr_t
, vec_av_set
, n
);
3736 insn_t insn
= EXPR_INSN_RTX (expr
);
3737 char target_available
;
3738 bool is_orig_reg_p
= true;
3739 int need_cycles
, new_prio
;
3741 /* Don't allow any insns other than from SCHED_GROUP if we have one. */
3742 if (FENCE_SCHED_NEXT (fence
) && insn
!= FENCE_SCHED_NEXT (fence
))
3744 VEC_unordered_remove (expr_t
, vec_av_set
, n
);
3748 /* Set number of sched_next insns (just in case there
3749 could be several). */
3750 if (FENCE_SCHED_NEXT (fence
))
3751 sched_next_worked
++;
3753 /* Check all liveness requirements and try renaming.
3754 FIXME: try to minimize calls to this. */
3755 target_available
= EXPR_TARGET_AVAILABLE (expr
);
3757 /* If insn was already scheduled on the current fence,
3758 set TARGET_AVAILABLE to -1 no matter what expr's attribute says. */
3759 if (vinsn_vec_has_expr_p (vec_target_unavailable_vinsns
, expr
))
3760 target_available
= -1;
3762 /* If the availability of the EXPR is invalidated by the insertion of
3763 bookkeeping earlier, make sure that we won't choose this expr for
3764 scheduling if it's not separable, and if it is separable, then
3765 we have to recompute the set of available registers for it. */
3766 if (vinsn_vec_has_expr_p (vec_bookkeeping_blocked_vinsns
, expr
))
3768 VEC_unordered_remove (expr_t
, vec_av_set
, n
);
3769 if (sched_verbose
>= 4)
3770 sel_print ("Expr %d is blocked by bookkeeping inserted earlier\n",
3775 if (target_available
== true)
3777 /* Do nothing -- we can use an existing register. */
3778 is_orig_reg_p
= EXPR_SEPARABLE_P (expr
);
3780 else if (/* Non-separable instruction will never
3781 get another register. */
3782 (target_available
== false
3783 && !EXPR_SEPARABLE_P (expr
))
3784 /* Don't try to find a register for low-priority expression. */
3785 || (int) VEC_length (expr_t
, vec_av_set
) - 1 - n
>= max_insns_to_rename
3786 /* ??? FIXME: Don't try to rename data speculation. */
3787 || (EXPR_SPEC_DONE_DS (expr
) & BEGIN_DATA
)
3788 || ! find_best_reg_for_expr (expr
, bnds
, &is_orig_reg_p
))
3790 VEC_unordered_remove (expr_t
, vec_av_set
, n
);
3791 if (sched_verbose
>= 4)
3792 sel_print ("Expr %d has no suitable target register\n",
3797 /* Filter expressions that need to be renamed or speculated when
3798 pipelining, because compensating register copies or speculation
3799 checks are likely to be placed near the beginning of the loop,
3801 if (pipelining_p
&& EXPR_ORIG_SCHED_CYCLE (expr
) > 0
3802 && (!is_orig_reg_p
|| EXPR_SPEC_DONE_DS (expr
) != 0))
3804 /* Estimation of number of cycles until loop branch for
3805 renaming/speculation to be successful. */
3806 int need_n_ticks_till_branch
= sel_vinsn_cost (EXPR_VINSN (expr
));
3808 if ((int) current_loop_nest
->ninsns
< 9)
3810 VEC_unordered_remove (expr_t
, vec_av_set
, n
);
3811 if (sched_verbose
>= 4)
3812 sel_print ("Pipelining expr %d will likely cause stall\n",
3817 if ((int) current_loop_nest
->ninsns
- num_insns_scheduled
3818 < need_n_ticks_till_branch
* issue_rate
/ 2
3819 && est_ticks_till_branch
< need_n_ticks_till_branch
)
3821 VEC_unordered_remove (expr_t
, vec_av_set
, n
);
3822 if (sched_verbose
>= 4)
3823 sel_print ("Pipelining expr %d will likely cause stall\n",
3829 /* We want to schedule speculation checks as late as possible. Discard
3830 them from av set if there are instructions with higher priority. */
3831 if (sel_insn_is_speculation_check (insn
)
3832 && EXPR_PRIORITY (expr
) < av_max_prio
)
3835 min_need_stall
= min_need_stall
< 0 ? 1 : MIN (min_need_stall
, 1);
3836 VEC_unordered_remove (expr_t
, vec_av_set
, n
);
3837 if (sched_verbose
>= 4)
3838 sel_print ("Delaying speculation check %d until its first use\n",
3843 /* Ignore EXPRs available from pipelining to update AV_MAX_PRIO. */
3844 if (EXPR_ORIG_SCHED_CYCLE (expr
) <= 0)
3845 av_max_prio
= MAX (av_max_prio
, EXPR_PRIORITY (expr
));
3847 /* Don't allow any insns whose data is not yet ready.
3848 Check first whether we've already tried them and failed. */
3849 if (INSN_UID (insn
) < FENCE_READY_TICKS_SIZE (fence
))
3851 need_cycles
= (FENCE_READY_TICKS (fence
)[INSN_UID (insn
)]
3852 - FENCE_CYCLE (fence
));
3853 if (EXPR_ORIG_SCHED_CYCLE (expr
) <= 0)
3854 est_ticks_till_branch
= MAX (est_ticks_till_branch
,
3855 EXPR_PRIORITY (expr
) + need_cycles
);
3857 if (need_cycles
> 0)
3860 min_need_stall
= (min_need_stall
< 0
3862 : MIN (min_need_stall
, need_cycles
));
3863 VEC_unordered_remove (expr_t
, vec_av_set
, n
);
3865 if (sched_verbose
>= 4)
3866 sel_print ("Expr %d is not ready until cycle %d (cached)\n",
3868 FENCE_READY_TICKS (fence
)[INSN_UID (insn
)]);
3873 /* Now resort to dependence analysis to find whether EXPR might be
3874 stalled due to dependencies from FENCE's context. */
3875 need_cycles
= tick_check_p (expr
, dc
, fence
);
3876 new_prio
= EXPR_PRIORITY (expr
) + EXPR_PRIORITY_ADJ (expr
) + need_cycles
;
3878 if (EXPR_ORIG_SCHED_CYCLE (expr
) <= 0)
3879 est_ticks_till_branch
= MAX (est_ticks_till_branch
,
3882 if (need_cycles
> 0)
3884 if (INSN_UID (insn
) >= FENCE_READY_TICKS_SIZE (fence
))
3886 int new_size
= INSN_UID (insn
) * 3 / 2;
3888 FENCE_READY_TICKS (fence
)
3889 = (int *) xrecalloc (FENCE_READY_TICKS (fence
),
3890 new_size
, FENCE_READY_TICKS_SIZE (fence
),
3893 FENCE_READY_TICKS (fence
)[INSN_UID (insn
)]
3894 = FENCE_CYCLE (fence
) + need_cycles
;
3897 min_need_stall
= (min_need_stall
< 0
3899 : MIN (min_need_stall
, need_cycles
));
3901 VEC_unordered_remove (expr_t
, vec_av_set
, n
);
3903 if (sched_verbose
>= 4)
3904 sel_print ("Expr %d is not ready yet until cycle %d\n",
3906 FENCE_READY_TICKS (fence
)[INSN_UID (insn
)]);
3910 if (sched_verbose
>= 4)
3911 sel_print ("Expr %d is ok\n", INSN_UID (insn
));
3915 /* Clear SCHED_NEXT. */
3916 if (FENCE_SCHED_NEXT (fence
))
3918 gcc_assert (sched_next_worked
== 1);
3919 FENCE_SCHED_NEXT (fence
) = NULL_RTX
;
3922 /* No need to stall if this variable was not initialized. */
3923 if (min_need_stall
< 0)
3926 if (VEC_empty (expr_t
, vec_av_set
))
3928 /* We need to set *pneed_stall here, because later we skip this code
3929 when ready list is empty. */
3930 *pneed_stall
= min_need_stall
;
3934 gcc_assert (min_need_stall
== 0);
3936 /* Sort the vector. */
3937 qsort (VEC_address (expr_t
, vec_av_set
), VEC_length (expr_t
, vec_av_set
),
3938 sizeof (expr_t
), sel_rank_for_schedule
);
3940 if (sched_verbose
>= 4)
3942 sel_print ("Total ready exprs: %d, stalled: %d\n",
3943 VEC_length (expr_t
, vec_av_set
), stalled
);
3944 sel_print ("Sorted av set (%d): ", VEC_length (expr_t
, vec_av_set
));
3945 FOR_EACH_VEC_ELT (expr_t
, vec_av_set
, n
, expr
)
3954 /* Convert a vectored and sorted av set to the ready list that
3955 the rest of the backend wants to see. */
3957 convert_vec_av_set_to_ready (void)
3962 /* Allocate and fill the ready list from the sorted vector. */
3963 ready
.n_ready
= VEC_length (expr_t
, vec_av_set
);
3964 ready
.first
= ready
.n_ready
- 1;
3966 gcc_assert (ready
.n_ready
> 0);
3968 if (ready
.n_ready
> max_issue_size
)
3970 max_issue_size
= ready
.n_ready
;
3971 sched_extend_ready_list (ready
.n_ready
);
3974 FOR_EACH_VEC_ELT (expr_t
, vec_av_set
, n
, expr
)
3976 vinsn_t vi
= EXPR_VINSN (expr
);
3977 insn_t insn
= VINSN_INSN_RTX (vi
);
3980 ready
.vec
[n
] = insn
;
3984 /* Initialize ready list from *AV_PTR for the max_issue () call.
3985 If any unrecognizable insn found in *AV_PTR, return it (and skip
3986 max_issue). BND and FENCE are current boundary and fence,
3987 respectively. If we need to stall for some cycles before an expr
3988 from *AV_PTR would become available, write this number to *PNEED_STALL. */
3990 fill_ready_list (av_set_t
*av_ptr
, blist_t bnds
, fence_t fence
,
3995 /* We do not support multiple boundaries per fence. */
3996 gcc_assert (BLIST_NEXT (bnds
) == NULL
);
3998 /* Process expressions required special handling, i.e. pipelined,
3999 speculative and recog() < 0 expressions first. */
4000 process_pipelined_exprs (av_ptr
);
4001 process_spec_exprs (av_ptr
);
4003 /* A USE could be scheduled immediately. */
4004 expr
= process_use_exprs (av_ptr
);
4011 /* Turn the av set to a vector for sorting. */
4012 if (! fill_vec_av_set (*av_ptr
, bnds
, fence
, pneed_stall
))
4018 /* Build the final ready list. */
4019 convert_vec_av_set_to_ready ();
4023 /* Wrapper for dfa_new_cycle (). Returns TRUE if cycle was advanced. */
4025 sel_dfa_new_cycle (insn_t insn
, fence_t fence
)
4027 int last_scheduled_cycle
= FENCE_LAST_SCHEDULED_INSN (fence
)
4028 ? INSN_SCHED_CYCLE (FENCE_LAST_SCHEDULED_INSN (fence
))
4029 : FENCE_CYCLE (fence
) - 1;
4033 if (!targetm
.sched
.dfa_new_cycle
)
4036 memcpy (curr_state
, FENCE_STATE (fence
), dfa_state_size
);
4038 while (!sort_p
&& targetm
.sched
.dfa_new_cycle (sched_dump
, sched_verbose
,
4039 insn
, last_scheduled_cycle
,
4040 FENCE_CYCLE (fence
), &sort_p
))
4042 memcpy (FENCE_STATE (fence
), curr_state
, dfa_state_size
);
4043 advance_one_cycle (fence
);
4044 memcpy (curr_state
, FENCE_STATE (fence
), dfa_state_size
);
4051 /* Invoke reorder* target hooks on the ready list. Return the number of insns
4052 we can issue. FENCE is the current fence. */
4054 invoke_reorder_hooks (fence_t fence
)
4057 bool ran_hook
= false;
4059 /* Call the reorder hook at the beginning of the cycle, and call
4060 the reorder2 hook in the middle of the cycle. */
4061 if (FENCE_ISSUED_INSNS (fence
) == 0)
4063 if (targetm
.sched
.reorder
4064 && !SCHED_GROUP_P (ready_element (&ready
, 0))
4065 && ready
.n_ready
> 1)
4067 /* Don't give reorder the most prioritized insn as it can break
4073 = targetm
.sched
.reorder (sched_dump
, sched_verbose
,
4074 ready_lastpos (&ready
),
4075 &ready
.n_ready
, FENCE_CYCLE (fence
));
4083 /* Initialize can_issue_more for variable_issue. */
4084 issue_more
= issue_rate
;
4086 else if (targetm
.sched
.reorder2
4087 && !SCHED_GROUP_P (ready_element (&ready
, 0)))
4089 if (ready
.n_ready
== 1)
4091 targetm
.sched
.reorder2 (sched_dump
, sched_verbose
,
4092 ready_lastpos (&ready
),
4093 &ready
.n_ready
, FENCE_CYCLE (fence
));
4100 targetm
.sched
.reorder2 (sched_dump
, sched_verbose
,
4102 ? ready_lastpos (&ready
) : NULL
,
4103 &ready
.n_ready
, FENCE_CYCLE (fence
));
4112 issue_more
= FENCE_ISSUE_MORE (fence
);
4114 /* Ensure that ready list and vec_av_set are in line with each other,
4115 i.e. vec_av_set[i] == ready_element (&ready, i). */
4116 if (issue_more
&& ran_hook
)
4119 rtx
*arr
= ready
.vec
;
4120 expr_t
*vec
= VEC_address (expr_t
, vec_av_set
);
4122 for (i
= 0, n
= ready
.n_ready
; i
< n
; i
++)
4123 if (EXPR_INSN_RTX (vec
[i
]) != arr
[i
])
4127 for (j
= i
; j
< n
; j
++)
4128 if (EXPR_INSN_RTX (vec
[j
]) == arr
[i
])
4141 /* Return an EXPR correponding to INDEX element of ready list, if
4142 FOLLOW_READY_ELEMENT is true (i.e., an expr of
4143 ready_element (&ready, INDEX) will be returned), and to INDEX element of
4144 ready.vec otherwise. */
4145 static inline expr_t
4146 find_expr_for_ready (int index
, bool follow_ready_element
)
4151 real_index
= follow_ready_element
? ready
.first
- index
: index
;
4153 expr
= VEC_index (expr_t
, vec_av_set
, real_index
);
4154 gcc_assert (ready
.vec
[real_index
] == EXPR_INSN_RTX (expr
));
4159 /* Calculate insns worth trying via lookahead_guard hook. Return a number
4160 of such insns found. */
4162 invoke_dfa_lookahead_guard (void)
4166 = targetm
.sched
.first_cycle_multipass_dfa_lookahead_guard
!= NULL
;
4168 if (sched_verbose
>= 2)
4169 sel_print ("ready after reorder: ");
4171 for (i
= 0, n
= 0; i
< ready
.n_ready
; i
++)
4177 /* In this loop insn is Ith element of the ready list given by
4178 ready_element, not Ith element of ready.vec. */
4179 insn
= ready_element (&ready
, i
);
4181 if (! have_hook
|| i
== 0)
4184 r
= !targetm
.sched
.first_cycle_multipass_dfa_lookahead_guard (insn
);
4186 gcc_assert (INSN_CODE (insn
) >= 0);
4188 /* Only insns with ready_try = 0 can get here
4189 from fill_ready_list. */
4190 gcc_assert (ready_try
[i
] == 0);
4195 expr
= find_expr_for_ready (i
, true);
4197 if (sched_verbose
>= 2)
4199 dump_vinsn (EXPR_VINSN (expr
));
4200 sel_print (":%d; ", ready_try
[i
]);
4204 if (sched_verbose
>= 2)
4209 /* Calculate the number of privileged insns and return it. */
4211 calculate_privileged_insns (void)
4213 expr_t cur_expr
, min_spec_expr
= NULL
;
4214 int privileged_n
= 0, i
;
4216 for (i
= 0; i
< ready
.n_ready
; i
++)
4221 if (! min_spec_expr
)
4222 min_spec_expr
= find_expr_for_ready (i
, true);
4224 cur_expr
= find_expr_for_ready (i
, true);
4226 if (EXPR_SPEC (cur_expr
) > EXPR_SPEC (min_spec_expr
))
4232 if (i
== ready
.n_ready
)
4235 if (sched_verbose
>= 2)
4236 sel_print ("privileged_n: %d insns with SPEC %d\n",
4237 privileged_n
, privileged_n
? EXPR_SPEC (min_spec_expr
) : -1);
4238 return privileged_n
;
4241 /* Call the rest of the hooks after the choice was made. Return
4242 the number of insns that still can be issued given that the current
4243 number is ISSUE_MORE. FENCE and BEST_INSN are the current fence
4244 and the insn chosen for scheduling, respectively. */
4246 invoke_aftermath_hooks (fence_t fence
, rtx best_insn
, int issue_more
)
4248 gcc_assert (INSN_P (best_insn
));
4250 /* First, call dfa_new_cycle, and then variable_issue, if available. */
4251 sel_dfa_new_cycle (best_insn
, fence
);
4253 if (targetm
.sched
.variable_issue
)
4255 memcpy (curr_state
, FENCE_STATE (fence
), dfa_state_size
);
4257 targetm
.sched
.variable_issue (sched_dump
, sched_verbose
, best_insn
,
4259 memcpy (FENCE_STATE (fence
), curr_state
, dfa_state_size
);
4261 else if (GET_CODE (PATTERN (best_insn
)) != USE
4262 && GET_CODE (PATTERN (best_insn
)) != CLOBBER
)
4268 /* Estimate the cost of issuing INSN on DFA state STATE. */
4270 estimate_insn_cost (rtx insn
, state_t state
)
4272 static state_t temp
= NULL
;
4276 temp
= xmalloc (dfa_state_size
);
4278 memcpy (temp
, state
, dfa_state_size
);
4279 cost
= state_transition (temp
, insn
);
4288 /* Return the cost of issuing EXPR on the FENCE as estimated by DFA.
4289 This function properly handles ASMs, USEs etc. */
4291 get_expr_cost (expr_t expr
, fence_t fence
)
4293 rtx insn
= EXPR_INSN_RTX (expr
);
4295 if (recog_memoized (insn
) < 0)
4297 if (!FENCE_STARTS_CYCLE_P (fence
)
4298 && INSN_ASM_P (insn
))
4299 /* This is asm insn which is tryed to be issued on the
4300 cycle not first. Issue it on the next cycle. */
4303 /* A USE insn, or something else we don't need to
4304 understand. We can't pass these directly to
4305 state_transition because it will trigger a
4306 fatal error for unrecognizable insns. */
4310 return estimate_insn_cost (insn
, FENCE_STATE (fence
));
4313 /* Find the best insn for scheduling, either via max_issue or just take
4314 the most prioritized available. */
4316 choose_best_insn (fence_t fence
, int privileged_n
, int *index
)
4320 if (dfa_lookahead
> 0)
4322 cycle_issued_insns
= FENCE_ISSUED_INSNS (fence
);
4323 can_issue
= max_issue (&ready
, privileged_n
,
4324 FENCE_STATE (fence
), index
);
4325 if (sched_verbose
>= 2)
4326 sel_print ("max_issue: we can issue %d insns, already did %d insns\n",
4327 can_issue
, FENCE_ISSUED_INSNS (fence
));
4331 /* We can't use max_issue; just return the first available element. */
4334 for (i
= 0; i
< ready
.n_ready
; i
++)
4336 expr_t expr
= find_expr_for_ready (i
, true);
4338 if (get_expr_cost (expr
, fence
) < 1)
4340 can_issue
= can_issue_more
;
4343 if (sched_verbose
>= 2)
4344 sel_print ("using %dth insn from the ready list\n", i
+ 1);
4350 if (i
== ready
.n_ready
)
4360 /* Choose the best expr from *AV_VLIW_PTR and a suitable register for it.
4361 BNDS and FENCE are current boundaries and scheduling fence respectively.
4362 Return the expr found and NULL if nothing can be issued atm.
4363 Write to PNEED_STALL the number of cycles to stall if no expr was found. */
4365 find_best_expr (av_set_t
*av_vliw_ptr
, blist_t bnds
, fence_t fence
,
4370 /* Choose the best insn for scheduling via:
4371 1) sorting the ready list based on priority;
4372 2) calling the reorder hook;
4373 3) calling max_issue. */
4374 best
= fill_ready_list (av_vliw_ptr
, bnds
, fence
, pneed_stall
);
4375 if (best
== NULL
&& ready
.n_ready
> 0)
4377 int privileged_n
, index
;
4379 can_issue_more
= invoke_reorder_hooks (fence
);
4380 if (can_issue_more
> 0)
4382 /* Try choosing the best insn until we find one that is could be
4383 scheduled due to liveness restrictions on its destination register.
4384 In the future, we'd like to choose once and then just probe insns
4385 in the order of their priority. */
4386 invoke_dfa_lookahead_guard ();
4387 privileged_n
= calculate_privileged_insns ();
4388 can_issue_more
= choose_best_insn (fence
, privileged_n
, &index
);
4390 best
= find_expr_for_ready (index
, true);
4392 /* We had some available insns, so if we can't issue them,
4394 if (can_issue_more
== 0)
4403 can_issue_more
= invoke_aftermath_hooks (fence
, EXPR_INSN_RTX (best
),
4405 if (can_issue_more
== 0)
4409 if (sched_verbose
>= 2)
4413 sel_print ("Best expression (vliw form): ");
4415 sel_print ("; cycle %d\n", FENCE_CYCLE (fence
));
4418 sel_print ("No best expr found!\n");
4425 /* Functions that implement the core of the scheduler. */
4428 /* Emit an instruction from EXPR with SEQNO and VINSN after
4431 emit_insn_from_expr_after (expr_t expr
, vinsn_t vinsn
, int seqno
,
4432 insn_t place_to_insert
)
4434 /* This assert fails when we have identical instructions
4435 one of which dominates the other. In this case move_op ()
4436 finds the first instruction and doesn't search for second one.
4437 The solution would be to compute av_set after the first found
4438 insn and, if insn present in that set, continue searching.
4439 For now we workaround this issue in move_op. */
4440 gcc_assert (!INSN_IN_STREAM_P (EXPR_INSN_RTX (expr
)));
4442 if (EXPR_WAS_RENAMED (expr
))
4444 unsigned regno
= expr_dest_regno (expr
);
4446 if (HARD_REGISTER_NUM_P (regno
))
4448 df_set_regs_ever_live (regno
, true);
4449 reg_rename_tick
[regno
] = ++reg_rename_this_tick
;
4453 return sel_gen_insn_from_expr_after (expr
, vinsn
, seqno
,
4457 /* Return TRUE if BB can hold bookkeeping code. */
4459 block_valid_for_bookkeeping_p (basic_block bb
)
4461 insn_t bb_end
= BB_END (bb
);
4463 if (!in_current_region_p (bb
) || EDGE_COUNT (bb
->succs
) > 1)
4466 if (INSN_P (bb_end
))
4468 if (INSN_SCHED_TIMES (bb_end
) > 0)
4472 gcc_assert (NOTE_INSN_BASIC_BLOCK_P (bb_end
));
4477 /* Attempt to find a block that can hold bookkeeping code for path(s) incoming
4478 into E2->dest, except from E1->src (there may be a sequence of empty basic
4479 blocks between E1->src and E2->dest). Return found block, or NULL if new
4480 one must be created. If LAX holds, don't assume there is a simple path
4481 from E1->src to E2->dest. */
4483 find_block_for_bookkeeping (edge e1
, edge e2
, bool lax
)
4485 basic_block candidate_block
= NULL
;
4488 /* Loop over edges from E1 to E2, inclusive. */
4489 for (e
= e1
; !lax
|| e
->dest
!= EXIT_BLOCK_PTR
; e
= EDGE_SUCC (e
->dest
, 0))
4491 if (EDGE_COUNT (e
->dest
->preds
) == 2)
4493 if (candidate_block
== NULL
)
4494 candidate_block
= (EDGE_PRED (e
->dest
, 0) == e
4495 ? EDGE_PRED (e
->dest
, 1)->src
4496 : EDGE_PRED (e
->dest
, 0)->src
);
4498 /* Found additional edge leading to path from e1 to e2
4502 else if (EDGE_COUNT (e
->dest
->preds
) > 2)
4503 /* Several edges leading to path from e1 to e2 from aside. */
4507 return ((!lax
|| candidate_block
)
4508 && block_valid_for_bookkeeping_p (candidate_block
)
4512 if (lax
&& EDGE_COUNT (e
->dest
->succs
) != 1)
4522 /* Create new basic block for bookkeeping code for path(s) incoming into
4523 E2->dest, except from E1->src. Return created block. */
4525 create_block_for_bookkeeping (edge e1
, edge e2
)
4527 basic_block new_bb
, bb
= e2
->dest
;
4529 /* Check that we don't spoil the loop structure. */
4530 if (current_loop_nest
)
4532 basic_block latch
= current_loop_nest
->latch
;
4534 /* We do not split header. */
4535 gcc_assert (e2
->dest
!= current_loop_nest
->header
);
4537 /* We do not redirect the only edge to the latch block. */
4538 gcc_assert (e1
->dest
!= latch
4539 || !single_pred_p (latch
)
4540 || e1
!= single_pred_edge (latch
));
4543 /* Split BB to insert BOOK_INSN there. */
4544 new_bb
= sched_split_block (bb
, NULL
);
4546 /* Move note_list from the upper bb. */
4547 gcc_assert (BB_NOTE_LIST (new_bb
) == NULL_RTX
);
4548 BB_NOTE_LIST (new_bb
) = BB_NOTE_LIST (bb
);
4549 BB_NOTE_LIST (bb
) = NULL_RTX
;
4551 gcc_assert (e2
->dest
== bb
);
4553 /* Skip block for bookkeeping copy when leaving E1->src. */
4554 if (e1
->flags
& EDGE_FALLTHRU
)
4555 sel_redirect_edge_and_branch_force (e1
, new_bb
);
4557 sel_redirect_edge_and_branch (e1
, new_bb
);
4559 gcc_assert (e1
->dest
== new_bb
);
4560 gcc_assert (sel_bb_empty_p (bb
));
4562 /* To keep basic block numbers in sync between debug and non-debug
4563 compilations, we have to rotate blocks here. Consider that we
4564 started from (a,b)->d, (c,d)->e, and d contained only debug
4565 insns. It would have been removed before if the debug insns
4566 weren't there, so we'd have split e rather than d. So what we do
4567 now is to swap the block numbers of new_bb and
4568 single_succ(new_bb) == e, so that the insns that were in e before
4569 get the new block number. */
4571 if (MAY_HAVE_DEBUG_INSNS
)
4574 insn_t insn
= sel_bb_head (new_bb
);
4577 if (DEBUG_INSN_P (insn
)
4578 && single_succ_p (new_bb
)
4579 && (succ
= single_succ (new_bb
))
4580 && succ
!= EXIT_BLOCK_PTR
4581 && DEBUG_INSN_P ((last
= sel_bb_end (new_bb
))))
4583 while (insn
!= last
&& (DEBUG_INSN_P (insn
) || NOTE_P (insn
)))
4584 insn
= NEXT_INSN (insn
);
4588 sel_global_bb_info_def gbi
;
4589 sel_region_bb_info_def rbi
;
4592 if (sched_verbose
>= 2)
4593 sel_print ("Swapping block ids %i and %i\n",
4594 new_bb
->index
, succ
->index
);
4597 new_bb
->index
= succ
->index
;
4600 SET_BASIC_BLOCK (new_bb
->index
, new_bb
);
4601 SET_BASIC_BLOCK (succ
->index
, succ
);
4603 memcpy (&gbi
, SEL_GLOBAL_BB_INFO (new_bb
), sizeof (gbi
));
4604 memcpy (SEL_GLOBAL_BB_INFO (new_bb
), SEL_GLOBAL_BB_INFO (succ
),
4606 memcpy (SEL_GLOBAL_BB_INFO (succ
), &gbi
, sizeof (gbi
));
4608 memcpy (&rbi
, SEL_REGION_BB_INFO (new_bb
), sizeof (rbi
));
4609 memcpy (SEL_REGION_BB_INFO (new_bb
), SEL_REGION_BB_INFO (succ
),
4611 memcpy (SEL_REGION_BB_INFO (succ
), &rbi
, sizeof (rbi
));
4613 i
= BLOCK_TO_BB (new_bb
->index
);
4614 BLOCK_TO_BB (new_bb
->index
) = BLOCK_TO_BB (succ
->index
);
4615 BLOCK_TO_BB (succ
->index
) = i
;
4617 i
= CONTAINING_RGN (new_bb
->index
);
4618 CONTAINING_RGN (new_bb
->index
) = CONTAINING_RGN (succ
->index
);
4619 CONTAINING_RGN (succ
->index
) = i
;
4621 for (i
= 0; i
< current_nr_blocks
; i
++)
4622 if (BB_TO_BLOCK (i
) == succ
->index
)
4623 BB_TO_BLOCK (i
) = new_bb
->index
;
4624 else if (BB_TO_BLOCK (i
) == new_bb
->index
)
4625 BB_TO_BLOCK (i
) = succ
->index
;
4627 FOR_BB_INSNS (new_bb
, insn
)
4629 EXPR_ORIG_BB_INDEX (INSN_EXPR (insn
)) = new_bb
->index
;
4631 FOR_BB_INSNS (succ
, insn
)
4633 EXPR_ORIG_BB_INDEX (INSN_EXPR (insn
)) = succ
->index
;
4635 if (bitmap_clear_bit (code_motion_visited_blocks
, new_bb
->index
))
4636 bitmap_set_bit (code_motion_visited_blocks
, succ
->index
);
4638 gcc_assert (LABEL_P (BB_HEAD (new_bb
))
4639 && LABEL_P (BB_HEAD (succ
)));
4641 if (sched_verbose
>= 4)
4642 sel_print ("Swapping code labels %i and %i\n",
4643 CODE_LABEL_NUMBER (BB_HEAD (new_bb
)),
4644 CODE_LABEL_NUMBER (BB_HEAD (succ
)));
4646 i
= CODE_LABEL_NUMBER (BB_HEAD (new_bb
));
4647 CODE_LABEL_NUMBER (BB_HEAD (new_bb
))
4648 = CODE_LABEL_NUMBER (BB_HEAD (succ
));
4649 CODE_LABEL_NUMBER (BB_HEAD (succ
)) = i
;
4657 /* Return insn after which we must insert bookkeeping code for path(s) incoming
4658 into E2->dest, except from E1->src. */
4660 find_place_for_bookkeeping (edge e1
, edge e2
)
4662 insn_t place_to_insert
;
4663 /* Find a basic block that can hold bookkeeping. If it can be found, do not
4664 create new basic block, but insert bookkeeping there. */
4665 basic_block book_block
= find_block_for_bookkeeping (e1
, e2
, FALSE
);
4669 place_to_insert
= BB_END (book_block
);
4671 /* Don't use a block containing only debug insns for
4672 bookkeeping, this causes scheduling differences between debug
4673 and non-debug compilations, for the block would have been
4675 if (DEBUG_INSN_P (place_to_insert
))
4677 rtx insn
= sel_bb_head (book_block
);
4679 while (insn
!= place_to_insert
&&
4680 (DEBUG_INSN_P (insn
) || NOTE_P (insn
)))
4681 insn
= NEXT_INSN (insn
);
4683 if (insn
== place_to_insert
)
4690 book_block
= create_block_for_bookkeeping (e1
, e2
);
4691 place_to_insert
= BB_END (book_block
);
4692 if (sched_verbose
>= 9)
4693 sel_print ("New block is %i, split from bookkeeping block %i\n",
4694 EDGE_SUCC (book_block
, 0)->dest
->index
, book_block
->index
);
4698 if (sched_verbose
>= 9)
4699 sel_print ("Pre-existing bookkeeping block is %i\n", book_block
->index
);
4702 /* If basic block ends with a jump, insert bookkeeping code right before it. */
4703 if (INSN_P (place_to_insert
) && control_flow_insn_p (place_to_insert
))
4704 place_to_insert
= PREV_INSN (place_to_insert
);
4706 return place_to_insert
;
4709 /* Find a proper seqno for bookkeeing insn inserted at PLACE_TO_INSERT
4712 find_seqno_for_bookkeeping (insn_t place_to_insert
, insn_t join_point
)
4717 /* Check if we are about to insert bookkeeping copy before a jump, and use
4718 jump's seqno for the copy; otherwise, use JOIN_POINT's seqno. */
4719 next
= NEXT_INSN (place_to_insert
);
4722 && BLOCK_FOR_INSN (next
) == BLOCK_FOR_INSN (place_to_insert
))
4724 gcc_assert (INSN_SCHED_TIMES (next
) == 0);
4725 seqno
= INSN_SEQNO (next
);
4727 else if (INSN_SEQNO (join_point
) > 0)
4728 seqno
= INSN_SEQNO (join_point
);
4731 seqno
= get_seqno_by_preds (place_to_insert
);
4733 /* Sometimes the fences can move in such a way that there will be
4734 no instructions with positive seqno around this bookkeeping.
4735 This means that there will be no way to get to it by a regular
4736 fence movement. Never mind because we pick up such pieces for
4737 rescheduling anyways, so any positive value will do for now. */
4740 gcc_assert (pipelining_p
);
4745 gcc_assert (seqno
> 0);
4749 /* Insert bookkeeping copy of C_EXPS's insn after PLACE_TO_INSERT, assigning
4750 NEW_SEQNO to it. Return created insn. */
4752 emit_bookkeeping_insn (insn_t place_to_insert
, expr_t c_expr
, int new_seqno
)
4754 rtx new_insn_rtx
= create_copy_of_insn_rtx (EXPR_INSN_RTX (c_expr
));
4757 = create_vinsn_from_insn_rtx (new_insn_rtx
,
4758 VINSN_UNIQUE_P (EXPR_VINSN (c_expr
)));
4760 insn_t new_insn
= emit_insn_from_expr_after (c_expr
, new_vinsn
, new_seqno
,
4763 INSN_SCHED_TIMES (new_insn
) = 0;
4764 bitmap_set_bit (current_copies
, INSN_UID (new_insn
));
4769 /* Generate a bookkeeping copy of C_EXPR's insn for path(s) incoming into to
4770 E2->dest, except from E1->src (there may be a sequence of empty blocks
4771 between E1->src and E2->dest). Return block containing the copy.
4772 All scheduler data is initialized for the newly created insn. */
4774 generate_bookkeeping_insn (expr_t c_expr
, edge e1
, edge e2
)
4776 insn_t join_point
, place_to_insert
, new_insn
;
4778 bool need_to_exchange_data_sets
;
4780 if (sched_verbose
>= 4)
4781 sel_print ("Generating bookkeeping insn (%d->%d)\n", e1
->src
->index
,
4784 join_point
= sel_bb_head (e2
->dest
);
4785 place_to_insert
= find_place_for_bookkeeping (e1
, e2
);
4786 if (!place_to_insert
)
4788 new_seqno
= find_seqno_for_bookkeeping (place_to_insert
, join_point
);
4789 need_to_exchange_data_sets
4790 = sel_bb_empty_p (BLOCK_FOR_INSN (place_to_insert
));
4792 new_insn
= emit_bookkeeping_insn (place_to_insert
, c_expr
, new_seqno
);
4794 /* When inserting bookkeeping insn in new block, av sets should be
4795 following: old basic block (that now holds bookkeeping) data sets are
4796 the same as was before generation of bookkeeping, and new basic block
4797 (that now hold all other insns of old basic block) data sets are
4798 invalid. So exchange data sets for these basic blocks as sel_split_block
4799 mistakenly exchanges them in this case. Cannot do it earlier because
4800 when single instruction is added to new basic block it should hold NULL
4802 if (need_to_exchange_data_sets
)
4803 exchange_data_sets (BLOCK_FOR_INSN (new_insn
),
4804 BLOCK_FOR_INSN (join_point
));
4806 stat_bookkeeping_copies
++;
4807 return BLOCK_FOR_INSN (new_insn
);
4810 /* Remove from AV_PTR all insns that may need bookkeeping when scheduling
4811 on FENCE, but we are unable to copy them. */
4813 remove_insns_that_need_bookkeeping (fence_t fence
, av_set_t
*av_ptr
)
4818 /* An expression does not need bookkeeping if it is available on all paths
4819 from current block to original block and current block dominates
4820 original block. We check availability on all paths by examining
4821 EXPR_SPEC; this is not equivalent, because it may be positive even
4822 if expr is available on all paths (but if expr is not available on
4823 any path, EXPR_SPEC will be positive). */
4825 FOR_EACH_EXPR_1 (expr
, i
, av_ptr
)
4827 if (!control_flow_insn_p (EXPR_INSN_RTX (expr
))
4828 && (!bookkeeping_p
|| VINSN_UNIQUE_P (EXPR_VINSN (expr
)))
4829 && (EXPR_SPEC (expr
)
4830 || !EXPR_ORIG_BB_INDEX (expr
)
4831 || !dominated_by_p (CDI_DOMINATORS
,
4832 BASIC_BLOCK (EXPR_ORIG_BB_INDEX (expr
)),
4833 BLOCK_FOR_INSN (FENCE_INSN (fence
)))))
4835 if (sched_verbose
>= 4)
4836 sel_print ("Expr %d removed because it would need bookkeeping, which "
4837 "cannot be created\n", INSN_UID (EXPR_INSN_RTX (expr
)));
4838 av_set_iter_remove (&i
);
4843 /* Moving conditional jump through some instructions.
4847 ... <- current scheduling point
4848 NOTE BASIC BLOCK: <- bb header
4849 (p8) add r14=r14+0x9;;
4855 We can schedule jump one cycle earlier, than mov, because they cannot be
4856 executed together as their predicates are mutually exclusive.
4858 This is done in this way: first, new fallthrough basic block is created
4859 after jump (it is always can be done, because there already should be a
4860 fallthrough block, where control flow goes in case of predicate being true -
4861 in our example; otherwise there should be a dependence between those
4862 instructions and jump and we cannot schedule jump right now);
4863 next, all instructions between jump and current scheduling point are moved
4864 to this new block. And the result is this:
4867 (!p8) jump L1 <- current scheduling point
4868 NOTE BASIC BLOCK: <- bb header
4869 (p8) add r14=r14+0x9;;
4875 move_cond_jump (rtx insn
, bnd_t bnd
)
4878 basic_block block_from
, block_next
, block_new
, block_bnd
, bb
;
4879 rtx next
, prev
, link
, head
;
4881 block_from
= BLOCK_FOR_INSN (insn
);
4882 block_bnd
= BLOCK_FOR_INSN (BND_TO (bnd
));
4883 prev
= BND_TO (bnd
);
4885 #ifdef ENABLE_CHECKING
4886 /* Moving of jump should not cross any other jumps or beginnings of new
4887 basic blocks. The only exception is when we move a jump through
4888 mutually exclusive insns along fallthru edges. */
4889 if (block_from
!= block_bnd
)
4892 for (link
= PREV_INSN (insn
); link
!= PREV_INSN (prev
);
4893 link
= PREV_INSN (link
))
4896 gcc_assert (sched_insns_conditions_mutex_p (insn
, link
));
4897 if (BLOCK_FOR_INSN (link
) && BLOCK_FOR_INSN (link
) != bb
)
4899 gcc_assert (single_pred (bb
) == BLOCK_FOR_INSN (link
));
4900 bb
= BLOCK_FOR_INSN (link
);
4906 /* Jump is moved to the boundary. */
4907 next
= PREV_INSN (insn
);
4908 BND_TO (bnd
) = insn
;
4910 ft_edge
= find_fallthru_edge (block_from
);
4911 block_next
= ft_edge
->dest
;
4912 /* There must be a fallthrough block (or where should go
4913 control flow in case of false jump predicate otherwise?). */
4914 gcc_assert (block_next
);
4916 /* Create new empty basic block after source block. */
4917 block_new
= sel_split_edge (ft_edge
);
4918 gcc_assert (block_new
->next_bb
== block_next
4919 && block_from
->next_bb
== block_new
);
4921 /* Move all instructions except INSN to BLOCK_NEW. */
4923 head
= BB_HEAD (block_new
);
4924 while (bb
!= block_from
->next_bb
)
4927 from
= bb
== block_bnd
? prev
: sel_bb_head (bb
);
4928 to
= bb
== block_from
? next
: sel_bb_end (bb
);
4930 /* The jump being moved can be the first insn in the block.
4931 In this case we don't have to move anything in this block. */
4932 if (NEXT_INSN (to
) != from
)
4934 reorder_insns (from
, to
, head
);
4936 for (link
= to
; link
!= head
; link
= PREV_INSN (link
))
4937 EXPR_ORIG_BB_INDEX (INSN_EXPR (link
)) = block_new
->index
;
4941 /* Cleanup possibly empty blocks left. */
4942 block_next
= bb
->next_bb
;
4943 if (bb
!= block_from
)
4944 tidy_control_flow (bb
, false);
4948 /* Assert there is no jump to BLOCK_NEW, only fallthrough edge. */
4949 gcc_assert (NOTE_INSN_BASIC_BLOCK_P (BB_HEAD (block_new
)));
4951 gcc_assert (!sel_bb_empty_p (block_from
)
4952 && !sel_bb_empty_p (block_new
));
4954 /* Update data sets for BLOCK_NEW to represent that INSN and
4955 instructions from the other branch of INSN is no longer
4956 available at BLOCK_NEW. */
4957 BB_AV_LEVEL (block_new
) = global_level
;
4958 gcc_assert (BB_LV_SET (block_new
) == NULL
);
4959 BB_LV_SET (block_new
) = get_clear_regset_from_pool ();
4960 update_data_sets (sel_bb_head (block_new
));
4962 /* INSN is a new basic block header - so prepare its data
4963 structures and update availability and liveness sets. */
4964 update_data_sets (insn
);
4966 if (sched_verbose
>= 4)
4967 sel_print ("Moving jump %d\n", INSN_UID (insn
));
4970 /* Remove nops generated during move_op for preventing removal of empty
4973 remove_temp_moveop_nops (bool full_tidying
)
4978 FOR_EACH_VEC_ELT (insn_t
, vec_temp_moveop_nops
, i
, insn
)
4980 gcc_assert (INSN_NOP_P (insn
));
4981 return_nop_to_pool (insn
, full_tidying
);
4984 /* Empty the vector. */
4985 if (VEC_length (insn_t
, vec_temp_moveop_nops
) > 0)
4986 VEC_block_remove (insn_t
, vec_temp_moveop_nops
, 0,
4987 VEC_length (insn_t
, vec_temp_moveop_nops
));
4990 /* Records the maximal UID before moving up an instruction. Used for
4991 distinguishing between bookkeeping copies and original insns. */
4992 static int max_uid_before_move_op
= 0;
4994 /* Remove from AV_VLIW_P all instructions but next when debug counter
4995 tells us so. Next instruction is fetched from BNDS. */
4997 remove_insns_for_debug (blist_t bnds
, av_set_t
*av_vliw_p
)
4999 if (! dbg_cnt (sel_sched_insn_cnt
))
5000 /* Leave only the next insn in av_vliw. */
5002 av_set_iterator av_it
;
5004 bnd_t bnd
= BLIST_BND (bnds
);
5005 insn_t next
= BND_TO (bnd
);
5007 gcc_assert (BLIST_NEXT (bnds
) == NULL
);
5009 FOR_EACH_EXPR_1 (expr
, av_it
, av_vliw_p
)
5010 if (EXPR_INSN_RTX (expr
) != next
)
5011 av_set_iter_remove (&av_it
);
5015 /* Compute available instructions on BNDS. FENCE is the current fence. Write
5016 the computed set to *AV_VLIW_P. */
5018 compute_av_set_on_boundaries (fence_t fence
, blist_t bnds
, av_set_t
*av_vliw_p
)
5020 if (sched_verbose
>= 2)
5022 sel_print ("Boundaries: ");
5027 for (; bnds
; bnds
= BLIST_NEXT (bnds
))
5029 bnd_t bnd
= BLIST_BND (bnds
);
5031 insn_t bnd_to
= BND_TO (bnd
);
5033 /* Rewind BND->TO to the basic block header in case some bookkeeping
5034 instructions were inserted before BND->TO and it needs to be
5036 if (sel_bb_head_p (bnd_to
))
5037 gcc_assert (INSN_SCHED_TIMES (bnd_to
) == 0);
5039 while (INSN_SCHED_TIMES (PREV_INSN (bnd_to
)) == 0)
5041 bnd_to
= PREV_INSN (bnd_to
);
5042 if (sel_bb_head_p (bnd_to
))
5046 if (BND_TO (bnd
) != bnd_to
)
5048 gcc_assert (FENCE_INSN (fence
) == BND_TO (bnd
));
5049 FENCE_INSN (fence
) = bnd_to
;
5050 BND_TO (bnd
) = bnd_to
;
5053 av_set_clear (&BND_AV (bnd
));
5054 BND_AV (bnd
) = compute_av_set (BND_TO (bnd
), NULL
, 0, true);
5056 av_set_clear (&BND_AV1 (bnd
));
5057 BND_AV1 (bnd
) = av_set_copy (BND_AV (bnd
));
5059 moveup_set_inside_insn_group (&BND_AV1 (bnd
), NULL
);
5061 av1_copy
= av_set_copy (BND_AV1 (bnd
));
5062 av_set_union_and_clear (av_vliw_p
, &av1_copy
, NULL
);
5065 if (sched_verbose
>= 2)
5067 sel_print ("Available exprs (vliw form): ");
5068 dump_av_set (*av_vliw_p
);
5073 /* Calculate the sequential av set on BND corresponding to the EXPR_VLIW
5074 expression. When FOR_MOVEOP is true, also replace the register of
5075 expressions found with the register from EXPR_VLIW. */
5077 find_sequential_best_exprs (bnd_t bnd
, expr_t expr_vliw
, bool for_moveop
)
5079 av_set_t expr_seq
= NULL
;
5083 FOR_EACH_EXPR (expr
, i
, BND_AV (bnd
))
5085 if (equal_after_moveup_path_p (expr
, NULL
, expr_vliw
))
5089 /* The sequential expression has the right form to pass
5090 to move_op except when renaming happened. Put the
5091 correct register in EXPR then. */
5092 if (EXPR_SEPARABLE_P (expr
) && REG_P (EXPR_LHS (expr
)))
5094 if (expr_dest_regno (expr
) != expr_dest_regno (expr_vliw
))
5096 replace_dest_with_reg_in_expr (expr
, EXPR_LHS (expr_vliw
));
5097 stat_renamed_scheduled
++;
5099 /* Also put the correct TARGET_AVAILABLE bit on the expr.
5100 This is needed when renaming came up with original
5102 else if (EXPR_TARGET_AVAILABLE (expr
)
5103 != EXPR_TARGET_AVAILABLE (expr_vliw
))
5105 gcc_assert (EXPR_TARGET_AVAILABLE (expr_vliw
) == 1);
5106 EXPR_TARGET_AVAILABLE (expr
) = 1;
5109 if (EXPR_WAS_SUBSTITUTED (expr
))
5110 stat_substitutions_total
++;
5113 av_set_add (&expr_seq
, expr
);
5115 /* With substitution inside insn group, it is possible
5116 that more than one expression in expr_seq will correspond
5117 to expr_vliw. In this case, choose one as the attempt to
5118 move both leads to miscompiles. */
5123 if (for_moveop
&& sched_verbose
>= 2)
5125 sel_print ("Best expression(s) (sequential form): ");
5126 dump_av_set (expr_seq
);
5134 /* Move nop to previous block. */
5135 static void ATTRIBUTE_UNUSED
5136 move_nop_to_previous_block (insn_t nop
, basic_block prev_bb
)
5138 insn_t prev_insn
, next_insn
, note
;
5140 gcc_assert (sel_bb_head_p (nop
)
5141 && prev_bb
== BLOCK_FOR_INSN (nop
)->prev_bb
);
5142 note
= bb_note (BLOCK_FOR_INSN (nop
));
5143 prev_insn
= sel_bb_end (prev_bb
);
5144 next_insn
= NEXT_INSN (nop
);
5145 gcc_assert (prev_insn
!= NULL_RTX
5146 && PREV_INSN (note
) == prev_insn
);
5148 NEXT_INSN (prev_insn
) = nop
;
5149 PREV_INSN (nop
) = prev_insn
;
5151 PREV_INSN (note
) = nop
;
5152 NEXT_INSN (note
) = next_insn
;
5154 NEXT_INSN (nop
) = note
;
5155 PREV_INSN (next_insn
) = note
;
5157 BB_END (prev_bb
) = nop
;
5158 BLOCK_FOR_INSN (nop
) = prev_bb
;
5161 /* Prepare a place to insert the chosen expression on BND. */
5163 prepare_place_to_insert (bnd_t bnd
)
5165 insn_t place_to_insert
;
5167 /* Init place_to_insert before calling move_op, as the later
5168 can possibly remove BND_TO (bnd). */
5169 if (/* If this is not the first insn scheduled. */
5172 /* Add it after last scheduled. */
5173 place_to_insert
= ILIST_INSN (BND_PTR (bnd
));
5174 if (DEBUG_INSN_P (place_to_insert
))
5176 ilist_t l
= BND_PTR (bnd
);
5177 while ((l
= ILIST_NEXT (l
)) &&
5178 DEBUG_INSN_P (ILIST_INSN (l
)))
5181 place_to_insert
= NULL
;
5185 place_to_insert
= NULL
;
5187 if (!place_to_insert
)
5189 /* Add it before BND_TO. The difference is in the
5190 basic block, where INSN will be added. */
5191 place_to_insert
= get_nop_from_pool (BND_TO (bnd
));
5192 gcc_assert (BLOCK_FOR_INSN (place_to_insert
)
5193 == BLOCK_FOR_INSN (BND_TO (bnd
)));
5196 return place_to_insert
;
5199 /* Find original instructions for EXPR_SEQ and move it to BND boundary.
5200 Return the expression to emit in C_EXPR. */
5202 move_exprs_to_boundary (bnd_t bnd
, expr_t expr_vliw
,
5203 av_set_t expr_seq
, expr_t c_expr
)
5205 bool b
, should_move
;
5208 int n_bookkeeping_copies_before_moveop
;
5210 /* Make a move. This call will remove the original operation,
5211 insert all necessary bookkeeping instructions and update the
5212 data sets. After that all we have to do is add the operation
5213 at before BND_TO (BND). */
5214 n_bookkeeping_copies_before_moveop
= stat_bookkeeping_copies
;
5215 max_uid_before_move_op
= get_max_uid ();
5216 bitmap_clear (current_copies
);
5217 bitmap_clear (current_originators
);
5219 b
= move_op (BND_TO (bnd
), expr_seq
, expr_vliw
,
5220 get_dest_from_orig_ops (expr_seq
), c_expr
, &should_move
);
5222 /* We should be able to find the expression we've chosen for
5226 if (stat_bookkeeping_copies
> n_bookkeeping_copies_before_moveop
)
5227 stat_insns_needed_bookkeeping
++;
5229 EXECUTE_IF_SET_IN_BITMAP (current_copies
, 0, book_uid
, bi
)
5234 /* We allocate these bitmaps lazily. */
5235 if (! INSN_ORIGINATORS_BY_UID (book_uid
))
5236 INSN_ORIGINATORS_BY_UID (book_uid
) = BITMAP_ALLOC (NULL
);
5238 bitmap_copy (INSN_ORIGINATORS_BY_UID (book_uid
),
5239 current_originators
);
5241 /* Transitively add all originators' originators. */
5242 EXECUTE_IF_SET_IN_BITMAP (current_originators
, 0, uid
, bi
)
5243 if (INSN_ORIGINATORS_BY_UID (uid
))
5244 bitmap_ior_into (INSN_ORIGINATORS_BY_UID (book_uid
),
5245 INSN_ORIGINATORS_BY_UID (uid
));
5252 /* Debug a DFA state as an array of bytes. */
5254 debug_state (state_t state
)
5257 unsigned int i
, size
= dfa_state_size
;
5259 sel_print ("state (%u):", size
);
5260 for (i
= 0, p
= (unsigned char *) state
; i
< size
; i
++)
5261 sel_print (" %d", p
[i
]);
5265 /* Advance state on FENCE with INSN. Return true if INSN is
5266 an ASM, and we should advance state once more. */
5268 advance_state_on_fence (fence_t fence
, insn_t insn
)
5272 if (recog_memoized (insn
) >= 0)
5275 state_t temp_state
= alloca (dfa_state_size
);
5277 gcc_assert (!INSN_ASM_P (insn
));
5280 memcpy (temp_state
, FENCE_STATE (fence
), dfa_state_size
);
5281 res
= state_transition (FENCE_STATE (fence
), insn
);
5282 gcc_assert (res
< 0);
5284 if (memcmp (temp_state
, FENCE_STATE (fence
), dfa_state_size
))
5286 FENCE_ISSUED_INSNS (fence
)++;
5288 /* We should never issue more than issue_rate insns. */
5289 if (FENCE_ISSUED_INSNS (fence
) > issue_rate
)
5295 /* This could be an ASM insn which we'd like to schedule
5296 on the next cycle. */
5297 asm_p
= INSN_ASM_P (insn
);
5298 if (!FENCE_STARTS_CYCLE_P (fence
) && asm_p
)
5299 advance_one_cycle (fence
);
5302 if (sched_verbose
>= 2)
5303 debug_state (FENCE_STATE (fence
));
5304 if (!DEBUG_INSN_P (insn
))
5305 FENCE_STARTS_CYCLE_P (fence
) = 0;
5306 FENCE_ISSUE_MORE (fence
) = can_issue_more
;
5310 /* Update FENCE on which INSN was scheduled and this INSN, too. NEED_STALL
5311 is nonzero if we need to stall after issuing INSN. */
5313 update_fence_and_insn (fence_t fence
, insn_t insn
, int need_stall
)
5317 /* First, reflect that something is scheduled on this fence. */
5318 asm_p
= advance_state_on_fence (fence
, insn
);
5319 FENCE_LAST_SCHEDULED_INSN (fence
) = insn
;
5320 VEC_safe_push (rtx
, gc
, FENCE_EXECUTING_INSNS (fence
), insn
);
5321 if (SCHED_GROUP_P (insn
))
5323 FENCE_SCHED_NEXT (fence
) = INSN_SCHED_NEXT (insn
);
5324 SCHED_GROUP_P (insn
) = 0;
5327 FENCE_SCHED_NEXT (fence
) = NULL_RTX
;
5328 if (INSN_UID (insn
) < FENCE_READY_TICKS_SIZE (fence
))
5329 FENCE_READY_TICKS (fence
) [INSN_UID (insn
)] = 0;
5331 /* Set instruction scheduling info. This will be used in bundling,
5332 pipelining, tick computations etc. */
5333 ++INSN_SCHED_TIMES (insn
);
5334 EXPR_TARGET_AVAILABLE (INSN_EXPR (insn
)) = true;
5335 EXPR_ORIG_SCHED_CYCLE (INSN_EXPR (insn
)) = FENCE_CYCLE (fence
);
5336 INSN_AFTER_STALL_P (insn
) = FENCE_AFTER_STALL_P (fence
);
5337 INSN_SCHED_CYCLE (insn
) = FENCE_CYCLE (fence
);
5339 /* This does not account for adjust_cost hooks, just add the biggest
5340 constant the hook may add to the latency. TODO: make this
5341 a target dependent constant. */
5342 INSN_READY_CYCLE (insn
)
5343 = INSN_SCHED_CYCLE (insn
) + (INSN_CODE (insn
) < 0
5345 : maximal_insn_latency (insn
) + 1);
5347 /* Change these fields last, as they're used above. */
5348 FENCE_AFTER_STALL_P (fence
) = 0;
5349 if (asm_p
|| need_stall
)
5350 advance_one_cycle (fence
);
5352 /* Indicate that we've scheduled something on this fence. */
5353 FENCE_SCHEDULED_P (fence
) = true;
5354 scheduled_something_on_previous_fence
= true;
5356 /* Print debug information when insn's fields are updated. */
5357 if (sched_verbose
>= 2)
5359 sel_print ("Scheduling insn: ");
5360 dump_insn_1 (insn
, 1);
5365 /* Update boundary BND (and, if needed, FENCE) with INSN, remove the
5366 old boundary from BNDSP, add new boundaries to BNDS_TAIL_P and
5369 update_boundaries (fence_t fence
, bnd_t bnd
, insn_t insn
, blist_t
*bndsp
,
5370 blist_t
*bnds_tailp
)
5375 advance_deps_context (BND_DC (bnd
), insn
);
5376 FOR_EACH_SUCC_1 (succ
, si
, insn
,
5377 SUCCS_NORMAL
| SUCCS_SKIP_TO_LOOP_EXITS
)
5379 ilist_t ptr
= ilist_copy (BND_PTR (bnd
));
5381 ilist_add (&ptr
, insn
);
5383 if (DEBUG_INSN_P (insn
) && sel_bb_end_p (insn
)
5384 && is_ineligible_successor (succ
, ptr
))
5390 if (FENCE_INSN (fence
) == insn
&& !sel_bb_end_p (insn
))
5392 if (sched_verbose
>= 9)
5393 sel_print ("Updating fence insn from %i to %i\n",
5394 INSN_UID (insn
), INSN_UID (succ
));
5395 FENCE_INSN (fence
) = succ
;
5397 blist_add (bnds_tailp
, succ
, ptr
, BND_DC (bnd
));
5398 bnds_tailp
= &BLIST_NEXT (*bnds_tailp
);
5401 blist_remove (bndsp
);
5405 /* Schedule EXPR_VLIW on BND. Return the insn emitted. */
5407 schedule_expr_on_boundary (bnd_t bnd
, expr_t expr_vliw
, int seqno
)
5410 expr_t c_expr
= XALLOCA (expr_def
);
5411 insn_t place_to_insert
;
5415 expr_seq
= find_sequential_best_exprs (bnd
, expr_vliw
, true);
5417 /* In case of scheduling a jump skipping some other instructions,
5418 prepare CFG. After this, jump is at the boundary and can be
5419 scheduled as usual insn by MOVE_OP. */
5420 if (vinsn_cond_branch_p (EXPR_VINSN (expr_vliw
)))
5422 insn
= EXPR_INSN_RTX (expr_vliw
);
5424 /* Speculative jumps are not handled. */
5425 if (insn
!= BND_TO (bnd
)
5426 && !sel_insn_is_speculation_check (insn
))
5427 move_cond_jump (insn
, bnd
);
5430 /* Find a place for C_EXPR to schedule. */
5431 place_to_insert
= prepare_place_to_insert (bnd
);
5432 should_move
= move_exprs_to_boundary (bnd
, expr_vliw
, expr_seq
, c_expr
);
5433 clear_expr (c_expr
);
5435 /* Add the instruction. The corner case to care about is when
5436 the expr_seq set has more than one expr, and we chose the one that
5437 is not equal to expr_vliw. Then expr_vliw may be insn in stream, and
5438 we can't use it. Generate the new vinsn. */
5439 if (INSN_IN_STREAM_P (EXPR_INSN_RTX (expr_vliw
)))
5443 vinsn_new
= vinsn_copy (EXPR_VINSN (expr_vliw
), false);
5444 change_vinsn_in_expr (expr_vliw
, vinsn_new
);
5445 should_move
= false;
5448 insn
= sel_move_insn (expr_vliw
, seqno
, place_to_insert
);
5450 insn
= emit_insn_from_expr_after (expr_vliw
, NULL
, seqno
,
5453 /* Return the nops generated for preserving of data sets back
5455 if (INSN_NOP_P (place_to_insert
))
5456 return_nop_to_pool (place_to_insert
, !DEBUG_INSN_P (insn
));
5457 remove_temp_moveop_nops (!DEBUG_INSN_P (insn
));
5459 av_set_clear (&expr_seq
);
5461 /* Save the expression scheduled so to reset target availability if we'll
5462 meet it later on the same fence. */
5463 if (EXPR_WAS_RENAMED (expr_vliw
))
5464 vinsn_vec_add (&vec_target_unavailable_vinsns
, INSN_EXPR (insn
));
5466 /* Check that the recent movement didn't destroyed loop
5468 gcc_assert (!pipelining_p
5469 || current_loop_nest
== NULL
5470 || loop_latch_edge (current_loop_nest
));
5474 /* Stall for N cycles on FENCE. */
5476 stall_for_cycles (fence_t fence
, int n
)
5480 could_more
= n
> 1 || FENCE_ISSUED_INSNS (fence
) < issue_rate
;
5482 advance_one_cycle (fence
);
5484 FENCE_AFTER_STALL_P (fence
) = 1;
5487 /* Gather a parallel group of insns at FENCE and assign their seqno
5488 to SEQNO. All scheduled insns are gathered in SCHEDULED_INSNS_TAILPP
5489 list for later recalculation of seqnos. */
5491 fill_insns (fence_t fence
, int seqno
, ilist_t
**scheduled_insns_tailpp
)
5493 blist_t bnds
= NULL
, *bnds_tailp
;
5494 av_set_t av_vliw
= NULL
;
5495 insn_t insn
= FENCE_INSN (fence
);
5497 if (sched_verbose
>= 2)
5498 sel_print ("Starting fill_insns for insn %d, cycle %d\n",
5499 INSN_UID (insn
), FENCE_CYCLE (fence
));
5501 blist_add (&bnds
, insn
, NULL
, FENCE_DC (fence
));
5502 bnds_tailp
= &BLIST_NEXT (bnds
);
5503 set_target_context (FENCE_TC (fence
));
5504 can_issue_more
= FENCE_ISSUE_MORE (fence
);
5505 target_bb
= INSN_BB (insn
);
5507 /* Do while we can add any operation to the current group. */
5510 blist_t
*bnds_tailp1
, *bndsp
;
5513 int was_stall
= 0, scheduled_insns
= 0, stall_iterations
= 0;
5514 int max_insns
= pipelining_p
? issue_rate
: 2 * issue_rate
;
5515 int max_stall
= pipelining_p
? 1 : 3;
5516 bool last_insn_was_debug
= false;
5517 bool was_debug_bb_end_p
= false;
5519 compute_av_set_on_boundaries (fence
, bnds
, &av_vliw
);
5520 remove_insns_that_need_bookkeeping (fence
, &av_vliw
);
5521 remove_insns_for_debug (bnds
, &av_vliw
);
5523 /* Return early if we have nothing to schedule. */
5524 if (av_vliw
== NULL
)
5527 /* Choose the best expression and, if needed, destination register
5531 expr_vliw
= find_best_expr (&av_vliw
, bnds
, fence
, &need_stall
);
5532 if (!expr_vliw
&& need_stall
)
5534 /* All expressions required a stall. Do not recompute av sets
5535 as we'll get the same answer (modulo the insns between
5536 the fence and its boundary, which will not be available for
5538 gcc_assert (! expr_vliw
&& stall_iterations
< 2);
5540 /* If we are going to stall for too long, break to recompute av
5541 sets and bring more insns for pipelining. */
5542 if (need_stall
<= 3)
5543 stall_for_cycles (fence
, need_stall
);
5546 stall_for_cycles (fence
, 1);
5551 while (! expr_vliw
&& need_stall
);
5553 /* Now either we've selected expr_vliw or we have nothing to schedule. */
5556 av_set_clear (&av_vliw
);
5561 bnds_tailp1
= bnds_tailp
;
5564 /* This code will be executed only once until we'd have several
5565 boundaries per fence. */
5567 bnd_t bnd
= BLIST_BND (*bndsp
);
5569 if (!av_set_is_in_p (BND_AV1 (bnd
), EXPR_VINSN (expr_vliw
)))
5571 bndsp
= &BLIST_NEXT (*bndsp
);
5575 insn
= schedule_expr_on_boundary (bnd
, expr_vliw
, seqno
);
5576 last_insn_was_debug
= DEBUG_INSN_P (insn
);
5577 if (last_insn_was_debug
)
5578 was_debug_bb_end_p
= (insn
== BND_TO (bnd
) && sel_bb_end_p (insn
));
5579 update_fence_and_insn (fence
, insn
, need_stall
);
5580 bnds_tailp
= update_boundaries (fence
, bnd
, insn
, bndsp
, bnds_tailp
);
5582 /* Add insn to the list of scheduled on this cycle instructions. */
5583 ilist_add (*scheduled_insns_tailpp
, insn
);
5584 *scheduled_insns_tailpp
= &ILIST_NEXT (**scheduled_insns_tailpp
);
5586 while (*bndsp
!= *bnds_tailp1
);
5588 av_set_clear (&av_vliw
);
5589 if (!last_insn_was_debug
)
5592 /* We currently support information about candidate blocks only for
5593 one 'target_bb' block. Hence we can't schedule after jump insn,
5594 as this will bring two boundaries and, hence, necessity to handle
5595 information for two or more blocks concurrently. */
5596 if ((last_insn_was_debug
? was_debug_bb_end_p
: sel_bb_end_p (insn
))
5598 && (was_stall
>= max_stall
5599 || scheduled_insns
>= max_insns
)))
5604 gcc_assert (!FENCE_BNDS (fence
));
5606 /* Update boundaries of the FENCE. */
5609 ilist_t ptr
= BND_PTR (BLIST_BND (bnds
));
5613 insn
= ILIST_INSN (ptr
);
5615 if (!ilist_is_in_p (FENCE_BNDS (fence
), insn
))
5616 ilist_add (&FENCE_BNDS (fence
), insn
);
5619 blist_remove (&bnds
);
5622 /* Update target context on the fence. */
5623 reset_target_context (FENCE_TC (fence
), false);
5626 /* All exprs in ORIG_OPS must have the same destination register or memory.
5627 Return that destination. */
5629 get_dest_from_orig_ops (av_set_t orig_ops
)
5631 rtx dest
= NULL_RTX
;
5632 av_set_iterator av_it
;
5634 bool first_p
= true;
5636 FOR_EACH_EXPR (expr
, av_it
, orig_ops
)
5638 rtx x
= EXPR_LHS (expr
);
5646 gcc_assert (dest
== x
5647 || (dest
!= NULL_RTX
&& x
!= NULL_RTX
5648 && rtx_equal_p (dest
, x
)));
5654 /* Update data sets for the bookkeeping block and record those expressions
5655 which become no longer available after inserting this bookkeeping. */
5657 update_and_record_unavailable_insns (basic_block book_block
)
5660 av_set_t old_av_set
= NULL
;
5662 rtx bb_end
= sel_bb_end (book_block
);
5664 /* First, get correct liveness in the bookkeeping block. The problem is
5665 the range between the bookeeping insn and the end of block. */
5666 update_liveness_on_insn (bb_end
);
5667 if (control_flow_insn_p (bb_end
))
5668 update_liveness_on_insn (PREV_INSN (bb_end
));
5670 /* If there's valid av_set on BOOK_BLOCK, then there might exist another
5671 fence above, where we may choose to schedule an insn which is
5672 actually blocked from moving up with the bookkeeping we create here. */
5673 if (AV_SET_VALID_P (sel_bb_head (book_block
)))
5675 old_av_set
= av_set_copy (BB_AV_SET (book_block
));
5676 update_data_sets (sel_bb_head (book_block
));
5678 /* Traverse all the expressions in the old av_set and check whether
5679 CUR_EXPR is in new AV_SET. */
5680 FOR_EACH_EXPR (cur_expr
, i
, old_av_set
)
5682 expr_t new_expr
= av_set_lookup (BB_AV_SET (book_block
),
5683 EXPR_VINSN (cur_expr
));
5686 /* In this case, we can just turn off the E_T_A bit, but we can't
5687 represent this information with the current vector. */
5688 || EXPR_TARGET_AVAILABLE (new_expr
)
5689 != EXPR_TARGET_AVAILABLE (cur_expr
))
5690 /* Unfortunately, the below code could be also fired up on
5692 FIXME: add an example of how this could happen. */
5693 vinsn_vec_add (&vec_bookkeeping_blocked_vinsns
, cur_expr
);
5696 av_set_clear (&old_av_set
);
5700 /* The main effect of this function is that sparams->c_expr is merged
5701 with (or copied to) lparams->c_expr_merged. If there's only one successor,
5702 we avoid merging anything by copying sparams->c_expr to lparams->c_expr_merged.
5703 lparams->c_expr_merged is copied back to sparams->c_expr after all
5704 successors has been traversed. lparams->c_expr_local is an expr allocated
5705 on stack in the caller function, and is used if there is more than one
5708 SUCC is one of the SUCCS_NORMAL successors of INSN,
5709 MOVEOP_DRV_CALL_RES is the result of call code_motion_path_driver on succ,
5710 LPARAMS and STATIC_PARAMS contain the parameters described above. */
5712 move_op_merge_succs (insn_t insn ATTRIBUTE_UNUSED
,
5713 insn_t succ ATTRIBUTE_UNUSED
,
5714 int moveop_drv_call_res
,
5715 cmpd_local_params_p lparams
, void *static_params
)
5717 moveop_static_params_p sparams
= (moveop_static_params_p
) static_params
;
5719 /* Nothing to do, if original expr wasn't found below. */
5720 if (moveop_drv_call_res
!= 1)
5723 /* If this is a first successor. */
5724 if (!lparams
->c_expr_merged
)
5726 lparams
->c_expr_merged
= sparams
->c_expr
;
5727 sparams
->c_expr
= lparams
->c_expr_local
;
5731 /* We must merge all found expressions to get reasonable
5732 EXPR_SPEC_DONE_DS for the resulting insn. If we don't
5733 do so then we can first find the expr with epsilon
5734 speculation success probability and only then with the
5735 good probability. As a result the insn will get epsilon
5736 probability and will never be scheduled because of
5737 weakness_cutoff in find_best_expr.
5739 We call merge_expr_data here instead of merge_expr
5740 because due to speculation C_EXPR and X may have the
5741 same insns with different speculation types. And as of
5742 now such insns are considered non-equal.
5744 However, EXPR_SCHED_TIMES is different -- we must get
5745 SCHED_TIMES from a real insn, not a bookkeeping copy.
5746 We force this here. Instead, we may consider merging
5747 SCHED_TIMES to the maximum instead of minimum in the
5749 int old_times
= EXPR_SCHED_TIMES (lparams
->c_expr_merged
);
5751 merge_expr_data (lparams
->c_expr_merged
, sparams
->c_expr
, NULL
);
5752 if (EXPR_SCHED_TIMES (sparams
->c_expr
) == 0)
5753 EXPR_SCHED_TIMES (lparams
->c_expr_merged
) = old_times
;
5755 clear_expr (sparams
->c_expr
);
5759 /* Add used regs for the successor SUCC into SPARAMS->USED_REGS.
5761 SUCC is one of the SUCCS_NORMAL successors of INSN,
5762 MOVEOP_DRV_CALL_RES is the result of call code_motion_path_driver on succ or 0,
5763 if SUCC is one of SUCCS_BACK or SUCCS_OUT.
5764 STATIC_PARAMS contain USED_REGS set. */
5766 fur_merge_succs (insn_t insn ATTRIBUTE_UNUSED
, insn_t succ
,
5767 int moveop_drv_call_res
,
5768 cmpd_local_params_p lparams ATTRIBUTE_UNUSED
,
5769 void *static_params
)
5772 fur_static_params_p sparams
= (fur_static_params_p
) static_params
;
5774 /* Here we compute live regsets only for branches that do not lie
5775 on the code motion paths. These branches correspond to value
5776 MOVEOP_DRV_CALL_RES==0 and include SUCCS_BACK and SUCCS_OUT, though
5777 for such branches code_motion_path_driver is not called. */
5778 if (moveop_drv_call_res
!= 0)
5781 /* Mark all registers that do not meet the following condition:
5782 (3) not live on the other path of any conditional branch
5783 that is passed by the operation, in case original
5784 operations are not present on both paths of the
5785 conditional branch. */
5786 succ_live
= compute_live (succ
);
5787 IOR_REG_SET (sparams
->used_regs
, succ_live
);
5790 /* This function is called after the last successor. Copies LP->C_EXPR_MERGED
5793 move_op_after_merge_succs (cmpd_local_params_p lp
, void *sparams
)
5795 moveop_static_params_p sp
= (moveop_static_params_p
) sparams
;
5797 sp
->c_expr
= lp
->c_expr_merged
;
5800 /* Track bookkeeping copies created, insns scheduled, and blocks for
5801 rescheduling when INSN is found by move_op. */
5803 track_scheduled_insns_and_blocks (rtx insn
)
5805 /* Even if this insn can be a copy that will be removed during current move_op,
5806 we still need to count it as an originator. */
5807 bitmap_set_bit (current_originators
, INSN_UID (insn
));
5809 if (!bitmap_clear_bit (current_copies
, INSN_UID (insn
)))
5811 /* Note that original block needs to be rescheduled, as we pulled an
5812 instruction out of it. */
5813 if (INSN_SCHED_TIMES (insn
) > 0)
5814 bitmap_set_bit (blocks_to_reschedule
, BLOCK_FOR_INSN (insn
)->index
);
5815 else if (INSN_UID (insn
) < first_emitted_uid
&& !DEBUG_INSN_P (insn
))
5816 num_insns_scheduled
++;
5819 /* For instructions we must immediately remove insn from the
5820 stream, so subsequent update_data_sets () won't include this
5822 For expr we must make insn look like "INSN_REG (insn) := c_expr". */
5823 if (INSN_UID (insn
) > max_uid_before_move_op
)
5824 stat_bookkeeping_copies
--;
5827 /* Emit a register-register copy for INSN if needed. Return true if
5828 emitted one. PARAMS is the move_op static parameters. */
5830 maybe_emit_renaming_copy (rtx insn
,
5831 moveop_static_params_p params
)
5833 bool insn_emitted
= false;
5836 /* Bail out early when expression can not be renamed at all. */
5837 if (!EXPR_SEPARABLE_P (params
->c_expr
))
5840 cur_reg
= expr_dest_reg (params
->c_expr
);
5841 gcc_assert (cur_reg
&& params
->dest
&& REG_P (params
->dest
));
5843 /* If original operation has expr and the register chosen for
5844 that expr is not original operation's dest reg, substitute
5845 operation's right hand side with the register chosen. */
5846 if (REGNO (params
->dest
) != REGNO (cur_reg
))
5848 insn_t reg_move_insn
, reg_move_insn_rtx
;
5850 reg_move_insn_rtx
= create_insn_rtx_with_rhs (INSN_VINSN (insn
),
5852 reg_move_insn
= sel_gen_insn_from_rtx_after (reg_move_insn_rtx
,
5856 EXPR_SPEC_DONE_DS (INSN_EXPR (reg_move_insn
)) = 0;
5857 replace_dest_with_reg_in_expr (params
->c_expr
, params
->dest
);
5859 insn_emitted
= true;
5860 params
->was_renamed
= true;
5863 return insn_emitted
;
5866 /* Emit a speculative check for INSN speculated as EXPR if needed.
5867 Return true if we've emitted one. PARAMS is the move_op static
5870 maybe_emit_speculative_check (rtx insn
, expr_t expr
,
5871 moveop_static_params_p params
)
5873 bool insn_emitted
= false;
5877 check_ds
= get_spec_check_type_for_insn (insn
, expr
);
5880 /* A speculation check should be inserted. */
5881 x
= create_speculation_check (params
->c_expr
, check_ds
, insn
);
5882 insn_emitted
= true;
5886 EXPR_SPEC_DONE_DS (INSN_EXPR (insn
)) = 0;
5890 gcc_assert (EXPR_SPEC_DONE_DS (INSN_EXPR (x
)) == 0
5891 && EXPR_SPEC_TO_CHECK_DS (INSN_EXPR (x
)) == 0);
5892 return insn_emitted
;
5895 /* Handle transformations that leave an insn in place of original
5896 insn such as renaming/speculation. Return true if one of such
5897 transformations actually happened, and we have emitted this insn. */
5899 handle_emitting_transformations (rtx insn
, expr_t expr
,
5900 moveop_static_params_p params
)
5902 bool insn_emitted
= false;
5904 insn_emitted
= maybe_emit_renaming_copy (insn
, params
);
5905 insn_emitted
|= maybe_emit_speculative_check (insn
, expr
, params
);
5907 return insn_emitted
;
5910 /* If INSN is the only insn in the basic block (not counting JUMP,
5911 which may be a jump to next insn, and DEBUG_INSNs), we want to
5912 leave a NOP there till the return to fill_insns. */
5915 need_nop_to_preserve_insn_bb (rtx insn
)
5917 insn_t bb_head
, bb_end
, bb_next
, in_next
;
5918 basic_block bb
= BLOCK_FOR_INSN (insn
);
5920 bb_head
= sel_bb_head (bb
);
5921 bb_end
= sel_bb_end (bb
);
5923 if (bb_head
== bb_end
)
5926 while (bb_head
!= bb_end
&& DEBUG_INSN_P (bb_head
))
5927 bb_head
= NEXT_INSN (bb_head
);
5929 if (bb_head
== bb_end
)
5932 while (bb_head
!= bb_end
&& DEBUG_INSN_P (bb_end
))
5933 bb_end
= PREV_INSN (bb_end
);
5935 if (bb_head
== bb_end
)
5938 bb_next
= NEXT_INSN (bb_head
);
5939 while (bb_next
!= bb_end
&& DEBUG_INSN_P (bb_next
))
5940 bb_next
= NEXT_INSN (bb_next
);
5942 if (bb_next
== bb_end
&& JUMP_P (bb_end
))
5945 in_next
= NEXT_INSN (insn
);
5946 while (DEBUG_INSN_P (in_next
))
5947 in_next
= NEXT_INSN (in_next
);
5949 if (IN_CURRENT_FENCE_P (in_next
))
5955 /* Remove INSN from stream. When ONLY_DISCONNECT is true, its data
5956 is not removed but reused when INSN is re-emitted. */
5958 remove_insn_from_stream (rtx insn
, bool only_disconnect
)
5960 /* If there's only one insn in the BB, make sure that a nop is
5961 inserted into it, so the basic block won't disappear when we'll
5962 delete INSN below with sel_remove_insn. It should also survive
5963 till the return to fill_insns. */
5964 if (need_nop_to_preserve_insn_bb (insn
))
5966 insn_t nop
= get_nop_from_pool (insn
);
5967 gcc_assert (INSN_NOP_P (nop
));
5968 VEC_safe_push (insn_t
, heap
, vec_temp_moveop_nops
, nop
);
5971 sel_remove_insn (insn
, only_disconnect
, false);
5974 /* This function is called when original expr is found.
5975 INSN - current insn traversed, EXPR - the corresponding expr found.
5976 LPARAMS is the local parameters of code modion driver, STATIC_PARAMS
5977 is static parameters of move_op. */
5979 move_op_orig_expr_found (insn_t insn
, expr_t expr
,
5980 cmpd_local_params_p lparams ATTRIBUTE_UNUSED
,
5981 void *static_params
)
5983 bool only_disconnect
, insn_emitted
;
5984 moveop_static_params_p params
= (moveop_static_params_p
) static_params
;
5986 copy_expr_onside (params
->c_expr
, INSN_EXPR (insn
));
5987 track_scheduled_insns_and_blocks (insn
);
5988 insn_emitted
= handle_emitting_transformations (insn
, expr
, params
);
5989 only_disconnect
= (params
->uid
== INSN_UID (insn
)
5990 && ! insn_emitted
&& ! EXPR_WAS_CHANGED (expr
));
5992 /* Mark that we've disconnected an insn. */
5993 if (only_disconnect
)
5995 remove_insn_from_stream (insn
, only_disconnect
);
5998 /* The function is called when original expr is found.
5999 INSN - current insn traversed, EXPR - the corresponding expr found,
6000 crosses_call and original_insns in STATIC_PARAMS are updated. */
6002 fur_orig_expr_found (insn_t insn
, expr_t expr ATTRIBUTE_UNUSED
,
6003 cmpd_local_params_p lparams ATTRIBUTE_UNUSED
,
6004 void *static_params
)
6006 fur_static_params_p params
= (fur_static_params_p
) static_params
;
6010 params
->crosses_call
= true;
6012 def_list_add (params
->original_insns
, insn
, params
->crosses_call
);
6014 /* Mark the registers that do not meet the following condition:
6015 (2) not among the live registers of the point
6016 immediately following the first original operation on
6017 a given downward path, except for the original target
6018 register of the operation. */
6019 tmp
= get_clear_regset_from_pool ();
6020 compute_live_below_insn (insn
, tmp
);
6021 AND_COMPL_REG_SET (tmp
, INSN_REG_SETS (insn
));
6022 AND_COMPL_REG_SET (tmp
, INSN_REG_CLOBBERS (insn
));
6023 IOR_REG_SET (params
->used_regs
, tmp
);
6024 return_regset_to_pool (tmp
);
6026 /* (*1) We need to add to USED_REGS registers that are read by
6027 INSN's lhs. This may lead to choosing wrong src register.
6028 E.g. (scheduling const expr enabled):
6030 429: ax=0x0 <- Can't use AX for this expr (0x0)
6037 /* FIXME: see comment above and enable MEM_P
6038 in vinsn_separable_p. */
6039 gcc_assert (!VINSN_SEPARABLE_P (INSN_VINSN (insn
))
6040 || !MEM_P (INSN_LHS (insn
)));
6043 /* This function is called on the ascending pass, before returning from
6044 current basic block. */
6046 move_op_at_first_insn (insn_t insn
, cmpd_local_params_p lparams
,
6047 void *static_params
)
6049 moveop_static_params_p sparams
= (moveop_static_params_p
) static_params
;
6050 basic_block book_block
= NULL
;
6052 /* When we have removed the boundary insn for scheduling, which also
6053 happened to be the end insn in its bb, we don't need to update sets. */
6054 if (!lparams
->removed_last_insn
6056 && sel_bb_head_p (insn
))
6058 /* We should generate bookkeeping code only if we are not at the
6059 top level of the move_op. */
6060 if (sel_num_cfg_preds_gt_1 (insn
))
6061 book_block
= generate_bookkeeping_insn (sparams
->c_expr
,
6062 lparams
->e1
, lparams
->e2
);
6063 /* Update data sets for the current insn. */
6064 update_data_sets (insn
);
6067 /* If bookkeeping code was inserted, we need to update av sets of basic
6068 block that received bookkeeping. After generation of bookkeeping insn,
6069 bookkeeping block does not contain valid av set because we are not following
6070 the original algorithm in every detail with regards to e.g. renaming
6071 simple reg-reg copies. Consider example:
6073 bookkeeping block scheduling fence
6083 We try to schedule insn "r1 := r3" on the current
6084 scheduling fence. Also, note that av set of bookkeeping block
6085 contain both insns "r1 := r2" and "r1 := r3". When the insn has
6086 been scheduled, the CFG is as follows:
6089 bookkeeping block scheduling fence
6099 Here, insn "r1 := r3" was scheduled at the current scheduling point
6100 and bookkeeping code was generated at the bookeeping block. This
6101 way insn "r1 := r2" is no longer available as a whole instruction
6102 (but only as expr) ahead of insn "r1 := r3" in bookkeeping block.
6103 This situation is handled by calling update_data_sets.
6105 Since update_data_sets is called only on the bookkeeping block, and
6106 it also may have predecessors with av_sets, containing instructions that
6107 are no longer available, we save all such expressions that become
6108 unavailable during data sets update on the bookkeeping block in
6109 VEC_BOOKKEEPING_BLOCKED_VINSNS. Later we avoid selecting such
6110 expressions for scheduling. This allows us to avoid recomputation of
6111 av_sets outside the code motion path. */
6114 update_and_record_unavailable_insns (book_block
);
6116 /* If INSN was previously marked for deletion, it's time to do it. */
6117 if (lparams
->removed_last_insn
)
6118 insn
= PREV_INSN (insn
);
6120 /* Do not tidy control flow at the topmost moveop, as we can erroneously
6121 kill a block with a single nop in which the insn should be emitted. */
6123 tidy_control_flow (BLOCK_FOR_INSN (insn
), true);
6126 /* This function is called on the ascending pass, before returning from the
6127 current basic block. */
6129 fur_at_first_insn (insn_t insn
,
6130 cmpd_local_params_p lparams ATTRIBUTE_UNUSED
,
6131 void *static_params ATTRIBUTE_UNUSED
)
6133 gcc_assert (!sel_bb_head_p (insn
) || AV_SET_VALID_P (insn
)
6134 || AV_LEVEL (insn
) == -1);
6137 /* Called on the backward stage of recursion to call moveup_expr for insn
6138 and sparams->c_expr. */
6140 move_op_ascend (insn_t insn
, void *static_params
)
6142 enum MOVEUP_EXPR_CODE res
;
6143 moveop_static_params_p sparams
= (moveop_static_params_p
) static_params
;
6145 if (! INSN_NOP_P (insn
))
6147 res
= moveup_expr_cached (sparams
->c_expr
, insn
, false);
6148 gcc_assert (res
!= MOVEUP_EXPR_NULL
);
6151 /* Update liveness for this insn as it was invalidated. */
6152 update_liveness_on_insn (insn
);
6155 /* This function is called on enter to the basic block.
6156 Returns TRUE if this block already have been visited and
6157 code_motion_path_driver should return 1, FALSE otherwise. */
6159 fur_on_enter (insn_t insn ATTRIBUTE_UNUSED
, cmpd_local_params_p local_params
,
6160 void *static_params
, bool visited_p
)
6162 fur_static_params_p sparams
= (fur_static_params_p
) static_params
;
6166 /* If we have found something below this block, there should be at
6167 least one insn in ORIGINAL_INSNS. */
6168 gcc_assert (*sparams
->original_insns
);
6170 /* Adjust CROSSES_CALL, since we may have come to this block along
6172 DEF_LIST_DEF (*sparams
->original_insns
)->crosses_call
6173 |= sparams
->crosses_call
;
6176 local_params
->old_original_insns
= *sparams
->original_insns
;
6181 /* Same as above but for move_op. */
6183 move_op_on_enter (insn_t insn ATTRIBUTE_UNUSED
,
6184 cmpd_local_params_p local_params ATTRIBUTE_UNUSED
,
6185 void *static_params ATTRIBUTE_UNUSED
, bool visited_p
)
6192 /* This function is called while descending current basic block if current
6193 insn is not the original EXPR we're searching for.
6195 Return value: FALSE, if code_motion_path_driver should perform a local
6196 cleanup and return 0 itself;
6197 TRUE, if code_motion_path_driver should continue. */
6199 move_op_orig_expr_not_found (insn_t insn
, av_set_t orig_ops ATTRIBUTE_UNUSED
,
6200 void *static_params
)
6202 moveop_static_params_p sparams
= (moveop_static_params_p
) static_params
;
6204 #ifdef ENABLE_CHECKING
6205 sparams
->failed_insn
= insn
;
6208 /* If we're scheduling separate expr, in order to generate correct code
6209 we need to stop the search at bookkeeping code generated with the
6210 same destination register or memory. */
6211 if (lhs_of_insn_equals_to_dest_p (insn
, sparams
->dest
))
6216 /* This function is called while descending current basic block if current
6217 insn is not the original EXPR we're searching for.
6219 Return value: TRUE (code_motion_path_driver should continue). */
6221 fur_orig_expr_not_found (insn_t insn
, av_set_t orig_ops
, void *static_params
)
6225 av_set_iterator avi
;
6226 fur_static_params_p sparams
= (fur_static_params_p
) static_params
;
6229 sparams
->crosses_call
= true;
6230 else if (DEBUG_INSN_P (insn
))
6233 /* If current insn we are looking at cannot be executed together
6234 with original insn, then we can skip it safely.
6236 Example: ORIG_OPS = { (p6) r14 = sign_extend (r15); }
6237 INSN = (!p6) r14 = r14 + 1;
6239 Here we can schedule ORIG_OP with lhs = r14, though only
6240 looking at the set of used and set registers of INSN we must
6241 forbid it. So, add set/used in INSN registers to the
6242 untouchable set only if there is an insn in ORIG_OPS that can
6245 FOR_EACH_EXPR (r
, avi
, orig_ops
)
6246 if (!sched_insns_conditions_mutex_p (insn
, EXPR_INSN_RTX (r
)))
6252 /* Mark all registers that do not meet the following condition:
6253 (1) Not set or read on any path from xi to an instance of the
6254 original operation. */
6257 IOR_REG_SET (sparams
->used_regs
, INSN_REG_SETS (insn
));
6258 IOR_REG_SET (sparams
->used_regs
, INSN_REG_USES (insn
));
6259 IOR_REG_SET (sparams
->used_regs
, INSN_REG_CLOBBERS (insn
));
6265 /* Hooks and data to perform move_op operations with code_motion_path_driver. */
6266 struct code_motion_path_driver_info_def move_op_hooks
= {
6268 move_op_orig_expr_found
,
6269 move_op_orig_expr_not_found
,
6270 move_op_merge_succs
,
6271 move_op_after_merge_succs
,
6273 move_op_at_first_insn
,
6278 /* Hooks and data to perform find_used_regs operations
6279 with code_motion_path_driver. */
6280 struct code_motion_path_driver_info_def fur_hooks
= {
6282 fur_orig_expr_found
,
6283 fur_orig_expr_not_found
,
6285 NULL
, /* fur_after_merge_succs */
6286 NULL
, /* fur_ascend */
6292 /* Traverse all successors of INSN. For each successor that is SUCCS_NORMAL
6293 code_motion_path_driver is called recursively. Original operation
6294 was found at least on one path that is starting with one of INSN's
6295 successors (this fact is asserted). ORIG_OPS is expressions we're looking
6296 for, PATH is the path we've traversed, STATIC_PARAMS is the parameters
6297 of either move_op or find_used_regs depending on the caller.
6299 Return 0 if we haven't found expression, 1 if we found it, -1 if we don't
6300 know for sure at this point. */
6302 code_motion_process_successors (insn_t insn
, av_set_t orig_ops
,
6303 ilist_t path
, void *static_params
)
6306 succ_iterator succ_i
;
6312 struct cmpd_local_params lparams
;
6315 lparams
.c_expr_local
= &_x
;
6316 lparams
.c_expr_merged
= NULL
;
6318 /* We need to process only NORMAL succs for move_op, and collect live
6319 registers from ALL branches (including those leading out of the
6320 region) for find_used_regs.
6322 In move_op, there can be a case when insn's bb number has changed
6323 due to created bookkeeping. This happens very rare, as we need to
6324 move expression from the beginning to the end of the same block.
6325 Rescan successors in this case. */
6328 bb
= BLOCK_FOR_INSN (insn
);
6329 old_index
= bb
->index
;
6330 old_succs
= EDGE_COUNT (bb
->succs
);
6332 FOR_EACH_SUCC_1 (succ
, succ_i
, insn
, code_motion_path_driver_info
->succ_flags
)
6336 lparams
.e1
= succ_i
.e1
;
6337 lparams
.e2
= succ_i
.e2
;
6339 /* Go deep into recursion only for NORMAL edges (non-backedges within the
6341 if (succ_i
.current_flags
== SUCCS_NORMAL
)
6342 b
= code_motion_path_driver (succ
, orig_ops
, path
, &lparams
,
6347 /* Merge c_expres found or unify live register sets from different
6349 code_motion_path_driver_info
->merge_succs (insn
, succ
, b
, &lparams
,
6353 else if (b
== -1 && res
!= 1)
6356 /* We have simplified the control flow below this point. In this case,
6357 the iterator becomes invalid. We need to try again. */
6358 if (BLOCK_FOR_INSN (insn
)->index
!= old_index
6359 || EDGE_COUNT (bb
->succs
) != old_succs
)
6363 #ifdef ENABLE_CHECKING
6364 /* Here, RES==1 if original expr was found at least for one of the
6365 successors. After the loop, RES may happen to have zero value
6366 only if at some point the expr searched is present in av_set, but is
6367 not found below. In most cases, this situation is an error.
6368 The exception is when the original operation is blocked by
6369 bookkeeping generated for another fence or for another path in current
6371 gcc_assert (res
== 1
6373 && av_set_could_be_blocked_by_bookkeeping_p (orig_ops
,
6378 /* Merge data, clean up, etc. */
6379 if (res
!= -1 && code_motion_path_driver_info
->after_merge_succs
)
6380 code_motion_path_driver_info
->after_merge_succs (&lparams
, static_params
);
6386 /* Perform a cleanup when the driver is about to terminate. ORIG_OPS_P
6387 is the pointer to the av set with expressions we were looking for,
6388 PATH_P is the pointer to the traversed path. */
6390 code_motion_path_driver_cleanup (av_set_t
*orig_ops_p
, ilist_t
*path_p
)
6392 ilist_remove (path_p
);
6393 av_set_clear (orig_ops_p
);
6396 /* The driver function that implements move_op or find_used_regs
6397 functionality dependent whether code_motion_path_driver_INFO is set to
6398 &MOVE_OP_HOOKS or &FUR_HOOKS. This function implements the common parts
6399 of code (CFG traversal etc) that are shared among both functions. INSN
6400 is the insn we're starting the search from, ORIG_OPS are the expressions
6401 we're searching for, PATH is traversed path, LOCAL_PARAMS_IN are local
6402 parameters of the driver, and STATIC_PARAMS are static parameters of
6405 Returns whether original instructions were found. Note that top-level
6406 code_motion_path_driver always returns true. */
6408 code_motion_path_driver (insn_t insn
, av_set_t orig_ops
, ilist_t path
,
6409 cmpd_local_params_p local_params_in
,
6410 void *static_params
)
6413 basic_block bb
= BLOCK_FOR_INSN (insn
);
6414 insn_t first_insn
, bb_tail
, before_first
;
6415 bool removed_last_insn
= false;
6417 if (sched_verbose
>= 6)
6419 sel_print ("%s (", code_motion_path_driver_info
->routine_name
);
6422 dump_av_set (orig_ops
);
6426 gcc_assert (orig_ops
);
6428 /* If no original operations exist below this insn, return immediately. */
6429 if (is_ineligible_successor (insn
, path
))
6431 if (sched_verbose
>= 6)
6432 sel_print ("Insn %d is ineligible successor\n", INSN_UID (insn
));
6436 /* The block can have invalid av set, in which case it was created earlier
6437 during move_op. Return immediately. */
6438 if (sel_bb_head_p (insn
))
6440 if (! AV_SET_VALID_P (insn
))
6442 if (sched_verbose
>= 6)
6443 sel_print ("Returned from block %d as it had invalid av set\n",
6448 if (bitmap_bit_p (code_motion_visited_blocks
, bb
->index
))
6450 /* We have already found an original operation on this branch, do not
6451 go any further and just return TRUE here. If we don't stop here,
6452 function can have exponential behaviour even on the small code
6453 with many different paths (e.g. with data speculation and
6454 recovery blocks). */
6455 if (sched_verbose
>= 6)
6456 sel_print ("Block %d already visited in this traversal\n", bb
->index
);
6457 if (code_motion_path_driver_info
->on_enter
)
6458 return code_motion_path_driver_info
->on_enter (insn
,
6465 if (code_motion_path_driver_info
->on_enter
)
6466 code_motion_path_driver_info
->on_enter (insn
, local_params_in
,
6467 static_params
, false);
6468 orig_ops
= av_set_copy (orig_ops
);
6470 /* Filter the orig_ops set. */
6471 if (AV_SET_VALID_P (insn
))
6472 av_set_intersect (&orig_ops
, AV_SET (insn
));
6474 /* If no more original ops, return immediately. */
6477 if (sched_verbose
>= 6)
6478 sel_print ("No intersection with av set of block %d\n", bb
->index
);
6482 /* For non-speculative insns we have to leave only one form of the
6483 original operation, because if we don't, we may end up with
6484 different C_EXPRes and, consequently, with bookkeepings for different
6485 expression forms along the same code motion path. That may lead to
6486 generation of incorrect code. So for each code motion we stick to
6487 the single form of the instruction, except for speculative insns
6488 which we need to keep in different forms with all speculation
6490 av_set_leave_one_nonspec (&orig_ops
);
6492 /* It is not possible that all ORIG_OPS are filtered out. */
6493 gcc_assert (orig_ops
);
6495 /* It is enough to place only heads and tails of visited basic blocks into
6497 ilist_add (&path
, insn
);
6499 bb_tail
= sel_bb_end (bb
);
6501 /* Descend the basic block in search of the original expr; this part
6502 corresponds to the part of the original move_op procedure executed
6503 before the recursive call. */
6506 /* Look at the insn and decide if it could be an ancestor of currently
6507 scheduling operation. If it is so, then the insn "dest = op" could
6508 either be replaced with "dest = reg", because REG now holds the result
6509 of OP, or just removed, if we've scheduled the insn as a whole.
6511 If this insn doesn't contain currently scheduling OP, then proceed
6512 with searching and look at its successors. Operations we're searching
6513 for could have changed when moving up through this insn via
6514 substituting. In this case, perform unsubstitution on them first.
6516 When traversing the DAG below this insn is finished, insert
6517 bookkeeping code, if the insn is a joint point, and remove
6520 expr
= av_set_lookup (orig_ops
, INSN_VINSN (insn
));
6523 insn_t last_insn
= PREV_INSN (insn
);
6525 /* We have found the original operation. */
6526 if (sched_verbose
>= 6)
6527 sel_print ("Found original operation at insn %d\n", INSN_UID (insn
));
6529 code_motion_path_driver_info
->orig_expr_found
6530 (insn
, expr
, local_params_in
, static_params
);
6532 /* Step back, so on the way back we'll start traversing from the
6533 previous insn (or we'll see that it's bb_note and skip that
6535 if (insn
== first_insn
)
6537 first_insn
= NEXT_INSN (last_insn
);
6538 removed_last_insn
= sel_bb_end_p (last_insn
);
6545 /* We haven't found the original expr, continue descending the basic
6547 if (code_motion_path_driver_info
->orig_expr_not_found
6548 (insn
, orig_ops
, static_params
))
6550 /* Av set ops could have been changed when moving through this
6551 insn. To find them below it, we have to un-substitute them. */
6552 undo_transformations (&orig_ops
, insn
);
6556 /* Clean up and return, if the hook tells us to do so. It may
6557 happen if we've encountered the previously created
6559 code_motion_path_driver_cleanup (&orig_ops
, &path
);
6563 gcc_assert (orig_ops
);
6566 /* Stop at insn if we got to the end of BB. */
6567 if (insn
== bb_tail
)
6570 insn
= NEXT_INSN (insn
);
6573 /* Here INSN either points to the insn before the original insn (may be
6574 bb_note, if original insn was a bb_head) or to the bb_end. */
6579 gcc_assert (insn
== sel_bb_end (bb
));
6581 /* Add bb tail to PATH (but it doesn't make any sense if it's a bb_head -
6582 it's already in PATH then). */
6583 if (insn
!= first_insn
)
6584 ilist_add (&path
, insn
);
6586 /* Process_successors should be able to find at least one
6587 successor for which code_motion_path_driver returns TRUE. */
6588 res
= code_motion_process_successors (insn
, orig_ops
,
6589 path
, static_params
);
6591 /* Remove bb tail from path. */
6592 if (insn
!= first_insn
)
6593 ilist_remove (&path
);
6597 /* This is the case when one of the original expr is no longer available
6598 due to bookkeeping created on this branch with the same register.
6599 In the original algorithm, which doesn't have update_data_sets call
6600 on a bookkeeping block, it would simply result in returning
6601 FALSE when we've encountered a previously generated bookkeeping
6602 insn in moveop_orig_expr_not_found. */
6603 code_motion_path_driver_cleanup (&orig_ops
, &path
);
6608 /* Don't need it any more. */
6609 av_set_clear (&orig_ops
);
6611 /* Backward pass: now, when we have C_EXPR computed, we'll drag it to
6612 the beginning of the basic block. */
6613 before_first
= PREV_INSN (first_insn
);
6614 while (insn
!= before_first
)
6616 if (code_motion_path_driver_info
->ascend
)
6617 code_motion_path_driver_info
->ascend (insn
, static_params
);
6619 insn
= PREV_INSN (insn
);
6622 /* Now we're at the bb head. */
6624 ilist_remove (&path
);
6625 local_params_in
->removed_last_insn
= removed_last_insn
;
6626 code_motion_path_driver_info
->at_first_insn (insn
, local_params_in
, static_params
);
6628 /* This should be the very last operation as at bb head we could change
6629 the numbering by creating bookkeeping blocks. */
6630 if (removed_last_insn
)
6631 insn
= PREV_INSN (insn
);
6632 bitmap_set_bit (code_motion_visited_blocks
, BLOCK_FOR_INSN (insn
)->index
);
6636 /* Move up the operations from ORIG_OPS set traversing the dag starting
6637 from INSN. PATH represents the edges traversed so far.
6638 DEST is the register chosen for scheduling the current expr. Insert
6639 bookkeeping code in the join points. EXPR_VLIW is the chosen expression,
6640 C_EXPR is how it looks like at the given cfg point.
6641 Set *SHOULD_MOVE to indicate whether we have only disconnected
6642 one of the insns found.
6644 Returns whether original instructions were found, which is asserted
6645 to be true in the caller. */
6647 move_op (insn_t insn
, av_set_t orig_ops
, expr_t expr_vliw
,
6648 rtx dest
, expr_t c_expr
, bool *should_move
)
6650 struct moveop_static_params sparams
;
6651 struct cmpd_local_params lparams
;
6654 /* Init params for code_motion_path_driver. */
6655 sparams
.dest
= dest
;
6656 sparams
.c_expr
= c_expr
;
6657 sparams
.uid
= INSN_UID (EXPR_INSN_RTX (expr_vliw
));
6658 #ifdef ENABLE_CHECKING
6659 sparams
.failed_insn
= NULL
;
6661 sparams
.was_renamed
= false;
6664 /* We haven't visited any blocks yet. */
6665 bitmap_clear (code_motion_visited_blocks
);
6667 /* Set appropriate hooks and data. */
6668 code_motion_path_driver_info
= &move_op_hooks
;
6669 res
= code_motion_path_driver (insn
, orig_ops
, NULL
, &lparams
, &sparams
);
6671 if (sparams
.was_renamed
)
6672 EXPR_WAS_RENAMED (expr_vliw
) = true;
6674 *should_move
= (sparams
.uid
== -1);
6680 /* Functions that work with regions. */
6682 /* Current number of seqno used in init_seqno and init_seqno_1. */
6683 static int cur_seqno
;
6685 /* A helper for init_seqno. Traverse the region starting from BB and
6686 compute seqnos for visited insns, marking visited bbs in VISITED_BBS.
6687 Clear visited blocks from BLOCKS_TO_RESCHEDULE. */
6689 init_seqno_1 (basic_block bb
, sbitmap visited_bbs
, bitmap blocks_to_reschedule
)
6691 int bbi
= BLOCK_TO_BB (bb
->index
);
6692 insn_t insn
, note
= bb_note (bb
);
6696 SET_BIT (visited_bbs
, bbi
);
6697 if (blocks_to_reschedule
)
6698 bitmap_clear_bit (blocks_to_reschedule
, bb
->index
);
6700 FOR_EACH_SUCC_1 (succ_insn
, si
, BB_END (bb
),
6701 SUCCS_NORMAL
| SUCCS_SKIP_TO_LOOP_EXITS
)
6703 basic_block succ
= BLOCK_FOR_INSN (succ_insn
);
6704 int succ_bbi
= BLOCK_TO_BB (succ
->index
);
6706 gcc_assert (in_current_region_p (succ
));
6708 if (!TEST_BIT (visited_bbs
, succ_bbi
))
6710 gcc_assert (succ_bbi
> bbi
);
6712 init_seqno_1 (succ
, visited_bbs
, blocks_to_reschedule
);
6716 for (insn
= BB_END (bb
); insn
!= note
; insn
= PREV_INSN (insn
))
6717 INSN_SEQNO (insn
) = cur_seqno
--;
6720 /* Initialize seqnos for the current region. NUMBER_OF_INSNS is the number
6721 of instructions in the region, BLOCKS_TO_RESCHEDULE contains blocks on
6722 which we're rescheduling when pipelining, FROM is the block where
6723 traversing region begins (it may not be the head of the region when
6724 pipelining, but the head of the loop instead).
6726 Returns the maximal seqno found. */
6728 init_seqno (int number_of_insns
, bitmap blocks_to_reschedule
, basic_block from
)
6730 sbitmap visited_bbs
;
6734 visited_bbs
= sbitmap_alloc (current_nr_blocks
);
6736 if (blocks_to_reschedule
)
6738 sbitmap_ones (visited_bbs
);
6739 EXECUTE_IF_SET_IN_BITMAP (blocks_to_reschedule
, 0, bbi
, bi
)
6741 gcc_assert (BLOCK_TO_BB (bbi
) < current_nr_blocks
);
6742 RESET_BIT (visited_bbs
, BLOCK_TO_BB (bbi
));
6747 sbitmap_zero (visited_bbs
);
6748 from
= EBB_FIRST_BB (0);
6751 cur_seqno
= number_of_insns
> 0 ? number_of_insns
: sched_max_luid
- 1;
6752 init_seqno_1 (from
, visited_bbs
, blocks_to_reschedule
);
6753 gcc_assert (cur_seqno
== 0 || number_of_insns
== 0);
6755 sbitmap_free (visited_bbs
);
6756 return sched_max_luid
- 1;
6759 /* Initialize scheduling parameters for current region. */
6761 sel_setup_region_sched_flags (void)
6763 enable_schedule_as_rhs_p
= 1;
6765 pipelining_p
= (bookkeeping_p
6766 && (flag_sel_sched_pipelining
!= 0)
6767 && current_loop_nest
!= NULL
);
6768 max_insns_to_rename
= PARAM_VALUE (PARAM_SELSCHED_INSNS_TO_RENAME
);
6772 /* Return true if all basic blocks of current region are empty. */
6774 current_region_empty_p (void)
6777 for (i
= 0; i
< current_nr_blocks
; i
++)
6778 if (! sel_bb_empty_p (BASIC_BLOCK (BB_TO_BLOCK (i
))))
6784 /* Prepare and verify loop nest for pipelining. */
6786 setup_current_loop_nest (int rgn
)
6788 current_loop_nest
= get_loop_nest_for_rgn (rgn
);
6790 if (!current_loop_nest
)
6793 /* If this loop has any saved loop preheaders from nested loops,
6794 add these basic blocks to the current region. */
6795 sel_add_loop_preheaders ();
6797 /* Check that we're starting with a valid information. */
6798 gcc_assert (loop_latch_edge (current_loop_nest
));
6799 gcc_assert (LOOP_MARKED_FOR_PIPELINING_P (current_loop_nest
));
6802 /* Compute instruction priorities for current region. */
6804 sel_compute_priorities (int rgn
)
6806 sched_rgn_compute_dependencies (rgn
);
6808 /* Compute insn priorities in haifa style. Then free haifa style
6809 dependencies that we've calculated for this. */
6810 compute_priorities ();
6812 if (sched_verbose
>= 5)
6813 debug_rgn_dependencies (0);
6818 /* Init scheduling data for RGN. Returns true when this region should not
6821 sel_region_init (int rgn
)
6826 rgn_setup_region (rgn
);
6828 /* Even if sched_is_disabled_for_current_region_p() is true, we still
6829 do region initialization here so the region can be bundled correctly,
6830 but we'll skip the scheduling in sel_sched_region (). */
6831 if (current_region_empty_p ())
6834 if (flag_sel_sched_pipelining
)
6835 setup_current_loop_nest (rgn
);
6837 sel_setup_region_sched_flags ();
6839 bbs
= VEC_alloc (basic_block
, heap
, current_nr_blocks
);
6841 for (i
= 0; i
< current_nr_blocks
; i
++)
6842 VEC_quick_push (basic_block
, bbs
, BASIC_BLOCK (BB_TO_BLOCK (i
)));
6844 sel_init_bbs (bbs
, NULL
);
6846 /* Initialize luids and dependence analysis which both sel-sched and haifa
6848 sched_init_luids (bbs
, NULL
, NULL
, NULL
);
6849 sched_deps_init (false);
6851 /* Initialize haifa data. */
6852 rgn_setup_sched_infos ();
6853 sel_set_sched_flags ();
6854 haifa_init_h_i_d (bbs
, NULL
, NULL
, NULL
);
6856 sel_compute_priorities (rgn
);
6857 init_deps_global ();
6859 /* Main initialization. */
6860 sel_setup_sched_infos ();
6861 sel_init_global_and_expr (bbs
);
6863 VEC_free (basic_block
, heap
, bbs
);
6865 blocks_to_reschedule
= BITMAP_ALLOC (NULL
);
6867 /* Init correct liveness sets on each instruction of a single-block loop.
6868 This is the only situation when we can't update liveness when calling
6869 compute_live for the first insn of the loop. */
6870 if (current_loop_nest
)
6872 int header
= (sel_is_loop_preheader_p (BASIC_BLOCK (BB_TO_BLOCK (0)))
6876 if (current_nr_blocks
== header
+ 1)
6877 update_liveness_on_insn
6878 (sel_bb_head (BASIC_BLOCK (BB_TO_BLOCK (header
))));
6881 /* Set hooks so that no newly generated insn will go out unnoticed. */
6882 sel_register_cfg_hooks ();
6884 /* !!! We call target.sched.init () for the whole region, but we invoke
6885 targetm.sched.finish () for every ebb. */
6886 if (targetm
.sched
.init
)
6887 /* None of the arguments are actually used in any target. */
6888 targetm
.sched
.init (sched_dump
, sched_verbose
, -1);
6890 first_emitted_uid
= get_max_uid () + 1;
6891 preheader_removed
= false;
6893 /* Reset register allocation ticks array. */
6894 memset (reg_rename_tick
, 0, sizeof reg_rename_tick
);
6895 reg_rename_this_tick
= 0;
6897 bitmap_initialize (forced_ebb_heads
, 0);
6898 bitmap_clear (forced_ebb_heads
);
6901 current_copies
= BITMAP_ALLOC (NULL
);
6902 current_originators
= BITMAP_ALLOC (NULL
);
6903 code_motion_visited_blocks
= BITMAP_ALLOC (NULL
);
6908 /* Simplify insns after the scheduling. */
6910 simplify_changed_insns (void)
6914 for (i
= 0; i
< current_nr_blocks
; i
++)
6916 basic_block bb
= BASIC_BLOCK (BB_TO_BLOCK (i
));
6919 FOR_BB_INSNS (bb
, insn
)
6922 expr_t expr
= INSN_EXPR (insn
);
6924 if (EXPR_WAS_SUBSTITUTED (expr
))
6925 validate_simplify_insn (insn
);
6930 /* Find boundaries of the EBB starting from basic block BB, marking blocks of
6931 this EBB in SCHEDULED_BLOCKS and appropriately filling in HEAD, TAIL,
6932 PREV_HEAD, and NEXT_TAIL fields of CURRENT_SCHED_INFO structure. */
6934 find_ebb_boundaries (basic_block bb
, bitmap scheduled_blocks
)
6937 basic_block bb1
= bb
;
6938 if (sched_verbose
>= 2)
6939 sel_print ("Finishing schedule in bbs: ");
6943 bitmap_set_bit (scheduled_blocks
, BLOCK_TO_BB (bb1
->index
));
6945 if (sched_verbose
>= 2)
6946 sel_print ("%d; ", bb1
->index
);
6948 while (!bb_ends_ebb_p (bb1
) && (bb1
= bb_next_bb (bb1
)));
6950 if (sched_verbose
>= 2)
6953 get_ebb_head_tail (bb
, bb1
, &head
, &tail
);
6955 current_sched_info
->head
= head
;
6956 current_sched_info
->tail
= tail
;
6957 current_sched_info
->prev_head
= PREV_INSN (head
);
6958 current_sched_info
->next_tail
= NEXT_INSN (tail
);
6961 /* Regenerate INSN_SCHED_CYCLEs for insns of current EBB. */
6963 reset_sched_cycles_in_current_ebb (void)
6966 int haifa_last_clock
= -1;
6967 int haifa_clock
= 0;
6970 if (targetm
.sched
.init
)
6972 /* None of the arguments are actually used in any target.
6973 NB: We should have md_reset () hook for cases like this. */
6974 targetm
.sched
.init (sched_dump
, sched_verbose
, -1);
6977 state_reset (curr_state
);
6978 advance_state (curr_state
);
6980 for (insn
= current_sched_info
->head
;
6981 insn
!= current_sched_info
->next_tail
;
6982 insn
= NEXT_INSN (insn
))
6984 int cost
, haifa_cost
;
6986 bool asm_p
, real_insn
, after_stall
;
6993 real_insn
= recog_memoized (insn
) >= 0;
6994 clock
= INSN_SCHED_CYCLE (insn
);
6996 cost
= clock
- last_clock
;
6998 /* Initialize HAIFA_COST. */
7001 asm_p
= INSN_ASM_P (insn
);
7004 /* This is asm insn which *had* to be scheduled first
7008 /* This is a use/clobber insn. It should not change
7013 haifa_cost
= estimate_insn_cost (insn
, curr_state
);
7015 /* Stall for whatever cycles we've stalled before. */
7017 if (INSN_AFTER_STALL_P (insn
) && cost
> haifa_cost
)
7027 while (haifa_cost
--)
7029 advance_state (curr_state
);
7032 if (sched_verbose
>= 2)
7034 sel_print ("advance_state (state_transition)\n");
7035 debug_state (curr_state
);
7038 /* The DFA may report that e.g. insn requires 2 cycles to be
7039 issued, but on the next cycle it says that insn is ready
7040 to go. Check this here. */
7044 && estimate_insn_cost (insn
, curr_state
) == 0)
7051 gcc_assert (haifa_cost
== 0);
7053 if (sched_verbose
>= 2)
7054 sel_print ("Haifa cost for insn %d: %d\n", INSN_UID (insn
), haifa_cost
);
7056 if (targetm
.sched
.dfa_new_cycle
)
7057 while (targetm
.sched
.dfa_new_cycle (sched_dump
, sched_verbose
, insn
,
7058 haifa_last_clock
, haifa_clock
,
7061 advance_state (curr_state
);
7063 if (sched_verbose
>= 2)
7065 sel_print ("advance_state (dfa_new_cycle)\n");
7066 debug_state (curr_state
);
7072 cost
= state_transition (curr_state
, insn
);
7074 if (sched_verbose
>= 2)
7075 debug_state (curr_state
);
7077 gcc_assert (cost
< 0);
7080 if (targetm
.sched
.variable_issue
)
7081 targetm
.sched
.variable_issue (sched_dump
, sched_verbose
, insn
, 0);
7083 INSN_SCHED_CYCLE (insn
) = haifa_clock
;
7086 haifa_last_clock
= haifa_clock
;
7090 /* Put TImode markers on insns starting a new issue group. */
7094 int last_clock
= -1;
7097 for (insn
= current_sched_info
->head
; insn
!= current_sched_info
->next_tail
;
7098 insn
= NEXT_INSN (insn
))
7105 clock
= INSN_SCHED_CYCLE (insn
);
7106 cost
= (last_clock
== -1) ? 1 : clock
- last_clock
;
7108 gcc_assert (cost
>= 0);
7111 && GET_CODE (PATTERN (insn
)) != USE
7112 && GET_CODE (PATTERN (insn
)) != CLOBBER
)
7114 if (reload_completed
&& cost
> 0)
7115 PUT_MODE (insn
, TImode
);
7120 if (sched_verbose
>= 2)
7121 sel_print ("Cost for insn %d is %d\n", INSN_UID (insn
), cost
);
7125 /* Perform MD_FINISH on EBBs comprising current region. When
7126 RESET_SCHED_CYCLES_P is true, run a pass emulating the scheduler
7127 to produce correct sched cycles on insns. */
7129 sel_region_target_finish (bool reset_sched_cycles_p
)
7132 bitmap scheduled_blocks
= BITMAP_ALLOC (NULL
);
7134 for (i
= 0; i
< current_nr_blocks
; i
++)
7136 if (bitmap_bit_p (scheduled_blocks
, i
))
7139 /* While pipelining outer loops, skip bundling for loop
7140 preheaders. Those will be rescheduled in the outer loop. */
7141 if (sel_is_loop_preheader_p (EBB_FIRST_BB (i
)))
7144 find_ebb_boundaries (EBB_FIRST_BB (i
), scheduled_blocks
);
7146 if (no_real_insns_p (current_sched_info
->head
, current_sched_info
->tail
))
7149 if (reset_sched_cycles_p
)
7150 reset_sched_cycles_in_current_ebb ();
7152 if (targetm
.sched
.init
)
7153 targetm
.sched
.init (sched_dump
, sched_verbose
, -1);
7157 if (targetm
.sched
.finish
)
7159 targetm
.sched
.finish (sched_dump
, sched_verbose
);
7161 /* Extend luids so that insns generated by the target will
7163 sched_init_luids (NULL
, NULL
, NULL
, NULL
);
7167 BITMAP_FREE (scheduled_blocks
);
7170 /* Free the scheduling data for the current region. When RESET_SCHED_CYCLES_P
7171 is true, make an additional pass emulating scheduler to get correct insn
7172 cycles for md_finish calls. */
7174 sel_region_finish (bool reset_sched_cycles_p
)
7176 simplify_changed_insns ();
7177 sched_finish_ready_list ();
7180 /* Free the vectors. */
7182 VEC_free (expr_t
, heap
, vec_av_set
);
7183 BITMAP_FREE (current_copies
);
7184 BITMAP_FREE (current_originators
);
7185 BITMAP_FREE (code_motion_visited_blocks
);
7186 vinsn_vec_free (&vec_bookkeeping_blocked_vinsns
);
7187 vinsn_vec_free (&vec_target_unavailable_vinsns
);
7189 /* If LV_SET of the region head should be updated, do it now because
7190 there will be no other chance. */
7195 FOR_EACH_SUCC_1 (insn
, si
, bb_note (EBB_FIRST_BB (0)),
7196 SUCCS_NORMAL
| SUCCS_SKIP_TO_LOOP_EXITS
)
7198 basic_block bb
= BLOCK_FOR_INSN (insn
);
7200 if (!BB_LV_SET_VALID_P (bb
))
7201 compute_live (insn
);
7205 /* Emulate the Haifa scheduler for bundling. */
7206 if (reload_completed
)
7207 sel_region_target_finish (reset_sched_cycles_p
);
7209 sel_finish_global_and_expr ();
7211 bitmap_clear (forced_ebb_heads
);
7215 finish_deps_global ();
7216 sched_finish_luids ();
7219 BITMAP_FREE (blocks_to_reschedule
);
7221 sel_unregister_cfg_hooks ();
7227 /* Functions that implement the scheduler driver. */
7229 /* Schedule a parallel instruction group on each of FENCES. MAX_SEQNO
7230 is the current maximum seqno. SCHEDULED_INSNS_TAILPP is the list
7231 of insns scheduled -- these would be postprocessed later. */
7233 schedule_on_fences (flist_t fences
, int max_seqno
,
7234 ilist_t
**scheduled_insns_tailpp
)
7236 flist_t old_fences
= fences
;
7238 if (sched_verbose
>= 1)
7240 sel_print ("\nScheduling on fences: ");
7241 dump_flist (fences
);
7245 scheduled_something_on_previous_fence
= false;
7246 for (; fences
; fences
= FLIST_NEXT (fences
))
7248 fence_t fence
= NULL
;
7251 bool first_p
= true;
7253 /* Choose the next fence group to schedule.
7254 The fact that insn can be scheduled only once
7255 on the cycle is guaranteed by two properties:
7256 1. seqnos of parallel groups decrease with each iteration.
7257 2. If is_ineligible_successor () sees the larger seqno, it
7258 checks if candidate insn is_in_current_fence_p (). */
7259 for (fences2
= old_fences
; fences2
; fences2
= FLIST_NEXT (fences2
))
7261 fence_t f
= FLIST_FENCE (fences2
);
7263 if (!FENCE_PROCESSED_P (f
))
7265 int i
= INSN_SEQNO (FENCE_INSN (f
));
7267 if (first_p
|| i
> seqno
)
7274 /* ??? Seqnos of different groups should be different. */
7275 gcc_assert (1 || i
!= seqno
);
7281 /* As FENCE is nonnull, SEQNO is initialized. */
7282 seqno
-= max_seqno
+ 1;
7283 fill_insns (fence
, seqno
, scheduled_insns_tailpp
);
7284 FENCE_PROCESSED_P (fence
) = true;
7287 /* All av_sets are invalidated by GLOBAL_LEVEL increase, thus we
7288 don't need to keep bookkeeping-invalidated and target-unavailable
7290 vinsn_vec_clear (&vec_bookkeeping_blocked_vinsns
);
7291 vinsn_vec_clear (&vec_target_unavailable_vinsns
);
7294 /* Calculate MIN_SEQNO and MAX_SEQNO. */
7296 find_min_max_seqno (flist_t fences
, int *min_seqno
, int *max_seqno
)
7298 *min_seqno
= *max_seqno
= INSN_SEQNO (FENCE_INSN (FLIST_FENCE (fences
)));
7300 /* The first element is already processed. */
7301 while ((fences
= FLIST_NEXT (fences
)))
7303 int seqno
= INSN_SEQNO (FENCE_INSN (FLIST_FENCE (fences
)));
7305 if (*min_seqno
> seqno
)
7307 else if (*max_seqno
< seqno
)
7312 /* Calculate new fences from FENCES. */
7314 calculate_new_fences (flist_t fences
, int orig_max_seqno
)
7316 flist_t old_fences
= fences
;
7317 struct flist_tail_def _new_fences
, *new_fences
= &_new_fences
;
7319 flist_tail_init (new_fences
);
7320 for (; fences
; fences
= FLIST_NEXT (fences
))
7322 fence_t fence
= FLIST_FENCE (fences
);
7325 if (!FENCE_BNDS (fence
))
7327 /* This fence doesn't have any successors. */
7328 if (!FENCE_SCHEDULED_P (fence
))
7330 /* Nothing was scheduled on this fence. */
7333 insn
= FENCE_INSN (fence
);
7334 seqno
= INSN_SEQNO (insn
);
7335 gcc_assert (seqno
> 0 && seqno
<= orig_max_seqno
);
7337 if (sched_verbose
>= 1)
7338 sel_print ("Fence %d[%d] has not changed\n",
7341 move_fence_to_fences (fences
, new_fences
);
7345 extract_new_fences_from (fences
, new_fences
, orig_max_seqno
);
7348 flist_clear (&old_fences
);
7349 return FLIST_TAIL_HEAD (new_fences
);
7352 /* Update seqnos of insns given by PSCHEDULED_INSNS. MIN_SEQNO and MAX_SEQNO
7353 are the miminum and maximum seqnos of the group, HIGHEST_SEQNO_IN_USE is
7354 the highest seqno used in a region. Return the updated highest seqno. */
7356 update_seqnos_and_stage (int min_seqno
, int max_seqno
,
7357 int highest_seqno_in_use
,
7358 ilist_t
*pscheduled_insns
)
7364 /* Actually, new_hs is the seqno of the instruction, that was
7365 scheduled first (i.e. it is the first one in SCHEDULED_INSNS). */
7366 if (*pscheduled_insns
)
7368 new_hs
= (INSN_SEQNO (ILIST_INSN (*pscheduled_insns
))
7369 + highest_seqno_in_use
+ max_seqno
- min_seqno
+ 2);
7370 gcc_assert (new_hs
> highest_seqno_in_use
);
7373 new_hs
= highest_seqno_in_use
;
7375 FOR_EACH_INSN (insn
, ii
, *pscheduled_insns
)
7377 gcc_assert (INSN_SEQNO (insn
) < 0);
7378 INSN_SEQNO (insn
) += highest_seqno_in_use
+ max_seqno
- min_seqno
+ 2;
7379 gcc_assert (INSN_SEQNO (insn
) <= new_hs
);
7381 /* When not pipelining, purge unneeded insn info on the scheduled insns.
7382 For example, having reg_last array of INSN_DEPS_CONTEXT in memory may
7383 require > 1GB of memory e.g. on limit-fnargs.c. */
7385 free_data_for_scheduled_insn (insn
);
7388 ilist_clear (pscheduled_insns
);
7394 /* The main driver for scheduling a region. This function is responsible
7395 for correct propagation of fences (i.e. scheduling points) and creating
7396 a group of parallel insns at each of them. It also supports
7397 pipelining. ORIG_MAX_SEQNO is the maximal seqno before this pass
7400 sel_sched_region_2 (int orig_max_seqno
)
7402 int highest_seqno_in_use
= orig_max_seqno
;
7404 stat_bookkeeping_copies
= 0;
7405 stat_insns_needed_bookkeeping
= 0;
7406 stat_renamed_scheduled
= 0;
7407 stat_substitutions_total
= 0;
7408 num_insns_scheduled
= 0;
7412 int min_seqno
, max_seqno
;
7413 ilist_t scheduled_insns
= NULL
;
7414 ilist_t
*scheduled_insns_tailp
= &scheduled_insns
;
7416 find_min_max_seqno (fences
, &min_seqno
, &max_seqno
);
7417 schedule_on_fences (fences
, max_seqno
, &scheduled_insns_tailp
);
7418 fences
= calculate_new_fences (fences
, orig_max_seqno
);
7419 highest_seqno_in_use
= update_seqnos_and_stage (min_seqno
, max_seqno
,
7420 highest_seqno_in_use
,
7424 if (sched_verbose
>= 1)
7425 sel_print ("Scheduled %d bookkeeping copies, %d insns needed "
7426 "bookkeeping, %d insns renamed, %d insns substituted\n",
7427 stat_bookkeeping_copies
,
7428 stat_insns_needed_bookkeeping
,
7429 stat_renamed_scheduled
,
7430 stat_substitutions_total
);
7433 /* Schedule a region. When pipelining, search for possibly never scheduled
7434 bookkeeping code and schedule it. Reschedule pipelined code without
7435 pipelining after. */
7437 sel_sched_region_1 (void)
7439 int number_of_insns
;
7442 /* Remove empty blocks that might be in the region from the beginning.
7443 We need to do save sched_max_luid before that, as it actually shows
7444 the number of insns in the region, and purge_empty_blocks can
7446 number_of_insns
= sched_max_luid
- 1;
7447 purge_empty_blocks ();
7449 orig_max_seqno
= init_seqno (number_of_insns
, NULL
, NULL
);
7450 gcc_assert (orig_max_seqno
>= 1);
7452 /* When pipelining outer loops, create fences on the loop header,
7455 if (current_loop_nest
)
7456 init_fences (BB_END (EBB_FIRST_BB (0)));
7458 init_fences (bb_note (EBB_FIRST_BB (0)));
7461 sel_sched_region_2 (orig_max_seqno
);
7463 gcc_assert (fences
== NULL
);
7469 struct flist_tail_def _new_fences
;
7470 flist_tail_t new_fences
= &_new_fences
;
7473 pipelining_p
= false;
7474 max_ws
= MIN (max_ws
, issue_rate
* 3 / 2);
7475 bookkeeping_p
= false;
7476 enable_schedule_as_rhs_p
= false;
7478 /* Schedule newly created code, that has not been scheduled yet. */
7485 for (i
= 0; i
< current_nr_blocks
; i
++)
7487 basic_block bb
= EBB_FIRST_BB (i
);
7489 if (sel_bb_empty_p (bb
))
7491 bitmap_clear_bit (blocks_to_reschedule
, bb
->index
);
7495 if (bitmap_bit_p (blocks_to_reschedule
, bb
->index
))
7497 clear_outdated_rtx_info (bb
);
7498 if (sel_insn_is_speculation_check (BB_END (bb
))
7499 && JUMP_P (BB_END (bb
)))
7500 bitmap_set_bit (blocks_to_reschedule
,
7501 BRANCH_EDGE (bb
)->dest
->index
);
7503 else if (INSN_SCHED_TIMES (sel_bb_head (bb
)) <= 0)
7504 bitmap_set_bit (blocks_to_reschedule
, bb
->index
);
7507 for (i
= 0; i
< current_nr_blocks
; i
++)
7509 bb
= EBB_FIRST_BB (i
);
7511 /* While pipelining outer loops, skip bundling for loop
7512 preheaders. Those will be rescheduled in the outer
7514 if (sel_is_loop_preheader_p (bb
))
7516 clear_outdated_rtx_info (bb
);
7520 if (bitmap_clear_bit (blocks_to_reschedule
, bb
->index
))
7522 flist_tail_init (new_fences
);
7524 orig_max_seqno
= init_seqno (0, blocks_to_reschedule
, bb
);
7526 /* Mark BB as head of the new ebb. */
7527 bitmap_set_bit (forced_ebb_heads
, bb
->index
);
7529 gcc_assert (fences
== NULL
);
7531 init_fences (bb_note (bb
));
7533 sel_sched_region_2 (orig_max_seqno
);
7543 /* Schedule the RGN region. */
7545 sel_sched_region (int rgn
)
7548 bool reset_sched_cycles_p
;
7550 if (sel_region_init (rgn
))
7553 if (sched_verbose
>= 1)
7554 sel_print ("Scheduling region %d\n", rgn
);
7556 schedule_p
= (!sched_is_disabled_for_current_region_p ()
7557 && dbg_cnt (sel_sched_region_cnt
));
7558 reset_sched_cycles_p
= pipelining_p
;
7560 sel_sched_region_1 ();
7562 /* Force initialization of INSN_SCHED_CYCLEs for correct bundling. */
7563 reset_sched_cycles_p
= true;
7565 sel_region_finish (reset_sched_cycles_p
);
7568 /* Perform global init for the scheduler. */
7570 sel_global_init (void)
7572 calculate_dominance_info (CDI_DOMINATORS
);
7573 alloc_sched_pools ();
7575 /* Setup the infos for sched_init. */
7576 sel_setup_sched_infos ();
7577 setup_sched_dump ();
7579 sched_rgn_init (false);
7583 /* Reset AFTER_RECOVERY if it has been set by the 1st scheduler pass. */
7585 can_issue_more
= issue_rate
;
7587 sched_extend_target ();
7588 sched_deps_init (true);
7589 setup_nop_and_exit_insns ();
7590 sel_extend_global_bb_info ();
7592 init_hard_regs_data ();
7595 /* Free the global data of the scheduler. */
7597 sel_global_finish (void)
7599 free_bb_note_pool ();
7601 sel_finish_global_bb_info ();
7603 free_regset_pool ();
7604 free_nop_and_exit_insns ();
7606 sched_rgn_finish ();
7607 sched_deps_finish ();
7611 sel_finish_pipelining ();
7613 free_sched_pools ();
7614 free_dominance_info (CDI_DOMINATORS
);
7617 /* Return true when we need to skip selective scheduling. Used for debugging. */
7619 maybe_skip_selective_scheduling (void)
7621 return ! dbg_cnt (sel_sched_cnt
);
7624 /* The entry point. */
7626 run_selective_scheduling (void)
7630 if (n_basic_blocks
== NUM_FIXED_BLOCKS
)
7635 for (rgn
= 0; rgn
< nr_regions
; rgn
++)
7636 sel_sched_region (rgn
);
7638 sel_global_finish ();