1 /* RTL simplification functions for GNU compiler.
2 Copyright (C) 1987-2020 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify it under
7 the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 3, or (at your option) any later
11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
23 #include "coretypes.h"
33 #include "diagnostic-core.h"
37 #include "selftest-rtl.h"
38 #include "rtx-vector-builder.h"
40 /* Simplification and canonicalization of RTL. */
42 /* Much code operates on (low, high) pairs; the low value is an
43 unsigned wide int, the high value a signed wide int. We
44 occasionally need to sign extend from low to high as if low were a
46 #define HWI_SIGN_EXTEND(low) \
47 ((((HOST_WIDE_INT) low) < 0) ? HOST_WIDE_INT_M1 : HOST_WIDE_INT_0)
49 static bool plus_minus_operand_p (const_rtx
);
50 static rtx
simplify_plus_minus (enum rtx_code
, machine_mode
, rtx
, rtx
);
51 static rtx
simplify_associative_operation (enum rtx_code
, machine_mode
,
53 static rtx
simplify_relational_operation_1 (enum rtx_code
, machine_mode
,
54 machine_mode
, rtx
, rtx
);
55 static rtx
simplify_unary_operation_1 (enum rtx_code
, machine_mode
, rtx
);
56 static rtx
simplify_binary_operation_1 (enum rtx_code
, machine_mode
,
59 /* Negate I, which satisfies poly_int_rtx_p. MODE is the mode of I. */
62 neg_poly_int_rtx (machine_mode mode
, const_rtx i
)
64 return immed_wide_int_const (-wi::to_poly_wide (i
, mode
), mode
);
67 /* Test whether expression, X, is an immediate constant that represents
68 the most significant bit of machine mode MODE. */
71 mode_signbit_p (machine_mode mode
, const_rtx x
)
73 unsigned HOST_WIDE_INT val
;
75 scalar_int_mode int_mode
;
77 if (!is_int_mode (mode
, &int_mode
))
80 width
= GET_MODE_PRECISION (int_mode
);
84 if (width
<= HOST_BITS_PER_WIDE_INT
87 #if TARGET_SUPPORTS_WIDE_INT
88 else if (CONST_WIDE_INT_P (x
))
91 unsigned int elts
= CONST_WIDE_INT_NUNITS (x
);
92 if (elts
!= (width
+ HOST_BITS_PER_WIDE_INT
- 1) / HOST_BITS_PER_WIDE_INT
)
94 for (i
= 0; i
< elts
- 1; i
++)
95 if (CONST_WIDE_INT_ELT (x
, i
) != 0)
97 val
= CONST_WIDE_INT_ELT (x
, elts
- 1);
98 width
%= HOST_BITS_PER_WIDE_INT
;
100 width
= HOST_BITS_PER_WIDE_INT
;
103 else if (width
<= HOST_BITS_PER_DOUBLE_INT
104 && CONST_DOUBLE_AS_INT_P (x
)
105 && CONST_DOUBLE_LOW (x
) == 0)
107 val
= CONST_DOUBLE_HIGH (x
);
108 width
-= HOST_BITS_PER_WIDE_INT
;
112 /* X is not an integer constant. */
115 if (width
< HOST_BITS_PER_WIDE_INT
)
116 val
&= (HOST_WIDE_INT_1U
<< width
) - 1;
117 return val
== (HOST_WIDE_INT_1U
<< (width
- 1));
120 /* Test whether VAL is equal to the most significant bit of mode MODE
121 (after masking with the mode mask of MODE). Returns false if the
122 precision of MODE is too large to handle. */
125 val_signbit_p (machine_mode mode
, unsigned HOST_WIDE_INT val
)
128 scalar_int_mode int_mode
;
130 if (!is_int_mode (mode
, &int_mode
))
133 width
= GET_MODE_PRECISION (int_mode
);
134 if (width
== 0 || width
> HOST_BITS_PER_WIDE_INT
)
137 val
&= GET_MODE_MASK (int_mode
);
138 return val
== (HOST_WIDE_INT_1U
<< (width
- 1));
141 /* Test whether the most significant bit of mode MODE is set in VAL.
142 Returns false if the precision of MODE is too large to handle. */
144 val_signbit_known_set_p (machine_mode mode
, unsigned HOST_WIDE_INT val
)
148 scalar_int_mode int_mode
;
149 if (!is_int_mode (mode
, &int_mode
))
152 width
= GET_MODE_PRECISION (int_mode
);
153 if (width
== 0 || width
> HOST_BITS_PER_WIDE_INT
)
156 val
&= HOST_WIDE_INT_1U
<< (width
- 1);
160 /* Test whether the most significant bit of mode MODE is clear in VAL.
161 Returns false if the precision of MODE is too large to handle. */
163 val_signbit_known_clear_p (machine_mode mode
, unsigned HOST_WIDE_INT val
)
167 scalar_int_mode int_mode
;
168 if (!is_int_mode (mode
, &int_mode
))
171 width
= GET_MODE_PRECISION (int_mode
);
172 if (width
== 0 || width
> HOST_BITS_PER_WIDE_INT
)
175 val
&= HOST_WIDE_INT_1U
<< (width
- 1);
179 /* Make a binary operation by properly ordering the operands and
180 seeing if the expression folds. */
183 simplify_gen_binary (enum rtx_code code
, machine_mode mode
, rtx op0
,
188 /* If this simplifies, do it. */
189 tem
= simplify_binary_operation (code
, mode
, op0
, op1
);
193 /* Put complex operands first and constants second if commutative. */
194 if (GET_RTX_CLASS (code
) == RTX_COMM_ARITH
195 && swap_commutative_operands_p (op0
, op1
))
196 std::swap (op0
, op1
);
198 return gen_rtx_fmt_ee (code
, mode
, op0
, op1
);
201 /* If X is a MEM referencing the constant pool, return the real value.
202 Otherwise return X. */
204 avoid_constant_pool_reference (rtx x
)
208 poly_int64 offset
= 0;
210 switch (GET_CODE (x
))
216 /* Handle float extensions of constant pool references. */
218 c
= avoid_constant_pool_reference (tmp
);
219 if (c
!= tmp
&& CONST_DOUBLE_AS_FLOAT_P (c
))
220 return const_double_from_real_value (*CONST_DOUBLE_REAL_VALUE (c
),
228 if (GET_MODE (x
) == BLKmode
)
233 /* Call target hook to avoid the effects of -fpic etc.... */
234 addr
= targetm
.delegitimize_address (addr
);
236 /* Split the address into a base and integer offset. */
237 addr
= strip_offset (addr
, &offset
);
239 if (GET_CODE (addr
) == LO_SUM
)
240 addr
= XEXP (addr
, 1);
242 /* If this is a constant pool reference, we can turn it into its
243 constant and hope that simplifications happen. */
244 if (GET_CODE (addr
) == SYMBOL_REF
245 && CONSTANT_POOL_ADDRESS_P (addr
))
247 c
= get_pool_constant (addr
);
248 cmode
= get_pool_mode (addr
);
250 /* If we're accessing the constant in a different mode than it was
251 originally stored, attempt to fix that up via subreg simplifications.
252 If that fails we have no choice but to return the original memory. */
253 if (known_eq (offset
, 0) && cmode
== GET_MODE (x
))
255 else if (known_in_range_p (offset
, 0, GET_MODE_SIZE (cmode
)))
257 rtx tem
= simplify_subreg (GET_MODE (x
), c
, cmode
, offset
);
258 if (tem
&& CONSTANT_P (tem
))
266 /* Simplify a MEM based on its attributes. This is the default
267 delegitimize_address target hook, and it's recommended that every
268 overrider call it. */
271 delegitimize_mem_from_attrs (rtx x
)
273 /* MEMs without MEM_OFFSETs may have been offset, so we can't just
274 use their base addresses as equivalent. */
277 && MEM_OFFSET_KNOWN_P (x
))
279 tree decl
= MEM_EXPR (x
);
280 machine_mode mode
= GET_MODE (x
);
281 poly_int64 offset
= 0;
283 switch (TREE_CODE (decl
))
293 case ARRAY_RANGE_REF
:
298 case VIEW_CONVERT_EXPR
:
300 poly_int64 bitsize
, bitpos
, bytepos
, toffset_val
= 0;
302 int unsignedp
, reversep
, volatilep
= 0;
305 = get_inner_reference (decl
, &bitsize
, &bitpos
, &toffset
, &mode
,
306 &unsignedp
, &reversep
, &volatilep
);
307 if (maybe_ne (bitsize
, GET_MODE_BITSIZE (mode
))
308 || !multiple_p (bitpos
, BITS_PER_UNIT
, &bytepos
)
309 || (toffset
&& !poly_int_tree_p (toffset
, &toffset_val
)))
312 offset
+= bytepos
+ toffset_val
;
318 && mode
== GET_MODE (x
)
320 && (TREE_STATIC (decl
)
321 || DECL_THREAD_LOCAL_P (decl
))
322 && DECL_RTL_SET_P (decl
)
323 && MEM_P (DECL_RTL (decl
)))
327 offset
+= MEM_OFFSET (x
);
329 newx
= DECL_RTL (decl
);
333 rtx n
= XEXP (newx
, 0), o
= XEXP (x
, 0);
334 poly_int64 n_offset
, o_offset
;
336 /* Avoid creating a new MEM needlessly if we already had
337 the same address. We do if there's no OFFSET and the
338 old address X is identical to NEWX, or if X is of the
339 form (plus NEWX OFFSET), or the NEWX is of the form
340 (plus Y (const_int Z)) and X is that with the offset
341 added: (plus Y (const_int Z+OFFSET)). */
342 n
= strip_offset (n
, &n_offset
);
343 o
= strip_offset (o
, &o_offset
);
344 if (!(known_eq (o_offset
, n_offset
+ offset
)
345 && rtx_equal_p (o
, n
)))
346 x
= adjust_address_nv (newx
, mode
, offset
);
348 else if (GET_MODE (x
) == GET_MODE (newx
)
349 && known_eq (offset
, 0))
357 /* Make a unary operation by first seeing if it folds and otherwise making
358 the specified operation. */
361 simplify_gen_unary (enum rtx_code code
, machine_mode mode
, rtx op
,
362 machine_mode op_mode
)
366 /* If this simplifies, use it. */
367 if ((tem
= simplify_unary_operation (code
, mode
, op
, op_mode
)) != 0)
370 return gen_rtx_fmt_e (code
, mode
, op
);
373 /* Likewise for ternary operations. */
376 simplify_gen_ternary (enum rtx_code code
, machine_mode mode
,
377 machine_mode op0_mode
, rtx op0
, rtx op1
, rtx op2
)
381 /* If this simplifies, use it. */
382 if ((tem
= simplify_ternary_operation (code
, mode
, op0_mode
,
383 op0
, op1
, op2
)) != 0)
386 return gen_rtx_fmt_eee (code
, mode
, op0
, op1
, op2
);
389 /* Likewise, for relational operations.
390 CMP_MODE specifies mode comparison is done in. */
393 simplify_gen_relational (enum rtx_code code
, machine_mode mode
,
394 machine_mode cmp_mode
, rtx op0
, rtx op1
)
398 if ((tem
= simplify_relational_operation (code
, mode
, cmp_mode
,
402 return gen_rtx_fmt_ee (code
, mode
, op0
, op1
);
405 /* If FN is NULL, replace all occurrences of OLD_RTX in X with copy_rtx (DATA)
406 and simplify the result. If FN is non-NULL, call this callback on each
407 X, if it returns non-NULL, replace X with its return value and simplify the
411 simplify_replace_fn_rtx (rtx x
, const_rtx old_rtx
,
412 rtx (*fn
) (rtx
, const_rtx
, void *), void *data
)
414 enum rtx_code code
= GET_CODE (x
);
415 machine_mode mode
= GET_MODE (x
);
416 machine_mode op_mode
;
418 rtx op0
, op1
, op2
, newx
, op
;
422 if (__builtin_expect (fn
!= NULL
, 0))
424 newx
= fn (x
, old_rtx
, data
);
428 else if (rtx_equal_p (x
, old_rtx
))
429 return copy_rtx ((rtx
) data
);
431 switch (GET_RTX_CLASS (code
))
435 op_mode
= GET_MODE (op0
);
436 op0
= simplify_replace_fn_rtx (op0
, old_rtx
, fn
, data
);
437 if (op0
== XEXP (x
, 0))
439 return simplify_gen_unary (code
, mode
, op0
, op_mode
);
443 op0
= simplify_replace_fn_rtx (XEXP (x
, 0), old_rtx
, fn
, data
);
444 op1
= simplify_replace_fn_rtx (XEXP (x
, 1), old_rtx
, fn
, data
);
445 if (op0
== XEXP (x
, 0) && op1
== XEXP (x
, 1))
447 return simplify_gen_binary (code
, mode
, op0
, op1
);
450 case RTX_COMM_COMPARE
:
453 op_mode
= GET_MODE (op0
) != VOIDmode
? GET_MODE (op0
) : GET_MODE (op1
);
454 op0
= simplify_replace_fn_rtx (op0
, old_rtx
, fn
, data
);
455 op1
= simplify_replace_fn_rtx (op1
, old_rtx
, fn
, data
);
456 if (op0
== XEXP (x
, 0) && op1
== XEXP (x
, 1))
458 return simplify_gen_relational (code
, mode
, op_mode
, op0
, op1
);
461 case RTX_BITFIELD_OPS
:
463 op_mode
= GET_MODE (op0
);
464 op0
= simplify_replace_fn_rtx (op0
, old_rtx
, fn
, data
);
465 op1
= simplify_replace_fn_rtx (XEXP (x
, 1), old_rtx
, fn
, data
);
466 op2
= simplify_replace_fn_rtx (XEXP (x
, 2), old_rtx
, fn
, data
);
467 if (op0
== XEXP (x
, 0) && op1
== XEXP (x
, 1) && op2
== XEXP (x
, 2))
469 if (op_mode
== VOIDmode
)
470 op_mode
= GET_MODE (op0
);
471 return simplify_gen_ternary (code
, mode
, op_mode
, op0
, op1
, op2
);
476 op0
= simplify_replace_fn_rtx (SUBREG_REG (x
), old_rtx
, fn
, data
);
477 if (op0
== SUBREG_REG (x
))
479 op0
= simplify_gen_subreg (GET_MODE (x
), op0
,
480 GET_MODE (SUBREG_REG (x
)),
482 return op0
? op0
: x
;
489 op0
= simplify_replace_fn_rtx (XEXP (x
, 0), old_rtx
, fn
, data
);
490 if (op0
== XEXP (x
, 0))
492 return replace_equiv_address_nv (x
, op0
);
494 else if (code
== LO_SUM
)
496 op0
= simplify_replace_fn_rtx (XEXP (x
, 0), old_rtx
, fn
, data
);
497 op1
= simplify_replace_fn_rtx (XEXP (x
, 1), old_rtx
, fn
, data
);
499 /* (lo_sum (high x) y) -> y where x and y have the same base. */
500 if (GET_CODE (op0
) == HIGH
)
502 rtx base0
, base1
, offset0
, offset1
;
503 split_const (XEXP (op0
, 0), &base0
, &offset0
);
504 split_const (op1
, &base1
, &offset1
);
505 if (rtx_equal_p (base0
, base1
))
509 if (op0
== XEXP (x
, 0) && op1
== XEXP (x
, 1))
511 return gen_rtx_LO_SUM (mode
, op0
, op1
);
520 fmt
= GET_RTX_FORMAT (code
);
521 for (i
= 0; fmt
[i
]; i
++)
526 newvec
= XVEC (newx
, i
);
527 for (j
= 0; j
< GET_NUM_ELEM (vec
); j
++)
529 op
= simplify_replace_fn_rtx (RTVEC_ELT (vec
, j
),
531 if (op
!= RTVEC_ELT (vec
, j
))
535 newvec
= shallow_copy_rtvec (vec
);
537 newx
= shallow_copy_rtx (x
);
538 XVEC (newx
, i
) = newvec
;
540 RTVEC_ELT (newvec
, j
) = op
;
548 op
= simplify_replace_fn_rtx (XEXP (x
, i
), old_rtx
, fn
, data
);
549 if (op
!= XEXP (x
, i
))
552 newx
= shallow_copy_rtx (x
);
561 /* Replace all occurrences of OLD_RTX in X with NEW_RTX and try to simplify the
562 resulting RTX. Return a new RTX which is as simplified as possible. */
565 simplify_replace_rtx (rtx x
, const_rtx old_rtx
, rtx new_rtx
)
567 return simplify_replace_fn_rtx (x
, old_rtx
, 0, new_rtx
);
570 /* Try to simplify a MODE truncation of OP, which has OP_MODE.
571 Only handle cases where the truncated value is inherently an rvalue.
573 RTL provides two ways of truncating a value:
575 1. a lowpart subreg. This form is only a truncation when both
576 the outer and inner modes (here MODE and OP_MODE respectively)
577 are scalar integers, and only then when the subreg is used as
580 It is only valid to form such truncating subregs if the
581 truncation requires no action by the target. The onus for
582 proving this is on the creator of the subreg -- e.g. the
583 caller to simplify_subreg or simplify_gen_subreg -- and typically
584 involves either TRULY_NOOP_TRUNCATION_MODES_P or truncated_to_mode.
586 2. a TRUNCATE. This form handles both scalar and compound integers.
588 The first form is preferred where valid. However, the TRUNCATE
589 handling in simplify_unary_operation turns the second form into the
590 first form when TRULY_NOOP_TRUNCATION_MODES_P or truncated_to_mode allow,
591 so it is generally safe to form rvalue truncations using:
593 simplify_gen_unary (TRUNCATE, ...)
595 and leave simplify_unary_operation to work out which representation
598 Because of the proof requirements on (1), simplify_truncation must
599 also use simplify_gen_unary (TRUNCATE, ...) to truncate parts of OP,
600 regardless of whether the outer truncation came from a SUBREG or a
601 TRUNCATE. For example, if the caller has proven that an SImode
606 is a no-op and can be represented as a subreg, it does not follow
607 that SImode truncations of X and Y are also no-ops. On a target
608 like 64-bit MIPS that requires SImode values to be stored in
609 sign-extended form, an SImode truncation of:
611 (and:DI (reg:DI X) (const_int 63))
613 is trivially a no-op because only the lower 6 bits can be set.
614 However, X is still an arbitrary 64-bit number and so we cannot
615 assume that truncating it too is a no-op. */
618 simplify_truncation (machine_mode mode
, rtx op
,
619 machine_mode op_mode
)
621 unsigned int precision
= GET_MODE_UNIT_PRECISION (mode
);
622 unsigned int op_precision
= GET_MODE_UNIT_PRECISION (op_mode
);
623 scalar_int_mode int_mode
, int_op_mode
, subreg_mode
;
625 gcc_assert (precision
<= op_precision
);
627 /* Optimize truncations of zero and sign extended values. */
628 if (GET_CODE (op
) == ZERO_EXTEND
629 || GET_CODE (op
) == SIGN_EXTEND
)
631 /* There are three possibilities. If MODE is the same as the
632 origmode, we can omit both the extension and the subreg.
633 If MODE is not larger than the origmode, we can apply the
634 truncation without the extension. Finally, if the outermode
635 is larger than the origmode, we can just extend to the appropriate
637 machine_mode origmode
= GET_MODE (XEXP (op
, 0));
638 if (mode
== origmode
)
640 else if (precision
<= GET_MODE_UNIT_PRECISION (origmode
))
641 return simplify_gen_unary (TRUNCATE
, mode
,
642 XEXP (op
, 0), origmode
);
644 return simplify_gen_unary (GET_CODE (op
), mode
,
645 XEXP (op
, 0), origmode
);
648 /* If the machine can perform operations in the truncated mode, distribute
649 the truncation, i.e. simplify (truncate:QI (op:SI (x:SI) (y:SI))) into
650 (op:QI (truncate:QI (x:SI)) (truncate:QI (y:SI))). */
652 && (!WORD_REGISTER_OPERATIONS
|| precision
>= BITS_PER_WORD
)
653 && (GET_CODE (op
) == PLUS
654 || GET_CODE (op
) == MINUS
655 || GET_CODE (op
) == MULT
))
657 rtx op0
= simplify_gen_unary (TRUNCATE
, mode
, XEXP (op
, 0), op_mode
);
660 rtx op1
= simplify_gen_unary (TRUNCATE
, mode
, XEXP (op
, 1), op_mode
);
662 return simplify_gen_binary (GET_CODE (op
), mode
, op0
, op1
);
666 /* Simplify (truncate:QI (lshiftrt:SI (sign_extend:SI (x:QI)) C)) into
667 to (ashiftrt:QI (x:QI) C), where C is a suitable small constant and
668 the outer subreg is effectively a truncation to the original mode. */
669 if ((GET_CODE (op
) == LSHIFTRT
670 || GET_CODE (op
) == ASHIFTRT
)
671 /* Ensure that OP_MODE is at least twice as wide as MODE
672 to avoid the possibility that an outer LSHIFTRT shifts by more
673 than the sign extension's sign_bit_copies and introduces zeros
674 into the high bits of the result. */
675 && 2 * precision
<= op_precision
676 && CONST_INT_P (XEXP (op
, 1))
677 && GET_CODE (XEXP (op
, 0)) == SIGN_EXTEND
678 && GET_MODE (XEXP (XEXP (op
, 0), 0)) == mode
679 && UINTVAL (XEXP (op
, 1)) < precision
)
680 return simplify_gen_binary (ASHIFTRT
, mode
,
681 XEXP (XEXP (op
, 0), 0), XEXP (op
, 1));
683 /* Likewise (truncate:QI (lshiftrt:SI (zero_extend:SI (x:QI)) C)) into
684 to (lshiftrt:QI (x:QI) C), where C is a suitable small constant and
685 the outer subreg is effectively a truncation to the original mode. */
686 if ((GET_CODE (op
) == LSHIFTRT
687 || GET_CODE (op
) == ASHIFTRT
)
688 && CONST_INT_P (XEXP (op
, 1))
689 && GET_CODE (XEXP (op
, 0)) == ZERO_EXTEND
690 && GET_MODE (XEXP (XEXP (op
, 0), 0)) == mode
691 && UINTVAL (XEXP (op
, 1)) < precision
)
692 return simplify_gen_binary (LSHIFTRT
, mode
,
693 XEXP (XEXP (op
, 0), 0), XEXP (op
, 1));
695 /* Likewise (truncate:QI (ashift:SI (zero_extend:SI (x:QI)) C)) into
696 to (ashift:QI (x:QI) C), where C is a suitable small constant and
697 the outer subreg is effectively a truncation to the original mode. */
698 if (GET_CODE (op
) == ASHIFT
699 && CONST_INT_P (XEXP (op
, 1))
700 && (GET_CODE (XEXP (op
, 0)) == ZERO_EXTEND
701 || GET_CODE (XEXP (op
, 0)) == SIGN_EXTEND
)
702 && GET_MODE (XEXP (XEXP (op
, 0), 0)) == mode
703 && UINTVAL (XEXP (op
, 1)) < precision
)
704 return simplify_gen_binary (ASHIFT
, mode
,
705 XEXP (XEXP (op
, 0), 0), XEXP (op
, 1));
707 /* Likewise (truncate:QI (and:SI (lshiftrt:SI (x:SI) C) C2)) into
708 (and:QI (lshiftrt:QI (truncate:QI (x:SI)) C) C2) for suitable C
710 if (GET_CODE (op
) == AND
711 && (GET_CODE (XEXP (op
, 0)) == LSHIFTRT
712 || GET_CODE (XEXP (op
, 0)) == ASHIFTRT
)
713 && CONST_INT_P (XEXP (XEXP (op
, 0), 1))
714 && CONST_INT_P (XEXP (op
, 1)))
716 rtx op0
= (XEXP (XEXP (op
, 0), 0));
717 rtx shift_op
= XEXP (XEXP (op
, 0), 1);
718 rtx mask_op
= XEXP (op
, 1);
719 unsigned HOST_WIDE_INT shift
= UINTVAL (shift_op
);
720 unsigned HOST_WIDE_INT mask
= UINTVAL (mask_op
);
722 if (shift
< precision
723 /* If doing this transform works for an X with all bits set,
724 it works for any X. */
725 && ((GET_MODE_MASK (mode
) >> shift
) & mask
)
726 == ((GET_MODE_MASK (op_mode
) >> shift
) & mask
)
727 && (op0
= simplify_gen_unary (TRUNCATE
, mode
, op0
, op_mode
))
728 && (op0
= simplify_gen_binary (LSHIFTRT
, mode
, op0
, shift_op
)))
730 mask_op
= GEN_INT (trunc_int_for_mode (mask
, mode
));
731 return simplify_gen_binary (AND
, mode
, op0
, mask_op
);
735 /* Turn (truncate:M1 (*_extract:M2 (reg:M2) (len) (pos))) into
736 (*_extract:M1 (truncate:M1 (reg:M2)) (len) (pos')) if possible without
738 if ((GET_CODE (op
) == ZERO_EXTRACT
|| GET_CODE (op
) == SIGN_EXTRACT
)
739 && REG_P (XEXP (op
, 0))
740 && GET_MODE (XEXP (op
, 0)) == GET_MODE (op
)
741 && CONST_INT_P (XEXP (op
, 1))
742 && CONST_INT_P (XEXP (op
, 2)))
744 rtx op0
= XEXP (op
, 0);
745 unsigned HOST_WIDE_INT len
= UINTVAL (XEXP (op
, 1));
746 unsigned HOST_WIDE_INT pos
= UINTVAL (XEXP (op
, 2));
747 if (BITS_BIG_ENDIAN
&& pos
>= op_precision
- precision
)
749 op0
= simplify_gen_unary (TRUNCATE
, mode
, op0
, GET_MODE (op0
));
752 pos
-= op_precision
- precision
;
753 return simplify_gen_ternary (GET_CODE (op
), mode
, mode
, op0
,
754 XEXP (op
, 1), GEN_INT (pos
));
757 else if (!BITS_BIG_ENDIAN
&& precision
>= len
+ pos
)
759 op0
= simplify_gen_unary (TRUNCATE
, mode
, op0
, GET_MODE (op0
));
761 return simplify_gen_ternary (GET_CODE (op
), mode
, mode
, op0
,
762 XEXP (op
, 1), XEXP (op
, 2));
766 /* Recognize a word extraction from a multi-word subreg. */
767 if ((GET_CODE (op
) == LSHIFTRT
768 || GET_CODE (op
) == ASHIFTRT
)
769 && SCALAR_INT_MODE_P (mode
)
770 && SCALAR_INT_MODE_P (op_mode
)
771 && precision
>= BITS_PER_WORD
772 && 2 * precision
<= op_precision
773 && CONST_INT_P (XEXP (op
, 1))
774 && (INTVAL (XEXP (op
, 1)) & (precision
- 1)) == 0
775 && UINTVAL (XEXP (op
, 1)) < op_precision
)
777 poly_int64 byte
= subreg_lowpart_offset (mode
, op_mode
);
778 int shifted_bytes
= INTVAL (XEXP (op
, 1)) / BITS_PER_UNIT
;
779 return simplify_gen_subreg (mode
, XEXP (op
, 0), op_mode
,
781 ? byte
- shifted_bytes
782 : byte
+ shifted_bytes
));
785 /* If we have a TRUNCATE of a right shift of MEM, make a new MEM
786 and try replacing the TRUNCATE and shift with it. Don't do this
787 if the MEM has a mode-dependent address. */
788 if ((GET_CODE (op
) == LSHIFTRT
789 || GET_CODE (op
) == ASHIFTRT
)
790 && is_a
<scalar_int_mode
> (mode
, &int_mode
)
791 && is_a
<scalar_int_mode
> (op_mode
, &int_op_mode
)
792 && MEM_P (XEXP (op
, 0))
793 && CONST_INT_P (XEXP (op
, 1))
794 && INTVAL (XEXP (op
, 1)) % GET_MODE_BITSIZE (int_mode
) == 0
795 && INTVAL (XEXP (op
, 1)) > 0
796 && INTVAL (XEXP (op
, 1)) < GET_MODE_BITSIZE (int_op_mode
)
797 && ! mode_dependent_address_p (XEXP (XEXP (op
, 0), 0),
798 MEM_ADDR_SPACE (XEXP (op
, 0)))
799 && ! MEM_VOLATILE_P (XEXP (op
, 0))
800 && (GET_MODE_SIZE (int_mode
) >= UNITS_PER_WORD
801 || WORDS_BIG_ENDIAN
== BYTES_BIG_ENDIAN
))
803 poly_int64 byte
= subreg_lowpart_offset (int_mode
, int_op_mode
);
804 int shifted_bytes
= INTVAL (XEXP (op
, 1)) / BITS_PER_UNIT
;
805 return adjust_address_nv (XEXP (op
, 0), int_mode
,
807 ? byte
- shifted_bytes
808 : byte
+ shifted_bytes
));
811 /* (truncate:SI (OP:DI ({sign,zero}_extend:DI foo:SI))) is
812 (OP:SI foo:SI) if OP is NEG or ABS. */
813 if ((GET_CODE (op
) == ABS
814 || GET_CODE (op
) == NEG
)
815 && (GET_CODE (XEXP (op
, 0)) == SIGN_EXTEND
816 || GET_CODE (XEXP (op
, 0)) == ZERO_EXTEND
)
817 && GET_MODE (XEXP (XEXP (op
, 0), 0)) == mode
)
818 return simplify_gen_unary (GET_CODE (op
), mode
,
819 XEXP (XEXP (op
, 0), 0), mode
);
821 /* (truncate:A (subreg:B (truncate:C X) 0)) is
823 if (GET_CODE (op
) == SUBREG
824 && is_a
<scalar_int_mode
> (mode
, &int_mode
)
825 && SCALAR_INT_MODE_P (op_mode
)
826 && is_a
<scalar_int_mode
> (GET_MODE (SUBREG_REG (op
)), &subreg_mode
)
827 && GET_CODE (SUBREG_REG (op
)) == TRUNCATE
828 && subreg_lowpart_p (op
))
830 rtx inner
= XEXP (SUBREG_REG (op
), 0);
831 if (GET_MODE_PRECISION (int_mode
) <= GET_MODE_PRECISION (subreg_mode
))
832 return simplify_gen_unary (TRUNCATE
, int_mode
, inner
,
835 /* If subreg above is paradoxical and C is narrower
836 than A, return (subreg:A (truncate:C X) 0). */
837 return simplify_gen_subreg (int_mode
, SUBREG_REG (op
), subreg_mode
, 0);
840 /* (truncate:A (truncate:B X)) is (truncate:A X). */
841 if (GET_CODE (op
) == TRUNCATE
)
842 return simplify_gen_unary (TRUNCATE
, mode
, XEXP (op
, 0),
843 GET_MODE (XEXP (op
, 0)));
845 /* (truncate:A (ior X C)) is (const_int -1) if C is equal to that already,
847 if (GET_CODE (op
) == IOR
848 && SCALAR_INT_MODE_P (mode
)
849 && SCALAR_INT_MODE_P (op_mode
)
850 && CONST_INT_P (XEXP (op
, 1))
851 && trunc_int_for_mode (INTVAL (XEXP (op
, 1)), mode
) == -1)
857 /* Try to simplify a unary operation CODE whose output mode is to be
858 MODE with input operand OP whose mode was originally OP_MODE.
859 Return zero if no simplification can be made. */
861 simplify_unary_operation (enum rtx_code code
, machine_mode mode
,
862 rtx op
, machine_mode op_mode
)
866 trueop
= avoid_constant_pool_reference (op
);
868 tem
= simplify_const_unary_operation (code
, mode
, trueop
, op_mode
);
872 return simplify_unary_operation_1 (code
, mode
, op
);
875 /* Return true if FLOAT or UNSIGNED_FLOAT operation OP is known
879 exact_int_to_float_conversion_p (const_rtx op
)
881 int out_bits
= significand_size (GET_MODE_INNER (GET_MODE (op
)));
882 machine_mode op0_mode
= GET_MODE (XEXP (op
, 0));
883 /* Constants shouldn't reach here. */
884 gcc_assert (op0_mode
!= VOIDmode
);
885 int in_prec
= GET_MODE_UNIT_PRECISION (op0_mode
);
886 int in_bits
= in_prec
;
887 if (HWI_COMPUTABLE_MODE_P (op0_mode
))
889 unsigned HOST_WIDE_INT nonzero
= nonzero_bits (XEXP (op
, 0), op0_mode
);
890 if (GET_CODE (op
) == FLOAT
)
891 in_bits
-= num_sign_bit_copies (XEXP (op
, 0), op0_mode
);
892 else if (GET_CODE (op
) == UNSIGNED_FLOAT
)
893 in_bits
= wi::min_precision (wi::uhwi (nonzero
, in_prec
), UNSIGNED
);
896 in_bits
-= wi::ctz (wi::uhwi (nonzero
, in_prec
));
898 return in_bits
<= out_bits
;
901 /* Perform some simplifications we can do even if the operands
904 simplify_unary_operation_1 (enum rtx_code code
, machine_mode mode
, rtx op
)
906 enum rtx_code reversed
;
907 rtx temp
, elt
, base
, step
;
908 scalar_int_mode inner
, int_mode
, op_mode
, op0_mode
;
913 /* (not (not X)) == X. */
914 if (GET_CODE (op
) == NOT
)
917 /* (not (eq X Y)) == (ne X Y), etc. if BImode or the result of the
918 comparison is all ones. */
919 if (COMPARISON_P (op
)
920 && (mode
== BImode
|| STORE_FLAG_VALUE
== -1)
921 && ((reversed
= reversed_comparison_code (op
, NULL
)) != UNKNOWN
))
922 return simplify_gen_relational (reversed
, mode
, VOIDmode
,
923 XEXP (op
, 0), XEXP (op
, 1));
925 /* (not (plus X -1)) can become (neg X). */
926 if (GET_CODE (op
) == PLUS
927 && XEXP (op
, 1) == constm1_rtx
)
928 return simplify_gen_unary (NEG
, mode
, XEXP (op
, 0), mode
);
930 /* Similarly, (not (neg X)) is (plus X -1). Only do this for
931 modes that have CONSTM1_RTX, i.e. MODE_INT, MODE_PARTIAL_INT
932 and MODE_VECTOR_INT. */
933 if (GET_CODE (op
) == NEG
&& CONSTM1_RTX (mode
))
934 return simplify_gen_binary (PLUS
, mode
, XEXP (op
, 0),
937 /* (not (xor X C)) for C constant is (xor X D) with D = ~C. */
938 if (GET_CODE (op
) == XOR
939 && CONST_INT_P (XEXP (op
, 1))
940 && (temp
= simplify_unary_operation (NOT
, mode
,
941 XEXP (op
, 1), mode
)) != 0)
942 return simplify_gen_binary (XOR
, mode
, XEXP (op
, 0), temp
);
944 /* (not (plus X C)) for signbit C is (xor X D) with D = ~C. */
945 if (GET_CODE (op
) == PLUS
946 && CONST_INT_P (XEXP (op
, 1))
947 && mode_signbit_p (mode
, XEXP (op
, 1))
948 && (temp
= simplify_unary_operation (NOT
, mode
,
949 XEXP (op
, 1), mode
)) != 0)
950 return simplify_gen_binary (XOR
, mode
, XEXP (op
, 0), temp
);
953 /* (not (ashift 1 X)) is (rotate ~1 X). We used to do this for
954 operands other than 1, but that is not valid. We could do a
955 similar simplification for (not (lshiftrt C X)) where C is
956 just the sign bit, but this doesn't seem common enough to
958 if (GET_CODE (op
) == ASHIFT
959 && XEXP (op
, 0) == const1_rtx
)
961 temp
= simplify_gen_unary (NOT
, mode
, const1_rtx
, mode
);
962 return simplify_gen_binary (ROTATE
, mode
, temp
, XEXP (op
, 1));
965 /* (not (ashiftrt foo C)) where C is the number of bits in FOO
966 minus 1 is (ge foo (const_int 0)) if STORE_FLAG_VALUE is -1,
967 so we can perform the above simplification. */
968 if (STORE_FLAG_VALUE
== -1
969 && is_a
<scalar_int_mode
> (mode
, &int_mode
)
970 && GET_CODE (op
) == ASHIFTRT
971 && CONST_INT_P (XEXP (op
, 1))
972 && INTVAL (XEXP (op
, 1)) == GET_MODE_PRECISION (int_mode
) - 1)
973 return simplify_gen_relational (GE
, int_mode
, VOIDmode
,
974 XEXP (op
, 0), const0_rtx
);
977 if (partial_subreg_p (op
)
978 && subreg_lowpart_p (op
)
979 && GET_CODE (SUBREG_REG (op
)) == ASHIFT
980 && XEXP (SUBREG_REG (op
), 0) == const1_rtx
)
982 machine_mode inner_mode
= GET_MODE (SUBREG_REG (op
));
985 x
= gen_rtx_ROTATE (inner_mode
,
986 simplify_gen_unary (NOT
, inner_mode
, const1_rtx
,
988 XEXP (SUBREG_REG (op
), 1));
989 temp
= rtl_hooks
.gen_lowpart_no_emit (mode
, x
);
994 /* Apply De Morgan's laws to reduce number of patterns for machines
995 with negating logical insns (and-not, nand, etc.). If result has
996 only one NOT, put it first, since that is how the patterns are
998 if (GET_CODE (op
) == IOR
|| GET_CODE (op
) == AND
)
1000 rtx in1
= XEXP (op
, 0), in2
= XEXP (op
, 1);
1001 machine_mode op_mode
;
1003 op_mode
= GET_MODE (in1
);
1004 in1
= simplify_gen_unary (NOT
, op_mode
, in1
, op_mode
);
1006 op_mode
= GET_MODE (in2
);
1007 if (op_mode
== VOIDmode
)
1009 in2
= simplify_gen_unary (NOT
, op_mode
, in2
, op_mode
);
1011 if (GET_CODE (in2
) == NOT
&& GET_CODE (in1
) != NOT
)
1012 std::swap (in1
, in2
);
1014 return gen_rtx_fmt_ee (GET_CODE (op
) == IOR
? AND
: IOR
,
1018 /* (not (bswap x)) -> (bswap (not x)). */
1019 if (GET_CODE (op
) == BSWAP
)
1021 rtx x
= simplify_gen_unary (NOT
, mode
, XEXP (op
, 0), mode
);
1022 return simplify_gen_unary (BSWAP
, mode
, x
, mode
);
1027 /* (neg (neg X)) == X. */
1028 if (GET_CODE (op
) == NEG
)
1029 return XEXP (op
, 0);
1031 /* (neg (x ? (neg y) : y)) == !x ? (neg y) : y.
1032 If comparison is not reversible use
1034 if (GET_CODE (op
) == IF_THEN_ELSE
)
1036 rtx cond
= XEXP (op
, 0);
1037 rtx true_rtx
= XEXP (op
, 1);
1038 rtx false_rtx
= XEXP (op
, 2);
1040 if ((GET_CODE (true_rtx
) == NEG
1041 && rtx_equal_p (XEXP (true_rtx
, 0), false_rtx
))
1042 || (GET_CODE (false_rtx
) == NEG
1043 && rtx_equal_p (XEXP (false_rtx
, 0), true_rtx
)))
1045 if (reversed_comparison_code (cond
, NULL
) != UNKNOWN
)
1046 temp
= reversed_comparison (cond
, mode
);
1050 std::swap (true_rtx
, false_rtx
);
1052 return simplify_gen_ternary (IF_THEN_ELSE
, mode
,
1053 mode
, temp
, true_rtx
, false_rtx
);
1057 /* (neg (plus X 1)) can become (not X). */
1058 if (GET_CODE (op
) == PLUS
1059 && XEXP (op
, 1) == const1_rtx
)
1060 return simplify_gen_unary (NOT
, mode
, XEXP (op
, 0), mode
);
1062 /* Similarly, (neg (not X)) is (plus X 1). */
1063 if (GET_CODE (op
) == NOT
)
1064 return simplify_gen_binary (PLUS
, mode
, XEXP (op
, 0),
1067 /* (neg (minus X Y)) can become (minus Y X). This transformation
1068 isn't safe for modes with signed zeros, since if X and Y are
1069 both +0, (minus Y X) is the same as (minus X Y). If the
1070 rounding mode is towards +infinity (or -infinity) then the two
1071 expressions will be rounded differently. */
1072 if (GET_CODE (op
) == MINUS
1073 && !HONOR_SIGNED_ZEROS (mode
)
1074 && !HONOR_SIGN_DEPENDENT_ROUNDING (mode
))
1075 return simplify_gen_binary (MINUS
, mode
, XEXP (op
, 1), XEXP (op
, 0));
1077 if (GET_CODE (op
) == PLUS
1078 && !HONOR_SIGNED_ZEROS (mode
)
1079 && !HONOR_SIGN_DEPENDENT_ROUNDING (mode
))
1081 /* (neg (plus A C)) is simplified to (minus -C A). */
1082 if (CONST_SCALAR_INT_P (XEXP (op
, 1))
1083 || CONST_DOUBLE_AS_FLOAT_P (XEXP (op
, 1)))
1085 temp
= simplify_unary_operation (NEG
, mode
, XEXP (op
, 1), mode
);
1087 return simplify_gen_binary (MINUS
, mode
, temp
, XEXP (op
, 0));
1090 /* (neg (plus A B)) is canonicalized to (minus (neg A) B). */
1091 temp
= simplify_gen_unary (NEG
, mode
, XEXP (op
, 0), mode
);
1092 return simplify_gen_binary (MINUS
, mode
, temp
, XEXP (op
, 1));
1095 /* (neg (mult A B)) becomes (mult A (neg B)).
1096 This works even for floating-point values. */
1097 if (GET_CODE (op
) == MULT
1098 && !HONOR_SIGN_DEPENDENT_ROUNDING (mode
))
1100 temp
= simplify_gen_unary (NEG
, mode
, XEXP (op
, 1), mode
);
1101 return simplify_gen_binary (MULT
, mode
, XEXP (op
, 0), temp
);
1104 /* NEG commutes with ASHIFT since it is multiplication. Only do
1105 this if we can then eliminate the NEG (e.g., if the operand
1107 if (GET_CODE (op
) == ASHIFT
)
1109 temp
= simplify_unary_operation (NEG
, mode
, XEXP (op
, 0), mode
);
1111 return simplify_gen_binary (ASHIFT
, mode
, temp
, XEXP (op
, 1));
1114 /* (neg (ashiftrt X C)) can be replaced by (lshiftrt X C) when
1115 C is equal to the width of MODE minus 1. */
1116 if (GET_CODE (op
) == ASHIFTRT
1117 && CONST_INT_P (XEXP (op
, 1))
1118 && INTVAL (XEXP (op
, 1)) == GET_MODE_UNIT_PRECISION (mode
) - 1)
1119 return simplify_gen_binary (LSHIFTRT
, mode
,
1120 XEXP (op
, 0), XEXP (op
, 1));
1122 /* (neg (lshiftrt X C)) can be replaced by (ashiftrt X C) when
1123 C is equal to the width of MODE minus 1. */
1124 if (GET_CODE (op
) == LSHIFTRT
1125 && CONST_INT_P (XEXP (op
, 1))
1126 && INTVAL (XEXP (op
, 1)) == GET_MODE_UNIT_PRECISION (mode
) - 1)
1127 return simplify_gen_binary (ASHIFTRT
, mode
,
1128 XEXP (op
, 0), XEXP (op
, 1));
1130 /* (neg (xor A 1)) is (plus A -1) if A is known to be either 0 or 1. */
1131 if (GET_CODE (op
) == XOR
1132 && XEXP (op
, 1) == const1_rtx
1133 && nonzero_bits (XEXP (op
, 0), mode
) == 1)
1134 return plus_constant (mode
, XEXP (op
, 0), -1);
1136 /* (neg (lt x 0)) is (ashiftrt X C) if STORE_FLAG_VALUE is 1. */
1137 /* (neg (lt x 0)) is (lshiftrt X C) if STORE_FLAG_VALUE is -1. */
1138 if (GET_CODE (op
) == LT
1139 && XEXP (op
, 1) == const0_rtx
1140 && is_a
<scalar_int_mode
> (GET_MODE (XEXP (op
, 0)), &inner
))
1142 int_mode
= as_a
<scalar_int_mode
> (mode
);
1143 int isize
= GET_MODE_PRECISION (inner
);
1144 if (STORE_FLAG_VALUE
== 1)
1146 temp
= simplify_gen_binary (ASHIFTRT
, inner
, XEXP (op
, 0),
1147 gen_int_shift_amount (inner
,
1149 if (int_mode
== inner
)
1151 if (GET_MODE_PRECISION (int_mode
) > isize
)
1152 return simplify_gen_unary (SIGN_EXTEND
, int_mode
, temp
, inner
);
1153 return simplify_gen_unary (TRUNCATE
, int_mode
, temp
, inner
);
1155 else if (STORE_FLAG_VALUE
== -1)
1157 temp
= simplify_gen_binary (LSHIFTRT
, inner
, XEXP (op
, 0),
1158 gen_int_shift_amount (inner
,
1160 if (int_mode
== inner
)
1162 if (GET_MODE_PRECISION (int_mode
) > isize
)
1163 return simplify_gen_unary (ZERO_EXTEND
, int_mode
, temp
, inner
);
1164 return simplify_gen_unary (TRUNCATE
, int_mode
, temp
, inner
);
1168 if (vec_series_p (op
, &base
, &step
))
1170 /* Only create a new series if we can simplify both parts. In other
1171 cases this isn't really a simplification, and it's not necessarily
1172 a win to replace a vector operation with a scalar operation. */
1173 scalar_mode inner_mode
= GET_MODE_INNER (mode
);
1174 base
= simplify_unary_operation (NEG
, inner_mode
, base
, inner_mode
);
1177 step
= simplify_unary_operation (NEG
, inner_mode
,
1180 return gen_vec_series (mode
, base
, step
);
1186 /* Don't optimize (lshiftrt (mult ...)) as it would interfere
1187 with the umulXi3_highpart patterns. */
1188 if (GET_CODE (op
) == LSHIFTRT
1189 && GET_CODE (XEXP (op
, 0)) == MULT
)
1192 if (GET_MODE_CLASS (mode
) == MODE_PARTIAL_INT
)
1194 if (TRULY_NOOP_TRUNCATION_MODES_P (mode
, GET_MODE (op
)))
1196 temp
= rtl_hooks
.gen_lowpart_no_emit (mode
, op
);
1200 /* We can't handle truncation to a partial integer mode here
1201 because we don't know the real bitsize of the partial
1206 if (GET_MODE (op
) != VOIDmode
)
1208 temp
= simplify_truncation (mode
, op
, GET_MODE (op
));
1213 /* If we know that the value is already truncated, we can
1214 replace the TRUNCATE with a SUBREG. */
1215 if (known_eq (GET_MODE_NUNITS (mode
), 1)
1216 && (TRULY_NOOP_TRUNCATION_MODES_P (mode
, GET_MODE (op
))
1217 || truncated_to_mode (mode
, op
)))
1219 temp
= rtl_hooks
.gen_lowpart_no_emit (mode
, op
);
1224 /* A truncate of a comparison can be replaced with a subreg if
1225 STORE_FLAG_VALUE permits. This is like the previous test,
1226 but it works even if the comparison is done in a mode larger
1227 than HOST_BITS_PER_WIDE_INT. */
1228 if (HWI_COMPUTABLE_MODE_P (mode
)
1229 && COMPARISON_P (op
)
1230 && (STORE_FLAG_VALUE
& ~GET_MODE_MASK (mode
)) == 0)
1232 temp
= rtl_hooks
.gen_lowpart_no_emit (mode
, op
);
1237 /* A truncate of a memory is just loading the low part of the memory
1238 if we are not changing the meaning of the address. */
1239 if (GET_CODE (op
) == MEM
1240 && !VECTOR_MODE_P (mode
)
1241 && !MEM_VOLATILE_P (op
)
1242 && !mode_dependent_address_p (XEXP (op
, 0), MEM_ADDR_SPACE (op
)))
1244 temp
= rtl_hooks
.gen_lowpart_no_emit (mode
, op
);
1251 case FLOAT_TRUNCATE
:
1252 if (DECIMAL_FLOAT_MODE_P (mode
))
1255 /* (float_truncate:SF (float_extend:DF foo:SF)) = foo:SF. */
1256 if (GET_CODE (op
) == FLOAT_EXTEND
1257 && GET_MODE (XEXP (op
, 0)) == mode
)
1258 return XEXP (op
, 0);
1260 /* (float_truncate:SF (float_truncate:DF foo:XF))
1261 = (float_truncate:SF foo:XF).
1262 This may eliminate double rounding, so it is unsafe.
1264 (float_truncate:SF (float_extend:XF foo:DF))
1265 = (float_truncate:SF foo:DF).
1267 (float_truncate:DF (float_extend:XF foo:SF))
1268 = (float_extend:DF foo:SF). */
1269 if ((GET_CODE (op
) == FLOAT_TRUNCATE
1270 && flag_unsafe_math_optimizations
)
1271 || GET_CODE (op
) == FLOAT_EXTEND
)
1272 return simplify_gen_unary (GET_MODE_UNIT_SIZE (GET_MODE (XEXP (op
, 0)))
1273 > GET_MODE_UNIT_SIZE (mode
)
1274 ? FLOAT_TRUNCATE
: FLOAT_EXTEND
,
1276 XEXP (op
, 0), mode
);
1278 /* (float_truncate (float x)) is (float x) */
1279 if ((GET_CODE (op
) == FLOAT
|| GET_CODE (op
) == UNSIGNED_FLOAT
)
1280 && (flag_unsafe_math_optimizations
1281 || exact_int_to_float_conversion_p (op
)))
1282 return simplify_gen_unary (GET_CODE (op
), mode
,
1284 GET_MODE (XEXP (op
, 0)));
1286 /* (float_truncate:SF (OP:DF (float_extend:DF foo:sf))) is
1287 (OP:SF foo:SF) if OP is NEG or ABS. */
1288 if ((GET_CODE (op
) == ABS
1289 || GET_CODE (op
) == NEG
)
1290 && GET_CODE (XEXP (op
, 0)) == FLOAT_EXTEND
1291 && GET_MODE (XEXP (XEXP (op
, 0), 0)) == mode
)
1292 return simplify_gen_unary (GET_CODE (op
), mode
,
1293 XEXP (XEXP (op
, 0), 0), mode
);
1295 /* (float_truncate:SF (subreg:DF (float_truncate:SF X) 0))
1296 is (float_truncate:SF x). */
1297 if (GET_CODE (op
) == SUBREG
1298 && subreg_lowpart_p (op
)
1299 && GET_CODE (SUBREG_REG (op
)) == FLOAT_TRUNCATE
)
1300 return SUBREG_REG (op
);
1304 if (DECIMAL_FLOAT_MODE_P (mode
))
1307 /* (float_extend (float_extend x)) is (float_extend x)
1309 (float_extend (float x)) is (float x) assuming that double
1310 rounding can't happen.
1312 if (GET_CODE (op
) == FLOAT_EXTEND
1313 || ((GET_CODE (op
) == FLOAT
|| GET_CODE (op
) == UNSIGNED_FLOAT
)
1314 && exact_int_to_float_conversion_p (op
)))
1315 return simplify_gen_unary (GET_CODE (op
), mode
,
1317 GET_MODE (XEXP (op
, 0)));
1322 /* (abs (neg <foo>)) -> (abs <foo>) */
1323 if (GET_CODE (op
) == NEG
)
1324 return simplify_gen_unary (ABS
, mode
, XEXP (op
, 0),
1325 GET_MODE (XEXP (op
, 0)));
1327 /* If the mode of the operand is VOIDmode (i.e. if it is ASM_OPERANDS),
1329 if (GET_MODE (op
) == VOIDmode
)
1332 /* If operand is something known to be positive, ignore the ABS. */
1333 if (GET_CODE (op
) == FFS
|| GET_CODE (op
) == ABS
1334 || val_signbit_known_clear_p (GET_MODE (op
),
1335 nonzero_bits (op
, GET_MODE (op
))))
1338 /* If operand is known to be only -1 or 0, convert ABS to NEG. */
1339 if (is_a
<scalar_int_mode
> (mode
, &int_mode
)
1340 && (num_sign_bit_copies (op
, int_mode
)
1341 == GET_MODE_PRECISION (int_mode
)))
1342 return gen_rtx_NEG (int_mode
, op
);
1347 /* (ffs (*_extend <X>)) = (ffs <X>) */
1348 if (GET_CODE (op
) == SIGN_EXTEND
1349 || GET_CODE (op
) == ZERO_EXTEND
)
1350 return simplify_gen_unary (FFS
, mode
, XEXP (op
, 0),
1351 GET_MODE (XEXP (op
, 0)));
1355 switch (GET_CODE (op
))
1359 /* (popcount (zero_extend <X>)) = (popcount <X>) */
1360 return simplify_gen_unary (POPCOUNT
, mode
, XEXP (op
, 0),
1361 GET_MODE (XEXP (op
, 0)));
1365 /* Rotations don't affect popcount. */
1366 if (!side_effects_p (XEXP (op
, 1)))
1367 return simplify_gen_unary (POPCOUNT
, mode
, XEXP (op
, 0),
1368 GET_MODE (XEXP (op
, 0)));
1377 switch (GET_CODE (op
))
1383 return simplify_gen_unary (PARITY
, mode
, XEXP (op
, 0),
1384 GET_MODE (XEXP (op
, 0)));
1388 /* Rotations don't affect parity. */
1389 if (!side_effects_p (XEXP (op
, 1)))
1390 return simplify_gen_unary (PARITY
, mode
, XEXP (op
, 0),
1391 GET_MODE (XEXP (op
, 0)));
1395 /* (parity (parity x)) -> parity (x). */
1404 /* (bswap (bswap x)) -> x. */
1405 if (GET_CODE (op
) == BSWAP
)
1406 return XEXP (op
, 0);
1410 /* (float (sign_extend <X>)) = (float <X>). */
1411 if (GET_CODE (op
) == SIGN_EXTEND
)
1412 return simplify_gen_unary (FLOAT
, mode
, XEXP (op
, 0),
1413 GET_MODE (XEXP (op
, 0)));
1417 /* (sign_extend (truncate (minus (label_ref L1) (label_ref L2))))
1418 becomes just the MINUS if its mode is MODE. This allows
1419 folding switch statements on machines using casesi (such as
1421 if (GET_CODE (op
) == TRUNCATE
1422 && GET_MODE (XEXP (op
, 0)) == mode
1423 && GET_CODE (XEXP (op
, 0)) == MINUS
1424 && GET_CODE (XEXP (XEXP (op
, 0), 0)) == LABEL_REF
1425 && GET_CODE (XEXP (XEXP (op
, 0), 1)) == LABEL_REF
)
1426 return XEXP (op
, 0);
1428 /* Extending a widening multiplication should be canonicalized to
1429 a wider widening multiplication. */
1430 if (GET_CODE (op
) == MULT
)
1432 rtx lhs
= XEXP (op
, 0);
1433 rtx rhs
= XEXP (op
, 1);
1434 enum rtx_code lcode
= GET_CODE (lhs
);
1435 enum rtx_code rcode
= GET_CODE (rhs
);
1437 /* Widening multiplies usually extend both operands, but sometimes
1438 they use a shift to extract a portion of a register. */
1439 if ((lcode
== SIGN_EXTEND
1440 || (lcode
== ASHIFTRT
&& CONST_INT_P (XEXP (lhs
, 1))))
1441 && (rcode
== SIGN_EXTEND
1442 || (rcode
== ASHIFTRT
&& CONST_INT_P (XEXP (rhs
, 1)))))
1444 machine_mode lmode
= GET_MODE (lhs
);
1445 machine_mode rmode
= GET_MODE (rhs
);
1448 if (lcode
== ASHIFTRT
)
1449 /* Number of bits not shifted off the end. */
1450 bits
= (GET_MODE_UNIT_PRECISION (lmode
)
1451 - INTVAL (XEXP (lhs
, 1)));
1452 else /* lcode == SIGN_EXTEND */
1453 /* Size of inner mode. */
1454 bits
= GET_MODE_UNIT_PRECISION (GET_MODE (XEXP (lhs
, 0)));
1456 if (rcode
== ASHIFTRT
)
1457 bits
+= (GET_MODE_UNIT_PRECISION (rmode
)
1458 - INTVAL (XEXP (rhs
, 1)));
1459 else /* rcode == SIGN_EXTEND */
1460 bits
+= GET_MODE_UNIT_PRECISION (GET_MODE (XEXP (rhs
, 0)));
1462 /* We can only widen multiplies if the result is mathematiclly
1463 equivalent. I.e. if overflow was impossible. */
1464 if (bits
<= GET_MODE_UNIT_PRECISION (GET_MODE (op
)))
1465 return simplify_gen_binary
1467 simplify_gen_unary (SIGN_EXTEND
, mode
, lhs
, lmode
),
1468 simplify_gen_unary (SIGN_EXTEND
, mode
, rhs
, rmode
));
1472 /* Check for a sign extension of a subreg of a promoted
1473 variable, where the promotion is sign-extended, and the
1474 target mode is the same as the variable's promotion. */
1475 if (GET_CODE (op
) == SUBREG
1476 && SUBREG_PROMOTED_VAR_P (op
)
1477 && SUBREG_PROMOTED_SIGNED_P (op
)
1478 && !paradoxical_subreg_p (mode
, GET_MODE (SUBREG_REG (op
))))
1480 temp
= rtl_hooks
.gen_lowpart_no_emit (mode
, SUBREG_REG (op
));
1485 /* (sign_extend:M (sign_extend:N <X>)) is (sign_extend:M <X>).
1486 (sign_extend:M (zero_extend:N <X>)) is (zero_extend:M <X>). */
1487 if (GET_CODE (op
) == SIGN_EXTEND
|| GET_CODE (op
) == ZERO_EXTEND
)
1489 gcc_assert (GET_MODE_UNIT_PRECISION (mode
)
1490 > GET_MODE_UNIT_PRECISION (GET_MODE (op
)));
1491 return simplify_gen_unary (GET_CODE (op
), mode
, XEXP (op
, 0),
1492 GET_MODE (XEXP (op
, 0)));
1495 /* (sign_extend:M (ashiftrt:N (ashift <X> (const_int I)) (const_int I)))
1496 is (sign_extend:M (subreg:O <X>)) if there is mode with
1497 GET_MODE_BITSIZE (N) - I bits.
1498 (sign_extend:M (lshiftrt:N (ashift <X> (const_int I)) (const_int I)))
1499 is similarly (zero_extend:M (subreg:O <X>)). */
1500 if ((GET_CODE (op
) == ASHIFTRT
|| GET_CODE (op
) == LSHIFTRT
)
1501 && GET_CODE (XEXP (op
, 0)) == ASHIFT
1502 && is_a
<scalar_int_mode
> (mode
, &int_mode
)
1503 && CONST_INT_P (XEXP (op
, 1))
1504 && XEXP (XEXP (op
, 0), 1) == XEXP (op
, 1)
1505 && (op_mode
= as_a
<scalar_int_mode
> (GET_MODE (op
)),
1506 GET_MODE_PRECISION (op_mode
) > INTVAL (XEXP (op
, 1))))
1508 scalar_int_mode tmode
;
1509 gcc_assert (GET_MODE_PRECISION (int_mode
)
1510 > GET_MODE_PRECISION (op_mode
));
1511 if (int_mode_for_size (GET_MODE_PRECISION (op_mode
)
1512 - INTVAL (XEXP (op
, 1)), 1).exists (&tmode
))
1515 rtl_hooks
.gen_lowpart_no_emit (tmode
, XEXP (XEXP (op
, 0), 0));
1517 return simplify_gen_unary (GET_CODE (op
) == ASHIFTRT
1518 ? SIGN_EXTEND
: ZERO_EXTEND
,
1519 int_mode
, inner
, tmode
);
1523 /* (sign_extend:M (lshiftrt:N <X> (const_int I))) is better as
1524 (zero_extend:M (lshiftrt:N <X> (const_int I))) if I is not 0. */
1525 if (GET_CODE (op
) == LSHIFTRT
1526 && CONST_INT_P (XEXP (op
, 1))
1527 && XEXP (op
, 1) != const0_rtx
)
1528 return simplify_gen_unary (ZERO_EXTEND
, mode
, op
, GET_MODE (op
));
1530 #if defined(POINTERS_EXTEND_UNSIGNED)
1531 /* As we do not know which address space the pointer is referring to,
1532 we can do this only if the target does not support different pointer
1533 or address modes depending on the address space. */
1534 if (target_default_pointer_address_modes_p ()
1535 && ! POINTERS_EXTEND_UNSIGNED
1536 && mode
== Pmode
&& GET_MODE (op
) == ptr_mode
1538 || (GET_CODE (op
) == SUBREG
1539 && REG_P (SUBREG_REG (op
))
1540 && REG_POINTER (SUBREG_REG (op
))
1541 && GET_MODE (SUBREG_REG (op
)) == Pmode
))
1542 && !targetm
.have_ptr_extend ())
1545 = convert_memory_address_addr_space_1 (Pmode
, op
,
1546 ADDR_SPACE_GENERIC
, false,
1555 /* Check for a zero extension of a subreg of a promoted
1556 variable, where the promotion is zero-extended, and the
1557 target mode is the same as the variable's promotion. */
1558 if (GET_CODE (op
) == SUBREG
1559 && SUBREG_PROMOTED_VAR_P (op
)
1560 && SUBREG_PROMOTED_UNSIGNED_P (op
)
1561 && !paradoxical_subreg_p (mode
, GET_MODE (SUBREG_REG (op
))))
1563 temp
= rtl_hooks
.gen_lowpart_no_emit (mode
, SUBREG_REG (op
));
1568 /* Extending a widening multiplication should be canonicalized to
1569 a wider widening multiplication. */
1570 if (GET_CODE (op
) == MULT
)
1572 rtx lhs
= XEXP (op
, 0);
1573 rtx rhs
= XEXP (op
, 1);
1574 enum rtx_code lcode
= GET_CODE (lhs
);
1575 enum rtx_code rcode
= GET_CODE (rhs
);
1577 /* Widening multiplies usually extend both operands, but sometimes
1578 they use a shift to extract a portion of a register. */
1579 if ((lcode
== ZERO_EXTEND
1580 || (lcode
== LSHIFTRT
&& CONST_INT_P (XEXP (lhs
, 1))))
1581 && (rcode
== ZERO_EXTEND
1582 || (rcode
== LSHIFTRT
&& CONST_INT_P (XEXP (rhs
, 1)))))
1584 machine_mode lmode
= GET_MODE (lhs
);
1585 machine_mode rmode
= GET_MODE (rhs
);
1588 if (lcode
== LSHIFTRT
)
1589 /* Number of bits not shifted off the end. */
1590 bits
= (GET_MODE_UNIT_PRECISION (lmode
)
1591 - INTVAL (XEXP (lhs
, 1)));
1592 else /* lcode == ZERO_EXTEND */
1593 /* Size of inner mode. */
1594 bits
= GET_MODE_UNIT_PRECISION (GET_MODE (XEXP (lhs
, 0)));
1596 if (rcode
== LSHIFTRT
)
1597 bits
+= (GET_MODE_UNIT_PRECISION (rmode
)
1598 - INTVAL (XEXP (rhs
, 1)));
1599 else /* rcode == ZERO_EXTEND */
1600 bits
+= GET_MODE_UNIT_PRECISION (GET_MODE (XEXP (rhs
, 0)));
1602 /* We can only widen multiplies if the result is mathematiclly
1603 equivalent. I.e. if overflow was impossible. */
1604 if (bits
<= GET_MODE_UNIT_PRECISION (GET_MODE (op
)))
1605 return simplify_gen_binary
1607 simplify_gen_unary (ZERO_EXTEND
, mode
, lhs
, lmode
),
1608 simplify_gen_unary (ZERO_EXTEND
, mode
, rhs
, rmode
));
1612 /* (zero_extend:M (zero_extend:N <X>)) is (zero_extend:M <X>). */
1613 if (GET_CODE (op
) == ZERO_EXTEND
)
1614 return simplify_gen_unary (ZERO_EXTEND
, mode
, XEXP (op
, 0),
1615 GET_MODE (XEXP (op
, 0)));
1617 /* (zero_extend:M (lshiftrt:N (ashift <X> (const_int I)) (const_int I)))
1618 is (zero_extend:M (subreg:O <X>)) if there is mode with
1619 GET_MODE_PRECISION (N) - I bits. */
1620 if (GET_CODE (op
) == LSHIFTRT
1621 && GET_CODE (XEXP (op
, 0)) == ASHIFT
1622 && is_a
<scalar_int_mode
> (mode
, &int_mode
)
1623 && CONST_INT_P (XEXP (op
, 1))
1624 && XEXP (XEXP (op
, 0), 1) == XEXP (op
, 1)
1625 && (op_mode
= as_a
<scalar_int_mode
> (GET_MODE (op
)),
1626 GET_MODE_PRECISION (op_mode
) > INTVAL (XEXP (op
, 1))))
1628 scalar_int_mode tmode
;
1629 if (int_mode_for_size (GET_MODE_PRECISION (op_mode
)
1630 - INTVAL (XEXP (op
, 1)), 1).exists (&tmode
))
1633 rtl_hooks
.gen_lowpart_no_emit (tmode
, XEXP (XEXP (op
, 0), 0));
1635 return simplify_gen_unary (ZERO_EXTEND
, int_mode
,
1640 /* (zero_extend:M (subreg:N <X:O>)) is <X:O> (for M == O) or
1641 (zero_extend:M <X:O>), if X doesn't have any non-zero bits outside
1643 (zero_extend:SI (subreg:QI (and:SI (reg:SI) (const_int 63)) 0)) is
1644 (and:SI (reg:SI) (const_int 63)). */
1645 if (partial_subreg_p (op
)
1646 && is_a
<scalar_int_mode
> (mode
, &int_mode
)
1647 && is_a
<scalar_int_mode
> (GET_MODE (SUBREG_REG (op
)), &op0_mode
)
1648 && GET_MODE_PRECISION (op0_mode
) <= HOST_BITS_PER_WIDE_INT
1649 && GET_MODE_PRECISION (int_mode
) >= GET_MODE_PRECISION (op0_mode
)
1650 && subreg_lowpart_p (op
)
1651 && (nonzero_bits (SUBREG_REG (op
), op0_mode
)
1652 & ~GET_MODE_MASK (GET_MODE (op
))) == 0)
1654 if (GET_MODE_PRECISION (int_mode
) == GET_MODE_PRECISION (op0_mode
))
1655 return SUBREG_REG (op
);
1656 return simplify_gen_unary (ZERO_EXTEND
, int_mode
, SUBREG_REG (op
),
1660 #if defined(POINTERS_EXTEND_UNSIGNED)
1661 /* As we do not know which address space the pointer is referring to,
1662 we can do this only if the target does not support different pointer
1663 or address modes depending on the address space. */
1664 if (target_default_pointer_address_modes_p ()
1665 && POINTERS_EXTEND_UNSIGNED
> 0
1666 && mode
== Pmode
&& GET_MODE (op
) == ptr_mode
1668 || (GET_CODE (op
) == SUBREG
1669 && REG_P (SUBREG_REG (op
))
1670 && REG_POINTER (SUBREG_REG (op
))
1671 && GET_MODE (SUBREG_REG (op
)) == Pmode
))
1672 && !targetm
.have_ptr_extend ())
1675 = convert_memory_address_addr_space_1 (Pmode
, op
,
1676 ADDR_SPACE_GENERIC
, false,
1688 if (VECTOR_MODE_P (mode
)
1689 && vec_duplicate_p (op
, &elt
)
1690 && code
!= VEC_DUPLICATE
)
1692 /* Try applying the operator to ELT and see if that simplifies.
1693 We can duplicate the result if so.
1695 The reason we don't use simplify_gen_unary is that it isn't
1696 necessarily a win to convert things like:
1698 (neg:V (vec_duplicate:V (reg:S R)))
1702 (vec_duplicate:V (neg:S (reg:S R)))
1704 The first might be done entirely in vector registers while the
1705 second might need a move between register files. */
1706 temp
= simplify_unary_operation (code
, GET_MODE_INNER (mode
),
1707 elt
, GET_MODE_INNER (GET_MODE (op
)));
1709 return gen_vec_duplicate (mode
, temp
);
1715 /* Try to compute the value of a unary operation CODE whose output mode is to
1716 be MODE with input operand OP whose mode was originally OP_MODE.
1717 Return zero if the value cannot be computed. */
1719 simplify_const_unary_operation (enum rtx_code code
, machine_mode mode
,
1720 rtx op
, machine_mode op_mode
)
1722 scalar_int_mode result_mode
;
1724 if (code
== VEC_DUPLICATE
)
1726 gcc_assert (VECTOR_MODE_P (mode
));
1727 if (GET_MODE (op
) != VOIDmode
)
1729 if (!VECTOR_MODE_P (GET_MODE (op
)))
1730 gcc_assert (GET_MODE_INNER (mode
) == GET_MODE (op
));
1732 gcc_assert (GET_MODE_INNER (mode
) == GET_MODE_INNER
1735 if (CONST_SCALAR_INT_P (op
) || CONST_DOUBLE_AS_FLOAT_P (op
))
1736 return gen_const_vec_duplicate (mode
, op
);
1737 if (GET_CODE (op
) == CONST_VECTOR
1738 && (CONST_VECTOR_DUPLICATE_P (op
)
1739 || CONST_VECTOR_NUNITS (op
).is_constant ()))
1741 unsigned int npatterns
= (CONST_VECTOR_DUPLICATE_P (op
)
1742 ? CONST_VECTOR_NPATTERNS (op
)
1743 : CONST_VECTOR_NUNITS (op
).to_constant ());
1744 gcc_assert (multiple_p (GET_MODE_NUNITS (mode
), npatterns
));
1745 rtx_vector_builder
builder (mode
, npatterns
, 1);
1746 for (unsigned i
= 0; i
< npatterns
; i
++)
1747 builder
.quick_push (CONST_VECTOR_ELT (op
, i
));
1748 return builder
.build ();
1752 if (VECTOR_MODE_P (mode
)
1753 && GET_CODE (op
) == CONST_VECTOR
1754 && known_eq (GET_MODE_NUNITS (mode
), CONST_VECTOR_NUNITS (op
)))
1756 gcc_assert (GET_MODE (op
) == op_mode
);
1758 rtx_vector_builder builder
;
1759 if (!builder
.new_unary_operation (mode
, op
, false))
1762 unsigned int count
= builder
.encoded_nelts ();
1763 for (unsigned int i
= 0; i
< count
; i
++)
1765 rtx x
= simplify_unary_operation (code
, GET_MODE_INNER (mode
),
1766 CONST_VECTOR_ELT (op
, i
),
1767 GET_MODE_INNER (op_mode
));
1768 if (!x
|| !valid_for_const_vector_p (mode
, x
))
1770 builder
.quick_push (x
);
1772 return builder
.build ();
1775 /* The order of these tests is critical so that, for example, we don't
1776 check the wrong mode (input vs. output) for a conversion operation,
1777 such as FIX. At some point, this should be simplified. */
1779 if (code
== FLOAT
&& CONST_SCALAR_INT_P (op
))
1783 if (op_mode
== VOIDmode
)
1785 /* CONST_INT have VOIDmode as the mode. We assume that all
1786 the bits of the constant are significant, though, this is
1787 a dangerous assumption as many times CONST_INTs are
1788 created and used with garbage in the bits outside of the
1789 precision of the implied mode of the const_int. */
1790 op_mode
= MAX_MODE_INT
;
1793 real_from_integer (&d
, mode
, rtx_mode_t (op
, op_mode
), SIGNED
);
1795 /* Avoid the folding if flag_signaling_nans is on and
1796 operand is a signaling NaN. */
1797 if (HONOR_SNANS (mode
) && REAL_VALUE_ISSIGNALING_NAN (d
))
1800 d
= real_value_truncate (mode
, d
);
1801 return const_double_from_real_value (d
, mode
);
1803 else if (code
== UNSIGNED_FLOAT
&& CONST_SCALAR_INT_P (op
))
1807 if (op_mode
== VOIDmode
)
1809 /* CONST_INT have VOIDmode as the mode. We assume that all
1810 the bits of the constant are significant, though, this is
1811 a dangerous assumption as many times CONST_INTs are
1812 created and used with garbage in the bits outside of the
1813 precision of the implied mode of the const_int. */
1814 op_mode
= MAX_MODE_INT
;
1817 real_from_integer (&d
, mode
, rtx_mode_t (op
, op_mode
), UNSIGNED
);
1819 /* Avoid the folding if flag_signaling_nans is on and
1820 operand is a signaling NaN. */
1821 if (HONOR_SNANS (mode
) && REAL_VALUE_ISSIGNALING_NAN (d
))
1824 d
= real_value_truncate (mode
, d
);
1825 return const_double_from_real_value (d
, mode
);
1828 if (CONST_SCALAR_INT_P (op
) && is_a
<scalar_int_mode
> (mode
, &result_mode
))
1830 unsigned int width
= GET_MODE_PRECISION (result_mode
);
1831 if (width
> MAX_BITSIZE_MODE_ANY_INT
)
1835 scalar_int_mode imode
= (op_mode
== VOIDmode
1837 : as_a
<scalar_int_mode
> (op_mode
));
1838 rtx_mode_t op0
= rtx_mode_t (op
, imode
);
1841 #if TARGET_SUPPORTS_WIDE_INT == 0
1842 /* This assert keeps the simplification from producing a result
1843 that cannot be represented in a CONST_DOUBLE but a lot of
1844 upstream callers expect that this function never fails to
1845 simplify something and so you if you added this to the test
1846 above the code would die later anyway. If this assert
1847 happens, you just need to make the port support wide int. */
1848 gcc_assert (width
<= HOST_BITS_PER_DOUBLE_INT
);
1854 result
= wi::bit_not (op0
);
1858 result
= wi::neg (op0
);
1862 result
= wi::abs (op0
);
1866 result
= wi::shwi (wi::ffs (op0
), result_mode
);
1870 if (wi::ne_p (op0
, 0))
1871 int_value
= wi::clz (op0
);
1872 else if (! CLZ_DEFINED_VALUE_AT_ZERO (imode
, int_value
))
1874 result
= wi::shwi (int_value
, result_mode
);
1878 result
= wi::shwi (wi::clrsb (op0
), result_mode
);
1882 if (wi::ne_p (op0
, 0))
1883 int_value
= wi::ctz (op0
);
1884 else if (! CTZ_DEFINED_VALUE_AT_ZERO (imode
, int_value
))
1886 result
= wi::shwi (int_value
, result_mode
);
1890 result
= wi::shwi (wi::popcount (op0
), result_mode
);
1894 result
= wi::shwi (wi::parity (op0
), result_mode
);
1898 result
= wide_int (op0
).bswap ();
1903 result
= wide_int::from (op0
, width
, UNSIGNED
);
1907 result
= wide_int::from (op0
, width
, SIGNED
);
1915 return immed_wide_int_const (result
, result_mode
);
1918 else if (CONST_DOUBLE_AS_FLOAT_P (op
)
1919 && SCALAR_FLOAT_MODE_P (mode
)
1920 && SCALAR_FLOAT_MODE_P (GET_MODE (op
)))
1922 REAL_VALUE_TYPE d
= *CONST_DOUBLE_REAL_VALUE (op
);
1928 d
= real_value_abs (&d
);
1931 d
= real_value_negate (&d
);
1933 case FLOAT_TRUNCATE
:
1934 /* Don't perform the operation if flag_signaling_nans is on
1935 and the operand is a signaling NaN. */
1936 if (HONOR_SNANS (mode
) && REAL_VALUE_ISSIGNALING_NAN (d
))
1938 d
= real_value_truncate (mode
, d
);
1941 /* Don't perform the operation if flag_signaling_nans is on
1942 and the operand is a signaling NaN. */
1943 if (HONOR_SNANS (mode
) && REAL_VALUE_ISSIGNALING_NAN (d
))
1945 /* All this does is change the mode, unless changing
1947 if (GET_MODE_CLASS (mode
) != GET_MODE_CLASS (GET_MODE (op
)))
1948 real_convert (&d
, mode
, &d
);
1951 /* Don't perform the operation if flag_signaling_nans is on
1952 and the operand is a signaling NaN. */
1953 if (HONOR_SNANS (mode
) && REAL_VALUE_ISSIGNALING_NAN (d
))
1955 real_arithmetic (&d
, FIX_TRUNC_EXPR
, &d
, NULL
);
1962 real_to_target (tmp
, &d
, GET_MODE (op
));
1963 for (i
= 0; i
< 4; i
++)
1965 real_from_target (&d
, tmp
, mode
);
1971 return const_double_from_real_value (d
, mode
);
1973 else if (CONST_DOUBLE_AS_FLOAT_P (op
)
1974 && SCALAR_FLOAT_MODE_P (GET_MODE (op
))
1975 && is_int_mode (mode
, &result_mode
))
1977 unsigned int width
= GET_MODE_PRECISION (result_mode
);
1978 if (width
> MAX_BITSIZE_MODE_ANY_INT
)
1981 /* Although the overflow semantics of RTL's FIX and UNSIGNED_FIX
1982 operators are intentionally left unspecified (to ease implementation
1983 by target backends), for consistency, this routine implements the
1984 same semantics for constant folding as used by the middle-end. */
1986 /* This was formerly used only for non-IEEE float.
1987 eggert@twinsun.com says it is safe for IEEE also. */
1989 const REAL_VALUE_TYPE
*x
= CONST_DOUBLE_REAL_VALUE (op
);
1990 wide_int wmax
, wmin
;
1991 /* This is part of the abi to real_to_integer, but we check
1992 things before making this call. */
1998 if (REAL_VALUE_ISNAN (*x
))
2001 /* Test against the signed upper bound. */
2002 wmax
= wi::max_value (width
, SIGNED
);
2003 real_from_integer (&t
, VOIDmode
, wmax
, SIGNED
);
2004 if (real_less (&t
, x
))
2005 return immed_wide_int_const (wmax
, mode
);
2007 /* Test against the signed lower bound. */
2008 wmin
= wi::min_value (width
, SIGNED
);
2009 real_from_integer (&t
, VOIDmode
, wmin
, SIGNED
);
2010 if (real_less (x
, &t
))
2011 return immed_wide_int_const (wmin
, mode
);
2013 return immed_wide_int_const (real_to_integer (x
, &fail
, width
),
2017 if (REAL_VALUE_ISNAN (*x
) || REAL_VALUE_NEGATIVE (*x
))
2020 /* Test against the unsigned upper bound. */
2021 wmax
= wi::max_value (width
, UNSIGNED
);
2022 real_from_integer (&t
, VOIDmode
, wmax
, UNSIGNED
);
2023 if (real_less (&t
, x
))
2024 return immed_wide_int_const (wmax
, mode
);
2026 return immed_wide_int_const (real_to_integer (x
, &fail
, width
),
2034 /* Handle polynomial integers. */
2035 else if (CONST_POLY_INT_P (op
))
2037 poly_wide_int result
;
2041 result
= -const_poly_int_value (op
);
2045 result
= ~const_poly_int_value (op
);
2051 return immed_wide_int_const (result
, mode
);
2057 /* Subroutine of simplify_binary_operation to simplify a binary operation
2058 CODE that can commute with byte swapping, with result mode MODE and
2059 operating on OP0 and OP1. CODE is currently one of AND, IOR or XOR.
2060 Return zero if no simplification or canonicalization is possible. */
2063 simplify_byte_swapping_operation (enum rtx_code code
, machine_mode mode
,
2068 /* (op (bswap x) C1)) -> (bswap (op x C2)) with C2 swapped. */
2069 if (GET_CODE (op0
) == BSWAP
&& CONST_SCALAR_INT_P (op1
))
2071 tem
= simplify_gen_binary (code
, mode
, XEXP (op0
, 0),
2072 simplify_gen_unary (BSWAP
, mode
, op1
, mode
));
2073 return simplify_gen_unary (BSWAP
, mode
, tem
, mode
);
2076 /* (op (bswap x) (bswap y)) -> (bswap (op x y)). */
2077 if (GET_CODE (op0
) == BSWAP
&& GET_CODE (op1
) == BSWAP
)
2079 tem
= simplify_gen_binary (code
, mode
, XEXP (op0
, 0), XEXP (op1
, 0));
2080 return simplify_gen_unary (BSWAP
, mode
, tem
, mode
);
2086 /* Subroutine of simplify_binary_operation to simplify a commutative,
2087 associative binary operation CODE with result mode MODE, operating
2088 on OP0 and OP1. CODE is currently one of PLUS, MULT, AND, IOR, XOR,
2089 SMIN, SMAX, UMIN or UMAX. Return zero if no simplification or
2090 canonicalization is possible. */
2093 simplify_associative_operation (enum rtx_code code
, machine_mode mode
,
2098 /* Linearize the operator to the left. */
2099 if (GET_CODE (op1
) == code
)
2101 /* "(a op b) op (c op d)" becomes "((a op b) op c) op d)". */
2102 if (GET_CODE (op0
) == code
)
2104 tem
= simplify_gen_binary (code
, mode
, op0
, XEXP (op1
, 0));
2105 return simplify_gen_binary (code
, mode
, tem
, XEXP (op1
, 1));
2108 /* "a op (b op c)" becomes "(b op c) op a". */
2109 if (! swap_commutative_operands_p (op1
, op0
))
2110 return simplify_gen_binary (code
, mode
, op1
, op0
);
2112 std::swap (op0
, op1
);
2115 if (GET_CODE (op0
) == code
)
2117 /* Canonicalize "(x op c) op y" as "(x op y) op c". */
2118 if (swap_commutative_operands_p (XEXP (op0
, 1), op1
))
2120 tem
= simplify_gen_binary (code
, mode
, XEXP (op0
, 0), op1
);
2121 return simplify_gen_binary (code
, mode
, tem
, XEXP (op0
, 1));
2124 /* Attempt to simplify "(a op b) op c" as "a op (b op c)". */
2125 tem
= simplify_binary_operation (code
, mode
, XEXP (op0
, 1), op1
);
2127 return simplify_gen_binary (code
, mode
, XEXP (op0
, 0), tem
);
2129 /* Attempt to simplify "(a op b) op c" as "(a op c) op b". */
2130 tem
= simplify_binary_operation (code
, mode
, XEXP (op0
, 0), op1
);
2132 return simplify_gen_binary (code
, mode
, tem
, XEXP (op0
, 1));
2138 /* Return a mask describing the COMPARISON. */
2140 comparison_to_mask (enum rtx_code comparison
)
2180 /* Return a comparison corresponding to the MASK. */
2181 static enum rtx_code
2182 mask_to_comparison (int mask
)
2222 /* Return true if CODE is valid for comparisons of mode MODE, false
2225 It is always safe to return false, even if the code was valid for the
2226 given mode as that will merely suppress optimizations. */
2229 comparison_code_valid_for_mode (enum rtx_code code
, enum machine_mode mode
)
2233 /* These are valid for integral, floating and vector modes. */
2240 return (INTEGRAL_MODE_P (mode
)
2241 || FLOAT_MODE_P (mode
)
2242 || VECTOR_MODE_P (mode
));
2244 /* These are valid for floating point modes. */
2253 return FLOAT_MODE_P (mode
);
2255 /* These are filtered out in simplify_logical_operation, but
2256 we check for them too as a matter of safety. They are valid
2257 for integral and vector modes. */
2262 return INTEGRAL_MODE_P (mode
) || VECTOR_MODE_P (mode
);
2269 /* Simplify a logical operation CODE with result mode MODE, operating on OP0
2270 and OP1, which should be both relational operations. Return 0 if no such
2271 simplification is possible. */
2273 simplify_logical_relational_operation (enum rtx_code code
, machine_mode mode
,
2276 /* We only handle IOR of two relational operations. */
2280 if (!(COMPARISON_P (op0
) && COMPARISON_P (op1
)))
2283 if (!(rtx_equal_p (XEXP (op0
, 0), XEXP (op1
, 0))
2284 && rtx_equal_p (XEXP (op0
, 1), XEXP (op1
, 1))))
2287 enum rtx_code code0
= GET_CODE (op0
);
2288 enum rtx_code code1
= GET_CODE (op1
);
2290 /* We don't handle unsigned comparisons currently. */
2291 if (code0
== LTU
|| code0
== GTU
|| code0
== LEU
|| code0
== GEU
)
2293 if (code1
== LTU
|| code1
== GTU
|| code1
== LEU
|| code1
== GEU
)
2296 int mask0
= comparison_to_mask (code0
);
2297 int mask1
= comparison_to_mask (code1
);
2299 int mask
= mask0
| mask1
;
2302 return const_true_rtx
;
2304 code
= mask_to_comparison (mask
);
2306 /* Many comparison codes are only valid for certain mode classes. */
2307 if (!comparison_code_valid_for_mode (code
, mode
))
2310 op0
= XEXP (op1
, 0);
2311 op1
= XEXP (op1
, 1);
2313 return simplify_gen_relational (code
, mode
, VOIDmode
, op0
, op1
);
2316 /* Simplify a binary operation CODE with result mode MODE, operating on OP0
2317 and OP1. Return 0 if no simplification is possible.
2319 Don't use this for relational operations such as EQ or LT.
2320 Use simplify_relational_operation instead. */
2322 simplify_binary_operation (enum rtx_code code
, machine_mode mode
,
2325 rtx trueop0
, trueop1
;
2328 /* Relational operations don't work here. We must know the mode
2329 of the operands in order to do the comparison correctly.
2330 Assuming a full word can give incorrect results.
2331 Consider comparing 128 with -128 in QImode. */
2332 gcc_assert (GET_RTX_CLASS (code
) != RTX_COMPARE
);
2333 gcc_assert (GET_RTX_CLASS (code
) != RTX_COMM_COMPARE
);
2335 /* Make sure the constant is second. */
2336 if (GET_RTX_CLASS (code
) == RTX_COMM_ARITH
2337 && swap_commutative_operands_p (op0
, op1
))
2338 std::swap (op0
, op1
);
2340 trueop0
= avoid_constant_pool_reference (op0
);
2341 trueop1
= avoid_constant_pool_reference (op1
);
2343 tem
= simplify_const_binary_operation (code
, mode
, trueop0
, trueop1
);
2346 tem
= simplify_binary_operation_1 (code
, mode
, op0
, op1
, trueop0
, trueop1
);
2351 /* If the above steps did not result in a simplification and op0 or op1
2352 were constant pool references, use the referenced constants directly. */
2353 if (trueop0
!= op0
|| trueop1
!= op1
)
2354 return simplify_gen_binary (code
, mode
, trueop0
, trueop1
);
2359 /* Subroutine of simplify_binary_operation_1 that looks for cases in
2360 which OP0 and OP1 are both vector series or vector duplicates
2361 (which are really just series with a step of 0). If so, try to
2362 form a new series by applying CODE to the bases and to the steps.
2363 Return null if no simplification is possible.
2365 MODE is the mode of the operation and is known to be a vector
2369 simplify_binary_operation_series (rtx_code code
, machine_mode mode
,
2373 if (vec_duplicate_p (op0
, &base0
))
2375 else if (!vec_series_p (op0
, &base0
, &step0
))
2379 if (vec_duplicate_p (op1
, &base1
))
2381 else if (!vec_series_p (op1
, &base1
, &step1
))
2384 /* Only create a new series if we can simplify both parts. In other
2385 cases this isn't really a simplification, and it's not necessarily
2386 a win to replace a vector operation with a scalar operation. */
2387 scalar_mode inner_mode
= GET_MODE_INNER (mode
);
2388 rtx new_base
= simplify_binary_operation (code
, inner_mode
, base0
, base1
);
2392 rtx new_step
= simplify_binary_operation (code
, inner_mode
, step0
, step1
);
2396 return gen_vec_series (mode
, new_base
, new_step
);
2399 /* Subroutine of simplify_binary_operation. Simplify a binary operation
2400 CODE with result mode MODE, operating on OP0 and OP1. If OP0 and/or
2401 OP1 are constant pool references, TRUEOP0 and TRUEOP1 represent the
2402 actual constants. */
2405 simplify_binary_operation_1 (enum rtx_code code
, machine_mode mode
,
2406 rtx op0
, rtx op1
, rtx trueop0
, rtx trueop1
)
2408 rtx tem
, reversed
, opleft
, opright
, elt0
, elt1
;
2410 scalar_int_mode int_mode
, inner_mode
;
2413 /* Even if we can't compute a constant result,
2414 there are some cases worth simplifying. */
2419 /* Maybe simplify x + 0 to x. The two expressions are equivalent
2420 when x is NaN, infinite, or finite and nonzero. They aren't
2421 when x is -0 and the rounding mode is not towards -infinity,
2422 since (-0) + 0 is then 0. */
2423 if (!HONOR_SIGNED_ZEROS (mode
) && trueop1
== CONST0_RTX (mode
))
2426 /* ((-a) + b) -> (b - a) and similarly for (a + (-b)). These
2427 transformations are safe even for IEEE. */
2428 if (GET_CODE (op0
) == NEG
)
2429 return simplify_gen_binary (MINUS
, mode
, op1
, XEXP (op0
, 0));
2430 else if (GET_CODE (op1
) == NEG
)
2431 return simplify_gen_binary (MINUS
, mode
, op0
, XEXP (op1
, 0));
2433 /* (~a) + 1 -> -a */
2434 if (INTEGRAL_MODE_P (mode
)
2435 && GET_CODE (op0
) == NOT
2436 && trueop1
== const1_rtx
)
2437 return simplify_gen_unary (NEG
, mode
, XEXP (op0
, 0), mode
);
2439 /* Handle both-operands-constant cases. We can only add
2440 CONST_INTs to constants since the sum of relocatable symbols
2441 can't be handled by most assemblers. Don't add CONST_INT
2442 to CONST_INT since overflow won't be computed properly if wider
2443 than HOST_BITS_PER_WIDE_INT. */
2445 if ((GET_CODE (op0
) == CONST
2446 || GET_CODE (op0
) == SYMBOL_REF
2447 || GET_CODE (op0
) == LABEL_REF
)
2448 && poly_int_rtx_p (op1
, &offset
))
2449 return plus_constant (mode
, op0
, offset
);
2450 else if ((GET_CODE (op1
) == CONST
2451 || GET_CODE (op1
) == SYMBOL_REF
2452 || GET_CODE (op1
) == LABEL_REF
)
2453 && poly_int_rtx_p (op0
, &offset
))
2454 return plus_constant (mode
, op1
, offset
);
2456 /* See if this is something like X * C - X or vice versa or
2457 if the multiplication is written as a shift. If so, we can
2458 distribute and make a new multiply, shift, or maybe just
2459 have X (if C is 2 in the example above). But don't make
2460 something more expensive than we had before. */
2462 if (is_a
<scalar_int_mode
> (mode
, &int_mode
))
2464 rtx lhs
= op0
, rhs
= op1
;
2466 wide_int coeff0
= wi::one (GET_MODE_PRECISION (int_mode
));
2467 wide_int coeff1
= wi::one (GET_MODE_PRECISION (int_mode
));
2469 if (GET_CODE (lhs
) == NEG
)
2471 coeff0
= wi::minus_one (GET_MODE_PRECISION (int_mode
));
2472 lhs
= XEXP (lhs
, 0);
2474 else if (GET_CODE (lhs
) == MULT
2475 && CONST_SCALAR_INT_P (XEXP (lhs
, 1)))
2477 coeff0
= rtx_mode_t (XEXP (lhs
, 1), int_mode
);
2478 lhs
= XEXP (lhs
, 0);
2480 else if (GET_CODE (lhs
) == ASHIFT
2481 && CONST_INT_P (XEXP (lhs
, 1))
2482 && INTVAL (XEXP (lhs
, 1)) >= 0
2483 && INTVAL (XEXP (lhs
, 1)) < GET_MODE_PRECISION (int_mode
))
2485 coeff0
= wi::set_bit_in_zero (INTVAL (XEXP (lhs
, 1)),
2486 GET_MODE_PRECISION (int_mode
));
2487 lhs
= XEXP (lhs
, 0);
2490 if (GET_CODE (rhs
) == NEG
)
2492 coeff1
= wi::minus_one (GET_MODE_PRECISION (int_mode
));
2493 rhs
= XEXP (rhs
, 0);
2495 else if (GET_CODE (rhs
) == MULT
2496 && CONST_INT_P (XEXP (rhs
, 1)))
2498 coeff1
= rtx_mode_t (XEXP (rhs
, 1), int_mode
);
2499 rhs
= XEXP (rhs
, 0);
2501 else if (GET_CODE (rhs
) == ASHIFT
2502 && CONST_INT_P (XEXP (rhs
, 1))
2503 && INTVAL (XEXP (rhs
, 1)) >= 0
2504 && INTVAL (XEXP (rhs
, 1)) < GET_MODE_PRECISION (int_mode
))
2506 coeff1
= wi::set_bit_in_zero (INTVAL (XEXP (rhs
, 1)),
2507 GET_MODE_PRECISION (int_mode
));
2508 rhs
= XEXP (rhs
, 0);
2511 if (rtx_equal_p (lhs
, rhs
))
2513 rtx orig
= gen_rtx_PLUS (int_mode
, op0
, op1
);
2515 bool speed
= optimize_function_for_speed_p (cfun
);
2517 coeff
= immed_wide_int_const (coeff0
+ coeff1
, int_mode
);
2519 tem
= simplify_gen_binary (MULT
, int_mode
, lhs
, coeff
);
2520 return (set_src_cost (tem
, int_mode
, speed
)
2521 <= set_src_cost (orig
, int_mode
, speed
) ? tem
: 0);
2525 /* (plus (xor X C1) C2) is (xor X (C1^C2)) if C2 is signbit. */
2526 if (CONST_SCALAR_INT_P (op1
)
2527 && GET_CODE (op0
) == XOR
2528 && CONST_SCALAR_INT_P (XEXP (op0
, 1))
2529 && mode_signbit_p (mode
, op1
))
2530 return simplify_gen_binary (XOR
, mode
, XEXP (op0
, 0),
2531 simplify_gen_binary (XOR
, mode
, op1
,
2534 /* Canonicalize (plus (mult (neg B) C) A) to (minus A (mult B C)). */
2535 if (!HONOR_SIGN_DEPENDENT_ROUNDING (mode
)
2536 && GET_CODE (op0
) == MULT
2537 && GET_CODE (XEXP (op0
, 0)) == NEG
)
2541 in1
= XEXP (XEXP (op0
, 0), 0);
2542 in2
= XEXP (op0
, 1);
2543 return simplify_gen_binary (MINUS
, mode
, op1
,
2544 simplify_gen_binary (MULT
, mode
,
2548 /* (plus (comparison A B) C) can become (neg (rev-comp A B)) if
2549 C is 1 and STORE_FLAG_VALUE is -1 or if C is -1 and STORE_FLAG_VALUE
2551 if (COMPARISON_P (op0
)
2552 && ((STORE_FLAG_VALUE
== -1 && trueop1
== const1_rtx
)
2553 || (STORE_FLAG_VALUE
== 1 && trueop1
== constm1_rtx
))
2554 && (reversed
= reversed_comparison (op0
, mode
)))
2556 simplify_gen_unary (NEG
, mode
, reversed
, mode
);
2558 /* If one of the operands is a PLUS or a MINUS, see if we can
2559 simplify this by the associative law.
2560 Don't use the associative law for floating point.
2561 The inaccuracy makes it nonassociative,
2562 and subtle programs can break if operations are associated. */
2564 if (INTEGRAL_MODE_P (mode
)
2565 && (plus_minus_operand_p (op0
)
2566 || plus_minus_operand_p (op1
))
2567 && (tem
= simplify_plus_minus (code
, mode
, op0
, op1
)) != 0)
2570 /* Reassociate floating point addition only when the user
2571 specifies associative math operations. */
2572 if (FLOAT_MODE_P (mode
)
2573 && flag_associative_math
)
2575 tem
= simplify_associative_operation (code
, mode
, op0
, op1
);
2580 /* Handle vector series. */
2581 if (GET_MODE_CLASS (mode
) == MODE_VECTOR_INT
)
2583 tem
= simplify_binary_operation_series (code
, mode
, op0
, op1
);
2590 /* Convert (compare (gt (flags) 0) (lt (flags) 0)) to (flags). */
2591 if (((GET_CODE (op0
) == GT
&& GET_CODE (op1
) == LT
)
2592 || (GET_CODE (op0
) == GTU
&& GET_CODE (op1
) == LTU
))
2593 && XEXP (op0
, 1) == const0_rtx
&& XEXP (op1
, 1) == const0_rtx
)
2595 rtx xop00
= XEXP (op0
, 0);
2596 rtx xop10
= XEXP (op1
, 0);
2598 if (GET_CODE (xop00
) == CC0
&& GET_CODE (xop10
) == CC0
)
2601 if (REG_P (xop00
) && REG_P (xop10
)
2602 && REGNO (xop00
) == REGNO (xop10
)
2603 && GET_MODE (xop00
) == mode
2604 && GET_MODE (xop10
) == mode
2605 && GET_MODE_CLASS (mode
) == MODE_CC
)
2611 /* We can't assume x-x is 0 even with non-IEEE floating point,
2612 but since it is zero except in very strange circumstances, we
2613 will treat it as zero with -ffinite-math-only. */
2614 if (rtx_equal_p (trueop0
, trueop1
)
2615 && ! side_effects_p (op0
)
2616 && (!FLOAT_MODE_P (mode
) || !HONOR_NANS (mode
)))
2617 return CONST0_RTX (mode
);
2619 /* Change subtraction from zero into negation. (0 - x) is the
2620 same as -x when x is NaN, infinite, or finite and nonzero.
2621 But if the mode has signed zeros, and does not round towards
2622 -infinity, then 0 - 0 is 0, not -0. */
2623 if (!HONOR_SIGNED_ZEROS (mode
) && trueop0
== CONST0_RTX (mode
))
2624 return simplify_gen_unary (NEG
, mode
, op1
, mode
);
2626 /* (-1 - a) is ~a, unless the expression contains symbolic
2627 constants, in which case not retaining additions and
2628 subtractions could cause invalid assembly to be produced. */
2629 if (trueop0
== constm1_rtx
2630 && !contains_symbolic_reference_p (op1
))
2631 return simplify_gen_unary (NOT
, mode
, op1
, mode
);
2633 /* Subtracting 0 has no effect unless the mode has signed zeros
2634 and supports rounding towards -infinity. In such a case,
2636 if (!(HONOR_SIGNED_ZEROS (mode
)
2637 && HONOR_SIGN_DEPENDENT_ROUNDING (mode
))
2638 && trueop1
== CONST0_RTX (mode
))
2641 /* See if this is something like X * C - X or vice versa or
2642 if the multiplication is written as a shift. If so, we can
2643 distribute and make a new multiply, shift, or maybe just
2644 have X (if C is 2 in the example above). But don't make
2645 something more expensive than we had before. */
2647 if (is_a
<scalar_int_mode
> (mode
, &int_mode
))
2649 rtx lhs
= op0
, rhs
= op1
;
2651 wide_int coeff0
= wi::one (GET_MODE_PRECISION (int_mode
));
2652 wide_int negcoeff1
= wi::minus_one (GET_MODE_PRECISION (int_mode
));
2654 if (GET_CODE (lhs
) == NEG
)
2656 coeff0
= wi::minus_one (GET_MODE_PRECISION (int_mode
));
2657 lhs
= XEXP (lhs
, 0);
2659 else if (GET_CODE (lhs
) == MULT
2660 && CONST_SCALAR_INT_P (XEXP (lhs
, 1)))
2662 coeff0
= rtx_mode_t (XEXP (lhs
, 1), int_mode
);
2663 lhs
= XEXP (lhs
, 0);
2665 else if (GET_CODE (lhs
) == ASHIFT
2666 && CONST_INT_P (XEXP (lhs
, 1))
2667 && INTVAL (XEXP (lhs
, 1)) >= 0
2668 && INTVAL (XEXP (lhs
, 1)) < GET_MODE_PRECISION (int_mode
))
2670 coeff0
= wi::set_bit_in_zero (INTVAL (XEXP (lhs
, 1)),
2671 GET_MODE_PRECISION (int_mode
));
2672 lhs
= XEXP (lhs
, 0);
2675 if (GET_CODE (rhs
) == NEG
)
2677 negcoeff1
= wi::one (GET_MODE_PRECISION (int_mode
));
2678 rhs
= XEXP (rhs
, 0);
2680 else if (GET_CODE (rhs
) == MULT
2681 && CONST_INT_P (XEXP (rhs
, 1)))
2683 negcoeff1
= wi::neg (rtx_mode_t (XEXP (rhs
, 1), int_mode
));
2684 rhs
= XEXP (rhs
, 0);
2686 else if (GET_CODE (rhs
) == ASHIFT
2687 && CONST_INT_P (XEXP (rhs
, 1))
2688 && INTVAL (XEXP (rhs
, 1)) >= 0
2689 && INTVAL (XEXP (rhs
, 1)) < GET_MODE_PRECISION (int_mode
))
2691 negcoeff1
= wi::set_bit_in_zero (INTVAL (XEXP (rhs
, 1)),
2692 GET_MODE_PRECISION (int_mode
));
2693 negcoeff1
= -negcoeff1
;
2694 rhs
= XEXP (rhs
, 0);
2697 if (rtx_equal_p (lhs
, rhs
))
2699 rtx orig
= gen_rtx_MINUS (int_mode
, op0
, op1
);
2701 bool speed
= optimize_function_for_speed_p (cfun
);
2703 coeff
= immed_wide_int_const (coeff0
+ negcoeff1
, int_mode
);
2705 tem
= simplify_gen_binary (MULT
, int_mode
, lhs
, coeff
);
2706 return (set_src_cost (tem
, int_mode
, speed
)
2707 <= set_src_cost (orig
, int_mode
, speed
) ? tem
: 0);
2711 /* (a - (-b)) -> (a + b). True even for IEEE. */
2712 if (GET_CODE (op1
) == NEG
)
2713 return simplify_gen_binary (PLUS
, mode
, op0
, XEXP (op1
, 0));
2715 /* (-x - c) may be simplified as (-c - x). */
2716 if (GET_CODE (op0
) == NEG
2717 && (CONST_SCALAR_INT_P (op1
) || CONST_DOUBLE_AS_FLOAT_P (op1
)))
2719 tem
= simplify_unary_operation (NEG
, mode
, op1
, mode
);
2721 return simplify_gen_binary (MINUS
, mode
, tem
, XEXP (op0
, 0));
2724 if ((GET_CODE (op0
) == CONST
2725 || GET_CODE (op0
) == SYMBOL_REF
2726 || GET_CODE (op0
) == LABEL_REF
)
2727 && poly_int_rtx_p (op1
, &offset
))
2728 return plus_constant (mode
, op0
, trunc_int_for_mode (-offset
, mode
));
2730 /* Don't let a relocatable value get a negative coeff. */
2731 if (poly_int_rtx_p (op1
) && GET_MODE (op0
) != VOIDmode
)
2732 return simplify_gen_binary (PLUS
, mode
,
2734 neg_poly_int_rtx (mode
, op1
));
2736 /* (x - (x & y)) -> (x & ~y) */
2737 if (INTEGRAL_MODE_P (mode
) && GET_CODE (op1
) == AND
)
2739 if (rtx_equal_p (op0
, XEXP (op1
, 0)))
2741 tem
= simplify_gen_unary (NOT
, mode
, XEXP (op1
, 1),
2742 GET_MODE (XEXP (op1
, 1)));
2743 return simplify_gen_binary (AND
, mode
, op0
, tem
);
2745 if (rtx_equal_p (op0
, XEXP (op1
, 1)))
2747 tem
= simplify_gen_unary (NOT
, mode
, XEXP (op1
, 0),
2748 GET_MODE (XEXP (op1
, 0)));
2749 return simplify_gen_binary (AND
, mode
, op0
, tem
);
2753 /* If STORE_FLAG_VALUE is 1, (minus 1 (comparison foo bar)) can be done
2754 by reversing the comparison code if valid. */
2755 if (STORE_FLAG_VALUE
== 1
2756 && trueop0
== const1_rtx
2757 && COMPARISON_P (op1
)
2758 && (reversed
= reversed_comparison (op1
, mode
)))
2761 /* Canonicalize (minus A (mult (neg B) C)) to (plus (mult B C) A). */
2762 if (!HONOR_SIGN_DEPENDENT_ROUNDING (mode
)
2763 && GET_CODE (op1
) == MULT
2764 && GET_CODE (XEXP (op1
, 0)) == NEG
)
2768 in1
= XEXP (XEXP (op1
, 0), 0);
2769 in2
= XEXP (op1
, 1);
2770 return simplify_gen_binary (PLUS
, mode
,
2771 simplify_gen_binary (MULT
, mode
,
2776 /* Canonicalize (minus (neg A) (mult B C)) to
2777 (minus (mult (neg B) C) A). */
2778 if (!HONOR_SIGN_DEPENDENT_ROUNDING (mode
)
2779 && GET_CODE (op1
) == MULT
2780 && GET_CODE (op0
) == NEG
)
2784 in1
= simplify_gen_unary (NEG
, mode
, XEXP (op1
, 0), mode
);
2785 in2
= XEXP (op1
, 1);
2786 return simplify_gen_binary (MINUS
, mode
,
2787 simplify_gen_binary (MULT
, mode
,
2792 /* If one of the operands is a PLUS or a MINUS, see if we can
2793 simplify this by the associative law. This will, for example,
2794 canonicalize (minus A (plus B C)) to (minus (minus A B) C).
2795 Don't use the associative law for floating point.
2796 The inaccuracy makes it nonassociative,
2797 and subtle programs can break if operations are associated. */
2799 if (INTEGRAL_MODE_P (mode
)
2800 && (plus_minus_operand_p (op0
)
2801 || plus_minus_operand_p (op1
))
2802 && (tem
= simplify_plus_minus (code
, mode
, op0
, op1
)) != 0)
2805 /* Handle vector series. */
2806 if (GET_MODE_CLASS (mode
) == MODE_VECTOR_INT
)
2808 tem
= simplify_binary_operation_series (code
, mode
, op0
, op1
);
2815 if (trueop1
== constm1_rtx
)
2816 return simplify_gen_unary (NEG
, mode
, op0
, mode
);
2818 if (GET_CODE (op0
) == NEG
)
2820 rtx temp
= simplify_unary_operation (NEG
, mode
, op1
, mode
);
2821 /* If op1 is a MULT as well and simplify_unary_operation
2822 just moved the NEG to the second operand, simplify_gen_binary
2823 below could through simplify_associative_operation move
2824 the NEG around again and recurse endlessly. */
2826 && GET_CODE (op1
) == MULT
2827 && GET_CODE (temp
) == MULT
2828 && XEXP (op1
, 0) == XEXP (temp
, 0)
2829 && GET_CODE (XEXP (temp
, 1)) == NEG
2830 && XEXP (op1
, 1) == XEXP (XEXP (temp
, 1), 0))
2833 return simplify_gen_binary (MULT
, mode
, XEXP (op0
, 0), temp
);
2835 if (GET_CODE (op1
) == NEG
)
2837 rtx temp
= simplify_unary_operation (NEG
, mode
, op0
, mode
);
2838 /* If op0 is a MULT as well and simplify_unary_operation
2839 just moved the NEG to the second operand, simplify_gen_binary
2840 below could through simplify_associative_operation move
2841 the NEG around again and recurse endlessly. */
2843 && GET_CODE (op0
) == MULT
2844 && GET_CODE (temp
) == MULT
2845 && XEXP (op0
, 0) == XEXP (temp
, 0)
2846 && GET_CODE (XEXP (temp
, 1)) == NEG
2847 && XEXP (op0
, 1) == XEXP (XEXP (temp
, 1), 0))
2850 return simplify_gen_binary (MULT
, mode
, temp
, XEXP (op1
, 0));
2853 /* Maybe simplify x * 0 to 0. The reduction is not valid if
2854 x is NaN, since x * 0 is then also NaN. Nor is it valid
2855 when the mode has signed zeros, since multiplying a negative
2856 number by 0 will give -0, not 0. */
2857 if (!HONOR_NANS (mode
)
2858 && !HONOR_SIGNED_ZEROS (mode
)
2859 && trueop1
== CONST0_RTX (mode
)
2860 && ! side_effects_p (op0
))
2863 /* In IEEE floating point, x*1 is not equivalent to x for
2865 if (!HONOR_SNANS (mode
)
2866 && trueop1
== CONST1_RTX (mode
))
2869 /* Convert multiply by constant power of two into shift. */
2870 if (CONST_SCALAR_INT_P (trueop1
))
2872 val
= wi::exact_log2 (rtx_mode_t (trueop1
, mode
));
2874 return simplify_gen_binary (ASHIFT
, mode
, op0
,
2875 gen_int_shift_amount (mode
, val
));
2878 /* x*2 is x+x and x*(-1) is -x */
2879 if (CONST_DOUBLE_AS_FLOAT_P (trueop1
)
2880 && SCALAR_FLOAT_MODE_P (GET_MODE (trueop1
))
2881 && !DECIMAL_FLOAT_MODE_P (GET_MODE (trueop1
))
2882 && GET_MODE (op0
) == mode
)
2884 const REAL_VALUE_TYPE
*d1
= CONST_DOUBLE_REAL_VALUE (trueop1
);
2886 if (real_equal (d1
, &dconst2
))
2887 return simplify_gen_binary (PLUS
, mode
, op0
, copy_rtx (op0
));
2889 if (!HONOR_SNANS (mode
)
2890 && real_equal (d1
, &dconstm1
))
2891 return simplify_gen_unary (NEG
, mode
, op0
, mode
);
2894 /* Optimize -x * -x as x * x. */
2895 if (FLOAT_MODE_P (mode
)
2896 && GET_CODE (op0
) == NEG
2897 && GET_CODE (op1
) == NEG
2898 && rtx_equal_p (XEXP (op0
, 0), XEXP (op1
, 0))
2899 && !side_effects_p (XEXP (op0
, 0)))
2900 return simplify_gen_binary (MULT
, mode
, XEXP (op0
, 0), XEXP (op1
, 0));
2902 /* Likewise, optimize abs(x) * abs(x) as x * x. */
2903 if (SCALAR_FLOAT_MODE_P (mode
)
2904 && GET_CODE (op0
) == ABS
2905 && GET_CODE (op1
) == ABS
2906 && rtx_equal_p (XEXP (op0
, 0), XEXP (op1
, 0))
2907 && !side_effects_p (XEXP (op0
, 0)))
2908 return simplify_gen_binary (MULT
, mode
, XEXP (op0
, 0), XEXP (op1
, 0));
2910 /* Reassociate multiplication, but for floating point MULTs
2911 only when the user specifies unsafe math optimizations. */
2912 if (! FLOAT_MODE_P (mode
)
2913 || flag_unsafe_math_optimizations
)
2915 tem
= simplify_associative_operation (code
, mode
, op0
, op1
);
2922 if (trueop1
== CONST0_RTX (mode
))
2924 if (INTEGRAL_MODE_P (mode
)
2925 && trueop1
== CONSTM1_RTX (mode
)
2926 && !side_effects_p (op0
))
2928 if (rtx_equal_p (trueop0
, trueop1
) && ! side_effects_p (op0
))
2930 /* A | (~A) -> -1 */
2931 if (((GET_CODE (op0
) == NOT
&& rtx_equal_p (XEXP (op0
, 0), op1
))
2932 || (GET_CODE (op1
) == NOT
&& rtx_equal_p (XEXP (op1
, 0), op0
)))
2933 && ! side_effects_p (op0
)
2934 && SCALAR_INT_MODE_P (mode
))
2937 /* (ior A C) is C if all bits of A that might be nonzero are on in C. */
2938 if (CONST_INT_P (op1
)
2939 && HWI_COMPUTABLE_MODE_P (mode
)
2940 && (nonzero_bits (op0
, mode
) & ~UINTVAL (op1
)) == 0
2941 && !side_effects_p (op0
))
2944 /* Canonicalize (X & C1) | C2. */
2945 if (GET_CODE (op0
) == AND
2946 && CONST_INT_P (trueop1
)
2947 && CONST_INT_P (XEXP (op0
, 1)))
2949 HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
2950 HOST_WIDE_INT c1
= INTVAL (XEXP (op0
, 1));
2951 HOST_WIDE_INT c2
= INTVAL (trueop1
);
2953 /* If (C1&C2) == C1, then (X&C1)|C2 becomes C2. */
2955 && !side_effects_p (XEXP (op0
, 0)))
2958 /* If (C1|C2) == ~0 then (X&C1)|C2 becomes X|C2. */
2959 if (((c1
|c2
) & mask
) == mask
)
2960 return simplify_gen_binary (IOR
, mode
, XEXP (op0
, 0), op1
);
2963 /* Convert (A & B) | A to A. */
2964 if (GET_CODE (op0
) == AND
2965 && (rtx_equal_p (XEXP (op0
, 0), op1
)
2966 || rtx_equal_p (XEXP (op0
, 1), op1
))
2967 && ! side_effects_p (XEXP (op0
, 0))
2968 && ! side_effects_p (XEXP (op0
, 1)))
2971 /* Convert (ior (ashift A CX) (lshiftrt A CY)) where CX+CY equals the
2972 mode size to (rotate A CX). */
2974 if (GET_CODE (op1
) == ASHIFT
2975 || GET_CODE (op1
) == SUBREG
)
2986 if (GET_CODE (opleft
) == ASHIFT
&& GET_CODE (opright
) == LSHIFTRT
2987 && rtx_equal_p (XEXP (opleft
, 0), XEXP (opright
, 0))
2988 && CONST_INT_P (XEXP (opleft
, 1))
2989 && CONST_INT_P (XEXP (opright
, 1))
2990 && (INTVAL (XEXP (opleft
, 1)) + INTVAL (XEXP (opright
, 1))
2991 == GET_MODE_UNIT_PRECISION (mode
)))
2992 return gen_rtx_ROTATE (mode
, XEXP (opright
, 0), XEXP (opleft
, 1));
2994 /* Same, but for ashift that has been "simplified" to a wider mode
2995 by simplify_shift_const. */
2997 if (GET_CODE (opleft
) == SUBREG
2998 && is_a
<scalar_int_mode
> (mode
, &int_mode
)
2999 && is_a
<scalar_int_mode
> (GET_MODE (SUBREG_REG (opleft
)),
3001 && GET_CODE (SUBREG_REG (opleft
)) == ASHIFT
3002 && GET_CODE (opright
) == LSHIFTRT
3003 && GET_CODE (XEXP (opright
, 0)) == SUBREG
3004 && known_eq (SUBREG_BYTE (opleft
), SUBREG_BYTE (XEXP (opright
, 0)))
3005 && GET_MODE_SIZE (int_mode
) < GET_MODE_SIZE (inner_mode
)
3006 && rtx_equal_p (XEXP (SUBREG_REG (opleft
), 0),
3007 SUBREG_REG (XEXP (opright
, 0)))
3008 && CONST_INT_P (XEXP (SUBREG_REG (opleft
), 1))
3009 && CONST_INT_P (XEXP (opright
, 1))
3010 && (INTVAL (XEXP (SUBREG_REG (opleft
), 1))
3011 + INTVAL (XEXP (opright
, 1))
3012 == GET_MODE_PRECISION (int_mode
)))
3013 return gen_rtx_ROTATE (int_mode
, XEXP (opright
, 0),
3014 XEXP (SUBREG_REG (opleft
), 1));
3016 /* If OP0 is (ashiftrt (plus ...) C), it might actually be
3017 a (sign_extend (plus ...)). Then check if OP1 is a CONST_INT and
3018 the PLUS does not affect any of the bits in OP1: then we can do
3019 the IOR as a PLUS and we can associate. This is valid if OP1
3020 can be safely shifted left C bits. */
3021 if (CONST_INT_P (trueop1
) && GET_CODE (op0
) == ASHIFTRT
3022 && GET_CODE (XEXP (op0
, 0)) == PLUS
3023 && CONST_INT_P (XEXP (XEXP (op0
, 0), 1))
3024 && CONST_INT_P (XEXP (op0
, 1))
3025 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
)
3027 int count
= INTVAL (XEXP (op0
, 1));
3028 HOST_WIDE_INT mask
= UINTVAL (trueop1
) << count
;
3030 if (mask
>> count
== INTVAL (trueop1
)
3031 && trunc_int_for_mode (mask
, mode
) == mask
3032 && (mask
& nonzero_bits (XEXP (op0
, 0), mode
)) == 0)
3033 return simplify_gen_binary (ASHIFTRT
, mode
,
3034 plus_constant (mode
, XEXP (op0
, 0),
3039 /* The following happens with bitfield merging.
3040 (X & C) | ((X | Y) & ~C) -> X | (Y & ~C) */
3041 if (GET_CODE (op0
) == AND
3042 && GET_CODE (op1
) == AND
3043 && CONST_INT_P (XEXP (op0
, 1))
3044 && CONST_INT_P (XEXP (op1
, 1))
3045 && (INTVAL (XEXP (op0
, 1))
3046 == ~INTVAL (XEXP (op1
, 1))))
3048 /* The IOR may be on both sides. */
3049 rtx top0
= NULL_RTX
, top1
= NULL_RTX
;
3050 if (GET_CODE (XEXP (op1
, 0)) == IOR
)
3051 top0
= op0
, top1
= op1
;
3052 else if (GET_CODE (XEXP (op0
, 0)) == IOR
)
3053 top0
= op1
, top1
= op0
;
3056 /* X may be on either side of the inner IOR. */
3058 if (rtx_equal_p (XEXP (top0
, 0),
3059 XEXP (XEXP (top1
, 0), 0)))
3060 tem
= XEXP (XEXP (top1
, 0), 1);
3061 else if (rtx_equal_p (XEXP (top0
, 0),
3062 XEXP (XEXP (top1
, 0), 1)))
3063 tem
= XEXP (XEXP (top1
, 0), 0);
3065 return simplify_gen_binary (IOR
, mode
, XEXP (top0
, 0),
3067 (AND
, mode
, tem
, XEXP (top1
, 1)));
3071 tem
= simplify_byte_swapping_operation (code
, mode
, op0
, op1
);
3075 tem
= simplify_associative_operation (code
, mode
, op0
, op1
);
3079 tem
= simplify_logical_relational_operation (code
, mode
, op0
, op1
);
3085 if (trueop1
== CONST0_RTX (mode
))
3087 if (INTEGRAL_MODE_P (mode
) && trueop1
== CONSTM1_RTX (mode
))
3088 return simplify_gen_unary (NOT
, mode
, op0
, mode
);
3089 if (rtx_equal_p (trueop0
, trueop1
)
3090 && ! side_effects_p (op0
)
3091 && GET_MODE_CLASS (mode
) != MODE_CC
)
3092 return CONST0_RTX (mode
);
3094 /* Canonicalize XOR of the most significant bit to PLUS. */
3095 if (CONST_SCALAR_INT_P (op1
)
3096 && mode_signbit_p (mode
, op1
))
3097 return simplify_gen_binary (PLUS
, mode
, op0
, op1
);
3098 /* (xor (plus X C1) C2) is (xor X (C1^C2)) if C1 is signbit. */
3099 if (CONST_SCALAR_INT_P (op1
)
3100 && GET_CODE (op0
) == PLUS
3101 && CONST_SCALAR_INT_P (XEXP (op0
, 1))
3102 && mode_signbit_p (mode
, XEXP (op0
, 1)))
3103 return simplify_gen_binary (XOR
, mode
, XEXP (op0
, 0),
3104 simplify_gen_binary (XOR
, mode
, op1
,
3107 /* If we are XORing two things that have no bits in common,
3108 convert them into an IOR. This helps to detect rotation encoded
3109 using those methods and possibly other simplifications. */
3111 if (HWI_COMPUTABLE_MODE_P (mode
)
3112 && (nonzero_bits (op0
, mode
)
3113 & nonzero_bits (op1
, mode
)) == 0)
3114 return (simplify_gen_binary (IOR
, mode
, op0
, op1
));
3116 /* Convert (XOR (NOT x) (NOT y)) to (XOR x y).
3117 Also convert (XOR (NOT x) y) to (NOT (XOR x y)), similarly for
3120 int num_negated
= 0;
3122 if (GET_CODE (op0
) == NOT
)
3123 num_negated
++, op0
= XEXP (op0
, 0);
3124 if (GET_CODE (op1
) == NOT
)
3125 num_negated
++, op1
= XEXP (op1
, 0);
3127 if (num_negated
== 2)
3128 return simplify_gen_binary (XOR
, mode
, op0
, op1
);
3129 else if (num_negated
== 1)
3130 return simplify_gen_unary (NOT
, mode
,
3131 simplify_gen_binary (XOR
, mode
, op0
, op1
),
3135 /* Convert (xor (and A B) B) to (and (not A) B). The latter may
3136 correspond to a machine insn or result in further simplifications
3137 if B is a constant. */
3139 if (GET_CODE (op0
) == AND
3140 && rtx_equal_p (XEXP (op0
, 1), op1
)
3141 && ! side_effects_p (op1
))
3142 return simplify_gen_binary (AND
, mode
,
3143 simplify_gen_unary (NOT
, mode
,
3144 XEXP (op0
, 0), mode
),
3147 else if (GET_CODE (op0
) == AND
3148 && rtx_equal_p (XEXP (op0
, 0), op1
)
3149 && ! side_effects_p (op1
))
3150 return simplify_gen_binary (AND
, mode
,
3151 simplify_gen_unary (NOT
, mode
,
3152 XEXP (op0
, 1), mode
),
3155 /* Given (xor (ior (xor A B) C) D), where B, C and D are
3156 constants, simplify to (xor (ior A C) (B&~C)^D), canceling
3157 out bits inverted twice and not set by C. Similarly, given
3158 (xor (and (xor A B) C) D), simplify without inverting C in
3159 the xor operand: (xor (and A C) (B&C)^D).
3161 else if ((GET_CODE (op0
) == IOR
|| GET_CODE (op0
) == AND
)
3162 && GET_CODE (XEXP (op0
, 0)) == XOR
3163 && CONST_INT_P (op1
)
3164 && CONST_INT_P (XEXP (op0
, 1))
3165 && CONST_INT_P (XEXP (XEXP (op0
, 0), 1)))
3167 enum rtx_code op
= GET_CODE (op0
);
3168 rtx a
= XEXP (XEXP (op0
, 0), 0);
3169 rtx b
= XEXP (XEXP (op0
, 0), 1);
3170 rtx c
= XEXP (op0
, 1);
3172 HOST_WIDE_INT bval
= INTVAL (b
);
3173 HOST_WIDE_INT cval
= INTVAL (c
);
3174 HOST_WIDE_INT dval
= INTVAL (d
);
3175 HOST_WIDE_INT xcval
;
3182 return simplify_gen_binary (XOR
, mode
,
3183 simplify_gen_binary (op
, mode
, a
, c
),
3184 gen_int_mode ((bval
& xcval
) ^ dval
,
3188 /* Given (xor (and A B) C), using P^Q == (~P&Q) | (~Q&P),
3189 we can transform like this:
3190 (A&B)^C == ~(A&B)&C | ~C&(A&B)
3191 == (~A|~B)&C | ~C&(A&B) * DeMorgan's Law
3192 == ~A&C | ~B&C | A&(~C&B) * Distribute and re-order
3193 Attempt a few simplifications when B and C are both constants. */
3194 if (GET_CODE (op0
) == AND
3195 && CONST_INT_P (op1
)
3196 && CONST_INT_P (XEXP (op0
, 1)))
3198 rtx a
= XEXP (op0
, 0);
3199 rtx b
= XEXP (op0
, 1);
3201 HOST_WIDE_INT bval
= INTVAL (b
);
3202 HOST_WIDE_INT cval
= INTVAL (c
);
3204 /* Instead of computing ~A&C, we compute its negated value,
3205 ~(A|~C). If it yields -1, ~A&C is zero, so we can
3206 optimize for sure. If it does not simplify, we still try
3207 to compute ~A&C below, but since that always allocates
3208 RTL, we don't try that before committing to returning a
3209 simplified expression. */
3210 rtx n_na_c
= simplify_binary_operation (IOR
, mode
, a
,
3213 if ((~cval
& bval
) == 0)
3215 rtx na_c
= NULL_RTX
;
3217 na_c
= simplify_gen_unary (NOT
, mode
, n_na_c
, mode
);
3220 /* If ~A does not simplify, don't bother: we don't
3221 want to simplify 2 operations into 3, and if na_c
3222 were to simplify with na, n_na_c would have
3223 simplified as well. */
3224 rtx na
= simplify_unary_operation (NOT
, mode
, a
, mode
);
3226 na_c
= simplify_gen_binary (AND
, mode
, na
, c
);
3229 /* Try to simplify ~A&C | ~B&C. */
3230 if (na_c
!= NULL_RTX
)
3231 return simplify_gen_binary (IOR
, mode
, na_c
,
3232 gen_int_mode (~bval
& cval
, mode
));
3236 /* If ~A&C is zero, simplify A&(~C&B) | ~B&C. */
3237 if (n_na_c
== CONSTM1_RTX (mode
))
3239 rtx a_nc_b
= simplify_gen_binary (AND
, mode
, a
,
3240 gen_int_mode (~cval
& bval
,
3242 return simplify_gen_binary (IOR
, mode
, a_nc_b
,
3243 gen_int_mode (~bval
& cval
,
3249 /* If we have (xor (and (xor A B) C) A) with C a constant we can instead
3250 do (ior (and A ~C) (and B C)) which is a machine instruction on some
3251 machines, and also has shorter instruction path length. */
3252 if (GET_CODE (op0
) == AND
3253 && GET_CODE (XEXP (op0
, 0)) == XOR
3254 && CONST_INT_P (XEXP (op0
, 1))
3255 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), trueop1
))
3258 rtx b
= XEXP (XEXP (op0
, 0), 1);
3259 rtx c
= XEXP (op0
, 1);
3260 rtx nc
= simplify_gen_unary (NOT
, mode
, c
, mode
);
3261 rtx a_nc
= simplify_gen_binary (AND
, mode
, a
, nc
);
3262 rtx bc
= simplify_gen_binary (AND
, mode
, b
, c
);
3263 return simplify_gen_binary (IOR
, mode
, a_nc
, bc
);
3265 /* Similarly, (xor (and (xor A B) C) B) as (ior (and A C) (and B ~C)) */
3266 else if (GET_CODE (op0
) == AND
3267 && GET_CODE (XEXP (op0
, 0)) == XOR
3268 && CONST_INT_P (XEXP (op0
, 1))
3269 && rtx_equal_p (XEXP (XEXP (op0
, 0), 1), trueop1
))
3271 rtx a
= XEXP (XEXP (op0
, 0), 0);
3273 rtx c
= XEXP (op0
, 1);
3274 rtx nc
= simplify_gen_unary (NOT
, mode
, c
, mode
);
3275 rtx b_nc
= simplify_gen_binary (AND
, mode
, b
, nc
);
3276 rtx ac
= simplify_gen_binary (AND
, mode
, a
, c
);
3277 return simplify_gen_binary (IOR
, mode
, ac
, b_nc
);
3280 /* (xor (comparison foo bar) (const_int 1)) can become the reversed
3281 comparison if STORE_FLAG_VALUE is 1. */
3282 if (STORE_FLAG_VALUE
== 1
3283 && trueop1
== const1_rtx
3284 && COMPARISON_P (op0
)
3285 && (reversed
= reversed_comparison (op0
, mode
)))
3288 /* (lshiftrt foo C) where C is the number of bits in FOO minus 1
3289 is (lt foo (const_int 0)), so we can perform the above
3290 simplification if STORE_FLAG_VALUE is 1. */
3292 if (is_a
<scalar_int_mode
> (mode
, &int_mode
)
3293 && STORE_FLAG_VALUE
== 1
3294 && trueop1
== const1_rtx
3295 && GET_CODE (op0
) == LSHIFTRT
3296 && CONST_INT_P (XEXP (op0
, 1))
3297 && INTVAL (XEXP (op0
, 1)) == GET_MODE_PRECISION (int_mode
) - 1)
3298 return gen_rtx_GE (int_mode
, XEXP (op0
, 0), const0_rtx
);
3300 /* (xor (comparison foo bar) (const_int sign-bit))
3301 when STORE_FLAG_VALUE is the sign bit. */
3302 if (is_a
<scalar_int_mode
> (mode
, &int_mode
)
3303 && val_signbit_p (int_mode
, STORE_FLAG_VALUE
)
3304 && trueop1
== const_true_rtx
3305 && COMPARISON_P (op0
)
3306 && (reversed
= reversed_comparison (op0
, int_mode
)))
3309 tem
= simplify_byte_swapping_operation (code
, mode
, op0
, op1
);
3313 tem
= simplify_associative_operation (code
, mode
, op0
, op1
);
3319 if (trueop1
== CONST0_RTX (mode
) && ! side_effects_p (op0
))
3321 if (INTEGRAL_MODE_P (mode
) && trueop1
== CONSTM1_RTX (mode
))
3323 if (HWI_COMPUTABLE_MODE_P (mode
))
3325 HOST_WIDE_INT nzop0
= nonzero_bits (trueop0
, mode
);
3326 HOST_WIDE_INT nzop1
;
3327 if (CONST_INT_P (trueop1
))
3329 HOST_WIDE_INT val1
= INTVAL (trueop1
);
3330 /* If we are turning off bits already known off in OP0, we need
3332 if ((nzop0
& ~val1
) == 0)
3335 nzop1
= nonzero_bits (trueop1
, mode
);
3336 /* If we are clearing all the nonzero bits, the result is zero. */
3337 if ((nzop1
& nzop0
) == 0
3338 && !side_effects_p (op0
) && !side_effects_p (op1
))
3339 return CONST0_RTX (mode
);
3341 if (rtx_equal_p (trueop0
, trueop1
) && ! side_effects_p (op0
)
3342 && GET_MODE_CLASS (mode
) != MODE_CC
)
3345 if (((GET_CODE (op0
) == NOT
&& rtx_equal_p (XEXP (op0
, 0), op1
))
3346 || (GET_CODE (op1
) == NOT
&& rtx_equal_p (XEXP (op1
, 0), op0
)))
3347 && ! side_effects_p (op0
)
3348 && GET_MODE_CLASS (mode
) != MODE_CC
)
3349 return CONST0_RTX (mode
);
3351 /* Transform (and (extend X) C) into (zero_extend (and X C)) if
3352 there are no nonzero bits of C outside of X's mode. */
3353 if ((GET_CODE (op0
) == SIGN_EXTEND
3354 || GET_CODE (op0
) == ZERO_EXTEND
)
3355 && CONST_INT_P (trueop1
)
3356 && HWI_COMPUTABLE_MODE_P (mode
)
3357 && (~GET_MODE_MASK (GET_MODE (XEXP (op0
, 0)))
3358 & UINTVAL (trueop1
)) == 0)
3360 machine_mode imode
= GET_MODE (XEXP (op0
, 0));
3361 tem
= simplify_gen_binary (AND
, imode
, XEXP (op0
, 0),
3362 gen_int_mode (INTVAL (trueop1
),
3364 return simplify_gen_unary (ZERO_EXTEND
, mode
, tem
, imode
);
3367 /* Transform (and (truncate X) C) into (truncate (and X C)). This way
3368 we might be able to further simplify the AND with X and potentially
3369 remove the truncation altogether. */
3370 if (GET_CODE (op0
) == TRUNCATE
&& CONST_INT_P (trueop1
))
3372 rtx x
= XEXP (op0
, 0);
3373 machine_mode xmode
= GET_MODE (x
);
3374 tem
= simplify_gen_binary (AND
, xmode
, x
,
3375 gen_int_mode (INTVAL (trueop1
), xmode
));
3376 return simplify_gen_unary (TRUNCATE
, mode
, tem
, xmode
);
3379 /* Canonicalize (A | C1) & C2 as (A & C2) | (C1 & C2). */
3380 if (GET_CODE (op0
) == IOR
3381 && CONST_INT_P (trueop1
)
3382 && CONST_INT_P (XEXP (op0
, 1)))
3384 HOST_WIDE_INT tmp
= INTVAL (trueop1
) & INTVAL (XEXP (op0
, 1));
3385 return simplify_gen_binary (IOR
, mode
,
3386 simplify_gen_binary (AND
, mode
,
3387 XEXP (op0
, 0), op1
),
3388 gen_int_mode (tmp
, mode
));
3391 /* Convert (A ^ B) & A to A & (~B) since the latter is often a single
3392 insn (and may simplify more). */
3393 if (GET_CODE (op0
) == XOR
3394 && rtx_equal_p (XEXP (op0
, 0), op1
)
3395 && ! side_effects_p (op1
))
3396 return simplify_gen_binary (AND
, mode
,
3397 simplify_gen_unary (NOT
, mode
,
3398 XEXP (op0
, 1), mode
),
3401 if (GET_CODE (op0
) == XOR
3402 && rtx_equal_p (XEXP (op0
, 1), op1
)
3403 && ! side_effects_p (op1
))
3404 return simplify_gen_binary (AND
, mode
,
3405 simplify_gen_unary (NOT
, mode
,
3406 XEXP (op0
, 0), mode
),
3409 /* Similarly for (~(A ^ B)) & A. */
3410 if (GET_CODE (op0
) == NOT
3411 && GET_CODE (XEXP (op0
, 0)) == XOR
3412 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), op1
)
3413 && ! side_effects_p (op1
))
3414 return simplify_gen_binary (AND
, mode
, XEXP (XEXP (op0
, 0), 1), op1
);
3416 if (GET_CODE (op0
) == NOT
3417 && GET_CODE (XEXP (op0
, 0)) == XOR
3418 && rtx_equal_p (XEXP (XEXP (op0
, 0), 1), op1
)
3419 && ! side_effects_p (op1
))
3420 return simplify_gen_binary (AND
, mode
, XEXP (XEXP (op0
, 0), 0), op1
);
3422 /* Convert (A | B) & A to A. */
3423 if (GET_CODE (op0
) == IOR
3424 && (rtx_equal_p (XEXP (op0
, 0), op1
)
3425 || rtx_equal_p (XEXP (op0
, 1), op1
))
3426 && ! side_effects_p (XEXP (op0
, 0))
3427 && ! side_effects_p (XEXP (op0
, 1)))
3430 /* For constants M and N, if M == (1LL << cst) - 1 && (N & M) == M,
3431 ((A & N) + B) & M -> (A + B) & M
3432 Similarly if (N & M) == 0,
3433 ((A | N) + B) & M -> (A + B) & M
3434 and for - instead of + and/or ^ instead of |.
3435 Also, if (N & M) == 0, then
3436 (A +- N) & M -> A & M. */
3437 if (CONST_INT_P (trueop1
)
3438 && HWI_COMPUTABLE_MODE_P (mode
)
3439 && ~UINTVAL (trueop1
)
3440 && (UINTVAL (trueop1
) & (UINTVAL (trueop1
) + 1)) == 0
3441 && (GET_CODE (op0
) == PLUS
|| GET_CODE (op0
) == MINUS
))
3446 pmop
[0] = XEXP (op0
, 0);
3447 pmop
[1] = XEXP (op0
, 1);
3449 if (CONST_INT_P (pmop
[1])
3450 && (UINTVAL (pmop
[1]) & UINTVAL (trueop1
)) == 0)
3451 return simplify_gen_binary (AND
, mode
, pmop
[0], op1
);
3453 for (which
= 0; which
< 2; which
++)
3456 switch (GET_CODE (tem
))
3459 if (CONST_INT_P (XEXP (tem
, 1))
3460 && (UINTVAL (XEXP (tem
, 1)) & UINTVAL (trueop1
))
3461 == UINTVAL (trueop1
))
3462 pmop
[which
] = XEXP (tem
, 0);
3466 if (CONST_INT_P (XEXP (tem
, 1))
3467 && (UINTVAL (XEXP (tem
, 1)) & UINTVAL (trueop1
)) == 0)
3468 pmop
[which
] = XEXP (tem
, 0);
3475 if (pmop
[0] != XEXP (op0
, 0) || pmop
[1] != XEXP (op0
, 1))
3477 tem
= simplify_gen_binary (GET_CODE (op0
), mode
,
3479 return simplify_gen_binary (code
, mode
, tem
, op1
);
3483 /* (and X (ior (not X) Y) -> (and X Y) */
3484 if (GET_CODE (op1
) == IOR
3485 && GET_CODE (XEXP (op1
, 0)) == NOT
3486 && rtx_equal_p (op0
, XEXP (XEXP (op1
, 0), 0)))
3487 return simplify_gen_binary (AND
, mode
, op0
, XEXP (op1
, 1));
3489 /* (and (ior (not X) Y) X) -> (and X Y) */
3490 if (GET_CODE (op0
) == IOR
3491 && GET_CODE (XEXP (op0
, 0)) == NOT
3492 && rtx_equal_p (op1
, XEXP (XEXP (op0
, 0), 0)))
3493 return simplify_gen_binary (AND
, mode
, op1
, XEXP (op0
, 1));
3495 /* (and X (ior Y (not X)) -> (and X Y) */
3496 if (GET_CODE (op1
) == IOR
3497 && GET_CODE (XEXP (op1
, 1)) == NOT
3498 && rtx_equal_p (op0
, XEXP (XEXP (op1
, 1), 0)))
3499 return simplify_gen_binary (AND
, mode
, op0
, XEXP (op1
, 0));
3501 /* (and (ior Y (not X)) X) -> (and X Y) */
3502 if (GET_CODE (op0
) == IOR
3503 && GET_CODE (XEXP (op0
, 1)) == NOT
3504 && rtx_equal_p (op1
, XEXP (XEXP (op0
, 1), 0)))
3505 return simplify_gen_binary (AND
, mode
, op1
, XEXP (op0
, 0));
3507 tem
= simplify_byte_swapping_operation (code
, mode
, op0
, op1
);
3511 tem
= simplify_associative_operation (code
, mode
, op0
, op1
);
3517 /* 0/x is 0 (or x&0 if x has side-effects). */
3518 if (trueop0
== CONST0_RTX (mode
)
3519 && !cfun
->can_throw_non_call_exceptions
)
3521 if (side_effects_p (op1
))
3522 return simplify_gen_binary (AND
, mode
, op1
, trueop0
);
3526 if (trueop1
== CONST1_RTX (mode
))
3528 tem
= rtl_hooks
.gen_lowpart_no_emit (mode
, op0
);
3532 /* Convert divide by power of two into shift. */
3533 if (CONST_INT_P (trueop1
)
3534 && (val
= exact_log2 (UINTVAL (trueop1
))) > 0)
3535 return simplify_gen_binary (LSHIFTRT
, mode
, op0
,
3536 gen_int_shift_amount (mode
, val
));
3540 /* Handle floating point and integers separately. */
3541 if (SCALAR_FLOAT_MODE_P (mode
))
3543 /* Maybe change 0.0 / x to 0.0. This transformation isn't
3544 safe for modes with NaNs, since 0.0 / 0.0 will then be
3545 NaN rather than 0.0. Nor is it safe for modes with signed
3546 zeros, since dividing 0 by a negative number gives -0.0 */
3547 if (trueop0
== CONST0_RTX (mode
)
3548 && !HONOR_NANS (mode
)
3549 && !HONOR_SIGNED_ZEROS (mode
)
3550 && ! side_effects_p (op1
))
3553 if (trueop1
== CONST1_RTX (mode
)
3554 && !HONOR_SNANS (mode
))
3557 if (CONST_DOUBLE_AS_FLOAT_P (trueop1
)
3558 && trueop1
!= CONST0_RTX (mode
))
3560 const REAL_VALUE_TYPE
*d1
= CONST_DOUBLE_REAL_VALUE (trueop1
);
3563 if (real_equal (d1
, &dconstm1
)
3564 && !HONOR_SNANS (mode
))
3565 return simplify_gen_unary (NEG
, mode
, op0
, mode
);
3567 /* Change FP division by a constant into multiplication.
3568 Only do this with -freciprocal-math. */
3569 if (flag_reciprocal_math
3570 && !real_equal (d1
, &dconst0
))
3573 real_arithmetic (&d
, RDIV_EXPR
, &dconst1
, d1
);
3574 tem
= const_double_from_real_value (d
, mode
);
3575 return simplify_gen_binary (MULT
, mode
, op0
, tem
);
3579 else if (SCALAR_INT_MODE_P (mode
))
3581 /* 0/x is 0 (or x&0 if x has side-effects). */
3582 if (trueop0
== CONST0_RTX (mode
)
3583 && !cfun
->can_throw_non_call_exceptions
)
3585 if (side_effects_p (op1
))
3586 return simplify_gen_binary (AND
, mode
, op1
, trueop0
);
3590 if (trueop1
== CONST1_RTX (mode
))
3592 tem
= rtl_hooks
.gen_lowpart_no_emit (mode
, op0
);
3597 if (trueop1
== constm1_rtx
)
3599 rtx x
= rtl_hooks
.gen_lowpart_no_emit (mode
, op0
);
3601 return simplify_gen_unary (NEG
, mode
, x
, mode
);
3607 /* 0%x is 0 (or x&0 if x has side-effects). */
3608 if (trueop0
== CONST0_RTX (mode
))
3610 if (side_effects_p (op1
))
3611 return simplify_gen_binary (AND
, mode
, op1
, trueop0
);
3614 /* x%1 is 0 (of x&0 if x has side-effects). */
3615 if (trueop1
== CONST1_RTX (mode
))
3617 if (side_effects_p (op0
))
3618 return simplify_gen_binary (AND
, mode
, op0
, CONST0_RTX (mode
));
3619 return CONST0_RTX (mode
);
3621 /* Implement modulus by power of two as AND. */
3622 if (CONST_INT_P (trueop1
)
3623 && exact_log2 (UINTVAL (trueop1
)) > 0)
3624 return simplify_gen_binary (AND
, mode
, op0
,
3625 gen_int_mode (UINTVAL (trueop1
) - 1,
3630 /* 0%x is 0 (or x&0 if x has side-effects). */
3631 if (trueop0
== CONST0_RTX (mode
))
3633 if (side_effects_p (op1
))
3634 return simplify_gen_binary (AND
, mode
, op1
, trueop0
);
3637 /* x%1 and x%-1 is 0 (or x&0 if x has side-effects). */
3638 if (trueop1
== CONST1_RTX (mode
) || trueop1
== constm1_rtx
)
3640 if (side_effects_p (op0
))
3641 return simplify_gen_binary (AND
, mode
, op0
, CONST0_RTX (mode
));
3642 return CONST0_RTX (mode
);
3648 /* Canonicalize rotates by constant amount. If op1 is bitsize / 2,
3649 prefer left rotation, if op1 is from bitsize / 2 + 1 to
3650 bitsize - 1, use other direction of rotate with 1 .. bitsize / 2 - 1
3652 #if defined(HAVE_rotate) && defined(HAVE_rotatert)
3653 if (CONST_INT_P (trueop1
)
3654 && IN_RANGE (INTVAL (trueop1
),
3655 GET_MODE_UNIT_PRECISION (mode
) / 2 + (code
== ROTATE
),
3656 GET_MODE_UNIT_PRECISION (mode
) - 1))
3658 int new_amount
= GET_MODE_UNIT_PRECISION (mode
) - INTVAL (trueop1
);
3659 rtx new_amount_rtx
= gen_int_shift_amount (mode
, new_amount
);
3660 return simplify_gen_binary (code
== ROTATE
? ROTATERT
: ROTATE
,
3661 mode
, op0
, new_amount_rtx
);
3666 if (trueop1
== CONST0_RTX (mode
))
3668 if (trueop0
== CONST0_RTX (mode
) && ! side_effects_p (op1
))
3670 /* Rotating ~0 always results in ~0. */
3671 if (CONST_INT_P (trueop0
)
3672 && HWI_COMPUTABLE_MODE_P (mode
)
3673 && UINTVAL (trueop0
) == GET_MODE_MASK (mode
)
3674 && ! side_effects_p (op1
))
3680 scalar constants c1, c2
3681 size (M2) > size (M1)
3682 c1 == size (M2) - size (M1)
3684 ([a|l]shiftrt:M1 (subreg:M1 (lshiftrt:M2 (reg:M2) (const_int <c1>))
3688 (subreg:M1 ([a|l]shiftrt:M2 (reg:M2) (const_int <c1 + c2>))
3690 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
3691 && is_a
<scalar_int_mode
> (mode
, &int_mode
)
3693 && CONST_INT_P (op1
)
3694 && GET_CODE (SUBREG_REG (op0
)) == LSHIFTRT
3695 && is_a
<scalar_int_mode
> (GET_MODE (SUBREG_REG (op0
)),
3697 && CONST_INT_P (XEXP (SUBREG_REG (op0
), 1))
3698 && GET_MODE_BITSIZE (inner_mode
) > GET_MODE_BITSIZE (int_mode
)
3699 && (INTVAL (XEXP (SUBREG_REG (op0
), 1))
3700 == GET_MODE_BITSIZE (inner_mode
) - GET_MODE_BITSIZE (int_mode
))
3701 && subreg_lowpart_p (op0
))
3703 rtx tmp
= gen_int_shift_amount
3704 (inner_mode
, INTVAL (XEXP (SUBREG_REG (op0
), 1)) + INTVAL (op1
));
3706 /* Combine would usually zero out the value when combining two
3707 local shifts and the range becomes larger or equal to the mode.
3708 However since we fold away one of the shifts here combine won't
3709 see it so we should immediately zero the result if it's out of
3711 if (code
== LSHIFTRT
3712 && INTVAL (tmp
) >= GET_MODE_BITSIZE (inner_mode
))
3715 tmp
= simplify_gen_binary (code
,
3717 XEXP (SUBREG_REG (op0
), 0),
3720 return lowpart_subreg (int_mode
, tmp
, inner_mode
);
3723 if (SHIFT_COUNT_TRUNCATED
&& CONST_INT_P (op1
))
3725 val
= INTVAL (op1
) & (GET_MODE_UNIT_PRECISION (mode
) - 1);
3726 if (val
!= INTVAL (op1
))
3727 return simplify_gen_binary (code
, mode
, op0
,
3728 gen_int_shift_amount (mode
, val
));
3735 if (trueop1
== CONST0_RTX (mode
))
3737 if (trueop0
== CONST0_RTX (mode
) && ! side_effects_p (op1
))
3739 goto canonicalize_shift
;
3742 if (trueop1
== CONST0_RTX (mode
))
3744 if (trueop0
== CONST0_RTX (mode
) && ! side_effects_p (op1
))
3746 /* Optimize (lshiftrt (clz X) C) as (eq X 0). */
3747 if (GET_CODE (op0
) == CLZ
3748 && is_a
<scalar_int_mode
> (GET_MODE (XEXP (op0
, 0)), &inner_mode
)
3749 && CONST_INT_P (trueop1
)
3750 && STORE_FLAG_VALUE
== 1
3751 && INTVAL (trueop1
) < GET_MODE_UNIT_PRECISION (mode
))
3753 unsigned HOST_WIDE_INT zero_val
= 0;
3755 if (CLZ_DEFINED_VALUE_AT_ZERO (inner_mode
, zero_val
)
3756 && zero_val
== GET_MODE_PRECISION (inner_mode
)
3757 && INTVAL (trueop1
) == exact_log2 (zero_val
))
3758 return simplify_gen_relational (EQ
, mode
, inner_mode
,
3759 XEXP (op0
, 0), const0_rtx
);
3761 goto canonicalize_shift
;
3764 if (HWI_COMPUTABLE_MODE_P (mode
)
3765 && mode_signbit_p (mode
, trueop1
)
3766 && ! side_effects_p (op0
))
3768 if (rtx_equal_p (trueop0
, trueop1
) && ! side_effects_p (op0
))
3770 tem
= simplify_associative_operation (code
, mode
, op0
, op1
);
3776 if (HWI_COMPUTABLE_MODE_P (mode
)
3777 && CONST_INT_P (trueop1
)
3778 && (UINTVAL (trueop1
) == GET_MODE_MASK (mode
) >> 1)
3779 && ! side_effects_p (op0
))
3781 if (rtx_equal_p (trueop0
, trueop1
) && ! side_effects_p (op0
))
3783 tem
= simplify_associative_operation (code
, mode
, op0
, op1
);
3789 if (trueop1
== CONST0_RTX (mode
) && ! side_effects_p (op0
))
3791 if (rtx_equal_p (trueop0
, trueop1
) && ! side_effects_p (op0
))
3793 tem
= simplify_associative_operation (code
, mode
, op0
, op1
);
3799 if (trueop1
== constm1_rtx
&& ! side_effects_p (op0
))
3801 if (rtx_equal_p (trueop0
, trueop1
) && ! side_effects_p (op0
))
3803 tem
= simplify_associative_operation (code
, mode
, op0
, op1
);
3816 /* ??? There are simplifications that can be done. */
3820 if (op1
== CONST0_RTX (GET_MODE_INNER (mode
)))
3821 return gen_vec_duplicate (mode
, op0
);
3822 if (valid_for_const_vector_p (mode
, op0
)
3823 && valid_for_const_vector_p (mode
, op1
))
3824 return gen_const_vec_series (mode
, op0
, op1
);
3828 if (!VECTOR_MODE_P (mode
))
3830 gcc_assert (VECTOR_MODE_P (GET_MODE (trueop0
)));
3831 gcc_assert (mode
== GET_MODE_INNER (GET_MODE (trueop0
)));
3832 gcc_assert (GET_CODE (trueop1
) == PARALLEL
);
3833 gcc_assert (XVECLEN (trueop1
, 0) == 1);
3835 /* We can't reason about selections made at runtime. */
3836 if (!CONST_INT_P (XVECEXP (trueop1
, 0, 0)))
3839 if (vec_duplicate_p (trueop0
, &elt0
))
3842 if (GET_CODE (trueop0
) == CONST_VECTOR
)
3843 return CONST_VECTOR_ELT (trueop0
, INTVAL (XVECEXP
3846 /* Extract a scalar element from a nested VEC_SELECT expression
3847 (with optional nested VEC_CONCAT expression). Some targets
3848 (i386) extract scalar element from a vector using chain of
3849 nested VEC_SELECT expressions. When input operand is a memory
3850 operand, this operation can be simplified to a simple scalar
3851 load from an offseted memory address. */
3853 if (GET_CODE (trueop0
) == VEC_SELECT
3854 && (GET_MODE_NUNITS (GET_MODE (XEXP (trueop0
, 0)))
3855 .is_constant (&n_elts
)))
3857 rtx op0
= XEXP (trueop0
, 0);
3858 rtx op1
= XEXP (trueop0
, 1);
3860 int i
= INTVAL (XVECEXP (trueop1
, 0, 0));
3866 gcc_assert (GET_CODE (op1
) == PARALLEL
);
3867 gcc_assert (i
< n_elts
);
3869 /* Select element, pointed by nested selector. */
3870 elem
= INTVAL (XVECEXP (op1
, 0, i
));
3872 /* Handle the case when nested VEC_SELECT wraps VEC_CONCAT. */
3873 if (GET_CODE (op0
) == VEC_CONCAT
)
3875 rtx op00
= XEXP (op0
, 0);
3876 rtx op01
= XEXP (op0
, 1);
3878 machine_mode mode00
, mode01
;
3879 int n_elts00
, n_elts01
;
3881 mode00
= GET_MODE (op00
);
3882 mode01
= GET_MODE (op01
);
3884 /* Find out the number of elements of each operand.
3885 Since the concatenated result has a constant number
3886 of elements, the operands must too. */
3887 n_elts00
= GET_MODE_NUNITS (mode00
).to_constant ();
3888 n_elts01
= GET_MODE_NUNITS (mode01
).to_constant ();
3890 gcc_assert (n_elts
== n_elts00
+ n_elts01
);
3892 /* Select correct operand of VEC_CONCAT
3893 and adjust selector. */
3894 if (elem
< n_elts01
)
3905 vec
= rtvec_alloc (1);
3906 RTVEC_ELT (vec
, 0) = GEN_INT (elem
);
3908 tmp
= gen_rtx_fmt_ee (code
, mode
,
3909 tmp_op
, gen_rtx_PARALLEL (VOIDmode
, vec
));
3915 gcc_assert (VECTOR_MODE_P (GET_MODE (trueop0
)));
3916 gcc_assert (GET_MODE_INNER (mode
)
3917 == GET_MODE_INNER (GET_MODE (trueop0
)));
3918 gcc_assert (GET_CODE (trueop1
) == PARALLEL
);
3920 if (vec_duplicate_p (trueop0
, &elt0
))
3921 /* It doesn't matter which elements are selected by trueop1,
3922 because they are all the same. */
3923 return gen_vec_duplicate (mode
, elt0
);
3925 if (GET_CODE (trueop0
) == CONST_VECTOR
)
3927 unsigned n_elts
= XVECLEN (trueop1
, 0);
3928 rtvec v
= rtvec_alloc (n_elts
);
3931 gcc_assert (known_eq (n_elts
, GET_MODE_NUNITS (mode
)));
3932 for (i
= 0; i
< n_elts
; i
++)
3934 rtx x
= XVECEXP (trueop1
, 0, i
);
3936 if (!CONST_INT_P (x
))
3939 RTVEC_ELT (v
, i
) = CONST_VECTOR_ELT (trueop0
,
3943 return gen_rtx_CONST_VECTOR (mode
, v
);
3946 /* Recognize the identity. */
3947 if (GET_MODE (trueop0
) == mode
)
3949 bool maybe_ident
= true;
3950 for (int i
= 0; i
< XVECLEN (trueop1
, 0); i
++)
3952 rtx j
= XVECEXP (trueop1
, 0, i
);
3953 if (!CONST_INT_P (j
) || INTVAL (j
) != i
)
3955 maybe_ident
= false;
3963 /* If we build {a,b} then permute it, build the result directly. */
3964 if (XVECLEN (trueop1
, 0) == 2
3965 && CONST_INT_P (XVECEXP (trueop1
, 0, 0))
3966 && CONST_INT_P (XVECEXP (trueop1
, 0, 1))
3967 && GET_CODE (trueop0
) == VEC_CONCAT
3968 && GET_CODE (XEXP (trueop0
, 0)) == VEC_CONCAT
3969 && GET_MODE (XEXP (trueop0
, 0)) == mode
3970 && GET_CODE (XEXP (trueop0
, 1)) == VEC_CONCAT
3971 && GET_MODE (XEXP (trueop0
, 1)) == mode
)
3973 unsigned int i0
= INTVAL (XVECEXP (trueop1
, 0, 0));
3974 unsigned int i1
= INTVAL (XVECEXP (trueop1
, 0, 1));
3977 gcc_assert (i0
< 4 && i1
< 4);
3978 subop0
= XEXP (XEXP (trueop0
, i0
/ 2), i0
% 2);
3979 subop1
= XEXP (XEXP (trueop0
, i1
/ 2), i1
% 2);
3981 return simplify_gen_binary (VEC_CONCAT
, mode
, subop0
, subop1
);
3984 if (XVECLEN (trueop1
, 0) == 2
3985 && CONST_INT_P (XVECEXP (trueop1
, 0, 0))
3986 && CONST_INT_P (XVECEXP (trueop1
, 0, 1))
3987 && GET_CODE (trueop0
) == VEC_CONCAT
3988 && GET_MODE (trueop0
) == mode
)
3990 unsigned int i0
= INTVAL (XVECEXP (trueop1
, 0, 0));
3991 unsigned int i1
= INTVAL (XVECEXP (trueop1
, 0, 1));
3994 gcc_assert (i0
< 2 && i1
< 2);
3995 subop0
= XEXP (trueop0
, i0
);
3996 subop1
= XEXP (trueop0
, i1
);
3998 return simplify_gen_binary (VEC_CONCAT
, mode
, subop0
, subop1
);
4001 /* If we select one half of a vec_concat, return that. */
4003 if (GET_CODE (trueop0
) == VEC_CONCAT
4004 && (GET_MODE_NUNITS (GET_MODE (XEXP (trueop0
, 0)))
4006 && (GET_MODE_NUNITS (GET_MODE (XEXP (trueop0
, 1)))
4008 && CONST_INT_P (XVECEXP (trueop1
, 0, 0)))
4010 rtx subop0
= XEXP (trueop0
, 0);
4011 rtx subop1
= XEXP (trueop0
, 1);
4012 machine_mode mode0
= GET_MODE (subop0
);
4013 machine_mode mode1
= GET_MODE (subop1
);
4014 int i0
= INTVAL (XVECEXP (trueop1
, 0, 0));
4015 if (i0
== 0 && !side_effects_p (op1
) && mode
== mode0
)
4017 bool success
= true;
4018 for (int i
= 1; i
< l0
; ++i
)
4020 rtx j
= XVECEXP (trueop1
, 0, i
);
4021 if (!CONST_INT_P (j
) || INTVAL (j
) != i
)
4030 if (i0
== l0
&& !side_effects_p (op0
) && mode
== mode1
)
4032 bool success
= true;
4033 for (int i
= 1; i
< l1
; ++i
)
4035 rtx j
= XVECEXP (trueop1
, 0, i
);
4036 if (!CONST_INT_P (j
) || INTVAL (j
) != i0
+ i
)
4048 if (XVECLEN (trueop1
, 0) == 1
4049 && CONST_INT_P (XVECEXP (trueop1
, 0, 0))
4050 && GET_CODE (trueop0
) == VEC_CONCAT
)
4053 offset
= INTVAL (XVECEXP (trueop1
, 0, 0)) * GET_MODE_SIZE (mode
);
4055 /* Try to find the element in the VEC_CONCAT. */
4056 while (GET_MODE (vec
) != mode
4057 && GET_CODE (vec
) == VEC_CONCAT
)
4059 poly_int64 vec_size
;
4061 if (CONST_INT_P (XEXP (vec
, 0)))
4063 /* vec_concat of two const_ints doesn't make sense with
4064 respect to modes. */
4065 if (CONST_INT_P (XEXP (vec
, 1)))
4068 vec_size
= GET_MODE_SIZE (GET_MODE (trueop0
))
4069 - GET_MODE_SIZE (GET_MODE (XEXP (vec
, 1)));
4072 vec_size
= GET_MODE_SIZE (GET_MODE (XEXP (vec
, 0)));
4074 if (known_lt (offset
, vec_size
))
4075 vec
= XEXP (vec
, 0);
4076 else if (known_ge (offset
, vec_size
))
4079 vec
= XEXP (vec
, 1);
4083 vec
= avoid_constant_pool_reference (vec
);
4086 if (GET_MODE (vec
) == mode
)
4090 /* If we select elements in a vec_merge that all come from the same
4091 operand, select from that operand directly. */
4092 if (GET_CODE (op0
) == VEC_MERGE
)
4094 rtx trueop02
= avoid_constant_pool_reference (XEXP (op0
, 2));
4095 if (CONST_INT_P (trueop02
))
4097 unsigned HOST_WIDE_INT sel
= UINTVAL (trueop02
);
4098 bool all_operand0
= true;
4099 bool all_operand1
= true;
4100 for (int i
= 0; i
< XVECLEN (trueop1
, 0); i
++)
4102 rtx j
= XVECEXP (trueop1
, 0, i
);
4103 if (sel
& (HOST_WIDE_INT_1U
<< UINTVAL (j
)))
4104 all_operand1
= false;
4106 all_operand0
= false;
4108 if (all_operand0
&& !side_effects_p (XEXP (op0
, 1)))
4109 return simplify_gen_binary (VEC_SELECT
, mode
, XEXP (op0
, 0), op1
);
4110 if (all_operand1
&& !side_effects_p (XEXP (op0
, 0)))
4111 return simplify_gen_binary (VEC_SELECT
, mode
, XEXP (op0
, 1), op1
);
4115 /* If we have two nested selects that are inverses of each
4116 other, replace them with the source operand. */
4117 if (GET_CODE (trueop0
) == VEC_SELECT
4118 && GET_MODE (XEXP (trueop0
, 0)) == mode
)
4120 rtx op0_subop1
= XEXP (trueop0
, 1);
4121 gcc_assert (GET_CODE (op0_subop1
) == PARALLEL
);
4122 gcc_assert (known_eq (XVECLEN (trueop1
, 0), GET_MODE_NUNITS (mode
)));
4124 /* Apply the outer ordering vector to the inner one. (The inner
4125 ordering vector is expressly permitted to be of a different
4126 length than the outer one.) If the result is { 0, 1, ..., n-1 }
4127 then the two VEC_SELECTs cancel. */
4128 for (int i
= 0; i
< XVECLEN (trueop1
, 0); ++i
)
4130 rtx x
= XVECEXP (trueop1
, 0, i
);
4131 if (!CONST_INT_P (x
))
4133 rtx y
= XVECEXP (op0_subop1
, 0, INTVAL (x
));
4134 if (!CONST_INT_P (y
) || i
!= INTVAL (y
))
4137 return XEXP (trueop0
, 0);
4143 machine_mode op0_mode
= (GET_MODE (trueop0
) != VOIDmode
4144 ? GET_MODE (trueop0
)
4145 : GET_MODE_INNER (mode
));
4146 machine_mode op1_mode
= (GET_MODE (trueop1
) != VOIDmode
4147 ? GET_MODE (trueop1
)
4148 : GET_MODE_INNER (mode
));
4150 gcc_assert (VECTOR_MODE_P (mode
));
4151 gcc_assert (known_eq (GET_MODE_SIZE (op0_mode
)
4152 + GET_MODE_SIZE (op1_mode
),
4153 GET_MODE_SIZE (mode
)));
4155 if (VECTOR_MODE_P (op0_mode
))
4156 gcc_assert (GET_MODE_INNER (mode
)
4157 == GET_MODE_INNER (op0_mode
));
4159 gcc_assert (GET_MODE_INNER (mode
) == op0_mode
);
4161 if (VECTOR_MODE_P (op1_mode
))
4162 gcc_assert (GET_MODE_INNER (mode
)
4163 == GET_MODE_INNER (op1_mode
));
4165 gcc_assert (GET_MODE_INNER (mode
) == op1_mode
);
4167 unsigned int n_elts
, in_n_elts
;
4168 if ((GET_CODE (trueop0
) == CONST_VECTOR
4169 || CONST_SCALAR_INT_P (trueop0
)
4170 || CONST_DOUBLE_AS_FLOAT_P (trueop0
))
4171 && (GET_CODE (trueop1
) == CONST_VECTOR
4172 || CONST_SCALAR_INT_P (trueop1
)
4173 || CONST_DOUBLE_AS_FLOAT_P (trueop1
))
4174 && GET_MODE_NUNITS (mode
).is_constant (&n_elts
)
4175 && GET_MODE_NUNITS (op0_mode
).is_constant (&in_n_elts
))
4177 rtvec v
= rtvec_alloc (n_elts
);
4179 for (i
= 0; i
< n_elts
; i
++)
4183 if (!VECTOR_MODE_P (op0_mode
))
4184 RTVEC_ELT (v
, i
) = trueop0
;
4186 RTVEC_ELT (v
, i
) = CONST_VECTOR_ELT (trueop0
, i
);
4190 if (!VECTOR_MODE_P (op1_mode
))
4191 RTVEC_ELT (v
, i
) = trueop1
;
4193 RTVEC_ELT (v
, i
) = CONST_VECTOR_ELT (trueop1
,
4198 return gen_rtx_CONST_VECTOR (mode
, v
);
4201 /* Try to merge two VEC_SELECTs from the same vector into a single one.
4202 Restrict the transformation to avoid generating a VEC_SELECT with a
4203 mode unrelated to its operand. */
4204 if (GET_CODE (trueop0
) == VEC_SELECT
4205 && GET_CODE (trueop1
) == VEC_SELECT
4206 && rtx_equal_p (XEXP (trueop0
, 0), XEXP (trueop1
, 0))
4207 && GET_MODE (XEXP (trueop0
, 0)) == mode
)
4209 rtx par0
= XEXP (trueop0
, 1);
4210 rtx par1
= XEXP (trueop1
, 1);
4211 int len0
= XVECLEN (par0
, 0);
4212 int len1
= XVECLEN (par1
, 0);
4213 rtvec vec
= rtvec_alloc (len0
+ len1
);
4214 for (int i
= 0; i
< len0
; i
++)
4215 RTVEC_ELT (vec
, i
) = XVECEXP (par0
, 0, i
);
4216 for (int i
= 0; i
< len1
; i
++)
4217 RTVEC_ELT (vec
, len0
+ i
) = XVECEXP (par1
, 0, i
);
4218 return simplify_gen_binary (VEC_SELECT
, mode
, XEXP (trueop0
, 0),
4219 gen_rtx_PARALLEL (VOIDmode
, vec
));
4228 if (mode
== GET_MODE (op0
)
4229 && mode
== GET_MODE (op1
)
4230 && vec_duplicate_p (op0
, &elt0
)
4231 && vec_duplicate_p (op1
, &elt1
))
4233 /* Try applying the operator to ELT and see if that simplifies.
4234 We can duplicate the result if so.
4236 The reason we don't use simplify_gen_binary is that it isn't
4237 necessarily a win to convert things like:
4239 (plus:V (vec_duplicate:V (reg:S R1))
4240 (vec_duplicate:V (reg:S R2)))
4244 (vec_duplicate:V (plus:S (reg:S R1) (reg:S R2)))
4246 The first might be done entirely in vector registers while the
4247 second might need a move between register files. */
4248 tem
= simplify_binary_operation (code
, GET_MODE_INNER (mode
),
4251 return gen_vec_duplicate (mode
, tem
);
4257 /* Return true if binary operation OP distributes over addition in operand
4258 OPNO, with the other operand being held constant. OPNO counts from 1. */
4261 distributes_over_addition_p (rtx_code op
, int opno
)
4279 simplify_const_binary_operation (enum rtx_code code
, machine_mode mode
,
4282 if (VECTOR_MODE_P (mode
)
4283 && code
!= VEC_CONCAT
4284 && GET_CODE (op0
) == CONST_VECTOR
4285 && GET_CODE (op1
) == CONST_VECTOR
)
4288 if (CONST_VECTOR_STEPPED_P (op0
)
4289 && CONST_VECTOR_STEPPED_P (op1
))
4290 /* We can operate directly on the encoding if:
4292 a3 - a2 == a2 - a1 && b3 - b2 == b2 - b1
4294 (a3 op b3) - (a2 op b2) == (a2 op b2) - (a1 op b1)
4296 Addition and subtraction are the supported operators
4297 for which this is true. */
4298 step_ok_p
= (code
== PLUS
|| code
== MINUS
);
4299 else if (CONST_VECTOR_STEPPED_P (op0
))
4300 /* We can operate directly on stepped encodings if:
4304 (a3 op c) - (a2 op c) == (a2 op c) - (a1 op c)
4306 which is true if (x -> x op c) distributes over addition. */
4307 step_ok_p
= distributes_over_addition_p (code
, 1);
4309 /* Similarly in reverse. */
4310 step_ok_p
= distributes_over_addition_p (code
, 2);
4311 rtx_vector_builder builder
;
4312 if (!builder
.new_binary_operation (mode
, op0
, op1
, step_ok_p
))
4315 unsigned int count
= builder
.encoded_nelts ();
4316 for (unsigned int i
= 0; i
< count
; i
++)
4318 rtx x
= simplify_binary_operation (code
, GET_MODE_INNER (mode
),
4319 CONST_VECTOR_ELT (op0
, i
),
4320 CONST_VECTOR_ELT (op1
, i
));
4321 if (!x
|| !valid_for_const_vector_p (mode
, x
))
4323 builder
.quick_push (x
);
4325 return builder
.build ();
4328 if (VECTOR_MODE_P (mode
)
4329 && code
== VEC_CONCAT
4330 && (CONST_SCALAR_INT_P (op0
)
4331 || CONST_FIXED_P (op0
)
4332 || CONST_DOUBLE_AS_FLOAT_P (op0
))
4333 && (CONST_SCALAR_INT_P (op1
)
4334 || CONST_DOUBLE_AS_FLOAT_P (op1
)
4335 || CONST_FIXED_P (op1
)))
4337 /* Both inputs have a constant number of elements, so the result
4339 unsigned n_elts
= GET_MODE_NUNITS (mode
).to_constant ();
4340 rtvec v
= rtvec_alloc (n_elts
);
4342 gcc_assert (n_elts
>= 2);
4345 gcc_assert (GET_CODE (op0
) != CONST_VECTOR
);
4346 gcc_assert (GET_CODE (op1
) != CONST_VECTOR
);
4348 RTVEC_ELT (v
, 0) = op0
;
4349 RTVEC_ELT (v
, 1) = op1
;
4353 unsigned op0_n_elts
= GET_MODE_NUNITS (GET_MODE (op0
)).to_constant ();
4354 unsigned op1_n_elts
= GET_MODE_NUNITS (GET_MODE (op1
)).to_constant ();
4357 gcc_assert (GET_CODE (op0
) == CONST_VECTOR
);
4358 gcc_assert (GET_CODE (op1
) == CONST_VECTOR
);
4359 gcc_assert (op0_n_elts
+ op1_n_elts
== n_elts
);
4361 for (i
= 0; i
< op0_n_elts
; ++i
)
4362 RTVEC_ELT (v
, i
) = CONST_VECTOR_ELT (op0
, i
);
4363 for (i
= 0; i
< op1_n_elts
; ++i
)
4364 RTVEC_ELT (v
, op0_n_elts
+i
) = CONST_VECTOR_ELT (op1
, i
);
4367 return gen_rtx_CONST_VECTOR (mode
, v
);
4370 if (SCALAR_FLOAT_MODE_P (mode
)
4371 && CONST_DOUBLE_AS_FLOAT_P (op0
)
4372 && CONST_DOUBLE_AS_FLOAT_P (op1
)
4373 && mode
== GET_MODE (op0
) && mode
== GET_MODE (op1
))
4384 real_to_target (tmp0
, CONST_DOUBLE_REAL_VALUE (op0
),
4386 real_to_target (tmp1
, CONST_DOUBLE_REAL_VALUE (op1
),
4388 for (i
= 0; i
< 4; i
++)
4405 real_from_target (&r
, tmp0
, mode
);
4406 return const_double_from_real_value (r
, mode
);
4410 REAL_VALUE_TYPE f0
, f1
, value
, result
;
4411 const REAL_VALUE_TYPE
*opr0
, *opr1
;
4414 opr0
= CONST_DOUBLE_REAL_VALUE (op0
);
4415 opr1
= CONST_DOUBLE_REAL_VALUE (op1
);
4417 if (HONOR_SNANS (mode
)
4418 && (REAL_VALUE_ISSIGNALING_NAN (*opr0
)
4419 || REAL_VALUE_ISSIGNALING_NAN (*opr1
)))
4422 real_convert (&f0
, mode
, opr0
);
4423 real_convert (&f1
, mode
, opr1
);
4426 && real_equal (&f1
, &dconst0
)
4427 && (flag_trapping_math
|| ! MODE_HAS_INFINITIES (mode
)))
4430 if (MODE_HAS_INFINITIES (mode
) && HONOR_NANS (mode
)
4431 && flag_trapping_math
4432 && REAL_VALUE_ISINF (f0
) && REAL_VALUE_ISINF (f1
))
4434 int s0
= REAL_VALUE_NEGATIVE (f0
);
4435 int s1
= REAL_VALUE_NEGATIVE (f1
);
4440 /* Inf + -Inf = NaN plus exception. */
4445 /* Inf - Inf = NaN plus exception. */
4450 /* Inf / Inf = NaN plus exception. */
4457 if (code
== MULT
&& MODE_HAS_INFINITIES (mode
) && HONOR_NANS (mode
)
4458 && flag_trapping_math
4459 && ((REAL_VALUE_ISINF (f0
) && real_equal (&f1
, &dconst0
))
4460 || (REAL_VALUE_ISINF (f1
)
4461 && real_equal (&f0
, &dconst0
))))
4462 /* Inf * 0 = NaN plus exception. */
4465 inexact
= real_arithmetic (&value
, rtx_to_tree_code (code
),
4467 real_convert (&result
, mode
, &value
);
4469 /* Don't constant fold this floating point operation if
4470 the result has overflowed and flag_trapping_math. */
4472 if (flag_trapping_math
4473 && MODE_HAS_INFINITIES (mode
)
4474 && REAL_VALUE_ISINF (result
)
4475 && !REAL_VALUE_ISINF (f0
)
4476 && !REAL_VALUE_ISINF (f1
))
4477 /* Overflow plus exception. */
4480 /* Don't constant fold this floating point operation if the
4481 result may dependent upon the run-time rounding mode and
4482 flag_rounding_math is set, or if GCC's software emulation
4483 is unable to accurately represent the result. */
4485 if ((flag_rounding_math
4486 || (MODE_COMPOSITE_P (mode
) && !flag_unsafe_math_optimizations
))
4487 && (inexact
|| !real_identical (&result
, &value
)))
4490 return const_double_from_real_value (result
, mode
);
4494 /* We can fold some multi-word operations. */
4495 scalar_int_mode int_mode
;
4496 if (is_a
<scalar_int_mode
> (mode
, &int_mode
)
4497 && CONST_SCALAR_INT_P (op0
)
4498 && CONST_SCALAR_INT_P (op1
)
4499 && GET_MODE_PRECISION (int_mode
) <= MAX_BITSIZE_MODE_ANY_INT
)
4502 wi::overflow_type overflow
;
4503 rtx_mode_t pop0
= rtx_mode_t (op0
, int_mode
);
4504 rtx_mode_t pop1
= rtx_mode_t (op1
, int_mode
);
4506 #if TARGET_SUPPORTS_WIDE_INT == 0
4507 /* This assert keeps the simplification from producing a result
4508 that cannot be represented in a CONST_DOUBLE but a lot of
4509 upstream callers expect that this function never fails to
4510 simplify something and so you if you added this to the test
4511 above the code would die later anyway. If this assert
4512 happens, you just need to make the port support wide int. */
4513 gcc_assert (GET_MODE_PRECISION (int_mode
) <= HOST_BITS_PER_DOUBLE_INT
);
4518 result
= wi::sub (pop0
, pop1
);
4522 result
= wi::add (pop0
, pop1
);
4526 result
= wi::mul (pop0
, pop1
);
4530 result
= wi::div_trunc (pop0
, pop1
, SIGNED
, &overflow
);
4536 result
= wi::mod_trunc (pop0
, pop1
, SIGNED
, &overflow
);
4542 result
= wi::div_trunc (pop0
, pop1
, UNSIGNED
, &overflow
);
4548 result
= wi::mod_trunc (pop0
, pop1
, UNSIGNED
, &overflow
);
4554 result
= wi::bit_and (pop0
, pop1
);
4558 result
= wi::bit_or (pop0
, pop1
);
4562 result
= wi::bit_xor (pop0
, pop1
);
4566 result
= wi::smin (pop0
, pop1
);
4570 result
= wi::smax (pop0
, pop1
);
4574 result
= wi::umin (pop0
, pop1
);
4578 result
= wi::umax (pop0
, pop1
);
4585 wide_int wop1
= pop1
;
4586 if (SHIFT_COUNT_TRUNCATED
)
4587 wop1
= wi::umod_trunc (wop1
, GET_MODE_PRECISION (int_mode
));
4588 else if (wi::geu_p (wop1
, GET_MODE_PRECISION (int_mode
)))
4594 result
= wi::lrshift (pop0
, wop1
);
4598 result
= wi::arshift (pop0
, wop1
);
4602 result
= wi::lshift (pop0
, wop1
);
4613 if (wi::neg_p (pop1
))
4619 result
= wi::lrotate (pop0
, pop1
);
4623 result
= wi::rrotate (pop0
, pop1
);
4634 return immed_wide_int_const (result
, int_mode
);
4637 /* Handle polynomial integers. */
4638 if (NUM_POLY_INT_COEFFS
> 1
4639 && is_a
<scalar_int_mode
> (mode
, &int_mode
)
4640 && poly_int_rtx_p (op0
)
4641 && poly_int_rtx_p (op1
))
4643 poly_wide_int result
;
4647 result
= wi::to_poly_wide (op0
, mode
) + wi::to_poly_wide (op1
, mode
);
4651 result
= wi::to_poly_wide (op0
, mode
) - wi::to_poly_wide (op1
, mode
);
4655 if (CONST_SCALAR_INT_P (op1
))
4656 result
= wi::to_poly_wide (op0
, mode
) * rtx_mode_t (op1
, mode
);
4662 if (CONST_SCALAR_INT_P (op1
))
4664 wide_int shift
= rtx_mode_t (op1
, mode
);
4665 if (SHIFT_COUNT_TRUNCATED
)
4666 shift
= wi::umod_trunc (shift
, GET_MODE_PRECISION (int_mode
));
4667 else if (wi::geu_p (shift
, GET_MODE_PRECISION (int_mode
)))
4669 result
= wi::to_poly_wide (op0
, mode
) << shift
;
4676 if (!CONST_SCALAR_INT_P (op1
)
4677 || !can_ior_p (wi::to_poly_wide (op0
, mode
),
4678 rtx_mode_t (op1
, mode
), &result
))
4685 return immed_wide_int_const (result
, int_mode
);
4693 /* Return a positive integer if X should sort after Y. The value
4694 returned is 1 if and only if X and Y are both regs. */
4697 simplify_plus_minus_op_data_cmp (rtx x
, rtx y
)
4701 result
= (commutative_operand_precedence (y
)
4702 - commutative_operand_precedence (x
));
4704 return result
+ result
;
4706 /* Group together equal REGs to do more simplification. */
4707 if (REG_P (x
) && REG_P (y
))
4708 return REGNO (x
) > REGNO (y
);
4713 /* Simplify and canonicalize a PLUS or MINUS, at least one of whose
4714 operands may be another PLUS or MINUS.
4716 Rather than test for specific case, we do this by a brute-force method
4717 and do all possible simplifications until no more changes occur. Then
4718 we rebuild the operation.
4720 May return NULL_RTX when no changes were made. */
4723 simplify_plus_minus (enum rtx_code code
, machine_mode mode
, rtx op0
,
4726 struct simplify_plus_minus_op_data
4733 int changed
, n_constants
, canonicalized
= 0;
4736 memset (ops
, 0, sizeof ops
);
4738 /* Set up the two operands and then expand them until nothing has been
4739 changed. If we run out of room in our array, give up; this should
4740 almost never happen. */
4745 ops
[1].neg
= (code
== MINUS
);
4752 for (i
= 0; i
< n_ops
; i
++)
4754 rtx this_op
= ops
[i
].op
;
4755 int this_neg
= ops
[i
].neg
;
4756 enum rtx_code this_code
= GET_CODE (this_op
);
4762 if (n_ops
== ARRAY_SIZE (ops
))
4765 ops
[n_ops
].op
= XEXP (this_op
, 1);
4766 ops
[n_ops
].neg
= (this_code
== MINUS
) ^ this_neg
;
4769 ops
[i
].op
= XEXP (this_op
, 0);
4771 /* If this operand was negated then we will potentially
4772 canonicalize the expression. Similarly if we don't
4773 place the operands adjacent we're re-ordering the
4774 expression and thus might be performing a
4775 canonicalization. Ignore register re-ordering.
4776 ??? It might be better to shuffle the ops array here,
4777 but then (plus (plus (A, B), plus (C, D))) wouldn't
4778 be seen as non-canonical. */
4781 && !(REG_P (ops
[i
].op
) && REG_P (ops
[n_ops
- 1].op
))))
4786 ops
[i
].op
= XEXP (this_op
, 0);
4787 ops
[i
].neg
= ! this_neg
;
4793 if (n_ops
!= ARRAY_SIZE (ops
)
4794 && GET_CODE (XEXP (this_op
, 0)) == PLUS
4795 && CONSTANT_P (XEXP (XEXP (this_op
, 0), 0))
4796 && CONSTANT_P (XEXP (XEXP (this_op
, 0), 1)))
4798 ops
[i
].op
= XEXP (XEXP (this_op
, 0), 0);
4799 ops
[n_ops
].op
= XEXP (XEXP (this_op
, 0), 1);
4800 ops
[n_ops
].neg
= this_neg
;
4808 /* ~a -> (-a - 1) */
4809 if (n_ops
!= ARRAY_SIZE (ops
))
4811 ops
[n_ops
].op
= CONSTM1_RTX (mode
);
4812 ops
[n_ops
++].neg
= this_neg
;
4813 ops
[i
].op
= XEXP (this_op
, 0);
4814 ops
[i
].neg
= !this_neg
;
4820 CASE_CONST_SCALAR_INT
:
4821 case CONST_POLY_INT
:
4825 ops
[i
].op
= neg_poly_int_rtx (mode
, this_op
);
4839 if (n_constants
> 1)
4842 gcc_assert (n_ops
>= 2);
4844 /* If we only have two operands, we can avoid the loops. */
4847 enum rtx_code code
= ops
[0].neg
|| ops
[1].neg
? MINUS
: PLUS
;
4850 /* Get the two operands. Be careful with the order, especially for
4851 the cases where code == MINUS. */
4852 if (ops
[0].neg
&& ops
[1].neg
)
4854 lhs
= gen_rtx_NEG (mode
, ops
[0].op
);
4857 else if (ops
[0].neg
)
4868 return simplify_const_binary_operation (code
, mode
, lhs
, rhs
);
4871 /* Now simplify each pair of operands until nothing changes. */
4874 /* Insertion sort is good enough for a small array. */
4875 for (i
= 1; i
< n_ops
; i
++)
4877 struct simplify_plus_minus_op_data save
;
4881 cmp
= simplify_plus_minus_op_data_cmp (ops
[j
].op
, ops
[i
].op
);
4884 /* Just swapping registers doesn't count as canonicalization. */
4890 ops
[j
+ 1] = ops
[j
];
4892 && simplify_plus_minus_op_data_cmp (ops
[j
].op
, save
.op
) > 0);
4897 for (i
= n_ops
- 1; i
> 0; i
--)
4898 for (j
= i
- 1; j
>= 0; j
--)
4900 rtx lhs
= ops
[j
].op
, rhs
= ops
[i
].op
;
4901 int lneg
= ops
[j
].neg
, rneg
= ops
[i
].neg
;
4903 if (lhs
!= 0 && rhs
!= 0)
4905 enum rtx_code ncode
= PLUS
;
4911 std::swap (lhs
, rhs
);
4913 else if (swap_commutative_operands_p (lhs
, rhs
))
4914 std::swap (lhs
, rhs
);
4916 if ((GET_CODE (lhs
) == CONST
|| CONST_INT_P (lhs
))
4917 && (GET_CODE (rhs
) == CONST
|| CONST_INT_P (rhs
)))
4919 rtx tem_lhs
, tem_rhs
;
4921 tem_lhs
= GET_CODE (lhs
) == CONST
? XEXP (lhs
, 0) : lhs
;
4922 tem_rhs
= GET_CODE (rhs
) == CONST
? XEXP (rhs
, 0) : rhs
;
4923 tem
= simplify_binary_operation (ncode
, mode
, tem_lhs
,
4926 if (tem
&& !CONSTANT_P (tem
))
4927 tem
= gen_rtx_CONST (GET_MODE (tem
), tem
);
4930 tem
= simplify_binary_operation (ncode
, mode
, lhs
, rhs
);
4934 /* Reject "simplifications" that just wrap the two
4935 arguments in a CONST. Failure to do so can result
4936 in infinite recursion with simplify_binary_operation
4937 when it calls us to simplify CONST operations.
4938 Also, if we find such a simplification, don't try
4939 any more combinations with this rhs: We must have
4940 something like symbol+offset, ie. one of the
4941 trivial CONST expressions we handle later. */
4942 if (GET_CODE (tem
) == CONST
4943 && GET_CODE (XEXP (tem
, 0)) == ncode
4944 && XEXP (XEXP (tem
, 0), 0) == lhs
4945 && XEXP (XEXP (tem
, 0), 1) == rhs
)
4948 if (GET_CODE (tem
) == NEG
)
4949 tem
= XEXP (tem
, 0), lneg
= !lneg
;
4950 if (poly_int_rtx_p (tem
) && lneg
)
4951 tem
= neg_poly_int_rtx (mode
, tem
), lneg
= 0;
4955 ops
[j
].op
= NULL_RTX
;
4965 /* Pack all the operands to the lower-numbered entries. */
4966 for (i
= 0, j
= 0; j
< n_ops
; j
++)
4975 /* If nothing changed, check that rematerialization of rtl instructions
4976 is still required. */
4979 /* Perform rematerialization if only all operands are registers and
4980 all operations are PLUS. */
4981 /* ??? Also disallow (non-global, non-frame) fixed registers to work
4982 around rs6000 and how it uses the CA register. See PR67145. */
4983 for (i
= 0; i
< n_ops
; i
++)
4985 || !REG_P (ops
[i
].op
)
4986 || (REGNO (ops
[i
].op
) < FIRST_PSEUDO_REGISTER
4987 && fixed_regs
[REGNO (ops
[i
].op
)]
4988 && !global_regs
[REGNO (ops
[i
].op
)]
4989 && ops
[i
].op
!= frame_pointer_rtx
4990 && ops
[i
].op
!= arg_pointer_rtx
4991 && ops
[i
].op
!= stack_pointer_rtx
))
4996 /* Create (minus -C X) instead of (neg (const (plus X C))). */
4998 && CONST_INT_P (ops
[1].op
)
4999 && CONSTANT_P (ops
[0].op
)
5001 return gen_rtx_fmt_ee (MINUS
, mode
, ops
[1].op
, ops
[0].op
);
5003 /* We suppressed creation of trivial CONST expressions in the
5004 combination loop to avoid recursion. Create one manually now.
5005 The combination loop should have ensured that there is exactly
5006 one CONST_INT, and the sort will have ensured that it is last
5007 in the array and that any other constant will be next-to-last. */
5010 && poly_int_rtx_p (ops
[n_ops
- 1].op
)
5011 && CONSTANT_P (ops
[n_ops
- 2].op
))
5013 rtx value
= ops
[n_ops
- 1].op
;
5014 if (ops
[n_ops
- 1].neg
^ ops
[n_ops
- 2].neg
)
5015 value
= neg_poly_int_rtx (mode
, value
);
5016 if (CONST_INT_P (value
))
5018 ops
[n_ops
- 2].op
= plus_constant (mode
, ops
[n_ops
- 2].op
,
5024 /* Put a non-negated operand first, if possible. */
5026 for (i
= 0; i
< n_ops
&& ops
[i
].neg
; i
++)
5029 ops
[0].op
= gen_rtx_NEG (mode
, ops
[0].op
);
5038 /* Now make the result by performing the requested operations. */
5041 for (i
= 1; i
< n_ops
; i
++)
5042 result
= gen_rtx_fmt_ee (ops
[i
].neg
? MINUS
: PLUS
,
5043 mode
, result
, ops
[i
].op
);
5048 /* Check whether an operand is suitable for calling simplify_plus_minus. */
5050 plus_minus_operand_p (const_rtx x
)
5052 return GET_CODE (x
) == PLUS
5053 || GET_CODE (x
) == MINUS
5054 || (GET_CODE (x
) == CONST
5055 && GET_CODE (XEXP (x
, 0)) == PLUS
5056 && CONSTANT_P (XEXP (XEXP (x
, 0), 0))
5057 && CONSTANT_P (XEXP (XEXP (x
, 0), 1)));
5060 /* Like simplify_binary_operation except used for relational operators.
5061 MODE is the mode of the result. If MODE is VOIDmode, both operands must
5062 not also be VOIDmode.
5064 CMP_MODE specifies in which mode the comparison is done in, so it is
5065 the mode of the operands. If CMP_MODE is VOIDmode, it is taken from
5066 the operands or, if both are VOIDmode, the operands are compared in
5067 "infinite precision". */
5069 simplify_relational_operation (enum rtx_code code
, machine_mode mode
,
5070 machine_mode cmp_mode
, rtx op0
, rtx op1
)
5072 rtx tem
, trueop0
, trueop1
;
5074 if (cmp_mode
== VOIDmode
)
5075 cmp_mode
= GET_MODE (op0
);
5076 if (cmp_mode
== VOIDmode
)
5077 cmp_mode
= GET_MODE (op1
);
5079 tem
= simplify_const_relational_operation (code
, cmp_mode
, op0
, op1
);
5082 if (SCALAR_FLOAT_MODE_P (mode
))
5084 if (tem
== const0_rtx
)
5085 return CONST0_RTX (mode
);
5086 #ifdef FLOAT_STORE_FLAG_VALUE
5088 REAL_VALUE_TYPE val
;
5089 val
= FLOAT_STORE_FLAG_VALUE (mode
);
5090 return const_double_from_real_value (val
, mode
);
5096 if (VECTOR_MODE_P (mode
))
5098 if (tem
== const0_rtx
)
5099 return CONST0_RTX (mode
);
5100 #ifdef VECTOR_STORE_FLAG_VALUE
5102 rtx val
= VECTOR_STORE_FLAG_VALUE (mode
);
5103 if (val
== NULL_RTX
)
5105 if (val
== const1_rtx
)
5106 return CONST1_RTX (mode
);
5108 return gen_const_vec_duplicate (mode
, val
);
5114 /* For vector comparison with scalar int result, it is unknown
5115 if the target means here a comparison into an integral bitmask,
5116 or comparison where all comparisons true mean const_true_rtx
5117 whole result, or where any comparisons true mean const_true_rtx
5118 whole result. For const0_rtx all the cases are the same. */
5119 if (VECTOR_MODE_P (cmp_mode
)
5120 && SCALAR_INT_MODE_P (mode
)
5121 && tem
== const_true_rtx
)
5127 /* For the following tests, ensure const0_rtx is op1. */
5128 if (swap_commutative_operands_p (op0
, op1
)
5129 || (op0
== const0_rtx
&& op1
!= const0_rtx
))
5130 std::swap (op0
, op1
), code
= swap_condition (code
);
5132 /* If op0 is a compare, extract the comparison arguments from it. */
5133 if (GET_CODE (op0
) == COMPARE
&& op1
== const0_rtx
)
5134 return simplify_gen_relational (code
, mode
, VOIDmode
,
5135 XEXP (op0
, 0), XEXP (op0
, 1));
5137 if (GET_MODE_CLASS (cmp_mode
) == MODE_CC
5141 trueop0
= avoid_constant_pool_reference (op0
);
5142 trueop1
= avoid_constant_pool_reference (op1
);
5143 return simplify_relational_operation_1 (code
, mode
, cmp_mode
,
5147 /* This part of simplify_relational_operation is only used when CMP_MODE
5148 is not in class MODE_CC (i.e. it is a real comparison).
5150 MODE is the mode of the result, while CMP_MODE specifies in which
5151 mode the comparison is done in, so it is the mode of the operands. */
5154 simplify_relational_operation_1 (enum rtx_code code
, machine_mode mode
,
5155 machine_mode cmp_mode
, rtx op0
, rtx op1
)
5157 enum rtx_code op0code
= GET_CODE (op0
);
5159 if (op1
== const0_rtx
&& COMPARISON_P (op0
))
5161 /* If op0 is a comparison, extract the comparison arguments
5165 if (GET_MODE (op0
) == mode
)
5166 return simplify_rtx (op0
);
5168 return simplify_gen_relational (GET_CODE (op0
), mode
, VOIDmode
,
5169 XEXP (op0
, 0), XEXP (op0
, 1));
5171 else if (code
== EQ
)
5173 enum rtx_code new_code
= reversed_comparison_code (op0
, NULL
);
5174 if (new_code
!= UNKNOWN
)
5175 return simplify_gen_relational (new_code
, mode
, VOIDmode
,
5176 XEXP (op0
, 0), XEXP (op0
, 1));
5180 /* (LTU/GEU (PLUS a C) C), where C is constant, can be simplified to
5181 (GEU/LTU a -C). Likewise for (LTU/GEU (PLUS a C) a). */
5182 if ((code
== LTU
|| code
== GEU
)
5183 && GET_CODE (op0
) == PLUS
5184 && CONST_INT_P (XEXP (op0
, 1))
5185 && (rtx_equal_p (op1
, XEXP (op0
, 0))
5186 || rtx_equal_p (op1
, XEXP (op0
, 1)))
5187 /* (LTU/GEU (PLUS a 0) 0) is not the same as (GEU/LTU a 0). */
5188 && XEXP (op0
, 1) != const0_rtx
)
5191 = simplify_gen_unary (NEG
, cmp_mode
, XEXP (op0
, 1), cmp_mode
);
5192 return simplify_gen_relational ((code
== LTU
? GEU
: LTU
), mode
,
5193 cmp_mode
, XEXP (op0
, 0), new_cmp
);
5196 /* (GTU (PLUS a C) (C - 1)) where C is a non-zero constant can be
5197 transformed into (LTU a -C). */
5198 if (code
== GTU
&& GET_CODE (op0
) == PLUS
&& CONST_INT_P (op1
)
5199 && CONST_INT_P (XEXP (op0
, 1))
5200 && (UINTVAL (op1
) == UINTVAL (XEXP (op0
, 1)) - 1)
5201 && XEXP (op0
, 1) != const0_rtx
)
5204 = simplify_gen_unary (NEG
, cmp_mode
, XEXP (op0
, 1), cmp_mode
);
5205 return simplify_gen_relational (LTU
, mode
, cmp_mode
,
5206 XEXP (op0
, 0), new_cmp
);
5209 /* Canonicalize (LTU/GEU (PLUS a b) b) as (LTU/GEU (PLUS a b) a). */
5210 if ((code
== LTU
|| code
== GEU
)
5211 && GET_CODE (op0
) == PLUS
5212 && rtx_equal_p (op1
, XEXP (op0
, 1))
5213 /* Don't recurse "infinitely" for (LTU/GEU (PLUS b b) b). */
5214 && !rtx_equal_p (op1
, XEXP (op0
, 0)))
5215 return simplify_gen_relational (code
, mode
, cmp_mode
, op0
,
5216 copy_rtx (XEXP (op0
, 0)));
5218 if (op1
== const0_rtx
)
5220 /* Canonicalize (GTU x 0) as (NE x 0). */
5222 return simplify_gen_relational (NE
, mode
, cmp_mode
, op0
, op1
);
5223 /* Canonicalize (LEU x 0) as (EQ x 0). */
5225 return simplify_gen_relational (EQ
, mode
, cmp_mode
, op0
, op1
);
5227 else if (op1
== const1_rtx
)
5232 /* Canonicalize (GE x 1) as (GT x 0). */
5233 return simplify_gen_relational (GT
, mode
, cmp_mode
,
5236 /* Canonicalize (GEU x 1) as (NE x 0). */
5237 return simplify_gen_relational (NE
, mode
, cmp_mode
,
5240 /* Canonicalize (LT x 1) as (LE x 0). */
5241 return simplify_gen_relational (LE
, mode
, cmp_mode
,
5244 /* Canonicalize (LTU x 1) as (EQ x 0). */
5245 return simplify_gen_relational (EQ
, mode
, cmp_mode
,
5251 else if (op1
== constm1_rtx
)
5253 /* Canonicalize (LE x -1) as (LT x 0). */
5255 return simplify_gen_relational (LT
, mode
, cmp_mode
, op0
, const0_rtx
);
5256 /* Canonicalize (GT x -1) as (GE x 0). */
5258 return simplify_gen_relational (GE
, mode
, cmp_mode
, op0
, const0_rtx
);
5261 /* (eq/ne (plus x cst1) cst2) simplifies to (eq/ne x (cst2 - cst1)) */
5262 if ((code
== EQ
|| code
== NE
)
5263 && (op0code
== PLUS
|| op0code
== MINUS
)
5265 && CONSTANT_P (XEXP (op0
, 1))
5266 && (INTEGRAL_MODE_P (cmp_mode
) || flag_unsafe_math_optimizations
))
5268 rtx x
= XEXP (op0
, 0);
5269 rtx c
= XEXP (op0
, 1);
5270 enum rtx_code invcode
= op0code
== PLUS
? MINUS
: PLUS
;
5271 rtx tem
= simplify_gen_binary (invcode
, cmp_mode
, op1
, c
);
5273 /* Detect an infinite recursive condition, where we oscillate at this
5274 simplification case between:
5275 A + B == C <---> C - B == A,
5276 where A, B, and C are all constants with non-simplifiable expressions,
5277 usually SYMBOL_REFs. */
5278 if (GET_CODE (tem
) == invcode
5280 && rtx_equal_p (c
, XEXP (tem
, 1)))
5283 return simplify_gen_relational (code
, mode
, cmp_mode
, x
, tem
);
5286 /* (ne:SI (zero_extract:SI FOO (const_int 1) BAR) (const_int 0))) is
5287 the same as (zero_extract:SI FOO (const_int 1) BAR). */
5288 scalar_int_mode int_mode
, int_cmp_mode
;
5290 && op1
== const0_rtx
5291 && is_int_mode (mode
, &int_mode
)
5292 && is_a
<scalar_int_mode
> (cmp_mode
, &int_cmp_mode
)
5293 /* ??? Work-around BImode bugs in the ia64 backend. */
5294 && int_mode
!= BImode
5295 && int_cmp_mode
!= BImode
5296 && nonzero_bits (op0
, int_cmp_mode
) == 1
5297 && STORE_FLAG_VALUE
== 1)
5298 return GET_MODE_SIZE (int_mode
) > GET_MODE_SIZE (int_cmp_mode
)
5299 ? simplify_gen_unary (ZERO_EXTEND
, int_mode
, op0
, int_cmp_mode
)
5300 : lowpart_subreg (int_mode
, op0
, int_cmp_mode
);
5302 /* (eq/ne (xor x y) 0) simplifies to (eq/ne x y). */
5303 if ((code
== EQ
|| code
== NE
)
5304 && op1
== const0_rtx
5306 return simplify_gen_relational (code
, mode
, cmp_mode
,
5307 XEXP (op0
, 0), XEXP (op0
, 1));
5309 /* (eq/ne (xor x y) x) simplifies to (eq/ne y 0). */
5310 if ((code
== EQ
|| code
== NE
)
5312 && rtx_equal_p (XEXP (op0
, 0), op1
)
5313 && !side_effects_p (XEXP (op0
, 0)))
5314 return simplify_gen_relational (code
, mode
, cmp_mode
, XEXP (op0
, 1),
5317 /* Likewise (eq/ne (xor x y) y) simplifies to (eq/ne x 0). */
5318 if ((code
== EQ
|| code
== NE
)
5320 && rtx_equal_p (XEXP (op0
, 1), op1
)
5321 && !side_effects_p (XEXP (op0
, 1)))
5322 return simplify_gen_relational (code
, mode
, cmp_mode
, XEXP (op0
, 0),
5325 /* (eq/ne (xor x C1) C2) simplifies to (eq/ne x (C1^C2)). */
5326 if ((code
== EQ
|| code
== NE
)
5328 && CONST_SCALAR_INT_P (op1
)
5329 && CONST_SCALAR_INT_P (XEXP (op0
, 1)))
5330 return simplify_gen_relational (code
, mode
, cmp_mode
, XEXP (op0
, 0),
5331 simplify_gen_binary (XOR
, cmp_mode
,
5332 XEXP (op0
, 1), op1
));
5334 /* Simplify eq/ne (and/ior x y) x/y) for targets with a BICS instruction or
5335 constant folding if x/y is a constant. */
5336 if ((code
== EQ
|| code
== NE
)
5337 && (op0code
== AND
|| op0code
== IOR
)
5338 && !side_effects_p (op1
)
5339 && op1
!= CONST0_RTX (cmp_mode
))
5341 /* Both (eq/ne (and x y) x) and (eq/ne (ior x y) y) simplify to
5342 (eq/ne (and (not y) x) 0). */
5343 if ((op0code
== AND
&& rtx_equal_p (XEXP (op0
, 0), op1
))
5344 || (op0code
== IOR
&& rtx_equal_p (XEXP (op0
, 1), op1
)))
5346 rtx not_y
= simplify_gen_unary (NOT
, cmp_mode
, XEXP (op0
, 1),
5348 rtx lhs
= simplify_gen_binary (AND
, cmp_mode
, not_y
, XEXP (op0
, 0));
5350 return simplify_gen_relational (code
, mode
, cmp_mode
, lhs
,
5351 CONST0_RTX (cmp_mode
));
5354 /* Both (eq/ne (and x y) y) and (eq/ne (ior x y) x) simplify to
5355 (eq/ne (and (not x) y) 0). */
5356 if ((op0code
== AND
&& rtx_equal_p (XEXP (op0
, 1), op1
))
5357 || (op0code
== IOR
&& rtx_equal_p (XEXP (op0
, 0), op1
)))
5359 rtx not_x
= simplify_gen_unary (NOT
, cmp_mode
, XEXP (op0
, 0),
5361 rtx lhs
= simplify_gen_binary (AND
, cmp_mode
, not_x
, XEXP (op0
, 1));
5363 return simplify_gen_relational (code
, mode
, cmp_mode
, lhs
,
5364 CONST0_RTX (cmp_mode
));
5368 /* (eq/ne (bswap x) C1) simplifies to (eq/ne x C2) with C2 swapped. */
5369 if ((code
== EQ
|| code
== NE
)
5370 && GET_CODE (op0
) == BSWAP
5371 && CONST_SCALAR_INT_P (op1
))
5372 return simplify_gen_relational (code
, mode
, cmp_mode
, XEXP (op0
, 0),
5373 simplify_gen_unary (BSWAP
, cmp_mode
,
5376 /* (eq/ne (bswap x) (bswap y)) simplifies to (eq/ne x y). */
5377 if ((code
== EQ
|| code
== NE
)
5378 && GET_CODE (op0
) == BSWAP
5379 && GET_CODE (op1
) == BSWAP
)
5380 return simplify_gen_relational (code
, mode
, cmp_mode
,
5381 XEXP (op0
, 0), XEXP (op1
, 0));
5383 if (op0code
== POPCOUNT
&& op1
== const0_rtx
)
5389 /* (eq (popcount x) (const_int 0)) -> (eq x (const_int 0)). */
5390 return simplify_gen_relational (EQ
, mode
, GET_MODE (XEXP (op0
, 0)),
5391 XEXP (op0
, 0), const0_rtx
);
5396 /* (ne (popcount x) (const_int 0)) -> (ne x (const_int 0)). */
5397 return simplify_gen_relational (NE
, mode
, GET_MODE (XEXP (op0
, 0)),
5398 XEXP (op0
, 0), const0_rtx
);
5417 /* Convert the known results for EQ, LT, GT, LTU, GTU contained in
5418 KNOWN_RESULT to a CONST_INT, based on the requested comparison CODE
5419 For KNOWN_RESULT to make sense it should be either CMP_EQ, or the
5420 logical OR of one of (CMP_LT, CMP_GT) and one of (CMP_LTU, CMP_GTU).
5421 For floating-point comparisons, assume that the operands were ordered. */
5424 comparison_result (enum rtx_code code
, int known_results
)
5430 return (known_results
& CMP_EQ
) ? const_true_rtx
: const0_rtx
;
5433 return (known_results
& CMP_EQ
) ? const0_rtx
: const_true_rtx
;
5437 return (known_results
& CMP_LT
) ? const_true_rtx
: const0_rtx
;
5440 return (known_results
& CMP_LT
) ? const0_rtx
: const_true_rtx
;
5444 return (known_results
& CMP_GT
) ? const_true_rtx
: const0_rtx
;
5447 return (known_results
& CMP_GT
) ? const0_rtx
: const_true_rtx
;
5450 return (known_results
& CMP_LTU
) ? const_true_rtx
: const0_rtx
;
5452 return (known_results
& CMP_LTU
) ? const0_rtx
: const_true_rtx
;
5455 return (known_results
& CMP_GTU
) ? const_true_rtx
: const0_rtx
;
5457 return (known_results
& CMP_GTU
) ? const0_rtx
: const_true_rtx
;
5460 return const_true_rtx
;
5468 /* Check if the given comparison (done in the given MODE) is actually
5469 a tautology or a contradiction. If the mode is VOIDmode, the
5470 comparison is done in "infinite precision". If no simplification
5471 is possible, this function returns zero. Otherwise, it returns
5472 either const_true_rtx or const0_rtx. */
5475 simplify_const_relational_operation (enum rtx_code code
,
5483 gcc_assert (mode
!= VOIDmode
5484 || (GET_MODE (op0
) == VOIDmode
5485 && GET_MODE (op1
) == VOIDmode
));
5487 /* If op0 is a compare, extract the comparison arguments from it. */
5488 if (GET_CODE (op0
) == COMPARE
&& op1
== const0_rtx
)
5490 op1
= XEXP (op0
, 1);
5491 op0
= XEXP (op0
, 0);
5493 if (GET_MODE (op0
) != VOIDmode
)
5494 mode
= GET_MODE (op0
);
5495 else if (GET_MODE (op1
) != VOIDmode
)
5496 mode
= GET_MODE (op1
);
5501 /* We can't simplify MODE_CC values since we don't know what the
5502 actual comparison is. */
5503 if (GET_MODE_CLASS (GET_MODE (op0
)) == MODE_CC
|| CC0_P (op0
))
5506 /* Make sure the constant is second. */
5507 if (swap_commutative_operands_p (op0
, op1
))
5509 std::swap (op0
, op1
);
5510 code
= swap_condition (code
);
5513 trueop0
= avoid_constant_pool_reference (op0
);
5514 trueop1
= avoid_constant_pool_reference (op1
);
5516 /* For integer comparisons of A and B maybe we can simplify A - B and can
5517 then simplify a comparison of that with zero. If A and B are both either
5518 a register or a CONST_INT, this can't help; testing for these cases will
5519 prevent infinite recursion here and speed things up.
5521 We can only do this for EQ and NE comparisons as otherwise we may
5522 lose or introduce overflow which we cannot disregard as undefined as
5523 we do not know the signedness of the operation on either the left or
5524 the right hand side of the comparison. */
5526 if (INTEGRAL_MODE_P (mode
) && trueop1
!= const0_rtx
5527 && (code
== EQ
|| code
== NE
)
5528 && ! ((REG_P (op0
) || CONST_INT_P (trueop0
))
5529 && (REG_P (op1
) || CONST_INT_P (trueop1
)))
5530 && (tem
= simplify_binary_operation (MINUS
, mode
, op0
, op1
)) != 0
5531 /* We cannot do this if tem is a nonzero address. */
5532 && ! nonzero_address_p (tem
))
5533 return simplify_const_relational_operation (signed_condition (code
),
5534 mode
, tem
, const0_rtx
);
5536 if (! HONOR_NANS (mode
) && code
== ORDERED
)
5537 return const_true_rtx
;
5539 if (! HONOR_NANS (mode
) && code
== UNORDERED
)
5542 /* For modes without NaNs, if the two operands are equal, we know the
5543 result except if they have side-effects. Even with NaNs we know
5544 the result of unordered comparisons and, if signaling NaNs are
5545 irrelevant, also the result of LT/GT/LTGT. */
5546 if ((! HONOR_NANS (trueop0
)
5547 || code
== UNEQ
|| code
== UNLE
|| code
== UNGE
5548 || ((code
== LT
|| code
== GT
|| code
== LTGT
)
5549 && ! HONOR_SNANS (trueop0
)))
5550 && rtx_equal_p (trueop0
, trueop1
)
5551 && ! side_effects_p (trueop0
))
5552 return comparison_result (code
, CMP_EQ
);
5554 /* If the operands are floating-point constants, see if we can fold
5556 if (CONST_DOUBLE_AS_FLOAT_P (trueop0
)
5557 && CONST_DOUBLE_AS_FLOAT_P (trueop1
)
5558 && SCALAR_FLOAT_MODE_P (GET_MODE (trueop0
)))
5560 const REAL_VALUE_TYPE
*d0
= CONST_DOUBLE_REAL_VALUE (trueop0
);
5561 const REAL_VALUE_TYPE
*d1
= CONST_DOUBLE_REAL_VALUE (trueop1
);
5563 /* Comparisons are unordered iff at least one of the values is NaN. */
5564 if (REAL_VALUE_ISNAN (*d0
) || REAL_VALUE_ISNAN (*d1
))
5574 return const_true_rtx
;
5587 return comparison_result (code
,
5588 (real_equal (d0
, d1
) ? CMP_EQ
:
5589 real_less (d0
, d1
) ? CMP_LT
: CMP_GT
));
5592 /* Otherwise, see if the operands are both integers. */
5593 if ((GET_MODE_CLASS (mode
) == MODE_INT
|| mode
== VOIDmode
)
5594 && CONST_SCALAR_INT_P (trueop0
) && CONST_SCALAR_INT_P (trueop1
))
5596 /* It would be nice if we really had a mode here. However, the
5597 largest int representable on the target is as good as
5599 machine_mode cmode
= (mode
== VOIDmode
) ? MAX_MODE_INT
: mode
;
5600 rtx_mode_t ptrueop0
= rtx_mode_t (trueop0
, cmode
);
5601 rtx_mode_t ptrueop1
= rtx_mode_t (trueop1
, cmode
);
5603 if (wi::eq_p (ptrueop0
, ptrueop1
))
5604 return comparison_result (code
, CMP_EQ
);
5607 int cr
= wi::lts_p (ptrueop0
, ptrueop1
) ? CMP_LT
: CMP_GT
;
5608 cr
|= wi::ltu_p (ptrueop0
, ptrueop1
) ? CMP_LTU
: CMP_GTU
;
5609 return comparison_result (code
, cr
);
5613 /* Optimize comparisons with upper and lower bounds. */
5614 scalar_int_mode int_mode
;
5615 if (CONST_INT_P (trueop1
)
5616 && is_a
<scalar_int_mode
> (mode
, &int_mode
)
5617 && HWI_COMPUTABLE_MODE_P (int_mode
)
5618 && !side_effects_p (trueop0
))
5621 unsigned HOST_WIDE_INT nonzero
= nonzero_bits (trueop0
, int_mode
);
5622 HOST_WIDE_INT val
= INTVAL (trueop1
);
5623 HOST_WIDE_INT mmin
, mmax
;
5633 /* Get a reduced range if the sign bit is zero. */
5634 if (nonzero
<= (GET_MODE_MASK (int_mode
) >> 1))
5641 rtx mmin_rtx
, mmax_rtx
;
5642 get_mode_bounds (int_mode
, sign
, int_mode
, &mmin_rtx
, &mmax_rtx
);
5644 mmin
= INTVAL (mmin_rtx
);
5645 mmax
= INTVAL (mmax_rtx
);
5648 unsigned int sign_copies
5649 = num_sign_bit_copies (trueop0
, int_mode
);
5651 mmin
>>= (sign_copies
- 1);
5652 mmax
>>= (sign_copies
- 1);
5658 /* x >= y is always true for y <= mmin, always false for y > mmax. */
5660 if ((unsigned HOST_WIDE_INT
) val
<= (unsigned HOST_WIDE_INT
) mmin
)
5661 return const_true_rtx
;
5662 if ((unsigned HOST_WIDE_INT
) val
> (unsigned HOST_WIDE_INT
) mmax
)
5667 return const_true_rtx
;
5672 /* x <= y is always true for y >= mmax, always false for y < mmin. */
5674 if ((unsigned HOST_WIDE_INT
) val
>= (unsigned HOST_WIDE_INT
) mmax
)
5675 return const_true_rtx
;
5676 if ((unsigned HOST_WIDE_INT
) val
< (unsigned HOST_WIDE_INT
) mmin
)
5681 return const_true_rtx
;
5687 /* x == y is always false for y out of range. */
5688 if (val
< mmin
|| val
> mmax
)
5692 /* x > y is always false for y >= mmax, always true for y < mmin. */
5694 if ((unsigned HOST_WIDE_INT
) val
>= (unsigned HOST_WIDE_INT
) mmax
)
5696 if ((unsigned HOST_WIDE_INT
) val
< (unsigned HOST_WIDE_INT
) mmin
)
5697 return const_true_rtx
;
5703 return const_true_rtx
;
5706 /* x < y is always false for y <= mmin, always true for y > mmax. */
5708 if ((unsigned HOST_WIDE_INT
) val
<= (unsigned HOST_WIDE_INT
) mmin
)
5710 if ((unsigned HOST_WIDE_INT
) val
> (unsigned HOST_WIDE_INT
) mmax
)
5711 return const_true_rtx
;
5717 return const_true_rtx
;
5721 /* x != y is always true for y out of range. */
5722 if (val
< mmin
|| val
> mmax
)
5723 return const_true_rtx
;
5731 /* Optimize integer comparisons with zero. */
5732 if (is_a
<scalar_int_mode
> (mode
, &int_mode
)
5733 && trueop1
== const0_rtx
5734 && !side_effects_p (trueop0
))
5736 /* Some addresses are known to be nonzero. We don't know
5737 their sign, but equality comparisons are known. */
5738 if (nonzero_address_p (trueop0
))
5740 if (code
== EQ
|| code
== LEU
)
5742 if (code
== NE
|| code
== GTU
)
5743 return const_true_rtx
;
5746 /* See if the first operand is an IOR with a constant. If so, we
5747 may be able to determine the result of this comparison. */
5748 if (GET_CODE (op0
) == IOR
)
5750 rtx inner_const
= avoid_constant_pool_reference (XEXP (op0
, 1));
5751 if (CONST_INT_P (inner_const
) && inner_const
!= const0_rtx
)
5753 int sign_bitnum
= GET_MODE_PRECISION (int_mode
) - 1;
5754 int has_sign
= (HOST_BITS_PER_WIDE_INT
>= sign_bitnum
5755 && (UINTVAL (inner_const
)
5766 return const_true_rtx
;
5770 return const_true_rtx
;
5784 /* Optimize comparison of ABS with zero. */
5785 if (trueop1
== CONST0_RTX (mode
) && !side_effects_p (trueop0
)
5786 && (GET_CODE (trueop0
) == ABS
5787 || (GET_CODE (trueop0
) == FLOAT_EXTEND
5788 && GET_CODE (XEXP (trueop0
, 0)) == ABS
)))
5793 /* Optimize abs(x) < 0.0. */
5794 if (!INTEGRAL_MODE_P (mode
) && !HONOR_SNANS (mode
))
5799 /* Optimize abs(x) >= 0.0. */
5800 if (!INTEGRAL_MODE_P (mode
) && !HONOR_NANS (mode
))
5801 return const_true_rtx
;
5805 /* Optimize ! (abs(x) < 0.0). */
5806 return const_true_rtx
;
5816 /* Recognize expressions of the form (X CMP 0) ? VAL : OP (X)
5817 where OP is CLZ or CTZ and VAL is the value from CLZ_DEFINED_VALUE_AT_ZERO
5818 or CTZ_DEFINED_VALUE_AT_ZERO respectively and return OP (X) if the expression
5819 can be simplified to that or NULL_RTX if not.
5820 Assume X is compared against zero with CMP_CODE and the true
5821 arm is TRUE_VAL and the false arm is FALSE_VAL. */
5824 simplify_cond_clz_ctz (rtx x
, rtx_code cmp_code
, rtx true_val
, rtx false_val
)
5826 if (cmp_code
!= EQ
&& cmp_code
!= NE
)
5829 /* Result on X == 0 and X !=0 respectively. */
5830 rtx on_zero
, on_nonzero
;
5834 on_nonzero
= false_val
;
5838 on_zero
= false_val
;
5839 on_nonzero
= true_val
;
5842 rtx_code op_code
= GET_CODE (on_nonzero
);
5843 if ((op_code
!= CLZ
&& op_code
!= CTZ
)
5844 || !rtx_equal_p (XEXP (on_nonzero
, 0), x
)
5845 || !CONST_INT_P (on_zero
))
5848 HOST_WIDE_INT op_val
;
5849 scalar_int_mode mode ATTRIBUTE_UNUSED
5850 = as_a
<scalar_int_mode
> (GET_MODE (XEXP (on_nonzero
, 0)));
5851 if (((op_code
== CLZ
&& CLZ_DEFINED_VALUE_AT_ZERO (mode
, op_val
))
5852 || (op_code
== CTZ
&& CTZ_DEFINED_VALUE_AT_ZERO (mode
, op_val
)))
5853 && op_val
== INTVAL (on_zero
))
5859 /* Try to simplify X given that it appears within operand OP of a
5860 VEC_MERGE operation whose mask is MASK. X need not use the same
5861 vector mode as the VEC_MERGE, but it must have the same number of
5864 Return the simplified X on success, otherwise return NULL_RTX. */
5867 simplify_merge_mask (rtx x
, rtx mask
, int op
)
5869 gcc_assert (VECTOR_MODE_P (GET_MODE (x
)));
5870 poly_uint64 nunits
= GET_MODE_NUNITS (GET_MODE (x
));
5871 if (GET_CODE (x
) == VEC_MERGE
&& rtx_equal_p (XEXP (x
, 2), mask
))
5873 if (side_effects_p (XEXP (x
, 1 - op
)))
5876 return XEXP (x
, op
);
5879 && VECTOR_MODE_P (GET_MODE (XEXP (x
, 0)))
5880 && known_eq (GET_MODE_NUNITS (GET_MODE (XEXP (x
, 0))), nunits
))
5882 rtx top0
= simplify_merge_mask (XEXP (x
, 0), mask
, op
);
5884 return simplify_gen_unary (GET_CODE (x
), GET_MODE (x
), top0
,
5885 GET_MODE (XEXP (x
, 0)));
5888 && VECTOR_MODE_P (GET_MODE (XEXP (x
, 0)))
5889 && known_eq (GET_MODE_NUNITS (GET_MODE (XEXP (x
, 0))), nunits
)
5890 && VECTOR_MODE_P (GET_MODE (XEXP (x
, 1)))
5891 && known_eq (GET_MODE_NUNITS (GET_MODE (XEXP (x
, 1))), nunits
))
5893 rtx top0
= simplify_merge_mask (XEXP (x
, 0), mask
, op
);
5894 rtx top1
= simplify_merge_mask (XEXP (x
, 1), mask
, op
);
5897 if (COMPARISON_P (x
))
5898 return simplify_gen_relational (GET_CODE (x
), GET_MODE (x
),
5899 GET_MODE (XEXP (x
, 0)) != VOIDmode
5900 ? GET_MODE (XEXP (x
, 0))
5901 : GET_MODE (XEXP (x
, 1)),
5902 top0
? top0
: XEXP (x
, 0),
5903 top1
? top1
: XEXP (x
, 1));
5905 return simplify_gen_binary (GET_CODE (x
), GET_MODE (x
),
5906 top0
? top0
: XEXP (x
, 0),
5907 top1
? top1
: XEXP (x
, 1));
5910 if (GET_RTX_CLASS (GET_CODE (x
)) == RTX_TERNARY
5911 && VECTOR_MODE_P (GET_MODE (XEXP (x
, 0)))
5912 && known_eq (GET_MODE_NUNITS (GET_MODE (XEXP (x
, 0))), nunits
)
5913 && VECTOR_MODE_P (GET_MODE (XEXP (x
, 1)))
5914 && known_eq (GET_MODE_NUNITS (GET_MODE (XEXP (x
, 1))), nunits
)
5915 && VECTOR_MODE_P (GET_MODE (XEXP (x
, 2)))
5916 && known_eq (GET_MODE_NUNITS (GET_MODE (XEXP (x
, 2))), nunits
))
5918 rtx top0
= simplify_merge_mask (XEXP (x
, 0), mask
, op
);
5919 rtx top1
= simplify_merge_mask (XEXP (x
, 1), mask
, op
);
5920 rtx top2
= simplify_merge_mask (XEXP (x
, 2), mask
, op
);
5921 if (top0
|| top1
|| top2
)
5922 return simplify_gen_ternary (GET_CODE (x
), GET_MODE (x
),
5923 GET_MODE (XEXP (x
, 0)),
5924 top0
? top0
: XEXP (x
, 0),
5925 top1
? top1
: XEXP (x
, 1),
5926 top2
? top2
: XEXP (x
, 2));
5932 /* Simplify CODE, an operation with result mode MODE and three operands,
5933 OP0, OP1, and OP2. OP0_MODE was the mode of OP0 before it became
5934 a constant. Return 0 if no simplifications is possible. */
5937 simplify_ternary_operation (enum rtx_code code
, machine_mode mode
,
5938 machine_mode op0_mode
, rtx op0
, rtx op1
,
5941 bool any_change
= false;
5943 scalar_int_mode int_mode
, int_op0_mode
;
5944 unsigned int n_elts
;
5949 /* Simplify negations around the multiplication. */
5950 /* -a * -b + c => a * b + c. */
5951 if (GET_CODE (op0
) == NEG
)
5953 tem
= simplify_unary_operation (NEG
, mode
, op1
, mode
);
5955 op1
= tem
, op0
= XEXP (op0
, 0), any_change
= true;
5957 else if (GET_CODE (op1
) == NEG
)
5959 tem
= simplify_unary_operation (NEG
, mode
, op0
, mode
);
5961 op0
= tem
, op1
= XEXP (op1
, 0), any_change
= true;
5964 /* Canonicalize the two multiplication operands. */
5965 /* a * -b + c => -b * a + c. */
5966 if (swap_commutative_operands_p (op0
, op1
))
5967 std::swap (op0
, op1
), any_change
= true;
5970 return gen_rtx_FMA (mode
, op0
, op1
, op2
);
5975 if (CONST_INT_P (op0
)
5976 && CONST_INT_P (op1
)
5977 && CONST_INT_P (op2
)
5978 && is_a
<scalar_int_mode
> (mode
, &int_mode
)
5979 && INTVAL (op1
) + INTVAL (op2
) <= GET_MODE_PRECISION (int_mode
)
5980 && HWI_COMPUTABLE_MODE_P (int_mode
))
5982 /* Extracting a bit-field from a constant */
5983 unsigned HOST_WIDE_INT val
= UINTVAL (op0
);
5984 HOST_WIDE_INT op1val
= INTVAL (op1
);
5985 HOST_WIDE_INT op2val
= INTVAL (op2
);
5986 if (!BITS_BIG_ENDIAN
)
5988 else if (is_a
<scalar_int_mode
> (op0_mode
, &int_op0_mode
))
5989 val
>>= GET_MODE_PRECISION (int_op0_mode
) - op2val
- op1val
;
5991 /* Not enough information to calculate the bit position. */
5994 if (HOST_BITS_PER_WIDE_INT
!= op1val
)
5996 /* First zero-extend. */
5997 val
&= (HOST_WIDE_INT_1U
<< op1val
) - 1;
5998 /* If desired, propagate sign bit. */
5999 if (code
== SIGN_EXTRACT
6000 && (val
& (HOST_WIDE_INT_1U
<< (op1val
- 1)))
6002 val
|= ~ ((HOST_WIDE_INT_1U
<< op1val
) - 1);
6005 return gen_int_mode (val
, int_mode
);
6010 if (CONST_INT_P (op0
))
6011 return op0
!= const0_rtx
? op1
: op2
;
6013 /* Convert c ? a : a into "a". */
6014 if (rtx_equal_p (op1
, op2
) && ! side_effects_p (op0
))
6017 /* Convert a != b ? a : b into "a". */
6018 if (GET_CODE (op0
) == NE
6019 && ! side_effects_p (op0
)
6020 && ! HONOR_NANS (mode
)
6021 && ! HONOR_SIGNED_ZEROS (mode
)
6022 && ((rtx_equal_p (XEXP (op0
, 0), op1
)
6023 && rtx_equal_p (XEXP (op0
, 1), op2
))
6024 || (rtx_equal_p (XEXP (op0
, 0), op2
)
6025 && rtx_equal_p (XEXP (op0
, 1), op1
))))
6028 /* Convert a == b ? a : b into "b". */
6029 if (GET_CODE (op0
) == EQ
6030 && ! side_effects_p (op0
)
6031 && ! HONOR_NANS (mode
)
6032 && ! HONOR_SIGNED_ZEROS (mode
)
6033 && ((rtx_equal_p (XEXP (op0
, 0), op1
)
6034 && rtx_equal_p (XEXP (op0
, 1), op2
))
6035 || (rtx_equal_p (XEXP (op0
, 0), op2
)
6036 && rtx_equal_p (XEXP (op0
, 1), op1
))))
6039 /* Convert (!c) != {0,...,0} ? a : b into
6040 c != {0,...,0} ? b : a for vector modes. */
6041 if (VECTOR_MODE_P (GET_MODE (op1
))
6042 && GET_CODE (op0
) == NE
6043 && GET_CODE (XEXP (op0
, 0)) == NOT
6044 && GET_CODE (XEXP (op0
, 1)) == CONST_VECTOR
)
6046 rtx cv
= XEXP (op0
, 1);
6049 if (!CONST_VECTOR_NUNITS (cv
).is_constant (&nunits
))
6052 for (int i
= 0; i
< nunits
; ++i
)
6053 if (CONST_VECTOR_ELT (cv
, i
) != const0_rtx
)
6060 rtx new_op0
= gen_rtx_NE (GET_MODE (op0
),
6061 XEXP (XEXP (op0
, 0), 0),
6063 rtx retval
= gen_rtx_IF_THEN_ELSE (mode
, new_op0
, op2
, op1
);
6068 /* Convert x == 0 ? N : clz (x) into clz (x) when
6069 CLZ_DEFINED_VALUE_AT_ZERO is defined to N for the mode of x.
6070 Similarly for ctz (x). */
6071 if (COMPARISON_P (op0
) && !side_effects_p (op0
)
6072 && XEXP (op0
, 1) == const0_rtx
)
6075 = simplify_cond_clz_ctz (XEXP (op0
, 0), GET_CODE (op0
),
6081 if (COMPARISON_P (op0
) && ! side_effects_p (op0
))
6083 machine_mode cmp_mode
= (GET_MODE (XEXP (op0
, 0)) == VOIDmode
6084 ? GET_MODE (XEXP (op0
, 1))
6085 : GET_MODE (XEXP (op0
, 0)));
6088 /* Look for happy constants in op1 and op2. */
6089 if (CONST_INT_P (op1
) && CONST_INT_P (op2
))
6091 HOST_WIDE_INT t
= INTVAL (op1
);
6092 HOST_WIDE_INT f
= INTVAL (op2
);
6094 if (t
== STORE_FLAG_VALUE
&& f
== 0)
6095 code
= GET_CODE (op0
);
6096 else if (t
== 0 && f
== STORE_FLAG_VALUE
)
6099 tmp
= reversed_comparison_code (op0
, NULL
);
6107 return simplify_gen_relational (code
, mode
, cmp_mode
,
6108 XEXP (op0
, 0), XEXP (op0
, 1));
6111 temp
= simplify_relational_operation (GET_CODE (op0
), op0_mode
,
6112 cmp_mode
, XEXP (op0
, 0),
6115 /* See if any simplifications were possible. */
6118 if (CONST_INT_P (temp
))
6119 return temp
== const0_rtx
? op2
: op1
;
6121 return gen_rtx_IF_THEN_ELSE (mode
, temp
, op1
, op2
);
6127 gcc_assert (GET_MODE (op0
) == mode
);
6128 gcc_assert (GET_MODE (op1
) == mode
);
6129 gcc_assert (VECTOR_MODE_P (mode
));
6130 trueop2
= avoid_constant_pool_reference (op2
);
6131 if (CONST_INT_P (trueop2
)
6132 && GET_MODE_NUNITS (mode
).is_constant (&n_elts
))
6134 unsigned HOST_WIDE_INT sel
= UINTVAL (trueop2
);
6135 unsigned HOST_WIDE_INT mask
;
6136 if (n_elts
== HOST_BITS_PER_WIDE_INT
)
6139 mask
= (HOST_WIDE_INT_1U
<< n_elts
) - 1;
6141 if (!(sel
& mask
) && !side_effects_p (op0
))
6143 if ((sel
& mask
) == mask
&& !side_effects_p (op1
))
6146 rtx trueop0
= avoid_constant_pool_reference (op0
);
6147 rtx trueop1
= avoid_constant_pool_reference (op1
);
6148 if (GET_CODE (trueop0
) == CONST_VECTOR
6149 && GET_CODE (trueop1
) == CONST_VECTOR
)
6151 rtvec v
= rtvec_alloc (n_elts
);
6154 for (i
= 0; i
< n_elts
; i
++)
6155 RTVEC_ELT (v
, i
) = ((sel
& (HOST_WIDE_INT_1U
<< i
))
6156 ? CONST_VECTOR_ELT (trueop0
, i
)
6157 : CONST_VECTOR_ELT (trueop1
, i
));
6158 return gen_rtx_CONST_VECTOR (mode
, v
);
6161 /* Replace (vec_merge (vec_merge a b m) c n) with (vec_merge b c n)
6162 if no element from a appears in the result. */
6163 if (GET_CODE (op0
) == VEC_MERGE
)
6165 tem
= avoid_constant_pool_reference (XEXP (op0
, 2));
6166 if (CONST_INT_P (tem
))
6168 unsigned HOST_WIDE_INT sel0
= UINTVAL (tem
);
6169 if (!(sel
& sel0
& mask
) && !side_effects_p (XEXP (op0
, 0)))
6170 return simplify_gen_ternary (code
, mode
, mode
,
6171 XEXP (op0
, 1), op1
, op2
);
6172 if (!(sel
& ~sel0
& mask
) && !side_effects_p (XEXP (op0
, 1)))
6173 return simplify_gen_ternary (code
, mode
, mode
,
6174 XEXP (op0
, 0), op1
, op2
);
6177 if (GET_CODE (op1
) == VEC_MERGE
)
6179 tem
= avoid_constant_pool_reference (XEXP (op1
, 2));
6180 if (CONST_INT_P (tem
))
6182 unsigned HOST_WIDE_INT sel1
= UINTVAL (tem
);
6183 if (!(~sel
& sel1
& mask
) && !side_effects_p (XEXP (op1
, 0)))
6184 return simplify_gen_ternary (code
, mode
, mode
,
6185 op0
, XEXP (op1
, 1), op2
);
6186 if (!(~sel
& ~sel1
& mask
) && !side_effects_p (XEXP (op1
, 1)))
6187 return simplify_gen_ternary (code
, mode
, mode
,
6188 op0
, XEXP (op1
, 0), op2
);
6192 /* Replace (vec_merge (vec_duplicate (vec_select a parallel (i))) a 1 << i)
6194 if (GET_CODE (op0
) == VEC_DUPLICATE
6195 && GET_CODE (XEXP (op0
, 0)) == VEC_SELECT
6196 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == PARALLEL
6197 && known_eq (GET_MODE_NUNITS (GET_MODE (XEXP (op0
, 0))), 1))
6199 tem
= XVECEXP ((XEXP (XEXP (op0
, 0), 1)), 0, 0);
6200 if (CONST_INT_P (tem
) && CONST_INT_P (op2
))
6202 if (XEXP (XEXP (op0
, 0), 0) == op1
6203 && UINTVAL (op2
) == HOST_WIDE_INT_1U
<< UINTVAL (tem
))
6207 /* Replace (vec_merge (vec_duplicate (X)) (const_vector [A, B])
6209 with (vec_concat (X) (B)) if N == 1 or
6210 (vec_concat (A) (X)) if N == 2. */
6211 if (GET_CODE (op0
) == VEC_DUPLICATE
6212 && GET_CODE (op1
) == CONST_VECTOR
6213 && known_eq (CONST_VECTOR_NUNITS (op1
), 2)
6214 && known_eq (GET_MODE_NUNITS (GET_MODE (op0
)), 2)
6215 && IN_RANGE (sel
, 1, 2))
6217 rtx newop0
= XEXP (op0
, 0);
6218 rtx newop1
= CONST_VECTOR_ELT (op1
, 2 - sel
);
6220 std::swap (newop0
, newop1
);
6221 return simplify_gen_binary (VEC_CONCAT
, mode
, newop0
, newop1
);
6223 /* Replace (vec_merge (vec_duplicate x) (vec_concat (y) (z)) (const_int N))
6224 with (vec_concat x z) if N == 1, or (vec_concat y x) if N == 2.
6225 Only applies for vectors of two elements. */
6226 if (GET_CODE (op0
) == VEC_DUPLICATE
6227 && GET_CODE (op1
) == VEC_CONCAT
6228 && known_eq (GET_MODE_NUNITS (GET_MODE (op0
)), 2)
6229 && known_eq (GET_MODE_NUNITS (GET_MODE (op1
)), 2)
6230 && IN_RANGE (sel
, 1, 2))
6232 rtx newop0
= XEXP (op0
, 0);
6233 rtx newop1
= XEXP (op1
, 2 - sel
);
6234 rtx otherop
= XEXP (op1
, sel
- 1);
6236 std::swap (newop0
, newop1
);
6237 /* Don't want to throw away the other part of the vec_concat if
6238 it has side-effects. */
6239 if (!side_effects_p (otherop
))
6240 return simplify_gen_binary (VEC_CONCAT
, mode
, newop0
, newop1
);
6245 (vec_merge:outer (vec_duplicate:outer x:inner)
6246 (subreg:outer y:inner 0)
6249 with (vec_concat:outer x:inner y:inner) if N == 1,
6250 or (vec_concat:outer y:inner x:inner) if N == 2.
6252 Implicitly, this means we have a paradoxical subreg, but such
6253 a check is cheap, so make it anyway.
6255 Only applies for vectors of two elements. */
6256 if (GET_CODE (op0
) == VEC_DUPLICATE
6257 && GET_CODE (op1
) == SUBREG
6258 && GET_MODE (op1
) == GET_MODE (op0
)
6259 && GET_MODE (SUBREG_REG (op1
)) == GET_MODE (XEXP (op0
, 0))
6260 && paradoxical_subreg_p (op1
)
6261 && subreg_lowpart_p (op1
)
6262 && known_eq (GET_MODE_NUNITS (GET_MODE (op0
)), 2)
6263 && known_eq (GET_MODE_NUNITS (GET_MODE (op1
)), 2)
6264 && IN_RANGE (sel
, 1, 2))
6266 rtx newop0
= XEXP (op0
, 0);
6267 rtx newop1
= SUBREG_REG (op1
);
6269 std::swap (newop0
, newop1
);
6270 return simplify_gen_binary (VEC_CONCAT
, mode
, newop0
, newop1
);
6273 /* Same as above but with switched operands:
6274 Replace (vec_merge:outer (subreg:outer x:inner 0)
6275 (vec_duplicate:outer y:inner)
6278 with (vec_concat:outer x:inner y:inner) if N == 1,
6279 or (vec_concat:outer y:inner x:inner) if N == 2. */
6280 if (GET_CODE (op1
) == VEC_DUPLICATE
6281 && GET_CODE (op0
) == SUBREG
6282 && GET_MODE (op0
) == GET_MODE (op1
)
6283 && GET_MODE (SUBREG_REG (op0
)) == GET_MODE (XEXP (op1
, 0))
6284 && paradoxical_subreg_p (op0
)
6285 && subreg_lowpart_p (op0
)
6286 && known_eq (GET_MODE_NUNITS (GET_MODE (op1
)), 2)
6287 && known_eq (GET_MODE_NUNITS (GET_MODE (op0
)), 2)
6288 && IN_RANGE (sel
, 1, 2))
6290 rtx newop0
= SUBREG_REG (op0
);
6291 rtx newop1
= XEXP (op1
, 0);
6293 std::swap (newop0
, newop1
);
6294 return simplify_gen_binary (VEC_CONCAT
, mode
, newop0
, newop1
);
6297 /* Replace (vec_merge (vec_duplicate x) (vec_duplicate y)
6299 with (vec_concat x y) or (vec_concat y x) depending on value
6301 if (GET_CODE (op0
) == VEC_DUPLICATE
6302 && GET_CODE (op1
) == VEC_DUPLICATE
6303 && known_eq (GET_MODE_NUNITS (GET_MODE (op0
)), 2)
6304 && known_eq (GET_MODE_NUNITS (GET_MODE (op1
)), 2)
6305 && IN_RANGE (sel
, 1, 2))
6307 rtx newop0
= XEXP (op0
, 0);
6308 rtx newop1
= XEXP (op1
, 0);
6310 std::swap (newop0
, newop1
);
6312 return simplify_gen_binary (VEC_CONCAT
, mode
, newop0
, newop1
);
6316 if (rtx_equal_p (op0
, op1
)
6317 && !side_effects_p (op2
) && !side_effects_p (op1
))
6320 if (!side_effects_p (op2
))
6323 = may_trap_p (op0
) ? NULL_RTX
: simplify_merge_mask (op0
, op2
, 0);
6325 = may_trap_p (op1
) ? NULL_RTX
: simplify_merge_mask (op1
, op2
, 1);
6327 return simplify_gen_ternary (code
, mode
, mode
,
6329 top1
? top1
: op1
, op2
);
6341 /* Try to calculate NUM_BYTES bytes of the target memory image of X,
6342 starting at byte FIRST_BYTE. Return true on success and add the
6343 bytes to BYTES, such that each byte has BITS_PER_UNIT bits and such
6344 that the bytes follow target memory order. Leave BYTES unmodified
6347 MODE is the mode of X. The caller must reserve NUM_BYTES bytes in
6348 BYTES before calling this function. */
6351 native_encode_rtx (machine_mode mode
, rtx x
, vec
<target_unit
> &bytes
,
6352 unsigned int first_byte
, unsigned int num_bytes
)
6354 /* Check the mode is sensible. */
6355 gcc_assert (GET_MODE (x
) == VOIDmode
6356 ? is_a
<scalar_int_mode
> (mode
)
6357 : mode
== GET_MODE (x
));
6359 if (GET_CODE (x
) == CONST_VECTOR
)
6361 /* CONST_VECTOR_ELT follows target memory order, so no shuffling
6362 is necessary. The only complication is that MODE_VECTOR_BOOL
6363 vectors can have several elements per byte. */
6364 unsigned int elt_bits
= vector_element_size (GET_MODE_BITSIZE (mode
),
6365 GET_MODE_NUNITS (mode
));
6366 unsigned int elt
= first_byte
* BITS_PER_UNIT
/ elt_bits
;
6367 if (elt_bits
< BITS_PER_UNIT
)
6369 /* This is the only case in which elements can be smaller than
6371 gcc_assert (GET_MODE_CLASS (mode
) == MODE_VECTOR_BOOL
);
6372 for (unsigned int i
= 0; i
< num_bytes
; ++i
)
6374 target_unit value
= 0;
6375 for (unsigned int j
= 0; j
< BITS_PER_UNIT
; j
+= elt_bits
)
6377 value
|= (INTVAL (CONST_VECTOR_ELT (x
, elt
)) & 1) << j
;
6380 bytes
.quick_push (value
);
6385 unsigned int start
= bytes
.length ();
6386 unsigned int elt_bytes
= GET_MODE_UNIT_SIZE (mode
);
6387 /* Make FIRST_BYTE relative to ELT. */
6388 first_byte
%= elt_bytes
;
6389 while (num_bytes
> 0)
6391 /* Work out how many bytes we want from element ELT. */
6392 unsigned int chunk_bytes
= MIN (num_bytes
, elt_bytes
- first_byte
);
6393 if (!native_encode_rtx (GET_MODE_INNER (mode
),
6394 CONST_VECTOR_ELT (x
, elt
), bytes
,
6395 first_byte
, chunk_bytes
))
6397 bytes
.truncate (start
);
6402 num_bytes
-= chunk_bytes
;
6407 /* All subsequent cases are limited to scalars. */
6409 if (!is_a
<scalar_mode
> (mode
, &smode
))
6412 /* Make sure that the region is in range. */
6413 unsigned int end_byte
= first_byte
+ num_bytes
;
6414 unsigned int mode_bytes
= GET_MODE_SIZE (smode
);
6415 gcc_assert (end_byte
<= mode_bytes
);
6417 if (CONST_SCALAR_INT_P (x
))
6419 /* The target memory layout is affected by both BYTES_BIG_ENDIAN
6420 and WORDS_BIG_ENDIAN. Use the subreg machinery to get the lsb
6421 position of each byte. */
6422 rtx_mode_t
value (x
, smode
);
6423 wide_int_ref
value_wi (value
);
6424 for (unsigned int byte
= first_byte
; byte
< end_byte
; ++byte
)
6426 /* Always constant because the inputs are. */
6428 = subreg_size_lsb (1, mode_bytes
, byte
).to_constant ();
6429 /* Operate directly on the encoding rather than using
6430 wi::extract_uhwi, so that we preserve the sign or zero
6431 extension for modes that are not a whole number of bits in
6432 size. (Zero extension is only used for the combination of
6433 innermode == BImode && STORE_FLAG_VALUE == 1). */
6434 unsigned int elt
= lsb
/ HOST_BITS_PER_WIDE_INT
;
6435 unsigned int shift
= lsb
% HOST_BITS_PER_WIDE_INT
;
6436 unsigned HOST_WIDE_INT uhwi
= value_wi
.elt (elt
);
6437 bytes
.quick_push (uhwi
>> shift
);
6442 if (CONST_DOUBLE_P (x
))
6444 /* real_to_target produces an array of integers in target memory order.
6445 All integers before the last one have 32 bits; the last one may
6446 have 32 bits or fewer, depending on whether the mode bitsize
6447 is divisible by 32. Each of these integers is then laid out
6448 in target memory as any other integer would be. */
6449 long el32
[MAX_BITSIZE_MODE_ANY_MODE
/ 32];
6450 real_to_target (el32
, CONST_DOUBLE_REAL_VALUE (x
), smode
);
6452 /* The (maximum) number of target bytes per element of el32. */
6453 unsigned int bytes_per_el32
= 32 / BITS_PER_UNIT
;
6454 gcc_assert (bytes_per_el32
!= 0);
6456 /* Build up the integers in a similar way to the CONST_SCALAR_INT_P
6458 for (unsigned int byte
= first_byte
; byte
< end_byte
; ++byte
)
6460 unsigned int index
= byte
/ bytes_per_el32
;
6461 unsigned int subbyte
= byte
% bytes_per_el32
;
6462 unsigned int int_bytes
= MIN (bytes_per_el32
,
6463 mode_bytes
- index
* bytes_per_el32
);
6464 /* Always constant because the inputs are. */
6466 = subreg_size_lsb (1, int_bytes
, subbyte
).to_constant ();
6467 bytes
.quick_push ((unsigned long) el32
[index
] >> lsb
);
6472 if (GET_CODE (x
) == CONST_FIXED
)
6474 for (unsigned int byte
= first_byte
; byte
< end_byte
; ++byte
)
6476 /* Always constant because the inputs are. */
6478 = subreg_size_lsb (1, mode_bytes
, byte
).to_constant ();
6479 unsigned HOST_WIDE_INT piece
= CONST_FIXED_VALUE_LOW (x
);
6480 if (lsb
>= HOST_BITS_PER_WIDE_INT
)
6482 lsb
-= HOST_BITS_PER_WIDE_INT
;
6483 piece
= CONST_FIXED_VALUE_HIGH (x
);
6485 bytes
.quick_push (piece
>> lsb
);
6493 /* Read a vector of mode MODE from the target memory image given by BYTES,
6494 starting at byte FIRST_BYTE. The vector is known to be encodable using
6495 NPATTERNS interleaved patterns with NELTS_PER_PATTERN elements each,
6496 and BYTES is known to have enough bytes to supply NPATTERNS *
6497 NELTS_PER_PATTERN vector elements. Each element of BYTES contains
6498 BITS_PER_UNIT bits and the bytes are in target memory order.
6500 Return the vector on success, otherwise return NULL_RTX. */
6503 native_decode_vector_rtx (machine_mode mode
, vec
<target_unit
> bytes
,
6504 unsigned int first_byte
, unsigned int npatterns
,
6505 unsigned int nelts_per_pattern
)
6507 rtx_vector_builder
builder (mode
, npatterns
, nelts_per_pattern
);
6509 unsigned int elt_bits
= vector_element_size (GET_MODE_BITSIZE (mode
),
6510 GET_MODE_NUNITS (mode
));
6511 if (elt_bits
< BITS_PER_UNIT
)
6513 /* This is the only case in which elements can be smaller than a byte.
6514 Element 0 is always in the lsb of the containing byte. */
6515 gcc_assert (GET_MODE_CLASS (mode
) == MODE_VECTOR_BOOL
);
6516 for (unsigned int i
= 0; i
< builder
.encoded_nelts (); ++i
)
6518 unsigned int bit_index
= first_byte
* BITS_PER_UNIT
+ i
* elt_bits
;
6519 unsigned int byte_index
= bit_index
/ BITS_PER_UNIT
;
6520 unsigned int lsb
= bit_index
% BITS_PER_UNIT
;
6521 builder
.quick_push (bytes
[byte_index
] & (1 << lsb
)
6522 ? CONST1_RTX (BImode
)
6523 : CONST0_RTX (BImode
));
6528 for (unsigned int i
= 0; i
< builder
.encoded_nelts (); ++i
)
6530 rtx x
= native_decode_rtx (GET_MODE_INNER (mode
), bytes
, first_byte
);
6533 builder
.quick_push (x
);
6534 first_byte
+= elt_bits
/ BITS_PER_UNIT
;
6537 return builder
.build ();
6540 /* Read an rtx of mode MODE from the target memory image given by BYTES,
6541 starting at byte FIRST_BYTE. Each element of BYTES contains BITS_PER_UNIT
6542 bits and the bytes are in target memory order. The image has enough
6543 values to specify all bytes of MODE.
6545 Return the rtx on success, otherwise return NULL_RTX. */
6548 native_decode_rtx (machine_mode mode
, vec
<target_unit
> bytes
,
6549 unsigned int first_byte
)
6551 if (VECTOR_MODE_P (mode
))
6553 /* If we know at compile time how many elements there are,
6554 pull each element directly from BYTES. */
6556 if (GET_MODE_NUNITS (mode
).is_constant (&nelts
))
6557 return native_decode_vector_rtx (mode
, bytes
, first_byte
, nelts
, 1);
6561 scalar_int_mode imode
;
6562 if (is_a
<scalar_int_mode
> (mode
, &imode
)
6563 && GET_MODE_PRECISION (imode
) <= MAX_BITSIZE_MODE_ANY_INT
)
6565 /* Pull the bytes msb first, so that we can use simple
6566 shift-and-insert wide_int operations. */
6567 unsigned int size
= GET_MODE_SIZE (imode
);
6568 wide_int
result (wi::zero (GET_MODE_PRECISION (imode
)));
6569 for (unsigned int i
= 0; i
< size
; ++i
)
6571 unsigned int lsb
= (size
- i
- 1) * BITS_PER_UNIT
;
6572 /* Always constant because the inputs are. */
6573 unsigned int subbyte
6574 = subreg_size_offset_from_lsb (1, size
, lsb
).to_constant ();
6575 result
<<= BITS_PER_UNIT
;
6576 result
|= bytes
[first_byte
+ subbyte
];
6578 return immed_wide_int_const (result
, imode
);
6581 scalar_float_mode fmode
;
6582 if (is_a
<scalar_float_mode
> (mode
, &fmode
))
6584 /* We need to build an array of integers in target memory order.
6585 All integers before the last one have 32 bits; the last one may
6586 have 32 bits or fewer, depending on whether the mode bitsize
6587 is divisible by 32. */
6588 long el32
[MAX_BITSIZE_MODE_ANY_MODE
/ 32];
6589 unsigned int num_el32
= CEIL (GET_MODE_BITSIZE (fmode
), 32);
6590 memset (el32
, 0, num_el32
* sizeof (long));
6592 /* The (maximum) number of target bytes per element of el32. */
6593 unsigned int bytes_per_el32
= 32 / BITS_PER_UNIT
;
6594 gcc_assert (bytes_per_el32
!= 0);
6596 unsigned int mode_bytes
= GET_MODE_SIZE (fmode
);
6597 for (unsigned int byte
= 0; byte
< mode_bytes
; ++byte
)
6599 unsigned int index
= byte
/ bytes_per_el32
;
6600 unsigned int subbyte
= byte
% bytes_per_el32
;
6601 unsigned int int_bytes
= MIN (bytes_per_el32
,
6602 mode_bytes
- index
* bytes_per_el32
);
6603 /* Always constant because the inputs are. */
6605 = subreg_size_lsb (1, int_bytes
, subbyte
).to_constant ();
6606 el32
[index
] |= (unsigned long) bytes
[first_byte
+ byte
] << lsb
;
6609 real_from_target (&r
, el32
, fmode
);
6610 return const_double_from_real_value (r
, fmode
);
6613 if (ALL_SCALAR_FIXED_POINT_MODE_P (mode
))
6615 scalar_mode smode
= as_a
<scalar_mode
> (mode
);
6621 unsigned int mode_bytes
= GET_MODE_SIZE (smode
);
6622 for (unsigned int byte
= 0; byte
< mode_bytes
; ++byte
)
6624 /* Always constant because the inputs are. */
6626 = subreg_size_lsb (1, mode_bytes
, byte
).to_constant ();
6627 unsigned HOST_WIDE_INT unit
= bytes
[first_byte
+ byte
];
6628 if (lsb
>= HOST_BITS_PER_WIDE_INT
)
6629 f
.data
.high
|= unit
<< (lsb
- HOST_BITS_PER_WIDE_INT
);
6631 f
.data
.low
|= unit
<< lsb
;
6633 return CONST_FIXED_FROM_FIXED_VALUE (f
, mode
);
6639 /* Simplify a byte offset BYTE into CONST_VECTOR X. The main purpose
6640 is to convert a runtime BYTE value into a constant one. */
6643 simplify_const_vector_byte_offset (rtx x
, poly_uint64 byte
)
6645 /* Cope with MODE_VECTOR_BOOL by operating on bits rather than bytes. */
6646 machine_mode mode
= GET_MODE (x
);
6647 unsigned int elt_bits
= vector_element_size (GET_MODE_BITSIZE (mode
),
6648 GET_MODE_NUNITS (mode
));
6649 /* The number of bits needed to encode one element from each pattern. */
6650 unsigned int sequence_bits
= CONST_VECTOR_NPATTERNS (x
) * elt_bits
;
6652 /* Identify the start point in terms of a sequence number and a byte offset
6653 within that sequence. */
6654 poly_uint64 first_sequence
;
6655 unsigned HOST_WIDE_INT subbit
;
6656 if (can_div_trunc_p (byte
* BITS_PER_UNIT
, sequence_bits
,
6657 &first_sequence
, &subbit
))
6659 unsigned int nelts_per_pattern
= CONST_VECTOR_NELTS_PER_PATTERN (x
);
6660 if (nelts_per_pattern
== 1)
6661 /* This is a duplicated vector, so the value of FIRST_SEQUENCE
6663 byte
= subbit
/ BITS_PER_UNIT
;
6664 else if (nelts_per_pattern
== 2 && known_gt (first_sequence
, 0U))
6666 /* The subreg drops the first element from each pattern and
6667 only uses the second element. Find the first sequence
6668 that starts on a byte boundary. */
6669 subbit
+= least_common_multiple (sequence_bits
, BITS_PER_UNIT
);
6670 byte
= subbit
/ BITS_PER_UNIT
;
6676 /* Subroutine of simplify_subreg in which:
6678 - X is known to be a CONST_VECTOR
6679 - OUTERMODE is known to be a vector mode
6681 Try to handle the subreg by operating on the CONST_VECTOR encoding
6682 rather than on each individual element of the CONST_VECTOR.
6684 Return the simplified subreg on success, otherwise return NULL_RTX. */
6687 simplify_const_vector_subreg (machine_mode outermode
, rtx x
,
6688 machine_mode innermode
, unsigned int first_byte
)
6690 /* Paradoxical subregs of vectors have dubious semantics. */
6691 if (paradoxical_subreg_p (outermode
, innermode
))
6694 /* We can only preserve the semantics of a stepped pattern if the new
6695 vector element is the same as the original one. */
6696 if (CONST_VECTOR_STEPPED_P (x
)
6697 && GET_MODE_INNER (outermode
) != GET_MODE_INNER (innermode
))
6700 /* Cope with MODE_VECTOR_BOOL by operating on bits rather than bytes. */
6701 unsigned int x_elt_bits
6702 = vector_element_size (GET_MODE_BITSIZE (innermode
),
6703 GET_MODE_NUNITS (innermode
));
6704 unsigned int out_elt_bits
6705 = vector_element_size (GET_MODE_BITSIZE (outermode
),
6706 GET_MODE_NUNITS (outermode
));
6708 /* The number of bits needed to encode one element from every pattern
6709 of the original vector. */
6710 unsigned int x_sequence_bits
= CONST_VECTOR_NPATTERNS (x
) * x_elt_bits
;
6712 /* The number of bits needed to encode one element from every pattern
6714 unsigned int out_sequence_bits
6715 = least_common_multiple (x_sequence_bits
, out_elt_bits
);
6717 /* Work out the number of interleaved patterns in the output vector
6718 and the number of encoded elements per pattern. */
6719 unsigned int out_npatterns
= out_sequence_bits
/ out_elt_bits
;
6720 unsigned int nelts_per_pattern
= CONST_VECTOR_NELTS_PER_PATTERN (x
);
6722 /* The encoding scheme requires the number of elements to be a multiple
6723 of the number of patterns, so that each pattern appears at least once
6724 and so that the same number of elements appear from each pattern. */
6725 bool ok_p
= multiple_p (GET_MODE_NUNITS (outermode
), out_npatterns
);
6726 unsigned int const_nunits
;
6727 if (GET_MODE_NUNITS (outermode
).is_constant (&const_nunits
)
6728 && (!ok_p
|| out_npatterns
* nelts_per_pattern
> const_nunits
))
6730 /* Either the encoding is invalid, or applying it would give us
6731 more elements than we need. Just encode each element directly. */
6732 out_npatterns
= const_nunits
;
6733 nelts_per_pattern
= 1;
6738 /* Get enough bytes of X to form the new encoding. */
6739 unsigned int buffer_bits
= out_npatterns
* nelts_per_pattern
* out_elt_bits
;
6740 unsigned int buffer_bytes
= CEIL (buffer_bits
, BITS_PER_UNIT
);
6741 auto_vec
<target_unit
, 128> buffer (buffer_bytes
);
6742 if (!native_encode_rtx (innermode
, x
, buffer
, first_byte
, buffer_bytes
))
6745 /* Reencode the bytes as OUTERMODE. */
6746 return native_decode_vector_rtx (outermode
, buffer
, 0, out_npatterns
,
6750 /* Try to simplify a subreg of a constant by encoding the subreg region
6751 as a sequence of target bytes and reading them back in the new mode.
6752 Return the new value on success, otherwise return null.
6754 The subreg has outer mode OUTERMODE, inner mode INNERMODE, inner value X
6755 and byte offset FIRST_BYTE. */
6758 simplify_immed_subreg (fixed_size_mode outermode
, rtx x
,
6759 machine_mode innermode
, unsigned int first_byte
)
6761 unsigned int buffer_bytes
= GET_MODE_SIZE (outermode
);
6762 auto_vec
<target_unit
, 128> buffer (buffer_bytes
);
6764 /* Some ports misuse CCmode. */
6765 if (GET_MODE_CLASS (outermode
) == MODE_CC
&& CONST_INT_P (x
))
6768 /* Paradoxical subregs read undefined values for bytes outside of the
6769 inner value. However, we have traditionally always sign-extended
6770 integer constants and zero-extended others. */
6771 unsigned int inner_bytes
= buffer_bytes
;
6772 if (paradoxical_subreg_p (outermode
, innermode
))
6774 if (!GET_MODE_SIZE (innermode
).is_constant (&inner_bytes
))
6777 target_unit filler
= 0;
6778 if (CONST_SCALAR_INT_P (x
) && wi::neg_p (rtx_mode_t (x
, innermode
)))
6781 /* Add any leading bytes due to big-endian layout. The number of
6782 bytes must be constant because both modes have constant size. */
6783 unsigned int leading_bytes
6784 = -byte_lowpart_offset (outermode
, innermode
).to_constant ();
6785 for (unsigned int i
= 0; i
< leading_bytes
; ++i
)
6786 buffer
.quick_push (filler
);
6788 if (!native_encode_rtx (innermode
, x
, buffer
, first_byte
, inner_bytes
))
6791 /* Add any trailing bytes due to little-endian layout. */
6792 while (buffer
.length () < buffer_bytes
)
6793 buffer
.quick_push (filler
);
6797 if (!native_encode_rtx (innermode
, x
, buffer
, first_byte
, inner_bytes
))
6800 return native_decode_rtx (outermode
, buffer
, 0);
6803 /* Simplify SUBREG:OUTERMODE(OP:INNERMODE, BYTE)
6804 Return 0 if no simplifications are possible. */
6806 simplify_subreg (machine_mode outermode
, rtx op
,
6807 machine_mode innermode
, poly_uint64 byte
)
6809 /* Little bit of sanity checking. */
6810 gcc_assert (innermode
!= VOIDmode
);
6811 gcc_assert (outermode
!= VOIDmode
);
6812 gcc_assert (innermode
!= BLKmode
);
6813 gcc_assert (outermode
!= BLKmode
);
6815 gcc_assert (GET_MODE (op
) == innermode
6816 || GET_MODE (op
) == VOIDmode
);
6818 poly_uint64 outersize
= GET_MODE_SIZE (outermode
);
6819 if (!multiple_p (byte
, outersize
))
6822 poly_uint64 innersize
= GET_MODE_SIZE (innermode
);
6823 if (maybe_ge (byte
, innersize
))
6826 if (outermode
== innermode
&& known_eq (byte
, 0U))
6829 if (GET_CODE (op
) == CONST_VECTOR
)
6830 byte
= simplify_const_vector_byte_offset (op
, byte
);
6832 if (multiple_p (byte
, GET_MODE_UNIT_SIZE (innermode
)))
6836 if (VECTOR_MODE_P (outermode
)
6837 && GET_MODE_INNER (outermode
) == GET_MODE_INNER (innermode
)
6838 && vec_duplicate_p (op
, &elt
))
6839 return gen_vec_duplicate (outermode
, elt
);
6841 if (outermode
== GET_MODE_INNER (innermode
)
6842 && vec_duplicate_p (op
, &elt
))
6846 if (CONST_SCALAR_INT_P (op
)
6847 || CONST_DOUBLE_AS_FLOAT_P (op
)
6848 || CONST_FIXED_P (op
)
6849 || GET_CODE (op
) == CONST_VECTOR
)
6851 unsigned HOST_WIDE_INT cbyte
;
6852 if (byte
.is_constant (&cbyte
))
6854 if (GET_CODE (op
) == CONST_VECTOR
&& VECTOR_MODE_P (outermode
))
6856 rtx tmp
= simplify_const_vector_subreg (outermode
, op
,
6862 fixed_size_mode fs_outermode
;
6863 if (is_a
<fixed_size_mode
> (outermode
, &fs_outermode
))
6864 return simplify_immed_subreg (fs_outermode
, op
, innermode
, cbyte
);
6868 /* Changing mode twice with SUBREG => just change it once,
6869 or not at all if changing back op starting mode. */
6870 if (GET_CODE (op
) == SUBREG
)
6872 machine_mode innermostmode
= GET_MODE (SUBREG_REG (op
));
6873 poly_uint64 innermostsize
= GET_MODE_SIZE (innermostmode
);
6876 if (outermode
== innermostmode
6877 && known_eq (byte
, 0U)
6878 && known_eq (SUBREG_BYTE (op
), 0))
6879 return SUBREG_REG (op
);
6881 /* Work out the memory offset of the final OUTERMODE value relative
6882 to the inner value of OP. */
6883 poly_int64 mem_offset
= subreg_memory_offset (outermode
,
6885 poly_int64 op_mem_offset
= subreg_memory_offset (op
);
6886 poly_int64 final_offset
= mem_offset
+ op_mem_offset
;
6888 /* See whether resulting subreg will be paradoxical. */
6889 if (!paradoxical_subreg_p (outermode
, innermostmode
))
6891 /* Bail out in case resulting subreg would be incorrect. */
6892 if (maybe_lt (final_offset
, 0)
6893 || maybe_ge (poly_uint64 (final_offset
), innermostsize
)
6894 || !multiple_p (final_offset
, outersize
))
6899 poly_int64 required_offset
= subreg_memory_offset (outermode
,
6901 if (maybe_ne (final_offset
, required_offset
))
6903 /* Paradoxical subregs always have byte offset 0. */
6907 /* Recurse for further possible simplifications. */
6908 newx
= simplify_subreg (outermode
, SUBREG_REG (op
), innermostmode
,
6912 if (validate_subreg (outermode
, innermostmode
,
6913 SUBREG_REG (op
), final_offset
))
6915 newx
= gen_rtx_SUBREG (outermode
, SUBREG_REG (op
), final_offset
);
6916 if (SUBREG_PROMOTED_VAR_P (op
)
6917 && SUBREG_PROMOTED_SIGN (op
) >= 0
6918 && GET_MODE_CLASS (outermode
) == MODE_INT
6919 && known_ge (outersize
, innersize
)
6920 && known_le (outersize
, innermostsize
)
6921 && subreg_lowpart_p (newx
))
6923 SUBREG_PROMOTED_VAR_P (newx
) = 1;
6924 SUBREG_PROMOTED_SET (newx
, SUBREG_PROMOTED_GET (op
));
6931 /* SUBREG of a hard register => just change the register number
6932 and/or mode. If the hard register is not valid in that mode,
6933 suppress this simplification. If the hard register is the stack,
6934 frame, or argument pointer, leave this as a SUBREG. */
6936 if (REG_P (op
) && HARD_REGISTER_P (op
))
6938 unsigned int regno
, final_regno
;
6941 final_regno
= simplify_subreg_regno (regno
, innermode
, byte
, outermode
);
6942 if (HARD_REGISTER_NUM_P (final_regno
))
6944 rtx x
= gen_rtx_REG_offset (op
, outermode
, final_regno
,
6945 subreg_memory_offset (outermode
,
6948 /* Propagate original regno. We don't have any way to specify
6949 the offset inside original regno, so do so only for lowpart.
6950 The information is used only by alias analysis that cannot
6951 grog partial register anyway. */
6953 if (known_eq (subreg_lowpart_offset (outermode
, innermode
), byte
))
6954 ORIGINAL_REGNO (x
) = ORIGINAL_REGNO (op
);
6959 /* If we have a SUBREG of a register that we are replacing and we are
6960 replacing it with a MEM, make a new MEM and try replacing the
6961 SUBREG with it. Don't do this if the MEM has a mode-dependent address
6962 or if we would be widening it. */
6965 && ! mode_dependent_address_p (XEXP (op
, 0), MEM_ADDR_SPACE (op
))
6966 /* Allow splitting of volatile memory references in case we don't
6967 have instruction to move the whole thing. */
6968 && (! MEM_VOLATILE_P (op
)
6969 || ! have_insn_for (SET
, innermode
))
6970 && known_le (outersize
, innersize
))
6971 return adjust_address_nv (op
, outermode
, byte
);
6973 /* Handle complex or vector values represented as CONCAT or VEC_CONCAT
6975 if (GET_CODE (op
) == CONCAT
6976 || GET_CODE (op
) == VEC_CONCAT
)
6978 poly_uint64 final_offset
;
6981 machine_mode part_mode
= GET_MODE (XEXP (op
, 0));
6982 if (part_mode
== VOIDmode
)
6983 part_mode
= GET_MODE_INNER (GET_MODE (op
));
6984 poly_uint64 part_size
= GET_MODE_SIZE (part_mode
);
6985 if (known_lt (byte
, part_size
))
6987 part
= XEXP (op
, 0);
6988 final_offset
= byte
;
6990 else if (known_ge (byte
, part_size
))
6992 part
= XEXP (op
, 1);
6993 final_offset
= byte
- part_size
;
6998 if (maybe_gt (final_offset
+ outersize
, part_size
))
7001 part_mode
= GET_MODE (part
);
7002 if (part_mode
== VOIDmode
)
7003 part_mode
= GET_MODE_INNER (GET_MODE (op
));
7004 res
= simplify_subreg (outermode
, part
, part_mode
, final_offset
);
7007 if (validate_subreg (outermode
, part_mode
, part
, final_offset
))
7008 return gen_rtx_SUBREG (outermode
, part
, final_offset
);
7013 (subreg (vec_merge (X)
7015 (const_int ((1 << N) | M)))
7016 (N * sizeof (outermode)))
7018 (subreg (X) (N * sizeof (outermode)))
7021 if (constant_multiple_p (byte
, GET_MODE_SIZE (outermode
), &idx
)
7022 && idx
< HOST_BITS_PER_WIDE_INT
7023 && GET_CODE (op
) == VEC_MERGE
7024 && GET_MODE_INNER (innermode
) == outermode
7025 && CONST_INT_P (XEXP (op
, 2))
7026 && (UINTVAL (XEXP (op
, 2)) & (HOST_WIDE_INT_1U
<< idx
)) != 0)
7027 return simplify_gen_subreg (outermode
, XEXP (op
, 0), innermode
, byte
);
7029 /* A SUBREG resulting from a zero extension may fold to zero if
7030 it extracts higher bits that the ZERO_EXTEND's source bits. */
7031 if (GET_CODE (op
) == ZERO_EXTEND
&& SCALAR_INT_MODE_P (innermode
))
7033 poly_uint64 bitpos
= subreg_lsb_1 (outermode
, innermode
, byte
);
7034 if (known_ge (bitpos
, GET_MODE_PRECISION (GET_MODE (XEXP (op
, 0)))))
7035 return CONST0_RTX (outermode
);
7038 scalar_int_mode int_outermode
, int_innermode
;
7039 if (is_a
<scalar_int_mode
> (outermode
, &int_outermode
)
7040 && is_a
<scalar_int_mode
> (innermode
, &int_innermode
)
7041 && known_eq (byte
, subreg_lowpart_offset (int_outermode
, int_innermode
)))
7043 /* Handle polynomial integers. The upper bits of a paradoxical
7044 subreg are undefined, so this is safe regardless of whether
7045 we're truncating or extending. */
7046 if (CONST_POLY_INT_P (op
))
7049 = poly_wide_int::from (const_poly_int_value (op
),
7050 GET_MODE_PRECISION (int_outermode
),
7052 return immed_wide_int_const (val
, int_outermode
);
7055 if (GET_MODE_PRECISION (int_outermode
)
7056 < GET_MODE_PRECISION (int_innermode
))
7058 rtx tem
= simplify_truncation (int_outermode
, op
, int_innermode
);
7064 /* If OP is a vector comparison and the subreg is not changing the
7065 number of elements or the size of the elements, change the result
7066 of the comparison to the new mode. */
7067 if (COMPARISON_P (op
)
7068 && VECTOR_MODE_P (outermode
)
7069 && VECTOR_MODE_P (innermode
)
7070 && known_eq (GET_MODE_NUNITS (outermode
), GET_MODE_NUNITS (innermode
))
7071 && known_eq (GET_MODE_UNIT_SIZE (outermode
),
7072 GET_MODE_UNIT_SIZE (innermode
)))
7073 return simplify_gen_relational (GET_CODE (op
), outermode
, innermode
,
7074 XEXP (op
, 0), XEXP (op
, 1));
7078 /* Make a SUBREG operation or equivalent if it folds. */
7081 simplify_gen_subreg (machine_mode outermode
, rtx op
,
7082 machine_mode innermode
, poly_uint64 byte
)
7086 newx
= simplify_subreg (outermode
, op
, innermode
, byte
);
7090 if (GET_CODE (op
) == SUBREG
7091 || GET_CODE (op
) == CONCAT
7092 || GET_MODE (op
) == VOIDmode
)
7095 if (validate_subreg (outermode
, innermode
, op
, byte
))
7096 return gen_rtx_SUBREG (outermode
, op
, byte
);
7101 /* Generates a subreg to get the least significant part of EXPR (in mode
7102 INNER_MODE) to OUTER_MODE. */
7105 lowpart_subreg (machine_mode outer_mode
, rtx expr
,
7106 machine_mode inner_mode
)
7108 return simplify_gen_subreg (outer_mode
, expr
, inner_mode
,
7109 subreg_lowpart_offset (outer_mode
, inner_mode
));
7112 /* Simplify X, an rtx expression.
7114 Return the simplified expression or NULL if no simplifications
7117 This is the preferred entry point into the simplification routines;
7118 however, we still allow passes to call the more specific routines.
7120 Right now GCC has three (yes, three) major bodies of RTL simplification
7121 code that need to be unified.
7123 1. fold_rtx in cse.c. This code uses various CSE specific
7124 information to aid in RTL simplification.
7126 2. simplify_rtx in combine.c. Similar to fold_rtx, except that
7127 it uses combine specific information to aid in RTL
7130 3. The routines in this file.
7133 Long term we want to only have one body of simplification code; to
7134 get to that state I recommend the following steps:
7136 1. Pour over fold_rtx & simplify_rtx and move any simplifications
7137 which are not pass dependent state into these routines.
7139 2. As code is moved by #1, change fold_rtx & simplify_rtx to
7140 use this routine whenever possible.
7142 3. Allow for pass dependent state to be provided to these
7143 routines and add simplifications based on the pass dependent
7144 state. Remove code from cse.c & combine.c that becomes
7147 It will take time, but ultimately the compiler will be easier to
7148 maintain and improve. It's totally silly that when we add a
7149 simplification that it needs to be added to 4 places (3 for RTL
7150 simplification and 1 for tree simplification. */
7153 simplify_rtx (const_rtx x
)
7155 const enum rtx_code code
= GET_CODE (x
);
7156 const machine_mode mode
= GET_MODE (x
);
7158 switch (GET_RTX_CLASS (code
))
7161 return simplify_unary_operation (code
, mode
,
7162 XEXP (x
, 0), GET_MODE (XEXP (x
, 0)));
7163 case RTX_COMM_ARITH
:
7164 if (swap_commutative_operands_p (XEXP (x
, 0), XEXP (x
, 1)))
7165 return simplify_gen_binary (code
, mode
, XEXP (x
, 1), XEXP (x
, 0));
7170 return simplify_binary_operation (code
, mode
, XEXP (x
, 0), XEXP (x
, 1));
7173 case RTX_BITFIELD_OPS
:
7174 return simplify_ternary_operation (code
, mode
, GET_MODE (XEXP (x
, 0)),
7175 XEXP (x
, 0), XEXP (x
, 1),
7179 case RTX_COMM_COMPARE
:
7180 return simplify_relational_operation (code
, mode
,
7181 ((GET_MODE (XEXP (x
, 0))
7183 ? GET_MODE (XEXP (x
, 0))
7184 : GET_MODE (XEXP (x
, 1))),
7190 return simplify_subreg (mode
, SUBREG_REG (x
),
7191 GET_MODE (SUBREG_REG (x
)),
7198 /* Convert (lo_sum (high FOO) FOO) to FOO. */
7199 if (GET_CODE (XEXP (x
, 0)) == HIGH
7200 && rtx_equal_p (XEXP (XEXP (x
, 0), 0), XEXP (x
, 1)))
7213 namespace selftest
{
7215 /* Make a unique pseudo REG of mode MODE for use by selftests. */
7218 make_test_reg (machine_mode mode
)
7220 static int test_reg_num
= LAST_VIRTUAL_REGISTER
+ 1;
7222 return gen_rtx_REG (mode
, test_reg_num
++);
7225 /* Test vector simplifications involving VEC_DUPLICATE in which the
7226 operands and result have vector mode MODE. SCALAR_REG is a pseudo
7227 register that holds one element of MODE. */
7230 test_vector_ops_duplicate (machine_mode mode
, rtx scalar_reg
)
7232 scalar_mode inner_mode
= GET_MODE_INNER (mode
);
7233 rtx duplicate
= gen_rtx_VEC_DUPLICATE (mode
, scalar_reg
);
7234 poly_uint64 nunits
= GET_MODE_NUNITS (mode
);
7235 if (GET_MODE_CLASS (mode
) == MODE_VECTOR_INT
)
7237 /* Test some simple unary cases with VEC_DUPLICATE arguments. */
7238 rtx not_scalar_reg
= gen_rtx_NOT (inner_mode
, scalar_reg
);
7239 rtx duplicate_not
= gen_rtx_VEC_DUPLICATE (mode
, not_scalar_reg
);
7240 ASSERT_RTX_EQ (duplicate
,
7241 simplify_unary_operation (NOT
, mode
,
7242 duplicate_not
, mode
));
7244 rtx neg_scalar_reg
= gen_rtx_NEG (inner_mode
, scalar_reg
);
7245 rtx duplicate_neg
= gen_rtx_VEC_DUPLICATE (mode
, neg_scalar_reg
);
7246 ASSERT_RTX_EQ (duplicate
,
7247 simplify_unary_operation (NEG
, mode
,
7248 duplicate_neg
, mode
));
7250 /* Test some simple binary cases with VEC_DUPLICATE arguments. */
7251 ASSERT_RTX_EQ (duplicate
,
7252 simplify_binary_operation (PLUS
, mode
, duplicate
,
7253 CONST0_RTX (mode
)));
7255 ASSERT_RTX_EQ (duplicate
,
7256 simplify_binary_operation (MINUS
, mode
, duplicate
,
7257 CONST0_RTX (mode
)));
7259 ASSERT_RTX_PTR_EQ (CONST0_RTX (mode
),
7260 simplify_binary_operation (MINUS
, mode
, duplicate
,
7264 /* Test a scalar VEC_SELECT of a VEC_DUPLICATE. */
7265 rtx zero_par
= gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (1, const0_rtx
));
7266 ASSERT_RTX_PTR_EQ (scalar_reg
,
7267 simplify_binary_operation (VEC_SELECT
, inner_mode
,
7268 duplicate
, zero_par
));
7270 unsigned HOST_WIDE_INT const_nunits
;
7271 if (nunits
.is_constant (&const_nunits
))
7273 /* And again with the final element. */
7274 rtx last_index
= gen_int_mode (const_nunits
- 1, word_mode
);
7275 rtx last_par
= gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (1, last_index
));
7276 ASSERT_RTX_PTR_EQ (scalar_reg
,
7277 simplify_binary_operation (VEC_SELECT
, inner_mode
,
7278 duplicate
, last_par
));
7280 /* Test a scalar subreg of a VEC_MERGE of a VEC_DUPLICATE. */
7281 rtx vector_reg
= make_test_reg (mode
);
7282 for (unsigned HOST_WIDE_INT i
= 0; i
< const_nunits
; i
++)
7284 if (i
>= HOST_BITS_PER_WIDE_INT
)
7286 rtx mask
= GEN_INT ((HOST_WIDE_INT_1U
<< i
) | (i
+ 1));
7287 rtx vm
= gen_rtx_VEC_MERGE (mode
, duplicate
, vector_reg
, mask
);
7288 poly_uint64 offset
= i
* GET_MODE_SIZE (inner_mode
);
7289 ASSERT_RTX_EQ (scalar_reg
,
7290 simplify_gen_subreg (inner_mode
, vm
,
7295 /* Test a scalar subreg of a VEC_DUPLICATE. */
7296 poly_uint64 offset
= subreg_lowpart_offset (inner_mode
, mode
);
7297 ASSERT_RTX_EQ (scalar_reg
,
7298 simplify_gen_subreg (inner_mode
, duplicate
,
7301 machine_mode narrower_mode
;
7302 if (maybe_ne (nunits
, 2U)
7303 && multiple_p (nunits
, 2)
7304 && mode_for_vector (inner_mode
, 2).exists (&narrower_mode
)
7305 && VECTOR_MODE_P (narrower_mode
))
7307 /* Test VEC_DUPLICATE of a vector. */
7308 rtx_vector_builder
nbuilder (narrower_mode
, 2, 1);
7309 nbuilder
.quick_push (const0_rtx
);
7310 nbuilder
.quick_push (const1_rtx
);
7311 rtx_vector_builder
builder (mode
, 2, 1);
7312 builder
.quick_push (const0_rtx
);
7313 builder
.quick_push (const1_rtx
);
7314 ASSERT_RTX_EQ (builder
.build (),
7315 simplify_unary_operation (VEC_DUPLICATE
, mode
,
7319 /* Test VEC_SELECT of a vector. */
7321 = gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, const1_rtx
, const0_rtx
));
7322 rtx narrower_duplicate
7323 = gen_rtx_VEC_DUPLICATE (narrower_mode
, scalar_reg
);
7324 ASSERT_RTX_EQ (narrower_duplicate
,
7325 simplify_binary_operation (VEC_SELECT
, narrower_mode
,
7326 duplicate
, vec_par
));
7328 /* Test a vector subreg of a VEC_DUPLICATE. */
7329 poly_uint64 offset
= subreg_lowpart_offset (narrower_mode
, mode
);
7330 ASSERT_RTX_EQ (narrower_duplicate
,
7331 simplify_gen_subreg (narrower_mode
, duplicate
,
7336 /* Test vector simplifications involving VEC_SERIES in which the
7337 operands and result have vector mode MODE. SCALAR_REG is a pseudo
7338 register that holds one element of MODE. */
7341 test_vector_ops_series (machine_mode mode
, rtx scalar_reg
)
7343 /* Test unary cases with VEC_SERIES arguments. */
7344 scalar_mode inner_mode
= GET_MODE_INNER (mode
);
7345 rtx duplicate
= gen_rtx_VEC_DUPLICATE (mode
, scalar_reg
);
7346 rtx neg_scalar_reg
= gen_rtx_NEG (inner_mode
, scalar_reg
);
7347 rtx series_0_r
= gen_rtx_VEC_SERIES (mode
, const0_rtx
, scalar_reg
);
7348 rtx series_0_nr
= gen_rtx_VEC_SERIES (mode
, const0_rtx
, neg_scalar_reg
);
7349 rtx series_nr_1
= gen_rtx_VEC_SERIES (mode
, neg_scalar_reg
, const1_rtx
);
7350 rtx series_r_m1
= gen_rtx_VEC_SERIES (mode
, scalar_reg
, constm1_rtx
);
7351 rtx series_r_r
= gen_rtx_VEC_SERIES (mode
, scalar_reg
, scalar_reg
);
7352 rtx series_nr_nr
= gen_rtx_VEC_SERIES (mode
, neg_scalar_reg
,
7354 ASSERT_RTX_EQ (series_0_r
,
7355 simplify_unary_operation (NEG
, mode
, series_0_nr
, mode
));
7356 ASSERT_RTX_EQ (series_r_m1
,
7357 simplify_unary_operation (NEG
, mode
, series_nr_1
, mode
));
7358 ASSERT_RTX_EQ (series_r_r
,
7359 simplify_unary_operation (NEG
, mode
, series_nr_nr
, mode
));
7361 /* Test that a VEC_SERIES with a zero step is simplified away. */
7362 ASSERT_RTX_EQ (duplicate
,
7363 simplify_binary_operation (VEC_SERIES
, mode
,
7364 scalar_reg
, const0_rtx
));
7366 /* Test PLUS and MINUS with VEC_SERIES. */
7367 rtx series_0_1
= gen_const_vec_series (mode
, const0_rtx
, const1_rtx
);
7368 rtx series_0_m1
= gen_const_vec_series (mode
, const0_rtx
, constm1_rtx
);
7369 rtx series_r_1
= gen_rtx_VEC_SERIES (mode
, scalar_reg
, const1_rtx
);
7370 ASSERT_RTX_EQ (series_r_r
,
7371 simplify_binary_operation (PLUS
, mode
, series_0_r
,
7373 ASSERT_RTX_EQ (series_r_1
,
7374 simplify_binary_operation (PLUS
, mode
, duplicate
,
7376 ASSERT_RTX_EQ (series_r_m1
,
7377 simplify_binary_operation (PLUS
, mode
, duplicate
,
7379 ASSERT_RTX_EQ (series_0_r
,
7380 simplify_binary_operation (MINUS
, mode
, series_r_r
,
7382 ASSERT_RTX_EQ (series_r_m1
,
7383 simplify_binary_operation (MINUS
, mode
, duplicate
,
7385 ASSERT_RTX_EQ (series_r_1
,
7386 simplify_binary_operation (MINUS
, mode
, duplicate
,
7388 ASSERT_RTX_EQ (series_0_m1
,
7389 simplify_binary_operation (VEC_SERIES
, mode
, const0_rtx
,
7392 /* Test NEG on constant vector series. */
7393 ASSERT_RTX_EQ (series_0_m1
,
7394 simplify_unary_operation (NEG
, mode
, series_0_1
, mode
));
7395 ASSERT_RTX_EQ (series_0_1
,
7396 simplify_unary_operation (NEG
, mode
, series_0_m1
, mode
));
7398 /* Test PLUS and MINUS on constant vector series. */
7399 rtx scalar2
= gen_int_mode (2, inner_mode
);
7400 rtx scalar3
= gen_int_mode (3, inner_mode
);
7401 rtx series_1_1
= gen_const_vec_series (mode
, const1_rtx
, const1_rtx
);
7402 rtx series_0_2
= gen_const_vec_series (mode
, const0_rtx
, scalar2
);
7403 rtx series_1_3
= gen_const_vec_series (mode
, const1_rtx
, scalar3
);
7404 ASSERT_RTX_EQ (series_1_1
,
7405 simplify_binary_operation (PLUS
, mode
, series_0_1
,
7406 CONST1_RTX (mode
)));
7407 ASSERT_RTX_EQ (series_0_m1
,
7408 simplify_binary_operation (PLUS
, mode
, CONST0_RTX (mode
),
7410 ASSERT_RTX_EQ (series_1_3
,
7411 simplify_binary_operation (PLUS
, mode
, series_1_1
,
7413 ASSERT_RTX_EQ (series_0_1
,
7414 simplify_binary_operation (MINUS
, mode
, series_1_1
,
7415 CONST1_RTX (mode
)));
7416 ASSERT_RTX_EQ (series_1_1
,
7417 simplify_binary_operation (MINUS
, mode
, CONST1_RTX (mode
),
7419 ASSERT_RTX_EQ (series_1_1
,
7420 simplify_binary_operation (MINUS
, mode
, series_1_3
,
7423 /* Test MULT between constant vectors. */
7424 rtx vec2
= gen_const_vec_duplicate (mode
, scalar2
);
7425 rtx vec3
= gen_const_vec_duplicate (mode
, scalar3
);
7426 rtx scalar9
= gen_int_mode (9, inner_mode
);
7427 rtx series_3_9
= gen_const_vec_series (mode
, scalar3
, scalar9
);
7428 ASSERT_RTX_EQ (series_0_2
,
7429 simplify_binary_operation (MULT
, mode
, series_0_1
, vec2
));
7430 ASSERT_RTX_EQ (series_3_9
,
7431 simplify_binary_operation (MULT
, mode
, vec3
, series_1_3
));
7432 if (!GET_MODE_NUNITS (mode
).is_constant ())
7433 ASSERT_FALSE (simplify_binary_operation (MULT
, mode
, series_0_1
,
7436 /* Test ASHIFT between constant vectors. */
7437 ASSERT_RTX_EQ (series_0_2
,
7438 simplify_binary_operation (ASHIFT
, mode
, series_0_1
,
7439 CONST1_RTX (mode
)));
7440 if (!GET_MODE_NUNITS (mode
).is_constant ())
7441 ASSERT_FALSE (simplify_binary_operation (ASHIFT
, mode
, CONST1_RTX (mode
),
7445 /* Verify simplify_merge_mask works correctly. */
7448 test_vec_merge (machine_mode mode
)
7450 rtx op0
= make_test_reg (mode
);
7451 rtx op1
= make_test_reg (mode
);
7452 rtx op2
= make_test_reg (mode
);
7453 rtx op3
= make_test_reg (mode
);
7454 rtx op4
= make_test_reg (mode
);
7455 rtx op5
= make_test_reg (mode
);
7456 rtx mask1
= make_test_reg (SImode
);
7457 rtx mask2
= make_test_reg (SImode
);
7458 rtx vm1
= gen_rtx_VEC_MERGE (mode
, op0
, op1
, mask1
);
7459 rtx vm2
= gen_rtx_VEC_MERGE (mode
, op2
, op3
, mask1
);
7460 rtx vm3
= gen_rtx_VEC_MERGE (mode
, op4
, op5
, mask1
);
7462 /* Simple vec_merge. */
7463 ASSERT_EQ (op0
, simplify_merge_mask (vm1
, mask1
, 0));
7464 ASSERT_EQ (op1
, simplify_merge_mask (vm1
, mask1
, 1));
7465 ASSERT_EQ (NULL_RTX
, simplify_merge_mask (vm1
, mask2
, 0));
7466 ASSERT_EQ (NULL_RTX
, simplify_merge_mask (vm1
, mask2
, 1));
7468 /* Nested vec_merge.
7469 It's tempting to make this simplify right down to opN, but we don't
7470 because all the simplify_* functions assume that the operands have
7471 already been simplified. */
7472 rtx nvm
= gen_rtx_VEC_MERGE (mode
, vm1
, vm2
, mask1
);
7473 ASSERT_EQ (vm1
, simplify_merge_mask (nvm
, mask1
, 0));
7474 ASSERT_EQ (vm2
, simplify_merge_mask (nvm
, mask1
, 1));
7476 /* Intermediate unary op. */
7477 rtx unop
= gen_rtx_NOT (mode
, vm1
);
7478 ASSERT_RTX_EQ (gen_rtx_NOT (mode
, op0
),
7479 simplify_merge_mask (unop
, mask1
, 0));
7480 ASSERT_RTX_EQ (gen_rtx_NOT (mode
, op1
),
7481 simplify_merge_mask (unop
, mask1
, 1));
7483 /* Intermediate binary op. */
7484 rtx binop
= gen_rtx_PLUS (mode
, vm1
, vm2
);
7485 ASSERT_RTX_EQ (gen_rtx_PLUS (mode
, op0
, op2
),
7486 simplify_merge_mask (binop
, mask1
, 0));
7487 ASSERT_RTX_EQ (gen_rtx_PLUS (mode
, op1
, op3
),
7488 simplify_merge_mask (binop
, mask1
, 1));
7490 /* Intermediate ternary op. */
7491 rtx tenop
= gen_rtx_FMA (mode
, vm1
, vm2
, vm3
);
7492 ASSERT_RTX_EQ (gen_rtx_FMA (mode
, op0
, op2
, op4
),
7493 simplify_merge_mask (tenop
, mask1
, 0));
7494 ASSERT_RTX_EQ (gen_rtx_FMA (mode
, op1
, op3
, op5
),
7495 simplify_merge_mask (tenop
, mask1
, 1));
7498 rtx badop0
= gen_rtx_PRE_INC (mode
, op0
);
7499 rtx badvm
= gen_rtx_VEC_MERGE (mode
, badop0
, op1
, mask1
);
7500 ASSERT_EQ (badop0
, simplify_merge_mask (badvm
, mask1
, 0));
7501 ASSERT_EQ (NULL_RTX
, simplify_merge_mask (badvm
, mask1
, 1));
7503 /* Called indirectly. */
7504 ASSERT_RTX_EQ (gen_rtx_VEC_MERGE (mode
, op0
, op3
, mask1
),
7505 simplify_rtx (nvm
));
7508 /* Test subregs of integer vector constant X, trying elements in
7509 the range [ELT_BIAS, ELT_BIAS + constant_lower_bound (NELTS)),
7510 where NELTS is the number of elements in X. Subregs involving
7511 elements [ELT_BIAS, ELT_BIAS + FIRST_VALID) are expected to fail. */
7514 test_vector_subregs_modes (rtx x
, poly_uint64 elt_bias
= 0,
7515 unsigned int first_valid
= 0)
7517 machine_mode inner_mode
= GET_MODE (x
);
7518 scalar_mode int_mode
= GET_MODE_INNER (inner_mode
);
7520 for (unsigned int modei
= 0; modei
< NUM_MACHINE_MODES
; ++modei
)
7522 machine_mode outer_mode
= (machine_mode
) modei
;
7523 if (!VECTOR_MODE_P (outer_mode
))
7526 unsigned int outer_nunits
;
7527 if (GET_MODE_INNER (outer_mode
) == int_mode
7528 && GET_MODE_NUNITS (outer_mode
).is_constant (&outer_nunits
)
7529 && multiple_p (GET_MODE_NUNITS (inner_mode
), outer_nunits
))
7531 /* Test subregs in which the outer mode is a smaller,
7532 constant-sized vector of the same element type. */
7534 = constant_lower_bound (GET_MODE_NUNITS (inner_mode
));
7535 for (unsigned int elt
= 0; elt
< limit
; elt
+= outer_nunits
)
7537 rtx expected
= NULL_RTX
;
7538 if (elt
>= first_valid
)
7540 rtx_vector_builder
builder (outer_mode
, outer_nunits
, 1);
7541 for (unsigned int i
= 0; i
< outer_nunits
; ++i
)
7542 builder
.quick_push (CONST_VECTOR_ELT (x
, elt
+ i
));
7543 expected
= builder
.build ();
7545 poly_uint64 byte
= (elt_bias
+ elt
) * GET_MODE_SIZE (int_mode
);
7546 ASSERT_RTX_EQ (expected
,
7547 simplify_subreg (outer_mode
, x
,
7551 else if (known_eq (GET_MODE_SIZE (outer_mode
),
7552 GET_MODE_SIZE (inner_mode
))
7553 && known_eq (elt_bias
, 0U)
7554 && (GET_MODE_CLASS (outer_mode
) != MODE_VECTOR_BOOL
7555 || known_eq (GET_MODE_BITSIZE (outer_mode
),
7556 GET_MODE_NUNITS (outer_mode
)))
7557 && (!FLOAT_MODE_P (outer_mode
)
7558 || (FLOAT_MODE_FORMAT (outer_mode
)->ieee_bits
7559 == GET_MODE_UNIT_PRECISION (outer_mode
)))
7560 && (GET_MODE_SIZE (inner_mode
).is_constant ()
7561 || !CONST_VECTOR_STEPPED_P (x
)))
7563 /* Try converting to OUTER_MODE and back. */
7564 rtx outer_x
= simplify_subreg (outer_mode
, x
, inner_mode
, 0);
7565 ASSERT_TRUE (outer_x
!= NULL_RTX
);
7566 ASSERT_RTX_EQ (x
, simplify_subreg (inner_mode
, outer_x
,
7571 if (BYTES_BIG_ENDIAN
== WORDS_BIG_ENDIAN
)
7573 /* Test each byte in the element range. */
7575 = constant_lower_bound (GET_MODE_SIZE (inner_mode
));
7576 for (unsigned int i
= 0; i
< limit
; ++i
)
7578 unsigned int elt
= i
/ GET_MODE_SIZE (int_mode
);
7579 rtx expected
= NULL_RTX
;
7580 if (elt
>= first_valid
)
7582 unsigned int byte_shift
= i
% GET_MODE_SIZE (int_mode
);
7583 if (BYTES_BIG_ENDIAN
)
7584 byte_shift
= GET_MODE_SIZE (int_mode
) - byte_shift
- 1;
7585 rtx_mode_t
vec_elt (CONST_VECTOR_ELT (x
, elt
), int_mode
);
7586 wide_int shifted_elt
7587 = wi::lrshift (vec_elt
, byte_shift
* BITS_PER_UNIT
);
7588 expected
= immed_wide_int_const (shifted_elt
, QImode
);
7590 poly_uint64 byte
= elt_bias
* GET_MODE_SIZE (int_mode
) + i
;
7591 ASSERT_RTX_EQ (expected
,
7592 simplify_subreg (QImode
, x
, inner_mode
, byte
));
7597 /* Test constant subregs of integer vector mode INNER_MODE, using 1
7598 element per pattern. */
7601 test_vector_subregs_repeating (machine_mode inner_mode
)
7603 poly_uint64 nunits
= GET_MODE_NUNITS (inner_mode
);
7604 unsigned int min_nunits
= constant_lower_bound (nunits
);
7605 scalar_mode int_mode
= GET_MODE_INNER (inner_mode
);
7606 unsigned int count
= gcd (min_nunits
, 8);
7608 rtx_vector_builder
builder (inner_mode
, count
, 1);
7609 for (unsigned int i
= 0; i
< count
; ++i
)
7610 builder
.quick_push (gen_int_mode (8 - i
, int_mode
));
7611 rtx x
= builder
.build ();
7613 test_vector_subregs_modes (x
);
7614 if (!nunits
.is_constant ())
7615 test_vector_subregs_modes (x
, nunits
- min_nunits
);
7618 /* Test constant subregs of integer vector mode INNER_MODE, using 2
7619 elements per pattern. */
7622 test_vector_subregs_fore_back (machine_mode inner_mode
)
7624 poly_uint64 nunits
= GET_MODE_NUNITS (inner_mode
);
7625 unsigned int min_nunits
= constant_lower_bound (nunits
);
7626 scalar_mode int_mode
= GET_MODE_INNER (inner_mode
);
7627 unsigned int count
= gcd (min_nunits
, 4);
7629 rtx_vector_builder
builder (inner_mode
, count
, 2);
7630 for (unsigned int i
= 0; i
< count
; ++i
)
7631 builder
.quick_push (gen_int_mode (i
, int_mode
));
7632 for (unsigned int i
= 0; i
< count
; ++i
)
7633 builder
.quick_push (gen_int_mode (-(int) i
, int_mode
));
7634 rtx x
= builder
.build ();
7636 test_vector_subregs_modes (x
);
7637 if (!nunits
.is_constant ())
7638 test_vector_subregs_modes (x
, nunits
- min_nunits
, count
);
7641 /* Test constant subregs of integer vector mode INNER_MODE, using 3
7642 elements per pattern. */
7645 test_vector_subregs_stepped (machine_mode inner_mode
)
7647 /* Build { 0, 1, 2, 3, ... }. */
7648 scalar_mode int_mode
= GET_MODE_INNER (inner_mode
);
7649 rtx_vector_builder
builder (inner_mode
, 1, 3);
7650 for (unsigned int i
= 0; i
< 3; ++i
)
7651 builder
.quick_push (gen_int_mode (i
, int_mode
));
7652 rtx x
= builder
.build ();
7654 test_vector_subregs_modes (x
);
7657 /* Test constant subregs of integer vector mode INNER_MODE. */
7660 test_vector_subregs (machine_mode inner_mode
)
7662 test_vector_subregs_repeating (inner_mode
);
7663 test_vector_subregs_fore_back (inner_mode
);
7664 test_vector_subregs_stepped (inner_mode
);
7667 /* Verify some simplifications involving vectors. */
7672 for (unsigned int i
= 0; i
< NUM_MACHINE_MODES
; ++i
)
7674 machine_mode mode
= (machine_mode
) i
;
7675 if (VECTOR_MODE_P (mode
))
7677 rtx scalar_reg
= make_test_reg (GET_MODE_INNER (mode
));
7678 test_vector_ops_duplicate (mode
, scalar_reg
);
7679 if (GET_MODE_CLASS (mode
) == MODE_VECTOR_INT
7680 && maybe_gt (GET_MODE_NUNITS (mode
), 2))
7682 test_vector_ops_series (mode
, scalar_reg
);
7683 test_vector_subregs (mode
);
7685 test_vec_merge (mode
);
7690 template<unsigned int N
>
7691 struct simplify_const_poly_int_tests
7697 struct simplify_const_poly_int_tests
<1>
7699 static void run () {}
7702 /* Test various CONST_POLY_INT properties. */
7704 template<unsigned int N
>
7706 simplify_const_poly_int_tests
<N
>::run ()
7708 rtx x1
= gen_int_mode (poly_int64 (1, 1), QImode
);
7709 rtx x2
= gen_int_mode (poly_int64 (-80, 127), QImode
);
7710 rtx x3
= gen_int_mode (poly_int64 (-79, -128), QImode
);
7711 rtx x4
= gen_int_mode (poly_int64 (5, 4), QImode
);
7712 rtx x5
= gen_int_mode (poly_int64 (30, 24), QImode
);
7713 rtx x6
= gen_int_mode (poly_int64 (20, 16), QImode
);
7714 rtx x7
= gen_int_mode (poly_int64 (7, 4), QImode
);
7715 rtx x8
= gen_int_mode (poly_int64 (30, 24), HImode
);
7716 rtx x9
= gen_int_mode (poly_int64 (-30, -24), HImode
);
7717 rtx x10
= gen_int_mode (poly_int64 (-31, -24), HImode
);
7718 rtx two
= GEN_INT (2);
7719 rtx six
= GEN_INT (6);
7720 poly_uint64 offset
= subreg_lowpart_offset (QImode
, HImode
);
7722 /* These tests only try limited operation combinations. Fuller arithmetic
7723 testing is done directly on poly_ints. */
7724 ASSERT_EQ (simplify_unary_operation (NEG
, HImode
, x8
, HImode
), x9
);
7725 ASSERT_EQ (simplify_unary_operation (NOT
, HImode
, x8
, HImode
), x10
);
7726 ASSERT_EQ (simplify_unary_operation (TRUNCATE
, QImode
, x8
, HImode
), x5
);
7727 ASSERT_EQ (simplify_binary_operation (PLUS
, QImode
, x1
, x2
), x3
);
7728 ASSERT_EQ (simplify_binary_operation (MINUS
, QImode
, x3
, x1
), x2
);
7729 ASSERT_EQ (simplify_binary_operation (MULT
, QImode
, x4
, six
), x5
);
7730 ASSERT_EQ (simplify_binary_operation (MULT
, QImode
, six
, x4
), x5
);
7731 ASSERT_EQ (simplify_binary_operation (ASHIFT
, QImode
, x4
, two
), x6
);
7732 ASSERT_EQ (simplify_binary_operation (IOR
, QImode
, x4
, two
), x7
);
7733 ASSERT_EQ (simplify_subreg (HImode
, x5
, QImode
, 0), x8
);
7734 ASSERT_EQ (simplify_subreg (QImode
, x8
, HImode
, offset
), x5
);
7737 /* Run all of the selftests within this file. */
7740 simplify_rtx_c_tests ()
7743 simplify_const_poly_int_tests
<NUM_POLY_INT_COEFFS
>::run ();
7746 } // namespace selftest
7748 #endif /* CHECKING_P */