1 /* RTL simplification functions for GNU compiler.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 2, or (at your option) any later
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING. If not, write to the Free
20 Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
26 #include "coretypes.h"
32 #include "hard-reg-set.h"
35 #include "insn-config.h"
44 /* Simplification and canonicalization of RTL. */
46 /* Much code operates on (low, high) pairs; the low value is an
47 unsigned wide int, the high value a signed wide int. We
48 occasionally need to sign extend from low to high as if low were a
50 #define HWI_SIGN_EXTEND(low) \
51 ((((HOST_WIDE_INT) low) < 0) ? ((HOST_WIDE_INT) -1) : ((HOST_WIDE_INT) 0))
53 static rtx
neg_const_int (enum machine_mode
, rtx
);
54 static bool plus_minus_operand_p (rtx
);
55 static int simplify_plus_minus_op_data_cmp (const void *, const void *);
56 static rtx
simplify_plus_minus (enum rtx_code
, enum machine_mode
, rtx
, rtx
);
57 static rtx
simplify_immed_subreg (enum machine_mode
, rtx
, enum machine_mode
,
59 static rtx
simplify_associative_operation (enum rtx_code
, enum machine_mode
,
61 static rtx
simplify_relational_operation_1 (enum rtx_code
, enum machine_mode
,
62 enum machine_mode
, rtx
, rtx
);
63 static rtx
simplify_unary_operation_1 (enum rtx_code
, enum machine_mode
, rtx
);
64 static rtx
simplify_binary_operation_1 (enum rtx_code
, enum machine_mode
,
67 /* Negate a CONST_INT rtx, truncating (because a conversion from a
68 maximally negative number can overflow). */
70 neg_const_int (enum machine_mode mode
, rtx i
)
72 return gen_int_mode (- INTVAL (i
), mode
);
75 /* Test whether expression, X, is an immediate constant that represents
76 the most significant bit of machine mode MODE. */
79 mode_signbit_p (enum machine_mode mode
, rtx x
)
81 unsigned HOST_WIDE_INT val
;
84 if (GET_MODE_CLASS (mode
) != MODE_INT
)
87 width
= GET_MODE_BITSIZE (mode
);
91 if (width
<= HOST_BITS_PER_WIDE_INT
92 && GET_CODE (x
) == CONST_INT
)
94 else if (width
<= 2 * HOST_BITS_PER_WIDE_INT
95 && GET_CODE (x
) == CONST_DOUBLE
96 && CONST_DOUBLE_LOW (x
) == 0)
98 val
= CONST_DOUBLE_HIGH (x
);
99 width
-= HOST_BITS_PER_WIDE_INT
;
104 if (width
< HOST_BITS_PER_WIDE_INT
)
105 val
&= ((unsigned HOST_WIDE_INT
) 1 << width
) - 1;
106 return val
== ((unsigned HOST_WIDE_INT
) 1 << (width
- 1));
109 /* Make a binary operation by properly ordering the operands and
110 seeing if the expression folds. */
113 simplify_gen_binary (enum rtx_code code
, enum machine_mode mode
, rtx op0
,
118 /* If this simplifies, do it. */
119 tem
= simplify_binary_operation (code
, mode
, op0
, op1
);
123 /* Put complex operands first and constants second if commutative. */
124 if (GET_RTX_CLASS (code
) == RTX_COMM_ARITH
125 && swap_commutative_operands_p (op0
, op1
))
126 tem
= op0
, op0
= op1
, op1
= tem
;
128 return gen_rtx_fmt_ee (code
, mode
, op0
, op1
);
131 /* If X is a MEM referencing the constant pool, return the real value.
132 Otherwise return X. */
134 avoid_constant_pool_reference (rtx x
)
137 enum machine_mode cmode
;
138 HOST_WIDE_INT offset
= 0;
140 switch (GET_CODE (x
))
146 /* Handle float extensions of constant pool references. */
148 c
= avoid_constant_pool_reference (tmp
);
149 if (c
!= tmp
&& GET_CODE (c
) == CONST_DOUBLE
)
153 REAL_VALUE_FROM_CONST_DOUBLE (d
, c
);
154 return CONST_DOUBLE_FROM_REAL_VALUE (d
, GET_MODE (x
));
162 if (GET_MODE (x
) == BLKmode
)
167 /* Call target hook to avoid the effects of -fpic etc.... */
168 addr
= targetm
.delegitimize_address (addr
);
170 /* Split the address into a base and integer offset. */
171 if (GET_CODE (addr
) == CONST
172 && GET_CODE (XEXP (addr
, 0)) == PLUS
173 && GET_CODE (XEXP (XEXP (addr
, 0), 1)) == CONST_INT
)
175 offset
= INTVAL (XEXP (XEXP (addr
, 0), 1));
176 addr
= XEXP (XEXP (addr
, 0), 0);
179 if (GET_CODE (addr
) == LO_SUM
)
180 addr
= XEXP (addr
, 1);
182 /* If this is a constant pool reference, we can turn it into its
183 constant and hope that simplifications happen. */
184 if (GET_CODE (addr
) == SYMBOL_REF
185 && CONSTANT_POOL_ADDRESS_P (addr
))
187 c
= get_pool_constant (addr
);
188 cmode
= get_pool_mode (addr
);
190 /* If we're accessing the constant in a different mode than it was
191 originally stored, attempt to fix that up via subreg simplifications.
192 If that fails we have no choice but to return the original memory. */
193 if (offset
!= 0 || cmode
!= GET_MODE (x
))
195 rtx tem
= simplify_subreg (GET_MODE (x
), c
, cmode
, offset
);
196 if (tem
&& CONSTANT_P (tem
))
206 /* Make a unary operation by first seeing if it folds and otherwise making
207 the specified operation. */
210 simplify_gen_unary (enum rtx_code code
, enum machine_mode mode
, rtx op
,
211 enum machine_mode op_mode
)
215 /* If this simplifies, use it. */
216 if ((tem
= simplify_unary_operation (code
, mode
, op
, op_mode
)) != 0)
219 return gen_rtx_fmt_e (code
, mode
, op
);
222 /* Likewise for ternary operations. */
225 simplify_gen_ternary (enum rtx_code code
, enum machine_mode mode
,
226 enum machine_mode op0_mode
, rtx op0
, rtx op1
, rtx op2
)
230 /* If this simplifies, use it. */
231 if (0 != (tem
= simplify_ternary_operation (code
, mode
, op0_mode
,
235 return gen_rtx_fmt_eee (code
, mode
, op0
, op1
, op2
);
238 /* Likewise, for relational operations.
239 CMP_MODE specifies mode comparison is done in. */
242 simplify_gen_relational (enum rtx_code code
, enum machine_mode mode
,
243 enum machine_mode cmp_mode
, rtx op0
, rtx op1
)
247 if (0 != (tem
= simplify_relational_operation (code
, mode
, cmp_mode
,
251 return gen_rtx_fmt_ee (code
, mode
, op0
, op1
);
254 /* Replace all occurrences of OLD_RTX in X with NEW_RTX and try to simplify the
255 resulting RTX. Return a new RTX which is as simplified as possible. */
258 simplify_replace_rtx (rtx x
, rtx old_rtx
, rtx new_rtx
)
260 enum rtx_code code
= GET_CODE (x
);
261 enum machine_mode mode
= GET_MODE (x
);
262 enum machine_mode op_mode
;
265 /* If X is OLD_RTX, return NEW_RTX. Otherwise, if this is an expression, try
266 to build a new expression substituting recursively. If we can't do
267 anything, return our input. */
272 switch (GET_RTX_CLASS (code
))
276 op_mode
= GET_MODE (op0
);
277 op0
= simplify_replace_rtx (op0
, old_rtx
, new_rtx
);
278 if (op0
== XEXP (x
, 0))
280 return simplify_gen_unary (code
, mode
, op0
, op_mode
);
284 op0
= simplify_replace_rtx (XEXP (x
, 0), old_rtx
, new_rtx
);
285 op1
= simplify_replace_rtx (XEXP (x
, 1), old_rtx
, new_rtx
);
286 if (op0
== XEXP (x
, 0) && op1
== XEXP (x
, 1))
288 return simplify_gen_binary (code
, mode
, op0
, op1
);
291 case RTX_COMM_COMPARE
:
294 op_mode
= GET_MODE (op0
) != VOIDmode
? GET_MODE (op0
) : GET_MODE (op1
);
295 op0
= simplify_replace_rtx (op0
, old_rtx
, new_rtx
);
296 op1
= simplify_replace_rtx (op1
, old_rtx
, new_rtx
);
297 if (op0
== XEXP (x
, 0) && op1
== XEXP (x
, 1))
299 return simplify_gen_relational (code
, mode
, op_mode
, op0
, op1
);
302 case RTX_BITFIELD_OPS
:
304 op_mode
= GET_MODE (op0
);
305 op0
= simplify_replace_rtx (op0
, old_rtx
, new_rtx
);
306 op1
= simplify_replace_rtx (XEXP (x
, 1), old_rtx
, new_rtx
);
307 op2
= simplify_replace_rtx (XEXP (x
, 2), old_rtx
, new_rtx
);
308 if (op0
== XEXP (x
, 0) && op1
== XEXP (x
, 1) && op2
== XEXP (x
, 2))
310 if (op_mode
== VOIDmode
)
311 op_mode
= GET_MODE (op0
);
312 return simplify_gen_ternary (code
, mode
, op_mode
, op0
, op1
, op2
);
315 /* The only case we try to handle is a SUBREG. */
318 op0
= simplify_replace_rtx (SUBREG_REG (x
), old_rtx
, new_rtx
);
319 if (op0
== SUBREG_REG (x
))
321 op0
= simplify_gen_subreg (GET_MODE (x
), op0
,
322 GET_MODE (SUBREG_REG (x
)),
324 return op0
? op0
: x
;
331 op0
= simplify_replace_rtx (XEXP (x
, 0), old_rtx
, new_rtx
);
332 if (op0
== XEXP (x
, 0))
334 return replace_equiv_address_nv (x
, op0
);
336 else if (code
== LO_SUM
)
338 op0
= simplify_replace_rtx (XEXP (x
, 0), old_rtx
, new_rtx
);
339 op1
= simplify_replace_rtx (XEXP (x
, 1), old_rtx
, new_rtx
);
341 /* (lo_sum (high x) x) -> x */
342 if (GET_CODE (op0
) == HIGH
&& rtx_equal_p (XEXP (op0
, 0), op1
))
345 if (op0
== XEXP (x
, 0) && op1
== XEXP (x
, 1))
347 return gen_rtx_LO_SUM (mode
, op0
, op1
);
349 else if (code
== REG
)
351 if (rtx_equal_p (x
, old_rtx
))
362 /* Try to simplify a unary operation CODE whose output mode is to be
363 MODE with input operand OP whose mode was originally OP_MODE.
364 Return zero if no simplification can be made. */
366 simplify_unary_operation (enum rtx_code code
, enum machine_mode mode
,
367 rtx op
, enum machine_mode op_mode
)
371 if (GET_CODE (op
) == CONST
)
374 trueop
= avoid_constant_pool_reference (op
);
376 tem
= simplify_const_unary_operation (code
, mode
, trueop
, op_mode
);
380 return simplify_unary_operation_1 (code
, mode
, op
);
383 /* Perform some simplifications we can do even if the operands
386 simplify_unary_operation_1 (enum rtx_code code
, enum machine_mode mode
, rtx op
)
388 enum rtx_code reversed
;
394 /* (not (not X)) == X. */
395 if (GET_CODE (op
) == NOT
)
398 /* (not (eq X Y)) == (ne X Y), etc. if BImode or the result of the
399 comparison is all ones. */
400 if (COMPARISON_P (op
)
401 && (mode
== BImode
|| STORE_FLAG_VALUE
== -1)
402 && ((reversed
= reversed_comparison_code (op
, NULL_RTX
)) != UNKNOWN
))
403 return simplify_gen_relational (reversed
, mode
, VOIDmode
,
404 XEXP (op
, 0), XEXP (op
, 1));
406 /* (not (plus X -1)) can become (neg X). */
407 if (GET_CODE (op
) == PLUS
408 && XEXP (op
, 1) == constm1_rtx
)
409 return simplify_gen_unary (NEG
, mode
, XEXP (op
, 0), mode
);
411 /* Similarly, (not (neg X)) is (plus X -1). */
412 if (GET_CODE (op
) == NEG
)
413 return plus_constant (XEXP (op
, 0), -1);
415 /* (not (xor X C)) for C constant is (xor X D) with D = ~C. */
416 if (GET_CODE (op
) == XOR
417 && GET_CODE (XEXP (op
, 1)) == CONST_INT
418 && (temp
= simplify_unary_operation (NOT
, mode
,
419 XEXP (op
, 1), mode
)) != 0)
420 return simplify_gen_binary (XOR
, mode
, XEXP (op
, 0), temp
);
422 /* (not (plus X C)) for signbit C is (xor X D) with D = ~C. */
423 if (GET_CODE (op
) == PLUS
424 && GET_CODE (XEXP (op
, 1)) == CONST_INT
425 && mode_signbit_p (mode
, XEXP (op
, 1))
426 && (temp
= simplify_unary_operation (NOT
, mode
,
427 XEXP (op
, 1), mode
)) != 0)
428 return simplify_gen_binary (XOR
, mode
, XEXP (op
, 0), temp
);
431 /* (not (ashift 1 X)) is (rotate ~1 X). We used to do this for
432 operands other than 1, but that is not valid. We could do a
433 similar simplification for (not (lshiftrt C X)) where C is
434 just the sign bit, but this doesn't seem common enough to
436 if (GET_CODE (op
) == ASHIFT
437 && XEXP (op
, 0) == const1_rtx
)
439 temp
= simplify_gen_unary (NOT
, mode
, const1_rtx
, mode
);
440 return simplify_gen_binary (ROTATE
, mode
, temp
, XEXP (op
, 1));
443 /* (not (ashiftrt foo C)) where C is the number of bits in FOO
444 minus 1 is (ge foo (const_int 0)) if STORE_FLAG_VALUE is -1,
445 so we can perform the above simplification. */
447 if (STORE_FLAG_VALUE
== -1
448 && GET_CODE (op
) == ASHIFTRT
449 && GET_CODE (XEXP (op
, 1)) == CONST_INT
450 && INTVAL (XEXP (op
, 1)) == GET_MODE_BITSIZE (mode
) - 1)
451 return simplify_gen_relational (GE
, mode
, VOIDmode
,
452 XEXP (op
, 0), const0_rtx
);
455 if (GET_CODE (op
) == SUBREG
456 && subreg_lowpart_p (op
)
457 && (GET_MODE_SIZE (GET_MODE (op
))
458 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (op
))))
459 && GET_CODE (SUBREG_REG (op
)) == ASHIFT
460 && XEXP (SUBREG_REG (op
), 0) == const1_rtx
)
462 enum machine_mode inner_mode
= GET_MODE (SUBREG_REG (op
));
465 x
= gen_rtx_ROTATE (inner_mode
,
466 simplify_gen_unary (NOT
, inner_mode
, const1_rtx
,
468 XEXP (SUBREG_REG (op
), 1));
469 return rtl_hooks
.gen_lowpart_no_emit (mode
, x
);
472 /* Apply De Morgan's laws to reduce number of patterns for machines
473 with negating logical insns (and-not, nand, etc.). If result has
474 only one NOT, put it first, since that is how the patterns are
477 if (GET_CODE (op
) == IOR
|| GET_CODE (op
) == AND
)
479 rtx in1
= XEXP (op
, 0), in2
= XEXP (op
, 1);
480 enum machine_mode op_mode
;
482 op_mode
= GET_MODE (in1
);
483 in1
= simplify_gen_unary (NOT
, op_mode
, in1
, op_mode
);
485 op_mode
= GET_MODE (in2
);
486 if (op_mode
== VOIDmode
)
488 in2
= simplify_gen_unary (NOT
, op_mode
, in2
, op_mode
);
490 if (GET_CODE (in2
) == NOT
&& GET_CODE (in1
) != NOT
)
493 in2
= in1
; in1
= tem
;
496 return gen_rtx_fmt_ee (GET_CODE (op
) == IOR
? AND
: IOR
,
502 /* (neg (neg X)) == X. */
503 if (GET_CODE (op
) == NEG
)
506 /* (neg (plus X 1)) can become (not X). */
507 if (GET_CODE (op
) == PLUS
508 && XEXP (op
, 1) == const1_rtx
)
509 return simplify_gen_unary (NOT
, mode
, XEXP (op
, 0), mode
);
511 /* Similarly, (neg (not X)) is (plus X 1). */
512 if (GET_CODE (op
) == NOT
)
513 return plus_constant (XEXP (op
, 0), 1);
515 /* (neg (minus X Y)) can become (minus Y X). This transformation
516 isn't safe for modes with signed zeros, since if X and Y are
517 both +0, (minus Y X) is the same as (minus X Y). If the
518 rounding mode is towards +infinity (or -infinity) then the two
519 expressions will be rounded differently. */
520 if (GET_CODE (op
) == MINUS
521 && !HONOR_SIGNED_ZEROS (mode
)
522 && !HONOR_SIGN_DEPENDENT_ROUNDING (mode
))
523 return simplify_gen_binary (MINUS
, mode
, XEXP (op
, 1), XEXP (op
, 0));
525 if (GET_CODE (op
) == PLUS
526 && !HONOR_SIGNED_ZEROS (mode
)
527 && !HONOR_SIGN_DEPENDENT_ROUNDING (mode
))
529 /* (neg (plus A C)) is simplified to (minus -C A). */
530 if (GET_CODE (XEXP (op
, 1)) == CONST_INT
531 || GET_CODE (XEXP (op
, 1)) == CONST_DOUBLE
)
533 temp
= simplify_unary_operation (NEG
, mode
, XEXP (op
, 1), mode
);
535 return simplify_gen_binary (MINUS
, mode
, temp
, XEXP (op
, 0));
538 /* (neg (plus A B)) is canonicalized to (minus (neg A) B). */
539 temp
= simplify_gen_unary (NEG
, mode
, XEXP (op
, 0), mode
);
540 return simplify_gen_binary (MINUS
, mode
, temp
, XEXP (op
, 1));
543 /* (neg (mult A B)) becomes (mult (neg A) B).
544 This works even for floating-point values. */
545 if (GET_CODE (op
) == MULT
546 && !HONOR_SIGN_DEPENDENT_ROUNDING (mode
))
548 temp
= simplify_gen_unary (NEG
, mode
, XEXP (op
, 0), mode
);
549 return simplify_gen_binary (MULT
, mode
, temp
, XEXP (op
, 1));
552 /* NEG commutes with ASHIFT since it is multiplication. Only do
553 this if we can then eliminate the NEG (e.g., if the operand
555 if (GET_CODE (op
) == ASHIFT
)
557 temp
= simplify_unary_operation (NEG
, mode
, XEXP (op
, 0), mode
);
559 return simplify_gen_binary (ASHIFT
, mode
, temp
, XEXP (op
, 1));
562 /* (neg (ashiftrt X C)) can be replaced by (lshiftrt X C) when
563 C is equal to the width of MODE minus 1. */
564 if (GET_CODE (op
) == ASHIFTRT
565 && GET_CODE (XEXP (op
, 1)) == CONST_INT
566 && INTVAL (XEXP (op
, 1)) == GET_MODE_BITSIZE (mode
) - 1)
567 return simplify_gen_binary (LSHIFTRT
, mode
,
568 XEXP (op
, 0), XEXP (op
, 1));
570 /* (neg (lshiftrt X C)) can be replaced by (ashiftrt X C) when
571 C is equal to the width of MODE minus 1. */
572 if (GET_CODE (op
) == LSHIFTRT
573 && GET_CODE (XEXP (op
, 1)) == CONST_INT
574 && INTVAL (XEXP (op
, 1)) == GET_MODE_BITSIZE (mode
) - 1)
575 return simplify_gen_binary (ASHIFTRT
, mode
,
576 XEXP (op
, 0), XEXP (op
, 1));
578 /* (neg (xor A 1)) is (plus A -1) if A is known to be either 0 or 1. */
579 if (GET_CODE (op
) == XOR
580 && XEXP (op
, 1) == const1_rtx
581 && nonzero_bits (XEXP (op
, 0), mode
) == 1)
582 return plus_constant (XEXP (op
, 0), -1);
584 /* (neg (lt x 0)) is (ashiftrt X C) if STORE_FLAG_VALUE is 1. */
585 /* (neg (lt x 0)) is (lshiftrt X C) if STORE_FLAG_VALUE is -1. */
586 if (GET_CODE (op
) == LT
587 && XEXP (op
, 1) == const0_rtx
)
589 enum machine_mode inner
= GET_MODE (XEXP (op
, 0));
590 int isize
= GET_MODE_BITSIZE (inner
);
591 if (STORE_FLAG_VALUE
== 1)
593 temp
= simplify_gen_binary (ASHIFTRT
, inner
, XEXP (op
, 0),
594 GEN_INT (isize
- 1));
597 if (GET_MODE_BITSIZE (mode
) > isize
)
598 return simplify_gen_unary (SIGN_EXTEND
, mode
, temp
, inner
);
599 return simplify_gen_unary (TRUNCATE
, mode
, temp
, inner
);
601 else if (STORE_FLAG_VALUE
== -1)
603 temp
= simplify_gen_binary (LSHIFTRT
, inner
, XEXP (op
, 0),
604 GEN_INT (isize
- 1));
607 if (GET_MODE_BITSIZE (mode
) > isize
)
608 return simplify_gen_unary (ZERO_EXTEND
, mode
, temp
, inner
);
609 return simplify_gen_unary (TRUNCATE
, mode
, temp
, inner
);
615 /* We can't handle truncation to a partial integer mode here
616 because we don't know the real bitsize of the partial
618 if (GET_MODE_CLASS (mode
) == MODE_PARTIAL_INT
)
621 /* (truncate:SI ({sign,zero}_extend:DI foo:SI)) == foo:SI. */
622 if ((GET_CODE (op
) == SIGN_EXTEND
623 || GET_CODE (op
) == ZERO_EXTEND
)
624 && GET_MODE (XEXP (op
, 0)) == mode
)
627 /* (truncate:SI (OP:DI ({sign,zero}_extend:DI foo:SI))) is
628 (OP:SI foo:SI) if OP is NEG or ABS. */
629 if ((GET_CODE (op
) == ABS
630 || GET_CODE (op
) == NEG
)
631 && (GET_CODE (XEXP (op
, 0)) == SIGN_EXTEND
632 || GET_CODE (XEXP (op
, 0)) == ZERO_EXTEND
)
633 && GET_MODE (XEXP (XEXP (op
, 0), 0)) == mode
)
634 return simplify_gen_unary (GET_CODE (op
), mode
,
635 XEXP (XEXP (op
, 0), 0), mode
);
637 /* (truncate:A (subreg:B (truncate:C X) 0)) is
639 if (GET_CODE (op
) == SUBREG
640 && GET_CODE (SUBREG_REG (op
)) == TRUNCATE
641 && subreg_lowpart_p (op
))
642 return simplify_gen_unary (TRUNCATE
, mode
, XEXP (SUBREG_REG (op
), 0),
643 GET_MODE (XEXP (SUBREG_REG (op
), 0)));
645 /* If we know that the value is already truncated, we can
646 replace the TRUNCATE with a SUBREG. Note that this is also
647 valid if TRULY_NOOP_TRUNCATION is false for the corresponding
648 modes we just have to apply a different definition for
649 truncation. But don't do this for an (LSHIFTRT (MULT ...))
650 since this will cause problems with the umulXi3_highpart
652 if ((TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode
),
653 GET_MODE_BITSIZE (GET_MODE (op
)))
654 ? (num_sign_bit_copies (op
, GET_MODE (op
))
655 > (unsigned int) (GET_MODE_BITSIZE (GET_MODE (op
))
656 - GET_MODE_BITSIZE (mode
)))
657 : truncated_to_mode (mode
, op
))
658 && ! (GET_CODE (op
) == LSHIFTRT
659 && GET_CODE (XEXP (op
, 0)) == MULT
))
660 return rtl_hooks
.gen_lowpart_no_emit (mode
, op
);
662 /* A truncate of a comparison can be replaced with a subreg if
663 STORE_FLAG_VALUE permits. This is like the previous test,
664 but it works even if the comparison is done in a mode larger
665 than HOST_BITS_PER_WIDE_INT. */
666 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
668 && ((HOST_WIDE_INT
) STORE_FLAG_VALUE
& ~GET_MODE_MASK (mode
)) == 0)
669 return rtl_hooks
.gen_lowpart_no_emit (mode
, op
);
673 if (DECIMAL_FLOAT_MODE_P (mode
))
676 /* (float_truncate:SF (float_extend:DF foo:SF)) = foo:SF. */
677 if (GET_CODE (op
) == FLOAT_EXTEND
678 && GET_MODE (XEXP (op
, 0)) == mode
)
681 /* (float_truncate:SF (float_truncate:DF foo:XF))
682 = (float_truncate:SF foo:XF).
683 This may eliminate double rounding, so it is unsafe.
685 (float_truncate:SF (float_extend:XF foo:DF))
686 = (float_truncate:SF foo:DF).
688 (float_truncate:DF (float_extend:XF foo:SF))
689 = (float_extend:SF foo:DF). */
690 if ((GET_CODE (op
) == FLOAT_TRUNCATE
691 && flag_unsafe_math_optimizations
)
692 || GET_CODE (op
) == FLOAT_EXTEND
)
693 return simplify_gen_unary (GET_MODE_SIZE (GET_MODE (XEXP (op
,
695 > GET_MODE_SIZE (mode
)
696 ? FLOAT_TRUNCATE
: FLOAT_EXTEND
,
700 /* (float_truncate (float x)) is (float x) */
701 if (GET_CODE (op
) == FLOAT
702 && (flag_unsafe_math_optimizations
703 || ((unsigned)significand_size (GET_MODE (op
))
704 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (op
, 0)))
705 - num_sign_bit_copies (XEXP (op
, 0),
706 GET_MODE (XEXP (op
, 0)))))))
707 return simplify_gen_unary (FLOAT
, mode
,
709 GET_MODE (XEXP (op
, 0)));
711 /* (float_truncate:SF (OP:DF (float_extend:DF foo:sf))) is
712 (OP:SF foo:SF) if OP is NEG or ABS. */
713 if ((GET_CODE (op
) == ABS
714 || GET_CODE (op
) == NEG
)
715 && GET_CODE (XEXP (op
, 0)) == FLOAT_EXTEND
716 && GET_MODE (XEXP (XEXP (op
, 0), 0)) == mode
)
717 return simplify_gen_unary (GET_CODE (op
), mode
,
718 XEXP (XEXP (op
, 0), 0), mode
);
720 /* (float_truncate:SF (subreg:DF (float_truncate:SF X) 0))
721 is (float_truncate:SF x). */
722 if (GET_CODE (op
) == SUBREG
723 && subreg_lowpart_p (op
)
724 && GET_CODE (SUBREG_REG (op
)) == FLOAT_TRUNCATE
)
725 return SUBREG_REG (op
);
729 if (DECIMAL_FLOAT_MODE_P (mode
))
732 /* (float_extend (float_extend x)) is (float_extend x)
734 (float_extend (float x)) is (float x) assuming that double
735 rounding can't happen.
737 if (GET_CODE (op
) == FLOAT_EXTEND
738 || (GET_CODE (op
) == FLOAT
739 && ((unsigned)significand_size (GET_MODE (op
))
740 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (op
, 0)))
741 - num_sign_bit_copies (XEXP (op
, 0),
742 GET_MODE (XEXP (op
, 0)))))))
743 return simplify_gen_unary (GET_CODE (op
), mode
,
745 GET_MODE (XEXP (op
, 0)));
750 /* (abs (neg <foo>)) -> (abs <foo>) */
751 if (GET_CODE (op
) == NEG
)
752 return simplify_gen_unary (ABS
, mode
, XEXP (op
, 0),
753 GET_MODE (XEXP (op
, 0)));
755 /* If the mode of the operand is VOIDmode (i.e. if it is ASM_OPERANDS),
757 if (GET_MODE (op
) == VOIDmode
)
760 /* If operand is something known to be positive, ignore the ABS. */
761 if (GET_CODE (op
) == FFS
|| GET_CODE (op
) == ABS
762 || ((GET_MODE_BITSIZE (GET_MODE (op
))
763 <= HOST_BITS_PER_WIDE_INT
)
764 && ((nonzero_bits (op
, GET_MODE (op
))
766 << (GET_MODE_BITSIZE (GET_MODE (op
)) - 1)))
770 /* If operand is known to be only -1 or 0, convert ABS to NEG. */
771 if (num_sign_bit_copies (op
, mode
) == GET_MODE_BITSIZE (mode
))
772 return gen_rtx_NEG (mode
, op
);
777 /* (ffs (*_extend <X>)) = (ffs <X>) */
778 if (GET_CODE (op
) == SIGN_EXTEND
779 || GET_CODE (op
) == ZERO_EXTEND
)
780 return simplify_gen_unary (FFS
, mode
, XEXP (op
, 0),
781 GET_MODE (XEXP (op
, 0)));
785 switch (GET_CODE (op
))
789 /* (popcount (zero_extend <X>)) = (popcount <X>) */
790 return simplify_gen_unary (POPCOUNT
, mode
, XEXP (op
, 0),
791 GET_MODE (XEXP (op
, 0)));
795 /* Rotations don't affect popcount. */
796 if (!side_effects_p (XEXP (op
, 1)))
797 return simplify_gen_unary (POPCOUNT
, mode
, XEXP (op
, 0),
798 GET_MODE (XEXP (op
, 0)));
807 switch (GET_CODE (op
))
813 return simplify_gen_unary (PARITY
, mode
, XEXP (op
, 0),
814 GET_MODE (XEXP (op
, 0)));
818 /* Rotations don't affect parity. */
819 if (!side_effects_p (XEXP (op
, 1)))
820 return simplify_gen_unary (PARITY
, mode
, XEXP (op
, 0),
821 GET_MODE (XEXP (op
, 0)));
830 /* (bswap (bswap x)) -> x. */
831 if (GET_CODE (op
) == BSWAP
)
836 /* (float (sign_extend <X>)) = (float <X>). */
837 if (GET_CODE (op
) == SIGN_EXTEND
)
838 return simplify_gen_unary (FLOAT
, mode
, XEXP (op
, 0),
839 GET_MODE (XEXP (op
, 0)));
843 /* (sign_extend (truncate (minus (label_ref L1) (label_ref L2))))
844 becomes just the MINUS if its mode is MODE. This allows
845 folding switch statements on machines using casesi (such as
847 if (GET_CODE (op
) == TRUNCATE
848 && GET_MODE (XEXP (op
, 0)) == mode
849 && GET_CODE (XEXP (op
, 0)) == MINUS
850 && GET_CODE (XEXP (XEXP (op
, 0), 0)) == LABEL_REF
851 && GET_CODE (XEXP (XEXP (op
, 0), 1)) == LABEL_REF
)
854 /* Check for a sign extension of a subreg of a promoted
855 variable, where the promotion is sign-extended, and the
856 target mode is the same as the variable's promotion. */
857 if (GET_CODE (op
) == SUBREG
858 && SUBREG_PROMOTED_VAR_P (op
)
859 && ! SUBREG_PROMOTED_UNSIGNED_P (op
)
860 && GET_MODE (XEXP (op
, 0)) == mode
)
863 #if defined(POINTERS_EXTEND_UNSIGNED) && !defined(HAVE_ptr_extend)
864 if (! POINTERS_EXTEND_UNSIGNED
865 && mode
== Pmode
&& GET_MODE (op
) == ptr_mode
867 || (GET_CODE (op
) == SUBREG
868 && REG_P (SUBREG_REG (op
))
869 && REG_POINTER (SUBREG_REG (op
))
870 && GET_MODE (SUBREG_REG (op
)) == Pmode
)))
871 return convert_memory_address (Pmode
, op
);
876 /* Check for a zero extension of a subreg of a promoted
877 variable, where the promotion is zero-extended, and the
878 target mode is the same as the variable's promotion. */
879 if (GET_CODE (op
) == SUBREG
880 && SUBREG_PROMOTED_VAR_P (op
)
881 && SUBREG_PROMOTED_UNSIGNED_P (op
) > 0
882 && GET_MODE (XEXP (op
, 0)) == mode
)
885 #if defined(POINTERS_EXTEND_UNSIGNED) && !defined(HAVE_ptr_extend)
886 if (POINTERS_EXTEND_UNSIGNED
> 0
887 && mode
== Pmode
&& GET_MODE (op
) == ptr_mode
889 || (GET_CODE (op
) == SUBREG
890 && REG_P (SUBREG_REG (op
))
891 && REG_POINTER (SUBREG_REG (op
))
892 && GET_MODE (SUBREG_REG (op
)) == Pmode
)))
893 return convert_memory_address (Pmode
, op
);
904 /* Try to compute the value of a unary operation CODE whose output mode is to
905 be MODE with input operand OP whose mode was originally OP_MODE.
906 Return zero if the value cannot be computed. */
908 simplify_const_unary_operation (enum rtx_code code
, enum machine_mode mode
,
909 rtx op
, enum machine_mode op_mode
)
911 unsigned int width
= GET_MODE_BITSIZE (mode
);
913 if (code
== VEC_DUPLICATE
)
915 gcc_assert (VECTOR_MODE_P (mode
));
916 if (GET_MODE (op
) != VOIDmode
)
918 if (!VECTOR_MODE_P (GET_MODE (op
)))
919 gcc_assert (GET_MODE_INNER (mode
) == GET_MODE (op
));
921 gcc_assert (GET_MODE_INNER (mode
) == GET_MODE_INNER
924 if (GET_CODE (op
) == CONST_INT
|| GET_CODE (op
) == CONST_DOUBLE
925 || GET_CODE (op
) == CONST_VECTOR
)
927 int elt_size
= GET_MODE_SIZE (GET_MODE_INNER (mode
));
928 unsigned n_elts
= (GET_MODE_SIZE (mode
) / elt_size
);
929 rtvec v
= rtvec_alloc (n_elts
);
932 if (GET_CODE (op
) != CONST_VECTOR
)
933 for (i
= 0; i
< n_elts
; i
++)
934 RTVEC_ELT (v
, i
) = op
;
937 enum machine_mode inmode
= GET_MODE (op
);
938 int in_elt_size
= GET_MODE_SIZE (GET_MODE_INNER (inmode
));
939 unsigned in_n_elts
= (GET_MODE_SIZE (inmode
) / in_elt_size
);
941 gcc_assert (in_n_elts
< n_elts
);
942 gcc_assert ((n_elts
% in_n_elts
) == 0);
943 for (i
= 0; i
< n_elts
; i
++)
944 RTVEC_ELT (v
, i
) = CONST_VECTOR_ELT (op
, i
% in_n_elts
);
946 return gen_rtx_CONST_VECTOR (mode
, v
);
950 if (VECTOR_MODE_P (mode
) && GET_CODE (op
) == CONST_VECTOR
)
952 int elt_size
= GET_MODE_SIZE (GET_MODE_INNER (mode
));
953 unsigned n_elts
= (GET_MODE_SIZE (mode
) / elt_size
);
954 enum machine_mode opmode
= GET_MODE (op
);
955 int op_elt_size
= GET_MODE_SIZE (GET_MODE_INNER (opmode
));
956 unsigned op_n_elts
= (GET_MODE_SIZE (opmode
) / op_elt_size
);
957 rtvec v
= rtvec_alloc (n_elts
);
960 gcc_assert (op_n_elts
== n_elts
);
961 for (i
= 0; i
< n_elts
; i
++)
963 rtx x
= simplify_unary_operation (code
, GET_MODE_INNER (mode
),
964 CONST_VECTOR_ELT (op
, i
),
965 GET_MODE_INNER (opmode
));
968 RTVEC_ELT (v
, i
) = x
;
970 return gen_rtx_CONST_VECTOR (mode
, v
);
973 /* The order of these tests is critical so that, for example, we don't
974 check the wrong mode (input vs. output) for a conversion operation,
975 such as FIX. At some point, this should be simplified. */
977 if (code
== FLOAT
&& GET_MODE (op
) == VOIDmode
978 && (GET_CODE (op
) == CONST_DOUBLE
|| GET_CODE (op
) == CONST_INT
))
980 HOST_WIDE_INT hv
, lv
;
983 if (GET_CODE (op
) == CONST_INT
)
984 lv
= INTVAL (op
), hv
= HWI_SIGN_EXTEND (lv
);
986 lv
= CONST_DOUBLE_LOW (op
), hv
= CONST_DOUBLE_HIGH (op
);
988 REAL_VALUE_FROM_INT (d
, lv
, hv
, mode
);
989 d
= real_value_truncate (mode
, d
);
990 return CONST_DOUBLE_FROM_REAL_VALUE (d
, mode
);
992 else if (code
== UNSIGNED_FLOAT
&& GET_MODE (op
) == VOIDmode
993 && (GET_CODE (op
) == CONST_DOUBLE
994 || GET_CODE (op
) == CONST_INT
))
996 HOST_WIDE_INT hv
, lv
;
999 if (GET_CODE (op
) == CONST_INT
)
1000 lv
= INTVAL (op
), hv
= HWI_SIGN_EXTEND (lv
);
1002 lv
= CONST_DOUBLE_LOW (op
), hv
= CONST_DOUBLE_HIGH (op
);
1004 if (op_mode
== VOIDmode
)
1006 /* We don't know how to interpret negative-looking numbers in
1007 this case, so don't try to fold those. */
1011 else if (GET_MODE_BITSIZE (op_mode
) >= HOST_BITS_PER_WIDE_INT
* 2)
1014 hv
= 0, lv
&= GET_MODE_MASK (op_mode
);
1016 REAL_VALUE_FROM_UNSIGNED_INT (d
, lv
, hv
, mode
);
1017 d
= real_value_truncate (mode
, d
);
1018 return CONST_DOUBLE_FROM_REAL_VALUE (d
, mode
);
1021 if (GET_CODE (op
) == CONST_INT
1022 && width
<= HOST_BITS_PER_WIDE_INT
&& width
> 0)
1024 HOST_WIDE_INT arg0
= INTVAL (op
);
1038 val
= (arg0
>= 0 ? arg0
: - arg0
);
1042 /* Don't use ffs here. Instead, get low order bit and then its
1043 number. If arg0 is zero, this will return 0, as desired. */
1044 arg0
&= GET_MODE_MASK (mode
);
1045 val
= exact_log2 (arg0
& (- arg0
)) + 1;
1049 arg0
&= GET_MODE_MASK (mode
);
1050 if (arg0
== 0 && CLZ_DEFINED_VALUE_AT_ZERO (mode
, val
))
1053 val
= GET_MODE_BITSIZE (mode
) - floor_log2 (arg0
) - 1;
1057 arg0
&= GET_MODE_MASK (mode
);
1060 /* Even if the value at zero is undefined, we have to come
1061 up with some replacement. Seems good enough. */
1062 if (! CTZ_DEFINED_VALUE_AT_ZERO (mode
, val
))
1063 val
= GET_MODE_BITSIZE (mode
);
1066 val
= exact_log2 (arg0
& -arg0
);
1070 arg0
&= GET_MODE_MASK (mode
);
1073 val
++, arg0
&= arg0
- 1;
1077 arg0
&= GET_MODE_MASK (mode
);
1080 val
++, arg0
&= arg0
- 1;
1089 for (s
= 0; s
< width
; s
+= 8)
1091 unsigned int d
= width
- s
- 8;
1092 unsigned HOST_WIDE_INT byte
;
1093 byte
= (arg0
>> s
) & 0xff;
1104 /* When zero-extending a CONST_INT, we need to know its
1106 gcc_assert (op_mode
!= VOIDmode
);
1107 if (GET_MODE_BITSIZE (op_mode
) == HOST_BITS_PER_WIDE_INT
)
1109 /* If we were really extending the mode,
1110 we would have to distinguish between zero-extension
1111 and sign-extension. */
1112 gcc_assert (width
== GET_MODE_BITSIZE (op_mode
));
1115 else if (GET_MODE_BITSIZE (op_mode
) < HOST_BITS_PER_WIDE_INT
)
1116 val
= arg0
& ~((HOST_WIDE_INT
) (-1) << GET_MODE_BITSIZE (op_mode
));
1122 if (op_mode
== VOIDmode
)
1124 if (GET_MODE_BITSIZE (op_mode
) == HOST_BITS_PER_WIDE_INT
)
1126 /* If we were really extending the mode,
1127 we would have to distinguish between zero-extension
1128 and sign-extension. */
1129 gcc_assert (width
== GET_MODE_BITSIZE (op_mode
));
1132 else if (GET_MODE_BITSIZE (op_mode
) < HOST_BITS_PER_WIDE_INT
)
1135 = arg0
& ~((HOST_WIDE_INT
) (-1) << GET_MODE_BITSIZE (op_mode
));
1137 & ((HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE (op_mode
) - 1)))
1138 val
-= (HOST_WIDE_INT
) 1 << GET_MODE_BITSIZE (op_mode
);
1146 case FLOAT_TRUNCATE
:
1156 return gen_int_mode (val
, mode
);
1159 /* We can do some operations on integer CONST_DOUBLEs. Also allow
1160 for a DImode operation on a CONST_INT. */
1161 else if (GET_MODE (op
) == VOIDmode
1162 && width
<= HOST_BITS_PER_WIDE_INT
* 2
1163 && (GET_CODE (op
) == CONST_DOUBLE
1164 || GET_CODE (op
) == CONST_INT
))
1166 unsigned HOST_WIDE_INT l1
, lv
;
1167 HOST_WIDE_INT h1
, hv
;
1169 if (GET_CODE (op
) == CONST_DOUBLE
)
1170 l1
= CONST_DOUBLE_LOW (op
), h1
= CONST_DOUBLE_HIGH (op
);
1172 l1
= INTVAL (op
), h1
= HWI_SIGN_EXTEND (l1
);
1182 neg_double (l1
, h1
, &lv
, &hv
);
1187 neg_double (l1
, h1
, &lv
, &hv
);
1199 lv
= HOST_BITS_PER_WIDE_INT
+ exact_log2 (h1
& -h1
) + 1;
1202 lv
= exact_log2 (l1
& -l1
) + 1;
1208 lv
= GET_MODE_BITSIZE (mode
) - floor_log2 (h1
) - 1
1209 - HOST_BITS_PER_WIDE_INT
;
1211 lv
= GET_MODE_BITSIZE (mode
) - floor_log2 (l1
) - 1;
1212 else if (! CLZ_DEFINED_VALUE_AT_ZERO (mode
, lv
))
1213 lv
= GET_MODE_BITSIZE (mode
);
1219 lv
= exact_log2 (l1
& -l1
);
1221 lv
= HOST_BITS_PER_WIDE_INT
+ exact_log2 (h1
& -h1
);
1222 else if (! CTZ_DEFINED_VALUE_AT_ZERO (mode
, lv
))
1223 lv
= GET_MODE_BITSIZE (mode
);
1251 for (s
= 0; s
< width
; s
+= 8)
1253 unsigned int d
= width
- s
- 8;
1254 unsigned HOST_WIDE_INT byte
;
1256 if (s
< HOST_BITS_PER_WIDE_INT
)
1257 byte
= (l1
>> s
) & 0xff;
1259 byte
= (h1
>> (s
- HOST_BITS_PER_WIDE_INT
)) & 0xff;
1261 if (d
< HOST_BITS_PER_WIDE_INT
)
1264 hv
|= byte
<< (d
- HOST_BITS_PER_WIDE_INT
);
1270 /* This is just a change-of-mode, so do nothing. */
1275 gcc_assert (op_mode
!= VOIDmode
);
1277 if (GET_MODE_BITSIZE (op_mode
) > HOST_BITS_PER_WIDE_INT
)
1281 lv
= l1
& GET_MODE_MASK (op_mode
);
1285 if (op_mode
== VOIDmode
1286 || GET_MODE_BITSIZE (op_mode
) > HOST_BITS_PER_WIDE_INT
)
1290 lv
= l1
& GET_MODE_MASK (op_mode
);
1291 if (GET_MODE_BITSIZE (op_mode
) < HOST_BITS_PER_WIDE_INT
1292 && (lv
& ((HOST_WIDE_INT
) 1
1293 << (GET_MODE_BITSIZE (op_mode
) - 1))) != 0)
1294 lv
-= (HOST_WIDE_INT
) 1 << GET_MODE_BITSIZE (op_mode
);
1296 hv
= HWI_SIGN_EXTEND (lv
);
1307 return immed_double_const (lv
, hv
, mode
);
1310 else if (GET_CODE (op
) == CONST_DOUBLE
1311 && SCALAR_FLOAT_MODE_P (mode
))
1313 REAL_VALUE_TYPE d
, t
;
1314 REAL_VALUE_FROM_CONST_DOUBLE (d
, op
);
1319 if (HONOR_SNANS (mode
) && real_isnan (&d
))
1321 real_sqrt (&t
, mode
, &d
);
1325 d
= REAL_VALUE_ABS (d
);
1328 d
= REAL_VALUE_NEGATE (d
);
1330 case FLOAT_TRUNCATE
:
1331 d
= real_value_truncate (mode
, d
);
1334 /* All this does is change the mode. */
1337 real_arithmetic (&d
, FIX_TRUNC_EXPR
, &d
, NULL
);
1344 real_to_target (tmp
, &d
, GET_MODE (op
));
1345 for (i
= 0; i
< 4; i
++)
1347 real_from_target (&d
, tmp
, mode
);
1353 return CONST_DOUBLE_FROM_REAL_VALUE (d
, mode
);
1356 else if (GET_CODE (op
) == CONST_DOUBLE
1357 && SCALAR_FLOAT_MODE_P (GET_MODE (op
))
1358 && GET_MODE_CLASS (mode
) == MODE_INT
1359 && width
<= 2*HOST_BITS_PER_WIDE_INT
&& width
> 0)
1361 /* Although the overflow semantics of RTL's FIX and UNSIGNED_FIX
1362 operators are intentionally left unspecified (to ease implementation
1363 by target backends), for consistency, this routine implements the
1364 same semantics for constant folding as used by the middle-end. */
1366 /* This was formerly used only for non-IEEE float.
1367 eggert@twinsun.com says it is safe for IEEE also. */
1368 HOST_WIDE_INT xh
, xl
, th
, tl
;
1369 REAL_VALUE_TYPE x
, t
;
1370 REAL_VALUE_FROM_CONST_DOUBLE (x
, op
);
1374 if (REAL_VALUE_ISNAN (x
))
1377 /* Test against the signed upper bound. */
1378 if (width
> HOST_BITS_PER_WIDE_INT
)
1380 th
= ((unsigned HOST_WIDE_INT
) 1
1381 << (width
- HOST_BITS_PER_WIDE_INT
- 1)) - 1;
1387 tl
= ((unsigned HOST_WIDE_INT
) 1 << (width
- 1)) - 1;
1389 real_from_integer (&t
, VOIDmode
, tl
, th
, 0);
1390 if (REAL_VALUES_LESS (t
, x
))
1397 /* Test against the signed lower bound. */
1398 if (width
> HOST_BITS_PER_WIDE_INT
)
1400 th
= (HOST_WIDE_INT
) -1 << (width
- HOST_BITS_PER_WIDE_INT
- 1);
1406 tl
= (HOST_WIDE_INT
) -1 << (width
- 1);
1408 real_from_integer (&t
, VOIDmode
, tl
, th
, 0);
1409 if (REAL_VALUES_LESS (x
, t
))
1415 REAL_VALUE_TO_INT (&xl
, &xh
, x
);
1419 if (REAL_VALUE_ISNAN (x
) || REAL_VALUE_NEGATIVE (x
))
1422 /* Test against the unsigned upper bound. */
1423 if (width
== 2*HOST_BITS_PER_WIDE_INT
)
1428 else if (width
>= HOST_BITS_PER_WIDE_INT
)
1430 th
= ((unsigned HOST_WIDE_INT
) 1
1431 << (width
- HOST_BITS_PER_WIDE_INT
)) - 1;
1437 tl
= ((unsigned HOST_WIDE_INT
) 1 << width
) - 1;
1439 real_from_integer (&t
, VOIDmode
, tl
, th
, 1);
1440 if (REAL_VALUES_LESS (t
, x
))
1447 REAL_VALUE_TO_INT (&xl
, &xh
, x
);
1453 return immed_double_const (xl
, xh
, mode
);
1459 /* Subroutine of simplify_binary_operation to simplify a commutative,
1460 associative binary operation CODE with result mode MODE, operating
1461 on OP0 and OP1. CODE is currently one of PLUS, MULT, AND, IOR, XOR,
1462 SMIN, SMAX, UMIN or UMAX. Return zero if no simplification or
1463 canonicalization is possible. */
1466 simplify_associative_operation (enum rtx_code code
, enum machine_mode mode
,
1471 /* Linearize the operator to the left. */
1472 if (GET_CODE (op1
) == code
)
1474 /* "(a op b) op (c op d)" becomes "((a op b) op c) op d)". */
1475 if (GET_CODE (op0
) == code
)
1477 tem
= simplify_gen_binary (code
, mode
, op0
, XEXP (op1
, 0));
1478 return simplify_gen_binary (code
, mode
, tem
, XEXP (op1
, 1));
1481 /* "a op (b op c)" becomes "(b op c) op a". */
1482 if (! swap_commutative_operands_p (op1
, op0
))
1483 return simplify_gen_binary (code
, mode
, op1
, op0
);
1490 if (GET_CODE (op0
) == code
)
1492 /* Canonicalize "(x op c) op y" as "(x op y) op c". */
1493 if (swap_commutative_operands_p (XEXP (op0
, 1), op1
))
1495 tem
= simplify_gen_binary (code
, mode
, XEXP (op0
, 0), op1
);
1496 return simplify_gen_binary (code
, mode
, tem
, XEXP (op0
, 1));
1499 /* Attempt to simplify "(a op b) op c" as "a op (b op c)". */
1500 tem
= swap_commutative_operands_p (XEXP (op0
, 1), op1
)
1501 ? simplify_binary_operation (code
, mode
, op1
, XEXP (op0
, 1))
1502 : simplify_binary_operation (code
, mode
, XEXP (op0
, 1), op1
);
1504 return simplify_gen_binary (code
, mode
, XEXP (op0
, 0), tem
);
1506 /* Attempt to simplify "(a op b) op c" as "(a op c) op b". */
1507 tem
= swap_commutative_operands_p (XEXP (op0
, 0), op1
)
1508 ? simplify_binary_operation (code
, mode
, op1
, XEXP (op0
, 0))
1509 : simplify_binary_operation (code
, mode
, XEXP (op0
, 0), op1
);
1511 return simplify_gen_binary (code
, mode
, tem
, XEXP (op0
, 1));
1518 /* Simplify a binary operation CODE with result mode MODE, operating on OP0
1519 and OP1. Return 0 if no simplification is possible.
1521 Don't use this for relational operations such as EQ or LT.
1522 Use simplify_relational_operation instead. */
1524 simplify_binary_operation (enum rtx_code code
, enum machine_mode mode
,
1527 rtx trueop0
, trueop1
;
1530 /* Relational operations don't work here. We must know the mode
1531 of the operands in order to do the comparison correctly.
1532 Assuming a full word can give incorrect results.
1533 Consider comparing 128 with -128 in QImode. */
1534 gcc_assert (GET_RTX_CLASS (code
) != RTX_COMPARE
);
1535 gcc_assert (GET_RTX_CLASS (code
) != RTX_COMM_COMPARE
);
1537 /* Make sure the constant is second. */
1538 if (GET_RTX_CLASS (code
) == RTX_COMM_ARITH
1539 && swap_commutative_operands_p (op0
, op1
))
1541 tem
= op0
, op0
= op1
, op1
= tem
;
1544 trueop0
= avoid_constant_pool_reference (op0
);
1545 trueop1
= avoid_constant_pool_reference (op1
);
1547 tem
= simplify_const_binary_operation (code
, mode
, trueop0
, trueop1
);
1550 return simplify_binary_operation_1 (code
, mode
, op0
, op1
, trueop0
, trueop1
);
1553 /* Subroutine of simplify_binary_operation. Simplify a binary operation
1554 CODE with result mode MODE, operating on OP0 and OP1. If OP0 and/or
1555 OP1 are constant pool references, TRUEOP0 and TRUEOP1 represent the
1556 actual constants. */
1559 simplify_binary_operation_1 (enum rtx_code code
, enum machine_mode mode
,
1560 rtx op0
, rtx op1
, rtx trueop0
, rtx trueop1
)
1562 rtx tem
, reversed
, opleft
, opright
;
1564 unsigned int width
= GET_MODE_BITSIZE (mode
);
1566 /* Even if we can't compute a constant result,
1567 there are some cases worth simplifying. */
1572 /* Maybe simplify x + 0 to x. The two expressions are equivalent
1573 when x is NaN, infinite, or finite and nonzero. They aren't
1574 when x is -0 and the rounding mode is not towards -infinity,
1575 since (-0) + 0 is then 0. */
1576 if (!HONOR_SIGNED_ZEROS (mode
) && trueop1
== CONST0_RTX (mode
))
1579 /* ((-a) + b) -> (b - a) and similarly for (a + (-b)). These
1580 transformations are safe even for IEEE. */
1581 if (GET_CODE (op0
) == NEG
)
1582 return simplify_gen_binary (MINUS
, mode
, op1
, XEXP (op0
, 0));
1583 else if (GET_CODE (op1
) == NEG
)
1584 return simplify_gen_binary (MINUS
, mode
, op0
, XEXP (op1
, 0));
1586 /* (~a) + 1 -> -a */
1587 if (INTEGRAL_MODE_P (mode
)
1588 && GET_CODE (op0
) == NOT
1589 && trueop1
== const1_rtx
)
1590 return simplify_gen_unary (NEG
, mode
, XEXP (op0
, 0), mode
);
1592 /* Handle both-operands-constant cases. We can only add
1593 CONST_INTs to constants since the sum of relocatable symbols
1594 can't be handled by most assemblers. Don't add CONST_INT
1595 to CONST_INT since overflow won't be computed properly if wider
1596 than HOST_BITS_PER_WIDE_INT. */
1598 if (CONSTANT_P (op0
) && GET_MODE (op0
) != VOIDmode
1599 && GET_CODE (op1
) == CONST_INT
)
1600 return plus_constant (op0
, INTVAL (op1
));
1601 else if (CONSTANT_P (op1
) && GET_MODE (op1
) != VOIDmode
1602 && GET_CODE (op0
) == CONST_INT
)
1603 return plus_constant (op1
, INTVAL (op0
));
1605 /* See if this is something like X * C - X or vice versa or
1606 if the multiplication is written as a shift. If so, we can
1607 distribute and make a new multiply, shift, or maybe just
1608 have X (if C is 2 in the example above). But don't make
1609 something more expensive than we had before. */
1611 if (SCALAR_INT_MODE_P (mode
))
1613 HOST_WIDE_INT coeff0h
= 0, coeff1h
= 0;
1614 unsigned HOST_WIDE_INT coeff0l
= 1, coeff1l
= 1;
1615 rtx lhs
= op0
, rhs
= op1
;
1617 if (GET_CODE (lhs
) == NEG
)
1621 lhs
= XEXP (lhs
, 0);
1623 else if (GET_CODE (lhs
) == MULT
1624 && GET_CODE (XEXP (lhs
, 1)) == CONST_INT
)
1626 coeff0l
= INTVAL (XEXP (lhs
, 1));
1627 coeff0h
= INTVAL (XEXP (lhs
, 1)) < 0 ? -1 : 0;
1628 lhs
= XEXP (lhs
, 0);
1630 else if (GET_CODE (lhs
) == ASHIFT
1631 && GET_CODE (XEXP (lhs
, 1)) == CONST_INT
1632 && INTVAL (XEXP (lhs
, 1)) >= 0
1633 && INTVAL (XEXP (lhs
, 1)) < HOST_BITS_PER_WIDE_INT
)
1635 coeff0l
= ((HOST_WIDE_INT
) 1) << INTVAL (XEXP (lhs
, 1));
1637 lhs
= XEXP (lhs
, 0);
1640 if (GET_CODE (rhs
) == NEG
)
1644 rhs
= XEXP (rhs
, 0);
1646 else if (GET_CODE (rhs
) == MULT
1647 && GET_CODE (XEXP (rhs
, 1)) == CONST_INT
)
1649 coeff1l
= INTVAL (XEXP (rhs
, 1));
1650 coeff1h
= INTVAL (XEXP (rhs
, 1)) < 0 ? -1 : 0;
1651 rhs
= XEXP (rhs
, 0);
1653 else if (GET_CODE (rhs
) == ASHIFT
1654 && GET_CODE (XEXP (rhs
, 1)) == CONST_INT
1655 && INTVAL (XEXP (rhs
, 1)) >= 0
1656 && INTVAL (XEXP (rhs
, 1)) < HOST_BITS_PER_WIDE_INT
)
1658 coeff1l
= ((HOST_WIDE_INT
) 1) << INTVAL (XEXP (rhs
, 1));
1660 rhs
= XEXP (rhs
, 0);
1663 if (rtx_equal_p (lhs
, rhs
))
1665 rtx orig
= gen_rtx_PLUS (mode
, op0
, op1
);
1667 unsigned HOST_WIDE_INT l
;
1670 add_double (coeff0l
, coeff0h
, coeff1l
, coeff1h
, &l
, &h
);
1671 coeff
= immed_double_const (l
, h
, mode
);
1673 tem
= simplify_gen_binary (MULT
, mode
, lhs
, coeff
);
1674 return rtx_cost (tem
, SET
) <= rtx_cost (orig
, SET
)
1679 /* (plus (xor X C1) C2) is (xor X (C1^C2)) if C2 is signbit. */
1680 if ((GET_CODE (op1
) == CONST_INT
1681 || GET_CODE (op1
) == CONST_DOUBLE
)
1682 && GET_CODE (op0
) == XOR
1683 && (GET_CODE (XEXP (op0
, 1)) == CONST_INT
1684 || GET_CODE (XEXP (op0
, 1)) == CONST_DOUBLE
)
1685 && mode_signbit_p (mode
, op1
))
1686 return simplify_gen_binary (XOR
, mode
, XEXP (op0
, 0),
1687 simplify_gen_binary (XOR
, mode
, op1
,
1690 /* Canonicalize (plus (mult (neg B) C) A) to (minus A (mult B C)). */
1691 if (!HONOR_SIGN_DEPENDENT_ROUNDING (mode
)
1692 && GET_CODE (op0
) == MULT
1693 && GET_CODE (XEXP (op0
, 0)) == NEG
)
1697 in1
= XEXP (XEXP (op0
, 0), 0);
1698 in2
= XEXP (op0
, 1);
1699 return simplify_gen_binary (MINUS
, mode
, op1
,
1700 simplify_gen_binary (MULT
, mode
,
1704 /* (plus (comparison A B) C) can become (neg (rev-comp A B)) if
1705 C is 1 and STORE_FLAG_VALUE is -1 or if C is -1 and STORE_FLAG_VALUE
1707 if (COMPARISON_P (op0
)
1708 && ((STORE_FLAG_VALUE
== -1 && trueop1
== const1_rtx
)
1709 || (STORE_FLAG_VALUE
== 1 && trueop1
== constm1_rtx
))
1710 && (reversed
= reversed_comparison (op0
, mode
)))
1712 simplify_gen_unary (NEG
, mode
, reversed
, mode
);
1714 /* If one of the operands is a PLUS or a MINUS, see if we can
1715 simplify this by the associative law.
1716 Don't use the associative law for floating point.
1717 The inaccuracy makes it nonassociative,
1718 and subtle programs can break if operations are associated. */
1720 if (INTEGRAL_MODE_P (mode
)
1721 && (plus_minus_operand_p (op0
)
1722 || plus_minus_operand_p (op1
))
1723 && (tem
= simplify_plus_minus (code
, mode
, op0
, op1
)) != 0)
1726 /* Reassociate floating point addition only when the user
1727 specifies unsafe math optimizations. */
1728 if (FLOAT_MODE_P (mode
)
1729 && flag_unsafe_math_optimizations
)
1731 tem
= simplify_associative_operation (code
, mode
, op0
, op1
);
1739 /* Convert (compare FOO (const_int 0)) to FOO unless we aren't
1740 using cc0, in which case we want to leave it as a COMPARE
1741 so we can distinguish it from a register-register-copy.
1743 In IEEE floating point, x-0 is not the same as x. */
1745 if ((TARGET_FLOAT_FORMAT
!= IEEE_FLOAT_FORMAT
1746 || ! FLOAT_MODE_P (mode
) || flag_unsafe_math_optimizations
)
1747 && trueop1
== CONST0_RTX (mode
))
1751 /* Convert (compare (gt (flags) 0) (lt (flags) 0)) to (flags). */
1752 if (((GET_CODE (op0
) == GT
&& GET_CODE (op1
) == LT
)
1753 || (GET_CODE (op0
) == GTU
&& GET_CODE (op1
) == LTU
))
1754 && XEXP (op0
, 1) == const0_rtx
&& XEXP (op1
, 1) == const0_rtx
)
1756 rtx xop00
= XEXP (op0
, 0);
1757 rtx xop10
= XEXP (op1
, 0);
1760 if (GET_CODE (xop00
) == CC0
&& GET_CODE (xop10
) == CC0
)
1762 if (REG_P (xop00
) && REG_P (xop10
)
1763 && GET_MODE (xop00
) == GET_MODE (xop10
)
1764 && REGNO (xop00
) == REGNO (xop10
)
1765 && GET_MODE_CLASS (GET_MODE (xop00
)) == MODE_CC
1766 && GET_MODE_CLASS (GET_MODE (xop10
)) == MODE_CC
)
1773 /* We can't assume x-x is 0 even with non-IEEE floating point,
1774 but since it is zero except in very strange circumstances, we
1775 will treat it as zero with -funsafe-math-optimizations. */
1776 if (rtx_equal_p (trueop0
, trueop1
)
1777 && ! side_effects_p (op0
)
1778 && (! FLOAT_MODE_P (mode
) || flag_unsafe_math_optimizations
))
1779 return CONST0_RTX (mode
);
1781 /* Change subtraction from zero into negation. (0 - x) is the
1782 same as -x when x is NaN, infinite, or finite and nonzero.
1783 But if the mode has signed zeros, and does not round towards
1784 -infinity, then 0 - 0 is 0, not -0. */
1785 if (!HONOR_SIGNED_ZEROS (mode
) && trueop0
== CONST0_RTX (mode
))
1786 return simplify_gen_unary (NEG
, mode
, op1
, mode
);
1788 /* (-1 - a) is ~a. */
1789 if (trueop0
== constm1_rtx
)
1790 return simplify_gen_unary (NOT
, mode
, op1
, mode
);
1792 /* Subtracting 0 has no effect unless the mode has signed zeros
1793 and supports rounding towards -infinity. In such a case,
1795 if (!(HONOR_SIGNED_ZEROS (mode
)
1796 && HONOR_SIGN_DEPENDENT_ROUNDING (mode
))
1797 && trueop1
== CONST0_RTX (mode
))
1800 /* See if this is something like X * C - X or vice versa or
1801 if the multiplication is written as a shift. If so, we can
1802 distribute and make a new multiply, shift, or maybe just
1803 have X (if C is 2 in the example above). But don't make
1804 something more expensive than we had before. */
1806 if (SCALAR_INT_MODE_P (mode
))
1808 HOST_WIDE_INT coeff0h
= 0, negcoeff1h
= -1;
1809 unsigned HOST_WIDE_INT coeff0l
= 1, negcoeff1l
= -1;
1810 rtx lhs
= op0
, rhs
= op1
;
1812 if (GET_CODE (lhs
) == NEG
)
1816 lhs
= XEXP (lhs
, 0);
1818 else if (GET_CODE (lhs
) == MULT
1819 && GET_CODE (XEXP (lhs
, 1)) == CONST_INT
)
1821 coeff0l
= INTVAL (XEXP (lhs
, 1));
1822 coeff0h
= INTVAL (XEXP (lhs
, 1)) < 0 ? -1 : 0;
1823 lhs
= XEXP (lhs
, 0);
1825 else if (GET_CODE (lhs
) == ASHIFT
1826 && GET_CODE (XEXP (lhs
, 1)) == CONST_INT
1827 && INTVAL (XEXP (lhs
, 1)) >= 0
1828 && INTVAL (XEXP (lhs
, 1)) < HOST_BITS_PER_WIDE_INT
)
1830 coeff0l
= ((HOST_WIDE_INT
) 1) << INTVAL (XEXP (lhs
, 1));
1832 lhs
= XEXP (lhs
, 0);
1835 if (GET_CODE (rhs
) == NEG
)
1839 rhs
= XEXP (rhs
, 0);
1841 else if (GET_CODE (rhs
) == MULT
1842 && GET_CODE (XEXP (rhs
, 1)) == CONST_INT
)
1844 negcoeff1l
= -INTVAL (XEXP (rhs
, 1));
1845 negcoeff1h
= INTVAL (XEXP (rhs
, 1)) <= 0 ? 0 : -1;
1846 rhs
= XEXP (rhs
, 0);
1848 else if (GET_CODE (rhs
) == ASHIFT
1849 && GET_CODE (XEXP (rhs
, 1)) == CONST_INT
1850 && INTVAL (XEXP (rhs
, 1)) >= 0
1851 && INTVAL (XEXP (rhs
, 1)) < HOST_BITS_PER_WIDE_INT
)
1853 negcoeff1l
= -(((HOST_WIDE_INT
) 1) << INTVAL (XEXP (rhs
, 1)));
1855 rhs
= XEXP (rhs
, 0);
1858 if (rtx_equal_p (lhs
, rhs
))
1860 rtx orig
= gen_rtx_MINUS (mode
, op0
, op1
);
1862 unsigned HOST_WIDE_INT l
;
1865 add_double (coeff0l
, coeff0h
, negcoeff1l
, negcoeff1h
, &l
, &h
);
1866 coeff
= immed_double_const (l
, h
, mode
);
1868 tem
= simplify_gen_binary (MULT
, mode
, lhs
, coeff
);
1869 return rtx_cost (tem
, SET
) <= rtx_cost (orig
, SET
)
1874 /* (a - (-b)) -> (a + b). True even for IEEE. */
1875 if (GET_CODE (op1
) == NEG
)
1876 return simplify_gen_binary (PLUS
, mode
, op0
, XEXP (op1
, 0));
1878 /* (-x - c) may be simplified as (-c - x). */
1879 if (GET_CODE (op0
) == NEG
1880 && (GET_CODE (op1
) == CONST_INT
1881 || GET_CODE (op1
) == CONST_DOUBLE
))
1883 tem
= simplify_unary_operation (NEG
, mode
, op1
, mode
);
1885 return simplify_gen_binary (MINUS
, mode
, tem
, XEXP (op0
, 0));
1888 /* Don't let a relocatable value get a negative coeff. */
1889 if (GET_CODE (op1
) == CONST_INT
&& GET_MODE (op0
) != VOIDmode
)
1890 return simplify_gen_binary (PLUS
, mode
,
1892 neg_const_int (mode
, op1
));
1894 /* (x - (x & y)) -> (x & ~y) */
1895 if (GET_CODE (op1
) == AND
)
1897 if (rtx_equal_p (op0
, XEXP (op1
, 0)))
1899 tem
= simplify_gen_unary (NOT
, mode
, XEXP (op1
, 1),
1900 GET_MODE (XEXP (op1
, 1)));
1901 return simplify_gen_binary (AND
, mode
, op0
, tem
);
1903 if (rtx_equal_p (op0
, XEXP (op1
, 1)))
1905 tem
= simplify_gen_unary (NOT
, mode
, XEXP (op1
, 0),
1906 GET_MODE (XEXP (op1
, 0)));
1907 return simplify_gen_binary (AND
, mode
, op0
, tem
);
1911 /* If STORE_FLAG_VALUE is 1, (minus 1 (comparison foo bar)) can be done
1912 by reversing the comparison code if valid. */
1913 if (STORE_FLAG_VALUE
== 1
1914 && trueop0
== const1_rtx
1915 && COMPARISON_P (op1
)
1916 && (reversed
= reversed_comparison (op1
, mode
)))
1919 /* Canonicalize (minus A (mult (neg B) C)) to (plus (mult B C) A). */
1920 if (!HONOR_SIGN_DEPENDENT_ROUNDING (mode
)
1921 && GET_CODE (op1
) == MULT
1922 && GET_CODE (XEXP (op1
, 0)) == NEG
)
1926 in1
= XEXP (XEXP (op1
, 0), 0);
1927 in2
= XEXP (op1
, 1);
1928 return simplify_gen_binary (PLUS
, mode
,
1929 simplify_gen_binary (MULT
, mode
,
1934 /* Canonicalize (minus (neg A) (mult B C)) to
1935 (minus (mult (neg B) C) A). */
1936 if (!HONOR_SIGN_DEPENDENT_ROUNDING (mode
)
1937 && GET_CODE (op1
) == MULT
1938 && GET_CODE (op0
) == NEG
)
1942 in1
= simplify_gen_unary (NEG
, mode
, XEXP (op1
, 0), mode
);
1943 in2
= XEXP (op1
, 1);
1944 return simplify_gen_binary (MINUS
, mode
,
1945 simplify_gen_binary (MULT
, mode
,
1950 /* If one of the operands is a PLUS or a MINUS, see if we can
1951 simplify this by the associative law. This will, for example,
1952 canonicalize (minus A (plus B C)) to (minus (minus A B) C).
1953 Don't use the associative law for floating point.
1954 The inaccuracy makes it nonassociative,
1955 and subtle programs can break if operations are associated. */
1957 if (INTEGRAL_MODE_P (mode
)
1958 && (plus_minus_operand_p (op0
)
1959 || plus_minus_operand_p (op1
))
1960 && (tem
= simplify_plus_minus (code
, mode
, op0
, op1
)) != 0)
1965 if (trueop1
== constm1_rtx
)
1966 return simplify_gen_unary (NEG
, mode
, op0
, mode
);
1968 /* Maybe simplify x * 0 to 0. The reduction is not valid if
1969 x is NaN, since x * 0 is then also NaN. Nor is it valid
1970 when the mode has signed zeros, since multiplying a negative
1971 number by 0 will give -0, not 0. */
1972 if (!HONOR_NANS (mode
)
1973 && !HONOR_SIGNED_ZEROS (mode
)
1974 && trueop1
== CONST0_RTX (mode
)
1975 && ! side_effects_p (op0
))
1978 /* In IEEE floating point, x*1 is not equivalent to x for
1980 if (!HONOR_SNANS (mode
)
1981 && trueop1
== CONST1_RTX (mode
))
1984 /* Convert multiply by constant power of two into shift unless
1985 we are still generating RTL. This test is a kludge. */
1986 if (GET_CODE (trueop1
) == CONST_INT
1987 && (val
= exact_log2 (INTVAL (trueop1
))) >= 0
1988 /* If the mode is larger than the host word size, and the
1989 uppermost bit is set, then this isn't a power of two due
1990 to implicit sign extension. */
1991 && (width
<= HOST_BITS_PER_WIDE_INT
1992 || val
!= HOST_BITS_PER_WIDE_INT
- 1))
1993 return simplify_gen_binary (ASHIFT
, mode
, op0
, GEN_INT (val
));
1995 /* Likewise for multipliers wider than a word. */
1996 if (GET_CODE (trueop1
) == CONST_DOUBLE
1997 && (GET_MODE (trueop1
) == VOIDmode
1998 || GET_MODE_CLASS (GET_MODE (trueop1
)) == MODE_INT
)
1999 && GET_MODE (op0
) == mode
2000 && CONST_DOUBLE_LOW (trueop1
) == 0
2001 && (val
= exact_log2 (CONST_DOUBLE_HIGH (trueop1
))) >= 0)
2002 return simplify_gen_binary (ASHIFT
, mode
, op0
,
2003 GEN_INT (val
+ HOST_BITS_PER_WIDE_INT
));
2005 /* x*2 is x+x and x*(-1) is -x */
2006 if (GET_CODE (trueop1
) == CONST_DOUBLE
2007 && SCALAR_FLOAT_MODE_P (GET_MODE (trueop1
))
2008 && GET_MODE (op0
) == mode
)
2011 REAL_VALUE_FROM_CONST_DOUBLE (d
, trueop1
);
2013 if (REAL_VALUES_EQUAL (d
, dconst2
))
2014 return simplify_gen_binary (PLUS
, mode
, op0
, copy_rtx (op0
));
2016 if (!HONOR_SNANS (mode
)
2017 && REAL_VALUES_EQUAL (d
, dconstm1
))
2018 return simplify_gen_unary (NEG
, mode
, op0
, mode
);
2021 /* Optimize -x * -x as x * x. */
2022 if (FLOAT_MODE_P (mode
)
2023 && GET_CODE (op0
) == NEG
2024 && GET_CODE (op1
) == NEG
2025 && rtx_equal_p (XEXP (op0
, 0), XEXP (op1
, 0))
2026 && !side_effects_p (XEXP (op0
, 0)))
2027 return simplify_gen_binary (MULT
, mode
, XEXP (op0
, 0), XEXP (op1
, 0));
2029 /* Likewise, optimize abs(x) * abs(x) as x * x. */
2030 if (SCALAR_FLOAT_MODE_P (mode
)
2031 && GET_CODE (op0
) == ABS
2032 && GET_CODE (op1
) == ABS
2033 && rtx_equal_p (XEXP (op0
, 0), XEXP (op1
, 0))
2034 && !side_effects_p (XEXP (op0
, 0)))
2035 return simplify_gen_binary (MULT
, mode
, XEXP (op0
, 0), XEXP (op1
, 0));
2037 /* Reassociate multiplication, but for floating point MULTs
2038 only when the user specifies unsafe math optimizations. */
2039 if (! FLOAT_MODE_P (mode
)
2040 || flag_unsafe_math_optimizations
)
2042 tem
= simplify_associative_operation (code
, mode
, op0
, op1
);
2049 if (trueop1
== const0_rtx
)
2051 if (GET_CODE (trueop1
) == CONST_INT
2052 && ((INTVAL (trueop1
) & GET_MODE_MASK (mode
))
2053 == GET_MODE_MASK (mode
)))
2055 if (rtx_equal_p (trueop0
, trueop1
) && ! side_effects_p (op0
))
2057 /* A | (~A) -> -1 */
2058 if (((GET_CODE (op0
) == NOT
&& rtx_equal_p (XEXP (op0
, 0), op1
))
2059 || (GET_CODE (op1
) == NOT
&& rtx_equal_p (XEXP (op1
, 0), op0
)))
2060 && ! side_effects_p (op0
)
2061 && SCALAR_INT_MODE_P (mode
))
2064 /* (ior A C) is C if all bits of A that might be nonzero are on in C. */
2065 if (GET_CODE (op1
) == CONST_INT
2066 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
2067 && (nonzero_bits (op0
, mode
) & ~INTVAL (op1
)) == 0)
2070 /* Canonicalize (X & C1) | C2. */
2071 if (GET_CODE (op0
) == AND
2072 && GET_CODE (trueop1
) == CONST_INT
2073 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
)
2075 HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
2076 HOST_WIDE_INT c1
= INTVAL (XEXP (op0
, 1));
2077 HOST_WIDE_INT c2
= INTVAL (trueop1
);
2079 /* If (C1&C2) == C1, then (X&C1)|C2 becomes X. */
2081 && !side_effects_p (XEXP (op0
, 0)))
2084 /* If (C1|C2) == ~0 then (X&C1)|C2 becomes X|C2. */
2085 if (((c1
|c2
) & mask
) == mask
)
2086 return simplify_gen_binary (IOR
, mode
, XEXP (op0
, 0), op1
);
2088 /* Minimize the number of bits set in C1, i.e. C1 := C1 & ~C2. */
2089 if (((c1
& ~c2
) & mask
) != (c1
& mask
))
2091 tem
= simplify_gen_binary (AND
, mode
, XEXP (op0
, 0),
2092 gen_int_mode (c1
& ~c2
, mode
));
2093 return simplify_gen_binary (IOR
, mode
, tem
, op1
);
2097 /* Convert (A & B) | A to A. */
2098 if (GET_CODE (op0
) == AND
2099 && (rtx_equal_p (XEXP (op0
, 0), op1
)
2100 || rtx_equal_p (XEXP (op0
, 1), op1
))
2101 && ! side_effects_p (XEXP (op0
, 0))
2102 && ! side_effects_p (XEXP (op0
, 1)))
2105 /* Convert (ior (ashift A CX) (lshiftrt A CY)) where CX+CY equals the
2106 mode size to (rotate A CX). */
2108 if (GET_CODE (op1
) == ASHIFT
2109 || GET_CODE (op1
) == SUBREG
)
2120 if (GET_CODE (opleft
) == ASHIFT
&& GET_CODE (opright
) == LSHIFTRT
2121 && rtx_equal_p (XEXP (opleft
, 0), XEXP (opright
, 0))
2122 && GET_CODE (XEXP (opleft
, 1)) == CONST_INT
2123 && GET_CODE (XEXP (opright
, 1)) == CONST_INT
2124 && (INTVAL (XEXP (opleft
, 1)) + INTVAL (XEXP (opright
, 1))
2125 == GET_MODE_BITSIZE (mode
)))
2126 return gen_rtx_ROTATE (mode
, XEXP (opright
, 0), XEXP (opleft
, 1));
2128 /* Same, but for ashift that has been "simplified" to a wider mode
2129 by simplify_shift_const. */
2131 if (GET_CODE (opleft
) == SUBREG
2132 && GET_CODE (SUBREG_REG (opleft
)) == ASHIFT
2133 && GET_CODE (opright
) == LSHIFTRT
2134 && GET_CODE (XEXP (opright
, 0)) == SUBREG
2135 && GET_MODE (opleft
) == GET_MODE (XEXP (opright
, 0))
2136 && SUBREG_BYTE (opleft
) == SUBREG_BYTE (XEXP (opright
, 0))
2137 && (GET_MODE_SIZE (GET_MODE (opleft
))
2138 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (opleft
))))
2139 && rtx_equal_p (XEXP (SUBREG_REG (opleft
), 0),
2140 SUBREG_REG (XEXP (opright
, 0)))
2141 && GET_CODE (XEXP (SUBREG_REG (opleft
), 1)) == CONST_INT
2142 && GET_CODE (XEXP (opright
, 1)) == CONST_INT
2143 && (INTVAL (XEXP (SUBREG_REG (opleft
), 1)) + INTVAL (XEXP (opright
, 1))
2144 == GET_MODE_BITSIZE (mode
)))
2145 return gen_rtx_ROTATE (mode
, XEXP (opright
, 0),
2146 XEXP (SUBREG_REG (opleft
), 1));
2148 /* If we have (ior (and (X C1) C2)), simplify this by making
2149 C1 as small as possible if C1 actually changes. */
2150 if (GET_CODE (op1
) == CONST_INT
2151 && (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
2152 || INTVAL (op1
) > 0)
2153 && GET_CODE (op0
) == AND
2154 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
2155 && GET_CODE (op1
) == CONST_INT
2156 && (INTVAL (XEXP (op0
, 1)) & INTVAL (op1
)) != 0)
2157 return simplify_gen_binary (IOR
, mode
,
2159 (AND
, mode
, XEXP (op0
, 0),
2160 GEN_INT (INTVAL (XEXP (op0
, 1))
2164 /* If OP0 is (ashiftrt (plus ...) C), it might actually be
2165 a (sign_extend (plus ...)). Then check if OP1 is a CONST_INT and
2166 the PLUS does not affect any of the bits in OP1: then we can do
2167 the IOR as a PLUS and we can associate. This is valid if OP1
2168 can be safely shifted left C bits. */
2169 if (GET_CODE (trueop1
) == CONST_INT
&& GET_CODE (op0
) == ASHIFTRT
2170 && GET_CODE (XEXP (op0
, 0)) == PLUS
2171 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
2172 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
2173 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
)
2175 int count
= INTVAL (XEXP (op0
, 1));
2176 HOST_WIDE_INT mask
= INTVAL (trueop1
) << count
;
2178 if (mask
>> count
== INTVAL (trueop1
)
2179 && (mask
& nonzero_bits (XEXP (op0
, 0), mode
)) == 0)
2180 return simplify_gen_binary (ASHIFTRT
, mode
,
2181 plus_constant (XEXP (op0
, 0), mask
),
2185 tem
= simplify_associative_operation (code
, mode
, op0
, op1
);
2191 if (trueop1
== const0_rtx
)
2193 if (GET_CODE (trueop1
) == CONST_INT
2194 && ((INTVAL (trueop1
) & GET_MODE_MASK (mode
))
2195 == GET_MODE_MASK (mode
)))
2196 return simplify_gen_unary (NOT
, mode
, op0
, mode
);
2197 if (rtx_equal_p (trueop0
, trueop1
)
2198 && ! side_effects_p (op0
)
2199 && GET_MODE_CLASS (mode
) != MODE_CC
)
2200 return CONST0_RTX (mode
);
2202 /* Canonicalize XOR of the most significant bit to PLUS. */
2203 if ((GET_CODE (op1
) == CONST_INT
2204 || GET_CODE (op1
) == CONST_DOUBLE
)
2205 && mode_signbit_p (mode
, op1
))
2206 return simplify_gen_binary (PLUS
, mode
, op0
, op1
);
2207 /* (xor (plus X C1) C2) is (xor X (C1^C2)) if C1 is signbit. */
2208 if ((GET_CODE (op1
) == CONST_INT
2209 || GET_CODE (op1
) == CONST_DOUBLE
)
2210 && GET_CODE (op0
) == PLUS
2211 && (GET_CODE (XEXP (op0
, 1)) == CONST_INT
2212 || GET_CODE (XEXP (op0
, 1)) == CONST_DOUBLE
)
2213 && mode_signbit_p (mode
, XEXP (op0
, 1)))
2214 return simplify_gen_binary (XOR
, mode
, XEXP (op0
, 0),
2215 simplify_gen_binary (XOR
, mode
, op1
,
2218 /* If we are XORing two things that have no bits in common,
2219 convert them into an IOR. This helps to detect rotation encoded
2220 using those methods and possibly other simplifications. */
2222 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
2223 && (nonzero_bits (op0
, mode
)
2224 & nonzero_bits (op1
, mode
)) == 0)
2225 return (simplify_gen_binary (IOR
, mode
, op0
, op1
));
2227 /* Convert (XOR (NOT x) (NOT y)) to (XOR x y).
2228 Also convert (XOR (NOT x) y) to (NOT (XOR x y)), similarly for
2231 int num_negated
= 0;
2233 if (GET_CODE (op0
) == NOT
)
2234 num_negated
++, op0
= XEXP (op0
, 0);
2235 if (GET_CODE (op1
) == NOT
)
2236 num_negated
++, op1
= XEXP (op1
, 0);
2238 if (num_negated
== 2)
2239 return simplify_gen_binary (XOR
, mode
, op0
, op1
);
2240 else if (num_negated
== 1)
2241 return simplify_gen_unary (NOT
, mode
,
2242 simplify_gen_binary (XOR
, mode
, op0
, op1
),
2246 /* Convert (xor (and A B) B) to (and (not A) B). The latter may
2247 correspond to a machine insn or result in further simplifications
2248 if B is a constant. */
2250 if (GET_CODE (op0
) == AND
2251 && rtx_equal_p (XEXP (op0
, 1), op1
)
2252 && ! side_effects_p (op1
))
2253 return simplify_gen_binary (AND
, mode
,
2254 simplify_gen_unary (NOT
, mode
,
2255 XEXP (op0
, 0), mode
),
2258 else if (GET_CODE (op0
) == AND
2259 && rtx_equal_p (XEXP (op0
, 0), op1
)
2260 && ! side_effects_p (op1
))
2261 return simplify_gen_binary (AND
, mode
,
2262 simplify_gen_unary (NOT
, mode
,
2263 XEXP (op0
, 1), mode
),
2266 /* (xor (comparison foo bar) (const_int 1)) can become the reversed
2267 comparison if STORE_FLAG_VALUE is 1. */
2268 if (STORE_FLAG_VALUE
== 1
2269 && trueop1
== const1_rtx
2270 && COMPARISON_P (op0
)
2271 && (reversed
= reversed_comparison (op0
, mode
)))
2274 /* (lshiftrt foo C) where C is the number of bits in FOO minus 1
2275 is (lt foo (const_int 0)), so we can perform the above
2276 simplification if STORE_FLAG_VALUE is 1. */
2278 if (STORE_FLAG_VALUE
== 1
2279 && trueop1
== const1_rtx
2280 && GET_CODE (op0
) == LSHIFTRT
2281 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
2282 && INTVAL (XEXP (op0
, 1)) == GET_MODE_BITSIZE (mode
) - 1)
2283 return gen_rtx_GE (mode
, XEXP (op0
, 0), const0_rtx
);
2285 /* (xor (comparison foo bar) (const_int sign-bit))
2286 when STORE_FLAG_VALUE is the sign bit. */
2287 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
2288 && ((STORE_FLAG_VALUE
& GET_MODE_MASK (mode
))
2289 == (unsigned HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE (mode
) - 1))
2290 && trueop1
== const_true_rtx
2291 && COMPARISON_P (op0
)
2292 && (reversed
= reversed_comparison (op0
, mode
)))
2297 tem
= simplify_associative_operation (code
, mode
, op0
, op1
);
2303 if (trueop1
== CONST0_RTX (mode
) && ! side_effects_p (op0
))
2305 /* If we are turning off bits already known off in OP0, we need
2307 if (GET_CODE (trueop1
) == CONST_INT
2308 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
2309 && (nonzero_bits (trueop0
, mode
) & ~INTVAL (trueop1
)) == 0)
2311 if (rtx_equal_p (trueop0
, trueop1
) && ! side_effects_p (op0
)
2312 && GET_MODE_CLASS (mode
) != MODE_CC
)
2315 if (((GET_CODE (op0
) == NOT
&& rtx_equal_p (XEXP (op0
, 0), op1
))
2316 || (GET_CODE (op1
) == NOT
&& rtx_equal_p (XEXP (op1
, 0), op0
)))
2317 && ! side_effects_p (op0
)
2318 && GET_MODE_CLASS (mode
) != MODE_CC
)
2319 return CONST0_RTX (mode
);
2321 /* Transform (and (extend X) C) into (zero_extend (and X C)) if
2322 there are no nonzero bits of C outside of X's mode. */
2323 if ((GET_CODE (op0
) == SIGN_EXTEND
2324 || GET_CODE (op0
) == ZERO_EXTEND
)
2325 && GET_CODE (trueop1
) == CONST_INT
2326 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
2327 && (~GET_MODE_MASK (GET_MODE (XEXP (op0
, 0)))
2328 & INTVAL (trueop1
)) == 0)
2330 enum machine_mode imode
= GET_MODE (XEXP (op0
, 0));
2331 tem
= simplify_gen_binary (AND
, imode
, XEXP (op0
, 0),
2332 gen_int_mode (INTVAL (trueop1
),
2334 return simplify_gen_unary (ZERO_EXTEND
, mode
, tem
, imode
);
2337 /* Canonicalize (A | C1) & C2 as (A & C2) | (C1 & C2). */
2338 if (GET_CODE (op0
) == IOR
2339 && GET_CODE (trueop1
) == CONST_INT
2340 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
)
2342 HOST_WIDE_INT tmp
= INTVAL (trueop1
) & INTVAL (XEXP (op0
, 1));
2343 return simplify_gen_binary (IOR
, mode
,
2344 simplify_gen_binary (AND
, mode
,
2345 XEXP (op0
, 0), op1
),
2346 gen_int_mode (tmp
, mode
));
2349 /* Convert (A ^ B) & A to A & (~B) since the latter is often a single
2350 insn (and may simplify more). */
2351 if (GET_CODE (op0
) == XOR
2352 && rtx_equal_p (XEXP (op0
, 0), op1
)
2353 && ! side_effects_p (op1
))
2354 return simplify_gen_binary (AND
, mode
,
2355 simplify_gen_unary (NOT
, mode
,
2356 XEXP (op0
, 1), mode
),
2359 if (GET_CODE (op0
) == XOR
2360 && rtx_equal_p (XEXP (op0
, 1), op1
)
2361 && ! side_effects_p (op1
))
2362 return simplify_gen_binary (AND
, mode
,
2363 simplify_gen_unary (NOT
, mode
,
2364 XEXP (op0
, 0), mode
),
2367 /* Similarly for (~(A ^ B)) & A. */
2368 if (GET_CODE (op0
) == NOT
2369 && GET_CODE (XEXP (op0
, 0)) == XOR
2370 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), op1
)
2371 && ! side_effects_p (op1
))
2372 return simplify_gen_binary (AND
, mode
, XEXP (XEXP (op0
, 0), 1), op1
);
2374 if (GET_CODE (op0
) == NOT
2375 && GET_CODE (XEXP (op0
, 0)) == XOR
2376 && rtx_equal_p (XEXP (XEXP (op0
, 0), 1), op1
)
2377 && ! side_effects_p (op1
))
2378 return simplify_gen_binary (AND
, mode
, XEXP (XEXP (op0
, 0), 0), op1
);
2380 /* Convert (A | B) & A to A. */
2381 if (GET_CODE (op0
) == IOR
2382 && (rtx_equal_p (XEXP (op0
, 0), op1
)
2383 || rtx_equal_p (XEXP (op0
, 1), op1
))
2384 && ! side_effects_p (XEXP (op0
, 0))
2385 && ! side_effects_p (XEXP (op0
, 1)))
2388 /* For constants M and N, if M == (1LL << cst) - 1 && (N & M) == M,
2389 ((A & N) + B) & M -> (A + B) & M
2390 Similarly if (N & M) == 0,
2391 ((A | N) + B) & M -> (A + B) & M
2392 and for - instead of + and/or ^ instead of |. */
2393 if (GET_CODE (trueop1
) == CONST_INT
2394 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
2395 && ~INTVAL (trueop1
)
2396 && (INTVAL (trueop1
) & (INTVAL (trueop1
) + 1)) == 0
2397 && (GET_CODE (op0
) == PLUS
|| GET_CODE (op0
) == MINUS
))
2402 pmop
[0] = XEXP (op0
, 0);
2403 pmop
[1] = XEXP (op0
, 1);
2405 for (which
= 0; which
< 2; which
++)
2408 switch (GET_CODE (tem
))
2411 if (GET_CODE (XEXP (tem
, 1)) == CONST_INT
2412 && (INTVAL (XEXP (tem
, 1)) & INTVAL (trueop1
))
2413 == INTVAL (trueop1
))
2414 pmop
[which
] = XEXP (tem
, 0);
2418 if (GET_CODE (XEXP (tem
, 1)) == CONST_INT
2419 && (INTVAL (XEXP (tem
, 1)) & INTVAL (trueop1
)) == 0)
2420 pmop
[which
] = XEXP (tem
, 0);
2427 if (pmop
[0] != XEXP (op0
, 0) || pmop
[1] != XEXP (op0
, 1))
2429 tem
= simplify_gen_binary (GET_CODE (op0
), mode
,
2431 return simplify_gen_binary (code
, mode
, tem
, op1
);
2434 tem
= simplify_associative_operation (code
, mode
, op0
, op1
);
2440 /* 0/x is 0 (or x&0 if x has side-effects). */
2441 if (trueop0
== CONST0_RTX (mode
))
2443 if (side_effects_p (op1
))
2444 return simplify_gen_binary (AND
, mode
, op1
, trueop0
);
2448 if (trueop1
== CONST1_RTX (mode
))
2449 return rtl_hooks
.gen_lowpart_no_emit (mode
, op0
);
2450 /* Convert divide by power of two into shift. */
2451 if (GET_CODE (trueop1
) == CONST_INT
2452 && (val
= exact_log2 (INTVAL (trueop1
))) > 0)
2453 return simplify_gen_binary (LSHIFTRT
, mode
, op0
, GEN_INT (val
));
2457 /* Handle floating point and integers separately. */
2458 if (SCALAR_FLOAT_MODE_P (mode
))
2460 /* Maybe change 0.0 / x to 0.0. This transformation isn't
2461 safe for modes with NaNs, since 0.0 / 0.0 will then be
2462 NaN rather than 0.0. Nor is it safe for modes with signed
2463 zeros, since dividing 0 by a negative number gives -0.0 */
2464 if (trueop0
== CONST0_RTX (mode
)
2465 && !HONOR_NANS (mode
)
2466 && !HONOR_SIGNED_ZEROS (mode
)
2467 && ! side_effects_p (op1
))
2470 if (trueop1
== CONST1_RTX (mode
)
2471 && !HONOR_SNANS (mode
))
2474 if (GET_CODE (trueop1
) == CONST_DOUBLE
2475 && trueop1
!= CONST0_RTX (mode
))
2478 REAL_VALUE_FROM_CONST_DOUBLE (d
, trueop1
);
2481 if (REAL_VALUES_EQUAL (d
, dconstm1
)
2482 && !HONOR_SNANS (mode
))
2483 return simplify_gen_unary (NEG
, mode
, op0
, mode
);
2485 /* Change FP division by a constant into multiplication.
2486 Only do this with -funsafe-math-optimizations. */
2487 if (flag_unsafe_math_optimizations
2488 && !REAL_VALUES_EQUAL (d
, dconst0
))
2490 REAL_ARITHMETIC (d
, RDIV_EXPR
, dconst1
, d
);
2491 tem
= CONST_DOUBLE_FROM_REAL_VALUE (d
, mode
);
2492 return simplify_gen_binary (MULT
, mode
, op0
, tem
);
2498 /* 0/x is 0 (or x&0 if x has side-effects). */
2499 if (trueop0
== CONST0_RTX (mode
))
2501 if (side_effects_p (op1
))
2502 return simplify_gen_binary (AND
, mode
, op1
, trueop0
);
2506 if (trueop1
== CONST1_RTX (mode
))
2507 return rtl_hooks
.gen_lowpart_no_emit (mode
, op0
);
2509 if (trueop1
== constm1_rtx
)
2511 rtx x
= rtl_hooks
.gen_lowpart_no_emit (mode
, op0
);
2512 return simplify_gen_unary (NEG
, mode
, x
, mode
);
2518 /* 0%x is 0 (or x&0 if x has side-effects). */
2519 if (trueop0
== CONST0_RTX (mode
))
2521 if (side_effects_p (op1
))
2522 return simplify_gen_binary (AND
, mode
, op1
, trueop0
);
2525 /* x%1 is 0 (of x&0 if x has side-effects). */
2526 if (trueop1
== CONST1_RTX (mode
))
2528 if (side_effects_p (op0
))
2529 return simplify_gen_binary (AND
, mode
, op0
, CONST0_RTX (mode
));
2530 return CONST0_RTX (mode
);
2532 /* Implement modulus by power of two as AND. */
2533 if (GET_CODE (trueop1
) == CONST_INT
2534 && exact_log2 (INTVAL (trueop1
)) > 0)
2535 return simplify_gen_binary (AND
, mode
, op0
,
2536 GEN_INT (INTVAL (op1
) - 1));
2540 /* 0%x is 0 (or x&0 if x has side-effects). */
2541 if (trueop0
== CONST0_RTX (mode
))
2543 if (side_effects_p (op1
))
2544 return simplify_gen_binary (AND
, mode
, op1
, trueop0
);
2547 /* x%1 and x%-1 is 0 (or x&0 if x has side-effects). */
2548 if (trueop1
== CONST1_RTX (mode
) || trueop1
== constm1_rtx
)
2550 if (side_effects_p (op0
))
2551 return simplify_gen_binary (AND
, mode
, op0
, CONST0_RTX (mode
));
2552 return CONST0_RTX (mode
);
2559 if (trueop1
== CONST0_RTX (mode
))
2561 if (trueop0
== CONST0_RTX (mode
) && ! side_effects_p (op1
))
2563 /* Rotating ~0 always results in ~0. */
2564 if (GET_CODE (trueop0
) == CONST_INT
&& width
<= HOST_BITS_PER_WIDE_INT
2565 && (unsigned HOST_WIDE_INT
) INTVAL (trueop0
) == GET_MODE_MASK (mode
)
2566 && ! side_effects_p (op1
))
2572 if (trueop1
== CONST0_RTX (mode
))
2574 if (trueop0
== CONST0_RTX (mode
) && ! side_effects_p (op1
))
2579 if (trueop1
== CONST0_RTX (mode
))
2581 if (trueop0
== CONST0_RTX (mode
) && ! side_effects_p (op1
))
2583 /* Optimize (lshiftrt (clz X) C) as (eq X 0). */
2584 if (GET_CODE (op0
) == CLZ
2585 && GET_CODE (trueop1
) == CONST_INT
2586 && STORE_FLAG_VALUE
== 1
2587 && INTVAL (trueop1
) < (HOST_WIDE_INT
)width
)
2589 enum machine_mode imode
= GET_MODE (XEXP (op0
, 0));
2590 unsigned HOST_WIDE_INT zero_val
= 0;
2592 if (CLZ_DEFINED_VALUE_AT_ZERO (imode
, zero_val
)
2593 && zero_val
== GET_MODE_BITSIZE (imode
)
2594 && INTVAL (trueop1
) == exact_log2 (zero_val
))
2595 return simplify_gen_relational (EQ
, mode
, imode
,
2596 XEXP (op0
, 0), const0_rtx
);
2601 if (width
<= HOST_BITS_PER_WIDE_INT
2602 && GET_CODE (trueop1
) == CONST_INT
2603 && INTVAL (trueop1
) == (HOST_WIDE_INT
) 1 << (width
-1)
2604 && ! side_effects_p (op0
))
2606 if (rtx_equal_p (trueop0
, trueop1
) && ! side_effects_p (op0
))
2608 tem
= simplify_associative_operation (code
, mode
, op0
, op1
);
2614 if (width
<= HOST_BITS_PER_WIDE_INT
2615 && GET_CODE (trueop1
) == CONST_INT
2616 && ((unsigned HOST_WIDE_INT
) INTVAL (trueop1
)
2617 == (unsigned HOST_WIDE_INT
) GET_MODE_MASK (mode
) >> 1)
2618 && ! side_effects_p (op0
))
2620 if (rtx_equal_p (trueop0
, trueop1
) && ! side_effects_p (op0
))
2622 tem
= simplify_associative_operation (code
, mode
, op0
, op1
);
2628 if (trueop1
== CONST0_RTX (mode
) && ! side_effects_p (op0
))
2630 if (rtx_equal_p (trueop0
, trueop1
) && ! side_effects_p (op0
))
2632 tem
= simplify_associative_operation (code
, mode
, op0
, op1
);
2638 if (trueop1
== constm1_rtx
&& ! side_effects_p (op0
))
2640 if (rtx_equal_p (trueop0
, trueop1
) && ! side_effects_p (op0
))
2642 tem
= simplify_associative_operation (code
, mode
, op0
, op1
);
2651 /* ??? There are simplifications that can be done. */
2655 if (!VECTOR_MODE_P (mode
))
2657 gcc_assert (VECTOR_MODE_P (GET_MODE (trueop0
)));
2658 gcc_assert (mode
== GET_MODE_INNER (GET_MODE (trueop0
)));
2659 gcc_assert (GET_CODE (trueop1
) == PARALLEL
);
2660 gcc_assert (XVECLEN (trueop1
, 0) == 1);
2661 gcc_assert (GET_CODE (XVECEXP (trueop1
, 0, 0)) == CONST_INT
);
2663 if (GET_CODE (trueop0
) == CONST_VECTOR
)
2664 return CONST_VECTOR_ELT (trueop0
, INTVAL (XVECEXP
2669 gcc_assert (VECTOR_MODE_P (GET_MODE (trueop0
)));
2670 gcc_assert (GET_MODE_INNER (mode
)
2671 == GET_MODE_INNER (GET_MODE (trueop0
)));
2672 gcc_assert (GET_CODE (trueop1
) == PARALLEL
);
2674 if (GET_CODE (trueop0
) == CONST_VECTOR
)
2676 int elt_size
= GET_MODE_SIZE (GET_MODE_INNER (mode
));
2677 unsigned n_elts
= (GET_MODE_SIZE (mode
) / elt_size
);
2678 rtvec v
= rtvec_alloc (n_elts
);
2681 gcc_assert (XVECLEN (trueop1
, 0) == (int) n_elts
);
2682 for (i
= 0; i
< n_elts
; i
++)
2684 rtx x
= XVECEXP (trueop1
, 0, i
);
2686 gcc_assert (GET_CODE (x
) == CONST_INT
);
2687 RTVEC_ELT (v
, i
) = CONST_VECTOR_ELT (trueop0
,
2691 return gen_rtx_CONST_VECTOR (mode
, v
);
2695 if (XVECLEN (trueop1
, 0) == 1
2696 && GET_CODE (XVECEXP (trueop1
, 0, 0)) == CONST_INT
2697 && GET_CODE (trueop0
) == VEC_CONCAT
)
2700 int offset
= INTVAL (XVECEXP (trueop1
, 0, 0)) * GET_MODE_SIZE (mode
);
2702 /* Try to find the element in the VEC_CONCAT. */
2703 while (GET_MODE (vec
) != mode
2704 && GET_CODE (vec
) == VEC_CONCAT
)
2706 HOST_WIDE_INT vec_size
= GET_MODE_SIZE (GET_MODE (XEXP (vec
, 0)));
2707 if (offset
< vec_size
)
2708 vec
= XEXP (vec
, 0);
2712 vec
= XEXP (vec
, 1);
2714 vec
= avoid_constant_pool_reference (vec
);
2717 if (GET_MODE (vec
) == mode
)
2724 enum machine_mode op0_mode
= (GET_MODE (trueop0
) != VOIDmode
2725 ? GET_MODE (trueop0
)
2726 : GET_MODE_INNER (mode
));
2727 enum machine_mode op1_mode
= (GET_MODE (trueop1
) != VOIDmode
2728 ? GET_MODE (trueop1
)
2729 : GET_MODE_INNER (mode
));
2731 gcc_assert (VECTOR_MODE_P (mode
));
2732 gcc_assert (GET_MODE_SIZE (op0_mode
) + GET_MODE_SIZE (op1_mode
)
2733 == GET_MODE_SIZE (mode
));
2735 if (VECTOR_MODE_P (op0_mode
))
2736 gcc_assert (GET_MODE_INNER (mode
)
2737 == GET_MODE_INNER (op0_mode
));
2739 gcc_assert (GET_MODE_INNER (mode
) == op0_mode
);
2741 if (VECTOR_MODE_P (op1_mode
))
2742 gcc_assert (GET_MODE_INNER (mode
)
2743 == GET_MODE_INNER (op1_mode
));
2745 gcc_assert (GET_MODE_INNER (mode
) == op1_mode
);
2747 if ((GET_CODE (trueop0
) == CONST_VECTOR
2748 || GET_CODE (trueop0
) == CONST_INT
2749 || GET_CODE (trueop0
) == CONST_DOUBLE
)
2750 && (GET_CODE (trueop1
) == CONST_VECTOR
2751 || GET_CODE (trueop1
) == CONST_INT
2752 || GET_CODE (trueop1
) == CONST_DOUBLE
))
2754 int elt_size
= GET_MODE_SIZE (GET_MODE_INNER (mode
));
2755 unsigned n_elts
= (GET_MODE_SIZE (mode
) / elt_size
);
2756 rtvec v
= rtvec_alloc (n_elts
);
2758 unsigned in_n_elts
= 1;
2760 if (VECTOR_MODE_P (op0_mode
))
2761 in_n_elts
= (GET_MODE_SIZE (op0_mode
) / elt_size
);
2762 for (i
= 0; i
< n_elts
; i
++)
2766 if (!VECTOR_MODE_P (op0_mode
))
2767 RTVEC_ELT (v
, i
) = trueop0
;
2769 RTVEC_ELT (v
, i
) = CONST_VECTOR_ELT (trueop0
, i
);
2773 if (!VECTOR_MODE_P (op1_mode
))
2774 RTVEC_ELT (v
, i
) = trueop1
;
2776 RTVEC_ELT (v
, i
) = CONST_VECTOR_ELT (trueop1
,
2781 return gen_rtx_CONST_VECTOR (mode
, v
);
2794 simplify_const_binary_operation (enum rtx_code code
, enum machine_mode mode
,
2797 HOST_WIDE_INT arg0
, arg1
, arg0s
, arg1s
;
2799 unsigned int width
= GET_MODE_BITSIZE (mode
);
2801 if (VECTOR_MODE_P (mode
)
2802 && code
!= VEC_CONCAT
2803 && GET_CODE (op0
) == CONST_VECTOR
2804 && GET_CODE (op1
) == CONST_VECTOR
)
2806 unsigned n_elts
= GET_MODE_NUNITS (mode
);
2807 enum machine_mode op0mode
= GET_MODE (op0
);
2808 unsigned op0_n_elts
= GET_MODE_NUNITS (op0mode
);
2809 enum machine_mode op1mode
= GET_MODE (op1
);
2810 unsigned op1_n_elts
= GET_MODE_NUNITS (op1mode
);
2811 rtvec v
= rtvec_alloc (n_elts
);
2814 gcc_assert (op0_n_elts
== n_elts
);
2815 gcc_assert (op1_n_elts
== n_elts
);
2816 for (i
= 0; i
< n_elts
; i
++)
2818 rtx x
= simplify_binary_operation (code
, GET_MODE_INNER (mode
),
2819 CONST_VECTOR_ELT (op0
, i
),
2820 CONST_VECTOR_ELT (op1
, i
));
2823 RTVEC_ELT (v
, i
) = x
;
2826 return gen_rtx_CONST_VECTOR (mode
, v
);
2829 if (VECTOR_MODE_P (mode
)
2830 && code
== VEC_CONCAT
2831 && CONSTANT_P (op0
) && CONSTANT_P (op1
))
2833 unsigned n_elts
= GET_MODE_NUNITS (mode
);
2834 rtvec v
= rtvec_alloc (n_elts
);
2836 gcc_assert (n_elts
>= 2);
2839 gcc_assert (GET_CODE (op0
) != CONST_VECTOR
);
2840 gcc_assert (GET_CODE (op1
) != CONST_VECTOR
);
2842 RTVEC_ELT (v
, 0) = op0
;
2843 RTVEC_ELT (v
, 1) = op1
;
2847 unsigned op0_n_elts
= GET_MODE_NUNITS (GET_MODE (op0
));
2848 unsigned op1_n_elts
= GET_MODE_NUNITS (GET_MODE (op1
));
2851 gcc_assert (GET_CODE (op0
) == CONST_VECTOR
);
2852 gcc_assert (GET_CODE (op1
) == CONST_VECTOR
);
2853 gcc_assert (op0_n_elts
+ op1_n_elts
== n_elts
);
2855 for (i
= 0; i
< op0_n_elts
; ++i
)
2856 RTVEC_ELT (v
, i
) = XVECEXP (op0
, 0, i
);
2857 for (i
= 0; i
< op1_n_elts
; ++i
)
2858 RTVEC_ELT (v
, op0_n_elts
+i
) = XVECEXP (op1
, 0, i
);
2861 return gen_rtx_CONST_VECTOR (mode
, v
);
2864 if (SCALAR_FLOAT_MODE_P (mode
)
2865 && GET_CODE (op0
) == CONST_DOUBLE
2866 && GET_CODE (op1
) == CONST_DOUBLE
2867 && mode
== GET_MODE (op0
) && mode
== GET_MODE (op1
))
2878 real_to_target (tmp0
, CONST_DOUBLE_REAL_VALUE (op0
),
2880 real_to_target (tmp1
, CONST_DOUBLE_REAL_VALUE (op1
),
2882 for (i
= 0; i
< 4; i
++)
2899 real_from_target (&r
, tmp0
, mode
);
2900 return CONST_DOUBLE_FROM_REAL_VALUE (r
, mode
);
2904 REAL_VALUE_TYPE f0
, f1
, value
, result
;
2907 REAL_VALUE_FROM_CONST_DOUBLE (f0
, op0
);
2908 REAL_VALUE_FROM_CONST_DOUBLE (f1
, op1
);
2909 real_convert (&f0
, mode
, &f0
);
2910 real_convert (&f1
, mode
, &f1
);
2912 if (HONOR_SNANS (mode
)
2913 && (REAL_VALUE_ISNAN (f0
) || REAL_VALUE_ISNAN (f1
)))
2917 && REAL_VALUES_EQUAL (f1
, dconst0
)
2918 && (flag_trapping_math
|| ! MODE_HAS_INFINITIES (mode
)))
2921 if (MODE_HAS_INFINITIES (mode
) && HONOR_NANS (mode
)
2922 && flag_trapping_math
2923 && REAL_VALUE_ISINF (f0
) && REAL_VALUE_ISINF (f1
))
2925 int s0
= REAL_VALUE_NEGATIVE (f0
);
2926 int s1
= REAL_VALUE_NEGATIVE (f1
);
2931 /* Inf + -Inf = NaN plus exception. */
2936 /* Inf - Inf = NaN plus exception. */
2941 /* Inf / Inf = NaN plus exception. */
2948 if (code
== MULT
&& MODE_HAS_INFINITIES (mode
) && HONOR_NANS (mode
)
2949 && flag_trapping_math
2950 && ((REAL_VALUE_ISINF (f0
) && REAL_VALUES_EQUAL (f1
, dconst0
))
2951 || (REAL_VALUE_ISINF (f1
)
2952 && REAL_VALUES_EQUAL (f0
, dconst0
))))
2953 /* Inf * 0 = NaN plus exception. */
2956 inexact
= real_arithmetic (&value
, rtx_to_tree_code (code
),
2958 real_convert (&result
, mode
, &value
);
2960 /* Don't constant fold this floating point operation if
2961 the result has overflowed and flag_trapping_math. */
2963 if (flag_trapping_math
2964 && MODE_HAS_INFINITIES (mode
)
2965 && REAL_VALUE_ISINF (result
)
2966 && !REAL_VALUE_ISINF (f0
)
2967 && !REAL_VALUE_ISINF (f1
))
2968 /* Overflow plus exception. */
2971 /* Don't constant fold this floating point operation if the
2972 result may dependent upon the run-time rounding mode and
2973 flag_rounding_math is set, or if GCC's software emulation
2974 is unable to accurately represent the result. */
2976 if ((flag_rounding_math
2977 || (REAL_MODE_FORMAT_COMPOSITE_P (mode
)
2978 && !flag_unsafe_math_optimizations
))
2979 && (inexact
|| !real_identical (&result
, &value
)))
2982 return CONST_DOUBLE_FROM_REAL_VALUE (result
, mode
);
2986 /* We can fold some multi-word operations. */
2987 if (GET_MODE_CLASS (mode
) == MODE_INT
2988 && width
== HOST_BITS_PER_WIDE_INT
* 2
2989 && (GET_CODE (op0
) == CONST_DOUBLE
|| GET_CODE (op0
) == CONST_INT
)
2990 && (GET_CODE (op1
) == CONST_DOUBLE
|| GET_CODE (op1
) == CONST_INT
))
2992 unsigned HOST_WIDE_INT l1
, l2
, lv
, lt
;
2993 HOST_WIDE_INT h1
, h2
, hv
, ht
;
2995 if (GET_CODE (op0
) == CONST_DOUBLE
)
2996 l1
= CONST_DOUBLE_LOW (op0
), h1
= CONST_DOUBLE_HIGH (op0
);
2998 l1
= INTVAL (op0
), h1
= HWI_SIGN_EXTEND (l1
);
3000 if (GET_CODE (op1
) == CONST_DOUBLE
)
3001 l2
= CONST_DOUBLE_LOW (op1
), h2
= CONST_DOUBLE_HIGH (op1
);
3003 l2
= INTVAL (op1
), h2
= HWI_SIGN_EXTEND (l2
);
3008 /* A - B == A + (-B). */
3009 neg_double (l2
, h2
, &lv
, &hv
);
3012 /* Fall through.... */
3015 add_double (l1
, h1
, l2
, h2
, &lv
, &hv
);
3019 mul_double (l1
, h1
, l2
, h2
, &lv
, &hv
);
3023 if (div_and_round_double (TRUNC_DIV_EXPR
, 0, l1
, h1
, l2
, h2
,
3024 &lv
, &hv
, <
, &ht
))
3029 if (div_and_round_double (TRUNC_DIV_EXPR
, 0, l1
, h1
, l2
, h2
,
3030 <
, &ht
, &lv
, &hv
))
3035 if (div_and_round_double (TRUNC_DIV_EXPR
, 1, l1
, h1
, l2
, h2
,
3036 &lv
, &hv
, <
, &ht
))
3041 if (div_and_round_double (TRUNC_DIV_EXPR
, 1, l1
, h1
, l2
, h2
,
3042 <
, &ht
, &lv
, &hv
))
3047 lv
= l1
& l2
, hv
= h1
& h2
;
3051 lv
= l1
| l2
, hv
= h1
| h2
;
3055 lv
= l1
^ l2
, hv
= h1
^ h2
;
3061 && ((unsigned HOST_WIDE_INT
) l1
3062 < (unsigned HOST_WIDE_INT
) l2
)))
3071 && ((unsigned HOST_WIDE_INT
) l1
3072 > (unsigned HOST_WIDE_INT
) l2
)))
3079 if ((unsigned HOST_WIDE_INT
) h1
< (unsigned HOST_WIDE_INT
) h2
3081 && ((unsigned HOST_WIDE_INT
) l1
3082 < (unsigned HOST_WIDE_INT
) l2
)))
3089 if ((unsigned HOST_WIDE_INT
) h1
> (unsigned HOST_WIDE_INT
) h2
3091 && ((unsigned HOST_WIDE_INT
) l1
3092 > (unsigned HOST_WIDE_INT
) l2
)))
3098 case LSHIFTRT
: case ASHIFTRT
:
3100 case ROTATE
: case ROTATERT
:
3101 if (SHIFT_COUNT_TRUNCATED
)
3102 l2
&= (GET_MODE_BITSIZE (mode
) - 1), h2
= 0;
3104 if (h2
!= 0 || l2
>= GET_MODE_BITSIZE (mode
))
3107 if (code
== LSHIFTRT
|| code
== ASHIFTRT
)
3108 rshift_double (l1
, h1
, l2
, GET_MODE_BITSIZE (mode
), &lv
, &hv
,
3110 else if (code
== ASHIFT
)
3111 lshift_double (l1
, h1
, l2
, GET_MODE_BITSIZE (mode
), &lv
, &hv
, 1);
3112 else if (code
== ROTATE
)
3113 lrotate_double (l1
, h1
, l2
, GET_MODE_BITSIZE (mode
), &lv
, &hv
);
3114 else /* code == ROTATERT */
3115 rrotate_double (l1
, h1
, l2
, GET_MODE_BITSIZE (mode
), &lv
, &hv
);
3122 return immed_double_const (lv
, hv
, mode
);
3125 if (GET_CODE (op0
) == CONST_INT
&& GET_CODE (op1
) == CONST_INT
3126 && width
<= HOST_BITS_PER_WIDE_INT
&& width
!= 0)
3128 /* Get the integer argument values in two forms:
3129 zero-extended in ARG0, ARG1 and sign-extended in ARG0S, ARG1S. */
3131 arg0
= INTVAL (op0
);
3132 arg1
= INTVAL (op1
);
3134 if (width
< HOST_BITS_PER_WIDE_INT
)
3136 arg0
&= ((HOST_WIDE_INT
) 1 << width
) - 1;
3137 arg1
&= ((HOST_WIDE_INT
) 1 << width
) - 1;
3140 if (arg0s
& ((HOST_WIDE_INT
) 1 << (width
- 1)))
3141 arg0s
|= ((HOST_WIDE_INT
) (-1) << width
);
3144 if (arg1s
& ((HOST_WIDE_INT
) 1 << (width
- 1)))
3145 arg1s
|= ((HOST_WIDE_INT
) (-1) << width
);
3153 /* Compute the value of the arithmetic. */
3158 val
= arg0s
+ arg1s
;
3162 val
= arg0s
- arg1s
;
3166 val
= arg0s
* arg1s
;
3171 || (arg0s
== (HOST_WIDE_INT
) 1 << (HOST_BITS_PER_WIDE_INT
- 1)
3174 val
= arg0s
/ arg1s
;
3179 || (arg0s
== (HOST_WIDE_INT
) 1 << (HOST_BITS_PER_WIDE_INT
- 1)
3182 val
= arg0s
% arg1s
;
3187 || (arg0s
== (HOST_WIDE_INT
) 1 << (HOST_BITS_PER_WIDE_INT
- 1)
3190 val
= (unsigned HOST_WIDE_INT
) arg0
/ arg1
;
3195 || (arg0s
== (HOST_WIDE_INT
) 1 << (HOST_BITS_PER_WIDE_INT
- 1)
3198 val
= (unsigned HOST_WIDE_INT
) arg0
% arg1
;
3216 /* Truncate the shift if SHIFT_COUNT_TRUNCATED, otherwise make sure
3217 the value is in range. We can't return any old value for
3218 out-of-range arguments because either the middle-end (via
3219 shift_truncation_mask) or the back-end might be relying on
3220 target-specific knowledge. Nor can we rely on
3221 shift_truncation_mask, since the shift might not be part of an
3222 ashlM3, lshrM3 or ashrM3 instruction. */
3223 if (SHIFT_COUNT_TRUNCATED
)
3224 arg1
= (unsigned HOST_WIDE_INT
) arg1
% width
;
3225 else if (arg1
< 0 || arg1
>= GET_MODE_BITSIZE (mode
))
3228 val
= (code
== ASHIFT
3229 ? ((unsigned HOST_WIDE_INT
) arg0
) << arg1
3230 : ((unsigned HOST_WIDE_INT
) arg0
) >> arg1
);
3232 /* Sign-extend the result for arithmetic right shifts. */
3233 if (code
== ASHIFTRT
&& arg0s
< 0 && arg1
> 0)
3234 val
|= ((HOST_WIDE_INT
) -1) << (width
- arg1
);
3242 val
= ((((unsigned HOST_WIDE_INT
) arg0
) << (width
- arg1
))
3243 | (((unsigned HOST_WIDE_INT
) arg0
) >> arg1
));
3251 val
= ((((unsigned HOST_WIDE_INT
) arg0
) << arg1
)
3252 | (((unsigned HOST_WIDE_INT
) arg0
) >> (width
- arg1
)));
3256 /* Do nothing here. */
3260 val
= arg0s
<= arg1s
? arg0s
: arg1s
;
3264 val
= ((unsigned HOST_WIDE_INT
) arg0
3265 <= (unsigned HOST_WIDE_INT
) arg1
? arg0
: arg1
);
3269 val
= arg0s
> arg1s
? arg0s
: arg1s
;
3273 val
= ((unsigned HOST_WIDE_INT
) arg0
3274 > (unsigned HOST_WIDE_INT
) arg1
? arg0
: arg1
);
3282 /* ??? There are simplifications that can be done. */
3289 return gen_int_mode (val
, mode
);
3297 /* Simplify a PLUS or MINUS, at least one of whose operands may be another
3300 Rather than test for specific case, we do this by a brute-force method
3301 and do all possible simplifications until no more changes occur. Then
3302 we rebuild the operation. */
3304 struct simplify_plus_minus_op_data
3311 simplify_plus_minus_op_data_cmp (const void *p1
, const void *p2
)
3313 const struct simplify_plus_minus_op_data
*d1
= p1
;
3314 const struct simplify_plus_minus_op_data
*d2
= p2
;
3317 result
= (commutative_operand_precedence (d2
->op
)
3318 - commutative_operand_precedence (d1
->op
));
3322 /* Group together equal REGs to do more simplification. */
3323 if (REG_P (d1
->op
) && REG_P (d2
->op
))
3324 return REGNO (d1
->op
) - REGNO (d2
->op
);
3330 simplify_plus_minus (enum rtx_code code
, enum machine_mode mode
, rtx op0
,
3333 struct simplify_plus_minus_op_data ops
[8];
3335 int n_ops
= 2, input_ops
= 2;
3336 int changed
, n_constants
= 0, canonicalized
= 0;
3339 memset (ops
, 0, sizeof ops
);
3341 /* Set up the two operands and then expand them until nothing has been
3342 changed. If we run out of room in our array, give up; this should
3343 almost never happen. */
3348 ops
[1].neg
= (code
== MINUS
);
3354 for (i
= 0; i
< n_ops
; i
++)
3356 rtx this_op
= ops
[i
].op
;
3357 int this_neg
= ops
[i
].neg
;
3358 enum rtx_code this_code
= GET_CODE (this_op
);
3367 ops
[n_ops
].op
= XEXP (this_op
, 1);
3368 ops
[n_ops
].neg
= (this_code
== MINUS
) ^ this_neg
;
3371 ops
[i
].op
= XEXP (this_op
, 0);
3374 canonicalized
|= this_neg
;
3378 ops
[i
].op
= XEXP (this_op
, 0);
3379 ops
[i
].neg
= ! this_neg
;
3386 && GET_CODE (XEXP (this_op
, 0)) == PLUS
3387 && CONSTANT_P (XEXP (XEXP (this_op
, 0), 0))
3388 && CONSTANT_P (XEXP (XEXP (this_op
, 0), 1)))
3390 ops
[i
].op
= XEXP (XEXP (this_op
, 0), 0);
3391 ops
[n_ops
].op
= XEXP (XEXP (this_op
, 0), 1);
3392 ops
[n_ops
].neg
= this_neg
;
3400 /* ~a -> (-a - 1) */
3403 ops
[n_ops
].op
= constm1_rtx
;
3404 ops
[n_ops
++].neg
= this_neg
;
3405 ops
[i
].op
= XEXP (this_op
, 0);
3406 ops
[i
].neg
= !this_neg
;
3416 ops
[i
].op
= neg_const_int (mode
, this_op
);
3430 if (n_constants
> 1)
3433 gcc_assert (n_ops
>= 2);
3435 /* If we only have two operands, we can avoid the loops. */
3438 enum rtx_code code
= ops
[0].neg
|| ops
[1].neg
? MINUS
: PLUS
;
3441 /* Get the two operands. Be careful with the order, especially for
3442 the cases where code == MINUS. */
3443 if (ops
[0].neg
&& ops
[1].neg
)
3445 lhs
= gen_rtx_NEG (mode
, ops
[0].op
);
3448 else if (ops
[0].neg
)
3459 return simplify_const_binary_operation (code
, mode
, lhs
, rhs
);
3462 /* Now simplify each pair of operands until nothing changes. */
3465 /* Insertion sort is good enough for an eight-element array. */
3466 for (i
= 1; i
< n_ops
; i
++)
3468 struct simplify_plus_minus_op_data save
;
3470 if (simplify_plus_minus_op_data_cmp (&ops
[j
], &ops
[i
]) < 0)
3476 ops
[j
+ 1] = ops
[j
];
3477 while (j
-- && simplify_plus_minus_op_data_cmp (&ops
[j
], &save
) > 0);
3481 /* This is only useful the first time through. */
3486 for (i
= n_ops
- 1; i
> 0; i
--)
3487 for (j
= i
- 1; j
>= 0; j
--)
3489 rtx lhs
= ops
[j
].op
, rhs
= ops
[i
].op
;
3490 int lneg
= ops
[j
].neg
, rneg
= ops
[i
].neg
;
3492 if (lhs
!= 0 && rhs
!= 0)
3494 enum rtx_code ncode
= PLUS
;
3500 tem
= lhs
, lhs
= rhs
, rhs
= tem
;
3502 else if (swap_commutative_operands_p (lhs
, rhs
))
3503 tem
= lhs
, lhs
= rhs
, rhs
= tem
;
3505 if ((GET_CODE (lhs
) == CONST
|| GET_CODE (lhs
) == CONST_INT
)
3506 && (GET_CODE (rhs
) == CONST
|| GET_CODE (rhs
) == CONST_INT
))
3508 rtx tem_lhs
, tem_rhs
;
3510 tem_lhs
= GET_CODE (lhs
) == CONST
? XEXP (lhs
, 0) : lhs
;
3511 tem_rhs
= GET_CODE (rhs
) == CONST
? XEXP (rhs
, 0) : rhs
;
3512 tem
= simplify_binary_operation (ncode
, mode
, tem_lhs
, tem_rhs
);
3514 if (tem
&& !CONSTANT_P (tem
))
3515 tem
= gen_rtx_CONST (GET_MODE (tem
), tem
);
3518 tem
= simplify_binary_operation (ncode
, mode
, lhs
, rhs
);
3520 /* Reject "simplifications" that just wrap the two
3521 arguments in a CONST. Failure to do so can result
3522 in infinite recursion with simplify_binary_operation
3523 when it calls us to simplify CONST operations. */
3525 && ! (GET_CODE (tem
) == CONST
3526 && GET_CODE (XEXP (tem
, 0)) == ncode
3527 && XEXP (XEXP (tem
, 0), 0) == lhs
3528 && XEXP (XEXP (tem
, 0), 1) == rhs
))
3531 if (GET_CODE (tem
) == NEG
)
3532 tem
= XEXP (tem
, 0), lneg
= !lneg
;
3533 if (GET_CODE (tem
) == CONST_INT
&& lneg
)
3534 tem
= neg_const_int (mode
, tem
), lneg
= 0;
3538 ops
[j
].op
= NULL_RTX
;
3544 /* Pack all the operands to the lower-numbered entries. */
3545 for (i
= 0, j
= 0; j
< n_ops
; j
++)
3555 /* Create (minus -C X) instead of (neg (const (plus X C))). */
3557 && GET_CODE (ops
[1].op
) == CONST_INT
3558 && CONSTANT_P (ops
[0].op
)
3560 return gen_rtx_fmt_ee (MINUS
, mode
, ops
[1].op
, ops
[0].op
);
3562 /* We suppressed creation of trivial CONST expressions in the
3563 combination loop to avoid recursion. Create one manually now.
3564 The combination loop should have ensured that there is exactly
3565 one CONST_INT, and the sort will have ensured that it is last
3566 in the array and that any other constant will be next-to-last. */
3569 && GET_CODE (ops
[n_ops
- 1].op
) == CONST_INT
3570 && CONSTANT_P (ops
[n_ops
- 2].op
))
3572 rtx value
= ops
[n_ops
- 1].op
;
3573 if (ops
[n_ops
- 1].neg
^ ops
[n_ops
- 2].neg
)
3574 value
= neg_const_int (mode
, value
);
3575 ops
[n_ops
- 2].op
= plus_constant (ops
[n_ops
- 2].op
, INTVAL (value
));
3579 /* Put a non-negated operand first, if possible. */
3581 for (i
= 0; i
< n_ops
&& ops
[i
].neg
; i
++)
3584 ops
[0].op
= gen_rtx_NEG (mode
, ops
[0].op
);
3593 /* Now make the result by performing the requested operations. */
3595 for (i
= 1; i
< n_ops
; i
++)
3596 result
= gen_rtx_fmt_ee (ops
[i
].neg
? MINUS
: PLUS
,
3597 mode
, result
, ops
[i
].op
);
3602 /* Check whether an operand is suitable for calling simplify_plus_minus. */
3604 plus_minus_operand_p (rtx x
)
3606 return GET_CODE (x
) == PLUS
3607 || GET_CODE (x
) == MINUS
3608 || (GET_CODE (x
) == CONST
3609 && GET_CODE (XEXP (x
, 0)) == PLUS
3610 && CONSTANT_P (XEXP (XEXP (x
, 0), 0))
3611 && CONSTANT_P (XEXP (XEXP (x
, 0), 1)));
3614 /* Like simplify_binary_operation except used for relational operators.
3615 MODE is the mode of the result. If MODE is VOIDmode, both operands must
3616 not also be VOIDmode.
3618 CMP_MODE specifies in which mode the comparison is done in, so it is
3619 the mode of the operands. If CMP_MODE is VOIDmode, it is taken from
3620 the operands or, if both are VOIDmode, the operands are compared in
3621 "infinite precision". */
3623 simplify_relational_operation (enum rtx_code code
, enum machine_mode mode
,
3624 enum machine_mode cmp_mode
, rtx op0
, rtx op1
)
3626 rtx tem
, trueop0
, trueop1
;
3628 if (cmp_mode
== VOIDmode
)
3629 cmp_mode
= GET_MODE (op0
);
3630 if (cmp_mode
== VOIDmode
)
3631 cmp_mode
= GET_MODE (op1
);
3633 tem
= simplify_const_relational_operation (code
, cmp_mode
, op0
, op1
);
3636 if (SCALAR_FLOAT_MODE_P (mode
))
3638 if (tem
== const0_rtx
)
3639 return CONST0_RTX (mode
);
3640 #ifdef FLOAT_STORE_FLAG_VALUE
3642 REAL_VALUE_TYPE val
;
3643 val
= FLOAT_STORE_FLAG_VALUE (mode
);
3644 return CONST_DOUBLE_FROM_REAL_VALUE (val
, mode
);
3650 if (VECTOR_MODE_P (mode
))
3652 if (tem
== const0_rtx
)
3653 return CONST0_RTX (mode
);
3654 #ifdef VECTOR_STORE_FLAG_VALUE
3659 rtx val
= VECTOR_STORE_FLAG_VALUE (mode
);
3660 if (val
== NULL_RTX
)
3662 if (val
== const1_rtx
)
3663 return CONST1_RTX (mode
);
3665 units
= GET_MODE_NUNITS (mode
);
3666 v
= rtvec_alloc (units
);
3667 for (i
= 0; i
< units
; i
++)
3668 RTVEC_ELT (v
, i
) = val
;
3669 return gen_rtx_raw_CONST_VECTOR (mode
, v
);
3679 /* For the following tests, ensure const0_rtx is op1. */
3680 if (swap_commutative_operands_p (op0
, op1
)
3681 || (op0
== const0_rtx
&& op1
!= const0_rtx
))
3682 tem
= op0
, op0
= op1
, op1
= tem
, code
= swap_condition (code
);
3684 /* If op0 is a compare, extract the comparison arguments from it. */
3685 if (GET_CODE (op0
) == COMPARE
&& op1
== const0_rtx
)
3686 return simplify_relational_operation (code
, mode
, VOIDmode
,
3687 XEXP (op0
, 0), XEXP (op0
, 1));
3689 if (GET_MODE_CLASS (cmp_mode
) == MODE_CC
3693 trueop0
= avoid_constant_pool_reference (op0
);
3694 trueop1
= avoid_constant_pool_reference (op1
);
3695 return simplify_relational_operation_1 (code
, mode
, cmp_mode
,
3699 /* This part of simplify_relational_operation is only used when CMP_MODE
3700 is not in class MODE_CC (i.e. it is a real comparison).
3702 MODE is the mode of the result, while CMP_MODE specifies in which
3703 mode the comparison is done in, so it is the mode of the operands. */
3706 simplify_relational_operation_1 (enum rtx_code code
, enum machine_mode mode
,
3707 enum machine_mode cmp_mode
, rtx op0
, rtx op1
)
3709 enum rtx_code op0code
= GET_CODE (op0
);
3711 if (op1
== const0_rtx
&& COMPARISON_P (op0
))
3713 /* If op0 is a comparison, extract the comparison arguments
3717 if (GET_MODE (op0
) == mode
)
3718 return simplify_rtx (op0
);
3720 return simplify_gen_relational (GET_CODE (op0
), mode
, VOIDmode
,
3721 XEXP (op0
, 0), XEXP (op0
, 1));
3723 else if (code
== EQ
)
3725 enum rtx_code new_code
= reversed_comparison_code (op0
, NULL_RTX
);
3726 if (new_code
!= UNKNOWN
)
3727 return simplify_gen_relational (new_code
, mode
, VOIDmode
,
3728 XEXP (op0
, 0), XEXP (op0
, 1));
3732 if (op1
== const0_rtx
)
3734 /* Canonicalize (GTU x 0) as (NE x 0). */
3736 return simplify_gen_relational (NE
, mode
, cmp_mode
, op0
, op1
);
3737 /* Canonicalize (LEU x 0) as (EQ x 0). */
3739 return simplify_gen_relational (EQ
, mode
, cmp_mode
, op0
, op1
);
3741 else if (op1
== const1_rtx
)
3746 /* Canonicalize (GE x 1) as (GT x 0). */
3747 return simplify_gen_relational (GT
, mode
, cmp_mode
,
3750 /* Canonicalize (GEU x 1) as (NE x 0). */
3751 return simplify_gen_relational (NE
, mode
, cmp_mode
,
3754 /* Canonicalize (LT x 1) as (LE x 0). */
3755 return simplify_gen_relational (LE
, mode
, cmp_mode
,
3758 /* Canonicalize (LTU x 1) as (EQ x 0). */
3759 return simplify_gen_relational (EQ
, mode
, cmp_mode
,
3765 else if (op1
== constm1_rtx
)
3767 /* Canonicalize (LE x -1) as (LT x 0). */
3769 return simplify_gen_relational (LT
, mode
, cmp_mode
, op0
, const0_rtx
);
3770 /* Canonicalize (GT x -1) as (GE x 0). */
3772 return simplify_gen_relational (GE
, mode
, cmp_mode
, op0
, const0_rtx
);
3775 /* (eq/ne (plus x cst1) cst2) simplifies to (eq/ne x (cst2 - cst1)) */
3776 if ((code
== EQ
|| code
== NE
)
3777 && (op0code
== PLUS
|| op0code
== MINUS
)
3779 && CONSTANT_P (XEXP (op0
, 1))
3780 && (INTEGRAL_MODE_P (cmp_mode
) || flag_unsafe_math_optimizations
))
3782 rtx x
= XEXP (op0
, 0);
3783 rtx c
= XEXP (op0
, 1);
3785 c
= simplify_gen_binary (op0code
== PLUS
? MINUS
: PLUS
,
3787 return simplify_gen_relational (code
, mode
, cmp_mode
, x
, c
);
3790 /* (ne:SI (zero_extract:SI FOO (const_int 1) BAR) (const_int 0))) is
3791 the same as (zero_extract:SI FOO (const_int 1) BAR). */
3793 && op1
== const0_rtx
3794 && GET_MODE_CLASS (mode
) == MODE_INT
3795 && cmp_mode
!= VOIDmode
3796 /* ??? Work-around BImode bugs in the ia64 backend. */
3798 && cmp_mode
!= BImode
3799 && nonzero_bits (op0
, cmp_mode
) == 1
3800 && STORE_FLAG_VALUE
== 1)
3801 return GET_MODE_SIZE (mode
) > GET_MODE_SIZE (cmp_mode
)
3802 ? simplify_gen_unary (ZERO_EXTEND
, mode
, op0
, cmp_mode
)
3803 : lowpart_subreg (mode
, op0
, cmp_mode
);
3805 /* (eq/ne (xor x y) 0) simplifies to (eq/ne x y). */
3806 if ((code
== EQ
|| code
== NE
)
3807 && op1
== const0_rtx
3809 return simplify_gen_relational (code
, mode
, cmp_mode
,
3810 XEXP (op0
, 0), XEXP (op0
, 1));
3812 /* (eq/ne (xor x y) x) simplifies to (eq/ne y 0). */
3813 if ((code
== EQ
|| code
== NE
)
3815 && rtx_equal_p (XEXP (op0
, 0), op1
)
3816 && !side_effects_p (XEXP (op0
, 0)))
3817 return simplify_gen_relational (code
, mode
, cmp_mode
,
3818 XEXP (op0
, 1), const0_rtx
);
3820 /* Likewise (eq/ne (xor x y) y) simplifies to (eq/ne x 0). */
3821 if ((code
== EQ
|| code
== NE
)
3823 && rtx_equal_p (XEXP (op0
, 1), op1
)
3824 && !side_effects_p (XEXP (op0
, 1)))
3825 return simplify_gen_relational (code
, mode
, cmp_mode
,
3826 XEXP (op0
, 0), const0_rtx
);
3828 /* (eq/ne (xor x C1) C2) simplifies to (eq/ne x (C1^C2)). */
3829 if ((code
== EQ
|| code
== NE
)
3831 && (GET_CODE (op1
) == CONST_INT
3832 || GET_CODE (op1
) == CONST_DOUBLE
)
3833 && (GET_CODE (XEXP (op0
, 1)) == CONST_INT
3834 || GET_CODE (XEXP (op0
, 1)) == CONST_DOUBLE
))
3835 return simplify_gen_relational (code
, mode
, cmp_mode
, XEXP (op0
, 0),
3836 simplify_gen_binary (XOR
, cmp_mode
,
3837 XEXP (op0
, 1), op1
));
3839 if (op0code
== POPCOUNT
&& op1
== const0_rtx
)
3845 /* (eq (popcount x) (const_int 0)) -> (eq x (const_int 0)). */
3846 return simplify_gen_relational (EQ
, mode
, GET_MODE (XEXP (op0
, 0)),
3847 XEXP (op0
, 0), const0_rtx
);
3852 /* (ne (popcount x) (const_int 0)) -> (ne x (const_int 0)). */
3853 return simplify_gen_relational (NE
, mode
, GET_MODE (XEXP (op0
, 0)),
3854 XEXP (op0
, 0), const0_rtx
);
3863 /* Check if the given comparison (done in the given MODE) is actually a
3864 tautology or a contradiction.
3865 If no simplification is possible, this function returns zero.
3866 Otherwise, it returns either const_true_rtx or const0_rtx. */
3869 simplify_const_relational_operation (enum rtx_code code
,
3870 enum machine_mode mode
,
3873 int equal
, op0lt
, op0ltu
, op1lt
, op1ltu
;
3878 gcc_assert (mode
!= VOIDmode
3879 || (GET_MODE (op0
) == VOIDmode
3880 && GET_MODE (op1
) == VOIDmode
));
3882 /* If op0 is a compare, extract the comparison arguments from it. */
3883 if (GET_CODE (op0
) == COMPARE
&& op1
== const0_rtx
)
3885 op1
= XEXP (op0
, 1);
3886 op0
= XEXP (op0
, 0);
3888 if (GET_MODE (op0
) != VOIDmode
)
3889 mode
= GET_MODE (op0
);
3890 else if (GET_MODE (op1
) != VOIDmode
)
3891 mode
= GET_MODE (op1
);
3896 /* We can't simplify MODE_CC values since we don't know what the
3897 actual comparison is. */
3898 if (GET_MODE_CLASS (GET_MODE (op0
)) == MODE_CC
|| CC0_P (op0
))
3901 /* Make sure the constant is second. */
3902 if (swap_commutative_operands_p (op0
, op1
))
3904 tem
= op0
, op0
= op1
, op1
= tem
;
3905 code
= swap_condition (code
);
3908 trueop0
= avoid_constant_pool_reference (op0
);
3909 trueop1
= avoid_constant_pool_reference (op1
);
3911 /* For integer comparisons of A and B maybe we can simplify A - B and can
3912 then simplify a comparison of that with zero. If A and B are both either
3913 a register or a CONST_INT, this can't help; testing for these cases will
3914 prevent infinite recursion here and speed things up.
3916 We can only do this for EQ and NE comparisons as otherwise we may
3917 lose or introduce overflow which we cannot disregard as undefined as
3918 we do not know the signedness of the operation on either the left or
3919 the right hand side of the comparison. */
3921 if (INTEGRAL_MODE_P (mode
) && trueop1
!= const0_rtx
3922 && (code
== EQ
|| code
== NE
)
3923 && ! ((REG_P (op0
) || GET_CODE (trueop0
) == CONST_INT
)
3924 && (REG_P (op1
) || GET_CODE (trueop1
) == CONST_INT
))
3925 && 0 != (tem
= simplify_binary_operation (MINUS
, mode
, op0
, op1
))
3926 /* We cannot do this if tem is a nonzero address. */
3927 && ! nonzero_address_p (tem
))
3928 return simplify_const_relational_operation (signed_condition (code
),
3929 mode
, tem
, const0_rtx
);
3931 if (! HONOR_NANS (mode
) && code
== ORDERED
)
3932 return const_true_rtx
;
3934 if (! HONOR_NANS (mode
) && code
== UNORDERED
)
3937 /* For modes without NaNs, if the two operands are equal, we know the
3938 result except if they have side-effects. */
3939 if (! HONOR_NANS (GET_MODE (trueop0
))
3940 && rtx_equal_p (trueop0
, trueop1
)
3941 && ! side_effects_p (trueop0
))
3942 equal
= 1, op0lt
= 0, op0ltu
= 0, op1lt
= 0, op1ltu
= 0;
3944 /* If the operands are floating-point constants, see if we can fold
3946 else if (GET_CODE (trueop0
) == CONST_DOUBLE
3947 && GET_CODE (trueop1
) == CONST_DOUBLE
3948 && SCALAR_FLOAT_MODE_P (GET_MODE (trueop0
)))
3950 REAL_VALUE_TYPE d0
, d1
;
3952 REAL_VALUE_FROM_CONST_DOUBLE (d0
, trueop0
);
3953 REAL_VALUE_FROM_CONST_DOUBLE (d1
, trueop1
);
3955 /* Comparisons are unordered iff at least one of the values is NaN. */
3956 if (REAL_VALUE_ISNAN (d0
) || REAL_VALUE_ISNAN (d1
))
3966 return const_true_rtx
;
3979 equal
= REAL_VALUES_EQUAL (d0
, d1
);
3980 op0lt
= op0ltu
= REAL_VALUES_LESS (d0
, d1
);
3981 op1lt
= op1ltu
= REAL_VALUES_LESS (d1
, d0
);
3984 /* Otherwise, see if the operands are both integers. */
3985 else if ((GET_MODE_CLASS (mode
) == MODE_INT
|| mode
== VOIDmode
)
3986 && (GET_CODE (trueop0
) == CONST_DOUBLE
3987 || GET_CODE (trueop0
) == CONST_INT
)
3988 && (GET_CODE (trueop1
) == CONST_DOUBLE
3989 || GET_CODE (trueop1
) == CONST_INT
))
3991 int width
= GET_MODE_BITSIZE (mode
);
3992 HOST_WIDE_INT l0s
, h0s
, l1s
, h1s
;
3993 unsigned HOST_WIDE_INT l0u
, h0u
, l1u
, h1u
;
3995 /* Get the two words comprising each integer constant. */
3996 if (GET_CODE (trueop0
) == CONST_DOUBLE
)
3998 l0u
= l0s
= CONST_DOUBLE_LOW (trueop0
);
3999 h0u
= h0s
= CONST_DOUBLE_HIGH (trueop0
);
4003 l0u
= l0s
= INTVAL (trueop0
);
4004 h0u
= h0s
= HWI_SIGN_EXTEND (l0s
);
4007 if (GET_CODE (trueop1
) == CONST_DOUBLE
)
4009 l1u
= l1s
= CONST_DOUBLE_LOW (trueop1
);
4010 h1u
= h1s
= CONST_DOUBLE_HIGH (trueop1
);
4014 l1u
= l1s
= INTVAL (trueop1
);
4015 h1u
= h1s
= HWI_SIGN_EXTEND (l1s
);
4018 /* If WIDTH is nonzero and smaller than HOST_BITS_PER_WIDE_INT,
4019 we have to sign or zero-extend the values. */
4020 if (width
!= 0 && width
< HOST_BITS_PER_WIDE_INT
)
4022 l0u
&= ((HOST_WIDE_INT
) 1 << width
) - 1;
4023 l1u
&= ((HOST_WIDE_INT
) 1 << width
) - 1;
4025 if (l0s
& ((HOST_WIDE_INT
) 1 << (width
- 1)))
4026 l0s
|= ((HOST_WIDE_INT
) (-1) << width
);
4028 if (l1s
& ((HOST_WIDE_INT
) 1 << (width
- 1)))
4029 l1s
|= ((HOST_WIDE_INT
) (-1) << width
);
4031 if (width
!= 0 && width
<= HOST_BITS_PER_WIDE_INT
)
4032 h0u
= h1u
= 0, h0s
= HWI_SIGN_EXTEND (l0s
), h1s
= HWI_SIGN_EXTEND (l1s
);
4034 equal
= (h0u
== h1u
&& l0u
== l1u
);
4035 op0lt
= (h0s
< h1s
|| (h0s
== h1s
&& l0u
< l1u
));
4036 op1lt
= (h1s
< h0s
|| (h1s
== h0s
&& l1u
< l0u
));
4037 op0ltu
= (h0u
< h1u
|| (h0u
== h1u
&& l0u
< l1u
));
4038 op1ltu
= (h1u
< h0u
|| (h1u
== h0u
&& l1u
< l0u
));
4041 /* Otherwise, there are some code-specific tests we can make. */
4044 /* Optimize comparisons with upper and lower bounds. */
4045 if (SCALAR_INT_MODE_P (mode
)
4046 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
4059 get_mode_bounds (mode
, sign
, mode
, &mmin
, &mmax
);
4066 /* x >= min is always true. */
4067 if (rtx_equal_p (trueop1
, mmin
))
4068 tem
= const_true_rtx
;
4074 /* x <= max is always true. */
4075 if (rtx_equal_p (trueop1
, mmax
))
4076 tem
= const_true_rtx
;
4081 /* x > max is always false. */
4082 if (rtx_equal_p (trueop1
, mmax
))
4088 /* x < min is always false. */
4089 if (rtx_equal_p (trueop1
, mmin
))
4096 if (tem
== const0_rtx
4097 || tem
== const_true_rtx
)
4104 if (trueop1
== const0_rtx
&& nonzero_address_p (op0
))
4109 if (trueop1
== const0_rtx
&& nonzero_address_p (op0
))
4110 return const_true_rtx
;
4114 /* Optimize abs(x) < 0.0. */
4115 if (trueop1
== CONST0_RTX (mode
)
4116 && !HONOR_SNANS (mode
)
4117 && (!INTEGRAL_MODE_P (mode
)
4118 || (!flag_wrapv
&& !flag_trapv
&& flag_strict_overflow
)))
4120 tem
= GET_CODE (trueop0
) == FLOAT_EXTEND
? XEXP (trueop0
, 0)
4122 if (GET_CODE (tem
) == ABS
)
4124 if (INTEGRAL_MODE_P (mode
)
4125 && (issue_strict_overflow_warning
4126 (WARN_STRICT_OVERFLOW_CONDITIONAL
)))
4127 warning (OPT_Wstrict_overflow
,
4128 ("assuming signed overflow does not occur when "
4129 "assuming abs (x) < 0 is false"));
4134 /* Optimize popcount (x) < 0. */
4135 if (GET_CODE (trueop0
) == POPCOUNT
&& trueop1
== const0_rtx
)
4136 return const_true_rtx
;
4140 /* Optimize abs(x) >= 0.0. */
4141 if (trueop1
== CONST0_RTX (mode
)
4142 && !HONOR_NANS (mode
)
4143 && (!INTEGRAL_MODE_P (mode
)
4144 || (!flag_wrapv
&& !flag_trapv
&& flag_strict_overflow
)))
4146 tem
= GET_CODE (trueop0
) == FLOAT_EXTEND
? XEXP (trueop0
, 0)
4148 if (GET_CODE (tem
) == ABS
)
4150 if (INTEGRAL_MODE_P (mode
)
4151 && (issue_strict_overflow_warning
4152 (WARN_STRICT_OVERFLOW_CONDITIONAL
)))
4153 warning (OPT_Wstrict_overflow
,
4154 ("assuming signed overflow does not occur when "
4155 "assuming abs (x) >= 0 is true"));
4156 return const_true_rtx
;
4160 /* Optimize popcount (x) >= 0. */
4161 if (GET_CODE (trueop0
) == POPCOUNT
&& trueop1
== const0_rtx
)
4162 return const_true_rtx
;
4166 /* Optimize ! (abs(x) < 0.0). */
4167 if (trueop1
== CONST0_RTX (mode
))
4169 tem
= GET_CODE (trueop0
) == FLOAT_EXTEND
? XEXP (trueop0
, 0)
4171 if (GET_CODE (tem
) == ABS
)
4172 return const_true_rtx
;
4183 /* If we reach here, EQUAL, OP0LT, OP0LTU, OP1LT, and OP1LTU are set
4189 return equal
? const_true_rtx
: const0_rtx
;
4192 return ! equal
? const_true_rtx
: const0_rtx
;
4195 return op0lt
? const_true_rtx
: const0_rtx
;
4198 return op1lt
? const_true_rtx
: const0_rtx
;
4200 return op0ltu
? const_true_rtx
: const0_rtx
;
4202 return op1ltu
? const_true_rtx
: const0_rtx
;
4205 return equal
|| op0lt
? const_true_rtx
: const0_rtx
;
4208 return equal
|| op1lt
? const_true_rtx
: const0_rtx
;
4210 return equal
|| op0ltu
? const_true_rtx
: const0_rtx
;
4212 return equal
|| op1ltu
? const_true_rtx
: const0_rtx
;
4214 return const_true_rtx
;
4222 /* Simplify CODE, an operation with result mode MODE and three operands,
4223 OP0, OP1, and OP2. OP0_MODE was the mode of OP0 before it became
4224 a constant. Return 0 if no simplifications is possible. */
4227 simplify_ternary_operation (enum rtx_code code
, enum machine_mode mode
,
4228 enum machine_mode op0_mode
, rtx op0
, rtx op1
,
4231 unsigned int width
= GET_MODE_BITSIZE (mode
);
4233 /* VOIDmode means "infinite" precision. */
4235 width
= HOST_BITS_PER_WIDE_INT
;
4241 if (GET_CODE (op0
) == CONST_INT
4242 && GET_CODE (op1
) == CONST_INT
4243 && GET_CODE (op2
) == CONST_INT
4244 && ((unsigned) INTVAL (op1
) + (unsigned) INTVAL (op2
) <= width
)
4245 && width
<= (unsigned) HOST_BITS_PER_WIDE_INT
)
4247 /* Extracting a bit-field from a constant */
4248 HOST_WIDE_INT val
= INTVAL (op0
);
4250 if (BITS_BIG_ENDIAN
)
4251 val
>>= (GET_MODE_BITSIZE (op0_mode
)
4252 - INTVAL (op2
) - INTVAL (op1
));
4254 val
>>= INTVAL (op2
);
4256 if (HOST_BITS_PER_WIDE_INT
!= INTVAL (op1
))
4258 /* First zero-extend. */
4259 val
&= ((HOST_WIDE_INT
) 1 << INTVAL (op1
)) - 1;
4260 /* If desired, propagate sign bit. */
4261 if (code
== SIGN_EXTRACT
4262 && (val
& ((HOST_WIDE_INT
) 1 << (INTVAL (op1
) - 1))))
4263 val
|= ~ (((HOST_WIDE_INT
) 1 << INTVAL (op1
)) - 1);
4266 /* Clear the bits that don't belong in our mode,
4267 unless they and our sign bit are all one.
4268 So we get either a reasonable negative value or a reasonable
4269 unsigned value for this mode. */
4270 if (width
< HOST_BITS_PER_WIDE_INT
4271 && ((val
& ((HOST_WIDE_INT
) (-1) << (width
- 1)))
4272 != ((HOST_WIDE_INT
) (-1) << (width
- 1))))
4273 val
&= ((HOST_WIDE_INT
) 1 << width
) - 1;
4275 return gen_int_mode (val
, mode
);
4280 if (GET_CODE (op0
) == CONST_INT
)
4281 return op0
!= const0_rtx
? op1
: op2
;
4283 /* Convert c ? a : a into "a". */
4284 if (rtx_equal_p (op1
, op2
) && ! side_effects_p (op0
))
4287 /* Convert a != b ? a : b into "a". */
4288 if (GET_CODE (op0
) == NE
4289 && ! side_effects_p (op0
)
4290 && ! HONOR_NANS (mode
)
4291 && ! HONOR_SIGNED_ZEROS (mode
)
4292 && ((rtx_equal_p (XEXP (op0
, 0), op1
)
4293 && rtx_equal_p (XEXP (op0
, 1), op2
))
4294 || (rtx_equal_p (XEXP (op0
, 0), op2
)
4295 && rtx_equal_p (XEXP (op0
, 1), op1
))))
4298 /* Convert a == b ? a : b into "b". */
4299 if (GET_CODE (op0
) == EQ
4300 && ! side_effects_p (op0
)
4301 && ! HONOR_NANS (mode
)
4302 && ! HONOR_SIGNED_ZEROS (mode
)
4303 && ((rtx_equal_p (XEXP (op0
, 0), op1
)
4304 && rtx_equal_p (XEXP (op0
, 1), op2
))
4305 || (rtx_equal_p (XEXP (op0
, 0), op2
)
4306 && rtx_equal_p (XEXP (op0
, 1), op1
))))
4309 if (COMPARISON_P (op0
) && ! side_effects_p (op0
))
4311 enum machine_mode cmp_mode
= (GET_MODE (XEXP (op0
, 0)) == VOIDmode
4312 ? GET_MODE (XEXP (op0
, 1))
4313 : GET_MODE (XEXP (op0
, 0)));
4316 /* Look for happy constants in op1 and op2. */
4317 if (GET_CODE (op1
) == CONST_INT
&& GET_CODE (op2
) == CONST_INT
)
4319 HOST_WIDE_INT t
= INTVAL (op1
);
4320 HOST_WIDE_INT f
= INTVAL (op2
);
4322 if (t
== STORE_FLAG_VALUE
&& f
== 0)
4323 code
= GET_CODE (op0
);
4324 else if (t
== 0 && f
== STORE_FLAG_VALUE
)
4327 tmp
= reversed_comparison_code (op0
, NULL_RTX
);
4335 return simplify_gen_relational (code
, mode
, cmp_mode
,
4336 XEXP (op0
, 0), XEXP (op0
, 1));
4339 if (cmp_mode
== VOIDmode
)
4340 cmp_mode
= op0_mode
;
4341 temp
= simplify_relational_operation (GET_CODE (op0
), op0_mode
,
4342 cmp_mode
, XEXP (op0
, 0),
4345 /* See if any simplifications were possible. */
4348 if (GET_CODE (temp
) == CONST_INT
)
4349 return temp
== const0_rtx
? op2
: op1
;
4351 return gen_rtx_IF_THEN_ELSE (mode
, temp
, op1
, op2
);
4357 gcc_assert (GET_MODE (op0
) == mode
);
4358 gcc_assert (GET_MODE (op1
) == mode
);
4359 gcc_assert (VECTOR_MODE_P (mode
));
4360 op2
= avoid_constant_pool_reference (op2
);
4361 if (GET_CODE (op2
) == CONST_INT
)
4363 int elt_size
= GET_MODE_SIZE (GET_MODE_INNER (mode
));
4364 unsigned n_elts
= (GET_MODE_SIZE (mode
) / elt_size
);
4365 int mask
= (1 << n_elts
) - 1;
4367 if (!(INTVAL (op2
) & mask
))
4369 if ((INTVAL (op2
) & mask
) == mask
)
4372 op0
= avoid_constant_pool_reference (op0
);
4373 op1
= avoid_constant_pool_reference (op1
);
4374 if (GET_CODE (op0
) == CONST_VECTOR
4375 && GET_CODE (op1
) == CONST_VECTOR
)
4377 rtvec v
= rtvec_alloc (n_elts
);
4380 for (i
= 0; i
< n_elts
; i
++)
4381 RTVEC_ELT (v
, i
) = (INTVAL (op2
) & (1 << i
)
4382 ? CONST_VECTOR_ELT (op0
, i
)
4383 : CONST_VECTOR_ELT (op1
, i
));
4384 return gen_rtx_CONST_VECTOR (mode
, v
);
4396 /* Evaluate a SUBREG of a CONST_INT or CONST_DOUBLE or CONST_VECTOR,
4397 returning another CONST_INT or CONST_DOUBLE or CONST_VECTOR.
4399 Works by unpacking OP into a collection of 8-bit values
4400 represented as a little-endian array of 'unsigned char', selecting by BYTE,
4401 and then repacking them again for OUTERMODE. */
4404 simplify_immed_subreg (enum machine_mode outermode
, rtx op
,
4405 enum machine_mode innermode
, unsigned int byte
)
4407 /* We support up to 512-bit values (for V8DFmode). */
4411 value_mask
= (1 << value_bit
) - 1
4413 unsigned char value
[max_bitsize
/ value_bit
];
4422 rtvec result_v
= NULL
;
4423 enum mode_class outer_class
;
4424 enum machine_mode outer_submode
;
4426 /* Some ports misuse CCmode. */
4427 if (GET_MODE_CLASS (outermode
) == MODE_CC
&& GET_CODE (op
) == CONST_INT
)
4430 /* We have no way to represent a complex constant at the rtl level. */
4431 if (COMPLEX_MODE_P (outermode
))
4434 /* Unpack the value. */
4436 if (GET_CODE (op
) == CONST_VECTOR
)
4438 num_elem
= CONST_VECTOR_NUNITS (op
);
4439 elems
= &CONST_VECTOR_ELT (op
, 0);
4440 elem_bitsize
= GET_MODE_BITSIZE (GET_MODE_INNER (innermode
));
4446 elem_bitsize
= max_bitsize
;
4448 /* If this asserts, it is too complicated; reducing value_bit may help. */
4449 gcc_assert (BITS_PER_UNIT
% value_bit
== 0);
4450 /* I don't know how to handle endianness of sub-units. */
4451 gcc_assert (elem_bitsize
% BITS_PER_UNIT
== 0);
4453 for (elem
= 0; elem
< num_elem
; elem
++)
4456 rtx el
= elems
[elem
];
4458 /* Vectors are kept in target memory order. (This is probably
4461 unsigned byte
= (elem
* elem_bitsize
) / BITS_PER_UNIT
;
4462 unsigned ibyte
= (((num_elem
- 1 - elem
) * elem_bitsize
)
4464 unsigned word_byte
= WORDS_BIG_ENDIAN
? ibyte
: byte
;
4465 unsigned subword_byte
= BYTES_BIG_ENDIAN
? ibyte
: byte
;
4466 unsigned bytele
= (subword_byte
% UNITS_PER_WORD
4467 + (word_byte
/ UNITS_PER_WORD
) * UNITS_PER_WORD
);
4468 vp
= value
+ (bytele
* BITS_PER_UNIT
) / value_bit
;
4471 switch (GET_CODE (el
))
4475 i
< HOST_BITS_PER_WIDE_INT
&& i
< elem_bitsize
;
4477 *vp
++ = INTVAL (el
) >> i
;
4478 /* CONST_INTs are always logically sign-extended. */
4479 for (; i
< elem_bitsize
; i
+= value_bit
)
4480 *vp
++ = INTVAL (el
) < 0 ? -1 : 0;
4484 if (GET_MODE (el
) == VOIDmode
)
4486 /* If this triggers, someone should have generated a
4487 CONST_INT instead. */
4488 gcc_assert (elem_bitsize
> HOST_BITS_PER_WIDE_INT
);
4490 for (i
= 0; i
< HOST_BITS_PER_WIDE_INT
; i
+= value_bit
)
4491 *vp
++ = CONST_DOUBLE_LOW (el
) >> i
;
4492 while (i
< HOST_BITS_PER_WIDE_INT
* 2 && i
< elem_bitsize
)
4495 = CONST_DOUBLE_HIGH (el
) >> (i
- HOST_BITS_PER_WIDE_INT
);
4498 /* It shouldn't matter what's done here, so fill it with
4500 for (; i
< elem_bitsize
; i
+= value_bit
)
4505 long tmp
[max_bitsize
/ 32];
4506 int bitsize
= GET_MODE_BITSIZE (GET_MODE (el
));
4508 gcc_assert (SCALAR_FLOAT_MODE_P (GET_MODE (el
)));
4509 gcc_assert (bitsize
<= elem_bitsize
);
4510 gcc_assert (bitsize
% value_bit
== 0);
4512 real_to_target (tmp
, CONST_DOUBLE_REAL_VALUE (el
),
4515 /* real_to_target produces its result in words affected by
4516 FLOAT_WORDS_BIG_ENDIAN. However, we ignore this,
4517 and use WORDS_BIG_ENDIAN instead; see the documentation
4518 of SUBREG in rtl.texi. */
4519 for (i
= 0; i
< bitsize
; i
+= value_bit
)
4522 if (WORDS_BIG_ENDIAN
)
4523 ibase
= bitsize
- 1 - i
;
4526 *vp
++ = tmp
[ibase
/ 32] >> i
% 32;
4529 /* It shouldn't matter what's done here, so fill it with
4531 for (; i
< elem_bitsize
; i
+= value_bit
)
4541 /* Now, pick the right byte to start with. */
4542 /* Renumber BYTE so that the least-significant byte is byte 0. A special
4543 case is paradoxical SUBREGs, which shouldn't be adjusted since they
4544 will already have offset 0. */
4545 if (GET_MODE_SIZE (innermode
) >= GET_MODE_SIZE (outermode
))
4547 unsigned ibyte
= (GET_MODE_SIZE (innermode
) - GET_MODE_SIZE (outermode
)
4549 unsigned word_byte
= WORDS_BIG_ENDIAN
? ibyte
: byte
;
4550 unsigned subword_byte
= BYTES_BIG_ENDIAN
? ibyte
: byte
;
4551 byte
= (subword_byte
% UNITS_PER_WORD
4552 + (word_byte
/ UNITS_PER_WORD
) * UNITS_PER_WORD
);
4555 /* BYTE should still be inside OP. (Note that BYTE is unsigned,
4556 so if it's become negative it will instead be very large.) */
4557 gcc_assert (byte
< GET_MODE_SIZE (innermode
));
4559 /* Convert from bytes to chunks of size value_bit. */
4560 value_start
= byte
* (BITS_PER_UNIT
/ value_bit
);
4562 /* Re-pack the value. */
4564 if (VECTOR_MODE_P (outermode
))
4566 num_elem
= GET_MODE_NUNITS (outermode
);
4567 result_v
= rtvec_alloc (num_elem
);
4568 elems
= &RTVEC_ELT (result_v
, 0);
4569 outer_submode
= GET_MODE_INNER (outermode
);
4575 outer_submode
= outermode
;
4578 outer_class
= GET_MODE_CLASS (outer_submode
);
4579 elem_bitsize
= GET_MODE_BITSIZE (outer_submode
);
4581 gcc_assert (elem_bitsize
% value_bit
== 0);
4582 gcc_assert (elem_bitsize
+ value_start
* value_bit
<= max_bitsize
);
4584 for (elem
= 0; elem
< num_elem
; elem
++)
4588 /* Vectors are stored in target memory order. (This is probably
4591 unsigned byte
= (elem
* elem_bitsize
) / BITS_PER_UNIT
;
4592 unsigned ibyte
= (((num_elem
- 1 - elem
) * elem_bitsize
)
4594 unsigned word_byte
= WORDS_BIG_ENDIAN
? ibyte
: byte
;
4595 unsigned subword_byte
= BYTES_BIG_ENDIAN
? ibyte
: byte
;
4596 unsigned bytele
= (subword_byte
% UNITS_PER_WORD
4597 + (word_byte
/ UNITS_PER_WORD
) * UNITS_PER_WORD
);
4598 vp
= value
+ value_start
+ (bytele
* BITS_PER_UNIT
) / value_bit
;
4601 switch (outer_class
)
4604 case MODE_PARTIAL_INT
:
4606 unsigned HOST_WIDE_INT hi
= 0, lo
= 0;
4609 i
< HOST_BITS_PER_WIDE_INT
&& i
< elem_bitsize
;
4611 lo
|= (HOST_WIDE_INT
)(*vp
++ & value_mask
) << i
;
4612 for (; i
< elem_bitsize
; i
+= value_bit
)
4613 hi
|= ((HOST_WIDE_INT
)(*vp
++ & value_mask
)
4614 << (i
- HOST_BITS_PER_WIDE_INT
));
4616 /* immed_double_const doesn't call trunc_int_for_mode. I don't
4618 if (elem_bitsize
<= HOST_BITS_PER_WIDE_INT
)
4619 elems
[elem
] = gen_int_mode (lo
, outer_submode
);
4620 else if (elem_bitsize
<= 2 * HOST_BITS_PER_WIDE_INT
)
4621 elems
[elem
] = immed_double_const (lo
, hi
, outer_submode
);
4628 case MODE_DECIMAL_FLOAT
:
4631 long tmp
[max_bitsize
/ 32];
4633 /* real_from_target wants its input in words affected by
4634 FLOAT_WORDS_BIG_ENDIAN. However, we ignore this,
4635 and use WORDS_BIG_ENDIAN instead; see the documentation
4636 of SUBREG in rtl.texi. */
4637 for (i
= 0; i
< max_bitsize
/ 32; i
++)
4639 for (i
= 0; i
< elem_bitsize
; i
+= value_bit
)
4642 if (WORDS_BIG_ENDIAN
)
4643 ibase
= elem_bitsize
- 1 - i
;
4646 tmp
[ibase
/ 32] |= (*vp
++ & value_mask
) << i
% 32;
4649 real_from_target (&r
, tmp
, outer_submode
);
4650 elems
[elem
] = CONST_DOUBLE_FROM_REAL_VALUE (r
, outer_submode
);
4658 if (VECTOR_MODE_P (outermode
))
4659 return gen_rtx_CONST_VECTOR (outermode
, result_v
);
4664 /* Simplify SUBREG:OUTERMODE(OP:INNERMODE, BYTE)
4665 Return 0 if no simplifications are possible. */
4667 simplify_subreg (enum machine_mode outermode
, rtx op
,
4668 enum machine_mode innermode
, unsigned int byte
)
4670 /* Little bit of sanity checking. */
4671 gcc_assert (innermode
!= VOIDmode
);
4672 gcc_assert (outermode
!= VOIDmode
);
4673 gcc_assert (innermode
!= BLKmode
);
4674 gcc_assert (outermode
!= BLKmode
);
4676 gcc_assert (GET_MODE (op
) == innermode
4677 || GET_MODE (op
) == VOIDmode
);
4679 gcc_assert ((byte
% GET_MODE_SIZE (outermode
)) == 0);
4680 gcc_assert (byte
< GET_MODE_SIZE (innermode
));
4682 if (outermode
== innermode
&& !byte
)
4685 if (GET_CODE (op
) == CONST_INT
4686 || GET_CODE (op
) == CONST_DOUBLE
4687 || GET_CODE (op
) == CONST_VECTOR
)
4688 return simplify_immed_subreg (outermode
, op
, innermode
, byte
);
4690 /* Changing mode twice with SUBREG => just change it once,
4691 or not at all if changing back op starting mode. */
4692 if (GET_CODE (op
) == SUBREG
)
4694 enum machine_mode innermostmode
= GET_MODE (SUBREG_REG (op
));
4695 int final_offset
= byte
+ SUBREG_BYTE (op
);
4698 if (outermode
== innermostmode
4699 && byte
== 0 && SUBREG_BYTE (op
) == 0)
4700 return SUBREG_REG (op
);
4702 /* The SUBREG_BYTE represents offset, as if the value were stored
4703 in memory. Irritating exception is paradoxical subreg, where
4704 we define SUBREG_BYTE to be 0. On big endian machines, this
4705 value should be negative. For a moment, undo this exception. */
4706 if (byte
== 0 && GET_MODE_SIZE (innermode
) < GET_MODE_SIZE (outermode
))
4708 int difference
= (GET_MODE_SIZE (innermode
) - GET_MODE_SIZE (outermode
));
4709 if (WORDS_BIG_ENDIAN
)
4710 final_offset
+= (difference
/ UNITS_PER_WORD
) * UNITS_PER_WORD
;
4711 if (BYTES_BIG_ENDIAN
)
4712 final_offset
+= difference
% UNITS_PER_WORD
;
4714 if (SUBREG_BYTE (op
) == 0
4715 && GET_MODE_SIZE (innermostmode
) < GET_MODE_SIZE (innermode
))
4717 int difference
= (GET_MODE_SIZE (innermostmode
) - GET_MODE_SIZE (innermode
));
4718 if (WORDS_BIG_ENDIAN
)
4719 final_offset
+= (difference
/ UNITS_PER_WORD
) * UNITS_PER_WORD
;
4720 if (BYTES_BIG_ENDIAN
)
4721 final_offset
+= difference
% UNITS_PER_WORD
;
4724 /* See whether resulting subreg will be paradoxical. */
4725 if (GET_MODE_SIZE (innermostmode
) > GET_MODE_SIZE (outermode
))
4727 /* In nonparadoxical subregs we can't handle negative offsets. */
4728 if (final_offset
< 0)
4730 /* Bail out in case resulting subreg would be incorrect. */
4731 if (final_offset
% GET_MODE_SIZE (outermode
)
4732 || (unsigned) final_offset
>= GET_MODE_SIZE (innermostmode
))
4738 int difference
= (GET_MODE_SIZE (innermostmode
) - GET_MODE_SIZE (outermode
));
4740 /* In paradoxical subreg, see if we are still looking on lower part.
4741 If so, our SUBREG_BYTE will be 0. */
4742 if (WORDS_BIG_ENDIAN
)
4743 offset
+= (difference
/ UNITS_PER_WORD
) * UNITS_PER_WORD
;
4744 if (BYTES_BIG_ENDIAN
)
4745 offset
+= difference
% UNITS_PER_WORD
;
4746 if (offset
== final_offset
)
4752 /* Recurse for further possible simplifications. */
4753 newx
= simplify_subreg (outermode
, SUBREG_REG (op
), innermostmode
,
4757 if (validate_subreg (outermode
, innermostmode
,
4758 SUBREG_REG (op
), final_offset
))
4759 return gen_rtx_SUBREG (outermode
, SUBREG_REG (op
), final_offset
);
4763 /* Merge implicit and explicit truncations. */
4765 if (GET_CODE (op
) == TRUNCATE
4766 && GET_MODE_SIZE (outermode
) < GET_MODE_SIZE (innermode
)
4767 && subreg_lowpart_offset (outermode
, innermode
) == byte
)
4768 return simplify_gen_unary (TRUNCATE
, outermode
, XEXP (op
, 0),
4769 GET_MODE (XEXP (op
, 0)));
4771 /* SUBREG of a hard register => just change the register number
4772 and/or mode. If the hard register is not valid in that mode,
4773 suppress this simplification. If the hard register is the stack,
4774 frame, or argument pointer, leave this as a SUBREG. */
4777 && REGNO (op
) < FIRST_PSEUDO_REGISTER
4778 #ifdef CANNOT_CHANGE_MODE_CLASS
4779 && ! (REG_CANNOT_CHANGE_MODE_P (REGNO (op
), innermode
, outermode
)
4780 && GET_MODE_CLASS (innermode
) != MODE_COMPLEX_INT
4781 && GET_MODE_CLASS (innermode
) != MODE_COMPLEX_FLOAT
)
4783 && ((reload_completed
&& !frame_pointer_needed
)
4784 || (REGNO (op
) != FRAME_POINTER_REGNUM
4785 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
4786 && REGNO (op
) != HARD_FRAME_POINTER_REGNUM
4789 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
4790 && REGNO (op
) != ARG_POINTER_REGNUM
4792 && REGNO (op
) != STACK_POINTER_REGNUM
4793 && subreg_offset_representable_p (REGNO (op
), innermode
,
4796 unsigned int regno
= REGNO (op
);
4797 unsigned int final_regno
4798 = regno
+ subreg_regno_offset (regno
, innermode
, byte
, outermode
);
4800 /* ??? We do allow it if the current REG is not valid for
4801 its mode. This is a kludge to work around how float/complex
4802 arguments are passed on 32-bit SPARC and should be fixed. */
4803 if (HARD_REGNO_MODE_OK (final_regno
, outermode
)
4804 || ! HARD_REGNO_MODE_OK (regno
, innermode
))
4807 int final_offset
= byte
;
4809 /* Adjust offset for paradoxical subregs. */
4811 && GET_MODE_SIZE (innermode
) < GET_MODE_SIZE (outermode
))
4813 int difference
= (GET_MODE_SIZE (innermode
)
4814 - GET_MODE_SIZE (outermode
));
4815 if (WORDS_BIG_ENDIAN
)
4816 final_offset
+= (difference
/ UNITS_PER_WORD
) * UNITS_PER_WORD
;
4817 if (BYTES_BIG_ENDIAN
)
4818 final_offset
+= difference
% UNITS_PER_WORD
;
4821 x
= gen_rtx_REG_offset (op
, outermode
, final_regno
, final_offset
);
4823 /* Propagate original regno. We don't have any way to specify
4824 the offset inside original regno, so do so only for lowpart.
4825 The information is used only by alias analysis that can not
4826 grog partial register anyway. */
4828 if (subreg_lowpart_offset (outermode
, innermode
) == byte
)
4829 ORIGINAL_REGNO (x
) = ORIGINAL_REGNO (op
);
4834 /* If we have a SUBREG of a register that we are replacing and we are
4835 replacing it with a MEM, make a new MEM and try replacing the
4836 SUBREG with it. Don't do this if the MEM has a mode-dependent address
4837 or if we would be widening it. */
4840 && ! mode_dependent_address_p (XEXP (op
, 0))
4841 /* Allow splitting of volatile memory references in case we don't
4842 have instruction to move the whole thing. */
4843 && (! MEM_VOLATILE_P (op
)
4844 || ! have_insn_for (SET
, innermode
))
4845 && GET_MODE_SIZE (outermode
) <= GET_MODE_SIZE (GET_MODE (op
)))
4846 return adjust_address_nv (op
, outermode
, byte
);
4848 /* Handle complex values represented as CONCAT
4849 of real and imaginary part. */
4850 if (GET_CODE (op
) == CONCAT
)
4852 unsigned int part_size
, final_offset
;
4855 part_size
= GET_MODE_UNIT_SIZE (GET_MODE (XEXP (op
, 0)));
4856 if (byte
< part_size
)
4858 part
= XEXP (op
, 0);
4859 final_offset
= byte
;
4863 part
= XEXP (op
, 1);
4864 final_offset
= byte
- part_size
;
4867 if (final_offset
+ GET_MODE_SIZE (outermode
) > part_size
)
4870 res
= simplify_subreg (outermode
, part
, GET_MODE (part
), final_offset
);
4873 if (validate_subreg (outermode
, GET_MODE (part
), part
, final_offset
))
4874 return gen_rtx_SUBREG (outermode
, part
, final_offset
);
4878 /* Optimize SUBREG truncations of zero and sign extended values. */
4879 if ((GET_CODE (op
) == ZERO_EXTEND
4880 || GET_CODE (op
) == SIGN_EXTEND
)
4881 && GET_MODE_BITSIZE (outermode
) < GET_MODE_BITSIZE (innermode
))
4883 unsigned int bitpos
= subreg_lsb_1 (outermode
, innermode
, byte
);
4885 /* If we're requesting the lowpart of a zero or sign extension,
4886 there are three possibilities. If the outermode is the same
4887 as the origmode, we can omit both the extension and the subreg.
4888 If the outermode is not larger than the origmode, we can apply
4889 the truncation without the extension. Finally, if the outermode
4890 is larger than the origmode, but both are integer modes, we
4891 can just extend to the appropriate mode. */
4894 enum machine_mode origmode
= GET_MODE (XEXP (op
, 0));
4895 if (outermode
== origmode
)
4896 return XEXP (op
, 0);
4897 if (GET_MODE_BITSIZE (outermode
) <= GET_MODE_BITSIZE (origmode
))
4898 return simplify_gen_subreg (outermode
, XEXP (op
, 0), origmode
,
4899 subreg_lowpart_offset (outermode
,
4901 if (SCALAR_INT_MODE_P (outermode
))
4902 return simplify_gen_unary (GET_CODE (op
), outermode
,
4903 XEXP (op
, 0), origmode
);
4906 /* A SUBREG resulting from a zero extension may fold to zero if
4907 it extracts higher bits that the ZERO_EXTEND's source bits. */
4908 if (GET_CODE (op
) == ZERO_EXTEND
4909 && bitpos
>= GET_MODE_BITSIZE (GET_MODE (XEXP (op
, 0))))
4910 return CONST0_RTX (outermode
);
4913 /* Simplify (subreg:QI (lshiftrt:SI (sign_extend:SI (x:QI)) C), 0) into
4914 to (ashiftrt:QI (x:QI) C), where C is a suitable small constant and
4915 the outer subreg is effectively a truncation to the original mode. */
4916 if ((GET_CODE (op
) == LSHIFTRT
4917 || GET_CODE (op
) == ASHIFTRT
)
4918 && SCALAR_INT_MODE_P (outermode
)
4919 /* Ensure that OUTERMODE is at least twice as wide as the INNERMODE
4920 to avoid the possibility that an outer LSHIFTRT shifts by more
4921 than the sign extension's sign_bit_copies and introduces zeros
4922 into the high bits of the result. */
4923 && (2 * GET_MODE_BITSIZE (outermode
)) <= GET_MODE_BITSIZE (innermode
)
4924 && GET_CODE (XEXP (op
, 1)) == CONST_INT
4925 && GET_CODE (XEXP (op
, 0)) == SIGN_EXTEND
4926 && GET_MODE (XEXP (XEXP (op
, 0), 0)) == outermode
4927 && INTVAL (XEXP (op
, 1)) < GET_MODE_BITSIZE (outermode
)
4928 && subreg_lsb_1 (outermode
, innermode
, byte
) == 0)
4929 return simplify_gen_binary (ASHIFTRT
, outermode
,
4930 XEXP (XEXP (op
, 0), 0), XEXP (op
, 1));
4932 /* Likewise (subreg:QI (lshiftrt:SI (zero_extend:SI (x:QI)) C), 0) into
4933 to (lshiftrt:QI (x:QI) C), where C is a suitable small constant and
4934 the outer subreg is effectively a truncation to the original mode. */
4935 if ((GET_CODE (op
) == LSHIFTRT
4936 || GET_CODE (op
) == ASHIFTRT
)
4937 && SCALAR_INT_MODE_P (outermode
)
4938 && GET_MODE_BITSIZE (outermode
) < GET_MODE_BITSIZE (innermode
)
4939 && GET_CODE (XEXP (op
, 1)) == CONST_INT
4940 && GET_CODE (XEXP (op
, 0)) == ZERO_EXTEND
4941 && GET_MODE (XEXP (XEXP (op
, 0), 0)) == outermode
4942 && INTVAL (XEXP (op
, 1)) < GET_MODE_BITSIZE (outermode
)
4943 && subreg_lsb_1 (outermode
, innermode
, byte
) == 0)
4944 return simplify_gen_binary (LSHIFTRT
, outermode
,
4945 XEXP (XEXP (op
, 0), 0), XEXP (op
, 1));
4947 /* Likewise (subreg:QI (ashift:SI (zero_extend:SI (x:QI)) C), 0) into
4948 to (ashift:QI (x:QI) C), where C is a suitable small constant and
4949 the outer subreg is effectively a truncation to the original mode. */
4950 if (GET_CODE (op
) == ASHIFT
4951 && SCALAR_INT_MODE_P (outermode
)
4952 && GET_MODE_BITSIZE (outermode
) < GET_MODE_BITSIZE (innermode
)
4953 && GET_CODE (XEXP (op
, 1)) == CONST_INT
4954 && (GET_CODE (XEXP (op
, 0)) == ZERO_EXTEND
4955 || GET_CODE (XEXP (op
, 0)) == SIGN_EXTEND
)
4956 && GET_MODE (XEXP (XEXP (op
, 0), 0)) == outermode
4957 && INTVAL (XEXP (op
, 1)) < GET_MODE_BITSIZE (outermode
)
4958 && subreg_lsb_1 (outermode
, innermode
, byte
) == 0)
4959 return simplify_gen_binary (ASHIFT
, outermode
,
4960 XEXP (XEXP (op
, 0), 0), XEXP (op
, 1));
4965 /* Make a SUBREG operation or equivalent if it folds. */
4968 simplify_gen_subreg (enum machine_mode outermode
, rtx op
,
4969 enum machine_mode innermode
, unsigned int byte
)
4973 newx
= simplify_subreg (outermode
, op
, innermode
, byte
);
4977 if (GET_CODE (op
) == SUBREG
4978 || GET_CODE (op
) == CONCAT
4979 || GET_MODE (op
) == VOIDmode
)
4982 if (validate_subreg (outermode
, innermode
, op
, byte
))
4983 return gen_rtx_SUBREG (outermode
, op
, byte
);
4988 /* Simplify X, an rtx expression.
4990 Return the simplified expression or NULL if no simplifications
4993 This is the preferred entry point into the simplification routines;
4994 however, we still allow passes to call the more specific routines.
4996 Right now GCC has three (yes, three) major bodies of RTL simplification
4997 code that need to be unified.
4999 1. fold_rtx in cse.c. This code uses various CSE specific
5000 information to aid in RTL simplification.
5002 2. simplify_rtx in combine.c. Similar to fold_rtx, except that
5003 it uses combine specific information to aid in RTL
5006 3. The routines in this file.
5009 Long term we want to only have one body of simplification code; to
5010 get to that state I recommend the following steps:
5012 1. Pour over fold_rtx & simplify_rtx and move any simplifications
5013 which are not pass dependent state into these routines.
5015 2. As code is moved by #1, change fold_rtx & simplify_rtx to
5016 use this routine whenever possible.
5018 3. Allow for pass dependent state to be provided to these
5019 routines and add simplifications based on the pass dependent
5020 state. Remove code from cse.c & combine.c that becomes
5023 It will take time, but ultimately the compiler will be easier to
5024 maintain and improve. It's totally silly that when we add a
5025 simplification that it needs to be added to 4 places (3 for RTL
5026 simplification and 1 for tree simplification. */
5029 simplify_rtx (rtx x
)
5031 enum rtx_code code
= GET_CODE (x
);
5032 enum machine_mode mode
= GET_MODE (x
);
5034 switch (GET_RTX_CLASS (code
))
5037 return simplify_unary_operation (code
, mode
,
5038 XEXP (x
, 0), GET_MODE (XEXP (x
, 0)));
5039 case RTX_COMM_ARITH
:
5040 if (swap_commutative_operands_p (XEXP (x
, 0), XEXP (x
, 1)))
5041 return simplify_gen_binary (code
, mode
, XEXP (x
, 1), XEXP (x
, 0));
5043 /* Fall through.... */
5046 return simplify_binary_operation (code
, mode
, XEXP (x
, 0), XEXP (x
, 1));
5049 case RTX_BITFIELD_OPS
:
5050 return simplify_ternary_operation (code
, mode
, GET_MODE (XEXP (x
, 0)),
5051 XEXP (x
, 0), XEXP (x
, 1),
5055 case RTX_COMM_COMPARE
:
5056 return simplify_relational_operation (code
, mode
,
5057 ((GET_MODE (XEXP (x
, 0))
5059 ? GET_MODE (XEXP (x
, 0))
5060 : GET_MODE (XEXP (x
, 1))),
5066 return simplify_subreg (mode
, SUBREG_REG (x
),
5067 GET_MODE (SUBREG_REG (x
)),
5074 /* Convert (lo_sum (high FOO) FOO) to FOO. */
5075 if (GET_CODE (XEXP (x
, 0)) == HIGH
5076 && rtx_equal_p (XEXP (XEXP (x
, 0), 0), XEXP (x
, 1)))