1 /* RTL simplification functions for GNU compiler.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
25 #include "coretypes.h"
31 #include "hard-reg-set.h"
34 #include "insn-config.h"
43 /* Simplification and canonicalization of RTL. */
45 /* Much code operates on (low, high) pairs; the low value is an
46 unsigned wide int, the high value a signed wide int. We
47 occasionally need to sign extend from low to high as if low were a
49 #define HWI_SIGN_EXTEND(low) \
50 ((((HOST_WIDE_INT) low) < 0) ? ((HOST_WIDE_INT) -1) : ((HOST_WIDE_INT) 0))
52 static rtx
neg_const_int (enum machine_mode
, rtx
);
53 static int simplify_plus_minus_op_data_cmp (const void *, const void *);
54 static rtx
simplify_plus_minus (enum rtx_code
, enum machine_mode
, rtx
,
56 static bool associative_constant_p (rtx
);
57 static rtx
simplify_associative_operation (enum rtx_code
, enum machine_mode
,
60 /* Negate a CONST_INT rtx, truncating (because a conversion from a
61 maximally negative number can overflow). */
63 neg_const_int (enum machine_mode mode
, rtx i
)
65 return gen_int_mode (- INTVAL (i
), mode
);
69 /* Make a binary operation by properly ordering the operands and
70 seeing if the expression folds. */
73 simplify_gen_binary (enum rtx_code code
, enum machine_mode mode
, rtx op0
,
78 /* Put complex operands first and constants second if commutative. */
79 if (GET_RTX_CLASS (code
) == 'c'
80 && swap_commutative_operands_p (op0
, op1
))
81 tem
= op0
, op0
= op1
, op1
= tem
;
83 /* If this simplifies, do it. */
84 tem
= simplify_binary_operation (code
, mode
, op0
, op1
);
88 /* Handle addition and subtraction specially. Otherwise, just form
91 if (code
== PLUS
|| code
== MINUS
)
93 tem
= simplify_plus_minus (code
, mode
, op0
, op1
, 1);
98 return gen_rtx_fmt_ee (code
, mode
, op0
, op1
);
101 /* If X is a MEM referencing the constant pool, return the real value.
102 Otherwise return X. */
104 avoid_constant_pool_reference (rtx x
)
107 enum machine_mode cmode
;
109 switch (GET_CODE (x
))
115 /* Handle float extensions of constant pool references. */
117 c
= avoid_constant_pool_reference (tmp
);
118 if (c
!= tmp
&& GET_CODE (c
) == CONST_DOUBLE
)
122 REAL_VALUE_FROM_CONST_DOUBLE (d
, c
);
123 return CONST_DOUBLE_FROM_REAL_VALUE (d
, GET_MODE (x
));
133 /* Call target hook to avoid the effects of -fpic etc.... */
134 addr
= (*targetm
.delegitimize_address
) (addr
);
136 if (GET_CODE (addr
) == LO_SUM
)
137 addr
= XEXP (addr
, 1);
139 if (GET_CODE (addr
) != SYMBOL_REF
140 || ! CONSTANT_POOL_ADDRESS_P (addr
))
143 c
= get_pool_constant (addr
);
144 cmode
= get_pool_mode (addr
);
146 /* If we're accessing the constant in a different mode than it was
147 originally stored, attempt to fix that up via subreg simplifications.
148 If that fails we have no choice but to return the original memory. */
149 if (cmode
!= GET_MODE (x
))
151 c
= simplify_subreg (GET_MODE (x
), c
, cmode
, 0);
158 /* Make a unary operation by first seeing if it folds and otherwise making
159 the specified operation. */
162 simplify_gen_unary (enum rtx_code code
, enum machine_mode mode
, rtx op
,
163 enum machine_mode op_mode
)
167 /* If this simplifies, use it. */
168 if ((tem
= simplify_unary_operation (code
, mode
, op
, op_mode
)) != 0)
171 return gen_rtx_fmt_e (code
, mode
, op
);
174 /* Likewise for ternary operations. */
177 simplify_gen_ternary (enum rtx_code code
, enum machine_mode mode
,
178 enum machine_mode op0_mode
, rtx op0
, rtx op1
, rtx op2
)
182 /* If this simplifies, use it. */
183 if (0 != (tem
= simplify_ternary_operation (code
, mode
, op0_mode
,
187 return gen_rtx_fmt_eee (code
, mode
, op0
, op1
, op2
);
190 /* Likewise, for relational operations.
191 CMP_MODE specifies mode comparison is done in.
195 simplify_gen_relational (enum rtx_code code
, enum machine_mode mode
,
196 enum machine_mode cmp_mode
, rtx op0
, rtx op1
)
200 if (cmp_mode
== VOIDmode
)
201 cmp_mode
= GET_MODE (op0
);
202 if (cmp_mode
== VOIDmode
)
203 cmp_mode
= GET_MODE (op1
);
205 if (cmp_mode
!= VOIDmode
)
207 tem
= simplify_relational_operation (code
, cmp_mode
, op0
, op1
);
211 #ifdef FLOAT_STORE_FLAG_VALUE
212 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
)
215 if (tem
== const0_rtx
)
216 return CONST0_RTX (mode
);
217 if (tem
!= const_true_rtx
)
219 val
= FLOAT_STORE_FLAG_VALUE (mode
);
220 return CONST_DOUBLE_FROM_REAL_VALUE (val
, mode
);
227 /* For the following tests, ensure const0_rtx is op1. */
228 if (swap_commutative_operands_p (op0
, op1
)
229 || (op0
== const0_rtx
&& op1
!= const0_rtx
))
230 tem
= op0
, op0
= op1
, op1
= tem
, code
= swap_condition (code
);
232 /* If op0 is a compare, extract the comparison arguments from it. */
233 if (GET_CODE (op0
) == COMPARE
&& op1
== const0_rtx
)
234 return simplify_gen_relational (code
, mode
, VOIDmode
,
235 XEXP (op0
, 0), XEXP (op0
, 1));
237 /* If op0 is a comparison, extract the comparison arguments form it. */
238 if (GET_RTX_CLASS (GET_CODE (op0
)) == '<' && op1
== const0_rtx
)
242 if (GET_MODE (op0
) == mode
)
244 return simplify_gen_relational (GET_CODE (op0
), mode
, VOIDmode
,
245 XEXP (op0
, 0), XEXP (op0
, 1));
249 enum rtx_code
new = reversed_comparison_code (op0
, NULL_RTX
);
251 return simplify_gen_relational (new, mode
, VOIDmode
,
252 XEXP (op0
, 0), XEXP (op0
, 1));
256 return gen_rtx_fmt_ee (code
, mode
, op0
, op1
);
259 /* Replace all occurrences of OLD in X with NEW and try to simplify the
260 resulting RTX. Return a new RTX which is as simplified as possible. */
263 simplify_replace_rtx (rtx x
, rtx old
, rtx
new)
265 enum rtx_code code
= GET_CODE (x
);
266 enum machine_mode mode
= GET_MODE (x
);
268 /* If X is OLD, return NEW. Otherwise, if this is an expression, try
269 to build a new expression substituting recursively. If we can't do
270 anything, return our input. */
275 switch (GET_RTX_CLASS (code
))
279 enum machine_mode op_mode
= GET_MODE (XEXP (x
, 0));
280 rtx op
= (XEXP (x
, 0) == old
281 ? new : simplify_replace_rtx (XEXP (x
, 0), old
, new));
283 return simplify_gen_unary (code
, mode
, op
, op_mode
);
289 simplify_gen_binary (code
, mode
,
290 simplify_replace_rtx (XEXP (x
, 0), old
, new),
291 simplify_replace_rtx (XEXP (x
, 1), old
, new));
294 enum machine_mode op_mode
= (GET_MODE (XEXP (x
, 0)) != VOIDmode
295 ? GET_MODE (XEXP (x
, 0))
296 : GET_MODE (XEXP (x
, 1)));
297 rtx op0
= simplify_replace_rtx (XEXP (x
, 0), old
, new);
298 rtx op1
= simplify_replace_rtx (XEXP (x
, 1), old
, new);
299 return simplify_gen_relational (code
, mode
, op_mode
, op0
, op1
);
305 enum machine_mode op_mode
= GET_MODE (XEXP (x
, 0));
306 rtx op0
= simplify_replace_rtx (XEXP (x
, 0), old
, new);
309 simplify_gen_ternary (code
, mode
,
314 simplify_replace_rtx (XEXP (x
, 1), old
, new),
315 simplify_replace_rtx (XEXP (x
, 2), old
, new));
319 /* The only case we try to handle is a SUBREG. */
323 exp
= simplify_gen_subreg (GET_MODE (x
),
324 simplify_replace_rtx (SUBREG_REG (x
),
326 GET_MODE (SUBREG_REG (x
)),
335 return replace_equiv_address_nv (x
,
336 simplify_replace_rtx (XEXP (x
, 0),
338 else if (code
== LO_SUM
)
340 rtx op0
= simplify_replace_rtx (XEXP (x
, 0), old
, new);
341 rtx op1
= simplify_replace_rtx (XEXP (x
, 1), old
, new);
343 /* (lo_sum (high x) x) -> x */
344 if (GET_CODE (op0
) == HIGH
&& rtx_equal_p (XEXP (op0
, 0), op1
))
347 return gen_rtx_LO_SUM (mode
, op0
, op1
);
349 else if (code
== REG
)
351 if (REG_P (old
) && REGNO (x
) == REGNO (old
))
363 /* Try to simplify a unary operation CODE whose output mode is to be
364 MODE with input operand OP whose mode was originally OP_MODE.
365 Return zero if no simplification can be made. */
367 simplify_unary_operation (enum rtx_code code
, enum machine_mode mode
,
368 rtx op
, enum machine_mode op_mode
)
370 unsigned int width
= GET_MODE_BITSIZE (mode
);
371 rtx trueop
= avoid_constant_pool_reference (op
);
373 if (code
== VEC_DUPLICATE
)
375 if (!VECTOR_MODE_P (mode
))
377 if (GET_MODE (trueop
) != VOIDmode
378 && !VECTOR_MODE_P (GET_MODE (trueop
))
379 && GET_MODE_INNER (mode
) != GET_MODE (trueop
))
381 if (GET_MODE (trueop
) != VOIDmode
382 && VECTOR_MODE_P (GET_MODE (trueop
))
383 && GET_MODE_INNER (mode
) != GET_MODE_INNER (GET_MODE (trueop
)))
385 if (GET_CODE (trueop
) == CONST_INT
|| GET_CODE (trueop
) == CONST_DOUBLE
386 || GET_CODE (trueop
) == CONST_VECTOR
)
388 int elt_size
= GET_MODE_SIZE (GET_MODE_INNER (mode
));
389 unsigned n_elts
= (GET_MODE_SIZE (mode
) / elt_size
);
390 rtvec v
= rtvec_alloc (n_elts
);
393 if (GET_CODE (trueop
) != CONST_VECTOR
)
394 for (i
= 0; i
< n_elts
; i
++)
395 RTVEC_ELT (v
, i
) = trueop
;
398 enum machine_mode inmode
= GET_MODE (trueop
);
399 int in_elt_size
= GET_MODE_SIZE (GET_MODE_INNER (inmode
));
400 unsigned in_n_elts
= (GET_MODE_SIZE (inmode
) / in_elt_size
);
402 if (in_n_elts
>= n_elts
|| n_elts
% in_n_elts
)
404 for (i
= 0; i
< n_elts
; i
++)
405 RTVEC_ELT (v
, i
) = CONST_VECTOR_ELT (trueop
, i
% in_n_elts
);
407 return gen_rtx_CONST_VECTOR (mode
, v
);
410 else if (GET_CODE (op
) == CONST
)
411 return simplify_unary_operation (code
, mode
, XEXP (op
, 0), op_mode
);
413 if (VECTOR_MODE_P (mode
) && GET_CODE (trueop
) == CONST_VECTOR
)
415 int elt_size
= GET_MODE_SIZE (GET_MODE_INNER (mode
));
416 unsigned n_elts
= (GET_MODE_SIZE (mode
) / elt_size
);
417 enum machine_mode opmode
= GET_MODE (trueop
);
418 int op_elt_size
= GET_MODE_SIZE (GET_MODE_INNER (opmode
));
419 unsigned op_n_elts
= (GET_MODE_SIZE (opmode
) / op_elt_size
);
420 rtvec v
= rtvec_alloc (n_elts
);
423 if (op_n_elts
!= n_elts
)
426 for (i
= 0; i
< n_elts
; i
++)
428 rtx x
= simplify_unary_operation (code
, GET_MODE_INNER (mode
),
429 CONST_VECTOR_ELT (trueop
, i
),
430 GET_MODE_INNER (opmode
));
433 RTVEC_ELT (v
, i
) = x
;
435 return gen_rtx_CONST_VECTOR (mode
, v
);
438 /* The order of these tests is critical so that, for example, we don't
439 check the wrong mode (input vs. output) for a conversion operation,
440 such as FIX. At some point, this should be simplified. */
442 if (code
== FLOAT
&& GET_MODE (trueop
) == VOIDmode
443 && (GET_CODE (trueop
) == CONST_DOUBLE
|| GET_CODE (trueop
) == CONST_INT
))
445 HOST_WIDE_INT hv
, lv
;
448 if (GET_CODE (trueop
) == CONST_INT
)
449 lv
= INTVAL (trueop
), hv
= HWI_SIGN_EXTEND (lv
);
451 lv
= CONST_DOUBLE_LOW (trueop
), hv
= CONST_DOUBLE_HIGH (trueop
);
453 REAL_VALUE_FROM_INT (d
, lv
, hv
, mode
);
454 d
= real_value_truncate (mode
, d
);
455 return CONST_DOUBLE_FROM_REAL_VALUE (d
, mode
);
457 else if (code
== UNSIGNED_FLOAT
&& GET_MODE (trueop
) == VOIDmode
458 && (GET_CODE (trueop
) == CONST_DOUBLE
459 || GET_CODE (trueop
) == CONST_INT
))
461 HOST_WIDE_INT hv
, lv
;
464 if (GET_CODE (trueop
) == CONST_INT
)
465 lv
= INTVAL (trueop
), hv
= HWI_SIGN_EXTEND (lv
);
467 lv
= CONST_DOUBLE_LOW (trueop
), hv
= CONST_DOUBLE_HIGH (trueop
);
469 if (op_mode
== VOIDmode
)
471 /* We don't know how to interpret negative-looking numbers in
472 this case, so don't try to fold those. */
476 else if (GET_MODE_BITSIZE (op_mode
) >= HOST_BITS_PER_WIDE_INT
* 2)
479 hv
= 0, lv
&= GET_MODE_MASK (op_mode
);
481 REAL_VALUE_FROM_UNSIGNED_INT (d
, lv
, hv
, mode
);
482 d
= real_value_truncate (mode
, d
);
483 return CONST_DOUBLE_FROM_REAL_VALUE (d
, mode
);
486 if (GET_CODE (trueop
) == CONST_INT
487 && width
<= HOST_BITS_PER_WIDE_INT
&& width
> 0)
489 HOST_WIDE_INT arg0
= INTVAL (trueop
);
503 val
= (arg0
>= 0 ? arg0
: - arg0
);
507 /* Don't use ffs here. Instead, get low order bit and then its
508 number. If arg0 is zero, this will return 0, as desired. */
509 arg0
&= GET_MODE_MASK (mode
);
510 val
= exact_log2 (arg0
& (- arg0
)) + 1;
514 arg0
&= GET_MODE_MASK (mode
);
515 if (arg0
== 0 && CLZ_DEFINED_VALUE_AT_ZERO (mode
, val
))
518 val
= GET_MODE_BITSIZE (mode
) - floor_log2 (arg0
) - 1;
522 arg0
&= GET_MODE_MASK (mode
);
525 /* Even if the value at zero is undefined, we have to come
526 up with some replacement. Seems good enough. */
527 if (! CTZ_DEFINED_VALUE_AT_ZERO (mode
, val
))
528 val
= GET_MODE_BITSIZE (mode
);
531 val
= exact_log2 (arg0
& -arg0
);
535 arg0
&= GET_MODE_MASK (mode
);
538 val
++, arg0
&= arg0
- 1;
542 arg0
&= GET_MODE_MASK (mode
);
545 val
++, arg0
&= arg0
- 1;
554 /* When zero-extending a CONST_INT, we need to know its
556 if (op_mode
== VOIDmode
)
558 if (GET_MODE_BITSIZE (op_mode
) == HOST_BITS_PER_WIDE_INT
)
560 /* If we were really extending the mode,
561 we would have to distinguish between zero-extension
562 and sign-extension. */
563 if (width
!= GET_MODE_BITSIZE (op_mode
))
567 else if (GET_MODE_BITSIZE (op_mode
) < HOST_BITS_PER_WIDE_INT
)
568 val
= arg0
& ~((HOST_WIDE_INT
) (-1) << GET_MODE_BITSIZE (op_mode
));
574 if (op_mode
== VOIDmode
)
576 if (GET_MODE_BITSIZE (op_mode
) == HOST_BITS_PER_WIDE_INT
)
578 /* If we were really extending the mode,
579 we would have to distinguish between zero-extension
580 and sign-extension. */
581 if (width
!= GET_MODE_BITSIZE (op_mode
))
585 else if (GET_MODE_BITSIZE (op_mode
) < HOST_BITS_PER_WIDE_INT
)
588 = arg0
& ~((HOST_WIDE_INT
) (-1) << GET_MODE_BITSIZE (op_mode
));
590 & ((HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE (op_mode
) - 1)))
591 val
-= (HOST_WIDE_INT
) 1 << GET_MODE_BITSIZE (op_mode
);
608 val
= trunc_int_for_mode (val
, mode
);
610 return GEN_INT (val
);
613 /* We can do some operations on integer CONST_DOUBLEs. Also allow
614 for a DImode operation on a CONST_INT. */
615 else if (GET_MODE (trueop
) == VOIDmode
616 && width
<= HOST_BITS_PER_WIDE_INT
* 2
617 && (GET_CODE (trueop
) == CONST_DOUBLE
618 || GET_CODE (trueop
) == CONST_INT
))
620 unsigned HOST_WIDE_INT l1
, lv
;
621 HOST_WIDE_INT h1
, hv
;
623 if (GET_CODE (trueop
) == CONST_DOUBLE
)
624 l1
= CONST_DOUBLE_LOW (trueop
), h1
= CONST_DOUBLE_HIGH (trueop
);
626 l1
= INTVAL (trueop
), h1
= HWI_SIGN_EXTEND (l1
);
636 neg_double (l1
, h1
, &lv
, &hv
);
641 neg_double (l1
, h1
, &lv
, &hv
);
653 lv
= HOST_BITS_PER_WIDE_INT
+ exact_log2 (h1
& -h1
) + 1;
656 lv
= exact_log2 (l1
& -l1
) + 1;
662 lv
= GET_MODE_BITSIZE (mode
) - floor_log2 (h1
) - 1
663 - HOST_BITS_PER_WIDE_INT
;
665 lv
= GET_MODE_BITSIZE (mode
) - floor_log2 (l1
) - 1;
666 else if (! CLZ_DEFINED_VALUE_AT_ZERO (mode
, lv
))
667 lv
= GET_MODE_BITSIZE (mode
);
673 lv
= exact_log2 (l1
& -l1
);
675 lv
= HOST_BITS_PER_WIDE_INT
+ exact_log2 (h1
& -h1
);
676 else if (! CTZ_DEFINED_VALUE_AT_ZERO (mode
, lv
))
677 lv
= GET_MODE_BITSIZE (mode
);
700 /* This is just a change-of-mode, so do nothing. */
705 if (op_mode
== VOIDmode
)
708 if (GET_MODE_BITSIZE (op_mode
) > HOST_BITS_PER_WIDE_INT
)
712 lv
= l1
& GET_MODE_MASK (op_mode
);
716 if (op_mode
== VOIDmode
717 || GET_MODE_BITSIZE (op_mode
) > HOST_BITS_PER_WIDE_INT
)
721 lv
= l1
& GET_MODE_MASK (op_mode
);
722 if (GET_MODE_BITSIZE (op_mode
) < HOST_BITS_PER_WIDE_INT
723 && (lv
& ((HOST_WIDE_INT
) 1
724 << (GET_MODE_BITSIZE (op_mode
) - 1))) != 0)
725 lv
-= (HOST_WIDE_INT
) 1 << GET_MODE_BITSIZE (op_mode
);
727 hv
= HWI_SIGN_EXTEND (lv
);
738 return immed_double_const (lv
, hv
, mode
);
741 else if (GET_CODE (trueop
) == CONST_DOUBLE
742 && GET_MODE_CLASS (mode
) == MODE_FLOAT
)
744 REAL_VALUE_TYPE d
, t
;
745 REAL_VALUE_FROM_CONST_DOUBLE (d
, trueop
);
750 if (HONOR_SNANS (mode
) && real_isnan (&d
))
752 real_sqrt (&t
, mode
, &d
);
756 d
= REAL_VALUE_ABS (d
);
759 d
= REAL_VALUE_NEGATE (d
);
762 d
= real_value_truncate (mode
, d
);
765 /* All this does is change the mode. */
768 real_arithmetic (&d
, FIX_TRUNC_EXPR
, &d
, NULL
);
774 return CONST_DOUBLE_FROM_REAL_VALUE (d
, mode
);
777 else if (GET_CODE (trueop
) == CONST_DOUBLE
778 && GET_MODE_CLASS (GET_MODE (trueop
)) == MODE_FLOAT
779 && GET_MODE_CLASS (mode
) == MODE_INT
780 && width
<= 2*HOST_BITS_PER_WIDE_INT
&& width
> 0)
782 /* Although the overflow semantics of RTL's FIX and UNSIGNED_FIX
783 operators are intentionally left unspecified (to ease implementation
784 by target backends), for consistency, this routine implements the
785 same semantics for constant folding as used by the middle-end. */
787 HOST_WIDE_INT xh
, xl
, th
, tl
;
788 REAL_VALUE_TYPE x
, t
;
789 REAL_VALUE_FROM_CONST_DOUBLE (x
, trueop
);
793 if (REAL_VALUE_ISNAN (x
))
796 /* Test against the signed upper bound. */
797 if (width
> HOST_BITS_PER_WIDE_INT
)
799 th
= ((unsigned HOST_WIDE_INT
) 1
800 << (width
- HOST_BITS_PER_WIDE_INT
- 1)) - 1;
806 tl
= ((unsigned HOST_WIDE_INT
) 1 << (width
- 1)) - 1;
808 real_from_integer (&t
, VOIDmode
, tl
, th
, 0);
809 if (REAL_VALUES_LESS (t
, x
))
816 /* Test against the signed lower bound. */
817 if (width
> HOST_BITS_PER_WIDE_INT
)
819 th
= (HOST_WIDE_INT
) -1 << (width
- HOST_BITS_PER_WIDE_INT
- 1);
825 tl
= (HOST_WIDE_INT
) -1 << (width
- 1);
827 real_from_integer (&t
, VOIDmode
, tl
, th
, 0);
828 if (REAL_VALUES_LESS (x
, t
))
834 REAL_VALUE_TO_INT (&xl
, &xh
, x
);
838 if (REAL_VALUE_ISNAN (x
) || REAL_VALUE_NEGATIVE (x
))
841 /* Test against the unsigned upper bound. */
842 if (width
== 2*HOST_BITS_PER_WIDE_INT
)
847 else if (width
>= HOST_BITS_PER_WIDE_INT
)
849 th
= ((unsigned HOST_WIDE_INT
) 1
850 << (width
- HOST_BITS_PER_WIDE_INT
)) - 1;
856 tl
= ((unsigned HOST_WIDE_INT
) 1 << width
) - 1;
858 real_from_integer (&t
, VOIDmode
, tl
, th
, 1);
859 if (REAL_VALUES_LESS (t
, x
))
866 REAL_VALUE_TO_INT (&xl
, &xh
, x
);
872 return immed_double_const (xl
, xh
, mode
);
875 /* This was formerly used only for non-IEEE float.
876 eggert@twinsun.com says it is safe for IEEE also. */
879 enum rtx_code reversed
;
882 /* There are some simplifications we can do even if the operands
887 /* (not (not X)) == X. */
888 if (GET_CODE (op
) == NOT
)
891 /* (not (eq X Y)) == (ne X Y), etc. */
892 if (GET_RTX_CLASS (GET_CODE (op
)) == '<'
893 && (mode
== BImode
|| STORE_FLAG_VALUE
== -1)
894 && ((reversed
= reversed_comparison_code (op
, NULL_RTX
))
896 return simplify_gen_relational (reversed
, mode
, VOIDmode
,
897 XEXP (op
, 0), XEXP (op
, 1));
899 /* (not (plus X -1)) can become (neg X). */
900 if (GET_CODE (op
) == PLUS
901 && XEXP (op
, 1) == constm1_rtx
)
902 return simplify_gen_unary (NEG
, mode
, XEXP (op
, 0), mode
);
904 /* Similarly, (not (neg X)) is (plus X -1). */
905 if (GET_CODE (op
) == NEG
)
906 return plus_constant (XEXP (op
, 0), -1);
908 /* (not (xor X C)) for C constant is (xor X D) with D = ~C. */
909 if (GET_CODE (op
) == XOR
910 && GET_CODE (XEXP (op
, 1)) == CONST_INT
911 && (temp
= simplify_unary_operation (NOT
, mode
,
914 return simplify_gen_binary (XOR
, mode
, XEXP (op
, 0), temp
);
917 /* (not (ashift 1 X)) is (rotate ~1 X). We used to do this for
918 operands other than 1, but that is not valid. We could do a
919 similar simplification for (not (lshiftrt C X)) where C is
920 just the sign bit, but this doesn't seem common enough to
922 if (GET_CODE (op
) == ASHIFT
923 && XEXP (op
, 0) == const1_rtx
)
925 temp
= simplify_gen_unary (NOT
, mode
, const1_rtx
, mode
);
926 return simplify_gen_binary (ROTATE
, mode
, temp
, XEXP (op
, 1));
929 /* If STORE_FLAG_VALUE is -1, (not (comparison X Y)) can be done
930 by reversing the comparison code if valid. */
931 if (STORE_FLAG_VALUE
== -1
932 && GET_RTX_CLASS (GET_CODE (op
)) == '<'
933 && (reversed
= reversed_comparison_code (op
, NULL_RTX
))
935 return simplify_gen_relational (reversed
, mode
, VOIDmode
,
936 XEXP (op
, 0), XEXP (op
, 1));
938 /* (not (ashiftrt foo C)) where C is the number of bits in FOO
939 minus 1 is (ge foo (const_int 0)) if STORE_FLAG_VALUE is -1,
940 so we can perform the above simplification. */
942 if (STORE_FLAG_VALUE
== -1
943 && GET_CODE (op
) == ASHIFTRT
944 && GET_CODE (XEXP (op
, 1)) == CONST_INT
945 && INTVAL (XEXP (op
, 1)) == GET_MODE_BITSIZE (mode
) - 1)
946 return simplify_gen_relational (GE
, mode
, VOIDmode
,
947 XEXP (op
, 0), const0_rtx
);
952 /* (neg (neg X)) == X. */
953 if (GET_CODE (op
) == NEG
)
956 /* (neg (plus X 1)) can become (not X). */
957 if (GET_CODE (op
) == PLUS
958 && XEXP (op
, 1) == const1_rtx
)
959 return simplify_gen_unary (NOT
, mode
, XEXP (op
, 0), mode
);
961 /* Similarly, (neg (not X)) is (plus X 1). */
962 if (GET_CODE (op
) == NOT
)
963 return plus_constant (XEXP (op
, 0), 1);
965 /* (neg (minus X Y)) can become (minus Y X). This transformation
966 isn't safe for modes with signed zeros, since if X and Y are
967 both +0, (minus Y X) is the same as (minus X Y). If the
968 rounding mode is towards +infinity (or -infinity) then the two
969 expressions will be rounded differently. */
970 if (GET_CODE (op
) == MINUS
971 && !HONOR_SIGNED_ZEROS (mode
)
972 && !HONOR_SIGN_DEPENDENT_ROUNDING (mode
))
973 return simplify_gen_binary (MINUS
, mode
, XEXP (op
, 1),
976 if (GET_CODE (op
) == PLUS
977 && !HONOR_SIGNED_ZEROS (mode
)
978 && !HONOR_SIGN_DEPENDENT_ROUNDING (mode
))
980 /* (neg (plus A C)) is simplified to (minus -C A). */
981 if (GET_CODE (XEXP (op
, 1)) == CONST_INT
982 || GET_CODE (XEXP (op
, 1)) == CONST_DOUBLE
)
984 temp
= simplify_unary_operation (NEG
, mode
, XEXP (op
, 1),
987 return simplify_gen_binary (MINUS
, mode
, temp
,
991 /* (neg (plus A B)) is canonicalized to (minus (neg A) B). */
992 temp
= simplify_gen_unary (NEG
, mode
, XEXP (op
, 0), mode
);
993 return simplify_gen_binary (MINUS
, mode
, temp
, XEXP (op
, 1));
996 /* (neg (mult A B)) becomes (mult (neg A) B).
997 This works even for floating-point values. */
998 if (GET_CODE (op
) == MULT
999 && !HONOR_SIGN_DEPENDENT_ROUNDING (mode
))
1001 temp
= simplify_gen_unary (NEG
, mode
, XEXP (op
, 0), mode
);
1002 return simplify_gen_binary (MULT
, mode
, temp
, XEXP (op
, 1));
1005 /* NEG commutes with ASHIFT since it is multiplication. Only do
1006 this if we can then eliminate the NEG (e.g., if the operand
1008 if (GET_CODE (op
) == ASHIFT
)
1010 temp
= simplify_unary_operation (NEG
, mode
, XEXP (op
, 0),
1013 return simplify_gen_binary (ASHIFT
, mode
, temp
,
1020 /* (sign_extend (truncate (minus (label_ref L1) (label_ref L2))))
1021 becomes just the MINUS if its mode is MODE. This allows
1022 folding switch statements on machines using casesi (such as
1024 if (GET_CODE (op
) == TRUNCATE
1025 && GET_MODE (XEXP (op
, 0)) == mode
1026 && GET_CODE (XEXP (op
, 0)) == MINUS
1027 && GET_CODE (XEXP (XEXP (op
, 0), 0)) == LABEL_REF
1028 && GET_CODE (XEXP (XEXP (op
, 0), 1)) == LABEL_REF
)
1029 return XEXP (op
, 0);
1031 #if defined(POINTERS_EXTEND_UNSIGNED) && !defined(HAVE_ptr_extend)
1032 if (! POINTERS_EXTEND_UNSIGNED
1033 && mode
== Pmode
&& GET_MODE (op
) == ptr_mode
1035 || (GET_CODE (op
) == SUBREG
1036 && GET_CODE (SUBREG_REG (op
)) == REG
1037 && REG_POINTER (SUBREG_REG (op
))
1038 && GET_MODE (SUBREG_REG (op
)) == Pmode
)))
1039 return convert_memory_address (Pmode
, op
);
1043 #if defined(POINTERS_EXTEND_UNSIGNED) && !defined(HAVE_ptr_extend)
1045 if (POINTERS_EXTEND_UNSIGNED
> 0
1046 && mode
== Pmode
&& GET_MODE (op
) == ptr_mode
1048 || (GET_CODE (op
) == SUBREG
1049 && GET_CODE (SUBREG_REG (op
)) == REG
1050 && REG_POINTER (SUBREG_REG (op
))
1051 && GET_MODE (SUBREG_REG (op
)) == Pmode
)))
1052 return convert_memory_address (Pmode
, op
);
1064 /* Subroutine of simplify_associative_operation. Return true if rtx OP
1065 is a suitable integer or floating point immediate constant. */
1067 associative_constant_p (rtx op
)
1069 if (GET_CODE (op
) == CONST_INT
1070 || GET_CODE (op
) == CONST_DOUBLE
)
1072 op
= avoid_constant_pool_reference (op
);
1073 return GET_CODE (op
) == CONST_INT
1074 || GET_CODE (op
) == CONST_DOUBLE
;
1077 /* Subroutine of simplify_binary_operation to simplify an associative
1078 binary operation CODE with result mode MODE, operating on OP0 and OP1.
1079 Return 0 if no simplification is possible. */
1081 simplify_associative_operation (enum rtx_code code
, enum machine_mode mode
,
1086 /* Simplify (x op c1) op c2 as x op (c1 op c2). */
1087 if (GET_CODE (op0
) == code
1088 && associative_constant_p (op1
)
1089 && associative_constant_p (XEXP (op0
, 1)))
1091 tem
= simplify_binary_operation (code
, mode
, XEXP (op0
, 1), op1
);
1094 return simplify_gen_binary (code
, mode
, XEXP (op0
, 0), tem
);
1097 /* Simplify (x op c1) op (y op c2) as (x op y) op (c1 op c2). */
1098 if (GET_CODE (op0
) == code
1099 && GET_CODE (op1
) == code
1100 && associative_constant_p (XEXP (op0
, 1))
1101 && associative_constant_p (XEXP (op1
, 1)))
1103 rtx c
= simplify_binary_operation (code
, mode
,
1104 XEXP (op0
, 1), XEXP (op1
, 1));
1107 tem
= simplify_gen_binary (code
, mode
, XEXP (op0
, 0), XEXP (op1
, 0));
1108 return simplify_gen_binary (code
, mode
, tem
, c
);
1111 /* Canonicalize (x op c) op y as (x op y) op c. */
1112 if (GET_CODE (op0
) == code
1113 && associative_constant_p (XEXP (op0
, 1)))
1115 tem
= simplify_gen_binary (code
, mode
, XEXP (op0
, 0), op1
);
1116 return simplify_gen_binary (code
, mode
, tem
, XEXP (op0
, 1));
1119 /* Canonicalize x op (y op c) as (x op y) op c. */
1120 if (GET_CODE (op1
) == code
1121 && associative_constant_p (XEXP (op1
, 1)))
1123 tem
= simplify_gen_binary (code
, mode
, op0
, XEXP (op1
, 0));
1124 return simplify_gen_binary (code
, mode
, tem
, XEXP (op1
, 1));
1130 /* Simplify a binary operation CODE with result mode MODE, operating on OP0
1131 and OP1. Return 0 if no simplification is possible.
1133 Don't use this for relational operations such as EQ or LT.
1134 Use simplify_relational_operation instead. */
1136 simplify_binary_operation (enum rtx_code code
, enum machine_mode mode
,
1139 HOST_WIDE_INT arg0
, arg1
, arg0s
, arg1s
;
1141 unsigned int width
= GET_MODE_BITSIZE (mode
);
1143 rtx trueop0
= avoid_constant_pool_reference (op0
);
1144 rtx trueop1
= avoid_constant_pool_reference (op1
);
1146 /* Relational operations don't work here. We must know the mode
1147 of the operands in order to do the comparison correctly.
1148 Assuming a full word can give incorrect results.
1149 Consider comparing 128 with -128 in QImode. */
1151 if (GET_RTX_CLASS (code
) == '<')
1154 /* Make sure the constant is second. */
1155 if (GET_RTX_CLASS (code
) == 'c'
1156 && swap_commutative_operands_p (trueop0
, trueop1
))
1158 tem
= op0
, op0
= op1
, op1
= tem
;
1159 tem
= trueop0
, trueop0
= trueop1
, trueop1
= tem
;
1162 if (VECTOR_MODE_P (mode
)
1163 && GET_CODE (trueop0
) == CONST_VECTOR
1164 && GET_CODE (trueop1
) == CONST_VECTOR
)
1166 int elt_size
= GET_MODE_SIZE (GET_MODE_INNER (mode
));
1167 unsigned n_elts
= (GET_MODE_SIZE (mode
) / elt_size
);
1168 enum machine_mode op0mode
= GET_MODE (trueop0
);
1169 int op0_elt_size
= GET_MODE_SIZE (GET_MODE_INNER (op0mode
));
1170 unsigned op0_n_elts
= (GET_MODE_SIZE (op0mode
) / op0_elt_size
);
1171 enum machine_mode op1mode
= GET_MODE (trueop1
);
1172 int op1_elt_size
= GET_MODE_SIZE (GET_MODE_INNER (op1mode
));
1173 unsigned op1_n_elts
= (GET_MODE_SIZE (op1mode
) / op1_elt_size
);
1174 rtvec v
= rtvec_alloc (n_elts
);
1177 if (op0_n_elts
!= n_elts
|| op1_n_elts
!= n_elts
)
1180 for (i
= 0; i
< n_elts
; i
++)
1182 rtx x
= simplify_binary_operation (code
, GET_MODE_INNER (mode
),
1183 CONST_VECTOR_ELT (trueop0
, i
),
1184 CONST_VECTOR_ELT (trueop1
, i
));
1187 RTVEC_ELT (v
, i
) = x
;
1190 return gen_rtx_CONST_VECTOR (mode
, v
);
1193 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
1194 && GET_CODE (trueop0
) == CONST_DOUBLE
1195 && GET_CODE (trueop1
) == CONST_DOUBLE
1196 && mode
== GET_MODE (op0
) && mode
== GET_MODE (op1
))
1198 REAL_VALUE_TYPE f0
, f1
, value
;
1200 REAL_VALUE_FROM_CONST_DOUBLE (f0
, trueop0
);
1201 REAL_VALUE_FROM_CONST_DOUBLE (f1
, trueop1
);
1202 f0
= real_value_truncate (mode
, f0
);
1203 f1
= real_value_truncate (mode
, f1
);
1205 if (HONOR_SNANS (mode
)
1206 && (REAL_VALUE_ISNAN (f0
) || REAL_VALUE_ISNAN (f1
)))
1210 && REAL_VALUES_EQUAL (f1
, dconst0
)
1211 && (flag_trapping_math
|| ! MODE_HAS_INFINITIES (mode
)))
1214 REAL_ARITHMETIC (value
, rtx_to_tree_code (code
), f0
, f1
);
1216 value
= real_value_truncate (mode
, value
);
1217 return CONST_DOUBLE_FROM_REAL_VALUE (value
, mode
);
1220 /* We can fold some multi-word operations. */
1221 if (GET_MODE_CLASS (mode
) == MODE_INT
1222 && width
== HOST_BITS_PER_WIDE_INT
* 2
1223 && (GET_CODE (trueop0
) == CONST_DOUBLE
1224 || GET_CODE (trueop0
) == CONST_INT
)
1225 && (GET_CODE (trueop1
) == CONST_DOUBLE
1226 || GET_CODE (trueop1
) == CONST_INT
))
1228 unsigned HOST_WIDE_INT l1
, l2
, lv
;
1229 HOST_WIDE_INT h1
, h2
, hv
;
1231 if (GET_CODE (trueop0
) == CONST_DOUBLE
)
1232 l1
= CONST_DOUBLE_LOW (trueop0
), h1
= CONST_DOUBLE_HIGH (trueop0
);
1234 l1
= INTVAL (trueop0
), h1
= HWI_SIGN_EXTEND (l1
);
1236 if (GET_CODE (trueop1
) == CONST_DOUBLE
)
1237 l2
= CONST_DOUBLE_LOW (trueop1
), h2
= CONST_DOUBLE_HIGH (trueop1
);
1239 l2
= INTVAL (trueop1
), h2
= HWI_SIGN_EXTEND (l2
);
1244 /* A - B == A + (-B). */
1245 neg_double (l2
, h2
, &lv
, &hv
);
1248 /* Fall through.... */
1251 add_double (l1
, h1
, l2
, h2
, &lv
, &hv
);
1255 mul_double (l1
, h1
, l2
, h2
, &lv
, &hv
);
1258 case DIV
: case MOD
: case UDIV
: case UMOD
:
1259 /* We'd need to include tree.h to do this and it doesn't seem worth
1264 lv
= l1
& l2
, hv
= h1
& h2
;
1268 lv
= l1
| l2
, hv
= h1
| h2
;
1272 lv
= l1
^ l2
, hv
= h1
^ h2
;
1278 && ((unsigned HOST_WIDE_INT
) l1
1279 < (unsigned HOST_WIDE_INT
) l2
)))
1288 && ((unsigned HOST_WIDE_INT
) l1
1289 > (unsigned HOST_WIDE_INT
) l2
)))
1296 if ((unsigned HOST_WIDE_INT
) h1
< (unsigned HOST_WIDE_INT
) h2
1298 && ((unsigned HOST_WIDE_INT
) l1
1299 < (unsigned HOST_WIDE_INT
) l2
)))
1306 if ((unsigned HOST_WIDE_INT
) h1
> (unsigned HOST_WIDE_INT
) h2
1308 && ((unsigned HOST_WIDE_INT
) l1
1309 > (unsigned HOST_WIDE_INT
) l2
)))
1315 case LSHIFTRT
: case ASHIFTRT
:
1317 case ROTATE
: case ROTATERT
:
1318 #ifdef SHIFT_COUNT_TRUNCATED
1319 if (SHIFT_COUNT_TRUNCATED
)
1320 l2
&= (GET_MODE_BITSIZE (mode
) - 1), h2
= 0;
1323 if (h2
!= 0 || l2
>= GET_MODE_BITSIZE (mode
))
1326 if (code
== LSHIFTRT
|| code
== ASHIFTRT
)
1327 rshift_double (l1
, h1
, l2
, GET_MODE_BITSIZE (mode
), &lv
, &hv
,
1329 else if (code
== ASHIFT
)
1330 lshift_double (l1
, h1
, l2
, GET_MODE_BITSIZE (mode
), &lv
, &hv
, 1);
1331 else if (code
== ROTATE
)
1332 lrotate_double (l1
, h1
, l2
, GET_MODE_BITSIZE (mode
), &lv
, &hv
);
1333 else /* code == ROTATERT */
1334 rrotate_double (l1
, h1
, l2
, GET_MODE_BITSIZE (mode
), &lv
, &hv
);
1341 return immed_double_const (lv
, hv
, mode
);
1344 if (GET_CODE (op0
) != CONST_INT
|| GET_CODE (op1
) != CONST_INT
1345 || width
> HOST_BITS_PER_WIDE_INT
|| width
== 0)
1347 /* Even if we can't compute a constant result,
1348 there are some cases worth simplifying. */
1353 /* Maybe simplify x + 0 to x. The two expressions are equivalent
1354 when x is NaN, infinite, or finite and nonzero. They aren't
1355 when x is -0 and the rounding mode is not towards -infinity,
1356 since (-0) + 0 is then 0. */
1357 if (!HONOR_SIGNED_ZEROS (mode
) && trueop1
== CONST0_RTX (mode
))
1360 /* ((-a) + b) -> (b - a) and similarly for (a + (-b)). These
1361 transformations are safe even for IEEE. */
1362 if (GET_CODE (op0
) == NEG
)
1363 return simplify_gen_binary (MINUS
, mode
, op1
, XEXP (op0
, 0));
1364 else if (GET_CODE (op1
) == NEG
)
1365 return simplify_gen_binary (MINUS
, mode
, op0
, XEXP (op1
, 0));
1367 /* (~a) + 1 -> -a */
1368 if (INTEGRAL_MODE_P (mode
)
1369 && GET_CODE (op0
) == NOT
1370 && trueop1
== const1_rtx
)
1371 return simplify_gen_unary (NEG
, mode
, XEXP (op0
, 0), mode
);
1373 /* Handle both-operands-constant cases. We can only add
1374 CONST_INTs to constants since the sum of relocatable symbols
1375 can't be handled by most assemblers. Don't add CONST_INT
1376 to CONST_INT since overflow won't be computed properly if wider
1377 than HOST_BITS_PER_WIDE_INT. */
1379 if (CONSTANT_P (op0
) && GET_MODE (op0
) != VOIDmode
1380 && GET_CODE (op1
) == CONST_INT
)
1381 return plus_constant (op0
, INTVAL (op1
));
1382 else if (CONSTANT_P (op1
) && GET_MODE (op1
) != VOIDmode
1383 && GET_CODE (op0
) == CONST_INT
)
1384 return plus_constant (op1
, INTVAL (op0
));
1386 /* See if this is something like X * C - X or vice versa or
1387 if the multiplication is written as a shift. If so, we can
1388 distribute and make a new multiply, shift, or maybe just
1389 have X (if C is 2 in the example above). But don't make
1390 real multiply if we didn't have one before. */
1392 if (! FLOAT_MODE_P (mode
))
1394 HOST_WIDE_INT coeff0
= 1, coeff1
= 1;
1395 rtx lhs
= op0
, rhs
= op1
;
1398 if (GET_CODE (lhs
) == NEG
)
1399 coeff0
= -1, lhs
= XEXP (lhs
, 0);
1400 else if (GET_CODE (lhs
) == MULT
1401 && GET_CODE (XEXP (lhs
, 1)) == CONST_INT
)
1403 coeff0
= INTVAL (XEXP (lhs
, 1)), lhs
= XEXP (lhs
, 0);
1406 else if (GET_CODE (lhs
) == ASHIFT
1407 && GET_CODE (XEXP (lhs
, 1)) == CONST_INT
1408 && INTVAL (XEXP (lhs
, 1)) >= 0
1409 && INTVAL (XEXP (lhs
, 1)) < HOST_BITS_PER_WIDE_INT
)
1411 coeff0
= ((HOST_WIDE_INT
) 1) << INTVAL (XEXP (lhs
, 1));
1412 lhs
= XEXP (lhs
, 0);
1415 if (GET_CODE (rhs
) == NEG
)
1416 coeff1
= -1, rhs
= XEXP (rhs
, 0);
1417 else if (GET_CODE (rhs
) == MULT
1418 && GET_CODE (XEXP (rhs
, 1)) == CONST_INT
)
1420 coeff1
= INTVAL (XEXP (rhs
, 1)), rhs
= XEXP (rhs
, 0);
1423 else if (GET_CODE (rhs
) == ASHIFT
1424 && GET_CODE (XEXP (rhs
, 1)) == CONST_INT
1425 && INTVAL (XEXP (rhs
, 1)) >= 0
1426 && INTVAL (XEXP (rhs
, 1)) < HOST_BITS_PER_WIDE_INT
)
1428 coeff1
= ((HOST_WIDE_INT
) 1) << INTVAL (XEXP (rhs
, 1));
1429 rhs
= XEXP (rhs
, 0);
1432 if (rtx_equal_p (lhs
, rhs
))
1434 tem
= simplify_gen_binary (MULT
, mode
, lhs
,
1435 GEN_INT (coeff0
+ coeff1
));
1436 return (GET_CODE (tem
) == MULT
&& ! had_mult
) ? 0 : tem
;
1440 /* If one of the operands is a PLUS or a MINUS, see if we can
1441 simplify this by the associative law.
1442 Don't use the associative law for floating point.
1443 The inaccuracy makes it nonassociative,
1444 and subtle programs can break if operations are associated. */
1446 if (INTEGRAL_MODE_P (mode
)
1447 && (GET_CODE (op0
) == PLUS
|| GET_CODE (op0
) == MINUS
1448 || GET_CODE (op1
) == PLUS
|| GET_CODE (op1
) == MINUS
1449 || (GET_CODE (op0
) == CONST
1450 && GET_CODE (XEXP (op0
, 0)) == PLUS
)
1451 || (GET_CODE (op1
) == CONST
1452 && GET_CODE (XEXP (op1
, 0)) == PLUS
))
1453 && (tem
= simplify_plus_minus (code
, mode
, op0
, op1
, 0)) != 0)
1456 /* Reassociate floating point addition only when the user
1457 specifies unsafe math optimizations. */
1458 if (FLOAT_MODE_P (mode
)
1459 && flag_unsafe_math_optimizations
)
1461 tem
= simplify_associative_operation (code
, mode
, op0
, op1
);
1469 /* Convert (compare FOO (const_int 0)) to FOO unless we aren't
1470 using cc0, in which case we want to leave it as a COMPARE
1471 so we can distinguish it from a register-register-copy.
1473 In IEEE floating point, x-0 is not the same as x. */
1475 if ((TARGET_FLOAT_FORMAT
!= IEEE_FLOAT_FORMAT
1476 || ! FLOAT_MODE_P (mode
) || flag_unsafe_math_optimizations
)
1477 && trueop1
== CONST0_RTX (mode
))
1481 /* Convert (compare (gt (flags) 0) (lt (flags) 0)) to (flags). */
1482 if (((GET_CODE (op0
) == GT
&& GET_CODE (op1
) == LT
)
1483 || (GET_CODE (op0
) == GTU
&& GET_CODE (op1
) == LTU
))
1484 && XEXP (op0
, 1) == const0_rtx
&& XEXP (op1
, 1) == const0_rtx
)
1486 rtx xop00
= XEXP (op0
, 0);
1487 rtx xop10
= XEXP (op1
, 0);
1490 if (GET_CODE (xop00
) == CC0
&& GET_CODE (xop10
) == CC0
)
1492 if (GET_CODE (xop00
) == REG
&& GET_CODE (xop10
) == REG
1493 && GET_MODE (xop00
) == GET_MODE (xop10
)
1494 && REGNO (xop00
) == REGNO (xop10
)
1495 && GET_MODE_CLASS (GET_MODE (xop00
)) == MODE_CC
1496 && GET_MODE_CLASS (GET_MODE (xop10
)) == MODE_CC
)
1503 /* We can't assume x-x is 0 even with non-IEEE floating point,
1504 but since it is zero except in very strange circumstances, we
1505 will treat it as zero with -funsafe-math-optimizations. */
1506 if (rtx_equal_p (trueop0
, trueop1
)
1507 && ! side_effects_p (op0
)
1508 && (! FLOAT_MODE_P (mode
) || flag_unsafe_math_optimizations
))
1509 return CONST0_RTX (mode
);
1511 /* Change subtraction from zero into negation. (0 - x) is the
1512 same as -x when x is NaN, infinite, or finite and nonzero.
1513 But if the mode has signed zeros, and does not round towards
1514 -infinity, then 0 - 0 is 0, not -0. */
1515 if (!HONOR_SIGNED_ZEROS (mode
) && trueop0
== CONST0_RTX (mode
))
1516 return simplify_gen_unary (NEG
, mode
, op1
, mode
);
1518 /* (-1 - a) is ~a. */
1519 if (trueop0
== constm1_rtx
)
1520 return simplify_gen_unary (NOT
, mode
, op1
, mode
);
1522 /* Subtracting 0 has no effect unless the mode has signed zeros
1523 and supports rounding towards -infinity. In such a case,
1525 if (!(HONOR_SIGNED_ZEROS (mode
)
1526 && HONOR_SIGN_DEPENDENT_ROUNDING (mode
))
1527 && trueop1
== CONST0_RTX (mode
))
1530 /* See if this is something like X * C - X or vice versa or
1531 if the multiplication is written as a shift. If so, we can
1532 distribute and make a new multiply, shift, or maybe just
1533 have X (if C is 2 in the example above). But don't make
1534 real multiply if we didn't have one before. */
1536 if (! FLOAT_MODE_P (mode
))
1538 HOST_WIDE_INT coeff0
= 1, coeff1
= 1;
1539 rtx lhs
= op0
, rhs
= op1
;
1542 if (GET_CODE (lhs
) == NEG
)
1543 coeff0
= -1, lhs
= XEXP (lhs
, 0);
1544 else if (GET_CODE (lhs
) == MULT
1545 && GET_CODE (XEXP (lhs
, 1)) == CONST_INT
)
1547 coeff0
= INTVAL (XEXP (lhs
, 1)), lhs
= XEXP (lhs
, 0);
1550 else if (GET_CODE (lhs
) == ASHIFT
1551 && GET_CODE (XEXP (lhs
, 1)) == CONST_INT
1552 && INTVAL (XEXP (lhs
, 1)) >= 0
1553 && INTVAL (XEXP (lhs
, 1)) < HOST_BITS_PER_WIDE_INT
)
1555 coeff0
= ((HOST_WIDE_INT
) 1) << INTVAL (XEXP (lhs
, 1));
1556 lhs
= XEXP (lhs
, 0);
1559 if (GET_CODE (rhs
) == NEG
)
1560 coeff1
= - 1, rhs
= XEXP (rhs
, 0);
1561 else if (GET_CODE (rhs
) == MULT
1562 && GET_CODE (XEXP (rhs
, 1)) == CONST_INT
)
1564 coeff1
= INTVAL (XEXP (rhs
, 1)), rhs
= XEXP (rhs
, 0);
1567 else if (GET_CODE (rhs
) == ASHIFT
1568 && GET_CODE (XEXP (rhs
, 1)) == CONST_INT
1569 && INTVAL (XEXP (rhs
, 1)) >= 0
1570 && INTVAL (XEXP (rhs
, 1)) < HOST_BITS_PER_WIDE_INT
)
1572 coeff1
= ((HOST_WIDE_INT
) 1) << INTVAL (XEXP (rhs
, 1));
1573 rhs
= XEXP (rhs
, 0);
1576 if (rtx_equal_p (lhs
, rhs
))
1578 tem
= simplify_gen_binary (MULT
, mode
, lhs
,
1579 GEN_INT (coeff0
- coeff1
));
1580 return (GET_CODE (tem
) == MULT
&& ! had_mult
) ? 0 : tem
;
1584 /* (a - (-b)) -> (a + b). True even for IEEE. */
1585 if (GET_CODE (op1
) == NEG
)
1586 return simplify_gen_binary (PLUS
, mode
, op0
, XEXP (op1
, 0));
1588 /* (-x - c) may be simplified as (-c - x). */
1589 if (GET_CODE (op0
) == NEG
1590 && (GET_CODE (op1
) == CONST_INT
1591 || GET_CODE (op1
) == CONST_DOUBLE
))
1593 tem
= simplify_unary_operation (NEG
, mode
, op1
, mode
);
1595 return simplify_gen_binary (MINUS
, mode
, tem
, XEXP (op0
, 0));
1598 /* If one of the operands is a PLUS or a MINUS, see if we can
1599 simplify this by the associative law.
1600 Don't use the associative law for floating point.
1601 The inaccuracy makes it nonassociative,
1602 and subtle programs can break if operations are associated. */
1604 if (INTEGRAL_MODE_P (mode
)
1605 && (GET_CODE (op0
) == PLUS
|| GET_CODE (op0
) == MINUS
1606 || GET_CODE (op1
) == PLUS
|| GET_CODE (op1
) == MINUS
1607 || (GET_CODE (op0
) == CONST
1608 && GET_CODE (XEXP (op0
, 0)) == PLUS
)
1609 || (GET_CODE (op1
) == CONST
1610 && GET_CODE (XEXP (op1
, 0)) == PLUS
))
1611 && (tem
= simplify_plus_minus (code
, mode
, op0
, op1
, 0)) != 0)
1614 /* Don't let a relocatable value get a negative coeff. */
1615 if (GET_CODE (op1
) == CONST_INT
&& GET_MODE (op0
) != VOIDmode
)
1616 return simplify_gen_binary (PLUS
, mode
,
1618 neg_const_int (mode
, op1
));
1620 /* (x - (x & y)) -> (x & ~y) */
1621 if (GET_CODE (op1
) == AND
)
1623 if (rtx_equal_p (op0
, XEXP (op1
, 0)))
1625 tem
= simplify_gen_unary (NOT
, mode
, XEXP (op1
, 1),
1626 GET_MODE (XEXP (op1
, 1)));
1627 return simplify_gen_binary (AND
, mode
, op0
, tem
);
1629 if (rtx_equal_p (op0
, XEXP (op1
, 1)))
1631 tem
= simplify_gen_unary (NOT
, mode
, XEXP (op1
, 0),
1632 GET_MODE (XEXP (op1
, 0)));
1633 return simplify_gen_binary (AND
, mode
, op0
, tem
);
1639 if (trueop1
== constm1_rtx
)
1640 return simplify_gen_unary (NEG
, mode
, op0
, mode
);
1642 /* Maybe simplify x * 0 to 0. The reduction is not valid if
1643 x is NaN, since x * 0 is then also NaN. Nor is it valid
1644 when the mode has signed zeros, since multiplying a negative
1645 number by 0 will give -0, not 0. */
1646 if (!HONOR_NANS (mode
)
1647 && !HONOR_SIGNED_ZEROS (mode
)
1648 && trueop1
== CONST0_RTX (mode
)
1649 && ! side_effects_p (op0
))
1652 /* In IEEE floating point, x*1 is not equivalent to x for
1654 if (!HONOR_SNANS (mode
)
1655 && trueop1
== CONST1_RTX (mode
))
1658 /* Convert multiply by constant power of two into shift unless
1659 we are still generating RTL. This test is a kludge. */
1660 if (GET_CODE (trueop1
) == CONST_INT
1661 && (val
= exact_log2 (INTVAL (trueop1
))) >= 0
1662 /* If the mode is larger than the host word size, and the
1663 uppermost bit is set, then this isn't a power of two due
1664 to implicit sign extension. */
1665 && (width
<= HOST_BITS_PER_WIDE_INT
1666 || val
!= HOST_BITS_PER_WIDE_INT
- 1)
1667 && ! rtx_equal_function_value_matters
)
1668 return simplify_gen_binary (ASHIFT
, mode
, op0
, GEN_INT (val
));
1670 /* x*2 is x+x and x*(-1) is -x */
1671 if (GET_CODE (trueop1
) == CONST_DOUBLE
1672 && GET_MODE_CLASS (GET_MODE (trueop1
)) == MODE_FLOAT
1673 && GET_MODE (op0
) == mode
)
1676 REAL_VALUE_FROM_CONST_DOUBLE (d
, trueop1
);
1678 if (REAL_VALUES_EQUAL (d
, dconst2
))
1679 return simplify_gen_binary (PLUS
, mode
, op0
, copy_rtx (op0
));
1681 if (REAL_VALUES_EQUAL (d
, dconstm1
))
1682 return simplify_gen_unary (NEG
, mode
, op0
, mode
);
1685 /* Reassociate multiplication, but for floating point MULTs
1686 only when the user specifies unsafe math optimizations. */
1687 if (! FLOAT_MODE_P (mode
)
1688 || flag_unsafe_math_optimizations
)
1690 tem
= simplify_associative_operation (code
, mode
, op0
, op1
);
1697 if (trueop1
== const0_rtx
)
1699 if (GET_CODE (trueop1
) == CONST_INT
1700 && ((INTVAL (trueop1
) & GET_MODE_MASK (mode
))
1701 == GET_MODE_MASK (mode
)))
1703 if (rtx_equal_p (trueop0
, trueop1
) && ! side_effects_p (op0
))
1705 /* A | (~A) -> -1 */
1706 if (((GET_CODE (op0
) == NOT
&& rtx_equal_p (XEXP (op0
, 0), op1
))
1707 || (GET_CODE (op1
) == NOT
&& rtx_equal_p (XEXP (op1
, 0), op0
)))
1708 && ! side_effects_p (op0
)
1709 && GET_MODE_CLASS (mode
) != MODE_CC
)
1711 tem
= simplify_associative_operation (code
, mode
, op0
, op1
);
1717 if (trueop1
== const0_rtx
)
1719 if (GET_CODE (trueop1
) == CONST_INT
1720 && ((INTVAL (trueop1
) & GET_MODE_MASK (mode
))
1721 == GET_MODE_MASK (mode
)))
1722 return simplify_gen_unary (NOT
, mode
, op0
, mode
);
1723 if (trueop0
== trueop1
&& ! side_effects_p (op0
)
1724 && GET_MODE_CLASS (mode
) != MODE_CC
)
1726 tem
= simplify_associative_operation (code
, mode
, op0
, op1
);
1732 if (trueop1
== const0_rtx
&& ! side_effects_p (op0
))
1734 if (GET_CODE (trueop1
) == CONST_INT
1735 && ((INTVAL (trueop1
) & GET_MODE_MASK (mode
))
1736 == GET_MODE_MASK (mode
)))
1738 if (trueop0
== trueop1
&& ! side_effects_p (op0
)
1739 && GET_MODE_CLASS (mode
) != MODE_CC
)
1742 if (((GET_CODE (op0
) == NOT
&& rtx_equal_p (XEXP (op0
, 0), op1
))
1743 || (GET_CODE (op1
) == NOT
&& rtx_equal_p (XEXP (op1
, 0), op0
)))
1744 && ! side_effects_p (op0
)
1745 && GET_MODE_CLASS (mode
) != MODE_CC
)
1747 tem
= simplify_associative_operation (code
, mode
, op0
, op1
);
1753 /* Convert divide by power of two into shift (divide by 1 handled
1755 if (GET_CODE (trueop1
) == CONST_INT
1756 && (arg1
= exact_log2 (INTVAL (trueop1
))) > 0)
1757 return simplify_gen_binary (LSHIFTRT
, mode
, op0
, GEN_INT (arg1
));
1759 /* Fall through.... */
1762 if (trueop1
== CONST1_RTX (mode
))
1764 /* On some platforms DIV uses narrower mode than its
1766 rtx x
= gen_lowpart_common (mode
, op0
);
1769 else if (mode
!= GET_MODE (op0
) && GET_MODE (op0
) != VOIDmode
)
1770 return gen_lowpart_SUBREG (mode
, op0
);
1775 /* Maybe change 0 / x to 0. This transformation isn't safe for
1776 modes with NaNs, since 0 / 0 will then be NaN rather than 0.
1777 Nor is it safe for modes with signed zeros, since dividing
1778 0 by a negative number gives -0, not 0. */
1779 if (!HONOR_NANS (mode
)
1780 && !HONOR_SIGNED_ZEROS (mode
)
1781 && trueop0
== CONST0_RTX (mode
)
1782 && ! side_effects_p (op1
))
1785 /* Change division by a constant into multiplication. Only do
1786 this with -funsafe-math-optimizations. */
1787 else if (GET_CODE (trueop1
) == CONST_DOUBLE
1788 && GET_MODE_CLASS (GET_MODE (trueop1
)) == MODE_FLOAT
1789 && trueop1
!= CONST0_RTX (mode
)
1790 && flag_unsafe_math_optimizations
)
1793 REAL_VALUE_FROM_CONST_DOUBLE (d
, trueop1
);
1795 if (! REAL_VALUES_EQUAL (d
, dconst0
))
1797 REAL_ARITHMETIC (d
, rtx_to_tree_code (DIV
), dconst1
, d
);
1798 tem
= CONST_DOUBLE_FROM_REAL_VALUE (d
, mode
);
1799 return simplify_gen_binary (MULT
, mode
, op0
, tem
);
1805 /* Handle modulus by power of two (mod with 1 handled below). */
1806 if (GET_CODE (trueop1
) == CONST_INT
1807 && exact_log2 (INTVAL (trueop1
)) > 0)
1808 return simplify_gen_binary (AND
, mode
, op0
,
1809 GEN_INT (INTVAL (op1
) - 1));
1811 /* Fall through.... */
1814 if ((trueop0
== const0_rtx
|| trueop1
== const1_rtx
)
1815 && ! side_effects_p (op0
) && ! side_effects_p (op1
))
1822 /* Rotating ~0 always results in ~0. */
1823 if (GET_CODE (trueop0
) == CONST_INT
&& width
<= HOST_BITS_PER_WIDE_INT
1824 && (unsigned HOST_WIDE_INT
) INTVAL (trueop0
) == GET_MODE_MASK (mode
)
1825 && ! side_effects_p (op1
))
1828 /* Fall through.... */
1832 if (trueop1
== const0_rtx
)
1834 if (trueop0
== const0_rtx
&& ! side_effects_p (op1
))
1839 if (width
<= HOST_BITS_PER_WIDE_INT
1840 && GET_CODE (trueop1
) == CONST_INT
1841 && INTVAL (trueop1
) == (HOST_WIDE_INT
) 1 << (width
-1)
1842 && ! side_effects_p (op0
))
1844 if (rtx_equal_p (trueop0
, trueop1
) && ! side_effects_p (op0
))
1846 tem
= simplify_associative_operation (code
, mode
, op0
, op1
);
1852 if (width
<= HOST_BITS_PER_WIDE_INT
1853 && GET_CODE (trueop1
) == CONST_INT
1854 && ((unsigned HOST_WIDE_INT
) INTVAL (trueop1
)
1855 == (unsigned HOST_WIDE_INT
) GET_MODE_MASK (mode
) >> 1)
1856 && ! side_effects_p (op0
))
1858 if (rtx_equal_p (trueop0
, trueop1
) && ! side_effects_p (op0
))
1860 tem
= simplify_associative_operation (code
, mode
, op0
, op1
);
1866 if (trueop1
== const0_rtx
&& ! side_effects_p (op0
))
1868 if (rtx_equal_p (trueop0
, trueop1
) && ! side_effects_p (op0
))
1870 tem
= simplify_associative_operation (code
, mode
, op0
, op1
);
1876 if (trueop1
== constm1_rtx
&& ! side_effects_p (op0
))
1878 if (rtx_equal_p (trueop0
, trueop1
) && ! side_effects_p (op0
))
1880 tem
= simplify_associative_operation (code
, mode
, op0
, op1
);
1889 /* ??? There are simplifications that can be done. */
1893 if (!VECTOR_MODE_P (mode
))
1895 if (!VECTOR_MODE_P (GET_MODE (trueop0
))
1897 != GET_MODE_INNER (GET_MODE (trueop0
)))
1898 || GET_CODE (trueop1
) != PARALLEL
1899 || XVECLEN (trueop1
, 0) != 1
1900 || GET_CODE (XVECEXP (trueop1
, 0, 0)) != CONST_INT
)
1903 if (GET_CODE (trueop0
) == CONST_VECTOR
)
1904 return CONST_VECTOR_ELT (trueop0
, INTVAL (XVECEXP (trueop1
, 0, 0)));
1908 if (!VECTOR_MODE_P (GET_MODE (trueop0
))
1909 || (GET_MODE_INNER (mode
)
1910 != GET_MODE_INNER (GET_MODE (trueop0
)))
1911 || GET_CODE (trueop1
) != PARALLEL
)
1914 if (GET_CODE (trueop0
) == CONST_VECTOR
)
1916 int elt_size
= GET_MODE_SIZE (GET_MODE_INNER (mode
));
1917 unsigned n_elts
= (GET_MODE_SIZE (mode
) / elt_size
);
1918 rtvec v
= rtvec_alloc (n_elts
);
1921 if (XVECLEN (trueop1
, 0) != (int) n_elts
)
1923 for (i
= 0; i
< n_elts
; i
++)
1925 rtx x
= XVECEXP (trueop1
, 0, i
);
1927 if (GET_CODE (x
) != CONST_INT
)
1929 RTVEC_ELT (v
, i
) = CONST_VECTOR_ELT (trueop0
, INTVAL (x
));
1932 return gen_rtx_CONST_VECTOR (mode
, v
);
1938 enum machine_mode op0_mode
= (GET_MODE (trueop0
) != VOIDmode
1939 ? GET_MODE (trueop0
)
1940 : GET_MODE_INNER (mode
));
1941 enum machine_mode op1_mode
= (GET_MODE (trueop1
) != VOIDmode
1942 ? GET_MODE (trueop1
)
1943 : GET_MODE_INNER (mode
));
1945 if (!VECTOR_MODE_P (mode
)
1946 || (GET_MODE_SIZE (op0_mode
) + GET_MODE_SIZE (op1_mode
)
1947 != GET_MODE_SIZE (mode
)))
1950 if ((VECTOR_MODE_P (op0_mode
)
1951 && (GET_MODE_INNER (mode
)
1952 != GET_MODE_INNER (op0_mode
)))
1953 || (!VECTOR_MODE_P (op0_mode
)
1954 && GET_MODE_INNER (mode
) != op0_mode
))
1957 if ((VECTOR_MODE_P (op1_mode
)
1958 && (GET_MODE_INNER (mode
)
1959 != GET_MODE_INNER (op1_mode
)))
1960 || (!VECTOR_MODE_P (op1_mode
)
1961 && GET_MODE_INNER (mode
) != op1_mode
))
1964 if ((GET_CODE (trueop0
) == CONST_VECTOR
1965 || GET_CODE (trueop0
) == CONST_INT
1966 || GET_CODE (trueop0
) == CONST_DOUBLE
)
1967 && (GET_CODE (trueop1
) == CONST_VECTOR
1968 || GET_CODE (trueop1
) == CONST_INT
1969 || GET_CODE (trueop1
) == CONST_DOUBLE
))
1971 int elt_size
= GET_MODE_SIZE (GET_MODE_INNER (mode
));
1972 unsigned n_elts
= (GET_MODE_SIZE (mode
) / elt_size
);
1973 rtvec v
= rtvec_alloc (n_elts
);
1975 unsigned in_n_elts
= 1;
1977 if (VECTOR_MODE_P (op0_mode
))
1978 in_n_elts
= (GET_MODE_SIZE (op0_mode
) / elt_size
);
1979 for (i
= 0; i
< n_elts
; i
++)
1983 if (!VECTOR_MODE_P (op0_mode
))
1984 RTVEC_ELT (v
, i
) = trueop0
;
1986 RTVEC_ELT (v
, i
) = CONST_VECTOR_ELT (trueop0
, i
);
1990 if (!VECTOR_MODE_P (op1_mode
))
1991 RTVEC_ELT (v
, i
) = trueop1
;
1993 RTVEC_ELT (v
, i
) = CONST_VECTOR_ELT (trueop1
,
1998 return gen_rtx_CONST_VECTOR (mode
, v
);
2010 /* Get the integer argument values in two forms:
2011 zero-extended in ARG0, ARG1 and sign-extended in ARG0S, ARG1S. */
2013 arg0
= INTVAL (trueop0
);
2014 arg1
= INTVAL (trueop1
);
2016 if (width
< HOST_BITS_PER_WIDE_INT
)
2018 arg0
&= ((HOST_WIDE_INT
) 1 << width
) - 1;
2019 arg1
&= ((HOST_WIDE_INT
) 1 << width
) - 1;
2022 if (arg0s
& ((HOST_WIDE_INT
) 1 << (width
- 1)))
2023 arg0s
|= ((HOST_WIDE_INT
) (-1) << width
);
2026 if (arg1s
& ((HOST_WIDE_INT
) 1 << (width
- 1)))
2027 arg1s
|= ((HOST_WIDE_INT
) (-1) << width
);
2035 /* Compute the value of the arithmetic. */
2040 val
= arg0s
+ arg1s
;
2044 val
= arg0s
- arg1s
;
2048 val
= arg0s
* arg1s
;
2053 || (arg0s
== (HOST_WIDE_INT
) 1 << (HOST_BITS_PER_WIDE_INT
- 1)
2056 val
= arg0s
/ arg1s
;
2061 || (arg0s
== (HOST_WIDE_INT
) 1 << (HOST_BITS_PER_WIDE_INT
- 1)
2064 val
= arg0s
% arg1s
;
2069 || (arg0s
== (HOST_WIDE_INT
) 1 << (HOST_BITS_PER_WIDE_INT
- 1)
2072 val
= (unsigned HOST_WIDE_INT
) arg0
/ arg1
;
2077 || (arg0s
== (HOST_WIDE_INT
) 1 << (HOST_BITS_PER_WIDE_INT
- 1)
2080 val
= (unsigned HOST_WIDE_INT
) arg0
% arg1
;
2096 /* If shift count is undefined, don't fold it; let the machine do
2097 what it wants. But truncate it if the machine will do that. */
2101 #ifdef SHIFT_COUNT_TRUNCATED
2102 if (SHIFT_COUNT_TRUNCATED
)
2106 val
= ((unsigned HOST_WIDE_INT
) arg0
) >> arg1
;
2113 #ifdef SHIFT_COUNT_TRUNCATED
2114 if (SHIFT_COUNT_TRUNCATED
)
2118 val
= ((unsigned HOST_WIDE_INT
) arg0
) << arg1
;
2125 #ifdef SHIFT_COUNT_TRUNCATED
2126 if (SHIFT_COUNT_TRUNCATED
)
2130 val
= arg0s
>> arg1
;
2132 /* Bootstrap compiler may not have sign extended the right shift.
2133 Manually extend the sign to insure bootstrap cc matches gcc. */
2134 if (arg0s
< 0 && arg1
> 0)
2135 val
|= ((HOST_WIDE_INT
) -1) << (HOST_BITS_PER_WIDE_INT
- arg1
);
2144 val
= ((((unsigned HOST_WIDE_INT
) arg0
) << (width
- arg1
))
2145 | (((unsigned HOST_WIDE_INT
) arg0
) >> arg1
));
2153 val
= ((((unsigned HOST_WIDE_INT
) arg0
) << arg1
)
2154 | (((unsigned HOST_WIDE_INT
) arg0
) >> (width
- arg1
)));
2158 /* Do nothing here. */
2162 val
= arg0s
<= arg1s
? arg0s
: arg1s
;
2166 val
= ((unsigned HOST_WIDE_INT
) arg0
2167 <= (unsigned HOST_WIDE_INT
) arg1
? arg0
: arg1
);
2171 val
= arg0s
> arg1s
? arg0s
: arg1s
;
2175 val
= ((unsigned HOST_WIDE_INT
) arg0
2176 > (unsigned HOST_WIDE_INT
) arg1
? arg0
: arg1
);
2183 /* ??? There are simplifications that can be done. */
2190 val
= trunc_int_for_mode (val
, mode
);
2192 return GEN_INT (val
);
2195 /* Simplify a PLUS or MINUS, at least one of whose operands may be another
2198 Rather than test for specific case, we do this by a brute-force method
2199 and do all possible simplifications until no more changes occur. Then
2200 we rebuild the operation.
2202 If FORCE is true, then always generate the rtx. This is used to
2203 canonicalize stuff emitted from simplify_gen_binary. Note that this
2204 can still fail if the rtx is too complex. It won't fail just because
2205 the result is not 'simpler' than the input, however. */
2207 struct simplify_plus_minus_op_data
2214 simplify_plus_minus_op_data_cmp (const void *p1
, const void *p2
)
2216 const struct simplify_plus_minus_op_data
*d1
= p1
;
2217 const struct simplify_plus_minus_op_data
*d2
= p2
;
2219 return (commutative_operand_precedence (d2
->op
)
2220 - commutative_operand_precedence (d1
->op
));
2224 simplify_plus_minus (enum rtx_code code
, enum machine_mode mode
, rtx op0
,
2227 struct simplify_plus_minus_op_data ops
[8];
2229 int n_ops
= 2, input_ops
= 2, input_consts
= 0, n_consts
;
2230 int first
, negate
, changed
;
2233 memset (ops
, 0, sizeof ops
);
2235 /* Set up the two operands and then expand them until nothing has been
2236 changed. If we run out of room in our array, give up; this should
2237 almost never happen. */
2242 ops
[1].neg
= (code
== MINUS
);
2248 for (i
= 0; i
< n_ops
; i
++)
2250 rtx this_op
= ops
[i
].op
;
2251 int this_neg
= ops
[i
].neg
;
2252 enum rtx_code this_code
= GET_CODE (this_op
);
2261 ops
[n_ops
].op
= XEXP (this_op
, 1);
2262 ops
[n_ops
].neg
= (this_code
== MINUS
) ^ this_neg
;
2265 ops
[i
].op
= XEXP (this_op
, 0);
2271 ops
[i
].op
= XEXP (this_op
, 0);
2272 ops
[i
].neg
= ! this_neg
;
2278 && GET_CODE (XEXP (this_op
, 0)) == PLUS
2279 && CONSTANT_P (XEXP (XEXP (this_op
, 0), 0))
2280 && CONSTANT_P (XEXP (XEXP (this_op
, 0), 1)))
2282 ops
[i
].op
= XEXP (XEXP (this_op
, 0), 0);
2283 ops
[n_ops
].op
= XEXP (XEXP (this_op
, 0), 1);
2284 ops
[n_ops
].neg
= this_neg
;
2292 /* ~a -> (-a - 1) */
2295 ops
[n_ops
].op
= constm1_rtx
;
2296 ops
[n_ops
++].neg
= this_neg
;
2297 ops
[i
].op
= XEXP (this_op
, 0);
2298 ops
[i
].neg
= !this_neg
;
2306 ops
[i
].op
= neg_const_int (mode
, this_op
);
2319 /* If we only have two operands, we can't do anything. */
2320 if (n_ops
<= 2 && !force
)
2323 /* Count the number of CONSTs we didn't split above. */
2324 for (i
= 0; i
< n_ops
; i
++)
2325 if (GET_CODE (ops
[i
].op
) == CONST
)
2328 /* Now simplify each pair of operands until nothing changes. The first
2329 time through just simplify constants against each other. */
2336 for (i
= 0; i
< n_ops
- 1; i
++)
2337 for (j
= i
+ 1; j
< n_ops
; j
++)
2339 rtx lhs
= ops
[i
].op
, rhs
= ops
[j
].op
;
2340 int lneg
= ops
[i
].neg
, rneg
= ops
[j
].neg
;
2342 if (lhs
!= 0 && rhs
!= 0
2343 && (! first
|| (CONSTANT_P (lhs
) && CONSTANT_P (rhs
))))
2345 enum rtx_code ncode
= PLUS
;
2351 tem
= lhs
, lhs
= rhs
, rhs
= tem
;
2353 else if (swap_commutative_operands_p (lhs
, rhs
))
2354 tem
= lhs
, lhs
= rhs
, rhs
= tem
;
2356 tem
= simplify_binary_operation (ncode
, mode
, lhs
, rhs
);
2358 /* Reject "simplifications" that just wrap the two
2359 arguments in a CONST. Failure to do so can result
2360 in infinite recursion with simplify_binary_operation
2361 when it calls us to simplify CONST operations. */
2363 && ! (GET_CODE (tem
) == CONST
2364 && GET_CODE (XEXP (tem
, 0)) == ncode
2365 && XEXP (XEXP (tem
, 0), 0) == lhs
2366 && XEXP (XEXP (tem
, 0), 1) == rhs
)
2367 /* Don't allow -x + -1 -> ~x simplifications in the
2368 first pass. This allows us the chance to combine
2369 the -1 with other constants. */
2371 && GET_CODE (tem
) == NOT
2372 && XEXP (tem
, 0) == rhs
))
2375 if (GET_CODE (tem
) == NEG
)
2376 tem
= XEXP (tem
, 0), lneg
= !lneg
;
2377 if (GET_CODE (tem
) == CONST_INT
&& lneg
)
2378 tem
= neg_const_int (mode
, tem
), lneg
= 0;
2382 ops
[j
].op
= NULL_RTX
;
2392 /* Pack all the operands to the lower-numbered entries. */
2393 for (i
= 0, j
= 0; j
< n_ops
; j
++)
2398 /* Sort the operations based on swap_commutative_operands_p. */
2399 qsort (ops
, n_ops
, sizeof (*ops
), simplify_plus_minus_op_data_cmp
);
2401 /* Create (minus -C X) instead of (neg (const (plus X C))). */
2403 && GET_CODE (ops
[1].op
) == CONST_INT
2404 && CONSTANT_P (ops
[0].op
)
2406 return gen_rtx_fmt_ee (MINUS
, mode
, ops
[1].op
, ops
[0].op
);
2408 /* We suppressed creation of trivial CONST expressions in the
2409 combination loop to avoid recursion. Create one manually now.
2410 The combination loop should have ensured that there is exactly
2411 one CONST_INT, and the sort will have ensured that it is last
2412 in the array and that any other constant will be next-to-last. */
2415 && GET_CODE (ops
[n_ops
- 1].op
) == CONST_INT
2416 && CONSTANT_P (ops
[n_ops
- 2].op
))
2418 rtx value
= ops
[n_ops
- 1].op
;
2419 if (ops
[n_ops
- 1].neg
^ ops
[n_ops
- 2].neg
)
2420 value
= neg_const_int (mode
, value
);
2421 ops
[n_ops
- 2].op
= plus_constant (ops
[n_ops
- 2].op
, INTVAL (value
));
2425 /* Count the number of CONSTs that we generated. */
2427 for (i
= 0; i
< n_ops
; i
++)
2428 if (GET_CODE (ops
[i
].op
) == CONST
)
2431 /* Give up if we didn't reduce the number of operands we had. Make
2432 sure we count a CONST as two operands. If we have the same
2433 number of operands, but have made more CONSTs than before, this
2434 is also an improvement, so accept it. */
2436 && (n_ops
+ n_consts
> input_ops
2437 || (n_ops
+ n_consts
== input_ops
&& n_consts
<= input_consts
)))
2440 /* Put a non-negated operand first. If there aren't any, make all
2441 operands positive and negate the whole thing later. */
2444 for (i
= 0; i
< n_ops
&& ops
[i
].neg
; i
++)
2448 for (i
= 0; i
< n_ops
; i
++)
2460 /* Now make the result by performing the requested operations. */
2462 for (i
= 1; i
< n_ops
; i
++)
2463 result
= gen_rtx_fmt_ee (ops
[i
].neg
? MINUS
: PLUS
,
2464 mode
, result
, ops
[i
].op
);
2466 return negate
? gen_rtx_NEG (mode
, result
) : result
;
2469 /* Like simplify_binary_operation except used for relational operators.
2470 MODE is the mode of the operands, not that of the result. If MODE
2471 is VOIDmode, both operands must also be VOIDmode and we compare the
2472 operands in "infinite precision".
2474 If no simplification is possible, this function returns zero. Otherwise,
2475 it returns either const_true_rtx or const0_rtx. */
2478 simplify_relational_operation (enum rtx_code code
, enum machine_mode mode
,
2481 int equal
, op0lt
, op0ltu
, op1lt
, op1ltu
;
2486 if (mode
== VOIDmode
2487 && (GET_MODE (op0
) != VOIDmode
2488 || GET_MODE (op1
) != VOIDmode
))
2491 /* If op0 is a compare, extract the comparison arguments from it. */
2492 if (GET_CODE (op0
) == COMPARE
&& op1
== const0_rtx
)
2493 op1
= XEXP (op0
, 1), op0
= XEXP (op0
, 0);
2495 trueop0
= avoid_constant_pool_reference (op0
);
2496 trueop1
= avoid_constant_pool_reference (op1
);
2498 /* We can't simplify MODE_CC values since we don't know what the
2499 actual comparison is. */
2500 if (GET_MODE_CLASS (GET_MODE (op0
)) == MODE_CC
|| CC0_P (op0
))
2503 /* Make sure the constant is second. */
2504 if (swap_commutative_operands_p (trueop0
, trueop1
))
2506 tem
= op0
, op0
= op1
, op1
= tem
;
2507 tem
= trueop0
, trueop0
= trueop1
, trueop1
= tem
;
2508 code
= swap_condition (code
);
2511 /* For integer comparisons of A and B maybe we can simplify A - B and can
2512 then simplify a comparison of that with zero. If A and B are both either
2513 a register or a CONST_INT, this can't help; testing for these cases will
2514 prevent infinite recursion here and speed things up.
2516 If CODE is an unsigned comparison, then we can never do this optimization,
2517 because it gives an incorrect result if the subtraction wraps around zero.
2518 ANSI C defines unsigned operations such that they never overflow, and
2519 thus such cases can not be ignored. */
2521 if (INTEGRAL_MODE_P (mode
) && trueop1
!= const0_rtx
2522 && ! ((GET_CODE (op0
) == REG
|| GET_CODE (trueop0
) == CONST_INT
)
2523 && (GET_CODE (op1
) == REG
|| GET_CODE (trueop1
) == CONST_INT
))
2524 && 0 != (tem
= simplify_binary_operation (MINUS
, mode
, op0
, op1
))
2525 && code
!= GTU
&& code
!= GEU
&& code
!= LTU
&& code
!= LEU
)
2526 return simplify_relational_operation (signed_condition (code
),
2527 mode
, tem
, const0_rtx
);
2529 if (flag_unsafe_math_optimizations
&& code
== ORDERED
)
2530 return const_true_rtx
;
2532 if (flag_unsafe_math_optimizations
&& code
== UNORDERED
)
2535 /* For modes without NaNs, if the two operands are equal, we know the
2536 result except if they have side-effects. */
2537 if (! HONOR_NANS (GET_MODE (trueop0
))
2538 && rtx_equal_p (trueop0
, trueop1
)
2539 && ! side_effects_p (trueop0
))
2540 equal
= 1, op0lt
= 0, op0ltu
= 0, op1lt
= 0, op1ltu
= 0;
2542 /* If the operands are floating-point constants, see if we can fold
2544 else if (GET_CODE (trueop0
) == CONST_DOUBLE
2545 && GET_CODE (trueop1
) == CONST_DOUBLE
2546 && GET_MODE_CLASS (GET_MODE (trueop0
)) == MODE_FLOAT
)
2548 REAL_VALUE_TYPE d0
, d1
;
2550 REAL_VALUE_FROM_CONST_DOUBLE (d0
, trueop0
);
2551 REAL_VALUE_FROM_CONST_DOUBLE (d1
, trueop1
);
2553 /* Comparisons are unordered iff at least one of the values is NaN. */
2554 if (REAL_VALUE_ISNAN (d0
) || REAL_VALUE_ISNAN (d1
))
2564 return const_true_rtx
;
2577 equal
= REAL_VALUES_EQUAL (d0
, d1
);
2578 op0lt
= op0ltu
= REAL_VALUES_LESS (d0
, d1
);
2579 op1lt
= op1ltu
= REAL_VALUES_LESS (d1
, d0
);
2582 /* Otherwise, see if the operands are both integers. */
2583 else if ((GET_MODE_CLASS (mode
) == MODE_INT
|| mode
== VOIDmode
)
2584 && (GET_CODE (trueop0
) == CONST_DOUBLE
2585 || GET_CODE (trueop0
) == CONST_INT
)
2586 && (GET_CODE (trueop1
) == CONST_DOUBLE
2587 || GET_CODE (trueop1
) == CONST_INT
))
2589 int width
= GET_MODE_BITSIZE (mode
);
2590 HOST_WIDE_INT l0s
, h0s
, l1s
, h1s
;
2591 unsigned HOST_WIDE_INT l0u
, h0u
, l1u
, h1u
;
2593 /* Get the two words comprising each integer constant. */
2594 if (GET_CODE (trueop0
) == CONST_DOUBLE
)
2596 l0u
= l0s
= CONST_DOUBLE_LOW (trueop0
);
2597 h0u
= h0s
= CONST_DOUBLE_HIGH (trueop0
);
2601 l0u
= l0s
= INTVAL (trueop0
);
2602 h0u
= h0s
= HWI_SIGN_EXTEND (l0s
);
2605 if (GET_CODE (trueop1
) == CONST_DOUBLE
)
2607 l1u
= l1s
= CONST_DOUBLE_LOW (trueop1
);
2608 h1u
= h1s
= CONST_DOUBLE_HIGH (trueop1
);
2612 l1u
= l1s
= INTVAL (trueop1
);
2613 h1u
= h1s
= HWI_SIGN_EXTEND (l1s
);
2616 /* If WIDTH is nonzero and smaller than HOST_BITS_PER_WIDE_INT,
2617 we have to sign or zero-extend the values. */
2618 if (width
!= 0 && width
< HOST_BITS_PER_WIDE_INT
)
2620 l0u
&= ((HOST_WIDE_INT
) 1 << width
) - 1;
2621 l1u
&= ((HOST_WIDE_INT
) 1 << width
) - 1;
2623 if (l0s
& ((HOST_WIDE_INT
) 1 << (width
- 1)))
2624 l0s
|= ((HOST_WIDE_INT
) (-1) << width
);
2626 if (l1s
& ((HOST_WIDE_INT
) 1 << (width
- 1)))
2627 l1s
|= ((HOST_WIDE_INT
) (-1) << width
);
2629 if (width
!= 0 && width
<= HOST_BITS_PER_WIDE_INT
)
2630 h0u
= h1u
= 0, h0s
= HWI_SIGN_EXTEND (l0s
), h1s
= HWI_SIGN_EXTEND (l1s
);
2632 equal
= (h0u
== h1u
&& l0u
== l1u
);
2633 op0lt
= (h0s
< h1s
|| (h0s
== h1s
&& l0u
< l1u
));
2634 op1lt
= (h1s
< h0s
|| (h1s
== h0s
&& l1u
< l0u
));
2635 op0ltu
= (h0u
< h1u
|| (h0u
== h1u
&& l0u
< l1u
));
2636 op1ltu
= (h1u
< h0u
|| (h1u
== h0u
&& l1u
< l0u
));
2639 /* Otherwise, there are some code-specific tests we can make. */
2645 if (trueop1
== const0_rtx
&& nonzero_address_p (op0
))
2650 if (trueop1
== const0_rtx
&& nonzero_address_p (op0
))
2651 return const_true_rtx
;
2655 /* Unsigned values are never negative. */
2656 if (trueop1
== const0_rtx
)
2657 return const_true_rtx
;
2661 if (trueop1
== const0_rtx
)
2666 /* Unsigned values are never greater than the largest
2668 if (GET_CODE (trueop1
) == CONST_INT
2669 && (unsigned HOST_WIDE_INT
) INTVAL (trueop1
) == GET_MODE_MASK (mode
)
2670 && INTEGRAL_MODE_P (mode
))
2671 return const_true_rtx
;
2675 if (GET_CODE (trueop1
) == CONST_INT
2676 && (unsigned HOST_WIDE_INT
) INTVAL (trueop1
) == GET_MODE_MASK (mode
)
2677 && INTEGRAL_MODE_P (mode
))
2682 /* Optimize abs(x) < 0.0. */
2683 if (trueop1
== CONST0_RTX (mode
) && !HONOR_SNANS (mode
))
2685 tem
= GET_CODE (trueop0
) == FLOAT_EXTEND
? XEXP (trueop0
, 0)
2687 if (GET_CODE (tem
) == ABS
)
2693 /* Optimize abs(x) >= 0.0. */
2694 if (trueop1
== CONST0_RTX (mode
) && !HONOR_NANS (mode
))
2696 tem
= GET_CODE (trueop0
) == FLOAT_EXTEND
? XEXP (trueop0
, 0)
2698 if (GET_CODE (tem
) == ABS
)
2699 return const_true_rtx
;
2704 /* Optimize ! (abs(x) < 0.0). */
2705 if (trueop1
== CONST0_RTX (mode
))
2707 tem
= GET_CODE (trueop0
) == FLOAT_EXTEND
? XEXP (trueop0
, 0)
2709 if (GET_CODE (tem
) == ABS
)
2710 return const_true_rtx
;
2721 /* If we reach here, EQUAL, OP0LT, OP0LTU, OP1LT, and OP1LTU are set
2727 return equal
? const_true_rtx
: const0_rtx
;
2730 return ! equal
? const_true_rtx
: const0_rtx
;
2733 return op0lt
? const_true_rtx
: const0_rtx
;
2736 return op1lt
? const_true_rtx
: const0_rtx
;
2738 return op0ltu
? const_true_rtx
: const0_rtx
;
2740 return op1ltu
? const_true_rtx
: const0_rtx
;
2743 return equal
|| op0lt
? const_true_rtx
: const0_rtx
;
2746 return equal
|| op1lt
? const_true_rtx
: const0_rtx
;
2748 return equal
|| op0ltu
? const_true_rtx
: const0_rtx
;
2750 return equal
|| op1ltu
? const_true_rtx
: const0_rtx
;
2752 return const_true_rtx
;
2760 /* Simplify CODE, an operation with result mode MODE and three operands,
2761 OP0, OP1, and OP2. OP0_MODE was the mode of OP0 before it became
2762 a constant. Return 0 if no simplifications is possible. */
2765 simplify_ternary_operation (enum rtx_code code
, enum machine_mode mode
,
2766 enum machine_mode op0_mode
, rtx op0
, rtx op1
,
2769 unsigned int width
= GET_MODE_BITSIZE (mode
);
2771 /* VOIDmode means "infinite" precision. */
2773 width
= HOST_BITS_PER_WIDE_INT
;
2779 if (GET_CODE (op0
) == CONST_INT
2780 && GET_CODE (op1
) == CONST_INT
2781 && GET_CODE (op2
) == CONST_INT
2782 && ((unsigned) INTVAL (op1
) + (unsigned) INTVAL (op2
) <= width
)
2783 && width
<= (unsigned) HOST_BITS_PER_WIDE_INT
)
2785 /* Extracting a bit-field from a constant */
2786 HOST_WIDE_INT val
= INTVAL (op0
);
2788 if (BITS_BIG_ENDIAN
)
2789 val
>>= (GET_MODE_BITSIZE (op0_mode
)
2790 - INTVAL (op2
) - INTVAL (op1
));
2792 val
>>= INTVAL (op2
);
2794 if (HOST_BITS_PER_WIDE_INT
!= INTVAL (op1
))
2796 /* First zero-extend. */
2797 val
&= ((HOST_WIDE_INT
) 1 << INTVAL (op1
)) - 1;
2798 /* If desired, propagate sign bit. */
2799 if (code
== SIGN_EXTRACT
2800 && (val
& ((HOST_WIDE_INT
) 1 << (INTVAL (op1
) - 1))))
2801 val
|= ~ (((HOST_WIDE_INT
) 1 << INTVAL (op1
)) - 1);
2804 /* Clear the bits that don't belong in our mode,
2805 unless they and our sign bit are all one.
2806 So we get either a reasonable negative value or a reasonable
2807 unsigned value for this mode. */
2808 if (width
< HOST_BITS_PER_WIDE_INT
2809 && ((val
& ((HOST_WIDE_INT
) (-1) << (width
- 1)))
2810 != ((HOST_WIDE_INT
) (-1) << (width
- 1))))
2811 val
&= ((HOST_WIDE_INT
) 1 << width
) - 1;
2813 return GEN_INT (val
);
2818 if (GET_CODE (op0
) == CONST_INT
)
2819 return op0
!= const0_rtx
? op1
: op2
;
2821 /* Convert a == b ? b : a to "a". */
2822 if (GET_CODE (op0
) == NE
&& ! side_effects_p (op0
)
2823 && !HONOR_NANS (mode
)
2824 && rtx_equal_p (XEXP (op0
, 0), op1
)
2825 && rtx_equal_p (XEXP (op0
, 1), op2
))
2827 else if (GET_CODE (op0
) == EQ
&& ! side_effects_p (op0
)
2828 && !HONOR_NANS (mode
)
2829 && rtx_equal_p (XEXP (op0
, 1), op1
)
2830 && rtx_equal_p (XEXP (op0
, 0), op2
))
2832 else if (GET_RTX_CLASS (GET_CODE (op0
)) == '<' && ! side_effects_p (op0
))
2834 enum machine_mode cmp_mode
= (GET_MODE (XEXP (op0
, 0)) == VOIDmode
2835 ? GET_MODE (XEXP (op0
, 1))
2836 : GET_MODE (XEXP (op0
, 0)));
2838 if (cmp_mode
== VOIDmode
)
2839 cmp_mode
= op0_mode
;
2840 temp
= simplify_relational_operation (GET_CODE (op0
), cmp_mode
,
2841 XEXP (op0
, 0), XEXP (op0
, 1));
2843 /* See if any simplifications were possible. */
2844 if (temp
== const0_rtx
)
2846 else if (temp
== const_true_rtx
)
2851 /* Look for happy constants in op1 and op2. */
2852 if (GET_CODE (op1
) == CONST_INT
&& GET_CODE (op2
) == CONST_INT
)
2854 HOST_WIDE_INT t
= INTVAL (op1
);
2855 HOST_WIDE_INT f
= INTVAL (op2
);
2857 if (t
== STORE_FLAG_VALUE
&& f
== 0)
2858 code
= GET_CODE (op0
);
2859 else if (t
== 0 && f
== STORE_FLAG_VALUE
)
2862 tmp
= reversed_comparison_code (op0
, NULL_RTX
);
2870 return gen_rtx_fmt_ee (code
, mode
, XEXP (op0
, 0), XEXP (op0
, 1));
2875 if (GET_MODE (op0
) != mode
2876 || GET_MODE (op1
) != mode
2877 || !VECTOR_MODE_P (mode
))
2879 op2
= avoid_constant_pool_reference (op2
);
2880 if (GET_CODE (op2
) == CONST_INT
)
2882 int elt_size
= GET_MODE_SIZE (GET_MODE_INNER (mode
));
2883 unsigned n_elts
= (GET_MODE_SIZE (mode
) / elt_size
);
2884 int mask
= (1 << n_elts
) - 1;
2886 if (!(INTVAL (op2
) & mask
))
2888 if ((INTVAL (op2
) & mask
) == mask
)
2891 op0
= avoid_constant_pool_reference (op0
);
2892 op1
= avoid_constant_pool_reference (op1
);
2893 if (GET_CODE (op0
) == CONST_VECTOR
2894 && GET_CODE (op1
) == CONST_VECTOR
)
2896 rtvec v
= rtvec_alloc (n_elts
);
2899 for (i
= 0; i
< n_elts
; i
++)
2900 RTVEC_ELT (v
, i
) = (INTVAL (op2
) & (1 << i
)
2901 ? CONST_VECTOR_ELT (op0
, i
)
2902 : CONST_VECTOR_ELT (op1
, i
));
2903 return gen_rtx_CONST_VECTOR (mode
, v
);
2915 /* Simplify SUBREG:OUTERMODE(OP:INNERMODE, BYTE)
2916 Return 0 if no simplifications is possible. */
2918 simplify_subreg (enum machine_mode outermode
, rtx op
,
2919 enum machine_mode innermode
, unsigned int byte
)
2921 /* Little bit of sanity checking. */
2922 if (innermode
== VOIDmode
|| outermode
== VOIDmode
2923 || innermode
== BLKmode
|| outermode
== BLKmode
)
2926 if (GET_MODE (op
) != innermode
2927 && GET_MODE (op
) != VOIDmode
)
2930 if (byte
% GET_MODE_SIZE (outermode
)
2931 || byte
>= GET_MODE_SIZE (innermode
))
2934 if (outermode
== innermode
&& !byte
)
2937 /* Simplify subregs of vector constants. */
2938 if (GET_CODE (op
) == CONST_VECTOR
)
2940 int elt_size
= GET_MODE_SIZE (GET_MODE_INNER (innermode
));
2941 const unsigned int offset
= byte
/ elt_size
;
2944 if (GET_MODE_INNER (innermode
) == outermode
)
2946 elt
= CONST_VECTOR_ELT (op
, offset
);
2948 /* ?? We probably don't need this copy_rtx because constants
2949 can be shared. ?? */
2951 return copy_rtx (elt
);
2953 else if (GET_MODE_INNER (innermode
) == GET_MODE_INNER (outermode
)
2954 && GET_MODE_SIZE (innermode
) > GET_MODE_SIZE (outermode
))
2956 return (gen_rtx_CONST_VECTOR
2958 gen_rtvec_v (GET_MODE_NUNITS (outermode
),
2959 &CONST_VECTOR_ELT (op
, offset
))));
2961 else if (GET_MODE_CLASS (outermode
) == MODE_INT
2962 && (GET_MODE_SIZE (outermode
) % elt_size
== 0))
2964 /* This happens when the target register size is smaller then
2965 the vector mode, and we synthesize operations with vectors
2966 of elements that are smaller than the register size. */
2967 HOST_WIDE_INT sum
= 0, high
= 0;
2968 unsigned n_elts
= (GET_MODE_SIZE (outermode
) / elt_size
);
2969 unsigned i
= BYTES_BIG_ENDIAN
? offset
: offset
+ n_elts
- 1;
2970 unsigned step
= BYTES_BIG_ENDIAN
? 1 : -1;
2971 int shift
= BITS_PER_UNIT
* elt_size
;
2972 unsigned HOST_WIDE_INT unit_mask
;
2974 unit_mask
= (unsigned HOST_WIDE_INT
) -1
2975 >> (sizeof (HOST_WIDE_INT
) * BITS_PER_UNIT
- shift
);
2977 for (; n_elts
--; i
+= step
)
2979 elt
= CONST_VECTOR_ELT (op
, i
);
2980 if (GET_CODE (elt
) == CONST_DOUBLE
2981 && GET_MODE_CLASS (GET_MODE (elt
)) == MODE_FLOAT
)
2983 elt
= gen_lowpart_common (int_mode_for_mode (GET_MODE (elt
)),
2988 if (GET_CODE (elt
) != CONST_INT
)
2990 /* Avoid overflow. */
2991 if (high
>> (HOST_BITS_PER_WIDE_INT
- shift
))
2993 high
= high
<< shift
| sum
>> (HOST_BITS_PER_WIDE_INT
- shift
);
2994 sum
= (sum
<< shift
) + (INTVAL (elt
) & unit_mask
);
2996 if (GET_MODE_BITSIZE (outermode
) <= HOST_BITS_PER_WIDE_INT
)
2997 return GEN_INT (trunc_int_for_mode (sum
, outermode
));
2998 else if (GET_MODE_BITSIZE (outermode
) == 2* HOST_BITS_PER_WIDE_INT
)
2999 return immed_double_const (sum
, high
, outermode
);
3003 else if (GET_MODE_CLASS (outermode
) == MODE_INT
3004 && (elt_size
% GET_MODE_SIZE (outermode
) == 0))
3006 enum machine_mode new_mode
3007 = int_mode_for_mode (GET_MODE_INNER (innermode
));
3008 int subbyte
= byte
% elt_size
;
3010 op
= simplify_subreg (new_mode
, op
, innermode
, byte
- subbyte
);
3013 return simplify_subreg (outermode
, op
, new_mode
, subbyte
);
3015 else if (GET_MODE_CLASS (outermode
) == MODE_INT
)
3016 /* This shouldn't happen, but let's not do anything stupid. */
3020 /* Attempt to simplify constant to non-SUBREG expression. */
3021 if (CONSTANT_P (op
))
3024 unsigned HOST_WIDE_INT val
= 0;
3026 if (VECTOR_MODE_P (outermode
))
3028 /* Construct a CONST_VECTOR from individual subregs. */
3029 enum machine_mode submode
= GET_MODE_INNER (outermode
);
3030 int subsize
= GET_MODE_UNIT_SIZE (outermode
);
3031 int i
, elts
= GET_MODE_NUNITS (outermode
);
3032 rtvec v
= rtvec_alloc (elts
);
3035 for (i
= 0; i
< elts
; i
++, byte
+= subsize
)
3037 /* This might fail, e.g. if taking a subreg from a SYMBOL_REF. */
3038 /* ??? It would be nice if we could actually make such subregs
3039 on targets that allow such relocations. */
3040 if (byte
>= GET_MODE_SIZE (innermode
))
3041 elt
= CONST0_RTX (submode
);
3043 elt
= simplify_subreg (submode
, op
, innermode
, byte
);
3046 RTVEC_ELT (v
, i
) = elt
;
3048 return gen_rtx_CONST_VECTOR (outermode
, v
);
3051 /* ??? This code is partly redundant with code below, but can handle
3052 the subregs of floats and similar corner cases.
3053 Later it we should move all simplification code here and rewrite
3054 GEN_LOWPART_IF_POSSIBLE, GEN_HIGHPART, OPERAND_SUBWORD and friends
3055 using SIMPLIFY_SUBREG. */
3056 if (subreg_lowpart_offset (outermode
, innermode
) == byte
3057 && GET_CODE (op
) != CONST_VECTOR
)
3059 rtx
new = gen_lowpart_if_possible (outermode
, op
);
3064 /* Similar comment as above apply here. */
3065 if (GET_MODE_SIZE (outermode
) == UNITS_PER_WORD
3066 && GET_MODE_SIZE (innermode
) > UNITS_PER_WORD
3067 && GET_MODE_CLASS (outermode
) == MODE_INT
)
3069 rtx
new = constant_subword (op
,
3070 (byte
/ UNITS_PER_WORD
),
3076 if (GET_MODE_CLASS (outermode
) != MODE_INT
3077 && GET_MODE_CLASS (outermode
) != MODE_CC
)
3079 enum machine_mode new_mode
= int_mode_for_mode (outermode
);
3081 if (new_mode
!= innermode
|| byte
!= 0)
3083 op
= simplify_subreg (new_mode
, op
, innermode
, byte
);
3086 return simplify_subreg (outermode
, op
, new_mode
, 0);
3090 offset
= byte
* BITS_PER_UNIT
;
3091 switch (GET_CODE (op
))
3094 if (GET_MODE (op
) != VOIDmode
)
3097 /* We can't handle this case yet. */
3098 if (GET_MODE_BITSIZE (outermode
) >= HOST_BITS_PER_WIDE_INT
)
3101 part
= offset
>= HOST_BITS_PER_WIDE_INT
;
3102 if ((BITS_PER_WORD
> HOST_BITS_PER_WIDE_INT
3103 && BYTES_BIG_ENDIAN
)
3104 || (BITS_PER_WORD
<= HOST_BITS_PER_WIDE_INT
3105 && WORDS_BIG_ENDIAN
))
3107 val
= part
? CONST_DOUBLE_HIGH (op
) : CONST_DOUBLE_LOW (op
);
3108 offset
%= HOST_BITS_PER_WIDE_INT
;
3110 /* We've already picked the word we want from a double, so
3111 pretend this is actually an integer. */
3112 innermode
= mode_for_size (HOST_BITS_PER_WIDE_INT
, MODE_INT
, 0);
3116 if (GET_CODE (op
) == CONST_INT
)
3119 /* We don't handle synthesizing of non-integral constants yet. */
3120 if (GET_MODE_CLASS (outermode
) != MODE_INT
)
3123 if (BYTES_BIG_ENDIAN
|| WORDS_BIG_ENDIAN
)
3125 if (WORDS_BIG_ENDIAN
)
3126 offset
= (GET_MODE_BITSIZE (innermode
)
3127 - GET_MODE_BITSIZE (outermode
) - offset
);
3128 if (BYTES_BIG_ENDIAN
!= WORDS_BIG_ENDIAN
3129 && GET_MODE_SIZE (outermode
) < UNITS_PER_WORD
)
3130 offset
= (offset
+ BITS_PER_WORD
- GET_MODE_BITSIZE (outermode
)
3131 - 2 * (offset
% BITS_PER_WORD
));
3134 if (offset
>= HOST_BITS_PER_WIDE_INT
)
3135 return ((HOST_WIDE_INT
) val
< 0) ? constm1_rtx
: const0_rtx
;
3139 if (GET_MODE_BITSIZE (outermode
) < HOST_BITS_PER_WIDE_INT
)
3140 val
= trunc_int_for_mode (val
, outermode
);
3141 return GEN_INT (val
);
3148 /* Changing mode twice with SUBREG => just change it once,
3149 or not at all if changing back op starting mode. */
3150 if (GET_CODE (op
) == SUBREG
)
3152 enum machine_mode innermostmode
= GET_MODE (SUBREG_REG (op
));
3153 int final_offset
= byte
+ SUBREG_BYTE (op
);
3156 if (outermode
== innermostmode
3157 && byte
== 0 && SUBREG_BYTE (op
) == 0)
3158 return SUBREG_REG (op
);
3160 /* The SUBREG_BYTE represents offset, as if the value were stored
3161 in memory. Irritating exception is paradoxical subreg, where
3162 we define SUBREG_BYTE to be 0. On big endian machines, this
3163 value should be negative. For a moment, undo this exception. */
3164 if (byte
== 0 && GET_MODE_SIZE (innermode
) < GET_MODE_SIZE (outermode
))
3166 int difference
= (GET_MODE_SIZE (innermode
) - GET_MODE_SIZE (outermode
));
3167 if (WORDS_BIG_ENDIAN
)
3168 final_offset
+= (difference
/ UNITS_PER_WORD
) * UNITS_PER_WORD
;
3169 if (BYTES_BIG_ENDIAN
)
3170 final_offset
+= difference
% UNITS_PER_WORD
;
3172 if (SUBREG_BYTE (op
) == 0
3173 && GET_MODE_SIZE (innermostmode
) < GET_MODE_SIZE (innermode
))
3175 int difference
= (GET_MODE_SIZE (innermostmode
) - GET_MODE_SIZE (innermode
));
3176 if (WORDS_BIG_ENDIAN
)
3177 final_offset
+= (difference
/ UNITS_PER_WORD
) * UNITS_PER_WORD
;
3178 if (BYTES_BIG_ENDIAN
)
3179 final_offset
+= difference
% UNITS_PER_WORD
;
3182 /* See whether resulting subreg will be paradoxical. */
3183 if (GET_MODE_SIZE (innermostmode
) > GET_MODE_SIZE (outermode
))
3185 /* In nonparadoxical subregs we can't handle negative offsets. */
3186 if (final_offset
< 0)
3188 /* Bail out in case resulting subreg would be incorrect. */
3189 if (final_offset
% GET_MODE_SIZE (outermode
)
3190 || (unsigned) final_offset
>= GET_MODE_SIZE (innermostmode
))
3196 int difference
= (GET_MODE_SIZE (innermostmode
) - GET_MODE_SIZE (outermode
));
3198 /* In paradoxical subreg, see if we are still looking on lower part.
3199 If so, our SUBREG_BYTE will be 0. */
3200 if (WORDS_BIG_ENDIAN
)
3201 offset
+= (difference
/ UNITS_PER_WORD
) * UNITS_PER_WORD
;
3202 if (BYTES_BIG_ENDIAN
)
3203 offset
+= difference
% UNITS_PER_WORD
;
3204 if (offset
== final_offset
)
3210 /* Recurse for further possible simplifications. */
3211 new = simplify_subreg (outermode
, SUBREG_REG (op
),
3212 GET_MODE (SUBREG_REG (op
)),
3216 return gen_rtx_SUBREG (outermode
, SUBREG_REG (op
), final_offset
);
3219 /* SUBREG of a hard register => just change the register number
3220 and/or mode. If the hard register is not valid in that mode,
3221 suppress this simplification. If the hard register is the stack,
3222 frame, or argument pointer, leave this as a SUBREG. */
3225 && (! REG_FUNCTION_VALUE_P (op
)
3226 || ! rtx_equal_function_value_matters
)
3227 && REGNO (op
) < FIRST_PSEUDO_REGISTER
3228 #ifdef CANNOT_CHANGE_MODE_CLASS
3229 && ! (REG_CANNOT_CHANGE_MODE_P (REGNO (op
), innermode
, outermode
)
3230 && GET_MODE_CLASS (innermode
) != MODE_COMPLEX_INT
3231 && GET_MODE_CLASS (innermode
) != MODE_COMPLEX_FLOAT
)
3233 && ((reload_completed
&& !frame_pointer_needed
)
3234 || (REGNO (op
) != FRAME_POINTER_REGNUM
3235 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3236 && REGNO (op
) != HARD_FRAME_POINTER_REGNUM
3239 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
3240 && REGNO (op
) != ARG_POINTER_REGNUM
3242 && REGNO (op
) != STACK_POINTER_REGNUM
3243 && subreg_offset_representable_p (REGNO (op
), innermode
,
3246 rtx tem
= gen_rtx_SUBREG (outermode
, op
, byte
);
3247 int final_regno
= subreg_hard_regno (tem
, 0);
3249 /* ??? We do allow it if the current REG is not valid for
3250 its mode. This is a kludge to work around how float/complex
3251 arguments are passed on 32-bit SPARC and should be fixed. */
3252 if (HARD_REGNO_MODE_OK (final_regno
, outermode
)
3253 || ! HARD_REGNO_MODE_OK (REGNO (op
), innermode
))
3255 rtx x
= gen_rtx_REG_offset (op
, outermode
, final_regno
, byte
);
3257 /* Propagate original regno. We don't have any way to specify
3258 the offset inside original regno, so do so only for lowpart.
3259 The information is used only by alias analysis that can not
3260 grog partial register anyway. */
3262 if (subreg_lowpart_offset (outermode
, innermode
) == byte
)
3263 ORIGINAL_REGNO (x
) = ORIGINAL_REGNO (op
);
3268 /* If we have a SUBREG of a register that we are replacing and we are
3269 replacing it with a MEM, make a new MEM and try replacing the
3270 SUBREG with it. Don't do this if the MEM has a mode-dependent address
3271 or if we would be widening it. */
3273 if (GET_CODE (op
) == MEM
3274 && ! mode_dependent_address_p (XEXP (op
, 0))
3275 /* Allow splitting of volatile memory references in case we don't
3276 have instruction to move the whole thing. */
3277 && (! MEM_VOLATILE_P (op
)
3278 || ! have_insn_for (SET
, innermode
))
3279 && GET_MODE_SIZE (outermode
) <= GET_MODE_SIZE (GET_MODE (op
)))
3280 return adjust_address_nv (op
, outermode
, byte
);
3282 /* Handle complex values represented as CONCAT
3283 of real and imaginary part. */
3284 if (GET_CODE (op
) == CONCAT
)
3286 int is_realpart
= byte
< GET_MODE_UNIT_SIZE (innermode
);
3287 rtx part
= is_realpart
? XEXP (op
, 0) : XEXP (op
, 1);
3288 unsigned int final_offset
;
3291 final_offset
= byte
% (GET_MODE_UNIT_SIZE (innermode
));
3292 res
= simplify_subreg (outermode
, part
, GET_MODE (part
), final_offset
);
3295 /* We can at least simplify it by referring directly to the relevant part. */
3296 return gen_rtx_SUBREG (outermode
, part
, final_offset
);
3301 /* Make a SUBREG operation or equivalent if it folds. */
3304 simplify_gen_subreg (enum machine_mode outermode
, rtx op
,
3305 enum machine_mode innermode
, unsigned int byte
)
3308 /* Little bit of sanity checking. */
3309 if (innermode
== VOIDmode
|| outermode
== VOIDmode
3310 || innermode
== BLKmode
|| outermode
== BLKmode
)
3313 if (GET_MODE (op
) != innermode
3314 && GET_MODE (op
) != VOIDmode
)
3317 if (byte
% GET_MODE_SIZE (outermode
)
3318 || byte
>= GET_MODE_SIZE (innermode
))
3321 if (GET_CODE (op
) == QUEUED
)
3324 new = simplify_subreg (outermode
, op
, innermode
, byte
);
3328 if (GET_CODE (op
) == SUBREG
|| GET_MODE (op
) == VOIDmode
)
3331 return gen_rtx_SUBREG (outermode
, op
, byte
);
3333 /* Simplify X, an rtx expression.
3335 Return the simplified expression or NULL if no simplifications
3338 This is the preferred entry point into the simplification routines;
3339 however, we still allow passes to call the more specific routines.
3341 Right now GCC has three (yes, three) major bodies of RTL simplification
3342 code that need to be unified.
3344 1. fold_rtx in cse.c. This code uses various CSE specific
3345 information to aid in RTL simplification.
3347 2. simplify_rtx in combine.c. Similar to fold_rtx, except that
3348 it uses combine specific information to aid in RTL
3351 3. The routines in this file.
3354 Long term we want to only have one body of simplification code; to
3355 get to that state I recommend the following steps:
3357 1. Pour over fold_rtx & simplify_rtx and move any simplifications
3358 which are not pass dependent state into these routines.
3360 2. As code is moved by #1, change fold_rtx & simplify_rtx to
3361 use this routine whenever possible.
3363 3. Allow for pass dependent state to be provided to these
3364 routines and add simplifications based on the pass dependent
3365 state. Remove code from cse.c & combine.c that becomes
3368 It will take time, but ultimately the compiler will be easier to
3369 maintain and improve. It's totally silly that when we add a
3370 simplification that it needs to be added to 4 places (3 for RTL
3371 simplification and 1 for tree simplification. */
3374 simplify_rtx (rtx x
)
3376 enum rtx_code code
= GET_CODE (x
);
3377 enum machine_mode mode
= GET_MODE (x
);
3380 switch (GET_RTX_CLASS (code
))
3383 return simplify_unary_operation (code
, mode
,
3384 XEXP (x
, 0), GET_MODE (XEXP (x
, 0)));
3386 if (swap_commutative_operands_p (XEXP (x
, 0), XEXP (x
, 1)))
3387 return simplify_gen_binary (code
, mode
, XEXP (x
, 1), XEXP (x
, 0));
3389 /* Fall through.... */
3392 return simplify_binary_operation (code
, mode
, XEXP (x
, 0), XEXP (x
, 1));
3396 return simplify_ternary_operation (code
, mode
, GET_MODE (XEXP (x
, 0)),
3397 XEXP (x
, 0), XEXP (x
, 1),
3401 temp
= simplify_relational_operation (code
,
3402 ((GET_MODE (XEXP (x
, 0))
3404 ? GET_MODE (XEXP (x
, 0))
3405 : GET_MODE (XEXP (x
, 1))),
3406 XEXP (x
, 0), XEXP (x
, 1));
3407 #ifdef FLOAT_STORE_FLAG_VALUE
3408 if (temp
!= 0 && GET_MODE_CLASS (mode
) == MODE_FLOAT
)
3410 if (temp
== const0_rtx
)
3411 temp
= CONST0_RTX (mode
);
3413 temp
= CONST_DOUBLE_FROM_REAL_VALUE (FLOAT_STORE_FLAG_VALUE (mode
),
3421 return simplify_gen_subreg (mode
, SUBREG_REG (x
),
3422 GET_MODE (SUBREG_REG (x
)),
3424 if (code
== CONSTANT_P_RTX
)
3426 if (CONSTANT_P (XEXP (x
, 0)))
3434 /* Convert (lo_sum (high FOO) FOO) to FOO. */
3435 if (GET_CODE (XEXP (x
, 0)) == HIGH
3436 && rtx_equal_p (XEXP (XEXP (x
, 0), 0), XEXP (x
, 1)))