1 /* RTL simplification functions for GNU compiler.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
25 #include "coretypes.h"
31 #include "hard-reg-set.h"
34 #include "insn-config.h"
43 /* Simplification and canonicalization of RTL. */
45 /* Much code operates on (low, high) pairs; the low value is an
46 unsigned wide int, the high value a signed wide int. We
47 occasionally need to sign extend from low to high as if low were a
49 #define HWI_SIGN_EXTEND(low) \
50 ((((HOST_WIDE_INT) low) < 0) ? ((HOST_WIDE_INT) -1) : ((HOST_WIDE_INT) 0))
52 static rtx
neg_const_int (enum machine_mode
, rtx
);
53 static int simplify_plus_minus_op_data_cmp (const void *, const void *);
54 static rtx
simplify_plus_minus (enum rtx_code
, enum machine_mode
, rtx
,
57 /* Negate a CONST_INT rtx, truncating (because a conversion from a
58 maximally negative number can overflow). */
60 neg_const_int (enum machine_mode mode
, rtx i
)
62 return gen_int_mode (- INTVAL (i
), mode
);
66 /* Make a binary operation by properly ordering the operands and
67 seeing if the expression folds. */
70 simplify_gen_binary (enum rtx_code code
, enum machine_mode mode
, rtx op0
,
75 /* Put complex operands first and constants second if commutative. */
76 if (GET_RTX_CLASS (code
) == 'c'
77 && swap_commutative_operands_p (op0
, op1
))
78 tem
= op0
, op0
= op1
, op1
= tem
;
80 /* If this simplifies, do it. */
81 tem
= simplify_binary_operation (code
, mode
, op0
, op1
);
85 /* Handle addition and subtraction specially. Otherwise, just form
88 if (code
== PLUS
|| code
== MINUS
)
90 tem
= simplify_plus_minus (code
, mode
, op0
, op1
, 1);
95 return gen_rtx_fmt_ee (code
, mode
, op0
, op1
);
98 /* If X is a MEM referencing the constant pool, return the real value.
99 Otherwise return X. */
101 avoid_constant_pool_reference (rtx x
)
104 enum machine_mode cmode
;
106 switch (GET_CODE (x
))
112 /* Handle float extensions of constant pool references. */
114 c
= avoid_constant_pool_reference (tmp
);
115 if (c
!= tmp
&& GET_CODE (c
) == CONST_DOUBLE
)
119 REAL_VALUE_FROM_CONST_DOUBLE (d
, c
);
120 return CONST_DOUBLE_FROM_REAL_VALUE (d
, GET_MODE (x
));
130 /* Call target hook to avoid the effects of -fpic etc... */
131 addr
= (*targetm
.delegitimize_address
) (addr
);
133 if (GET_CODE (addr
) == LO_SUM
)
134 addr
= XEXP (addr
, 1);
136 if (GET_CODE (addr
) != SYMBOL_REF
137 || ! CONSTANT_POOL_ADDRESS_P (addr
))
140 c
= get_pool_constant (addr
);
141 cmode
= get_pool_mode (addr
);
143 /* If we're accessing the constant in a different mode than it was
144 originally stored, attempt to fix that up via subreg simplifications.
145 If that fails we have no choice but to return the original memory. */
146 if (cmode
!= GET_MODE (x
))
148 c
= simplify_subreg (GET_MODE (x
), c
, cmode
, 0);
155 /* Make a unary operation by first seeing if it folds and otherwise making
156 the specified operation. */
159 simplify_gen_unary (enum rtx_code code
, enum machine_mode mode
, rtx op
,
160 enum machine_mode op_mode
)
164 /* If this simplifies, use it. */
165 if ((tem
= simplify_unary_operation (code
, mode
, op
, op_mode
)) != 0)
168 return gen_rtx_fmt_e (code
, mode
, op
);
171 /* Likewise for ternary operations. */
174 simplify_gen_ternary (enum rtx_code code
, enum machine_mode mode
,
175 enum machine_mode op0_mode
, rtx op0
, rtx op1
, rtx op2
)
179 /* If this simplifies, use it. */
180 if (0 != (tem
= simplify_ternary_operation (code
, mode
, op0_mode
,
184 return gen_rtx_fmt_eee (code
, mode
, op0
, op1
, op2
);
187 /* Likewise, for relational operations.
188 CMP_MODE specifies mode comparison is done in.
192 simplify_gen_relational (enum rtx_code code
, enum machine_mode mode
,
193 enum machine_mode cmp_mode
, rtx op0
, rtx op1
)
197 if ((tem
= simplify_relational_operation (code
, cmp_mode
, op0
, op1
)) != 0)
200 /* For the following tests, ensure const0_rtx is op1. */
201 if (op0
== const0_rtx
&& swap_commutative_operands_p (op0
, op1
))
202 tem
= op0
, op0
= op1
, op1
= tem
, code
= swap_condition (code
);
204 /* If op0 is a compare, extract the comparison arguments from it. */
205 if (GET_CODE (op0
) == COMPARE
&& op1
== const0_rtx
)
206 op1
= XEXP (op0
, 1), op0
= XEXP (op0
, 0);
208 /* If op0 is a comparison, extract the comparison arguments form it. */
209 if (code
== NE
&& op1
== const0_rtx
210 && GET_RTX_CLASS (GET_CODE (op0
)) == '<')
212 else if (code
== EQ
&& op1
== const0_rtx
)
214 /* The following tests GET_RTX_CLASS (GET_CODE (op0)) == '<'. */
215 enum rtx_code
new = reversed_comparison_code (op0
, NULL_RTX
);
225 /* Put complex operands first and constants second. */
226 if (swap_commutative_operands_p (op0
, op1
))
227 tem
= op0
, op0
= op1
, op1
= tem
, code
= swap_condition (code
);
229 return gen_rtx_fmt_ee (code
, mode
, op0
, op1
);
232 /* Replace all occurrences of OLD in X with NEW and try to simplify the
233 resulting RTX. Return a new RTX which is as simplified as possible. */
236 simplify_replace_rtx (rtx x
, rtx old
, rtx
new)
238 enum rtx_code code
= GET_CODE (x
);
239 enum machine_mode mode
= GET_MODE (x
);
241 /* If X is OLD, return NEW. Otherwise, if this is an expression, try
242 to build a new expression substituting recursively. If we can't do
243 anything, return our input. */
248 switch (GET_RTX_CLASS (code
))
252 enum machine_mode op_mode
= GET_MODE (XEXP (x
, 0));
253 rtx op
= (XEXP (x
, 0) == old
254 ? new : simplify_replace_rtx (XEXP (x
, 0), old
, new));
256 return simplify_gen_unary (code
, mode
, op
, op_mode
);
262 simplify_gen_binary (code
, mode
,
263 simplify_replace_rtx (XEXP (x
, 0), old
, new),
264 simplify_replace_rtx (XEXP (x
, 1), old
, new));
267 enum machine_mode op_mode
= (GET_MODE (XEXP (x
, 0)) != VOIDmode
268 ? GET_MODE (XEXP (x
, 0))
269 : GET_MODE (XEXP (x
, 1)));
270 rtx op0
= simplify_replace_rtx (XEXP (x
, 0), old
, new);
271 rtx op1
= simplify_replace_rtx (XEXP (x
, 1), old
, new);
272 rtx temp
= simplify_gen_relational (code
, mode
,
275 : GET_MODE (op0
) != VOIDmode
279 #ifdef FLOAT_STORE_FLAG_VALUE
280 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
)
282 if (temp
== const0_rtx
)
283 temp
= CONST0_RTX (mode
);
284 else if (temp
== const_true_rtx
)
285 temp
= CONST_DOUBLE_FROM_REAL_VALUE (FLOAT_STORE_FLAG_VALUE (mode
),
295 enum machine_mode op_mode
= GET_MODE (XEXP (x
, 0));
296 rtx op0
= simplify_replace_rtx (XEXP (x
, 0), old
, new);
299 simplify_gen_ternary (code
, mode
,
304 simplify_replace_rtx (XEXP (x
, 1), old
, new),
305 simplify_replace_rtx (XEXP (x
, 2), old
, new));
309 /* The only case we try to handle is a SUBREG. */
313 exp
= simplify_gen_subreg (GET_MODE (x
),
314 simplify_replace_rtx (SUBREG_REG (x
),
316 GET_MODE (SUBREG_REG (x
)),
325 return replace_equiv_address_nv (x
,
326 simplify_replace_rtx (XEXP (x
, 0),
328 else if (code
== LO_SUM
)
330 rtx op0
= simplify_replace_rtx (XEXP (x
, 0), old
, new);
331 rtx op1
= simplify_replace_rtx (XEXP (x
, 1), old
, new);
333 /* (lo_sum (high x) x) -> x */
334 if (GET_CODE (op0
) == HIGH
&& rtx_equal_p (XEXP (op0
, 0), op1
))
337 return gen_rtx_LO_SUM (mode
, op0
, op1
);
339 else if (code
== REG
)
341 if (REG_P (old
) && REGNO (x
) == REGNO (old
))
353 /* Try to simplify a unary operation CODE whose output mode is to be
354 MODE with input operand OP whose mode was originally OP_MODE.
355 Return zero if no simplification can be made. */
357 simplify_unary_operation (enum rtx_code code
, enum machine_mode mode
,
358 rtx op
, enum machine_mode op_mode
)
360 unsigned int width
= GET_MODE_BITSIZE (mode
);
361 rtx trueop
= avoid_constant_pool_reference (op
);
363 if (code
== VEC_DUPLICATE
)
365 if (!VECTOR_MODE_P (mode
))
367 if (GET_MODE (trueop
) != VOIDmode
368 && !VECTOR_MODE_P (GET_MODE (trueop
))
369 && GET_MODE_INNER (mode
) != GET_MODE (trueop
))
371 if (GET_MODE (trueop
) != VOIDmode
372 && VECTOR_MODE_P (GET_MODE (trueop
))
373 && GET_MODE_INNER (mode
) != GET_MODE_INNER (GET_MODE (trueop
)))
375 if (GET_CODE (trueop
) == CONST_INT
|| GET_CODE (trueop
) == CONST_DOUBLE
376 || GET_CODE (trueop
) == CONST_VECTOR
)
378 int elt_size
= GET_MODE_SIZE (GET_MODE_INNER (mode
));
379 unsigned n_elts
= (GET_MODE_SIZE (mode
) / elt_size
);
380 rtvec v
= rtvec_alloc (n_elts
);
383 if (GET_CODE (trueop
) != CONST_VECTOR
)
384 for (i
= 0; i
< n_elts
; i
++)
385 RTVEC_ELT (v
, i
) = trueop
;
388 enum machine_mode inmode
= GET_MODE (trueop
);
389 int in_elt_size
= GET_MODE_SIZE (GET_MODE_INNER (inmode
));
390 unsigned in_n_elts
= (GET_MODE_SIZE (inmode
) / in_elt_size
);
392 if (in_n_elts
>= n_elts
|| n_elts
% in_n_elts
)
394 for (i
= 0; i
< n_elts
; i
++)
395 RTVEC_ELT (v
, i
) = CONST_VECTOR_ELT (trueop
, i
% in_n_elts
);
397 return gen_rtx_CONST_VECTOR (mode
, v
);
401 if (VECTOR_MODE_P (mode
) && GET_CODE (trueop
) == CONST_VECTOR
)
403 int elt_size
= GET_MODE_SIZE (GET_MODE_INNER (mode
));
404 unsigned n_elts
= (GET_MODE_SIZE (mode
) / elt_size
);
405 enum machine_mode opmode
= GET_MODE (trueop
);
406 int op_elt_size
= GET_MODE_SIZE (GET_MODE_INNER (opmode
));
407 unsigned op_n_elts
= (GET_MODE_SIZE (opmode
) / op_elt_size
);
408 rtvec v
= rtvec_alloc (n_elts
);
411 if (op_n_elts
!= n_elts
)
414 for (i
= 0; i
< n_elts
; i
++)
416 rtx x
= simplify_unary_operation (code
, GET_MODE_INNER (mode
),
417 CONST_VECTOR_ELT (trueop
, i
),
418 GET_MODE_INNER (opmode
));
421 RTVEC_ELT (v
, i
) = x
;
423 return gen_rtx_CONST_VECTOR (mode
, v
);
426 /* The order of these tests is critical so that, for example, we don't
427 check the wrong mode (input vs. output) for a conversion operation,
428 such as FIX. At some point, this should be simplified. */
430 if (code
== FLOAT
&& GET_MODE (trueop
) == VOIDmode
431 && (GET_CODE (trueop
) == CONST_DOUBLE
|| GET_CODE (trueop
) == CONST_INT
))
433 HOST_WIDE_INT hv
, lv
;
436 if (GET_CODE (trueop
) == CONST_INT
)
437 lv
= INTVAL (trueop
), hv
= HWI_SIGN_EXTEND (lv
);
439 lv
= CONST_DOUBLE_LOW (trueop
), hv
= CONST_DOUBLE_HIGH (trueop
);
441 REAL_VALUE_FROM_INT (d
, lv
, hv
, mode
);
442 d
= real_value_truncate (mode
, d
);
443 return CONST_DOUBLE_FROM_REAL_VALUE (d
, mode
);
445 else if (code
== UNSIGNED_FLOAT
&& GET_MODE (trueop
) == VOIDmode
446 && (GET_CODE (trueop
) == CONST_DOUBLE
447 || GET_CODE (trueop
) == CONST_INT
))
449 HOST_WIDE_INT hv
, lv
;
452 if (GET_CODE (trueop
) == CONST_INT
)
453 lv
= INTVAL (trueop
), hv
= HWI_SIGN_EXTEND (lv
);
455 lv
= CONST_DOUBLE_LOW (trueop
), hv
= CONST_DOUBLE_HIGH (trueop
);
457 if (op_mode
== VOIDmode
)
459 /* We don't know how to interpret negative-looking numbers in
460 this case, so don't try to fold those. */
464 else if (GET_MODE_BITSIZE (op_mode
) >= HOST_BITS_PER_WIDE_INT
* 2)
467 hv
= 0, lv
&= GET_MODE_MASK (op_mode
);
469 REAL_VALUE_FROM_UNSIGNED_INT (d
, lv
, hv
, mode
);
470 d
= real_value_truncate (mode
, d
);
471 return CONST_DOUBLE_FROM_REAL_VALUE (d
, mode
);
474 if (GET_CODE (trueop
) == CONST_INT
475 && width
<= HOST_BITS_PER_WIDE_INT
&& width
> 0)
477 HOST_WIDE_INT arg0
= INTVAL (trueop
);
491 val
= (arg0
>= 0 ? arg0
: - arg0
);
495 /* Don't use ffs here. Instead, get low order bit and then its
496 number. If arg0 is zero, this will return 0, as desired. */
497 arg0
&= GET_MODE_MASK (mode
);
498 val
= exact_log2 (arg0
& (- arg0
)) + 1;
502 arg0
&= GET_MODE_MASK (mode
);
503 if (arg0
== 0 && CLZ_DEFINED_VALUE_AT_ZERO (mode
, val
))
506 val
= GET_MODE_BITSIZE (mode
) - floor_log2 (arg0
) - 1;
510 arg0
&= GET_MODE_MASK (mode
);
513 /* Even if the value at zero is undefined, we have to come
514 up with some replacement. Seems good enough. */
515 if (! CTZ_DEFINED_VALUE_AT_ZERO (mode
, val
))
516 val
= GET_MODE_BITSIZE (mode
);
519 val
= exact_log2 (arg0
& -arg0
);
523 arg0
&= GET_MODE_MASK (mode
);
526 val
++, arg0
&= arg0
- 1;
530 arg0
&= GET_MODE_MASK (mode
);
533 val
++, arg0
&= arg0
- 1;
542 /* When zero-extending a CONST_INT, we need to know its
544 if (op_mode
== VOIDmode
)
546 if (GET_MODE_BITSIZE (op_mode
) == HOST_BITS_PER_WIDE_INT
)
548 /* If we were really extending the mode,
549 we would have to distinguish between zero-extension
550 and sign-extension. */
551 if (width
!= GET_MODE_BITSIZE (op_mode
))
555 else if (GET_MODE_BITSIZE (op_mode
) < HOST_BITS_PER_WIDE_INT
)
556 val
= arg0
& ~((HOST_WIDE_INT
) (-1) << GET_MODE_BITSIZE (op_mode
));
562 if (op_mode
== VOIDmode
)
564 if (GET_MODE_BITSIZE (op_mode
) == HOST_BITS_PER_WIDE_INT
)
566 /* If we were really extending the mode,
567 we would have to distinguish between zero-extension
568 and sign-extension. */
569 if (width
!= GET_MODE_BITSIZE (op_mode
))
573 else if (GET_MODE_BITSIZE (op_mode
) < HOST_BITS_PER_WIDE_INT
)
576 = arg0
& ~((HOST_WIDE_INT
) (-1) << GET_MODE_BITSIZE (op_mode
));
578 & ((HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE (op_mode
) - 1)))
579 val
-= (HOST_WIDE_INT
) 1 << GET_MODE_BITSIZE (op_mode
);
596 val
= trunc_int_for_mode (val
, mode
);
598 return GEN_INT (val
);
601 /* We can do some operations on integer CONST_DOUBLEs. Also allow
602 for a DImode operation on a CONST_INT. */
603 else if (GET_MODE (trueop
) == VOIDmode
604 && width
<= HOST_BITS_PER_WIDE_INT
* 2
605 && (GET_CODE (trueop
) == CONST_DOUBLE
606 || GET_CODE (trueop
) == CONST_INT
))
608 unsigned HOST_WIDE_INT l1
, lv
;
609 HOST_WIDE_INT h1
, hv
;
611 if (GET_CODE (trueop
) == CONST_DOUBLE
)
612 l1
= CONST_DOUBLE_LOW (trueop
), h1
= CONST_DOUBLE_HIGH (trueop
);
614 l1
= INTVAL (trueop
), h1
= HWI_SIGN_EXTEND (l1
);
624 neg_double (l1
, h1
, &lv
, &hv
);
629 neg_double (l1
, h1
, &lv
, &hv
);
641 lv
= HOST_BITS_PER_WIDE_INT
+ exact_log2 (h1
& -h1
) + 1;
644 lv
= exact_log2 (l1
& -l1
) + 1;
650 lv
= GET_MODE_BITSIZE (mode
) - floor_log2 (l1
) - 1;
652 lv
= GET_MODE_BITSIZE (mode
) - floor_log2 (h1
) - 1
653 - HOST_BITS_PER_WIDE_INT
;
661 lv
= GET_MODE_BITSIZE (mode
);
663 lv
= HOST_BITS_PER_WIDE_INT
+ exact_log2 (h1
& -h1
);
666 lv
= exact_log2 (l1
& -l1
);
689 /* This is just a change-of-mode, so do nothing. */
694 if (op_mode
== VOIDmode
)
697 if (GET_MODE_BITSIZE (op_mode
) > HOST_BITS_PER_WIDE_INT
)
701 lv
= l1
& GET_MODE_MASK (op_mode
);
705 if (op_mode
== VOIDmode
706 || GET_MODE_BITSIZE (op_mode
) > HOST_BITS_PER_WIDE_INT
)
710 lv
= l1
& GET_MODE_MASK (op_mode
);
711 if (GET_MODE_BITSIZE (op_mode
) < HOST_BITS_PER_WIDE_INT
712 && (lv
& ((HOST_WIDE_INT
) 1
713 << (GET_MODE_BITSIZE (op_mode
) - 1))) != 0)
714 lv
-= (HOST_WIDE_INT
) 1 << GET_MODE_BITSIZE (op_mode
);
716 hv
= HWI_SIGN_EXTEND (lv
);
727 return immed_double_const (lv
, hv
, mode
);
730 else if (GET_CODE (trueop
) == CONST_DOUBLE
731 && GET_MODE_CLASS (mode
) == MODE_FLOAT
)
733 REAL_VALUE_TYPE d
, t
;
734 REAL_VALUE_FROM_CONST_DOUBLE (d
, trueop
);
739 if (HONOR_SNANS (mode
) && real_isnan (&d
))
741 real_sqrt (&t
, mode
, &d
);
745 d
= REAL_VALUE_ABS (d
);
748 d
= REAL_VALUE_NEGATE (d
);
751 d
= real_value_truncate (mode
, d
);
754 /* All this does is change the mode. */
757 real_arithmetic (&d
, FIX_TRUNC_EXPR
, &d
, NULL
);
763 return CONST_DOUBLE_FROM_REAL_VALUE (d
, mode
);
766 else if (GET_CODE (trueop
) == CONST_DOUBLE
767 && GET_MODE_CLASS (GET_MODE (trueop
)) == MODE_FLOAT
768 && GET_MODE_CLASS (mode
) == MODE_INT
769 && width
<= HOST_BITS_PER_WIDE_INT
&& width
> 0)
773 REAL_VALUE_FROM_CONST_DOUBLE (d
, trueop
);
776 case FIX
: i
= REAL_VALUE_FIX (d
); break;
777 case UNSIGNED_FIX
: i
= REAL_VALUE_UNSIGNED_FIX (d
); break;
781 return gen_int_mode (i
, mode
);
784 /* This was formerly used only for non-IEEE float.
785 eggert@twinsun.com says it is safe for IEEE also. */
788 enum rtx_code reversed
;
789 /* There are some simplifications we can do even if the operands
794 /* (not (not X)) == X. */
795 if (GET_CODE (op
) == NOT
)
798 /* (not (eq X Y)) == (ne X Y), etc. */
799 if (mode
== BImode
&& GET_RTX_CLASS (GET_CODE (op
)) == '<'
800 && ((reversed
= reversed_comparison_code (op
, NULL_RTX
))
802 return gen_rtx_fmt_ee (reversed
,
803 op_mode
, XEXP (op
, 0), XEXP (op
, 1));
807 /* (neg (neg X)) == X. */
808 if (GET_CODE (op
) == NEG
)
813 /* (sign_extend (truncate (minus (label_ref L1) (label_ref L2))))
814 becomes just the MINUS if its mode is MODE. This allows
815 folding switch statements on machines using casesi (such as
817 if (GET_CODE (op
) == TRUNCATE
818 && GET_MODE (XEXP (op
, 0)) == mode
819 && GET_CODE (XEXP (op
, 0)) == MINUS
820 && GET_CODE (XEXP (XEXP (op
, 0), 0)) == LABEL_REF
821 && GET_CODE (XEXP (XEXP (op
, 0), 1)) == LABEL_REF
)
824 #if defined(POINTERS_EXTEND_UNSIGNED) && !defined(HAVE_ptr_extend)
825 if (! POINTERS_EXTEND_UNSIGNED
826 && mode
== Pmode
&& GET_MODE (op
) == ptr_mode
828 || (GET_CODE (op
) == SUBREG
829 && GET_CODE (SUBREG_REG (op
)) == REG
830 && REG_POINTER (SUBREG_REG (op
))
831 && GET_MODE (SUBREG_REG (op
)) == Pmode
)))
832 return convert_memory_address (Pmode
, op
);
836 #if defined(POINTERS_EXTEND_UNSIGNED) && !defined(HAVE_ptr_extend)
838 if (POINTERS_EXTEND_UNSIGNED
> 0
839 && mode
== Pmode
&& GET_MODE (op
) == ptr_mode
841 || (GET_CODE (op
) == SUBREG
842 && GET_CODE (SUBREG_REG (op
)) == REG
843 && REG_POINTER (SUBREG_REG (op
))
844 && GET_MODE (SUBREG_REG (op
)) == Pmode
)))
845 return convert_memory_address (Pmode
, op
);
857 /* Simplify a binary operation CODE with result mode MODE, operating on OP0
858 and OP1. Return 0 if no simplification is possible.
860 Don't use this for relational operations such as EQ or LT.
861 Use simplify_relational_operation instead. */
863 simplify_binary_operation (enum rtx_code code
, enum machine_mode mode
,
866 HOST_WIDE_INT arg0
, arg1
, arg0s
, arg1s
;
868 unsigned int width
= GET_MODE_BITSIZE (mode
);
870 rtx trueop0
= avoid_constant_pool_reference (op0
);
871 rtx trueop1
= avoid_constant_pool_reference (op1
);
873 /* Relational operations don't work here. We must know the mode
874 of the operands in order to do the comparison correctly.
875 Assuming a full word can give incorrect results.
876 Consider comparing 128 with -128 in QImode. */
878 if (GET_RTX_CLASS (code
) == '<')
881 /* Make sure the constant is second. */
882 if (GET_RTX_CLASS (code
) == 'c'
883 && swap_commutative_operands_p (trueop0
, trueop1
))
885 tem
= op0
, op0
= op1
, op1
= tem
;
886 tem
= trueop0
, trueop0
= trueop1
, trueop1
= tem
;
889 if (VECTOR_MODE_P (mode
)
890 && GET_CODE (trueop0
) == CONST_VECTOR
891 && GET_CODE (trueop1
) == CONST_VECTOR
)
893 int elt_size
= GET_MODE_SIZE (GET_MODE_INNER (mode
));
894 unsigned n_elts
= (GET_MODE_SIZE (mode
) / elt_size
);
895 enum machine_mode op0mode
= GET_MODE (trueop0
);
896 int op0_elt_size
= GET_MODE_SIZE (GET_MODE_INNER (op0mode
));
897 unsigned op0_n_elts
= (GET_MODE_SIZE (op0mode
) / op0_elt_size
);
898 enum machine_mode op1mode
= GET_MODE (trueop1
);
899 int op1_elt_size
= GET_MODE_SIZE (GET_MODE_INNER (op1mode
));
900 unsigned op1_n_elts
= (GET_MODE_SIZE (op1mode
) / op1_elt_size
);
901 rtvec v
= rtvec_alloc (n_elts
);
904 if (op0_n_elts
!= n_elts
|| op1_n_elts
!= n_elts
)
907 for (i
= 0; i
< n_elts
; i
++)
909 rtx x
= simplify_binary_operation (code
, GET_MODE_INNER (mode
),
910 CONST_VECTOR_ELT (trueop0
, i
),
911 CONST_VECTOR_ELT (trueop1
, i
));
914 RTVEC_ELT (v
, i
) = x
;
917 return gen_rtx_CONST_VECTOR (mode
, v
);
920 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
921 && GET_CODE (trueop0
) == CONST_DOUBLE
922 && GET_CODE (trueop1
) == CONST_DOUBLE
923 && mode
== GET_MODE (op0
) && mode
== GET_MODE (op1
))
925 REAL_VALUE_TYPE f0
, f1
, value
;
927 REAL_VALUE_FROM_CONST_DOUBLE (f0
, trueop0
);
928 REAL_VALUE_FROM_CONST_DOUBLE (f1
, trueop1
);
929 f0
= real_value_truncate (mode
, f0
);
930 f1
= real_value_truncate (mode
, f1
);
933 && !MODE_HAS_INFINITIES (mode
)
934 && REAL_VALUES_EQUAL (f1
, dconst0
))
937 REAL_ARITHMETIC (value
, rtx_to_tree_code (code
), f0
, f1
);
939 value
= real_value_truncate (mode
, value
);
940 return CONST_DOUBLE_FROM_REAL_VALUE (value
, mode
);
943 /* We can fold some multi-word operations. */
944 if (GET_MODE_CLASS (mode
) == MODE_INT
945 && width
== HOST_BITS_PER_WIDE_INT
* 2
946 && (GET_CODE (trueop0
) == CONST_DOUBLE
947 || GET_CODE (trueop0
) == CONST_INT
)
948 && (GET_CODE (trueop1
) == CONST_DOUBLE
949 || GET_CODE (trueop1
) == CONST_INT
))
951 unsigned HOST_WIDE_INT l1
, l2
, lv
;
952 HOST_WIDE_INT h1
, h2
, hv
;
954 if (GET_CODE (trueop0
) == CONST_DOUBLE
)
955 l1
= CONST_DOUBLE_LOW (trueop0
), h1
= CONST_DOUBLE_HIGH (trueop0
);
957 l1
= INTVAL (trueop0
), h1
= HWI_SIGN_EXTEND (l1
);
959 if (GET_CODE (trueop1
) == CONST_DOUBLE
)
960 l2
= CONST_DOUBLE_LOW (trueop1
), h2
= CONST_DOUBLE_HIGH (trueop1
);
962 l2
= INTVAL (trueop1
), h2
= HWI_SIGN_EXTEND (l2
);
967 /* A - B == A + (-B). */
968 neg_double (l2
, h2
, &lv
, &hv
);
971 /* .. fall through ... */
974 add_double (l1
, h1
, l2
, h2
, &lv
, &hv
);
978 mul_double (l1
, h1
, l2
, h2
, &lv
, &hv
);
981 case DIV
: case MOD
: case UDIV
: case UMOD
:
982 /* We'd need to include tree.h to do this and it doesn't seem worth
987 lv
= l1
& l2
, hv
= h1
& h2
;
991 lv
= l1
| l2
, hv
= h1
| h2
;
995 lv
= l1
^ l2
, hv
= h1
^ h2
;
1001 && ((unsigned HOST_WIDE_INT
) l1
1002 < (unsigned HOST_WIDE_INT
) l2
)))
1011 && ((unsigned HOST_WIDE_INT
) l1
1012 > (unsigned HOST_WIDE_INT
) l2
)))
1019 if ((unsigned HOST_WIDE_INT
) h1
< (unsigned HOST_WIDE_INT
) h2
1021 && ((unsigned HOST_WIDE_INT
) l1
1022 < (unsigned HOST_WIDE_INT
) l2
)))
1029 if ((unsigned HOST_WIDE_INT
) h1
> (unsigned HOST_WIDE_INT
) h2
1031 && ((unsigned HOST_WIDE_INT
) l1
1032 > (unsigned HOST_WIDE_INT
) l2
)))
1038 case LSHIFTRT
: case ASHIFTRT
:
1040 case ROTATE
: case ROTATERT
:
1041 #ifdef SHIFT_COUNT_TRUNCATED
1042 if (SHIFT_COUNT_TRUNCATED
)
1043 l2
&= (GET_MODE_BITSIZE (mode
) - 1), h2
= 0;
1046 if (h2
!= 0 || l2
>= GET_MODE_BITSIZE (mode
))
1049 if (code
== LSHIFTRT
|| code
== ASHIFTRT
)
1050 rshift_double (l1
, h1
, l2
, GET_MODE_BITSIZE (mode
), &lv
, &hv
,
1052 else if (code
== ASHIFT
)
1053 lshift_double (l1
, h1
, l2
, GET_MODE_BITSIZE (mode
), &lv
, &hv
, 1);
1054 else if (code
== ROTATE
)
1055 lrotate_double (l1
, h1
, l2
, GET_MODE_BITSIZE (mode
), &lv
, &hv
);
1056 else /* code == ROTATERT */
1057 rrotate_double (l1
, h1
, l2
, GET_MODE_BITSIZE (mode
), &lv
, &hv
);
1064 return immed_double_const (lv
, hv
, mode
);
1067 if (GET_CODE (op0
) != CONST_INT
|| GET_CODE (op1
) != CONST_INT
1068 || width
> HOST_BITS_PER_WIDE_INT
|| width
== 0)
1070 /* Even if we can't compute a constant result,
1071 there are some cases worth simplifying. */
1076 /* Maybe simplify x + 0 to x. The two expressions are equivalent
1077 when x is NaN, infinite, or finite and nonzero. They aren't
1078 when x is -0 and the rounding mode is not towards -infinity,
1079 since (-0) + 0 is then 0. */
1080 if (!HONOR_SIGNED_ZEROS (mode
) && trueop1
== CONST0_RTX (mode
))
1083 /* ((-a) + b) -> (b - a) and similarly for (a + (-b)). These
1084 transformations are safe even for IEEE. */
1085 if (GET_CODE (op0
) == NEG
)
1086 return simplify_gen_binary (MINUS
, mode
, op1
, XEXP (op0
, 0));
1087 else if (GET_CODE (op1
) == NEG
)
1088 return simplify_gen_binary (MINUS
, mode
, op0
, XEXP (op1
, 0));
1090 /* (~a) + 1 -> -a */
1091 if (INTEGRAL_MODE_P (mode
)
1092 && GET_CODE (op0
) == NOT
1093 && trueop1
== const1_rtx
)
1094 return gen_rtx_NEG (mode
, XEXP (op0
, 0));
1096 /* Handle both-operands-constant cases. We can only add
1097 CONST_INTs to constants since the sum of relocatable symbols
1098 can't be handled by most assemblers. Don't add CONST_INT
1099 to CONST_INT since overflow won't be computed properly if wider
1100 than HOST_BITS_PER_WIDE_INT. */
1102 if (CONSTANT_P (op0
) && GET_MODE (op0
) != VOIDmode
1103 && GET_CODE (op1
) == CONST_INT
)
1104 return plus_constant (op0
, INTVAL (op1
));
1105 else if (CONSTANT_P (op1
) && GET_MODE (op1
) != VOIDmode
1106 && GET_CODE (op0
) == CONST_INT
)
1107 return plus_constant (op1
, INTVAL (op0
));
1109 /* See if this is something like X * C - X or vice versa or
1110 if the multiplication is written as a shift. If so, we can
1111 distribute and make a new multiply, shift, or maybe just
1112 have X (if C is 2 in the example above). But don't make
1113 real multiply if we didn't have one before. */
1115 if (! FLOAT_MODE_P (mode
))
1117 HOST_WIDE_INT coeff0
= 1, coeff1
= 1;
1118 rtx lhs
= op0
, rhs
= op1
;
1121 if (GET_CODE (lhs
) == NEG
)
1122 coeff0
= -1, lhs
= XEXP (lhs
, 0);
1123 else if (GET_CODE (lhs
) == MULT
1124 && GET_CODE (XEXP (lhs
, 1)) == CONST_INT
)
1126 coeff0
= INTVAL (XEXP (lhs
, 1)), lhs
= XEXP (lhs
, 0);
1129 else if (GET_CODE (lhs
) == ASHIFT
1130 && GET_CODE (XEXP (lhs
, 1)) == CONST_INT
1131 && INTVAL (XEXP (lhs
, 1)) >= 0
1132 && INTVAL (XEXP (lhs
, 1)) < HOST_BITS_PER_WIDE_INT
)
1134 coeff0
= ((HOST_WIDE_INT
) 1) << INTVAL (XEXP (lhs
, 1));
1135 lhs
= XEXP (lhs
, 0);
1138 if (GET_CODE (rhs
) == NEG
)
1139 coeff1
= -1, rhs
= XEXP (rhs
, 0);
1140 else if (GET_CODE (rhs
) == MULT
1141 && GET_CODE (XEXP (rhs
, 1)) == CONST_INT
)
1143 coeff1
= INTVAL (XEXP (rhs
, 1)), rhs
= XEXP (rhs
, 0);
1146 else if (GET_CODE (rhs
) == ASHIFT
1147 && GET_CODE (XEXP (rhs
, 1)) == CONST_INT
1148 && INTVAL (XEXP (rhs
, 1)) >= 0
1149 && INTVAL (XEXP (rhs
, 1)) < HOST_BITS_PER_WIDE_INT
)
1151 coeff1
= ((HOST_WIDE_INT
) 1) << INTVAL (XEXP (rhs
, 1));
1152 rhs
= XEXP (rhs
, 0);
1155 if (rtx_equal_p (lhs
, rhs
))
1157 tem
= simplify_gen_binary (MULT
, mode
, lhs
,
1158 GEN_INT (coeff0
+ coeff1
));
1159 return (GET_CODE (tem
) == MULT
&& ! had_mult
) ? 0 : tem
;
1163 /* If one of the operands is a PLUS or a MINUS, see if we can
1164 simplify this by the associative law.
1165 Don't use the associative law for floating point.
1166 The inaccuracy makes it nonassociative,
1167 and subtle programs can break if operations are associated. */
1169 if (INTEGRAL_MODE_P (mode
)
1170 && (GET_CODE (op0
) == PLUS
|| GET_CODE (op0
) == MINUS
1171 || GET_CODE (op1
) == PLUS
|| GET_CODE (op1
) == MINUS
1172 || (GET_CODE (op0
) == CONST
1173 && GET_CODE (XEXP (op0
, 0)) == PLUS
)
1174 || (GET_CODE (op1
) == CONST
1175 && GET_CODE (XEXP (op1
, 0)) == PLUS
))
1176 && (tem
= simplify_plus_minus (code
, mode
, op0
, op1
, 0)) != 0)
1182 /* Convert (compare FOO (const_int 0)) to FOO unless we aren't
1183 using cc0, in which case we want to leave it as a COMPARE
1184 so we can distinguish it from a register-register-copy.
1186 In IEEE floating point, x-0 is not the same as x. */
1188 if ((TARGET_FLOAT_FORMAT
!= IEEE_FLOAT_FORMAT
1189 || ! FLOAT_MODE_P (mode
) || flag_unsafe_math_optimizations
)
1190 && trueop1
== CONST0_RTX (mode
))
1194 /* Convert (compare (gt (flags) 0) (lt (flags) 0)) to (flags). */
1195 if (((GET_CODE (op0
) == GT
&& GET_CODE (op1
) == LT
)
1196 || (GET_CODE (op0
) == GTU
&& GET_CODE (op1
) == LTU
))
1197 && XEXP (op0
, 1) == const0_rtx
&& XEXP (op1
, 1) == const0_rtx
)
1199 rtx xop00
= XEXP (op0
, 0);
1200 rtx xop10
= XEXP (op1
, 0);
1203 if (GET_CODE (xop00
) == CC0
&& GET_CODE (xop10
) == CC0
)
1205 if (GET_CODE (xop00
) == REG
&& GET_CODE (xop10
) == REG
1206 && GET_MODE (xop00
) == GET_MODE (xop10
)
1207 && REGNO (xop00
) == REGNO (xop10
)
1208 && GET_MODE_CLASS (GET_MODE (xop00
)) == MODE_CC
1209 && GET_MODE_CLASS (GET_MODE (xop10
)) == MODE_CC
)
1216 /* We can't assume x-x is 0 even with non-IEEE floating point,
1217 but since it is zero except in very strange circumstances, we
1218 will treat it as zero with -funsafe-math-optimizations. */
1219 if (rtx_equal_p (trueop0
, trueop1
)
1220 && ! side_effects_p (op0
)
1221 && (! FLOAT_MODE_P (mode
) || flag_unsafe_math_optimizations
))
1222 return CONST0_RTX (mode
);
1224 /* Change subtraction from zero into negation. (0 - x) is the
1225 same as -x when x is NaN, infinite, or finite and nonzero.
1226 But if the mode has signed zeros, and does not round towards
1227 -infinity, then 0 - 0 is 0, not -0. */
1228 if (!HONOR_SIGNED_ZEROS (mode
) && trueop0
== CONST0_RTX (mode
))
1229 return gen_rtx_NEG (mode
, op1
);
1231 /* (-1 - a) is ~a. */
1232 if (trueop0
== constm1_rtx
)
1233 return gen_rtx_NOT (mode
, op1
);
1235 /* Subtracting 0 has no effect unless the mode has signed zeros
1236 and supports rounding towards -infinity. In such a case,
1238 if (!(HONOR_SIGNED_ZEROS (mode
)
1239 && HONOR_SIGN_DEPENDENT_ROUNDING (mode
))
1240 && trueop1
== CONST0_RTX (mode
))
1243 /* See if this is something like X * C - X or vice versa or
1244 if the multiplication is written as a shift. If so, we can
1245 distribute and make a new multiply, shift, or maybe just
1246 have X (if C is 2 in the example above). But don't make
1247 real multiply if we didn't have one before. */
1249 if (! FLOAT_MODE_P (mode
))
1251 HOST_WIDE_INT coeff0
= 1, coeff1
= 1;
1252 rtx lhs
= op0
, rhs
= op1
;
1255 if (GET_CODE (lhs
) == NEG
)
1256 coeff0
= -1, lhs
= XEXP (lhs
, 0);
1257 else if (GET_CODE (lhs
) == MULT
1258 && GET_CODE (XEXP (lhs
, 1)) == CONST_INT
)
1260 coeff0
= INTVAL (XEXP (lhs
, 1)), lhs
= XEXP (lhs
, 0);
1263 else if (GET_CODE (lhs
) == ASHIFT
1264 && GET_CODE (XEXP (lhs
, 1)) == CONST_INT
1265 && INTVAL (XEXP (lhs
, 1)) >= 0
1266 && INTVAL (XEXP (lhs
, 1)) < HOST_BITS_PER_WIDE_INT
)
1268 coeff0
= ((HOST_WIDE_INT
) 1) << INTVAL (XEXP (lhs
, 1));
1269 lhs
= XEXP (lhs
, 0);
1272 if (GET_CODE (rhs
) == NEG
)
1273 coeff1
= - 1, rhs
= XEXP (rhs
, 0);
1274 else if (GET_CODE (rhs
) == MULT
1275 && GET_CODE (XEXP (rhs
, 1)) == CONST_INT
)
1277 coeff1
= INTVAL (XEXP (rhs
, 1)), rhs
= XEXP (rhs
, 0);
1280 else if (GET_CODE (rhs
) == ASHIFT
1281 && GET_CODE (XEXP (rhs
, 1)) == CONST_INT
1282 && INTVAL (XEXP (rhs
, 1)) >= 0
1283 && INTVAL (XEXP (rhs
, 1)) < HOST_BITS_PER_WIDE_INT
)
1285 coeff1
= ((HOST_WIDE_INT
) 1) << INTVAL (XEXP (rhs
, 1));
1286 rhs
= XEXP (rhs
, 0);
1289 if (rtx_equal_p (lhs
, rhs
))
1291 tem
= simplify_gen_binary (MULT
, mode
, lhs
,
1292 GEN_INT (coeff0
- coeff1
));
1293 return (GET_CODE (tem
) == MULT
&& ! had_mult
) ? 0 : tem
;
1297 /* (a - (-b)) -> (a + b). True even for IEEE. */
1298 if (GET_CODE (op1
) == NEG
)
1299 return simplify_gen_binary (PLUS
, mode
, op0
, XEXP (op1
, 0));
1301 /* If one of the operands is a PLUS or a MINUS, see if we can
1302 simplify this by the associative law.
1303 Don't use the associative law for floating point.
1304 The inaccuracy makes it nonassociative,
1305 and subtle programs can break if operations are associated. */
1307 if (INTEGRAL_MODE_P (mode
)
1308 && (GET_CODE (op0
) == PLUS
|| GET_CODE (op0
) == MINUS
1309 || GET_CODE (op1
) == PLUS
|| GET_CODE (op1
) == MINUS
1310 || (GET_CODE (op0
) == CONST
1311 && GET_CODE (XEXP (op0
, 0)) == PLUS
)
1312 || (GET_CODE (op1
) == CONST
1313 && GET_CODE (XEXP (op1
, 0)) == PLUS
))
1314 && (tem
= simplify_plus_minus (code
, mode
, op0
, op1
, 0)) != 0)
1317 /* Don't let a relocatable value get a negative coeff. */
1318 if (GET_CODE (op1
) == CONST_INT
&& GET_MODE (op0
) != VOIDmode
)
1319 return simplify_gen_binary (PLUS
, mode
,
1321 neg_const_int (mode
, op1
));
1323 /* (x - (x & y)) -> (x & ~y) */
1324 if (GET_CODE (op1
) == AND
)
1326 if (rtx_equal_p (op0
, XEXP (op1
, 0)))
1328 tem
= simplify_gen_unary (NOT
, mode
, XEXP (op1
, 1),
1329 GET_MODE (XEXP (op1
, 1)));
1330 return simplify_gen_binary (AND
, mode
, op0
, tem
);
1332 if (rtx_equal_p (op0
, XEXP (op1
, 1)))
1334 tem
= simplify_gen_unary (NOT
, mode
, XEXP (op1
, 0),
1335 GET_MODE (XEXP (op1
, 0)));
1336 return simplify_gen_binary (AND
, mode
, op0
, tem
);
1342 if (trueop1
== constm1_rtx
)
1344 tem
= simplify_unary_operation (NEG
, mode
, op0
, mode
);
1346 return tem
? tem
: gen_rtx_NEG (mode
, op0
);
1349 /* Maybe simplify x * 0 to 0. The reduction is not valid if
1350 x is NaN, since x * 0 is then also NaN. Nor is it valid
1351 when the mode has signed zeros, since multiplying a negative
1352 number by 0 will give -0, not 0. */
1353 if (!HONOR_NANS (mode
)
1354 && !HONOR_SIGNED_ZEROS (mode
)
1355 && trueop1
== CONST0_RTX (mode
)
1356 && ! side_effects_p (op0
))
1359 /* In IEEE floating point, x*1 is not equivalent to x for
1361 if (!HONOR_SNANS (mode
)
1362 && trueop1
== CONST1_RTX (mode
))
1365 /* Convert multiply by constant power of two into shift unless
1366 we are still generating RTL. This test is a kludge. */
1367 if (GET_CODE (trueop1
) == CONST_INT
1368 && (val
= exact_log2 (INTVAL (trueop1
))) >= 0
1369 /* If the mode is larger than the host word size, and the
1370 uppermost bit is set, then this isn't a power of two due
1371 to implicit sign extension. */
1372 && (width
<= HOST_BITS_PER_WIDE_INT
1373 || val
!= HOST_BITS_PER_WIDE_INT
- 1)
1374 && ! rtx_equal_function_value_matters
)
1375 return gen_rtx_ASHIFT (mode
, op0
, GEN_INT (val
));
1377 /* x*2 is x+x and x*(-1) is -x */
1378 if (GET_CODE (trueop1
) == CONST_DOUBLE
1379 && GET_MODE_CLASS (GET_MODE (trueop1
)) == MODE_FLOAT
1380 && GET_MODE (op0
) == mode
)
1383 REAL_VALUE_FROM_CONST_DOUBLE (d
, trueop1
);
1385 if (REAL_VALUES_EQUAL (d
, dconst2
))
1386 return gen_rtx_PLUS (mode
, op0
, copy_rtx (op0
));
1388 if (REAL_VALUES_EQUAL (d
, dconstm1
))
1389 return gen_rtx_NEG (mode
, op0
);
1394 if (trueop1
== const0_rtx
)
1396 if (GET_CODE (trueop1
) == CONST_INT
1397 && ((INTVAL (trueop1
) & GET_MODE_MASK (mode
))
1398 == GET_MODE_MASK (mode
)))
1400 if (rtx_equal_p (trueop0
, trueop1
) && ! side_effects_p (op0
))
1402 /* A | (~A) -> -1 */
1403 if (((GET_CODE (op0
) == NOT
&& rtx_equal_p (XEXP (op0
, 0), op1
))
1404 || (GET_CODE (op1
) == NOT
&& rtx_equal_p (XEXP (op1
, 0), op0
)))
1405 && ! side_effects_p (op0
)
1406 && GET_MODE_CLASS (mode
) != MODE_CC
)
1411 if (trueop1
== const0_rtx
)
1413 if (GET_CODE (trueop1
) == CONST_INT
1414 && ((INTVAL (trueop1
) & GET_MODE_MASK (mode
))
1415 == GET_MODE_MASK (mode
)))
1416 return gen_rtx_NOT (mode
, op0
);
1417 if (trueop0
== trueop1
&& ! side_effects_p (op0
)
1418 && GET_MODE_CLASS (mode
) != MODE_CC
)
1423 if (trueop1
== const0_rtx
&& ! side_effects_p (op0
))
1425 if (GET_CODE (trueop1
) == CONST_INT
1426 && ((INTVAL (trueop1
) & GET_MODE_MASK (mode
))
1427 == GET_MODE_MASK (mode
)))
1429 if (trueop0
== trueop1
&& ! side_effects_p (op0
)
1430 && GET_MODE_CLASS (mode
) != MODE_CC
)
1433 if (((GET_CODE (op0
) == NOT
&& rtx_equal_p (XEXP (op0
, 0), op1
))
1434 || (GET_CODE (op1
) == NOT
&& rtx_equal_p (XEXP (op1
, 0), op0
)))
1435 && ! side_effects_p (op0
)
1436 && GET_MODE_CLASS (mode
) != MODE_CC
)
1441 /* Convert divide by power of two into shift (divide by 1 handled
1443 if (GET_CODE (trueop1
) == CONST_INT
1444 && (arg1
= exact_log2 (INTVAL (trueop1
))) > 0)
1445 return gen_rtx_LSHIFTRT (mode
, op0
, GEN_INT (arg1
));
1447 /* ... fall through ... */
1450 if (trueop1
== CONST1_RTX (mode
))
1452 /* On some platforms DIV uses narrower mode than its
1454 rtx x
= gen_lowpart_common (mode
, op0
);
1457 else if (mode
!= GET_MODE (op0
) && GET_MODE (op0
) != VOIDmode
)
1458 return gen_lowpart_SUBREG (mode
, op0
);
1463 /* Maybe change 0 / x to 0. This transformation isn't safe for
1464 modes with NaNs, since 0 / 0 will then be NaN rather than 0.
1465 Nor is it safe for modes with signed zeros, since dividing
1466 0 by a negative number gives -0, not 0. */
1467 if (!HONOR_NANS (mode
)
1468 && !HONOR_SIGNED_ZEROS (mode
)
1469 && trueop0
== CONST0_RTX (mode
)
1470 && ! side_effects_p (op1
))
1473 /* Change division by a constant into multiplication. Only do
1474 this with -funsafe-math-optimizations. */
1475 else if (GET_CODE (trueop1
) == CONST_DOUBLE
1476 && GET_MODE_CLASS (GET_MODE (trueop1
)) == MODE_FLOAT
1477 && trueop1
!= CONST0_RTX (mode
)
1478 && flag_unsafe_math_optimizations
)
1481 REAL_VALUE_FROM_CONST_DOUBLE (d
, trueop1
);
1483 if (! REAL_VALUES_EQUAL (d
, dconst0
))
1485 REAL_ARITHMETIC (d
, rtx_to_tree_code (DIV
), dconst1
, d
);
1486 return gen_rtx_MULT (mode
, op0
,
1487 CONST_DOUBLE_FROM_REAL_VALUE (d
, mode
));
1493 /* Handle modulus by power of two (mod with 1 handled below). */
1494 if (GET_CODE (trueop1
) == CONST_INT
1495 && exact_log2 (INTVAL (trueop1
)) > 0)
1496 return gen_rtx_AND (mode
, op0
, GEN_INT (INTVAL (op1
) - 1));
1498 /* ... fall through ... */
1501 if ((trueop0
== const0_rtx
|| trueop1
== const1_rtx
)
1502 && ! side_effects_p (op0
) && ! side_effects_p (op1
))
1509 /* Rotating ~0 always results in ~0. */
1510 if (GET_CODE (trueop0
) == CONST_INT
&& width
<= HOST_BITS_PER_WIDE_INT
1511 && (unsigned HOST_WIDE_INT
) INTVAL (trueop0
) == GET_MODE_MASK (mode
)
1512 && ! side_effects_p (op1
))
1515 /* ... fall through ... */
1519 if (trueop1
== const0_rtx
)
1521 if (trueop0
== const0_rtx
&& ! side_effects_p (op1
))
1526 if (width
<= HOST_BITS_PER_WIDE_INT
&& GET_CODE (trueop1
) == CONST_INT
1527 && INTVAL (trueop1
) == (HOST_WIDE_INT
) 1 << (width
-1)
1528 && ! side_effects_p (op0
))
1530 else if (rtx_equal_p (trueop0
, trueop1
) && ! side_effects_p (op0
))
1535 if (width
<= HOST_BITS_PER_WIDE_INT
&& GET_CODE (trueop1
) == CONST_INT
1536 && ((unsigned HOST_WIDE_INT
) INTVAL (trueop1
)
1537 == (unsigned HOST_WIDE_INT
) GET_MODE_MASK (mode
) >> 1)
1538 && ! side_effects_p (op0
))
1540 else if (rtx_equal_p (trueop0
, trueop1
) && ! side_effects_p (op0
))
1545 if (trueop1
== const0_rtx
&& ! side_effects_p (op0
))
1547 else if (rtx_equal_p (trueop0
, trueop1
) && ! side_effects_p (op0
))
1552 if (trueop1
== constm1_rtx
&& ! side_effects_p (op0
))
1554 else if (rtx_equal_p (trueop0
, trueop1
) && ! side_effects_p (op0
))
1562 /* ??? There are simplifications that can be done. */
1566 if (!VECTOR_MODE_P (mode
))
1568 if (!VECTOR_MODE_P (GET_MODE (trueop0
))
1570 != GET_MODE_INNER (GET_MODE (trueop0
)))
1571 || GET_CODE (trueop1
) != PARALLEL
1572 || XVECLEN (trueop1
, 0) != 1
1573 || GET_CODE (XVECEXP (trueop1
, 0, 0)) != CONST_INT
)
1576 if (GET_CODE (trueop0
) == CONST_VECTOR
)
1577 return CONST_VECTOR_ELT (trueop0
, INTVAL (XVECEXP (trueop1
, 0, 0)));
1581 if (!VECTOR_MODE_P (GET_MODE (trueop0
))
1582 || (GET_MODE_INNER (mode
)
1583 != GET_MODE_INNER (GET_MODE (trueop0
)))
1584 || GET_CODE (trueop1
) != PARALLEL
)
1587 if (GET_CODE (trueop0
) == CONST_VECTOR
)
1589 int elt_size
= GET_MODE_SIZE (GET_MODE_INNER (mode
));
1590 unsigned n_elts
= (GET_MODE_SIZE (mode
) / elt_size
);
1591 rtvec v
= rtvec_alloc (n_elts
);
1594 if (XVECLEN (trueop1
, 0) != (int) n_elts
)
1596 for (i
= 0; i
< n_elts
; i
++)
1598 rtx x
= XVECEXP (trueop1
, 0, i
);
1600 if (GET_CODE (x
) != CONST_INT
)
1602 RTVEC_ELT (v
, i
) = CONST_VECTOR_ELT (trueop0
, INTVAL (x
));
1605 return gen_rtx_CONST_VECTOR (mode
, v
);
1611 enum machine_mode op0_mode
= (GET_MODE (trueop0
) != VOIDmode
1612 ? GET_MODE (trueop0
)
1613 : GET_MODE_INNER (mode
));
1614 enum machine_mode op1_mode
= (GET_MODE (trueop1
) != VOIDmode
1615 ? GET_MODE (trueop1
)
1616 : GET_MODE_INNER (mode
));
1618 if (!VECTOR_MODE_P (mode
)
1619 || (GET_MODE_SIZE (op0_mode
) + GET_MODE_SIZE (op1_mode
)
1620 != GET_MODE_SIZE (mode
)))
1623 if ((VECTOR_MODE_P (op0_mode
)
1624 && (GET_MODE_INNER (mode
)
1625 != GET_MODE_INNER (op0_mode
)))
1626 || (!VECTOR_MODE_P (op0_mode
)
1627 && GET_MODE_INNER (mode
) != op0_mode
))
1630 if ((VECTOR_MODE_P (op1_mode
)
1631 && (GET_MODE_INNER (mode
)
1632 != GET_MODE_INNER (op1_mode
)))
1633 || (!VECTOR_MODE_P (op1_mode
)
1634 && GET_MODE_INNER (mode
) != op1_mode
))
1637 if ((GET_CODE (trueop0
) == CONST_VECTOR
1638 || GET_CODE (trueop0
) == CONST_INT
1639 || GET_CODE (trueop0
) == CONST_DOUBLE
)
1640 && (GET_CODE (trueop1
) == CONST_VECTOR
1641 || GET_CODE (trueop1
) == CONST_INT
1642 || GET_CODE (trueop1
) == CONST_DOUBLE
))
1644 int elt_size
= GET_MODE_SIZE (GET_MODE_INNER (mode
));
1645 unsigned n_elts
= (GET_MODE_SIZE (mode
) / elt_size
);
1646 rtvec v
= rtvec_alloc (n_elts
);
1648 unsigned in_n_elts
= 1;
1650 if (VECTOR_MODE_P (op0_mode
))
1651 in_n_elts
= (GET_MODE_SIZE (op0_mode
) / elt_size
);
1652 for (i
= 0; i
< n_elts
; i
++)
1656 if (!VECTOR_MODE_P (op0_mode
))
1657 RTVEC_ELT (v
, i
) = trueop0
;
1659 RTVEC_ELT (v
, i
) = CONST_VECTOR_ELT (trueop0
, i
);
1663 if (!VECTOR_MODE_P (op1_mode
))
1664 RTVEC_ELT (v
, i
) = trueop1
;
1666 RTVEC_ELT (v
, i
) = CONST_VECTOR_ELT (trueop1
,
1671 return gen_rtx_CONST_VECTOR (mode
, v
);
1683 /* Get the integer argument values in two forms:
1684 zero-extended in ARG0, ARG1 and sign-extended in ARG0S, ARG1S. */
1686 arg0
= INTVAL (trueop0
);
1687 arg1
= INTVAL (trueop1
);
1689 if (width
< HOST_BITS_PER_WIDE_INT
)
1691 arg0
&= ((HOST_WIDE_INT
) 1 << width
) - 1;
1692 arg1
&= ((HOST_WIDE_INT
) 1 << width
) - 1;
1695 if (arg0s
& ((HOST_WIDE_INT
) 1 << (width
- 1)))
1696 arg0s
|= ((HOST_WIDE_INT
) (-1) << width
);
1699 if (arg1s
& ((HOST_WIDE_INT
) 1 << (width
- 1)))
1700 arg1s
|= ((HOST_WIDE_INT
) (-1) << width
);
1708 /* Compute the value of the arithmetic. */
1713 val
= arg0s
+ arg1s
;
1717 val
= arg0s
- arg1s
;
1721 val
= arg0s
* arg1s
;
1726 || (arg0s
== (HOST_WIDE_INT
) 1 << (HOST_BITS_PER_WIDE_INT
- 1)
1729 val
= arg0s
/ arg1s
;
1734 || (arg0s
== (HOST_WIDE_INT
) 1 << (HOST_BITS_PER_WIDE_INT
- 1)
1737 val
= arg0s
% arg1s
;
1742 || (arg0s
== (HOST_WIDE_INT
) 1 << (HOST_BITS_PER_WIDE_INT
- 1)
1745 val
= (unsigned HOST_WIDE_INT
) arg0
/ arg1
;
1750 || (arg0s
== (HOST_WIDE_INT
) 1 << (HOST_BITS_PER_WIDE_INT
- 1)
1753 val
= (unsigned HOST_WIDE_INT
) arg0
% arg1
;
1769 /* If shift count is undefined, don't fold it; let the machine do
1770 what it wants. But truncate it if the machine will do that. */
1774 #ifdef SHIFT_COUNT_TRUNCATED
1775 if (SHIFT_COUNT_TRUNCATED
)
1779 val
= ((unsigned HOST_WIDE_INT
) arg0
) >> arg1
;
1786 #ifdef SHIFT_COUNT_TRUNCATED
1787 if (SHIFT_COUNT_TRUNCATED
)
1791 val
= ((unsigned HOST_WIDE_INT
) arg0
) << arg1
;
1798 #ifdef SHIFT_COUNT_TRUNCATED
1799 if (SHIFT_COUNT_TRUNCATED
)
1803 val
= arg0s
>> arg1
;
1805 /* Bootstrap compiler may not have sign extended the right shift.
1806 Manually extend the sign to insure bootstrap cc matches gcc. */
1807 if (arg0s
< 0 && arg1
> 0)
1808 val
|= ((HOST_WIDE_INT
) -1) << (HOST_BITS_PER_WIDE_INT
- arg1
);
1817 val
= ((((unsigned HOST_WIDE_INT
) arg0
) << (width
- arg1
))
1818 | (((unsigned HOST_WIDE_INT
) arg0
) >> arg1
));
1826 val
= ((((unsigned HOST_WIDE_INT
) arg0
) << arg1
)
1827 | (((unsigned HOST_WIDE_INT
) arg0
) >> (width
- arg1
)));
1831 /* Do nothing here. */
1835 val
= arg0s
<= arg1s
? arg0s
: arg1s
;
1839 val
= ((unsigned HOST_WIDE_INT
) arg0
1840 <= (unsigned HOST_WIDE_INT
) arg1
? arg0
: arg1
);
1844 val
= arg0s
> arg1s
? arg0s
: arg1s
;
1848 val
= ((unsigned HOST_WIDE_INT
) arg0
1849 > (unsigned HOST_WIDE_INT
) arg1
? arg0
: arg1
);
1856 /* ??? There are simplifications that can be done. */
1863 val
= trunc_int_for_mode (val
, mode
);
1865 return GEN_INT (val
);
1868 /* Simplify a PLUS or MINUS, at least one of whose operands may be another
1871 Rather than test for specific case, we do this by a brute-force method
1872 and do all possible simplifications until no more changes occur. Then
1873 we rebuild the operation.
1875 If FORCE is true, then always generate the rtx. This is used to
1876 canonicalize stuff emitted from simplify_gen_binary. Note that this
1877 can still fail if the rtx is too complex. It won't fail just because
1878 the result is not 'simpler' than the input, however. */
1880 struct simplify_plus_minus_op_data
1887 simplify_plus_minus_op_data_cmp (const void *p1
, const void *p2
)
1889 const struct simplify_plus_minus_op_data
*d1
= p1
;
1890 const struct simplify_plus_minus_op_data
*d2
= p2
;
1892 return (commutative_operand_precedence (d2
->op
)
1893 - commutative_operand_precedence (d1
->op
));
1897 simplify_plus_minus (enum rtx_code code
, enum machine_mode mode
, rtx op0
,
1900 struct simplify_plus_minus_op_data ops
[8];
1902 int n_ops
= 2, input_ops
= 2, input_consts
= 0, n_consts
;
1903 int first
, negate
, changed
;
1906 memset ((char *) ops
, 0, sizeof ops
);
1908 /* Set up the two operands and then expand them until nothing has been
1909 changed. If we run out of room in our array, give up; this should
1910 almost never happen. */
1915 ops
[1].neg
= (code
== MINUS
);
1921 for (i
= 0; i
< n_ops
; i
++)
1923 rtx this_op
= ops
[i
].op
;
1924 int this_neg
= ops
[i
].neg
;
1925 enum rtx_code this_code
= GET_CODE (this_op
);
1934 ops
[n_ops
].op
= XEXP (this_op
, 1);
1935 ops
[n_ops
].neg
= (this_code
== MINUS
) ^ this_neg
;
1938 ops
[i
].op
= XEXP (this_op
, 0);
1944 ops
[i
].op
= XEXP (this_op
, 0);
1945 ops
[i
].neg
= ! this_neg
;
1951 && GET_CODE (XEXP (this_op
, 0)) == PLUS
1952 && CONSTANT_P (XEXP (XEXP (this_op
, 0), 0))
1953 && CONSTANT_P (XEXP (XEXP (this_op
, 0), 1)))
1955 ops
[i
].op
= XEXP (XEXP (this_op
, 0), 0);
1956 ops
[n_ops
].op
= XEXP (XEXP (this_op
, 0), 1);
1957 ops
[n_ops
].neg
= this_neg
;
1965 /* ~a -> (-a - 1) */
1968 ops
[n_ops
].op
= constm1_rtx
;
1969 ops
[n_ops
++].neg
= this_neg
;
1970 ops
[i
].op
= XEXP (this_op
, 0);
1971 ops
[i
].neg
= !this_neg
;
1979 ops
[i
].op
= neg_const_int (mode
, this_op
);
1992 /* If we only have two operands, we can't do anything. */
1993 if (n_ops
<= 2 && !force
)
1996 /* Count the number of CONSTs we didn't split above. */
1997 for (i
= 0; i
< n_ops
; i
++)
1998 if (GET_CODE (ops
[i
].op
) == CONST
)
2001 /* Now simplify each pair of operands until nothing changes. The first
2002 time through just simplify constants against each other. */
2009 for (i
= 0; i
< n_ops
- 1; i
++)
2010 for (j
= i
+ 1; j
< n_ops
; j
++)
2012 rtx lhs
= ops
[i
].op
, rhs
= ops
[j
].op
;
2013 int lneg
= ops
[i
].neg
, rneg
= ops
[j
].neg
;
2015 if (lhs
!= 0 && rhs
!= 0
2016 && (! first
|| (CONSTANT_P (lhs
) && CONSTANT_P (rhs
))))
2018 enum rtx_code ncode
= PLUS
;
2024 tem
= lhs
, lhs
= rhs
, rhs
= tem
;
2026 else if (swap_commutative_operands_p (lhs
, rhs
))
2027 tem
= lhs
, lhs
= rhs
, rhs
= tem
;
2029 tem
= simplify_binary_operation (ncode
, mode
, lhs
, rhs
);
2031 /* Reject "simplifications" that just wrap the two
2032 arguments in a CONST. Failure to do so can result
2033 in infinite recursion with simplify_binary_operation
2034 when it calls us to simplify CONST operations. */
2036 && ! (GET_CODE (tem
) == CONST
2037 && GET_CODE (XEXP (tem
, 0)) == ncode
2038 && XEXP (XEXP (tem
, 0), 0) == lhs
2039 && XEXP (XEXP (tem
, 0), 1) == rhs
)
2040 /* Don't allow -x + -1 -> ~x simplifications in the
2041 first pass. This allows us the chance to combine
2042 the -1 with other constants. */
2044 && GET_CODE (tem
) == NOT
2045 && XEXP (tem
, 0) == rhs
))
2048 if (GET_CODE (tem
) == NEG
)
2049 tem
= XEXP (tem
, 0), lneg
= !lneg
;
2050 if (GET_CODE (tem
) == CONST_INT
&& lneg
)
2051 tem
= neg_const_int (mode
, tem
), lneg
= 0;
2055 ops
[j
].op
= NULL_RTX
;
2065 /* Pack all the operands to the lower-numbered entries. */
2066 for (i
= 0, j
= 0; j
< n_ops
; j
++)
2071 /* Sort the operations based on swap_commutative_operands_p. */
2072 qsort (ops
, n_ops
, sizeof (*ops
), simplify_plus_minus_op_data_cmp
);
2074 /* We suppressed creation of trivial CONST expressions in the
2075 combination loop to avoid recursion. Create one manually now.
2076 The combination loop should have ensured that there is exactly
2077 one CONST_INT, and the sort will have ensured that it is last
2078 in the array and that any other constant will be next-to-last. */
2081 && GET_CODE (ops
[n_ops
- 1].op
) == CONST_INT
2082 && CONSTANT_P (ops
[n_ops
- 2].op
))
2084 rtx value
= ops
[n_ops
- 1].op
;
2085 if (ops
[n_ops
- 1].neg
^ ops
[n_ops
- 2].neg
)
2086 value
= neg_const_int (mode
, value
);
2087 ops
[n_ops
- 2].op
= plus_constant (ops
[n_ops
- 2].op
, INTVAL (value
));
2091 /* Count the number of CONSTs that we generated. */
2093 for (i
= 0; i
< n_ops
; i
++)
2094 if (GET_CODE (ops
[i
].op
) == CONST
)
2097 /* Give up if we didn't reduce the number of operands we had. Make
2098 sure we count a CONST as two operands. If we have the same
2099 number of operands, but have made more CONSTs than before, this
2100 is also an improvement, so accept it. */
2102 && (n_ops
+ n_consts
> input_ops
2103 || (n_ops
+ n_consts
== input_ops
&& n_consts
<= input_consts
)))
2106 /* Put a non-negated operand first. If there aren't any, make all
2107 operands positive and negate the whole thing later. */
2110 for (i
= 0; i
< n_ops
&& ops
[i
].neg
; i
++)
2114 for (i
= 0; i
< n_ops
; i
++)
2126 /* Now make the result by performing the requested operations. */
2128 for (i
= 1; i
< n_ops
; i
++)
2129 result
= gen_rtx_fmt_ee (ops
[i
].neg
? MINUS
: PLUS
,
2130 mode
, result
, ops
[i
].op
);
2132 return negate
? gen_rtx_NEG (mode
, result
) : result
;
2135 /* Like simplify_binary_operation except used for relational operators.
2136 MODE is the mode of the operands, not that of the result. If MODE
2137 is VOIDmode, both operands must also be VOIDmode and we compare the
2138 operands in "infinite precision".
2140 If no simplification is possible, this function returns zero. Otherwise,
2141 it returns either const_true_rtx or const0_rtx. */
2144 simplify_relational_operation (enum rtx_code code
, enum machine_mode mode
,
2147 int equal
, op0lt
, op0ltu
, op1lt
, op1ltu
;
2152 if (mode
== VOIDmode
2153 && (GET_MODE (op0
) != VOIDmode
2154 || GET_MODE (op1
) != VOIDmode
))
2157 /* If op0 is a compare, extract the comparison arguments from it. */
2158 if (GET_CODE (op0
) == COMPARE
&& op1
== const0_rtx
)
2159 op1
= XEXP (op0
, 1), op0
= XEXP (op0
, 0);
2161 trueop0
= avoid_constant_pool_reference (op0
);
2162 trueop1
= avoid_constant_pool_reference (op1
);
2164 /* We can't simplify MODE_CC values since we don't know what the
2165 actual comparison is. */
2166 if (GET_MODE_CLASS (GET_MODE (op0
)) == MODE_CC
|| CC0_P (op0
))
2169 /* Make sure the constant is second. */
2170 if (swap_commutative_operands_p (trueop0
, trueop1
))
2172 tem
= op0
, op0
= op1
, op1
= tem
;
2173 tem
= trueop0
, trueop0
= trueop1
, trueop1
= tem
;
2174 code
= swap_condition (code
);
2177 /* For integer comparisons of A and B maybe we can simplify A - B and can
2178 then simplify a comparison of that with zero. If A and B are both either
2179 a register or a CONST_INT, this can't help; testing for these cases will
2180 prevent infinite recursion here and speed things up.
2182 If CODE is an unsigned comparison, then we can never do this optimization,
2183 because it gives an incorrect result if the subtraction wraps around zero.
2184 ANSI C defines unsigned operations such that they never overflow, and
2185 thus such cases can not be ignored. */
2187 if (INTEGRAL_MODE_P (mode
) && trueop1
!= const0_rtx
2188 && ! ((GET_CODE (op0
) == REG
|| GET_CODE (trueop0
) == CONST_INT
)
2189 && (GET_CODE (op1
) == REG
|| GET_CODE (trueop1
) == CONST_INT
))
2190 && 0 != (tem
= simplify_binary_operation (MINUS
, mode
, op0
, op1
))
2191 && code
!= GTU
&& code
!= GEU
&& code
!= LTU
&& code
!= LEU
)
2192 return simplify_relational_operation (signed_condition (code
),
2193 mode
, tem
, const0_rtx
);
2195 if (flag_unsafe_math_optimizations
&& code
== ORDERED
)
2196 return const_true_rtx
;
2198 if (flag_unsafe_math_optimizations
&& code
== UNORDERED
)
2201 /* For modes without NaNs, if the two operands are equal, we know the
2202 result except if they have side-effects. */
2203 if (! HONOR_NANS (GET_MODE (trueop0
))
2204 && rtx_equal_p (trueop0
, trueop1
)
2205 && ! side_effects_p (trueop0
))
2206 equal
= 1, op0lt
= 0, op0ltu
= 0, op1lt
= 0, op1ltu
= 0;
2208 /* If the operands are floating-point constants, see if we can fold
2210 else if (GET_CODE (trueop0
) == CONST_DOUBLE
2211 && GET_CODE (trueop1
) == CONST_DOUBLE
2212 && GET_MODE_CLASS (GET_MODE (trueop0
)) == MODE_FLOAT
)
2214 REAL_VALUE_TYPE d0
, d1
;
2216 REAL_VALUE_FROM_CONST_DOUBLE (d0
, trueop0
);
2217 REAL_VALUE_FROM_CONST_DOUBLE (d1
, trueop1
);
2219 /* Comparisons are unordered iff at least one of the values is NaN. */
2220 if (REAL_VALUE_ISNAN (d0
) || REAL_VALUE_ISNAN (d1
))
2230 return const_true_rtx
;
2243 equal
= REAL_VALUES_EQUAL (d0
, d1
);
2244 op0lt
= op0ltu
= REAL_VALUES_LESS (d0
, d1
);
2245 op1lt
= op1ltu
= REAL_VALUES_LESS (d1
, d0
);
2248 /* Otherwise, see if the operands are both integers. */
2249 else if ((GET_MODE_CLASS (mode
) == MODE_INT
|| mode
== VOIDmode
)
2250 && (GET_CODE (trueop0
) == CONST_DOUBLE
2251 || GET_CODE (trueop0
) == CONST_INT
)
2252 && (GET_CODE (trueop1
) == CONST_DOUBLE
2253 || GET_CODE (trueop1
) == CONST_INT
))
2255 int width
= GET_MODE_BITSIZE (mode
);
2256 HOST_WIDE_INT l0s
, h0s
, l1s
, h1s
;
2257 unsigned HOST_WIDE_INT l0u
, h0u
, l1u
, h1u
;
2259 /* Get the two words comprising each integer constant. */
2260 if (GET_CODE (trueop0
) == CONST_DOUBLE
)
2262 l0u
= l0s
= CONST_DOUBLE_LOW (trueop0
);
2263 h0u
= h0s
= CONST_DOUBLE_HIGH (trueop0
);
2267 l0u
= l0s
= INTVAL (trueop0
);
2268 h0u
= h0s
= HWI_SIGN_EXTEND (l0s
);
2271 if (GET_CODE (trueop1
) == CONST_DOUBLE
)
2273 l1u
= l1s
= CONST_DOUBLE_LOW (trueop1
);
2274 h1u
= h1s
= CONST_DOUBLE_HIGH (trueop1
);
2278 l1u
= l1s
= INTVAL (trueop1
);
2279 h1u
= h1s
= HWI_SIGN_EXTEND (l1s
);
2282 /* If WIDTH is nonzero and smaller than HOST_BITS_PER_WIDE_INT,
2283 we have to sign or zero-extend the values. */
2284 if (width
!= 0 && width
< HOST_BITS_PER_WIDE_INT
)
2286 l0u
&= ((HOST_WIDE_INT
) 1 << width
) - 1;
2287 l1u
&= ((HOST_WIDE_INT
) 1 << width
) - 1;
2289 if (l0s
& ((HOST_WIDE_INT
) 1 << (width
- 1)))
2290 l0s
|= ((HOST_WIDE_INT
) (-1) << width
);
2292 if (l1s
& ((HOST_WIDE_INT
) 1 << (width
- 1)))
2293 l1s
|= ((HOST_WIDE_INT
) (-1) << width
);
2295 if (width
!= 0 && width
<= HOST_BITS_PER_WIDE_INT
)
2296 h0u
= h1u
= 0, h0s
= HWI_SIGN_EXTEND (l0s
), h1s
= HWI_SIGN_EXTEND (l1s
);
2298 equal
= (h0u
== h1u
&& l0u
== l1u
);
2299 op0lt
= (h0s
< h1s
|| (h0s
== h1s
&& l0u
< l1u
));
2300 op1lt
= (h1s
< h0s
|| (h1s
== h0s
&& l1u
< l0u
));
2301 op0ltu
= (h0u
< h1u
|| (h0u
== h1u
&& l0u
< l1u
));
2302 op1ltu
= (h1u
< h0u
|| (h1u
== h0u
&& l1u
< l0u
));
2305 /* Otherwise, there are some code-specific tests we can make. */
2311 if (trueop1
== const0_rtx
&& nonzero_address_p (op0
))
2316 if (trueop1
== const0_rtx
&& nonzero_address_p (op0
))
2317 return const_true_rtx
;
2321 /* Unsigned values are never negative. */
2322 if (trueop1
== const0_rtx
)
2323 return const_true_rtx
;
2327 if (trueop1
== const0_rtx
)
2332 /* Unsigned values are never greater than the largest
2334 if (GET_CODE (trueop1
) == CONST_INT
2335 && (unsigned HOST_WIDE_INT
) INTVAL (trueop1
) == GET_MODE_MASK (mode
)
2336 && INTEGRAL_MODE_P (mode
))
2337 return const_true_rtx
;
2341 if (GET_CODE (trueop1
) == CONST_INT
2342 && (unsigned HOST_WIDE_INT
) INTVAL (trueop1
) == GET_MODE_MASK (mode
)
2343 && INTEGRAL_MODE_P (mode
))
2348 /* Optimize abs(x) < 0.0. */
2349 if (trueop1
== CONST0_RTX (mode
) && !HONOR_SNANS (mode
))
2351 tem
= GET_CODE (trueop0
) == FLOAT_EXTEND
? XEXP (trueop0
, 0)
2353 if (GET_CODE (tem
) == ABS
)
2359 /* Optimize abs(x) >= 0.0. */
2360 if (trueop1
== CONST0_RTX (mode
) && !HONOR_NANS (mode
))
2362 tem
= GET_CODE (trueop0
) == FLOAT_EXTEND
? XEXP (trueop0
, 0)
2364 if (GET_CODE (tem
) == ABS
)
2365 return const_true_rtx
;
2370 /* Optimize ! (abs(x) < 0.0). */
2371 if (trueop1
== CONST0_RTX (mode
))
2373 tem
= GET_CODE (trueop0
) == FLOAT_EXTEND
? XEXP (trueop0
, 0)
2375 if (GET_CODE (tem
) == ABS
)
2376 return const_true_rtx
;
2387 /* If we reach here, EQUAL, OP0LT, OP0LTU, OP1LT, and OP1LTU are set
2393 return equal
? const_true_rtx
: const0_rtx
;
2396 return ! equal
? const_true_rtx
: const0_rtx
;
2399 return op0lt
? const_true_rtx
: const0_rtx
;
2402 return op1lt
? const_true_rtx
: const0_rtx
;
2404 return op0ltu
? const_true_rtx
: const0_rtx
;
2406 return op1ltu
? const_true_rtx
: const0_rtx
;
2409 return equal
|| op0lt
? const_true_rtx
: const0_rtx
;
2412 return equal
|| op1lt
? const_true_rtx
: const0_rtx
;
2414 return equal
|| op0ltu
? const_true_rtx
: const0_rtx
;
2416 return equal
|| op1ltu
? const_true_rtx
: const0_rtx
;
2418 return const_true_rtx
;
2426 /* Simplify CODE, an operation with result mode MODE and three operands,
2427 OP0, OP1, and OP2. OP0_MODE was the mode of OP0 before it became
2428 a constant. Return 0 if no simplifications is possible. */
2431 simplify_ternary_operation (enum rtx_code code
, enum machine_mode mode
,
2432 enum machine_mode op0_mode
, rtx op0
, rtx op1
,
2435 unsigned int width
= GET_MODE_BITSIZE (mode
);
2437 /* VOIDmode means "infinite" precision. */
2439 width
= HOST_BITS_PER_WIDE_INT
;
2445 if (GET_CODE (op0
) == CONST_INT
2446 && GET_CODE (op1
) == CONST_INT
2447 && GET_CODE (op2
) == CONST_INT
2448 && ((unsigned) INTVAL (op1
) + (unsigned) INTVAL (op2
) <= width
)
2449 && width
<= (unsigned) HOST_BITS_PER_WIDE_INT
)
2451 /* Extracting a bit-field from a constant */
2452 HOST_WIDE_INT val
= INTVAL (op0
);
2454 if (BITS_BIG_ENDIAN
)
2455 val
>>= (GET_MODE_BITSIZE (op0_mode
)
2456 - INTVAL (op2
) - INTVAL (op1
));
2458 val
>>= INTVAL (op2
);
2460 if (HOST_BITS_PER_WIDE_INT
!= INTVAL (op1
))
2462 /* First zero-extend. */
2463 val
&= ((HOST_WIDE_INT
) 1 << INTVAL (op1
)) - 1;
2464 /* If desired, propagate sign bit. */
2465 if (code
== SIGN_EXTRACT
2466 && (val
& ((HOST_WIDE_INT
) 1 << (INTVAL (op1
) - 1))))
2467 val
|= ~ (((HOST_WIDE_INT
) 1 << INTVAL (op1
)) - 1);
2470 /* Clear the bits that don't belong in our mode,
2471 unless they and our sign bit are all one.
2472 So we get either a reasonable negative value or a reasonable
2473 unsigned value for this mode. */
2474 if (width
< HOST_BITS_PER_WIDE_INT
2475 && ((val
& ((HOST_WIDE_INT
) (-1) << (width
- 1)))
2476 != ((HOST_WIDE_INT
) (-1) << (width
- 1))))
2477 val
&= ((HOST_WIDE_INT
) 1 << width
) - 1;
2479 return GEN_INT (val
);
2484 if (GET_CODE (op0
) == CONST_INT
)
2485 return op0
!= const0_rtx
? op1
: op2
;
2487 /* Convert a == b ? b : a to "a". */
2488 if (GET_CODE (op0
) == NE
&& ! side_effects_p (op0
)
2489 && !HONOR_NANS (mode
)
2490 && rtx_equal_p (XEXP (op0
, 0), op1
)
2491 && rtx_equal_p (XEXP (op0
, 1), op2
))
2493 else if (GET_CODE (op0
) == EQ
&& ! side_effects_p (op0
)
2494 && !HONOR_NANS (mode
)
2495 && rtx_equal_p (XEXP (op0
, 1), op1
)
2496 && rtx_equal_p (XEXP (op0
, 0), op2
))
2498 else if (GET_RTX_CLASS (GET_CODE (op0
)) == '<' && ! side_effects_p (op0
))
2500 enum machine_mode cmp_mode
= (GET_MODE (XEXP (op0
, 0)) == VOIDmode
2501 ? GET_MODE (XEXP (op0
, 1))
2502 : GET_MODE (XEXP (op0
, 0)));
2504 if (cmp_mode
== VOIDmode
)
2505 cmp_mode
= op0_mode
;
2506 temp
= simplify_relational_operation (GET_CODE (op0
), cmp_mode
,
2507 XEXP (op0
, 0), XEXP (op0
, 1));
2509 /* See if any simplifications were possible. */
2510 if (temp
== const0_rtx
)
2512 else if (temp
== const1_rtx
)
2517 /* Look for happy constants in op1 and op2. */
2518 if (GET_CODE (op1
) == CONST_INT
&& GET_CODE (op2
) == CONST_INT
)
2520 HOST_WIDE_INT t
= INTVAL (op1
);
2521 HOST_WIDE_INT f
= INTVAL (op2
);
2523 if (t
== STORE_FLAG_VALUE
&& f
== 0)
2524 code
= GET_CODE (op0
);
2525 else if (t
== 0 && f
== STORE_FLAG_VALUE
)
2528 tmp
= reversed_comparison_code (op0
, NULL_RTX
);
2536 return gen_rtx_fmt_ee (code
, mode
, XEXP (op0
, 0), XEXP (op0
, 1));
2541 if (GET_MODE (op0
) != mode
2542 || GET_MODE (op1
) != mode
2543 || !VECTOR_MODE_P (mode
))
2545 op2
= avoid_constant_pool_reference (op2
);
2546 if (GET_CODE (op2
) == CONST_INT
)
2548 int elt_size
= GET_MODE_SIZE (GET_MODE_INNER (mode
));
2549 unsigned n_elts
= (GET_MODE_SIZE (mode
) / elt_size
);
2550 int mask
= (1 << n_elts
) - 1;
2552 if (!(INTVAL (op2
) & mask
))
2554 if ((INTVAL (op2
) & mask
) == mask
)
2557 op0
= avoid_constant_pool_reference (op0
);
2558 op1
= avoid_constant_pool_reference (op1
);
2559 if (GET_CODE (op0
) == CONST_VECTOR
2560 && GET_CODE (op1
) == CONST_VECTOR
)
2562 rtvec v
= rtvec_alloc (n_elts
);
2565 for (i
= 0; i
< n_elts
; i
++)
2566 RTVEC_ELT (v
, i
) = (INTVAL (op2
) & (1 << i
)
2567 ? CONST_VECTOR_ELT (op0
, i
)
2568 : CONST_VECTOR_ELT (op1
, i
));
2569 return gen_rtx_CONST_VECTOR (mode
, v
);
2581 /* Simplify SUBREG:OUTERMODE(OP:INNERMODE, BYTE)
2582 Return 0 if no simplifications is possible. */
2584 simplify_subreg (enum machine_mode outermode
, rtx op
,
2585 enum machine_mode innermode
, unsigned int byte
)
2587 /* Little bit of sanity checking. */
2588 if (innermode
== VOIDmode
|| outermode
== VOIDmode
2589 || innermode
== BLKmode
|| outermode
== BLKmode
)
2592 if (GET_MODE (op
) != innermode
2593 && GET_MODE (op
) != VOIDmode
)
2596 if (byte
% GET_MODE_SIZE (outermode
)
2597 || byte
>= GET_MODE_SIZE (innermode
))
2600 if (outermode
== innermode
&& !byte
)
2603 /* Simplify subregs of vector constants. */
2604 if (GET_CODE (op
) == CONST_VECTOR
)
2606 int elt_size
= GET_MODE_SIZE (GET_MODE_INNER (innermode
));
2607 const unsigned int offset
= byte
/ elt_size
;
2610 if (GET_MODE_INNER (innermode
) == outermode
)
2612 elt
= CONST_VECTOR_ELT (op
, offset
);
2614 /* ?? We probably don't need this copy_rtx because constants
2615 can be shared. ?? */
2617 return copy_rtx (elt
);
2619 else if (GET_MODE_INNER (innermode
) == GET_MODE_INNER (outermode
)
2620 && GET_MODE_SIZE (innermode
) > GET_MODE_SIZE (outermode
))
2622 return (gen_rtx_CONST_VECTOR
2624 gen_rtvec_v (GET_MODE_NUNITS (outermode
),
2625 &CONST_VECTOR_ELT (op
, offset
))));
2627 else if (GET_MODE_CLASS (outermode
) == MODE_INT
2628 && (GET_MODE_SIZE (outermode
) % elt_size
== 0))
2630 /* This happens when the target register size is smaller then
2631 the vector mode, and we synthesize operations with vectors
2632 of elements that are smaller than the register size. */
2633 HOST_WIDE_INT sum
= 0, high
= 0;
2634 unsigned n_elts
= (GET_MODE_SIZE (outermode
) / elt_size
);
2635 unsigned i
= BYTES_BIG_ENDIAN
? offset
: offset
+ n_elts
- 1;
2636 unsigned step
= BYTES_BIG_ENDIAN
? 1 : -1;
2637 int shift
= BITS_PER_UNIT
* elt_size
;
2638 unsigned HOST_WIDE_INT unit_mask
;
2640 unit_mask
= (unsigned HOST_WIDE_INT
) -1
2641 >> (sizeof (HOST_WIDE_INT
) * BITS_PER_UNIT
- shift
);
2643 for (; n_elts
--; i
+= step
)
2645 elt
= CONST_VECTOR_ELT (op
, i
);
2646 if (GET_CODE (elt
) == CONST_DOUBLE
2647 && GET_MODE_CLASS (GET_MODE (elt
)) == MODE_FLOAT
)
2649 elt
= gen_lowpart_common (int_mode_for_mode (GET_MODE (elt
)),
2654 if (GET_CODE (elt
) != CONST_INT
)
2656 /* Avoid overflow. */
2657 if (high
>> (HOST_BITS_PER_WIDE_INT
- shift
))
2659 high
= high
<< shift
| sum
>> (HOST_BITS_PER_WIDE_INT
- shift
);
2660 sum
= (sum
<< shift
) + (INTVAL (elt
) & unit_mask
);
2662 if (GET_MODE_BITSIZE (outermode
) <= HOST_BITS_PER_WIDE_INT
)
2663 return GEN_INT (trunc_int_for_mode (sum
, outermode
));
2664 else if (GET_MODE_BITSIZE (outermode
) == 2* HOST_BITS_PER_WIDE_INT
)
2665 return immed_double_const (sum
, high
, outermode
);
2669 else if (GET_MODE_CLASS (outermode
) == MODE_INT
2670 && (elt_size
% GET_MODE_SIZE (outermode
) == 0))
2672 enum machine_mode new_mode
2673 = int_mode_for_mode (GET_MODE_INNER (innermode
));
2674 int subbyte
= byte
% elt_size
;
2676 op
= simplify_subreg (new_mode
, op
, innermode
, byte
- subbyte
);
2679 return simplify_subreg (outermode
, op
, new_mode
, subbyte
);
2681 else if (GET_MODE_CLASS (outermode
) == MODE_INT
)
2682 /* This shouldn't happen, but let's not do anything stupid. */
2686 /* Attempt to simplify constant to non-SUBREG expression. */
2687 if (CONSTANT_P (op
))
2690 unsigned HOST_WIDE_INT val
= 0;
2692 if (VECTOR_MODE_P (outermode
))
2694 /* Construct a CONST_VECTOR from individual subregs. */
2695 enum machine_mode submode
= GET_MODE_INNER (outermode
);
2696 int subsize
= GET_MODE_UNIT_SIZE (outermode
);
2697 int i
, elts
= GET_MODE_NUNITS (outermode
);
2698 rtvec v
= rtvec_alloc (elts
);
2701 for (i
= 0; i
< elts
; i
++, byte
+= subsize
)
2703 /* This might fail, e.g. if taking a subreg from a SYMBOL_REF. */
2704 /* ??? It would be nice if we could actually make such subregs
2705 on targets that allow such relocations. */
2706 if (byte
>= GET_MODE_SIZE (innermode
))
2707 elt
= CONST0_RTX (submode
);
2709 elt
= simplify_subreg (submode
, op
, innermode
, byte
);
2712 RTVEC_ELT (v
, i
) = elt
;
2714 return gen_rtx_CONST_VECTOR (outermode
, v
);
2717 /* ??? This code is partly redundant with code below, but can handle
2718 the subregs of floats and similar corner cases.
2719 Later it we should move all simplification code here and rewrite
2720 GEN_LOWPART_IF_POSSIBLE, GEN_HIGHPART, OPERAND_SUBWORD and friends
2721 using SIMPLIFY_SUBREG. */
2722 if (subreg_lowpart_offset (outermode
, innermode
) == byte
2723 && GET_CODE (op
) != CONST_VECTOR
)
2725 rtx
new = gen_lowpart_if_possible (outermode
, op
);
2730 /* Similar comment as above apply here. */
2731 if (GET_MODE_SIZE (outermode
) == UNITS_PER_WORD
2732 && GET_MODE_SIZE (innermode
) > UNITS_PER_WORD
2733 && GET_MODE_CLASS (outermode
) == MODE_INT
)
2735 rtx
new = constant_subword (op
,
2736 (byte
/ UNITS_PER_WORD
),
2742 if (GET_MODE_CLASS (outermode
) != MODE_INT
2743 && GET_MODE_CLASS (outermode
) != MODE_CC
)
2745 enum machine_mode new_mode
= int_mode_for_mode (outermode
);
2747 if (new_mode
!= innermode
|| byte
!= 0)
2749 op
= simplify_subreg (new_mode
, op
, innermode
, byte
);
2752 return simplify_subreg (outermode
, op
, new_mode
, 0);
2756 offset
= byte
* BITS_PER_UNIT
;
2757 switch (GET_CODE (op
))
2760 if (GET_MODE (op
) != VOIDmode
)
2763 /* We can't handle this case yet. */
2764 if (GET_MODE_BITSIZE (outermode
) >= HOST_BITS_PER_WIDE_INT
)
2767 part
= offset
>= HOST_BITS_PER_WIDE_INT
;
2768 if ((BITS_PER_WORD
> HOST_BITS_PER_WIDE_INT
2769 && BYTES_BIG_ENDIAN
)
2770 || (BITS_PER_WORD
<= HOST_BITS_PER_WIDE_INT
2771 && WORDS_BIG_ENDIAN
))
2773 val
= part
? CONST_DOUBLE_HIGH (op
) : CONST_DOUBLE_LOW (op
);
2774 offset
%= HOST_BITS_PER_WIDE_INT
;
2776 /* We've already picked the word we want from a double, so
2777 pretend this is actually an integer. */
2778 innermode
= mode_for_size (HOST_BITS_PER_WIDE_INT
, MODE_INT
, 0);
2782 if (GET_CODE (op
) == CONST_INT
)
2785 /* We don't handle synthesizing of non-integral constants yet. */
2786 if (GET_MODE_CLASS (outermode
) != MODE_INT
)
2789 if (BYTES_BIG_ENDIAN
|| WORDS_BIG_ENDIAN
)
2791 if (WORDS_BIG_ENDIAN
)
2792 offset
= (GET_MODE_BITSIZE (innermode
)
2793 - GET_MODE_BITSIZE (outermode
) - offset
);
2794 if (BYTES_BIG_ENDIAN
!= WORDS_BIG_ENDIAN
2795 && GET_MODE_SIZE (outermode
) < UNITS_PER_WORD
)
2796 offset
= (offset
+ BITS_PER_WORD
- GET_MODE_BITSIZE (outermode
)
2797 - 2 * (offset
% BITS_PER_WORD
));
2800 if (offset
>= HOST_BITS_PER_WIDE_INT
)
2801 return ((HOST_WIDE_INT
) val
< 0) ? constm1_rtx
: const0_rtx
;
2805 if (GET_MODE_BITSIZE (outermode
) < HOST_BITS_PER_WIDE_INT
)
2806 val
= trunc_int_for_mode (val
, outermode
);
2807 return GEN_INT (val
);
2814 /* Changing mode twice with SUBREG => just change it once,
2815 or not at all if changing back op starting mode. */
2816 if (GET_CODE (op
) == SUBREG
)
2818 enum machine_mode innermostmode
= GET_MODE (SUBREG_REG (op
));
2819 int final_offset
= byte
+ SUBREG_BYTE (op
);
2822 if (outermode
== innermostmode
2823 && byte
== 0 && SUBREG_BYTE (op
) == 0)
2824 return SUBREG_REG (op
);
2826 /* The SUBREG_BYTE represents offset, as if the value were stored
2827 in memory. Irritating exception is paradoxical subreg, where
2828 we define SUBREG_BYTE to be 0. On big endian machines, this
2829 value should be negative. For a moment, undo this exception. */
2830 if (byte
== 0 && GET_MODE_SIZE (innermode
) < GET_MODE_SIZE (outermode
))
2832 int difference
= (GET_MODE_SIZE (innermode
) - GET_MODE_SIZE (outermode
));
2833 if (WORDS_BIG_ENDIAN
)
2834 final_offset
+= (difference
/ UNITS_PER_WORD
) * UNITS_PER_WORD
;
2835 if (BYTES_BIG_ENDIAN
)
2836 final_offset
+= difference
% UNITS_PER_WORD
;
2838 if (SUBREG_BYTE (op
) == 0
2839 && GET_MODE_SIZE (innermostmode
) < GET_MODE_SIZE (innermode
))
2841 int difference
= (GET_MODE_SIZE (innermostmode
) - GET_MODE_SIZE (innermode
));
2842 if (WORDS_BIG_ENDIAN
)
2843 final_offset
+= (difference
/ UNITS_PER_WORD
) * UNITS_PER_WORD
;
2844 if (BYTES_BIG_ENDIAN
)
2845 final_offset
+= difference
% UNITS_PER_WORD
;
2848 /* See whether resulting subreg will be paradoxical. */
2849 if (GET_MODE_SIZE (innermostmode
) > GET_MODE_SIZE (outermode
))
2851 /* In nonparadoxical subregs we can't handle negative offsets. */
2852 if (final_offset
< 0)
2854 /* Bail out in case resulting subreg would be incorrect. */
2855 if (final_offset
% GET_MODE_SIZE (outermode
)
2856 || (unsigned) final_offset
>= GET_MODE_SIZE (innermostmode
))
2862 int difference
= (GET_MODE_SIZE (innermostmode
) - GET_MODE_SIZE (outermode
));
2864 /* In paradoxical subreg, see if we are still looking on lower part.
2865 If so, our SUBREG_BYTE will be 0. */
2866 if (WORDS_BIG_ENDIAN
)
2867 offset
+= (difference
/ UNITS_PER_WORD
) * UNITS_PER_WORD
;
2868 if (BYTES_BIG_ENDIAN
)
2869 offset
+= difference
% UNITS_PER_WORD
;
2870 if (offset
== final_offset
)
2876 /* Recurse for further possible simplifications. */
2877 new = simplify_subreg (outermode
, SUBREG_REG (op
),
2878 GET_MODE (SUBREG_REG (op
)),
2882 return gen_rtx_SUBREG (outermode
, SUBREG_REG (op
), final_offset
);
2885 /* SUBREG of a hard register => just change the register number
2886 and/or mode. If the hard register is not valid in that mode,
2887 suppress this simplification. If the hard register is the stack,
2888 frame, or argument pointer, leave this as a SUBREG. */
2891 && (! REG_FUNCTION_VALUE_P (op
)
2892 || ! rtx_equal_function_value_matters
)
2893 && REGNO (op
) < FIRST_PSEUDO_REGISTER
2894 #ifdef CANNOT_CHANGE_MODE_CLASS
2895 && ! (REG_CANNOT_CHANGE_MODE_P (REGNO (op
), innermode
, outermode
)
2896 && GET_MODE_CLASS (innermode
) != MODE_COMPLEX_INT
2897 && GET_MODE_CLASS (innermode
) != MODE_COMPLEX_FLOAT
)
2899 && ((reload_completed
&& !frame_pointer_needed
)
2900 || (REGNO (op
) != FRAME_POINTER_REGNUM
2901 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
2902 && REGNO (op
) != HARD_FRAME_POINTER_REGNUM
2905 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
2906 && REGNO (op
) != ARG_POINTER_REGNUM
2908 && REGNO (op
) != STACK_POINTER_REGNUM
)
2910 int final_regno
= subreg_hard_regno (gen_rtx_SUBREG (outermode
, op
, byte
),
2913 /* ??? We do allow it if the current REG is not valid for
2914 its mode. This is a kludge to work around how float/complex
2915 arguments are passed on 32-bit SPARC and should be fixed. */
2916 if (HARD_REGNO_MODE_OK (final_regno
, outermode
)
2917 || ! HARD_REGNO_MODE_OK (REGNO (op
), innermode
))
2919 rtx x
= gen_rtx_REG_offset (op
, outermode
, final_regno
, byte
);
2921 /* Propagate original regno. We don't have any way to specify
2922 the offset inside original regno, so do so only for lowpart.
2923 The information is used only by alias analysis that can not
2924 grog partial register anyway. */
2926 if (subreg_lowpart_offset (outermode
, innermode
) == byte
)
2927 ORIGINAL_REGNO (x
) = ORIGINAL_REGNO (op
);
2932 /* If we have a SUBREG of a register that we are replacing and we are
2933 replacing it with a MEM, make a new MEM and try replacing the
2934 SUBREG with it. Don't do this if the MEM has a mode-dependent address
2935 or if we would be widening it. */
2937 if (GET_CODE (op
) == MEM
2938 && ! mode_dependent_address_p (XEXP (op
, 0))
2939 /* Allow splitting of volatile memory references in case we don't
2940 have instruction to move the whole thing. */
2941 && (! MEM_VOLATILE_P (op
)
2942 || ! have_insn_for (SET
, innermode
))
2943 && GET_MODE_SIZE (outermode
) <= GET_MODE_SIZE (GET_MODE (op
)))
2944 return adjust_address_nv (op
, outermode
, byte
);
2946 /* Handle complex values represented as CONCAT
2947 of real and imaginary part. */
2948 if (GET_CODE (op
) == CONCAT
)
2950 int is_realpart
= byte
< GET_MODE_UNIT_SIZE (innermode
);
2951 rtx part
= is_realpart
? XEXP (op
, 0) : XEXP (op
, 1);
2952 unsigned int final_offset
;
2955 final_offset
= byte
% (GET_MODE_UNIT_SIZE (innermode
));
2956 res
= simplify_subreg (outermode
, part
, GET_MODE (part
), final_offset
);
2959 /* We can at least simplify it by referring directly to the relevant part. */
2960 return gen_rtx_SUBREG (outermode
, part
, final_offset
);
2965 /* Make a SUBREG operation or equivalent if it folds. */
2968 simplify_gen_subreg (enum machine_mode outermode
, rtx op
,
2969 enum machine_mode innermode
, unsigned int byte
)
2972 /* Little bit of sanity checking. */
2973 if (innermode
== VOIDmode
|| outermode
== VOIDmode
2974 || innermode
== BLKmode
|| outermode
== BLKmode
)
2977 if (GET_MODE (op
) != innermode
2978 && GET_MODE (op
) != VOIDmode
)
2981 if (byte
% GET_MODE_SIZE (outermode
)
2982 || byte
>= GET_MODE_SIZE (innermode
))
2985 if (GET_CODE (op
) == QUEUED
)
2988 new = simplify_subreg (outermode
, op
, innermode
, byte
);
2992 if (GET_CODE (op
) == SUBREG
|| GET_MODE (op
) == VOIDmode
)
2995 return gen_rtx_SUBREG (outermode
, op
, byte
);
2997 /* Simplify X, an rtx expression.
2999 Return the simplified expression or NULL if no simplifications
3002 This is the preferred entry point into the simplification routines;
3003 however, we still allow passes to call the more specific routines.
3005 Right now GCC has three (yes, three) major bodies of RTL simplification
3006 code that need to be unified.
3008 1. fold_rtx in cse.c. This code uses various CSE specific
3009 information to aid in RTL simplification.
3011 2. simplify_rtx in combine.c. Similar to fold_rtx, except that
3012 it uses combine specific information to aid in RTL
3015 3. The routines in this file.
3018 Long term we want to only have one body of simplification code; to
3019 get to that state I recommend the following steps:
3021 1. Pour over fold_rtx & simplify_rtx and move any simplifications
3022 which are not pass dependent state into these routines.
3024 2. As code is moved by #1, change fold_rtx & simplify_rtx to
3025 use this routine whenever possible.
3027 3. Allow for pass dependent state to be provided to these
3028 routines and add simplifications based on the pass dependent
3029 state. Remove code from cse.c & combine.c that becomes
3032 It will take time, but ultimately the compiler will be easier to
3033 maintain and improve. It's totally silly that when we add a
3034 simplification that it needs to be added to 4 places (3 for RTL
3035 simplification and 1 for tree simplification. */
3038 simplify_rtx (rtx x
)
3040 enum rtx_code code
= GET_CODE (x
);
3041 enum machine_mode mode
= GET_MODE (x
);
3044 switch (GET_RTX_CLASS (code
))
3047 return simplify_unary_operation (code
, mode
,
3048 XEXP (x
, 0), GET_MODE (XEXP (x
, 0)));
3050 if (swap_commutative_operands_p (XEXP (x
, 0), XEXP (x
, 1)))
3055 XEXP (x
, 0) = XEXP (x
, 1);
3057 return simplify_binary_operation (code
, mode
,
3058 XEXP (x
, 0), XEXP (x
, 1));
3062 return simplify_binary_operation (code
, mode
, XEXP (x
, 0), XEXP (x
, 1));
3066 return simplify_ternary_operation (code
, mode
, GET_MODE (XEXP (x
, 0)),
3067 XEXP (x
, 0), XEXP (x
, 1),
3071 temp
= simplify_relational_operation (code
,
3072 ((GET_MODE (XEXP (x
, 0))
3074 ? GET_MODE (XEXP (x
, 0))
3075 : GET_MODE (XEXP (x
, 1))),
3076 XEXP (x
, 0), XEXP (x
, 1));
3077 #ifdef FLOAT_STORE_FLAG_VALUE
3078 if (temp
!= 0 && GET_MODE_CLASS (mode
) == MODE_FLOAT
)
3080 if (temp
== const0_rtx
)
3081 temp
= CONST0_RTX (mode
);
3083 temp
= CONST_DOUBLE_FROM_REAL_VALUE (FLOAT_STORE_FLAG_VALUE (mode
),
3091 return simplify_gen_subreg (mode
, SUBREG_REG (x
),
3092 GET_MODE (SUBREG_REG (x
)),
3094 if (code
== CONSTANT_P_RTX
)
3096 if (CONSTANT_P (XEXP (x
, 0)))
3104 /* Convert (lo_sum (high FOO) FOO) to FOO. */
3105 if (GET_CODE (XEXP (x
, 0)) == HIGH
3106 && rtx_equal_p (XEXP (XEXP (x
, 0), 0), XEXP (x
, 1)))