1 /* RTL simplification functions for GNU compiler.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 3, or (at your option) any later
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
25 #include "coretypes.h"
31 #include "hard-reg-set.h"
34 #include "insn-config.h"
43 /* Simplification and canonicalization of RTL. */
45 /* Much code operates on (low, high) pairs; the low value is an
46 unsigned wide int, the high value a signed wide int. We
47 occasionally need to sign extend from low to high as if low were a
49 #define HWI_SIGN_EXTEND(low) \
50 ((((HOST_WIDE_INT) low) < 0) ? ((HOST_WIDE_INT) -1) : ((HOST_WIDE_INT) 0))
52 static rtx
neg_const_int (enum machine_mode
, const_rtx
);
53 static bool plus_minus_operand_p (const_rtx
);
54 static bool simplify_plus_minus_op_data_cmp (rtx
, rtx
);
55 static rtx
simplify_plus_minus (enum rtx_code
, enum machine_mode
, rtx
, rtx
);
56 static rtx
simplify_immed_subreg (enum machine_mode
, rtx
, enum machine_mode
,
58 static rtx
simplify_associative_operation (enum rtx_code
, enum machine_mode
,
60 static rtx
simplify_relational_operation_1 (enum rtx_code
, enum machine_mode
,
61 enum machine_mode
, rtx
, rtx
);
62 static rtx
simplify_unary_operation_1 (enum rtx_code
, enum machine_mode
, rtx
);
63 static rtx
simplify_binary_operation_1 (enum rtx_code
, enum machine_mode
,
66 /* Negate a CONST_INT rtx, truncating (because a conversion from a
67 maximally negative number can overflow). */
69 neg_const_int (enum machine_mode mode
, const_rtx i
)
71 return gen_int_mode (- INTVAL (i
), mode
);
74 /* Test whether expression, X, is an immediate constant that represents
75 the most significant bit of machine mode MODE. */
78 mode_signbit_p (enum machine_mode mode
, const_rtx x
)
80 unsigned HOST_WIDE_INT val
;
83 if (GET_MODE_CLASS (mode
) != MODE_INT
)
86 width
= GET_MODE_BITSIZE (mode
);
90 if (width
<= HOST_BITS_PER_WIDE_INT
91 && GET_CODE (x
) == CONST_INT
)
93 else if (width
<= 2 * HOST_BITS_PER_WIDE_INT
94 && GET_CODE (x
) == CONST_DOUBLE
95 && CONST_DOUBLE_LOW (x
) == 0)
97 val
= CONST_DOUBLE_HIGH (x
);
98 width
-= HOST_BITS_PER_WIDE_INT
;
103 if (width
< HOST_BITS_PER_WIDE_INT
)
104 val
&= ((unsigned HOST_WIDE_INT
) 1 << width
) - 1;
105 return val
== ((unsigned HOST_WIDE_INT
) 1 << (width
- 1));
108 /* Make a binary operation by properly ordering the operands and
109 seeing if the expression folds. */
112 simplify_gen_binary (enum rtx_code code
, enum machine_mode mode
, rtx op0
,
117 /* If this simplifies, do it. */
118 tem
= simplify_binary_operation (code
, mode
, op0
, op1
);
122 /* Put complex operands first and constants second if commutative. */
123 if (GET_RTX_CLASS (code
) == RTX_COMM_ARITH
124 && swap_commutative_operands_p (op0
, op1
))
125 tem
= op0
, op0
= op1
, op1
= tem
;
127 return gen_rtx_fmt_ee (code
, mode
, op0
, op1
);
130 /* If X is a MEM referencing the constant pool, return the real value.
131 Otherwise return X. */
133 avoid_constant_pool_reference (rtx x
)
136 enum machine_mode cmode
;
137 HOST_WIDE_INT offset
= 0;
139 switch (GET_CODE (x
))
145 /* Handle float extensions of constant pool references. */
147 c
= avoid_constant_pool_reference (tmp
);
148 if (c
!= tmp
&& GET_CODE (c
) == CONST_DOUBLE
)
152 REAL_VALUE_FROM_CONST_DOUBLE (d
, c
);
153 return CONST_DOUBLE_FROM_REAL_VALUE (d
, GET_MODE (x
));
161 if (GET_MODE (x
) == BLKmode
)
166 /* Call target hook to avoid the effects of -fpic etc.... */
167 addr
= targetm
.delegitimize_address (addr
);
169 /* Split the address into a base and integer offset. */
170 if (GET_CODE (addr
) == CONST
171 && GET_CODE (XEXP (addr
, 0)) == PLUS
172 && GET_CODE (XEXP (XEXP (addr
, 0), 1)) == CONST_INT
)
174 offset
= INTVAL (XEXP (XEXP (addr
, 0), 1));
175 addr
= XEXP (XEXP (addr
, 0), 0);
178 if (GET_CODE (addr
) == LO_SUM
)
179 addr
= XEXP (addr
, 1);
181 /* If this is a constant pool reference, we can turn it into its
182 constant and hope that simplifications happen. */
183 if (GET_CODE (addr
) == SYMBOL_REF
184 && CONSTANT_POOL_ADDRESS_P (addr
))
186 c
= get_pool_constant (addr
);
187 cmode
= get_pool_mode (addr
);
189 /* If we're accessing the constant in a different mode than it was
190 originally stored, attempt to fix that up via subreg simplifications.
191 If that fails we have no choice but to return the original memory. */
192 if (offset
!= 0 || cmode
!= GET_MODE (x
))
194 rtx tem
= simplify_subreg (GET_MODE (x
), c
, cmode
, offset
);
195 if (tem
&& CONSTANT_P (tem
))
205 /* Make a unary operation by first seeing if it folds and otherwise making
206 the specified operation. */
209 simplify_gen_unary (enum rtx_code code
, enum machine_mode mode
, rtx op
,
210 enum machine_mode op_mode
)
214 /* If this simplifies, use it. */
215 if ((tem
= simplify_unary_operation (code
, mode
, op
, op_mode
)) != 0)
218 return gen_rtx_fmt_e (code
, mode
, op
);
221 /* Likewise for ternary operations. */
224 simplify_gen_ternary (enum rtx_code code
, enum machine_mode mode
,
225 enum machine_mode op0_mode
, rtx op0
, rtx op1
, rtx op2
)
229 /* If this simplifies, use it. */
230 if (0 != (tem
= simplify_ternary_operation (code
, mode
, op0_mode
,
234 return gen_rtx_fmt_eee (code
, mode
, op0
, op1
, op2
);
237 /* Likewise, for relational operations.
238 CMP_MODE specifies mode comparison is done in. */
241 simplify_gen_relational (enum rtx_code code
, enum machine_mode mode
,
242 enum machine_mode cmp_mode
, rtx op0
, rtx op1
)
246 if (0 != (tem
= simplify_relational_operation (code
, mode
, cmp_mode
,
250 return gen_rtx_fmt_ee (code
, mode
, op0
, op1
);
253 /* Replace all occurrences of OLD_RTX in X with NEW_RTX and try to simplify the
254 resulting RTX. Return a new RTX which is as simplified as possible. */
257 simplify_replace_rtx (rtx x
, const_rtx old_rtx
, rtx new_rtx
)
259 enum rtx_code code
= GET_CODE (x
);
260 enum machine_mode mode
= GET_MODE (x
);
261 enum machine_mode op_mode
;
264 /* If X is OLD_RTX, return NEW_RTX. Otherwise, if this is an expression, try
265 to build a new expression substituting recursively. If we can't do
266 anything, return our input. */
271 switch (GET_RTX_CLASS (code
))
275 op_mode
= GET_MODE (op0
);
276 op0
= simplify_replace_rtx (op0
, old_rtx
, new_rtx
);
277 if (op0
== XEXP (x
, 0))
279 return simplify_gen_unary (code
, mode
, op0
, op_mode
);
283 op0
= simplify_replace_rtx (XEXP (x
, 0), old_rtx
, new_rtx
);
284 op1
= simplify_replace_rtx (XEXP (x
, 1), old_rtx
, new_rtx
);
285 if (op0
== XEXP (x
, 0) && op1
== XEXP (x
, 1))
287 return simplify_gen_binary (code
, mode
, op0
, op1
);
290 case RTX_COMM_COMPARE
:
293 op_mode
= GET_MODE (op0
) != VOIDmode
? GET_MODE (op0
) : GET_MODE (op1
);
294 op0
= simplify_replace_rtx (op0
, old_rtx
, new_rtx
);
295 op1
= simplify_replace_rtx (op1
, old_rtx
, new_rtx
);
296 if (op0
== XEXP (x
, 0) && op1
== XEXP (x
, 1))
298 return simplify_gen_relational (code
, mode
, op_mode
, op0
, op1
);
301 case RTX_BITFIELD_OPS
:
303 op_mode
= GET_MODE (op0
);
304 op0
= simplify_replace_rtx (op0
, old_rtx
, new_rtx
);
305 op1
= simplify_replace_rtx (XEXP (x
, 1), old_rtx
, new_rtx
);
306 op2
= simplify_replace_rtx (XEXP (x
, 2), old_rtx
, new_rtx
);
307 if (op0
== XEXP (x
, 0) && op1
== XEXP (x
, 1) && op2
== XEXP (x
, 2))
309 if (op_mode
== VOIDmode
)
310 op_mode
= GET_MODE (op0
);
311 return simplify_gen_ternary (code
, mode
, op_mode
, op0
, op1
, op2
);
314 /* The only case we try to handle is a SUBREG. */
317 op0
= simplify_replace_rtx (SUBREG_REG (x
), old_rtx
, new_rtx
);
318 if (op0
== SUBREG_REG (x
))
320 op0
= simplify_gen_subreg (GET_MODE (x
), op0
,
321 GET_MODE (SUBREG_REG (x
)),
323 return op0
? op0
: x
;
330 op0
= simplify_replace_rtx (XEXP (x
, 0), old_rtx
, new_rtx
);
331 if (op0
== XEXP (x
, 0))
333 return replace_equiv_address_nv (x
, op0
);
335 else if (code
== LO_SUM
)
337 op0
= simplify_replace_rtx (XEXP (x
, 0), old_rtx
, new_rtx
);
338 op1
= simplify_replace_rtx (XEXP (x
, 1), old_rtx
, new_rtx
);
340 /* (lo_sum (high x) x) -> x */
341 if (GET_CODE (op0
) == HIGH
&& rtx_equal_p (XEXP (op0
, 0), op1
))
344 if (op0
== XEXP (x
, 0) && op1
== XEXP (x
, 1))
346 return gen_rtx_LO_SUM (mode
, op0
, op1
);
348 else if (code
== REG
)
350 if (rtx_equal_p (x
, old_rtx
))
361 /* Try to simplify a unary operation CODE whose output mode is to be
362 MODE with input operand OP whose mode was originally OP_MODE.
363 Return zero if no simplification can be made. */
365 simplify_unary_operation (enum rtx_code code
, enum machine_mode mode
,
366 rtx op
, enum machine_mode op_mode
)
370 if (GET_CODE (op
) == CONST
)
373 trueop
= avoid_constant_pool_reference (op
);
375 tem
= simplify_const_unary_operation (code
, mode
, trueop
, op_mode
);
379 return simplify_unary_operation_1 (code
, mode
, op
);
382 /* Perform some simplifications we can do even if the operands
385 simplify_unary_operation_1 (enum rtx_code code
, enum machine_mode mode
, rtx op
)
387 enum rtx_code reversed
;
393 /* (not (not X)) == X. */
394 if (GET_CODE (op
) == NOT
)
397 /* (not (eq X Y)) == (ne X Y), etc. if BImode or the result of the
398 comparison is all ones. */
399 if (COMPARISON_P (op
)
400 && (mode
== BImode
|| STORE_FLAG_VALUE
== -1)
401 && ((reversed
= reversed_comparison_code (op
, NULL_RTX
)) != UNKNOWN
))
402 return simplify_gen_relational (reversed
, mode
, VOIDmode
,
403 XEXP (op
, 0), XEXP (op
, 1));
405 /* (not (plus X -1)) can become (neg X). */
406 if (GET_CODE (op
) == PLUS
407 && XEXP (op
, 1) == constm1_rtx
)
408 return simplify_gen_unary (NEG
, mode
, XEXP (op
, 0), mode
);
410 /* Similarly, (not (neg X)) is (plus X -1). */
411 if (GET_CODE (op
) == NEG
)
412 return plus_constant (XEXP (op
, 0), -1);
414 /* (not (xor X C)) for C constant is (xor X D) with D = ~C. */
415 if (GET_CODE (op
) == XOR
416 && GET_CODE (XEXP (op
, 1)) == CONST_INT
417 && (temp
= simplify_unary_operation (NOT
, mode
,
418 XEXP (op
, 1), mode
)) != 0)
419 return simplify_gen_binary (XOR
, mode
, XEXP (op
, 0), temp
);
421 /* (not (plus X C)) for signbit C is (xor X D) with D = ~C. */
422 if (GET_CODE (op
) == PLUS
423 && GET_CODE (XEXP (op
, 1)) == CONST_INT
424 && mode_signbit_p (mode
, XEXP (op
, 1))
425 && (temp
= simplify_unary_operation (NOT
, mode
,
426 XEXP (op
, 1), mode
)) != 0)
427 return simplify_gen_binary (XOR
, mode
, XEXP (op
, 0), temp
);
430 /* (not (ashift 1 X)) is (rotate ~1 X). We used to do this for
431 operands other than 1, but that is not valid. We could do a
432 similar simplification for (not (lshiftrt C X)) where C is
433 just the sign bit, but this doesn't seem common enough to
435 if (GET_CODE (op
) == ASHIFT
436 && XEXP (op
, 0) == const1_rtx
)
438 temp
= simplify_gen_unary (NOT
, mode
, const1_rtx
, mode
);
439 return simplify_gen_binary (ROTATE
, mode
, temp
, XEXP (op
, 1));
442 /* (not (ashiftrt foo C)) where C is the number of bits in FOO
443 minus 1 is (ge foo (const_int 0)) if STORE_FLAG_VALUE is -1,
444 so we can perform the above simplification. */
446 if (STORE_FLAG_VALUE
== -1
447 && GET_CODE (op
) == ASHIFTRT
448 && GET_CODE (XEXP (op
, 1)) == CONST_INT
449 && INTVAL (XEXP (op
, 1)) == GET_MODE_BITSIZE (mode
) - 1)
450 return simplify_gen_relational (GE
, mode
, VOIDmode
,
451 XEXP (op
, 0), const0_rtx
);
454 if (GET_CODE (op
) == SUBREG
455 && subreg_lowpart_p (op
)
456 && (GET_MODE_SIZE (GET_MODE (op
))
457 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (op
))))
458 && GET_CODE (SUBREG_REG (op
)) == ASHIFT
459 && XEXP (SUBREG_REG (op
), 0) == const1_rtx
)
461 enum machine_mode inner_mode
= GET_MODE (SUBREG_REG (op
));
464 x
= gen_rtx_ROTATE (inner_mode
,
465 simplify_gen_unary (NOT
, inner_mode
, const1_rtx
,
467 XEXP (SUBREG_REG (op
), 1));
468 return rtl_hooks
.gen_lowpart_no_emit (mode
, x
);
471 /* Apply De Morgan's laws to reduce number of patterns for machines
472 with negating logical insns (and-not, nand, etc.). If result has
473 only one NOT, put it first, since that is how the patterns are
476 if (GET_CODE (op
) == IOR
|| GET_CODE (op
) == AND
)
478 rtx in1
= XEXP (op
, 0), in2
= XEXP (op
, 1);
479 enum machine_mode op_mode
;
481 op_mode
= GET_MODE (in1
);
482 in1
= simplify_gen_unary (NOT
, op_mode
, in1
, op_mode
);
484 op_mode
= GET_MODE (in2
);
485 if (op_mode
== VOIDmode
)
487 in2
= simplify_gen_unary (NOT
, op_mode
, in2
, op_mode
);
489 if (GET_CODE (in2
) == NOT
&& GET_CODE (in1
) != NOT
)
492 in2
= in1
; in1
= tem
;
495 return gen_rtx_fmt_ee (GET_CODE (op
) == IOR
? AND
: IOR
,
501 /* (neg (neg X)) == X. */
502 if (GET_CODE (op
) == NEG
)
505 /* (neg (plus X 1)) can become (not X). */
506 if (GET_CODE (op
) == PLUS
507 && XEXP (op
, 1) == const1_rtx
)
508 return simplify_gen_unary (NOT
, mode
, XEXP (op
, 0), mode
);
510 /* Similarly, (neg (not X)) is (plus X 1). */
511 if (GET_CODE (op
) == NOT
)
512 return plus_constant (XEXP (op
, 0), 1);
514 /* (neg (minus X Y)) can become (minus Y X). This transformation
515 isn't safe for modes with signed zeros, since if X and Y are
516 both +0, (minus Y X) is the same as (minus X Y). If the
517 rounding mode is towards +infinity (or -infinity) then the two
518 expressions will be rounded differently. */
519 if (GET_CODE (op
) == MINUS
520 && !HONOR_SIGNED_ZEROS (mode
)
521 && !HONOR_SIGN_DEPENDENT_ROUNDING (mode
))
522 return simplify_gen_binary (MINUS
, mode
, XEXP (op
, 1), XEXP (op
, 0));
524 if (GET_CODE (op
) == PLUS
525 && !HONOR_SIGNED_ZEROS (mode
)
526 && !HONOR_SIGN_DEPENDENT_ROUNDING (mode
))
528 /* (neg (plus A C)) is simplified to (minus -C A). */
529 if (GET_CODE (XEXP (op
, 1)) == CONST_INT
530 || GET_CODE (XEXP (op
, 1)) == CONST_DOUBLE
)
532 temp
= simplify_unary_operation (NEG
, mode
, XEXP (op
, 1), mode
);
534 return simplify_gen_binary (MINUS
, mode
, temp
, XEXP (op
, 0));
537 /* (neg (plus A B)) is canonicalized to (minus (neg A) B). */
538 temp
= simplify_gen_unary (NEG
, mode
, XEXP (op
, 0), mode
);
539 return simplify_gen_binary (MINUS
, mode
, temp
, XEXP (op
, 1));
542 /* (neg (mult A B)) becomes (mult (neg A) B).
543 This works even for floating-point values. */
544 if (GET_CODE (op
) == MULT
545 && !HONOR_SIGN_DEPENDENT_ROUNDING (mode
))
547 temp
= simplify_gen_unary (NEG
, mode
, XEXP (op
, 0), mode
);
548 return simplify_gen_binary (MULT
, mode
, temp
, XEXP (op
, 1));
551 /* NEG commutes with ASHIFT since it is multiplication. Only do
552 this if we can then eliminate the NEG (e.g., if the operand
554 if (GET_CODE (op
) == ASHIFT
)
556 temp
= simplify_unary_operation (NEG
, mode
, XEXP (op
, 0), mode
);
558 return simplify_gen_binary (ASHIFT
, mode
, temp
, XEXP (op
, 1));
561 /* (neg (ashiftrt X C)) can be replaced by (lshiftrt X C) when
562 C is equal to the width of MODE minus 1. */
563 if (GET_CODE (op
) == ASHIFTRT
564 && GET_CODE (XEXP (op
, 1)) == CONST_INT
565 && INTVAL (XEXP (op
, 1)) == GET_MODE_BITSIZE (mode
) - 1)
566 return simplify_gen_binary (LSHIFTRT
, mode
,
567 XEXP (op
, 0), XEXP (op
, 1));
569 /* (neg (lshiftrt X C)) can be replaced by (ashiftrt X C) when
570 C is equal to the width of MODE minus 1. */
571 if (GET_CODE (op
) == LSHIFTRT
572 && GET_CODE (XEXP (op
, 1)) == CONST_INT
573 && INTVAL (XEXP (op
, 1)) == GET_MODE_BITSIZE (mode
) - 1)
574 return simplify_gen_binary (ASHIFTRT
, mode
,
575 XEXP (op
, 0), XEXP (op
, 1));
577 /* (neg (xor A 1)) is (plus A -1) if A is known to be either 0 or 1. */
578 if (GET_CODE (op
) == XOR
579 && XEXP (op
, 1) == const1_rtx
580 && nonzero_bits (XEXP (op
, 0), mode
) == 1)
581 return plus_constant (XEXP (op
, 0), -1);
583 /* (neg (lt x 0)) is (ashiftrt X C) if STORE_FLAG_VALUE is 1. */
584 /* (neg (lt x 0)) is (lshiftrt X C) if STORE_FLAG_VALUE is -1. */
585 if (GET_CODE (op
) == LT
586 && XEXP (op
, 1) == const0_rtx
587 && SCALAR_INT_MODE_P (GET_MODE (XEXP (op
, 0))))
589 enum machine_mode inner
= GET_MODE (XEXP (op
, 0));
590 int isize
= GET_MODE_BITSIZE (inner
);
591 if (STORE_FLAG_VALUE
== 1)
593 temp
= simplify_gen_binary (ASHIFTRT
, inner
, XEXP (op
, 0),
594 GEN_INT (isize
- 1));
597 if (GET_MODE_BITSIZE (mode
) > isize
)
598 return simplify_gen_unary (SIGN_EXTEND
, mode
, temp
, inner
);
599 return simplify_gen_unary (TRUNCATE
, mode
, temp
, inner
);
601 else if (STORE_FLAG_VALUE
== -1)
603 temp
= simplify_gen_binary (LSHIFTRT
, inner
, XEXP (op
, 0),
604 GEN_INT (isize
- 1));
607 if (GET_MODE_BITSIZE (mode
) > isize
)
608 return simplify_gen_unary (ZERO_EXTEND
, mode
, temp
, inner
);
609 return simplify_gen_unary (TRUNCATE
, mode
, temp
, inner
);
615 /* We can't handle truncation to a partial integer mode here
616 because we don't know the real bitsize of the partial
618 if (GET_MODE_CLASS (mode
) == MODE_PARTIAL_INT
)
621 /* (truncate:SI ({sign,zero}_extend:DI foo:SI)) == foo:SI. */
622 if ((GET_CODE (op
) == SIGN_EXTEND
623 || GET_CODE (op
) == ZERO_EXTEND
)
624 && GET_MODE (XEXP (op
, 0)) == mode
)
627 /* (truncate:SI (OP:DI ({sign,zero}_extend:DI foo:SI))) is
628 (OP:SI foo:SI) if OP is NEG or ABS. */
629 if ((GET_CODE (op
) == ABS
630 || GET_CODE (op
) == NEG
)
631 && (GET_CODE (XEXP (op
, 0)) == SIGN_EXTEND
632 || GET_CODE (XEXP (op
, 0)) == ZERO_EXTEND
)
633 && GET_MODE (XEXP (XEXP (op
, 0), 0)) == mode
)
634 return simplify_gen_unary (GET_CODE (op
), mode
,
635 XEXP (XEXP (op
, 0), 0), mode
);
637 /* (truncate:A (subreg:B (truncate:C X) 0)) is
639 if (GET_CODE (op
) == SUBREG
640 && GET_CODE (SUBREG_REG (op
)) == TRUNCATE
641 && subreg_lowpart_p (op
))
642 return simplify_gen_unary (TRUNCATE
, mode
, XEXP (SUBREG_REG (op
), 0),
643 GET_MODE (XEXP (SUBREG_REG (op
), 0)));
645 /* If we know that the value is already truncated, we can
646 replace the TRUNCATE with a SUBREG. Note that this is also
647 valid if TRULY_NOOP_TRUNCATION is false for the corresponding
648 modes we just have to apply a different definition for
649 truncation. But don't do this for an (LSHIFTRT (MULT ...))
650 since this will cause problems with the umulXi3_highpart
652 if ((TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode
),
653 GET_MODE_BITSIZE (GET_MODE (op
)))
654 ? (num_sign_bit_copies (op
, GET_MODE (op
))
655 > (unsigned int) (GET_MODE_BITSIZE (GET_MODE (op
))
656 - GET_MODE_BITSIZE (mode
)))
657 : truncated_to_mode (mode
, op
))
658 && ! (GET_CODE (op
) == LSHIFTRT
659 && GET_CODE (XEXP (op
, 0)) == MULT
))
660 return rtl_hooks
.gen_lowpart_no_emit (mode
, op
);
662 /* A truncate of a comparison can be replaced with a subreg if
663 STORE_FLAG_VALUE permits. This is like the previous test,
664 but it works even if the comparison is done in a mode larger
665 than HOST_BITS_PER_WIDE_INT. */
666 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
668 && ((HOST_WIDE_INT
) STORE_FLAG_VALUE
& ~GET_MODE_MASK (mode
)) == 0)
669 return rtl_hooks
.gen_lowpart_no_emit (mode
, op
);
673 if (DECIMAL_FLOAT_MODE_P (mode
))
676 /* (float_truncate:SF (float_extend:DF foo:SF)) = foo:SF. */
677 if (GET_CODE (op
) == FLOAT_EXTEND
678 && GET_MODE (XEXP (op
, 0)) == mode
)
681 /* (float_truncate:SF (float_truncate:DF foo:XF))
682 = (float_truncate:SF foo:XF).
683 This may eliminate double rounding, so it is unsafe.
685 (float_truncate:SF (float_extend:XF foo:DF))
686 = (float_truncate:SF foo:DF).
688 (float_truncate:DF (float_extend:XF foo:SF))
689 = (float_extend:SF foo:DF). */
690 if ((GET_CODE (op
) == FLOAT_TRUNCATE
691 && flag_unsafe_math_optimizations
)
692 || GET_CODE (op
) == FLOAT_EXTEND
)
693 return simplify_gen_unary (GET_MODE_SIZE (GET_MODE (XEXP (op
,
695 > GET_MODE_SIZE (mode
)
696 ? FLOAT_TRUNCATE
: FLOAT_EXTEND
,
700 /* (float_truncate (float x)) is (float x) */
701 if (GET_CODE (op
) == FLOAT
702 && (flag_unsafe_math_optimizations
703 || (SCALAR_FLOAT_MODE_P (GET_MODE (op
))
704 && ((unsigned)significand_size (GET_MODE (op
))
705 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (op
, 0)))
706 - num_sign_bit_copies (XEXP (op
, 0),
707 GET_MODE (XEXP (op
, 0))))))))
708 return simplify_gen_unary (FLOAT
, mode
,
710 GET_MODE (XEXP (op
, 0)));
712 /* (float_truncate:SF (OP:DF (float_extend:DF foo:sf))) is
713 (OP:SF foo:SF) if OP is NEG or ABS. */
714 if ((GET_CODE (op
) == ABS
715 || GET_CODE (op
) == NEG
)
716 && GET_CODE (XEXP (op
, 0)) == FLOAT_EXTEND
717 && GET_MODE (XEXP (XEXP (op
, 0), 0)) == mode
)
718 return simplify_gen_unary (GET_CODE (op
), mode
,
719 XEXP (XEXP (op
, 0), 0), mode
);
721 /* (float_truncate:SF (subreg:DF (float_truncate:SF X) 0))
722 is (float_truncate:SF x). */
723 if (GET_CODE (op
) == SUBREG
724 && subreg_lowpart_p (op
)
725 && GET_CODE (SUBREG_REG (op
)) == FLOAT_TRUNCATE
)
726 return SUBREG_REG (op
);
730 if (DECIMAL_FLOAT_MODE_P (mode
))
733 /* (float_extend (float_extend x)) is (float_extend x)
735 (float_extend (float x)) is (float x) assuming that double
736 rounding can't happen.
738 if (GET_CODE (op
) == FLOAT_EXTEND
739 || (GET_CODE (op
) == FLOAT
740 && SCALAR_FLOAT_MODE_P (GET_MODE (op
))
741 && ((unsigned)significand_size (GET_MODE (op
))
742 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (op
, 0)))
743 - num_sign_bit_copies (XEXP (op
, 0),
744 GET_MODE (XEXP (op
, 0)))))))
745 return simplify_gen_unary (GET_CODE (op
), mode
,
747 GET_MODE (XEXP (op
, 0)));
752 /* (abs (neg <foo>)) -> (abs <foo>) */
753 if (GET_CODE (op
) == NEG
)
754 return simplify_gen_unary (ABS
, mode
, XEXP (op
, 0),
755 GET_MODE (XEXP (op
, 0)));
757 /* If the mode of the operand is VOIDmode (i.e. if it is ASM_OPERANDS),
759 if (GET_MODE (op
) == VOIDmode
)
762 /* If operand is something known to be positive, ignore the ABS. */
763 if (GET_CODE (op
) == FFS
|| GET_CODE (op
) == ABS
764 || ((GET_MODE_BITSIZE (GET_MODE (op
))
765 <= HOST_BITS_PER_WIDE_INT
)
766 && ((nonzero_bits (op
, GET_MODE (op
))
768 << (GET_MODE_BITSIZE (GET_MODE (op
)) - 1)))
772 /* If operand is known to be only -1 or 0, convert ABS to NEG. */
773 if (num_sign_bit_copies (op
, mode
) == GET_MODE_BITSIZE (mode
))
774 return gen_rtx_NEG (mode
, op
);
779 /* (ffs (*_extend <X>)) = (ffs <X>) */
780 if (GET_CODE (op
) == SIGN_EXTEND
781 || GET_CODE (op
) == ZERO_EXTEND
)
782 return simplify_gen_unary (FFS
, mode
, XEXP (op
, 0),
783 GET_MODE (XEXP (op
, 0)));
787 switch (GET_CODE (op
))
791 /* (popcount (zero_extend <X>)) = (popcount <X>) */
792 return simplify_gen_unary (POPCOUNT
, mode
, XEXP (op
, 0),
793 GET_MODE (XEXP (op
, 0)));
797 /* Rotations don't affect popcount. */
798 if (!side_effects_p (XEXP (op
, 1)))
799 return simplify_gen_unary (POPCOUNT
, mode
, XEXP (op
, 0),
800 GET_MODE (XEXP (op
, 0)));
809 switch (GET_CODE (op
))
815 return simplify_gen_unary (PARITY
, mode
, XEXP (op
, 0),
816 GET_MODE (XEXP (op
, 0)));
820 /* Rotations don't affect parity. */
821 if (!side_effects_p (XEXP (op
, 1)))
822 return simplify_gen_unary (PARITY
, mode
, XEXP (op
, 0),
823 GET_MODE (XEXP (op
, 0)));
832 /* (bswap (bswap x)) -> x. */
833 if (GET_CODE (op
) == BSWAP
)
838 /* (float (sign_extend <X>)) = (float <X>). */
839 if (GET_CODE (op
) == SIGN_EXTEND
)
840 return simplify_gen_unary (FLOAT
, mode
, XEXP (op
, 0),
841 GET_MODE (XEXP (op
, 0)));
845 /* (sign_extend (truncate (minus (label_ref L1) (label_ref L2))))
846 becomes just the MINUS if its mode is MODE. This allows
847 folding switch statements on machines using casesi (such as
849 if (GET_CODE (op
) == TRUNCATE
850 && GET_MODE (XEXP (op
, 0)) == mode
851 && GET_CODE (XEXP (op
, 0)) == MINUS
852 && GET_CODE (XEXP (XEXP (op
, 0), 0)) == LABEL_REF
853 && GET_CODE (XEXP (XEXP (op
, 0), 1)) == LABEL_REF
)
856 /* Check for a sign extension of a subreg of a promoted
857 variable, where the promotion is sign-extended, and the
858 target mode is the same as the variable's promotion. */
859 if (GET_CODE (op
) == SUBREG
860 && SUBREG_PROMOTED_VAR_P (op
)
861 && ! SUBREG_PROMOTED_UNSIGNED_P (op
)
862 && GET_MODE (XEXP (op
, 0)) == mode
)
865 #if defined(POINTERS_EXTEND_UNSIGNED) && !defined(HAVE_ptr_extend)
866 if (! POINTERS_EXTEND_UNSIGNED
867 && mode
== Pmode
&& GET_MODE (op
) == ptr_mode
869 || (GET_CODE (op
) == SUBREG
870 && REG_P (SUBREG_REG (op
))
871 && REG_POINTER (SUBREG_REG (op
))
872 && GET_MODE (SUBREG_REG (op
)) == Pmode
)))
873 return convert_memory_address (Pmode
, op
);
878 /* Check for a zero extension of a subreg of a promoted
879 variable, where the promotion is zero-extended, and the
880 target mode is the same as the variable's promotion. */
881 if (GET_CODE (op
) == SUBREG
882 && SUBREG_PROMOTED_VAR_P (op
)
883 && SUBREG_PROMOTED_UNSIGNED_P (op
) > 0
884 && GET_MODE (XEXP (op
, 0)) == mode
)
887 #if defined(POINTERS_EXTEND_UNSIGNED) && !defined(HAVE_ptr_extend)
888 if (POINTERS_EXTEND_UNSIGNED
> 0
889 && mode
== Pmode
&& GET_MODE (op
) == ptr_mode
891 || (GET_CODE (op
) == SUBREG
892 && REG_P (SUBREG_REG (op
))
893 && REG_POINTER (SUBREG_REG (op
))
894 && GET_MODE (SUBREG_REG (op
)) == Pmode
)))
895 return convert_memory_address (Pmode
, op
);
906 /* Try to compute the value of a unary operation CODE whose output mode is to
907 be MODE with input operand OP whose mode was originally OP_MODE.
908 Return zero if the value cannot be computed. */
910 simplify_const_unary_operation (enum rtx_code code
, enum machine_mode mode
,
911 rtx op
, enum machine_mode op_mode
)
913 unsigned int width
= GET_MODE_BITSIZE (mode
);
915 if (code
== VEC_DUPLICATE
)
917 gcc_assert (VECTOR_MODE_P (mode
));
918 if (GET_MODE (op
) != VOIDmode
)
920 if (!VECTOR_MODE_P (GET_MODE (op
)))
921 gcc_assert (GET_MODE_INNER (mode
) == GET_MODE (op
));
923 gcc_assert (GET_MODE_INNER (mode
) == GET_MODE_INNER
926 if (GET_CODE (op
) == CONST_INT
|| GET_CODE (op
) == CONST_DOUBLE
927 || GET_CODE (op
) == CONST_VECTOR
)
929 int elt_size
= GET_MODE_SIZE (GET_MODE_INNER (mode
));
930 unsigned n_elts
= (GET_MODE_SIZE (mode
) / elt_size
);
931 rtvec v
= rtvec_alloc (n_elts
);
934 if (GET_CODE (op
) != CONST_VECTOR
)
935 for (i
= 0; i
< n_elts
; i
++)
936 RTVEC_ELT (v
, i
) = op
;
939 enum machine_mode inmode
= GET_MODE (op
);
940 int in_elt_size
= GET_MODE_SIZE (GET_MODE_INNER (inmode
));
941 unsigned in_n_elts
= (GET_MODE_SIZE (inmode
) / in_elt_size
);
943 gcc_assert (in_n_elts
< n_elts
);
944 gcc_assert ((n_elts
% in_n_elts
) == 0);
945 for (i
= 0; i
< n_elts
; i
++)
946 RTVEC_ELT (v
, i
) = CONST_VECTOR_ELT (op
, i
% in_n_elts
);
948 return gen_rtx_CONST_VECTOR (mode
, v
);
952 if (VECTOR_MODE_P (mode
) && GET_CODE (op
) == CONST_VECTOR
)
954 int elt_size
= GET_MODE_SIZE (GET_MODE_INNER (mode
));
955 unsigned n_elts
= (GET_MODE_SIZE (mode
) / elt_size
);
956 enum machine_mode opmode
= GET_MODE (op
);
957 int op_elt_size
= GET_MODE_SIZE (GET_MODE_INNER (opmode
));
958 unsigned op_n_elts
= (GET_MODE_SIZE (opmode
) / op_elt_size
);
959 rtvec v
= rtvec_alloc (n_elts
);
962 gcc_assert (op_n_elts
== n_elts
);
963 for (i
= 0; i
< n_elts
; i
++)
965 rtx x
= simplify_unary_operation (code
, GET_MODE_INNER (mode
),
966 CONST_VECTOR_ELT (op
, i
),
967 GET_MODE_INNER (opmode
));
970 RTVEC_ELT (v
, i
) = x
;
972 return gen_rtx_CONST_VECTOR (mode
, v
);
975 /* The order of these tests is critical so that, for example, we don't
976 check the wrong mode (input vs. output) for a conversion operation,
977 such as FIX. At some point, this should be simplified. */
979 if (code
== FLOAT
&& GET_MODE (op
) == VOIDmode
980 && (GET_CODE (op
) == CONST_DOUBLE
|| GET_CODE (op
) == CONST_INT
))
982 HOST_WIDE_INT hv
, lv
;
985 if (GET_CODE (op
) == CONST_INT
)
986 lv
= INTVAL (op
), hv
= HWI_SIGN_EXTEND (lv
);
988 lv
= CONST_DOUBLE_LOW (op
), hv
= CONST_DOUBLE_HIGH (op
);
990 REAL_VALUE_FROM_INT (d
, lv
, hv
, mode
);
991 d
= real_value_truncate (mode
, d
);
992 return CONST_DOUBLE_FROM_REAL_VALUE (d
, mode
);
994 else if (code
== UNSIGNED_FLOAT
&& GET_MODE (op
) == VOIDmode
995 && (GET_CODE (op
) == CONST_DOUBLE
996 || GET_CODE (op
) == CONST_INT
))
998 HOST_WIDE_INT hv
, lv
;
1001 if (GET_CODE (op
) == CONST_INT
)
1002 lv
= INTVAL (op
), hv
= HWI_SIGN_EXTEND (lv
);
1004 lv
= CONST_DOUBLE_LOW (op
), hv
= CONST_DOUBLE_HIGH (op
);
1006 if (op_mode
== VOIDmode
)
1008 /* We don't know how to interpret negative-looking numbers in
1009 this case, so don't try to fold those. */
1013 else if (GET_MODE_BITSIZE (op_mode
) >= HOST_BITS_PER_WIDE_INT
* 2)
1016 hv
= 0, lv
&= GET_MODE_MASK (op_mode
);
1018 REAL_VALUE_FROM_UNSIGNED_INT (d
, lv
, hv
, mode
);
1019 d
= real_value_truncate (mode
, d
);
1020 return CONST_DOUBLE_FROM_REAL_VALUE (d
, mode
);
1023 if (GET_CODE (op
) == CONST_INT
1024 && width
<= HOST_BITS_PER_WIDE_INT
&& width
> 0)
1026 HOST_WIDE_INT arg0
= INTVAL (op
);
1040 val
= (arg0
>= 0 ? arg0
: - arg0
);
1044 /* Don't use ffs here. Instead, get low order bit and then its
1045 number. If arg0 is zero, this will return 0, as desired. */
1046 arg0
&= GET_MODE_MASK (mode
);
1047 val
= exact_log2 (arg0
& (- arg0
)) + 1;
1051 arg0
&= GET_MODE_MASK (mode
);
1052 if (arg0
== 0 && CLZ_DEFINED_VALUE_AT_ZERO (mode
, val
))
1055 val
= GET_MODE_BITSIZE (mode
) - floor_log2 (arg0
) - 1;
1059 arg0
&= GET_MODE_MASK (mode
);
1062 /* Even if the value at zero is undefined, we have to come
1063 up with some replacement. Seems good enough. */
1064 if (! CTZ_DEFINED_VALUE_AT_ZERO (mode
, val
))
1065 val
= GET_MODE_BITSIZE (mode
);
1068 val
= exact_log2 (arg0
& -arg0
);
1072 arg0
&= GET_MODE_MASK (mode
);
1075 val
++, arg0
&= arg0
- 1;
1079 arg0
&= GET_MODE_MASK (mode
);
1082 val
++, arg0
&= arg0
- 1;
1091 for (s
= 0; s
< width
; s
+= 8)
1093 unsigned int d
= width
- s
- 8;
1094 unsigned HOST_WIDE_INT byte
;
1095 byte
= (arg0
>> s
) & 0xff;
1106 /* When zero-extending a CONST_INT, we need to know its
1108 gcc_assert (op_mode
!= VOIDmode
);
1109 if (GET_MODE_BITSIZE (op_mode
) == HOST_BITS_PER_WIDE_INT
)
1111 /* If we were really extending the mode,
1112 we would have to distinguish between zero-extension
1113 and sign-extension. */
1114 gcc_assert (width
== GET_MODE_BITSIZE (op_mode
));
1117 else if (GET_MODE_BITSIZE (op_mode
) < HOST_BITS_PER_WIDE_INT
)
1118 val
= arg0
& ~((HOST_WIDE_INT
) (-1) << GET_MODE_BITSIZE (op_mode
));
1124 if (op_mode
== VOIDmode
)
1126 if (GET_MODE_BITSIZE (op_mode
) == HOST_BITS_PER_WIDE_INT
)
1128 /* If we were really extending the mode,
1129 we would have to distinguish between zero-extension
1130 and sign-extension. */
1131 gcc_assert (width
== GET_MODE_BITSIZE (op_mode
));
1134 else if (GET_MODE_BITSIZE (op_mode
) < HOST_BITS_PER_WIDE_INT
)
1137 = arg0
& ~((HOST_WIDE_INT
) (-1) << GET_MODE_BITSIZE (op_mode
));
1139 & ((HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE (op_mode
) - 1)))
1140 val
-= (HOST_WIDE_INT
) 1 << GET_MODE_BITSIZE (op_mode
);
1148 case FLOAT_TRUNCATE
:
1159 return gen_int_mode (val
, mode
);
1162 /* We can do some operations on integer CONST_DOUBLEs. Also allow
1163 for a DImode operation on a CONST_INT. */
1164 else if (GET_MODE (op
) == VOIDmode
1165 && width
<= HOST_BITS_PER_WIDE_INT
* 2
1166 && (GET_CODE (op
) == CONST_DOUBLE
1167 || GET_CODE (op
) == CONST_INT
))
1169 unsigned HOST_WIDE_INT l1
, lv
;
1170 HOST_WIDE_INT h1
, hv
;
1172 if (GET_CODE (op
) == CONST_DOUBLE
)
1173 l1
= CONST_DOUBLE_LOW (op
), h1
= CONST_DOUBLE_HIGH (op
);
1175 l1
= INTVAL (op
), h1
= HWI_SIGN_EXTEND (l1
);
1185 neg_double (l1
, h1
, &lv
, &hv
);
1190 neg_double (l1
, h1
, &lv
, &hv
);
1202 lv
= HOST_BITS_PER_WIDE_INT
+ exact_log2 (h1
& -h1
) + 1;
1205 lv
= exact_log2 (l1
& -l1
) + 1;
1211 lv
= GET_MODE_BITSIZE (mode
) - floor_log2 (h1
) - 1
1212 - HOST_BITS_PER_WIDE_INT
;
1214 lv
= GET_MODE_BITSIZE (mode
) - floor_log2 (l1
) - 1;
1215 else if (! CLZ_DEFINED_VALUE_AT_ZERO (mode
, lv
))
1216 lv
= GET_MODE_BITSIZE (mode
);
1222 lv
= exact_log2 (l1
& -l1
);
1224 lv
= HOST_BITS_PER_WIDE_INT
+ exact_log2 (h1
& -h1
);
1225 else if (! CTZ_DEFINED_VALUE_AT_ZERO (mode
, lv
))
1226 lv
= GET_MODE_BITSIZE (mode
);
1254 for (s
= 0; s
< width
; s
+= 8)
1256 unsigned int d
= width
- s
- 8;
1257 unsigned HOST_WIDE_INT byte
;
1259 if (s
< HOST_BITS_PER_WIDE_INT
)
1260 byte
= (l1
>> s
) & 0xff;
1262 byte
= (h1
>> (s
- HOST_BITS_PER_WIDE_INT
)) & 0xff;
1264 if (d
< HOST_BITS_PER_WIDE_INT
)
1267 hv
|= byte
<< (d
- HOST_BITS_PER_WIDE_INT
);
1273 /* This is just a change-of-mode, so do nothing. */
1278 gcc_assert (op_mode
!= VOIDmode
);
1280 if (GET_MODE_BITSIZE (op_mode
) > HOST_BITS_PER_WIDE_INT
)
1284 lv
= l1
& GET_MODE_MASK (op_mode
);
1288 if (op_mode
== VOIDmode
1289 || GET_MODE_BITSIZE (op_mode
) > HOST_BITS_PER_WIDE_INT
)
1293 lv
= l1
& GET_MODE_MASK (op_mode
);
1294 if (GET_MODE_BITSIZE (op_mode
) < HOST_BITS_PER_WIDE_INT
1295 && (lv
& ((HOST_WIDE_INT
) 1
1296 << (GET_MODE_BITSIZE (op_mode
) - 1))) != 0)
1297 lv
-= (HOST_WIDE_INT
) 1 << GET_MODE_BITSIZE (op_mode
);
1299 hv
= HWI_SIGN_EXTEND (lv
);
1310 return immed_double_const (lv
, hv
, mode
);
1313 else if (GET_CODE (op
) == CONST_DOUBLE
1314 && SCALAR_FLOAT_MODE_P (mode
))
1316 REAL_VALUE_TYPE d
, t
;
1317 REAL_VALUE_FROM_CONST_DOUBLE (d
, op
);
1322 if (HONOR_SNANS (mode
) && real_isnan (&d
))
1324 real_sqrt (&t
, mode
, &d
);
1328 d
= REAL_VALUE_ABS (d
);
1331 d
= REAL_VALUE_NEGATE (d
);
1333 case FLOAT_TRUNCATE
:
1334 d
= real_value_truncate (mode
, d
);
1337 /* All this does is change the mode. */
1340 real_arithmetic (&d
, FIX_TRUNC_EXPR
, &d
, NULL
);
1347 real_to_target (tmp
, &d
, GET_MODE (op
));
1348 for (i
= 0; i
< 4; i
++)
1350 real_from_target (&d
, tmp
, mode
);
1356 return CONST_DOUBLE_FROM_REAL_VALUE (d
, mode
);
1359 else if (GET_CODE (op
) == CONST_DOUBLE
1360 && SCALAR_FLOAT_MODE_P (GET_MODE (op
))
1361 && GET_MODE_CLASS (mode
) == MODE_INT
1362 && width
<= 2*HOST_BITS_PER_WIDE_INT
&& width
> 0)
1364 /* Although the overflow semantics of RTL's FIX and UNSIGNED_FIX
1365 operators are intentionally left unspecified (to ease implementation
1366 by target backends), for consistency, this routine implements the
1367 same semantics for constant folding as used by the middle-end. */
1369 /* This was formerly used only for non-IEEE float.
1370 eggert@twinsun.com says it is safe for IEEE also. */
1371 HOST_WIDE_INT xh
, xl
, th
, tl
;
1372 REAL_VALUE_TYPE x
, t
;
1373 REAL_VALUE_FROM_CONST_DOUBLE (x
, op
);
1377 if (REAL_VALUE_ISNAN (x
))
1380 /* Test against the signed upper bound. */
1381 if (width
> HOST_BITS_PER_WIDE_INT
)
1383 th
= ((unsigned HOST_WIDE_INT
) 1
1384 << (width
- HOST_BITS_PER_WIDE_INT
- 1)) - 1;
1390 tl
= ((unsigned HOST_WIDE_INT
) 1 << (width
- 1)) - 1;
1392 real_from_integer (&t
, VOIDmode
, tl
, th
, 0);
1393 if (REAL_VALUES_LESS (t
, x
))
1400 /* Test against the signed lower bound. */
1401 if (width
> HOST_BITS_PER_WIDE_INT
)
1403 th
= (HOST_WIDE_INT
) -1 << (width
- HOST_BITS_PER_WIDE_INT
- 1);
1409 tl
= (HOST_WIDE_INT
) -1 << (width
- 1);
1411 real_from_integer (&t
, VOIDmode
, tl
, th
, 0);
1412 if (REAL_VALUES_LESS (x
, t
))
1418 REAL_VALUE_TO_INT (&xl
, &xh
, x
);
1422 if (REAL_VALUE_ISNAN (x
) || REAL_VALUE_NEGATIVE (x
))
1425 /* Test against the unsigned upper bound. */
1426 if (width
== 2*HOST_BITS_PER_WIDE_INT
)
1431 else if (width
>= HOST_BITS_PER_WIDE_INT
)
1433 th
= ((unsigned HOST_WIDE_INT
) 1
1434 << (width
- HOST_BITS_PER_WIDE_INT
)) - 1;
1440 tl
= ((unsigned HOST_WIDE_INT
) 1 << width
) - 1;
1442 real_from_integer (&t
, VOIDmode
, tl
, th
, 1);
1443 if (REAL_VALUES_LESS (t
, x
))
1450 REAL_VALUE_TO_INT (&xl
, &xh
, x
);
1456 return immed_double_const (xl
, xh
, mode
);
1462 /* Subroutine of simplify_binary_operation to simplify a commutative,
1463 associative binary operation CODE with result mode MODE, operating
1464 on OP0 and OP1. CODE is currently one of PLUS, MULT, AND, IOR, XOR,
1465 SMIN, SMAX, UMIN or UMAX. Return zero if no simplification or
1466 canonicalization is possible. */
1469 simplify_associative_operation (enum rtx_code code
, enum machine_mode mode
,
1474 /* Linearize the operator to the left. */
1475 if (GET_CODE (op1
) == code
)
1477 /* "(a op b) op (c op d)" becomes "((a op b) op c) op d)". */
1478 if (GET_CODE (op0
) == code
)
1480 tem
= simplify_gen_binary (code
, mode
, op0
, XEXP (op1
, 0));
1481 return simplify_gen_binary (code
, mode
, tem
, XEXP (op1
, 1));
1484 /* "a op (b op c)" becomes "(b op c) op a". */
1485 if (! swap_commutative_operands_p (op1
, op0
))
1486 return simplify_gen_binary (code
, mode
, op1
, op0
);
1493 if (GET_CODE (op0
) == code
)
1495 /* Canonicalize "(x op c) op y" as "(x op y) op c". */
1496 if (swap_commutative_operands_p (XEXP (op0
, 1), op1
))
1498 tem
= simplify_gen_binary (code
, mode
, XEXP (op0
, 0), op1
);
1499 return simplify_gen_binary (code
, mode
, tem
, XEXP (op0
, 1));
1502 /* Attempt to simplify "(a op b) op c" as "a op (b op c)". */
1503 tem
= simplify_binary_operation (code
, mode
, XEXP (op0
, 1), op1
);
1505 return simplify_gen_binary (code
, mode
, XEXP (op0
, 0), tem
);
1507 /* Attempt to simplify "(a op b) op c" as "(a op c) op b". */
1508 tem
= simplify_binary_operation (code
, mode
, XEXP (op0
, 0), op1
);
1510 return simplify_gen_binary (code
, mode
, tem
, XEXP (op0
, 1));
1517 /* Simplify a binary operation CODE with result mode MODE, operating on OP0
1518 and OP1. Return 0 if no simplification is possible.
1520 Don't use this for relational operations such as EQ or LT.
1521 Use simplify_relational_operation instead. */
1523 simplify_binary_operation (enum rtx_code code
, enum machine_mode mode
,
1526 rtx trueop0
, trueop1
;
1529 /* Relational operations don't work here. We must know the mode
1530 of the operands in order to do the comparison correctly.
1531 Assuming a full word can give incorrect results.
1532 Consider comparing 128 with -128 in QImode. */
1533 gcc_assert (GET_RTX_CLASS (code
) != RTX_COMPARE
);
1534 gcc_assert (GET_RTX_CLASS (code
) != RTX_COMM_COMPARE
);
1536 /* Make sure the constant is second. */
1537 if (GET_RTX_CLASS (code
) == RTX_COMM_ARITH
1538 && swap_commutative_operands_p (op0
, op1
))
1540 tem
= op0
, op0
= op1
, op1
= tem
;
1543 trueop0
= avoid_constant_pool_reference (op0
);
1544 trueop1
= avoid_constant_pool_reference (op1
);
1546 tem
= simplify_const_binary_operation (code
, mode
, trueop0
, trueop1
);
1549 return simplify_binary_operation_1 (code
, mode
, op0
, op1
, trueop0
, trueop1
);
1552 /* Subroutine of simplify_binary_operation. Simplify a binary operation
1553 CODE with result mode MODE, operating on OP0 and OP1. If OP0 and/or
1554 OP1 are constant pool references, TRUEOP0 and TRUEOP1 represent the
1555 actual constants. */
1558 simplify_binary_operation_1 (enum rtx_code code
, enum machine_mode mode
,
1559 rtx op0
, rtx op1
, rtx trueop0
, rtx trueop1
)
1561 rtx tem
, reversed
, opleft
, opright
;
1563 unsigned int width
= GET_MODE_BITSIZE (mode
);
1565 /* Even if we can't compute a constant result,
1566 there are some cases worth simplifying. */
1571 /* Maybe simplify x + 0 to x. The two expressions are equivalent
1572 when x is NaN, infinite, or finite and nonzero. They aren't
1573 when x is -0 and the rounding mode is not towards -infinity,
1574 since (-0) + 0 is then 0. */
1575 if (!HONOR_SIGNED_ZEROS (mode
) && trueop1
== CONST0_RTX (mode
))
1578 /* ((-a) + b) -> (b - a) and similarly for (a + (-b)). These
1579 transformations are safe even for IEEE. */
1580 if (GET_CODE (op0
) == NEG
)
1581 return simplify_gen_binary (MINUS
, mode
, op1
, XEXP (op0
, 0));
1582 else if (GET_CODE (op1
) == NEG
)
1583 return simplify_gen_binary (MINUS
, mode
, op0
, XEXP (op1
, 0));
1585 /* (~a) + 1 -> -a */
1586 if (INTEGRAL_MODE_P (mode
)
1587 && GET_CODE (op0
) == NOT
1588 && trueop1
== const1_rtx
)
1589 return simplify_gen_unary (NEG
, mode
, XEXP (op0
, 0), mode
);
1591 /* Handle both-operands-constant cases. We can only add
1592 CONST_INTs to constants since the sum of relocatable symbols
1593 can't be handled by most assemblers. Don't add CONST_INT
1594 to CONST_INT since overflow won't be computed properly if wider
1595 than HOST_BITS_PER_WIDE_INT. */
1597 if (CONSTANT_P (op0
) && GET_MODE (op0
) != VOIDmode
1598 && GET_CODE (op1
) == CONST_INT
)
1599 return plus_constant (op0
, INTVAL (op1
));
1600 else if (CONSTANT_P (op1
) && GET_MODE (op1
) != VOIDmode
1601 && GET_CODE (op0
) == CONST_INT
)
1602 return plus_constant (op1
, INTVAL (op0
));
1604 /* See if this is something like X * C - X or vice versa or
1605 if the multiplication is written as a shift. If so, we can
1606 distribute and make a new multiply, shift, or maybe just
1607 have X (if C is 2 in the example above). But don't make
1608 something more expensive than we had before. */
1610 if (SCALAR_INT_MODE_P (mode
))
1612 HOST_WIDE_INT coeff0h
= 0, coeff1h
= 0;
1613 unsigned HOST_WIDE_INT coeff0l
= 1, coeff1l
= 1;
1614 rtx lhs
= op0
, rhs
= op1
;
1616 if (GET_CODE (lhs
) == NEG
)
1620 lhs
= XEXP (lhs
, 0);
1622 else if (GET_CODE (lhs
) == MULT
1623 && GET_CODE (XEXP (lhs
, 1)) == CONST_INT
)
1625 coeff0l
= INTVAL (XEXP (lhs
, 1));
1626 coeff0h
= INTVAL (XEXP (lhs
, 1)) < 0 ? -1 : 0;
1627 lhs
= XEXP (lhs
, 0);
1629 else if (GET_CODE (lhs
) == ASHIFT
1630 && GET_CODE (XEXP (lhs
, 1)) == CONST_INT
1631 && INTVAL (XEXP (lhs
, 1)) >= 0
1632 && INTVAL (XEXP (lhs
, 1)) < HOST_BITS_PER_WIDE_INT
)
1634 coeff0l
= ((HOST_WIDE_INT
) 1) << INTVAL (XEXP (lhs
, 1));
1636 lhs
= XEXP (lhs
, 0);
1639 if (GET_CODE (rhs
) == NEG
)
1643 rhs
= XEXP (rhs
, 0);
1645 else if (GET_CODE (rhs
) == MULT
1646 && GET_CODE (XEXP (rhs
, 1)) == CONST_INT
)
1648 coeff1l
= INTVAL (XEXP (rhs
, 1));
1649 coeff1h
= INTVAL (XEXP (rhs
, 1)) < 0 ? -1 : 0;
1650 rhs
= XEXP (rhs
, 0);
1652 else if (GET_CODE (rhs
) == ASHIFT
1653 && GET_CODE (XEXP (rhs
, 1)) == CONST_INT
1654 && INTVAL (XEXP (rhs
, 1)) >= 0
1655 && INTVAL (XEXP (rhs
, 1)) < HOST_BITS_PER_WIDE_INT
)
1657 coeff1l
= ((HOST_WIDE_INT
) 1) << INTVAL (XEXP (rhs
, 1));
1659 rhs
= XEXP (rhs
, 0);
1662 if (rtx_equal_p (lhs
, rhs
))
1664 rtx orig
= gen_rtx_PLUS (mode
, op0
, op1
);
1666 unsigned HOST_WIDE_INT l
;
1669 add_double (coeff0l
, coeff0h
, coeff1l
, coeff1h
, &l
, &h
);
1670 coeff
= immed_double_const (l
, h
, mode
);
1672 tem
= simplify_gen_binary (MULT
, mode
, lhs
, coeff
);
1673 return rtx_cost (tem
, SET
) <= rtx_cost (orig
, SET
)
1678 /* (plus (xor X C1) C2) is (xor X (C1^C2)) if C2 is signbit. */
1679 if ((GET_CODE (op1
) == CONST_INT
1680 || GET_CODE (op1
) == CONST_DOUBLE
)
1681 && GET_CODE (op0
) == XOR
1682 && (GET_CODE (XEXP (op0
, 1)) == CONST_INT
1683 || GET_CODE (XEXP (op0
, 1)) == CONST_DOUBLE
)
1684 && mode_signbit_p (mode
, op1
))
1685 return simplify_gen_binary (XOR
, mode
, XEXP (op0
, 0),
1686 simplify_gen_binary (XOR
, mode
, op1
,
1689 /* Canonicalize (plus (mult (neg B) C) A) to (minus A (mult B C)). */
1690 if (!HONOR_SIGN_DEPENDENT_ROUNDING (mode
)
1691 && GET_CODE (op0
) == MULT
1692 && GET_CODE (XEXP (op0
, 0)) == NEG
)
1696 in1
= XEXP (XEXP (op0
, 0), 0);
1697 in2
= XEXP (op0
, 1);
1698 return simplify_gen_binary (MINUS
, mode
, op1
,
1699 simplify_gen_binary (MULT
, mode
,
1703 /* (plus (comparison A B) C) can become (neg (rev-comp A B)) if
1704 C is 1 and STORE_FLAG_VALUE is -1 or if C is -1 and STORE_FLAG_VALUE
1706 if (COMPARISON_P (op0
)
1707 && ((STORE_FLAG_VALUE
== -1 && trueop1
== const1_rtx
)
1708 || (STORE_FLAG_VALUE
== 1 && trueop1
== constm1_rtx
))
1709 && (reversed
= reversed_comparison (op0
, mode
)))
1711 simplify_gen_unary (NEG
, mode
, reversed
, mode
);
1713 /* If one of the operands is a PLUS or a MINUS, see if we can
1714 simplify this by the associative law.
1715 Don't use the associative law for floating point.
1716 The inaccuracy makes it nonassociative,
1717 and subtle programs can break if operations are associated. */
1719 if (INTEGRAL_MODE_P (mode
)
1720 && (plus_minus_operand_p (op0
)
1721 || plus_minus_operand_p (op1
))
1722 && (tem
= simplify_plus_minus (code
, mode
, op0
, op1
)) != 0)
1725 /* Reassociate floating point addition only when the user
1726 specifies associative math operations. */
1727 if (FLOAT_MODE_P (mode
)
1728 && flag_associative_math
)
1730 tem
= simplify_associative_operation (code
, mode
, op0
, op1
);
1738 /* Convert (compare FOO (const_int 0)) to FOO unless we aren't
1739 using cc0, in which case we want to leave it as a COMPARE
1740 so we can distinguish it from a register-register-copy.
1742 In IEEE floating point, x-0 is not the same as x. */
1744 if ((TARGET_FLOAT_FORMAT
!= IEEE_FLOAT_FORMAT
1745 || ! FLOAT_MODE_P (mode
) || flag_unsafe_math_optimizations
)
1746 && trueop1
== CONST0_RTX (mode
))
1750 /* Convert (compare (gt (flags) 0) (lt (flags) 0)) to (flags). */
1751 if (((GET_CODE (op0
) == GT
&& GET_CODE (op1
) == LT
)
1752 || (GET_CODE (op0
) == GTU
&& GET_CODE (op1
) == LTU
))
1753 && XEXP (op0
, 1) == const0_rtx
&& XEXP (op1
, 1) == const0_rtx
)
1755 rtx xop00
= XEXP (op0
, 0);
1756 rtx xop10
= XEXP (op1
, 0);
1759 if (GET_CODE (xop00
) == CC0
&& GET_CODE (xop10
) == CC0
)
1761 if (REG_P (xop00
) && REG_P (xop10
)
1762 && GET_MODE (xop00
) == GET_MODE (xop10
)
1763 && REGNO (xop00
) == REGNO (xop10
)
1764 && GET_MODE_CLASS (GET_MODE (xop00
)) == MODE_CC
1765 && GET_MODE_CLASS (GET_MODE (xop10
)) == MODE_CC
)
1772 /* We can't assume x-x is 0 even with non-IEEE floating point,
1773 but since it is zero except in very strange circumstances, we
1774 will treat it as zero with -ffinite-math-only. */
1775 if (rtx_equal_p (trueop0
, trueop1
)
1776 && ! side_effects_p (op0
)
1777 && (!FLOAT_MODE_P (mode
) || !HONOR_NANS (mode
)))
1778 return CONST0_RTX (mode
);
1780 /* Change subtraction from zero into negation. (0 - x) is the
1781 same as -x when x is NaN, infinite, or finite and nonzero.
1782 But if the mode has signed zeros, and does not round towards
1783 -infinity, then 0 - 0 is 0, not -0. */
1784 if (!HONOR_SIGNED_ZEROS (mode
) && trueop0
== CONST0_RTX (mode
))
1785 return simplify_gen_unary (NEG
, mode
, op1
, mode
);
1787 /* (-1 - a) is ~a. */
1788 if (trueop0
== constm1_rtx
)
1789 return simplify_gen_unary (NOT
, mode
, op1
, mode
);
1791 /* Subtracting 0 has no effect unless the mode has signed zeros
1792 and supports rounding towards -infinity. In such a case,
1794 if (!(HONOR_SIGNED_ZEROS (mode
)
1795 && HONOR_SIGN_DEPENDENT_ROUNDING (mode
))
1796 && trueop1
== CONST0_RTX (mode
))
1799 /* See if this is something like X * C - X or vice versa or
1800 if the multiplication is written as a shift. If so, we can
1801 distribute and make a new multiply, shift, or maybe just
1802 have X (if C is 2 in the example above). But don't make
1803 something more expensive than we had before. */
1805 if (SCALAR_INT_MODE_P (mode
))
1807 HOST_WIDE_INT coeff0h
= 0, negcoeff1h
= -1;
1808 unsigned HOST_WIDE_INT coeff0l
= 1, negcoeff1l
= -1;
1809 rtx lhs
= op0
, rhs
= op1
;
1811 if (GET_CODE (lhs
) == NEG
)
1815 lhs
= XEXP (lhs
, 0);
1817 else if (GET_CODE (lhs
) == MULT
1818 && GET_CODE (XEXP (lhs
, 1)) == CONST_INT
)
1820 coeff0l
= INTVAL (XEXP (lhs
, 1));
1821 coeff0h
= INTVAL (XEXP (lhs
, 1)) < 0 ? -1 : 0;
1822 lhs
= XEXP (lhs
, 0);
1824 else if (GET_CODE (lhs
) == ASHIFT
1825 && GET_CODE (XEXP (lhs
, 1)) == CONST_INT
1826 && INTVAL (XEXP (lhs
, 1)) >= 0
1827 && INTVAL (XEXP (lhs
, 1)) < HOST_BITS_PER_WIDE_INT
)
1829 coeff0l
= ((HOST_WIDE_INT
) 1) << INTVAL (XEXP (lhs
, 1));
1831 lhs
= XEXP (lhs
, 0);
1834 if (GET_CODE (rhs
) == NEG
)
1838 rhs
= XEXP (rhs
, 0);
1840 else if (GET_CODE (rhs
) == MULT
1841 && GET_CODE (XEXP (rhs
, 1)) == CONST_INT
)
1843 negcoeff1l
= -INTVAL (XEXP (rhs
, 1));
1844 negcoeff1h
= INTVAL (XEXP (rhs
, 1)) <= 0 ? 0 : -1;
1845 rhs
= XEXP (rhs
, 0);
1847 else if (GET_CODE (rhs
) == ASHIFT
1848 && GET_CODE (XEXP (rhs
, 1)) == CONST_INT
1849 && INTVAL (XEXP (rhs
, 1)) >= 0
1850 && INTVAL (XEXP (rhs
, 1)) < HOST_BITS_PER_WIDE_INT
)
1852 negcoeff1l
= -(((HOST_WIDE_INT
) 1) << INTVAL (XEXP (rhs
, 1)));
1854 rhs
= XEXP (rhs
, 0);
1857 if (rtx_equal_p (lhs
, rhs
))
1859 rtx orig
= gen_rtx_MINUS (mode
, op0
, op1
);
1861 unsigned HOST_WIDE_INT l
;
1864 add_double (coeff0l
, coeff0h
, negcoeff1l
, negcoeff1h
, &l
, &h
);
1865 coeff
= immed_double_const (l
, h
, mode
);
1867 tem
= simplify_gen_binary (MULT
, mode
, lhs
, coeff
);
1868 return rtx_cost (tem
, SET
) <= rtx_cost (orig
, SET
)
1873 /* (a - (-b)) -> (a + b). True even for IEEE. */
1874 if (GET_CODE (op1
) == NEG
)
1875 return simplify_gen_binary (PLUS
, mode
, op0
, XEXP (op1
, 0));
1877 /* (-x - c) may be simplified as (-c - x). */
1878 if (GET_CODE (op0
) == NEG
1879 && (GET_CODE (op1
) == CONST_INT
1880 || GET_CODE (op1
) == CONST_DOUBLE
))
1882 tem
= simplify_unary_operation (NEG
, mode
, op1
, mode
);
1884 return simplify_gen_binary (MINUS
, mode
, tem
, XEXP (op0
, 0));
1887 /* Don't let a relocatable value get a negative coeff. */
1888 if (GET_CODE (op1
) == CONST_INT
&& GET_MODE (op0
) != VOIDmode
)
1889 return simplify_gen_binary (PLUS
, mode
,
1891 neg_const_int (mode
, op1
));
1893 /* (x - (x & y)) -> (x & ~y) */
1894 if (GET_CODE (op1
) == AND
)
1896 if (rtx_equal_p (op0
, XEXP (op1
, 0)))
1898 tem
= simplify_gen_unary (NOT
, mode
, XEXP (op1
, 1),
1899 GET_MODE (XEXP (op1
, 1)));
1900 return simplify_gen_binary (AND
, mode
, op0
, tem
);
1902 if (rtx_equal_p (op0
, XEXP (op1
, 1)))
1904 tem
= simplify_gen_unary (NOT
, mode
, XEXP (op1
, 0),
1905 GET_MODE (XEXP (op1
, 0)));
1906 return simplify_gen_binary (AND
, mode
, op0
, tem
);
1910 /* If STORE_FLAG_VALUE is 1, (minus 1 (comparison foo bar)) can be done
1911 by reversing the comparison code if valid. */
1912 if (STORE_FLAG_VALUE
== 1
1913 && trueop0
== const1_rtx
1914 && COMPARISON_P (op1
)
1915 && (reversed
= reversed_comparison (op1
, mode
)))
1918 /* Canonicalize (minus A (mult (neg B) C)) to (plus (mult B C) A). */
1919 if (!HONOR_SIGN_DEPENDENT_ROUNDING (mode
)
1920 && GET_CODE (op1
) == MULT
1921 && GET_CODE (XEXP (op1
, 0)) == NEG
)
1925 in1
= XEXP (XEXP (op1
, 0), 0);
1926 in2
= XEXP (op1
, 1);
1927 return simplify_gen_binary (PLUS
, mode
,
1928 simplify_gen_binary (MULT
, mode
,
1933 /* Canonicalize (minus (neg A) (mult B C)) to
1934 (minus (mult (neg B) C) A). */
1935 if (!HONOR_SIGN_DEPENDENT_ROUNDING (mode
)
1936 && GET_CODE (op1
) == MULT
1937 && GET_CODE (op0
) == NEG
)
1941 in1
= simplify_gen_unary (NEG
, mode
, XEXP (op1
, 0), mode
);
1942 in2
= XEXP (op1
, 1);
1943 return simplify_gen_binary (MINUS
, mode
,
1944 simplify_gen_binary (MULT
, mode
,
1949 /* If one of the operands is a PLUS or a MINUS, see if we can
1950 simplify this by the associative law. This will, for example,
1951 canonicalize (minus A (plus B C)) to (minus (minus A B) C).
1952 Don't use the associative law for floating point.
1953 The inaccuracy makes it nonassociative,
1954 and subtle programs can break if operations are associated. */
1956 if (INTEGRAL_MODE_P (mode
)
1957 && (plus_minus_operand_p (op0
)
1958 || plus_minus_operand_p (op1
))
1959 && (tem
= simplify_plus_minus (code
, mode
, op0
, op1
)) != 0)
1964 if (trueop1
== constm1_rtx
)
1965 return simplify_gen_unary (NEG
, mode
, op0
, mode
);
1967 /* Maybe simplify x * 0 to 0. The reduction is not valid if
1968 x is NaN, since x * 0 is then also NaN. Nor is it valid
1969 when the mode has signed zeros, since multiplying a negative
1970 number by 0 will give -0, not 0. */
1971 if (!HONOR_NANS (mode
)
1972 && !HONOR_SIGNED_ZEROS (mode
)
1973 && trueop1
== CONST0_RTX (mode
)
1974 && ! side_effects_p (op0
))
1977 /* In IEEE floating point, x*1 is not equivalent to x for
1979 if (!HONOR_SNANS (mode
)
1980 && trueop1
== CONST1_RTX (mode
))
1983 /* Convert multiply by constant power of two into shift unless
1984 we are still generating RTL. This test is a kludge. */
1985 if (GET_CODE (trueop1
) == CONST_INT
1986 && (val
= exact_log2 (INTVAL (trueop1
))) >= 0
1987 /* If the mode is larger than the host word size, and the
1988 uppermost bit is set, then this isn't a power of two due
1989 to implicit sign extension. */
1990 && (width
<= HOST_BITS_PER_WIDE_INT
1991 || val
!= HOST_BITS_PER_WIDE_INT
- 1))
1992 return simplify_gen_binary (ASHIFT
, mode
, op0
, GEN_INT (val
));
1994 /* Likewise for multipliers wider than a word. */
1995 if (GET_CODE (trueop1
) == CONST_DOUBLE
1996 && (GET_MODE (trueop1
) == VOIDmode
1997 || GET_MODE_CLASS (GET_MODE (trueop1
)) == MODE_INT
)
1998 && GET_MODE (op0
) == mode
1999 && CONST_DOUBLE_LOW (trueop1
) == 0
2000 && (val
= exact_log2 (CONST_DOUBLE_HIGH (trueop1
))) >= 0)
2001 return simplify_gen_binary (ASHIFT
, mode
, op0
,
2002 GEN_INT (val
+ HOST_BITS_PER_WIDE_INT
));
2004 /* x*2 is x+x and x*(-1) is -x */
2005 if (GET_CODE (trueop1
) == CONST_DOUBLE
2006 && SCALAR_FLOAT_MODE_P (GET_MODE (trueop1
))
2007 && GET_MODE (op0
) == mode
)
2010 REAL_VALUE_FROM_CONST_DOUBLE (d
, trueop1
);
2012 if (REAL_VALUES_EQUAL (d
, dconst2
))
2013 return simplify_gen_binary (PLUS
, mode
, op0
, copy_rtx (op0
));
2015 if (!HONOR_SNANS (mode
)
2016 && REAL_VALUES_EQUAL (d
, dconstm1
))
2017 return simplify_gen_unary (NEG
, mode
, op0
, mode
);
2020 /* Optimize -x * -x as x * x. */
2021 if (FLOAT_MODE_P (mode
)
2022 && GET_CODE (op0
) == NEG
2023 && GET_CODE (op1
) == NEG
2024 && rtx_equal_p (XEXP (op0
, 0), XEXP (op1
, 0))
2025 && !side_effects_p (XEXP (op0
, 0)))
2026 return simplify_gen_binary (MULT
, mode
, XEXP (op0
, 0), XEXP (op1
, 0));
2028 /* Likewise, optimize abs(x) * abs(x) as x * x. */
2029 if (SCALAR_FLOAT_MODE_P (mode
)
2030 && GET_CODE (op0
) == ABS
2031 && GET_CODE (op1
) == ABS
2032 && rtx_equal_p (XEXP (op0
, 0), XEXP (op1
, 0))
2033 && !side_effects_p (XEXP (op0
, 0)))
2034 return simplify_gen_binary (MULT
, mode
, XEXP (op0
, 0), XEXP (op1
, 0));
2036 /* Reassociate multiplication, but for floating point MULTs
2037 only when the user specifies unsafe math optimizations. */
2038 if (! FLOAT_MODE_P (mode
)
2039 || flag_unsafe_math_optimizations
)
2041 tem
= simplify_associative_operation (code
, mode
, op0
, op1
);
2048 if (trueop1
== const0_rtx
)
2050 if (GET_CODE (trueop1
) == CONST_INT
2051 && ((INTVAL (trueop1
) & GET_MODE_MASK (mode
))
2052 == GET_MODE_MASK (mode
)))
2054 if (rtx_equal_p (trueop0
, trueop1
) && ! side_effects_p (op0
))
2056 /* A | (~A) -> -1 */
2057 if (((GET_CODE (op0
) == NOT
&& rtx_equal_p (XEXP (op0
, 0), op1
))
2058 || (GET_CODE (op1
) == NOT
&& rtx_equal_p (XEXP (op1
, 0), op0
)))
2059 && ! side_effects_p (op0
)
2060 && SCALAR_INT_MODE_P (mode
))
2063 /* (ior A C) is C if all bits of A that might be nonzero are on in C. */
2064 if (GET_CODE (op1
) == CONST_INT
2065 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
2066 && (nonzero_bits (op0
, mode
) & ~INTVAL (op1
)) == 0)
2069 /* Canonicalize (X & C1) | C2. */
2070 if (GET_CODE (op0
) == AND
2071 && GET_CODE (trueop1
) == CONST_INT
2072 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
)
2074 HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
2075 HOST_WIDE_INT c1
= INTVAL (XEXP (op0
, 1));
2076 HOST_WIDE_INT c2
= INTVAL (trueop1
);
2078 /* If (C1&C2) == C1, then (X&C1)|C2 becomes X. */
2080 && !side_effects_p (XEXP (op0
, 0)))
2083 /* If (C1|C2) == ~0 then (X&C1)|C2 becomes X|C2. */
2084 if (((c1
|c2
) & mask
) == mask
)
2085 return simplify_gen_binary (IOR
, mode
, XEXP (op0
, 0), op1
);
2087 /* Minimize the number of bits set in C1, i.e. C1 := C1 & ~C2. */
2088 if (((c1
& ~c2
) & mask
) != (c1
& mask
))
2090 tem
= simplify_gen_binary (AND
, mode
, XEXP (op0
, 0),
2091 gen_int_mode (c1
& ~c2
, mode
));
2092 return simplify_gen_binary (IOR
, mode
, tem
, op1
);
2096 /* Convert (A & B) | A to A. */
2097 if (GET_CODE (op0
) == AND
2098 && (rtx_equal_p (XEXP (op0
, 0), op1
)
2099 || rtx_equal_p (XEXP (op0
, 1), op1
))
2100 && ! side_effects_p (XEXP (op0
, 0))
2101 && ! side_effects_p (XEXP (op0
, 1)))
2104 /* Convert (ior (ashift A CX) (lshiftrt A CY)) where CX+CY equals the
2105 mode size to (rotate A CX). */
2107 if (GET_CODE (op1
) == ASHIFT
2108 || GET_CODE (op1
) == SUBREG
)
2119 if (GET_CODE (opleft
) == ASHIFT
&& GET_CODE (opright
) == LSHIFTRT
2120 && rtx_equal_p (XEXP (opleft
, 0), XEXP (opright
, 0))
2121 && GET_CODE (XEXP (opleft
, 1)) == CONST_INT
2122 && GET_CODE (XEXP (opright
, 1)) == CONST_INT
2123 && (INTVAL (XEXP (opleft
, 1)) + INTVAL (XEXP (opright
, 1))
2124 == GET_MODE_BITSIZE (mode
)))
2125 return gen_rtx_ROTATE (mode
, XEXP (opright
, 0), XEXP (opleft
, 1));
2127 /* Same, but for ashift that has been "simplified" to a wider mode
2128 by simplify_shift_const. */
2130 if (GET_CODE (opleft
) == SUBREG
2131 && GET_CODE (SUBREG_REG (opleft
)) == ASHIFT
2132 && GET_CODE (opright
) == LSHIFTRT
2133 && GET_CODE (XEXP (opright
, 0)) == SUBREG
2134 && GET_MODE (opleft
) == GET_MODE (XEXP (opright
, 0))
2135 && SUBREG_BYTE (opleft
) == SUBREG_BYTE (XEXP (opright
, 0))
2136 && (GET_MODE_SIZE (GET_MODE (opleft
))
2137 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (opleft
))))
2138 && rtx_equal_p (XEXP (SUBREG_REG (opleft
), 0),
2139 SUBREG_REG (XEXP (opright
, 0)))
2140 && GET_CODE (XEXP (SUBREG_REG (opleft
), 1)) == CONST_INT
2141 && GET_CODE (XEXP (opright
, 1)) == CONST_INT
2142 && (INTVAL (XEXP (SUBREG_REG (opleft
), 1)) + INTVAL (XEXP (opright
, 1))
2143 == GET_MODE_BITSIZE (mode
)))
2144 return gen_rtx_ROTATE (mode
, XEXP (opright
, 0),
2145 XEXP (SUBREG_REG (opleft
), 1));
2147 /* If we have (ior (and (X C1) C2)), simplify this by making
2148 C1 as small as possible if C1 actually changes. */
2149 if (GET_CODE (op1
) == CONST_INT
2150 && (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
2151 || INTVAL (op1
) > 0)
2152 && GET_CODE (op0
) == AND
2153 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
2154 && GET_CODE (op1
) == CONST_INT
2155 && (INTVAL (XEXP (op0
, 1)) & INTVAL (op1
)) != 0)
2156 return simplify_gen_binary (IOR
, mode
,
2158 (AND
, mode
, XEXP (op0
, 0),
2159 GEN_INT (INTVAL (XEXP (op0
, 1))
2163 /* If OP0 is (ashiftrt (plus ...) C), it might actually be
2164 a (sign_extend (plus ...)). Then check if OP1 is a CONST_INT and
2165 the PLUS does not affect any of the bits in OP1: then we can do
2166 the IOR as a PLUS and we can associate. This is valid if OP1
2167 can be safely shifted left C bits. */
2168 if (GET_CODE (trueop1
) == CONST_INT
&& GET_CODE (op0
) == ASHIFTRT
2169 && GET_CODE (XEXP (op0
, 0)) == PLUS
2170 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
2171 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
2172 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
)
2174 int count
= INTVAL (XEXP (op0
, 1));
2175 HOST_WIDE_INT mask
= INTVAL (trueop1
) << count
;
2177 if (mask
>> count
== INTVAL (trueop1
)
2178 && (mask
& nonzero_bits (XEXP (op0
, 0), mode
)) == 0)
2179 return simplify_gen_binary (ASHIFTRT
, mode
,
2180 plus_constant (XEXP (op0
, 0), mask
),
2184 tem
= simplify_associative_operation (code
, mode
, op0
, op1
);
2190 if (trueop1
== const0_rtx
)
2192 if (GET_CODE (trueop1
) == CONST_INT
2193 && ((INTVAL (trueop1
) & GET_MODE_MASK (mode
))
2194 == GET_MODE_MASK (mode
)))
2195 return simplify_gen_unary (NOT
, mode
, op0
, mode
);
2196 if (rtx_equal_p (trueop0
, trueop1
)
2197 && ! side_effects_p (op0
)
2198 && GET_MODE_CLASS (mode
) != MODE_CC
)
2199 return CONST0_RTX (mode
);
2201 /* Canonicalize XOR of the most significant bit to PLUS. */
2202 if ((GET_CODE (op1
) == CONST_INT
2203 || GET_CODE (op1
) == CONST_DOUBLE
)
2204 && mode_signbit_p (mode
, op1
))
2205 return simplify_gen_binary (PLUS
, mode
, op0
, op1
);
2206 /* (xor (plus X C1) C2) is (xor X (C1^C2)) if C1 is signbit. */
2207 if ((GET_CODE (op1
) == CONST_INT
2208 || GET_CODE (op1
) == CONST_DOUBLE
)
2209 && GET_CODE (op0
) == PLUS
2210 && (GET_CODE (XEXP (op0
, 1)) == CONST_INT
2211 || GET_CODE (XEXP (op0
, 1)) == CONST_DOUBLE
)
2212 && mode_signbit_p (mode
, XEXP (op0
, 1)))
2213 return simplify_gen_binary (XOR
, mode
, XEXP (op0
, 0),
2214 simplify_gen_binary (XOR
, mode
, op1
,
2217 /* If we are XORing two things that have no bits in common,
2218 convert them into an IOR. This helps to detect rotation encoded
2219 using those methods and possibly other simplifications. */
2221 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
2222 && (nonzero_bits (op0
, mode
)
2223 & nonzero_bits (op1
, mode
)) == 0)
2224 return (simplify_gen_binary (IOR
, mode
, op0
, op1
));
2226 /* Convert (XOR (NOT x) (NOT y)) to (XOR x y).
2227 Also convert (XOR (NOT x) y) to (NOT (XOR x y)), similarly for
2230 int num_negated
= 0;
2232 if (GET_CODE (op0
) == NOT
)
2233 num_negated
++, op0
= XEXP (op0
, 0);
2234 if (GET_CODE (op1
) == NOT
)
2235 num_negated
++, op1
= XEXP (op1
, 0);
2237 if (num_negated
== 2)
2238 return simplify_gen_binary (XOR
, mode
, op0
, op1
);
2239 else if (num_negated
== 1)
2240 return simplify_gen_unary (NOT
, mode
,
2241 simplify_gen_binary (XOR
, mode
, op0
, op1
),
2245 /* Convert (xor (and A B) B) to (and (not A) B). The latter may
2246 correspond to a machine insn or result in further simplifications
2247 if B is a constant. */
2249 if (GET_CODE (op0
) == AND
2250 && rtx_equal_p (XEXP (op0
, 1), op1
)
2251 && ! side_effects_p (op1
))
2252 return simplify_gen_binary (AND
, mode
,
2253 simplify_gen_unary (NOT
, mode
,
2254 XEXP (op0
, 0), mode
),
2257 else if (GET_CODE (op0
) == AND
2258 && rtx_equal_p (XEXP (op0
, 0), op1
)
2259 && ! side_effects_p (op1
))
2260 return simplify_gen_binary (AND
, mode
,
2261 simplify_gen_unary (NOT
, mode
,
2262 XEXP (op0
, 1), mode
),
2265 /* (xor (comparison foo bar) (const_int 1)) can become the reversed
2266 comparison if STORE_FLAG_VALUE is 1. */
2267 if (STORE_FLAG_VALUE
== 1
2268 && trueop1
== const1_rtx
2269 && COMPARISON_P (op0
)
2270 && (reversed
= reversed_comparison (op0
, mode
)))
2273 /* (lshiftrt foo C) where C is the number of bits in FOO minus 1
2274 is (lt foo (const_int 0)), so we can perform the above
2275 simplification if STORE_FLAG_VALUE is 1. */
2277 if (STORE_FLAG_VALUE
== 1
2278 && trueop1
== const1_rtx
2279 && GET_CODE (op0
) == LSHIFTRT
2280 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
2281 && INTVAL (XEXP (op0
, 1)) == GET_MODE_BITSIZE (mode
) - 1)
2282 return gen_rtx_GE (mode
, XEXP (op0
, 0), const0_rtx
);
2284 /* (xor (comparison foo bar) (const_int sign-bit))
2285 when STORE_FLAG_VALUE is the sign bit. */
2286 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
2287 && ((STORE_FLAG_VALUE
& GET_MODE_MASK (mode
))
2288 == (unsigned HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE (mode
) - 1))
2289 && trueop1
== const_true_rtx
2290 && COMPARISON_P (op0
)
2291 && (reversed
= reversed_comparison (op0
, mode
)))
2294 tem
= simplify_associative_operation (code
, mode
, op0
, op1
);
2300 if (trueop1
== CONST0_RTX (mode
) && ! side_effects_p (op0
))
2302 /* If we are turning off bits already known off in OP0, we need
2304 if (GET_CODE (trueop1
) == CONST_INT
2305 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
2306 && (nonzero_bits (trueop0
, mode
) & ~INTVAL (trueop1
)) == 0)
2308 if (rtx_equal_p (trueop0
, trueop1
) && ! side_effects_p (op0
)
2309 && GET_MODE_CLASS (mode
) != MODE_CC
)
2312 if (((GET_CODE (op0
) == NOT
&& rtx_equal_p (XEXP (op0
, 0), op1
))
2313 || (GET_CODE (op1
) == NOT
&& rtx_equal_p (XEXP (op1
, 0), op0
)))
2314 && ! side_effects_p (op0
)
2315 && GET_MODE_CLASS (mode
) != MODE_CC
)
2316 return CONST0_RTX (mode
);
2318 /* Transform (and (extend X) C) into (zero_extend (and X C)) if
2319 there are no nonzero bits of C outside of X's mode. */
2320 if ((GET_CODE (op0
) == SIGN_EXTEND
2321 || GET_CODE (op0
) == ZERO_EXTEND
)
2322 && GET_CODE (trueop1
) == CONST_INT
2323 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
2324 && (~GET_MODE_MASK (GET_MODE (XEXP (op0
, 0)))
2325 & INTVAL (trueop1
)) == 0)
2327 enum machine_mode imode
= GET_MODE (XEXP (op0
, 0));
2328 tem
= simplify_gen_binary (AND
, imode
, XEXP (op0
, 0),
2329 gen_int_mode (INTVAL (trueop1
),
2331 return simplify_gen_unary (ZERO_EXTEND
, mode
, tem
, imode
);
2334 /* Canonicalize (A | C1) & C2 as (A & C2) | (C1 & C2). */
2335 if (GET_CODE (op0
) == IOR
2336 && GET_CODE (trueop1
) == CONST_INT
2337 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
)
2339 HOST_WIDE_INT tmp
= INTVAL (trueop1
) & INTVAL (XEXP (op0
, 1));
2340 return simplify_gen_binary (IOR
, mode
,
2341 simplify_gen_binary (AND
, mode
,
2342 XEXP (op0
, 0), op1
),
2343 gen_int_mode (tmp
, mode
));
2346 /* Convert (A ^ B) & A to A & (~B) since the latter is often a single
2347 insn (and may simplify more). */
2348 if (GET_CODE (op0
) == XOR
2349 && rtx_equal_p (XEXP (op0
, 0), op1
)
2350 && ! side_effects_p (op1
))
2351 return simplify_gen_binary (AND
, mode
,
2352 simplify_gen_unary (NOT
, mode
,
2353 XEXP (op0
, 1), mode
),
2356 if (GET_CODE (op0
) == XOR
2357 && rtx_equal_p (XEXP (op0
, 1), op1
)
2358 && ! side_effects_p (op1
))
2359 return simplify_gen_binary (AND
, mode
,
2360 simplify_gen_unary (NOT
, mode
,
2361 XEXP (op0
, 0), mode
),
2364 /* Similarly for (~(A ^ B)) & A. */
2365 if (GET_CODE (op0
) == NOT
2366 && GET_CODE (XEXP (op0
, 0)) == XOR
2367 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), op1
)
2368 && ! side_effects_p (op1
))
2369 return simplify_gen_binary (AND
, mode
, XEXP (XEXP (op0
, 0), 1), op1
);
2371 if (GET_CODE (op0
) == NOT
2372 && GET_CODE (XEXP (op0
, 0)) == XOR
2373 && rtx_equal_p (XEXP (XEXP (op0
, 0), 1), op1
)
2374 && ! side_effects_p (op1
))
2375 return simplify_gen_binary (AND
, mode
, XEXP (XEXP (op0
, 0), 0), op1
);
2377 /* Convert (A | B) & A to A. */
2378 if (GET_CODE (op0
) == IOR
2379 && (rtx_equal_p (XEXP (op0
, 0), op1
)
2380 || rtx_equal_p (XEXP (op0
, 1), op1
))
2381 && ! side_effects_p (XEXP (op0
, 0))
2382 && ! side_effects_p (XEXP (op0
, 1)))
2385 /* For constants M and N, if M == (1LL << cst) - 1 && (N & M) == M,
2386 ((A & N) + B) & M -> (A + B) & M
2387 Similarly if (N & M) == 0,
2388 ((A | N) + B) & M -> (A + B) & M
2389 and for - instead of + and/or ^ instead of |. */
2390 if (GET_CODE (trueop1
) == CONST_INT
2391 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
2392 && ~INTVAL (trueop1
)
2393 && (INTVAL (trueop1
) & (INTVAL (trueop1
) + 1)) == 0
2394 && (GET_CODE (op0
) == PLUS
|| GET_CODE (op0
) == MINUS
))
2399 pmop
[0] = XEXP (op0
, 0);
2400 pmop
[1] = XEXP (op0
, 1);
2402 for (which
= 0; which
< 2; which
++)
2405 switch (GET_CODE (tem
))
2408 if (GET_CODE (XEXP (tem
, 1)) == CONST_INT
2409 && (INTVAL (XEXP (tem
, 1)) & INTVAL (trueop1
))
2410 == INTVAL (trueop1
))
2411 pmop
[which
] = XEXP (tem
, 0);
2415 if (GET_CODE (XEXP (tem
, 1)) == CONST_INT
2416 && (INTVAL (XEXP (tem
, 1)) & INTVAL (trueop1
)) == 0)
2417 pmop
[which
] = XEXP (tem
, 0);
2424 if (pmop
[0] != XEXP (op0
, 0) || pmop
[1] != XEXP (op0
, 1))
2426 tem
= simplify_gen_binary (GET_CODE (op0
), mode
,
2428 return simplify_gen_binary (code
, mode
, tem
, op1
);
2432 /* (and X (ior (not X) Y) -> (and X Y) */
2433 if (GET_CODE (op1
) == IOR
2434 && GET_CODE (XEXP (op1
, 0)) == NOT
2435 && op0
== XEXP (XEXP (op1
, 0), 0))
2436 return simplify_gen_binary (AND
, mode
, op0
, XEXP (op1
, 1));
2438 /* (and (ior (not X) Y) X) -> (and X Y) */
2439 if (GET_CODE (op0
) == IOR
2440 && GET_CODE (XEXP (op0
, 0)) == NOT
2441 && op1
== XEXP (XEXP (op0
, 0), 0))
2442 return simplify_gen_binary (AND
, mode
, op1
, XEXP (op0
, 1));
2444 tem
= simplify_associative_operation (code
, mode
, op0
, op1
);
2450 /* 0/x is 0 (or x&0 if x has side-effects). */
2451 if (trueop0
== CONST0_RTX (mode
))
2453 if (side_effects_p (op1
))
2454 return simplify_gen_binary (AND
, mode
, op1
, trueop0
);
2458 if (trueop1
== CONST1_RTX (mode
))
2459 return rtl_hooks
.gen_lowpart_no_emit (mode
, op0
);
2460 /* Convert divide by power of two into shift. */
2461 if (GET_CODE (trueop1
) == CONST_INT
2462 && (val
= exact_log2 (INTVAL (trueop1
))) > 0)
2463 return simplify_gen_binary (LSHIFTRT
, mode
, op0
, GEN_INT (val
));
2467 /* Handle floating point and integers separately. */
2468 if (SCALAR_FLOAT_MODE_P (mode
))
2470 /* Maybe change 0.0 / x to 0.0. This transformation isn't
2471 safe for modes with NaNs, since 0.0 / 0.0 will then be
2472 NaN rather than 0.0. Nor is it safe for modes with signed
2473 zeros, since dividing 0 by a negative number gives -0.0 */
2474 if (trueop0
== CONST0_RTX (mode
)
2475 && !HONOR_NANS (mode
)
2476 && !HONOR_SIGNED_ZEROS (mode
)
2477 && ! side_effects_p (op1
))
2480 if (trueop1
== CONST1_RTX (mode
)
2481 && !HONOR_SNANS (mode
))
2484 if (GET_CODE (trueop1
) == CONST_DOUBLE
2485 && trueop1
!= CONST0_RTX (mode
))
2488 REAL_VALUE_FROM_CONST_DOUBLE (d
, trueop1
);
2491 if (REAL_VALUES_EQUAL (d
, dconstm1
)
2492 && !HONOR_SNANS (mode
))
2493 return simplify_gen_unary (NEG
, mode
, op0
, mode
);
2495 /* Change FP division by a constant into multiplication.
2496 Only do this with -freciprocal-math. */
2497 if (flag_reciprocal_math
2498 && !REAL_VALUES_EQUAL (d
, dconst0
))
2500 REAL_ARITHMETIC (d
, RDIV_EXPR
, dconst1
, d
);
2501 tem
= CONST_DOUBLE_FROM_REAL_VALUE (d
, mode
);
2502 return simplify_gen_binary (MULT
, mode
, op0
, tem
);
2508 /* 0/x is 0 (or x&0 if x has side-effects). */
2509 if (trueop0
== CONST0_RTX (mode
))
2511 if (side_effects_p (op1
))
2512 return simplify_gen_binary (AND
, mode
, op1
, trueop0
);
2516 if (trueop1
== CONST1_RTX (mode
))
2517 return rtl_hooks
.gen_lowpart_no_emit (mode
, op0
);
2519 if (trueop1
== constm1_rtx
)
2521 rtx x
= rtl_hooks
.gen_lowpart_no_emit (mode
, op0
);
2522 return simplify_gen_unary (NEG
, mode
, x
, mode
);
2528 /* 0%x is 0 (or x&0 if x has side-effects). */
2529 if (trueop0
== CONST0_RTX (mode
))
2531 if (side_effects_p (op1
))
2532 return simplify_gen_binary (AND
, mode
, op1
, trueop0
);
2535 /* x%1 is 0 (of x&0 if x has side-effects). */
2536 if (trueop1
== CONST1_RTX (mode
))
2538 if (side_effects_p (op0
))
2539 return simplify_gen_binary (AND
, mode
, op0
, CONST0_RTX (mode
));
2540 return CONST0_RTX (mode
);
2542 /* Implement modulus by power of two as AND. */
2543 if (GET_CODE (trueop1
) == CONST_INT
2544 && exact_log2 (INTVAL (trueop1
)) > 0)
2545 return simplify_gen_binary (AND
, mode
, op0
,
2546 GEN_INT (INTVAL (op1
) - 1));
2550 /* 0%x is 0 (or x&0 if x has side-effects). */
2551 if (trueop0
== CONST0_RTX (mode
))
2553 if (side_effects_p (op1
))
2554 return simplify_gen_binary (AND
, mode
, op1
, trueop0
);
2557 /* x%1 and x%-1 is 0 (or x&0 if x has side-effects). */
2558 if (trueop1
== CONST1_RTX (mode
) || trueop1
== constm1_rtx
)
2560 if (side_effects_p (op0
))
2561 return simplify_gen_binary (AND
, mode
, op0
, CONST0_RTX (mode
));
2562 return CONST0_RTX (mode
);
2569 if (trueop1
== CONST0_RTX (mode
))
2571 if (trueop0
== CONST0_RTX (mode
) && ! side_effects_p (op1
))
2573 /* Rotating ~0 always results in ~0. */
2574 if (GET_CODE (trueop0
) == CONST_INT
&& width
<= HOST_BITS_PER_WIDE_INT
2575 && (unsigned HOST_WIDE_INT
) INTVAL (trueop0
) == GET_MODE_MASK (mode
)
2576 && ! side_effects_p (op1
))
2579 if (SHIFT_COUNT_TRUNCATED
&& GET_CODE (op1
) == CONST_INT
)
2581 val
= INTVAL (op1
) & (GET_MODE_BITSIZE (mode
) - 1);
2582 if (val
!= INTVAL (op1
))
2583 return simplify_gen_binary (code
, mode
, op0
, GEN_INT (val
));
2590 if (trueop1
== CONST0_RTX (mode
))
2592 if (trueop0
== CONST0_RTX (mode
) && ! side_effects_p (op1
))
2594 goto canonicalize_shift
;
2597 if (trueop1
== CONST0_RTX (mode
))
2599 if (trueop0
== CONST0_RTX (mode
) && ! side_effects_p (op1
))
2601 /* Optimize (lshiftrt (clz X) C) as (eq X 0). */
2602 if (GET_CODE (op0
) == CLZ
2603 && GET_CODE (trueop1
) == CONST_INT
2604 && STORE_FLAG_VALUE
== 1
2605 && INTVAL (trueop1
) < (HOST_WIDE_INT
)width
)
2607 enum machine_mode imode
= GET_MODE (XEXP (op0
, 0));
2608 unsigned HOST_WIDE_INT zero_val
= 0;
2610 if (CLZ_DEFINED_VALUE_AT_ZERO (imode
, zero_val
)
2611 && zero_val
== GET_MODE_BITSIZE (imode
)
2612 && INTVAL (trueop1
) == exact_log2 (zero_val
))
2613 return simplify_gen_relational (EQ
, mode
, imode
,
2614 XEXP (op0
, 0), const0_rtx
);
2616 goto canonicalize_shift
;
2619 if (width
<= HOST_BITS_PER_WIDE_INT
2620 && GET_CODE (trueop1
) == CONST_INT
2621 && INTVAL (trueop1
) == (HOST_WIDE_INT
) 1 << (width
-1)
2622 && ! side_effects_p (op0
))
2624 if (rtx_equal_p (trueop0
, trueop1
) && ! side_effects_p (op0
))
2626 tem
= simplify_associative_operation (code
, mode
, op0
, op1
);
2632 if (width
<= HOST_BITS_PER_WIDE_INT
2633 && GET_CODE (trueop1
) == CONST_INT
2634 && ((unsigned HOST_WIDE_INT
) INTVAL (trueop1
)
2635 == (unsigned HOST_WIDE_INT
) GET_MODE_MASK (mode
) >> 1)
2636 && ! side_effects_p (op0
))
2638 if (rtx_equal_p (trueop0
, trueop1
) && ! side_effects_p (op0
))
2640 tem
= simplify_associative_operation (code
, mode
, op0
, op1
);
2646 if (trueop1
== CONST0_RTX (mode
) && ! side_effects_p (op0
))
2648 if (rtx_equal_p (trueop0
, trueop1
) && ! side_effects_p (op0
))
2650 tem
= simplify_associative_operation (code
, mode
, op0
, op1
);
2656 if (trueop1
== constm1_rtx
&& ! side_effects_p (op0
))
2658 if (rtx_equal_p (trueop0
, trueop1
) && ! side_effects_p (op0
))
2660 tem
= simplify_associative_operation (code
, mode
, op0
, op1
);
2673 /* ??? There are simplifications that can be done. */
2677 if (!VECTOR_MODE_P (mode
))
2679 gcc_assert (VECTOR_MODE_P (GET_MODE (trueop0
)));
2680 gcc_assert (mode
== GET_MODE_INNER (GET_MODE (trueop0
)));
2681 gcc_assert (GET_CODE (trueop1
) == PARALLEL
);
2682 gcc_assert (XVECLEN (trueop1
, 0) == 1);
2683 gcc_assert (GET_CODE (XVECEXP (trueop1
, 0, 0)) == CONST_INT
);
2685 if (GET_CODE (trueop0
) == CONST_VECTOR
)
2686 return CONST_VECTOR_ELT (trueop0
, INTVAL (XVECEXP
2689 /* Extract a scalar element from a nested VEC_SELECT expression
2690 (with optional nested VEC_CONCAT expression). Some targets
2691 (i386) extract scalar element from a vector using chain of
2692 nested VEC_SELECT expressions. When input operand is a memory
2693 operand, this operation can be simplified to a simple scalar
2694 load from an offseted memory address. */
2695 if (GET_CODE (trueop0
) == VEC_SELECT
)
2697 rtx op0
= XEXP (trueop0
, 0);
2698 rtx op1
= XEXP (trueop0
, 1);
2700 enum machine_mode opmode
= GET_MODE (op0
);
2701 int elt_size
= GET_MODE_SIZE (GET_MODE_INNER (opmode
));
2702 int n_elts
= GET_MODE_SIZE (opmode
) / elt_size
;
2704 int i
= INTVAL (XVECEXP (trueop1
, 0, 0));
2710 gcc_assert (GET_CODE (op1
) == PARALLEL
);
2711 gcc_assert (i
< n_elts
);
2713 /* Select element, pointed by nested selector. */
2714 elem
= INTVAL (XVECEXP (op1
, 0, i
));
2716 /* Handle the case when nested VEC_SELECT wraps VEC_CONCAT. */
2717 if (GET_CODE (op0
) == VEC_CONCAT
)
2719 rtx op00
= XEXP (op0
, 0);
2720 rtx op01
= XEXP (op0
, 1);
2722 enum machine_mode mode00
, mode01
;
2723 int n_elts00
, n_elts01
;
2725 mode00
= GET_MODE (op00
);
2726 mode01
= GET_MODE (op01
);
2728 /* Find out number of elements of each operand. */
2729 if (VECTOR_MODE_P (mode00
))
2731 elt_size
= GET_MODE_SIZE (GET_MODE_INNER (mode00
));
2732 n_elts00
= GET_MODE_SIZE (mode00
) / elt_size
;
2737 if (VECTOR_MODE_P (mode01
))
2739 elt_size
= GET_MODE_SIZE (GET_MODE_INNER (mode01
));
2740 n_elts01
= GET_MODE_SIZE (mode01
) / elt_size
;
2745 gcc_assert (n_elts
== n_elts00
+ n_elts01
);
2747 /* Select correct operand of VEC_CONCAT
2748 and adjust selector. */
2749 if (elem
< n_elts01
)
2760 vec
= rtvec_alloc (1);
2761 RTVEC_ELT (vec
, 0) = GEN_INT (elem
);
2763 tmp
= gen_rtx_fmt_ee (code
, mode
,
2764 tmp_op
, gen_rtx_PARALLEL (VOIDmode
, vec
));
2770 gcc_assert (VECTOR_MODE_P (GET_MODE (trueop0
)));
2771 gcc_assert (GET_MODE_INNER (mode
)
2772 == GET_MODE_INNER (GET_MODE (trueop0
)));
2773 gcc_assert (GET_CODE (trueop1
) == PARALLEL
);
2775 if (GET_CODE (trueop0
) == CONST_VECTOR
)
2777 int elt_size
= GET_MODE_SIZE (GET_MODE_INNER (mode
));
2778 unsigned n_elts
= (GET_MODE_SIZE (mode
) / elt_size
);
2779 rtvec v
= rtvec_alloc (n_elts
);
2782 gcc_assert (XVECLEN (trueop1
, 0) == (int) n_elts
);
2783 for (i
= 0; i
< n_elts
; i
++)
2785 rtx x
= XVECEXP (trueop1
, 0, i
);
2787 gcc_assert (GET_CODE (x
) == CONST_INT
);
2788 RTVEC_ELT (v
, i
) = CONST_VECTOR_ELT (trueop0
,
2792 return gen_rtx_CONST_VECTOR (mode
, v
);
2796 if (XVECLEN (trueop1
, 0) == 1
2797 && GET_CODE (XVECEXP (trueop1
, 0, 0)) == CONST_INT
2798 && GET_CODE (trueop0
) == VEC_CONCAT
)
2801 int offset
= INTVAL (XVECEXP (trueop1
, 0, 0)) * GET_MODE_SIZE (mode
);
2803 /* Try to find the element in the VEC_CONCAT. */
2804 while (GET_MODE (vec
) != mode
2805 && GET_CODE (vec
) == VEC_CONCAT
)
2807 HOST_WIDE_INT vec_size
= GET_MODE_SIZE (GET_MODE (XEXP (vec
, 0)));
2808 if (offset
< vec_size
)
2809 vec
= XEXP (vec
, 0);
2813 vec
= XEXP (vec
, 1);
2815 vec
= avoid_constant_pool_reference (vec
);
2818 if (GET_MODE (vec
) == mode
)
2825 enum machine_mode op0_mode
= (GET_MODE (trueop0
) != VOIDmode
2826 ? GET_MODE (trueop0
)
2827 : GET_MODE_INNER (mode
));
2828 enum machine_mode op1_mode
= (GET_MODE (trueop1
) != VOIDmode
2829 ? GET_MODE (trueop1
)
2830 : GET_MODE_INNER (mode
));
2832 gcc_assert (VECTOR_MODE_P (mode
));
2833 gcc_assert (GET_MODE_SIZE (op0_mode
) + GET_MODE_SIZE (op1_mode
)
2834 == GET_MODE_SIZE (mode
));
2836 if (VECTOR_MODE_P (op0_mode
))
2837 gcc_assert (GET_MODE_INNER (mode
)
2838 == GET_MODE_INNER (op0_mode
));
2840 gcc_assert (GET_MODE_INNER (mode
) == op0_mode
);
2842 if (VECTOR_MODE_P (op1_mode
))
2843 gcc_assert (GET_MODE_INNER (mode
)
2844 == GET_MODE_INNER (op1_mode
));
2846 gcc_assert (GET_MODE_INNER (mode
) == op1_mode
);
2848 if ((GET_CODE (trueop0
) == CONST_VECTOR
2849 || GET_CODE (trueop0
) == CONST_INT
2850 || GET_CODE (trueop0
) == CONST_DOUBLE
)
2851 && (GET_CODE (trueop1
) == CONST_VECTOR
2852 || GET_CODE (trueop1
) == CONST_INT
2853 || GET_CODE (trueop1
) == CONST_DOUBLE
))
2855 int elt_size
= GET_MODE_SIZE (GET_MODE_INNER (mode
));
2856 unsigned n_elts
= (GET_MODE_SIZE (mode
) / elt_size
);
2857 rtvec v
= rtvec_alloc (n_elts
);
2859 unsigned in_n_elts
= 1;
2861 if (VECTOR_MODE_P (op0_mode
))
2862 in_n_elts
= (GET_MODE_SIZE (op0_mode
) / elt_size
);
2863 for (i
= 0; i
< n_elts
; i
++)
2867 if (!VECTOR_MODE_P (op0_mode
))
2868 RTVEC_ELT (v
, i
) = trueop0
;
2870 RTVEC_ELT (v
, i
) = CONST_VECTOR_ELT (trueop0
, i
);
2874 if (!VECTOR_MODE_P (op1_mode
))
2875 RTVEC_ELT (v
, i
) = trueop1
;
2877 RTVEC_ELT (v
, i
) = CONST_VECTOR_ELT (trueop1
,
2882 return gen_rtx_CONST_VECTOR (mode
, v
);
2895 simplify_const_binary_operation (enum rtx_code code
, enum machine_mode mode
,
2898 HOST_WIDE_INT arg0
, arg1
, arg0s
, arg1s
;
2900 unsigned int width
= GET_MODE_BITSIZE (mode
);
2902 if (VECTOR_MODE_P (mode
)
2903 && code
!= VEC_CONCAT
2904 && GET_CODE (op0
) == CONST_VECTOR
2905 && GET_CODE (op1
) == CONST_VECTOR
)
2907 unsigned n_elts
= GET_MODE_NUNITS (mode
);
2908 enum machine_mode op0mode
= GET_MODE (op0
);
2909 unsigned op0_n_elts
= GET_MODE_NUNITS (op0mode
);
2910 enum machine_mode op1mode
= GET_MODE (op1
);
2911 unsigned op1_n_elts
= GET_MODE_NUNITS (op1mode
);
2912 rtvec v
= rtvec_alloc (n_elts
);
2915 gcc_assert (op0_n_elts
== n_elts
);
2916 gcc_assert (op1_n_elts
== n_elts
);
2917 for (i
= 0; i
< n_elts
; i
++)
2919 rtx x
= simplify_binary_operation (code
, GET_MODE_INNER (mode
),
2920 CONST_VECTOR_ELT (op0
, i
),
2921 CONST_VECTOR_ELT (op1
, i
));
2924 RTVEC_ELT (v
, i
) = x
;
2927 return gen_rtx_CONST_VECTOR (mode
, v
);
2930 if (VECTOR_MODE_P (mode
)
2931 && code
== VEC_CONCAT
2932 && (CONST_INT_P (op0
)
2933 || GET_CODE (op0
) == CONST_DOUBLE
2934 || GET_CODE (op0
) == CONST_FIXED
)
2935 && (CONST_INT_P (op1
)
2936 || GET_CODE (op1
) == CONST_DOUBLE
2937 || GET_CODE (op1
) == CONST_FIXED
))
2939 unsigned n_elts
= GET_MODE_NUNITS (mode
);
2940 rtvec v
= rtvec_alloc (n_elts
);
2942 gcc_assert (n_elts
>= 2);
2945 gcc_assert (GET_CODE (op0
) != CONST_VECTOR
);
2946 gcc_assert (GET_CODE (op1
) != CONST_VECTOR
);
2948 RTVEC_ELT (v
, 0) = op0
;
2949 RTVEC_ELT (v
, 1) = op1
;
2953 unsigned op0_n_elts
= GET_MODE_NUNITS (GET_MODE (op0
));
2954 unsigned op1_n_elts
= GET_MODE_NUNITS (GET_MODE (op1
));
2957 gcc_assert (GET_CODE (op0
) == CONST_VECTOR
);
2958 gcc_assert (GET_CODE (op1
) == CONST_VECTOR
);
2959 gcc_assert (op0_n_elts
+ op1_n_elts
== n_elts
);
2961 for (i
= 0; i
< op0_n_elts
; ++i
)
2962 RTVEC_ELT (v
, i
) = XVECEXP (op0
, 0, i
);
2963 for (i
= 0; i
< op1_n_elts
; ++i
)
2964 RTVEC_ELT (v
, op0_n_elts
+i
) = XVECEXP (op1
, 0, i
);
2967 return gen_rtx_CONST_VECTOR (mode
, v
);
2970 if (SCALAR_FLOAT_MODE_P (mode
)
2971 && GET_CODE (op0
) == CONST_DOUBLE
2972 && GET_CODE (op1
) == CONST_DOUBLE
2973 && mode
== GET_MODE (op0
) && mode
== GET_MODE (op1
))
2984 real_to_target (tmp0
, CONST_DOUBLE_REAL_VALUE (op0
),
2986 real_to_target (tmp1
, CONST_DOUBLE_REAL_VALUE (op1
),
2988 for (i
= 0; i
< 4; i
++)
3005 real_from_target (&r
, tmp0
, mode
);
3006 return CONST_DOUBLE_FROM_REAL_VALUE (r
, mode
);
3010 REAL_VALUE_TYPE f0
, f1
, value
, result
;
3013 REAL_VALUE_FROM_CONST_DOUBLE (f0
, op0
);
3014 REAL_VALUE_FROM_CONST_DOUBLE (f1
, op1
);
3015 real_convert (&f0
, mode
, &f0
);
3016 real_convert (&f1
, mode
, &f1
);
3018 if (HONOR_SNANS (mode
)
3019 && (REAL_VALUE_ISNAN (f0
) || REAL_VALUE_ISNAN (f1
)))
3023 && REAL_VALUES_EQUAL (f1
, dconst0
)
3024 && (flag_trapping_math
|| ! MODE_HAS_INFINITIES (mode
)))
3027 if (MODE_HAS_INFINITIES (mode
) && HONOR_NANS (mode
)
3028 && flag_trapping_math
3029 && REAL_VALUE_ISINF (f0
) && REAL_VALUE_ISINF (f1
))
3031 int s0
= REAL_VALUE_NEGATIVE (f0
);
3032 int s1
= REAL_VALUE_NEGATIVE (f1
);
3037 /* Inf + -Inf = NaN plus exception. */
3042 /* Inf - Inf = NaN plus exception. */
3047 /* Inf / Inf = NaN plus exception. */
3054 if (code
== MULT
&& MODE_HAS_INFINITIES (mode
) && HONOR_NANS (mode
)
3055 && flag_trapping_math
3056 && ((REAL_VALUE_ISINF (f0
) && REAL_VALUES_EQUAL (f1
, dconst0
))
3057 || (REAL_VALUE_ISINF (f1
)
3058 && REAL_VALUES_EQUAL (f0
, dconst0
))))
3059 /* Inf * 0 = NaN plus exception. */
3062 inexact
= real_arithmetic (&value
, rtx_to_tree_code (code
),
3064 real_convert (&result
, mode
, &value
);
3066 /* Don't constant fold this floating point operation if
3067 the result has overflowed and flag_trapping_math. */
3069 if (flag_trapping_math
3070 && MODE_HAS_INFINITIES (mode
)
3071 && REAL_VALUE_ISINF (result
)
3072 && !REAL_VALUE_ISINF (f0
)
3073 && !REAL_VALUE_ISINF (f1
))
3074 /* Overflow plus exception. */
3077 /* Don't constant fold this floating point operation if the
3078 result may dependent upon the run-time rounding mode and
3079 flag_rounding_math is set, or if GCC's software emulation
3080 is unable to accurately represent the result. */
3082 if ((flag_rounding_math
3083 || (REAL_MODE_FORMAT_COMPOSITE_P (mode
)
3084 && !flag_unsafe_math_optimizations
))
3085 && (inexact
|| !real_identical (&result
, &value
)))
3088 return CONST_DOUBLE_FROM_REAL_VALUE (result
, mode
);
3092 /* We can fold some multi-word operations. */
3093 if (GET_MODE_CLASS (mode
) == MODE_INT
3094 && width
== HOST_BITS_PER_WIDE_INT
* 2
3095 && (GET_CODE (op0
) == CONST_DOUBLE
|| GET_CODE (op0
) == CONST_INT
)
3096 && (GET_CODE (op1
) == CONST_DOUBLE
|| GET_CODE (op1
) == CONST_INT
))
3098 unsigned HOST_WIDE_INT l1
, l2
, lv
, lt
;
3099 HOST_WIDE_INT h1
, h2
, hv
, ht
;
3101 if (GET_CODE (op0
) == CONST_DOUBLE
)
3102 l1
= CONST_DOUBLE_LOW (op0
), h1
= CONST_DOUBLE_HIGH (op0
);
3104 l1
= INTVAL (op0
), h1
= HWI_SIGN_EXTEND (l1
);
3106 if (GET_CODE (op1
) == CONST_DOUBLE
)
3107 l2
= CONST_DOUBLE_LOW (op1
), h2
= CONST_DOUBLE_HIGH (op1
);
3109 l2
= INTVAL (op1
), h2
= HWI_SIGN_EXTEND (l2
);
3114 /* A - B == A + (-B). */
3115 neg_double (l2
, h2
, &lv
, &hv
);
3118 /* Fall through.... */
3121 add_double (l1
, h1
, l2
, h2
, &lv
, &hv
);
3125 mul_double (l1
, h1
, l2
, h2
, &lv
, &hv
);
3129 if (div_and_round_double (TRUNC_DIV_EXPR
, 0, l1
, h1
, l2
, h2
,
3130 &lv
, &hv
, <
, &ht
))
3135 if (div_and_round_double (TRUNC_DIV_EXPR
, 0, l1
, h1
, l2
, h2
,
3136 <
, &ht
, &lv
, &hv
))
3141 if (div_and_round_double (TRUNC_DIV_EXPR
, 1, l1
, h1
, l2
, h2
,
3142 &lv
, &hv
, <
, &ht
))
3147 if (div_and_round_double (TRUNC_DIV_EXPR
, 1, l1
, h1
, l2
, h2
,
3148 <
, &ht
, &lv
, &hv
))
3153 lv
= l1
& l2
, hv
= h1
& h2
;
3157 lv
= l1
| l2
, hv
= h1
| h2
;
3161 lv
= l1
^ l2
, hv
= h1
^ h2
;
3167 && ((unsigned HOST_WIDE_INT
) l1
3168 < (unsigned HOST_WIDE_INT
) l2
)))
3177 && ((unsigned HOST_WIDE_INT
) l1
3178 > (unsigned HOST_WIDE_INT
) l2
)))
3185 if ((unsigned HOST_WIDE_INT
) h1
< (unsigned HOST_WIDE_INT
) h2
3187 && ((unsigned HOST_WIDE_INT
) l1
3188 < (unsigned HOST_WIDE_INT
) l2
)))
3195 if ((unsigned HOST_WIDE_INT
) h1
> (unsigned HOST_WIDE_INT
) h2
3197 && ((unsigned HOST_WIDE_INT
) l1
3198 > (unsigned HOST_WIDE_INT
) l2
)))
3204 case LSHIFTRT
: case ASHIFTRT
:
3206 case ROTATE
: case ROTATERT
:
3207 if (SHIFT_COUNT_TRUNCATED
)
3208 l2
&= (GET_MODE_BITSIZE (mode
) - 1), h2
= 0;
3210 if (h2
!= 0 || l2
>= GET_MODE_BITSIZE (mode
))
3213 if (code
== LSHIFTRT
|| code
== ASHIFTRT
)
3214 rshift_double (l1
, h1
, l2
, GET_MODE_BITSIZE (mode
), &lv
, &hv
,
3216 else if (code
== ASHIFT
)
3217 lshift_double (l1
, h1
, l2
, GET_MODE_BITSIZE (mode
), &lv
, &hv
, 1);
3218 else if (code
== ROTATE
)
3219 lrotate_double (l1
, h1
, l2
, GET_MODE_BITSIZE (mode
), &lv
, &hv
);
3220 else /* code == ROTATERT */
3221 rrotate_double (l1
, h1
, l2
, GET_MODE_BITSIZE (mode
), &lv
, &hv
);
3228 return immed_double_const (lv
, hv
, mode
);
3231 if (GET_CODE (op0
) == CONST_INT
&& GET_CODE (op1
) == CONST_INT
3232 && width
<= HOST_BITS_PER_WIDE_INT
&& width
!= 0)
3234 /* Get the integer argument values in two forms:
3235 zero-extended in ARG0, ARG1 and sign-extended in ARG0S, ARG1S. */
3237 arg0
= INTVAL (op0
);
3238 arg1
= INTVAL (op1
);
3240 if (width
< HOST_BITS_PER_WIDE_INT
)
3242 arg0
&= ((HOST_WIDE_INT
) 1 << width
) - 1;
3243 arg1
&= ((HOST_WIDE_INT
) 1 << width
) - 1;
3246 if (arg0s
& ((HOST_WIDE_INT
) 1 << (width
- 1)))
3247 arg0s
|= ((HOST_WIDE_INT
) (-1) << width
);
3250 if (arg1s
& ((HOST_WIDE_INT
) 1 << (width
- 1)))
3251 arg1s
|= ((HOST_WIDE_INT
) (-1) << width
);
3259 /* Compute the value of the arithmetic. */
3264 val
= arg0s
+ arg1s
;
3268 val
= arg0s
- arg1s
;
3272 val
= arg0s
* arg1s
;
3277 || (arg0s
== (HOST_WIDE_INT
) 1 << (HOST_BITS_PER_WIDE_INT
- 1)
3280 val
= arg0s
/ arg1s
;
3285 || (arg0s
== (HOST_WIDE_INT
) 1 << (HOST_BITS_PER_WIDE_INT
- 1)
3288 val
= arg0s
% arg1s
;
3293 || (arg0s
== (HOST_WIDE_INT
) 1 << (HOST_BITS_PER_WIDE_INT
- 1)
3296 val
= (unsigned HOST_WIDE_INT
) arg0
/ arg1
;
3301 || (arg0s
== (HOST_WIDE_INT
) 1 << (HOST_BITS_PER_WIDE_INT
- 1)
3304 val
= (unsigned HOST_WIDE_INT
) arg0
% arg1
;
3322 /* Truncate the shift if SHIFT_COUNT_TRUNCATED, otherwise make sure
3323 the value is in range. We can't return any old value for
3324 out-of-range arguments because either the middle-end (via
3325 shift_truncation_mask) or the back-end might be relying on
3326 target-specific knowledge. Nor can we rely on
3327 shift_truncation_mask, since the shift might not be part of an
3328 ashlM3, lshrM3 or ashrM3 instruction. */
3329 if (SHIFT_COUNT_TRUNCATED
)
3330 arg1
= (unsigned HOST_WIDE_INT
) arg1
% width
;
3331 else if (arg1
< 0 || arg1
>= GET_MODE_BITSIZE (mode
))
3334 val
= (code
== ASHIFT
3335 ? ((unsigned HOST_WIDE_INT
) arg0
) << arg1
3336 : ((unsigned HOST_WIDE_INT
) arg0
) >> arg1
);
3338 /* Sign-extend the result for arithmetic right shifts. */
3339 if (code
== ASHIFTRT
&& arg0s
< 0 && arg1
> 0)
3340 val
|= ((HOST_WIDE_INT
) -1) << (width
- arg1
);
3348 val
= ((((unsigned HOST_WIDE_INT
) arg0
) << (width
- arg1
))
3349 | (((unsigned HOST_WIDE_INT
) arg0
) >> arg1
));
3357 val
= ((((unsigned HOST_WIDE_INT
) arg0
) << arg1
)
3358 | (((unsigned HOST_WIDE_INT
) arg0
) >> (width
- arg1
)));
3362 /* Do nothing here. */
3366 val
= arg0s
<= arg1s
? arg0s
: arg1s
;
3370 val
= ((unsigned HOST_WIDE_INT
) arg0
3371 <= (unsigned HOST_WIDE_INT
) arg1
? arg0
: arg1
);
3375 val
= arg0s
> arg1s
? arg0s
: arg1s
;
3379 val
= ((unsigned HOST_WIDE_INT
) arg0
3380 > (unsigned HOST_WIDE_INT
) arg1
? arg0
: arg1
);
3393 /* ??? There are simplifications that can be done. */
3400 return gen_int_mode (val
, mode
);
3408 /* Simplify a PLUS or MINUS, at least one of whose operands may be another
3411 Rather than test for specific case, we do this by a brute-force method
3412 and do all possible simplifications until no more changes occur. Then
3413 we rebuild the operation. */
3415 struct simplify_plus_minus_op_data
3422 simplify_plus_minus_op_data_cmp (rtx x
, rtx y
)
3426 result
= (commutative_operand_precedence (y
)
3427 - commutative_operand_precedence (x
));
3431 /* Group together equal REGs to do more simplification. */
3432 if (REG_P (x
) && REG_P (y
))
3433 return REGNO (x
) > REGNO (y
);
3439 simplify_plus_minus (enum rtx_code code
, enum machine_mode mode
, rtx op0
,
3442 struct simplify_plus_minus_op_data ops
[8];
3444 int n_ops
= 2, input_ops
= 2;
3445 int changed
, n_constants
= 0, canonicalized
= 0;
3448 memset (ops
, 0, sizeof ops
);
3450 /* Set up the two operands and then expand them until nothing has been
3451 changed. If we run out of room in our array, give up; this should
3452 almost never happen. */
3457 ops
[1].neg
= (code
== MINUS
);
3463 for (i
= 0; i
< n_ops
; i
++)
3465 rtx this_op
= ops
[i
].op
;
3466 int this_neg
= ops
[i
].neg
;
3467 enum rtx_code this_code
= GET_CODE (this_op
);
3476 ops
[n_ops
].op
= XEXP (this_op
, 1);
3477 ops
[n_ops
].neg
= (this_code
== MINUS
) ^ this_neg
;
3480 ops
[i
].op
= XEXP (this_op
, 0);
3483 canonicalized
|= this_neg
;
3487 ops
[i
].op
= XEXP (this_op
, 0);
3488 ops
[i
].neg
= ! this_neg
;
3495 && GET_CODE (XEXP (this_op
, 0)) == PLUS
3496 && CONSTANT_P (XEXP (XEXP (this_op
, 0), 0))
3497 && CONSTANT_P (XEXP (XEXP (this_op
, 0), 1)))
3499 ops
[i
].op
= XEXP (XEXP (this_op
, 0), 0);
3500 ops
[n_ops
].op
= XEXP (XEXP (this_op
, 0), 1);
3501 ops
[n_ops
].neg
= this_neg
;
3509 /* ~a -> (-a - 1) */
3512 ops
[n_ops
].op
= constm1_rtx
;
3513 ops
[n_ops
++].neg
= this_neg
;
3514 ops
[i
].op
= XEXP (this_op
, 0);
3515 ops
[i
].neg
= !this_neg
;
3525 ops
[i
].op
= neg_const_int (mode
, this_op
);
3539 if (n_constants
> 1)
3542 gcc_assert (n_ops
>= 2);
3544 /* If we only have two operands, we can avoid the loops. */
3547 enum rtx_code code
= ops
[0].neg
|| ops
[1].neg
? MINUS
: PLUS
;
3550 /* Get the two operands. Be careful with the order, especially for
3551 the cases where code == MINUS. */
3552 if (ops
[0].neg
&& ops
[1].neg
)
3554 lhs
= gen_rtx_NEG (mode
, ops
[0].op
);
3557 else if (ops
[0].neg
)
3568 return simplify_const_binary_operation (code
, mode
, lhs
, rhs
);
3571 /* Now simplify each pair of operands until nothing changes. */
3574 /* Insertion sort is good enough for an eight-element array. */
3575 for (i
= 1; i
< n_ops
; i
++)
3577 struct simplify_plus_minus_op_data save
;
3579 if (!simplify_plus_minus_op_data_cmp (ops
[j
].op
, ops
[i
].op
))
3585 ops
[j
+ 1] = ops
[j
];
3586 while (j
-- && simplify_plus_minus_op_data_cmp (ops
[j
].op
, save
.op
));
3590 /* This is only useful the first time through. */
3595 for (i
= n_ops
- 1; i
> 0; i
--)
3596 for (j
= i
- 1; j
>= 0; j
--)
3598 rtx lhs
= ops
[j
].op
, rhs
= ops
[i
].op
;
3599 int lneg
= ops
[j
].neg
, rneg
= ops
[i
].neg
;
3601 if (lhs
!= 0 && rhs
!= 0)
3603 enum rtx_code ncode
= PLUS
;
3609 tem
= lhs
, lhs
= rhs
, rhs
= tem
;
3611 else if (swap_commutative_operands_p (lhs
, rhs
))
3612 tem
= lhs
, lhs
= rhs
, rhs
= tem
;
3614 if ((GET_CODE (lhs
) == CONST
|| GET_CODE (lhs
) == CONST_INT
)
3615 && (GET_CODE (rhs
) == CONST
|| GET_CODE (rhs
) == CONST_INT
))
3617 rtx tem_lhs
, tem_rhs
;
3619 tem_lhs
= GET_CODE (lhs
) == CONST
? XEXP (lhs
, 0) : lhs
;
3620 tem_rhs
= GET_CODE (rhs
) == CONST
? XEXP (rhs
, 0) : rhs
;
3621 tem
= simplify_binary_operation (ncode
, mode
, tem_lhs
, tem_rhs
);
3623 if (tem
&& !CONSTANT_P (tem
))
3624 tem
= gen_rtx_CONST (GET_MODE (tem
), tem
);
3627 tem
= simplify_binary_operation (ncode
, mode
, lhs
, rhs
);
3629 /* Reject "simplifications" that just wrap the two
3630 arguments in a CONST. Failure to do so can result
3631 in infinite recursion with simplify_binary_operation
3632 when it calls us to simplify CONST operations. */
3634 && ! (GET_CODE (tem
) == CONST
3635 && GET_CODE (XEXP (tem
, 0)) == ncode
3636 && XEXP (XEXP (tem
, 0), 0) == lhs
3637 && XEXP (XEXP (tem
, 0), 1) == rhs
))
3640 if (GET_CODE (tem
) == NEG
)
3641 tem
= XEXP (tem
, 0), lneg
= !lneg
;
3642 if (GET_CODE (tem
) == CONST_INT
&& lneg
)
3643 tem
= neg_const_int (mode
, tem
), lneg
= 0;
3647 ops
[j
].op
= NULL_RTX
;
3653 /* Pack all the operands to the lower-numbered entries. */
3654 for (i
= 0, j
= 0; j
< n_ops
; j
++)
3664 /* Create (minus -C X) instead of (neg (const (plus X C))). */
3666 && GET_CODE (ops
[1].op
) == CONST_INT
3667 && CONSTANT_P (ops
[0].op
)
3669 return gen_rtx_fmt_ee (MINUS
, mode
, ops
[1].op
, ops
[0].op
);
3671 /* We suppressed creation of trivial CONST expressions in the
3672 combination loop to avoid recursion. Create one manually now.
3673 The combination loop should have ensured that there is exactly
3674 one CONST_INT, and the sort will have ensured that it is last
3675 in the array and that any other constant will be next-to-last. */
3678 && GET_CODE (ops
[n_ops
- 1].op
) == CONST_INT
3679 && CONSTANT_P (ops
[n_ops
- 2].op
))
3681 rtx value
= ops
[n_ops
- 1].op
;
3682 if (ops
[n_ops
- 1].neg
^ ops
[n_ops
- 2].neg
)
3683 value
= neg_const_int (mode
, value
);
3684 ops
[n_ops
- 2].op
= plus_constant (ops
[n_ops
- 2].op
, INTVAL (value
));
3688 /* Put a non-negated operand first, if possible. */
3690 for (i
= 0; i
< n_ops
&& ops
[i
].neg
; i
++)
3693 ops
[0].op
= gen_rtx_NEG (mode
, ops
[0].op
);
3702 /* Now make the result by performing the requested operations. */
3704 for (i
= 1; i
< n_ops
; i
++)
3705 result
= gen_rtx_fmt_ee (ops
[i
].neg
? MINUS
: PLUS
,
3706 mode
, result
, ops
[i
].op
);
3711 /* Check whether an operand is suitable for calling simplify_plus_minus. */
3713 plus_minus_operand_p (const_rtx x
)
3715 return GET_CODE (x
) == PLUS
3716 || GET_CODE (x
) == MINUS
3717 || (GET_CODE (x
) == CONST
3718 && GET_CODE (XEXP (x
, 0)) == PLUS
3719 && CONSTANT_P (XEXP (XEXP (x
, 0), 0))
3720 && CONSTANT_P (XEXP (XEXP (x
, 0), 1)));
3723 /* Like simplify_binary_operation except used for relational operators.
3724 MODE is the mode of the result. If MODE is VOIDmode, both operands must
3725 not also be VOIDmode.
3727 CMP_MODE specifies in which mode the comparison is done in, so it is
3728 the mode of the operands. If CMP_MODE is VOIDmode, it is taken from
3729 the operands or, if both are VOIDmode, the operands are compared in
3730 "infinite precision". */
3732 simplify_relational_operation (enum rtx_code code
, enum machine_mode mode
,
3733 enum machine_mode cmp_mode
, rtx op0
, rtx op1
)
3735 rtx tem
, trueop0
, trueop1
;
3737 if (cmp_mode
== VOIDmode
)
3738 cmp_mode
= GET_MODE (op0
);
3739 if (cmp_mode
== VOIDmode
)
3740 cmp_mode
= GET_MODE (op1
);
3742 tem
= simplify_const_relational_operation (code
, cmp_mode
, op0
, op1
);
3745 if (SCALAR_FLOAT_MODE_P (mode
))
3747 if (tem
== const0_rtx
)
3748 return CONST0_RTX (mode
);
3749 #ifdef FLOAT_STORE_FLAG_VALUE
3751 REAL_VALUE_TYPE val
;
3752 val
= FLOAT_STORE_FLAG_VALUE (mode
);
3753 return CONST_DOUBLE_FROM_REAL_VALUE (val
, mode
);
3759 if (VECTOR_MODE_P (mode
))
3761 if (tem
== const0_rtx
)
3762 return CONST0_RTX (mode
);
3763 #ifdef VECTOR_STORE_FLAG_VALUE
3768 rtx val
= VECTOR_STORE_FLAG_VALUE (mode
);
3769 if (val
== NULL_RTX
)
3771 if (val
== const1_rtx
)
3772 return CONST1_RTX (mode
);
3774 units
= GET_MODE_NUNITS (mode
);
3775 v
= rtvec_alloc (units
);
3776 for (i
= 0; i
< units
; i
++)
3777 RTVEC_ELT (v
, i
) = val
;
3778 return gen_rtx_raw_CONST_VECTOR (mode
, v
);
3788 /* For the following tests, ensure const0_rtx is op1. */
3789 if (swap_commutative_operands_p (op0
, op1
)
3790 || (op0
== const0_rtx
&& op1
!= const0_rtx
))
3791 tem
= op0
, op0
= op1
, op1
= tem
, code
= swap_condition (code
);
3793 /* If op0 is a compare, extract the comparison arguments from it. */
3794 if (GET_CODE (op0
) == COMPARE
&& op1
== const0_rtx
)
3795 return simplify_relational_operation (code
, mode
, VOIDmode
,
3796 XEXP (op0
, 0), XEXP (op0
, 1));
3798 if (GET_MODE_CLASS (cmp_mode
) == MODE_CC
3802 trueop0
= avoid_constant_pool_reference (op0
);
3803 trueop1
= avoid_constant_pool_reference (op1
);
3804 return simplify_relational_operation_1 (code
, mode
, cmp_mode
,
3808 /* This part of simplify_relational_operation is only used when CMP_MODE
3809 is not in class MODE_CC (i.e. it is a real comparison).
3811 MODE is the mode of the result, while CMP_MODE specifies in which
3812 mode the comparison is done in, so it is the mode of the operands. */
3815 simplify_relational_operation_1 (enum rtx_code code
, enum machine_mode mode
,
3816 enum machine_mode cmp_mode
, rtx op0
, rtx op1
)
3818 enum rtx_code op0code
= GET_CODE (op0
);
3820 if (op1
== const0_rtx
&& COMPARISON_P (op0
))
3822 /* If op0 is a comparison, extract the comparison arguments
3826 if (GET_MODE (op0
) == mode
)
3827 return simplify_rtx (op0
);
3829 return simplify_gen_relational (GET_CODE (op0
), mode
, VOIDmode
,
3830 XEXP (op0
, 0), XEXP (op0
, 1));
3832 else if (code
== EQ
)
3834 enum rtx_code new_code
= reversed_comparison_code (op0
, NULL_RTX
);
3835 if (new_code
!= UNKNOWN
)
3836 return simplify_gen_relational (new_code
, mode
, VOIDmode
,
3837 XEXP (op0
, 0), XEXP (op0
, 1));
3841 /* Canonicalize (LTU/GEU (PLUS a b) b) as (LTU/GEU (PLUS a b) a). */
3842 if ((code
== LTU
|| code
== GEU
)
3843 && GET_CODE (op0
) == PLUS
3844 && rtx_equal_p (op1
, XEXP (op0
, 1))
3845 /* Don't recurse "infinitely" for (LTU/GEU (PLUS b b) b). */
3846 && !rtx_equal_p (op1
, XEXP (op0
, 0)))
3847 return simplify_gen_relational (code
, mode
, cmp_mode
, op0
, XEXP (op0
, 0));
3849 if (op1
== const0_rtx
)
3851 /* Canonicalize (GTU x 0) as (NE x 0). */
3853 return simplify_gen_relational (NE
, mode
, cmp_mode
, op0
, op1
);
3854 /* Canonicalize (LEU x 0) as (EQ x 0). */
3856 return simplify_gen_relational (EQ
, mode
, cmp_mode
, op0
, op1
);
3858 else if (op1
== const1_rtx
)
3863 /* Canonicalize (GE x 1) as (GT x 0). */
3864 return simplify_gen_relational (GT
, mode
, cmp_mode
,
3867 /* Canonicalize (GEU x 1) as (NE x 0). */
3868 return simplify_gen_relational (NE
, mode
, cmp_mode
,
3871 /* Canonicalize (LT x 1) as (LE x 0). */
3872 return simplify_gen_relational (LE
, mode
, cmp_mode
,
3875 /* Canonicalize (LTU x 1) as (EQ x 0). */
3876 return simplify_gen_relational (EQ
, mode
, cmp_mode
,
3882 else if (op1
== constm1_rtx
)
3884 /* Canonicalize (LE x -1) as (LT x 0). */
3886 return simplify_gen_relational (LT
, mode
, cmp_mode
, op0
, const0_rtx
);
3887 /* Canonicalize (GT x -1) as (GE x 0). */
3889 return simplify_gen_relational (GE
, mode
, cmp_mode
, op0
, const0_rtx
);
3892 /* (eq/ne (plus x cst1) cst2) simplifies to (eq/ne x (cst2 - cst1)) */
3893 if ((code
== EQ
|| code
== NE
)
3894 && (op0code
== PLUS
|| op0code
== MINUS
)
3896 && CONSTANT_P (XEXP (op0
, 1))
3897 && (INTEGRAL_MODE_P (cmp_mode
) || flag_unsafe_math_optimizations
))
3899 rtx x
= XEXP (op0
, 0);
3900 rtx c
= XEXP (op0
, 1);
3902 c
= simplify_gen_binary (op0code
== PLUS
? MINUS
: PLUS
,
3904 return simplify_gen_relational (code
, mode
, cmp_mode
, x
, c
);
3907 /* (ne:SI (zero_extract:SI FOO (const_int 1) BAR) (const_int 0))) is
3908 the same as (zero_extract:SI FOO (const_int 1) BAR). */
3910 && op1
== const0_rtx
3911 && GET_MODE_CLASS (mode
) == MODE_INT
3912 && cmp_mode
!= VOIDmode
3913 /* ??? Work-around BImode bugs in the ia64 backend. */
3915 && cmp_mode
!= BImode
3916 && nonzero_bits (op0
, cmp_mode
) == 1
3917 && STORE_FLAG_VALUE
== 1)
3918 return GET_MODE_SIZE (mode
) > GET_MODE_SIZE (cmp_mode
)
3919 ? simplify_gen_unary (ZERO_EXTEND
, mode
, op0
, cmp_mode
)
3920 : lowpart_subreg (mode
, op0
, cmp_mode
);
3922 /* (eq/ne (xor x y) 0) simplifies to (eq/ne x y). */
3923 if ((code
== EQ
|| code
== NE
)
3924 && op1
== const0_rtx
3926 return simplify_gen_relational (code
, mode
, cmp_mode
,
3927 XEXP (op0
, 0), XEXP (op0
, 1));
3929 /* (eq/ne (xor x y) x) simplifies to (eq/ne y 0). */
3930 if ((code
== EQ
|| code
== NE
)
3932 && rtx_equal_p (XEXP (op0
, 0), op1
)
3933 && !side_effects_p (XEXP (op0
, 0)))
3934 return simplify_gen_relational (code
, mode
, cmp_mode
,
3935 XEXP (op0
, 1), const0_rtx
);
3937 /* Likewise (eq/ne (xor x y) y) simplifies to (eq/ne x 0). */
3938 if ((code
== EQ
|| code
== NE
)
3940 && rtx_equal_p (XEXP (op0
, 1), op1
)
3941 && !side_effects_p (XEXP (op0
, 1)))
3942 return simplify_gen_relational (code
, mode
, cmp_mode
,
3943 XEXP (op0
, 0), const0_rtx
);
3945 /* (eq/ne (xor x C1) C2) simplifies to (eq/ne x (C1^C2)). */
3946 if ((code
== EQ
|| code
== NE
)
3948 && (GET_CODE (op1
) == CONST_INT
3949 || GET_CODE (op1
) == CONST_DOUBLE
)
3950 && (GET_CODE (XEXP (op0
, 1)) == CONST_INT
3951 || GET_CODE (XEXP (op0
, 1)) == CONST_DOUBLE
))
3952 return simplify_gen_relational (code
, mode
, cmp_mode
, XEXP (op0
, 0),
3953 simplify_gen_binary (XOR
, cmp_mode
,
3954 XEXP (op0
, 1), op1
));
3956 if (op0code
== POPCOUNT
&& op1
== const0_rtx
)
3962 /* (eq (popcount x) (const_int 0)) -> (eq x (const_int 0)). */
3963 return simplify_gen_relational (EQ
, mode
, GET_MODE (XEXP (op0
, 0)),
3964 XEXP (op0
, 0), const0_rtx
);
3969 /* (ne (popcount x) (const_int 0)) -> (ne x (const_int 0)). */
3970 return simplify_gen_relational (NE
, mode
, GET_MODE (XEXP (op0
, 0)),
3971 XEXP (op0
, 0), const0_rtx
);
3990 /* Convert the known results for EQ, LT, GT, LTU, GTU contained in
3991 KNOWN_RESULT to a CONST_INT, based on the requested comparison CODE
3992 For KNOWN_RESULT to make sense it should be either CMP_EQ, or the
3993 logical OR of one of (CMP_LT, CMP_GT) and one of (CMP_LTU, CMP_GTU).
3994 For floating-point comparisons, assume that the operands were ordered. */
3997 comparison_result (enum rtx_code code
, int known_results
)
4003 return (known_results
& CMP_EQ
) ? const_true_rtx
: const0_rtx
;
4006 return (known_results
& CMP_EQ
) ? const0_rtx
: const_true_rtx
;
4010 return (known_results
& CMP_LT
) ? const_true_rtx
: const0_rtx
;
4013 return (known_results
& CMP_LT
) ? const0_rtx
: const_true_rtx
;
4017 return (known_results
& CMP_GT
) ? const_true_rtx
: const0_rtx
;
4020 return (known_results
& CMP_GT
) ? const0_rtx
: const_true_rtx
;
4023 return (known_results
& CMP_LTU
) ? const_true_rtx
: const0_rtx
;
4025 return (known_results
& CMP_LTU
) ? const0_rtx
: const_true_rtx
;
4028 return (known_results
& CMP_GTU
) ? const_true_rtx
: const0_rtx
;
4030 return (known_results
& CMP_GTU
) ? const0_rtx
: const_true_rtx
;
4033 return const_true_rtx
;
4041 /* Check if the given comparison (done in the given MODE) is actually a
4042 tautology or a contradiction.
4043 If no simplification is possible, this function returns zero.
4044 Otherwise, it returns either const_true_rtx or const0_rtx. */
4047 simplify_const_relational_operation (enum rtx_code code
,
4048 enum machine_mode mode
,
4055 gcc_assert (mode
!= VOIDmode
4056 || (GET_MODE (op0
) == VOIDmode
4057 && GET_MODE (op1
) == VOIDmode
));
4059 /* If op0 is a compare, extract the comparison arguments from it. */
4060 if (GET_CODE (op0
) == COMPARE
&& op1
== const0_rtx
)
4062 op1
= XEXP (op0
, 1);
4063 op0
= XEXP (op0
, 0);
4065 if (GET_MODE (op0
) != VOIDmode
)
4066 mode
= GET_MODE (op0
);
4067 else if (GET_MODE (op1
) != VOIDmode
)
4068 mode
= GET_MODE (op1
);
4073 /* We can't simplify MODE_CC values since we don't know what the
4074 actual comparison is. */
4075 if (GET_MODE_CLASS (GET_MODE (op0
)) == MODE_CC
|| CC0_P (op0
))
4078 /* Make sure the constant is second. */
4079 if (swap_commutative_operands_p (op0
, op1
))
4081 tem
= op0
, op0
= op1
, op1
= tem
;
4082 code
= swap_condition (code
);
4085 trueop0
= avoid_constant_pool_reference (op0
);
4086 trueop1
= avoid_constant_pool_reference (op1
);
4088 /* For integer comparisons of A and B maybe we can simplify A - B and can
4089 then simplify a comparison of that with zero. If A and B are both either
4090 a register or a CONST_INT, this can't help; testing for these cases will
4091 prevent infinite recursion here and speed things up.
4093 We can only do this for EQ and NE comparisons as otherwise we may
4094 lose or introduce overflow which we cannot disregard as undefined as
4095 we do not know the signedness of the operation on either the left or
4096 the right hand side of the comparison. */
4098 if (INTEGRAL_MODE_P (mode
) && trueop1
!= const0_rtx
4099 && (code
== EQ
|| code
== NE
)
4100 && ! ((REG_P (op0
) || GET_CODE (trueop0
) == CONST_INT
)
4101 && (REG_P (op1
) || GET_CODE (trueop1
) == CONST_INT
))
4102 && 0 != (tem
= simplify_binary_operation (MINUS
, mode
, op0
, op1
))
4103 /* We cannot do this if tem is a nonzero address. */
4104 && ! nonzero_address_p (tem
))
4105 return simplify_const_relational_operation (signed_condition (code
),
4106 mode
, tem
, const0_rtx
);
4108 if (! HONOR_NANS (mode
) && code
== ORDERED
)
4109 return const_true_rtx
;
4111 if (! HONOR_NANS (mode
) && code
== UNORDERED
)
4114 /* For modes without NaNs, if the two operands are equal, we know the
4115 result except if they have side-effects. Even with NaNs we know
4116 the result of unordered comparisons and, if signaling NaNs are
4117 irrelevant, also the result of LT/GT/LTGT. */
4118 if ((! HONOR_NANS (GET_MODE (trueop0
))
4119 || code
== UNEQ
|| code
== UNLE
|| code
== UNGE
4120 || ((code
== LT
|| code
== GT
|| code
== LTGT
)
4121 && ! HONOR_SNANS (GET_MODE (trueop0
))))
4122 && rtx_equal_p (trueop0
, trueop1
)
4123 && ! side_effects_p (trueop0
))
4124 return comparison_result (code
, CMP_EQ
);
4126 /* If the operands are floating-point constants, see if we can fold
4128 if (GET_CODE (trueop0
) == CONST_DOUBLE
4129 && GET_CODE (trueop1
) == CONST_DOUBLE
4130 && SCALAR_FLOAT_MODE_P (GET_MODE (trueop0
)))
4132 REAL_VALUE_TYPE d0
, d1
;
4134 REAL_VALUE_FROM_CONST_DOUBLE (d0
, trueop0
);
4135 REAL_VALUE_FROM_CONST_DOUBLE (d1
, trueop1
);
4137 /* Comparisons are unordered iff at least one of the values is NaN. */
4138 if (REAL_VALUE_ISNAN (d0
) || REAL_VALUE_ISNAN (d1
))
4148 return const_true_rtx
;
4161 return comparison_result (code
,
4162 (REAL_VALUES_EQUAL (d0
, d1
) ? CMP_EQ
:
4163 REAL_VALUES_LESS (d0
, d1
) ? CMP_LT
: CMP_GT
));
4166 /* Otherwise, see if the operands are both integers. */
4167 if ((GET_MODE_CLASS (mode
) == MODE_INT
|| mode
== VOIDmode
)
4168 && (GET_CODE (trueop0
) == CONST_DOUBLE
4169 || GET_CODE (trueop0
) == CONST_INT
)
4170 && (GET_CODE (trueop1
) == CONST_DOUBLE
4171 || GET_CODE (trueop1
) == CONST_INT
))
4173 int width
= GET_MODE_BITSIZE (mode
);
4174 HOST_WIDE_INT l0s
, h0s
, l1s
, h1s
;
4175 unsigned HOST_WIDE_INT l0u
, h0u
, l1u
, h1u
;
4177 /* Get the two words comprising each integer constant. */
4178 if (GET_CODE (trueop0
) == CONST_DOUBLE
)
4180 l0u
= l0s
= CONST_DOUBLE_LOW (trueop0
);
4181 h0u
= h0s
= CONST_DOUBLE_HIGH (trueop0
);
4185 l0u
= l0s
= INTVAL (trueop0
);
4186 h0u
= h0s
= HWI_SIGN_EXTEND (l0s
);
4189 if (GET_CODE (trueop1
) == CONST_DOUBLE
)
4191 l1u
= l1s
= CONST_DOUBLE_LOW (trueop1
);
4192 h1u
= h1s
= CONST_DOUBLE_HIGH (trueop1
);
4196 l1u
= l1s
= INTVAL (trueop1
);
4197 h1u
= h1s
= HWI_SIGN_EXTEND (l1s
);
4200 /* If WIDTH is nonzero and smaller than HOST_BITS_PER_WIDE_INT,
4201 we have to sign or zero-extend the values. */
4202 if (width
!= 0 && width
< HOST_BITS_PER_WIDE_INT
)
4204 l0u
&= ((HOST_WIDE_INT
) 1 << width
) - 1;
4205 l1u
&= ((HOST_WIDE_INT
) 1 << width
) - 1;
4207 if (l0s
& ((HOST_WIDE_INT
) 1 << (width
- 1)))
4208 l0s
|= ((HOST_WIDE_INT
) (-1) << width
);
4210 if (l1s
& ((HOST_WIDE_INT
) 1 << (width
- 1)))
4211 l1s
|= ((HOST_WIDE_INT
) (-1) << width
);
4213 if (width
!= 0 && width
<= HOST_BITS_PER_WIDE_INT
)
4214 h0u
= h1u
= 0, h0s
= HWI_SIGN_EXTEND (l0s
), h1s
= HWI_SIGN_EXTEND (l1s
);
4216 if (h0u
== h1u
&& l0u
== l1u
)
4217 return comparison_result (code
, CMP_EQ
);
4221 cr
= (h0s
< h1s
|| (h0s
== h1s
&& l0u
< l1u
)) ? CMP_LT
: CMP_GT
;
4222 cr
|= (h0u
< h1u
|| (h0u
== h1u
&& l0u
< l1u
)) ? CMP_LTU
: CMP_GTU
;
4223 return comparison_result (code
, cr
);
4227 /* Optimize comparisons with upper and lower bounds. */
4228 if (SCALAR_INT_MODE_P (mode
)
4229 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4230 && GET_CODE (trueop1
) == CONST_INT
)
4233 unsigned HOST_WIDE_INT nonzero
= nonzero_bits (trueop0
, mode
);
4234 HOST_WIDE_INT val
= INTVAL (trueop1
);
4235 HOST_WIDE_INT mmin
, mmax
;
4245 /* Get a reduced range if the sign bit is zero. */
4246 if (nonzero
<= (GET_MODE_MASK (mode
) >> 1))
4253 rtx mmin_rtx
, mmax_rtx
;
4254 get_mode_bounds (mode
, sign
, mode
, &mmin_rtx
, &mmax_rtx
);
4256 mmin
= INTVAL (mmin_rtx
);
4257 mmax
= INTVAL (mmax_rtx
);
4260 unsigned int sign_copies
= num_sign_bit_copies (trueop0
, mode
);
4262 mmin
>>= (sign_copies
- 1);
4263 mmax
>>= (sign_copies
- 1);
4269 /* x >= y is always true for y <= mmin, always false for y > mmax. */
4271 if ((unsigned HOST_WIDE_INT
) val
<= (unsigned HOST_WIDE_INT
) mmin
)
4272 return const_true_rtx
;
4273 if ((unsigned HOST_WIDE_INT
) val
> (unsigned HOST_WIDE_INT
) mmax
)
4278 return const_true_rtx
;
4283 /* x <= y is always true for y >= mmax, always false for y < mmin. */
4285 if ((unsigned HOST_WIDE_INT
) val
>= (unsigned HOST_WIDE_INT
) mmax
)
4286 return const_true_rtx
;
4287 if ((unsigned HOST_WIDE_INT
) val
< (unsigned HOST_WIDE_INT
) mmin
)
4292 return const_true_rtx
;
4298 /* x == y is always false for y out of range. */
4299 if (val
< mmin
|| val
> mmax
)
4303 /* x > y is always false for y >= mmax, always true for y < mmin. */
4305 if ((unsigned HOST_WIDE_INT
) val
>= (unsigned HOST_WIDE_INT
) mmax
)
4307 if ((unsigned HOST_WIDE_INT
) val
< (unsigned HOST_WIDE_INT
) mmin
)
4308 return const_true_rtx
;
4314 return const_true_rtx
;
4317 /* x < y is always false for y <= mmin, always true for y > mmax. */
4319 if ((unsigned HOST_WIDE_INT
) val
<= (unsigned HOST_WIDE_INT
) mmin
)
4321 if ((unsigned HOST_WIDE_INT
) val
> (unsigned HOST_WIDE_INT
) mmax
)
4322 return const_true_rtx
;
4328 return const_true_rtx
;
4332 /* x != y is always true for y out of range. */
4333 if (val
< mmin
|| val
> mmax
)
4334 return const_true_rtx
;
4342 /* Optimize integer comparisons with zero. */
4343 if (trueop1
== const0_rtx
)
4345 /* Some addresses are known to be nonzero. We don't know
4346 their sign, but equality comparisons are known. */
4347 if (nonzero_address_p (trueop0
))
4349 if (code
== EQ
|| code
== LEU
)
4351 if (code
== NE
|| code
== GTU
)
4352 return const_true_rtx
;
4355 /* See if the first operand is an IOR with a constant. If so, we
4356 may be able to determine the result of this comparison. */
4357 if (GET_CODE (op0
) == IOR
)
4359 rtx inner_const
= avoid_constant_pool_reference (XEXP (op0
, 1));
4360 if (GET_CODE (inner_const
) == CONST_INT
&& inner_const
!= const0_rtx
)
4362 int sign_bitnum
= GET_MODE_BITSIZE (mode
) - 1;
4363 int has_sign
= (HOST_BITS_PER_WIDE_INT
>= sign_bitnum
4364 && (INTVAL (inner_const
)
4365 & ((HOST_WIDE_INT
) 1 << sign_bitnum
)));
4374 return const_true_rtx
;
4378 return const_true_rtx
;
4392 /* Optimize comparison of ABS with zero. */
4393 if (trueop1
== CONST0_RTX (mode
)
4394 && (GET_CODE (trueop0
) == ABS
4395 || (GET_CODE (trueop0
) == FLOAT_EXTEND
4396 && GET_CODE (XEXP (trueop0
, 0)) == ABS
)))
4401 /* Optimize abs(x) < 0.0. */
4402 if (!HONOR_SNANS (mode
)
4403 && (!INTEGRAL_MODE_P (mode
)
4404 || (!flag_wrapv
&& !flag_trapv
&& flag_strict_overflow
)))
4406 if (INTEGRAL_MODE_P (mode
)
4407 && (issue_strict_overflow_warning
4408 (WARN_STRICT_OVERFLOW_CONDITIONAL
)))
4409 warning (OPT_Wstrict_overflow
,
4410 ("assuming signed overflow does not occur when "
4411 "assuming abs (x) < 0 is false"));
4417 /* Optimize abs(x) >= 0.0. */
4418 if (!HONOR_NANS (mode
)
4419 && (!INTEGRAL_MODE_P (mode
)
4420 || (!flag_wrapv
&& !flag_trapv
&& flag_strict_overflow
)))
4422 if (INTEGRAL_MODE_P (mode
)
4423 && (issue_strict_overflow_warning
4424 (WARN_STRICT_OVERFLOW_CONDITIONAL
)))
4425 warning (OPT_Wstrict_overflow
,
4426 ("assuming signed overflow does not occur when "
4427 "assuming abs (x) >= 0 is true"));
4428 return const_true_rtx
;
4433 /* Optimize ! (abs(x) < 0.0). */
4434 return const_true_rtx
;
4444 /* Simplify CODE, an operation with result mode MODE and three operands,
4445 OP0, OP1, and OP2. OP0_MODE was the mode of OP0 before it became
4446 a constant. Return 0 if no simplifications is possible. */
4449 simplify_ternary_operation (enum rtx_code code
, enum machine_mode mode
,
4450 enum machine_mode op0_mode
, rtx op0
, rtx op1
,
4453 unsigned int width
= GET_MODE_BITSIZE (mode
);
4455 /* VOIDmode means "infinite" precision. */
4457 width
= HOST_BITS_PER_WIDE_INT
;
4463 if (GET_CODE (op0
) == CONST_INT
4464 && GET_CODE (op1
) == CONST_INT
4465 && GET_CODE (op2
) == CONST_INT
4466 && ((unsigned) INTVAL (op1
) + (unsigned) INTVAL (op2
) <= width
)
4467 && width
<= (unsigned) HOST_BITS_PER_WIDE_INT
)
4469 /* Extracting a bit-field from a constant */
4470 HOST_WIDE_INT val
= INTVAL (op0
);
4472 if (BITS_BIG_ENDIAN
)
4473 val
>>= (GET_MODE_BITSIZE (op0_mode
)
4474 - INTVAL (op2
) - INTVAL (op1
));
4476 val
>>= INTVAL (op2
);
4478 if (HOST_BITS_PER_WIDE_INT
!= INTVAL (op1
))
4480 /* First zero-extend. */
4481 val
&= ((HOST_WIDE_INT
) 1 << INTVAL (op1
)) - 1;
4482 /* If desired, propagate sign bit. */
4483 if (code
== SIGN_EXTRACT
4484 && (val
& ((HOST_WIDE_INT
) 1 << (INTVAL (op1
) - 1))))
4485 val
|= ~ (((HOST_WIDE_INT
) 1 << INTVAL (op1
)) - 1);
4488 /* Clear the bits that don't belong in our mode,
4489 unless they and our sign bit are all one.
4490 So we get either a reasonable negative value or a reasonable
4491 unsigned value for this mode. */
4492 if (width
< HOST_BITS_PER_WIDE_INT
4493 && ((val
& ((HOST_WIDE_INT
) (-1) << (width
- 1)))
4494 != ((HOST_WIDE_INT
) (-1) << (width
- 1))))
4495 val
&= ((HOST_WIDE_INT
) 1 << width
) - 1;
4497 return gen_int_mode (val
, mode
);
4502 if (GET_CODE (op0
) == CONST_INT
)
4503 return op0
!= const0_rtx
? op1
: op2
;
4505 /* Convert c ? a : a into "a". */
4506 if (rtx_equal_p (op1
, op2
) && ! side_effects_p (op0
))
4509 /* Convert a != b ? a : b into "a". */
4510 if (GET_CODE (op0
) == NE
4511 && ! side_effects_p (op0
)
4512 && ! HONOR_NANS (mode
)
4513 && ! HONOR_SIGNED_ZEROS (mode
)
4514 && ((rtx_equal_p (XEXP (op0
, 0), op1
)
4515 && rtx_equal_p (XEXP (op0
, 1), op2
))
4516 || (rtx_equal_p (XEXP (op0
, 0), op2
)
4517 && rtx_equal_p (XEXP (op0
, 1), op1
))))
4520 /* Convert a == b ? a : b into "b". */
4521 if (GET_CODE (op0
) == EQ
4522 && ! side_effects_p (op0
)
4523 && ! HONOR_NANS (mode
)
4524 && ! HONOR_SIGNED_ZEROS (mode
)
4525 && ((rtx_equal_p (XEXP (op0
, 0), op1
)
4526 && rtx_equal_p (XEXP (op0
, 1), op2
))
4527 || (rtx_equal_p (XEXP (op0
, 0), op2
)
4528 && rtx_equal_p (XEXP (op0
, 1), op1
))))
4531 if (COMPARISON_P (op0
) && ! side_effects_p (op0
))
4533 enum machine_mode cmp_mode
= (GET_MODE (XEXP (op0
, 0)) == VOIDmode
4534 ? GET_MODE (XEXP (op0
, 1))
4535 : GET_MODE (XEXP (op0
, 0)));
4538 /* Look for happy constants in op1 and op2. */
4539 if (GET_CODE (op1
) == CONST_INT
&& GET_CODE (op2
) == CONST_INT
)
4541 HOST_WIDE_INT t
= INTVAL (op1
);
4542 HOST_WIDE_INT f
= INTVAL (op2
);
4544 if (t
== STORE_FLAG_VALUE
&& f
== 0)
4545 code
= GET_CODE (op0
);
4546 else if (t
== 0 && f
== STORE_FLAG_VALUE
)
4549 tmp
= reversed_comparison_code (op0
, NULL_RTX
);
4557 return simplify_gen_relational (code
, mode
, cmp_mode
,
4558 XEXP (op0
, 0), XEXP (op0
, 1));
4561 if (cmp_mode
== VOIDmode
)
4562 cmp_mode
= op0_mode
;
4563 temp
= simplify_relational_operation (GET_CODE (op0
), op0_mode
,
4564 cmp_mode
, XEXP (op0
, 0),
4567 /* See if any simplifications were possible. */
4570 if (GET_CODE (temp
) == CONST_INT
)
4571 return temp
== const0_rtx
? op2
: op1
;
4573 return gen_rtx_IF_THEN_ELSE (mode
, temp
, op1
, op2
);
4579 gcc_assert (GET_MODE (op0
) == mode
);
4580 gcc_assert (GET_MODE (op1
) == mode
);
4581 gcc_assert (VECTOR_MODE_P (mode
));
4582 op2
= avoid_constant_pool_reference (op2
);
4583 if (GET_CODE (op2
) == CONST_INT
)
4585 int elt_size
= GET_MODE_SIZE (GET_MODE_INNER (mode
));
4586 unsigned n_elts
= (GET_MODE_SIZE (mode
) / elt_size
);
4587 int mask
= (1 << n_elts
) - 1;
4589 if (!(INTVAL (op2
) & mask
))
4591 if ((INTVAL (op2
) & mask
) == mask
)
4594 op0
= avoid_constant_pool_reference (op0
);
4595 op1
= avoid_constant_pool_reference (op1
);
4596 if (GET_CODE (op0
) == CONST_VECTOR
4597 && GET_CODE (op1
) == CONST_VECTOR
)
4599 rtvec v
= rtvec_alloc (n_elts
);
4602 for (i
= 0; i
< n_elts
; i
++)
4603 RTVEC_ELT (v
, i
) = (INTVAL (op2
) & (1 << i
)
4604 ? CONST_VECTOR_ELT (op0
, i
)
4605 : CONST_VECTOR_ELT (op1
, i
));
4606 return gen_rtx_CONST_VECTOR (mode
, v
);
4618 /* Evaluate a SUBREG of a CONST_INT or CONST_DOUBLE or CONST_FIXED
4620 returning another CONST_INT or CONST_DOUBLE or CONST_FIXED or CONST_VECTOR.
4622 Works by unpacking OP into a collection of 8-bit values
4623 represented as a little-endian array of 'unsigned char', selecting by BYTE,
4624 and then repacking them again for OUTERMODE. */
4627 simplify_immed_subreg (enum machine_mode outermode
, rtx op
,
4628 enum machine_mode innermode
, unsigned int byte
)
4630 /* We support up to 512-bit values (for V8DFmode). */
4634 value_mask
= (1 << value_bit
) - 1
4636 unsigned char value
[max_bitsize
/ value_bit
];
4645 rtvec result_v
= NULL
;
4646 enum mode_class outer_class
;
4647 enum machine_mode outer_submode
;
4649 /* Some ports misuse CCmode. */
4650 if (GET_MODE_CLASS (outermode
) == MODE_CC
&& GET_CODE (op
) == CONST_INT
)
4653 /* We have no way to represent a complex constant at the rtl level. */
4654 if (COMPLEX_MODE_P (outermode
))
4657 /* Unpack the value. */
4659 if (GET_CODE (op
) == CONST_VECTOR
)
4661 num_elem
= CONST_VECTOR_NUNITS (op
);
4662 elems
= &CONST_VECTOR_ELT (op
, 0);
4663 elem_bitsize
= GET_MODE_BITSIZE (GET_MODE_INNER (innermode
));
4669 elem_bitsize
= max_bitsize
;
4671 /* If this asserts, it is too complicated; reducing value_bit may help. */
4672 gcc_assert (BITS_PER_UNIT
% value_bit
== 0);
4673 /* I don't know how to handle endianness of sub-units. */
4674 gcc_assert (elem_bitsize
% BITS_PER_UNIT
== 0);
4676 for (elem
= 0; elem
< num_elem
; elem
++)
4679 rtx el
= elems
[elem
];
4681 /* Vectors are kept in target memory order. (This is probably
4684 unsigned byte
= (elem
* elem_bitsize
) / BITS_PER_UNIT
;
4685 unsigned ibyte
= (((num_elem
- 1 - elem
) * elem_bitsize
)
4687 unsigned word_byte
= WORDS_BIG_ENDIAN
? ibyte
: byte
;
4688 unsigned subword_byte
= BYTES_BIG_ENDIAN
? ibyte
: byte
;
4689 unsigned bytele
= (subword_byte
% UNITS_PER_WORD
4690 + (word_byte
/ UNITS_PER_WORD
) * UNITS_PER_WORD
);
4691 vp
= value
+ (bytele
* BITS_PER_UNIT
) / value_bit
;
4694 switch (GET_CODE (el
))
4698 i
< HOST_BITS_PER_WIDE_INT
&& i
< elem_bitsize
;
4700 *vp
++ = INTVAL (el
) >> i
;
4701 /* CONST_INTs are always logically sign-extended. */
4702 for (; i
< elem_bitsize
; i
+= value_bit
)
4703 *vp
++ = INTVAL (el
) < 0 ? -1 : 0;
4707 if (GET_MODE (el
) == VOIDmode
)
4709 /* If this triggers, someone should have generated a
4710 CONST_INT instead. */
4711 gcc_assert (elem_bitsize
> HOST_BITS_PER_WIDE_INT
);
4713 for (i
= 0; i
< HOST_BITS_PER_WIDE_INT
; i
+= value_bit
)
4714 *vp
++ = CONST_DOUBLE_LOW (el
) >> i
;
4715 while (i
< HOST_BITS_PER_WIDE_INT
* 2 && i
< elem_bitsize
)
4718 = CONST_DOUBLE_HIGH (el
) >> (i
- HOST_BITS_PER_WIDE_INT
);
4721 /* It shouldn't matter what's done here, so fill it with
4723 for (; i
< elem_bitsize
; i
+= value_bit
)
4728 long tmp
[max_bitsize
/ 32];
4729 int bitsize
= GET_MODE_BITSIZE (GET_MODE (el
));
4731 gcc_assert (SCALAR_FLOAT_MODE_P (GET_MODE (el
)));
4732 gcc_assert (bitsize
<= elem_bitsize
);
4733 gcc_assert (bitsize
% value_bit
== 0);
4735 real_to_target (tmp
, CONST_DOUBLE_REAL_VALUE (el
),
4738 /* real_to_target produces its result in words affected by
4739 FLOAT_WORDS_BIG_ENDIAN. However, we ignore this,
4740 and use WORDS_BIG_ENDIAN instead; see the documentation
4741 of SUBREG in rtl.texi. */
4742 for (i
= 0; i
< bitsize
; i
+= value_bit
)
4745 if (WORDS_BIG_ENDIAN
)
4746 ibase
= bitsize
- 1 - i
;
4749 *vp
++ = tmp
[ibase
/ 32] >> i
% 32;
4752 /* It shouldn't matter what's done here, so fill it with
4754 for (; i
< elem_bitsize
; i
+= value_bit
)
4760 if (elem_bitsize
<= HOST_BITS_PER_WIDE_INT
)
4762 for (i
= 0; i
< elem_bitsize
; i
+= value_bit
)
4763 *vp
++ = CONST_FIXED_VALUE_LOW (el
) >> i
;
4767 for (i
= 0; i
< HOST_BITS_PER_WIDE_INT
; i
+= value_bit
)
4768 *vp
++ = CONST_FIXED_VALUE_LOW (el
) >> i
;
4769 for (; i
< 2 * HOST_BITS_PER_WIDE_INT
&& i
< elem_bitsize
;
4771 *vp
++ = CONST_FIXED_VALUE_HIGH (el
)
4772 >> (i
- HOST_BITS_PER_WIDE_INT
);
4773 for (; i
< elem_bitsize
; i
+= value_bit
)
4783 /* Now, pick the right byte to start with. */
4784 /* Renumber BYTE so that the least-significant byte is byte 0. A special
4785 case is paradoxical SUBREGs, which shouldn't be adjusted since they
4786 will already have offset 0. */
4787 if (GET_MODE_SIZE (innermode
) >= GET_MODE_SIZE (outermode
))
4789 unsigned ibyte
= (GET_MODE_SIZE (innermode
) - GET_MODE_SIZE (outermode
)
4791 unsigned word_byte
= WORDS_BIG_ENDIAN
? ibyte
: byte
;
4792 unsigned subword_byte
= BYTES_BIG_ENDIAN
? ibyte
: byte
;
4793 byte
= (subword_byte
% UNITS_PER_WORD
4794 + (word_byte
/ UNITS_PER_WORD
) * UNITS_PER_WORD
);
4797 /* BYTE should still be inside OP. (Note that BYTE is unsigned,
4798 so if it's become negative it will instead be very large.) */
4799 gcc_assert (byte
< GET_MODE_SIZE (innermode
));
4801 /* Convert from bytes to chunks of size value_bit. */
4802 value_start
= byte
* (BITS_PER_UNIT
/ value_bit
);
4804 /* Re-pack the value. */
4806 if (VECTOR_MODE_P (outermode
))
4808 num_elem
= GET_MODE_NUNITS (outermode
);
4809 result_v
= rtvec_alloc (num_elem
);
4810 elems
= &RTVEC_ELT (result_v
, 0);
4811 outer_submode
= GET_MODE_INNER (outermode
);
4817 outer_submode
= outermode
;
4820 outer_class
= GET_MODE_CLASS (outer_submode
);
4821 elem_bitsize
= GET_MODE_BITSIZE (outer_submode
);
4823 gcc_assert (elem_bitsize
% value_bit
== 0);
4824 gcc_assert (elem_bitsize
+ value_start
* value_bit
<= max_bitsize
);
4826 for (elem
= 0; elem
< num_elem
; elem
++)
4830 /* Vectors are stored in target memory order. (This is probably
4833 unsigned byte
= (elem
* elem_bitsize
) / BITS_PER_UNIT
;
4834 unsigned ibyte
= (((num_elem
- 1 - elem
) * elem_bitsize
)
4836 unsigned word_byte
= WORDS_BIG_ENDIAN
? ibyte
: byte
;
4837 unsigned subword_byte
= BYTES_BIG_ENDIAN
? ibyte
: byte
;
4838 unsigned bytele
= (subword_byte
% UNITS_PER_WORD
4839 + (word_byte
/ UNITS_PER_WORD
) * UNITS_PER_WORD
);
4840 vp
= value
+ value_start
+ (bytele
* BITS_PER_UNIT
) / value_bit
;
4843 switch (outer_class
)
4846 case MODE_PARTIAL_INT
:
4848 unsigned HOST_WIDE_INT hi
= 0, lo
= 0;
4851 i
< HOST_BITS_PER_WIDE_INT
&& i
< elem_bitsize
;
4853 lo
|= (HOST_WIDE_INT
)(*vp
++ & value_mask
) << i
;
4854 for (; i
< elem_bitsize
; i
+= value_bit
)
4855 hi
|= ((HOST_WIDE_INT
)(*vp
++ & value_mask
)
4856 << (i
- HOST_BITS_PER_WIDE_INT
));
4858 /* immed_double_const doesn't call trunc_int_for_mode. I don't
4860 if (elem_bitsize
<= HOST_BITS_PER_WIDE_INT
)
4861 elems
[elem
] = gen_int_mode (lo
, outer_submode
);
4862 else if (elem_bitsize
<= 2 * HOST_BITS_PER_WIDE_INT
)
4863 elems
[elem
] = immed_double_const (lo
, hi
, outer_submode
);
4870 case MODE_DECIMAL_FLOAT
:
4873 long tmp
[max_bitsize
/ 32];
4875 /* real_from_target wants its input in words affected by
4876 FLOAT_WORDS_BIG_ENDIAN. However, we ignore this,
4877 and use WORDS_BIG_ENDIAN instead; see the documentation
4878 of SUBREG in rtl.texi. */
4879 for (i
= 0; i
< max_bitsize
/ 32; i
++)
4881 for (i
= 0; i
< elem_bitsize
; i
+= value_bit
)
4884 if (WORDS_BIG_ENDIAN
)
4885 ibase
= elem_bitsize
- 1 - i
;
4888 tmp
[ibase
/ 32] |= (*vp
++ & value_mask
) << i
% 32;
4891 real_from_target (&r
, tmp
, outer_submode
);
4892 elems
[elem
] = CONST_DOUBLE_FROM_REAL_VALUE (r
, outer_submode
);
4904 f
.mode
= outer_submode
;
4907 i
< HOST_BITS_PER_WIDE_INT
&& i
< elem_bitsize
;
4909 f
.data
.low
|= (HOST_WIDE_INT
)(*vp
++ & value_mask
) << i
;
4910 for (; i
< elem_bitsize
; i
+= value_bit
)
4911 f
.data
.high
|= ((HOST_WIDE_INT
)(*vp
++ & value_mask
)
4912 << (i
- HOST_BITS_PER_WIDE_INT
));
4914 elems
[elem
] = CONST_FIXED_FROM_FIXED_VALUE (f
, outer_submode
);
4922 if (VECTOR_MODE_P (outermode
))
4923 return gen_rtx_CONST_VECTOR (outermode
, result_v
);
4928 /* Simplify SUBREG:OUTERMODE(OP:INNERMODE, BYTE)
4929 Return 0 if no simplifications are possible. */
4931 simplify_subreg (enum machine_mode outermode
, rtx op
,
4932 enum machine_mode innermode
, unsigned int byte
)
4934 /* Little bit of sanity checking. */
4935 gcc_assert (innermode
!= VOIDmode
);
4936 gcc_assert (outermode
!= VOIDmode
);
4937 gcc_assert (innermode
!= BLKmode
);
4938 gcc_assert (outermode
!= BLKmode
);
4940 gcc_assert (GET_MODE (op
) == innermode
4941 || GET_MODE (op
) == VOIDmode
);
4943 gcc_assert ((byte
% GET_MODE_SIZE (outermode
)) == 0);
4944 gcc_assert (byte
< GET_MODE_SIZE (innermode
));
4946 if (outermode
== innermode
&& !byte
)
4949 if (GET_CODE (op
) == CONST_INT
4950 || GET_CODE (op
) == CONST_DOUBLE
4951 || GET_CODE (op
) == CONST_FIXED
4952 || GET_CODE (op
) == CONST_VECTOR
)
4953 return simplify_immed_subreg (outermode
, op
, innermode
, byte
);
4955 /* Changing mode twice with SUBREG => just change it once,
4956 or not at all if changing back op starting mode. */
4957 if (GET_CODE (op
) == SUBREG
)
4959 enum machine_mode innermostmode
= GET_MODE (SUBREG_REG (op
));
4960 int final_offset
= byte
+ SUBREG_BYTE (op
);
4963 if (outermode
== innermostmode
4964 && byte
== 0 && SUBREG_BYTE (op
) == 0)
4965 return SUBREG_REG (op
);
4967 /* The SUBREG_BYTE represents offset, as if the value were stored
4968 in memory. Irritating exception is paradoxical subreg, where
4969 we define SUBREG_BYTE to be 0. On big endian machines, this
4970 value should be negative. For a moment, undo this exception. */
4971 if (byte
== 0 && GET_MODE_SIZE (innermode
) < GET_MODE_SIZE (outermode
))
4973 int difference
= (GET_MODE_SIZE (innermode
) - GET_MODE_SIZE (outermode
));
4974 if (WORDS_BIG_ENDIAN
)
4975 final_offset
+= (difference
/ UNITS_PER_WORD
) * UNITS_PER_WORD
;
4976 if (BYTES_BIG_ENDIAN
)
4977 final_offset
+= difference
% UNITS_PER_WORD
;
4979 if (SUBREG_BYTE (op
) == 0
4980 && GET_MODE_SIZE (innermostmode
) < GET_MODE_SIZE (innermode
))
4982 int difference
= (GET_MODE_SIZE (innermostmode
) - GET_MODE_SIZE (innermode
));
4983 if (WORDS_BIG_ENDIAN
)
4984 final_offset
+= (difference
/ UNITS_PER_WORD
) * UNITS_PER_WORD
;
4985 if (BYTES_BIG_ENDIAN
)
4986 final_offset
+= difference
% UNITS_PER_WORD
;
4989 /* See whether resulting subreg will be paradoxical. */
4990 if (GET_MODE_SIZE (innermostmode
) > GET_MODE_SIZE (outermode
))
4992 /* In nonparadoxical subregs we can't handle negative offsets. */
4993 if (final_offset
< 0)
4995 /* Bail out in case resulting subreg would be incorrect. */
4996 if (final_offset
% GET_MODE_SIZE (outermode
)
4997 || (unsigned) final_offset
>= GET_MODE_SIZE (innermostmode
))
5003 int difference
= (GET_MODE_SIZE (innermostmode
) - GET_MODE_SIZE (outermode
));
5005 /* In paradoxical subreg, see if we are still looking on lower part.
5006 If so, our SUBREG_BYTE will be 0. */
5007 if (WORDS_BIG_ENDIAN
)
5008 offset
+= (difference
/ UNITS_PER_WORD
) * UNITS_PER_WORD
;
5009 if (BYTES_BIG_ENDIAN
)
5010 offset
+= difference
% UNITS_PER_WORD
;
5011 if (offset
== final_offset
)
5017 /* Recurse for further possible simplifications. */
5018 newx
= simplify_subreg (outermode
, SUBREG_REG (op
), innermostmode
,
5022 if (validate_subreg (outermode
, innermostmode
,
5023 SUBREG_REG (op
), final_offset
))
5024 return gen_rtx_SUBREG (outermode
, SUBREG_REG (op
), final_offset
);
5028 /* Merge implicit and explicit truncations. */
5030 if (GET_CODE (op
) == TRUNCATE
5031 && GET_MODE_SIZE (outermode
) < GET_MODE_SIZE (innermode
)
5032 && subreg_lowpart_offset (outermode
, innermode
) == byte
)
5033 return simplify_gen_unary (TRUNCATE
, outermode
, XEXP (op
, 0),
5034 GET_MODE (XEXP (op
, 0)));
5036 /* SUBREG of a hard register => just change the register number
5037 and/or mode. If the hard register is not valid in that mode,
5038 suppress this simplification. If the hard register is the stack,
5039 frame, or argument pointer, leave this as a SUBREG. */
5042 && REGNO (op
) < FIRST_PSEUDO_REGISTER
5043 #ifdef CANNOT_CHANGE_MODE_CLASS
5044 && ! (REG_CANNOT_CHANGE_MODE_P (REGNO (op
), innermode
, outermode
)
5045 && GET_MODE_CLASS (innermode
) != MODE_COMPLEX_INT
5046 && GET_MODE_CLASS (innermode
) != MODE_COMPLEX_FLOAT
)
5048 && ((reload_completed
&& !frame_pointer_needed
)
5049 || (REGNO (op
) != FRAME_POINTER_REGNUM
5050 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
5051 && REGNO (op
) != HARD_FRAME_POINTER_REGNUM
5054 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
5055 && REGNO (op
) != ARG_POINTER_REGNUM
5057 && REGNO (op
) != STACK_POINTER_REGNUM
5058 && subreg_offset_representable_p (REGNO (op
), innermode
,
5061 unsigned int regno
= REGNO (op
);
5062 unsigned int final_regno
5063 = regno
+ subreg_regno_offset (regno
, innermode
, byte
, outermode
);
5065 /* ??? We do allow it if the current REG is not valid for
5066 its mode. This is a kludge to work around how float/complex
5067 arguments are passed on 32-bit SPARC and should be fixed. */
5068 if (HARD_REGNO_MODE_OK (final_regno
, outermode
)
5069 || ! HARD_REGNO_MODE_OK (regno
, innermode
))
5072 int final_offset
= byte
;
5074 /* Adjust offset for paradoxical subregs. */
5076 && GET_MODE_SIZE (innermode
) < GET_MODE_SIZE (outermode
))
5078 int difference
= (GET_MODE_SIZE (innermode
)
5079 - GET_MODE_SIZE (outermode
));
5080 if (WORDS_BIG_ENDIAN
)
5081 final_offset
+= (difference
/ UNITS_PER_WORD
) * UNITS_PER_WORD
;
5082 if (BYTES_BIG_ENDIAN
)
5083 final_offset
+= difference
% UNITS_PER_WORD
;
5086 x
= gen_rtx_REG_offset (op
, outermode
, final_regno
, final_offset
);
5088 /* Propagate original regno. We don't have any way to specify
5089 the offset inside original regno, so do so only for lowpart.
5090 The information is used only by alias analysis that can not
5091 grog partial register anyway. */
5093 if (subreg_lowpart_offset (outermode
, innermode
) == byte
)
5094 ORIGINAL_REGNO (x
) = ORIGINAL_REGNO (op
);
5099 /* If we have a SUBREG of a register that we are replacing and we are
5100 replacing it with a MEM, make a new MEM and try replacing the
5101 SUBREG with it. Don't do this if the MEM has a mode-dependent address
5102 or if we would be widening it. */
5105 && ! mode_dependent_address_p (XEXP (op
, 0))
5106 /* Allow splitting of volatile memory references in case we don't
5107 have instruction to move the whole thing. */
5108 && (! MEM_VOLATILE_P (op
)
5109 || ! have_insn_for (SET
, innermode
))
5110 && GET_MODE_SIZE (outermode
) <= GET_MODE_SIZE (GET_MODE (op
)))
5111 return adjust_address_nv (op
, outermode
, byte
);
5113 /* Handle complex values represented as CONCAT
5114 of real and imaginary part. */
5115 if (GET_CODE (op
) == CONCAT
)
5117 unsigned int part_size
, final_offset
;
5120 part_size
= GET_MODE_UNIT_SIZE (GET_MODE (XEXP (op
, 0)));
5121 if (byte
< part_size
)
5123 part
= XEXP (op
, 0);
5124 final_offset
= byte
;
5128 part
= XEXP (op
, 1);
5129 final_offset
= byte
- part_size
;
5132 if (final_offset
+ GET_MODE_SIZE (outermode
) > part_size
)
5135 res
= simplify_subreg (outermode
, part
, GET_MODE (part
), final_offset
);
5138 if (validate_subreg (outermode
, GET_MODE (part
), part
, final_offset
))
5139 return gen_rtx_SUBREG (outermode
, part
, final_offset
);
5143 /* Optimize SUBREG truncations of zero and sign extended values. */
5144 if ((GET_CODE (op
) == ZERO_EXTEND
5145 || GET_CODE (op
) == SIGN_EXTEND
)
5146 && GET_MODE_BITSIZE (outermode
) < GET_MODE_BITSIZE (innermode
))
5148 unsigned int bitpos
= subreg_lsb_1 (outermode
, innermode
, byte
);
5150 /* If we're requesting the lowpart of a zero or sign extension,
5151 there are three possibilities. If the outermode is the same
5152 as the origmode, we can omit both the extension and the subreg.
5153 If the outermode is not larger than the origmode, we can apply
5154 the truncation without the extension. Finally, if the outermode
5155 is larger than the origmode, but both are integer modes, we
5156 can just extend to the appropriate mode. */
5159 enum machine_mode origmode
= GET_MODE (XEXP (op
, 0));
5160 if (outermode
== origmode
)
5161 return XEXP (op
, 0);
5162 if (GET_MODE_BITSIZE (outermode
) <= GET_MODE_BITSIZE (origmode
))
5163 return simplify_gen_subreg (outermode
, XEXP (op
, 0), origmode
,
5164 subreg_lowpart_offset (outermode
,
5166 if (SCALAR_INT_MODE_P (outermode
))
5167 return simplify_gen_unary (GET_CODE (op
), outermode
,
5168 XEXP (op
, 0), origmode
);
5171 /* A SUBREG resulting from a zero extension may fold to zero if
5172 it extracts higher bits that the ZERO_EXTEND's source bits. */
5173 if (GET_CODE (op
) == ZERO_EXTEND
5174 && bitpos
>= GET_MODE_BITSIZE (GET_MODE (XEXP (op
, 0))))
5175 return CONST0_RTX (outermode
);
5178 /* Simplify (subreg:QI (lshiftrt:SI (sign_extend:SI (x:QI)) C), 0) into
5179 to (ashiftrt:QI (x:QI) C), where C is a suitable small constant and
5180 the outer subreg is effectively a truncation to the original mode. */
5181 if ((GET_CODE (op
) == LSHIFTRT
5182 || GET_CODE (op
) == ASHIFTRT
)
5183 && SCALAR_INT_MODE_P (outermode
)
5184 /* Ensure that OUTERMODE is at least twice as wide as the INNERMODE
5185 to avoid the possibility that an outer LSHIFTRT shifts by more
5186 than the sign extension's sign_bit_copies and introduces zeros
5187 into the high bits of the result. */
5188 && (2 * GET_MODE_BITSIZE (outermode
)) <= GET_MODE_BITSIZE (innermode
)
5189 && GET_CODE (XEXP (op
, 1)) == CONST_INT
5190 && GET_CODE (XEXP (op
, 0)) == SIGN_EXTEND
5191 && GET_MODE (XEXP (XEXP (op
, 0), 0)) == outermode
5192 && INTVAL (XEXP (op
, 1)) < GET_MODE_BITSIZE (outermode
)
5193 && subreg_lsb_1 (outermode
, innermode
, byte
) == 0)
5194 return simplify_gen_binary (ASHIFTRT
, outermode
,
5195 XEXP (XEXP (op
, 0), 0), XEXP (op
, 1));
5197 /* Likewise (subreg:QI (lshiftrt:SI (zero_extend:SI (x:QI)) C), 0) into
5198 to (lshiftrt:QI (x:QI) C), where C is a suitable small constant and
5199 the outer subreg is effectively a truncation to the original mode. */
5200 if ((GET_CODE (op
) == LSHIFTRT
5201 || GET_CODE (op
) == ASHIFTRT
)
5202 && SCALAR_INT_MODE_P (outermode
)
5203 && GET_MODE_BITSIZE (outermode
) < GET_MODE_BITSIZE (innermode
)
5204 && GET_CODE (XEXP (op
, 1)) == CONST_INT
5205 && GET_CODE (XEXP (op
, 0)) == ZERO_EXTEND
5206 && GET_MODE (XEXP (XEXP (op
, 0), 0)) == outermode
5207 && INTVAL (XEXP (op
, 1)) < GET_MODE_BITSIZE (outermode
)
5208 && subreg_lsb_1 (outermode
, innermode
, byte
) == 0)
5209 return simplify_gen_binary (LSHIFTRT
, outermode
,
5210 XEXP (XEXP (op
, 0), 0), XEXP (op
, 1));
5212 /* Likewise (subreg:QI (ashift:SI (zero_extend:SI (x:QI)) C), 0) into
5213 to (ashift:QI (x:QI) C), where C is a suitable small constant and
5214 the outer subreg is effectively a truncation to the original mode. */
5215 if (GET_CODE (op
) == ASHIFT
5216 && SCALAR_INT_MODE_P (outermode
)
5217 && GET_MODE_BITSIZE (outermode
) < GET_MODE_BITSIZE (innermode
)
5218 && GET_CODE (XEXP (op
, 1)) == CONST_INT
5219 && (GET_CODE (XEXP (op
, 0)) == ZERO_EXTEND
5220 || GET_CODE (XEXP (op
, 0)) == SIGN_EXTEND
)
5221 && GET_MODE (XEXP (XEXP (op
, 0), 0)) == outermode
5222 && INTVAL (XEXP (op
, 1)) < GET_MODE_BITSIZE (outermode
)
5223 && subreg_lsb_1 (outermode
, innermode
, byte
) == 0)
5224 return simplify_gen_binary (ASHIFT
, outermode
,
5225 XEXP (XEXP (op
, 0), 0), XEXP (op
, 1));
5230 /* Make a SUBREG operation or equivalent if it folds. */
5233 simplify_gen_subreg (enum machine_mode outermode
, rtx op
,
5234 enum machine_mode innermode
, unsigned int byte
)
5238 newx
= simplify_subreg (outermode
, op
, innermode
, byte
);
5242 if (GET_CODE (op
) == SUBREG
5243 || GET_CODE (op
) == CONCAT
5244 || GET_MODE (op
) == VOIDmode
)
5247 if (validate_subreg (outermode
, innermode
, op
, byte
))
5248 return gen_rtx_SUBREG (outermode
, op
, byte
);
5253 /* Simplify X, an rtx expression.
5255 Return the simplified expression or NULL if no simplifications
5258 This is the preferred entry point into the simplification routines;
5259 however, we still allow passes to call the more specific routines.
5261 Right now GCC has three (yes, three) major bodies of RTL simplification
5262 code that need to be unified.
5264 1. fold_rtx in cse.c. This code uses various CSE specific
5265 information to aid in RTL simplification.
5267 2. simplify_rtx in combine.c. Similar to fold_rtx, except that
5268 it uses combine specific information to aid in RTL
5271 3. The routines in this file.
5274 Long term we want to only have one body of simplification code; to
5275 get to that state I recommend the following steps:
5277 1. Pour over fold_rtx & simplify_rtx and move any simplifications
5278 which are not pass dependent state into these routines.
5280 2. As code is moved by #1, change fold_rtx & simplify_rtx to
5281 use this routine whenever possible.
5283 3. Allow for pass dependent state to be provided to these
5284 routines and add simplifications based on the pass dependent
5285 state. Remove code from cse.c & combine.c that becomes
5288 It will take time, but ultimately the compiler will be easier to
5289 maintain and improve. It's totally silly that when we add a
5290 simplification that it needs to be added to 4 places (3 for RTL
5291 simplification and 1 for tree simplification. */
5294 simplify_rtx (const_rtx x
)
5296 const enum rtx_code code
= GET_CODE (x
);
5297 const enum machine_mode mode
= GET_MODE (x
);
5299 switch (GET_RTX_CLASS (code
))
5302 return simplify_unary_operation (code
, mode
,
5303 XEXP (x
, 0), GET_MODE (XEXP (x
, 0)));
5304 case RTX_COMM_ARITH
:
5305 if (swap_commutative_operands_p (XEXP (x
, 0), XEXP (x
, 1)))
5306 return simplify_gen_binary (code
, mode
, XEXP (x
, 1), XEXP (x
, 0));
5308 /* Fall through.... */
5311 return simplify_binary_operation (code
, mode
, XEXP (x
, 0), XEXP (x
, 1));
5314 case RTX_BITFIELD_OPS
:
5315 return simplify_ternary_operation (code
, mode
, GET_MODE (XEXP (x
, 0)),
5316 XEXP (x
, 0), XEXP (x
, 1),
5320 case RTX_COMM_COMPARE
:
5321 return simplify_relational_operation (code
, mode
,
5322 ((GET_MODE (XEXP (x
, 0))
5324 ? GET_MODE (XEXP (x
, 0))
5325 : GET_MODE (XEXP (x
, 1))),
5331 return simplify_subreg (mode
, SUBREG_REG (x
),
5332 GET_MODE (SUBREG_REG (x
)),
5339 /* Convert (lo_sum (high FOO) FOO) to FOO. */
5340 if (GET_CODE (XEXP (x
, 0)) == HIGH
5341 && rtx_equal_p (XEXP (XEXP (x
, 0), 0), XEXP (x
, 1)))