gdb/aarch64-linux-nat.c

   1 /* Native-dependent code for GNU/Linux AArch64.
   2
   3    Copyright (C) 2011-2022 Free Software Foundation, Inc.
   4    Contributed by ARM Ltd.
   5
   6    This file is part of GDB.
   7
   8    This program is free software; you can redistribute it and/or modify
   9    it under the terms of the GNU General Public License as published by
  10    the Free Software Foundation; either version 3 of the License, or
  11    (at your option) any later version.
  12
  13    This program is distributed in the hope that it will be useful,
  14    but WITHOUT ANY WARRANTY; without even the implied warranty of
  15    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16    GNU General Public License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  20
  21 #include "defs.h"
  22
  23 #include "inferior.h"
  24 #include "gdbcore.h"
  25 #include "regcache.h"
  26 #include "linux-nat.h"
  27 #include "target-descriptions.h"
  28 #include "auxv.h"
  29 #include "gdbcmd.h"
  30 #include "aarch64-nat.h"
  31 #include "aarch64-tdep.h"
  32 #include "aarch64-linux-tdep.h"
  33 #include "aarch32-linux-nat.h"
  34 #include "aarch32-tdep.h"
  35 #include "arch/arm.h"
  36 #include "nat/aarch64-linux.h"
  37 #include "nat/aarch64-linux-hw-point.h"
  38 #include "nat/aarch64-sve-linux-ptrace.h"
  39
  40 #include "elf/external.h"
  41 #include "elf/common.h"
  42
  43 #include "nat/gdb_ptrace.h"
  44 #include <sys/utsname.h>
  45 #include <asm/ptrace.h>
  46
  47 #include "gregset.h"
  48 #include "linux-tdep.h"
  49
  50 /* Defines ps_err_e, struct ps_prochandle.  */
  51 #include "gdb_proc_service.h"
  52 #include "arch-utils.h"
  53
  54 #include "arch/aarch64-mte-linux.h"
  55
  56 #include "nat/aarch64-mte-linux-ptrace.h"
  57
  58 #ifndef TRAP_HWBKPT
  59 #define TRAP_HWBKPT 0x0004
  60 #endif
  61
  62 class aarch64_linux_nat_target final
  63   : public aarch64_nat_target<linux_nat_target>
  64 {
  65 public:
  66   /* Add our register access methods.  */
  67   void fetch_registers (struct regcache *, int) override;
  68   void store_registers (struct regcache *, int) override;
  69
  70   const struct target_desc *read_description () override;
  71
  72   /* Add our hardware breakpoint and watchpoint implementation.  */
  73   bool stopped_by_watchpoint () override;
  74   bool stopped_data_address (CORE_ADDR *) override;
  75
  76   int can_do_single_step () override;
  77
  78   /* Override the GNU/Linux inferior startup hook.  */
  79   void post_startup_inferior (ptid_t) override;
  80
  81   /* Override the GNU/Linux post attach hook.  */
  82   void post_attach (int pid) override;
  83
  84   /* These three defer to common nat/ code.  */
  85   void low_new_thread (struct lwp_info *lp) override
  86   { aarch64_linux_new_thread (lp); }
  87   void low_delete_thread (struct arch_lwp_info *lp) override
  88   { aarch64_linux_delete_thread (lp); }
  89   void low_prepare_to_resume (struct lwp_info *lp) override
  90   { aarch64_linux_prepare_to_resume (lp); }
  91
  92   void low_new_fork (struct lwp_info *parent, pid_t child_pid) override;
  93   void low_forget_process (pid_t pid) override;
  94
  95   /* Add our siginfo layout converter.  */
  96   bool low_siginfo_fixup (siginfo_t *ptrace, gdb_byte *inf, int direction)
  97     override;
  98
  99   struct gdbarch *thread_architecture (ptid_t) override;
 100
 101   bool supports_memory_tagging () override;
 102
 103   /* Read memory allocation tags from memory via PTRACE.  */
 104   bool fetch_memtags (CORE_ADDR address, size_t len,
 105                       gdb::byte_vector &tags, int type) override;
 106
 107   /* Write allocation tags to memory via PTRACE.  */
 108   bool store_memtags (CORE_ADDR address, size_t len,
 109                       const gdb::byte_vector &tags, int type) override;
 110 };
 111
 112 static aarch64_linux_nat_target the_aarch64_linux_nat_target;
 113
 114 /* Called whenever GDB is no longer debugging process PID.  It deletes
 115    data structures that keep track of debug register state.  */
 116
 117 void
 118 aarch64_linux_nat_target::low_forget_process (pid_t pid)
 119 {
 120   aarch64_remove_debug_reg_state (pid);
 121 }
 122
 123 /* Fill GDB's register array with the general-purpose register values
 124    from the current thread.  */
 125
 126 static void
 127 fetch_gregs_from_thread (struct regcache *regcache)
 128 {
 129   int ret, tid;
 130   struct gdbarch *gdbarch = regcache->arch ();
 131   elf_gregset_t regs;
 132   struct iovec iovec;
 133
 134   /* Make sure REGS can hold all registers contents on both aarch64
 135      and arm.  */
 136   gdb_static_assert (sizeof (regs) >= 18 * 4);
 137
 138   tid = regcache->ptid ().lwp ();
 139
 140   iovec.iov_base = &regs;
 141   if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 32)
 142     iovec.iov_len = 18 * 4;
 143   else
 144     iovec.iov_len = sizeof (regs);
 145
 146   ret = ptrace (PTRACE_GETREGSET, tid, NT_PRSTATUS, &iovec);
 147   if (ret < 0)
 148     perror_with_name (_("Unable to fetch general registers."));
 149
 150   if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 32)
 151     aarch32_gp_regcache_supply (regcache, (uint32_t *) regs, 1);
 152   else
 153     {
 154       int regno;
 155
 156       for (regno = AARCH64_X0_REGNUM; regno <= AARCH64_CPSR_REGNUM; regno++)
 157         regcache->raw_supply (regno, &regs[regno - AARCH64_X0_REGNUM]);
 158     }
 159 }
 160
 161 /* Store to the current thread the valid general-purpose register
 162    values in the GDB's register array.  */
 163
 164 static void
 165 store_gregs_to_thread (const struct regcache *regcache)
 166 {
 167   int ret, tid;
 168   elf_gregset_t regs;
 169   struct iovec iovec;
 170   struct gdbarch *gdbarch = regcache->arch ();
 171
 172   /* Make sure REGS can hold all registers contents on both aarch64
 173      and arm.  */
 174   gdb_static_assert (sizeof (regs) >= 18 * 4);
 175   tid = regcache->ptid ().lwp ();
 176
 177   iovec.iov_base = &regs;
 178   if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 32)
 179     iovec.iov_len = 18 * 4;
 180   else
 181     iovec.iov_len = sizeof (regs);
 182
 183   ret = ptrace (PTRACE_GETREGSET, tid, NT_PRSTATUS, &iovec);
 184   if (ret < 0)
 185     perror_with_name (_("Unable to fetch general registers."));
 186
 187   if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 32)
 188     aarch32_gp_regcache_collect (regcache, (uint32_t *) regs, 1);
 189   else
 190     {
 191       int regno;
 192
 193       for (regno = AARCH64_X0_REGNUM; regno <= AARCH64_CPSR_REGNUM; regno++)
 194         if (REG_VALID == regcache->get_register_status (regno))
 195           regcache->raw_collect (regno, &regs[regno - AARCH64_X0_REGNUM]);
 196     }
 197
 198   ret = ptrace (PTRACE_SETREGSET, tid, NT_PRSTATUS, &iovec);
 199   if (ret < 0)
 200     perror_with_name (_("Unable to store general registers."));
 201 }
 202
 203 /* Fill GDB's register array with the fp/simd register values
 204    from the current thread.  */
 205
 206 static void
 207 fetch_fpregs_from_thread (struct regcache *regcache)
 208 {
 209   int ret, tid;
 210   elf_fpregset_t regs;
 211   struct iovec iovec;
 212   struct gdbarch *gdbarch = regcache->arch ();
 213
 214   /* Make sure REGS can hold all VFP registers contents on both aarch64
 215      and arm.  */
 216   gdb_static_assert (sizeof regs >= ARM_VFP3_REGS_SIZE);
 217
 218   tid = regcache->ptid ().lwp ();
 219
 220   iovec.iov_base = &regs;
 221
 222   if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 32)
 223     {
 224       iovec.iov_len = ARM_VFP3_REGS_SIZE;
 225
 226       ret = ptrace (PTRACE_GETREGSET, tid, NT_ARM_VFP, &iovec);
 227       if (ret < 0)
 228         perror_with_name (_("Unable to fetch VFP registers."));
 229
 230       aarch32_vfp_regcache_supply (regcache, (gdb_byte *) &regs, 32);
 231     }
 232   else
 233     {
 234       int regno;
 235
 236       iovec.iov_len = sizeof (regs);
 237
 238       ret = ptrace (PTRACE_GETREGSET, tid, NT_FPREGSET, &iovec);
 239       if (ret < 0)
 240         perror_with_name (_("Unable to fetch vFP/SIMD registers."));
 241
 242       for (regno = AARCH64_V0_REGNUM; regno <= AARCH64_V31_REGNUM; regno++)
 243         regcache->raw_supply (regno, &regs.vregs[regno - AARCH64_V0_REGNUM]);
 244
 245       regcache->raw_supply (AARCH64_FPSR_REGNUM, &regs.fpsr);
 246       regcache->raw_supply (AARCH64_FPCR_REGNUM, &regs.fpcr);
 247     }
 248 }
 249
 250 /* Store to the current thread the valid fp/simd register
 251    values in the GDB's register array.  */
 252
 253 static void
 254 store_fpregs_to_thread (const struct regcache *regcache)
 255 {
 256   int ret, tid;
 257   elf_fpregset_t regs;
 258   struct iovec iovec;
 259   struct gdbarch *gdbarch = regcache->arch ();
 260
 261   /* Make sure REGS can hold all VFP registers contents on both aarch64
 262      and arm.  */
 263   gdb_static_assert (sizeof regs >= ARM_VFP3_REGS_SIZE);
 264   tid = regcache->ptid ().lwp ();
 265
 266   iovec.iov_base = &regs;
 267
 268   if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 32)
 269     {
 270       iovec.iov_len = ARM_VFP3_REGS_SIZE;
 271
 272       ret = ptrace (PTRACE_GETREGSET, tid, NT_ARM_VFP, &iovec);
 273       if (ret < 0)
 274         perror_with_name (_("Unable to fetch VFP registers."));
 275
 276       aarch32_vfp_regcache_collect (regcache, (gdb_byte *) &regs, 32);
 277     }
 278   else
 279     {
 280       int regno;
 281
 282       iovec.iov_len = sizeof (regs);
 283
 284       ret = ptrace (PTRACE_GETREGSET, tid, NT_FPREGSET, &iovec);
 285       if (ret < 0)
 286         perror_with_name (_("Unable to fetch FP/SIMD registers."));
 287
 288       for (regno = AARCH64_V0_REGNUM; regno <= AARCH64_V31_REGNUM; regno++)
 289         if (REG_VALID == regcache->get_register_status (regno))
 290           regcache->raw_collect
 291             (regno, (char *) &regs.vregs[regno - AARCH64_V0_REGNUM]);
 292
 293       if (REG_VALID == regcache->get_register_status (AARCH64_FPSR_REGNUM))
 294         regcache->raw_collect (AARCH64_FPSR_REGNUM, (char *) &regs.fpsr);
 295       if (REG_VALID == regcache->get_register_status (AARCH64_FPCR_REGNUM))
 296         regcache->raw_collect (AARCH64_FPCR_REGNUM, (char *) &regs.fpcr);
 297     }
 298
 299   if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 32)
 300     {
 301       ret = ptrace (PTRACE_SETREGSET, tid, NT_ARM_VFP, &iovec);
 302       if (ret < 0)
 303         perror_with_name (_("Unable to store VFP registers."));
 304     }
 305   else
 306     {
 307       ret = ptrace (PTRACE_SETREGSET, tid, NT_FPREGSET, &iovec);
 308       if (ret < 0)
 309         perror_with_name (_("Unable to store FP/SIMD registers."));
 310     }
 311 }
 312
 313 /* Fill GDB's register array with the sve register values
 314    from the current thread.  */
 315
 316 static void
 317 fetch_sveregs_from_thread (struct regcache *regcache)
 318 {
 319   std::unique_ptr<gdb_byte[]> base
 320     = aarch64_sve_get_sveregs (regcache->ptid ().lwp ());
 321   aarch64_sve_regs_copy_to_reg_buf (regcache, base.get ());
 322 }
 323
 324 /* Store to the current thread the valid sve register
 325    values in the GDB's register array.  */
 326
 327 static void
 328 store_sveregs_to_thread (struct regcache *regcache)
 329 {
 330   int ret;
 331   struct iovec iovec;
 332   int tid = regcache->ptid ().lwp ();
 333
 334   /* First store vector length to the thread.  This is done first to ensure the
 335      ptrace buffers read from the kernel are the correct size.  */
 336   if (!aarch64_sve_set_vq (tid, regcache))
 337     perror_with_name (_("Unable to set VG register."));
 338
 339   /* Obtain a dump of SVE registers from ptrace.  */
 340   std::unique_ptr<gdb_byte[]> base = aarch64_sve_get_sveregs (tid);
 341
 342   /* Overwrite with regcache state.  */
 343   aarch64_sve_regs_copy_from_reg_buf (regcache, base.get ());
 344
 345   /* Write back to the kernel.  */
 346   iovec.iov_base = base.get ();
 347   iovec.iov_len = ((struct user_sve_header *) base.get ())->size;
 348   ret = ptrace (PTRACE_SETREGSET, tid, NT_ARM_SVE, &iovec);
 349
 350   if (ret < 0)
 351     perror_with_name (_("Unable to store sve registers"));
 352 }
 353
 354 /* Fill GDB's register array with the pointer authentication mask values from
 355    the current thread.  */
 356
 357 static void
 358 fetch_pauth_masks_from_thread (struct regcache *regcache)
 359 {
 360   aarch64_gdbarch_tdep *tdep
 361     = (aarch64_gdbarch_tdep *) gdbarch_tdep (regcache->arch ());
 362   int ret;
 363   struct iovec iovec;
 364   uint64_t pauth_regset[2] = {0, 0};
 365   int tid = regcache->ptid ().lwp ();
 366
 367   iovec.iov_base = &pauth_regset;
 368   iovec.iov_len = sizeof (pauth_regset);
 369
 370   ret = ptrace (PTRACE_GETREGSET, tid, NT_ARM_PAC_MASK, &iovec);
 371   if (ret != 0)
 372     perror_with_name (_("unable to fetch pauth registers."));
 373
 374   regcache->raw_supply (AARCH64_PAUTH_DMASK_REGNUM (tdep->pauth_reg_base),
 375                         &pauth_regset[0]);
 376   regcache->raw_supply (AARCH64_PAUTH_CMASK_REGNUM (tdep->pauth_reg_base),
 377                         &pauth_regset[1]);
 378 }
 379
 380 /* Fill GDB's register array with the MTE register values from
 381    the current thread.  */
 382
 383 static void
 384 fetch_mteregs_from_thread (struct regcache *regcache)
 385 {
 386   aarch64_gdbarch_tdep *tdep
 387     = (aarch64_gdbarch_tdep *) gdbarch_tdep (regcache->arch ());
 388   int regno = tdep->mte_reg_base;
 389
 390   gdb_assert (regno != -1);
 391
 392   uint64_t tag_ctl = 0;
 393   struct iovec iovec;
 394
 395   iovec.iov_base = &tag_ctl;
 396   iovec.iov_len = sizeof (tag_ctl);
 397
 398   int tid = get_ptrace_pid (regcache->ptid ());
 399   if (ptrace (PTRACE_GETREGSET, tid, NT_ARM_TAGGED_ADDR_CTRL, &iovec) != 0)
 400       perror_with_name (_("unable to fetch MTE registers."));
 401
 402   regcache->raw_supply (regno, &tag_ctl);
 403 }
 404
 405 /* Store to the current thread the valid MTE register set in the GDB's
 406    register array.  */
 407
 408 static void
 409 store_mteregs_to_thread (struct regcache *regcache)
 410 {
 411   aarch64_gdbarch_tdep *tdep
 412     = (aarch64_gdbarch_tdep *) gdbarch_tdep (regcache->arch ());
 413   int regno = tdep->mte_reg_base;
 414
 415   gdb_assert (regno != -1);
 416
 417   uint64_t tag_ctl = 0;
 418
 419   if (REG_VALID != regcache->get_register_status (regno))
 420     return;
 421
 422   regcache->raw_collect (regno, (char *) &tag_ctl);
 423
 424   struct iovec iovec;
 425
 426   iovec.iov_base = &tag_ctl;
 427   iovec.iov_len = sizeof (tag_ctl);
 428
 429   int tid = get_ptrace_pid (regcache->ptid ());
 430   if (ptrace (PTRACE_SETREGSET, tid, NT_ARM_TAGGED_ADDR_CTRL, &iovec) != 0)
 431     perror_with_name (_("unable to store MTE registers."));
 432 }
 433
 434 /* Fill GDB's register array with the TLS register values from
 435    the current thread.  */
 436
 437 static void
 438 fetch_tlsregs_from_thread (struct regcache *regcache)
 439 {
 440   aarch64_gdbarch_tdep *tdep
 441     = (aarch64_gdbarch_tdep *) gdbarch_tdep (regcache->arch ());
 442   int regno = tdep->tls_regnum;
 443
 444   gdb_assert (regno != -1);
 445
 446   uint64_t tpidr = 0;
 447   struct iovec iovec;
 448
 449   iovec.iov_base = &tpidr;
 450   iovec.iov_len = sizeof (tpidr);
 451
 452   int tid = get_ptrace_pid (regcache->ptid ());
 453   if (ptrace (PTRACE_GETREGSET, tid, NT_ARM_TLS, &iovec) != 0)
 454       perror_with_name (_("unable to fetch TLS register."));
 455
 456   regcache->raw_supply (regno, &tpidr);
 457 }
 458
 459 /* Store to the current thread the valid TLS register set in GDB's
 460    register array.  */
 461
 462 static void
 463 store_tlsregs_to_thread (struct regcache *regcache)
 464 {
 465   aarch64_gdbarch_tdep *tdep
 466     = (aarch64_gdbarch_tdep *) gdbarch_tdep (regcache->arch ());
 467   int regno = tdep->tls_regnum;
 468
 469   gdb_assert (regno != -1);
 470
 471   uint64_t tpidr = 0;
 472
 473   if (REG_VALID != regcache->get_register_status (regno))
 474     return;
 475
 476   regcache->raw_collect (regno, (char *) &tpidr);
 477
 478   struct iovec iovec;
 479
 480   iovec.iov_base = &tpidr;
 481   iovec.iov_len = sizeof (tpidr);
 482
 483   int tid = get_ptrace_pid (regcache->ptid ());
 484   if (ptrace (PTRACE_SETREGSET, tid, NT_ARM_TLS, &iovec) != 0)
 485     perror_with_name (_("unable to store TLS register."));
 486 }
 487
 488 /* Implement the "fetch_registers" target_ops method.  */
 489
 490 void
 491 aarch64_linux_nat_target::fetch_registers (struct regcache *regcache,
 492                                            int regno)
 493 {
 494   aarch64_gdbarch_tdep *tdep
 495     = (aarch64_gdbarch_tdep *) gdbarch_tdep (regcache->arch ());
 496
 497   if (regno == -1)
 498     {
 499       fetch_gregs_from_thread (regcache);
 500       if (tdep->has_sve ())
 501         fetch_sveregs_from_thread (regcache);
 502       else
 503         fetch_fpregs_from_thread (regcache);
 504
 505       if (tdep->has_pauth ())
 506         fetch_pauth_masks_from_thread (regcache);
 507
 508       if (tdep->has_mte ())
 509         fetch_mteregs_from_thread (regcache);
 510
 511       if (tdep->has_tls ())
 512         fetch_tlsregs_from_thread (regcache);
 513     }
 514   else if (regno < AARCH64_V0_REGNUM)
 515     fetch_gregs_from_thread (regcache);
 516   else if (tdep->has_sve ())
 517     fetch_sveregs_from_thread (regcache);
 518   else
 519     fetch_fpregs_from_thread (regcache);
 520
 521   if (tdep->has_pauth ())
 522     {
 523       if (regno == AARCH64_PAUTH_DMASK_REGNUM (tdep->pauth_reg_base)
 524           || regno == AARCH64_PAUTH_CMASK_REGNUM (tdep->pauth_reg_base))
 525         fetch_pauth_masks_from_thread (regcache);
 526     }
 527
 528   /* Fetch individual MTE registers.  */
 529   if (tdep->has_mte ()
 530       && (regno == tdep->mte_reg_base))
 531     fetch_mteregs_from_thread (regcache);
 532
 533   if (tdep->has_tls () && regno == tdep->tls_regnum)
 534     fetch_tlsregs_from_thread (regcache);
 535 }
 536
 537 /* Implement the "store_registers" target_ops method.  */
 538
 539 void
 540 aarch64_linux_nat_target::store_registers (struct regcache *regcache,
 541                                            int regno)
 542 {
 543   aarch64_gdbarch_tdep *tdep
 544     = (aarch64_gdbarch_tdep *) gdbarch_tdep (regcache->arch ());
 545
 546   if (regno == -1)
 547     {
 548       store_gregs_to_thread (regcache);
 549       if (tdep->has_sve ())
 550         store_sveregs_to_thread (regcache);
 551       else
 552         store_fpregs_to_thread (regcache);
 553
 554       if (tdep->has_mte ())
 555         store_mteregs_to_thread (regcache);
 556
 557       if (tdep->has_tls ())
 558         store_tlsregs_to_thread (regcache);
 559     }
 560   else if (regno < AARCH64_V0_REGNUM)
 561     store_gregs_to_thread (regcache);
 562   else if (tdep->has_sve ())
 563     store_sveregs_to_thread (regcache);
 564   else
 565     store_fpregs_to_thread (regcache);
 566
 567   /* Store MTE registers.  */
 568   if (tdep->has_mte ()
 569       && (regno == tdep->mte_reg_base))
 570     store_mteregs_to_thread (regcache);
 571
 572   if (tdep->has_tls () && regno == tdep->tls_regnum)
 573     store_tlsregs_to_thread (regcache);
 574 }
 575
 576 /* Fill register REGNO (if it is a general-purpose register) in
 577    *GREGSETPS with the value in GDB's register array.  If REGNO is -1,
 578    do this for all registers.  */
 579
 580 void
 581 fill_gregset (const struct regcache *regcache,
 582               gdb_gregset_t *gregsetp, int regno)
 583 {
 584   regcache_collect_regset (&aarch64_linux_gregset, regcache,
 585                            regno, (gdb_byte *) gregsetp,
 586                            AARCH64_LINUX_SIZEOF_GREGSET);
 587 }
 588
 589 /* Fill GDB's register array with the general-purpose register values
 590    in *GREGSETP.  */
 591
 592 void
 593 supply_gregset (struct regcache *regcache, const gdb_gregset_t *gregsetp)
 594 {
 595   regcache_supply_regset (&aarch64_linux_gregset, regcache, -1,
 596                           (const gdb_byte *) gregsetp,
 597                           AARCH64_LINUX_SIZEOF_GREGSET);
 598 }
 599
 600 /* Fill register REGNO (if it is a floating-point register) in
 601    *FPREGSETP with the value in GDB's register array.  If REGNO is -1,
 602    do this for all registers.  */
 603
 604 void
 605 fill_fpregset (const struct regcache *regcache,
 606                gdb_fpregset_t *fpregsetp, int regno)
 607 {
 608   regcache_collect_regset (&aarch64_linux_fpregset, regcache,
 609                            regno, (gdb_byte *) fpregsetp,
 610                            AARCH64_LINUX_SIZEOF_FPREGSET);
 611 }
 612
 613 /* Fill GDB's register array with the floating-point register values
 614    in *FPREGSETP.  */
 615
 616 void
 617 supply_fpregset (struct regcache *regcache, const gdb_fpregset_t *fpregsetp)
 618 {
 619   regcache_supply_regset (&aarch64_linux_fpregset, regcache, -1,
 620                           (const gdb_byte *) fpregsetp,
 621                           AARCH64_LINUX_SIZEOF_FPREGSET);
 622 }
 623
 624 /* linux_nat_new_fork hook.   */
 625
 626 void
 627 aarch64_linux_nat_target::low_new_fork (struct lwp_info *parent,
 628                                         pid_t child_pid)
 629 {
 630   pid_t parent_pid;
 631   struct aarch64_debug_reg_state *parent_state;
 632   struct aarch64_debug_reg_state *child_state;
 633
 634   /* NULL means no watchpoint has ever been set in the parent.  In
 635      that case, there's nothing to do.  */
 636   if (parent->arch_private == NULL)
 637     return;
 638
 639   /* GDB core assumes the child inherits the watchpoints/hw
 640      breakpoints of the parent, and will remove them all from the
 641      forked off process.  Copy the debug registers mirrors into the
 642      new process so that all breakpoints and watchpoints can be
 643      removed together.  */
 644
 645   parent_pid = parent->ptid.pid ();
 646   parent_state = aarch64_get_debug_reg_state (parent_pid);
 647   child_state = aarch64_get_debug_reg_state (child_pid);
 648   *child_state = *parent_state;
 649 }
 650 \f
 651
 652 /* Called by libthread_db.  Returns a pointer to the thread local
 653    storage (or its descriptor).  */
 654
 655 ps_err_e
 656 ps_get_thread_area (struct ps_prochandle *ph,
 657                     lwpid_t lwpid, int idx, void **base)
 658 {
 659   int is_64bit_p
 660     = (gdbarch_bfd_arch_info (target_gdbarch ())->bits_per_word == 64);
 661
 662   return aarch64_ps_get_thread_area (ph, lwpid, idx, base, is_64bit_p);
 663 }
 664 \f
 665
 666 /* Implement the virtual inf_ptrace_target::post_startup_inferior method.  */
 667
 668 void
 669 aarch64_linux_nat_target::post_startup_inferior (ptid_t ptid)
 670 {
 671   low_forget_process (ptid.pid ());
 672   aarch64_linux_get_debug_reg_capacity (ptid.pid ());
 673   linux_nat_target::post_startup_inferior (ptid);
 674 }
 675
 676 /* Implement the "post_attach" target_ops method.  */
 677
 678 void
 679 aarch64_linux_nat_target::post_attach (int pid)
 680 {
 681   low_forget_process (pid);
 682   /* Set the hardware debug register capacity.  If
 683      aarch64_linux_get_debug_reg_capacity is not called
 684      (as it is in aarch64_linux_child_post_startup_inferior) then
 685      software watchpoints will be used instead of hardware
 686      watchpoints when attaching to a target.  */
 687   aarch64_linux_get_debug_reg_capacity (pid);
 688   linux_nat_target::post_attach (pid);
 689 }
 690
 691 /* Implement the "read_description" target_ops method.  */
 692
 693 const struct target_desc *
 694 aarch64_linux_nat_target::read_description ()
 695 {
 696   int ret, tid;
 697   gdb_byte regbuf[ARM_VFP3_REGS_SIZE];
 698   struct iovec iovec;
 699
 700   tid = inferior_ptid.pid ();
 701
 702   iovec.iov_base = regbuf;
 703   iovec.iov_len = ARM_VFP3_REGS_SIZE;
 704
 705   ret = ptrace (PTRACE_GETREGSET, tid, NT_ARM_VFP, &iovec);
 706   if (ret == 0)
 707     return aarch32_read_description ();
 708
 709   CORE_ADDR hwcap = linux_get_hwcap (this);
 710   CORE_ADDR hwcap2 = linux_get_hwcap2 (this);
 711
 712   aarch64_features features;
 713   features.vq = aarch64_sve_get_vq (tid);
 714   features.pauth = hwcap & AARCH64_HWCAP_PACA;
 715   features.mte = hwcap2 & HWCAP2_MTE;
 716   features.tls = true;
 717
 718   return aarch64_read_description (features);
 719 }
 720
 721 /* Convert a native/host siginfo object, into/from the siginfo in the
 722    layout of the inferiors' architecture.  Returns true if any
 723    conversion was done; false otherwise.  If DIRECTION is 1, then copy
 724    from INF to NATIVE.  If DIRECTION is 0, copy from NATIVE to
 725    INF.  */
 726
 727 bool
 728 aarch64_linux_nat_target::low_siginfo_fixup (siginfo_t *native, gdb_byte *inf,
 729                                              int direction)
 730 {
 731   struct gdbarch *gdbarch = get_frame_arch (get_current_frame ());
 732
 733   /* Is the inferior 32-bit?  If so, then do fixup the siginfo
 734      object.  */
 735   if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 32)
 736     {
 737       if (direction == 0)
 738         aarch64_compat_siginfo_from_siginfo ((struct compat_siginfo *) inf,
 739                                              native);
 740       else
 741         aarch64_siginfo_from_compat_siginfo (native,
 742                                              (struct compat_siginfo *) inf);
 743
 744       return true;
 745     }
 746
 747   return false;
 748 }
 749
 750 /* Implement the "stopped_data_address" target_ops method.  */
 751
 752 bool
 753 aarch64_linux_nat_target::stopped_data_address (CORE_ADDR *addr_p)
 754 {
 755   siginfo_t siginfo;
 756   struct aarch64_debug_reg_state *state;
 757
 758   if (!linux_nat_get_siginfo (inferior_ptid, &siginfo))
 759     return false;
 760
 761   /* This must be a hardware breakpoint.  */
 762   if (siginfo.si_signo != SIGTRAP
 763       || (siginfo.si_code & 0xffff) != TRAP_HWBKPT)
 764     return false;
 765
 766   /* Make sure to ignore the top byte, otherwise we may not recognize a
 767      hardware watchpoint hit.  The stopped data addresses coming from the
 768      kernel can potentially be tagged addresses.  */
 769   struct gdbarch *gdbarch = thread_architecture (inferior_ptid);
 770   const CORE_ADDR addr_trap
 771     = address_significant (gdbarch, (CORE_ADDR) siginfo.si_addr);
 772
 773   /* Check if the address matches any watched address.  */
 774   state = aarch64_get_debug_reg_state (inferior_ptid.pid ());
 775   return aarch64_stopped_data_address (state, addr_trap, addr_p);
 776 }
 777
 778 /* Implement the "stopped_by_watchpoint" target_ops method.  */
 779
 780 bool
 781 aarch64_linux_nat_target::stopped_by_watchpoint ()
 782 {
 783   CORE_ADDR addr;
 784
 785   return stopped_data_address (&addr);
 786 }
 787
 788 /* Implement the "can_do_single_step" target_ops method.  */
 789
 790 int
 791 aarch64_linux_nat_target::can_do_single_step ()
 792 {
 793   return 1;
 794 }
 795
 796 /* Implement the "thread_architecture" target_ops method.  */
 797
 798 struct gdbarch *
 799 aarch64_linux_nat_target::thread_architecture (ptid_t ptid)
 800 {
 801   /* Return the gdbarch for the current thread.  If the vector length has
 802      changed since the last time this was called, then do a further lookup.  */
 803
 804   uint64_t vq = aarch64_sve_get_vq (ptid.lwp ());
 805
 806   /* Find the current gdbarch the same way as process_stratum_target.  Only
 807      return it if the current vector length matches the one in the tdep.  */
 808   inferior *inf = find_inferior_ptid (this, ptid);
 809   gdb_assert (inf != NULL);
 810   aarch64_gdbarch_tdep *tdep
 811     = (aarch64_gdbarch_tdep *) gdbarch_tdep (inf->gdbarch);
 812   if (vq == tdep->vq)
 813     return inf->gdbarch;
 814
 815   /* We reach here if the vector length for the thread is different from its
 816      value at process start.  Lookup gdbarch via info (potentially creating a
 817      new one), stashing the vector length inside id.  Use -1 for when SVE
 818      unavailable, to distinguish from an unset value of 0.  */
 819   struct gdbarch_info info;
 820   info.bfd_arch_info = bfd_lookup_arch (bfd_arch_aarch64, bfd_mach_aarch64);
 821   info.id = (int *) (vq == 0 ? -1 : vq);
 822   return gdbarch_find_by_info (info);
 823 }
 824
 825 /* Implement the "supports_memory_tagging" target_ops method.  */
 826
 827 bool
 828 aarch64_linux_nat_target::supports_memory_tagging ()
 829 {
 830   return (linux_get_hwcap2 (this) & HWCAP2_MTE) != 0;
 831 }
 832
 833 /* Implement the "fetch_memtags" target_ops method.  */
 834
 835 bool
 836 aarch64_linux_nat_target::fetch_memtags (CORE_ADDR address, size_t len,
 837                                          gdb::byte_vector &tags, int type)
 838 {
 839   int tid = get_ptrace_pid (inferior_ptid);
 840
 841   /* Allocation tags?  */
 842   if (type == static_cast<int> (aarch64_memtag_type::mte_allocation))
 843     return aarch64_mte_fetch_memtags (tid, address, len, tags);
 844
 845   return false;
 846 }
 847
 848 /* Implement the "store_memtags" target_ops method.  */
 849
 850 bool
 851 aarch64_linux_nat_target::store_memtags (CORE_ADDR address, size_t len,
 852                                          const gdb::byte_vector &tags, int type)
 853 {
 854   int tid = get_ptrace_pid (inferior_ptid);
 855
 856   /* Allocation tags?  */
 857   if (type == static_cast<int> (aarch64_memtag_type::mte_allocation))
 858     return aarch64_mte_store_memtags (tid, address, len, tags);
 859
 860   return false;
 861 }
 862
 863 void _initialize_aarch64_linux_nat ();
 864 void
 865 _initialize_aarch64_linux_nat ()
 866 {
 867   aarch64_initialize_hw_point ();
 868
 869   /* Register the target.  */
 870   linux_target = &the_aarch64_linux_nat_target;
 871   add_inf_child_target (&the_aarch64_linux_nat_target);
 872 }