1 /* Common target dependent code for GDB on AArch64 systems.
3 Copyright (C) 2009-2021 Free Software Foundation, Inc.
4 Contributed by ARM Ltd.
6 This file is part of GDB.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
28 #include "reggroups.h"
30 #include "arch-utils.h"
32 #include "frame-unwind.h"
33 #include "frame-base.h"
34 #include "trad-frame.h"
37 #include "dwarf2/frame.h"
39 #include "prologue-value.h"
40 #include "target-descriptions.h"
41 #include "user-regs.h"
43 #include "gdbsupport/selftest.h"
45 #include "aarch64-tdep.h"
46 #include "aarch64-ravenscar-thread.h"
49 #include "record-full.h"
50 #include "arch/aarch64-insn.h"
53 #include "opcode/aarch64.h"
56 /* A Homogeneous Floating-Point or Short-Vector Aggregate may have at most
58 #define HA_MAX_NUM_FLDS 4
60 /* All possible aarch64 target descriptors. */
61 static target_desc
*tdesc_aarch64_list
[AARCH64_MAX_SVE_VQ
+ 1][2/*pauth*/][2 /* mte */];
63 /* The standard register names, and all the valid aliases for them. */
66 const char *const name
;
68 } aarch64_register_aliases
[] =
70 /* 64-bit register names. */
71 {"fp", AARCH64_FP_REGNUM
},
72 {"lr", AARCH64_LR_REGNUM
},
73 {"sp", AARCH64_SP_REGNUM
},
75 /* 32-bit register names. */
76 {"w0", AARCH64_X0_REGNUM
+ 0},
77 {"w1", AARCH64_X0_REGNUM
+ 1},
78 {"w2", AARCH64_X0_REGNUM
+ 2},
79 {"w3", AARCH64_X0_REGNUM
+ 3},
80 {"w4", AARCH64_X0_REGNUM
+ 4},
81 {"w5", AARCH64_X0_REGNUM
+ 5},
82 {"w6", AARCH64_X0_REGNUM
+ 6},
83 {"w7", AARCH64_X0_REGNUM
+ 7},
84 {"w8", AARCH64_X0_REGNUM
+ 8},
85 {"w9", AARCH64_X0_REGNUM
+ 9},
86 {"w10", AARCH64_X0_REGNUM
+ 10},
87 {"w11", AARCH64_X0_REGNUM
+ 11},
88 {"w12", AARCH64_X0_REGNUM
+ 12},
89 {"w13", AARCH64_X0_REGNUM
+ 13},
90 {"w14", AARCH64_X0_REGNUM
+ 14},
91 {"w15", AARCH64_X0_REGNUM
+ 15},
92 {"w16", AARCH64_X0_REGNUM
+ 16},
93 {"w17", AARCH64_X0_REGNUM
+ 17},
94 {"w18", AARCH64_X0_REGNUM
+ 18},
95 {"w19", AARCH64_X0_REGNUM
+ 19},
96 {"w20", AARCH64_X0_REGNUM
+ 20},
97 {"w21", AARCH64_X0_REGNUM
+ 21},
98 {"w22", AARCH64_X0_REGNUM
+ 22},
99 {"w23", AARCH64_X0_REGNUM
+ 23},
100 {"w24", AARCH64_X0_REGNUM
+ 24},
101 {"w25", AARCH64_X0_REGNUM
+ 25},
102 {"w26", AARCH64_X0_REGNUM
+ 26},
103 {"w27", AARCH64_X0_REGNUM
+ 27},
104 {"w28", AARCH64_X0_REGNUM
+ 28},
105 {"w29", AARCH64_X0_REGNUM
+ 29},
106 {"w30", AARCH64_X0_REGNUM
+ 30},
109 {"ip0", AARCH64_X0_REGNUM
+ 16},
110 {"ip1", AARCH64_X0_REGNUM
+ 17}
113 /* The required core 'R' registers. */
114 static const char *const aarch64_r_register_names
[] =
116 /* These registers must appear in consecutive RAW register number
117 order and they must begin with AARCH64_X0_REGNUM! */
118 "x0", "x1", "x2", "x3",
119 "x4", "x5", "x6", "x7",
120 "x8", "x9", "x10", "x11",
121 "x12", "x13", "x14", "x15",
122 "x16", "x17", "x18", "x19",
123 "x20", "x21", "x22", "x23",
124 "x24", "x25", "x26", "x27",
125 "x28", "x29", "x30", "sp",
129 /* The FP/SIMD 'V' registers. */
130 static const char *const aarch64_v_register_names
[] =
132 /* These registers must appear in consecutive RAW register number
133 order and they must begin with AARCH64_V0_REGNUM! */
134 "v0", "v1", "v2", "v3",
135 "v4", "v5", "v6", "v7",
136 "v8", "v9", "v10", "v11",
137 "v12", "v13", "v14", "v15",
138 "v16", "v17", "v18", "v19",
139 "v20", "v21", "v22", "v23",
140 "v24", "v25", "v26", "v27",
141 "v28", "v29", "v30", "v31",
146 /* The SVE 'Z' and 'P' registers. */
147 static const char *const aarch64_sve_register_names
[] =
149 /* These registers must appear in consecutive RAW register number
150 order and they must begin with AARCH64_SVE_Z0_REGNUM! */
151 "z0", "z1", "z2", "z3",
152 "z4", "z5", "z6", "z7",
153 "z8", "z9", "z10", "z11",
154 "z12", "z13", "z14", "z15",
155 "z16", "z17", "z18", "z19",
156 "z20", "z21", "z22", "z23",
157 "z24", "z25", "z26", "z27",
158 "z28", "z29", "z30", "z31",
160 "p0", "p1", "p2", "p3",
161 "p4", "p5", "p6", "p7",
162 "p8", "p9", "p10", "p11",
163 "p12", "p13", "p14", "p15",
167 static const char *const aarch64_pauth_register_names
[] =
169 /* Authentication mask for data pointer. */
171 /* Authentication mask for code pointer. */
175 static const char *const aarch64_mte_register_names
[] =
177 /* Tag Control Register. */
181 /* AArch64 prologue cache structure. */
182 struct aarch64_prologue_cache
184 /* The program counter at the start of the function. It is used to
185 identify this frame as a prologue frame. */
188 /* The program counter at the time this frame was created; i.e. where
189 this function was called from. It is used to identify this frame as a
193 /* The stack pointer at the time this frame was created; i.e. the
194 caller's stack pointer when this function was called. It is used
195 to identify this frame. */
198 /* Is the target available to read from? */
201 /* The frame base for this frame is just prev_sp - frame size.
202 FRAMESIZE is the distance from the frame pointer to the
203 initial stack pointer. */
206 /* The register used to hold the frame pointer for this frame. */
209 /* Saved register offsets. */
210 trad_frame_saved_reg
*saved_regs
;
214 show_aarch64_debug (struct ui_file
*file
, int from_tty
,
215 struct cmd_list_element
*c
, const char *value
)
217 fprintf_filtered (file
, _("AArch64 debugging is %s.\n"), value
);
222 /* Abstract instruction reader. */
224 class abstract_instruction_reader
227 /* Read in one instruction. */
228 virtual ULONGEST
read (CORE_ADDR memaddr
, int len
,
229 enum bfd_endian byte_order
) = 0;
232 /* Instruction reader from real target. */
234 class instruction_reader
: public abstract_instruction_reader
237 ULONGEST
read (CORE_ADDR memaddr
, int len
, enum bfd_endian byte_order
)
240 return read_code_unsigned_integer (memaddr
, len
, byte_order
);
246 /* If address signing is enabled, mask off the signature bits from the link
247 register, which is passed by value in ADDR, using the register values in
251 aarch64_frame_unmask_lr (aarch64_gdbarch_tdep
*tdep
,
252 struct frame_info
*this_frame
, CORE_ADDR addr
)
254 if (tdep
->has_pauth ()
255 && frame_unwind_register_unsigned (this_frame
,
256 tdep
->pauth_ra_state_regnum
))
258 int cmask_num
= AARCH64_PAUTH_CMASK_REGNUM (tdep
->pauth_reg_base
);
259 CORE_ADDR cmask
= frame_unwind_register_unsigned (this_frame
, cmask_num
);
260 addr
= addr
& ~cmask
;
262 /* Record in the frame that the link register required unmasking. */
263 set_frame_previous_pc_masked (this_frame
);
269 /* Implement the "get_pc_address_flags" gdbarch method. */
272 aarch64_get_pc_address_flags (frame_info
*frame
, CORE_ADDR pc
)
274 if (pc
!= 0 && get_frame_pc_masked (frame
))
280 /* Analyze a prologue, looking for a recognizable stack frame
281 and frame pointer. Scan until we encounter a store that could
282 clobber the stack frame unexpectedly, or an unknown instruction. */
285 aarch64_analyze_prologue (struct gdbarch
*gdbarch
,
286 CORE_ADDR start
, CORE_ADDR limit
,
287 struct aarch64_prologue_cache
*cache
,
288 abstract_instruction_reader
& reader
)
290 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
293 /* Whether the stack has been set. This should be true when we notice a SP
294 to FP move or if we are using the SP as the base register for storing
295 data, in case the FP is ommitted. */
296 bool seen_stack_set
= false;
298 /* Track X registers and D registers in prologue. */
299 pv_t regs
[AARCH64_X_REGISTER_COUNT
+ AARCH64_D_REGISTER_COUNT
];
301 for (i
= 0; i
< AARCH64_X_REGISTER_COUNT
+ AARCH64_D_REGISTER_COUNT
; i
++)
302 regs
[i
] = pv_register (i
, 0);
303 pv_area
stack (AARCH64_SP_REGNUM
, gdbarch_addr_bit (gdbarch
));
305 for (; start
< limit
; start
+= 4)
310 insn
= reader
.read (start
, 4, byte_order_for_code
);
312 if (aarch64_decode_insn (insn
, &inst
, 1, NULL
) != 0)
315 if (inst
.opcode
->iclass
== addsub_imm
316 && (inst
.opcode
->op
== OP_ADD
317 || strcmp ("sub", inst
.opcode
->name
) == 0))
319 unsigned rd
= inst
.operands
[0].reg
.regno
;
320 unsigned rn
= inst
.operands
[1].reg
.regno
;
322 gdb_assert (aarch64_num_of_operands (inst
.opcode
) == 3);
323 gdb_assert (inst
.operands
[0].type
== AARCH64_OPND_Rd_SP
);
324 gdb_assert (inst
.operands
[1].type
== AARCH64_OPND_Rn_SP
);
325 gdb_assert (inst
.operands
[2].type
== AARCH64_OPND_AIMM
);
327 if (inst
.opcode
->op
== OP_ADD
)
329 regs
[rd
] = pv_add_constant (regs
[rn
],
330 inst
.operands
[2].imm
.value
);
334 regs
[rd
] = pv_add_constant (regs
[rn
],
335 -inst
.operands
[2].imm
.value
);
338 /* Did we move SP to FP? */
339 if (rn
== AARCH64_SP_REGNUM
&& rd
== AARCH64_FP_REGNUM
)
340 seen_stack_set
= true;
342 else if (inst
.opcode
->iclass
== pcreladdr
343 && inst
.operands
[1].type
== AARCH64_OPND_ADDR_ADRP
)
345 gdb_assert (aarch64_num_of_operands (inst
.opcode
) == 2);
346 gdb_assert (inst
.operands
[0].type
== AARCH64_OPND_Rd
);
348 regs
[inst
.operands
[0].reg
.regno
] = pv_unknown ();
350 else if (inst
.opcode
->iclass
== branch_imm
)
352 /* Stop analysis on branch. */
355 else if (inst
.opcode
->iclass
== condbranch
)
357 /* Stop analysis on branch. */
360 else if (inst
.opcode
->iclass
== branch_reg
)
362 /* Stop analysis on branch. */
365 else if (inst
.opcode
->iclass
== compbranch
)
367 /* Stop analysis on branch. */
370 else if (inst
.opcode
->op
== OP_MOVZ
)
372 gdb_assert (inst
.operands
[0].type
== AARCH64_OPND_Rd
);
374 /* If this shows up before we set the stack, keep going. Otherwise
375 stop the analysis. */
379 regs
[inst
.operands
[0].reg
.regno
] = pv_unknown ();
381 else if (inst
.opcode
->iclass
== log_shift
382 && strcmp (inst
.opcode
->name
, "orr") == 0)
384 unsigned rd
= inst
.operands
[0].reg
.regno
;
385 unsigned rn
= inst
.operands
[1].reg
.regno
;
386 unsigned rm
= inst
.operands
[2].reg
.regno
;
388 gdb_assert (inst
.operands
[0].type
== AARCH64_OPND_Rd
);
389 gdb_assert (inst
.operands
[1].type
== AARCH64_OPND_Rn
);
390 gdb_assert (inst
.operands
[2].type
== AARCH64_OPND_Rm_SFT
);
392 if (inst
.operands
[2].shifter
.amount
== 0
393 && rn
== AARCH64_SP_REGNUM
)
397 aarch64_debug_printf ("prologue analysis gave up "
398 "addr=%s opcode=0x%x (orr x register)",
399 core_addr_to_string_nz (start
), insn
);
404 else if (inst
.opcode
->op
== OP_STUR
)
406 unsigned rt
= inst
.operands
[0].reg
.regno
;
407 unsigned rn
= inst
.operands
[1].addr
.base_regno
;
408 int size
= aarch64_get_qualifier_esize (inst
.operands
[0].qualifier
);
410 gdb_assert (aarch64_num_of_operands (inst
.opcode
) == 2);
411 gdb_assert (inst
.operands
[0].type
== AARCH64_OPND_Rt
);
412 gdb_assert (inst
.operands
[1].type
== AARCH64_OPND_ADDR_SIMM9
);
413 gdb_assert (!inst
.operands
[1].addr
.offset
.is_reg
);
416 (pv_add_constant (regs
[rn
], inst
.operands
[1].addr
.offset
.imm
),
419 /* Are we storing with SP as a base? */
420 if (rn
== AARCH64_SP_REGNUM
)
421 seen_stack_set
= true;
423 else if ((inst
.opcode
->iclass
== ldstpair_off
424 || (inst
.opcode
->iclass
== ldstpair_indexed
425 && inst
.operands
[2].addr
.preind
))
426 && strcmp ("stp", inst
.opcode
->name
) == 0)
428 /* STP with addressing mode Pre-indexed and Base register. */
431 unsigned rn
= inst
.operands
[2].addr
.base_regno
;
432 int32_t imm
= inst
.operands
[2].addr
.offset
.imm
;
433 int size
= aarch64_get_qualifier_esize (inst
.operands
[0].qualifier
);
435 gdb_assert (inst
.operands
[0].type
== AARCH64_OPND_Rt
436 || inst
.operands
[0].type
== AARCH64_OPND_Ft
);
437 gdb_assert (inst
.operands
[1].type
== AARCH64_OPND_Rt2
438 || inst
.operands
[1].type
== AARCH64_OPND_Ft2
);
439 gdb_assert (inst
.operands
[2].type
== AARCH64_OPND_ADDR_SIMM7
);
440 gdb_assert (!inst
.operands
[2].addr
.offset
.is_reg
);
442 /* If recording this store would invalidate the store area
443 (perhaps because rn is not known) then we should abandon
444 further prologue analysis. */
445 if (stack
.store_would_trash (pv_add_constant (regs
[rn
], imm
)))
448 if (stack
.store_would_trash (pv_add_constant (regs
[rn
], imm
+ 8)))
451 rt1
= inst
.operands
[0].reg
.regno
;
452 rt2
= inst
.operands
[1].reg
.regno
;
453 if (inst
.operands
[0].type
== AARCH64_OPND_Ft
)
455 rt1
+= AARCH64_X_REGISTER_COUNT
;
456 rt2
+= AARCH64_X_REGISTER_COUNT
;
459 stack
.store (pv_add_constant (regs
[rn
], imm
), size
, regs
[rt1
]);
460 stack
.store (pv_add_constant (regs
[rn
], imm
+ size
), size
, regs
[rt2
]);
462 if (inst
.operands
[2].addr
.writeback
)
463 regs
[rn
] = pv_add_constant (regs
[rn
], imm
);
465 /* Ignore the instruction that allocates stack space and sets
467 if (rn
== AARCH64_SP_REGNUM
&& !inst
.operands
[2].addr
.writeback
)
468 seen_stack_set
= true;
470 else if ((inst
.opcode
->iclass
== ldst_imm9
/* Signed immediate. */
471 || (inst
.opcode
->iclass
== ldst_pos
/* Unsigned immediate. */
472 && (inst
.opcode
->op
== OP_STR_POS
473 || inst
.opcode
->op
== OP_STRF_POS
)))
474 && inst
.operands
[1].addr
.base_regno
== AARCH64_SP_REGNUM
475 && strcmp ("str", inst
.opcode
->name
) == 0)
477 /* STR (immediate) */
478 unsigned int rt
= inst
.operands
[0].reg
.regno
;
479 int32_t imm
= inst
.operands
[1].addr
.offset
.imm
;
480 unsigned int rn
= inst
.operands
[1].addr
.base_regno
;
481 int size
= aarch64_get_qualifier_esize (inst
.operands
[0].qualifier
);
482 gdb_assert (inst
.operands
[0].type
== AARCH64_OPND_Rt
483 || inst
.operands
[0].type
== AARCH64_OPND_Ft
);
485 if (inst
.operands
[0].type
== AARCH64_OPND_Ft
)
486 rt
+= AARCH64_X_REGISTER_COUNT
;
488 stack
.store (pv_add_constant (regs
[rn
], imm
), size
, regs
[rt
]);
489 if (inst
.operands
[1].addr
.writeback
)
490 regs
[rn
] = pv_add_constant (regs
[rn
], imm
);
492 /* Are we storing with SP as a base? */
493 if (rn
== AARCH64_SP_REGNUM
)
494 seen_stack_set
= true;
496 else if (inst
.opcode
->iclass
== testbranch
)
498 /* Stop analysis on branch. */
501 else if (inst
.opcode
->iclass
== ic_system
)
503 aarch64_gdbarch_tdep
*tdep
504 = (aarch64_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
505 int ra_state_val
= 0;
507 if (insn
== 0xd503233f /* paciasp. */
508 || insn
== 0xd503237f /* pacibsp. */)
510 /* Return addresses are mangled. */
513 else if (insn
== 0xd50323bf /* autiasp. */
514 || insn
== 0xd50323ff /* autibsp. */)
516 /* Return addresses are not mangled. */
521 aarch64_debug_printf ("prologue analysis gave up addr=%s"
522 " opcode=0x%x (iclass)",
523 core_addr_to_string_nz (start
), insn
);
527 if (tdep
->has_pauth () && cache
!= nullptr)
529 int regnum
= tdep
->pauth_ra_state_regnum
;
530 cache
->saved_regs
[regnum
].set_value (ra_state_val
);
535 aarch64_debug_printf ("prologue analysis gave up addr=%s"
537 core_addr_to_string_nz (start
), insn
);
546 if (pv_is_register (regs
[AARCH64_FP_REGNUM
], AARCH64_SP_REGNUM
))
548 /* Frame pointer is fp. Frame size is constant. */
549 cache
->framereg
= AARCH64_FP_REGNUM
;
550 cache
->framesize
= -regs
[AARCH64_FP_REGNUM
].k
;
552 else if (pv_is_register (regs
[AARCH64_SP_REGNUM
], AARCH64_SP_REGNUM
))
554 /* Try the stack pointer. */
555 cache
->framesize
= -regs
[AARCH64_SP_REGNUM
].k
;
556 cache
->framereg
= AARCH64_SP_REGNUM
;
560 /* We're just out of luck. We don't know where the frame is. */
561 cache
->framereg
= -1;
562 cache
->framesize
= 0;
565 for (i
= 0; i
< AARCH64_X_REGISTER_COUNT
; i
++)
569 if (stack
.find_reg (gdbarch
, i
, &offset
))
570 cache
->saved_regs
[i
].set_addr (offset
);
573 for (i
= 0; i
< AARCH64_D_REGISTER_COUNT
; i
++)
575 int regnum
= gdbarch_num_regs (gdbarch
);
578 if (stack
.find_reg (gdbarch
, i
+ AARCH64_X_REGISTER_COUNT
,
580 cache
->saved_regs
[i
+ regnum
+ AARCH64_D0_REGNUM
].set_addr (offset
);
587 aarch64_analyze_prologue (struct gdbarch
*gdbarch
,
588 CORE_ADDR start
, CORE_ADDR limit
,
589 struct aarch64_prologue_cache
*cache
)
591 instruction_reader reader
;
593 return aarch64_analyze_prologue (gdbarch
, start
, limit
, cache
,
599 namespace selftests
{
601 /* Instruction reader from manually cooked instruction sequences. */
603 class instruction_reader_test
: public abstract_instruction_reader
606 template<size_t SIZE
>
607 explicit instruction_reader_test (const uint32_t (&insns
)[SIZE
])
608 : m_insns (insns
), m_insns_size (SIZE
)
611 ULONGEST
read (CORE_ADDR memaddr
, int len
, enum bfd_endian byte_order
)
614 SELF_CHECK (len
== 4);
615 SELF_CHECK (memaddr
% 4 == 0);
616 SELF_CHECK (memaddr
/ 4 < m_insns_size
);
618 return m_insns
[memaddr
/ 4];
622 const uint32_t *m_insns
;
627 aarch64_analyze_prologue_test (void)
629 struct gdbarch_info info
;
631 info
.bfd_arch_info
= bfd_scan_arch ("aarch64");
633 struct gdbarch
*gdbarch
= gdbarch_find_by_info (info
);
634 SELF_CHECK (gdbarch
!= NULL
);
636 struct aarch64_prologue_cache cache
;
637 cache
.saved_regs
= trad_frame_alloc_saved_regs (gdbarch
);
639 aarch64_gdbarch_tdep
*tdep
= (aarch64_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
641 /* Test the simple prologue in which frame pointer is used. */
643 static const uint32_t insns
[] = {
644 0xa9af7bfd, /* stp x29, x30, [sp,#-272]! */
645 0x910003fd, /* mov x29, sp */
646 0x97ffffe6, /* bl 0x400580 */
648 instruction_reader_test
reader (insns
);
650 CORE_ADDR end
= aarch64_analyze_prologue (gdbarch
, 0, 128, &cache
, reader
);
651 SELF_CHECK (end
== 4 * 2);
653 SELF_CHECK (cache
.framereg
== AARCH64_FP_REGNUM
);
654 SELF_CHECK (cache
.framesize
== 272);
656 for (int i
= 0; i
< AARCH64_X_REGISTER_COUNT
; i
++)
658 if (i
== AARCH64_FP_REGNUM
)
659 SELF_CHECK (cache
.saved_regs
[i
].addr () == -272);
660 else if (i
== AARCH64_LR_REGNUM
)
661 SELF_CHECK (cache
.saved_regs
[i
].addr () == -264);
663 SELF_CHECK (cache
.saved_regs
[i
].is_realreg ()
664 && cache
.saved_regs
[i
].realreg () == i
);
667 for (int i
= 0; i
< AARCH64_D_REGISTER_COUNT
; i
++)
669 int num_regs
= gdbarch_num_regs (gdbarch
);
670 int regnum
= i
+ num_regs
+ AARCH64_D0_REGNUM
;
672 SELF_CHECK (cache
.saved_regs
[regnum
].is_realreg ()
673 && cache
.saved_regs
[regnum
].realreg () == regnum
);
677 /* Test a prologue in which STR is used and frame pointer is not
680 static const uint32_t insns
[] = {
681 0xf81d0ff3, /* str x19, [sp, #-48]! */
682 0xb9002fe0, /* str w0, [sp, #44] */
683 0xf90013e1, /* str x1, [sp, #32]*/
684 0xfd000fe0, /* str d0, [sp, #24] */
685 0xaa0203f3, /* mov x19, x2 */
686 0xf94013e0, /* ldr x0, [sp, #32] */
688 instruction_reader_test
reader (insns
);
690 trad_frame_reset_saved_regs (gdbarch
, cache
.saved_regs
);
691 CORE_ADDR end
= aarch64_analyze_prologue (gdbarch
, 0, 128, &cache
, reader
);
693 SELF_CHECK (end
== 4 * 5);
695 SELF_CHECK (cache
.framereg
== AARCH64_SP_REGNUM
);
696 SELF_CHECK (cache
.framesize
== 48);
698 for (int i
= 0; i
< AARCH64_X_REGISTER_COUNT
; i
++)
701 SELF_CHECK (cache
.saved_regs
[i
].addr () == -16);
703 SELF_CHECK (cache
.saved_regs
[i
].addr () == -48);
705 SELF_CHECK (cache
.saved_regs
[i
].is_realreg ()
706 && cache
.saved_regs
[i
].realreg () == i
);
709 for (int i
= 0; i
< AARCH64_D_REGISTER_COUNT
; i
++)
711 int num_regs
= gdbarch_num_regs (gdbarch
);
712 int regnum
= i
+ num_regs
+ AARCH64_D0_REGNUM
;
716 SELF_CHECK (cache
.saved_regs
[regnum
].addr () == -24);
718 SELF_CHECK (cache
.saved_regs
[regnum
].is_realreg ()
719 && cache
.saved_regs
[regnum
].realreg () == regnum
);
723 /* Test handling of movz before setting the frame pointer. */
725 static const uint32_t insns
[] = {
726 0xa9bf7bfd, /* stp x29, x30, [sp, #-16]! */
727 0x52800020, /* mov w0, #0x1 */
728 0x910003fd, /* mov x29, sp */
729 0x528000a2, /* mov w2, #0x5 */
730 0x97fffff8, /* bl 6e4 */
733 instruction_reader_test
reader (insns
);
735 trad_frame_reset_saved_regs (gdbarch
, cache
.saved_regs
);
736 CORE_ADDR end
= aarch64_analyze_prologue (gdbarch
, 0, 128, &cache
, reader
);
738 /* We should stop at the 4th instruction. */
739 SELF_CHECK (end
== (4 - 1) * 4);
740 SELF_CHECK (cache
.framereg
== AARCH64_FP_REGNUM
);
741 SELF_CHECK (cache
.framesize
== 16);
744 /* Test handling of movz/stp when using the stack pointer as frame
747 static const uint32_t insns
[] = {
748 0xa9bc7bfd, /* stp x29, x30, [sp, #-64]! */
749 0x52800020, /* mov w0, #0x1 */
750 0x290207e0, /* stp w0, w1, [sp, #16] */
751 0xa9018fe2, /* stp x2, x3, [sp, #24] */
752 0x528000a2, /* mov w2, #0x5 */
753 0x97fffff8, /* bl 6e4 */
756 instruction_reader_test
reader (insns
);
758 trad_frame_reset_saved_regs (gdbarch
, cache
.saved_regs
);
759 CORE_ADDR end
= aarch64_analyze_prologue (gdbarch
, 0, 128, &cache
, reader
);
761 /* We should stop at the 5th instruction. */
762 SELF_CHECK (end
== (5 - 1) * 4);
763 SELF_CHECK (cache
.framereg
== AARCH64_SP_REGNUM
);
764 SELF_CHECK (cache
.framesize
== 64);
767 /* Test handling of movz/str when using the stack pointer as frame
770 static const uint32_t insns
[] = {
771 0xa9bc7bfd, /* stp x29, x30, [sp, #-64]! */
772 0x52800020, /* mov w0, #0x1 */
773 0xb9002be4, /* str w4, [sp, #40] */
774 0xf9001be5, /* str x5, [sp, #48] */
775 0x528000a2, /* mov w2, #0x5 */
776 0x97fffff8, /* bl 6e4 */
779 instruction_reader_test
reader (insns
);
781 trad_frame_reset_saved_regs (gdbarch
, cache
.saved_regs
);
782 CORE_ADDR end
= aarch64_analyze_prologue (gdbarch
, 0, 128, &cache
, reader
);
784 /* We should stop at the 5th instruction. */
785 SELF_CHECK (end
== (5 - 1) * 4);
786 SELF_CHECK (cache
.framereg
== AARCH64_SP_REGNUM
);
787 SELF_CHECK (cache
.framesize
== 64);
790 /* Test handling of movz/stur when using the stack pointer as frame
793 static const uint32_t insns
[] = {
794 0xa9bc7bfd, /* stp x29, x30, [sp, #-64]! */
795 0x52800020, /* mov w0, #0x1 */
796 0xb80343e6, /* stur w6, [sp, #52] */
797 0xf80383e7, /* stur x7, [sp, #56] */
798 0x528000a2, /* mov w2, #0x5 */
799 0x97fffff8, /* bl 6e4 */
802 instruction_reader_test
reader (insns
);
804 trad_frame_reset_saved_regs (gdbarch
, cache
.saved_regs
);
805 CORE_ADDR end
= aarch64_analyze_prologue (gdbarch
, 0, 128, &cache
, reader
);
807 /* We should stop at the 5th instruction. */
808 SELF_CHECK (end
== (5 - 1) * 4);
809 SELF_CHECK (cache
.framereg
== AARCH64_SP_REGNUM
);
810 SELF_CHECK (cache
.framesize
== 64);
813 /* Test handling of movz when there is no frame pointer set or no stack
816 static const uint32_t insns
[] = {
817 0xa9bf7bfd, /* stp x29, x30, [sp, #-16]! */
818 0x52800020, /* mov w0, #0x1 */
819 0x528000a2, /* mov w2, #0x5 */
820 0x97fffff8, /* bl 6e4 */
823 instruction_reader_test
reader (insns
);
825 trad_frame_reset_saved_regs (gdbarch
, cache
.saved_regs
);
826 CORE_ADDR end
= aarch64_analyze_prologue (gdbarch
, 0, 128, &cache
, reader
);
828 /* We should stop at the 4th instruction. */
829 SELF_CHECK (end
== (4 - 1) * 4);
830 SELF_CHECK (cache
.framereg
== AARCH64_SP_REGNUM
);
831 SELF_CHECK (cache
.framesize
== 16);
834 /* Test a prologue in which there is a return address signing instruction. */
835 if (tdep
->has_pauth ())
837 static const uint32_t insns
[] = {
838 0xd503233f, /* paciasp */
839 0xa9bd7bfd, /* stp x29, x30, [sp, #-48]! */
840 0x910003fd, /* mov x29, sp */
841 0xf801c3f3, /* str x19, [sp, #28] */
842 0xb9401fa0, /* ldr x19, [x29, #28] */
844 instruction_reader_test
reader (insns
);
846 trad_frame_reset_saved_regs (gdbarch
, cache
.saved_regs
);
847 CORE_ADDR end
= aarch64_analyze_prologue (gdbarch
, 0, 128, &cache
,
850 SELF_CHECK (end
== 4 * 4);
851 SELF_CHECK (cache
.framereg
== AARCH64_FP_REGNUM
);
852 SELF_CHECK (cache
.framesize
== 48);
854 for (int i
= 0; i
< AARCH64_X_REGISTER_COUNT
; i
++)
857 SELF_CHECK (cache
.saved_regs
[i
].addr () == -20);
858 else if (i
== AARCH64_FP_REGNUM
)
859 SELF_CHECK (cache
.saved_regs
[i
].addr () == -48);
860 else if (i
== AARCH64_LR_REGNUM
)
861 SELF_CHECK (cache
.saved_regs
[i
].addr () == -40);
863 SELF_CHECK (cache
.saved_regs
[i
].is_realreg ()
864 && cache
.saved_regs
[i
].realreg () == i
);
867 if (tdep
->has_pauth ())
869 int regnum
= tdep
->pauth_ra_state_regnum
;
870 SELF_CHECK (cache
.saved_regs
[regnum
].is_value ());
874 } // namespace selftests
875 #endif /* GDB_SELF_TEST */
877 /* Implement the "skip_prologue" gdbarch method. */
880 aarch64_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
882 CORE_ADDR func_addr
, limit_pc
;
884 /* See if we can determine the end of the prologue via the symbol
885 table. If so, then return either PC, or the PC after the
886 prologue, whichever is greater. */
887 if (find_pc_partial_function (pc
, NULL
, &func_addr
, NULL
))
889 CORE_ADDR post_prologue_pc
890 = skip_prologue_using_sal (gdbarch
, func_addr
);
892 if (post_prologue_pc
!= 0)
893 return std::max (pc
, post_prologue_pc
);
896 /* Can't determine prologue from the symbol table, need to examine
899 /* Find an upper limit on the function prologue using the debug
900 information. If the debug information could not be used to
901 provide that bound, then use an arbitrary large number as the
903 limit_pc
= skip_prologue_using_sal (gdbarch
, pc
);
905 limit_pc
= pc
+ 128; /* Magic. */
907 /* Try disassembling prologue. */
908 return aarch64_analyze_prologue (gdbarch
, pc
, limit_pc
, NULL
);
911 /* Scan the function prologue for THIS_FRAME and populate the prologue
915 aarch64_scan_prologue (struct frame_info
*this_frame
,
916 struct aarch64_prologue_cache
*cache
)
918 CORE_ADDR block_addr
= get_frame_address_in_block (this_frame
);
919 CORE_ADDR prologue_start
;
920 CORE_ADDR prologue_end
;
921 CORE_ADDR prev_pc
= get_frame_pc (this_frame
);
922 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
924 cache
->prev_pc
= prev_pc
;
926 /* Assume we do not find a frame. */
927 cache
->framereg
= -1;
928 cache
->framesize
= 0;
930 if (find_pc_partial_function (block_addr
, NULL
, &prologue_start
,
933 struct symtab_and_line sal
= find_pc_line (prologue_start
, 0);
937 /* No line info so use the current PC. */
938 prologue_end
= prev_pc
;
940 else if (sal
.end
< prologue_end
)
942 /* The next line begins after the function end. */
943 prologue_end
= sal
.end
;
946 prologue_end
= std::min (prologue_end
, prev_pc
);
947 aarch64_analyze_prologue (gdbarch
, prologue_start
, prologue_end
, cache
);
953 frame_loc
= get_frame_register_unsigned (this_frame
, AARCH64_FP_REGNUM
);
957 cache
->framereg
= AARCH64_FP_REGNUM
;
958 cache
->framesize
= 16;
959 cache
->saved_regs
[29].set_addr (0);
960 cache
->saved_regs
[30].set_addr (8);
964 /* Fill in *CACHE with information about the prologue of *THIS_FRAME. This
965 function may throw an exception if the inferior's registers or memory is
969 aarch64_make_prologue_cache_1 (struct frame_info
*this_frame
,
970 struct aarch64_prologue_cache
*cache
)
972 CORE_ADDR unwound_fp
;
975 aarch64_scan_prologue (this_frame
, cache
);
977 if (cache
->framereg
== -1)
980 unwound_fp
= get_frame_register_unsigned (this_frame
, cache
->framereg
);
984 cache
->prev_sp
= unwound_fp
+ cache
->framesize
;
986 /* Calculate actual addresses of saved registers using offsets
987 determined by aarch64_analyze_prologue. */
988 for (reg
= 0; reg
< gdbarch_num_regs (get_frame_arch (this_frame
)); reg
++)
989 if (cache
->saved_regs
[reg
].is_addr ())
990 cache
->saved_regs
[reg
].set_addr (cache
->saved_regs
[reg
].addr ()
993 cache
->func
= get_frame_func (this_frame
);
995 cache
->available_p
= 1;
998 /* Allocate and fill in *THIS_CACHE with information about the prologue of
999 *THIS_FRAME. Do not do this is if *THIS_CACHE was already allocated.
1000 Return a pointer to the current aarch64_prologue_cache in
1003 static struct aarch64_prologue_cache
*
1004 aarch64_make_prologue_cache (struct frame_info
*this_frame
, void **this_cache
)
1006 struct aarch64_prologue_cache
*cache
;
1008 if (*this_cache
!= NULL
)
1009 return (struct aarch64_prologue_cache
*) *this_cache
;
1011 cache
= FRAME_OBSTACK_ZALLOC (struct aarch64_prologue_cache
);
1012 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
1013 *this_cache
= cache
;
1017 aarch64_make_prologue_cache_1 (this_frame
, cache
);
1019 catch (const gdb_exception_error
&ex
)
1021 if (ex
.error
!= NOT_AVAILABLE_ERROR
)
1028 /* Implement the "stop_reason" frame_unwind method. */
1030 static enum unwind_stop_reason
1031 aarch64_prologue_frame_unwind_stop_reason (struct frame_info
*this_frame
,
1034 struct aarch64_prologue_cache
*cache
1035 = aarch64_make_prologue_cache (this_frame
, this_cache
);
1037 if (!cache
->available_p
)
1038 return UNWIND_UNAVAILABLE
;
1040 /* Halt the backtrace at "_start". */
1041 gdbarch
*arch
= get_frame_arch (this_frame
);
1042 aarch64_gdbarch_tdep
*tdep
= (aarch64_gdbarch_tdep
*) gdbarch_tdep (arch
);
1043 if (cache
->prev_pc
<= tdep
->lowest_pc
)
1044 return UNWIND_OUTERMOST
;
1046 /* We've hit a wall, stop. */
1047 if (cache
->prev_sp
== 0)
1048 return UNWIND_OUTERMOST
;
1050 return UNWIND_NO_REASON
;
1053 /* Our frame ID for a normal frame is the current function's starting
1054 PC and the caller's SP when we were called. */
1057 aarch64_prologue_this_id (struct frame_info
*this_frame
,
1058 void **this_cache
, struct frame_id
*this_id
)
1060 struct aarch64_prologue_cache
*cache
1061 = aarch64_make_prologue_cache (this_frame
, this_cache
);
1063 if (!cache
->available_p
)
1064 *this_id
= frame_id_build_unavailable_stack (cache
->func
);
1066 *this_id
= frame_id_build (cache
->prev_sp
, cache
->func
);
1069 /* Implement the "prev_register" frame_unwind method. */
1071 static struct value
*
1072 aarch64_prologue_prev_register (struct frame_info
*this_frame
,
1073 void **this_cache
, int prev_regnum
)
1075 struct aarch64_prologue_cache
*cache
1076 = aarch64_make_prologue_cache (this_frame
, this_cache
);
1078 /* If we are asked to unwind the PC, then we need to return the LR
1079 instead. The prologue may save PC, but it will point into this
1080 frame's prologue, not the next frame's resume location. */
1081 if (prev_regnum
== AARCH64_PC_REGNUM
)
1084 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1085 aarch64_gdbarch_tdep
*tdep
1086 = (aarch64_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
1088 lr
= frame_unwind_register_unsigned (this_frame
, AARCH64_LR_REGNUM
);
1090 if (tdep
->has_pauth ()
1091 && cache
->saved_regs
[tdep
->pauth_ra_state_regnum
].is_value ())
1092 lr
= aarch64_frame_unmask_lr (tdep
, this_frame
, lr
);
1094 return frame_unwind_got_constant (this_frame
, prev_regnum
, lr
);
1097 /* SP is generally not saved to the stack, but this frame is
1098 identified by the next frame's stack pointer at the time of the
1099 call. The value was already reconstructed into PREV_SP. */
1105 | | | <- Previous SP
1108 +--| saved fp |<- FP
1112 if (prev_regnum
== AARCH64_SP_REGNUM
)
1113 return frame_unwind_got_constant (this_frame
, prev_regnum
,
1116 return trad_frame_get_prev_register (this_frame
, cache
->saved_regs
,
1120 /* AArch64 prologue unwinder. */
1121 static frame_unwind aarch64_prologue_unwind
=
1125 aarch64_prologue_frame_unwind_stop_reason
,
1126 aarch64_prologue_this_id
,
1127 aarch64_prologue_prev_register
,
1129 default_frame_sniffer
1132 /* Allocate and fill in *THIS_CACHE with information about the prologue of
1133 *THIS_FRAME. Do not do this is if *THIS_CACHE was already allocated.
1134 Return a pointer to the current aarch64_prologue_cache in
1137 static struct aarch64_prologue_cache
*
1138 aarch64_make_stub_cache (struct frame_info
*this_frame
, void **this_cache
)
1140 struct aarch64_prologue_cache
*cache
;
1142 if (*this_cache
!= NULL
)
1143 return (struct aarch64_prologue_cache
*) *this_cache
;
1145 cache
= FRAME_OBSTACK_ZALLOC (struct aarch64_prologue_cache
);
1146 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
1147 *this_cache
= cache
;
1151 cache
->prev_sp
= get_frame_register_unsigned (this_frame
,
1153 cache
->prev_pc
= get_frame_pc (this_frame
);
1154 cache
->available_p
= 1;
1156 catch (const gdb_exception_error
&ex
)
1158 if (ex
.error
!= NOT_AVAILABLE_ERROR
)
1165 /* Implement the "stop_reason" frame_unwind method. */
1167 static enum unwind_stop_reason
1168 aarch64_stub_frame_unwind_stop_reason (struct frame_info
*this_frame
,
1171 struct aarch64_prologue_cache
*cache
1172 = aarch64_make_stub_cache (this_frame
, this_cache
);
1174 if (!cache
->available_p
)
1175 return UNWIND_UNAVAILABLE
;
1177 return UNWIND_NO_REASON
;
1180 /* Our frame ID for a stub frame is the current SP and LR. */
1183 aarch64_stub_this_id (struct frame_info
*this_frame
,
1184 void **this_cache
, struct frame_id
*this_id
)
1186 struct aarch64_prologue_cache
*cache
1187 = aarch64_make_stub_cache (this_frame
, this_cache
);
1189 if (cache
->available_p
)
1190 *this_id
= frame_id_build (cache
->prev_sp
, cache
->prev_pc
);
1192 *this_id
= frame_id_build_unavailable_stack (cache
->prev_pc
);
1195 /* Implement the "sniffer" frame_unwind method. */
1198 aarch64_stub_unwind_sniffer (const struct frame_unwind
*self
,
1199 struct frame_info
*this_frame
,
1200 void **this_prologue_cache
)
1202 CORE_ADDR addr_in_block
;
1205 addr_in_block
= get_frame_address_in_block (this_frame
);
1206 if (in_plt_section (addr_in_block
)
1207 /* We also use the stub winder if the target memory is unreadable
1208 to avoid having the prologue unwinder trying to read it. */
1209 || target_read_memory (get_frame_pc (this_frame
), dummy
, 4) != 0)
1215 /* AArch64 stub unwinder. */
1216 static frame_unwind aarch64_stub_unwind
=
1220 aarch64_stub_frame_unwind_stop_reason
,
1221 aarch64_stub_this_id
,
1222 aarch64_prologue_prev_register
,
1224 aarch64_stub_unwind_sniffer
1227 /* Return the frame base address of *THIS_FRAME. */
1230 aarch64_normal_frame_base (struct frame_info
*this_frame
, void **this_cache
)
1232 struct aarch64_prologue_cache
*cache
1233 = aarch64_make_prologue_cache (this_frame
, this_cache
);
1235 return cache
->prev_sp
- cache
->framesize
;
1238 /* AArch64 default frame base information. */
1239 static frame_base aarch64_normal_base
=
1241 &aarch64_prologue_unwind
,
1242 aarch64_normal_frame_base
,
1243 aarch64_normal_frame_base
,
1244 aarch64_normal_frame_base
1247 /* Return the value of the REGNUM register in the previous frame of
1250 static struct value
*
1251 aarch64_dwarf2_prev_register (struct frame_info
*this_frame
,
1252 void **this_cache
, int regnum
)
1254 gdbarch
*arch
= get_frame_arch (this_frame
);
1255 aarch64_gdbarch_tdep
*tdep
= (aarch64_gdbarch_tdep
*) gdbarch_tdep (arch
);
1260 case AARCH64_PC_REGNUM
:
1261 lr
= frame_unwind_register_unsigned (this_frame
, AARCH64_LR_REGNUM
);
1262 lr
= aarch64_frame_unmask_lr (tdep
, this_frame
, lr
);
1263 return frame_unwind_got_constant (this_frame
, regnum
, lr
);
1266 internal_error (__FILE__
, __LINE__
,
1267 _("Unexpected register %d"), regnum
);
1271 static const unsigned char op_lit0
= DW_OP_lit0
;
1272 static const unsigned char op_lit1
= DW_OP_lit1
;
1274 /* Implement the "init_reg" dwarf2_frame_ops method. */
1277 aarch64_dwarf2_frame_init_reg (struct gdbarch
*gdbarch
, int regnum
,
1278 struct dwarf2_frame_state_reg
*reg
,
1279 struct frame_info
*this_frame
)
1281 aarch64_gdbarch_tdep
*tdep
= (aarch64_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
1285 case AARCH64_PC_REGNUM
:
1286 reg
->how
= DWARF2_FRAME_REG_FN
;
1287 reg
->loc
.fn
= aarch64_dwarf2_prev_register
;
1290 case AARCH64_SP_REGNUM
:
1291 reg
->how
= DWARF2_FRAME_REG_CFA
;
1295 /* Init pauth registers. */
1296 if (tdep
->has_pauth ())
1298 if (regnum
== tdep
->pauth_ra_state_regnum
)
1300 /* Initialize RA_STATE to zero. */
1301 reg
->how
= DWARF2_FRAME_REG_SAVED_VAL_EXP
;
1302 reg
->loc
.exp
.start
= &op_lit0
;
1303 reg
->loc
.exp
.len
= 1;
1306 else if (regnum
== AARCH64_PAUTH_DMASK_REGNUM (tdep
->pauth_reg_base
)
1307 || regnum
== AARCH64_PAUTH_CMASK_REGNUM (tdep
->pauth_reg_base
))
1309 reg
->how
= DWARF2_FRAME_REG_SAME_VALUE
;
1315 /* Implement the execute_dwarf_cfa_vendor_op method. */
1318 aarch64_execute_dwarf_cfa_vendor_op (struct gdbarch
*gdbarch
, gdb_byte op
,
1319 struct dwarf2_frame_state
*fs
)
1321 aarch64_gdbarch_tdep
*tdep
= (aarch64_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
1322 struct dwarf2_frame_state_reg
*ra_state
;
1324 if (op
== DW_CFA_AARCH64_negate_ra_state
)
1326 /* On systems without pauth, treat as a nop. */
1327 if (!tdep
->has_pauth ())
1330 /* Allocate RA_STATE column if it's not allocated yet. */
1331 fs
->regs
.alloc_regs (AARCH64_DWARF_PAUTH_RA_STATE
+ 1);
1333 /* Toggle the status of RA_STATE between 0 and 1. */
1334 ra_state
= &(fs
->regs
.reg
[AARCH64_DWARF_PAUTH_RA_STATE
]);
1335 ra_state
->how
= DWARF2_FRAME_REG_SAVED_VAL_EXP
;
1337 if (ra_state
->loc
.exp
.start
== nullptr
1338 || ra_state
->loc
.exp
.start
== &op_lit0
)
1339 ra_state
->loc
.exp
.start
= &op_lit1
;
1341 ra_state
->loc
.exp
.start
= &op_lit0
;
1343 ra_state
->loc
.exp
.len
= 1;
1351 /* Used for matching BRK instructions for AArch64. */
1352 static constexpr uint32_t BRK_INSN_MASK
= 0xffe0001f;
1353 static constexpr uint32_t BRK_INSN_BASE
= 0xd4200000;
1355 /* Implementation of gdbarch_program_breakpoint_here_p for aarch64. */
1358 aarch64_program_breakpoint_here_p (gdbarch
*gdbarch
, CORE_ADDR address
)
1360 const uint32_t insn_len
= 4;
1361 gdb_byte target_mem
[4];
1363 /* Enable the automatic memory restoration from breakpoints while
1364 we read the memory. Otherwise we may find temporary breakpoints, ones
1365 inserted by GDB, and flag them as permanent breakpoints. */
1366 scoped_restore restore_memory
1367 = make_scoped_restore_show_memory_breakpoints (0);
1369 if (target_read_memory (address
, target_mem
, insn_len
) == 0)
1372 (uint32_t) extract_unsigned_integer (target_mem
, insn_len
,
1373 gdbarch_byte_order_for_code (gdbarch
));
1375 /* Check if INSN is a BRK instruction pattern. There are multiple choices
1376 of such instructions with different immediate values. Different OS'
1377 may use a different variation, but they have the same outcome. */
1378 return ((insn
& BRK_INSN_MASK
) == BRK_INSN_BASE
);
1384 /* When arguments must be pushed onto the stack, they go on in reverse
1385 order. The code below implements a FILO (stack) to do this. */
1389 /* Value to pass on stack. It can be NULL if this item is for stack
1391 const gdb_byte
*data
;
1393 /* Size in bytes of value to pass on stack. */
1397 /* Implement the gdbarch type alignment method, overrides the generic
1398 alignment algorithm for anything that is aarch64 specific. */
1401 aarch64_type_align (gdbarch
*gdbarch
, struct type
*t
)
1403 t
= check_typedef (t
);
1404 if (t
->code () == TYPE_CODE_ARRAY
&& t
->is_vector ())
1406 /* Use the natural alignment for vector types (the same for
1407 scalar type), but the maximum alignment is 128-bit. */
1408 if (TYPE_LENGTH (t
) > 16)
1411 return TYPE_LENGTH (t
);
1414 /* Allow the common code to calculate the alignment. */
1418 /* Worker function for aapcs_is_vfp_call_or_return_candidate.
1420 Return the number of register required, or -1 on failure.
1422 When encountering a base element, if FUNDAMENTAL_TYPE is not set then set it
1423 to the element, else fail if the type of this element does not match the
1427 aapcs_is_vfp_call_or_return_candidate_1 (struct type
*type
,
1428 struct type
**fundamental_type
)
1430 if (type
== nullptr)
1433 switch (type
->code ())
1436 if (TYPE_LENGTH (type
) > 16)
1439 if (*fundamental_type
== nullptr)
1440 *fundamental_type
= type
;
1441 else if (TYPE_LENGTH (type
) != TYPE_LENGTH (*fundamental_type
)
1442 || type
->code () != (*fundamental_type
)->code ())
1447 case TYPE_CODE_COMPLEX
:
1449 struct type
*target_type
= check_typedef (TYPE_TARGET_TYPE (type
));
1450 if (TYPE_LENGTH (target_type
) > 16)
1453 if (*fundamental_type
== nullptr)
1454 *fundamental_type
= target_type
;
1455 else if (TYPE_LENGTH (target_type
) != TYPE_LENGTH (*fundamental_type
)
1456 || target_type
->code () != (*fundamental_type
)->code ())
1462 case TYPE_CODE_ARRAY
:
1464 if (type
->is_vector ())
1466 if (TYPE_LENGTH (type
) != 8 && TYPE_LENGTH (type
) != 16)
1469 if (*fundamental_type
== nullptr)
1470 *fundamental_type
= type
;
1471 else if (TYPE_LENGTH (type
) != TYPE_LENGTH (*fundamental_type
)
1472 || type
->code () != (*fundamental_type
)->code ())
1479 struct type
*target_type
= TYPE_TARGET_TYPE (type
);
1480 int count
= aapcs_is_vfp_call_or_return_candidate_1
1481 (target_type
, fundamental_type
);
1486 count
*= (TYPE_LENGTH (type
) / TYPE_LENGTH (target_type
));
1491 case TYPE_CODE_STRUCT
:
1492 case TYPE_CODE_UNION
:
1496 for (int i
= 0; i
< type
->num_fields (); i
++)
1498 /* Ignore any static fields. */
1499 if (field_is_static (&type
->field (i
)))
1502 struct type
*member
= check_typedef (type
->field (i
).type ());
1504 int sub_count
= aapcs_is_vfp_call_or_return_candidate_1
1505 (member
, fundamental_type
);
1506 if (sub_count
== -1)
1511 /* Ensure there is no padding between the fields (allowing for empty
1512 zero length structs) */
1513 int ftype_length
= (*fundamental_type
== nullptr)
1514 ? 0 : TYPE_LENGTH (*fundamental_type
);
1515 if (count
* ftype_length
!= TYPE_LENGTH (type
))
1528 /* Return true if an argument, whose type is described by TYPE, can be passed or
1529 returned in simd/fp registers, providing enough parameter passing registers
1530 are available. This is as described in the AAPCS64.
1532 Upon successful return, *COUNT returns the number of needed registers,
1533 *FUNDAMENTAL_TYPE contains the type of those registers.
1535 Candidate as per the AAPCS64 5.4.2.C is either a:
1538 - HFA (Homogeneous Floating-point Aggregate, 4.3.5.1). A Composite type where
1539 all the members are floats and has at most 4 members.
1540 - HVA (Homogeneous Short-vector Aggregate, 4.3.5.2). A Composite type where
1541 all the members are short vectors and has at most 4 members.
1544 Note that HFAs and HVAs can include nested structures and arrays. */
1547 aapcs_is_vfp_call_or_return_candidate (struct type
*type
, int *count
,
1548 struct type
**fundamental_type
)
1550 if (type
== nullptr)
1553 *fundamental_type
= nullptr;
1555 int ag_count
= aapcs_is_vfp_call_or_return_candidate_1 (type
,
1558 if (ag_count
> 0 && ag_count
<= HA_MAX_NUM_FLDS
)
1567 /* AArch64 function call information structure. */
1568 struct aarch64_call_info
1570 /* the current argument number. */
1571 unsigned argnum
= 0;
1573 /* The next general purpose register number, equivalent to NGRN as
1574 described in the AArch64 Procedure Call Standard. */
1577 /* The next SIMD and floating point register number, equivalent to
1578 NSRN as described in the AArch64 Procedure Call Standard. */
1581 /* The next stacked argument address, equivalent to NSAA as
1582 described in the AArch64 Procedure Call Standard. */
1585 /* Stack item vector. */
1586 std::vector
<stack_item_t
> si
;
1589 /* Pass a value in a sequence of consecutive X registers. The caller
1590 is responsible for ensuring sufficient registers are available. */
1593 pass_in_x (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
1594 struct aarch64_call_info
*info
, struct type
*type
,
1597 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1598 int len
= TYPE_LENGTH (type
);
1599 enum type_code typecode
= type
->code ();
1600 int regnum
= AARCH64_X0_REGNUM
+ info
->ngrn
;
1601 const bfd_byte
*buf
= value_contents (arg
).data ();
1607 int partial_len
= len
< X_REGISTER_SIZE
? len
: X_REGISTER_SIZE
;
1608 CORE_ADDR regval
= extract_unsigned_integer (buf
, partial_len
,
1612 /* Adjust sub-word struct/union args when big-endian. */
1613 if (byte_order
== BFD_ENDIAN_BIG
1614 && partial_len
< X_REGISTER_SIZE
1615 && (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
))
1616 regval
<<= ((X_REGISTER_SIZE
- partial_len
) * TARGET_CHAR_BIT
);
1618 aarch64_debug_printf ("arg %d in %s = 0x%s", info
->argnum
,
1619 gdbarch_register_name (gdbarch
, regnum
),
1620 phex (regval
, X_REGISTER_SIZE
));
1622 regcache_cooked_write_unsigned (regcache
, regnum
, regval
);
1629 /* Attempt to marshall a value in a V register. Return 1 if
1630 successful, or 0 if insufficient registers are available. This
1631 function, unlike the equivalent pass_in_x() function does not
1632 handle arguments spread across multiple registers. */
1635 pass_in_v (struct gdbarch
*gdbarch
,
1636 struct regcache
*regcache
,
1637 struct aarch64_call_info
*info
,
1638 int len
, const bfd_byte
*buf
)
1642 int regnum
= AARCH64_V0_REGNUM
+ info
->nsrn
;
1643 /* Enough space for a full vector register. */
1644 gdb_byte reg
[register_size (gdbarch
, regnum
)];
1645 gdb_assert (len
<= sizeof (reg
));
1650 memset (reg
, 0, sizeof (reg
));
1651 /* PCS C.1, the argument is allocated to the least significant
1652 bits of V register. */
1653 memcpy (reg
, buf
, len
);
1654 regcache
->cooked_write (regnum
, reg
);
1656 aarch64_debug_printf ("arg %d in %s", info
->argnum
,
1657 gdbarch_register_name (gdbarch
, regnum
));
1665 /* Marshall an argument onto the stack. */
1668 pass_on_stack (struct aarch64_call_info
*info
, struct type
*type
,
1671 const bfd_byte
*buf
= value_contents (arg
).data ();
1672 int len
= TYPE_LENGTH (type
);
1678 align
= type_align (type
);
1680 /* PCS C.17 Stack should be aligned to the larger of 8 bytes or the
1681 Natural alignment of the argument's type. */
1682 align
= align_up (align
, 8);
1684 /* The AArch64 PCS requires at most doubleword alignment. */
1688 aarch64_debug_printf ("arg %d len=%d @ sp + %d\n", info
->argnum
, len
,
1693 info
->si
.push_back (item
);
1696 if (info
->nsaa
& (align
- 1))
1698 /* Push stack alignment padding. */
1699 int pad
= align
- (info
->nsaa
& (align
- 1));
1704 info
->si
.push_back (item
);
1709 /* Marshall an argument into a sequence of one or more consecutive X
1710 registers or, if insufficient X registers are available then onto
1714 pass_in_x_or_stack (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
1715 struct aarch64_call_info
*info
, struct type
*type
,
1718 int len
= TYPE_LENGTH (type
);
1719 int nregs
= (len
+ X_REGISTER_SIZE
- 1) / X_REGISTER_SIZE
;
1721 /* PCS C.13 - Pass in registers if we have enough spare */
1722 if (info
->ngrn
+ nregs
<= 8)
1724 pass_in_x (gdbarch
, regcache
, info
, type
, arg
);
1725 info
->ngrn
+= nregs
;
1730 pass_on_stack (info
, type
, arg
);
1734 /* Pass a value, which is of type arg_type, in a V register. Assumes value is a
1735 aapcs_is_vfp_call_or_return_candidate and there are enough spare V
1736 registers. A return value of false is an error state as the value will have
1737 been partially passed to the stack. */
1739 pass_in_v_vfp_candidate (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
1740 struct aarch64_call_info
*info
, struct type
*arg_type
,
1743 switch (arg_type
->code ())
1746 return pass_in_v (gdbarch
, regcache
, info
, TYPE_LENGTH (arg_type
),
1747 value_contents (arg
).data ());
1750 case TYPE_CODE_COMPLEX
:
1752 const bfd_byte
*buf
= value_contents (arg
).data ();
1753 struct type
*target_type
= check_typedef (TYPE_TARGET_TYPE (arg_type
));
1755 if (!pass_in_v (gdbarch
, regcache
, info
, TYPE_LENGTH (target_type
),
1759 return pass_in_v (gdbarch
, regcache
, info
, TYPE_LENGTH (target_type
),
1760 buf
+ TYPE_LENGTH (target_type
));
1763 case TYPE_CODE_ARRAY
:
1764 if (arg_type
->is_vector ())
1765 return pass_in_v (gdbarch
, regcache
, info
, TYPE_LENGTH (arg_type
),
1766 value_contents (arg
).data ());
1769 case TYPE_CODE_STRUCT
:
1770 case TYPE_CODE_UNION
:
1771 for (int i
= 0; i
< arg_type
->num_fields (); i
++)
1773 /* Don't include static fields. */
1774 if (field_is_static (&arg_type
->field (i
)))
1777 struct value
*field
= value_primitive_field (arg
, 0, i
, arg_type
);
1778 struct type
*field_type
= check_typedef (value_type (field
));
1780 if (!pass_in_v_vfp_candidate (gdbarch
, regcache
, info
, field_type
,
1791 /* Implement the "push_dummy_call" gdbarch method. */
1794 aarch64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
1795 struct regcache
*regcache
, CORE_ADDR bp_addr
,
1797 struct value
**args
, CORE_ADDR sp
,
1798 function_call_return_method return_method
,
1799 CORE_ADDR struct_addr
)
1802 struct aarch64_call_info info
;
1804 /* We need to know what the type of the called function is in order
1805 to determine the number of named/anonymous arguments for the
1806 actual argument placement, and the return type in order to handle
1807 return value correctly.
1809 The generic code above us views the decision of return in memory
1810 or return in registers as a two stage processes. The language
1811 handler is consulted first and may decide to return in memory (eg
1812 class with copy constructor returned by value), this will cause
1813 the generic code to allocate space AND insert an initial leading
1816 If the language code does not decide to pass in memory then the
1817 target code is consulted.
1819 If the language code decides to pass in memory we want to move
1820 the pointer inserted as the initial argument from the argument
1821 list and into X8, the conventional AArch64 struct return pointer
1824 /* Set the return address. For the AArch64, the return breakpoint
1825 is always at BP_ADDR. */
1826 regcache_cooked_write_unsigned (regcache
, AARCH64_LR_REGNUM
, bp_addr
);
1828 /* If we were given an initial argument for the return slot, lose it. */
1829 if (return_method
== return_method_hidden_param
)
1835 /* The struct_return pointer occupies X8. */
1836 if (return_method
!= return_method_normal
)
1838 aarch64_debug_printf ("struct return in %s = 0x%s",
1839 gdbarch_register_name
1840 (gdbarch
, AARCH64_STRUCT_RETURN_REGNUM
),
1841 paddress (gdbarch
, struct_addr
));
1843 regcache_cooked_write_unsigned (regcache
, AARCH64_STRUCT_RETURN_REGNUM
,
1847 for (argnum
= 0; argnum
< nargs
; argnum
++)
1849 struct value
*arg
= args
[argnum
];
1850 struct type
*arg_type
, *fundamental_type
;
1853 arg_type
= check_typedef (value_type (arg
));
1854 len
= TYPE_LENGTH (arg_type
);
1856 /* If arg can be passed in v registers as per the AAPCS64, then do so if
1857 if there are enough spare registers. */
1858 if (aapcs_is_vfp_call_or_return_candidate (arg_type
, &elements
,
1861 if (info
.nsrn
+ elements
<= 8)
1863 /* We know that we have sufficient registers available therefore
1864 this will never need to fallback to the stack. */
1865 if (!pass_in_v_vfp_candidate (gdbarch
, regcache
, &info
, arg_type
,
1867 gdb_assert_not_reached ("Failed to push args");
1872 pass_on_stack (&info
, arg_type
, arg
);
1877 switch (arg_type
->code ())
1880 case TYPE_CODE_BOOL
:
1881 case TYPE_CODE_CHAR
:
1882 case TYPE_CODE_RANGE
:
1883 case TYPE_CODE_ENUM
:
1886 /* Promote to 32 bit integer. */
1887 if (arg_type
->is_unsigned ())
1888 arg_type
= builtin_type (gdbarch
)->builtin_uint32
;
1890 arg_type
= builtin_type (gdbarch
)->builtin_int32
;
1891 arg
= value_cast (arg_type
, arg
);
1893 pass_in_x_or_stack (gdbarch
, regcache
, &info
, arg_type
, arg
);
1896 case TYPE_CODE_STRUCT
:
1897 case TYPE_CODE_ARRAY
:
1898 case TYPE_CODE_UNION
:
1901 /* PCS B.7 Aggregates larger than 16 bytes are passed by
1902 invisible reference. */
1904 /* Allocate aligned storage. */
1905 sp
= align_down (sp
- len
, 16);
1907 /* Write the real data into the stack. */
1908 write_memory (sp
, value_contents (arg
).data (), len
);
1910 /* Construct the indirection. */
1911 arg_type
= lookup_pointer_type (arg_type
);
1912 arg
= value_from_pointer (arg_type
, sp
);
1913 pass_in_x_or_stack (gdbarch
, regcache
, &info
, arg_type
, arg
);
1916 /* PCS C.15 / C.18 multiple values pass. */
1917 pass_in_x_or_stack (gdbarch
, regcache
, &info
, arg_type
, arg
);
1921 pass_in_x_or_stack (gdbarch
, regcache
, &info
, arg_type
, arg
);
1926 /* Make sure stack retains 16 byte alignment. */
1928 sp
-= 16 - (info
.nsaa
& 15);
1930 while (!info
.si
.empty ())
1932 const stack_item_t
&si
= info
.si
.back ();
1935 if (si
.data
!= NULL
)
1936 write_memory (sp
, si
.data
, si
.len
);
1937 info
.si
.pop_back ();
1940 /* Finally, update the SP register. */
1941 regcache_cooked_write_unsigned (regcache
, AARCH64_SP_REGNUM
, sp
);
1946 /* Implement the "frame_align" gdbarch method. */
1949 aarch64_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR sp
)
1951 /* Align the stack to sixteen bytes. */
1952 return sp
& ~(CORE_ADDR
) 15;
1955 /* Return the type for an AdvSISD Q register. */
1957 static struct type
*
1958 aarch64_vnq_type (struct gdbarch
*gdbarch
)
1960 aarch64_gdbarch_tdep
*tdep
= (aarch64_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
1962 if (tdep
->vnq_type
== NULL
)
1967 t
= arch_composite_type (gdbarch
, "__gdb_builtin_type_vnq",
1970 elem
= builtin_type (gdbarch
)->builtin_uint128
;
1971 append_composite_type_field (t
, "u", elem
);
1973 elem
= builtin_type (gdbarch
)->builtin_int128
;
1974 append_composite_type_field (t
, "s", elem
);
1979 return tdep
->vnq_type
;
1982 /* Return the type for an AdvSISD D register. */
1984 static struct type
*
1985 aarch64_vnd_type (struct gdbarch
*gdbarch
)
1987 aarch64_gdbarch_tdep
*tdep
= (aarch64_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
1989 if (tdep
->vnd_type
== NULL
)
1994 t
= arch_composite_type (gdbarch
, "__gdb_builtin_type_vnd",
1997 elem
= builtin_type (gdbarch
)->builtin_double
;
1998 append_composite_type_field (t
, "f", elem
);
2000 elem
= builtin_type (gdbarch
)->builtin_uint64
;
2001 append_composite_type_field (t
, "u", elem
);
2003 elem
= builtin_type (gdbarch
)->builtin_int64
;
2004 append_composite_type_field (t
, "s", elem
);
2009 return tdep
->vnd_type
;
2012 /* Return the type for an AdvSISD S register. */
2014 static struct type
*
2015 aarch64_vns_type (struct gdbarch
*gdbarch
)
2017 aarch64_gdbarch_tdep
*tdep
= (aarch64_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
2019 if (tdep
->vns_type
== NULL
)
2024 t
= arch_composite_type (gdbarch
, "__gdb_builtin_type_vns",
2027 elem
= builtin_type (gdbarch
)->builtin_float
;
2028 append_composite_type_field (t
, "f", elem
);
2030 elem
= builtin_type (gdbarch
)->builtin_uint32
;
2031 append_composite_type_field (t
, "u", elem
);
2033 elem
= builtin_type (gdbarch
)->builtin_int32
;
2034 append_composite_type_field (t
, "s", elem
);
2039 return tdep
->vns_type
;
2042 /* Return the type for an AdvSISD H register. */
2044 static struct type
*
2045 aarch64_vnh_type (struct gdbarch
*gdbarch
)
2047 aarch64_gdbarch_tdep
*tdep
= (aarch64_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
2049 if (tdep
->vnh_type
== NULL
)
2054 t
= arch_composite_type (gdbarch
, "__gdb_builtin_type_vnh",
2057 elem
= builtin_type (gdbarch
)->builtin_bfloat16
;
2058 append_composite_type_field (t
, "bf", elem
);
2060 elem
= builtin_type (gdbarch
)->builtin_half
;
2061 append_composite_type_field (t
, "f", elem
);
2063 elem
= builtin_type (gdbarch
)->builtin_uint16
;
2064 append_composite_type_field (t
, "u", elem
);
2066 elem
= builtin_type (gdbarch
)->builtin_int16
;
2067 append_composite_type_field (t
, "s", elem
);
2072 return tdep
->vnh_type
;
2075 /* Return the type for an AdvSISD B register. */
2077 static struct type
*
2078 aarch64_vnb_type (struct gdbarch
*gdbarch
)
2080 aarch64_gdbarch_tdep
*tdep
= (aarch64_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
2082 if (tdep
->vnb_type
== NULL
)
2087 t
= arch_composite_type (gdbarch
, "__gdb_builtin_type_vnb",
2090 elem
= builtin_type (gdbarch
)->builtin_uint8
;
2091 append_composite_type_field (t
, "u", elem
);
2093 elem
= builtin_type (gdbarch
)->builtin_int8
;
2094 append_composite_type_field (t
, "s", elem
);
2099 return tdep
->vnb_type
;
2102 /* Return the type for an AdvSISD V register. */
2104 static struct type
*
2105 aarch64_vnv_type (struct gdbarch
*gdbarch
)
2107 aarch64_gdbarch_tdep
*tdep
= (aarch64_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
2109 if (tdep
->vnv_type
== NULL
)
2111 /* The other AArch64 pseudo registers (Q,D,H,S,B) refer to a single value
2112 slice from the non-pseudo vector registers. However NEON V registers
2113 are always vector registers, and need constructing as such. */
2114 const struct builtin_type
*bt
= builtin_type (gdbarch
);
2116 struct type
*t
= arch_composite_type (gdbarch
, "__gdb_builtin_type_vnv",
2119 struct type
*sub
= arch_composite_type (gdbarch
, "__gdb_builtin_type_vnd",
2121 append_composite_type_field (sub
, "f",
2122 init_vector_type (bt
->builtin_double
, 2));
2123 append_composite_type_field (sub
, "u",
2124 init_vector_type (bt
->builtin_uint64
, 2));
2125 append_composite_type_field (sub
, "s",
2126 init_vector_type (bt
->builtin_int64
, 2));
2127 append_composite_type_field (t
, "d", sub
);
2129 sub
= arch_composite_type (gdbarch
, "__gdb_builtin_type_vns",
2131 append_composite_type_field (sub
, "f",
2132 init_vector_type (bt
->builtin_float
, 4));
2133 append_composite_type_field (sub
, "u",
2134 init_vector_type (bt
->builtin_uint32
, 4));
2135 append_composite_type_field (sub
, "s",
2136 init_vector_type (bt
->builtin_int32
, 4));
2137 append_composite_type_field (t
, "s", sub
);
2139 sub
= arch_composite_type (gdbarch
, "__gdb_builtin_type_vnh",
2141 append_composite_type_field (sub
, "bf",
2142 init_vector_type (bt
->builtin_bfloat16
, 8));
2143 append_composite_type_field (sub
, "f",
2144 init_vector_type (bt
->builtin_half
, 8));
2145 append_composite_type_field (sub
, "u",
2146 init_vector_type (bt
->builtin_uint16
, 8));
2147 append_composite_type_field (sub
, "s",
2148 init_vector_type (bt
->builtin_int16
, 8));
2149 append_composite_type_field (t
, "h", sub
);
2151 sub
= arch_composite_type (gdbarch
, "__gdb_builtin_type_vnb",
2153 append_composite_type_field (sub
, "u",
2154 init_vector_type (bt
->builtin_uint8
, 16));
2155 append_composite_type_field (sub
, "s",
2156 init_vector_type (bt
->builtin_int8
, 16));
2157 append_composite_type_field (t
, "b", sub
);
2159 sub
= arch_composite_type (gdbarch
, "__gdb_builtin_type_vnq",
2161 append_composite_type_field (sub
, "u",
2162 init_vector_type (bt
->builtin_uint128
, 1));
2163 append_composite_type_field (sub
, "s",
2164 init_vector_type (bt
->builtin_int128
, 1));
2165 append_composite_type_field (t
, "q", sub
);
2170 return tdep
->vnv_type
;
2173 /* Implement the "dwarf2_reg_to_regnum" gdbarch method. */
2176 aarch64_dwarf_reg_to_regnum (struct gdbarch
*gdbarch
, int reg
)
2178 aarch64_gdbarch_tdep
*tdep
= (aarch64_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
2180 if (reg
>= AARCH64_DWARF_X0
&& reg
<= AARCH64_DWARF_X0
+ 30)
2181 return AARCH64_X0_REGNUM
+ reg
- AARCH64_DWARF_X0
;
2183 if (reg
== AARCH64_DWARF_SP
)
2184 return AARCH64_SP_REGNUM
;
2186 if (reg
>= AARCH64_DWARF_V0
&& reg
<= AARCH64_DWARF_V0
+ 31)
2187 return AARCH64_V0_REGNUM
+ reg
- AARCH64_DWARF_V0
;
2189 if (reg
== AARCH64_DWARF_SVE_VG
)
2190 return AARCH64_SVE_VG_REGNUM
;
2192 if (reg
== AARCH64_DWARF_SVE_FFR
)
2193 return AARCH64_SVE_FFR_REGNUM
;
2195 if (reg
>= AARCH64_DWARF_SVE_P0
&& reg
<= AARCH64_DWARF_SVE_P0
+ 15)
2196 return AARCH64_SVE_P0_REGNUM
+ reg
- AARCH64_DWARF_SVE_P0
;
2198 if (reg
>= AARCH64_DWARF_SVE_Z0
&& reg
<= AARCH64_DWARF_SVE_Z0
+ 15)
2199 return AARCH64_SVE_Z0_REGNUM
+ reg
- AARCH64_DWARF_SVE_Z0
;
2201 if (tdep
->has_pauth ())
2203 if (reg
>= AARCH64_DWARF_PAUTH_DMASK
&& reg
<= AARCH64_DWARF_PAUTH_CMASK
)
2204 return tdep
->pauth_reg_base
+ reg
- AARCH64_DWARF_PAUTH_DMASK
;
2206 if (reg
== AARCH64_DWARF_PAUTH_RA_STATE
)
2207 return tdep
->pauth_ra_state_regnum
;
2213 /* Implement the "print_insn" gdbarch method. */
2216 aarch64_gdb_print_insn (bfd_vma memaddr
, disassemble_info
*info
)
2218 info
->symbols
= NULL
;
2219 return default_print_insn (memaddr
, info
);
2222 /* AArch64 BRK software debug mode instruction.
2223 Note that AArch64 code is always little-endian.
2224 1101.0100.0010.0000.0000.0000.0000.0000 = 0xd4200000. */
2225 constexpr gdb_byte aarch64_default_breakpoint
[] = {0x00, 0x00, 0x20, 0xd4};
2227 typedef BP_MANIPULATION (aarch64_default_breakpoint
) aarch64_breakpoint
;
2229 /* Extract from an array REGS containing the (raw) register state a
2230 function return value of type TYPE, and copy that, in virtual
2231 format, into VALBUF. */
2234 aarch64_extract_return_value (struct type
*type
, struct regcache
*regs
,
2237 struct gdbarch
*gdbarch
= regs
->arch ();
2238 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2240 struct type
*fundamental_type
;
2242 if (aapcs_is_vfp_call_or_return_candidate (type
, &elements
,
2245 int len
= TYPE_LENGTH (fundamental_type
);
2247 for (int i
= 0; i
< elements
; i
++)
2249 int regno
= AARCH64_V0_REGNUM
+ i
;
2250 /* Enough space for a full vector register. */
2251 gdb_byte buf
[register_size (gdbarch
, regno
)];
2252 gdb_assert (len
<= sizeof (buf
));
2254 aarch64_debug_printf
2255 ("read HFA or HVA return value element %d from %s",
2256 i
+ 1, gdbarch_register_name (gdbarch
, regno
));
2258 regs
->cooked_read (regno
, buf
);
2260 memcpy (valbuf
, buf
, len
);
2264 else if (type
->code () == TYPE_CODE_INT
2265 || type
->code () == TYPE_CODE_CHAR
2266 || type
->code () == TYPE_CODE_BOOL
2267 || type
->code () == TYPE_CODE_PTR
2268 || TYPE_IS_REFERENCE (type
)
2269 || type
->code () == TYPE_CODE_ENUM
)
2271 /* If the type is a plain integer, then the access is
2272 straight-forward. Otherwise we have to play around a bit
2274 int len
= TYPE_LENGTH (type
);
2275 int regno
= AARCH64_X0_REGNUM
;
2280 /* By using store_unsigned_integer we avoid having to do
2281 anything special for small big-endian values. */
2282 regcache_cooked_read_unsigned (regs
, regno
++, &tmp
);
2283 store_unsigned_integer (valbuf
,
2284 (len
> X_REGISTER_SIZE
2285 ? X_REGISTER_SIZE
: len
), byte_order
, tmp
);
2286 len
-= X_REGISTER_SIZE
;
2287 valbuf
+= X_REGISTER_SIZE
;
2292 /* For a structure or union the behaviour is as if the value had
2293 been stored to word-aligned memory and then loaded into
2294 registers with 64-bit load instruction(s). */
2295 int len
= TYPE_LENGTH (type
);
2296 int regno
= AARCH64_X0_REGNUM
;
2297 bfd_byte buf
[X_REGISTER_SIZE
];
2301 regs
->cooked_read (regno
++, buf
);
2302 memcpy (valbuf
, buf
, len
> X_REGISTER_SIZE
? X_REGISTER_SIZE
: len
);
2303 len
-= X_REGISTER_SIZE
;
2304 valbuf
+= X_REGISTER_SIZE
;
2310 /* Will a function return an aggregate type in memory or in a
2311 register? Return 0 if an aggregate type can be returned in a
2312 register, 1 if it must be returned in memory. */
2315 aarch64_return_in_memory (struct gdbarch
*gdbarch
, struct type
*type
)
2317 type
= check_typedef (type
);
2319 struct type
*fundamental_type
;
2321 if (aapcs_is_vfp_call_or_return_candidate (type
, &elements
,
2324 /* v0-v7 are used to return values and one register is allocated
2325 for one member. However, HFA or HVA has at most four members. */
2329 if (TYPE_LENGTH (type
) > 16)
2331 /* PCS B.6 Aggregates larger than 16 bytes are passed by
2332 invisible reference. */
2340 /* Write into appropriate registers a function return value of type
2341 TYPE, given in virtual format. */
2344 aarch64_store_return_value (struct type
*type
, struct regcache
*regs
,
2345 const gdb_byte
*valbuf
)
2347 struct gdbarch
*gdbarch
= regs
->arch ();
2348 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2350 struct type
*fundamental_type
;
2352 if (aapcs_is_vfp_call_or_return_candidate (type
, &elements
,
2355 int len
= TYPE_LENGTH (fundamental_type
);
2357 for (int i
= 0; i
< elements
; i
++)
2359 int regno
= AARCH64_V0_REGNUM
+ i
;
2360 /* Enough space for a full vector register. */
2361 gdb_byte tmpbuf
[register_size (gdbarch
, regno
)];
2362 gdb_assert (len
<= sizeof (tmpbuf
));
2364 aarch64_debug_printf
2365 ("write HFA or HVA return value element %d to %s",
2366 i
+ 1, gdbarch_register_name (gdbarch
, regno
));
2368 memcpy (tmpbuf
, valbuf
,
2369 len
> V_REGISTER_SIZE
? V_REGISTER_SIZE
: len
);
2370 regs
->cooked_write (regno
, tmpbuf
);
2374 else if (type
->code () == TYPE_CODE_INT
2375 || type
->code () == TYPE_CODE_CHAR
2376 || type
->code () == TYPE_CODE_BOOL
2377 || type
->code () == TYPE_CODE_PTR
2378 || TYPE_IS_REFERENCE (type
)
2379 || type
->code () == TYPE_CODE_ENUM
)
2381 if (TYPE_LENGTH (type
) <= X_REGISTER_SIZE
)
2383 /* Values of one word or less are zero/sign-extended and
2385 bfd_byte tmpbuf
[X_REGISTER_SIZE
];
2386 LONGEST val
= unpack_long (type
, valbuf
);
2388 store_signed_integer (tmpbuf
, X_REGISTER_SIZE
, byte_order
, val
);
2389 regs
->cooked_write (AARCH64_X0_REGNUM
, tmpbuf
);
2393 /* Integral values greater than one word are stored in
2394 consecutive registers starting with r0. This will always
2395 be a multiple of the regiser size. */
2396 int len
= TYPE_LENGTH (type
);
2397 int regno
= AARCH64_X0_REGNUM
;
2401 regs
->cooked_write (regno
++, valbuf
);
2402 len
-= X_REGISTER_SIZE
;
2403 valbuf
+= X_REGISTER_SIZE
;
2409 /* For a structure or union the behaviour is as if the value had
2410 been stored to word-aligned memory and then loaded into
2411 registers with 64-bit load instruction(s). */
2412 int len
= TYPE_LENGTH (type
);
2413 int regno
= AARCH64_X0_REGNUM
;
2414 bfd_byte tmpbuf
[X_REGISTER_SIZE
];
2418 memcpy (tmpbuf
, valbuf
,
2419 len
> X_REGISTER_SIZE
? X_REGISTER_SIZE
: len
);
2420 regs
->cooked_write (regno
++, tmpbuf
);
2421 len
-= X_REGISTER_SIZE
;
2422 valbuf
+= X_REGISTER_SIZE
;
2427 /* Implement the "return_value" gdbarch method. */
2429 static enum return_value_convention
2430 aarch64_return_value (struct gdbarch
*gdbarch
, struct value
*func_value
,
2431 struct type
*valtype
, struct regcache
*regcache
,
2432 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
2435 if (valtype
->code () == TYPE_CODE_STRUCT
2436 || valtype
->code () == TYPE_CODE_UNION
2437 || valtype
->code () == TYPE_CODE_ARRAY
)
2439 if (aarch64_return_in_memory (gdbarch
, valtype
))
2441 aarch64_debug_printf ("return value in memory");
2442 return RETURN_VALUE_STRUCT_CONVENTION
;
2447 aarch64_store_return_value (valtype
, regcache
, writebuf
);
2450 aarch64_extract_return_value (valtype
, regcache
, readbuf
);
2452 aarch64_debug_printf ("return value in registers");
2454 return RETURN_VALUE_REGISTER_CONVENTION
;
2457 /* Implement the "get_longjmp_target" gdbarch method. */
2460 aarch64_get_longjmp_target (struct frame_info
*frame
, CORE_ADDR
*pc
)
2463 gdb_byte buf
[X_REGISTER_SIZE
];
2464 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2465 aarch64_gdbarch_tdep
*tdep
= (aarch64_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
2466 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2468 jb_addr
= get_frame_register_unsigned (frame
, AARCH64_X0_REGNUM
);
2470 if (target_read_memory (jb_addr
+ tdep
->jb_pc
* tdep
->jb_elt_size
, buf
,
2474 *pc
= extract_unsigned_integer (buf
, X_REGISTER_SIZE
, byte_order
);
2478 /* Implement the "gen_return_address" gdbarch method. */
2481 aarch64_gen_return_address (struct gdbarch
*gdbarch
,
2482 struct agent_expr
*ax
, struct axs_value
*value
,
2485 value
->type
= register_type (gdbarch
, AARCH64_LR_REGNUM
);
2486 value
->kind
= axs_lvalue_register
;
2487 value
->u
.reg
= AARCH64_LR_REGNUM
;
2491 /* Return the pseudo register name corresponding to register regnum. */
2494 aarch64_pseudo_register_name (struct gdbarch
*gdbarch
, int regnum
)
2496 aarch64_gdbarch_tdep
*tdep
= (aarch64_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
2498 static const char *const q_name
[] =
2500 "q0", "q1", "q2", "q3",
2501 "q4", "q5", "q6", "q7",
2502 "q8", "q9", "q10", "q11",
2503 "q12", "q13", "q14", "q15",
2504 "q16", "q17", "q18", "q19",
2505 "q20", "q21", "q22", "q23",
2506 "q24", "q25", "q26", "q27",
2507 "q28", "q29", "q30", "q31",
2510 static const char *const d_name
[] =
2512 "d0", "d1", "d2", "d3",
2513 "d4", "d5", "d6", "d7",
2514 "d8", "d9", "d10", "d11",
2515 "d12", "d13", "d14", "d15",
2516 "d16", "d17", "d18", "d19",
2517 "d20", "d21", "d22", "d23",
2518 "d24", "d25", "d26", "d27",
2519 "d28", "d29", "d30", "d31",
2522 static const char *const s_name
[] =
2524 "s0", "s1", "s2", "s3",
2525 "s4", "s5", "s6", "s7",
2526 "s8", "s9", "s10", "s11",
2527 "s12", "s13", "s14", "s15",
2528 "s16", "s17", "s18", "s19",
2529 "s20", "s21", "s22", "s23",
2530 "s24", "s25", "s26", "s27",
2531 "s28", "s29", "s30", "s31",
2534 static const char *const h_name
[] =
2536 "h0", "h1", "h2", "h3",
2537 "h4", "h5", "h6", "h7",
2538 "h8", "h9", "h10", "h11",
2539 "h12", "h13", "h14", "h15",
2540 "h16", "h17", "h18", "h19",
2541 "h20", "h21", "h22", "h23",
2542 "h24", "h25", "h26", "h27",
2543 "h28", "h29", "h30", "h31",
2546 static const char *const b_name
[] =
2548 "b0", "b1", "b2", "b3",
2549 "b4", "b5", "b6", "b7",
2550 "b8", "b9", "b10", "b11",
2551 "b12", "b13", "b14", "b15",
2552 "b16", "b17", "b18", "b19",
2553 "b20", "b21", "b22", "b23",
2554 "b24", "b25", "b26", "b27",
2555 "b28", "b29", "b30", "b31",
2558 int p_regnum
= regnum
- gdbarch_num_regs (gdbarch
);
2560 if (p_regnum
>= AARCH64_Q0_REGNUM
&& p_regnum
< AARCH64_Q0_REGNUM
+ 32)
2561 return q_name
[p_regnum
- AARCH64_Q0_REGNUM
];
2563 if (p_regnum
>= AARCH64_D0_REGNUM
&& p_regnum
< AARCH64_D0_REGNUM
+ 32)
2564 return d_name
[p_regnum
- AARCH64_D0_REGNUM
];
2566 if (p_regnum
>= AARCH64_S0_REGNUM
&& p_regnum
< AARCH64_S0_REGNUM
+ 32)
2567 return s_name
[p_regnum
- AARCH64_S0_REGNUM
];
2569 if (p_regnum
>= AARCH64_H0_REGNUM
&& p_regnum
< AARCH64_H0_REGNUM
+ 32)
2570 return h_name
[p_regnum
- AARCH64_H0_REGNUM
];
2572 if (p_regnum
>= AARCH64_B0_REGNUM
&& p_regnum
< AARCH64_B0_REGNUM
+ 32)
2573 return b_name
[p_regnum
- AARCH64_B0_REGNUM
];
2575 if (tdep
->has_sve ())
2577 static const char *const sve_v_name
[] =
2579 "v0", "v1", "v2", "v3",
2580 "v4", "v5", "v6", "v7",
2581 "v8", "v9", "v10", "v11",
2582 "v12", "v13", "v14", "v15",
2583 "v16", "v17", "v18", "v19",
2584 "v20", "v21", "v22", "v23",
2585 "v24", "v25", "v26", "v27",
2586 "v28", "v29", "v30", "v31",
2589 if (p_regnum
>= AARCH64_SVE_V0_REGNUM
2590 && p_regnum
< AARCH64_SVE_V0_REGNUM
+ AARCH64_V_REGS_NUM
)
2591 return sve_v_name
[p_regnum
- AARCH64_SVE_V0_REGNUM
];
2594 /* RA_STATE is used for unwinding only. Do not assign it a name - this
2595 prevents it from being read by methods such as
2596 mi_cmd_trace_frame_collected. */
2597 if (tdep
->has_pauth () && regnum
== tdep
->pauth_ra_state_regnum
)
2600 internal_error (__FILE__
, __LINE__
,
2601 _("aarch64_pseudo_register_name: bad register number %d"),
2605 /* Implement the "pseudo_register_type" tdesc_arch_data method. */
2607 static struct type
*
2608 aarch64_pseudo_register_type (struct gdbarch
*gdbarch
, int regnum
)
2610 aarch64_gdbarch_tdep
*tdep
= (aarch64_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
2612 int p_regnum
= regnum
- gdbarch_num_regs (gdbarch
);
2614 if (p_regnum
>= AARCH64_Q0_REGNUM
&& p_regnum
< AARCH64_Q0_REGNUM
+ 32)
2615 return aarch64_vnq_type (gdbarch
);
2617 if (p_regnum
>= AARCH64_D0_REGNUM
&& p_regnum
< AARCH64_D0_REGNUM
+ 32)
2618 return aarch64_vnd_type (gdbarch
);
2620 if (p_regnum
>= AARCH64_S0_REGNUM
&& p_regnum
< AARCH64_S0_REGNUM
+ 32)
2621 return aarch64_vns_type (gdbarch
);
2623 if (p_regnum
>= AARCH64_H0_REGNUM
&& p_regnum
< AARCH64_H0_REGNUM
+ 32)
2624 return aarch64_vnh_type (gdbarch
);
2626 if (p_regnum
>= AARCH64_B0_REGNUM
&& p_regnum
< AARCH64_B0_REGNUM
+ 32)
2627 return aarch64_vnb_type (gdbarch
);
2629 if (tdep
->has_sve () && p_regnum
>= AARCH64_SVE_V0_REGNUM
2630 && p_regnum
< AARCH64_SVE_V0_REGNUM
+ AARCH64_V_REGS_NUM
)
2631 return aarch64_vnv_type (gdbarch
);
2633 if (tdep
->has_pauth () && regnum
== tdep
->pauth_ra_state_regnum
)
2634 return builtin_type (gdbarch
)->builtin_uint64
;
2636 internal_error (__FILE__
, __LINE__
,
2637 _("aarch64_pseudo_register_type: bad register number %d"),
2641 /* Implement the "pseudo_register_reggroup_p" tdesc_arch_data method. */
2644 aarch64_pseudo_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
2645 struct reggroup
*group
)
2647 aarch64_gdbarch_tdep
*tdep
= (aarch64_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
2649 int p_regnum
= regnum
- gdbarch_num_regs (gdbarch
);
2651 if (p_regnum
>= AARCH64_Q0_REGNUM
&& p_regnum
< AARCH64_Q0_REGNUM
+ 32)
2652 return group
== all_reggroup
|| group
== vector_reggroup
;
2653 else if (p_regnum
>= AARCH64_D0_REGNUM
&& p_regnum
< AARCH64_D0_REGNUM
+ 32)
2654 return (group
== all_reggroup
|| group
== vector_reggroup
2655 || group
== float_reggroup
);
2656 else if (p_regnum
>= AARCH64_S0_REGNUM
&& p_regnum
< AARCH64_S0_REGNUM
+ 32)
2657 return (group
== all_reggroup
|| group
== vector_reggroup
2658 || group
== float_reggroup
);
2659 else if (p_regnum
>= AARCH64_H0_REGNUM
&& p_regnum
< AARCH64_H0_REGNUM
+ 32)
2660 return group
== all_reggroup
|| group
== vector_reggroup
;
2661 else if (p_regnum
>= AARCH64_B0_REGNUM
&& p_regnum
< AARCH64_B0_REGNUM
+ 32)
2662 return group
== all_reggroup
|| group
== vector_reggroup
;
2663 else if (tdep
->has_sve () && p_regnum
>= AARCH64_SVE_V0_REGNUM
2664 && p_regnum
< AARCH64_SVE_V0_REGNUM
+ AARCH64_V_REGS_NUM
)
2665 return group
== all_reggroup
|| group
== vector_reggroup
;
2666 /* RA_STATE is used for unwinding only. Do not assign it to any groups. */
2667 if (tdep
->has_pauth () && regnum
== tdep
->pauth_ra_state_regnum
)
2670 return group
== all_reggroup
;
2673 /* Helper for aarch64_pseudo_read_value. */
2675 static struct value
*
2676 aarch64_pseudo_read_value_1 (struct gdbarch
*gdbarch
,
2677 readable_regcache
*regcache
, int regnum_offset
,
2678 int regsize
, struct value
*result_value
)
2680 unsigned v_regnum
= AARCH64_V0_REGNUM
+ regnum_offset
;
2682 /* Enough space for a full vector register. */
2683 gdb_byte reg_buf
[register_size (gdbarch
, AARCH64_V0_REGNUM
)];
2684 gdb_static_assert (AARCH64_V0_REGNUM
== AARCH64_SVE_Z0_REGNUM
);
2686 if (regcache
->raw_read (v_regnum
, reg_buf
) != REG_VALID
)
2687 mark_value_bytes_unavailable (result_value
, 0,
2688 TYPE_LENGTH (value_type (result_value
)));
2690 memcpy (value_contents_raw (result_value
).data (), reg_buf
, regsize
);
2692 return result_value
;
2695 /* Implement the "pseudo_register_read_value" gdbarch method. */
2697 static struct value
*
2698 aarch64_pseudo_read_value (struct gdbarch
*gdbarch
, readable_regcache
*regcache
,
2701 aarch64_gdbarch_tdep
*tdep
= (aarch64_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
2702 struct value
*result_value
= allocate_value (register_type (gdbarch
, regnum
));
2704 VALUE_LVAL (result_value
) = lval_register
;
2705 VALUE_REGNUM (result_value
) = regnum
;
2707 regnum
-= gdbarch_num_regs (gdbarch
);
2709 if (regnum
>= AARCH64_Q0_REGNUM
&& regnum
< AARCH64_Q0_REGNUM
+ 32)
2710 return aarch64_pseudo_read_value_1 (gdbarch
, regcache
,
2711 regnum
- AARCH64_Q0_REGNUM
,
2712 Q_REGISTER_SIZE
, result_value
);
2714 if (regnum
>= AARCH64_D0_REGNUM
&& regnum
< AARCH64_D0_REGNUM
+ 32)
2715 return aarch64_pseudo_read_value_1 (gdbarch
, regcache
,
2716 regnum
- AARCH64_D0_REGNUM
,
2717 D_REGISTER_SIZE
, result_value
);
2719 if (regnum
>= AARCH64_S0_REGNUM
&& regnum
< AARCH64_S0_REGNUM
+ 32)
2720 return aarch64_pseudo_read_value_1 (gdbarch
, regcache
,
2721 regnum
- AARCH64_S0_REGNUM
,
2722 S_REGISTER_SIZE
, result_value
);
2724 if (regnum
>= AARCH64_H0_REGNUM
&& regnum
< AARCH64_H0_REGNUM
+ 32)
2725 return aarch64_pseudo_read_value_1 (gdbarch
, regcache
,
2726 regnum
- AARCH64_H0_REGNUM
,
2727 H_REGISTER_SIZE
, result_value
);
2729 if (regnum
>= AARCH64_B0_REGNUM
&& regnum
< AARCH64_B0_REGNUM
+ 32)
2730 return aarch64_pseudo_read_value_1 (gdbarch
, regcache
,
2731 regnum
- AARCH64_B0_REGNUM
,
2732 B_REGISTER_SIZE
, result_value
);
2734 if (tdep
->has_sve () && regnum
>= AARCH64_SVE_V0_REGNUM
2735 && regnum
< AARCH64_SVE_V0_REGNUM
+ 32)
2736 return aarch64_pseudo_read_value_1 (gdbarch
, regcache
,
2737 regnum
- AARCH64_SVE_V0_REGNUM
,
2738 V_REGISTER_SIZE
, result_value
);
2740 gdb_assert_not_reached ("regnum out of bound");
2743 /* Helper for aarch64_pseudo_write. */
2746 aarch64_pseudo_write_1 (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2747 int regnum_offset
, int regsize
, const gdb_byte
*buf
)
2749 unsigned v_regnum
= AARCH64_V0_REGNUM
+ regnum_offset
;
2751 /* Enough space for a full vector register. */
2752 gdb_byte reg_buf
[register_size (gdbarch
, AARCH64_V0_REGNUM
)];
2753 gdb_static_assert (AARCH64_V0_REGNUM
== AARCH64_SVE_Z0_REGNUM
);
2755 /* Ensure the register buffer is zero, we want gdb writes of the
2756 various 'scalar' pseudo registers to behavior like architectural
2757 writes, register width bytes are written the remainder are set to
2759 memset (reg_buf
, 0, register_size (gdbarch
, AARCH64_V0_REGNUM
));
2761 memcpy (reg_buf
, buf
, regsize
);
2762 regcache
->raw_write (v_regnum
, reg_buf
);
2765 /* Implement the "pseudo_register_write" gdbarch method. */
2768 aarch64_pseudo_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2769 int regnum
, const gdb_byte
*buf
)
2771 aarch64_gdbarch_tdep
*tdep
= (aarch64_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
2772 regnum
-= gdbarch_num_regs (gdbarch
);
2774 if (regnum
>= AARCH64_Q0_REGNUM
&& regnum
< AARCH64_Q0_REGNUM
+ 32)
2775 return aarch64_pseudo_write_1 (gdbarch
, regcache
,
2776 regnum
- AARCH64_Q0_REGNUM
, Q_REGISTER_SIZE
,
2779 if (regnum
>= AARCH64_D0_REGNUM
&& regnum
< AARCH64_D0_REGNUM
+ 32)
2780 return aarch64_pseudo_write_1 (gdbarch
, regcache
,
2781 regnum
- AARCH64_D0_REGNUM
, D_REGISTER_SIZE
,
2784 if (regnum
>= AARCH64_S0_REGNUM
&& regnum
< AARCH64_S0_REGNUM
+ 32)
2785 return aarch64_pseudo_write_1 (gdbarch
, regcache
,
2786 regnum
- AARCH64_S0_REGNUM
, S_REGISTER_SIZE
,
2789 if (regnum
>= AARCH64_H0_REGNUM
&& regnum
< AARCH64_H0_REGNUM
+ 32)
2790 return aarch64_pseudo_write_1 (gdbarch
, regcache
,
2791 regnum
- AARCH64_H0_REGNUM
, H_REGISTER_SIZE
,
2794 if (regnum
>= AARCH64_B0_REGNUM
&& regnum
< AARCH64_B0_REGNUM
+ 32)
2795 return aarch64_pseudo_write_1 (gdbarch
, regcache
,
2796 regnum
- AARCH64_B0_REGNUM
, B_REGISTER_SIZE
,
2799 if (tdep
->has_sve () && regnum
>= AARCH64_SVE_V0_REGNUM
2800 && regnum
< AARCH64_SVE_V0_REGNUM
+ 32)
2801 return aarch64_pseudo_write_1 (gdbarch
, regcache
,
2802 regnum
- AARCH64_SVE_V0_REGNUM
,
2803 V_REGISTER_SIZE
, buf
);
2805 gdb_assert_not_reached ("regnum out of bound");
2808 /* Callback function for user_reg_add. */
2810 static struct value
*
2811 value_of_aarch64_user_reg (struct frame_info
*frame
, const void *baton
)
2813 const int *reg_p
= (const int *) baton
;
2815 return value_of_register (*reg_p
, frame
);
2819 /* Implement the "software_single_step" gdbarch method, needed to
2820 single step through atomic sequences on AArch64. */
2822 static std::vector
<CORE_ADDR
>
2823 aarch64_software_single_step (struct regcache
*regcache
)
2825 struct gdbarch
*gdbarch
= regcache
->arch ();
2826 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
2827 const int insn_size
= 4;
2828 const int atomic_sequence_length
= 16; /* Instruction sequence length. */
2829 CORE_ADDR pc
= regcache_read_pc (regcache
);
2830 CORE_ADDR breaks
[2] = { CORE_ADDR_MAX
, CORE_ADDR_MAX
};
2832 CORE_ADDR closing_insn
= 0;
2833 uint32_t insn
= read_memory_unsigned_integer (loc
, insn_size
,
2834 byte_order_for_code
);
2837 int bc_insn_count
= 0; /* Conditional branch instruction count. */
2838 int last_breakpoint
= 0; /* Defaults to 0 (no breakpoints placed). */
2841 if (aarch64_decode_insn (insn
, &inst
, 1, NULL
) != 0)
2844 /* Look for a Load Exclusive instruction which begins the sequence. */
2845 if (inst
.opcode
->iclass
!= ldstexcl
|| bit (insn
, 22) == 0)
2848 for (insn_count
= 0; insn_count
< atomic_sequence_length
; ++insn_count
)
2851 insn
= read_memory_unsigned_integer (loc
, insn_size
,
2852 byte_order_for_code
);
2854 if (aarch64_decode_insn (insn
, &inst
, 1, NULL
) != 0)
2856 /* Check if the instruction is a conditional branch. */
2857 if (inst
.opcode
->iclass
== condbranch
)
2859 gdb_assert (inst
.operands
[0].type
== AARCH64_OPND_ADDR_PCREL19
);
2861 if (bc_insn_count
>= 1)
2864 /* It is, so we'll try to set a breakpoint at the destination. */
2865 breaks
[1] = loc
+ inst
.operands
[0].imm
.value
;
2871 /* Look for the Store Exclusive which closes the atomic sequence. */
2872 if (inst
.opcode
->iclass
== ldstexcl
&& bit (insn
, 22) == 0)
2879 /* We didn't find a closing Store Exclusive instruction, fall back. */
2883 /* Insert breakpoint after the end of the atomic sequence. */
2884 breaks
[0] = loc
+ insn_size
;
2886 /* Check for duplicated breakpoints, and also check that the second
2887 breakpoint is not within the atomic sequence. */
2889 && (breaks
[1] == breaks
[0]
2890 || (breaks
[1] >= pc
&& breaks
[1] <= closing_insn
)))
2891 last_breakpoint
= 0;
2893 std::vector
<CORE_ADDR
> next_pcs
;
2895 /* Insert the breakpoint at the end of the sequence, and one at the
2896 destination of the conditional branch, if it exists. */
2897 for (index
= 0; index
<= last_breakpoint
; index
++)
2898 next_pcs
.push_back (breaks
[index
]);
2903 struct aarch64_displaced_step_copy_insn_closure
2904 : public displaced_step_copy_insn_closure
2906 /* It is true when condition instruction, such as B.CON, TBZ, etc,
2907 is being displaced stepping. */
2910 /* PC adjustment offset after displaced stepping. If 0, then we don't
2911 write the PC back, assuming the PC is already the right address. */
2912 int32_t pc_adjust
= 0;
2915 /* Data when visiting instructions for displaced stepping. */
2917 struct aarch64_displaced_step_data
2919 struct aarch64_insn_data base
;
2921 /* The address where the instruction will be executed at. */
2923 /* Buffer of instructions to be copied to NEW_ADDR to execute. */
2924 uint32_t insn_buf
[AARCH64_DISPLACED_MODIFIED_INSNS
];
2925 /* Number of instructions in INSN_BUF. */
2926 unsigned insn_count
;
2927 /* Registers when doing displaced stepping. */
2928 struct regcache
*regs
;
2930 aarch64_displaced_step_copy_insn_closure
*dsc
;
2933 /* Implementation of aarch64_insn_visitor method "b". */
2936 aarch64_displaced_step_b (const int is_bl
, const int32_t offset
,
2937 struct aarch64_insn_data
*data
)
2939 struct aarch64_displaced_step_data
*dsd
2940 = (struct aarch64_displaced_step_data
*) data
;
2941 int64_t new_offset
= data
->insn_addr
- dsd
->new_addr
+ offset
;
2943 if (can_encode_int32 (new_offset
, 28))
2945 /* Emit B rather than BL, because executing BL on a new address
2946 will get the wrong address into LR. In order to avoid this,
2947 we emit B, and update LR if the instruction is BL. */
2948 emit_b (dsd
->insn_buf
, 0, new_offset
);
2954 emit_nop (dsd
->insn_buf
);
2956 dsd
->dsc
->pc_adjust
= offset
;
2962 regcache_cooked_write_unsigned (dsd
->regs
, AARCH64_LR_REGNUM
,
2963 data
->insn_addr
+ 4);
2967 /* Implementation of aarch64_insn_visitor method "b_cond". */
2970 aarch64_displaced_step_b_cond (const unsigned cond
, const int32_t offset
,
2971 struct aarch64_insn_data
*data
)
2973 struct aarch64_displaced_step_data
*dsd
2974 = (struct aarch64_displaced_step_data
*) data
;
2976 /* GDB has to fix up PC after displaced step this instruction
2977 differently according to the condition is true or false. Instead
2978 of checking COND against conditional flags, we can use
2979 the following instructions, and GDB can tell how to fix up PC
2980 according to the PC value.
2982 B.COND TAKEN ; If cond is true, then jump to TAKEN.
2988 emit_bcond (dsd
->insn_buf
, cond
, 8);
2989 dsd
->dsc
->cond
= true;
2990 dsd
->dsc
->pc_adjust
= offset
;
2991 dsd
->insn_count
= 1;
2994 /* Dynamically allocate a new register. If we know the register
2995 statically, we should make it a global as above instead of using this
2998 static struct aarch64_register
2999 aarch64_register (unsigned num
, int is64
)
3001 return (struct aarch64_register
) { num
, is64
};
3004 /* Implementation of aarch64_insn_visitor method "cb". */
3007 aarch64_displaced_step_cb (const int32_t offset
, const int is_cbnz
,
3008 const unsigned rn
, int is64
,
3009 struct aarch64_insn_data
*data
)
3011 struct aarch64_displaced_step_data
*dsd
3012 = (struct aarch64_displaced_step_data
*) data
;
3014 /* The offset is out of range for a compare and branch
3015 instruction. We can use the following instructions instead:
3017 CBZ xn, TAKEN ; xn == 0, then jump to TAKEN.
3022 emit_cb (dsd
->insn_buf
, is_cbnz
, aarch64_register (rn
, is64
), 8);
3023 dsd
->insn_count
= 1;
3024 dsd
->dsc
->cond
= true;
3025 dsd
->dsc
->pc_adjust
= offset
;
3028 /* Implementation of aarch64_insn_visitor method "tb". */
3031 aarch64_displaced_step_tb (const int32_t offset
, int is_tbnz
,
3032 const unsigned rt
, unsigned bit
,
3033 struct aarch64_insn_data
*data
)
3035 struct aarch64_displaced_step_data
*dsd
3036 = (struct aarch64_displaced_step_data
*) data
;
3038 /* The offset is out of range for a test bit and branch
3039 instruction We can use the following instructions instead:
3041 TBZ xn, #bit, TAKEN ; xn[bit] == 0, then jump to TAKEN.
3047 emit_tb (dsd
->insn_buf
, is_tbnz
, bit
, aarch64_register (rt
, 1), 8);
3048 dsd
->insn_count
= 1;
3049 dsd
->dsc
->cond
= true;
3050 dsd
->dsc
->pc_adjust
= offset
;
3053 /* Implementation of aarch64_insn_visitor method "adr". */
3056 aarch64_displaced_step_adr (const int32_t offset
, const unsigned rd
,
3057 const int is_adrp
, struct aarch64_insn_data
*data
)
3059 struct aarch64_displaced_step_data
*dsd
3060 = (struct aarch64_displaced_step_data
*) data
;
3061 /* We know exactly the address the ADR{P,} instruction will compute.
3062 We can just write it to the destination register. */
3063 CORE_ADDR address
= data
->insn_addr
+ offset
;
3067 /* Clear the lower 12 bits of the offset to get the 4K page. */
3068 regcache_cooked_write_unsigned (dsd
->regs
, AARCH64_X0_REGNUM
+ rd
,
3072 regcache_cooked_write_unsigned (dsd
->regs
, AARCH64_X0_REGNUM
+ rd
,
3075 dsd
->dsc
->pc_adjust
= 4;
3076 emit_nop (dsd
->insn_buf
);
3077 dsd
->insn_count
= 1;
3080 /* Implementation of aarch64_insn_visitor method "ldr_literal". */
3083 aarch64_displaced_step_ldr_literal (const int32_t offset
, const int is_sw
,
3084 const unsigned rt
, const int is64
,
3085 struct aarch64_insn_data
*data
)
3087 struct aarch64_displaced_step_data
*dsd
3088 = (struct aarch64_displaced_step_data
*) data
;
3089 CORE_ADDR address
= data
->insn_addr
+ offset
;
3090 struct aarch64_memory_operand zero
= { MEMORY_OPERAND_OFFSET
, 0 };
3092 regcache_cooked_write_unsigned (dsd
->regs
, AARCH64_X0_REGNUM
+ rt
,
3096 dsd
->insn_count
= emit_ldrsw (dsd
->insn_buf
, aarch64_register (rt
, 1),
3097 aarch64_register (rt
, 1), zero
);
3099 dsd
->insn_count
= emit_ldr (dsd
->insn_buf
, aarch64_register (rt
, is64
),
3100 aarch64_register (rt
, 1), zero
);
3102 dsd
->dsc
->pc_adjust
= 4;
3105 /* Implementation of aarch64_insn_visitor method "others". */
3108 aarch64_displaced_step_others (const uint32_t insn
,
3109 struct aarch64_insn_data
*data
)
3111 struct aarch64_displaced_step_data
*dsd
3112 = (struct aarch64_displaced_step_data
*) data
;
3114 uint32_t masked_insn
= (insn
& CLEAR_Rn_MASK
);
3115 if (masked_insn
== BLR
)
3117 /* Emit a BR to the same register and then update LR to the original
3118 address (similar to aarch64_displaced_step_b). */
3119 aarch64_emit_insn (dsd
->insn_buf
, insn
& 0xffdfffff);
3120 regcache_cooked_write_unsigned (dsd
->regs
, AARCH64_LR_REGNUM
,
3121 data
->insn_addr
+ 4);
3124 aarch64_emit_insn (dsd
->insn_buf
, insn
);
3125 dsd
->insn_count
= 1;
3127 if (masked_insn
== RET
|| masked_insn
== BR
|| masked_insn
== BLR
)
3128 dsd
->dsc
->pc_adjust
= 0;
3130 dsd
->dsc
->pc_adjust
= 4;
3133 static const struct aarch64_insn_visitor visitor
=
3135 aarch64_displaced_step_b
,
3136 aarch64_displaced_step_b_cond
,
3137 aarch64_displaced_step_cb
,
3138 aarch64_displaced_step_tb
,
3139 aarch64_displaced_step_adr
,
3140 aarch64_displaced_step_ldr_literal
,
3141 aarch64_displaced_step_others
,
3144 /* Implement the "displaced_step_copy_insn" gdbarch method. */
3146 displaced_step_copy_insn_closure_up
3147 aarch64_displaced_step_copy_insn (struct gdbarch
*gdbarch
,
3148 CORE_ADDR from
, CORE_ADDR to
,
3149 struct regcache
*regs
)
3151 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
3152 uint32_t insn
= read_memory_unsigned_integer (from
, 4, byte_order_for_code
);
3153 struct aarch64_displaced_step_data dsd
;
3156 if (aarch64_decode_insn (insn
, &inst
, 1, NULL
) != 0)
3159 /* Look for a Load Exclusive instruction which begins the sequence. */
3160 if (inst
.opcode
->iclass
== ldstexcl
&& bit (insn
, 22))
3162 /* We can't displaced step atomic sequences. */
3166 std::unique_ptr
<aarch64_displaced_step_copy_insn_closure
> dsc
3167 (new aarch64_displaced_step_copy_insn_closure
);
3168 dsd
.base
.insn_addr
= from
;
3171 dsd
.dsc
= dsc
.get ();
3173 aarch64_relocate_instruction (insn
, &visitor
,
3174 (struct aarch64_insn_data
*) &dsd
);
3175 gdb_assert (dsd
.insn_count
<= AARCH64_DISPLACED_MODIFIED_INSNS
);
3177 if (dsd
.insn_count
!= 0)
3181 /* Instruction can be relocated to scratch pad. Copy
3182 relocated instruction(s) there. */
3183 for (i
= 0; i
< dsd
.insn_count
; i
++)
3185 displaced_debug_printf ("writing insn %.8x at %s",
3187 paddress (gdbarch
, to
+ i
* 4));
3189 write_memory_unsigned_integer (to
+ i
* 4, 4, byte_order_for_code
,
3190 (ULONGEST
) dsd
.insn_buf
[i
]);
3198 /* This is a work around for a problem with g++ 4.8. */
3199 return displaced_step_copy_insn_closure_up (dsc
.release ());
3202 /* Implement the "displaced_step_fixup" gdbarch method. */
3205 aarch64_displaced_step_fixup (struct gdbarch
*gdbarch
,
3206 struct displaced_step_copy_insn_closure
*dsc_
,
3207 CORE_ADDR from
, CORE_ADDR to
,
3208 struct regcache
*regs
)
3210 aarch64_displaced_step_copy_insn_closure
*dsc
3211 = (aarch64_displaced_step_copy_insn_closure
*) dsc_
;
3215 regcache_cooked_read_unsigned (regs
, AARCH64_PC_REGNUM
, &pc
);
3217 displaced_debug_printf ("PC after stepping: %s (was %s).",
3218 paddress (gdbarch
, pc
), paddress (gdbarch
, to
));
3222 displaced_debug_printf ("[Conditional] pc_adjust before: %d",
3227 /* Condition is true. */
3229 else if (pc
- to
== 4)
3231 /* Condition is false. */
3235 gdb_assert_not_reached ("Unexpected PC value after displaced stepping");
3237 displaced_debug_printf ("[Conditional] pc_adjust after: %d",
3241 displaced_debug_printf ("%s PC by %d",
3242 dsc
->pc_adjust
? "adjusting" : "not adjusting",
3245 if (dsc
->pc_adjust
!= 0)
3247 /* Make sure the previous instruction was executed (that is, the PC
3248 has changed). If the PC didn't change, then discard the adjustment
3249 offset. Otherwise we may skip an instruction before its execution
3253 displaced_debug_printf ("PC did not move. Discarding PC adjustment.");
3257 displaced_debug_printf ("fixup: set PC to %s:%d",
3258 paddress (gdbarch
, from
), dsc
->pc_adjust
);
3260 regcache_cooked_write_unsigned (regs
, AARCH64_PC_REGNUM
,
3261 from
+ dsc
->pc_adjust
);
3265 /* Implement the "displaced_step_hw_singlestep" gdbarch method. */
3268 aarch64_displaced_step_hw_singlestep (struct gdbarch
*gdbarch
)
3273 /* Get the correct target description for the given VQ value.
3274 If VQ is zero then it is assumed SVE is not supported.
3275 (It is not possible to set VQ to zero on an SVE system).
3277 MTE_P indicates the presence of the Memory Tagging Extension feature. */
3280 aarch64_read_description (uint64_t vq
, bool pauth_p
, bool mte_p
)
3282 if (vq
> AARCH64_MAX_SVE_VQ
)
3283 error (_("VQ is %" PRIu64
", maximum supported value is %d"), vq
,
3284 AARCH64_MAX_SVE_VQ
);
3286 struct target_desc
*tdesc
= tdesc_aarch64_list
[vq
][pauth_p
][mte_p
];
3290 tdesc
= aarch64_create_target_description (vq
, pauth_p
, mte_p
);
3291 tdesc_aarch64_list
[vq
][pauth_p
][mte_p
] = tdesc
;
3297 /* Return the VQ used when creating the target description TDESC. */
3300 aarch64_get_tdesc_vq (const struct target_desc
*tdesc
)
3302 const struct tdesc_feature
*feature_sve
;
3304 if (!tdesc_has_registers (tdesc
))
3307 feature_sve
= tdesc_find_feature (tdesc
, "org.gnu.gdb.aarch64.sve");
3309 if (feature_sve
== nullptr)
3312 uint64_t vl
= tdesc_register_bitsize (feature_sve
,
3313 aarch64_sve_register_names
[0]) / 8;
3314 return sve_vq_from_vl (vl
);
3317 /* Add all the expected register sets into GDBARCH. */
3320 aarch64_add_reggroups (struct gdbarch
*gdbarch
)
3322 reggroup_add (gdbarch
, general_reggroup
);
3323 reggroup_add (gdbarch
, float_reggroup
);
3324 reggroup_add (gdbarch
, system_reggroup
);
3325 reggroup_add (gdbarch
, vector_reggroup
);
3326 reggroup_add (gdbarch
, all_reggroup
);
3327 reggroup_add (gdbarch
, save_reggroup
);
3328 reggroup_add (gdbarch
, restore_reggroup
);
3331 /* Implement the "cannot_store_register" gdbarch method. */
3334 aarch64_cannot_store_register (struct gdbarch
*gdbarch
, int regnum
)
3336 aarch64_gdbarch_tdep
*tdep
= (aarch64_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
3338 if (!tdep
->has_pauth ())
3341 /* Pointer authentication registers are read-only. */
3342 return (regnum
== AARCH64_PAUTH_DMASK_REGNUM (tdep
->pauth_reg_base
)
3343 || regnum
== AARCH64_PAUTH_CMASK_REGNUM (tdep
->pauth_reg_base
));
3346 /* Initialize the current architecture based on INFO. If possible,
3347 re-use an architecture from ARCHES, which is a list of
3348 architectures already created during this debugging session.
3350 Called e.g. at program startup, when reading a core file, and when
3351 reading a binary file. */
3353 static struct gdbarch
*
3354 aarch64_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
3356 const struct tdesc_feature
*feature_core
, *feature_fpu
, *feature_sve
;
3357 const struct tdesc_feature
*feature_pauth
;
3358 bool valid_p
= true;
3359 int i
, num_regs
= 0, num_pseudo_regs
= 0;
3360 int first_pauth_regnum
= -1, pauth_ra_state_offset
= -1;
3361 int first_mte_regnum
= -1;
3363 /* Use the vector length passed via the target info. Here -1 is used for no
3364 SVE, and 0 is unset. If unset then use the vector length from the existing
3367 if (info
.id
== (int *) -1)
3369 else if (info
.id
!= 0)
3370 vq
= (uint64_t) info
.id
;
3372 vq
= aarch64_get_tdesc_vq (info
.target_desc
);
3374 if (vq
> AARCH64_MAX_SVE_VQ
)
3375 internal_error (__FILE__
, __LINE__
, _("VQ out of bounds: %s (max %d)"),
3376 pulongest (vq
), AARCH64_MAX_SVE_VQ
);
3378 /* If there is already a candidate, use it. */
3379 for (gdbarch_list
*best_arch
= gdbarch_list_lookup_by_info (arches
, &info
);
3380 best_arch
!= nullptr;
3381 best_arch
= gdbarch_list_lookup_by_info (best_arch
->next
, &info
))
3383 aarch64_gdbarch_tdep
*tdep
3384 = (aarch64_gdbarch_tdep
*) gdbarch_tdep (best_arch
->gdbarch
);
3385 if (tdep
&& tdep
->vq
== vq
)
3386 return best_arch
->gdbarch
;
3389 /* Ensure we always have a target descriptor, and that it is for the given VQ
3391 const struct target_desc
*tdesc
= info
.target_desc
;
3392 if (!tdesc_has_registers (tdesc
) || vq
!= aarch64_get_tdesc_vq (tdesc
))
3393 tdesc
= aarch64_read_description (vq
, false, false);
3396 feature_core
= tdesc_find_feature (tdesc
,"org.gnu.gdb.aarch64.core");
3397 feature_fpu
= tdesc_find_feature (tdesc
, "org.gnu.gdb.aarch64.fpu");
3398 feature_sve
= tdesc_find_feature (tdesc
, "org.gnu.gdb.aarch64.sve");
3399 feature_pauth
= tdesc_find_feature (tdesc
, "org.gnu.gdb.aarch64.pauth");
3400 const struct tdesc_feature
*feature_mte
3401 = tdesc_find_feature (tdesc
, "org.gnu.gdb.aarch64.mte");
3403 if (feature_core
== nullptr)
3406 tdesc_arch_data_up tdesc_data
= tdesc_data_alloc ();
3408 /* Validate the description provides the mandatory core R registers
3409 and allocate their numbers. */
3410 for (i
= 0; i
< ARRAY_SIZE (aarch64_r_register_names
); i
++)
3411 valid_p
&= tdesc_numbered_register (feature_core
, tdesc_data
.get (),
3412 AARCH64_X0_REGNUM
+ i
,
3413 aarch64_r_register_names
[i
]);
3415 num_regs
= AARCH64_X0_REGNUM
+ i
;
3417 /* Add the V registers. */
3418 if (feature_fpu
!= nullptr)
3420 if (feature_sve
!= nullptr)
3421 error (_("Program contains both fpu and SVE features."));
3423 /* Validate the description provides the mandatory V registers
3424 and allocate their numbers. */
3425 for (i
= 0; i
< ARRAY_SIZE (aarch64_v_register_names
); i
++)
3426 valid_p
&= tdesc_numbered_register (feature_fpu
, tdesc_data
.get (),
3427 AARCH64_V0_REGNUM
+ i
,
3428 aarch64_v_register_names
[i
]);
3430 num_regs
= AARCH64_V0_REGNUM
+ i
;
3433 /* Add the SVE registers. */
3434 if (feature_sve
!= nullptr)
3436 /* Validate the description provides the mandatory SVE registers
3437 and allocate their numbers. */
3438 for (i
= 0; i
< ARRAY_SIZE (aarch64_sve_register_names
); i
++)
3439 valid_p
&= tdesc_numbered_register (feature_sve
, tdesc_data
.get (),
3440 AARCH64_SVE_Z0_REGNUM
+ i
,
3441 aarch64_sve_register_names
[i
]);
3443 num_regs
= AARCH64_SVE_Z0_REGNUM
+ i
;
3444 num_pseudo_regs
+= 32; /* add the Vn register pseudos. */
3447 if (feature_fpu
!= nullptr || feature_sve
!= nullptr)
3449 num_pseudo_regs
+= 32; /* add the Qn scalar register pseudos */
3450 num_pseudo_regs
+= 32; /* add the Dn scalar register pseudos */
3451 num_pseudo_regs
+= 32; /* add the Sn scalar register pseudos */
3452 num_pseudo_regs
+= 32; /* add the Hn scalar register pseudos */
3453 num_pseudo_regs
+= 32; /* add the Bn scalar register pseudos */
3456 /* Add the pauth registers. */
3457 if (feature_pauth
!= NULL
)
3459 first_pauth_regnum
= num_regs
;
3460 pauth_ra_state_offset
= num_pseudo_regs
;
3461 /* Validate the descriptor provides the mandatory PAUTH registers and
3462 allocate their numbers. */
3463 for (i
= 0; i
< ARRAY_SIZE (aarch64_pauth_register_names
); i
++)
3464 valid_p
&= tdesc_numbered_register (feature_pauth
, tdesc_data
.get (),
3465 first_pauth_regnum
+ i
,
3466 aarch64_pauth_register_names
[i
]);
3469 num_pseudo_regs
+= 1; /* Count RA_STATE pseudo register. */
3472 /* Add the MTE registers. */
3473 if (feature_mte
!= NULL
)
3475 first_mte_regnum
= num_regs
;
3476 /* Validate the descriptor provides the mandatory MTE registers and
3477 allocate their numbers. */
3478 for (i
= 0; i
< ARRAY_SIZE (aarch64_mte_register_names
); i
++)
3479 valid_p
&= tdesc_numbered_register (feature_mte
, tdesc_data
.get (),
3480 first_mte_regnum
+ i
,
3481 aarch64_mte_register_names
[i
]);
3489 /* AArch64 code is always little-endian. */
3490 info
.byte_order_for_code
= BFD_ENDIAN_LITTLE
;
3492 aarch64_gdbarch_tdep
*tdep
= new aarch64_gdbarch_tdep
;
3493 struct gdbarch
*gdbarch
= gdbarch_alloc (&info
, tdep
);
3495 /* This should be low enough for everything. */
3496 tdep
->lowest_pc
= 0x20;
3497 tdep
->jb_pc
= -1; /* Longjump support not enabled by default. */
3498 tdep
->jb_elt_size
= 8;
3500 tdep
->pauth_reg_base
= first_pauth_regnum
;
3501 tdep
->pauth_ra_state_regnum
= (feature_pauth
== NULL
) ? -1
3502 : pauth_ra_state_offset
+ num_regs
;
3503 tdep
->mte_reg_base
= first_mte_regnum
;
3505 set_gdbarch_push_dummy_call (gdbarch
, aarch64_push_dummy_call
);
3506 set_gdbarch_frame_align (gdbarch
, aarch64_frame_align
);
3508 /* Advance PC across function entry code. */
3509 set_gdbarch_skip_prologue (gdbarch
, aarch64_skip_prologue
);
3511 /* The stack grows downward. */
3512 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
3514 /* Breakpoint manipulation. */
3515 set_gdbarch_breakpoint_kind_from_pc (gdbarch
,
3516 aarch64_breakpoint::kind_from_pc
);
3517 set_gdbarch_sw_breakpoint_from_kind (gdbarch
,
3518 aarch64_breakpoint::bp_from_kind
);
3519 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
3520 set_gdbarch_software_single_step (gdbarch
, aarch64_software_single_step
);
3522 /* Information about registers, etc. */
3523 set_gdbarch_sp_regnum (gdbarch
, AARCH64_SP_REGNUM
);
3524 set_gdbarch_pc_regnum (gdbarch
, AARCH64_PC_REGNUM
);
3525 set_gdbarch_num_regs (gdbarch
, num_regs
);
3527 set_gdbarch_num_pseudo_regs (gdbarch
, num_pseudo_regs
);
3528 set_gdbarch_pseudo_register_read_value (gdbarch
, aarch64_pseudo_read_value
);
3529 set_gdbarch_pseudo_register_write (gdbarch
, aarch64_pseudo_write
);
3530 set_tdesc_pseudo_register_name (gdbarch
, aarch64_pseudo_register_name
);
3531 set_tdesc_pseudo_register_type (gdbarch
, aarch64_pseudo_register_type
);
3532 set_tdesc_pseudo_register_reggroup_p (gdbarch
,
3533 aarch64_pseudo_register_reggroup_p
);
3534 set_gdbarch_cannot_store_register (gdbarch
, aarch64_cannot_store_register
);
3537 set_gdbarch_short_bit (gdbarch
, 16);
3538 set_gdbarch_int_bit (gdbarch
, 32);
3539 set_gdbarch_float_bit (gdbarch
, 32);
3540 set_gdbarch_double_bit (gdbarch
, 64);
3541 set_gdbarch_long_double_bit (gdbarch
, 128);
3542 set_gdbarch_long_bit (gdbarch
, 64);
3543 set_gdbarch_long_long_bit (gdbarch
, 64);
3544 set_gdbarch_ptr_bit (gdbarch
, 64);
3545 set_gdbarch_char_signed (gdbarch
, 0);
3546 set_gdbarch_wchar_signed (gdbarch
, 0);
3547 set_gdbarch_float_format (gdbarch
, floatformats_ieee_single
);
3548 set_gdbarch_double_format (gdbarch
, floatformats_ieee_double
);
3549 set_gdbarch_long_double_format (gdbarch
, floatformats_ia64_quad
);
3550 set_gdbarch_type_align (gdbarch
, aarch64_type_align
);
3552 /* Internal <-> external register number maps. */
3553 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, aarch64_dwarf_reg_to_regnum
);
3555 /* Returning results. */
3556 set_gdbarch_return_value (gdbarch
, aarch64_return_value
);
3559 set_gdbarch_print_insn (gdbarch
, aarch64_gdb_print_insn
);
3561 /* Virtual tables. */
3562 set_gdbarch_vbit_in_delta (gdbarch
, 1);
3564 /* Register architecture. */
3565 aarch64_add_reggroups (gdbarch
);
3567 /* Hook in the ABI-specific overrides, if they have been registered. */
3568 info
.target_desc
= tdesc
;
3569 info
.tdesc_data
= tdesc_data
.get ();
3570 gdbarch_init_osabi (info
, gdbarch
);
3572 dwarf2_frame_set_init_reg (gdbarch
, aarch64_dwarf2_frame_init_reg
);
3573 /* Register DWARF CFA vendor handler. */
3574 set_gdbarch_execute_dwarf_cfa_vendor_op (gdbarch
,
3575 aarch64_execute_dwarf_cfa_vendor_op
);
3577 /* Permanent/Program breakpoint handling. */
3578 set_gdbarch_program_breakpoint_here_p (gdbarch
,
3579 aarch64_program_breakpoint_here_p
);
3581 /* Add some default predicates. */
3582 frame_unwind_append_unwinder (gdbarch
, &aarch64_stub_unwind
);
3583 dwarf2_append_unwinders (gdbarch
);
3584 frame_unwind_append_unwinder (gdbarch
, &aarch64_prologue_unwind
);
3586 frame_base_set_default (gdbarch
, &aarch64_normal_base
);
3588 /* Now we have tuned the configuration, set a few final things,
3589 based on what the OS ABI has told us. */
3591 if (tdep
->jb_pc
>= 0)
3592 set_gdbarch_get_longjmp_target (gdbarch
, aarch64_get_longjmp_target
);
3594 set_gdbarch_gen_return_address (gdbarch
, aarch64_gen_return_address
);
3596 set_gdbarch_get_pc_address_flags (gdbarch
, aarch64_get_pc_address_flags
);
3598 tdesc_use_registers (gdbarch
, tdesc
, std::move (tdesc_data
));
3600 /* Add standard register aliases. */
3601 for (i
= 0; i
< ARRAY_SIZE (aarch64_register_aliases
); i
++)
3602 user_reg_add (gdbarch
, aarch64_register_aliases
[i
].name
,
3603 value_of_aarch64_user_reg
,
3604 &aarch64_register_aliases
[i
].regnum
);
3606 register_aarch64_ravenscar_ops (gdbarch
);
3612 aarch64_dump_tdep (struct gdbarch
*gdbarch
, struct ui_file
*file
)
3614 aarch64_gdbarch_tdep
*tdep
= (aarch64_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
3619 fprintf_unfiltered (file
, _("aarch64_dump_tdep: Lowest pc = 0x%s"),
3620 paddress (gdbarch
, tdep
->lowest_pc
));
3626 static void aarch64_process_record_test (void);
3630 void _initialize_aarch64_tdep ();
3632 _initialize_aarch64_tdep ()
3634 gdbarch_register (bfd_arch_aarch64
, aarch64_gdbarch_init
,
3637 /* Debug this file's internals. */
3638 add_setshow_boolean_cmd ("aarch64", class_maintenance
, &aarch64_debug
, _("\
3639 Set AArch64 debugging."), _("\
3640 Show AArch64 debugging."), _("\
3641 When on, AArch64 specific debugging is enabled."),
3644 &setdebuglist
, &showdebuglist
);
3647 selftests::register_test ("aarch64-analyze-prologue",
3648 selftests::aarch64_analyze_prologue_test
);
3649 selftests::register_test ("aarch64-process-record",
3650 selftests::aarch64_process_record_test
);
3654 /* AArch64 process record-replay related structures, defines etc. */
3656 #define REG_ALLOC(REGS, LENGTH, RECORD_BUF) \
3659 unsigned int reg_len = LENGTH; \
3662 REGS = XNEWVEC (uint32_t, reg_len); \
3663 memcpy(®S[0], &RECORD_BUF[0], sizeof(uint32_t)*LENGTH); \
3668 #define MEM_ALLOC(MEMS, LENGTH, RECORD_BUF) \
3671 unsigned int mem_len = LENGTH; \
3674 MEMS = XNEWVEC (struct aarch64_mem_r, mem_len); \
3675 memcpy(&MEMS->len, &RECORD_BUF[0], \
3676 sizeof(struct aarch64_mem_r) * LENGTH); \
3681 /* AArch64 record/replay structures and enumerations. */
3683 struct aarch64_mem_r
3685 uint64_t len
; /* Record length. */
3686 uint64_t addr
; /* Memory address. */
3689 enum aarch64_record_result
3691 AARCH64_RECORD_SUCCESS
,
3692 AARCH64_RECORD_UNSUPPORTED
,
3693 AARCH64_RECORD_UNKNOWN
3696 typedef struct insn_decode_record_t
3698 struct gdbarch
*gdbarch
;
3699 struct regcache
*regcache
;
3700 CORE_ADDR this_addr
; /* Address of insn to be recorded. */
3701 uint32_t aarch64_insn
; /* Insn to be recorded. */
3702 uint32_t mem_rec_count
; /* Count of memory records. */
3703 uint32_t reg_rec_count
; /* Count of register records. */
3704 uint32_t *aarch64_regs
; /* Registers to be recorded. */
3705 struct aarch64_mem_r
*aarch64_mems
; /* Memory locations to be recorded. */
3706 } insn_decode_record
;
3708 /* Record handler for data processing - register instructions. */
3711 aarch64_record_data_proc_reg (insn_decode_record
*aarch64_insn_r
)
3713 uint8_t reg_rd
, insn_bits24_27
, insn_bits21_23
;
3714 uint32_t record_buf
[4];
3716 reg_rd
= bits (aarch64_insn_r
->aarch64_insn
, 0, 4);
3717 insn_bits24_27
= bits (aarch64_insn_r
->aarch64_insn
, 24, 27);
3718 insn_bits21_23
= bits (aarch64_insn_r
->aarch64_insn
, 21, 23);
3720 if (!bit (aarch64_insn_r
->aarch64_insn
, 28))
3724 /* Logical (shifted register). */
3725 if (insn_bits24_27
== 0x0a)
3726 setflags
= (bits (aarch64_insn_r
->aarch64_insn
, 29, 30) == 0x03);
3728 else if (insn_bits24_27
== 0x0b)
3729 setflags
= bit (aarch64_insn_r
->aarch64_insn
, 29);
3731 return AARCH64_RECORD_UNKNOWN
;
3733 record_buf
[0] = reg_rd
;
3734 aarch64_insn_r
->reg_rec_count
= 1;
3736 record_buf
[aarch64_insn_r
->reg_rec_count
++] = AARCH64_CPSR_REGNUM
;
3740 if (insn_bits24_27
== 0x0b)
3742 /* Data-processing (3 source). */
3743 record_buf
[0] = reg_rd
;
3744 aarch64_insn_r
->reg_rec_count
= 1;
3746 else if (insn_bits24_27
== 0x0a)
3748 if (insn_bits21_23
== 0x00)
3750 /* Add/subtract (with carry). */
3751 record_buf
[0] = reg_rd
;
3752 aarch64_insn_r
->reg_rec_count
= 1;
3753 if (bit (aarch64_insn_r
->aarch64_insn
, 29))
3755 record_buf
[1] = AARCH64_CPSR_REGNUM
;
3756 aarch64_insn_r
->reg_rec_count
= 2;
3759 else if (insn_bits21_23
== 0x02)
3761 /* Conditional compare (register) and conditional compare
3762 (immediate) instructions. */
3763 record_buf
[0] = AARCH64_CPSR_REGNUM
;
3764 aarch64_insn_r
->reg_rec_count
= 1;
3766 else if (insn_bits21_23
== 0x04 || insn_bits21_23
== 0x06)
3768 /* Conditional select. */
3769 /* Data-processing (2 source). */
3770 /* Data-processing (1 source). */
3771 record_buf
[0] = reg_rd
;
3772 aarch64_insn_r
->reg_rec_count
= 1;
3775 return AARCH64_RECORD_UNKNOWN
;
3779 REG_ALLOC (aarch64_insn_r
->aarch64_regs
, aarch64_insn_r
->reg_rec_count
,
3781 return AARCH64_RECORD_SUCCESS
;
3784 /* Record handler for data processing - immediate instructions. */
3787 aarch64_record_data_proc_imm (insn_decode_record
*aarch64_insn_r
)
3789 uint8_t reg_rd
, insn_bit23
, insn_bits24_27
, setflags
;
3790 uint32_t record_buf
[4];
3792 reg_rd
= bits (aarch64_insn_r
->aarch64_insn
, 0, 4);
3793 insn_bit23
= bit (aarch64_insn_r
->aarch64_insn
, 23);
3794 insn_bits24_27
= bits (aarch64_insn_r
->aarch64_insn
, 24, 27);
3796 if (insn_bits24_27
== 0x00 /* PC rel addressing. */
3797 || insn_bits24_27
== 0x03 /* Bitfield and Extract. */
3798 || (insn_bits24_27
== 0x02 && insn_bit23
)) /* Move wide (immediate). */
3800 record_buf
[0] = reg_rd
;
3801 aarch64_insn_r
->reg_rec_count
= 1;
3803 else if (insn_bits24_27
== 0x01)
3805 /* Add/Subtract (immediate). */
3806 setflags
= bit (aarch64_insn_r
->aarch64_insn
, 29);
3807 record_buf
[0] = reg_rd
;
3808 aarch64_insn_r
->reg_rec_count
= 1;
3810 record_buf
[aarch64_insn_r
->reg_rec_count
++] = AARCH64_CPSR_REGNUM
;
3812 else if (insn_bits24_27
== 0x02 && !insn_bit23
)
3814 /* Logical (immediate). */
3815 setflags
= bits (aarch64_insn_r
->aarch64_insn
, 29, 30) == 0x03;
3816 record_buf
[0] = reg_rd
;
3817 aarch64_insn_r
->reg_rec_count
= 1;
3819 record_buf
[aarch64_insn_r
->reg_rec_count
++] = AARCH64_CPSR_REGNUM
;
3822 return AARCH64_RECORD_UNKNOWN
;
3824 REG_ALLOC (aarch64_insn_r
->aarch64_regs
, aarch64_insn_r
->reg_rec_count
,
3826 return AARCH64_RECORD_SUCCESS
;
3829 /* Record handler for branch, exception generation and system instructions. */
3832 aarch64_record_branch_except_sys (insn_decode_record
*aarch64_insn_r
)
3835 aarch64_gdbarch_tdep
*tdep
3836 = (aarch64_gdbarch_tdep
*) gdbarch_tdep (aarch64_insn_r
->gdbarch
);
3837 uint8_t insn_bits24_27
, insn_bits28_31
, insn_bits22_23
;
3838 uint32_t record_buf
[4];
3840 insn_bits24_27
= bits (aarch64_insn_r
->aarch64_insn
, 24, 27);
3841 insn_bits28_31
= bits (aarch64_insn_r
->aarch64_insn
, 28, 31);
3842 insn_bits22_23
= bits (aarch64_insn_r
->aarch64_insn
, 22, 23);
3844 if (insn_bits28_31
== 0x0d)
3846 /* Exception generation instructions. */
3847 if (insn_bits24_27
== 0x04)
3849 if (!bits (aarch64_insn_r
->aarch64_insn
, 2, 4)
3850 && !bits (aarch64_insn_r
->aarch64_insn
, 21, 23)
3851 && bits (aarch64_insn_r
->aarch64_insn
, 0, 1) == 0x01)
3853 ULONGEST svc_number
;
3855 regcache_raw_read_unsigned (aarch64_insn_r
->regcache
, 8,
3857 return tdep
->aarch64_syscall_record (aarch64_insn_r
->regcache
,
3861 return AARCH64_RECORD_UNSUPPORTED
;
3863 /* System instructions. */
3864 else if (insn_bits24_27
== 0x05 && insn_bits22_23
== 0x00)
3866 uint32_t reg_rt
, reg_crn
;
3868 reg_rt
= bits (aarch64_insn_r
->aarch64_insn
, 0, 4);
3869 reg_crn
= bits (aarch64_insn_r
->aarch64_insn
, 12, 15);
3871 /* Record rt in case of sysl and mrs instructions. */
3872 if (bit (aarch64_insn_r
->aarch64_insn
, 21))
3874 record_buf
[0] = reg_rt
;
3875 aarch64_insn_r
->reg_rec_count
= 1;
3877 /* Record cpsr for hint and msr(immediate) instructions. */
3878 else if (reg_crn
== 0x02 || reg_crn
== 0x04)
3880 record_buf
[0] = AARCH64_CPSR_REGNUM
;
3881 aarch64_insn_r
->reg_rec_count
= 1;
3884 /* Unconditional branch (register). */
3885 else if((insn_bits24_27
& 0x0e) == 0x06)
3887 record_buf
[aarch64_insn_r
->reg_rec_count
++] = AARCH64_PC_REGNUM
;
3888 if (bits (aarch64_insn_r
->aarch64_insn
, 21, 22) == 0x01)
3889 record_buf
[aarch64_insn_r
->reg_rec_count
++] = AARCH64_LR_REGNUM
;
3892 return AARCH64_RECORD_UNKNOWN
;
3894 /* Unconditional branch (immediate). */
3895 else if ((insn_bits28_31
& 0x07) == 0x01 && (insn_bits24_27
& 0x0c) == 0x04)
3897 record_buf
[aarch64_insn_r
->reg_rec_count
++] = AARCH64_PC_REGNUM
;
3898 if (bit (aarch64_insn_r
->aarch64_insn
, 31))
3899 record_buf
[aarch64_insn_r
->reg_rec_count
++] = AARCH64_LR_REGNUM
;
3902 /* Compare & branch (immediate), Test & branch (immediate) and
3903 Conditional branch (immediate). */
3904 record_buf
[aarch64_insn_r
->reg_rec_count
++] = AARCH64_PC_REGNUM
;
3906 REG_ALLOC (aarch64_insn_r
->aarch64_regs
, aarch64_insn_r
->reg_rec_count
,
3908 return AARCH64_RECORD_SUCCESS
;
3911 /* Record handler for advanced SIMD load and store instructions. */
3914 aarch64_record_asimd_load_store (insn_decode_record
*aarch64_insn_r
)
3917 uint64_t addr_offset
= 0;
3918 uint32_t record_buf
[24];
3919 uint64_t record_buf_mem
[24];
3920 uint32_t reg_rn
, reg_rt
;
3921 uint32_t reg_index
= 0, mem_index
= 0;
3922 uint8_t opcode_bits
, size_bits
;
3924 reg_rt
= bits (aarch64_insn_r
->aarch64_insn
, 0, 4);
3925 reg_rn
= bits (aarch64_insn_r
->aarch64_insn
, 5, 9);
3926 size_bits
= bits (aarch64_insn_r
->aarch64_insn
, 10, 11);
3927 opcode_bits
= bits (aarch64_insn_r
->aarch64_insn
, 12, 15);
3928 regcache_raw_read_unsigned (aarch64_insn_r
->regcache
, reg_rn
, &address
);
3931 debug_printf ("Process record: Advanced SIMD load/store\n");
3933 /* Load/store single structure. */
3934 if (bit (aarch64_insn_r
->aarch64_insn
, 24))
3936 uint8_t sindex
, scale
, selem
, esize
, replicate
= 0;
3937 scale
= opcode_bits
>> 2;
3938 selem
= ((opcode_bits
& 0x02) |
3939 bit (aarch64_insn_r
->aarch64_insn
, 21)) + 1;
3943 if (size_bits
& 0x01)
3944 return AARCH64_RECORD_UNKNOWN
;
3947 if ((size_bits
>> 1) & 0x01)
3948 return AARCH64_RECORD_UNKNOWN
;
3949 if (size_bits
& 0x01)
3951 if (!((opcode_bits
>> 1) & 0x01))
3954 return AARCH64_RECORD_UNKNOWN
;
3958 if (bit (aarch64_insn_r
->aarch64_insn
, 22) && !(opcode_bits
& 0x01))
3965 return AARCH64_RECORD_UNKNOWN
;
3971 for (sindex
= 0; sindex
< selem
; sindex
++)
3973 record_buf
[reg_index
++] = reg_rt
+ AARCH64_V0_REGNUM
;
3974 reg_rt
= (reg_rt
+ 1) % 32;
3978 for (sindex
= 0; sindex
< selem
; sindex
++)
3980 if (bit (aarch64_insn_r
->aarch64_insn
, 22))
3981 record_buf
[reg_index
++] = reg_rt
+ AARCH64_V0_REGNUM
;
3984 record_buf_mem
[mem_index
++] = esize
/ 8;
3985 record_buf_mem
[mem_index
++] = address
+ addr_offset
;
3987 addr_offset
= addr_offset
+ (esize
/ 8);
3988 reg_rt
= (reg_rt
+ 1) % 32;
3992 /* Load/store multiple structure. */
3995 uint8_t selem
, esize
, rpt
, elements
;
3996 uint8_t eindex
, rindex
;
3998 esize
= 8 << size_bits
;
3999 if (bit (aarch64_insn_r
->aarch64_insn
, 30))
4000 elements
= 128 / esize
;
4002 elements
= 64 / esize
;
4004 switch (opcode_bits
)
4006 /*LD/ST4 (4 Registers). */
4011 /*LD/ST1 (4 Registers). */
4016 /*LD/ST3 (3 Registers). */
4021 /*LD/ST1 (3 Registers). */
4026 /*LD/ST1 (1 Register). */
4031 /*LD/ST2 (2 Registers). */
4036 /*LD/ST1 (2 Registers). */
4042 return AARCH64_RECORD_UNSUPPORTED
;
4045 for (rindex
= 0; rindex
< rpt
; rindex
++)
4046 for (eindex
= 0; eindex
< elements
; eindex
++)
4048 uint8_t reg_tt
, sindex
;
4049 reg_tt
= (reg_rt
+ rindex
) % 32;
4050 for (sindex
= 0; sindex
< selem
; sindex
++)
4052 if (bit (aarch64_insn_r
->aarch64_insn
, 22))
4053 record_buf
[reg_index
++] = reg_tt
+ AARCH64_V0_REGNUM
;
4056 record_buf_mem
[mem_index
++] = esize
/ 8;
4057 record_buf_mem
[mem_index
++] = address
+ addr_offset
;
4059 addr_offset
= addr_offset
+ (esize
/ 8);
4060 reg_tt
= (reg_tt
+ 1) % 32;
4065 if (bit (aarch64_insn_r
->aarch64_insn
, 23))
4066 record_buf
[reg_index
++] = reg_rn
;
4068 aarch64_insn_r
->reg_rec_count
= reg_index
;
4069 aarch64_insn_r
->mem_rec_count
= mem_index
/ 2;
4070 MEM_ALLOC (aarch64_insn_r
->aarch64_mems
, aarch64_insn_r
->mem_rec_count
,
4072 REG_ALLOC (aarch64_insn_r
->aarch64_regs
, aarch64_insn_r
->reg_rec_count
,
4074 return AARCH64_RECORD_SUCCESS
;
4077 /* Record handler for load and store instructions. */
4080 aarch64_record_load_store (insn_decode_record
*aarch64_insn_r
)
4082 uint8_t insn_bits24_27
, insn_bits28_29
, insn_bits10_11
;
4083 uint8_t insn_bit23
, insn_bit21
;
4084 uint8_t opc
, size_bits
, ld_flag
, vector_flag
;
4085 uint32_t reg_rn
, reg_rt
, reg_rt2
;
4086 uint64_t datasize
, offset
;
4087 uint32_t record_buf
[8];
4088 uint64_t record_buf_mem
[8];
4091 insn_bits10_11
= bits (aarch64_insn_r
->aarch64_insn
, 10, 11);
4092 insn_bits24_27
= bits (aarch64_insn_r
->aarch64_insn
, 24, 27);
4093 insn_bits28_29
= bits (aarch64_insn_r
->aarch64_insn
, 28, 29);
4094 insn_bit21
= bit (aarch64_insn_r
->aarch64_insn
, 21);
4095 insn_bit23
= bit (aarch64_insn_r
->aarch64_insn
, 23);
4096 ld_flag
= bit (aarch64_insn_r
->aarch64_insn
, 22);
4097 vector_flag
= bit (aarch64_insn_r
->aarch64_insn
, 26);
4098 reg_rt
= bits (aarch64_insn_r
->aarch64_insn
, 0, 4);
4099 reg_rn
= bits (aarch64_insn_r
->aarch64_insn
, 5, 9);
4100 reg_rt2
= bits (aarch64_insn_r
->aarch64_insn
, 10, 14);
4101 size_bits
= bits (aarch64_insn_r
->aarch64_insn
, 30, 31);
4103 /* Load/store exclusive. */
4104 if (insn_bits24_27
== 0x08 && insn_bits28_29
== 0x00)
4107 debug_printf ("Process record: load/store exclusive\n");
4111 record_buf
[0] = reg_rt
;
4112 aarch64_insn_r
->reg_rec_count
= 1;
4115 record_buf
[1] = reg_rt2
;
4116 aarch64_insn_r
->reg_rec_count
= 2;
4122 datasize
= (8 << size_bits
) * 2;
4124 datasize
= (8 << size_bits
);
4125 regcache_raw_read_unsigned (aarch64_insn_r
->regcache
, reg_rn
,
4127 record_buf_mem
[0] = datasize
/ 8;
4128 record_buf_mem
[1] = address
;
4129 aarch64_insn_r
->mem_rec_count
= 1;
4132 /* Save register rs. */
4133 record_buf
[0] = bits (aarch64_insn_r
->aarch64_insn
, 16, 20);
4134 aarch64_insn_r
->reg_rec_count
= 1;
4138 /* Load register (literal) instructions decoding. */
4139 else if ((insn_bits24_27
& 0x0b) == 0x08 && insn_bits28_29
== 0x01)
4142 debug_printf ("Process record: load register (literal)\n");
4144 record_buf
[0] = reg_rt
+ AARCH64_V0_REGNUM
;
4146 record_buf
[0] = reg_rt
;
4147 aarch64_insn_r
->reg_rec_count
= 1;
4149 /* All types of load/store pair instructions decoding. */
4150 else if ((insn_bits24_27
& 0x0a) == 0x08 && insn_bits28_29
== 0x02)
4153 debug_printf ("Process record: load/store pair\n");
4159 record_buf
[0] = reg_rt
+ AARCH64_V0_REGNUM
;
4160 record_buf
[1] = reg_rt2
+ AARCH64_V0_REGNUM
;
4164 record_buf
[0] = reg_rt
;
4165 record_buf
[1] = reg_rt2
;
4167 aarch64_insn_r
->reg_rec_count
= 2;
4172 imm7_off
= bits (aarch64_insn_r
->aarch64_insn
, 15, 21);
4174 size_bits
= size_bits
>> 1;
4175 datasize
= 8 << (2 + size_bits
);
4176 offset
= (imm7_off
& 0x40) ? (~imm7_off
& 0x007f) + 1 : imm7_off
;
4177 offset
= offset
<< (2 + size_bits
);
4178 regcache_raw_read_unsigned (aarch64_insn_r
->regcache
, reg_rn
,
4180 if (!((insn_bits24_27
& 0x0b) == 0x08 && insn_bit23
))
4182 if (imm7_off
& 0x40)
4183 address
= address
- offset
;
4185 address
= address
+ offset
;
4188 record_buf_mem
[0] = datasize
/ 8;
4189 record_buf_mem
[1] = address
;
4190 record_buf_mem
[2] = datasize
/ 8;
4191 record_buf_mem
[3] = address
+ (datasize
/ 8);
4192 aarch64_insn_r
->mem_rec_count
= 2;
4194 if (bit (aarch64_insn_r
->aarch64_insn
, 23))
4195 record_buf
[aarch64_insn_r
->reg_rec_count
++] = reg_rn
;
4197 /* Load/store register (unsigned immediate) instructions. */
4198 else if ((insn_bits24_27
& 0x0b) == 0x09 && insn_bits28_29
== 0x03)
4200 opc
= bits (aarch64_insn_r
->aarch64_insn
, 22, 23);
4210 if (size_bits
== 0x3 && vector_flag
== 0x0 && opc
== 0x2)
4212 /* PRFM (immediate) */
4213 return AARCH64_RECORD_SUCCESS
;
4215 else if (size_bits
== 0x2 && vector_flag
== 0x0 && opc
== 0x2)
4217 /* LDRSW (immediate) */
4231 debug_printf ("Process record: load/store (unsigned immediate):"
4232 " size %x V %d opc %x\n", size_bits
, vector_flag
,
4238 offset
= bits (aarch64_insn_r
->aarch64_insn
, 10, 21);
4239 datasize
= 8 << size_bits
;
4240 regcache_raw_read_unsigned (aarch64_insn_r
->regcache
, reg_rn
,
4242 offset
= offset
<< size_bits
;
4243 address
= address
+ offset
;
4245 record_buf_mem
[0] = datasize
>> 3;
4246 record_buf_mem
[1] = address
;
4247 aarch64_insn_r
->mem_rec_count
= 1;
4252 record_buf
[0] = reg_rt
+ AARCH64_V0_REGNUM
;
4254 record_buf
[0] = reg_rt
;
4255 aarch64_insn_r
->reg_rec_count
= 1;
4258 /* Load/store register (register offset) instructions. */
4259 else if ((insn_bits24_27
& 0x0b) == 0x08 && insn_bits28_29
== 0x03
4260 && insn_bits10_11
== 0x02 && insn_bit21
)
4263 debug_printf ("Process record: load/store (register offset)\n");
4264 opc
= bits (aarch64_insn_r
->aarch64_insn
, 22, 23);
4271 if (size_bits
!= 0x03)
4274 return AARCH64_RECORD_UNKNOWN
;
4278 ULONGEST reg_rm_val
;
4280 regcache_raw_read_unsigned (aarch64_insn_r
->regcache
,
4281 bits (aarch64_insn_r
->aarch64_insn
, 16, 20), ®_rm_val
);
4282 if (bit (aarch64_insn_r
->aarch64_insn
, 12))
4283 offset
= reg_rm_val
<< size_bits
;
4285 offset
= reg_rm_val
;
4286 datasize
= 8 << size_bits
;
4287 regcache_raw_read_unsigned (aarch64_insn_r
->regcache
, reg_rn
,
4289 address
= address
+ offset
;
4290 record_buf_mem
[0] = datasize
>> 3;
4291 record_buf_mem
[1] = address
;
4292 aarch64_insn_r
->mem_rec_count
= 1;
4297 record_buf
[0] = reg_rt
+ AARCH64_V0_REGNUM
;
4299 record_buf
[0] = reg_rt
;
4300 aarch64_insn_r
->reg_rec_count
= 1;
4303 /* Load/store register (immediate and unprivileged) instructions. */
4304 else if ((insn_bits24_27
& 0x0b) == 0x08 && insn_bits28_29
== 0x03
4309 debug_printf ("Process record: load/store "
4310 "(immediate and unprivileged)\n");
4312 opc
= bits (aarch64_insn_r
->aarch64_insn
, 22, 23);
4319 if (size_bits
!= 0x03)
4322 return AARCH64_RECORD_UNKNOWN
;
4327 imm9_off
= bits (aarch64_insn_r
->aarch64_insn
, 12, 20);
4328 offset
= (imm9_off
& 0x0100) ? (((~imm9_off
) & 0x01ff) + 1) : imm9_off
;
4329 datasize
= 8 << size_bits
;
4330 regcache_raw_read_unsigned (aarch64_insn_r
->regcache
, reg_rn
,
4332 if (insn_bits10_11
!= 0x01)
4334 if (imm9_off
& 0x0100)
4335 address
= address
- offset
;
4337 address
= address
+ offset
;
4339 record_buf_mem
[0] = datasize
>> 3;
4340 record_buf_mem
[1] = address
;
4341 aarch64_insn_r
->mem_rec_count
= 1;
4346 record_buf
[0] = reg_rt
+ AARCH64_V0_REGNUM
;
4348 record_buf
[0] = reg_rt
;
4349 aarch64_insn_r
->reg_rec_count
= 1;
4351 if (insn_bits10_11
== 0x01 || insn_bits10_11
== 0x03)
4352 record_buf
[aarch64_insn_r
->reg_rec_count
++] = reg_rn
;
4354 /* Advanced SIMD load/store instructions. */
4356 return aarch64_record_asimd_load_store (aarch64_insn_r
);
4358 MEM_ALLOC (aarch64_insn_r
->aarch64_mems
, aarch64_insn_r
->mem_rec_count
,
4360 REG_ALLOC (aarch64_insn_r
->aarch64_regs
, aarch64_insn_r
->reg_rec_count
,
4362 return AARCH64_RECORD_SUCCESS
;
4365 /* Record handler for data processing SIMD and floating point instructions. */
4368 aarch64_record_data_proc_simd_fp (insn_decode_record
*aarch64_insn_r
)
4370 uint8_t insn_bit21
, opcode
, rmode
, reg_rd
;
4371 uint8_t insn_bits24_27
, insn_bits28_31
, insn_bits10_11
, insn_bits12_15
;
4372 uint8_t insn_bits11_14
;
4373 uint32_t record_buf
[2];
4375 insn_bits24_27
= bits (aarch64_insn_r
->aarch64_insn
, 24, 27);
4376 insn_bits28_31
= bits (aarch64_insn_r
->aarch64_insn
, 28, 31);
4377 insn_bits10_11
= bits (aarch64_insn_r
->aarch64_insn
, 10, 11);
4378 insn_bits12_15
= bits (aarch64_insn_r
->aarch64_insn
, 12, 15);
4379 insn_bits11_14
= bits (aarch64_insn_r
->aarch64_insn
, 11, 14);
4380 opcode
= bits (aarch64_insn_r
->aarch64_insn
, 16, 18);
4381 rmode
= bits (aarch64_insn_r
->aarch64_insn
, 19, 20);
4382 reg_rd
= bits (aarch64_insn_r
->aarch64_insn
, 0, 4);
4383 insn_bit21
= bit (aarch64_insn_r
->aarch64_insn
, 21);
4386 debug_printf ("Process record: data processing SIMD/FP: ");
4388 if ((insn_bits28_31
& 0x05) == 0x01 && insn_bits24_27
== 0x0e)
4390 /* Floating point - fixed point conversion instructions. */
4394 debug_printf ("FP - fixed point conversion");
4396 if ((opcode
>> 1) == 0x0 && rmode
== 0x03)
4397 record_buf
[0] = reg_rd
;
4399 record_buf
[0] = reg_rd
+ AARCH64_V0_REGNUM
;
4401 /* Floating point - conditional compare instructions. */
4402 else if (insn_bits10_11
== 0x01)
4405 debug_printf ("FP - conditional compare");
4407 record_buf
[0] = AARCH64_CPSR_REGNUM
;
4409 /* Floating point - data processing (2-source) and
4410 conditional select instructions. */
4411 else if (insn_bits10_11
== 0x02 || insn_bits10_11
== 0x03)
4414 debug_printf ("FP - DP (2-source)");
4416 record_buf
[0] = reg_rd
+ AARCH64_V0_REGNUM
;
4418 else if (insn_bits10_11
== 0x00)
4420 /* Floating point - immediate instructions. */
4421 if ((insn_bits12_15
& 0x01) == 0x01
4422 || (insn_bits12_15
& 0x07) == 0x04)
4425 debug_printf ("FP - immediate");
4426 record_buf
[0] = reg_rd
+ AARCH64_V0_REGNUM
;
4428 /* Floating point - compare instructions. */
4429 else if ((insn_bits12_15
& 0x03) == 0x02)
4432 debug_printf ("FP - immediate");
4433 record_buf
[0] = AARCH64_CPSR_REGNUM
;
4435 /* Floating point - integer conversions instructions. */
4436 else if (insn_bits12_15
== 0x00)
4438 /* Convert float to integer instruction. */
4439 if (!(opcode
>> 1) || ((opcode
>> 1) == 0x02 && !rmode
))
4442 debug_printf ("float to int conversion");
4444 record_buf
[0] = reg_rd
+ AARCH64_X0_REGNUM
;
4446 /* Convert integer to float instruction. */
4447 else if ((opcode
>> 1) == 0x01 && !rmode
)
4450 debug_printf ("int to float conversion");
4452 record_buf
[0] = reg_rd
+ AARCH64_V0_REGNUM
;
4454 /* Move float to integer instruction. */
4455 else if ((opcode
>> 1) == 0x03)
4458 debug_printf ("move float to int");
4460 if (!(opcode
& 0x01))
4461 record_buf
[0] = reg_rd
+ AARCH64_X0_REGNUM
;
4463 record_buf
[0] = reg_rd
+ AARCH64_V0_REGNUM
;
4466 return AARCH64_RECORD_UNKNOWN
;
4469 return AARCH64_RECORD_UNKNOWN
;
4472 return AARCH64_RECORD_UNKNOWN
;
4474 else if ((insn_bits28_31
& 0x09) == 0x00 && insn_bits24_27
== 0x0e)
4477 debug_printf ("SIMD copy");
4479 /* Advanced SIMD copy instructions. */
4480 if (!bits (aarch64_insn_r
->aarch64_insn
, 21, 23)
4481 && !bit (aarch64_insn_r
->aarch64_insn
, 15)
4482 && bit (aarch64_insn_r
->aarch64_insn
, 10))
4484 if (insn_bits11_14
== 0x05 || insn_bits11_14
== 0x07)
4485 record_buf
[0] = reg_rd
+ AARCH64_X0_REGNUM
;
4487 record_buf
[0] = reg_rd
+ AARCH64_V0_REGNUM
;
4490 record_buf
[0] = reg_rd
+ AARCH64_V0_REGNUM
;
4492 /* All remaining floating point or advanced SIMD instructions. */
4496 debug_printf ("all remain");
4498 record_buf
[0] = reg_rd
+ AARCH64_V0_REGNUM
;
4502 debug_printf ("\n");
4504 /* Record the V/X register. */
4505 aarch64_insn_r
->reg_rec_count
++;
4507 /* Some of these instructions may set bits in the FPSR, so record it
4509 record_buf
[1] = AARCH64_FPSR_REGNUM
;
4510 aarch64_insn_r
->reg_rec_count
++;
4512 gdb_assert (aarch64_insn_r
->reg_rec_count
== 2);
4513 REG_ALLOC (aarch64_insn_r
->aarch64_regs
, aarch64_insn_r
->reg_rec_count
,
4515 return AARCH64_RECORD_SUCCESS
;
4518 /* Decodes insns type and invokes its record handler. */
4521 aarch64_record_decode_insn_handler (insn_decode_record
*aarch64_insn_r
)
4523 uint32_t ins_bit25
, ins_bit26
, ins_bit27
, ins_bit28
;
4525 ins_bit25
= bit (aarch64_insn_r
->aarch64_insn
, 25);
4526 ins_bit26
= bit (aarch64_insn_r
->aarch64_insn
, 26);
4527 ins_bit27
= bit (aarch64_insn_r
->aarch64_insn
, 27);
4528 ins_bit28
= bit (aarch64_insn_r
->aarch64_insn
, 28);
4530 /* Data processing - immediate instructions. */
4531 if (!ins_bit26
&& !ins_bit27
&& ins_bit28
)
4532 return aarch64_record_data_proc_imm (aarch64_insn_r
);
4534 /* Branch, exception generation and system instructions. */
4535 if (ins_bit26
&& !ins_bit27
&& ins_bit28
)
4536 return aarch64_record_branch_except_sys (aarch64_insn_r
);
4538 /* Load and store instructions. */
4539 if (!ins_bit25
&& ins_bit27
)
4540 return aarch64_record_load_store (aarch64_insn_r
);
4542 /* Data processing - register instructions. */
4543 if (ins_bit25
&& !ins_bit26
&& ins_bit27
)
4544 return aarch64_record_data_proc_reg (aarch64_insn_r
);
4546 /* Data processing - SIMD and floating point instructions. */
4547 if (ins_bit25
&& ins_bit26
&& ins_bit27
)
4548 return aarch64_record_data_proc_simd_fp (aarch64_insn_r
);
4550 return AARCH64_RECORD_UNSUPPORTED
;
4553 /* Cleans up local record registers and memory allocations. */
4556 deallocate_reg_mem (insn_decode_record
*record
)
4558 xfree (record
->aarch64_regs
);
4559 xfree (record
->aarch64_mems
);
4563 namespace selftests
{
4566 aarch64_process_record_test (void)
4568 struct gdbarch_info info
;
4571 info
.bfd_arch_info
= bfd_scan_arch ("aarch64");
4573 struct gdbarch
*gdbarch
= gdbarch_find_by_info (info
);
4574 SELF_CHECK (gdbarch
!= NULL
);
4576 insn_decode_record aarch64_record
;
4578 memset (&aarch64_record
, 0, sizeof (insn_decode_record
));
4579 aarch64_record
.regcache
= NULL
;
4580 aarch64_record
.this_addr
= 0;
4581 aarch64_record
.gdbarch
= gdbarch
;
4583 /* 20 00 80 f9 prfm pldl1keep, [x1] */
4584 aarch64_record
.aarch64_insn
= 0xf9800020;
4585 ret
= aarch64_record_decode_insn_handler (&aarch64_record
);
4586 SELF_CHECK (ret
== AARCH64_RECORD_SUCCESS
);
4587 SELF_CHECK (aarch64_record
.reg_rec_count
== 0);
4588 SELF_CHECK (aarch64_record
.mem_rec_count
== 0);
4590 deallocate_reg_mem (&aarch64_record
);
4593 } // namespace selftests
4594 #endif /* GDB_SELF_TEST */
4596 /* Parse the current instruction and record the values of the registers and
4597 memory that will be changed in current instruction to record_arch_list
4598 return -1 if something is wrong. */
4601 aarch64_process_record (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
4602 CORE_ADDR insn_addr
)
4604 uint32_t rec_no
= 0;
4605 uint8_t insn_size
= 4;
4607 gdb_byte buf
[insn_size
];
4608 insn_decode_record aarch64_record
;
4610 memset (&buf
[0], 0, insn_size
);
4611 memset (&aarch64_record
, 0, sizeof (insn_decode_record
));
4612 target_read_memory (insn_addr
, &buf
[0], insn_size
);
4613 aarch64_record
.aarch64_insn
4614 = (uint32_t) extract_unsigned_integer (&buf
[0],
4616 gdbarch_byte_order (gdbarch
));
4617 aarch64_record
.regcache
= regcache
;
4618 aarch64_record
.this_addr
= insn_addr
;
4619 aarch64_record
.gdbarch
= gdbarch
;
4621 ret
= aarch64_record_decode_insn_handler (&aarch64_record
);
4622 if (ret
== AARCH64_RECORD_UNSUPPORTED
)
4624 printf_unfiltered (_("Process record does not support instruction "
4625 "0x%0x at address %s.\n"),
4626 aarch64_record
.aarch64_insn
,
4627 paddress (gdbarch
, insn_addr
));
4633 /* Record registers. */
4634 record_full_arch_list_add_reg (aarch64_record
.regcache
,
4636 /* Always record register CPSR. */
4637 record_full_arch_list_add_reg (aarch64_record
.regcache
,
4638 AARCH64_CPSR_REGNUM
);
4639 if (aarch64_record
.aarch64_regs
)
4640 for (rec_no
= 0; rec_no
< aarch64_record
.reg_rec_count
; rec_no
++)
4641 if (record_full_arch_list_add_reg (aarch64_record
.regcache
,
4642 aarch64_record
.aarch64_regs
[rec_no
]))
4645 /* Record memories. */
4646 if (aarch64_record
.aarch64_mems
)
4647 for (rec_no
= 0; rec_no
< aarch64_record
.mem_rec_count
; rec_no
++)
4648 if (record_full_arch_list_add_mem
4649 ((CORE_ADDR
)aarch64_record
.aarch64_mems
[rec_no
].addr
,
4650 aarch64_record
.aarch64_mems
[rec_no
].len
))
4653 if (record_full_arch_list_add_end ())
4657 deallocate_reg_mem (&aarch64_record
);